STM32L4x6 Advanced ARM® Based 32 Bit MCUs STM32L476VGT6 Reference Manual
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RM0351 Reference manual STM32L4x6 advanced ARM®-based 32-bit MCUs Introduction This reference manual targets application developers. It provides complete information on how to use the STM32L4x6 microcontroller memory and peripherals. The STM32L4x6 is a family of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics please refer to the corresponding datasheets. For information on the ARM® Cortex®-M4 core, please refer to the Cortex®-M4 Technical Reference Manual. Related documents • Cortex®-M4 Technical Reference Manual, available from: http://infocenter.arm.com • STM32L476xx and STM32L486xx datasheet • Cortex®-M4 programming manual (PM0214) May 2015 DocID024597 Rev 1 1/1680 www.st.com 1 Contents RM0351 Contents 1 2 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.1 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.3 Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.1 2.2 2.3 3 2/1680 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.1.1 S0: I-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.1.2 S1: D-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.1.3 S2: S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.1.4 S3, S4: DMA-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.1.5 BusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.2.2 Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 68 2.2.3 Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.3.1 SRAM2 Parity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.3.2 SRAM2 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.3.3 SRAM2 Read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.3.4 SRAM2 Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.4 Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.5 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Embedded Flash memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.2 FLASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.3 FLASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.3.1 Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.3.2 Error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.3.3 Read access latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.3.4 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 83 3.3.5 Flash program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 DocID024597 Rev 1 RM0351 Contents 3.4 3.5 4 3.3.6 Flash main memory erase sequences . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.3.7 Flash main memory programming sequences . . . . . . . . . . . . . . . . . . . . 87 3.3.8 Read-while-write (RWW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 FLASH option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.4.1 Option bytes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.4.2 Option bytes programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 FLASH memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.5.1 Read protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.5.2 Proprietary code readout protection (PCROP) . . . . . . . . . . . . . . . . . . 103 3.5.3 Write protection (WRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 3.6 FLASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 3.7 FLASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.7.1 Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . 106 3.7.2 Flash Power-down key register (FLASH_PDKEYR) . . . . . . . . . . . . . . 107 3.7.3 Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.7.4 Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . 108 3.7.5 Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.7.6 Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 3.7.7 Flash ECC register (FLASH_ECCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 112 3.7.8 Flash option register (FLASH_OPTR) . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.7.9 Flash Bank 1 PCROP Start address register (FLASH_PCROP1SR) . 114 3.7.10 Flash Bank 1 PCROP End address register (FLASH_PCROP1ER) . . 115 3.7.11 Flash Bank 1 WRP area A address register (FLASH_WRP1AR) . . . . 115 3.7.12 Flash Bank 1 WRP area B address register (FLASH_WRP1BR) . . . . 116 3.7.13 Flash Bank 2 PCROP Start address register (FLASH_PCROP2SR) . 116 3.7.14 Flash Bank 2 PCROP End address register (FLASH_PCROP2ER) . . 117 3.7.15 Flash Bank 2 WRP area A address register (FLASH_WRP2AR) . . . . 117 3.7.16 Flash Bank 2 WRP area B address register (FLASH_WRP2BR) . . . . 118 3.7.17 FLASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Firewall (FW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.2 Firewall main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.3 Firewall functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.3.1 Firewall AMBA bus snoop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.3.2 Functional requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 DocID024597 Rev 1 3/1680 43 Contents RM0351 4.4 5 6 Firewall segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.3.4 Segment accesses and properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.3.5 Firewall initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.3.6 Firewall states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Firewall registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.4.1 Code segment start address (FW_CSSA) . . . . . . . . . . . . . . . . . . . . . . 128 4.4.2 Code segment length (FW_CSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.4.3 Non-volatile data segment start address (FW_NVDSSA) . . . . . . . . . . 129 4.4.4 Non-volatile data segment length (FW_NVDSL) . . . . . . . . . . . . . . . . . 129 4.4.5 Volatile data segment start address (FW_VDSSA) . . . . . . . . . . . . . . . 130 4.4.6 Volatile data segment length (FW_VDSL) . . . . . . . . . . . . . . . . . . . . . . 130 4.4.7 Configuration register (FW_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.4.8 Firewall register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . 133 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.4 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.4.1 Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.4.2 Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . 136 5.4.3 Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.4.4 Initial CRC value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5.4.5 CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5.4.6 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.1 6.2 4/1680 4.3.3 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.1.1 Independent analog peripherals supply . . . . . . . . . . . . . . . . . . . . . . . . 140 6.1.2 Independent I/O supply rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.1.3 Independent USB transceivers supply . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.1.4 Independent LCD supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.1.5 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.1.6 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.1.7 Dynamic voltage scaling management . . . . . . . . . . . . . . . . . . . . . . . . 144 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 DocID024597 Rev 1 RM0351 Contents 6.3 6.4 6.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6.2.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 145 6.2.3 Peripheral Voltage Monitoring (PVM) . . . . . . . . . . . . . . . . . . . . . . . . . 146 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.3.1 Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 6.3.2 Low-power run mode (LP run) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 6.3.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 6.3.4 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 6.3.5 Low-power sleep mode (LP sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 6.3.6 Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6.3.7 Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6.3.8 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 6.3.9 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6.3.10 Auto-wakeup from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . 165 PWR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6.4.1 Power control register 1 (PWR_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 166 6.4.2 Power control register 2 (PWR_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.4.3 Power control register 3 (PWR_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.4.4 Power control register 4 (PWR_CR4) . . . . . . . . . . . . . . . . . . . . . . . . . 169 6.4.5 Power status register 1 (PWR_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 170 6.4.6 Power status register 2 (PWR_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 171 6.4.7 Power status clear register (PWR_SCR) . . . . . . . . . . . . . . . . . . . . . . . 173 6.4.8 Power Port A pull-up control register (PWR_PUCRA) . . . . . . . . . . . . . 173 6.4.9 Power Port A pull-down control register (PWR_PDCRA) . . . . . . . . . . 174 6.4.10 Power Port B pull-up control register (PWR_PUCRB) . . . . . . . . . . . . . 174 6.4.11 Power Port B pull-down control register (PWR_PDCRB) . . . . . . . . . . 175 6.4.12 Power Port C pull-up control register (PWR_PUCRC) . . . . . . . . . . . . 175 6.4.13 Power Port C pull-down control register (PWR_PDCRC) . . . . . . . . . . 176 6.4.14 Power Port D pull-up control register (PWR_PUCRD) . . . . . . . . . . . . 176 6.4.15 Power Port D pull-down control register (PWR_PDCRD) . . . . . . . . . . 177 6.4.16 Power Port E pull-up control register (PWR_PUCRE) . . . . . . . . . . . . . 177 6.4.17 Power Port E pull-down control register (PWR_PDCRE) . . . . . . . . . . 178 6.4.18 Power Port F pull-up control register (PWR_PUCRF) . . . . . . . . . . . . . 178 6.4.19 Power Port F pull-down control register (PWR_PDCRF) . . . . . . . . . . 178 6.4.20 Power Port G pull-up control register (PWR_PUCRG) . . . . . . . . . . . . 179 6.4.21 Power Port G pull-down control register (PWR_PDCRG) . . . . . . . . . . 179 DocID024597 Rev 1 5/1680 43 Contents 7 8 RM0351 6.4.22 Power Port H pull-up control register (PWR_PUCRH) . . . . . . . . . . . . 180 6.4.23 Power Port H pull-down control register (PWR_PDCRH) . . . . . . . . . . 180 6.4.24 PWR register map and reset value table . . . . . . . . . . . . . . . . . . . . . . . 182 Peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 7.2 Connection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 7.3 Interconnection details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 7.3.1 From timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15/TIM16/TIM17) to timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15) . . . . . . . . . . . . . . . . 185 7.3.2 From timer (TIM1/TIM2/TIM3/TIM4/TIM6/TIM8/TIM15) and EXTI to ADC (ADC1/ADC2/ADC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 7.3.3 From ADC (ADC1/ADC2/ADC3) to timer (TIM1/TIM8) . . . . . . . . . . . . 187 7.3.4 From timer (TIM2/TIM4/TIM5/TIM6/TIM7/TIM8) and EXTI to DAC (DAC1/DAC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 7.3.5 From timer (TIM1/TIM3/TIM4/TIM6/TIM7/TIM8/TIM16) and EXTI to DFSDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 7.3.6 From DFSDM to timer (TIM1/TIM8/TIM15/TIM16/TIM17) . . . . . . . . . . 188 7.3.7 From HSE, LSE, LSI, MSI, MCO, RTC to timer (TIM2/TIM15/TIM16/TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 7.3.8 From RTC, COMP1, COMP2 to low-power timer (LPTIM1/LPTIM2) . . 189 7.3.9 From timer (TIM1/TIM2/TIM3/TIM8/TIM15) to comparators (COMP1/COMP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 7.3.10 From ADC (ADC1) to ADC (ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 7.3.11 From USB to timer (TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 7.3.12 From internal analog source to ADC (ADC1/ADC2/ADC3) and OPAMP (OPAMP1/OPAM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 7.3.13 From comparators (COMP1/COMP2) to timers (TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17) . . . . . . . . . . . . . . . . . . . 191 7.3.14 From system errors to timers (TIM1/TIM8/TIM15/TIM16/TIM17) . . . . 191 7.3.15 From timers (TIM16/TIM17) to IRTIM . . . . . . . . . . . . . . . . . . . . . . . . . 192 Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 8.1 8.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 8.1.1 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 8.1.2 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 8.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 8.2.1 6/1680 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 DocID024597 Rev 1 RM0351 Contents 8.2.2 HSI16 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 8.2.3 MSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 8.2.4 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 8.2.5 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 8.2.6 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 8.2.7 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 8.2.8 Clock source frequency versus voltage scaling . . . . . . . . . . . . . . . . . . 203 8.2.9 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 8.2.10 Clock security system on LSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 8.2.11 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 8.2.12 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 8.2.13 Timer clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 8.2.14 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 8.2.15 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 8.2.16 Internal/external clock measurement with TIM15/TIM16/TIM17 . . . . . 206 8.2.17 Peripheral clock enable register (RCC_AHBxENR, RCC_APBxENRy) . . . . . . . . . . . . . . . . . . . . . . . . . 209 8.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 8.4 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 8.4.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 8.4.2 Internal clock sources calibration register (RCC_ICSCR) . . . . . . . . . . 213 8.4.3 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 214 8.4.4 PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . . . . . 217 8.4.5 PLLSAI1 configuration register (RCC_PLLSAI1CFGR) . . . . . . . . . . . 220 8.4.6 PLLSAI2 configuration register (RCC_PLLSAI2CFGR) . . . . . . . . . . . 223 8.4.7 Clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . . . . . 225 8.4.8 Clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . . . . . 227 8.4.9 Clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . . . . . 229 8.4.10 AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . . . . . 230 8.4.11 AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . . . . . 231 8.4.12 AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . . . . . 232 8.4.13 APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . . . . . . . . . 234 8.4.14 APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . . . . . . . . . 236 8.4.15 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 237 8.4.16 AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . . . . . 238 8.4.17 AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . . . . . 239 8.4.18 AHB3 peripheral clock enable register(RCC_AHB3ENR) . . . . . . . . . . 241 DocID024597 Rev 1 7/1680 43 Contents 9 8/1680 RM0351 8.4.19 APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . . . . 241 8.4.20 APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . . . . 244 8.4.21 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 246 8.4.22 AHB1 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 8.4.23 AHB2 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 8.4.24 AHB3 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB3SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 8.4.25 APB1 peripheral clocks enable in Sleep and Stop modes register 1 (RCC_APB1SMENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 8.4.26 APB1 peripheral clocks enable in Sleep and Stop modes register 2 (RCC_APB1SMENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 8.4.27 APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 8.4.28 Peripherals independent clock configuration register (RCC_CCIPR) . 257 8.4.29 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 260 8.4.30 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 8.4.31 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 9.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 9.3 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 9.3.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 9.3.2 I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 271 9.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 9.3.4 I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 9.3.5 I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 9.3.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 9.3.7 I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 9.3.8 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 9.3.9 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 9.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 9.3.11 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 9.3.12 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 9.3.13 Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 277 9.3.14 Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 277 DocID024597 Rev 1 RM0351 Contents 9.4 10 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 9.4.1 GPIO port mode register (GPIOx_MODER) (x =A..H) . . . . . . . . . . . . . 278 9.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..H) . . . . . . . 278 9.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 9.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 9.4.5 GPIO port input data register (GPIOx_IDR) (x = A..H) . . . . . . . . . . . . 280 9.4.6 GPIO port output data register (GPIOx_ODR) (x = A..H) . . . . . . . . . . 280 9.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..H) . . . . . . . . . 280 9.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 9.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 9.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 9.4.11 GPIO port bit reset register (GPIOx_BRR) (x =A..H) . . . . . . . . . . . . . . 283 9.4.12 GPIO port analog switch control register (GPIOx_ASCR)(x = A..H) . . 283 9.4.13 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 287 10.1 SYSCFG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 10.2 SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 10.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . . . . . . . 287 10.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . . . . . . . . 288 10.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 10.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 10.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 10.2.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR) . . . . 296 10.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . . . . . . . . 297 10.2.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR) . . . . . . 297 10.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR) . . . . . . . . . . . . . . . . . 298 10.2.11 SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 300 DocID024597 Rev 1 9/1680 43 Contents RM0351 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 11.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 11.3 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 11.4 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 11.5 12 13 10/1680 11.4.1 DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 11.4.2 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 11.4.3 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 11.4.4 Programmable data width, data alignment and endians . . . . . . . . . . . 304 11.4.5 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 11.4.6 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 11.4.7 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 11.5.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 312 11.5.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 313 11.5.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7 , where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . 314 11.5.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 11.5.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 11.5.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 11.5.7 DMA1 channel selection register (DMA1_CSELR) . . . . . . . . . . . . . . . 318 11.5.8 DMA2 channel selection register (DMA2_CSELR) . . . . . . . . . . . . . . . 320 11.5.9 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . 324 12.1 NVIC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 12.2 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 12.3 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . 329 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 13.2 EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 13.3 EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 13.3.1 EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 13.3.2 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 DocID024597 Rev 1 RM0351 Contents 13.3.3 Peripherals asynchronous Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 331 13.3.4 Hardware interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 13.3.5 Hardware event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 13.3.6 Software interrupt/event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 13.4 EXTI interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 13.5 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 13.5.1 Interrupt mask register 1 (EXTI_IMR1) . . . . . . . . . . . . . . . . . . . . . . . . 334 13.5.2 Event mask register 1 (EXTI_EMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 334 13.5.3 Rising trigger selection register 1 (EXTI_RTSR1) . . . . . . . . . . . . . . . . 335 13.5.4 Falling trigger selection register 1 (EXTI_FTSR1) . . . . . . . . . . . . . . . . 335 13.5.5 Software interrupt event register 1 (EXTI_SWIER1) . . . . . . . . . . . . . . 336 13.5.6 Pending register 1 (EXTI_PR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 13.5.7 Interrupt mask register 2 (EXTI_IMR2) . . . . . . . . . . . . . . . . . . . . . . . . 337 13.5.8 Event mask register 2 (EXTI_EMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 338 13.5.9 Rising trigger selection register 2 (EXTI_RTSR2) . . . . . . . . . . . . . . . . 338 13.5.10 Falling trigger selection register 2 (EXTI_FTSR2) . . . . . . . . . . . . . . . . 339 13.5.11 Software interrupt event register 2 (EXTI_SWIER2) . . . . . . . . . . . . . . 339 13.5.12 Pending register 2 (EXTI_PR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 13.5.13 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 14 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . 342 14.1 FMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 14.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 14.3 AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 14.3.1 14.4 14.5 14.6 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 344 External device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 14.4.1 NOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 14.4.2 NAND Flash memory address mapping . . . . . . . . . . . . . . . . . . . . . . . 346 NOR Flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 14.5.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 14.5.2 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 350 14.5.3 General timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 14.5.4 NOR Flash/PSRAM controller asynchronous transactions . . . . . . . . . 352 14.5.5 Synchronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 14.5.6 NOR/PSRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 NAND Flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 DocID024597 Rev 1 11/1680 43 Contents RM0351 14.7 15 14.6.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 14.6.2 NAND Flash supported memories and transactions . . . . . . . . . . . . . . 385 14.6.3 Timing diagrams for NAND Flash memory . . . . . . . . . . . . . . . . . . . . . 385 14.6.4 NAND Flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 14.6.5 NAND Flash prewait functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 14.6.6 Computation of the error correction code (ECC) in NAND Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 14.6.7 NAND Flashcontroller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 FMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 QuadSPI interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 15.2 QUADSPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 15.3 QUADSPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 15.3.1 QUADSPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 15.3.2 QUADSPI Command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 15.3.3 QUADSPI signal interface protocol modes . . . . . . . . . . . . . . . . . . . . . 400 15.3.4 QUADSPI indirect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 15.3.5 QUADSPI status flag polling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 15.3.6 QUADSPI memory-mapped mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 15.3.7 QUADSPI Flash memory configuration . . . . . . . . . . . . . . . . . . . . . . . . 404 15.3.8 QUADSPI delayed data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 15.3.9 QUADSPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 15.3.10 QUADSPI usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 15.3.11 Sending the instruction only once . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 15.3.12 QUADSPI error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 15.3.13 QUADSPI busy bit and abort functionality . . . . . . . . . . . . . . . . . . . . . . 408 15.3.14 nCS behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 12/1680 15.4 QUADSPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 15.5 QUADSPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411 15.5.1 QUADSPI control register (QUADSPI_CR) . . . . . . . . . . . . . . . . . . . . . 411 15.5.2 QUADSPI device configuration register (QUADSPI_DCR) . . . . . . . . . 413 15.5.3 QUADSPI status register (QUADSPI_SR) . . . . . . . . . . . . . . . . . . . . . 414 15.5.4 QUADSPI flag clear register (QUADSPI_FCR) . . . . . . . . . . . . . . . . . . 415 15.5.5 QUADSPI data length register (QUADSPI_DLR) . . . . . . . . . . . . . . . . 416 15.5.6 QUADSPI communication configuration register (QUADSPI_CCR) . . 416 15.5.7 QUADSPI address register (QUADSPI_AR) . . . . . . . . . . . . . . . . . . . . 418 DocID024597 Rev 1 RM0351 Contents 15.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR) . . . . . . . . . . . . 418 15.5.9 QUADSPI data register (QUADSPI_DR) . . . . . . . . . . . . . . . . . . . . . . . 419 15.5.10 QUADSPI polling status mask register (QUADSPI _PSMKR) . . . . . . . 419 15.5.11 QUADSPI polling status match register (QUADSPI _PSMAR) . . . . . . 420 15.5.12 QUADSPI polling interval register (QUADSPI _PIR) . . . . . . . . . . . . . . 420 15.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR) . . . . . . . . . . 421 15.5.14 QUADSPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 16 Analog-to-digital converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 16.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 16.3 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 16.3.1 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 16.3.2 Pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 16.3.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 16.3.4 ADC1/2/3 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 16.3.5 Slave AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 16.3.6 ADC Deep-Power-Down Mode (DEEPPWD) & ADC Voltage Regulator (ADVREGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 16.3.7 Single-ended and differential input channels . . . . . . . . . . . . . . . . . . . . 433 16.3.8 Calibration (ADCAL, ADCALDIF, ADCx_CALFACT) . . . . . . . . . . . . . . 434 16.3.9 ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . 437 16.3.10 Constraints when writing the ADC control bits . . . . . . . . . . . . . . . . . . . 438 16.3.11 Channel selection (SQRx, JSQRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 16.3.12 Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . . 439 16.3.13 Single conversion mode (CONT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 16.3.14 Continuous conversion mode (CONT=1) . . . . . . . . . . . . . . . . . . . . . . . 440 16.3.15 Starting conversions (ADSTART, JADSTART) . . . . . . . . . . . . . . . . . . . 441 16.3.16 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 16.3.17 Stopping an ongoing conversion (ADSTP, JADSTP) . . . . . . . . . . . . . . 442 16.3.18 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 16.3.19 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 16.3.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . . . . . . . . . 449 16.3.21 Queue of context for injected conversions . . . . . . . . . . . . . . . . . . . . . . 450 16.3.22 Programmable resolution (RES) - fast conversion mode . . . . . . . . . . 457 16.3.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . 457 DocID024597 Rev 1 13/1680 43 Contents RM0351 16.3.24 End of conversion sequence (EOS, JEOS) . . . . . . . . . . . . . . . . . . . . . 457 16.3.25 Timing diagrams example (single/continuous modes, hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 16.3.26 Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 16.3.27 Dynamic low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 16.3.28 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . 470 16.3.29 Oversampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 16.3.30 Dual ADC modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 16.3.31 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 16.3.32 VBAT supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 16.3.33 Monitoring the internal voltage reference . . . . . . . . . . . . . . . . . . . . . . 497 16.4 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 16.5 ADC registers (for each ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 16.5.1 ADC interrupt and status register (ADCx_ISR) . . . . . . . . . . . . . . . . . . 499 16.5.2 ADC interrupt enable register (ADCx_IER) . . . . . . . . . . . . . . . . . . . . . 501 16.5.3 ADC control register (ADCx_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 16.5.4 ADC configuration register (ADCx_CFGR) . . . . . . . . . . . . . . . . . . . . . 506 16.5.5 ADC configuration register 2 (ADCx_CFGR2) . . . . . . . . . . . . . . . . . . . 510 16.5.6 ADC sample time register 1 (ADCx_SMPR1) . . . . . . . . . . . . . . . . . . . 511 16.5.7 ADC sample time register 2 (ADCx_SMPR2) . . . . . . . . . . . . . . . . . . . 513 16.5.8 ADC watchdog threshold register 1 (ADCx_TR1) . . . . . . . . . . . . . . . . 513 16.5.9 ADC watchdog threshold register 2 (ADCx_TR2) . . . . . . . . . . . . . . . . 514 16.5.10 ADC watchdog threshold register 3 (ADCx_TR3) . . . . . . . . . . . . . . . . 515 16.5.11 ADC regular sequence register 1 (ADCx_SQR1) . . . . . . . . . . . . . . . . 516 16.5.12 ADC regular sequence register 2 (ADCx_SQR2) . . . . . . . . . . . . . . . . 517 16.5.13 ADC regular sequence register 3 (ADCx_SQR3) . . . . . . . . . . . . . . . . 518 16.5.14 ADC regular sequence register 4 (ADCx_SQR4) . . . . . . . . . . . . . . . . 519 16.5.15 ADC regular Data Register (ADCx_DR) . . . . . . . . . . . . . . . . . . . . . . . 520 16.5.16 ADC injected sequence register (ADCx_JSQR) . . . . . . . . . . . . . . . . . 521 16.5.17 ADC offset register (ADCx_OFRy) (y=1..4) . . . . . . . . . . . . . . . . . . . . . 523 16.5.18 ADC injected data register (ADCx_JDRy, y= 1..4) . . . . . . . . . . . . . . . . 524 16.5.19 ADC Analog Watchdog 2 Configuration Register (ADCx_AWD2CR) . 524 16.5.20 ADC Analog Watchdog 3 Configuration Register (ADCx_AWD3CR) . 525 16.5.21 ADC Differential Mode Selection Register (ADCx_DIFSEL) . . . . . . . . 525 16.5.22 ADC Calibration Factors (ADCx_CALFACT) . . . . . . . . . . . . . . . . . . . . 526 16.6 14/1680 ADC common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 DocID024597 Rev 1 RM0351 17 Contents 16.6.1 ADC Common status register (ADCx_CSR) . . . . . . . . . . . . . . . . . . . . 528 16.6.2 ADC common control register (ADCx_CCR) . . . . . . . . . . . . . . . . . . . . 530 16.6.3 ADC common regular data register for dual mode (ADCx_CDR) . . . . 533 16.6.4 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 17.2 DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 17.3 DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 17.3.1 DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 17.3.2 DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 17.3.3 DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 17.3.4 DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 17.3.5 DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 17.3.6 DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 17.3.7 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 17.3.8 Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 17.3.9 Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 17.3.10 DAC channel modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 17.3.11 DAC channel buffer calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 17.3.12 Dual DAC channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 17.3.13 Simultaneous trigger with different triangle generation . . . . . . . . . . . . 552 17.4 DAC low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 17.5 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 17.5.1 DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 17.5.2 DAC software trigger register (DAC_SWTRGR) . . . . . . . . . . . . . . . . . 556 17.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 17.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 17.5.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 17.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 17.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 17.5.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 DocID024597 Rev 1 15/1680 43 Contents RM0351 17.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 17.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 17.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 17.5.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 560 17.5.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 560 17.5.14 DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 17.5.15 DAC calibration control register (DAC_CCR) . . . . . . . . . . . . . . . . . . . 562 17.5.16 DAC mode control register (DAC_MCR) . . . . . . . . . . . . . . . . . . . . . . . 562 17.5.17 DAC Sample and Hold sample time register 1 (DAC_SHSR1) . . . . . . 563 17.5.18 DAC Sample and Hold sample time register 2 (DAC_SHSR2) . . . . . . 564 17.5.19 DAC Sample and Hold hold time register (DAC_SHHR) . . . . . . . . . . . 564 17.5.20 DAC Sample and Hold refresh time register (DAC_SHRR) . . . . . . . . 565 17.5.21 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 18 19 16/1680 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . 568 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 18.2 VREFBUF functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 18.3 VREFBUF registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 18.3.1 VREFBUF control and status register (VREFBUF_CSR) . . . . . . . . . . 568 18.3.2 VREFBUF calibration control register (VREFBUF_CCR) . . . . . . . . . . 569 18.3.3 VREFBUF register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 19.2 COMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 19.3 COMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 19.3.1 COMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 19.3.2 COMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 19.3.3 COMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 19.3.4 Comparator LOCK mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 19.3.5 Window comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 19.3.6 Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 19.3.7 Comparator output blanking function . . . . . . . . . . . . . . . . . . . . . . . . . . 575 19.3.8 COMP power and speed modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 DocID024597 Rev 1 RM0351 20 21 Contents 19.4 COMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 19.5 COMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 19.6 COMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 19.6.1 Comparator 1 control and status register (COMP1_CSR) . . . . . . . . . . 577 19.6.2 Comparator 2 control and status register (COMP2_CSR) . . . . . . . . . . 579 19.6.3 COMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 20.2 OPAMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 20.3 OPAMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 20.3.1 OPAMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 20.3.2 Initial configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 20.3.3 Signal routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 20.3.4 OPAMP modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 20.3.5 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 20.4 OPAMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 20.5 OPAMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 20.5.1 OPAMP1 control/status register (OPAMP1_CSR) . . . . . . . . . . . . . . . . 590 20.5.2 OPAMP1 offset trimming register in normal mode (OPAMP1_OTR) . . 591 20.5.3 OPAMP1 offset trimming register in low-power mode (OPAMP1_LPOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 20.5.4 OPAMP2 control/status register (OPAMP2_CSR) . . . . . . . . . . . . . . . . 592 20.5.5 OPAMP2 offset trimming register in normal mode (OPAMP2_OTR) . . 593 20.5.6 OPAMP2 offset trimming register in low-power mode (OPAMP2_LPOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 20.5.7 OPAMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 Digital filter for sigma delta modulators (DFSDM) . . . . . . . . . . . . . . . 596 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 21.2 DFSDM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 21.3 DFSDM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 21.3.1 DFSDM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 21.3.2 DFSDM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 21.3.3 DFSDM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 21.3.4 Serial channel transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 21.3.5 Configuring the input serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . 609 DocID024597 Rev 1 17/1680 43 Contents RM0351 21.3.6 Parallel data inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 21.3.7 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 21.3.8 Digital filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 21.3.9 Integrator unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 21.3.10 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 21.3.11 Short-circuit detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 21.3.12 Extremes detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 21.3.13 Data unit block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 21.3.14 Signed data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 21.3.15 Launching conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 21.3.16 Continuous and fast continuous modes . . . . . . . . . . . . . . . . . . . . . . . . 618 21.3.17 Request precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 21.3.18 Power optimization in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 21.4 DFSDM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 21.5 DFSDM DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 21.6 DFSDM channel y registers (y=0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 21.7 21.6.1 DFSDM channel configuration y register (DFSDM_CHCFGyR1) (y=0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 21.6.2 DFSDM channel configuration y register (DFSDM_CHCFGyR2) (y=0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 21.6.3 DFSDM analog watchdog and short-circuit detector register (DFSDM_AWSCDyR) (y=0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 21.6.4 DFSDM channel watchdog filter data register (DFSDM_CHWDATyR) (y=0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 21.6.5 DFSDM channel data input register (DFSDM_CHDATINyR) (y=0..7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 DFSDMx module registers (x=0..3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 21.7.1 DFSDM control register 1 (DFSDMx_CR1) . . . . . . . . . . . . . . . . . . . . . 627 21.7.2 DFSDM control register 2 (DFSDMx_CR2) . . . . . . . . . . . . . . . . . . . . . 630 21.7.3 DFSDM interrupt and status register (DFSDMx_ISR) . . . . . . . . . . . . . 631 21.7.4 DFSDM interrupt flag clear register (DFSDMx_ICR) . . . . . . . . . . . . . . 633 21.7.5 DFSDM injected channel group selection register (DFSDMx_JCHGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634 21.7.6 DFSDM filter control register (DFSDMx_FCR) . . . . . . . . . . . . . . . . . . 634 21.7.7 DFSDM data register for injected group (DFSDMx_JDATAR) . . . . . . . 635 21.7.8 DFSDM data register for the regular channel (DFSDMx_RDATAR) . . 636 21.7.9 DFSDM analog watchdog high threshold register (DFSDMx_AWHTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 21.7.10 DFSDM analog watchdog low threshold register (DFSDMx_AWLTR) 637 18/1680 DocID024597 Rev 1 RM0351 Contents 21.7.11 DFSDM analog watchdog status register (DFSDMx_AWSR) . . . . . . . 638 21.7.12 DFSDM analog watchdog clear flag register (DFSDMx_AWCFR) . . . 638 21.7.13 DFSDM Extremes detector maximum register (DFSDMx_EXMAX) . . 639 21.7.14 DFSDM Extremes detector minimum register (DFSDMx_EXMIN) . . . 639 21.7.15 DFSDM conversion timer register (DFSDMx_CNVTIMR) . . . . . . . . . . 640 21.8 22 23 DFSDM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . 651 22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 22.2 LCD main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 22.3 LCD functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 22.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 22.3.2 Frequency generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 22.3.3 Common driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 22.3.4 Segment driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 22.3.5 Voltage generator and contrast control . . . . . . . . . . . . . . . . . . . . . . . . 662 22.3.6 Double buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 22.3.7 COM and SEG multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 22.3.8 Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 22.4 LCD low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 22.5 LCD interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 22.6 LCD registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 22.6.1 LCD control register (LCD_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 22.6.2 LCD frame control register (LCD_FCR) . . . . . . . . . . . . . . . . . . . . . . . . 674 22.6.3 LCD status register (LCD_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678 22.6.4 LCD clear register (LCD_CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 22.6.5 LCD display memory (LCD_RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 22.6.6 LCD register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 23.2 TSC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 23.3 TSC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 23.3.1 TSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 23.3.2 Surface charge transfer acquisition overview . . . . . . . . . . . . . . . . . . . 684 23.3.3 Reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 DocID024597 Rev 1 19/1680 43 Contents RM0351 23.3.4 Charge transfer acquisition sequence . . . . . . . . . . . . . . . . . . . . . . . . . 687 23.3.5 Spread spectrum feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 23.3.6 Max count error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 23.3.7 Sampling capacitor I/O and channel I/O mode selection . . . . . . . . . . . 689 23.3.8 Acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 23.3.9 I/O hysteresis and analog switch control . . . . . . . . . . . . . . . . . . . . . . . 690 23.3.10 Capacitive sensing GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 23.4 TSC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 23.5 TSC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 23.6 TSC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 23.6.1 TSC control register (TSC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 23.6.2 TSC interrupt enable register (TSC_IER) . . . . . . . . . . . . . . . . . . . . . . 695 23.6.3 TSC interrupt clear register (TSC_ICR) . . . . . . . . . . . . . . . . . . . . . . . . 696 23.6.4 TSC interrupt status register (TSC_ISR) . . . . . . . . . . . . . . . . . . . . . . . 697 23.6.5 TSC I/O hysteresis control register (TSC_IOHCR) . . . . . . . . . . . . . . . 697 23.6.6 TSC I/O analog switch control register (TSC_IOASCR) . . . . . . . . . . . 698 23.6.7 TSC I/O sampling control register (TSC_IOSCR) . . . . . . . . . . . . . . . . 698 23.6.8 TSC I/O channel control register (TSC_IOCCRTSC_IOCCR) . . . . . . . 699 23.6.9 TSC I/O group control status register (TSC_IOGCSR) . . . . . . . . . . . . 699 23.6.10 TSC I/O group x counter register (TSC_IOGxCR) (x = 1..8) . . . . . . . . 700 23.6.11 TSC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 24 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 24.2 RNG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 24.3 RNG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 24.4 25 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 24.3.2 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 RNG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 24.4.1 RNG control register (RNG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 24.4.2 RNG status register (RNG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 24.4.3 RNG data register (RNG_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 24.4.4 RNG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 Advanced encryption standard hardware accelerator (AES) . . . . . . 708 25.1 20/1680 24.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 DocID024597 Rev 1 RM0351 Contents 25.2 AES main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 25.3 AES functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 25.4 Encryption and derivation keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710 25.5 AES chaining algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .711 25.5.1 Electronic codebook (ECB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 25.5.2 Cipher block chaining (CBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 25.5.3 Counter Mode (CTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 25.6 Galois counter mode (GCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 25.7 AES cipher message authentication code mode (CMAC) . . . . . . . . . . . 720 25.8 Data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 25.9 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 25.9.1 Mode 1: encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 25.9.2 Mode 2: key derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 25.9.3 Mode 3: decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 25.9.4 Mode 4: key derivation and decryption . . . . . . . . . . . . . . . . . . . . . . . . 726 25.10 AES DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727 25.11 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 25.12 Processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 25.13 AES interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730 25.14 AES registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 25.14.1 AES control register (AES_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 25.14.2 AES status register (AES_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733 25.14.3 AES data input register (AES_DINR) . . . . . . . . . . . . . . . . . . . . . . . . . 735 25.14.4 AES data output register (AES_DOUTR) . . . . . . . . . . . . . . . . . . . . . . 735 25.14.5 AES key register 0 (AES_KEYR0) (LSB: key [31:0]) . . . . . . . . . . . . . . 736 25.14.6 AES key register 1 (AES_KEYR1) (key[63:32]) . . . . . . . . . . . . . . . . . . 736 25.14.7 AES key register 2 (AES_KEYR2) (key [95:64]) . . . . . . . . . . . . . . . . . 737 25.14.8 AES key register 3 (AES_KEYR3) (MSB: key[127:96]) . . . . . . . . . . . . 737 25.14.9 AES initialization vector register 0 (AES_IVR0) (LSB: IVR[31:0]) . . . . 737 25.14.10 AES initialization vector register 1 (AES_IVR1) (IVR[63:32]) . . . . . . . 738 25.14.11 AES initialization vector register 2 (AES_IVR2) (IVR[95:64]) . . . . . . . 739 25.14.12 AES initialization vector register 3 (AES_IVR3) (MSB: IVR[127:96]) . 739 25.14.13 AES key register 4 (AES_KEYR4) (key[159:128]) . . . . . . . . . . . . . . . . 739 25.14.14 AES key register 5 (AES_KEYR5) (key[191:160]) . . . . . . . . . . . . . . . . 740 25.14.15 AES key register 6 (AES_KEYR6) (key[223:192]) . . . . . . . . . . . . . . . . 740 25.14.16 AES key register 7 (AES_KEYR7) (MSB: key[255:224]) . . . . . . . . . . . 740 DocID024597 Rev 1 21/1680 43 Contents RM0351 25.14.17 AES Suspend registers (AES_SUSPxR) (x = 0..7) . . . . . . . . . . . . . . . 742 25.14.18 AES register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 26 Advanced-control timers (TIM1/TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 745 26.1 TIM1/TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 26.2 TIM1/TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 26.3 TIM1/TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 26.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 26.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 26.3.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760 26.3.4 External trigger input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 26.3.5 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 26.3.6 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 26.3.7 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 26.3.8 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 26.3.9 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 26.3.10 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 26.3.11 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 26.3.12 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 26.3.13 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 26.3.14 Combined 3-phase PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 26.3.15 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 780 26.3.16 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 26.3.17 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788 26.3.18 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 788 26.3.19 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 26.3.20 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791 26.3.21 Retriggerable one pulse mode (OPM) . . . . . . . . . . . . . . . . . . . . . . . . . 792 26.3.22 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 26.3.23 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 26.3.24 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796 26.3.25 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796 26.3.26 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799 26.3.27 ADC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 26.3.28 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 26.3.29 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 26.4 22/1680 TIM1/TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805 DocID024597 Rev 1 RM0351 Contents 26.4.1 TIM1/TIM8 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . 805 26.4.2 TIM1/TIM8 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . 806 26.4.3 TIM1/TIM8 slave mode control register (TIMx_SMCR) . . . . . . . . . . . . 809 26.4.4 TIM1/TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . . . . 812 26.4.5 TIM1/TIM8 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . 813 26.4.6 TIM1/TIM8 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . 815 26.4.7 TIM1/TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . 816 26.4.8 TIM1/TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . . . . . 821 26.4.9 TIM1/TIM8 capture/compare enable register (TIMx_CCER) . . . . . . . . 822 26.4.10 TIM1/TIM8 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 26.4.11 TIM1/TIM8 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 26.4.12 TIM1/TIM8 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 826 26.4.13 TIM1/TIM8 repetition counter register (TIMx_RCR) . . . . . . . . . . . . . . 827 26.4.14 TIM1/TIM8 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . 827 26.4.15 TIM1/TIM8 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . 828 26.4.16 TIM1/TIM8 capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . 828 26.4.17 TIM1/TIM8 capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . 829 26.4.18 TIM1/TIM8 break and dead-time register (TIMx_BDTR) . . . . . . . . . . . 829 26.4.19 TIM1/TIM8 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . 833 26.4.20 TIM1/TIM8 DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . 834 26.4.21 TIM1 option register 1 (TIM1_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 26.4.22 TIM8 option register 1 (TIM8_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 26.4.23 TIM1/TIM8 capture/compare mode register 3 (TIMx_CCMR3) . . . . . . 836 26.4.24 TIM1/TIM8 capture/compare register 5 (TIMx_CCR5) . . . . . . . . . . . . 836 26.4.25 TIM1/TIM8 capture/compare register 6 (TIMx_CCR6) . . . . . . . . . . . . 838 26.4.26 TIM1 option register 2 (TIM1_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 838 26.4.27 TIM1 option register 3 (TIM1_OR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 26.4.28 TIM8 option register 2 (TIM8_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 26.4.29 TIM8 option register 3 (TIM8_OR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 843 26.4.30 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844 26.4.31 TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 27 General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . . . . . . . . . . . . . . 850 27.1 TIM2/TIM3/TIM4/TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 27.2 TIM2/TIM3/TIM4/TIM5 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 27.3 TIM2/TIM3/TIM4/TIM5 functional description . . . . . . . . . . . . . . . . . . . . . 852 27.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 DocID024597 Rev 1 23/1680 43 Contents RM0351 27.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854 27.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864 27.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 27.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 27.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872 27.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873 27.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873 27.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874 27.3.10 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878 27.3.11 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878 27.3.12 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 879 27.3.13 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881 27.3.14 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882 27.3.15 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884 27.3.16 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885 27.3.17 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 885 27.3.18 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889 27.3.19 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893 27.3.20 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894 27.4 TIM2/TIM3/TIM4/TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895 27.4.1 TIMx control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 895 27.4.2 TIMx control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 897 27.4.3 TIMx slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . 898 27.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 902 27.4.5 TIMx status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903 27.4.6 TIMx event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 905 27.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 906 27.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . 910 27.4.9 TIMx capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . 911 27.4.10 TIMx counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913 27.4.11 TIMx prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914 27.4.12 TIMx auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 914 27.4.13 TIMx capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 914 27.4.14 TIMx capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 915 27.4.15 TIMx capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . 915 27.4.16 TIMx capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . 916 27.4.17 TIMx DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . 917 24/1680 DocID024597 Rev 1 RM0351 Contents 27.4.18 TIMx DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . 917 27.4.19 TIM2 option register 1 (TIM2_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 917 27.4.20 TIM3 option register 1 (TIM3_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 918 27.4.21 TIM2 option register 2 (TIM2_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 918 27.4.22 TIM3 option register 2 (TIM3_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 919 27.4.23 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920 28 General-purpose timers (TIM15/16/17) . . . . . . . . . . . . . . . . . . . . . . . . 923 28.1 TIM15/16/17 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923 28.2 TIM15 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923 28.3 TIM16 and TIM17 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924 28.4 TIM15/16/17 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927 28.4.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927 28.4.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 28.4.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933 28.4.4 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934 28.4.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936 28.4.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 28.4.7 PWM input mode (only for TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940 28.4.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941 28.4.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941 28.4.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942 28.4.11 Combined PWM mode (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . . . 943 28.4.12 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 945 28.4.13 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947 28.4.14 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951 28.4.15 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952 28.4.16 Timer input XOR function (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . 953 28.4.17 External trigger synchronization (TIM15 only) . . . . . . . . . . . . . . . . . . . 954 28.4.18 Slave mode: Combined reset + trigger mode . . . . . . . . . . . . . . . . . . . 956 28.4.19 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956 28.4.20 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957 28.5 TIM15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 28.5.1 TIM15 control register 1 (TIM15_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 958 28.5.2 TIM15 control register 2 (TIM15_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 959 28.5.3 TIM15 slave mode control register (TIM15_SMCR) . . . . . . . . . . . . . . 961 28.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . . . . . . . . . . 962 DocID024597 Rev 1 25/1680 43 Contents RM0351 28.5.5 TIM15 status register (TIM15_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 963 28.5.6 TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . . 965 28.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . . . . . 966 28.5.8 TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . . 969 28.5.9 TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972 28.5.10 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972 28.5.11 TIM15 auto-reload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . . 972 28.5.12 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . . 973 28.5.13 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . . 973 28.5.14 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . . 974 28.5.15 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . . 974 28.5.16 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . . 976 28.5.17 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . . 976 28.5.18 TIM15 option register 1 (TIM15_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . 977 28.5.19 TIM15 option register 2 (TIM15_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . 977 28.5.20 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979 28.6 TIM16&TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982 28.6.1 TIM16&TIM17 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . 982 28.6.2 TIM16&TIM17 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . 983 28.6.3 TIM16&TIM17 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . 984 28.6.4 TIM16&TIM17 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . 985 28.6.5 TIM16&TIM17 event generation register (TIMx_EGR) . . . . . . . . . . . . 986 28.6.6 TIM16&TIM17 capture/compare mode register 1 (TIMx_CCMR1) . . . 987 28.6.7 TIM16&TIM17 capture/compare enable register (TIMx_CCER) . . . . . 989 28.6.8 TIM16&TIM17 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 991 28.6.9 TIM16&TIM17 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . 992 28.6.10 TIM16&TIM17 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . 992 28.6.11 TIM16&TIM17 repetition counter register (TIMx_RCR) . . . . . . . . . . . . 993 28.6.12 TIM16&TIM17 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . 993 28.6.13 TIM16&TIM17 break and dead-time register (TIMx_BDTR) . . . . . . . . 994 28.6.14 TIM16&TIM17 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . 996 28.6.15 TIM16&TIM17 DMA address for full transfer (TIMx_DMAR) . . . . . . . . 996 28.6.16 TIM16 option register 1 (TIM16_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . 996 28.6.17 TIM16 option register 2 (TIM16_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . 997 28.6.18 TIM17 option register 1 (TIM17_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . 998 28.6.19 TIM17 option register 2 (TIM17_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . 999 28.6.20 TIM16&TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001 26/1680 DocID024597 Rev 1 RM0351 29 Contents Basic timers (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003 29.1 TIM6/TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003 29.2 TIM6/TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003 29.3 TIM6/TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004 29.4 30 29.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004 29.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006 29.3.3 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009 29.3.4 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009 29.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010 TIM6/TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010 29.4.1 TIM6/TIM7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . 1010 29.4.2 TIM6/TIM7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . 1012 29.4.3 TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . 1012 29.4.4 TIM6/TIM7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . 1013 29.4.5 TIM6/TIM7 event generation register (TIMx_EGR) . . . . . . . . . . . . . . 1013 29.4.6 TIM6/TIM7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 29.4.7 TIM6/TIM7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014 29.4.8 TIM6/TIM7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . 1014 29.4.9 TIM6/TIM7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015 Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016 30.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016 30.2 LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016 30.3 LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016 30.4 LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 30.4.1 LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 30.4.2 LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 30.4.3 Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018 30.4.4 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019 30.4.5 Trigger multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019 30.4.6 Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020 30.4.7 Timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020 30.4.8 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021 30.4.9 Register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022 30.4.10 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023 30.4.11 Timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023 DocID024597 Rev 1 27/1680 43 Contents RM0351 30.4.12 Encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023 30.5 LPTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025 30.6 LPTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026 30.6.1 LPTIM Interrupt and Status Register (LPTIMx_ISR) . . . . . . . . . . . . . 1026 30.6.2 LPTIM Interrupt Clear Register (LPTIMx_ICR) . . . . . . . . . . . . . . . . . 1027 30.6.3 LPTIM Interrupt Enable Register (LPTIMx_IER) . . . . . . . . . . . . . . . . 1028 30.6.4 LPTIM Configuration Register (LPTIMx_CFGR) . . . . . . . . . . . . . . . . 1029 30.6.5 LPTIM Control Register (LPTIMx_CR) . . . . . . . . . . . . . . . . . . . . . . . 1032 30.6.6 LPTIM Compare Register (LPTIMx_CMP) . . . . . . . . . . . . . . . . . . . . 1033 30.6.7 LPTIM Autoreload Register (LPTIMx_ARR) . . . . . . . . . . . . . . . . . . . 1033 30.6.8 LPTIM Counter Register (LPTIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . 1034 30.6.9 LPTIM1 Option Register (LPTIM1_OR) . . . . . . . . . . . . . . . . . . . . . . . 1034 30.6.10 LPTIM2 Option Register (LPTIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . 1034 30.6.11 LPTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036 31 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037 32 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038 32.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038 32.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038 32.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038 32.4 33 IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038 32.3.2 Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039 32.3.3 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039 32.3.4 Low-power freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040 32.3.5 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040 32.3.6 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040 32.4.1 Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040 32.4.2 Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041 32.4.3 Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042 32.4.4 Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043 32.4.5 Window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044 32.4.6 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . 1046 33.1 28/1680 32.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046 DocID024597 Rev 1 RM0351 Contents 33.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046 33.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046 33.4 34 33.3.1 Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047 33.3.2 Controlling the downcounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047 33.3.3 Advanced watchdog interrupt feature . . . . . . . . . . . . . . . . . . . . . . . . 1047 33.3.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . 1048 33.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049 33.4.1 Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049 33.4.2 Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . 1050 33.4.3 Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050 33.4.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052 34.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052 34.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053 34.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054 34.3.1 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054 34.3.2 GPIOs controlled by the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055 34.3.3 Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056 34.3.4 Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057 34.3.5 Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058 34.3.6 Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058 34.3.7 RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 1059 34.3.8 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060 34.3.9 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061 34.3.10 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062 34.3.11 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062 34.3.12 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063 34.3.13 Time-stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065 34.3.14 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066 34.3.15 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068 34.3.16 Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068 34.4 RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 34.5 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 34.6 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 DocID024597 Rev 1 29/1680 43 Contents RM0351 34.6.1 RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 34.6.2 RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072 34.6.3 RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073 34.6.4 RTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . 1076 34.6.5 RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . 1079 34.6.6 RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . 1080 34.6.7 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . 1081 34.6.8 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . 1082 34.6.9 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . 1083 34.6.10 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . 1083 34.6.11 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . 1084 34.6.12 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . 1085 34.6.13 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . 1086 34.6.14 RTC time-stamp sub second register (RTC_TSSSR) . . . . . . . . . . . . 1087 34.6.15 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . 1088 34.6.16 RTC tamper configuration register (RTC_TAMPCR) . . . . . . . . . . . . . 1089 34.6.17 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . 1092 34.6.18 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . 1093 34.6.19 RTC option register (RTC_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094 34.6.20 RTC backup registers (RTC_BKPxR) . . . . . . . . . . . . . . . . . . . . . . . . 1095 34.6.21 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096 35 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . 1098 35.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098 35.2 I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098 35.3 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099 35.4 I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099 35.4.1 I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100 35.4.2 I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101 35.4.3 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101 35.4.4 I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103 35.4.5 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107 35.4.6 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108 35.4.7 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110 35.4.8 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119 35.4.9 I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . 1131 35.4.10 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132 30/1680 DocID024597 Rev 1 RM0351 Contents 35.4.11 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135 35.4.12 SMBus: I2C_TIMEOUTR register configuration examples . . . . . . . . 1137 35.4.13 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138 35.4.14 Wakeup from Stop mode on address match . . . . . . . . . . . . . . . . . . . 1145 35.4.15 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146 35.4.16 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148 35.4.17 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149 35.5 I2C low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1149 35.6 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1149 35.7 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1151 35.7.1 Control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151 35.7.2 Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154 35.7.3 Own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . . . 1157 35.7.4 Own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . 1158 35.7.5 Timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159 35.7.6 Timeout register (I2C_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1160 35.7.7 Interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . . . . 1161 35.7.8 Interrupt clear register (I2C_ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163 35.7.9 PEC register (I2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164 35.7.10 Receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1165 35.7.11 Transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1165 35.7.12 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166 36 Universal synchronous asynchronous receiver transmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168 36.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1168 36.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1168 36.3 USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1169 36.4 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1170 36.5 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1170 36.5.1 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173 36.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174 36.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177 36.5.4 Baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184 36.5.5 Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . 1186 36.5.6 Auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187 DocID024597 Rev 1 31/1680 43 Contents RM0351 36.5.7 Multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188 36.5.8 Modbus communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190 36.5.9 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191 36.5.10 LIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . 1192 36.5.11 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194 36.5.12 Single-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . 1197 36.5.13 Smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197 36.5.14 IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202 36.5.15 Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . 1204 36.5.16 RS232 Hardware flow control and RS485 Driver Enable . . . . . . . . . 1206 36.5.17 Wakeup from Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208 36.6 USART low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209 36.7 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210 36.8 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212 36.8.1 Control register 1 (USARTx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212 36.8.2 Control register 2 (USARTx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215 36.8.3 Control register 3 (USARTx_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219 36.8.4 Baud rate register (USARTx_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1223 36.8.5 Guard time and prescaler register (USARTx_GTPR) . . . . . . . . . . . . 1223 36.8.6 Receiver timeout register (USARTx_RTOR) . . . . . . . . . . . . . . . . . . . 1224 36.8.7 Request register (USARTx_RQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225 36.8.8 Interrupt & status register (USARTx_ISR) . . . . . . . . . . . . . . . . . . . . . 1226 36.8.9 Interrupt flag clear register (USARTx_ICR) . . . . . . . . . . . . . . . . . . . . 1231 36.8.10 Receive data register (USARTx_RDR) . . . . . . . . . . . . . . . . . . . . . . . 1232 36.8.11 Transmit data register (USARTx_TDR) . . . . . . . . . . . . . . . . . . . . . . . 1232 36.8.12 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233 37 32/1680 Low-power universal asynchronous receiver transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235 37.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235 37.2 LPUART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236 37.3 LPUART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236 37.4 LPUART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1237 37.4.1 LPUART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238 37.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241 37.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243 DocID024597 Rev 1 RM0351 Contents 37.4.4 Baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246 37.4.5 Multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1247 37.4.6 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249 37.4.7 Single-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . 1250 37.4.8 Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . 1250 37.4.9 RS232 Hardware flow control and RS485 Driver Enable . . . . . . . . . 1253 37.4.10 Wakeup from Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255 37.5 LPUART low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255 37.6 LPUART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256 37.7 LPUART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258 37.7.1 Control register 1 (LPUART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258 37.7.2 Control register 2 (LPUART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261 37.7.3 Control register 3 (LPUART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263 37.7.4 Baud rate register (LPUART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1265 37.7.5 Request register (LPUART_RQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265 37.7.6 Interrupt & status register (LPUART_ISR) . . . . . . . . . . . . . . . . . . . . . 1266 37.7.7 Interrupt flag clear register (LPUART_ICR) . . . . . . . . . . . . . . . . . . . . 1269 37.7.8 Receive data register (LPUART_RDR) . . . . . . . . . . . . . . . . . . . . . . . 1270 37.7.9 Transmit data register (LPUART_TDR) . . . . . . . . . . . . . . . . . . . . . . . 1270 37.7.10 LPUART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272 38 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273 38.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273 38.2 SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273 38.3 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273 38.4 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274 38.4.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274 38.4.2 Communications between one master and one slave . . . . . . . . . . . . 1275 38.4.3 Standard multi-slave communication . . . . . . . . . . . . . . . . . . . . . . . . . 1277 38.4.4 Slave select (NSS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . 1278 38.4.5 Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280 38.4.6 Configuration of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282 38.4.7 Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283 38.4.8 Data transmission and reception procedures . . . . . . . . . . . . . . . . . . 1283 38.4.9 SPI status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293 38.4.10 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294 DocID024597 Rev 1 33/1680 43 Contents RM0351 38.4.11 NSS pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295 38.4.12 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295 38.4.13 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296 39 38.5 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1298 38.6 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299 38.6.1 SPI control register 1 (SPIx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299 38.6.2 SPI control register 2 (SPIx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301 38.6.3 SPI status register (SPIx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304 38.6.4 SPI data register (SPIx_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305 38.6.5 SPI CRC polynomial register (SPIx_CRCPR) . . . . . . . . . . . . . . . . . . 1305 38.6.6 SPI Rx CRC register (SPIx_RXCRCR) . . . . . . . . . . . . . . . . . . . . . . . 1306 38.6.7 SPI Tx CRC register (SPIx_TXCRCR) . . . . . . . . . . . . . . . . . . . . . . . 1306 38.6.8 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308 39.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308 39.2 SAI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309 39.3 SAI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310 39.3.1 SAI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310 39.3.2 Main SAI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311 39.3.3 SAI synchronization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312 39.3.4 Audio data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313 39.3.5 Frame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313 39.3.6 Slot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1316 39.3.7 SAI clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1318 39.3.8 Internal FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1320 39.3.9 AC’97 link controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1322 39.3.10 SPDIF output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1324 39.3.11 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326 39.3.12 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1331 39.3.13 Disabling the SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1334 39.3.14 SAI DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1334 34/1680 39.4 SAI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336 39.5 SAI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1337 39.5.1 Global configuration register (SAI_GCR) . . . . . . . . . . . . . . . . . . . . . . 1337 39.5.2 Configuration register 1 (SAI_ACR1 / SAI_BCR1) . . . . . . . . . . . . . . 1337 DocID024597 Rev 1 RM0351 Contents 39.5.3 Configuration register 2 (SAI_ACR2 / SAI_BCR2) . . . . . . . . . . . . . . 1341 39.5.4 Frame configuration register (SAI_AFRCR / SAI_BFRCR) . . . . . . . . 1343 39.5.5 Slot register (SAI_ASLOTR / SAI_BSLOTR) . . . . . . . . . . . . . . . . . . . 1345 39.5.6 Interrupt mask register 2 (SAI_AIM / SAI_BIM) . . . . . . . . . . . . . . . . . 1347 39.5.7 Status register (SAI_ASR / SAI_BSR) . . . . . . . . . . . . . . . . . . . . . . . . 1349 39.5.8 Clear flag register (SAI_ACLRFR / SAI_BCLRFR) . . . . . . . . . . . . . . 1351 39.5.9 Data register (SAI_ADR / SAI_BDR) . . . . . . . . . . . . . . . . . . . . . . . . . 1352 39.5.10 SAI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1352 40 Single Wire Protocol Master Interface (SWPMI) . . . . . . . . . . . . . . . . 1354 40.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354 40.2 SWPMI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355 40.3 SWPMI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356 40.3.1 SWPMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356 40.3.2 SWP initialization and activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356 40.3.3 SWP bus states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356 40.3.4 SWPMI_IO (internal transceiver) bypass . . . . . . . . . . . . . . . . . . . . . . 1358 40.3.5 SWPMI Bit rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358 40.3.6 SWPMI frame handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358 40.3.7 Transmission procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1359 40.3.8 Reception procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363 40.3.9 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368 40.3.10 Loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370 40.4 SWPMI low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370 40.5 SWPMI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370 40.6 SWPMI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1372 40.6.1 SWPMI Configuration/Control register (SWPMI_CR) . . . . . . . . . . . . 1372 40.6.2 SWPMI Bitrate register (SWPMI_BRR) . . . . . . . . . . . . . . . . . . . . . . . 1374 40.6.3 SWPMI Interrupt and Status register (SWPMI_ISR) . . . . . . . . . . . . . 1375 40.6.4 SWPMI Interrupt Flag Clear register (SWPMI_ICR) . . . . . . . . . . . . . 1377 40.6.5 SWPMI Interrupt Enable register (SMPMI_IER) . . . . . . . . . . . . . . . . 1378 40.6.6 SWPMI Receive Frame Length register (SWPMI_RFL) . . . . . . . . . . 1379 40.6.7 SWPMI Transmit data register (SWPMI_TDR) . . . . . . . . . . . . . . . . . 1380 40.6.8 SWPMI Receive data register (SWPMI_RDR) . . . . . . . . . . . . . . . . . 1381 40.6.9 SWPMI Option register (SWPMI_OR) . . . . . . . . . . . . . . . . . . . . . . . . 1382 40.6.10 SWPMI register map and reset value table . . . . . . . . . . . . . . . . . . . . 1383 DocID024597 Rev 1 35/1680 43 Contents 41 RM0351 SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . 1384 41.1 SDMMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384 41.2 SDMMC bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384 41.3 SDMMC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386 41.4 41.3.1 SDMMC adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388 41.3.2 SDMMC APB2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399 Card functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400 41.4.1 Card identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400 41.4.2 Card reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400 41.4.3 Operating voltage range validation . . . . . . . . . . . . . . . . . . . . . . . . . . 1401 41.4.4 Card identification process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401 41.4.5 Block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402 41.4.6 Block read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1403 41.4.7 Stream access, stream write and stream read (MultiMediaCard only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1403 41.4.8 Erase: group erase and sector erase . . . . . . . . . . . . . . . . . . . . . . . . 1405 41.4.9 Wide bus selection or deselection . . . . . . . . . . . . . . . . . . . . . . . . . . . 1405 41.4.10 Protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1405 41.4.11 Card status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1409 41.4.12 SD status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412 41.4.13 SD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1416 41.4.14 Commands and responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417 41.5 41.6 36/1680 Response formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1420 41.5.1 R1 (normal response command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421 41.5.2 R1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421 41.5.3 R2 (CID, CSD register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421 41.5.4 R3 (OCR register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1422 41.5.5 R4 (Fast I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1422 41.5.6 R4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1422 41.5.7 R5 (interrupt request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423 41.5.8 R6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423 SDIO I/O card-specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424 41.6.1 SDIO I/O read wait operation by SDMMC_D2 signalling . . . . . . . . . . 1424 41.6.2 SDIO read wait operation by stopping SDMMC_CK . . . . . . . . . . . . . 1425 41.6.3 SDIO suspend/resume operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425 41.6.4 SDIO interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425 DocID024597 Rev 1 RM0351 Contents 41.7 HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425 41.8 SDMMC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1426 41.8.1 SDMMC power control register (SDMMC_POWER) . . . . . . . . . . . . . 1426 41.8.2 SDMMC clock control register (SDMMC_CLKCR) . . . . . . . . . . . . . . 1426 41.8.3 SDMMC argument register (SDMMC_ARG) . . . . . . . . . . . . . . . . . . . 1428 41.8.4 SDMMC command register (SDMMC_CMD) . . . . . . . . . . . . . . . . . . 1428 41.8.5 SDMMC command response register (SDMMC_RESPCMD) . . . . . . 1429 41.8.6 SDMMC response 1..4 register (SDMMC_RESPx) . . . . . . . . . . . . . . 1429 41.8.7 SDMMC data timer register (SDMMC_DTIMER) . . . . . . . . . . . . . . . . 1430 41.8.8 SDMMC data length register (SDMMC_DLEN) . . . . . . . . . . . . . . . . . 1431 41.8.9 SDMMC data control register (SDMMC_DCTRL) . . . . . . . . . . . . . . . 1431 41.8.10 SDMMC data counter register (SDMMC_DCOUNT) . . . . . . . . . . . . . 1433 41.8.11 SDMMC status register (SDMMC_STA) . . . . . . . . . . . . . . . . . . . . . . 1433 41.8.12 SDMMC interrupt clear register (SDMMC_ICR) . . . . . . . . . . . . . . . . 1434 41.8.13 SDMMC mask register (SDMMC_MASK) . . . . . . . . . . . . . . . . . . . . . 1436 41.8.14 SDMMC FIFO counter register (SDMMC_FIFOCNT) . . . . . . . . . . . . 1438 41.8.15 SDMMC data FIFO register (SDMMC_FIFO) . . . . . . . . . . . . . . . . . . 1439 41.8.16 SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1439 42 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1442 42.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1442 42.2 bxCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1442 42.3 bxCAN general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1443 42.4 42.5 42.6 42.3.1 CAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1443 42.3.2 Control, status and configuration registers . . . . . . . . . . . . . . . . . . . . 1443 42.3.3 Tx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1443 42.3.4 Acceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1444 bxCAN operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1444 42.4.1 Initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1444 42.4.2 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1444 42.4.3 Sleep mode (low-power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1445 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446 42.5.1 Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446 42.5.2 Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447 42.5.3 Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . 1447 Behavior in Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1448 DocID024597 Rev 1 37/1680 43 Contents RM0351 42.7 43 42.7.1 Transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1448 42.7.2 Time triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 1450 42.7.3 Reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1450 42.7.4 Identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1451 42.7.5 Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455 42.7.6 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457 42.7.7 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457 42.8 bxCAN interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1460 42.9 CAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461 42.9.1 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461 42.9.2 CAN control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461 42.9.3 CAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1471 42.9.4 CAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478 42.9.5 bxCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482 USB on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . . . . . . . . . . 1486 43.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486 43.2 USB_OTG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486 43.2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486 43.2.2 Host-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487 43.2.3 Peripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488 43.3 USB_OTG Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488 43.4 USB OTG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489 43.5 43.6 43.7 38/1680 bxCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1448 43.4.1 USB OTG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489 43.4.2 OTG core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489 43.4.3 Full-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490 OTG dual role device (DRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491 43.5.1 ID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491 43.5.2 HNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491 43.5.3 SRP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492 USB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492 43.6.1 SRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493 43.6.2 Peripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493 43.6.3 Peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494 USB host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1496 DocID024597 Rev 1 RM0351 Contents 43.8 43.9 43.7.1 SRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497 43.7.2 USB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497 43.7.3 Host channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1499 43.7.4 Host scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 SOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501 43.8.1 Host SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501 43.8.2 Peripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501 Power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502 43.10 Dynamic update of the OTG_HFIR register . . . . . . . . . . . . . . . . . . . . . 1503 43.11 USB data FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1503 43.11.1 Peripheral FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504 43.11.2 Host FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505 43.11.3 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506 43.12 OTG_FS system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507 43.13 OTG_FS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1508 43.14 OTG_FS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . 1509 43.14.1 CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1509 43.15 OTG_FS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1513 43.15.1 OTG control and status register (OTG_GOTGCTL) . . . . . . . . . . . . . 1513 43.15.2 OTG interrupt register (OTG_GOTGINT) . . . . . . . . . . . . . . . . . . . . . 1515 43.15.3 OTG AHB configuration register (OTG_GAHBCFG) . . . . . . . . . . . . . 1517 43.15.4 OTG USB configuration register (OTG_GUSBCFG) . . . . . . . . . . . . . 1517 43.15.5 OTG reset register (OTG_GRSTCTL) . . . . . . . . . . . . . . . . . . . . . . . . 1519 43.15.6 OTG core interrupt register (OTG_GINTSTS) . . . . . . . . . . . . . . . . . . 1521 43.15.7 OTG interrupt mask register (OTG_GINTMSK) . . . . . . . . . . . . . . . . . 1525 43.15.8 OTG_FS Receive status debug read/OTG status read and pop registers (OTG_GRXSTSR/OTG_GRXSTSP) . . . . . . . . . . . . . . 1528 43.15.9 OTG Receive FIFO size register (OTG_GRXFSIZ) . . . . . . . . . . . . . . 1530 43.15.10 OTG Host non-periodic transmit FIFO size register (OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531 43.15.11 OTG non-periodic transmit FIFO/queue status register (OTG_HNPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532 43.15.12 OTG general core configuration register (OTG_GCCFG) . . . . . . . . . 1533 43.15.13 OTG core ID register (OTG_CID) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1534 43.15.14 OTG core LPM configuration register (OTG_GLPMCFG) . . . . . . . . . 1535 43.15.15 OTG power down register (OTG_GPWRDN) . . . . . . . . . . . . . . . . . . 1539 DocID024597 Rev 1 39/1680 43 Contents RM0351 43.15.16 OTG ADP timer, control and status register (OTG_GADPCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1539 43.15.17 OTG Host periodic transmit FIFO size register (OTG_HPTXFSIZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541 43.15.18 OTG device IN endpoint transmit FIFO size register (OTG_DIEPTXFx) (x = 1..5 , where x is the FIFO_number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542 43.15.19 Host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542 43.15.20 OTG Host configuration register (OTG_HCFG) . . . . . . . . . . . . . . . . . 1542 43.15.21 OTG Host frame interval register (OTG_HFIR) . . . . . . . . . . . . . . . . . 1543 43.15.22 OTG Host frame number/frame time remaining register (OTG_HFNUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544 43.15.23 OTG_Host periodic transmit FIFO/queue status register (OTG_HPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1545 43.15.24 OTG Host all channels interrupt register (OTG_HAINT) . . . . . . . . . . 1546 43.15.25 OTG Host all channels interrupt mask register (OTG_HAINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1546 43.15.26 OTG Host port control and status register (OTG_HPRT) . . . . . . . . . 1547 43.15.27 OTG Host channel-x characteristics register (OTG_HCCHARx) (x = 0..11, where x = Channel_number) . . . . . . . . . . . . . . . . . . . . . . 1549 43.15.28 OTG Host channel-x interrupt register (OTG_HCINTx) (x = 0..11, where x = Channel_number) . . . . . . . . . . . . . . . . . . . . . . 1551 43.15.29 OTG Host channel-x interrupt mask register (OTG_HCINTMSKx) (x = 0..11, where x = Channel_number) . . . . . . . . . . . . . . . . . . . . . . 1552 43.15.30 OTG Host channel-x transfer size register (OTG_HCTSIZx) (x = 0..11, where x = Channel_number) . . . . . . . . . . . . . . . . . . . . . . 1553 43.15.31 Device-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1554 43.15.32 OTG device configuration register (OTG_DCFG) . . . . . . . . . . . . . . . 1554 43.15.33 OTG device control register (OTG_DCTL) . . . . . . . . . . . . . . . . . . . . 1555 43.15.34 OTG device status register (OTG_DSTS) . . . . . . . . . . . . . . . . . . . . . 1557 43.15.35 OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558 43.15.36 OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559 43.15.37 OTG device all endpoints interrupt register (OTG_DAINT) . . . . . . . . 1559 43.15.38 OTG all endpoints interrupt mask register (OTG_DAINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560 43.15.39 OTG device VBUS discharge time register (OTG_DVBUSDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561 43.15.40 OTG device VBUS pulsing time register (OTG_DVBUSPULSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561 40/1680 DocID024597 Rev 1 RM0351 Contents 43.15.41 OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562 43.15.42 OTG device control IN endpoint 0 control register (OTG_DIEPCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562 43.15.43 OTG device endpoint-x control register (OTG_DIEPCTLx) (x = 1..5 , where x = Endpoint_number) . . . . . . . . . . . . . . . . . . . . . . 1564 43.15.44 OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566 43.15.45 OTG device endpoint-x control register (OTG_DOEPCTLx) (x = 1..5 , where x = Endpoint_number) . . . . . . . . . . . . . . . . . . . . . . 1568 43.15.46 OTG device endpoint-x interrupt register (OTG_DIEPINTx) (x = 0..5 , where x = Endpoint_number) . . . . . . . . . . . . . . . . . . . . . . 1570 43.15.47 OTG device endpoint-x interrupt register (OTG_DOEPINTx) (x = 0..5 , where x = Endpoint_number) . . . . . . . . . . . . . . . . . . . . . . 1571 43.15.48 OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1572 43.15.49 OTG device OUT endpoint 0 transfer size register (OTG_DOEPTSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1573 43.15.50 OTG device IN endpoint-x transfer size register (OTG_DIEPTSIZx) (x = 1..5 , where x= Endpoint_number) . . . . . . . . . . . . . . . . . . . . . . . 1574 43.15.51 OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) (x = 0..5 , where x = Endpoint_number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575 43.15.52 OTG device OUT endpoint-x transfer size register (OTG_DOEPTSIZx) (x = 1..5 , where x = Endpoint_number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575 43.15.53 OTG power and clock gating control register (OTG_PCGCCTL) . . . 1576 43.15.54 OTG_FS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577 43.16 OTG_FS programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1585 43.16.1 Core initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1585 43.16.2 Host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1586 43.16.3 Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1586 43.16.4 Host programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1587 43.16.5 Device programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607 43.16.6 Worst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627 43.16.7 OTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629 44 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636 44.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636 44.2 Reference ARM® documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1637 44.3 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . 1637 DocID024597 Rev 1 41/1680 43 Contents RM0351 44.3.1 44.4 Mechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . 1638 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1638 44.4.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639 44.4.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639 44.4.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . 1640 44.4.4 Using serial wire and releasing the unused debug pins as GPIOs . . 1641 44.5 STM32L4x6 JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641 44.6 ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642 44.6.1 MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643 44.6.2 Boundary scan TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643 44.6.3 Cortex®-M4 TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643 44.6.4 Cortex®-M4 JEDEC-106 ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644 44.7 JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644 44.8 SW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646 44.9 44.8.1 SW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646 44.8.2 SW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646 44.8.3 SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . 1647 44.8.4 DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647 44.8.5 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648 44.8.6 SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649 44.10 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650 44.11 Capability of the debugger host to connect under system reset . . . . . 1650 44.12 FPB (Flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651 44.13 DWT (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651 44.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . 1652 44.14.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652 44.14.2 Time stamp packets, synchronization and overflow packets . . . . . . . 1652 44.15 ETM (Embedded trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654 44.15.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654 44.15.2 Signal protocol, packet types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654 44.15.3 Main ETM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654 44.15.4 Configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655 44.16 MCU debug component (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . . 1655 44.16.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 1655 42/1680 DocID024597 Rev 1 RM0351 Contents 44.16.2 Debug support for timers, RTC, watchdog, bxCAN and I2C . . . . . . . 1656 44.16.3 Debug MCU configuration register (DBGMCU_CR) . . . . . . . . . . . . . 1656 44.16.4 Debug MCU APB1 freeze register1(DBGMCU_APB1FZR1) . . . . . . 1658 44.16.5 Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2) . . . . . 1660 44.16.6 Debug MCU APB2 freeze register (DBGMCU_APB2FZR) . . . . . . . . 1661 44.17 TPIU (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662 44.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662 44.17.2 TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662 44.17.3 TPUI formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1664 44.17.4 TPUI frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . 1665 44.17.5 Transmission of the synchronization frame packet . . . . . . . . . . . . . . 1665 44.17.6 Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665 44.17.7 Asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666 44.17.8 TRACECLKIN connection inside the STM32L4x6 . . . . . . . . . . . . . . . 1666 44.17.9 TPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1667 44.17.10 Example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668 44.18 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669 45 46 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1670 45.1 Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1670 45.2 Flash size data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671 45.3 Package data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1679 DocID024597 Rev 1 43/1680 43 List of tables RM0351 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. 44/1680 STM32L4x6 memory map and peripheral register boundary addresses . . . . . . . . . . . . . . 68 SRAM2 organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Flash module - 1 MB dual bank organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Flash module - 512 KB dual bank organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Flash module - 256 KB dual bank organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Number of wait states according to CPU clock (HCLK) frequency . . . . . . . . . . . . . . . . . . . 82 Option byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Option byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Flash memory read protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Access status versus protection level and execution modes . . . . . . . . . . . . . . . . . . . . . . 102 Flash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Flash interface - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Segment accesses according to the Firewall state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Segment granularity and area ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Firewall register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 PVM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Low-power run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Low-power sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 STM32L4x6 peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Clock source frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Programmable data width & endian behavior (when bits PINC = MINC = 1) . . . . . . . . . . 304 DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Summary of the DMA1 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 Summary of the DMA2 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 STM32L4x6 vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 EXTI lines connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 Extended interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . 341 NOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 NOR/PSRAM External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 NAND memory mapping and timing registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 NAND bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 Programmable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 DocID024597 Rev 1 RM0351 Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. List of tables Non-multiplexed I/O NOR Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 16-bit multiplexed I/O NOR Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 Non-multiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 16-Bit multiplexed I/O PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 NOR Flash/PSRAM: example of supported memories and transactions . . . . . . . . . . . . . 351 FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 FMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 FMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 FMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 FMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Programmable NAND Flash access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 8-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 16-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 ECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 FMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 QUADSPI interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 QUADSPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 ADC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 Configuring the trigger polarity for regular external triggers . . . . . . . . . . . . . . . . . . . . . . . 445 Configuring the trigger polarity for injected external triggers . . . . . . . . . . . . . . . . . . . . . . 445 ADC1, ADC2 and ADC3 - External triggers for regular channels . . . . . . . . . . . . . . . . . . . 446 ADC1, ADC2 and ADC3 - External trigger for injected channels . . . . . . . . . . . . . . . . . . . 447 TSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 Offset computation versus data resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 Analog watchdog 1 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 Analog watchdog 2 and 3 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 Maximum output results versus N and M (gray cells indicate truncation). . . . . . . . . . . . . 475 Oversampler operating modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 ADC interrupts per each ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 DELAY bits versus ADC resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 ADC global register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 ADC register map and reset values (master and slave ADC DocID024597 Rev 1 45/1680 49 List of tables Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142. Table 143. Table 144. Table 145. Table 146. Table 147. Table 148. 46/1680 RM0351 common registers) offset =0x300) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 DAC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 Sample and refresh timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 Channel output modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 Effect of low power modes on DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 VREFBUF buffer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 VREFBUF register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 COMP1 input plus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 COMP1 input minus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 COMP2 input plus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 COMP2 input minus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 COMP register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 Operational amplifier possible connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 Operating modes and calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 Effect of low-power modes on the OPAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 OPAMP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 DFSDM external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 DFSDM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 DFSDM triggers connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 Filter maximum output resolution (peak data values from filter output) for some FOSR values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 Integrator maximum output resolution (peak data values from integrator output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . . 613 DFSDM interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 DFSDM register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 DFSDMx register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 Example of frame rate calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 Blink frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662 Remapping capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 LCD behavior in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 LCD interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 LCD register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 Acquisition sequence summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 Spread spectrum deviation versus AHB clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . 688 I/O state depending on its mode and IODEF bit value . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 Capacitive sensing GPIOs available on STM32L4x6 devices . . . . . . . . . . . . . . . . . . . . . 691 Effect of low-power modes on TSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 TSC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 RNG register map and reset map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 Processing time (in clock cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 Processing time (in clock cycle) for ECB, CBC and CTR . . . . . . . . . . . . . . . . . . . . . . . . . 729 Processing time (in clock cycle) for GCM and CMAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 AES interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730 AES register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 Behavior of timer outputs versus BRK/BRK2 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811 Output control bits for complementary OCx and OCxN channels with break feature . . . . 825 TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844 DocID024597 Rev 1 RM0351 Table 149. Table 150. Table 151. Table 152. Table 153. Table 154. Table 155. Table 156. Table 157. Table 158. Table 159. Table 160. Table 161. Table 162. Table 163. Table 164. Table 165. Table 166. Table 167. Table 168. Table 169. Table 170. Table 171. Table 172. Table 173. Table 174. Table 175. Table 176. Table 177. Table 178. Table 179. Table 180. Table 181. Table 182. Table 183. Table 184. Table 185. Table 186. Table 187. Table 188. Table 189. Table 190. Table 191. Table 192. Table 193. Table 194. Table 195. Table 196. Table 197. List of tables TIM8 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901 Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913 TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 920 TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962 Output control bits for complementary OCx and OCxN channels with break feature . . . . 971 TIM15 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979 Output control bits for complementary OCx and OCxN channels with break feature . . . . 991 TIM16&TIM17 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001 TIM6/TIM7 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015 STM32L4xx LPTIM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016 Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019 Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024 LPTIM external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031 LPTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036 IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045 WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051 RTC pin PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055 RTC_OUT mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056 Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096 STM32L4x6 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099 Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103 I2C-SMBUS specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106 I2C configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110 I2C-SMBUS specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120 Examples of timings settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131 Examples of timings settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131 Examples of timings settings for fI2CCLK = 48 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132 SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134 SMBUS with PEC configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136 Examples of TIMEOUTA settings for various I2CCLK frequencies (max tTIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137 Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . . . . . . . . . . . . . 1138 Examples of TIMEOUTA settings for various I2CCLK frequencies (max tIDLE = 50 µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149 I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149 I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166 STM32L4x6 USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170 Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182 Error calculation for programmed baud rates at fCK = 72MHz in both cases of oversampling by 16 or by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185 Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . 1187 Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . . . . . . . . . 1187 Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191 Effect of low-power modes on the USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209 USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210 USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233 Error calculation for programmed baudrates at fck = 32,768 KHz . . . . . . . . . . . . . . . . . 1247 DocID024597 Rev 1 47/1680 49 List of tables Table 198. Table 199. Table 200. Table 201. Table 202. Table 203. Table 204. Table 205. Table 206. Table 207. Table 208. Table 209. Table 210. Table 211. Table 212. Table 213. Table 214. Table 215. Table 216. Table 217. Table 218. Table 219. Table 220. Table 221. Table 222. Table 223. Table 224. Table 225. Table 226. Table 227. Table 228. Table 229. Table 230. Table 231. Table 232. Table 233. Table 234. Table 235. Table 236. Table 237. Table 238. Table 239. Table 240. Table 241. Table 242. Table 243. Table 244. Table 245. Table 246. Table 247. Table 248. Table 249. 48/1680 RM0351 Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249 Effect of low-power modes on the LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255 LPUART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256 LPUART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272 STM32L4x6 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274 SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1298 SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307 External Synchronization Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313 Example of possible audio frequency sampling range . . . . . . . . . . . . . . . . . . . . . . . . . . 1319 SOPD pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1325 Parity bit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1325 Audio sampling frequency versus symbol rates (SHARK) . . . . . . . . . . . . . . . . . . . . . . . 1326 SAI interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336 SAI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1352 Effect of low-power modes on SWPMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370 Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371 Buffer modes selection for transmission/reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373 swpmi register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383 SDMMC I/O definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387 Command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1392 Short response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1393 Long response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1393 Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1393 Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396 DPSM flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1397 Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1398 Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1398 Card status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1409 SD status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412 Speed class code field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1413 Performance move field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414 AU_SIZE field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414 Maximum AU size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414 Erase size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1415 Erase timeout field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1415 Erase offset field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1415 Block-oriented write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418 Block-oriented write protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1419 Erase commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1419 I/O mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1419 Lock card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1420 Application-specific commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1420 R1 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421 R2 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421 R3 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1422 R4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1422 R4b response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1422 R5 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423 R6 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424 Response type and SDMMC_RESPx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1430 SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1439 Transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456 DocID024597 Rev 1 RM0351 Table 250. Table 251. Table 252. Table 253. Table 254. Table 255. Table 256. Table 257. Table 258. Table 259. Table 260. Table 261. Table 262. Table 263. Table 264. Table 265. Table 266. Table 267. Table 268. Table 269. Table 270. Table 271. Table 272. Table 273. Table 274. Table 275. Table 276. Table 277. List of tables Receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456 bxCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482 USB_OTG Implementation for STM32L4xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488 Core global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1509 Host-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510 Device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511 Data FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1513 Power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1513 Minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1556 OTG_FS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639 JTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . 1645 Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646 ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647 DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648 Cortex®-M4 AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649 Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650 Main ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652 Main ETM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654 Asynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662 Synchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1663 Flexible TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1663 Important TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1667 DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1679 DocID024597 Rev 1 49/1680 49 List of figures RM0351 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. 50/1680 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Sequential 16 bits instructions execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Changing the Read protection (RDP) level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 STM32L4x6 firewall connection schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Firewall functional states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Brown-out reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Low-power modes possible transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Frequency measurement with TIM15 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Frequency measurement with TIM16 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Frequency measurement with TIM17 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Basic structure of a five-volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 DMA1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 DMA2 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Configurable interrupt/event block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 FMC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 FMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 Mode1 read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 Mode1 write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 ModeA read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 ModeA write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 Mode2 and mode B read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Mode2 write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 ModeB write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 ModeC read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 ModeC write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 ModeD read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 ModeD write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 Muxed read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Muxed write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Asynchronous wait during a read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Asynchronous wait during a write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Wait configuration waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . . . . . . . . 372 Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . . . . . . . . . . . . . 374 DocID024597 Rev 1 RM0351 Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. List of figures NAND Flash controller waveforms for common memory access . . . . . . . . . . . . . . . . . . . 386 Access to non ‘CE don’t care’ NAND-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 QUADSPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 An example of a read command in quad mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 An example of a DDR command in quad mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 nCS when CKMODE = 0 (T = CLK period). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 nCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 409 nCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 409 nCS when CKMODE = 1 with an abort (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . . 409 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 ADC1 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 ADC2 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 ADC3 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 Updating the ADC calibration factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 Mixing single-ended and differential channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 Enabling / Disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 Analog to digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 Stopping ongoing regular conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 Stopping ongoing regular and injected conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 Triggers are shared between ADC master and ADC slave . . . . . . . . . . . . . . . . . . . . . . . 446 Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 Example of JSQR queue of context (sequence change) . . . . . . . . . . . . . . . . . . . . . . . . . 451 Example of JSQR queue of context (trigger change) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 Example of JSQR queue of context with overflow before conversion . . . . . . . . . . . . . . . 452 Example of JSQR queue of context with overflow during conversion . . . . . . . . . . . . . . . 452 Example of JSQR queue of context with empty queue (case JQM=0). . . . . . . . . . . . . . . 453 Example of JSQR queue of context with empty queue (case JQM=1). . . . . . . . . . . . . . . 453 Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion. . . . . . . . . . . . . . . . . . . . . . . 454 Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion and a new trigger occurs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs outside an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . 455 Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . . . . . . . . . . . . . . . 455 Flushing JSQR queue of context by setting ADDIS=1 (JQM=0). . . . . . . . . . . . . . . . . . . . 456 Flushing JSQR queue of context by setting ADDIS=1 (JQM=1). . . . . . . . . . . . . . . . . . . . 456 Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 458 Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 459 Right alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 Right alignment (offset enabled, signed value). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 Left alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 Left alignment (offset enabled, signed value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 AUTODLY=1, regular conversion in continuous mode, software trigger . . . . . . . . . . . . . 466 AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=0; JDISCEN=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 AUTODLY=1, regular HW conversions interrupted by injected conversions . . . . . . . . . . . . . DocID024597 Rev 1 51/1680 60 List of figures Figure 96. Figure 97. Figure 98. Figure 99. Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. Figure 109. Figure 110. Figure 111. Figure 112. Figure 113. Figure 114. Figure 115. Figure 116. Figure 117. Figure 118. Figure 119. Figure 120. Figure 121. Figure 122. Figure 123. Figure 124. Figure 125. Figure 126. Figure 127. Figure 128. Figure 129. Figure 130. Figure 131. Figure 132. Figure 133. Figure 134. Figure 135. Figure 136. Figure 137. Figure 138. Figure 139. Figure 140. Figure 141. Figure 142. Figure 143. Figure 144. 52/1680 RM0351 (DISCEN=1, JDISCEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 AUTODLY=1, regular continuous conversions interrupted by injected conversions . . . . 469 AUTODLY=1 in auto- injected mode (JAUTO=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 Analog watchdog’s guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 ADCy_AWDx_OUT signal generation (on all regular channels). . . . . . . . . . . . . . . . . . . . 472 ADCy_AWDx_OUT signal generation (AWDx flag not cleared by SW) . . . . . . . . . . . . . . 473 ADCy_AWDx_OUT signal generation (on a single regular channel) . . . . . . . . . . . . . . . . 473 ADCy_AWDx_OUT signal generation (on all injected channels) . . . . . . . . . . . . . . . . . . . 473 20-bit to 16-bit result truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 Numerical example with 5-bits shift and rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 Triggered regular oversampling mode (TROVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 476 Regular oversampling modes (4x ratio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 Regular and injected oversampling modes used simultaneously . . . . . . . . . . . . . . . . . . . 478 Triggered regular oversampling with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 Oversampling in auto-injected mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 Dual ADC block diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 Injected simultaneous mode on 4 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . . 482 Regular simultaneous mode on 16 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . 484 Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode. . . . . . 486 Interleaved mode on 1 channel in single conversion mode: dual ADC mode. . . . . . . . . . 486 Interleaved conversion with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 Alternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . . . . . . . . . 489 Alternate + regular simultaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . . . . . . . . . . . . 491 Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 1: Master interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 2: Slave interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 DMA Requests in regular simultaneous mode when MDMA=0b00 . . . . . . . . . . . . . . . . . 492 DMA requests in regular simultaneous mode when MDMA=0b10 . . . . . . . . . . . . . . . . . . 493 DMA requests in interleaved mode when MDMA=0b10 . . . . . . . . . . . . . . . . . . . . . . . . . . 493 Temperature sensor channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 VBAT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 DAC channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 541 DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 543 DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 544 DAC sample and hold mode phases diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 Comparators block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 Window mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 Comparator hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 Comparator output blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 Standalone mode: external gain setting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 Follower configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . . . . . . . . . 586 DocID024597 Rev 1 RM0351 List of figures Figure 145. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 Figure 146. Single DFSDM block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 Figure 147. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 Figure 148. Clock absence timing diagram for SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 Figure 149. Clock absence timing diagram for Manchester coding . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 Figure 150. First conversion for Manchester coding (Manchester synchronization) . . . . . . . . . . . . . . 607 Figure 151. DFSDM_CHDATINyR registers operation modes and assignment . . . . . . . . . . . . . . . . . 611 Figure 152. Example: Sinc3 filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 Figure 153. LCD controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 Figure 154. 1/3 bias, 1/4 duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 Figure 155. Static duty case 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 Figure 156. Static duty case 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 Figure 157. 1/2 duty, 1/2 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 Figure 158. 1/3 duty, 1/3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 Figure 159. 1/4 duty, 1/3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 Figure 160. 1/8 duty, 1/4 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 Figure 161. VLCD pin for 1/2 1/3 1/4 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 Figure 162. Deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 Figure 163. SEG/COM mux feature example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 Figure 164. Flowchart example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 Figure 165. TSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 Figure 166. Surface charge transfer analog I/O group structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 Figure 167. Sampling capacitor voltage variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 Figure 168. Charge transfer acquisition sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 Figure 169. Spread spectrum variation principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 Figure 170. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 Figure 171. AES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 Figure 172. ECB encryption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 Figure 173. ECB decryption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 Figure 174. CBC mode encryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 Figure 175. CBC mode decryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 Figure 176. Example of suspend mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 Figure 177. CTR mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 Figure 178. CTR mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 Figure 179. 32-bit counter + nonce organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 Figure 180. 128-bit block construction according to the data type. . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 Figure 181. 128-bit block construction according to the data type (continued) . . . . . . . . . . . . . . . . . . 724 Figure 182. Mode 1: encryption with 128-bit key length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 Figure 183. Mode 2: key derivation with 128-bit key length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 Figure 184. Mode 3: decryption with 128-bit key length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 Figure 185. Mode 4: key derivation and decryption with 128-bit key length . . . . . . . . . . . . . . . . . . . . 727 Figure 186. DMA requests and data transfers during Input phase (AES_IN) . . . . . . . . . . . . . . . . . . . 728 Figure 187. DMA requests during Output phase (AES_OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 Figure 188. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 Figure 189. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 748 Figure 190. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 748 Figure 191. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 Figure 192. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 Figure 193. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 Figure 194. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 Figure 195. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 752 DocID024597 Rev 1 53/1680 60 List of figures Figure 196. Figure 197. Figure 198. Figure 199. Figure 200. Figure 201. Figure 202. Figure 203. Figure 204. Figure 205. Figure 206. Figure 207. Figure 208. Figure 209. Figure 210. Figure 211. Figure 212. Figure 213. Figure 214. Figure 215. Figure 216. Figure 217. Figure 218. Figure 219. Figure 220. Figure 221. Figure 222. Figure 223. Figure 224. Figure 225. Figure 226. Figure 227. Figure 228. Figure 229. Figure 230. Figure 231. Figure 232. Figure 233. Figure 234. Figure 235. Figure 236. Figure 237. Figure 238. Figure 239. Figure 240. Figure 241. Figure 242. Figure 243. Figure 244. Figure 245. Figure 246. Figure 247. 54/1680 RM0351 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 752 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 756 Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 757 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 758 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 759 Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 760 Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 761 External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 TIM1 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 TIM8 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 764 TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 768 Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . . . . . . . . . 769 Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 770 Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . . 770 PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . . 778 Combined PWM mode on channel 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 3-phase combined PWM signals with multiple trigger pulses per period . . . . . . . . . . . . . 780 Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . . 781 Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 782 Break and Break2 circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784 Various output behavior in response to a break event on BRK (OSSI = 1) . . . . . . . . . . . 786 PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . . . . . . . . . . . . 787 PWM output state following BRK assertion (OSSI=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 788 Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788 Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 794 Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 795 Measuring time interval between edges on 3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796 Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799 Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801 DocID024597 Rev 1 RM0351 Figure 248. Figure 249. Figure 250. Figure 251. Figure 252. Figure 253. Figure 254. Figure 255. Figure 256. Figure 257. Figure 258. Figure 259. Figure 260. Figure 261. Figure 262. Figure 263. Figure 264. Figure 265. Figure 266. Figure 267. Figure 268. Figure 269. Figure 270. Figure 271. Figure 272. Figure 273. Figure 274. Figure 275. Figure 276. Figure 277. Figure 278. Figure 279. Figure 280. Figure 281. Figure 282. Figure 283. Figure 284. Figure 285. Figure 286. Figure 287. Figure 288. Figure 289. Figure 290. Figure 291. Figure 292. Figure 293. Figure 294. Figure 295. Figure 296. Figure 297. Figure 298. List of figures Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 802 General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 853 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 853 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856 Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 856 Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 857 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 Counter timing diagram, Update event when repetition counter is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 861 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 862 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863 Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 863 Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 864 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 865 TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 869 Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869 Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 870 PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872 Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874 Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875 Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877 Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . . 878 Combined PWM mode on channels 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879 Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880 Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881 Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 884 Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 884 Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886 Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887 Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888 Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 889 Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889 Gating TIM2 with OC1REF of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890 Gating TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891 Triggering TIM2 with update of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892 Triggering TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892 Triggering TIM3 and TIM2 with TIM3 TI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893 TIM15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 TIM16 and TIM17 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926 DocID024597 Rev 1 55/1680 60 List of figures Figure 299. Figure 300. Figure 301. Figure 302. Figure 303. Figure 304. Figure 305. Figure 306. Figure 307. Figure 308. Figure 309. Figure 310. Figure 311. Figure 312. Figure 313. Figure 314. Figure 315. Figure 316. Figure 317. Figure 318. Figure 319. Figure 320. Figure 321. Figure 322. Figure 323. Figure 324. Figure 325. Figure 326. Figure 327. Figure 328. Figure 329. Figure 330. Figure 331. Figure 332. Figure 333. Figure 334. Figure 335. Figure 336. Figure 337. Figure 338. Figure 339. Figure 340. Figure 341. Figure 342. Figure 343. Figure 344. Figure 345. Figure 346. 56/1680 RM0351 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 928 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 928 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931 Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932 Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 934 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 935 TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935 Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936 Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 937 Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937 Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 938 Output stage of capture/compare channel (channel 2 for TIM15) . . . . . . . . . . . . . . . . . . 938 PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940 Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942 Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943 Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944 Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945 Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 946 Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 946 Break circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948 Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950 Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951 Measuring time interval between edges on 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953 Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954 Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955 Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956 Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1005 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1005 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008 Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1010 Low-power timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022 Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025 IR internal hardware connections with TIM16 and TIM17 . . . . . . . . . . . . . . . . . . . . . . . 1037 Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038 Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047 Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048 DocID024597 Rev 1 RM0351 Figure 347. Figure 348. Figure 349. Figure 350. Figure 351. Figure 352. Figure 353. Figure 354. Figure 355. Figure 356. Figure 357. Figure 358. Figure 359. Figure 360. Figure 361. Figure 362. Figure 363. Figure 364. Figure 365. Figure 366. Figure 367. Figure 368. Figure 369. Figure 370. Figure 371. Figure 372. Figure 373. Figure 374. Figure 375. Figure 376. Figure 377. Figure 378. Figure 379. Figure 380. Figure 381. Figure 382. Figure 383. Figure 384. Figure 385. Figure 386. Figure 387. Figure 388. Figure 389. Figure 390. Figure 391. Figure 392. Figure 393. Figure 394. Figure 395. Figure 396. Figure 397. Figure 398. List of figures RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054 I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1102 Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104 I2C initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107 Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108 Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1109 Slave initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112 Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0. . . . . . . . . . . . 1114 Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=1. . . . . . . . . . . . 1115 Transfer bus diagrams for I2C slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1116 Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . . . . . . . . . . . 1117 Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . . . . . . . . . . . 1118 Transfer bus diagrams for I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118 Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120 Master initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122 10-bit address read access with HEAD10R=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122 10-bit address read access with HEAD10R=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123 Transfer sequence flowchart for I2C master transmitter for N≤255 bytes . . . . . . . . . . . 1124 Transfer sequence flowchart for I2C master transmitter for N>255 bytes . . . . . . . . . . . 1125 Transfer bus diagrams for I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126 Transfer sequence flowchart for I2C master receiver for N≤255 bytes. . . . . . . . . . . . . . 1128 Transfer sequence flowchart for I2C master receiver for N >255 bytes . . . . . . . . . . . . . 1129 Transfer bus diagrams for I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130 Timeout intervals for tLOW:SEXT, tLOW:MEXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135 Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . 1139 Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . 1139 Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . . . . . . . . . 1141 Bus transfer diagrams for SMBus slave receiver (SBC=1) . . . . . . . . . . . . . . . . . . . . . . 1142 Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143 Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145 I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150 USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172 Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174 Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175 TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177 Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178 Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182 Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182 Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189 Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190 Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . 1193 Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . 1194 USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195 USART data clock timing diagram (M bits = 00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195 USART data clock timing diagram (M bits = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196 RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196 ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198 Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199 IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203 IrDA data modulation (3/16) -Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203 Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205 DocID024597 Rev 1 57/1680 60 List of figures Figure 399. Figure 400. Figure 401. Figure 402. Figure 403. Figure 404. Figure 405. Figure 406. Figure 407. Figure 408. Figure 409. Figure 410. Figure 411. Figure 412. Figure 413. Figure 414. Figure 415. Figure 416. Figure 417. Figure 418. Figure 419. Figure 420. Figure 421. Figure 422. Figure 423. Figure 424. Figure 425. Figure 426. Figure 427. Figure 428. Figure 429. Figure 430. Figure 431. Figure 432. Figure 433. Figure 434. Figure 435. Figure 436. Figure 437. Figure 438. Figure 439. Figure 440. Figure 441. Figure 442. Figure 443. Figure 444. Figure 445. Figure 446. Figure 447. Figure 448. 58/1680 RM0351 Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1206 Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1206 RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207 RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208 USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211 LPUART Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238 Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240 Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241 TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243 Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248 Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249 Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251 Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252 Hardware flow control between 2 LPUARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253 RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253 RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254 LPUART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257 SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274 Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275 Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276 Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277 Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278 Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279 Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281 Data alignment when data length is not equal to 8-bit or 16-bit . . . . . . . . . . . . . . . . . . . 1282 Packing data in FIFO for transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . 1286 Master full duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289 Slave full duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290 Master full duplex communication with CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291 Master full duplex communication in packed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292 NSSP pulse generation in Motorola SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 1295 TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310 Audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313 FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . . . . . . . 1315 FS role is start of frame (FSDEF = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1316 Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . . . . . . . . . . . . . . . . . . . . . 1317 First bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1317 Audio block clock generator overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1318 AC’97 audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1322 Example of typical AC’97 configuration on devices featuring at least 2 embedded SAIs (three external AC’97 decoders) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1323 SPDIF format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1324 SAI_xDR register ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1325 Data companding hardware in an audio block in the SAI . . . . . . . . . . . . . . . . . . . . . . . . 1328 Tristate strategy on SD output line on an inactive slot . . . . . . . . . . . . . . . . . . . . . . . . . . 1330 Tristate on output data line in a protocol like I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1331 Overrun detection error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1332 FIFO underrun event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1332 S1 signal coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354 S2 signal coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354 DocID024597 Rev 1 RM0351 Figure 449. Figure 450. Figure 451. Figure 452. Figure 453. Figure 454. Figure 455. Figure 456. Figure 457. Figure 458. Figure 459. Figure 460. Figure 461. Figure 462. Figure 463. Figure 464. Figure 465. Figure 466. Figure 467. Figure 468. Figure 469. Figure 470. Figure 471. Figure 472. Figure 473. Figure 474. Figure 475. Figure 476. Figure 477. Figure 478. Figure 479. Figure 480. Figure 481. Figure 482. Figure 483. Figure 484. Figure 485. Figure 486. Figure 487. Figure 488. Figure 489. Figure 490. Figure 491. Figure 492. Figure 493. Figure 494. Figure 495. Figure 496. Figure 497. Figure 498. Figure 499. Figure 500. List of figures SWPMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356 SWP bus states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358 SWP frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1359 SWPMI No software buffer mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1360 SWPMI No software buffer mode transmission, consecutive frames . . . . . . . . . . . . . . . 1361 SWPMI Multi software buffer mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363 SWPMI No software buffer mode reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364 SWPMI single software buffer mode reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366 SWPMI Multi software buffer mode reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368 SWPMI single buffer mode reception with CRC error. . . . . . . . . . . . . . . . . . . . . . . . . . . 1369 “No response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385 (Multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385 (Multiple) block write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385 Sequential read operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386 Sequential write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386 SDMMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386 SDMMC adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388 Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1389 SDMMC_CK clock dephasing (BYPASS = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1390 SDMMC adapter command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1390 Command path state machine (SDMMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1391 SDMMC command transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1392 Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394 Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395 CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1443 bxCAN operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446 bxCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447 bxCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447 bxCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1448 Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1449 Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1450 Filter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . 1453 Example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454 Filtering mechanism - example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455 CAN error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458 CAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1459 Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1460 Can mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1472 OTG full-speed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489 OTG_FS A-B device connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491 USB_FS peripheral-only connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493 USB_FS host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497 SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . . . . . . . . . . . . 1501 Updating OTG_HFIR dynamically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1503 Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . 1504 Host-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . . 1505 Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1508 Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588 Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1589 Normal bulk/control OUT/SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1590 Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1594 DocID024597 Rev 1 59/1680 60 List of figures Figure 501. Figure 502. Figure 503. Figure 504. Figure 505. Figure 506. Figure 507. Figure 508. Figure 509. Figure 510. Figure 511. Figure 512. Figure 513. Figure 514. Figure 515. Figure 516. 60/1680 RM0351 Normal interrupt OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1597 Normal interrupt IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1601 Isochronous OUT transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603 Isochronous IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606 Receive FIFO packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1611 Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613 Bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619 TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629 A-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1630 B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631 A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632 B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634 Block diagram of STM32 MCU and Cortex®-M4-level debug support . . . . . . . . . . . . . . 1636 SWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1638 JTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642 TPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662 DocID024597 Rev 1 RM0351 Documentation conventions 1 Documentation conventions 1.1 List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to these bits. read-only (r) Software can only read these bits. write-only (w) Software can only write to this bit. Reading the bit returns the reset value. read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on the bit value. read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on the bit value. read/clear by read (rc_r) Software can read this bit. Reading this bit automatically clears it to ‘0’. Writing ‘0’ has no effect on the bit value. read/set (rs) Software can read as well as set this bit. Writing ‘0’ has no effect on the bit value. Reserved (Res.) Reserved bit, must be kept at reset value. 1.2 Glossary This section gives a brief definition of acronyms and abbreviations used in this document: • Word: data of 32-bit length. • Half-word: data of 16-bit length. • Byte: data of 8-bit length. • IAP (in-application programming): IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running. • ICP (in-circuit programming): ICP is the ability to program the Flash memory of a microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the device is mounted on the user application board. • Option bytes: product configuration bits stored in the Flash memory. • OBL: option byte loader. • AHB: advanced high-performance bus. • APB: advanced peripheral bus. DocID024597 Rev 1 61/1680 62 Documentation conventions 1.3 RM0351 Peripheral availability For peripheral availability and number across all sales types, please refer to the particular device datasheet. 62/1680 DocID024597 Rev 1 RM0351 System and memory overview 2 System and memory overview 2.1 System architecture The main system consists of 32-bit multilayer AHB bus matrix that interconnects: • • Five masters: – Cortex®-M4 with FPU core I-bus – Cortex®-M4 with FPU core D-bus – Cortex®-M4 with FPU core S-bus – DMA1 – DMA2 Seven slaves: – Internal Flash memory on the ICode bus – Internal Flash memory on DCode bus – Internal SRAM1 (96 KB) – Internal SRAM2 (32 KB) – AHB1 peripherals including AHB to APB bridges and APB peripherals (connected to APB1 and APB2) – AHB2 peripherals – The external memory controllers (FMC and QUADSPI). The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. This architecture is shown in Figure 1: DocID024597 Rev 1 63/1680 65 System and memory overview RM0351 Figure 1. System architecture $50 '0$ '0$ 6 6 &RUWH[ 0ZLWK)38 6 6 6 0 ,&RGH $&&(/ )/$6+ 0% 0 '&RGH 0 65$0 0 65$0 0 $+% SHULSKHUDOV 0 $+% SHULSKHUDOV 0 )0& DQG 48$'63, %XV0DWUL[6 069 2.1.1 S0: I-bus This bus connects the instruction bus of the Cortex®-M4 core to the BusMatrix. This bus is used by the core to fetch instructions. The targets of this bus are the internal Flash memory, SRAM1, SRAM2 and external memories through FMC or QUADSPI. 2.1.2 S1: D-bus This bus connects the data bus of the Cortex®-M4 core to the BusMatrix. This bus is used by the core for literal load and debug access. The targets of this bus are the internal Flash memory, SRAM1, SRAM2 and external memories through FMC or QUADSPI. 64/1680 DocID024597 Rev 1 RM0351 2.1.3 System and memory overview S2: S-bus This bus connects the system bus of the Cortex®-M4 core to the BusMatrix. This bus is used by the core to access data located in a peripheral or SRAM area. The targets of this bus are the SRAM1, the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the external memories through the FMC or QUADSPI. 2.1.4 S3, S4: DMA-bus This bus connects the AHB master interface of the DMA to the BusMatrix.The targets of this bus are the SRAM1 and SRAM2, the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the external memories through the FMC or QUADSPI. 2.1.5 BusMatrix The BusMatrix manages the access arbitration between Masters. The arbitration uses a Round Robin algorithm. The BusMatrix is composed of five masters (CPU AHB, System bus, DCode bus, ICode bus, DMA1 and DMA2 bus) and seven slaves (FLASH, SRAM1, SRAM2, AHB1 (including APB1 and APB2), AHB2 and FMC/QUADSPI). AHB/APB bridges The two AHB/APB bridges provide full synchronous connections between the AHB and the 2 APB buses, allowing flexible selection of the peripheral frequency. Refer to Section 2.2.2: Memory map and register boundary addresses on page 68 for the address mapping of the peripherals connected to this bridge. After each device reset, all peripheral clocks are disabled (except for the SRAM1/2 and Flash memory interface). Before using a peripheral you have to enable its clock in the RCC_AHBxENR and the RCC_APBxENR registers. Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector. DocID024597 Rev 1 65/1680 65 RM0351 2.2 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant. The addressable memory space is divided into 8 main blocks, of 512 Mbyte each. 66/1680 DocID024597 Rev 1 RM0351 Figure 2. Memory map [)))))))) [%))))))) &RUWH[0 ZLWK)38 ,QWHUQDO 3HULSKHUDOV 5HVHUYHG [$ 48$'63,UHJLVWHUV [$ )0&UHJLVWHUV [$ [( [))))))) 5HVHUYHG [& $+% [ [& 5HVHUYHG [ )0&DQG 48$'63, UHJLVWHUV $+% [ [ [$ 48$'63,)ODVK EDQN [ )0&EDQN [ [ 5HVHUYHG $3% 5HVHUYHG [ $3% [))))))) [ 5HVHUYHG [)))) 2SWLRQ%\WHV [ [)))) )0&EDQN 5HVHUYHG [)))) 6\VWHPPHPRU\ [ [))) [))) [))) 5HVHUYHG 2SWLRQV%\WHV 5HVHUYHG [))) 3HULSKHUDOV [ 273DUHD [))) 6\VWHPPHPRU\ [))) [ 65$0 5HVHUYHG [ 65$0 [ 5HVHUYHG &2'( [ )ODVKPHPRU\ [ [ [ 5HVHUYHG [ 5HVHUYHG )ODVKV\VWHPPHPRU\ RU65$0GHSHQGLQJRQ %227FRQILJXUDWLRQ 069 It is forbidden to access QUADSPI Flash bank area before having properly configured and enabled the QUADSPI peripheral. DocID024597 Rev 1 67/1680 77 RM0351 All the memory areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, please refer to the Memory map and register boundary addresses chapter and peripheral chapters. 2.2.2 Memory map and register boundary addresses See the datasheet corresponding to your device for a comprehensive diagram of the memory map. The following table gives the boundary addresses of the peripherals available in the devices. Table 1. STM32L4x6 memory map and peripheral register boundary addresses Bus Boundary address Size (bytes) Peripheral Section 24.4.4: RNG register map 0x5006 0800 - 0x5006 0BFF 1 KB RNG 0x5006 0400 - 0x5006 07FF 1 KB Reserved 0x5006 0000 - 0x5006 03FF 1 KB AES 0x5004 0400 - 0x5005 FFFF 127 KB 0x5004 0000 - 0x5004 03FF 1 KB ADC Section 16.6.4: ADC register map 0x5000 0000 - 0x5003 FFFF 16 KB OTG_FS Section 43.15.54: OTG_FS register map 0x4800 2000 - 0x4FFF FFFF ~127 MB Reserved 0x4800 1C00 - 0x4800 1FFF 1 KB GPIOH Section 9.4.13: GPIO register map 0x4800 1800 - 0x4800 1BFF 1 KB GPIOG Section 9.4.13: GPIO register map 0x4800 1400 - 0x4800 17FF 1 KB GPIOF Section 9.4.13: GPIO register map 0x4800 1000 - 0x4800 13FF 1 KB GPIOE Section 9.4.13: GPIO register map 0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD Section 9.4.13: GPIO register map 0x4800 0800 - 0x4800 0BFF 1 KB GPIOC Section 9.4.13: GPIO register map 0x4800 0400 - 0x4800 07FF 1 KB GPIOB Section 9.4.13: GPIO register map 0x4800 0000 - 0x4800 03FF 1 KB GPIOA Section 9.4.13: GPIO register map 0x4002 4400 - 0x47FF FFFF ~127 MB Reserved AHB2 68/1680 Peripheral register map Reserved DocID024597 Rev 1 Section 25.14.18: AES register map - - - RM0351 Table 1. STM32L4x6 memory map and peripheral register boundary addresses (continued) Bus AHB1 APB2 Boundary address Size (bytes) Peripheral Peripheral register map Section 23.6.11: TSC register map 0x4002 4000 - 0x4002 43FF 1 KB TSC 0x4002 3400 - 0x4002 3FFF 1 KB Reserved 0x4002 3000 - 0x4002 33FF 1 KB CRC 0x4002 2400 - 0x4002 2FFF 3 KB Reserved 0x4002 2000 - 0x4002 23FF 1 KB FLASH registers 0x4002 1400 - 0x4002 1FFF 3 KB Reserved 0x4002 1000 - 0x4002 13FF 1 KB RCC 0x4002 0800 - 0x4002 0FFF 2 KB Reserved 0x4002 0400 - 0x4002 07FF 1 KB DMA2 Section 11.5.9: DMA register map 0x4002 0000 - 0x4002 03FF 1 KB DMA1 Section 11.5.9: DMA register map 0x4001 6400 - 0x4001 FFFF 39 KB Reserved 0x4001 6000 - 0x4000 63FF 1 KB DFSDM 0x4001 5C00 - 0x4000 5FFF 1 KB Reserved 0x4001 5800 - 0x4000 5BFF 1 KB SAI2 Section 39.5.10: SAI register map 0x4001 5400 - 0x4000 57FF 1 KB SAI1 Section 39.5.10: SAI register map 0x4001 4C00 - 0x4000 53FF 2 KB Reserved DocID024597 Rev 1 Section 5.4.6: CRC register map Section 3.7.17: FLASH register map Section 8.4.31: RCC register map - Section 21.8: DFSDM register map - - 69/1680 77 RM0351 Table 1. STM32L4x6 memory map and peripheral register boundary addresses (continued) Bus Boundary address Size (bytes) Peripheral 0x4001 4800 - 0x4001 4BFF 1 KB TIM17 Section 28.6.20: TIM16&TIM17 register map 0x4001 4400 - 0x4001 47FF 1 KB TIM16 Section 28.6.20: TIM16&TIM17 register map 0x4001 4000 - 0x4001 43FF 1 KB TIM15 Section 28.6.20: TIM16&TIM17 register map 0x4001 3C00 - 0x4001 3FFF 1 KB Reserved 0x4001 3800 - 0x4001 3BFF 1 KB USART1 Section 36.8.12: USART register map 0x4001 3400 - 0x4001 37FF 1 KB TIM8 Section 26.4.31: TIM8 register map 0x4001 3000 - 0x4001 33FF 1 KB SPI1 Section 38.6.8: SPI register map 0x4001 2C00 - 0x4001 2FFF 1 KB TIM1 Section 26.4.30: TIM1 register map 0x4001 2800 - 0x4001 2BFF 1 KB SDMMC1 Section 41.8.16: SDMMC register map 0x4001 2000 - 0x4001 27FF 2 KB Reserved 0x4001 1C00 - 0x4001 1FFF 1 KB FIREWALL 0x4001 0800- 0x4001 1BFF 5 KB Reserved 0x4001 0400 - 0x4001 07FF 1 KB EXTI Section 13.5.13: EXTI register map COMP Section 19.6.3: COMP register map VREFBUF Section 18.3.3: VREFBUF register map SYSCFG Section 10.2.11: SYSCFG register map APB2 0x4001 0200 - 0x4001 03FF 0x4001 0030 - 0x4001 01FF 0x4001 0000 - 0x4001 002F 70/1680 Peripheral register map 1 KB DocID024597 Rev 1 - Section 4.4.8: Firewall register map - RM0351 Table 1. STM32L4x6 memory map and peripheral register boundary addresses (continued) Bus Boundary address Size (bytes) Peripheral Peripheral register map 0x4000 9800 - 0x4000 FFFF 26 KB Reserved 0x4000 9400 - 0x4000 97FF 1 KB LPTIM2 0x4000 8C00 - 0x4000 93FF 2 KB Reserved 0x4000 8800 - 0x4000 8BFF 1 KB SWPMI1 0x4000 8400 - 0x4000 87FF 1 KB Reserved 0x4000 8000 - 0x4000 83FF 1 KB LPUART1 Section 37.7.10: LPUART register map 0x4000 7C00 - 0x4000 7FFF 1 KB LPTIM1 Section 30.6.11: LPTIM register map 0x4000 7800 - 0x4000 7BFF 1 KB OPAMP Section 20.5.7: OPAMP register map 0x4000 7400 - 0x4000 77FF 1 KB DAC1 Section 17.5.21: DAC register map 0x4000 7000 - 0x4000 73FF 1 KB PWR Section 6.4.24: PWR register map and reset value table 0x4000 6800 - 0x4000 6FFF 1 KB Reserved 0x4000 6400 - 0x4000 67FF 1 KB CAN1 0x4000 6000 - 0x4000 63FF 1 KB Reserved 0x4000 5C00- 0x4000 5FFF 1 KB I2C3 Section 35.7.12: I2C register map 0x4000 5800 - 0x4000 5BFF 1 KB I2C2 Section 35.7.12: I2C register map 0x4000 5400 - 0x4000 57FF 1 KB I2C1 Section 35.7.12: I2C register map APB1 DocID024597 Rev 1 Section 30.6.11: LPTIM register map Section 40.6.10: SWPMI register map and reset value table - Section 42.9.5: bxCAN register map - 71/1680 77 RM0351 Table 1. STM32L4x6 memory map and peripheral register boundary addresses (continued) Bus Boundary address Size (bytes) Peripheral 0x4000 5000 - 0x4000 53FF 1 KB UART5 Section 36.8.12: USART register map 0x4000 4C00 - 0x4000 4FFF 1 KB UART4 Section 36.8.12: USART register map 0x4000 4800 - 0x4000 4BFF 1 KB USART3 Section 36.8.12: USART register map 0x4000 4400 - 0x4000 47FF 1 KB USART2 Section 36.8.12: USART register map 0x4000 4000 - 0x4000 43FF 1 KB Reserved 0x4000 3C00 - 0x4000 3FFF 1 KB SPI3 Section 38.6.8: SPI register map 0x4000 3800 - 0x4000 3BFF 1 KB SPI2 Section 38.6.8: SPI register map 0x4000 3400 - 0x4000 37FF 1 KB Reserved 0x4000 3000 - 0x4000 33FF 1 KB IWDG Section 32.4.6: IWDG register map 0x4000 2C00 - 0x4000 2FFF 1 KB WWDG Section 33.4.4: WWDG register map 0x4000 2800 - 0x4000 2BFF 1 KB RTC Section 34.6.21: RTC register map 0x4000 2400 - 0x4000 27FF 1 KB LCD Section 22.6.6: LCD register map 0x4000 1800 - 0x4000 2400 3 KB Reserved 0x4000 1400 - 0x4000 17FF 1 KB TIM7 Section 29.4.9: TIM6/TIM7 register map 0x4000 1000 - 0x4000 13FF 1 KB TIM6 Section 29.4.9: TIM6/TIM7 register map 0x4000 0C00- 0x4000 0FFF 1 KB TIM5 Section 27.4.23: TIMx register map 0x4000 0800 - 0x4000 0BFF 1 KB TIM4 Section 27.4.23: TIMx register map 0x4000 0400 - 0x4000 07FF 1 KB TIM3 Section 27.4.23: TIMx register map 0x4000 0000 - 0x4000 03FF 1 KB TIM2 Section 27.4.23: TIMx register map APB1 2.2.3 Peripheral register map - - - Bit banding The Cortex®-M4 memory map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region. In the STM32L4x6 devices both the peripheral registers and the SRAM1 are mapped to a bit-band region, so that single bit-band write and read operations are allowed. The 72/1680 DocID024597 Rev 1 RM0351 operations are only available for Cortex®-M4 accesses, and not from other bus masters (e.g. DMA). A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is: bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4) where: – bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit – bit_band_base is the starting address of the alias region – byte_offset is the number of the byte in the bit-band region that contains the targeted bit – bit_number is the bit position (0-7) of the targeted bit Example The following example shows how to map bit 2 of the byte located at SRAM1 address 0x20000300 to the alias region: 0x22006008 = 0x22000000 + (0x300*32) + (2*4) Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit 2 of the byte at SRAM1 address 0x20000300. Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM1 address 0x20000300 (0x01: bit set; 0x00: bit reset). For more information on bit-banding, please refer to the Cortex®-M4 programming manual (see Related documents on page 1). 2.3 Embedded SRAM The STM32L4x6 devices feature up to 128 Kbyte SRAM: • Up to 96 Kbyte SRAM1. • 32 Kbyte SRAM2. These SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). These memories can be addressed at maximum system clock frequency without wait state and thus by both CPU and DMA. The CPU can access the SRAM1 through the System bus or through the ICode/DCode buses when boot from SRAM1 is selected or when physical remap is selected (Section 10.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller). To get the maximum performance on SRAM1 execution, physical remap should be selected (boot or software selection). Execution can be performed from SRAM2 with maximum performance without any remap thanks to access through ICode bus. 2.3.1 SRAM2 Parity check The user can enable the SRAM2 parity check using the option bit SRAM2_PE in the user option byte (refer to Section 3.4.1: Option bytes description). DocID024597 Rev 1 73/1680 77 RM0351 The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in order to increase memory robustness, as required for instance by Class B or SIL norms. The parity bits are computed and stored when writing into the SRAM2. Then, they are automatically checked when reading. If one bit fails, an NMI is generated. The same error can also be linked to the BRK_IN Break input of TIM1/TIM8/TIM15/TIM16/TIM17, with the SPL control bit in the SYSCFG configuration register 2 (SYSCFG_CFGR2). The SRAM2 Parity Error flag (SPF) is available in the SYSCFG configuration register 2 (SYSCFG_CFGR2). Note: When enabling the RAM parity check, it is advised to initialize by software the whole RAM memory at the beginning of the code, to avoid getting parity errors when reading noninitialized locations. 2.3.2 SRAM2 Write protection The SRAM2 can be write protected with a page granularity of 1 KByte. Table 2. SRAM2 organization 74/1680 Page number Start address End address Page 0 0x1000 0000 0x1000 03FF Page 1 0x1000 0400 0x1000 07FF Page 2 0x1000 0800 0x1000 0BFF Page 3 0x1000 0C00 0x1000 0FFF Page 4 0x1000 1000 0x1000 13FF Page 5 0x1000 1400 0x1000 17FF Page 6 0x1000 1800 0x1000 1BFF Page 7 0x1000 1C00 0x1000 1FFF Page 8 0x1000 2000 0x1000 23FF Page 9 0x1000 2400 0x1000 27FF Page 10 0x1000 2800 0x1000 2BFF Page 11 0x1000 2C00 0x1000 2FFF Page 12 0x1000 3000 0x1000 33FF Page 13 0x1000 3400 0x1000 37FF Page 14 0x1000 3800 0x1000 3BFF Page 15 0x1000 3C00 0x1000 3FFF Page 16 0x1000 4000 0x1000 43FF Page 17 0x1000 4400 0x1000 47FF Page 18 0x1000 4800 0x1000 4BFF Page 19 0x1000 4C00 0x1000 4FFF Page 20 0x1000 5000 0x1000 53FF Page 21 0x1000 5400 0x1000 57FF Page 22 0x1000 5800 0x1000 5BFF DocID024597 Rev 1 RM0351 Table 2. SRAM2 organization (continued) Page number Start address End address Page 23 0x1000 5C00 0x1000 5FFF Page 24 0x1000 6000 0x1000 63FF Page 25 0x1000 6400 0x1000 67FF Page 26 0x1000 6800 0x1000 6BFF Page 27 0x1000 6C00 0x1000 6FFF Page 28 0x1000 7000 0x1000 73FF Page 29 0x1000 7400 0x1000 77FF Page 30 0x1000 7800 0x1000 7BFF Page 31 0x1000 7C00 0x1000 7FFF The write protection can be enabled in SYSCFG SRAM2 write protection register (SYSCFG_SWPR) in the SYSCFG block. This is a register with write ‘1’ once mechanism, which means by writing ‘1’ on a bit it will setup the write protection for that page of SRAM and it can be removed/cleared by a system reset only. 2.3.3 SRAM2 Read protection The SRAM2 is protected with the Read protection (RDP). Refer to Section 3.5.1: Read protection (RDP) for more details. 2.3.4 SRAM2 Erase The SRAM2 can be erased with a system reset using the option bit SRAM2_RST in the user option byte (refer to Section 3.4.1: Option bytes description). The SRAM2 erase can also be requested by software by setting the bit SRAM2ER in the SYSCFG SRAM2 control and status register (SYSCFG_SCSR). 2.4 Flash memory overview The Flash memory is composed of two distinct physical areas: • The main Flash memory block. It contains the application program and user data if necessary. • The information block. It is composed of three parts: – Option bytes for hardware and memory protection user configuration. – System memory which contains the proprietary boot loader code. – OTP (one-time programmable) area The Flash interface implements instruction access and data access based on the AHB protocol. It implements a system of instruction prefetch and caches lines that speeds up CPU code execution. It also implements the logic necessary to carry out the Flash memory operations (Program/Erase) controlled through the Flash registers. Refer to Section 3: Embedded Flash memory (FLASH) for more details. DocID024597 Rev 1 75/1680 77 RM0351 2.5 Boot configuration In the STM32L4x6, three different boot modes can be selected through the BOOT0 pin and nBOOT1 bit in the User option byte, as shown in the following table. Table 3. Boot modes Boot mode selection Boot mode Aliasing BOOT1(1) BOOT0 x 0 Main Flash memory Main Flash memory is selected as boot space 0 1 System memory System memory is selected as boot space 1 1 Embedded SRAM1 Embedded SRAM1 is selected as boot space 1. The BOOT1 value is the opposite of the nBOOT1 Option Bit. The values on both BOOT0 pin and nBOOT1 bit are latched after a reset. It is up to the user to set nBOOT1 and BOOT0 to select the required boot mode. The BOOT0 pin and nBOOT1 bit are also re-sampled when exiting from Standby mode. Consequently they must be kept in the required Boot mode configuration in Standby mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory at 0x0000 0004. Depending on the selected boot mode, main Flash memory, system memory or SRAM1 is accessible as follows: • Boot from main Flash memory: the main Flash memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x0800 0000). In other words, the Flash memory contents can be accessed starting from address 0x0000 0000 or 0x0800 0000. • Boot from system memory: the system memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x1FFF 0000). • Boot from the embedded SRAM1: the SRAM1 is aliased in the boot memory space (0x0000 0000), but it is still accessible from its original memory space (0x2000 0000). Note: When the device boots from SRAM, in the application initialization code, you have to relocate the vector table in SRAM using the NVIC exception table and the offset register. When booting from the main Flash memory, the application software can either boot from bank 1 or from bank 2. By default, boot from bank 1 is selected. To select boot from Flash memory bank 2, set the BFB2 bit in the user option bytes. When this bit is set and the boot pins are in the boot from main Flash memory configuration, the device boots from system memory, and the boot loader jumps to execute the user application programmed in Flash memory bank 2. For further details, please refer to AN2606. Note: When booting from bank 2, in the application initialization code, you have to relocate the vector table to bank 2 base address. (0x0808 0000) using the NVIC exception table and offset register. Physical remap Once the boot pins are selected, the application software can modify the memory accessible in the code area (in this way the code can be executed through the ICode bus in 76/1680 DocID024597 Rev 1 RM0351 place of the System bus). This modification is performed by programming the SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller. The following memories can thus be remapped: • Main Flash memory • System memory • Embedded SRAM1 (96 KB) • FSMC bank 1 (NOR/PSRAM 1 and 2) • Quad SPI memory Embedded boot loader The embedded boot loader is located in the System memory, programmed by ST during production. Refer to AN2606 STM32 microcontroller system memory boot mode DocID024597 Rev 1 77/1680 77 Embedded Flash memory (FLASH) RM0351 3 Embedded Flash memory (FLASH) 3.1 Introduction The Flash memory interface manages CPU AHB ICode and DCode accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines. 3.2 FLASH main features • Up to 1 MByte of Flash memory with dual bank architecture supporting read-while-write capability (RWW) • Memory organization: 2 banks (Bank 1 and Bank 2) – Main memory: 512 KBytes per bank – Information block: 32 KBytes per bank • 72-bit wide data read (64 bits plus 8 ECC bits) • 72-bit wide data write (64 bits plus 8 ECC bits) • Page erase (2 KBytes), Bank erase and Mass erase (both banks) Flash memory interface features: • Flash memory read operations • Flash memory program/erase operations • Read protection activated by option (RDP) • 4 Write protection areas (2 per bank) selected by option (WRP) • 2 Proprietary code read protection areas (1 per bank) selected by option (PCROP) • Prefetch on ICODE • Instruction Cache: 32 cache lines of 4 x 64 bits on ICode (1 KB RAM) • Data Cache: 8 cache lines of 4 x 64 bits on DCode (256B RAM) • Error Code Correction (ECC): 8 bits for 64-bit double-word • Option byte loader • Low-power mode 3.3 FLASH functional description 3.3.1 Flash memory organization The Flash memory is organized as 72-bit wide memory cells (64 bits plus 8 ECC bits) that can be used for storing both code and data constants. 78/1680 DocID024597 Rev 1 RM0351 Embedded Flash memory (FLASH) The Flash memory is divided in 2 banks. Each bank is organized as follows: • A Main memory block containing 256 pages of 2 KBytes. Each page is made of 8 rows of 256 Bytes. • An Information block containing: – System memory from which the device boots in System memory boot mode. The area is reserved for use by STMicroelectronics and contains the boot loader which is used to reprogram the Flash memory through one of the following interfaces: USART1, USART2, USART3, USB (DFU), I2C1, I2C2, I2C3, SPI1, SPI2, SPI3. It is programmed by STMicroelectronics when the device is manufactured, and protected against spurious write/erase operations. For further details, please refer to the AN2606 available from http://www.st.com. – 1 KByte (128 double word) OTP (one-time programmable) bytes for user data. The OTP area is available in Bank 1 only. The OTP data cannot be erased and can be written only once. If only one bit is at 0, the entire double word cannot be written anymore, even with the value 0x0000 0000 0000 0000. – Option bytes for user configuration. The memory organization is based on a main area and an information block as shown in Table 4. Table 4. Flash module - 1 MB dual bank organization Flash area Bank 1 Main memory Bank 2 Flash memory addresses Size (bytes) Name 0x0800 0000 - 0x0800 07FF 2K Page 0 0x0800 0800 - 0x0800 0FFF 2K Page 1 0x0800 1000 - 0x0800 17FF 2K Page 2 0x0800 1800 - 0x0800 1FFF 2K Page 3 - - - 0x0807 F800 - 0x0807 FFFF 2K Page 255 0x0808 0000 - 0x0808 07FF 2K Page 256 0x0808 0800 - 0x0808 0FFF 2K Page 257 0x0808 1000 - 0x0808 17FF 2K Page 258 0x0808 1800 - 0x0808 1FFF 2K Page 259 - - - 0x080F F800 - 0x080F FFFF 2K Page 511 DocID024597 Rev 1 79/1680 120 Embedded Flash memory (FLASH) RM0351 Table 4. Flash module - 1 MB dual bank organization (continued) Flash memory addresses Size (bytes) Bank 1 0x1FFF 0000 - 0x1FFF 6FFF 28 K Bank 2 0x1FFF 8000 - 0x1FFF EFFF 28 K Bank 1 0x1FFF 7000 - 0x1FFF 73FF 1K Bank 1 0x1FFF 7800 - 0x1FFF 780F 16 Bank 2 0x1FFF F800 - 0x1FFF F80F 16 Flash area Information block Name System memory OTP area Option bytes Table 5. Flash module - 512 KB dual bank organization(1) Flash memory addresses Size (bytes) Name 0x0800 0000 - 0x0800 07FF 2K Page 0 0x0800 0800 - 0x0800 0FFF 2K Page 1 0x0800 1000 - 0x0800 17FF 2K Page 2 0x0800 1800 - 0x0800 1FFF 2K Page 3 - - - 0x0803 F800 - 0x0803 FFFF 2K Page 127 0x0804 0000 - 0x0804 07FF 2K Page 256 0x0804 0800 - 0x0804 0FFF 2K Page 257 0x0804 1000 - 0x0804 17FF 2K Page 258 0x0804 1800 - 0x0804 1FFF 2K Page 259 - - - 0x0807 F800 - 0x0807 FFFF 2K Page 383 Bank 1 0x1FFF 0000 - 0x1FFF 6FFF 28 K Bank 2 0x1FFF 8000 - 0x1FFF EFFF 28 K Bank 1 0x1FFF 7000 - 0x1FFF 73FF 1K Bank 1 0x1FFF 7800 - 0x1FFF 780F 16 Bank 2 0x1FFF F800 - 0x1FFF F80F 16 Flash area Bank 1 Main memory Bank 2 Information block 1. For 512 KB devices, option DUALBANK=1 80/1680 DocID024597 Rev 1 System memory OTP area Option bytes RM0351 Embedded Flash memory (FLASH) Table 6. Flash module - 256 KB dual bank organization(1) Flash memory addresses Size (bytes) Name 0x0800 0000 - 0x0800 07FF 2K Page 0 0x0800 0800 - 0x0800 0FFF 2K Page 1 0x0800 1000 - 0x0800 17FF 2K Page 2 0x0800 1800 - 0x0800 1FFF 2K Page 3 - - - 0x0801 F800 - 0x0801 FFFF 2K Page 63 0x0802 0000 - 0x0802 07FF 2K Page 256 0x0802 0800 - 0x0802 0FFF 2K Page 257 0x0802 1000 - 0x0802 17FF 2K Page 258 0x0802 1800 - 0x0802 1FFF 2K Page 259 - - - 0x0803 F800 - 0x0803 FFFF 2K Page 319 Bank 1 0x1FFF 0000 - 0x1FFF 6FFF 28 K Bank 2 0x1FFF 8000 - 0x1FFF EFFF 28 K Bank 1 0x1FFF 7000 - 0x1FFF 73FF 1K Bank 1 0x1FFF 7800 - 0x1FFF 780F 16 Bank 2 0x1FFF F800 - 0x1FFF F80F 16 Flash area Bank 1 Main memory Bank 2 Information block System memory OTP area Option bytes 1. For 256 KB devices, option DUALBANK=1 3.3.2 Error code correction (ECC) Data in Flash memory are 72-bits words: 8 bits are added per double word (64 bits). The ECC mechanism supports: • One error detection and correction • Two errors detection When one error is detected and corrected, the flag ECCC (ECC correction) is set in Flash ECC register (FLASH_ECCR). If ECCCIE is set, an interrupt is generated. When two errors are detected, a flag ECCD (ECC detection) is set in FLASH_ECCR register. In this case, a NMI is generated. When an ECC error is detected, the address of the failing double word and its associated bank are saved in ADDR_ECC[20:0] and BK_ECC in the FLASH_ECCR register. ADDR_ECC[2:0] are always cleared. DocID024597 Rev 1 81/1680 120 Embedded Flash memory (FLASH) RM0351 When ECCC or ECCD is set, ADDR_ECC and BK_ECC are not updated if a new ECC error occurs. FLASH_ECCR is updated only when ECC flags are cleared. Note: For a virgin data: 0xFF FFFF FFFF FFFF FFFF, one error is detected and corrected but 2 errors detection is not supported. When an ECC error is reported, a new read at the failing address may not generate an ECC error if the data is still present in the current buffer, even if ECCC and ECCD are cleared. 3.3.3 Read access latency To correctly read data from Flash memory, the number of wait states (LATENCY) must be correctly programmed in the Flash access control register (FLASH_ACR) according to the frequency of the CPU clock (HCLK) and the internal voltage range of the device VCORE. Refer to Section 6.1.7: Dynamic voltage scaling management. Table 7 shows the correspondence between wait states and CPU clock frequency. Table 7. Number of wait states according to CPU clock (HCLK) frequency HCLK (MHz) Wait states (WS) (LATENCY) VCORE Range 1 VCORE Range 2 0 WS (1 CPU cycles) ≤ 16 ≤6 1 WS (2 CPU cycles) ≤ 32 ≤ 12 2 WS (3 CPU cycles) ≤ 48 ≤ 18 3 WS (4 CPU cycles) ≤ 64 ≤ 26 4 WS (5 CPU cycles) ≤ 80 ≤ 26 After reset, the CPU clock frequency is 4 MHz and 0 wait state (WS) is configured in the FLASH_ACR register. When changing the CPU frequency, the following software sequences must be applied in order to tune the number of wait states needed to access the Flash memory: Increasing the CPU frequency: 82/1680 1. Program the new number of wait states to the LATENCY bits in the Flash access control register (FLASH_ACR). 2. Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register 3. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register 4. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR 5. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits), respectively, in the RCC_CFGR register. DocID024597 Rev 1 RM0351 Embedded Flash memory (FLASH) Decreasing the CPU frequency: 3.3.4 1. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register 2. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR 3. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits), respectively, in the RCC_CFGR register 4. Program the new number of wait states to the LATENCY bits in Flash access control register (FLASH_ACR) 5. Check that the new number of wait states is used to access the Flash memory by reading the FLASH_ACR register Adaptive real-time memory accelerator (ART Accelerator™) The proprietary Adaptive real-time (ART) memory accelerator is optimized for STM32 industry-standard ARM® Cortex®-M4 with FPU processors. It balances the inherent performance advantage of the ARM® Cortex®-M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher operating frequencies. To release the processor full performance, the accelerator implements an instruction prefetch queue and branch cache which increases program execution speed from the 64bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 80 MHz. Instruction prefetch The Cortex®-M4 fetches the instruction over the ICode bus and the literal pool (constant/data) over the DCode bus. The prefetch block aims at increasing the efficiency of ICode bus accesses. Each Flash memory read operation provides 64 bits from either two instructions of 32 bits or four instructions of 16 bits according to the program launched. This 64-bits current instruction line is saved in a current buffer. So, in case of sequential code, at least two CPU cycles are needed to execute the previous read instruction line. Prefetch on the ICode bus can be used to read the next sequential instruction line from the Flash memory while the current instruction line is being requested by the CPU. Prefetch is enabled by setting the PRFTEN bit in the Flash access control register (FLASH_ACR). This feature is useful if at least one wait state is needed to access the Flash memory. Figure 3 shows the execution of sequential 16-bit instructions with and without prefetch when 3 WS are needed to access the Flash memory. DocID024597 Rev 1 83/1680 120 Embedded Flash memory (FLASH) RM0351 Figure 3. Sequential 16 bits instructions execution # :$,7 ) # ' ( ) ' ( # ) ' ( # ) ' :,7+28735()(7&+ # ( ) :$,7 # LQV LQV LQV LQV IHWFK IHWFK IHWFK IHWFK 5HDGLQV # :$,7 # *LYHVLQV ) ' ( ) ' ( # ) ' # ) LQV LQV LQV LQV IHWFK IHWFK IHWFK IHWFK 5HDGLQV *LYHVLQV ' ( ) ' ( # ) ' ( # ) ' ( # ) ' ( # ) ' ( # ) ' # ) :,7+35()(7&+ LQV LQV LQV LQV LQV LQV LQV LQV IHWFK IHWFK IHWFK IHWFK IHWFK IHWFK IHWFK IHWFK 5HDGLQV *LYHVLQV 5HDGLQV *LYHVLQV &RUWH[0SLSHOLQH # ) ' ( $+%SURWRFRO #DGGUHVVUHTXHVWHG ))HWFKVWDJH ''HFRGHVWDJH (([HFXWHVWDJH 5HDGLQV 069 When the code is not sequential (branch), the instruction may not be present in the currently used instruction line or in the prefetched instruction line. In this case (miss), the penalty in terms of number of cycles is at least equal to the number of wait states. 84/1680 DocID024597 Rev 1 RM0351 Embedded Flash memory (FLASH) If a loop is present in the current buffer, no new flash access is performed. Instruction cache memory (I-Cache) To limit the time lost due to jumps, it is possible to retain 32 lines of 4*64 bits in an instruction cache memory.This feature can be enabled by setting the instruction cache enable (ICEN) bit in the Flash access control register (FLASH_ACR). Each time a miss occurs (requested data not present in the currently used instruction line, in the prefetched instruction line or in the instruction cache memory), the line read is copied into the instruction cache memory. If some data contained in the instruction cache memory are requested by the CPU, they are provided without inserting any delay. Once all the instruction cache memory lines have been filled, the LRU (least recently used) policy is used to determine the line to replace in the instruction memory cache. This feature is particularly useful in case of code containing loops. The Instruction cache memory is enable after system reset. Data cache memory (D-Cache) Literal pools are fetched from Flash memory through the DCode bus during the execution stage of the CPU pipeline. Each DCode bus read access fetches 64 bits which are saved in a current buffer. The CPU pipeline is consequently stalled until the requested literal pool is provided. To limit the time lost due to literal pools, accesses through the AHB databus DCode have priority over accesses through the AHB instruction bus ICode. If some literal pools are frequently used, the data cache memory can be enabled by setting the data cache enable (DCEN) bit in the Flash access control register (FLASH_ACR). This feature works like the instruction cache memory, but the retained data size is limited to 8 rows of 4*64 bits. The Data cache memory is enable after system reset. Note: The D-Cache is active only when data is requested by the CPU (not by DMA1 and DMA2). Data in option bytes block are not cacheable. 3.3.5 Flash program and erase operations The STM32L4x embedded Flash memory can be programmed using in-circuit programming or in-application programming. The in-circuit programming (ICP) method is used to update the entire contents of the Flash memory, using the JTAG, SWD protocol or the boot loader to load the user application into the microcontroller. ICP offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. In contrast to the ICP method, in-application programming (IAP) can use any communication interface supported by the microcontroller (I/Os, USB, CAN, UART, I2C, SPI, etc.) to download programming data into memory. IAP allows the user to re-program the Flash memory while the application is running. Nevertheless, part of the application has to have been previously programmed in the Flash memory using ICP. The contents of the Flash memory are not guaranteed if a device reset occurs during a Flash memory operation. An on-going Flash memory operation will not block the CPU as long as the CPU does not access the same Flash memory bank. Code or data fetches are possible on one bank while DocID024597 Rev 1 85/1680 120 Embedded Flash memory (FLASH) RM0351 a write/erase operation is performed to the other bank (refer to Section 3.3.8: Read-whilewrite (RWW)). On the contrary, during a program/erase operation to the Flash memory, any attempt to read the same Flash memory bank will stall the bus. The read operation will proceed correctly once the program/erase operation has completed. Unlocking the Flash memory After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the Flash memory against possible unwanted operations due, for example, to electric disturbances. The following sequence is used to unlock this register: 1. Write KEY1 = 0x45670123 in the Flash key register (FLASH_KEYR) 2. Write KEY2 = 0xCDEF89AB in the FLASH_KEYR register. Any wrong sequence will lock up the FLASH_CR register until the next system reset. In the case of a wrong key sequence, a bus error is detected and a Hard Fault interrupt is generated. The FLASH_CR register can be locked again by software by setting the LOCK bit in the FLASH_CR register. Note: The FLASH_CR register cannot be written when the BSY bit in the Flash status register (FLASH_SR) is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to stall until the BSY bit is cleared. 3.3.6 Flash main memory erase sequences The Flash memory erase operation can be performed at page level, bank level or on the whole Flash memory (Mass Erase). Mass Erase does not affect the Information block (system flash, OTP and option bytes). Page erase To erase a page (2Kbytes), follow the procedure below: Note: 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the Flash status register (FLASH_SR). 2. Check and clear all error programming flags due to a previous programming. If not, PGSERR is set. 3. Set the PER bit and select the page you wish to erase (PNB) with the associated bank (BKER) in the Flash control register (FLASH_CR). 4. Set the STRT bit in the FLASH_CR register. 5. Wait for the BSY bit to be cleared in the FLASH_SR register. The internal oscillator HSI16 (16 MHz) is enabled automatically when STRT bit is set, and disabled automatically when STRT bit is cleared, except if the HSI16 is previously enabled with HSION in RCC_CR register. If the page erase is part of write-protected area (by WRP or PCROP), WRPERR is set and the page erase request is aborted. Bank 1, Bank 2 or both banks Mass erase To perform a bank Mass Erase, follow the procedure below: 86/1680 DocID024597 Rev 1 RM0351 Note: Embedded Flash memory (FLASH) 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register 2. Check and clear all error programming flags due to a previous programming. If not, PGSERR is set. 3. Set the MER1 bit or/and MER2 (depending on the bank) in the Flash control register (FLASH_CR). The both banks can be selected in the same operation. 4. Set the STRT bit in the FLACH_CR register. 5. Wait for the BSY bit to be cleared in the Flash status register (FLASH_SR). The internal oscillator HSI16 (16 MHz) is enabled automatically when STRT bit is set, and disabled automatically when STRT bit is cleared, except if the HSI16 is previously enabled with HSION in RCC_CR register. If the bank to erase or if one of the banks to erase contains a write-protected area (by WRP or PCROP), WRPERR is set and the mass erase request is aborted (for both banks if both are selected). 3.3.7 Flash main memory programming sequences The Flash memory is programmed 72 bits at a time (64 bits + 8 bits ECC). Programming in a previously programmed address is not allowed except if the data to write is full zero, and any attempt will set PROGERR flag in the Flash status register (FLASH_SR). It is only possible to program double word (2 x 32-bit data). • Any attempt to write byte or half-word will set SIZERR flag in the FLASH_SR register. • Any attempt to write a double word which is not aligned with a double word address will set PGAERR flag in the FLASH_SR register. Standard programming The Flash memory programming sequence in standard mode is as follows: Note: 1. Check that no Flash main memory operation is ongoing by checking the BSY bit in the Flash status register (FLASH_SR). 2. Check and clear all error programming flags due to a previous programming. If not, PGSERR is set. 3. Set the PG bit in the Flash control register (FLASH_CR). 4. Perform the data write operation at the desired memory address, inside main memory block or OTP area. Only double word can be programmed. – Write a first word in an address aligned with double word – Write the second word 5. Wait until the BSY bit is cleared in the FLASH_SR register. 6. Check that EOP flag is set in the FLASH_SR register (meaning that the programming operation has succeed), and clear it by software. 7. Clear the PG bit in the FLASH_SR register if there no more programming request anymore. When the flash interface has received a good sequence (a double word), programming is automatically launched and BSY bit is set. The internal oscillator HSI16 (16 MHz) is enabled DocID024597 Rev 1 87/1680 120 Embedded Flash memory (FLASH) RM0351 automatically when PG bit is set, and disabled automatically when PG bit is cleared, except if the HSI16 is previously enabled with HSION in RCC_CR register. If the user needs to program only one word, double word must be completed with the erase value 0xFFFF FFFF to launch automatically the programming. ECC is calculated from the double word to program. Fast programming This mode allows to program a row (32 double word) and to reduce the page programming time by eliminating the need for verifying the flash locations before they are programmed and to avoid rising and falling time of high voltage for each double word. During fast programming, the CPU clock frequency (HCLK) must be at least 8 MHz. Only the main memory can be programmed in Fast programming mode. The Flash main memory programming sequence in standard mode is as follows: Note: 1. Perform a mass erase of the bank to program. If not, PGSERR is set. 2. Check that no Flash main memory operation is ongoing by checking the BSY bit in the Flash status register (FLASH_SR). 3. Check and clear all error programming flag due to a previous programming. 4. Set the FSTPG bit in Flash control register (FLASH_CR). 5. Write the 32 double words to program a row. 6. Wait until the BSY bit is cleared in the FLASH_SR register. 7. Check that EOP flag is set in the FLASH_SR register (meaning that the programming operation has succeed), and clear it by software. 8. Clear the FSTPG bit in the FLASH_SR register if there no more programming request anymore. When the flash interface has received the first double word, programming is automatically launched. The BSY bit is set when the high voltage is applied for the first double word, and it is cleared when the last double word has been programmed or in case of error. The internal oscillator HSI16 (16 MHz) is enabled automatically when FSTPG bit is set, and disabled automatically when FSTPG bit is cleared, except if the HSI16 is previously enabled with HSION in RCC_CR register. The 32 double word must be written successively. The high voltage is kept on the flash for all the programming. Maximum time between two double words write requests is the time programming (around 20us). If a second double word arrives after this time programming, fast programming is interrupted and MISSERR is set. High voltage mustn’t exceed 8 ms for a full row between 2 erases. This is guaranteed by the sequence of 32 double words successively written with a clock system greater or equal to 8MHz. An internal time-out counter counts 7ms when Fast programming is set and stops the programming when time-out is over. In this case the FASTERR bit is set. If an error occurs, high voltage is stopped and next double word to programmed is not programmed. Anyway, all previous double words have been properly programmed. 88/1680 DocID024597 Rev 1 RM0351 Embedded Flash memory (FLASH) Programming errors Several kind of errors can be detected. In case of error, the Flash operation (programming or erasing) is aborted. • PROGERR: Programming Error In standard programming: PROGERR is set if the word to write is not previously erased (except if the value to program is full zero). • SIZERR: Size Programming Error In standard programming or in fast programming: only double word can be programmed and only 32-bit data can be written. SIZERR is set if a byte or an halfword is written. • PGAERR: Alignment Programming error PGAERR is set if one of the following conditions occurs: • – In standard programming: the first word to be programmed is not aligned with a double word address, or the second word doesn’t belong to the same double word address. – In fast programming: the data to program doesn’t belong to the same row than the previous programmed double words, or the address to program in not greater than the previous one. PGSERR: Programming Sequence Error PGSERR is set if one of the following conditions occurs: • – In the standard programming sequence or the fast programming sequence: a data is written when PG and FSTPG are cleared. – In the standard programming sequence or the fast programming sequence: MER1, MER2, and PER are not cleared when PG or FSTPG is set. – In the fast programming sequence: the Mass erase is not performed before setting FSTPG bit. – In the mass erase sequence: PG, FSTPG, and PER are not cleared when MER1 or MER2 is set. – In the page erase sequence: PG, FSTPG, MER1 and MER2 are not cleared when PER is set. – PGSERR is set also if PROGERR, SIZERR, PGAERR, WRPERR, MISSERR, FASTERR or PGSERR is set due to a previous programming error. WRPERR: Write Protection Error WRPERR is set if one of the following conditions occurs: • – Attempt to program or erase in a write protected area (WRP) or in a PCROP area. – Attempt to perform a bank erase when one page or more is protected by WRP or PCROP. – The debug features are connected or the boot is executed from SRAM or from System flash when the read protection (RDP) is set to Level 1. – Attempt to modify the option bytes when the read protection (RDP) is set to Level 2. MISSERR: Fast Programming Data Miss Error In fast programming: all the data must be written successively. MISSERR is set if the previous data programmation is finished and the next data to program is not written yet. • FASTERR: Fast Programming Error DocID024597 Rev 1 89/1680 120 Embedded Flash memory (FLASH) RM0351 In fast programming: FASTERR is set if one of the following conditions occurs: – When FSTPG bit is set for more than 7µs which generates a time-out detection. – When the row fast programming has been interrupted by a MISSERR, PGAERR, WRPERR or SIZERR. If an error occurs during a program or erase operation, one of the following error flags is set in the FLASH_SR register: PROGERR, SIZERR, PGAERR, PGSERR, MISSERR (Program error flags), WRPERR (Protection error flag) In this case, if the error interrupt enable bit ERRIE is set in the Flash status register (FLASH_SR), an interrupt is generated and the operation error flag OPERR is set in the FLASH_SR register. Note: If several successive errors are detected (for example, in case of DMA transfer to the Flash memory), the error flags cannot be cleared until the end of the successive write requests. Programming and caches If a Flash memory write access concerns some data in the data cache, the Flash write access modifies the data in the Flash memory and the data in the cache. If an erase operation in Flash memory also concerns data in the data or instruction cache, you have to make sure that these data are rewritten before they are accessed during code execution. If this cannot be done safely, it is recommended to flush the caches by setting the DCRST and ICRST bits in the Flash control register (FLASH_CR). Note: The I/D cache should be flushed only when it is disabled (I/DCEN = 0). 3.3.8 Read-while-write (RWW) The Flash memory is divided into two banks allowing read-while-write operations. This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank. Note: Write-while-write operations are not allowed. As an exampled, It is not possible to perform an erase operation on one bank while programming the other one. Read from bank 1 while page erasing in bank 2 (or vice versa) While executing a program code from bank 1, it is possible to perform a page erase operation on bank 2 (and vice versa). Follow the procedure below: 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the Flash status register (FLASH_SR) (BSY is active when erase/program operation is on going in bank 1 or bank 2). 2. Set PER bit, PSB to select the page and BKER to select the bank in the Flash control register (FLASH_CR). 3. Set the STRT bit in the FLASH_CR register. 4. Wait for the BSY bit to be cleared (or use the EOP interrupt). Read from bank 1 while mass erasing bank 2 (or vice versa) While executing a program code from bank 1, it is possible to perform a mass erase operation on bank 2 (and vice versa). Follow the procedure below: 90/1680 DocID024597 Rev 1 RM0351 Embedded Flash memory (FLASH) 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the Flash status register (FLASH_SR) (BSY is active when erase/program operation is on going in bank 1 or bank 2). 2. Set MER1 or MER2 to in the Flash control register (FLASH_CR). 3. Set the STRT bit in the FLASH_CR register. 4. Wait for the BSY bit to be cleared (or use the EOP interrupt). Read from bank 1 while programming bank 2 (or vice versa) While executing a program code from bank 1, it is possible to perform a program operation on the bank 2. (and vice versa). Follow the procedure below: 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the Flash status register (FLASH_SR) (BSY is active when erase/program operation is on going on bank 1 or bank 2). 2. Set the PG bit in the Flash control register (FLASH_CR). 3. Perform the data write operations at the desired address memory inside the main memory block or OTP area. 4. Wait for the BSY bit to be cleared (or use the EOP interrupt). DocID024597 Rev 1 91/1680 120 Embedded Flash memory (FLASH) RM0351 3.4 FLASH option bytes 3.4.1 Option bytes description The option bytes are configured by the end user depending on the application requirements. As a configuration example, the watchdog may be selected in hardware or software mode (refer to Section 3.4.2: Option bytes programming). A double word is split up as follows in the option bytes: Table 8. Option byte format 63-24 23-16 15 -8 7-0 Complemented Complemented Complemented Complemented option byte 3 option byte 2 option byte 1 option byte 0 31-24 23-16 15 -8 7-0 Option byte 3 Option byte 2 Option byte 1 Option byte 0 The organization of these bytes inside the information block is as shown in Table 9: Option byte organization. The option bytes can be read from the memory locations listed in Table 9: Option byte organization or from the Option byte registers: • Flash option register (FLASH_OPTR) • Flash Bank 1 PCROP Start address register (FLASH_PCROP1SR) • Flash Bank 1 PCROP End address register (FLASH_PCROP1ER) • Flash Bank 1 WRP area A address register (FLASH_WRP1AR) • Flash Bank 1 WRP area B address register (FLASH_WRP1BR) • Flash Bank 2 PCROP Start address register (FLASH_PCROP2SR) • Flash Bank 2 PCROP End address register (FLASH_PCROP2ER) • Flash Bank 2 WRP area A address register (FLASH_WRP2AR) • Flash Bank 2 WRP area B address register (FLASH_WRP2BR). Table 9. Option byte organization Address 63 [62:56] 1FFF7800 92/1680 Unused PCROP_RDP Bank 1 [47:40] USER OPT 1FFF7808 1FFF7810 [55:48] Unused [39:32] 31 [30:24] RDP Unused PCROP1_STRT PCROP1_END [23:16] [15:8] USER OPT PCROP_RDP BANK Unused [7:0] RDP PCROP1_STRT PCROP1_END 1FFF7818 Unused WRP1A _END Unused WRP1A _STRT Unused WRP1A _ END Unused WRP1A _STRT 1FFF7820 Unused WRP1B _END Unused WRP1B _STRT Unused WRP1B _ END Unused WRP1B _STRT DocID024597 Rev 1 RM0351 Embedded Flash memory (FLASH) Table 9. Option byte organization (continued) BANK Address 63 [62:56] [55:48] 1FFFF800 [47:40] [39:32] 31 [30:24] [23:16] Unused [15:8] [7:0] Unused 1FFFF808 Unused PCROP2_STRT Unused PCROP2_STRT 1FFFF810 Unused PCROP2_END Unused PCROP2_END Bank 2 1FFFF818 Unused WRP2A _END Unused WRP2A _STRT Unused WRP2A _END Unused WRP2A _STRT 1FFFF820 Unused WRP2B _END Unused WRP2B _STRT Unused WRP2B _END Unused WRP2B _STRT User and read protection option bytes Flash memory address: 0x1FFF 7800 ST production value: 0xFFEF F8AA 31 30 29 28 27 26 25 Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 Res. nRST_ nRST_ nRST_ SHDW STDBY STOP r r r Res. 24 23 SRAM2 SRAM2 n _RST _PE BOOT1 r r r 9 8 7 22 21 Res. DUAL BANK r r r r r r 6 5 4 3 2 1 0 r r r BOR_LEV[2:0] r r 20 BFB2 19 18 17 16 WWDG IWGD_ IWDG_ IWDG_ _SW STDBY StOP SW RDP[7:0] r r r r r r Bits 31:26 Not used Bit 25 SRAM2_RST: SRAM2 Erase when system reset 0: SRAM2 erased when a system reset occurs 1: SRAM2 is not erased when a system reset occurs Bit 24 SRAM2_PE: SRAM2 parity check enable 0: SRAM2 parity check enable 1: SRAM2 parity check disable Bit 23 nBOOT1: Boot configuration Together with the BOOT0 pin, this bit selects boot mode from the Flash main memory, SRAM1 or the System memory. Refer to Section 2.5: Boot configuration. Bit 22 Not used Bit 21 DUALBANK: Dual-Bank on 512 KB or 256 KB Flash memory devices 0: 256 KB/512 KB Single-bank Flash: Contiguous addresses in Bank 1 1: 256 KB/512 KB Dual-bank Flash: Refer to Table 5 and Table 6. Bit 20 BFB2: Dual-bank boot 0: Dual-bank boot disable 1: Dual-bank boot enable Bit 19 WWDG_SW: Window watchdog selection 0: Hardware window watchdog 1: Software window watchdog DocID024597 Rev 1 93/1680 120 Embedded Flash memory (FLASH) RM0351 Bit 18 IWDG_STDBY: Independent watchdog counter freeze in Standby mode 0: Independent watchdog counter is frozen in Standby mode 1: Independent watchdog counter is running in Standby mode Bit 17 IWDG_STOP: Independent watchdog counter freeze in Stop mode 0: Independent watchdog counter is frozen in Stop mode 1: Independent watchdog counter is running in Stop mode Bit 16 IDWG_SW: Independent watchdog selection 0: Hardware independent watchdog 1: Software independent watchdog Bit 15 Not used Bit 14 nRST_SHDW 0: Reset generated when entering the Shutdown mode 1: No reset generated when entering the Shutdown mode Bit 13 nRST_STDBY 0: Reset generated when entering the Standby mode 1: No reset generate when entering the Standby mode Bit 12 nRST_STOP 0: Reset generated when entering the Stop mode 1: No reset generated when entering the Stop mode Bit 11 Not used Bits10:8 BOR_LEV: BOR reset Level These bits contain the VDD supply level threshold that activates/releases the reset. 000: BOR Level 0. Reset level threshold is around 1.7 V 001: BOR Level 1. Reset level threshold is around 2.0 V 010: BOR Level 2. Reset level threshold is around 2.2 V 011: BOR Level 3. Reset level threshold is around 2.5 V 100: BOR Level 4. Reset level threshold is around 2.8 V Bits 7:0 RDP: Read protection level 0xAA: Level 0, read protection not active 0xCC: Level 2, chip read protection active Others: Level 1, memories read protection active Bank 1 PCROP Start address option bytes Flash memory address: 0x1FFF 7808 ST production value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r PCROP1_STRT[15:0] r 94/1680 r r r r r r r r DocID024597 Rev 1 RM0351 Embedded Flash memory (FLASH) Bits 31:16 Not used Bits 15:0 PCROP1_STRT: Bank 1 PCROP area start offset PCROP1_STRT contains the first double-word of the bank 1 PCROP area. Bank 1 PCROP End address option bytes Flash memory address: 0x1FFF 7810 ST production value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PCROP _RDP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r r PCROP1_END[15:0] r r Bit 31 PCROP_RDP: PCROP area preserved when RDP level decreased This bit is set only. It is reset after a full mass erase due to a change of RDP from Level 1 to Level 0. 0: PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0. 1: PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase). Bits 30:16 Not used Bits 15:0 PCROP1_END: Bank 1 PCROP area end offset PCROP1_END contains the last double-word of the bank 1 PCROP area. Bank 1 WRP Area A address option bytes Flash memory address: 0x1FFF 7818 ST production value: 0x0000 00FF 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 WRP1A_END[15:0] r r r 7 6 5 r r r r r 4 3 2 1 0 r r r WRP1A_STRT[15:0] r r r r r Bits 31:24 Not used Bits 23:16 WRP1A_END: Bank 1 WRP first area “A” end offset WRPA1_END contains the last page of the Bank 1 WRP first area. Bits 15:8 Not used Bits 7:0 WRP1A_STRT: Bank 1 WRP first area “A” start offset WRPA1_STRT contains the first page of the Bank 1 WRP first area. DocID024597 Rev 1 95/1680 120 Embedded Flash memory (FLASH) RM0351 Bank 1 WRP Area B address option bytes Flash memory address: 0x1FFF 7820 ST production value: 0x0000 00FF 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 r r r r r r r r 7 6 5 4 3 2 1 0 r r r WRP1B_END[15:0] WRP1B_STRT[15:0] r r r r r Bits 31:24 Not used Bits 23:16 WRP1B_END: Bank 1 WRP first area “B” end offset WRPB1_END contains the last page of the Bank 1 WRP second area. Bits 15:8 Not used Bits 7:0 WRP1B_STRT: Bank 1 WRP first area “B” start offset WRPB1_STRT contains the first page of the Bank 1 WRP second area. Bank 2 PCROP Start address option bytes Flash memory address: 0x1FFF F808 ST production value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r PCROP2_STRT[15:0] r r r r r r r r r Bits 31:16 Not used Bits 15:0 PCROP2_STRT: Bank 2 PCROP area start offset PCROP2_STRT contains the first double-word of the bank 2 PCROP area. Bank 2 PCROP End address option bytes Flash memory address: 0x1FFF F810 ST production value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r PCROP2_END[15:0] 96/1680 r r DocID024597 Rev 1 RM0351 Embedded Flash memory (FLASH) Bits 31:16 Not used Bits 15:0 PCROP2_END: Bank 2 PCROP area end offset PCROP2_END contains the last double-word of the bank 2 PCROP area. Bank 2 WRP Area A address option bytes Flash memory address: 0x1FFF F818 ST production value: 0x0000 00FF 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 WRP2A_END[15:0] r r r r r r r r 7 6 5 4 3 2 1 0 r r r r r r 17 16 WRP2A_STRT[15:0] r r Bits 31:24 Not used Bits 23:16 WRP2A_END: Bank 2 WRP first area “A” end offset WRP2A_END contains the last page of the Bank 2 WRP first area. Bits 15:8 Not used Bits 7:0 WRP2A_STRT: Bank 2 WRP first area “A” start offset WRP2A_STRT contains the first page of the Bank 2 WRP first area. Bank 2 WRP Area B address option bytes Flash memory address: 0x1FFF F820 ST production value: 0x0000 00FF 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 WRP2B_END[15:0] r r r r r r r r 7 6 5 4 3 2 1 0 r r r r r r WRP2B_STRT[15:0] r r Bits 31:24 Not used Bits 23:16 WRP2B_END: Bank 2 WRP first area “B” end offset WRP2B_END contains the last page of the Bank 2 WRP second area. Bits 15:8 Not used Bits 7:0 WRP2B_STRT: Bank 2 WRP first area “B” start offset WRP2B_STRT contains the first page of the Bank 2 WRP second area. 3.4.2 Option bytes programming After reset, the options related bits in the Flash control register (FLASH_CR) are writeprotected. To run any operation on the option bytes page, the option lock bit OPTLOCK in DocID024597 Rev 1 97/1680 120 Embedded Flash memory (FLASH) RM0351 the Flash control register (FLASH_CR) must be cleared. The following sequence is used to unlock this register: 1. Unlock the FLASH_CR with the LOCK clearing sequence (refer to Unlocking the Flash memory). 2. Write OPTKEY1 = 0x08192A3B in the Flash option key register (FLASH_OPTKEYR). 3. Write OPTKEY2 = 0x4C5D6E7F in the FLASH_OPTKEYR register. The user options can be protected against unwanted erase/program operations by setting the OPTLOCK bit by software. Note: If LOCK is set by software, OPTLOCK is automatically set too. Modifying user options The option bytes are programmed differently from a main memory user address. It is not possible to modify independently user options of bank 1 or bank 2. The users Options of the bank 1 are modified first. To modify the user options value, follow the procedure below: Note: 1. Check that no Flash memory operation is on going by checking the BSY bit in the Flash status register (FLASH_SR). 2. Clear OPTLOCK option lock bit with the clearing sequence described above. 3. Write the desired options value in the options registers: Flash option register (FLASH_OPTR), Flash Bank 1 PCROP Start address register (FLASH_PCROP1SR), Flash Bank 1 PCROP End address register (FLASH_PCROP1ER), Flash Bank 1 WRP area A address register (FLASH_WRP1AR), Flash Bank 1 WRP area B address register (FLASH_WRP1BR), Flash Bank 2 PCROP Start address register (FLASH_PCROP2SR), Flash Bank 2 PCROP End address register (FLASH_PCROP2ER), Flash Bank 2 WRP area A address register (FLASH_WRP2AR), Flash Bank 2 WRP area B address register (FLASH_WRP2BR). 4. Set the Options Start bit OPTSTRT in the Flash control register (FLASH_CR). 5. Wait for the BSY bit to be cleared. Any modification of the value of one option is automatically performed by erasing both user option bytes pages first (bank 1 and bank 2) and then programming all the option bytes with the values contained in the flash option registers. Option byte loading After the BSY bit is cleared, all new options are updated into the flash but they are not applied to the system. They will have effect on the system when they are loaded. Option bytes loading is performed in two cases: – when OBL_LAUNCH bit is set in the Flash control register (FLASH_CR). – after a power reset (BOR reset or exit from Standby/Shutdown modes). Option byte loader performs a read of the options block and stores the data into internal option registers. These internal registers configure the system and cannot be read with by software. Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset. Each option bit has also its complement in the same double word. During option loading, a verification of the option bit and its complement allows to check the loading has correctly taken place. 98/1680 DocID024597 Rev 1 RM0351 Embedded Flash memory (FLASH) During option byte loading, the options are read by double word with ECC. If the word and its complement are matching, the option word/byte is copied into the option register. If the comparison between the word and its complement fails, a status bit OPTVERR is set. Mismatch values are forced into the option registers: – For USR OPT option, the value of mismatch is all options at ‘1’, except for BOR_LEV which is “000” (lowest threshold) – For WRP option, the value of mismatch is the default value “No protection” – For RDP option, the value of mismatch is the default value “Level 1” – For PCROP, the value of mismatch is “all memory protected” On system reset rising, internal option registers are copied into option registers which can be read and written by software (FLASH_OPTR, FLASH_PCROP1/2SR, FLASH_PCROP1/2ER, FLASH_WRP1/2AR, FLASH_WRP1/2BR). These registers are also used to modify options. If these registers are not modified by user, they reflects the options states of the system. See Section : Modifying user options for more details. DocID024597 Rev 1 99/1680 120 Embedded Flash memory (FLASH) 3.5 RM0351 FLASH memory protection The Flash main memory can be protected against external accesses with the Read protection (RDP). The pages of the Flash memory can also be protected against unwanted write due to loss of program counter contexts. The write-protection (WRP) granularity is one page (2 KBytes). Apart of the flash memory can also be protected against read and write from third parties (PCROP). The PCROP granularity is double word (64-bit). 3.5.1 Read protection (RDP) The read protection is activated by setting the RDP option byte and then, by applying a system reset to reload the new RDP option byte. The read protection protects to the Flash main memory, the option bytes, the backup registers (RTC_BKPxR in the RTC) and the SRAM2. Note: If the read protection is set while the debugger is still connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset. There are three levels of read protection from no protection (level 0) to maximum protection or no debug (level 2). The Flash memory is protected when the RDP option byte and its complement contain the pair of values shown in Table 10. Table 10. Flash memory read protection status RDP byte value RDP complement value Read protection level 0xAA 0x55 Level 0 Any value except 0xAA or 0xCC Any value (not necessarily complementary) except 0x55 and 0x33 Level 1 (default) 0xCC 0x33 Level 2 The System memory area is read accessible whatever the protection level. It is never accessible for program/erase operation. Level 0: no protection Read, program and erase operations into the Flash main memory area are possible. The option bytes, the SRAM2 and the backup registers are also accessible by all operations. 100/1680 DocID024597 Rev 1 RM0351 Embedded Flash memory (FLASH) Level 1: Read protection This is the default protection level when RDP option byte is erased. It is defined as well when RDP value is at any value different from 0xAA and 0xCC, or even if the complement is not correct. • User mode: Code executing in user mode (Boot Flash) can access Flash main memory, option bytes, SRAM2 and backup registers with all operations. • Debug, boot RAM and boot loader modes: In debug mode or when code is running from boot RAM or boot loader, the Flash main memory, the backup registers (RTC_BKPxR in the RTC) and the SRAM2 are totally inaccessible. In these modes, a read or write access to the Flash generates a bus error and a Hard Fault interrupt. Level 2: No debug In this level, the protection level 1 is guaranteed. In addition, the Cortex®-M4 debug port, the boot from RAM (boot RAM mode) and the boot from System memory (boot loader mode) are no more available. In user execution mode (boot FLASH mode), all operations are allowed on the Flash Main memory. On the contrary, only read operations can be performed on the option bytes. Option bytes cannot be programmed nor erased. Thus, the level 2 cannot be removed at all: it is an irreversible operation. When attempting to modify the options bytes, the protection error flag WRPERR is set in the Flash_SR register and an interrupt can be generated. Note: The debug feature is also disabled under reset. STMicroelectronics is not able to perform analysis on defective parts on which the level 2 protection has been set. Changing the Read protection level It is easy to move from level 0 to level 1 by changing the value of the RDP byte to any value (except 0xCC). By programming the 0xCC value in the RDP byte, it is possible to go to level 2 either directly from level 0 or from level 1. Once in level 2, it is no more possible to modify the Read protection level. When the RDP is reprogrammed to the value 0xAA to move from Level 1 to Level 0, a mass erase of the Flash main memory is performed if PCROP_RDP is set in the Flash Bank 1 PCROP End address register (FLASH_PCROP1ER). The backup registers (RTC_BKPxR in the RTC) and the SRAM2 are also erased. The user options except PCROP protection are set to their previous values copied from FLASH_OPTR, FLASH_WRPxyR (x=1, 2 and y =A or B). PCROP is disable. The OTP area is not affected by mass erase and remains unchanged. If the bit PCROP_RDP is cleared in the FLASH_PCROP1ER, the full mass erase is replaced by a partial mass erase that is successive page erases in the bank where PCROP is active, except for the pages protected by PCROP. This is done in order to keep the PCROP code. If PCROP is active for both banks, both banks are erased by page erases. Only when both banks are erased, options are re-programmed with their previous values. This is also true for FLASH_PCROPxSR and FLASH_PCROPxER registers (x=1,2). Note: Full Mass Erase or Partial Mass Erase is performed only when Level 1 is active and Level 0 requested. When the protection level is increased (0->1, 1->2, 0->2) there is no mass erase. To validate the protection level change, the option bytes must be reloaded through the OBL_LAUNCH bit in Flash control register. DocID024597 Rev 1 101/1680 120 Embedded Flash memory (FLASH) RM0351 Figure 4. Changing the Read protection (RDP) level 5'3[$$DQG5'3[&& 2WKHUVRSWLRQVPRGLILHG /HYHO 5'3[$$ 5'3[&& GHIDXOW :ULWHRSWLRQV,QFOXGLQJ 5'3 [&& :ULWHRSWLRQVLQFOXGLQJ 5'3[&&DQG5'3[$$ /HYHO 5'3 [&& :ULWHRSWLRQVLQFOXGLQJ 5'3 [$$ /HYHO 5'3 [$$ :ULWHRSWLRQVLQFOXGLQJ 5'3 [&& 5'3 [$$ 2WKHU V RSWLRQ V PRGLILHG 2SWLRQVZULWH 5'3OHYHOLQFUHDVH LQFOXGHV 2SWLRQVSDJHHUDVH 1HZRSWLRQVSURJUDP 2SWLRQVZULWH 5'3OHYHOGHFUHDVH LQFOXGHV )XOO0DVVHUDVHRU3DUWLDO0DVVHUDVHWRQRW HUDVH3&523SDJHVLI3&523B5'3LVFOHDUHG %DFNXSUHJLVWHUVDQG65$0HUDVH 2SWLRQVSDJHHUDVH 1HZRSWLRQVSURJUDP 2SWLRQVZULWH 5'3OHYHOLGHQWLFDO LQFOXGHV 2SWLRQVSDJHHUDVH 1HZRSWLRQVSURJUDP 069 Table 11. Access status versus protection level and execution modes Area Flash main memory System memory (2) Option bytes Backup registers SRAM2 Protection level Debug/ BootFromRam/ BootFromLoader User execution (BootFromFlash) Read Write Erase Read Write Erase 1 Yes Yes Yes No No No(3) 2 Yes Yes Yes N/A(1) N/A(1) N/A(1) 1 Yes No No Yes No No 2 Yes No No NA(1) N/A(1) N/A(1) 1 Yes Yes(3) Yes Yes Yes(3) Yes N/A(1) N/A(1) No No(4) N/A(1) N/A(1) 2 Yes No No 1 Yes Yes N/A N/A (1) No (1) 2 Yes Yes N/A N/A 1 Yes Yes N/A No No No(5) 2 Yes Yes N/A N/A(1) N/A(1) N/A(1) 1. When the protection level 2 is active, the Debug port, the boot from RAM and the boot from system memory are disabled. 2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode. 3. The Flash main memory is erased when the RDP option byte is programmed with all level protections disabled (0xAA). 4. The backup registers are erased when RDP changes from level 1 to level 0. 5. The SRAM2 is erased when RDP changes from level 1 to level 0. 102/1680 DocID024597 Rev 1 RM0351 3.5.2 Embedded Flash memory (FLASH) Proprietary code readout protection (PCROP) Apart of the flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. One area per bank can be selected, with double word (64-bit) granularity. An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0 (refer to Changing the Read protection level). Each PCROP area is defined by a start page offset and an end page offset related to the physical Flash bank base address. These offsets are defined in the PCROP address registers Flash Bank 1 PCROP Start address register (FLASH_PCROP1SR), Flash Bank 1 PCROP End address register (FLASH_PCROP1ER), Flash Bank 2 PCROP Start address register (FLASH_PCROP2SR), Flash Bank 2 PCROP End address register (FLASH_PCROP2ER). The Bank “x” PCROP (x=1,2) area is defined from the address: Bank “x” Base address + [PCROPx_STRT x 0x8] (included) to the address: Bank “x” Base address + [(PCROPx_END+1) x 0x8] (excluded). The minimum PCROP area size is two double-words (128 bits). For example, to protect by PCROP from the address 0x08062F80 (included) to the address 0x08070004 (included): • • if boot in flash is done in Bank 1, FLASH_PCROP1SR and FLASH_PCROP1ER registers must be programmed with: – PCROP1_STRT = 0xC5F0. – PCROP1_END = 0xE000. If the two banks are swapped, the protection must apply to bank 2, and FLASH_PCROP2SR and FLASH_PCROP2ER register must be programmed with: – PCROP2_STRT = 0xC5F0. – PCROP2_END = 0xE000. Any read access performed through the D-bus to a PCROP protected area will trigger RDERR flag error. Any PCROP protected address is also write protected and any write access to one of these addresses will trigger WRPERR. Any PCROP area is also erase protected. Consequently, any erase to a page in this zone is impossible (including the page containing the start address and the end address of this zone). Moreover, a software mass erase cannot be performed if one zone is PCROP protected. For previous example, due to erase by page, all pages from page 0xC5 to 0xE0 are protected in case of page erase. (All addresses from 0x08062800 to 0x080707FF can’t be erased). Deactivation of PCROP can only occurs when the RDP is changing from level 1 to level 0. If the user options modification tries to clear PCROP or to decrease the PCROP area, the options programming is launched but PCROP area stays unchanged. On the contrary, it is possible to increase the PCROP area. When option bit PCROP_RDP is cleared, when the RDP is changing from level 1 to level 0, Full Mass Erase is replaced by Partial Mass Erase in order to keep the PCROP area (refer DocID024597 Rev 1 103/1680 120 Embedded Flash memory (FLASH) RM0351 to Changing the Read protection level). In this case, PCROP1/2_STRT and PCROP1/2_END are also not erased. Note: It is recommended to align PCROP area with page granularity when using PCROP_RDP, or to leave free the rest of the page where PCROP zone starts or ends. 3.5.3 Write protection (WRP) The user area in Flash memory can be protected against unwanted write operations. Two write-protected (WRP) areas can be defined in each bank, with page (2 KBytes) granularity. Each area is defined by a start page offset and an end page offset related to the physical Flash bank base address. These offsets are defined in the WRP address registers: Flash Bank 1 WRP area A address register (FLASH_WRP1AR), Flash Bank 1 WRP area B address register (FLASH_WRP1BR), Flash Bank 2 WRP area A address register (FLASH_WRP2AR), Flash Bank 2 WRP area B address register (FLASH_WRP2BR). The Bank “x” WRP “y” area (x=1,2 and y=A,B) is defined from the address: Bank “x” Base address + [WRPxy_STRT x 0x800] (included) to the address: Bank “x” Base address + [(WRPxy_END+1) x 0x800] (excluded). For example, to protect by WRP from the address 0x08062800 (included) to the address 0x080707FF (included): • if boot in flash is done in Bank 1, FLASH_WRP1AR register must be programmed with: – WRP1A_STRT = 0xC5. – WRP1A_END = 0xE0. WRP1B_STRT and WRP1B_END in FLASH_WRP1BR can be used instead (area “B” in Bank 1). • If the two banks are swapped, the protection must apply to bank 2, and FLASH_WRP2AR register must be programmed with: – WRP2A_STRT = 0xC5. – WRP2A_END = 0xE0. WRP2B_STRT and WRP2B_END in FLASH_WRP2BR can be used instead (area “B in Bank 2). When WRP is active, it cannot be erased or programmed. Consequently, a software mass erase cannot be performed if one area is write-protected. If an erase/program operation to a write-protected part of the Flash memory is attempted, the write protection error flag (WRPERR) is set in the FLASH_SR register. This flag is also set for any write access to: – OTP area – part of the Flash memory that can never be written like the ICP – PCROP area. Note: When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase Flash memory if the CPU debug features are connected (JTAG or single wire) or boot code is being executed from RAM or System flash, even if WRP is not activated. Note: To validate the WRP options, the option bytes must be reloaded through the OBL_LAUNCH bit in Flash control register. 104/1680 DocID024597 Rev 1 RM0351 3.6 Embedded Flash memory (FLASH) FLASH interrupts Table 12. Flash interrupt request Interrupt event Event flag Event flag/interrupt clearing method Interrupt enable control bit End of operation EOP(1) Write EOP=1 EOPIE Operation error OPERR(2) Write OPERR=1 ERRIE RDERR Write RDERR=1 RDERRIE ECCC Write ECCC=1 ECCCIE Read error ECC correction 1. EOP is set only if EOPIE is set. 2. OPERR is set only if ERRIE is set. DocID024597 Rev 1 105/1680 120 Embedded Flash memory (FLASH) RM0351 3.7 FLASH registers 3.7.1 Flash access control register (FLASH_ACR) Address offset: 0x00 Reset value: 0x0000 0600 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. SLEEP _PD DCEN ICEN PRFTEN Res. Res. Res. Res. Res. rw rw rw RUN_ DCRST ICRST PD rw rw rw rw LATENCY[2:0] rw rw rw -- Bits 31:15 Reserved, must be kept at reset value. Bit 14 SLEEP_PD: Flash Power-down mode during Sleep or Low-power sleep mode This bit determines whether the flash memory is in Power-down mode or Idle mode when the device is in Sleep or Low-power sleep mode. 0: Flash in Idle mode during Sleep and Low-power sleep modes 1: Flash in Power-down mode during Sleep and Low-power sleep modes Caution: The flash must not be put in power-down while a program or an erase operation is on-going. Bit 13 RUN_PD: Flash Power-down mode during Run or Low-power run mode This bit is write-protected with FLASH_PDKEYR. This bit determines whether the flash memory is in Power-down mode or Idle mode when the device is in Run or Low-power run mode. The flash memory can be put in power-down mode only when the code is executed from RAM. The Flash must not be accessed when RUN_PD is set. 0: Flash in Idle mode 1: Flash in Power-down mode Caution: The flash must not be put in power-down while a program or an erase operation is on-going. Bit 12 DCRST: Data cache reset 0: Data cache is not reset 1: Data cache is reset This bit can be written only when the data cache is disabled. Bit 11 ICRST: Instruction cache reset 0: Instruction cache is not reset 1: Instruction cache is reset This bit can be written only when the instruction cache is disabled. Bit 10 DCEN: Data cache enable 0: Data cache is disabled 1: Data cache is enabled 106/1680 DocID024597 Rev 1 RM0351 Embedded Flash memory (FLASH) Bit 9 ICEN: Instruction cache enable 0: Instruction cache is disabled 1: Instruction cache is enabled Bit 8 PRFTEN: Prefetch enable 0: Prefetch disabled 1: Prefetch enabled Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 LATENCY[2:0]: Latency These bits represent the ratio of the SYSCLK (system clock) period to the Flash access time. 000: Zero wait state 001: One wait state 010: Two wait sates 011: Three wait sates 100: Four wait sates others: reserved 3.7.2 Flash Power-down key register (FLASH_PDKEYR) Address offset: 0x04 Reset value: 0x0000 0000 Access: no wait state, word access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PDKEYR[31:16] w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w w w w w w w w PDKEYR[15:0] w w Bits 31:0 PDKEYR: Power-down in Run mode Flash key The following values must be written consecutively to unlock the RUN_PD bit in FLASH_ACR: PDKEY1: 0x04152637 PDKEY2: 0xFAFBFCFD 3.7.3 Flash key register (FLASH_KEYR) Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word access DocID024597 Rev 1 107/1680 120 Embedded Flash memory (FLASH) RM0351 31 30 29 28 27 26 25 24 w w w w w w w w 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 w w w w w w w w 7 6 5 4 3 2 1 0 w w w w w w w KEYR[31:16] KEYR[15:0] w w w w w w w w w Bits 31:0 KEYR: Flash key The following values must be written consecutively to unlock the FLACH_CR register allowing flash programming/erasing operations: KEY1: 0x45670123 KEY2: 0xCDEF89AB 3.7.4 Flash option key register (FLASH_OPTKEYR) Address offset: 0x0C Reset value: 0x0000 0000 Access: no wait state, word access 31 30 29 28 27 26 25 24 w w w w w w w w 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 w w w w w w w w 7 6 5 4 3 2 1 0 w w w w w w w OPTKEYR[31:16] OPTKEYR[15:0] w w w w w Bits 31:0 3.7.5 w w w w OPTKEYR: Option byte key The following values must be written consecutively to unlock the FLACH_OPTR register allowing option byte programming/erasing operations: KEY1: 0x08192A3B KEY2: 0x4C5D6E7F Flash status register (FLASH_SR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BSY r 15 14 OPTV ERR RD ERR rc_w1 rc_w1 108/1680 13 Res. 12 Res. 11 Res. 10 9 8 7 6 5 4 3 Res. FAST ERR MISS ERR PGS ERR SIZ ERR PGA ERR WRP ERR PROG ERR rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 DocID024597 Rev 1 2 1 0 Res. OP ERR EOP rc_w1 rc_w1 RM0351 Embedded Flash memory (FLASH) - Bits 31:17 Reserved, must be kept at reset value. Bit 16 BSY: Busy This indicates that a Flash operation is in progress. This is set on the beginning of a Flash operation and reset when the operation finishes or when an error occurs. Bit 15 OPTVERR: Option validity error Set by hardware when the options read may not be the one configured by the user. If option haven’t been properly loaded, OPTVERR is set again after each system reset. Cleared by writing 1. Bit 14 RDERR: PCROP read error Set by hardware when an address to be read through the D-bus belongs to a read protected area of the flash (PCROP protection). An interrupt is generated if RDERRIE is set in FLASH_CR. Cleared by writing 1. Bits 13:10 Reserved, must be kept at reset value. Bit 9 FASTERR: Fast programming error Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted due to an error (alignment, size, write protection or data miss). The corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time. Cleared by writing 1. Bit 8 MISERR: Fast programming data miss error In Fast programming mode, 32 double words must be sent to flash successively, and the new data must be sent to the flash logic control before the current data is fully programmed. MISSERR is set by hardware when the new data is not present in time. Cleared by writing 1. Bit 7 PGSERR: Programming sequence error Set by hardware when a write access to the Flash memory is performed by the code while PG or FSTPG have not been set previously. Set also by hardware when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous programming error. Cleared by writing 1. Bit 6 SIZERR: Size error Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access). Cleared by writing 1. Bit 5 PGAERR: Programming alignment error Set by hardware when the data to program cannot be contained in the same 64bit Flash memory row in case of standard programming, or if there is a change of page during fast programming. Cleared by writing 1. Bit 4 WRPERR: Write protection error Set by hardware when an address to be erased/programmed belongs to a writeprotected part (by WRP, PCROP or RDP level 1) of the Flash memory. Cleared by writing 1. DocID024597 Rev 1 109/1680 120 Embedded Flash memory (FLASH) RM0351 Bit 3 PROGERR: Programming error Set by hardware when a double-word address to be programmed contains a value different from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000'. Cleared by writing 1. Bit 2 Reserved, must be kept at reset value. Bit 1 OPERR: Operation error Set by hardware when a Flash memory operation (program / erase) completes unsuccessfully. This bit is set only if error interrupts are enabled (ERRIE = 1). Cleared by writing ‘1’. Bit 0 EOP: End of operation Set by hardware when one or more Flash memory operation (programming / erase) has been completed successfully. This bit is set only if the end of operation interrupts are enabled (EOPIE = 1). Cleared by writing 1. 3.7.6 Flash control register (FLASH_CR) Address offset: 0x14 Reset value: 0xC000 0000 Access: no wait state when no Flash memory operation is on going, word, half-word and byte access 31 30 LOCK OPT LOCK 29 28 27 26 25 24 Res. Res. OBL_ LAUNCH RD ERRIE ERR IE EOP IE rs rs rc_w1 rw rw rw 15 14 13 12 11 10 9 8 MER2 Res. Res. Res. BKER rw rw 23 22 21 20 19 Res. Res. Res. Res. Res. 7 6 5 4 3 PNB[7:0] rw rw rw rw rw rw rw rw 18 17 16 FSTPG OPT STRT STRT rw rs rs 2 1 0 MER1 PER PG rw rw rw Bit 31 LOCK: FLASH_CR Lock This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. Bit 30 OPTLOCK: Options Lock This bit is set only. When set, all bits concerning user option in FLASH_CR register and so option page are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset. Bits 29:28 Reserved, must be kept at reset value. 110/1680 DocID024597 Rev 1 RM0351 Embedded Flash memory (FLASH) Bit 27 OBL_LAUNCH: Force the option byte loading When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. It cannot be written if OPTLOCK is set. 0: Option byte loading complete 1: Option byte loading requested Bit 26 RDERRIE: PCROP read error interrupt enable This bit enables the interrupt generation when the RDERR bit in the FLASH_SR is set to 1. 0: PCROP read error interrupt disabled 1: PCROP read error interrupt enabled Bit 25 ERRIE: Error interrupt enable This bit enables the interrupt generation when the OPERR bit in the FLASH_SR is set to 1. 0: OPERR error interrupt disabled 1: OPERR error interrupt enabled Bit 24 EOPIE: End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_SR is set to 1. 0: EOP Interrupt disabled 1: EOP Interrupt enabled Bits 23:19 Reserved, must be kept at reset value Bit 18 FSTPG: Fast programming 0: Fast programming disabled 1: Fast programming enabled Bit 17 OPTSTRT: Options modification start This bit triggers an options operation when set. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_SR. Bit 16 START: Start This bit triggers an erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, an unpredictable behavior may occur without generating any error flag. This condition should be forbidden. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_SR. Bit 15 MER2: Bank 2 Mass erase This bit triggers the bank 2 mass erase (all bank 2 user pages) when set. Bits 14:12 Reserved, must be kept at reset value. Bit 11 BKER: Page number MSB (Bank selection) 0: Bank 1 is selected for page erase 1: Bank 2 is selected for page erase DocID024597 Rev 1 111/1680 120 Embedded Flash memory (FLASH) RM0351 Bits 10:3 PNB[7:0]: Page number selection These bits select the page to erase: If BKER = 0: 00000000: page 0 00000001: page 1 ... 11111111: page 255 If BKER=1 00000000: page 256 00000001: page 257 ... 11111111: page 511 Bit 2 MER1: Bank 1 Mass erase This bit triggers the bank 1 mass erase (all bank 1 user pages) when set. Bit 1 PER: Page erase 0: page erase disabled 1: page erase enabled Bit 0 PG: Programming 0: Flash programming disabled 1: Flash programming enabled 3.7.7 Flash ECC register (FLASH_ECCR) Address offset: 0x18 Reset value: 0x0000 0000 Access: no wait state when no Flash memory operation is on going, word, half-word and byte access 31 30 ECCD ECCC rc_w1 rc_w1 15 14 29 28 27 26 25 24 ECCC IE Res. Res. Res. Res. Res. 13 12 11 10 9 23 22 21 20 19 BK _ECC 17 16 Res. Res. Res. r r r r r 7 6 5 4 3 2 1 0 r r r r r r r rw 8 18 SYSF_ ECC ADDR_ECC[18:16] ADDR_ECC[15:0] r r r r r r r r r Bit 31 ECCD: ECC detection Set by hardware when two ECC errors have been detected. When this bit is set, a NMI is generated Cleared by writing 1. Bit 30 ECCD: ECC correction Set by hardware when one ECC error has been detected and corrected. An interrupt is generated if ECCIE is set. Cleared by writing 1. Bits 29:25 Reserved, must be kept at reset value. 112/1680 DocID024597 Rev 1 RM0351 Embedded Flash memory (FLASH) Bit 24 ECCIE: ECC correction interrupt enable 0: ECCC interrupt disabled 1: ECCC interrupt enabled Bits 23:21 Reserved, must be kept at reset value. Bit 20 SYSF_ECC: System Flash ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the System Flash. Bit 19 BK_ECC: ECC fail bank This bit indicates which bank is concerned by the ECC error correction or by the double ECC error detection. 0: bank 1 1: bank 2 Bits 18:0 ADDR_ECC: ECC fail address This bit indicates which address in the bank is concerned by the ECC error correction or by the double ECC error detection. 3.7.8 Flash option register (FLASH_OPTR) Address offset: 0x20 Reset value: 0xFXXX XXXX. The option bits are loaded with values from Flash memory at reset release. Access: no wait state when no Flash memory operation is on going, word, half-word and byte access 31 Res. 15 Res. 30 Res. 14 29 Res. 13 28 Res. 12 nRST_ nRST_ nRST_ SHDW STDBY STOP rw rw rw 27 Res. 11 26 25 Res. 10 Res. 24 23 SRAM2 SRAM2 nBOOT _RST _PE 1 rw rw rw 9 8 7 22 21 Res. DUAL BANK BFB2 rw rw rw rw rw rw 5 4 3 2 1 0 rw rw rw 6 BOR_LEV[2:0] rw rw 20 19 18 17 16 WWDG IWGD_ IWDG_ IWDG_ _SW STDBY StOP SW RDP[7:0] rw rw rw rw rw rw Bits 31:26 Reserved, must be kept at reset value. Bit 25 SRAM2_RST: SRAM2 Erase when system reset 0: SRAM2 erased when a system reset occurs 1: SRAM2 is not erased when a system reset occurs Bit 24 SRAM2_PE: SRAM2 parity check enable 0: SRAM2 parity check enable 1: SRAM2 parity check disable Bit 23 nBOOT1: Boot configuration Together with the BOOT0 pin, this bit selects boot mode from the Flash main memory, SRAM1 or the System memory. Refer to Section 2.5: Boot configuration. Bit 22 Reserved, must be kept at reset value. DocID024597 Rev 1 113/1680 120 Embedded Flash memory (FLASH) RM0351 Bit 21 DUALBANK: Dual-Bank on 512 KB or 256 KB Flash memory devices 0: 256 KB/512 KB Single-bank Flash: Contiguous addresses in Bank 1 1: 256 KB/512 KB Dual-bank Flash: Refer to Table 5 and Table 6. Bit 20 BFB2: Dual-bank boot 0: Dual-bank boot disable 1: Dual-bank boot enable Bit 19 WWDG_SW: Window watchdog selection 0: Hardware window watchdog 1: Software window watchdog Bit 18 IWDG_STDBY: Independent watchdog counter freeze in Standby mode 0: Independent watchdog counter is frozen in Standby mode 1: Independent watchdog counter is running in Standby mode Bit 17 IWDG_STOP: Independent watchdog counter freeze in Stop mode 0: Independent watchdog counter is frozen in Stop mode 1: Independent watchdog counter is running in Stop mode Bit 16 IDWG_SW: Independent watchdog selection 0: Hardware independent watchdog 1: Software independent watchdog Bit 15 Reserved, must be kept cleared Bit 14 nRST_SHDW 0: Reset generated when entering the Shutdown mode 1: No reset generated when entering the Shutdown mode Bit 13 nRST_STDBY 0: Reset generated when entering the Standby mode 1: No reset generate when entering the Standby mode Bit 12 nRST_STOP 0: Reset generated when entering the Stop mode 1: No reset generated when entering the Stop mode Bit 11 Reserved, must be kept cleared Bits10:8 BOR_LEV: BOR reset Level These bits contain the VDD supply level threshold that activates/releases the reset. 000: BOR Level 0. Reset level threshold is around 1.7 V 001: BOR Level 1. Reset level threshold is around 2.0 V 010: BOR Level 2. Reset level threshold is around 2.2 V 011: BOR Level 3. Reset level threshold is around 2.5 V 100: BOR Level 4. Reset level threshold is around 2.8 V Bits 7:0 RDP: Read protection level 0xAA: Level 0, read protection not active 0xCC: Level 2, chip read protection active Others: Level 1, memories read protection active 3.7.9 Flash Bank 1 PCROP Start address register (FLASH_PCROP1SR) Address offset: 0x24 Reset value: 0xFFFF XXXX 114/1680 DocID024597 Rev 1 RM0351 Embedded Flash memory (FLASH) Access: no wait state when no Flash memory operation is on going, word, half-word access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PCROP1_STRT[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept cleared Bits 15:0 PCROP1_STRT: Bank 1 PCROP area start offset PCROP1_STRT contains the first double-word of the PCROP area. 3.7.10 Flash Bank 1 PCROP End address register (FLASH_PCROP1ER) Address offset: 0x28 Reset value: 0xX000 XXXX Access: no wait state when no Flash memory operation is on going, word, half-word access. PCROP_RDP bit can be accessed with byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PCROP _RDP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rs 15 PCROP1_END[15:0] rw rw rw rw rw rw rw rw rw Bit 31 PCROP_RDP: PCROP area preserved when RDP level decreased This bit is set only. It is reset after a full mass erase due to a change of RDP from Level 1 to Level 0. 0: PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0. 1: PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase). Bits 30:16 Reserved, must be kept cleared Bits 15:0 PCROP1_END: Bank 1 PCROP area end offset PCROP1_END contains the last double-word of the bank 1 PCROP area. 3.7.11 Flash Bank 1 WRP area A address register (FLASH_WRP1AR) Address offset: 0x2C Reset value: 0x00XX 00XX Access: no wait state when no Flash memory operation is on going, word, half-word and byte access DocID024597 Rev 1 115/1680 120 Embedded Flash memory (FLASH) RM0351 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 rw rw rw rw 7 6 5 4 19 18 17 16 rw rw rw rw 3 2 1 0 rw rw rw WRP1A_END[7:0] WRP1A_STRT[7:0] rw rw rw rw rw Bits 31:24 Reserved, must be kept cleared Bits 23:16 WRP1A_END: Bank 1 WRP first area “A” end offset WRP1A_END contains the last page of the Bank 1 WRP first area. Bits 15:8 Reserved, must be kept cleared Bits 7:0 WRP1A_STRT: Bank 1 WRP first area “A” start offset WRP1A_STRT contains the first page of the Bank 1 WRP first area. 3.7.12 Flash Bank 1 WRP area B address register (FLASH_WRP1BR) Address offset: 0x30 Reset value: 0x00XX 00XX Access: no wait state when no Flash memory operation is on going, word, half-word and byte access 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 WRP1B_END[7:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw WRP1B_STRT[7:0] rw rw Bits 31:24 Reserved, must be kept cleared Bits 23:16 WRP1B_END: Bank 1 WRP second area “B” end offset WRP1B_END contains the last page of the Bank 1 WRP second area. Bits 15:8 Reserved, must be kept cleared Bits 7:0 WRP1B_STRT: Bank 1 WRP second area “B” start offset WRP1B_STRT contains the first page of the Bank 1 WRP second area. 3.7.13 Flash Bank 2 PCROP Start address register (FLASH_PCROP2SR) Address offset: 0x44 Reset value: 0xFFFF XXXX Access: no wait state when no Flash memory operation is on going, word, half-word access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 116/1680 DocID024597 Rev 1 RM0351 15 Embedded Flash memory (FLASH) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PCROP2_STRT[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept cleared Bits 15:0 PCROP2_STRT: Bank 2 PCROP area start offset PCROP2_STRT contains the first double-word of the Bank 2 PCROP area. 3.7.14 Flash Bank 2 PCROP End address register (FLASH_PCROP2ER) Address offset: 0x48 Reset value: 0x0000 XXXX Access: no wait state when no Flash memory operation is on going, word, half-word access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw PCROP2_END[15:0] rw rw Bits 31:16 Reserved, must be kept cleared Bits 15:0 PCROP2_END: Bank 2 PCROP area end offset PCROP2_END contains the last double-word of the bank 2 PCROP area. 3.7.15 Flash Bank 2 WRP area A address register (FLASH_WRP2AR) Address offset: 0x4C Reset value: 0x00XX 00XX Access: no wait state when no Flash memory operation is on going, word, half-word and byte access 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 WRP2A_END[7:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw WRP2A_STRT[7:0] rw rw rw rw rw Bits 31:24 Reserved, must be kept cleared Bits 23:16 WRP2A_END: Bank 2 WRP first area “A” end offset WRP2A_END contains the last page of the bank 2 WRP first area. Bits 15:8 Reserved, must be kept cleared Bits 7:0 WRP2A_STRT: Bank 2 WRP first area “A” start offset WRP2A_STRT contains the first page of the bank 2 WRP first area. DocID024597 Rev 1 117/1680 120 Embedded Flash memory (FLASH) 3.7.16 RM0351 Flash Bank 2 WRP area B address register (FLASH_WRP2BR) Address offset: 0x50 Reset value: 0x00XX 00XX Access: no wait state when no Flash memory operation is on going, word, half-word and byte access 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 WRP2B_END[7:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw WRP2B_STRT[7:0] rw rw rw rw rw Bits 31:24 Reserved, must be kept cleared Bits 23:16 WRP2B_END: Bank 2 WRP second area “B” end offset WRP2B_END contains the last page of the bank 2 WRP second area. Bits 15:8 Reserved, must be kept cleared Bits 7:0 WRP2B_STRT: Bank 2 WRP second area “B” start offset WRP2B_STRT contains the first page of the bank 2 WRP second area. 118/1680 DocID024597 Rev 1 0x28 FLASH_ PCROP1ER Reset value x IWDG_STOP IWDG_SW Res. nRST_SHDW nRST_STDBY nRST_STOP X X X X X X Res. Res. Res. Res. SYSF_ECC BK_ECC Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_SR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FASTERR MISERR PGSERR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_OPT KEYR 0 0 0 0 0 0 0 Reset value DocID024597 Rev 1 DCEN ICEN PRFTEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X 0 X X X 0 0 0 BOR_ LEV[2:0] 0 X X X 0 0 X X X 0 0 X X X X X X X X X Res. Res. Res. Res. Res. ICRST Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DCRST 0 RUN_PD 0 1 PNB[7:0] ADDR_ECC[18:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOP 0 1 0 0 0 PG 0 0 PER 0 0 Res. OPERR 0 0 MER1 0 Res. SLEEP_PD PDKEYR[31:0] 0 PROGERR 0 WRPERR 0 PGAERR 0 SIZERR 0 Res. BKER 0 Res. 0 RDERR MER2 0 Res. 0 Res. STRT 0 Res. 0 OPTVERR OPTSTRT 0 Res. KEYR[31:0] 0 BSY Res. FSTPG Res. Res. Res. 0 Res. Reset value Res. IWDG_STBY X Res. Res. ECCCIE 0 Res. FLASH_KEYR 0 Res. WWDG_SW X Res. Res. 0 Res. Reset value 0 Res. FLASH_ PDKEYR Res. Res. Res. BFB2 X Res. 0 Res. Res. Res. DUALBANK X Res. Res. Res. EOPIE 0 Res. ERRIE 0 Res. Res. RDERRIE 0 nBOOT1 SRAM2_PE X Res. Res. OBL_LAUNCH Res. 0 Res. Res. X Res. Res. Res. SRAM2_RST Res. Reset value Res. Res. FLASH_ PCROP1SR Res. 0 Res. 0 Res. OPTLOCK Reset value Res. FLASH_ECCR Res. 1 Res. FLASH_OPTR Res. 1 Res. 0x24 Reset value Res. 0x20 FLASH_CR Res. 0x18 Reset value Res. Reset value Res. 0x14 FLASH_ACR Res. 0x10 Reset value Res. 0x0C LOCK 0x08 ECCC 0x04 ECCD 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. 3.7.17 PCROP_RDP. RM0351 Embedded Flash memory (FLASH) FLASH register map Table 13. Flash interface - register map and reset values LATENCY [2:0] OPTKEYR[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDP[7:0] PCROP1_STRT[15:0] PCROP1_END[15:0] X X X X X X X X X X X X X X X 119/1680 120 Embedded Flash memory (FLASH) RM0351 X X X X X X X X Res. Res. Res. Res. Res. Res. Res. Reset value X X X X X X X Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. X X X X X X X X X X Res. Res. Res. Res. Res. Res. Res. X WRP2B_END[7:0] X X X DocID024597 Rev 1 X X X X X X X X X X X X X X X X X X X X X X X X X X WRP2A_STRT[7:0] X Refer to Section 2.2.2 on page 68 for the register boundary addresses. 120/1680 X Res. X X Res. X X Res. X X Res. X X PCROP2_END[15:0] Res. Res. Res. Res. Res. X X Res. Res. Res. Res. Res. Res. Res. Res. FLASH_ WRP2BR Res. 0x50 X Res. Reset value WRP2A_END[7:0] X PCROP2_STRT[15:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLASH_ WRP2AR Res. 0x4C Res. Reset value X WRP1B_STRT[7:0] X X Res. FLASH_ PCROP2ER WRP1A_STRT[7:0] X Res. WRP1B_END[7:0] Reset value 0x48 Res. Res. X Res. X Res. X Res. X Res. X Res. X Res. Res. Res. Res. Res. Res. Res. Res. FLASH_ PCROP2SR Res. Reset value 0x44 X Res. Res. Res. Res. Res. Res. FLASH_ WRP1BR Res. 0x30 X Res. Reset value WRP1A_END[7:0] Res. Res. Res. Res. Res. Res. Res. FLASH_ WRP1AR Res. 0x2C Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 13. Flash interface - register map and reset values (continued) X X X X X X X WRP2B_STRT[7:0] X X X X X X X X RM0351 Firewall (FW) 4 Firewall (FW) 4.1 Introduction The Firewall is made to protect a specific part of code or data into the Non-Volatile Memory, and/or to protect the Volatile data into the SRAM 1 from the rest of the code executed outside the protected area. 4.2 Firewall main features • • The code to protect by the Firewall (Code Segment) may be located in: – The Flash memory map – The SRAM 1 memory, if declared as an executable protected area during the Firewall configuration step. The data to protect can be located either – in the Flash memory (non-volatile data segment) – in the SRAM 1 memory (volatile data segment) The software can access these protected areas once the Firewall is opened. The Firewall can be opened or closed using a mechanism based on “call gate” (Refer to Opening the Firewall). The start address of each segment and its respective length must be configured before enabling the Firewall (Refer to Section 4.3.5: Firewall initialization). Each illegal access into these protected segments (if the Firewall is enabled) generates a reset which immediately kills the detected intrusion. Any DMA access to protected segments is forbidden whatever the Firewall state (opened or closed). It is considered as an illegal access and generates a reset. DocID024597 Rev 1 121/1680 132 Firewall (FW) RM0351 4.3 Firewall functional description 4.3.1 Firewall AMBA bus snoop The Firewall peripheral is snooping the AMBA buses on which the memories (volatile and non-volatile) are connected. A global architecture view is illustrated in Figure 5. Figure 5. STM32L4x6 firewall connection schematics $+%6ODYH $+%0DVWHU &257(;0 $+%0DVWHU '0$ % 8 6 0 $ 7 5 , ; , 1 7 ( 5 ) $ & ( [.% )/$6+ ),5(:$// 65$0 $+%6ODYH 069 4.3.2 Functional requirements There are several requirements to guaranty the highest security level by the application code/data which needs to be protected by the Firewall and to avoid unwanted Firewall alarm (reset generation). Debug consideration In debug mode, if the Firewall is opened, the accesses by the debugger to the protected segments are not blocked. For this reason, the Read out level 2 protection must be active in conjunction with the Firewall implementation. If the debug is needed, it is possible to proceed in the following way: 122/1680 • A dummy code having the same API as the protected code may be developed during the development phase of the final user code. This dummy code may send back coherent answers (in terms of function and potentially timing if needed), as the protected code should do in production phase. • In the development phase, the protected code can be given to the customer-end under NDA agreement and its software can be developed in level 0 protection. The customer- DocID024597 Rev 1 RM0351 Firewall (FW) end code needs to embed an IAP located in a write protected segment in order to allow future code updates when the production parts will be Level 2 ROP. Write protection In order to offer a maximum security level, the following points need to be respected: • It is mandatory to keep a write protection on the part of the code enabling the Firewall. This activation code should be located outside the segments protected by the Firewall. • The write protection is also mandatory on the code segment protected by the Firewall. • The sector including the reset vector must be write-protected. Interruptions management The code protected by the Firewall must not be interruptible. It is up to the user code to disable any interrupt source before executing the code protected by the Firewall. If this constraint is not respected, if an interruption comes while the protected code is executed (Firewall opened), the Firewall will be closed as soon as the interrupt subroutine is executed. When the code returns back to the protected code area, a Firewall alarm will raise since the “call gate” sequence will not be applied and a reset will be generated. Concerning the interrupt vectors and the first user sector in the Flash memory: • If the first user sector (including the reset vector) is protected by the Firewall, the NVIC vector should be reprogrammed outside the protected segment. • If the first user sector is not protected by the Firewall, the interrupt vectors may be kept at this location. There is no interruption generated by the Firewall. 4.3.3 Firewall segments The Firewall has been designed to protect three different segment areas: Code segment This segment is located into the Flash memory. It should contain the code to execute which requires the Firewall protection. The segment must be reached using the “call gate” entry sequence to open the Firewall. A system reset is generated if the “call gate” entry sequence is not respected (refer to Opening the Firewall) and if the Firewall is enabled using the FWDIS bit in the system configuration register. The length of the segment and the segment base address must be configured before enabling the Firewall (refer to Section 4.3.5: Firewall initialization). Non-volatile data segment This segment contains non-volatile data used by the protected code which must be protected by the Firewall. The access to this segment is defined into Section 4.3.4: Segment accesses and properties. The Firewall must be opened before accessing the data in this area. The Non-Volatile data segment should be located into the Flash memory. The segment length and the base address of the segment must be configured before enabling the Firewall (refer to Section 4.3.5: Firewall initialization). Volatile data segment Volatile data used by the protected code located into the code segment must be defined into the SRAM 1 memory. The access to this segment is defined into the Section 4.3.4: Segment DocID024597 Rev 1 123/1680 132 Firewall (FW) RM0351 accesses and properties. Depending on the Volatile data segment configuration, the Firewall must be opened or not before accessing this segment area. The segment length and the base address of the segment as well as the segment options must be configured before enabling the Firewall (refer to Section 4.3.5: Firewall initialization). The Volatile data segment can also be defined as executable (for the code execution) or shared using two bit of the Firewall configuration register (bit VDS for the volatile data sharing option and bit VDE for the volatile data execution capability). For more details, refer to Table 14. 4.3.4 Segment accesses and properties All DMA accesses to the protected segments are forbidden, whatever the Firewall state, and generate a system reset. Segment access depending on the Firewall state Each of the three segments has specific properties which are presented in Table 14. Table 14. Segment accesses according to the Firewall state Segment Code segment Non-volatile data segment Volatile data segment 124/1680 Firewall opened access allowed Read and execute Read and write Read and Write Execute if VDE = 1 and VDS = 0 into the Firewall configuration register Firewall closed access allowed Firewall disabled access allowed No access allowed. Any access to the segment (except the “call gate” entry) generates a system reset All accesses are allowed (according to the Flash sector protection properties in which the code is located) No access allowed All accesses are allowed (according to the Flash sector protection properties in which the code is located) No access allowed if VDS = 0 and VDE = 0 into the Firewall configuration register Read/write/execute accesses allowed if VDS = 1 (whatever VDE bit value) Execute if VDE = 1 and VDS = 0 but with a “call gate” entry to open the Firewall at first. All accesses are allowed DocID024597 Rev 1 RM0351 Firewall (FW) The Volatile data segment is a bit different from the two others. The segment can be: • Shared (VDS bit in the register) It means that the area and the data located into this segment can be shared between the protected code and the user code executed in a non-protected area. The access is allowed whether the Firewall is opened or closed or disabled. The VDS bit gets priority over the VDE bit, this last bit value being ignored in such a case. It means that the Volatile data segment can execute parts of code located there without any need to open the Firewall before executing the code. • Execute The VDE bit is considered as soon as the VDS bit = 0 in the FW_CR register. If the VDS bit = 1, refer to the description above on the Volatile data segment sharing. If VDS = 0 and VDE = 1, the Volatile data segment is executable. To avoid a system reset generation from the Firewall, the “call gate” sequence should be applied on the Volatile data segment to open the Firewall as an entry point for the code execution. Segments properties Each segment has a specific length register to define the segment size to be protected by the Firewall: CSL register for the Code segment length register, NVDSL for the Non-volatile data segment length register, and VDSL register for the Volatile data segment length register. Granularity and area ranges for each of the segments are presented in Table 15. Table 15. Segment granularity and area ranges Segment 4.3.5 Granularity Area range Code segment 256 bytes 1024 KBytes - 256 Bytes Non-volatile data segment 256 bytes 1024 KBytes - 256 Bytes Volatile data segment 64 bytes 96 KBytes - 64 Bytes Firewall initialization The initialization phase should take place at the beginning of the user code execution (refer to the Write protection). The initialization phase consists of setting up the addresses and the lengths of each segment which needs to be protected by the Firewall. It must be done before enabling the Firewall, because the enabling bit can be written once. Thus, when the Firewall is enabled, it cannot be disabled anymore until the next system reset. Once the Firewall is enabled, the accesses to the address and length segments are no longer possible. All write attempts are discarded. A segment defined with a length equal to 0 is not considered as protected by the Firewall. As a consequence, there is no reset generation from the Firewall when an access to the base address of this segment is performed. After a reset, the Firewall is disabled by default (FWDIS bit in the SYSCFG register is set). It has to be cleared to enable the Firewall feature. Below is the initialization procedure to follow: DocID024597 Rev 1 125/1680 132 Firewall (FW) RM0351 1. Configure the RCC to enable the clock to the Firewall module 2. Configure the RCC to enable the clock of the system configuration registers 3. Set the base address and length of each segment (CSSA, CSL, NVDSSA, NVDSL, VDSSA, VDSL registers) 4. Set the configuration register of the Firewall (FW_CR register) 5. Enable the Firewall clearing the FWDIS bit in the system configuration register. The Firewall configuration register (FW_CR register) is the only one which can be managed in a dynamic way even if the Firewall is enabled: 4.3.6 • when the Non-Volatile data segment is undefined (meaning the NVDSL register is equal to 0), the accesses to this register are possible whatever the Firewall state (opened or closed). • when the Non-Volatile data segment is defined (meaning the NVDSL register is different from 0), the accesses to this register are only possible when the Firewall is opened. Firewall states The Firewall has three different states as shown in Figure 6: • Disabled: The FWDIS bit is set by default after the reset. The Firewall is not active. • Closed: The Firewall protects the accesses to the three segments (Code, Non-volatile data, and Volatile data segments). • Opened: The Firewall allows access to the protected segments as defined in Section 4.3.4: Segment accesses and properties. Figure 6. Firewall functional states )LUHZDOOGLVDEOH UHVHW ,OOHJDODFFHVVHVWR WKHSURWHFWHG VHJPHQWV (QDEOHWKHILUHZDOO ):',6 3URWHFWHGFRGHMXPSV WRDQXQSURWHFWHG VHJPHQWDQG)3$ µµFDOOJDWH¶¶HQWU\ )LUHZDOO FORVHG )LUHZDOO RSHQHG &RGHSURWHFWHGMXPSV WRXQSURWHFWHG VHJPHQWV 069 126/1680 DocID024597 Rev 1 RM0351 Firewall (FW) Opening the Firewall As soon as the Firewall is enabled, it is closed. It means that most of the accesses to the protected segments are forbidden (refer to Section 4.3.4: Segment accesses and properties). In order to open the Firewall to interact with the protected segments, it is mandatory to apply the “call gate” sequence described hereafter. “call gate” sequence The “call gate” is composed of 3 words located on the first three 32-bit addresses of the base address of the code segment and of the Volatile data segment if it is declared as not shared (VDS = 0) and executable (VDE = 1). – 1st word: Dummy 32-bit words always closed in order to protect the “call gate” opening from an access due to a prefetch buffer. – 2nd and 3rd words: 2 specific 32-bit words called “call gate” and always opened. To open the Firewall, the code currently executed must jump to the 2nd word of the “call gate” and execute the code from this point. The 2nd word and 3rd word execution must not be interrupted by any intermediate instruction fetch; otherwise, the Firewall is not considered open and comes back to a close state. Then, executing the 3rd word after receiving the intermediate instruction fetch would generate a system reset as a consequence. As soon as the Firewall is opened, the protected segments can be accessed as described in Section 4.3.4: Segment accesses and properties. Closing the Firewall The Firewall is closed immediately after it is enabled (clearing the FWDIS bit in the system configuration register). To close the Firewall, the protected code must: • Write the correct value in the Firewall Pre Arm Flag into the FW_CR register. • Jump to any executable location outside the Firewall segments. If the Firewall Pre Arm Flag is not set when the protected code jumps to a non protected segment, a reset is generated. This control bit is an additional protection to avoid an undesired attempt to close the Firewall with the private information not yet cleaned (see the note below). For security reasons, following the application for which the Firewall is used, it is advised to clean all private information from CPU registers and hardware cells. DocID024597 Rev 1 127/1680 132 Firewall (FW) RM0351 4.4 Firewall registers 4.4.1 Code segment start address (FW_CSSA) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 ADD[23:16] rw 15 14 13 12 11 10 9 8 ADD[15:8] 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:8 ADD[23:8]: code segment start address The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a 256-byte granularity. Note: These bits can be written only before enabling the Firewall. Refer to Section 4.3.5: Firewall initialization. Bits 7:0 Reserved, must be kept at the reset value. 4.4.2 Code segment length (FW_CSL) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21 20 19 18 17 16 LENG[21:16] rw 15 14 13 12 11 LENG15:8] 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:22 Reserved, must be kept at the reset value. Bits 21:8 LENG[21:8]: code segment length LENG[21:8] selects the size of the code segment expressed in bytes but is a multiple of 256 bytes. The segment area is defined from {ADD[23:8],0x00} to {ADD[23:8]+LENG[21:8], 0x00} - 0x01 Note: If LENG[21:8] = 0 after enabling the Firewall, this segment is not defined, thus not protected by the Firewall. These bits can only be written before enabling the Firewall. Refer to Section 4.3.5: Firewall initialization. Bits 7:0 Reserved, must be kept at the reset value. 128/1680 DocID024597 Rev 1 RM0351 Firewall (FW) 4.4.3 Non-volatile data segment start address (FW_NVDSSA) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 ADD[23:16] rw 15 14 13 12 11 10 9 8 ADD[15:8] 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res rw Bits 31:24 Reserved, must be kept at the reset value. Bits 23:8 ADD[23:8]: Non-volatile data segment start address The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a 256-byte granularity. Note: These bits can only be written before enabling the Firewall. Refer to Section 4.3.5: Firewall initialization. Bits 7:0 Reserved, must be kept at the reset value. 4.4.4 Non-volatile data segment length (FW_NVDSL) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21 20 19 18 17 16 LENG[21:16] rw 15 14 13 12 11 LENG[15:8] 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:22 Reserved, must be kept at the reset value. Bits 21:8 LENG[21:8]: Non-volatile data segment length LENG[21:8] selects the size of the Non-volatile data segment expressed in bytes but is a multiple of 256 bytes. The segment area is defined from {ADD[23:8],0x00} to {ADD[23:8]+LENG[21:8], 0x00} - 0x01 Note: If LENG[21:8] = 0 after enabling the Firewall, this segment is not defined, thus not protected by the Firewall. These bits can only be written before enabling the Firewall. Refer to Section 4.3.5: Firewall initialization. Bits 7:0 Reserved, must be kept at the reset value. DocID024597 Rev 1 129/1680 132 Firewall (FW) 4.4.5 RM0351 Volatile data segment start address (FW_VDSSA) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADD [16] rw 15 14 13 12 11 10 9 8 7 6 ADD[15:6] 5 4 3 2 1 0 Res Res Res Res Res Res rw Bits 31:17 Reserved, must be kept at the reset value. Bits 16:6 ADD[16:6]: Volatile data segment start address The LSB bits of the start address (bit 5:0) are reserved and forced to 0 in order to allow a 64-byte granularity. Note: These bits can only be written before enabling the Firewall. Refer to Section 4.3.5: Firewall initialization Bits 5:0 Reserved, must be kept at the reset value. 4.4.6 Volatile data segment length (FW_VDSL) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LENG [16] rw 15 14 13 12 11 10 9 8 7 LENG[15:6] 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. rw Bits 31:17 Reserved, must be kept at the reset value. Bits 16:6 LENG[16:6]: non volatile data segment length LENG[16:6] selects the size of the non volatile data segment expressed in bytes but is a multiple of 64 bytes. The segment area is defined from {ADD[16:6],0x00} to {ADD[16:6]+LENG[16:6], 0x00} - 0x01 Note: If LENG[16:6] = 0 after enabling the Firewall, this segment is not defined, thus not protected by the Firewall. These bits can only be written before enabling the Firewall. Refer to Section 4.3.5: Firewall initialization. Bits 5:0 Reserved, must be kept at the reset value. 130/1680 DocID024597 Rev 1 RM0351 Firewall (FW) 4.4.7 Configuration register (FW_CR) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VDE VDS FPA rw rw rw Bits 31:3 Reserved, must be kept at the reset value. Bit 2 VDE: Volatile data execution 0: Volatile data segment cannot be executed if VDS = 0 1: Volatile data segment is declared executable whatever VDS bit value When VDS = 1, this bit has no meaning. The Volatile data segment can be executed whatever the VDE bit value. If VDS = 1, the code can be executed whatever the Firewall state (opened or closed) If VDS = 0, the code can only be executed if the Firewall is opened or applying the “call gate” entry sequence if the Firewall is closed. Refer to Segment access depending on the Firewall state. Bit 1 VDS: Volatile data shared 0: Volatile data segment is not shared and cannot be hit by a non protected executable code when the Firewall is closed. If it is accessed in such a condition, a system reset will be generated by the Firewall. 1: Volatile data segment is shared with non protected application code. It can be accessed whatever the Firewall state (opened or closed). Refer to Segment access depending on the Firewall state. Bit 0 FPA: Firewall pre arm 0: any code executed outside the protected segment when the Firewall is opened will generate a system reset. 1: any code executed outside the protected segment will close the Firewall. Refer to Closing the Firewall. This register is protected in the same way as the Non-volatile data segment (refer to Section 4.3.5: Firewall initialization). DocID024597 Rev 1 131/1680 132 0x20 132/1680 0x18 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VDE VDS FPA Reset Value Res. FW_CR Res. Reset Value Res. 0x1C Res. Reset Value Res. 0 0 0 0 DocID024597 Rev 1 0 0 LENG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 68 for the register boundary addresses. Res. Res. Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Reset Value 0 0 Res. ADD 0 Res. 0 0 0 Res. LENG 0 Res. ADD 0 Res. LENG Res. Res. Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0 FW_CSSA Res. Res. Res. Res. Res. Res. Res. Res. Offset Res. Res. Res. Res. Res. Res. Res. Res. ADD Res. Reset Value 0 Res. 0 0 Res. 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. 0 0 Res. Reset Value 0 Res. 0 Res. Reset Value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset Value Res. Res. Res. Res. Res. Res. Res. Res. Reset Value Res. Res. Res. Res. Res. Res. Res. FW_VDSL Res. FW_VDSSA Res. 0x14 FW_NVDSL Res. 0x10 Res. 0xC FW_NVDSSA Res. 0x8 FW_CSL Res. 0x4 Res. 4.4.8 Res. Firewall (FW) RM0351 Firewall register map The table below provides the Firewall register map and reset values. Table 16. Firewall register map and reset values RM0351 Cyclic redundancy check calculation unit (CRC) 5 Cyclic redundancy check calculation unit (CRC) 5.1 Introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16or 32-bit data word and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the functional safety standards, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location. 5.2 CRC main features • Fully programmable polynomial with programmable size (7, 8, 16, 32 bits). • Handles 8-,16-, 32-bit data size • Programmable CRC initial value • Single input/output 32-bit data register • Input buffer to avoid bus stall during calculation • CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size • General-purpose 8-bit register (can be used for temporary storage) • Reversibility option on I/O data DocID024597 Rev 1 133/1680 138 Cyclic redundancy check calculation unit (CRC) 5.3 RM0351 CRC functional description Figure 7. CRC calculation unit block diagram $+%EXV ELW UHDGDFFHVV 'DWDUHJLVWHU RXWSXW &5&FRPSXWDWLRQ ELW ZULWHDFFHVV 'DWDUHJLVWHU LQSXW 069 The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to input new data (write access), and holds the result of the previous CRC calculation (read access). Each write operation to the data register creates a combination of the previous CRC value (stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data word or byte by byte depending on the format of the data being written. The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned byte. For the other registers only 32-bit access is allowed. The duration of the computation depends on data width: • 4 AHB clock cycles for 32-bit • 2 AHB clock cycles for 16-bit • 1 AHB clock cycles for 8-bit An input buffer allows to immediately write a second data without waiting for any wait states due to the previous CRC calculation. The data size can be dynamically adjusted to minimize the number of write accesses for a given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write followed by a byte write. The input data can be reversed, to manage the various endianness schemes. The reversing operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits in the CRC_CR register. For example: input data 0x1A2B3C4D is used for CRC calculation as: 0x58D43CB2 with bit-reversal done by byte 0xD458B23C with bit-reversal done by half-word 0xB23CD458 with bit-reversal done on the full word The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register. The operation is done at bit level: for example, output data 0x11223344 is converted into 0x22CC4488. 134/1680 DocID024597 Rev 1 RM0351 Cyclic redundancy check calculation unit (CRC) The CRC calculator can be initialized to a programmable value using the RESET control bit in the CRC_CR register (the default value is 0xFFFFFFFF). The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR register is automatically initialized upon CRC_INIT register write access. The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It is not affected by the RESET bit in the CRC_CR register. Polynomial programmability The polynomial coefficients are fully programmable through the CRC_POL register, and the polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the POLYSIZE[1:0] bits in the CRC_CR register. Even polynomials are not supported. If the CRC data is less than 32-bit, its value can be read from the least significant bits of the CRC_DR register. To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can not be performed during a CRC calculation. As a result, if a CRC calculation is ongoing, the application must either reset it or perform a CRC_DR read before changing the polynomial. The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7. 5.4 CRC registers 5.4.1 Data register (CRC_DR) Address offset: 0x00 Reset value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DR[31:16] rw 15 14 13 12 11 10 9 8 7 DR[15:0] rw Bits 31:0 DR[31:0]: Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. DocID024597 Rev 1 135/1680 138 Cyclic redundancy check calculation unit (CRC) 5.4.2 RM0351 Independent data register (CRC_IDR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. IDR[7:0] rw Bits 31:8 Reserved, must be kept cleared. Bits 7:0 IDR[7:0]: General-purpose 8-bit data register bits These bits can be used as a temporary storage location for one byte. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register 5.4.3 Control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. REV_ OUT Res. Res. RESET Res. Res. Res. Res. Res. Res. Res. rw REV_IN[1:0] rw rw Bits 31:8 Reserved, must be kept cleared. Bit 7 REV_OUT: Reverse output data This bit controls the reversal of the bit order of the output data. 0: Bit order not affected 1: Bit-reversed output format Bits 6:5 REV_IN[1:0]: Reverse input data These bits control the reversal of the bit order of the input data 00: Bit order not affected 01: Bit reversal done by byte 10: Bit reversal done by half-word 11: Bit reversal done by word 136/1680 DocID024597 Rev 1 POLYSIZE[1:0] rw rw rs RM0351 Cyclic redundancy check calculation unit (CRC) Bits 4:3 POLYSIZE[1:0]: Polynomial size These bits control the size of the polynomial. 00: 32 bit polynomial 01: 16 bit polynomial 10: 8 bit polynomial 11: 7 bit polynomial Bits 2:1 Reserved, must be kept cleared. Bit 0 RESET: RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware 5.4.4 Initial CRC value (CRC_INIT) Address offset: 0x10 Reset value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CRC_INIT[31:16] rw 15 14 13 12 11 10 9 8 7 CRC_INIT[15:0] rw Bits 31:0 CRC_INIT: Programmable initial CRC value This register is used to write the CRC initial value. 5.4.5 CRC polynomial (CRC_POL) Address offset: 0x14 Reset value: 0x04C11DB7 31 30 29 28 27 26 25 24 23 POL[31:16] rw 15 14 13 12 11 10 9 8 7 POL[15:0] rw Bits 31:0 POL[31:0]: Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32-bits, the least significant bits have to be used to program the correct value. DocID024597 Rev 1 137/1680 138 Cyclic redundancy check calculation unit (CRC) 5.4.6 RM0351 CRC register map Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 17. CRC register map and reset values CRC_DR DR[31:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CRC_IDR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CRC_CR 0 Res. 0x08 Reset value 0x10 CRC_INIT Reset value 0x14 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 CRC_INIT[31:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CRC_POL Polynomial coefficients Reset value 0x04C11DB7 1 1 1 1 1 Refer to Section 2.2.2 on page 68 for the register boundary addresses. 138/1680 1 IDR[7:0] REV_OUT 0x04 1 Res. 1 RESET 1 Res. 1 POLYSIZE[1:0] 1 REV_IN[1:0] Reset value Res. 0x00 DocID024597 Rev 1 1 1 1 RM0351 Power control (PWR) 6 Power control (PWR) 6.1 Power supplies The STM32L4x devices require a 1.71 V to 3.6V VDD operating voltage supply. Several independent supplies (VDDA, VDDIO2, VDDUSB, VLCD), can be provided for specific peripherals: • VDD = 1.71 V to 3.6 V VDD is the external power supply for the I/Os, the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD pins. • VDDA = 1.62 V (ADCs/COMPs) / 1.8 V (DACs/OPAMPs) to 2.4 V (VREFBUF) to 3.6V VDDA is the external analog power supply for A/D converters, D/A converters, voltage reference buffer, operational amplifiers and comparators. The VDDA voltage level is independent from the VDD voltage and can be tied to ground when these peripherals are not used. • VDDUSB = 3.0 to 3.6 V VDDUSB is the external independent power supply for USB transceivers. The VDDUSB voltage level is independent from the VDD voltage and can be tied to ground when the USB is not used. • VDDIO2 = 1.08 to 3.6 V VDDIO2 is the external power supply for 14 I/Os (Port G[15:2]). The VDDIO2 voltage level is independent from the VDD voltage and can be tied to ground when PG[15:2] are not used. • VLCD = 2.5 to 3.6 V The LCD controller can be powered either externally through VLCD pin, or internally from an internal voltage generated by the embedded step-up converter. VLCD is multiplexed with PC3 which can be used as GPIO when the LCD is not used. • VBAT = 1.55 to 3.6 V VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. • VREF-, VREF+ VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage reference buffer when enabled. When VDDA < 2 V VREF+ must be equal to VDDA. When VDDA ≥ 2 V VREF+ must be between 2 V and VDDA. VREF+ can be grounded when ADC and DAC are not active. The internal voltage reference buffer supports two output voltages, which are configured with VRS bit in the VREFBUF_CSR register: – VREF+ around 2.048 V. This requires VDDA equal to or higher than 2.4 V. – VREF+ around 2.5 V. This requires VDDA equal to or higher than 2.8 V. VREF- and VREF+ pins are not available on all packages. When not available, they are bonded to VSSA and VDDA, respectively. DocID024597 Rev 1 139/1680 183 Power control (PWR) RM0351 When the VREF+ is double-bonded with VDDA in a package, the internal voltage reference buffer is not available and must be kept disable (refer to datasheet for packages pinout description). VREF- must always be equal to VSSA. An embedded linear voltage regulator is used to supply the internal digital power VCORE. VCORE is the power supply for digital peripherals, SRAM1 and SRAM2. The Flash is supplied by VCORE and VDD. Figure 8. Power supply overview 9''$GRPDLQ 9''$ 966$ [$'FRQYHUWHUV [FRPSDUDWRUV ['$FRQYHUWHUV [RSHUDWLRQDODPSOLILHUV 9ROWDJHUHIHUHQFHEXIIHU 9/&' /&' 9''86% 966 86%WUDQVFHLYHUV 9'',2GRPDLQ 9'',2 9'',2 966 ,2ULQJ 3*>@ 9''GRPDLQ 9'',2 ,2ULQJ 9&25(GRPDLQ 5HVHWEORFN 7HPSVHQVRU 966 9'' [3//+6,06, &RUH 6WDQGE\FLUFXLWU\ :DNHXSORJLF ,:'* 65$0 65$0 'LJLWDO SHULSKHUDOV 9ROWDJHUHJXODWRU /RZYROWDJHGHWHFWRU 9&25( )ODVKPHPRU\ %DFNXSGRPDLQ 9%$7 /6(FU\VWDO.RVF %.3UHJLVWHUV 5&&%'&5UHJLVWHU 57& 069 6.1.1 Independent analog peripherals supply To improve ADC and DAC conversion accuracy and to extend the supply flexibility, the analog peripherals have an independent power supply which can be separately filtered and shielded from noise on the PCB. • The analog peripherals voltage supply input is available on a separate VDDA pin. • An isolated supply ground connection is provided on VSSA pin. The VDDA supply voltage can be different from VDD. The presence of VDDA must be checked before enabling any of the analog peripherals supplied by VDDA (A/D converter, D/C converter, comparators, operational amplifiers, voltage reference buffer). 140/1680 DocID024597 Rev 1 RM0351 Power control (PWR) The VDDA supply can be monitored by the Peripheral Voltage Monitoring, and compared with two thresholds (1.65 V for PVM3 or 2.2 V for PVM4), refer to Section 6.2.3: Peripheral Voltage Monitoring (PVM) for more details. When a single supply is used, VDDA can be externally connected to VDD through the external filtering circuit in order to ensure a noise-free VDDA reference voltage. ADC and DAC reference voltage To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to VREF+ a separate reference voltage lower than VDDA. VREF+ is the highest voltage, represented by the full scale value, for an analog input (ADC) or output (DAC) signal. VREF+ can be provided either by an external reference of by an internal buffered voltage reference (VREFBUF). The internal voltage reference is enabled by setting the ENVR bit in the VREFBUF control and status register (VREFBUF_CSR). The voltage reference is set to 2.5 V when the VRS bit is set and to 2.048 V when the VRS bit is cleared. The internal voltage reference can also provide the voltage to external components through VREF+ pin. Refer to the device datasheet and to Section 18: Voltage reference buffer (VREFBUF) for further information. 6.1.2 Independent I/O supply rail Some I/Os from Port G (PG[15:2]) are supplied from a separate supply rail. The power supply for this rail can range from 1.08 to 3.6 V and is provided externally through the VDDIO2 pin. The VDDIO2 voltage level is completely independent from VDD or VDDA. The VDDIO2 pin is available only for some packages. Refer to the pinout diagrams or tables in the related device datasheet(s) for I/O list(s). After reset, the I/Os supplied by VDDIO2 are logically and electrically isolated and therefore are not available. The isolation must be removed before using any I/O from PG[15:2], by setting the IOSV bit in the PWR_CR2 register, once the VDDIO2 supply is present. The VDDIO2 supply is monitored by the Peripheral Voltage Monitoring (PVM2) and compared with the internal reference voltage (3/4 VREFINT, around 0.9V), refer to Section 6.2.3: Peripheral Voltage Monitoring (PVM) for more details. 6.1.3 Independent USB transceivers supply The USB transceivers are supplied from a separate VDDUSB power supply pin. VDDUSB range is from 3.0 V to 3.6 V and is completely independent from VDD or VDDA. After reset, the USB features supplied by VDDUSB are logically and electrically isolated and therefore are not available. The isolation must be removed before using the USB OTG peripheral, by setting the USV bit in the PWR_CR2 register, once the VDDUSB supply is present. The VDDUSB supply is monitored by the Peripheral Voltage Monitoring (PVM1) and compared with the internal reference voltage (VREFINT, around 1.2 V), refer to Section 6.2.3: Peripheral Voltage Monitoring (PVM) for more details. DocID024597 Rev 1 141/1680 183 Power control (PWR) 6.1.4 RM0351 Independent LCD supply The VLCD pin is provided to control the contrast of the glass LCD. This pin can be used in two ways: • It can receive from an external circuitry the desired maximum voltage that is provided on segment and common lines to the glass LCD by the microcontroller. • It can also be used to connect an external capacitor that is used by the microcontroller for its voltage step-up converter. This step-up converter is controlled by software to provide the desired voltage to segment and common lines of the glass LCD. The voltage provided to segment and common lines defines the contrast of the glass LCD pixels. This contrast can be reduced when you configure the dead time between frames. 6.1.5 • When an external power supply is provided to the VLCD pin, it should range from 2.5 V to 3.6 V. It does not depend on VDD. • When the LCD is based on the internal step-up converter, the VLCD pin should be connected to a capacitor (see the product datasheet for further information). Battery backup domain To retain the content of the Backup registers and supply the RTC function when VDD is turned off, the VBAT pin can be connected to an optional backup voltage supplied by a battery or by another source. The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 I/Os, allowing the RTC to operate even when the main power supply is turned off. The switch to the VBAT supply is controlled by the power-down reset embedded in the Reset block. Warning: During tRSTTEMPO (temporization at VDD startup) or after a PDR has been detected, the power switch between VBAT and VDD remains connected to VBAT. During the startup phase, if VDD is established in less than tRSTTEMPO (refer to the datasheet for the value of tRSTTEMPO) and VDD > VBAT + 0.6 V, a current may be injected into VBAT through an internal diode connected between VDD and the power switch (VBAT). If the power supply/battery connected to the VBAT pin cannot support this current injection, it is strongly recommended to connect an external low-drop diode between this power supply and the VBAT pin. If no external battery is used in the application, it is recommended to connect VBAT externally to VDD with a 100 nF external ceramic decoupling capacitor. When the backup domain is supplied by VDD (analog switch connected to VDD), the following pins are available: 142/1680 • PC13, PC14 and PC15, which can be used as GPIO pins • PC13, PC14 and PC15, which can be configured by RTC or LSE (refer to Section 34.3: RTC functional description on page 1054) • PA0/RTC_TAMP2 and PE6/RTC_TAMP3 when they are configured by the RTC as tamper pins DocID024597 Rev 1 RM0351 Note: Power control (PWR) Due to the fact that the analog switch can transfer only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive a LED). When the backup domain is supplied by VBAT (analog switch connected to VBAT because VDD is not present), the following functions are available: • PC13, PC14 and PC15 can be controlled only by RTC or LSE (refer to Section 34.3: RTC functional description) • PA0/RTC_TAMP2 and PE6/RTC_TAMP3 when they are configured by the RTC as tamper pins Backup domain access After a system reset, the backup domain (RTC registers and backup registers) is protected against possible unwanted write accesses. To enable access to the backup domain, proceed as follows: 1. Enable the power interface clock by setting the PWREN bits in the Section 8.4.19: APB1 peripheral clock enable register 1 (RCC_APB1ENR1) 2. Set the DBP bit in the Power control register 1 (PWR_CR1) to enable access to the backup domain 3. Select the RTC clock source in the Backup domain control register (RCC_BDCR). 4. Enable the RTC clock by setting the RTCEN [15] bit in the Backup domain control register (RCC_BDCR). VBAT battery charging When VDD is present, It is possible to charge the external battery on VBAT through an internal resistance. The VBAT charging is done either through a 5 kOhm resistor or through a 1.5 kOhm resistor depending on the VBRS bit value in the PWR_CR4 register. The battery charging is enabled by setting VBE bit in the PWR_CR4 register. It is automatically disabled in VBAT mode. 6.1.6 Voltage regulator Two embedded linear voltage regulators supply all the digital circuitries, except for the Standby circuitry and the backup domain. The main regulator output voltage (VCORE) can be programmed by software to two different power ranges (Range 1 and Range 2) in order to optimize the consumption depending on the system’s maximum operating frequency (refer to Section 8.2.8: Clock source frequency versus voltage scaling and to Section 3.3.3: Read access latency. The voltage regulators are always enabled after a reset. Depending on the application modes, the VCORE supply is provided either by the main regulator (MR) or by the low-power regulator (LPR). • In Run and Sleep modes, both regulators are enabled and the main regulator (MR) supplies full power to the VCORE domain (core, memories and digital peripherals). • In low-power run and low-power sleep modes, the main regulator is off and the lowpower regulator (LPR) supplies low power to the VCORE domain, preserving the DocID024597 Rev 1 143/1680 183 Power control (PWR) RM0351 contents of the registers and internal SRAM1 and SRAM2. 6.1.7 • In Stop 1 and Stop 2 modes, the main regulator is off and the low-power regulator (LPR) supplies low power to the VCORE domain, preserving the contents of the registers and of internal SRAM1 and SRAM2. However it is possible to keep the main regulator ON in Stop 1 mode. • In Standby mode with SRAM2 content preserved (RRS bit is set in the PWR_CR3 register), the main regulator (MR) is off and the low-power regulator (LPR) provides the supply to SRAM2 only. The core and digital peripherals (except Standby circuitry and backup domain) and SRAM1 are powered off. • In Standby mode, both regulators are powered off. The contents of the registers and of SRAM1 and SRAM2 is lost except for the Standby circuitry and the backup domain. • In Shutdown mode, both regulators are powered off. When exiting from Shutdown mode, a power-on reset is generated. Consequently, the contents of the registers and SRAM1 and SRAM2 is lost, except for the backup domain. Dynamic voltage scaling management The dynamic voltage scaling is a power management technique which consists in increasing or decreasing the voltage used for the digital peripherals (VCORE), according to the application performance and power consumption needs. Dynamic voltage scaling to increase VCORE is known as overvolting. It allows to improve the device performance. Dynamic voltage scaling to decrease VCORE is known as undervolting. It is performed to save power, particularly in laptop and other mobile devices where the energy comes from a battery and is thus limited. • Range 1: High-performance range. The main regulator provides a typical output voltage at 1.2 V. The system clock frequency can be up to 80 MHz. The Flash access time for read access is minimum, write and erase operations are possible. • Range 2: Low-power range. The main regulator provides a typical output voltage at 1.0 V. The system clock frequency can be up to 26 MHz.The Flash access time for a read access is increased as compared to Range 1; write and erase operations are possible. Voltage scaling is selected through the VOS bit in the PWR_CR1 register. The sequence to go from Range 1 to Range 2 is: 1. Reduce the system frequency to a value lower than 26 MHz. 2. Adjust number of wait states according new frequency target in Range2 (LATENCY bits in the FLASH_ACR). 3. Program the VOS bits to “10” in the PWR_CR1 register. The sequence to go from Range 2 to Range 1 is: 144/1680 1. Program the VOS bits to “01” in the PWR_CR1 register. 2. Wait until the VOSF flag is cleared in the PWR_SR2 register. 3. Adjust number of wait states according new frequency target in Range1 (LATENCY bits in the FLASH_ACR). 4. Increase the system frequency. DocID024597 Rev 1 RM0351 Power control (PWR) 6.2 Power supply supervisor 6.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR) The device has an integrated power-on reset (POR) / power-down reset (PDR), coupled with a brown-out reset (BOR) circuitry. The BOR is active in all power modes except Shutdown mode, and cannot be disabled. Five BOR thresholds can be selected through option bytes. During power-on, the BOR keeps the device under reset until the supply voltage VDD reaches the specified VBORx threshold. When VDD drops below the selected threshold, a device reset is generated. When VDD is above the VBORx upper limit, the device reset is released and the system can start. For more details on the brown-out reset thresholds, refer to the electrical characteristics section in the datasheet. Figure 9. Brown-out reset waveform 9'' 9%25 ULVLQJHGJH K\VWHUHVLV 9%25 IDOOLQJHGJH 7HPSRUL]DWLRQ W5677(032 5HVHW 069 1. The reset temporization tRSTTEMPO is present only for the BOR lowest threshold (VBOR0). 6.2.2 Programmable voltage detector (PVD) You can use the PVD to monitor the VDD power supply by comparing it to a threshold selected by the PLS[2:0] bits in the Power control register 2 (PWR_CR2). The PVD is enabled by setting the PVDE bit. A PVDO flag is available, in the Power status register 2 (PWR_SR2), to indicate if VDD is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when VDD drops below the PVD threshold and/or when VDD rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example, the service routine could perform emergency shutdown tasks. DocID024597 Rev 1 145/1680 183 Power control (PWR) RM0351 Figure 10. PVD thresholds 9 '' 9WKUHVKROG 39' P9 K\VWHUHVLV 39'RXWSXW 069 6.2.3 Peripheral Voltage Monitoring (PVM) Only VDD is monitored by default, as it is the only supply required for all system-related functions. The other supplies (VDDA, VDDIO2 and VDDUSB) can be independent from VDD and can be monitored with four Peripheral Voltage Monitoring (PVM). Each of the four PVMx (x=1, 2, 3, 4) is a comparator between a fixed threshold VPVMx and the selected power supply. PVMOx flags indicate if the independent power supply is higher or lower than the PVMx threshold: PVMOx flag is cleared when the supply voltage is above the PVMx threshold, and is set when the supply voltage is below the PVMx threshold. Each PVM output is connected to an EXTI line and can generate an interrupt if enabled through the EXTI registers. The PVMx output interrupt is generated when the independent power supply drops below the PVMx threshold and/or when it rises above the PVMx threshold, depending on EXTI line rising/falling edge configuration. Each PVM can remain active in Stop 1 and Stop 2 modes, and the PVM interrupt can wake up from the Stop mode. Table 18. PVM features PVM Power supply PVM threshold EXTI line PVM1 VDDUSB VPVM1 (around 1.2 V) 35 PVM2 VDDIO2 VPVM2 (around 0.9 V) 36 PVM3 VDDA VPVM3 (around 1.65 V) 37 PVM4 VDDA VPVM4 (around 2.2 V) 38 The independent supplies (VDDA, VDDIO2 and VDDUSB) are not considered as present by default, and a logical and electrical isolation is applied to ignore any information coming from the peripherals supplied by these dedicated supplies. 146/1680 • If these supplies are shorted externally to VDD, the application should assume they are available without enabling any Peripheral Voltage Monitoring. • If these supplies are independent from VDD, the Peripheral Voltage Monitoring (PVM) DocID024597 Rev 1 RM0351 Power control (PWR) can be enabled to confirm whether the supply is present or not. The following sequence must be done before using the USB_OTG peripheral: 1. 2. If VDDUSB is independent from VDD: a) Enable the PVM1 by setting PVME1 bit in the Power control register 2 (PWR_CR2). b) Wait for the PVM1 wakeup time c) Wait until PVMO1 bit is cleared in the Power status register 2 (PWR_SR2). d) Optional: Disable the PVM1 for consumption saving. Set the USV bit in the Power control register 2 (PWR_CR2) to remove the VDDUSB power isolation. The following sequence must be done before using any I/O from PG[15:2]: 1. 2. If VDDIO2 is independent from VDD: a) Enable the PVM2 by setting PVME2 bit in the Power control register 2 (PWR_CR2). b) Wait for the PVM2 wakeup time c) Wait until PVMO2 bit is cleared in the Power status register 2 (PWR_SR2). d) Optional: Disable the PVM2 for consumption saving. Set the IOSV bit in the Power control register 2 (PWR_CR2) to remove the VDDIO2 power isolation. The following sequence must be done before using any of these analog peripherals: analog to digital converters, digital to analog converters, comparators, operational amplifiers, voltage reference buffer: 1. 2. 6.3 If VDDA is independent from VDD: a) Enable the PVM3 (or PVM4) by setting PVME3 (or PVME4) bit in the Power control register 2 (PWR_CR2). b) Wait for the PVM3 (or PVM4) wakeup time c) Wait until PVMO3 (or PVMO4) bit is cleared in the Power status register 2 (PWR_SR2). d) Optional: Disable the PVM3 (or PVM4) for consumption saving. Enable the analog peripheral, which automatically removes the VDDA isolation. Low-power modes By default, the microcontroller is in Run mode after a system or a power Reset. Several lowpower modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wakeup sources. The device features seven low-power modes: • Sleep mode: CPU clock off, all peripherals including Cortex®-M4 core peripherals such as NVIC, SysTick, etc. can run and wake up the CPU when an interrupt or an event occurs. Refer to Section 6.3.4: Sleep mode. • Low-power run mode: This mode is achieved when the system clock frequency is reduced below 2 MHz. The code is executed from the SRAM or the Flash memory. The DocID024597 Rev 1 147/1680 183 Power control (PWR) RM0351 regulator is in low-power mode to minimize the regulator's operating current. Refer to Section 6.3.2: Low-power run mode (LP run). • Low-power sleep mode: This mode is entered from the Low-power run mode: Cortex®M4 is off. Refer to Section 6.3.5: Low-power sleep mode (LP sleep). • Stop 1 and Stop 2 modes: SRAM1, SRAM2 and all registers content are retained. All clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI16 and the HSE are disabled. The LSI and the LSE can be kept running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with the wakeup capability can enable the HSI16 RC during the Stop mode to detect their wakeup condition. In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode. Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. The system clock, when exiting from Stop1 or Stop2 mode, can be either MSI up to 48 MHz or HSI16, depending on the software configuration. Refer to Section 6.3.6: Stop 1 mode and Section 6.3.7: Stop 2 mode. • Standby mode: VCORE domain is powered off. However, it is possible to preserve the SRAM2 contents: – Standby mode with SRAM2 retention when the bit RRS is set in PWR_CR3 register. In this case, SRAM2 is supplied by the low-power regulator. – Standby mode when the bit RRS is cleared in PWR_CR3 register. In this case the main regulator and the low-power regulator are powered off. All clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI16 and the HSE are disabled. The LSI and the LSE can be kept running. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The system clock, when exiting Standby modes, is MSI from 1 MHz up to 8 MHz. Refer to Section 6.3.8: Standby mode. • Shutdown mode: VCORE domain is powered off. All clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI16, the LSI and the HSE are disabled. The LSE can be kept running. The system clock, when exiting the Shutdown mode, is MSI at 4 MHz. In this mode, the supply voltage monitoring is disabled and the product behavior is not guaranteed in case of a power voltage drop. Refer to Section 6.3.9: Shutdown mode. In addition, the power consumption in Run mode can be reduced by one of the following means: 148/1680 • Slowing down the system clocks • Gating the clocks to the APB and AHB peripherals when they are unused. DocID024597 Rev 1 RM0351 Power control (PWR) Figure 11. Low-power modes possible transitions /RZSRZHUVOHHSPRGH 6OHHSPRGH /RZSRZHUUXQPRGH 6KXWGRZQPRGH 6WRSPRGH 5XQPRGH 6WDQGE\PRGH 6WRSPRGH 069 DocID024597 Rev 1 149/1680 183 Power control (PWR) RM0351 Table 19. Low-power mode summary Mode name Entry WFI or Return Sleep (Sleep-now or from ISR Sleep-on-exit) WFE Low-power run Low-power sleep Stop 1 Stop 2 Wakeup source(1) Any interrupt Wakeup event Set LPR bit Clear LPR bit Set LPR bit + WFI or Return from ISR Any interrupt Set LPR bit + WFE Wakeup event system clock Voltage regulators MR LPR Same as before entering Sleep mode CPU clock OFF no effect on other clocks ON or analog clock sources ON Same as Lowpower run clock None OFF ON Same as before entering Lowpower sleep mode OFF CPU clock OFF no effect on other clocks or analog clock sources OFF ON ON ON HSI16 when Any EXTI line STOPWUCK=1 in (configured in the RCC_CFGR LPMS=”001” + SLEEPDEEP bit EXTI registers) MSI with the + WFI or Return Specific frequency before from ISR or WFE peripherals entering the Stop events mode when LPMS=”010” + STOPWUCK=0. SLEEPDEEP bit + WFI or Return All clocks OFF except LSI and LSE from ISR or WFE WKUP pin edge, RTC event, external reset in NRST pin, IWDG reset Standby LPMS=”011” + Clear RRS bit + SLEEPDEEP bit + WFI or Return from ISR or WFE WKUP pin edge, RTC event, external reset in NRST pin, IWDG reset Shutdown LPMS=”1--” + SLEEPDEEP bit + WFI or Return from ISR or WFE WKUP pin edge, RTC event, external reset in NRST pin ON OFF MSI from 1 MHz up to 8 MHz MSI 4 MHz 1. Refer to Table 20: Functionalities depending on the working mode. 150/1680 Effect on clocks LPMS=”000” + SLEEPDEEP bit + WFI or Return from ISR or WFE LPMS=”011”+ Set RRS bit + SLEEPDEEP bit + WFI or Return from ISR or WFE Standby with SRAM2 Wakeup DocID024597 Rev 1 All clocks OFF except LSE OFF OFF OFF OFF RM0351 Power control (PWR) Table 20. Functionalities depending on the working mode(1) - - CPU Y - Y - - - - - - - - - - Flash memory (up to 1 MB) (2) (2) (2) O (2) - - - - - - - - - Y Y(3) Y - Y - - - - - - (3) Y - Y - O (4) - - - - Peripheral Run O Low- LowSleep power power run sleep O O - Wakeup capability - Wakeup capability Standby Shutdow Wakeup capability Stop 2 Wakeup capability Stop 1 VBAT Y Y(3) SRAM2 (32 KB) Y (3) Y FSMC O O O O - - - - - - - - - QUADSPI O O O O - - - - - - - - - Backup Registers Y Y Y Y Y - Y - Y - Y - Y Brown-out reset (BOR) Y Y Y Y Y Y Y Y Y Y - - - Programmable Voltage Detector (PVD) O O O O O O O O - - - - - Peripheral Voltage Monitor (PVMx; x=1,2,3,4) O O O O O O O O - - - - - DMA O O O O - - - - - - - - - - (5) - - - - - - SRAM1 (up to 96 KB) Y Y High Speed Internal (HSI16) O O O O (5) High Speed External (HSE) O O O O - - - - - - - - - Low Speed Internal (LSI) O O O O O - O - O - - - - Low Speed External (LSE) O O O O O - O - O - O - O Multi-Speed Internal (MSI) O O O O - - - - - - - - - Clock Security System (CSS) O O O O - - - - - - - - - Clock Security System on LSE O O O O O O O O O O - - - RTC / Auto wakeup O O O O O O O O O O O O O Number of RTC Tamper pins 3 3 3 3 3 O 3 O 3 O 3 O 3 LCD O O O O O O O O - - - - - O(6) - - - O - - - - - - - - - - - - - - - - - - - USB OTG FS O (6) USARTx (x=1,2,3,4,5) O O O O O(7) O(7) Low-power UART (LPUART) O O O O O(7) O(7) O(7) O(7) DocID024597 Rev 1 151/1680 183 Power control (PWR) RM0351 Table 20. Functionalities depending on the working mode(1) (continued) O O O - O(8) O(8) (8) (8) - (8) - Wakeup capability O Low- LowSleep power power run sleep Standby Shutdow Wakeup capability I2Cx (x=1,2) Run Stop 2 Wakeup capability Peripheral Wakeup capability Stop 1 - - - (8) - - - - - - - - - VBAT O O O - - - - - - - - - O - - - - - - - - - O O - - - - - - - - - O O O - O - - - - - - - O O O O - - - - - - - - - DFSDM O O O O - - - - - - - - - ADCx (x=1,2,3) O O O O - - - - - - - - - DACx (x=1,2) O O O O O - - - - - - - - OPAMPx (x=1,2) O O O O O - - - - - - - - COMPx (x=1,2) O O O O O O O O - - - - - Temperature sensor O O O O - - - - - - - - - Timers (TIMx) O O O O - - - - - - - - - Low-power timer 1 (LPTIM1) O O O O O O O O - - - - - Low-power timer 2 (LPTIM2) O O O O O O - - - - - - - Independent watchdog (IWDG) O O O O O O O O O O - - - Window watchdog (WWDG) O O O O - - - - - - - - - SysTick timer O O O O - - - - - - - - - Touch sensing controller (TSC) O O O O - - - - - - - - - Random number generator (RNG) O(6) O(6) - - - - - - - - - - - AES hardware accelerator O O O O - - - - - - - - - CRC calculation unit O O O O - - - - - - - - - O (9) 5 pin s (11) 5 pin s I2C3 O O O O O SPIx (x=1,2,3) O O O O CAN O O O SDMMC1 O O SWPMI O SAIx (x=1,2) GPIOs O O O O O O O (10) 152/1680 DocID024597 Rev 1 (10) - RM0351 Power control (PWR) 1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available. 2. The Flash can be configured in power-down mode. By default, it is not in power-down mode. 3. The SRAM clock can be gated on or off. 4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register. 5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore. 6. RNG and USB peripherals are functional in voltage scaling Range 1 only. 7. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 8. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode. 10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. Debug mode By default, the debug connection is lost if the application puts the MCU in Stop1, Stop 2, Standby or Shutdown mode while the debug features are used. This is due to the fact that the Cortex®-M4 core is no longer clocked. However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to Section 44.16.1: Debug support for low-power modes. 6.3.1 Run mode Slowing down system clocks In Run mode, the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down the peripherals before entering the Sleep mode. For more details, refer to Section 8.4.3: Clock configuration register (RCC_CFGR). Peripheral clock gating In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped at any time to reduce the power consumption. To further reduce the power consumption in Sleep mode, the peripheral clocks can be disabled prior to executing the WFI or WFE instructions. The peripheral clock gating is controlled by the RCC_AHBxENR and RCC_APBxENR registers. Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in the RCC_AHBxSMENR and RCC_APBxSMENR registers. 6.3.2 Low-power run mode (LP run) To further reduce the consumption when the system is in Run mode, the regulator can be configured in low-power mode. In this mode, the system frequency should not exceed 2 MHz. DocID024597 Rev 1 153/1680 183 Power control (PWR) RM0351 Please refer to the product datasheet for more details on voltage regulator and peripherals operating conditions. I/O states in Low-power run mode In Low-power run mode, all I/O pins keep the same state as in Run mode. Entering the Low-power run mode To enter the Low-power run mode, proceed as follows: 1. Optional: Jump into the SRAM and power-down the Flash by setting the RUN_PD bit in the Flash access control register (FLASH_ACR). 2. Decrease the system clock frequency below 2 MHz. 3. Force the regulator in low-power mode by setting the LPR bit in the PWR_CR1 register. Refer to Table 21: Low-power run on how to enter the Low-power run mode. Exiting the Low-power run mode To exit the Low-power run mode, proceed as follows: 1. Force the regulator in main mode by clearing the LPR bit in the PWR_CR1 register. 2. Wait until REGLPF bit is cleared in the PWR_SR2 register. 3. Increase the system clock frequency. Refer to Table 21: Low-power run on how to exit the Low-power run mode. Table 21. Low-power run Low-power run mode 6.3.3 Description Mode entry Decrease the system clock frequency below 2 MHz LPR = 1 Mode exit LPR = 0 Wait until REGLPF = 0 Increase the system clock frequency Wakeup latency Regulator wakeup time from low-power mode Low power modes Entering low power mode Low power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M4 System Control register is set on Return from ISR. Exiting low power mode From Sleep modes, and Stop modes the MCU exit low power mode depending on the way the low power mode was entered: • If the WFI instruction or Return from ISR was used to enter the low power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device. • 154/1680 If the WFE instruction is used to enter the low power mode, the MCU exits the low DocID024597 Rev 1 RM0351 Power control (PWR) power mode as soon as an event occurs. The wakeup event can be generated either by: – NVIC IRQ interrupt. - When SEVONPEND = 0 in the Cortex®-M4 System Control register. By enabling an interrupt in the peripheral control register and in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU. - When SEVONPEND = 1 in the Cortex®-M4 System Control register. By enabling an interrupt in the peripheral control register and optionally in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. All NVIC interrupts will wakeup the MCU, even the disabled ones. Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU. – Event Configuring a EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set. It may be necessary to clear the interrupt flag in the peripheral. From Standby modes, and Shutdown modes the MCU exit low power mode through an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs (see Figure 347: RTC block diagrams). After waking up from Standby or Shutdown mode, program execution restarts in the same way as after a Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.). 6.3.4 Sleep mode I/O states in Sleep mode In Sleep mode, all I/O pins keep the same state as in Run mode. Entering the Sleep mode The Sleep mode is entered according Section : Entering low power mode, when the SLEEPDEEP bit in the Cortex®-M4 System Control register is clear. Refer to Table 22: Sleep for details on how to enter the Sleep mode. Exiting the Sleep mode The Sleep mode is exit according Section : Exiting low power mode. Refer to Table 22: Sleep for more details on how to exit the Sleep mode. DocID024597 Rev 1 155/1680 183 Power control (PWR) RM0351 Table 22. Sleep Sleep-now mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 Refer to the Cortex®-M4 System Control register. Mode entry On return from ISR while: – – SLEEPDEEP = 0 and – – SLEEPONEXIT = 1 Refer to the Cortex®-M4 System Control register. If WFI or return from ISR was used for entry Interrupt: refer to Table 41: STM32L4x6 vector table 6.3.5 Mode exit If WFE was used for entry and SEVONPEND = 0: Wakeup event: refer to Section 13.3.2: Wakeup event management Wakeup latency None If WFE was used for entry and SEVONPEND = 1: Interrupt even when disabled in NVIC: refer to Table 41: STM32L4x6 vector table or Wakeup event: refer to Section 13.3.2: Wakeup event management Low-power sleep mode (LP sleep) Please refer to the product datasheet for more details on voltage regulator and peripherals operating conditions. I/O states in Low-power sleep mode In Low-power sleep mode, all I/O pins keep the same state as in Run mode. Entering the Low-power sleep mode The Low-power sleep mode is entered from low-power run mode according Section : Entering low power mode, when the SLEEPDEEP bit in the Cortex®-M4 System Control register is clear. Refer to Table 23: Low-power sleep for details on how to enter the Low-power sleep mode. Exiting the Low-power sleep mode The low-power Sleep mode is exit according Section : Exiting low power mode. When exiting the Low-power sleep mode by issuing an interrupt or an event, the MCU is in Lowpower run mode. Refer to Table 23: Low-power sleep for details on how to exit the Low-power sleep mode. 156/1680 DocID024597 Rev 1 RM0351 Power control (PWR) Table 23. Low-power sleep Low-power sleep-now mode Description Low-power sleep mode is entered from the Low-power run mode. WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 Refer to the Cortex®-M4 System Control register. Mode entry Low-power sleep mode is entered from the Low-power run mode. On return from ISR while: – SLEEPDEEP = 0 and – SLEEPONEXIT = 1 Refer to the Cortex®-M4 System Control register. If WFI or Return from ISR was used for entry Interrupt: refer to Table 41: STM32L4x6 vector table If WFE was used for entry and SEVONPEND = 0: Wakeup event: refer to Section 13.3.2: Wakeup event management 6.3.6 Mode exit If WFE was used for entry and SEVONPEND = 1: Interrupt even when disabled in NVIC: refer to Table 41: STM32L4x6 vector table Wakeup event: refer to Section 13.3.2: Wakeup event management After exiting the Low-power sleep mode, the MCU is in Low-power run mode. Wakeup latency None Stop 1 mode The Stop 1 mode is based on the Cortex®-M4 deepsleep mode combined with the peripheral clock gating. The voltage regulator can be configured either in normal or lowpower mode. In Stop 1 mode, all clocks in the VCORE domain are stopped; the PLL, the MSI, the HSI16 and the HSE oscillators are disabled. Some peripherals with the wakeup capability (I2Cx (x=1,2,3), U(S)ARTx(x=1,2...5) and LPUART) can switch on the HSI16 to receive a frame, and switch off the HSI16 after receiving the frame if it is not a wakeup frame. In this case, the HSI16 clock is propagated only to the peripheral requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is always available in Stop 1 mode. The consumption is increased when thresholds higher than VBOR0 are used. I/O states in Stop 1 mode In the Stop 1 mode, all I/O pins keep the same state as in the Run mode. Entering the Stop 1 mode The Stop 1 mode is entered according Section : Entering low power mode, when the SLEEPDEEP bit in the Cortex®-M4 System Control register is set. Refer to Table 24: Stop 1 mode for details on how to enter the Stop 1 mode. DocID024597 Rev 1 157/1680 183 Power control (PWR) RM0351 To further reduce the power consumption in Stop 1 mode, the internal voltage regulator can be put in low-power mode. This is configured by the LPMS bits of the Power control register 1 (PWR_CR1). Stop 1 mode can be entered from Run mode and low-power run mode. If Flash memory programming is ongoing, the Stop 1 mode entry is delayed until the memory access is finished. If an access to the APB domain is ongoing, The Stop 1 mode entry is delayed until the APB access is finished. In Stop 1 mode, the following features can be selected by programming individual control bits: • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started, it cannot be stopped except by a Reset. See Section 32.3: IWDG functional description. • real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR) • Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status register (RCC_CSR). • External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR). Several peripherals can be used in Stop 1 mode and can add consumption if they are enabled and clocked by LSI or LSE, or when they request the HSI16 clock: LCD, LPTIM1, LPTIM2, I2Cx (x=1,2,3) U(S)ARTx(x=1,2...5), LPUART. The DACx (x=1,2), the OPAMPs and the comparators can be used in Stop 1 mode, the PVMx (x=1,2,3,4) and the PVD as well. If they are not needed, they must be disabled by software to save their power consumptions. The ADCx (x=1,2,3), temperature sensor and VREFBUF buffer can consume power during the Stop 1 mode, unless they are disabled before entering this mode. Exiting the Stop 1 mode The Stop 1 mode is exit according Section : Entering low power mode. Refer to Table 24: Stop 1 mode for details on how to exit Stop 1 mode. When exiting Stop 1 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is selected as system clock if the bit STOPWUCK is set in Clock configuration register (RCC_CFGR). The MSI oscillator is selected as system clock if the bit STOPWUCK is cleared. The wakeup time is shorter when HSI16 is selected as wakeup system clock. The MSI selection allows wakeup at higher frequency, up to 48 MHz. When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop 1 mode with HSI16. By keeping the internal regulator ON during Stop 1 mode, the consumption is higher although the startup time is reduced. When exiting the Stop 1 mode, the MCU is either in Run mode (Range 1 or Range 2 depending on VOS bit in PWR_CR1) or in Low-power run mode if the bit LPR is set in the PWR_CR1 register. 158/1680 DocID024597 Rev 1 RM0351 Power control (PWR) Table 24. Stop 1 mode Stop 1 mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP bit is set in Cortex®-M4 System Control register – LPMS = “000” in PWR_CR1: voltage regulator in main regulator mode – LPMS = “001” in PWR_CR1: voltage regulator in low-power regulator mode Mode entry On Return from ISR while: – SLEEPDEEP bit is set in Cortex®-M4 System Control register – SLEEPONEXIT = 1 – LPMS = “000” in PWR_CR1: voltage regulator in main regulator mode – LPMS = “001” in PWR_CR1: voltage regulator in low-power regulator mode Note: To enter Stop 1 mode, all EXTI Line pending bits (in Pending register 1 (EXTI_PR1)), and the peripheral flags generating wakeup interrupts must be cleared. Otherwise, the Stop 1 mode entry procedure is ignored and program execution continues. Mode exit If WFI or Return from ISR was used for entry Any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer to Table 41: STM32L4x6 vector table. If WFE was used for entry and SEVONPEND = 0: Any EXTI Line configured in event mode. Refer to Section 13.3.2: Wakeup event management. If WFE was used for entry and SEVONPEND = 1: Any EXTI Line configured in Interrupt mode (even if the corresponding EXTI Interrupt vector is disabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer toTable 41: STM32L4x6 vector table. Wakeup event: refer to Section 13.3.2: Wakeup event management Wakeup latency 6.3.7 Longest wakeup time between: MSI or HSI16 wakeup time and regulator wakeup time from Low-power mode + Flash wakeup time from Stop 1 mode. Stop 2 mode The Stop 2 mode is based on the Cortex®-M4 deepsleep mode combined with peripheral clock gating. In Stop 2 mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI16 and the HSE oscillators are disabled. Some peripherals with wakeup capability (I2C3 and LPUART) can switch on the HSI16 to receive a frame, and switch off the HSI16 after receiving the frame if it is not a wakeup frame. In this case the HSI16 clock is propagated only to the peripheral requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is always available in Stop 2 mode. The consumption is increased when thresholds higher than VBOR0 are used. Note: The comparators outputs, the LPUART outputs and the LPTIM1 outputs are forced to low speed (OSPEEDy=00) during the Stop 2 mode. DocID024597 Rev 1 159/1680 183 Power control (PWR) RM0351 I/O states in Stop 2 mode In the Stop 2 mode, all I/O pins keep the same state as in the Run mode. Entering Stop 2 mode The Stop 2 mode is entered according Section : Entering low power mode, when the SLEEPDEEP bit in the Cortex®-M4 System Control register is set. Refer to Table 25: Stop 2 mode for details on how to enter the Stop 2 mode. Stop 2 mode can only be entered from Run mode. It is not possible to enter Stop 2 mode from the Low-power run mode. If Flash memory programming is ongoing, the Stop 2 mode entry is delayed until the memory access is finished. If an access to the APB domain is ongoing, The Stop 2 mode entry is delayed until the APB access is finished. In Stop 2 mode, the following features can be selected by programming individual control bits: • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See Section 32.3: IWDG functional description in Section 32: Independent watchdog (IWDG). • real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR) • Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status register (RCC_CSR). • External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR). Several peripherals can be used in Stop 2 mode and can add consumption if they are enabled and clocked by LSI or LSE, or when they request the HSI16 clock: LCD, LPTIM1, I2C3, LPUART. The comparators can be used in Stop 2 mode, the PVMx (x=1,2,3,4) and the PVD as well. If they are not needed, they must be disabled by software to save their power consumptions. The ADCx, OPAMPx, DACx, temperature sensor and VREFBUF buffer can consume power during Stop 2 mode, unless they are disabled before entering this mode. All the peripherals which cannot be enabled in Stop 2 mode must be either disabled by clearing the Enable bit in the peripheral itself, or put under reset state by setting the corresponding bit in the AHB1 peripheral reset register (RCC_AHB1RSTR), AHB2 peripheral reset register (RCC_AHB2RSTR), AHB3 peripheral reset register (RCC_AHB3RSTR), APB1 peripheral reset register 1 (RCC_APB1RSTR1), APB1 peripheral reset register 2 (RCC_APB1RSTR2), APB2 peripheral reset register (RCC_APB2RSTR). Exiting Stop 2 mode The Stop 2 mode is exit according Section : Exiting low power mode. Refer to Table 25: Stop 2 mode for details on how to exit Stop 2 mode. 160/1680 DocID024597 Rev 1 RM0351 Power control (PWR) When exiting Stop 2 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is selected as system clock if the bit STOPWUCK is set in Clock configuration register (RCC_CFGR). The MSI oscillator is selected as system clock if the bit STOPWUCK is cleared. The wakeup time is shorter when HSI16 is selected as wakeup system clock. The MSI selection allows wakeup at higher frequency, up to 48 MHz. When exiting the Stop 2 mode, the MCU is in Run mode (Range 1 or Range 2 depending on VOS bit in PWR_CR1). Table 25. Stop 2 mode Stop 2 mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP bit is set in Cortex®-M4 System Control register – LPMS = “010” in PWR_CR1 Mode entry On return from ISR while: – SLEEPDEEP bit is set in Cortex®-M4 System Control register and – SLEEPONEXIT = 1 and – LPMS = “010” in PWR_CR1 Note: To enter Stop 2 mode, all EXTI Line pending bits (in Pending register 1 (EXTI_PR1)), and the peripheral flags generating wakeup interrupts must be cleared. Otherwise, the Stop mode entry procedure is ignored and program execution continues. Mode exit If WFI or Return from ISR was used for entry: Any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer to Table 41: STM32L4x6 vector table. If WFE was used for entry and SEVONPEND = 0: Any EXTI Line configured in event mode. Refer to Section 13.3.2: Wakeup event management. If WFE was used for entry and SEVONPEND = 1: Any EXTI Line configured in Interrupt mode (even if the corresponding EXTI Interrupt vector is disabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer to Table 41: STM32L4x6 vector table. Any EXTI Line configured in event mode. Refer to Section 13.3.2: Wakeup event management. Wakeup latency Longest wakeup time between: MSI or HSI16 wakeup time and regulator wakeup time from Low-power mode + Flash wakeup time from Stop 2 mode. DocID024597 Rev 1 161/1680 183 Power control (PWR) 6.3.8 RM0351 Standby mode The Standby mode allows to achieve the lowest power consumption with BOR. It is based on the Cortex®-M4 deepsleep mode, with the voltage regulators disabled (except when SRAM2 content is preserved). The PLL, the HSI16, the MSI and the HSE oscillators are also switched off. SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry (see Figure 8). SRAM2 content can be preserved if the bit RRS is set in the PWR_CR3 register. In this case the Low-power regulator is ON and provides the supply to SRAM2 only. The BOR is always available in Standby mode. The consumption is increased when thresholds higher than VBOR0 are used. I/O states in Standby mode In the Standby mode, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx registers (x=A,B,C,D,E,F,G,H)), or with a pull-down (refer to PWR_PDCRx registers (x=A,B,C,D,E,F,G,H)), or can be kept in analog state. The RTC outputs on PC13 are functional in Standby mode. PC14 and PC15 used for LSE are also functional. 5 wakeup pins (WKUPx, x=1,2...5) and the 3 RTC tampers are available. Entering Standby mode The Standby mode is entered according Section : Entering low power mode, when the SLEEPDEEP bit in the Cortex®-M4 System Control register is set. Refer to Table 26: Standby mode for details on how to enter Standby mode. In Standby mode, the following features can be selected by programming individual control bits: • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. See Section 32.3: IWDG functional description in Section 32: Independent watchdog (IWDG). • real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR) • Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status register (RCC_CSR). • External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR) Exiting Standby mode The Standby mode is exit according Section : Entering low power mode. The SBF status flag in the Power control register 3 (PWR_CR3) indicates that the MCU was in Standby mode. All registers are reset after wakeup from Standby except for Power control register 3 (PWR_CR3). Refer to Table 26: Standby mode for more details on how to exit Standby mode. 162/1680 DocID024597 Rev 1 RM0351 Power control (PWR) Table 26. Standby mode Standby mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – Set SLEEPDEEP in Cortex®-M4 System Control register – LPMS = “011” in PWR_CR1 – Clear WUFx bits in Power Control/Status register (PWR_SCR) Mode entry On return from ISR while: – SLEEPDEEP bit is set in Cortex®-M4 System Control register and – SLEEPONEXIT = 1 and – LPMS = “011” in PWR_CR1 and – Clear WUFx bits in Power Control/Status register (PWR_SCR) Mode exit WKUPx pin edge, RTC event, external Reset in NRST pin, IWDG Reset, BOR reset Wakeup latency Reset phase DocID024597 Rev 1 163/1680 183 Power control (PWR) 6.3.9 RM0351 Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. It is based on the deepsleep mode, with the voltage regulator disabled. The VCORE domain is consequently powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off. SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain. The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported. I/O states in Shutdown mode In the Shutdown mode, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx registers (x=A,B,C,D,E,F,G,H), or with a pull-down (refer to PWR_PDCRx registers (x=A,B,C,D,E,F,G,H)), or can be kept in analog state. However this configuration is lost when exiting the Shutdown mode due to the power-on reset. The RTC outputs on PC13 are functional in Shutdown mode. PC14 and PC15 used for LSE are also functional. 5 wakeup pins (WKUPx, x=1,2...5) and the 3 RTC tampers are available. Entering Shutdown mode The Shutdown mode is entered according Entering low power mode, when the SLEEPDEEP bit in the Cortex®-M4 System Control register is set. Refer to Table 27: Shutdown mode for details on how to enter Shutdown mode. In Shutdown mode, the following features can be selected by programming individual control bits: • real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR). Caution: in case of VDD power-down the RTC content will be lost. • external 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR) Exiting Shutdown mode The Shutdown mode is exit according Section : Exiting low power mode. A power-on reset occurs when exiting from Shutdown mode. All registers (except for the ones in the Backup domain) are reset after wakeup from Shutdown. Refer to Table 27: Shutdown mode for more details on how to exit Shutdown mode. 164/1680 DocID024597 Rev 1 RM0351 Power control (PWR) Table 27. Shutdown mode Shutdown mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – Set SLEEPDEEP in Cortex®-M4 System Control register – LPMS = “1XX” in PWR_CR1 Clear WUFx bits in Power Control/Status register (PWR_CSR) 6.3.10 Mode entry On return from ISR while: – SLEEPDEEP bit is set in Cortex®-M4 System Control register and – SLEEPONEXT = 1 and – LPMS = “1XX” in PWR_CR1 and Clear WUFx bits in Power Control/Status register (PWR_CSR) Mode exit WKUPx pin edge, RTC event, external Reset in NRST pin Wakeup latency Reset phase Auto-wakeup from low-power mode The RTC can be used to wakeup the MCU from low-power mode without depending on an external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for waking up from Stop (1 or 2) or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR): • Low-power 32.768 kHz external crystal oscillator (LSE OSC) This clock source provides a precise time base with very low-power consumption. • Low-power internal RC Oscillator (LSI) This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC Oscillator is designed to add minimum power consumption. To wakeup from Stop mode with an RTC alarm event, it is necessary to: • Configure the EXTI Line 18 to be sensitive to rising edge • Configure the RTC to generate the RTC alarm To wakeup from Standby mode, there is no need to configure the EXTI Line 18. To wakeup from Stop mode with an RTC wakeup event, it is necessary to: • Configure the EXTI Line 20 to be sensitive to rising edge • Configure the RTC to generate the RTC alarm To wakeup from Standby mode, there is no need to configure the EXTI Line 20. The LCD Start of frame interrupt can also be used as a periodic wakeup from Stop (1 or 2) mode. The LCD is not available in Standby mode. The LCD clock is derived from the RTC clock selected by RTCSEL[1:0]. DocID024597 Rev 1 165/1680 183 Power control (PWR) 6.4 RM0351 PWR registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 6.4.1 Power control register 1 (PWR_CR1) Address offset: 0x00 Reset value: 0x0000 0200. This register is reset after wakeup from Standby mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. LPR Res. Res. Res. DBP Res. Res. Res. Res. Res. rw VOS[1:0] rw rw rw LPMS[2:0] rw rw rw Bits 31:15 Reserved, must be kept at reset value. Bit 14 LPR: Low-power run When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead. Bits 13:11 Reserved, must be kept at reset value. Bits 10:9 VOS: Voltage scaling range selection 00: Cannot be written (forbidden by hardware) 01: Range 1 10: Range 2 11: Cannot be written (forbidden by hardware) Bit 8 DBP: Disable backup domain write protection In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. 0: Access to RTC and Backup registers disabled 1: Access to RTC and Backup registers enabled Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 LPMS[2:0]: Low-power mode selection These bits select the low-power mode entered when CPU enters the deepsleep mode. 000: Stop 1 mode with main regulator (MR) 001: Stop 1 mode with low-power regulator (LPR) 010: Stop 2 mode 011: Standby mode 1xx: Shutdown mode Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered instead of Stop 2. In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3. 166/1680 DocID024597 Rev 1 RM0351 Power control (PWR) 6.4.2 Power control register 2 (PWR_CR2) Address offset: 0x04 Reset value: 0x0000 0000. This register is reset when exiting the Standby mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. USV IOSV Res. rw rw PVME4 PVME3 PVME2 PVME1 rw rw rw rw PLS[2:0] rw rw PVDE rw rw Bits 31:11 Reserved, must be kept at reset value. Bit 10 USV: VDDUSB USB supply valid This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USB OTG_FS peripheral. If VDDUSB is not always present in the application, the PVM can be used to determine whether this supply is ready or not. 0: VDDUSB is not present. Logical and electrical isolation is applied to ignore this supply. 1: VDDUSB is valid. Bit 9 IOSV: VDDIO2 Independent I/Os supply valid This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose. Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the PVM can be used to determine whether this supply is ready or not. 0: VDDIO2 is not present. Logical and electrical isolation is applied to ignore this supply. 1: VDDIO2 is valid. Bit 8 Reserved, must be kept at reset value. Bit 7 PVME4: Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V 0: PVM4 (VDDA monitoring vs. 2.2V threshold) disable. 1: PVM4 (VDDA monitoring vs. 2.2V threshold) enable. Bit 6 PVME3: Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V 0: PVM3 (VDDA monitoring vs. 1.62V threshold) disable. 1: PVM3 (VDDA monitoring vs. 1.62V threshold) enable. Bit 5 PVME2: Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V 0: PVM2 (VDDIO2 monitoring vs. 0.9V threshold) disable. 1: PVM2 (VDDIO2 monitoring vs. 0.9V threshold) enable. DocID024597 Rev 1 167/1680 183 Power control (PWR) RM0351 Bit 4 PVME1: Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V 0: PVM1 (VDDUSB monitoring vs. 1.2V threshold) disable. 1: PVM1 (VDDUSB monitoring vs. 1.2V threshold) enable. Bits 3:1 PLS[2:0]: Power voltage detector level selection. These bits select the voltage threshold detected by the power voltage detector: 000: VPVD0 around 2.0 V 001: VPVD1 around 2.2 V 010: VPVD2 around 2.4 V 011: VPVD3 around 2.5 V 100: VPVD4 around 2.6 V 101: VPVD5 around 2.8 V 110: VPVD6 around 2.9 V 111: External input analog voltage PVD_IN (compared internally to VREFINT) Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. These bits are reset only by a system reset. Bit 0 PVDE: Power voltage detector enable 0: Power voltage detector disable. 1: Power voltage detector enable. Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. This bit is reset only by a system reset. 6.4.3 Power control register 3 (PWR_CR3) Address offset: 0x08 Reset value: 0x0000 8000. This register is not reset when exiting Standby modes and with the PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EIWF Res. Res. Res. Res. APC Res. RRS Res. Res. Res. rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bit 15 EIWF: Enable internal wakeup line 0: Internal wakeup line disable. 1: Internal wakeup line enable. Bits 14:11 Reserved, must be kept at reset value. 168/1680 DocID024597 Rev 1 EWUP5 EWUP4 EWUP3 EWUP2 EWUP1 rw rw rw rw rw RM0351 Power control (PWR) Bit 10 APC: Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os. Bit 9 Reserved, must be kept at reset value. Bit 8 RRS: SRAM2 retention in Standby mode 0: SRAM2 is powered off in Standby mode (SRAM2 content is lost). 1: SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 content is kept). Bits 7:5 Reserved, must be kept at reset value. Bit 4 EWUP5: Enable Wakeup pin WKUP5 When this bit is set, the external wakeup pin WKUP5 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register. Bit 3 EWUP4: Enable Wakeup pin WKUP4 When this bit is set, the external wakeup pin WKUP4 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register. Bit 2 EWUP3: Enable Wakeup pin WKUP3 When this bit is set, the external wakeup pin WKUP3 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register. Bit 1 EWUP2: Enable Wakeup pin WKUP2 When this bit is set, the external wakeup pin WKUP2 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register. Bit 0 EWUP1: Enable Wakeup pin WKUP1 When this bit is set, the external wakeup pin WKUP1 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register. 6.4.4 Power control register 4 (PWR_CR4) Address offset: 0x0C Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with the PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. VBRS VBE Res. Res. Res. WP5 WP4 WP3 WP2 WP1 rw rw rw rw rw rw rw DocID024597 Rev 1 169/1680 183 Power control (PWR) RM0351 Bits 31:10 Reserved, must be kept at reset value. Bit 9 VBRS: VBAT battery charging resistor selection 0: Charge VBAT through a 5 kOhms resistor 1: Charge VBAT through a 1.5 kOhms resistor Bit 8 VBE: VBAT battery charging enable 0: VBAT battery charging disable 1: VBAT battery charging enable Bits 7:5 Reserved, must be kept at reset value. Bit 4 WP5: Wakeup pin WKUP5 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP5 0: Detection on high level (rising edge) 1: Detection on low level (falling edge) Bit 3 WP4: Wakeup pin WKUP4 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP4 0: Detection on high level (rising edge) 1: Detection on low level (falling edge) Bit 2 WP3: Wakeup pin WKUP3 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP3 0: Detection on high level (rising edge) 1: Detection on low level (falling edge) Bit 1 WP2: Wakeup pin WKUP2 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP2 0: Detection on high level (rising edge) 1: Detection on low level (falling edge) Bit 0 WP1: Wakeup pin WKUP1 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP1 0: Detection on high level (rising edge) 1: Detection on low level (falling edge) Power status register 1 (PWR_SR1) 6.4.5 Address offset: 0x10 Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with the PWRRST bit in the RCC_APB1RSTR1 register. Access: 2 additional APB cycles are needed to read this register vs. a standard APB read. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WUFI Res. Res. Res. Res. Res. Res. SBF Res. Res. Res. WUF5 WUF4 WUF3 WUF2 WUF1 r r r r r r 170/1680 r DocID024597 Rev 1 RM0351 Power control (PWR) Bits 31:16 Reserved, must be kept at reset value. Bit 15 WUFI: Wakeup flag internal This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared. Bits 14:9 Reserved, must be kept at reset value. Bit 8 SBF: Standby flag This bit is set by hardware when the device enters the Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. 0: The device did not enter the Standby mode 1: The device entered the Standby mode Bits 7:5 Reserved, must be kept at reset value. Bit 4 WUF5: Wakeup flag 5 This bit is set when a wakeup event is detected on wakeup pin, WKUP5. It is cleared by writing ‘1’ in the CWUF5 bit of the PWR_SCR register. Bit 3 WUF4: Wakeup flag 4 This bit is set when a wakeup event is detected on wakeup pin,WKUP4. It is cleared by writing ‘1’ in the CWUF4 bit of the PWR_SCR register. Bit 2 WUF3: Wakeup flag 3 This bit is set when a wakeup event is detected on wakeup pin, WKUP3. It is cleared by writing ‘1’ in the CWUF3 bit of the PWR_SCR register. Bit 1 WUF2: Wakeup flag 2 This bit is set when a wakeup event is detected on wakeup pin, WKUP2. It is cleared by writing ‘1’ in the CWUF2 bit of the PWR_SCR register. Bit 0 WUF1: Wakeup flag 1 This bit is set when a wakeup event is detected on wakeup pin, WKUP1. It is cleared by writing ‘1’ in the CWUF1 bit of the PWR_SCR register. 6.4.6 Power status register 2 (PWR_SR2) Address offset: 0x14 Reset value: 0x0000 0000. This register is partially reset when exiting Standby/Shutdown modes. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PVMO 4 PVMO 3 PVMO 2 PVMO 1 PVDO VOSF Res. Res. Res. Res. Res. Res. Res. Res. r r r r r r REGLP REGLP F S r r DocID024597 Rev 1 171/1680 183 Power control (PWR) RM0351 Bits 31:16 Reserved, must be kept at reset value. Bit 15 PVMO4: Peripheral voltage monitoring output: VDDA vs. 2.2 V 0: VDDA voltage is above PVM4 threshold (around 2.2 V). 1: VDDA voltage is below PVM4 threshold (around 2.2 V). Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the PVM4 output is valid after the PVM4 wakeup time. Bit 14 PVMO3: Peripheral voltage monitoring output: VDDA vs. 1.62 V 0: VDDA voltage is above PVM3 threshold (around 1.62 V). 1: VDDA voltage is below PVM3 threshold (around 1.62 V). Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the PVM3 output is valid after the PVM3 wakeup time. Bit 13 PVMO2: Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V 0: VDDIO2 voltage is above PVM2 threshold (around 0.9 V). 1: VDDIO2 voltage is below PVM2 threshold (around 0.9 V). Note: PVMO2 is cleared when PVM2 is disabled (PVME2 = 0). After enabling PVM2, the PVM2 output is valid after the PVM2 wakeup time. Bit 12 PVMO1: Peripheral voltage monitoring output: VDDUSB vs. 1.2 V 0: VDDUSB voltage is above PVM1 threshold (around 1.2 V). 1: VDDUSB voltage is below PVM1 threshold (around 1.2 V). Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wakeup time. Bit 11 PVDO: Power voltage detector output 0: VDD is above the selected PVD threshold 1: VDD is below the selected PVD threshold Bit 10 VOSF: Voltage scaling flag A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register. 0: The regulator is ready in the selected voltage range 1: The regulator output voltage is changing to the required voltage level Bit 9 REGLPF: Low-power regulator flag This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. This bit is cleared by hardware when the regulator is ready. 0: The regulator is ready in main mode (MR) 1: The regulator is in low-power mode (LPR) Bit 8 REGLPS: Low-power regulator started This bit provides the information whether the low-power regulator is ready after a power-on reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wakeup from Standby mode time may be increased. 0: The low-power regulator is not ready 1: The low-power regulator is ready Bits 7:0 Reserved, must be kept at reset value. 172/1680 DocID024597 Rev 1 RM0351 Power control (PWR) 6.4.7 Power status clear register (PWR_SCR) Address offset: 0x18 Reset value: 0x0000 0000. Access: 3 additional APB cycles are needed to write this register vs. a standard APB write. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. CSBF Res. Res. Res. w CWUF5 CWUF4 CWUF3 CWUF2 CWUF1 w w w w w Bits 31:9 Reserved, must be kept at reset value. Bit 8 CSBF: Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register. Bits 7:5 Reserved, must be kept at reset value. Bit 4 CWUF5: Clear wakeup flag 5 Setting this bit clears the WUF5 flag in the PWR_SR1 register. Bit 3 CWUF4: Clear wakeup flag 4 Setting this bit clears the WUF4 flag in the PWR_SR1 register. Bit 2 CWUF3: Clear wakeup flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register. Bit 1 CWUF2: Clear wakeup flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register. Bit 0 CWUF1: Clear wakeup flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register. 6.4.8 Power Port A pull-up control register (PWR_PUCRA) Address offset: 0x20. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PU15 Res. PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw DocID024597 Rev 1 173/1680 183 Power control (PWR) RM0351 Bits 31:16 Reserved, must be kept at reset value. Bit 15 PU15: Port A pull-up bit 15 When set, this bit activates the pull-up on PA[15] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PD15 bit is also set. Bit 14 Reserved, must be kept at reset value. Bits 13:0 PUy: Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6.4.9 Power Port A pull-down control register (PWR_PDCRA) Address offset: 0x24. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. PD14 Res. PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:15 Reserved, must be kept at reset value. Bit 14 PD14: Port A pull-down bit 14 When set, this bit activates the pull-down on PA[14] when APC bit is set in PWR_CR3 register. Bit 13 Reserved, must be kept at reset value. Bits 12:0 PDy: Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 6.4.10 Power Port B pull-up control register (PWR_PUCRB) Address offset: 0x28. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 174/1680 DocID024597 Rev 1 RM0351 Power control (PWR) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6.4.11 Power Port B pull-down control register (PWR_PDCRB) Address offset: 0x2C. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 Res. PD3 PD2 PD1 PD0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:5 PDy: Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. Bit 4 Reserved, must be kept at reset value. Bits 3:0 PDy: Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 6.4.12 Power Port C pull-up control register (PWR_PUCRC) Address offset: 0x30. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DocID024597 Rev 1 175/1680 183 Power control (PWR) RM0351 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6.4.13 Power Port C pull-down control register (PWR_PDCRC) Address offset: 0x34. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PDy: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 6.4.14 Power Port D pull-up control register (PWR_PUCRD) Address offset: 0x38. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 176/1680 DocID024597 Rev 1 RM0351 Power control (PWR) Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6.4.15 Power Port D pull-down control register (PWR_PDCRD) Address offset: 0x3C. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PDy: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 6.4.16 Power Port E pull-up control register (PWR_PUCRE) Address offset: 0x20. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. DocID024597 Rev 1 177/1680 183 Power control (PWR) 6.4.17 RM0351 Power Port E pull-down control register (PWR_PDCRE) Address offset: 0x44. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PDy: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 6.4.18 Power Port F pull-up control register (PWR_PUCRF) Address offset: 0x48. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6.4.19 Power Port F pull-down control register (PWR_PDCRF) Address offset: 0x4C. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. 178/1680 DocID024597 Rev 1 RM0351 Power control (PWR) Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PDy: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register. 6.4.20 Power Port G pull-up control register (PWR_PUCRG) Address offset: 0x50. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6.4.21 Power Port G pull-down control register (PWR_PDCRG) Address offset: 0x54. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). DocID024597 Rev 1 179/1680 183 Power control (PWR) RM0351 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PDy: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register. 6.4.22 Power Port H pull-up control register (PWR_PUCRH) Address offset: 0x58. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU1 PU0 rw rw Bits 31:2 Reserved, must be kept at reset value. Bits 1:0 PUy: Port H pull-up bit y (y=0..1) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 6.4.23 Power Port H pull-down control register (PWR_PDCRH) Address offset: 0x5C. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 180/1680 DocID024597 Rev 1 RM0351 Power control (PWR) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PD1 PD0 rw rw Bits 31:2 Reserved, must be kept at reset value. Bits 1:0 PDy: Port H pull-down bit y (y=0..1) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. DocID024597 Rev 1 181/1680 183 0x040 182/1680 PWR_PUCRE DocID024597 Rev 1 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 Reset value PD13 Reset value PU13 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 Reset value PU14 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Reset value PD14 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 Reset value PU14 PU1 PU0 PU1 PU0 0 0 PD0 0 PD1 PU2 0 PD2 PU3 Reset value Res. Res. Res. Res. WUF4 WUF3 WUF2 WUF1 0 Res. 0 SBF 0 WUF5 REGLPF REGLPS 0 Res. 0 0 0 0 0 0 0 0 0 0 0 WP4 WP3 WP2 WP1 0 0 0 0 0 CWUF4 CWUF3 CWUF2 CWUF1 0 WP5 Res. Res. IOSV 0 0 Res. Res. 0 0 0 0 PLS [2:0] PVDE 0 EWUP1 PVME1 0 EWUP2 PVME2 0 EWUP3 PVME3 0 EWUP4 PVME4 Res. USV Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. RRS Res. APC Res. Res. Res. Res. EWF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 EWUP5 0 CWUF5 Res. Res. Res. VBE Res. VBRS Res. Res. CSBF Res. Res. Res. 0 Res. VOSF 0 Res. Res. Res. Res. 0 Res. PVDO 0 Res. Reset value Res. PVMO1 0 Res. Res. Res. 0 Res. PVMO2 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD0 PU2 PU4 0 PD3 0 0 Res. PVMO3 0 Res. WUFI Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 1 Res. PVMO4 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 PD1 PU3 PU5 0 PD4 PU6 0 PD5 PU7 0 PD6 PU8 0 PD7 PU9 0 PD8 PU10 0 PD9 PU11 0 PD10 PU12 0 PD11 0 PD12 PU13 0 Res. Res. PU15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 PD2 PU4 0 Res. Reset value PD14 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. LPR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DBP VOS [1:0] PD3 PU5 PD5 PU6 PD6 PU7 PD7 PU8 PD8 PU9 PD9 PU10 PD10 PU11 PD11 PU12 PD12 PU13 PD13 PU14 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PD14 Reset value PD15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value PU15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value PD15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value PU15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value PD15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value PU15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PWR_PDCRD Res. 0x03C PWR_PUCRD Res. 0x038 PWR_PDCRC Res. 0x034 PWR_PUCRC Res. 0x030 PWR_PDCRB Res. 0x02C PWR_PUCRB Res. 0x028 PWR_PDCRA Res. 0x024 PWR_PUCRA Res. 0x020 PWR_SCR Res. 0x018 PWR_SR2 Res. 0x014 PWR_SR1 Res. 0x010 PWR_CR4 Res. 0x00C PWR_CR3 Res. 0x008 PWR_CR2 Res. 0x004 PWR_CR1 Res. 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. 6.4.24 Res. Power control (PWR) RM0351 PWR register map and reset value table Table 28. PWR register map and reset values LPMS [2:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x05C PWR_PDCRH DocID024597 Rev 1 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU0 PD12 0 0 0 PD0 PD13 0 PU1 PD14 0 PD1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 Reset value PU15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PD15 Reset value PD15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PD15 Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PWR_PUCRH Res. 0x058 PWR_PDCRG Res. 0x054 PWR_PUCRG Res. 0x050 PWR_PDCRF Res. 0x04C PWR_PUCRF Res. 0x048 PWR_PDCRE Res. 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. RM0351 Power control (PWR) Table 28. PWR register map and reset values (continued) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer toSection 2.2.2: Memory map and register boundary addresses for the register boundary addresses. 183/1680 183 Peripherals interconnect matrix RM0351 7 Peripherals interconnect matrix 7.1 Introduction Several peripherals have direct connections between them. This allows autonomous communication and or synchronization between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections remove software latency and allow design of predictable system. Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run and sleep, Stop 1 and Stop 2 modes. 7.2 Connection summary Table 29. STM32L4x6 peripherals interconnect matrix(1) (2) TIM1 TIM8 TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 TIM15 TIM16 TIM17 LPTIM1 LPTIM2 ADC1 ADC2 ADC3 DFSDM OPAMP1 OPAMP2 DAC1 DAC2 COMP1 COMP2 DMA IRTIM Destination TIM1 - 1 1 1 1 - - - 1 - - - - 2 2 2 5 - - - - 9 - - - TIM8 - - 1 - 1 1 - - - - - - - 2 2 2 5 - - 4 4 - 9 - - TIM2 1 1 - 1 1 1 - - - - - - - 2 2 2 - - - 4 4 9 - - - TIM3 1 - 1 - 1 1 - - 1 - - - - 2 2 2 5 - - - - 9 9 - - TIM4 1 1 1 1 - 1 - - - - - - - 2 2 2 5 - - 4 4 - - - - TIM5 - 1 - - - - - - - - - - - - - - - - - 4 4 - - - - TIM6 - - - - - - - - - - - - - 2 2 2 5 - - 4 4 - - - - TIM7 - - - - - - - - - - - - - - - - 5 - - 4 4 - - - - TIM15 1 - - 1 - - - - - - - - - 2 2 2 - - - - - - 9 - - TIM16 - - - - - - - - 1 - - - - - - - 5 - - - - - - - 15 TIM17 - - - - - - - - 1 - - - - - - - - - - - - - - - 15 LPTIM1 - - - - - - - - - - - - - - - - - - - - - - - - - LPTIM2 - - - - - - - - - - - - - - - - - - - - - - - - - ADC1 3 - - - - - - - - - - - - - 10 - - - - - - - - - - ADC2 - 3 - - - - - - - - - - - - - - - - - - - - - - - ADC3 3 3 - - - - - - - - - - - - - - - - - - - - - - - DFSDM 6 6 - - - - - - 6 6 6 - - - - - - - - - - - - - - T. Sensor - - - - - - - - - - - - - 12 - 12 - - - - - - - - - VBAT - - - - - - - - - - - - - 12 - 12 - - - - - - - - - Source 184/1680 DocID024597 Rev 1 RM0351 Peripherals interconnect matrix Table 29. STM32L4x6 peripherals interconnect matrix(1) (2) (continued) ADC3 DFSDM OPAMP1 OPAMP2 DAC1 DAC2 COMP1 COMP2 DMA IRTIM - - - - - - - - - 12 12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2 2 2 5 - - 4 4 - - - - 8 8 - - - - - - - - - - - - ADC1 - LPTIM2 12 12 LPTIM1 - TIM17 - TIM16 - TIM15 - TIM7 - TIM6 - TIM5 - TIM4 - TIM3 - TIM2 - TIM8 - TIM1 Source ADC2 Destination VREFINT - - - - - - - - - - - - - 12 OPAMP1 - - - - - - - - - - - - - OPAMP2 - - - - - - - - - - - - - DAC1 - - - - - - - - - - - - - - 12 12 - DAC2 - - - - - - - - - - - - - - 12 12 - - HSE - - - - - - - - - - 7 - - - - - - LSE - - 7 - - - - - 7 7 - - - - - - MSI - - - - - - - - - - 7 - - - - LSI - - - - - - - - - 7 - - - - MCO - - - - - - - - - - 7 - - EXTI - - - - - - - - - - - - RTC - - - - - - - - - 7 - 12 12 COMP1 13 13 13 13 - - - - 13 13 13 8 8 - - - - - - - - - - - - COMP2 13 13 13 13 - - - - 13 13 13 8 8 - - - - - - - - - - - - 14 14 14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SYST ERR 14 14 USB - - - - - - - - 11 - - - - - - - - 1. Numbers in table are links to corresponding detailed sub-section in Section 7.3: Interconnection details. 2. The “-” symbol in grayed cells means no interconnect. 7.3 Interconnection details 7.3.1 From timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15/TIM16/TIM17) to timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15) Purpose Some of the TIMx timers are linked together internally for timer synchronization or chaining. When one timer is configured in Master Mode, it can reset, start, stop or clock the counter of another timer configured in Slave Mode. A description of the feature is provided in: Section 27.3.18: Timer synchronization. DocID024597 Rev 1 185/1680 192 Peripherals interconnect matrix RM0351 The modes of synchronization are detailed in: • Section 26.3.26: Timer synchronization for advanced-control timers (TIM1/TIM8) • Section 27.3.17: Timers and external trigger synchronization for general-purpose timers (TIM2/TIM3/TIM4/TIM5) • Section 28.4.17: External trigger synchronization (TIM15 only) for general-purpose timer (TIM15) Triggering signals The output (from Master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1/TIM8) following a configurable timer event. The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3 The input and output signals for TIM1/TIM8 are shown in Figure 188: Advanced-control timer block diagram. The possible master/slave connections are given in: • Table 146: TIMx internal trigger connection • Table 151: TIMx internal trigger connection • Table 154: TIMx Internal trigger connection Active power mode Run, Sleep, Low-power run, Low-power sleep. 7.3.2 From timer (TIM1/TIM2/TIM3/TIM4/TIM6/TIM8/TIM15) and EXTI to ADC (ADC1/ADC2/ADC3) Purpose General-purpose timers (TIM2/TIM3/TIM4), basic timer (TIM6), advanced-control timers (TIM1/TIM8), general-purpose timer (TIM15) and EXTI can be used to generate an ADC triggering event. TIMx synchronization is described in: Section 26.3.27: ADC synchronization (TIM1/TIM8). ADC synchronization is described in: Section 16.3.18: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN). Triggering signals The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event. The input (to ADC) is on signal EXT[15:0], JEXT[15:0]. The connection between timers and ADCs is provided in: • Table 86: ADC1, ADC2 and ADC3 - External triggers for regular channels • Table 87: ADC1, ADC2 and ADC3 - External trigger for injected channels Active power mode Run, Sleep, Low-power run, Low-power sleep. 186/1680 DocID024597 Rev 1 RM0351 7.3.3 Peripherals interconnect matrix From ADC (ADC1/ADC2/ADC3) to timer (TIM1/TIM8) Purpose ADC1/ADC2/ADC3 can provide trigger event through watchdog signals to advanced-control timers (TIM1/TIM8). A description of the ADC analog watchdog setting is provided in: Section 16.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx). Trigger settings on the timer are provided in: Section 26.3.4: External trigger input. Triggering signals The output (from ADC) is on signals ADCn_AWDx_OUT n = 1, 2, 3 (for ADC1, 2, 3) x = 1, 2, 3 (3 watchdog per ADC) and the input (to timer) on signal TIMx_ETR (external trigger). Active power mode Run, Sleep, Low-power run, Low-power sleep. 7.3.4 From timer (TIM2/TIM4/TIM5/TIM6/TIM7/TIM8) and EXTI to DAC (DAC1/DAC2) Purpose General-purpose timers (TIM2/TIM4/TIM5), basic timers (TIM6, TIM7), advanced-control timers (TIM8) and EXTI can be used as triggering event to start a DAC conversion. Triggering signals The output (from timer) is on signal TIMx_TRGO directly connected to corresponding DAC inputs. Selection of input triggers on DAC is provided in Section 17.3.6: DAC trigger selection (single and dual mode). Active power mode Run, Sleep, Low-power run, Low-power sleep. 7.3.5 From timer (TIM1/TIM3/TIM4/TIM6/TIM7/TIM8/TIM16) and EXTI to DFSDM Purpose General-purpose timers (TIM3/TIM4), basic timers (TIM6/TIM7), advanced-control timers (TIM1/TIM8), general-purpose timer (TIM16) and EXTI can be used to generate a triggering event on DFSDM module (on each possible data block DFSDM0/DFSDM1/DFSDM2/DFSDM3) and start an ADC conversion. DFSDM triggered conversion feature is described in: Section 21.3.15: Launching conversions. DocID024597 Rev 1 187/1680 192 Peripherals interconnect matrix RM0351 Triggering signals The output (from timer) is on signal TIMx_TRGO/TIMx_TRGO2 or TIM16_OC1. The input (on DFSDM) is on signal DFSDM_INTRG[0:8]. The connection between timers, EXTI and DFSDM is provided in Table 119: DFSDM triggers connection. Active power mode Run, Sleep, Low-power run, Low-power sleep. 7.3.6 From DFSDM to timer (TIM1/TIM8/TIM15/TIM16/TIM17) Purpose DFSDM can generate a timer break on advanced-control timers (TIM1/TIM8) and generalpurpose timers (TIM15/TIM16/TIM17) when a watchdog is activated (minimum or maximum threshold value crossed by analog signal) or when a short-circuit detection is made. DFSDM watchdog is described in Section 21.3.10: Analog watchdog. DFSDM short-circuit detection is described in Section 21.3.11: Short-circuit detector. Timer break is described in: • Section 26.3.16: Using the break function (TIM1/TIM8) • Section 28.4.13: Using the break function (TIM15/TIM16/TIM17) Triggering signals The output (from DFSDM) is on signals DFSDM_BREAK[0:3] directly connected to timer and ‘Ored’ with other break input signals of the timer. Active power mode Run, Sleep, Low-power run, Low-power sleep. 7.3.7 From HSE, LSE, LSI, MSI, MCO, RTC to timer (TIM2/TIM15/TIM16/TIM17) Purpose External clocks (HSE, LSE), internal clocks (LSI, MSI), microcontroller output clock (MCO), GPIO and RTC wakeup interrupt can be used as input to general-purpose timer (TIM15/16/17) channel 1. This allows to calibrate the HSI16/MSI system clocks (with TIM15/TIM16 and LSE) or LSI (with TIM16 and HSE). This is also used to precisely measure LSI (with TIM16 and HSI16) or MSI (with TIM17 and HSI16) oscillator frequency. When Low Speed External (LSE) oscillator is used, no additional hardware connections are required. This feature is described in Section 8.2.16: Internal/external clock measurement with TIM15/TIM16/TIM17. 188/1680 DocID024597 Rev 1 RM0351 Peripherals interconnect matrix External clock LSE can be used as input to general-purpose timers (TIM2) on TIM2_ETR pin, see Section 27.4.19: TIM2 option register 1 (TIM2_OR1). Active power mode Run, Sleep, Low-power run, Low-power sleep. 7.3.8 From RTC, COMP1, COMP2 to low-power timer (LPTIM1/LPTIM2) Purpose RTC alarm A/B, RTC_TAMP1/2/3 input detection, COMP1/2_OUT can be used as trigger to start LPTIM counters (LPTIM1/2). Triggering signals This trigger feature is described in Section 30.4.5: Trigger multiplexer (and following sections). The input selection is described in Table 163: LPTIM external trigger connection. Active power mode Run, Sleep, Low-power run, Low-power sleep, Stop1, Stop2 (LPTIM1 only). 7.3.9 From timer (TIM1/TIM2/TIM3/TIM8/TIM15) to comparators (COMP1/COMP2) Purpose Advanced-control timers (TIM1/TIM8), general-purpose timers (TIM2/TIM3) and generalpurpose timer (TIM15) can be used as blanking window input to COMP1/COMP2 The blanking function is described in Section 19.3.7: Comparator output blanking function. The blanking sources are given in: • Section 19.6.1: Comparator 1 control and status register (COMP1_CSR) bits 20:18 BLANKING[2:0] • Section 19.6.2: Comparator 2 control and status register (COMP2_CSR) bits 20:18 BLANKING[2:0] Triggering signals Timer output signal TIMx_Ocx are the inputs to blanking source of COMP1/COMP2. Active power mode Run, Sleep, Low-power run, Low-power sleep. 7.3.10 From ADC (ADC1) to ADC (ADC2) Purpose ADC1 can be used as a “master” to trigger ADC2 “slave” start of conversion. In dual ADC mode, the converted data of the master and slave ADCs can be read in parallel. DocID024597 Rev 1 189/1680 192 Peripherals interconnect matrix RM0351 A description of dual ADC mode is provided in: Section 16.3.30: Dual ADC modes. Triggering signals Internal to the ADCs. Active power mode Run, Sleep, Low-power run, Low-power sleep. 7.3.11 From USB to timer (TIM2) Purpose USB (OTG_FS SOF) can generate a trigger to general-purpose timer (TIM2). Connection of USB to TIM2 is described in Table 151: TIMx internal trigger connection. Triggering signals Internal signal generated by USB_FS Start Of Frame. Active power mode Run, Sleep. 7.3.12 From internal analog source to ADC (ADC1/ADC2/ADC3) and OPAMP (OPAMP1/OPAM2) Purpose Internal temperature sensor (VTS) and VBAT monitoring channel are connected to ADC1/ADC3 input channels. Internal reference voltage (VREFINT) is connected to ADC1 input channels. OPAMP1 and OPAMP2 outputs can be connected to ADC1 or ADC2 input channels through the GPIO. DAC1_OUT1 and DAC1_OUT2 outputs can be connected to ADC2 or ADC3 input channels. DAC1_OUT1 can be connected to OPAMP1_VINP. DAC1_OUT2 can be connected to OPAMP2_VINP. This is according: • Section 16.2: ADC main features • Section 16.3.11: Channel selection (SQRx, JSQRx) • Figure 60: ADC1 connectivity • Figure 62: ADC3 connectivity • Table 113: Operational amplifier possible connections Active power mode Run, Sleep, Low-power run, Low-power sleep. 190/1680 DocID024597 Rev 1 RM0351 7.3.13 Peripherals interconnect matrix From comparators (COMP1/COMP2) to timers (TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17) Purpose Comparators (COMP1/COMP2) output values can be connected to timers (TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17) input captures or TIMx_ETR signals. The connection to ETR is described in Section 26.3.4: External trigger input. Comparators (COMP1/COMP2) output values can also generate break input signals for timers (TIM1/TIM8) on input pins TIMx_BKIN or TIMx_BKIN2 through GPIO alternate function selection using open drain connection of IO, see Section 26.3.17: Bidirectional break inputs. The possible connections are given in: • Section 26.4.21: TIM1 option register 1 (TIM1_OR1) • Section 26.4.22: TIM8 option register 1 (TIM8_OR1) • Section 26.4.26: TIM1 option register 2 (TIM1_OR2) • Section 26.4.28: TIM8 option register 2 (TIM8_OR2) • Section 27.4.19: TIM2 option register 1 (TIM2_OR1) • Section 27.4.20: TIM3 option register 1 (TIM3_OR1) • Section 27.4.21: TIM2 option register 2 (TIM2_OR2) • Section 27.4.22: TIM3 option register 2 (TIM3_OR2) • Section 28.3: TIM16 and TIM17 main features Active power mode Run, Sleep, Low-power run, Low-power sleep. 7.3.14 From system errors to timers (TIM1/TIM8/TIM15/TIM16/TIM17) Purpose CSS, CPU hardfault, RAM parity error, FLASH ECC double error detection, PVD can generate system errors in the form of timer break toward timers (TIM1/TIM8/TIM15/TIM16/TIM17). The purpose of the break function is to protect power switches driven by PWM signals generated by the timers. List of possible source of break are described in: • Section 26.3.16: Using the break function (TIM1/TIM8) • Section 28.4.13: Using the break function (TIM15/TIM16/TIM17) • Section Figure 297.: TIM15 block diagram • Section Figure 298.: TIM16 and TIM17 block diagram Active power mode Run, Sleep, Low-power run, Low-power sleep. DocID024597 Rev 1 191/1680 192 Peripherals interconnect matrix 7.3.15 RM0351 From timers (TIM16/TIM17) to IRTIM Purpose General-purpose timer (TIM16/TIM17) output channel TIMx_OC1 are used to generate the waveform of infrared signal output. The functionality is described in Section 31: Infrared interface (IRTIM). Active power mode Run, Sleep, Low-power run, Low-power sleep. 192/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) 8 Reset and clock control (RCC) 8.1 Reset There are three types of reset, defined as system reset, power reset and backup domain reset. 8.1.1 Power reset A power reset is generated when one of the following events occurs: 1. a Brown-out reset (BOR). 2. when exiting from Standby mode. 3. when exiting from Shutdown mode. A Brown-out reset, including power-on or power-down reset (POR/PDR), sets all registers to their reset values except the Backup domain. When exiting Standby mode, all registers in the VCORE domain are set to their reset value. Registers outside the VCORE domain (RTC, WKUP, IWDG, and Standby/Shutdown modes control) are not impacted. When exiting Shutdown mode, a Brown-out reset is generated, resetting all registers except those in the Backup domain. 8.1.2 System reset A system reset sets all registers to their reset values except the reset flags in the clock control/status register (RCC_CSR) and the registers in the Backup domain. A system reset is generated when one of the following events occurs: 1. A low level on the NRST pin (external reset) 2. Window watchdog event (WWDG reset) 3. Independent watchdog event (IWDG reset) 4. A firewall event (FIREWALL reset) 5. A software reset (SW reset) (see Software reset) 6. Low-power mode security reset (see Low-power mode security reset) 7. Option byte loader reset (see Option byte loader reset) 8. A Brown-out reset The reset source can be identified by checking the reset flags in the Control/Status register, RCC_CSR (see Section 8.4.30: Control/status register (RCC_CSR)). These sources act on the NRST pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at address 0x0000_0004 in the memory map. The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal reset source. In case of an external reset, the reset pulse is generated while the NRST pin is asserted low. In case on an internal reset, the internal pull-up RPU is deactivated in order to save the power consumption through the pull-up resistor. DocID024597 Rev 1 193/1680 267 Reset and clock control (RCC) RM0351 Figure 12. Simplified diagram of the reset circuit sͬs ZWh džƚĞƌŶĂů ƌĞƐĞƚ EZ^d )LOWHU 3XOVH JHQHUDWRU PLQȝV ^LJƐƚĞŵƌĞƐĞƚ tt'ƌĞƐĞƚ /t'ƌĞƐĞƚ &ŝƌĞǁĂůůƌĞƐĞƚ ^ŽĨƚǁĂƌĞƌĞƐĞƚ >ŽǁͲƉŽǁĞƌŵĂŶĂŐĞƌƌĞƐĞƚ KƉƚŝŽŶďLJƚĞůŽĂĚĞƌƌĞƐĞƚ KZƌĞƐĞƚ 069 069 Software reset The SYSRESETREQ bit in Cortex®-M4 Application Interrupt and Reset Control Register must be set to force a software reset on the device (refer to the STM32F3xx/F4xx/L4xx Cortex®-M4 programming manual (PM0214)). Low-power mode security reset To prevent that critical applications mistakenly enter a low-power mode, two low-power mode security resets are available. If enabled in option bytes, the resets are generated in the following conditions: 1. Entering Standby mode: this type of reset is enabled by resetting nRST_STDBY bit in User option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode. 2. Entering Stop mode: this type of reset is enabled by resetting nRST_STOP bit in User option bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode. 3. Entering Shutdown mode: this type of reset is enabled by resetting nRST_SHDW bit in User option bytes. In this case, whenever a Shutdown mode entry sequence is successfully executed, the device is reset instead of entering Shutdown mode. For further information on the User Option Bytes, refer to Section 3.4.1: Option bytes description. Option byte loader reset The option byte loader reset is generated when the OBL_LAUNCH bit (bit 27) is set in the FLASH_CR register. This bit is used to launch the option byte loading by software. 8.1.3 Backup domain reset The backup domain has two specific resets. A backup domain reset is generated when one of the following events occurs: 194/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) 1. Software reset, triggered by setting the BDRST bit in the Backup domain control register (RCC_BDCR). 2. VDD or VBAT power on, if both supplies have previously been powered off. A backup domain reset only affects the LSE oscillator, the RTC, the Backup registers and the RCC Backup domain control register. 8.2 Clocks Four different clock sources can be used to drive the system clock (SYSCLK): • HSI16 (high speed internal)16 MHz RC oscillator clock • MSI (multispeed internal) RC oscillator clock • HSE oscillator clock, from 4 to 48 MHz • PLL clock The MSI is used as system clock source after startup from Reset, configured at 4 MHz. The devices have the following additional clock sources: • 32 kHz low speed internal RC (LSI RC) which drives the independent watchdog and optionally the RTC used for Auto-wakeup from Stop and Standby modes. • 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the realtime clock (RTCCLK). Each clock source can be switched on or off independently when it is not used, to optimize power consumption. Several prescalers can be used to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB, the APB1 and the APB2 domains is 80 MHz. DocID024597 Rev 1 195/1680 267 Reset and clock control (RCC) RM0351 All the peripheral clocks are derived from their bus clock (HCLK, PCLK1 or PCLK2) except: • The 48 MHz clock, used for USB OTG FS, SDMMC and RNG. This clock is derived (selected by software) from one of the three following sources: – main PLL VCO (PLL48M1CLK) – PLLSAI1 VCO (PLL48M2CLK) – MSI clock. When the MSI clock is auto-trimmed with the LSE, it can be used by the USB OTG FS device. • • The ADCs clock which is derived (selected by software) from one of the three following sources: – system clock (SYSCLK) – PLLSAI1 VCO (PLLADC1CLK) – PLLSAI2 VCO (PLLADC2CLK). The U(S)ARTs clocks which are derived (selected by software) from one of the four following sources: – system clock (SYSCLK) – HSI16 clock – LSE clock – APB1 or APB2 clock (PCLK1 or PCLK2 depending on which APB is mapped the U(S)ART) The wakeup from Stop mode is supported only when the clock is HSI16 or LSE. • The I2Cs clocks which are derived (selected by software) from one of the three following sources: – system clock (SYSCLK) – HSI16 clock – APB1 clock (PCLK1) The wakeup from Stop mode is supported only when the clock is HSI16. • • The SAI1 and SAI2 clocks which are derived (selected by software) from one of the four following sources: – an external clock mapped on SAI1_EXTCLK for SAI1 and SAI2_EXTCLK for SAI2. – PLLSAI1 VCO (PLLSAI1CLK) – PLLSAI2 VCO (PLLSAI2CLK) – main PLL VCO (PLLSAI3CLK) The SWPMI1 clock which is derived (selected by software) from one of the two following sources: – HSI16 clock – APB1 clock (PCLK1) The wakeup from Stop mode is supported only when the clock is HSI16. • 196/1680 The low-power timers (LPTIMx) clock which are derived (selected by software) from one of the five following sources: – LSI clock – LSE clock – HSI16 clock DocID024597 Rev 1 RM0351 Reset and clock control (RCC) – APB1 clock (PCLK1) – External clock mapped on LPTIMx_IN1 The functionality in Stop mode (including wakeup) is supported only when the clock is LSI or LSE, or in external clock mode. • The RTC and LCD clock which is derived (selected by software) from one of the three following sources: – LSE clock – LSI clock – HSE clock divided by 32 The functionality in Stop mode (including wakeup) is supported only when the clock is LSI or LSE. • The IWDG clock which is always the LSI clock. The RCC feeds the Cortex® System Timer (SysTick) external clock with the AHB clock (HCLK) divided by 8. The SysTick can work either with this clock or directly with the Cortex® clock (HCLK), configurable in the SysTick Control and Status Register. FCLK acts as Cortex®-M4 free-running clock. For more details refer to the STM32F3 and STM32F4 Series Cortex®-M4 programming manual (PM0214) DocID024597 Rev 1 197/1680 267 Reset and clock control (RCC) RM0351 Figure 13. Clock tree WR,:'* /6,5&N+] /6&2 WR57&DQG/&' 26&B287 /6(26& N+] 26&B,1 /6( /6, +6( 0&2 ĺ WR3:5 6<6&/. +6, WR$+%EXVFRUHPHPRU\DQG'0$ &ORFN VRXUFH FRQWURO 26&B287 +6(26& 0+] 26&B,1 $+% 35(6& +6( &ORFN GHWHFWRU +&/. )&/.&RUWH[IUHHUXQQLQJFORFN WR&RUWH[V\VWHPWLPHU 06, +6, 6<6&/. $3% 35(6& 3&/. WR$3%SHULSKHUDOV [RU[ +6,5& 0+] /6( +6, 6<6&/. WR86$57[ ; WR/38$57 +6, 6<6&/. 06,5& N+]±0+] WR,&[ [ /6, /6( +6, WR/37,0[ [ +6, 06, 3// 0 3 3//6$,&/. 4 3//0&/. 5 3//&/. 3 3//6$,&/. 4 3//0&/. 5 3//$'&&/. 3 3//6$,&/. +6, $3% 35(6& +6( WR6:30, 3&/. WR$3%SHULSKHUDOV [RU[ WR7,0[ [ /6( +6, 6<6&/. 3//6$, 06, 4 WR 86$57 0+]FORFNWR86%51*6'00& 6<6&/. 3//6$, WR$'& WR6$, 3//$'&&/. 5 WR7,0[ [ 6$,B(;7&/. WR6$, 6$,B(;7&/. 069 1. For full details about the internal and external clock source characteristics, please refer to the “Electrical 198/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) characteristics” section in your device datasheet. 2. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). When the programmable factor is ‘1’, the AHB prescaler must be equal to ‘1’. 8.2.1 HSE clock The high speed external clock signal (HSE) can be generated from two possible clock sources: • HSE external crystal/ceramic resonator • HSE user external clock The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. Figure 14. HSE/ LSE clock sources Clock source External clock Hardware configuration OSC_IN OSC_OUT GPIO External source OSC_IN OSC_OUT Crystal/Ceramic resonators CL1 DocID024597 Rev 1 Load capacitors CL2 199/1680 267 Reset and clock control (RCC) RM0351 External crystal/ceramic resonator (HSE crystal) The 4 to 48 MHz external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware configuration is shown in Figure 14. Refer to the electrical characteristics section of the datasheet for more details. The HSERDY flag in the Clock control register (RCC_CR) indicates if the HSE oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER). The HSE Crystal can be switched on and off using the HSEON bit in the Clock control register (RCC_CR). External source (HSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 48 MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control register (RCC_CR). The external clock signal (square, sinus or triangle) with ~40-60 % duty cycle depending on the frequency (refer to the datasheet) has to drive the OSC_IN pin while the OSC_OUT pin can be used a GPIO. See Figure 14. 8.2.2 HSI16 clock The HSI16 clock signal is generated from an internal 16 MHz RC Oscillator. The HSI16 RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator. The HSI16 clock can be selected as system clock after wakeup from Stop modes (Stop 1 or Stop 2). Refer to Section 8.3: Low-power modes. It can also be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 8.2.9: Clock security system (CSS). Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1 % accuracy at TA=25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Internal clock sources calibration register (RCC_ICSCR). If the application is subject to voltage or temperature variations this may affect the RC oscillator speed. You can trim the HSI16 frequency in the application using the HSITRIM[4:0] bits in the Internal clock sources calibration register (RCC_ICSCR). For more details on how to measure the HSI16 frequency variation, refer to Section 8.2.16: Internal/external clock measurement with TIM15/TIM16/TIM17. The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI16 RC is stable or not. At startup, the HSI16 RC output clock is not released until this bit is set by hardware. The HSI16 RC can be switched on and off using the HSION bit in the Clock control register (RCC_CR). 200/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) The HSI16 signal can also be used as a backup source (Auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 8.2.9: Clock security system (CSS) on page 204. 8.2.3 MSI clock The MSI clock signal is generated from an internal RC oscillator. Its frequency range can be adjusted by software by using the MSIRANGE[3:0] bits in the Clock control register (RCC_CR). Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, 1 MHz, 2 MHz, 4 MHz (default value), 8 MHz, 16 MHz, 24 MHz, 32 MHz and 48 MHz. The MSI clock is used as system clock after restart from Reset, wakeup from Standby and Shutdown low-power modes. After restart from Reset, the MSI frequency is set to its default value 4 MHz. Refer to Section 8.3: Low-power modes. The MSI clock can be selected as system clock after a wakeup from Stop mode (Stop 1 or Stop 2). Refer to Section 8.3: Low-power modes. It can also be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 8.2.9: Clock security system (CSS). The MSI RC oscillator has the advantage of providing a low-cost (no external components) low-power clock source. In addition, when used in PLL-mode with the LSE, it provides a very accurate clock source which can be used by the USB OTG FS device, and feed the main PLL to run the system at the maximum speed 80 MHz. The MSIRDY flag in the Clock control register (RCC_CR) indicates wether the MSI RC is stable or not. At startup, the MSI RC output clock is not released until this bit is set by hardware. The MSI RC can be switched on and off by using the MSION bit in the Clock control register (RCC_CR). Hardware auto calibration with LSE (PLL-mode) When a 32.768 kHz external oscillator is present in the application, it is possible to configure the MSI in a PLL-mode by setting the MSIPLLEN bit in the Clock control register (RCC_CR). When configured in PLL-mode, the MSI automatically calibrates itself thanks to the LSE. This mode is available for all MSI frequency ranges. At 48 MHz, the MSI in PLL-mode can be used for the USB OTG FS device, saving the need of an external high-speed crystal. Software calibration The MSI RC oscillator frequency can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1 % accuracy at an ambient temperature, TA, of 25 °C. After reset, the factory calibration value is loaded in the MSICAL[7:0] bits in the Internal clock sources calibration register (RCC_ICSCR). If the application is subject to voltage or temperature variations, this may affect the RC oscillator speed. You can trim the MSI frequency in the application by using the MSITRIM[7:0] bits in the RCC_ICSCR register. For more details on how to measure the MSI frequency variation please refer to Section 8.2.16: Internal/external clock measurement with TIM15/TIM16/TIM17. DocID024597 Rev 1 201/1680 267 Reset and clock control (RCC) 8.2.4 RM0351 PLL The device embeds 3 PLLs: PLL, PLLSAI1, PLLSAI2. Each PLL provides up to three independent outputs. The internal PLLs can be used to multiply the HSI16, HSE or MSI output clock frequency. The PLLs input frequency must be between 4 and 16 MHz. The selected clock source is divided by a programmable factor PLLM from 1 to 8 to provide a clock frequency in the requested input range. Refer to Figure 13: Clock tree and PLL configuration register (RCC_PLLCFGR). The PLLs configuration (selection of the input clock and multiplication factor) must be done before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed. To modify the PLL configuration, proceed as follows: 1. Disable the PLL by setting PLLON to 0 in Clock control register (RCC_CR). 2. Wait until PLLRDY is cleared. The PLL is now fully stopped. 3. Change the desired parameter. 4. Enable the PLL again by setting PLLON to 1. 5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN in PLL configuration register (RCC_PLLCFGR). An interrupt can be generated when the PLL is ready, if enabled in the Clock interrupt enable register (RCC_CIER). The same procedure is applied for changing the configuration of the PLLSAI1 or PLLSAI2: 1. Disable the PLLSAI1/PLLSAI2 by setting PLLSAI1ON/PLLSAI2ON to 0 in Clock control register (RCC_CR). 2. Wait until PLLSAI1RDY/PLLSAI2RDY is cleared. The PLLSAI1/PLLSAI2 is now fully stopped. 3. Change the desired parameter. 4. Enable the PLLSAI1/PLLSAI2 again by setting PLLSAI1ON/PLLSAI2ON to 1. 5. Enable the desired PLL outputs by configuring PLLSAI1PEN/PLLSAI2PEN, PLLSAI1QEN/PLLSAI2QEN, PLLSAI1REN/PLLSAI2REN in PLLSAI1 configuration register (RCC_PLLSAI1CFGR) and PLLSAI2 configuration register (RCC_PLLSAI2CFGR). The PLL output frequency must not exceed 80 MHz. The enable bit of each PLL output clock (PLLPEN, PLLQEN, PLLREN, PLLSAI1PEN, PLLSAI1QEN, PLLSAI1REN, PLLSAI2PEN and PLLSAI2REN) can be modified at any time without stopping the corresponding PLL. PLLREN cannot be cleared if PLLCLK is used as system clock. 8.2.5 LSE clock The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the advantage of providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions. The LSE crystal is switched on and off using the LSEON bit in Backup domain control register (RCC_BDCR). The crystal oscillator driving strength can be changed at runtime using the LSEDRV[1:0] bits in the Backup domain control register (RCC_BDCR) to obtain the best compromise between robustness and short start-up time on one side and lowpower-consumption on the other side. The LSE drive can be decreased to the lower drive 202/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) capability (LSEDRV=00) when the LSE is ON. However, once LSEDRV is selected, the drive capability can not be increased if LSEON=1. The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER). External source (LSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the AHB1 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR). The external clock signal (square, sinus or triangle) with ~50 % duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin can be used as GPIO. See Figure 14. 8.2.6 LSI clock The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby mode for the independent watchdog (IWDG), RTC and LCD. The clock frequency is 32 kHz. For more details, refer to the electrical characteristics section of the datasheets. The LSI RC can be switched on and off using the LSION bit in the Control/status register (RCC_CSR). The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the LSI oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER). 8.2.7 System clock (SYSCLK) selection Four different clock sources can be used to drive the system clock (SYSCLK): • MSI oscillator • HSI16 oscillator • HSE oscillator • PLL The system clock maximum frequency is 80 MHz. After a system reset, the MSI oscillator, at 4 MHz, is selected as system clock. When a clock source is used directly or through the PLL as a system clock, it is not possible to stop it. A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source becomes ready. Status bits in the Internal clock sources calibration register (RCC_ICSCR) indicate which clock(s) is (are) ready and which clock is currently used as a system clock. 8.2.8 Clock source frequency versus voltage scaling The following table gives the different clock source frequencies depending on the product voltage range. DocID024597 Rev 1 203/1680 267 Reset and clock control (RCC) RM0351 Table 30. Clock source frequency Product voltage range 8.2.9 Clock frequency MSI HSI16 HSE PLL/PLLSAI1/PLLSAI2 Range 1 48 MHz 16 MHz 48 MHz 80 MHz (VCO max = 344 MHz) Range 2 24 MHz range 16 MHz 26 MHz 26 MHz (VCO max = 128 MHz) Clock security system (CSS) Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock failure event is sent to the break input of the advanced-control timers (TIM1/TIM8 and TIM15/16/17) and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex®-M4 NMI (Non-Maskable Interrupt) exception vector. Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and a NMI is automatically generated. The NMI will be executed indefinitely unless the CSS interrupt pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt by setting the CSSC bit in the Clock interrupt clear register (RCC_CICR). If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock to the MSI or the HSI16 oscillator depending on the STOPWUCK configuration in the Clock configuration register (RCC_CFGR), and the disabling of the HSE oscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too. 8.2.10 Clock security system on LSE A Clock Security System on LSE can be activated by software writing the LSECSSON bit in the Control/status register (RCC_CSR). This bit can be disabled only by a hardware reset or RTC software reset, or after a failure detection on LSE. LSECSSON must be written after LSE and LSI are enabled (LSEON and LSION enabled) and ready (LSERDY and LSIRDY set by hardware), and after the RTC clock has been selected by RTCSEL. The CSS on LSE is working in all modes except VBAT. It is working also under system reset (excluding power on reset). If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied to the RTC but no hardware action is made to the registers. If the MSI was in PLL-mode, this mode is disabled. In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup the software (see Clock interrupt enable register (RCC_CIER), Clock interrupt flag register (RCC_CIFR), Clock interrupt clear register (RCC_CICR)). The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator (disabling LSEON), and change the RTC clock source (no clock or LSI or HSE, with RTCSEL), or take any required action to secure the application. 204/1680 DocID024597 Rev 1 RM0351 8.2.11 Reset and clock control (RCC) ADC clock The ADC clock is derived from the system clock, or from the PLLSAI1 or the PLLSAI2 output. It can reach 80 MHz and can be divided by the following prescalers values: 1,2,4,6,8,10,12,16,32,64,128 or 256 by configuring the ADC123_CCR register. It is asynchronous to the AHB clock. Alternatively, the ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). This programmable factor is configured using the CKMODE bit fields in the ADC123_CCR. If the programmed factor is ‘1’, the AHB prescaler must be set to ‘1’. 8.2.12 RTC clock The RTCCLK clock source can be either the HSE/32, LSE or LSI clock. It is selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR). This selection cannot be modified without resetting the Backup domain. The system must always be configured so as to get a PCLK frequency greater then or equal to the RTCCLK frequency for a proper operation of the RTC. The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. Consequently: • If LSE is selected as RTC clock: – • If LSI is selected as the RTC clock: – • The RTC state is not guaranteed if the VDD supply is powered off. If the HSE clock divided by a prescaler is used as the RTC clock: – 8.2.13 The RTC continues to work even if the VDD supply is switched off, provided the VBAT supply is maintained. The RTC state is not guaranteed if the VDD supply is powered off or if the internal voltage regulator is powered off (removing power from the VCORE domain). Timer clock The timer clock frequencies are automatically defined by hardware. There are two cases: 8.2.14 1. If the APB prescaler equals 1, the timer clock frequencies are set to the same frequency as that of the APB domain. 2. Otherwise, they are set to twice (×2) the frequency of the APB domain. Watchdog clock If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG. DocID024597 Rev 1 205/1680 267 Reset and clock control (RCC) 8.2.15 RM0351 Clock-out capability • MCO The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. One of seven clock signals can be selected as the MCO clock. – LSI – LSE – SYSCLK – HSI16 – HSE – PLLCLK – MSI The selection is controlled by the MCOSEL[2:0] bits of the Clock configuration register (RCC_CFGR). The selected clock can be divided with the MCOPRE[2:0] field of the Clock configuration register (RCC_CFGR). • LSCO Another output (LSCO) allows a low speed clock to be output onto the external LSCO pin: – LSI – LSE This output remains available in Stop (Stop 1 and Stop 2) and Standby modes. The selection is controlled by the LSCOSEL, and enabled with the LSCOEN in the Backup domain control register (RCC_BDCR). The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. 8.2.16 Internal/external clock measurement with TIM15/TIM16/TIM17 It is possible to indirectly measure the frequency of all on-board clock sources by mean of the TIM15, TIM16 or TIM17 channel 1 input capture, as represented on Figure 15, Figure 16 and Figure 17. Figure 15. Frequency measurement with TIM15 in capture mode 7,0 7,B503 *3,2 7, /6( 069 206/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) The input capture channel of the Timer 15 can be a GPIO line or an internal clock of the MCU. This selection is performed through the TI1_RMP bit in the TIM15_OR register. The possibilities are the following ones: • TIM15 Channel1 is connected to the GPIO. Refer to the alternate function mapping in the device datasheets. • TIM15 Channel1 is connected to the LSE. Figure 16. Frequency measurement with TIM16 in capture mode 7,0 7,B503>@ *3,2 7, /6, /6( 57&ZDNHXSLQWHUUXSW 069 The input capture channel of the Timer 16 can be a GPIO line or an internal clock of the MCU. This selection is performed through the TI1_RMP[1:0] bits in the TIM16_OR register. The possibilities are the following ones: • TIM16 Channel1 is connected to the GPIO. Refer to the alternate function mapping in the device datasheets. • TIM16 Channel1 is connected to the LSI clock. • TIM16 Channel1 is connected to the LSE clock. • TIM16 Channel1 is connected to the RTC wakeup interrupt signal. In this case the RTC interrupt should be enabled. Figure 17. Frequency measurement with TIM17 in capture mode 7,0 7,B503>@ *3,2 06, +6( 0&2 7, 069 DocID024597 Rev 1 207/1680 267 Reset and clock control (RCC) RM0351 The input capture channel of the Timer 17 can be a GPIO line or an internal clock of the MCU. This selection is performed through the TI1_RMP[1:0] bits in the TIM17_OR register. The possibilities are the following ones: • TIM17 Channel1 is connected to the GPIO. Refer to the alternate function mapping in the device datasheets. • TIM17 Channel1 is connected to the MSI Clock. • TIM17 Channel1 is connected to the HSE/32 Clock. • TIM17 Channel1 is connected to the microcontroller clock output (MCO), this selection is controlled by the MCO[2:0] bits of the Clock configuration register (RCC_CFGR). Calibration of the HSI16 and the MSI For TIM15 and TIM16, the primary purpose of connecting the LSE to the channel 1 input capture is to be able to precisely measure the HSI16 and MSI system clocks (for this, either the HSI16 or MSI should be used as the system clock source). The number of HSI16 (MSI, respectively) clock counts between consecutive edges of the LSE signal provides a measure of the internal clock period. Taking advantage of the high precision of LSE crystals (typically a few tens of ppm’s), it is possible to determine the internal clock frequency with the same resolution, and trim the source to compensate for manufacturing-process- and/or temperature- and voltage-related frequency deviations. The MSI and HSI16 oscillator both have dedicated user-accessible calibration bits for this purpose. The basic concept consists in providing a relative measurement (e.g. the HSI16/LSE ratio): the precision is therefore closely related to the ratio between the two clock sources. The higher the ratio is, the better the measurement will be. If LSE is not available, HSE/32 will be the better option in order to reach the most precise calibration possible. It is however not possible to have a good enough resolution when the MSI clock is low (typically below 1 MHz). In this case, it is advised to: • accumulate the results of several captures in a row • use the timer’s input capture prescaler (up to 1 capture every 8 periods) • use the RTC wakeup interrupt signal (when the RTC is clocked by the LSE) as the input for the channel1 input capture. This improves the measurement precision. For this purpose the RTC wakeup interrupt must be enable. Calibration of the LSI The calibration of the LSI will follow the same pattern that for the HSI16, but changing the reference clock. It will be necessary to connect LSI clock to the channel 1 input capture of the TIM16. Then define the HSE as system clock source, the number of his clock counts between consecutive edges of the LSI signal provides a measure of the internal low speed clock period. The basic concept consists in providing a relative measurement (e.g. the HSE/LSI ratio): the precision is therefore closely related to the ratio between the two clock sources. The higher the ratio is, the better the measurement will be. 208/1680 DocID024597 Rev 1 RM0351 8.2.17 Reset and clock control (RCC) Peripheral clock enable register (RCC_AHBxENR, RCC_APBxENRy) Each peripheral clock can be enabled by the xxxxEN bit of the RCC_AHBxENR, RCC_APBxENRy registers. When the peripheral clock is not active, the peripheral registers read or write accesses are not supported. The enable bit has a synchronization mechanism to create a glitch free clock for the peripheral. After the enable bit is set, there is a 2 clock cycles delay before the clock be active. Caution: Just after enabling the clock for a peripheral, software must wait for a delay before accessing the peripheral registers. 8.3 Low-power modes • AHB and APB peripheral clocks, including DMA clock, can be disabled by software. • Sleep and Low Power Sleep modes stops the CPU clock. The memory interface clocks (Flash and SRAM1 and SRAM2 interfaces) can be stopped by software during sleep mode. The AHB to APB bridge clocks are disabled by hardware during Sleep mode when all the clocks of the peripherals connected to them are disabled. • Stop modes (Stop 1 and Stop 2) stops all the clocks in the VCORE domain and disables the three PLL, the HSI16, the MSI and the HSE oscillators. All U(S)ARTs, LPUARTs and I2Cs have the capability to enable the HSI16 oscillator even when the MCU is in Stop mode (if HSI16 is selected as the clock source for that peripheral). All U(S)ARTs and LPUARTs can also be driven by the LSE oscillator when the system is in Stop mode (if LSE is selected as clock source for that peripheral) and the LSE oscillator is enabled (LSEON). In that case the LSE remains always ON in Stop mode (they do not have the capability to turn on the LSE oscillator). • Standby and Shutdown modes stops all the clocks in the VCORE domain and disables the PLL, the HSI16, the MSI and the HSE oscillators. The CPU’s deepsleep mode can be overridden for debugging by setting the DBG_STOP or DBG_STANDBY bits in the DBGMCU_CR register. When leaving the Stop modes (Stop 1 or Stop 2), the system clock is either MSI or HSI16, depending on the software configuration of the STOPWUCK bit in the RCC_CFGR register. The frequency (range and user trim) of the MSI oscillator is the one configured before entering Stop mode. The user trim of HSI16 is kept. If the MSI was in PLL-mode before entering Stop mode, the PLL-mode stabilization time must be waited for after wakeup even if the LSE was kept ON during the Stop mode. When leaving the Standby and Shutdown modes, the system clock is MSI. The MSI frequency at wakeup from Standby mode is configured with the MSISRANGE is the RCC_CSR register, from 1 to 8 MHz. The MSI frequency at wakeup from Shutdown mode is 4 MHz. The user trim is lost. If a Flash memory programming operation is on going, Stop, Standby and Shutdown modes entry is delayed until the Flash memory interface access is finished. If an access to the APB domain is ongoing, Stop, Standby and Shutdown modes entry is delayed until the APB access is finished. DocID024597 Rev 1 209/1680 267 Reset and clock control (RCC) RM0351 8.4 RCC registers 8.4.1 Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 0063. HSEBYP is not affected by reset. Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. PLL SAI2 RDY PLL SAI2 ON PLL SAI1 RDY PLL SAI1 ON PLL RDY PLLON Res. Res. Res. Res. CSS ON HSE BYP HSE RDY HSE ON r rw r rw r rw rs rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. HSI ASFS HSI RDY MSI RDY MSION rw r r rw Res. Res. Res. HSI HSION KERON rw rw MSI MSI RGSEL PLLEN MSIRANGE[3:0] rw rw rw rw rs rw Bits 31:30 Reserved, must be kept at reset value. Bit 29 PLLSAI2RDY: SAI2 PLL clock ready flag Set by hardware to indicate that the PLLSAI2 is locked. 0: PLLSAI2 unlocked 1: PLLSAI2 locked Bit 28 PLLSAI2ON: SAI2 PLL enable Set and cleared by software to enable PLLSAI2. Cleared by hardware when entering Stop, Standby or Shutdown mode. 0: PLLSAI2 OFF 1: PLLSAI2 ON Bit 27 PLLSAI1RDY: SAI1 PLL clock ready flag Set by hardware to indicate that the PLLSAI1 is locked. 0: PLLSAI1 unlocked 1: PLLSAI1 locked Bit 26 PLLSAI1ON: SAI1 PLL enable Set and cleared by software to enable PLLSAI1. Cleared by hardware when entering Stop, Standby or Shutdown mode. 0: PLLSAI1 OFF 1: PLLSAI1 ON Bit 25 PLLRDY: Main PLL clock ready flag Set by hardware to indicate that the main PLL is locked. 0: PLL unlocked 1: PLL locked Bit 24 PLLON: Main PLL enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock. 0: PLL OFF 1: PLL ON 210/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) Bits 23:20 Reserved, must be kept at reset value. Bit 19 CSSON: Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. 0: Clock security system OFF (clock detector OFF) 1: Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not). Bit 18 HSEBYP: HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. 0: HSE crystal oscillator not bypassed 1: HSE crystal oscillator bypassed with external clock Bit 17 HSERDY: HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. 0: HSE oscillator not ready 1: HSE oscillator ready Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles. Bit 16 HSEON: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 0: HSE oscillator OFF 1: HSE oscillator ON Bits 15:12 Reserved, must be kept at reset value. Bit 11 HSIASFS: HSI16 automatic start from Stop Set and cleared by software. When the system wakeup clock is MSI, this bit is used to wakeup the HSI16 is parallel of the system wakeup. 0: HSI16 oscillator is not enabled by hardware when exiting Stop mode with MSI as wakeup clock. 1: HSI16 oscillator is enabled by hardware when exiting Stop mode with MSI as wakeup clock. Bit 10 HSIRDY: HSI16 clock ready flag Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION. 0: HSI16 oscillator not ready 1: HSI16 oscillator ready Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles. Bit 9 HSIKERON: HSI16 always enable for peripheral kernels. Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only feed USARTs and I2Cs peripherals configured with HSI16 as kernel clock. Keeping the HSI16 ON in Stop mode allows to avoid slowing down the communication speed because of the HSI16 startup time. This bit has no effect on HSION value. 0: No effect on HSI16 oscillator. 1: HSI16 oscillator is forced ON even in Stop mode. DocID024597 Rev 1 211/1680 267 Reset and clock control (RCC) RM0351 Bit 8 HSION: HSI clock enable Set and cleared by software. Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the HSI16 oscillator ON when STOPWUCK=1 or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI16 is used directly or indirectly as system clock. 0: HSI16 oscillator OFF 1: HSI16 oscillator ON Bits 7:4 MSIRANGE[3:0]: MSI clock ranges These bits are configured by software to choose the frequency range of MSI when MSIRGSEL is set.12 frequency ranges are available: 0000: range 0 around 100 kHz 0001: range 1 around 200 kHz 0010: range 2 around 400 kHz 0011: range 3 around 800 kHz 0100: range 4 around 1M Hz 0101: range 5 around 2 MHz 0110: range 6 around 4 MHz (reset value) 0111: range 7 around 8 MHz 1000: range 8 around 16 MHz 1001: range 9 around 24 MHz 1010: range 10 around 32 MHz 1011: range 11 around 48 MHz others: not allowed (hardware write protection) Note: Warning: MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready (MSIRDY=1). MSIRANGE must NOT be modified when MSI is ON and NOT ready (MSION=1 and MSIRDY=0) Bit 3 MSIRGSEL: MSI clock range selection Set by software to select the MSI clock range with MSIRANGE[3:0]. Write 0 has no effect. After a standby or a reset MSIRGSEL is at 0 and the MSI range value is provided by MSISRANGE in CSR register. 0: MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register 1: MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register Bit 2 MSIPLLEN: MSI clock PLL enable Set and cleared by software to enable/ disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware).There is a hardware protection to avoid enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the Clock Security System on LSE detects a LSE failure (refer to RCC_CSR register). 0: MSI PLL OFF 1: MSI PLL ON Bit 1 MSIRDY: MSI clock ready flag This bit is set by hardware to indicate that the MSI oscillator is stable. 0: MSI oscillator not ready 1: MSI oscillator ready Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles. 212/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) Bit 0 MSION: MSI clock enable This bit is set and cleared by software. Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop modes, or in case of a failure of the HSE oscillator Set by hardware when used directly or indirectly as system clock. 0: MSI oscillator OFF 1: MSI oscillator ON 8.4.2 Internal clock sources calibration register (RCC_ICSCR) Address offset: 0x04 Reset value: 0x10XX 00XX where X is factory-programmed. Access: no wait state, word, half-word and byte access 31 30 29 Res. Res. Res. 15 14 13 rw rw rw 28 27 26 25 24 23 22 21 HSITRIM[4:0] 20 19 18 17 16 HSICAL[7:0] rw rw rw rw rw r r r r r r r r 12 11 10 9 8 7 6 5 4 3 2 1 0 rwr rw rw r r r r r r MSITRIM[7:0] rw rw MSICAL[7:0] r r Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 HSITRIM[4:0]: HSI16 clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI16. The default value is 16, which, when added to the HSICAL value, should trim the HSI16 to 16 MHz ± 1 %. Bits 23:16 HSICAL[7:0]: HSI16 clock calibration These bits are initialized at startup with the factory-programmed HSI16 calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. Bits 15:8 MSITRIM[7:0]: MSI clock trimming These bits provide an additional user-programmable trimming value that is added to the MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the MSI. Bits 7:0 MSICAL[7:0]: MSI clock calibration These bits are initialized at startup with the factory-programmed MSI calibration trim value. When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value. DocID024597 Rev 1 213/1680 267 Reset and clock control (RCC) 8.4.3 RM0351 Clock configuration register (RCC_CFGR) Address offset: 0x08 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during clock source switch. From 0 to 15 wait states inserted if the access occurs when the APB or AHB prescalers values update is on going. 31 30 Res. 29 28 MCOPRE[2:0] rw rw rw 15 14 13 12 STOP WUCK Res. rw 27 26 Res. 11 rw 24 rw rw rw 10 9 8 PPRE2[2:0] rw 25 MCOSEL[2:0] 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 PPRE1[2:0] rw rw rw HPRE[3:0] rw rw rw rw SWS[1:0] rw r r SW[1:0] rw Bit 31 Reserved, must be kept at reset value. Bits 30:28 MCOPRE[2:0]: Microcontroller clock output prescaler These bits are set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. 000: MCO is divided by 1 001: MCO is divided by 2 010: MCO is divided by 4 011: MCO is divided by 8 100: MCO is divided by 16 Others: not allowed Bit 27 Reserved, must be kept at reset value. Bits 26:24 MCOSEL[2:0]: Microcontroller clock output Set and cleared by software. 000: MCO output disabled, no clock on MCO 001: SYSCLK system clock selected 010: MSI clock selected. 011: HSI16 clock selected. 100: HSE clock selected 101: Main PLL clock selected 110: LSI clock selected 111: LSE clock selected Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Bits 23:16 Reserved, must be kept at reset value. 214/1680 DocID024597 Rev 1 rw RM0351 Reset and clock control (RCC) Bit 15 STOPWUCK: Wakeup from Stop and CSS backup clock selection Set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the Clock Security System on HSE. Warning: STOPWUCK must not be modified when the Clock Security System is enabled by HSECSSON in RCC_CR register and the system clock is HSE (SWS=”10”) or a switch on HSE is requested (SW=”10”). 0: MSI oscillator selected as wakeup from stop clock and CSS backup clock. 1: HSI16 oscillator selected as wakeup from stop clock and CSS backup clock Bit 14 Reserved, must be kept at reset value. Bits 13:11 PPRE2[2:0]: APB high-speed prescaler (APB2) Set and cleared by software to control the division factor of the APB2 clock (PCLK2). 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 Bits 10:8 PPRE1[2:0]:APB low-speed prescaler (APB1) Set and cleared by software to control the division factor of the APB1 clock (PCLK1). 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 Bits 7:4 HPRE[3:0]: AHB prescaler Set and cleared by software to control the division factor of the AHB clock. Caution: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details please refer to Section 6.1.7: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account. 0xxx: SYSCLK not divided 1000: SYSCLK divided by 2 1001: SYSCLK divided by 4 1010: SYSCLK divided by 8 1011: SYSCLK divided by 16 1100: SYSCLK divided by 64 1101: SYSCLK divided by 128 1110: SYSCLK divided by 256 1111: SYSCLK divided by 512 Bits 3:2 SWS[1:0]: System clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. 00: MSI oscillator used as system clock 01: HSI16 oscillator used as system clock 10: HSE used as system clock 11: PLL used as system clock DocID024597 Rev 1 215/1680 267 Reset and clock control (RCC) RM0351 Bits 1:0 SW[1:0]: System clock switch Set and cleared by software to select system clock source (SYSCLK). Configured by HW to force MSI oscillator selection when exiting Standby or Shutdown mode. Configured by HW to force MSI or HSI16 oscillator selection when exiting Stop mode or in case of failure of the HSE oscillator, depending on STOPWUCK value. 00: MSI selected as system clock 01: HSI16 selected as system clock 10: HSE selected as system clock 11: PLL selected as system clock 216/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) 8.4.4 PLL configuration register (RCC_PLLCFGR) Address offset: 0x0C Reset value: 0x0000 1000 Access: no wait state, word, half-word and byte access This register is used to configure the PLL clock outputs according to the formulas: • f(VCO clock) = f(PLL clock input) × (PLLN / PLLM) • f(PLL_P) = f(VCO clock) / PLLP • f(PLL_Q) = f(VCO clock) / PLLQ • f(PLL_R) = f(VCO clock) / PLLR 31 Res. 15 30 Res. 14 29 Res. 13 28 Res. 12 Res. 27 Res. 11 26 25 PLLR[1:0] 24 PLL REN rw rw rw 10 9 8 PLLN[7:0] rw rw rw rw 23 22 Res. PLLQ[1:0] rw 7 6 Res. rw rw rw 21 20 PLL QEN rw rw 5 4 PLLM[2:0] rw rw rw 19 Res. 18 Res. 3 2 Res. Res. 17 16 PLLP PLL PEN rw rw 1 0 PLLSRC[1:0] rw rw Bits 31:27 Reserved, must be kept at reset value. Bits 26:25 PLLR[1:0]: Main PLL division factor for PLLCLK (system clock) Set and cleared by software to control the frequency of the main PLL output clock PLLCLK. This output can be selected as system clock. These bits can be written only if PLL is disabled. PLLCLK output clock frequency = VCO frequency / PLLR with PLLR = 2, 4, 6, or 8 00: PLLR = 2 01: PLLR = 4 10: PLLR = 6 11: PLLR = 8 Caution: The software has to set these bits correctly not to exceed 80 MHz on this domain. Bit 24 PLLREN: Main PLL PLLCLK output enable Set and reset by software to enable the PLLCLK output of the main PLL (used as system clock). This bit cannot be written when PLLCLK output of the PLL is used as System Clock. In order to save power, when the PLLCLK output of the PLL is not used, the value of PLLREN should be 0. 0: PLLCLK output disable 1: PLLCLK output enable Bit 23 Reserved, must be kept at reset value. DocID024597 Rev 1 217/1680 267 Reset and clock control (RCC) RM0351 Bits 22:21 PLLQ[1:0]: Main PLL division factor for PLL48M1CLK (48 MHz clock). Set and cleared by software to control the frequency of the main PLL output clock PLL48M1CLK. This output can be selected for USB, RNG, SDMMC (48 MHz clock). These bits can be written only if PLL is disabled. PLL48M1CLK output clock frequency = VCO frequency / PLLQ with PLLQ = 2, 4, 6, or 8 00: PLLQ = 2 01: PLLQ = 4 10: PLLQ = 6 11: PLLQ = 8 Caution: The software has to set these bits correctly not to exceed 80 MHz on this domain. Bit 20 PLLQEN: Main PLL PLL48M1CLK output enable Set and reset by software to enable the PLL48M1CLK output of the main PLL. In order to save power, when the PLL48M1CLK output of the PLL is not used, the value of PLLQEN should be 0. 0: PLL48M1CLK output disable 1: PLL48M1CLK output enable Bits 19:18 Reserved, must be kept at reset value. Bit 17 PLLP: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock). Set and cleared by software to control the frequency of the main PLL output clock PLLSAI3CLK. This output can be selected for SAI1 or SAI2. These bits can be written only if PLL is disabled. PLLSAI3CLK output clock frequency = VCO frequency / PLLP with PLLP =7, or 17 0: PLLP = 7 1: PLLP = 17 Caution: The software has to set these bits correctly not to exceed 80 MHz on this domain. Bit 16 PLLPEN: Main PLL PLLSAI3CLK output enable Set and reset by software to enable the PLLSAI3CLK output of the main PLL. In order to save power, when the PLLSAI3CLK output of the PLL is not used, the value of PLLPEN should be 0. 0: PLLSAI3CLK output disable 1: PLLSAI3CLK output enable Bit 15 Reserved, must be kept at reset value. 218/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) Bits 14:8 PLLN[6:0]: Main PLL multiplication factor for VCO Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled. VCO output frequency = VCO input frequency x PLLN with 8 =< PLLN =< 86 0000000: PLLN = 0 wrong configuration 0000001: PLLN = 1 wrong configuration ... 0000111: PLLN = 7 wrong configuration 0001000: PLLN = 8 0001001: PLLN = 9 ... 1010101: PLLN = 85 1010110: PLLN = 86 1010111: PLLN = 87 wrong configuration ... 1111111: PLLN = 127 wrong configuration Caution: The software has to set correctly these bits to assure that the VCO output frequency is between 64 and 344 MHz. Bit 7 Reserved, must be kept at reset value. Bits 6:4 PLLM: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock Set and cleared by software to divide the PLL, PLLSAI1 and PLLSAI2 input clock before the VCO. These bits can be written only when all PLLs are disabled. VCO input frequency = PLL input clock frequency / PLLM with 1 <= PLLM <= 8 000: PLLM = 1 001: PLLM = 2 010: PLLM = 3 011: PLLM = 4 100: PLLM = 5 101: PLLM = 6 110: PLLM = 7 111: PLLM = 8 Caution: The software has to set these bits correctly to ensure that the VCO input frequency ranges from 4 to 16 MHz. Bits 3:2 Reserved, must be kept at reset value. Bits 1:0 PLLSRC: Main PLL, PLLSAI1 and PLLSAI2 entry clock source Set and cleared by software to select PLL, PLLSAI1 and PLLSAI2 clock source. These bits can be written only when PLL, PLLSAI1 and PLLSAI2 are disabled. In order to save power, when no PLL is used, the value of PLLSRC should be 00. 00: No clock sent to PLL, PLLSAI1 and PLLSAI2 01: MSI clock selected as PLL, PLLSAI1 and PLLSAI2 clock entry 10: HSI16 clock selected as PLL, PLLSAI1 and PLLSAI2 clock entry 11: HSE clock selected as PLL, PLLSAI1 and PLLSAI2 clock entry DocID024597 Rev 1 219/1680 267 Reset and clock control (RCC) 8.4.5 RM0351 PLLSAI1 configuration register (RCC_PLLSAI1CFGR) Address offset: 0x10 Reset value: 0x0000 1000 Access: no wait state, word, half-word and byte access This register is used to configure the PLLSAI1 clock outputs according to the formulas: • f(VCOSAI1 clock) = f(PLL clock input) × (PLLSAI1N / PLLM) • f(PLLSAI1_P) = f(VCOSAI1 clock) / PLLSAI1P • f(PLLSAI1_Q) = f(VCOSAI1 clock) / PLLSAI1Q • f(PLLSAI1_R) = f(VCOSAI1 clock) / PLLSAI1R 31 30 29 28 27 Res. Res. Res. Res. Res. 15 14 13 12 11 Res. 26 25 24 PLLSAI1R[1:0] PLL SAI1 REN rw rw rw 10 9 8 PLLSAI1N[6:0] rw rw rw rw rw rw 23 Res. 22 21 PLLSAI1Q[1:0] 20 PLL SAI1 QEN 19 18 Res. Res. 17 16 PLL SAI1P PLL SAI1 PEN rw rw rw rw rw 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:27 Reserved, must be kept at reset value. Bits 26:25 PLLSAI1R[1:0]: PLLSAI1 division factor for PLLADC1CLK (ADC clock) Set and cleared by software to control the frequency of the SAI1PLL output clock PLLADC1CLK. This output can be selected as ADC clock. These bits can be written only if SAI1PLL is disabled. PLLADC1CLK output clock frequency = VCOSAI1 frequency / PLLSAI1R with PLLSAI1R = 2, 4, 6, or 8 00: PLLSAI1R = 2 01: PLLSAI1R = 4 10: PLLSAI1R = 6 11: PLLSAI1R = 8 Bit 24 PLLSAI1REN: PLLSAI1 PLLADC1CLK output enable Set and reset by software to enable the PLLADC1CLK output of the SAI1PLL (used as clock for ADC). In order to save power, when the PLLADC1CLK output of the SAI1PLL is not used, the value of PLLSAI1REN should be 0. 0: PLLADC1CLK output disable 1: PLLADC1CLK output enable Bit 23 Reserved, must be kept at reset value. 220/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) Bits 22:21 PLLSAI1Q[1:0]: SAI1PLL division factor for PLL48M2CLK (48 MHz clock) Set and cleared by software to control the frequency of the SAI1PLL output clock PLL48M2CLK. This output can be selected for USB, RNG, SDMMC (48 MHz clock). These bits can be written only if SAI1PLL is disabled. PLL48M2CLK output clock frequency = VCOSAI1 frequency / PLLQ with PLLQ = 2, 4, 6, or 8 00: PLLQ = 2 01: PLLQ = 4 10: PLLQ = 6 11: PLLQ = 8 Caution: The software has to set these bits correctly not to exceed 80 MHz on this domain. Bit 20 PLLSAI1QEN: SAI1PLL PLL48M2CLK output enable Set and reset by software to enable the PLL48M2CLK output of the SAI1PLL. In order to save power, when the PLL48M2CLK output of the SAI1PLL is not used, the value of PLLSAI1QEN should be 0. 0: PLL48M2CLK output disable 1: PLL48M2CLK output enable Bits 19:18 Reserved, must be kept at reset value. Bit 17 PLLSAI1P: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock). Set and cleared by software to control the frequency of the SAI1PLL output clock PLLSAI1CLK. This output can be selected for SAI1 or SAI2. These bits can be written only if SAI1PLL is disabled. PLLSAI1CLK output clock frequency = VCOSAI1 frequency / PLLSAI1P with PLLSAI1P =7, or 17 0: PLLSAI1P = 7 1: PLLSAI1P = 17 Bit 16 PLLSAI1PEN: SAI1PLL PLLSAI1CLK output enable Set and reset by software to enable the PLLSAI1CLK output of the SAI1PLL. In order to save power, when the PLLSAI1CLK output of the SAI1PLL is not used, the value of PLLSAI1PEN should be 0. 0: PLLSAI1CLK output disable 1: PLLSAI1CLK output enable DocID024597 Rev 1 221/1680 267 Reset and clock control (RCC) RM0351 Bit 15 Reserved, must be kept at reset value. Bits 14:8 PLLSAI1N[6:0]: SAI1PLL multiplication factor for VCO Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the SAI1PLL is disabled. VCOSAI1 output frequency = VCOSAI1 input frequency x PLLSAI1N with 8 =< PLLSAI1N =< 86 0000000: PLLSAI1N = 0 wrong configuration 0000001: PLLSAI1N = 1 wrong configuration ... 0000111: PLLSAI1N = 7 wrong configuration 0001000: PLLSAI1N = 8 0001001: PLLSAI1N = 9 ... 1010101: PLLSAI1N = 85 1010110: PLLSAI1N = 86 1010111: PLLSAI1N = 87 wrong configuration ... 1111111: PLLSAI1N = 127 wrong configuration Caution: The software has to set correctly these bits to ensure that the VCO output frequency is between 64 and 344 MHz. Bits 7:0 Reserved, must be kept at reset value. 222/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) 8.4.6 PLLSAI2 configuration register (RCC_PLLSAI2CFGR) Address offset: 0x14 Reset value: 0x0000 1000 Access: no wait state, word, half-word and byte access This register is used to configure the PLLSAI2 clock outputs according to the formulas: • f(VCOSAI2 clock) = f(PLL clock input) × (PLLSAI2N / PLLM) • f(PLLSAI2_P) = f(VCOSAI2 clock) / PLLSAI2P • f(PLLSAI2_R) = f(VCOSAI2 clock) / PLLSAI2R 31 30 29 28 27 Res. Res. Res. Res. Res. 15 14 13 12 11 Res. 26 25 24 PLLSAI2R[1:0] PLL SAI2 REN rw rw rw 10 9 8 PLLSAI2N[6:0] rw rw rw rw rw rw 23 22 21 20 19 18 17 16 PLL SAI2P PLL SAI2 PEN rw rw Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:27 Reserved, must be kept at reset value. Bits 26:25 PLLSAI2R[1:0]: PLLSAI2 division factor for PLLADC2CLK (ADC clock) Set and cleared by software to control the frequency of the SAI2PLL output clock PLLADC2CLK. This output can be selected as ADC clock. These bits can be written only if SAI2PLL is disabled. PLLADC2CLK output clock frequency = VCOSAI2 frequency / PLLSAI2R with PLLSAI2R = 2, 4, 6, or 8 00: PLLSAI2R = 2 01: PLLSAI2R = 4 10: PLLSAI2R = 6 11: PLLSAI2R = 8 Bit 24 PLLSAI2REN: PLLSAI2 PLLADC2CLK output enable Set and reset by software to enable the PLLADC2CLK output of the SAI2PLL (used as clock for ADC). In order to save power, when the PLLADC2CLK output of the SAI2PLL is not used, the value of PLLSAI2REN should be 0. 0: PLLADC2CLK output disable 1: PLLADC2CLK output enable Bits 23:18 Reserved, must be kept at reset value. Bit 17 PLLSAI2P: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock). Set and cleared by software to control the frequency of the SAI2PLL output clock PLLSAI2CLK. This output can be selected for SAI1 or SAI2. These bits can be written only if SAI2PLL is disabled. PLLSAI2CLK output clock frequency = VCOSAI2 frequency / PLLSAI2P with PLLSAI2P =7, or 17 0: PLLSAI2P = 7 1: PLLSAI2P = 17 DocID024597 Rev 1 223/1680 267 Reset and clock control (RCC) RM0351 Bit 16 PLLSAI2PEN: SAI2PLL PLLSAI2CLK output enable Set and reset by software to enable the PLLSAI2CLK output of the SAI2PLL. In order to save power, when the PLLSAI2CLK output of the SAI2PLL is not used, the value of PLLSAI2PEN should be 0. 0: PLLSAI2CLK output disable 1: PLLSAI2CLK output enable Bit 15 Reserved, must be kept at reset value. Bits 14:8 PLLSAI2N[6:0]: SAI2PLL multiplication factor for VCO Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the SAI2PLL is disabled. VCOSAI2 output frequency = VCOSAI2 input frequency x PLLSAI2N with 8 =< PLLSAI2N =< 86 0000000: PLLSAI2N = 0 wrong configuration 0000001: PLLSAI2N = 1 wrong configuration ... 0000111: PLLSAI2N = 7 wrong configuration 0001000: PLLSAI2N = 8 0001001: PLLSAI2N = 9 ... 1010101: PLLSAI2N = 85 1010110: PLLSAI2N = 86 1010111: PLLSAI2N = 87 wrong configuration ... 1111111: PLLSAI2N = 127 wrong configuration Caution: The software has to set correctly these bits to ensure that the VCO output frequency is between 64 and 344 MHz. Bits 7:0 Reserved, must be kept at reset value. 224/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) 8.4.7 Clock interrupt enable register (RCC_CIER) Address offset: 0x18 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. LSE CSSIE Res. PLL SAI2 RDYIE PLL SAI1 RDYIE PLL RDYIE HSE RDYIE HSI RDYIE MSI RDYIE LSE RDYIE LSI RDYIE rw rw rw rw rw rw rw rw rw Bits 31:10 Reserved, must be kept at reset value. Bit 9 LSECSSIE: LSE clock security system interrupt enable Set and cleared by software to enable/disable interrupt caused by the clock security system on LSE. 0: Clock security interrupt caused by LSE clock failure disabled 1: Clock security interrupt caused by LSE clock failure enabled Bit 8 Reserved, must be kept at reset value. Bit 7 PLLSAI2RDYIE: PLLSAI2 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLLSAI2 lock. 0: PLLSAI2 lock interrupt disabled 1: PLLSAI2 lock interrupt enabled Bit 6 PLLSAI1RDYIE: PLLSAI1 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLSAI1L lock. 0: PLLSAI1 lock interrupt disabled 1: PLLSAI1 lock interrupt enabled Bit 5 PLLRDYIE: PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock. 0: PLL lock interrupt disabled 1: PLL lock interrupt enabled Bit 4 HSERDYIE: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization. 0: HSE ready interrupt disabled 1: HSE ready interrupt enabled Bit 3 HSIRDYIE: HSI16 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization. 0: HSI16 ready interrupt disabled 1: HSI16 ready interrupt enabled DocID024597 Rev 1 225/1680 267 Reset and clock control (RCC) RM0351 Bit 2 MSIRDYIE: MSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSI oscillator stabilization. 0: MSI ready interrupt disabled 1: MSI ready interrupt enabled Bit 1 LSERDYIE: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. 0: LSE ready interrupt disabled 1: LSE ready interrupt enabled Bit 0 LSIRDYIE: LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization. 0: LSI ready interrupt disabled 1: LSI ready interrupt enabled 226/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) 8.4.8 Clock interrupt flag register (RCC_CIFR) Address offset: 0x1C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. LSE CSSF CSSF PLL RDYF HSE RDYF HSI RDYF MSI RDYF LSE RDYF LSI RDYF r r r r r r r r PLLSAI PLLSAI 2RDYF 1RDYF r r Bits 31:10 Reserved, must be kept at reset value. Bit 9 LSECSSF: LSE Clock security system interrupt flag Set by hardware when a failure is detected in the LSE oscillator. Cleared by software setting the LSECSSC bit. 0: No clock security interrupt caused by LSE clock failure 1: Clock security interrupt caused by LSE clock failure Bit 8 CSSF: Clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit. 0: No clock security interrupt caused by HSE clock failure 1: Clock security interrupt caused by HSE clock failure Bit 7 PLLSAI2RDYF: PLLSAI2 ready interrupt flag Set by hardware when the PLLSAI2 locks and PLLSAI2RDYDIE is set. Cleared by software setting the PLLSAI2RDYC bit. 0: No clock ready interrupt caused by PLLSAI2 lock 1: Clock ready interrupt caused by PLLSAI2 lock Bit 6 PLLSAI1RDYF: PLLSAI1 ready interrupt flag Set by hardware when the PLLSAI1 locks and PLLSAI1RDYDIE is set. Cleared by software setting the PLLSAI1RDYC bit. 0: No clock ready interrupt caused by PLLSAI1 lock 1: Clock ready interrupt caused by PLLSAI1 lock Bit 5 PLLRDYF: PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYDIE is set. Cleared by software setting the PLLRDYC bit. 0: No clock ready interrupt caused by PLL lock 1: Clock ready interrupt caused by PLL lock Bit 4 HSERDYF: HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYDIE is set. Cleared by software setting the HSERDYC bit. 0: No clock ready interrupt caused by the HSE oscillator 1: Clock ready interrupt caused by the HSE oscillator DocID024597 Rev 1 227/1680 267 Reset and clock control (RCC) RM0351 Bit 3 HSIRDYF: HSI16 ready interrupt flag Set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit. 0: No clock ready interrupt caused by the HSI16 oscillator 1: Clock ready interrupt caused by the HSI16 oscillator Bit 2 MSIRDYF: MSI ready interrupt flag Set by hardware when the MSI clock becomes stable and MSIRDYDIE is set. Cleared by software setting the MSIRDYC bit. 0: No clock ready interrupt caused by the MSI oscillator 1: Clock ready interrupt caused by the MSI oscillator Bit 1 LSERDYF: LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit. 0: No clock ready interrupt caused by the LSE oscillator 1: Clock ready interrupt caused by the LSE oscillator Bit 0 LSIRDYF: LSI ready interrupt flag Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit. 0: No clock ready interrupt caused by the LSI oscillator 1: Clock ready interrupt caused by the LSI oscillator 228/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) 8.4.9 Clock interrupt clear register (RCC_CICR) Address offset: 0x20 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. LSE CSSC CSSC PLLSAI 2RDYC PLL SAI1 RDYC PLL RDYC HSE RDYC HSI RDYC MSI RDYC LSE RDYC LSI RDYC w w w w w w w w w w Bits 31:10 Reserved, must be kept at reset value. Bit 9 LSECSSC: LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag. 0: No effect 1: Clear LSECSSF flag Bit 8 CSSC: Clock security system interrupt clear This bit is set by software to clear the CSSF flag. 0: No effect 1: Clear CSSF flag Bit 7 PLLSAI2RDYC: PLLSAI2 ready interrupt clear This bit is set by software to clear the PLLSAI2RDYF flag. 0: No effect 1: Clear PLLSAI2RDYF flag Bit 6 PLLSAI1RDYC: PLLSAI1 ready interrupt clear This bit is set by software to clear the PLLSAI1RDYF flag. 0: No effect 1: Clear PLLSAI1RDYF flag Bit 5 PLLRDYC: PLL ready interrupt clear This bit is set by software to clear the PLLRDYF flag. 0: No effect 1: Clear PLLRDYF flag Bit 4 HSERDYC: HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. 0: No effect 1: Clear HSERDYF flag Bit 3 HSIRDYC: HSI16 ready interrupt clear This bit is set software to clear the HSIRDYF flag. 0: No effect 1: Clear HSIRDYF flag DocID024597 Rev 1 229/1680 267 Reset and clock control (RCC) RM0351 Bit 2 MSIRDYC: MSI ready interrupt clear This bit is set by software to clear the MSIRDYF flag. 0: No effect 1: MSIRDYF cleared Bit 1 LSERDYC: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. 0: No effect 1: LSERDYF cleared Bit 0 LSIRDYC: LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. 0: No effect 1: LSIRDYF cleared 8.4.10 AHB1 peripheral reset register (RCC_AHB1RSTR) Address offset: 0x28 Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TSC RST Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. CRC RST Res. FLASH RST Res. DMA2 RST DMA1 RST rw rw rw Res. Res. Res. Res. rw Res. Res. rw Res. Res. Res. Bits 31:17 Reserved, must be kept at reset value. Bit 16 TSCRST: Touch Sensing Controller reset Set and cleared by software. 0: No effect 1: Reset TSC Bits 15:13 Reserved, must be kept at reset value. Bit 12 CRCRST: CRC reset Set and cleared by software. 0: No effect 1: Reset CRC Bits 11:9 Reserved, must be kept at reset value. Bit 8 FLASHRST: Flash memory interface reset Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode. 0: No effect 1: Reset Flash memory interface 230/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) Bits 7:2 Reserved, must be kept at reset value. Bit 1 DMA2RST: DMA2 reset Set and cleared by software. 0: No effect 1: Reset DMA2 Bit 0 DMA1RST: DMA1 reset Set and cleared by software. 0: No effect 1: Reset DMA1 8.4.11 AHB2 peripheral reset register (RCC_AHB2RSTR) Address offset: 0x2C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 RNG RST Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. ADC RST OTGFS RST 17 16 Res. AES RST rw Res. Res. Res. Res. Res. 2 rw 1 0 GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA RST RST RST RST RST RST RST RST rw rw rw rw rw rw rw rw rw Bits 31:19 Reserved, must be kept at reset value. Bit 18 RNGRST: Random number generator reset Set and cleared by software. 0: No effect 1: Reset RNG Bit 17 Reserved, must be kept at reset value. Bit 16 AESRST: AES hardware accelerator reset Set and cleared by software. 0: No effect 1: Reset AES Bits 15:14 Reserved, must be kept at reset value. Bit 13 ADCRST: ADC reset Set and cleared by software. 0: No effect 1: Reset ADC interface Bit 12 OTGFSRST: USB OTG FS reset Set and cleared by software. 0: No effect 1: Reset USB OTG FS Bits 11:8 Reserved, must be kept at reset value. DocID024597 Rev 1 231/1680 267 Reset and clock control (RCC) RM0351 Bit 7 GPIOHRST: IO port H reset Set and cleared by software. 0: No effect 1: Reset IO port H Bit 6 GPIOGRST: IO port G reset Set and cleared by software. 0: No effect 1: Reset IO port G Bit 5 GPIOFRST: IO port F reset Set and cleared by software. 0: No effect 1: Reset IO port F Bit 4 GPIOERST: IO port E reset Set and cleared by software. 0: No effect 1: Reset IO port E Bit 3 GPIODRST: IO port D reset Set and cleared by software. 0: No effect 1: Reset IO port D Bit 2 GPIOCRST: IO port C reset Set and cleared by software. 0: No effect 1: Reset IO port C Bit 1 GPIOBRST: IO port B reset Set and cleared by software. 0: No effect 1: Reset IO port B Bit 0 GPIOARST: IO port A reset Set and cleared by software. 0: No effect 1: Reset IO port A 8.4.12 AHB3 peripheral reset register (RCC_AHB3RSTR) Address offset: 0x30 Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. QSPI RST Res. Res. Res. Res. Res. Res. Res. FMC RST rw 232/1680 DocID024597 Rev 1 rw RM0351 Reset and clock control (RCC) Bits 31:9 Reserved, must be kept at reset value. Bit 8 QSPIRST: Quad SPI memory interface reset Set and cleared by software. 0: No effect 1: Reset QUADSPI Bits 7:1 Reserved, must be kept at reset value. Bit 0 FMCRST: Flexible memory controller reset Set and cleared by software. 0: No effect 1: Reset FMC DocID024597 Rev 1 233/1680 267 Reset and clock control (RCC) 8.4.13 RM0351 APB1 peripheral reset register 1 (RCC_APB1RSTR1) Address offset: 0x38 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 LPTIM1 OPAMP DAC1 RST RST RST 28 PWR RST rw rw rw rw 15 14 13 12 SPI3 RST SPI2 RST rw rw Res. Res. 27 26 25 Res. Res. CAN1 RST 11 10 9 Res. LCD RST 24 23 22 21 Res. I2C3R ST I2C2 RST I2C1 RST rw rw rw rw rw rw 7 6 5 4 3 2 1 0 Res. TIM7 RST TIM6 RST TIM5 RST TIM4 RST TIM3 RST TIM2 RST rw rw rw rw rw rw rw Res. 8 Res. Res. rw Bit 31 LPTIM1RST: Low Power Timer 1 reset Set and cleared by software. 0: No effect 1: Reset LPTIM1 Bit 30 OPAMPRST: OPAMP interface reset Set and cleared by software. 0: No effect 1: Reset OPAMP interface Bit 29 DAC1RST: DAC1 interface reset Set and cleared by software. 0: No effect 1: Reset DAC1 interface Bit 28 PWRRST: Power interface reset Set and cleared by software. 0: No effect 1: Reset PWR Bits 27:26 Reserved, must be kept at reset value. Bit 25 CAN1RST: CAN1 reset Set and reset by software. 0: No effect 1: resets the CAN1 Bit 24 Reserved, must be kept at reset value Bit 23 I2C3RST: I2C3 reset Set and reset by software. 0: No effect 1: resets I2C3 Bit 22 I2C2RST: I2C2 reset Set and cleared by software. 0: No effect 1: Reset I2C2 234/1680 DocID024597 Rev 1 20 19 18 17 UART5 UART4 USART3 USART2 RST RST RST RST 16 Res. rw RM0351 Reset and clock control (RCC) Bit 21 I2C1RST: I2C1 reset Set and cleared by software. 0: No effect 1: Reset I2C1 Bit 20 UART5RST: UART5 reset Set and cleared by software. 0: No effect 1: Reset UART5 Bit 19 UART4RST: UART4 reset Set and cleared by software. 0: No effect 1: Reset UART4 Bit 18 USART3RST: USART3 reset Set and cleared by software. 0: No effect 1: Reset USART3 Bit 17 USART2RST: USART2 reset Set and cleared by software. 0: No effect 1: Reset USART2 Bit 16 Reserved, must be kept at reset value. Bit 15 SPI3RST: SPI3 reset Set and cleared by software. 0: No effect 1: Reset SPI3 Bit 14 SPI2RST: SPI2 reset Set and cleared by software. 0: No effect 1: Reset SPI2 Bits 13:10 Reserved, must be kept at reset value. Bit 9 LCDRST: LCD interface reset Set and cleared by software. 0: No effect 1: Reset LCD Bits 8:6 Reserved, must be kept at reset value. Bit 5 TIM7RST: TIM7 timer reset Set and cleared by software. 0: No effect 1: Reset TIM7 Bit 4 TIM6RST: TIM6 timer reset Set and cleared by software. 0: No effect 1: Reset TIM6 DocID024597 Rev 1 235/1680 267 Reset and clock control (RCC) RM0351 Bit 3 TIM5RST: TIM5 timer reset Set and cleared by software. 0: No effect 1: Reset TIM5 Bit 2 TIM4RST: TIM3 timer reset Set and cleared by software. 0: No effect 1: Reset TIM3 Bit 1 TIM3RST: TIM3 timer reset Set and cleared by software. 0: No effect 1: Reset TIM3 Bit 0 TIM2RST: TIM2 timer reset Set and cleared by software. 0: No effect 1: Reset TIM2 8.4.14 APB1 peripheral reset register 2 (RCC_APB1RSTR2) Address offset: 0x3C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. SWP MI1 RST Res. LP UART1 RST Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LPTIM2 RST rw Bits 31:6 Reserved, must be kept at reset value. Bit 5 LPTIM2RST: Low-power timer 2 reset Set and cleared by software. 0: No effect 1: Reset LPTIM2 Bits 4:3 Reserved, must be kept at reset value. Bit 2 SWPMI1RST: Single wire protocol reset Set and cleared by software. 0: No effect 1: Reset SWPMI1 Bit 1 Reserved, must be kept at reset value. Bit 0 LPUART1RST: Low-power UART 1 reset Set and cleared by software. 0: No effect 1: Reset LPUART1 236/1680 DocID024597 Rev 1 Res. rw rw RM0351 Reset and clock control (RCC) 8.4.15 APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x40 Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 DFSDM RST Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 Res. USART 1 RST TIM8 RST SPI1 RST TIM1 RST SDMMC 1 RST rw rw rw rw rw 23 22 21 Res. SAI2 RST SAI1 RST rw rw 6 5 rw 8 Res. Res. 7 Res. Res. Res. 20 19 18 Res. Res. TIM17 RST 4 3 Res. Res. 17 16 TIM16 TIM15R RST ST rw rw 2 1 0 Res. SYS CFG RST Res. rw rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 DFSDMRST: Digital filters for sigma-delta modulators (DFSDM) reset Set and cleared by software. 0: No effect 1: Reset DFSDM Bit 23 Reserved, must be kept at reset value. Bit 22 SAI2RST: Serial audio interface 2 (SAI2) reset Set and cleared by software. 0: No effect 1: Reset SAI2 Bit 21 SAI1RST: Serial audio interface 1 (SAI1) reset Set and cleared by software. 0: No effect 1: Reset SAI1 Bits 20:19 Reserved, must be kept at reset value. Bit 18 TIM17RST: TIM17 timer reset Set and cleared by software. 0: No effect 1: Reset TIM17 timer Bit 17 TIM16RST: TIM16 timer reset Set and cleared by software. 0: No effect 1: Reset TIM16 timer Bit 16 TIM15RST: TIM15 timer reset Set and cleared by software. 0: No effect 1: Reset TIM15 timer Bit 15 Reserved, must be kept at reset value. DocID024597 Rev 1 237/1680 267 Reset and clock control (RCC) RM0351 Bit 14 USART1RST: USART1 reset Set and cleared by software. 0: No effect 1: Reset USART1 Bit 13 TIM8RST: TIM8 timer reset Set and cleared by software. 0: No effect 1: Reset TIM8 timer Bit 12 SPI1RST: SPI1 reset Set and cleared by software. 0: No effect 1: Reset SPI1 Bit 11 TIM1RST: TIM1 timer reset Set and cleared by software. 0: No effect 1: Reset TIM1 timer Bit 10 SDMMC1RST: SDMMC reset Set and cleared by software. 0: No effect 1: Reset SDMMC Bits 9:1 Reserved, must be kept at reset value. Bit 0 SYSCFGRST: SYSCFG + COMP + VREFBUF reset 0: No effect 1: Reset SYSCFG + COMP + VREFBUF 8.4.16 AHB1 peripheral clock enable register (RCC_AHB1ENR) Address offset: 0x48 Reset value: 0x0000 0100 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSC EN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. CRC EN Res. Res. Res. FLASH EN Res. Res. Res. Res. Res. Res. DMA2 EN DMA1 EN rw rw rw rw 238/1680 rw DocID024597 Rev 1 RM0351 Reset and clock control (RCC) Bits 31:17 Reserved, must be kept at reset value. Bit 16 TSCEN: Touch Sensing Controller clock enable Set and cleared by software. 0: TSC clock disable 1: TSC clock enable Bits 15:13 Reserved, must be kept at reset value. Bit 12 CRCEN: CRC clock enable Set and cleared by software. 0: CRC clock disable 1: CRC clock enable Bits 11:9 Reserved, must be kept at reset value. Bit 8 FLASHEN: Flash memory interface clock enable Set and cleared by software. This bit can be disabled only when the Flash is in power down mode. 0: Flash memory interface clock disable 1: Flash memory interface clock enable Bits 7:2 Reserved, must be kept at reset value. Bit 1 DMA2EN: DMA2 clock enable Set and cleared by software. 0: DMA2 clock disable 1: DMA2 clock enable Bit 0 DMA1EN: DMA1 clock enable Set and cleared by software. 0: DMA1 clock disable 1: DMA1 clock enable 8.4.17 AHB2 peripheral clock enable register (RCC_AHB2ENR) Address offset: 0x4C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Note: 31 When the peripheral clock is not active, the peripheral registers read or write access is not supported. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RNG EN Res. AESEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 rw Res. Res. OTGFS ADCEN EN rw rw Res. Res. Res. Res. 2 rw 1 0 GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA EN EN EN EN EN EN EN EN rw rw DocID024597 Rev 1 rw rw rw rw rw rw 239/1680 267 Reset and clock control (RCC) RM0351 Bits 31:19 Reserved, must be kept at reset value. Bit 18 RNGEN: Random Number Generator clock enable Set and cleared by software. 0: Random Number Generator clock disabled 1: Random Number Generator clock enabled Bit 17 Reserved, must be kept at reset value. Bit 16 AESEN: AES accelerator clock enable Set and cleared by software. 0: AES clock disabled 1: AES clock enabled Bits 15:14 Reserved, must be kept at reset value. Bit 13 ADCEN: ADC clock enable Set and cleared by software. 0: ADC clock disabled 1: ADC clock enabled Bit 12 OTGFSEN: OTG full speed clock enable Set and cleared by software. 0: USB OTG full speed clock disabled 1: USB OTG full speed clock enabled Bits 11:8 Reserved, must be kept at reset value. Bit 7 GPIOHEN: IO port H clock enable Set and cleared by software. 0: IO port H clock disabled 1: IO port H clock enabled Bit 6 GPIOGEN: IO port G clock enable Set and cleared by software. 0: IO port G clock disabled 1: IO port G clock enabled Bit 5 GPIOFEN: IO port F clock enable Set and cleared by software. 0: IO port F clock disabled 1: IO port F clock enabled Bit 4 GPIOEEN: IO port E clock enable Set and cleared by software. 0: IO port E clock disabled 1: IO port E clock enabled Bit 3 GPIODEN: IO port D clock enable Set and cleared by software. 0: IO port D clock disabled 1: IO port D clock enabled 240/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) Bit 2 GPIOCEN: IO port C clock enable Set and cleared by software. 0: IO port C clock disabled 1: IO port C clock enabled Bit 1 GPIOBEN: IO port B clock enable Set and cleared by software. 0: IO port B clock disabled 1: IO port B clock enabled Bit 0 GPIOAEN: IO port A clock enable Set and cleared by software. 0: IO port A clock disabled 1: IO port A clock enabled 8.4.18 AHB3 peripheral clock enable register(RCC_AHB3ENR) Address offset: 0x50 Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. QSPI EN Res. Res. Res. Res. Res. Res. Res. FMC EN rw rw Bits 31:9 Reserved, must be kept at reset value. Bit 8 QSPIEN Quad SPI memory interface clock enable Set and cleared by software. 0: QUADSPI clock disable 1: QUADSPI clock enable Bits 7:1 Reserved, must be kept at reset value. Bit 0 FMCEN: Flexible memory controller clock enable Set and cleared by software. 0: FMC clock disable 1: FMC clock enable 8.4.19 APB1 peripheral clock enable register 1 (RCC_APB1ENR1) Address: 0x58 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access DocID024597 Rev 1 241/1680 267 Reset and clock control (RCC) Note: RM0351 When the peripheral clock is not active, the peripheral registers read or write access is not supported. 31 30 29 LPTIM1 OPAMP DAC1 EN EN EN rw 28 PWR EN 27 Res. rw rw rw 13 12 11 Res. WWD GEN 15 14 SPI3 EN SPI2 EN rw rw Res. 26 25 Res. CAN1 EN 24 23 22 21 20 19 Res. I2C3 EN I2C2 EN I2C1 EN UART5 EN UART4 EN rw rw rw rw rw rw rw 7 6 5 4 3 2 1 Res. TIM7 EN TIM6EN rw rw rw rw 10 9 Res. LCD EN 8 Res. Res. rw Bit 31 LPTIM1EN: Low power timer 1 clock enable Set and cleared by software. 0: LPTIM1 clock disabled 1: LPTIM1 clock enabled Bit 30 OPAMPEN: OPAMP interface clock enable Set and cleared by software. 0: OPAMP interface clock disabled 1: OPAMP interface clock enabled Bit 29 DAC1EN: DAC1 interface clock enable Set and cleared by software. 0: DAC1 interface clock disabled 1: DAC1 interface clock enabled Bit 28 PWREN: Power interface clock enable Set and cleared by software. 0: Power interface clock disabled 1: Power interface clock enabled Bits 27:26 Reserved, must be kept at reset value. Bit 25 CAN1EN: CAN1 clock enable Set and cleared by software. 0: CAN1 clock disabled 1: CAN1 clock enabled Bit 24 Reserved, must be kept at reset value. Bit 23 I2C3EN: I2C3 clock enable Set and cleared by software. 0: I2C3 clock disabled 1: I2C3 clock enabled Bit 22 I2C2EN: I2C2 clock enable Set and cleared by software. 0: I2C2 clock disabled 1: I2C2 clock enabled Bit 21 I2C1EN: I2C1 clock enable Set and cleared by software. 0: I2C1 clock disabled 1: I2C1 clock enabled 242/1680 DocID024597 Rev 1 18 17 USART3 USART2 EN EN TIM5EN TIM4EN TIM3EN rw rw rw 16 Res. 0 TIM2 EN rw RM0351 Reset and clock control (RCC) Bit 20 UART5EN: UART5 clock enable Set and cleared by software. 0: UART5 clock disabled 1: UART5 clock enabled Bit 19 UART4EN: UART4 clock enable Set and cleared by software. 0: UART4 clock disabled 1: UART4 clock enabled Bit 18 USART3EN: USART3 clock enable Set and cleared by software. 0: USART3 clock disabled 1: USART3 clock enabled Bit 17 USART2EN: USART2 clock enable Set and cleared by software. 0: USART2 clock disabled 1: USART2 clock enabled Bit 16 Reserved, must be kept at reset value. Bit 15 SPI3EN: SPI3 clock enable Set and cleared by software. 0: SPI3 clock disabled 1: SPI3 clock enabled Bit 14 SPI2EN: SPI2 clock enable Set and cleared by software. 0: SPI2 clock disabled 1: SPI2 clock enabled Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGEN: Window watchdog clock enable Set and cleared by software. 0: Window watchdog clock disabled 1: Window watchdog clock enabled Bit 10 Reserved, must be kept at reset value. Bit 9 LCDEN: LCD clock enable Set and cleared by software. 0: LCD clock disabled 1: LCD clock enabled Bits 8:6 Reserved, must be kept at reset value. Bit 5 TIM7EN: TIM7 timer clock enable Set and cleared by software. 0: TIM7 clock disabled 1: TIM7 clock enabled Bit 4 TIM6EN: TIM6 timer clock enable Set and cleared by software. 0: TIM6 clock disabled 1: TIM6 clock enabled DocID024597 Rev 1 243/1680 267 Reset and clock control (RCC) RM0351 Bit 3 TIM5EN: TIM5 timer clock enable Set and cleared by software. 0: TIM5 clock disabled 1: TIM5 clock enabled Bit 2 TIM4EN: TIM4 timer clock enable Set and cleared by software. 0: TIM4 clock disabled 1: TIM4 clock enabled Bit 1 TIM3EN: TIM3 timer clock enable Set and cleared by software. 0: TIM3 clock disabled 1: TIM3 clock enabled Bit 0 TIM2EN: TIM2 timer clock enable Set and cleared by software. 0: TIM2 clock disabled 1: TIM2 clock enabled 8.4.20 APB1 peripheral clock enable register 2 (RCC_APB1ENR2) Address offset: 0x5C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. SWP MI1 EN Res. LP UART1 EN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LPTIM2 EN Res. rw Bits 31:6 Reserved, must be kept at reset value. Bit 5 LPTIM2EN Low power timer 2 clock enable Set and cleared by software. 0: LPTIM2 clock disable 1: LPTIM2 clock enable Bits 4:3 Reserved, must be kept at reset value. 244/1680 DocID024597 Rev 1 rw RM0351 Reset and clock control (RCC) Bit 2 SWPMI1EN: Single wire protocol clock enable Set and cleared by software. 0: SWPMI1 clock disable 1: SWPMI1 clock enable Bit 1 Reserved, must be kept at reset value. Bit 0 LPUART1EN: Low power UART 1 clock enable Set and cleared by software. 0: LPUART1 clock disable 1: LPUART1 clock enable DocID024597 Rev 1 245/1680 267 Reset and clock control (RCC) 8.4.21 RM0351 APB2 peripheral clock enable register (RCC_APB2ENR) Address: 0x60 Reset value: 0x0000 0000 Access: word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported. 31 30 29 28 27 26 25 24 DFSDM EN 23 22 21 Res. SAI2 EN SAI1 EN 20 19 18 17 16 Res. Res. TIM 17EN TIM16 EN TIM15 EN Res. Res. Res. Res. Res. Res. Res. rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. USART 1 EN TIM8 EN SPI1 EN TIM1 EN SDMMC 1 EN Res. Res. FW EN Res. Res. Res. Res. Res. Res. SYS CFGEN rw rw rw rw rw rw rs Bits 31:25 Reserved, must be kept at reset value. Bit 24 DFSDMEN: DFSDM timer clock enable Set and cleared by software. 0: DFSDM clock disabled 1: DFSDM clock enabled Bit 23 Reserved, must be kept at reset value. Bit 22 SAI2EN: SAI2 clock enable Set and cleared by software. 0: SAI2 clock disabled 1: SAI2 clock enabled Bit 21 SAI1EN: SAI1 clock enable Set and cleared by software. 0: SAI1 clock disabled 1: SAI1 clock enabled Bits 20:19 Reserved, must be kept at reset value. Bit 18 TIM17EN: TIM17 timer clock enable Set and cleared by software. 0: TIM17 timer clock disabled 1: TIM17 timer clock enabled Bit 17 TIM16EN: TIM16 timer clock enable Set and cleared by software. 0: TIM16 timer clock disabled 1: TIM16 timer clock enabled Bit 16 TIM15EN: TIM15 timer clock enable Set and cleared by software. 0: TIM15 timer clock disabled 1: TIM15 timer clock enabled Bit 15 Reserved, must be kept at reset value. 246/1680 DocID024597 Rev 1 rw RM0351 Reset and clock control (RCC) Bit 14 USART1EN: USART1clock enable Set and cleared by software. 0: USART1clock disabled 1: USART1clock enabled Bit 13 TIM8EN: TIM8 timer clock enable Set and cleared by software. 0: TIM8 timer clock disabled 1: TIM8 timer clock enabled Bit 12 SPI1EN: SPI1 clock enable Set and cleared by software. 0: SPI1 clock disabled 1: SPI1 clock enabled Bit 11 TIM1EN: TIM1 timer clock enable Set and cleared by software. 0: TIM1 timer clock disabled 1: TIM1P timer clock enabled Bit 10 SDMMC1EN: SDMMC clock enable Set and cleared by software. 0: SDMMC clock disabled 1: SDMMC clock enabled Bits 9:8 Reserved, must be kept at reset value. Bit 7 FWEN: Firewall clock enable Set by software, reset by hardware. Software can only write 1. A write at 0 has no effect. 0: Firewall clock disabled 1: Firewall clock enabled Bits 6:1 Reserved, must be kept at reset value. Bit 0 SYSCFGEN: SYSCFG + COMP + VREFBUF clock enable Set and cleared by software. 0: SYSCFG + COMP + VREFBUF clock disabled 1: SYSCFG + COMP + VREFBUF clock enabled 8.4.22 AHB1 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR) Address offset: 0x68 Reset value: 0x0001 1303 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TSC SMEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. DMA2 SMEN DMA1 SMEN rw rw rw Res. Res. Res. CRCSMEN rw Res. Res. SRAM1 FLASH SMEN SMEN rw Res. rw DocID024597 Rev 1 Res. Res. Res. Res. 247/1680 267 Reset and clock control (RCC) RM0351 Bits 31:17 Reserved, must be kept at reset value. Bit 16 TSCSMEN: Touch Sensing Controller clocks enable during Sleep and Stop modes Set and cleared by software. 0: TSC clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TSC clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 15:13 Reserved, must be kept at reset value. Bit 12 CRCSMEN: CRC clocks enable during Sleep and Stop modes Set and cleared by software. 0: CRC clocks disabled by the clock gating(1) during Sleep and Stop modes 1: CRC clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 11:10 Reserved, must be kept at reset value. Bit 9 SRAM1SMEN: SRAM1 interface clocks enable during Sleep and Stop modes Set and cleared by software. 0: SRAM1 interface clocks disabled by the clock gating(1) during Sleep and Stop modes 1: SRAM1 interface clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 8 FLASHSMEN: Flash memory interface clocks enable during Sleep and Stop modes Set and cleared by software. 0: Flash memory interface clocks disabled by the clock gating(1) during Sleep and Stop modes 1: Flash memory interface clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 7:2 Reserved, must be kept at reset value. Bit 1 DMA2SMEN: DMA2 clocks enable during Sleep and Stop modes Set and cleared by software during Sleep mode. 0: DMA2 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: DMA2 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 0 DMA1SMEN: DMA1 clocks enable during Sleep and Stop modes Set and cleared by software. 0: DMA1 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: DMA1 clocks enabled by the clock gating(1) during Sleep and Stop modes 1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode. 8.4.23 AHB2 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB2SMENR) Address offset: 0x6C Reset value: 0x0005 32FF Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RNG SMEN Res. AES SMEN rw 248/1680 DocID024597 Rev 1 rw RM0351 15 Res. Reset and clock control (RCC) 14 Res. 13 12 ADC OTGFS SMEN SMEN rw rw 11 Res. 10 9 Res. SRAM2 SMEN 8 Res. 7 6 5 4 3 2 1 0 GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SMEN SMEN SMEN SMEN SMEN SMEN SMEN SMEN rw rw rw rw rw rw rw rw rw Bits 31:19 Reserved, must be kept at reset value. Bit 18 RNGSMEN: Random Number Generator clocks enable during Sleep and Stop modes Set and cleared by software. 0: Random Number Generator clocks disabled by the clock gating(1) during Sleep and Stop modes 1: Random Number Generator clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 17 Reserved, must be kept at reset value. Bit 16 AESSMEN: AES accelerator clocks enable during Sleep and Stop modes Set and cleared by software. 0: AES clocks disabled by the clock gating(1) during Sleep and Stop modes 1: AES clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 15:14 Reserved, must be kept at reset value. Bit 13 ADCSMEN: ADC clocks enable during Sleep and Stop modes Set and cleared by software. 0: ADC clocks disabled by the clock gating(1) during Sleep and Stop modes 1: ADC clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 12 OTGFSSMEN: OTG full speed clocks enable during Sleep and Stop modes Set and cleared by software. 0: USB OTG full speed clocks disabled by the clock gating(1) during Sleep and Stop modes 1: USB OTG full speed clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 11:10 Reserved, must be kept at reset value. Bit 9 SRAM2SMEN: SRAM2 interface clocks enable during Sleep and Stop modes Set and cleared by software. 0: SRAM2 interface clocks disabled by the clock gating(1) during Sleep and Stop modes 1: SRAM2 interface clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 8 Reserved, must be kept at reset value. Bit 7 GPIOHSMEN: IO port H clocks enable during Sleep and Stop modes Set and cleared by software. 0: IO port H clocks disabled by the clock gating(1) during Sleep and Stop modes 1: IO port H clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 6 GPIOGSMEN: IO port G clocks enable during Sleep and Stop modes Set and cleared by software. 0: IO port G clocks disabled by the clock gating(1) during Sleep and Stop modes 1: IO port G clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 5 GPIOFSMEN: IO port F clocks enable during Sleep and Stop modes Set and cleared by software. 0: IO port F clocks disabled by the clock gating(1) during Sleep and Stop modes 1: IO port F clocks enabled by the clock gating(1) during Sleep and Stop modes DocID024597 Rev 1 249/1680 267 Reset and clock control (RCC) RM0351 Bit 4 GPIOESMEN: IO port E clocks enable during Sleep and Stop modes Set and cleared by software. 0: IO port E clocks disabled by the clock gating(1) during Sleep and Stop modes 1: IO port E clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 3 GPIODSMEN: IO port D clocks enable during Sleep and Stop modes Set and cleared by software. 0: IO port D clocks disabled by the clock gating(1) during Sleep and Stop modes 1: IO port D clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 2 GPIOCSMEN: IO port C clocks enable during Sleep and Stop modes Set and cleared by software. 0: IO port C clocks disabled by the clock gating(1) during Sleep and Stop modes 1: IO port C clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 1 GPIOBSMEN: IO port B clocks enable during Sleep and Stop modes Set and cleared by software. 0: IO port B clocks disabled by the clock gating(1) during Sleep and Stop modes 1: IO port B clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 0 GPIOASMEN: IO port A clocks enable during Sleep and Stop modes Set and cleared by software. 0: IO port A clocks disabled by the clock gating(1) during Sleep and Stop modes 1: IO port A clocks enabled by the clock gating(1) during Sleep and Stop modes 1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode. 8.4.24 AHB3 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB3SMENR) Address offset: 0x70 Reset value: 0x00000 0101 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. QSPI SMEN Res. FMC SMEN Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:9 Reserved, must be kept at reset value. 250/1680 DocID024597 Rev 1 Res. Res. Res. Res. rw RM0351 Reset and clock control (RCC) Bit 8 QSPISMEN Quad SPI memory interface clocks enable during Sleep and Stop modes Set and cleared by software. 0: QUADSPI clocks disabled by the clock gating(1) during Sleep and Stop modes 1: QUADSPI clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 7:1 Reserved, must be kept at reset value. Bit 0 FMCSMEN: Flexible memory controller clocks enable during Sleep and Stop modes Set and cleared by software. 0: FMC clocks disabled by the clock gating(1) during Sleep and Stop modes 1: FMC clocks enabled by the clock gating(1) during Sleep and Stop modes 1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode. 8.4.25 APB1 peripheral clocks enable in Sleep and Stop modes register 1 (RCC_APB1SMENR1) Address: 0x78 Reset value: 0xF2FE CA3F Access: no wait state, word, half-word and byte access 31 30 29 28 LPTIM1 OPAMP DAC1 PWR SMEN SMEN SMEN SMEN 27 26 25 Res. Res. CAN1 SMEN 24 23 22 21 20 19 Res. I2C3 SMEN I2C2 SMEN I2C1 SMEN UART5 SMEN UART4 SMEN rw 18 17 16 USART3 USART2 SMEN SMEN Res. rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPI3 SMEN SPI2 SMEN Res. Res. WWDG SMEN Res. LCD SMEN Res. Res. Res. TIM7 SMEN TIM6 SMEN TIM5 SMEN TIM4 SMEN TIM3 SMEN TIM2 SMEN rw rw rw rw rw rw rw rw rw rw Bit 31 LPTIM1SMEN: Low power timer 1 clocks enable during Sleep and Stop modes Set and cleared by software. 0: LPTIM1 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: LPTIM1 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 30 OPAMPSMEN: OPAMP interface clocks enable during Sleep and Stop modes Set and cleared by software. 0: OPAMP interface clocks disabled by the clock gating(1) during Sleep and Stop modes 1: OPAMP interface clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 29 DAC1SMEN: DAC1 interface clocks enable during Sleep and Stop modes Set and cleared by software. 0: DAC1 interface clocks disabled by the clock gating(1) during Sleep and Stop modes 1: DAC1 interface clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 28 PWRSMEN: Power interface clocks enable during Sleep and Stop modes Set and cleared by software. 0: Power interface clocks disabled by the clock gating(1) during Sleep and Stop modes 1: Power interface clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 27:26 Reserved, must be kept at reset value. DocID024597 Rev 1 251/1680 267 Reset and clock control (RCC) RM0351 Bit 25 CAN1SMEN: CAN1 clocks enable during Sleep and Stop modes Set and cleared by software. 0: CAN1 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: CAN1 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 24 Reserved, must be kept at reset value. Bit 23 I2C3SMEN: I2C3 clocks enable during Sleep and Stop modes Set and cleared by software. 0: I2C3 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: I2C3 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 22 I2C2SMEN: I2C2 clocks enable during Sleep and Stop modes Set and cleared by software. 0: I2C2 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: I2C2 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 21 I2C1SMEN: I2C1 clocks enable during Sleep and Stop modes Set and cleared by software. 0: I2C1 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: I2C1 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 20 UART5SMEN: UART5 clocks enable during Sleep and Stop modes Set and cleared by software. 0: UART5 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: UART5 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 19 UART4SMEN: UART4 clocks enable during Sleep and Stop modes Set and cleared by software. 0: UART4 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: UART4 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 18 USART3SMEN: USART3 clocks enable during Sleep and Stop modes Set and cleared by software. 0: USART3 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: USART3 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 17 USART2SMEN: USART2 clocks enable during Sleep and Stop modes Set and cleared by software. 0: USART2 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: USART2 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 16 Reserved, must be kept at reset value. Bit 15 SPI3SMEN: SPI3 clocks enable during Sleep and Stop modes Set and cleared by software. 0: SPI3 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: SPI3 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 14 SPI2SMEN: SPI2 clocks enable during Sleep and Stop modes Set and cleared by software. 0: SPI2 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: SPI2 clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 13:12 Reserved, must be kept at reset value. 252/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) Bit 11 WWDGSMEN: Window watchdog clocks enable during Sleep and Stop modes Set and cleared by software. This bit is forced to ‘1’ by hardware when the hardware WWDG option is activated. 0: Window watchdog clocks disabled by the clock gating(1) during Sleep and Stop modes 1: Window watchdog clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 10 Reserved, must be kept at reset value. Bit 9 LCDSMEN: LCD clocks enable during Sleep and Stop modes Set and cleared by software. 0: LCD clocks disabled by the clock gating(1) during Sleep and Stop modes 1: LCD clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 8:6 Reserved, must be kept at reset value. Bit 5 TIM7SMEN: TIM7 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM7 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM7 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 4 TIM6SMEN: TIM6 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM6 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM6 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 3 TIM5SMEN: TIM5 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM5 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM5 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 2 TIM4SMEN: TIM4 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM4 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM4 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 1 TIM3SMEN: TIM3 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM3 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM3 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 0 TIM2SMEN: TIM2 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM2 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM2 clocks enabled by the clock gating(1) during Sleep and Stop modes 1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode. 8.4.26 APB1 peripheral clocks enable in Sleep and Stop modes register 2 (RCC_APB1SMENR2) Address offset: 0x7C Reset value: 0x0000 0025 Access: no wait state, word, half-word and byte access DocID024597 Rev 1 253/1680 267 Reset and clock control (RCC) RM0351 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. SWP MI1 SMEN Res. LP UART1 SMEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LPTIM 2SMEN rw Res. rw Bits 31:6 Reserved, must be kept at reset value. Bit 5 LPTIM2SMEN Low power timer 2 clocks enable during Sleep and Stop modes Set and cleared by software. 0: LPTIM2 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: LPTIM2 clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 4:3 Reserved, must be kept at reset value. Bit 2 SWPMI1SMEN: Single wire protocol clocks enable during Sleep and Stop modes Set and cleared by software. 0: SWPMI1 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: SWPMI1 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 1 Reserved, must be kept at reset value. Bit 0 LPUART1SMEN: Low power UART 1 clocks enable during Sleep and Stop modes Set and cleared by software. 0: LPUART1 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: LPUART1 clocks enabled by the clock gating(1) during Sleep and Stop modes 1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode. 254/1680 DocID024597 Rev 1 rw RM0351 Reset and clock control (RCC) 8.4.27 APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR) Address: 0x80 Reset value: 0x0167 7C01 Access: word, half-word and byte access 31 30 29 28 27 26 25 24 DFSDM SMEN 23 22 21 Res. SAI2 SMEN SAI1 SMEN 20 19 18 17 16 Res. Res. TIM17 SMEN TIM16 SMEN TIM15 SMEN Res. Res. Res. Res. Res. Res. Res. rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. SYS CFG SMEN rw Res. USART TIM8 1 SMEN SMEN rw rw SPI1 SMEN rw TIM1 SDMMC 1 SMEN SMEN rw rw rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 DFSDMSMEN: DFSDM timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: DFSDM clocks disabled by the clock gating(1) during Sleep and Stop modes 1: DFSDM clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 23 Reserved, must be kept at reset value. Bit 22 SAI2SMEN: SAI2 clocks enable during Sleep and Stop modes Set and cleared by software. 0: SAI2 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: SAI2 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 21 SAI1SMEN: SAI1 clocks enable during Sleep and Stop modes Set and cleared by software. 0: SAI1 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: SAI1 clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 20:19 Reserved, must be kept at reset value. Bit 18 TIM17SMEN: TIM17 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM17 timer clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM17 timer clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 17 TIM16SMEN: TIM16 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM16 timer clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM16 timer clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 16 TIM15SMEN: TIM15 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM15 timer clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM15 timer clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 15 Reserved, must be kept at reset value. DocID024597 Rev 1 255/1680 267 Reset and clock control (RCC) RM0351 Bit 14 USART1SMEN: USART1clocks enable during Sleep and Stop modes Set and cleared by software. 0: USART1clocks disabled by the clock gating(1) during Sleep and Stop modes 1: USART1clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 13 TIM8SMEN: TIM8 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM8 timer clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM8 timer clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 12 SPI1SMEN: SPI1 clocks enable during Sleep and Stop modes Set and cleared by software. 0: SPI1 clocks disabled by the clock gating during(1) Sleep and Stop modes 1: SPI1 clocks enabled by the clock gating during(1) Sleep and Stop modes Bit 11 TIM1SMEN: TIM1 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM1 timer clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM1P timer clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 10 SDMMC1SMEN: SDMMC clocks enable during Sleep and Stop modes Set and cleared by software. 0: SDMMC clocks disabled by the clock gating(1) during Sleep and Stop modes 1: SDMMC clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 9:1 Reserved, must be kept at reset value. Bit 0 SYSCFGSMEN: SYSCFG + COMP + VREFBUF clocks enable during Sleep and Stop modes Set and cleared by software. 0: SYSCFG + COMP + VREFBUF clocks disabled by the clock gating(1) during Sleep and Stop modes 1: SYSCFG + COMP + VREFBUF clocks enabled by the clock gating(1) during Sleep and Stop modes 1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode. 256/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) 8.4.28 Peripherals independent clock configuration register (RCC_CCIPR) Address: 0x88 Reset value: 0x0000 0000 Access: no wait states, word, half-word and byte access 31 30 DFSDM SEL SWP MI1 SEL 29 28 ADCSEL[1:0] 27 26 CLK48SEL[1:0] 25 24 SAI2SEL[1:0] 23 22 SAI1SEL[1:0] 21 20 LPTIM2SEL[1:0] 19 18 LPTIM1SEL[1:0 17 16 I2C3SEL[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2C2SEL[1:0] rw rw I2C1SEL[1:0] rw LPUART1SEL [1:0] rw rw rw UART5SEL [1:0] UART4SEL [1:0] rw rw rw rw USART3SEL [1:0] rw rw USART2SEL [1:0] rw rw USART1SEL [1:0] rw rw Bit 31 DFSDMSEL: DFSDM clock source selection This bit is set and cleared by software to select the DFSDM clock source. 0: PCLK selected as DFSDM clock 1: System clock (SYSCLK) used as DFSDM clock Bit 30 SWPMI1SEL: SWPMI1 clock source selection This bit is set and cleared by software to select the SWPMI1 clock source. 0: PCLK selected as SWPMI1 clock 1: HSI16 clock selected as SWPMI1 clock Bits 29:28 ADCSEL[1:0]: ADCs clock source selection These bits are set and cleared by software to select the clock source used by the ADC interface. 00: No clock selected 01: PLLSAI1 “R” clock (PLLADC1CLK) selected as ADCs clock 10: PLLSAI2 “R” clock (PLLADC2CLK) selected as ADCs clock 11: System clock selected as ADCs clock Bits 27:26 CLK48SEL[1:0]: 48 MHz clock source selection These bits are set and cleared by software to select the 48 MHz clock source used by USB OTG FS, RNG and SDMMC. 00: No clock selected 01: PLLSAI1 “Q” clock (PLL48M2CLK) selected as 48 MHz clock 10: PLL “Q” clock (PLL48M1CLK) selected as 48 MHz clock 11: MSI clock selected as 48 MHz clock Bits 25:24 SAI2SEL[1:0]: SAI2 clock source selection These bits are set and cleared by software to select the SAI2 clock source. 00: PLLSAI1 “P” clock (PLLSAI1CLK) selected as SAI2 clock 01: PLLSAI2 “P” clock (PLLSAI2CLK) selected as SAI2 clock 10: PLL “P” clock (PLLSAI3CLK) selected as SAI2 clock 11: External input SAI2_EXTCLK selected as SAI2 clock Caution: If the selected clock is the external clock, it is not possible to switch to another clock if the external clock is not present. DocID024597 Rev 1 257/1680 267 Reset and clock control (RCC) RM0351 Bits 23:22 SAI1SEL[1:0]: SAI1 clock source selection These bits are set and cleared by software to select the SAI1 clock source. 00: PLLSAI1 “P” clock (PLLSAI1CLK) selected as SAI1 clock 01: PLLSAI2 “P” clock (PLLSAI2CLK) selected as SAI1 clock 10: PLL “P” clock (PLLSAI3CLK) selected as SAI1 clock 11: External input SAI1_EXTCLK selected as SAI1 clock Caution: If the selected clock is the external clock, it is not possible to switch to another clock if the external clock is not present. Bits 21:20 LPTIM2SEL[1:0]: Low power timer 2 clock source selection These bits are set and cleared by software to select the LPTIM2 clock source. 00: PCLK selected as LPTIM2 clock 01: LSI clock selected as LPTIM2 clock 10: HSI16 clock selected as LPTIM2 clock 11: LSE clock selected as LPTIM2 clock Bits 19:18 LPTIM1SEL[1:0]: Low power timer 1 clock source selection These bits are set and cleared by software to select the LPTIM1 clock source. 00: PCLK selected as LPTIM1 clock 01: LSI clock selected as LPTIM1 clock 10: HSI16 clock selected as LPTIM1 clock 11: LSE clock selected as LPTIM1 clock Bits 17:16 I2C3SEL[1:0]: I2C3 clock source selection These bits are set and cleared by software to select the I2C3 clock source. 00: PCLK selected as I2C3 clock 01: System clock (SYSCLK) selected as I2C3 clock 10: HSI16 clock selected as I2C3 clock 11: reserved Bits 15:13 I2C2SEL[1:0]: I2C2 clock source selection These bits are set and cleared by software to select the I2C2 clock source. 00: PCLK selected as I2C2 clock 01: System clock (SYSCLK) selected as I2C2 clock 10: HSI16 clock selected as I2C2 clock 11: reserved Bits 13:12 I2C1SEL[1:0]: I2C1 clock source selection These bits are set and cleared by software to select the I2C1 clock source. 00: PCLK selected as I2C1 clock 01: System clock (SYSCLK) selected as I2C1 clock 10: HSI16 clock selected as I2C1 clock 11: reserved Bits 11:10 LPUART1SEL[1:0]: LPUART1 clock source selection These bits are set and cleared by software to select the LPUART1 clock source. 00: PCLK selected as LPUART1 clock 01: System clock (SYSCLK) selected as LPUART1 clock 10: HSI16 clock selected as LPUART1 clock 11: LSE clock selected as LPUART1 clock 258/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) Bits 9:8 UART5SEL[1:0]: UART5 clock source selection These bits are set and cleared by software to select the UART5 clock source. 00: PCLK selected as UART5 clock 01: System clock (SYSCLK) selected as UART5 clock 10: HSI16 clock selected as UART5 clock 11: LSE clock selected as UART5 clock Bits 7:6 UART4SEL[1:0]: UART4 clock source selection This bit is set and cleared by software to select the UART4 clock source. 00: PCLK selected as UART4 clock 01: System clock (SYSCLK) selected as UART4 clock 10: HSI16 clock selected as UART4 clock 11: LSE clock selected as UART4 clock Bits 5:4 USART3SEL[1:0]: USART3 clock source selection This bit is set and cleared by software to select the USART3 clock source. 00: PCLK selected as USART3 clock 01: System clock (SYSCLK) selected as USART3 clock 10: HSI16 clock selected as USART3 clock 11: LSE clock selected as USART3 clock Bits 3:2 USART2SEL[1:0]: USART2 clock source selection This bit is set and cleared by software to select the USART2 clock source. 00: PCLK selected as USART2 clock 01: System clock (SYSCLK) selected as USART2 clock 10: HSI16 clock selected as USART2 clock 11: LSE clock selected as USART2 clock Bits 1:0 USART1SEL[1:0]: USART1 clock source selection This bit is set and cleared by software to select the USART1 clock source. 00: PCLK selected as USART1 clock 01: System clock (SYSCLK) selected as USART1 clock 10: HSI16 clock selected as USART1 clock 11: LSE clock selected as USART1 clock DocID024597 Rev 1 259/1680 267 Reset and clock control (RCC) 8.4.29 RM0351 Backup domain control register (RCC_BDCR) Address offset: 0x90 Reset value: 0x0000 0000, reset by Backup domain Reset, except LSCOSEL, LSCOEN and BDRST which are reset only by Backup domain power-on reset. Access: 0 ≤wait state ≤3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. Note: The bits of the Backup domain control register (RCC_BDCR) are outside of the VCORE domain. As a result, after Reset, these bits are write-protected and the DBP bit in the Section 6.4.1: Power control register 1 (PWR_CR1) has to be set before these can be modified. Refer to Section 6.1.5: Battery backup domain on page 142 for further information. These bits (except LSCOSEL, LSCOEN and BDRST) are only reset after a Backup domain Reset (see Section 8.1.3: Backup domain reset). Any internal or external Reset will not have any effect on these bits. 31 Res. 30 Res. 15 RTC EN 14 Res. rw 29 Res. 13 Res. 28 Res. 12 Res. 27 Res. 11 Res. 26 25 24 23 22 21 20 19 18 17 16 Res. LSCO SEL LSCO EN Res. Res. Res. Res. Res. Res. Res. BDRST rw rw 9 8 10 Res. RTCSEL[1:0] rw rw 7 Res. 6 rw Bits 31:26 Reserved, must be kept at reset value. Bit 25 LSCOSEL: Low speed clock output selection Set and cleared by software. 0: LSI clock selected 1: LSE clock selected Bit 24 LSCOEN: Low speed clock output enable Set and cleared by software. 0: Low speed clock output (LSCO) disable 1: Low speed clock output (LSCO) enable Bits 23:17 Reserved, must be kept at reset value. Bit 16 BDRST: Backup domain software reset Set and cleared by software. 0: Reset not activated 1: Resets the entire Backup domain Bit 15 RTCEN: RTC clock enable Set and cleared by software. 0: RTC clock disabled 1: RTC clock enabled Bits 14:10 Reserved, must be kept at reset value. 260/1680 5 LSE LSE CSSD CSSON DocID024597 Rev 1 r rw 4 3 LSEDRV[1:0] rw rw 2 1 0 LSE BYP LSE RDY LSEON rw r rw RM0351 Reset and clock control (RCC) Bits 9:8 RTCSEL[1:0]: RTC clock source selection Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them. 00: No clock 01: LSE oscillator clock used as RTC clock 10: LSI oscillator clock used as RTC clock 11: HSE oscillator clock divided by 32 used as RTC clock Bit 7 Reserved, must be kept at reset value. Bit 6 LSECSSD CSS on LSE failure Detection Set by hardware to indicate when a failure has been detected by the Clock Security System on the external 32 kHz oscillator (LSE). 0: No failure detected on LSE (32 kHz oscillator) 1: Failure detected on LSE (32 kHz oscillator) Bit 5 LSECSSON CSS on LSE enable Set by software to enable the Clock Security System on LSE (32 kHz oscillator). LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software MUST disable the LSECSSON bit. 0: CSS on LSE (32 kHz external oscillator) OFF 1: CSS on LSE (32 kHz external oscillator) ON Bits 4:3 LSEDRV[1:0] LSE oscillator drive capability Set by software to modulate the LSE oscillator’s drive capability. 00: ‘Xtal mode’ lower driving capability 01: ‘Xtal mode’ medium low driving capability 10: ‘Xtal mode’ medium high driving capability 11: ‘Xtal mode’ higher driving capability The oscillator is in Xtal mode when it is not in bypass mode. Bit 2 LSEBYP: LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0). 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. 0: LSE oscillator not ready 1: LSE oscillator ready Bit 0 LSEON: LSE oscillator enable Set and cleared by software. 0: LSE oscillator OFF 1: LSE oscillator ON DocID024597 Rev 1 261/1680 267 Reset and clock control (RCC) 8.4.30 RM0351 Control/status register (RCC_CSR) Address: 0x94 Reset value: 0x0C00 0600, reset by system Reset, except reset flags by power Reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LPWR RSTF WWDG RSTF IWWG RSTF SFT RSTF BOR RSTF PIN RSTF OB L RSTF FW RSTF RMVF Res. Res. Res. Res. Res. Res. Res. r r r r r r r r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. LSI RDY LSION r rw Res. Res. Res. Res. MSISRANGE[3:0] rw rw rw Res. Res. Res. Res. Res. rw Bit 31 LPWRSTF: Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, Standby or Shutdown mode entry. Cleared by writing to the RMVF bit. 0: No illegal mode reset occurred 1: Illegal mode reset occurred Bit 30 WWDGRSTF: Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit. 0: No window watchdog reset occurred 1: Window watchdog reset occurred Bit 29 IWDGRSTF: Independent window watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by writing to the RMVF bit. 0: No independent watchdog reset occurred 1: Independent watchdog reset occurred Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 BORRSTF: BOR flag Set by hardware when a BOR occurs. Cleared by writing to the RMVF bit. 0: No BOR occurred 1: BOR occurred Bit 26 PINRSTF: Pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit. 0: No reset from NRST pin occurred 1: Reset from NRST pin occurred 262/1680 DocID024597 Rev 1 RM0351 Reset and clock control (RCC) Bit 25 OBLRSTF: Option byte loader reset flag Set by hardware when a reset from the Option Byte loading occurs. Cleared by writing to the RMVF bit. 0: No reset from Option Byte loading occurred 1: Reset from Option Byte loading occurred Bit 24 FWRSTF: Firewall reset flag Set by hardware when a reset from the firewall occurs. Cleared by writing to the RMVF bit. 0: No reset from the firewall occurred 1: Reset from the firewall occurred Bit 23 RMVF: Remove reset flag Set by software to clear the reset flags. 0: No effect 1: Clear the reset flags Bits 22:12 Reserved, must be kept at reset value. Bits 11:8 MSISRANGE[3:1] MSI range after Standby mode Set by software to chose the MSI frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a pad or a power-on reset, the range is always 4 MHz. MSISRANGE can be written only when MSIRGSEL = ‘1’. 0100: Range 4 around 1 MHz 0101: Range 5 around 2 MHz 0101: Range 6 around 4 MHz (reset value) 0111: Range 7 around 8 MHz others: reserved Note: Changing the MSISRANGE does not change the current MSI frequency. Bits 7:2 Reserved, must be kept at reset value. Bit 1 LSIRDY: LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC. 0: LSI oscillator not ready 1: LSI oscillator ready Bit 0 LSION: LSI oscillator enable Set and cleared by software. 0: LSI oscillator OFF 1: LSI oscillator ON DocID024597 Rev 1 263/1680 267 0x20 RCC_CICR 264/1680 DocID024597 Rev 1 PLLSAI1RDYF. PLLRDYF HSERDYF HSIRDYF MSIRDYF LSERDYF LSIRDYF 0 0 0 0 0 0 0 0 0 0 PLLRDYC HSERDYC HSIRDYC MSIRDYC LSERDYC LSIRDYC Reset value PLLSAI1RDYC Reset value 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HSERDYIE HSIRDYIE MSIRDYIE LSERDYIE LSIRDYIE 0 Res. x 0 1 1 MSITRIM[7:0] x 0 0 0 x x HPRE[3:0] 0 0 PLLM [2:0] MSIPLLEN MSIRDY MSION 0 MSIRGSEL MSIRANGE [3:0] x Res. HSION 0 Res. 0 Res. 0 PLLRDYIE 0 0 0 PLLSAI1RDYIE PLLN [6:0] Res. 0 Res. HSIRDY HSIKERON HSIASFS Res. Res. Res. 0 Res. 0 Res. HSEON Res. HSEBYP HSERDY 0 PLLSAI2RDYIE 0 CSSF 0 PLLSAI2RDYF PPRE1 [2:0] 0 CSSC PLLSAI2N [6:0] 0 Res. PLLSAI1N [6:0] 0 LSECSSIE. 0 0 PLLSAI2RDYC 1 0 Res. 0 LSECSSF 1 Res. 0 Res. PPRE2 [2:0] 0 Res. 0 0 Res. 1 Res. 0 0 Res. 0 0 Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. STOPWUCK HSICAL[7:0] 0 LSECSSC Reset value Res. 0 Res. 0 Res. x Res. PLLPEN PLLSAI1PEN 0 Res. PLLSAI2PEN Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. Res. CSSON Res. Res. Res. Res. 0 Res. Res. PLLSAI2P x Res. PLLP PLLSAI1P 0 Res. Res. Res. x Res. Res. 0 Res. Res. 0 0 Res. x Res. Res. Res. Res. Res. PLLON 0 Res. Res. PLLQEN 0 Res. 0 x Res. PLL SAI1Q [1:0] 0 PLLSAI1QEN 0 Res. Res. PLLQ [1:0] Res. 0 0 x Res. 0 0 Res. PLL SAI2R [1:0] x Res. 0 Res. HSITRIM[4:0] Res. 0 Res. PLL SAI1R [1:0] Res. 0 x Res. MCOSEL [2:0] Res. 0 Res. 0 Res. PLLRDY 0 Res. PLLR [1:0] PLLREN PLLSAI1ON 0 Res. 0 PLLSAI1REN PLLSAI2ON PLLSAI1RDY PLLSAI2RDY Res. Res. 0 Res. 0 PLLSAI2REN Res. Res. Res. Res. 0 Res. 0 Res. 0 0 Res. Res. 0 0 Res. Reset value Res. Reset value Res. Reset value 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. MCOPRE [2:0] Res. RCC_CFGR Res. Res. Res. 0 Res. Res. Res. 1 Res. RCC_CIFR Res. Reset value Res. 0x1C RCC_CIER Res. 0x14 RCC_ PLLSAI2 CFGR 0 0 Res. 0x10 RCC_ PLLSAI1 CFGR Res. Reset value Res. 0x18 RCC_PLL CFGR Res. 0x0C Res. Reset value Res. 0x08 RCC_ICSCR Res. 0x00 RCC_CR Res. 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. 8.4.31 Res. Reset and clock control (RCC) RM0351 RCC register map The following table gives the RCC register map and the reset values. Table 31. RCC register map and reset values 0 0 1 1 MSICAL[7:0] x SWS [1:0] SW [1:0] 0 0 0 0 x x PLL SRC [1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x58 RCC_ APB1ENR1 Reset value 0 0 0 0 I2C1EN UART5EN UART4EN USART3EN USART2EN 0 0 0 0 0 0 0 DocID024597 Rev 1 0 0 0 TIM5EN TIM4EN TIM3EN TIM2EN GPIOFEN GPIOEEN GPIODEN GPIOCEN GPIOBEN GPIOAEN 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. FMCEN DMA1EN 1 TIM7RST TIM6RST TIM5RST TIM4RST TIM3RST TIM2RST 0 0 0 0 0 Res. Res. SWPMI1RST Res. LPUART1RST Res. Res. Res. 0 0 0 SYSCFGRST Res. Res. LCDRST 0 LPTIM2RST Res. Res. Res. Res. Res. GPIOHRST GPIOGRST GPIOFRST GPIOERST GPIODRST GPIOCRST GPIOBRST GPIOARST 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. FMCRST Res. Res. Res. Res. 0 Res. QSPIRST Res. Res. Res. OTGFSRST Res. DMA1RST Res. Res. Res. Res. Res. Res. FLASHRST. Res. Res. CRCRST. Res. Res. Res. Res. TSCRST. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA2RST 0 DMA2EN Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Reset value TIM6EN GPIOHEN GPIOGEN 0 Res. FLASHEN Res. SDMMC1RST Res. Res. 0 TIM7EN 0 Res. Reset value Res. 0 Res. Res. Res. Res. Reset value QSPIEN Res. Res. Res. ADCRST. Res. Res. Res. Res. Res. AESRST. Res. 0 Res. 0 Res. 0 Res. 0 LCDEN TIM1RST 0 CRCEN Res. Res. SPI2RST Res. Res. SPI3RST Res. Res. Res. RNGRST. 0 Res. Res. Res. Res. Res. Res. 0 Res. SPI1RST 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 WWDGEN OTGFSEN 0 Res. 0 Res. TIM8RST 0 Res. Res. 0 ADCEN Res. USART1RST 0 Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. 0 Res. Reset value Res. USART2RST 0 Res. USART3RST 0 Res. UART4RST 0 SP3EN TIM15RST 0 TSCEN. UART5RST 0 SPI2EN TIM16RST 0 Res. I2C1RST 0 AESEN Res. TIM17RST Res. 0 Res. Res. Res. I2C2RST 0 Res. Res. Res. Res. Res. 0 Res. Res. Reset value RNGEN Res. Res. SAI1RST Res. I2C3RST Res. CAN1RST Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. SAI2RST 0 Res. Res. DFSDMRST Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. PWRRST Res. Res. DAC1RST Res. Reset value Res. I2C2EN Res. Res. Res. Res. Res. Res. Res. Res. 0 I2C3EN 0 Res. Res. Res. Reset value Res. CAN1EN Res. Res. Res. Res. 0 Res. Res. Res. LPTIM1RST OPAMPRST 0 Res. Res. Res. Res. 0 Res. RCC_AHB3 ENR 0 Res. 0x50 RCC_AHB2 ENR PWREN 0x4C RCC_AHB1 ENR DAC1EN 0x48 RCC_ APB2RSTR Res. RCC_ 0x3C APB1RSTR2 Res. Reset value Res. RCC_ 0x38 APB1RSTR1 Res. 0x40 RCC_ AHB3RSTR Res. 0x30 RCC_ AHB2RSTR Res. 0x2C RCC_ AHB1RSTR Res. 0x28 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register LPTIM1EN Offset OPAMPEN RM0351 Reset and clock control (RCC) Table 31. RCC register map and reset values (continued) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 265/1680 267 0x88 RCC_CCIPR Reset value 0 0 266/1680 0 0 0 0 0 Reset value 1 0 0 1 1 0 0 0 1 1 1 0 0 0 DocID024597 Rev 1 0 1 0 0 SDMMC1SMEN 1 1 1 0 0 0 0 0 0 0 0 0 0 TIM2SMEN SWPMI1SMEN TIM3SMEN Res. 1 1 1 Res. 1 LPUART1SMEN TIM5SMEN 1 TIM4SMEN TIM6SMEN 1 Res. Res. Res. Res. Res. GPIOASMEN Res. GPIOBSMEN 1 1 1 1 Res. GPIOESMEN GPIODSMEN 1 FMCSMEN GPIOFSMEN 1 GPIOCSMEN GPIOGSMEN 1 1 0 Res. 1 SYSCFGSMEN 1 Res. Res. Res. Res. DMA2SMEN DMA1SMEN Res. Res. Res. Res. Res. 0 SYSCFGEN Res. 0 Res. Res. Res. Res. Res. FIREWALLEN 0 USART1SEL USART2SEL USART3SEL Reset value TIM7SMEN 1 LPTIM2SMEN Res. Res. Res. Reset value Res. Res. GPIOHSMEN FLASHSMEN Res. Res. 1 Res. QSPISMEN 1 Res. Res. CRCSMEN 1 Res. Res. SDMMC1EN Res. Res. TIM1EN Res. 1 Res. Res. Reset value UART4SEL UART5SEL 1 SRAM1SMEN 1 SRAM2SMEN Res. SPI1EN 0 Res. Res. TIM8EN 0 LCDSMEN Res. USART1EN 0 Res. Res. TIM15EN TSCSMEN. Res. TIM16EN Res. 0 Res. Res. Res. Res. Res. OTGFSSMEN 1 WWDGSMEN Res. 1 Res. Res. ADCFSSMEN Res. 1 Res. Res. Res. AESSMEN Res. TIM17EN Res. Res. 0 Res. TIM1SMEN 1 LPUART1SEL SPI1SMEN I2C1SEL 1 Res. SPI2SMEN 1 Res. Res. 1 Res. SP3SMEN 1 Res. Res. Res. RNGSMEN Res. 0 TIM8SMEN Res. Res. Res. Res. SAI1EN Res. Res. SAI2EN Res. Res. DFSDMEN Res. Res. 0 USART1SMEN Res. Res. Res. Reset value I2C2SEL USART2SMEN 1 Res. USART3SMEN 1 Res. UART4SMEN 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. TIM15SMEN UART5SMEN 1 Res. Res. Reset value I2C3SEL TIM16SMEN 0 TIM17SMEN LPTIM1SEL I2C1SMEN 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. I2C2SMEN 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. I2C3SMEN Res. CAN1SMEN Res. 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 LPTIM2SEL SAI1SMEN Res. 1 SAI2SMEN SAI1SEL Res. Res. Reset value Res. DFSDMSMEN Res. RCC_ APB1SM ENR2 Res. 1 Res. 1 Res. PWRSMEN 1 Res. DAC1SMEN 1 SAI2SEL CLK48SEL RCC_ 0x80 APB2SMENR Res. RCC_ 0x70 AHB3SMENR Res. RCC_ 0x6C AHB2SMENR Res. RCC_ 0x68 AHB1SMENR Res. RCC_ APB2ENR Res. 0 LPUART1EN Res. SWPMI1EN Res. Res. LPTIM2EN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RCC_ APB1ENR2 ADCSEL LPTIM1SMEN OPAMPSMEN 0x7C Reset value Res. 0x78 RCC_ APB1SM ENR1 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. 0x60 DFSDMSEL 0x5C SWPMI1SEL Reset and clock control (RCC) RM0351 Table 31. RCC register map and reset values (continued) 0 0 1 1 1 1 1 0 0x94 PINRSTF OBLRSTF FIREWALLRSTF RMVF 0 0 0 0 0 0 0 0 0 DocID024597 Rev 1 Res. 0 1 0 MSIS RANGE[3:0] 1 LSECSSD LSECSSON 0 0 0 0 Res. Res. Res. Res. 0 LSEBYP LSERDY LSEON 0 0 0 Res. LSION LSE DRV [1:0] LSIRDY 0 Res. RTC SEL [1:0] Res. Res. Res. Res. Res. Res. RTCEN 0 Res. BDRST Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. LSCOEN Res. Res. Res. Res. Res. LSCOSEL Reset value Res. BORRSTF Reset value SFTRSTF RCC_CSR Res. RCC_BDCR IWDGRSTF 0x90 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register LPWRSTF Offset WWDGRSTF RM0351 Reset and clock control (RCC) Table 31. RCC register map and reset values (continued) 0 0 267/1680 267 General-purpose I/Os (GPIO) RM0351 9 General-purpose I/Os (GPIO) 9.1 Introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL). 9.2 9.3 GPIO main features • Output states: push-pull or open drain + pull-up/down • Output data from output data register (GPIOx_ODR) or peripheral (alternate function output) • Speed selection for each I/O • Input states: floating, pull-up/down, analog • Input data to input data register (GPIOx_IDR) or peripheral (alternate function input) • Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR • Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations • Analog function • Alternate function selection registers • Fast toggle capable of changing every two clock cycles • Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral functions GPIO functional description Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in several modes: • Input floating • Input pull-up • Input-pull-down • Analog • Output open-drain with pull-up or pull-down capability • Output push-pull with pull-up or pull-down capability • Alternate function push-pull with pull-up or pull-down capability • Alternate function open-drain with pull-up or pull-down capability Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIOx_ODR registers. In this way, there is no risk of an IRQ occurring between the read and the modify access. 268/1680 DocID024597 Rev 1 RM0351 General-purpose I/Os (GPIO) Figure 18 and Figure 19 show the basic structures of a standard and a 5 V tolerant I/O port bit, respectively. Table 32 gives the possible port bit configurations. Figure 18. Basic structure of an I/O port bit $QDORJ 7RRQFKLS SHULSKHUDO $OWHUQDWHIXQFWLRQLQSXW ,QSXWGDWDUHJLVWHU RQRII 9'',2[9'',2[ WULJJHU RQRII ,2SLQ 2XWSXWGULYHU 9'',2[ RQRII 3026 3URWHFWLRQ GLRGH 3XOO GRZQ 966 2XWSXW FRQWURO 966 1026 5HDGZULWH )URPRQFKLS SHULSKHUDO 3URWHFWLRQ GLRGH 3XOO XS ,QSXWGULYHU 2XWSXWGDWDUHJLVWHU :ULWH %LWVHWUHVHWUHJLVWHUV 5HDG 966 $OWHUQDWHIXQFWLRQRXWSXW 3XVKSXOO RSHQGUDLQRU GLVDEOHG $QDORJ 069 Figure 19. Basic structure of a five-volt tolerant I/O port bit 7RRQFKLS SHULSKHUDO ,QSXWGDWDUHJLVWHU $OWHUQDWHIXQFWLRQLQSXW 5HDGZULWH )URPRQFKLS SHULSKHUDO 2XWSXWGDWDUHJLVWHU :ULWH %LWVHWUHVHWUHJLVWHUV 5HDG $OWHUQDWHIXQFWLRQRXWSXW RQRII 9'',2[ 9''B)7 77/6FKPLWW WULJJHU RQRII 3XOO XS 3URWHFWLRQ GLRGH ,QSXWGULYHU ,2SLQ 2XWSXWGULYHU 9'',2[ RQRII 3026 2XWSXW FRQWURO 3XOO GRZQ 966 3URWHFWLRQ GLRGH 966 1026 966 3XVKSXOO RSHQGUDLQRU GLVDEOHG DLG 1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD. DocID024597 Rev 1 269/1680 286 General-purpose I/Os (GPIO) RM0351 Table 32. Port bit configuration table(1) MODE(i) [1:0] 01 10 00 11 OTYPER(i) OSPEED(i) [1:0] PUPD(i) [1:0] I/O configuration 0 0 0 GP output PP 0 0 1 GP output PP + PU 0 1 0 GP output PP + PD 1 1 Reserved 0 0 GP output OD 1 0 1 GP output OD + PU 1 1 0 GP output OD + PD 1 1 1 Reserved (GP output OD) 0 0 0 AF PP 0 0 1 AF PP + PU 0 1 0 AF PP + PD 1 1 Reserved 0 0 AF OD 1 0 1 AF OD + PU 1 1 0 AF OD + PD 1 1 1 Reserved 0 SPEED [1:0] 1 0 SPEED [1:0] 1 x x x 0 0 Input Floating x x x 0 1 Input PU x x x 1 0 Input PD x x x 1 1 Reserved (input floating) x x x 0 0 Input/output x x x 0 1 x x x 1 0 x x x 1 1 Analog Reserved 1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate function. 270/1680 DocID024597 Rev 1 RM0351 9.3.1 General-purpose I/Os (GPIO) General-purpose I/O (GPIO) During and just after reset, the alternate functions are not active and most of the I/O ports are configured in analog mode. The debug pins are in AF pull-up/pull-down after reset: • PA15: JTDI in pull-up • PA14: JTCK/SWCLK in pull-down • PA13: JTMS/SWDAT in pull-up • PB4: NJTRST in pull-up • PB3: JTDO in floating stateno pull-up/pull-down When the pin is configured as output, the value written to the output data register (GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull mode or open-drain mode (only the low level is driven, high level is HI-Z). The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB clock cycle. All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not depending on the value in the GPIOx_PUPDR register. 9.3.2 I/O pin alternate function multiplexer and mapping The device I/O pins are connected to on-board peripherals/modules through a multiplexer that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals available on the same I/O pin. Each I/O pin has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers: • After reset the multiplexer selection is alternate function 0 (AF0). The I/Os are configured in alternate function mode through GPIOx_MODER register. • The specific alternate function assignments for each pin are detailed in the device datasheet. In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripherals available in smaller packages. DocID024597 Rev 1 271/1680 286 General-purpose I/Os (GPIO) RM0351 To use an I/O in a given configuration, you have to proceed as follows: • Debug function: after each device reset these pins are assigned as alternate function pins immediately usable by the debugger host • GPIO: configure the desired I/O as output, input or analog in the GPIOx_MODER register. • Peripheral alternate function: • – Connect the I/O to the desired AFx in one of the GPIOx_AFRL or GPIOx_AFRH register. – Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER, GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively. – Configure the desired I/O as an alternate function in the GPIOx_MODER register. Additional functions: – For the ADC, DAC, OPAMP, and COMP, configure the desired I/O in analog mode in the GPIOx_MODER register and configure the required function in the ADC, DAC, OPAMP, and COMP registers. For the ADC, it is necessary to configure the GPIOx_ASCR register. – For the additional functions like RTC, WKUPx and oscillators, configure the required function in the related RTC, PWR and RCC registers. These functions have priority over the configuration in the standard GPIO registers. Please refer to the “Alternate function mapping” table in the device datasheet for the detailed mapping of the alternate function I/O pins. 9.3.3 I/O port control registers Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (pushpull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pullup/pull-down whatever the I/O direction. 9.3.4 I/O port data registers Each GPIO has two 16-bit memory-mapped data registers: input and output data registers (GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write accessible. The data input through the I/O are stored into the input data register (GPIOx_IDR), a read-only register. See Section 9.4.5: GPIO port input data register (GPIOx_IDR) (x = A..H) and Section 9.4.6: GPIO port output data register (GPIOx_ODR) (x = A..H) for the register descriptions. 9.3.5 I/O data bitwise handling The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset register has twice the size of GPIOx_ODR. To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i). When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i) resets the ODR(i) corresponding bit. 272/1680 DocID024597 Rev 1 RM0351 General-purpose I/Os (GPIO) Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set action takes priority. Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a “one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always be accessed directly. The GPIOx_BSRR register provides a way of performing atomic bitwise handling. There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: it is possible to modify one or more bits in a single atomic AHB write access. 9.3.6 GPIO locking mechanism It is possible to freeze the GPIO control registers by applying a specific write sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must be the same). When the LOCK sequence has been applied to a port bit, the value of the port bit can no longer be modified until the next MCU reset or peripheral reset. Each GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. The LOCK sequence (refer to Section 9.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A..H)) can only be performed using a word (32-bit long) access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits. For more details please refer to LCKR register description in Section 9.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A..H). 9.3.7 I/O alternate function input/output Two registers are provided to select one of the alternate function inputs/outputs available for each I/O. With these registers, you can connect an alternate function to some other pin as required by your application. This means that a number of possible peripheral functions are multiplexed on each GPIO using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can thus select any one of the possible functions for each I/O. The AF selection signal being common to the alternate function input and alternate function output, a single channel is selected for the alternate function input/output of a given I/O. To know which functions are multiplexed on each GPIO pin, refer to the device datasheet. 9.3.8 External interrupt/wakeup lines All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode.Section 13: Extended interrupts and events controller (EXTI) and to Section 13.3.2: Wakeup event management. DocID024597 Rev 1 273/1680 286 General-purpose I/Os (GPIO) 9.3.9 RM0351 Input configuration When the I/O port is programmed as input: • The output buffer is disabled • The Schmitt trigger input is activated • The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register • The data present on the I/O pin are sampled into the input data register every AHB clock cycle • A read access to the input data register provides the I/O state Figure 20 shows the input configuration of the I/O port bit. ,QSXWGDWDUHJLVWHU Figure 20. Input floating/pull up/pull down configurations 5HDGZULWH 2XWSXWGDWDUHJLVWHU :ULWH %LWVHWUHVHWUHJLVWHUV 5HDG RQ 77/6FKPLWW WULJJHU LQSXWGULYHU 9'',2[ 9'',2[ RQRII SURWHFWLRQ GLRGH SXOO XS ,2SLQ RQRII RXWSXWGULYHU SXOO GRZQ 966 SURWHFWLRQ GLRGH 966 069 9.3.10 Output configuration When the I/O port is programmed as output: • The output buffer is enabled: – Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated) – Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register activates the P-MOS • The Schmitt trigger input is activated • The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register • The data present on the I/O pin are sampled into the input data register every AHB clock cycle • A read access to the input data register gets the I/O state • A read access to the output data register gets the last written value Figure 21 shows the output configuration of the I/O port bit. 274/1680 DocID024597 Rev 1 RM0351 General-purpose I/Os (GPIO) ,QSXWGDWDUHJLVWHU Figure 21. Output configuration 5HDGZULWH 2XWSXWGDWDUHJLVWHU :ULWH %LWVHWUHVHWUHJLVWHUV 5HDG RQ 9'',2[ 9'',2[ 77/6FKPLWW WULJJHU RQRII ,QSXWGULYHU SURWHFWLRQ GLRGH SXOO XS 2XWSXWGULYHU 9'',2[ ,2SLQ RQRII 3026 2XWSXW FRQWURO SXOO GRZQ 966 1026 3XVKSXOORU 966 2SHQGUDLQ SURWHFWLRQ GLRGH 966 069 9.3.11 Alternate function configuration When the I/O port is programmed as alternate function: Note: • The output buffer can be configured in open-drain or push-pull mode • The output buffer is driven by the signals coming from the peripheral (transmitter enable and data) • The Schmitt trigger input is activated • The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register • The data present on the I/O pin are sampled into the input data register every AHB clock cycle • A read access to the input data register gets the I/O state The alternate function configuration described above is not applied when the selected alternate function is a LCD function or a SWPMI_IO. In this case, the I/O, programmed as an alternate function output, is configured as described in the analog configuration. Figure 22 shows the Alternate function configuration of the I/O port bit. DocID024597 Rev 1 275/1680 286 General-purpose I/Os (GPIO) RM0351 Figure 22. Alternate function configuration $OWHUQDWH IXQFWLRQ LQSXW %LW VHWUHVHW UHJLVWHUV 5HDG RQRII SURWHFWLRQ GLRGH 3XOO XS ,QSXW GULYHU 5HDGZULWH )URP RQFKLS SHULSKHUDO 9'',2[9'',2[ 77/ 6FKPLWW WULJJHU 2XWSXW GDWD UHJLVWHU :ULWH RQ ,QSXW GDWD UHJLVWHU 7R RQFKLS SHULSKHUDO ,2 SLQ 2XWSXW GULYHU RQRII 9'' 3026 2XWSXW FRQWURO SURWHFWLRQ GLRGH 3XOO GRZQ 966 966 1026 966 SXVKSXOO RU RSHQGUDLQ $OWHUQDWH IXQFWLRQ RXWSXW 06Y9 9.3.12 Analog configuration When the I/O port is programmed as analog configuration: • The output buffer is disabled • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0). • The weak pull-up and pull-down resistors are disabled by hardware • Read access to the input data register gets the value “0” Figure 23 shows the high-impedance, analog-input configuration of the I/O port bit. Figure 23. High impedance-analog configuration ,QSXWGDWDUHJLVWHU $QDORJ 7RRQFKLS SHULSKHUDO 5HDGZULWH )URPRQFKLS SHULSKHUDO 276/1680 2XWSXWGDWDUHJLVWHU :ULWH %LWVHWUHVHWUHJLVWHUV 5HDG RII 9'',2[ 77/6FKPLWW WULJJHU SURWHFWLRQ GLRGH ,QSXWGULYHU ,2SLQ SURWHFWLRQ GLRGH 966 $QDORJ 069 DocID024597 Rev 1 RM0351 9.3.13 General-purpose I/Os (GPIO) Using the HSE or LSE oscillator pins as GPIOs When the HSE or LSE oscillator is switched OFF (default state after reset), the related oscillator pins can be used as normal GPIOs. When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the RCC_CSR register) the oscillator takes control of its associated pins and the GPIO configuration of these pins has no effect. When the oscillator is configured in a user external clock mode, only the pin is reserved for clock input and the OSC_OUT or OSC32_OUT pin can still be used as normal GPIO. 9.3.14 Using the GPIO pins in the RTC supply domain The PC13/PC14/PC15 GPIO functionality is lost when the core supply domain is powered off (when the device enters Standby mode). In this case, if their GPIO configuration is not bypassed by the RTC configuration, these pins are set in an analog input mode. For details about I/O control by the RTC, refer to Section 34.3: RTC functional description on page 1054. DocID024597 Rev 1 277/1680 286 General-purpose I/Os (GPIO) 9.4 RM0351 GPIO registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table 33. The peripheral registers can be written in word, half word or byte mode. 9.4.1 GPIO port mode register (GPIOx_MODER) (x =A..H) Address offset:0x00 Reset values: 31 30 • 0xABFF FFFF for port A • 0xFFFF FEBF for port B • 0xFFFF FFFF for ports C..G • 0x0000 000F for port H 29 MODE15[1:0] 28 MODE14[1:0] 27 26 MODE13[1:0] 25 24 MODE12[1:0] 23 22 MODE11[1:0] 21 20 MODE10[1:0] 19 18 17 16 MODE9[1:0] MODE8[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODE7[1:0] MODE6[1:0] MODE5[1:0] MODE4[1:0] MODE3[1:0] MODE2[1:0] MODE1[1:0] MODE0[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 2y+1:2y MODEy[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode. 00: Input mode 01: General purpose output mode 10: Alternate function mode 11: Analog mode (reset state) 9.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..H) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OT15 OT14 OT13 OT12 OT11 OT10 OT9 OT8 OT7 OT6 OT5 OT4 OT3 OT2 OT1 OT0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 OTy: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type. 0: Output push-pull (reset state) 1: Output open-drain 278/1680 DocID024597 Rev 1 RM0351 General-purpose I/Os (GPIO) 9.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..H) Address offset: 0x08 Reset value: 31 • 0x0C00 0000 for port A • 0x0000 0000 for the other ports 30 29 OSPEED15 [1:0] 28 27 26 25 24 23 22 21 20 19 18 17 16 OSPEED14 [1:0] OSPEED13 [1:0] OSPEED12 [1:0] OSPEED11 [1:0] OSPEED10 [1:0] OSPEED9 [1:0] OSPEED8 [1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSPEED7 [1:0] OSPEED6 [1:0] OSPEED5 [1:0] OSPEED4 [1:0] OSPEED3 [1:0] OSPEED2 [1:0] OSPEED1 [1:0] OSPEED0 [1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 2y+1:2y OSPEEDy[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. 00: Low speed 01: Medium speed 10: Fast speed 11: High speed Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed. 9.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..H) Address offset: 0x0C Reset values: 31 30 PUPD15[1:0] rw rw 15 14 • 0x1210 0000 for port A • 0x6400 0000 for port B • 0x0000 0000 for other ports 29 28 PUPD14[1:0] rw rw 13 12 27 26 PUPD13[1:0] rw rw 11 10 25 24 23 22 21 20 19 18 17 16 PUPD12[1:0] PUPD11[1:0] PUPD10[1:0] PUPD9[1:0] PUPD8[1:0] rw rw rw rw rw rw rw rw rw rw 9 8 7 6 5 4 3 2 1 0 PUPD7[1:0] PUPD6[1:0] PUPD5[1:0] PUPD4[1:0] PUPD3[1:0] PUPD2[1:0] PUPD1[1:0] PUPD0[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 2y+1:2y PUPDy[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down 00: No pull-up, pull-down 01: Pull-up 10: Pull-down 11: Reserved DocID024597 Rev 1 279/1680 286 General-purpose I/Os (GPIO) 9.4.5 RM0351 GPIO port input data register (GPIOx_IDR) (x = A..H) Address offset: 0x10 Reset value: 0x0000 XXXX (where X means undefined) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 r r r r r r r r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 IDy: Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port. 9.4.6 GPIO port output data register (GPIOx_ODR) (x = A..H) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 ODy: Port output data bit (y = 0..15) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F). 9.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..H) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0 w w w w w w w w w w w w w w w w 280/1680 DocID024597 Rev 1 RM0351 General-purpose I/Os (GPIO) Bits 31:16 BRy: Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODx bit 1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority. Bits 15:0 BSy: Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODx bit 1: Sets the corresponding ODx bit 9.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..H) This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCKK rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw DocID024597 Rev 1 281/1680 286 General-purpose I/Os (GPIO) RM0351 Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. LOCK key write sequence: WR LCKR[16] = ‘1’ + LCKR[15:0] WR LCKR[16] = ‘0’ + LCKR[15:0] WR LCKR[16] = ‘1’ + LCKR[15:0] RD LCKR RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return ‘1’ until the next MCU reset or peripheral reset. Bits 15:0 LCKy: Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is ‘0. 0: Port configuration not locked 1: Port configuration locked 9.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..H) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 AFSEL7[3:0] rw 15 rw rw rw rw 14 13 12 11 AFSEL3[3:0] rw rw rw 26 25 24 23 AFSEL6[3:0] rw rw rw rw 10 9 8 7 AFSEL2[3:0] rw rw rw rw 22 21 20 19 AFSEL5[3:0] rw rw rw rw 6 5 4 3 AFSEL1[3:0] rw rw rw rw 282/1680 1000: AF8 1001: AF9 1010: AF10 1011: AF11 1100: AF12 1101: AF13 1110: AF14 1111: AF15 DocID024597 Rev 1 17 16 rw rw rw 2 1 0 AFSEL0[3:0] rw rw Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: 0000: AF0 0001: AF1 0010: AF2 0011: AF3 0100: AF4 0101: AF5 0110: AF6 0111: AF7 18 AFSEL4[3:0] rw rw rw RM0351 General-purpose I/Os (GPIO) 9.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..H) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 AFSEL15[3:0] 26 25 24 23 AFSEL14[3:0] 22 21 20 19 AFSEL13[3:0] 18 17 16 AFSEL12[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AFSEL11[3:0] rw rw rw AFSEL10[3:0] rw rw rw rw AFSEL9[3:0] rw rw rw rw AFSEL8[3:0] rw rw rw rw rw Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: 0000: AF0 0001: AF1 0010: AF2 0011: AF3 0100: AF4 0101: AF5 0110: AF6 0111: AF7 9.4.11 1000: AF8 1001: AF9 1010: AF10 1011: AF11 1100: AF12 1101: AF13 1110: AF14 1111: AF15 GPIO port bit reset register (GPIOx_BRR) (x =A..H) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 w w w w w w w w w w w w w w w w Bits 31:16 Reserved Bits 15:0 BRy: Port x Reset bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000 0: No action on the corresponding ODx bit 1: Reset the corresponding ODx bit 9.4.12 GPIO port analog switch control register (GPIOx_ASCR)(x = A..H) Address offset: 0x2C Reset value: 0x0000 0000 DocID024597 Rev 1 283/1680 286 General-purpose I/Os (GPIO) RM0351 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ASC15 ASC14 ASC13 ASC12 ASC11 ASC10 ASC9 ASC8 ASC7 ASC6 ASC5 ASC4 ASC3 ASC2 ASC1 ASC0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 ASCy: Port x analog switch control y (y= 0..15) These bits are written by software to configure the analog connection of the IOs 0: Disconnect analog switch to the ADC input (reset state) 1: Connect analog switch to the ADC input Note: This bis must be set prior to the ADC conversion. Only the IO which connected to the ADC input are effective. Other IO must be kept reset value 284/1680 DocID024597 Rev 1 Reset value 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 GPIOx_IDR (where x = A..H) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x14 GPIOx_ODR (where x = A..H) DocID024597 Rev 1 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 x x x x x x x x x x x x x x x OD11 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0 Reset value x OD10 Reset value ID12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GPIOx_OTYPER (where x = A..H) 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OT1 OT0 MODER0[1:0] 1 MODE0[1:0] 1 0 0 0 0 0 0 0 0 0 0 OSPEED0[1:0] MODER1[1:0] 1 OSPEED0[1:0] MODE1[1:0] 1 PUPD0[1:0] OT2 1 OT3 0 OSPEED1[1:0] MODER2[1:0] 1 OSPEED1[1:0] MODE2[1:0] 1 PUPD1[1:0] OT4 1 OT5 MODER3[1:0] 0 OSPEED2[1:0] MODE3[1:0] 1 OSPEED2[1:0] OT6 1 PUPD2[1:0] OT7 MODER4[1:0] 1 OSPEED3[1:0] MODE4[1:0] 1 OSPEED3[1:0] OT8 MODER5[1:0] MODER6[1:0] MODER7[1:0] MODER8[1:0] MODER9[1:0] MODER10[1:0] MODER11[1:0] MODER12[1:0] MODER13[1:0] 1 PUPD3[1:0] OT9 OSPEED4[1:0] 0 OSPEED4[1:0] MODE5[1:0] MODE6[1:0] MODE7[1:0] MODE8[1:0] MODE9[1:0] MODE10[1:0] MODE11[1:0] MODE12[1:0] MODE13[1:0] 1 PUPD4[1:0] OT11 OT10 OSPEED5[1:0] 0 OSPEED5[1:0] OT12 0 PUPD5[1:0] OT13 OSPEED6[1:0] 0 OSPEED6[1:0] 0 PUPD6[1:0] 0 1 1 PUPDR0[1:0] 0 1 1 PUPDR1[1:0] 0 1 1 PUPDR2[1:0] 1 Res. MODER14[1:0] 1 1 PUPDR3[1:0] 1 Res. MODE14[1:0] 1 1 PUPDR4[1:0] 1 Res. 1 PUPDR5[1:0] 1 OT14 1 OT15 OSPEED7[1:0] 1 Res. MODER15[1:0] 1 PUPDR6[1:0] 0 ID13 0 OD12 0 OD13 0 OSPEED7[1:0] 0 PUPD7[1:0] 0 PUPDR7[1:0] 0 OSPEED8[1:0] OSPEED9[1:0] OSPEED10[1:0] OSPEED11[1:0] OSPEED12[1:0] OSPEED13[1:0] OSPEED14[1:0] Reset value ID14 1 1 ID15 0 OSPEED8[1:0] 0 PUPD8[1:0] 0 1 OD14 0 0 1 OD15 0 1 PUPDR8[1:0] 0 OSPEED9[1:0] 0 PUPD9[1:0] 0 1 1 Res. 0 0 1 Res. 0 1 PUPDR9[1:0] 0 OSPEED10[1:0] 0 PUPD10[1:0] 0 1 1 Res. 1 0 1 Res. 0 1 PUPDR10[1:0] 0 OSPEED11[1:0] 0 PUPD11[1:0] 0 1 1 Res. 0 1 1 Res. 1 1 PUPDR11[1:0] 0 OSPEED12[1:0] 0 PUPD12[1:0] 1 1 1 Res. 0 0 1 Res. 0 1 PUPDR12[1:0] 0 OSPEED13[1:0] 0 PUPD13[1:0] OSPEED14[1:0] 0 1 0 Res. GPIOB_PUPDR 0 0 1 Res. Reset value 1 PUPDR13[1:0] GPIOA_PUPDR 0 1 0 Res. Reset value 1 Res. 0x0C GPIOx_OSPEEDR (where x = B..H) 0 PUPD14[1:0] Reset value PUPDR14[1:0] 0x0C GPIOA_OSPEEDR 1 0 Res. 0x08 GPIOx_MODER (where x = C..H) MODE15[1:0] Reset value 1 Res. 0x08 1 Res. 0x04 Reset value Res. 0x00 GPIOB_MODER OSPEED15[1:0] Reset value OSPEED15[1:0] 0x00 MODE0[1:0] MODE1[1:0] MODE2[1:0] MODE3[1:0] MODE4[1:0] MODE5[1:0] MODE6[1:0] MODE7[1:0] MODE8[1:0] MODE9[1:0] MODE10[1:0] MODE11[1:0] MODE12[1:0] MODE13[1:0] MODE14[1:0] MODE15[1:0] GPIOA_MODER PUPD15[1:0] 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register PUPDR15[1:0] Offset Res. 9.4.13 Res. RM0351 General-purpose I/Os (GPIO) GPIO register map The following table gives the GPIO register map and reset values. Table 33. GPIO register map and reset values 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 285/1680 286 General-purpose I/Os (GPIO) RM0351 Register 0x18 GPIOx_BSRR (where x = A..H) BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_LCKR (where x = A..H ) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCKK LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x1C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Res. Table 33. GPIO register map and reset values (continued) 0x20 GPIOx_AFRL (where x = A..H) 0x24 GPIOx_AFRH (where x = A..H) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x28 GPIOx_BRR (where x = A..H) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0x2C GPIOx_ASCR (where x = A..H) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASC14 ASC13 ASC12 ASC11 ASC10 ASC9 ASC8 ASC7 ASC6 ASC5 ASC4 ASC3 ASC2 ASC1 ASC0 Reset value BR15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 68 for the register boundary addresses. 286/1680 0 AFSEL15[3:0] AFSEL14[3:0] AFSEL13[3:0] AFSEL12[3:0] AFSEL11[3:0] AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0] ASC15 Reset value AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0] DocID024597 Rev 1 RM0351 System configuration controller (SYSCFG) 10 System configuration controller (SYSCFG) 10.1 SYSCFG main features The STM32L4x6 devices feature a set of configuration registers. The main purposes of the system configuration controller are the following: • Remapping memory areas • Managing the external interrupt line connection to the GPIOs • Managing robustness feature • Setting SRAM2 write protection and software erase • Configuring FPU interrupts • Enabling the firewall • Enabling /disabling I2C Fast-mode Plus driving capability on some I/Os and voltage booster for I/Os analog switches. 10.2 SYSCFG registers 10.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP) This register is used for specific configurations on memory remap. Address offset: 0x00 Reset value: 0x0000 000X (X is the memory mode selected by the BOOT0 pin and BOOT1 option bit) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res FB_ MODE Res Res Res Res Res rw MEM_MODE rw rw rw Bits 31:9 Reserved, must be kept at reset value. DocID024597 Rev 1 287/1680 299 System configuration controller (SYSCFG) RM0351 Bit 8 FB_MODE: Flash Bank mode selection 0: Flash Bank 1 mapped at 0x0800 0000 (and aliased @0x0000 0000) and Flash Bank 2 mapped at 0x0808 0000 (and aliased at 0x0008 0000) 1: Flash Bank2 mapped at 0x0800 0000 (and aliased @0x0000 0000) and Flash Bank 1 mapped at 0x0808 0000 (and aliased at 0x0008 0000) Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 MEM_MODE: Memory mapping selection These bits control the memory internal mapping at address 0x0000 0000. These bits are used to select the physical remap by software and so, bypass the BOOT pin and the option bit setting. After reset these bits take the value selected by BOOT0 pin and BOOT1 option bit. 000: Main Flash memory mapped at 0x00000000. 001: System Flash memory mapped at 0x00000000. 010: FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. 011: SRAM1 mapped at 0x00000000. 100: Reserved 101: Reserved 110: QUADSPI memory mapped at 0x00000000. 111: Reserved Note: When the FSMC is remapped at address 0x0000 0000, only the first two regions of Bank 1 memory controller (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) can be remapped. In remap mode, the CPU can access the external memory via ICode bus instead of System bus which boosts up the performance. 10.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1) Address offset: 0x04 Reset value: 0x7C00 0001 31 30 29 28 27 26 FPU_IE[5..0] 25 24 23 Res Res Res 22 21 20 19 18 17 16 I2C_ PB8_ FMP I2C_ PB7_ FMP I2C_ PB6_ FMP I2C3_ FMP I2C2_ FMP I2C1_ FMP I2C_ PB9_ FMP rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res BOOST EN Res Res Res Res Res Res Res FWDIS rw 288/1680 DocID024597 Rev 1 rc_w0 RM0351 System configuration controller (SYSCFG) Bits 31:26 FPU_IE[5..0]: Floating Point Unit interrupts enable bits FPU_IE[5]: Inexact interrupt enable FPU_IE[4]: Input denormal interrupt enable FPU_IE[3]: Overflow interrupt enable FPU_IE[2]: underflow interrupt enable FPU_IE[1]: Divide-by-zero interrupt enable FPU_IE[0]: Invalid operation interrupt enable Bits 25:23 Reserved, must be kept at reset value. Bit 22 I2C3_FMP: I2C3 Fast-mode Plus driving capability activation This bit enables the Fm+ driving mode on I2C3 pins selected through AF selection bits. 0: Fm+ mode is not enabled on I2C3 pins selected through AF selection bits 1: Fm+ mode is enabled on I2C3 pins selected through AF selection bits. Bit 21 I2C2_FMP: I2C2 Fast-mode Plus driving capability activation This bit enables the Fm+ driving mode on I2C2 pins selected through AF selection bits. 0: Fm+ mode is not enabled on I2C2 pins selected through AF selection bits 1: Fm+ mode is enabled on I2C2 pins selected through AF selection bits. Bit 20 I2C1_FMP: I2C1 Fast-mode Plus driving capability activation This bit enables the Fm+ driving mode on I2C1 pins selected through AF selection bits. 0: Fm+ mode is not enabled on I2C1 pins selected through AF selection bits 1: Fm+ mode is enabled on I2C1 pins selected through AF selection bits. Bit 19 I2C_PB9_FMP: Fast-mode Plus (Fm+) driving capability activation on PB9 This bit enables the Fm+ driving mode for PB9. 0: PB9 pin operates in standard mode. 1: Fm+ mode enabled on PB9 pin, and the Speed control is bypassed. Bit 18 I2C_PB8_FMP: Fast-mode Plus (Fm+) driving capability activation on PB8 This bit enables the Fm+ driving mode for PB8. 0: PB8 pin operates in standard mode. 1: Fm+ mode enabled on PB8 pin, and the Speed control is bypassed. Bit 17 I2C_PB7_FMP: Fast-mode Plus (Fm+) driving capability activation on PB7 This bit enables the Fm+ driving mode for PB7. 0: PB7 pin operates in standard mode. 1: Fm+ mode enabled on PB7 pin, and the Speed control is bypassed. Bit 16 I2C_PB6_FMP: Fast-mode Plus (Fm+) driving capability activation on PB6 This bit enables the Fm+ driving mode for PB6. 0: PB6 pin operates in standard mode. 1: Fm+ mode enabled on PB6 pin, and the Speed control is bypassed. Bits 15:9 Reserved, must be kept at reset value. DocID024597 Rev 1 289/1680 299 System configuration controller (SYSCFG) RM0351 Bit 8 BOOSTEN: I/O analog switch voltage booster enable 0: I/O analog switches are supplied by VDDA voltage. This is the recommended configuration when using the ADC in high VDDA voltage operation. 1: I/O analog switches are supplied by a dedicated voltage booster (supplied by VDD). This is the recommended configuration when using the ADC in low VDDA voltage operation. Bits 7:1 Reserved, must be kept at reset value. Bit 0 FWDIS: Firewall disable This bit is cleared by software to protect the access to the memory segments according to the Firewall configuration. Once enabled, the firewall cannot be disabled by software. Only a system reset set the bit. 0 : Firewall protection enabled 1 : Firewall protection disabled 10.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res EXTI3[2:0] rw rw Res rw EXTI2[2:0] rw rw Res rw EXTI1[2:0] rw rw Res rw EXTI0[2:0] rw rw Bits 31:15 Reserved, must be kept at reset value. Bits 14:12 EXTI3[2:0]: EXTI 3 configuration bits These bits are written by software to select the source input for the EXTI3 external interrupt. 000: PA[3] pin 001: PB[3] pin 010: PC[3] pin 011: PD[3] pin 100: PE[3] pin 101: PF[3] pin 110: PG[3] pin 111: Reserved Bit 11 Reserved, must be kept at reset value. 290/1680 DocID024597 Rev 1 rw RM0351 System configuration controller (SYSCFG) Bits 10:8 EXTI2[2:0]: EXTI 2 configuration bits These bits are written by software to select the source input for the EXTI2 external interrupt. 000: PA[2] pin 001: PB[2] pin 010: PC[2] pin 011: PD[2] pin 100: PE[2] pin 101: PF[2] pin 110: PG[2] pin 111: Reserved Bit 7 Reserved, must be kept at reset value. Bits 6:4 EXTI1[2:0]: EXTI 1 configuration bits These bits are written by software to select the source input for the EXTI1 external interrupt. 000: PA[1] pin 001: PB[1] pin 010: PC[1] pin 011: PD[1] pin 100: PE[1] pin 101: PF[1] pin 110: PG[1] pin 111: PH[1] pin Bit 3 Reserved, must be kept at reset value. Bits 2:0 EXTI0[2:0]: EXTI 0 configuration bits These bits are written by software to select the source input for the EXTI0 external interrupt. 000: PA[0] pin 001: PB[0] pin 010: PC[0] pin 011: PD[0] pin 100: PE[0] pin 101: PF[0] pin 110: PG[0] pin 111: PH[0] pin DocID024597 Rev 1 291/1680 299 System configuration controller (SYSCFG) 10.2.4 RM0351 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res EXTI7[2:0] rw rw Res rw EXTI6[2:0] rw rw Res rw EXTI5[2:0] rw rw Res rw EXTI4[2:0] rw rw Bits 31:15 Reserved, must be kept at reset value. Bits 14:12 EXTI7[2:0]: EXTI 7 configuration bits These bits are written by software to select the source input for the EXTI7 external interrupt. 000: PA[7] pin 001: PB[7] pin 010: PC[7] pin 011: PD[7] pin 100: PE[7] pin 101: PF[7] pin 110: PG[7] pin 111: Reserved Bit 11 Reserved, must be kept at reset value. Bits 10:8 EXTI6[2:0]: EXTI 6 configuration bits These bits are written by software to select the source input for the EXTI6 external interrupt. 000: PA[6] pin 001: PB[6] pin 010: PC[6] pin 011: PD[6] pin 100: PE[6] pin 101: PF[6] pin 110: PG[6] pin 111: Reserved Bit 7 Reserved, must be kept at reset value. 292/1680 DocID024597 Rev 1 rw RM0351 System configuration controller (SYSCFG) Bits 6:4 EXTI5[2:0]: EXTI 5 configuration bits These bits are written by software to select the source input for the EXTI5 external interrupt. 000: PA[5] pin 001: PB[5] pin 010: PC[5] pin 011: PD[5] pin 100: PE[5] pin 101: PF[5] pin 110: PG[5] pin 111: Reserved Bit 3 Reserved, must be kept at reset value. Bits 2:0 EXTI4[2:0]: EXTI 4 configuration bits These bits are written by software to select the source input for the EXTI4 external interrupt. 000: PA[4] pin 001: PB[4] pin 010: PC[4] pin 011: PD[4] pin 100: PE[4] pin 101: PF[4] pin 110: PG[4] pin 111: Reserved Note: Some of the I/O pins mentioned in the above register may not be available on small packages. 10.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res EXTI11[2:0] rw rw Res rw EXTI10[2:0] rw rw Res rw EXTI9[2:0] rw DocID024597 Rev 1 rw Res rw EXTI8[2:0] rw rw rw 293/1680 299 System configuration controller (SYSCFG) RM0351 Bits 31:15 Reserved, must be kept at reset value. Bits 14:12 EXTI11[2:0]: EXTI 11 configuration bits These bits are written by software to select the source input for the EXTI11 external interrupt. 000: PA[11] pin 001: PB[11] pin 010: PC[11] pin 011: PD[11] pin 100: PE[11] pin 101: PF[11] pin 110: PG[11] pin 111: Reserved Bit 11 Reserved, must be kept at reset value. Bits 10:8 EXTI10[2:0]: EXTI 10 configuration bits These bits are written by software to select the source input for the EXTI10 external interrupt. 000: PA[10] pin 001: PB[10] pin 010: PC[10] pin 011: PD[10] pin 100: PE[10] pin 101: PF[10] pin 110: PG[10] pin 111: Reserved Bit 7 Reserved, must be kept at reset value. Bits 6:4 EXTI9[2:0]: EXTI 9 configuration bits These bits are written by software to select the source input for the EXTI9 external interrupt. 000: PA[9] pin 001: PB[9] pin 010: PC[9] pin 011: PD[9] pin 100: PE[9] pin 101: PF[9] pin 110: PG[9] pin 111: Reserved Bit 3 Reserved, must be kept at reset value. Bits 2:0 EXTI8[2:0]: EXTI 8 configuration bits These bits are written by software to select the source input for the EXTI8 external interrupt. 000: PA[8] pin 001: PB[8] pin 010: PC[8] pin 011: PD[8] pin 100: PE[8] pin 101: PF[8] pin 110: PG[8] pin 111: Reserved Note: 294/1680 Some of the I/O pins mentioned in the above register may not be available on small packages. DocID024597 Rev 1 RM0351 System configuration controller (SYSCFG) 10.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res EXTI15[2:0] rw rw Res rw EXTI14[2:0] rw rw Res rw EXTI13[2:0] rw rw Res rw EXTI12[2:0] rw rw rw Bits 31:15 Reserved, must be kept at reset value. Bits 14:12 EXTI15[2:0]: EXTI15 configuration bits These bits are written by software to select the source input for the EXTI15 external interrupt. 000: PA[15] pin 001: PB[15] pin 010: PC[15] pin 011: PD[15] pin 100: PE[15] pin 101: PF[15] pin 110: PG[15] pin 111: Reserved Bit 11 Reserved, must be kept at reset value. Bits 10:8 EXTI14[2:0]: EXTI14 configuration bits These bits are written by software to select the source input for the EXTI14 external interrupt. 000: PA[14] pin 001: PB[14] pin 010: PC[14] pin 011: PD[14] pin 100: PE[14] pin 101: PF[14] pin 110: PG[14] pin 111: Reserved Bit 7 Reserved, must be kept at reset value. DocID024597 Rev 1 295/1680 299 System configuration controller (SYSCFG) RM0351 Bits 6:4 EXTI13[2:0]: EXTI13 configuration bits These bits are written by software to select the source input for the EXTI13 external interrupt. 000: PA[13] pin 001: PB[13] pin 010: PC[13] pin 011: PD[13] pin 100: PE[13] pin 101: PF[13] pin 110: PG[13] pin 111: Reserved Bit 3 Reserved, must be kept at reset value. Bits 2:0 EXTI12[2:0]: EXTI12 configuration bits These bits are written by software to select the source input for the EXTI12 external interrupt. 000: PA[12] pin 001: PB[12] pin 010: PC[12] pin 011: PD[12] pin 100: PE[12] pin 101: PF[12] pin 110: PG[12] pin 111: Reserved Note: Some of the I/O pins mentioned in the above register may not be available on small packages. 10.2.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR) Address offset: 0x18 System reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res SRAM2 SRAM2 BSY ER r rw Bits 31:2 Reserved, must be kept at reset value Bit 1 SRAM2BSY: SRAM2 busy by erase operation 0: No SRAM2 erase operation is on going. 1: SRAM2 erase operation is on going. Bit 0 SRAM2ER: SRAM2 Erase Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at the end of the SRAM2 erase operation. Note: This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register. 296/1680 DocID024597 Rev 1 RM0351 System configuration controller (SYSCFG) 10.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2) Address offset: 0x1C System reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res SPF Res Res Res Res ECCL PVDL SPL CLL rs rs rs rs rc_w1 Bits 31:9 Reserved, must be kept at reset value Bit 8 SPF: SRAM2 parity error flag This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing ‘1’. 0: No SRAM2 parity error detected 1: SRAM2 parity error detected Bits 7:4 Reserved, must be kept at reset value Bit 3 ECCL: ECC Lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Flash ECC error connection to TIM1/8/15/16/17 Break input. 0: ECC error disconnected from TIM1/8/15/16/17 Break input. 1: ECC error connected to TIM1/8/15/16/17 Break input. Bit 2 PVDL: PVD lock enable bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. 0: PVD interrupt disconnected from TIM1/8/15/16/17 Break input. PVDE and PLS[2:0] bits can be programmed by the application. 1: PVD interrupt connected to TIM1/8/15/16/17 Break input, PVDE and PLS[2:0] bits are read only. Bit 1 SPL: SRAM2 parity lock bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break inputs. 0: SRAM2 parity error signal disconnected from TIM1/8/15/16/17 Break inputs 1: SRAM2 parity error signal connected to TIM1/8/15/16/17 Break inputs Bit 0 CLL: Cortex®-M4 LOCKUP (Hardfault) output enable bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of Cortex®-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input 0: Cortex®-M4 LOCKUP output disconnected from TIM1/8/15/16/17 Break inputs 1: Cortex®-M4 LOCKUP output connected to TIM1/8/15/16/17 Break inputs 10.2.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR) Address offset: 0x20 DocID024597 Rev 1 297/1680 299 System configuration controller (SYSCFG) RM0351 System reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P31WP P30WP P29WP P28WP P27WP P26WP P25WP P24WP P23WP P22WP P21WP P20WP P19WP P18WP P17WP P16WP rs rs rs rs rs rs 15 14 13 12 11 10 P15WP P14WP P13WP P12WP P11WP P10WP rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs 9 8 7 6 5 4 3 2 1 0 P9WP P8WP P7WP P6WP P5WP P4WP P3WP P2WP P1WP P0WP rs rs rs rs rs rs rs rs rs rs Bits 31:0 PxWP (x= 0 to 31): SRAM2 page x write protection These bits are set by software and cleared only by a system reset. 0: Write protection of SRAM2 page x is disabled. 1: Write protection of SRAM2 page x is enabled. 10.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR) Address offset: 0x24 System reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 7 6 5 4 3 2 1 0 w w w 15 14 13 12 11 10 9 8 Res Res Res Res Res Res Res Res KEY[7:0] w w w w w Bits 31:8 Reserved, must be kept at reset value Bits 7:0 KEY[7:0]: SRAM2 write protection key for software erase The following steps are required to unlock the write protection of the SRAM2ER bit in the SYSCFG_CFGR2 register. 1. Write "0xCA” into Key[7:0] 2. Write "0x53” into Key[7:0] Writing a wrong key reactivates the write protection. 298/1680 DocID024597 Rev 1 P27WP P26WP P25WP P24WP P23WP P22WP P21WP P20WP P19WP P18WP P17WP P16WP P15WP P14WP P13WP P12WP P11WP P10WP P9WP P8WP P7WP P6WP P5WP P4WP Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFG_SKR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x24 SYSCFG_SWPR Res. 0x20 P28WP DocID024597 Rev 1 Reset value 0 0 0 0 0 0 CLL 0 SPL 0 0 0 0 0 KEY 0 0 0 0 0 0 0 0 0 0 0 Reset value SRAM2ER 0 SRAM2BSY EXTI13 [2:0] P0WP Res. Res. Res. I2C_PB8_FMP I2C_PB7_FMP I2C_PB6_FMP x x x Res. Res. Res. FWDIS Res. Res. Res. Res. BOOSTEN Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. EXTI9 [2:0] PVDL 0 0 Res. EXTI5 [2:0] Res. 0 Res. Res. EXTI1 [2:0] ECCL 0 0 0 Res. 0 Res. Res. I2C_PB9_FMP 0 P1WP Reset value 0 Res. EXTI14 [2:0] Res. 0 0 Res. EXTI10 [2:0] Res. 0 Res. Res. EXTI6 [2:0] 0 Res. 0 0 0 0 Res. 0 EXTI2 [2:0] Res. 0 0 0 SPF 0 Res. EXTI15 [2:0] 0 Res. EXTI11 [2:0] Res. 0 Res. 0 0 Res. 0 0 Res. EXTI7 [2:0] Res. EXTI3 [2:0] Res. Reset value Res. 0 0 Res. Reset value Res. 0 Res. Reset value Res. Reset value Res. I2C1_FMP 0 Res. I2C2_FMP 0 Res. Res. Res. Res. Res. Res. Res. I2C3_FMP Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 Res. Res. Res. Res. Res. FPU_IE[5..0] P2WP SYSCFG_CFGR2 1 Res. SYSCFG_SCSR 1 Res. SYSCFG_EXTICR4 1 Res. SYSCFG_EXTICR3 Res. SYSCFG_EXTICR2 0 Res. SYSCFG_EXTICR1 Res. Reset value P3WP 0x1C P29WP 0x18 Res. 0x14 Res. 0x10 SYSCFG_CFGR1 Res. Reset value Res. Res. Res. Res. Res. Res. FB_MODE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SYSCFG_ MEMRMP Res. 0x00 Res. Register Res. Offset Res. 0x0C P30WP 0x08 P31WP 0x04 Res. 10.2.11 Res. RM0351 System configuration controller (SYSCFG) SYSCFG register map The following table gives the SYSCFG register map and the reset values. Table 34. SYSCFG register map and reset values MEM_ MODE 0 0 0 1 EXTI0 [2:0] 0 0 0 0 EXTI4 [2:0] 0 EXTI8 [2:0] 0 EXTI12 [2:0] 0 0 0 0 0 0 Refer to Section 2.2.2 on page 68 for the register boundary addresses. 299/1680 299 Direct memory access controller (DMA) RM0351 11 Direct memory access controller (DMA) 11.1 Introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations. The two DMA controllers have 14 channels in total, each dedicated to managing memory access requests from one or more peripherals. Each has an arbiter for handling the priority between DMA requests. 11.2 300/1680 DMA main features • 14 independently configurable channels (requests) • Each channel is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software. • Priorities between requests from channels of one DMA are software programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, etc.) • Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size. • Support for circular buffer management • 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel • Memory-to-memory transfer • Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers • Access to Flash, SRAM, APB and AHB peripherals as source and destination • Programmable number of data to be transferred: up to 65535 DocID024597 Rev 1 RM0351 Direct memory access controller (DMA) The block diagram is shown in the following figure. Figure 24. DMA block diagram ,EXV ,&RGH 'EXV '&RGH )ODVKLQWHUIDFH &RUWH[0ZLWK)38 6EXV %XVPDWUL[ 65$0 '0$ 65$0 )0&DQG4XDG63, &K &K $+%SHULSKHUDOV ZLWK'0$FDSDELOLW\ '0$ &K $(6$'&$'&$'& $+% &5& '0$ &K &K 76& '0$ 5HVHW FORFNFRQWURO 5&& &K $3%SHULSKHUDOV ZLWK'0$FDSDELOLW\ %ULGJH $3% ')6'06$,6$,7,0 7,07,07,07,0 86$5763,6'00& $3%SHULSKHUDOV ZLWK'0$FDSDELOLW\ %ULGJH $3% '0$UHTXHVWV 6:30,/38$57'$& '$&,&,&,& 86$5786$578$57 8$5763,63,7,0 7,07,07,07,07,0 069 11.3 DMA implementation This manual describes the full set of features implemented in DMA1. DMA2 supports the same number of channels, and is identical to DMA1. Table 35. DMA implementation Feature Number of DMA channels DocID024597 Rev 1 DMA1 DMA2 7 7 301/1680 323 Direct memory access controller (DMA) 11.4 RM0351 DMA functional description The DMA controller performs direct memory transfer by sharing the system bus with the Cortex®-M4 core. The DMA request may stop the CPU access to the system bus for some bus cycles, when the CPU and DMA are targeting the same destination (memory or peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half of the system bus bandwidth (both to memory and peripheral) for the CPU. 11.4.1 DMA transactions After an event, the peripheral sends a request signal to the DMA Controller. The DMA controller serves the request depending on the channel priorities. As soon as the DMA Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA Controller. The peripheral releases its request as soon as it gets the Acknowledge from the DMA Controller. Once the request is de-asserted by the peripheral, the DMA Controller release the Acknowledge. If there are more requests, the peripheral can initiate the next transaction. In summary, each DMA transfer consists of three operations: 11.4.2 • The loading of data from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register • The storage of the data loaded to the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register • The post-decrementing of the DMA_CNDTRx register, which contains the number of transactions that have still to be performed. Arbiter The arbiter manages the channel requests based on their priority and launches the peripheral/memory access sequences. The priorities are managed in two stages: • • 302/1680 Software: each channel priority can be configured in the DMA_CCRx register. There are four levels: – Very high priority – High priority – Medium priority – Low priority Hardware: if 2 requests have the same software priority level, the channel with the lowest number will get priority versus the channel with the highest number. For example, channel 2 gets priority over channel 4. DocID024597 Rev 1 RM0351 11.4.3 Direct memory access controller (DMA) DMA channels Each channel can handle DMA transfer between a peripheral register located at a fixed address and a memory address. The amount of data to be transferred (up to 65535) is programmable. The register which contains the amount of data items to be transferred is decremented after each transaction. Programmable data sizes Transfer data sizes of the peripheral and memory are fully programmable through the PSIZE and MSIZE bits in the DMA_CCRx register. Pointer incrementation Peripheral and memory pointers can optionally be automatically post-incremented after each transaction depending on the PINC and MINC bits in the DMA_CCRx register. If incremented mode is enabled, the address of the next transfer will be the address of the previous one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer address is the one programmed in the DMA_CPARx/DMA_CMARx registers. During transfer operations, these registers keep the initially programmed value. The current transfer addresses (in the current internal peripheral/memory address register) are not accessible by software. If the channel is configured in non-circular mode, no DMA request is served after the last transfer (that is once the number of data items to be transferred has reached zero). In order to reload a new number of data items to be transferred into the DMA_CNDTRx register, the DMA channel must be disabled. Note: If a DMA channel is disabled, the DMA registers are not reset. The DMA channel registers (DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during the channel configuration phase. In circular mode, after the last transfer, the DMA_CNDTRx register is automatically reloaded with the initially programmed value. The current internal address registers are reloaded with the base address values from the DMA_CPARx/DMA_CMARx registers. Channel configuration procedure The following sequence should be followed to configure a DMA channel x (where x is the channel number). 1. Set the peripheral register address in the DMA_CPARx register. The data will be moved from/ to this address to/ from the memory after the peripheral event. 2. Set the memory address in the DMA_CMARx register. The data will be written to or read from this memory after the peripheral event. 3. Configure the total number of data to be transferred in the DMA_CNDTRx register. After each peripheral event, this value will be decremented. 4. Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register 5. Configure data transfer direction, circular mode, peripheral & memory incremented mode, peripheral & memory data size, and interrupt after half and/or full transfer in the DMA_CCRx register 6. Activate the channel by setting the ENABLE bit in the DMA_CCRx register. As soon as the channel is enabled, it can serve any DMA request from the peripheral connected on the channel. DocID024597 Rev 1 303/1680 323 Direct memory access controller (DMA) RM0351 Once half of the bytes are transferred, the half-transfer flag (HTIF) is set and an interrupt is generated if the Half-Transfer Interrupt Enable bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag (TCIF) is set and an interrupt is generated if the Transfer Complete Interrupt Enable bit (TCIE) is set. Circular mode Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_CCRx register. When circular mode is activated, the number of data to be transferred is automatically reloaded with the initial value programmed during the channel configuration phase, and the DMA requests continue to be served. Memory-to-memory mode The DMA channels can also work without being triggered by a request from a peripheral. This mode is called Memory to Memory mode. If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers as soon as it is enabled by software by setting the Enable bit (EN) in the DMA_CCRx register. The transfer stops once the DMA_CNDTRx register reaches zero. Memory to Memory mode may not be used at the same time as Circular mode. 11.4.4 Programmable data width, data alignment and endians When PSIZE and MSIZE are not equal, the DMA performs some data alignments as described in Table 36: Programmable data width & endian behavior (when bits PINC = MINC = 1). Table 36. Programmable data width & endian behavior (when bits PINC = MINC = 1) Number Source of data Destination port items to port width width transfer (NDT) Source content: address / data Transfer operations Destination content: address / data 8 8 4 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B1[7:0] @0x1 then WRITE B1[7:0] @0x1 3: READ B2[7:0] @0x2 then WRITE B2[7:0] @0x2 4: READ B3[7:0] @0x3 then WRITE B3[7:0] @0x3 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 8 16 4 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE 00B0[15:0] @0x0 2: READ B1[7:0] @0x1 then WRITE 00B1[15:0] @0x2 3: READ B3[7:0] @0x2 then WRITE 00B2[15:0] @0x4 4: READ B4[7:0] @0x3 then WRITE 00B3[15:0] @0x6 @0x0 / 00B0 @0x2 / 00B1 @0x4 / 00B2 @0x6 / 00B3 8 32 4 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE 000000B0[31:0] @0x0 2: READ B1[7:0] @0x1 then WRITE 000000B1[31:0] @0x4 3: READ B3[7:0] @0x2 then WRITE 000000B2[31:0] @0x8 4: READ B4[7:0] @0x3 then WRITE 000000B3[31:0] @0xC @0x0 / 000000B0 @0x4 / 000000B1 @0x8 / 000000B2 @0xC / 000000B3 16 8 4 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE B2[7:0] @0x1 3: READ B5B4[15:0] @0x4 then WRITE B4[7:0] @0x2 4: READ B7B6[15:0] @0x6 then WRITE B6[7:0] @0x3 @0x0 / B0 @0x1 / B2 @0x2 / B4 @0x3 / B6 16 16 4 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE B1B0[15:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE B3B2[15:0] @0x2 3: READ B5B4[15:0] @0x4 then WRITE B5B4[15:0] @0x4 4: READ B7B6[15:0] @0x6 then WRITE B7B6[15:0] @0x6 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 16 32 4 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE 0000B1B0[31:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE 0000B3B2[31:0] @0x4 3: READ B5B4[15:0] @0x4 then WRITE 0000B5B4[31:0] @0x8 4: READ B7B6[15:0] @0x6 then WRITE 0000B7B6[31:0] @0xC @0x0 / 0000B1B0 @0x4 / 0000B3B2 @0x8 / 0000B5B4 @0xC / 0000B7B6 304/1680 DocID024597 Rev 1 RM0351 Direct memory access controller (DMA) Table 36. Programmable data width & endian behavior (when bits PINC = MINC = 1) (continued) Number Source of data Destination port items to port width width transfer (NDT) Source content: address / data Transfer operations Destination content: address / data 32 8 4 @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC 1: READ B3B2B1B0[31:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B7B6B5B4[31:0] @0x4 then WRITE B4[7:0] @0x1 3: READ BBBAB9B8[31:0] @0x8 then WRITE B8[7:0] @0x2 4: READ BFBEBDBC[31:0] @0xC then WRITE BC[7:0] @0x3 @0x0 / B0 @0x1 / B4 @0x2 / B8 @0x3 / BC 32 16 4 @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC 1: READ B3B2B1B0[31:0] @0x0 then WRITE B1B0[15:0] @0x0 2: READ B7B6B5B4[31:0] @0x4 then WRITE B5B4[15:0] @0x2 3: READ BBBAB9B8[31:0] @0x8 then WRITE B9B8[15:0] @0x4 4: READ BFBEBDBC[31:0] @0xC then WRITE BDBC[15:0] @0x6 @0x0 / B1B0 @0x2 / B5B4 @0x4 / B9B8 @0x6 / BDBC 32 32 4 @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC 1: READ B3B2B1B0[31:0] @0x0 then WRITE B3B2B1B0[31:0] @0x0 @0x0 / B3B2B1B0 2: READ B7B6B5B4[31:0] @0x4 then WRITE B7B6B5B4[31:0] @0x4 @0x4 / B7B6B5B4 3: READ BBBAB9B8[31:0] @0x8 then WRITE BBBAB9B8[31:0] @0x8 @0x8 / BBBAB9B8 4: READ BFBEBDBC[31:0] @0xC then WRITE BFBEBDBC[31:0] @0xC @0xC / BFBEBDBC DocID024597 Rev 1 305/1680 323 Direct memory access controller (DMA) RM0351 Addressing an AHB peripheral that does not support byte or halfword write operations When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does not support byte or halfword write operations (when HSIZE is not used by the peripheral) and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two examples below: • To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD” with HSIZE = HalfWord • To write the byte “0xAB”, the DMA sets the HWDATA bus to “0xABABABAB” with HSIZE = Byte Assuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the HSIZE data into account, it will transform any AHB byte or halfword operation into a 32-bit APB operation in the following manner: • an AHB byte write operation of the data “0xB0” to 0x0 (or to 0x1, 0x2 or 0x3) will be converted to an APB word write operation of the data “0xB0B0B0B0” to 0x0 • an AHB halfword write operation of the data “0xB1B0” to 0x0 (or to 0x2) will be converted to an APB word write operation of the data “0xB1B0B1B0” to 0x0 For instance, if you want to write the APB backup registers (16-bit registers aligned to a 32bit address boundary), you must configure the memory source size (MSIZE) to “16-bit” and the peripheral destination size (PSIZE) to “32-bit”. 11.4.5 Error management A DMA transfer error can be generated by reading from or writing to a reserved address space. When a DMA transfer error occurs during a DMA read or a write access, the faulty channel is automatically disabled through a hardware clear of its EN bit in the corresponding Channel configuration register (DMA_CCRx). The channel's transfer error interrupt flag (TEIF) in the DMA_IFR register is set and an interrupt is generated if the transfer error interrupt enable bit (TEIE) in the DMA_CCRx register is set. 11.4.6 DMA interrupts An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for each DMA channel. Separate interrupt enable bits are available for flexibility. Table 37. DMA interrupt requests Interrupt event 306/1680 Event flag Enable control bit Half-transfer HTIF HTIE Transfer complete TCIF TCIE Transfer error TEIF TEIE DocID024597 Rev 1 RM0351 11.4.7 Direct memory access controller (DMA) DMA request mapping DMA controller The hardware requests from the peripherals (TIM1/2/3/4/5/6/7/8/15/16/17, ADC1/2/3, DAC1/2, SPI1/2/3, I2C1/2/3, SDMMC1, QUADSPI, SWPMI1, DFSDM, SAI1/2, AES, USART1/2/3, UART4/5 and LPUART1) are mapped to the DMA1 or DMA2 channels (1 to 7) through the DMA1/2 channel selection register. Refer to Figure 25: DMA1 request mapping and Figure 26: DMA2 request mapping. The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral. DocID024597 Rev 1 307/1680 323 Direct memory access controller (DMA) RM0351 Figure 25. DMA1 request mapping 3HULSKHUDOUHTXHVWVLJQDOV $'&7,0B&+7,0B&+7,0B83 7,0B&+ 6:WULJJHU 0(00(0ELW $'&63,B5;86$57B7;,&B7; 7,0B837,0B&+7,0B&+ 6:WULJJHU 0(00(0ELW $'&63,B7;86$57B5;,&B5; 7,0B&+7,0B837,0B&+ 7,0B837,0B83'$&7,0B&+ 6:WULJJHU 0(00(0ELW ')6'063,B5;86$57B7; ,&B7;7,0B83'$&7,0B&+ 7,0B&+7,0B75,*7,0B&20 6:WULJJHU 0(00(0ELW ')6'063,B7;86$57B5; ,&B5;7,0B&+48$'63, 7,0B&+7,0B&+7,0B83 7,0B75,*7,0B&20 6:WULJJHU 0(00(0ELW ')6'06$,B$86$57B5;,&B7; 7,0B&+7,0B837,0B&+ 7,0B75,*7,0B83 6:WULJJHU 0(00(0ELW ')6'06$,B%86$57B7;,&B5; 7,0B&+7,0B&+7,0B&+ 7,0B837,0B837,0B&+ 6:WULJJHU 0(00(0ELW '0$FKDQQHO &KDQQHO '0$B5(4 )L[HGKDUGZDUHSULRULW\ +LJKSULRULW\ &6 &KDQQHO '0$B5(4 &6 &KDQQHO '0$B5(4 &6 &KDQQHO '0$B5(4 ,QWHUQDO'0$ UHTXHVW &6 &KDQQHO '0$B5(4 &6 &KDQQHO '0$B5(4 &6 &KDQQHO '0$B5(4 /RZSULRULW\ &6 '0$B&6(/5 069 308/1680 DocID024597 Rev 1 RM0351 Direct memory access controller (DMA) Figure 26. DMA2 request mapping 3HULSKHUDOUHTXHVWVLJQDOV 6$,B$8$57B7;63,B5; 6:30,B5;7,0B&+7,0B75,* 7,0B&20$(6B,17,0B&+7,0B83 6:WULJJHU 0(00(0ELW 6$,B%8$57B5;63,B7; 6:30,B7;7,0B&+7,0B83 $(6B2877,0B&+7,0B75,* 7,0B&20 6:WULJJHU 0(00(0ELW $'&6$,B$8$57B7;63,B5; $(6B287 6:WULJJHU 0(00(0ELW $'&6$,B%7,0B83'$&63,B7; 7,0B&+6'00& 6:WULJJHU 0(00(0ELW $'&8$57B5;7,0B83'$& 7,0B&+$(6B,16'00& 6:WULJJHU 0(00(0ELW 6$,B$86$57B7;/38$57B7; ,&B5;7,0B&+ 6:WULJJHU 0(00(0ELW 6$,B%86$57B5;48$'63, /38$57B5;,&B7;7,0B&+ '0$FKDQQHO &KDQQHO '0$B5(4 )L[HGKDUGZDUHSULRULW\ +LJKSULRULW\ &6 &KDQQHO '0$B5(4 &6 &KDQQHO '0$B5(4 &6 &KDQQHO '0$B5(4 ,QWHUQDO'0$ UHTXHVW &6 &KDQQHO '0$B5(4 &6 &KDQQHO '0$B5(4 &6 &KDQQHO '0$B5(4 /RZSULRULW\ 6:WULJJHU 0(00(0ELW &6 '0$B&6(/5 069 DocID024597 Rev 1 309/1680 323 Direct memory access controller (DMA) RM0351 Table 38. Summary of the DMA1 requests for each channel Request. number Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 0 ADC1 ADC2 ADC3 DFSDM0 DFSDM1 DFSDM2 DFSDM3 1 - SPI1_RX SPI1_TX SPI2_RX SPI2_TX SAI2_A SAI2_B 2 - 3 - I2C3_TX I2C3_RX I2C2_TX I2C2_RX I2C1_TX I2C1_RX 4 TIM2_CH3 TIM2_UP TIM16_CH1 TIM16_UP - TIM2_CH1 TIM16_CH1 TIM16_UP TIM2_CH2 TIM2_CH4 5 TIM17_CH1 TIM17_UP TIM3_CH3 TIM3_CH4 TIM3_UP TIM7_UP. DAC2 QUADSPI TIM3_CH1 TIM3_TRIG TIM17_CH1 TIM17_UP 6 TIM4_CH1 - TIM6_UP DAC1 TIM4_CH2 TIM4_CH3 - TIM4_UP TIM1_CH2 TIM1_CH4 TIM1_TRIG TIM1_COM TIM15_CH1 TIM15_UP TIM15_TRIG TIM15_COM TIM1_UP TIM1_CH3 7 310/1680 - USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX TIM1_CH1 DocID024597 Rev 1 RM0351 Direct memory access controller (DMA) Table 39. Summary of the DMA2 requests for each channel Request. number Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 0 - - ADC1 ADC2 ADC3 - - 1 SAI1_A SAI1_B SAI2_A SAI2_B - SAI1_A SAI1_B 2 UART5_TX UART5_RX UART4_TX - UART4_RX 3 SPI3_RX SPI3_TX - TIM6_UP DAC1 TIM7_UP DAC2 4 SWPMI_RX SWPMI_TX SPI1_RX SPI1_TX - 5 TIM5_CH4 TIM5_TRIG TIM5_COM TIM5_CH3 TIM5_UP - TIM5_CH2 TIM5_CH1 I2C1_RX I2C1_TX 6 AES_IN AES_OUT AES_OUT - AES_IN - - 7 TIM8_CH3 TIM8_UP TIM8_CH4 TIM8_TRIG TIM8_COM - SDMMC1 SDMMC1 TIM8_CH1 TIM8_CH2 DocID024597 Rev 1 USART1_TX USART1_RX - QUADSPI LPUART_TX LPUART_RX 311/1680 323 Direct memory access controller (DMA) 11.5 RM0351 DMA registers Refer to Section 1.1 on page 61 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32bit). 11.5.1 DMA interrupt status register (DMA_ISR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. TEIF7 HTIF7 TCIF7 GIF7 TEIF6 HTIF6 TCIF6 GIF6 TEIF5 HTIF5 TCIF5 GIF5 r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1 r r r r r r r r r r r r r r r r Bits 31:28 Reserved, must be kept at reset value. Bits 27, 23, 19, 15, TEIFx: Channel x transfer error flag (x = 1..7) 11, 7, 3 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel x 1: A transfer error (TE) occurred on channel x Bits 26, 22, 18, 14, HTIFx: Channel x half transfer flag (x = 1..7) 10, 6, 2 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel x 1: A half transfer (HT) event occurred on channel x Bits 25, 21, 17, 13, TCIFx: Channel x transfer complete flag (x = 1..7) 9, 5, 1 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel x 1: A transfer complete (TC) event occurred on channel x Bits 24, 20, 16, 12, GIFx: Channel x global interrupt flag (x = 1..7) 8, 4, 0 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel x 1: A TE, HT or TC event occurred on channel x 312/1680 DocID024597 Rev 1 RM0351 Direct memory access controller (DMA) 11.5.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 CHTIF CTCIF7 7 23 22 21 20 19 18 17 16 Res. Res. Res. Res. CTEIF 7 w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTEIF 4 CHTIF 4 CTCIF 4 CGIF4 CTEIF 3 w w w w w CHTIF CTCIF3 3 w w CGIF7 CGIF3 w CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF2 CHTIF2 CTCIF2 CGIF2 w w w w CTEIF5 CHTIF5 CTCIF5 CTEIF1 CHTIF1 CTCIF1 w w w CGIF5 CGIF1 w Bits 31:28 Reserved, must be kept at reset value. Bits 27, 23, 19, 15, CTEIFx: Channel x transfer error clear (x = 1..7) 11, 7, 3 This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register Bits 26, 22, 18, 14, CHTIFx: Channel x half transfer clear (x = 1..7) 10, 6, 2 This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register Bits 25, 21, 17, 13, CTCIFx: Channel x transfer complete clear (x = 1..7) 9, 5, 1 This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register Bits 24, 20, 16, 12, CGIFx: Channel x global interrupt clear (x = 1..7) 8, 4, 0 This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register DocID024597 Rev 1 313/1680 323 Direct memory access controller (DMA) 11.5.3 RM0351 DMA channel x configuration register (DMA_CCRx) (x = 1..7 , where x = channel number) Address offset: 0x08 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. MEM2 MEM MINC PINC CIRC DIR TEIE HTIE TCIE EN rw rw rw rw rw rw rw rw rw PL[1:0] rw rw MSIZE[1:0] PSIZE[1:0] rw rw rw rw Bits 31:15 Reserved, must be kept at reset value. Bit 14 MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled Bits 13:12 PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high Bits 11:10 MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits 11: Reserved Bits 9:8 PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits 11: Reserved Bit 7 MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled Bit 6 PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled 314/1680 DocID024597 Rev 1 RM0351 Direct memory access controller (DMA) Bit 5 CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled Bit 4 DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory Bit 3 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled Bit 2 HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled Bit 1 TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled Bit 0 EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled DocID024597 Rev 1 315/1680 323 Direct memory access controller (DMA) 11.5.4 RM0351 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number) Address offset: 0x0C + 0d20 × (channel number – 1) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw NDT[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not. 11.5.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number) Address offset: 0x10 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 This register must not be written when the channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PA [31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw PA [15:0] rw Bits 31:0 PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address. 316/1680 DocID024597 Rev 1 RM0351 Direct memory access controller (DMA) 11.5.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number) Address offset: 0x14 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 This register must not be written when the channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MA [31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw MA [15:0] rw Bits 31:0 MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address. DocID024597 Rev 1 317/1680 323 Direct memory access controller (DMA) 11.5.7 RM0351 DMA1 channel selection register (DMA1_CSELR) Address offset: 0xA8 (with respect to DMA1 base address) Reset value: 0x0000 0000 This register is used to manage the mapping of DMA channels (see Figure 25). 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 27 rw rw 25 24 23 22 C7S [3:0] 20 19 18 16 rw rw rw rw rw rw rw rw rw rw rw 10 9 8 7 6 5 4 3 2 1 0 rw rw C2S [3:0] rw rw rw rw rw C1S [3:0] rw rw rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 C7S[3:0]: DMA channel 7 selection 0000: Channel 7 mapped on DFSDM3 0001: Channel 7 mapped on SAI2_B 0010: Channel 7 mapped on USART2_TX 0011: Channel 7 mapped on I2C1_RX 0100: Channel 7 mapped on TIM2_CH2/TIM2_CH4 0101: Channel 7 mapped on TIM17_CH1/TIM17_UP 0110: Channel 7 mapped on TIM4_UP 0111: Channel 7 mapped on TIM1_CH3 Bits 23:20 C6S[3:0]: DMA channel 6 selection 0000: Channel 6 mapped on DFSDM2 0001: Channel 6 mapped on SAI2_A 0010: Channel 6 mapped on USART2_RX 0011: Channel 6 mapped on I2C1_TX 0100: Channel 6 mapped on TIM16_CH1/TIM16_UP 0101: Channel 6 mapped on TIM3_CH1/TIM3_TRIG 0110: Reserved 0111: Channel 6 mapped on TIM1_UP others: Reserved Bits 19:16 C5S[3:0]: DMA channel 5 selection 0000: Channel 5 mapped on DFSDM1 0001: Channel 5 mapped on SPI2_TX 0010: Channel 5 mapped on USART1_RX 0011: Channel 5 mapped on I2C2_RX 0100: Channel 5 mapped on TIM2_CH1 0101: Channel 5 mapped on QUADSPI 0110: Channel 5 mapped on TIM4_CH3 0111: Channel 5 mapped on TIM15_CH1/TIM15_UP/TIM15_TRIG/TIM15_COM others: Reserved 318/1680 17 C5S [3:0] 11 C3S [3:0] rw 21 C6S [3:0] rw C4S [3:0] rw 26 DocID024597 Rev 1 rw rw RM0351 Direct memory access controller (DMA) Bits 15:12 C4S[3:0]: DMA channel 4 selection 0000: Channel 4 mapped on DFSDM0 0001: Channel 4 mapped on SPI2_RX 0010: Channel 4 mapped on USART1_TX 0011: Channel 4 mapped on I2C2_TX 0100: Reserved 0101: Channel 4 mapped on TIM7_UP/DAC2 0110: Channel 4 mapped on TIM4_CH2 0111: Channel 4 mapped on TIM1_CH4/TIM1_TRIG/TIM1_COM others: Reserved Bits 11:8 C3S[3:0]: DMA channel 3 selection 0000: Channel 3 mapped on ADC3 0001: Channel 3 mapped on SPI1_TX 0010: Channel 3 mapped on USART3_RX 0011: Channel 3 mapped on I2C3_RX 0100: Channel 3 mapped on TIM16_CH1/TIM16_UP 0101: Channel 3 mapped on TIM3_CH4/TIM3_UP 0110: Channel 3 mapped on TIM6_UP/DAC1 0111: Channel 3 mapped on TIM1_CH2 others: Reserved Bits 7:4 C2S[3:0]: DMA channel 2 selection 0000: Channel 2 mapped on ADC2 0001: Channel 2 mapped on SPI1_RX 0010: Channel 2 mapped on USART3_TX 0011: Channel 2 mapped on I2C3_TX 0100: Channel 2 mapped on TIM2_UP 0101: Channel 2 mapped on TIM3_CH3 0110: Reserved 0111: Channel 2 mapped on TIM1_CH1 others: Reserved Bits 3:0 C1S[3:0]: DMA channel 1 selection 0000: Channel 1 mapped on ADC1 0001: Reserved 0010: Reserved 0011: Reserved 0100: Channel 1 mapped on TIM2_CH3 0101: Channel 1 mapped on TIM17_CH1/TIM17_UP 0110: Channel 1 mapped on TIM4_CH1 0111: Reserved others: Reserved DocID024597 Rev 1 319/1680 323 Direct memory access controller (DMA) 11.5.8 RM0351 DMA2 channel selection register (DMA2_CSELR) Address offset: 0xA8 (with respect to DMA2 base address) Reset value: 0x0000 0000 This register is used to manage the mapping of DMA channels (see Figure 26). 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 27 rw rw 25 24 23 22 C7S [3:0] 19 18 17 16 C5S [3:0] rw rw rw rw rw rw rw rw rw rw rw 10 9 8 7 6 5 4 3 2 1 0 rw rw C2S [3:0] rw rw rw rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 C7S[3:0]: DMA channel 7 selection 0000: Reserved 0001: Channel 7 mapped on SAI1_B 0010: Channel 7 mapped on USART1_RX 0011: Channel 7 mapped on QUADSPI 0100: Channel 7 mapped on LPUART_RX 0101: Channel 7 mapped on I2C1_TX 0110: Reserved 0111: Channel 7 mapped on TIM8_CH2 others: Reserved Bits 23:20 C6S[3:0]: DMA channel 6 selection 0000: Reserved 0001: Channel 6 mapped on SAI1_A 0010: Channel 6 mapped on USART1_TX 0011: Reserved 0100: Channel 6 mapped on LPUART_TX 0101: Channel 6 mapped on I2C1_RX 0110: Reserved 0111: Channel 6 mapped on TIM8_CH1 others: Reserved Bits 19:16 C5S[3:0]: DMA channel 5 selection 0000: Channel 5 mapped on ADC3 0001: Reserved 0010: Channel 5 mapped on UART4_RX 0011: Channel 5 mapped on TIM7_UP/DAC2 0100: Reserved 0101: Channel 5 mapped on TIM5_CH1 0110: Channel 5 mapped on AES_IN 0111: Channel 5 mapped on SDMMC1 others: Reserved 320/1680 20 11 C3S [3:0] rw 21 C6S [3:0] rw C4S [3:0] rw 26 DocID024597 Rev 1 rw C1S [3:0] rw rw rw rw rw RM0351 Direct memory access controller (DMA) Bits 15:12 C4S[3:0]: DMA channel 4 selection 0000: Channel 4 mapped on ADC2 0001: Channel 4 mapped on SAI2_B 0010: Reserved 0011: Channel 4 mapped on TIM6_UP/DAC1 0100: Channel 4 mapped on SPI1_TX 0101: Channel 4 mapped on TIM5_CH2 0110: Reserved 0111: Channel 4 mapped on SDMMC1 others: Reserved Bits 11:8 C3S[3:0]: DMA channel 3 selection 0000: Channel 3 mapped on ADC1 0001: Channel 3 mapped on SAI2_A 0010: Channel 3 mapped on UART4_TX 0011: Reserved 0100: Channel 3 mapped on SPI1_RX 0101: Reserved 0110: Channel 3 mapped on AES_OUT 0111: Reserved others: Reserved Bits 7:4 C2S[3:0]: DMA channel 2 selection 0000: Reserved 0001: Channel 2 mapped on SAI1_B 0010: Channel 2 mapped on UART5_RX 0011: Channel 2 mapped on SPI3_TX 0100: Channel 2 mapped on SWPMI1_TX 0101: Channel 2 mapped on TIM5_CH3/TIM5_UP 0110: Channel 2 mapped on AES_OUT 0111: Channel 2 mapped on TIM8_CH4/TIM8_TRIG/TIM8_COM others: Reserved Bits 3:0 C1S[3:0]: DMA channel 1 selection 0000: Reserved 0001: Channel 1 mapped on SAI1_A 0010: Channel 1 mapped on UART5_TX 0011: Channel 1 mapped on SPI3_RX 0100: Channel 1 mapped on SWPMI1_RX 0101: Channel 1 mapped on TIM5_CH4/TIM5_TRIG/TIM5_COM 0110: Channel 1 mapped on AES_IN 0111: Channel 1 mapped on TIM8_CH3/TIM8_UP others: Reserved DocID024597 Rev 1 321/1680 323 0x48 DMA_CNDTR4 322/1680 0 0 0 DMA_CPAR3 DMA_CMAR3 0 0 Reset value 0 Reset value 0 0 Reset value DocID024597 Rev 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 PL [1:0] 0 0 PA[31:0] MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL [1:0] 0 NDT[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE 0 TCIE 0 HTIE 0 TEIE HTIE 0 TEIE NDT[15:0] DIR 0 0 EN MA[31:0] 0 TCIE PA[31:0] 0 HTIE 0 0 PL [1:0] DIR GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1 0 0 0 0 0 0 0 0 0 0 CHTIF7 CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 0 0 0 0 0 0 0 0 0 0 0 CHTIF3 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1 0 0 0 0 0 0 0 0 MINC PSIZE [1:0] MSIZE [1:0] CTEIF3 0 0 PINC CIRC DIR TEIE HTIE TCIE EN 0 PINC TCIF3 0 0 CIRC HTIF3 0 0 0 TEIE 0 0 DIR 0 0 0 PINC 0 CIRC GIF4 TEIF3 0 0 PINC MA[31:0] 0 MINC TCIF4 0 0 MINC HTIF4 0 0 CIRC Reset value MINC Reset value PL [1:0] PSIZE [1:0] GIF5 TEIF4 0 0 PSIZE [1:0] TCIF5 0 0 MSIZE [1:0] HTIF5 0 CGIF4 GIF6 TEIF5 0 CTCIF4 TCIF6 0 CHTIF4 HTIF6 0 MEM2MEM GIF7 TEIF6 0 CTEIF4 TCIF7 0 Res. HTIF7 0 0 MSIZE [1:0] 0 MEM2MEM Reset value MEM2MEM PA[31:0] Res. 0 Res. TEIF7 Res. Res. Res. Res. 0 CTEIF7 Res. Res. Res. Res. 0 CGIF5 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 PSIZE [1:0] 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 MSIZE [1:0] 0 0 MEM2MEM DMA_CMAR2 Res. Reset value Res. DMA_CPAR2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CMAR1 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CPAR1 Res. 0 0 0 Res. 0 0 Res. 0 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 Res. 0 0 0 0 Res. 0 0 0 0 Res. 0 0 0 0 Res. 0 0 0 Res. 0 0 0 0 0 Res. DMA_CCR4 0 0 0 0 Res. 0x44 0 0 0 0 Res. Reset value 0 0 0 Res. Reset value 0 0 0 0 Res. DMA_CNDTR3 0 0 0 Res. DMA_CCR3 0 0 0 Res. 0x30 0 0 0 Res. Reset value 0 0 Res. Reset value Res. Reset value Res. 0x3C DMA_CNDTR2 Res. Reset value Res. 0x38 DMA_CCR2 Res. 0x1C 0 0 Res. 0x34 Reset value 0 Res. 0x28 Reset value Res. 0x24 DMA_CNDTR1 Res. 0x20 DMA_CCR1 Res. 0x08 Res. 0x14 DMA_IFCR Res. 0x04 Res. 0x10 DMA_ISR Res. 0x00 Res. 0x0C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. 11.5.9 Res. Direct memory access controller (DMA) RM0351 DMA register map The following table gives the DMA register map and the reset values. Table 40. DMA register map and reset values 0 0 0 0 0 0 0 NDT[15:0] 0 0 0 0 0 0 0 NDT[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0351 Direct memory access controller (DMA) 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR4 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x08C PINC CIRC DIR TEIE HTIE TCIE EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIRC DIR TEIE HTIE TCIE EN PSIZE [1:0] 0 PINC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM2MEM MINC 0 0 0 PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR6 Reset value 0 Res. Reset value 0 NDT[15:0] 0 DMA_CPAR6 PL [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CNDTR6 0 0 MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value CIRC DIR TEIE HTIE TCIE EN PSIZE [1:0] 0 PINC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR7 Reset value 0 NDT[15:0] 0 DMA_CPAR7 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CNDTR7 0 PL [1:0] MSIZE [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CCR7 Res. Reserved 0 0 MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value Res. Res. DMA_CSELR Res. Reserved Res. 0x090 0x0A8 PSIZE [1:0] 0 0 Reset value 0x088 0 0 Reset value 0x084 0 0 MSIZE [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CCR6 0x07C 0x080 0 Reserved Res. 0x078 0 MA[31:0] Reset value 0x074 0 0 Reset value 0x070 0 MINC 0 0x068 0x06C 0 MEM2MEM 0 DMA_CMAR5 Reset value 0 NDT[15:0] 0 Res. 0x64 Reset value 0 PA[31:0] Res. 0x60 0 Res. Reset value DMA_CPAR5 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CNDTR5 Res. 0x5C 0 Res. Reset value PL [1:0] MSIZE [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CCR5 Res. Reserved Res. 0x54 0x58 0 MINC 0 Res. PA[31:0] 0 MEM2MEM Reset value Res. 0x50 DMA_CPAR4 Res. 0x4C Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 40. DMA register map and reset values (continued) C7S[3:0] 0 0 0 C6S[3:0] 0 0 0 0 C5S[3:0] 0 0 0 0 C4S[3:0] 0 0 C3S[3:0] 0 0 C2S[3:0] 0 0 C1S[3:0] 0 0 0 Refer to Section 2.2.2 on page 68 for the register boundary addresses. DocID024597 Rev 1 323/1680 323 Nested vectored interrupt controller (NVIC) 12 Nested vectored interrupt controller (NVIC) 12.1 NVIC main features RM0351 • 82 maskable interrupt channels (not including the sixteen Cortex®-M4 with FPU interrupt lines) • 16 programmable priority levels (4 bits of interrupt priority are used) • Low-latency exception and interrupt handling • Power management control • Implementation of System Control Registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to the PM0214 programming manual for CortexTM-M4 products. 12.2 SysTick calibration value register The SysTick calibration value is set to 0x100270F, which gives a reference time base of 1 ms with the SysTick clock set to 10 MHz (max fHCLK/8). 324/1680 DocID024597 Rev 1 RM0351 Nested vectored interrupt controller (NVIC) 12.3 Interrupt and exception vectors Position Priority Table 41. STM32L4x6 vector table Type of priority - - - - -3 fixed - -2 - Acronym - Description Address Reserved 0x0000 0000 Reset Reset 0x0000 0004 fixed NMI Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector. 0x0000 0008 -1 fixed HardFault All classes of fault 0x0000 000C - 0 settable MemManage Memory management 0x0000 0010 - 1 settable BusFault Pre-fetch fault, memory access fault 0x0000 0014 - 2 settable UsageFault Undefined instruction or illegal state 0x0000 0018 - - - - 3 settable SVCall System service call via SWI instruction 0x0000 002C - 4 settable Debug Monitor 0x0000 0030 - - - Reserved 0x0000 0034 - 5 settable PendSV Pendable request for system service 0x0000 0038 - 6 settable SysTick System tick timer 0x0000 003C 0 7 settable WWDG Window Watchdog interrupt 0x0000 0040 1 8 settable PVD_PVM PVD/PVM1/PVM2/PVM3/PVM4 through EXTI lines 16/35/36/37/38 interrupts 0x0000 0044 2 9 settable RTC_TAMP_STAMP RTC Tamper or TimeStamp /CSS on LSE /CSS_LSE through EXTI line 19 interrupts 3 10 settable RTC_WKUP RTC Wakeup timer through EXTI line 20 interrupt 0x0000 004C 4 11 settable FLASH Flash global interrupt 0x0000 0050 5 12 settable RCC RCC global interrupt 0x0000 005C 6 13 settable EXTI0 EXTI Line0 interrupt 0x0000 005C 7 14 settable EXTI1 EXTI Line1 interrupt 0x0000 005C 8 15 settable EXTI2 EXTI Line2 interrupt 0x0000 0060 9 16 settable EXTI3 EXTI Line3 interrupt 0x0000 0064 10 17 settable EXTI4 EXTI Line4 interrupt 0x0000 0068 11 18 settable DMA1_CH1 DMA1 channel 1 interrupt 0x0000 006C 12 19 settable DMA1_CH2 DMA1 channel 2 interrupt 0x0000 0070 13 20 settable DMA1_CH3 DMA1 channel 3 interrupt 0x0000 0074 - - Reserved DocID024597 Rev 1 0x0000 001C 0x0000 0028 0x0000 0048 325/1680 341 Nested vectored interrupt controller (NVIC) RM0351 Position Priority Table 41. STM32L4x6 vector table (continued) Type of priority 14 21 settable DMA1_CH4 DMA1 channel 4 interrupt 0x0000 0078 15 22 settable DMA1_CH5 DMA1 channel 5 interrupt 0x0000 007C 16 23 settable DMA1_CH6 DMA1 channel 6 interrupt 0x0000 0080 17 24 settable DMA1_CH7 DMA1 channel 7 interrupt 0x0000 0084 18 25 settable ADC1_2 ADC1 and ADC2 global interrupt 0x0000 0088 19 26 settable CAN1_TX CAN1_TX interrupts 0x0000 008C 20 27 settable CAN1_RX0 CAN1_RX0 interrupts 0x0000 0090 21 28 settable CAN1_RX1 CAN1_RX1 interrupt 0x0000 0094 22 29 settable CAN1_SCE CAN1_SCE interrupt 0x0000 0098 23 30 settable EXTI9_5 EXTI Line[9:5] interrupts 0x0000 009C 24 31 settable TIM1_BRK/TIM15 TIM1 Break/TIM15 global interrupts 0x0000 00A0 25 32 settable TIM1_UP/TIM16 TIM1 Update/TIM16 global interrupts 0x0000 00A4 26 33 settable TIM1_TRG_COM /TIM17 TIM1 trigger and commutation/TIM17 interrupts 0x0000 00A8 27 34 settable TIM1_CC TIM1 capture compare interrupt 0x0000 00AC 28 35 settable TIM2 TIM2 global interrupt 0x0000 00B0 29 36 settable TIM3 TIM3 global interrupt 0x0000 00B4 30 37 settable TIM4 TIM4 global interrupt 0x0000 00B8 31 38 settable I2C1_EV I2C1 event interrupt 0x0000 00BC 32 39 settable I2C1_ER I2C1 error interrupt 0x0000 00C0 33 40 settable I2C2_EV I2C2 event interrupt 0x0000 00C4 34 41 settable I2C2_ER I2C2 error interrupt 0x0000 00C8 35 42 settable SPI1 SPI1 global interrupt 0x0000 00CC 36 43 settable SPI2 SPI2 global interrupt 0x0000 00D0 37 44 settable USART1 USART1 global interrupt 0x0000 00D4 38 45 settable USART2 USART2 global interrupt 0x0000 00D8 39 46 settable USART3 USART3 global interrupt 0x0000 00DC 40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000 00E0 41 48 settable RTC_ALARM RTC alarms through EXTI line 18 interrupts 0x0000 00E4 42 49 settable DFSDM3 DFSDM3 global interrupt 0x0000 00E8 43 50 settable TIM8_BRK TIM8 Break interrupt 0x0000 00EC 44 51 settable TIM8_UP TIM8 Update interrupt 0x0000 00F0 45 52 settable TIM8_TRG_COM TIM8 trigger and commutation interrupt 0x0000 00F4 326/1680 Acronym Description DocID024597 Rev 1 Address RM0351 Nested vectored interrupt controller (NVIC) Position Priority Table 41. STM32L4x6 vector table (continued) Type of priority 46 53 settable TIM1_CC TIM8 capture compare interrupt 0x0000 00F8 47 54 settable ADC3 ADC3 global interrupt 0x0000 00FC 48 55 settable FMC FMC global interrupt 0x0000 0100 49 56 settable SDMMC1 SDMMC1 global interrupt 0x0000 0104 50 57 settable TIM5 TIM5 global interrupt 0x0000 0108 51 58 settable SPI3 SPI3 global interrupt 0x0000 010C 52 59 settable UART4 UART4 global interrupt 0x0000 0110 53 60 settable UART5 UART5 global interrupt 0x0000 0114 54 61 settable TIM6_DACUNDER TIM6 global and DAC12 underrun interrupts 0x0000 0118 55 62 settable TIM7 TIM7 global interrupt 0x0000 011C 56 63 settable DMA2_CH1 DMA2 channel 1 interrupt 0x0000 0120 57 64 settable DMA2_CH2 DMA2 channel 2 interrupt 0x0000 0124 58 65 settable DMA2_CH3 DMA2 channel 3 interrupt 0x0000 0128 59 66 settable DMA2_CH4 DMA2 channel 4 interrupt 0x0000 012C 60 67 settable DMA2_CH5 DMA2 channel 5 interrupt 0x0000 0130 61 68 settable DFSDM0 DFSDM0 global interrupt 0x0000 0134 62 69 settable DFSDM1 DFSDM1 global interrupt 0x0000 0138 63 70 settable DFSDM2 DFSDM2 global interrupt 0x0000 013C 64 71 settable COMP COMP1/COMP2 through EXTI lines 21/22 interrupts 0x0000 0140 65 72 settable LPTIM1 LPTIM1 global interrupt 0x0000 0144 66 73 settable LPTIM2 LPTIM2 global interrupt 0x0000 0148 67 74 settable OTG_FS OTG_FS global interrupt 0x0000 014C 68 75 settable DMA2_CH6 DMA2 channel 6 interrupt 0x0000 0150 69 76 settable DMA2_CH7 DMA2 channel 7 interrupt 0x0000 0154 70 77 settable LPUART1 LPUART1 global interrupt 0x0000 0158 71 78 settable QUADSPI QUADSPI global interrupt 0x0000 015C 72 79 settable I2C3_EV I2C3 event interrupt 0x0000 0160 73 79 settable I2C3_ER I2C3 error interrupt 0x0000 0164 74 80 settable SAI1 SAI1 global interrupt 0x0000 0168 75 74 settable SAI2 SAI2 global interrupt 0x0000 016C 76 75 settable SWPMI1 SWPMI1 global interrupt 0x0000 0170 Acronym Description DocID024597 Rev 1 Address 327/1680 341 Nested vectored interrupt controller (NVIC) RM0351 Position Priority Table 41. STM32L4x6 vector table (continued) Type of priority 77 76 settable TSC TSC global interrupt 0x0000 0174 78 77 settable LCD LCD global interrupt 0x0000 0178 79 78 settable AES AES global interrupt 0x0000 017C 80 79 settable RNG RNG global interrupt 0x0000 0180 81 88 settable FPU Floating point interrupt 0x0000 0184 328/1680 Acronym Description DocID024597 Rev 1 Address RM0351 Extended interrupts and events controller (EXTI) 13 Extended interrupts and events controller (EXTI) 13.1 Introduction The EXTI main features are as follows: • 13.2 Generation of up to 40 event/interrupt requests – 26 configurable lines – 14 direct lines • Independent mask on each event/interrupt line • Configurable rising or falling edge (configurable lines only) • Dedicated status bit (configurable lines only) • Emulation of event/interrupt requests (configurable lines only) EXTI main features The extended interrupts and events controller (EXTI) manages the external and internal asynchronous events/interrupts and generates the event request to the CPU/Interrupt Controller and a wake-up request to the Power Controller. The EXTI allows the management of up to 40 event lines which can wake up from the Stop 1 mode. Not all events can wake up from the Stop 2 mode (refer to Table 42: EXTI lines connections). The lines are either configurable or direct: • The lines are configurable: the active edge can be chosen independently, and a status flag indicates the source of the interrupt. The configurable lines are used by the I/Os external interrupts, and by few peripherals. • The lines are direct: they are used by some peripherals to generate a wakeup from Stop event or interrupt. The status flag is provided by the peripheral. Each line can be masked independently for an interrupt or an event generation. This controller also allows to emulate events or interrupts by software, multiplexed with the corresponding hardware event line, by writing to a dedicated register. 13.3 EXTI functional description For the configurable interrupt lines, the interrupt line should be configured and enabled in order to generate an interrupt. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register. When the selected edge occurs on the interrupt line, an interrupt request is generated. The pending bit corresponding to the interrupt line is also set. This request is cleared by writing a ‘1’ in the pending register. For the direct interrupt lines, the interrupt is enabled by default in the interrupt mask register and there is no corresponding pending bit in the pending register. To generate an event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’ to the corresponding bit in the event mask register. When the DocID024597 Rev 1 329/1680 341 Extended interrupts and events controller (EXTI) RM0351 selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set. For the configurable lines, an interrupt/event request can also be generated by software by writing a ‘1’ in the software interrupt/event register. Note: The interrupts or events associated to the direct lines are triggered only when the system is in Stop mode. If the system is still running, no interrupt/event is generated by the EXTI. 13.3.1 EXTI block diagram The extended interrupt/event block diagram is shown on Figure 27. Figure 27. Configurable interrupt/event block diagram $3%EXV 3&/. 3HULSKHUDOLQWHUIDFH )DOOLQJ WULJJHU VHOHFWLRQ UHJLVWHU 5LVLQJ WULJJHU VHOHFWLRQ UHJLVWHU 6RIWZDUH LQWHUUXSW HYHQW UHJLVWHU (YHQW PDVN UHJLVWHU ,QWHUUXSW PDVN UHJLVWHU 3HQGLQJ UHTXHVW UHJLVWHU ,QWHUUXSWV &RQILJXUDEOH HYHQWV (GJHGHWHFW FLUFXLW (YHQWV 6WRSPRGH 'LUHFWHYHQWV 3JTJOH FEHF EFUFDU :DNHXS 069 13.3.2 Wakeup event management The STM32L4x6 is able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated either by: 330/1680 • enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the CortexTM-M4 System Control register. When the MCU resumes from WFE, the EXTI peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared • or by configuring an EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set. DocID024597 Rev 1 RM0351 13.3.3 Extended interrupts and events controller (EXTI) Peripherals asynchronous Interrupts Some peripherals are able to generate events when the system is in run mode and also when the system is in Stop mode, allowing to wake up the system from Stop mode. To accomplish this, the peripheral generates both a synchronized (to the system clock, e.g. APB clock) and an asynchronous version of the event. This asynchronous event is connected to an EXTI direct line. Note: Few peripherals with wakeup from Stop capability are connected to an EXTI configurable line. In this case, the EXTI configuration is necessary to allow the wakeup from Stop mode. 13.3.4 Hardware interrupt selection To configure a line as an interrupt source, use the following procedure: 1. Configure the corresponding mask bit in the EXTI_IMR register. 2. Configure the Trigger Selection bits of the Interrupt line (EXTI_RTSR and EXTI_FTSR). 3. Configure the enable and mask bits that control the NVIC IRQ channel mapped to the EXTI so that an interrupt coming from one of the EXTI lines can be correctly acknowledged. Note: The direct lines do not require any EXTI configuration. 13.3.5 Hardware event selection To configure a line as an event source, use the following procedure: 13.3.6 1. Configure the corresponding mask bit in the EXTI_EMR register. 2. Configure the Trigger Selection bits of the Event line (EXTI_RTSR and EXTI_FTSR). Software interrupt/event selection Any of the configurable lines can be configured as a software interrupt/event line. The procedure to generate a software interrupt is as follows: 13.4 1. Configure the corresponding mask bit (EXTI_IMR, EXTI_EMR). 2. Set the required bit of the software interrupt register (EXTI_SWIER). EXTI interrupt/event line mapping In the STM32L4x6, 40 interrupt/event lines are available. The GPIOs are connected to 16 configurable interrupt/event lines (see Figure 28). DocID024597 Rev 1 331/1680 341 Extended interrupts and events controller (EXTI) RM0351 Figure 28. External interrupt/event GPIO mapping %84);= BITS IN THE 393#&'?%84)#2 REGISTER 0! 0" 0# 0$ 0% 0& %84) %84);= BITS IN THE 393#&'?%84)#2 REGISTER 0! 0" 0# 0$ 0% 0& %84) %84);= BITS IN THE 393#&'?%84)#2 REGISTER 0! 0" 0# 0$ 0% 0& %84) -36 The 40 lines are connected as shown in Table 42: EXTI lines connections. Table 42. EXTI lines connections 332/1680 EXTI line Line source(1) Line type 0-15 GPIO configurable 16 PVD configurable 17 OTG_FS wakeup event(2) direct 18 RTC alarms configurable 19 RTC tamper or timestamp or CSS_LSE configurable 20 RTC wakeup timer configurable 21 COMP1 output configurable 22 COMP2 output configurable 23 I2C1 wakeup(2) direct DocID024597 Rev 1 RM0351 Extended interrupts and events controller (EXTI) Table 42. EXTI lines connections (continued) EXTI line 24 25 26 27 28 Line source(1) Line type (2) I2C2 wakeup I2C3 wakeup USART1 direct wakeup(2) direct (2) direct wakeup(2) direct USART2 wakeup USART3 direct 29 UART4 wakeup(2) direct 30 UART5 wakeup (2) direct 31 LPUART1 wakeup direct 32 LPTIM1 direct 33 LPTIM2(2) direct 34 SWPMI1 wakeup(2) direct 35 PVM1 wakeup configurable 36 PVM2 wakeup configurable 37 PVM3 wakeup configurable 38 PVM4 wakeup configurable 39 LCD wakeup direct 1. All the lines can wake up from the Stop 1 mode. All the lines, except the ones mentioned above, can wake up from the Stop 2 mode. 2. This line source cannot wake up from the Stop 2 mode. DocID024597 Rev 1 333/1680 341 Extended interrupts and events controller (EXTI) 13.5 RM0351 EXTI registers Refer to Section 1.1 on page 61 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 13.5.1 Interrupt mask register 1 (EXTI_IMR1) Address offset: 0x00 Reset value: 0xFF82 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IM31 IM30 IM29 IM28 IM27 IM26 IM25 IM24 IM23 IM22 IM21 IM20 IM19 IM18 IM17 IM16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 IMx: Interrupt Mask on line x (x = 31 to 0) 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is not masked Note: The reset value for the direct lines (line 17, lines from 23 to 34, line 39) is set to ‘1’ in order to enable the interrupt by default. 13.5.2 Event mask register 1 (EXTI_EMR1) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EM31 EM30 EM29 EM28 EM27 EM26 EM25 EM24 EM23 EM22 EM21 EM20 EM19 EM18 EM17 EM16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EM15 EM14 EM13 EM12 EM11 EM10 EM9 EM8 EM7 EM6 EM5 EM4 EM3 EM2 EM1 EM0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 EMx: Event mask on line x (x = 31 to 0) 0: Event request from line x is masked 1: Event request from line x is not masked 334/1680 DocID024597 Rev 1 RM0351 Extended interrupts and events controller (EXTI) 13.5.3 Rising trigger selection register 1 (EXTI_RTSR1) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. RT22 RT21 RT20 RT19 RT18 Res. RT16 rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:23 Reserved, must be kept at reset value. Bits 22:18 RTx: Rising trigger event configuration bit of line x (x = 22 to 18) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line Bit 17 Reserved, must be kept at reset value. Bits 16:0 RTx: Rising trigger event configuration bit of line x (x = 16 to 0) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition. 13.5.4 Falling trigger selection register 1 (EXTI_FTSR1) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. FT22 FT21 FT20 FT19 FT18 Res. FT16 rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FT15 FT14 FT13 FT12 FT11 FT10 FT9 FT8 FT7 FT6 FT5 FT4 FT3 FT2 FT1 FT0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:23 Reserved, must be kept at reset value. DocID024597 Rev 1 335/1680 341 Extended interrupts and events controller (EXTI) RM0351 Bits 22:18 FTx: Falling trigger event configuration bit of line x (x = 22 to 18) 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line Bit 17 Reserved, must be kept at reset value. Bits 16:0 FTx: Falling trigger event configuration bit of line x (x = 16 to 0) 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a falling edge on a configurable interrupt line occurs during a write operation to the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition. 13.5.5 Software interrupt event register 1 (EXTI_SWIER1) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. SWI 22 SWI 21 SWI 20 SWI 19 SWI 18 Res. SWI 16 rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWI 15 SWI 14 SWI 13 SWI 12 SWI 11 SWI 10 SWI 9 SWI 8 SWI 7 SWI 6 SWI 5 SWI 4 SWI 3 SWI 2 SWI 1 SWI 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:23 Reserved, must be kept at reset value. Bits 22: 18 SWIx: Software interrupt on line x (x = 22 o 18) If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit in the EXTI_PR register (by writing a ‘1’ into the bit). Bit 17 Reserved, must be kept at reset value. Bits 16:0 SWIx: Software interrupt on line x (x = 16 to 0) If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a ‘1’ into the bit). 336/1680 DocID024597 Rev 1 RM0351 Extended interrupts and events controller (EXTI) 13.5.6 Pending register 1 (EXTI_PR1) Address offset: 0x14 Reset value: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. PIF22 PIF21 PIF20 PIF19 PIF18 Res. PIF16 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIF15 PIF14 PIF13 PIF12 PIF11 PIF10 PIF9 PIF8 PIF7 PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits 31:23 Reserved, must be kept at reset value. Bits 22:18 PIFx: Pending interrupt flag on line x (x = 22 to 18) 0: No trigger request occurred 1: Selected trigger request occurred This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a ‘1’ to the bit. Bit 17 Reserved, must be kept at reset value. Bits 16:0 PIFx: Pending interrupt flag on line x (x = 16 to 0) 0: No trigger request occurred 1: Selected trigger request occurred This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a ‘1’ to the bit. 13.5.7 Interrupt mask register 2 (EXTI_IMR2) Address offset: 0x20 Reset value: 0xFFFF FF87 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. IM39 IM38 IM37 IM36 IM35 IM34 IM33 IM32 rw rw rw rw rw rw rw rw Bits 31:8 Reserved, must be kept at reset value Bits 7:0 IMx: Interrupt mask on line x (x = 39 to 32) 0: Interrupt request from line x is masked 1: Interrupt request from line x is not masked Note: The reset value for the direct lines (line 17, lines from 23 to 34, line 39) is set to ‘1’ in order to enable the interrupt by default. DocID024597 Rev 1 337/1680 341 Extended interrupts and events controller (EXTI) 13.5.8 RM0351 Event mask register 2 (EXTI_EMR2) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. EM39 EM38 EM37 EM36 EM35 EM34 EM33 EM32 rw rw rw rw rw rw rw rw Bits 31:8 Reserved, must be kept at reset value Bits 7:0 EMx: Event mask on line x (x = 39 to 32) 0: Event request from line x is masked 1: Event request from line x is not masked 13.5.9 Rising trigger selection register 2 (EXTI_RTSR2) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. RT38 RT37 RT36 RT35 Res. Res. Res. rw rw rw rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:3 RTx: Rising trigger event configuration bit of line x (x = 35 to 38) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line Bits 2:0 Reserved, must be kept at reset value. Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation to the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition. 338/1680 DocID024597 Rev 1 RM0351 Extended interrupts and events controller (EXTI) 13.5.10 Falling trigger selection register 2 (EXTI_FTSR2) Address offset: 0x2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. FT38 FT37 FT36 FT35 Res. Res. Res. rw rw rw rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:3 FTx: Falling trigger event configuration bit of line x (x = 35 to 38) 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line Bits 2:0 Reserved, must be kept at reset value. Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a falling edge on a configurable interrupt line occurs during a write operation to the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition. 13.5.11 Software interrupt event register 2 (EXTI_SWIER2) Address offset: 0x30 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. SWI 38 SWI 37 SWI 36 SWI 35 Res. Res. Res. rw rw rw rw Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:8 Reserved, must be kept at reset value. Bit 7 SWIx: Software interrupt on line x (x = 35 to 38) If the interrupt is enabled on this line in EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit of EXTI_PR resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a ‘1’ to the bit). Bits 2:0 Reserved, must be kept at reset value. DocID024597 Rev 1 339/1680 341 Extended interrupts and events controller (EXTI) 13.5.12 RM0351 Pending register 2 (EXTI_PR2) Address offset: 0x34 Reset value: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. PIF38 PIF37 PIF36 PIF35 Res. Res. Res. rc_w1 rc_w1 rc_w1 rc_w1 Bits 31:8 Reserved, must be kept at reset value. Bit 7 PIFx: Pending interrupt flag on line x (x = 35 to 38) 0: No trigger request occurred 1: Selected trigger request occurred This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a ‘1’ into the bit. Bits 2:0 Reserved, must be kept at reset value. 340/1680 DocID024597 Rev 1 0x34 EXTI_PR2 DocID024597 Rev 1 EM32 PIF0 0 0 IM32 EM19 EM18 EM17 EM16 EM15 EM14 EM13 EM12 EM11 EM10 EM9 EM8 EM7 EM6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI_RTSR1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RT11 RT10 RT9 RT8 RT7 RT6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RT0 RT12 0 RT1 RT13 0 RT2 RT14 0 RT3 RT15 0 RT5 RT4 RT16 0 IM0 EM20 0 IM1 EM21 0 EM0 EM22 0 FT0 EM23 0 SWI0 EM24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. EM25 0 0 0 0 0 0 0 Res. EM26 0 IM2 EM27 0 EM1 EM28 0 FT1 EM29 0 IM3 EM30 0 EM2 EM31 Reset value EM3 EXTI_EMR1 FT2 0 IM5 IM4 IM6 0 EM5 EM4 IM7 0 FT3 FT6 IM8 0 FT5 FT4 FT7 IM9 0 SWI1 SWI6 FT8 IM11 IM10 0 SWI2 SWI7 FT9 IM12 0 SWI3 SWI8 IM13 0 SWI5 SWI4 SWI9 IM14 0 Res. PIF1 0 IM33 0 Res. FT10 IM15 0 Res. EM33 PIF2 0 Res. SWI10 FT11 IM16 0 Res. PIF3 0 IM34 PIF5 PIF4 0 IM35 PIF6 0 Res. SWI11 FT12 IM17 1 Res. EM34 PIF7 0 Res. SWI12 FT13 IM18 0 Res. PIF8 0 Res. SWI13 FT14 IM19 0 Res. EM35 0 RT35 PIF9 0 IM36 PIF10 0 Res. SWI14 FT15 IM20 0 Res. FT35 EM36 0 RT36 PIF11 0 IM37 PIF12 0 Res. SWI15 IM21 0 Res. SWI35 0 PIF35 FT36 EM37 0 RT37 PIF13 0 IM38 PIF14 0 IM39 PIF15 0 Res. FT16 IM22 0 Res. SWI36 0 PIF36 FT37 EM38 0 RT38 EM39 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. SWI16 IM23 1 RT18 IM24 1 RT19 IM25 1 RT20 IM26 1 RT21 IM27 1 Res. SWI37 Reset value PIF37 Reset value FT38 Res. Res. Res. Res. Res. Res. Res. Res. Reset value SWI38 Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value PIF38 Reset value Res. PIF16 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. FT18 0 Res. SWI18 FT19 0 Res. PIF18 0 Res. SWI19 FT20 0 Res. PIF19 0 Res. SWI20 FT21 0 Res. PIF20 0 Res. SWI21 0 Res. PIF21 0 Res. IM28 1 0 Res. Res. Res. Res. Res. IM29 1 RT22 IM30 1 0 Res. Res. Res. Res. Res. FT22 Res. Res. Res. Res. Res. Res. Res. IM31 1 0 Res. Res. Res. Res. Res. SWI22 Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 Res. Res. Res. Res. Res. PIF22 Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI_IMR1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. EXTI_SWIER2 Res. 0x30 EXTI_FTSR2 Res. 0x2C EXTI_RTSR2 Res. 0x28 EXTI_EMR2 Res. 0x24 EXTI_IMR2 Res. 0x20 EXTI_PR1 Res. 0x14 EXTI_SWIER1 Res. 0x10 EXTI_FTSR1 Res. 0x0C Res. 0x08 Res. 0x04 Res. 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. 13.5.13 Res. RM0351 Extended interrupts and events controller (EXTI) EXTI register map Table 43 gives the EXTI register map and the reset values. Table 43. Extended interrupt/event controller register map and reset values 0 1 1 1 1 0 0 0 341/1680 341 Flexible static memory controller (FSMC) 14 RM0351 Flexible static memory controller (FSMC) The Flexible static memory controller (FSMC) includes memory controllers: • The NOR/PSRAM memory controller • The NAND memory controller This memory controller is also named Flexible memory controller (FMC). 14.1 FMC main features The FMC functional block makes the interface with: synchronous and asynchronous static memories, and NAND flash memory. Its main purposes are: • to translate AHB transactions into the appropriate external device protocol • to meet the access time requirements of the external memory devices All external memories share the addresses, data and control signals with the controller. Each external device is accessed by means of a unique Chip Select. The FMC performs only one access at a time to an external device. The main features of the FMC controller are the following: • Interface with static-memory mapped devices including: – Static random access memory (SRAM) – NOR Flash memory/OneNAND Flash memory – PSRAM (4 memory banks) – NAND Flash memory with ECC hardware to check up to 8 Kbytes of data • Burst mode support for faster access to synchronous devices such as NOR Flash memory, PSRAM) • Programmable continuous clock output for asynchronous and synchronous accesses • 8-,16-bit wide data bus • Independent Chip Select control for each memory bank • Independent configuration for each memory bank • Write enable and byte lane select outputs for use with PSRAM, SRAM devices • External asynchronous wait control • Write FIFO with 16 x32-bit depth The Write FIFO is common to all memory controllers and consists of: • a Write Data FIFO which stores the AHB data to be written to the memory (up to 32 bits) plus one bit for the AHB transfer (burst or not sequential mode) • a Write Address FIFO which stores the AHB address (up to 28 bits) plus the AHB data size (up to 2 bits). When operating in burst mode, only the start address is stored except when crossing a page boundary (for PSRAM ). In this case, the AHB burst is broken into two FIFO entries. The Write FIFO can be disabled by setting the WFDIS bit in the FMC_BCR1 register At startup the FMC pins must be configured by the user application. The FMC I/O pins which are not used by the application can be used for other purposes. 342/1680 DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) The FMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up. However, the settings can be changed at any time. 14.2 Block diagram The FMC consists of the following main blocks: • The AHB interface (including the FMC configuration registers) • The NOR Flash/PSRAM/SRAM controller • The external device interface The block diagram is shown in the figure below. Figure 29. FMC block diagram )0&LQWHUUXSWVWR19,& )0&B1/ RU1$'9 )0&B&/. )URPFORFN FRQWUROOHU +&/. 125365$0 PHPRU\ FRQWUROOHU &RQILJXUDWLRQ UHJLVWHUV 1$1' PHPRU\ FRQWUROOHU 125365$0 VLJQDOV )0&B1%/>@ 125365$065$0 VKDUHGVLJQDOV )0&B$>@ )0&B'>@ 6KDUHGVLJQDOV )0&B1(>@ )0&B12( )0&B1:( )0&B1:$,7 125365$065$0 VKDUHGVLJQDOV )0&B1&( )0&B,17 1$1'VLJQDOV 069 14.3 AHB interface The AHB slave interface allows internal CPUs and other bus master peripherals to access the external memories. AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses. The FMC Chip Select (FMC_NEx) does not toggle between the consecutive accesses. DocID024597 Rev 1 343/1680 396 Flexible static memory controller (FSMC) RM0351 The FMC generates an AHB error in the following conditions: • When reading or writing to an FMC bank (Bank 1 to 4) which is not enabled. • When reading or writing to the NOR Flash bank while the FACCEN bit is reset in the FMC_BCRx register. The effect of an AHB error depends on the AHB master which has attempted the R/W access: • If the access has been attempted by the Cortex®-M4 with FPU CPU, a hard fault interrupt is generated. • If the access has been performed by a DMA controller, a DMA transfer error is generated and the corresponding DMA channel is automatically disabled. The AHB clock (HCLK) is the reference clock for the FMC. 14.3.1 Supported memories and transactions General transaction rules The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the accessed external device has a fixed data width. This may lead to inconsistent transfers. Therefore, some simple transaction rules must be followed: • AHB transaction size and memory data size are equal There is no issue in this case. • AHB transaction size is greater than the memory size: In this case, the FMC splits the AHB transaction into smaller consecutive memory accesses to meet the external data width. The FMC Chip Select (FMC_NEx) does not toggle between the consecutive accesses. • AHB transaction size is smaller than the memory size: The transfer may or not be consistent depending on the type of external device: – Accesses to devices that have the byte select feature (SRAM, ROM, PSRAM) In this case, the FMC allows read/write transactions and accesses the right data through its byte lanes NBL[1:0]. Bytes to be written are addressed by NBL[1:0]. All memory bytes are read (NBL[1:0] are driven low during read transaction) and the useless ones are discarded. – Accesses to devices that do not have the byte select feature (NOR and NAND Flash memories) This situation occurs when a byte access is requested to a 16-bit wide Flash memory. Since the device cannot be accessed in byte mode (only 16-bit words can be read/written from/to the Flash memory), Write transactions and Read transactions are allowed (the controller reads the entire 16-bit memory word and uses only the required byte). Wrap support for NOR Flash/PSRAM Wrap burst mode for synchronous memories is not supported. The memories must be configured in linear burst mode of undefined length. 344/1680 DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) Configuration registers The FMC can be configured through a set of registers. Refer to Section 14.5.6, for a detailed description of the NOR Flash/PSRAM controller registers. Refer to Section 14.6.7, for a detailed description of the NAND Flash registers. 14.4 External device address mapping From the FMC point of view, the external memory is divided into fixed-size banks of 256 Mbytes each (see Figure 30): • • Bank 1 used to address up to 4 NOR Flash memory or PSRAM devices. This bank is split into 4 NOR/PSRAM subbanks with 4 dedicated Chip Selects, as follows: – Bank 1 - NOR/PSRAM 1 – Bank 1 - NOR/PSRAM 2 – Bank 1 - NOR/PSRAM 3 – Bank 1 - NOR/PSRAM 4 Bank 3 used to address NAND Flash memory devices.The MPU memory attribute for this space must be reconfigured by software to Device For each bank the type of memory to be used can be configured by the user application through the Configuration register. Figure 30. FMC memory banks ĚĚƌĞƐƐ ĂŶŬ ϬdžϲϬϬϬϬϬϬϬ ^ƵƉƉŽƌƚĞĚŵĞŵŽƌLJƚLJƉĞ EKZͬW^ZDͬ^ZD ĂŶŬϭ ϰdžϲϰD Ϭdžϲ&&&&&&& ϬdžϳϬϬϬϬϬϬϬ ZĞƐĞƌǀĞĚ Ϭdžϳ&&&&&&& ϬdžϴϬϬϬϬϬϬϬ ĂŶŬϯ ϰdžϲϰD EE&ůĂƐŚŵĞŵŽƌLJ Ϭdžϴ&&&&&&& ϬdžϵϬϬϬϬϬϬϬ ZĞƐĞƌǀĞĚ D^ϯϰϰϳϱsϭ Ϭdžϵ&&&&&&& DocID024597 Rev 1 345/1680 396 Flexible static memory controller (FSMC) 14.4.1 RM0351 NOR/PSRAM address mapping HADDR[27:26] bits are used to select one of the four memory banks as shown in Table 44. Table 44. NOR/PSRAM bank selection HADDR[27:26](1) Selected bank 00 Bank 1 - NOR/PSRAM 1 01 Bank 1 - NOR/PSRAM 2 10 Bank 1 - NOR/PSRAM 3 11 Bank 1 - NOR/PSRAM 4 1. HADDR are internal AHB address lines that are translated to external memory. The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte address whereas the memory is addressed at word level, the address actually issued to the memory varies according to the memory data width, as shown in the following table. Table 45. NOR/PSRAM External memory address Memory width(1) Data address issued to the memory Maximum memory capacity (bits) 8-bit HADDR[25:0] 64 Mbytes x 8 = 512 Mbit 16-bit HADDR[25:1] >> 1 64 Mbytes/2 x 16 = 512 Mbit 1. In case of a 16-bit external memory width, the FMC will internally use HADDR[25:1] to generate the address for external memory FMC_A[24:0]. Whatever the external memory width, FMC_A[0] should be connected to external memory address A[0]. 14.4.2 NAND Flash memory address mapping The NAND bank is divided into memory areas as indicated in Table 46. Table 46. NAND memory mapping and timing registers Start address End address 0x8800 0000 0x8BFF FFFF 0x8000 0000 0x83FF FFFF FMC bank Bank 3 - NAND Flash Memory space Timing register Attribute FMC_PATT (0x8C) Common FMC_PMEM (0x88) For NAND Flash memory, the common and attribute memory spaces are subdivided into three sections (see in Table 47 below) located in the lower 256 Kbytes: 346/1680 • Data section (first 64 Kbytes in the common/attribute memory space) • Command section (second 64 Kbytes in the common / attribute memory space) • Address section (next 128 Kbytes in the common / attribute memory space) DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) Table 47. NAND bank selection Section name HADDR[17:16] Address range Address section 1X 0x020000-0x03FFFF Command section 01 0x010000-0x01FFFF Data section 00 0x000000-0x0FFFF The application software uses the 3 sections to access the NAND Flash memory: • To sending a command to NAND Flash memory, the software must write the command value to any memory location in the command section. • To specify the NAND Flash address that must be read or written, the software must write the address value to any memory location in the address section. Since an address can be 4 or 5 bytes long (depending on the actual memory size), several consecutive write operations to the address section are required to specify the full address. • To read or write data, the software reads or writes the data from/to any memory location in the data section. Since the NAND Flash memory automatically increments addresses, there is no need to increment the address of the data section to access consecutive memory locations. 14.5 NOR Flash/PSRAM controller The FMC generates the appropriate signal timings to drive the following types of memories: • • • Asynchronous SRAM and ROM – 8 bits – 16 bits PSRAM (Cellular RAM) – Asynchronous mode – Burst mode for synchronous accesses – Multiplexed or non-multiplexed NOR Flash memory – Asynchronous mode – Burst mode for synchronous accesses – Multiplexed or non-multiplexed The FMC outputs a unique Chip Select signal, NE[4:1], per bank. All the other signals (addresses, data and control) are shared. The FMC supports a wide range of devices through a programmable timings among which: • Programmable wait states (up to 15) • Programmable bus turnaround cycles (up to 15) • Programmable output enable and write enable delays (up to 15) • Independent read and write timings and protocol to support the widest variety of memories and timings • Programmable continuous clock (FMC_CLK) output. DocID024597 Rev 1 347/1680 396 Flexible static memory controller (FSMC) RM0351 The FMC Clock (FMC_CLK) is a submultiple of the HCLK clock. It can be delivered to the selected external device either during synchronous accesses only or during asynchronous and synchronous accesses depending on the CCKEN bit configuration in the FMC_BCR1 register: • If the CCLKEN bit is reset, the FMC generates the clock (CLK) only during synchronous accesses (Read/write transactions). • If the CCLKEN bit is set, the FMC generates a continuous clock during asynchronous and synchronous accesses. To generate the FMC_CLK continuous clock, Bank 1 must be configured in synchronous mode (see Section 14.5.6: NOR/PSRAM controller registers). Since the same clock is used for all synchronous memories, when a continuous output clock is generated and synchronous accesses are performed, the AHB data size has to be the same as the memory data width (MWID) otherwise the FMC_CLK frequency will be changed depending on AHB data transaction (refer to Section 14.5.5: Synchronous transactions for FMC_CLK divider ratio formula). The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured through dedicated registers (see Section 14.5.6: NOR/PSRAM controller registers). The programmable memory parameters include access times (see Table 48) and support for wait management (for PSRAM and NOR Flash accessed in burst mode). Table 48. Programmable NOR/PSRAM access parameters 14.5.1 Parameter Function Access mode Unit Min. Max. Address setup Duration of the address setup phase Asynchronous AHB clock cycle (HCLK) 0 15 Address hold Duration of the address hold phase Asynchronous, muxed I/Os AHB clock cycle (HCLK) 1 15 Data setup Duration of the data setup phase Asynchronous AHB clock cycle (HCLK) 1 256 Bust turn Duration of the bus turnaround phase Asynchronous and AHB clock cycle synchronous read (HCLK) / write 0 15 Clock divide ratio Number of AHB clock cycles (HCLK) to build one memory clock cycle (CLK) Synchronous AHB clock cycle (HCLK) 2 16 Data latency Number of clock cycles to issue to the memory before the first data of the burst Synchronous Memory clock cycle (CLK) 2 17 External memory interface signals Table 49, Table 50 and Table 51 list the signals that are typically used to interface with NOR Flash memory, SRAM and PSRAM. Note: 348/1680 The prefix “N” identifies the signals which are active low. DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) NOR Flash memory, non-multiplexed I/Os Table 49. Non-multiplexed I/O NOR Flash memory FMC signal name I/O Function CLK O Clock (for synchronous access) A[25:0] O Address bus D[15:0] I/O Bidirectional data bus NE[x] O Chip Select, x = 1..4 NOE O Output enable NWE O Write enable NL(=NADV) O Latch enable (this signal is called address valid, NADV, by some NOR Flash devices) NWAIT I NOR Flash wait input signal to the FMC The maximum capacity is 512 Mbits (26 address lines). NOR Flash memory, 16-bit multiplexed I/Os Table 50. 16-bit multiplexed I/O NOR Flash memory FMC signal name I/O Function CLK O Clock (for synchronous access) A[25:16] O Address bus AD[15:0] I/O 16-bit multiplexed, bidirectional address/data bus (the 16-bit address A[15:0] and data D[15:0] are multiplexed on the databus) NE[x] O Chip Select, x = 1..4 NOE O Output enable NWE O Write enable NL(=NADV) O Latch enable (this signal is called address valid, NADV, by some NOR Flash devices) NWAIT I NOR Flash wait input signal to the FMC The maximum capacity is 512 Mbits. PSRAM/SRAM, non-multiplexed I/Os Table 51. Non-multiplexed I/Os PSRAM/SRAM FMC signal name I/O Function CLK O Clock (only for PSRAM synchronous access) A[25:0] O Address bus D[15:0] I/O Data bidirectional bus NE[x] O Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM)) DocID024597 Rev 1 349/1680 396 Flexible static memory controller (FSMC) RM0351 Table 51. Non-multiplexed I/Os PSRAM/SRAM (continued) FMC signal name I/O Function NOE O Output enable NWE O Write enable NL(= NADV) O Address valid only for PSRAM input (memory signal name: NADV) NWAIT I PSRAM wait input signal to the FMC NBL[1:0] O Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable) The maximum capacity is 512 Mbits. PSRAM, 16-bit multiplexed I/Os Table 52. 16-Bit multiplexed I/O PSRAM FMC signal name I/O Function CLK O Clock (for synchronous access) A[25:16] O Address bus AD[15:0] I/O 16-bit multiplexed, bidirectional address/data bus (the 16-bit address A[15:0] and data D[15:0] are multiplexed on the databus) NE[x] O Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM)) NOE O Output enable NWE O Write enable NL(= NADV) O Address valid PSRAM input (memory signal name: NADV) NWAIT I PSRAM wait input signal to the FMC NBL[1:0] O Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable) The maximum capacity is 512 Mbits (26 address lines). 14.5.2 Supported memories and transactions Table 53 below shows an example of the supported devices, access modes and transactions when the memory data bus is 16-bit wide for NOR Flash memory, PSRAM and SRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in this example. 350/1680 DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) Table 53. NOR Flash/PSRAM: example of supported memories and transactions Device NOR Flash (muxed I/Os and nonmuxed I/Os) PSRAM (multiplexed I/Os and nonmultiplexed I/Os) SRAM and ROM Mode R/W AHB data size Memory data size Allowed/ not allowed Comments Asynchronous R 8 16 Y - Asynchronous W 8 16 N - Asynchronous R 16 16 Y - Asynchronous W 16 16 Y - Asynchronous R 32 16 Y Split into 2 FMC accesses Asynchronous W 32 16 Y Split into 2 FMC accesses Asynchronous page R - 16 N Mode is not supported Synchronous R 8 16 N - Synchronous R 16 16 Y - Synchronous R 32 16 Y - Asynchronous R 8 16 Y - Asynchronous W 8 16 Y Use of byte lanes NBL[1:0] Asynchronous R 16 16 Y - Asynchronous W 16 16 Y - Asynchronous R 32 16 Y Split into 2 FMC accesses Asynchronous W 32 16 Y Split into 2 FMC accesses Asynchronous page R - 16 N Mode is not supported Synchronous R 8 16 N - Synchronous R 16 16 Y - Synchronous R 32 16 Y - Synchronous W 8 16 Y Use of byte lanes NBL[1:0] Synchronous W 16/32 16 Y - Asynchronous R 8 / 16 16 Y - Asynchronous W 8 / 16 16 Y Use of byte lanes NBL[1:0] Asynchronous R 32 16 Y Split into 2 FMC accesses Asynchronous W 32 16 Y Split into 2 FMC accesses Use of byte lanes NBL[1:0] DocID024597 Rev 1 351/1680 396 Flexible static memory controller (FSMC) 14.5.3 RM0351 General timing rules Signals synchronization 14.5.4 • All controller output signals change on the rising edge of the internal clock (HCLK) • In synchronous mode (read or write), all output signals change on the rising edge of HCLK. Whatever the CLKDIV value, all outputs change as follows: – NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the falling edge of FMC_CLK clock. – NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising edge of FMC_CLK clock. NOR Flash/PSRAM controller asynchronous transactions Asynchronous static memories (NOR Flash, PSRAM, SRAM) 352/1680 • Signals are synchronized by the internal clock HCLK. This clock is not issued to the memory • The FMC always samples the data before de-asserting the Chip Select signal NE. This guarantees that the memory data hold timing constraint is met (minimum Chip Enable high to data transition is usually 0 ns) • If the extended mode is enabled (EXTMOD bit is set in the FMC_BCRx register), up to four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and D modes for read and write operations. For example, read operation can be performed in mode A and write in mode B. • If the extended mode is disabled (EXTMOD bit is reset in the FMC_BCRx register), the FMC can operate in Mode1 or Mode2 as follows: – Mode 1 is the default mode when SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01 in the FMC_BCRx register) – Mode 2 is the default mode when NOR memory type is selected (MTYP = 0x10 in the FMC_BCRx register). DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) Mode 1 - SRAM/PSRAM (CRAM) The next figures show the read and write transactions for the supported modes followed by the required configuration of FMC _BCRx, and FMC_BTRx/FMC_BWTRx registers. Figure 31. Mode1 read access waveforms 0HPRU\WUDQVDFWLRQ $>@ 1%/>@ 1([ 12( 1:( +LJK GDWDGULYHQ E\PHPRU\ '>@ $''6(7 +&/.F\FOHV '$7$67 +&/.F\FOHV 069 Figure 32. Mode1 write access waveforms 0HPRU\WUDQVDFWLRQ $>@ 1%/>@ 1([ 12( +&/. 1:( '>@ GDWDGULYHQE\)0& $''6(7 '$7$67 +&/.F\FOHV +&/.F\FOHV 069 DocID024597 Rev 1 353/1680 396 Flexible static memory controller (FSMC) RM0351 The one HCLK cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the DATAST value must be greater than zero (DATAST > 0). Table 54. FMC_BCRx bit fields Bit number Bit name Value to set 31-22 Reserved 21 WFDIS As needed 20 CCLKEN As needed 19 CBURSTRW 0x0 (no effect in asynchronous mode) 18:16 CPSIZE 0x0 (no effect in asynchronous mode) 15 ASYNCWAIT 14 EXTMOD 0x0 13 WAITEN 0x0 (no effect in asynchronous mode) 12 WREN 11 Reserved 0x0 10 WRAPMOD 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN Don’t care 5-4 MWID As needed 3-2 MTYP As needed, exclude 0x2 (NOR Flash memory) 1 MUXE 0x0 0 MBKEN 0x1 0x000 Set to 1 if the memory supports this feature. Otherwise keep at 0. As needed Table 55. FMC_BTRx bit fields 354/1680 Bit number Bit name Value to set 31:30 Reserved 0x0 29-28 ACCMOD Don’t care 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Duration of the second access phase (DATAST+1 HCLK cycles for write accesses, DATAST HCLK cycles for read accesses). 7-4 ADDHLD Don’t care 3-0 ADDSET Duration of the first access phase (ADDSET HCLK cycles). Minimum value for ADDSET is 0. Time between NEx high to NEx low (BUSTURN HCLK) DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) Mode A - SRAM/PSRAM (CRAM) OE toggling Figure 33. ModeA read access waveforms -EMORY TRANSACTION !;= .",;= .%X ./% .7% (IGH DATA DRIVEN BY MEMORY $;= !$$3%4 (#,+ CYCLES $!4!34 (#,+ CYCLES -36 1. NBL[1:0] are driven low during the read access Figure 34. ModeA write access waveforms DĞŵŽƌLJƚƌĂŶƐĂĐƚŝŽŶ Ϯϱ͗Ϭ E>ϭ͗Ϭ Edž EK ϭ,>< Et ĚĂƚĂĚƌŝǀĞŶďLJ&^D ϭϱ͗Ϭ ^d ,><ĐLJĐůĞƐ ;d^dнϭͿ ,><ĐLJĐůĞƐ D^ϯϯϰϰϴϬsϭ DocID024597 Rev 1 355/1680 396 Flexible static memory controller (FSMC) RM0351 The differences compared with mode1 are the toggling of NOE and the independent read and write timings. Table 56. FMC_BCRx bit fields Bit number Bit name Value to set 31-22 Reserved 21 WFDIS As needed 20 CCLKEN As needed 19 CBURSTRW 0x0 (no effect in asynchronous mode) 18:16 CPSIZE 0x0 (no effect in asynchronous mode) 15 ASYNCWAIT 14 EXTMOD 0x1 13 WAITEN 0x0 (no effect in asynchronous mode) 12 WREN As needed 11 WAITCFG Don’t care 11 Reserved 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN Don’t care 5-4 MWID As needed 3-2 MTYP As needed, exclude 0x2 (NOR Flash memory) 1 MUXEN 0x0 0 MBKEN 0x1 0x000 Set to 1 if the memory supports this feature. Otherwise keep at 0. Table 57. FMC_BTRx bit fields 356/1680 Bit number Bit name Value to set 31:30 Reserved 0x0 29-28 ACCMOD 0x0 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Duration of the second access phase (DATAST HCLK cycles) for read accesses. 7-4 ADDHLD Don’t care 3-0 ADDSET Duration of the first access phase (ADDSET HCLK cycles) for read accesses. Minimum value for ADDSET is 0. Time between NEx high to NEx low (BUSTURN HCLK) DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) Table 58. FMC_BWTRx bit fields Bit number Bit name Value to set 31:30 Reserved 0x0 29-28 ACCMOD 0x0 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Duration of the second access phase (DATAST HCLK cycles) for write accesses. 7-4 ADDHLD Don’t care 3-0 ADDSET Duration of the first access phase (ADDSET HCLK cycles) for write accesses. Minimum value for ADDSET is 0. Time between NEx high to NEx low (BUSTURN HCLK) Mode 2/B - NOR Flash Figure 35. Mode2 and mode B read access waveforms 0HPRU\WUDQVDFWLRQ $>@ 1$'9 1([ 12( 1:( +LJK GDWDGULYHQ E\PHPRU\ '>@ $''6(7 +&/.F\FOHV '$7$67 +&/.F\FOHV 069 DocID024597 Rev 1 357/1680 396 Flexible static memory controller (FSMC) RM0351 Figure 36. Mode2 write access waveforms -EMORY TRANSACTION !;= .!$6 .%X ./% .7% (IGH DATA DRIVEN BY MEMORY $;= !$$3%4 (#,+ CYCLES $!4!34 (#,+ CYCLES -36 Figure 37. ModeB write access waveforms 0HPRU\WUDQVDFWLRQ $>@ 1$'9 1([ 12( +&/. 1:( '>@ GDWDGULYHQE\)0& $''6(7 +&/.F\FOHV '$7$67 +&/.F\FOHV 069 The differences with mode1 are the toggling of NWE and the independent read and write timings when extended mode is set (Mode B). 358/1680 DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) Table 59. FMC_BCRx bit fields Bit number Bit name Value to set 31-22 Reserved 21 WFDIS As needed 20 CCLKEN As needed 19 CBURSTRW 0x0 (no effect in asynchronous mode) 18:16 CPSIZE 0x0 (no effect in asynchronous mode) 15 ASYNCWAIT 14 EXTMOD 0x1 for mode B, 0x0 for mode 2 13 WAITEN 0x0 (no effect in asynchronous mode) 12 WREN As needed 11 WAITCFG Don’t care 10 Reserved 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN 0x1 5-4 MWID As needed 3-2 MTYP 0x2 (NOR Flash memory) 1 MUXEN 0x0 0 MBKEN 0x1 0x000 Set to 1 if the memory supports this feature. Otherwise keep at 0. Table 60. FMC_BTRx bit fields Bit number Bit name Value to set 31-30 Reserved 0x0 29-28 ACCMOD 0x1 if extended mode is set 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Duration of the access second phase (DATAST HCLK cycles) for read accesses. 7-4 ADDHLD Don’t care 3-0 ADDSET Duration of the access first phase (ADDSET HCLK cycles) for read accesses. Minimum value for ADDSET is 0. Time between NEx high to NEx low (BUSTURN HCLK) DocID024597 Rev 1 359/1680 396 Flexible static memory controller (FSMC) RM0351 Table 61. FMC_BWTRx bit fields Note: Bit number Bit name Value to set 31-30 Reserved 0x0 29-28 ACCMOD 0x1 if extended mode is set 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Duration of the access second phase (DATAST HCLK cycles) for write accesses. 7-4 ADDHLD Don’t care 3-0 ADDSET Duration of the access first phase (ADDSET HCLK cycles) for write accesses. Minimum value for ADDSET is 0. Time between NEx high to NEx low (BUSTURN HCLK) The FMC_BWTRx register is valid only if the extended mode is set (mode B), otherwise its content is don’t care. Mode C - NOR Flash - OE toggling Figure 38. ModeC read access waveforms -EMORY TRANSACTION !;= .!$6 .%X ./% .7% (IGH DATA DRIVEN BY MEMORY $;= !$$3%4 (#,+ CYCLES $!4!34 (#,+ CYCLES -36 360/1680 DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) Figure 39. ModeC write access waveforms -EMORY TRANSACTION !;= .!$6 .%X ./% (#,+ .7% $;= DATA DRIVEN BY &3-# !$$3%4 (#,+ CYCLES $!4!34 (#,+ CYCLES -36 The differences compared with mode1 are the toggling of NOE and the independent read and write timings. Table 62. FMC_BCRx bit fields Bit number Bit name Value to set 31-22 Reserved 21 WFDIS As needed 20 CCLKEN As needed 19 CBURSTRW 0x0 (no effect in asynchronous mode) 18:16 CPSIZE 0x0 (no effect in asynchronous mode) 15 ASYNCWAIT 14 EXTMOD 0x1 13 WAITEN 0x0 (no effect in asynchronous mode) 12 WREN As needed 11 WAITCFG Don’t care 10 Reserved 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN 0x1 5-4 MWID 0x000 Set to 1 if the memory supports this feature. Otherwise keep at 0. As needed DocID024597 Rev 1 361/1680 396 Flexible static memory controller (FSMC) RM0351 Table 62. FMC_BCRx bit fields (continued) Bit number Bit name Value to set 3-2 MTYP 1 MUXEN 0x0 0 MBKEN 0x1 0x02 (NOR Flash memory) Table 63. FMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 0x0 29-28 ACCMOD 0x2 27-24 DATLAT 0x0 23-20 CLKDIV 0x0 19-16 BUSTURN 15-8 DATAST Duration of the second access phase (DATAST HCLK cycles) for read accesses. 7-4 ADDHLD Don’t care 3-0 ADDSET Duration of the first access phase (ADDSET HCLK cycles) for read accesses. Minimum value for ADDSET is 0. Time between NEx high to NEx low (BUSTURN HCLK) Table 64. FMC_BWTRx bit fields 362/1680 Bit number Bit name Value to set 31:30 Reserved 0x0 29-28 ACCMOD 0x2 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Duration of the second access phase (DATAST HCLK cycles) for write accesses. 7-4 ADDHLD Don’t care 3-0 ADDSET Duration of the first access phase (ADDSET HCLK cycles) for write accesses. Minimum value for ADDSET is 0. Time between NEx high to NEx low (BUSTURN HCLK) DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) Mode D - asynchronous access with extended address Figure 40. ModeD read access waveforms -EMORY TRANSACTION !;= .!$6 .%X ./% .7% (IGH DATA DRIVEN BY MEMORY $;= !$$3%4 (#,+ CYCLES !$$(,$ (#,+ CYCLES $!4!34 (#,+ CYCLES -36 Figure 41. ModeD write access waveforms 0HPRU\WUDQVDFWLRQ $>@ 1$'9 1([ 12( +&/. 1:( GDWDGULYHQE\)60& '>@ $''6(7 +&/.F\FOHV $''+/' +&/.F\FOHV DocID024597 Rev 1 '$7$67 +&/.F\FOHV 069 363/1680 396 Flexible static memory controller (FSMC) RM0351 The differences with mode1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings. Table 65. FMC_BCRx bit fields Bit number Bit name Value to set 31-22 Reserved 21 WFDIS As needed 20 CCLKEN As needed 19 CBURSTRW 0x0 (no effect in asynchronous mode) 18:16 CPSIZE 0x0 (no effect in asynchronous mode) 15 ASYNCWAIT 14 EXTMOD 0x1 13 WAITEN 0x0 (no effect in asynchronous mode) 12 WREN As needed 11 WAITCFG Don’t care 10 Reserved 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN Set according to memory support 5-4 MWID As needed 3-2 MTYP As needed 1 MUXEN 0x0 0 MBKEN 0x1 0x000 Set to 1 if the memory supports this feature. Otherwise keep at 0. Table 66. FMC_BTRx bit fields 364/1680 Bit number Bit name Value to set 31:30 Reserved 0x0 29-28 ACCMOD 0x3 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Duration of the second access phase (DATAST HCLK cycles) for read accesses. 7-4 ADDHLD Duration of the middle phase of the read access (ADDHLD HCLK cycles) 3-0 ADDSET Duration of the first access phase (ADDSET HCLK cycles) for read accesses. Minimum value for ADDSET is 1. Time between NEx high to NEx low (BUSTURN HCLK) DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) Table 67. FMC_BWTRx bit fields Bit number Bit name Value to set 31:30 Reserved 0x0 29-28 ACCMOD 0x3 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Duration of the second access phase (DATAST + 1 HCLK cycles) for write accesses. 7-4 ADDHLD Duration of the middle phase of the write access (ADDHLD HCLK cycles) 3-0 ADDSET Duration of the first access phase (ADDSET HCLK cycles) for write accesses. Minimum value for ADDSET is 1. Time between NEx high to NEx low (BUSTURN HCLK) Muxed mode - multiplexed asynchronous access to NOR Flash memory Figure 42. Muxed read access waveforms -EMORY TRANSACTION !;= .!$6 .%X ./% .7% !$;= (IGH ,OWER ADDRESS !$$3%4 (#,+ CYCLES !$$(,$ (#,+ CYCLES DocID024597 Rev 1 DATA DRIVEN BY MEMORY $!4!34 (#,+ CYCLES AI 365/1680 396 Flexible static memory controller (FSMC) RM0351 Figure 43. Muxed write access waveforms -EMORY TRANSACTION !;= .!$6 .%X ./% (#,+ .7% ,OWER ADDRESS !$;= !$$3%4 (#,+ CYCLES DATA DRIVEN BY &3-# !$$(,$ (#,+ CYCLES $!4!34 (#,+ CYCLES AI The difference with mode D is the drive of the lower address byte(s) on the data bus. Table 68. FMC_BCRx bit fields 366/1680 Bit number Bit name Value to set 31-22 Reserved 21 WFDIS As needed 20 CCLKEN As needed 19 CBURSTRW 0x0 (no effect in asynchronous mode) 18:16 CPSIZE 0x0 (no effect in asynchronous mode) 15 ASYNCWAIT 14 EXTMOD 0x0 13 WAITEN 0x0 (no effect in asynchronous mode) 12 WREN As needed 11 WAITCFG Don’t care 10 Reserved 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN 0x1 5-4 MWID As needed 3-2 MTYP 0x2 (NOR Flash memory) 0x000 Set to 1 if the memory supports this feature. Otherwise keep at 0. DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) Table 68. FMC_BCRx bit fields (continued) Bit number Bit name Value to set 1 MUXEN 0x1 0 MBKEN 0x1 Table 69. FMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 0x0 29-28 ACCMOD 0x0 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN 15-8 DATAST Duration of the second access phase (DATAST HCLK cycles for read accesses and DATAST+1 HCLK cycles for write accesses). 7-4 ADDHLD Duration of the middle phase of the access (ADDHLD HCLK cycles). 3-0 ADDSET Duration of the first access phase (ADDSET HCLK cycles). Minimum value for ADDSET is 1. Time between NEx high to NEx low (BUSTURN HCLK) WAIT management in asynchronous accesses If the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to accept or to provide data, the ASYNCWAIT bit has to be set in FMC_BCRx register. If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access phase (Data setup phase), programmed by the DATAST bits, is extended until WAIT becomes inactive. Unlike the data setup phase, the first access phases (Address setup and Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT sensitive and so they are not prolonged. The data setup phase must be programmed so that WAIT can be detected 4 HCLK cycles before the end of the memory transaction. The following cases must be considered: DocID024597 Rev 1 367/1680 396 Flexible static memory controller (FSMC) 1. RM0351 The memory asserts the WAIT signal aligned to NOE/NWE which toggles: DATAST ≥ ( 4 × HCLK ) + max_wait_assertion_time 2. The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling): if max_wait_assertion_time > address_phase + hold_phase then: DATAST ≥ ( 4 × HCLK ) + ( max_wait_assertion_time – address_phase – hold_phase ) otherwise DATAST ≥ 4 × HCLK where max_wait_assertion_time is the maximum time taken by the memory to assert the WAIT signal once NEx/NOE/NWE is low. Figure 44 and Figure 45 show the number of HCLK clock cycles that are added to the memory access phase after WAIT is released by the asynchronous memory (independently of the above cases). Figure 44. Asynchronous wait during a read access waveforms 0HPRU\WUDQVDFWLRQ $>@ DGGUHVVSKDVH GDWDVHWXSSKDVH 1([ .7!)4 DONT CARE DONT CARE 12( GDWDGULYHQE\PHPRU\ '>@ +&/. 069 1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register. 368/1680 DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) Figure 45. Asynchronous wait during a write access waveforms 0HPRU\WUDQVDFWLRQ $>@ DGGUHVVSKDVH GDWDVHWXSSKDVH 1([ .7!)4 DONT CARE DONT CARE +&/. 1:( '>@ GDWDGULYHQE\)60& +&/. 069 1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register. 14.5.5 Synchronous transactions The memory clock, FMC_CLK, is a submultiple of HCLK. It depends on the value of CLKDIV and the MWID/ AHB data size, following the formula given below: FMC_CLK divider ratio = max (CLKDIV + 1,MWID ( AHB data size )) Whatever MWID size: 16 or 8-bit, the FMC_CLK divider ratio is always defined by the programmed CLKDIV value. Example: • If CLKDIV=1, MWID = 16 bits, AHB data size=8 bits, FMC_CLK=HCLK/2. NOR Flash memories specify a minimum time from NADV assertion to CLK high. To meet this constraint, the FMC does not issue the clock to the memory during the first internal clock cycle of the synchronous access (before NADV assertion). This guarantees that the rising edge of the memory clock occurs in the middle of the NADV low pulse. Data latency versus NOR memory latency The data latency is the number of cycles to wait before sampling the data. The DATLAT value must be consistent with the latency value specified in the NOR Flash configuration register. The FMC does not include the clock cycle when NADV is low in the data latency count. DocID024597 Rev 1 369/1680 396 Flexible static memory controller (FSMC) Caution: RM0351 Some NOR Flash memories include the NADV Low cycle in the data latency count, so that the exact relation between the NOR Flash latency and the FMC DATLAT parameter can be either: • NOR Flash latency = (DATLAT + 2) CLK clock cycles • or NOR Flash latency = (DATLAT + 3) CLK clock cycles Some recent memories assert NWAIT during the latency phase. In such cases DATLAT can be set to its minimum value. As a result, the FMC samples the data and waits long enough to evaluate if the data are valid. Thus the FMC detects when the memory exits latency and real data are processed. Other memories do not assert NWAIT during latency. In this case the latency must be set correctly for both the FMC and the memory, otherwise invalid data are mistaken for good data, or valid data are lost in the initial phase of the memory access. Single-burst transfer When the selected bank is configured in burst mode for synchronous accesses, if for example an AHB single-burst transaction is requested on 16-bit memories, the FMC performs a burst transaction of length 1 (if the AHB transfer is 16 bits), or length 2 (if the AHB transfer is 32 bits) and de-assert the Chip Select signal when the last data is strobed. Such transfers are not the most efficient in terms of cycles compared to asynchronous read operations. Nevertheless, a random asynchronous access would first require to re-program the memory access mode, which would altogether last longer. Cross boundary page for Cellular RAM 1.5 Cellular RAM 1.5 does not allow burst access to cross the page boundary. The FMC controller allows to split automatically the burst access when the memory page size is reached by configuring the CPSIZE bits in the FMC_BCR1 register following the memory page size. Wait management For synchronous NOR Flash memories, NWAIT is evaluated after the programmed latency period, which corresponds to (DATLAT+2) CLK clock cycles. If NWAIT is active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait states are inserted until NWAIT is inactive (high level when WAITPOL = 0, low level when WAITPOL = 1). When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1) or on the next clock edge (bit WAITCFG = 0). During wait-state insertion via the NWAIT signal, the controller continues to send clock pulses to the memory, keeping the Chip Select and output enable signals valid. It does not consider the data as valid. In burst mode, there are two timing configurations for the NOR Flash NWAIT signal: • The Flash memory asserts the NWAIT signal one data cycle before the wait state (default after reset). • The Flash memory asserts the NWAIT signal during the wait state The FMC supports both NOR Flash wait state configurations, for each Chip Select, thanks to the WAITCFG bit in the FMC_BCRx registers (x = 0..3). 370/1680 DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) Figure 46. Wait configuration waveforms 0HPRU\WUDQVDFWLRQ EXUVWRIKDOIZRUGV +&/. &/. $>@ DGGU>@ 1$'9 1:$,7 :$,7&)* 1:$,7 :$,7&)* LQVHUWHGZDLWVWDWH $'>@ DGGU>@ GDWD GDWD GDWD DLF DocID024597 Rev 1 371/1680 396 Flexible static memory controller (FSMC) RM0351 Figure 47. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) 0HPRU\WUDQVDFWLRQ EXUVWRIKDOIZRUGV +&/. &/. $>@ DGGU>@ 1([ 12( 1:( +LJK 1$'9 1:$,7 :$,7&)* '$7/$7 &/.F\FOHV $'>@ $GGU>@ LQVHUWHGZDLWVWDWH GDWD FORFN FORFN F\FOH F\FOH GDWD GDWD GDWD 'DWDVWUREHV 'DWDVWUREHV DLI 1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held low. Table 70. FMC_BCRx bit fields 372/1680 Bit number Bit name Value to set 31-22 Reserved 21 WFDIS As needed 20 CCLKEN As needed 19 CBURSTRW 18:16 CPSIZE 15 ASYNCWAIT 0x0 14 EXTMOD 0x0 13 WAITEN To be set to 1 if the memory supports this feature, to be kept at 0 otherwise 12 WREN 0x000 No effect on synchronous read 0x0 (no effect in asynchronous mode) no effect on synchronous read DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) Table 70. FMC_BCRx bit fields (continued) Bit number Bit name Value to set 11 WAITCFG to be set according to memory 10 Reserved 0x0 9 WAITPOL to be set according to memory 8 BURSTEN 0x1 7 Reserved 0x1 6 FACCEN Set according to memory support (NOR Flash memory) 5-4 MWID As needed 3-2 MTYP 0x1 or 0x2 1 MUXEN As needed 0 MBKEN 0x1 Table 71. FMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 0x0 29:28 ACCMOD 0x0 27-24 DATLAT Data latency 27-24 DATLAT Data latency 23-20 CLKDIV 0x0 to get CLK = HCLK (Not supported) 0x1 to get CLK = 2 × HCLK .. 19-16 BUSTURN 15-8 DATAST Don’t care 7-4 ADDHLD Don’t care 3-0 ADDSET Don’t care Time between NEx high to NEx low (BUSTURN HCLK) DocID024597 Rev 1 373/1680 396 Flexible static memory controller (FSMC) RM0351 Figure 48. Synchronous multiplexed write mode waveforms - PSRAM (CRAM) -EMORY TRANSACTION BURST OF HALF WORDS (#,+ #,+ !;= ADDR;= .%X (I : ./% .7% .!$6 .7!)4 7!)4#&' $!4,!4 #,+ CYCLES !$;= !DDR;= INSERTED WAIT STATE DATA DATA CLOCK CLOCK AIF 1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0. 2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active. Table 72. FMC_BCRx bit fields Bit number Bit name 31-22 Reserved 21 WFDIS As needed 20 CCLKEN As needed 19 18:16 15 374/1680 Value to set 0x000 CBURSTRW 0x1 CPSIZE As needed (0x1 for CRAM 1.5) ASYNCWAIT 0x0 14 EXTMOD 0x0 13 WAITEN To be set to 1 if the memory supports this feature, to be kept at 0 otherwise. DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) Table 72. FMC_BCRx bit fields (continued) Bit number Bit name Value to set 12 WREN 0x1 11 WAITCFG 0x0 10 Reserved 0x0 9 WAITPOL to be set according to memory 8 BURSTEN no effect on synchronous write 7 Reserved 0x1 6 FACCEN Set according to memory support 5-4 MWID As needed 3-2 MTYP 0x1 1 MUXEN As needed 0 MBKEN 0x1 Table 73. FMC_BTRx bit fields Bit number Bit name Value to set 31-30 Reserved 0x0 29:28 ACCMOD 0x0 27-24 DATLAT Data latency 23-20 CLKDIV 0x0 to get CLK = HCLK (not supported) 0x1 to get CLK = 2 × HCLK 19-16 BUSTURN 15-8 DATAST Don’t care 7-4 ADDHLD Don’t care 3-0 ADDSET Don’t care Time between NEx high to NEx low (BUSTURN HCLK) DocID024597 Rev 1 375/1680 396 Flexible static memory controller (FSMC) 14.5.6 RM0351 NOR/PSRAM controller registers SRAM/NOR-Flash chip-select control registers 1..4 (FMC_BCR1..4) Address offset: 8 * (x – 1), x = 1...4 Reset value: 0x0000 30DB for Bank1 and 0x0000 30D2 for Bank 2 to 4 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories. 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 ASYNC WAIT EXT MOD WAIT EN WREN WAIT CFG Res. WAIT POL BURST EN Res. FACC EN rw rw rw rw rw rw rw rw 21 20 19 WFDIS CCLK EN CBURST RW rw rw rw rw rw 5 4 3 2 1 0 MUX EN MBK EN rw rw MWID rw 18 rw 16 CPSIZE[2:0] MTYP rw 17 rw rw Bits 31: 22 Reserved, must be kept at reset value Bit 21 WFDIS: Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. 0 : Write FIFO enabled (Default after reset) 1: Write FIFO disabled Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bit 20 CCLKEN: Continuous Clock Enable. This bit enables the FMC_CLK clock output to external memory devices. 0: The FMC_CLK is only generated during the synchronous memory access (read/write transaction). The FMC_CLK clock ratio is specified by the programmed CLKDIV value in the FMC_BCRx register (default after reset) . 1: The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.) Bit 19 CBURSTRW: Write burst enable. For PSRAM (CRAM) operating in burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. 0: Write operations are always performed in asynchronous mode 1: Write operations are performed in synchronous mode. 376/1680 DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) Bits 18:16 CPSIZE[2:0]: CRAM page size. These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). 000: No burst split when crossing page boundary (default after reset) 001: 128 bytes 010: 256 bytes 100: 1024 bytes Others: reserved Bit 15 ASYNCWAIT: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. 0: NWAIT signal is not taken in to account when running an asynchronous protocol (default after reset) 1: NWAIT signal is taken in to account when running an asynchronous protocol Bit 14 EXTMOD: Extended mode enable. This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. 0: values inside FMC_BWTR register are not taken into account (default after reset) 1: values inside FMC_BWTR register are taken into account Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: – Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) – Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). Bit 13 WAITEN: Wait enable bit. This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. 0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period) 1: NWAIT signal is enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset) Bit 12 WREN: Write enable bit. This bit indicates whether write operations are enabled/disabled in the bank by the FMC: 0: Write operations are disabled in the bank by the FMC, an AHB error is reported, 1: Write operations are enabled for the bank by the FMC (default after reset). Bit 11 WAITCFG: Wait timing configuration. The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 0: NWAIT signal is active one data cycle before wait state (default after reset), 1: NWAIT signal is active during wait state (not used for PSRAM). Bit 10 Reserved, must be kept at reset value Bit 9 WAITPOL: Wait signal polarity bit. Defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode: 0: NWAIT active low (default after reset), 1: NWAIT active high. DocID024597 Rev 1 377/1680 396 Flexible static memory controller (FSMC) RM0351 Bit 8 BURSTEN: Burst enable bit. This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in burst mode: 0: Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode. 1: Burst mode enable. Read accesses are performed in synchronous mode. Bit 7 Reserved, must be kept at reset value Bit 6 FACCEN: Flash access enable Enables NOR Flash memory access operations. 0: Corresponding NOR Flash memory access is disabled 1: Corresponding NOR Flash memory access is enabled (default after reset) Bits 5:4 MWID: Memory data bus width. Defines the external memory device width, valid for all type of memories. 00: 8 bits 01: 16 bits (default after reset) 10: reserved 11: reserved Bits 3:2 MTYP: Memory type. Defines the type of external memory attached to the corresponding memory bank: 00: SRAM (default after reset for Bank 2...4) 01: PSRAM (CRAM) 10: NOR Flash/OneNAND Flash (default after reset for Bank 1) 11: reserved Bit 1 MUXEN: Address/data multiplexing enable bit. When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories: 0: Address/Data nonmultiplexed 1: Address/Data multiplexed on databus (default after reset) Bit 0 MBKEN: Memory bank enable bit. Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus. 0: Corresponding memory bank is disabled 1: Corresponding memory bank is enabled SRAM/NOR-Flash chip-select timing registers 1..4 (FMC_BTR1..4) Address offset: 0x04 + 8 * (x – 1), x = 1..4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). 31 30 Res. Res. 29 rw 378/1680 28 27 ACCMOD rw 26 25 24 23 22 DATLAT rw rw 21 20 19 CLKDIV rw rw rw rw DocID024597 Rev 1 rw 18 17 16 BUSTURN rw rw rw rw rw RM0351 15 Flexible static memory controller (FSMC) 14 13 12 11 10 9 8 7 6 DATAST rw rw rw rw rw 5 4 3 ADDHLD rw rw rw rw rw rw 2 1 0 ADDSET rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value Bits 29:28 ACCMOD: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 00: access mode A 01: access mode B 10: access mode C 11: access mode D Bits 27:24 DATLAT: (see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods. For asynchronous access, this value is don't care. 0000: Data latency of 2 CLK clock cycles for first burst access 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) Bits 23:20 CLKDIV: Clock divide ratio (for FMC_CLK signal) Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles: 0000: Reserved 0001: FMC_CLK period = 2 × HCLK periods 0010: FMC_CLK period = 3 × HCLK periods 1111: FMC_CLK period = 16 × HCLK periods (default value after reset) In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Note: Refer to Section 14.5.5: Synchronous transactions for FMC_CLK divider ratio formula) Bits 19:16 BUSTURN: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read (and read-towrite) transaction. The bus turnaround delay is also inserted between two consecutive read or write transactions from or to different banks. In case of two consecutive read transactions to the same FMC bank, only 1 HCLK clock cycle is inserted whatever the configured BUSTURN timing. And in case of two consecutive write transactions to the same FMC bank, the bus turnaround delay is not inserted. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1)HCLK period ≥ tEHELmin and (BUSTRUN + 2)HCLK period ≥ tEHQZmax if EXTMOD = ‘0’ (BUSTRUN + 2)HCLK period ≥ max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. 0000: BUSTURN phase duration = 0 HCLK clock cycle added ... 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) DocID024597 Rev 1 379/1680 396 Flexible static memory controller (FSMC) RM0351 Bits 15:8 DATAST: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 31 to Figure 43), used in asynchronous accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 1 × HCLK clock cycles 0000 0010: DATAST phase duration = 2 × HCLK clock cycles ... 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) For each memory type and access mode data-phase duration, please refer to the respective figure (Figure 31 to Figure 43). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles. Note: In synchronous accesses, this value is don’t care. Bits 7:4 ADDHLD: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 31 to Figure 43), used in mode D or multiplexed accesses: 0000: Reserved 0001: ADDHLD phase duration =1 × HCLK clock cycle 0010: ADDHLD phase duration = 2 × HCLK clock cycle ... 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) For each access mode address-hold phase duration, please refer to the respective figure (Figure 31 to Figure 43). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration. Bits 3:0 ADDSET: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 31 to Figure 43), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM: 0000: ADDSET phase duration = 0 × HCLK clock cycle ... 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) For each access mode address setup phase duration, please refer to the respective figure (refer to Figure 31 to Figure 43). Note: In synchronous accesses, this value is don’t care. In Muxed mode or Mode D, the minimum value for ADDSET is 1. Note: 380/1680 PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these memories issue the NWAIT signal during the whole latency phase to prolong the latency as needed. With PSRAMs (CRAMs) the filled DATLAT must be set to 0, so that the FMC exits its latency phase soon and starts sampling NWAIT from memory, then starts to read or write when the memory is ready. This method can be used also with the latest generation of synchronous Flash memories that issue the NWAIT signal, unlike older Flash memories (check the datasheet of the specific Flash memory being used). DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) SRAM/NOR-Flash write timing registers 1..4 (FMC_BWTR1..4) Address offset: 0x104 + 8 * (x – 1), x = 1...4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 31 30 Res. Res. 15 14 29 28 ACCMOD rw rw 13 12 27 26 25 24 23 22 21 20 Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 DATAST rw rw rw rw rw 19 rw rw rw rw rw 17 16 BUSTURN rw rw rw rw 3 2 1 0 ADDHLD rw 18 ADDSET rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value Bits 29:28 ACCMOD: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 00: access mode A 01: access mode B 10: access mode C 11: access mode D Bits 27:20 Reserved, must be kept at reset value Bits 19:16 BUSTURN: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write to read transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) HCLK period ≥ tEHELmin. 0000: BUSTURN phase duration = 0 HCLK clock cycle added ... 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) Bits 15:8 DATAST: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 31 to Figure 43), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 1 × HCLK clock cycles 0000 0010: DATAST phase duration = 2 × HCLK clock cycles ... 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) DocID024597 Rev 1 381/1680 396 Flexible static memory controller (FSMC) RM0351 Bits 7:4 ADDHLD: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 40 to Figure 43), used in asynchronous multiplexed accesses: 0000: Reserved 0001: ADDHLD phase duration = 1 × HCLK clock cycle 0010: ADDHLD phase duration = 2 × HCLK clock cycle ... 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. Bits 3:0 ADDSET: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 31 to Figure 43), used in asynchronous accesses: 0000: ADDSET phase duration = 0 × HCLK clock cycle ... 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1. 14.6 NAND Flash controller The FMC generates the appropriate signal timings to drive the following types of device: • 8- and 16-bit NAND Flash memories The NAND bank is configured through dedicated registers (Section 14.6.7). The programmable memory parameters include access timings (shown in Table 74) and ECC configuration. 382/1680 DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) Table 74. Programmable NAND Flash access parameters 14.6.1 Parameter Function Access mode Unit Min. Max. Memory setup time Number of clock cycles (HCLK) required to set up the address before the command assertion Read/Write AHB clock cycle (HCLK) 1 256 Memory wait Minimum duration (in HCLK clock cycles) of the command assertion Read/Write AHB clock cycle (HCLK) 2 255 Memory hold Number of clock cycles (HCLK) during which the address must be held (as well as the data if a write access is performed) after the command de-assertion Read/Write AHB clock cycle (HCLK) 1 255 Memory databus high-Z Number of clock cycles (HCLK) during which the data bus is kept in high-Z state after a write access has started Write AHB clock cycle (HCLK) 1 255 External memory interface signals The following tables list the signals that are typically used to interface NAND Flash memory. Note: The prefix “N” identifies the signals which are active low. 8-bit NAND Flash memory t Table 75. 8-bit NAND Flash FMC signal name I/O Function A[17] O NAND Flash address latch enable (ALE) signal A[16] O NAND Flash command latch enable (CLE) signal D[7:0] I/O 8-bit multiplexed, bidirectional address/data bus NCE O Chip Select NOE(= NRE) O Output enable (memory signal name: read enable, NRE) NWE O Write enable NWAIT/INT I NAND Flash ready/busy input signal to the FMC Theoretically, there is no capacity limitation as the FMC can manage as many address cycles as needed. DocID024597 Rev 1 383/1680 396 Flexible static memory controller (FSMC) RM0351 16-bit NAND Flash memory Table 76. 16-bit NAND Flash FMC signal name I/O Function A[17] O NAND Flash address latch enable (ALE) signal A[16] O NAND Flash command latch enable (CLE) signal D[15:0] I/O 16-bit multiplexed, bidirectional address/data bus NCE O Chip Select NOE(= NRE) O Output enable (memory signal name: read enable, NRE) NWE O Write enable NWAIT/INT I NAND Flash ready/busy input signal to the FMC Theoretically, there is no capacity limitation as the FMC can manage as many address cycles as needed. 384/1680 DocID024597 Rev 1 RM0351 14.6.2 Flexible static memory controller (FSMC) NAND Flash supported memories and transactions Table 77 shows the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the NAND Flash controller are shown in gray. Table 77. Supported memories and transactions Device NAND 8-bit NAND 16-bit 14.6.3 AHB Memory Allowed/ data size data size not allowed Mode R/W Comments Asynchronous R 8 8 Y - Asynchronous W 8 8 Y - Asynchronous R 16 8 Y Split into 2 FMC accesses Asynchronous W 16 8 Y Split into 2 FMC accesses Asynchronous R 32 8 Y Split into 4 FMC accesses Asynchronous W 32 8 Y Split into 4 FMC accesses Asynchronous R 8 16 Y - Asynchronous W 8 16 N - Asynchronous R 16 16 Y - Asynchronous W 16 16 Y - Asynchronous R 32 16 Y Split into 2 FMC accesses Asynchronous W 32 16 Y Split into 2 FMC accesses Timing diagrams for NAND Flash memory The NAND Flash memory bank is managed through a set of registers: • Control register: FMC_PCR • Interrupt status register: FMC_SR • ECC register: FMC_ECCR • Timing register for Common memory space: FMC_PMEM • Timing register for Attribute memory space: FMC_PATT Each timing configuration register contains three parameters used to define number of HCLK cycles for the three phases of any NAND Flash access, plus one parameter that defines the timing for starting driving the data bus when a write access is performed. Figure 49 shows the timing parameter definitions for common memory accesses, knowing that Attribute memory space access timings are similar. DocID024597 Rev 1 385/1680 396 Flexible static memory controller (FSMC) RM0351 Figure 49. NAND Flash controller waveforms for common memory access +&/. $>@ 1&([ +LJK 15(* 1,2: 1,25 1:( 12( 0(0[6(7 0(0[:$,7 0(0[+2/' 0(0[+,= ZULWHBGDWD UHDGBGDWD 9DOLG 069 1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses. 14.6.4 NAND Flash operations The command latch enable (CLE) and address latch enable (ALE) signals of the NAND Flash memory device are driven by address signals from the FMC controller. This means that to send a command or an address to the NAND Flash memory, the CPU has to perform a write to a specific address in its memory space. A typical page read operation from the NAND Flash device requires the following steps: 386/1680 3. Program and enable the corresponding memory bank by configuring the FMC_PCR and FMC_PMEM (and for some devices, FMC_PATT, see Section 14.6.5: NAND Flash prewait functionality) registers according to the characteristics of the NAND Flash memory (PWID bits for the data bus width of the NAND Flash, PTYP = 1, PWAITEN = 0 or 1 as needed, see Section 14.4.2: NAND Flash memory address mapping for timing configuration). 4. The CPU performs a byte write to the common memory space, with data byte equal to one Flash command byte (for example 0x00 for Samsung NAND Flash devices). The LE input of the NAND Flash memory is active during the write strobe (low pulse on NWE), thus the written byte is interpreted as a command by the NAND Flash memory. Once the command is latched by the memory device, it does not need to be written again for the following page read operations. 5. The CPU can send the start address (STARTAD) for a read operation by writing four bytes (or three for smaller capacity devices), STARTAD[7:0], STARTAD[16:9], STARTAD[24:17] and finally STARTAD[25] (for 64 Mb x 8 bit NAND Flash memories) in the common memory or attribute space. The ALE input of the NAND Flash device is active during the write strobe (low pulse on NWE), thus the written bytes are interpreted as the start address for read operations. Using the attribute memory space makes it possible to use a different timing configuration of the FMC, which can be used DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) to implement the prewait functionality needed by some NAND Flash memories (see details in Section 14.6.5: NAND Flash prewait functionality). 14.6.5 6. The controller waits for the NAND Flash memory to be ready (R/NB signal high), before starting a new access to the same or another memory bank. While waiting, the controller holds the NCE signal active (low). 7. The CPU can then perform byte read operations from the common memory space to read the NAND Flash page (data field + Spare field) byte by byte. 8. The next NAND Flash page can be read without any CPU command or address write operation. This can be done in three different ways: – by simply performing the operation described in step 5 – a new random address can be accessed by restarting the operation at step 3 – a new command can be sent to the NAND Flash device by restarting at step 2 NAND Flash prewait functionality Some NAND Flash devices require that, after writing the last part of the address, the controller waits for the R/NB signal to go low. (see Figure 50). Figure 50. Access to non ‘CE don’t care’ NAND-Flash .#% MUST STAY LOW .#% #,% !,% .7% (IGH ./% T2 )/;= X ! ! ! ! ! ! ! T7" 2." AI 1. CPU wrote byte 0x00 at address 0x7001 0000. 2. CPU wrote byte A7~A0 at address 0x7002 0000. 3. CPU wrote byte A16~A9 at address 0x7002 0000. 4. CPU wrote byte A24~A17 at address 0x7002 0000. 5. CPU wrote byte A25 at address 0x7802 0000: FMC performs a write access using FMC_PATT2 timing definition, where ATTHOLD ≥ 7 (providing that (7+1) × HCLK = 112 ns > tWB max). This guarantees that NCE remains low until R/NB goes low and high again (only requested for NAND Flash memories where NCE is not don’t care). DocID024597 Rev 1 387/1680 396 Flexible static memory controller (FSMC) RM0351 When this functionality is required, it can be ensured by programming the MEMHOLD value to meet the tWB timing. However any CPU read or write access to the NAND Flash memory has a hold delay of (MEMHOLD + 1) HCLK cycles inserted between the rising edge of the NWE signal and the next access. To cope with this timing constraint, the attribute memory space can be used by programming its timing register with an ATTHOLD value that meets the tWB timing, and by keeping the MEMHOLD value at its minimum value. The CPU must then use the common memory space for all NAND Flash read and write accesses, except when writing the last address byte to the NAND Flash device, where the CPU must write to the attribute memory space. 14.6.6 Computation of the error correction code (ECC) in NAND Flash memory The FMC NAND Card controller includes two error correction code computation hardware blocks, one per memory bank. They reduce the host CPU workload when processing the ECC by software. These two ECC blocks are identical and associated with Bank 2 and Bank 3. As a consequence, no hardware ECC computation is available for memories connected to Bank 4. The ECC algorithm implemented in the FMC can perform 1-bit error correction and 2-bit error detection per 256, 512, 1 024, 2 048, 4 096 or 8 192 bytes read or written from/to the NAND Flash memory. It is based on the Hamming coding algorithm and consists in calculating the row and column parity. The ECC modules monitor the NAND Flash data bus and read/write signals (NCE and NWE) each time the NAND Flash memory bank is active. The ECC operates as follows: • When accessing NAND Flash memory bank 2 or bank 3, the data present on the D[15:0] bus is latched and used for ECC computation. • When accessing any other address in NAND Flash memory, the ECC logic is idle, and does not perform any operation. As a result, write operations to define commands or addresses to the NAND Flash memory are not taken into account for ECC computation. Once the desired number of bytes has been read/written from/to the NAND Flash memory by the host CPU, the FMC_ECCR registers must be read to retrieve the computed value. Once read, they should be cleared by resetting the ECCEN bit to ‘0’. To compute a new data block, the ECCEN bit must be set to one in the FMC_PCR registers. 388/1680 DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) To perform an ECC computation: 14.6.7 1. Enable the ECCEN bit in the FMC_PCR register. 2. Write data to the NAND Flash memory page. While the NAND page is written, the ECC block computes the ECC value. 3. Read the ECC value available in the FMC_ECCR register and store it in a variable. 4. Clear the ECCEN bit and then enable it in the FMC_PCR register before reading back the written data from the NAND page. While the NAND page is read, the ECC block computes the ECC value. 5. Read the new ECC value available in the FMC_ECCR register. 6. If the two ECC values are the same, no correction is required, otherwise there is an ECC error and the software correction routine returns information on whether the error can be corrected or not. NAND Flashcontroller registers NAND Flash control registers (FMC_PCR) Address offset: 0x80 Reset value: 0x0000 0018 31 30 29 28 27 26 25 24 23 22 21 20 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 TAR rw rw 10 9 TCLR rw rw rw rw 8 7 6 Res. Res. ECCEN rw rw 5 4 PWID rw 19 18 17 16 ECCPS TAR rw rw rw 3 2 1 rw 0 PTYP PBKEN PWAITEN rw rw rw Res. rw Bits 31:20 Reserved, must be kept at reset value Bits 19:17 ECCPS: ECC page size. Defines the page size for the extended ECC: 000: 256 bytes 001: 512 bytes 010: 1024 bytes 011: 2048 bytes 100: 4096 bytes 101: 8192 bytes Bits 16:13 TAR: ALE to RE delay. Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period 0000: 1 HCLK cycle (default) 1111: 16 HCLK cycles Note: SET is MEMSET or ATTSET according to the addressed space. DocID024597 Rev 1 389/1680 396 Flexible static memory controller (FSMC) RM0351 Bits 12:9 TCLR: CLE to RE delay. Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period 0000: 1 HCLK cycle (default) 1111: 16 HCLK cycles Note: SET is MEMSET or ATTSET according to the addressed space. Bits 8:7 Reserved, must be kept at reset value Bit 6 ECCEN: ECC computation logic enable bit 0: ECC logic is disabled and reset (default after reset), 1: ECC logic is enabled. Bits 5:4 PWID: Data bus width. Defines the external memory device width. 00: 8 bits 01: 16 bits (default after reset). 10: reserved. 11: reserved. Bit 3 PTYP: Memory type. Defines the type of device attached to the corresponding memory bank: 0: Reserved, must be kept at reset value 1: NAND Flash (default after reset) Bit 2 PBKEN: NAND Flash memory bank enable bit. Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus 0: Corresponding memory bank is disabled (default after reset) 1: Corresponding memory bank is enabled Bit 1 PWAITEN: Wait feature enable bit. Enables the Wait feature for the NAND Flash memory bank: 0: disabled 1: enabled Bit 0 Reserved, must be kept at reset value FIFO status and interrupt register (FMC_SR) Address offset: 0x84 Reset value: 0x0000 0040 This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data from the AHB. This is used to quickly write to the FIFO and free the AHB for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes. The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 390/1680 DocID024597 Rev 1 RM0351 Flexible static memory controller (FSMC) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. FEMPT IFEN ILEN IREN IFS ILS IRS r rw rw rw rw rw rw Bits 31:7 Reserved, must be kept at reset value Bit 6 FEMPT: FIFO empty. Read-only bit that provides the status of the FIFO 0: FIFO not empty 1: FIFO empty Bit 5 IFEN: Interrupt falling edge detection enable bit 0: Interrupt falling edge detection request disabled 1: Interrupt falling edge detection request enabled Bit 4 ILEN: Interrupt high-level detection enable bit 0: Interrupt high-level detection request disabled 1: Interrupt high-level detection request enabled Bit 3 IREN: Interrupt rising edge detection enable bit 0: Interrupt rising edge detection request disabled 1: Interrupt rising edge detection request enabled Bit 2 IFS: Interrupt falling edge status The flag is set by hardware and reset by software. 0: No interrupt falling edge occurred 1: Interrupt falling edge occurred Bit 1 ILS: Interrupt high-level status The flag is set by hardware and reset by software. 0: No Interrupt high-level occurred 1: Interrupt high-level occurred Bit 0 IRS: Interrupt rising edge status The flag is set by hardware and reset by software. 0: No interrupt rising edge occurred 1: Interrupt rising edge occurred Common memory space timing register 2..4 (FMC_PMEM) Address offset: Address: 0x88 Reset value: 0xFCFC FCFC The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access. 31 30 29 28 27 26 25 24 23 22 21 MEMHIZx 20 19 18 17 16 MEMHOLDx rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw MEMWAITx rw rw rw rw rw MEMSETx rw rw rw rw rw DocID024597 Rev 1 rw rw rw 391/1680 396 Flexible static memory controller (FSMC) RM0351 Bits 31:24 MEMHIZ: Common memory x data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space on socket. This is only valid for write transactions: 0000 0000: 1 HCLK cycle 1111 1111: 256 HCLK cycles Bits 23:16 MEMHOLD: Common memory hold time Defines the number of HCLK clock cycles during which the address is held (and data for write accesses) after the command is deasserted (NWE, NOE), for NAND Flash read or write access to common memory space on socket x: 0000 0000: reserved. 0000 0001: 1 HCLK cycle 1111 1111: 255 HCLK cycles Bits 15:8 MEMWAIT: Common memory wait time Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space on socket. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK: 0000 0000: reserved 0000 0001: 2HCLK cycles (+ wait cycle introduced by deasserting NWAIT) 1111 1110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) 1111 1111: reserved. Bits 7:0 MEMSET: Common memory x setup time Defines the number of HCLK (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space on socket x: 0000 0000: 1 HCLK cycle 1111 1111: 256 HCLK cycles Attribute memory space timing registers 2..4 (FMC_PATT) Address offset: 0x8C Reset value: 0xFCFC FCFC The FMC_PATT ead/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section 14.6.5: NAND Flash prewait functionality). 31 30 29 28 27 26 25 24 23 22 21 ATTHIZx 20 19 18 17 16 ATTHOLDx rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw ATTWAITx rw 392/1680 rw rw rw rw ATTSETx rw rw rw rw rw DocID024597 Rev 1 rw rw rw RM0351 Flexible static memory controller (FSMC) Bits 31:24 ATTHIZx: Attribute memory data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction: 0000 0000: 0 HCLK cycle 1111 1111: 255 HCLK cycles Bits 23:16 ATTHOLD: Attribute memory hold time Defines the number of HCLK clock cycles during which the address is held (and data for write access) after the command deassertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket: 0000 0000: reserved 0000 0001: 1 HCLK cycle 1111 1111: 255 HCLK cycles Bits 15:8 ATTWAIT: Attribute memory wait time Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket x. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK: 0000 0000: reserved 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) 1111 1110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) 1111 1111: reserved. Bits 7:0 ATTSET: Attribute memory setup time Defines the number of HCLK (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket: 0000 0000: 1 HCLK cycle 1111 1111: 256 HCLK cycles DocID024597 Rev 1 393/1680 396 Flexible static memory controller (FSMC) RM0351 ECC result registers (FMC_ECCR) Address offset: 0x94 Reset value: 0x0000 0000 This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads the data from a NAND Flash memory page at the correct address (refer to Section 14.6.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to ‘0’. To compute a new data block, the ECCEN bit must be set to ’1’. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ECCx r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r ECCx r r r r r r r r Bits 31:0 ECC: ECC result This field contains the value computed by the ECC computation logic. Table 78 describes the contents of these bit fields. Table 78. ECC result relevant bits 394/1680 ECCPS[2:0] Page size in bytes ECC bits 000 256 ECC[21:0] 001 512 ECC[23:0] 010 1024 ECC[25:0] 011 2048 ECC[27:0] 100 4096 ECC[29:0] 101 8192 ECC[31:0] DocID024597 Rev 1 RM0351 14.7 Flexible static memory controller (FSMC) FMC register map The following table summarizes the FMC registers. Reset value ACCMOD ACCMOD ACCMOD 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CLKDIV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Res. Res. Res. Res. Res. Res. 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. WAITCFG WAITPOL BURSTEN 1 0 0 0 CPSIZE [2:0] WAITEN WREN WAITCFG WAITPOL BURSTEN 0 0 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DocID024597 Rev 1 1 1 1 1 Res. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MBKEN 0 1 0 MWID MTYP 1 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ADDSET 1 1 1 1 1 ADDSET 1 1 1 1 1 ADDSET 1 1 1 1 1 ADDSET 1 1 ADDHLD 1 1 ADDSET ADDHLD 1 0 ADDSET ADDHLD DATAST 1 MWID MTYP ADDHLD DATAST 1 0 0 ADDHLD DATAST 1 1 1 ADDHLD DATAST 1 MUXEN Res. 1 DATAST 1 0 0 ADDHLD DATAST 1 FACCEN 1 DATAST BUSTURN 1 1 MBKEN WREN 1 MUXEN WAITEN 0 MWID MTYP 1 MBKEN EXTMOD 0 0 Res. ASYNCWAIT 0 0 1 1 MUXEN CPSIZE [2:0] 1 1 0 MBKEN 0 0 MWID MTYP MUXEN BURSTEN 0 FACCEN WAITPOL 0 FACCEN BURSTEN WAITCFG 1 FACCEN WAITPOL WREN 1 Res. WAITEN 0 Res. WREN WAITCFG EXTMOD 0 0 Res. WAITEN ASYNCWAIT 0 0 1 Res. EXTMOD CPSIZE [2:0] Res. ASYNCWAIT 0 BUSTURN 1 Res. 0 Res. 0 BUSTURN 1 Res. 0 BUSTURN Res. CLKDIV 1 Res. 1 BUSTURN 0 0 1 BUSTURN Res. 0 1 0 0 BUSTURN CLKDIV DATLAT Res. FMC_BWTR3 Res. 0x114 0 Res. Reset value 1 DATLAT Res. FMC_BWTR2 Res. 0x10C 0 Res. Reset value 1 Res. FMC_BWTR1 Res. 0x104 0 Res. Reset value 0 ACCMOD FMC_BTR4 Res. 0x1C 0 Res. Reset value 1 CLKDIV DATLAT ACCMOD FMC_BTR3 Res. 0x14 0 Res. Reset value 0 ACCMOD FMC_BTR2 Res. 0x0C 0 Res. Reset value DATLAT ACCMOD FMC_BTR1 Res. 0x04 0 Res. Reset value 0 0 EXTMOD Res. Res. CBURSTRW Res. Res. Res. Res. Res. Res. Res. FMC_BCR4 Res. 0 Res. Reset value CBURSTRW Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FMC_BCR3 0 CPSIZE [2:0] ASYNCWAIT CCLKEN CBURSTRW 0 CBURSTRW Res. WFDIS Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Res. 0x18 0 Reset value Res. 0x10 FMC_BCR2 Res. 0x08 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. FMC_BCR1 Res. 0x00 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 79. FMC register map 1 1 1 ADDSET 1 1 1 1 1 395/1680 396 Flexible static memory controller (FSMC) RM0351 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Reset value 0x88 FMC_PMEM Reset value 1 1 1 FMC_PATT 0x8C 0x94 MEMHIZx Reset value 1 1 MEMHOLDx 1 0 0 1 1 ATTHIZx 1 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 0 0 1 0 0 0 1 1 1 1 1 1 0 0 1 Res. 1 1 0 0 0 1 0 0 MEMSETx 0 0 1 1 1 1 1 ATTSETx 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCx 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 68 for the register boundary addresses. 396/1680 0 ATTWAITx FMC_ECCR Reset value 0 PWID 0 MEMWAITx ATTHOLDx 1 PWAITEN 0 1 ILS 0 1 IRS 0 1 PTYP 0 1 PBKEN 0 1 IFS 0 Res. TCLR 1 ILEN 1 IREN 1 IFEN 1 Res. TAR 1 Res. 1 ECCEN 1 ADDSET FEMPT 1 Res. ECCPS 1 Res. 1 Res. 1 ADDHLD Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 DATAST Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FMC_SR Res. Reset value 0x84 BUSTURN 1 Res. 0 Res. 0 Res. Res. FMC_PCR 0x80 Res. Reset value ACCM OD Res. FMC_BWTR4 Res. 0x11C Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 79. FMC register map (continued) DocID024597 Rev 1 RM0351 QuadSPI interface (QUADSPI) 15 QuadSPI interface (QUADSPI) 15.1 Introduction The QUADSPI is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the three following modes: 15.2 • indirect mode: all the operations are performed using the QUADSPI registers • status polling mode: the external Flash memory status register is periodically read and an interrupt can be generated in case of flag setting • memory-mapped mode: the external Flash memory is mapped to the microcontroller address space and is seen by the system as if it was an internal memory QUADSPI main features • Three functional modes: indirect, status-polling, and memory-mapped • SDR and DDR support • Fully programmable opcode for both indirect and memory mapped mode • Fully programmable frame format for both indirect and memory mapped mode • Integrated FIFO for reception and transmission • 8, 16, and 32-bit data accesses are allowed • DMA channel for indirect mode operations • Interrupt generation on FIFO threshold, timeout, operation complete, and access error 15.3 QUADSPI functional description 15.3.1 QUADSPI block diagram Figure 51. QUADSPI block diagram 48$'63, 5HJLVWHUV FRQWURO &ORFN PDQDJHPHQW $+% ),)2 6KLIWUHJLVWHU 63,)/$6+ &/. %.B,262 %.B,26, %.B,2 %.B,2 %.BQ&6 &/. 46, 462 4:3 4+2/' &6 069 DocID024597 Rev 1 397/1680 422 QuadSPI interface (QUADSPI) RM0351 The QUADSPI uses 6 signals to interface with a Flash memory: 15.3.2 – CLK - Clock output – BK1_IO0/SO - Bidirectional IO in dual/quad modes or serial output in single mode – BK1_IO1/SI - Bidirectional IO in dual/quad modes or serial input in single mode – BK1_IO2 - Bidirectional IO in quad mode – BK1_IO3 - Bidirectional IO in quad mode – BK1_nCS - Chip select output (active low) QUADSPI Command sequence The QUADSPI communicates with the Flash memory using commands. Each command can include 5 phases: instruction, address, alternate byte, dummy, data. Any of these phases can be configured to be skipped, but at least one of the instruction, address, alternate byte, or data phase must be present. nCS falls before the start of each command and rises again after each command finishes. Figure 52. An example of a read command in quad mode ,QVWUXFWLRQ $GGUHVV $OW 'XPP\ 'DWD Q&6 6&/. ,2 ,2 ,2 ,2 $ $ $ 0 %\WH ,2VZLWFKIURP RXWSXWWRLQSXW %\WH 069 Instruction phase During this phase, an 8-bit instruction, configured in INSTRUCTION field of QUADSPI_CCR[7:0] register, is sent to the Flash memory, specifying the type of operation to be performed. Though most Flash memories can receive instructions only one bit at a time from the IO0/SO signal (single SPI mode), the instruction phase can optionally send 2 bits at a time (over IO0/IO1 in dual SPI mode) or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode). This can be configured using the IMODE[1:0] field of QUADSPI_CCR[9:8] register. When IMODE = 00, the instruction phase is skipped, and the command sequence starts with the address phase, if present. Address phase In the address phase, 1-4 bytes are sent to the Flash memory to indicate the address of the operation. The number of address bytes to be sent is configured in the ADSIZE[1:0] field of QUADSPI_CCR[13:12] register. In indirect and automatic-polling modes, the address bytes to be sent are specified in the ADDRESS[31:0] field of QUADSPI_AR register, while in memory-mapped mode the address is given directly via the AHB (from the Cortex® or from a DMA). 398/1680 DocID024597 Rev 1 RM0351 QuadSPI interface (QUADSPI) The address phase can send 1 bit at a time (over SO in single SPI mode), 2 bits at a time (over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode). This can be configured using the ADMODE[1:0] field of QUADSPI_CCR[11:10] register. When ADMODE = 00, the address phase is skipped, and the command sequence proceeds directly to the next phase, if any. Alternate-bytes phase In the alternate-bytes phase, 1-4 bytes are sent to the Flash memory, generally to control the mode of operation. The number of alternate bytes to be sent is configured in the ABSIZE[1:0] field of QUADSPI_CCR[17:16] register. The bytes to be sent are specified in the QUADSPI_ABR register. The alternate-bytes phase can send 1 bit at a time (over SO in single SPI mode), 2 bits at a time (over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode). This can be configured using the ABMODE[1:0] field of QUADSPI_CCR[15:14] register. When ABMODE = 00, the alternate-bytes phase is skipped, and the command sequence proceeds directly to the next phase, if any. There may be times when only a single nibble needs to be sent during the alternate-byte phase rather than a full byte, such as when dual-mode is used and only two cycles are used for the alternate bytes. In this case, firmware can use quad-mode (ABMODE = 11) and send a byte with bits 7 and 3 of ALTERNATE set to ‘1’ (keeping the IO3 line high), and bits 6 and 2 set to ‘0’ (keeping the IO2 line low). In this case the upper two bits of the nibble to be sent are placed in bits 4:3 of ALTERNATE while the lower two bits are placed in bits 1 and 0. For example, if the nibble 2 (0010) is to be sent over IO0/IO1, then ALTERNATE should be set to 0x8A (1000_1010). Dummy-cycles phase In the dummy-cycles phase, 1-31 cycles are given without any data being sent or received, in order to allow the Flash memory the time to prepare for the data phase when higher clock frequencies are used. The number of cycles given during this phase is specified in the DCYC[4:0] field of QUADSPI_CCR[22:18] register. In both SDR and DDR modes, the duration is specified as a number of full CLK cycles. When DCYC is zero, the dummy-cycles phase is skipped, and the command sequence proceeds directly to the data phase, if present. The operating mode of the dummy-cycles phase is determined by DMODE. In order to assure enough “turn-around” time for changing the data signals from output mode to input mode, there must be at least one dummy cycle when using dual or quad mode to receive data from the Flash memory. Data phase During the data phase, any number of bytes can be sent to, or received from the Flash memory. In indirect and automatic-polling modes, the number of bytes to be sent/received is specified in the QUADSPI_DLR register. DocID024597 Rev 1 399/1680 422 QuadSPI interface (QUADSPI) RM0351 In indirect write mode the data to be sent to the Flash memory must be written to the QUADSPI_DR register, while in indirect read mode the data received from the Flash memory is obtained by reading from the QUADSPI_DR register. In memory-mapped mode, the data which is read is sent back directly over the AHB to the Cortex or to a DMA. The data phase can send/receive 1 bit at a time (over SO/SI in single SPI mode), 2 bits at a time (over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode). This can be configured using the ABMODE[1:0] field of QUADSPI_CCR[15:14] register. When DMODE = 00, the data phase is skipped, and the command sequence finishes immediately by raising nCS. This configuration must only be used in only indirect write mode. 15.3.3 QUADSPI signal interface protocol modes Single SPI mode Legacy SPI mode allows just a single bit to be sent/received serially. In this mode, data is sent to the Flash memory over the SO signal (whose I/O shared with IO0). Data received from the Flash memory arrives via SI (whose I/O shared with IO1). The different phases can each be configured separately to use this single bit mode by setting the IMODE/ADMODE/ABMODE/DMODE fields (in QUADSPI_CCR) to 01. In each phase which is configured in single mode: • IO0 (SO) is in output mode • IO1 (SI) is in input mode (high impedance) • IO2 is in output mode and forced to ‘0’ (to deactivate the “write protect” function) • IO3 is in output mode and forced to ‘1’ (to deactivate the “hold” function) This is the case even for the dummy phase if DMODE = 01. Dual SPI mode In dual SPI mode, two bits are sent/received simultaneously over the IO0/IO1 signals. The different phases can each be configured separately to use dual SPI mode by setting the IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 10. In each phase which is configured in dual mode: • IO0/IO1 are at high-impedance (input) during the data phase for read operations, and outputs in all other cases • IO2 is in output mode and forced to ‘0’ • IO3 is in output mode and forced to ‘1’ In the dummy phase when DMODE = 01, IO0/IO1 are always high-impedance. Quad SPI mode In quad SPI mode, four bits are sent/received simultaneously over the IO0/IO1/IO2/IO3 signals. The different phases can each be configured separately to use quad SPI mode by setting the IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 11. 400/1680 DocID024597 Rev 1 RM0351 QuadSPI interface (QUADSPI) In each phase which is configured in quad mode, IO0/IO1/IO2/IO3 are all are at highimpedance (input) during the data phase for read operations, and outputs in all other cases. In the dummy phase when DMODE = 11, IO0/IO1/IO2/IO3 are all high-impedance. IO2 and IO3 are used only in Quad SPI mode. If none of the phases are configured to use Quad SPI mode, then the pins corresponding to IO2 and IO3 can be used for other functions even while QUADSPI is active. SDR mode By default, the DDRM bit (QUADSPI_CCR[31]) is 0 and the QUADSPI operates in single data rate (SDR) mode. In SDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals, these signals transition only with the falling edge of CLK. When receiving data in SDR mode, the QUADSPI assumes that the Flash memories also send the data using CLK’s falling edge. By default (when SSHIFT = 0), the signals are sampled using the following (rising) edge of CLK. DDR mode When the DDRM bit (QUADSPI_CCR[31]) is set to 1, the QUADSPI operates in double data rate (DDR) mode. In DDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals in the address/alternate-byte/data phases, a bit is sent on each of the falling and rising edges of CLK. The instruction phase is not affected by DDRM. The instruction is always sent using CLK’s falling edge. When receiving data in DDR mode, the QUADSPI assumes that the Flash memories also send the data using both rising and falling CLK edges. When DDRM = 1, firmware must clear SSHIFT bit (QUADSPI_CR[4]). Thus, the signals are sampled one half of a CLK cycle later (on the following, opposite edge). Figure 53. An example of a DDR command in quad mode ,QVWUXFWLRQ $GGUHVV $OW 'XPP\ 'DWD Q&6 6&/. ,2 ,2 ,2 ,2 $$ $ 0 %\WH%\WH ,2VZLWFKIURP RXWSXWWRLQSXW 15.3.4 069 QUADSPI indirect mode When in indirect mode, commands are started by writing to QUADSPI registers and data is transferred by writing or reading the data register, in the same way as for other communication peripherals. DocID024597 Rev 1 401/1680 422 QuadSPI interface (QUADSPI) RM0351 When FMODE = 00 (QUADSPI_CCR[27:26]), the QUADSPI is in indirect write mode, where bytes are sent to the Flash memory during the data phase. Data are provided by writing to the data register (QUADSPI_DR). When FMODE = 01, the QUADSPI is in indirect read mode, where bytes are received from the Flash memory during the data phase. Data are recovered by reading QUADSPI_DR. The number of bytes to be read/written is specified in the data length register (QUADSPI_DLR). If QUADSPI_DLR = 0xFFFF_FFFF (all 1’s), then the data length is considered undefined and the QUADSPI simply continues to transfer data until the end of Flash memory (as defined by FSIZE) is reached. If no bytes are to be transferred, DMODE (QUADSPI_CCR[25:24]) should be set to 00. If QUADSPI_DLR = 0xFFFF_FFFF and FSIZE = 0x1F (max value indicating a 4GB Flash memory), then in this special case the transfers continue indefinitely, stopping only after an abort request or after the QUADSPI is disabled. After the last memory address is read (at address 0xFFFF_FFFF), reading continues with address = 0x0000_0000. When the programmed number of bytes to be transmitted or received is reached, TCF is set and an interrupt is generated if TCIE = 1. In the case of undefined number of data, the TCF is set when the limit of the external SPI memory is reached according to the Flash memory size defined in the QUADSPI_CR. Triggering the start of a command Essentially, a command starts as soon as firmware gives the last information that is necessary for this command. Depending on the QUADSPI configuration, there are three different ways to trigger the start of a command in indirect mode. The commands starts immediately after: 1. a write is performed to INSTRUCTION[7:0] (QUADSPI_CCR), if no address is necessary (when ADMODE = 00) and if no data needs to be provided by the firmware (when FMODE = 01 or DMODE = 00) 2. a write is performed to ADDRESS[31:0] (QUADSPI_AR), if an address is necessary (when ADMODE != 00) and if no data needs to be provided by the firmware (when FMODE = 01 or DMODE = 00) 3. a write is performed to DATA[31:0] (QUADSPI_DR), if an address is necessary (when ADMODE != 00) and if data needs to be provided by the firmware (when FMODE = 00 and DMODE != 00) Writes to the alternate byte register (QUADSPI_ABR) never trigger the communication start. If alternate bytes are required, they must be programmed before. As soon as a command is started, the BUSY bit (bit 5 of QUADSPI_SR) is automatically set. FIFO and data management In indirect mode, data go through a 16-byte FIFO which is internal to the QUADSPI. FLEVEL[4:0] (QUADSPI_SR[12:8]) indicates how many bytes are currently being held in the FIFO. In indirect write mode (FMODE = 00), firmware adds data to the FIFO when it writes QUADSPI_DR. Word writes add 4 bytes to the FIFO, halfword writes add 2 bytes, and byte writes add only 1 byte. If firmware adds too many bytes to the FIFO (more than is indicated by DL[31:0]), the extra bytes are flushed from the FIFO at the end of the write operation (when TCF is set). 402/1680 DocID024597 Rev 1 RM0351 QuadSPI interface (QUADSPI) Byte/halfword accesses to QUADSPI_DR must be done only to the least significant byte/halfword of the 32-bit register. FTHRES[3:0] is used to define a FIFO threshold. When the threshold is reached, the FTF (FIFO threshold flag) is set. In indirect read mode, FTF is set when the number of valid bytes to be read from the FIFO is above the threshold. FTF is also set if there are data in the FIFO after the last byte is read from the Flash memory, regardless of the FTHRES setting. In indirect write mode, FTF is set when the number of empty bytes in the FIFO is above the threshold. If FTIE = 1, there is an interrupt when FTF is set. If DMAEN = 1, a DMA transfer is initiated when FTF is set. FTF is cleared by HW as soon as the threshold condition is no longer true (after enough data has been transferred by the CPU or DMA). In indirect read mode when the FIFO becomes full, the QUADSPI temporarily stops reading bytes from the Flash memory to avoid an overrun. Please note that the reading of the Flash memory does not restart until 4 bytes become vacant in the FIFO (when FLEVEL ≤ 11). Thus, when FTHRES ≥ 13, the application must take care to read enough bytes to assure that the QUADSPI will start retrieving data from the Flash memory again. Otherwise, the FTF flag will stay at '0' as long as 11 < FLEVEL < FTHRES. 15.3.5 QUADSPI status flag polling mode In automatic-polling mode, the QUADSPI periodically starts a command to read a defined number of status bytes (up to 4). The received bytes can be masked to isolate some status bits and an interrupt can be generated when the selected bits have a defined value. The accesses to the Flash memory begin in the same way as in indirect read mode: if no address is required (AMODE = 00), accesses begin as soon as the QUADSPI_CCR is written. Otherwise, if an address is required, the first access begins when QUADSPI_AR is written. BUSY goes high at this point and stays high even between the periodic accesses. The contents of MASK[31:0] (QUADSPI_PSMAR) are used to mask the data from the Flash memory in automatic-polling mode. If the MASK[n] = 0, then bit n of the result is masked and not considered. If MASK[n] = 1, and the content of bit[n] is the same as MATCH[n] (QUADSPI_PSMAR), then there is a match for bit n. If the polling match mode bit (PMM, QUADSPI_CR[23]) is 0, then “AND” match mode is activated. This means status match flag (SMF) is set only when there is a match on all of the unmasked bits. If PMM = 1, then “OR” match mode is activated. This means SMF is set if there is a match on any of the unmasked bits. An interrupt is called when SMF is set if SMIE = 1. If the automatic-polling-mode-stop (APMS) bit is set, operation stops and BUSY goes to 0 as soon as a match is detected. Otherwise, BUSY stays at ‘1’ and the periodic accesses continue until there is an abort or the QUADSPI is disabled (EN = 0). The data register (QUADSPI_DR) contains the latest received status bytes (the FIFO is deactivated). The content of the data register is not affected by the masking used in the matching logic. The FTF status bit is set as soon as a new reading of the status is complete, and FTF is cleared as soon as the data is read. DocID024597 Rev 1 403/1680 422 QuadSPI interface (QUADSPI) 15.3.6 RM0351 QUADSPI memory-mapped mode When configured in memory-mapped mode, the external SPI device is seen as an internal memory. It is forbidden to access QUADSPI Flash bank area before having properly configured and enabled the QUADSPI peripheral. No more than 256MB can addressed even if the Flash memory capacity is larger. If an access is made to an address outside of the range defined by FSIZE but still within the 256MB range, then an AHB error is given. The effect of this error depends on the AHB master that attempted the access: • If it is the Cortex® CPU, a hard fault interrupt is generated • If it is a DMA, a DMA transfer error is generated and the corresponding DMA channel is automatically disabled. Byte, halfword, and word access types are all supported. Support for execute in place (XIP) operation is implemented, where the QUADSPI anticipates the next microcontroller access and load in advance the byte at the following address. If the subsequent access is indeed made at a continuous address, the access will be completed faster since the value is already pre-fetched. By default, the QUADSPI never stops its prefetch operation, keeping the previous read operation active with nCS maintained low, even if no access to the Flash memory occurs for a long time. Since Flash memories tend to consume more when nCS is held low, the application might want to activate the timeout counter (TCEN = 1, QUADSPI_CR[3]) so that nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without any access since when the FIFO becomes full with prefetch data. BUSY goes high as soon as the first memory-mapped access occurs. Because of the prefetch operations, BUSY does not fall until there is a timeout, there is an abort, or the peripheral is disabled. 15.3.7 QUADSPI Flash memory configuration The device configuration register (QUADSPI_DCR) can be used to specify the characteristics of the external SPI Flash memory. The FSIZE[4:0] field defines the size of external memory using the following formula: Number of bytes in Flash memory = 2[FSIZE+1] FSIZE+1 is effectively the number of address bits required to address the Flash memory. The Flash memory capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB. When the QUADSPI executes two commands, one immediately after the other, it raises the chip select signal (nCS) high between the two commands for only one CLK cycle by default. If the Flash memory requires more time between commands, the chip select high time (CSHT) field can be used to specify the minimum number of CLK cycles (up to 8) that nCS must remain high. The clock mode (CKMODE) bit indicates the CLK signal logic level in between commands (when nCS = 1). 404/1680 DocID024597 Rev 1 RM0351 15.3.8 QuadSPI interface (QUADSPI) QUADSPI delayed data sampling By default, the QUADSPI samples the data driven by the Flash memory one half of a CLK cycle after the Flash memory drives the signal. In case of external signal delays, it may be beneficial to sample the data later. Using the SSHIFT bit (QUADSPI_CR[4]), the sampling of the data can be shifted by half of a CLK cycle. Clock shifting is not supported in DDR mode: the SSHIFT bit must be clear when DDRM bit is set. 15.3.9 QUADSPI configuration The QUADSPI configuration is done in two phases: • QUADSPI IP configuration • QUADSPI Flash memory configuration Once configured and enabled, the QUADSPI can be used in one of its three operating modes: indirect mode, status-polling mode, or memory-mapped mode. QUADSPI IP configuration The QUADSPI IP is configured using the QUADSPI_CR. The user shall configure the clock prescaler division factor and the sample shifting settings for the incoming data. DDR mode can be set through the DDRM bit. Once enabled, the address and the alternate bytes are sent on both clock edges and the data are sent/received on both clock edges. Regardless of the DDRM bit setting, instructions are always sent in SDR mode. The DMA requests are enabled setting the DMAEN bit. In case of interrupt usage, their respective enable bit can be also set during this phase. FIFO level for either DMA request generation or interrupt generation is programmed in the FTHRES bits. If timeout counter is needed, the TCEN bit can be set and the timeout value programmed in the QUADSPI_LPTR register. QUADSPI Flash memory configuration The parameters related to the targeted external Flash memory are configured through the QUADSPI_DCR register.The user shall program the Flash memory size in the FSIZE bits, the Chip Select minimum high time in the CSHT bits, and the functional mode (Mode 0 or Mode 3) in the MODE bit. 15.3.10 QUADSPI usage The operating mode is selected using FMODE[1:0] (QUADSPI_CCR[27:26]). Indirect mode procedure When FMODE is programmed to 00, indirect write mode is selected and data can be sent to the Flash memory. With FMODE = 01, indirect read mode is selected where data can be read from the Flash memory. When the QUADSPI is used in indirect mode, the frames are constructed in the following way: DocID024597 Rev 1 405/1680 422 QuadSPI interface (QUADSPI) RM0351 1. Specify a number of data bytes to read or write in the QUADSPI_DLR 2. Specify the frame format, mode and instruction code in the QUADSPI_CCR 3. Specify optional alternate byte to be sent right after the address phase in the QUADSPI_ABR 4. Specify the operating mode in the QUADSPI_CR. If FMODE = 00 (indirect write mode) and DMAEN = 1, then QUADSPI_AR should be specified before QUADSPI_CR, because otherwise QUADSPI_DR might be written by the DMA before QUADSPI_AR is updated (if the DMA controller has already been enabled) 5. Specify the targeted address in the QUADSPI_AR 6. Read/Write the data from/to the FIFO through the QUADSPI_DR When writing the control register (QUADSPI_CR) the user specifies the following settings: • The enable bit (EN) set to ‘1’ • The DMA enable bit (DMAEN) for transferring data to/from RAM • Timeout counter enable bit (TCEN) • Sample shift setting (SSHIFT) • FIFO threshold level (FTRHES) to indicate when the FTF flag should be set • Interrupt enables • Automatic polling mode parameters: match mode and stop mode (valid when FMODE = 11) • Clock prescaler When writing the communication configuration register (QUADSPI_CCR) the user specifies the following parameters: • The instruction byte through the INSTRUCTION bits • The way the instruction has to be sent through the IMODE bits (1/2/4 lines) • The way the address has to be sent through the ADMODE bits (None/1/2/4 lines) • The address size (8/16/24/32-bit) through the ADSIZE bits • The way the alternate bytes have to be sent through the ABMODE (None/1/2/4 lines) • The alternate bytes number (1/2/3/4) through the ABSIZE bits • The presence or not of dummy bytes through the DBMODE bit • The number of dummy bytes through the DCYC bits • The way the data have to be sent/received (None/1/2/4 lines) through the DMODE bits If neither the address register (QUADSPI_AR) nor the data register (QUADSPI_DR) need to be updated for a particular command, then the command sequence starts as soon as QUADSPI_CCR is written. This is the case when both ADMODE and DMODE are 00, or if just ADMODE = 00 when in indirect read mode (FMODE = 01). When an address is required (ADMODE is not 00) and the data register does not need to be written (when FMODE = 01 or DMODE = 00), the command sequence starts as soon as the address is updated with a write to QUADSPI_AR. In case of data transmission (FMODE = 00 and DMODE! = 00), the communication start is triggered by a write in the FIFO through QUADSPI_DR. Status flag polling mode The status flag polling mode is enabled setting the FMODE field (QUADSPI_CCR[27:26]) to 10. In this mode, the programmed frame will be sent and the data retrieved periodically. 406/1680 DocID024597 Rev 1 RM0351 QuadSPI interface (QUADSPI) The maximum amount of data read in each frame is 4 bytes. If more data is requested in QUADSPI_DLR, it will be ignored and only 4 bytes will be read. The periodicity is specified in the QUADSPI_PISR register. Once the status data has been retrieved, it can internally be processed i order to: • set the status match flag and generate an interrupt if enabled • stop automatically the periodic retrieving of the status bytes The received value can be masked with the value stored in the QUADSPI_PSMKR and ORed or ANDed with the value stored in the QUADSPI_PSMAR. In case of match, the status match flag is set and an interrupt is generated if enabled, and the QUADSPI can be automatically stopped if the AMPS bit is set. In any case, the latest retrieved value is available in the QUADSPI_DR. Memory-mapped mode In memory-mapped mode, the external Flash memory is seen as internal memory but with some latency during accesses. Only read operations are allowed to the external Flash memory in this mode. Memory-mapped mode is entered by setting the FMODE to 11 in the QUADSPI_CCR register. The programmed instruction and frame is sent when an AHB master is accessing the memory mapped space. The FIFO is used as a prefetch buffer to anticipate linear reads. Any access to QUADSPI_DR in this mode returns zero. The data length register (QUADSPI_DLR) has no meaning in memory-mapped mode. 15.3.11 Sending the instruction only once Some Flash memories (e.g. Winbound) might provide a mode where an instruction must be sent only with the first command sequence, while subsequent commands start directly with the address. One can take advantage of such a feature using the SIOO bit (QUADSPI_CCR[28]). SIOO is valid for all functional modes (indirect, automatic polling, and memory-mapped). If the SIOO bit is set, the instruction is sent only for the first command following a write to QUADSPI_CCR. Subsequent command sequences skip the instruction phase, until there is a write to QUADSPI_CCR. SIOO has no effect when IMODE = 00 (no instruction). 15.3.12 QUADSPI error management A error can be generated in the following case: • In indirect mode or status flag polling mode when a wrong address has been programmed in the QUADSPI_AR (according to the Flash memory size defined by DocID024597 Rev 1 407/1680 422 QuadSPI interface (QUADSPI) RM0351 FSIZE[4:0] in the QUADSPI_DCR): this will set the TEF and an interrupt is generated if enabled. 15.3.13 • Also in indirect mode, if the address plus the data length exceeds the Flash memory size, TEF will be set as soon as the access is triggered. • In memory-mapped mode, when an out of range access is done by an AHB master or when the QUADSPI is disabled: this will generate an AHB error as a response to the faulty AHB request. • When an AHB master is accessing the memory mapped space while the memory mapped mode is disabled: this will generate an AHB error as a response to the faulty AHB request. QUADSPI busy bit and abort functionality Once the QUADSPI starts an operation with the Flash memory, the BUSY bit is automatically set in the QUADSPI_SR. In indirect mode, the BUSY bit is reset once the QUADSPI has completed the requested command sequence and the FIFO is empty. In automatic-polling mode, BUSY goes low only after the last periodic access is complete, due to a match when APMS = 1, or due to an abort. After the first access in memory-mapped mode, BUSY goes low only on a timeout event or on an abort. Any operation can be aborted by setting the ABORT bit in the QUADSPI_CR. Once the abort is completed, the BUSY bit and the ABORT bit are automatically reset, and the FIFO is flushed. Note: Some Flash memories might misbehave if a write operation to a status registers is aborted. 15.3.14 nCS behavior By default, nCS is high, deselecting the external Flash memory. nCS falls before an operation begins and rises as soon as it finishes. When CKMODE = 0 (“mode0”, where CLK stays low when no operation is in progress) nCS falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final rising CLK edge, as shown in Figure 54. Figure 54. nCS when CKMODE = 0 (T = CLK period) 7 7 Q&6 6&/. 069 When CKMODE=1 (“mode3”, where CLK goes high when no operation is in progress) and DDRM=0 (SDR mode), nCS still falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final rising CLK edge, as shown in Figure 55. 408/1680 DocID024597 Rev 1 RM0351 QuadSPI interface (QUADSPI) Figure 55. nCS when CKMODE = 1 in SDR mode (T = CLK period) 7 7 Q&6 6&/. 069 When CKMODE = 1 (“mode3”) and DDRM = 1 (DDR mode), nCS falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final active rising CLK edge, as shown in Figure 56. Because DDR operations must finish with a falling edge, CLK is low when nCS rises, and CLK rises back up one half of a CLK cycle afterwards. Figure 56. nCS when CKMODE = 1 in DDR mode (T = CLK period) 7 7 7 Q&6 6&/. 069 When the FIFO stays full in a read operation or if the FIFO stays empty in a write operation, the operation stalls and CLK stays low until firmware services the FIFO. If an abort occurs when an operation is stalled, nCS rises just after the abort is requested and then CLK rises one half of a CLK cycle later, as shown in Figure 57. Figure 57. nCS when CKMODE = 1 with an abort (T = CLK period) 7 &ORFNVWDOOHG 7 Q&6 6&/. $ERUW 069 DocID024597 Rev 1 409/1680 422 QuadSPI interface (QUADSPI) 15.4 RM0351 QUADSPI interrupts An interrupt can be produced on the following events: • Timeout • Status match • FIFO threshold • Transfer complete • Transfer error Separate interrupt enable bits are available for flexibility. Table 80. QUADSPI interrupt requests Interrupt event 410/1680 Event flag Enable control bit Timeout TOF TOIE Status match SMF SMIE FIFO threshold FTF FTIE Transfer complete TCF TCIE Transfer error TEF TEIE DocID024597 Rev 1 RM0351 QuadSPI interface (QUADSPI) 15.5 QUADSPI registers 15.5.1 QUADSPI control register (QUADSPI_CR) Address offset: 0x0000 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 PRESCALER 23 22 21 20 19 18 17 16 PMM APMS Res. TOIE SMIE FTIE TCIE TEIE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. SSHIFT TCEN rw rw FTHRES rw rw rw rw DMAEN ABORT w1s rw EN w1s Bits 31: 24 PRESCALER[7:0]: Clock prescaler This field defines the scaler factor for generating CLK based on the AHB clock (value+1). 0: FCLK = FAHB, AHB clock used directly as QUADSPI CLK (prescaler bypassed) 1: FCLK = FAHB/2 2: FCLK = FAHB/3 ... 255: FCLK = FAHB/256 For odd clock division factors, CLK’s duty cycle is not 50%. The clock signal remains high one cycle longer than it stays low. This field can be modified only when BUSY = 0. Bit 23 PMM: Polling match mode This bit indicates which method should be used for determining a “match” during automatic polling mode. 0: AND match mode. SMF is set if all the unmasked bits received from the Flash memory match the corresponding bits in the match register. 1: OR match mode. SMF is set if any one of the unmasked bits received from the Flash memory matches its corresponding bit in the match register. This bit can be modified only when BUSY = 0. Bit 22 APMS: Automatic poll mode stop This bit determines if automatic polling is stopped after a match. 0: Automatic polling mode is stopped only by abort or by disabling the QUADSPI. 1: Automatic polling mode stops as soon as there is a match. This bit can be modified only when BUSY = 0. Bit 21 Reserved, must be kept at reset value. Bit 20 TOIE: TimeOut interrupt enable This bit enables the TimeOut interrupt. 0: Interrupt disable 1: Interrupt enabled Bit 19 SMIE: Status match interrupt enable This bit enables the status match interrupt. 0: Interrupt disable 1: Interrupt enabled DocID024597 Rev 1 411/1680 422 QuadSPI interface (QUADSPI) RM0351 Bit 18 FTIE: FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 17 TCIE: Transfer complete interrupt enable This bit enables the transfer complete interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 16 TEIE: Transfer error interrupt enable This bit enables the transfer error interrupt. 0: Interrupt disable 1: Interrupt enabled Bits 15:12 Reserved, must be kept at reset value. Bits 11: 8 FTHRES[3:0] FIFO threshold level Defines, in indirect mode, the threshold number of bytes in the FIFO that will cause the FIFO threshold flag (FTF, QUADSPI_SR[2]) to be set. In indirect write mode (FMODE = 00): 0: FTF is set if there are 1 or more free bytes available to be written to in the FIFO 1: FTF is set if there are 2 or more free bytes available to be written to in the FIFO ... 15: FTF is set if there are 16 free bytes available to be written to in the FIFO In indirect read mode (FMODE = 01): 0: FTF is set if there are 1 or more valid bytes that can be read from the FIFO 1: FTF is set if there are 2 or more valid bytes that can be read from the FIFO ... 15: FTF is set if there are 16 valid bytes that can be read from the FIFO If DMAEN = 1, then the DMA controller for the corresponding channel must be disabled before changing the FTHRES value. Bits 7:5 Reserved, must be kept at reset value. Bit 4 SSHIFT: Sample shift By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the Flash memory. This bit allows the data is to be sampled later in order to account for external signal delays. 0: No shift 1: 1/2 cycle shift Firmware must assure that SSHIFT = 0 when in DDR mode (when DDRM = 1). This field can be modified only when BUSY = 0. 412/1680 DocID024597 Rev 1 RM0351 QuadSPI interface (QUADSPI) Bit 3 TCEN: Timeout counter enable This bit is valid only when memory-mapped mode (FMODE = 11) is selected. Activating this bit causes the chip select (nCS) to be released (and thus reduces consumption) if there has not been an access after a certain amount of time, where this time is defined by TIMEOUT[15:0] (QUADSPI_LPTR). Enable the timeout counter. By default, the QUADSPI never stops its prefetch operation, keeping the previous read operation active with nCS maintained low, even if no access to the Flash memory occurs for a long time. Since Flash memories tend to consume more when nCS is held low, the application might want to activate the timeout counter (TCEN = 1, QUADSPI_CR[3]) so that nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without an access since when the FIFO becomes full with prefetch data. 0: Timeout counter is disabled, and thus the chip select (nCS) remains active indefinitely after an access in memory-mapped mode. 1: Timeout counter is enabled, and thus the chip select is released in memory-mapped mode after TIMEOUT[15:0] cycles of Flash memory inactivity. This bit can be modified only when BUSY = 0. Bit 2 DMAEN: DMA enable In indirect mode, DMA can be used to input or output data via the QUADSPI_DR register. DMA transfers are initiated when the FIFO threshold flag, FTF, is set. 0: DMA is disabled for indirect mode 1: DMA is enabled for indirect mode Bit 1 ABORT: Abort request This bit aborts the on-going command sequence. It is automatically reset once the abort is complete. This bit stops the current transfer. In polling mode or memory-mapped mode, this bit also reset the APM bit or the DM bit. 0: No abort requested 1: Abort requested Bit 0 EN: Enable Enable the QUADSPI. 0: QUADSPI is disabled 1: QUADSPI is enabled 15.5.2 QUADSPI device configuration register (QUADSPI_DCR) Address offset: 0x0004 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 Res. 14 Res. 13 Res. 12 Res. 11 10 Res. 9 8 CSHT rw rw 7 Res. 6 Res. rw DocID024597 Rev 1 5 Res. 20 19 18 17 16 rw FSIZE rw rw rw rw 4 3 2 1 0 Res. CKMODE Res. Res. Res. rw 413/1680 422 QuadSPI interface (QUADSPI) RM0351 Bits 31: 21 Reserved, must be kept at reset value. Bits 20: 16 FSIZE[4:0]: Flash memory size This field defines the size of external memory using the following formula: Number of bytes in Flash memory = 2[FSIZE+1] FSIZE+1 is effectively the number of address bits required to address the Flash memory. The Flash memory capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB. This field can be modified only when BUSY = 0. Bits 15: 11 Reserved, must be kept at reset value. Bits 10:8 CSHT[2:0]: Chip select high time CSHT+1 defines the minimum number of CLK cycles which the chip select (nCS) must remain high between commands issued to the Flash memory. 0: nCS stays high for at least 1 cycle between Flash memory commands 1: nCS stays high for at least 2 cycles between Flash memory commands ... 7: nCS stays high for at least 8 cycles between Flash memory commands This field can be modified only when BUSY = 0. Bits 7: 1 Reserved, must be kept at reset value. Bit 0 CKMODE: Mode 0 / mode 3 This bit indicates the level that CLK takes between commands (when nCS = 1). 0: CLK must stay low while nCS is high (chip select released). This is referred to as mode 0. 1: CLK must stay high while nCS is high (chip select released). This is referred to as mode 3. This field can be modified only when BUSY = 0. 15.5.3 QUADSPI status register (QUADSPI_SR) Address offset: 0x0008 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. BUSY TOF SMF FTF TCF TEF r r r r r r FLEVEL[4:0] r r r r r Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 FLEVEL[4:0]: FIFO level This field gives the number of valid bytes which are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 16 when it is full. In memory-mapped mode and in automatic status polling mode, FLEVEL is zero. Bits 7:6 Reserved, must be kept at reset value. 414/1680 DocID024597 Rev 1 RM0351 QuadSPI interface (QUADSPI) Bit 5 BUSY: Busy This bit is set when an operation is on going. This bit clears automatically when the operation with the Flash memory is finished and the FIFO is empty. Bit 4 TOF: Timeout flag This bit is set when timeout occurs. It is cleared by writing 1 to CTOF. Bit 3 SMF: Status match flag This bit is set in automatic polling mode when the unmasked received data matches the corresponding bits in the match register (QUADSPI_PSMAR). It is cleared by writing 1 to CSMF. Bit 2 FTF: FIFO threshold flag In indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after reads from the Flash memory are complete. It is cleared automatically as soon as threshold condition is no longer true. In automatic polling mode this bit is set every time the status register is read, and the bit is cleared when the data register is read. Bit 1 TCF: Transfer complete flag This bit is set in indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF. Bit 0 TEF: Transfer error flag This bit is set in indirect mode when an invalid address is being accessed in indirect mode. It is cleared by writing 1 to CTEF. 15.5.4 QUADSPI flag clear register (QUADSPI_FCR) Address offset: 0x000C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTOF CSMF Res. CTCF CTEF w1o w1o w1o w1o Bits 31: 4 Reserved, must be kept at reset value. Bit 4 CTOF: Clear timeout flag Writing 1 clears the TOF flag in the QUADSPI_SR register Bit 3 CSMF: Clear status match flag Writing 1 clears the SMF flag in the QUADSPI_SR register Bit 2 Reserved, must be kept at reset value. Bit 1 CTCF: Clear transfer complete flag Writing 1 clears the TCF flag in the QUADSPI_SR register Bit 0 CTEF: Clear transfer error flag Writing 1 clears the TEF flag in the QUADSPI_SR register DocID024597 Rev 1 415/1680 422 QuadSPI interface (QUADSPI) 15.5.5 RM0351 QUADSPI data length register (QUADSPI_DLR) Address offset: 0x0010 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DL[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DL[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 DL[31: 0]: Data length Number of data to be retrieved (value+1) in indirect and status-polling modes. A value no greater than 3 (indicating 4 bytes) should be used for status-polling mode. All 1s in indirect mode means undefined length, where QUADSPI will continue until the end of memory, as defined by FSIZE. 0x0000_0000: 1 byte is to be transferred 0x0000_0001: 2 bytes are to be transferred 0x0000_0002: 3 bytes are to be transferred 0x0000_0003: 4 bytes are to be transferred ... 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred 0xFFFF_FFFF: undefined length -- all bytes until the end of Flash memory (as defined by FSIZE) are to be transferred. Continue reading indefinitely if FSIZE = 0x1F. This field has no effect when in memory-mapped mode (FMODE = 10). This field can be written only when BUSY = 0. 15.5.6 QUADSPI communication configuration register (QUADSPI_CCR) Address offset: 0x0014 Reset value: 0x0000 0000 31 30 29 28 DDRM Res. Res. SIOO rw rw rw rw rw 14 13 12 11 10 9 8 rw 15 ABMODE rw 416/1680 rw ADSIZE rw rw 27 26 25 DMODE FMODE[1:0] ADMODE rw rw 24 23 22 21 Res. 7 rw 19 18 17 DCYC[4:0] 16 ABSIZE rw rw rw rw rw rw rw 6 5 4 3 2 1 0 rw rw rw IMODE rw 20 INSTRUCTION[7:0] rw rw DocID024597 Rev 1 rw rw rw RM0351 QuadSPI interface (QUADSPI) Bit 31 DDRM: Double data rate mode This bit sets the DDR mode for the address, alternate byte and data phase: 0: DDR Mode disabled 1: DDR Mode enabled This field can be written only when BUSY = 0. Bits 30:29 Reserved, must be kept at reset value. Bit 28 SIOO: Send instruction only once mode See Section 15.3.11: Sending the instruction only once on page 407. This bit has no effect when IMODE = 00. 0: Send instruction on every transaction 1: Send instruction only for the first command This field can be written only when BUSY = 0. Bits 27:26 FMODE[1:0]: Functional mode This field defines the QUADSPI functional mode of operation. 00: Indirect write mode 01: Indirect read mode 10: Automatic polling mode 11: Memory-mapped mode If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE value. This field can be written only when BUSY = 0. Bits 25:24 DMODE[1:0]: Data mode This field defines the data phase’s mode of operation: 00: No data 01: Data on a single line 10: Data on two lines 11: Data on four lines This field also determines the dummy phase mode of operation. This field can be written only when BUSY = 0. Bit 23 Reserved, must be kept at reset value. Bits 22:18 DCYC[4:0]: Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DDR modes, it specifies a number of CLK cycles (0-31). This field can be written only when BUSY = 0. Bits 17:16 ABSIZE[1:0]: Alternate bytes size This bit defines alternate bytes size: 00: 8-bit alternate byte 01: 16-bit alternate bytes 10: 24-bit alternate bytes 11: 32-bit alternate bytes This field can be written only when BUSY = 0. Bits 15:14 ABMODE[1:0]: Alternate bytes mode This field defines the alternate-bytes phase mode of operation: 00: No alternate bytes 01: Alternate bytes on a single line 10: Alternate bytes on two lines 11: Alternate bytes on four lines This field can be written only when BUSY = 0. DocID024597 Rev 1 417/1680 422 QuadSPI interface (QUADSPI) RM0351 Bits 13:12 ADSIZE[1:0]: Address size This bit defines address size: 00: 8-bit address 01: 16-bit address 10: 24-bit address 11: 32-bit address This field can be written only when BUSY = 0. Bits 11:10 ADMODE[1:0]: Address mode This field defines the address phase mode of operation: 00: No address 01: Address on a single line 10: Address on two lines 11: Address on four lines This field can be written only when BUSY = 0. Bits 9:8 IMODE[1:0]: Instruction mode This field defines the instruction phase mode of operation: 00: No instruction 01: Instruction on a single line 10: Instruction on two lines 11: Instruction on four lines This field can be written only when BUSY = 0. Bits 7: 0 INSTRUCTION[7: 0]: Instruction Instruction to be send to the external SPI device. This field can be written only when BUSY = 0. 15.5.7 QUADSPI address register (QUADSPI_AR) Address offset: 0x0018 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDRESS[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ADDRESS[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 ADDRESS[31 0]: Address Address to be send to the external Flash memory Writes to this field are ignored when BUSY = 0 or when FMODE = 11 (memory-mapped mode). 15.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR) Address offset: 0x001C Reset value: 0x0000 0000 418/1680 DocID024597 Rev 1 RM0351 31 QuadSPI interface (QUADSPI) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ALTERNATE[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ALTERNATE[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 0 ALTERNATE[31: 0]: Alternate Bytes Optional data to be send to the external SPI device right after the address. This field can be written only when BUSY = 0. 15.5.9 QUADSPI data register (QUADSPI_DR) Address offset: 0x0020 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DATA[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 0 DATA[31: 0]: Data Data to be sent/received to/from the external SPI device. In indirect write mode, data written to this register is stored on the FIFO before it is sent to the Flash memory during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written. In indirect read mode, reading this register gives (via the FIFO) the data which was received from the Flash memory. If the FIFO does not have as many bytes as requested by the read operation and if BUSY=1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first. In automatic polling mode, this register contains the last data read from the Flash memory (without masking). Word, halfword, and byte accesses to this register are supported. In indirect write mode, a byte write adds 1 byte to the FIFO, a halfword write 2, and a word write 4. Similarly, in indirect read mode, a byte read removes 1 byte from the FIFO, a halfword read 2, and a word read 4. Accesses in indirect mode must be aligned to the bottom of this register: a byte read must read DATA[7:0] and a halfword read must read DATA[15:0]. 15.5.10 QUADSPI polling status mask register (QUADSPI _PSMKR) Address offset: 0x0024 Reset value: 0x0000 0000 DocID024597 Rev 1 419/1680 422 QuadSPI interface (QUADSPI) 31 30 29 28 27 RM0351 26 25 24 23 22 21 20 19 18 17 16 MASK[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MASK[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 0 MASK[31: 0]: Status mask Mask to be applied to the status bytes received in polling mode. For bit n: 0: Bit n of the data received in automatic polling mode is masked and its value is not considered in the matching logic 1: Bit n of the data received in automatic polling mode is unmasked and its value is considered in the matching logic This field can be written only when BUSY = 0. 15.5.11 QUADSPI polling status match register (QUADSPI _PSMAR) Address offset: 0x0028 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MATCH[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MATCH[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 0 MATCH[31: 0]: Status match Value to be compared with the masked status register to get a match. This field can be written only when BUSY = 0. 15.5.12 QUADSPI polling interval register (QUADSPI _PIR) Address offset: 0x002C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw INTERVAL[15:0] rw 420/1680 rw rw rw rw rw rw rw rw DocID024597 Rev 1 RM0351 QuadSPI interface (QUADSPI) Bits 31: 16 Reserved, must be kept at reset value. Bits 15: 0 INTERVAL[15: 0]: Polling interval Number of CLK cycles between to read during automatic polling phases. This field can be written only when BUSY = 0. 15.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR) Address offset: 0x0030 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw TIMEOUT[15:0] rw rw rw rw rw rw rw rw rw Bits 31: 16 Reserved, must be kept at reset value. Bits 15: 0 TIMEOUT[15: 0]: Timeout period After each access in memory-mapped mode, the QUADSPI prefetches the subsequent bytes and holds these bytes in the FIFO. This field indicates how many CLK cycles the QUADSPI waits after the FIFO becomes full until it raises nCS, putting the Flash memory in a lower-consumption state. This field can be written only when BUSY = 0. DocID024597 Rev 1 421/1680 422 QuadSPI interface (QUADSPI) 15.5.14 RM0351 QUADSPI register map Reset value 0x0020 0x0024 0 0 0 0 0 0 0 0 0 0 0 0 0 DCYC[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ABORT EN Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTRUCTION[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA[31:0] 0 0 0 MASK[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QUADSPI_PIR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MATCH[31:0] 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 INTERVAL[15:0] 0 Reset value 0 DocID024597 Rev 1 0 0 0 0 TIMEOUT[15:0] 0 0 0 Refer to Section 2.2.2 for the register boundary addresses. 422/1680 Res. TEF 0 ALTERNATE[31:0] QUADSPI_ PSMAR QUADSPI_ LPTR CKMODE TCF 0 ADDRESS[31:0] 0 Reset value 0x0030 TCEN 0 CTEF 0 Res. 0x002C DMAEN FTF 0 CTCF 0 Res. 0x0028 Res. SMF 0 CSMF 0 QUADSPI_ PSMKR Reset value Res. Res. TOF 0 CTOF 0 BUSY 0 Res. 0 IMODE[1:0] 0 QUADSPI_DR Reset value SSHIFT Res. Res. 0 ADMODE[1:0] 0 QUADSPI_ABR Reset value 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 ADSIZE[1:0] 0 ABMODE[1:0] 0 QUADSPI_AR 0x0018 0x001C 0 ABSIZE[1:0] 0 0 Res. Reset value 0 DMODE[1:0] QUADSPI_CCR 0 FMODE[1:0] 0 Res. 0 SIOO Reset value Res. 0x0014 0 DL[31:0] DDRM 0x0010 0 0 Reset value QUADSPI_DLR 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. QUADSPI_FCR 0 FLEVEL[5:0] Reset value 0x000C Res. Res. Res. 0 Res. 0 Res. 0 CSHT Res. 0 0 Res. 0 0 Res. 0 0 Res. Res. 0 Res. Res. FSIZE[4:0] FTHRES [3:0] Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. TEIE Res. Res. 0 Res. Res. Res. Res. Res. Res. QUADSPI_SR Res. Reset value 0x0008 0 Res. QUADSPI_DCR Res. 0x0004 0 Res. 0 FTIE 0 TCIE 0 Res. 0 SMIE 0 Res. 0 Res. 0 Res. 0 TOIE 0 PRESCALER[7:0] Res. 0 QUADSPI_CR 0x0000 Res. PMM APMS Reset value Res. Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 81. QUADSPI register map and reset values 0 0 0 0 0 0 RM0351 Analog-to-digital converters (ADC) 16 Analog-to-digital converters (ADC) 16.1 Introduction This section describes the implementation of up to 3 ADCs • ADC1 and ADC2 are tightly coupled and can operate in dual mode (ADC1 is master). • ADC3 is controlled independently. Each ADC consists of a 12-bit successive approximation analog-to-digital converter. Each ADC has up to 19 multiplexed channels. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit data register. The ADCs are mapped on the AHB bus to allow fast data handling. The analog watchdog features allow the application to detect if the input voltage goes outside the user-defined high or low thresholds. A built-in hardware oversampler allows to improve analog performances while off-loading the related computational burden from the CPU. An efficient low-power mode is implemented to allow very low consumption at low frequency. DocID024597 Rev 1 423/1680 536 Analog-to-digital converters (ADC) 16.2 RM0351 ADC main features • High-performance features – Up to 3x ADCs, out of which two of them can operate in dual mode – ADC1 is connected to 16 external channels + 3 internal channels – ADC2 is connected to 16 external channels + 2 internal channels – ADC3 is connected to 12 external channels + 4 internal channels – 12, 10, 8 or 6-bit configurable resolution – ADC conversion time: Fast channels: 0.188 µs for 12-bit resolution (5.33 Ms/s) Slow channels: 0.238 µs for 12-bit resolution (4.21 Ms/s) • • • • 424/1680 – ADC conversion time is independent from the AHB bus clock frequency – Faster conversion time by lowering resolution: 0.16 µs for 10-bit resolution – Can manage Single-ended or differential inputs (programmable per channels) – AHB slave bus interface to allow fast data handling – Self-calibration – Channel-wise programmable sampling time – Up to four injected channels (analog inputs assignment to regular or injected channels is fully configurable) – Hardware assistant to prepare the context of the injected channels to allow fast context switching – Data alignment with in-built data coherency – Data can be managed by GP-DMA for regular channel conversions – 4 dedicated data registers for the injected channels Oversampler – 16-bit data register – Oversampling ratio adjustable from 2 to 256x – Programmable data shift up to 8-bit Low-power features – Speed adaptive low-power mode to reduce ADC consumption when operating at low frequency – Allows slow bus frequency application while keeping optimum ADC performance (0.188 µs conversion time for fast channels can be kept whatever the AHB bus clock frequency) – Provides automatic control to avoid ADC overrun in low AHB bus clock frequency application (auto-delayed mode) Each ADC features an external analog input channel – Up to 5 fast channels from dedicated GPIO pads – Up to 11 slow channels from dedicated GPIO pads In addition, there are five internal dedicated channels – The internal reference voltage (VREFINT), connected to ADC1 – The internal temperature sensor (VTS), connected to ADC1 and ADC3 – The VBAT monitoring channel (VBAT/3), connected to ADC1 and ADC3 – DAC1 and DAC2 internal channels, connected to ADC2 and ADC3 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) • • Start-of-conversion can be initiated: – by software for both regular and injected conversions – by hardware triggers with configurable polarity (internal timers events or GPIO input events) for both regular and injected conversions Conversion modes – Each ADC can convert a single channel or can scan a sequence of channels – Single mode converts selected inputs once per trigger – Continuous mode converts selected inputs continuously – Discontinuous mode • Dual ADC mode for ADC1 and 2 • Interrupt generation at ADC ready, the end of sampling, the end of conversion (regular or injected), end of sequence conversion (regular or injected), analog watchdog 1, 2 or 3 or overrun events • 3 analog watchdogs per ADC • ADC supply requirements: 1.62 to 3.6 V • ADC input range: VREF– ≤ VIN ≤ VREF+ Figure 58 shows the block diagram of one ADC. DocID024597 Rev 1 425/1680 536 Analog-to-digital converters (ADC) RM0351 16.3 ADC functional description 16.3.1 ADC block diagram Figure 58 shows the ADC block diagram and Table 83 gives the ADC pin description. Figure 58. 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ADC internal signals Signal type Description Inputs Up to 16 external trigger inputs for the regular conversions (can be connected to on-chip timers). These inputs are shared between the ADC master and the ADC slave. JEXT[15:0] Inputs Up to 16 external trigger inputs for the injected conversions (can be connected to on-chip timers). These inputs are shared between the ADC master and the ADC slave. ADC1_AWDx_OUT ADC2_AWDx_OUT ADC3_AWDx_OUT Output Internal analog watchdog output signal connected to on-chip timers. (x = Analog watchdog number 1,2,3) Internal signal name EXT[15:0] VTS Input Output voltage from internal temperature sensor VREFINT Input Output voltage from internal reference voltage VBAT Input supply External battery voltage supply Table 83. ADC pins Name Signal type Comments VREF+ Input, analog reference positive The higher/positive reference voltage for the ADC, 1.62 V ≤ VREF+ ≤ VDDA VDDA Input, analog supply Analog power supply equal VDDA: 1.62 V ≤ VDDA ≤ VDD VREF- Input, analog reference negative The lower/negative reference voltage for the ADC, VREF- = VSSA VSSA Input, analog supply ground Ground for analog power supply equal to VSS VINP[18:0] Positive input analog channels for each ADC Connected either to external channels: ADC_INi or internal channels. VINN[18:0] Negative input analog channels for each ADC Connected to VREF- or external channels: ADC_INi-1 ADCx_IN16:1 External analog input signals Up to 16 analog input channels (x = ADC number = 1,2 or 3): – 5 fast channels – 11 slow channels DocID024597 Rev 1 427/1680 536 Analog-to-digital converters (ADC) 16.3.3 RM0351 Clocks Dual clock domain architecture The dual clock-domain architecture means that the ADCs clock is independent from the AHB bus clock. The input clock is the same for the three ADCs and can be selected between two different clock sources (see Figure 59: ADC clock scheme): a) The ADC clock can be a specific clock source, coming from the system clock, the PLLSAI1 or the PLLSAI2. It can be configured in the RCC to deliver up to 80 MHz (PLL output). Refer to RCC Section for more information on how to generate ADC dedicated clock. To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be reset. b) The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). In this mode, a programmable divider factor can be selected (/1, 2 or 4 according to bits CKMODE[1:0]). To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be different from “00”. Note: For option b), a prescaling factor of 1 (CKMODE[1:0]=01) can be used only if the AHB prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register). Option a) has the advantage of reaching the maximum ADC clock frequency whatever the AHB clock scheme selected. The ADC clock can eventually be divided by the following ratio: 1, 2, 4, 6, 8, 12, 16, 32, 64, 128, 256; using the prescaler configured with bits PRESC[3:0] in the ADCx_CCR register. Option b) has the advantage of bypassing the clock domain resynchronizations. This can be useful when the ADC is triggered by a timer and if the application requires that the ADC is precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is added by the resynchronizations between the two clock domains). 428/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Figure 59. ADC clock scheme 5&& 5HVHWDQG FORFN FRQWUROOHU $'&$'&DQG$'& +&/. $+%LQWHUIDFH %LWV&.02'(>@ RI$'&[B&&5 $QDORJ$'& PDVWHU RURU $'&B&. %LWV35(&>@ RI$'&[B&&5 2WKHUV $QDORJ$'& VODYH $QDORJ$'& VLQJOH %LWV&.02'(>@ RI$'&[B&&5 069 Clock ratio constraint between ADC clock and AHB clock There are generally no constraints to be respected for the ratio between the ADC clock and the AHB clock except if some injected channels are programmed. In this case, it is mandatory to respect the following ratio: • FHCLK >= FADC / 4 if the resolution of all channels are 12-bit or 10-bit • FHCLK >= FADC / 3 if there are some channels with resolutions equal to 8-bit (and none with lower resolutions) • FHCLK >= FADC / 2 if there are some channels with resolutions equal to 6-bit DocID024597 Rev 1 429/1680 536 Analog-to-digital converters (ADC) 16.3.4 RM0351 ADC1/2/3 connectivity ADC1, ADC2 and ADC3 are tightly coupled and share some external channels as described in the below figures. Figure 60. ADC1 connectivity 670/[[ $'& 95(),17 95() $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 95() 976 95() 9%$7 95() 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ &KDQQHOVHOHFWLRQ )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO 6ORZFKDQQHO 95() 6ORZFKDQQHO 9,13 6ORZFKDQQHO 6ORZFKDQQHO 9,11 6$5 $'& 6ORZFKDQQHO 95() 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 069 430/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Figure 61. ADC2 connectivity 670/[[ $'& 5HVHUYHG 95() $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 95() '$&LQWHUQDOFKDQQHO 95() '$&LQWHUQDOFKDQQHO 95() 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ &KDQQHOVHOHFWLRQ )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO 6ORZFKDQQHO 95() 6ORZFKDQQHO 9,13 6ORZFKDQQHO 6ORZFKDQQHO 9,11 6$5 $'& 6ORZFKDQQHO 95() 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 069 DocID024597 Rev 1 431/1680 536 Analog-to-digital converters (ADC) RM0351 Figure 62. ADC3 connectivity 670/[[ $'& 5HVHUYHG 95() $'&B,1 $'&B,1 $'&B,1 $'&B,1 95() 95() 95() $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 $'&B,1 95() '$&LQWHUQDOFKDQQHO 95() '$&LQWHUQDOFKDQQHO 95() 5HVHUYHG 95() 976 95() 9%$7 95() 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ &KDQQHOVHOHFWLRQ )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO 6ORZFKDQQHO 95() 6ORZFKDQQHO 9,13 6ORZFKDQQHO 6ORZFKDQQHO 9,11 6$5 $'& 6ORZFKDQQHO 95() 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 069 432/1680 DocID024597 Rev 1 RM0351 16.3.5 Analog-to-digital converters (ADC) Slave AHB interface The ADCs implement an AHB slave port for control/status register and data access. The features of the AHB interface are listed below: • Word (32-bit) accesses • Single cycle response • Response to all read/write accesses to the registers with zero wait states. The AHB slave interface does not support split/retry requests, and never generates AHB errors. 16.3.6 ADC Deep-Power-Down Mode (DEEPPWD) & ADC Voltage Regulator (ADVREGEN) By default, the ADC is in deep-power-down mode where its supply is internally switched off to reduce the leakage currents (the reset state of bit DEEPPWD is 1 in the ADCx_CR register). To start ADC operations, it is first needed to exit deep-power-down mode by setting bit DEEPPWD=0. Then, it is mandatory to enable the ADC internal voltage regulator by setting the bit ADVREGEN=1 into ADCx_CR register. The software must wait for the startup time of the ADC voltage regulator (TADCVREG_STUP) before launching a calibration or enabling the ADC. This delay must be implemented by software. For the startup time of the ADC voltge regulator, please refer to device datasheet for TADCVREG_STUP parameter. After ADC operations are complete, the ADC can be disabled (ADEN=0). It is possible to save power by also disabling the ADC voltage regulator. This is done by writing bit ADVREGEN=0. Then, to save more power by reducing the leakage currents, it is also possible to re-enter in ADC deep-power-down mode by setting bit DEEPPWD=1 into ADCx_CR register. This is particularly interesting before entering STOP mode. Note: Writing DEEPPWD=1 automatically disables the ADC voltage regulator and bit ADVREGEN is automatically cleared. Note: When the internal voltage regulator is disabled (ADVREGEN=0), the internal analog calibration is kept. In ADC deep-power-down mode (DEEPPWD=1), the internal analog calibration is lost and it is necessary to either relaunch a calibration or re-apply the calibration factor which was previously saved (refer to Section 16.3.8: Calibration (ADCAL, ADCALDIF, ADCx_CALFACT)). 16.3.7 Single-ended and differential input channels Channels can be configured to be either single-ended input or differential input by writing into bits DIFSEL[15:1] in the ADCx_DIFSEL register. This configuration must be written while the ADC is disabled (ADEN=0). Note that DIFSEL[18:16] are fixed to single ended channels (internal channels only) and are always read as 0. In single-ended input mode, the analog voltage to be converted for channel “i” is the difference between the external voltage ADC_INi (positive input) and VREF- (negative input). DocID024597 Rev 1 433/1680 536 Analog-to-digital converters (ADC) RM0351 In differential input mode, the analog voltage to be converted for channel “i” is the difference between the external voltage ADC_INi (positive input) and ADC_INi+1 (negative input). For a complete description of how the input channels are connected for each ADC, refer to Figure 60: ADC1 connectivity to Figure 62: ADC3 connectivity. Caution: When configuring the channel “i” in differential input mode, its negative input voltage is connected to ADC_INi+1. As a consequence, channel “i+1” is no longer usable in singleended mode or in differential mode and must never be configured to be converted. Some channels are shared between ADC1/ADC2/ADC3: this can make the channel on the other ADC unusable. Only exception is interleave mode for ADC master and the slave . Example: Configuring ADC1_IN5 in differential input mode will make ADC12_IN6 not usable: in that case, the channels 6 of both ADC1 and ADC2 must never be converted. Note: Channels 16, 17 and 18 of ADC1/ADC2/ADC3 are forced to single-ended configuration (corresponding bits DIFSEL[i] is always zero), either because connected to a single external analog input or connected to an internal channel. The ADC channels connected to internal voltages must be configured in single-ended mode. 16.3.8 Calibration (ADCAL, ADCALDIF, ADCx_CALFACT) Each ADC provides an automatic calibration procedure which drives all the calibration sequence including the power-on/off sequence of the ADC. During the procedure, the ADC calculates a calibration factor which is 7-bit wide and which is applied internally to the ADC until the next ADC power-off. During the calibration procedure, the application must not use the ADC and must wait until calibration is complete. Calibration is preliminary to any ADC operation. It removes the offset error which may vary from chip to chip due to process or bandgap variation. The calibration factor to be applied for single-ended input conversions is different from the factor to be applied for differential input conversions: • Write ADCALDIF=0 before launching a calibration which will be applied for singleended input conversions. • Write ADCALDIF=1 before launching a calibration which will be applied for differential input conversions. The calibration is then initiated by software by setting bit ADCAL=1. Calibration can only be initiated when the ADC is disabled (when ADEN=0). ADCAL bit stays at 1 during all the calibration sequence. It is then cleared by hardware as soon the calibration completes. At this time, the associated calibration factor is stored internally in the analog ADC and also in the bits CALFACT_S[6:0] or CALFACT_D[6:0] of ADCx_CALFACT register (depending on single-ended or differential input calibration) The internal analog calibration is kept if the ADC is disabled (ADEN=0). However, if the ADC is disabled for extended periods, then it is recommended that a new calibration cycle is run before re-enabling the ADC. The internal analog calibration is lost each time the power of the ADC is removed (example, when the product enters in STANDBY or VBAT mode). In this case, to avoid spending time recalibrating the ADC, it is possible to re-write the calibration factor into the ADCx_CALFACT register without recalibrating, supposing that the software has previously saved the calibration factor delivered during the previous calibration. The calibration factor can be written if the ADC is enabled but not converting (ADEN=1 and ADSTART=0 and JADSTART=0). Then, at the next start of conversion, the calibration factor 434/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) will automatically be injected into the analog ADC. This loading is transparent and does not add any cycle latency to the start of the conversion. It is recommended to recalibrate when VREF+ voltage changed more than 10%. Software procedure to calibrate the ADC 1. Ensure DEEPPWD=0, ADVREGRN=1 and that ADC voltage regulator startup time has elapsed. 2. Ensure that ADEN=0. 3. Select the input mode for this calibration by setting ADCALDIF=0 (Single-ended input) or ADCALDIF=1 (Differential input). 4. Set ADCAL=1. 5. Wait until ADCAL=0. 6. The calibration factor can be read from ADCx_CALFACT register. Figure 63. ADC calibration $'&$/',) 6LQJOHHQGHGLQSXW'LIIHUHQWLDOLQSXW W&$% $'&$/ $'&6WDWH 2)) 6WDUWXS [ &$/)$&7B[>@ E\6: &DOLEUDWH E\+: 2)) &DOLEUDWLRQIDFWRU ,QGLFDWLYHWLPLQJV 06Y9 Software procedure to re-inject a calibration factor into the ADC 1. Ensure ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing). 2. Write CALFACT_S and CALFACT_D with the new calibration factors. 3. When a conversion is launched, the calibration factor will be injected into the analog ADC only if the internal analog calibration factor differs from the one stored in bits CALFACT_S for single-ended input channel or bits CALFACT_D for differential input channel. DocID024597 Rev 1 435/1680 536 Analog-to-digital converters (ADC) RM0351 Figure 64. Updating the ADC calibration factor 5HDG\ QRWFRQYHUWLQJ $'&VWDWH &RQYHUWLQJFKDQQHO 6LQJOHHQGHG 5HDG\ &RQYHUWLQJFKDQQHO 6LQJOHHQGHG 8SGDWLQJFDOLEUDWLRQ ,QWHUQDO FDOLEUDWLRQIDFWRU>@ ) ) 6WDUWFRQYHUVLRQ KDUGZDUHRUVRIZDUH :5,7($'&B&$/)$&7 &$/)$&7B6>@ E\VZ ) E\KZ 06Y9 Converting single-ended and differential analog inputs with a single ADC If the ADC is supposed to convert both differential and single-ended inputs, two calibrations must be performed, one with ADCALDIF=0 and one with ADCALDIF=1. The procedure is the following: 1. Disable the ADC. 2. Calibrate the ADC in single-ended input mode (with ADCALDIF=0). This updates the register CALFACT_S[6:0]. 3. Calibrate the ADC in Differential input modes (with ADCALDIF=1). This updates the register CALFACT_D[6:0]. 4. Enable the ADC, configure the channels and launch the conversions. Each time there is a switch from a single-ended to a differential inputs channel (and vice-versa), the calibration will automatically be injected into the analog ADC. Figure 65. Mixing single-ended and differential channels 7ULJJHUHYHQW $'&VWDWH 5'< &219&+ 5'< &219&+ 5'< &219&+ 5'< 6LQJOHHQGHG LQSXWVFKDQQHO ,QWHUQDO FDOLEUDWLRQIDFWRU>@ ) &$/)$&7B6>@ ) &$/)$&7B'>@ ) 'LIIHUHQWLDO LQSXWVFKDQQHO ) 'LIIHUHQWLDO LQSXWVFKDQQHO &219&+ 6LQJOHLQSXWV FKDQQHO ) 06Y9 436/1680 DocID024597 Rev 1 RM0351 16.3.9 Analog-to-digital converters (ADC) ADC on-off control (ADEN, ADDIS, ADRDY) First of all, follow the procedure explained in Section 16.3.6: ADC Deep-Power-Down Mode (DEEPPWD) & ADC Voltage Regulator (ADVREGEN)). Once DEEPPWD=0 and ADVREGRN=1, the ADC can be enabled and the ADC needs a stabilization time of tSTAB before it starts converting accurately, as shown in Figure 66. Two control bits enable or disable the ADC: • ADEN=1 enables the ADC. The flag ADRDY will be set once the ADC is ready for operation. • ADDIS=1 disables the ADC and disable the ADC. ADEN and ADDIS are then automatically cleared by hardware as soon as the analog ADC is effectively disabled. Regular conversion can then start either by setting ADSTART=1 (refer to Section 16.3.18: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN)) or when an external trigger event occurs, if triggers are enabled. Injected conversions start by setting JADSTART=1 or when an external injected trigger event occurs, if injected triggers are enabled. Software procedure to enable the ADC Caution: 1. Set ADEN=1. 2. Wait until ADRDY=1 (ADRDY is set after the ADC startup time). This can be done using the associated interrupt (setting ADRDYIE=1). ADEN bit cannot be set during ADCAL=1 and 4 ADC clock cycle after the ADCAL bit is cleared by hardware(end of the calibration). Software procedure to disable the ADC 1. Check that both ADSTART=0 and JADSTART=0 to ensure that no conversion is ongoing. If required, stop any regular and injected conversion ongoing by setting ADSTP=1 and JADSTP=1 and then wait until ADSTP=0 and JADSTP=0. 2. Set ADDIS=1. 3. If required by the application, wait until ADEN=0, until the analog ADC is effectively disabled (ADDIS will automatically be reset once ADEN=0). Figure 66. Enabling / Disabling the ADC $'(1 W67$% $'5'< $'',6 $'& VWDW E\6: 2)) 6WDUWXS 5'< &RQYHUWLQJ&+ E\+: 5'< 5(4 2) 2)) 06Y9 DocID024597 Rev 1 437/1680 536 Analog-to-digital converters (ADC) 16.3.10 RM0351 Constraints when writing the ADC control bits The software is allowed to write the RCC control bits to configure and enable the ADC clock (refer to RCC Section), the control bits DIFSEL in the ADCx_DIFSEL register and the control bits ADCAL and ADEN in the ADCx_CR register, only if the ADC is disabled (ADEN must be equal to 0). The software is then allowed to write the control bits ADSTART, JADSTART and ADDIS of the ADCx_CR register only if the ADC is enabled and there is no pending request to disable the ADC (ADEN must be equal to 1 and ADDIS to 0). For all the other control bits of the ADCx_CFGR, ADCx_SMPRx, ADCx_TRx, ADCx_SQRx, ADCx_JDRy, ADCx_OFRy, ADCx_OFCHR and ADCx_IER registers: • For control bits related to configuration of regular conversions, the software is allowed to write them only if the ADC is enabled (ADEN=1) and if there is no regular conversion ongoing (ADSTART must be equal to 0). • For control bits related to configuration of injected conversions, the software is allowed to write them only if the ADC is enabled (ADEN=1) and if there is no injected conversion ongoing (JADSTART must be equal to 0). The software is allowed to write the control bits ADSTP or JADSTP of the ADCx_CR register only if the ADC is enabled and eventually converting and if there is no pending request to disable the ADC (ADSTART or JADSTART must be equal to 1 and ADDIS to 0). The software can write the register ADCx_JSQR at any time, when the ADC is enabled (ADEN=1). Note: There is no hardware protection to prevent these forbidden write accesses and ADC behavior may become in an unknown state. To recover from this situation, the ADC must be disabled (clear ADEN=0 as well as all the bits of ADCx_CR register). 16.3.11 Channel selection (SQRx, JSQRx) There are up to 19 multiplexed channels per ADC: • 5 fast analog inputs coming from GPIO pads (ADC_IN1..5) • Up to 10 slow analog inputs coming from GPIO pads (ADC_IN6..15). Depending on the products, not all of them are available on GPIO pads. • The ADCs are connected to 5 internal analog inputs: – the internal reference voltage (VREFINT) is connected to ADC1_IN0. – the internal temperature sensor (VTS) is connected to ADC1_IN17 and ADC3_IN17. – the VBAT monitoring channel (VBAT/3) is connected to ADC1_IN18 and ADC3_IN18. – the DAC1 internal channel is connected to ADC2_IN17 and ADC3_IN14. – the DAC2 internal channel is connected to ADC2_IN18 and ADC3_IN15. Note: To convert one of the internal analog channels, the corresponding analog sources must first be enabled by programming bits VREFEN, CH17_SEL or CH18_SEL in the ADCx_CCR registers. Caution: Before any conversion of an input channel coming from GPIO pads, it is necessary to configure the corresponding GPIOx_ASCR register in the GPIO, in addition to the I/O configuration in analog mode. 438/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) It is possible to organize the conversions in two groups: regular and injected. A group consists of a sequence of conversions that can be done on any channel and in any order. For instance, it is possible to implement the conversion sequence in the following order: ADC_IN3, ADC_IN8, ADC_IN2, ADC_IN2, ADC_IN0, ADC_IN2, ADC_IN2, ADC_IN15. • A regular group is composed of up to 16 conversions. The regular channels and their order in the conversion sequence must be selected in the ADCx_SQR registers. The total number of conversions in the regular group must be written in the L[3:0] bits in the ADCx_SQR1 register. • An injected group is composed of up to 4 conversions. The injected channels and their order in the conversion sequence must be selected in the ADCx_JSQR register. The total number of conversions in the injected group must be written in the L[1:0] bits in the ADCx_JSQR register. ADCx_SQR registers must not be modified while regular conversions can occur. For this, the ADC regular conversions must be first stopped by writing ADSTP=1 (refer to Section 16.3.17: Stopping an ongoing conversion (ADSTP, JADSTP)). It is possible to modify the ADCx_JSQR registers on-the-fly while injected conversions are occurring. Refer to Section 16.3.21: Queue of context for injected conversions 16.3.12 Channel-wise programmable sampling time (SMPR1, SMPR2) Before starting a conversion, the ADC must establish a direct connection between the voltage source under measurement and the embedded sampling capacitor of the ADC. This sampling time must be enough for the input voltage source to charge the embedded capacitor to the input voltage level. Each channel can be sampled with a different sampling time which is programmable using the SMP[2:0] bits in the ADCx_SMPR1 and ADCx_SMPR2 registers. It is therefore possible to select among the following sampling time values: • SMP = 000: 2.5 ADC clock cycles • SMP = 001: 6.5 ADC clock cycles • SMP = 010: 12.5 ADC clock cycles • SMP = 011: 24.5 ADC clock cycles • SMP = 100: 47.5 ADC clock cycles • SMP = 101: 92.5 ADC clock cycles • SMP = 110: 247.5 ADC clock cycles • SMP = 111: 640.5 ADC clock cycles The total conversion time is calculated as follows: Tconv = Sampling time + 12.5 ADC clock cycles Example: With FADC_CLK = 80 MHz and a sampling time of 2.5 ADC clock cycles: Tconv = (2.5 + 12.5) ADC clock cycles = 15 ADC clock cycles = 187.5 ns (for fast channels) The ADC notifies the end of the sampling phase by setting the status bit EOSMP (only for regular conversion). DocID024597 Rev 1 439/1680 536 Analog-to-digital converters (ADC) RM0351 Constraints on the sampling time for fast and slow channels For each channel, SMP[2:0] bits must be programmed to respect a minimum sampling time as specified in the ADC characteristics section of the datasheets. I/O analog switches voltage booster The I/O analog switches resistance increases when the VDDA voltage is too low. This requires to have the sampling time adapted accordingly (cf datasheet for electrical characteristics). This resistance can be minimized at low VDDA by enabling an internal voltage booster with BOOSTEN bit in the SYSCFG_CFGR1 register. 16.3.13 Single conversion mode (CONT=0) In Single conversion mode, the ADC performs once all the conversions of the channels. This mode is started with the CONT bit at 0 by either: • Setting the ADSTART bit in the ADCx_CR register (for a regular channel) • Setting the JADSTART bit in the ADCx_CR register (for an injected channel) • External hardware trigger event (for a regular or injected channel) Inside the regular sequence, after each conversion is complete: • The converted data are stored into the 16-bit ADCx_DR register • The EOC (end of regular conversion) flag is set • An interrupt is generated if the EOCIE bit is set Inside the injected sequence, after each conversion is complete: • The converted data are stored into one of the four 16-bit ADCx_JDRy registers • The JEOC (end of injected conversion) flag is set • An interrupt is generated if the JEOCIE bit is set After the regular sequence is complete: • The EOS (end of regular sequence) flag is set • An interrupt is generated if the EOSIE bit is set After the injected sequence is complete: • The JEOS (end of injected sequence) flag is set • An interrupt is generated if the JEOSIE bit is set Then the ADC stops until a new external regular or injected trigger occurs or until bit ADSTART or JADSTART is set again. Note: To convert a single channel, program a sequence with a length of 1. 16.3.14 Continuous conversion mode (CONT=1) This mode applies to regular channels only. In continuous conversion mode, when a software or hardware regular trigger event occurs, the ADC performs once all the regular conversions of the channels and then automatically re-starts and continuously converts each conversions of the sequence. This mode is started with the CONT bit at 1 either by external trigger or by setting the ADSTART bit in the ADCx_CR register. 440/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Inside the regular sequence, after each conversion is complete: • The converted data are stored into the 16-bit ADCx_DR register • The EOC (end of conversion) flag is set • An interrupt is generated if the EOCIE bit is set After the sequence of conversions is complete: • The EOS (end of sequence) flag is set • An interrupt is generated if the EOSIE bit is set Then, a new sequence restarts immediately and the ADC continuously repeats the conversion sequence. Note: To convert a single channel, program a sequence with a length of 1. It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1. Injected channels cannot be converted continuously. The only exception is when an injected channel is configured to be converted automatically after regular channels in continuous mode (using JAUTO bit), refer to Auto-injection mode section). 16.3.15 Starting conversions (ADSTART, JADSTART) Software starts ADC regular conversions by setting ADSTART=1. When ADSTART is set, the conversion starts: • Immediately: if EXTEN = 0x0 (software trigger) • At the next active edge of the selected regular hardware trigger: if EXTEN /= 0x0 Software starts ADC injected conversions by setting JADSTART=1. When JADSTART is set, the conversion starts: Note: • Immediately, if JEXTEN = 0x0 (software trigger) • At the next active edge of the selected injected hardware trigger: if JEXTEN /= 0x0 In auto-injection mode (JAUTO=1), use ADSTART bit to start the regular conversions followed by the auto-injected conversions (JADSTART must be kept cleared). ADSTART and JADSTART also provide information on whether any ADC operation is currently ongoing. It is possible to re-configure the ADC while ADSTART=0 and JADSTART=0 are both true, indicating that the ADC is idle. ADSTART is cleared by hardware: • In single mode with software regular trigger (CONT=0, EXTSEL=0x0) – • In all cases (CONT=x, EXTSEL=x) – Note: at any end of regular conversion sequence (EOS assertion) or at any end of subgroup processing if DISCEN = 1 after execution of the ADSTP procedure asserted by the software. In continuous mode (CONT=1), ADSTART is not cleared by hardware with the assertion of EOS because the sequence is automatically relaunched. When a hardware trigger is selected in single mode (CONT=0 and EXTSEL /=0x00), ADSTART is not cleared by hardware with the assertion of EOS to help the software which does not need to reset ADSTART again for the next hardware trigger event. This ensures that no further hardware triggers are missed. DocID024597 Rev 1 441/1680 536 Analog-to-digital converters (ADC) RM0351 JADSTART is cleared by hardware: • in single mode with software injected trigger (JEXTSEL=0x0) – • at any end of injected conversion sequence (JEOS assertion) or at any end of sub-group processing if JDISCEN = 1 in all cases (JEXTSEL=x) – 16.3.16 after execution of the JADSTP procedure asserted by the software. Timing The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution: TADC = TSMPL + TSAR = [ 2.5 |min + 12.5 |12bit ] x TADC_CLK TADC = TSMPL + TSAR = 31.25 ns |min + 156.25 ns |12bit = 187.5 ns (for FADC_CLK = 80 MHz) Figure 67. Analog to digital conversion time $'&VWDWH 5'< 6DPSOLQJ&K 1 $QDORJFKDQQHO &K 1 &K 1 ,QWHUQDO6+ $'67$57 6DPSOLQJ&K 1 &RQYHUWLQJ&K 1 6HW E\6: (2603 +ROG$,1 1 W6$5 6DPSOH$,1 1 W603/ 6HW E\+: &OHDUHG E\6: 6HW E\+: (2& $'&B'5 6DPSOH$,1 1 'DWD1 &OHDUHG E\6: 'DWD1 ,QGLFDWLYHWLPLQJV 069 1. TSMPL depends on SMP[2:0] 2. TSAR depends on RES[2:0] 16.3.17 Stopping an ongoing conversion (ADSTP, JADSTP) The software can decide to stop regular conversions ongoing by setting ADSTP=1 and injected conversions ongoing by setting JADSTP=1. Stopping conversions will reset the ongoing ADC operation. Then the ADC can be reconfigured (ex: changing the channel selection or the trigger) ready for a new operation. Note that it is possible to stop injected conversions while regular conversions are still operating and vice-versa. This allows, for instance, re-configuration of the injected conversion sequence and triggers while regular conversions are still operating (and viceversa). When the ADSTP bit is set by software, any ongoing regular conversion is aborted with partial result discarded (ADCx_DR register is not updated with the current conversion). 442/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) When the JADSTP bit is set by software, any ongoing injected conversion is aborted with partial result discarded (ADCx_JDRy register is not updated with the current conversion). The scan sequence is also aborted and reset (meaning that relaunching the ADC would restart a new sequence). Once this procedure is complete, bits ADSTP/ADSTART (in case of regular conversion), or JADSTP/JADSTART (in case of injected conversion) are cleared by hardware and the software must wait until ADSTART = 0 (or JADSTART = 0) before starting a new conversion. Note: In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (JADSTP must not be used). Figure 68. Stopping ongoing regular conversions 7ULJJHU 7ULJJHU $'&VWDWH 5'< 6DPSOH &K 1 &RQYHUW &K 1 5'< 6DPSOH &K 1 & 5'< -$'67$57 $'67$57 &OHDUHG E\6: &OHDUHG E\+: 5(*8/$5&219(56,216RQJRLQJ VRIWZDUHLVQRWDOORZHGWRFRQILJXUHUHJXODUFRQYHUVLRQVVHOHFWLRQDQGWULJJHUV &OHDUHG E\6: $'673 $'&B'5 'DWD1 &OHDUHG E\+: 'DWD1 069 DocID024597 Rev 1 443/1680 536 Analog-to-digital converters (ADC) RM0351 Figure 69. Stopping ongoing regular and injected conversions 2EGULAR TRIGGER $'&VWDWH 2$9 3AMPLE #H. )NJECTED TRIGGER #ONVERT #H. 2$9 2EGULAR TRIGGER 3AMPLE #H- # 2$9 3AMPL 2$9 #LEARED 3ET *!$34!24 BY 37 BY (7 ).*%#4%$ #/.6%23)/.3 ONGOING SOFTWARE IS NOT ALLOWED TO CONFIGURE INJECTED CONVERSIONS SELECTION AND TRIGGERS 3ET BY 37 *!$340 !$#?*$2 #LEARED BY (7 $!4! - 3ET BY 37 !$34!24 !$340 !$#?$2 #LEARED BY (7 2%'5,!2 #/.6%23)/.3 ONGOING SOFTWARE IS NOT ALLOWED TO CONFIGURE REGULAR CONVERSIONS SELECTION AND TRIGGERS 3ET BY 37 $!4! . #LEARED BY (7 $!4! . 069 16.3.18 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) A conversion or a sequence of conversions can be triggered either by software or by an external event (e.g. timer capture, input pins). If the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 0b00, then external events are able to trigger a conversion with the selected polarity. When the Injected Queue is enabled (bit JQDIS=0), injected software triggers are not possible. The regular trigger selection is effective once software has set bit ADSTART=1 and the injected trigger selection is effective once software has set bit JADSTART=1. Any hardware triggers which occur while a conversion is ongoing are ignored. • If bit ADSTART=0, any regular hardware triggers which occur are ignored. • If bit JADSTART=0, any injected hardware triggers which occur are ignored. Table 84 provides the correspondence between the EXTEN[1:0] and JEXTEN[1:0] values and the trigger polarity. 444/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Table 84. Configuring the trigger polarity for regular external triggers EXTEN[1:0] Note: Source 00 Hardware Trigger detection disabled, software trigger detection enabled 01 Hardware Trigger with detection on the rising edge 10 Hardware Trigger with detection on the falling edge 11 Hardware Trigger with detection on both the rising and falling edges The polarity of the regular trigger cannot be changed on-the-fly. Table 85. Configuring the trigger polarity for injected external triggers Note: JEXTEN[1:0] Source 00 – If JQDIS=1 (Queue disabled): Hardware trigger detection disabled, software trigger detection enabled – If JQDIS=0 (Queue enabled), Hardware and software trigger detection disabled 01 Hardware Trigger with detection on the rising edge 10 Hardware Trigger with detection on the falling edge 11 Hardware Trigger with detection on both the rising and falling edges The polarity of the injected trigger can be anticipated and changed on-the-fly when the queue is enabled (JQDIS=0). Refer to Section 16.3.21: Queue of context for injected conversions. The EXTSEL[3:0] and JEXTSEL[3:0] control bits select which out of 16 possible events can trigger conversion for the regular and injected groups. A regular group conversion can be interrupted by an injected trigger. Note: The regular trigger selection cannot be changed on-the-fly. The injected trigger selection can be anticipated and changed on-the-fly. Refer to Section 16.3.21: Queue of context for injected conversions on page 450 Each ADC master shares the same input triggers with its ADC slave as described in Figure 70. DocID024597 Rev 1 445/1680 536 Analog-to-digital converters (ADC) RM0351 Figure 70. Triggers are shared between ADC master and ADC slave $'&0$67(5 5HJXODU VHTXHQFHU WULJJHUV (;7 (;7 ([WHUQDOUHJXODUWULJJHU (;7 (;76(/>@ ([WHUQDOLQMHFWHGWULJJHU -(;76(/>@ $'&6/$9( ([WHUQDOUHJXODUWULJJHU (;76(/>@ ,QMHFWHG VHTXHQFHU WULJJHUV -(;7 -(;7 -(;7 ([WHUQDOLQMHFWHGWULJJHU -(;76(/>@ 069 Table 86 to Table 87 give all the possible external triggers of the three ADCs for regular and injected conversion. Table 86. ADC1, ADC2 and ADC3 - External triggers for regular channels Name Source Type EXTSEL[3:0] EXT0 TIM1_CC1 event Internal signal from on-chip timers 0000 EXT1 TIM1_CC2 event Internal signal from on-chip timers 0001 EXT2 TIM1_CC3 event Internal signal from on-chip timers 0010 EXT3 TIM2_CC2 event Internal signal from on-chip timers 0011 EXT4 TIM3_TRGO event Internal signal from on-chip timers 0100 EXT5 TIM4_CC4 event Internal signal from on-chip timers 0101 EXT6 EXTI line 11 External pin 0110 EXT7 TIM8_TRGO event Internal signal from on-chip timers 0111 EXT8 TIM8_TRGO2 event Internal signal from on-chip timers 1000 EXT9 TIM1_TRGO event Internal signal from on-chip timers 1001 EXT10 TIM1_TRGO2 event Internal signal from on-chip timers 1010 EXT11 TIM2_TRGO event Internal signal from on-chip timers 1011 EXT12 TIM4_TRGO event Internal signal from on-chip timers 1100 EXT13 TIM6_TRGO event Internal signal from on-chip timers 1101 446/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Table 86. ADC1, ADC2 and ADC3 - External triggers for regular channels (continued) Name Source Type EXTSEL[3:0] EXT14 TIM15_TRGO event Internal signal from on-chip timers 1110 EXT15 TIM3_CC4 event Internal signal from on-chip timers 1111 Table 87. ADC1, ADC2 and ADC3 - External trigger for injected channels Name Source Type JEXTSEL[3..0] JEXT0 TIM1_TRGO event Internal signal from on-chip timers 0000 JEXT1 TIM1_CC4 event Internal signal from on-chip timers 0001 JEXT2 TIM2_TRGO event Internal signal from on-chip timers 0010 JEXT3 TIM2_CC1 event Internal signal from on-chip timers 0011 JEXT4 TIM3_CC4 event Internal signal from on-chip timers 0100 JEXT5 TIM4_TRGO event Internal signal from on-chip timers 0101 JEXT6 EXTI line 15 External pin 0110 JEXT7 TIM8_CC4 event Internal signal from on-chip timers 0111 JEXT8 TIM1_TRGO2 event Internal signal from on-chip timers 1000 JEXT9 TIM8_TRGO event Internal signal from on-chip timers 1001 JEXT10 TIM8_TRGO2 event Internal signal from on-chip timers 1010 JEXT11 TIM3_CC3 event Internal signal from on-chip timers 1011 JEXT12 TIM3_TRGO event Internal signal from on-chip timers 1100 JEXT13 TIM3_CC1 event Internal signal from on-chip timers 1101 JEXT14 TIM6_TRGO event Internal signal from on-chip timers 1110 JEXT15 TIM15_TRGO event Internal signal from on-chip timers 1111 16.3.19 Injected channel management Triggered injection mode To use triggered injection, the JAUTO bit in the ADCx_CFGR register must be cleared. 1. Start the conversion of a group of regular channels either by an external trigger or by setting the ADSTART bit in the ADCx_CR register. 2. If an external injected trigger occurs, or if the JADSTART bit in the ADCx_CR register is set during the conversion of a regular group of channels, the current conversion is reset and the injected channel sequence switches are launched (all the injected channels are converted once). 3. Then, the regular conversion of the regular group of channels is resumed from the last interrupted regular conversion. 4. If a regular event occurs during an injected conversion, the injected conversion is not interrupted but the regular sequence is executed at the end of the injected sequence. Figure 71 shows the corresponding timing diagram. DocID024597 Rev 1 447/1680 536 Analog-to-digital converters (ADC) Note: RM0351 When using triggered injection, one must ensure that the interval between trigger events is longer than the injection sequence. For instance, if the sequence length is 28 ADC clock cycles (that is two conversions with a sampling time of 1.5 clock periods), the minimum interval between triggers must be 29 ADC clock cycles. Auto-injection mode If the JAUTO bit in the ADCx_CFGR register is set, then the channels in the injected group are automatically converted after the regular group of channels. This can be used to convert a sequence of up to 20 conversions programmed in the ADCx_SQR and ADCx_JSQR registers. In this mode, the ADSTART bit in the ADCx_CR register must be set to start regular conversions, followed by injected conversions (JADSTART must be kept cleared). Setting the ADSTP bit aborts both regular and injected conversions (JADSTP bit must not be used). In this mode, external trigger on injected channels must be disabled. If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected channels are continuously converted. Note: It is not possible to use both the auto-injected and discontinuous modes simultaneously. When the DMA is used for exporting regular sequencer’s data in JAUTO mode, it is necessary to program it in circular mode (CIRC bit set in DMA_CCRx register). If the CIRC bit is reset (single-shot mode), the JAUTO sequence will be stopped upon DMA Transfer Complete event. Figure 71. Injected conversion latency !$##,+ ,QMHFWLRQHYHQW 5HVHW$'& PD[ODWHQF\ 62& AIB 1. The maximum latency value can be found in the electrical characteristics of the STM32L4x6 datasheet. 448/1680 DocID024597 Rev 1 RM0351 16.3.20 Analog-to-digital converters (ADC) Discontinuous mode (DISCEN, DISCNUM, JDISCEN) Regular group mode This mode is enabled by setting the DISCEN bit in the ADCx_CFGR register. It is used to convert a short sequence (sub-group) of n conversions (n ≤8) that is part of the sequence of conversions selected in the ADCx_SQR registers. The value of n is specified by writing to the DISCNUM[2:0] bits in the ADCx_CFGR register. When an external trigger occurs, it starts the next n conversions selected in the ADCx_SQR registers until all the conversions in the sequence are done. The total sequence length is defined by the L[3:0] bits in the ADCx_SQR1 register. Example: • • Note: DISCEN=1, n=3, channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10, 11 – 1st trigger: channels converted are 1, 2, 3 (an EOC event is generated at each conversion). – 2nd trigger: channels converted are 6, 7, 8 (an EOC event is generated at each conversion). – 3rd trigger: channels converted are 9, 10, 11 (an EOC event is generated at each conversion) and an EOS event is generated after the conversion of channel 11. – 4th trigger: channels converted are 1, 2, 3 (an EOC event is generated at each conversion). – ... DISCEN=0, channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10,11 – 1st trigger: the complete sequence is converted: channel 1, then 2, 3, 6, 7, 8, 9, 10 and 11. Each conversion generates an EOC event and the last one also generates an EOS event. – all the next trigger events will relaunch the complete sequence. When a regular group is converted in discontinuous mode, no rollover occurs (the last subgroup of the sequence can have less than n conversions). When all subgroups are converted, the next trigger starts the conversion of the first subgroup. In the example above, the 4th trigger reconverts the channels 1, 2 and 3 in the 1st subgroup. It is not possible to have both discontinuous mode and continuous mode enabled. In this case (if DISCEN=1, CONT=1), the ADC behaves as if continuous mode was disabled. Injected group mode This mode is enabled by setting the JDISCEN bit in the ADCx_CFGR register. It converts the sequence selected in the ADCx_JSQR register, channel by channel, after an external injected trigger event. This is equivalent to discontinuous mode for regular channels where ‘n’ is fixed to 1. When an external trigger occurs, it starts the next channel conversions selected in the ADCx_JSQR registers until all the conversions in the sequence are done. The total sequence length is defined by the JL[1:0] bits in the ADCx_JSQR register. DocID024597 Rev 1 449/1680 536 Analog-to-digital converters (ADC) RM0351 Example: • Note: JDISCEN=1, channels to be converted = 1, 2, 3 – 1st trigger: channel 1 converted (a JEOC event is generated) – 2nd trigger: channel 2 converted (a JEOC event is generated) – 3rd trigger: channel 3 converted and a JEOC event + a JEOS event are generated – ... When all injected channels have been converted, the next trigger starts the conversion of the first injected channel. In the example above, the 4th trigger reconverts the 1st injected channel 1. It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. 16.3.21 Queue of context for injected conversions A queue of context is implemented to anticipate up to 2 contexts for the next injected sequence of conversions. JQDIS bit of ADCx_CFGR register must be reset to enable this feature. Only hardware-triggered conversions are possible when the context queue is enabled. This context consists of: • Configuration of the injected triggers (bits JEXTEN[1:0] and JEXTSEL[3:0] in ADCx_JSQR register) • Definition of the injected sequence (bits JSQx[4:0] and JL[1:0] in ADCx_JSQR register) All the parameters of the context are defined into a single register ADCx_JSQR and this register implements a queue of 2 buffers, allowing the bufferization of up to 2 sets of parameters: 450/1680 • The JSQR register can be written at any moment even when injected conversions are ongoing. • Each data written into the JSQR register is stored into the Queue of context. • At the beginning, the Queue is empty and the first write access into the JSQR register immediately changes the context and the ADC is ready to receive injected triggers. • Once an injected sequence is complete, the Queue is consumed and the context changes according to the next JSQR parameters stored in the Queue. This new context is applied for the next injected sequence of conversions. • A Queue overflow occurs when writing into register JSQR while the Queue is full. This overflow is signaled by the assertion of the flag JQOVF. When an overflow occurs, the write access of JSQR register which has created the overflow is ignored and the queue of context is unchanged. An interrupt can be generated if bit JQOVFIE is set. • Two possible behaviors are possible when the Queue becomes empty, depending on the value of the control bit JQM of register ADCx_CFGR: – If JQM=0, the Queue is empty just after enabling the ADC, but then it can never be empty during run operations: the Queue always maintains the last active context and any further valid start of injected sequence will be served according to the last active context. – If JQM=1, the Queue can be empty after the end of an injected sequence or if the Queue is flushed. When this occurs, there is no more context in the queue and DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) hardware triggers are disabled. Therefore, any further hardware injected triggers are ignored until the software re-writes a new injected context into JSQR register. Note: • Reading JSQR register returns the current JSQR context which is active at that moment. When the JSQR context is empty, JSQR is read as 0x0000. • The Queue is flushed when stopping injected conversions by setting JADSTP=1 or when disabling the ADC by setting ADDIS=1: – If JQM=0, the Queue is maintained with the last active context. – If JQM=1, the Queue becomes empty and triggers are ignored. When configured in discontinuous mode (bit JDISCEN=1), only the last trigger of the injected sequence changes the context and consumes the Queue.The 1st trigger only consumes the queue but others are still valid triggers as shown by the discontinuous mode example below (length = 3 for both contexts): • • • • • • 1st trigger, discontinuous. Sequence 1: context 1 consumed, 1st conversion carried out 2nd trigger, disc. Sequence 1: 2nd conversion. 3rd trigger, discontinuous. Sequence 1: 3rd conversion. 4th trigger, discontinuous. Sequence 2: context 2 consumed, 1st conversion carried out. 5th trigger, discontinuous. Sequence 2: 2nd conversion. 6th trigger, discontinuous. Sequence 2: 3rd conversion. Behavior when changing the trigger or sequence context The Figure 72 and Figure 73 show the behavior of the context Queue when changing the sequence or the triggers. Figure 72. Example of JSQR queue of context (sequence change) 3 3 3 :ULWH-645 -645TXHXH (037< 3 $'&-FRQWH[W UHWXUQHGE\UHDGLQJ-465 (037< 3 33 3 3 33 7ULJJHU 3 5'< $'&VWDWH &RQYHUVLRQ &RQYHUVLRQ &RQYHUVLRQ 3 5'< &RQYHUVLRQ 5'< 069 1. Parameters: P1: sequence of 3 conversions, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 4 conversions, hardware trigger 1 Figure 73. Example of JSQR queue of context (trigger change) 3 3 3 :ULWH-645 -645TXHXH (037< 3 33 3 3 33 ,JQRUHG 7ULJJHU ,JQRUHG 7ULJJHU $'&-FRQWH[W (037< UHWXUQHGE\UHDGLQJ-465 $'&VWDWH 3 5'< 3 &RQYHUVLRQ &RQYHUVLRQ 3 5'< &RQYHUVLRQ 5'< 069 1. Parameters: DocID024597 Rev 1 451/1680 536 Analog-to-digital converters (ADC) RM0351 P1: sequence of 2 conversions, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 2 P3: sequence of 4 conversions, hardware trigger 1 Queue of context: Behavior when a queue overflow occurs The Figure 74 and Figure 75 show the behavior of the context Queue if an overflow occurs before or during a conversion. Figure 74. Example of JSQR queue of context with overflow before conversion 3 3 3 :ULWH-645 -645 (037< TXHXH 3 3 !2YHUIORZ LJQRUHG 33 3 33 &OHDUHGE\6: -429) 7ULJJHU 7ULJJHU $'& -FRQWH[W (037< 3 3 UHWXUQHGE\UHDGLQJ-465 5'< $'&VWDWH &RQYHUVLRQ &RQYHUVLRQ 5'< &RQYHUVLRQ -(26 069 1. Parameters: P1: sequence of 2 conversions, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 2 P3: sequence of 3 conversions, hardware trigger 1 P4: sequence of 4 conversions, hardware trigger 1 Figure 75. Example of JSQR queue of context with overflow during conversion 3 3 3 :ULWH-645 -645 (037< TXHXH 3 3 !2YHUIORZ LJQRUHG 33 3 33 &OHDUHGE\6: -429) 7ULJJHU 7ULJJHU $'& -FRQWH[W (037< 3 3 UHWXUQHGE\UHDGLQJ-465 $'&VWDWH 5'< &RQYHUVLRQ &RQYHUVLRQ 5'< &RQYHUVLRQ -(26 069 1. Parameters: P1: sequence of 2 conversions, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 2 P3: sequence of 3 conversions, hardware trigger 1 P4: sequence of 4 conversions, hardware trigger 1 452/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) It is recommended to manage the queue overflows as described below: • After each P context write into JSQR register, flag JQOVF shows if the write has been ignored or not (an interrupt can be generated). • Avoid Queue overflows by writing the third context (P3) only once the flag JEOS of the previous context P2 has been set. This ensures that the previous context has been consumed and that the queue is not full. Queue of context: Behavior when the queue becomes empty Figure 76 and Figure 77 show the behavior of the context Queue when the Queue becomes empty in both cases JQM=0 or 1. Figure 76. Example of JSQR queue of context with empty queue (case JQM=0) 3 7KHTXHXHLVQRWHPSW\ DQGPDLQWDLQV3EHFDXVH-40 3 4XHXHQRWHPSW\ 3PDLQWDLQHG 3 :ULWH-645 33 3 (037< -645TXHXH 3 3 7ULJJHU $'&-FRQWH[W UHWXUQHGE\ (037< UHDGLQJ-465 3 3 &RQYHUVLRQ 5'< $'&VWDWH 3 &RQYHUVLRQ 5'< 5'< &RQYHUVLRQ 5'< &RQYHUVLRQ 5'< &RQY 069 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Note: When writing P3, the context changes immediately. However, because of internal resynchronization, there is a latency and if a trigger occurs just after or before writing P3, it can happen that the conversion is launched considering the context P2. To avoid this situation, the user must ensure that there is no ADC trigger happening when writing a new context that applies immediately. Figure 77. Example of JSQR queue of context with empty queue (case JQM=1) 3 1UEUE BECOMES EMPTY AND TRIGGERS ARE IGNORED BECAUSE *1- 3 3 :ULWH-645 -645 TXHXH (037< 3 33 3 (037< )GNORED )GNORED 7ULJJHU $'& 3 -FRQWH[W (037< UHWXUQHGE\UHDGLQJ-465 $'&VWDWH 3 (037< 3 5'< &RQYHUVLRQ 5'< &RQYHUVLRQ (037< [ 5'< 3 &RQYHUVLRQ (037< 5'< -36 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 DocID024597 Rev 1 453/1680 536 Analog-to-digital converters (ADC) RM0351 Flushing the queue of context The figures below show the behavior of the context Queue in various situations when the queue is flushed. Figure 78. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion. 3 3 4XHXHLVIOXVKHGDQGPDLQWDLQV WKHODVWDFWLYHFRQWH[W 3LVORVW 3 :ULWH-645 -645TXHXH (037< 3 33 3 6HW E\6: -$'673 3 5HVHW E\+: -$'67$57 5HVHW E\+: 6HW E\6: 7ULJJHU $'&-FRQWH[W (037< 3 3 UHWXUQHGE\UHDGLQJ-645 5'< $'&VWDWH &RQYHUVLRQ 5'< 5'< 673 069 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Figure 79. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion and a new trigger occurs. 0 0 7RITE *312 *312 QUEUE %-049 0 1UEUE IS FLUSHED AND MAINTAINS THE LAST ACTIVE CONTEXT 0 0 IS LOST 0 0 3ET BY 37 *!$340 *!$34!24 0 0 0 0 2ESET BY (7 2ESET BY (7 3ET BY 37 4RIGGER !$# * %-049 0 CONTEXT RETURNED BY READING *312 !$# STATE 2$9 0 #ONV 340 !BORTED 2$9 #ONVERSION 2$9 #ONVERSION 2$9 -36 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 454/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Figure 80. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs outside an ongoing conversion 3 WKHODVWDFWLYHFRQWH[W 3LVORVW 3 :ULWH-645 -645TXHXH (037< 33 3 3 6HW E\6: -$'673 3 3 5HVHW E\+: -$'67$57 5HVHW E\+: 6HW E\6: 7ULJJHU $'&-FRQWH[W (037< 3 UHWXUQHGE\UHDGLQJ-645 3 5'< $'&VWDWH &RQYHUVLRQ 5'< 5'< 673 069 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Figure 81. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) 0 1UEUE IS FLUSHED AND BECOMES EMPTY 0 IS LOST 0 0 7RITE *312 *312 QUEUE %-049 0 0 0 %-049 %-049 0 %-049 2ESET BY (7 3ET BY 37 *!$340 *!$34!24 0 2ESET BY (7 3ET BY 37 )GNORED 4RIGGER !$# * CONTEXT %-049 0 RETURNED BY READING *312 !$# STATE 2$9 %-049 X #ONV 340 !BORTED 2$9 #ONVERSION 2$9 -36 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 DocID024597 Rev 1 455/1680 536 Analog-to-digital converters (ADC) RM0351 Figure 82. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0) 1UEUE IS FLUSHED AND MAINTAINS THE LAST ACTIVE CONTEXT 0 WHICH WAS NOT CONSUMED IS LOST 0 0 *312 QUEUE 0 2ESET BY (7 3ET BY 37 !$$)3 0 !$# * CONTEXT RETURNED BY READING *312 !$# STATE 2$9 2%1 /&& /&& -36 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Figure 83. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1) 1UEUE IS FLUSHED AND BEOMES EMPTY *312 IS READ AS X *312 QUEUE 0 0 %-049 3ET BY 37 !$$)3 0 !$# * CONTEXT RETURNED BY READING *312 !$# STATE 2$9 2ESET BY (7 %-049 X 2%1 /&& /&& -36 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Queue of context: Starting the ADC with an empty queue The following procedure must be followed to start ADC operation with an empty queue, in case the first context is not known at the time the ADC is initialized. This procedure is only applicable when JQM bit is reset: 5. Write a dummy JSQR with JEXTEN not equal to 0 (otherwise triggering a software conversion) 6. Set JADSTART 7. Set JADSTP 8. Wait until JADSTART is reset 9. Set JADSTART. Disabling the queue It is possible to disable the queue by setting bit JQDIS=1 into the ADCx_CFGR register. 456/1680 DocID024597 Rev 1 RM0351 16.3.22 Analog-to-digital converters (ADC) Programmable resolution (RES) - fast conversion mode It is possible to perform faster conversion by reducing the ADC resolution. The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the control bits RES[1:0]. Figure 88, Figure 89, Figure 90 and Figure 91 show the conversion result format with respect to the resolution as well as to the data alignment. Lower resolution allows faster conversion time for applications where high-data precision is not required. It reduces the conversion time spent by the successive approximation steps according to Table 88. Table 88. TSAR timings depending on resolution RES (bits) 16.3.23 TSAR (ADC clock cycles) TADC (ADC clock cycles) TSAR (ns) at FADC=80 MHz (with Sampling Time= 2.5 ADC clock cycles) TADC (ns) at FADC=80 MHz 12 12.5 ADC clock cycles 156.25 ns 15 ADC clock cycles 187.5 ns 10 10.5 ADC clock cycles 131.25 ns 13 ADC clock cycles 162.5 ns 8 8.5 ADC clock cycles 106.25 ns 11 ADC clock cycles 137.5 ns 6 6.5 ADC clock cycles 81.25 ns 9 ADC clock cycles 112.5 ns End of conversion, end of sampling phase (EOC, JEOC, EOSMP) The ADC notifies the application for each end of regular conversion (EOC) event and each injected conversion (JEOC) event. The ADC sets the EOC flag as soon as a new regular conversion data is available in the ADCx_DR register. An interrupt can be generated if bit EOCIE is set. EOC flag is cleared by the software either by writing 1 to it or by reading ADCx_DR. The ADC sets the JEOC flag as soon as a new injected conversion data is available in one of the ADCx_JDRy register. An interrupt can be generated if bit JEOCIE is set. JEOC flag is cleared by the software either by writing 1 to it or by reading the corresponding ADCx_JDRy register. The ADC also notifies the end of Sampling phase by setting the status bit EOSMP (for regular conversions only). EOSMP flag is cleared by software by writing 1 to it. An interrupt can be generated if bit EOSMPIE is set. 16.3.24 End of conversion sequence (EOS, JEOS) The ADC notifies the application for each end of regular sequence (EOS) and for each end of injected sequence (JEOS) event. The ADC sets the EOS flag as soon as the last data of the regular conversion sequence is available in the ADCx_DR register. An interrupt can be generated if bit EOSIE is set. EOS flag is cleared by the software either by writing 1 to it. The ADC sets the JEOS flag as soon as the last data of the injected conversion sequence is complete. An interrupt can be generated if bit JEOSIE is set. JEOS flag is cleared by the software either by writing 1 to it. DocID024597 Rev 1 457/1680 536 Analog-to-digital converters (ADC) 16.3.25 RM0351 Timing diagrams example (single/continuous modes, hardware/software triggers) Figure 84. Single conversions of a sequence, software trigger $'67$57 (2& (26 $'&VWDWH 5'< &+ &+ &+ &+ ' ' ' $'&B'5 E\VZ 5'< &+ ' &+ &+ &+ 5'< ' ' ' ' E\KZ ,QGLFDWLYHWLPLQJV 069 1. EXTEN=0x0, CONT=0 2. Channels selected = 1,9, 10, 17; AUTDLY=0. Figure 85. Continuous conversion of a sequence, software trigger $'67$57 (2& (26 $'673 $'&VWDWH 5($'< &+ $'&B'5 E\VZ &+ &+ &+ &+ &+ ' ' ' ' ' &+ 673 5($'< &+ ' &+ ' ,QGLFDWLYHWLPLQJV E\KZ -36 1. EXTEN=0x0, CONT=1 2. Channels selected = 1,9, 10, 17; AUTDLY=0. 458/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Figure 86. Single conversions of a sequence, hardware trigger $'67$57 (2& (26 75*; $'&VWDWH &+ 5'< $'&B'5 E\VZ E\KZ &+ &+ &+ ' ' ' WULJJHUHG 5($'< &+ ' &+ &+ &+ 5'< ' ' ' ' ,QGLFDWLYHWLPLQJV LJQRUHG 069 1. TRGx (over-frequency) is selected as trigger source, EXTEN = 01, CONT = 0 2. Channels selected = 1, 2, 3, 4; AUTDLY=0. Figure 87. Continuous conversions of a sequence, hardware trigger $'67$57 (2& (26 $'673 75*[ $'& 5'< &+ &+ &+ ' $'&B'5 E\VZ E\KZ ' &+ &+ &+ &+ &+ &+ ' ' ' ' ' ' WULJJHUHG LJQRUHG 6723 5'< 1RWLQVFDOHWLPLQJV 069 1. TRGx is selected as trigger source, EXTEN = 10, CONT = 1 2. Channels selected = 1, 2, 3, 4; AUTDLY=0. 16.3.26 Data management Data register, data alignment and offset (ADCx_DR, OFFSETy, OFFSETy_CH, ALIGN) Data and alignment At the end of each regular conversion channel (when EOC event occurs), the result of the converted data is stored into the ADCx_DR data register which is 16 bits wide. At the end of each injected conversion channel (when JEOC event occurs), the result of the converted data is stored into the corresponding ADCx_JDRy data register which is 16 bits wide. The ALIGN bit in the ADCx_CFGR register selects the alignment of the data stored after conversion. Data can be right- or left-aligned as shown in Figure 88, Figure 89, Figure 90 and Figure 91. DocID024597 Rev 1 459/1680 536 Analog-to-digital converters (ADC) RM0351 Special case: when left-aligned, the data are aligned on a half-word basis except when the resolution is set to 6-bit. In that case, the data are aligned on a byte basis as shown in Figure 90 and Figure 91. Note: Left-alignment is not supported in oversampling mode. When ROVSE and/or JOVSE bit is set, the ALIGN bit value is ignored and the ADC only provides right-aligned data. Offset An offset y (y=1,2,3,4) can be applied to a channel by setting the bit OFFSETy_EN=1 into ADCx_OFRy register. The channel to which the offset will be applied is programmed into the bits OFFSETy_CH[4:0] of ADCx_OFRy register. In this case, the converted value is decreased by the user-defined offset written in the bits OFFSETy[11:0]. The result may be a negative value so the read data is signed and the SEXT bit represents the extended sign value. Note: Offset correction is not supported in oversampling mode. When ROVSE and/or JOVSE bit is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset). Table 91 describes how the comparison is performed for all the possible resolutions for analog watchdog 1. Table 89. Offset computation versus data resolution Resolution (bits RES[1:0]) Substraction between raw converted data and offset: Raw converted Data, left aligned Result Comments Offset 00: 12-bit DATA[11:0] OFFSET[11:0] signed 12-bit data - 01: 10-bit DATA[11:2],00 OFFSET[11:0] signed 10-bit data The user must configure OFFSET[1:0] to “00” 10: 8-bit DATA[11:4],00 00 OFFSET[11:0] signed 8-bit data The user must configure OFFSET[3:0] to “0000” 11: 6-bit DATA[11:6],00 0000 OFFSET[11:0] signed 6-bit data The user must configure OFFSET[5:0] to “000000” When reading data from ADCx_DR (regular channel) or from ADCx_JDRy (injected channel, y=1,2,3,4) corresponding to the channel “i”: • If one of the offsets is enabled (bit OFFSETy_EN=1) for the corresponding channel, the read data is signed. • If none of the four offsets is enabled for this channel, the read data is not signed. Figure 88, Figure 89, Figure 90 and Figure 91 show alignments for signed and unsigned data. 460/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Figure 88. Right alignment (offset disabled, unsigned value) ELWGDWD ELW ELW ' ' ' ' ' ' ELWGDWD ELW ' ' ' ' ' ' ' ' ' ' ' ' ' ' ELW ' ' ' ' ' ' ELW ' ELW ELW ELWGDWD ELW ELW ' ELW ELWGDWD ELW ' ' ELW ' ' ' ' ' ' 069 Figure 89. Right alignment (offset enabled, signed value) ELWGDWD ELW 6(;7 6(;7 6(;7 6(;7 ' ELW ' ' ' ELWGDWD ELW ' ' ' ' ' ' ' ' ' ELW ' ' ' ' ' ' ELW 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 ' ELWGDWD ELW ' ELW 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 ELWGDWD ELW ' ELW ' ELW ' ' ' ' ' ' ELW 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 ' ELW ' ' ' ' ' ' 069 DocID024597 Rev 1 461/1680 536 Analog-to-digital converters (ADC) RM0351 Figure 90. Left alignment (offset disabled, unsigned value) ELWGDWD ELW ' ' ELW ' ' ' ' ' ' ELWGDWD ELW ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ELW ELW ELW ELW ELWGDWD ELW ' ELW ELWGDWD ELW ' ' ELW ELW ' ' ' ' ' 069 Figure 91. Left alignment (offset enabled, signed value) ELWGDWD ELW 6(;7 ' ELW ' ' ' ' ' ' ELWGDWD ELW 6(;7 ' ' ELWGDWD ELW ' ' ' ' ELW ' ' ' ' ' ' ELWGDWD ELW 6(;7 ' ELW ' ELW ' ' ELW ' ' ' ' ' ' ' ELW ELW 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 ' ELW ' ' ' ' ' 069 462/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) ADC overrun (OVR, OVRMOD) The overrun flag (OVR) notifies of a buffer overrun event, when the regular converted data was not read (by the CPU or the DMA) before new converted data became available. The OVR flag is set if the EOC flag is still 1 at the time when a new conversion completes. An interrupt can be generated if bit OVRIE=1. When an overrun condition occurs, the ADC is still operating and can continue to convert unless the software decides to stop and reset the sequence by setting bit ADSTP=1. OVR flag is cleared by software by writing 1 to it. It is possible to configure if data is preserved or overwritten when an overrun event occurs by programming the control bit OVRMOD: • OVRMOD=0: The overrun event preserves the data register from being overrun: the old data is maintained and the new conversion is discarded and lost. If OVR remains at 1, any further conversions will occur but the result data will be also discarded. • OVRMOD=1: The data register is overwritten with the last conversion result and the previous unread data is lost. If OVR remains at 1, any further conversions will operate normally and the ADCx_DR register will always contain the latest converted data. Figure 92. Example of overrun (OVR) $'67$57 (2& (26 295 $'673 75*[ $'&VWDWH 5'< &+ &+ &+ &+ &+ $'&B'5UHDGDFFHVV $'&B'5 29502' ' ' ' ' $'&B'5 29502' ' ' ' ' E\VZ &+ &+ ' ' 6723 5'< 2YHUXQ E\KZ WULJJHUHG ,QGLFDWLYHWLPLQJV -36 Note: There is no overrun detection on the injected channels since there is a dedicated data register for each of the four injected channels. Managing a sequence of conversion without using the DMA If the conversions are slow enough, the conversion sequence can be handled by the software. In this case the software must use the EOC flag and its associated interrupt to handle each data. Each time a conversion is complete, EOC is set and the ADCx_DR register can be read. OVRMOD should be configured to 0 to manage overrun events as an error. DocID024597 Rev 1 463/1680 536 Analog-to-digital converters (ADC) RM0351 Managing conversions without using the DMA and without overrun It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). In this case, the OVRMOD bit must be configured to 1 and OVR flag should be ignored by the software. An overrun event will not prevent the ADC from continuing to convert and the ADCx_DR register will always contain the latest conversion. Managing conversions using the DMA Since converted channel values are stored into a unique data register, it is useful to use DMA for conversion of more than one channel. This avoids the loss of the data already stored in the ADCx_DR register. When the DMA mode is enabled (DMAEN bit set to 1 in the ADCx_CFGR register in single ADC mode or MDMA different from 0b00 in dual ADC mode), a DMA request is generated after each conversion of a channel. This allows the transfer of the converted data from the ADCx_DR register to the destination location selected by the software. Despite this, if an overrun occurs (OVR=1) because the DMA could not serve the DMA transfer request in time, the ADC stops generating DMA requests and the data corresponding to the new conversion is not transferred by the DMA. Which means that all the data transferred to the RAM can be considered as valid. Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten (refer to Section : ADC overrun (OVR, OVRMOD)). The DMA transfer requests are blocked until the software clears the OVR bit. Two different DMA modes are proposed depending on the application use and are configured with bit DMACFG of the ADCx_CFGR register in single ADC mode, or with bit DMACFG of the ADCx_CCR register in dual ADC mode: • DMA one shot mode (DMACFG=0). This mode is suitable when the DMA is programmed to transfer a fixed number of data. • DMA circular mode (DMACFG=1) This mode is suitable when programming the DMA in circular mode. DMA one shot mode (DMACFG=0) In this mode, the ADC generates a DMA transfer request each time a new conversion data is available and stops generating DMA requests once the DMA has reached the last DMA transfer (when DMA_EOT interrupt occurs - refer to DMA paragraph) even if a conversion has been started again. When the DMA transfer is complete (all the transfers configured in the DMA controller have been done): 464/1680 • The content of the ADC data register is frozen. • Any ongoing conversion is aborted with partial result discarded. • No new DMA request is issued to the DMA controller. This avoids generating an overrun error if there are still conversions which are started. • Scan sequence is stopped and reset. • The DMA is stopped. DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) DMA circular mode (DMACFG=1) In this mode, the ADC generates a DMA transfer request each time a new conversion data is available in the data register, even if the DMA has reached the last DMA transfer. This allows configuring the DMA in circular mode to handle a continuous analog input data stream. 16.3.27 Dynamic low-power features Auto-delayed conversion mode (AUTDLY) The ADC implements an auto-delayed conversion mode controlled by the AUTDLY configuration bit. Auto-delayed conversions are useful to simplify the software as well as to optimize performance of an application clocked at low frequency where there would be risk of encountering an ADC overrun. When AUTDLY=1, a new conversion can start only if all the previous data of the same group has been treated: • For a regular conversion: once the ADCx_DR register has been read or if the EOC bit has been cleared (see Figure 93). • For an injected conversion: when the JEOS bit has been cleared (see Figure 94). This is a way to automatically adapt the speed of the ADC to the speed of the system which will read the data. The delay is inserted after each regular conversion (whatever DISCEN=0 or 1) and after each sequence of injected conversions (whatever JDISCEN=0 or 1). Note: There is no delay inserted between each conversions of the injected sequence, except after the last one. During a conversion, a hardware trigger event (for the same group of conversions) occurring during this delay is ignored. Note: This is not true for software triggers where it remains possible during this delay to set the bits ADSTART or JADSTART to re-start a conversion: it is up to the software to read the data before launching a new conversion. No delay is inserted between conversions of different groups (a regular conversion followed by an injected conversion or conversely): • If an injected trigger occurs during the automatic delay of a regular conversion, the injected conversion starts immediately (see Figure 94). • Once the injected sequence is complete, the ADC waits for the delay (if not ended) of the previous regular conversion before launching a new regular conversion (see Figure 96). The behavior is slightly different in auto-injected mode (JAUTO=1) where a new regular conversion can start only when the automatic delay of the previous injected sequence of conversion has ended (when JEOS has been cleared). This is to ensure that the software can read all the data of a given sequence before starting a new sequence (see Figure 97). To stop a conversion in continuous auto-injection mode combined with autodelay mode (JAUTO=1, CONT=1 and AUTDLY=1), follow the following procedure: DocID024597 Rev 1 465/1680 536 Analog-to-digital converters (ADC) RM0351 1. Wait until JEOS=1 (no more conversions are restarted) 2. Clear JEOS, 3. Set ADSTP=1 4. Read the regular data. If this procedure is not respected, a new regular sequence can re-start if JEOS is cleared after ADSTP has been set. In AUTDLY mode, a hardware regular trigger event is ignored if it occurs during an already ongoing regular sequence or during the delay that follows the last regular conversion of the sequence. It is however considered pending if it occurs after this delay, even if it occurs during an injected sequence of the delay that follows it. The conversion then starts at the end of the delay of the injected sequence. In AUTDLY mode, a hardware injected trigger event is ignored if it occurs during an already ongoing injected sequence or during the delay that follows the last injected conversion of the sequence. Figure 93. AUTODLY=1, regular conversion in continuous mode, software trigger $'67$57 (2& (26 $'673 $'&B'5UHDGDFFHVV $'&VWDWH 5'< &+ '/< $'&B'5 &+ ' E\VZ '/< &+ ' '/< &+ ' E\KZ '/< 6723 5'< ' ,QGLFDWLYHWLPLQJV 069 1. AUTDLY=1 2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, CHANNELS = 1,2,3 3. Injected configuration DISABLED 466/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Figure 94. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=0; JDISCEN=0) 1RWLJQRUHG RFFXUVGXULQJLQMHFWHGVHTXHQFH ,JQRUHG 5HJXODU WULJJHU $'&VWDWH 5'< &+ '/< &+ '/< &+ UHJXODU UHJXODU '/< &+ &+ &+ LQMHFWHG UHJXODU '/< &+ &+ '/< '/< &+ UHJXODU UHJXODU LQMHFWHG '/< &+ '/< &+ (2& (26 $'&B'5 UHDGDFFHVV ' $'&B'5 ' ' ' ,JQRUHG ,QMHFWHG WULJJHU '/< LQM -(26 ' $'&B-'5 ' $'&B-'5 E\VZ E\KZ ,QGLFDWLYHWLPLQJV 069 1. AUTDLY=1 2. Regular configuration: EXTEN=0x1 (HW trigger), CONT=0, DISCEN=0, CHANNELS = 1, 2, 3 3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=0, CHANNELS = 5,6 DocID024597 Rev 1 467/1680 536 Analog-to-digital converters (ADC) RM0351 Figure 95. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=1, JDISCEN=1) 1RWLJQRUHG RFFXUVGXULQJLQMHFWHGVHTXHQFH ,JQRUHG 5HJXODU WULJJHU $'& VWDWH 5'< &+ UHJXODU &+ '/< 5'< &+ '/< 5'< &+ 5'< &+ '/< 5'< &+ '/< 5'<&+ UHJXODU UHJXODU LQMHFWHG LQMHFWHG UHJXODU UHJXODU '/< &+ '/< &+ '/< &+ '/< &+ (2& (26 $'&B'5UHDGDFFHVV $'&B'5 ' ' ,JQRUHG ,QMHFWHG WULJJHU ' ' ,JQRUHG '/< LQM -(26 $'&B-'5 ' ' $'&B-'5 E\VZ ,QGLFDWLYHWLPLQJV E\KZ 069 1. AUTDLY=1 2. Regular configuration: EXTEN=0x1 (HW trigger), CONT=0, DISCEN=1, DISCNUM=1, CHANNELS = 1, 2, 3. 3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=1, CHANNELS = 5,6 468/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Figure 96. AUTODLY=1, regular continuous conversions interrupted by injected conversions $'67$57 $'& VWDWH 5'< &+ &+ '/< UHJXODU '/< UHJXODU &+ &+ LQMHFWHG LQMHFWHG '/< &+ '/< &+ '/< &+ UHJXODU '/< &+ UHJXODU '/< &+ (2& (26 $'&B'5UHDGDFFHVV ' $'&B'5 ' ' ,JQRUHG ,QMHFWHG WULJJHU '/< LQM -(26 $'&B-'5 ' $'&B-'5 ' E\VZ E\KZ ,QGLFDWLYHWLPLQJV 069 1. AUTDLY=1 2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2, 3 3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=0, CHANNELS = 5,6 Figure 97. AUTODLY=1 in auto- injected mode (JAUTO=1) ^dZd;ϭͿ ƐƚĂƚĞ EŽĚĞůĂLJ Zz ,ϭ >z;,ϭͿ ,Ϯ ƌĞŐƵůĂƌ ƌĞŐƵůĂƌ ,ϱ ŝŶũĞĐƚĞĚ ,ϲ >z;ŝŶũͿ >z;,ϮͿ ,ϯ ƌĞŐƵůĂƌ ŝŶũĞĐƚĞĚ >z ,ϭ ƌĞŐƵůĂƌ K K^ ͺZƌĞĂĚĂĐĐĞƐƐ ͺZ ϭ Ϯ ϯ :K^ ͺ:Zϭ ϱ ϲ ͺ:ZϮ ďLJƐͬǁ ďLJŚͬǁ /ŶĚŝĐĂƚŝǀĞƚŝŵŝŶŐƐ D^ϯϭϬϮϰsϯ 1. AUTDLY=1 2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2 3. Injected configuration: JAUTO=1, CHANNELS = 5,6 DocID024597 Rev 1 469/1680 536 Analog-to-digital converters (ADC) 16.3.28 RM0351 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) The three AWD analog watchdogs monitor whether some channels remain within a configured voltage range (window). Figure 98. Analog watchdog’s guarded area $QDORJYROWDJH +LJKHUWKUHVKROG +75 *XDUGHGDUHD /RZHUWKUHVKROG /75 DL AWDx flag and interrupt An interrupt can be enabled for each of the 3 analog watchdogs by setting AWDxIE in the ADCx_IER register (x=1,2,3). AWDx (x=1,2,3) flag is cleared by software by writing 1 to it. The ADC conversion result is compared to the lower and higher thresholds before alignment. Description of analog watchdog 1 The AWD analog watchdog 1 is enabled by setting the AWD1EN bit in the ADCx_CFGR register. This watchdog monitors whether either one selected channel or all enabled channels(1) remain within a configured voltage range (window). Table 90 shows how the ADCx_CFGR registers should be configured to enable the analog watchdog on one or more channels. Table 90. Analog watchdog channel selection Channels guarded by the analog watchdog AWD1SGL bit AWD1EN bit JAWD1EN bit None x 0 0 All injected channels 0 0 1 All regular channels 0 1 0 All regular and injected channels 0 1 1 1 0 1 1 1 0 1 1 1 (1) Single injected channel Single(1) regular channel (1) Single regular or injected channel 1. Selected by the AWD1CH[4:0] bits. The channels must also be programmed to be converted in the appropriate regular or injected sequence. The AWD1 analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold. 470/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) These thresholds are programmed in bits HT1[11:0] and LT1[11:0] of the ADCx_TR1 register for the analog watchdog 1. When converting data with a resolution of less than 12 bits (according to bits RES[1:0]), the LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data (left aligned). Table 91 describes how the comparison is performed for all the possible resolutions for analog watchdog 1. Table 91. Analog watchdog 1 comparison Resolution (bit RES[1:0]) Analog watchdog comparison between: Comments Raw converted data, (1) left aligned Thresholds 00: 12-bit DATA[11:0] LT1[11:0] and HT1[11:0] - 01: 10-bit DATA[11:2],00 LT1[11:0] and HT1[11:0] User must configure LT1[1:0] and HT1[1:0] to 00 10: 8-bit DATA[11:4],0000 LT1[11:0] and HT1[11:0] User must configure LT1[3:0] and HT1[3:0] to 0000 11: 6-bit DATA[11:6],0000 LT1[11:0] and 00 HT1[11:0] User must configure LT1[5:0] and HT1[5:0] to 000000 1. The watchdog comparison is performed on the raw converted data before any alignment calculation and before applying any offsets (the data which is compared is not signed). Description of analog watchdog 2 and 3 The second and third analog watchdogs are more flexible and can guard several selected channels by programming the corresponding bits in AWDCHx[19:0] (x=2,3). The corresponding watchdog is enabled when any bit of AWDCHx[19:0] (x=2,3) is set. They are limited to a resolution of 8 bits and only the 8 MSBs of the thresholds can be programmed into HTx[7:0] and LTx[7:0]. Table 92 describes how the comparison is performed for all the possible resolutions. Table 92. Analog watchdog 2 and 3 comparison Analog watchdog comparison between: Resolution (bits RES[1:0]) Raw converted data, left aligned(1) Comments Thresholds 00: 12-bit DATA[11:4] LTx[7:0] and HTx[7:0] DATA[3:0] are not relevant for the comparison 01: 10-bit DATA[11:4] LTx[7:0] and HTx[7:0] DATA[3:2] are not relevant for the comparison 10: 8-bit DATA[11:4] LTx[7:0] and HTx[7:0] - 11: 6-bit DATA[11:6],00 LTx[7:0] and HTx[7:0] User must configure LTx[1:0] and HTx[1:0] to 00 1. The watchdog comparison is performed on the raw converted data before any alignment calculation and before applying any offsets (the data which is compared is not signed). DocID024597 Rev 1 471/1680 536 Analog-to-digital converters (ADC) RM0351 ADCy_AWDx_OUT signal output generation Each analog watchdog is associated to an internal hardware signal ADCy_AWDx_OUT (y=ADC number, x=watchdog number) which is directly connected to the ETR input (external trigger) of some on-chip timers. Refer to the on-chip timers section to understand how to select the ADCy_AWDx_OUT signal as ETR. ADCy_AWDx_OUT is activated when the associated analog watchdog is enabled: Note: • ADCy_AWDx_OUT is set when a guarded conversion is outside the programmed thresholds. • ADCy_AWDx_OUT is reset after the end of the next guarded conversion which is inside the programmed thresholds (It remains at 1 if the next guarded conversions are still outside the programmed thresholds). • ADCy_AWDx_OUT is also reset when disabling the ADC (when setting ADDIS=1). Note that stopping regular or injected conversions (setting ADSTP=1 or JADSTP=1) has no influence on the generation of ADCy_AWDx_OUT. AWDx flag is set by hardware and reset by software: AWDx flag has no influence on the generation of ADCy_AWDx_OUT (ex: ADCy_AWDx_OUT can toggle while AWDx flag remains at 1 if the software did not clear the flag). Figure 99. ADCy_AWDx_OUT signal generation (on all regular channels) $'& 67$7( 5'< &RQYHUVLRQ LQVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ LQVLGH &RQYHUVLRQ &RQYHUVLRQ RXWVLGH RXWVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ LQVLGH (2&)/$* $:'[)/$* FOHDUHG E\6: FOHDUHG E\6: FOHDUHG E\6: FOHDUHG E\6: $'&\B$:'[B287 &RQYHUWLQJUHJXODUFKDQQHOV 5HJXODUFKDQQHOVDUHDOOJXDUGHG 069 472/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Figure 100. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by SW) $'& 67$7( 5'< &RQYHUVLRQ &RQYHUVLRQ LQVLGH &RQYHUVLRQ RXWVLGH LQVLGH &RQYHUVLRQ &RQYHUVLRQ RXWVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ RXWVLGH LQVLGH (2&)/$* QRWFOHDUHG E\6: $:'[)/$* $'&\B$:'[B287 &RQYHUWLQJUHJXODUFKDQQHOV 5HJXODUFKDQQHOVDUHDOOJXDUGHG 069 Figure 101. ADCy_AWDx_OUT signal generation (on a single regular channel) $'& &RQYHUVLRQ 67$7( RXWVLGH &RQYHUVLRQ &RQYHUVLRQ &RQYHUVLRQ &RQYHUVLRQ LQVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ &RQYHUVLRQ RXWVLGH (2&)/$* (26)/$* FOHDUHG E\6: $:'[)/$* FOHDUHG E\6: $'&\B$:'[B287 &RQYHUWLQJUHJXODUFKDQQHOVDQG 2QO\FKDQQHOLVJXDUGHG 069 Figure 102. ADCy_AWDx_OUT signal generation (on all injected channels) $'& 67$7( 5'< &RQYHUVLRQ LQVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ &RQYHUVLRQ LQVLGH RXWVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ LQVLGH -(26)/$* $:'[)/$* FOHDUHG E\6: FOHDUHG E\6: FOHDUHG E\6: FOHDUHG E\6: $'&\B$:'[B287 &RQYHUWLQJWKHLQMHFWHGFKDQQHOV $OOLQMHFWHGFKDQQHOVDUHJXDUGHG 069 DocID024597 Rev 1 473/1680 536 Analog-to-digital converters (ADC) 16.3.29 RM0351 Oversampler The oversampling unit performs data pre-processing to offload the CPU. It is able to handle multiple conversions and average them into a single data with increased data width, up to 16-bit. It provides a result with the following form, where N and M can be adjusted: n = N–1 1 Result = ----- × M ∑ Conversion(t n) n=0 It allows to perform by hardware the following functions: averaging, data rate reduction, SNR improvement, basic filtering. The oversampling ratio N is defined using the OVFS[2:0] bits in the ADCx_CFGR2 register, and can range from 2x to 256x. The division coefficient M consists of a right bit shift up to 8 bits, and is defined using the OVSS[3:0] bits in the ADCx_CFGR2 register. The summation unit can yield a result up to 20 bits (256x 12-bit results), which is first shifted right. It is then truncated to the 16 least significant bits, rounded to the nearest value using the least significant bits left apart by the shifting, before being finally transferred into the ADCx_DR data register. Note: If the intermediary result after the shifting exceeds 16-bit, the result is truncated as is, without saturation. Figure 103. 20-bit to 16-bit result truncation 5DZELWGDWD 6KLIWLQJ 7UXQFDWLRQDQGURXQGLQJ 069 The Figure 104 gives a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result. Figure 104. Numerical example with 5-bits shift and rounding 5DZELWGDWD )LQDOUHVXOWDIWHUELWVKLIW DQGURXQGLQJWRQHDUHVW % ' ' % ) 069 The Table 93 below gives the data format for the various N and M combinations, for a raw conversion data equal to 0xFFF. 474/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Table 93. Maximum output results versus N and M (gray cells indicate truncation) Over Max sampling Raw data ratio No-shift OVSS = 0000 1-bit shift OVSS = 0001 2-bit shift OVSS = 0010 3-bit shift OVSS = 0011 4-bit shift OVSS = 0100 5-bit shift OVSS = 0101 6-bit shift OVSS = 0110 7-bit shift OVSS = 0111 8-bit shift OVSS = 1000 2x 0x1FFE 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x020 4x 0x3FFC 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 8x 0x7FF8 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 16x 0xFFF0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 32x 0x1FFE0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 64x 0x3FFC0 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 128x 0x7FF80 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 256x 0xFFF00 0xFF00 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF There are no changes for conversion timings in oversampled mode: the sample time is maintained equal during the whole oversampling sequence. A new data is provided every N conversions, with an equivalent delay equal to N x tADC = N x (tSMPL + tSAR). The flags are set as follow: • the end of the sampling phase (EOSMP) is set after each sampling phase • the end of conversion (EOC) occurs once every N conversions, when the oversampled result is available • the end of sequence (EOS) occurs once the sequence of oversampled data is completed (i.e. after N x sequence length conversions total) Single ADC operating modes support when oversampling In oversampling mode, most of the ADC operating modes are maintained: • Single or continuous mode conversions • ADC conversions start either by software or with triggers • ADC stop during a conversion (abort) • Data read via CPU or DMA with overrun detection • Low-power modes (AUTDLY) • Programmable resolution: in this case, the reduced conversion values (as per RES[1:0] bits in ADCx_CFGR1 register) are accumulated, truncated, rounded and shifted in the same way as 12-bit conversions are Note: The alignment mode is not available when working with oversampled data. The ALIGN bit in ADCx_CFGR1 is ignored and the data are always provided right-aligned. Note: Offset correction is not supported in oversampling mode. When ROVSE and/or JOVSE bit is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset). DocID024597 Rev 1 475/1680 536 Analog-to-digital converters (ADC) RM0351 Analog watchdog The analog watchdog functionality is maintained (AWDSGL and AWDEN bits), with the following difference: Note: – the RES[1:0] bits are ignored, comparison is always done on using the full 12-bit values HT[11:0] and LT[11:0] – the comparison is performed on the most significant 12-bit of the 16-bit oversampled results ADCx_DR[15:4] Care must be taken when using high shifting values, this will reduce the comparison range. For instance, if the oversampled result is shifted by 4 bits, thus yielding a 12-bit data rightaligned, the effective analog watchdog comparison can only be performed on 8 bits. The comparison is done between ADCx_DR[11:4] and HT[0:7] / LT[[0:7], and HT[11:8] / LT[11:8] must be kept reset. Triggered mode The averager can also be used for basic filtering purpose. Although not a very powerful filter (slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject constant parasitic frequencies (typically coming from the mains or from a switched mode power supply). For this purpose, a specific discontinuous mode can be enabled with TROVS bit in ADCx_CFGR2, to be able to have an oversampling frequency defined by a user and independent from the conversion time itself. The Figure 105 below shows how conversions are started in response to triggers during discontinuous mode. If the TROVS bit is set, the content of the DISCEN bit is ignored and considered as 1. Figure 105. Triggered regular oversampling mode (TROVS bit = 1) &217 ',6&(1 75296 7ULJJHU &K 1 7ULJJHU &K 1 &K 1 &K 1 &K 1 &K 1 &K 1 &K 1 (2&IODJVHW &217 ',6&(1 75296 7ULJJHU &K 1 7ULJJHU &K 1 7ULJJHU &K 1 7ULJJHU &K 1 7ULJJHU &K 1 7ULJJHU &K 1 7ULJJHU &K 1 (2&IODJVHW 069 Injected and regular sequencer management when oversampling In oversampling mode, it is possible to have differentiated behavior for injected and regular sequencers. The oversampling can be enabled for both sequencers with some limitations if they have to be used simultaneously (this is related to a unique accumulation unit). 476/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Oversampling regular channels only The regular oversampling mode bit ROVSM defines how the regular oversampling sequence is resumed if it is interrupted by injected conversion: – in continued mode, the accumulation re-starts from the last valid data (prior to the conversion abort request due to the injected trigger). This ensures that oversampling will be completed whatever the injection frequency (providing at least one regular conversion can be completed between triggers); – in resumed mode, the accumulation re-starts from 0 (previous conversions results are ignored). This mode allows to guarantee that all data used for oversampling were converted back-to-back within a single timeslot. Care must be taken to have a injection trigger period above the oversampling period length. If this condition is not respected, the oversampling cannot be completed and the regular sequencer will be blocked. The Figure 106 gives examples for a 4x oversampling ratio. Figure 106. Regular oversampling modes (4x ratio) 2YHUVDPSOLQJ VWRSSHG 5HJXODUFKDQQHOV &K 1 &K 1 &K 1 &K 1 &K 0 7ULJJHU 2YHUVDPSOLQJ FRQWLQXHG &K 0 $ERUW ,QMHFWHGFKDQQHOV &K - &K 0 &K 0 &K 0 &K 2 &K 0 &K 0 &K . -(2& &RQWLQXHGPRGH5296( -296( 52960 75296 ; 2YHUVDPSOLQJ DERUWHG 5HJXODUFKDQQHOV &K 1 &K 1 &K 1 &K 1 &K 0 7ULJJHU 2YHUVDPSOLQJ UHVXPHG &K 0 $ERUW ,QMHFWHGFKDQQHOV &K - &K 0 &K 0 &K . -(2& 5HVXPHGPRGH5296( -296( 52960 75296 ; 069 Oversampling Injected channels only The Injected oversampling mode bit JOVSE enables oversampling solely for conversions in the injected sequencer. DocID024597 Rev 1 477/1680 536 Analog-to-digital converters (ADC) RM0351 Oversampling regular and Injected channels It is possible to have both ROVSE and JOVSE bits set. In this case, the regular oversampling mode is forced to resumed mode (ROVSM bit ignored), as represented on Figure 107 below. Figure 107. Regular and injected oversampling modes used simultaneously 2YHUVDPSOLQJ DERUWHG 5HJXODUFKDQQHOV &K 1 &K 1 &K 1 &K 1 &K 0 2YHUVDPSOLQJ UHVXPHG &K 0 $ERUW 7ULJJHU ,QMHFWHGFKDQQHOV &K - &K 0 &K - &K - &K - &K 0 -(2& 5296( -296( 52960 ;75296 069 Triggered regular oversampling with injected conversions It is possible to have triggered regular mode with injected conversions. In this case, the injected mode oversampling mode must be disabled, and the ROVSM bit is ignored (resumed mode is forced). The JOVSE bit must be reset. The behavior is represented on Figure 108 below. Figure 108. Triggered regular oversampling with injection 2YHUVDPSOLQJ UHVXPHG 7ULJJHU 5HJXODUFKDQQHOV &K 1 7ULJJHU &K 1 7ULJJHU 7ULJJHU 7ULJJHU &K 1 $ERUW ,QMHFWHGFKDQQHOV &K - 7ULJJHU &K 1 &K . 5296( -296( 52960 ;75296 069 Autoinjected mode It is possible to oversample auto-injected sequences and have all conversions results stored in registers to save a DMA resource. This mode is available only with both regular and injected oversampling active: JAUTO = 1, ROVSE = 1 and JOVSE = 1, other combinations are not supported. The ROVSM bit is ignored in auto-injected mode. The Figure 109 below shows how the conversions are sequenced. 478/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Figure 109. Oversampling in auto-injected mode 5HJXODUFKDQQHOV 1 1 1 1 1 1 1 1 ,QMHFWHGFKDQQHOV , , , , - - - - . . . . / / / / -$872 5296( -296( 52960 ;75296 069 It is possible to have also the triggered mode enabled, using the TROVS bit. In this case, the ADC must be configured as following: JAUTO = 1, DISCEN = 0, JDISCEN = 0, ROVSE = 1, JOVSE = 1 and TROVSE = 1. Dual ADC modes support when oversampling It is possible to have oversampling enabled when working in dual ADC configuration, for the injected simultaneous mode and regular simultaneous mode. In this case, the two ADCs must be programmed with the very same settings (including oversampling). All other dual ADC modes are not supported when either regular or injected oversampling is enabled (ROVSE = 1 or JOVSE = 1). Combined modes summary The Table 94 below summarizes all combinations, including modes not supported. Table 94. Oversampler operating modes summary Regular Over- Injected Oversampling sampling ROVSE JOVSE Oversampler mode ROVSM Triggered Regular mode 0 = continued TROVS Comment 1 = resumed 16.3.30 1 0 0 0 Regular continued mode 1 0 0 1 Not supported 1 0 1 0 Regular resumed mode 1 0 1 1 Triggered regular resumed mode 1 1 0 X Not supported 1 1 1 0 Injected and regular resumed mode 1 1 1 1 Not supported 0 1 X X Injected oversampling Dual ADC modes In devices with two ADCs or more, dual ADC modes can be used (see Figure 110): • ADC1 and ADC2 can be used together in dual mode (ADC1 is master) In dual ADC mode the start of conversion is triggered alternately or simultaneously by the ADCx master to the ADC slave, depending on the mode selected by the bits DUAL[4:0] in the ADCx_CCR register. DocID024597 Rev 1 479/1680 536 Analog-to-digital converters (ADC) RM0351 Four possible modes are implemented: • Injected simultaneous mode • Regular simultaneous mode • Interleaved mode • Alternate trigger mode It is also possible to use these modes combined in the following ways: • Injected simultaneous mode + Regular simultaneous mode • Regular simultaneous mode + Alternate trigger mode • Injected simultaneous mode + Interleave mode In dual ADC mode (when bits DUAL[4:0] in ADCx_CCR register are not equal to zero), the bits CONT, AUTDLY, DISCEN, DISCNUM[2:0], JDISCEN, JQM, JAUTO of the ADCx_CFGR register are shared between the master and slave ADC: the bits in the slave ADC are always equal to the corresponding bits of the master ADC. To start a conversion in dual mode, the user must program the bits EXTEN, EXTSEL, JEXTEN, JEXTSEL of the master ADC only, to configure a software or hardware trigger, and a regular or injected trigger. (the bits EXTEN[1:0] and JEXTEN[1:0] of the slave ADC are don’t care). In regular simultaneous or interleaved modes: once the user sets bit ADSTART or bit ADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically set. However, bit ADSTART or bit ADSTP of the slave ADC is not necessary cleared at the same time as the master ADC bit. In injected simultaneous or alternate trigger modes: once the user sets bit JADSTART or bit JADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically set. However, bit JADSTART or bit JADSTP of the slave ADC is not necessary cleared at the same time as the master ADC bit. In dual ADC mode, the converted data of the master and slave ADC can be read in parallel, by reading the ADC common data register (ADCx_CDR). The status bits can be also read in parallel by reading the dual-mode status register (ADCx_CSR). 480/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Figure 110. Dual ADC block diagram(1) 5HJXODUGDWDUHJLVWHU ELWV ,QMHFWHGGDWDUHJLVWHUV [ELWV ,QWHUQDODQDORJLQSXWV $'&[B,1 $GGUHVVGDWDEXV 5HJXODU FKDQQHOV $'&[B,1 6ODYH$'& ,QMHFWHG FKDQQHOV ,QWHUQDOWULJJHUV 5HJXODUGDWDUHJLVWHU ELWV $'&[B,1 ,QMHFWHGGDWDUHJLVWHUV [ELWV ,QWHUQDODQDORJLQSXWV 5HJXODU FKDQQHOV ,QMHFWHG FKDQQHOV 'XDOPRGH FRQWURO 6WDUWWULJJHUPX[ UHJXODUJURXS 0DVWHU$'& 6WDUWWULJJHUPX[ LQMHFWHGJURXS 06Y9 1. External triggers also exist on slave ADC but are not shown for the purposes of this diagram. 2. The ADC common data register (ADCx_CDR) contains both the master and slave ADC regular converted data. DocID024597 Rev 1 481/1680 536 Analog-to-digital converters (ADC) RM0351 Injected simultaneous mode This mode is selected by programming bits DUAL[4:0]=00101 This mode converts an injected group of channels. The external trigger source comes from the injected group multiplexer of the master ADC (selected by the JEXTSEL[3:0] bits in the ADCx_JSQR register). Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel). In simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the longer of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. Regular conversions can be performed on one or all ADCs. In that case, they are independent of each other and are interrupted when an injected event occurs. They are resumed at the end of the injected conversion group. • At the end of injected sequence of conversion event (JEOS) on the master ADC, the converted data is stored into the master ADCx_JDRy registers and a JEOS interrupt is generated (if enabled) • At the end of injected sequence of conversion event (JEOS) on the slave ADC, the converted data is stored into the slave ADCx_JDRy registers and a JEOS interrupt is generated (if enabled) • If the duration of the master injected sequence is equal to the duration of the slave injected one (like in Figure 111), it is possible for the software to enable only one of the two JEOS interrupt (ex: master JEOS) and read both converted data (from master ADCx_JDRy and slave ADCx_JDRy registers). Figure 111. Injected simultaneous mode on 4 channels: dual ADC mode 0$67(5$'& &+ &+ &+ &+ 6/$9($'& &+ &+ &+ &+ 7ULJJHU 6DPSOLQJ (QGRILQMHFWHGVHTXHQFHRQ 0$67(5DQG6/$9($'& &RQYHUVLRQ 069 If JDISCEN=1, each simultaneous conversion of the injected sequence requires an injected trigger event to occur. This mode can be combined with AUTDLY mode: 482/1680 • Once a simultaneous injected sequence of conversions has ended, a new injected trigger event is accepted only if both JEOS bits of the master and the slave ADC have been cleared (delay phase). Any new injected trigger events occurring during the ongoing injected sequence and the associated delay phase are ignored. • Once a regular sequence of conversions of the master ADC has ended, a new regular trigger event of the master ADC is accepted only if the master data register (ADCx_DR) has been read. Any new regular trigger events occurring for the master ADC during the DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) ongoing regular sequence and the associated delay phases are ignored. There is the same behavior for regular sequences occurring on the slave ADC. Regular simultaneous mode with independent injected This mode is selected by programming bits DUAL[4:0] = 00110. This mode is performed on a regular group of channels. The external trigger source comes from the regular group multiplexer of the master ADC (selected by the EXTSEL[3:0] bits in the ADCx_CFGR register). A simultaneous trigger is provided to the slave ADC. In this mode, independent injected conversions are supported. An injection request (either on master or on the slave) will abort the current simultaneous conversions, which are restarted once the injected conversion is completed. Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel). In regular simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the longer conversion time of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. Software is notified by interrupts when it can read the data: • At the end of each conversion event (EOC) on the master ADC, a master EOC interrupt is generated (if EOCIE is enabled) and software can read the ADCx_DR of the master ADC. • At the end of each conversion event (EOC) on the slave ADC, a slave EOC interrupt is generated (if EOCIE is enabled) and software can read the ADCx_DR of the slave ADC. • If the duration of the master regular sequence is equal to the duration of the slave one (like in Figure 112), it is possible for the software to enable only one of the two EOC interrupt (ex: master EOC) and read both converted data from the Common Data register (ADCx_CDR). It is also possible to read the regular data using the DMA. Two methods are possible: • • Using two DMA channels (one for the master and one for the slave). In this case bits MDMA[1:0] must be kept cleared. – Configure the DMA master ADC channel to read ADCx_DR from the master. DMA requests are generated at each EOC event of the master ADC. – Configure the DMA slave ADC channel to read ADCx_DR from the slave. DMA requests are generated at each EOC event of the slave ADC. Using MDMA mode, which leaves one DMA channel free for other uses: – Configure MDMA[1:0]=0b10 or 0b11 (depending on resolution). – A single DMA channel is used (the one of the master). Configure the DMA master ADC channel to read the common ADC register (ADCx_CDR) – A single DMA request is generated each time both master and slave EOC events have occurred. At that time, the slave ADC converted data is available in the upper half-word of the ADCx_CDR 32-bit register and the master ADC converted data is available in the lower half-word of ADCx_CCR register. – both EOC flags are cleared when the DMA reads the ADCx_CCR register. DocID024597 Rev 1 483/1680 536 Analog-to-digital converters (ADC) Note: RM0351 In MDMA mode (MDMA[1:0]=0b10 or 0b11), the user must program the same number of conversions in the master’s sequence as in the slave’s sequence. Otherwise, the remaining conversions will not generate a DMA request. Figure 112. Regular simultaneous mode on 16 channels: dual ADC mode 0$67(5$'& 6/$9($'& &+ &+ &+ &+ &+ &+ &+ &+ &+ &+ 7ULJJHU 6DPSOLQJ (QGRIUHJXODUVHTXHQFHRQ 0$67(5DQG6/$9($'& &RQYHUVLRQ DLE If DISCEN=1 then each “n” simultaneous conversions of the regular sequence require a regular trigger event to occur (“n” is defined by DISCNUM). This mode can be combined with AUTDLY mode: • Once a simultaneous conversion of the sequence has ended, the next conversion in the sequence is started only if the common data register, ADCx_CDR (or the regular data register of the master ADC) has been read (delay phase). • Once a simultaneous regular sequence of conversions has ended, a new regular trigger event is accepted only if the common data register (ADCx_CDR) has been read (delay phase). Any new regular trigger events occurring during the ongoing regular sequence and the associated delay phases are ignored. It is possible to use the DMA to handle data in regular simultaneous mode combined with AUTDLY mode, assuming that multi-DMA mode is used: bits MDMA must be set to 0b10 or 0b11. When regular simultaneous mode is combined with AUTDLY mode, it is mandatory for the user to ensure that: Note: • The number of conversions in the master’s sequence is equal to the number of conversions in the slave’s. • For each simultaneous conversions of the sequence, the length of the conversion of the slave ADC is inferior to the length of the conversion of the master ADC. Note that the length of the sequence depends on the number of channels to convert and the sampling time and the resolution of each channels. This combination of regular simultaneous mode and AUTDLY mode is restricted to the use case when only regular channels are programmed: it is forbidden to program injected channels in this combined mode. Interleaved mode with independent injected This mode is selected by programming bits DUAL[4:0] = 00111. This mode can be started only on a regular group (usually one channel). The external trigger source comes from the regular channel multiplexer of the master ADC. After an external trigger occurs: 484/1680 • The master ADC starts immediately. • The slave ADC starts after a delay of several ADC clock cycles after the sampling phase of the master ADC has complete. DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) The minimum delay which separates 2 conversions in interleaved mode is configured in the DELAY bits in the ADCx_CCR register. This delay starts to count after the end of the sampling phase of the master conversion. This way, an ADC cannot start a conversion if the complementary ADC is still sampling its input (only one ADC can sample the input signal at a given time). • The minimum possible DELAY is 1 to ensure that there is at least one cycle time between the opening of the analog switch of the master ADC sampling phase and the closing of the analog switch of the slave ADC sampling phase. • The maximum DELAY is equal to the number of cycles corresponding to the selected resolution. However the user must properly calculate this delay to ensure that an ADC does not start a conversion while the other ADC is still sampling its input. If the CONT bit is set on both master and slave ADCs, the selected regular channels of both ADCs are continuously converted. Software is notified by interrupts when it can read the data: Note: • At the end of each conversion event (EOC) on the master ADC, a master EOC interrupt is generated (if EOCIE is enabled) and software can read the ADCx_DR of the master ADC. • At the end of each conversion event (EOC) on the slave ADC, a slave EOC interrupt is generated (if EOCIE is enabled) and software can read the ADCx_DR of the slave ADC. It is possible to enable only the EOC interrupt of the slave and read the common data register (ADCx_CDR). But in this case, the user must ensure that the duration of the conversions are compatible to ensure that inside the sequence, a master conversion is always followed by a slave conversion before a new master conversion restarts. It is also possible to have the regular data transferred by DMA. In this case, individual DMA requests on each ADC cannot be used and it is mandatory to use the MDMA mode, as following: • Configure MDMA[1:0]=0b10 or 0b11 (depending on resolution). • A single DMA channel is used (the one of the master). Configure the DMA master ADC channel to read the common ADC register (ADCx_CDR). • A single DMA request is generated each time both master and slave EOC events have occurred. At that time, the slave ADC converted data is available in the upper half-word of the ADCx_CDR 32-bit register and the master ADC converted data is available in the lower half-word of ADCx_CCR register. • Both EOC flags are cleared when the DMA reads the ADCx_CCR register. DocID024597 Rev 1 485/1680 536 Analog-to-digital converters (ADC) RM0351 Figure 113. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode (QGRIFRQYHUVLRQRQPDVWHU$'& 0$67(5$'& &+ &+ 6/$9($'& 7ULJJHU &+ &+ $'&&/. F\FOHV $'&&/. (QGRIFRQYHUVLRQRQVODYH$'& F\FOHV 6DPSOLQJ &RQYHUVLRQ -36 Figure 114. Interleaved mode on 1 channel in single conversion mode: dual ADC mode (QGRIFRQYHUVLRQRQPDVWHU$'& 0$67(5$'& &+ &+ 6/$9($'& 7ULJJHU &+ &+ $'&&/. (QGRIFRQYHUVLRQ RQVODYH$'& F\FOHV 6DPSOLQJ (QGRIFRQYHUVLRQ RQVODYH$'& $'&&/. F\FOHV &RQYHUVLRQ 069 If DISCEN=1, each “n” simultaneous conversions (“n” is defined by DISCNUM) of the regular sequence require a regular trigger event to occur. In this mode, injected conversions are supported. When injection is done (either on master or on slave), both the master and the slave regular conversions are aborted and the sequence is re-started from the master (see Figure 115 below). 486/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Figure 115. Interleaved conversion with injection ,QMHFWHGWULJJHU 5HVXPH DOZD\VRQPDVWHU &+ $'& PDVWHU &+ $'& VODYH &+ &+ 6DPSOLQJ &+ UHDG &'5 /HJHQG &+ &+ &+ UHDG &'5 &+ &+ FRQYHUVLRQV DERUWHG &+ &+ UHDG &'5 &+ UHDG &'5 &RQYHUVLRQ 069 Alternate trigger mode This mode is selected by programming bits DUAL[4:0] = 01001. This mode can be started only on an injected group. The source of external trigger comes from the injected group multiplexer of the master ADC. This mode is only possible when selecting hardware triggers: JEXTEN must not be 0x0. Injected discontinuous mode disabled (JDISCEN=0 for both ADC) 1. When the 1st trigger occurs, all injected master ADC channels in the group are converted. 2. When the 2nd trigger occurs, all injected slave ADC channels in the group are converted. 3. And so on. A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in the group have been converted. A JEOS interrupt, if enabled, is generated after all injected channels of the slave ADC in the group have been converted. JEOC interrupts, if enabled, can also be generated after each injected conversion. If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts by converting the injected channels of the master ADC in the group. DocID024597 Rev 1 487/1680 536 Analog-to-digital converters (ADC) RM0351 Figure 116. Alternate trigger: injected group of each ADC -(2&RQ PDVWHU$'& VWWULJJHU -(2&RQ PDVWHU$'& -(2&-(26RQ PDVWHU$'& 0$67(5$'& 6/$9($'& QGWULJJHU -(2&RQ VODYH$'& UGWULJJHU -(2&RQ VODYH$'& -(2&-(26RQ VODYH$'& -(2&RQ PDVWHU$'& -(2&RQ PDVWHU$'& -(2&-(26RQ PDVWHU$'& 0$67(5$'& 6/$9($'& WKWULJJHU -(2&RQ VODYH$'& -(2&RQ VODYH$'& -(2&-(26RQ VODYH$'& 6DPSOLQJ &RQYHUVLRQ DLP Note: Regular conversions can be enabled on one or all ADCs. In this case the regular conversions are independent of each other. A regular conversion is interrupted when the ADC has to perform an injected conversion. It is resumed when the injected conversion is finished. The time interval between 2 trigger events must be greater than or equal to 1 ADC clock period. The minimum time interval between 2 trigger events that start conversions on the same ADC is the same as in the single ADC mode. Injected discontinuous mode enabled (JDISCEN=1 for both ADC) If the injected discontinuous mode is enabled for both master and slave ADCs: • When the 1st trigger occurs, the first injected channel of the master ADC is converted. • When the 2nd trigger occurs, the first injected channel of the slave ADC is converted. • And so on. A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in the group have been converted. A JEOS interrupt, if enabled, is generated after all injected channels of the slave ADC in the group have been converted. JEOC interrupts, if enabled, can also be generated after each injected conversions. If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts. 488/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Figure 117. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode VWWULJJHU UGWULJJHU WKWULJJHU WKWULJJHU -(2&-(26RQ -(2&RQ -(2&RQ -(2&RQ PDVWHU$'& PDVWHU$'& PDVWHU$'& PDVWHU$'& 0$67(5$'& 6/$9($'& -(2&RQ PDVWHU$'& QGWULJJHU -(2&RQ PDVWHU$'& WKWULJJHU -(2&RQ PDVWHU$'& WKWULJJHU WKWULJJHU -(2&-(26RQ PDVWHU$'& 6DPSOLQJ &RQYHUVLRQ DL9P Combined regular/injected simultaneous mode This mode is selected by programming bits DUAL[4:0] = 00001. It is possible to interrupt the simultaneous conversion of a regular group to start the simultaneous conversion of an injected group. Note: In combined regular/injected simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the long conversion time of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. Combined regular simultaneous + alternate trigger mode This mode is selected by programming bits DUAL[4:0]=00010. It is possible to interrupt the simultaneous conversion of a regular group to start the alternate trigger conversion of an injected group. Figure 118 shows the behavior of an alternate trigger interrupting a simultaneous regular conversion. The injected alternate conversion is immediately started after the injected event. If a regular conversion is already running, in order to ensure synchronization after the injected conversion, the regular conversion of all (master/slave) ADCs is stopped and resumed synchronously at the end of the injected conversion. Note: In combined regular simultaneous + alternate trigger mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the long conversion time of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. DocID024597 Rev 1 489/1680 536 Analog-to-digital converters (ADC) RM0351 Figure 118. Alternate + regular simultaneous VWWULJJHU $'&0$67(5UHJ &+ &+ &+ &+ &+ &+ &+ &+ &+ &+ &+ $'&0$67(5LQM $'&6/$9(UHJ &+ &+ &+ &+ &+ $'&6/$9(LQM V\QFKURQRWORVW QGWULJJHU DL9P If a trigger occurs during an injected conversion that has interrupted a regular conversion, the alternate trigger is served. Figure 119 shows the behavior in this case (note that the 6th trigger is ignored because the associated alternate conversion is not complete). Figure 119. Case of trigger occurring during injected conversion VWWULJJHU $'&0$67(5UHJ &+ &+ &+ &+ $'&0$67(5LQM $'&6/$9(UHJ $'&6/$9(LQM UGWULJJHU &+ &+ &+ &+ &+ &+ &+ &+ WKWULJJHU &+ &+ &+ QGWULJJHU &+ &+ &+ &+ &+ &+ &+ &+ WKWULJJHU WKWULJJHU LJQRUHG DL9 Combined injected simultaneous plus interleaved This mode is selected by programming bits DUAL[4:0]=00011 It is possible to interrupt an interleaved conversion with a simultaneous injected event. Caution: 490/1680 In this case the interleaved conversion is interrupted immediately and the simultaneous injected conversion starts. At the end of the injected sequence the interleaved conversion is resumed. When the interleaved regular conversion resumes, the first regular conversion which is performed is alway the master’s one. Figure 120, Figure 121 and Figure 122 show the behavior using an example. In this mode, it is mandatory to use the Common Data Register to read the regular data with a single read access. On the contrary, master-slave data coherency is not guaranteed. DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Figure 120. Interleaved single channel CH0 with injected sequence CH11, CH12 $'& PDVWHU &+ &+ $'& VODYH &+ &+ &RQYHUVLRQV DERUWHG &+ UHDG &'5 &+ &+ UHDG &'5 &+ &+ &+ &+ &+ &+ &+ &+ UHDG &'5 &+ UHDG &'5 /HJHQG ,QMHFWHGWULJJHU 6DPSOLQJ 5HVXPH DOZD\VUHVWDUWZLWKWKHPDVWHU &RQYHUVLRQ 069 Figure 121. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 1: Master interrupted first $'& PDVWHU &+ &+ $'& VODYH &+ &+ &RQYHUVLRQV DERUWHG &+ UHDG &'5 &+ &+ UHDG &'5 &+ &+ &+ &+ &+ &+ &+ &+ UHDG &'5 &+ UHDG &'5 /HJHQG ,QMHFWHGWULJJHU 6DPSOLQJ 5HVXPH DOZD\VUHVWDUWZLWKWKHPDVWHU &RQYHUVLRQ 069 Figure 122. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 2: Slave interrupted first $'& PDVWHU &+ $'& VODYH &+ &+ &+ &RQYHUVLRQV DERUWHG &+ UHDG &'5 &+ UHDG &'5 &+ &+ &+ &+ &+ &+ &+ &+ &+ UHDG &'5 &+ UHDG &'5 /HJHQG ,QMHFWHGWULJJHU 6DPSOLQJ &RQYHUVLRQ 5HVXPH DOZD\VUHVWDUWZLWKWKHPDVWHU 069 DocID024597 Rev 1 491/1680 536 Analog-to-digital converters (ADC) RM0351 DMA requests in dual ADC mode In all dual ADC modes, it is possible to use two DMA channels (one for the master, one for the slave) to transfer the data, like in single mode (refer to Figure 123: DMA Requests in regular simultaneous mode when MDMA=0b00). Figure 123. DMA Requests in regular simultaneous mode when MDMA=0b00 7ULJJHU $'&0DVWHUUHJXODU 7ULJJHU &+ &+ $'&0DVWHU(2& $'&6ODYHUHJXODU &+ &+ $'&6ODYH(2& '0$UHTXHVWIURP$'&0DVWHU '0$UHDGV0DVWHU $'&B'5 '0$UHDGV0DWHU $'&B'5 '0$UHTXHVWIURP$'&6ODYH '0$UHDGV6ODYH $'&B'5 '0$UHDGV6ODYH $'&B'5 &RQILJXUDWLRQZKHUHHDFKVHTXHQFHFRQWDLQVRQO\RQHFRQYHUVLRQ 06Y9 In simultaneous regular and interleaved modes, it is also possible to save one DMA channel and transfer both data using a single DMA channel. For this MDMA bits must be configured in the ADCx_CCR register: • MDMA=0b10: A single DMA request is generated each time both master and slave EOC events have occurred. At that time, two data items are available and the 32-bit register ADCx_CDR contains the two half-words representing two ADC-converted data items. The slave ADC data take the upper half-word and the master ADC data take the lower half-word. This mode is used in interleaved mode and in regular simultaneous mode when resolution is 10-bit or 12-bit. Example: Interleaved dual mode: a DMA request is generated each time 2 data items are available: 1st DMA request: ADCx_CDR[31:0] = SLV_ADCx_DR[15:0] | MST_ADCx_DR[15:0] 2nd DMA request: ADCx_CDR[31:0] = SLV_ADCx_DR[15:0] | MST_ADCx_DR[15:0] 492/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Figure 124. DMA requests in regular simultaneous mode when MDMA=0b10 7ULJJHU 7ULJJHU &+ $'&0DVWHUUHJXODU 7ULJJHU &+ 7ULJJHU &+ &+ $'&6ODYH(2& &+ &+ &+ $'&6ODYHUHJXODU &+ $'&6ODYH(2& '0$UHTXHVWIURP $'&0DVWHU '0$UHTXHVWIURP $'&6ODYH &RQILJXUDWLRQZKHUHHDFKVHTXHQFHFRQWDLQVRQO\RQHFRQYHUVLRQ 06Y9 Figure 125. DMA requests in interleaved mode when MDMA=0b10 7ULJJHU $'&0DVWHUUHJXODU $'&0DVWHU(2& $'&6ODYHUHJXODU 7ULJJHU &+ &+ &+ &+ &+ 'HOD\ 'HOD\ 'HOD\ 'HOD\ &+ 7ULJJHU 7ULJJHU 7ULJJHU &+ &+ 'HOD\ &+ &+ $'&6ODYH(2& '0$UHTXHVWIURP $'&0DVWHU '0$UHTXHVWIURP $'&6ODYH &RQILJXUDWLRQZKHUHHDFKVHTXHQFHFRQWDLQVRQO\RQHFRQYHUVLRQ 06Y9 DocID024597 Rev 1 493/1680 536 Analog-to-digital converters (ADC) Note: RM0351 When using MDMA mode, the user must take care to configure properly the duration of the master and slave conversions so that a DMA request is generated and served for reading both data (master + slave) before a new conversion is available. • MDMA=0b11: This mode is similar to the MDMA=0b10. The only differences are that on each DMA request (two data items are available), two bytes representing two ADC converted data items are transferred as a half-word. This mode is used in interleaved and regular simultaneous mode when resolution is 6bit or when resolution is 8-bit and data is not signed (offsets must be disabled for all the involved channels). Example: Interleaved dual mode: a DMA request is generated each time 2 data items are available: 1st DMA request: ADCx_CDR[15:0] = SLV_ADCx_DR[7:0] | MST_ADCx_DR[7:0] 2nd DMA request: ADCx_CDR[15:0] = SLV_ADCx_DR[7:0] | MST_ADCx_DR[7:0] Overrun detection In dual ADC mode (when DUAL[4:0] is not equal to b00000), if an overrun is detected on one of the ADCs, the DMA requests are no longer issued to ensure that all the data transferred to the RAM are valid (this behavior occurs whatever the MDMA configuration). It may happen that the EOC bit corresponding to one ADC remains set because the data register of this ADC contains valid data. DMA one shot mode/ DMA circular mode when MDMA mode is selected When MDMA mode is selected (0b10 or 0b11), bit DMACFG of the ADCx_CCR register must also be configured to select between DMA one shot mode and circular mode, as explained in section Section : Managing conversions using the DMA (bits DMACFG of master and slave ADCx_CFGR are not relevant). Stopping the conversions in dual ADC modes The user must set the control bits ADSTP/JADSTP of the master ADC to stop the conversions of both ADC in dual ADC mode. The other ADSTP control bit of the slave ADC has no effect in dual ADC mode. Once both ADC are effectively stopped, the bits ADSTART/JADSTART of the master and slave ADCs are both cleared by hardware. 16.3.31 Temperature sensor The temperature sensor can be used to measure the junction temperature (Tj) of the device. The temperature sensor is internally connected to the ADC1_IN17 and ADC3_IN17 input channels which are used to convert the sensor output voltage to a digital value. When not in use, the sensor can be put in power down mode. Figure 126 shows the block diagram of connections between the temperature sensor and the ADC. The temperature sensor output voltage changes linearly with temperature. The offset of this line varies from chip to chip due to process variation (up to 45 °C from one chip to another). The uncalibrated internal temperature sensor is more suited for applications that detect temperature variations instead of absolute temperatures. To improve the accuracy of the 494/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) temperature sensor measurement, calibration values are stored in system memory for each device by ST during production. During the manufacturing process, the calibration data of the temperature sensor and the internal voltage reference are stored in the system memory area. The user application can then read them and use them to improve the accuracy of the temperature sensor or the internal reference. Refer to the STM32L4x6 datasheet for additional information. Main features • Supported temperature range: –40 to 125 °C • Precision: ±2 °C The temperature sensor is internally connected to the ADC1_IN17 and ADC3_IN17 input channel which is used to convert the sensor’s output voltage to a digital value. Refer to the electrical characteristics section of the device datasheet for the sampling time value to be applied when converting the internal temperature sensor. When not in use, the sensor can be put in power-down mode. Figure 126 shows the block diagram of the temperature sensor. Figure 126. Temperature sensor channel block diagram &RQYHUWHG GDWD $'&[ 7HPSHUDWXUH VHQVRU 976 $GGUHVVGDWDEXV &+6(/FRQWUROELW $'&LQSXW 06Y9 Note: The CH17SEL bit must be set to enable the conversion of the temperature sensor voltage VTS. Reading the temperature To use the sensor: 1. Select the ADC1_IN17 or ADC3_IN17 input channels (with the appropriate sampling time). 2. Program with the appropriate sampling time (refer to electrical characteristics section of the device datasheet). 3. Set the CH17SEL bit in the ADCx_CCR register to wake up the temperature sensor from power-down mode. 4. Start the ADC conversion. 5. Read the resulting VTS data in the ADC data register. DocID024597 Rev 1 495/1680 536 Analog-to-digital converters (ADC) 6. RM0351 Calculate the actual temperature using the following formula: 110 °C – 30 °C Temperature ( in °C ) = ---------------------------------------------------------- × ( TS_DATA – TS_CAL1 ) + 30 °C TS_CAL2 – TS_CAL1 Where: • TS_CAL2 is the temperature sensor calibration value acquired at 110°C • TS_CAL1 is the temperature sensor calibration value acquired at 30°C • TS_DATA is the actual temperature sensor output value converted by ADC Refer to the device datasheet for more information about TS_CAL1 and TS_CAL2 calibration points. Note: The sensor has a startup time after waking from power-down mode before it can output VTS at the correct level. The ADC also has a startup time after power-on, so to minimize the delay, the ADEN and CH17SEL bits should be set at the same time. 16.3.32 VBAT supply monitoring The CH18SEL bit in the ADCx_CCR register is used to switch to the battery voltage. As the VBAT voltage could be higher than VDDA, to ensure the correct operation of the ADC, the VBAT pin is internally connected to a bridge divider by 3. This bridge is automatically enabled when CH18_SEL is set, to connect VBAT/3 to the ADC1_IN18 or ADC3_IN18 input channels. As a consequence, the converted digital value is one third of the VBAT voltage. To prevent any unwanted consumption on the battery, it is recommended to enable the bridge divider only when needed, for ADC conversion. Refer to the electrical characteristics of the device datasheet for the sampling time value to be applied when converting the VBAT/3 voltage. Figure 127 shows the block diagram of the VBAT sensing feature. Figure 127. VBAT channel block diagram 9%$7 $'&[ 9%$7 $GGUHVVGDWDEXV &+6(/FRQWUROELW $'&LQSXW 06Y9 Note: 496/1680 The CH18_SEL bit must be set to enable the conversion of internal channels ADC1_IN18 and ADC3_IN18 (VBAT/3). DocID024597 Rev 1 RM0351 16.3.33 Analog-to-digital converters (ADC) Monitoring the internal voltage reference It is possible to monitor the internal voltage reference (VREFINT) to have a reference point for evaluating the ADC VREF+ voltage level. The internal voltage reference is internally connected to the input channel 0 of the ADC1 (ADC1_IN0). Refer to the electrical characteristics section of the STM32L4x6 datasheet for the sampling time value to be applied when converting the internal voltage reference voltage. Figure 127 shows the block diagram of the VREFINT sensing feature. Figure 128. VREFINT channel block diagram $'&B95()(1 FRQWUROELW ,QWHUQDO SRZHUEORFN 95(),17 $'& $'&B,1 069 Note: The VREFEN bit into ADCx_CCR register must be set to enable the conversion of internal channels ADC1_IN0 (VREFINT). Calculating the actual VDDA voltage using the internal reference voltage The VDDA power supply voltage applied to the microcontroller may be subject to variation or not precisely known. The embedded internal voltage reference (VREFINT) and its calibration data acquired by the ADC during the manufacturing process at VDDA = 3.3 V can be used to evaluate the actual VDDA voltage level. The following formula gives the actual VDDA voltage supplying the device: VDDA = 3.0 V x VREFINT_CAL / VREFINT_DATA Where: • VREFINT_CAL is the VREFINT calibration value • VREFINT_DATA is the actual VREFINT output value converted by ADC Converting a supply-relative ADC measurement to an absolute voltage value The ADC is designed to deliver a digital value corresponding to the ratio between the analog power supply and the voltage applied on the converted channel. For most application use cases, it is necessary to convert this ratio into a voltage independent of VDDA. For applications where VDDA is known and ADC converted values are right-aligned you can use the following formula to get this absolute value: V DDA V CHANNELx = ------------------------------------- × ADCx_DATA FULL_SCALE DocID024597 Rev 1 497/1680 536 Analog-to-digital converters (ADC) RM0351 For applications where VDDA value is not known, you must use the internal voltage reference and VDDA can be replaced by the expression provided in Section : Calculating the actual VDDA voltage using the internal reference voltage, resulting in the following formula: 3.0 V × VREFINT_CAL × ADCx_DATA V CHANNELx = -------------------------------------------------------------------------------------------------------VREFINT_DATA × FULL_SCALE Where: • VREFINT_CAL is the VREFINT calibration value • ADCx_DATA is the value measured by the ADC on channel x (right-aligned) • VREFINT_DATA is the actual VREFINT output value converted by the ADC • FULL_SCALE is the maximum digital value of the ADC output. For example with 12-bit resolution, it will be 212 - 1 = 4095 or with 8-bit resolution, 28 - 1 = 255. Note: If ADC measurements are done using an output format other than 12 bit right-aligned, all the parameters must first be converted to a compatible format before the calculation is done. 16.4 ADC interrupts For each ADC, an interrupt can be generated: • After ADC power-up, when the ADC is ready (flag ADRDY) • On the end of any conversion for regular groups (flag EOC) • On the end of a sequence of conversion for regular groups (flag EOS) • On the end of any conversion for injected groups (flag JEOC) • On the end of a sequence of conversion for injected groups (flag JEOS) • When an analog watchdog detection occurs (flag AWD1, AWD2 and AWD3) • When the end of sampling phase occurs (flag EOSMP) • When the data overrun occurs (flag OVR) • When the injected sequence context queue overflows (flag JQOVF) Separate interrupt enable bits are available for flexibility. Table 95. ADC interrupts per each ADC Interrupt event Event flag Enable control bit ADRDY ADRDYIE End of conversion of a regular group EOC EOCIE End of sequence of conversions of a regular group EOS EOSIE End of conversion of a injected group JEOC JEOCIE End of sequence of conversions of an injected group JEOS JEOSIE Analog watchdog 1 status bit is set AWD1 AWD1IE Analog watchdog 2 status bit is set AWD2 AWD2IE Analog watchdog 3 status bit is set AWD3 AWD3IE EOSMP EOSMPIE OVR OVRIE JQOVF JQOVFIE ADC ready End of sampling phase Overrun Injected context queue overflows 498/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) 16.5 ADC registers (for each ADC) Refer to Section 1.1 on page 61 for a list of abbreviations used in register descriptions. 16.5.1 ADC interrupt and status register (ADCx_ISR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. AWD2 AWD1 JEOS JEOC OVR EOS EOC r_w1 r_w1 r_w1 r_w1 r_w1 r_w1 rc_w1 JQOVF AWD3 r_w1 r_w1 EOSMP ADRDY r_w1 r_w1 Bits 31:11 Reserved, must be kept at reset value. Bit 10 JQOVF: Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to Section 16.3.21: Queue of context for injected conversions for more information. 0: No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software) 1: Injected context queue overflow has occurred Bit 9 AWD3: Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT3[7:0] and HT3[7:0] of ADCx_TR3 register. It is cleared by software writing 1 to it. 0: No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software) 1: Analog watchdog 3 event occurred Bit 8 AWD2: Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT2[7:0] and HT2[7:0] of ADCx_TR2 register. It is cleared by software writing 1 to it. 0: No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software) 1: Analog watchdog 2 event occurred Bit 7 AWD1: Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT1[11:0] and HT1[11:0] of ADCx_TR1 register. It is cleared by software. writing 1 to it. 0: No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software) 1: Analog watchdog 1 event occurred Bit 6 JEOS: Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it. 0: Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software) 1: Injected conversions complete DocID024597 Rev 1 499/1680 536 Analog-to-digital converters (ADC) RM0351 Bit 5 JEOC: Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADCx_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADCx_JDRy register 0: Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software) 1: Injected channel conversion complete Bit 4 OVR: ADC overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it. 0: No overrun occurred (or the flag event was already acknowledged and cleared by software) 1: Overrun has occurred Bit 3 EOS: End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it. 0: Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software) 1: Regular Conversions sequence complete Bit 2 EOC: End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADCx_DR register. It is cleared by software writing 1 to it or by reading the ADCx_DR register 0: Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software) 1: Regular channel conversion complete Bit 1 EOSMP: End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase. 0: not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software) 1: End of sampling phase reached Bit 0 ADRDY: ADC ready This bit is set by hardware after the ADC has been enabled (bit ADEN=1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it. 0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software) 1: ADC is ready to start conversion 500/1680 DocID024597 Rev 1 RM0351 16.5.2 Analog-to-digital converters (ADC) ADC interrupt enable register (ADCx_IER) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. JQ OVFIE AWD3 IE AWD2 IE rw rw rw Res. Res. Res. Res. AWD1 JEOSIE JEOCIE OVRIE IE rw rw rw rw EOSIE rw EOSMP ADRDY EOCIE IE IE rw rw rw Bits 31:11 Reserved, must be kept at reset value. Bit 10 JQOVFIE: Injected context queue overflow interrupt enable This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt. 0: Injected Context Queue Overflow interrupt disabled 1: Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit is set. Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing). Bit 9 AWD3IE: Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. 0: Analog watchdog 3 interrupt disabled 1: Analog watchdog 3 interrupt enabled Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bit 8 AWD2IE: Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. 0: Analog watchdog 2 interrupt disabled 1: Analog watchdog 2 interrupt enabled Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bit 7 AWD1IE: Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt. 0: Analog watchdog 1 interrupt disabled 1: Analog watchdog 1 interrupt enabled Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bit 6 JEOSIE: End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. 0: JEOS interrupt disabled 1: JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set. Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing). DocID024597 Rev 1 501/1680 536 Analog-to-digital converters (ADC) RM0351 Bit 5 JEOCIE: End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. 0: JEOC interrupt disabled. 1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set. Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no regular conversion is ongoing). Bit 4 OVRIE: Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. 0: Overrun interrupt disabled 1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 3 EOSIE: End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. 0: EOS interrupt disabled 1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 2 EOCIE: End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. 0: EOC interrupt disabled. 1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 1 EOSMPIE: End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. 0: EOSMP interrupt disabled. 1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 0 ADRDYIE: ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. 0: ADRDY interrupt disabled 1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set. Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 502/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) 16.5.3 ADC control register (ADCx_CR) Address offset: 0x08 Reset value: 0x2000 0000 31 30 AD CAL ADCA LDIF rs rw rw rw 15 14 13 12 Res. Res. 29 28 DEEP ADVREG PWD EN Res. Res. 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 3 2 Res. JAD STP AD STP rs rs Res. Res. Res. Res. Res. JAD AD START START rs rs 1 0 AD DIS AD EN rs rs Bit 31 ADCAL: ADC calibration This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for single-ended or differential inputs mode. It is cleared by hardware after calibration is complete. 0: Calibration complete 1: Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress. Note: Software is allowed to launch a calibration by setting ADCAL only when ADEN=0. Note: Software is allowed to update the calibration factor by writing ADCx_CALFACT only when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing) Bit 30 ADCALDIF: Differential mode for calibration This bit is set and cleared by software to configure the single-ended or differential inputs mode for the calibration. 0: Writing ADCAL will launch a calibration in Single-ended inputs Mode. 1: Writing ADCAL will launch a calibration in Differential inputs Mode. Note: Software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Bit 29 DEEPPWD: Deep-power-down enable This bit is set and cleared by software to put the ADC in deep-power-down mode. 0: ADC not in deep-power down 1: ADC in deep-power-down (default reset state) Note: Software is allowed to write this bit only when the ADC is disabled (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Bit 28 ADVREGEN: ADC voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. 0: ADC Voltage regulator disabled 1: ADC Voltage regulator enabled. For more details about the ADC voltage regulator enable and disable sequences, refer to Section 16.3.6: ADC Deep-Power-Down Mode (DEEPPWD) & ADC Voltage Regulator (ADVREGEN). The software can program this bit field only when the ADC is disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Bits 27:6 Reserved, must be kept at reset value. DocID024597 Rev 1 503/1680 536 Analog-to-digital converters (ADC) RM0351 Bit 5 JADSTP: ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). 0: No ADC stop injected conversion command ongoing 1: Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is in progress. Note: Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC) In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP) Bit 4 ADSTP: ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). 0: No ADC stop regular conversion command ongoing 1: Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in progress. Note: Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP). In dual ADC regular simultaneous mode and interleaved mode, the bit ADSTP of the master ADC must be used to stop regular conversions. The other ADSTP bit is inactive. Bit 3 JADSTART: ADC start of injected conversion This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN, a conversion will start immediately (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: – in single conversion mode when software trigger is selected (JEXTSEL=0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag. – in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware. 0: No ADC injected conversion is ongoing. 1: Write 1 to start injected conversions. Read 1 means that the ADC is operating and eventually converting an injected channel. Note: Software is allowed to set JADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared) 504/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Bit 2 ADSTART: ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion will start immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: – in single conversion mode when software trigger is selected (EXTSEL=0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag. – in all cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. 0: No ADC regular conversion is ongoing. 1: Write 1 to start regular conversions. Read 1 means that the ADC is operating and eventually converting a regular channel. Note: Software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC) In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared) Bit 1 ADDIS: ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). 0: no ADDIS command ongoing 1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress. Note: Software is allowed to set ADDIS only when ADEN=1 and both ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing) Bit 0 ADEN: ADC enable control This bit is set by software to enable the ADC. The ADC will be effectively ready to operate once the flag ADRDY has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. 0: ADC is disabled (OFF state) 1: Write 1 to enable the ADC. Note: Software is allowed to set ADEN only when all bits of ADCx_CR registers are 0 (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator) DocID024597 Rev 1 505/1680 536 Analog-to-digital converters (ADC) 16.5.4 RM0351 ADC configuration register (ADCx_CFGR) Address offset: 0x0C Reset value: 0x8000 0000 31 30 29 JQDIS 28 27 26 25 24 JAWD1 JAUTO EN AWD1CH[4:0] 23 22 AWD1 AWD1S EN GL 21 20 JQM JDISC EN 19 18 17 16 DISC EN DISCNUM[2:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. AUT DLY CONT OVR MOD Res. DMA CFG DMA EN rw rw rw rw rw EXTEN[1:0] rw rw EXTSEL[3:0] rw rw rw ALIGN rw rw RES[1:0] rw rw Bit 31 JQDIS: Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism : 0: Injected Queue enabled 1: Injected Queue disabled Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no regular nor injected conversion is ongoing). A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared. Bits 30:26 AWD1CH[4:0]: Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. 00000: ADC analog input channel-0 monitored by AWD1 (available on ADC1 only) 00001: ADC analog input channel-1 monitored by AWD1 ..... 10010: ADC analog input channel-18 monitored by AWD1 others: reserved, must not be used Note: The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bit 25 JAUTO: Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. 0: Automatic injected group conversion disabled 1: Automatic injected group conversion enabled Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no regular nor injected conversion is ongoing). When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit JAUTO of the slave ADC is no more writable and its content is equal to the bit JAUTO of the master ADC. Bit 24 JAWD1EN: Analog watchdog 1 enable on injected channels This bit is set and cleared by software 0: Analog watchdog 1 disabled on injected channels 1: Analog watchdog 1 enabled on injected channels Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing). 506/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Bit 23 AWD1EN: Analog watchdog 1 enable on regular channels This bit is set and cleared by software 0: Analog watchdog 1 disabled on regular channels 1: Analog watchdog 1 enabled on regular channels Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 22 AWD1SGL: Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels 0: Analog watchdog 1 enabled on all channels 1: Analog watchdog 1 enabled on a single channel Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bit 21 JQM: JSQR queue mode This bit is set and cleared by software. It defines how an empty Queue is managed. 0: JSQR Mode 0: The Queue is never empty and maintains the last written configuration into JSQR. 1: JSQR Mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence. Refer to Section 16.3.21: Queue of context for injected conversions for more information. Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing). When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit JQM of the slave ADC is no more writable and its content is equal to the bit JQM of the master ADC. Bit 20 JDISCEN: Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group. 0: Discontinuous mode on injected channels disabled 1: Discontinuous mode on injected channels enabled Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing). It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. When dual mode is enabled (bits DUAL of ADCx_CCR register are not equal to zero), the bit JDISCEN of the slave ADC is no more writable and its content is equal to the bit JDISCEN of the master ADC. Bits 19:17 DISCNUM[2:0]: Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. 000: 1 channel 001: 2 channels ... 111: 8 channels Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bits DISCNUM[2:0] of the slave ADC are no more writable and their content is equal to the bits DISCNUM[2:0] of the master ADC. DocID024597 Rev 1 507/1680 536 Analog-to-digital converters (ADC) RM0351 Bit 16 DISCEN: Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. 0: Discontinuous mode for regular channels disabled 1: Discontinuous mode for regular channels enabled Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1. It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit DISCEN of the slave ADC is no more writable and its content is equal to the bit DISCEN of the master ADC. Bit 15 Reserved, must be kept at reset value. Bit 14 AUTDLY: Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.. 0: Auto-delayed conversion mode off 1: Auto-delayed conversion mode on Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit AUTDLY of the slave ADC is no more writable and its content is equal to the bit AUTDLY of the master ADC. Bit 13 CONT: Single / continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. 0: Single conversion mode 1: Continuous conversion mode Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1. Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit CONT of the slave ADC is no more writable and its content is equal to the bit CONT of the master ADC. Bit 12 OVRMOD: Overrun Mode This bit is set and cleared by software and configure the way data overrun is managed. 0: ADCx_DR register is preserved with the old data when an overrun is detected. 1: ADCx_DR register is overwritten with the last conversion result when an overrun is detected. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. 00: Hardware trigger detection disabled (conversions can be launched by software) 01: Hardware trigger detection on the rising edge 10: Hardware trigger detection on the falling edge 11: Hardware trigger detection on both the rising and falling edges Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). 508/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Bits 9:6 EXTSEL[3:0]: External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: 0000: Event 0 0001: Event 1 0010: Event 2 0011: Event 3 0100: Event 4 0101: Event 5 0110: Event 6 0111: Event 7 ... 1111: Event 15 Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 5 ALIGN: Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Section : Data register, data alignment and offset (ADCx_DR, OFFSETy, OFFSETy_CH, ALIGN) 0: Right alignment 1: Left alignment Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bits 4:3 RES[1:0]: Data resolution These bits are written by software to select the resolution of the conversion. 00: 12-bit 01: 10-bit 10: 8-bit 11: 6-bit Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bit 2 Reserved, must be kept at reset value. Bit 1 DMACFG: Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN=1. 0: DMA One Shot Mode selected 1: DMA Circular Mode selected For more details, refer to Section : Managing conversions using the DMA Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). In dual-ADC modes, this bit is not relevant and replaced by control bit DMACFG of the ADCx_CCR register. Bit 0 DMAEN: Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows to use the GP-DMA to manage automatically the converted data. For more details, refer to Section : Managing conversions using the DMA. 0: DMA disabled 1: DMA enabled Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). In dual-ADC modes, this bit is not relevant and replaced by control bits MDMA[1:0] of the ADCx_CCR register. DocID024597 Rev 1 509/1680 536 Analog-to-digital converters (ADC) 16.5.5 RM0351 ADC configuration register 2 (ADCx_CFGR2) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. ROV SM TROVS rw rw Res. Res. Res. Res. OVSS[3:0] rw rw rw OVSR[2:0] rw rw rw JOVSE ROVSE rw rw rw Bits 31:11 Reserved, must be kept at reset value. Bit 10 ROVSM: Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. 0: Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence) 1: Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start) Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 9 TROVS: Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling 0: All oversampled conversions for a channel are done consecutively following a trigger 1: Each oversampled conversion for a channel needs a new trigger Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bits 8:5 OVSS[3:0]: Oversampling shift This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. 0000: No shift 0001: Shift 1-bit 0010: Shift 2-bits 0011: Shift 3-bits 0100: Shift 4-bits 0101: Shift 5-bits 0110: Shift 6-bits 0111: Shift 7-bits 1000: Shift 8-bits Other codes reserved Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing). 510/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Bits 4:2 OVSR[2:0]: Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. 000: 2x 001: 4x 010: 8x 011: 16x 100: 32x 101: 64x 110: 128x 111: 256x Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 1 JOVSE: Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. 0: Injected Oversampling disabled 1: Injected Oversampling enabled Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing) Bit 0 ROVSE: Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. 0: Regular Oversampling disabled 1: Regular Oversampling enabled Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing) 16.5.6 ADC sample time register 1 (ADCx_SMPR1) Address offset: 0x14 Reset value: 0x0000 0000 31 30 Res. Res. 15 14 SMP 5_0 rw 29 28 27 25 24 23 SMP8[2:0] 22 21 20 SMP7[2:0] 19 18 SMP6[2:0] 17 16 SMP5[2:1] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMP4[2:0] rw 26 SMP9[2:0] rw SMP3[2:0] rw rw rw SMP2[2:0] rw rw rw SMP1[2:0] rw DocID024597 Rev 1 rw rw SMP0[2:0] rw rw rw rw 511/1680 536 Analog-to-digital converters (ADC) RM0351 Bits 31:30 Reserved, must be kept at reset value. Bits 29:0 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. 000: 2.5 ADC clock cycles 001: 6.5 ADC clock cycles 010: 12.5 ADC clock cycles 011: 24.5 ADC clock cycles 100: 47.5 ADC clock cycles 101: 92.5 ADC clock cycles 110: 247.5 ADC clock cycles 111: 640.5 ADC clock cycles Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 512/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) 16.5.7 ADC sample time register 2 (ADCx_SMPR2) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 Res. Res. Res. Res. Res. 15 14 13 12 11 rw rw SMP15_0 rw SMP14[2:0] rw rw 26 25 24 23 SMP18[2:0] 22 21 20 SMP17[2:0] 19 18 SMP16[2:0] 17 16 SMP15[2:1] rw rw rw rw rw rw rw rw rw rw rw 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw SMP13[2:0] rw SMP12[2:0] rw SMP11[2:0] rw SMP10[2:0] rw rw Bits 31:27 Reserved, must be kept at reset value. Bits 26:0 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. 000: 2.5 ADC clock cycles 001: 6.5 ADC clock cycles 010: 12.5 ADC clock cycles 011: 24.5 ADC clock cycles 100: 47.5 ADC clock cycles 101: 92.5 ADC clock cycles 110: 247.5 ADC clock cycles 111: 640.5 ADC clock cycles Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 16.5.8 ADC watchdog threshold register 1 (ADCx_TR1) Address offset: 0x20 Reset value: 0x0FFF 0000 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 23 22 21 20 19 18 17 16 4 3 2 1 0 rw rw rw rw rw HT1[11:0] 11 10 9 8 7 6 5 LT1[11:0] rw rw rw rw rw rw rw Bits 31:28 Reserved, must be kept at reset value. DocID024597 Rev 1 513/1680 536 Analog-to-digital converters (ADC) RM0351 Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to Section 16.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 LT1[11:0]: Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 1. Refer to Section 16.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 16.5.9 ADC watchdog threshold register 2 (ADCx_TR2) Address offset: 0x24 Reset value: 0x00FF 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 HT2[7:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw LT2[7:0] rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 HT2[7:0]: Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to Section 16.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 LT2[7:0]: Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 2. Refer to Section 16.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 514/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) 16.5.10 ADC watchdog threshold register 3 (ADCx_TR3) Address offset: 0x28 Reset value: 0x00FF 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 HT3[7:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw LT3[7:0] rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 HT3[7:0]: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to Section 16.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 LT3[7:0]: Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 3. This watchdog compares the 8-bit of LT3 with the 8 MSB of the converted data. Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). DocID024597 Rev 1 515/1680 536 Analog-to-digital converters (ADC) 16.5.11 RM0351 ADC regular sequence register 1 (ADCx_SQR1) Address offset: 0x30 Reset value: 0x0000 0000 31 30 29 Res. Res. Res. 15 14 13 rw rw 28 26 25 24 SQ4[4:0] rw rw rw rw rw 11 10 9 8 rw rw Res. rw 23 22 21 Res. 12 SQ2[3:0] rw 27 19 18 rw rw rw rw rw 7 6 5 4 3 2 Res. Res. rw rw rw rw SQ1[4:0] rw 20 SQ3[4:0] 17 16 Res. SQ2[4] rw 1 0 rw rw L[3:0] Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SQ4[4:0]: 4th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 4th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 23 Reserved, must be kept at reset value. Bits 22:18 SQ3[4:0]: 3rd conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 3rd in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 17 Reserved, must be kept at reset value. Bits 16:12 SQ2[4:0]: 2nd conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 2nd in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 11 Reserved, must be kept at reset value. Bits 10:6 SQ1[4:0]: 1st conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 1st in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bits 5:4 Reserved, must be kept at reset value. Bits 3:0 L[3:0]: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. 0000: 1 conversion 0001: 2 conversions ... 1111: 16 conversions Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). 516/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) 16.5.12 ADC regular sequence register 2 (ADCx_SQR2) Address offset: 0x34 Reset value: 0x0000 0000 31 30 29 Res. Res. Res. 15 14 13 rw rw 28 26 25 24 SQ9[4:0] rw rw rw rw rw 11 10 9 8 rw rw Res. rw 23 22 21 Res. 12 SQ7[3:0] rw 27 19 18 rw rw rw rw rw 7 6 5 4 3 2 rw rw rw rw SQ6[4:0] rw 20 SQ8[4:0] Res. 17 16 Res. SQ7[4] rw 1 0 rw rw SQ5[4:0] rw Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SQ9[4:0]: 9th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 9th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 23 Reserved, must be kept at reset value. Bits 22:18 SQ8[4:0]: 8th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 8th in the regular conversion sequence Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 17 Reserved, must be kept at reset value. Bits 16:12 SQ7[4:0]: 7th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 7th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 11 Reserved, must be kept at reset value. Bits 10:6 SQ6[4:0]: 6th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 6th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 5 Reserved, must be kept at reset value. Bits 4:0 SQ5[4:0]: 5th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 5th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). DocID024597 Rev 1 517/1680 536 Analog-to-digital converters (ADC) 16.5.13 RM0351 ADC regular sequence register 3 (ADCx_SQR3) Address offset: 0x38 Reset value: 0x0000 0000 31 30 29 Res. Res. Res. 15 14 13 rw rw 28 26 25 24 SQ14[4:0] rw rw rw rw rw 11 10 9 8 rw rw Res. rw 23 22 21 Res. 12 SQ12[3:0] rw 27 19 18 rw rw rw rw rw 7 6 5 4 3 2 rw rw rw rw SQ11[4:0] rw 20 SQ13[4:0] Res. 17 16 Res. SQ12[4] rw 1 0 rw rw SQ10[4:0] rw Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SQ14[4:0]: 14th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 14th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 23 Reserved, must be kept at reset value. Bits 22:18 SQ13[4:0]: 13th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 13th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 17 Reserved, must be kept at reset value. Bits 16:12 SQ12[4:0]: 12th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 12th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 11 Reserved, must be kept at reset value. Bits 10:6 SQ11[4:0]: 11th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 11th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 5 Reserved, must be kept at reset value. Bits 4:0 SQ10[4:0]: 10th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 10th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). 518/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) 16.5.14 ADC regular sequence register 4 (ADCx_SQR4) Address offset: 0x3C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. rw rw rw rw rw rw rw rw SQ16[4:0] rw Res. SQ15[4:0] rw Bits 31:11 Reserved, must be kept at reset value. Bits 10:6 SQ16[4:0]: 16th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 16th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 5 Reserved, must be kept at reset value. Bits 4:0 SQ15[4:0]: 15th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 15th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). DocID024597 Rev 1 519/1680 536 Analog-to-digital converters (ADC) 16.5.15 RM0351 ADC regular Data Register (ADCx_DR) Address offset: 0x40 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r RDATA[15:0] r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 RDATA[15:0]: Regular Data converted These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in Section 16.3.26: Data management. 520/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) 16.5.16 ADC injected sequence register (ADCx_JSQR) Address offset: 0x4C Reset value: 0x0000 0000 31 30 29 Res. 15 27 26 rw rw rw rw rw 13 12 11 10 rw rw Res. rw 25 24 23 Res. 14 JSQ2[1:0] rw 28 JSQ4[4:0] 21 20 rw rw rw rw rw 8 7 6 5 4 rw rw JEXTEN[1:0] rw 19 18 Res. 9 JSQ1[4:0] rw 22 JSQ3[4:0] 3 17 rw rw rw 2 1 0 rw rw JEXTSEL[3:0] rw rw rw 16 JSQ2[4:2] JL[1:0] rw Bit 31 Reserved, must be kept at reset value. Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence These bits are written by software with the channel number (0..18) assigned as the 4th in the injected conversion sequence. Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1). Bit 25 Reserved, must be kept at reset value. Bits 24:20 JSQ3[4:0]: 3rd conversion in the injected sequence These bits are written by software with the channel number (0..18) assigned as the 3rd in the injected conversion sequence. Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1). Bit 19 Reserved, must be kept at reset value. Bits 18:14 JSQ2[4:0]: 2nd conversion in the injected sequence These bits are written by software with the channel number (0..18) assigned as the 2nd in the injected conversion sequence. Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1). Bit 13 Reserved, must be kept at reset value. Bits 12:8 JSQ1[4:0]: 1st conversion in the injected sequence These bits are written by software with the channel number (0..18) assigned as the 1st in the injected conversion sequence. Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1). DocID024597 Rev 1 521/1680 536 Analog-to-digital converters (ADC) RM0351 Bits 7:6 JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. 00: If JQDIS=0 (queue enabled), Hardware and software trigger detection disabled 00: If JQDIS=1 (queue disabled), Hardware trigger detection disabled (conversions can be launched by software) 01: Hardware trigger detection on the rising edge 10: Hardware trigger detection on the falling edge 11: Hardware trigger detection on both the rising and falling edges Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1). If JQM=1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to Section 16.3.21: Queue of context for injected conversions) Bits 5:2 JEXTSEL[3:0]: External Trigger Selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: 0000: Event 0 0001: Event 1 0010: Event 2 0011: Event 3 0100: Event 4 0101: Event 5 0110: Event 6 0111: Event 7 ... 1111: Event 15 Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1). Bits 1:0 JL[1:0]: Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. 00: 1 conversion 01: 2 conversions 10: 3 conversions 11: 4 conversions Note: Software is allowed to write these bits at any time, once the ADC is enabled (ADEN=1). 522/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) 16.5.17 ADC offset register (ADCx_OFRy) (y=1..4) Address offset: 0x60, 0x64, 0x68, 0x6C Reset value: 0x0000 0000 31 30 OFFSETy _EN 29 28 27 26 OFFSETy_CH[4:0] 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 Res. Res. Res. Res. rw rw rw rw rw OFFSETy[11:0] rw rw Bit 31 OFFSETy_EN: Offset y Enable This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]. Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bits 30:26 OFFSETy_CH[4:0]: Channel selection for the Data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[11:0] will apply. Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). Bits 25:12 Reserved, must be kept at reset value. Bits 11:0 OFFSETy[11:0]: Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADCx_DR (regular conversion) or from in the ADCx_JDRyi registers (injected conversion). Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[11:0] which is subtracted when converting channel 4. DocID024597 Rev 1 523/1680 536 Analog-to-digital converters (ADC) 16.5.18 RM0351 ADC injected data register (ADCx_JDRy, y= 1..4) Address offset: 0x80 - 0x8C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r r JDATA[15:0] r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 JDATA[15:0]: Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in Section 16.3.26: Data management. 16.5.19 ADC Analog Watchdog 2 Configuration Register (ADCx_AWD2CR) Address offset: 0xA0 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw AWD2CH[18:16] AWD2CH[15:0] rw rw rw rw rw rw rw rw rw Bits 31:19 Reserved, must be kept at reset value. Bits 18:0 AWD2CH[18:0]: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel-i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel-i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog Watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 524/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) 16.5.20 ADC Analog Watchdog 3 Configuration Register (ADCx_AWD3CR) Address offset: 0xA4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw AWD3CH[18:16] AWD3CH[15:0] rw rw rw rw rw rw rw rw rw Bits 31:19 Reserved, must be kept at reset value. Bits 18:0 AWD2CH[18:0]: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel-i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel-i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog Watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 16.5.21 ADC Differential Mode Selection Register (ADCx_DIFSEL) Address offset: 0xB0 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 18 17 16 DIFSEL[18:16] r r r 6 5 4 3 2 1 0 rw rw rw rw rw rw r DIFSEL[15:0] rw rw rw rw rw rw rw rw rw DocID024597 Rev 1 525/1680 536 Analog-to-digital converters (ADC) RM0351 Bits 31:19 Reserved, must be kept at reset value. Bits 18:16 DIFSEL[18:16]: Differential mode for channels 18 to 16. These bits are read only. These channels are forced to single-ended input mode (either connected to a single-ended I/O port or to an internal channel). Bits 15:1 DIFSEL[15:1]: Differential mode for channels 15 to 1 These bits are set and cleared by software. They allow to select if a channel is configured as single ended or differential mode. DIFSEL[i] = 0: ADC analog input channel-i is configured in single ended mode DIFSEL[i] = 1: ADC analog input channel-i is configured in differential mode Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). It is mandatory to keep cleared ADC1_DIFSEL[15] (connected to an internal single ended channel) Bit 0 DIFSEL[0]: Differential mode for channel 0 This bit is read only. This channel is forced to single-ended input mode (connected to an internal channel). 16.5.22 ADC Calibration Factors (ADCx_CALFACT) Address offset: 0xB4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 Res. Res. Res. Res. Res. Res. Res. Res. Res. 22 20 19 18 17 16 CALFACT_D[6:0] rw rw rw rw rw rw rw 6 5 4 3 2 1 0 rw rw CALFACT_S[6:0] rw Bits 31:23 Reserved, must be kept at reset value. 526/1680 21 DocID024597 Rev 1 rw rw rw rw RM0351 Analog-to-digital converters (ADC) Bits 22:16 CALFACT_D[6:0]: Calibration Factors in differential mode These bits are written by hardware or by software. Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new differential calibration is launched. Note: Software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Bits 15:7 Reserved, must be kept at reset value. Bits 6:0 CALFACT_S[6:0]: Calibration Factors In Single-Ended mode These bits are written by hardware or by software. Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new single-ended calibration is launched. Note: Software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). DocID024597 Rev 1 527/1680 536 Analog-to-digital converters (ADC) 16.6 RM0351 ADC common registers These registers define the control and status registers common to master and slave ADCs: 16.6.1 ADC Common status register (ADCx_CSR) Address offset: 0x00 (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 This register provides an image of the status bits of the different ADCs. Nevertheless it is read-only and does not allow to clear the different status bits. Instead each status bit must be cleared by writing 0 to it in the corresponding ADCx_SR register. 31 30 Res. Res. 29 28 27 26 Res. Res. Res. JQOVF_ SLV 25 24 AWD3_ AWD2_ SLV SLV 23 AWD1_ SLV 22 21 JEOS_ JEOC_ SLV SLV 20 19 18 17 16 OVR_ SLV EOS_ SLV EOC_ SLV EOSMP_ SLV ADRDY_ SLV r r r Slave ADC r 15 14 Res. Res. 13 12 Res. Res. 11 10 Res. JQOVF_ MST r r 9 8 r 7 AWD3_ AWD2_ MST MST AWD1_ MST r r 6 5 JEOS_ JEOC_ MST MST r r 4 3 2 1 0 OVR_ MST EOS_ MST EOC_ MST EOSMP_ MST ADRDY_ MST r r r Master ADC r r r r r r r r Bits 31:27 Reserved, must be kept at reset value. Bit 26 JQOVF_SLV: Injected Context Queue Overflow flag of the slave ADC This bit is a copy of the JQOVF bit in the corresponding ADCx_ISR register. Bit 25 AWD3_SLV: Analog watchdog 3 flag of the slave ADC This bit is a copy of the AWD3 bit in the corresponding ADCx_ISR register. Bit 24 AWD2_SLV: Analog watchdog 2 flag of the slave ADC This bit is a copy of the AWD2 bit in the corresponding ADCx_ISR register. Bit 23 AWD1_SLV: Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADCx_ISR register. Bit 22 JEOS_SLV: End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADCx_ISR register. Bit 21 JEOC_SLV: End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADCx_ISR register. Bit 20 OVR_SLV: Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADCx_ISR register. Bit 19 EOS_SLV: End of regular sequence flag of the slave ADC . This bit is a copy of the EOS bit in the corresponding ADCx_ISR register. Bit 18 EOC_SLV: End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADCx_ISR register. Bit 17 EOSMP_SLV: End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADCx_ISR register. 528/1680 DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) Bit 16 ADRDY_SLV: Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADCx_ISR register. Bits 15:11 Reserved, must be kept at reset value. Bit 10 JQOVF_MST: Injected Context Queue Overflow flag of the master ADC This bit is a copy of the JQOVF bit in the corresponding ADCx_ISR register. Bit 9 AWD3_MST: Analog watchdog 3 flag of the master ADC This bit is a copy of the AWD3 bit in the corresponding ADCx_ISR register. Bit 8 AWD2_MST: Analog watchdog 2 flag of the master ADC This bit is a copy of the AWD2 bit in the corresponding ADCx_ISR register. Bit 7 AWD1_MST: Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADCx_ISR register. Bit 6 JEOS_MST: End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADCx_ISR register. Bit 5 JEOC_MST: End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADCx_ISR register. Bit 4 OVR_MST: Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADCx_ISR register. Bit 3 EOS_MST: End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADCx_ISR register. Bit 2 EOC_MST: End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADCx_ISR register. Bit 1 EOSMP_MST: End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADCx_ISR register. Bit 0 ADRDY_MST: Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADCx_ISR register. DocID024597 Rev 1 529/1680 536 Analog-to-digital converters (ADC) 16.6.2 RM0351 ADC common control register (ADCx_CCR) Address offset: 0x08 (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 CH18 SEL CH17 SEL VREF EN rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 Res. Res. Res. rw rw Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 DMA CFG Res. MDMA[1:0] rw rw rw DELAY[3:0] rw rw rw rw 21 20 19 18 PRESC[3:0] 17 CKMODE[1:0] DUAL[4:0] rw rw rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 CH18SEL: CH18 selection This bit is set and cleared by software to control the channel 18 of ADC1 and ADC3 0: VBAT channel disabled. 1: VBAT channel enabled Note: Software is allowed to write this bit only when the ADCs are disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Bit 23 CH17SEL: CH17 selection This bit is set and cleared by software to control the channel 17 of ADC1 and ADC3 0: Temperature sensor channel disabled 1: Temperature sensor channel enabled Note: Software is allowed to write this bit only when the ADCs are disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Bit 22 VREFEN: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel. 0: VREFINT channel disabled 1: VREFINT channel enabled Note: Software is allowed to write this bit only when the ADCs are disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). 530/1680 DocID024597 Rev 1 16 RM0351 Analog-to-digital converters (ADC) Bits 21:18 PRESC[3:0]: ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. 0000: input ADC clock not divided 0001: input ADC clock divided by 2 0010: input ADC clock divided by 4 0011: input ADC clock divided by 6 0100: input ADC clock divided by 8 0101: input ADC clock divided by 10 0110: input ADC clock divided by 12 0111: input ADC clock divided by 16 1000: input ADC clock divided by 32 1001: input ADC clock divided by 64 1010: input ADC clock divided by 128 1011: input ADC clock divided by 256 other: reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00. Bits 17:16 CKMODE[1:0]: ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): 00: CK_ADCx (x=123) (Asynchronous clock mode), generated at product level (refer to Section 8: Reset and clock control (RCC)) 01: HCLK/1 (Synchronous clock mode). This configuration must be enabled only if the AHB clock prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register) and if the system clock has a 50% duty cycle. 10: HCLK/2 (Synchronous clock mode) 11: HCLK/4 (Synchronous clock mode) In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: Software is allowed to write these bits only when the ADCs are disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Bits 15:14 MDMA[1:0]: Direct memory access mode for dual ADC mode This bit-field is set and cleared by software. Refer to the DMA controller section for more details. 00: MDMA mode disabled 01: reserved 10: MDMA mode enabled for 12 and 10-bit resolution 11: MDMA mode enabled for 8 and 6-bit resolution Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 13 DMACFG: DMA configuration (for dual ADC mode) ) This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN=1. 0: DMA One Shot Mode selected 1: DMA Circular Mode selected For more details, refer to Section : Managing conversions using the DMA Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). Bit 12 Reserved, must be kept at reset value. DocID024597 Rev 1 531/1680 536 Analog-to-digital converters (ADC) RM0351 Bits 11:8 DELAY: Delay between 2 sampling phases These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to Table 96 for the value of ADC resolution versus DELAY bits values. Note: Software is allowed to write these bits only when the ADCs are disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 DUAL[4:0]: Dual ADC mode selection These bits are written by software to select the operating mode. All the ADCs independent: 00000: Independent mode 00001 to 01001: Dual mode, master and slave ADCs working together 00001: Combined regular simultaneous + injected simultaneous mode 00010: Combined regular simultaneous + alternate trigger mode 00011: Combined Interleaved mode + injected simultaneous mode 00100: Reserved 00101: Injected simultaneous mode only 00110: Regular simultaneous mode only 00111: Interleaved mode only 01001: Alternate trigger mode only All other combinations are reserved and must not be programmed Note: Software is allowed to write these bits only when the ADCs are disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Table 96. DELAY bits versus ADC resolution 532/1680 DELAY bits 12-bit resolution 10-bit resolution 8-bit resolution 6-bit resolution 0000 1 * TADC_CLK 1 * TADC_CLK 1 * TADC_CLK 1 * TADC_CLK 0001 2 * TADC_CLK 2 * TADC_CLK 2 * TADC_CLK 2 * TADC_CLK 0010 3 * TADC_CLK 3 * TADC_CLK 3 * TADC_CLK 3 * TADC_CLK 0011 4 * TADC_CLK 4 * TADC_CLK 4 * TADC_CLK 4 * TADC_CLK 0100 5 * TADC_CLK 5 * TADC_CLK 5 * TADC_CLK 5 * TADC_CLK 0101 6 * TADC_CLK 6 * TADC_CLK 6 * TADC_CLK 6 * TADC_CLK 0110 7 * TADC_CLK 7 * TADC_CLK 7 * TADC_CLK 6 * TADC_CLK 0111 8 * TADC_CLK 8 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK 1000 9 * TADC_CLK 9 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK 1001 10 * TADC_CLK 10 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK 1010 11 * TADC_CLK 10 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK 1011 12 * TADC_CLK 10 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK others 12 * TADC_CLK 10 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK DocID024597 Rev 1 RM0351 Analog-to-digital converters (ADC) 16.6.3 ADC common regular data register for dual mode (ADCx_CDR) Address offset: 0x0C (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RDATA_SLV[15:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r RDATA_MST[15:0] r r Bits 31:16 RDATA_SLV[15:0]: Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Section 16.3.30: Dual ADC modes. The data alignment is applied as described in Section : Data register, data alignment and offset (ADCx_DR, OFFSETy, OFFSETy_CH, ALIGN)) Bits 15:0 RDATA_MST[15:0]: Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to Section 16.3.30: Dual ADC modes. The data alignment is applied as described in Section : Data register, data alignment and offset (ADCx_DR, OFFSETy, OFFSETy_CH, ALIGN)) In MDMA=0b11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0]. 16.6.4 ADC register map The following table summarizes the ADC registers. Table 97. ADC global register map Offset Register 0x000 - 0x0B4 Master ADC1 0x0B8 - 0x0FC Reserved 0x100 - 0x1B4 Slave ADC2 0x1B8 - 0x1FC Reserved 0x200 - 0x2B4 Single ADC3 0x2B8 - 0x2FC Reserved 0x300 - 0x30C Master and slave ADCs common registers DocID024597 Rev 1 533/1680 536 Analog-to-digital converters (ADC) RM0351 AWD3 AWD2 AWD1 JEOS JEOC OVR EOS EOC EOSMP ADRDY 0 0 0 0 0 0 0 0 0 0 0 OVRIE EOSIE EOCIE EOSMPIE ADRDYIE 0 0 0 0 0 Res. Res. Res. Res. JADSTP 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 534/1680 0 0 SMP1 [2:0] 0 0 0 SMP11 [2:0] 0 0 0 DMAEN 0 OVSR [2:0] DMACFG 0 0 0 0 0 0 0 SMP0 [2:0] 0 0 0 SMP10 [2:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L[3:0] 0 0 0 0 0 0 0 0 SQ10[4:0] 0 0 0 SQ5[4:0] 0 0 SQ16[4:0] 0 0 0 SQ11[4:0] 0 0 Res. 0 SQ6[4:0] 0 0 Res. 0 0 LT3[7:0] Res. Res. Res. 0 0 LT2[7:0] SQ1[4:0] 0 0 Res. Res. Res. Res. LT1[11:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JSQ3[4:0] 0 0 0 0 0 JSQ2[4:0] 0 0 0 DocID024597 Rev 1 0 0 JEXTEN[1:0] JSQ4[4:0] Res. Res. ADCx_JSQR 0 0 0 0 0 SQ15[4:0] 0 0 0 0 0 0 0 0 0 0 Res. Res. 0x4C 0 Reserved RES [1:0] JOVSE TROVS 0 Res. ROVSM 0 0 Reset value 0x440x48 0 regular RDATA[15:0] Res. 0x40 0 ROVSE EXTEN[1:0] Res. Res. 0 Reset value ADCx_DR 0 Res. Res. 0 Res. 0 Res. 0 Res. 0 0 OVSS[3:0] 0 0 0 Res. 0 Res. 0 Res. 0 0 0 0 0 SMP2 [2:0] 0 0 0 SMP12 [2:0] 0 0 0 0 SQ12[4:0] Res. 0 0 SQ7[4:0] Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 0 SMP3 [2:0] 0 0 0 SMP13 [2:0] 0 0 0 Res. 0 SQ13[4:0] 0 Res. 0 0 Res. Res. SQ8[4:0] 0 0 SQ2[4:0] 0 Res. 0 0 Res. 0 0 Res. 0 0 0 1 Res. Res. 0 0 1 Res. 0 Res. SQ3[4:0] 0 0 1 Res. 0 1 Res. 0 1 Res. Res. 0 1 Res. Res. 0 SQ14[4:0] Res. Res. Res. Res. Res. 0 Res. Res. 0 1 Res. 0x3C 1 1 Res. Reset value ADCx_SQR4 0 SQ9[4:0] 0 Res. ADCx_SQR3 Res. Reset value 0x38 Res. Res. Res. Res. 0x34 ADCx_SQR2 SQ4[4:0] 0 Res. Reset value 1 1 HT3[[7:0] Res. ADCx_SQR1 1 HT2[[7:0] 1 Res. 0x30 Reset value Reserved Res. 0x2C Res. 0x28 ADCx_TR3 Res. Reset value Res. 1 1 Res. 1 1 Res. 1 1 1 Res. Res. Res. Res. Res. ADCx_TR2 1 Res. 1 Res. 1 HT1[11:0] SMP4 [2:0] 0 0 0 SMP14 [2:0] 0 0 0 Res. 1 SMP5 [2:0] 0 0 0 SMP15 [2:0] 0 0 0 Res. Res. 1 Res. ADCx_TR1 SMP6 [2:0] 0 0 0 SMP16 [2:0] 0 0 0 Res. 1 Res. Res. Res. 1 Res. Res. Res. 1 Reset value Reserved Reset value 0x24 SMP7 [2:0] 0 0 0 SMP17 [2:0] 0 0 0 Res. Res. 0x20 Res. 0x1C Res. 0x18 SMP9 [2:0] 0 0 0 Res. Reset value ADCx_SMPR2 SMP8 [2:0] 0 0 0 SMP18 [2:0] 0 0 0 Res. Res. 0x14 Res. Reset value ADCx_SMPR1 EXTSEL [3:0] Res. Res. 0 Res. OVRMOD Res. 0 Res. CONT Res. AUTDLY 0 Res. Res. Res. Res. DISCEN 0 Res. 0 Res. 0 Res. Res. Res. Res. 0 Res. 0 DISCNUM [2:0] Res. Res. 0 Res. JDISCEN Res. 0 Res. JQM Res. AWD1SGL 0 Res. 0 Res. Res. Res. JAUTO JAWD1EN 0 AWD1EN 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. ADCx_CFGR2 Res. DEEPPWD ADVREGEN 1 Res. Reset value AWD1CH[4:0] Res. ADCx_CFGR Res. ADCAL ADCALDIF 0 JQDIS. 1 Res. 0x0C 0 Reset value Res. 0x0C 0 ADCx_CR 0x08 ADEN JEOCIE 0 ADDIS JEOSIE 0 ADSTART AWD1IE 0 Res. AWD2IE 0 ADSTP AWD3IE 0 Reset value JADSTART JQOVFIE 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADCx_IER 0x04 Res. Reset value ALIGN Res. JQOVF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADCx_ISR Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 Register Res. Offset Res. Table 98. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) JSQ1[4:0] 0 0 0 0 0 0 JEXTSEL [3:0] 0 0 0 0 JL[1:0] 0 0 0 RM0351 Analog-to-digital converters (ADC) 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 Res. Res. 0 Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET4[11:0] 0 0 0 0 Res. 0 0 0 0 0 0 0 0 0 0 Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 0 Res. Res. Res. 0 0 AWD3CH[18:0] DIFSEL[18:0] CALFACT_D[6:0] 0 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Reset value Res. 0xB4 Res. Reset value ADCx_CALFACT 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADCx_DIFSEL Res. 0xB0 Reserved Res. Reset value 0xA80xAC 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0xA4 0 AWD2CH[18:0] 0 Res. Reset value ADCx_AWD3CR 0 Res. Res. ADCx_AWD2CR 0 JDATA4[15:0] 0 Reserved Res. 0xA0 0 OFFSET3[11:0] Res. Res. Res. Res. Res. Res. Res. Reset value 0x8C0x9C 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x8C 0 JDATA3[15:0] 0 Res. Reset value ADCx_JDR4 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x88 0 JDATA2[15:0] 0 Res. Reset value ADCx_JDR3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x84 0 JDATA1[15:0] 0 Res. Reset value ADCx_JDR2 0 Res. Res. ADCx_JDR1 Res. Res. Res. Res. Res. Res. Res. 0 Reserved 0 OFFSET2[11:0] 0 Res. OFFSET4_ CH[4:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. OFFSET3_ CH[4:0] 0 0 Res. 0 Res. 0 Res. Res. 0 0 Res. Reset value 0 Res. ADCx_OFR4 0 Res. 0 OFFSET2_ CH[4:0] OFFSET1[11:0] 0 Res. Reset value 0 Res. ADCx_OFR3 0 Res. 0 0 Res. 0x80 Reset value 0 Res. 0x700x7C ADCx_OFR2 0 Res. 0x6C 0 Res. 0x68 Reset value OFFSET1_ CH[4:0] Res. 0x64 ADCx_OFR1 Res. 0x60 Res. Res. OFFSET1_EN Reserved OFFSET2_EN 0x500x5C OFFSET3_EN Register OFFSET4_EN Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 98. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) (continued) 0 0 0 DocID024597 Rev 1 0 CALFACT_S[6:0] 0 0 0 0 0 0 0 535/1680 536 Analog-to-digital converters (ADC) RM0351 0x0C Reset value ADCx_CDR Reset value 0 0 0 0 0 0 0 0 RDATA_SLV[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOS_MST EOC_MST EOSMP_MST ADRDY_MST OVR_MST JEOS_MST JEOC_MST 0 Res. AWD1_MST 0 Res. AWD2_MST 0 AWD3_MST Res. 0 0 DELAY[3:0] 0 0 0 0 Res. Res. DMACFG 0 master ADC1 0 0 0 0 JQOVF_MST Res. Res. Res. Res. 0 Res. MDMA[1:0] PRESC[3:0] ADRDY_SLV EOSMP_SLV 0 CKMODE[1:0] EOS_SLV EOC_SLV CH17SEL 0 OVR_SLV Res. slave ADC2 0 0 0 0 JEOS_SLV AWD1_SLV 0 JEOC_SLV AWD2_SLV 0 VREFEN AWD3_SLV 0 CH18SEL Res. JQOVF_SLV Res. 0 0 Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCx_CCR Res. 0x08 Reset value Reserved Res. 0x04 ADCx_CSR Res. 0x00 Register Res. Offset Res. Table 99. ADC register map and reset values (master and slave ADC common registers) offset =0x300) 0 0 0 RDATA_MST[15:0] 0 0 0 0 0 0 DUAL[4:0] 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. 536/1680 DocID024597 Rev 1 RM0351 Digital-to-analog converter (DAC) 17 Digital-to-analog converter (DAC) 17.1 Introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each with its own converter. In dual DAC channel mode, conversions could be done independently or simultaneously when both channels are grouped together for synchronous update operations. An input reference pin, VREF+ (shared with others analog peripherals) is available for better resolution. The DAC_OUTx pin can be used as general purpose Input/Output (GPIO) when the DAC output is disconnected from output pad and connected to on chip peripheral. The DAC’s output buffer can be optionally enabled to allow a high drive output current. An individual calibration can be applied on each DAC’s output channel. The DAC output channels support a low power mode; the sample and hold mode. 17.2 DAC main features The DAC main features are the following (see Figure 129: DAC channel block diagram) • Two DAC converters: one output channel each • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave and Triangular-wave generation • Dual DAC channel for independent or simultaneous conversions • DMA capability for each channel including DMA underrun error detection • External triggers for conversion • DAC output channel buffered/unbuffered modes • buffer offset calibration • The DAC_OUTx can be disconnected from output pin • Internal pin connection to on chip peripherals • Sample and hold mode for low power operation in STOP mode • Input voltage reference, VREF+ Figure 129 shows the block diagram of a DAC channel and Table 100 gives the pin description. DocID024597 Rev 1 537/1680 567 Digital-to-analog converter (DAC) RM0351 17.3 DAC functional description 17.3.1 DAC block diagram Figure 129. DAC channel block diagram s sZ&н KĨĨƐĞƚĐĂůŝďƌĂƚŝŽŶ ^ĂŵƉůĞΘ,ŽůĚZĞŐŝƐƚĞƌƐ ŽŶƚƌŽůƌĞŐŝƐƚĞƌƐ ΘůŽŐŝĐŚĂŶŶĞůϭ KdZ/Dϭϱ͗ϬďŝƚƐ d^DW>ϭ d,K>ϭ d/DϲͺdZ/' d/DϴͺdZ/' d/DϳͺdZ/' d/DϱͺdZ/' d/DϮͺdZ/' d/DϰͺdZ/' yd/ϵͺdZ/' ^tͺdZ/' DͺZĞƋƵĞƐƚ dZ/' dZ&Z^,ϭ džͺKZϭ ϭϮͲďŝƚ ĐŽŶǀĞƌƚĞƌϭ džͺKhdϭ d^>ϭϮ͗Ϭ ďŝƚƐ ƵĨĨĞƌϭ DKϭďŝƚƐ >^/ĐůŽĐŬ ŽŶƚƌŽůƌĞŐŝƐƚĞƌƐ ΘůŽŐŝĐŚĂŶŶĞůϮ d/DϲͺdZ/' d/DϴͺdZ/' d/DϳͺdZ/' d/DϱͺdZ/' d/DϮͺdZ/' d/DϰͺdZ/' yd/ϵͺdZ/' ^tͺdZ/' KdZ/DϮϱ͗ϬďŝƚƐ d^DW>Ϯ KŶͲĐŚŝƉ WĞƌŝƉŚĞƌĂůƐ d,K>Ϯ DͺZĞƋƵĞƐƚ dZ/' dZ&Z^,Ϯ džͺKZϮ ϭϮͲďŝƚ ĐŽŶǀĞƌƚĞƌϮ džͺKhdϮ d^>ϮϮ͗Ϭ ďŝƚƐ KĨĨƐĞƚĐĂůŝďƌĂƚŝŽŶ ^ĂŵƉůĞΘ,ŽůĚZĞŐŝƐƚĞƌƐ ƵĨĨĞƌϮ DKϮďŝƚƐ WϭƵƐ KŶͲĐŚŝƉ WĞƌŝƉŚĞƌĂůƐ s^^ 06Y9 1. The output mode controller switch between the normal mode in buffer/unbuffer configuration and the sample&hold mode The DAC includes : 538/1680 • Two output channels • The DAC_OUTx can be disconnected from output pin and used as ordinary GPIO • The DAC_OUTx can used internal pin connection to on-chip peripherals such as comparators and OPAMPs. • DAC output channel buffered or non buffered • Sample and hold block and registers using LSI clock source and operational in STOP mode for static conversion DocID024597 Rev 1 RM0351 Digital-to-analog converter (DAC) Table 100. DAC pins Name 17.3.2 Signal type Remarks VREF+ Input, analog reference positive The higher/positive reference voltage for the DAC, VDDAmin≤ VREF+ ≤ VDDA (refer to datasheet) VDDA Input, analog supply Analog power supply VSSA Input, analog supply ground Ground for analog power supply DAC_OUTx Analog output signal DAC channelx analog output DAC channel enable Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time tWAKEUP. Note: The ENx bit enables the analog DAC Channelx only. The DAC Channelx digital interface is enabled even if the ENx bit is reset. 17.3.3 DAC data format Depending on the selected configuration mode, the data have to be written into the specified register as described below: • Single DAC channelx, there are three possibilities: – 8-bit right alignment: the software has to load data into the DAC_DHR8Rx [7:0] bits (stored into the DHRx[11:4] bits) – 12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4] bits (stored into the DHRx[11:0] bits) – 12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0] bits (stored into the DHRx[11:0] bits) Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and stored into the corresponding DHRx (data holding registerx, which are internal non-memorymapped registers). The DHRx register is then loaded into the DORx register either automatically, by software trigger or by an external event trigger. DocID024597 Rev 1 539/1680 567 Digital-to-analog converter (DAC) RM0351 Figure 130. Data registers in single DAC channel mode 31 24 15 7 0 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14710 • Dual DAC channels, there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD [7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits) – 12-bit left alignment: data for DAC channel1 to be loaded into the DAC_DHR12LD [15:4] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be loaded into the DAC_DHR12LD [31:20] bits (stored into the DHR2[11:0] bits) – 12-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR12RD [11:0] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be loaded into the DAC_DHR12RD [27:16] bits (stored into the DHR2[11:0] bits) Depending on the loaded DAC_DHRyyyD register, the data written by the user is shifted and stored into DHR1 and DHR2 (data holding registers, which are internal non-memorymapped registers). The DHR1 and DHR2 registers are then loaded into the DOR1 and DOR2 registers, respectively, either automatically, by software trigger or by an external event trigger. Figure 131. Data registers in dual DAC channel mode 31 24 15 7 0 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14709 17.3.4 DAC conversion The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register (write to DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12RD or DAC_DHR12LD). Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR register is set) and a trigger occurs, the transfer is performed three APB1 clock cycles later. When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time tSETTLING that depends on the power supply voltage and the analog output load. 540/1680 DocID024597 Rev 1 RM0351 Digital-to-analog converter (DAC) Figure 132. Timing diagram for conversion with trigger disabled TEN = 0 APB1_CLK DHR DOR 0x1AC 0x1AC Output voltage available on DAC_OUT pin tSETTLING ai14711b 17.3.5 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and VREF+. The analog output voltages on each DAC channel pin are determined by the following equation: DOR DACoutput = V REF × -------------4096 17.3.6 DAC trigger selection If the TENx control bit is set, conversion can then be triggered by an external event (timer counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8 possible events will trigger conversion as shown in bits TSEL1[2:0] and TSEL2[2:0] in Section 17.5.1: DAC control register (DAC_CR). Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on the selected external interrupt line 9, the last data stored into the DAC_DHRx register are transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1 cycles after the trigger occurs. If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents. Note: 17.3.7 1 TSELx[2:0] bit cannot be changed when the ENx bit is set. 2 When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only one APB clock cycle. DMA request Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests. A DAC DMA request is generated when an external trigger (but not a software trigger) occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred into the DAC_DORx register. In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one DMA request is needed, you should set only the corresponding DMAENx bit. In this way, the application can manage both DAC channels in dual mode by using one DMA request and a unique DMA channel. DocID024597 Rev 1 541/1680 567 Digital-to-analog converter (DAC) RM0351 DMA underrun The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgement for the first external trigger is received (first request), then no new request is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set, reporting the error condition. The DAC channelx continues to convert old data. The software should clear the DMAUDRx flag by writing “1”, clear the DMAEN bit of the used DMA stream and re-initialize both DMA and DAC channelx to restart the transfer correctly. The software should modify the DAC trigger conversion frequency or lighten the DMA workload to avoid a new DMA underrun. Finally, the DAC conversion could be resumed by enabling both DMA data transfer and conversion trigger. For each DAC channlex, an interrupt is also generated if its corresponding DMAUDRIEx bit in the DAC_CR register is enabled. 17.3.8 Noise generation In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift register) is available. DAC noise generation is selected by setting WAVEx[1:0] to “01”. The preloaded value in LFSR is 0xAAA. This register is updated three APB1 clock cycles after each trigger event, following a specific calculation algorithm. Figure 133. DAC LFSR register calculation algorithm XOR X6 X X4 X0 X 12 11 10 9 8 7 6 5 4 3 2 1 0 12 NOR ai14713b The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register. If LFSR is 0x0000, a ‘1 is injected into it (antilock-up mechanism). It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits. 542/1680 DocID024597 Rev 1 RM0351 Digital-to-analog converter (DAC) Figure 134. DAC conversion (SW trigger enabled) with LFSR wave generation APB1_CLK DHR 0x00 0xD55 0xAAA DOR SWTRIG ai14714 Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DAC_CR register. 17.3.9 Triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three APB1 clock cycles after each trigger event. The value of this counter is then added to the DAC_DHRx register without overflow and the sum is stored into the DAC_DORx register. The triangle counter is incremented as long as it is less than the maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is reached, the counter is decremented down to 0, then incremented again and so on. It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits. Figure 135. DAC triangle wave generation N TIO TA EN EM CR )N N TIO TA EN EM CR $E -!-0X;= MAX AMPLITUDE $!#?$(2X BASE VALUE $!#?$(2X BASE VALUE AIC DocID024597 Rev 1 543/1680 567 Digital-to-analog converter (DAC) RM0351 Figure 136. DAC conversion (SW trigger enabled) with triangle wave generation APB1_CLK DHR 0xABE 0xABE DOR 0xABF 0xAC0 SWTRIG ai14714 Note: 1 The DAC trigger must be enabled for noise generation by setting the TENx bit in the DAC_CR register. 2 The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed. 17.3.10 DAC channel modes Each DAC channel can be configured in normal mode or sample and hold mode. The output buffer can be enabled to allow a high drive capability. Before enabling output buffer, the voltage offset needs to be calibrated. This calibration is performed at the factory (loaded after reset) and can be adjusted by software during application operation. Normal Mode In normal mode, there are four combinations, by changing the buffer state and by changing the DAC_OUTx pin interconnections. To enable the output buffer, the MODEx[2:0] bits in DAC_MCR register should be: – 000: DAC is connected to the external pin – 001: DAC is connected to external pin and to on-chip peripherals To disable the output buffer, the MODEx[2:0] bits in DAC_MCR register should be: – 010: DAC is connected to the external pin – 011: DAC is connected to on-chip peripherals Sample and Hold Mode In sample and Hold mode, the DAC core converts data on a triggered conversion, then, holds the converted voltage on a capacitor. When not converting, the DAC cores and buffer are completely turned off between samples and the DAC output is tri-stated, therefore reducing the overall power consumption. A new stabilization period (Tstab-BON or Tstab-BOFF depending on buffer state) is needed before each new conversion. In this mode, the DAC core and all corresponding logic and registers are driven by the lowspeed clock (LSI : Low Speed Internal oscillator) in addition to the APB bus clock, allowing to use the DAC channels in deep Low power modes such as STOP mode. 544/1680 DocID024597 Rev 1 RM0351 Digital-to-analog converter (DAC) The sample/hold mode operations can be divided into 3 phases: 7. Sample phase: the sample/hold element is charged to the desired voltage. The charging time depends on capacitor value (internal or external, selected by the user). The sampling time is configured with the TSAMx[9:0] bits in DAC_SHSRx register. During the write of the TSAMx[9:0] bits; the BWSTx bit in DAC_SR register is set to 1 to synchronize between both clocks domains (APB and low speed clock) and allowing the software to change the value of sample phase during the DAC channel operation 8. Hold phase: the DAC output channel is tri-stated, the DAC core and the buffer are turned off, to reduce the current consumption. The hold time is configured with the THOLDx[9:0] bits in DAC_SHHR register 9. Refresh phase: the refresh time is configured with the TREFx[7:0] bits in DAC_SHRR register The timings for the three phases above are in units of LSI clocks. As example, to configure a Sample time of 350µs, Hold time of 2ms and Refresh time of 100µs assuming LSI ~32KHz is selected: 12 cycles are required for sample phase: SAMx[9:0] = 11, 62 cycles are required for hold phase: THOLDx[9:0] = 62, and 4 cycles are required for refresh period: TREFx[7:0] = 4. In this example, the power consumption is reduced by almost a factor of 15 versus Normal modes. The Formulas to compute the right sample and refresh timings are described in the table below, the Hold time depends on the leakage current (not yet specified, moment when this user specification is written) Table 101. Sample and refresh timings Note: Buffer State tsampling (1)(3) trefresh (2)(3) Enable Tstab-BON + (10*RBON*Cload) Tstab-BON + (RBON*Cload)*ln(2*Nlsb) Disable Tstab-BOFF + ( 10*RBOFF*Cload) Tstab-BOFF + (RBOFF*Cload)*ln(2*Nlsb) 1 In the above formula the settling to the desired code value with ½ LSB or accuracy requires 10 constant time for 12 bits resolution. For 8 bits resolution, the settling time is 7 constant time. 2 The tolerated voltage drop during the hold phase “Vd” is represented by the number of LSBs after the capacitor discharging with the output leakage current. The settling back to the desired value with ½ LSB error accuracy requires ln(2*Nlsb) constant time of the DAC. 3 The parameters “Tstab-BON“,“Tstab-BON“, “RBON” and “RBOFF” are specified in the datasheet DocID024597 Rev 1 545/1680 567 Digital-to-analog converter (DAC) RM0351 Figure 137. DAC sample and hold mode phases diagram Vd LSI DAC ON ON ON Like in normal mode, the sample and hold mode has different configurations. To enable the output buffer, the MODEx[2:0] bits in DAC_MCR register should be: – 100: DAC is connected to the external pin – 101: DAC is connected to external pin and to on chip peripherals To disabled the output buffer, The MODEx[2:0] bits in DAC_MCR register should be: – 110: DAC is connected to external pin and to on chip peripherals – 111: DAC is connected to on chip peripherals When MODEx[2:0] bits in DAC_MCR register is equal to 111. An internal capacitor “Cloadint“ will hold the voltage output of the DAC Core and then drive it to on-chip peripherals. All sample and hold phases are interruptible and any change in DAC_DHRx will trigger immediately a new sample phase. Table 102. Channel output modes summary MODEx[2:0] 0 0 0 0 0 1 0 1 0 0 1 1 546/1680 Mode Buffer Enabled Normal mode Disabled Output connections Connected to external pin Connected to external pin and to on chip-peripherals (ex, comparators) Connected to external pin Connected to on chip peripherals (ex, comparators) DocID024597 Rev 1 RM0351 Digital-to-analog converter (DAC) Table 102. Channel output modes summary MODEx[2:0] 1 0 0 1 0 1 1 1 0 1 1 1 17.3.11 Mode Buffer Enabled Sample & hold mode Disabled Output connections Connected to external pin Connected to external pin and to on chip peripherals (ex, comparators) Connected to external pin and to on chip peripherals (ex, comparators) Connected to on chip peripherals (ex, comparators) DAC channel buffer calibration The transfer function for an N-bit digital-to-analog converter (DAC) is V out = ( ( D ⁄ 2 N – 1 ) × G × V ref ) + V OS Where Vout is the analog output, D is the digital input, G is the gain, Vref is the nominal fullscale voltage, and Vos is the offset voltage.For an ideal DAC channel, G = 1 and Vos = 0. Due to output buffer characteristics, the voltage offset may differ from part-to-part and introduce an absolute offset error on the analog output. To compensate the Vos, a calibration is required by a trimming technique. The calibration is only valid when the DAC channelx is operating with buffer enabled (MODEx[2:0] = 000b or 001b or 100b or 101b). if applied in other modes when the buffer is off, it has no effect. During the calibration: • The buffer output will be disconnected from the pin internal/external connections and put in tristate mode (HiZ), • The buffer will act as a comparator, to sense the middle-code value 0x800 and compare it to VREF+/2 signal thru an internal bridge, then toggle its output signal to 0 or 1 depending on the comparison result (CAL_FLAGx bit) Two calibration techniques are provided: • Factory trimming (always enabled) The DAC buffer offset is factory trimmed. The default value of OTRIMx[4:0] bits in DAC_CCR register is the factory trimming value and it is loaded once DAC digital interface is reset. • User trimming The user trimming can be done when the operating conditions differs from nominal factory trimming conditions and in particular when VDD/VDDA voltage, temperature, VREF+ values change and can be done at any point during application by software. Note: Refer to the datasheet for more details of the Nominal factory trimming conditions Note: Also, when VDD/VDDA is removed (exemple the MCU enters in STANDBY or VBAT modes) the calibration is required. DocID024597 Rev 1 547/1680 567 Digital-to-analog converter (DAC) RM0351 The steps to perform a user trimming calibration are as below: 1. If the DAC channel is active, Write 0 to ENx bit in DAC_CR to disable the channel. 2. Select a mode where the buffer is enabled, by writing to DACx_MCR register, MODEx[2:0] = 000b or 001b or 100b or 101b, 3. Write DACx_DHR12Rx[11:0] with the middle code: 0x800 value, 4. Start the DAC channelx calibration, by setting the CENx bit in DACx_CR register to 1, 5. Apply a trimming algorithm: a) Write a code into OTRIMx[4:0] bits, starting by 00000b b) Wait for tOFFTRIMmax delay c) Check if CAL_FLAGx bit in DACx_SR is set to 1 d) if CAL_FLAGx is set to 1 the trimming code OTRIMx[4:0] is found and will be used during operation to compensate the output value, else increment OTRIMx[4:0] and repeat sub-steps from (a) to (d) again. The software algorithm may use either a successive approximation or dichotomy techniques to compute and set the content of OTRIMx[4:0] bits in a faster way, The commutation/toggle of CAL_FLAGx bit indicates that the offset is correctly compensated and the corresponding trim code must be kept in the OTRIMx[4:0] bits in DAC_CCR register. Note: 1 A tOFFTRIMmax delay must be respected between the write to the OTRIMx[4:0] bits and the read of the CAL_FLAGx bit in DAC_SR register in order to get a correct value.This parameter is specified into datasheet electrical characteristics section. 2 If the VDD/VDDA, VREF+ and temperature conditions will not change during the MCU operation while it enters more often in standby and VBAT mode, the software may store the OTRIMx[4:0] bits found in the first user calibration in the flash or in back-up registers. then to load/write them directly when the MCU power is back again thus avoiding to wait for a new calibration time. 17.3.12 Dual DAC channel conversion To efficiently use the bus bandwidth in applications that require the two DAC channels at the same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A unique register access is then required to drive both DAC channels at the same time. Eleven possible conversion modes are possible using the two DAC channels and these dual registers. All the conversion modes can nevertheless be obtained using separate DHRx registers if needed. All modes are described in the paragraphs below. Independent trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: 548/1680 • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits • Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) DocID024597 Rev 1 RM0351 Digital-to-analog converter (DAC) When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1 (three APB1 clock cycles later). When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2 (three APB1 clock cycles later). Independent trigger with single LFSR generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits • Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask value in the MAMPx[3:0] bits • Load the dual DAC channel data into the desired DHR register (DHR12RD, DHR12LD or DHR8RD) When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB clock cycles later). Then the LFSR1 counter is updated. When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB clock cycles later). Then the LFSR2 counter is updated. Independent trigger with different LFSR generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits • Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR masks values in the MAMP1[3:0] and MAMP2[3:0] bits • Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB clock cycles later). Then the LFSR1 counter is updated. When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB clock cycles later). Then the LFSR2 counter is updated. DocID024597 Rev 1 549/1680 567 Digital-to-analog converter (DAC) RM0351 Independent trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits • Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum amplitude value in the MAMPx[3:0] bits • Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated. When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated. Independent trigger with different triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits • Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits • Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated. When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated. Simultaneous software start To configure the DAC in this conversion mode, the following sequence is required: • Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) In this configuration, one APB1 clock cycle later, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and DAC_DOR2, respectively. 550/1680 DocID024597 Rev 1 RM0351 Digital-to-analog converter (DAC) Simultaneous trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits • Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and DAC_DOR2, respectively (after three APB1 clock cycles). Simultaneous trigger with single LFSR generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits • Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask value in the MAMPx[3:0] bits • Load the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or DHR8RD) When a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The LFSR2 counter is then updated. Simultaneous trigger with different LFSR generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits • Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR mask values using the MAMP1[3:0] and MAMP2[3:0] bits • Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The LFSR2 counter is then updated. DocID024597 Rev 1 551/1680 567 Digital-to-analog converter (DAC) RM0351 Simultaneous trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits • Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum amplitude value using the MAMPx[3:0] bits • Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated. At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated. 17.3.13 Simultaneous trigger with different triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits • Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits • Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB clock cycles later). Then the DAC channel1 triangle counter is updated. At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). Then the DAC channel2 triangle counter is updated. 17.4 DAC low power modes Table 103. Effect of low power modes on DAC Mode 552/1680 Description Sleep No effect, DAC used with DMA Stop DAC remains active with a static value, if sample and hold mode is selected using LSI clock DocID024597 Rev 1 RM0351 Digital-to-analog converter (DAC) 17.5 DAC registers Refer to Section 1 on page 61 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 17.5.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 Res. CEN2 DMAU DRIE2 DMA EN2 rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CEN1 DMAU DRIE1 DMA EN1 TEN1 Res. EN1 rw rw rw Res. 27 26 25 24 MAMP2[3:0] rw rw 22 21 WAVE2[1:0] MAMP1[3:0] rw 23 rw rw 19 TSEL2[2:0] WAVE1[1:0] rw 20 TSEL1[2:0] rw rw rw 18 17 16 TEN2 Res. EN2 rw rw rw Bit 31 Reserved, must be kept at reset value Bit 30 CEN2: DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 0: DAC channel 2 in normal operating mode 1: DAC channel 2 in calibration mode Bit 29 DMAUDRIE2: DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. 0: DAC channel2 DMA underrun interrupt disabled 1: DAC channel2 DMA underrun interrupt enabled Bit 28 DMAEN2: DAC channel2 DMA enable This bit is set and cleared by software. 0: DAC channel2 DMA mode disabled 1: DAC channel2 DMA mode enabled Bits 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63 0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 DocID024597 Rev 1 553/1680 567 Digital-to-analog converter (DAC) RM0351 Bits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 00: wave generation disabled 01: Noise wave generation enabled 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 000: Timer 6 TRGO event 001: Timer 8 TRGO event 010: Timer 7 TRGO event 011: Timer 5 TRGO event 100: Timer 2 TRGO event 101: Timer 4 TRGO event 110: External line9 111: Software trigger Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). Bit 18 TEN2: DAC channel2 trigger enable This bit is set and cleared by software to enable/disable DAC channel2 trigger 0: DAC channel2 trigger disabled and data written into the DAC_DHRx register are transferred one APB1 clock cycle later to the DAC_DOR2 register 1: DAC channel2 trigger enabled and data from the DAC_DHRx register are transferred three APB1 clock cycles later to the DAC_DOR2 register Note: When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DOR2 register takes only one APB1 clock cycle. Bit 17 Reserved, must be kept at reset value. Bit 16 EN2: DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. 0: DAC channel2 disabled 1: DAC channel2 enabled Bit 15 Reserved, must be kept at reset value. Bit 14 CEN1: DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 0: DAC channel 1 in normal operating mode 1: DAC channel 1 in calibration mode Bit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. 0: DAC channel1 DMA Underrun Interrupt disabled 1: DAC channel1 DMA Underrun Interrupt enabled Bit 12 DMAEN1: DAC channel1 DMA enable This bit is set and cleared by software. 0: DAC channel1 DMA mode disabled 1: DAC channel1 DMA mode enabled 554/1680 DocID024597 Rev 1 RM0351 Digital-to-analog converter (DAC) Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63 0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 Bits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. 00: wave generation disabled 01: Noise wave generation enabled 1x: Triangle wave generation enabled Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). Bits 5:3 TSEL1[2:0]: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. 000: Timer 6 TRGO event 001: Timer 8 TRGO event 010: Timer 7 TRGO event 011: Timer 5 TRGO event 100: Timer 2 TRGO event 101: Timer 4 TRGO event 110: External line9 111: Software trigger Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). Bit 2 TEN1: DAC channel1 trigger enable This bit is set and cleared by software to enable/disable DAC channel1 trigger. 0: DAC channel1 trigger disabled and data written into the DAC_DHRx register are transferred one APB1 clock cycle later to the DAC_DOR1 register 1: DAC channel1 trigger enabled and data from the DAC_DHRx register are transferred three APB1 clock cycles later to the DAC_DOR1 register Note: When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DOR1 register takes only one APB1 clock cycle. Bit 1 Reserved, must be kept at reset value. Bit 0 EN1: DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1. 0: DAC channel1 disabled 1: DAC channel1 enabled DocID024597 Rev 1 555/1680 567 Digital-to-analog converter (DAC) 17.5.2 RM0351 DAC software trigger register (DAC_SWTRGR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWTRIG2 SWTRIG1 w w Bits 31:2 Reserved, must be kept at reset value. Bit 1 SWTRIG2: DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. 0: No trigger 1: Trigger Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. Bit 0 SWTRIG1: DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. 0: No trigger 1: Trigger Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register. 17.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw 15 14 13 12 Res. Res. Res. Res. DACC1DHR[11:0] rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 17.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 556/1680 DocID024597 Rev 1 RM0351 Digital-to-analog converter (DAC) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 DACC1DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw 3 2 1 0 Res. Res. Res. Res. rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. Bits 3:0 Reserved, must be kept at reset value. 17.5.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw rw rw rw DACC1DHR[7:0] rw rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 17.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. rw rw rw rw rw rw rw rw rw rw DACC2DHR[11:0] rw rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. DocID024597 Rev 1 557/1680 567 Digital-to-analog converter (DAC) 17.5.7 RM0351 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 DACC2DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw 3 2 1 0 Res. Res. Res. Res. rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. Bits 3:0 Reserved, must be kept at reset value. 17.5.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 rw rw rw 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. DACC2DHR[7:0] rw rw rw rw rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 17.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 23 rw rw rw rw rw rw 11 10 9 8 7 6 21 20 19 18 17 16 rw rw rw rw rw rw 5 4 3 2 1 0 rw rw rw rw rw DACC2DHR[11:0] DACC1DHR[11:0] rw 558/1680 22 rw rw rw rw rw DocID024597 Rev 1 rw RM0351 Digital-to-analog converter (DAC) Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 17.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 DACC2DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 DACC1DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw 19 18 17 16 Res. Res. Res. Res. 3 2 1 0 Res. Res. Res. Res. rw Bits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. Bits 19:16 Reserved, must be kept at reset value. Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. Bits 3:0 Reserved, must be kept at reset value. DocID024597 Rev 1 559/1680 567 Digital-to-analog converter (DAC) 17.5.11 RM0351 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw DACC2DHR[7:0] rw rw rw rw DACC1DHR[7:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 17.5.12 DAC channel1 data output register (DAC_DOR1) Address offset: 0x2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r 15 14 13 12 Res. Res. Res. Res. DACC1DOR[11:0] r r r r r r r Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC1DOR[11:0]: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. 17.5.13 DAC channel2 data output register (DAC_DOR2) Address offset: 0x30 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r 15 14 13 12 Res. Res. Res. Res. DACC2DOR[11:0] r 560/1680 r r r r DocID024597 Rev 1 r r RM0351 Digital-to-analog converter (DAC) Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC2DOR[11:0]: DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. 17.5.14 DAC status register (DAC_SR) Address offset: 0x34 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BWST2 CAL_ FLAG2 DMAU DR2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r r rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAU DR1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CAL_ BWST1 FLAG1 r r rc_w1 Bit 31 BWST2: DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2 , It is cleared by hardware when the write operation of DAC_SHSR2 is complete. ( It takes about 3 LSI periods of synchronization). 0:There is no write operation of DAC_SHSR2 ongoing : DAC_SHSR2 can be written 1:There is a write operation of DAC_SHSR2 ongoing : DAC_SHSR2 cannot be written Bit 30 CAL_FLAG2: DAC Channel 2 calibration offset status This bit is set and cleared by hardware 0: calibration trimming value is greater than the offset correction value 1: calibration trimming value is lower than the offset correction value Bit 29 DMAUDR2: DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 0: No DMA underrun error condition occurred for DAC channel2 1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is driving DAC channel2 conversion at a frequency higher than the DMA service capability rate) Bits 28:16 Reserved, must be kept at reset value. Bit 15 BWST1: DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1 , It is cleared by hardware when the write operation of DAC_SHSR1 is complete. ( It takes about 3LSI periods of synchronization). 0:There is no write operation of DAC_SHSR1 ongoing : DAC_SHSR1 can be written 1:There is a write operation of DAC_SHSR1 ongoing : DAC_SHSR1 cannot be written DocID024597 Rev 1 561/1680 567 Digital-to-analog converter (DAC) RM0351 Bit 14 CAL_FLAG1: DAC Channel 1 calibration offset status This bit is set and cleared by hardware 0: calibration trimming value is greater than the offset correction value 1: calibration trimming value is lower than the offset correction value Bit 13 DMAUDR1: DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 0: No DMA underrun error condition occurred for DAC channel1 1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) Bits 12:0 Reserved, must be kept at reset value. 17.5.15 DAC calibration control register (DAC_CCR) Address offset: 0x38 Reset value: 0x00XX 00XX 31 30 29 28 27 26 25 24 23 22 21 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20 19 18 17 16 1 0 17 16 OTRIM2[4:0] rw 4 3 2 OTRIM1[4:0] rw Bits 31:21 Reserved, must be kept at reset value. Bits 20:16 OTRIM2[4:0]: DAC Channel 2 offset trimming value Bits 15:5 Reserved, must be kept at reset value. Bits 4:0 OTRIM1[4:0]: DAC Channel 1 offset trimming value 17.5.16 DAC mode control register (DAC_MCR) Address offset: 0x3C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18 MODE2[2:0] rw 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 2 1 MODE1[2:0] rw 562/1680 DocID024597 Rev 1 0 RM0351 Digital-to-analog converter (DAC) Bits 31:19 Reserved, must be kept at reset value. Bits 18:16 MODE2[2:0]: DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode : – DAC Channel 2 in normal Mode 000: DAC Channel 2 is connected to external pin with Buffer enabled 001: DAC Channel 2 is connected to external pin and to on chip peripherals with buffer enabled 010: DAC Channel 2 is connected to external pin with buffer disabled 011: DAC Channel 2 is connected to on chip peripherals with Buffer disabled – DAC Channel 2 in sample & hold mode 100: DAC Channel 2 is connected to external pin with Buffer enabled 101: DAC Channel 2 is connected to external pin and to on chip peripherals with Buffer enabled 110: DAC Channel 2 is connected to external pin and to on chip peripherals with Buffer disabled 111: DAC Channel 2 is connected to on chip peripherals with Buffer disabled Bits 15:3 Reserved, must be kept at reset value. Bits 0:2 MODE1[2:0]: DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode : – DAC Channel 1 in normal Mode 000: DAC Channel 1 is connected to external pin with Buffer enabled 001: DAC Channel 1 is connected to external pin and to on chip peripherals with Buffer enabled 010: DAC Channel 1 is connected to external pin with Buffer disabled 011: DAC Channel 1 is connected to on chip peripherals with Buffer disabled – DAC Channel 1 in sample & hold mode 100: DAC Channel 1 is connected to external pin with Buffer enabled 101: DAC Channel 1 is connected to external pin and to on chip peripherals with Buffer enabled 110: DAC Channel 1 is connected to external pin and to on chip peripherals with Buffer disabled 111: DAC Channel 1 is connected to on chip peripherals with Buffer disabled 17.5.17 DAC Sample and Hold sample time register 1 (DAC_SHSR1) Address offset: 0x40 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DocID024597 Rev 1 563/1680 567 Digital-to-analog converter (DAC) 15 14 13 12 11 10 Res. Res. Res. Res. Res. Res. RM0351 9 8 7 6 5 4 3 2 1 0 rw rw rw rw TSAMPLE1[9:0] rw rw rw rw rw rw Bits 31:10 Reserved, must be kept at reset value. Bits 9:0 TSAMPLE1[9:0]: DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored. Note: It represents the number of low-speed (LSI) clocks to perform a sample phase. Sampling time = (TSAMPLE1[9:0] + 1) x T LSI 17.5.18 DAC Sample and Hold sample time register 2 (DAC_SHSR2) Address offset: 0x44 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 9 8 7 6 5 4 3 2 1 0 rw rw rw rw 15 14 13 12 11 10 Res. Res. Res. Res. Res. Res. TSAMPLE2[9:0] rw rw rw rw rw rw Bits 31:10 Reserved, must be kept at reset value. Bits 9:0 TSAMPLE2[9:0]: DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored. Note: It represents the number of low-speed (LSI) clocks to perform a sample phase. Sampling time = (TSAMPLE1[9:0] + 1) x T LSI 17.5.19 DAC Sample and Hold hold time register (DAC_SHHR) Address offset: 0x48 Reset value: 0x0001 0001 31 30 29 28 27 26 Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 Res. Res. Res. Res. Res. Res. 25 24 23 22 21 20 19 18 17 16 3 2 1 0 THOLD2[9:0] rw 9 8 7 6 5 4 THOLD1[9:0] rw 564/1680 DocID024597 Rev 1 RM0351 Digital-to-analog converter (DAC) Bits 31:26 Reserved, must be kept at reset value. Bits 25:16 THOLD2[9:0]: DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0] ) x T LSI Bits 15:10 Reserved, must be kept at reset value. Bits 9:0 THOLD1[9:0]: DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0] ) x T LSI Note: These bits can be written only when the DAC channel is disabled and in normal operating mode(when bit ENx=0 and bit CEN2x=0 in the DAC_CR register ). If ENx=1 or CENx=1 the write operation is ignored. 17.5.20 DAC Sample and Hold refresh time register (DAC_SHRR) Address offset: 0x4C Reset value: 0x0001 0001 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 2 1 0 TREFRESH2[7:0] rw 7 6 5 4 3 TREFRESH1[7:0] rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 TREFRESH2[7:0]: DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0] ) x T LSI Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 TREFRESH1[7:0]: DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0] ) x T LSI Note: These bits can be written only when the DAC channel is disabled and in normal operating mode(when bit ENx=0 and bit CEN2x=0 in the DAC_CR register ). If ENx=1 or CENx=1 the write operation is ignored. DocID024597 Rev 1 565/1680 567 0x34 566/1680 DAC_SR Reset value 0 0 0 DocID024597 Rev 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Reset value Res. Reset value Res. 0 Res. 0 Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. 0 Reset value 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 DACC2DHR[7:0] 0 0 0 0 0 0 0 DACC2DHR[11:0] 0 0 0 0 0 0 0 DACC1DHR[11:0] 0 0 0 0 0 0 0 0 0 0 Res. 0 0 Res. 0 0 Res. 0 Res. 0 0 DACC2DHR[11:0] 0 0 0 0 0 0 0 Res. 0 Res. DACC1DHR[11:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. 0 0 DACC1DHR[11:0] 0 0 0 0 0 0 0 Res. 0 Res. 0 0 Res. 0 Res. Res. Res. 0 Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMAEN1 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 SWTRIG1 Reset value SWTRIG2 WAVE1[2:0] 0 EN1 Res. TEN1 TSEL1 [2:0] Res. CEN1 DMAUDRIE1 0 Res. Res. EN2 Res. TEN2 0 Res. Res. Res. WAVE2[2:0] 0 MAMP1[3:0] Res. 0 Res. Reset value Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Reset value Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. DMAUDR1 Reset value CAL_FLAG1 0 Res. DACC2DHR[11:0] Res. Res. Reset value Res. Res. Reset value BWST1 Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. Res. DMAEN2 0 Res. Res. Res. Res. Res. DMAUDRIE2 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CEN2 0 Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. DAC_ DHR8RD Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 TSEL2 [2:0] Res. 0 Res. 0 Res. 0 Res. DACC2DHR[11:0] Res. Res. Res. 0 Res. Res. Res. 0 Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. Res. Res. 0 MAMP2[3:0] Res. Res. Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Reset value Res. DAC_ DHR12LD Res. DAC_DOR2 Res. Reset value Res. DAC_DOR1 Res. DAC_ DHR12RD Res. 0x30 DAC_ DHR8R2 Res. 0x2C DAC_ DHR12L2 Res. 0x28 DAC_ DHR12R2 Res. 0x24 DAC_ DHR8R1 Res. 0x20 DMAUDR2 0x1C DAC_ DHR12L1 Res. 0x18 DAC_ DHR12R1 Res. 0x14 DAC_ SWTRGR Res. 0x10 Res. 0x0C Res. Reset value Res. 0x08 DAC_CR Res. 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. 17.5.21 Res. 0x00 CAL_FLAG2 Offset BWST2 Digital-to-analog converter (DAC) RM0351 DAC register map Table 104 summarizes the DAC registers. Table 104. DAC register map 0 0 0 DACC1DHR[11:0] DACC1DHR[7:0] DACC2DHR[7:0] DACC1DHR[7:0] DACC1DOR[11:0] 0 0 0 0 0 0 DACC2DOR[11:0] RM0351 Digital-to-analog converter (DAC) Reset value 0 TREFRESH2[7:0] 0 0 0 0 0 0 0 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Res. Res. Res. Res. Res. 1 X X MODE1 [2:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 THOLD1[9:0] 0 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. DAC_SHRR Res. 0x4C Res. Reset value THOLD2[9:0] 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DAC_SHHR Res. 0x48 X TSAMPLE2[9:0] 0 Res. Reset value X TSAMPLE1[9:0] 0 Res. DAC_SHSR2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Reset value 0x44 Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 OTRIM1[4:0] X Res. X X MODE2 [2:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DAC_SHSR1 Res. 0x40 Res. Reset value X Res. X Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DAC_MCR Res. 0x3C X Res. Reset value OTRIM2[4:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. DAC_CCR Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x38 Register Res. Offset Res. Table 104. DAC register map 0 0 0 0 0 TREFRESH1[7:0] 0 0 0 0 0 0 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. DocID024597 Rev 1 567/1680 567 Voltage reference buffer (VREFBUF) RM0351 18 Voltage reference buffer (VREFBUF) 18.1 Introduction The STM32L4x6 devices embed a voltage reference buffer which can be used as voltage reference for ADCs, DACs and also as voltage reference for external components through the VREF+ pin. When the VREF+ is double-bonded with VDDA in a package, the voltage reference buffer is not available and must be kept disable (refer to datasheet for packages pinout description). 18.2 VREFBUF functional description The internal voltage reference buffer supports two voltages, which are configured with VRS bit in the VREFBUF_CSR register: • VREF_OUT1 around 2.048 V. This requires VDDA equal to or higher than 2.4 V. • VREF_OUT2 around 2.5 V. This requires VDDA equal to or higher than 2.8 V. The internal voltage reference can be configured in four different modes depending on ENVR and HIZ bits configuration. These modes are provided in the table below: Table 105. VREFBUF buffer modes ENVR HIZ 0 0 VREFBUF buffer OFF: – VREF+ pin pulled-down to VSSA 0 1 External voltage reference mode (default value): – VREFBUF buffer OFF – VREF+ pin floating 1 0 Internal voltage reference mode: – VREFBUF buffer ON – VREF+ pin connected to VREFBUF buffer output 1 Hold mode: – VREFBUF buffer ON – VREF+ pin floating. The voltage is held with the external capacitor 1 VREFBUF buffer configuration After enabling the VREFBUF buffer by setting ENVR bit and clearing HIZ bit in the VREFBUF_CSR register, the user must wait until VRR bit is set, meaning that the voltage reference output has reached its expected value. 18.3 VREFBUF registers 18.3.1 VREFBUF control and status register (VREFBUF_CSR) Address offset: 0x00 Reset value: 0x0000 0002 568/1680 DocID024597 Rev 1 RM0351 Voltage reference buffer (VREFBUF) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res VRR VRS HIZ ENVR r rw rw rw Bits 31:4 Reserved, must be kept at reset value. Bit 3 VRR: Voltage reference buffer ready 0: the voltage reference buffer output is not ready. 1: the voltage reference buffer output reached the requested level. Bit 2 VRS: Voltage reference scale This bit selects the value generated by the voltage reference buffer. 0: Voltage reference set to VREF_OUT1 (around 2.048 V). 1: Voltage reference set to VREF_OUT2 (around 2.5 V). Bit 1 HIZ: High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. 0: VREF+ pin is internally connected to the voltage reference buffer output. 1: VREF+ pin is high impedance. Refer to Table 105: VREFBUF buffer modes for modes descriptions depending on ENVR bit configuration. Bit 0 ENVR: Voltage reference buffer enable This bit is used to enable the voltage reference buffer. 0: Internal voltage reference disable. 1: Internal voltage reference enable. 18.3.2 VREFBUF calibration control register (VREFBUF_CCR) Address offset: 0x04 Reset value: 0x0000 00XX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 5 4 3 2 1 0 rw rw 15 14 13 12 11 10 9 8 7 6 Res Res Res Res Res Res Res Res Res Res TRIM[5:0] rw rw rw rw Bits 31:6 Reserved, must be kept at reset value. Bits 5:0 TRIM[5:0]: Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash during production test. Writing into these bits allows to tune the internal reference buffer voltage. DocID024597 Rev 1 569/1680 570 Voltage reference buffer (VREFBUF) 18.3.3 RM0351 VREFBUF register map The following table gives the VREFBUF register map and the reset values. Reset value DocID024597 Rev 1 Res. VRS HIZ ENVR Res. 0 0 1 0 TRIM[5:0] x Refer to Section 2.2.2 on page 68 for the register boundary addresses. 570/1680 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VREFBUF_CCR Res. 0x04 Res. Reset value VRR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VREFBUF_CSR Res. 0x00 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 106. VREFBUF register map and reset values x x x x x RM0351 Comparator (COMP) 19 Comparator (COMP) 19.1 Introduction The device embeds two ultra-low power comparators COMP1, and COMP2 The comparators can be used for a variety of functions including: 19.2 • Wake-up from low-power mode triggered by an analog signal, • Analog signal conditioning, • Cycle-by-cycle current control loop when combined with a PWM output from a timer. COMP main features • Each comparator has configurable plus and minus inputs used for flexible voltage selection: – Multiplexed I/O pins – DAC Channel1 and Channel2 – Internal reference voltage and three submultiple values (1/4, 1/2, 3/4) provided by scaler (buffered voltage divider) • Programmable hysteresis • Programmable speed / consumption • The outputs can be redirected to an I/O or to timer inputs for triggering: – Break events for fast PWM shutdowns • Comparator outputs with blanking source • The two comparators can be combined in a window comparator • Each comparator has interrupt generation capability with wake-up from Sleep and Stop modes (through the EXTI controller) DocID024597 Rev 1 571/1680 581 Comparator (COMP) RM0351 19.3 COMP functional description 19.3.1 COMP block diagram The block diagram of the comparators is shown in Figure 138: Comparators block diagram. Figure 138. Comparators block diagram *3,2 DOWHUQDWH IXQFWLRQ &203[B,136(/ &203[B32/ &203[B,13 &203[B,13,2V &203[B287 &203[ &203[B ,106(/ &203[B9$/8( &203[B,10 &203[B,10,2V :DNHXS(;7,OLQH LQWHUUXSW 3RODULW\VHOHFWLRQ 7,0(56 '$&B&+ '$&B&+ 95(),17 95(),17 95(),17 95(),17 19.3.2 069 COMP pins and internal signals The I/Os used as comparators inputs must be configured in analog mode in the GPIOs registers. The comparator output can be connected to the I/Os using the alternate function channel given in “Alternate function mapping” table in the datasheet. The output can also be internally redirected to a variety of timer input for the following purposes: • Emergency shut-down of PWM signals, using BKIN and BKIN2 inputs • Cycle-by-cycle current control, using OCREF_CLR inputs • Input capture for timing measures It is possible to have the comparator output simultaneously redirected internally and externally. Table 107. COMP1 input plus assignment COMP1_INP COMP1_INPSEL PC5 0 PB2 1 Table 108. COMP1 input minus assignment COMP1_INM 572/1680 COMP1_INMSEL[2:0] ¼ VREFINT 000 ½ VREFINT 001 DocID024597 Rev 1 RM0351 Comparator (COMP) Table 108. COMP1 input minus assignment (continued) COMP1_INM COMP1_INMSEL[2:0] ¾ VREFINT 010 VREFINT 011 DAC Channel1 100 DAC Channel2 101 PB1 110 PC4 111 Table 109. COMP2 input plus assignment COMP2_INP COMP2_INPSEL PB4 0 PB6 1 Table 110. COMP2 input minus assignment COMP2_INM 19.3.3 COMP2_INMSEL[2:0] ¼ VREFINT 000 ½ VREFINT 001 ¾ VREFINT 010 VREFINT 011 DAC Channel1 100 DAC Channel2 101 PB3 110 PB7 111 COMP reset and clocks The COMP clock provided by the clock controller is synchronous with the APB2 clock. There is no clock enable control bit provided in the RCC controller. Reset and clock enable bits are common for COMP and SYSCFG. Note: Important: The polarity selection logic and the output redirection to the port works independently from the APB2 clock. This allows the comparator to work even in Stop mode. 19.3.4 Comparator LOCK mechanism The comparators can be used for safety purposes, such as over-current or thermal protection. For applications having specific functional safety requirements, it is necessary to insure that the comparator programming cannot be altered in case of spurious register access or program counter corruption. DocID024597 Rev 1 573/1680 581 Comparator (COMP) RM0351 For this purpose, the comparator control and status registers can be write-protected (readonly). Once the programming is completed, the COMPxLOCK bit can be set to 1. This causes the whole register to become read-only, including the COMPxLOCK bit. The write protection can only be reset by a MCU reset. 19.3.5 Window comparator The purpose of window comparator is to monitor the analog voltage if it is within specified voltage range defined by lower and upper threshold. Two embedded comparators can be utilized to create window comparator. The monitored analog voltage is connected to the non-inverting (plus) inputs of comparators connected together and the upper and lower threshold voltages are connected to the inverting (minus) inputs of the comparators. Two non-inverting inputs can be connected internally together by enabling WINMODE bit to save one IO for other purpose. Figure 139. Window mode &203[B,136(/ &203[B,13 &203[B,13,2V &203[ &203[B,10 &203[B,106(/ &203[B,10,2V ,QWHUQDOVRXUFHV &203[B,136(/ :,102'( &203\B,13 &203\B,13,2V &203\ &203\B,106(/ &203\B,10 &203\B,10,2V ,QWHUQDOVRXUFHV 069 19.3.6 Hysteresis The comparator includes a programmable hysteresis to avoid spurious output transitions in case of noisy signals. The hysteresis can be disabled if it is not needed (for instance when exiting from low-power mode) to be able to force the hysteresis value using external components. 574/1680 DocID024597 Rev 1 RM0351 Comparator (COMP) Figure 140. Comparator hysteresis ).0 ).).- 6 HYS T #/-0?/54 -36 19.3.7 Comparator output blanking function The purpose of the blanking function is to prevent the current regulation to trip upon short current spikes at the beginning of the PWM period (typically the recovery current in power switches anti parallel diodes).It consists of a selection of a blanking window which is a timer output compare signal. The selection is done by software (refer to the comparator register description for possible blanking signals). Then, the complementary of the blanking signal is ANDed with the comparator output to provide the wanted comparator output. See the example provided in the figure below. Figure 141. Comparator output blanking 3:0 &XUUHQWOLPLW &XUUHQW 5DZFRPSRXWSXW %ODQNLQJZLQGRZ )LQDOFRPSRXWSXW &RPSRXW &RPSRXW WR7,0B%.« %ODQN 069 DocID024597 Rev 1 575/1680 581 Comparator (COMP) 19.3.8 RM0351 COMP power and speed modes COMP1 and COMP2 power consumption versus propagation delay can be adjusted to have the optimum trade-off for a given application. The bits COMPx_PWR_MODE[1:0] in COMPx_CSR registers can be programmed as follows: 00: High speed / full power 01: Medium speed / medium power 10: Low speed / low-power 11: Very-low speed / ultra-low-power 19.4 COMP low-power modes Comparator behavior in the low power modes Mode 19.5 Description Sleep No effect on the comparators. Comparator interrupts cause the device to exit the Sleep mode. Stop No effect on the comparators. Comparator interrupts cause the device to exit the Stop mode. COMP interrupts The comparator outputs are internally connected to the Extended interrupts and events controller. Each comparator has its own EXTI line and can generate either interrupts or events. The same mechanism is used to exit from low-power modes. Refer to Interrupt and events section for more details. To enable the COMPx interrupt, it is required to follow this sequence: 1. Configure and enable the EXTI line corresponding to the COMPx output event in interrupt mode and select the rising, falling or both edges sensitivity 2. Configure and enable the NVIC IRQ channel mapped to the corresponding EXTI lines 3. Enable the COMPx Table 111. Interrupt control bits Interrupt event Event flag Enable control bit Exit from Sleep mode Exit from Stop modes Exit from Standby mode COMP1 output VALUE in COMP1_CSR through EXTI yes yes N/A COMP2 output VALUE in COMP2_CSR through EXTI yes yes N/A 576/1680 DocID024597 Rev 1 RM0351 Comparator (COMP) 19.6 COMP registers 19.6.1 Comparator 1 control and status register (COMP1_CSR) The COMP1_CSR is the Comparator 1 control/status register. It contains all the bits /flags related to comparator1. Address offset: 0x00 System reset value: 0x0000 0000 31 LOCK 30 VALUE rs r 15 14 POLA RITY Res. 29 28 27 26 25 24 23 22 21 SCAL EN BRG EN Res. 20 19 18 Res. Res. Res. Res. Res. Res. rw rw 13 12 11 10 9 8 7 6 Res. INP SEL. INMSEL PWRMODE rw rw rw Res. Res. Res. Res. Res. rw 17 BLANKING 16 HYST rw 5 4 rw 3 2 1 0 Res. EN rw Bit 31 LOCK: COMP1_CSR register lock bit This bit is set by software and cleared by a hardware system reset. It locks the whole content of the comparator 1 control register, COMP1_CSR[31:0]. 0: COMP1_CSR[31:0] for comparator 1 are read/write 1: COMP1_CSR[31:0] for comparator 1 are read-only Bit 30 VALUE: Comparator 1 output status bit This bit is read-only. It reflects the current comparator 1 output taking into account POLARITY bit effect. Bits 29:24 Reserved, must be kept at reset value. Bit 23 SCALEN: Voltage scaler enable bit This bit is set and cleared by software. This bit enable the outputs of the VREFINT divider available on the minus input of the Comparator 1. 0: Bandgap scaler disable (if SCALEN bit of COMP2_CSR register is also reset) 1: Bandgap scaler enable Bit 22 BRGEN: Scaler bridge enable This bit is set and cleared by software (only if LOCK not set). This bit enable the bridge of the scaler. 0: Scaler resistor bridge disable (if BRGEN bit of COMP2_CSR register is also reset) 1: Scaler resistor bridge enable If SCALEN is set and BRGEN is reset, BG voltage reference is available but not 1/4BGAP, 1/2BGAP, 3/4 BGAP. BGAP value is sent instead of 1/4BGAP, 1/2BGAP, 3/4 BGAP. If SCALEN and BRGEN are set, 1/4 BGAP 1/2BGAP 3/4BGAP and BGAP voltage references are available. Bit 21 Reserved, must be kept at reset value DocID024597 Rev 1 577/1680 581 Comparator (COMP) RM0351 Bits 20:18 BLANKING[2:0]: Comparator 1 blanking source selection bits These bits select which timer output controls the comparator 1 output blanking. 000: No blanking 001: TIM1 OC5 selected as blanking source 010: TIM2 OC3 selected as blanking source 100: TIM3 OC3 selected as blanking source All other values: reserved Bits 17:16 HYST[1:0]: Comparator 1 hysteresis selection bits These bits are set and cleared by software (only if LOCK not set). They select the Hysteresis voltage of the comparator 1. 00: No hysteresis 01: Low hysteresis 10: Medium hysteresis 11: High hysteresis Bit 15 POLARITY: Comparator 1 polarity selection bit This bit is set and cleared by software (only if LOCK not set). It inverts Comparator 1 polarity. 0: Comparator 1 output value not inverted 1: Comparator 1output value inverted Bits 14:8 Reserved, must be kept at reset value. Bit 7 INPSEL: Comparator1 input plus selection bit This bit is set and cleared by software (only if LOCK not set). 0: external IO - PC5 1: PB2 Bits 6:4 INMSEL: Comparator 1 input minus selection bits These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of comparator 1. 000 = 1/4 VREFINT 001 = 1/2 VREFINT 010 = 3/4 VREFINT 011 = VREFINT 100 = DAC Channel1 101 = DAC Channel2 110 = PB1 111 = PC4 Bits 3:2 PWRMODE[1:0]: Power Mode of the comparator 1 These bits are set and cleared by software (only if LOCK not set). They control the power/speed of the Comparator 1. 00: High speed 01 or 10: Medium speed 11: Ultra low power Bit 1 Reserved, must be kept cleared. Bit 0 EN: Comparator 1 enable bit This bit is set and cleared by software (only if LOCK not set). It switches on Comparator1. 0: Comparator 1 switched OFF 1: Comparator 1 switched ON 578/1680 DocID024597 Rev 1 RM0351 Comparator (COMP) 19.6.2 Comparator 2 control and status register (COMP2_CSR) The COMP2_CSR is the Comparator 2 control/status register. It contains all the bits /flags related to comparator2. Address offset: 0x04 System reset value: 0x0000 0000 31 LOCK 30 VALUE rs r 15 14 POLA RITY rw Res. 29 28 27 26 25 24 23 22 21 SCAL EN BRG EN Res. 20 19 18 Res. Res. Res. Res. Res. Res. rw rw 13 12 11 10 9 8 7 6 Res. WIN MODE Res. INP SEL. INMSEL PWRMODE rw rw rw Res. Res. Res. rw 17 BLANKING 16 HYST rw 5 4 rw 3 2 1 0 Res. EN rw Bit 31 LOCK: CSR register lock bit This bit is set by software and cleared by a hardware system reset. It locks the whole content of the comparator 2 control register, COMP2_CSR[31:0]. 0: COMP2_CSR[31:0] for comparator 2 are read/write 1: COMP2_CSR[31:0] for comparator 2 are read-only Bit 30 VALUE: Comparator 2 output status bit This bit is read-only. It reflects the current comparator 2 output taking into account POLARITY bit effect. Bits 29:24 Reserved, must be kept at reset value Bit 23 SCALEN: Voltage scaler enable bit This bit is set and cleared by software. This bit enable the outputs of the VREFINT divider available on the minus input of the Comparator 2. 0: Bandgap scaler disable (if SCALEN bit of COMP1_CSR register is also reset) 1: Bandgap scaler enable Bit 22 BRGEN: Scaler bridge enable This bit is set and cleared by software (only if LOCK not set). This bit enable the bridge of the scaler. 0: Scaler resistor bridge disable (if BRGEN bit of COMP1_CSR register is also reset) 1: Scaler resistor bridge enable If SCALEN is set and BRGEN is reset, BG voltage reference is available but not 1/4BGAP, 1/2BGAP, 3/4 BGAP. BGAP value is sent instead of 1/4BGAP, 1/2BGAP, 3/4 BGAP. If SCALEN and BRGEN are set, 1/4 BGAP 1/2BGAP 3/4BGAP and BGAP voltage references are available. Bit 21 Reserved, must be kept at reset value Bits 20:18 BLANKING[2:0]: Comparator 2 blanking source selection bits These bits select which timer output controls the comparator 2 output blanking. 000: No blanking 001: TIM3 OC4 selected as blanking source 010: TIM8 OC5 selected as blanking source 100: TIM15 OC1 selected as blanking source All other values: reserved DocID024597 Rev 1 579/1680 581 Comparator (COMP) RM0351 Bits 17:16 HYST[1:0]: Comparator 2 hysteresis selection bits These bits are set and cleared by software (only if LOCK not set). Select the Hysteresis voltage of the comparator 2. 00: No hysteresis 01: Low hysteresis 10: Medium hysteresis 11: High hysteresis Bit 15 POLARITY: Comparator 2 polarity selection bit This bit is set and cleared by software (only if LOCK not set). It inverts Comparator 2 polarity. 0: Comparator 2 output value not inverted 1: Comparator 2output value inverted Bits 14:10 Reserved, must be kept at reset value. Bit 9 WINMODE: Windows mode selection bit This bit is set and cleared by software (only if LOCK not set). This bit selects the window mode of the comparators. If set, both positive inputs of comparators will be connected together. 0: Input plus of Comparator 2 is not connected to Comparator 1 1: Input plus of Comparator 2 is connected with input plus of Comparator 1 Bit 8 Reserved, must be kept at reset value. Bit 7 INPSEL: Comparator 1 input plus selection bit This bit is set and cleared by software (only if LOCK not set). 0: PB4 1: PB6 Bits 6:4 INMSEL: Comparator 2 input minus selection bits These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of comparator 2. 000 = 1/4 VREFINT 001 = 1/2 VREFINT 010 = 3/4 VREFINT 011 = VREFINT 100 = DAC Channel1 101 = DAC Channel2 110 = PB3 111 = PB7 Bits 3:2 PWRMODE[1:0]: Power Mode of the comparator 2 These bits are set and cleared by software (only if LOCK not set). They control the power/speed of the Comparator 2. 00: High speed 01 or 10: Medium speed 11: Ultra low power Bit 1 Reserved, must be kept cleared. Bit 0 EN: Comparator 2 enable bit This bit is set and cleared by software (only if LOCK not set). It switches oncomparator2. 0: Comparator 2 switched OFF 1: Comparator 2 switched ON 580/1680 DocID024597 Rev 1 RM0351 19.6.3 Comparator (COMP) COMP register map The following table summarizes the comparator registers. 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 EN Res. 0 PWRMODE 0 EN PWRMODE INMSEL INPSEL Res. WINMODE Res. 0 INMSEL Res. INPSEL. Res. Res. Res. Res. Res. Res. POLARITY. HYST. 0 0 Res. 0 0 Res. 0 0 Res. 0 POLARITY. 0 Res. HYST BLANKING 0 BLANKING 0 Res. BRGEN. 0 0 Res. 0 BRGEN. Res. SCALEN Res. Res. 0 SCALEN. Res. Res. 0 Res. 0 Res. Reset value Res. COMP2_CSR Res. 0 Res. 0 Res. Reset value Res. LOCK VALUE 0x04 COMP1_CSR LOCK 0x00 Register VALUE Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 112. COMP register map and reset values 0 Refer to Section 2.2.2 on page 68 for the register boundary addresses. DocID024597 Rev 1 581/1680 581 Operational amplifiers (OPAMP) RM0351 20 Operational amplifiers (OPAMP) 20.1 Introduction The device embeds two operational amplifiers with two inputs and one output each. The three I/Os can be connected to the external pins, this enables any type of external interconnections. The operational amplifier can be configured internally as a follower or as an amplifier with a non-inverting gain ranging from 2 to 16. The positive input can be connected to the internal DAC. The output can be connected to the internal ADC. 20.2 20.3 OPAMP main features • Rail-to-rail input and output voltage range • Low input bias current (down to 1 nA) • Low input offset voltage (1.5 mV after calibration, 3 mV with factory calibration) • Low-power mode (current consumption reduced to 30 µA instead of 100 µA) • Fast wakeup time (10 µs in normal mode, 30 µs in low-power mode) • Gain bandwidth of 1.6 MHz OPAMP functional description The OPAMP has several modes. Each OPAMP can be individually enabled, when disabled the output is high-impedance. When enabled, it can be in calibration mode, all input and output of the OPAMP are then disconnected, or in functional mode. There are two functional modes, the low-power mode or the normal mode. In functional mode the inputs and output of the OPAMP are connected as described in the Section 20.3.3: Signal routing. 20.3.1 OPAMP reset and clocks The operational amplifier clock is necessary for accessing the registers. When the application does not need to have read or write access to those registers, the clock can be switched off using the peripheral clock enable register (see OPAMPEN bit in Section 8.4.19: APB1 peripheral clock enable register 1 (RCC_APB1ENR1)). The bit OPAEN enables and disables the OPAMP operation. The OPAMP registers configurations should be changed before enabling the OPAEN bit in order to avoid spurious effects on the output. When the output of the operational amplifier is no more needed the operational amplifier can be disabled to save power. All the configurations previously set (including the calibration) are maintained while OPAMP is disabled. 582/1680 DocID024597 Rev 1 RM0351 20.3.2 Operational amplifiers (OPAMP) Initial configuration The default configuration of the operational amplifier is a functional mode where the three IOs are connected to external pins. In the default mode the operational amplifier uses the factory trimming values. See electrical characteristics section of the datasheet for factory trimming conditions, usually the temperature is 30 °C and the voltage is 3 V. The trimming values can be adjusted, see Section 20.3.5: Calibration for changing the trimming values. The default configuration uses the normal mode, which provides the highest performance. Bit OPALPM can be set in order to switch the operational amplifier to low-power mode and reduced performance. Both normal and low-power mode characteristics are defined in the section “electrical characteristics” of the datasheet. Before utilization, the bit OPA_RANGE of OPAMP_CSR must be set to 1 if VDDA is above 2.4V, or kept at 0 otherwise. As soon as the OPAEN bit in OPAMP_CSR register is set, the operational amplifier is functional. The two input pins and the output pin are connected as defined in Section 20.3.3: Signal routing and the default connection settings can be changed. Note: The inputs and output pins must be configured in analog mode (default state) in the corresponding GPIOx_MODER register. 20.3.3 Signal routing The routing for the operational amplifier pins is determined by OPAMP_CSR register. The connections of the two operational amplifiers (OPAMP1 and OPAMP2) are described in the table below. Table 113. Operational amplifier possible connections Signal Pin OPAMP1_VINM PA1 or dedicated pin(1) OPAMP1_OUT or PGA controlled by bits OPAMODE and VM_SEL. OPAMP1_VINP PA0 DAC1_OUT1 controlled by bit VP_SEL. ADC1_IN8 ADC2_IN8 The pin is connected when the OPAMP is enabled. The ADC input is controlled by ADC. OPAMP1_VOUT PA3 Internal comment OPAMP2_VINM PA7 or dedicated pin(1) OPAMP2_OUT or PGA controlled by bits OPAMODE and VM_SEL. OPAMP2_VINP PA6 DAC1_OUT2 controlled by bit VP_SEL ADC1_IN15 ADC2_IN15 The pin is connected when the OPAMP is enabled. The ADC input is controlled by ADC. OPAMP2_VOUT PB0 1. The dedicated pin is only available on BGA132 package. This configuration provides the lowest input bias current (see datasheet). DocID024597 Rev 1 583/1680 595 Operational amplifiers (OPAMP) 20.3.4 RM0351 OPAMP modes The operational amplifier inputs and outputs are all accessible on terminals. The amplifiers can be used in multiple configuration environments: • Standalone mode (external gain setting mode) • Follower configuration mode • PGA modes Note: The amplifier output pin is directly connected to the output pad to minimize the output impedance. It cannot be used as a general purpose I/O, even if the amplifier is configured as a PGA and only connected to the ADC channel. Note: The impedance of the signal must be maintained below a level which avoids the input leakage to create significant artifacts (due to a resistive drop in the source). Please refer to the electrical characteristics section in the datasheet for further details. Standalone mode (external gain setting mode) The procedure to use the OPAMP in standalone mode is presented hereafter. Starting from the default value of OPAMP_CSR, and the default state of GPIOx_MODER, configure bit OPA_RANGE according the VDDA voltage. As soon as the OPAEN bit is set, the two input pins and the output pin are connected to the operational amplifier. This default configuration uses the factory trimming values and operates in normal mode (highest performance). The behavior of the OPAMP can be changed as follows: • OPALPM can be set to “operational amplifier low-power” mode in order to save power. • USERTRIM can be set to modify the trimming values for the input offset. Figure 142. Standalone mode: external gain setting mode 670 *3,2 '$&B287 $'& *3,2 069 584/1680 DocID024597 Rev 1 RM0351 Operational amplifiers (OPAMP) Follower configuration mode The procedure to use the OPAMP in follower mode is presented hereafter. • configure OPAMODE bits as “internal follower” • configure VP_SEL bits as “GPIO connected to VINP”. • As soon as the OPAEN bit is set, the signal on pin OPAMP_VINP is copied to pin OPAMP_VOUT. Note: The pin corresponding to OPAMP_VINM is free for another usage. Note: The signal on the operational amplifier output is also seen as an ADC input. As a consequence, the OPAMP configured in follower mode can be used to perform impedance adaptation on input signals before feeding them to the ADC input, assuming the input signal frequency is compatible with the operational amplifier gain bandwidth specification. Figure 143. Follower configuration 670 *3,2 '$&B287 $'& *3,2 $OZD\VFRQQHFWHGWR 23$03RXWSXW FDQEH XVHGGXULQJGHEXJ 069 DocID024597 Rev 1 585/1680 595 Operational amplifiers (OPAMP) RM0351 Programmable Gain Amplifier mode The procedure to use the OPAMP to amplify the amplitude of an input signal is presented hereafter. • configure OPAMODE bits as “internal PGA enabled”, • configure PGA_GAIN bits as “internal PGA Gain 2, 4, 8 or 16”, • configure VM_SEL bits as “inverting not externally connected”, • configure VP_SEL bits as “GPIO connected to VINP”. As soon as the OPAEN bit is set, the signal on pin OPAMP_VINP is amplified by the selected gain and visible on pin OPAMP_VOUT. Note: To avoid saturation, the input voltage should stay below VDDA divided by the selected gain. Figure 144. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used 670 *3,2 '$&B287 $'& *3,2 $OZD\VFRQQHFWHGWR 23$03RXWSXW FDQEH XVHGGXULQJGHEXJ 069 586/1680 DocID024597 Rev 1 RM0351 Operational amplifiers (OPAMP) Programmable Gain Amplifier mode with external filtering The procedure to use the OPAMP to amplify the amplitude of an input signal, with an external filtering, is presented hereafter. • configure OPAMODE bits as “internal PGA enabled”, • configure PGA_GAIN bits as “internal PGA Gain 2, 4, 8 or 16”, • configure VM_SEL bits as “GPIO connected to VINM”, • configure VP_SEL bits as “GPIO connected to VINP”. Any external connection on VINP can be used in parallel with the internal PGA, for example a capacitor can be connected between VOUT and VINM for filtering purpose (see datasheet for the value of resistors used in the PGA resistor network). Figure 145. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for filtering 670 *3,2 '$&B287 $'& *3,2 $OORZVRSWLRQDO ORZSDVV ILOWHULQJ (TXLYDOHQWWR 069 1. The gain depends on the cut-off frequency. 20.3.5 Calibration At startup, the trimming values are initialized with the preset ‘factory’ trimming value. Each operational amplifier offset can be trimmed by the user. Specific registers allow to have different trimming values for normal mode and for low-power mode. The aim of the calibration is to cancel as much as possible the OPAMP inputs offset voltage. The calibration circuitry allows to reduce the inputs offset voltage to less than +/-1.5 mV within stable voltage and temperature conditions. For each operational amplifier and each mode two trimming values need to be trimmed, one for N differential pair and one for P differential pair. There are two registers for trimming the offsets for each operational amplifiers, one for normal mode (OPAMP_OTR) and one low-power mode (OPAMP_LPOTR). Each register is composed of five bits for P differential pair trimming and five bits for N differential pair trimming. These are the ‘user’ values. DocID024597 Rev 1 587/1680 595 Operational amplifiers (OPAMP) RM0351 The user is able to switch from ‘factory’ values to ‘user’ trimmed values using the USERTRIM bit in the OPAMP_CSR register. This bit is reset at startup and so the ‘factory’ value are applied by default to the OPAMP trimming registers. User is liable to change the trimming values in calibration or in functional mode. The offset trimming registers are typically configured after the calibration operation is initialized by setting bit CALON to 1. When CALON = 1 the inputs of the operational amplifier are disconnected from the functional environment. • Setting CALSEL to 1 initializes the offset calibration for the P differential pair (low voltage reference used). • Resetting CALSEL to 0 initializes the offset calibration for the N differential pair (high voltage reference used). When CALON = 1, the bit CALOUT will reflect the influence of the trimming value selected by CALSEL and OPALPM. When the value of CALOUT switches between two consecutive trimming values, this means that those two values are the best trimming values. The CALOUT flag needs up to 1 ms after the trimming value is changed to become steady (see tOFFTRIMmax delay specification in the electrical characteristics section of the datasheet). Note: The closer the trimming value is to the optimum trimming value, the longer it takes to stabilize (with a maximum stabilization time remaining below 1 ms in any case). Table 114. Operating modes and calibration Control bits Output Mode 588/1680 OPAEN OPALPM CALON CALSEL VOUT CALOUT flag Normal operating mode 1 0 0 X analog 0 Low-power mode 1 1 0 X analog 0 Power down 0 X X X Z 0 Offset cal high for normal mode 1 0 1 0 analog X Offset cal low for normal mode 1 0 1 1 analog X Offset cal high for low-power mode 1 1 1 0 analog X Offset cal low for low-power mode 1 1 1 1 analog X DocID024597 Rev 1 RM0351 Operational amplifiers (OPAMP) Calibration procedure Here are the steps to perform a full calibration of either one of the operational amplifiers: 1. Select correct OPA_RANGE in OPAMP_CSR, then set the OPAEN bit in OPAMP_CSR to 1 to enable the operational amplifier. 2. Set the USERTRIM bit in the OPAMP_CSR register to 1. 3. Choose a calibration mode (refer to Table 114: Operating modes and calibration). The steps 3 to 4 will have to be repeated 4 times. For the first iteration select – Normal mode, offset cal high (N differential pair) The above calibration mode correspond to OPALPM=0 and CALSEL=0 in the OPAMP_CSR register. 4. Increment TRIMOFFSETN[4:0] in OPAMP_OTR starting from 00000b until CALOUT changes to 1 in OPAMP_CSR. Note: CALOUT will switch from 0 to 1 for offset cal high and from 1 to 0 for offset cal low. Note: Between the write to the OPAMP_OTR register and the read of the CALOUT value, make sure to wait for the tOFFTRIMmax delay specified in the electrical characteristics section of the datasheet, to get the correct CALOUT value. The commutation means that the offset is correctly compensated and that the corresponding trim code must be saved in the OPAMP_OTR register. Repeat steps 3 to 4 for: – Normal_mode and offset cal low – Low power mode and offset cal high – Low power mode and offset cal low If a mode is not used it is not necessary to perform the corresponding calibration. All operational amplifier can be calibrated at the same time. Note: During the whole calibration phase the external connection of the operational amplifier output must not pull up or down currents higher than 500 µA. 20.4 OPAMP low-power modes Table 115. Effect of low-power modes on the OPAMP Mode Description Sleep No effect. Stop 1 No effect, OPAMP registers content is kept. Stop 2 The OPAMP are not available. Standby The OPAMP registers are powered down and must be re-initialized after exiting Standby. DocID024597 Rev 1 589/1680 595 Operational amplifiers (OPAMP) RM0351 20.5 OPAMP registers 20.5.1 OPAMP1 control/status register (OPAMP1_CSR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OPA_ RANGE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12 11 10 9 8 7 6 5 4 3 2 Res. VP_ SEL rw 15 14 13 CAL OUT USER TRIM CAL SEL CALON r rw rw rw rw VM_SEL rw Res. Res. rw PGA_GAIN OPAMODE rw rw rw w 1 0 OPA LPM OPAEN rw rw Bit 31 OPA_RANGE: Operational amplifier power supply range for stability All AOP must be in power down to allow AOP-RANGE bit write. It applies to all AOP embedded in the product. 0: Low range (VDDA < 2.4V) 1: High range (VDDA > 2.4V) Bits 30:16 Reserved, must be kept at reset value. Bit 15 CALOUT: Operational amplifier calibration output During calibration mode offset is trimmed when this signal toggle. Bit 14 USERTRIM: allows to switch from ‘factory’ AOP offset trimmed values to AOP offset ‘user’ trimmed values This bit is active for both mode normal and low-power. 0: ‘factory’ trim code used 1: ‘user’ trim code used Bit 13 CALSEL: Calibration selection 0: NMOS calibration (200mV applied on OPAMP inputs) 1: PMOS calibration (VDDA-200mV applied on OPAMP inputs) Bit 12 CALON: Calibration mode enabled 0: Normal mode 1: Calibration mode (all switches opened by HW) Bit 11 Reserved, must be kept at reset value. Bit 10 VP_SEL: Non inverted input selection 0: GPIO connected to VINP 1: DAC connected to VINP Bits 9:8 VM_SEL: Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. 00: GPIO connected to VINM (valid also in PGA mode for filtering) 01: Dedicated low leakage input, (available only on BGA132) connected to VINM (valid also in PGA mode for filtering) 1x: Inverting input not externally connected. These configurations are valid only when OPAMODE = 10 (PGA mode) Bits 7:6 Reserved, must be kept at reset value. 590/1680 DocID024597 Rev 1 RM0351 Operational amplifiers (OPAMP) Bits 5:4 PGA_GAIN: Operational amplifier Programmable amplifier gain value 00: internal PGA Gain 2 01: internal PGA Gain 4 10: internal PGA Gain 8 11: internal PGA Gain 16 Bits 3:2 OPAMODE: Operational amplifier PGA mode 00: internal PGA disable 01: internal PGA disable 10: internal PGA enable, gain programmed in PGA_GAIN 11: internal follower Bit 1 OPALPM: Operational amplifier Low Power Mode The operational amplifier must be disable to change this configuration. 0: operational amplifier in normal mode 1: operational amplifier in low-power mode Bit 0 OPAEN: Operational amplifier Enable 0: operational amplifier disabled 1: operational amplifier enabled 20.5.2 OPAMP1 offset trimming register in normal mode (OPAMP1_OTR) Address offset: 0x04 Reset value: 0x0000 XXXX (factory trimmed values) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12 11 10 9 8 4 3 2 1 0 rw rw 15 14 13 Res. Res. Res. TRIMOFFSETP rw rw rw rw 7 6 5 Res. Res. Res. rw TRIMOFFSETN rw rw rw Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 TRIMOFFSETP[4:0]: Trim for PMOS differential pairs Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 TRIMOFFSETN[4:0]: Trim for NMOS differential pairs 20.5.3 OPAMP1 offset trimming register in low-power mode (OPAMP1_LPOTR) Address offset: 0x08 Reset value: 0x0000 XXXX (factory trimmed values) DocID024597 Rev 1 591/1680 595 Operational amplifiers (OPAMP) RM0351 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12 11 10 9 8 4 3 2 1 0 15 14 13 Res. Res. Res. TRIMLPOFFSETP rw rw rw rw 7 6 5 Res. Res. Res. rw TRIMLPOFFSETN rw rw rw rw rw Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 TRIMLPOFFSETP[4:0]: Low-power mode trim for PMOS differential pairs Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 TRIMLPOFFSETN[4:0]: Low-power mode trim for NMOS differential pairs 20.5.4 OPAMP2 control/status register (OPAMP2_CSR) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAL OUT USER TRIM CAL SEL CALON Res. VP_ SEL Res. Res. OPA LPM OPAEN r rw rw rw rw rw rw VM_SEL rw rw PGA_GAIN OPAMODE rw rw rw w Bits 31:16 Reserved, must be kept at reset value. Bit 15 CALOUT: Operational amplifier calibration output During calibration mode offset is trimmed when this signal toggle. Bit 14 USERTRIM: allows to switch from ‘factory’ AOP offset trimmed values to AOP offset ‘user’ trimmed values This bit is active for both mode normal and low-power. 0: ‘factory’ trim code used 1: ‘user’ trim code used Bit 13 CALSEL: Calibration selection 0: NMOS calibration (200mV applied on OPAMP inputs) 1: PMOS calibration (VDDA-200mV applied on OPAMP inputs) Bit 12 CALON: Calibration mode enabled 0: Normal mode 1: Calibration mode (all switches opened by HW) Bit 11 Reserved, must be kept at reset value. Bit 10 VP_SEL: Non inverted input selection 0: GPIO connected to VINP 1: DAC connected to VINP 592/1680 DocID024597 Rev 1 RM0351 Operational amplifiers (OPAMP) Bits 9:8 VM_SEL: Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. 00: GPIO connected to VINM (valid also in PGA mode for filtering) 01: Dedicated low leakage input, (available only on BGA132) connected to VINM (valid also in PGA mode for filtering) 1x: Inverting input not externally connected. These configurations are valid only when OPAMODE = 10 (PGA mode) Bits 7:6 Reserved, must be kept at reset value. Bits 5:4 PGA_GAIN: Operational amplifier Programmable amplifier gain value 00: internal PGA Gain 2 01: internal PGA Gain 4 10: internal PGA Gain 8 11: internal PGA Gain 16 Bits 3:2 OPAMODE: Operational amplifier PGA mode 00: internal PGA disable 01: internal PGA disable 10: internal PGA enable, gain programmed in PGA_GAIN 11: internal follower Bit 1 OPALPM: Operational amplifier Low Power Mode The operational amplifier must be disable to change this configuration. 0: operational amplifier in normal mode 1: operational amplifier in low-power mode Bit 0 OPAEN: Operational amplifier Enable 0: operational amplifier disabled 1: operational amplifier enabled 20.5.5 OPAMP2 offset trimming register in normal mode (OPAMP2_OTR) Address offset: 0x14 Reset value: 0x0000 XXXX (factory trimmed values) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12 11 10 9 8 4 3 2 1 0 rw rw 15 14 13 Res. Res. Res. TRIMOFFSETP rw rw rw rw 7 6 5 Res. Res. Res. rw TRIMOFFSETN rw rw rw Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 TRIMOFFSETP[4:0]: Trim for PMOS differential pairs Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 TRIMOFFSETN[4:0]: Trim for NMOS differential pairs 20.5.6 OPAMP2 offset trimming register in low-power mode (OPAMP2_LPOTR) Address offset: 0x18 DocID024597 Rev 1 593/1680 595 Operational amplifiers (OPAMP) RM0351 Reset value: 0x0000 XXXX (factory trimmed values) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12 11 10 9 8 4 3 2 1 0 15 14 13 Res. Res. Res. TRIMLPOFFSETP rw rw rw rw 7 6 5 Res. Res. Res. rw TRIMLPOFFSETN rw rw Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 TRIMLPOFFSETP[4:0]: Low-power mode trim for PMOS differential pairs Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 TRIMLPOFFSETN[4:0]: Low-power mode trim for NMOS differential pairs 594/1680 DocID024597 Rev 1 rw rw rw 0x18 1. Reset value (1) (1) OPAMP2_ LPOTR TRIMLP OFFSETP[4:0] TRIMLP OFFSETN[4:0] Reset value DocID024597 Rev 1 0 0 0 (1) 0 TRIM OFFSETP[4:0] 0 0 0 Res. Res. Res. CALSEL CALON (1) 0 0 OPAEN 0 OPALPM OPAMODE PGA_GAIN Res. Res. VM_SEL VP_SEL Res. USERTRIM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CALOUT 0 OPAEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 OPALPM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 OPAMODE PGA_GAIN TRIMLP OFFSETN[4:0] Res. Res. TRIM OFFSETP[4:0] Res. Res. VM_SEL TRIMLP OFFSETP[4:0] Res. Res. Res. 0 Res. 0 VP_SEL Reset value 0 Res. 0 0 Res. CALON OPAMP1_ LPOTR Res. Res. OPA_RANGE 0 Res. CALSEL (1) Res. Res. Res. 0 Res. USERTRIM (1) Res. 0 Res. Res. Res. CALOUT Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OPAMP2_OTR Res. OPAMP2_CSR Res. 0x14 0 Res. 0x10 Reset value Res. 0x08 OPAMP1_OTR Res. 0x04 OPAMP1_CSR Res. 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. 20.5.7 Res. RM0351 Operational amplifiers (OPAMP) OPAMP register map Table 116. OPAMP register map and reset values 0 0 TRIM OFFSETN[4:0] (1) TRIM OFFSETN[4:0] 0 0 (1) Factory trimmed values. Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. 595/1680 595 Digital filter for sigma delta modulators (DFSDM) RM0351 21 Digital filter for sigma delta modulators (DFSDM) 21.1 Introduction Digital filter for sigma delta modulators (DFSDM) is a high-performance module dedicated to interface external Σ∆ modulators to a microcontroller. It is featuring up to 8 external digital serial interfaces (channels) and up to 4 digital filters with flexible Sigma Delta stream digital processing options to offer up to 24-bit final ADC resolution. DFSDM also features optional parallel data stream input from microcontrollers memory. An external Σ∆ modulator provides digital data stream of converted analog values from the external Σ∆ modulator analog input. This digital data stream is sent into a DFSDM input channel through a serial interface. DFSDM supports several standards to connect various Σ∆ modulator outputs: SPI interface and Manchester coded 1-wire interface (both with adjustable parameters). DFSDM module supports the connection of up to 8 multiplexed input digital serial channels which are shared with up to 4 DFSDM modules. DFSDM module also supports alternative parallel data inputs from up to 8 internal 16-bit data channels (from microcontrollers memory). DFSDM is converting an input data stream into a final digital data word which represents an analog input value on a Σ∆ modulator analog input. The conversion is based on a configurable digital process: the digital filtering and decimation of the input serial data stream. The conversion speed and resolution are adjustable according to configurable parameters for digital processing: filter type, filter order, length of filter, integrator length. The maximum output data resolution is up to 24 bits. There are two conversion modes: single conversion mode and continuous mode. The data can be automatically stored in a system RAM buffer through DMA, thus reducing the software overhead. A flexible timer triggering system can be used to control the start of conversion of DFSDM. This timing control is capable of triggering simultaneous conversions or inserting a programmable delay between conversions. DFSDM features an analog watchdog function. Analog watchdog can be assigned to any of the input channel data stream or to final output data. Analog watchdog has its own digital filtering of input data stream to reach the required speed and resolution of watched data. To detect short-circuit in control applications, there is a short-circuit detector. This block watches each input channel data stream for occurrence of stable data for a defined time duration (several 0’s or 1’s in an input data stream). An extremes detector block watches final output data and stores maximum and minimum values from the output data values. The extremes values stored can be restarted by software. Two power modes are supported: normal mode and stop mode. 596/1680 DocID024597 Rev 1 RM0351 21.2 Digital filter for sigma delta modulators (DFSDM) DFSDM main features • • • • Up to 8 multiplexed input digital serial channels: – configurable SPI interface to connect various Σ∆ modulators – configurable Manchester coded 1 wire interface support – maximum input clock frequency up to 20 MHz (10 MHz for Manchester coded stream) – clock output for Σ∆ modulator(s): 0..20 MHz Alternative inputs from up to 8 internal digital parallel channels: – inputs with up to 16 bit resolution – internal sources: memory (CPU/DMA write) data streams Adjustable digital signal processing: – Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024) – integrator: oversampling ratio (1..256) Up to 24-bit output data resolution: – right bit-shifter on final data (0..31 bits) • Signed output data format • Automatic data offset correction (offset stored in register by user) • Continuous or single conversion • Start-of-conversion synchronization with: – • • software trigger – internal timers – external events – start-of-conversion synchronously with first DFSDM (DFSDM0) Analog watchdog feature: – low value and high value data threshold registers – own configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32) – input from output data register or from one or more input digital serial channels – continuous monitoring independently from standard conversion Short-circuit detector to detect saturated analog input values (bottom and top ranges): – up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on input data stream – monitoring continuously each channel (8 serial channel transceiver outputs) • Break generation on analog watchdog event or short-circuit detector event • Extremes detector: – store minimum and maximum values of output data values – refreshed by software • DMA may be used to read the conversion data • Interrupts: end of conversion, overrun, analog watchdog, short-circuit, channel clock absence • “regular” or “injected” conversions: – “regular” conversions can be requested at any time or even in continuous mode without having any impact on the timing of “injected” conversions DocID024597 Rev 1 597/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 21.3 DFSDM functional description 21.3.1 DFSDM block diagram Figure 146. Single DFSDM block diagram $3%EXV 6DPSOH 6DPSOH 3DUDOOHOLQSXWGDWD UHJLVWHU 6DPSOH 6DPSOH &KDQQHOPXOWLSOH[HU 3DUDOOHOLQSXWGDWD UHJLVWHU ')6'0B(;75*>@ &ORFN FRQWURO ')6'0B&.287 ')6'0B'$7$,1 ')6'0B&.,1 ')6'0B'$7$,1 0RGH FRQWURO 'DWD 6HULDOWUDQVFHLYHU 0RGH &ORFN FRQWURO FRQWURO &ORFN 'DWDLQ )LOWHU RUGHU 2YHUVDPSOLQJ UDWLR 6LQF[ILOWHU 6KRUWFLUFXLW V VFRXQWHU GHWHFWRU WKUHVKROG 6WDWXV ,QWHUUXSW EUHDN &RQILJ ZDWFKGRJILOWHUV ZDWFKGRJFRPSDUDWRUV V VFRXQWHU WKUHVKROG )LOWHU FRQILJ ,QWHUUXSW EUHDN +LJKWKUHVKROG /RZWKUHVKROG $QDORJZDWFKGRJ 6KRUWFLUFXLW GHWHFWRU )LOWHU FRQILJ 2YHUVDPSOLQJ UDWLR 6LQF[ILOWHU ,QWHJUDWRUXQLW )LOWHU 2YHUVDPSOLQJ 2YHUVDPSOLQJ RUGHU UDWLR UDWLR &ORFNLQ 6HULDOWUDQVFHLYHU ')6'0B&.,1 'DWD &ORFN +LJKWKUHVKROG /RZWKUHVKROG ,QWHJUDWRUXQLW 5LJKWELWVKLIW FRXQW 5LJKWELWVKLIW &DOLEUDWLRQGDWD FRXQW FRUUHFWLRQXQLW &DOLEUDWLRQGDWD ')6'0GDWD FRUUHFWLRQXQLW ')6'0GDWD 'DWDRXWSXW $QDORJZDWFKGRJ $3%EXV &RQWUROXQLW &RQILJXUDWLRQ UHJLVWHUV '0$LQWHUUXSWEUHDN FRQWUROFORFNFRQWURO 598/1680 0D[LPXPYDOXH 0LQLPXPYDOXH ([WUHPHV ,QWHUUXSWVDQGHYHQWV GHWHFWRU HQGRIFRQYHUVLRQ 0D[LPXPYDOXH DQDORJZDWFKGRJ 0LQLPXPYDOXH VKRUWFLUFXLWGHWHFWLRQ ([WUHPHV RYHUUXQ GHWHFWRU DocID024597 Rev 1 069 RM0351 Digital filter for sigma delta modulators (DFSDM) Note: This example shows 4 DFSDM interfaces and 8 input channels (max. configuration). 21.3.2 DFSDM pins and internal signals Table 117. DFSDM external pins Name Signal Type Remarks VDD Power supply Digital power supply 1.65 - 3.6V. VSS Power supply Digital ground power supply. DFSDM_CKIN[7:0] Clock input Clock signal provided from external Σ∆ modulator. FT input. DFSDM_DATIN[7:0] Data input Data signal provided from external Σ∆ modulator. FT input. DFSDM_CKOUT Clock output Clock output to provide clock signal into external Σ∆ modulator. DFSDM_EXTRG[1:0] External trigger Input trigger from two EXTI signals to start analog signal conversion (from GPIOs: EXTI11, EXTI15). Table 118. DFSDM internal signals Name Signal Type Remarks DFSDM_INTRG[8:0] Internal trigger Input trigger from internal trigger sources to start analog signal conversion, see Table 119 for details. DFSDM_BREAK[3:0] break signal output Break signals event generation from Analog watchdog or short-circuit detector DFSDM_DMAREQ[3:0] DMA request signal DMA request signal from each DFSDMx (x=0..3): end of injected conversion event. DFSDM_INT[3:0] Interrupt request signal Interrupt signal for each DFSDMx (x=0..3) Table 119. DFSDM triggers connection Trigger name Trigger source DFSDM_INTRG[0] TIM1_TRGO DFSDM_INTRG[1] TIM1_TRGO2 DFSDM_INTRG[2] TIM8_TRGO DFSDM_INTRG[3] TIM8_TRGO2 DFSDM_INTRG[4] TIM3_TRGO DFSDM_INTRG[5] TIM4_TRGO DFSDM_INTRG[6] TIM16_OC1 DFSDM_INTRG[7] TIM6_TRGO DFSDM_INTRG[8] TIM7_TRGO DFSDM_EXTRG[0] EXTI11 DFSDM_EXTRG[1] EXTI15 DocID024597 Rev 1 599/1680 650 Digital filter for sigma delta modulators (DFSDM) 21.3.3 RM0351 DFSDM reset and clocks DFSDM on-off control The DFSDM interface is globally enabled by setting DFSDMEN=1 in the DFSDM_CHCFG0R1 register. Once DFSDM is globally enabled, all input channels (y=0..7) and digital filters DFSDMx (x=0..3) start to work if their enable bits are set (channel enable bit CHEN in DFSDM_CHCFGyR1 and DFSDMx enable bit DFEN in DFSDMx_CR1). Digital filter x DFSDMx (x=0..3) is enabled by setting DFEN=1 in the DFSDMx_CR1 register. Once DFSDMx is enabled (DFEN=1), both Sincx digital filter unit and integrator unit are reinitialized. By clearing DFEN, any conversion which may be in progress is immediately stopped and DFSDMx is put into stop mode. All register settings remain unchanged except DFSDMx_AWSR and DFSDMx_ISR (which are reset). Channel y (y=0..7) is enabled by setting CHEN=1 in the DFSDM_CHCFGyR1 register. Once the channel is enabled, it receives serial data from the external Σ∆ modulator or parallel internal data sources (CPU/DMA wire from memory). DFSDM must be globally disabled (by DFSDMEN=0 in DFSDM_CHCFG0R1) before stopping the system clock to enter in the STOP mode of the device. DFSDM clocks The internal DFSDM clock fDFSDMCLK, which is used to drive the channel transceivers, digital processing blocks (digital filter, integrator) and next additional blocks (analog watchdog, short-circuit detector, extremes detector, control block) is generated by the RCC block and is derived from the system clock SYSCLK (max. up to fSYSCLK = 80MHz) or peripheral clock PCLK2 (see DFSDMSEL bit description in Section 8.4.28: Peripherals independent clock configuration register (RCC_CCIPR)). The DFSDM clock is automatically stopped in stop mode (if DFEN = 0 for all DFSDMx, x=0..3). The DFSDM serial channel transceivers can receive an external serial clock to sample an external serial data stream. The internal DFSDM clock must be at least 4 times faster than the external serial clock if standard SPI coding is used, and 6 times faster than the external serial clock if Manchester coding is used. DFSDM can provide one external output clock signal to drive external Σ∆ modulator(s) clock input(s). It is provided on DFSDM_CKOUT pin. This output clock signal must be in the range 0 - 20 MHz and is derived from DFSDM clock or from audio clock (see CKOUTSRC bit in DFSDM_CHCFG0R1 register) by programmable divider in the range 2 - 256 (CKOUTDIV in DFSDM_CHCFG0R1 register). Audio clock source is SAI1 clock selected by SAI1SEL[1:0] field in RCC configuration (see Section 8.4.28: Peripherals independent clock configuration register (RCC_CCIPR)). 21.3.4 Serial channel transceivers There are 8 multiplexed serial data channels which can be selected for conversion by each filter or Analog watchdog or Short-circuit detector. Those serial transceivers receive data stream from external Σ∆ modulator. Data stream can be sent in SPI format or Manchester coded format (see SITP[1:0] bits in DFSDM_CHCFGyR1 register). The channel is enabled for operation by setting CHEN=1 in DFSDM_CHCFGyR1 register. 600/1680 DocID024597 Rev 1 RM0351 Digital filter for sigma delta modulators (DFSDM) Channel inputs selection Serial inputs (data and clock signals) from DFSDM_DATINy and DFSDM_CKINy pins can be redirected from the following channel. The serial input channel redirection is set by CHINSEL bit in DFSDM_CHCFGyR1 register. Channel redirection can be used to collect audio data from PDM (pulse density modulation) stereo microphone type. PDM stereo microphone has one data and one clock signal. Data signal provides information for both left and right audio channel (rising clock edge samples for left channel and falling clock edge samples for right channel). Configuration of serial channels for PDM microphone input: • PDM microphone signals (data, clock) will be connected to DFSDM input serial channel y (DFSDM_DATINy, DFSDM_CKINy). • Channel y will be configured: CHINSEL = 0 (input from channel y). • Channel (y-1) will be configured: CHINSEL = 1 (also input from channel y). • Channel y: SITP[1:0] = 0 (rising edge to strobe data) => left audio channel on channel y. • Channel (y-1): SITP[1:0] = 1 (falling edge to strobe data) => right audio channel on channel y-1. • Two DFSDM filters will be assigned to channel y and channel (y-1) (to filter left and right channels from PDM microphone). Output clock generation A clock signal can be provided on DFSDM_CKOUT pin to drive external Σ∆ modulator clock inputs. The frequency of this DFSDM_CKOUT signal is derived from DFSDM clock or from audio clock (see CKOUTSRC bit in DFSDM_CHCFG0R1 register) divided by a predivider (see CKOUTDIV bits in DFSDM_CHCFG0R1 register). If the output clock is stopped, then DFSDM_CKOUT signal is set to low state (output clock can be stopped by CKOUTDIV=0 in DFSDM_CHCFGyR1 register or by DFSDMEN=0 in DFSDMx_CHCFG0R1 register). The output clock stopping is performed: • 4 system clocks after DFSDMEN is cleared (if CKOUTSRC=0) • 1 system clock and 3 audio clocks after DFSDMEN is cleared (if CKOUTSRC=1) Before changing CKOUTSRC the software has to wait for CKOUT being stopped to avoid glitch on DFSDM_CKOUT pin. The output clock signal frequency must be in the range 0 20 MHz. SPI data input format operation In SPI format, the data stream is sent in serial format through data and clock signals. Data signal is always provided from DFSDM_DATINy pin. A clock signal can be provided externally from DFSDM_CKINy pin or internally from a signal derived from the DFSDM_CKOUT signal source. In case of external clock source selection (SPICKSEL[1:0]=0) data signal (on DFSDM_DATINy pin) is sampled on rising or falling clock edge (of DFSDM_CKINy pin) according SITP[1:0] bits setting (in DFSDM_CHCFGyR1 register). DocID024597 Rev 1 601/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 Internal clock sources - see SPICKSEL[1:0] in DFSDM_CHCFGyR1 register: • • • Note: DFSDM_CKOUT signal: – For connection to external ΣΔ modulator which uses directly its clock input (from DFSDM_CKOUT) to generate its output serial communication clock. – Sampling point: on rising/falling edge according SITP[1:0] setting. DFSDM_CKOUT/2 signal (generated on DFSDM_CKOUT rising edge): – For connection to external Σ∆ modulator which divides its clock input (from DFSDM_CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). – Sampling point: on each second DFSDM_CKOUT falling edge. DFSDM_CKOUT/2 signal (generated on DFSDM_CKOUT falling edge): – For connection to external Σ∆ modulator which divides its clock input (from DFSDM_CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). – Sampling point: on each second DFSDM_CKOUT rising edge. An internal clock source can only be used when the external Σ∆ modulator uses DFSDM_CKOUT signal as a clock input (to have synchronous clock and data operation). Internal clock source usage can save DFSDM_CKINy pin connection (DFSDM_CKINy pins can be used for other purpose). The clock source signal frequency must be in the range 0.5 - 20 MHz for SPI coding and less than fDFSDMCLK/4. Manchester coded data input format operation In Manchester coded format, the data stream is sent in serial format through DFSDM_DATINy pin only. Decoded data and clock signal are recovered from serial stream after Manchester decoding. There are two possible settings of Manchester codings (see SITP[1:0] bits in DFSDM_CHCFGyR1 register): • signal rising edge = log 0; signal falling edge = log 1 • signal rising edge = log 1; signal falling edge = log 0 The recovered clock signal frequency for Manchester coding must be in the range 0.5 10 MHz and less than fDFSDMCLK/6. To correctly receive Manchester coded data, the CKOUTDIV divider (in DFSDM_CHCFG0R1 register) must be set with respect to expected Manchester data rate according formula: ( ( CKOUTDIV + 1 ) × T SYSCLK ) < T Manchester clock < ( 2 × CKOUTDIV × T SYSCLK ) 602/1680 DocID024597 Rev 1 RM0351 Digital filter for sigma delta modulators (DFSDM) ')6'0B&.,1\ ')6'0B'$7,1\ ')6'0B&.287 63,&.6(/ WVX WK WZO WZK WU WI WU WI 6,73 WVX WK 6,73 63,&.6(/ 63,&.6(/ 63,&.6(/ WVX ')6'0B'$7,1\ 63,WLPLQJ63,&.6(/ 63,WLPLQJ63,&.6(/ Figure 147. Channel transceiver timing diagrams WK WZO WZK 6,73 WVX WK 6,73 ')6'0B'$7,1\ 0DQFKHVWHUWLPLQJ 6,73 6,73 UHFRYHUHGFORFN UHFRYHUHGGDWD 069 DocID024597 Rev 1 603/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 Clock absence detection Channels serial clock inputs can be checked for clock absence/presence to ensure the correct operation of conversion and error reporting. Clock absence detection can be enabled or disabled on each input channel y by bit CKABEN in DFSDMx_CHCFGyR1 register. If enabled, then this clock absence detection is performed continuously on a given channel. A clock absence flag is set (CKABF[y] = 1) and an interrupt can be invoked (if CKABIE=1) in case of an input clock error (see CKABF[7:0] in DFSDMx_ISR register and CKABEN in DFSDMx_CHCFGyR1). After a clock absence flag clearing (by CLRCKABF in DFSDMx_ICR register), the clock absence flag is refreshed. Clock absence status bit CKABF[y] is set also by hardware when corresponding channel y is disabled (if CHEN[y] = 0 CKABF[y] is held in set state). When a clock absence event has occurred, the data conversion (and/or analog watchdog and short-circuit detector) provides incorrect data. The user should manage this event and discard given data while a clock absence is reported. The clock absence feature is available only when the system clock is used for the DFSDM_CKOUT signal (CKOUTSRC=0 in DFSDM_CHCFG0R1 register). When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y] bit (in DFSDMx_ICR register). The software sequence concerning clock absence detection feature should be: • Enable given channel by CHEN = 1 • Try to clear the clock absence flag (by CLRCKABF = 1) until the clock absence flag is really cleared (CKABF = 0). At this time, the transceiver is synchronized (signal clock is valid) and is able to receive data. • Enable the clock absence feature CKABEN = 1 and the associated interrupt CKABIE = 1 to detect if the SPI clock is lost or Manchester data edges are missing. If SPI data format is used, then the clock absence detection is based on the comparison of an external input clock with an output clock generation (DFSDM_CKOUT signal). The external input clock signal into the input channel must be changed at least once per 8 signal periods of DFSDM_CKOUT signal (which is controlled by CKOUTDIV field in DFSDM_CHCFG0R1 register). Figure 148. Clock absence timing diagram for SPI 63,FORFNSUHVHQFH WLPLQJ PD[SHULRGV ')6'0B&.287 UHVWDUWFRXQWLQJ ')6'0B&.,1\ ODVWFORFNFKDQJH &.$%)>\@ HUURUUHSRUWHG 069 604/1680 DocID024597 Rev 1 RM0351 Digital filter for sigma delta modulators (DFSDM) If Manchester data format is used, then the clock absence means that the clock recovery is unable to perform from Manchester coded signal. For a correct clock recovery, it is first necessary to receive data with 1 to 0 or 0 to 1 transition (see Figure 150 for Manchester synchronization). The detection of a clock absence in Manchester coding (after a first successful synchronization) is based on changes comparison of coded serial data input signal with output clock generation (DFSDM_CKOUT signal). There must be a voltage level change on DFSDM_DATINy pin during 2 periods of DFSDM_CKOUT signal (which is controlled by CKOUTDIV bits in DFSDM_CHCFG0R1 register). This condition also defines the minimum data rate to be able to correctly recover the Manchester coded data and clock signals. The maximum data rate of Manchester coded data must be less than the DFSDM_CKOUT signal. So to correctly receive Manchester coded data, the CKOUTDIV divider must be set according the formula: ( ( CKOUTDIV + 1 ) × T SYSCLK ) < T Manchester clock < ( 2 × CKOUTDIV × T SYSCLK ) A clock absence flag is set (CKABF[y] = 1) and an interrupt can be invoked (if CKABIE=1) in case of an input clock recovery error (see CKABF[7:0] in DFSDMx_ISR register and CKABEN in DFSDMx_CHCFGyR1). After a clock absence flag clearing (by CLRCKABF in DFSDMx_ICR register), the clock absence flag is refreshed. DocID024597 Rev 1 605/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 Figure 149. Clock absence timing diagram for Manchester coding PD[SHULRGV ')6'0B&.287 ')6'0B'$7,1\ 0DQFKHVWHUFORFNSUHVHQFH WLPLQJ UHVWDUWFRXQWLQJ 6,73 ODVWGDWDFKDQJH 6,73 UHFRYHUHGFORFN UHFRYHUHGGDWD " " &.$%)>\@ HUURUUHSRUWHG 069 Manchester/SPI code synchronization The Manchester coded stream must be synchronized the first time after enabling the channel (CHEN=1 in DFSDM_CHCFGyR1 register). The synchronization ends when a data transition from 0 to 1 or from 1 to 0 (to be able to detect valid data edge) is received. The end of the synchronization can be checked by polling CKABF[y]=0 for a given channel after it has been cleared by CLRCKABF[y] in DFSDMx_ICR, following the software sequence detailed hereafter: CKABF[y] flag is cleared by setting CLRCKABF[y] bit. If channel y is not yet synchronized the hardware immediately set the CKABF[y] flag. Software is then reading back the CKABF[y] flag and if it is set then perform again clearing of this flag by setting CLRCKABF[y] bit. This software sequence (polling of CKABF[y] flag) continues until CKABF[y] flag is set (signalizing that Manchester stream is synchronized). To be able to synchronize/receive Manchester coded data the CKOUTDIV divider (in DFSDM_CHCFG0R1 register) must be set with respect to expected Manchester data rate according the formula below. ( ( CKOUTDIV + 1 ) × T SYSCLK ) < T Manchester clock < ( 2 × CKOUTDIV × T SYSCLK ) 606/1680 DocID024597 Rev 1 RM0351 Digital filter for sigma delta modulators (DFSDM) SPI coded stream is synchronized after first detection of clock input signal (valid rising/falling edge). Note: When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y] bit (in DFSDMx_ICR register). ')6'0B'$7,1\ 0DQFKHVWHUWLPLQJ Figure 150. First conversion for Manchester coding (Manchester synchronization) 6,73 6,73 UHFRYHUHGFORFN GDWDIURP PRGXODWRU &+(1 UHDOVWDUWRIILUVWFRQYHUVLRQ ILUVWFRQYHUVLRQ VWDUWWULJJHU UHFRYHUHGGDWD ILUVWGDWDELWWRJJOHHQGRI0DQFKHVWHUV\QFKURQL]DWLRQ " " &.$%)>\@ FOHDULQJRI&.$%)>\@IODJE\VRIWZDUHSROOLQJ 069 External serial clock frequency measurement The measuring of a channel serial clock input frequency provides a real data rate from an external Σ∆ modulator, which is important for application purposes. An external serial clock input frequency can be measured by a timer counting DFSDM clocks (fDFSDMCLK) during one conversion duration. The counting starts at the first input data clock after a conversion trigger (regular or injected) and finishes by last input data clock before conversion ends (end of conversion flag is set). Each conversion duration (time between first serial sample and last serial sample) is updated in counter CNVCNT[27:0] in register DFSDMx_CNVTIMR when the conversion finishes (JEOCF=1 or REOCF=1). The user can then compute the data rate according to the digital filter settings (FORD, FOSR, IOSR, FAST). The external serial frequency measurement is stopped only if the filter is DocID024597 Rev 1 607/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 bypassed (FOSR=0, only integrator is active, CNVCNT[27:0]=0 in DFSDMx_CNVTIMR register). In case of parallel data input (Section 21.3.6: Parallel data inputs) the measured frequency is the average input data rate during one conversion. Note: When conversion is interrupted (e.g. by disabling/enabling the selected channel) the interruption time is also counted in CNVCNT[27:0]. Therefore it is recommended to not interrupt the conversion for correct conversion duration result. Conversion times: injected conversion or regular conversion with FAST = 0 (or first conversion if FAST=1): for Sincx filters (x=1..5): t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + FORD) + FORD] / fDFSDM_CKIN for FastSinc filter: t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + 4) + 2] / fDFSDM_CKIN regular conversion with FAST = 1 (except first conversion): for Sincx and FastSinc filters: t = CNVCNT/fDFSDMCLK = [FOSR * IOSR] / fDFSDM_CKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fDFSDM_CKIN (... but CNVCNT=0) where: • fDFSDM_CKIN is the channel input clock frequency (on given channel DFSDM_CKINypin) or input data rate (in case of parallel data input) • FOSR is the filter oversampling ratio: FOSR = FOSR[9:0]+1 (see DFSDMx_FCR register) • IOSR is the integrator oversampling ratio: IOSR = IOSR[7:0]+1 (see DFSDMx_FCR register) • FORD is the filter order: FORD = FORD[2:0] (see DFSDMx_FCR register) Channel offset setting Each channel has its own offset setting (in register) which is finally subtracted from each conversion result (injected or regular) from a given channel. The offset is stored as a 24-bit signed value in OFFSET[23:0] field in DFSDM_CHCFGyR2 register. Data right bit shift To have the result aligned to a 24-bit value, each channel defines a number of right bit shifts which will be applied on each conversion result (injected or regular) from a given channel. The data bit shift number is stored in DTRBS[4:0] bits in DFSDM_CHCFGyR2 register. The right bit-shift is rounding the result to nearest integer value. The sign of shifted result is maintained, in order to have valid 24-bit signed format of result data. 608/1680 DocID024597 Rev 1 RM0351 21.3.5 Digital filter for sigma delta modulators (DFSDM) Configuring the input serial interface The following parameters must be configured for the input serial interface: 21.3.6 • Output clock predivider. There is a programmable predivider to generate the output clock from DFSDM clock (2 - 256). It is defined in DFSDMx_CR1 register. • Serial interface type and input clock phase. Selection of SPI or Manchester coding and sampling edge of input clock. It is defined by SITP [1:0] bits in DFSDM_CHCFGyR1 register. • Input clock source. External source from DFSDM_CKINy pin or internal from DFSDM_CKOUT pin. It is defined by SPICKSEL[1:0] field in DFSDM_CHCFGyR1 register. • Final data right bit-shift. Defines the final data right bit shift to have the result aligned to a 24-bit value. It is defined by DTRBS[4:0] in DFSDM_CHCFGyR2 register. • Channel offset per channel. Defines the analog offset of a given serial channel (offset of connected external Σ∆ modulator). It is defined by OFFSET[23:0] bits in DFSDM_CHCFGyR2 register. • short-circuit detector and clock absence per channel enable. To enable or disable the short-circuit detector (by SCDEN bit) and the clock absence monitoring (by CKABEN bit) on a given serial channel in register DFSDM_CHCFGyR1. • Analog watchdog filter and short-circuit detector threshold settings. To configure channel analog watchdog filter parameters and channel short-circuit detector parameters. Configurations are defined in DFSDM_AWSCDyR register. Parallel data inputs Each input channel provides a register for 16-bit parallel data input (besides serial data input). Each 16-bit parallel input can be sourced from internal data sources only: • direct CPU/DMA writing. The selection for using serial or parallel data input for a given channel is done by field DATMPX[1:0] of DFSDM_CHCFGyR1 register. In DATMPX[1:0] is also defined the parallel data source: direct write by CPU/DMA. Each channel contains a 32-bit data input register DFSDM_CHDATINyR in which it can be written a 16-bit data. Data are in 16-bit signed format. Those data can be used as input to the digital filter which is accepting 16-bit parallel data. If serial data input is selected (DATMPX[1:0] = 0), the DFSDM_CHDATINyR register is write protected. Input from memory (direct CPU/DMA write) The direct data write into DFSDM_CHDATINyR register by CPU or DMA (DATMPX[1:0]=2) can be used as data input in order to process digital data streams from memory or peripherals. Data can be written by CPU or DMA into DFSDM_CHDATINyR register: 1. CPU data write: Input data are written directly by CPU into DFSDM_CHDATINyR register. 2. DMA data write: The DMA should be configured in memory-to-memory transfer mode to transfer data from memory buffer into DFSDM_CHDATINyR register. The destination memory DocID024597 Rev 1 609/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 address is the address of DFSDM_CHDATINyR register. Data are transferred at DMA transfer speed from memory to DFSDM parallel input. This DMA transfer is different from DMA used to read DFSDM conversion results. Both DMA can be used at the same time - first DMA (configured as memory-to-memory transfer) for input data writings and second DMA (configured as peripheral-to-memory transfer) for data results reading. The accesses to DFSDM_CHDATINyR can be either 16-bit or 32-bit wide, allowing to load respectively one or two samples in one write operation. 32-bit input data register (DFSDM_CHDATINyR) can be filled with one or two 16-bit data samples, depending on the data packing operation mode defined in field DATPACK[1:0] of DFSDM_CHCFGyR1 register: 1. Standard mode (DATPACK[1:0]=0): Only one sample is stored in field INDAT0[15:0] of DFSDM_CHDATINyR register which is used as input data for channel y. The upper 16 bits (INDAT1[15:0]) are ignored and write protected. The digital filter must perform one input sampling (from INDAT0[15:0]) to empty data register after it has been filled by CPU/DMA. This mode is used together with 16-bit CPU/DMA access to DFSDM_CHDATINyR register to load one sample per write operation. 2. Interleaved mode (DATPACK[1:0]=1): DFSDM_CHDATINyR register is used as a two sample buffer. The first sample is stored in INDAT0[15:0] and the second sample is stored in INDAT1[15:0]. The digital filter must perform two input samplings from channel y to empty DFSDM_CHDATINyR register. This mode is used together with 32-bit CPU/DMA access to DFSDM_CHDATINyR register to load two samples per write operation. 3. Dual mode (DATPACK[1:0]=2): Two samples are written into DFSDM_CHDATINyR register. The data INDAT0[15:0] is for channel y, the data in INDAT1[15:0] is for channel y+1. The data in INDAT1[15:0] is automatically copied INDAT0[15:0] of the following (y+1) channel data register DFSDM_CHDATIN[y+1]R). The digital filters must perform two samplings - one from channel y and one from channel (y+1) - in order to empty DFSDM_CHDATINyR registers. Dual mode setting (DATPACK[1:0]=2) is available only on even channel numbers (y = 0, 2, 4, 6). If odd channel (y = 1, 3, 5, 7) is set to Dual mode then both INDAT0[15:0] and INDAT1[15:0] parts are write protected for this channel. If even channel is set to Dual mode then the following odd channel must be set into Standard mode (DATPACK[1:0]=0) for correct cooperation with even channels. See Figure 151 for DFSDM_CHDATINyR registers data modes and assignments of data samples to channels. 610/1680 DocID024597 Rev 1 RM0351 Digital filter for sigma delta modulators (DFSDM) Figure 151. DFSDM_CHDATINyR registers operation modes and assignment 6WDQGDUGPRGH ,QWHUOHDYHGPRGH 'XDOPRGH &K VDPSOH &K VDPSOH 8QXVHG &K VDPSOH &K VDPSOH &K VDPSOH 8QXVHG &K VDPSOH &K VDPSOH &K VDPSOH 8QXVHG &K VDPSOH &K VDPSOH &K VDPSOH 8QXVHG &K VDPSOH &K VDPSOH &K VDPSOH 8QXVHG &K VDPSOH &K VDPSOH &K VDPSOH 8QXVHG &K VDPSOH &K VDPSOH &K VDPSOH 8QXVHG &K VDPSOH &K VDPSOH &K VDPSOH 8QXVHG &K VDPSOH &K VDPSOH &K VDPSOH 8QXVHG \ &K VDPSOH \ &K VDPSOH &K VDPSOH \ 8QXVHG &K VDPSOH \ &K VDPSOH &K VDPSOH \ 8QXVHG &K VDPSOH \ &K VDPSOH &K VDPSOH \ 8QXVHG &K VDPSOH \ 069 The write into DFSDM_CHDATINyR register to load one or two samples must be performed after the selected input channel (channel y) is enabled for data collection (starting conversion for channel y). Otherwise written data are lost for next processing. For example: for single conversion and interleaved mode, do not start writing pair of data samples into DFSDM_CHDATINyR before the single conversion is started (any data present in the DFSDM_CHDATINyR before starting a conversion is discarded). 21.3.7 Channel selection There are 8 multiplexed channels which can be selected for conversion using the injected channel group and/or using the regular channel. The injected channel group is a selection of any or all of the 8 channels. JCHG[7:0] in the DFSDMx_JCHGR register selects the channels of the injected group, where JCHG[y]=1 means that channel y is selected. Injected conversions can operate in scan mode (JSCAN=1) or single mode (JSCAN=0). In scan mode, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first, followed immediately by the next higher channel until all the channels selected by JCHG[7:0] have been converted. In single mode (JSCAN=0), only one channel from the selected channels is converted, and the channel selection is moved to the next channel. Writing to JCHG[7:0] if JSCAN=0 resets the channel selection to the lowest selected channel. Injected conversions can be launched by software or by a trigger. They are never interrupted by regular conversions. The regular channel is a selection of just one of the 8 channels. RCH[2:0] in the DFSDMx_CR1 register indicates the selected channel. Regular conversions can be launched only by software (not by a trigger). A sequence of continuous regular conversions is temporarily interrupted when an injected conversion is requested. Performing a conversion on a disabled channel (CHEN=0 in DFSDM_CHCFGyR1 register) causes that the conversion will never end - because no input data is provided (with no clock signal). In this case, it is necessary to enable a given channel (CHEN=1 in DFSDM_CHCFGyR1 register) or to stop the conversion by DFEN=0 in DFSDMx_CR1 register. DocID024597 Rev 1 611/1680 650 Digital filter for sigma delta modulators (DFSDM) 21.3.8 RM0351 Digital filter configuration DFSDM contains a Sincx type digital filter implementation. This Sincx filter performs an input digital data stream filtering, which results in decreasing the output data rate (decimation) and increasing the output data resolution. The Sincx digital filter is configurable in order to reach the required output data rates and required output data resolution. The configurable parameters are: • • Filter order/type: (see FORD[2:0] bits in DFSDMx_FCR register): – FastSinc – Sinc1 – Sinc2 – Sinc3 – Sinc4 – Sinc5 Filter oversampling/decimation ratio (see FOSR[9:0] bits in DFSDMx_FCR register): – FOSR = 1-1024 – FOSR = 1-215 – FOSR = 1-73 - for FastSinc filter and Sincx filter x = FORD = 1..3 - for Sincx filter x = FORD = 4 - for Sincx filter x = FORD = 5 The filter has the following transfer function (impulse response in H domain): • x Sincx filter type: ⎛ 1 – z – FOSR⎞ -⎟ H ( z ) = ⎜ ---------------------------⎝ 1 – z–1 ⎠ FastSinc filter type: ⎛ 1 – z– FOSR⎞ –( 2 ⋅ -⎟ ⋅ ( 1 + z H ( z ) = ⎜ ---------------------------–1 ⎝ 1–z ⎠ 2 • FOSR ) ) *DLQ G% Figure 152. Example: Sinc3 filter response 1RUPDOL]HGIUHTXHQF\ I,1I'$7$ 612/1680 DocID024597 Rev 1 069 RM0351 Digital filter for sigma delta modulators (DFSDM) Table 120. Filter maximum output resolution (peak data values from filter output) for some FOSR values FOSR Sinc1 Sinc2 FastSinc Sinc3 Sinc4 Sinc5 x +/- x +/- x2 +/- 2x2 +/- x3 +/- x4 +/- x5 4 +/- 4 +/- 16 +/- 32 +/- 64 +/- 256 +/- 1024 8 +/- 8 +/- 64 +/- 128 +/- 512 +/- 4096 - 32 +/- 32 +/- 1024 +/- 2048 +/- 32768 +/- 1048576 +/- 33554432 64 +/- 64 +/- 4096 +/- 8192 +/- 262144 +/- 16777216 +/- 1073741824 128 +/- 128 +/- 16384 +/- 32768 +/- 2097152 +/- 268435456 256 +/- 256 +/- 65536 +/- 131072 +/- 16777216 1024 +/- 1024 +/- 1048576 Result can overflow on full scale input (> 32-bit signed integer) +/- 2097152 +/- 1073741824 For more information about Sinc filter type properties and usage, it is recommended to study the theory about digital filters (more resources can be downloaded from internet). 21.3.9 Integrator unit The integrator performs additional decimation and a resolution increase of data coming from the digital filter. The integrator simply performs the sum of data from a digital filter for a given number of data samples from a filter. The integrator oversampling ratio parameter defines how many data counts will be summed to one data output from the integrator. IOSR can be set in the range 1-256 (see IOSR[7:0] bits description in DFSDMx_FCR register). Table 121. Integrator maximum output resolution (peak data values from integrator output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) IOSR x 21.3.10 Sinc1 Sinc2 FastSinc +/- FOSR. x +/- FOSR2. x +/- 2.FOSR2. x Sinc3 Sinc4 Sinc5 +/- FOSR3. x +/- FOSR4. x +/- FOSR5. x 4 - - - +/- 67 108 864 - - 32 - - - +/- 536 870 912 - - 128 - - - +/- 2 147 483 648 - - 256 - - - +/- 232 - - Analog watchdog The analog watchdog purpose is to trigger an external signal (break or interrupt) when an analog signal reaches or crosses given maximum and minimum threshold values. An interrupt/event/break generation can then be invoked. Each analog watchdog will supervise serial data receiver outputs (after the analog watchdog filter on each channel) or data output register (current injected or regular conversion result) according to AWFSEL bit setting (in DFSDMx_CR1 register). The input channels to be monitored or not by the analog watchdog x will be selected by AWDCH[7:0] in DFSDMx_CR2 register. DocID024597 Rev 1 613/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 Analog watchdog conversions on input channels are independent from standard conversions. In this case, the analog watchdog uses its own filters and signal processing on each input channel independently from the main injected or regular conversions. Analog watchdog conversions are performed in a continuous mode on the selected input channels in order to watch channels also when main injected or regular conversions are paused (RCIP = 0, JCIP = 0). There are high and low threshold registers which are compared with given data values (set by AWHT[23:0] bits in DFSDMx_AWHTR register and by AWLT[23:0] bits in DFSDMx_AWLTR register). Input data into analog watchdog selection and features: • • from final output data register (AWFSEL=0): – high resolution (up to 24-bits) – slow response time - not good for fast response (e.g overcurrent) – for comparison, final data is taken after offset data correction and bit shifting – final data is watched only when main regular or injected conversions are converted – can be used in case of parallel input data source (DATMPX[1:0] ≠ 0 in DFSDM_CHCFGyR1 register) from any of serial data receiver outputs (AWFSEL=1): – through own analog watchdog Sincx channel filters with configurable oversampling ratio (1..32) and filter order (1..3) (see AWFOSR[4:0] and AWFORD[1:0] bits setting in DFSDM_AWSCDyR register) – lower resolution (up to 16-bit) – fast response time - for applications which require a fast response (e.g overcurrent, overvoltage detection) – data is watched in continuous mode independently from main regular or injected conversions In case of input channels monitoring (AWFSEL=1), the data for comparison to threshold is taken from channels selected by AWDCH[7:0] field (DFSDMx_CR2 register). Each of the selected channels filter result is compared to one threshold value pair (AWHT[23:0] / AWLT[23:0]). In this case, only higher 16 bits (AWHT[23:8] / AWLT[23:8]) define the 16-bit threshold compared with the analog watchdog filter output because data coming from the analog watchdog filter is up to a 16-bit resolution. Bits AWHT[7:0] / AWLT[7:0] are not taken into comparison in this case (AWFSEL=1). Parameters of the analog watchdog filter configuration for each input channel are set in DFSDM_AWSCDyR register (filter order AWFORD[1:0] and filter oversampling ratio AWFOSR[4:0]). Each input channel has its own comparator which compares the analog watchdog data (from analog watchdog filter) with analog watchdog threshold values (AWHT/AWLT). When several channels are selected (field AWDCH[7:0] field of DFSDMx_CR2 register), several comparison requests may be received simultaneously. In this case, the channel request with the lowest number is managed first and then continuing to higher selected channels. For each channel, the result can be recorded in a separate flag (fields AWHTF[7:0], AWLTF[7:0] of DFSDMx_AWSR register). Each channel request is executed in 8 DFSDM clock cycles. So, the bandwidth from each channel is limited to 8 DFSDM clock cycles (if AWDCH[7:0] = 0xFF). Because the maximum input channel sampling clock frequency is the DFSDM clock frequency divided by 4, the configuration AWFOSR = 0 (analog watchdog filter is bypassed) 614/1680 DocID024597 Rev 1 RM0351 Digital filter for sigma delta modulators (DFSDM) cannot be used for analog watchdog feature at this input clock speed. Therefore user must properly configure the number of watched channels and analog watchdog filter parameters with respect to input sampling clock speed and DFSDM frequency. Analog watchdog filter data for given channel y is available for reading by firmware on field WDATA[15:0] in DFSDM_CHWDATyR register. That analog watchdog filter data is converted continuously (if CHEN=1 in DFSDM_CHCFGyR1 register) with the data rate given by the analog watchdog filter setting and the channel input clock frequency. The analog watchdog filter conversion works like a regular Fast Continuous Conversion without the intergator. The number of serial samples needed for one result from analog watchdog filter output (at channel input clock frequency fDFSDM_CKIN): first conversion: for Sincx filters (x=1..5): number of samples = [FOSR * FORD + FORD + 1] for FastSinc filter: number of samples = [FOSR * 4 + 2 + 1] next conversions: for Sincx and FastSinc filters: number of samples = [FOSR * IOSR] where: FOSR ....... filter oversampling ratio: FOSR = AWFOSR[4:0]+1 (see DFSDM_AWSCDyR register) FORD ....... the filter order: FORD = AWFORD[1:0] (see DFSDM_AWSCDyR register) In case of output data register monitoring (AWFSEL=0), the comparison is done after an offset correction and a right bit shift of final data (see OFFSET[23:0] and DTRBS[4:0] fields in DFSDM_CHCFGyR2 register). A comparison is performed after each injected or regular end of conversion for the channels selected by AWDCH[7:0] field (in DFSDMx_CR2 register). The status of an analog watchdog event is signalized in DFSDMx_AWSR register where a given event is latched. AWHTF[y]=1 flag signalizes crossing AWHT[23:0] value on channel y. AWLTF[y]=1 flag signalizes crossing AWLT[23:0] value on channel y. Latched events in DFSDMx_AWSR register are cleared by writing ‘1’ into the corresponding clearing bit CLRAWHTF[y] or CLRAWLTF[y] in DFSDMx_AWCFR register. The global status of an analog watchdog is signalized by the AWDF flag bit in DFSDMx_ISR register (it is used for the fast detection of an interrupt source). AWDF=1 signalizes that at least one watchdog occurred (AWHTF[y]=1 or AWLTF[y]=1 for at least one channel). AWDF bit is cleared when all AWHTF[7:0] and AWLTF[7:0] are cleared. An analog watchdog event can be assigned to break output signal. There are four break outputs to be assigned to a high or low threshold crossing event (DFSDM_BREAK[3:0]). The break signal assignment to a given analog watchdog event is done by BKAWH[3:0] and BKAWL[3:0] fields in DFSDMx_AWHTR and DFSDMx_AWLTR register. 21.3.11 Short-circuit detector The purpose of a short-circuit detector is to signalize with a very fast response time if an analog signal reached saturated values (out of full scale ranges) and remained on this value given time. This behavior can detect short-circuit or open circuit errors (e.g. overcurrent or overvoltage). An interrupt/event/break generation can be invoked. Input data into a short-circuit detector is taken from channel transceiver outputs. DocID024597 Rev 1 615/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 There is an upcounting counter on each input channel which is counting consecutive 0’s or 1’s on serial data receiver outputs. A counter is restarted if there is a change in the data stream received - 1 to 0 or 0 to 1 change of data signal. If this counter reaches a short-circuit threshold register value (SCDT[7:0] bits in DFSDM_AWSCDyR register), then a short-circuit event is invoked. Each input channel has its short-circuit detector. Any channel can be selected to be continuously monitored by setting the SCDEN bit (in DFSDM_CHCFGyR1 register) and it has its own short-circuit detector settings (threshold value in SCDT[7:0] bits, status bit SCDF[7:0], status clearing bits CLRSCDF[7:0]). Status flag SCDF[y] is cleared also by hardware when corresponding channel y is disabled (CHEN[y] = 0). On each channel, a short-circuit detector event can be assigned to break output signal DFSDM_BREAK[3:0]. There are four break outputs to be assigned to a short-circuit detector event. The break signal assignment to a given channel short-circuit detector event is done by BKSCD[3:0] field in DFSDM_AWSCDyR register. Short circuit detector cannot be used in case of parallel input data channel selection (DATMPX[1:0] ≠ 0 in DFSDM_CHCFGyR1 register). Four break outputs are totally available (shared with the analog watchdog function). 21.3.12 Extremes detector The purpose of an extremes detector is to collect the minimum and maximum values of final output data words (peak to peak values). If the output data word is higher than the value stored in the extremes detector maximum register (EXMAX[23:0] bits in DFSDMx_EXMAX register), then this register is updated with the current output data word value and the channel from which the data is stored is in EXMAXCH[2:0] bits (in DFSDMx_EXMAX register) . If the output data word is lower than the value stored in the extremes detector minimum register (EXMIN[23:0] bits in DFSDMx_EXMIN register), then this register is updated with the current output data word value and the channel from which the data is stored is in EXMINCH[2:0] bits (in DFSDMx_EXMIN register). The minimum and maximum register values can be refreshed by software (by reading given DFSDMx_EXMAX or DFSDMx_EXMIN register). After refresh, the extremes detector minimum data register DFSDMx_EXMIN is filled with 0x7FFFFF (maximum positive value) and the extremes detector maximum register DFSDMx_EXMAX is filled with 0x800000 (minimum negative value). The extremes detector performs a comparison after an offset and a bit shift data correction. For each extremes detector, the input channels to be considered into computing the extremes value are selected in EXCH[7:0] bits (in DFSDMx_CR2 register). 21.3.13 Data unit block The data unit block is the last block of the whole processing path: External Σ∆ modulators Serial transceivers - Sinc filter - Integrator - Data unit block. The output data rate depends on the serial data stream rate, and filter and integrator settings. The maximum output data rate is: Datarate samples ⁄ s 616/1680 f DFSDM_CKIN = ---------------------------------------------------------------------------------------------------------F OSR ⋅ ( I OSR – 1 + F ORD ) + ( F ORD + 1 ) DocID024597 Rev 1 ...FAST = 0, Sincx filter RM0351 Digital filter for sigma delta modulators (DFSDM) Datarate samples ⁄ s f DFSDM_CKIN = ----------------------------------------------------------------------------------F OSR ⋅ ( I OSR – 1 + 4 ) + ( 2 + 1 ) ...FAST = 0, FastSinc filter or Datarate samples ⁄ s f DFSDM_CKIN = ----------------------------------F OSR ⋅ I OSR ...FAST = 1 Maximum output data rate in case of parallel data input: Datarate samples ⁄ s f DATAIN_RATE = ---------------------------------------------------------------------------------------------------------F OSR ⋅ ( I OSR – 1 + F ORD ) + ( F ORD + 1 ) ...FAST = 0, Sincx filter or Datarate samples ⁄ s f DATAIN_RATE = ----------------------------------------------------------------------------------F OSR ⋅ ( I OSR – 1 + 4 ) + ( 2 + 1 ) ...FAST = 0, FastSinc filter or Datarate samples ⁄ s f DATAIN_RATE = -----------------------------------F OSR ⋅ I OSR ...FAST=1 or any filter bypass case ( F OSR = 1 ) where: f DATAIN_RATE ...input data rate from CPU/DMA The final right bit-shift of final data is performed in this module because the final data width is 24-bit and data coming from the processing path can be up to 32 bits. This right bit-shift is configurable in the range 0-31 bits for each selected input channel (see DTRBS[4:0] bits in DFSDM_CHCFGyR2 register). The right bit-shift is rounding the result to nearest integer value. The sign of shifted result is maintained - to have valid 24-bit signed format of result data. At last, an offset correction of the result is performed. The offset correction value (OFFSET[23:0] stored in register DFSDM_CHCFGyR2) is subtracted from the output data for a given channel. Data in the OFFSET[23:0] field is set by software by the appropriate calibration routine. Due to the fact that all operations in digital processing are performed on 32-bit signed registers, the following conditions must be fulfilled not to overflow the result: FOSR FORD . IOSR <= 231 ... for Sincx filters, x = 1..5) 2 . FOSR 2 . IOSR <= 231 ... for FastSinc filter) Note: In case of filter and integrator bypass (IOSR[7:0]=0, FOSR[9:0]=0), the input data rate (fDATAIN_RATE) must be limited to be able to read all output data: fDATAIN_RATE ≤ fAPB where fAPB is the bus frequency to which the DFSDM peripheral is connected. 21.3.14 Signed data format Each DFSDM input serial channel can be connected to one external Σ∆ modulator. An external Σ∆ modulator can have 2 differential inputs (positive and negative) which can be used for a differential or single-ended signal measurement. DocID024597 Rev 1 617/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 A Σ∆ modulator output is always assumed in a signed format (a data stream of zeros and ones from a Σ∆ modulator represents values -1 and +1). Signed data format in registers: Data is in a signed format in registers for final output data, analog watchdog, extremes detector, offset correction. The msb of output data word represents the sign of value (two’s complement format). 21.3.15 Launching conversions Injected conversions can be launched using the following methods: • Software: writing ‘1’ to JSWSTART in the DFSDMx_CR1 register. • Trigger: JEXTSEL[2:0] selects the trigger signal while JEXTEN activates the trigger and selects the active edge at the same time (see the DFSDMx_CR1 register). • Synchronous with DFSDM0 if JSYNC=1: for DFSDMx (x>0), an injected conversion is automatically launched when in DFSDM0; the injected conversion is started by software (JSWSTART=1 in DFSDM0_CR2 register). Each injected conversion in DFSDMx (x>0) is always executed according to its local configuration settings (JSCAN, JCHG, etc.). If the scan conversion is enabled (bit JSCAN=1) then, each time an injected conversion is triggered, all of the selected channels in the injected group (JCHG[7:0] bits in DFSDMx_JCHGR register) are converted sequentially, starting with the lowest channel (channel 0, if selected). If the scan conversion is disabled (bit JSCAN=0) then, each time an injected conversion is triggered, only one of the selected channels in the injected group (JCHG[7:0] bits in DFSDMx_JCHGR register) is converted and the channel selection is then moved to the next selected channel. Writing to the JCHG[7:0] bits when JSCAN=0 sets the channel selection to the lowest selected injected channel. Only one injected conversion can be ongoing at a given time. Thus, any request to launch an injected conversion is ignored if another request for an injected conversion has already been issued but not yet completed. Regular conversions can be launched using the following methods: • Software: by writing ‘1’ to RSWSTART in the DFSDMx_CR1 register. • Synchronous with DFSDM0 if RSYNC=1: for DFSDMx (x>0), a regular conversion is automatically launched when in DFSDM0; a regular conversion is started by software (RSWSTART=1 in DFSDM0_CR2 register). Each regular conversion in DFSDMx (x>0) is always executed according to its local configuration settings (RCONT, RCH, etc.). Only one regular conversion can be pending or ongoing at a given time. Thus, any request to launch a regular conversion is ignored if another request for a regular conversion has already been issued but not yet completed. A regular conversion can be pending if it was interrupted by an injected conversion or if it was started while an injected conversion was in progress. This pending regular conversion is then delayed and is performed when all injected conversion are finished. Any delayed regular conversion is signalized by RPEND bit in DFSDMx_RDATAR register. 21.3.16 Continuous and fast continuous modes Setting RCONT in the DFSDMx_CR1 register causes regular conversions to execute in continuous mode. RCONT=1 means that the channel selected by RCH[3:0] is converted repeatedly after ‘1’ is written to RSWSTART. 618/1680 DocID024597 Rev 1 RM0351 Digital filter for sigma delta modulators (DFSDM) The regular conversions executing in continuous mode can be stopped by writing ‘0’ to RCONT. After clearing RCONT, the on-going conversion is stopped immediately. In continuous mode, the data rate can be increased by setting the FAST bit in the DFSDMx_CR1 register. In this case, the filter does not need to be refilled by new fresh data if converting continuously from one channel because data inside the filter is valid from previously sampled continuous data. The speed increase depends on the chosen filter order. The first conversion in fast mode (FAST=1) after starting a continuous conversion by RSWSTART=1 takes still full time (as when FAST=0), then each subsequent conversion is finished in shorter intervals. Conversion time in continuous mode: if FAST = 0 (or first conversion if FAST=1): for Sincx filters: t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + FORD) + FORD] / fDFSDM_CKIN for FastSinc filter: t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + 4) + 2] / fDFSDM_CKIN if FAST = 1 (except first conversion): for Sincx and FastSinc filters: t = CNVCNT/fDFSDMCLK = [FOSR * IOSR] / fDFSDM_CKIN in case FOSR = FOSR[9:0]+1 = 1 (filter bypassed, only integrator active): t = IOSR / fDFSDM_CKIN (... but CNVCNT=0) Continuous mode is not available for injected conversions. Injected conversions can be started by timer trigger to emulate the continuous mode with precise timing. If a regular continuous conversion is in progress (RCONT=1) and if a write access to DFSDMx_CR1 register requesting regular continuous conversion (RCONT=1) is performed, then regular continuous conversion is restarted from the next conversion cycle (like new regular continuous conversion is applied for new channel selection - even if there is no change in DFSDMx_CR1 register). 21.3.17 Request precedence An injected conversion has a higher precedence than a regular conversion. A regular conversion which is already in progress is immediately interrupted by the request of an injected conversion; this regular conversion is restarted after the injected conversion finishes. An injected conversion cannot be launched if another injected conversion is pending or already in progress: any request to launch an injected conversion (either by JSWSTART or by a trigger) is ignored as long as bit JCIP is ‘1’ (in the DFSDMx_ISR register). Similarly, a regular conversion cannot be launched if another regular conversion is pending or already in progress: any request to launch a regular conversion (using RSWSTART) is ignored as long as bit RCIP is ‘1’ (in the DFSDMx_ISR register). However, if an injected conversion is requested while a regular conversion is already in progress, the regular conversion is immediately stopped and an injected conversion is launched. The regular conversion is then restarted and this delayed restart is signalized in bit RPEND. Injected conversions have precedence over regular conversions in that a injected conversion can temporarily interrupt a sequence of continuous regular conversions. When DocID024597 Rev 1 619/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 the sequence of injected conversions finishes, the continuous regular conversions start again if RCONT is still set (and RPEND bit will signalize the delayed start on the first regular conversion result). Precedence also matters when actions are initiated by the same write to DFSDM, or if multiple actions are pending at the end of another action. For example, suppose that, while an injected conversion is in process (JCIP=1), a single write operation to DFSDMx_CR1 writes ‘1’ to RSWSTART, requesting a regular conversion. When the injected sequence finishes, the precedence dictates that the regular conversion is performed next and its delayed start is signalized in RPEND bit. 21.3.18 Power optimization in run mode In order to reduce the consumption, the DFSDM filter and integrator are automatically put into idle when not used by conversions (RCIP=0, JCIP=0). 21.4 DFSDM interrupts In order to increase the CPU performance, a set of interrupts related to the CPU event occurrence has been implemented: • • • • • 620/1680 End of injected conversion interrupt: – enabled by JEOCIE bit in DFSDMx_CR2 register – indicated in JEOCF bit in DFSDMx_ISR register – cleared by reading DFSDMx_JDATAR register (injected data) – indication of which channel end of conversion occurred, reported in JDATACH[2:0] bits in DFSDMx_JDATAR register End of regular conversion interrupt: – enabled by REOCIE bit in DFSDMx_CR2 register – indicated in REOCF bit in DFSDMx_ISR register – cleared by reading DFSDMx_RDATAR register (regular data) – indication of which channel end of conversion occurred, reported in RDATACH[2:0] bits in DFSDMx_RDATAR register Data overrun interrupt for injected conversions: – occurred when injected converted data were not read from DFSDMx_JDATAR register (by CPU or DMA) and were overwritten by a new injected conversion – enabled by JOVRIE bit in DFSDMx_CR2 register – indicated in JOVRF bit in DFSDMx_ISR register – cleared by writing ‘1’ into CLRJOVRF bit in DFSDMx_ICR register Data overrun interrupt for regular conversions: – occurred when regular converted data were not read from DFSDMx_RDATAR register (by CPU or DMA) and were overwritten by a new regular conversion – enabled by ROVRIE bit in DFSDMx_CR2 register – indicated in ROVRF bit in DFSDMx_ISR register – cleared by writing ‘1’ into CLRROVRF bit in DFSDMx_ICR register Analog watchdog interrupt: DocID024597 Rev 1 RM0351 Digital filter for sigma delta modulators (DFSDM) • • – occurred when converted data (output data or data from analog watchdog filter according to AWFSEL bit setting in DFSDMx_CR1 register) crosses over/under high/low thresholds in DFSDMx_AWHTR / DFSDMx_AWLTR registers – enabled by AWDIE bit in DFSDMx_CR2 register (on selected channels AWDCH[7:0]) – indicated in AWDF bit in DFSDMx_ISR register – separate indication of high or low analog watchdog threshold error by AWHTF[7:0] and AWLTF[7:0] fields in DFSDMx_AWSR register – cleared by writing ‘1’ into corresponding CLRAWHTF[7:0] or CLRAWLTF[7:0] bits in DFSDMx_AWCFR register Short-circuit detector interrupt: – occurred when the number of stable data crosses over thresholds in DFSDM_AWSCDyR register – enabled by SCDIE bit in DFSDMx_CR2 register (on channel selected by SCDEN bi tin DFSDM_CHCFGyR1 register) – indicated in SCDF[7:0] bits in DFSDMx_ISR register (which also reports the channel on which the short-circuit detector event occurred) – cleared by writing ‘1’ into the corresponding CLRSCDF[7:0] bit in DFSDMx_ICR register Channel clock absence interrupt: – occurred when there is clock absence on DFSDM_CKINy pin (see Clock absence detection in Section 21.3.4: Serial channel transceivers) – enabled by CKABIE bit in DFSDMx_CR2 register (on channels selected by CKABEN bit in DFSDM_CHCFGyR1 register) – indicated in CKABF[y] bit in DFSDMx_ISR register – cleared by writing ‘1’ into CLRCKABF[y] bit in DFSDMx_ICR register Table 122. DFSDM interrupt requests Interrupt event Event flag Event/Interrupt clearing method Interrupt enable control bit End of injected conversion JEOCF reading DFSDMx_JDATAR JEOCIE End of regular conversion REOCF reading DFSDMx_RDATAR REOCIE Injected data overrun JOVRF writing CLRJOVRF = 1 JOVRIE Regular data overrun ROVRF writing CLRROVRF = 1 ROVRIE Analog watchdog AWDF, AWHTF[7:0], AWLTF[7:0] writing CLRAWHTF[7:0] = 1 writing CLRAWLTF[7:0] = 1 AWDIE, (AWDCH[7:0]) short-circuit detector SCDF[7:0] writing CLRSCDF[7:0] = 1 SCDIE, (SCDEN) Channel clock absence CKABF[7:0] writing CLRCKABF[7:0] = 1 CKABIE, (CKABEN) DocID024597 Rev 1 621/1680 650 Digital filter for sigma delta modulators (DFSDM) 21.5 RM0351 DFSDM DMA transfer To decrease the CPU intervention, conversions can be transferred into memory using a DMA transfer. A DMA transfer for injected conversions is enabled by setting bit JDMAEN=1 in DFSDMx_CR1 register. A DMA transfer for regular conversions is enabled by setting bit RDMAEN=1 in DFSDMx_CR1 register. Note: With a DMA transfer, the interrupt flag is automatically cleared at the end of the injected or regular conversion (JEOCF or REOCF bit in DFSDMx_ISR register) because DMA is reading DFSDMx_JDATAR or DFSDMx_RDATAR register. 21.6 DFSDM channel y registers (y=0..7) 21.6.1 DFSDM channel configuration y register (DFSDM_CHCFGyR1) (y=0..7) This register specifies the parameters used by channel y (y = 0..7). Address offset: 0x00 Reset value: 0x0000 0000 31 30 DFSDM CKOUT EN SRC rw rw 15 14 DATPACK[1:0] rw rw 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. rw rw rw rw 13 12 11 10 9 8 7 6 5 4 Res. Res. Res. CHIN SEL CHEN CKAB EN SCDEN Res. rw rw rw rw DATMPX[1:0] rw rw 23 22 21 20 19 18 17 16 rw rw rw rw 3 2 1 0 CKOUTDIV[7:0] SPICKSEL[1:0] rw rw SITP[1:0] rw rw Bit 31 DFSDMEN: Global enable for DFSDM interface 0: DFSDM interface disabled 1: DFSDM interface enabled If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHCFGyR1 and DFEN bit in DFSDMx_CR1). Data cleared by setting DFSDMEN=0: – all registers DFSDMx_ISR ars set to reset state (x = 0..3) – all registers DFSDMx_AWSR are set to reset state (x = 0..3) Note: DFSDMEN is present only in DFSDM_CHCFG0R1 register (channel y=0) Bit 30 CKOUTSRC: Output serial clock source selection 0: Source for output clock is from system clock 1: Source for output clock is from audio clock – SAI1 clock selected by SAI1SEL[1:0] field in RCC configuration (see Section 8.4.28: Peripherals independent clock configuration register (RCC_CCIPR)) This value can be modified only when DFSDMEN=0 (in DFSDM_CHCFG0R1 register). Note: CKOUTSRC is present only in DFSDM_CHCFG0R1 register (channel y=0) Bits 29:24 Reserved, must be kept at reset value. 622/1680 DocID024597 Rev 1 RM0351 Digital filter for sigma delta modulators (DFSDM) Bits 23:16 CKOUTDIV[7:0]: Output serial clock divider 0: Output clock generation is disabled (DFSDM_CKOUT signal is set to low state) 1- 255: Defines the division of system clock for the serial clock output for DFSDM_CKOUT signal in range 2 - 256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CHCFG0R1 register). If DFSDMEN=0 (in DFSDM_CHCFG0R1 register) then DFSDM_CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CHCFG0R1 register (channel y=0) Bits 15:14 DATPACK[1:0]: Data packing mode in DFSDM_CHDATINyR register. 0: Standard: input data in DFSDM_CHDATINyR register are stored only in INDAT0[15:0]. To empty DFSDM_CHDATINyR register one sample must be read by the DFSDM filter from channel y. 1: Interleaved: input data in DFSDM_CHDATINyR register are stored as two samples: – first sample in INDAT0[15:0] (assigned to channel y) – second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHDATINyR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHDATINyR register are stored as two samples: – first sample INDAT0[15:0] (assigned to channel y) – second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHDATINyR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHDATINyR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHCFGyR1 register). Bits 13:12 DATMPX[1:0]: Input data multiplexer for channel y 0: Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHDATINyR register is write protected. 1: Reserved 2: Data to channel y are taken from internal DFSDM_CHDATINyR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHCFGyR1 register). Bits 11:9 Reserved, must be kept at reset value. Bit 8 CHINSEL: Channel inputs selection 0: Channel inputs are taken from pins of the same channel y. 1: Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8). This value can be modified only when CHEN=0 (in DFSDM_CHCFGyR1 register). Bit 7 CHEN: Channel y enable 0: Channel y disabled 1: Channel y enabled If channel y is enabled, then serial data receiving is started according to the given channel setting. Bit 6 CKABEN: Clock absence detector enable on channel y 0: Clock absence detector disabled on channel y 1: Clock absence detector enabled on channel y DocID024597 Rev 1 623/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 Bit 5 SCDEN: Short-circuit detector enable on channel y 0: Input channel y will not be guarded by the short-circuit detector 1: Input channel y will be continuously guarded by the short-circuit detector Bit 4 Reserved, must be kept at reset value. Bits 3:2 SPICKSEL[1:0]: SPI clock select for channel y 0: clock coming from external DFSDM_CKINy input - sampling point according SITP[1:0] 1: clock coming from internal DFSDM_CKOUT output - sampling point according SITP[1:0] 2: clock coming from internal DFSDM_CKOUT - sampling point on each second DFSDM_CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from DFSDM_CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal DFSDM_CKOUT output - sampling point on each second DFSDM_CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from DFSDM_CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHCFGyR1 register). Bits 1:0 SITP[1:0]: Serial interface type for channel y 00: SPI with rising edge to strobe data 01: SPI with falling edge to strobe data 10: Manchester coded input on DFSDM_DATINy pin: rising edge = logic 0, falling edge = logic 1 11: Manchester coded input on DFSDM_DATINy pin: rising edge = logic 1, falling edge = logic 0 This value can only be modified when CHEN=0 (in DFSDM_CHCFGyR1 register). 21.6.2 DFSDM channel configuration y register (DFSDM_CHCFGyR2) (y=0..7) This register specifies the parameters used by channel y (y = 0..7). Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OFFSET[23:8] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. OFFSET[7:0] rw rw 624/1680 rw rw rw DTRBS[4:0] rw rw rw rw rw DocID024597 Rev 1 rw rw rw RM0351 Digital filter for sigma delta modulators (DFSDM) Bits 31:8 OFFSET[23:0]: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software. Bits 7:3 DTRBS[4:0]: Data right bit-shift for channel y 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHCFGyR1 register). Bits 2:0 Reserved, must be kept at reset value. 21.6.3 DFSDM analog watchdog and short-circuit detector register (DFSDM_AWSCDyR) (y=0..7) Short-circuit detector and analog watchdog settings for channel y Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. BKSCD[3:0] rw rw rw rw 23 22 AWFORD[1:0] rw rw 7 6 21 20 19 Res. 18 17 16 AWFOSR[4:0] 5 rw rw rw rw rw 4 3 2 1 0 rw rw rw SCDT[7:0] rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:22 AWFORD[1:0]: Analog watchdog Sinc filter order on channel y 0: FastSinc filter type 1: Sinc1 filter type 2: Sinc2 filter type 3: Sinc3 filter type x ⎛ 1 – z – FOSR⎞ Sincx filter type transfer function: H ( z ) = ⎜ ---------------------------⎟ ⎝ 1 – z –1 ⎠ 2 FastSinc filter type transfer function: ⎛ 1 – z– FOSR⎞ –( 2 ⋅ -⎟ ⋅ ( 1 + z H ( z ) = ⎜ ---------------------------⎝ 1 – z–1 ⎠ FOSR ) ) This bit can be modified only when CHEN=0 (in DFSDM_CHCFGyR1 register). Bit 21 Reserved, must be kept at reset value. Bits 20:16 AWFOSR[4:0]: Analog watchdog filter oversampling ratio (decimation rate) on channel y 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHCFGyR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). DocID024597 Rev 1 625/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 Bits 15:12 BKSCD[3:0]: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y Bits 11:8 Reserved, must be kept at reset value. Bits 7:0 SCDT[7:0]: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel. 21.6.4 DFSDM channel watchdog filter data register (DFSDM_CHWDATyR) (y=0..7) This register contains the data resulting from the analog watchdog filter associated to the input channels. Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r WDATA[15:0] r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 WDATA[15:0]: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1...32/sinc order = 1...3). 21.6.5 DFSDM channel data input register (DFSDM_CHDATINyR) (y=0..7) This register contains 16-bit input data to be processed by DFSDM filter module. Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INDAT1[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw INDAT0[15:0] rw rw 626/1680 rw rw rw rw rw rw rw DocID024597 Rev 1 RM0351 Digital filter for sigma delta modulators (DFSDM) Bits 31:16 INDAT0[15:0]: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See Section 21.3.6: Parallel data inputs for more details. INDAT0[15:1] is in the16-bit signed format. Bits 15:0 INDAT0[15:0]: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See Section 21.3.6: Parallel data inputs for more details. INDAT0[15:0] is in the16-bit signed format. 21.7 DFSDMx module registers (x=0..3) 21.7.1 DFSDM control register 1 (DFSDMx_CR1) Address offset: 0x100 Reset value: 0x0000 0000 31 30 Res. AWF SEL FAST rw rw 14 13 15 Res. 29 JEXTEN[1:0] rw rw 28 Res. 12 Res. 27 26 Res. 11 25 24 RCH[2:0] Res. rw rw rw 10 9 8 Res. JEXTSEL[2:0] rw rw 23 22 21 Res. RDMA EN 20 Res. rw 7 Res. 6 5 Res. JDMA EN rw DocID024597 Rev 1 rw 4 19 17 16 RSW START Res. rw rw 3 2 1 0 Res. JSW START DFEN r0w rw JSCAN JSYNC rw 18 RCON RSYNC T rw r0w 627/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 Bit 31 Reserved, must be kept at reset value. Bit 30 AWFSEL: Analog watchdog fast mode select 0: Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift 1: Analog watchdog on channel transceivers value (after watchdog filter) Bit 29 FAST: Fast conversion mode selection for regular conversions 0: Fast conversion mode disabled 1: Fast conversion mode enabled When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDMx_CR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fDFSDM_CKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fDFSDM_CKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fDFSDM_CKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fDFSDM_CKIN (... but CNVCNT=0) where: fDFSDM_CKIN is the channel input clock frequency (on given channel DFSDM_CKINy pin) or input data rate in case of parallel data input. Bits 28:27 Reserved, must be kept at reset value. Bits 26:24 RCH[2:0]: Regular channel selection 0: Channel 0 is selected as the regular channel 1: Channel 1 is selected as the regular channel ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion). Bits 23:22 Reserved, must be kept at reset value. Bit 21 RDMAEN: DMA channel enabled to read data for the regular conversion 0: The DMA channel is not enabled to read regular data 1: The DMA channel is enabled to read regular data This bit can be modified only when DFEN=0 (DFSDMx_CR1). Bit 20 Reserved, must be kept at reset value. Bit 19 RSYNC: Launch regular conversion synchronously with DFSDM0 0: Do not launch a regular conversion synchronously wi th DFSDM0 1: Launch a regular conversion in this DFSDM at the very moment when a regular conversion is launched in DFSDM0 This bit can be modified only when DFEN=0 (DFSDMx_CR1). Bit 18 RCONT: Continuous mode selection for regular conversions 0: The regular channel is converted just once for each conversion request 1: The regular channel is converted repeatedly after each conversion request Writing ‘0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately. 628/1680 DocID024597 Rev 1 RM0351 Digital filter for sigma delta modulators (DFSDM) Bit 17 RSWSTART: Software start of a conversion on the regular channel 0: Writing ‘0’ has no effect 1: Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to become ‘1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing ‘1’ has no effect if RSYNC=1. This bit is always read as ‘0’. Bits 16:15 Reserved, must be kept at reset value. Bits 14:13 JEXTEN[1:0]: Trigger enable and trigger edge selection for injected conversions 00: Trigger detection is disabled 01: Each rising edge on the selected trigger makes a request to launch an injected conversion 10: Each falling edge on the selected trigger makes a request to launch an injected conversion 11: Both rising edges and falling edges on the selected trigger make requests to launch injected conversions This bit can be modified only when DFEN=0 (DFSDMx_CR1). Bits 12:11 Reserved, must be kept at reset value. Bits 10:8 JEXTSEL[2:0]: Trigger signal selection for launching injected conversions 0x0-0x7: Trigger inputs selected by the following table. This bit can be modified only when DFEN=0 (DFSDMx_CR1). 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 DFSDM0 DFSDM_INTRG0 DFSDM_INTRG1 DFSDM_INTRG2 DFSDM_INTRG3 DFSDM_INTRG5 DFSDM_INTRG7 DFSDM_EXTRG0 DFSDM_EXTRG1 DFSDM1 DFSDM_INTRG0 DFSDM_INTRG1 DFSDM_INTRG2 DFSDM_INTRG3 DFSDM_INTRG5 DFSDM_INTRG7 DFSDM_EXTRG0 DFSDM_EXTRG1 DFSDM2 DFSDM_INTRG0 DFSDM_INTRG1 DFSDM_INTRG2 DFSDM_INTRG3 DFSDM_INTRG5 DFSDM_INTRG8 DFSDM_EXTRG0 DFSDM_EXTRG1 DFSDM3 DFSDM_INTRG0 DFSDM_INTRG1 DFSDM_INTRG2 DFSDM_INTRG4 DFSDM_INTRG6 DFSDM_INTRG8 DFSDM_EXTRG0 DFSDM_EXTRG1 Refer to Table 119: DFSDM triggers connection. Bits 7:6 Reserved, must be kept at reset value. Bit 5 JDMAEN: DMA channel enabled to read data for the injected channel group 0: The DMA channel is not enabled to read injected data 1: The DMA channel is enabled to read injected data This bit can be modified only when DFEN=0 (DFSDMx_CR1). Bit 4 JSCAN: Scanning conversion mode for injected conversions 0: One channel conversion is performed from the injected channel group and next the selected channel from this group is selected. 1: The series of conversions for the injected group channels is executed, starting over with the lowest selected channel. This bit can be modified only when DFEN=0 (DFSDMx_CR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel. Bit 3 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 0: Do not launch an injected conversion synchronously with DFSDM0 1: Launch an injected conversion in this DFSDM at the very moment when an injected conversion is launched in DFSDM0 by its JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDMx_CR1). DocID024597 Rev 1 629/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 Bit 2 Reserved, must be kept at reset value. Bit 1 JSWSTART: Start a conversion of the injected group of channels 0: Writing ‘0’ has no effect. 1: Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become ‘1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing ‘1’ has no effect if JSYNC=1. This bit is always read as ‘0’. Bit 0 DFEN: DFSDM enable 0: DFSDMx is disabled. All conversions of given DFSDMx are stopped immediately and all DFSDMx functions are stopped. 1: DFSDMx is enabled. If DFSDMx is enabled, then DFSDM starts operating according to its setting. Data is cleared by setting DFEN=0: – register DFSDMx_ISR is set to the reset state – register DFSDMx_AWSR is set to the reset state 21.7.2 DFSDM control register 2 (DFSDMx_CR2) Address offset: 0x104 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 EXCH[7:0] rw rw rw rw rw rw rw rw 23 22 21 20 19 18 17 16 AWDCH[7:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 Res. CKAB IE ROVR IE JOVRI E REOC IE JEOCI E rw rw rw rw rw SCDIE AWDIE rw rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 AWDCH[7:0]: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y Bits 15:8 EXCH[7:0]: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y Bit 7 Reserved, must be kept at reset value. Bit 6 CKABIE: Clock absence interrupt enable 0: Detection of channel input clock absence interrupt is disabled 1: Detection of channel input clock absence interrupt is enabled Please see the explanation of CKABF[7:0] in DFSDMx_ISR. Note: CKABIE is present only in DFSDM0_CR2 register (filter x=0) 630/1680 DocID024597 Rev 1 RM0351 Digital filter for sigma delta modulators (DFSDM) Bit 5 SCDIE: Short-circuit detector interrupt enable 0: short-circuit detector interrupt is disabled 1: short-circuit detector interrupt is enabled Please see the explanation of SCDF[7:0] in DFSDMx_ISR. Note: SCDIE is present only in DFSDM0_CR2 register (filter x=0) Bit 4 AWDIE: Analog watchdog interrupt enable 0: Analog watchdog interrupt is disabled 1: Analog watchdog interrupt is enabled Please see the explanation of AWDF in DFSDMx_ISR. Bit 3 ROVRIE: Regular data overrun interrupt enable 0: Regular data overrun interrupt is disabled 1: Regular data overrun interrupt is enabled Please see the explanation of ROVRF in DFSDMx_ISR. Bit 2 JOVRIE: Injected data overrun interrupt enable 0: Injected data overrun interrupt is disabled 1: Injected data overrun interrupt is enabled Please see the explanation of JOVRF in DFSDMx_ISR. Bit 1 REOCIE: Regular end of conversion interrupt enable 0: Regular end of conversion interrupt is disabled 1: Regular end of conversion interrupt is enabled Please see the explanation of REOCF in DFSDMx_ISR. Bit 0 JEOCIE: Injected end of conversion interrupt enable 0: Injected end of conversion interrupt is disabled 1: Injected end of conversion interrupt is enabled Please see the explanation of JEOCF in DFSDMx_ISR. 21.7.3 DFSDM interrupt and status register (DFSDMx_ISR) Address offset: 0x108 Reset value: 0x00FF 0000 31 30 29 28 27 26 25 24 23 22 21 SCDF[7:0] 20 19 18 17 16 CKABF[7:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. RCIP JCIP Res. Res. Res. Res. Res. Res. Res. Res. r r AWDF ROVRF JOVRF REOCF JEOCF r DocID024597 Rev 1 r r r r 631/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 Bits 31:24 SCDF[7:0]: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_AWSCDyR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDMx_ICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM0_ISR register (filter x=0) Bits 23:16 CKABF[7:0]: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHCFGyR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDMx_ICR register. Note: CKABF[7:0] is present only in DFSDM0_ISR register (filter x=0) Bit 15 Reserved, must be kept at reset value. Bit 14 RCIP: Regular conversion in progress status 0: No request to convert the regular channel has been issued 1: The conversion of the regular channel is in progress or a request for a regular conversion is pending A request to start a regular conversion is ignored when RCIP=1. Bit 13 JCIP: Injected conversion in progress status 0: No request to convert the injected channel group (neither by software nor by trigger) has been issued 1: The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to ‘1’ being written to JSWSTART or to a trigger detection A request to start an injected conversion is ignored when JCIP=1. Bits 12:5 Reserved, must be kept at reset value. Bit 4 AWDF: Analog watchdog 0: No Analog watchdog event occurred 1: The analog watchdog block detected voltage which crosses the value programmed in the DFSDMx_AWLTR or DFSDMx_AWHTR registers. This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDMx_AWSR register (by writing ‘1’ into the clear bits in DFSDMx_AWCFR register). Bit 3 ROVRF: Regular conversion overrun flag 0: No regular conversion overrun has occurred 1: A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already ‘1’. RDATAR is not affected by overruns This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDMx_ICR register. 632/1680 DocID024597 Rev 1 RM0351 Digital filter for sigma delta modulators (DFSDM) Bit 2 JOVRF: Injected conversion overrun flag 0: No injected conversion overrun has occurred 1: An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already ‘1’. JDATAR is not affected by overruns This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDMx_ICR register. Bit 1 REOCF: End of regular conversion flag 0: No regular conversion has completed 1: A regular conversion has completed and its data may be read This bit is set by hardware. It is cleared when the software or DMA reads DFSDMx_RDATAR. Bit 0 JEOCF: End of injected conversion flag 0: No injected conversion has completed 1: An injected conversion has completed and its data may be read This bit is set by hardware. It is cleared when the software or DMA reads DFSDMx_JDATAR. Note: For each of the flag bits, an interrupt can be enabled by setting the corresponding bit in DFSDMx_CR2. If an interrupt is called, the flag must be cleared before exiting the interrupt service routine. All the bits of DFSDMx_ISR are automatically reset when DFEN=0. 21.7.4 DFSDM interrupt flag clear register (DFSDMx_ICR) Address offset: 0x10C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 CLRSCDF[7:0] 20 19 18 17 16 CLRCKABF[7:0] rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. CLRR OVRF CLR J OVRF Res. Res. rc_w1 rc_w1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:24 CLRSCDF[7:0]: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing ‘0’ has no effect CLRSCDF[y]=1: Writing ‘1’ to position y clears the corresponding SCDF[y] bit in the DFSDMx_ISR register Note: CLRSCDF[7:0] is present only in DFSDM0_ICR register (filter x=0) Bits 23:16 CLRCKABF[7:0]: Clear the clock absence flag CLRCKABF[y]=0: Writing ‘0’ has no effect CLRCKABF[y]=1: Writing ‘1’ to position y clears the corresponding CKABF[y] bit in the DFSDMx_ISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM0_ICR register (filter x=0) Bits 15:4 Reserved, must be kept at reset value. DocID024597 Rev 1 633/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 Bit 3 CLRROVRF: Clear the regular conversion overrun flag 0: Writing ‘0’ has no effect 1: Writing ‘1’ clears the ROVRF bit in the DFSDMx_ISR register Bit 2 CLRJOVRF: Clear the injected conversion overrun flag 0: Writing ‘0’ has no effect 1: Writing ‘1’ clears the JOVRF bit in the DFSDMx_ISR register Bits 1:0 Reserved, must be kept at reset value. Note: The bits of DFSDMx_ICR are always read as ‘0’. 21.7.5 DFSDM injected channel group selection register (DFSDMx_JCHGR) Address offset: 0x110 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw JCHG[7:0] rw rw rw rw rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 JCHG[7:0]: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored. 21.7.6 DFSDM filter control register (DFSDMx_FCR) Address offset: 0x114 Reset value: 0x0000 0000 31 30 29 FORD[2:0] 28 27 26 Res. Res. Res. rw rw rw 15 14 13 12 11 Res. Res. Res. Res. Res. 25 24 23 21 20 19 18 17 16 FOSR[9:0] rw rw rw rw rw rw rw rw rw rw 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. rw rw rw IOSR[7:0] rw 634/1680 22 rw DocID024597 Rev 1 rw rw rw RM0351 Digital filter for sigma delta modulators (DFSDM) Bits 31:29 FORD[2:0]: Sinc filter order 0: FastSinc filter type 1: Sinc1 filter type 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: ⎛ 1 – z –FOSR⎞ -⎟ H ( z ) = ⎜ ---------------------------⎝ 1 – z –1 ⎠ x 2 ⎛ 1 – z– FOSR⎞ –( 2 ⋅ -⎟ ⋅ ( 1 + z H ( z ) = ⎜ ---------------------------⎝ 1 – z–1 ⎠ FastSinc filter type transfer function: FOSR ) ) This bit can only be modified when DFEN=0 (DFSDMx_CR1). Bits 28:26 Reserved, must be kept at reset value. Bits 25:16 FOSR[9:0]: Sinc filter oversampling ratio (decimation rate) 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDMx_CR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 IOSR[7:0]: Integrator oversampling ratio (averaging length) 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDMx_CR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 21.7.7 DFSDM data register for injected group (DFSDMx_JDATAR) Address offset: 0x118 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 JDATA[23:8] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. JDATA[7:0] r r r r r r r r DocID024597 Rev 1 JDATACH[2:0] r r r 635/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 Bits 31:8 JDATA[23:0]: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF. Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 JDATACH[2:0]: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]. Note: DMA may be used to read the data from this register. Half-word accesses may be used to read only the MSBs of conversion data. Reading this register also clears JEOCF in DFSDMx_ISR. Thus, the firmware must not read this register if DMA is activated to read data from this register. 21.7.8 DFSDM data register for the regular channel (DFSDMx_RDATAR) Address offset: 0x11C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Res. Res. Res. RPEND Res. RDATA[23:8] 15 14 13 12 11 10 9 8 RDATA[7:0] r r r r r r r r r RDATACH[2:0] r r r Bits 31:8 RDATA[23:0]: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF. Bits 7:5 Reserved, must be kept at reset value. Bit 4 RPEND: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion Bit 3 Reserved, must be kept at reset value. Bits 2:0 RDATACH[2:0]: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDMx_CR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]. Note: Half-word accesses may be used to read only the MSBs of conversion data. Reading this register also clears REOCF in DFSDMx_ISR. 636/1680 DocID024597 Rev 1 RM0351 Digital filter for sigma delta modulators (DFSDM) 21.7.9 DFSDM analog watchdog high threshold register (DFSDMx_AWHTR) Address offset: 0x120 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AWHT[23:8] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. AWHT[7:0] rw rw rw rw rw rw rw rw BKAWH[3:0] rw rw rw rw Bits 31:8 AWHT[23:0]: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case. Bits 7:4 Reserved, must be kept at reset value. Bits 3:0 BKAWH[3:0]: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event 21.7.10 DFSDM analog watchdog low threshold register (DFSDMx_AWLTR) Address offset: 0x124 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AWLT[23:8] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. AWLT[7:0] rw rw rw rw rw rw rw rw DocID024597 Rev 1 BKAWL[3:0] rw rw rw rw 637/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 Bits 31:8 AWLT[23:0]: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case. Bits 7:4 Reserved, must be kept at reset value. Bits 3:0 BKAWL[3:0]: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event 21.7.11 DFSDM analog watchdog status register (DFSDMx_AWSR) Address offset: 0x128 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r AWHTF[7:0] r r r r AWLTF[7:0] r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 AWHTF[7:0]: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDMx_AWCFR register. Bits 7:0 AWLTF[7:0]: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDMx_AWCFR register. Note: All the bits of DFSDMx_AWSR are automatically reset when DFEN=0. 21.7.12 DFSDM analog watchdog clear flag register (DFSDMx_AWCFR) Address offset: 0x12C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rc_w1 rc_w1 rc_w1 CLRAWHTF[7:0] rc_w1 rc_w1 638/1680 rc_w1 rc_w1 rc_w1 CLRAWLTF[7:0] rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 DocID024597 Rev 1 rc_w1 rc_w1 rc_w1 RM0351 Digital filter for sigma delta modulators (DFSDM) Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 CLRAWHTF[7:0]: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing ‘0’ has no effect CLRAWHTF[y]=1: Writing ‘1’ to position y clears the corresponding AWHTF[y] bit in the DFSDMx_AWSR register Bits 7:0 CLRAWLTF[7:0]: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing ‘0’ has no effect CLRAWLTF[y]=1: Writing ‘1’ to position y clears the corresponding AWLTF[y] bit in the DFSDMx_AWSR register 21.7.13 DFSDM Extremes detector maximum register (DFSDMx_EXMAX) Address offset: 0x130 Reset value: 0x8000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EXMAX[23:8] r1 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 r0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. EXMAX[7:0] r0 r0 r0 r0 r0 r0 r0 r0 EXMAXCH[2:0] r r r Bits 31:8 EXMAX[23:0]: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register. Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 EXMAXCH[2:0]: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register. 21.7.14 DFSDM Extremes detector minimum register (DFSDMx_EXMIN) Address offset: 0x134 Reset value: 0x7FFF FF00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EXMIN[23:8] r0 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. EXMIN[7:0] r1 r1 r1 r1 r1 r1 r1 r1 DocID024597 Rev 1 EXMINCH[2:0] r r r 639/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 Bits 31:8 EXMIN[23:0]: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register. Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 EXMINCH[2:0]: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register. 21.7.15 DFSDM conversion timer register (DFSDMx_CNVTIMR) Address offset: 0x138 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CNVCNT[27:12] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. CNVCNT[11:0] r r r r r r r r r r r r Bits 31:4 CNVCNT[27:0]: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fDFSDM_CKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fDFSDM_CKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fDFSDM_CKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fDFSDM_CKIN) where: fDFSDM_CKIN is the channel input clock frequency (on given channel DFSDM_CKINy pin) or input data rate in case of parallel data input (from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time. Bits 3:0 Reserved, must be kept at reset value. 640/1680 DocID024597 Rev 1 RM0351 21.8 Digital filter for sigma delta modulators (DFSDM) DFSDM register map The following table summarizes the DFSDM registers. Register 0x00 DFSDM_ CHCFG0R1 DFSDMEN reset value 0 0 0 0 0 0 0 Res. Res. Res. 0 Res. 0 0 0 0 0 0 0 0 0 Res. 0 0 0 0 0 0 0 BKSCD[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. INDAT0[15:0] Res. Res. 0 WDATA[15:0] Res. Res. 0 Res. Res. 0 Res. Res. 0 SCDT[7:0] Res. Res. 0 0 Res. Res. 0 0 Res. Res. 0 0 Res. Res. 0 Res. Reserved 0 Res. 0 Res. 0 0 Res. 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 Res. AWFOSR[4:0] 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 DTRBS[4:0] Res. 0 0 SITP[1:0] Res. Res. SPICKSEL [1:0] Res. Res. 0 Res. Res. Res. Res. CHINSEL SCDEN Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 CHEN Res. 0 CKABEN Res. DATMPX[1:0] Res. Res. Res. Res. Res. DATPACK[1:0] Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 0 Res. 0 0 Res. 0 0 0 Res. Res. Res. 0 0 0 Res. Res. Res. 0 0 0 Res. Res. Res. 0 0 0 Res. Res. 0 0 0 INDAT1[15:0] reset value 0 0 0 DFSDM_ CHDATIN1R 0 0 Res. Res. Res. 0 0 0 Res. Res. Res. Res. 0 0 0 Res. Res. Res. Res. 0 0 0 Res. DFSDM_ AWSCD1R 0 0 0 Res. 0 Res. 0 Res. 0 AWFORD[1:0] 0 Res. 0 0 0 Res. 0 0 0 Res. 0 Res. 0 0 SCDT[7:0] OFFSET[23:0] reset value 0 WDATA[15:0] 0 DFSDM_ CHCFG1R2 Res. Res. Res. 0 SITP[1:0] Res. Res. Res. Res. DATMPX[1:0] 0 SPICKSEL [1:0] 0 0 DFSDM_ CHCFG1R1 Res. 0x34 0x3C 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 reset value 0x30 0 INDAT0[15:0] Reserved DFSDM_ CHWDAT1R 0 INDAT1[15:0] reset value 0x2C 0 Res. 0 BKSCD[3:0] 0 DFSDM_ CHDATIN0R Res. 0x28 0 Res. 0 Res. Res. AWFOSR[4:0] Res. 0 Res. AWFORD [1:0] 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. DFSDM_ CHWDAT0R Res. Res. Res. Res. Res. Res. Res. DFSDM_ AWSCD0R reset value 0x24 0 0 Res. 0x20 0 0 reset value 0x14 0x1C 0 reset value reset value 0x10 0 Res. 0 SCDEN 0 CHEN 0 CKABEN 0 CHINSEL 0 DTRBS[4:0] reset value 0x0C DATPACK[1:0] Res. Res. Res. Res. Res. Res. 0 OFFSET[23:0] Res. 0x08 CKOUTDIV[7:0] DFSDM_ CHCFG0R2 Res. 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset CKOUTSRC Table 123. DFSDM register map and reset values DocID024597 Rev 1 641/1680 650 642/1680 0 0 0 0 0 0 0 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. 0 0 Res. 0 0 0 reset value DocID024597 Rev 1 0 0 0 0 0 0 Res. Res. Res. Res. 0 0 0 0 0 0 0 0 BKSCD[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT1[15:0] 0 0 0 0 0 OFFSET[23:0] 0 0 0 Res. Res. Res. Res. 0 SCDT[7:0] WDATA[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS[4:0] SCDT[7:0] WDATA[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. DATMPX[1:0] DATPACK[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SCDEN 0 SITP[1:0] SPICKSEL[1:0] Res. CHEN CKABEN CHINSEL 0 0 0 Res. Res. DTRBS[4:0] Res. 0 0 0 SITP[1:0] INDAT1[15:0] 0 0 SPICKSEL[1:0] 0 0 0 0 0 Res. 0 Res. 0 Res. 0 Res. 0 0 SCDEN 0 0 Res. 0 Res. 0 CHEN BKSCD[3:0] CKABEN Res. Res. 0 Res. 0 Res. Res. Res. OFFSET[23:0] Res. 0 CHINSEL Res. Res. DFSDM_ CHCFG2R1 0 SITP[1:0] 0 Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x40 0 SPICKSEL[1:0] 0 0 Res. 0 0 Res. 0 0 0 Res. AWFOSR[4:0] 0 0 SCDEN 0 Res. 0 Res. reset value Res. 0 Res. 0 DATMPX[1:0] 0 DATPACK[1:0] 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. AWFORD[1:0] Res. Register Res. Offset 0 Res. 0 0 Res. 0 0 Res. Res. Res. Res. 0 Res. reset value 0 Res. Res. Res. Res. Res. AWFOSR[4:0] 0 0 Res. 0 0 0 0 CHEN 0 0 0 0 CKABEN 0 0 0 Res. Res. Res. Res. Res. 0 DATMPX[1:0] 0 Res. Res. Res. Res. reset value DATPACK[1:0] 0 0 Res. 0 0 0 Res. Res. Res. reset value 0 Res. DFSDM_ CHCFG3R2 0 0 CHINSEL Res. Res. DFSDM_ AWSCD3R 0 Res. 0 0 Res. 0 0 Res. 0 0 0 Res. Res. Res. 0 0 0 Res. Res. Res. DFSDM_ CHDATIN3R 0 Res. reset value 0 Res. Res. Res. 0 Res. DFSDM_ AWSCD2R AWFORD[1:0] Res. Res. 0 Res. Res. Res. 0 Res. 0 Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 0 Res. 0 Res. Res. Res. DFSDM_ CHDATIN2R Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 0 Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 0 Res. reset value Res. Res. 0 Res. Res. Res. reset value 0 Res. Res. DFSDM_ CHCFG3R1 Res. reset value Res. Res. DFSDM_ CHCFG4R1 Res. DFSDM_ CHWDAT3R 0 Res. Reserved Res. DFSDM_ CHCFG2R2 Res. Res. 0x80 Reserved Res. 0x74 0x7C Res. 0x70 Res. 0x6C Res. 0x68 Res. 0x64 Res. 0x60 Res. reset value Res. 0x54 0x5C DFSDM_ CHWDAT2R Res. 0x50 Res. 0x4C Res. 0x48 Res. 0x44 Res. Digital filter for sigma delta modulators (DFSDM) RM0351 Table 123. DFSDM register map and reset values (continued) 0 INDAT0[15:0] 0 INDAT0[15:0] 0 0 0 RM0351 Digital filter for sigma delta modulators (DFSDM) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CHINSEL CHEN CKABEN SCDEN Res. 0 0 0 0 0 0 0 0 BKSCD[3:0] Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP[1:0] 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CHINSEL CHEN CKABEN SCDEN Res. 0 0 0 0 0 0 0 0 DTRBS[4:0] 0 0 DocID024597 Rev 1 0 0 0 0 0 0 0 0 0 0 0 0 SITP[1:0] 0 0 0 Res. DATMPX[1:0] DATPACK[1:0] Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 OFFSET[23:0] 0 0 SCDT[7:0] WDATA[15:0] 0 0 0 0 0 DFSDM_ CHCFG6R1 0 0 0 0 Reserved DFSDM_ CHCFG6R2 0 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 0 0 INDAT0[15:0] Res. 0 0 0 Res. 0 0 Res. AWFOSR[4:0] 0 0 Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 0 Res. Res. 0 0 Res. 0 Res. 0 DTRBS[4:0] Res. 0 Res. Res. Res. 0 SPICKSEL[1:0] Res. Res. Res. DATMPX[1:0] Res. Res. Res. Res. DATPACK[1:0] Res. Res. 0 Res. 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 INDAT1[15:0] 0 0 0 0 DFSDM_ CHDATIN5R 0 0 Res. Res. Res. Res. Res. Res. 0 0 WDATA[15:0] 0 Res. Res. 0 0 0 Res. DFSDM_ AWSCD5R 0 0 0 Res. 0 Res. 0 0 0 Res. 0 Res. 0 0 0 Res. 0 0 0 Res. 0 AWFORD[1:0] 0 0 0 0 Res. 0 0 0 SCDT[7:0] OFFSET[23:0] reset value reset value 0 0 0 reset value 0xC4 0 0 0 Res. 0xC0 0 0 DFSDM_ CHCFG5R2 reset value 0xB4 0xBC BKSCD[3:0] 0 0 reset value 0xB0 0 0 DFSDM_ CHCFG5R1 DFSDM_ CHWDAT5R 0 0 Reserved reset value 0xAC 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0xA8 0 INDAT0[15:0] reset value 0xA4 0 0 0 INDAT1[15:0] Res. 0xA0 0 0 Res. reset value 0x94 0x9C 0 Res. 0x90 Res. AWFOSR[4:0] reset value DFSDM_ CHDATIN4R Res. 0 Res. 0 Res. Res. 0 SPICKSEL[1:0] 0 0 Res. 0 0 Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0x8C DFSDM_ CHWDAT4R Res. reset value 0 Res. DFSDM_ AWSCD4R 0 Res. 0 Res. 0 Res. 0 Res. 0 DTRBS[4:0] Res. 0 Res. 0 AWFORD[1:0] 0 Res. 0 Res. reset value Res. 0x88 OFFSET[23:0] Res. DFSDM_ CHCFG4R2 Res. 0x84 Res. Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 123. DFSDM register map and reset values (continued) 0 643/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 0 0 0 0 0 Res. Res. Res. Res. reset value 644/1680 0 Res. Res. Res. 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CHINSEL CHEN CKABEN SCDEN Res. 0 0 0 0 0 0 Res. Res. Res. AWFOSR[4:0] 0 0 0 0 0 BKSCD[3:0] Res. 0 Res. 0 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. INDAT0[15:0] Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 WDATA[15:0] Res. Res. 0 Res. Res. 0 Res. Res. 0 SCDT[7:0] Res. Reserved 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 Res. 0 0 0 Res. 0 0 0 0 DTRBS[4:0] Res. 0 0 Res. 0 Res. 0 Res. DATMPX[1:0] 0 SPICKSEL[1:0] Res. Res. Res. DATPACK[1:0] Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 0 0 Res. Res. Res. 0 0 0 Res. Res. Res. 0 0 0 Res. Res. Res. 0 0 0 INDAT1[15:0] reset value 0 0 0 DFSDM_ CHDATIN7R 0 0 Res. Res. Res. 0 0 0 Res. Res. 0 Res. Res. Res. Res. 0 Res. 0xF4 0xFC 0 0 reset value 0xF0 0 0 Res. Res. Res. Res. 0 Res. DFSDM_ AWSCD7R 0 0 0 Res. 0 0 0 Res. 0 AWFORD[1:0] 0 Res. 0 0 0 Res. 0 0 0 Res. 0 Res. 0 reset value 0xEC 0 OFFSET[23:0] 0 0 WDATA[15:0] 0 reset value 0 0 DFSDM_ CHCFG7R1 DFSDM_ CHCFG7R2 0 0 Reserved DFSDM_ CHWDAT7R 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0xE8 0 INDAT0[15:0] reset value 0xE4 0 INDAT1[15:0] Res. 0xE0 0 0 DFSDM_ CHDATIN6R reset value 0xD4 0xDC 0 SCDT[7:0] Res. 0xD0 BKSCD[3:0] Res. Res. Res. 0 AWFOSR[4:0] Res. AWFORD[1:0] 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0xCC DFSDM_ CHWDAT6R Res. reset value Res. Res. Res. Res. DFSDM_ AWSCD6R Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0xC8 Res. Register Res. Offset Res. Table 123. DFSDM register map and reset values (continued) DocID024597 Rev 1 RM0351 Digital filter for sigma delta modulators (DFSDM) The following table summarizes the DFSDMx registers. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFSDM0_ AWSR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN Res. JEOCF JEOCIE Res. JSW START Res. REOCF REOCIE JSYNC JOVRF CLR JOVRF JOVRIE JSCAN AWDIE AWDF ROVRF Res. CLR ROVRF ROVRIE Res. JDMAEN SCDIE 0 0 1 0 0 0 Res. JDATACH [2:0] 0 0 0 0 0 0 0 0 RDATA CH[2:0] 0 0 0 BKAWH[3:0] 0 0 0 0 BKAWL[3:0] 0 0 0 0 0 0 0 0 AWLTF[7:0] 0 0 0 0 CLRAWHTF[7:0] 0 DocID024597 Rev 1 0 Res. 0 AWHTF[7:0] 0 Res. 0 0 AWLT[23:0] reset value Res. Res. Res. 0 CKABIE Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 AWHT[23:0] DFSDM0_ AWLTR DFSDM0_ AWCFR 0 RDATA[23:0] reset value 0x12C 0 0 Res. 0 0 Res. 0 0 RPEND 0 0 Res. 0 0 0 Res. 0 0 Res. 0 JDATA[23:0] 0 Res. 0 0 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 Res. Res. Res. 0 Res. 0x128 0 DFSDM0_ AWHTR reset value 0x124 0 DFSDM0_ RDATAR reset value 0x120 0 DFSDM0_ JDATAR reset value 0x11C 0 0 IOSR[7:0] Res. 0x118 0 FOSR[9:0] Res. reset value Res. DFSDM0_ FCR Res. 0x114 0 JCHG[7:0] 0 FORD[2:0] reset value 0 0 Res. JEXTSEL[2:0] Res. Res. JEXTEN[1:0] Res. 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 0 Res. 0 0 Res. 0 0 Res. 0 Res. 0 Res. 0 0 Res. 1 0 Res. 1 0 Res. 1 0 JCIP 1 0 Res. 1 0 0 Res. 1 0 0 RCIP 0 Res. 1 0 Res. 0 CLRCKABF[7:0] 0 Res. Res. Res. Res. RDMAEN Res. 1 Res. 0 0 Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. 0 0 CKABF[7:0] CLRSCDF[7:0] 0 0 EXCH[7:0] Res. 0 0 Res. 0 0 Res. 0 Res. DFSDM0_ JCHGR 0 0 Res. 0 DFSDM0_ ICR reset value 0x110 0 Res. 0x10C SCDF[7:0] Res. reset value 0 Res. DFSDM0_ ISR 0 AWDCH[7:0] 0 Res. 0x108 0 Res. Res. reset value 0 RCONT 0 RSW START 0 RSYNC 0 Res. Res. RCH[2:0] Res. Res. 0 Res. FAST DFSDM0_ CR2 0 Res. 0x104 Res. reset value Res. DFSDM0_ CR1 Res. 0x100 AWFSEL Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 124. DFSDMx register map and reset values 0 0 0 0 CLRAWLTF[7:0] 0 0 0 0 0 0 0 0 645/1680 650 0x218 646/1680 reset value reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFSDM1_ JDATAR 0 0 0 0 0 0 0 0 0 JDATA[23:0] 0 0 DocID024597 Rev 1 0 0 0 0 0 0 0 Res. Res. reset value 0 0 0 0 REOCF JEOCF 0 0 0 0 0 JCHG[7:0] 0 0 IOSR[7:0] 0 0 0 0 0 Res. 0 Res. JOVRF 0 CLR JOVRF reset value ROVRF 0 Res. Res. 0 Res. 0 Res. 0 DFEN EXMINCH[2:0] Res. Res. Res. 0 JSW START Res. Res. Res. 0 JEOCIE Res. Res. JSYNC 0 CLR ROVRF 0 Res. CNVCNT[27:0] JSCAN 0 AWDF 1 Res. 1 Res. 1 JDMAEN 1 Res. 1 Res. Res. 1 Res. Res. 1 Res. Res. Res. 1 Res. Res. 1 Res. Res. Res. 1 Res. EXCH[7:0] Res. 0 JEXTSEL[2:0] Res. 0 Res. 0 Res. 0 REOCIE Res. 0 Res. 0 JOVRIE Res. 0 Res. 0 ROVRIE 0 Res. 0 Res. 0 Res. Res. Res. Res. 0 Res. 0 AWDIE 0 Res. 0 Res. 0 JDATACH[2:0] Res. Res. Res. 0 Res. 0 Res. Res. Res. 0 JEXTEN[1:0] 0 Res. 0 Res. 0 0 Res. 0 0 Res. reset value Res. 0 JCIP 0 Res. AWDCH[7:0] Res. 0 Res. 0 Res. 0 RCIP 0 0 Res. 0 Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. Res. 0 Res. 0 RSW START EXMIN[23:0] 0 Res. FOSR[9:0] Res. Res. 0 Res. 1 Res. 0 Res. 0 RCONT 0 Res. 0 Res. 0 1 Res. 0 Res. 0 RSYNC DFSDM0_ CNVTIMR 0 Res. 0 Res. 1 Res. Res. 0 Res. 0 Res. 0 Res. 1 Res. Res. RDMAEN 1 0 Res. 0 Res. Res. DFSDM0_ EXMIN Res. Res. Res. Res. 0 Res. 0 Res. reset value 1 Res. 0 0 Res. Res. Res. 0 Res. Res. 0 Res. 0 Res. Res. Res. 0 Res. 1 Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. FAST RCH[2:0] Res. Res. 1 Res. Res. Res. Res. Res. Res. Res. Res. 1 0 Res. DFSDM1_ FCR 1 0 Res. DFSDM1_ JCHGR 0 Res. DFSDM1_ ICR Res. DFSDM1_ ISR EXMAXCH[2:0] Res. Res. Res. Res. Res. EXMAX[23:0] Res. 0x214 DFSDM1_ CR2 AWFSEL reset value 0 1 0 Res. 0x210 DFSDM1_ CR1 1 0 Res. 0x20C Reserved 0 Res. 0x208 0 0 Res. 0x204 reset value 1 Res. 0x200 0 0 Res. 0x13C 0x1FC Res. 0x138 Res. reset value 1 Res. 0x134 Res. reset value Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DFSDM0_ EXMAX Res. 0x130 Res. Register Res. Offset FORD[2:0] Digital filter for sigma delta modulators (DFSDM) RM0351 Table 124. DFSDMx register map and reset values (continued) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 RM0351 Digital filter for sigma delta modulators (DFSDM) 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFSDM1_ EXMIN 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 DFSDM1_ CNVTIMR 1 1 0 CLRAWHTF[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 - - - - 0 0 0 0 0 0 0 0 JEOCF 0 REOCF 0 0 0 0 0 0 Res. 0 Res. 0 JOVRF 0 ROVRF Res. Res. 0 CLR JOVRF Res. Res. Res. 0 CLR ROVRF Res. Res. Res. Res. 0 Res. 0 Res. 0 0 0 AWDF Res. JEXTSEL[2:0] Res. 0 Res. 0 Res. 0 0 0 Res. Res. DocID024597 Rev 1 0 Res. Res. Res. reset value 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. - Res. - Res. reset value Res. - Res. - Res. DFSDM2_ ISR 0 Res. 0 Res. 0 EXCH[7:0] Res. 0 Res. 0 0 Res. AWDCH[7:0] 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. 0 0 Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. 0 RSW START 0 Res. 0 RCONT 0 Res. 0 RSYNC 0 Res. 0 Res. 0 Res. 0 RDMAEN 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 0 0 0 0 0 0 0 0 RCH[2:0] 0 0 0 Res. 0 FAST 0 Res. Reserved 0 Res. 0 Res. RPEND Res. 0 CNVCNT[27:0] reset value 0 CLRAWLTF[7:0] EXMIN[23:0] 0 0 Res. 0 0 AWLTF[7:0] EXMAX[23:0] 1 Res. 0 AWHTF[7:0] 0 Res. 0 EXMAXCH[2:0] 0 BKAWL[3:0] EXMINCH[2:0] 0 0 Res. 0 0 Res. 0 0 Res. 0 DFSDM1_ EXMAX 0 Res. 0 Res. 0 DFEN 0 DFSDM2_ ICR 0 JSW START 0 Res. 0x30C 0 JEOCIE 0 reset value 0x308 0 REOCIE 0 DFSDM2_ CR2 0 Res. 0 reset value 0x304 0 Res. 0 DFSDM2_ CR1 0 AWLT[23:0] Res. 0x300 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 0 BKAWH[3:0] JSYNC 0 0 JOVRIE 0 0 ROVRIE 0 Res. 0 0 Res. 0 Res. 0x23C 0x2FC 0 Res. 0 AWFSEL 0x238 0 Res. 0 DFSDM1_ AWSR reset value 0 JSCAN 0 Res. 0x234 0 AWDIE 0 reset value reset value 0 Res. 0 reset value 0x230 0 Res. 0 reset value 0x22C 0 AWHT[23:0] DFSDM1_ AWLTR DFSDM1_ AWCFR 0 Res. 0 Res. Res. 0 Res. 0 Res. 0 JDMAEN 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 RDATA CH[2:0] Res. 0 Res. 0x228 0 JEXTEN[1:0] reset value 0x224 0 JCIP 0x220 0 DFSDM1_ AWHTR RCIP reset value RDATA[23:0] Res. DFSDM1_ RDATAR Res. 0x21C Res. Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 124. DFSDMx register map and reset values (continued) 0 0 647/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 648/1680 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFSDM2_ EXMIN 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 Res. Res. Res. Res. Res. JEXTSEL[2:0] Res. Res. Res. 0 0 DocID024597 Rev 1 0 0 Res. Res. 0 0 JEXTEN[1:0] Res. Res. Res. 0 Res. 0 Res. Res. 0 Res. 0 RSW START 0 Res. 0 RCONT 0 Res. 0 RSYNC 0 Res. 0 Res. 0 Res. 0 RDMAEN 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 0 0 0 0 Res. 0 0 0 0 EXMAX CH[2:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCH[2:0] 0 0 0 Res. 0 Res. 0 Res. Reserved 0 FAST 0 0 BKAWL[3:0] 0 CNVCNT[27:0] reset value 0 CLRAWLTF[7:0] EXMIN[23:0] DFSDM2_ CNVTIMR 0 Res. 0 0 AWLTF[7:0] 0 0 0 BKAWH[3:0] 0 Res. 0 0 0 0 EXMAX[23:0] 0 Res. 0 CLRAWHTF[7:0] 0 1 0 0 AWHTF[7:0] 0 DFSDM2_ EXMAX Res. Res. Res. Res. Res. Res. 0 AWLT[23:0] 0 reset value 0 Res. 0 0 DFSDM3_ CR1 0 AWHT[23:0] Res. 0x400 0 EXMINCH[2:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 RDATA CH[2:0] DFEN 0 0 JSW START 0 0 Res. 0 0 Res. 0 Res. 0x33C 0x3FC 0 Res. 0 Res. 0x338 0 Res. 0 DFSDM2_ AWSR reset value 0 Res. 0 AWFSEL 0x334 0 Res. 0 reset value reset value 0 0 Res. 0 reset value 0x330 0 Res. 0 DFSDM2_ AWLTR DFSDM2_ AWCFR 0 RDATA[23:0] reset value 0x32C 0 Res. 0 0 JSYNC 0 RPEND 0 Res. 0 Res. 0 Res. 0 Res. 0 0 Res. 0 1 JSCAN 0 Res. 0 Res. 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 JDATA[23:0] 0 Res. 0 Res. 0 0 IOSR[7:0] Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 JDMAEN 0 0 Res. 0 Res. Res. Res. Res. 0 Res. 0x328 0 DFSDM2_ AWHTR reset value 0x324 0 DFSDM2_ RDATAR reset value 0x320 0 FOSR[9:0] DFSDM2_ JDATAR reset value 0x31C 0 Res. DFSDM2_ FCR reset value 0x318 FORD[2:0] 0x314 0 JDATACH[2:0] reset value JCHG[7:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DFSDM2_ JCHGR Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x310 Res. Register Res. Offset Res. Table 124. DFSDMx register map and reset values (continued) RM0351 Digital filter for sigma delta modulators (DFSDM) JEOCIE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFSDM3_ AWSR 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID024597 Rev 1 1 0 0 0 JDATACH[2:0] 0 0 0 0 0 0 RDATA CH[2:0] 0 0 0 BKAWH[3:0] 0 0 0 0 0 BKAWL[3:0] 0 0 0 0 0 0 0 0 AWLTF[7:0] 0 0 0 0 CLRAWHTF[7:0] 0 0 0 0 CLRAWLTF[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAX[23:0] 1 Res. 0 AWHTF[7:0] 0 DFSDM3_ EXMAX Res. Res. Res. Res. Res. Res. 0 AWLT[23:0] reset value reset value 0 AWHT[23:0] reset value 0x430 0 Res. 0 reset value 0x42C 0 RDATA[23:0] DFSDM3_ AWLTR DFSDM3_ AWCFR 0 Res. 0 0 0 0 0 0 0 0 EXMAXCH[2:0] 0 Res. 0 Res. 0 RPEND 0 Res. 0 Res. 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 JDATA[23:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 0 Res. 0 0 Res. 0 Res. Res. Res. 0 Res. 0x428 0 DFSDM3_ AWHTR reset value 0x424 0 DFSDM3_ RDATAR reset value 0x420 0 DFSDM3_ JDATAR reset value 0x41C 0 0 IOSR[7:0] Res. 0x418 0 FOSR[9:0] 0 Res. reset value Res. DFSDM3_ FCR Res. 0x414 0 FORD[2:0] reset value 0 JCHG[7:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x410 DFSDM3_ JCHGR Res. reset value Res. JEOCF JOVRIE REOCIE 0 Res. REOCF ROVRIE JOVRF 0 ROVRF 0 CLR JOVRF 0 CLR ROVRF Res. AWDIE 0 AWDF Res. Res. 0 Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DFSDM3_ ICR Res. 0x40C Res. reset value Res. 0 Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. 0 Res. 0 Res. 0 JCIP 0 Res. 0 Res. 0 RCIP 0 Res. 0 Res. EXCH[7:0] Res. Res. Res. Res. Res. Res. Res. Res. DFSDM3_ ISR Res. 0x408 Res. reset value AWDCH[7:0] Res. Res. Res. Res. DFSDM3_ CR2 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x404 Res. Register Res. Offset Res. Table 124. DFSDMx register map and reset values (continued) 0 0 0 649/1680 650 Digital filter for sigma delta modulators (DFSDM) RM0351 1 1 1 1 DFSDM3_ CNVTIMR 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Reserved 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. CNVCNT[27:0] reset value EXMINCH[2:0] Res. Res. 0 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. 650/1680 DocID024597 Rev 1 0 0 Res. 1 Res. 1 Res. 1 Res. 1 Res. 1 Res. 1 Res. 0x43C 0x4FC 1 Res. 0x438 0 Res. reset value EXMIN[23:0] Res. DFSDM3_ EXMIN Res. 0x434 Res. Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 124. DFSDMx register map and reset values (continued) RM0351 Liquid crystal display controller (LCD) 22 Liquid crystal display controller (LCD) 22.1 Introduction The LCD controller is a digital controller/driver for monochrome passive liquid crystal display (LCD) with up to 8 common terminals and up to 44 segment terminals to drive 176 (44x4) or 320 (40x8) LCD picture elements (pixels). The exact number of terminals depends on the device pinout as described in the datasheet. The LCD is made up of several segments (pixels or complete symbols) which can be turned visible or invisible. Each segment consists of a layer of liquid crystal molecules aligned between two electrodes. When a voltage greater than a threshold voltage is applied across the liquid crystal, the segment becomes visible. The segment voltage must be alternated to avoid an electrophoresis effect in the liquid crystal (which degrades the display). The waveform across a segment must then be generated so as to avoid having a direct current (DC). Glossary Bias: Number of voltage levels used when driving an LCD. It is defined as 1/(number of voltage levels used to drive an LCD display - 1). Boost circuit: Contrast controller circuit Common: Electrical connection terminal connected to several segments (44 segments). Duty ratio: Number defined as 1/(number of common terminals on a given LCD display). Frame: One period of the waveform written to a segment. Frame rate: Number of frames per second, that is, the number of times the LCD segments are energized per second. LCD: (liquid crystal display) a passive display panel with terminals leading directly to a segment. Segment: The smallest viewing element (a single bar or dot that is used to help create a character on an LCD display). DocID024597 Rev 1 651/1680 682 Liquid crystal display controller (LCD) 22.2 RM0351 LCD main features • Highly flexible frame rate control. • Supports Static, 1/2, 1/3, 1/4 and 1/8 duty. • Supports Static, 1/2, 1/3 and 1/4 bias. • Double buffered memory allows data in LCD_RAM registers to be updated at any time by the application firmware without affecting the integrity of the data displayed. – LCD data RAM of up to 16 x 32-bit registers which contain pixel information (active/inactive) • Software selectable LCD output voltage (contrast) from VLCDmin to VLCDmax. • No need for external analog components: • – A step-up converter is embedded to generate an internal VLCD voltage higher than VDD – Software selection between external and internal VLCD voltage source. In case of an external source, the internal boost circuit is disabled to reduce power consumption – A resistive network is embedded to generate intermediate VLCD voltages – The structure of the resistive network is configurable by software to adapt the power consumption to match the capacitive charge required by the LCD panel – Integrated voltage output buffers for higher LCD driving capability. The contrast can be adjusted using two different methods: – When using the internal step-up converter, the software can adjust VLCD between VLCDmin and VLCDmax. – Programmable dead time (up to 8 phase periods) between frames. • Full support of low-power modes: the LCD controller can be displayed in Sleep, Lowpower run, Low-power sleep and Stop modes or can be fully disabled to reduce power consumption. • Built in phase inversion for reduced power consumption and EMI (electromagnetic interference). • Start of frame interrupt to synchronize the software when updating the LCD data RAM. • Blink capability: • – Up to 1, 2, 3, 4, 8 or all pixels which can be programmed to blink at a configurable frequency – Software adjustable blink frequency to achieve around 0.5 Hz, 1 Hz, 2 Hz or 4 Hz. Used LCD segment and common pins should be configured as GPIO alternate functions and unused segment and common pins can be used for general purpose I/O or for another peripheral alternate function. Note: When the LCD relies on the internal step-up converter, the VLCD pin should be connected to VSS with a capacitor. Its typical value is 1 µF (see CEXT value in the product datasheets for further information). Note: The VLCD pin should be connected to VDDA if the LCD peripheral is not used. 652/1680 DocID024597 Rev 1 RM0351 Liquid crystal display controller (LCD) 22.3 LCD functional description 22.3.1 General description The LCD controller has five main blocks (see Figure 153): Figure 153. LCD controller block diagram )5(48(1&<*(1(5$725 /&'&/. ELWSUHVFDOHU /&'&/. 36>@ /&' 5(*6 /&'&/. &/2&.08; FNBSV ',9>@ 'LYLGHE\WR ,QWHUUXSW FNBGLY &20>@ WR08; 6(*>@ $QDORJ VZLWFK DUUUD\ $QDORJ VZLWFK DUUD\ 6(* '5,9(5 5($'< 67$7,& 6(*>@ 6(*>@ /&' 5(*6 &20 &20>@ 6(*>@ '$7$%86 $''5(66%86 &20 '5,9(5 /&'5$0 [ELWV &20 6(* 6(* &20 6(* &20 08; 96(/ 6(* &20 6(*>@ (1 38/6(*(1 +' 92/7$*( *(1(5$725 6(* &20 966 9/&' 6(* &20 9/&' %,$6>@ &&>@ &2175$67 &21752//(5 $QDORJVWHSXS FRQYHUWHU Note: 6(* 9/&' 9/&' ,23RUWV 069 LCDCLK is the same as RTCCLK. Please refer to the RTC/LCD clock description in the RCC section of this manual. The frequency generator allows you to achieve various LCD frame rates starting from an LCD input clock frequency (LCDCLK) which can vary from 32 kHz up to 1 MHz. 3 different clock sources can be used to provide the LCD clock (LCDCLK/RTCCLK): • 32 kHz Low speed external RC (LSE) • 32 kHz Low speed internal RC (LSI) • High speed external (HSE) divided by 32 DocID024597 Rev 1 653/1680 682 Liquid crystal display controller (LCD) 22.3.2 RM0351 Frequency generator This clock source must be stable in order to obtain accurate LCD timing and hence minimize DC voltage offset across LCD segments. The input clock LCDCLK can be divided by any value from 1 to 215x 31 (see Section 22.6.2: LCD frame control register (LCD_FCR) on page 674). The frequency generator consists of a prescaler (16-bit ripple counter) and a 16 to 31 clock divider. The PS[3:0] bits, in the LCD_FCR register, select LCDCLK divided by 2PS[3:0]. If a finer resolution rate is required, the DIV[3:0] bits, in the LCD_FCR register, can be used to divide the clock further by 16 to 31. In this way you can roughly scale the frequency, and then fine-tune it by linearly scaling the clock with the counter. The output of the frequency generator block is fck_div which constitutes the time base for the entire LCD controller. The ck_div frequency is equivalent to the LCD phase frequency, rather than the frame frequency (they are equal only in case of static duty). The frame frequency (fframe) is obtained from fck_div by dividing it by the number of active common terminals (or by multiplying it for the duty). Thus the relation between the input clock frequency (fLCDCLK) of the frequency generator and its output clock frequency fck_div is: f LCDCLK f ckdiv = -----------------------------------------------PS 2 × 〈 16 + DIV〉 f frame = f ckdiv × duty This makes the frequency generator very flexible. An example of frame rate calculation is shown in Table 125. Table 125. Example of frame rate calculation LCDCLK PS[3:0] DIV[3:0] Ratio Duty fframe 32.768 kHz 3 1 136 1/8 30.12 Hz 32.768 kHz 4 1 272 1/4 30.12 Hz 32.768 kHz 4 6 352 1/3 31.03 Hz 32.768 kHz 5 1 544 1/2 30.12 Hz 32.768 kHz 6 1 1088 static 30.12 Hz 32.768 kHz 1 4 40 1/8 102.40 Hz 32.768 kHz 2 4 80 1/4 102.40 Hz 32.768 kHz 2 11 108 1/3 101.14 Hz 32.768 kHz 3 4 160 1/2 102.40 Hz 32.768 kHz 4 4 320 static 102.40 Hz 1.00 MHz 6 3 1216 1/8 102.80 Hz 1.00 MHz 7 3 2432 1/4 102.80 Hz 1.00 MHz 7 10 3328 1/3 100.16 Hz 1.00 MHz 8 3 4864 1/2 102.80 Hz 1.00 MHz 9 3 9728 static 102.80 Hz The frame frequency must be selected to be within a range of around ~30 Hz to ~100 Hz and is a compromise between power consumption and the acceptable refresh rate. In 654/1680 DocID024597 Rev 1 RM0351 Liquid crystal display controller (LCD) addition, a dedicated blink prescaler selects the blink frequency. This frequency is defined as: fBLINK = fck_div/2(BLINKF + 3), with BLINKF[2:0] = 0, 1, 2, ... ,7 The blink frequency achieved is in the range of 0.5 Hz, 1 Hz, 2 Hz or 4 Hz. Common driver Common signals are generated by the common driver block (see Figure 153). COM signal bias Each COM signal has identical waveforms, but different phases. It has its max amplitude VLCD or VSS only in the corresponding phase of a frame cycle, while during the other phases, the signal amplitude is: • 1/4 VLCD or 3/4 VLCD in case of 1/4 bias • 1/3 VLCD or 2/3 VLCD in case of 1/3 bias • and 1/2 VLCD in case of 1/2 bias. Selection between 1/2, 1/3 and 1/4 bias mode can be done through the BIAS bits in the LCD_CR register. A pixel is activated when both of its corresponding common and segment lines are active during the same phase, it means when the voltage difference between common and segment is maximum during this phase. Common signals are phase inverted in order to reduce EMI. As shown in Figure 154, with phase inversion, there is a mean voltage of 1/2 VLCD at the end of every odd cycle. Figure 154. 1/3 bias, 1/4 duty 2GGIUDPH (YHQIUDPH &RPPRQ 9/&' 9/&' 9/&' 966 &RPDFWLYH &RPLQDFWLYH &RPLQDFWLYH &RPLQDFWLYH &RPDFWLYH &RPLQDFWLYH &RPLQDFWLYH &RPLQDFWLYH 9/&' 6HJPHQW 22.3.3 9/&' 9/&' 966 &RPDFWLYH &RPDFWLYH 3KDVH 3KDVH &RPLQDFWLYH &RPLQDFWLYH 3KDVH 3KDVH &RPDFWLYH &RPDFWLYH 3KDVH 3KDVH &RPLQDFWLYH &RPLQDFWLYH 3KDVH 3KDVH 069 In case of 1/2 bias (BIAS = 01) the VLCD pin generates an intermediate voltage equal to 1/2 VLCD on node b for odd and even frames (see Figure 157). COM signal duty Depending on the DUTY[2:0] bits in the LCD_CR register, the COM signals are generated with static duty (see Figure 156), 1/2 duty (see Figure 157), 1/3 duty (see Figure 158), 1/4 duty (see Figure 159) or 1/8 duty (see Figure 160). DocID024597 Rev 1 655/1680 682 Liquid crystal display controller (LCD) RM0351 COM[n] n[0 to 7] is active during phase n in the odd frame, so the COM pin is driven to VLCD. During phase n of the even frame the COM pin is driven to VSS. In the case of 1/3 or 1/4) bias: • COM[n] is inactive during phases other than n so the COM pin is driven to 1/3 (1/4) VLCD during odd frames and to 2/3 (3/4) VLCD during even frames In the case of 1/2 bias: • If COM[n] is inactive during phases other than n, the COM pin is always driven (odd and even frame) to 1/2 VLCD. When static duty is selected, the segment lines are not multiplexed, which means that each segment output corresponds to one pixel. In this way only up to 44 pixels can be driven. COM[0] is always active while COM[7:1] are not used and are driven to VSS. When the LCDEN bit in the LCD_CR register is reset, all common lines are pulled down to VSS and the ENS flag in the LCD_SR register becomes 0. Static duty means that COM[0] is always active and only two voltage levels are used for the segment and common lines: VLCD and VSS. A pixel is active if the corresponding SEG line has a voltage opposite to that of the COM, and inactive when the voltages are equal. In this way the LCD has maximum contrast (see Figure 155, Figure 156). In the Figure 155 pixel 0 is active while pixel 1 is inactive. Figure 155. Static duty case 1 2GGIUDPH (YHQIUDPH 2GGIUDPH (YHQIUDPH 9/&' &20 966 9/&' 6(* 966 9/&' 6(* 966 9/&' &20 6(* 9/&' 9/&' &20 6(* 9/&' 069 In each frame there is only one phase, this is why fframe is equal to fLCD. If 1/4 duty is selected there are four phases in a frame in which COM[0] is active during phase 0, COM[1] is active during phase 1, COM[2] is active during phase 2, and COM[3] is active during phase 3. 656/1680 DocID024597 Rev 1 RM0351 Liquid crystal display controller (LCD) Figure 156. Static duty case 2 /LTXLGFU\VWDOGLVSOD\ DQGWHUPLQDOFRQQHFWLRQ 9 3,1 &20 9 9 3,1 6(* 9 &20 9 6(* 3,1 6(* 9 6(* 9 6(* 6(* 6(* 6(* 6(* 6(* &206(* VHOHFWHGZDYHIRUP 9 9 &206(* QRQVHOHFWHGZDYHIRUP 9 069 In this mode, the segment terminals are multiplexed and each of them control four pixels. A pixel is activated only when both of its corresponding SEG and COM lines are active in the same phase. In case of 1/4 duty, to deactivate pixel 0 connected to COM[0] the SEG[0] needs to be inactive during the phase 0 when COM[0] is active. To activate pixel 0 connected to COM[1], the SEG[0] needs to be active during phase 1 when COM[1] is active (see Figure 159). To activate pixels from 0 to 43 connected to COM[0], SEG[0:43] need to be active during phase 0 when COM[0] is active. These considerations can be extended to the other pixels. 8 to 1 Mux When COM[0] is active the common driver block, also drives the 8 to 1 mux shown in Figure 153 in order to select the content of first two RAM register locations. When COM[7] is active, the output of the 8 to 1 mux is the content of the last two RAM locations. DocID024597 Rev 1 657/1680 682 Liquid crystal display controller (LCD) RM0351 Figure 157. 1/2 duty, 1/2 bias /LTXLGFU\VWDOGLVSOD\ DQGWHUPLQDOFRQQHFWLRQ 9 3,1 &20 9 9 9 &20 3,1 &20 9 9 9 &20 3,1 6(* 9 9 3,1 6(* 9 9 &206(* VHOHFWHGZDYHIRUP 9 9 9 6(* 6(* 6(* 6(* 9 9 &206(* QRQVHOHFWHGZDYHIRUP 9 9 069 22.3.4 Segment driver The segment driver block controls the SEG lines according to the pixel data coming from the 8 to 1 mux driven in each phase by the common driver block. In the case of 1/4 or 1/8 duty When COM[0] is active, the pixel information (active/inactive) related to the pixel connected to COM[0] (content of the first two LCD_RAM locations) goes through the 8 to 1 mux. The SEG[n] pin n [0 to 43] is driven to VSS (indicating pixel n is active when COM[0] is active) in phase 0 of the odd frame. The SEG[n] pin is driven to VLCD in phase 0 of the even frame. If pixel n is inactive then the SEG[n] pin is driven to 2/3 (2/4) VLCD in the odd frame or 1/3 (2/4) VLCD in the even frame (current inversion in VLCD pad) (see Figure 154). In case of 1/2 bias, if the pixel is inactive the SEG[n] pin is driven to VLCD in the odd and to VSS in the even frame. When the LCD controller is disabled (LCDEN bit cleared in the LCD_CR register) then the SEG lines are pulled down to VSS. 658/1680 DocID024597 Rev 1 RM0351 Liquid crystal display controller (LCD) Figure 158. 1/3 duty, 1/3 bias 9 3,1 &20 9 9 /LTXLGFU\VWDOGLVSOD\ DQGWHUPLQDOFRQQHFWLRQ 9 9 3,1 &20 9 9 &20 9 9 3,1 &20 &20 9 9 9 &20 9 3,1 6(* 9 9 9 9 3,1 6(* 9 9 9 9 6(* 6(* 9 6(* 9 &206(* VHOHFWHGZDYHIRUP 9 9 9 9 9 &206(* QRQVHOHFWHGZDYHIRUP 9 9 IUDPH 069 DocID024597 Rev 1 659/1680 682 Liquid crystal display controller (LCD) RM0351 Figure 159. 1/4 duty, 1/3 bias 9 3,1 &20 9 9 /LTXLGFU\VWDOGLVSOD\ DQGWHUPLQDOFRQQHFWLRQ 9 9 3,1 &20 &20 9 9 9 &20 9 3,1 &20 &20 9 9 9 &20 9 3,1 6(* 9 9 9 9 3,1 6(* 9 9 9 9 9 6(* 6(* 9 &206(* VHOHFWHGZDYHIRUP 9 9 9 9 9 &206(* QRQVHOHFWHGZDYHIRUP 9 9 IUDPH 069 660/1680 DocID024597 Rev 1 RM0351 Liquid crystal display controller (LCD) Figure 160. 1/8 duty, 1/4 bias /LTXLGFU\VWDOGLVSOD\ DQGWHUPLQDOFRQQHFWLRQ 9 9 3,1 &20 9 &20 9 9 &20 &20 9 &20 &20 9 3,1 &20 9 &20 9 9 &20 &20 9 9 3,1 &20 9 9 9 9 9 3,1 &20 9 9 6(* 9 9 9 3,1 6(* 9 9 9 9 9 9 9 &206(* VHOHFWHGZDYHIRUP 9 9 9 9 9 9 9 9 9 &206(* QRQVHOHFWHGZDYHIRUP 9 9 9 9 9 IUDPH 069 DocID024597 Rev 1 661/1680 682 Liquid crystal display controller (LCD) RM0351 Blink The segment driver also implements a programmable blink feature to allow some pixels to continuously switch on at a specific frequency. The blink mode can be configured by the BLINK[1:0] bits in the LCD_FCR register, making possible to blink up to 1, 2, 4, 8 or all pixels (see Section 22.6.2: LCD frame control register (LCD_FCR)). The blink frequency can be selected from eight different values using the BLINKF[2:0] bits in the LCD_FCR register. Table 126 gives examples of different blink frequencies (as a function of ck_div frequency). Table 126. Blink frequency BLINKF[2:0] bits 22.3.5 ck_div frequency (with LCDCLK frequency of 32.768 kHz) 32 Hz 64 Hz 128 Hz 256 Hz 0 0 0 4.0 Hz N/A N/A N/A 0 0 1 2.0 Hz 4.0 Hz N/A N/A 0 1 0 1.0 Hz 2.0 Hz 4.0 Hz N/A 0 1 1 0.5 Hz 1.0 Hz 2.0 Hz 4.0 Hz 1 0 0 0.25 Hz 0.5 Hz 1.0 Hz 2.0 Hz 1 0 1 N/A 0.25 Hz 0.5 Hz 1.0 Hz 1 1 0 N/A N/A 0.25 Hz 0.5 Hz 1 1 1 N/A N/A N/A 0.25 Hz Voltage generator and contrast control LCD supply source The LCD power supply source may come from either the internal step-up converter or from an external voltage applied on the VLCD pin. Internal or external voltage source can be selected using the VSEL bit in the LCD_CR register. In case of external source selected, the internal boost circuit (step-up converter) is disabled to reduce power consumption. When the step-up converter is selected as VLCD source, the VLCD value can be chosen among a wide set of values from VLCDmin to VLCDmax by means of CC[2:0] (Contrast Control) bits inside LCD_FCR (see Section 22.6.2) register. New values of VLCD takes effect every beginning of a new frame. When external power source is selected as VLCD source, the VLCD voltage must be chosen in the range of VLCDmin to VLCDmax (see datasheets). The contrast can then be controlled by programming a dead time between frames (see Deadtime on page 665). A specific software sequence must be performed to configure the LCD depending on the LCD power supply source to be used. Here we consider the LCD controller is disabled prior to the configuration sequence. 662/1680 DocID024597 Rev 1 RM0351 Liquid crystal display controller (LCD) In case the internal step-up converter is used (capacitor CEXT on VLCD pin is required): • Configure the VLCD pin as alternate function LCD in the GPIO_AFR register. • Wait for the external capacitor CEXT to be charged (CEXT connected to the VLCD pin, approximately 2 ms for CEXT = 1 μF) • Set voltage source to internal source by resetting VSEL bit in the LCD_CR register • Enable the LCD controller by setting LCDEN bit in the LCD_CR register In case of LCD external power source is used: • Set voltage source to external source by setting VSEL bit in the LCD_CR register • Configure the VLCD pin as alternate function LCD in the GPIO_AFR register • Enable the LCD controller by setting LCDEN bit in the LCD_CR register LCD intermediate voltages The LCD voltage generator generates up to three intermediate voltage levels (1/3 VLCD, 2/3 VLCD or 1/4 VLCD, 2/4 VLCD, 3/4 VLCD) between VSS and VLCD in case of 1/3 (1/4) bias and only one voltage level (1/2 VLCD) between VSS and VLCD in case of 1/2 bias. In case of 1/2 bias, one voltage level (1/2 VLCD) is generated and node b voltage is 1/2 VLCD In case of 1/3 bias, two intermediate voltage levels (1/3 VLCD, 2/3 VLCD) are generated • node a is 1/3 VLCD • node b is 2/3 VLCD In case of 1/4 bias, three intermediate voltage levels (1/4 VLCD, 1/2 VLCD and 3/4 VLCD) are generated • node a is 1/4 VLCD • node b is 1/2 VLCD • node c is 3/4 VLCD LCD drive selection 1. High drive and low drive resistive network Internal resistor networks are used to generate all intermediate voltages (see Figure 161). Actually, one with low value resistors (RLN) and one with high value resistors (RHN) which are respectively used to increase the current during transitions and to reduce power consumption in static state. The EN switch allows the following rules: If LCDEN bit in the LCD_CR register is set, the EN switch is closed. When clearing the LCDEN bit in the LCD_CR register, the EN switch is open at the end of the even frame in order to avoid a medium voltage level different from 0 considering the entire frame odd plus even. The PON[2:0] (Pulse ON duration) bits in the LCD_FCR register configure the time during which RLN is enabled (see Figure 153) through the HD (high drive) switch when the levels of the common and segment lines change. A short drive time will lead to lower power consumption, but displays with high internal resistance may need a longer drive time to achieve satisfactory contrast. DocID024597 Rev 1 663/1680 682 Liquid crystal display controller (LCD) RM0351 Figure 161. VLCD pin for 1/2 1/3 1/4 bias +' (1 9/&' %8)(1 %8)(1 QRGHF %8)(1 ELDV %8)(1 %8)(1 ELDVRUELDV QRGHE %8)(1 ELDV %8)(1 %8)(1 QRGHD ELDV %8)(1 5/1 5+1 67$7,& 966 069 1. RLN: Low value resistor network. RHN: High value resistor network. The RLN divider can be always switched on using the HD bit in the LCD_FCR configuration register (see Section 22.6.2). The HD switch follows the rules described below: • If the HD bit and the PON[2:0] bits in the LCD_FCR register are reset, then HD switch is open. • If the HD bit in the LCD_FCR register is reset and the PON[2:0] bits in the LCD_FCR are different from 00 then, the HD switch is closed during the number of pulses defined in the PON[2:0] bits. • If HD bit in the LCD_FCR register is 1 then HD switch is always closed. Buffered mode When voltage output buffers are enabled by setting BUFEN bit in the LCD_CR register, LCD driving capability is improved as buffers prevent the LCD capacitive loads from loading the resistor bridge unacceptably and interfering with its voltage generation. As a result we obtain more stable intermediate voltage levels thus improving RMS voltage applied to the LCD pixels. 664/1680 DocID024597 Rev 1 RM0351 Liquid crystal display controller (LCD) In buffer mode, intermediate voltages are generated by the high value resistor bridge RHN to reduce power consumption, the low value resistor bridge RLN is automatically disabled whatever the HD bit or PON bits configuration. Buffers can be used independently of the VLCD supply source (internal or external) but can only be enabled or disabled when LCD controller is not activated. After the LCDEN bit is activated, the RDY bit is set in the LCD_SR register to indicate that voltage levels are stable and the LCD controller can start to work. Deadtime In addition to using the CC[2:0] bits, the contrast can be controlled by programming a dead time between each frame. During the dead time the COM and SEG values are put to VSS. The DEAD[2:0] bits in the LCD_FCR register can be used to program a time of up to eight phase periods. This dead time reduces the contrast without modifying the frame rate. Figure 162. Deadtime ŽĚĚĨƌĂŵĞ ĞǀĞŶĨƌĂŵĞ ĚĞĂĚƚŝŵĞ ŽĚĚĨƌĂŵĞ ĞǀĞŶĨƌĂŵĞ 069 DocID024597 Rev 1 665/1680 682 Liquid crystal display controller (LCD) 22.3.6 RM0351 Double buffer memory Using its double buffer memory the LCD controller ensures the coherency of the displayed information without having to use interrupts to control LCD_RAM modification. The application software can access the first buffer level (LCD_RAM) through the APB interface. Once it has modified the LCD_RAM, it sets the UDR flag in the LCD_SR register. This UDR flag (update display request) requests the updated information to be moved into the second buffer level (LCD_DISPLAY). This operation is done synchronously with the frame (at the beginning of the next frame), until the update is completed, the LCD_RAM is write protected and the UDR flag stays high. Once the update is completed another flag (UDD - Update Display Done) is set and generates an interrupt if the UDDIE bit in the LCD_FCR register is set. The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one even frame. The update will not occur (UDR = 1 and UDD = 0) until the display is enabled (LCDEN = 1) 22.3.7 COM and SEG multiplexing Output pins versus duty modes The output pins consists of: • SEG[43:0] • COM[3:0] Depending on the duty configuration, the COM and SEG output pins may have different functions: • In static, 1/2, 1/3 and 1/4 duty modes there are up to 44 SEG pins and respectively 1, 2, 3 and 4 COM pins • In 1/8 duty mode (DUTY[2:0] = 100), COM[7:4] outputs are available on the SEG[43:40] pins, reducing to the number of available segments to 40. Remapping capability for small packages Additionally, it is possible to remap 4 segments by setting the MUX_SEG bit in the LCD_CR register. This is particularly useful when using smaller device types with fewer external pins. When MUX_SEG is set, output pins SEG[43:40] have the same function as SEG[31:28]. 666/1680 DocID024597 Rev 1 RM0351 Liquid crystal display controller (LCD) Summary of COM and SEG functions versus duty and remap All the possible ways of multiplexing the COM and SEG functions are described in Table 127. Figure 163 gives examples showing the signal connections to the external pins. Table 127. Remapping capability Configuration bits DUTY MUX_SEG 0/1 CSP72 LQFP64 - LQFP144 BGA132/ LQFP100 40x8 1/8 0/1 28x8 0 - 44x4 1 40x4 1/4 0 28x4 - 1 32x4 Output pin Function SEG[43:40]/SEG[31:28]/COM[7:4] COM[7:4] COM[3:0] COM[3:0] SEG[39:0] SEG[39:0] SEG[43:40]/SEG[31:28]/COM[7:4] COM[7:4] COM[3:0] COM[3:0] SEG[27:0] SEG[27:0] COM[3:0] COM[3:0] SEG[43:40]/SEG[31:28]/COM[7:4] SEG[43:40] SEG[39:0] SEG[39:0] COM[3:0] COM[3:0] SEG[43:40]/SEG[31:28]/COM[7:4] SEG[31:28] SEG[39:32] SEG[39:32] SEG[31:28] not used SEG[27:0] SEG[27:0] COM[3:0] COM[3:0] SEG[43:40]/SEG[31:28]/COM[7:4] not used SEG[27:0] SEG[27:0] COM[3:0] COM[3:0] SEG[43:40]/SEG[31:28]/COM[7:4] SEG[31:28] SEG[27:0] SEG[27:0] DocID024597 Rev 1 667/1680 682 Liquid crystal display controller (LCD) RM0351 Table 127. Remapping capability (continued) Configuration bits DUTY MUX_SEG CSP72 LQFP64 0 LQFP144 BGA132/ LQFP100 44x3 - 1 40x3 1/3 0 28x3 - 1 32x3 0 1/2 - 1 668/1680 44x2 40x2 Output pin Function COM3 not used COM[2:0] COM[2:0] SEG[43:40]/SEG[31:28]/COM[7:4] SEG[43:40] SEG[39:0] SEG[39:0] COM3 not used COM[2:0] COM[2:0] SEG[43:40]/SEG[31:28]/COM[7:4] SEG[31:28] SEG[39:32] SEG[39:32] SEG[31:28] not used SEG[27:0] SEG[27:0] COM3 not used COM[2:0] COM[2:0] SEG[43:40]/SEG[31:28]/COM[7:4] not used SEG[31:0] SEG[31:0] COM3 not used COM[2:0] COM[2:0] SEG[43:40]/SEG[31:28]/COM[7:4] SEG[31:28] SEG[27:0] SEG[27:0] COM[3:2] not used COM[1:0] COM[1:0] SEG[43:40]/SEG[31:28]/COM[7:4] SEG[43:40] SEG[39:0] SEG[39:0] COM[3:2] not used COM[1:0] COM[1:0] SEG[43:40]/SEG[31:28]/COM[7:4] SEG[31:28] SEG[39:32] SEG[39:32] SEG[31:28] not used SEG[27:0] SEG[27:0] DocID024597 Rev 1 RM0351 Liquid crystal display controller (LCD) Table 127. Remapping capability (continued) Configuration bits DUTY MUX_SEG 0 CSP72 LQFP64 LQFP144 BGA132/ LQFP100 28x2 1/2 - 1 32x2 0 44x1 - 1 40x1 STATIC 0 28x1 - 1 32x1 Output pin Function COM[3:2] not used COM[1:0] COM[1:0] SEG[43:40]/SEG[31:28]/COM[7:4] not used SEG[27:0] SEG[27:0] COM[3:2] not used COM[1:0] COM[1:0] SEG[43:40]/SEG[31:28]/COM[7:4] SEG[31:28] SEG[27:0] SEG[27:0] COM[3:1] not used COM0 COM0 SEG[43:40]/SEG[31:28]/COM[7:4] SEG[43:40] SEG[39:0] SEG[39:0] COM[3:1] not used COM0 COM0 SEG[43:40]/SEG[31:28]/COM[7:4] SEG[31:28] SEG[39:32] SEG[39:32] SEG[31:28] not used SEG[27:0] SEG[27:0] COM[3:1] not used COM0 COM0 SEG[43:40]/SEG[31:28]/COM[7:4] not used SEG[27:0] SEG[27:0] COM[3:1] not used COM0 COM0 SEG[43:40]/SEG[31:28]/COM[7:4] SEG[31:28] SEG[27:0] SEG[27:0] DocID024597 Rev 1 669/1680 682 Liquid crystal display controller (LCD) RM0351 Figure 163. SEG/COM mux feature example /&'&21752//(5 6(*>@ 6(*>@ 6(* &20 08; 6(*'5,9(5 6(*B287>@ /&'B6(*>@ 3,1 6(*B287>@ /&'B6(*>@ 3,1 6(*B287>@ /&'B6(*>@ 3,1 &20>@ &20'5,9(5 '87<DQG08;B6(* /&'&21752//(5 6(*>@ 6(*>@ 6(* &20 08; 6(*'5,9(5 &20>@ &20'5,9(5 '87<DQG08;B6(* /&'&21752//(5 6(*>@ 6(*>@ 6(*'5,9(5 6(* &20 08; &20>@ &20'5,9(5 '87< DQG08;B6(* 069 670/1680 DocID024597 Rev 1 RM0351 22.3.8 Liquid crystal display controller (LCD) Flowchart Figure 164. Flowchart example 67$57 ,1,7 (QDEOHWKH*3,2SRUWFORFNV &RQILJXUHWKH/&'*3,2SLQVDVDOWHUQDWH IXQFWLRQV &RQILJXUH/&'FRQWUROOHUDFFRUGLQJWRWKH 'LVSOD\WREHGULYHQ /RDGWKHLQLWLDOGDWDWREHGLVSOD\HGLQWR /&'B5$0DQGVHWWKH8'5ELWLQWKH/&'B65 UHJLVWHU 3URJUDPWKHGHVLUHGIUDPHUDWH 36DQG',9 ELWVLQ/&'B)&5 3URJUDPWKHFRQWUDVW &&ELWVLQ/&'B)&5 UHJLVWHU %NABLE THE DISPLAY ,#$%. BIT IN ,#$?#2 REGISTER !DJUST CONTRAST 9ES &KDQJH36',9&&321 '($'RU+'LQ/&'B)&5 .O -ODIFY DATA 9ES 5$2 9ES .O 6HW8'5ELWLQ/&'B65 .O #HANGE BLINK 0RGLI\WKH/&'B5$0 9ES &KDQJH%/,1.RU%/,1.)LQ /&'B)&5 .O $ISABLE ,#$ 9ES 'LVDEOHWKHGLVSOD\ /&'(1ELWLQ/&'B&5UHJLVWHU .O %.3 9ES (1' 069 DocID024597 Rev 1 671/1680 682 Liquid crystal display controller (LCD) 22.4 RM0351 LCD low-power modes the LCD controller can be displayed in Stop mode or can be fully disabled to reduce power consumption. Table 128. LCD behavior in low-power modes Mode 22.5 Description Stop The LCD is still active Standby The LCD is not active LCD interrupts The table below gives the list of LCD interrupt requests. Table 129. LCD interrupt requests Interrupt event Event flag Event flag/Interrupt clearing method Interrupt enable control bit Start Of Frame (SOF) SOF Write SOFC =1 SOFIE Update Display Done (UDD) UDD Write UDDC = 1 UDDIE Start of frame (SOF) The LCD start of frame interrupt is executed if the SOFIE (start of frame interrupt enable) bit is set (see Section 22.6.2: LCD frame control register (LCD_FCR)). SOF is cleared by writing the SOFC bit to 1 in the LCD_CLR register when executing the corresponding interrupt handling vector. Update display done (UDD) The LCD update display interrupt is executed if the UDDIE (update display done interrupt enable) bit is set (see Section 22.6.2: LCD frame control register (LCD_FCR)). UDD is cleared by writing the UDDC bit to 1 in the LCD_CLR register when executing the corresponding interrupt handling vector. Depending on the product implementation, all these interrupts events can either share the same interrupt vector (LCD global interrupt), or be grouped into 2 interrupt vectors (LCD SOF interrupt and LCD UDD interrupt). Refer to the Table 41: STM32L4x6 vector table for details. In order to enable the LCD interrupts, the following sequence is required: 672/1680 1. Configure and enable the LCD IRQ channel in the NVIC 2. Configure the LCD to generate interrupts DocID024597 Rev 1 RM0351 Liquid crystal display controller (LCD) 22.6 LCD registers The peripheral registers have to be accessed by words (32-bit). 22.6.1 LCD control register (LCD_CR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUFEN MUX_ SEG VSEL LCDEN rw rw rw rw Res. Res. Res. Res. Res. Res. Res. BIAS[1:0] rw rw DUTY[2:0] rw rw rw Bits 31:9 Reserved, must be kept at reset value Bit 8 BUFEN: Voltage output buffer enable This bit is used to enable/disable the voltage output buffer for higher driving capability. 0: Output buffer disabled 1: Output buffer enabled Bit 7 MUX_SEG: Mux segment enable This bit is used to enable SEG pin remapping. Four SEG pins can be multiplexed with SEG[31:28]. See Section 22.3.7. 0: SEG pin multiplexing disabled 1: SEG[31:28] are multiplexed with SEG[43:40] Bits 6:5 BIAS[1:0]: Bias selector These bits determine the bias used. Value 11 is forbidden. 00: Bias 1/4 01: Bias 1/2 10: Bias 1/3 11: Reserved DocID024597 Rev 1 673/1680 682 Liquid crystal display controller (LCD) RM0351 Bits 4:2 DUTY[2:0]: Duty selection These bits determine the duty cycle. Values 101, 110 and 111 are forbidden. 000: Static duty 001: 1/2 duty 010: 1/3 duty 011: 1/4 duty 100: 1/8 duty 101: Reserved 110: Reserved 111: Reserved Bit 1 VSEL: Voltage source selection The VSEL bit determines the voltage source for the LCD. 0: Internal source (voltage step-up converter) 1: External source (VLCD pin) Bit 0 LCDEN: LCD controller enable This bit is set by software to enable the LCD Controller/Driver. It is cleared by software to turn off the LCD at the beginning of the next frame. When the LCD is disabled all COM and SEG pins are driven to VSS. 0: LCD Controller disabled 1: LCD Controller enabled Note: The VSEL, MUX_SEG, BIAS, DUTY and BUFEN bits are write-protected when the LCD is enabled (ENS bit in LCD_SR to 1). 22.6.2 LCD frame control register (LCD_FCR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 Res. Res. Res. Res. Res. Res. 15 14 13 12 BLINKF[2:0] rw 674/1680 rw 11 10 25 rw rw 23 22 20 19 18 DIV[3:0] 17 16 BLINK[1:0] rw rw rw rw rw rw rw rw rw rw 9 8 7 6 5 4 3 2 1 0 UDDIE Res. SOFIE HD rw rw DEAD[2:0] rw 21 PS[3:0] CC[2:0] rw 24 rw rw PON[2:0] rw rw DocID024597 Rev 1 rw rw rw RM0351 Liquid crystal display controller (LCD) Bits 31:26 Reserved, must be kept at reset value Bits 25:22 PS[3:0]: PS 16-bit prescaler These bits are written by software to define the division factor of the PS 16-bit prescaler. ck_ps = LCDCLK/(2). See Section 22.3.2. 0000: ck_ps = LCDCLK 0001: ck_ps = LCDCLK/2 0002: ck_ps = LCDCLK/4 ... 1111:ck_ps = LCDCLK/32768 Bits 21:18 DIV[3:0]: DIV clock divider These bits are written by software to define the division factor of the DIV divider. See Section 22.3.2. 0000: ck_div = ck_ps/16 0001: ck_div = ck_ps/17 0002: ck_div = ck_ps/18 ... 1111:ck_div = ck_ps/31 Bits 17:16 BLINK[1:0]: Blink mode selection 00: Blink disabled 01: Blink enabled on SEG[0], COM[0] (1 pixel) 10: Blink enabled on SEG[0], all COMs (up to 8 pixels depending on the programmed duty) 11: Blink enabled on all SEGs and all COMs (all pixels) Bits 15:13 BLINKF[2:0]: Blink frequency selection 000: fLCD/8 001: fLCD/16 010: fLCD/32 011: fLCD/64 100: fLCD/128 101: fLCD/256 110: fLCD/512 111: fLCD/1024 Bits 12:10 CC[2:0]: Contrast control These bits specify one of the VLCD maximum voltages (independent of VDD). It ranges from 2.60 V to 3.51V. 000: VLCD0 001: VLCD1 010: VLCD2 011: VLCD3 100: VLCD4 101: VLCD5 110: VLCD6 111: VLCD7 Refer to the product datasheet for the VLCDx values. DocID024597 Rev 1 675/1680 682 Liquid crystal display controller (LCD) RM0351 Bits 9:7 DEAD[2:0]: Dead time duration These bits are written by software to configure the length of the dead time between frames. During the dead time the COM and SEG voltage levels are held at 0 V to reduce the contrast without modifying the frame rate. 000: No dead time 001: 1 phase period dead time 010: 2 phase period dead time ...... 111: 7 phase period dead time Bits 6:4 PON[2:0]: Pulse ON duration These bits are written by software to define the pulse duration in terms of ck_ps pulses. A short pulse will lead to lower power consumption, but displays with high internal resistance may need a longer pulse to achieve satisfactory contrast. Note that the pulse will never be longer than one half prescaled LCD clock period. 000: 0 001: 1/ck_ps 010: 2/ck_ps 011: 3/ck_ps 100: 4/ck_ps 101: 5/ck_ps 110: 6/ck_ps 111: 7/ck_ps PON duration example with LCDCLK = 32.768 kHz and PS=0x03: 000: 0 µs 001: 244 µs 010: 488 µs 011: 782 µs 100: 976 µs 101: 1.22 ms 110: 1.46 ms 111: 1.71 ms Bit 3 UDDIE: Update display done interrupt enable This bit is set and cleared by software. 0: LCD Update Display Done interrupt disabled 1: LCD Update Display Done interrupt enabled Bit 2 Reserved, must be kept at reset value Bit 1 SOFIE: Start of frame interrupt enable This bit is set and cleared by software. 0: LCD Start of Frame interrupt disabled 1: LCD Start of Frame interrupt enabled Bit 0 HD: High drive enable This bit is written by software to enable a low resistance divider. Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast. This bit is useful in this case if some additional power consumption can be tolerated. 0: Permanent high drive disabled 1: Permanent high drive enabled. When HD=1, then the PON bits have to be programmed to 001. 676/1680 DocID024597 Rev 1 RM0351 Note: Liquid crystal display controller (LCD) The data in this register can be updated any time, however the new values are applied only at the beginning of the next frame (except for UDDIE, SOFIE that affect the device behavior immediately). The new value of CC[2:0] bits is also applied immediately but its effect on device is delayed at the beginning of next frame by the voltage generator. Reading this register obtains the last value written in the register and not the configuration used to display the current frame. Note: When BUFEN bit is set in the LCD_CR register, low resistor divider network is automatically disabled whatever the HD or PON[2:0] bits configuration. DocID024597 Rev 1 677/1680 682 Liquid crystal display controller (LCD) 22.6.3 RM0351 LCD status register (LCD_SR) Address offset: 0x08 Reset value: 0x0000 0020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FCRSF RDY UDD UDR SOF ENS r r r rs r r Bits 31:6 Reserved, must be kept at reset value Bit 5 FCRSF: LCD Frame Control Register Synchronization flag This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK domain. It is cleared by hardware when writing to the LCD_FCR register. 0: LCD Frame Control Register not yet synchronized 1: LCD Frame Control Register synchronized Bit 4 RDY: Ready flag This bit is set and cleared by hardware. It indicates the status of the step-up converter. 0: Not ready 1: Step-up converter is enabled and ready to provide the correct voltage. Bit 3 UDD: Update Display Done This bit is set by hardware. It is cleared by writing 1 to the UDDC bit in the LCD_CLR register. The bit set has priority over the clear. 0: No event 1: Update Display Request done. A UDD interrupt is generated if the UDDIE bit in the LCD_FCR register is set. Note: If the device is in Stop mode (PCLK not provided) UDD will not generate an interrupt even if UDDIE = 1. If the display is not enabled the UDD interrupt will never occur. 678/1680 DocID024597 Rev 1 RM0351 Liquid crystal display controller (LCD) Bit 2 UDR: Update display request Each time software modifies the LCD_RAM it must set the UDR bit to transfer the updated data to the second level buffer. The UDR bit stays set until the end of the update and during this time the LCD_RAM is write protected. 0: No effect 1: Update Display request Note: When the display is disabled, the update is performed for all LCD_DISPLAY locations. When the display is enabled, the update is performed only for locations for which commons are active (depending on DUTY). For example if DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated. Note: Writing 0 on this bit or writing 1 when it is already 1 has no effect. This bit can be cleared by hardware only. It can be cleared only when LCDEN = 1 Bit 1 SOF: Start of frame flag This bit is set by hardware at the beginning of a new frame, at the same time as the display data is updated. It is cleared by writing a 1 to the SOFC bit in the LCD_CLR register. The bit clear has priority over the set. 0: No event 1: Start of Frame event occurred. An LCD Start of Frame Interrupt is generated if the SOFIE bit is set. ENS: LCD enabled status This bit is set and cleared by hardware. It indicates the LCD controller status. 0: LCD Controller disabled. 1: LCD Controller enabled Note: The ENS bit is set immediately when the LCDEN bit in the LCD_CR goes from 0 to 1. On deactivation it reflects the real status of LCD so it becomes 0 at the end of the last displayed frame. DocID024597 Rev 1 679/1680 682 Liquid crystal display controller (LCD) 22.6.4 RM0351 LCD clear register (LCD_CLR) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UDDC Res. SOFC Res. w w Bits 31:4 Reserved, must be kept at reset value Bit 3 UDDC: Update display done clear This bit is written by software to clear the UDD flag in the LCD_SR register. 0: No effect 1: Clear UDD flag Bit 2 Reserved, must be kept at reset value Bit 1 SOFC: Start of frame flag clear This bit is written by software to clear the SOF flag in the LCD_SR register. 0: No effect 1: Clear SOF flag Bit 0 Reserved, must be kept at reset value 22.6.5 LCD display memory (LCD_RAM) Address offset: 0x14 to 0x50 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SEGMENT_DATA[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw SEGMENT_DATA[15:0] rw rw Bits 31:0 SEGMENT_DATA[31:0] Each bit corresponds to one pixel of the LCD display. 0: Pixel inactive 1: Pixel active 680/1680 DocID024597 Rev 1 0x0C 0x14 0x28 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01 S00 LCD_CLR LCD_RAM (COM0) 0x18 0x1C LCD_RAM (COM1) 0x20 0x24 LCD_RAM (COM2) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FCRSF RDY UDD UDR SOF ENS LCD_SR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UDDC Res. SOFC Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 0x08 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01 S00 0x04 Res. Res. Res. Res. Res. Res. LCD_FCR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 PS[3:0] DIV[3:0] Reset value Reset value DocID024597 Rev 1 BLINKF[2:0] BLINK[1:0] Reset value CC [2:0] DEAD [2:0] PON [2:0] UDDIE Res. SOFIE HD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LCD_CR BIAS[1:0] Register Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BUFEN. MUX_SEG. 0x00 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01 S00 DUTY [2:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSEL LCDEN 22.6.6 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 Offset RM0351 Liquid crystal display controller (LCD) LCD register map The following table summarizes the LCD registers. Table 130. LCD register map and reset values 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 681/1680 682 0x4C S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01 S00 0x44 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01 S00 0x3C S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01 S00 0x34 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01 S00 LCD_RAM (COM4) 0x38 LCD_RAM (COM5) 0x40 LCD_RAM (COM6) 0x48 LCD_RAM (COM7) 0x50 682/1680 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 0x30 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. S39 S38 S37 S36 S35 S34 S33 S32 LCD_RAM (COM3) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01 S00 0x2C Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. S39 S38 S37 S36 S35 S34 S33 S32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. S39 S38 S37 S36 S35 S34 S33 S32 Offset Liquid crystal display controller (LCD) RM0351 Table 130. LCD register map and reset values (continued) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 68 for the Register boundary addresses table. DocID024597 Rev 1 RM0351 Touch sensing controller (TSC) 23 Touch sensing controller (TSC) 23.1 Introduction The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (for example glass, plastic). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application. 23.2 TSC main features The touch sensing controller has the following main features: Note: • Proven and robust surface charge transfer acquisition principle • Supports up to 24 capacitive sensing channels • Up to 8 capacitive sensing channels can be acquired in parallel offering a very good response time • Spread spectrum feature to improve system robustness in noisy environments • full hardware management of the charge transfer acquisition sequence • Programmable charge transfer frequency • Programmable sampling capacitor I/O pin • Programmable channel I/O pin • Programmable max count value to avoid long acquisition when a channel is faulty • Dedicated end of acquisition and max count error flags with interrupt capability • One sampling capacitor for up to 3 capacitive sensing channels to reduce the system components • Compatible with proximity, touchkey, linear and rotary touch sensor implementation • Designed to operate with STMTouch touch sensing firmware library The number of capacitive sensing channels is dependent on the size of the packages and subject to IO availability. DocID024597 Rev 1 683/1680 702 Touch sensing controller (TSC) RM0351 23.3 TSC functional description 23.3.1 TSC block diagram The block diagram of the touch sensing controller is shown in Figure 165: TSC block diagram. Figure 165. TSC block diagram 39.# 0ULSE GENERATOR F(#,+ '?)/ #LOCK PRESCALERS '?)/ '?)/ 3PREAD SPECTRUM '?)/ '?)/ '?)/ 'ROUP COUNTERS )/ CONTROL LOGIC '?)/ '?)/ 43#?)/'#2 43#?)/'#2 'X?)/ 'X?)/ 43#?)/'X#2 'X?)/ 'X?)/ -36 23.3.2 Surface charge transfer acquisition overview The surface charge transfer acquisition is a proven, robust and efficient way to measure a capacitance. It uses a minimum number of external components to operate with a single ended electrode type. This acquisition is designed around an analog I/O group which is composed of four GPIOs (see Figure 166). Several analog I/O groups are available to allow the acquisition of several capacitive sensing channels simultaneously and to support a larger number of capacitive sensing channels. Within a same analog I/O group, the acquisition of the capacitive sensing channels is sequential. One of the GPIOs is dedicated to the sampling capacitor CS. Only one sampling capacitor I/O per analog I/O group must be enabled at a time. 684/1680 DocID024597 Rev 1 RM0351 Touch sensing controller (TSC) The remaining GPIOs are dedicated to the electrodes and are commonly called channels. For some specific needs (such as proximity detection), it is possible to simultaneously enable more than one channel per analog I/O group. Figure 166. Surface charge transfer analog I/O group structure %LECTRODE 23 '?)/ !NALOG )/ GROUP #8 '?)/ #3 %LECTRODE 23 '?)/ 23 '?)/ #8 %LECTRODE #8 -36 Note: Gx_IOy where x is the analog I/O group number and y the GPIO number within the selected group. The surface charge transfer acquisition principle consists of charging an electrode capacitance (CX) and transferring a part of the accumulated charge into a sampling capacitor (CS). This sequence is repeated until the voltage across CS reaches a given threshold (VIH in our case). The number of charge transfers required to reach the threshold is a direct representation of the size of the electrode capacitance. The Table 131 details the charge transfer acquisition sequence of the capacitive sensing channel 1. States 3 to 7 are repeated until the voltage across CS reaches the given threshold. The same sequence applies to the acquisition of the other channels. The electrode serial resistor RS improves the ESD immunity of the solution. DocID024597 Rev 1 685/1680 702 Touch sensing controller (TSC) RM0351 Table 131. Acquisition sequence summary State G1_IO1 (electrode) G1_IO2 (sampling) #1 Input floating with analog switch closed Output opendrain low with analog switch closed #2 #3 G1_IO4 (electrode) State description Input floating with analog switch Discharge all CX and CS closed Input floating Output pushpull high #4 #5 G1_IO3 (electrode) Dead time Input floating Charge CX1 Input floating Input floating with analog switch closed Dead time Input floating Charge transfer from CX1 to CS #6 Input floating Dead time #7 Input floating Measure CS voltage The voltage variation over the time on the sampling capacitor CS is detailed below: Figure 167. Sampling capacitor voltage variation 6#3 6$$ 4HRESHOLD 6)( T "URST DURATION -36 23.3.3 Reset and clocks The TSC clock source is the AHB clock (HCLK). Two programmable prescalers are used to generate the pulse generator and the spread spectrum internal clocks: • The pulse generator clock (PGCLK) is defined using the PGPSC[2:0] bits of the TSC_CR register • The spread spectrum clock (SSCLK) is defined using the SSPSC bit of the TSC_CR register The Reset and Clock Controller (RCC) provides dedicated bits to enable the touch sensing controller clock and to reset this peripheral. For more information, please refer to Section 8: Reset and clock control (RCC). 686/1680 DocID024597 Rev 1 RM0351 Charge transfer acquisition sequence An example of a charge transfer acquisition sequence is detailed in Figure 168. Figure 168. Charge transfer acquisition sequence #HARGE TRANSFER FREQUENCY #,+?!(" #8 (I: $EAD TIME STATE #3 READING STATE 0ULSE LOW STATE CHARGE TRANSFER FROM #8 TO #3 $EAD TIME STATE 0ULSE HIGH STATE CHARGE OF #8 #3 READING STATE $ISCHARGE #8 AND #3 $EAD TIME STATE 3TATE $EAD TIME STATE 3PREAD 3PECTRUM STATE #3 (I: $EAD TIME STATE 23.3.4 Touch sensing controller (TSC) T -36 For higher flexibility, the charge transfer frequency is fully configurable. Both the pulse high state (charge of CX) and the pulse low state (transfer of charge from CX to CS) duration can be defined using the CTPH[3:0] and CTPL[3:0] bits in the TSC_CR register. The standard range for the pulse high and low states duration is 500 ns to 2 µs. To ensure a correct measurement of the electrode capacitance, the pulse high state duration must be set to ensure that CX is always fully charged. A dead time where both the sampling capacitor I/O and the channel I/O are in input floating state is inserted between the pulse high and low states to ensure an optimum charge transfer acquisition sequence. This state duration is 1 periods of HCLK. At the end of the pulse high state and if the spread spectrum feature is enabled, a variable number of periods of the SSCLK clock are added. The reading of the sampling capacitor I/O, to determine if the voltage across CS has reached the given threshold, is performed at the end of the pulse low state and its duration is one period of HCLK. DocID024597 Rev 1 687/1680 702 Touch sensing controller (TSC) 23.3.5 RM0351 Spread spectrum feature The spread spectrum feature allows to generate a variation of the charge transfer frequency. This is done to improve the robustness of the charge transfer acquisition in noisy environments and also to reduce the induced emission. The maximum frequency variation is in the range of 10% to 50% of the nominal charge transfer period. For instance, for a nominal charge transfer frequency of 250 kHz (4 µs), the typical spread spectrum deviation is 10% (400 ns) which leads to a minimum charge transfer frequency of ~227 kHz. In practice, the spread spectrum consists of adding a variable number of SSCLK periods to the pulse high state using the principle shown below: Figure 169. Spread spectrum variation principle $EVIATION VALUE 33$ N N N .UMBER OF PULSES -36 The table below details the maximum frequency deviation with different HCLK settings: Table 132. Spread spectrum deviation versus AHB clock frequency fHCLK Spread spectrum step Maximum spread spectrum deviation 24 MHz 41.6 ns 10666.6 ns 48 MHz 20.8 ns 5333.3 ns The spread spectrum feature can be disabled/enabled using the SSE bit in the TSC_CR register. The frequency deviation is also configurable to accommodate the device HCLK clock frequency and the selected charge transfer frequency through the SSPSC and SSD[6:0] bits in the TSC_CR register. 23.3.6 Max count error The max count error prevents long acquisition times resulting from a faulty capacitive sensing channel. It consists of specifying a maximum count value for the analog I/O group counters. This maximum count value is specified using the MCV[2:0] bits in the TSC_CR register. As soon as an acquisition group counter reaches this maximum value, the ongoing acquisition is stopped and the end of acquisition (EOAF bit) and max count error (MCEF bit) flags are both set. An interrupt can also be generated if the corresponding end of acquisition (EOAIE bit) or/and max count error (MCEIE bit) interrupt enable bits are set. 688/1680 DocID024597 Rev 1 RM0351 23.3.7 Touch sensing controller (TSC) Sampling capacitor I/O and channel I/O mode selection To allow the GPIOs to be controlled by the touch sensing controller, the corresponding alternate function must be enabled through the standard GPIO registers and the GPIOxAFR registers. The GPIOs modes controlled by the TSC are defined using the TSC_IOSCR and TSC_IOCCR register. When there is no ongoing acquisition, all the I/Os controlled by the touch sensing controller are in default state. While an acquisition is ongoing, only unused I/Os (neither defined as sampling capacitor I/O nor as channel I/O) are in default state. The IODEF bit in the TSC_CR register defines the configuration of the I/Os which are in default state. The table below summarizes the configuration of the I/O depending on its mode. Table 133. I/O state depending on its mode and IODEF bit value IODEF bit Acquisition status Unused I/O mode Electrode I/O mode Sampling capacitor I/O mode 0 (output push-pull low) No Output push-pull low Output push-pull low Output push-pull low 0 (output push-pull low) ongoing Output push-pull low - - 1 (input floating) No Input floating Input floating Input floating 1 (input floating) ongoing Input floating - - Unused I/O mode An unused I/O corresponds to a GPIO controlled by the TSC peripheral but not defined as an electrode I/O nor as a sampling capacitor I/O. Sampling capacitor I/O mode To allow the control of the sampling capacitor I/O by the TSC peripheral, the corresponding GPIO must be first set to alternate output open drain mode and then the corresponding Gx_IOy bit in the TSC_IOSCR register must be set. Only one sampling capacitor per analog I/O group must be enabled at a time. Channel I/O mode To allow the control of the channel I/O by the TSC peripheral, the corresponding GPIO must be first set to alternate output push-pull mode and the corresponding Gx_IOy bit in the TSC_IOCCR register must be set. For proximity detection where a higher equivalent electrode surface is required or to speedup the acquisition process, it is possible to enable and simultaneously acquire several channels belonging to the same analog I/O group. DocID024597 Rev 1 689/1680 702 Touch sensing controller (TSC) RM0351 Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR or TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. 23.3.8 Acquisition mode The touch sensing controller offers two acquisition modes: • Normal acquisition mode: the acquisition starts as soon as the START bit in the TSC_CR register is set. • Synchronized acquisition mode: the acquisition is enabled by setting the START bit in the TSC_CR register but only starts upon the detection of a falling edge or a rising edge and high level on the SYNC input pin. This mode is useful for synchronizing the capacitive sensing channels acquisition with an external signal without additional CPU load. The GxE bits in the TSC_IOGCSR registers specify which analog I/O groups are enabled (corresponding counter is counting). The CS voltage of a disabled analog I/O group is not monitored and this group does not participate in the triggering of the end of acquisition flag. However, if the disabled analog I/O group contains some channels, they will be pulsed. When the CS voltage of an enabled analog I/O group reaches the given threshold, the corresponding GxS bit of the TSC_IOGCSR register is set. When the acquisition of all enabled analog I/O groups is complete (all GxS bits of all enabled analog I/O groups are set), the EOAF flag in the TSC_ISR register is set. An interrupt request is generated if the EOAIE bit in the TSC_IER register is set. In the case that a max count error is detected, the ongoing acquisition is stopped and both the EOAF and MCEF flags in the TSC_ISR register are set. Interrupt requests can be generated for both events if the corresponding bits (EOAIE and MCEIE bits of the TSCIER register) are set. Note that when the max count error is detected the remaining GxS bits in the enabled analog I/O groups are not set. To clear the interrupt flags, the corresponding EOAIC and MCEIC bits in the TSC_ICR register must be set. The analog I/O group counters are cleared when a new acquisition is started. They are updated with the number of charge transfer cycles generated on the corresponding channel(s) upon the completion of the acquisition. 23.3.9 I/O hysteresis and analog switch control In order to offer a higher flexibility, the touch sensing controller also allows to take the control of the Schmitt trigger hysteresis and analog switch of each Gx_IOy. This control is available whatever the I/O control mode is (controlled by standard GPIO registers or other peripherals) assuming that the touch sensing controller is enabled. This may be useful to perform a different acquisition sequence or for other purposes. In order to improve the system immunity, the Schmitt trigger hysteresis of the GPIOs controlled by the TSC must be disabled by resetting the corresponding Gx_IOy bit in the TSC_IOHCR register. 690/1680 DocID024597 Rev 1 RM0351 23.3.10 Touch sensing controller (TSC) Capacitive sensing GPIOs The table below provides an overview of the capacitive sensing GPIOs. Table 134. Capacitive sensing GPIOs available on STM32L4x6 devices Group 1 2 3 4 23.4 Capacitive sensing signal name Pin name Capacitive sensing signal name Pin name TSC_G1_IO1 PB12 TSC_G5_IO1 PE10 TSG_G1_IO2 PB13 TSG_G5_IO2 PE11 TSG_G1_IO3 PB14 TSG_G5_IO3 PE12 TSG_G1_IO4 PB15 TSG_G5_IO4 PE13 TSC_G2_IO1 PB4 TSC_G6_IO1 PD10 TSG_G2_IO2 PB5 TSG_G6_IO2 PD11 TSG_G2_IO3 PB6 TSG_G6_IO3 PD12 TSG_G2_IO4 PB7 TSG_G6_IO4 PD13 TSC_G3_IO1 PA15 TSC_G7_IO1 PE2 TSG_G3_IO2 PC10 TSG_G7_IO2 PE3 TSG_G3_IO3 PC11 TSG_G7_IO3 PE4 TSG_G3_IO4 PC12 TSG_G7_IO4 PE5 TSC_G4_IO1 PC6 TSC_G8_IO1 PF14 TSG_G4_IO2 PC7 TSG_G8_IO2 PF15 TSG_G4_IO3 PC8 TSG_G8_IO3 PG0 TSG_G4_IO4 PC9 TSG_G8_IO4 PG1 Group 5 6 7 8 TSC low-power modes Table 135. Effect of low-power modes on TSC Mode Sleep Description No effect TSC interrupts cause the device to exit Sleep mode. Stop TSC registers are frozen Standby The TSC stops its operation until the Stop or Standby mode is exited. DocID024597 Rev 1 691/1680 702 Touch sensing controller (TSC) 23.5 RM0351 TSC interrupts Table 136. Interrupt control bits Interrupt event Enable control bit Event flag Clear flag bit Exit the Sleep mode Exit the Stop mode Exit the Standby mode End of acquisition EOAIE EOAIF EOAIC yes no no Max count error MCEIE MCEIF MCEIC yes no no 692/1680 DocID024597 Rev 1 RM0351 Touch sensing controller (TSC) 23.6 TSC registers Refer to Section 1.1 on page 61 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). 23.6.1 TSC control register (TSC_CR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 CTPH[3:0] 26 25 24 23 22 21 CTPL[3:0] 20 rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 rw PGPSC[2:0] rw rw Res. rw Res. 18 17 16 SSD[6:0] rw SSPSC 19 Res. Res. MCV[2:0] rw rw rw SSE rw rw rw rw 4 3 2 1 0 IODEF SYNC POL AM START TSCE rw rw rw rw rw Bits 31:28 CTPH[3:0]: Charge transfer pulse high These bits are set and cleared by software. They define the duration of the high state of the charge transfer pulse (charge of CX). 0000: 1x tPGCLK 0001: 2x tPGCLK ... 1111: 16x tPGCLK Note: These bits must not be modified when an acquisition is ongoing. Bits 27:24 CTPL[3:0]: Charge transfer pulse low These bits are set and cleared by software. They define the duration of the low state of the charge transfer pulse (transfer of charge from CX to CS). 0000: 1x tPGCLK 0001: 2x tPGCLK ... 1111: 16x tPGCLK Note: These bits must not be modified when an acquisition is ongoing. Bits 23:17 SSD[6:0]: Spread spectrum deviation These bits are set and cleared by software. They define the spread spectrum deviation which consists in adding a variable number of periods of the SSCLK clock to the charge transfer pulse high state. 0000000: 1x tSSCLK 0000001: 2x tSSCLK ... 1111111: 128x tSSCLK Note: These bits must not be modified when an acquisition is ongoing. Bit 16 SSE: Spread spectrum enable This bit is set and cleared by software to enable/disable the spread spectrum feature. 0: Spread spectrum disabled 1: Spread spectrum enabled Note: This bit must not be modified when an acquisition is ongoing. DocID024597 Rev 1 693/1680 702 Touch sensing controller (TSC) RM0351 Bit 15 SSPSC: Spread spectrum prescaler This bit is set and cleared by software. It selects the AHB clock divider used to generate the spread spectrum clock (SSCLK). 0: fHCLK 1: fHCLK /2 Note: This bit must not be modified when an acquisition is ongoing. Bits 14:12 PGPSC[2:0]: pulse generator prescaler These bits are set and cleared by software.They select the AHB clock divider used to generate the pulse generator clock (PGCLK). 000: fHCLK 001: fHCLK /2 010: fHCLK /4 011: fHCLK /8 100: fHCLK /16 101: fHCLK /32 110: fHCLK /64 111: fHCLK /128 Note: These bits must not be modified when an acquisition is ongoing. Bits 11:8 Reserved, must be kept at reset value. Bits 7:5 MCV[2:0]: Max count value These bits are set and cleared by software. They define the maximum number of charge transfer pulses that can be generated before a max count error is generated. 000: 255 001: 511 010: 1023 011: 2047 100: 4095 101: 8191 110: 16383 111: reserved Note: These bits must not be modified when an acquisition is ongoing. Bit 4 IODEF: I/O Default mode This bit is set and cleared by software. It defines the configuration of all the TSC I/Os when there is no ongoing acquisition. When there is an ongoing acquisition, it defines the configuration of all unused I/Os (not defined as sampling capacitor I/O or as channel I/O). 0: I/Os are forced to output push-pull low 1: I/Os are in input floating Note: This bit must not be modified when an acquisition is ongoing. Bit 3 SYNCPOL: Synchronization pin polarity This bit is set and cleared by software to select the polarity of the synchronization input pin. 0: Falling edge only 1: Rising edge and high level 694/1680 DocID024597 Rev 1 RM0351 Touch sensing controller (TSC) Bit 2 AM: Acquisition mode This bit is set and cleared by software to select the acquisition mode. 0: Normal acquisition mode (acquisition starts as soon as START bit is set) 1: Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) Note: This bit must not be modified when an acquisition is ongoing. Bit 1 START: Start a new acquisition This bit is set by software to start a new acquisition. It is cleared by hardware as soon as the acquisition is complete or by software to cancel the ongoing acquisition. 0: Acquisition not started 1: Start a new acquisition Bit 0 TSCE: Touch sensing controller enable This bit is set and cleared by software to enable/disable the touch sensing controller. 0: Touch sensing controller disabled 1: Touch sensing controller enabled Note: When the touch sensing controller is disabled, TSC registers settings have no effect. 23.6.2 TSC interrupt enable register (TSC_IER) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MCEIE EOAIE rw rw Bits 31:2 Reserved, must be kept at reset value. Bit 1 MCEIE: Max count error interrupt enable This bit is set and cleared by software to enable/disable the max count error interrupt. 0: Max count error interrupt disabled 1: Max count error interrupt enabled Bit 0 EOAIE: End of acquisition interrupt enable This bit is set and cleared by software to enable/disable the end of acquisition interrupt. 0: End of acquisition interrupt disabled 1: End of acquisition interrupt enabled DocID024597 Rev 1 695/1680 702 Touch sensing controller (TSC) 23.6.3 RM0351 TSC interrupt clear register (TSC_ICR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MCEIC EOAIC rw rw Bits 31:2 Reserved, must be kept at reset value. Bit 1 MCEIC: Max count error interrupt clear This bit is set by software to clear the max count error flag and it is cleared by hardware when the flag is reset. Writing a ‘0’ has no effect. 0: No effect 1: Clears the corresponding MCEF of the TSC_ISR register Bit 0 EOAIC: End of acquisition interrupt clear This bit is set by software to clear the end of acquisition flag and it is cleared by hardware when the flag is reset. Writing a ‘0’ has no effect. 0: No effect 1: Clears the corresponding EOAF of the TSC_ISR register 696/1680 DocID024597 Rev 1 RM0351 Touch sensing controller (TSC) 23.6.4 TSC interrupt status register (TSC_ISR) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MCEF EOAF rw rw Bits 31:2 Reserved, must be kept at reset value. Bit 1 MCEF: Max count error flag This bit is set by hardware as soon as an analog I/O group counter reaches the max count value specified. It is cleared by software writing 1 to the bit MCEIC of the TSC_ICR register. 0: No max count error (MCE) detected 1: Max count error (MCE) detected Bit 0 EOAF: End of acquisition flag This bit is set by hardware when the acquisition of all enabled group is complete (all GxS bits of all enabled analog I/O groups are set or when a max count error is detected). It is cleared by software writing 1 to the bit EOAIC of the TSC_ICR register. 0: Acquisition is ongoing or not started 1: Acquisition is complete 23.6.5 TSC I/O hysteresis control register (TSC_IOHCR) Address offset: 0x10 Reset value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 Gx_IOy: Gx_IOy Schmitt trigger hysteresis mode These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger hysteresis. 0: Gx_IOy Schmitt trigger hysteresis disabled 1: Gx_IOy Schmitt trigger hysteresis enabled Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is (even if controlled by standard GPIO registers). DocID024597 Rev 1 697/1680 702 Touch sensing controller (TSC) 23.6.6 RM0351 TSC I/O analog switch control register (TSC_IOASCR) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 Gx_IOy: Gx_IOy analog switch enable These bits are set and cleared by software to enable/disable the Gx_IOy analog switch. 0: Gx_IOy analog switch disabled (opened) 1: Gx_IOy analog switch enabled (closed) Note: These bits control the I/O analog switch whatever the I/O control mode is (even if controlled by standard GPIO registers). 23.6.7 TSC I/O sampling control register (TSC_IOSCR) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 Gx_IOy: Gx_IOy sampling mode These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor I/O. Only one I/O per analog I/O group must be defined as sampling capacitor. 0: Gx_IOy unused 1: Gx_IOy used as sampling capacitor Note: These bits must not be modified when an acquisition is ongoing. During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. 698/1680 DocID024597 Rev 1 RM0351 Touch sensing controller (TSC) 23.6.8 TSC I/O channel control register (TSC_IOCCRTSC_IOCCR) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 Gx_IOy: Gx_IOy channel mode These bits are set and cleared by software to configure the Gx_IOy as a channel I/O. 0: Gx_IOy unused 1: Gx_IOy used as channel Note: These bits must not be modified when an acquisition is ongoing. During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. 23.6.9 TSC I/O group control status register (TSC_IOGCSR) Address offset: 0x30 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. G8S G7S G6S G5S G4S G3S G2S G1S r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res.. Res. Res. Res. Res. Res. Res. Res. G8E G7E G6E G5E G4E G3E G2E G1E rw rw rw rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. DocID024597 Rev 1 699/1680 702 Touch sensing controller (TSC) RM0351 Bits 23:16 GxS: Analog I/O group x status These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. 0: Acquisition on analog I/O group x is ongoing or not started 1: Acquisition on analog I/O group x is complete Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O groups are not set. Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 GxE: Analog I/O group x enable These bits are set and cleared by software to enable/disable the acquisition (counter is counting) on the corresponding analog I/O group x. 0: Acquisition on analog I/O group x disabled 1: Acquisition on analog I/O group x enabled 23.6.10 TSC I/O group x counter register (TSC_IOGxCR) (x = 1..8) Address offset: 0x30 + 0x04 x Analog I/O group number Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. r r r r r r CNT[13:0] r r r r r r r r Bits 31:14 Reserved, must be kept at reset value. Bits 13:0 CNT[13:0]: Counter value These bits represent the number of charge transfer cycles generated on the analog I/O group x to complete its acquisition (voltage across CS has reached the threshold). 23.6.11 TSC register map Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DocID024597 Rev 1 Res. TSCE TSC_IER 0 0 0 0 0 EOAIE 0 AM 0 START 0 Res. 0 MCEIE 0 IODEF 0 SYNCPOL 0 0 0 0 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 MCV [2:0] Res. 0 Res. 0 Res. 0 Res. 0 SSD[6:0] Res. 0 CTPL[3:0] Res. 0 CTPH[3:0] Res. 0 TSC_CR Reset value 700/1680 PGPSC[2:0] SSE SSPSC 0 Res. 0x0004 Reset value Res. 0x0000 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 137. TSC register map and reset values 0x0044 TSC_IOG5CR 0 0 0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value Reset value Reset value Reset value Reset value DocID024597 Rev 1 CNT[13:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT[13:0] 0 CNT[13:0] 0 CNT[13:0] 0 CNT[13:0] 0 G1E 0 G2E 0 G3E 0 G4E 0 G5E 0 G6E G1_IO1 0 G1_IO2 0 G1_IO3 0 G1_IO4 0 G2_IO1 0 G2_IO2 0 G2_IO3 0 G7E 0 G2_IO4 0 G8E 0 G3_IO1 0 Res. Reset value G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 0 G3_IO2 0 Res. 0 G3_IO3 0 G3_IO3 0 Res. 0 G3_IO4 0 G3_IO4 0 Res. 0 G4_IO1 0 G4_IO1 0 Res. 0 G4_IO2 0 G4_IO2 0 Res. Reset value G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 0 G4_IO3 0 G4_IO3 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 G4_IO4 0 G4_IO4 0 G4_IO4 0 Res. 0 Res. 0 Res. Reset value G5_IO1 G5_IO3 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 G5_IO3 G5_IO1 G5_IO4 G5_IO2 G6_IO1 1 G5_IO2 G5_IO4 G6_IO2 1 G5_IO1 G5_IO3 G6_IO1 G6_IO3 1 G5_IO2 G5_IO4 G6_IO2 G6_IO4 1 Res. G5_IO3 G6_IO1 G6_IO3 G7_IO1 1 Res. G5_IO4 G6_IO2 G6_IO4 G7_IO2 1 Res. G6_IO1 G6_IO3 G7_IO1 G7_IO3 1 G5_IO1 G1S 0 Res. G6_IO2 G6_IO4 G7_IO2 G7_IO4 1 Res. G6_IO3 G7_IO1 G7_IO3 G8_IO1 1 Res. G6_IO4 G7_IO2 G7_IO4 G8_IO2 1 Res. G7_IO1 G7_IO3 G8_IO1 G8_IO3 1 Res. G2S 0 Res. G7_IO2 G7_IO4 G8_IO2 G8_IO4 1 G5_IO2 G3S 0 Res. G7_IO3 G8_IO1 G8_IO3 1 Res. Res. G4S 0 Res. G7_IO4 G8_IO2 TSC_IOASCR G8_IO4 1 Res. Res. G5S 0 Res. G8_IO1 G8_IO3 Reset value Res. Res. G6S 0 Res. G8_IO2 TSC_IOSCR G8_IO4 TSC_IOHCR Res. Res. G7S 0 Res. 0x002C Res. Res. Res. Res. G8S Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. G8_IO3 0x0024 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSC_IOCCR G8_IO4 0x001C Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x0014 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. TSC_IOG4CR Res. 0x0040 TSC_IOG3CR Res. 0x003C TSC_IOG2CR Res. 0x0038 TSC_IOG1CR Res. 0x0034 TSC_IOGCSR Res. 0x0030 Res. 0x0028 Res. 0x0020 Res. 0x0018 Res. 0x0010 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOAF Reset value EOAIC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MCEIC Reset value MCEF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSC_ISR Res. 0x000C TSC_ICR Res. 0x0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. RM0351 Touch sensing controller (TSC) Table 137. TSC register map and reset values (continued) 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 701/1680 702 Touch sensing controller (TSC) RM0351 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSC_IOG6CR Res. 0x0048 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 137. TSC register map and reset values (continued) 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 68 for the register boundary addresses. 702/1680 DocID024597 Rev 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT[13:0] 0 Reset value 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSC_IOG8CR 0 CNT[13:0] 0 Reset value 0x0050 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSC_IOG7CR Res. Reset value 0x004C CNT[13:0] 0 0 0 RM0351 Random number generator (RNG) 24 Random number generator (RNG) 24.1 Introduction The RNG processor is a random number generator, based on a continuous analog noise, that provides a random 32-bit value to the host when read. The RNG passed the FIPS PUB 140-2 (2001 October 10) tests with a success ratio of 99%. 24.2 24.3 RNG main features • It delivers 32-bit random numbers, produced by an analog generator • 40 periods of the RNG_CLK clock signal between two consecutive random numbers • Monitoring of the RNG entropy to flag abnormal behavior (generation of stable values, or of a stable sequence of values) • It can be disabled to reduce power consumption RNG functional description Figure 170 shows the RNG block diagram. Figure 170. Block diagram BIT !(" BUS DATA REGISTER #ONTROL REGISTER 2.'?$2 2.' ?#2 ,&32 2.'?#,+ 3TATUS REGISTER 2.' ?32 #LOCK CHECKER FAULT DETECTOR FEED A ,INEAR &EEDBACK 3HIFT 2EGISTER !NALOG SEED AI 1. For more details about RNG Clock (RNG_CLK) source, please refer to Section 8: Reset and clock control (RCC). The random number generator implements an analog circuit. This circuit generates seeds that feed a linear feedback shift register (RNG_LFSR) in order to produce 32-bit random numbers. The analog circuit is made of several ring oscillators whose outputs are XORed to generate the seeds. The RNG_LFSR is clocked by a dedicated clock (RNG_CLK) at a constant frequency, so that the quality of the random number is independent of the HCLK frequency. The contents of the RNG_LFSR are transferred into the data register (RNG_DR) when a significant number of seeds have been introduced into the RNG_LFSR. DocID024597 Rev 1 703/1680 707 Random number generator (RNG) RM0351 In parallel, the analog seed and the dedicated RNG_CLK clock are monitored. Status bits (in the RNG_SR register) indicate when an abnormal sequence occurs on the seed or when the frequency of the RNG_CLK clock is too low. An interrupt can be generated when an error is detected. 24.3.1 Operation To run the RNG, follow the steps below: 1. Enable the interrupt if needed (to do so, set the IE bit in the RNG_CR register). An interrupt is generated when a random number is ready or when an error occurs. 2. Enable the random number generation by setting the RNGEN bit in the RNG_CR register. This activates the analog part, the RNG_LFSR and the error detector. 3. At each interrupt, check that no error occurred (the SEIS and CEIS bits should be ‘0’ in the RNG_SR register) and that a random number is ready (the DRDY bit is ‘1’ in the RNG_SR register). The contents of the RNG_DR register can then be read. As required by the FIPS PUB (Federal Information Processing Standard Publication) 140-2, the first random number generated after setting the RNGEN bit should not be used, but saved for comparison with the next generated random number. Each subsequent generated random number has to be compared with the previously generated number. The test fails if any two compared numbers are equal (continuous random number generator test). 24.3.2 Error management If the CEIS bit is read as ‘1’ (clock error) In the case of a clock, the RNG is no more able to generate random numbers because the RNG_CLK clock is not correct. Check that the clock controller is correctly configured to provide the RNG clock and clear the CEIS bit. The RNG can work when the CECS bit is ‘0’. The clock error has no impact on the previously generated random numbers, and the RNG_DR register contents can be used. If the SEIS bit is read as ‘1’ (seed error) In the case of a seed error, the generation of random numbers is interrupted for as long as the SECS bit is ‘1’. If a number is available in the RNG_DR register, it must not be used because it may not have enough entropy. What you should do is clear the SEIS bit, then clear and set the RNGEN bit to reinitialize and restart the RNG. 704/1680 DocID024597 Rev 1 RM0351 Random number generator (RNG) 24.4 RNG registers The RNG is associated with a control register, a data register and a status register. They have to be accessed by words (32 bits). 24.4.1 RNG control register (RNG_CR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IE RNGEN Res. Res. rw rw Bits 31:4 Reserved, must be kept at reset value Bit 3 IE: Interrupt enable 0: RNG Interrupt is disabled 1: RNG Interrupt is enabled. An interrupt is pending as soon as DRDY=1 or SEIS=1 or CEIS=1 in the RNG_SR register. Bit 2 RNGEN: Random number generator enable 0: Random number generator is disabled 1: random Number Generator is enabled. Bits 1:0 Reserved, must be kept at reset value 24.4.2 RNG status register (RNG_SR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. SEIS CEIS Res. Res. SECS CECS DRDY rc_w0 rc_w0 r r r DocID024597 Rev 1 705/1680 707 Random number generator (RNG) RM0351 Bits 31:7 Reserved, must be kept at reset value Bit 6 SEIS: Seed error interrupt status This bit is set at the same time as SECS, it is cleared by writing it to 0. 0: No faulty sequence detected 1: One of the following faulty sequences has been detected: – More than 64 consecutive bits at the same value (0 or 1) – More than 32 consecutive alternations of 0 and 1 (0101010101...01) An interrupt is pending if IE = 1 in the RNG_CR register. Bit 5 CEIS: Clock error interrupt status This bit is set at the same time as CECS, it is cleared by writing it to 0. 0: The RNG_CLK clock was correctly detected 1: The RNG_CLK was not correctly detected (fRNG_CLK< fHCLK/16) An interrupt is pending if IE = 1 in the RNG_CR register. Bits 4:3 Reserved, must be kept at reset value Bit 2 SECS: Seed error current status 0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 1: One of the following faulty sequences has been detected: – More than 64 consecutive bits at the same value (0 or 1) – More than 32 consecutive alternations of 0 and 1 (0101010101...01) Bit 1 CECS: Clock error current status 0: The RNG_CLK clock has been correctly detected. If the CEIS bit is set, this means that a clock error was detected and the situation has been recovered 1: The RNG_CLK was not correctly detected (fRNG_CLK< fHCLK/16). Bit 0 DRDY: Data ready 0: The RNG_DR register is not yet valid, no random data is available 1: The RNG_DR register contains valid random data Note: An interrupt is pending if IE = 1 in the RNG_CR register. Once the RNG_DR register has been read, this bit returns to 0 until a new valid value is computed. 24.4.3 RNG data register (RNG_DR) Address offset: 0x08 Reset value: 0x0000 0000 The RNG_DR register is a read-only register that delivers a 32-bit random value when read. After being read, this register delivers a new random value after a maximum time of 40 periods of the RNG_CLK clock. The software must check that the DRDY bit is set before reading the RNDATA value. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RNDATA r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r r RNDATA 706/1680 r DocID024597 Rev 1 RM0351 Random number generator (RNG) Bits 31:0 RNDATA: Random data 32-bit random data. 24.4.4 RNG register map Table 138 gives the RNG register map and reset values. Table 138. RNG register map and reset map Register size 0 0 0 0 0 0 0 0 0 0 0 0 IE Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. 0 Res. 0 Res. 0 Res. Res. Res. 0 0 Res. 0 0 RNGEN 0 RNDATA[31:0] 0 0 0 0 0 0 CEIS Reset value RNG_DR Reset value SEIS 0x08 RNG_SR Res. 0x04 0 Res. Reset value SECS Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. RNG_CR Res. 0x00 reset value Res. Offset Register name 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 68 for the register boundary addresses. DocID024597 Rev 1 707/1680 707 Advanced encryption standard hardware accelerator (AES) RM0351 25 Advanced encryption standard hardware accelerator (AES) 25.1 Introduction The AES hardware accelerator can be used to both encipher and decipher data using AES algorithm. It is a fully compliant implementation of the following standard: • The advanced encryption standard (AES) as defined by Federal Information Processing Standards Publication (FIPS PUB 197, 2001 November 26) The accelerator encrypts and decrypts 128-bit blocks using either 128-bit or 256-bit key length. It can also perform key derivation. The encryption or decryption key is stored in an internal register in order to minimize write operations by the CPU or DMA when processing several data blocks using the same key. By default, electronic codebook mode (ECB) is selected. Cipher block chaining (CBC), counter (CTR) mode, Galois counter (GCM) mode, Galois message authentication code (GMAC) or cipher message authentication code mode (CMAC) chaining algorithms are also supported by the hardware. The AES supports DMA transfer for incoming and for outcoming data (2 DMA channels required). 25.2 708/1680 AES main features • Encryption/decryption using AES Rijndael Block Cipher algorithm • NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm • 256-bit register for storing the encryption, decryption or derivation key (8x 32-bit registers) • Electronic codebook (ECB), cipher block chaining (CBC), counter mode (CTR), Galois counter mode (GCM), Galois message authentication code mode (GMAC) and cipher message authentication code mode (CMAC) supported • Key scheduler • Key derivation for decryption • 128-bit data block processing • 128-bit, 256-bit key length • 1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer • Register access supporting 32-bit data width only • One register used as a 128-bit initialization vector when AES is configured in CBC mode or used as a 32-bit counter initialization when CTR, GCM or CMAC mode is selected • Automatic data flow control with support of direct memory access (DMA) using 2 channels, one for incoming data, and one for outcoming data. • Suspend a message if another message with a higher priority needs to be processed • Cycles to process for each mode DocID024597 Rev 1 RM0351 25.3 Advanced encryption standard hardware accelerator (AES) AES functional description Figure 171 shows the block diagram of the AES accelerator. Figure 171. AES block diagram $(6B 6835[ $(6B65 $(6B&5 $(6B,95 $(6B',15 $(6B '2875 $(6B .(<5[ $(6KDUGZDUHDFFHOHUDWRU 069 The AES accelerator processes data blocks of 128-bits (4 words) using a key with a length of either 256 bits or 128 bits, and an initialization vector when CBC, CTR, GCM, GMAC or CMAC chaining mode is selected. It provides 4 operating modes: • Mode 1: encryption using the encryption key stored in the AES_KEYRx registers. • Mode 2: key derivation stored internally in the AES_KEYRx registers at the end of the key derivation processed from the encryption key stored in this register before enabling the AES. This mode is independent from the AES chaining mode selection. • Mode 3: decryption using a given (pre-computed) decryption key stored in the AES_KEYRx registers. • Mode 4: key derivation + decryption using an encryption key stored in the AES_KEYRx registers (not used when the AES is configured in Counter mode for perform a chaining algorithm). The operating mode is selected by programming bits MODE[1:0] into the AES_CR register. The mode must be changed only when the AES is disabled (bit EN = 0 in the AES_CR register). Note: The AES_KEYRx registers must be stored before enabling the AES. To select which one of the ECB, CBC, CTR, GCM, GMAC or CMAC mode is going to be used for the cryptographic solution, it is mandatory to write the bit CHMOD[2:0] of the AES_CR register and the AES_IVR register when the AES is disabled (bit EN = 0 in the AES_CR register). Once enabled (bit EN = 1 in AES_CR register), the AES is in the input phase, waiting for the software to write the input data words into the AES_DINR (4 words) for the modes 1, 3 or 4. The data correspond either to the plaintext message or the cipher message. A wait cycle is automatically inserted between two consecutive writes to the AES_DINR register in order to send, interleaved with the data, the key to the AES processor. For mode 2, the key derivation processing is started immediately after the EN bit in the AES_CR register is set. It requires that the AES_KEYRx registers are loaded with the encrypted key before enabling the AES. At the end of the key derivation processing computation complete flag (CCF) in AES_SR register is set. The derivative key is available DocID024597 Rev 1 709/1680 744 Advanced encryption standard hardware accelerator (AES) RM0351 in the AES_KEYRx registers and the AES is disabled by hardware. In this mode, the AES_KEYRx registers must not be read when AES is enabled and until the CCF flag is set to 1 by hardware. The status flag CCF in the AES_SR register is set once the computation phase is complete. An interrupt can be generated if bit CCFIE = 1 (CCF interrupt enable) in the AES_CR register. The software can then read back the data from the AES_DOUTR register (for modes 1, 3, 4) or from the AES_KEYRx registers (if mode 2 is selected). The flag CCF has no meaning when DMA is used (DMAOUTEN = 1 in the AES_CR register), because the reading the AES_DOUTR register is managed by DMA automatically without any software action at the end of the computation phase. The operation ends with the output phase, during which the software reads successively the 4 output data words from the AES_DOUTR register in mode 1, 3 or 4. In mode 2 (key derivation mode), the data is automatically stored in the AES_KEYRx registers and the AES is disabled by hardware. Then, software can select mode 3 (decryption mode) before it enables the AES to start the decryption using this derivative key. During the input and output phases, the software must read or write the data bytes successively (except in mode 2) but the AES is tolerant of any delays occurring between each read or write operation (example: if servicing another interrupt at this time). The read error flag (RDERR) and write error flag (WRERR) in the AES_SR register are set when an unexpected read or write operation is detected. An interrupt can be generated if the error interrupt enable (ERRIE) bit is set in the AES_CR register. AES is not disabled after an error detection and continues processing as normal. It is also possible to use the general purpose DMA to write the input words and to read the output words (refer to Figure 186 and Figure 187). The AES can be re-initialized at any moment by resetting the EN bit in the AES_CR register. Then the AES can be re-started from the beginning by setting EN = 1, waiting for the first input data byte to be written (except in mode 2 where key derivation processing starts as soon as the EN bit is set, starting from the value stored in the AES_KEYRx registers). 25.4 Encryption and derivation keys The AES_KEYRx registers are used to store the encryption or decryption keys. These four (respectively eight) registers are organized in little-endian configuration: Register AES_KEYR0 has to be loaded with the 32-bit LSB of the key. Consequently, AES_KEYR3 (respectively AES_KEYR7) has to be loaded with the 32-bit MSB of the 128-bit key (respectively with the 32-bit MSB of the 256-bit key). Note: 1 AES_KEYR0 to AES_KEYR3 registers are used when key length equal to 128-bit or 256-bit is selected. 2 AES_KEYR4 to AES_KEYR7 registers are used only when key length equal to 256-bit is selected. The key for encryption or decryption must be stored in these registers when the AES is disabled (EN = 0 into the AES_CR register). Their endianess are fixed. In mode 2 (key derivation), the AES_KEYRx needs to be loaded with the encryption key. Then, the AES has to be enabled. At the end of the computation phase, the derivation key is stored automatically in the AES_KEYRx registers, overwriting the previous encryption key. The AES is disabled by hardware when the derivation key is available. If the software needs 710/1680 DocID024597 Rev 1 RM0351 Advanced encryption standard hardware accelerator (AES) to switch the AES to mode 3 (decryption mode), there is no need to write the AES_KEYRx registers if their content corresponds to the derivation key (previously computed by mode 2). In mode 4 (key derivation + decryption), the AES_KEYRx registers contain only the encryption key. The derivation key is calculated internally without any write to these registers. 25.5 AES chaining algorithms Five algorithms are supported by the AES hardware and can be selected through the CHMOD[2:0] bits in the AES_CR register when the AES is disabled (bit EN = 0): 25.5.1 • Electronic codebook (ECB) • Cipher block chaining (CBC) • Counter mode (CTR) • Galois counter mode (GCM) and Galois message authentication code mode (GMAC) • Cipher message authentication code mode (CMAC) Electronic codebook (ECB) This is the default mode. This mode does not use the AES_IVR register. There are no chaining operations. The message is divided into blocks and each block is encrypted separately. Figure 172 and Figure 173 describe the principle of the electronic codebook algorithm for encryption and decryption respectively. Figure 172. ECB encryption mode $(6B',15 3ODLQWH[W 'DWDW\SH>@ $(6B.(<5[ 'DWDW\SH>@ 6:$3 PDQDJHPHQW %ORFNFLSKHU (QFU\SWLRQ 6:$3 PDQDJHPHQW $(6B'2875 &LSKHUWH[W 069 DocID024597 Rev 1 711/1680 744 Advanced encryption standard hardware accelerator (AES) RM0351 Figure 173. ECB decryption mode $(6B ',15 &LSKHUWH[W 'DWDW\SH >@ $(6B.(<5[ .H\ 'DWDW\SH >@ 6:$3 PDQDJHPHQW %ORFNFLSKHU 'HFU\SWLRQ 6:$3 PDQDJHPHQW $(6B '2875 3ODLQWH[W 069 25.5.2 Cipher block chaining (CBC) In cipher-block chaining (CBC) mode, each block of plain text is XORed with the previous cipher text block before being encrypted. To make each message unique, an initialization vector (AES_IVRx) is used during the first block processing. The initialization vector is XORed after the swapping management block during encryption mode and before it in decryption mode (refer to Figure 174 and Figure 175). 712/1680 DocID024597 Rev 1 RM0351 Advanced encryption standard hardware accelerator (AES) Figure 174. CBC mode encryption $(6B ',15 3ODLQWH[W 'DWDW\SH >@ $(6B ',15 3ODLQWH[W 6:$3 PDQDJHPHQW 6:$3 PDQDJHPHQW 'DWDW\SH >@ $(6B ,95[ $(6B.(<5[ .H\ 'DWDW\SH >@ %ORFNFLSKHU (QFU\SWLRQ $(6B.(<5[ .H\ 6:$3 PDQDJHPHQW %ORFNFLSKHU (QFU\SWLRQ 6:$3 PDQDJHPHQW 'DWDW\SH >@ $(6B'2875 &LSKHUWH[W $(6B'2875 &LSKHUWH[W 069 Figure 175. CBC mode decryption $(6B',15 &LSKHUWH[W 'DWDW\SH>@ $(6B.(<5[ .H\ $(6B',15 &LSKHUWH[W 6:$3 PDQDJHPHQW %ORFNFLSKHU 'HFU\SWLRQ 'DWDW\SH>@ $(6B.(<5[ .H\ 6:$3 PDQDJHPHQW %ORFNFLSKHU 'HFU\SWLRQ $(6B,95[ 'DWDW\SH>@ 6:$3 PDQDJHPHQW $(6B'2875 3ODLQWH[W 'DWDW\SH>@ 6:$3 PDQDJHPHQW $(6B'2875 3ODLQWH[W 069 Note: When the AES is enabled, reading the AES_IVR returns the value 0x0000 0000. DocID024597 Rev 1 713/1680 744 Advanced encryption standard hardware accelerator (AES) RM0351 Suspended mode for a given message It is possible to suspend a message if another message with a higher priority needs to be processed. After sending this highest priority message, the suspended message may be resumed in both encryption or decryption mode. This feature is available only when the data transfer is done by CPU accesses to the AES_DOUTR and AES_DINR registers. It is advised to not use it when the DMA controller is managing the data transfer. For correct operation, the message must be suspended at the end of a block processing (after the fourth read of the AES_DOUTR register and before the next AES_DINR write access corresponding to the input of the next block to be processed). The AES should be disabled writing bit EN = 0 in the AES_CR register. The software has to read the AES_IVRx which contains the latest value to be used for the chaining XOR operation before message interruption. This value has to be stored for reuse by writing the AES_IVRx registers as soon as the interrupted message has to be resumed (when AES is disabled). Note: This does not break the chaining operation and the message processing can be resumed as soon as the AES is enabled again to send the next 128-bit data block. Note: This behavior is valid whatever the AES configuration (encryption or decryption mode). Figure 176 gives an example of a message 1 which is suspended in order to send a higher priority message 2, shorter than message 1. At the end of the 128-bit block processing, AES is disabled. The AES_IVR register is read back to store the value to be retrieved later on when the message is resumed, in order not to break the chaining operation. Then, the AES is configured to send message 2 and it is enabled to start processing. At the end of message 2 processing, AES has to be disabled again and the AES_IVRx registers have to be loaded with the value previously stored when the message 1 was interrupted. Then software has to restart from the input value corresponding to block 4 as soon as AES is enabled to resume message 1. 714/1680 DocID024597 Rev 1 RM0351 Advanced encryption standard hardware accelerator (AES) Figure 176. Example of suspend mode management 0HVVDJH ELWEORFN ELWEORFN 1HZKLJKHUSULRULW\ PHVVDJHWR EHSURFHVVHG 0HVVDJH $(6GLVDEOHG UHDG$(6B,95DQGVWRUHWKHYDOXH &RQILJXULQJ$(6IRUQH[WPHVVDJH $(6HQDEOHG ELWEORFN ELWEORFN ELWEORFN ELWEORFN ELWEORFN ELWEORFN ELWEORFN $(6GLVDEOHG ZULWHWKH$(6B,95ZLWKWKHYDOXHVWRUHG $(6HQDEOHG ELWEORFN 069 DocID024597 Rev 1 715/1680 744 Advanced encryption standard hardware accelerator (AES) 25.5.3 RM0351 Counter Mode (CTR) In counter mode, a 32-bit counter is used in addition to a nonce value for the XOR operation with the cipher text or plain text (refer to Figure 177 and Figure 178). Figure 177. CTR mode encryption $(6B,95[ 1RQFH $(6B.(<5[ .H\ $(6B,95[ FRXQWHU 1RQFH $(6B.(<5[ .H\ %ORFNFLSKHU HQFU\SWLRQ $(6B',15 3ODLQWH[W 6ZDS PDQDJHPHQW FRXQWHU %ORFNFLSKHU HQFU\SWLRQ $(6B',15 3ODLQWH[W 6ZDS PDQDJHPHQW 'DWDW\SH>@ 'DWDW\SH>@ 6ZDS PDQDJHPHQW 'DWDW\SH>@ 'DWDW\SH>@ 6ZDS PDQDJHPHQW $(6B'2875 &LSKHUWH[W $(6B'2875 &LSKHUWH[W 06 Figure 178. CTR mode decryption $(6B,95[ 1RQFH $(6B.(<5[ .H\ FRXQWHU %ORFNFLSKHU HQFU\SWLRQ $(6B',15 &LSKHUWH[W 6ZDS PDQDJHPHQW 'DWDW\SH>@ 'DWDW\SH >@ 6ZDS PDQDJHPHQW $(6B'2875 3ODLQWH[W D^ϭϴϵϰϮsϭ 716/1680 DocID024597 Rev 1 RM0351 Advanced encryption standard hardware accelerator (AES) The nonce value and 32-bit counter are accessible through the AES_IVRx register and organized like below in Figure 179: Figure 179. 32-bit counter + nonce organization $(6B,95 $(6B,95 $(6B,95 1RQFH $(6B,95 ELWFRXQWHU 069 In counter mode, the counter is incremented from the initialized value for each block to be processed in order to guarantee a unique sequence which is not repeated for a long time. It is a 32-bit counter, meaning that the nonce message is kept to the initialized value stored when the AES was disabled. Only the 32-bit LSB of the 128-bit initialization vector register represents the counter. In contrast to CBC mode (which uses the AES_IVRx registers only once when processing the first data block), in counter mode, the AES_IVRx registers are used for processing each data block. In counter mode, key derivation + decryption mode is not applicable. Note: The AES_IVRx register has be written only when the AES is disabled (bit EN = 0) to guarantee good AES behavior. Reading it while AES is enabled returns the value 0x00000000. Reading it while the AES is disabled returns the latest counter value (useful for managing suspend mode). In CTR mode, key derivation + decryption serves no purpose. Consequently it is forbidden to set MODE[1:0] = 11 in the AES_CR register and any attempt to set this configuration is forced to MODE[1:0] = 10 (which corresponds to CTR mode decryption). This uses the encryption block of the AES processor to decipher the message as shown in Figure 178. Suspend mode in CTR mode Like for the CBC mode, it is possible to interrupt a message, sending a higher priority message and resume the message which was interrupted. Refer to the Figure 176 and Section 25.5.2 for more details about the suspend mode capability. 25.6 Galois counter mode (GCM) GCM allows to encrypt and authenticate the plaintext, generating the corresponding ciphertext and the TAG (also known as message authentication code or message integrity check). It is based on AES in counter mode for confidentiality and it uses a multiplier over a fixed finite field for generating the TAG. It requires an initialization vector at the beginning. The message to process can be split in 2 different portions: • The first that is authenticated only (the header of the message), • The second that is authenticated and encrypted (the payload). The header part must precede the payload and the two portions cannot be mixed. GCM standard requires to pass at the end of the message a particular 128-bit block composed by DocID024597 Rev 1 717/1680 744 Advanced encryption standard hardware accelerator (AES) RM0351 the size of the header on 64 bits and the size of the payload on 64 bits. During computation we have to distinguish between the blocks of the header and the blocks of the payload. • Header (aka additional authentication data): data which is authenticated but not • Payload (aka plaintext / ciphertext): the message itself which is protected. protected (such as information for routing the packet) In GCM mode the user must follow 4 phases: GCM Init, GCM header, GCM payload, GCM final. • • GCM init phase: in this first step, the hash key is calculated and saved internally for use during the processing of all the blocks. a) Make sure that the AES core is disabled by clearing EN (AES_CR). b) Select GCM chaining mode by programming CHMOD[1:0] = 011 in AES_CR. c) Configure GCMPH[1:0] = 00 in AES_CR to indicate GCM init phase and force DATATYPE[1:0] = 00 (No swapping) in AES_CR. d) Select mode by selecting either MODE[1:0]= 00 for encryption or MODE[1:0] = 10 for decryption in AES_CR register. e) Initialize the key registers (128/256 bits) in AES_KEYRx and IV. f) Set EN bit in AES_CR register to 1 to start the calculation of the hash key. EN is automatically reset when the calculation finishes. g) Wait until the CCF flag in AES_SR register is set to 1 (or use the corresponding interrupt) before moving on to the next phase. h) Erase the CCF flag by setting CCFC in AES_CR. GCM header phase: To be performed after the GCM init phase. i) Set GCMPH=”01” in AES_CR register to indicate that we are in the header phase and configure DATATYPE[1:0] (1-bit, 8-bits, 16-bits or 32-bits) in AES_CR j) Enable the AES by setting EN bit in AES_CR register. k) Write 4 times the header message into AES_DINR register. l) Wait until the computation flag CCF in AES_SR register is set to 1 (or use the corresponding interrupt). m) Erase CCF by setting the bit CCFC in AES_CR register. n) • 718/1680 Repeat (k), (l), and (m) until each of the header blocks is inserted. Alternatively, DMA may be used. GCM payload phase (encryption / decryption): This step is after GCM_header phase. o) Choose the combination 10 of GCMPH in AES_CR register. p) Write 4 times the payload message into AES_DINR register. q) Wait until the computation flag CCF in AES_SR is set to 1 (or use the corresponding interrupt). r) Erase CCF flag by writing 1 in CCFC bit (AES_CR). This must be done before inserting the next block. s) Read AES_DOUTR 4 times to get the (ciphertext / plaintext). This is compulsory before starting a new block. DocID024597 Rev 1 RM0351 Advanced encryption standard hardware accelerator (AES) Repeat (p), (q), (r) and (s) until ciphering or deciphering of all the payload blocks. Alternatively, DMA may be used. • GCM Final Phase: In this last step, we generate the authentication tag. t) Choose the combination GCMPH[1:0] = 11 in AES_CR. u) Write 4 times the input into the AES_DINR register: the input must be composed of the length of header coded on 64 bits followed with the length of payload coded on 64 bits. v) Wait until the computation flag CCF in AES_SR register is set to 1 (or use the corresponding interrupt). w) Read 4 times the AES_DOUTR register: the output is the “auth tag”. x) Clear CCF flag in AES_SR register by setting CCFC bit in AES_CR to 1. y) Disable AES processor by setting bit EN in AES_CR to 0. No need to disable / enable AES processor when moving from header phase to tag phase. AES can move directly from init to payload or/and to tag (bypassing header phase or/and payload phase) in this case AES enable step should be added after selecting the next phase. AES Galois message authentication code (GMAC) The AES processor supports also GMAC to authenticate the plaintext based on GCM algorithm for generating the corresponding TAG. It is based on a multiplier over a fixed finite field for generating the TAG. It requires an initialization vector at the beginning. Actually GMAC is the same as GCM applied on a message composed only by the header, so all steps and settings are the same except phase 3 will not be used. Suspend mode in GCM In GCM algorithm, suspend mode can be performed during header phase and payload phase. It is advised to not use suspend mode in init phase or tag phase since suspend mode has no benefit in these phases: Suspend mode during header phase: the user must respect the following steps: • • Before interrupting the current message: a) Make sure that CCF flag read from AES_SR is set to 1. b) Clear CCF flag in AES_SR register by setting CCFC in AES_CR to 1. c) Save AES_SUSPxR registers in the memory. d) Disable AES processor by setting EN in AES_CR to 0. e) Save the current AES configuration in the memory. To resume: f) Make sure that AES processor is disabled by reading the bit EN in AES_CR. g) Write back AES_SUSPxR registers into their corresponding suspend registers. h) Re-configure AES with the initial setting values in CR register, IV register and key registers. i) Enable the AES processor by setting EN in AES_CR register. DocID024597 Rev 1 719/1680 744 Advanced encryption standard hardware accelerator (AES) RM0351 Suspend mode during Payload phase: the user must respect the following steps: • Note: Before interrupting the current message: a) Read 4 times the AES_DOUTR register. b) Make sure that busy flag is set to 0 (only in encryption mode, not necessary in decryption mode). c) Save AES_SUSPxR registers in the memory. d) Save AES initialization vector registers AES_IVx in the memory. AES_IVx registers are modified during payload phase. • e) Disable AES processor by setting EN i n AES_CR to 0. f) Save the current AES configuration in the memory (except AES initialization vector values) To resume: g) Make sure that AES processor is disabled by reading EN in AES_CR. h) Write back AES_SUSPxR registers into their corresponding suspend registers. i) Write back AES_IVx registers into their AES initialization vectors. j) Re-configure AES with the initial setting values in CR register and key registers. k) Enable the AES processor by setting EN bit in AES_CR register. Suspend mode in GMAC GMAC is exactly the same as GCM algorithm except: only Header phase can be interrupt. 25.7 AES cipher message authentication code mode (CMAC) CMAC allows to authenticate the plaintext, generating the corresponding TAG. The message is composed only by the header phase and the tag phase. The CCM standard (RFC 3610 Counter with CBC-MAC (CCM) dated September 2003) defines particular encoding rules for the first authentication block (called B0 in the standard). In particular, the first block includes flags, a nonce and the payload length expressed in bytes. • 720/1680 a) Make sure that the AES processor is disabled by clearing EN (AES_CR) and that AES operating mode is different than mode 2 (key derivation) and mode 4 (key derivation + decryption) b) Select CMAC chaining mode by programming CHMOD bits[2:0] = 100 in AES_CR. c) Initialize key registers (128 / 256 bits) in AES_KEYRx and IV with zero values in AES_IVRx CMAC header phase: DocID024597 Rev 1 RM0351 Note: Advanced encryption standard hardware accelerator (AES) In this stage, no output is provided in AES_DOUTR register. • Note: d) Set GCMPH=”01” in AES_CR to indicate that we are in the header phase. e) Enable the AES by setting EN bit in AES_CR. f) Insert B0 for first transfer, and then B for further transfers. g) Write 4 times the header message into AES_DINR register. h) Wait until the computation flag CCF (AES_SR) is set (or use the corresponding interrupt). i) Erase CCF by setting CCFC in AES_CR. j) Repeat (g), (h), and (i) until each of the header blocks is inserted. Alternatively, DMA may be used. CMAC Final Phase: in this last step, we generate the authorization tag. In this stage, The authorization tag of the message is provided in AES_DOUTR register. k) Choose the combination GCMPH[1:0] = 11 in AES_CR. l) Write 4 times the input into the AES_DIN register: the input must be the 128-bit value formatted from the original B0 packet.(i.e bits [7:3] of B0 should be forced to zero value). m) Wait until computation flag CCF is set in AES_SR. Note: n) Read 4 times the AES_DOUTR: the output is the “auth tag”. o) Erase the flag by raising CCFC bit in AES_CR. p) Disable AES. 1 The hardware does not manage the formatting operation of the original B0 and B1, the latter having to contain the header length. This task must be handled by software. 2 No need to disable/enable AES processor when moving from header phase to tag phase. 3 The software should filter the Auth Tag output with tag length to obtain the valid TAG. Suspend mode in CMAC mode In CMAC algorithm, suspend mode can be performed only during header phase. It is advised to not use suspend mode in tag phase since suspend mode has no benefit in this phase: DocID024597 Rev 1 721/1680 744 Advanced encryption standard hardware accelerator (AES) RM0351 To suspend mode CMAC during header phase, the user must respect the following steps: • Before interrupting the current message: a) • 25.8 Make sure that CCF flag in AES_SR is set to 1. b) Clear CCF flag in AES_SR register by setting CCFC bit to 1 in AES_CR. c) Save AES initialization vector registers AES_IVx and AES_SUSPxR registers in the memory (AES_IVx registers are modified during header phase) d) Disable AES processor by setting EN in AES_CR to 0. e) Save the current AES configuration values in the memory. To resume: f) Make sure that AES processor is disabled by reading bit EN in AES_CR. g) Write back AES_SUSPxR registers into their corresponding suspend registers. h) Write back AES_IVx registers into their AES initialization vector registers i) Re-configure AES with the initial setting values in CR register and key registers. j) Enable the AES processor by setting EN in AES_CR register. Data type Data are entered in the AES processor 32 bits at a time (words), by writing them in the AES_DINR register. AES handles 128-bit data blocks. The AES_DINR or AES_DOUTR registers must be read or written four times to handle one 128-bit data block with the MSB first. The system memory organization is little-endian: whatever the data type (bit, byte, 16-bit half-word, 32-bit word) used, the less-significant data occupies the lowest address location. Thus, there must be a bit, byte, or half-word swapping operation to be performed on data to be written in the AES_DINR from system memory before entering the AES processor, and the same swapping must be performed for AES data to be read from the AES_DOUTR register to the system memory, depending on to the kind of data to be encrypted or decrypted. The DATATYPE bits in the AES_CR register offer different swap modes to be applied to the AES_DINR register before sending it to the AES processor and to be applied on the AES_DOUTR register on the data coming out from the processor (refer to Figure 180). Note: 722/1680 The swapping operation concerns only the AES_DOUTR and AES_DINR registers. The AES_KEYRx and AES_IVRx registers are not sensitive to the swap mode selected. They have a fixed little-endian configuration (refer to Section 25.4 and Section 25.14). DocID024597 Rev 1 RM0351 Advanced encryption standard hardware accelerator (AES) Figure 180. 128-bit block construction according to the data type $!4!490% B .O SWAPPING !%3?$).2 OR !%3?$/542 ,3" -3" 7ORD 7ORD 7ORD 7ORD ,3" -3" !%3 PROCESSOR INPUT OR !%3 PROCESSOR OUTPUT $!4!490% B BIT OR HALF WORD SWAPPING !%3?$).2 OR !%3?$/542 -3" 7ORD 7ORD BIT BIT BIT BIT BIT BIT BIT BIT ,3" 7ORD 7ORD BIT BIT BIT BIT BIT BIT -3" BIT BIT ,3" !%3 PROCESSOR INPUT OR !%3 PROCESSOR OUTPUT $!4!490% B BIT OR "YTE SWAPPING !%3?$).2 OR !%3?$/542 -3" 7ORD 7ORD BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT ,3" 7ORD 7ORD BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT -3" BIT BIT ,3" !%3 PROCESSOR INPUT OR !%3 PROCESSOR OUTPUT -36 DocID024597 Rev 1 723/1680 744 Advanced encryption standard hardware accelerator (AES) RM0351 Figure 181. 128-bit block construction according to the data type (continued) $!4!490% B "IT SWAPPING !%3?$).2 OR !%3?$/542 -3" 7/2$ 7/2$ BIT BIT BIT BIT BIT BIT BIT BIT BIT ,3" 7/2$ 7/2$ BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT ,3" -3" !%3 PROCESSOR INPUT OR !%3 PROCESSOR OUTPUT -36 25.9 Operating modes 25.9.1 Mode 1: encryption 724/1680 1. Disable the AES by resetting EN bit in the AES_CR register. 2. Configure the mode 1 by programming MODE[1:0] = 00 in the AES_CR register and select which type of chaining mode needs to be performed by programming the CHMOD[2:0] bits. 3. Select key length 128-bits or 256-bits via KEYSIZE bits configuration in AES_CR register. 4. Write the AES_KEYRx registers (128-bit or 256-bit with encryption key) and the AES_IVRx registers if CTR, CBC or GCM mode is selected. For ECB mode, the AES_IVRx register is not used. 5. Enable the AES by setting the EN bit in the AES_CR register. 6. Write the AES_DINR register 4 times to input the plain text (MSB first) as shown in Figure 182: Mode 1: encryption with 128-bit key length. 7. Wait until the CCF flag is set in the AES_SR register. 8. Read the AES_DOUTR register 4 times to get the cipher text (MSB first) as shown in Figure 182: Mode 1: encryption with 128-bit key length. 9. Repeat steps 6,7,8 to process all the blocks with the same encryption key. DocID024597 Rev 1 RM0351 Advanced encryption standard hardware accelerator (AES) Figure 182. Mode 1: encryption with 128-bit key length :5 37 :5 37 :5 37 06% :5 37 :DLWXQWLOIODJ&&) /6% 5' &7 5' &7 5' &7 5' &7 06% ,QSXWSKDVH ZULWHRSHUDWLRQVLQWR $(6B',1>@ /6% 2XWSXWSKDVH UHDGRSHUDWLRQVRI $(6B'287>@ &RPSXWDWLRQSKDVH 37 SODLQWH[W ZRUGV 37«37 &7 F\SKHUWH[W ZRUGV &7«&7 069 25.9.2 Note: Mode 2: key derivation 1. Disable the AES by resetting the EN bit in the AES_CR register. 2. Configure mode 2 by programming MODE[1:0] = 01 in the AES_CR register. CHMOD[2:0] bits are not significant in this case because this key derivation mode is independent from the chaining algorithm selected. 3. Select key length 128-bit or 256-bit via KEYSIZE bits configuration in AES_CR register. 4. Write the AES_KEYRx registers with the encryption key to obtain the derivative key. A write to the AES_IVRx has no effect. 5. Enable the AES by setting the EN bit in the AES_CR register. 6. Wait until the CCF flag is set in the AES_SR register. 7. The derivation key is put automatically into the AES_KEYRx registers. Read the AES_KEYRx registers to obtain the decryption key if needed. The AES is disabled by hardware. To restart a derivation key calculation, repeat steps 3, 4, 5 and 6. Figure 183. Mode 2: key derivation with 128-bit key length :5 (. 06% :5 (. :5 (. :5 (. :DLWXQWLOIODJ&&) /6% ,QSXWSKDVH ZULWHRSHUDWLRQVLQWR $(6B.(<5[>@ 5' '. 06% &RPSXWDWLRQSKDVH (1 LQWR$(6B&5 (. HQFU\SWLRQNH\ ZRUGV (.«(. '. GHFU\SWLRQNH\ ZRUGV '.«'. 5' '. 5' '. 5' '. /6% 2XWSXWSKDVH RSWLRQDO UHDGRSHUDWLRQVRI $(6B.(<5[>@ ELWGHULYDWLRQNH\ VWRUHGLQWR$(6B.(<5[ 069 DocID024597 Rev 1 725/1680 744 Advanced encryption standard hardware accelerator (AES) 25.9.3 RM0351 Mode 3: decryption 1. Disable the AES by resetting the EN bit in the AES_CR register. 2. Configure mode 3 by programming MODE[1:0] = 10 in the AES_CR register and select which type of chaining mode needs to be performed by programming the CHMOD[2:0] bits. 3. Select Key length 128-bit or 256-bit via KEYSIZE bits configuration in AES_CR register. 4. Write the AES_KEYRx registers with the decryption key (this step can be bypassed if the derivation key is already stored in the AES_KEYRx registers using mode 2: key derivation). Write the AES_IVRx registers if CTR, CBC or GCM mode is selected. For ECB mode, the AES_IVRx registers are not used. 5. Enable the AES by setting the EN bit in the AES_CR register. 6. Write the AES_DINR register 4 times to input the cipher text (MSB first) as shown in Figure 184: Mode 3: decryption with 128-bit key length. 7. Wait until the CCF flag is set in the AES_SR register. 8. Read the AES_DOUTR register 4 times to get the plain text (MSB first) as shown in Figure 184: Mode 3: decryption with 128-bit key length. 9. Repeat steps 6, 7, 8 to process all the blocks using the same derivation key stored in the AES_KEYRx registers. Figure 184. Mode 3: decryption with 128-bit key length :5 &7 06% :5 &7 :5 &7 :5 &7 :DLWXQWLOIODJ&&) /6% 5' 37 06% ,QSXWSKDVH ZULWHRSHUDWLRQVLQWR $(6B',1>@ &RPSXWDWLRQSKDVH 5' 37 5' 37 5' 37 /6% 2XWSXWSKDVH UHDGRSHUDWLRQVRI $(6B'287>@ 37 SODLQWH[W ZRUGV 37«37 &7 F\SKHUWH[W ZRUGV &7«&7 069 25.9.4 726/1680 Mode 4: key derivation and decryption 1. Disable the AES by resetting the EN bit in the AES_CR register. 2. Configure mode 4 by programming MODE[1:0] = 11 in the AES_CR register. This mode is forbidden when AES is configured in CTR, GCM, GMAC or CMAC mode. It will be DocID024597 Rev 1 RM0351 Advanced encryption standard hardware accelerator (AES) forced to CTR decryption mode if the software writes MODE[1:0] = 11 and CHMOD[2:0] = 010. Note: 3. Select key length 128-bit or 256-bit via KEYSIZE bits configuration in AES_CR register. 4. Write the AES_KEYRx register with the encryption key. Write the AES_IVRx register if the CBC mode is selected. 5. Enable the AES by setting the EN bit in the AES_CR register. 6. Write the AES_DINR register 4 times to input the cipher text (MSB first) as shown in Figure 185: Mode 4: key derivation and decryption with 128-bit key length. 7. Wait until the CCF flag is set in the AES_SR register. 8. Read the AES_DOUTR register 4 times to get the plain text (MSB first) as shown in Figure 185: Mode 4: key derivation and decryption with 128-bit key length. 9. Repeat steps 6, 7, 8 to process all the blocks with the same encryption key. The AES_KEYRx registers contain the encryption key during all phases of the processing, No derivation key is stored in these registers. The derivation key starting from the encryption key is stored internally in the AES without storing a copy in the AES_KEYRx registers. Figure 185. Mode 4: key derivation and decryption with 128-bit key length 72 #4 72 #4 72 #4 -3" 72 #4 7!)4 5.4), FLAG ##& ,3" ).054 0(!3% 72)4% /0%2!4)/.3 ).4/ !%3?$).;= 2$ 04 -3" #/-054!4)/. 0(!3% 2$ 04 2$ 04 ,3" /54054 0(!3% 2%!$ /0%2!4)/.3 /& !%3?$/54;= 04 0,!). 4%84 7ORDS 04 04 #4 #90(%2 4%84 7ORDS #4 #4 25.10 2$ 04 -36 AES DMA interface The AES accelerator provides an interface to connect to the DMA controller. The DMA must be configured to transfer words. The AES can be associated with two distinct DMA request channels: • A DMA request channel for the inputs: When the DMAINEN bit is set in the AES_CR register, the AES initiates a DMA request (AES_IN) during the INPUT phase each time it requires a word to be written to the AES_DINR register. The DMA channel must be configured in memory-to-peripheral mode with 32-bit data size. • A DMA request channel for the outputs: When the DMAOUTEN bit is enabled, the AES initiates a DMA request (AES_OUT) during the OUTPUT phase each time it requires a word to be read from the AES_DOUTR register. The DMA channel must be configured in peripheral-to-memory mode with a data size equal to 32-bit. Four DMA requests are asserted for each phase, these are described in Figure 186 and Figure 187. DMA requests are generated until the AES is disabled. So, after the data output phase at the end of processing a 128-bit data block, the AES switches automatically to a new data input phase for the next data block if any. DocID024597 Rev 1 727/1680 744 Advanced encryption standard hardware accelerator (AES) Note: RM0351 1 For mode 2 (key derivation), access to the AES_KEYRx registers can be done by software using the CPU. No DMA channel is provided for this purpose. Consequently, the DMAINEN bit and DMAOUTEN bits in the AES_CR register have no effect during this mode. 2 The CCF flag is not relevant when DMAOUTEN = 1 and software does not need to read it in this case. This bit may stay high and has to be cleared by software if the application needs to disable the AES to cancel the DMA management and use CPU access for the data input or data output phase. Figure 186. DMA requests and data transfers during Input phase (AES_IN) -/$% %NCRYPTION -ODE OR $ECRYPTION $-! 2%15%343 -3" !%3?$).2 72 4 $-! 2%1 . $-! 2%1 .§ !%3?$).2 72 4 !%3?$).2 72 4 !%3?$).2 72 4 $-! 2%1 .§ $-! 2%1 .§ -36 Figure 187. DMA requests during Output phase (AES_OUT) -/$% %NCRYPTION -ODE OR $ECRYPTION $-! 2%15%343 -3" !%3?$/542 2$ $ $-! 2%1 .§ !%3?$/542 2$ $ !%3?$/542 2$ $ $-! 2%1 .§ $-! 2%1 .§ !%3?$/542 2$ $ $-! 2%1 .§ $ 0,!). OR #)0(%2 4%84 DEPENDING ON MODE OF OPERATION 7/2$3$ $ -36 25.11 Error flags The AES read error flag (RDERR) in the AES_SR register is set when an unexpected read operation is detected during the computation phase or during the input phase. The AES write error flag (WRERR) in the AES_SR register is set when an unexpected write operation is detected during the output phase or during the computation phase. The flags may be cleared setting the respective bit in the AES_CR register (CCFC bit to clear the CCF flag, ERRC bit to clear the WERR and RDERR flags). An interrupt can be generated when one of the error flags (WERR or RDERR) is set if the error interrupt enable (ERRIE) bit in the AES_CR register has been previously set. If an error is detected, AES is not disabled by hardware and continues processing as normal. 728/1680 DocID024597 Rev 1 RM0351 25.12 Advanced encryption standard hardware accelerator (AES) Processing time The following tables summarize the time required to process a 128-bit block for each mode of operation. Table 139. Processing time (in clock cycle) Input phase Computation phase Output phase Total Mode 1: Encryption 8 202 4 214 Mode 2: Key derivation - 80 - 80 Mode 3: Decryption 8 202 4 214 Mode 4: Key derivation + decryption 8 276 4 288 Mode of operation Table 140. Processing time (in clock cycle) for ECB, CBC and CTR Key size Algorithm Input phase Computation phase Output phase Total ECB, CBC, CTR 8 202 4 214 - - 80 - 80 Mode 3: Decryption ECB, CBC, CTR 8 202 4 214 Mode 4: Key derivation + decryption ECB, CBC 8 276 4 288 Mode 1: Encryption ECB, CBC, CTR 8 286 4 298 - - 109 - 109 Mode 3: Decryption ECB, CBC, CTR 8 286 4 298 Mode 4: Key derivation + decryption ECB, CBC 8 380 4 392 Mode of operation Mode 1: Encryption 128-bit 256-bit Mode 2: Key derivation Mode 2: Key derivation Table 141. Processing time (in clock cycle) for GCM and CMAC Algorithm Init Phase Header phase Payload phase Tag phase GCM 215 67 202 202 - GMAC 215 67 - 202 - CMAC - 206 - 202 GCM 299 67 286 286 - GMAC 299 67 - 286 - CMAC - 290 - 286 Key size Mode of operation Mode 1: Encryption/ Mode 3: Decryption 128-bit Mode 1: Encryption/ Mode 3: Decryption 256-bit Note: Mode 2 and mode 4 has no meaning when GCM is selected. Mode operation (mode 1 to mode 4) has no meaning when GMAC/CMAC is used. DocID024597 Rev 1 729/1680 744 Advanced encryption standard hardware accelerator (AES) 25.13 RM0351 AES interrupts Table 142. AES interrupt requests Event flag Enable control bit Exit from Wait CCF CCFIE yes AES read error flag RDERR ERRIE yes AES write error flag WRERR ERRIE yes Interrupt event AES computation completed flag 730/1680 DocID024597 Rev 1 RM0351 Advanced encryption standard hardware accelerator (AES) 25.14 AES registers 25.14.1 AES control register (AES_CR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. KEY SIZE Res. CH MOD [2] 15 14 13 12 11 10 9 8 7 6 5 4 3 DMA OUT EN DMA INEN ERRIE CCFIE ERRC CCFC rw rw rw rw rw rw rw Res. GCMPH[1:0] rw rw CHMOD[1:0] MODE[1:0] rw rw rw rw 2 rw 1 0 DATATYPE[1:0] rw rw EN rw Bits 31:19 Reserved, must be kept at reset value. Bit 18 KEYSIZE: Key size selection 0: 128 bit key length 1: 256 bit key length The operation mode must only be changed if the AES is disabled. Writing these bits while the AES is enabled is forbidden in order to avoid unpredictable AES behavior. Bits 17, 15 Reserved, must be kept at reset value. Bits 14:13 GCMPH[1:0]: Used only for GCM, GMAC and CMAC algorithms and has no effect when other algorithms are selected 00: GCM init Phase 01: GCM header phase 10: GCM payload phase 11: GCM final phase Note: GCM init phase and GCM payload phase must not be used when CMAC is selected, else AES peripheral behavior is not guaranteed. Bit 12 DMAOUTEN: Enable DMA management of data output phase 0: DMA (during data output phase) disabled 1: DMA (during data output phase) enabled If the DMAOUTEN bit is set, DMA requests are generated for the output data phase in mode 1, 3 or 4. This bit has no effect in mode 2 (key derivation). Bit 11 DMAINEN: Enable DMA management of data input phase 0: DMA (during data input phase) disabled 1: DMA (during data input phase) enabled If the DMAINEN bit is set, DMA requests are generated for the data input phase in mode 1, 3 or 4. This bit has no action in mode 2 (key derivation). Bit 10 ERRIE: Error interrupt enable An interrupt is generated if at least one of the both flags RDERR or WRERR is set. 0: Error interrupt disabled 1: Error interrupt enabled DocID024597 Rev 1 731/1680 744 Advanced encryption standard hardware accelerator (AES) RM0351 Bit 9 CCFIE: CCF flag interrupt enable An interrupt is generated if the CCF flag is set. 0: CCF interrupt disabled 1: CCF interrupt enabled Bit 8 ERRC: Error clear Writing 1 to this bit clears the RDERR and WRERR flags. This bit is always read low. Bit 7 CCFC: Computation complete flag clear Writing 1 to this bit clears the CCF flag. This bit is always read low. Bit 16 and CHMOD[2:0]: AES chaining mode Bits 6:5 000: Electronic codebook (ECB) 001: Cipher block chaining (CBC) 010: Counter mode (CTR) 011: Galois counter mode (GCM) and Galois message authentication code (GMAC) 100: Cipher message authentication code (CMAC) The AES chaining mode must only be changed while the AES is disabled. Writing these bits while the AES is enabled is forbidden in order to avoid unpredictable AES behavior. Bits 4:3 MODE[1:0]: AES operating mode 00: Mode 1: Encryption 01: Mode 2: Key derivation 10: Mode 3: Decryption 11: Mode 4: Key derivation + decryption The operation mode must only be changed if the AES is disabled. Writing these bits while the AES is enabled is forbidden in order to avoid unpredictable AES behavior. Mode 4 is forbidden if CTR mode/GCM mode is selected. It will be forced to mode 3 if the software, nevertheless, attempts to set mode 4 for this CTR/GCM mode configuration. Bits 2:1 DATATYPE[1:0]: Data type selection (for data in and data out to/from the cryptographic block) 00: 32-bit data. No swapping. 01: 16-bit data or half-word. In the word, each half-word is swapped. For example, if one of the four 32-bit data written in the AES_DINR register is 0x764356AB, the value given to the cryptographic block is 0x56AB7643 10: 8-bit data or bytes. In the word, all the bytes are swapped. For example, if one of the four 32-bit data written in the AES_DINR register is 0x764356AB, the value given to the cryptographic block is 0xAB564376. 11: Bit data. In the word all the bits are swapped. For example, if one of the four 32-bit data written in the AES_DINR register is 0x764356AB, the value given to the cryptographic block is 0xD56AC26E The DATATYPE selection must be changed if the AES is disabled. Writing these bits while the AES is enabled is forbidden to avoid unpredictable AES behavior. Bit 0 EN: AES enable 0: AES disable 1: AES enable The AES can be re-initialized at any moment by resetting this bit: the AES is then ready to start processing a new block when EN is set. This bit is cleared by hardware when the AES computation is finished in mode 2 (key derivation) 732/1680 DocID024597 Rev 1 RM0351 25.14.2 Advanced encryption standard hardware accelerator (AES) AES status register (AES_SR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BUSY r WRERR RDERR r r CCF r Bits 31:4 Reserved, must be kept at reset value. Bit 3 Busy: Busy flag This bit is set and reset by hardware to indicate that higher priority message can interrupt the current message during GCM payload phase for encryption mode only 0: GCM suspend mode can perform 1: GCM suspend mode cannot perform Note: This bit has effect only when GCM algorithm is selected. Note: This flag has no effect when GCM is configured in GCM init phase, GCM header phase, GCM payload phase (decryption mode) and GCM final phase. DocID024597 Rev 1 733/1680 744 Advanced encryption standard hardware accelerator (AES) RM0351 Bit 2 WRERR: Write error flag This bit is set by hardware when an unexpected write operation to the AES_DINR register is detected (during computation or data output phase). An interrupt is generated if the ERRIE bit has been previously set in the AES_CR register. This flag has no impact on the AES which continues running even if WERR is set. It is cleared by software by setting the ERRC bit in the AES_CR register. 0: No write error detected 1: Write error detected Note: This Flags has no meaning when: – Key derivation mode is selected – GCM init phase Bit 1 RDERR: Read error flag This bit is set by hardware when an unexpected read operation from the AES_DOUTR register is detected (during computation or data input phase). An interrupt is generated if the ERRIE bit has been previously set in the AES_CR register.This flag has no impact on the AES which continues running even if RDERR is set. It is cleared by software by setting the ERRC bit i in the AES_CR register. 0: No read error detected 1: Read error detected Note: This Flags has no meaning when: – Key derivation mode is selected – GCM init phase is selected – GMAC or CMAC header phase is selected Bit 0 CCF: Computation complete flag This bit is set by hardware when the computation is complete. An interrupt is generated if the CCFIE bit has been previously set in the AES_CR register. It is cleared by software by setting the CCFC bit in the AES_CR register. 0: Computation is not complete 1: Computation complete Note: This bit is significant only when DMAOUTEN = 0. It may stay high when DMA_EN = 1. 734/1680 DocID024597 Rev 1 RM0351 Advanced encryption standard hardware accelerator (AES) 25.14.3 AES data input register (AES_DINR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DINR[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DINR[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 DINR[31:0]: Data input register This register must be written 4 times during the input phase: – In mode 1 (encryption), 4 words must be written which represent the plain text from MSB to LSB. – In mode 2 (key derivation), This register is not used because this mode concerns only derivative key calculation starting from the AES_KEYRx register. – In mode 3 (decryption) and 4 (Key derivation + decryption), 4 words must be written which represent the cipher text MSB to LSB. Note: This register must be accessed with 32-bit data width. 25.14.4 AES data output register (AES_DOUTR) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DOUTR[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r DOUTR[15:0] r r r r r r r r r Bits 31:0 DOUTR[31:0]: Data output register This register is read only. Once the CCF flag (computation complete flag) is set, reading this data register 4 times gives access to the 128-bit output results: – In mode 1 (encryption), the 4 words read represent the cipher text from MSB to LSB. – In mode 2 (key derivation), there is no need to read this register because the derivative key is located in the AES_KEYRx registers. – In mode 3 (decryption) and mode 4 (key derivation + decryption), the 4 words read represent the plain text from MSB to LSB. Note: This register must be accessed with 32-bit data width. DocID024597 Rev 1 735/1680 744 Advanced encryption standard hardware accelerator (AES) 25.14.5 RM0351 AES key register 0 (AES_KEYR0) (LSB: key [31:0]) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEYR0[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw KEYR0[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 KEYR0[31:0]: Data output register (LSB key [31:0]) This register must be written before the EN bit in the AES_CR register is set: In mode 1 (encryption), mode 2 (key derivation) and mode 4 (key derivation + decryption), the value to be written represents the encryption key from LSB, meaning key [31:0]. In mode 3 (decryption), the value to be written represents the decryption key from LSB, meaning key [31:0]. When the register is written with the encryption key in this decryption mode, reading it before the AES is enabled will return the encryption value. Reading it after CCF flag is set will return the derivation key. Reading this register while AES is enabled returns an unpredictable value. Note: This register does not contain the derivation key in mode 4 (derivation key + decryption). It always contains the encryption key value. 25.14.6 AES key register 1 (AES_KEYR1) (key[63:32]) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEYR1[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw KEYR1[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 KEYR1[31:0]: Data output register (key [63:32]) Refer to the description of AES_KEYR0. 736/1680 DocID024597 Rev 1 RM0351 25.14.7 Advanced encryption standard hardware accelerator (AES) AES key register 2 (AES_KEYR2) (key [95:64]) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEYR2[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw KEYR2[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 KEYR2[31:0]: Data output register (key [95:64]) Refer to the description of AES_KEYR0. 25.14.8 AES key register 3 (AES_KEYR3) (MSB: key[127:96]) Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEYR3[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw KEYR3[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 KEYR3[31:0]: Data output register (MSB key [127:96]) Refer to the description of AES_KEYR0. 25.14.9 AES initialization vector register 0 (AES_IVR0) (LSB: IVR[31:0]) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IVR0[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw IVR0[15:0] rw rw rw rw rw rw rw rw rw DocID024597 Rev 1 737/1680 744 Advanced encryption standard hardware accelerator (AES) RM0351 Bits 31:0 IVR0[31:0]: initialization vector register (LSB IVR[31:0]) This register must be written before the EN bit in the AES_CR register is set: The register value has no meaning if: – The ECB mode (electronic codebook) is selected. – The CTR or CBC mode is selected in addition with the key derivation. In CTR mode (counter mode), this register contains the 32-bit counter value. Reading this register while AES is enabled will return the value 0x00000000. 25.14.10 AES initialization vector register 1 (AES_IVR1) (IVR[63:32]) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IVR1[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw IVR1[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 IVR1[31:0]: Initialization vector register (IVR[63:32]) This register must be written before the EN bit in the AES_CR register is set: The register value has no meaning if: – The ECB mode (electronic codebook) is selected. – The CTR or CBC mode is selected in addition with the key derivation or key derivation + decryption mode. In CTR mode (counter mode), this register contains the nonce value. Reading this register while AES is enabled will return the value 0x00000000. 738/1680 DocID024597 Rev 1 RM0351 Advanced encryption standard hardware accelerator (AES) 25.14.11 AES initialization vector register 2 (AES_IVR2) (IVR[95:64]) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IVR2[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw IVR2[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 IVR2[31:0]: Initialization vector register (IVR[95:64]) This register must be written before the EN bit in the AES_CR register is set: The register value has no meaning if: – The ECB mode (electronic codebook) is selected. – The CTR or CBC mode is selected in addition with the key derivation or key derivation + decryption mode. In CTR mode (counter mode), this register contains the nonce value. Reading this register while AES is enabled will return the value 0x00000000. 25.14.12 AES initialization vector register 3 (AES_IVR3) (MSB: IVR[127:96]) Address offset: 0x2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IVR3[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw IVR3[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 IVR3[31:0]: Initialization vector register (MSB IVR[127:96]) This register must be written before the EN bit in the AES_CR register is set: The register value has no meaning if: – The ECB mode (electronic codebook) is selected. – The CTR or CBC mode is selected in addition with the key derivation or key derivation + decryption mode. In CTR mode (counter mode), this register contains the nonce value. Reading this register while AES is enabled will return the value 0x00000000. 25.14.13 AES key register 4 (AES_KEYR4) (key[159:128]) Address offset: 0x30 Reset value: 0x0000 0000 DocID024597 Rev 1 739/1680 744 Advanced encryption standard hardware accelerator (AES) 31 30 29 28 27 26 25 24 23 RM0351 22 21 20 19 18 17 16 KEYR431:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw KEYR4[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 KEYR4[31:0]: Data output register (key [159:128]) Same description as AES_KEYR0 for the key[159:128]. 25.14.14 AES key register 5 (AES_KEYR5) (key[191:160]) Address offset: 0x34 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEYR5[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw KEYR5[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 KEYR5[31:0]: Data output register (key [191:160]) Same description as AES_KEYR0 for the key[191:160]. 25.14.15 AES key register 6 (AES_KEYR6) (key[223:192]) Address offset: 0x38 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEYR631:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw KEYR615:0] rw rw rw rw rw rw rw rw rw Bits 31:0 KEYR6[31:0]: Data output register (key [223:192]) Same description as AES_KEYR0 for the key[223:192]. 25.14.16 AES key register 7 (AES_KEYR7) (MSB: key[255:224]) Address offset: 0x3C Reset value: 0x0000 0000 740/1680 DocID024597 Rev 1 RM0351 31 30 Advanced encryption standard hardware accelerator (AES) 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEYR731:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw KEYR7[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 KEYR7[31:0]: Data output register (MSB key [255:224]) Same description as AES_KEYR0 for the key[255:224]. Note: The key registers from 4 to 7 are used only when 256-bit key length is selected. These registers have no effect when 128-bit key length is selected (only key registers from 0 to 3 are used). DocID024597 Rev 1 741/1680 744 Advanced encryption standard hardware accelerator (AES) RM0351 25.14.17 AES Suspend registers (AES_SUSPxR) (x = 0..7) Address offset: 0x040 (AES_SUSP0R) to 0x05C (AES_SUSP7R) Reset value: 0x0000 0000 These registers contain the complete internal register states of the AES processor when the GCM/GMAC is selected, and are useful when a suspend has to be done because a highpriority task has to use the AES processor while it is already in use by another task. When such an event occurs, the AES_SUSP0..7R registers (when GCM/GMAC is selected) have to be read and the read values have to be saved somewhere in the memory space. Then the AES processor can be used by the preemptive task, and when AES computation is finished, the saved context can be read from memory and written back into their corresponding suspend registers. Note: 1 These registers are used only when GCM/GMAC algorithm mode is selected. 2 These registers can only be read when AES is enabled (Bit [0] set to 1 in AES_CR register), else reading these registers while AES is disabled will return the value 0x00000000. 31 30 29 28 27 26 25 24 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw AES_SUSPxR AES_SUSPxR rw rw rw rw rw rw rw rw rw 25.14.18 AES register map CCFIE ERRC CCFC 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. AES_DINR Reset value 0x000C 742/1680 0 0 0 0 AES_DINR[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_DOUTR Reset value CCF 0 RDERR 0 WRERR 0 Res. MODE[1:0] 0 BUSY 0 Reset value 0x0008 EN ERRIE 0 DATATYPE[1:0] DMAINEN 0 CHMOD[1:0] DMAOUTEN 0 GCMPH[1:0] 0 Res. Res. Res. 0 Res. Res. Res. CHMOD[2] Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AES_SR Res. 0x0004 0 Res. Reset value KEYSIZE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AES_CR Res. 0x0000 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 143. AES register map 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_DOUTR[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID024597 Rev 1 0 0 0 RM0351 Advanced encryption standard hardware accelerator (AES) Offset 0x0010 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 143. AES register map AES_KEYR0 AES_KEYR0[31:0] Reset value 0x0014 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_KEYR2[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_KEYR3[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_IVR0[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_IVR1[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_IVR2[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_IVR3[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_KEYR4[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_KEYR5[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_KEYR6[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_KEYR7[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_SUSP0R[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_SUSP1R Reset value 0 AES_KEYR1[31:0] AES_SUSP0R Reset value 0x0044 0 AES_KEYR7 Reset value 0x0040 0 AES_KEYR6 Reset value 0x003C 0 AES_KEYR5 Reset value 0x0038 0 AES_KEYR4 Reset value 0x0034 0 AES_IVR3 Reset value 0x0030 0 AES_IVR2 Reset value 0x002C 0 AES_IVR1 Reset value 0x0028 0 AES_IVR0 Reset value 0x0024 0 AES_KEYR3 Reset value 0x0020 0 AES_KEYR2 Reset value 0x001C 0 AES_KEYR1 Reset value 0x0018 0 0 0 0 0 0 0 AES_SUSP1R[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID024597 Rev 1 0 0 0 743/1680 744 Advanced encryption standard hardware accelerator (AES) RM0351 Offset 0x0048 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 143. AES register map AES_SUSP2R AES_SUSP2R[31:0] Reset value 0x004C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_SUSP4R[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_SUSP5R[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_SUSP6R[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_SUSP7R Reset value 0 AES_SUSP3R[31:0] AES_SUSP6R Reset value 0x005C 0 AES_SUSP5R Reset value 0x0058 0 AES_SUSP4R Reset value 0x0054 0 AES_SUSP3R Reset value 0x0050 0 0 0 0 0 0 0 AES_SUSP7R[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 for the register boundary addresses. 744/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) 26 Advanced-control timers (TIM1/TIM8) 26.1 TIM1/TIM8 introduction The advanced-control timers (TIM1/TIM8) consist of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. The advanced-control (TIM1/TIM8) and general-purpose (TIMx) timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 26.3.27. 26.2 TIM1/TIM8 main features TIM1/TIM8 timer features include: • 16-bit up, down, up/down auto-reload counter. • 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65536. • Up to 6 independent channels for: – Input Capture (but channels 5 and 6) – Output Compare – PWM generation (Edge and Center-aligned Mode) – One-pulse mode output • Complementary outputs with programmable dead-time • Synchronization circuit to control the timer with external signals and to interconnect several timers together. • Repetition counter to update the timer registers only after a given number of cycles of the counter. • 2 break inputs to put the timer’s output signals in a safe user selectable configuration. • Interrupt/DMA generation on the following events: – Update: counter overflow/underflow, counter initialization (by software or internal/external trigger) – Trigger event (counter start, stop, initialization or count by internal/external trigger) – Input capture – Output compare • Supports incremental (quadrature) encoder and Hall-sensor circuitry for positioning purposes • Trigger input for external clock or cycle-by-cycle current management DocID024597 Rev 1 745/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Figure 188. Advanced-control timer block diagram /ŶƚĞƌŶĂůĐůŽĐŬ;<ͺ/EdͿ <ͺd/DϭϴĨƌŽŵZ dZ& dZW WŽůĂƌŝƚLJƐĞůĞĐƚŝŽŶΘ ĞĚŐĞĚĞƚĞĐƚŽƌΘƉƌĞƐĐĂůĞƌ dZ d/DdžͺdZ /dZϬ /dZϭ /dZϮ /dZϯ dƌŝŐŐĞƌ ĐŽŶƚƌŽůůĞƌ dZ'K ƚŽŽƚŚĞƌƚŝŵĞƌƐƚŽͬ /ŶƉƵƚ ĨŝůƚĞƌ d'/ /dZ dZ dZ'/ d/ϭ&ͺ ^ůĂǀĞ ĐŽŶƚƌŽůůĞƌ ŵŽĚĞ ZĞƐĞƚ͕ĞŶĂďůĞ͕ƵƉͬĚŽǁŶ͕ĐŽƵŶƚ ŶĐŽĚĞƌ /ŶƚĞƌĨĂĐĞ d/ϭ&Wϭ d/Ϯ&WϮ ZWƌĞŐŝƐƚĞƌ h h/ ƵƚŽͲƌĞůŽĂĚƌĞŐŝƐƚĞƌ ZĞƉĞƚŝƚŝŽŶ ĐŽƵŶƚĞƌ ^ƚŽƉ͕ĐůĞĂƌŽƌƵƉͬĚŽǁŶ <ͺW^ yKZ d/ϭ d/Ddžͺ,ϭ d/Ϯ d/Ddžͺ,Ϯ d/ϯ d/Ddžͺ,ϯ d/ϰ d/Ddžͺ,ϰ d/ϭ&Wϭ /ŶƉƵƚĨŝůƚĞƌΘ d/ϭ&WϮ ĞĚŐĞĚĞƚĞĐƚŽƌ dZ d/Ϯ&Wϭ /ŶƉƵƚĨŝůƚĞƌΘ d/Ϯ&WϮ ĞĚŐĞĚĞƚĞĐƚŽƌ dZ /ŶƉƵƚĨŝůƚĞƌΘ ĞĚŐĞĚĞƚĞĐƚŽƌ d/ϯ&Wϯ d/ϯ&Wϰ <ͺEd W^ ƉƌĞƐĐĂůĞƌ ϭ/ h /ϭ WƌĞƐĐĂůĞƌ /ϭW^ Ϯ/ /Ϯ WƌĞƐĐĂůĞƌ /ŶƚĞƌŶĂůƐŽƵƌĐĞƐ EdĐŽƵŶƚĞƌ ϭ/ ĂƉƚƵƌĞͬŽŵƉĂƌĞϭƌĞŐŝƐƚĞƌ d'ƌĞŐŝƐƚĞƌƐ KϭZ& d' d/Ddžͺ,ϭ KƵƚƉƵƚ ĐŽŶƚƌŽů ĂƉƚƵƌĞͬŽŵƉĂƌĞϮƌĞŐŝƐƚĞƌ Kϭ d/Ddžͺ,ϭE KϭE Ϯ/ h /ϮW^ d/Ddžͺ,Ϯ KϮZ& d' KƵƚƉƵƚ ĐŽŶƚƌŽů KϮ d/Ddžͺ,ϮE KϮE ϯ/ h /ϯ WƌĞƐĐĂůĞƌ /ϯW^ dZ d/ϰ&Wϯ /ŶƉƵƚĨŝůƚĞƌΘ d/ϰ&Wϰ ĞĚŐĞĚĞƚĞĐƚŽƌ dZ нͬͲ h ϰ/ /ϰ WƌĞƐĐĂůĞƌ /ϰW^ ϯ/ ĂƉƚƵƌĞͬŽŵƉĂƌĞϯƌĞŐŝƐƚĞƌ d' ϰ/ h d/Ddžͺ,ϯ KϯZ& KƵƚƉƵƚ ĐŽŶƚƌŽů Kϯ d/Ddžͺ,ϯE KϯE ĂƉƚƵƌĞͬŽŵƉĂƌĞϰƌĞŐŝƐƚĞƌ KϰZ& KƵƚƉƵƚ Kϰ ĐŽŶƚƌŽů ĂƉƚƵƌĞͬŽŵƉĂƌĞϱƌĞŐŝƐƚĞƌ KϱZ& KƵƚƉƵƚ Kϱ ĐŽŶƚƌŽů ĂƉƚƵƌĞͬŽŵƉĂƌĞϲƌĞŐŝƐƚĞƌ KϲZ& KƵƚƉƵƚ Kϲ ĐŽŶƚƌŽů d/Ddžͺ,ϰ ^/& /& d/Ddžͺ@ 7,0[B60&5 (753 I'76 )LOWHU GRZQFRXQWHU 7RWKH2XWSXWPRGHFRQWUROOHU 7RWKH&.B36&FLUFXLWU\ 7RWKH6ODYHPRGHFRQWUROOHU (7)>@ 7,0[B60&5 069 The ETR input comes from multiple sources: input pins (default configuration), comparator outputs and analog watchdogs. The selection is done with the ETRSEL[2:0] bitfield in the TIMx_OR2 register and the TIMxOR1[1:0] and TIMxOR1[3:2] bitfields. Figure 210. TIM1 ETR input circuitry (75LQSXWVIURP $)FRQWUROOHU 7,0B25>@ (75OHJDF\PRGH &203 &203 1& 1& 1& 1& 1& 7,0B25>@ 1& $'&B$:' $'&B$:' $'&B$:' (75LQSXW 7,0B25>@ 1& $'&B$:' $'&B$:' $'&B$:' 069 762/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Figure 211. TIM8 ETR input circuitry (75LQSXWVIURP $)FRQWUROOHU 7,0B25>@ (75OHJDF\PRGH &203 &203 1& 1& 1& 1& 1& 7,0B25>@ 1& $'&B$:' $'&B$:' $'&B$:' (75LQSXW 7,0B25>@ 1& $'&B$:' $'&B$:' $'&B$:' 069 DocID024597 Rev 1 763/1680 849 Advanced-control timers (TIM1/TIM8) 26.3.5 RM0351 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Encoder mode Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 212 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. Figure 212. Control circuit in normal mode, internal clock divided by 1 ,QWHUQDOFORFN &(1 &17B(1 8* &17B,1,7 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 069 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. 764/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Figure 213. TI2 external clock connection example 7,0[B60&5 76>@ RU 7,) 7,) ,75[ 7,B(' 7, )LOWHU (GJH GHWHFWRU 7,)B5LVLQJ 7,)B)DOOLQJ 7,)3 7,)3 (75) RU RU [[ 75*, (75) &.B,17 ,&)>@ &&3 7,0[B&&05 7,0[B&&(5 LQWHUQDOFORFN (QFRGHU PRGH ([WHUQDOFORFN PRGH ([WHUQDOFORFN PRGH &.B36& ,QWHUQDOFORFN PRGH (&( 606>@ 7,0[B60&5 069 For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Note: 1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register. 2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). 3. Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER register. 4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register. 5. Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register. 6. Enable the counter by writing CEN=1 in the TIMx_CR1 register. The capture prescaler is not used for triggering, so you don’t need to configure it. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. DocID024597 Rev 1 765/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Figure 214. Control circuit in external clock mode 1 7, &17B(1 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. The Figure 215 gives an overview of the external trigger input block. Figure 215. External trigger input block RU 7,) 7,) (75 RU RU 75*, (75SLQ 'LYLGHU (753 I'76 )LOWHU GRZQFRXQWHU (75) &.B,17 (73 (736>@ (7)>@ 7,0[B60&5 7,0[B60&5 7,0[B60&5 LQWHUQDOFORFN (QFRGHU PRGH ([WHUQDOFORFN PRGH ([WHUQDOFORFN PRGH &.B36& ,QWHUQDOFORFN PRGH (&( 606>@ 7,0[B60&5 069 For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: 766/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) 1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. 2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register 3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register 4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register. 5. Enable the counter by writing CEN=1 in the TIMx_CR1 register. The counter counts once each 2 ETR rising edges. The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. Figure 216. Control circuit in external clock mode 2 I &.B,17 &17B(1 (75 (753 (75) &RXQWHUFORFN &.B,17 &.B36& &RXQWHUUHJLVWHU 069 DocID024597 Rev 1 767/1680 849 Advanced-control timers (TIM1/TIM8) 26.3.6 RM0351 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), an input stage for capture (with digital filter, multiplexing, and prescaler, except for channels 5 and 6) and an output stage (with comparator and output control). Figure 217 to Figure 220 give an overview of one Capture/Compare channel. The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). Figure 217. Capture/compare channel (example: channel 1 input stage) 7,)B(' 7RWKHVODYHPRGHFRQWUROOHU 7, I'76 7,)B5LVLQJ )LOWHU 7,) GRZQFRXQWHU (GJH GHWHFWRU 7,)B)DOOLQJ 7,)3 7,)3 ,&)>@ 7,0[B&&05 &&3&&13 7,0[B&&(5 7,)B5LVLQJ IURPFKDQQHO 7,)B)DOOLQJ IURPFKDQQHO 75& IURPVODYHPRGH FRQWUROOHU ,& ,&36 'LYLGHU &&6>@ ,&36>@ &&( 7,0[B&&05 7,0[B&&(5 069 The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. 768/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Figure 218. Capture/compare channel 1 main circuit $3%%XV LIELW 0&8SHULSKHUDOLQWHUIDFH 5HDG&&5/ UHDGBLQBSURJUHVV ORZ 5HDG&&5+ 6 KLJK &DSWXUHFRPSDUHSUHORDGUHJLVWHU 5 5 FRPSDUHBWUDQVIHU FDSWXUHBWUDQVIHU ,QSXW PRGH &&6>@ &&6>@ 6 ZULWH&&5+ ZULWHBLQBSURJUHVV 2XWSXW PRGH &&6>@ &&6>@ 2&3( &DSWXUHFRPSDUHVKDGRZUHJLVWHU 8(9 &RPSDUDWRU &DSWXUH ,&36 ZULWH&&5/ &&( &17!&&5 &RXQWHU IURPWLPH EDVHXQLW 2&3( 7,0B&&05 &17 &&5 &&* 7,0B(*5 069 Figure 219. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) 7,0[B60&5 2&&6 1& (75) 7RWKHPDVWHUPRGH FRQWUROOHU µ¶ RFUHIBFOUBLQW 2&5() &17!&&5 2XWSXW PRGH &17 &&5 FRQWUROOHU 2&[5() 2&5() 2&5()& 2&B'7 2XWSXW VHOHFWRU 'HDGWLPH JHQHUDWRU [ &&3 2XWSXW HQDEOH FLUFXLW 2& 2XWSXW HQDEOH FLUFXLW 2&1 7,0B&&(5 2&1B'7 µ¶ [ &&1( &&( 7,0B&&(5 2&&( 2&0>@ '7*>@ &&1( &&( &&13 02( 266, 2665 7,0B&&05 7,0B%'75 7,0B&&(5 7,0B&&(5 7,0B%'75 06Y9 1. OCxREF, where x is the rank of the complementary channel DocID024597 Rev 1 769/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Figure 220. Output stage of capture/compare channel (channel 4) 7,0[B60&5 2&&6 1& (75) 7RWKHPDVWHU PRGHFRQWUROOHU 2&5()& RFUHIBFOUBLQW &17!&&5 &17 &&5 2&5() 2XWSXW PRGH FRQWUROOHU µ¶ &&( &&3 2XWSXW VHOHFWRU 2&5() 7,0B&&(5 7,0B&&(5 7,0B&&05 2& &&( 7,0B&&(5 02( 2&0>@ 2&&( 2XWSXW HQDEOH FLUFXLW 266, 7,0B%'75 2,6 7,0B&5 06Y9 Figure 221. Output stage of capture/compare channel (channel 5, idem ch. 6) 7,0[B60&5 2&&6 1& (75) 7RWKHPDVWHU PRGHFRQWUROOHU RFUHIBFOUBLQW &17!&&5 &17 &&5 µ¶ 2XWSXW PRGH FRQWUROOHU 2&&( &&( &&3 7,0B&&(5 7,0B&&(5 2&5() 2&0>@ 2XWSXW HQDEOH FLUFXLW 2& &&( 7,0B&&(5 02( 266, 7,0B%'75 7,0B&&05 2,6 7,0B&5 06Y9 1. Not available externally. The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. 770/1680 DocID024597 Rev 1 RM0351 26.3.7 Advanced-control timers (TIM1/TIM8) Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: • Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only. • Program the input filter duration you need with respect to the signal you connect to the timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. • Select the edge of the active transition on the TI1 channel by writing CC1P and CC1NP bits to 0 in the TIMx_CCER register (rising edge in this case). • Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the TIMx_CCMR1 register). • Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register. • If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register. When an input capture occurs: • The TIMx_CCR1 register gets the value of the counter on the active transition. • CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared. • An interrupt is generated depending on the CC1IE bit. • A DMA request is generated depending on the CC1DE bit. In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data. Note: IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. DocID024597 Rev 1 771/1680 849 Advanced-control timers (TIM1/TIM8) 26.3.8 RM0351 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. • One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): • Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected). • Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P and CC1NP bits to ‘0’ (active on rising edge). • Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected). • Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P and CC2NP bits to CC2P/CC2NP=’10’ (active on falling edge). • Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register (TI1FP1 selected). • Configure the slave mode controller in reset mode: write the SMS bits to 0100 in the TIMx_SMCR register. • Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register. Figure 222. PWM input mode timing 7, 7,0[B&17 7,0[B&&5 7,0[B&&5 ,&FDSWXUH ,&FDSWXUH UHVHWFRXQWHU ,&FDSWXUH SXOVHZLGWK PHDVXUHPHQW ,&FDSWXUH SHULRG PHDVXUHPHQW DL 26.3.9 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, you just need to write 0101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. 772/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) For example: CCxP=0 (OCx active high) => OCx is forced to high level. The OCxREF signal can be forced low by writing the OCxM bits to 0100 in the TIMx_CCMRx register. Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below. 26.3.10 Output compare mode This function is used to control an output waveform or indicate when a period of time has elapsed. Channels 1 to 4 can be output, while Channel 5 and 6 are only available inside the microcontroller (for instance, for compound waveform generation or for ADC triggering). When a match is found between the capture/compare register and the counter, the output compare function: • Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=0000), be set active (OCxM=0001), be set inactive (OCxM=0010) or can toggle (OCxM=0011) on match. • Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register). • Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register). • Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection). The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register. In output compare mode, the update event UEV has no effect on OCxREF and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One Pulse mode). Procedure 1. Select the counter clock (internal, external, prescaler). 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. 3. Set the CCxIE bit if an interrupt request is to be generated. 4. Select the output mode. For example: 5. – Write OCxM = 0011 to toggle OCx output pin when CNT matches CCRx – Write OCxPE = 0 to disable preload register – Write CCxP = 0 to select active high polarity – Write CCxE = 1 to enable the output Enable the counter by setting the CEN bit in the TIMx_CR1 register. The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 223. DocID024597 Rev 1 773/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Figure 223. Output compare mode, toggle on OC1 :ULWH%KLQWKH&&5UHJLVWHU 7,0B&17 7,0B&&5 % $ % % % $ 2&5() 2& 0DWFKGHWHFWHGRQ&&5 ,QWHUUXSWJHQHUDWHGLIHQDEOHG 069 26.3.11 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘0110’ (PWM mode 1) or ‘0111’ (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register. As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers). Refer to the TIMx_CCER register description for more details. In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx ≤TIMx_CNT or TIMx_CNT ≤TIMx_CCRx (depending on the direction of the counter). The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. 774/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) PWM edge-aligned mode • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Upcounting mode on page 749. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 224 shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8. Figure 224. Edge-aligned PWM waveforms (ARR=8) &RXQWHUUHJLVWHU &&5[ 2&;5() &&[,) 2&;5() &&5[ &&[,) 2&;5() µ¶ &&5[! &&[,) 2&;5() µ¶ &&5[ &&[,) 069 • Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to the Downcounting mode on page 753 In PWM mode 1, the reference signal OCxRef is low as long as TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM is not possible in this mode. PWM center-aligned mode Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the DocID024597 Rev 1 775/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to the Center-aligned mode (up/down counting) on page 756. Figure 225 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. Figure 225. Center-aligned PWM waveforms (ARR=8) &RXQWHUUHJLVWHU 2&[5() &&5[ &06 &06 &06 &&[,) 2&[5() &&5[ &06 RU &&[,) 2&[5() µ¶ &&5[ &&[,) 2&[5() &&5[! µ¶ &06 &06 &06 &&[,) 2&[5() &&5[ &&[,) &06 &06 &06 µ¶ &06 &06 &06 $,E Hints on using center-aligned mode • 776/1680 When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • • 26.3.12 Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular: – The direction is not updated if you write a value in the counter that is greater than the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count up. – The direction is updated if you write 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated. The safest way to use center-aligned mode is to generate an update by software (setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running. Asymmetric PWM mode Asymmetric mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of TIMx_CCRx register. One register controls the PWM during up-counting, the second during down counting, so that PWM is adjusted every half PWM cycle: – OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2 – OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4 Asymmetric PWM mode can be selected independently on two channel (one OCx output per pair of CCR registers) by writing ‘1110’ (Asymmetric PWM mode 1) or ‘1111’ (Asymmetric PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones. When a given channel is used as asymmetric PWM channel, its complementary channel can also be used. For instance, if an OC1REFC signal is generated on channel 1 (Asymmetric PWM mode 1), it is possible to output either the OC2REF signal on channel 2, or an OC2REFC signal resulting from asymmetric PWM mode 1. Figure 226 represents an example of signals that can be generated using Asymmetric PWM mode (channels 1 to 4 are configured in Asymmetric PWM mode 1). Together with the deadtime generator, this allows a full-bridge phase-shifted DC to DC converter to be controlled. DocID024597 Rev 1 777/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Figure 226. Generation of 2 phase-shifted PWM signals with 50% duty cycle &RXQWHUUHJLVWHU &&5 &&5 &&5 &&5 2&5()& 2&5()& 069 26.3.13 Combined PWM mode Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and delay are determined by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or AND logical combination of two reference PWMs: – OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2 – OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4 Combined PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing ‘1100’ (Combined PWM mode 1) or ‘1101’ (Combined PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. When a given channel is used as combined PWM channel, its complementary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2). Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones. Figure 227 represents an example of signals that can be generated using Asymmetric PWM mode, obtained with the following configuration: 778/1680 – Channel 1 is configured in Combined PWM mode 2, – Channel 2 is configured in PWM mode 1, – Channel 3 is configured in Combined PWM mode 2, – Channel 4 is configured in PWM mode 1. DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Figure 227. Combined PWM mode on channel 1 and 3 2&¶ 2&¶ 2& 2& 2&5() 2&5() 2&5()¶ 2&5()¶ 2&5()& 2&5()&¶ 2&5()& 2&5()$1'2&5() 2&5()&¶ 2&5()¶252&5()¶ 069 26.3.14 Combined 3-phase PWM mode Combined 3-phase PWM mode allows one to three center-aligned PWM signals to be generated with a single programmable signal ANDed in the middle of the pulses. The OC5REF signal is used to define the resulting combined signal. The 3-bits GC5C[3:1] in the TIMx_CCR5 allow selection on which reference signal the OC5REF is combined. The resulting signals, OCxREFC, are made of an AND logical combination of two reference PWMs: – If GC5C1 is set, OC1REFC is controlled by TIMx_CCR1 and TIMx_CCR5 – If GC5C2 is set, OC2REFC is controlled by TIMx_CCR2 and TIMx_CCR5 – If GC5C3 is set, OC3REFC is controlled by TIMx_CCR3 and TIMx_CCR5 Combined 3-phase PWM mode can be selected independently on channels 1 to 3 by setting at least one of the 3-bits GC5C[3:1]. DocID024597 Rev 1 779/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Figure 228. 3-phase combined PWM signals with multiple trigger pulses per period 2& $55 2& 2& 2& 2& 2& &RXQWHU 2&UHI 2&UHI& *&&>@ 2&UHI& 2&UHI& 3UHORDG $FWLYH [[[ [[[ 2&UHI 2&UHI 75*2 069 The TRGO2 waveform shows how the ADC can be synchronized on given 3-phase PWM signals. Please refer to Section 26.3.27: ADC synchronization for more details. 26.3.15 Complementary outputs and dead-time insertion The advanced-control timers (TIM1/TIM8) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs. This time is generally known as dead-time and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of levelshifters, delays due to power switches...) You can select the polarity of the outputs (main output OCx or complementary OCxN) independently for each output. This is done by writing to the CCxP and CCxNP bits in the TIMx_CCER register. The complementary signals OCx and OCxN are activated by a combination of several control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx, OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to Table 147: Output control bits for complementary OCx and OCxN channels with break feature on page 825 for more details. In particular, the dead-time is activated when switching to the idle state (MOE falling down to 0). 780/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit dead-time generator for each channel. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high: • The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge. • The OCxN output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge. If the delay is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated. The following figures show the relationships between the output signals of the dead-time generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1, CCxE=1 and CCxNE=1 in these examples) Figure 229. Complementary output with dead-time insertion 2&[5() 2&[ GHOD\ 2&[1 GHOD\ 069 Figure 230. Dead-time waveforms with delay greater than the negative pulse 2&[5() 2&[ GHOD\ 2&[1 069 DocID024597 Rev 1 781/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Figure 231. Dead-time waveforms with delay greater than the positive pulse 2&[5() 2&[ 2&[1 GHOD\ 069 The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 26.4.18: TIM1/TIM8 break and deadtime register (TIMx_BDTR) on page 829 for delay calculation. Re-directing OCxREF to OCx or OCxN In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER register. This allows you to send a specific waveform (such as PWM or static active level) on one output while the complementary remains at its inactive level. Other alternative possibilities are to have both outputs at inactive level or both outputs active and complementary with dead-time. Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low. 26.3.16 Using the break function The purpose of the break function is to protect power switches driven by PWM signals generated with the TIM1 and TIM8 timers. The two break inputs are usually connected to fault outputs of power stages and 3-phase inverters. When activated, the break circuitry shuts down the PWM outputs and forces them to a predefined safe state. A number of internal MCU events can also be selected to trigger an output shut-down. The break features two channels. A break channel which gathers both system-level fault (clock failure, parity error,...) and application fault (from input pins and built-in comparator), and can force the outputs to a predefined level (either active or inactive) after a deadtime duration. A break2 channel which only includes application faults and is able to force the outputs to an inactive state. 782/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) The output enable signal and output levels during break are depending on several control bits: – the MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event. – the OSSI bit in the TIMx_BDTR register defines whether the timer controls the output in inactive state or releases the control to the GPIO controller (typically to have it in Hi-Z mode) – the OISx and OISxN bits in the TIMx_CR2 register which are setting the output shut-down level, either active or inactive. The OCx and OCxN outputs cannot be set both to active level at a given time, whatever the OISx and OISxN values. Refer to Table 147: Output control bits for complementary OCx and OCxN channels with break feature on page 825 for more details. When exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable the break functions by setting the BKE and BKE2 bits in the TIMx_BDTR register. The break input polarities can be selected by configuring the BKP and BKP2 bits in the same register. BKEx and BKPx can be modified at the same time. When the BKEx and BKPx bits are written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1 APB clock period to correctly read back the bit after the write operation. Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit (accessed in the TIMx_BDTR register). It results in some delays between the asynchronous and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you must insert a delay (dummy instruction) before reading it correctly. This is because you write the asynchronous signal and read the synchronous signal. The break can be generated from multiple sources which can be individually enabled and with programmable edge sensitivity, using the TIMx_OR2 and TIMx_OR3 registers. The source for break (BRK) channel is: • An external source connected to one of the BKIN pin (as per selection done in the AFIO controller), with polarity selection and optional digital filtering • An internal source: – the Cortex®-M4 LOCKUP output – the PVD output – the SRAM parity error signal – a flash ECC error – a clock failure event generated by the CSS detector – the output from a comparator, with polarity selection and optional digital filtering – the analog watchdog output of the DFSDM peripheral The source for break2 (BRK2) can be: • An external source connected to one of the BKIN pin (as per selection done in the AFIO controller), with polarity selection and optional digital filtering • An internal source coming from a comparator output. Break events can also be generated by software using BG and B2G bits in the TIMx_EGR register. DocID024597 Rev 1 783/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 All sources are ORed before entering the timer BRK or BRK2 inputs, as per Figure 232 below. Figure 232. Break and Break2 circuitry overview &RUH/RFNXS 39' /RFNXS/2&. 39'/2&. 6\VWHPEUHDNUHTXHVWV 5$0SDULW\(UURU (&&(UURU 6%,)IODJ 3DULW\/2&. (&&/2&. &66 %.,13 %.,1LQSXWV IURP$) FRQWUROOHU %.,1( 6RIWZDUHEUHDNUHTXHVWV%* %.&033 %.&03( &203RXWSXW %.)>@ %.( %,)IODJ %.3 %5.UHTXHVW )LOWHU %.&033 %.&03( &203RXWSXW $SSOLFDWLRQEUHDNUHTXHVWV %.')%.[( ')6'0 %5($.RXWSXW %.,13 %.,1LQSXWV IURP$) FRQWUROOHU %.,1( 6RIWZDUHEUHDNUHTXHVWV%* %.&033 %.&03( &203RXWSXW %.)>@ %.( %,)IODJ %.3 %5.UHTXHVW )LOWHU %.&033 &203RXWSXW ')6'0 %5($.RXWSXW %.&03( $SSOLFDWLRQEUHDNUHTXHVWV %.')%.[( 069 784/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) When one of the breaks occurs (selected level on one of the break inputs): Note: • The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or even releasing the control to the GPIO controller (selected by the OSSI bit). This feature is enabled even if the MCU oscillator is off. • Each output channel is driven with the level programmed in the OISx bit in the TIMx_CR2 register as soon as MOE=0. If OSSI=0, the timer releases the output control (taken over by the GPIO controller), otherwise the enable output remains high. • When complementary outputs are used: – The outputs are first put in inactive state (depending on the polarity). This is done asynchronously so that it works even if no clock is provided to the timer. – If the timer clock is still present, then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the OISx and OISxN bits after a dead-time. Even in this case, OCx and OCxN cannot be driven to their active level together. Note that because of the resynchronization on MOE, the dead-time duration is slightly longer than usual (around 2 ck_tim clock cycles). – If OSSI=0, the timer releases the output control (taken over by the GPIO controller which forces a Hi-Z state), otherwise the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high. • The break status flag (SBIF, BIF and B2IF bits in the TIMx_SR register) is set. An interrupt is generated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if the BDE bit in the TIMx_DIER register is set. • If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again at the next update event (UEV). As an example, this can be used to perform a regulation. Otherwise, MOE remains low until the application sets it to ‘1’ again. In this case, it can be used for security and you can connect the break input to an alarm from power drivers, thermal sensors or any security components. The break inputs are active on level. Thus, the MOE cannot be set while the break input is active (neither automatically nor by software). In the meantime, the status flag BIF and B2IF cannot be cleared. In addition to the break input and the output management, a write protection has been implemented inside the break circuit to safeguard the application. It allows to freeze the configuration of several parameters (dead-time duration, OCx/OCxN polarities and state when disabled, OCxM configurations, break enable and polarity). The application can choose from 3 levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to Section 26.4.18: TIM1/TIM8 break and dead-time register (TIMx_BDTR) on page 829. The LOCK bits can be written only once after an MCU reset. Figure 233 shows an example of behavior of the outputs in response to a break. DocID024597 Rev 1 785/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Figure 233. Various output behavior in response to a break event on BRK (OSSI = 1) %5($. 02( 2&[5() 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ GHOD\ GHOD\ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ GHOD\ GHOD\ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ 2&[1 &&[( &&[3 &&[1( &&[13 2,6[ 2,6[1 RU2,6[ 2,6[1 069 786/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) The two break inputs have different behaviors on timer outputs: – The BRK input can either disable (inactive state) or force the PWM outputs to a predefined safe state. – BRK2 can only disable (inactive state) the PWM outputs. The BRK has a higher priority than BRK2 input, as described in Table 144. Note: BRK2 must only be used with OSSR = OSSI = 1. Table 144. Behavior of timer outputs versus BRK/BRK2 inputs Typical use case BRK2 Timer outputs state Active Inactive BRK OCxN output (low side switches) OCx output (high side switches) X – Inactive then forced output state (after a deadtime) – Outputs disabled if OSSI = 0 (control taken over by GPIO logic) ON after deadtime insertion OFF Active Inactive OFF OFF Figure 234 gives an example of OCx and OCxN output behavior in case of active signals on BRK and BRK2 inputs. In this case, both outputs have active high polarities (CCxP = CCxNP = 0 in TIMx_CCER register). Figure 234. PWM output state following BRK and BRK2 pins assertion (OSSI=1) Z<Ϯ Z< Kdž ĞĂĚƚŝŵĞ ĞĂĚƚŝŵĞ /ͬKƐƚĂƚĞ ĐƚŝǀĞ /ŶĂĐƚŝǀĞ /ĚůĞ D^ϯϰϭϬϲsϭ DocID024597 Rev 1 787/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Figure 235. PWM output state following BRK assertion (OSSI=0) Z< /ͬKƐƚĂƚĞĚĞĨŝŶĞĚďLJƚŚĞ'W/KĐŽŶƚƌŽůůĞƌ;,/ͲͿ Kdž ĞĂĚƚŝŵĞ /ͬKƐƚĂƚĞĚĞĨŝŶĞĚďLJƚŚĞ'W/KĐŽŶƚƌŽůůĞƌ;,/ͲͿ /ͬKƐƚĂƚĞ ĐƚŝǀĞ /ŶĂĐƚŝǀĞ ŝƐĂďůĞĚ D^ϯϰϭϬϳsϭ 26.3.17 Bidirectional break inputs Beside regular digital break inputs and internal break events coming from the comparators, the timer 1 and 8 are featuring bidirectional break inputs/outputs combining the two sources, as represented on Figure 236. The TIMx_BKINy_COMPz pins are combining the COMPz output (to be configured in open drain) and the Timerx’s TIMx_BKINy input. They allow to have: - A global break information available for external MCUs or gate drivers shut down inputs, with a single-pin. - An internal comparator and multiple external open drain comparators outputs ORed together and triggering a break event, when the multiple internal and external break inputs must be merged. Figure 236. Output redirection %.,13 7RWKHWLPHUEUHDNLQSXW DFWLYHKLJK $), $)LQSXWHQDEOHG DFWLYHORZ 7,0[B%.,1\B&203] [ \ 1$] &203 $)2 $)RXWSXWFRQILJXUHGDVRSHQGUDLQ 069 26.3.18 Clearing the OCxREF signal on an external event The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1). OCxREF remains low until the next update event (UEV) occurs. This function can only be used in Output compare and PWM modes. It does not work in Forced mode. 788/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) OCREF_CLR_INPUT can be selected between the OCREF_CLR input and ETRF (ETR after the filter) by configuring the OCCS bit in the TIMx_SMCR register. The OCREF_CLR input is not connected (NC) in this product. The OCCS bit must be set to work in OCxREF clearing mode. When ETRF is chosen, ETR must be configured as follows: 1. The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR register set to ‘00’. 2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to ‘0’. 3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be configured according to the user needs. Figure 237 shows the behavior of the OCxREF signal when the ETRF Input becomes High, for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in PWM mode. Figure 237. Clearing TIMx OCxREF &&5[ &RXQWHU &17 (75) 2&[5() 2&[&( µ¶ 2&[5() 2&[&( µ¶ 2&[5()B&/5 EHFRPHVKLJK 2&[5()B&/5 VWLOOKLJK 069 Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at the next counter overflow. DocID024597 Rev 1 789/1680 849 Advanced-control timers (TIM1/TIM8) 26.3.19 RM0351 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time. COM can be generated by software by setting the COM bit in the TIMx_EGR register or by hardware (on TRGI rising edge). A flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can generate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request (if the COMDE bit is set in the TIMx_DIER register). The Figure 238 describes the behavior of the OCx and OCxN outputs when a COM event occurs, in 3 different examples of programmed configurations. Figure 238. 6-step generation, COM example (OSSR=1) &&5[ &RXQWHU &17 2&[5() :ULWH&20WR &20HYHQW &&[( ZULWH2&[0WR &&[1( 2&[0 IRUFHGLQDFWLYH &&[( &&[1( 2&[0 2&[ ([DPSOH 2&[1 2&[ :ULWH&&[1(WR DQG2&[0WR &&[( &&[1( 2&[0 IRUFHGLQDFWLYH &&[( &&[1( 2&[0 ([DPSOH 2&[1 ZULWH&&[1(WR &&[( DQG2&[0WR &&[1( 2&[0 IRUFHGLQDFWLYH &&[( &&[1( 2&[0 2&[ ([DPSOH 2&[1 DL 790/1680 DocID024597 Rev 1 RM0351 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be: • In upcounting: CNT < CCRx ≤ ARR (in particular, 0 < CCRx) • In downcounting: CNT > CCRx Figure 239. Example of one pulse mode. 7, 2&5() 2& 7,0B$55 &RXQWHU 26.3.20 Advanced-control timers (TIM1/TIM8) 7,0B&&5 W'(/$< W38/6( W 069 For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin. Let’s use TI2FP2 as trigger 1: • Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register. • TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER register. • Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in the TIMx_SMCR register. • TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register (trigger mode). DocID024597 Rev 1 791/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The tDELAY is defined by the value written in the TIMx_CCR1 register. • The tPULSE is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1). • Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1 register. You can optionally enable the preload registers by writing OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0’ in this example. In our example, the DIR and CMS bits in the TIMx_CR1 register should be low. You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected. Particular case: OCx fast enable: In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get. If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode. 26.3.21 Retriggerable one pulse mode (OPM) This mode allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length, but with the following differences with Non-retriggerable one pulse mode described in Section 26.3.20: – The pulse starts as soon as the trigger occurs (no programmable delay) – The pulse is extended if a new trigger occurs before the previous one is completed The timer must be in Slave mode, with the bits SMS[3:0] = ‘1000’ (Combined Reset + trigger mode) in the TIMx_SMCR register, and the OCxM[3:0] bits set to ‘1000’ or ‘1001’ for Retrigerrable OPM mode 1 or 2. If the timer is configured in Up-counting mode, the corresponding CCRx must be set to 0 (the ARR register sets the pulse length). If the timer is configured in Down-counting mode, the ARR must be set to 0 (the CCRx register sets the pulse length). Note: The OCxM[3:0] and SMS[3:0] bit fields are split into two parts for compatibility reasons, the most significant bit are not contiguous with the 3 least significant ones. In Retriggerable one pulse mode, the CCxIF flags are not significant. 792/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Figure 240. Retriggerable one pulse mode 75*, &RXQWHU 2XWSXW 069 26.3.22 Encoder interface mode To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and SMS=’011’ if it is counting on both TI1 and TI2 edges. Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. When needed, you can program the input filter as well. CC1NP and CC2NP must be kept low. The two inputs TI1 and TI2 are used to interface to an quadrature encoder. Refer to Table 145. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted, TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in TIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2. Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must configure TIMx_ARR before starting. in the same way, the capture, compare, prescaler, repetition counter, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together. In this mode, the counter is modified automatically following the speed and the direction of the quadrature encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same time. DocID024597 Rev 1 793/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Table 145. Counting direction versus encoder signals Active edge Level on opposite signal (TI1FP1 for TI2, TI2FP2 for TI1) TI1FP1 signal TI2FP2 signal Rising Falling Rising Falling Counting on TI1 only High Down Up No Count No Count Low Up Down No Count No Count Counting on TI2 only High No Count No Count Up Down Low No Count No Count Down Up Counting on TI1 and TI2 High Down Up Up Down Low Up Down Down Up A quadrature encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset. The Figure 241 gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following: • CC1S=’01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1). • CC2S=’01’ (TIMx_CCMR2 register, TI1FP2 mapped on TI2). • CC1P=’0’ and CC1NP=’0’ (TIMx_CCER register, TI1FP1 non-inverted, TI1FP1=TI1). • CC2P=’0’ and CC2NP=’0’ (TIMx_CCER register, TI1FP2 non-inverted, TI1FP2= TI2). • SMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling edges). • CEN=’1’ (TIMx_CR1 register, Counter enabled). Figure 241. Example of counter operation in encoder interface mode. IRUZDUG MLWWHU EDFNZDUG MLWWHU IRUZDUG 7, 7, &RXQWHU XS GRZQ XS 069 794/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Figure 242 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 242. Example of encoder interface mode with TI1FP1 polarity inverted. IRUZDUG MLWWHU EDFNZDUG MLWWHU IRUZDUG 7, 7, &RXQWHU GRZQ XS GRZQ 069 The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. You can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. You can do this by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a DMA request. The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the update interrupt flag (UIF) into the timer counter register’s bit 31 (TIMxCNT[31]). This allows both the counter value and a potential roll-over condition signaled by the UIFCPY flag to be read in an atomic way. It eases the calculation of angular speed by avoiding race conditions caused, for instance, by a processing shared between a background task (counter reading) and an interrupt (update interrupt). There is no latency between the UIF and UIFCPY flag assertions. In 32-bit timer implementations, when the IUFREMAP bit is set, bit 31 of the counter is overwritten by the UIFCPY flag upon read access (the counter’s most significant bit is only accessible in write mode). 26.3.23 UIF bit remapping The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update Interrupt Flag UIF into the timer counter register’s bit 31 (TIMxCNT[31]). This allows both the counter value and a potential roll-over condition signaled by the UIFCPY flag to be read in an atomic way. In particular cases, it can ease the calculations by avoiding race conditions, caused for instance by a processing shared between a background task (counter reading) and an interrupt (Update Interrupt). There is no latency between the UIF and UIFCPY flags assertion. DocID024597 Rev 1 795/1680 849 Advanced-control timers (TIM1/TIM8) 26.3.24 RM0351 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of an XOR gate, combining the two input pins TIMx_CH1 and TIMx_CH2. The XOR output can be used with all the timer input functions such as trigger or input capture. It is convenient to measure the interval between edges on two input signals, as per Figure 243 below. Figure 243. Measuring time interval between edges on 3 signals 7, 7, 7, ;25 7,0[ &RXQWHU 069 26.3.25 Interfacing with Hall sensors This is done using the advanced-control timers (TIM1 or TIM8) to generate PWM signals to drive the motor and another timer TIMx (TIM2, TIM3, TIM4) referred to as “interfacing timer” in Figure 244. The “interfacing timer” captures the 3 timer input pins (CC1, CC2, CC3) connected through a XOR to the TI1 input channel (selected by setting the TI1S bit in the TIMx_CR2 register). The slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus, each time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a time base triggered by any change on the Hall inputs. On the “interfacing timer”, capture/compare channel 1 is configured in capture mode, capture signal is TRC (See Figure 217: Capture/compare channel (example: channel 1 input stage) on page 768). The captured value, which corresponds to the time elapsed between 2 changes on the inputs, gives information about motor speed. The “interfacing timer” can be used in output mode to generate a pulse which changes the configuration of the channels of the advanced-control timer (TIM1 or TIM8) (by triggering a COM event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this, the interfacing timer channel must be programmed so that a positive pulse is generated after a programmed delay (in output compare or PWM mode). This pulse is sent to the advanced-control timer (TIM1 or TIM8) through the TRGO output. 796/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Example: you want to change the PWM configuration of your advanced-control timer TIM1 after a programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers. • Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the TIMx_CR2 register to ‘1’, • Program the time base: write the TIMx_ARR to the max value (the counter must be cleared by the TI1 change. Set the prescaler to get a maximum counter period longer than the time between 2 changes on the sensors, • Program the channel 1 in capture mode (TRC selected): write the CC1S bits in the TIMx_CCMR1 register to ‘01’. You can also program the digital filter if needed, • Program the channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to ‘111’ and the CC2S bits to ‘00’ in the TIMx_CCMR1 register, • Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 register to ‘101’, In the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the timer is programmed to generate PWM signals, the capture/compare control signals are preloaded (CCPC=1 in the TIMx_CR2 register) and the COM event is controlled by the trigger input (CCUS=1 in the TIMx_CR2 register). The PWM control bits (CCxE, OCxM) are written after a COM event for the next step (this can be done in an interrupt subroutine generated by the rising edge of OC2REF). The Figure 244 describes this example. DocID024597 Rev 1 797/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Figure 244. Example of Hall sensor interface 7,+ ,QWHUIDFLQJWLPHU 7,+ 7,+ &RXQWHU &17 &&5 &&5 &$ &$ & &$ &$% & $GYDQFHGFRQWUROWLPHUV 7,0 7,0 75*2 2&5() &20 2& 2&1 2& 2&1 2& 2&1 :ULWH&&[(&&[1( DQG2&[0IRUQH[WVWHS DL 798/1680 DocID024597 Rev 1 RM0351 26.3.26 Advanced-control timers (TIM1/TIM8) Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. They can be synchronized in several modes: Reset mode, Gated mode, and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated. In the following example, the upcounter is cleared in response to a rising edge on TI1 input: • Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect rising edges only). • Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. • Start the counter by writing CEN=1 in the TIMx_CR1 register. The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register). The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. Figure 245. Control circuit in reset mode 7, 8* &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 DocID024597 Rev 1 799/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write CC1P=1 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect low level only). • Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. • Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level). The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops. The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input. Figure 246. Control circuit in Gated mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: • 800/1680 Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 register. DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). • Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 247. Control circuit in trigger mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 Slave mode: Combined reset + trigger mode In this case, a rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers, and starts the counter. This mode is used for one-pulse mode. Slave mode: external clock mode 2 + trigger mode The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input (in reset mode, gated mode or trigger mode). It is recommended not to select ETR as TRGI through the TS bits of TIMx_SMCR register. In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs: DocID024597 Rev 1 801/1680 849 Advanced-control timers (TIM1/TIM8) 1. 2. 3. RM0351 Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: – ETF = 0000: no filter – ETPS=00: prescaler disabled – ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2. Configure the channel 1 as follows, to detect rising edges on TI: – IC1F=0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S=01in TIMx_CCMR1 register to select only the input capture source – CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect rising edge only). Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on ETR rising edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input. Figure 248. Control circuit in external clock mode 2 + trigger mode 7, &(1&17B(1 (75 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 7,) 069 Note: 802/1680 The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. DocID024597 Rev 1 RM0351 26.3.27 Advanced-control timers (TIM1/TIM8) ADC synchronization The timer can generate an ADC triggering event with various internal signals, such as reset, enable or compare events. It is also possible to generate a pulse issued by internal edge detectors, such as: – Rising and falling edges of OC4ref – Rising edge on OC5ref or falling edge on OC6ref The triggers are issued on the TRGO2 internal line which is redirected to the ADC. There is a total of 16 possible events, which can be selected using the MMS2[3:0] bits in the TIMx_CR2 register. An example of an application for 3-phase motor drives is given in Figure 228 on page 780. Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. Note: The clock of the ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the timer. 26.3.28 DMA burst mode The TIMx timers have the capability to generate multiple DMA requests upon a single event. The main purpose is to be able to re-program part of the timer multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals. The DMA controller destination is unique and must point to the virtual register TIMx_DMAR. On a given timer event, the timer launches a sequence of DMA requests (burst). Each write into the TIMx_DMAR register is actually redirected to one of the timer registers. The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers (either in half-words or in bytes). The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register: Example: 00000: TIMx_CR1 00001: TIMx_CR2 00010: TIMx_SMCR As an example, the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) upon an update event, with the DMA transferring half words into the CCRx registers. This is done in the following steps: DocID024597 Rev 1 803/1680 849 Advanced-control timers (TIM1/TIM8) 1. RM0351 Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers. – Number of data to transfer = 3 (See note below). – Circular mode disabled. 2. Configure the DCR register by configuring the DBA and DBL bit fields as follows: DBL = 3 transfers, DBA = 0xE. 3. Enable the TIMx update DMA request (set the UDE bit in the DIER register). 4. Enable TIMx 5. Enable the DMA channel This example is for the case where every CCRx register to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer should be 6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4. 26.3.29 Debug mode When the microcontroller enters debug mode (Cortex®-M4 core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module. For more details, refer to Section 44.16.2: Debug support for timers, RTC, watchdog, bxCAN and I2C. 804/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) 26.4 TIM1/TIM8 registers Refer to for a list of abbreviations used in register descriptions. 26.4.1 TIM1/TIM8 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 Res. 14 Res. 13 Res. 12 11 10 Res. UIFRE MAP Res. rw 9 8 CKD[1:0] rw 7 6 ARPE rw rw 5 CMS[1:0] rw rw 4 3 2 1 0 DIR OPM URS UDIS CEN rw rw rw rw rw Bits 15:12 Reserved, must be kept at reset value. Bit 11 UIFREMAP: UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. Bit 10 Reserved, must be kept at reset value. Bits 9:8 CKD[1:0]: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx), 00: tDTS=tCK_INT 01: tDTS=2*tCK_INT 10: tDTS=4*tCK_INT 11: Reserved, do not program this value Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered Bits 6:5 CMS[1:0]: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) Bit 4 DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. DocID024597 Rev 1 805/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 26.4.2 TIM1/TIM8 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 23 21 20 MMS2[3:0] rw rw 6 15 14 13 12 11 10 9 8 7 Res. OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 TI1S rw rw rw rw rw rw rw rw 806/1680 22 rw rw 5 4 MMS[2:0] rw DocID024597 Rev 1 rw rw 19 18 17 16 Res. OIS6 Res. OIS5 rw rw 3 2 1 0 CCDS CCUS Res. CCPC rw rw rw RM0351 Advanced-control timers (TIM1/TIM8) Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 MMS2[3:0]: Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: 0000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset. 0001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register). 0010: Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer. 0011: Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2). 0100: Compare - OC1REF signal is used as trigger output (TRGO2) 0101: Compare - OC2REF signal is used as trigger output (TRGO2) 0110: Compare - OC3REF signal is used as trigger output (TRGO2) 0111: Compare - OC4REF signal is used as trigger output (TRGO2) 1000: Compare - OC5REF signal is used as trigger output (TRGO2) 1001: Compare - OC6REF signal is used as trigger output (TRGO2) 1010: Compare Pulse - OC4REF rising or falling edges generate pulses on TRGO2 1011: Compare Pulse - OC6REF rising or falling edges generate pulses on TRGO2 1100: Compare Pulse - OC4REF or OC6REF rising edges generate pulses on TRGO2 1101: Compare Pulse - OC4REF rising or OC6REF falling edges generate pulses on TRGO2 1110: Compare Pulse - OC5REF or OC6REF rising edges generate pulses on TRGO2 1111: Compare Pulse - OC5REF rising or OC6REF falling edges generate pulses on TRGO2 Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. Bit 19 Reserved, must be kept at reset value. Bit 18 OIS6: Output Idle state 6 (OC6 output) Refer to OIS1 bit Bit 17 Reserved, must be kept at reset value. Bit 16 OIS5: Output Idle state 5 (OC5 output) Refer to OIS1 bit Bit 15 Reserved, must be kept at reset value. Bit 14 OIS4: Output Idle state 4 (OC4 output) Refer to OIS1 bit Bit 13 OIS3N: Output Idle state 3 (OC3N output) Refer to OIS1N bit Bit 12 OIS3: Output Idle state 3 (OC3 output) Refer to OIS1 bit DocID024597 Rev 1 807/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Bit 11 OIS2N: Output Idle state 2 (OC2N output) Refer to OIS1N bit Bit 10 OIS2: Output Idle state 2 (OC2 output) Refer to OIS1 bit Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). Bit 8 OIS1: Output Idle state 1 (OC1 output) 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) Bits 6:4 MMS[1:0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). 100: Compare - OC1REF signal is used as trigger output (TRGO) 101: Compare - OC2REF signal is used as trigger output (TRGO) 110: Compare - OC3REF signal is used as trigger output (TRGO) 111: Compare - OC4REF signal is used as trigger output (TRGO) Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. Bit 3 CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs 808/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI Note: This bit acts only on channels that have a complementary output. Bit 1 Reserved, must be kept at reset value. Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). Note: This bit acts only on channels that have a complementary output. 26.4.3 TIM1/TIM8 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SMS[3] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ETP ECE rw rw rw ETPS[1:0] rw rw ETF[3:0] rw rw rw MSM rw rw TS[2:0] rw rw OCCS rw rw 0 SMS[2:0] rw rw rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 SMS[3]: Slave mode selection - bit 3 Refer to SMS description - bits2:0 Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge. 1: ETR is inverted, active at low level or falling edge. Bit 14 ECE: External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=111). 2: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 111). 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. DocID024597 Rev 1 809/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Bits 13:12 ETPS[1:0]: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8 Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 Bit 7 MSM: Master/slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. Bits 6:4 TS[2:0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: External Trigger input (ETRF) See Table 146: TIMx internal trigger connection on page 811 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. Bit 3 OCCS: OCREF clear selection This bit is used to select the OCREF clear source. 0: OCREF_CLR_INT is not connected (reserved configuration) 1: OCREF_CLR_INT is connected to ETRF 810/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 0000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock. 0001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. 0010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. 0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. Codes above 1000: Reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. Table 146. TIMx internal trigger connection Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011) TIM1 TIM15 TIM2 TIM3 TIM4 TIM8 TIM1 TIM2 TIM4 TIM5 DocID024597 Rev 1 811/1680 849 Advanced-control timers (TIM1/TIM8) 26.4.4 RM0351 TIM1/TIM8 DMA/interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 Res. TDE rw 13 12 11 10 9 COMDE CC4DE CC3DE CC2DE CC1DE rw rw rw rw rw 8 7 6 5 4 3 2 1 0 UDE BIE TIE COMIE CC4IE CC3IE CC2IE CC1IE UIE rw rw rw rw rw rw rw rw rw Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled Bit 13 COMDE: COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled 1: CC4 DMA request enabled Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled 1: CC3 DMA request enabled Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled Bit 7 BIE: Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled 1: Trigger interrupt enabled Bit 5 COMIE: COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled Bit 4 CC4IE: Capture/Compare 4 interrupt enable 0: CC4 interrupt disabled 1: CC4 interrupt enabled Bit 3 CC3IE: Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled 1: CC3 interrupt enabled 812/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 26.4.5 TIM1/TIM8 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. C6IF C5IF rc_w0 rc_w0 15 14 13 Res. Res. SBIF rc_w0 12 11 10 9 CC4OF CC3OF CC2OF CC1OF rc_w0 rc_w0 rc_w0 rc_w0 8 7 6 5 4 3 2 1 0 B2IF BIF TIF COMIF CC4IF CC3IF CC2IF CC1IF UIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 31:18 Reserved, must be kept at reset value. Bit 17 CC6IF: Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output) Bit 16 CC5IF: Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output) Bits 15:14 Reserved, must be kept at reset value. Bit 13 SBIF: System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation. 0: No break event occurred. 1: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. Bit 12 CC4OF: Capture/Compare 4 overcapture flag Refer to CC1OF description Bit 11 CC3OF: Capture/Compare 3 overcapture flag Refer to CC1OF description Bit 10 CC2OF: Capture/Compare 2 overcapture flag Refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set DocID024597 Rev 1 813/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Bit 8 B2IF: Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. 0: No break event occurred. 1: An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register. Bit 7 BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred. 1: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending. Bit 5 COMIF: COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. 0: No COM event occurred. 1: COM interrupt pending. Bit 4 CC4IF: Capture/Compare 4 interrupt flag Refer to CC1IF description Bit 3 CC3IF: Capture/Compare 3 interrupt flag Refer to CC1IF description Bit 2 CC2IF: Capture/Compare 2 interrupt flag Refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow (in downcounting mode) If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity) 814/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. – When CNT is reinitialized by a trigger event (refer to Section 26.4.3: TIM1/TIM8 slave mode control register (TIMx_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 26.4.6 TIM1/TIM8 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. B2G BG TG COMG CC4G CC3G CC2G CC1G UG w w w w w w w w w Bits 15:9 Reserved, must be kept at reset value. Bit 8 B2G: Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled. Bit 7 BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits Note: This bit acts only on channels having a complementary output. Bit 4 CC4G: Capture/Compare 4 generation Refer to CC1G description Bit 3 CC3G: Capture/Compare 3 generation Refer to CC1G description DocID024597 Rev 1 815/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Bit 2 CC2G: Capture/Compare 2 generation Refer to CC1G description Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). 26.4.7 TIM1/TIM8 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. OC2M[3] Res. Res. Res. Res. Res. Res. Res. OC1M[3] Res. 15 14 OC2 CE 13 12 OC2M[2:0] IC2F[3:0] rw rw rw 11 10 OC2 PE OC2 FE 9 Res. 8 CC2S[1:0] 7 6 OC1 CE rw rw IC1F[3:0] rw rw rw rw Output compare mode: Bits 31:25 Reserved, must be kept at reset value. Bit 24 OC2M[3]: Output Compare 2 mode - bit 3 Bits 23:17 Reserved, must be kept at reset value. Bits16 OC1M[3]: Output Compare 1 mode - bit 3 Refer to OC1M description on bits 6:4 816/1680 4 OC1M[2:0] IC2PSC[1:0] rw 5 DocID024597 Rev 1 rw 3 2 OC1 PE OC1 FE 1 0 CC1S[1:0] IC1PSC[1:0] rw rw rw rw rw RM0351 Advanced-control timers (TIM1/TIM8) Bit 15 OC2CE: Output Compare 2 clear enable Bits 14:12 OC2M[2:0]: Output Compare 2 mode Bit 11 OC2PE: Output Compare 2 preload enable Bit 10 OC2FE: Output Compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER). Bit 7 OC1CE: Output Compare 1 clear enable OC1CE: Output Compare 1 Clear Enable 0: OC1Ref is not affected by the ETRF Input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input DocID024597 Rev 1 817/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). 0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0100: Force inactive level - OC1REF is forced low. 0101: Force active level - OC1REF is forced high. 0110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (OC1REF=’1’). 0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT TIMx_CCR1 else inactive. 1000: Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 1001: Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 1010: Reserved, 1011: Reserved, 1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. 818/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. Bit 2 OC1FE: Output Compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER). Input capture mode Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER). DocID024597 Rev 1 819/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events Bits 1:0 CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER). 820/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) 26.4.8 TIM1/TIM8 capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 0000 Refer to the above CCMR1 register description. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. OC4M[3] Res. Res. Res. Res. Res. Res. Res. OC3M[3] Res. Res. rw 15 14 OC4 CE 13 12 OC4M[2:0] IC4F[3:0] rw rw rw 11 10 OC4 PE OC4 FE 9 rw 8 CC4S[1:0] 7 6 OC3 CE. rw rw 4 OC3M[2:0] IC4PSC[1:0] rw 5 IC3F[3:0] rw rw rw rw rw 3 2 OC3 PE OC3 FE 1 0 CC3S[1:0] IC3PSC[1:0] rw rw rw rw rw Output compare mode Bits 31:25 Reserved, must be kept at reset value. Bit 24 OC4M[3]: Output Compare 4 mode - bit 3 Bits 23:17 Reserved, must be kept at reset value. Bit 16 OC3M[3]: Output Compare 3 mode - bit 3 Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Bit 11 OC4PE: Output compare 4 preload enable Bit 10 OC4FE: Output compare 4 fast enable Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER). Bit 7 OC3CE: Output compare 3 clear enable Bits 6:4 OC3M: Output compare 3 mode Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER). DocID024597 Rev 1 821/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Input capture mode Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER). Bits 7:4 IC3F: Input capture 3 filter Bits 3:2 IC3PSC: Input capture 3 prescaler Bits 1:0 CC3S: Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER). 26.4.9 TIM1/TIM8 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC6P CC6E Res. Res. CC5P CC5E rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CC4NP Res. CC4P CC4E CC3P CC3E CC2P CC2E CC1P CC1E rw rw rw rw rw rw rw rw rw CC3NP CC3NE rw rw CC2NP CC2NE rw rw Bits 31:22 Reserved, must be kept at reset value. Bit 21 CC6P: Capture/Compare 6 output polarity Refer to CC1P description Bit 20 CC6E: Capture/Compare 6 output enable Refer to CC1E description Bits 19:18 Reserved, must be kept at reset value. Bit 17 CC5P: Capture/Compare 5 output polarity Refer to CC1P description Bit 16 CC5E: Capture/Compare 5 output enable Refer to CC1E description 822/1680 DocID024597 Rev 1 CC1NP CC1NE rw rw RM0351 Advanced-control timers (TIM1/TIM8) Bit 15 CC4NP: Capture/Compare 4 complementary output polarity Refer to CC1NP description Bit 14 Reserved, must be kept at reset value. Bit 13 CC4P: Capture/Compare 4 output polarity Refer to CC1P description Bit 12 CC4E: Capture/Compare 4 output enable Refer to CC1E description Bit 11 CC3NP: Capture/Compare 3 complementary output polarity Refer to CC1NP description Bit 10 CC3NE: Capture/Compare 3 complementary output enable Refer to CC1NE description Bit 9 CC3P: Capture/Compare 3 output polarity Refer to CC1P description Bit 8 CC3E: Capture/Compare 3 output enable Refer to CC1E description Bit 7 CC2NP: Capture/Compare 2 complementary output polarity Refer to CC1NP description Bit 6 CC2NE: Capture/Compare 2 complementary output enable Refer to CC1NE description Bit 5 CC2P: Capture/Compare 2 output polarity Refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable Refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high. 1: OC1N active low. CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (channel configured as output). Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated. Bit 2 CC1NE: Capture/Compare 1 complementary output enable 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated. DocID024597 Rev 1 823/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. 00: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). 01: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). 10: reserved, do not use this configuration. 11: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. Bit 0 CC1E: Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled. 1: Capture enabled. Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated. 824/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Table 147. Output control bits for complementary OCx and OCxN channels with break feature Output states(1) Control bits MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit 1 0 0 Output disabled (not driven by the timer: Hi-Z) OCx=0, OCxN=0 0 0 1 Output disabled (not driven OCxREF + Polarity by the timer: Hi-Z) OCxN = OCxREF xor CCxNP OCx=0 0 1 0 OCxREF + Polarity OCx=OCxREF xor CCxP Output Disabled (not driven by the timer: Hi-Z) OCxN=0 X 1 1 OCREF + Polarity + deadtime Complementary to OCREF (not OCREF) + Polarity + dead-time 1 0 1 Off-State (output enabled with inactive state) OCx=CCxP OCxREF + Polarity OCxN = OCxREF x or CCxNP 1 1 0 OCxREF + Polarity OCx=OCxREF xor CCxP Off-State (output enabled with inactive state) OCxN=CCxNP X X 0 0 0 1 1 0 1 1 X 1 OCxN output state X 0 0 OCx output state X Output Disabled (not driven by the timer: Hi-Z) OCx=CCxP, OCxN=CCxNP Off-State (output enabled with inactive state) Asynchronously: OCx=CCxP, OCxN=CCxNP (if BRK or BRK2 is triggered). Then (this is valid only if BRK is triggered), if the clock is present: OCx=OISx and OCxN=OISxN after a dead-time, assuming that OISx and OISxN do not correspond to OCX and OCxN both in active state (may cause a short circuit when driving switches in half-bridge configuration). Note: BRK2 can only be used if OSSI = OSSR = 1. 1. When both outputs of a channel are not used (control taken over by GPIO), the OISx, OISxN, CCxP and CCxNP bits must be kept cleared. Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIO registers. DocID024597 Rev 1 825/1680 849 Advanced-control timers (TIM1/TIM8) 26.4.10 RM0351 TIM1/TIM8 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UIFCPY Res. Res. Res. Res. Res. Res. Res. Re s. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw r CNT[15:0] rw Bit 31 UIFCPY: UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0. Bits 30:16 Reserved, must be kept at reset value. Bits 15:0 CNT[15:0]: Counter value 26.4.11 TIM1/TIM8 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PSC[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). 26.4.12 TIM1/TIM8 auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ARR[15:0] rw Bits 15:0 ARR[15:0]: Prescaler value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 26.3.1: Time-base unit on page 747 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 826/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) 26.4.13 TIM1/TIM8 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw REP[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 REP[15:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to: the number of PWM periods in edge-aligned mode the number of half PWM period in center-aligned mode. 26.4.14 TIM1/TIM8 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR1[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output:: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1 is configured as input:: CR1 is the counter value transferred by the last input capture 1 event (IC1). DocID024597 Rev 1 827/1680 849 Advanced-control timers (TIM1/TIM8) 26.4.15 RM0351 TIM1/TIM8 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR2[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). 26.4.16 TIM1/TIM8 capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR3[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CCR3[15:0]: Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3 is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). 828/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) 26.4.17 TIM1/TIM8 capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR4[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. If channel CC4 is configured as input: CCR4 is the counter value transferred by the last input capture 4 event (IC4). 26.4.18 TIM1/TIM8 break and dead-time register (TIMx_BDTR) Address offset: 0x44 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 R e s. Res. Res. Res. Res. Res. BK2P BK2E rw rw rw rw rw rw rw rw rw rw 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw 15 14 13 12 11 10 MOE AOE BKP BKE OSSR OSSI rw rw rw rw rw rw Note: 23 22 21 LOCK[1:0] rw rw 20 19 BK2F[3:0] 18 17 16 BKF[3:0] DTG[7:0] rw As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. Bits 31:26 Reserved. Bit 25 BK2P: Break 2 polarity 0: Break input BRK2 is active low 1: Break input BRK2 is active high Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. DocID024597 Rev 1 829/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Bit 24 BK2E: Break 2 enable This bit enables the complete break 2 protection (including all sources connected to bk_acth and BKIN sources, as per). 0: Break2 function disabled 1: Break2 function enabled Note: The BRKIN2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. Bits 23:20 BK2F[3:0]: Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, BRK2 acts asynchronously 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 19:16 BKF[3:0]: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, BRK acts asynchronously 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 830/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Bit 15 MOE: Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. 0: In response to a break 2 event. OC and OCN outputs are disabled In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. 1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register). See OC/OCN enable description for more details (Section 26.4.9: TIM1/TIM8 capture/compare enable register (TIMx_CCER) on page 822). Bit 14 AOE: Automatic output enable 0: MOE can be set only by software 1: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. Bit 12 BKE: Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per). 0: Break function disabled 1: Break function enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. Bit 11 OSSR: Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 26.4.9: TIM1/TIM8 capture/compare enable register (TIMx_CCER) on page 822). 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state). 1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). DocID024597 Rev 1 831/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Bit 10 OSSI: Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (Section 26.4.9: TIM1/TIM8 capture/compare enable register (TIMx_CCER) on page 822). 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state). 1: When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output. Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). Bits 9:8 LOCK[1:0]: Lock configuration These bits offer a write protection against software errors. 00: LOCK OFF - No bit is write protected. 01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS. DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS. DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS. DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS. Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 832/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) 26.4.19 TIM1/TIM8 DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 15 14 13 Res. Res. Res. 12 11 10 9 8 DBL[4:0] rw rw rw rw 7 6 5 Res. Res. Res. rw 4 3 2 1 0 rw rw DBA[4:0] rw rw rw Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). 00000: 1 transfer 00001: 2 transfers 00010: 3 transfers ... 10001: 18 transfers Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIM2_CR1. – If DBL = 7 bytes and DBA = TIM2_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data will be copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: – If you configure the DMA Data Size in half-words, 16-bit data will be transferred to each of the 7 registers. – If you configure the DMA Data Size in bytes, the data will also be transferred to 7 registers: the first register will contain the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, you also have to specify the size of data transferred by DMA. Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 DBA[4:0]: DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: TIMx_SMCR, ... DocID024597 Rev 1 833/1680 849 Advanced-control timers (TIM1/TIM8) 26.4.20 RM0351 TIM1/TIM8 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DMAB[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 26.4.21 TIM1 option register 1 (TIM1_OR1) Address offset: 0x50 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI1_R MP rw ETR_ADC3_RMP rw rw ETR_ADC1_RMP rw rw Bits 31:5 Reserved, must be kept at reset value Bit 4 TI1_RMP: Input Capture 1 remap 0: TIM1 input capture 1 is connected to I/O 1: TIM1 input capture 1 is connected to COMP1 output. Bits 3:2 ETR_ADC3_RMP: External trigger remap on ADC3 analog watchdog 00: TIM1_ETR is not connected to ADC3 AWDx. This configuration must be selected when the ETR comes from the I/O. 01: TIM1_ETR is connected to ADC3 AWD1. 10: TIM1_ETR is connected to ADC3 AWD2. 11: TIM1_ETR is connected to ADC3 AWD3. Note: ADC3 AWDx sources are ‘ORed’ with the TIM1_ETR input signals. When ADC3 AWDx is used, it is necessary to make sure that the corresponding TIM1_ETR input pin is not enabled in the alternate function controller. Refer to Figure 210: TIM1 ETR input circuitry. 834/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Bits 1:0 ETR_ADC1_RMP: External trigger remap on ADC1 analog watchdog 00 : TIM1_ETR is not connected to ADC1 AWDx. This configuration must be selected when the ETR comes from the I/O. 01 : TIM1_ETR is connected to ADC1 AWD1. 10 : TIM1_ETR is connected to ADC1 AWD2. 11 : TIM1_ETR is connected to ADC1 AWD3. Note: ADC1 AWDx sources are ‘ORed’ with the TIM1_ETR input signals. When ADC1 AWDx is used, it is necessary to make sure that the corresponding TIM1_ETR input pin is not enabled in the alternate function controller. Refer to Figure 210: TIM1 ETR input circuitry. 26.4.22 TIM8 option register 1 (TIM8_OR1) Address offset: 0x50 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. TI1_ RMP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw ETR_ADC3_RMP rw rw ETR_ADC2_RMP rw rw Bits 31:5 Reserved, must be kept at reset value Bit 4 TI1_RMP: Input Capture 1 remap 0: TIM8 input capture 1 is connected to I/O 1: TIM8 input capture 1 is connected to COMP2 output. Bits 3:2 ETR_ADC3_RMP: External trigger remap on ADC3 analog watchdog 00: TIM8_ETR is not connected to ADC3 AWDx. This configuration must be selected when the ETR comes from the I/O. 01: TIM8_ETR is connected to ADC3 AWD1. 10: TIM8_ETR is connected to ADC3 AWD2. 11: TIM8_ETR is connected to ADC3 AWD3. Note: ADC3 AWDx sources are ‘ORed’ with the TIM8_ETR input signals. When ADC3 AWDx is used, it is necessary to make sure that the corresponding TIM8_ETR input pin is not enabled in the alternate function controller. Refer to Figure 211: TIM8 ETR input circuitry. Bits 1:0 ETR_ADC2_RMP: External trigger remap on ADC1 analog watchdog 00 : TIM8_ETR is not connected to ADC2 AWDx. This configuration must be selected when the ETR comes from the I/O. 01 : TIM8_ETR is connected to ADC2 AWD1. 10 : TIM8_ETR is connected to ADC2 AWD2. 11 : TIM8_ETR is connected to ADC2 AWD3. Note: ADC2 AWDx sources are ‘ORed’ with the TIM8_ETR input signals. When ADC2 AWDx is used, it is necessary to make sure that the corresponding TIM8_ETR input pin is not enabled in the alternate function controller. Refer to Figure 211: TIM8 ETR input circuitry. DocID024597 Rev 1 835/1680 849 Advanced-control timers (TIM1/TIM8) 26.4.23 RM0351 TIM1/TIM8 capture/compare mode register 3 (TIMx_CCMR3) Address offset: 0x54 Reset value: 0x0000 0000 Refer to the above CCMR1 register description. Channels 5 and 6 can only be configured in output. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. OC6M[3] Res. Res. Res. Res. Res. Res. Res. OC5M[3] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. OC5 CE. Res. Res. rw OC6 CE rw OC6M[2:0] rw rw rw OC6 PE OC6FE rw rw Res. rw OC5M[2:0] rw rw rw OC5PE OC5FE rw rw rw Output compare mode Bits 31:25 Reserved, must be kept at reset value. Bit 24 OC6M[3]: Output Compare 6 mode - bit 3 Bits 23:17 Reserved, must be kept at reset value. Bit 16 OC5M[3]: Output Compare 5 mode - bit 3 Bit 15 OC6CE: Output compare 6 clear enable Bits 14:12 OC6M: Output compare 6 mode Bit 11 OC6PE: Output compare 6 preload enable Bit 10 OC6FE: Output compare 6 fast enable Bits 9:8 Reserved, must be kept at reset value. Bit 7 OC5CE: Output compare 5 clear enable Bits 6:4 OC5M: Output compare 5 mode Bit 3 OC5PE: Output compare 5 preload enable Bit 2 OC5FE: Output compare 5 fast enable Bits 1:0 Reserved, must be kept at reset value. 26.4.24 TIM1/TIM8 capture/compare register 5 (TIMx_CCR5) Address offset: 0x58 Reset value: 0x0000 0000 31 30 29 GC5C3 GC5C2 GC5C1 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw CCR5[15:0] 836/1680 rw rw DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Bit 31 GC5C3: Group Channel 5 and Channel 3 Distortion on Channel 3 output: 0: No effect of OC5REF on OC3REFC 1: OC3REFC is the logical AND of OC3REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals. Bit 30 GC5C2: Group Channel 5 and Channel 2 Distortion on Channel 2 output: 0: No effect of OC5REF on OC2REFC 1: OC2REFC is the logical AND of OC2REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. Bit 29 GC5C1: Group Channel 5 and Channel 1 Distortion on Channel 1 output: 0: No effect of OC5REF on OC1REFC5 1: OC1REFC is the logical AND of OC1REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. Bits 28:16 Reserved, must be kept at reset value. Bits 15:0 CCR5[15:0]: Capture/Compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC5 output. DocID024597 Rev 1 837/1680 849 Advanced-control timers (TIM1/TIM8) 26.4.25 RM0351 TIM1/TIM8 capture/compare register 6 (TIMx_CCR6) Address offset: 0x5C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR6[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CCR6[15:0]: Capture/Compare 6 value CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC6 output. 26.4.26 TIM1 option register 2 (TIM1_OR2) Address offset: 0x60 Reset value: 0x0000 0001 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 Res. 25 Res. 24 Res. 23 Res. 22 Res. 21 Res. 20 Res. 19 Res. 18 Res. 17 16 Res. ETR SEL [2] rw 15 14 ETRSEL[1:0] rw rw 13 Res. 12 Res. 11 10 9 8 BK BK BKDFB BKINP CMP2P CMP1P K0E rw rw rw 7 Res. 6 Res. rw 5 Res. 4 Res. 3 Res. 2 1 0 BK BK BKINE CMP2E CMP1E rw rw rw Bits 31:17 Reserved, must be kept at reset value Bits 16:14 ETRSEL[2:0]: ETR source selection This bit selects the ETR input source. 000: ETR legacy mode 001: COMP1 output connected to ETR input 010: COMP2 output connected to ETR input Other codes reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 13:12 Reserved, must be kept at reset value Bit 11 BKCMP2P: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP2 input is active high 1: COMP2 input is active low Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 838/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Bit 10 BKCMP1P: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active high 1: COMP1 input is active low Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 9 BKINP: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active high 1: BKIN input is active low Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 8 BKDFBK0E: BRK DFSDM_BREAK[0] enable This bit enables the DFSDM_BREAK[0] for the timer’s BRK input. DFSDM_BREAK[0] output is ‘ORed’ with the other BRK sources. 0: DFSDM_BREAK[0] input disabled 1: DFSDM_BREAK[0] input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 7:3 Reserved, must be kept at reset value Bit 2 BKCMP2E: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is ‘ORed’ with the other BRK sources. 0: COMP2 input disabled 1: COMP2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 1 BKCMP1E: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is ‘ORed’ with the other BRK sources. 0: COMP1 input disabled 1: COMP1 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 0 BKINE: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is ‘ORed’ with the other BRK sources. 0: BKIN input disabled 1: BKIN input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Refer to Figure 210: TIM1 ETR input circuitry and to Figure 232: Break and Break2 circuitry overview. DocID024597 Rev 1 839/1680 849 Advanced-control timers (TIM1/TIM8) 26.4.27 RM0351 TIM1 option register 3 (TIM1_OR3) Address offset: 0x64 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. BK2C MP2P BK2C MP1P Res. Res. Res. Res. Res. rw rw BK2IN BK2DFB P K1E rw rw BK2CMP BK2CM 2E P1E rw rw BK2INE rw Bits 31:12 Reserved, must be kept at reset value Bit 11 BK2CMP2P: BRK2 COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP2 polarity bit. 0: COMP2 input is active low 1: COMP2 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 10 BK2CMP1P: BRK2 COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP2 polarity bit. 0: COMP1 input is active low 1: COMP1 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 9 BK2INP: BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BKP2 polarity bit. 0: BKIN2 input is active low 1: BKIN2 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 8 BK2DFBK1E: BRK2 DFSDM_BREAK[1] enable This bit enables the DFSDM_BREAK[1] for the timer’s BRK2 input. DFSDM_BREAK[1] output is ‘ORed’ with the other BRK2 sources. 0: DFSDM_BREAK[1] input disabled 1: DFSDM_BREAK[1] input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 7:3 Reserved, must be kept at reset value Bit 2 BK2CMP2E: BRK2 COMP2 enable This bit enables the COMP2 for the timer’s BRK2 input. COMP2 output is ‘ORed’ with the other BRK2 sources. 0: COMP2 input disabled 1: COMP2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 840/1680 DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) Bit 1 BK2CMP1E: BRK2 COMP1 enable This bit enables the COMP1 for the timer’s BRK2 input. COMP1 output is ‘ORed’ with the other BRK2 sources. 0: COMP1 input disabled 1: COMP1 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 0 BK2INE: BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timer’s BRK2 input. BKIN2 input is ‘ORed’ with the other BRK2 sources. 0: BKIN2 input disabled 1: BKIN2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Refer to Figure 232: Break and Break2 circuitry overview. 26.4.28 TIM8 option register 2 (TIM8_OR2) Address offset: 0x60 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ETRSEL [2] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 rw ETRSEL[1:0] rw rw Res. Res. BKDFBK BKCM BKCM BKINP 2E P2P P1P rw rw rw Res. Res. rw Res. Res. Res. BKCMP2 BKCMP E 1E rw rw 0 BKINE rw Bits 31:17 Reserved, must be kept at reset value Bits 16:14 ETRSEL[2:0]: ETR source selection This bit selects the ETR input source. 000: ETR legacy mode 001: COMP1 output connected to ETR input 010: COMP2 output connected to ETR input Other codes reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 13:12 Reserved, must be kept at reset value Bit 11 BKCMP2P: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP2 input is active high 1: COMP2 input is active low Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). DocID024597 Rev 1 841/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Bit 10 BKCMP1P: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active high 1: COMP1 input is active low Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 9 BKINP: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active high 1: BKIN input is active low Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 8 BKDFBK2E: BRK DFSDM_BREAK[2] enable This bit enables the DFSDM_BREAK[2] for the timer’s BRK input. DFSDM_BREAK[2] output is ‘ORed’ with the other BRK sources. 0: DFSDM_BREAK[2] input disabled 1: DFSDM_BREAK[2] input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 7:3 Reserved, must be kept at reset value Bit 2 BKCMP2E: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is ‘ORed’ with the other BRK sources. 0: COMP2 input disabled 1: COMP2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 1 BKCMP1E: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is ‘ORed’ with the other BRK sources. 0: COMP1 input disabled 1: COMP1 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 0 BKINE: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is ‘ORed’ with the other BRK sources. 0: BKIN input disabled 1: BKIN input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: 842/1680 Refer to Figure 211: TIM8 ETR input circuitry and to Figure 232: Break and Break2 circuitry overview. DocID024597 Rev 1 RM0351 Advanced-control timers (TIM1/TIM8) 26.4.29 TIM8 option register 3 (TIM8_OR3) Address offset: 0x64 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. BK2C MP2P BK2C MP1P Res. Res. Res. Res. Res. rw rw BK2IN BK2DFB P K3E rw rw BK2CMP BK2CM 2E P1E rw rw BK2INE rw Bits 31:12 Reserved, must be kept at reset value Bit 11 BK2CMP2P: BRK2 COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP2 polarity bit. 0: COMP2 input is active low 1: COMP2 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 10 BK2CMP1P: BRK2 COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP2 polarity bit. 0: COMP1 input is active low 1: COMP1 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 9 BK2INP: BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BKP2 polarity bit. 0: BKIN2 input is active low 1: BKIN2 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 8 BK2DFBK3E: BRK2 DFSDM_BREAK[3] enable This bit enables the DFSDM_BREAK[3] for the timer’s BRK2 input. DFSDM_BREAK[3] output is ‘ORed’ with the other BRK2 sources. 0: DFSDM_BREAK[3] input disabled 1: DFSDM_BREAK[3] input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 7:3 Reserved, must be kept at reset value Bit 2 BK2CMP2E: BRK2 COMP2 enable This bit enables the COMP2 for the timer’s BRK2 input. COMP2 output is ‘ORed’ with the other BRK2 sources. 0: COMP2 input disabled 1: COMP2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). DocID024597 Rev 1 843/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Bit 1 BK2CMP1E: BRK2 COMP1 enable This bit enables the COMP1 for the timer’s BRK2 input. COMP1 output is ‘ORed’ with the other BRK2 sources. 0: COMP1 input disabled 1: COMP1 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 0 BK2INE: BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timer’s BRK2 input. BKIN2 input is ‘ORed’ with the other BRK2 sources. 0: BKIN2 input disabled 1: BKIN2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Refer to Figure 232: Break and Break2 circuitry overview. 26.4.30 TIM1 register map TIM1 registers are mapped as 16-bit addressable registers as described in the table below: URS UDIS CEN 0 0 0 Res CCPC ARPE 0 CCUS 0 DIR OIS2 OIS1N 0 OPM OIS2N 0 0 CCDS OIS3 TI1S OIS3N OIS1 Res Res OIS4 Res 0 0 0 0 MMS [2:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIE UIF 0 0 0 0 0 0 0 0 UG CC1IE CC1IF 0 CC1G CC2IE CC2IF 0 CC2G CC3IE CC3IF 0 CC3G CC4IE CC4IF 0 COM COMIE COMIF 0 CC4G TIE TIF BIE 0 TG UDE 0 BIF 0 B2IF 0 BG CC1DE 0 B2G CC2DE 0 CC1OF 0 CC2OF 0 Res 0 Res CC3DE 0 CC3OF 0 Res CC4DE 0 CC4OF 0 Res COMDE 0 SBIF 0 Res TDE SMS[2:0] Res TS[2:0] 0 Res Res DocID024597 Rev 1 Res 0 Res C5IF 0 ETF[3:0] OCCS 0 MSM ECE 0 ETP 0 Res ETP S [1:0] 0 0 Reset value 844/1680 0 0 0 0 C6IF Res Res Res Res Res Res Res Res Res Res Res Res TIM1_EGR Res 0x14 Res Reset value 0 0 0 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM1_SR 0 0 Reset value 0x10 0 CMS [1:0] SMS[3] Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM1_DIER CKD [1:0] Res Res Res 0 Reset value 0x0C OIS5 Res OIS6 Res 0 Res 0 Res 0 Res 0 Res Res Res Res Res Res Res TIM1_SMCR Res 0x08 0 Res Reset value MMS2[3:0] Res Res Res Res Res Res Res TIM1_CR2 Res 0x04 Res Reset value UIFREMAP Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM1_CR1 Res 0x00 Register Res Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 148. TIM1 register map and reset values 0 0 0 0 0 0 0 0 0 RM0351 Advanced-control timers (TIM1/TIM8) OC1FE OC2FE OC1CE OC2PE OC1PE 0 0 0 CC3 S [1:0] 0 0 CC3P CC3E CC2NP 0 0 0 0 0 0 CC1E CC3NE 0 CC1P 0 CC1NE 0 CC2E 0 CC1NP 0 CC2P 0 CC2NE 0 CC4E CC3 S [1:0] CC3NP IC3 PSC [1:0] CC4P IC3F[3:0] OC3FE 0 OC3PE OC4CE Res 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT[15:0] 0 0 0 0 0 0 0 0 0 PSC[15:0] 0 0 0 0 0 0 0 0 0 ARR[15:0] 0 0 0 0 0 0 0 0 0 REP[15:0] 0 0 0 0 0 0 0 0 0 CCR1[15:0] 0 0 0 0 0 0 0 0 0 CCR2[15:0] 0 0 0 0 0 0 0 0 0 CCR3[15:0] 0 0 0 0 0 0 0 0 0 CCR4[15:0] 0 DocID024597 Rev 1 0 0 0 Res Res Res Res Res Reset value OC3M [2:0] 0 CC1 S [1:0] 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM1_CCR4 Res 0x40 0 0 0 0 Res Reset value 0 0 0 IC1 PSC [1:0] 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM1_CCR3 Res 0x3C 0 0 0 0 0 Res Reset value CC4 S [1:0] CC4 S [1:0] Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM1_CCR2 0 0 0 0 0 Res Reset value 0x38 0 0 IC1F[3:0] 0 IC4 PSC [1:0] Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM1_CCR1 0 0 0 0 Res Reset value 0x34 0 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM1_RCR 0 0 0 0 0 Res Reset value 0x30 0 0 CC2 S [1:0] Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM1_ARR 0 0 CC1 S [1:0] 0 0 Res Reset value 0x2C OC4M [2:0] 0 IC2 PSC [1:0] OC1M [2:0] Res CC5E 0 0 0 OC3CE OC3M[3] CC5P 0 Res Res Res Res Res CC6E 0 Res CC6P Res Res Res Res Res Res Res Res TIM1_PSC 0 0 IC4F[3:0] 0 Res 0 Res Reset value Res UIFCPY 0x28 TIM1_CNT Res 0x24 Res Reset value Res Res Res Res Res Res Res Res Res Res Res TIM1_CCER 0 CC2 S [1:0] Res Res Res Res Res Res Res Res Res Res Res Res 0 Reset value 0x20 0 0 Res Res Res Res Res Res Res Res OC4M[3] Res Res Res Res Res Res Res 0 Res Reset value TIM1_CCMR2 Input Capture mode Res 0x1C Res TIM1_CCMR2 Output Compare mode 0 IC2F[3:0] 0 Res Reset value 0 OC4FE OC2CE 0 OC2M [2:0] OC4PE OC1M[3] Res Res Res Res Res Res Res Res 0 Res Res Res Res Res Res Res Res Res Res Res Res OC2M[3] Res Res Res Res Res 0 Res Reset value TIM1_CCMR1 Input Capture mode Res 0x18 Res TIM1_CCMR1 Output Compare mode Res Register Res Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 148. TIM1 register map and reset values (continued) 0 0 0 0 0 0 0 0 0 845/1680 849 0x64 846/1680 TIM1_OR3 0 0 0 0 0 0 TIM1_OR2 ETRSEL [2:0] Res Res DocID024597 Rev 1 Res Res Res Res 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR6[15:0] 0 0 0 0 0 Refer to Section 2.2.2 on page 68 for the register boundary addresses. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKINE 0 BKCMP1E 0 TI1_RMP 0 DMAB[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 Res Res Res Res Res Res Res Res Res BKE OSSR OSSI Res Res Res 0 ETR_ADC1_RMP ETR_ADC3_RMP Res 0 0 0 1 BK2INE 0 Res Res 0 BK2CMP1E Res 0 0 Res CCR5[15:0] OC5FE 0 0 OC5PE 0 0 OC5M [2:0] Res 0 Res 0 0 BKCMP2E 0 Res Res DBL[4:0] 0 BK2CMP2E 0 Res 0 0 Res OC6M [2:0] 0 0 Res 0 LOC K [1:0] Res 0 0 0 Res 0 0 Res 0 0 OC5CE Reset value BKDFBK0E 0 Res 0 Res 0 BK2DFBK1E 0 Res 0 Res 0 Res BKP 0 OC6FE 0 Res AOE 0 OC6PE 0 Res MOE 0 BKINP Reset value 0 Res Reset value Res Res Res Res Res Res Res Res 0 BKCMP1P OC6CE Res Res Res Res Res Res Res BK2E 0 BK2INP OC5M[3] Res Res Res Res Res Res Res Res 0 BK2CMP1P Res Res Res Res Res Res Res Res Res BK2P Res Res 0 Res Res Res 0 BKCMP2P Res Res Res Res Res Res Res Res OC6M[3] Res Res Res Res 0 BK2CMP2P Res Res Res Res Res Res Res Res Res Res Res Res 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res 0 Res 0 Res Res Res Res Res Res Res Res Res Res TIM1_BDTR BKF[3:0] Res 0 Res Reset value Res 0 Res Res 0 Res Res 0 Res Res Res Res Res Res Res Res Register BK2F[3:0] Res Res Res Res Res Res 0 Res Res Res Reset value Res 0 Res Res Res Res Res Res Reset value Res 0 Res Res Res GC5C1 TIM1_CCR6 Res 0 Res 0 Res Reset value Res 0 Res 0x60 Reset value Res TIM1_CCMR3 Output Compare mode Res TIM1_OR1 Res TIM1_DMAR Res 0x5C TIM1_CCR5 GC5C2 0x58 GC5C3 0x50 Res 0x4C Res 0x54 TIM1_DCR Res 0x48 Res 0x44 Res Offset Res Advanced-control timers (TIM1/TIM8) RM0351 Table 148. TIM1 register map and reset values (continued) DT[7:0] 0 0 0 DBA[4:0] 0 0 1 0x20 TIM8_CCER 0 0 DocID024597 Rev 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC3E CC2NP CC2NE CC2P CC2E CC1NP CC1NE CC1P CC1E 0 0 CC3P 0 0 CC3NE Reset value CC3NP 0 0 0 0 0 0 0 IC2F[3:0] 0 0 OC4M [2:0] 0 0 IC4F[3:0] UIF 0 0 0 0 0 UG UIE CC1IF 0 CC1G CC1IE CC2IF 0 CC2G OIS2 OIS1N 0 0 ETF[3:0] 0 IC2 PSC [1:0] 0 CC2 S [1:0] 0 0 0 0 0 0 0 0 CC4 S [1:0] 0 0 IC4 PSC [1:0] CC4 S [1:0] 0 0 0 0 0 0 0 0 0 0 Res UIFREMAP Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res ARPE DIR URS UDIS CEN 0 0 0 0 CCUS Res CCPC 0 OPM MMS [2:0] 0 CCDS 0 0 0 0 0 0 0 0 0 0 CC2 S [1:0] OC1M [2:0] 0 0 IC1F[3:0] 0 0 OC3M [2:0] 0 0 IC3F[3:0] OC1FE CC2IE CC3IF 0 CC3G OIS2N 0 TI1S OIS3 0 OIS1 OIS3N 0 MSM OIS4 Res OIS5 Res OIS6 Res 0 0 OC1PE CC3IE CC4IF CC4IE COMIF COMIE TIF 0 COM BIF Reset value B2IF 0 CC1OF 0 CC2OF 0 Res 0 Res 0 CC3OF 0 Res 0 CC4OF 0 Res 0 SBIF 0 Res 0 0 CC4G 0 TIE 0 0 0 TG 0 BIE 0 UDE 0 0 0 BG 0 0 0 B2G 0 0 0 OC1CE 0 CC1DE 0 CC2DE 0 Res Res Res 0 0 OC3FE 0 0 0 CMS [1:0] OC3PE 0 OC2FE 0 ETP S [1:0] CKD [1:0] OC3CE 0 OC2M [2:0] OC4FE 0 CC3DE Reset value OC2PE 0 CC4DE 0 COMDE ECE 0 TDE ETP 0 Res Res SMS[3] 0 Res Res Res Res Res 0 Res Res C5IF Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value OC4PE Reset value CC4E OC2CE C6IF Res Res 0 CC4P OC1M[3] Res Res Res 0 Res OC4CE 0 Res 0 OC3M[3] Res Res Res Res Res Res Res Reset value Res Res Res Res Res Res Res Res Res Res Res Res 0 Res CC5E Res Res Res Res Reset value CC5P Res Res Res Res Res Res Res Res Res Res Res Res 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Res Res Res Res OC2M[3] Res Res Res Res Res Res Res MMS2[3:0] Res CC6E Res Res Res Res Res Res Res Res Res Res Res 0 Res Res Res OC4M[3] Res Res Res Res Res Res Res 0 Res Res Reset value Res Res Res Res Res Res Reset value Res Res Res Res Res Res Res Reset value CC6P Reset value Res TIM8_CCMR2 Input Capture mode Res 0x1C Res TIM8_CCMR2 Output Compare mode Res TIM8_CCMR1 Input Capture mode Res TIM8_CCMR1 Output Compare mode Res 0x18 TIM8_EGR Res 0x14 TIM8_SR Res 0x10 TIM8_DIER Res 0x0C TIM8_SMCR Res 0x08 TIM8_CR2 Res 0x04 TIM8_CR1 Res 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res Offset Res 26.4.31 Res RM0351 Advanced-control timers (TIM1/TIM8) TIM8 register map TIM8 registers are mapped as 16-bit addressable registers as described in the table below: Table 149. TIM8 register map and reset values 0 0 TS[2:0] 0 0 IC1 PSC [1:0] CC1 S [1:0] 0 0 0 0 0 0 SMS[2:0] CC1 S [1:0] 0 0 0 CC3 S [1:0] 0 0 IC3 PSC [1:0] CC3 S [1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 847/1680 849 Advanced-control timers (TIM1/TIM8) RM0351 Res 0 0 0 0 0 0 0 0 848/1680 0 0 0 0 0 0 0 0 Res Res Res Res Res Res Res Res 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res Res Res 0 0 0 0 0 0 0 0 0 0 DBL[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 LOC K [1:0] 0 DT[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res Res Res Res Res Res Res Res Res TI1_RMP ETR_ADC2_RMP 0 ETR_ADC3_RMP 0 Res DMAB[15:0] 0 DocID024597 Rev 1 0 DBA[4:0] Res Res Res Res Res Res Res Res Res 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Res 0 Reset value 0 Res BKP 0 Res Res Res Res Res Res Res Res TIM8_OR1 0 Res AOE 0 Reset value 0x50 0 0 Res TIM8_DMAR 0 OSSI MOE 0 BKF[3:0] Reset value 0x4C 0 BKE BK2E 0 Res 0 0 BK2F[3:0] 0 Res Res Res Res Res Res Res Res Res 0 BK2P Res Res Res Res TIM8_DCR Res 0x48 Res Reset value 0 Res Res Res Res Res Res TIM8_BDTR 0 CCR4[15:0] 0 Res Reset value 0x44 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM8_CCR4 0 CCR3[15:0] 0 Res Reset value 0x40 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM8_CCR3 0 CCR2[15:0] 0 Res Reset value 0x3C 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM8_CCR2 0 CCR1[15:0] 0 Res Reset value 0x38 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIMx_CCR1 0 REP[15:0] 0 Res Reset value 0x34 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM8_RCR 0 ARR[15:0] 0 Res Reset value 0x30 0 PSC[15:0] 0 Res TIM8_ARR 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Reset value 0x2C CNT[15:0] OSSR Res Res Res Res Res Res Res Res Res Res Res TIM8_PSC Res 0 Res Reset value Res 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x28 TIM8_CNT UIFCPY 0x24 Register Res Offset Res Table 149. TIM8 register map and reset values (continued) 0 0x64 TIM8_OR3 ETRSEL [2:0] Res DocID024597 Rev 1 0 0 0 0 0 0 0 0 Res Res Res Res 0 0 0 0 0 0 0 OC5M[3] OC6CE Res Res Res Res Res Res Res OC6FE OC5CE Res Res OC6PE 0 0 0 0 0 0 0 0 BKINE 0 0 0 1 BK2INE 0 BKCMP1E 0 BK2CMP1E 0 BKCMP2E 0 BK2CMP2E Res 0 Res CCR6[15:0] OC5FE 0 0 OC5PE CCR5[15:0] 0 Res 0 0 OC5M [2:0] Res 0 0 Res 0 0 Res Res OC6M[3] 0 Res Res Res Res Res Res Res Res Res Res Res 0 Res BKDFBK2E 0 BK2DFBK3E 0 BKINP 0 BK2INP 0 BKCMP1P 0 0 BK2CMP1P 0 0 BKCMP2P Reset value OC6M [2:0] BK2CMP2P Res Res Res Res Res Res Res Res 0 0 Res Res Res Res Res Res Res Res Res Res Res 0 Res TIM8_OR2 Res Res Res Res Res Res Res 0 Res 0 Res Reset value Res 0 Res Res Res 0 Res Res Res Res Res Res Res Res 0 Res Res Reset value Res Res Res 0 Res Res Res GC5C1 TIM8_CCR6 Res 0 Res GC5C2 0 Res Reset value Res GC5C3 0 Res Res 0x60 Reset value Res 0x5C TIM8_CCR5 Res 0x58 Res 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x54 TIM8_CCMR3 Output Compare mode Res Register Res Offset Res RM0351 Advanced-control timers (TIM1/TIM8) Table 149. TIM8 register map and reset values (continued) 0 0 1 Refer to Section 2.2.2 on page 68 for the register boundary addresses. 849/1680 849 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.1 TIM2/TIM3/TIM4/TIM5 introduction RM0351 The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. The timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 27.3.18. 27.2 TIM2/TIM3/TIM4/TIM5 main features General-purpose TIMx timer features include: 850/1680 • 16-bit (TIM3, TIM4) or 32-bit (TIM2 and TIM5) up, down, up/down auto-reload counter. • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535. • Up to 4 independent channels for: – Input capture – Output compare – PWM generation (Edge- and Center-aligned modes) – One-pulse mode output • Synchronization circuit to control the timer with external signals and to interconnect several timers. • Interrupt/DMA generation on the following events: – Update: counter overflow/underflow, counter initialization (by software or internal/external trigger) – Trigger event (counter start, stop, initialization or count by internal/external trigger) – Input capture – Output compare • Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes • Trigger input for external clock or cycle-by-cycle current management DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 249. General-purpose timer block diagram ,QWHUQDOFORFN &.B,17 7,0[&/.IURP5&& (75) (75 7,0[B(75 7ULJJHU FRQWUROOHU 75*2 3RODULW\VHOHFWLRQ HGJH (753 ,QSXWILOWHU GHWHFWRU SUHVFDOHU ,75 ,75 ,75 ,75 WRRWKHUWLPHUV WR'$&$'& 7*, ,75 75& 75*, 6ODYH FRQWUROOHU 5HVHWHQDEOHXSFRXQW PRGH 7,)B(' (QFRGHU LQWHUIDFH 7,)3 7,)3 8 $XWRUHORDGUHJLVWHU 6WRSFOHDURUXSGRZQ &.B36& ;25 7, 7,0[B&+ 7, 7,0[B&+ ,QSXWILOWHU HGJHGHWHFWRU ,QSXWILOWHU HGJHGHWHFWRU 7,)3 7,)3 ,& 36& &.B&17 SUHVFDOHU &&, 8 3UHVFDOHU 75& 7,)3 7,)3 75& ,&36 &&, ,& 3UHVFDOHU 7, 7,0[B&+ 7, 7,0[B&+ ,QSXWILOWHU HGJHGHWHFWRU ,QSXWILOWHU HGJHGHWHFWRU ,& 3UHVFDOHU 75& 7,)3 7,)3 &17FRXQWHU &&, &DSWXUH&RPSDUHUHJLVWHU &DSWXUH&RPSDUHUHJLVWHU 2&5() &DSWXUH&RPSDUHUHJLVWHU 3UHVFDOHU 7,0[B&+ 2XWSXW 2& FRQWURO 7,0[B&+ 2&5() 2XWSXW 2& FRQWURO 7,0[B&+ 2XWSXW 2& FRQWURO 7,0[B&+ &&, 8 ,&36 2XWSXW 2& FRQWURO &&, 8 ,&36 &&, ,& 2&5() &&, 8 ,&36 &&, 7,)3 7,)3 8, 8 &DSWXUH&RPSDUHUHJLVWHU 2&5() 75& (75) 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW '0$RXWSXW 069 DocID024597 Rev 1 851/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.3 TIM2/TIM3/TIM4/TIM5 functional description 27.3.1 Time-base unit RM0351 The main block of the programmable timer is a 16-bit/32-bit counter with its related autoreload register. The counter can count up, down or both up and down but also down or both up and down. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: • Counter Register (TIMx_CNT) • Prescaler Register (TIMx_PSC): • Auto-Reload Register (TIMx_ARR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling). Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 250 and Figure 251 give some examples of the counter behavior when the prescaler ratio is changed on the fly: 852/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 250. Counter timing diagram with prescaler division change from 1 to 2 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW 8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 Figure 251. Counter timing diagram with prescaler division change from 1 to 4 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW 8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 DocID024597 Rev 1 853/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.3.2 RM0351 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller). The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register) • The auto-reload shadow register is updated with the preload value (TIMx_ARR) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 252. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 854/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 253. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 254. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID024597 Rev 1 855/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 255. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 256. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 856/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 257. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) ) ) ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU ) $XWRUHORDGVKDGRZ UHJLVWHU ) :ULWHDQHZYDOXHLQ7,0[B$55 069 Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. An Update event can be generate at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). • The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one. DocID024597 Rev 1 857/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 258. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ FQWBXGI 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 259. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 858/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 260. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 261. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID024597 Rev 1 859/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 262. Counter timing diagram, Update event when repetition counter is not used &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0. Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to '00'. The Output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3, CMS = "11"). In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter. The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler. The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value. In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or 860/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). • The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value). The following figures show some examples of the counter behavior for different clock frequencies. Figure 263. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 1. Here, center-aligned mode 1 is used (for more details refer to Section 27.4.1: TIMx control register 1 (TIMx_CR1) on page 895). DocID024597 Rev 1 861/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 264. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 265. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 1RWH+HUHFHQWHUBDOLJQHGPRGHRULVXSGDWHGZLWKDQ8,)RQRYHUIORZ 069 1. Center-aligned mode 2 or 3 is used with an UIF on overflow. 862/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 266. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 267. Counter timing diagram, Update event with ARPE=1 (counter underflow) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )' :ULWHDQHZYDOXHLQ7,0[B$55 $XWRUHORDGDFWLYH UHJLVWHU )' 069 DocID024597 Rev 1 863/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 268. Counter timing diagram, Update event with ARPE=1 (counter overflow) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )' :ULWHDQHZYDOXHLQ7,0[B$55 $XWRUHORDGDFWLYH )' UHJLVWHU 069 27.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin (TIx) • External clock mode2: external trigger input (ETR) • Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, you can configure Timer 13 to act as a prescaler for Timer 2. Refer to : Using one timer as prescaler for another timer on page 889 for more details. Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 269 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. 864/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 269. Control circuit in normal mode, internal clock divided by 1 ,QWHUQDOFORFN &(1 &17B(1 8* &17B,1,7 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 069 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 270. TI2 external clock connection example 7,0[B60&5 76>@ RU 7,) 7,) ,75[ 7,B(' 7, )LOWHU (GJH GHWHFWRU 7,)B5LVLQJ 7,)B)DOOLQJ 7,)3 7,)3 (75) RU RU [[ 75*, (75) &.B,17 ,&)>@ &&3 7,0[B&&05 7,0[B&&(5 LQWHUQDOFORFN (QFRGHU PRGH ([WHUQDOFORFN PRGH ([WHUQDOFORFN PRGH &.B36& ,QWHUQDOFORFN PRGH (&( 606>@ 7,0[B60&5 069 For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: DocID024597 Rev 1 865/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Note: RM0351 1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the TIMx_CCMR1 register. 2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. 3. Select rising edge polarity by writing CC2P=0 and CC2NP=0 and CC2NP=0 in the TIMx_CCER register. 4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register. 5. Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register. 6. Enable the counter by writing CEN=1 in the TIMx_CR1 register. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. Figure 271. Control circuit in external clock mode 1 7, &17B(1 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 272 gives an overview of the external trigger input block. 866/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 272. External trigger input block RU 7,) 7,) (75 RU RU 75*, (75SLQ 'LYLGHU (753 I'76 )LOWHU GRZQFRXQWHU (75) &.B,17 (73 (736>@ (7)>@ 7,0[B60&5 7,0[B60&5 7,0[B60&5 LQWHUQDOFORFN (QFRGHU PRGH ([WHUQDOFORFN PRGH ([WHUQDOFORFN PRGH &.B36& ,QWHUQDOFORFN PRGH (&( 606>@ 7,0[B60&5 069 For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: 1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. 2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register 3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register 4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register. 5. Enable the counter by writing CEN=1 in the TIMx_CR1 register. The counter counts once each 2 ETR rising edges. The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. DocID024597 Rev 1 867/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 273. Control circuit in external clock mode 2 I &.B,17 &17B(1 (75 (753 (75) &RXQWHUFORFN &.B,17 &.B36& &RXQWHUUHJLVWHU 069 27.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). The following figure gives an overview of one Capture/Compare channel. The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). 868/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 274. Capture/compare channel (example: channel 1 input stage) 7,)B(' 7RWKHVODYHPRGHFRQWUROOHU 7,)B5LVLQJ 7, )LOWHU 7,) GRZQFRXQWHU I'76 (GJH GHWHFWRU 7,)B)DOOLQJ 7,)3 7,)3 &&3&&13 ,&)>@ 75& 7,0[B&&(5 7,0[B&&05 7,)B5LVLQJ IURPFKDQQHO 7,)B)DOOLQJ IURPFKDQQHO ,& IURPVODYHPRGH FRQWUROOHU ,&36 'LYLGHU &&6>@ ,&36>@ &&( 7,0[B&&05 7,0[B&&(5 069 The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 275. Capture/compare channel 1 main circuit $3%%XV 5HDG&&5+ 6 5HDG&&5/ KLJK UHDGBLQBSURJUHVV &&6>@ ,&36 ZULWHBLQBSURJUHVV ,QSXW PRGH 6 ZULWH&&5+ &DSWXUHFRPSDUHSUHORDGUHJLVWHU 5 5 FRPSDUHBWUDQVIHU FDSWXUHBWUDQVIHU &&6>@ ORZ LIELW 0&8SHULSKHUDOLQWHUIDFH 2XWSXW PRGH &17!&&5 &RXQWHU &&* &&6>@ 8(9 &RPSDUDWRU &&( &&6>@ 2&3( &DSWXUHFRPSDUHVKDGRZUHJLVWHU &DSWXUH ZULWH&&5/ IURPWLPH EDVHXQLW 2&3( 7,0[B&&05 &17 &&5 7,0[B(*5 069 DocID024597 Rev 1 869/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 276. Output stage of capture/compare channel (channel 1) 7,0[B60&5 2&&6 2&5()B&/5 7RWKHPDVWHU PRGHFRQWUROOHU (75) 2&5()& RFUHIBFOUBLQW 2&5() µ¶ &17!&&5 2XWSXW PRGH &17 &&5 FRQWUROOHU 2&5() 2XWSXW VHOHFWRU &&( &&3 7,0[B&&(5 7,0[B&&(5 2XWSXW HQDEOH FLUFXLW &&( 7,0[B&&(5 02( 2&&( 2&0>@ 7,0[B&&05 2& 266, 7,0[B%'75 2,6 7,0[B&5 069 The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. 27.3.5 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to 0 or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to 0. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: 870/1680 1. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only. 2. Program the input filter duration you need with respect to the signal you connect to the timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. 3. Select the edge of the active transition on the TI1 channel by writing the CC1P and CC1NP and CC1NP bits to 000 in the TIMx_CCER register (rising edge in this case). 4. Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the TIMx_CCMR1 register). 5. Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register. 6. If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register. When an input capture occurs: • The TIMx_CCR1 register gets the value of the counter on the active transition. • CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared. • An interrupt is generated depending on the CC1IE bit. • A DMA request is generated depending on the CC1DE bit. In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data. Note: IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. DocID024597 Rev 1 871/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.3.6 RM0351 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. • One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): 1. Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected). 2. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P to ‘0’ and the CC1NP bit to ‘0’ (active on rising edge). 3. Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected). 4. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P bit to ‘1’ and the CC2NP bit to ’0’ (active on falling edge). 5. Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register (TI1FP1 selected). 6. Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx_SMCR register. 7. Enable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register. Figure 277. PWM input mode timing 7, 7,0[B&17 7,0[B&&5 7,0[B&&5 ,&FDSWXUH ,&FDSWXUH UHVHWFRXQWHU ,&FDSWXUH SXOVHZLGWK PHDVXUHPHQW ,&FDSWXUH SHULRG PHDVXUHPHQW DL 1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only TI1FP1 and TI2FP2 are connected to the slave mode controller. 872/1680 DocID024597 Rev 1 RM0351 27.3.7 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (ocxref/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. e.g.: CCxP=0 (OCx active high) => OCx is forced to high level. ocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register. Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section. 27.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: • Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match. • Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register). • Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register). • Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection). The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register. In output compare mode, the update event UEV has no effect on ocxref and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode). Procedure 1. Select the counter clock (internal, external, prescaler). 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. 3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be generated. 4. Select the output mode. For example, you must write OCxM=011, OCxPE=0, CCxP=0 and CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx preload is not used, OCx is enabled and active high. 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register. DocID024597 Rev 1 873/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 278. Figure 278. Output compare mode, toggle on OC1 :ULWH%KLQWKH&&5UHJLVWHU 7,0B&17 7,0B&&5 % $ % % % $ 2&5() 2& 0DWFKGHWHFWHGRQ&&5 ,QWHUUXSWJHQHUDWHGLIHQDEOHG 069 27.3.9 PWM mode Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register. As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details. In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx≤TIMx_CNT or TIMx_CNT≤TIMx_CCRx (depending on the direction of the counter). However, to comply with the OCREF_CLR functionality (OCREF can be 874/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) cleared by an external event through the ETR signal until the next PWM period), the OCREF signal is asserted only: • When the result of the comparison or • When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from the “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes (OCxM=‘110 or ‘111). This forces the PWM by software while the timer is running. The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting mode on page 854. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then ocxref is held at ‘1. 0% PWM is not possible in this mode. PWM center-aligned mode Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ‘00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Center-aligned mode (up/down counting) on page 860. Figure 280 shows some center-aligned PWM waveforms in an example where: 876/1680 • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 280. Center-aligned PWM waveforms (ARR=8) &RXQWHUUHJLVWHU 2&[5() &&5[ &06 &06 &06 &&[,) 2&[5() &&5[ &06 RU &&[,) 2&[5() µ¶ &&5[ &&[,) 2&[5() &&5[! µ¶ &06 &06 &06 &&[,) 2&[5() &&5[ &&[,) &06 &06 &06 µ¶ &06 &06 &06 $,E Hints on using center-aligned mode: • When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular: • – The direction is not updated if you write a value in the counter that is greater than the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count up. – The direction is updated if you write 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated. The safest way to use center-aligned mode is to generate an update by software (setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running. DocID024597 Rev 1 877/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.3.10 RM0351 Asymmetric PWM mode Asymmetric mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of TIMx_CCRx registers. One register controls the PWM during up-counting, the second during down counting, so that PWM is adjusted every half PWM cycle: • OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2 • OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4 Asymmetric PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing ‘1110’ (Asymmetric PWM mode 1) or ‘1111’ (Asymmetric PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones. When a given channel is used as asymmetric PWM channel, its secondary channel can also be used. For instance, if an OC1REFC signal is generated on channel 1 (Asymmetric PWM mode 1), it is possible to output either the OC2REF signal on channel 2, or an OC2REFC signal resulting from asymmetric PWM mode 2. Figure 281 shows an example of signals that can be generated using Asymmetric PWM mode (channels 1 to 4 are configured in Asymmetric PWM mode 1). Figure 281. Generation of 2 phase-shifted PWM signals with 50% duty cycle &RXQWHUUHJLVWHU &&5 &&5 &&5 &&5 2&5()& 2&5()& 069 27.3.11 Combined PWM mode Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and delay are determined by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or AND logical combination of two reference PWMs: – OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2 – OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4 Combined PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing ‘1100’ (Combined PWM mode 1) or ‘1101’ (Combined PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. 878/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) When a given channel is used as combined PWM channel, its secondary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2). Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones. Figure 282 shows an example of signals that can be generated using Asymmetric PWM mode, obtained with the following configuration: • Channel 1 is configured in Combined PWM mode 2, • Channel 2 is configured in PWM mode 1, • Channel 3 is configured in Combined PWM mode 2, • Channel 4 is configured in PWM mode 1 Figure 282. Combined PWM mode on channels 1 and 3 2&¶ 2&¶ 2& 2& 2&5() 2&5() 2&5()¶ 2&5()¶ 2&5()& 2&5()&¶ 2&5()& 2&5()$1'2&5() 2&5()&¶ 2&5()¶252&5()¶ 069 27.3.12 Clearing the OCxREF signal on an external event The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1). OCxREF remains low until the next update event (UEV) occurs. This function can only be used in Output compare and PWM modes. It does not work in Forced mode. OCREF_CLR_INPUT can be selected between the OCREF_CLR input and ETRF (ETR after the filter) by configuring the OCCS bit in the TIMx_SMCR register. When ETRF is chosen, ETR must be configured as follows: DocID024597 Rev 1 879/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 The OCxREF signal for a given channel can be reset by applying a high level on the ETRF input (OCxCE enable bit set to 1 in the corresponding TIMx_CCMRx register). OCxREF remains low until the next update event (UEV) occurs. This function can be used only in the output compare and PWM modes. It does not work in forced mode. For example, the OCxREF signal can be connected to the output of a comparator to be used for current handling. In this case, ETR must be configured as follows: 1. The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00. 2. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is cleared to 0. 3. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application’s needs. Figure 283 shows the behavior of the OCxREF signal when the ETRF input becomes high, for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in PWM mode. Figure 283. Clearing TIMx OCxREF &&5[ &RXQWHU &17 (75) 2&[5() 2&[&( µ¶ 2&[5() 2&[&( µ¶ 2&[5()B&/5 EHFRPHVKLJK 2&[5()B&/5 VWLOOKLJK 069 Note: 880/1680 In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the next counter overflow. DocID024597 Rev 1 RM0351 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be: • CNT TIMx_CCR1 else active (OC1REF=1). 0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT TIMx_CCR1 else inactive. 1000: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 1001: Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 1010: Reserved, 1011: Reserved, 1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). 2: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. DocID024597 Rev 1 907/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in onepulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. Bit 2 OC1FE: Output compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output. 01: CC1 channel is configured as input, IC1 is mapped on TI1. 10: CC1 channel is configured as input, IC1 is mapped on TI2. 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). Input capture mode Bits 31:16 Reserved, always read as 0. Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1. 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). 908/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). DocID024597 Rev 1 909/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.4.8 RM0351 TIMx capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 Res. 25 24 Res. OC4M [3] 23 Res. 22 Res. 21 Res. 20 Res. 19 Res. 18 Res. 17 16 Res. OC3M [3] Res. Res. rw 15 14 OC4CE 13 12 OC4M[2:0] rw rw 10 OC4PE OC4FE IC4F[3:0] rw 11 IC4PSC[1:0] rw rw rw 9 rw 8 CC4S[1:0] rw 7 6 OC3CE rw 5 4 OC3M[2:0] rw rw 2 OC3PE OC3FE IC3F[3:0] rw 3 IC3PSC[1:0] rw rw rw 1 0 CC3S[1:0] rw rw Output compare mode Bits 31:25 Reserved, always read as 0. Bit 24 OC4M[3]: Output Compare 2 mode - bit 3 Bits 23:17 Reserved, always read as 0. Bit 16 OC3M[3]: Output Compare 1 mode - bit 3 Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register) Bit 11 OC4PE: Output compare 4 preload enable Bit 10 OC4FE: Output compare 4 fast enable Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). Bit 7 OC3CE: Output compare 3 clear enable Bits 6:4 OC3M: Output compare 3 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register) 910/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). Input capture mode Bits 31:16 Reserved, always read as 0. Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). Bits 7:4 IC3F: Input capture 3 filter Bits 3:2 IC3PSC: Input capture 3 prescaler Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 27.4.9 TIMx capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CC4NP Res. CC4P CC4E CC3NP Res. CC3P CC3E CC2NP Res. CC2P CC2E CC1NP Res. CC1P CC1E rw rw rw rw rw rw rw rw rw rw rw rw DocID024597 Rev 1 911/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Bit 15 CC4NP: Capture/Compare 4 output Polarity. Refer to CC1NP description Bit 14 Reserved, must be kept at reset value. Bit 13 CC4P: Capture/Compare 4 output Polarity. Refer to CC1P description Bit 12 CC4E: Capture/Compare 4 output enable. refer to CC1E description Bit 11 CC3NP: Capture/Compare 3 output Polarity. Refer to CC1NP description Bit 10 Reserved, must be kept at reset value. Bit 9 CC3P: Capture/Compare 3 output Polarity. Refer to CC1P description Bit 8 CC3E: Capture/Compare 3 output enable. Refer to CC1E description Bit 7 CC2NP: Capture/Compare 2 output Polarity. Refer to CC1NP description Bit 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity. refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable. Refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 output Polarity. CC1 channel configured as output: CC1NP must be kept cleared in this case. CC1 channel configured as input: This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description. 912/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Bit 2 Reserved, must be kept at reset value. Bit 1 CC1P: Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations. 00: noninverted/rising edge Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode). 01: inverted/falling edge Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is inverted (trigger in gated mode, encoder mode). 10: reserved, do not use this configuration. 11: noninverted/both edges Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration must not be used for encoder mode. Bit 0 CC1E: Capture/Compare 1 output enable. CC1 channel configured as output: 0: Off - OC1 is not active 1: On - OC1 signal is output on the corresponding output pin CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled 1: Capture enabled Table 152. Output control bit for standard OCx channels CCxE bit OCx output state 0 Output Disabled (OCx=0, OCx_EN=0) 1 OCx=OCxREF + Polarity, OCx_EN=1 Note: The state of the external IO pins connected to the standard OCx channels depends on the OCx channel state and the GPIO and AFIO registers. 27.4.10 TIMx counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 31 30 29 28 27 26 25 CNT[31] or UIFCPY 24 23 22 21 20 19 18 17 16 CNT[30:16] (depending on timers) rw or r rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CNT[15:0] rw rw rw rw rw rw rw rw rw DocID024597 Rev 1 913/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Bit 31 Value depends on IUFREMAP in TIMx_CR1. If UIFREMAP = 0 CNT[31]: Most significant bit of counter value (on TIM2 and TIM5) Reserved on other timers If UIFREMAP = 1 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register Bits 30:16 CNT[30:16]: Most significant part counter value (on TIM2 and TIM5) Bits 15:0 CNT[15:0]: Least significant part of counter value 27.4.11 TIMx prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PSC[15:0] rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event. 27.4.12 TIMx auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ARR[31:16] (depending on timers) rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ARR[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 ARR[31:16]: High auto-reload value (on TIM2 and TIM5) Bits 15:0 ARR[15:0]: Low Auto-reload Prescaler value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 27.3.1: Time-base unit on page 852 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 27.4.13 TIMx capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw CCR1[31:16] (depending on timers) rw 914/1680 rw rw rw rw rw rw rw rw rw DocID024597 Rev 1 RM0351 15 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR1[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value (on TIM2 and TIM5) Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). 27.4.14 TIMx capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x00000000 31 30 29 28 27 26 25 24 23 rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 22 21 20 19 18 17 16 rw rw rw rw rw rw rw 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR2[31:16] (depending on timers) CCR2[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 CCR2[31:16]: High Capture/Compare 2 value (on TIM2 and TIM5) Bits 15:0 CCR2[15:0]: Low Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). 27.4.15 TIMx capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw CCR3[31:16] (depending on timers) rw rw rw rw rw rw rw rw rw rw DocID024597 Rev 1 915/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 15 14 13 12 11 10 9 8 RM0351 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR3[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2 and TIM5) Bits 15:0 CCR3[15:0]: Low Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). 27.4.16 TIMx capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CCR4[31:16] (depending on timers) rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw CCR4[15:0] rw rw Bits 31:16 CCR4[31:16]: High Capture/Compare 4 value (on TIM2 and TIM5) Bits 15:0 CCR4[15:0]: Low Capture/Compare value 1. if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. 2. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). 916/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.4.17 TIMx DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 15 14 13 Res. Res. Res. 12 11 10 9 8 DBL[4:0] rw rw rw rw 7 6 5 Res. Res. Res. rw 4 3 2 1 0 rw rw DBA[4:0] rw rw rw Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers. Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 DBA[4:0]: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1 00001: TIMx_CR2 00010: TIMx_SMCR ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 27.4.18 TIMx DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DMAB[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 27.4.19 TIM2 option register 1 (TIM2_OR1) Address offset: 0x50 DocID024597 Rev 1 917/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI4_RMP[1:0] rw 1 0 ETR1_ RMP ITR1_ RMP rw rw rw Bits 31:4 Reserved, must be kept at reset value. Bits 3:2 TI4_RMP[1:0]: Input Capture 4 remap 00: TIM2 input capture 4 is connected to I/O 01: TIM2 input capture 4 is connected to COMP1_OUT 10: TIM2 input capture 4 is connected to COMP2_OUT 11: TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT Bit 1 ETR1_RMP: External trigger remap 0: TIM2_ETR is connected to I/O 1: TIM2_ETR is connected to LSE Bit 0 ITR1_RMP: Internal trigger 1 remap 0: TIM2_ITR1 is connected to TIM8_TRGO 1: TIM2_ITR1 is connected to OTG_FS SOF 27.4.20 TIM3 option register 1 (TIM3_OR1) Address offset: 0x50 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI1_RMP[1:0] rw Bits 31:2 Reserved, must be kept at reset value. Bits 1:0 TI1_RMP[1:0]: Input Capture 1 remap 00: TIM3 input capture 1 is connected to I/O 01: TIM3 input capture 1 is connected to COMP1_OUT 10: TIM3 input capture 1 is connected to COMP2_OUT 11: TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT 27.4.21 TIM2 option register 2 (TIM2_OR2) Address offset: 0x60 918/1680 DocID024597 Rev 1 rw RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Reset value: 0x0000 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 Res. 25 Res. 24 Res. 23 Res. 22 Res. 21 Res. 20 Res. 19 Res. 18 Res. 17 16 Res. ETR SEL2 rw 15 14 ETRSEL[1:0] rw 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:17 Reserved, must be kept at reset value. Bits 16:14 ETRSEL[2:0]: ETR source selection These bits select the ETR input source. 000: ETR legacy mode 001: COMP1 output connected to ETR input 010: COMP2 output connected to ETR input Other: reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 13:0 Reserved, must be kept at reset value. 27.4.22 TIM3 option register 2 (TIM3_OR2) Address offset: 0x60 Reset value: 0x0000 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 Res. 25 Res. 24 Res. 23 Res. 22 Res. 21 Res. 20 Res. 19 Res. 18 Res. 17 16 Res. ETR SEL2 rw 15 14 ETRSEL[1:0] rw 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:17 Reserved, must be kept at reset value. Bits 16:14 ETRSEL[2:0]: ETR source selection These bits select the ETR input source. 000: ETR legacy mode 001: COMP1 output connected to ETR input Other: reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 13:0 Reserved, must be kept at reset value. DocID024597 Rev 1 919/1680 922 0x20 920/1680 TIMx_CCER Reset value DocID024597 Rev 1 0 0 0 OC4M [2:0] CC4S [1:0] 0 0 0 0 0 0 IC4F[3:0] 0 0 0 0 0 0 0 Reset value 0 0 0 OC1M [2:0] 0 0 0 0 0 IC4 PSC [1:0] CC4S [1:0] 0 0 0 0 0 0 0 0 0 UG 0 CC1G UIE UIF 0 CC2G CC1IE CC1IF 0 0 0 0 0 0 OC1FE CC2IE CC2IF 0 CC3G CC3IE CC3IF 0 OC1PE 0 0 0 0 0 0 Res CC4IE 0 Res CC4IF 0 Res TIE 0 TIF 0 TG MSM DIR OPM URS UDIS CEN 0 0 0 0 TI1S MMS[2:0] CCDS Res Res Res ARPE 0 0 0 0 0 0 0 TS[2:0] 0 IC1F[3:0] 0 0 OC3M [2:0] 0 IC3F[3:0] Res Res UIFREMAP Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 IC1 PSC [1:0] CC1S [1:0] 0 0 0 OC3FE 0 0 0 CC4G Res UDE 0 Res CC1OF 0 Res Res CC2OF 0 Res 0 CC3OF 0 Res 0 CC4OF 0 Res 0 Res Res 0 0 Res 0 0 CMS [1:0] OC3PE CC2S [1:0] OC1CE 0 CC1DE 0 CC2DE 0 IC3 PSC [1:0] CC3S [1:0] 0 0 0 0 0 CC1E CC2S [1:0] 0 OC2FE 0 CC3DE 0 CC4DE 0 COMDE 0 Res ECE 0 ETF[3:0] Res 0 Res ETP 0 TDE SMS[3] Res Res Res Res Res Res Res 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res ETPS [1:0] Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value CC1P 0 0 CC1NP 0 0 CC2E 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value CKD [1:0] CC2P 0 IC2 PSC [1:0] OC3CE IC2F[3:0] Res 0 0 0 CC3E 0 OC2M [2:0] OC2PE 0 CC2NP 0 OC4FE OC2CE 0 OC4PE OC1M[3] Res Res Res Res Res Res Res Res Res Res Res Reset value Res 0 CC3NP Res Res Res Res Res Res Res Res OC2M[3] Res Res Res Res Res Reset value CC3P 0 CC4E 0 0 CC4P Reset value Res O24CE Reset value CC4NP 0 OC3M[3] Res Res Res Res Res Res Res Res Res Res 0 Res Res Res Res Res Res Res Res OC4M[3] Res Res Res Res Res Res Reset value Res Res Res Res Res Res Res Res Reset value Res Res Res Res Res Res Reset value Res Res Res TIMx_CCMR2 Input Capture mode Res 0x1C Res TIMx_CCMR2 Output Compare mode Res TIMx_CCMR1 Input Capture mode Res 0x18 Res TIMx_CCMR1 Output Compare mode Res TIMx_EGR Res 0x14 Res TIMx_SR Res 0x10 Res TIMx_DIER Res 0x0C Res TIMx_SMCR Res 0x08 Res TIMx_CR2 Res 0x04 Res TIMx_CR1 Res 0x00 Res 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res Offset Res 27.4.23 Res General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 TIMx register map TIMx registers are mapped as described in the table below: Table 153. TIM2/TIM3/TIM4/TIM5 register map and reset values SMS[2:0] 0 0 0 CC1S [1:0] 0 0 0 0 CC3S [1:0] 0 0 0 0 0 0 0 0 0 0 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) CNT[31] or UIFCPY Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_PSC Res Res Res Res Res Res Res Res Res Res Res Res Res Res CNT[30:16] (TIM2 and TIM5 only, reserved on the other timers) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR1[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR3[31:16] (TIM2 and TIM5 only, reserved on the other timers) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR4[15:0] Res 0 0 CCR3[15:0] CCR4[31:16] (TIM2 and TIM5 only, reserved on the other timers) TIMx_CCR4 0 CCR2[15:0] 0 0 0 0 0 0 0 0 0 0 0 DBA[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM3_OR1 Res 0x50 Res Reset value 0 0 ITR1_RMP 0 ETR1_RMP 0 0 0 Res 0 TI1_RMP[1:0] 0 TI4_RMP[1:0] 0 Res 0 Res DMAB[15:0] Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value TIM2_OR1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Res TIMx_DMAR DBL[4:0] Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIMx_DCR Res Reserved Reset value 0x50 0 Res 0 0x44 0x4C 0 PSC[15:0] CCR2[31:16] (TIM2 and TIM5 only, reserved on the other timers) TIMx_CCR3 Reset value 0x48 0 Res 0 TIMx_CCR2 Reset value 0x40 0 CCR1[31:16] (TIM2 and TIM5 only, reserved on the other timers) TIMx_CCR1 Reset value 0x3C 0 Reserved Reset value 0x38 0 Res 0x30 0x34 0 ARR[31:16] (TIM2 and TIM5 only, reserved on the other timers) TIMx_ARR Reset value 0 0 Res 0x2C CNT[15:0] Res 0x28 TIMx_CNT Res 0x24 Register Res Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 153. TIM2/TIM3/TIM4/TIM5 register map and reset values (continued) 0 DocID024597 Rev 1 921/1680 922 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Reset value 0 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Res Res Res Res Res Res Res Res Res Res ETRSEL [2:0] Res TIM3_OR2 Res 0 Res Reset value Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res ETRSEL [2:0] Res 0x60 TIM2_OR2 Res 0x60 Register Res Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 153. TIM2/TIM3/TIM4/TIM5 register map and reset values (continued) 0 0 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. 922/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) 28 General-purpose timers (TIM15/16/17) 28.1 TIM15/16/17 introduction The TIM15/16/17 timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. The TIM15/16/17 timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 27.3.18: Timer synchronization on page 889. 28.2 TIM15 main features TIM15 includes the following features: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535 • Up to 2 independent channels for: – Input capture – Output compare – PWM generation (edge mode) – One-pulse mode output • Complementary outputs with programmable dead-time (for channel 1 only) • Synchronization circuit to control the timer with external signals and to interconnect several timers together • Repetition counter to update the timer registers only after a given number of cycles of the counter • Break input to put the timer’s output signals in the reset state or a known state • Interrupt/DMA generation on the following events: – Update: counter overflow, counter initialization (by software or internal/external trigger) – Trigger event (counter start, stop, initialization or count by internal/external trigger) – Input capture – Output compare – Break input (interrupt request) DocID024597 Rev 1 923/1680 1002 General-purpose timers (TIM15/16/17) 28.3 RM0351 TIM16 and TIM17 main features The TIM16 and TIM17 timers include the following features: 924/1680 • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535 • One channel for: – Input capture – Output compare – PWM generation (edge-aligned mode) – One-pulse mode output • Complementary outputs with programmable dead-time • Repetition counter to update the timer registers only after a given number of cycles of the counter • Break input to put the timer’s output signals in the reset state or a known state • Interrupt/DMA generation on the following events: – Update: counter overflow – Trigger event (counter start, stop, initialization or count by internal/external trigger) – Input capture – Output compare – Break input DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) Figure 297. TIM15 block diagram ,QWHUQDOFORFN &.B,17 &.B7,0IURP5&& ,75 ,75 ,75 ,75 7ULJJHU FRQWUROOHU 7*, ,75 75& 7,)B(' 75*, 75*2 WRRWKHUWLPHUV 6ODYH FRQWUROOHU 5HVHWHQDEOHXSFRXQW PRGH 7,)3 7,)3 5(3UHJLVWHU 8 8, $XWRUHORDGUHJLVWHU 5HSHWLWLRQ FRXQWHU 6WRSFOHDURUXSGRZQ &.B36& ;25 7, 7,0[B&+ 7,0[B&+ 7, ,QSXWILOWHU HGJHGHWHFWRU ,QSXWILOWHU HGJHGHWHFWRU ,QWHUQDOVRXUFHV 7,)3 7,)3 3UHVFDOHU 75& 7,)3 7,)3 75& ,&36 &&, ,& 3UHVFDOHU ,&36 &17FRXQWHU &&, &DSWXUH&RPSDUHUHJLVWHU '7*UHJLVWHUV 2&5() '7* &&, 8 &DSWXUH&RPSDUHUHJLVWHU 2&5() 7,0[B&+ 2XWSXW 2& FRQWURO 7,0[B&+1 2&1 2XWSXW 2& 7,0[B&+ FRQWURO 6%,) %,) %UHDNFLUFXLWU\ 7,0[B%.,1 ,& &.B&17 36& SUHVFDOHU &&, 8 8 %5.UHTXHVW 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW '0$RXWSXW 06Y9 1. The internal break event source can be: A clock failure event generated by CSS. For further information on the CSS, refer to Section 8.2.9: Clock security system (CSS) A PVD output SRAM parity error signal Cortex®-M4 LOCKUP (Hardfault) output COMP output DocID024597 Rev 1 925/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Figure 298. TIM16 and TIM17 block diagram ,QWHUQDOFORFN &.B,17 &RXQWHU(QDEOH &(1 5(3UHJLVWHU $XWRUHORDGUHJLVWHU 8 8, 5HSHWLWLRQ FRXQWHU 6WRSFOHDURUXSGRZQ &.B36& 7,0[B&+ 7, ,QSXWILOWHU HGJHVHOHFWRU 7,)3 ,& 36& &.B&17 SUHVFDOHU &, 8 ,&36 3UHVFDOHU &17FRXQWHU 8 '7*UHJLVWHUV &&, &DSWXUHFRPSDUHUHJLVWHU 7,0[B&+ 2&5() '7* 2XWSXW 2& FRQWURO 7,0[B&+1 2&1 ,QWHUQDOVRXUFHV 6%,) %,) %UHDNFLUFXLWU\ 7,0[B%.,1 %5.UHTXHVW 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW '0$RXWSXW 06Y9 1. The internal break event source can be: A clock failure event generated by CSS. For further information on the CSS, refer to Section 8.2.9: Clock security system (CSS) A PVD output SRAM parity error signal Cortex®-M4 LOCKUP (Hardfault) output COMP output 926/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) 28.4 TIM15/16/17 functional description 28.4.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: • Counter register (TIMx_CNT) • Prescaler register (TIMx_PSC) • Auto-reload register (TIMx_ARR) • Repetition counter register (TIMx_RCR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detailed for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling). Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 299 and Figure 300 give some examples of the counter behavior when the prescaler ratio is changed on the fly: DocID024597 Rev 1 927/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Figure 299. Counter timing diagram with prescaler division change from 1 to 2 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW 8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 Figure 300. Counter timing diagram with prescaler division change from 1 to 4 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW 8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 928/1680 DocID024597 Rev 1 RM0351 28.4.2 General-purpose timers (TIM15/16/17) Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR). Else the update event is generated at each counter overflow. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The repetition counter is reloaded with the content of TIMx_RCR register, • The auto-reload shadow register is updated with the preload value (TIMx_ARR), • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. DocID024597 Rev 1 929/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Figure 301. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 302. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 930/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) Figure 303. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 304. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID024597 Rev 1 931/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Figure 305. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 Figure 306. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) ) ) ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU ) $XWRUHORDGVKDGRZ UHJLVWHU ) :ULWHDQHZYDOXHLQ7,0[B$55 932/1680 DocID024597 Rev 1 069 RM0351 28.4.3 General-purpose timers (TIM15/16/17) Repetition counter Section 28.4.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals. This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N counter overflows, where N is the value in the TIMx_RCR repetition counter register. The repetition counter is decremented at each counter overflow. The repetition counter is an auto-reload type; the repetition rate is maintained as defined by the TIMx_RCR register value (refer to Figure 307). When the update event is generated by software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition counter is and the repetition counter is reloaded with the content of the TIMx_RCR register. DocID024597 Rev 1 933/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Figure 307. Update rate examples depending on mode and TIMx_RCR register settings (GJHDOLJQHGPRGH 8SFRXQWLQJ &RXQWHU 7,0[B&17 7,0[B5&5 8(9 7,0[B5&5 8(9 7,0[B5&5 8(9 7,0[B5&5 8(9 7,0[B5&5 DQG UHV\QFKURQL]DWLRQ8(9 E\6: 8(9 8SGDWH(YHQWSUHORDGUHJLVWHUVWUDQVIHUUHGWRDFWLYHUHJLVWHUV DQGXSGDWHLQWHUUXSWJHQHUDWHG 069 28.4.4 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • Internal trigger inputs (ITRx) (only for TIM15): using one timer as the prescaler for another timer, for example, you can configure TIM1 to act as a prescaler for TIM15. Refer to Using one timer as prescaler for another timer on page 889 for more details. Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000), then the CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed 934/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 308 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. Figure 308. Control circuit in normal mode, internal clock divided by 1 ,QWHUQDOFORFN &(1 &17B(1 8* &17B,1,7 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 069 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 309. TI2 external clock connection example 7,0[B60&5 76>@ ,75[ 7,B(' 7, )LOWHU (GJH GHWHFWRU 7,)B5LVLQJ 7,)B)DOOLQJ 7,)3 7,)3 [[ 75*, &&3 7,0[B&&05 7,0[B&&(5 &.B36& &.B,17 ,&)>@ ([WHUQDOFORFN PRGH LQWHUQDOFORFN ,QWHUQDOFORFN PRGH 606>@ 7,0[B60&5 069 DocID024597 Rev 1 935/1680 1002 General-purpose timers (TIM15/16/17) RM0351 For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Note: 1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register. 2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). 3. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register. 4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register. 5. Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register. 6. Enable the counter by writing CEN=1 in the TIMx_CR1 register. The capture prescaler is not used for triggering, so you don’t need to configure it. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. Figure 310. Control circuit in external clock mode 1 7, &17B(1 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 28.4.5 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). Figure 311 to Figure 314 give an overview of one Capture/Compare channel. The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). 936/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) Figure 311. Capture/compare channel (example: channel 1 input stage) 7,)B(' 7RWKHVODYHPRGHFRQWUROOHU 7,)B5LVLQJ 7, )LOWHU 7,) GRZQFRXQWHU I'76 (GJH GHWHFWRU 7,)B)DOOLQJ 7,)3 7,)3 ,&)>@ &&3 7,0[B&&05 7,0[B&&(5 7,)B5LVLQJ IURPFKDQQHO 7,)B)DOOLQJ IURPFKDQQHO ,& 75& IURPVODYHPRGH FRQWUROOHU ,&36 'LYLGHU &&6>@ ,&36>@ &&( 7,0[B&&05 7,0[B&&(5 069 The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 312. Capture/compare channel 1 main circuit $3%%XV 5HDG&&5+ 6 5HDG&&5/ KLJK UHDGBLQBSURJUHVV &&6>@ ,&36 ZULWHBLQBSURJUHVV ,QSXW PRGH 6 ZULWH&&5+ &DSWXUHFRPSDUHSUHORDGUHJLVWHU 5 5 FRPSDUHBWUDQVIHU FDSWXUHBWUDQVIHU &&6>@ ORZ LIELW 0&8SHULSKHUDOLQWHUIDFH 2XWSXW PRGH &17!&&5 &RXQWHU &&* &&6>@ 8(9 &RPSDUDWRU &&( &&6>@ 2&3( &DSWXUHFRPSDUHVKDGRZUHJLVWHU &DSWXUH ZULWH&&5/ IURPWLPH EDVHXQLW 2&3( 7,0B&&05 &17 &&5 7,0B(*5 069 DocID024597 Rev 1 937/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Figure 313. Output stage of capture/compare channel (channel 1) 7RWKHPDVWHUPRGH FRQWUROOHU µ¶ 2&5()& 2&5() &17!&&5 2XWSXW PRGH &17 &&5 FRQWUROOHU 2&B'7 'HDGWLPH JHQHUDWRU 2XWSXW VHOHFWRU [ &&3 2XWSXW HQDEOH FLUFXLW 2& 2XWSXW HQDEOH FLUFXLW 2&1 7,0B&&(5 2&1B'7 µ¶ 2&5() [ &&1( &&( 7,0B&&(5 2&&( 2&0>@ '7*>@ &&1( &&( &&13 02( 266, 2665 7,0B&&05 7,0B%'75 7,0B&&(5 7,0B&&(5 7,0B%'75 069 Figure 314. Output stage of capture/compare channel (channel 2 for TIM15) 7RWKHPDVWHU PRGHFRQWUROOHU 2&5()& 2&5() µ¶ &17!&&5 2XWSXW PRGH &17 &&5 FRQWUROOHU 2&5() 2XWSXW VHOHFWRU &&( &&3 7,0B&&(5 7,0B&&(5 2XWSXW HQDEOH FLUFXLW 2& &&( 7,0B&&(5 2&&( 2&0>@ 7,0B&&05 069 The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. 938/1680 DocID024597 Rev 1 RM0351 28.4.6 General-purpose timers (TIM15/16/17) Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: 1. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only. 2. Program the input filter duration you need with respect to the signal you connect to the timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. 3. Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in the TIMx_CCER register (rising edge in this case). 4. Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the TIMx_CCMR1 register). 5. Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register. 6. If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register. When an input capture occurs: • The TIMx_CCR1 register gets the value of the counter on the active transition. • CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared. • An interrupt is generated depending on the CC1IE bit. • A DMA request is generated depending on the CC1DE bit. In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data. Note: IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. DocID024597 Rev 1 939/1680 1002 General-purpose timers (TIM15/16/17) 28.4.7 RM0351 PWM input mode (only for TIM15) This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. • One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): 1. Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected). 2. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P and CC1NP bits to ‘0’ (active on rising edge). 3. Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected). 4. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P and CC2NP bits to ‘1’ (active on falling edge). 5. Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register (TI1FP1 selected). 6. Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx_SMCR register. 7. Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register. Figure 315. PWM input mode timing 7, 7,0[B&17 7,0[B&&5 7,0[B&&5 ,&FDSWXUH ,&FDSWXUH UHVHWFRXQWHU ,&FDSWXUH SXOVHZLGWK PHDVXUHPHQW ,&FDSWXUH SHULRG PHDVXUHPHQW DL 1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only TI1FP1 and TI2FP2 are connected to the slave mode controller. 940/1680 DocID024597 Rev 1 RM0351 28.4.8 General-purpose timers (TIM15/16/17) Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=0 (OCx active high) => OCx is forced to high level. The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register. Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below. 28.4.9 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: • Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match. • Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register). • Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register). • Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection). The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register. In output compare mode, the update event UEV has no effect on OCxREF and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode). DocID024597 Rev 1 941/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Procedure 1. Select the counter clock (internal, external, prescaler). 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. 3. Set the CCxIE bit if an interrupt request is to be generated. 4. 5. Select the output mode. For example: – Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx – Write OCxPE = 0 to disable preload register – Write CCxP = 0 to select active high polarity – Write CCxE = 1 to enable the output Enable the counter by setting the CEN bit in the TIMx_CR1 register. The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 315. Figure 316. Output compare mode, toggle on OC1 :ULWH%KLQWKH&&5UHJLVWHU 7,0B&17 7,0B&&5 % $ % % % $ 2&5() 2& 0DWFKGHWHFWHGRQ&&5 ,QWHUUXSWJHQHUDWHGLIHQDEOHG 069 28.4.10 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register. 942/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers). Refer to the TIMx_CCER register description for more details. In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx ≤TIMx_CNT or TIMx_CNT ≤TIMx_CCRx (depending on the direction of the counter). The TIM15/16/17 are capable of upcounting only. Refer to Upcounting mode on page 929. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 317 shows some edgealigned PWM waveforms in an example where TIMx_ARR=8. Figure 317. Edge-aligned PWM waveforms (ARR=8) &RXQWHUUHJLVWHU &&5[ 2&;5() &&[,) 2&;5() &&5[ &&[,) 2&;5() µ¶ &&5[! &&[,) 2&;5() µ¶ &&5[ &&[,) 069 28.4.11 Combined PWM mode (TIM15 only) Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and delay are determined DocID024597 Rev 1 943/1680 1002 General-purpose timers (TIM15/16/17) RM0351 by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or AND logical combination of two reference PWMs: • OC1REFC (or OC2REFC) is controlled by the TIMx_CCR1 and TIMx_CCR2 registers Combined PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing ‘1100’ (Combined PWM mode 1) or ‘1101’ (Combined PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. When a given channel is used as a combined PWM channel, its complementary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2). Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones. Figure 318 represents an example of signals that can be generated using Asymmetric PWM mode, obtained with the following configuration: • Channel 1 is configured in Combined PWM mode 2, • Channel 2 is configured in PWM mode 1, Figure 318. Combined PWM mode on channel 1 and 2 2&¶ 2&¶ 2& 2& 2&5() 2&5() 2&5()¶ 2&5()¶ 2&5()& 2&5()&¶ 2&5()& 2&5()$1'2&5() 2&5()&¶ 2&5()¶252&5()¶ 069 944/1680 DocID024597 Rev 1 RM0351 28.4.12 General-purpose timers (TIM15/16/17) Complementary outputs and dead-time insertion The TIM15/16/17 general-purpose timers can output one complementary signal and manage the switching-off and switching-on of the outputs. This time is generally known as dead-time and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of levelshifters, delays due to power switches...) You can select the polarity of the outputs (main output OCx or complementary OCxN) independently for each output. This is done by writing to the CCxP and CCxNP bits in the TIMx_CCER register. The complementary signals OCx and OCxN are activated by a combination of several control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx, OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to Table 155: Output control bits for complementary OCx and OCxN channels with break feature on page 971 for more details. In particular, the dead-time is activated when switching to the idle state (MOE falling down to 0). Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit dead-time generator for each channel. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high: • The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge. • The OCxN output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge. If the delay is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated. The following figures show the relationships between the output signals of the dead-time generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1, CCxE=1 and CCxNE=1 in these examples) Figure 319. Complementary output with dead-time insertion. 2&[5() 2&[ GHOD\ 2&[1 GHOD\ 069 DocID024597 Rev 1 945/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Figure 320. Dead-time waveforms with delay greater than the negative pulse. 2&[5() 2&[ GHOD\ 2&[1 069 Figure 321. Dead-time waveforms with delay greater than the positive pulse. 2&[5() 2&[ 2&[1 GHOD\ 069 The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 28.5.15: TIM15 break and dead-time register (TIM15_BDTR) on page 974 for delay calculation. Re-directing OCxREF to OCx or OCxN In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER register. This allows you to send a specific waveform (such as PWM or static active level) on one output while the complementary remains at its inactive level. Other alternative possibilities are to have both outputs at inactive level or both outputs active and complementary with dead-time. Note: 946/1680 When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low. DocID024597 Rev 1 RM0351 28.4.13 General-purpose timers (TIM15/16/17) Using the break function The purpose of the break function is to protect power switches driven by PWM signals generated with the TIM15/16/17 timers. The break input is usually connected to fault outputs of power stages and 3-phase inverters. When activated, the break circuitry shuts down the PWM outputs and forces them to a predefined safe state. The break channel gathers both system-level fault (clock failure, parity error,...) and application fault (from input pins and built-in comparator), and can force the outputs to a predefined level (either active or inactive) after a deadtime duration. The output enable signal and output levels during break are depending on several control bits: • the MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event. • the OSSI bit in the TIMx_BDTR register defines whether the timer controls the output in inactive state or releases the control to the GPIO controller (typically to have it in Hi-Z mode) • the OISx and OISxN bits in the TIMx_CR2 register which are setting the output shutdown level, either active or inactive. The OCx and OCxN outputs cannot be set both to active level at a given time, whatever the OISx and OISxN values. Refer to Table 155: Output control bits for complementary OCx and OCxN channels with break feature on page 971 for more details. When exiting from reset, the break circuit is disabled and the MOE bit is low. The break function is enabled by setting the BKE bit in the TIMx_BDTR register. The break input polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1 APB clock period to correctly read back the bit after the write operation. Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit (accessed in the TIMx_BDTR register). It results in some delays between the asynchronous and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you must insert a delay (dummy instruction) before reading it correctly. This is because you write the asynchronous signal and read the synchronous signal. The break can be generated from multiple sources which can be individually enabled and with programmable edge sensitivity, using the TIMx_OR2 register. The sources for break (BRK) channel are: • An external source connected to one of the BKIN pin (as per selection done in the AFIO controller), with polarity selection and optional digital filtering • An internal source: – – the Cortex®-M4 LOCKUP output – – the PVD output – – the SRAM parity error signal – – a flash ECC error – – a clock failure event generated by the CSS detector – – the output from a comparator, with polarity selection and optional digital filtering – – the analog watchdog output of the DFSDM peripheral DocID024597 Rev 1 947/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Break events can also be generated by software using BG bit in the TIMx_EGR register. All sources are ORed before entering the timer BRK inputs, as per Figure 322 below. Figure 322. Break circuitry overview &RUH/RFNXS 39' /RFNXS/2&. 39'/2&. 6\VWHPEUHDNUHTXHVWV 5$0SDULW\(UURU (&&(UURU 6%,)IODJ 3DULW\/2&. (&&/2&. &66 %.,13 %.,1LQSXWV IURP$) FRQWUROOHU %.,1( 6RIWZDUHEUHDNUHTXHVWV%* %.&033 %.&03( &203RXWSXW %.)>@ %.( %,)IODJ %.3 %5.UHTXHVW %.&033 )LOWHU %.&03( &203RXWSXW $SSOLFDWLRQEUHDNUHTXHVWV %.')%.[( ')6'0 %5($.RXWSXW 06Y9 Note: An asynchronous (clockless) operation is only guaranteed when the programmable filter is disabled. If it is enabled, a fail safe clock mode (for example by using the internal PLL and/or the CSS) must be used to guarantee that break events are handled. When a break occurs (selected level on the break input): 948/1680 • The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or even releasing the control to the AFIO controller (selected by the OSSI bit). This feature functions even if the MCU oscillator is off. • Each output channel is driven with the level programmed in the OISx bit in the TIMx_CR2 register as soon as MOE=0. If OSSI=0, the timer releases the output control (taken over by the AFIO controller) else the enable output remains high. • When complementary outputs are used: – The outputs are first put in reset state inactive state (depending on the polarity). This is done asynchronously so that it works even if no clock is provided to the timer. – If the timer clock is still present, then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the OISx and OISxN bits after a dead-time. Even in this case, OCx and OCxN cannot be driven to their DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles). – Note: If OSSI=0 then the timer releases the enable outputs (taken over by the AFIO controller which forces a Hi-Z state) else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high. • The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be generated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if the BDE bit in the TIMx_DIER register is set. • If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again at the next update event UEV. This can be used to perform a regulation, for instance. Else, MOE remains low until you write it to ‘1’ again. In this case, it can be used for security and you can connect the break input to an alarm from power drivers, thermal sensors or any security components. The break inputs is acting on level. Thus, the MOE cannot be set while the break input is active (neither automatically nor by software). In the meantime, the status flag BIF cannot be cleared. The break can be generated by the BRK input which has a programmable polarity and an enable bit BKE in the TIMx_BDTR Register. In addition to the break input and the output management, a write protection has been implemented inside the break circuit to safeguard the application. It allows you to freeze the configuration of several parameters (dead-time duration, OCx/OCxN polarities and state when disabled, OCxM configurations, break enable and polarity). You can choose from 3 levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to Section 28.5.15: TIM15 break and dead-time register (TIM15_BDTR) on page 974. The LOCK bits can be written only once after an MCU reset. The Figure 323 shows an example of behavior of the outputs in response to a break. DocID024597 Rev 1 949/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Figure 323. Output behavior in response to a break %5($. 02( 2&[5() 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ GHOD\ GHOD\ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ GHOD\ GHOD\ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ 2&[1 &&[( &&[3 &&[1( &&[13 2,6[ 2,6[1 RU2,6[ 2,6[1 069 950/1680 DocID024597 Rev 1 RM0351 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be: • CNT < CCRx ≤ ARR (in particular, 0 < CCRx) Figure 324. Example of one pulse mode. 7, 2&5() 2& 7,0B$55 &RXQWHU 28.4.14 General-purpose timers (TIM15/16/17) 7,0B&&5 W'(/$< W38/6( W 069 For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin. Let’s use TI2FP2 as trigger 1: 1. Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register. 2. TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER register. 3. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in the TIMx_SMCR register. 4. TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register (trigger mode). DocID024597 Rev 1 951/1680 1002 General-purpose timers (TIM15/16/17) RM0351 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The tDELAY is defined by the value written in the TIMx_CCR1 register. • The tPULSE is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1). • Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1 register. You can optionally enable the preload registers by writing OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0’ in this example. You only want 1 pulse, so you write ‘1’ in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). Particular case: OCx fast enable In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get. If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode. 28.4.15 UIF bit remapping The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update Interrupt Flag UIF into bit 31 of the timer counter register (TIMxCNT[31]). This allows to atomically read both the counter value and a potential roll-over condition signaled by the UIFCPY flag. In particular cases, it can ease the calculations by avoiding race conditions caused for instance by a processing shared between a background task (counter reading) and an interrupt (Update Interrupt). There is no latency between the assertions of the UIF and UIFCPY flags. 952/1680 DocID024597 Rev 1 RM0351 28.4.16 General-purpose timers (TIM15/16/17) Timer input XOR function (TIM15 only) The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the two input pins TIMx_CH1 and TIMx_CH2. The XOR output can be used with all the timer input functions such as trigger or input capture. It is useful for measuring the interval between the edges on two input signals, as shown in Figure 325. Figure 325. Measuring time interval between edges on 2 signals 7, 7, 7,;257, &RXQWHU 069 DocID024597 Rev 1 953/1680 1002 General-purpose timers (TIM15/16/17) 28.4.17 RM0351 External trigger synchronization (TIM15 only) The TIM timers are linked together internally for timer synchronization or chaining. The TIM15 timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated. In the following example, the upcounter is cleared in response to a rising edge on TI1 input: 1. Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=’0’ and CC1NP=’0’ in the TIMx_CCER register to validate the polarity (and detect rising edges only). 2. Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. 3. Start the counter by writing CEN=1 in the TIMx_CR1 register. The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register). The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. Figure 326. Control circuit in reset mode 7, 8* &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 954/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: 1. Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write CC1P=1 and CC1NP = ‘0’ in the TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. 3. Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level). The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops. The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input. Figure 327. Control circuit in gated mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 DocID024597 Rev 1 955/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: 1. Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write CC2P=’1’ and CC2NP=’0’ in the TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in trigger mode by writing SMS=110 in the TIMx_SMCR register. Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 328. Control circuit in trigger mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 28.4.18 Slave mode: Combined reset + trigger mode In this case, a rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers, and starts the counter. This mode is used for one-pulse mode. 28.4.19 DMA burst mode The TIMx timers have the capability to generate multiple DMA requests on a single event. The main purpose is to be able to re-program several timer registers multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals. The DMA controller destination is unique and must point to the virtual register TIMx_DMAR. On a given timer event, the timer launches a sequence of DMA requests (burst). Each write into the TIMx_DMAR register is actually redirected to one of the timer registers. 956/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers (either in half-words or in bytes). The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: TIMx_SMCR, For example, the timer DMA burst feature could be used to update the contents of the CCRx registers (x = 2, 3, 4) on an update event, with the DMA transferring half words into the CCRx registers. This is done in the following steps: 1. Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into the CCRx registers. – Number of data to transfer = 3 (See note below). – Circular mode disabled. 2. Configure the DCR register by configuring the DBA and DBL bit fields as follows: DBL = 3 transfers, DBA = 0xE. 3. Enable the TIMx update DMA request (set the UDE bit in the DIER register). 4. Enable TIMx 5. Enable the DMA channel This example is for the case where every CCRx register is to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer should be 6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4. 28.4.20 Debug mode When the microcontroller enters debug mode (Cortex®-M4 core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module. For more details, refer to Section 44.16.2: Debug support for timers, RTC, watchdog, bxCAN and I2C. DocID024597 Rev 1 957/1680 1002 General-purpose timers (TIM15/16/17) 28.5 RM0351 TIM15 registers Refer to Section 1.1 for a list of abbreviations used in register descriptions. 28.5.1 TIM15 control register 1 (TIM15_CR1) Address offset: 0x00 Reset value: 0x0000 15 Res. 14 Res. 13 Res. 12 11 10 Res. UIF REMAP Res. rw 9 8 CKD[1:0] rw 7 6 5 4 3 2 1 0 ARPE Res. Res. Res. OPM URS UDIS CEN rw rw rw rw rw rw Bits 15:12 Reserved, must be kept at reset value. Bit 11 UIFREMAP: UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. Bit 10 Reserved, must be kept at reset value. Bits 9:8 CKD[1:0]: Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx) 00: tDTS = tCK_INT 01: tDTS = 2*tCK_INT 10: tDTS = 4*tCK_INT 11: Reserved, do not program this value Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered Bits 6:4 Reserved, must be kept at reset value. Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) 958/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt if enabled Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 28.5.2 TIM15 control register 2 (TIM15_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 Res. Res. Res. Res. Res. OIS2 OIS1N OIS1 TI1S rw rw rw rw 6 5 4 MMS[2:0] rw rw rw 3 2 1 0 CCDS CCUS Res. CCPC rw rw rw Bits 15:11 Reserved, must be kept at reset value. Bit 10 OIS2: Output idle state 2 (OC2 output) 0: OC2=0 when MOE=0 1: OC2=1 when MOE=0 Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIMx_BKR register). Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register). Bit 8 OIS1: Output Idle state 1 (OC1 output) 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register). DocID024597 Rev 1 959/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination) Bits 6:4 MMS[1:0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). 100: Compare - OC1REF signal is used as trigger output (TRGO). 101: Compare - OC2REF signal is used as trigger output (TRGO). Bit 3 CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. Note: This bit acts only on channels that have a complementary output. Bit 1 Reserved, must be kept at reset value. Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). Note: This bit acts only on channels that have a complementary output. 960/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) 28.5.3 TIM15 slave mode control register (TIM15_SMCR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SMS[3] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Res. Res. Res. Res. Res. Res. Res. Res. MSM rw rw TS[2:0] rw rw Res. rw 0 SMS[2:0] rw rw rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 SMS[3]: Slave mode selection - bit 3 Refer to SMS description - bits 2:0 Bits 15:8 Reserved, must be kept at reset value. Bit 7 MSM: Master/slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. Bits 6:4 TS[2:0]: Trigger selection This bit field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) See Table 154: TIMx Internal trigger connection on page 962 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. Bit 3 Reserved, must be kept at reset value. DocID024597 Rev 1 961/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 0000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock. 0001: Reserved 0010: Reserved 0011: Reserved 0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. Table 154. TIMx Internal trigger connection 28.5.4 Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011) TIM15 TIM1 TIM3 TIM16 OC1 TIM17 OC1 TIM15 DMA/interrupt enable register (TIM15_DIER) Address offset: 0x0C Reset value: 0x0000 15 Res. 14 13 12 11 TDE COMD E Res. Res. rw rw 10 9 CC2DE CC1DE rw rw 8 7 6 5 4 3 2 1 0 UDE BIE TIE COMIE Res. Res. CC2IE CC1IE UIE rw rw rw rw rw rw rw Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled Bit 13 COMDE: COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled Bits 12:11 Reserved, must be kept at reset value. 962/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled Bit 7 BIE: Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled 1: Trigger interrupt enabled Bit 5 COMIE: COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled Bits 4:3 Reserved, must be kept at reset value. Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 28.5.5 TIM15 status register (TIM15_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 Res. Res. Res. Res. Res. 10 9 CC2OF CC1OF rc_w0 rc_w0 8 7 6 5 4 3 2 1 0 Res. BIF TIF COMIF Res. Res. CC2IF CC1IF UIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:11 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/Compare 2 overcapture flag Refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set DocID024597 Rev 1 963/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Bit 8 Reserved, must be kept at reset value. Bit 7 BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred 1: An active level has been detected on the break input Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0: No trigger event occurred 1: Trigger interrupt pending Bit 5 COMIF: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software. 0: No COM event occurred 1: COM interrupt pending Bits 5:3 Reserved, must be kept at reset value. Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow. If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity) Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. – When CNT is reinitialized by a trigger event (refer to Section 28.5.3: TIM15 slave mode control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 964/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) 28.5.6 TIM15 event generation register (TIM15_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. BG TG COMG Res. Res. CC2G CC1G UG w w rw w w w Bits 15:8 Reserved, must be kept at reset value. Bit 7 BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits Note: This bit acts only on channels that have a complementary output. Bits 4:3 Reserved, must be kept at reset value. Bit 2 CC2G: Capture/Compare 2 generation Refer to CC1G description Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). DocID024597 Rev 1 965/1680 1002 General-purpose timers (TIM15/16/17) 28.5.7 RM0351 TIM15 capture/compare mode register 1 (TIM15_CCMR1) Address offset: 0x18 Reset value: 0x0000 0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage. 31 Res. 30 Res. 15 14 Res 29 Res. 13 28 Res. 12 OC2M[2:0] IC2F[3:0] rw rw rw 27 Res. 26 Res. 11 10 OC2 PE OC2 FE 25 24 Res. OC2M [3] 9 23 Res. 22 Res. rw rw Res. 20 Res. Res. 18 Res. 17 16 Res. OC1M [3] Res. rw rw 8 CC2S[1:0] 7 6 Res 5 4 OC1M[2:0] IC1F[3:0] rw 19 Res. IC2PSC[1:0] rw 21 rw rw rw rw 3 2 OC1 PE OC1 FE 1 0 CC1S[1:0] IC1PSC[1:0] rw rw rw rw rw Output compare mode: Bits 31:25 Reserved, always read as 0 Bit 24 OC2M[3]: Output Compare 2 mode - bit 3 Bits 23:17 Reserved, always read as 0 Bit 16 OC1M[3]: Output Compare 1 mode - bit 3 refer to OC1M description on bits 6:4 Bit 15 Reserved, always read as 0 Bits 14:12 OC2M[2:0]: Output Compare 2 mode Bit 11 OC2PE: Output Compare 2 preload enable Bit 10 OC2FE: Output Compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1. 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER). Bit 7 Reserved, always read as 0 966/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0100: Force inactive level - OC1REF is forced low. 0101: Force active level - OC1REF is forced high. 0110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 28.5.16 TIM15 DMA control register (TIM15_DCR) Address offset: 0x48 Reset value: 0x0000 15 14 13 Res Res Res 12 11 10 9 8 DBL[4:0] rw rw rw rw 7 6 5 Res Res Res rw 4 3 2 1 0 rw rw DBA[4:0] rw rw rw Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers. Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 DBA[4:0]: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: TIMx_SMCR, ... 28.5.17 TIM15 DMA address for full transfer (TIM15_DMAR) Address offset: 0x4C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DMAB[15:0] rw 976/1680 rw rw rw rw rw rw rw rw DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 28.5.18 TIM15 option register 1 (TIM15_OR1) Address offset: 0x50 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Res Res Res Res Res Res Res Res Res Res Res Res Res 0 ENCODER_ MODE[1:0] rw TI1_ RMP rw rw Bits 31:3 Reserved, must be kept at reset value. Bits 2:1 ENCODER_MODE[1:0]: Encoder mode 00: No redirection 01:TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively 10:TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively 11:TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively Bit 0 TI1_RMP: Input capture 1 remap 0: TIM15 input capture 1 is connected to I/O 1: TIM15 input capture 1 is connected to LSE 28.5.19 TIM15 option register 2 (TIM15_OR2) Address offset: 0x60 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res BKCM P2P BKCM P1P BKINP BKDF BK0E Res. BKCM P2E BKCM P1E BKINE rw rw rw rw rw rw rw Res Res Res Res Res Res. Res. Bits 31:12 Reserved, must be kept at reset value. DocID024597 Rev 1 977/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Bit 11 BKCMP2P: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP2 input is active low 1: COMP2 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 10 BKCMP1P: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active low 1: COMP1 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 9 BKINP: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active low 1: BKIN input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 8 BKDFBK0E: BRK DFSDM_BREAK[0] enable This bit enables the DFSDM_BREAK[0] for the timer’s BRK input. DFSDM_BREAK[0] output is ‘ORed’ with the other BRK sources. 0: DFSDM_BREAK[0]input disabled 1: DFSDM_BREAK[0]input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 7:3 Reserved, must be kept at reset value Bit 2 BKCMP2E: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is ‘ORed’ with the other BRK sources. 0: COMP2 input disabled 1: COMP2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 1 BKCMP1E: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is ‘ORed’ with the other BRK sources. 0: COMP1 input disabled 1: COMP1 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 978/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) Bit 0 BKINE: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is ‘ORed’ with the other BRK sources. 0: BKIN input disabled 1: BKIN input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 28.5.20 TIM15 register map TIM15 registers are mapped as 16-bit addressable registers as described in the table below: Reset value 0 0 0 CC2S [1:0] 0 0 0 IC1F[3:0] 0 0 0 0 OPM URS UDIS CEN CCUS Res CCPC 0 UIF 0 CC1IF 0 CC2IF UIE 0 CC1IE 0 CC2IE 0 0 0 0 UG 0 SMS[2:0] 0 CC1G 0 0 CC2G 0 0 0 0 0 OC1FE OC1M [2:0] CCDS Res Res Res 0 Res COMIE COMIF COMG 0 0 Res TI1S TIF 0 0 IC2 PSC [1:0] 0 TG TIE 0 0 0 Res OIS1 Res MSM BIE 0 BIF UDE 0 0 BG Res CC2S [1:0] 0 Res 0 Res 0 CC1OF 0 CC2OF CC1DE 0 CC2DE 0 0 OC2FE 0 IC2F[3:0] 0 DocID024597 Rev 1 0 0 0 OC2PE Res 0 Res Res Res Res Res Res Res 0 Res Res Res Res Res Res Res OC1M[3] Res Res Res Res Res Res Res OC2M[3] Res Res Res Res Res Res Res 0 Res Reset value TIM15_CCMR1 Input Capture mode Res 0x18 OC2M [2:0] 0 0 0 0 TS[2:0] 0 Reset value TIM15_CCMR1 Output Compare mode 0 0 Res OIS2 OIS1N 0 Res 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM15_EGR 0 Res Res Res Res Res Res COMDE 0 Reset value 0x14 0 Res Res Res Res TDE 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM15_SR Res Reset value 0x10 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM15_DIER Res 0x0C 0 0 Res Reset value SMS[3] Res Res Res Res Res Res Res Res Res Res Res Res Res TIM15_SMCR Res 0x08 Res Reset value MMS[2:0] 0 CC1S [1:0] 0 0 0 Res 0 OC1PE 0 Res 0 Res 0 Res ARPE UIFREMAP Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM15_CR2 Res 0x04 Res Reset value CKD [1:0] Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM15_CR1 Res 0x00 Register Res Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 156. TIM15 register map and reset values 0 IC1 PSC [1:0] CC1S [1:0] 0 0 0 0 979/1680 1002 0x50 980/1680 TIM15_OR1 Reset value DocID024597 Rev 1 0 0 0 0 0 0 0 0 0 0 0 0 Res Res Res Res Res Res Res Res Res Res BKE OSSR OSSI 0 0 0 0 0 0 0 0 0 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 0 0 Reset value Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res UIFCPY or Res. Res Res 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 DBL[4:0] 0 0 0 Res 0 0 0 Res 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 CC2E CC1NP 0 0 CNT[15:0] 0 0 0 0 0 0 0 PSC[15:0] 0 ARR[15:0] 0 0 0 0 CC1E CC2P 0 CC1P CC2NE 0 CC1NE CC2NP Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 CCR1[15:0] CCR2[15:0] DT[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TI1_RMP BKP 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value ENCODER_MODE[1:0] 0 Res Reset value AOE Reset value LOCK [1:0] Res Reset value MOE Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value Res Res Res Res Res Res Res Res Res Res Res Res TIM15_DMAR Res TIM15_DCR Res TIM15_BDTR Res TIM15_CCR2 Res 0x4C TIM15_CCR1 Res 0x48 TIM15_RCR Res 0x44 TIM15_PSC Res 0x38 0 Res 0x34 TIM15_ARR Res 0x30 Reset value Res 0x2C Res 0x28 TIM15_CNT Res 0x24 TIM15_CCER Res 0x20 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res Offset Res General-purpose timers (TIM15/16/17) RM0351 Table 156. TIM15 register map and reset values (continued) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REP[7:0] DBA[4:0] DMAB[15:0] 0 0 0 0 0 0 0 0 0 0 RM0351 General-purpose timers (TIM15/16/17) BKCMP1E BKINE Res BKCMP2E 0 Res 0 Res BKDFBK0E 0 Res BKINP 0 Res BKCMP1P Res Res Res BKCMP2P Reset value Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM15_OR2 Res 0x60 Register Res Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 156. TIM15 register map and reset values (continued) 0 0 1 Refer to Section 2.2 on page 66 for the register boundary addresses. DocID024597 Rev 1 981/1680 1002 General-purpose timers (TIM15/16/17) 28.6 RM0351 TIM16&TIM17 registers Refer to Section 1.1 on page 61 for a list of abbreviations used in register descriptions. 28.6.1 TIM16&TIM17 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 Res 14 Res 13 Res 12 11 10 Res UIF REMAP Res rw 9 8 CKD[1:0] rw 7 6 5 4 3 2 1 0 ARPE Res Res Res OPM URS UDIS CEN rw rw rw rw rw rw Bits 15:12 Reserved, must be kept at reset value. Bit 11 UIFREMAP: UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. Bit 10 Reserved, must be kept at reset value. Bits 9:8 CKD[1:0]: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx), 00: tDTS=tCK_INT 01: tDTS=2*tCK_INT 10: tDTS=4*tCK_INT 11: Reserved, do not program this value Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered Bits 6:4 Reserved, must be kept at reset value. Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. 982/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 28.6.2 TIM16&TIM17 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res OIS1N OIS1 Res Res Res Res CCDS CCUS Res CCPC rw rw rw rw rw Bits 15:10 Reserved, must be kept at reset value. Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register). Bit 8 OIS1: Output Idle state 1 (OC1 output) 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register). Bits 7:4 Reserved, must be kept at reset value. Bit 3 CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. Note: This bit acts only on channels that have a complementary output. Bit 1 Reserved, must be kept at reset value. DocID024597 Rev 1 983/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. Note: This bit acts only on channels that have a complementary output. 28.6.3 TIM16&TIM17 DMA/interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res TDE COMDE Res Res Res CC1DE UDE BIE TIE COMIE Res Res Res CC1IE UIE rw rw rw rw rw rw rw rw rw Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled Bit 13 COMDE: COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled Bits 12:10 Reserved, must be kept at reset value. Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled Bit 7 BIE: Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled 1: Trigger interrupt enabled Bit 5 COMIE: COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled Bits 4:2 Reserved, must be kept at reset value. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 984/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) 28.6.4 TIM16&TIM17 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res CC1OF Res BIF TIF COMIF Res Res Res CC1IF UIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:10 Reserved, must be kept at reset value. Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bit 8 Reserved, must be kept at reset value. Bit 7 BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred 1: An active level has been detected on the break input Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is cleared by software. 0: No trigger event occurred 1: Trigger interrupt pending Bit 5 COMIF: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software. 0: No COM event occurred 1: COM interrupt pending Bits 4:2 Reserved, must be kept at reset value. Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity) DocID024597 Rev 1 985/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. – When CNT is reinitialized by a trigger event (refer to Section 28.5.3: TIM15 slave mode control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 28.6.5 TIM16&TIM17 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res BG TG COMG Res Res Res CC1G UG w w w w w Bits 15:8 Reserved, must be kept at reset value. Bit 7 BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits Note: This bit acts only on channels that have a complementary output. Bits 4:2 Reserved, must be kept at reset value. Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. 986/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). 28.6.6 TIM16&TIM17 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res OC1M [3] Res rw 15 14 13 12 11 10 9 8 Res Res Res Res Res Res Res Res 7 6 Res 5 4 OC1M[2:0] rw rw 2 OC1PE OC1FE IC1F[3:0] rw 3 IC1PSC[1:0] rw rw rw 1 0 CC1S[1:0] rw rw Output compare mode: Bits 31:17 Reserved, always read as 0 Bit 16 OC1M[3]: Output Compare 1 mode (bit 3) Bits 15:7 Reserved DocID024597 Rev 1 987/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Bits 6:4 OC1M[2:0]: Output Compare 1 mode (bits 2 to 0) These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0100: Force inactive level - OC1REF is forced low. 0101: Force active level - OC1REF is forced high. 0110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). DocID024597 Rev 1 995/1680 1002 General-purpose timers (TIM15/16/17) 28.6.14 RM0351 TIM16&TIM17 DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 15 14 13 Res Res Res 12 11 10 9 8 DBL[4:0] rw rw rw rw 7 6 5 Res Res Res rw 4 3 2 1 0 rw rw DBA[4:0] rw rw rw Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers. Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 DBA[4:0]: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: TIMx_SMCR, ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 28.6.15 TIM16&TIM17 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DMAB[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 28.6.16 TIM16 option register 1 (TIM16_OR1) Address offset: 0x50 996/1680 DocID024597 Rev 1 RM0351 General-purpose timers (TIM15/16/17) Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Res Res Res Res Res Res Res Res Res Res Res Res Res Res TI1_RMP[1:0] rw rw Bits 31:2 Reserved, must be kept at reset value. Bits1:0 TI1_RMP[1:0]: Input capture 1 remap 00: TIM16 input capture 1 is connected to I/O 01: TIM16 input capture 1 is connected to LSI 10: TIM16 input capture 1 is connected to LSE 11: TIM16 input capture 1 is connected to RTC wakeup interrupt 28.6.17 TIM16 option register 2 (TIM16_OR2) Address offset: 0x60 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res BKCM P2P BKCM P1P BKINP BKDF BK1E Res BKCM P2E BKCM P1E BKINE rw rw rw rw rw rw rw Res Res Res Res Res Res Res Bits 31:12 Reserved, must be kept at reset value. Bit 11 BKCMP2P: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP2 input is active low 1: COMP2 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 10 BKCMP1P: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active low 1: COMP1 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). DocID024597 Rev 1 997/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Bit 9 BKINP: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active low 1: BKIN input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 8 BKDFBK1E: BRK DFSDM_BREAK[1] enable This bit enables the DFSDM_BREAK[1] for the timer’s BRK input. DFSDM_BREAK[1] output is ‘ORed’ with the other BRK sources. 0: DFSDM_BREAK[1] input disabled 1: DFSDM_BREAK[1] input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 7:3 Reserved, must be kept at reset value Bit 2 BKCMP2E: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is ‘ORed’ with the other BRK sources. 0: COMP2 input disabled 1: COMP2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 1 BKCMP1E: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is ‘ORed’ with the other BRK sources. 0: COMP1 input disabled 1: COMP1 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 0 BKINE: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is ‘ORed’ with the other BRK sources. 0: BKIN input disabled 1: BKIN input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 28.6.18 TIM17 option register 1 (TIM17_OR1) Address offset: 0x50 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Res Res Res Res Res Res Res Res Res Res Res Res Res Res TI1_RMP[1:0] rw 998/1680 DocID024597 Rev 1 rw RM0351 General-purpose timers (TIM15/16/17) Bits 31:2 Reserved, must be kept at reset value. Bits1:0 TI1_RMP[1:0]: Input capture 1 remap 00: TIM17 input capture 1 is connected to I/O 01: TIM17 input capture 1 is connected to MSI 10: TIM17 input capture 1 is connected to HSE/32 11: TIM17 input capture 1 is connected to MCO 28.6.19 TIM17 option register 2 (TIM17_OR2) Address offset: 0x60 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res BKCM P2P BKCM P1P BKINP BKDF BK2E Res BKCM P2E BKCM P1E BKINE rw rw rw rw rw rw rw Res Res Res Res Res Res Res Bits 31:12 Reserved, must be kept at reset value. Bit 11 BKCMP2P: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP2 input is active low 1: COMP2 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 10 BKCMP1P: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active low 1: COMP1 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 9 BKINP: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active low 1: BKIN input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). DocID024597 Rev 1 999/1680 1002 General-purpose timers (TIM15/16/17) RM0351 Bit 8 BKDFBK2E: BRK DFSDM_BREAK[2] enable This bit enables the DFSDM_BREAK[2] for the timer’s BRK input. DFSDM_BREAK[2] output is ‘ORed’ with the other BRK sources. 0: DFSDM_BREAK[2] input disabled 1: DFSDM_BREAK[2] input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bits 7:3 Reserved, must be kept at reset value Bit 2 BKCMP2E: BRK COMP2 enable This bit enables the COMP2 for the timer’s BRK input. COMP2 output is ‘ORed’ with the other BRK sources. 0: COMP2 input disabled 1: COMP2 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 1 BKCMP1E: BRK COMP1 enable This bit enables the COMP1 for the timer’s BRK input. COMP1 output is ‘ORed’ with the other BRK sources. 0: COMP1 input disabled 1: COMP1 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 0 BKINE: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is ‘ORed’ with the other BRK sources. 0: BKIN input disabled 1: BKIN input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 1000/1680 DocID024597 Rev 1 0x24 TIMx_CNT Reset value 0 DocID024597 Rev 1 0 0 0 0 0 0 0 0 0 0 0 0 0 IC1F[3:0] Reset value 0 OC1FE 0 0 0 0 0 0 0 0 CNT[15:0] CC1E 0 OC1M [2:0] CC1P 0 CC1NE 0 OC1PE 0 CC1IF UIF 0 UG Res Res 0 CC1G Res Res Res 0 Res 0 CC1IE UIE Res Res Res COMIE COMIF Res ARPE OPM URS UDIS CEN 0 0 0 CCUS Res CCPC Res Res Res 0 CCDS Res Res Res Res Res OIS1 Res 0 OIS1N UIFREMAP 0 Res Res Res 0 CC1NP 0 Res Reset value 0 COMG Reset value Res TIE 0 TIF BIE 0 TG UDE 0 BIF 0 BG Res 0 Res Res Res CC1DE 0 CC1OF Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res CKD [1:0] 0 Res Res Res Res Res Reset value Res Res Res Res COMDE Res Reset value Res Res Res Res Res TDE Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Res Res Res Res OC1M[3] Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value Res Res Res Res Res Res Res Res Res Res Res TIMx_CCER Res 0x20 Res TIMx_CCMR1 Input Capture mode Res TIMx_CCMR1 Output Compare mode Res 0x18 TIMx_EGR Res 0x14 TIMx_SR Res 0x10 TIMx_DIER Res TIMx_CR2 Res 0x04 Res 0x0C TIMx_CR1 Res 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res Offset Res 28.6.20 UIFCPY or Res. RM0351 General-purpose timers (TIM15/16/17) TIM16&TIM17 register map TIM16&TIM17 registers are mapped as 16-bit addressable registers as described in the table below: Table 158. TIM16&TIM17 register map and reset values 0 0 0 0 0 0 0 CC1 S [1:0] 0 0 0 0 IC1 PSC [1:0] CC1 S [1:0] 0 0 0 0 0 0 0 0 1001/1680 1002 0x60 TIM17_OR2 1002/1680 DocID024597 Rev 1 BKINP BKDFBK2E 0 0 0 0 0 0 BKINE DMAB[15:0] 0 0 0 0 0 0 0 0 0 TI1_ RMP [1:0] Res 0 Res 0 BKCMP1E 0 Res 0 BKCMP2E 0 0 0 1 Res DT[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 BKINE 0 Res CCR1[15:0] 0 0 BKCMP1E 0 0 Res 0 0 Res DBL[4:0] 0 Res 0 0 BKCMP2E 0 Res 0 Res 0 Res 0 0 Res 0 0 0 Res 0 0 Res 0 Res Res Res Res Res Res Res 0 Res Reset value 0 Res 0 Res 0 Res 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Res 0 0 Res 0 Res 0 Res OSSI 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Res OSSR 0 Res BKE 0 0 Res BKDFBK1E 0 Res 0 0 Res BKINP 0 Res 0 0 Res Reset value BKCMP1P 0 0 Res 0 0 Res BKCMP1P BKP 0 Res 0 Res AOE 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Res 0 Res Reset value Res BKCMP2P Res Res 0 Res Res Res 0 Res Res 0 0 0 Res BKCMP2P Reset value MOE Res Res Res Res Res Res Res Res Res Res Res 0 0 Res Reset value LOC K [1:0] Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value Res Res Res Res Res Res Res Res Res Res Res Res TIM17_OR1 Res TIM16_OR2 Res TIM16_OR1 Res TIMx_DMAR Res TIMx_DCR Res 0x48 Res 0x50 TIMx_BDTR Res 0x60 TIMx_CCR1 Res 0x50 TIMx_RCR Res 0x30 Res 0x4C TIMx_ARR Res 0x2C Res 0x44 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIMx_PSC Res 0x28 Res 0x34 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res Offset Res General-purpose timers (TIM15/16/17) RM0351 Table 158. TIM16&TIM17 register map and reset values (continued) PSC[15:0] ARR[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 REP[7:0] DBA[4:0] Reset value Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. 0 0 TI1_ RMP [1:0] 0 0 1 RM0351 Basic timers (TIM6/TIM7) 29 Basic timers (TIM6/TIM7) 29.1 TIM6/TIM7 introduction The basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used as generic timers for time-base generation but they are also specifically used to drive the digital-to-analog converter (DAC). In fact, the timers are internally connected to the DAC and are able to drive it through their trigger outputs. The timers are completely independent, and do not share any resources. 29.2 TIM6/TIM7 main features Basic timer (TIM6/TIM7) features include: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535 • Synchronization circuit to trigger the DAC • Interrupt/DMA generation on the update event: counter overflow Figure 329. Basic timer block diagram 7ULJJHU FRQWUROOHU ,QWHUQDOFORFN &.B,17 7,0[&/.IURP5&& &RQWURO &.B&17 5HVHWHQDEOH&RXQW 8, 6WRSFOHDURUXS 36& SUHVFDOHU WR'$& $XWRUHORDGUHJLVWHU 8 &.B36& 75*2 8 &17FRXQWHU 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW '0$RXWSXW 069 DocID024597 Rev 1 1003/1680 1015 Basic timers (TIM6/TIM7) RM0351 29.3 TIM6/TIM7 functional description 29.3.1 Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: • Counter Register (TIMx_CNT) • Prescaler Register (TIMx_PSC) • Auto-Reload Register (TIMx_ARR) The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to write or read the auto-reload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set. Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 330 and Figure 331 give some examples of the counter behavior when the prescaler ratio is changed on the fly. 1004/1680 DocID024597 Rev 1 RM0351 Basic timers (TIM6/TIM7) Figure 330. Counter timing diagram with prescaler division change from 1 to 2 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW 8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 Figure 331. Counter timing diagram with prescaler division change from 1 to 4 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW 8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 DocID024597 Rev 1 1005/1680 1015 Basic timers (TIM6/TIM7) 29.3.2 RM0351 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller). The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent). When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit): • The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register) • The auto-reload shadow register is updated with the preload value (TIMx_ARR) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36. Figure 332. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 1006/1680 DocID024597 Rev 1 RM0351 Basic timers (TIM6/TIM7) Figure 333. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 334. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID024597 Rev 1 1007/1680 1015 Basic timers (TIM6/TIM7) RM0351 Figure 335. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 336. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 1008/1680 DocID024597 Rev 1 RM0351 Basic timers (TIM6/TIM7) Figure 337. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) ) ) ) &RXQWHURYHUIORZ 8SGDWHHYHQW 8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU ) $XWRUHORDGVKDGRZ UHJLVWHU ) :ULWHDQHZYDOXHLQ7,0[B$55 29.3.3 069 UIF bit remapping The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update Interrupt Flag UIF into the timer counter register’s bit 31 (TIMxCNT[31]). This allows to atomically read both the counter value and a potential roll-over condition signaled by the UIFCPY flag. In particular cases, it can ease the calculations by avoiding race conditions caused for instance by a processing shared between a background task (counter reading) and an interrupt (Update Interrupt). There is no latency between the assertions of the UIF and UIFCPY flags. 29.3.4 Clock source The counter clock is provided by the Internal clock (CK_INT) source. The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 338 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. DocID024597 Rev 1 1009/1680 1015 Basic timers (TIM6/TIM7) RM0351 Figure 338. Control circuit in normal mode, internal clock divided by 1 ,QWHUQDOFORFN &(1 &17B(1 8* &17B,1,7 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 069 29.3.5 Debug mode When the microcontroller enters the debug mode (Cortex®-M4 core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module. For more details, refer to Section 44.16.2: Debug support for timers, RTC, watchdog, bxCAN and I2C. 29.4 TIM6/TIM7 registers Refer to Section 1.1 on page 61 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 29.4.1 TIM6/TIM7 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 Res 14 Res 13 Res 12 11 10 9 8 7 6 5 4 3 2 1 0 Res UIF REMAP Res Res Res ARPE Res Res Res OPM URS UDIS CEN rw rw rw rw rw rw Bits 15:12 Reserved, must be kept at reset value. Bit 11 UIFREMAP: UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. Bits 10:8 Reserved, must be kept at reset value. 1010/1680 DocID024597 Rev 1 RM0351 Basic timers (TIM6/TIM7) Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. Bits 6:4 Reserved, must be kept at reset value. Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the CEN bit). Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. DocID024597 Rev 1 1011/1680 1015 Basic timers (TIM6/TIM7) 29.4.2 RM0351 TIM6/TIM7 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 Res Res Res Res Res Res Res Res Res 6 5 4 MMS[2:0] rw rw 3 2 1 0 Res Res Res Res rw Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). 010: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. Bits 3:0 Reserved, must be kept at reset value. 29.4.3 TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res UDE Res Res Res Res Res Res Res UIE rw Bits 15:9 Reserved, must be kept at reset value. Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled. Bits 7:1 Reserved, must be kept at reset value. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled. 1012/1680 DocID024597 Rev 1 rw RM0351 Basic timers (TIM6/TIM7) 29.4.4 TIM6/TIM7 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 UIF rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register. 29.4.5 TIM6/TIM7 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res UG w Bits 15:1 Reserved, must be kept at reset value. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected). 29.4.6 TIM6/TIM7 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UIF CPY Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw r 15 CNT[15:0] rw rw rw rw rw rw rw rw rw DocID024597 Rev 1 1013/1680 1015 Basic timers (TIM6/TIM7) RM0351 Bit 31 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. Bits 30:16 Reserved, must be kept at reset value. Bits 15:0 CNT[15:0]: Counter value 29.4.7 TIM6/TIM7 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PSC[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. 29.4.8 TIM6/TIM7 auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ARR[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Prescaler value ARR is the value to be loaded into the actual auto-reload register. Refer to Section 29.3.1: Time-base unit on page 1004 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 1014/1680 DocID024597 Rev 1 0x2C TIMx_ARR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0x180x20 Res Res Res Res Res Res Res Res Res Res Reset value Reset value DocID024597 Rev 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value Reset value UIF Res Res 0 UG Res Res Res Res Res Res UIE URS UDIS CEN OPM Res Res Res ARPE Res Res Res UIFREMAP Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Res Res Res 0 Res 0 Res Reserved 0 Res MMS [2:0] Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Res Res Res Res Reset value Res Res UDE Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0 Res Res Res Res Reset value Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Reset value Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0x08 Res Res Res Res Res TIMx_PSC Res 0 Res Reset value Res TIMx_CNT Res TIMx_EGR Res 0x28 TIMx_SR Res 0x24 TIMx_DIER Res 0x14 TIMx_CR2 Res 0x10 TIMx_CR1 Res 0x0C UIFCPY or Res. 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res 0x00 Res Offset Res 29.4.9 Res RM0351 Basic timers (TIM6/TIM7) TIM6/TIM7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 159. TIM6/TIM7 register map and reset values 0 0 0 0 0 0 Reserved CNT[15:0] PSC[15:0] ARR[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. 1015/1680 1015 Low-power timer (LPTIM) RM0351 30 Low-power timer (LPTIM) 30.1 Introduction The LPTIM is a 16-bit timer that benefits from the ultimate developments in power consumption reduction. Thanks to its diversity of clock sources, the LPTIM is able to keep running whatever the selected power mode. Given its capability to run even with no internal clock source, the LPTIM can be used as a “Pulse Counter” which can be useful in some applications. Also, the LPTIM capability to wake up the system from low-power modes, makes it suitable to realize “Timeout functions” with extremely low power consumption. The LPTIM introduces a flexible clock scheme that provides the needed functionalities and performance, while minimizing the power consumption. 30.2 30.3 LPTIM main features • 16 bit upcounter • 3-bit prescaler with 8 possible dividing factor (1,2,4,8,16,32,64,128) • Selectable clock – Internal clock sources: LSE, LSI, HSI16 or APB clock – External clock source over ULPTIM input (working with no LP oscillator running, used by Pulse Counter application) • 16 bit ARR autoreload register • 16 bit compare register • Continuous/one shot mode • Selectable software/hardware input trigger • Programmable Digital Glitch filter • Configurable output: Pulse, PWM • Configurable I/O polarity • Encoder mode LPTIM implementation Table 160 describes LPTIM implementation on STM32L4xx devices: the full set of features is implemented in LPTIM1. LPTIM2 supports a smaller set of features, but is otherwise identical to LPTIM1. Table 160. STM32L4xx LPTIM features LPTIM modes/features(1) Encoder mode 1. X = supported. 1016/1680 DocID024597 Rev 1 LPTIM1 LPTIM2 X - RM0351 Low-power timer (LPTIM) 30.4 LPTIM functional description 30.4.1 LPTIM block diagram Figure 339. Low-power timer block diagram /37,0 $3%B,7) .HUQHO 8SGRZQ (QFRGHU XSWRH[W WULJJHU *OLWFK ILOWHU VZ WULJJHU 5&& *OLWFK ILOWHU ,QSXW *OLWFK ILOWHU ,QSXW ELW$55 0X[WULJJHU $3%FORFN /6( /6, +6, µ &/.08; &2817 02'( 3UHVFDOHU ELWFRXQWHU 2XW ELWFRPSDUH 069 30.4.2 LPTIM reset and clocks The LPTIM can be clocked using several clock sources. It can be clocked using an internal clock signal which can be chosen among APB, LSI, LSE or HSI16 sources through the Clock Tree controller (RCC). Also, the LPTIM can be clocked using an external clock signal injected on its external Input1. When clocked with an external clock source, the LPTIM may run in one of these two possible configurations: • The first configuration is when the LPTIM is clocked by an external signal but in the same time an internal clock signal is provided to the LPTIM either from APB or any other embedded oscillator including LSE, LSI and HSI16. • The second configuration is when the LPTIM is solely clocked by an external clock source through its external Input1. This configuration is the one used to realize Timeout function or Pulse counter function when all the embedded oscillators are turned off after entering a low-power mode. DocID024597 Rev 1 1017/1680 1036 Low-power timer (LPTIM) RM0351 Programming the CKSEL and COUNTMODE bits allows controlling whether the LPTIM will use an external clock source or an internal one. When configured to use an external clock source, the CKPOL bits are used to select the external clock signal active edge. If both edges are configured to be active ones, an internal clock signal should also be provided (first configuration). In this case, the internal clock signal frequency should be at least four time higher than the external clock signal frequency. 30.4.3 Glitch filter The LPTIM inputs, either external or internal, are protected with digital filters that prevent any glitches and noise perturbations to propagate inside the LPTIM. This is in order to prevent spurious counts or triggers. Before activating the digital filters, an internal clock source should first be provided to the LPTIM. This is necessary to guarantee the proper operation of the filters. The digital filters are divided into two groups: Note: • The first group of digital filters protects the LPTIM external inputs. The digital filters sensitivity is controlled by the CKFLT bits • The second group of digital filters protects the LPTIM internal trigger inputs. The digital filters sensitivity is controlled by the TRGFLT bits. The digital filters sensitivity is controlled by groups. It is not possible to configure each digital filter sensitivity separately inside the same group. The filter sensitivity acts on the number of consecutive equal samples that should be detected on one of the LPTIM inputs to consider a signal level change as a valid transition. Figure 340 shows an example of glitch filter behavior in case of a 2 consecutive samples programmed. Figure 340. Glitch filter timing diagram &/.08; ,QSXW )LOWHURXW FRQVHFXWLYHVDPSOHV FRQVHFXWLYHVDPSOHV )LOWHUHG 069 Note: 1018/1680 In case no internal clock signal is provided, the digital filter must be deactivated by setting the CKFLT and TRGFLT bits to ‘0’. In that case, an external analog filter may be used to protect the LPTIM external inputs against glitches. DocID024597 Rev 1 RM0351 30.4.4 Low-power timer (LPTIM) Prescaler The LPTIM 16-bit counter is preceded by a configurable power-of-2 prescaler. The prescaler division ratio is controlled by the PRESC[2:0] 3-bit field. The table below lists all the possible division ratios: Table 161. Prescaler division ratios 30.4.5 programming dividing factor 000 /1 001 /2 010 /4 011 /8 100 /16 101 /32 110 /64 111 /128 Trigger multiplexer The LPTIM counter may be started either by software or after the detection of an active edge on one of the 8 trigger inputs. TRIGEN[1:0] is used to determine the LPTIM trigger source: • When TRIGEN[1:0] equals ‘00’, The LPTIM counter is started as soon as one of the CNTSTRT or the SNGSTRT bits is set by software. • The three remaining possible values for the TRIGEN[1:0] are used to configure the active edge used by the trigger inputs. The LPTIM counter starts as soon as an active edge is detected. When TRIGEN[1:0] is different than ‘00’, TRIGSEL[2:0] is used to select which of the 8 trigger inputs is used to start the counter. The external triggers are considered asynchronous signals for the LPTIM. So after a trigger detection, a two-counter-clock period latency is needed before the timer starts running due to the synchronization. If a new trigger event occurs when the timer is already started it will be ignored (unless timeout function is enabled). Note: The timer must be enabled before setting the SNGSTRT/CNTSTRT bits. Any write on these bits when the timer is disabled will be discarded by hardware. DocID024597 Rev 1 1019/1680 1036 Low-power timer (LPTIM) 30.4.6 RM0351 Operating mode The LPTIM features two operating modes: • The Continuous mode: the timer is free running, the timer is started from a trigger event and never stops until the timer is disabled • One shot mode: the timer is started from a trigger event and stops when reaching the ARR value. A new trigger event will re-start the timer. Any trigger event occurring after the counter starts and before the counter reaches ARR will be discarded. To enable the one shot counting, the SNGSTRT bit must be set. In case an external trigger is selected, an external trigger event arriving after SNGSTRT is set will start the counter for one shot counting. In case of software start (TRIGEN[1:0] = ‘00’), the SNGSTRT setting will start the counter for one shot counting. To enable the continuous counting, the CNTSTRT bit must be set. In case an external trigger is selected, an external trigger event arriving after CNTSTRT is set will start the counter for continuous counting. In case of software start (TRIGEN[1:0] = ‘00’), setting CNTSTRT will start the counter for continuous counting. SNGSTRT and CNTSTRT bits can only be set when the timer is enabled (The ENABLE bit is set to ‘1’). It is possible to change “on the fly” from One Shot mode to Continuous mode. If the Continuous mode was previously selected, setting SNGSTRT will switch the LPTIM to the One Shot mode. The counter (if active) will stop as soon as it reaches ARR. If the One Shot mode was previously selected, setting CNTSTRT will switch the LPTIM to the Continuous mode. The counter (if active) will restart as soon as it reaches ARR. 30.4.7 Timeout function The detection of an active edge on one selected trigger input can be used to reset the LPTIM counter. This feature is controlled through the TIMOUT bit. The first trigger event will start the timer, any successive trigger event will reset the counter and the timer will restart. A low-power timeout function can be realized. The timeout value corresponds to the compare value; if no trigger occurs within the expected time frame, the MCU is waked-up by the compare match event. 1020/1680 DocID024597 Rev 1 RM0351 30.4.8 Low-power timer (LPTIM) Waveform generation Two 16-bit registers, the LPTIMx_ARR (autoreload register) and LPTIMx_CMP (Compare register), are used to generate several different waveforms on LPTIM output The timer can generate the following waveforms: • The PWM mode: the LPTIM output is set as soon as a match occurs between the LPTIMx_CMP and the LPTIMx_CNT registers. The LPTIM output is reset as soon as a match occurs between the LPTIMx_ARR and the LPTIMx_CNT registers • The One-pulse mode: the output waveform is similar to the one of the PWM mode for the first pulse, then the output is permanently reset • The Set Once mode: the output waveform is similar to the One-pulse mode except that the output is kept to the last signal level (depends on the output configured polarity). The above described modes require that the LPTIMx_ARR register value be strictly greater than the LPTIMx_CMP register value. The LPTIM output waveform can be configured through the WAVE bit as follow: • Resetting the WAVE bit to ‘0’ forces the LPTIM to generate either a PWM waveform or a One pulse waveform depending on which bit is set: CNTSTRT or SNGSTRT. • Setting the WAVE bit to ‘1’ forces the LPTIM to generate a Set Once waveform. The WAVPOL bit controls the LPTIM output polarity. The change takes effect immediately, so the output default value will change immediately after the polarity is re-configured, even before the timer is enabled. Signals with frequencies up to the LPTIM clock frequency divided by 2 can be generated. Figure 341 below shows the three possible waveforms that can be generated on the LPTIM output. Also, it shows the effect of the polarity change using the WAVPOL bit. DocID024597 Rev 1 1021/1680 1036 Low-power timer (LPTIM) RM0351 Figure 341. Waveform generation $55 &RPSDUH 3:0 2QHVKRW 3RO 6HWRQFH 3:0 3RO 2QHVKRW 6HWRQFH 069 30.4.9 Register update The LPTIMx_ARR register and LPTIMx_CMP register are updated immediately after the APB bus write operation, or at the end of the current period if the timer is already started. The PRELOAD bit controls how the LPTIMx_ARR and the LPTIMx_CMP registers are updated: • When the PRELOAD bit is reset to ‘0’, the LPTIMx_ARR and the LPTIMx_CMP registers are immediately updated after any write access. • When the PRELOAD bit is set to ‘1’, the LPTIMx_ARR and the LPTIMx_CMP registers are updated at the end of the current period, if the timer has been already started. The APB bus and the LPTIM use different clocks, so there is some latency between the APB write and the moment when these values are available to the counter comparator. Within this latency period, any additional write into these registers must be avoided. The ARROK flag and the CMPOK flag in the LPTIMx_ISR register indicate when the write operation is completed to respectively the LPTIMx_ARR register and the LPTIMx_CMP register. After a write to the LPTIMx_ARR register or the LPTIMx_CMP register, a new write operation to the same register can only be performed when the previous write operation is completed. Any successive write before respectively the ARROK flag or the CMPOK flag be set, will lead to unpredictable results. 1022/1680 DocID024597 Rev 1 RM0351 30.4.10 Low-power timer (LPTIM) Counter mode The LPTIM counter can be used to count external events on the LPTIM Input1 or it can be used to count internal clock cycles. The CKSEL and COUNTMODE bits control which source will be used for updating the counter. In case the LPTIM is configured to count external events on Input1, the counter can be updated following a rising edge, falling edge or both edges depending on the value written to the CKPOL[1:0] bits. The count modes below can be selected, depending on CKSEL and COUNTMODE values: • CKSEL = 0: the LPTIM is clocked by an internal clock source – COUNTMODE = 0 When the LPTIM is configured to be clocked by an internal clock source and the LPTIM counter is configured to be updated by active edges detected on the LPTIM external Input1, the internal clock provided to the LPTIM must be not be prescaled (PRESC[2:0] = ‘000’). – COUNTMODE = 1 The LPTIM external Input1 is sampled with the internal clock provided to the LPTIM. Consequently, in order not to miss any event, the frequency of the changes on the external Input1 signal should never exceed the frequency of the internal clock provided to the LPTIM. • CKSEL = 1: the LPTIM is clocked by an external clock source COUNTMODE value is don’t care. In this configuration, the LPTIM has no need for an internal clock source (except if the glitch filters are enabled). The signal injected on the LPTIM external Input1 is used as system clock for the LPTIM. This configuration is suitable for operation modes where no embedded oscillator is enabled. For this configuration, the LPTIM counter can be updated either on rising edges or falling edges of the input1 clock signal but not on both rising and falling edges. Since the signal injected on the LPTIM external Input1 is also used to clock the LPTIM, there is some initial latency (after the LPTIM is enabled) before the counter is incremented. More precisely, the first five active edges on the LPTIM external Input1 (after LPTIM is enable) are lost. 30.4.11 Timer enable The ENABLE bit located in the LPTIMx_CR register is used to enable/disable the LPTIM. After setting the ENABLE bit, a delay of two counter clock is needed before the LPTIM is actually enabled. The LPTIMx_CFGR and LPTIMx_IER registers must be modified only when the LPTIM is disabled. 30.4.12 Encoder mode This mode allows handling signals from quadrature encoders used to detect angular position of rotary elements. Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value programmed into the LPTIMx_ARR register (0 up to ARR or ARR down to 0 depending on the direction). Therefore you must configure LPTIMx_ARR before starting. DocID024597 Rev 1 1023/1680 1036 Low-power timer (LPTIM) RM0351 From the two external input signals, Input1 and Input2, a clock signal is generated to clock the LPTIM counter. The phase between those two signals determines the counting direction. The Encoder mode is only available when the LPTIM is clocked by an internal clock source. The signals frequency on both Input1 and Input2 inputs must not exceed the LPTIM internal clock frequency divided by 4. This is mandatory in order to guarantee a proper operation of the LPTIM. Direction change is signalized by the two Down and Up flags in the LPTIMx_ISR register. Also, an interrupt can be generated for both direction change events if enabled through the LPTIMx_IER register. To activate the Encoder mode the ENC bit has to be set to ‘1’. The LPTIM must first be configured in continuous mode. When Encoder mode is active, the LPTIM counter is modified automatically following the speed and the direction of the incremental encoder. Therefore, its content always represents the encoder’s position. The count direction, signaled by the Up and Down flags, correspond to the rotation direction of the connected sensor. According to the edge sensitivity configured using the CKPOL[1:0] bits, different counting scenarios are possible. The following table summarizes the possible combinations, assuming that Input1 and Input2 do not switch at the same time. Table 162. Encoder counting scenarios Active edge Rising Edge Falling Edge Both Edges Level on opposite signal (Input1 for Input2, Input2 for Input1) Input1 signal Input2 signal Rising Falling Rising Falling High Down No count Up No count Low Up No count Down No count High No count Up No count Down Low No count Down No count Up High Down Up Up Down Low Up Down Down Up The following figure shows a counting sequence for Encoder mode where both edges sensitivity is configured. Caution: 1024/1680 In this mode the LPTIM must be clocked by an internal clock source, so the CKSEL bit must be maintained to its reset value which is equal to ‘0’. Also, the prescaler division ratio must be equal to its reset value which is 1 (PRESC[2:0] bits must be ‘000’). DocID024597 Rev 1 RM0351 Low-power timer (LPTIM) Figure 342. Encoder mode counting sequence 7 7 &RXQWHU XS 30.5 GRZQ XS 069 LPTIM interrupts The following events generate an interrupt/wake-up event, if they are enabled through the LPTIMx_IER register: Note: • Compare match • Auto-reload match (whatever the direction if encoder mode) • External trigger event • Autoreload register write completed • Compare register write completed • Direction change (encoder mode), programmable (up / down / both). if any bit in the LPTIMx_IER register (Interrupt Enable Register) is set after that its corresponding flag in the LPTIMx_ISR register (Status Register) is set, the interrupt is not asserted DocID024597 Rev 1 1025/1680 1036 Low-power timer (LPTIM) RM0351 30.6 LPTIM registers 30.6.1 LPTIM Interrupt and Status Register (LPTIMx_ISR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWN UP ARROK CMPOK EXTTRIG r r r r r ARRM CMPM r r Bits 31:7 Reserved, must be kept at reset value. Bit 6 DOWN: Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. Bit 5 UP: Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. Bit 4 ARROK: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated. Bit 3 CMPOK: Compare register update OK CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated. Bit 2 EXTTRIG: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. Bit 1 ARRM: Autoreload match ARRM is set by hardware to inform application that LPTIMx_CNT register’s value reached the LPTIMx_ARR register’s value. Bit 0 CMPM: Compare match The CMPM bit is set by hardware to inform application that LPTIMx_CNT register value reached the LPTIMx_CMP register’s value. 1026/1680 DocID024597 Rev 1 RM0351 Low-power timer (LPTIM) 30.6.2 LPTIM Interrupt Clear Register (LPTIMx_ICR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWN CF UPCF ARRO KCF ARRM CF CMPM CF w w w w w CMPO EXTTR KCF IGCF w w Bits 31:7 Reserved, must be kept at reset value. Bit 6 DOWNCF: Direction change to down Clear Flag Writing 1 to this bit clear the DOWN flag in the LPT_ISR register Bit 5 UPCF: Direction change to UP Clear Flag Writing 1 to this bit clear the UP flag in the LPT_ISR register Bit 4 ARROKCF: Autoreload register update OK Clear Flag Writing 1 to this bit clears the ARROK flag in the LPT_ISR register Bit 3 CMPOKCF: Compare register update OK Clear Flag Writing 1 to this bit clears the CMPOK flag in the LPT_ISR register Bit 2 EXTTRIGCF: External trigger valid edge Clear Flag Writing 1 to this bit clears the EXTTRIG flag in the LPT_ISR register Bit 1 ARRMCF: Autoreload match Clear Flag Writing 1 to this bit clears the ARRM flag in the LPT_ISR register Bit 0 CMPMCF: compare match Clear Flag Writing 1 to this bit clears the CMP flag in the LPT_ISR register DocID024597 Rev 1 1027/1680 1036 Low-power timer (LPTIM) 30.6.3 RM0351 LPTIM Interrupt Enable Register (LPTIMx_IER) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWNI E UPIE ARRO KIE rw rw rw CMPO EXTTR ARRMI CMPMI KIE IGIE E E rw rw rw rw Bits 31:7 Reserved, must be kept at reset value. Bit 6 DOWNIE: Direction change to down Interrupt Enable 0: DOWN interrupt disabled 1: DOWN interrupt enabled Bit 5 UPIE: Direction change to UP Interrupt Enable 0: UP interrupt disabled 1: UP interrupt enabled Bit 4 ARROKIE: Autoreload register update OK Interrupt Enable 0: ARROK interrupt disabled 1: ARROK interrupt enabled Bit 3 CMPOKIE: Compare register update OK Interrupt Enable 0: CMPOK interrupt disabled 1: CMPOK interrupt enabled Bit 2 EXTTRIGIE: External trigger valid edge Interrupt Enable 0: EXTTRIG interrupt disabled 1: EXTTRIG interrupt enabled Bit 1 ARRMIE: Autoreload match Interrupt Enable 0: ARRM interrupt disabled 1: ARRM interrupt enabled Bit 0 CMPMIE: Compare match Interrupt Enable 0: CMPM interrupt disabled 1: CMPM interrupt enabled Caution: The LPTIMx_IER register must only be modified when the LPTIM is disabled (ENABLE bit is reset to ‘0’) 1028/1680 DocID024597 Rev 1 RM0351 30.6.4 Low-power timer (LPTIM) LPTIM Configuration Register (LPTIMx_CFGR) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 Res. TRIGSEL rw rw rw PRESC rw rw 24 ENC 23 22 21 COUNT PRELOAD WAVPOL MODE 20 19 WAVE TIMOUT 18 17 TRIGEN Res. rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 rw rw Res. rw TRGFLT rw Res. rw CKFLT rw 16 CKPOL 0 CKSEL rw rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 ENC: Encoder mode enable The ENC bit controls the Encoder mode 0: Encoder mode disabled 1: Encoder mode enabled Bit 23 COUNTMODE: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter: 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid clock pulse on the LPTIM external Input1 Bit 22 PRELOAD: Registers update mode The PRELOAD bit controls the LPTIMx_ARR and the LPTIMx_CMP registers update modality 0: Registers are updated after each APB bus write access 1: Registers are updated at the end of the current LPTIM period Bit 21 WAVPOL: Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers. 1: The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers Bit 20 WAVE: Waveform shape The WAVE bit controls the output shape 0: PWM / One Pulse waveform (depending on OPMODE bit) 1: Set Once waveform Bit 19 TIMOUT: Timeout enable The TIMOUT bit controls the Timeout feature 0: a trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the counter Bits18:17 TRIGEN: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: sw trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges Bit 16 Reserved, must be kept at reset value. DocID024597 Rev 1 1029/1680 1036 Low-power timer (LPTIM) RM0351 Bits 15:13 TRIGSEL: Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: ext_trig0 001: ext_trig1 010: ext_trig2 011: ext_trig3 100: ext_trig4 101: ext_trig5 110: ext_trig6 111: ext_trig7 Bit 12 Reserved, must be kept at reset value. Bits 11:9 PRESC: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128 Bit 8 Reserved, must be kept at reset value. Bits 7:6 TRGFLT: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. Bit 5 Reserved, must be kept at reset value. 1030/1680 DocID024597 Rev 1 RM0351 Low-power timer (LPTIM) Bits 4:3 CKFLT: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. Bits 2:1 CKPOL: Clock Polarity If LPTIM is clocked by an external clock source: When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal’s edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed If the LPTIM is configured in Encoder mode (ENC bit is set): 00: the encoder sub-mode 1 is active 01: the encoder sub-mode 2 is active 10: the encoder sub-mode 3 is active Refer to Section 30.4.12: Encoder mode for more details about Encoder mode sub-modes. Bit 0 CKSEL: Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) 1: LPTIM is clocked by an external clock source through the LPTIM external Input1 Caution: The LPTIMx_CFGR register must only be modified when the LPTIM is disabled (ENABLE bit is reset to ‘0’). Table 163. LPTIM external trigger connection TRIGSEL External trigger ext_trig0 GPIO ext_trig1 RTC alarm A ext_trig2 RTC alarm B ext_trig3 RTC_TAMP1 input detection ext_trig4 RTC_TAMP2 input detection ext_trig5 RTC_TAMP3 input detection ext_trig6 COMP1_OUT ext_trig7 COMP2_OUT DocID024597 Rev 1 1031/1680 1036 Low-power timer (LPTIM) 30.6.5 RM0351 LPTIM Control Register (LPTIMx_CR) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNTST SNGST ENABL RT RT E rw rw rw Bits 31:3 Reserved, must be kept at reset value. Bit 2 CNTSTRT: Timer start in continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIMx_ARR and LPTIMx_CNT registers and the LPTIM counter keeps counting in continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware. Bit 1 SNGSTRT: LPTIM start in single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIMx_ARR and LPTIMx_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware. Bit 0 ENABLE: LPTIM Enable The ENABLE bit is set and cleared by software. 0: LPTIM is disabled 1: LPTIM is enabled 1032/1680 DocID024597 Rev 1 RM0351 Low-power timer (LPTIM) 30.6.6 LPTIM Compare Register (LPTIMx_CMP) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMP[15:0] rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CMP: Compare value. CMP is the compare value used by the LPTIM. The LPTIMx_CMP register’s content must only be modified when the LPTIM is enabled (ENABLE bit is set to ‘1’). 30.6.7 LPTIM Autoreload Register (LPTIMx_ARR) Address offset: 0x18 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARR[15:0] rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 ARR: Auto reload value. ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP[15:0] value. The LPTIMx_ARR register’s content must only be modified when the LPTIM is enabled (ENABLE bit is set to ‘1’). DocID024597 Rev 1 1033/1680 1036 Low-power timer (LPTIM) 30.6.8 RM0351 LPTIM Counter Register (LPTIMx_CNT) Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT[15:0] r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CNT: Counter value. When the LPTIM is running with an asynchronous clock, reading the LPTIMx_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. 30.6.9 LPTIM1 Option Register (LPTIM1_OR) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OR_1 OR_0 rw rw Bits 31:2 Reserved, must be kept at reset value. Bit 1 OR_1: Option register bit 1. 0: LPTIM1 input 2 is connected to I/O 1: LPTIM1 input 2 is connected to COMP2_OUT Bit 0 OR_0: Option register bit 0. 0: LPTIM1 input 1 is connected to I/O 1: LPTIM1 input 1 is connected to COMP1_OUT 30.6.10 LPTIM2 Option Register (LPTIM2_OR) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OR_1 OR_0 rw rw 1034/1680 DocID024597 Rev 1 RM0351 Low-power timer (LPTIM) Bits 31:2 Reserved, must be kept at reset value. Bit 1 OR_1: Option register bit 1. 0: LPTIM2 input 1 is connected to I/O 1: LPTIM2 input 1 is connected to COMP2_OUT Bit 0 OR_0: Option register bit 0. 0: LPTIM2 input 1 is connected to I/O 1: LPTIM2 input 1 is connected to COMP1_OUT Note: When both OR_1 and OR_0 are set, LPTIM2 input 1 is connected to (COMP1_OUT OR COMP2_OUT). DocID024597 Rev 1 1035/1680 1036 0x14 0x18 LPTIMx_CFGR 0x10 LPTIMx_CMP Reset value LPTIMx_ARR Reset value 0x1C 0x20 1036/1680 LPTIMx_CNT Reset value LPTIMx_OR Reset Value Refer to Section 2.2.2 on page 68 for the register boundary addresses. DocID024597 Rev 1 OR_1 OR_0 0x0C CKSEL CKPOL CKFLT Res. TRGFLT Res. PRESC Res. TRIGSEL Res. TRIGEN Res. Res. Res. Res. Res. Res. Res. ENC COUNTMODE PRELOAD WAVPOL WAVE TIMOUT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LPTIMx_ISR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWN UP ARROK CMPOK EXTTRIG ARRM CMPM Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPTIMx_ICR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWNCF UPCF ARROKCF CMPOKCF EXTTRIGCF ARRMCF CMPMCF Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPTIMx_IER Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWNIE UPIE ARROKIE CMPOKIE EXTTRIGIE ARRMIE CMPMIE 0x08 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPTIMx_CR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNTSTRT SNGSTRT ENABLE 0x04 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x00 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Offset Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30.6.11 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Low-power timer (LPTIM) RM0351 LPTIM register map The following table summarizes the LPTIM registers. Table 164. LPTIM register map and reset values Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 CNT[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0351 31 Infrared interface (IRTIM) Infrared interface (IRTIM) An infrared interface (IRTIM) for remote control is available on the device. It can be used with an infrared LED to perform remote control functions. It uses internal connections with TIM16 and TIM17 as shown in Figure 343. To generate the infrared remote control signals, the IR interface must be enabled and TIM16 channel 1 (TIM16_OC1) and TIM17 channel 1 (TIM17_OC1) must be properly configured to generate correct waveforms. The infrared receiver can be implemented easily through a basic input capture mode. Figure 343. IR internal hardware connections with TIM16 and TIM17 7,0B&+ ,57,0 ,5B287 7,0B&+ 069 All standard IR pulse modulation modes can be obtained by programming the two timer output compare channels. TIM17 is used to generate the high frequency carrier signal, while TIM16 generates the modulation envelope. The infrared function is output on the IR_OUT pin. The activation of this function is done through the GPIOx_AFRx register by enabling the related alternate function bit. The high sink LED driver capability (only available on the PB9 pin) can be activated through the I2C_PB9_FMP bit in the SYSCFG_CFGR1 register and used to sink the high current needed to directly control an infrared LED. DocID024597 Rev 1 1037/1680 1037 Independent watchdog (IWDG) RM0351 32 Independent watchdog (IWDG) 32.1 Introduction The devices feature an embedded watchdog peripheral which offers a combination of high safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral serves to detect and resolve malfunctions due to software failure, and to trigger system reset when the counter reaches a given timeout value. The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI) and thus stays active even if the main clock fails. The IWDG is best suited to applications which require the watchdog to run as a totally independent process outside the main application, but have lower timing accuracy constraints. For further information on the window watchdog, refer to Section 33 on page 1046. 32.2 IWDG main features • Free-running downcounter • Clocked from an independent RC oscillator (can operate in Standby and Stop modes) • Conditional Reset – Reset (if watchdog activated) when the downcounter value becomes less than 0x000 – Reset (if watchdog activated) if the downcounter is reloaded outside the window 32.3 IWDG functional description 32.3.1 IWDG block diagram Figure 344 shows the functional blocks of the independent watchdog module. Figure 344. Independent watchdog block diagram 9&25( 3UHVFDOHUUHJLVWHU ,:'*B35 6WDWXVUHJLVWHU ,:'*B65 5HORDGUHJLVWHU ,:'*B5/5 .H\UHJLVWHU ,:'*B.5 ELWUHORDGYDOXH /6, ELW N+] SUHVFDOHU ELWGRZQFRXQWHU ,:'*UHVHW 9''YROWDJHGRPDLQ 069 Note: 1038/10 The watchdog function is implemented in the VCORE voltage domain that is still functional in Stop and Standby modes. DocID024597 Rev 1 RM0351 Independent watchdog (IWDG) When the independent watchdog is started by writing the value 0x0000 CCCC in the Key register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, the IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented. 32.3.2 Window option The IWDG can also work as a window watchdog by setting the appropriate window in the IWDG_WINR register. If the reload operation is performed while the counter is greater than the value stored in the window register (IWDG_WINR), then a reset is provided. The default value of the IWDG_WINR is 0x0000 0FFF, so if it is not updated, the window option is disabled. As soon as the window value is changed, a reload operation is performed in order to reset the downcounter to the IWDG_RLR value and ease the cycle number calculation to generate the next reload. Configuring the IWDG when the window option is enabled Note: 1. Enable the IWDG by writing 0x0000 CCCC in the IWDG_KR register. 2. Enable register access by writing 0x0000 5555 in the IWDG_KR register. 3. Write the IWDG prescaler by programming IWDG_PR from 0 to 7. 4. Write the reload register (IWDG_RLR). 5. Wait for the registers to be updated (IWDG_SR = 0x0000 0000). 6. Write to the window register IWDG_WINR. This automatically refreshes the counter value IWDG_RLR. Writing the window value allows to refresh the Counter value by the RLR when IWDG_SR is set to 0x0000 0000. Configuring the IWDG when the window option is disabled When the window option it is not used, the IWDG can be configured as follows: 32.3.3 1. Enable the IWDG by writing 0x0000 CCCC in the IWDG_KR register. 2. Enable register access by writing 0x0000 5555 in the IWDG_KR register. 3. Write the IWDG prescaler by programming IWDG_PR from 0 to 7. 4. Write the reload register (IWDG_RLR). 5. Wait for the registers to be updated (IWDG_SR = 0x0000 0000). 6. Refresh the counter value with IWDG_RLR (IWDG_KR = 0x0000 AAAA) Hardware watchdog If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the Key register is written by the software before the counter reaches end of count or if the downcounter is reloaded inside the window. DocID024597 Rev 1 1039/10 1045 Independent watchdog (IWDG) 32.3.4 RM0351 Low-power freeze Depending on the IWDG_STOP and IWDG_STBY options configuration, the IWDG can continue counting or not during the Stop mode and the Standby mode respectively. If the IWDG is kept running during Stop or Standby modes, it can wake up the device from this mode. Refer to Section : User and read protection option bytes for more details. 32.3.5 Register access protection Write access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers is protected. To modify them, you must first write the code 0x0000 5555 in the IWDG_KR register. A write access to this register with a different value will break the sequence and register access will be protected again. This implies that it is the case of the reload operation (writing 0x0000 AAAA). A status register is available to indicate that an update of the prescaler or the down-counter reload value or the window value is on going. 32.3.6 Debug mode When the microcontroller enters debug mode (core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module. 32.4 IWDG registers Refer to Section 1.1 on page 61 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 32.4.1 Key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w w w w w w w w w KEY[15:0] w Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 KEY[15:0]: Key value (write only, read 0x0000) These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see Section 32.3.5: Register access protection) Writing the key value CCCCh starts the watchdog (except if the hardware watchdog option is selected) 1040/10 DocID024597 Rev 1 RM0351 Independent watchdog (IWDG) 32.4.2 Prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PR[2:0] rw rw rw Bits 31:3 Reserved, must be kept at reset value. Bits 2:0 PR[2:0]: Prescaler divider These bits are write access protected see Section 32.3.5: Register access protection. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. 000: divider /4 001: divider /8 010: divider /16 011: divider /32 100: divider /64 101: divider /128 110: divider /256 111: divider /256 Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG_SR register is reset. DocID024597 Rev 1 1041/10 1045 Independent watchdog (IWDG) 32.4.3 RM0351 Reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw 15 14 13 12 Res. Res. Res. Res. RL[11:0] rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits11:0 RL[11:0]: Watchdog counter reload value These bits are write access protected see Section 32.3.5. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. Refer to the datasheet for the timeout information. The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on this register. For this reason the value read from this register is valid only when the RVU bit in the IWDG_SR register is reset. 1042/10 DocID024597 Rev 1 RM0351 Independent watchdog (IWDG) 32.4.4 Status register (IWDG_SR) Address offset: 0x0C Reset value: 0x0000 0000 (not reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WVU RVU PVU r r r Bits 31:3 Reserved, must be kept at reset value. Bit 2 WVU: Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Window value can be updated only when WVU bit is reset. This bit is generated only if generic “window” = 1 Bit 1 RVU: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Reload value can be updated only when RVU bit is reset. Bit 0 PVU: Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Prescaler value can be updated only when PVU bit is reset. Note: If several reload, prescaler, or window values are used by the application, it is mandatory to wait until RVU bit is reset before changing the reload value, to wait until PVU bit is reset before changing the prescaler value, and to wait until WVU bit is reset before changing the window value. However, after updating the prescaler and/or the reload/window value it is not necessary to wait until RVU or PVU or WVU is reset before continuing code execution except in case of low-power mode entry. DocID024597 Rev 1 1043/10 1045 Independent watchdog (IWDG) 32.4.5 RM0351 Window register (IWDG_WINR) Address offset: 0x10 Reset value: 0x0000 0FFF (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw 15 14 13 12 Res. Res. Res. Res. WIN[11:0] rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits11:0 WIN[11:0]: Watchdog counter window value These bits are write access protected see Section 32.3.5. These bits contain the high limit of the window value to be compared to the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the IWDG_SR register is reset. 1044/10 DocID024597 Rev 1 0x0C 0x10 Reset value DocID024597 Rev 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Reset value 1 1 1 1 1 WIN[11:0] 1 1 1 1 PVU 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 RVU 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 WVU 1 Res. 1 Res. 1 Res. 1 Res. Res. Res. 1 Res. Res. Res. 1 Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Reset value Res. IWDG_WINR Res. IWDG_SR Res. IWDG_RLR Res. 0x08 Res. 0x04 IWDG_PR Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IWDG_KR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Register Res. 0x00 Res. Offset Res. 32.4.6 Res. RM0351 Independent watchdog (IWDG) IWDG register map The following table gives the IWDG register map and reset values. Table 165. IWDG register map and reset values KEY[15:0] 0 PR[2:0] 0 0 0 0 0 RL[11:0] 0 0 0 1 1 1 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. 1045/10 1045 System window watchdog (WWDG) RM0351 33 System window watchdog (WWDG) 33.1 Introduction The system window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared. An MCU reset is also generated if the 7-bit downcounter value (in the control register) is refreshed before the downcounter has reached the window register value. This implies that the counter must be refreshed in a limited window. The WWDG clock is prescaled from the APB clock and has a configurable time-window that can be programmed to detect abnormally late or early application behavior. The WWDG is best suited for applications which require the watchdog to react within an accurate timing window. 33.2 WWDG main features • Programmable free-running downcounter • Conditional reset • 33.3 – Reset (if watchdog activated) when the downcounter value becomes less than 0x40 – Reset (if watchdog activated) if the downcounter is reloaded outside the window (see Figure 346) Early wakeup interrupt (EWI): triggered (if enabled and the watchdog activated) when the downcounter is equal to 0x40. WWDG functional description If the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the 7-bit downcounter (T[6:0] bits) rolls over from 0x40 to 0x3F (T6 becomes cleared), it initiates a reset. If the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated. 1046/10 DocID024597 Rev 1 RM0351 System window watchdog (WWDG) Figure 345. Watchdog block diagram 5(6(7 :DWFKGRJFRQILJXUDWLRQUHJLVWHU ::'*B&)5 FRPSDUDWRU ZKHQ 7!: : : : : : : : :ULWH::'*B&5 :DWFKGRJFRQWUROUHJLVWHU ::'*B&5 :'*$ 3&/. IURP5&&FORFNFRQWUROOHU 7 7 7 7 7 7 7 ELWGRZQFRXQWHU &17 :'*SUHVFDOHU :'*7% 06Y9 The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. The value to be stored in the WWDG_CR register must be between 0xFF and 0xC0. 33.3.1 Enabling the watchdog The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot be disabled again except by a reset. 33.3.2 Controlling the downcounter This downcounter is free-running, counting down even if the watchdog is disabled. When the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset. The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. The timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WWDG_CR register (see Figure 346). The Configuration register (WWDG_CFR) contains the high limit of the window: To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x3F. Figure 346 describes the window watchdog process. Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 33.3.3 Advanced watchdog interrupt feature The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. The EWI interrupt is enabled by setting the EWI bit in the WWDG_CFR register. When the downcounter reaches the value 0x40, an EWI interrupt is generated and the corresponding interrupt service routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device. DocID024597 Rev 1 1047/10 1051 System window watchdog (WWDG) RM0351 In some applications, the EWI interrupt can be used to manage a software system check and/or system recovery/graceful degradation, without generating a WWDG reset. In this case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required actions. The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register. Note: When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task, the WWDG reset will eventually be generated. 33.3.4 How to program the watchdog timeout You can use the formula in Figure 346 to calculate the WWDG timeout. Warning: When writing to the WWDG_CR register, always write 1 in the T6 bit to avoid generating an immediate reset. Figure 346. Window watchdog timing diagram 4;= #.4 DOWNCOUNTER 7;= X& 2EFRESH NOT ALLOWED 2EFRESH ALLOWED 4IME 4 BIT 2%3%4 AIC The formula to calculate the timeout value is given by: WDGTB[1:0] × ( T [ 5:0 ] + 1 ) t WWDG = t PCLK × 4096 × 2 ( ms ) where: tWWDG: WWDG timeout tPCLK: APB clock period measured in ms 4096: value corresponding to internal divider As an example, lets assume APB frequency is equal to 48 MHz, WDGTB[1:0] is set to 3 and T[5:0] is set to 63: 1048/10 DocID024597 Rev 1 RM0351 System window watchdog (WWDG) t WWDG 3 = 1 ⁄ 48000 × 4096 × 2 × ( 63 + 1 ) = 43.69 ms Refer to the datasheet for the minimum and maximum values of the tWWDG. 33.3.5 Debug mode When the microcontroller enters debug mode (Cortex®-M4 core halted), the WWDG counter either continues to work normally or stops, depending on DBG_WWDG_STOP configuration bit in DBG module. For more details, refer to Section 44.16.2: Debug support for timers, RTC, watchdog, bxCAN and I2C. 33.4 WWDG registers Refer to Section 1.1 on page 61 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 33.4.1 Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x0000 007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. WDGA T[6:0] rs rw Bits 31:8 Reserved, must be kept at reset value. Bit 7 WDGA: Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter. It is decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it rolls over from 0x40 to 0x3F (T6 becomes cleared). DocID024597 Rev 1 1049/10 1051 System window watchdog (WWDG) 33.4.2 RM0351 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x0000 007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8 7 6 5 4 3 2 1 0 rw rw rw 15 14 13 12 11 10 9 Res. Res. Res. Res. Res. Res. EWI rs WDGTB[1:0] rw rw W[6:0] rw rw rw rw Bits 31:10 Reserved, must be kept at reset value. Bit 9 EWI: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset. Bits 8:7 WDGTB[1:0]: Timer base The time base of the prescaler can be modified as follows: 00: CK Counter Clock (PCLK div 4096) div 1 01: CK Counter Clock (PCLK div 4096) div 2 10: CK Counter Clock (PCLK div 4096) div 4 11: CK Counter Clock (PCLK div 4096) div 8 Bits 6:0 W[6:0]: 7-bit window value These bits contain the window value to be compared to the downcounter. 33.4.3 Status register (WWDG_SR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EWIF rc_w0 Bits 31:1 Reserved, must be kept at reset value. Bit 0 EWIF: Early wakeup interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing ‘0’. A write of ‘1’ has no effect. This bit is also set if the interrupt is not enabled. 1050/10 DocID024597 Rev 1 RM0351 33.4.4 System window watchdog (WWDG) WWDG register map The following table gives the WWDG register map and reset values. 0 1 1 1 1 1 Res. Res. Res. Res. 1 1 1 Res. 0 1 EWIF Res. 0 Res. 1 WDGTB0 1 Res. 1 WDGTB1 1 Res. 1 EWI Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WWDG_SR Res. 0x08 Res. Reset value T[6:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WWDG_CFR Res. 0x04 0 Res. Reset value WDGA Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WWDG_CR Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 Register Res. Offset Res. Table 166. WWDG register map and reset values W[6:0] Reset value 0 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. DocID024597 Rev 1 1051/10 1051 Real-time clock (RTC) RM0351 34 Real-time clock (RTC) 34.1 Introduction The RTC provides an automatic wakeup to manage all low-power modes. The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a timeof-day clock/calendar with programmable alarm interrupts. The RTC includes also a periodic programmable wakeup flag with interrupt capability. Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of month), month, and year, expressed in binary coded decimal format (BCD). The sub-seconds value is also available in binary format. Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed automatically. Daylight saving time compensation can also be performed. Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. A digital calibration feature is available to compensate for any deviation in crystal oscillator accuracy. After Backup domain reset, all RTC registers are protected against possible parasitic write accesses. As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, low-power mode or under reset). 1052/1680 DocID024597 Rev 1 RM0351 34.2 Real-time clock (RTC) RTC main features The RTC unit main features are the following (see Figure 347: RTC block diagram): • Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year. • Daylight saving compensation programmable by software. • Programmable alarm with interrupt function. The alarm can be triggered by any combination of the calendar fields. • Automatic wakeup unit generating a periodic flag that triggers an automatic wakeup interrupt. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. • Accurate synchronization with an external clock using the subsecond shift feature. • Digital calibration circuit (periodic counter correction): 0.95 ppm accuracy, obtained in a calibration window of several seconds • Time-stamp function for event saving • Tamper detection event with configurable filter and internal pull-up • Maskable interrupts/events: • – Alarm A – Alarm B – Wakeup interrupt – Time-stamp – Tamper detection Backup registers. DocID024597 Rev 1 1053/1680 1097 Real-time clock (RTC) RM0351 34.3 RTC functional description 34.3.1 RTC block diagram Figure 347. RTC block diagram Z dͺ dDWϯ Ă ĐŬƵƉƌĞŐŝƐƚĞƌƐ ĂŶĚZ dƚĂŵƉĞƌ ĐŽŶƚƌŽůƌĞŐŝƐƚĞƌƐ Z dͺ dDWϮ Z dͺ dDWϭ dDWdž& Z dͺd^ dŝŵĞƐƚĂŵƉ ƌĞŐŝƐƚĞƌƐ Z dͺZ&/E d^& >^;ϯϮ͘ϳϲϴ,njͿ ,^ͬϯϮ Z d>< >^/ Z dͺ>Z ^ŵŽŽƚŚ ĐĂůŝď ƌĂƚŝŽŶ Z dͺWZZ ƐLJŶĐŚƌŽŶŽƵƐ ϳͲďŝƚƉƌĞƐĐĂůĞƌ ;ĚĞ ĨĂƵůƚсϭϮϴͿ ĐŬͺĂƉƌĞ ;ĚĞ ĨĂƵůƚϮϱϲ,njͿ Z dͺWZZ ^LJŶĐŚƌŽŶŽƵƐ ϭϱͲďŝƚƉƌĞƐĐĂůĞƌ ;ĚĞ ĨĂƵůƚсϮϱϲͿ ĐŬͺƐƉƌĞ ;ĚĞ ĨĂƵůƚϭ,njͿ ĂůĞŶĚĂƌ ^ŚĂĚŽǁƌĞŐŝƐƚĞƌƐ ZdͺdZ͕ ZdͺZ ^ŚĂĚŽǁƌĞŐŝƐƚĞƌ Zdͺ^^Z th<^>ϭ͗Ϭ WƌĞƐĐĂůĞƌ Ϯ͕ϰ͕ϴ͕ϭϲ ϭ,nj ϱϭϮ,nj Z dͺ>/ Z dͺ>ZD KƵƚƉƵƚ ĐŽŶƚƌŽů Z dͺKhd ZdͺthdZ thd& ϭϲͲďŝƚǁĂŬĞƵƉ ĂƵƚŽƌĞůŽĂĚƚŝŵĞƌ K^>ϭ͗Ϭ ůĂ ƌŵ Z dͺ>ZDZ Z dͺ>ZD^^Z >Z& с ůĂ ƌŵ Z dͺ>ZDZ Z dͺ>ZD^^Z с >Z& D^ϯϬϮϭϲsϯ 1054/1680 DocID024597 Rev 1 RM0351 Real-time clock (RTC) The RTC includes: • Two alarms • Three tamper events • 32 x 32-bit backup registers – • • 34.3.2 The backup registers (RTC_BKPxR) are implemented in the RTC domain that remains powered-on by VBAT when the VDD power is switched off. Alternate function outputs: RTC_OUT which selects one of the following two outputs: – RTC_CALI\\Rsd028.rou.st.com\corpcom\Banque 512 Hz or 1Hz clock output (with an LSE frequency of 32.768 kHz). This output is enabled by setting the COE bit in the RTC_CR register. – RTC_ALARM: This output is enabled by configuring the OSEL[1:0] bits in the RTC_CR register which select the Alarm A, Alarm B or Wakeup outputs. Alternate function inputs: – RTC_TS: timestamp event – RTC_TAMP1: tamper1 event detection – RTC_TAMP2: tamper2 event detection – RTC_TAMP3: tamper3 event detection – RTC_REFIN: 50 or 60 Hz reference clock input GPIOs controlled by the RTC RTC_OUT, RTC_TS and RTC_TAMP1 are mapped on the same pin (PC13). PC13 pin configuration is controlled by the RTC, whatever the PC13 GPIO configuration. The RTC functions mapped on PC13 are available in all low-power modes and in VBAT mode. The output mechanism follows the priority order shown in Table 167. Table 167. RTC pin PC13 configuration(1) OSEL[1:0] bits PC13 Pin configuration (RTC_ALARM and function output enable) COE bit (RTC_CALIB output enable) RTC_OUT _RMP bit 01 or 10 or 11 Don’t care RTC_ALARM output PP 01 or 10 or 11 Don’t care RTC_CALIB output PP 00 1 0 00 0 Don’t care 00 1 01 or 10 or 11 0 RTC_TAMP1 input floating TAMP1E bit (RTC_TAMP1 input enable) (RTC_TS input enable) 0 Don’t care Don’t care 1 Don’t care Don’t care Don’t care Don’t care Don’t care Don’t care 1 0 0 RTC_ALARM output OD TSE bit RTC_ALARM _TYPE bit 1 0 1 1 DocID024597 Rev 1 1055/1680 1097 Real-time clock (RTC) RM0351 Table 167. RTC pin PC13 configuration(1) (continued) OSEL[1:0] bits PC13 Pin configuration (RTC_ALARM and function output enable) RTC_TS and RTC_TAMP1 input floating RTC_TS input floating Wakeup pin or Standard GPIO COE bit (RTC_CALIB output enable) RTC_OUT 00 0 Don’t care 00 1 01 or 10 or 11 0 00 0 00 1 01 or 10 or 11 0 00 0 00 1 01 or 10 or 11 0 _RMP bit TSE bit RTC_ALARM _TYPE bit TAMP1E bit (RTC_TAMP1 input enable) (RTC_TS input enable) Don’t care 1 1 Don’t care 0 1 Don’t care 0 0 1 Don’t care 1 Don’t care 1 1. OD: open drain; PP: push-pull. In addition, it is possible to remap RTC_OUT on PB2 pin thanks to RTC_OUT_RMP bit. In this case it is mandatory to configure PB2 GPIO registers as alternate function with the correct type. The remap functions are shown in Table 168. Table 168. RTC_OUT mapping OSEL[1:0] bits 34.3.3 (RTC_ALARM output enable) COE bit (RTC_CALIB output enable) 00 0 00 1 01 or 10 or 11 RTC_OUT_RMP bit RTC_OUT on PC13 RTC_OUT on PB2 - - RTC_CALIB - Don’t care RTC_ALARM - 00 0 - - 00 1 - RTC_CALIB 01 or 10 or 11 0 - RTC_ALARM 01 or 10 or 11 1 RTC_ALARM RTC_CALIB 0 1 Clock and prescalers The RTC clock source (RTCCLK) is selected through the clock controller among the LSE clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock source configuration, refer to Section 8: Reset and clock control (RCC). 1056/1680 DocID024597 Rev 1 RM0351 Real-time clock (RTC) A programmable prescaler stage generates a 1 Hz clock which is used to update the calendar. To minimize power consumption, the prescaler is split into 2 programmable prescalers (see Figure 347: RTC block diagram): Note: • A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the RTC_PRER register. • A 15-bit synchronous prescaler configured through the PREDIV_S bits of the RTC_PRER register. When both prescalers are used, it is recommended to configure the asynchronous prescaler to a high value to minimize consumption. The asynchronous prescaler division factor is set to 128, and the synchronous division factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency of 32.768 kHz. The minimum division factor is 1 and the maximum division factor is 222. This corresponds to a maximum input frequency of around 4 MHz. fck_apre is given by the following formula: f RTCCLK f CK_APRE = --------------------------------------PREDIV_A + 1 The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it reaches 0, RTC_SSR is reloaded with the content of PREDIV_S. fck_spre is given by the following formula: f RTCCLK f CK_SPRE = ----------------------------------------------------------------------------------------------( PREDIV_S + 1 ) × ( PREDIV_A + 1 ) The ck_spre clock can be used either to update the calendar or as timebase for the 16-bit wakeup auto-reload timer. To obtain short timeout periods, the 16-bit wakeup auto-reload timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous prescaler (see Section 34.3.6: Periodic auto-wakeup for details). 34.3.4 Real-time clock and calendar The RTC calendar time and date registers are accessed through shadow registers which are synchronized with PCLK (APB clock). They can also be accessed directly in order to avoid waiting for the synchronization duration. • RTC_SSR for the subseconds • RTC_TR for the time • RTC_DR for the date Every two RTCCLK periods, the current calendar value is copied into the shadow registers, and the RSF bit of RTC_ISR register is set (see Section 34.6.4: RTC initialization and status register (RTC_ISR)). The copy is not performed in Stop and Standby mode. When exiting these modes, the shadow registers are updated after up to 2 RTCCLK periods. When the application reads the calendar registers, it accesses the content of the shadow registers. It is possible to make a direct access to the calendar registers by setting the DocID024597 Rev 1 1057/1680 1097 Real-time clock (RTC) RM0351 BYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user accesses the shadow registers. When reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD=0 mode, the frequency of the APB clock (fAPB) must be at least 7 times the frequency of the RTC clock (fRTCCLK). The shadow registers are reset by system reset. 34.3.5 Programmable alarms The RTC unit provides programmable alarm: Alarm A and Alarm B. The description below is given for Alarm A, but can be translated in the same way for Alarm B. The programmable alarm function is enabled through the ALRAE bit in the RTC_CR register. The ALRAF is set to 1 if the calendar subseconds, seconds, minutes, hours, date or day match the values programmed in the alarm registers RTC_ALRMASSR and RTC_ALRMAR. Each calendar field can be independently selected through the MSKx bits of the RTC_ALRMAR register, and through the MASKSSx bits of the RTC_ALRMASSR register. The alarm interrupt is enabled through the ALRAIE bit in the RTC_CR register. Caution: If the seconds field is selected (MSK1 bit reset in RTC_ALRMAR), the synchronous prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct behavior. Alarm A and Alarm B (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the RTC_ALARM output. RTC_ALARM output polarity can be configured through bit POL the RTC_CR register. 34.3.6 Periodic auto-wakeup The periodic wakeup flag is generated by a 16-bit programmable auto-reload down-counter. The wakeup timer range can be extended to 17 bits. The wakeup function is enabled through the WUTE bit in the RTC_CR register. The wakeup timer clock input can be: • RTC clock (RTCCLK) divided by 2, 4, 8, or 16. When RTCCLK is LSE(32.768kHz), this allows to configure the wakeup interrupt period from 122 µs to 32 s, with a resolution down to 61 µs. • ck_spre (usually 1 Hz internal clock) When ck_spre frequency is 1Hz, this allows to achieve a wakeup time from 1 s to around 36 hours with one-second resolution. This large programmable time range is divided in 2 parts: – from 1s to 18 hours when WUCKSEL [2:1] = 10 – and from around 18h to 36h when WUCKSEL[2:1] = 11. In this last case 216 is added to the 16-bit counter current value.When the initialization sequence is complete (see Programming the wakeup timer on page 1060), the timer starts counting down.When the wakeup function is enabled, the down-counting remains active in low-power modes. In addition, when it reaches 0, the WUTF flag is set in the RTC_ISR register, and the wakeup counter is automatically reloaded with its reload value (RTC_WUTR register value). The WUTF flag must then be cleared by software. 1058/1680 DocID024597 Rev 1 RM0351 Real-time clock (RTC) When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR2 register, it can exit the device from low-power modes. The periodic wakeup flag can be routed to the RTC_ALARM output provided it has been enabled through bits OSEL[1:0] of RTC_CR register. RTC_ALARM output polarity can be configured through the POL bit in the RTC_CR register. System reset, as well as low-power modes (Sleep, Stop and Standby) have no influence on the wakeup timer. 34.3.7 RTC initialization and configuration RTC register access The RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC register accesses except on read accesses to calendar shadow registers when BYPSHAD=0. RTC register write protection After system reset, the RTC registers are protected against parasitic write access by clearing the DBP bit in the PWR_CR1 register (refer to the power control section). DBP bit must be set in order to enable RTC registers write access. After Backup domain reset, all the RTC registers are write-protected. Writing to the RTC registers is enabled by writing a key into the Write Protection register, RTC_WPR. The following steps are required to unlock the write protection on all the RTC registers except for RTC_TAMPCR, RTC_BKPxR, RTC_OR and RTC_ISR[13:8]. 1. Write ‘0xCA’ into the RTC_WPR register. 2. Write ‘0x53’ into the RTC_WPR register. Writing a wrong key reactivates the write protection. The protection mechanism is not affected by system reset. Calendar initialization and configuration To program the initial time and date calendar values, including the time format and the prescaler configuration, the following sequence is required: 1. Set INIT bit to 1 in the RTC_ISR register to enter initialization mode. In this mode, the calendar counter is stopped and its value can be updated. 2. Poll INITF bit of in the RTC_ISR register. The initialization phase mode is entered when INITF is set to 1. It takes around 2 RTCCLK clock cycles (due to clock synchronization). 3. To generate a 1 Hz clock for the calendar counter, program both the prescaler factors in RTC_PRER register. 4. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR), and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR register. 5. Exit the initialization mode by clearing the INIT bit. The actual calendar counter value is then automatically loaded and the counting restarts after 4 RTCCLK clock cycles. When the initialization sequence is complete, the calendar starts counting. DocID024597 Rev 1 1059/1680 1097 Real-time clock (RTC) Note: RM0351 After a system reset, the application can read the INITS flag in the RTC_ISR register to check if the calendar has been initialized or not. If this flag equals 0, the calendar has not been initialized since the year field is set at its Backup domain reset default value (0x00). To read the calendar after initialization, the software must first check that the RSF flag is set in the RTC_ISR register. Daylight saving time The daylight saving time management is performed through bits SUB1H, ADD1H, and BKP of the RTC_CR register. Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one single operation without going through the initialization procedure. In addition, the software can use the BKP bit to memorize this operation. Programming the alarm A similar procedure must be followed to program or update the programmable alarms. The procedure below is given for Alarm A but can be translated in the same way for Alarm B. Note: 1. Clear ALRAE in RTC_CR to disable Alarm A. 2. Program the Alarm A registers (RTC_ALRMASSR/RTC_ALRMAR). 3. Set ALRAE in the RTC_CR register to enable Alarm A again. Each change of the RTC_CR register is taken into account after around 2 RTCCLK clock cycles due to clock synchronization. Programming the wakeup timer The following sequence is required to configure or change the wakeup timer auto-reload value (WUT[15:0] in RTC_WUTR): 34.3.8 1. Clear WUTE in RTC_CR to disable the wakeup timer. 2. Poll WUTWF until it is set in RTC_ISR to make sure the access to wakeup auto-reload counter and to WUCKSEL[2:0] bits is allowed. It takes around 2 RTCCLK clock cycles (due to clock synchronization). 3. Program the wakeup auto-reload value WUT[15:0], and the wakeup clock selection (WUCKSEL[2:0] bits in RTC_CR). Set WUTE in RTC_CR to enable the timer again. The wakeup timer restarts down-counting. Reading the calendar When BYPSHAD control bit is cleared in the RTC_CR register To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB clock frequency (fPCLK) must be equal to or greater than seven times the RTC clock frequency (fRTCCLK). This ensures a secure behavior of the synchronization mechanism. If the APB clock frequency is less than seven times the RTC clock frequency, the software must read the calendar time and date registers twice. If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done. In any case the APB clock frequency must never be lower than the RTC clock frequency. 1060/1680 DocID024597 Rev 1 RM0351 Real-time clock (RTC) The RSF bit is set in RTC_ISR register each time the calendar registers are copied into the RTC_SSR, RTC_TR and RTC_DR shadow registers. The copy is performed every two RTCCLK cycles. To ensure consistency between the 3 values, reading either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read. In case the software makes read accesses to the calendar in a time interval smaller than 2 RTCCLK periods: RSF must be cleared by software after the first calendar read, and then the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR and RTC_DR registers. After waking up from low-power mode (Stop or Standby), RSF must be cleared by software. The software must then wait until it is set again before reading the RTC_SSR, RTC_TR and RTC_DR registers. The RSF bit must be cleared after wakeup and not before entering low-power mode. After a system reset, the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. Indeed, a system reset resets the shadow registers to their default values. After an initialization (refer to Calendar initialization and configuration on page 1059): the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. After synchronization (refer to Section 34.3.10: RTC synchronization): the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow registers) Reading the calendar registers gives the values from the calendar counters directly, thus eliminating the need to wait for the RSF bit to be set. This is especially useful after exiting from low-power modes (STOP or Standby), since the shadow registers are not updated during these modes. When the BYPSHAD bit is set to 1, the results of the different registers might not be coherent with each other if an RTCCLK edge occurs between two read accesses to the registers. Additionally, the value of one of the registers may be incorrect if an RTCCLK edge occurs during the read operation. The software must read all the registers twice, and then compare the results to confirm that the data is coherent and correct. Alternatively, the software can just compare the two results of the least-significant calendar register. Note: While BYPSHAD=1, instructions which read the calendar registers require one extra APB cycle to complete. 34.3.9 Resetting the RTC The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the RTC status register (RTC_ISR) are reset to their default values by all available system reset sources. On the contrary, the following registers are reset to their default values by a Backup domain reset and are not affected by a system reset: the RTC current calendar registers, the RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration register (RTC_CALR), the RTC shift register (RTC_SHIFTR), the RTC timestamp registers (RTC_TSSSR, RTC_TSTR and RTC_TSDR), the RTC tamper and alternate function DocID024597 Rev 1 1061/1680 1097 Real-time clock (RTC) RM0351 configuration register (RTC_TAMPCR), the RTC backup registers (RTC_BKPxR), the wakeup timer register (RTC_WUTR), the Alarm A and Alarm B registers (RTC_ALRMASSR/RTC_ALRMAR and RTC_ALRMBSSR/RTC_ALRMBR), and the Option register (RTC_OR). In addition, the RTC keeps on running under system reset if the reset source is different from the Backup domain reset one. When a Backup domain reset occurs, the RTC is stopped and all the RTC registers are set to their reset values. 34.3.10 RTC synchronization The RTC can be synchronized to a remote clock with a high degree of precision. After reading the sub-second field (RTC_SSR or RTC_TSSSR), a calculation can be made of the precise offset between the times being maintained by the remote clock and the RTC. The RTC can then be adjusted to eliminate this offset by “shifting” its clock by a fraction of a second using RTC_SHIFTR. RTC_SSR contains the value of the synchronous prescaler counter. This allows one to calculate the exact time being maintained by the RTC down to a resolution of 1 / (PREDIV_S + 1) seconds. As a consequence, the resolution can be improved by increasing the synchronous prescaler value (PREDIV_S[14:0]. The maximum resolution allowed (30.52 μs with a 32768 Hz clock) is obtained with PREDIV_S set to 0x7FFF. However, increasing PREDIV_S means that PREDIV_A must be decreased in order to maintain the synchronous prescaler output at 1 Hz. In this way, the frequency of the asynchronous prescaler output increases, which may increase the RTC dynamic consumption. The RTC can be finely adjusted using the RTC shift control register (RTC_SHIFTR). Writing to RTC_SHIFTR can shift (either delay or advance) the clock by up to a second with a resolution of 1 / (PREDIV_S + 1) seconds. The shift operation consists of adding the SUBFS[14:0] value to the synchronous prescaler counter SS[15:0]: this will delay the clock. If at the same time the ADD1S bit is set, this results in adding one second and at the same time subtracting a fraction of second, so this will advance the clock. Caution: Before initiating a shift operation, the user must check that SS[15] = 0 in order to ensure that no overflow will occur. As soon as a shift operation is initiated by a write to the RTC_SHIFTR register, the SHPF flag is set by hardware to indicate that a shift operation is pending. This bit is cleared by hardware as soon as the shift operation has completed. Caution: This synchronization feature is not compatible with the reference clock detection feature: firmware must not write to RTC_SHIFTR when REFCKON=1. 34.3.11 RTC reference clock detection The update of the RTC calendar can be synchronized to a reference clock, RTC_REFIN, which is usually the mains frequency (50 or 60 Hz). The precision of the RTC_REFIN reference clock should be higher than the 32.768 kHz LSE clock. When the RTC_REFIN detection is enabled (REFCKON bit of RTC_CR set to 1), the calendar is still clocked by the LSE, and RTC_REFIN is used to compensate for the imprecision of the calendar update frequency (1 Hz). Each 1 Hz clock edge is compared to the nearest RTC_REFIN clock edge (if one is found within a given time window). In most cases, the two clock edges are properly aligned. When 1062/1680 DocID024597 Rev 1 RM0351 Real-time clock (RTC) the 1 Hz clock becomes misaligned due to the imprecision of the LSE clock, the RTC shifts the 1 Hz clock a bit so that future 1 Hz clock edges are aligned. Thanks to this mechanism, the calendar becomes as precise as the reference clock. The RTC detects if the reference clock source is present by using the 256 Hz clock (ck_apre) generated from the 32.768 kHz quartz. The detection is performed during a time window around each of the calendar updates (every 1 s). The window equals 7 ck_apre periods when detecting the first reference clock edge. A smaller window of 3 ck_apre periods is used for subsequent calendar updates. Each time the reference clock is detected in the window, the asynchronous prescaler which outputs the ck_apre clock is forced to reload. This has no effect when the reference clock and the 1 Hz clock are aligned because the prescaler is being reloaded at the same moment. When the clocks are not aligned, the reload shifts future 1 Hz clock edges a little for them to be aligned with the reference clock. If the reference clock halts (no reference clock edge occurred during the 3 ck_apre window), the calendar is updated continuously based solely on the LSE clock. The RTC then waits for the reference clock using a large 7 ck_apre period detection window centered on the ck_spre edge. When the RTC_REFIN detection is enabled, PREDIV_A and PREDIV_S must be set to their default values: • PREDIV_A = 0x007F • PREVID_S = 0x00FF Note: RTC_REFIN clock detection is not available in Standby mode. 34.3.12 RTC smooth digital calibration The RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a range from -487.1 ppm to +488.5 ppm. The correction of the frequency is performed using series of small adjustments (adding and/or subtracting individual RTCCLK pulses). These adjustments are fairly well distributed so that the RTC is well calibrated even when observed over short durations of time. The smooth digital calibration is performed during a cycle of about 220 RTCCLK pulses, or 32 seconds when the input frequency is 32768 Hz. This cycle is maintained by a 20-bit counter, cal_cnt[19:0], clocked by RTCCLK. The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles to be masked during the 32-second cycle: • Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32- second cycle. Note: • Setting CALM[1] to 1 causes two additional cycles to be masked • Setting CALM[2] to 1 causes four additional cycles to be masked • and so on up to CALM[8] set to 1 which causes 256 clocks to be masked. CALM[8:0] (RTC_CALR) specifies the number of RTCCLK pulses to be masked during the 32-second cycle. Setting the bit CALM[0] to ‘1’ causes exactly one pulse to be masked during the 32-second cycle at the moment when cal_cnt[19:0] is 0x80000; CALM[1]=1 causes two other cycles to be masked (when cal_cnt is 0x40000 and 0xC0000); CALM[2]=1 causes four other cycles to be masked (cal_cnt = 0x20000/0x60000/0xA0000/ 0xE0000); and so on up to CALM[8]=1 which causes 256 clocks to be masked (cal_cnt = 0xXX800). DocID024597 Rev 1 1063/1680 1097 Real-time clock (RTC) RM0351 While CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine resolution, the bit CALP can be used to increase the frequency by 488.5 ppm. Setting CALP to ‘1’ effectively inserts an extra RTCCLK pulse every 211 RTCCLK cycles, which means that 512 clocks are added during every 32-second cycle. Using CALM together with CALP, an offset ranging from -511 to +512 RTCCLK cycles can be added during the 32-second cycle, which translates to a calibration range of -487.1 ppm to +488.5 ppm with a resolution of about 0.954 ppm. The formula to calculate the effective calibrated frequency (FCAL) given the input frequency (FRTCCLK) is as follows: FCAL = FRTCCLK x [1 + (CALP x 512 - CALM) / (220 + CALM - CALP x 512)] Calibration when PREDIV_A<3 The CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in RTC_PRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are set to a value less than 3, CALP is ignored and the calibration operates as if CALP was equal to 0. To perform a calibration with PREDIV_A less than 3, the synchronous prescaler value (PREDIV_S) should be reduced so that each second is accelerated by 8 RTCCLK clock cycles, which is equivalent to adding 256 clock cycles every 32 seconds. As a result, between 255 and 256 clock pulses (corresponding to a calibration range from 243.3 to 244.1 ppm) can effectively be added during each 32-second cycle using only the CALM bits. With a nominal RTCCLK frequency of 32768 Hz, when PREDIV_A equals 1 (division factor of 2), PREDIV_S should be set to 16379 rather than 16383 (4 less). The only other interesting case is when PREDIV_A equals 0, PREDIV_S should be set to 32759 rather than 32767 (8 less). If PREDIV_S is reduced in this way, the formula given the effective frequency of the calibrated input clock is as follows: FCAL = FRTCCLK x [1 + (256 - CALM) / (220 + CALM - 256)] In this case, CALM[7:0] equals 0x100 (the midpoint of the CALM range) is the correct setting if RTCCLK is exactly 32768.00 Hz. Verifying the RTC calibration RTC precision is ensured by measuring the precise frequency of RTCCLK and calculating the correct CALM value and CALP values. An optional 1 Hz output is provided to allow applications to measure and verify the RTC precision. Measuring the precise frequency of the RTC over a limited interval can result in a measurement error of up to 2 RTCCLK clock cycles over the measurement period, depending on how the digital calibration cycle is aligned with the measurement period. However, this measurement error can be eliminated if the measurement period is the same length as the calibration cycle period. In this case, the only error observed is the error due to the resolution of the digital calibration. • 1064/1680 By default, the calibration cycle period is 32 seconds. DocID024597 Rev 1 RM0351 Real-time clock (RTC) Using this mode and measuring the accuracy of the 1 Hz output over exactly 32 seconds guarantees that the measure is within 0.477 ppm (0.5 RTCCLK cycles over 32 seconds, due to the limitation of the calibration resolution). • CALW16 bit of the RTC_CALR register can be set to 1 to force a 16- second calibration cycle period. In this case, the RTC precision can be measured during 16 seconds with a maximum error of 0.954 ppm (0.5 RTCCLK cycles over 16 seconds). However, since the calibration resolution is reduced, the long term RTC precision is also reduced to 0.954 ppm: CALM[0] bit is stuck at 0 when CALW16 is set to 1. • CALW8 bit of the RTC_CALR register can be set to 1 to force a 8- second calibration cycle period. In this case, the RTC precision can be measured during 8 seconds with a maximum error of 1.907 ppm (0.5 RTCCLK cycles over 8s). The long term RTC precision is also reduced to 1.907 ppm: CALM[1:0] bits are stuck at 00 when CALW8 is set to 1. Re-calibration on-the-fly The calibration register (RTC_CALR) can be updated on-the-fly while RTC_ISR/INITF=0, by using the follow process: 34.3.13 1. Poll the RTC_ISR/RECALPF (re-calibration pending flag). 2. If it is set to 0, write a new value to RTC_CALR, if necessary. RECALPF is then automatically set to 1 3. Within three ck_apre cycles after the write operation to RTC_CALR, the new calibration settings take effect. Time-stamp function Time-stamp is enabled by setting the TSE or ITSE bits of RTC_CR register to 1. When TSE is set: The calendar is saved in the time-stamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) when a time-stamp event is detected on the RTC_TS pin. When ITSE is set: The calendar is saved in the time-stamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) when an internal time-stamp event is detected. The internal timestamp event is generated by the switch to the VBAT supply. When a time-stamp event occurs, due to internal or external event, the time-stamp flag bit (TSF) in RTC_ISR register is set. In case the event is internal, the ITSF flag is also set in RTC_ISR register. By setting the TSIE bit in the RTC_CR register, an interrupt is generated when a time-stamp event occurs. If a new time-stamp event is detected while the time-stamp flag (TSF) is already set, the time-stamp overflow flag (TSOVF) flag is set and the time-stamp registers (RTC_TSTR and RTC_TSDR) maintain the results of the previous event. DocID024597 Rev 1 1065/1680 1097 Real-time clock (RTC) Note: RM0351 TSF is set 2 ck_apre cycles after the time-stamp event occurs due to synchronization process. There is no delay in the setting of TSOVF. This means that if two time-stamp events are close together, TSOVF can be seen as '1' while TSF is still '0'. As a consequence, it is recommended to poll TSOVF only after TSF has been set. Caution: If a time-stamp event occurs immediately after the TSF bit is supposed to be cleared, then both TSF and TSOVF bits are set.To avoid masking a time-stamp event occurring at the same moment, the application must not write ‘0’ into TSF bit unless it has already read it to ‘1’. Optionally, a tamper event can cause a time-stamp to be recorded. See the description of the TAMPTS control bit in Section 34.6.14: RTC time-stamp sub second register (RTC_TSSSR). 34.3.14 Tamper detection The RTC_TAMPx input events can be configured either for edge detection, or for level detection with filtering. The tamper detection can be configured for the following purposes: • erase the RTC backup registers (default configuration) • generate an interrupt, capable to wakeup from Stop and Standby modes • generate a hardware trigger for the low-power timers RTC backup registers The backup registers (RTC_BKPxR) are not reset by system reset or when the device wakes up from Standby mode. The backup registers are reset when a tamper detection event occurs (see Section 34.6.20: RTC backup registers (RTC_BKPxR) and Tamper detection initialization on page 1066, or when the readout protection of the flash is changed from level 1 to level 0) except if the TAMPxNOERASE bit is set, or if TAMPxMF is set in the RTC_TAMPCR register. Tamper detection initialization Each input can be enabled by setting the corresponding TAMPxE bits to 1 in the RTC_TAMPCR register. Each RTC_TAMPx tamper detection input is associated with a flag TAMPxF in the RTC_ISR register. When TAMPxMF is cleared: The TAMPxF flag is asserted after the tamper event on the pin, with the latency provided below: • 3 ck_apre cycles when TAMPFLT differs from 0x0 (Level detection with filtering) • 3 ck_apre cycles when TAMPTS=1 (Timestamp on tamper event) • No latency when TAMPFLT=0x0 (Edge detection) and TAMPTS=0 A new tamper occurring on the same pin during this period and as long as TAMPxF is set cannot be detected. When TAMPxMF is set: 1066/1680 DocID024597 Rev 1 RM0351 Real-time clock (RTC) A new tamper occurring on the same pin cannot be detected during the latency described above and 2.5 ck_rtc additional cycles. By setting the TAMPIE bit in the RTC_TAMPCR register, an interrupt is generated when a tamper detection event occurs (when TAMPxF is set). Setting TAMPIE is not allowed when one or more TAMPxMF is set. When TAMPIE is cleared, each tamper pin event interrupt can be individually enabled by setting the corresponding TAMPxIE bit in the RTC_TAMPCR register. Setting TAMPxIE is not allowed when the corresponding TAMPxMF is set. Trigger output generation on tamper event The tamper event detection can be used as trigger input by the low-power timers. When TAMPxMF bit in cleared in RTC_TAMPCR register, the TAMPxF flag must be cleared by software in order to allow a new tamper detection on the same pin. When TAMPxMF bit is set, the TAMPxF flag is masked, and kept cleared in RTC_ISR register. This configuration allows to trig automatically the low-power timers in Stop mode, without requiring the system wakeup to perform the TAMPxF clearing. In this case, the backup registers are not cleared. Timestamp on tamper event With TAMPTS set to ‘1’, any tamper event causes a timestamp to occur. In this case, either the TSF bit or the TSOVF bit are set in RTC_ISR, in the same manner as if a normal timestamp event occurs. The affected tamper flag register TAMPxF is set at the same time that TSF or TSOVF is set. Edge detection on tamper inputs If the TAMPFLT bits are “00”, the RTC_TAMPx pins generate tamper detection events when either a rising edge or a falling edge is observed depending on the corresponding TAMPxTRG bit. The internal pull-up resistors on the RTC_TAMPx inputs are deactivated when edge detection is selected. Caution: When using the edge detection, it is recommended to check by software the tamper pin level just after enabling the tamper detection (by reading the GPIO registers), and before writing sensitive values in the backup registers, to ensure that an active edge did not occur before enabling the tamper event detection. When TAMPFLT="00" and TAMPxTRG = 0 (rising edge detection), a tamper event may be detected by hardware if the tamper input is already at high level before enabling the tamper detection. After a tamper event has been detected and cleared, the RTC_TAMPx alternate function should be disabled and then re-enabled (TAMPxE set to 1) before re-programming the backup registers (RTC_BKPxR). This prevents the application from writing to the backup registers while the RTC_TAMPx input value still indicates a tamper detection. This is equivalent to a level detection on the RTC_TAMPx alternate function input. Note: Tamper detection is still active when VDD power is switched off. To avoid unwanted resetting of the backup registers, the pin to which the RTC_TAMPx alternate function is mapped should be externally tied to the correct level. DocID024597 Rev 1 1067/1680 1097 Real-time clock (RTC) RM0351 Level detection with filtering on RTC_TAMPx inputs Level detection with filtering is performed by setting TAMPFLT to a non-zero value. A tamper detection event is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive samples are observed at the level designated by the TAMPxTRG bits. The RTC_TAMPx inputs are precharged through the I/O internal pull-up resistance before its state is sampled, unless disabled by setting TAMPPUDIS to 1,The duration of the precharge is determined by the TAMPPRCH bits, allowing for larger capacitances on the RTC_TAMPx inputs. The trade-off between tamper detection latency and power consumption through the pull-up can be optimized by using TAMPFREQ to determine the frequency of the sampling for level detection. Note: Refer to the datasheets for the electrical characteristics of the pull-up resistors. 34.3.15 Calibration clock output When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the RTC_CALIB device output. If the COSEL bit in the RTC_CR register is reset and PREDIV_A = 0x7F, the RTC_CALIB frequency is fRTCCLK/64. This corresponds to a calibration output at 512 Hz for an RTCCLK frequency at 32.768 kHz. The RTC_CALIB duty cycle is irregular: there is a light jitter on falling edges. It is therefore recommended to use rising edges. When COSEL is set and “PREDIV_S+1” is a non-zero multiple of 256 (i.e: PREDIV_S[7:0] = 0xFF), the RTC_CALIB frequency is fRTCCLK/(256 * (PREDIV_A+1)). This corresponds to a calibration output at 1 Hz for prescaler default values (PREDIV_A = Ox7F, PREDIV_S = 0xFF), with an RTCCLK frequency at 32.768 kHz. Note: When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is automatically configured in output alternate function. 34.3.16 Alarm output The OSEL[1:0] control bits in the RTC_CR register are used to activate the alarm alternate function output RTC_ALARM, and to select the function which is output. These functions reflect the contents of the corresponding flags in the RTC_ISR register. The polarity of the output is determined by the POL control bit in RTC_CR so that the opposite of the selected flag bit is output when POL is set to 1. Alarm alternate function output The RTC_ALARM pin can be configured in output open drain or output push-pull using the control bit RTC_ALARM_TYPE in the RTC_OR register. Note: Once the RTC_ALARM output is enabled, it has priority over RTC_CALIB (COE bit is don't care and must be kept cleared). When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is automatically configured in output alternate function. 1068/1680 DocID024597 Rev 1 RM0351 34.4 Real-time clock (RTC) RTC low-power modes Table 169. Effect of low-power modes on RTC Mode Description Sleep No effect RTC interrupts cause the device to exit the Sleep mode. Stop The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC tamper event, RTC timestamp event, and RTC Wakeup cause the device to exit the Stop mode. The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC Standby tamper event, RTC timestamp event, and RTC Wakeup cause the device to exit the Standby mode. 34.5 RTC interrupts All RTC interrupts are connected to the EXTI controller. Refer to Section 13: Extended interrupts and events controller (EXTI). To enable the RTC Alarm interrupt, the following sequence is required: 1. Configure and enable the EXTI line corresponding to the RTC Alarm event in interrupt mode and select the rising edge sensitivity. 2. Configure and enable the RTC_ALARM IRQ channel in the NVIC. 3. Configure the RTC to generate RTC alarms. To enable the RTC Tamper interrupt, the following sequence is required: 1. Configure and enable the EXTI line corresponding to the RTC Tamper event in interrupt mode and select the rising edge sensitivity. 2. Configure and Enable the RTC_TAMP_STAMP IRQ channel in the NVIC. 3. Configure the RTC to detect the RTC tamper event. To enable the RTC TimeStamp interrupt, the following sequence is required: 1. Configure and enable the EXTI line corresponding to the RTC TimeStamp event in interrupt mode and select the rising edge sensitivity. 2. Configure and Enable the RTC_TAMP_STAMP IRQ channel in the NVIC. 3. Configure the RTC to detect the RTC time-stamp event. To enable the Wakeup timer interrupt, the following sequence is required: 1. Configure and enable the EXTI line corresponding to the Wakeup timer even in interrupt mode and select the rising edge sensitivity. 2. Configure and Enable the RTC_WKUP IRQ channel in the NVIC. 3. Configure the RTC to detect the RTC Wakeup timer event. DocID024597 Rev 1 1069/1680 1097 Real-time clock (RTC) RM0351 Table 170. Interrupt control bits Interrupt event Event flag Enable control bit Exit from Sleep mode Exit from Stop mode Exit from Standby mode Alarm A ALRAF ALRAIE yes yes(1) yes(1) Alarm B ALRBF ALRBIE yes yes(1) yes(1) RTC_TS input (timestamp) TSF TSIE yes yes(1) yes(1) RTC_TAMP1 input detection TAMP1F TAMPIE yes yes(1) yes(1) RTC_TAMP2 input detection TAMP2F TAMPIE yes yes(1) yes(1) RTC_TAMP3 input detection TAMP3F TAMPIE yes yes(1) yes(1) Wakeup timer interrupt WUTF WUTIE yes yes(1) yes(1) 1. Wakeup from STOP and Standby modes is possible only when the RTC clock source is LSE or LSI. 34.6 RTC registers Refer to Section 1.1 on page 61 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). 34.6.1 RTC time register (RTC_TR) The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page 1059 and Reading the calendar on page 1060. This register is write protected. The write access procedure is described in RTC register write protection on page 1059. Address offset: 0x00 Backup domain reset value: 0x0000 0000 System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1. 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. PM rw 15 14 Res. 13 12 11 MNT[2:0] rw rw 10 9 8 MNU[3:0] rw rw rw 7 6 Res. rw rw 20 19 18 HT[1:0] rw Bit 22 PM: AM/PM notation 0: AM or 24-hour format 1: PM Bits 21:20 HT[1:0]: Hour tens in BCD format DocID024597 Rev 1 17 16 HU[3:0] rw rw rw rw rw rw 5 4 3 2 1 0 rw rw ST[2:0] Bits 31-23 Reserved, must be kept at reset value 1070/1680 21 rw SU[3:0] rw rw rw RM0351 Real-time clock (RTC) Bits 19:16 HU[3:0]: Hour units in BCD format Bit 15 Reserved, must be kept at reset value. Bits 14:12 MNT[2:0]: Minute tens in BCD format Bits 11:8 MNU[3:0]: Minute units in BCD format Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format DocID024597 Rev 1 1071/1680 1097 Real-time clock (RTC) 34.6.2 RM0351 RTC date register (RTC_DR) The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page 1059 and Reading the calendar on page 1060. This register is write protected. The write access procedure is described in RTC register write protection on page 1059. Address offset: 0x04 Backup domain reset value: 0x0000 2101 System reset: 0x0000 2101 when BYPSHAD = 0. Not affected when BYPSHAD = 1. 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 rw rw rw rw WDU[2:0] rw rw MT rw rw MU[3:0] 23 22 20 19 18 17 16 YU[3:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 Res. Res. rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value Bits 23:20 YT[3:0]: Year tens in BCD format Bits 19:16 YU[3:0]: Year units in BCD format Bits 15:13 WDU[2:0]: Week day units 000: forbidden 001: Monday ... 111: Sunday Bit 12 MT: Month tens in BCD format Bits 11:8 MU: Month units in BCD format Bits 7:6 Reserved, must be kept at reset value. Bits 5:4 DT[1:0]: Date tens in BCD format Bits 3:0 DU[3:0]: Date units in BCD format 1072/1680 21 YT[3:0] DocID024597 Rev 1 DT[1:0] rw DU[3:0] RM0351 Real-time clock (RTC) 34.6.3 RTC control register (RTC_CR) Address offset: 0x08 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 Res. Res. Res. Res. Res. Res. Res. ITSE COE rw rw rw 15 14 13 12 11 10 9 8 7 6 TSIE rw WUTIE ALRBIE ALRAIE rw rw rw TSE WUTE rw rw ALRBE ALRAE rw Res. rw 22 21 20 19 18 POL COSEL BKP rw rw rw rw w w 5 4 3 2 1 0 OSEL[1:0] FMT rw BYPS REFCKON TSEDGE HAD rw rw rw 17 16 SUB1H ADD1H WUCKSEL[2:0] rw rw rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 ITSE: timestamp on internal event enable 0: internal event timestamp disabled 1: internal event timestamp enabled Bit 23 COE: Calibration output enable This bit enables the RTC_CALIB output 0: Calibration output disabled 1: Calibration output enabled Bits 22:21 OSEL[1:0]: Output selection These bits are used to select the flag to be routed to RTC_ALARM output 00: Output disabled 01: Alarm A output enabled 10: Alarm B output enabled 11: Wakeup output enabled Bit 20 POL: Output polarity This bit is used to configure the polarity of RTC_ALARM output 0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]). Bit 19 COSEL: Calibration output selection When COE=1, this bit selects which signal is output on RTC_CALIB. 0: Calibration output is 512 Hz 1: Calibration output is 1 Hz These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). Refer to Section 34.3.15: Calibration clock output Bit 18 BKP: Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. Bit 17 SUB1H: Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0. 0: No effect 1: Subtracts 1 hour to the current time. This can be used for winter time change. DocID024597 Rev 1 1073/1680 1097 Real-time clock (RTC) RM0351 Bit 16 ADD1H: Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change Bit 15 TSIE: Time-stamp interrupt enable 0: Time-stamp Interrupt disable 1: Time-stamp Interrupt enable Bit 14 WUTIE: Wakeup timer interrupt enable 0: Wakeup timer interrupt disabled 1: Wakeup timer interrupt enabled Bit 13 ALRBIE: Alarm B interrupt enable 0: Alarm B Interrupt disable 1: Alarm B Interrupt enable Bit 12 ALRAIE: Alarm A interrupt enable 0: Alarm A interrupt disabled 1: Alarm A interrupt enabled Bit 11 TSE: timestamp enable 0: timestamp disable 1: timestamp enable Bit 10 WUTE: Wakeup timer enable 0: Wakeup timer disabled 1: Wakeup timer enabled Bit 9 ALRBE: Alarm B enable 0: Alarm B disabled 1: Alarm B enabled Bit 8 ALRAE: Alarm A enable 0: Alarm A disabled 1: Alarm A enabled Bit 7 Reserved, must be kept at reset value. Bit 6 FMT: Hour format 0: 24 hour/day format 1: AM/PM hour format Bit 5 BYPSHAD: Bypass the shadow registers 0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. 1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to ‘1’. 1074/1680 DocID024597 Rev 1 RM0351 Real-time clock (RTC) Bit 4 REFCKON: RTC_REFIN reference clock detection enable (50 or 60 Hz) 0: RTC_REFIN detection disabled 1: RTC_REFIN detection enabled Note: PREDIV_S must be 0x00FF. Bit 3 TSEDGE: Time-stamp event active edge 0: RTC_TS input rising edge generates a time-stamp event 1: RTC_TS input falling edge generates a time-stamp event TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. Bits 2:0 WUCKSEL[2:0]: Wakeup clock selection 000: RTC/16 clock is selected 001: RTC/8 clock is selected 010: RTC/4 clock is selected 011: RTC/2 clock is selected 10x: ck_spre (usually 1 Hz) clock is selected 11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value (see note below) Note: Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1). WUT = Wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when WUCKSEL[2:1 = 11]. Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1. It is recommended not to change the hour during the calendar hour increment as it could mask the incrementation of the calendar hour. ADD1H and SUB1H changes are effective in the next second. This register is write protected. The write access procedure is described in RTC register write protection on page 1059. DocID024597 Rev 1 1075/1680 1097 Real-time clock (RTC) 34.6.4 RM0351 RTC initialization and status register (RTC_ISR) This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page 1059. Address offset: 0x0C Backup domain reset value: 0x0000 0007 System reset: not affected except INIT, INITF, and RSF bits which are cleared to ‘0’ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ITSF RECALPF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 INIT INITF RSF INITS rw r rc_w0 r TAMP3F TAMP2F TAMP1F TSOVF rc_w0 rc_w0 rc_w0 rc_w0 TSF rc_w0 WUTF ALRBF ALRAF rc_w0 rc_w0 rc_w0 SHPF WUTWF r r rc_w0 r 1 0 ALRB WF ALRAWF r r Bits 31:18 Reserved, must be kept at reset value Bit 17 ITSF: Internal tTime-stamp flag This flag is set by hardware when a time-stamp on the internal event occurs. This flag is cleared by software by writing 0, and must be cleared together with TSF bit by writing 0 in both bits. Bit 16 RECALPF: Recalibration pending Flag The RECALPF status flag is automatically set to ‘1’ when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to ‘0’. Refer to Re-calibration on-the-fly. Bit 15 TAMP3F: RTC_TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP3 input. It is cleared by software writing 0 Bit 14 TAMP2F: RTC_TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP2 input. It is cleared by software writing 0 Bit 13 TAMP1F: RTC_TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1 input. It is cleared by software writing 0 Bit 12 TSOVF: Time-stamp overflow flag This flag is set by hardware when a time-stamp event occurs while TSF is already set. This flag is cleared by software by writing 0. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. Bit 11 TSF: Time-stamp flag This flag is set by hardware when a time-stamp event occurs. This flag is cleared by software by writing 0. If ITSF flag is set, TSF must be cleared together with ITSF by writing 0 in both bits. 1076/1680 DocID024597 Rev 1 RM0351 Real-time clock (RTC) Bit 10 WUTF: Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag is cleared by software by writing 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. Bit 9 ALRBF: Alarm B flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR). This flag is cleared by software by writing 0. Bit 8 ALRAF: Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). This flag is cleared by software by writing 0. Bit 7 INIT: Initialization mode 0: Free running mode 1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. Bit 6 INITF: Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. 0: Calendar registers update is not allowed 1: Calendar registers update is allowed Bit 5 RSF: Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow register mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 0: Calendar shadow registers not yet synchronized 1: Calendar shadow registers synchronized Bit 4 INITS: Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state). 0: Calendar has not been initialized 1: Calendar has been initialized Bit 3 SHPF: Shift operation pending 0: No shift operation is pending 1: A shift operation is pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. DocID024597 Rev 1 1077/1680 1097 Real-time clock (RTC) RM0351 Bit 2 WUTWF: Wakeup timer write flag This bit is set by hardware when the wakeup timer values can be changed, after the WUTE bit has been set to 0 in RTC_CR. 0: Wakeup timer configuration update not allowed 1: Wakeup timer configuration update allowed Bit 1 ALRBWF: Alarm B write flag This bit is set by hardware when Alarm B values can be changed, after the ALRBE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0: Alarm B update not allowed 1: Alarm B update allowed Bit 0 ALRAWF: Alarm A write flag This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0: Alarm A update not allowed 1: Alarm A update allowed Note: 1078/1680 The bits ALRAF, ALRBF, WUTF and TSF are cleared 2 APB clock cycles after programming them to 0. DocID024597 Rev 1 RM0351 Real-time clock (RTC) 34.6.5 RTC prescaler register (RTC_PRER) This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page 1059. This register is write protected. The write access procedure is described in RTC register write protection on page 1059. Address offset: 0x10 Backup domain reset value: 0x007F 00FF System reset: not affected 31 30 29 28 27 26 25 24 23 Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 rw rw rw rw rw rw rw Res. 22 21 20 19 18 17 16 PREDIV_A[6:0] rw rw rw rw rw rw rw 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PREDIV_S[14:0] rw Bits 31:23 Reserved, must be kept at reset value Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) Bit 15 Reserved, must be kept at reset value. Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1) DocID024597 Rev 1 1079/1680 1097 Real-time clock (RTC) 34.6.6 RM0351 RTC wakeup timer register (RTC_WUTR) This register can be written only when WUTWF is set to 1 in RTC_ISR. This register is write protected. The write access procedure is described in RTC register write protection on page 1059. Address offset: 0x14 Backup domain reset value: 0x0000 FFFF System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw WUT[15:0] rw Bits 31:16 Reserved, must be kept at reset value Bits 15:0 WUT[15:0]: Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden. 1080/1680 DocID024597 Rev 1 RM0351 Real-time clock (RTC) 34.6.7 RTC alarm A register (RTC_ALRMAR) This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 1059. Address offset: 0x1C Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 MSK4 WDSEL 29 28 27 DT[1:0] 26 25 24 DU[3:0] 23 22 MSK3 PM 21 20 19 18 HT[1:0] 17 16 HU[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw MSK2 rw MNT[2:0] rw rw MNU[3:0] rw rw rw MSK1 rw rw rw ST[2:0] rw rw SU[3:0] rw rw rw Bit 31 MSK4: Alarm A date mask 0: Alarm A set if the date/day match 1: Date/day don’t care in Alarm A comparison Bit 30 WDSEL: Week day selection 0: DU[3:0] represents the date units 1: DU[3:0] represents the week day. DT[1:0] is don’t care. Bits 29:28 DT[1:0]: Date tens in BCD format. Bits 27:24 DU[3:0]: Date units or day in BCD format. Bit 23 MSK3: Alarm A hours mask 0: Alarm A set if the hours match 1: Hours don’t care in Alarm A comparison Bit 22 PM: AM/PM notation 0: AM or 24-hour format 1: PM Bits 21:20 HT[1:0]: Hour tens in BCD format. Bits 19:16 HU[3:0]: Hour units in BCD format. Bit 15 MSK2: Alarm A minutes mask 0: Alarm A set if the minutes match 1: Minutes don’t care in Alarm A comparison Bits 14:12 MNT[2:0]: Minute tens in BCD format. Bits 11:8 MNU[3:0]: Minute units in BCD format. Bit 7 MSK1: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds don’t care in Alarm A comparison Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. DocID024597 Rev 1 1081/1680 1097 Real-time clock (RTC) 34.6.8 RM0351 RTC alarm B register (RTC_ALRMBR) This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 1059. Address offset: 0x20 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 MSK4 WDSEL 29 28 27 DT[1:0] 26 25 24 DU[3:0] 23 22 MSK3 PM 21 20 19 18 HT[1:0] 17 16 HU[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw MSK2 rw MNT[2:0] rw rw MNU[3:0] rw rw rw rw MSK1 rw rw ST[2:0] rw rw Bit 31 MSK4: Alarm B date mask 0: Alarm B set if the date and day match 1: Date and day don’t care in Alarm B comparison Bit 30 WDSEL: Week day selection 0: DU[3:0] represents the date units 1: DU[3:0] represents the week day. DT[1:0] is don’t care. Bits 29:28 DT[1:0]: Date tens in BCD format Bits 27:24 DU[3:0]: Date units or day in BCD format Bit 23 MSK3: Alarm B hours mask 0: Alarm B set if the hours match 1: Hours don’t care in Alarm B comparison Bit 22 PM: AM/PM notation 0: AM or 24-hour format 1: PM Bits 21:20 HT[1:0]: Hour tens in BCD format Bits 19:16 HU[3:0]: Hour units in BCD format Bit 15 MSK2: Alarm B minutes mask 0: Alarm B set if the minutes match 1: Minutes don’t care in Alarm B comparison Bits 14:12 MNT[2:0]: Minute tens in BCD format Bits 11:8 MNU[3:0]: Minute units in BCD format Bit 7 MSK1: Alarm B seconds mask 0: Alarm B set if the seconds match 1: Seconds don’t care in Alarm B comparison Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format 1082/1680 DocID024597 Rev 1 SU[3:0] rw rw rw RM0351 Real-time clock (RTC) 34.6.9 RTC write protection register (RTC_WPR) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 w w w w 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. KEY w w w w Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 KEY: Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to RTC register write protection for a description of how to unlock RTC register write protection. 34.6.10 RTC sub second register (RTC_SSR) Address offset: 0x28 Backup domain reset value: 0x0000 0000 System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r SS[15:0] r r r r r r r r r Bits31:16 Reserved, must be kept at reset value Bits 15:0 SS: Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR. DocID024597 Rev 1 1083/1680 1097 Real-time clock (RTC) 34.6.11 RM0351 RTC shift control register (RTC_SHIFTR) This register is write protected. The write access procedure is described in RTC register write protection on page 1059. Address offset: 0x2C Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADD1S Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w w 15 Res. SUBFS[14:0] w w w w w w w w Bit 31 ADD1S: Add one second 0: No effect 1: Add one second to the clock/calendar This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. Bits 30:15 Reserved, must be kept at reset value Bits 14:0 SUBFS: Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be sure that the shadow registers have been updated with the shifted time. 1084/1680 DocID024597 Rev 1 RM0351 Real-time clock (RTC) 34.6.12 RTC timestamp time register (RTC_TSTR) The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset. Address offset: 0x30 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. PM r 15 14 Res. 13 12 11 MNT[2:0] r r 10 9 8 MNU[3:0] r r r r 7 6 Res. r 21 20 19 18 HT[1:0] r r r r 5 4 3 2 ST[2:0] r r 17 16 HU[3:0] r r 1 0 r r SU[3:0] r r r Bits 31:23 Reserved, must be kept at reset value Bit 22 PM: AM/PM notation 0: AM or 24-hour format 1: PM Bits 21:20 HT[1:0]: Hour tens in BCD format. Bits 19:16 HU[3:0]: Hour units in BCD format. Bit 15 Reserved, must be kept at reset value Bits 14:12 MNT[2:0]: Minute tens in BCD format. Bits 11:8 MNU[3:0]: Minute units in BCD format. Bit 7 Reserved, must be kept at reset value Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. DocID024597 Rev 1 1085/1680 1097 Real-time clock (RTC) 34.6.13 RM0351 RTC timestamp date register (RTC_TSDR) The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset. Address offset: 0x34 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. r r 15 WDU[1:0] r r MT r r MU[3:0] r r r r Bits 31:16 Reserved, must be kept at reset value Bits 15:13 WDU[1:0]: Week day units Bit 12 MT: Month tens in BCD format Bits 11:8 MU[3:0]: Month units in BCD format Bits 7:6 Reserved, must be kept at reset value Bits 5:4 DT[1:0]: Date tens in BCD format Bits 3:0 DU[3:0]: Date units in BCD format 1086/1680 DocID024597 Rev 1 DT[1:0] r DU[3:0] r r r RM0351 Real-time clock (RTC) 34.6.14 RTC time-stamp sub second register (RTC_TSSSR) The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset. Address offset: 0x38 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r SS[15:0] r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value Bits 15:0 SS: Sub second value SS[15:0] is the value of the synchronous prescaler counter when the timestamp event occurred. DocID024597 Rev 1 1087/1680 1097 Real-time clock (RTC) 34.6.15 RM0351 RTC calibration register (RTC_CALR) This register is write protected. The write access procedure is described in RTC register write protection on page 1059. Address offset: 0x3C Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CALP CALW8 CALW 16 Res. Res. Res. Res. rw rw rw rw rw rw rw CALM[8:0] rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value Bit 15 CALP: Increase frequency of RTC by 488.5 ppm 0: No RTCCLK pulses are added. 1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency increased by 488.5 ppm). This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM. Refer to Section 34.3.12: RTC smooth digital calibration. Bit 14 CALW8: Use an 8-second calibration cycle period When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at “00” when CALW8=’1’. Refer to Section 34.3.12: RTC smooth digital calibration. Bit 13 CALW16: Use a 16-second calibration cycle period When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1. Note: CALM[0] is stuck at ‘0’ when CALW16=’1’. Refer to Section 34.3.12: RTC smooth digital calibration. Bits 12:9 Reserved, must be kept at reset value Bits 8:0 CALM[8:0]: Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section 34.3.12: RTC smooth digital calibration on page 1063. 1088/1680 DocID024597 Rev 1 RM0351 Real-time clock (RTC) 34.6.16 RTC tamper configuration register (RTC_TAMPCR) Address offset: 0x40 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 TAMP PUDIS rw TAMPPRCH [1:0] rw rw TAMPFLT[1:0] rw rw 24 rw 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 TAMPFREQ[2:0] rw 23 TAMP3 TAMP2 TAMP1 TAMP3 TAMP3 TAMP2 TAMP2 TAMP1 TAMP1 NO NO NO MF IE MF IE MF IE ERASE ERASE ERASE TAMP TS rw rw TAMP3 TAMP3 TAMP2 TAMP2 TRG E TRG E rw rw rw rw TAMPI E rw TAMP1 TAMP1 TRG E rw rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 TAMP3MF: Tamper 3 mask flag 0: Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to allow next tamper event detection. 1: Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased. Note: The Tamper 3 interrupt must not be enabled when TAMP3MF is set. Bit 23 TAMP3NOERASE: Tamper 3 no erase 0: Tamper 3 event erases the backup registers. 1: Tamper 3 event does not erase the backup registers. Bit 22 TAMP3IE: Tamper 3 interrupt enable 0: Tamper 3 interrupt is disabled if TAMPIE = 0. 1: Tamper 3 interrupt enabled. Bit 21 TAMP2MF: Tamper 2 mask flag 0: Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to allow next tamper event detection. 1: Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. Note: The Tamper 2 interrupt must not be enabled when TAMP2MF is set. Bit 20 TAMP2NOERASE: Tamper 2 no erase 0: Tamper 2 event erases the backup registers. 1: Tamper 2 event does not erase the backup registers. Bit 19 TAMP2IE: Tamper 2 interrupt enable 0: Tamper 2 interrupt is disabled if TAMPIE = 0. 1: Tamper 2 interrupt enabled. Bit 18 TAMP1MF: Tamper 1 mask flag 0: Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection. 1: Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased. Note: The Tamper 1 interrupt must not be enabled when TAMP1MF is set. DocID024597 Rev 1 1089/1680 1097 Real-time clock (RTC) RM0351 Bit 17 TAMP1NOERASE: Tamper 1 no erase 0: Tamper 1 event erases the backup registers. 1: Tamper 1 event does not erase the backup registers. Bit 16 TAMP1IE: Tamper 1 interrupt enable 0: Tamper 1 interrupt is disabled if TAMPIE = 0. 1: Tamper 1 interrupt enabled. Bit 15 TAMPPUDIS: RTC_TAMPx pull-up disable This bit determines if each of the RTC_TAMPx pins are precharged before each sample. 0: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) 1: Disable precharge of RTC_TAMPx pins. Bits 14:13 TAMPPRCH[1:0]: RTC_TAMPx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs. 0x0: 1 RTCCLK cycle 0x1: 2 RTCCLK cycles 0x2: 4 RTCCLK cycles 0x3: 8 RTCCLK cycles Bits 12:11 TAMPFLT[1:0]: RTC_TAMPx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a Tamper event. TAMPFLT is valid for each of the RTC_TAMPx inputs. 0x0: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input). 0x1: Tamper event is activated after 2 consecutive samples at the active level. 0x2: Tamper event is activated after 4 consecutive samples at the active level. 0x3: Tamper event is activated after 8 consecutive samples at the active level. Bits 10:8 TAMPFREQ[2:0]: Tamper sampling frequency Determines the frequency at which each of the RTC_TAMPx inputs are sampled. 0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) 0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) 0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) 0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) 0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) 0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) 0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) 0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) Bit 7 TAMPTS: Activate timestamp on tamper detection event 0: Tamper detection event does not cause a timestamp to be saved 1: Save timestamp on tamper detection event TAMPTS is valid even if TSE=0 in the RTC_CR register. Bit 6 TAMP3TRG: Active level for RTC_TAMP3 input if TAMPFLT ≠ 00: 0: RTC_TAMP3 input staying low triggers a tamper detection event. 1: RTC_TAMP3 input staying high triggers a tamper detection event. if TAMPFLT = 00: 0: RTC_TAMP3 input rising edge triggers a tamper detection event. 1: RTC_TAMP3 input falling edge triggers a tamper detection event. 1090/1680 DocID024597 Rev 1 RM0351 Real-time clock (RTC) Bit 5 TAMP3E: RTC_TAMP3 detection enable 0: RTC_TAMP3 input detection disabled 1: RTC_TAMP3 input detection enabled Bit 4 TAMP2TRG: Active level for RTC_TAMP2 input if TAMPFLT != 00: 0: RTC_TAMP2 input staying low triggers a tamper detection event. 1: RTC_TAMP2 input staying high triggers a tamper detection event. if TAMPFLT = 00: 0: RTC_TAMP2 input rising edge triggers a tamper detection event. 1: RTC_TAMP2 input falling edge triggers a tamper detection event. Bit 3 TAMP2E: RTC_TAMP2 input detection enable 0: RTC_TAMP2 detection disabled 1: RTC_TAMP2 detection enabled Bit 2 TAMPIE: Tamper interrupt enable 0: Tamper interrupt disabled 1: Tamper interrupt enabled. Note: This bit enables the interrupt for all tamper pins events, whatever TAMPxIE level. If this bit is cleared, each tamper event interrupt can be individually enabled by setting TAMPxIE. Bit 1 TAMP1TRG: Active level for RTC_TAMP1 input If TAMPFLT != 00 0: RTC_TAMP1 input staying low triggers a tamper detection event. 1: RTC_TAMP1 input staying high triggers a tamper detection event. if TAMPFLT = 00: 0: RTC_TAMP1 input rising edge triggers a tamper detection event. 1: RTC_TAMP1 input falling edge triggers a tamper detection event. Bit 0 TAMP1E: RTC_TAMP1 input detection enable 0: RTC_TAMP1 detection disabled 1: RTC_TAMP1 detection enabled Caution: When TAMPFLT = 0, TAMP1E must be reset when TAMP1TRG is changed to avoid spuriously setting TAMP1F. DocID024597 Rev 1 1091/1680 1097 Real-time clock (RTC) 34.6.17 RM0351 RTC alarm A sub second register (RTC_ALRMASSR) This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 1059 Address offset: 0x44 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 Res. Res. Res. Res. 27 26 25 24 rw rw rw rw 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw MASKSS[3:0] Res. 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 rw rw rw rw w rw rw SS[14:0] rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit 0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). 1: SS[14:1] are don’t care in Alarm A comparison. Only SS[0] is compared. 2: SS[14:2] are don’t care in Alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are don’t care in Alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are don’t care in Alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are don’t care in Alarm A comparison. SS[12:0] are compared. 14: SS[14] is don’t care in Alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Bits23:15 Reserved, must be kept at reset value. Bits 14:0 SS[14:0]: Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. 1092/1680 DocID024597 Rev 1 RM0351 Real-time clock (RTC) 34.6.18 RTC alarm B sub second register (RTC_ALRMBSSR) This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode. This register is write protected.The write access procedure is described in Section : RTC register write protection. Address offset: 0x48 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 Res. Res. Res. Res. 27 26 25 24 rw rw rw rw 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw MASKSS[3:0] Res. 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 rw rw rw rw w rw rw SS[14:0] rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit 0x0: No comparison on sub seconds for Alarm B. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). 0x1: SS[14:1] are don’t care in Alarm B comparison. Only SS[0] is compared. 0x2: SS[14:2] are don’t care in Alarm B comparison. Only SS[1:0] are compared. 0x3: SS[14:3] are don’t care in Alarm B comparison. Only SS[2:0] are compared. ... 0xC: SS[14:12] are don’t care in Alarm B comparison. SS[11:0] are compared. 0xD: SS[14:13] are don’t care in Alarm B comparison. SS[12:0] are compared. 0xE: SS[14] is don’t care in Alarm B comparison. SS[13:0] are compared. 0xF: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Bits 23:15 Reserved, must be kept at reset value. Bits 14:0 SS[14:0]: Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared. DocID024597 Rev 1 1093/1680 1097 Real-time clock (RTC) 34.6.19 RM0351 RTC option register (RTC_OR) Address offset: 0x4C Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. RTC_ OUT_ RMP RTC_ ALARM _TYPE rw rw Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:2 Reserved, must be kept at reset value. Bit 1 RTC_OUT_RMP: RTC_OUT remap Setting this bit allows to remap the RTC outputs on PB2 as follows: RTC_OUT_RMP = ‘0’: If OSEL/= “00” : RTC_ALARM is output on PC13 If OSEL= “00” and COE = ‘1’ : RTC_CALIB is output on PC13 RTC_OUT_RMP = ‘1’ : If OSEL /= “00” and COE = ‘0’ : RTC_ALARM is output on PB2 If OSEL = “00” and COE = ‘1’: RTC_CALIB is output on PB2 If OSEL /= “00” and COE = ‘1’: RTC_CALIB is output on PB2 and RTC_ALARM is output on PC13. Bit 0 RTC_ALARM_TYPE: RTC_ALARM on PC13 output type 0: RTC_ALARM, when mapped on PC13, is open-drain output 1: RTC_ALARM, when mapped on PC13, is push-pull output 1094/1680 DocID024597 Rev 1 RM0351 Real-time clock (RTC) 34.6.20 RTC backup registers (RTC_BKPxR) Address offset: 0x50 to 0xCC Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BKP[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw w rw rw BKP[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 BKP[31:0] The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled. DocID024597 Rev 1 1095/1680 1097 Real-time clock (RTC) 34.6.21 RM0351 RTC register map Res. 0 0 0 0 0 1 1 1 1 1 1 Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_WPR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DU[3:0] 0 0 0 0 0 HT [1:0] 0 0 0 0 HU[3:0] MNT[2:0] 0 0 0 MNU[3:0] 0 MNT[2:0] 0 0 0 MNU[3:0] Res. 0 0 0 0 Res. Res. Res. Res. WDU[1:0] 0 MT 0 0 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ST[2:0] 0 0 0 SU[3:0] 0 ST[2:0] 0 0 0 0 0 0 SU[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MU[3:0] 0 0 0 0 0 0 0 0 0 0 0 ST[2:0] 0 0 0 0 SU[3:0] 0 DT [1:0] 0 0 0 DU[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 SS[15:0] 0 DocID024597 Rev 1 1 KEY Res. 0 Res. Res. Res. Res. Res. 0 MNT[2:0] Res. HT[1:0] 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. PM 0 MNU[3:0] 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Reset value 1096/1680 0 0 0 Res. RTC_TSSSR 0 SUBFS[14:0] 0 Reset value 0x38 0 Res. Res. Res. Res. Res. HU[3:0] 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RTC_TSDR Res. Reset value 0x34 Res. Res. Res. Res. Res. Res. Res. Res. RTC_TSTR 0 0 Res. 0 Res. ADD1S Reset value Res. RTC_SHIFTR Res. 0x30 0 SS[15:0] 0 Res. Reset value 0x2C 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RTC_SSR 0 0 Res. Reset value 0x28 0 MSK2 0 HU[3:0] MSK2 0 0 MSK1 PM 0 DT [1:0] 0 MSK2 MSK3 Reset value 0 PM RTC_ALRMBR 0 MSK3 0 Res. 1 Res. 1 Res. 1 MSK4 1 WDSEL 1 MSK4 1 WDSEL 1 0 0 0 WUCKS EL[2:0] WUT[15:0] Reset value HT [1:0] 1 0 Res. 1 RTC_ALRMAR DU[3:0] 0 PREDIV_S[14:0] 1 DT [1:0] 0 ALRAWF 0 0 ALRBWF ALRAF 0 0 TSEDGE WUTF ALRBF 0 0 SHPF TSF 0 DU[3:0] WUT WF 0 0 BYPSHAD 0 0 REFCKON 0 0 RSF 0 0 INITS ALRAE 0 0 DT [1:0] Res. Res. WUTE ALRBE 0 0 FMT TSE 0 Res. ALRAIE 0 PREDIV_A[6:0] 0 SU[3:0] INITF ALRBIE 0 ST[2:0] INIT Res. 0 TSOVF 1 TAMP1F 0 TSIE 0 WUTIE 0 .TAMP2F Res. 0 MU[3:0] Res. 0x24 1 0 Res. 0x20 0 0 0 Reset value 0x1C 0 0 ADD1H Res. Res. Res. Res. Res. Res. Res. Res. Res. RTC_WUTR Res. 0x14 Res. Reset value WDU[2:0] 0 TAMP3F 0 0 RECALPF 0 0 0 BKP 0 0 0 SUB1H 0 Res. Res. Res. Res. Res. Res. Res. Res. RTC_PRER 0 0 Reset value 0x10 0 MNU[3:0] Res. 0 Res. POL COE 0 Res. OSE L [1:0] 0 COSEL 0 Res. 0 0 MNT[2:0] MT 0 YU[3:0] ITSE Res. Res. Res. Res. Res. Res. RTC_ISR 0x0C Res. Reset value 0 Res. Res. Res. Res. Res. Res. Res. RTC_CR 0x08 0 HU[3:0] YT[3:0] 0 Res. Reset value HT [1:0] ITSF Res. Res. Res. Res. Res. Res. Res. RTC_DR 0x04 0 Res. Reset value PM Res. Res. Res. Res. Res. Res. Res. RTC_TR 0x00 Res. Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 171. RTC register map and reset values 0 0 0 0 0 0 0 0 0 0x4C 0x50 to 0xCC RTC_ OR Reset value Reset value 0 0 0 0 0 0 Res. Reset value 0 0 MASKSS [3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_BKP0R 0 to RTC_BKP31R 0 0 0 DocID024597 Rev 1 Res. Res. Res. Res. Res. 0 Res. 0 Res. 0 Res. Reset value TAMP2NOERASE TAMP2IE TAMP1MF TAMP1NOERASE TAMP1IE TAMPPUDIS 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAMP1E 0 .TAMPIE SS[14:0] TAMP1TRG 0 .TAMP2E SS[14:0] TAMP3E 0 TAMP2-TRG 0 TAMPTS CALW8 CALW16 Res. Res. Res. Res. CALP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 TAMP3-TRG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. RTC_ CALR 0 TAMPFREQ[2:0] TAMPFLT[1:0] TAMPPRCH[1:0] TAMP3IE TAMP2MF TAMP3NOERASE 0 Res. MASKSS [3:0] TAMP3MF Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value RTC_ALARM_TYPE RTC_ ALRMBSSR Res. Reset value RTC_OUT_RMP 0x48 RTC_ ALRMASSR Res. 0x44 RTC_TAMPCR Res. 0x40 Res. 0x3C Res. Offset Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RM0351 Real-time clock (RTC) Table 171. RTC register map and reset values (continued) CALM[8:0] 0 0 0 0 0 0 0 0 0 0 BKP[31:0] BKP[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 68 for the register boundary addresses. 1097/1680 1097 Inter-integrated circuit (I2C) interface RM0351 35 Inter-integrated circuit (I2C) interface 35.1 Introduction The I2C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial I2C bus. It provides multimaster capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+). It is also SMBus (system management bus) and PMBus (power management bus) compatible. DMA can be used to reduce CPU overload. 35.2 I2C main features • 1098/1680 I2C bus specification rev03 compatibility: – Slave and master modes – Multimaster capability – Standard-mode (up to 100 kHz) – Fast-mode (up to 400 kHz) – Fast-mode Plus (up to 1 MHz) – 7-bit and 10-bit addressing mode – Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) – All 7-bit addresses acknowledge mode – General call – Programmable setup and hold times – Easy to use event management – Optional clock stretching – Software reset • 1-byte buffer with DMA capability • Programmable analog and digital noise filters DocID024597 Rev 1 RM0351 Inter-integrated circuit (I2C) interface The following additional features are also available depending on the product implementation (see Section 35.3: I2C implementation): • SMBus specification rev 2.0 compatibility: – 35.3 Hardware PEC (Packet Error Checking) generation and verification with ACK control – Command and data acknowledge control – Address resolution protocol (ARP) support – Host and Device support – SMBus alert – Timeouts and idle condition detection • PMBus rev 1.1 standard compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming • Wakeup from Stop mode on address match. I2C implementation This manual describes the full set of features implemented in I2C1, I2C3 and I2C3./I2C3. In the STM32L4x6 devices I2C1, I2C2, and I2C3 implement the full set of features as shown in the following table, with the restriction than only I2C3 can wake up from Stop 2 mode. Table 172. STM32L4x6 I2C implementation I2C features(1) I2C1 I2C2 I2C3 7-bit addressing mode X X X 10-bit addressing mode X X X Standard-mode (up to 100 kbit/s) X X X Fast-mode (up to 400 kbit/s) X X X Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X Independent clock X X X SMBus X X X Wakeup from Stop 1 mode X X X Wakeup from Stop 2 mode - - X 1. X = supported. 35.4 I2C functional description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa. The interrupts are enabled or disabled by software. The interface is connected to the I2C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected with a standard (up to 100 kHz), Fast-mode (up to 400 kHz) or Fast-mode Plus (up to 1 MHz) I2C bus. This interface can also be connected to a SMBus with the data pin (SDA) and clock pin (SCL). DocID024597 Rev 1 1099/1680 1167 Inter-integrated circuit (I2C) interface RM0351 If SMBus feature is supported: the additional optional SMBus Alert pin (SMBA) is also available. 35.4.1 I2C block diagram The block diagram of the I2C interface is shown in Figure 348. Figure 348. I2C block diagram 6<6&/. $3% ,&&/. )URPV\VWHPFRQILJXUDWLRQ FRQWUROOHU 6<6&)* )0GULYH +6, 'DWDFRQWURO 6KLIWUHJLVWHU 5&&B,&[6: IURPUHVHWDQG FORFN FRQWUROOHU 'LJLWDO QRLVH ILOWHU :83(1 $QDORJ QRLVH ILOWHU *3,2 ORJLF ,&[B6'$ 60%86 3(& JHQHUDWLRQ FKHFN :DNHXS RQ DGGUHVV PDWFK )URPV\VWHPFRQILJXUDWLRQ FRQWUROOHU 6<6&)* )0GULYH &ORFNFRQWURO 0DVWHUFORFN JHQHUDWLRQ 6ODYHFORFN VWUHWFKLQJ 'LJLWDO QRLVH ILOWHU $QDORJ QRLVH ILOWHU *3,2 ORJLF ,&[B6&/ 60%XV 7LPHRXW FKHFN 60%XV$OHUW FRQWURO VWDWXV 3&/. ,&[B60%$ 5HJLVWHUV $3%EXV 069 The I2C is clocked by an independent clock source which allows to the I2C to operate independently from the PCLK frequency. 1100/1680 DocID024597 Rev 1 RM0351 Inter-integrated circuit (I2C) interface This independent clock source can be selected for either of the following three clock sources: • PCLK1: APB1 clock (default value) • HSI16: internal 16 MHz RC oscillator • SYSCLK: system clock Refer to Section 8: Reset and clock control (RCC) for more details. I2C I/Os support 20 mA output current drive for Fast-mode Plus operation. This is enabled by setting the driving capability control bits for SCL and SDA in Section 10.2.3: SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) 35.4.2 I2C clock requirements The I2C kernel is clocked by I2CCLK. The I2CCLK period tI2CCLK must respect the following conditions: tI2CCLK < (tLOW - tfilters ) / 4 and tI2CCLK < tHIGH with: tLOW: SCL low time and tHIGH : SCL high time tfilters: when enabled, sum of the delays brought by the analog filter and by the digital filter. Analog filter delay is maximum 260 ns. Digital filter delay is DNF x tI2CCLK. The PCLK clock period tPCLK must respect the following condition: tPCLK < 4/3 tSCL with tSCL: SCL period Caution: When the I2C kernel is clocked by PCLK. PCLK must respect the conditions for tI2CCLK. 35.4.3 Mode selection The interface can operate in one of the four following modes: • Slave transmitter • Slave receiver • Master transmitter • Master receiver By default, it operates in slave mode. The interface automatically switches from slave to master when it generates a START condition, and from master to slave if an arbitration loss or a STOP generation occurs, allowing multimaster capability. Communication flow In Master mode, the I2C interface initiates a data transfer and generates the clock signal. A serial data transfer always begins with a START condition and ends with a STOP condition. Both START and STOP conditions are generated in master mode by software. In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and the General Call address. The General Call address detection can be enabled or disabled by software. The reserved SMBus addresses can also be enabled by software. DocID024597 Rev 1 1101/1680 1167 Inter-integrated circuit (I2C) interface RM0351 Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the START condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to the following figure. Figure 349. I2C bus protocol 3$! !#+ -3" 3#, 3TOP CONDITION 3TART CONDITION -36 Acknowledge can be enabled or disabled by software. The I2C interface addresses can be selected by software. 1102/1680 DocID024597 Rev 1 RM0351 35.4.4 Inter-integrated circuit (I2C) interface I2C initialization Enabling and disabling the peripheral The I2C peripheral clock must be configured and enabled in the clock controller (refer to Section 8: Reset and clock control (RCC)). Then the I2C can be enabled by setting the PE bit in the I2C_CR1 register. When the I2C is disabled (PE=0), the I2C performs a software reset. Refer to Section 35.4.5: Software reset for more details. Noise filters Before you enable the I2C peripheral by setting the PE bit in I2C_CR1 register, you must configure the noise filters, if needed. By default, an analog noise filter is present on the SDA and SCL inputs. This analog filter is compliant with the I2C specification which requires the suppression of spikes with a pulse width up to 50 ns in Fast-mode and Fast-mode Plus. You can disable this analog filter by setting the ANFOFF bit, and/or select a digital filter by configuring the DNF[3:0] bit in the I2C_CR1 register. When the digital filter is enabled, the level of the SCL or the SDA line is internally changed only if it remains stable for more than DNF x I2CCLK periods. This allows to suppress spikes with a programmable length of 1 to 15 I2CCLK periods. Table 173. Comparison of analog vs. digital filters Pulse width of suppressed spikes Benefits Drawbacks Caution: Analog filter Digital filter ≥ 50 ns Programmable length from 1 to 15 I2C peripheral clocks Available in Stop mode – Programmable length: extra filtering capability vs. standard requirements – Stable length Variation vs. temperature, voltage, process Wakeup from Stop mode on address match is not available when digital filter is enabled Changing the filter configuration is not allowed when the I2C is enabled. DocID024597 Rev 1 1103/1680 1167 Inter-integrated circuit (I2C) interface RM0351 I2C timings The timings must be configured in order to guarantee a correct data hold and setup time, used in master and slave modes. This is done by programming the PRESC[3:0], SCLDEL[3:0] and SDADEL[3:0] bits in the I2C_TIMINGR register. Figure 350. Setup and hold timings '$7$+2/'7,0( 6&/IDOOLQJHGJHLQWHUQDOGHWHFWLRQ W6<1& 6'$'(/ 6'$RXWSXWGHOD\ 6&/ 6'$ W+''$7 'DWDKROGWLPH '$7$6(7837,0( 6&/'(/ 6&/VWUHWFKHGORZE\WKHVODYHWUDQVPLWWHU 6&/ 6'$ W68'$7 'DWDVHWXSWLPH 069 • When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is tSDADEL = SDADEL x tPRESC + tI2CCLK where tPRESC = (PRESC+1) x tI2CCLK. TSDADEL impacts the hold time tHD;DAT. The total SDA output delay is: tSYNC1 + {[SDADEL x (PRESC+1) + 1] x tI2CCLK } 1104/1680 DocID024597 Rev 1 RM0351 Inter-integrated circuit (I2C) interface tSYNC1 duration depends on these parameters: – SCL falling slope – When enabled, input delay brought by the analog filter: tAF(min) < tAF < tAF(max) ns. – When enabled, input delay brought by the digital filter: tDNF = DNF x tI2CCLK – Delay due to SCL synchronization to I2CCLK clock (2 to 3 I2CCLK periods) In order to bridge the undefined region of the SCL falling edge, you must program SDADEL in such a way that: {tf (max) +tHD;DAT (min) -tAF(min) - [(DNF +3) x tI2CCLK]} / {(PRESC +1) x tI2CCLK } ≤ SDADEL SDADEL ≤ {tHD;DAT (max) -tAF(max) - [(DNF+4) x tI2CCLK]} / {(PRESC +1) x tI2CCLK } Note: tAF(min) / tAF(max) are part of the equation only when the analog filter is enabled. Refer to device datasheet for tAF values. The maximum tHD;DAT could be 3.45 µs, 0.9 µs and 0.45 µs for Standard-mode, Fast-mode and Fast-mode Plus, but must be less than the maximum of tVD;DAT by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. The SDA rising edge is usually the worst case, so in this case the previous equation becomes: SDADEL ≤ {tVD;DAT (max) -tr (max) -260 ns - [(DNF+4) x tI2CCLK]} / {(PRESC +1) x tI2CCLK }. Note: This condition can be violated when NOSTRETCH=0, because the device stretches SCL low to guarantee the set-up time, according to the SCLDEL value. Refer to Table 174: I2C-SMBUS specification data setup and hold times for tf, tr, tHD;DAT and tVD;DAT standard values. • After sending SDA output, SCL line is kept at low level during the setup time. This setup time is tSCLDEL = (SCLDEL+1) x tPRESC where tPRESC = (PRESC+1) x tI2CCLK. tSCLDEL impacts the setup time tSU;DAT . In order to bridge the undefined region of the SDA transition (rising edge usually worst case), you must program SCLDEL in such a way that: {[tr (max) + tSU;DAT (min)] / [(PRESC+1)] x tI2CCLK]} - 1 <= SCLDEL Refer to Table 174: I2C-SMBUS specification data setup and hold times for tr and tSU;DAT standard values. The SDA and SCL transition time values to be used are the ones in the application. Using the maximum values from the standard increases the constraints for the SDADEL and SCLDEL calculation, but ensures the feature whatever the application. DocID024597 Rev 1 1105/1680 1167 Inter-integrated circuit (I2C) interface RM0351 Table 174. I2C-SMBUS specification data setup and hold times Symbol Parameter Standard-mode (Sm) Fast-mode (Fm) Fast-mode Plus (Fm+) SMBUS Unit Min. Max Min. Max Min. Max Min. Max tHD;DAT Data hold time 0 - 0 - 0 - 0.3 - tVD;DAT Data valid time - 3.45 - 0.9 - 0.45 - - tSU;DAT Data setup time 250 - 100 tr Rise time of both SDA and SCL signals - 1000 tf Fall time of both SDA and SCL signals - 50 300 - µs 250 120 - 1000 ns 300 300 - 120 - 300 Additionally, in master mode, the SCL clock high and low levels must be configured by programming the PRESC[3:0], SCLH[7:0] and SCLL[7:0] bits in the I2C_TIMINGR register. • When the SCL falling edge is internally detected, a delay is inserted before releasing the SCL output. This delay is tSCLL = (SCLL+1) x tPRESC where tPRESC = (PRESC+1) x tI2CCLK. tSCLL impacts the SCL low time tLOW . • When the SCL rising edge is internally detected, a delay is inserted before forcing the SCL output to low level. This delay is tSCLH = (SCLH+1) x tPRESC where tPRESC = (PRESC+1) x tI2CCLK. tSCLH impacts the SCL high time tHIGH . Refer to section : I2C master initialization for more details. Caution: Changing the timing configuration is not allowed when the I2C is enabled. The I2C slave NOSTRETCH mode must also be configured before enabling the peripheral. Refer to : I2C slave initialization for more details. Caution: 1106/1680 Changing the NOSTRETCH configuration is not allowed when the I2C is enabled. DocID024597 Rev 1 RM0351 Inter-integrated circuit (I2C) interface Figure 351. I2C initialization flowchart ,QLWLDOVHWWLQJV &OHDU3(ELWLQ,&B&5 &RQILJXUH$1)2))DQG'1)>@LQ,&B&5 &RQILJXUH35(6&>@ 6'$'(/>@6&/'(/>@6&/+>@ 6&//>@LQ,&B7,0,1*5 &RQILJXUH12675(7&+LQ,&B&5 6HW3(ELWLQ,&B&5 (QG D^ϭϵϴϰϳsϮ 35.4.5 Software reset A software reset can be performed by clearing the PE bit in the I2C_CR1 register. In that case I2C lines SCL and SDA are released. Internal states machines are reset and communication control bits, as well as status bits come back to their reset value. The configuration registers are not impacted. Here is the list of impacted register bits: 1. I2C_CR2 register: START, STOP, NACK 2. I2C_ISR register: BUSY, TXE, TXIS, RXNE, ADDR, NACKF, TCR, TC, STOPF, BERR, ARLO, OVR and in addition when the SMBus feature is supported: 1. I2C_CR2 register: PECBYTE 2. I2C_ISR register: PECERR, TIMEOUT, ALERT PE must be kept low during at least 3 APB clock cycles in order to perform the software reset. This is ensured by writing the following software sequence: - Write PE=0 - Check PE=0 - Write PE=1 DocID024597 Rev 1 1107/1680 1167 Inter-integrated circuit (I2C) interface 35.4.6 RM0351 Data transfer The data transfer is managed through transmit and receive data registers and a shift register. Reception The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is received), the shift register is copied into I2C_RXDR register if it is empty (RXNE=0). If RXNE=1, meaning that the previous received data byte has not yet been read, the SCL line is stretched low until I2C_RXDR is read. The stretch is inserted between the 8th and 9th SCL pulse (before the Acknowledge pulse). Figure 352. Data reception !#+ PULSE !#+ PULSE LEGEND 3#, 3HIFT REGISTER 3#, STRETCH XX DATA XX DATA XX 28.% RD DATA RD DATA )#?28$2 DATA DATA DATA -36 Transmission If the I2C_TXDR register is not empty (TXE=0), its content is copied into the shift register after the 9th SCL pulse (the Acknowledge pulse). Then the shift register content is shifted out on SDA line. If TXE=1, meaning that no data is written yet in I2C_TXDR, SCL line is stretched low until I2C_TXDR is written. The stretch is done after the 9th SCL pulse. 1108/1680 DocID024597 Rev 1 RM0351 Inter-integrated circuit (I2C) interface Figure 353. Data transmission !#+ PULSE !#+ PULSE LEGEND XX XX DATA 3HIFT REGISTER DATA 3#, 3#, STRETCH XX 48% WR DATA )#?48$2 DATA WR DATA DATA DATA -36 Hardware transfer management The I2C has a byte counter embedded in hardware in order to manage byte transfer and to close the communication in various modes such as: – NACK, STOP and ReSTART generation in master mode – ACK control in slave receiver mode – PEC generation/checking when SMBus feature is supported The byte counter is always used in master mode. By default it is disabled in slave mode, but it can be enabled by software by setting the SBC (Slave Byte Control) bit in the I2C_CR2 register. The number of bytes to be transferred is programmed in the NBYTES[7:0] bit field in the I2C_CR2 register. If the number of bytes to be transferred (NBYTES) is greater than 255, or if a receiver wants to control the acknowledge value of a received data byte, the reload mode must be selected by setting the RELOAD bit in the I2C_CR2 register. In this mode, TCR flag is set when the number of bytes programmed in NBYTES has been transferred, and an interrupt is generated if TCIE is set. SCL is stretched as long as TCR flag is set. TCR is cleared by software when NBYTES is written to a non-zero value. When the NBYTES counter is reloaded with the last number of bytes, RELOAD bit must be cleared. When RELOAD=0 in master mode, the counter can be used in 2 modes: • Automatic end mode (AUTOEND = ‘1’ in the I2C_CR2 register). In this mode, the master automatically sends a STOP condition once the number of bytes programmed in the NBYTES[7:0] bit field has been transferred. • Software end mode (AUTOEND = ‘0’ in the I2C_CR2 register). In this mode, software action is expected once the number of bytes programmed in the NBYTES[7:0] bit field has been transferred; the TC flag is set and an interrupt is generated if the TCIE bit is set. The SCL signal is stretched as long as the TC flag is set. The TC flag is cleared by software when the START or STOP bit is set in the I2C_CR2 register. This mode must be used when the master wants to send a RESTART condition. DocID024597 Rev 1 1109/1680 1167 Inter-integrated circuit (I2C) interface Caution: RM0351 The AUTOEND bit has no effect when the RELOAD bit is set. Table 175. I2C configuration table 35.4.7 Function SBC bit RELOAD bit AUTOEND bit Master Tx/Rx NBYTES + STOP x 0 1 Master Tx/Rx + NBYTES + RESTART x 0 0 Slave Tx/Rx all received bytes ACKed 0 x x Slave Rx with ACK control 1 1 x I2C slave mode I2C slave initialization In order to work in slave mode, you must enable at least one slave address. Two registers I2C_OAR1 and I2C_OAR2 are available in order to program the slave own addresses OA1 and OA2. • OA1 can be configured either in 7-bit mode (by default) or in 10-bit addressing mode by setting the OA1MODE bit in the I2C_OAR1 register. OA1 is enabled by setting the OA1EN bit in the I2C_OAR1 register. • If additional slave addresses are required, you can configure the 2nd slave address OA2. Up to 7 OA2 LSB can be masked by configuring the OA2MSK[2:0] bits in the I2C_OAR2 register. Therefore for OA2MSK configured from 1 to 6, only OA2[7:2], OA2[7:3], OA2[7:4], OA2[7:5], OA2[7:6] or OA2[7] are compared with the received address. As soon as OA2MSK is not equal to 0, the address comparator for OA2 excludes the I2C reserved addresses (0000 XXX and 1111 XXX), which are not acknowledged. If OA2MSK=7, all received 7-bit addresses are acknowledged (except reserved addresses). OA2 is always a 7-bit address. These reserved addresses can be acknowledged if they are enabled by the specific enable bit, if they are programmed in the I2C_OAR1 or I2C_OAR2 register with OA2MSK=0. OA2 is enabled by setting the OA2EN bit in the I2C_OAR2 register. • The General Call address is enabled by setting the GCEN bit in the I2C_CR1 register. When the I2C is selected by one of its enabled addresses, the ADDR interrupt status flag is set, and an interrupt is generated if the ADDRIE bit is set. By default, the slave uses its clock stretching capability, which means that it stretches the SCL signal at low level when needed, in order to perform software actions. If the master does not support clock stretching, the I2C must be configured with NOSTRETCH=1 in the I2C_CR1 register. After receiving an ADDR interrupt, if several addresses are enabled you must read the ADDCODE[6:0] bits in the I2C_ISR register in order to check which address matched. DIR flag must also be checked in order to know the transfer direction. 1110/1680 DocID024597 Rev 1 RM0351 Inter-integrated circuit (I2C) interface Slave clock stretching (NOSTRETCH = 0) In default mode, the I2C slave stretches the SCL clock in the following situations: • When the ADDR flag is set: the received address matches with one of the enabled slave addresses. This stretch is released when the ADDR flag is cleared by software setting the ADDRCF bit. • In transmission, if the previous data transmission is completed and no new data is written in I2C_TXDR register, or if the first data byte is not written when the ADDR flag is cleared (TXE=1). This stretch is released when the data is written to the I2C_TXDR register. • In reception when the I2C_RXDR register is not read yet and a new data reception is completed. This stretch is released when I2C_RXDR is read. • When TCR = 1 in Slave Byte Control mode, reload mode (SBC=1 and RELOAD=1), meaning that the last data byte has been transferred. This stretch is released when then TCR is cleared by writing a non-zero value in the NBYTES[7:0] field. • After SCL falling edge detection, the I2C stretches SCL low during [(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x tI2CCLK. Slave without clock stretching (NOSTRETCH = 1) When NOSTRETCH = 1 in the I2C_CR1 register, the I2C slave does not stretch the SCL signal. • The SCL clock is not stretched while the ADDR flag is set. • In transmission, the data must be written in the I2C_TXDR register before the first SCL pulse corresponding to its transfer occurs. If not, an underrun occurs, the OVR flag is set in the I2C_ISR register and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register. The OVR flag is also set when the first data transmission starts and the STOPF bit is still set (has not been cleared). Therefore, if you clear the STOPF flag of the previous transfer only after writing the first data to be transmitted in the next transfer, you ensure that the OVR status is provided, even for the first data to be transmitted. • In reception, the data must be read from the I2C_RXDR register before the 9th SCL pulse (ACK pulse) of the next data byte occurs. If not an overrun occurs, the OVR flag is set in the I2C_ISR register and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register. Slave Byte Control Mode In order to allow byte ACK control in slave reception mode, Slave Byte Control mode must be enabled by setting the SBC bit in the I2C_CR1 register. This is required to be compliant with SMBus standards. Reload mode must be selected in order to allow byte ACK control in slave reception mode (RELOAD=1). To get control of each byte, NBYTES must be initialized to 0x1 in the ADDR interrupt subroutine, and reloaded to 0x1 after each received byte. When the byte is received, the TCR bit is set, stretching the SCL signal low between the 8th and 9th SCL pulses. You can read the data from the I2C_RXDR register, and then decide to acknowledge it or not by configuring the ACK bit in the I2C_CR2 register. The SCL stretch is released by programming NBYTES to a non-zero value: the acknowledge or not-acknowledge is sent and next byte can be received. NBYTES can be loaded with a value greater than 0x1, and in this case, the reception flow is continuous during NBYTES data reception. DocID024597 Rev 1 1111/1680 1167 Inter-integrated circuit (I2C) interface Note: RM0351 The SBC bit must be configured when the I2C is disabled, or when the slave is not addressed, or when ADDR=1. The RELOAD bit value can be changed when ADDR=1, or when TCR=1. Caution: Slave Byte Control mode is not compatible with NOSTRETCH mode. Setting SBC when NOSTRETCH=1 is not allowed. Figure 354. Slave initialization flowchart 6ODYH LQLWLDOL]DWLRQ ,QLWLDOVHWWLQJV &OHDU^2$(12$(1`LQ,&B&5 &RQILJXUH^2$>@2$02'(2$(1 2$>@2$06.>@2$(1*&(1` &RQILJXUH6%&LQ,&B&5 (QDEOHLQWHUUXSWVDQGRU '0$LQ,&B&5 (QG 6%&PXVWEHVHWWRVXSSRUW60%XVIHDWXUHV D^ϭϵϴϱϬsϮ Slave transmitter A transmit interrupt status (TXIS) is generated when the I2C_TXDR register becomes empty. An interrupt is generated if the TXIE bit is set in the I2C_CR1 register. The TXIS bit is cleared when the I2C_TXDR register is written with the next data byte to be transmitted. When a NACK is received, the NACKF bit is set in the I2C_ISR register and an interrupt is generated if the NACKIE bit is set in the I2C_CR1 register. The slave automatically releases the SCL and SDA lines in order to let the master perform a STOP or a RESTART condition. The TXIS bit is not set when a NACK is received. When a STOP is received and the STOPIE bit is set in the I2C_CR1 register, the STOPF flag is set in the I2C_ISR register and an interrupt is generated. In most applications, the SBC bit is usually programmed to ‘0’. In this case, If TXE = 0 when the slave address is 1112/1680 DocID024597 Rev 1 RM0351 Inter-integrated circuit (I2C) interface received (ADDR=1), you can choose either to send the content of the I2C_TXDR register as the first data byte, or to flush the I2C_TXDR register by setting the TXE bit in order to program a new data byte. In Slave Byte Control mode (SBC=1), the number of bytes to be transmitted must be programmed in NBYTES in the address match interrupt subroutine (ADDR=1). In this case, the number of TXIS events during the transfer corresponds to the value programmed in NBYTES. Caution: When NOSTRETCH=1, the SCL clock is not stretched while the ADDR flag is set, so you cannot flush the I2C_TXDR register content in the ADDR subroutine, in order to program the first data byte. The first data byte to be sent must be previously programmed in the I2C_TXDR register: • This data can be the data written in the last TXIS event of the previous transmission message. • If this data byte is not the one to be sent, the I2C_TXDR register can be flushed by setting the TXE bit in order to program a new data byte. The STOPF bit must be cleared only after these actions, in order to guarantee that they are executed before the first data transmission starts, following the address acknowledge. If STOPF is still set when the first data transmission starts, an underrun error will be generated (the OVR flag is set). If you need a TXIS event, (Transmit Interrupt or Transmit DMA request), you must set the TXIS bit in addition to the TXE bit, in order to generate a TXIS event. DocID024597 Rev 1 1113/1680 1167 Inter-integrated circuit (I2C) interface RM0351 Figure 355. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0 6ODYH WUDQVPLVVLRQ 6ODYHLQLWLDOL]DWLRQ 1R ,&B,65$''5 " 255 bytes 0DVWHU WUDQVPLVVLRQ 0DVWHULQLWLDOL]DWLRQ 1%<7(6 [))1 1 5(/2$' &RQILJXUHVODYHDGGUHVV 6HW,&B&567$57 1R 1R ,&B,657;,6 ,&B,651$&.) " " 255 bytes 0DVWHUUHFHSWLRQ 0DVWHULQLWLDOL]DWLRQ 1%<7(6 [))1 1 5(/2$' &RQILJXUHVODYHDGGUHVV 6HW,&B&567$57 ,&B,655;1( " 1R @ 5( I&. 1RWH 7UDQVPLWWHU UDWHFRQWUROOHU 5HFHLYHUUDWH FRQWUROOHU &RQYHQWLRQDOEDXGUDWHJHQHUDWRU 069 1. For details on coding USARTDIV in the USARTx_BRR register, please refer to Section 36.5.4: Baud rate generation. 2. fCK can be fLSE, fHSI, fPCLK, fSYS. 1172/1680 DocID024597 Rev 1 RM0351 36.5.1 Universal synchronous asynchronous receiver transmitter (USART) USART character description The word length can be selected as being either 7 or 8 or 9 bits by programming the M[1:0] bits in the USARTx_CR1 register (see Figure 380). Note: • 7-bit character length: M[1:0] = 10 • 8-bit character length: M[1:0] = 00 • 9-bit character length: M[1:0] = 01 In 7-bit data length mode, the Smartcard mode, LIN master mode and Autobaudrate (0x7F and 0x55 frames detection) are not supported. 7-bit mode is supported only on some USARTs. In default configuration, the signal (TX or RX) is in low state during the start bit. It is in high state during the stop bit. These values can be inverted, separately for each signal, through polarity configuration control. An Idle character is interpreted as an entire frame of “1”s. (The number of “1” ‘s will include the number of stop bits). A Break character is interpreted on receiving “0”s for a frame period. At the end of the break frame, the transmitter inserts 2 stop bits. Transmission and reception are driven by a common baud rate generator, the clock for each is generated when the enable bit is set respectively for the transmitter and receiver. The details of each block is given below. DocID024597 Rev 1 1173/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Figure 380. Word length programming ELWZRUGOHQJWK 0 6WRSELW 3RVVLEOH 3DULW\ ELW 'DWDIUDPH 6WDUW ELW %LW %LW %LW %LW %LW %LW %LW %LW %LW 6WRS ELW 1H[W 6WDUW ELW &ORFN 6WDUW ELW ,GOHIUDPH 6WRS ELW 6WRS ELW 6WRS ELW 6WRS ELW 6WDUW ELW 6WRS ELW 6WDUW ELW %UHDNIUDPH 6WDUW ELW ELWZRUGOHQJWK 0 6WRSELW 3RVVLEOH 3DULW\ ELW 'DWDIUDPH 6WDUW ELW %LW %LW %LW %LW %LW %LW %LW %LW 6WRS ELW 1H[W 6WDUW ELW &ORFN 6WDUW ELW ,GOHIUDPH %UHDNIUDPH ELWZRUGOHQJWK 0 6WRSELW 3RVVLEOH 3DULW\ ELW 'DWDIUDPH 6WDUW ELW %LW %LW %LW %LW %LW %LW %LW 6WRS ELW 1H[W 6WDUW ELW &ORFN ,GOHIUDPH %UHDNIUDPH 6WDUW ELW 6WRS ELW /%&/ELWFRQWUROVODVWGDWDFORFNSXOVH 069 36.5.2 Transmitter The transmitter can send data words of either 7, 8 or 9 bits depending on the M bits status. The Transmit Enable bit (TE) must be set in order to activate the transmitter function. The data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the SCLK pin. 1174/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Character transmission During an USART transmission, data shifts out least significant bit first (default configuration) on the TX pin. In this mode, the USARTx_TDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 379). Every character is preceded by a start bit which is a logic level low for one bit period. The character is terminated by a configurable number of stop bits. The following stop bits are supported by USART: 1, 1.5 and 2 stop bits. Note: The TE bit must be set before writing the data to be transmitted to the USARTx_TDR. The TE bit should not be reset during transmission of data. Resetting the TE bit during the transmission will corrupt the data on the TX pin as the baud rate counters will get frozen. The current data being transmitted will be lost. An idle frame will be sent after the TE bit is enabled. Configurable stop bits The number of stop bits to be transmitted with every character can be programmed in Control register 2, bits 13,12. • 1 stop bit: This is the default value of number of stop bits. • 2 stop bits: This will be supported by normal USART, single-wire and modem modes. • 1.5 stop bits: To be used in Smartcard mode. An idle frame transmission will include the stop bits. A break transmission will be 10 low bits (when M[1:0] = 00) or 11 low bits (when M[1:0] = 01) or 9 low bits (when M[1:0] = 10) followed by 2 stop bits (see Figure 381). It is not possible to transmit long breaks (break of length greater than 9/10/11 low bits). Figure 381. Configurable stop bits ELWGDWD6WRSELW 3RVVLEOH SDULW\ELW 'DWDIUDPH 6WDUWELW %LW %LW %LW %LW %LW %LW %LW %LW 6WRS ELW 1H[W 1H[WGDWDIUDPH VWDUW ELW &/2&. /%&/ELWFRQWUROVODVWGDWDFORFNSXOVH ELWGDWD6WRSELWV 3RVVLEOH SDULW\ELW 'DWDIUDPH 6WDUWELW %LW %LW %LW %LW %LW %LW %LW %LW 6WRS ELWV 1H[W VWDUW ELW 1H[WGDWDIUDPH ELWGDWD6WRSELWV 3RVVLEOH SDULW\ELW 'DWDIUDPH 6WDUWELW %LW %LW %LW %LW %LW %LW %LW %LW 6WRS ELWV 1H[W VWDUW ELW 1H[WGDWDIUDPH 06Y9 DocID024597 Rev 1 1175/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Character transmission procedure 1. Program the M bits in USARTx_CR1 to define the word length. 2. Select the desired baud rate using the USARTx_BRR register. 3. Program the number of stop bits in USARTx_CR2. 4. Enable the USART by writing the UE bit in USARTx_CR1 register to 1. 5. Select DMA enable (DMAT) in USARTx_CR3 if multibuffer communication is to take place. Configure the DMA register as explained in multibuffer communication. 6. Set the TE bit in USARTx_CR1 to send an idle frame as first transmission. 7. Write the data to send in the USARTx_TDR register (this clears the TXE bit). Repeat this for each data to be transmitted in case of single buffer. 8. After writing the last data into the USARTx_TDR register, wait until TC=1. This indicates that the transmission of the last frame is complete. This is required for instance when the USART is disabled or enters the Halt mode to avoid corrupting the last transmission. Single byte communication Clearing the TXE bit is always performed by a write to the transmit data register. The TXE bit is set by hardware and it indicates: • The data has been moved from the USARTx_TDR register to the shift register and the data transmission has started. • The USARTx_TDR register is empty. • The next data can be written in the USARTx_TDR register without overwriting the previous data. This flag generates an interrupt if the TXEIE bit is set. When a transmission is taking place, a write instruction to the USARTx_TDR register stores the data in the TDR register; next, the data is copied in the shift register at the end of the currently ongoing transmission. When no transmission is taking place, a write instruction to the USARTx_TDR register places the data in the shift register, the data transmission starts, and the TXE bit is set. If a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An interrupt is generated if the TCIE bit is set in the USARTx_CR1 register. After writing the last data in the USARTx_TDR register, it is mandatory to wait for TC=1 before disabling the USART or causing the microcontroller to enter the low-power mode (see Figure 382: TC/TXE behavior when transmitting). 1176/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Figure 382. TC/TXE behavior when transmitting )DLE PREAMBLE &RAME &RAME &RAME 48 LINE SET BY HARDWARE CLEARED BY SOFTWARE 48% FLAG 53!24?$2 SET BY HARDWARE CLEARED BY SOFTWARE & & SET BY HARDWARE & SET BY HARDWARE 4# FLAG SOFTWARE ENABLES THE 53!24 SOFTWARE WAITS UNTIL 48% AND WRITES & INTO $2 SOFTWARE WAITS UNTIL 48% AND WRITES & INTO $2 4# IS NOT SET BECAUSE 48% SOFTWARE WAITS UNTIL 48% AND WRITES & INTO $2 4# IS NOT SET BECAUSE 48% 4# IS SET BECAUSE 48% SOFTWARE WAITS UNTIL 4# AIB Break characters Setting the SBKRQ bit transmits a break character. The break frame length depends on the M bits (see Figure 380). If a ‘1’ is written to the SBKRQ bit, a break character is sent on the TX line after completing the current character transmission. The SBKF bit is set by the write operation and it is reset by hardware when the break character is completed (during the stop bits after the break character). The USART inserts a logic 1 signal (STOP) for the duration of 2 bits at the end of the break frame to guarantee the recognition of the start bit of the next frame. In the case the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. Idle characters Setting the TE bit drives the USART to send an idle frame before the first data frame. 36.5.3 Receiver The USART can receive data words of either 7, 8 or 9 bits depending on the M bits in the USARTx_CR1 register. Start bit detection The start bit detection sequence is the same when oversampling by 16 or by 8. In the USART, the start bit is detected when a specific sequence of samples is recognized. This sequence is: 1 1 1 0 X 0 X 0X 0X 0 X 0X 0. DocID024597 Rev 1 1177/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Figure 383. Start bit detection when oversampling by 16 or 8 28 STATE )DLE 3TART BIT 28 LINE )DEAL SAMPLE CLOCK 8 8 SAMPLED VALUES 2EAL SAMPLE CLOCK 8 8 8 8 8 8 8 8 /NE BIT TIME #ONDITIONS TO VALIDATE THE START BIT &ALLING EDGE DETECTION Note: 8 8 !T LEAST BITS OUT OF AT 8 !T LEAST BITS OUT OF AT 8 8 8 8 AI If the sequence is not complete, the start bit detection aborts and the receiver returns to the idle state (no flag is set), where it waits for a falling edge. The start bit is confirmed (RXNE flag set, interrupt generated if RXNEIE=1) if the 3 sampled bits are at 0 (first sampling on the 3rd, 5th and 7th bits finds the 3 bits at 0 and second sampling on the 8th, 9th and 10th bits also finds the 3 bits at 0). The start bit is validated (RXNE flag set, interrupt generated if RXNEIE=1) but the NF noise flag is set if, a. for both samplings, 2 out of the 3 sampled bits are at 0 (sampling on the 3rd, 5th and 7th bits and sampling on the 8th, 9th and 10th bits) or b. for one of the samplings (sampling on the 3rd, 5th and 7th bits or sampling on the 8th, 9th and 10th bits), 2 out of the 3 bits are found at 0. If neither conditions a. or b. are met, the start detection aborts and the receiver returns to the idle state (no flag is set). 1178/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Character reception During an USART reception, data shifts in least significant bit first (default configuration) through the RX pin. In this mode, the USARTx_RDR register consists of a buffer (RDR) between the internal bus and the receive shift register. Character reception procedure 1. Program the M bits in USARTx_CR1 to define the word length. 2. Select the desired baud rate using the baud rate register USARTx_BRR 3. Program the number of stop bits in USARTx_CR2. 4. Enable the USART by writing the UE bit in USARTx_CR1 register to 1. 5. Select DMA enable (DMAR) in USARTx_CR3 if multibuffer communication is to take place. Configure the DMA register as explained in multibuffer communication. 6. Set the RE bit USARTx_CR1. This enables the receiver which begins searching for a start bit. When a character is received: • The RXNE bit is set to indicate that the content of the shift register is transferred to the RDR. In other words, data has been received and can be read (as well as its associated error flags). • An interrupt is generated if the RXNEIE bit is set. • The error flags can be set if a frame error, noise or an overrun error has been detected during reception. PE flag can also be set with RXNE. • In multibuffer, RXNE is set after every byte received and is cleared by the DMA read of the Receive data Register. • In single buffer mode, clearing the RXNE bit is performed by a software read to the USARTx_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. The RXNE bit must be cleared before the end of the reception of the next character to avoid an overrun error. Break character When a break character is received, the USART handles it as a framing error. Idle character When an idle frame is detected, there is the same procedure as for a received data character plus an interrupt if the IDLEIE bit is set. DocID024597 Rev 1 1179/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Overrun error An overrun error occurs when a character is received when RXNE has not been reset. Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared. The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set when the next data is received or the previous DMA request has not been serviced. When an overrun error occurs: Note: • The ORE bit is set. • The RDR content will not be lost. The previous data is available when a read to USARTx_RDR is performed. • The shift register will be overwritten. After that point, any data received during overrun is lost. • An interrupt is generated if either the RXNEIE bit is set or EIE bit is set. • The ORE bit is reset by setting the ORECF bit in the ICR register. The ORE bit, when set, indicates that at least 1 data has been lost. There are two possibilities: - if RXNE=1, then the last valid data is stored in the receive register RDR and can be read, - if RXNE=0, then it means that the last valid data has already been read and thus there is nothing to be read in the RDR. This case can occur when the last valid data is read in the RDR at the same time as the new (and lost) data is received. Selecting the clock source and the proper oversampling method The choice of the clock source is done through the Clock Control system (see Section Reset and clock control (RCC))). The clock source must be chosen before enabling the USART (by setting the UE bit). The choice of the clock source must be done according to two criteria: • Possible use of the USART in low-power mode • Communication speed. The clock source frequency is fCK. When the dual clock domain with the wakeup from Stop mode is supported, the clock source can be one of the following sources: PCLK (default), LSE, HSI16 or SYSCLK. Otherwise, the USART clock source is PCLK. Choosing LSE or HSI16 as clock source may allow the USART to receive data while the MCU is in low-power mode. Depending on the received data and wakeup mode selection, the USART wakes up the MCU, when needed, in order to transfer the received data by software reading the USARTx_RDR register or by DMA. For the other clock sources, the system must be active in order to allow USART communication. The communication speed range (specially the maximum communication speed) is also determined by the clock source. The receiver implements different user-configurable oversampling techniques (except in synchronous mode) for data recovery by discriminating between valid incoming data and noise. This allows a trade-off between the maximum communication speed and noise/clock inaccuracy immunity. 1180/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) The oversampling method can be selected by programming the OVER8 bit in the USARTx_CR1 register and can be either 16 or 8 times the baud rate clock (Figure 384 and Figure 385). Depending on the application: • Select oversampling by 8 (OVER8=1) to achieve higher speed (up to fCK/8). In this case the maximum receiver tolerance to clock deviation is reduced (refer to Section 36.5.5: Tolerance of the USART receiver to clock deviation on page 1186) • Select oversampling by 16 (OVER8=0) to increase the tolerance of the receiver to clock deviations. In this case, the maximum speed is limited to maximum fCK/16 where fCK is the clock source frequency. Programming the ONEBIT bit in the USARTx_CR3 register selects the method used to evaluate the logic level. There are two options: • The majority vote of the three samples in the center of the received bit. In this case, when the 3 samples used for the majority vote are not equal, the NF bit is set • A single sample in the center of the received bit Depending on the application: – select the three samples’ majority vote method (ONEBIT=0) when operating in a noisy environment and reject the data when a noise is detected (refer to Figure 189) because this indicates that a glitch occurred during the sampling. – select the single sample method (ONEBIT=1) when the line is noise-free to increase the receiver’s tolerance to clock deviations (see Section 36.5.5: Tolerance of the USART receiver to clock deviation on page 1186). In this case the NF bit will never be set. When noise is detected in a frame: • The NF bit is set at the rising edge of the RXNE bit. • The invalid data is transferred from the Shift register to the USARTx_RDR register. • No interrupt is generated in case of single byte communication. However this bit rises at the same time as the RXNE bit which itself generates an interrupt. In case of multibuffer communication an interrupt will be issued if the EIE bit is set in the USARTx_CR3 register. The NF bit is reset by setting NFCF bit in ICR register. Note: Oversampling by 8 is not available in LIN, smartcard and IrDA modes. In those modes, the OVER8 bit is forced to ‘0’ by hardware. DocID024597 Rev 1 1181/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Figure 384. Data sampling when oversampling by 16 5;OLQH VDPSOHGYDOXHV 6DPSOHFORFN 2QHELWWLPH 06Y9 Figure 385. Data sampling when oversampling by 8 5;OLQH VDPSOHGYDOXHV 6DPSOH FORFN [ 2QHELWWLPH 06Y9 Table 189. Noise detection from sampled data 1182/1680 Sampled value NE status Received bit value 000 0 0 001 1 0 010 1 0 011 1 1 100 1 0 101 1 1 110 1 1 111 0 1 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Framing error A framing error is detected when: The stop bit is not recognized on reception at the expected time, following either a desynchronization or excessive noise. When the framing error is detected: • The FE bit is set by hardware • The invalid data is transferred from the Shift register to the USARTx_RDR register. • No interrupt is generated in case of single byte communication. However this bit rises at the same time as the RXNE bit which itself generates an interrupt. In case of multibuffer communication an interrupt will be issued if the EIE bit is set in the USARTx_CR3 register. The FE bit is reset by writing 1 to the FECF in the USARTx_ICR register. Configurable stop bits during reception The number of stop bits to be received can be configured through the control bits of Control Register 2 - it can be either 1 or 2 in normal mode and 1.5 in Smartcard mode. • 1 stop bit: Sampling for 1 stop Bit is done on the 8th, 9th and 10th samples. • 1.5 stop bits (Smartcard mode): When transmitting in Smartcard mode, the device must check that the data is correctly sent. Thus the receiver block must be enabled (RE =1 in the USARTx_CR1 register) and the stop bit is checked to test if the smartcard has detected a parity error. In the event of a parity error, the smartcard forces the data signal low during the sampling - NACK signal-, which is flagged as a framing error. Then, the FE flag is set with the RXNE at the end of the 1.5 stop bit. Sampling for 1.5 stop bits is done on the 16th, 17th and 18th samples (1 baud clock period after the beginning of the stop bit). The 1.5 stop bit can be decomposed into 2 parts: one 0.5 baud clock period during which nothing happens, followed by 1 normal stop bit period during which sampling occurs halfway through. Refer to Section 36.5.13: Smartcard mode on page 1197 for more details. • 2 stop bits: Sampling for 2 stop bits is done on the 8th, 9th and 10th samples of the first stop bit. If a framing error is detected during the first stop bit the framing error flag will be set. The second stop bit is not checked for framing error. The RXNE flag will be set at the end of the first stop bit. DocID024597 Rev 1 1183/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) 36.5.4 RM0351 Baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as programmed in the USARTx_BRR register. Equation 1: Baud rate for standard USART (SPI mode included) (OVER8 = 0 or 1) In case of oversampling by 16, the equation is: f CK Tx/Rx baud = -------------------------------USARTDIV In case of oversampling by 8, the equation is: 2 × f CK Tx/Rx baud = -------------------------------USARTDIV Equation 2: Baud rate in smartcard, LIN and IrDA modes (OVER8 = 0) In smartcard, LIN and IrDA modes, only Oversampling by 16 is supported: f CK Tx/Rx baud = -------------------------------USARTDIV USARTDIV is an unsigned fixed point number that is coded on the USARTx_BRR register. Note: • When OVER8 = 0, BRR = USARTDIV. • When OVER8 = 1 – BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. – BRR[3] must be kept cleared. – BRR[15:4] = USARTDIV[15:4] The baud counters are updated to the new value in the baud registers after a write operation to USARTx_BRR. Hence the baud rate register value should not be changed during communication. In case of oversampling by 16 or 8, USARTDIV must be greater than or equal to 16d. How to derive USARTDIV from USARTx_BRR register values Example 1 To obtain 9600 baud with fCK = 8 MHz. • In case of oversampling by 16: USARTDIV = 8 000 000/9600 BRR = USARTDIV = 833d = 0341h • In case of oversampling by 8: USARTDIV = 2 * 8 000 000/9600 USARTDIV = 1666,66 (1667d = 683h) BRR[3:0] = 3h << 1 = 1h BRR = 0x681 1184/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Example 2 To obtain 921.6 Kbaud with fCK = 48 MHz. • In case of oversampling by 16: USARTDIV = 48 000 000/921 600 BRR = USARTDIV = 52d = 34h • In case of oversampling by 8: USARTDIV = 2 * 48 000 000/921 600 USARTDIV = 104 (104d = 68h) BRR[3:0] = USARTDIV[3:0] >> 1 = 8h >> 1 = 4h BRR = 0x64 Table 190. Error calculation for programmed baud rates at fCK = 72MHz in both cases of oversampling by 16 or by 8(1) Baud rate Oversampling by 16 (OVER8 = 0) Oversampling by 8 (OVER8 = 1) S.No Desired Actual BRR % Error = (Calculated Desired)B.Rate / Desired B.Rate 1 2.4 KBps 2.4 KBps 0x7530 0 2.4 KBps 0xEA60 0 2 9.6 KBps 9.6 KBps 0x1D4C 0 9.6 KBps 0x3A94 0 3 19.2 KBps 19.2 KBps 0xEA6 0 19.2 KBps 0x1D46 0 4 38.4 KBps 38.4 KBps 0x753 0 38.4 KBps 0xEA3 0 5 57.6 KBps 57.6 KBps 0x4E2 0 57.6 KBps 0x9C2 0 6 115.2 KBps 115.2 KBps 0x271 0 115.2 KBps 0x4E1 0 7 230.4 KBps 230.03KBps 0x139 0.16 230.4 KBps 0x270 0 8 460.8 KBps 461.54KBps 0x9C 0.16 460.06KBps 0x134 0.16 9 921.6 KBps 923.08KBps 0x4E 0.16 923.07KBps 0x96 0.16 10 2 MBps 2 MBps 0x24 0 2 MBps 0x44 0 11 3 MBps 3 MBps 0x18 0 3 MBps 0x30 0 12 4MBps 4MBps 0x12 0 4MBps 0x22 0 13 5MBps N.A N.A N.A 4965.51KBps 0x16 0.69 14 6MBps N.A N.A N.A 6MBps 0x14 0 15 7MBps N.A N.A N.A 6857.14KBps 0x12 2 16 9MBps N.A N.A N.A 9MBps 0x10 0 Actual BRR % Error 1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can be fixed with these data. DocID024597 Rev 1 1185/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) 36.5.5 RM0351 Tolerance of the USART receiver to clock deviation The asynchronous receiver of the USART works correctly only if the total clock system deviation is less than the tolerance of the USART receiver. The causes which contribute to the total deviation are: • DTRA: Deviation due to the transmitter error (which also includes the deviation of the transmitter’s local oscillator) • DQUANT: Error due to the baud rate quantization of the receiver • DREC: Deviation of the receiver’s local oscillator • DTCL: Deviation due to the transmission line (generally due to the transceivers which can introduce an asymmetry between the low-to-high transition timing and the high-tolow transition timing) DTRA + DQUANT + DREC + DTCL + DWU < USART receiver′ s tolerance where DWU is the error due to sampling point deviation when the wakeup from Stop mode is used. when M[1:0] = 01: t WUSTOP DWU = ------------------------11 × Tbit when M[1:0] = 00: t WUSTOP DWU = ------------------------10 × Tbit when M[1:0] = 10: t WUSTOP DWU = -----------------------9 × Tbit tWUSTOP is the wakeup time from Stop mode, which is specified in the product datasheet. The USART receiver can receive data correctly at up to the maximum tolerated deviation specified in Table 191 and Table 192 depending on the following choices: 1186/1680 • 9-, 10- or 11-bit character length defined by the M bits in the USARTx_CR1 register • Oversampling by 8 or 16 defined by the OVER8 bit in the USARTx_CR1 register • Bits BRR[3:0] of USARTx_BRR register are equal to or different from 0000. • Use of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in the USARTx_CR3 register. DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Table 191. Tolerance of the USART receiver when BRR [3:0] = 0000 OVER8 bit = 0 OVER8 bit = 1 M bits ONEBIT=0 ONEBIT=1 ONEBIT=0 ONEBIT=1 00 3.75% 4.375% 2.50% 3.75% 01 3.41% 3.97% 2.27% 3.41% 10 4.16% 4.86% 2.77% 4.16% Table 192. Tolerance of the USART receiver when BRR[3:0] is different from 0000 OVER8 bit = 0 OVER8 bit = 1 M bits ONEBIT=0 ONEBIT=1 ONEBIT=0 ONEBIT=1 00 3.33% 3.88% 2% 3% 01 3.03% 3.53% 1.82% 2.73% 10 3.7% 4.31% 2.22% 3.33% Note: The data specified in Table 191 and Table 192 may slightly differ in the special case when the received frames contain some Idle frames of exactly 10-bit durations when M bits = 00 (11-bit durations when M bits =01 or 9- bit durations when M bits = 10). 36.5.6 Auto baud rate detection The USART is able to detect and automatically set the USARTx_BRR register value based on the reception of one character. Automatic baud rate detection is useful under two circumstances: • The communication speed of the system is not known in advance • The system is using a relatively low accuracy clock source and this mechanism allows the correct baud rate to be obtained without measuring the clock deviation. The clock source frequency must be compatible with the expected communication speed (when oversampling by 16, the baud rate is between fCK/65535 and fCK/16. when oversampling by 8, the baudrate is between fCK/65535 and fCK/8). Before activating the auto baud rate detection, the auto baud rate detection mode must be chosen. There are various modes based on different character patterns. They can be chosen through the ABRMOD[1:0] field in the USARTx_CR2 register. In these auto baud rate modes, the baud rate is measured several times during the synchronization data reception and each measurement is compared to the previous one. These modes are: • Mode 0: Any character starting with a bit at 1. In this case the USART measures the duration of the Start bit (falling edge to rising edge). • Mode 1: Any character starting with a 10xx bit pattern. In this case, the USART measures the duration of the Start and of the 1st data bit. The measurement is done falling edge to falling edge, ensuring better accuracy in the case of slow signal slopes. • Mode 2: A 0x7F character frame (it may be a 0x7F character in LSB first mode or a 0xFE in MSB first mode). In this case, the baudrate is updated first at the end of the DocID024597 Rev 1 1187/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 start bit (BRs), then at the end of bit 6 (based on the measurement done from falling edge to falling edge: BR6). Bit 0 to bit 6 are sampled at BRs while further bits of the character are sampled at BR6. • Mode 3: A 0x55 character frame. In this case, the baudrate is updated first at the end of the start bit (BRs), then at the end of bit 0 (based on the measurement done from falling edge to falling edge: BR0), and finally at the end of bit 6 (BR6). Bit 0 is sampled at BRs, bit 1 to bit 6 are sampled at BR0, and further bits of the character are sampled at BR6. In parallel, another check is performed for each intermediate transition of RX line. An error is generated if the transitions on RX are not sufficiently synchronized with the receiver (the receiver being based on the baud rate calculated on bit 0). Prior to activating auto baud rate detection, the USARTx_BRR register must be initialized by writing a non-zero baud rate value. The automatic baud rate detection is activated by setting the ABREN bit in the USARTx_CR2 register. The USART will then wait for the first character on the RX line. The auto baud rate operation completion is indicated by the setting of the ABRF flag in the USARTx_ISR register. If the line is noisy, the correct baud rate detection cannot be guaranteed. In this case the BRR value may be corrupted and the ABRE error flag will be set. This also happens if the communication speed is not compatible with the automatic baud rate detection range (bit duration not between 16 and 65536 clock periods (oversampling by 16) and not between 8 and 65536 clock periods (oversampling by 8)). The RXNE interrupt will signal the end of the operation. At any later time, the auto baud rate detection may be relaunched by resetting the ABRF flag (by writing a 0). Note: If the USART is disabled (UE=0) during an auto baud rate operation, the BRR value may be corrupted. 36.5.7 Multiprocessor communication In multiprocessor communication, the following bits are to be kept cleared: • LINEN bit in the USART_CR2 register, • HDSEL, IREN and SCEN bits in the USART_CR3 register. It is possible to perform multiprocessor communication with the USART (with several USARTs connected in a network). For instance one of the USARTs can be the master, its TX output connected to the RX inputs of the other USARTs. The others are slaves, their respective TX outputs are logically ANDed together and connected to the RX input of the master. In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant USART service overhead for all non addressed receivers. The non addressed devices may be placed in mute mode by means of the muting function. In order to use the mute mode feature, the MME bit must be set in the USARTx_CR1 register. 1188/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) In mute mode: • None of the reception status bits can be set. • All the receive interrupts are inhibited. • The RWU bit in USARTx_ISR register is set to 1. RWU can be controlled automatically by hardware or by software, through the MMRQ bit in the USARTx_RQR register, under certain conditions. The USART can enter or exit from mute mode using one of two methods, depending on the WAKE bit in the USARTx_CR1 register: • Idle Line detection if the WAKE bit is reset, • Address Mark detection if the WAKE bit is set. Idle line detection (WAKE=0) The USART enters mute mode when the MMRQ bit is written to 1 and the RWU is automatically set. It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but the IDLE bit is not set in the USARTx_ISR register. An example of mute mode behavior using Idle line detection is given in Figure 386. Figure 386. Mute mode using Idle line detection 5;1( 'DWD 'DWD 'DWD 'DWD 5; 0XWHPRGH 5:8 0054ZULWWHQWR ,'/( 5;1( 'DWD 'DWD 1RUPDOPRGH ,GOHIUDPHGHWHFWHG 06Y9 Note: If the MMRQ is set while the IDLE character has already elapsed, mute mode will not be entered (RWU is not set). If the USART is activated while the line is IDLE, the idle state is detected after the duration of one IDLE frame (not only after the reception of one character frame). 4-bit/7-bit address mark detection (WAKE=1) In this mode, bytes are recognized as addresses if their MSB is a ‘1’ otherwise they are considered as data. In an address byte, the address of the targeted receiver is put in the 4 or 7 LSBs. The choice of 7 or 4-bit address detection is done using the ADDM7 bit. This 4bit/7-bit word is compared by the receiver with its own address which is programmed in the ADD bits in the USARTx_CR2 register. Note: In 7-bit and 9-bit data modes, address detection is done on 6-bit and 8-bit addresses (ADD[5:0] and ADD[7:0]) respectively. DocID024597 Rev 1 1189/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 The USART enters mute mode when an address character is received which does not match its programmed address. In this case, the RWU bit is set by hardware. The RXNE flag is not set for this address byte and no interrupt or DMA request is issued when the USART enters mute mode. The USART also enters mute mode when the MMRQ bit is written to 1. The RWU bit is also automatically set in this case. The USART exits from mute mode when an address character is received which matches the programmed address. Then the RWU bit is cleared and subsequent bytes are received normally. The RXNE bit is set for the address character since the RWU bit has been cleared. An example of mute mode behavior using address mark detection is given in Figure 387. Figure 387. Mute mode using address mark detection ,QWKLVH[DPSOHWKHFXUUHQWDGGUHVVRIWKHUHFHLYHULV SURJUDPPHGLQWKH86$57B&5UHJLVWHU 5;1( ,'/( 5; $GGU 'DWD 'DWD 5:8 ,'/( 5;1( $GGU 'DWD 'DWD $GGU 'DWD 0XWHPRGH 1RUPDOPRGH 0DWFKLQJDGGUHVV 0054ZULWWHQWR 5;1(ZDVFOHDUHG 5;1( 0XWHPRGH 1RQPDWFKLQJDGGUHVV 1RQPDWFKLQJDGGUHVV 06Y9 36.5.8 Modbus communication The USART offers basic support for the implementation of Modbus/RTU and Modbus/ASCII protocols. Modbus/RTU is a half duplex, block transfer protocol. The control part of the protocol (address recognition, block integrity control and command interpretation) must be implemented in software. The USART offers basic support for the end of the block detection, without software overhead or other resources. Modbus/RTU In this mode, the end of one block is recognized by a “silence” (idle line) for more than 2 character times. This function is implemented through the programmable timeout function. The timeout function and interrupt must be activated, through the RTOEN bit in the USARTx_CR2 register and the RTOIE in the USARTx_CR1 register. The value corresponding to a timeout of 2 character times (for example 22 x bit duration) must be programmed in the RTO register. when the receive line is idle for this duration, after the last stop bit is received, an interrupt is generated, informing the software that the current block reception is completed. 1190/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Modbus/ASCII In this mode, the end of a block is recognized by a specific (CR/LF) character sequence. The USART manages this mechanism using the character match function. By programming the LF ASCII code in the ADD[7:0] field and by activating the character match interrupt (CMIE=1), the software is informed when a LF has been received and can check the CR/LF in the DMA buffer. 36.5.9 Parity control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the USARTx_CR1 register. Depending on the frame length defined by the M bits, the possible USART frame formats are as listed in Table 193. Table 193. Frame formats M bits PCE bit USART frame(1) 00 0 | SB | 8-bit data | STB | 00 1 | SB | 7-bit data | PB | STB | 01 0 | SB | 9-bit data | STB | 01 1 | SB | 8-bit data | PB | STB | 10 0 | SB | 7-bit data | STB | 10 1 | SB | 6-bit data | PB | STB | 1. Legends: SB: start bit, STB: stop bit, PB: parity bit. In the data register, the PB is always taking the MSB position (9th, 8th or 7th, depending on the M bits value). Even parity The parity bit is calculated to obtain an even number of “1s” inside the frame of the 6, 7 or 8 LSB bits (depending on M bits values) and the parity bit. As an example, if data=00110101, and 4 bits are set, then the parity bit will be 0 if even parity is selected (PS bit in USARTx_CR1 = 0). Odd parity The parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 6, 7 or 8 LSB bits (depending on M bits values) and the parity bit. As an example, if data=00110101 and 4 bits set, then the parity bit will be 1 if odd parity is selected (PS bit in USARTx_CR1 = 1). Parity checking in reception If the parity check fails, the PE flag is set in the USARTx_ISR register and an interrupt is generated if PEIE is set in the USARTx_CR1 register. The PE flag is cleared by software writing 1 to the PECF in the USARTx_ICR register. DocID024597 Rev 1 1191/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Parity generation in transmission If the PCE bit is set in USARTx_CR1, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit (even number of “1s” if even parity is selected (PS=0) or an odd number of “1s” if odd parity is selected (PS=1)). 36.5.10 LIN (local interconnection network) mode This section is relevant only when LIN mode is supported. Please refer to Section 36.4: USART implementation on page 1170. The LIN mode is selected by setting the LINEN bit in the USARTx_CR2 register. In LIN mode, the following bits must be kept cleared: • CLKEN in the USARTx_CR2 register, • STOP[1:0], SCEN, HDSEL and IREN in the USARTx_CR3 register. LIN transmission The procedure explained in Section 36.5.2: Transmitter has to be applied for LIN Master transmission. It must be the same as for normal USART transmission with the following differences: • Clear the M bits to configure 8-bit word length. • Set the LINEN bit to enter LIN mode. In this case, setting the SBKRQ bit sends 13 ‘0’ bits as a break character. Then 2 bits of value ‘1’ are sent to allow the next start detection. LIN reception When LIN mode is enabled, the break detection circuit is activated. The detection is totally independent from the normal USART receiver. A break can be detected whenever it occurs, during Idle state or during a frame. When the receiver is enabled (RE=1 in USARTx_CR1), the circuit looks at the RX input for a start signal. The method for detecting start bits is the same when searching break characters or data. After a start bit has been detected, the circuit samples the next bits exactly like for the data (on the 8th, 9th and 10th samples). If 10 (when the LBDL = 0 in USARTx_CR2) or 11 (when LBDL=1 in USARTx_CR2) consecutive bits are detected as ‘0, and are followed by a delimiter character, the LBDF flag is set in USARTx_ISR. If the LBDIE bit=1, an interrupt is generated. Before validating the break, the delimiter is checked for as it signifies that the RX line has returned to a high level. If a ‘1’ is sampled before the 10 or 11 have occurred, the break detection circuit cancels the current detection and searches for a start bit again. If the LIN mode is disabled (LINEN=0), the receiver continues working as normal USART, without taking into account the break detection. If the LIN mode is enabled (LINEN=1), as soon as a framing error occurs (i.e. stop bit detected at ‘0’, which will be the case for any break frame), the receiver stops until the break detection circuit receives either a ‘1’, if the break word was not complete, or a delimiter character if a break has been detected. The behavior of the break detector state machine and the break flag is shown on the Figure 388: Break detection in LIN mode (11-bit break length - LBDL bit is set) on page 1193. 1192/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Examples of break frames are given on Figure 389: Break detection in LIN mode vs. Framing error detection on page 1194. Figure 388. Break detection in LIN mode (11-bit break length - LBDL bit is set) &DVHEUHDNVLJQDOQRWORQJHQRXJK !EUHDNGLVFDUGHG/%')LVQRWVHW %UHDNIUDPH 5;OLQH &DSWXUHVWUREH %UHDNVWDWH PDFKLQH ,GOH %LW %LW %LW %LW 5HDGVDPSOHV %LW %LW %LW %LW %LW %LW %LW ,GOH &DVHEUHDNVLJQDOMXVWORQJHQRXJK !EUHDNGHWHFWHG/%')LVVHW %UHDNIUDPH 5;OLQH 'HOLPLWHULVLPPHGLDWH &DSWXUHVWUREH %UHDNVWDWH PDFKLQH ,GOH %LW %LW %LW %LW 5HDGVDPSOHV %LW %LW %LW %LW %LW %LW % ,GOH /%') &DVHEUHDNVLJQDOORQJHQRXJK !EUHDNGHWHFWHG/%')LVVHW %UHDNIUDPH 5;OLQH &DSWXUHVWUREH %UHDNVWDWH ,GOH PDFKLQH 5HDGVDPSOHV %LW %LW %LW %LW %LW %LW %LW %LW %LW %LW %LW ZDLWGHOLPLWHU ,GOH /%') 06Y9 DocID024597 Rev 1 1193/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Figure 389. Break detection in LIN mode vs. Framing error detection &DVHEUHDNRFFXUULQJDIWHUDQ,GOH 5;OLQH GDWD ,'/( %5($. GDWDWLPH GDWD [ GDWD KHDGHU GDWDWLPH 5;1()( /%') &DVHEUHDNRFFXUULQJZKLOHGDWDLVEHLQJUHFHLYHG 5;OLQH GDWD GDWD %5($. GDWDWLPH GDWD [ GDWD KHDGHU GDWDWLPH 5;1()( /%') 06Y9 36.5.11 USART synchronous mode The synchronous mode is selected by writing the CLKEN bit in the USARTx_CR2 register to 1. In synchronous mode, the following bits must be kept cleared: • LINEN bit in the USARTx_CR2 register, • SCEN, HDSEL and IREN bits in the USARTx_CR3 register. In this mode, the USART can be used to control bidirectional synchronous serial communications in master mode. The SCLK pin is the output of the USART transmitter clock. No clock pulses are sent to the SCLK pin during start bit and stop bit. Depending on the state of the LBCL bit in the USARTx_CR2 register, clock pulses are, or are not, generated during the last valid data bit (address mark). The CPOL bit in the USARTx_CR2 register is used to select the clock polarity, and the CPHA bit in the USARTx_CR2 register is used to select the phase of the external clock (see Figure 390, Figure 391 and Figure 392). During the Idle state, preamble and send break, the external SCLK clock is not activated. In synchronous mode the USART transmitter works exactly like in asynchronous mode. But as SCLK is synchronized with TX (according to CPOL and CPHA), the data on TX is synchronous. In this mode the USART receiver works in a different manner compared to the asynchronous mode. If RE=1, the data is sampled on SCLK (rising or falling edge, depending on CPOL and CPHA), without any oversampling. A setup and a hold time must be respected (which depends on the baud rate: 1/16 bit duration). Note: 1194/1680 The SCLK pin works in conjunction with the TX pin. Thus, the clock is provided only if the transmitter is enabled (TE=1) and data is being transmitted (the data register USARTx_TDR DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) written). This means that it is not possible to receive synchronous data without transmitting data. The LBCL, CPOL and CPHA bits have to be selected when the USART is disabled (UE=0) to ensure that the clock pulses function correctly. Figure 390. USART example of synchronous transmission 5; 7; 'DWDRXW 'DWDLQ 6\QFKURQRXVGHYLFH HJVODYH63, 86$57 &ORFN 6&/. 06Y9 Figure 391. USART data clock timing diagram (M bits = 00) ,GOHRUSUHFHGLQJ 6WDUW WUDQVPLVVLRQ ,GOHRUQH[W 6WRS WUDQVPLVVLRQ 0ELWV &ORFN &32/ &3+$ &ORFN &32/ &3+$ &ORFN &32/ &3+$ &ORFN &32/ &3+$ 'DWDRQ7; IURPPDVWHU 6WDUW 'DWDRQ5; IURPVODYH /6% 06% 6WRS 06% /6% &DSWXUHVWUREH /%&/ELWFRQWUROVODVWGDWDSXOVH 06Y9 DocID024597 Rev 1 1195/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Figure 392. USART data clock timing diagram (M bits = 01) ,GOHRU SUHFHGLQJ 6WDUW WUDQVPLVVLRQ 6WRS 0ELWV GDWDELWV ,GOHRUQH[W WUDQVPLVVLRQ &ORFN &32/ &3+$ &ORFN &32/ &3+$ &ORFN &32/ &3+$ &ORFN &32/ &3+$ 'DWDRQ7; IURPPDVWHU 6WDUW /6% 'DWDRQ5; IURPVODYH 06% /6% &DSWXUH VWUREH 6WRS 06% /%&/ELWFRQWUROVODVWGDWDSXOVH 06Y9 Figure 393. RX data setup/hold time 6&/. FDSWXUHVWUREHRQ6&/. ULVLQJHGJHLQWKLVH[DPSOH 'DWDRQ5; IURPVODYH 9DOLG'$7$ELW W6(783 W+2/' W6(783 W+2/'ELWWLPH 06Y9 Note: 1196/1680 The function of SCLK is different in Smartcard mode. Refer to Section 36.5.13: Smartcard mode for more details. DocID024597 Rev 1 RM0351 36.5.12 Universal synchronous asynchronous receiver transmitter (USART) Single-wire half-duplex communication Single-wire half-duplex mode is selected by setting the HDSEL bit in the USARTx_CR3 register. In this mode, the following bits must be kept cleared: • LINEN and CLKEN bits in the USARTx_CR2 register, • SCEN and IREN bits in the USARTx_CR3 register. The USART can be configured to follow a single-wire half-duplex protocol where the TX and RX lines are internally connected. The selection between half- and full-duplex communication is made with a control bit HDSEL in USARTx_CR3. As soon as HDSEL is written to 1: • The TX and RX lines are internally connected • The RX pin is no longer used • The TX pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception. It means that the I/O must be configured so that TX is configured as alternate function open-drain with an external pull-up. Apart from this, the communication protocol is similar to normal USART mode. Any conflicts on the line must be managed by software (by the use of a centralized arbiter, for instance). In particular, the transmission is never blocked by hardware and continues as soon as data is written in the data register while the TE bit is set. 36.5.13 Smartcard mode This section is relevant only when Smartcard mode is supported. Please refer to Section 36.4: USART implementation on page 1170. Smartcard mode is selected by setting the SCEN bit in the USARTx_CR3 register. In Smartcard mode, the following bits must be kept cleared: • LINEN bit in the USARTx_CR2 register, • HDSEL and IREN bits in the USARTx_CR3 register. Moreover, the CLKEN bit may be set in order to provide a clock to the smartcard. The smartcard interface is designed to support asynchronous protocol for smartcards as defined in the ISO 7816-3 standard. Both T=0 (character mode) and T=1 (block mode) are supported. The USART should be configured as: • 8 bits plus parity: where word length is set to 8 bits and PCE=1 in the USARTx_CR1 register • 1.5 stop bits: where STOP=11 in the USARTx_CR2 register. In T=0 (character) mode, the parity error is indicated at the end of each character during the guard time period. Figure 394 shows examples of what can be seen on the data line with and without parity error. DocID024597 Rev 1 1197/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Figure 394. ISO 7816-3 asynchronous protocol :LWKRXW3DULW\HUURU 6 *XDUGWLPH S 6WDUWELW :LWK3DULW\HUURU 6 *XDUGWLPH 6WDUWELW S /LQHSXOOHGORZE\UHFHLYHU GXULQJVWRSLQFDVHRISDULW\HUURU 06Y9 When connected to a smartcard, the TX output of the USART drives a bidirectional line that is also driven by the smartcard. The TX pin must be configured as open drain. Smartcard mode implements a single wire half duplex communication protocol. 1198/1680 • Transmission of data from the transmit shift register is guaranteed to be delayed by a minimum of 1/2 baud clock. In normal operation a full transmit shift register starts shifting on the next baud clock edge. In Smartcard mode this transmission is further delayed by a guaranteed 1/2 baud clock. • In transmission, if the smartcard detects a parity error, it signals this condition to the USART by driving the line low (NACK). This NACK signal (pulling transmit line low for 1 baud clock) causes a framing error on the transmitter side (configured with 1.5 stop bits). The USART can handle automatic re-sending of data according to the protocol. The number of retries is programmed in the SCARCNT bit field. If the USART continues receiving the NACK after the programmed number of retries, it stops transmitting and signals the error as a framing error. The TXE bit can be set using the TXFRQ bit in the USARTx_RQR register. • Smartcard auto-retry in transmission: a delay of 2.5 baud periods is inserted between the NACK detection by the USART and the start bit of the repeated character. The TC bit is set immediately at the end of reception of the last repeated character (no guardtime). If the software wants to repeat it again, it must insure the minimum 2 baud periods required by the standard. • If a parity error is detected during reception of a frame programmed with a 1.5 stop bit period, the transmit line is pulled low for a baud clock period after the completion of the receive frame. This is to indicate to the smartcard that the data transmitted to the USART has not been correctly received. A parity error is NACKed by the receiver if the NACK control bit is set, otherwise a NACK is not transmitted (to be used in T=1 mode). If the received character is erroneous, the RXNE/receive DMA request is not activated. According to the protocol specification, the smartcard must resend the same character. If the received character is still erroneous after the maximum number of retries specified in the SCARCNT bit field, the USART stops transmitting the NACK and signals the error as a parity error. • Smartcard auto-retry in reception: the BUSY flag remains set if the USART NACKs the card but the card doesn’t repeat the character. • In transmission, the USART inserts the Guard Time (as programmed in the Guard Time register) between two successive characters. As the Guard Time is measured after the stop bit of the previous character, the GT[7:0] register must be programmed to the DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) desired CGT (Character Guard Time, as defined by the 7816-3 specification) minus 12 (the duration of one character). Note: • The assertion of the TC flag can be delayed by programming the Guard Time register. In normal operation, TC is asserted when the transmit shift register is empty and no further transmit requests are outstanding. In Smartcard mode an empty transmit shift register triggers the Guard Time counter to count up to the programmed value in the Guard Time register. TC is forced low during this time. When the Guard Time counter reaches the programmed value TC is asserted high. • The de-assertion of TC flag is unaffected by Smartcard mode. • If a framing error is detected on the transmitter end (due to a NACK from the receiver), the NACK is not detected as a start bit by the receive block of the transmitter. According to the ISO protocol, the duration of the received NACK can be 1 or 2 baud clock periods. • On the receiver side, if a parity error is detected and a NACK is transmitted the receiver does not detect the NACK as a start bit. A break character is not significant in Smartcard mode. A 0x00 data with a framing error is treated as data and not as a break. No Idle frame is transmitted when toggling the TE bit. The Idle frame (as defined for the other configurations) is not defined by the ISO protocol. Figure 395 details how the NACK signal is sampled by the USART. In this example the USART is transmitting data and is configured with 1.5 stop bits. The receiver part of the USART is enabled in order to check the integrity of the data and the NACK signal. Figure 395. Parity error detection using the 1.5 stop bits %LW 3DULW\ELW ELWWLPH 6WRSELW ELWWLPH 6DPSOLQJDW 6DPSOLQJDW WKWKWK WKWKWK ELWWLPH 6DPSOLQJDW 6DPSOLQJDW WKWKWK WKWKWK 06Y9 The USART can provide a clock to the smartcard through the SCLK output. In Smartcard mode, SCLK is not associated to the communication but is simply derived from the internal peripheral input clock through a 5-bit prescaler. The division ratio is configured in the prescaler register USARTx_. SCLK frequency can be programmed from fCK/2 to fCK/62, where fCK is the peripheral input clock. DocID024597 Rev 1 1199/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Block mode (T=1) In T=1 (block) mode, the parity error transmission is deactivated, by clearing the NACK bit in the UART_CR3 register. When requesting a read from the smartcard, in block mode, the software must enable the receiver Timeout feature by setting the RTOEN bit in the USART_CR2 register and program the RTO bits field in the RTOR register to the BWT (block wait time) - 11 value. If no answer is received from the card before the expiration of this period, the RTOF flag will be set and a timeout interrupt will be generated (if RTOIE bit in the USART_CR1 register is set). If the first character is received before the expiration of the period, it is signaled by the RXNE interrupt. Note: The RXNE interrupt must be enabled even when using the USART in DMA mode to read from the smartcard in block mode. In parallel, the DMA must be enabled only after the first received byte. After the reception of the first character (RXNE interrupt), the RTO bit fields in the RTOR register must be programmed to the CWT (character wait time) - 11 value, in order to allow the automatic check of the maximum wait time between two consecutive characters. This time is expressed in baudtime units. If the smartcard doesn’t send a new character in less than the CWT period after the end of the previous character, the USART signals this to the software through the RTOF flag and interrupt (when RTOIE bit is set). Note: The RTO counter starts counting: - From the end of the stop bit in case STOP = 00. - From the end of the second stop bit in case of STOP = 10. - 1 bit duration after the beginning of the STOP bit in case STOP = 11. As in the smartcard protocol definition, the BWT/CWT values are defined from the beginning (start bit) of the last character. The RTO register must be programmed to BWT -11 or CWT 11, respectively, taking into account the length of the last character itself. A block length counter is used to count all the characters received by the USART. This counter is reset when the USART is transmitting (TXE=0). The length of the block is communicated by the smartcard in the third byte of the block (prologue field). This value must be programmed to the BLEN field in the USARTx_RTOR register. when using DMA mode, before the start of the block, this register field must be programmed to the minimum value (0x0). with this value, an interrupt is generated after the 4th received character. The software must read the LEN field (third byte), its value must be read from the receive buffer. In interrupt driven receive mode, the length of the block may be checked by software or by programming the BLEN value. However, before the start of the block, the maximum value of BLEN (0xFF) may be programmed. The real value will be programmed after the reception of the third character. If the block is using the LRC longitudinal redundancy check (1 epilogue byte), the BLEN=LEN. If the block is using the CRC mechanism (2 epilogue bytes), BLEN=LEN+1 must be programmed. The total block length (including prologue, epilogue and information fields) equals BLEN+4. The end of the block is signaled to the software through the EOBF flag and interrupt (when EOBIE bit is set). In case of an error in the block length, the end of the block is signaled by the RTO interrupt (Character wait Time overflow). Note: 1200/1680 The error checking code (LRC/CRC) must be computed/verified by software. DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Direct and inverse convention The smartcard protocol defines two conventions: direct and inverse. The direct convention is defined as: LSB first, logical bit value of 1 corresponds to a H state of the line and parity is even. In order to use this convention, the following control bits must be programmed: MSBFIRST=0, DATAINV=0 (default values). The inverse convention is defined as: MSB first, logical bit value 1 corresponds to an L state on the signal line and parity is even. In order to use this convention, the following control bits must be programmed: MSBFIRST=1, DATAINV=1. Note: When logical data values are inverted (0=H, 1=L), the parity bit is also inverted in the same way. In order to recognize the card convention, the card sends the initial character, TS, as the first character of the ATR (Answer To Reset) frame. The two possible patterns for the TS are: LHHL LLL LLH and LHHL HHH LLH. • (H) LHHL LLL LLH sets up the inverse convention: state L encodes value 1 and moment 2 conveys the most significant bit (MSB first). when decoded by inverse convention, the conveyed byte is equal to '3F'. • (H) LHHL HHH LLH sets up the direct convention: state H encodes value 1 and moment 2 conveys the least significant bit (LSB first). when decoded by direct convention, the conveyed byte is equal to '3B'. Character parity is correct when there is an even number of bits set to 1 in the nine moments 2 to 10. As the USART does not know which convention is used by the card, it needs to be able to recognize either pattern and act accordingly. The pattern recognition is not done in hardware, but through a software sequence. Moreover, supposing that the USART is configured in direct convention (default) and the card answers with the inverse convention, TS = LHHL LLL LLH => the USART received character will be ‘03’ and the parity will be odd. Therefore, two methods are available for TS pattern recognition: Method 1 The USART is programmed in standard Smartcard mode/direct convention. In this case, the TS pattern reception generates a parity error interrupt and error signal to the card. • The parity error interrupt informs the software that the card didn’t answer correctly in direct convention. Software then reprograms the USART for inverse convention • In response to the error signal, the card retries the same TS character, and it will be correctly received this time, by the reprogrammed USART Alternatively, in answer to the parity error interrupt, the software may decide to reprogram the USART and to also generate a new reset command to the card, then wait again for the TS. Method 2 The USART is programmed in 9-bit/no-parity mode, no bit inversion. In this mode it receives any of the two TS patterns as: (H) LHHL LLL LLH = 0x103 -> inverse convention to be chosen (H) LHHL HHH LLH = 0x13B -> direct convention to be chosen The software checks the received character against these two patterns and, if any of them match, then programs the USART accordingly for the next character reception. DocID024597 Rev 1 1201/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 If none of the two is recognized, a card reset may be generated in order to restart the negotiation. 36.5.14 IrDA SIR ENDEC block This section is relevant only when IrDA mode is supported. Please refer to Section 36.4: USART implementation on page 1170. IrDA mode is selected by setting the IREN bit in the USARTx_CR3 register. In IrDA mode, the following bits must be kept cleared: • LINEN, STOP and CLKEN bits in the USARTx_CR2 register, • SCEN and HDSEL bits in the USARTx_CR3 register. The IrDA SIR physical layer specifies use of a Return to Zero, Inverted (RZI) modulation scheme that represents logic 0 as an infrared light pulse (see Figure 396). The SIR Transmit encoder modulates the Non Return to Zero (NRZ) transmit bit stream output from USART. The output pulse stream is transmitted to an external output driver and infrared LED. USART supports only bit rates up to 115.2 Kbps for the SIR ENDEC. In normal mode the transmitted pulse width is specified as 3/16 of a bit period. The SIR receive decoder demodulates the return-to-zero bit stream from the infrared detector and outputs the received NRZ serial bit stream to the USART. The decoder input is normally high (marking state) in the Idle state. The transmit encoder output has the opposite polarity to the decoder input. A start bit is detected when the decoder input is low. 1202/1680 • IrDA is a half duplex communication protocol. If the Transmitter is busy (when the USART is sending data to the IrDA encoder), any data on the IrDA receive line is ignored by the IrDA decoder and if the Receiver is busy (when the USART is receiving decoded data from the IrDA decoder), data on the TX from the USART to IrDA is not encoded. while receiving data, transmission should be avoided as the data to be transmitted could be corrupted. • A 0 is transmitted as a high pulse and a 1 is transmitted as a 0. The width of the pulse is specified as 3/16th of the selected bit period in normal mode (see Figure 397). • The SIR decoder converts the IrDA compliant receive signal into a bit stream for USART. • The SIR receive logic interprets a high state as a logic one and low pulses as logic zeros. • The transmit encoder output has the opposite polarity to the decoder input. The SIR output is in low state when Idle. • The IrDA specification requires the acceptance of pulses greater than 1.41 µs. The acceptable pulse width is programmable. Glitch detection logic on the receiver end filters out pulses of width less than 2 PSC periods (PSC is the prescaler value programmed in the USARTx_GTPR). Pulses of width less than 1 PSC period are always rejected, but those of width greater than one and less than two periods may be accepted or rejected, those greater than 2 periods will be accepted as a pulse. The IrDA encoder/decoder doesn’t work when PSC=0. • The receiver can communicate with a low-power transmitter. • In IrDA mode, the STOP bits in the USARTx_CR2 register must be configured to “1 stop bit”. DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) IrDA low-power mode Transmitter In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz. Generally, this value is 1.8432 MHz (1.42 MHz < PSC< 2.12 MHz). A low-power mode programmable divisor divides the system clock to achieve this value. Receiver Receiving in low-power mode is similar to receiving in normal mode. For glitch detection the USART should discard pulses of duration shorter than 1 PSC period. A valid low is accepted only if its duration is greater than 2 periods of the IrDA low-power Baud clock (PSC value in the USARTx_GTPR). Note: A pulse of width less than two and greater than one PSC period(s) may or may not be rejected. The receiver set up time should be managed by software. The IrDA physical layer specification specifies a minimum of 10 ms delay between transmission and reception (IrDA is a half duplex protocol). Figure 396. IrDA SIR ENDEC- block diagram 6,5(1 7; 25 86$57 5; 86$57B7; 6,5 7UDQVPLW (QFRGHU ,U'$B287 6,5 5HFHLYH '(FRGHU ,U'$B,1 86$57B5; 06Y9 Figure 397. IrDA data modulation (3/16) -Normal Mode 7; 6WDUW ELW 6WRS ELW ,U'$B287 %LWSHULRG ,U'$B,1 5; 06Y9 DocID024597 Rev 1 1203/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) 36.5.15 RM0351 Continuous communication using DMA The USART is capable of performing continuous communication using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently. Note: Please refer to Section 36.4: USART implementation on page 1170 to determine if the DMA mode is supported. If DMA is not supported, use the USART as explained in Section 36.5.2: Transmitter or Section 36.5.3: Receiver. To perform continuous communication, you can clear the TXE/ RXNE flags In the USARTx_ISR register. Transmission using DMA DMA mode can be enabled for transmission by setting DMAT bit in the USARTx_CR3 register. Data is loaded from a SRAM area configured using the DMA peripheral (refer to Section 11: Direct memory access controller (DMA) on page 300) to the USARTx_TDR register whenever the TXE bit is set. To map a DMA channel for USART transmission, use the following procedure (x denotes the channel number): 1. Write the USARTx_TDR register address in the DMA control register to configure it as the destination of the transfer. The data is moved to this address from memory after each TXE event. 2. Write the memory address in the DMA control register to configure it as the source of the transfer. The data is loaded into the USARTx_TDR register from this memory area after each TXE event. 3. Configure the total number of bytes to be transferred to the DMA control register. 4. Configure the channel priority in the DMA register 5. Configure DMA interrupt generation after half/ full transfer as required by the application. 6. Clear the TC flag in the USARTx_ISR register by setting the TCCF bit in the USARTx_ICR register. 7. Activate the channel in the DMA register. When the number of data transfers programmed in the DMA Controller is reached, the DMA controller generates an interrupt on the DMA channel interrupt vector. In transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag is set in the DMA_ISR register), the TC flag can be monitored to make sure that the USART communication is complete. This is required to avoid corrupting the last transmission before disabling the USART or entering Stop mode. Software must wait until TC=1. The TC flag remains cleared during all data transfers and it is set by hardware at the end of transmission of the last frame. 1204/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Figure 398. Transmission using DMA ,GOHSUHDPEOH )UDPH )UDPH )UDPH 7;OLQH 6HWE\KDUGZDUH FOHDUHGE\'0$UHDG 6HWE\KDUGZDUH FOHDUHGE\'0$UHDG 7;(IODJ 6HWE\KDUGZDUH ,JQRUHGE\WKH'0$EHFDXVH WKHWUDQVIHULVFRPSOHWH '0$UHTXHVW ) 86$57B7'5 ) ) 7&IODJ 6HWE\ KDUGZDUH '0$ZULWHV 86$57B7'5 '0$7&,)IODJ WUDQVIHU FRPSOHWH 6HWE\KDUGZDUH 6RIWZDUH FRQILJXUHV'0$ '0$ZULWHV '0$ZULWHV '0$ZULWHV )LQWR )LQWR )LQWR WRVHQGGDWD EORFNVDQG 86$57B7'5 86$57B7'5 86$57B7'5 HQDEOHV86$57 &OHDUHG E\ VRIWZDUH 7KH'0$ WUDQVIHULV FRPSOHWH 7&,) LQ '0$B,65 6RIWZDUHZDLWVXQWLO7& AIB Reception using DMA DMA mode can be enabled for reception by setting the DMAR bit in USARTx_CR3 register. Data is loaded from the USARTx_RDR register to a SRAM area configured using the DMA peripheral (refer to Section 11: Direct memory access controller (DMA) on page 300) whenever a data byte is received. To map a DMA channel for USART reception, use the following procedure: 1. Write the USARTx_RDR register address in the DMA control register to configure it as the source of the transfer. The data is moved from this address to the memory after each RXNE event. 2. Write the memory address in the DMA control register to configure it as the destination of the transfer. The data is loaded from USARTx_RDR to this memory area after each RXNE event. 3. Configure the total number of bytes to be transferred to the DMA control register. 4. Configure the channel priority in the DMA control register 5. Configure interrupt generation after half/ full transfer as required by the application. 6. Activate the channel in the DMA control register. When the number of data transfers programmed in the DMA Controller is reached, the DMA controller generates an interrupt on the DMA channel interrupt vector. DocID024597 Rev 1 1205/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Figure 399. Reception using DMA )UDPH )UDPH )UDPH 7;OLQH 6HWE\KDUGZDUH FOHDUHGE\'0$UHDG 5;1(IODJ '0$UHTXHVW ) ) 86$57B7'5 ) '0$UHDGV 86$57B7'5 '0$7&,)IODJ WUDQVIHUFRPSOHWH 6RIWZDUHFRQILJXUHVWKH '0$WRUHFHLYHGDWD EORFNVDQGHQDEOHV WKH86$57 &OHDUHG E\ VRIWZDUH 6HWE\KDUGZDUH '0$UHDGV) IURP86$57B7'5 '0$UHDGV) IURP86$57B7'5 7KH'0$WUDQVIHU '0$UHDGV) LVFRPSOHWH IURP86$57B7'5 7&,) LQ '0$B,65 DLE Error flagging and interrupt generation in multibuffer communication In multibuffer communication if any error occurs during the transaction the error flag is asserted after the current byte. An interrupt is generated if the interrupt enable flag is set. For framing error, overrun error and noise flag which are asserted with RXNE in single byte reception, there is a separate error flag interrupt enable bit (EIE bit in the USARTx_CR3 register), which, if set, enables an interrupt after the current byte if any of these errors occur. 36.5.16 RS232 Hardware flow control and RS485 Driver Enable It is possible to control the serial data flow between 2 devices by using the nCTS input and the nRTS output. The Figure 400 shows how to connect 2 devices in this mode: Figure 400. Hardware flow control between 2 USARTs 86$57 86$57 7; 7;FLUFXLW Q&76 5; 5;FLUFXLW Q576 5; Q576 5;FLUFXLW 7; 7;FLUFXLW Q&76 06Y9 RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and CTSE bits respectively to 1 (in the USARTx_CR3 register). 1206/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) RS232 RTS flow control If the RTS flow control is enabled (RTSE=1), then nRTS is asserted (tied low) as long as the USART receiver is ready to receive a new data. When the receive register is full, nRTS is de-asserted, indicating that the transmission is expected to stop at the end of the current frame. Figure 401 shows an example of communication with RTS flow control enabled. Figure 401. RS232 RTS flow control 5; 6WDUW ELW 'DWD 6WRS 6WDUW ,GOH ELW ELW 'DWD 6WRS ELW Q576 5;1( 5;1( 'DWDUHDG 'DWDFDQQRZEHWUDQVPLWWHG 06Y9 RS232 CTS flow control If the CTS flow control is enabled (CTSE=1), then the transmitter checks the nCTS input before transmitting the next frame. If nCTS is asserted (tied low), then the next data is transmitted (assuming that data is to be transmitted, in other words, if TXE=0), else the transmission does not occur. when nCTS is de-asserted during a transmission, the current transmission is completed before the transmitter stops. When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the nCTS input toggles. It indicates when the receiver becomes ready or not ready for communication. An interrupt is generated if the CTSIE bit in the USARTx_CR3 register is set. Figure 402 shows an example of communication with CTS flow control enabled. DocID024597 Rev 1 1207/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Figure 402. RS232 CTS flow control &76 &76 Q&76 7UDQVPLWGDWDUHJLVWHU 7'5 'DWD 7; 'DWD HPSW\ 6WRS 6WDUW ELW ELW HPSW\ 'DWD 'DWD :ULWLQJGDWDLQ7'5 6WRS 6WDUW ,GOH ELW ELW 'DWD 7UDQVPLVVLRQRI'DWDLV GHOD\HGXQWLOQ&76 06Y9 Note: For correct behavior, nCTS must be asserted at least 3 USART clock source periods before the end of the current character. In addition it should be noted that the CTSCF flag may not be set for pulses shorter than 2 x PCLK periods. RS485 Driver Enable The driver enable feature is enabled by setting bit DEM in the USARTx_CR3 control register. This allows the user to activate the external transceiver control, through the DE (Driver Enable) signal. The assertion time is the time between the activation of the DE signal and the beginning of the START bit. It is programmed using the DEAT [4:0] bit fields in the USARTx_CR1 control register. The de-assertion time is the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE signal. It is programmed using the DEDT [4:0] bit fields in the USARTx_CR1 control register. The polarity of the DE signal can be configured using the DEP bit in the USARTx_CR3 control register. In USART, the DEAT and DEDT are expressed in sample time units (1/8 or 1/16 bit duration, depending on the oversampling rate). 36.5.17 Wakeup from Stop mode The USART is able to wake up the MCU from Stop mode when the UESM bit is set and the USART clock is set to HSI16 or LSE (refer to Section Reset and clock control (RCC)). The MCU wakeup from Stop mode can be done using the standard RXNE interrupt. In this case, the RXNEIE bit must be set before entering Stop mode. Alternatively, a specific interrupt may be selected through the WUS bit fields. In order to be able to wake up the MCU from Stop mode, the UESM bit in the USARTx_CR1 control register must be set prior to entering Stop mode. When the wakeup event is detected, the WUF flag is set by hardware and a wakeup interrupt is generated if the WUFIE bit is set. 1208/1680 DocID024597 Rev 1 RM0351 Note: Universal synchronous asynchronous receiver transmitter (USART) Before entering Stop mode, the user must ensure that the USART is not performing a transfer. BUSY flag cannot ensure that Stop mode is never entered during a running reception. The WUF flag is set when a wakeup event is detected, independently of whether the MCU is in Stop or in an active mode. When entering Stop mode just after having initialized and enabled the receiver, the REACK bit must be checked to ensure the USART is actually enabled. When DMA is used for reception, it must be disabled before entering Stop mode and reenabled upon exit from Stop mode. The wakeup from Stop mode feature is not available for all modes. For example it doesn’t work in SPI mode because the SPI operates in master mode only. Using Mute mode with Stop mode If the USART is put into Mute mode before entering Stop mode: 36.6 • Wakeup from Mute mode on idle detection must not be used, because idle detection cannot work in Stop mode. • If the wakeup from Mute mode on address match is used, then the source of wake-up from Stop mode must also be the address match. If the RXNE flag is set when entering the Stop mode, the interface will remain in mute mode upon address match and wake up from Stop. • If the USART is configured to wake up the MCU from Stop mode on START bit detection, the WUF flag is set, but the RXNE flag is not set. USART low-power modes Table 194. Effect of low-power modes on the USART Mode Description Sleep No effect. USART interrupt causes the device to exit Sleep mode. Low-power run No effect. Low-power sleep No effect. USART interrupt causes the device to exit Low-power sleep mode. Stop 1 The USART is able to wake up the MCU from Stop 1 mode when the UESM bit is set and the USART clock is set to HSI16 or LSE. The MCU wakeup from Stop 1 mode can be done using either a standard RXNE or a WUF interrupt. Stop 2 The USART must either be disabled or put in reset state. Standby The USART is powered down and must be reinitialized when the device has exited from Standby mode. Shutdown The USART is powered down and must be reinitialized when the device has exited from Shutdown mode. DocID024597 Rev 1 1209/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) 36.7 RM0351 USART interrupts Table 195. USART interrupt requests Interrupt event Transmit data register empty CTS interrupt Transmission Complete Receive data register not empty (data ready to be read) Event flag Enable Control bit TXE TXEIE CTSIF CTSIE TC TCIE RXNE RXNEIE Overrun error detected ORE Idle line detected IDLE IDLEIE PE PEIE LBDF LBDIE NF or ORE or FE EIE Character match CMF CMIE Receiver timeout error RTOF RTOIE End of Block EOBF EOBIE Parity error LIN break Noise Flag, Overrun error and Framing Error in multibuffer communication. Wakeup from Stop mode WUF (1) WUFIE 1. The wUF interrupt is active only in Stop mode. The USART interrupt events are connected to the same interrupt vector (see Figure 403). • During transmission: Transmission Complete, Transmit data Register empty or Framing error (in Smartcard mode) interrupt. • During reception: Idle Line detection, Overrun error, Receive data register not empty, Parity error, LIN break detection, Noise Flag, Framing Error, Character match, etc. These events generate an interrupt if the corresponding Enable Control Bit is set. 1210/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Figure 403. USART interrupt mapping diagram 7& 7&,( 7;( 7;(,( &76,) &76,( ,'/( ,'/(,( 86$57 LQWHUUXSW 5;1(,( 25( 5;1(,( 5;1( 3( 3(,( /%') /%',( )( 1) 25( (,( &0) &0,( 572) 572,( (2%) (2%,( :8) :8),( 06Y9 DocID024597 Rev 1 1211/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) 36.8 RM0351 USART registers Refer to Section 1.1 on page 61 for a list of abbreviations used in register descriptions. 36.8.1 Control register 1 (USARTx_CR1) Address offset: 0x00 Reset value: 0x0000 31 30 29 28 27 26 Res. Res. Res. M1 EOBIE RTOIE rw rw rw 25 24 23 22 21 20 19 DEAT[4:0] rw rw rw 18 17 16 rw rw DEDT[4:0] rw 15 14 13 12 11 10 9 8 7 6 OVER8 CMIE MME M0 WAKE PCE PS PEIE TXEIE TCIE rw rw rw rw rw rw rw rw rw rw rw rw 5 4 RXNEIE IDLEIE rw rw rw rw 3 2 1 0 TE RE UESM UE rw rw rw rw Bits 31:29 Reserved, must be kept at reset value Bit 28 M1: Word length This bit, with bit 12 (M0), determines the word length. It is set or cleared by software. M[1:0] = 00: 1 Start bit, 8 data bits, n stop bits M[1:0] = 01: 1 Start bit, 9 data bits, n stop bits M[1:0] = 10: 1 Start bit, 7 data bits, n stop bits This bit can only be written when the USART is disabled (UE=0). Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and Autobaudrate (0x7F and 0x55 frames detection) are not supported. Bit 27 EOBIE: End of Block interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A USART interrupt is generated when the EOBF flag is set in the USARTx_ISR register Note: If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 26 RTOIE: Receiver timeout interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An USART interrupt is generated when the RTOF bit is set in the USARTx_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and forced by hardware to ‘0’. Section 36.4: USART implementation on page 1170. Bits 25:21 DEAT[4:0]: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit duration, depending on the oversampling rate). This bit field can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept cleared. Please refer to Section 36.4: USART implementation on page 1170. 1212/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Bits 20:16 DEDT[4:0]: Driver Enable de-assertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit duration, depending on the oversampling rate). If the USARTx_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bit field can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept cleared. Please refer to Section 36.4: USART implementation on page 1170. Bit 15 OVER8: Oversampling mode 0: Oversampling by 16 1: Oversampling by 8 This bit can only be written when the USART is disabled (UE=0). Note: In LIN, IrDA and modes, this bit must be kept cleared. Bit 14 CMIE: Character match interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A USART interrupt is generated when the CMF bit is set in the USARTx_ISR register. Bit 13 MME: Mute mode enable This bit activates the mute mode function of the USART. when set, the USART can switch between the active and mute modes, as defined by the WAKE bit. It is set and cleared by software. 0: Receiver in active mode permanently 1: Receiver can switch between mute mode and active mode. Bit 12 M0: Word length This bit, with bit 28 (M1), determines the word length. It is set or cleared by software. See Bit 28 (M1) description. This bit can only be written when the USART is disabled (UE=0). Bit 11 WAKE: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. 0: Idle line 1: Address mark This bit field can only be written when the USART is disabled (UE=0). Bit 10 PCE: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). 0: Parity control disabled 1: Parity control enabled This bit field can only be written when the USART is disabled (UE=0). Bit 9 PS: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. 0: Even parity 1: Odd parity This bit field can only be written when the USART is disabled (UE=0). DocID024597 Rev 1 1213/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Bit 8 PEIE: PE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A USART interrupt is generated whenever PE=1 in the USARTx_ISR register Bit 7 TXEIE: interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A USART interrupt is generated whenever TXE=1 in the USARTx_ISR register Bit 6 TCIE: Transmission complete interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A USART interrupt is generated whenever TC=1 in the USARTx_ISR register Bit 5 RXNEIE: RXNE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A USART interrupt is generated whenever ORE=1 or RXNE=1 in the USARTx_ISR register Bit 4 IDLEIE: IDLE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A USART interrupt is generated whenever IDLE=1 in the USARTx_ISR register Bit 3 TE: Transmitter enable This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled Note: During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. In order to ensure the required duration, the software can poll the TEACK bit in the USARTx_ISR register. In Smartcard mode, when TE is set there is a 1 bit-time delay before the transmission starts. 1214/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Bit 2 RE: Receiver enable This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit Bit 1 UESM: USART enable in Stop mode When this bit is cleared, the USART is not able to wake up the MCU from Stop mode. When this bit is set, the USART is able to wake up the MCU from Stop mode, provided that the USART clock selection is HSI16 or LSE in the RCC. This bit is set and cleared by software. 0: USART not able to wake up the MCU from Stop mode. 1: USART able to wake up the MCU from Stop mode. When this function is active, the clock source for the USART must be HSI16 or LSE (see Section Reset and clock control (RCC). Note: It is recommended to set the UESM bit just before entering Stop mode and clear it on exit from Stop mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 0 UE: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the USART is kept, but all the status flags, in the USARTx_ISR are set to their default values. This bit is set and cleared by software. 0: USART prescaler and outputs disabled, low-power mode 1: USART enabled Note: In order to go into low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the USARTx_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. 36.8.2 Control register 2 (USARTx_CR2) Address offset: 0x04 Reset value: 0x0000 31 30 29 28 27 ADD[7:4] 26 25 24 ADD[3:0] 23 RTOEN 22 21 ABRMOD[1:0] 20 19 18 17 MSBFI ABREN DATAINV TXINV RST 16 RXINV rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWAP LINEN CLKEN CPOL CPHA LBCL Res. LBDIE LBDL ADDM7 Res. Res. Res. Res. rw rw rw rw rw rw rw rw rw STOP[1:0] rw rw DocID024597 Rev 1 1215/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Bits 31:28 ADD[7:4]: Address of the USART node This bit-field gives the address of the USART node or a character code to be recognized. This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8bit) is compared to the ADD[7:0] value and CMF flag is set on match. This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled (UE=0) Bits 27:24 ADD[3:0]: Address of the USART node This bit-field gives the address of the USART node or a character code to be recognized. This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with address mark detection. This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled (UE=0) Bit 23 RTOEN: Receiver timeout enable This bit is set and cleared by software. 0: Receiver timeout feature disabled. 1: Receiver timeout feature enabled. When this feature is enabled, the RTOF flag in the USARTx_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bits 22:21 ABRMOD[1:0]: Auto baud rate mode These bits are set and cleared by software. 00: Measurement of the start bit is used to detect the baud rate. 01: Falling edge to falling edge measurement. (the received frame must start with a single bit = 1 -> Frame = Start10xxxxxx) 10: 0x7F frame detection. 11: 0x55 frame detection This bit field can only be written when ABREN = 0 or the USART is disabled (UE=0). Note: If DATAINV=1 and/or MSBFIRST=1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 20 ABREN: Auto baud rate enable This bit is set and cleared by software. 0: Auto baud rate detection is disabled. 1: Auto baud rate detection is enabled. Note: If the USART does not support the auto baud rate feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 19 MSBFIRST: Most significant bit first This bit is set and cleared by software. 0: data is transmitted/received with data bit 0 first, following the start bit. 1: data is transmitted/received with the MSB (bit 7/8/9) first, following the start bit. This bit field can only be written when the USART is disabled (UE=0). 1216/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Bit 18 DATAINV: Binary data inversion This bit is set and cleared by software. 0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) 1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. This bit field can only be written when the USART is disabled (UE=0). Bit 17 TXINV: TX pin active level inversion This bit is set and cleared by software. 0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) 1: TX pin signal values are inverted. (VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the TX line. This bit field can only be written when the USART is disabled (UE=0). Bit 16 RXINV: RX pin active level inversion This bit is set and cleared by software. 0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) 1: RX pin signal values are inverted. (VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the RX line. This bit field can only be written when the USART is disabled (UE=0). Bit 15 SWAP: Swap TX/RX pins This bit is set and cleared by software. 0: TX/RX pins are used as defined in standard pinout 1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired connection to another USART. This bit field can only be written when the USART is disabled (UE=0). Bit 14 LINEN: LIN mode enable This bit is set and cleared by software. 0: LIN mode disabled 1: LIN mode enabled The LIN mode enables the capability to send LIN Sync Breaks (13 low bits) using the SBKRQ bit in the USARTx_RQR register, and to detect LIN Sync breaks. This bit field can only be written when the USART is disabled (UE=0). Note: If the USART does not support LIN mode, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bits 13:12 STOP[1:0]: STOP bits These bits are used for programming the stop bits. 00: 1 stop bit 01: Reserved 10: 2 stop bits 11: 1.5 stop bits This bit field can only be written when the USART is disabled (UE=0). Bit 11 CLKEN: Clock enable This bit allows the user to enable the SCLK pin. 0: SCLK pin disabled 1: SCLK pin enabled This bit can only be written when the USART is disabled (UE=0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. DocID024597 Rev 1 1217/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Note: In order to provide correctly the SCLK clock to the Smartcard, the steps below must be respected: - UE = 0 - SCEN = 1 - GTPR configuration - CLKEN= 1 - UE = 1 Bit 10 CPOL: Clock polarity This bit allows the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship 0: Steady low value on SCLK pin outside transmission window 1: Steady high value on SCLK pin outside transmission window This bit can only be written when the USART is disabled (UE=0). Note: If synchronous mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 9 CPHA: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 391 and Figure 392) 0: The first clock transition is the first data capture edge 1: The second clock transition is the first data capture edge This bit can only be written when the USART is disabled (UE=0). Note: If synchronous mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 8 LBCL: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. 0: The clock pulse of the last data bit is not output to the SCLK pin 1: The clock pulse of the last data bit is output to the SCLK pin Caution: The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bits in the USARTx_CR1 register. This bit can only be written when the USART is disabled (UE=0). Note: If synchronous mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 7 Reserved, must be kept at reset value. Bit 6 LBDIE: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). 0: Interrupt is inhibited 1: An interrupt is generated whenever LBDF=1 in the USARTx_ISR register Note: If LIN mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. 1218/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Bit 5 LBDL: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. 0: 10-bit break detection 1: 11-bit break detection This bit can only be written when the USART is disabled (UE=0). Note: If LIN mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 4 ADDM7:7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. 0: 4-bit address detection 1: 7-bit address detection (in 8-bit data mode) This bit can only be written when the USART is disabled (UE=0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. Bits 3:0 Reserved, must be kept at reset value. Note: The 3 bits (CPOL, CPHA, LBCL) should not be written while the transmitter is enabled. 36.8.3 Control register 3 (USARTx_CR3) Address offset: 0x08 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. WUFIE 15 14 21 20 19 WUS 18 17 SCARCNT2:0] 16 Res. rw rw rw rw rw rw 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ONE BIT CTSIE CTSE RTSE DMAT DMAR SCEN NACK HDSEL IRLP IREN EIE rw rw rw rw rw rw v v rw rw rw rw DEP DEM DDRE OVR DIS rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bit 23 Reserved, must be kept at reset value. Bit 22 WUFIE: Wakeup from Stop mode interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An USART interrupt is generated whenever WUF=1 in the USARTx_ISR register Note: WUFIE must be set before entering in Stop mode. The WUF interrupt is active only in Stop mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. DocID024597 Rev 1 1219/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Bits 21:20 WUS[1:0]: Wakeup from Stop mode interrupt flag selection This bit-field specify the event which activates the WUF (wakeup from Stop mode flag). 00: WUF active on address match (as defined by ADD[7:0] and ADDM7) 01:Reserved. 10: WuF active on Start bit detection 11: WUF active on RXNE. This bit field can only be written when the USART is disabled (UE=0). Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Bits 19:17 SCARCNT[2:0]: Smartcard auto-retry count This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE and PE bits set). This bit field must be programmed only when the USART is disabled (UE=0). When the USART is enabled (UE=1), this bit field may only be written to 0x0, in order to stop retransmission. 0x0: retransmission disabled - No automatic retransmission in transmit mode. 0x1 to 0x7: number of automatic retransmission attempts (before signaling error) Note: If Smartcard mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 16 Reserved, must be kept at reset value. Bit 15 DEP: Driver enable polarity selection 0: DE signal is active high. 1: DE signal is active low. This bit can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept cleared. Please refer to Section 36.4: USART implementation on page 1170. Bit 14 DEM: Driver enable mode This bit allows the user to activate the external transceiver control, through the DE signal. 0: DE function is disabled. 1: DE function is enabled. The DE signal is output on the RTS pin. This bit can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept cleared. Section 36.4: USART implementation on page 1170. Bit 13 DDRE: DMA Disable on Reception Error 0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data will be transferred (used for Smartcard mode). 1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE before clearing the error flag. This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error. 1220/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Bit 12 OVRDIS: Overrun Disable This bit is used to disable the receive overrun detection. 0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data. 1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the USARTx_RDR register. This bit can only be written when the USART is disabled (UE=0). Note: This control bit allows checking the communication flow without reading the data. Bit 11 ONEBIT: One sample bit method enable This bit allows the user to select the sample method. When the one sample bit method is selected the noise detection flag (NF) is disabled. 0: Three sample bit method 1: One sample bit method This bit can only be written when the USART is disabled (UE=0). Bit 10 CTSIE: CTS interrupt enable 0: Interrupt is inhibited 1: An interrupt is generated whenever CTSIF=1 in the USARTx_ISR register Note: If the hardware flow control feature is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 9 CTSE: CTS enable 0: CTS hardware flow control disabled 1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is de-asserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is deasserted, the transmission is postponed until nCTS is asserted. This bit can only be written when the USART is disabled (UE=0) Note: If the hardware flow control feature is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 8 RTSE: RTS enable 0: RTS hardware flow control disabled 1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received. This bit can only be written when the USART is disabled (UE=0). Note: If the hardware flow control feature is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 7 DMAT: DMA enable transmitter This bit is set/reset by software 1: DMA mode is enabled for transmission 0: DMA mode is disabled for transmission Bit 6 DMAR: DMA enable receiver This bit is set/reset by software 1: DMA mode is enabled for reception 0: DMA mode is disabled for reception DocID024597 Rev 1 1221/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Bit 5 SCEN: Smartcard mode enable This bit is used for enabling Smartcard mode. 0: Smartcard Mode disabled 1: Smartcard Mode enabled This bit field can only be written when the USART is disabled (UE=0). Note: If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 4 NACK: Smartcard NACK enable 0: NACK transmission in case of parity error is disabled 1: NACK transmission during parity error is enabled This bit field can only be written when the USART is disabled (UE=0). Note: If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 3 HDSEL: Half-duplex selection Selection of Single-wire Half-duplex mode 0: Half duplex mode is not selected 1: Half duplex mode is selected This bit can only be written when the USART is disabled (UE=0). Bit 2 IRLP: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes 0: Normal mode 1: Low-power mode This bit can only be written when the USART is disabled (UE=0). Note: If IrDA mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 1 IREN: IrDA mode enable This bit is set and cleared by software. 0: IrDA disabled 1: IrDA enabled This bit can only be written when the USART is disabled (UE=0). Note: If IrDA mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 0 EIE: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). 0: Interrupt is inhibited 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. 1222/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) 36.8.4 Baud rate register (USARTx_BRR) This register can only be written when the USART is disabled (UE=0). It may be automatically updated by hardware in auto baud rate detection mode. Address offset: 0x0C Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw BRR[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:4 BRR[15:4] BRR[15:4] = USARTDIV[15:4] Bits 3:0 BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared. 36.8.5 Guard time and prescaler register (USARTx_GTPR) Address offset: 0x10 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GT[7:0] PSC[7:0] rw rw DocID024597 Rev 1 1223/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Bits 31:16 Reserved, must be kept at reset value Bits 15:8 GT[7:0]: Guard time value This bit-field is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bit field can only be written when the USART is disabled (UE=0). Note: If Smartcard mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bits 7:0 PSC[7:0]: Prescaler value In IrDA Low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power Baud Rate Used for programming the prescaler for dividing the USART source clock to achieve the lowpower frequency: The source clock is divided by the value given in the register (8 significant bits): 00000000: Reserved - do not program this value 00000001: divides the source clock by 1 00000010: divides the source clock by 2 ... In Smartcard mode: PSC[4:0]: Prescaler value Used for programming the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: 00000: Reserved - do not program this value 00001: divides the source clock by 2 00010: divides the source clock by 4 00011: divides the source clock by 6 ... This bit field can only be written when the USART is disabled (UE=0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bit field is reserved and forced by hardware to ‘0’ when the Smartcard and IrDA modes are not supported. Please refer to Section 36.4: USART implementation on page 1170. 36.8.6 Receiver timeout register (USARTx_RTOR) Address offset: 0x14 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 BLEN[7:0] 20 19 18 17 16 RTO[23:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RTO[15:0] 1224/1680 rw DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Bits 31:24 BLEN[7:0]: Block Length This bit-field gives the Block length in Smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0 -> 0 information characters + LEC BLEN = 1 -> 0 information characters + CRC BLEN = 255 -> 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE=0. This bit-field can be used also in other modes. In this case, the Block length counter is reset when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block. Bits 23:0 RTO[23:0]: Receiver timeout value This bit-field gives the Receiver timeout value in terms of number of bit duration. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In this case, the timeout measurement is done starting from the Start Bit of the last received character. Note: This value must only be programmed once per received character. Note: RTOR can be written on the fly. If the new value is lower than or equal to the counter, the RTOF flag is set. This register is reserved and forced by hardware to “0x00000000” when the Receiver timeout feature is not supported. Please refer to Section 36.4: USART implementation on page 1170. 36.8.7 Request register (USARTx_RQR) Address offset: 0x18 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TXFRQ RXFRQ MMRQ SBKRQ ABRRQ w DocID024597 Rev 1 w w w w 1225/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Bits 31:5 Reserved, must be kept at reset value Bit 4 TXFRQ: Transmit data flush request Writing 1 to this bit sets the TXE flag. This allows to discard the transmit data. This bit must be used only in Smartcard mode, when data has not been sent due to errors (NACK) and the FE flag is active in the USARTx_ISR register. If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 3 RXFRQ: Receive data flush request Writing 1 to this bit clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition. Bit 2 MMRQ: Mute mode request Writing 1 to this bit puts the USART in mute mode and sets the RWU flag. Bit 1 SBKRQ: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: In the case the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. Bit 0 ABRRQ: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USARTx_ISR and request an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. 36.8.8 Interrupt & status register (USARTx_ISR) Address offset: 0x1C Reset value: 0x00C0 31 30 29 28 27 26 25 24 23 Res. Res. Res. Res. Res. Res. Res. Res. Res. 22 r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ABRF ABRE Res. EOBF RTOF CTS CTSIF LBDF TXE TC RXNE IDLE ORE NF FE PE r r r r r r r r r r r r r r r Bits 31:25 Reserved, must be kept at reset value. Bits 24:23 Reserved, must be kept at reset value. 1226/1680 21 REACK TEACK DocID024597 Rev 1 20 19 18 17 16 WUF RWU SBKF CMF BUSY RM0351 Universal synchronous asynchronous receiver transmitter (USART) Bit 22 REACK: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. When the wakeup from Stop mode is supported, the REACK flag can be used to verify that the USART is ready for reception before entering Stop mode. Bit 21 TEACK: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the USARTx_CR1 register, in order to respect the TE=0 minimum period. Bit 20 WUF: Wakeup from Stop mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bit field. It is cleared by software, writing a 1 to the WUCF in the USARTx_ICR register. An interrupt is generated if WUFIE=1 in the USARTx_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. The WUF interrupt is active only in Stop mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Bit 19 RWU: Receiver wakeup from Mute mode This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USARTx_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USARTx_RQR register. 0: Receiver in active mode 1: Receiver in mute mode Bit 18 SBKF: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USARTx_RQR register. It is automatically reset by hardware during the stop bit of break transmission. 0: No break character is transmitted 1: Break character will be transmitted Bit 17 CMF: Character match flag This bit is set by hardware, when the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USARTx_ICR register. An interrupt is generated if CMIE=1in the USARTx_CR1 register. 0: No Character match detected 1: Character Match detected Bit 16 BUSY: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). 0: USART is idle (no reception) 1: Reception on going DocID024597 Rev 1 1227/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Bit 15 ABRF: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE will also be set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USARTx_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and forced by hardware to ‘0’. Bit 14 ABRE: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USARTx_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and forced by hardware to ‘0’. Bit 13 Reserved, must be kept at reset value. Bit 12 EOBF: End of block flag This bit is set by hardware when a complete block has been received (for example T=1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE=1 in the USARTx_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USARTx_ICR register. 0: End of Block not reached 1: End of Block (number of characters) reached Note: If Smartcard mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 11 RTOF: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USARTx_ICR register. An interrupt is generated if RTOIE=1 in the USARTx_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. 0: Timeout value not reached 1: Timeout value reached without any data reception Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF will be set. If the USART does not support the Receiver timeout feature, this bit is reserved and forced by hardware to ‘0’. Bit 10 CTS: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. 0: nCTS line set 1: nCTS line reset Note: If the hardware flow control feature is not supported, this bit is reserved and forced by hardware to ‘0’. 1228/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) Bit 9 CTSIF: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USARTx_ICR register. An interrupt is generated if CTSIE=1 in the USARTx_CR3 register. 0: No change occurred on the nCTS status line 1: A change occurred on the nCTS status line Note: If the hardware flow control feature is not supported, this bit is reserved and forced by hardware to ‘0’. Bit 8 LBDF: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USARTx_ICR. An interrupt is generated if LBDIE = 1 in the USARTx_CR2 register. 0: LIN Break not detected 1: LIN break detected Note: If the USART does not support LIN mode, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 7 TXE: Transmit data register empty This bit is set by hardware when the content of the USARTx_TDR register has been transferred into the shift register. It is cleared by a write to the USARTx_TDR register. The TXE flag can also be cleared by writing 1 to the TXFRQ in the USARTx_RQR register, in order to discard the data (only in smartcard T=0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit =1 in the USARTx_CR1 register. 0: data is not transferred to the shift register 1: data is transferred to the shift register) Note: This bit is used during single buffer transmission. Bit 6 TC: Transmission complete This bit is set by hardware if the transmission of a frame containing data is complete and if TXE is set. An interrupt is generated if TCIE=1 in the USARTx_CR1 register. It is cleared by software, writing 1 to the TCCF in the USARTx_ICR register or by a write to the USARTx_TDR register. An interrupt is generated if TCIE=1 in the USARTx_CR1 register. 0: Transmission is not complete 1: Transmission is complete Note: If TE bit is reset and no transmission is on going, the TC bit will be set immediately. Bit 5 RXNE: Read data register not empty This bit is set by hardware when the content of the RDR shift register has been transferred to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. An interrupt is generated if RXNEIE=1 in the USARTx_CR1 register. 0: data is not received 1: Received data is ready to be read. DocID024597 Rev 1 1229/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Bit 4 IDLE: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USARTx_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USARTx_ICR register. 0: No Idle line is detected 1: Idle line is detected Note: The IDLE bit will not be set again until the RXNE bit has been set (i.e. a new idle line occurs). If mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0), whatever the mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. Bit 3 ORE: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the RDR register while RXNE=1. It is cleared by a software, writing 1 to the ORECF, in the USARTx_ICR register. An interrupt is generated if RXNEIE=1 or EIE = 1 in the USARTx_CR1 register. 0: No overrun error 1: Overrun error is detected Note: When this bit is set, the RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multibuffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the OVRDIS bit is set in the USARTx_CR3 register. Bit 2 NF: START bit Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USARTx_ICR register. 0: No noise is detected 1: Noise is detected Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NF flag is set during multibuffer communication if the EIE bit is set. Note: When the line is noise-free, the NF flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section 36.5.5: Tolerance of the USART receiver to clock deviation on page 1186). Bit 1 FE: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USARTx_ICR register. In Smartcard mode, in transmission, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USARTx_CR1 register. 0: No Framing error is detected 1: Framing error or break character is detected Bit 0 PE: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USARTx_ICR register. An interrupt is generated if PEIE = 1 in the USARTx_CR1 register. 0: No parity error 1: Parity error 1230/1680 DocID024597 Rev 1 RM0351 Universal synchronous asynchronous receiver transmitter (USART) 36.8.9 Interrupt flag clear register (USARTx_ICR) Address offset: 0x20 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WUCF Res. Res. CMCF Res. 15 14 13 12 11 10 9 8 7 6 5 3 2 1 0 Res. Res. Res. Res. TCCF Res. NCF FECF PECF w w w w EOBCF RTOCF w w Res. CTSCF LBDCF w w w w 4 IDLECF ORECF w w Bits 31:21 Reserved, must be kept at reset value. Bit 20 WUCF: Wakeup from Stop mode clear flag Writing 1 to this bit clears the WUF flag in the USARTx_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Bits 19:18 Reserved, must be kept at reset value. Bit 17 CMCF: Character match clear flag Writing 1 to this bit clears the CMF flag in the USARTx_ISR register. Bits 16:13 Reserved, must be kept at reset value. Bit 12 EOBCF: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USARTx_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 11 RTOCF: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USARTx_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 10 Reserved, must be kept at reset value. Bit 9 CTSCF: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USARTx_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 8 LBDCF: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USARTx_ISR register. Note: If LIN mode is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 36.4: USART implementation on page 1170. Bit 7 Reserved, must be kept at reset value. Bit 6 TCCF: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USARTx_ISR register. Bit 5 Reserved, must be kept at reset value. Bit 4 IDLECF: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USARTx_ISR register. DocID024597 Rev 1 1231/1680 1272 Universal synchronous asynchronous receiver transmitter (USART) RM0351 Bit 3 ORECF: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USARTx_ISR register. Bit 2 NCF: Noise detected clear flag Writing 1 to this bit clears the NF flag in the USARTx_ISR register. Bit 1 FECF: Framing error clear flag Writing 1 to this bit clears the FE flag in the USARTx_ISR register. Bit 0 PECF: Parity error clear flag Writing 1 to this bit clears the PE flag in the USARTx_ISR register. 36.8.10 Receive data register (USARTx_RDR) Address offset: 0x24 Reset value: Undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8 7 6 5 4 3 2 1 0 r r r r 15 14 13 12 11 10 9 Res. Res. Res. Res. Res. Res. Res. RDR[8:0] r r r r r Bits 31:9 Reserved, must be kept at reset value. Bits 8:0 RDR[8:0]: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 379). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. 36.8.11 Transmit data register (USARTx_TDR) Address offset: 0x28 Reset value: Undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8 7 6 5 4 3 2 1 0 rw rw rw rw 15 14 13 12 11 10 9 Res. Res. Res. Res. Res. Res. Res. TDR[8:0] rw 1232/1680 rw rw DocID024597 Rev 1 rw rw RM0351 Universal synchronous asynchronous receiver transmitter (USART) Bits 31:9 Reserved, must be kept at reset value. Bits 8:0 TDR[8:0]: Transmit data value Contains the data character to be transmitted. The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 379). When transmitting with the parity enabled (PCE bit set to 1 in the USARTx_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE=1. 36.8.12 USART register map The table below gives the USART register map and reset values. UE Res. EIE UESM Res. IREN TE Res. IRLP RE IDLEIE Res. NACK HDSEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRR[15:0] 0 0 0 Res. Res. ADDM7 TCIE RXNEIE 0 0 0 SCEN 0 LBDL TXEIE Res. 0 LBDIE 0 0 0 DMAT 0 0 0 0 DMAR RTSE PS CTSE 0 0 Res. PEIE LBCL CTSIE 0 0 Res. PCE CPOL CPHA ONEBIT 0 0 Res. M0 0 0 Res. WAKE CLKEN 0 OVRDIS MME 0 DEM CMIE LINEN 0 DDRE DEDT0 OVER8 SWAP 0 DEP DEDT1 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 GT[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USARTx_RQR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x18 DocID024597 Rev 1 RXNE IDLE ORE NF FE PE 0 0 TC 0 0 TXE 0 0 LBDF 0 0 CTS 0 0 CTSIF 0 RTOF ABRE 0 EOBF ABRF 0 Res. BUSY 0 CMF 0 RWU WUF 0 SBKF TEACK Res. Res. Res. Res. Res. Res. Res. REACK Reset value Res. USARTx_ISR 0x1C Res. Reset value SBKRQ 0 ABRRQ 0 MMRQ 0 TXFRQ 0 RXFRQ Reset value Res. RTO[23:0] Res. BLEN[7:0] 0 PSC[7:0] Res. USARTx_RTOR 0 0 Reset value 0x14 0 0 0 Res. USARTx_GTPR 0 0 Reset value 0x10 0 RXINV 0 0 Res. DEDT2 0 0 TXINV DEDT3 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. USARTx_BRR 0x0C Res. Reset value 0 Res. USARTx_CR3 0x08 DATAINV 0 SCARCNT2:0] 0 Res. 0 0 STOP [1:0] Res. 0 0 MSBFIRST DEAT0 DEDT4 0 0 WUS 0 0 Res. 0 0x04 0 ABREN DEAT1 0 ADD[3:0] 0 Res. 0 ADD[7:4] 0 ABRMOD0 DEAT2 ABRMOD1 0 USARTx_CR2 0 Res. Reset value WUFIE DEAT3 RTOEN 0 Res. 0 Res. RTOIE DEAT4 0 Res. 0 Res. M1 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Reset value EOBIE Res. USARTx_CR1 0x00 Res. Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 196. USART register map and reset values 0 0 0 1 1 0 0 0 0 0 0 1233/1680 1272 0x28 USARTx_TDR 1234/1680 Reset value DocID024597 Rev 1 Res. Res. LBDCF 0 0 Reset value Refer to Section 2.2 on page 66 for the register boundary addresses. ORECF NCF FECF 0 0 0 0 RDR[8:0] X X X X X X TDR[8:0] X X X X X X PECF IDLECF 0 Res. TCCF Res. CTSCF Res. RTOCF Res. Res. 0 Res. Res. EOBCF Res. Res. Res. Res. CMCF Res. Res. WUCF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. USARTx_RDR Res. 0x24 Res. USARTx_ICR Res. 0x20 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. Universal synchronous asynchronous receiver transmitter (USART) RM0351 Table 196. USART register map and reset values (continued) 0 X X X X X X RM0351 Low-power universal asynchronous receiver transmitter (LPUART) 37 Low-power universal asynchronous receiver transmitter (LPUART) 37.1 Introduction The low-power universal asynchronous receiver transmitted (LPUART) is an UART which allows bidirectional UART communications with a limited power consumption. Only 32.768 kHz LSE clock is required to allow UART communications up to 9600 baud/s. Higher baud rates can be reached when the LPUART is clocked by clock sources different from the LSE clock. Even when the microcontroller is in Stop mode, the LPUART can wait for an incoming UART frame while having an extremely low energy consumption. The LPUART includes all necessary hardware support to make asynchronous serial communications possible with minimum power consumption. It supports half-duplex single wire communications and modem operations (CTS/RTS). It also supports multiprocessor communications. DMA (direct memory access) can be used for data transmission/reception. DocID024597 Rev 1 1235/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) 37.2 LPUART main features • Full-duplex asynchronous communications • NRZ standard format (mark/space) • Programmable baud rate from 300 baud/s to 9600 baud/s using a 32.768 kHz clock source. Higher baud rates can be achieved by using a higher frequency clock source • Dual clock domain allowing – UART functionality and wakeup from Stop mode – Convenient baud rate programming independent from the PCLK reprogramming • Programmable data word length (7 or 8 or 9 bits) • Programmable data order with MSB-first or LSB-first shifting • Configurable stop bits (1 or 2 stop bits) • Single-wire half-duplex communications • Continuous communications using DMA • Received/transmitted bytes are buffered in reserved SRAM using centralized DMA. • Separate enable bits for transmitter and receiver • Separate signal polarity control for transmission and reception • Swappable Tx/Rx pin configuration • Hardware flow control for modem and RS-485 transceiver • Transfer detection flags: • • – Receive buffer full – Transmit buffer empty – Busy and end of transmission flags Parity control: – Transmits parity bit – Checks parity of received data byte Four error detection flags: – Overrun error – Noise detection – Frame error – Parity error • Fourteen interrupt sources with flags • Multiprocessor communications The LPUART enters mute mode if the address does not match. • 37.3 Wakeup from mute mode (by idle line detection or address mark detection) LPUART implementation The STM32L4x6 devices embed one LPUART. Refer to Section 36.4: USART implementation for LPUART supported features. 1236/1680 RM0351 DocID024597 Rev 1 RM0351 37.4 Low-power universal asynchronous receiver transmitter (LPUART) LPUART functional description Any LPUART bidirectional communication requires a minimum of two pins: Receive data In (RX) and Transmit data Out (TX): • RX: Receive data Input. This is the serial data input. • TX: Transmit data Output. When the transmitter is disabled, the output pin returns to its I/O port configuration. When the transmitter is enabled and nothing is to be transmitted, the TX pin is at high level. In single-wire mode, this I/O is used to transmit and receive the data. Through these pins, serial data is transmitted and received in normal LPUART mode as frames comprising: • An Idle Line prior to transmission or reception • A start bit • A data word (7 or 8 or 9 bits) least significant bit first • 1, 2 stop bits indicating that the frame is complete • The LPUART interface uses a baud rate generator • A status register (LPUART_ISR) • Receive and transmit data registers (LPUART_RDR, LPUART_TDR) • A baud rate register (LPUART_BRR) Refer to Section 37.7: LPUART registers for the definitions of each bit. The following pins are required in RS232 Hardware flow control mode: • nCTS: Clear To Send blocks the data transmission at the end of the current transfer when high • nRTS: Request to send indicates that the LPUART is ready to receive data (when low). The following pin is required in RS485 Hardware control mode: • Note: DE: Driver Enable activates the transmission mode of the external transceiver. DE and nRTS share the same pin. DocID024597 Rev 1 1237/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) RM0351 Figure 404. LPUART Block diagram 3:'$7$ 35'$7$ :ULWH 5HDG &38RU'0$ '5 GDWDUHJLVWHU &38RU'0$ 7UDQVPLWGDWDUHJLVWHU 7'5 5HFHLYHGDWDUHJLVWHU 5'5 7; 7UDQVPLWVKLIWUHJLVWHU 5; 5HFHLYHVKLIWUHJLVWHU /38$57B*735UHJLVWHU *7 36& /38$57[B&5UHJLVWHU /38$57[B&5UHJLVWHU Q567 '( Q&76 6&./FRQWURO /38$57[B&5UHJLVWHU /38$57[B&5UHJLVWHU +DUGZDUH IORZ FRQWUROOHU 7UDQVPLW FRQWURO 6&/. :DNHXS XQLW 5HFHLYHU FRQWURO /38$57[B&5UHJLVWHU 5HFHLYHU FORFN /38$57[B,65UHJLVWHU /38$57 LQWHUUXSW FRQWURO /38$57[B%55UHJLVWHU d 7UDQVPLWWHU FORFN /38$57',9 7UDQVPLWWHU UDWHFRQWUROOHU %55>@ I3&/. Z 5HFHLYHUUDWH FRQWUROOHU &RQYHQWLRQDOEDXGUDWHJHQHUDWRU /38$57',9 %%5>@ 37.4.1 06Y9 LPUART character description Word length may be selected as being either 7 or 8 or 9 bits by programming the M[1:0] bits in the LPUART_CR1 register (see Figure 405). • 7-bit character length: M[1:0] = 10 • 8-bit character length: M[1:0] = 00 • 9-bit character length: M[1:0] = 01 In default configuration, the signal (TX or RX) is in low state during the start bit. It is in high state during the stop bit. 1238/1680 DocID024597 Rev 1 RM0351 Low-power universal asynchronous receiver transmitter (LPUART) These values can be inverted, separately for each signal, through polarity configuration control. An Idle character is interpreted as an entire frame of “1”s. (The number of “1” ‘s will include the number of stop bits). A Break character is interpreted on receiving “0”s for a frame period. At the end of the break frame, the transmitter inserts 2 stop bits. Transmission and reception are driven by a common baud rate generator, the clock for each is generated when the enable bit is set respectively for the transmitter and receiver. The details of each block is given below. DocID024597 Rev 1 1239/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) RM0351 Figure 405. Word length programming ELWZRUGOHQJWK 0 6WRSELW 3RVVLEOH 3DULW\ ELW 'DWDIUDPH 6WDUW ELW %LW %LW %LW %LW %LW %LW %LW %LW %LW 6WRS ELW 1H[W 6WDUW ELW &ORFN 6WDUW ELW ,GOHIUDPH 6WRS ELW 6WRS ELW 6WRS ELW 6WRS ELW 6WDUW ELW 6WRS ELW 6WDUW ELW %UHDNIUDPH 6WDUW ELW ELWZRUGOHQJWK 0 6WRSELW 3RVVLEOH 3DULW\ ELW 'DWDIUDPH 6WDUW ELW %LW %LW %LW %LW %LW %LW %LW %LW 6WRS ELW 1H[W 6WDUW ELW &ORFN 6WDUW ELW ,GOHIUDPH %UHDNIUDPH ELWZRUGOHQJWK 0 6WRSELW 3RVVLEOH 3DULW\ ELW 'DWDIUDPH 6WDUW ELW %LW %LW %LW %LW %LW %LW %LW 6WRS ELW 1H[W 6WDUW ELW &ORFN ,GOHIUDPH %UHDNIUDPH 6WDUW ELW 6WRS ELW /%&/ELWFRQWUROVODVWGDWDFORFNSXOVH 069 1240/1680 DocID024597 Rev 1 RM0351 37.4.2 Low-power universal asynchronous receiver transmitter (LPUART) Transmitter The transmitter can send data words of either 7 or 8 or 9 bits depending on the M bits status. The Transmit Enable bit (TE) must be set in order to activate the transmitter function. The data in the transmit shift register is output on the TX pin. Character transmission During an LPUART transmission, data shifts out least significant bit first (default configuration) on the TX pin. In this mode, the LPUART_TDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 379). Every character is preceded by a start bit which is a logic level low for one bit period. The character is terminated by a configurable number of stop bits. The following stop bits are supported by LPUART: 1 and 2 stop bits. Note: The TE bit must be set before writing the data to be transmitted to the LPUART_TDR. The TE bit should not be reset during transmission of data. Resetting the TE bit during the transmission will corrupt the data on the TX pin as the baud rate counters will get frozen. The current data being transmitted will be lost. An idle frame will be sent after the TE bit is enabled. Configurable stop bits The number of stop bits to be transmitted with every character can be programmed in Control register 2, bits 13,12. • 1 stop bit: This is the default value of number of stop bits. • 2 stop bits: This will be supported by normal LPUART, single-wire and modem modes. An idle frame transmission will include the stop bits. A break transmission will be 10 low bits (when M[1:0] = 00) or 11 low bits (when M[1:0] = 01) or 9 low bits (when M[1:0] = 10) followed by 2 stop bits. It is not possible to transmit long breaks (break of length greater than 9/10/11 low bits). Figure 406. Configurable stop bits ELW:RUGOHQJWK 0>@ ELWLVUHVHW D 6WRSELW 3RVVLEOH SDULW\ELW 'DWDIUDPH 6WDUWELW %LW %LW %LW %LW %LW %LW %LW %LW 6WRS ELW 1H[W 1H[WGDWDIUDPH VWDUW ELW &/2&. /%&/ELWFRQWUROVODVWGDWDFORFNSXOVH E 6WRSELWV 3RVVLEOH SDULW\ELW 'DWDIUDPH 6WDUWELW %LW %LW %LW %LW %LW %LW DocID024597 Rev 1 %LW %LW 6WRS ELWV 1H[W VWDUW ELW 1H[WGDWDIUDPH 069 1241/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) RM0351 Character transmission procedure 1. Program the M bits in LPUART_CR1 to define the word length. 2. Select the desired baud rate using the LPUART_BRR register. 3. Program the number of stop bits in LPUART_CR2. 4. Enable the LPUART by writing the UE bit in LPUART_CR1 register to 1. 5. Select DMA enable (DMAT) in LPUART_CR3 if multibuffer Communication is to take place. Configure the DMA register as explained in multibuffer communication. 6. Set the TE bit in LPUART_CR1 to send an idle frame as first transmission. 7. Write the data to send in the LPUART_TDR register (this clears the TXE bit). Repeat this for each data to be transmitted in case of single buffer. 8. After writing the last data into the LPUART_TDR register, wait until TC=1. This indicates that the transmission of the last frame is complete. This is required for instance when the LPUART is disabled or enters the Halt mode to avoid corrupting the last transmission. Single byte communication Clearing the TXE bit is always performed by a write to the transmit data register. The TXE bit is set by hardware and it indicates: • The data has been moved from the LPUART_TDR register to the shift register and the data transmission has started. • The LPUART_TDR register is empty. • The next data can be written in the LPUART_TDR register without overwriting the previous data. This flag generates an interrupt if the TXEIE bit is set. When a transmission is taking place, a write instruction to the LPUART_TDR register stores the data in the TDR register; next, the data is copied in the shift register at the end of the currently ongoing transmission. When no transmission is taking place, a write instruction to the LPUART_TDR register places the data in the shift register, the data transmission starts, and the TXE bit is set. If a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An interrupt is generated if the TCIE bit is set in the LPUART_CR1 register. After writing the last data in the LPUART_TDR register, it is mandatory to wait for TC=1 before disabling the LPUART or causing the microcontroller to enter the low-power mode (see Figure 382: TC/TXE behavior when transmitting). 1242/1680 DocID024597 Rev 1 RM0351 Low-power universal asynchronous receiver transmitter (LPUART) Figure 407. TC/TXE behavior when transmitting )UDPH )UDPH )UDPH ,GOHSUHDPEOH 7;OLQH 7;(IODJ /38$57B'5 6HWE\KDUGZDUH FOHDUHGE\VRIWZDUH 6HWE\KDUGZDUH FOHDUHGE\VRIWZDUH ) ) ) 6HWE\KDUGZDUH 6HWE\KDUGZDUH 7&IODJ 6RIWZDUH HQDEOHVWKH /38$57 6RIWZDUHZDLWVXQWLO7;( DQGZULWHV)LQWR'5 6RIWZDUHZDLWVXQWLO7;( DQGZULWHV)LQWR'5 7&LVQRWVHW EHFDXVH7;( 6RIWZDUHZDLWVXQWLO 7;( DQGZULWHV )LQWR'5 7&LVQRWVHW EHFDXVH7;( 7&LVVHW EHFDXVH7;( 6RIWZDUHZDLWVXQWLO7& 06Y9 Break characters Setting the SBKRQ bit transmits a break character. The break frame length depends on the M bits (see Figure 405). If a ‘1’ is written to the SBKRQ bit, a break character is sent on the TX line after completing the current character transmission. The SBKF bit is set by the write operation and it is reset by hardware when the break character is completed (during the stop bits after the break character). The LPUART inserts a logic 1 signal (STOP) for the duration of 2 bits at the end of the break frame to guarantee the recognition of the start bit of the next frame. In the case the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. Idle characters Setting the TE bit drives the LPUART to send an idle frame before the first data frame. 37.4.3 Receiver The LPUART can receive data words of either 7 or 8 or 9 bits depending on the M bits in the LPUART_CR1 register. Start bit detection In LPUART, for START bit detection, a falling edge should be detected first on the Rx line, then a sample is taken in the middle of the start bit to confirm that it is still ‘0’. If the start sample is at ‘1’, then the noise error flag (NF) is set, then the START bit is discarded and the receiver waits for a new START bit. Else, the receiver continues to sample all incoming bits normally. DocID024597 Rev 1 1243/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) RM0351 Character reception During an LPUART reception, data shifts in least significant bit first (default configuration) through the RX pin. In this mode, the LPUART_RDR register consists of a buffer (RDR) between the internal bus and the received shift register. Character reception procedure 1. Program the M bits in LPUART_CR1 to define the word length. 2. Select the desired baud rate using the baud rate register LPUART_BRR 3. Program the number of stop bits in LPUART_CR2. 4. Enable the LPUART by writing the UE bit in LPUART_CR1 register to 1. 5. Select DMA enable (DMAR) in LPUART_CR3 if multibuffer communication is to take place. Configure the DMA register as explained in multibuffer communication. 6. Set the RE bit LPUART_CR1. This enables the receiver which begins searching for a start bit. When a character is received • The RXNE bit is set. It indicates that the content of the shift register is transferred to the RDR. In other words, data has been received and can be read (as well as its associated error flags). • An interrupt is generated if the RXNEIE bit is set. • The error flags can be set if a frame error, noise or an overrun error has been detected during reception. PE flag can also be set with RXNE. • In multibuffer, RXNE is set after every byte received and is cleared by the DMA read of the Receive data Register. • In single buffer mode, clearing the RXNE bit is performed by a software read to the LPUART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. The RXNE bit must be cleared before the end of the reception of the next character to avoid an overrun error. Break character When a break character is received, the LPUART handles it as a framing error. Idle character When an idle frame is detected, there is the same procedure as for a received data character plus an interrupt if the IDLEIE bit is set. 1244/1680 DocID024597 Rev 1 RM0351 Low-power universal asynchronous receiver transmitter (LPUART) Overrun error An overrun error occurs when a character is received when RXNE has not been reset. Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared. The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set when the next data is received or the previous DMA request has not been serviced. When an overrun error occurs: Note: • The ORE bit is set. • The RDR content will not be lost. The previous data is available when a read to LPUART_RDR is performed. • The shift register will be overwritten. After that point, any data received during overrun is lost. • An interrupt is generated if either the RXNEIE bit is set or EIE bit is set. • The ORE bit is reset by setting the ORECF bit in the ICR register. The ORE bit, when set, indicates that at least 1 data has been lost. There are two possibilities: - if RXNE=1, then the last valid data is stored in the receive register RDR and can be read, - if RXNE=0, then it means that the last valid data has already been read and thus there is nothing to be read in the RDR. This case can occur when the last valid data is read in the RDR at the same time as the new (and lost) data is received. Selecting the clock source The choice of the clock source is done through the Reset and Clock Control system (RCC). The clock source must be chosen before enabling the LPUART (by setting the UE bit). The choice of the clock source must be done according to two criteria: • Possible use of the LPUART in low-power mode • Communication speed. The clock source frequency is fCK. When the dual clock domain and the wakeup from Stop mode features are supported, the clock source can be one of the following sources: fPCLK (default), fLSE, fHSI or fSYS. Otherwise, the LPUART clock source is fPCLK . Choosing fLSE, fHSI as clock source may allow the LPUART to receive data while the MCU is in low-power mode. Depending on the received data and wakeup mode selection, the LPUART wakes up the MCU, when needed, in order to transfer the received data by software reading the LPUART_RDR register or by DMA. For the other clock sources, the system must be active in order to allow LPUART communication. The communication speed range (specially the maximum communication speed) is also determined by the clock source. The receiver samples each incoming baud as close as possible to the middle of the baudperiod. Only a single sample is taken of each of the incoming bauds. Note: There is no noise detection for data. DocID024597 Rev 1 1245/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) RM0351 Framing error A framing error is detected when: The stop bit is not recognized on reception at the expected time, following either a desynchronization or excessive noise. When the framing error is detected: • The FE bit is set by hardware • The invalid data is transferred from the Shift register to the LPUART_RDR register. • No interrupt is generated in case of single byte communication. However this bit rises at the same time as the RXNE bit which itself generates an interrupt. In case of multibuffer communication an interrupt will be issued if the EIE bit is set in the LPUART_CR3 register. The FE bit is reset by writing 1 to the FECF in the LPUART_ICR register. Configurable stop bits during reception The number of stop bits to be received can be configured through the control bits of Control Register 2 - it can be either 1 or 2 in normal mode. 37.4.4 • 1 stop bit: Sampling for 1 stop Bit is done on the 8th, 9th and 10th samples. • 2 stop bits: Sampling for the 2 stop bits is done in the middle of the second stop bit. The RXNE and FE flags are set just after this sample i.e. during the second stop bit. The first stop bit is not checked for framing error. Baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as programmed in the LPUART_BRR register. The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as programmed in the LPUART_BRR register. 256 × f CK Tx/Rx baud = -----------------------------------LPUARTDIV LPUARTDIV is coded on the LPUART_BRR register. Note: The baud counters are updated to the new value in the baud registers after a write operation to LPUART_BRR. Hence the baud rate register value should not be changed during communication. It is forbidden to write values less than 0x300 in the LPUART_BRR register. fck must be in the range [3 x baudrate, 4096 x baudrate] 1246/1680 DocID024597 Rev 1 RM0351 Low-power universal asynchronous receiver transmitter (LPUART) Table 197. Error calculation for programmed baudrates at fck = 32,768 KHz fCK = 32,768 KHz Baud rate S.No Desired Actual Value programmed in the baud rate register % Error = (Calculated - Desired) B.rate / Desired B.rate 1 300 Bps 300 Bps 0x6D3A 0 2 600 Bps 600 Bps 0x369D 0 3 1200 Bps 1200.087 Bps 0x1B4E 0.007 4 2400 Bps 2400.17 Bps 0xDA7 0.007 5 4800 Bps 4801.72 Bps 0x6D3 0.035 6 9600 Bps 9608.94 Bps 0x369 0.093 37.4.5 Multiprocessor communication It is possible to perform multiprocessor communication with the LPUART (with several LPUARTs connected in a network). For instance one of the LPUARTs can be the master, its TX output connected to the RX inputs of the other LPUARTs. The others are slaves, their respective TX outputs are logically ANDed together and connected to the RX input of the master. In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant LPUART service overhead for all non addressed receivers. The non addressed devices may be placed in mute mode by means of the muting function. In order to use the mute mode feature, the MME bit must be set in the LPUART_CR1 register. In mute mode: • None of the reception status bits can be set. • All the receive interrupts are inhibited. • The RWU bit in LPUART_ISR register is set to 1. RWU can be controlled automatically by hardware or by software, through the MMRQ bit in the LPUART_RQR register, under certain conditions. The LPUART can enter or exit from mute mode using one of two methods, depending on the WAKE bit in the LPUART_CR1 register: • Idle Line detection if the WAKE bit is reset, • Address Mark detection if the WAKE bit is set. Idle line detection (WAKE=0) The LPUART enters mute mode when the MMRQ bit is written to 1 and the RWU is automatically set. It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but the IDLE bit is not set in the LPUART_ISR register. An example of mute mode behavior using Idle line detection is given in Figure 386. DocID024597 Rev 1 1247/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) RM0351 Figure 408. Mute mode using Idle line detection 5;1( 'DWD 'DWD 'DWD 'DWD 5; 0XWHPRGH 5:8 0054ZULWWHQWR ,'/( 5;1( 'DWD 'DWD 1RUPDOPRGH ,GOHIUDPHGHWHFWHG 06Y9 Note: If the MMRQ is set while the IDLE character has already elapsed, mute mode will not be entered (RWU is not set). If the LPUART is activated while the line is IDLE, the idle state is detected after the duration of one IDLE frame (not only after the reception of one character frame). 4-bit/7-bit address mark detection (WAKE=1) In this mode, bytes are recognized as addresses if their MSB is a ‘1’ otherwise they are considered as data. In an address byte, the address of the targeted receiver is put in the 4 or 7 LSBs. The choice of 7 or 4 bit address detection is done using the ADDM7 bit. This 4bit/7-bit word is compared by the receiver with its own address which is programmed in the ADD bits in the LPUART_CR2 register. Note: In 7-bit and 9-bit data modes, address detection is done on 6-bit and 8-bit addresses (ADD[5:0] and ADD[7:0]) respectively. The LPUART enters mute mode when an address character is received which does not match its programmed address. In this case, the RWU bit is set by hardware. The RXNE flag is not set for this address byte and no interrupt or DMA request is issued when the LPUART enters mute mode. The LPUART also enters mute mode when the MMRQ bit is written to 1. The RWU bit is also automatically set in this case. The LPUART exits from mute mode when an address character is received which matches the programmed address. Then the RWU bit is cleared and subsequent bytes are received normally. The RXNE bit is set for the address character since the RWU bit has been cleared. An example of mute mode behavior using address mark detection is given in Figure 387. 1248/1680 DocID024597 Rev 1 RM0351 Low-power universal asynchronous receiver transmitter (LPUART) Figure 409. Mute mode using address mark detection ,QWKLVH[DPSOHWKHFXUUHQWDGGUHVVRIWKHUHFHLYHULV SURJUDPPHGLQWKH/38$57B&5UHJLVWHU 5;1( ,'/( 5; $GGU 'DWD 'DWD 5:8 ,'/( 5;1( $GGU 'DWD 'DWD $GGU 'DWD 0XWHPRGH 1RUPDOPRGH 0DWFKLQJDGGUHVV 0054ZULWWHQWR 5;1(ZDVFOHDUHG 5;1( 0XWHPRGH 1RQPDWFKLQJDGGUHVV 1RQPDWFKLQJDGGUHVV 06Y9 37.4.6 Parity control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the LPUART_CR1 register. Depending on the frame length defined by the M bits, the possible LPUART frame formats are as listed in Table 193. Table 198. Frame formats M bits PCE bit LPUART frame(1) 00 0 | SB | 8-bit data | STB | 00 1 | SB | 7-bit data | PB | STB | 01 0 | SB | 9-bit data | STB | 01 1 | SB | 8-bit data | PB | STB | 10 0 | SB | 7-bit data | STB | 10 1 | SB | 6-bit data | PB | STB | 1. Legends: SB: start bit, STB: stop bit, PB: parity bit. 2. In the data register, the PB is always taking the MSB position (9th, 8th or 7th, depending on the M bits value). Even parity The parity bit is calculated to obtain an even number of “1s” inside the frame which is made of the 6, 7 or 8 LSB bits (depending on M bits values) and the parity bit. As an example, if data=00110101, and 4 bits are set, then the parity bit will be 0 if even parity is selected (PS bit in LPUART_CR1 = 0). Odd parity The parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 6, 7 or 8 LSB bits (depending on M bits values) and the parity bit. As an example, if data=00110101 and 4 bits set, then the parity bit will be 1 if odd parity is selected (PS bit in LPUART_CR1 = 1). DocID024597 Rev 1 1249/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) RM0351 Parity checking in reception If the parity check fails, the PE flag is set in the LPUART_ISR register and an interrupt is generated if PEIE is set in the LPUART_CR1 register. The PE flag is cleared by software writing 1 to the PECF in the LPUART_ICR register. Parity generation in transmission If the PCE bit is set in LPUARTx_CR1, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit (even number of “1s” if even parity is selected (PS=0) or an odd number of “1s” if odd parity is selected (PS=1)). 37.4.7 Single-wire half-duplex communication Single-wire half-duplex mode is selected by setting the HDSEL bit in the LPUART_CR3 register. In this mode, the following bits must be kept cleared: • LINEN and CLKEN bits in the LPUART_CR2 register, • SCEN and IREN bits in the LPUART_CR3 register. The LPUART can be configured to follow a single-wire half-duplex protocol where the TX and RX lines are internally connected. The selection between half- and full-duplex communication is made with a control bit HDSEL in LPUART_CR3. As soon as HDSEL is written to 1: • The TX and RX lines are internally connected • The RX pin is no longer used • The TX pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception. It means that the I/O must be configured so that TX is configured as alternate function open-drain with an external pull-up. Apart from this, the communication protocol is similar to normal LPUART mode. Any conflicts on the line must be managed by software (by the use of a centralized arbiter, for instance). In particular, the transmission is never blocked by hardware and continues as soon as data is written in the data register while the TE bit is set. Note: In LPUART, in the case of 1-stop bit configuration, the RXNE flag is set in the middle of the stop bit. 37.4.8 Continuous communication using DMA The LPUART is capable of performing continuous communication using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently. Note: Use the LPUART as explained in Section 37.4.3. To perform continuous communication, you can clear the TXE/ RXNE flags In the LPUART_ISR register. Transmission using DMA DMA mode can be enabled for transmission by setting DMAT bit in the LPUART_CR3 register. Data is loaded from a SRAM area configured using the DMA peripheral (refer to Section 11: Direct memory access controller (DMA) on page 300) to the LPUART_TDR register whenever the TXE bit is set. To map a DMA channel for LPUART transmission, use the following procedure (x denotes the channel number): 1250/1680 DocID024597 Rev 1 RM0351 Low-power universal asynchronous receiver transmitter (LPUART) 1. Write the LPUART_TDR register address in the DMA control register to configure it as the destination of the transfer. The data is moved to this address from memory after each TXE event. 2. Write the memory address in the DMA control register to configure it as the source of the transfer. The data is loaded into the LPUART_TDR register from this memory area after each TXE event. 3. Configure the total number of bytes to be transferred to the DMA control register. 4. Configure the channel priority in the DMA register 5. Configure DMA interrupt generation after half/ full transfer as required by the application. 6. Clear the TC flag in the LPUART_ISR register by setting the TCCF bit in the LPUART_ICR register. 7. Activate the channel in the DMA register. When the number of data transfers programmed in the DMA Controller is reached, the DMA controller generates an interrupt on the DMA channel interrupt vector. In transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag is set in the DMA_ISR register), the TC flag can be monitored to make sure that the LPUART communication is complete. This is required to avoid corrupting the last transmission before disabling the LPUART or entering Stop mode. Software must wait until TC=1. The TC flag remains cleared during all data transfers and it is set by hardware at the end of transmission of the last frame. Figure 410. Transmission using DMA ,GOHSUHDPEOH )UDPH )UDPH )UDPH 7;OLQH 6HWE\KDUGZDUHFOHDUHGE\ '0$UHDG 6HWE\KDUGZDUHFOHDUHG E\'0$UHDG 7;(IODJ 6HWE\KDUGZDUH ,JQRUHGE\WKH'0$EHFDXVHWKHWUDQVIHU LVFRPSOHWH '0$UHTXHVW D /38$57B7'5 ) ) ) 7&IODJ 6HWE\KDUGZDUH '0$ZULWHV /38$57B7'5 &OHDUHGE\VRIWZDUH '0$7&,)IODJ WUDQVIHUFRPSOHWH 6RIWZDUH FRQILJXUHV '0$WRVHQG GDWDEORFNV DQGHQDEOHV /38$57 6HWE\KDUGZDUH '0$ZULWHV) '0$ZULWHV) '0$ZULWHV) LQWR LQWR LQWR /38$57B7'5 /38$57B7'5 /38$57B7'5 7KH'0$ WUDQVIHULV FRPSOHWH 7&,) LQ '0$B,65 6RIWZDUHZDLWVXQWLO7& 06Y9 DocID024597 Rev 1 1251/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) RM0351 Reception using DMA DMA mode can be enabled for reception by setting the DMAR bit in LPUART_CR3 register. Data is loaded from the LPUART_RDR register to a SRAM area configured using the DMA peripheral (refer Section 11: Direct memory access controller (DMA) on page 300) whenever a data byte is received. To map a DMA channel for LPUART reception, use the following procedure: 1. Write the LPUART_RDR register address in the DMA control register to configure it as the source of the transfer. The data is moved from this address to the memory after each RXNE event. 2. Write the memory address in the DMA control register to configure it as the destination of the transfer. The data is loaded from LPUART_RDR to this memory area after each RXNE event. 3. Configure the total number of bytes to be transferred to the DMA control register. 4. Configure the channel priority in the DMA control register 5. Configure interrupt generation after half/ full transfer as required by the application. 6. Activate the channel in the DMA control register. When the number of data transfers programmed in the DMA Controller is reached, the DMA controller generates an interrupt on the DMA channel interrupt vector. Figure 411. Reception using DMA )UDPH )UDPH )UDPH 7;OLQH 6HWE\KDUGZDUHFOHDUHGE\ '0$UHDG 5;1(IODJ '0$UHTXHVW ) ) /38$57B7'5 ) '0$UHDGV /38$57B7'5 '0$7&,)IODJ WUDQVIHUFRPSOHWH 6RIWZDUHFRQILJXUHV WKH'0$WRUHFHLYH GDWDEORFNVDQGHQDEOHV WKH/38$57 6HWE\KDUGZDUH '0$UHDGV )IURP /38$57B7'5 '0$UHDGV) )URP /38$57B7'5 '0$UHDGV) IURP /38$57B7'5 &OHDUHGE\ VRIWZDUH 7KH'0$ WUDQVIHULV FRPSOHWH 7&,) LQ '0$B,65 06Y9 Error flagging and interrupt generation in multibuffer communication In multibuffer communication if any error occurs during the transaction the error flag is asserted after the current byte. An interrupt is generated if the interrupt enable flag is set. For framing error, overrun error and noise flag which are asserted with RXNE in single byte reception, there is a separate error flag interrupt enable bit (EIE bit in the LPUART_CR3 register), which, if set, enables an interrupt after the current byte if any of these errors occur. 1252/1680 DocID024597 Rev 1 RM0351 37.4.9 Low-power universal asynchronous receiver transmitter (LPUART) RS232 Hardware flow control and RS485 Driver Enable It is possible to control the serial data flow between 2 devices by using the nCTS input and the nRTS output. The Figure 400 shows how to connect 2 devices in this mode: Figure 412. Hardware flow control between 2 LPUARTs /38$57 /38$57 7; 7;FLUFXLW 5; Q&76 Q576 5; 5;FLUFXLW 5;FLUFXLW 7; 7;FLUFXLW Q576 Q&76 06Y9 RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and CTSE bits respectively to 1 (in the LPUART_CR3 register). RS232 RTS flow control If the RTS flow control is enabled (RTSE=1), then nRTS is asserted (tied low) as long as the LPUART receiver is ready to receive a new data. when the receive register is full, nRTS is de-asserted, indicating that the transmission is expected to stop at the end of the current frame. Figure 401 shows an example of communication with RTS flow control enabled. Figure 413. RS232 RTS flow control 5; 6WDUW ELW 'DWD 6WRS 6WDUW ,GOH ELW ELW 'DWD 6WRS ELW Q576 5;1( 5;1( 'DWDUHDG 'DWDFDQQRZEHWUDQVPLWWHG 06Y9 RS232 CTS flow control If the CTS flow control is enabled (CTSE=1), then the transmitter checks the nCTS input before transmitting the next frame. If nCTS is asserted (tied low), then the next data is transmitted (assuming that data is to be transmitted, in other words, if TXE=0), else the transmission does not occur. When nCTS is de-asserted during a transmission, the current transmission is completed before the transmitter stops. DocID024597 Rev 1 1253/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) RM0351 When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the nCTS input toggles. It indicates when the receiver becomes ready or not ready for communication. An interrupt is generated if the CTSIE bit in the LPUART_CR3 register is set. Figure 402 shows an example of communication with CTS flow control enabled. Figure 414. RS232 CTS flow control &76 &76 Q&76 7UDQVPLWGDWDUHJLVWHU 7'5 'DWD 7; 'DWD HPSW\ 6WRS 6WDUW ELW ELW HPSW\ 'DWD 'DWD :ULWLQJGDWDLQ7'5 6WRS 6WDUW ,GOH ELW ELW 'DWD 7UDQVPLVVLRQRI'DWDLV GHOD\HGXQWLOQ&76 06Y9 Note: For correct behavior, nCTS must be asserted at least 3 LPUART clock source periods before the end of the current character. In addition it should be noted that the CTSCF flag may not be set for pulses shorter than 2 x PCLK periods. RS485 Driver Enable The driver enable feature is enabled by setting bit DEM in the LPUART_CR3 control register. This allows the user to activate the external transceiver control, through the DE (Driver Enable) signal. The assertion time is the time between the activation of the DE signal and the beginning of the START bit. It is programmed using the DEAT [4:0] bit fields in the LPUART_CR1 control register. The de-assertion time is the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE signal. It is programmed using the DEDT [4:0] bit fields in the LPUART_CR1 control register. The polarity of the DE signal can be configured using the DEP bit in the LPUART_CR3 control register. In LPUART, the DEAT and DEDT are expressed in USART clock source (fCK) cycles: • • The Driver enable assertion time = – (1 + (DEAT x P)) x fCK , if P <> 0 – (1 + DEAT) x fCK , if P = 0 The Driver enable de-assertion time = – (1 + (DEDT x P)) x fCK , if P <> 0 – (1 + DEDT) x fCK , if P = 0 With P = BRR[14:11] 1254/1680 DocID024597 Rev 1 RM0351 37.4.10 Low-power universal asynchronous receiver transmitter (LPUART) Wakeup from Stop mode The LPUART is able to wake up the MCU from Stop mode when the UESM bit is set and the LPUART clock is set to HSI16 or LSE (refer to the Reset and clock control (RCC) section. The MCU wakeup from Stop mode can be done using the standard RXNE interrupt. In this case, the RXNEIE bit must be set before entering Stop mode. Alternatively, a specific interrupt may be selected through the WUS bit fields. In order to be able to wake up the MCU from Stop mode, the UESM bit in the LPUART_CR1 control register must be set prior to entering Stop mode. When the wakeup event is detected, the WUF flag is set by hardware and a wakeup interrupt is generated if the WUFIE bit is set. Note: Before entering Stop mode, the user must ensure that the LPUART is not performing a transfer. BUSY flag cannot ensure that Stop mode is never entered during a running reception. The WUF flag is set when a wakeup event is detected, independently of whether the MCU is in Stop or in an active mode. When entering Stop mode just after having initialized and enabled the receiver, the REACK bit must be checked to ensure the LPUART is actually enabled. When DMA is used for reception, it must be disabled before entering Stop mode and reenabled upon exit from Stop mode. The wakeup from Stop mode feature is not available for all modes. For example it doesn’t work in SPI mode because the SPI operates in master mode only. Using Mute mode with Stop mode If the LPUART is put into Mute mode before entering Stop mode: 37.5 • Wakeup from Mute mode on idle detection must not be used, because idle detection cannot work in Stop mode. • If the wakeup from Mute mode on address match is used, then the source of wake-up from Stop mode must also be the address match. If the RXNE flag is set when entering the Stop mode, the interface will remain in mute mode upon address match and wake up from Stop. • If the LPUART is configured to wake up the MCU from Stop mode on START bit detection, the WUF flag is set, but the RXNE flag is not set. LPUART low-power mode Table 199. Effect of low-power modes on the LPUART Mode Description Sleep No effect Low-power run No effect. Low-power sleep No effect. USART interrupt causes the device to exit Low-power sleep mode. DocID024597 Rev 1 1255/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) RM0351 Table 199. Effect of low-power modes on the LPUART (continued) Mode 37.6 Description Stop 1 and Stop 2 The LPUART is able to wake up the MCU from Stop 1 and 2 modes when the UESM bit is set and the LPUART clock is set to HSI16 or LSE. The MCU wakeup from Stop 1 and 2 mode can be done using either the standard RXNE or the WUF interrupt. Standby The LPUART is powered down and must be reinitialized when the device has exited from Standby mode. Shutdown The LPUART is powered down and must be reinitialized when the device has exited from Shutdown mode. LPUART interrupts Table 200. LPUART interrupt requests Interrupt event Transmit data register empty CTS interrupt Transmission Complete Receive data register not empty (data ready to be read) Event flag Enable Control bit TXE TXEIE CTSIF CTSIE TC TCIE RXNE RXNEIE Overrun error detected ORE Idle line detected IDLE IDLEIE PE PEIE NF or ORE or FE EIE CMF CMIE WUF(1) WUFIE Parity error Noise Flag, Overrun error and Framing Error in multibuffer communication. Character match Wakeup from Stop mode 1. The wUF interrupt is active only in Stop mode. The LPUART interrupt events are connected to the same interrupt vector (see Figure 403). • During transmission: Transmission Complete, Clear to Send, Transmit data Register empty or Framing error interrupt. • During reception: Idle Line detection, Overrun error, Receive data register not empty, Parity error, Noise Flag, Framing Error, Character match, etc. These events generate an interrupt if the corresponding Enable Control Bit is set. 1256/1680 DocID024597 Rev 1 RM0351 Low-power universal asynchronous receiver transmitter (LPUART) Figure 415. LPUART interrupt mapping diagram 7& 7&,( 7;( 7;(,( &76,) &76,( ,'/( ,'/(,( /38$57 LQWHUUXSW 5;1(,( 25( 5;1(,( 5;1( 3( 3(,( /%') /%',( )( 1) 25( &0) &0,( (,( :8) :8),( 069 DocID024597 Rev 1 1257/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) 37.7 RM0351 LPUART registers Refer to Section 1.1 on page 61 for a list of abbreviations used in register descriptions. 37.7.1 Control register 1 (LPUART_CR1) Address offset: 0x00 Reset value: 0x0000 31 30 29 28 27 26 Res. Res. Res. M1 Res. Res. rw 25 24 23 22 21 20 19 DEAT[4:0] rw rw rw 18 17 16 rw rw DEDT[4:0] rw 15 14 13 12 11 10 9 8 7 6 Res. CMIE MME M0 WAKE PCE PS PEIE TXEIE TCIE rw rw rw rw rw rw rw rw rw rw rw 5 4 RXNEIE IDLEIE rw rw rw rw 3 2 1 0 TE RE UESM UE rw rw rw rw Bits 31:29 Reserved, must be kept at reset value Bit 28 M1: Word length This bit, with bit 12 (M0) determines the word length. It is set or cleared by software. M[1:0] = 00: 1 Start bit, 8 data bits, n stop bits M[1:0] = 01: 1 Start bit, 9 data bits, n stop bits M[1:0] = 10: 1 Start bit, 7 data bits, n stop bits This bit can only be written when the LPUART is disabled (UE=0). Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and Autobaudrate (0x7F and 0x55 frames detection) are not supported. Bit 27 Reserved, must be kept at reset value Bit 26 Reserved, must be kept at reset value Bits 25:21 DEAT[4:0]: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in UCLK (USART clock) clock cycles. For more details, refer to RS485 Driver Enable paragraph. This bit field can only be written when the LPUART is disabled (UE=0). Bits 20:16 DEDT[4:0]: Driver Enable de-assertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in UCLK (USART clock) clock cycles. For more details, refer to RS485 Driver Enable paragraph. If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bit field can only be written when the LPUART is disabled (UE=0). Bit 15 Reserved, must be kept at reset value Bit 14 CMIE: Character match interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register. 1258/1680 DocID024597 Rev 1 RM0351 Low-power universal asynchronous receiver transmitter (LPUART) Bit 13 MME: Mute mode enable This bit activates the mute mode function of the LPUART. When set, the LPUART can switch between the active and mute modes, as defined by the WAKE bit. It is set and cleared by software. 0: Receiver in active mode permanently 1: Receiver can switch between mute mode and active mode. Bit 12 M0: Word length This bit, with bit 28 (M1) determines the word length. It is set or cleared by software. See Bit 28 (M1) description. This bit can only be written when the LPUART is disabled (UE=0). Bit 11 WAKE: Receiver wakeup method This bit determines the LPUART wakeup method from Mute mode. It is set or cleared by software. 0: Idle line 1: Address mark This bit field can only be written when the LPUART is disabled (UE=0). Bit 10 PCE: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). 0: Parity control disabled 1: Parity control enabled This bit field can only be written when the LPUART is disabled (UE=0). Bit 9 PS: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. 0: Even parity 1: Odd parity This bit field can only be written when the LPUART is disabled (UE=0). Bit 8 PEIE: PE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register Bit 7 TXEIE: interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An LPUART interrupt is generated whenever TXE=1 in the LPUART_ISR register Bit 6 TCIE: Transmission complete interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register Bit 5 RXNEIE: RXNE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An LPUART interrupt is generated whenever ORE=1 or RXNE=1 in the LPUART_ISR register DocID024597 Rev 1 1259/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) RM0351 Bit 4 IDLEIE: IDLE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register Bit 3 TE: Transmitter enable This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled Note: During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble (idle line) after the current word. In order to generate an idle character, the TE must not be immediately written to 1. In order to ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register. When TE is set there is a 1 bit-time delay before the transmission starts. Bit 2 RE: Receiver enable This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit Bit 1 UESM: LPUART enable in Stop mode When this bit is cleared, the LPUART is not able to wake up the MCU from Stop mode. When this bit is set, the LPUART is able to wake up the MCU from Stop mode, provided that the LPUART clock selection is HSI or LSE in the RCC. This bit is set and cleared by software. 0: LPUART not able to wake up the MCU from Stop mode. 1: LPUART able to wake up the MCU from Stop mode. When this function is active, the clock source for the LPUART must be HSI or LSE (see Section Reset and clock control (RCC)). Note: It is recommended to set the UESM bit just before entering Stop mode and clear it on exit from Stop mode. Bit 0 UE: LPUART enable When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. 0: LPUART prescaler and outputs disabled, low-power mode 1: LPUART enabled Note: In order to go into low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. 1260/1680 DocID024597 Rev 1 RM0351 Low-power universal asynchronous receiver transmitter (LPUART) 37.7.2 Control register 2 (LPUART_CR2) Address offset: 0x04 Reset value: 0x0000 31 30 29 28 27 ADD[7:4] 26 25 24 ADD[3:0] 23 22 21 20 Res. Res. Res. Res. 19 18 17 MSBFI DATAINV TXINV RST 16 RXINV rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWAP Res. Res. Res. Res. Res. Res. Res. Res. ADDM7 Res. Res. Res. Res. rw STOP[1:0] rw rw rw Bits 31:28 ADD[7:4]: Address of the LPUART node This bit-field gives the address of the LPUART node or a character code to be recognized. This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. It may also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in Modbus protocol). In this case, the whole received character (8bit) is compared to the ADD[7:0] value and CMF flag is set on match. This bit field can only be written when reception is disabled (RE = 0) or the LPUART is disabled (UE=0) Bits 27:24 ADD[3:0]: Address of the LPUART node This bit-field gives the address of the LPUART node or a character code to be recognized. This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with address mark detection. This bit field can only be written when reception is disabled (RE = 0) or the LPUART is disabled (UE=0) Bits 23:20 Reserved, must be kept at reset value Bit 19 MSBFIRST: Most significant bit first This bit is set and cleared by software. 0: data is transmitted/received with data bit 0 first, following the start bit. 1: data is transmitted/received with the MSB (bit 7/8/9) first, following the start bit. This bit field can only be written when the LPUART is disabled (UE=0). Bit 18 DATAINV: Binary data inversion This bit is set and cleared by software. 0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) 1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. This bit field can only be written when the LPUART is disabled (UE=0). Bit 17 TXINV: TX pin active level inversion This bit is set and cleared by software. 0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) 1: TX pin signal values are inverted. (VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the TX line. This bit field can only be written when the LPUART is disabled (UE=0). DocID024597 Rev 1 1261/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) RM0351 Bit 16 RXINV: RX pin active level inversion This bit is set and cleared by software. 0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) 1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). This allows the use of an external inverter on the RX line. This bit field can only be written when the LPUART is disabled (UE=0). Bit 15 SWAP: Swap TX/RX pins This bit is set and cleared by software. 0: TX/RX pins are used as defined in standard pinout 1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired connection to another UART. This bit field can only be written when the LPUART is disabled (UE=0). Bit 14 Reserved, must be kept at reset value Bits 13:12 STOP[1:0]: STOP bits These bits are used for programming the stop bits. 00: 1 stop bit 01: Reserved. 10: 2 stop bits 11: Reserved This bit field can only be written when the LPUART is disabled (UE=0). Bits 11:5 Reserved, must be kept at reset value Bit 4 ADDM7:7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. 0: 4-bit address detection 1: 7-bit address detection (in 8-bit data mode) This bit can only be written when the LPUART is disabled (UE=0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. Bits 3:0 Reserved, must be kept at reset value. 1262/1680 DocID024597 Rev 1 RM0351 Low-power universal asynchronous receiver transmitter (LPUART) 37.7.3 Control register 3 (LPUART_CR3) Address offset: 0x08 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. WUFIE 21 20 19 18 17 16 Res. Res. Res. Res. rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEP DEM DDRE OVR DIS Res. CTSIE CTSE RTSE DMAT DMAR Res. Res. HD SEL Res. Res. EIE rw rw rw rw rw rw rw rw rw WUS[2:0] rw rw Bits 31:23 Reserved, must be kept at reset value. Bit 22 WUFIE: Wakeup from Stop mode interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An LPUART interrupt is generated whenever WUF=1 in the LPUART_ISR register Note: WUFIE must be set before entering in Stop mode. The WUF interrupt is active only in Stop mode. If the LPUART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Bits 21:20 WUS[1:0]: Wakeup from Stop mode interrupt flag selection This bit-field specify the event which activates the WUF (wakeup from Stop mode flag). 00: WUF active on address match (as defined by ADD[7:0] and ADDM7) 01:Reserved. 10: WUF active on Start bit detection 11: WUF active on RXNE. This bit field can only be written when the LPUART is disabled (UE=0). Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Bits 19:16 Reserved, must be kept at reset value. Bit 15 DEP: Driver enable polarity selection 0: DE signal is active high. 1: DE signal is active low. This bit can only be written when the LPUART is disabled (UE=0). Bit 14 DEM: Driver enable mode This bit allows the user to activate the external transceiver control, through the DE signal. 0: DE function is disabled. 1: DE function is enabled. The DE signal is output on the RTS pin. This bit can only be written when the LPUART is disabled (UE=0). DocID024597 Rev 1 1263/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) RM0351 Bit 13 DDRE: DMA Disable on Reception Error 0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data will be transferred. 1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE before clearing the error flag. This bit can only be written when the LPUART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error. Bit 12 OVRDIS: Overrun Disable This bit is used to disable the receive overrun detection. 0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data. 1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the LPUART_RDR register. This bit can only be written when the LPUART is disabled (UE=0). Note: This control bit allows checking the communication flow without reading the data. Bit 11 Reserved, must be kept at reset value. Bit 10 CTSIE: CTS interrupt enable 0: Interrupt is inhibited 1: An interrupt is generated whenever CTSIF=1 in the LPUART_ISR register Bit 9 CTSE: CTS enable 0: CTS hardware flow control disabled 1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is de-asserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is deasserted, the transmission is postponed until nCTS is asserted. This bit can only be written when the LPUART is disabled (UE=0) Bit 8 RTSE: RTS enable 0: RTS hardware flow control disabled 1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received. This bit can only be written when the LPUART is disabled (UE=0). Bit 7 DMAT: DMA enable transmitter This bit is set/reset by software 1: DMA mode is enabled for transmission 0: DMA mode is disabled for transmission Bit 6 DMAR: DMA enable receiver This bit is set/reset by software 1: DMA mode is enabled for reception 0: DMA mode is disabled for reception Bits 5:4 Reserved, must be kept at reset value. 1264/1680 DocID024597 Rev 1 RM0351 Low-power universal asynchronous receiver transmitter (LPUART) Bit 3 HDSEL: Half-duplex selection Selection of Single-wire Half-duplex mode 0: Half duplex mode is not selected 1: Half duplex mode is selected This bit can only be written when the LPUART is disabled (UE=0). Bits 2:1 Reserved, must be kept at reset value. Bit 0 EIE: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUART_ISR register). 0: Interrupt is inhibited 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUART_ISR register. 37.7.4 Baud rate register (LPUART_BRR) This register can only be written when the LPUART is disabled (UE=0). Address offset: 0x0C Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 19 18 rw rw 17 16 BRR[19:16] rw rw 6 5 4 3 2 1 0 rw rw rw rw rw rw rw 7 BRR[15:0] rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value. Bits 19:0 BRR[19:0] Note: It is forbidden to write values less than 0x300 in the LPUART_BRR register. Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, a care should be taken when generating high baudrates using high fck values. fck must be in the range [3 x baudrate,.4096 x baudrate]. 37.7.5 Request register (LPUART_RQR) Address offset: 0x18 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 3 2 1 15 14 13 12 11 10 9 8 7 6 5 4 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RXFRQ MMRQ SBKRQ w DocID024597 Rev 1 w 0 Res. w 1265/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) RM0351 Bits 31:4 Reserved, must be kept at reset value Bit 3 RXFRQ: Receive data flush request Writing 1 to this bit clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition. Bit 2 MMRQ: Mute mode request Writing 1 to this bit puts the LPUART in mute mode and resets the RWU flag. Bit 1 SBKRQ: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: In the case the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit. Bit 0 Reserved, must be kept at reset value 37.7.6 Interrupt & status register (LPUART_ISR) Address offset: 0x1C Reset value: 0x00C0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TE ACK WUF RWU SBKF CMF BUSY Res. Res. Res. Res. Res. Res. Res. Res. Res. RE ACK r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. CTS CTSIF Res. TXE TC RXNE IDLE ORE NF FE PE r r r r r r r r r r Bits 31:23 Reserved, must be kept at reset value. Bit 22 REACK: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the LPUART. It can be used to verify that the LPUART is ready for reception before entering Stop mode. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Bit 21 TEACK: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the LPUART. It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 in the LPUART_CR1 register, in order to respect the TE=0 minimum period. Bit 20 WUF: Wakeup from Stop mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bit field. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. An interrupt is generated if WUFIE=1 in the LPUART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. The WUF interrupt is active only in Stop mode. If the LPUART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. 1266/1680 DocID024597 Rev 1 RM0351 Low-power universal asynchronous receiver transmitter (LPUART) Bit 19 RWU: Receiver wakeup from Mute mode This bit indicates if the LPUART is in mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the LPUART_RQR register. 0: Receiver in active mode 1: Receiver in mute mode Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Bit 18 SBKF: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. 0: No break character is transmitted 1: Break character will be transmitted Bit 17 CMF: Character match flag This bit is set by hardware, when the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the LPUART_ICR register. An interrupt is generated if CMIE=1in the LPUART_CR1 register. 0: No Character match detected 1: Character Match detected Bit 16 BUSY: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). 0: LPUART is idle (no reception) 1: Reception on going Bits 15:11 Reserved, must be kept at reset value. Bit 10 CTS: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. 0: nCTS line set 1: nCTS line reset Note: If the hardware flow control feature is not supported, this bit is reserved and forced by hardware to ‘0’. Bit 9 CTSIF: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the LPUART_ICR register. An interrupt is generated if CTSIE=1 in the LPUART_CR3 register. 0: No change occurred on the nCTS status line 1: A change occurred on the nCTS status line Note: If the hardware flow control feature is not supported, this bit is reserved and forced by hardware to ‘0’. Bit 8 Reserved, must be kept at reset value. DocID024597 Rev 1 1267/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) RM0351 Bit 7 TXE: Transmit data register empty This bit is set by hardware when the content of the LPUART_TDR register has been transferred into the shift register. It is cleared by a write to the LPUART_TDR register. An interrupt is generated if the TXEIE bit =1 in the LPUART_CR1 register. 0: data is not transferred to the shift register 1: data is transferred to the shift register) Note: This bit is used during single buffer transmission. Bit 6 TC: Transmission complete This bit is set by hardware if the transmission of a frame containing data is complete and if TXE is set. An interrupt is generated if TCIE=1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the TCCF in the LPUART_ICR register or by a write to the LPUART_TDR register. An interrupt is generated if TCIE=1 in the LPUART_CR1 register. 0: Transmission is not complete 1: Transmission is complete Note: If TE bit is reset and no transmission is on going, the TC bit will be set immediately. Bit 5 RXNE: Read data register not empty This bit is set by hardware when the content of the RDR shift register has been transferred to the LPUART_RDR register. It is cleared by a read to the LPUART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. An interrupt is generated if RXNEIE=1 in the LPUART_CR1 register. 0: data is not received 1: Received data is ready to be read. Bit 4 IDLE: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the LPUART_ICR register. 0: No Idle line is detected 1: Idle line is detected Note: The IDLE bit will not be set again until the RXNE bit has been set (i.e. a new idle line occurs). If mute mode is enabled (MME=1), IDLE is set if the LPUART is not mute (RWU=0), whatever the mute mode selected by the WAKE bit. If RWU=1, IDLE is not set. Bit 3 ORE: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the RDR register while RXNE=1. It is cleared by a software, writing 1 to the ORECF, in the LPUART_ICR register. An interrupt is generated if RXNEIE=1 or EIE = 1 in the LPUART_CR1 register. 0: No overrun error 1: Overrun error is detected Note: When this bit is set, the RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multibuffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the OVRDIS bit is set in the LPUART_CR3 register. 1268/1680 DocID024597 Rev 1 RM0351 Low-power universal asynchronous receiver transmitter (LPUART) Bit 2 NF: START bit Noise detection flag This bit is set by hardware when noise is detected on the START bit of a received frame. It is cleared by software, writing 1 to the NFCF bit in the LPUART_ICR register. 0: No noise is detected 1: Noise is detected Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NF flag is set during multibuffer communication if the EIE bit is set. Bit 1 FE: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register. An interrupt is generated if EIE = 1 in the LPUART_CR1 register. 0: No Framing error is detected 1: Framing error or break character is detected Bit 0 PE: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the LPUART_ICR register. An interrupt is generated if PEIE = 1 in the LPUART_CR1 register. 0: No parity error 1: Parity error 37.7.7 Interrupt flag clear register (LPUART_ICR) Address offset: 0x20 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WUCF Res. Res. CMCF Res. w 15 14 13 12 11 10 9 8 7 6 5 Res. Res. Res. Res. Res. Res. CTSCF Res. Res. TCCF Res. w w 4 w 3 IDLECF ORECF w w 2 1 0 NCF FECF PECF w w w Bits 31:21 Reserved, must be kept at reset value. Bit 20 WUCF: Wakeup from Stop mode clear flag Writing 1 to this bit clears the WUF flag in the LPUART_ISR register. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and forced by hardware to ‘0’. Bits 19:18 Reserved, must be kept at reset value. Bit 17 CMCF: Character match clear flag Writing 1 to this bit clears the CMF flag in the LPUART_ISR register. Bits 16:10 Reserved, must be kept at reset value. Bit 9 CTSCF: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the LPUART_ISR register. Bits 8:7 Reserved, must be kept at reset value. DocID024597 Rev 1 1269/1680 1272 Low-power universal asynchronous receiver transmitter (LPUART) RM0351 Bit 6 TCCF: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the LPUART_ISR register. Bit 5 Reserved, must be kept at reset value. Bit 4 IDLECF: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the LPUART_ISR register. Bit 3 ORECF: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the LPUART_ISR register. Bit 2 NCF: Noise detected clear flag Writing 1 to this bit clears the NF flag in the LPUART_ISR register. Bit 1 FECF: Framing error clear flag Writing 1 to this bit clears the FE flag in the LPUART_ISR register. Bit 0 PECF: Parity error clear flag Writing 1 to this bit clears the PE flag in the LPUART_ISR register. 37.7.8 Receive data register (LPUART_RDR) Address offset: 0x24 Reset value: Undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8 7 6 5 4 3 2 1 0 r r r r 15 14 13 12 11 10 9 Res. Res. Res. Res. Res. Res. Res. RDR[8:0] r r r r r Bits 31:9 Reserved, must be kept at reset value. Bits 8:0 RDR[8:0]: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 379). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. 37.7.9 Transmit data register (LPUART_TDR) Address offset: 0x28 Reset value: Undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8 7 6 5 4 3 2 1 0 rw rw rw rw 15 14 13 12 11 10 9 Res. Res. Res. Res. Res. Res. Res. TDR[8:0] rw 1270/1680 rw rw DocID024597 Rev 1 rw rw RM0351 Low-power universal asynchronous receiver transmitter (LPUART) Bits 31:9 Reserved, must be kept at reset value. Bits 8:0 TDR[8:0]: Transmit data value Contains the data character to be transmitted. The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 379). When transmitting with the parity enabled (PCE bit set to 1 in the LPUART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE=1. DocID024597 Rev 1 1271/1680 1272 0x28 LPUART_ TDR 1272/1680 Reset value DocID024597 Rev 1 0 Res. Res. Reset value Res. X X Refer to Section 2.2.2 on page 68 for the register boundary addresses. 0 X X X X 0 X X X X FE PE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDR[8:0] TDR[8:0] 0 0 0 0 X X X X X X X X Res. SBKRQ ADDM7 UE Res. UESM Res. Res. Res. Res. Res. EIE 0 Res. Res. TE Res. RE 0 Res. 0 Res. IDLEIE 0 FECF 0 MMRQ TCIE RXNEIE 0 Res. TXEIE 0 HDSEL PS PEIE 0 PECF NF Reset value Res. Res. PCE 0 NCF 0 TXFRQ 0 Res. DMAT DMAR 0 RXFRQ 0 Res. RTSE 0 ORE 0 Res. CTSE M WAKE 0 Res. MME 0 ORECF 0 Res. CTSIE 0 IDLE Res. 0 Res. 0 Res. TC 1 Res. 0 Res. 0 RXNE TXE 1 TCCF Res. 0 Res. CTS CTSIF 0 CTSCF 0 Res. 0 Res. 0 Res. DDRE OVRDIS 0 Res. 0 Res. Reserved 0 Res. 0 Res. Res. Res. STOP [1:0] Res. Res. Res. Res. Res. CMIE 0 Res. Res. Res. 0 DEM 0 Res. Res. Res. Reset value Res. DEDT0 SWAP DEP 0 Res. Res. 0 Res. Res. 0 Res. DEDT1 RXINV 0 Res. Res. Res. 0 Res. DEDT2 TXINV 0 Res. Res. BUSY 0 Res. Res. DATAINV 0 MSBFIRST 0 Res. 0 Res. DEDT3 DEAT0 DEDT4 0 Res. Res. 0 Res. CMF 0 CMCF 0x100x14 Res. 0 Res. 0 Res. 0 Res. DEAT1 0 Res. DEAT2 0 Res. RWU SBKF 0 Res. 0 Res. Res. DEAT3 0 Res. Res. 0 Res. Res. Res. 0 Res. WUF 0 WUCF Res. WUFIE Res. Res. WUS [1:0] Res. Res. Res. Res. DEAT4 0 Res. TEACK 0 Res. Res. Res. Res. Res. Res. Res. M1 Res. Res. Res. 0 Res. Res. Res. Reset value Res. Res. REACK Res. Res. 0 Res. Reset value Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. ADD[3:0] Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. LPUART_ RDR ADD[7:4] Res. 0x24 Res. LPUART_ICR 0 Res. 0x20 Res. LPUART_ISR 0 Res. 0x1C Res. LPUART_ RQR Res. Reset value Res. 0x18 Res. LPUART_ BRR 0 Res. 0x0C Res. LPUART_ CR3 Res. 0x08 0 Res. Reset value Res. 0x04 LPUART_ CR2 Res. LPUART_ CR1 Res. 0x00 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. 37.7.10 Res. Low-power universal asynchronous receiver transmitter (LPUART) RM0351 LPUART register map The table below gives the LPUART register map and reset values. Table 201. LPUART register map and reset values 0 0 0 0 0 BRR[19:0] 0 RM0351 Serial peripheral interface (SPI) 38 Serial peripheral interface (SPI) 38.1 Introduction The SPI interface can be used to communicate with external devices using the SPI protocol. SPI mode is selectable by software. SPI Motorola mode is selected by default after a device reset. The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex synchronous, serial communication with external devices. The interface can be configured as master and in this case it provides the communication clock (SCK) to the external slave device. The interface is also capable of operating in multimaster configuration. 38.2 38.3 SPI main features • Master or slave operation • Full-duplex synchronous transfers on three lines • Half-duplex synchronous transfer on two lines (with bidirectional data line) • Simplex synchronous transfers on two lines (with unidirectional data line) • 4-bit to 16-bit data size selection • Multimaster mode capability • 8 master mode baud rate prescalers up to fPCLK/2. • Slave mode frequency up to fPCLK/2. • NSS management by hardware or software for both master and slave: dynamic change of master/slave operations • Programmable clock polarity and phase • Programmable data order with MSB-first or LSB-first shifting • Dedicated transmission and reception flags with interrupt capability • SPI bus busy status flag • SPI Motorola support • Hardware CRC feature for reliable communication: – CRC value can be transmitted as last byte in Tx mode – Automatic CRC error checking for last received byte • Master mode fault, overrun flags with interrupt capability • CRC Error flag • Two 32-bit embedded Rx and Tx FIFOs with DMA capability • SPI TI mode support SPI implementation This manual describes the full set of features implemented in SPI1, SPI2 and SPI3. DocID024597 Rev 1 1273/1680 1307 Serial peripheral interface (SPI) RM0351 Table 202. STM32L4x6 SPI implementation SPI Features (1) SPI1 SPI2 SPI3 Hardware CRC calculation X X X Rx/Tx FIFO X X X NSS pulse mode X X X TI mode X X X 1. X = supported. 38.4 SPI functional description 38.4.1 General description The SPI allows synchronous, serial communication between the MCU and external devices. Application software can manage the communication by polling the status flag or using dedicated SPI interrupt. The main elements of SPI and their interactions are shown in the following block diagram Figure 416. Figure 416. SPI block diagram $GGUHVVDQGGDWDEXV 5HDG 5[ ),)2 &5&FRQWUROOHU 026, 0,62 6KLIWUHJLVWHU 5;21/< &32/ &3+$ '6>@ 7[ ),)2 :ULWH %,',2( 6&. %DXGUDWH JHQHUDWRU &5&(1 &5&1(;7 &5&/ &RPPXQLFDWLRQ FRQWUROOHU %5>@ ,QWHUQDO166 166 ORJLF 166 069 1274/1680 DocID024597 Rev 1 RM0351 Serial peripheral interface (SPI) Four I/O pins are dedicated to SPI communication with external devices. • MISO: Master In / Slave Out data. In the general case, this pin is used to transmit data in slave mode and receive data in master mode. • MOSI: Master Out / Slave In data. In the general case, this pin is used to transmit data in master mode and receive data in slave mode. • SCK: Serial Clock output pin for SPI masters and input pin for SPI slaves. • NSS: Slave select pin. Depending on the SPI and NSS settings, this pin can be used to either: – select an individual slave device for communication – synchronize the data frame or – detect a conflict between multiple masters See Section 38.4.4: Slave select (NSS) pin management for details. The SPI bus allows the communication between one master device and one or more slave devices. The bus consists of at least two wires - one for the clock signal and the other for synchronous data transfer. Other signals can be added depending on the data exchange between SPI nodes and their slave select signal management. 38.4.2 Communications between one master and one slave The SPI allows the MCU to communicate using different configurations, depending on the device targeted and the application requirements. These configurations use 2 or 3 wires (with software NSS management) or 3 or 4 wires (with hardware NSS management). Communication is always initiated by the master. Full-duplex communication By default, the SPI is configured for full-duplex communication. In this configuration, the shift registers of the master and slave are linked using two unidirectional lines between the MOSI and the MISO pins. During SPI communication, data is shifted synchronously on the SCK clock edges provided by the master. The master transmits the data to be sent to the slave via the MOSI line and receives data from the slave via the MISO line. When the data frame transfer is complete (all the bits are shifted) the information between the master and slave is exchanged. Figure 417. Full-duplex single master/ single slave application VKLIWUHJLVWHU 63,FORFN JHQHUDWRU 0,62 0,62 026, 026, 6&. 6&. 166 0DVWHU 9FF 166 VKLIWUHJLVWHU 6ODYH 069 1. The NSS pin is configured as an input in this case. DocID024597 Rev 1 1275/1680 1307 Serial peripheral interface (SPI) RM0351 Half-duplex communication The SPI can communicate in half-duplex mode by setting the BIDIMODE bit in the SPIx_CR1 register. In this configuration, one single cross connection line is used to link the shift registers of the master and slave together. During this communication, the data is synchronously shifted between the shift registers on the SCK clock edge in the transfer direction selected reciprocally by both master and slave with the BDIOE bit in their SPIx_CR1 registers. In this configuration, the master’s MISO pin and the slave’s MOSI pin are free for other application uses and act as GPIOs. Figure 418. Half-duplex single master/ single slave application SHIFT REGISTER 30) CLOCK GENERATOR -)3/ -)3/ -/3) -/3) 3#+ 3#+ .33 -ASTER SHIFT REGISTER 6CC .33 3LAVE -36 1. The NSS pin is configured as an input in this case. 2. In this configuration, the master’s MISO pin and the slave’s MOSI pin can be used as GPIOs. Simplex communications The SPI can communicate in simplex mode by setting the SPI in transmit-only or in receiveonly using the RXONLY bit in the SPIx_CR2 register. In this configuration, only one line is used for the transfer between the shift registers of the master and slave. The remaining MISO and MOSI pins pair is not used for communication and can be used as standard GPIOs. 1276/1680 • Transmit-only mode (RXONLY=0): The configuration settings are the same as for fullduplex. The application has to ignore the information captured on the unused input pin. This pin can be used as a standard GPIO. • Receive-only mode (RXONLY=1): The application can disable the SPI output function by setting the RXONLY bit. In slave configuration, the MISO output is disabled and the pin can be used as a GPIO. The slave continues to receive data from the MOSI pin while its slave select signal is active (see 38.4.4: Slave select (NSS) pin management). Received data events appear depending on the data buffer configuration. In the master configuration, the MOSI output is disabled and the pin can be used as a GPIO. The clock signal is generated continuously as long as the SPI is enabled. The only way to stop the clock is to clear the RXONLY bit or the SPE bit and wait until the incoming pattern from the MISO pin is finished and fills the data buffer structure, depending on its configuration. DocID024597 Rev 1 RM0351 Serial peripheral interface (SPI) Figure 419. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) SHIFT REGISTER 30) CLOCK GENERATOR -)3/ -)3/ -/3) -/3) 3#+ 3#+ .33 -ASTER SHIFT REGISTER 6CC .33 3LAVE -36 1. The NSS pin is configured as an input in this case. 2. The input information is captured in the shift register and must be ignored in standard transmit only mode (for example, OVF flag) 3. In this configuration, both the MISO pins can be used as GPIOs. Note: Any simplex communication can be alternatively replaced by a variant of the half duplex communication with a constant setting of the transaction direction (bidirectional mode is enabled while BDIO bit is not changed). 38.4.3 Standard multi-slave communication In a configuration with two or more independent slaves, the master uses GPIO pins to manage the chip select lines for each slave (see Figure 420.). The master must select one of the slaves individually by pulling low the GPIO connected to the slave NSS input. When this is done, a standard master and dedicated slave communication is established. DocID024597 Rev 1 1277/1680 1307 Serial peripheral interface (SPI) RM0351 Figure 420. Master and three independent slaves NSS shift register (1) Vcc MOSI MISO SPI clock generator Master MOSI shift register MISO SCK SCK I/O 1 NSS I/O 2 Slave 1 I/O 3 MOSI shift register MISO SCK NSS MOSI Slave 2 shift register MISO SCK NSS Slave 3 MS19830V1 1. As MISO pins of the slaves are connected together, all slaves must have the GPIO configuration of their MISO pin set as alternate function open-drain (see Section 9.3.7: I/O alternate function input/output on page 273. 38.4.4 Slave select (NSS) pin management In slave mode, the NSS works as a standard “chip select” input and lets the slave communicate with the master. In master mode, NSS can be used either as output or input. As an input it can prevent multimaster bus collision, and as an output it can drive a slave select signal of a single slave. 1278/1680 DocID024597 Rev 1 RM0351 Serial peripheral interface (SPI) Hardware or software slave select management can be set using the SSM bit in the SPIx_CR1 register: • Software NSS management (SSM = 1): in this configuration, slave select information is driven internally by the SSI bit value in register SPIx_CR1. The external NSS pin is free for other application uses. • Hardware NSS management (SSM = 0): in this case, there are two possible configurations. The configuration used depends on the NSS output configuration (SSOE bit in register SPIx_CR1). – NSS output enable (SSM=0,SSOE = 1): this configuration is only used when the MCU is set as master. The NSS pin is managed by the hardware. The NSS signal is driven low as soon as the SPI is enabled in master mode (SPE=1), and is kept low until the SPI is disabled (SPE =0). A pulse can be generated between continuous communications if NSS pulse mode is activated (NSSP=1). The SPI cannot work in multimaster configuration with this NSS setting. – NSS output disable (SSM=0, SSOE = 0): if the microcontroller is acting as the master on the bus, this configuration allows multimaster capability. If the NSS pin is pulled low in this mode, the SPI enters master mode fault state and the device is automatically reconfigured in slave mode. In slave mode, the NSS pin works as a standard “chip select” input and the slave is selected while NSS line is at low level. Figure 421. Hardware/software slave select management 66,FRQWUROELW 660FRQWUROELW 166 ,QS 0DVWHU PRGH 6ODYHPRGH 9GG 2. 1RQDFWLYH 9VV &RQIOLFW $FWLYH 166,QSXW 166 SLQ *3,2 ORJLF 166 2XWSXW &RQWURO 1662XWSXW XVHGLQ0DVWHUPRGHDQG166 +:PDQDJHPHQWRQO\ 662(FRQWUROELW 166H[WHUQDOORJLF 166LQWHUQDOORJLF 06Y9 DocID024597 Rev 1 1279/1680 1307 Serial peripheral interface (SPI) 38.4.5 RM0351 Communication formats During SPI communication, receive and transmit operations are performed simultaneously. The serial clock (SCK) synchronizes the shifting and sampling of the information on the data lines. The communication format depends on the clock phase, the clock polarity and the data frame format. To be able to communicate together, the master and slaves devices must follow the same communication format. Clock phase and polarity controls Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits in the SPIx_CR1 register. The CPOL (clock polarity) bit controls the idle state value of the clock when no data is being transferred. This bit affects both master and slave modes. If CPOL is reset, the SCK pin has a low-level idle state. If CPOL is set, the SCK pin has a high-level idle state. If the CPHA bit is set, the second edge on the SCK pin captures the first data bit transacted (falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set). Data are latched on each occurrence of this clock transition type. If the CPHA bit is reset, the first edge on the SCK pin captures the first data bit transacted (falling edge if the CPOL bit is set, rising edge if the CPOL bit is reset). Data are latched on each occurrence of this clock transition type. The combination of CPOL (clock polarity) and CPHA (clock phase) bits selects the data capture clock edge. Figure 422, shows an SPI full-duplex transfer with the four combinations of the CPHA and CPOL bits. Note: Prior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit. The idle state of SCK must correspond to the polarity selected in the SPIx_CR1 register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). 1280/1680 DocID024597 Rev 1 RM0351 Serial peripheral interface (SPI) Figure 422. Data clock timing diagram &3+$ &32/ &32/ 026, 06%LW 0,62 06%LW /6%LW /6%LW 166 WRVODYH &DSWXUHVWUREH &3+$ &32/ &32/ 026, 0,62 /6%LW 06%LW 06%LW /6%LW 166 WRVODYH &DSWXUHVWUREH DLH 1. The order of data bits depends on LSBFIRST bit setting. Data frame format The SPI shift register can be set up to shift out MSB-first or LSB-first, depending on the value of the LSBFIRST bit. The data frame size is chosen by using the DS bits. It can be set from 4-bit up to 16-bit length and the setting applies for both transmission and reception. Whatever the selected data frame size, read access to the FIFO must be aligned with the FRXTH level. When the SPIx_DR register is accessed, data frames are always right-aligned into either a byte (if the data fits into a byte) or a half-word (see Figure 423). During communication, only bits within the data frame are clocked and transferred. DocID024597 Rev 1 1281/1680 1307 Serial peripheral interface (SPI) RM0351 Figure 423. Data alignment when data length is not equal to 8-bit or 16-bit '6 ELWVGDWDLVULJKWDOLJQHGRQE\WH ([DPSOH'6 ELW ;;; 'DWDIUDPH 5; ;; 7; 'DWDIUDPH '6!ELWVGDWDLVULJKWDOLJQHGRQELW ([DPSOH'6 ELW 'DWDIUDPH 7; 'DWDIUDPH 5; 069 Note: The minimum data length is 4 bits. If a data length of less than 4 bits is selected, it is forced to an 8-bit data frame size. 38.4.6 Configuration of SPI The configuration procedure is almost the same for master and slave. For specific mode setups, follow the dedicated chapters. When a standard communication is to be initialized, perform these steps: 1. 2. 3. 1282/1680 Write proper GPIO registers: Configure GPIO for MOSI, MISO and SCK pins. Write to the SPI_CR1 register: a) Configure the serial clock baud rate using the BR[2:0] bits (Note: 4). b) Configure the CPOL and CPHA bits combination to define one of the four relationships between the data transfer and the serial clock (CPHA must be cleared in NSSP mode). (Note: 2). c) Select simplex or half-duplex mode by configuring RXONLY or BIDIMODE and BIDIOE (RXONLY and BIDIMODE can't be set at the same time). d) Configure the LSBFIRST bit to define the frame format (Note: 2). e) Configure the CRCL and CRCEN bits if CRC is needed (while SCK clock signal is at idle state). f) Configure SSM and SSI (Note: 2 & 3). g) Configure the MSTR bit (in multimaster NSS configuration, avoid conflict state on NSS if master is configured to prevent MODF error). Write to SPI_CR2 register: a) Configure the DS[3:0] bits to select the data length for the transfer. b) Configure SSOE (Note: 1 & 2 & 3). c) Set the FRF bit if the TI protocol is required (keep NSSP bit cleared in TI mode). d) Set the NSSP bit if the NSS pulse mode between two data units is required (keep CHPA and TI bits cleared in NSSP mode). e) Configure the FRXTH bit. The RXFIFO threshold must be aligned to the read access size for the SPIx_DR register. f) Initialize LDMA_TX and LDMA_RX bits if DMA is used in packed mode. 4. Write to SPI_CRCPR register: Configure the CRC polynomial if needed. 5. Write proper DMA registers: Configure DMA streams dedicated for SPI Tx and Rx in DMA registers if the DMA streams are used. DocID024597 Rev 1 RM0351 Note: Serial peripheral interface (SPI) (1) Step is not required in slave mode. (2) Step is not required in TI mode. (3) Step is not required in NSSP mode. (4) The step is not required in slave mode except slave working at TI mode 38.4.7 Procedure for enabling SPI It is recommended to enable the SPI slave before the master sends the clock. If not, undesired data transmission might occur. The data register of the slave must already contain data to be sent before starting communication with the master (either on the first edge of the communication clock, or before the end of the ongoing communication if the clock signal is continuous). The SCK signal must be settled at an idle state level corresponding to the selected polarity before the SPI slave is enabled. The master at full duplex (or in any transmit-only mode) starts to communicate when the SPI is enabled and TXFIFO is not empty, or with the next write to TXFIFO. In any master receive only mode (RXONLY=1 or BIDIMODE=1 & BIDIOE=0), master starts to communicate and the clock starts running immediately after SPI is enabled. For handling DMA, follow the dedicated chapter. 38.4.8 Data transmission and reception procedures RXFIFO and TXFIFO All SPI data transactions pass through the 32-bit embedded FIFOs. This enables the SPI to work in a continuous flow, and prevents overruns when the data frame size is short. Each direction has its own FIFO called TXFIFO and RXFIFO. These FIFOs are used in all SPI modes except for receiver-only mode (slave or master) with CRC calculation enabled (see Section 38.4.13: CRC calculation). The handling of FIFOs depends on the data exchange mode (duplex, simplex), data frame format (number of bits in the frame), access size performed on the FIFO data registers (8-bit or 16-bit), and whether or not data packing is used when accessing the FIFOs (see Section 38.4.12: TI mode). A read access to the SPIx_DR register returns the oldest value stored in RXFIFO that has not been read yet. A write access to the SPIx_DR stores the written data in the TXFIFO at the end of a send queue. The read access must be always aligned with the RXFIFO threshold configured by the FRXTH bit in SPIx_CR2 register. FTLVL[1:0] and FRLVL[1:0] bits indicate the current occupancy level of both FIFOs. A read access to the SPIx_DR register must be managed by the RXNE event. This event is triggered when data is stored in RXFIFO and the threshold (defined by FRXTH bit) is reached. When RXNE is cleared, RXFIFO is considered to be empty. In a similar way, write access of a data frame to be transmitted is managed by the TXE event. This event is triggered when the TXFIFO level is less than or equal to half of its capacity. Otherwise TXE is cleared and the TXFIFO is considered as full. In this way, RXFIFO can store up to four data frames, whereas TXFIFO can only store up to three when the data frame format is not greater than 8 bits. This difference prevents possible corruption of 3x 8-bit data frames already stored in the TXFIFO when software tries to write more data in 16-bit mode into DocID024597 Rev 1 1283/1680 1307 Serial peripheral interface (SPI) RM0351 TXFIFO. Both TXE and RXNE events can be polled or handled by interrupts. See Figure 425 through Figure 428. Another way to manage the data exchange is to use DMA (see Section 11.2: DMA main features). If the next data is received when the RXFIFO is full, an overrun event occurs (see description of OVR flag at Section 38.4.9: SPI status flags). An overrun event can be polled or handled by an interrupt. The BSY bit being set indicates ongoing transaction of a current data frame. When the clock signal runs continuously, the BSY flag stays set between data frames at master but becomes low for a minimum duration of one SPI clock at slave between each data frame transfer. Sequence handling A few data frames can be passed at single sequence to complete a message. When transmission is enabled, a sequence begins and continues while any data is present in the TXFIFO of the master. The clock signal is provided continuously by the master until TXFIFO becomes empty, then it stops waiting for additional data. In receive-only modes, half duplex (BIDIMODE=1, BIDIOE=0) or simplex (BIDIMODE=0, RXONLY=1) the master starts the sequence immediately when both SPI is enabled and receive-only mode is activated. The clock signal is provided by the master and it does not stop until either SPI or receive-only mode is disabled by the master. The master receives data frames continuously up to this moment. While the master can provide all the transactions in continuous mode (SCK signal is continuous) it has to respect slave capability to handle data flow and its content at anytime. When necessary, the master must slow down the communication and provide either a slower clock or separate frames or data sessions with sufficient delays. Be aware there is no underflow error signal for master or slave in SPI mode, and data from the slave is always transacted and processed by the master even if the slave could not prepare it correctly in time. It is preferable for the slave to use DMA, especially when data frames are shorter and bus rate is high. Each sequence must be encased by the NSS pulse in parallel with the multislave system to select just one of the slaves for communication. In a single slave system it is not necessary to control the slave with NSS, but it is often better to provide the pulse here too, to synchronize the slave with the beginning of each data sequence. NSS can be managed by both software and hardware (see Section 38.4.4: Slave select (NSS) pin management). When the BSY bit is set it signifies an ongoing data frame transaction. When the dedicated frame transaction is finished, the RXNE flag is raised. The last bit is just sampled and the complete data frame is stored in the RXFIFO. Procedure for disabling the SPI When SPI is disabled, it is mandatory to follow the disable procedures described in this paragraph. It is important to do this before the system enters a low-power mode when the peripheral clock is stopped. Ongoing transactions can be corrupted in this case. In some modes the disable procedure is the only way to stop continuous communication running. Master in full duplex or transmit only mode can finish any transaction when it stops providing data for transmission. In this case, the clock stops after the last data transaction. Special care must be taken in packing mode when an odd number of data frames are transacted to 1284/1680 DocID024597 Rev 1 RM0351 Serial peripheral interface (SPI) prevent some dummy byte exchange (refer to Data packing section). Before the SPI is disabled in these modes, the user must follow standard disable procedure. When the SPI is disabled at the master transmitter while a frame transaction is ongoing or next data frame is stored in TXFIFO, the SPI behavior is not guaranteed. When the master is in any receive only mode, the only way to stop the continuous clock is to disable the peripheral by SPE=0. This must occur in specific time window within last data frame transaction just between the sampling time of its first bit and before its last bit transfer starts (in order to receive a complete number of expected data frames and to prevent any additional “dummy” data reading after the last valid data frame). Specific procedure must be followed when disabling SPI in this mode. Data received but not read remains stored in RXFIFO when the SPI is disabled, and must be processed the next time the SPI is enabled, before starting a new sequence. To prevent having unread data, ensure that RXFIFO is empty when disabling the SPI, by using the correct disabling procedure, or by initializing all the SPI registers with a software reset via the control of a specific register dedicated to peripheral reset (see the SPIiRST bits in the RCC_APBiRSTR registers). Standard disable procedure is based on pulling BSY status together with FTLVL[1:0] to check if a transmission session is fully completed. This check can be done in specific cases, too, when it is necessary to identify the end of ongoing transactions, for example: • When NSS signal is managed by software and master has to provide proper end of NSS pulse for slave, or • When transactions’ streams from DMA or FIFO are completed while the last data frame or CRC frame transaction is still ongoing in the peripheral bus. The correct disable procedure is (except when receive only mode is used): 1. Wait until FTLVL[1:0] = 00 (no more data to transmit). 2. Wait until BSY=0 (the last data frame is processed). 3. Disable the SPI (SPE=0). 4. Read data until FRLVL[1:0] = 00 (read all the received data). The correct disable procedure for certain receive only modes is: Note: 1. Interrupt the receive flow by disabling SPI (SPE=0) in the specific time window while the last data frame is ongoing. 2. Wait until BSY=0 (the last data frame is processed). 3. Read data until FRLVL[1:0] = 00 (read all the received data). If packing mode is used and an odd number of data frames with a format less than or equal to 8 bits (fitting into one byte) has to be received, FRXTH must be set when FRLVL[1:0] = 01, in order to generate the RXNE event to read the last odd data frame and to keep good FIFO pointer alignment. Data packing When the data frame size fits into one byte (less than or equal to 8 bits), data packing is used automatically when any read or write 16-bit access is performed on the SPIx_DR register. The double data frame pattern is handled in parallel in this case. At first, the SPI operates using the pattern stored in the LSB of the accessed word, then with the other half stored in the MSB. Figure 424 provides an example of data packing mode sequence handling. Two data frames are sent after the single 16-bit access the SPIx_DR register of the transmitter. This sequence can generate just one RXNE event in the receiver if the DocID024597 Rev 1 1285/1680 1307 Serial peripheral interface (SPI) RM0351 RXFIFO threshold is set to 16 bits (FRXTH=0). The receiver then has to access both data frames by a single 16-bit read of SPIx_DR as a response to this single RXNE event. The RxFIFO threshold setting and the following read access must be always kept aligned at the receiver side, as data can be lost if it is not in line. A specific problem appears if an odd number of such “fit into one byte” data frames must be handled. On the transmitter side, writing the last data frame of any odd sequence with an 8bit access to SPIx_DR is enough. The receiver has to change the Rx_FIFO threshold level for the last data frame received in the odd sequence of frames in order to generate the RXNE event. Figure 424. Packing data in FIFO for transmission and reception 166 6&. 7;),)2 63,[B'5 [$ [ [$ [ 5;),)2 026, [$ 63,IVP VKLIW ELWDFFHVVZKHQZULWHWRGDWDUHJLVWHU 63,B'5 [$ZKHQ7[( [$ [ 63,IVP VKLIW 63,[B'5 [ [ [$ ELWDFFHVVZKHQUHDGIURPGDWDUHJLVWHU 63,B'5 [$ZKHQ5[1( 069 Communication using DMA (direct memory addressing) To operate at its maximum speed and to facilitate the data register read/write process required to avoid overrun, the SPI features a DMA capability, which implements a simple request/acknowledge protocol. A DMA access is requested when the TXE or RXNE enable bit in the SPIx_CR2 register is set. Separate requests must be issued to the Tx and Rx buffers. • In transmission, a DMA request is issued each time TXE is set to 1. The DMA then writes to the SPIx_DR register. • In reception, a DMA request is issued each time RXNE is set to 1. The DMA then reads the SPIx_DR register. See Figure 425 through Figure 428. When the SPI is used only to transmit data, it is possible to enable only the SPI Tx DMA channel. In this case, the OVR flag is set because the data received is not read. When the SPI is used only to receive data, it is possible to enable only the SPI Rx DMA channel. In transmission mode, when the DMA has written all the data to be transmitted (the TCIF flag is set in the DMA_ISR register), the BSY flag can be monitored to ensure that the SPI communication is complete. This is required to avoid corrupting the last transmission before disabling the SPI or entering the Stop mode. The software must first wait until FTLVL[1:0]=00 and then until BSY=0. When starting communication using DMA, to prevent DMA channel management raising error events, these steps must be followed in order: 1286/1680 DocID024597 Rev 1 RM0351 Serial peripheral interface (SPI) 1. Enable DMA Rx buffer in the RXDMAEN bit in the SPI_CR2 register, if DMA Rx is used. 2. Enable DMA streams for Tx and Rx in DMA registers, if the streams are used. 3. Enable DMA Tx buffer in the TXDMAEN bit in the SPI_CR2 register, if DMA Tx is used. 4. Enable the SPI by setting the SPE bit. To close communication it is mandatory to follow these steps in order: 1. Disable DMA streams for Tx and Rx in the DMA registers, if the streams are used. 2. Disable the SPI by following the SPI disable procedure. 3. Disable DMA Tx and Rx buffers by clearing the TXDMAEN and RXDMAEN bits in the SPI_CR2 register, if DMA Tx and/or DMA Rx are used. Packing with DMA If the transfers are managed by DMA (TXDMAEN and RXDMAEN set in the SPIx_CR2 register) packing mode is enabled/disabled automatically depending on the PSIZE value configured for SPI TX and the SPI RX DMA channel. If the DMA channel PSIZE value is equal to 16-bit and SPI data size is less than or equal to 8-bit, then packing mode is enabled. The DMA then automatically manages the write operations to the SPIx_DR register. If data packing mode is used and the number of data to transfer is not a multiple of two, the LDMA_TX/LDMA_RX bits must be set. The SPI then considers only one data for the transmission or reception to serve the last DMA transfer (for more details refer to Data packing on page 1285.) DocID024597 Rev 1 1287/1680 1307 Serial peripheral interface (SPI) RM0351 Communication diagrams Some typical timing schemes are explained in this section. These schemes are valid no matter if the SPI events are handled by pulling, interrupts or DMA. For simplicity, the LSBFIRST=0, CPOL=0 and CPHA=1 setting is used as a common assumption here. No complete configuration of DMA streams is provided. The following numbered notes are common for Figure 425 on page 1289 through Figure 428 on page 1292. 1288/1680 1. The slave starts to control MISO line as NSS is active and SPI is enabled, and is disconnected from the line when one of them is released. Sufficient time must be provided for the slave to prepare data dedicated to the master in advance before its transaction starts. At the master, the SPI peripheral takes control at MOSI and SCK signals (occasionally at NSS signal as well) only if SPI is enabled. If SPI is disabled the SPI peripheral is disconnected from GPIO logic, so the levels at these lines depends on GPIO setting exclusively. 2. At the master, BSY stays active between frames if the communication (clock signal) is continuous. At the slave, BSY signal always goes down for at least one clock cycle between data frames. 3. The TXE signal is cleared only if TXFIFO is full. 4. The DMA arbitration process starts just after the TXDMAEN bit is set. The TXE interrupt is generated just after the TXEIE is set. As the TXE signal is at an active level, data transfers to TxFIFO start, until TxFIFO becomes full or the DMA transfer completes. 5. If all the data to be sent can fit into TxFIFO, the DMA Tx TCIF flag can be raised even before communication on the SPI bus starts. This flag always rises before the SPI transaction is completed. 6. The CRC value for a package is calculated continuously frame by frame in the SPIx_TxCRCR and SPIx_RxCRCR registers. The CRC information is processed after the entire data package has completed, either automatically by DMA (Tx channel must be set to the number of data frames to be processed) or by SW (the user must handle CRCNEXT bit during the last data frame processing). While the CRC value calculated in SPIx_TxCRCR is simply sent out by transmitter, received CRC information is loaded into RxFIFO and then compared with the SPIx_RxCRCR register content (CRC error flag can be raised here if any difference). This is why the user must take care to flush this information from the FIFO, either by software reading out all the stored content of RxFIFO, or by DMA when the proper number of data frames is preset for Rx channel (number of data frames + number of CRC frames) (see the settings at the example assumption). 7. In data packed mode, TxE and RxNE events are paired and each read/write access to the FIFO is 16 bits wide until the number of data frames are even. If the TxFIFO is ¾ full FTLVL status stays at FIFO full level. That is why the last odd data frame cannot be stored before the TxFIFO becomes ½ full. This frame is stored into TxFIFO with an 8bit access either by software or automatically by DMA when LDMA_TX control is set. 8. To receive the last odd data frame in packed mode, the Rx threshold must be changed to 8-bit when the last data frame is processed, either by software setting FRXTH=1 or automatically by a DMA internal signal when LDMA_RX is set. DocID024597 Rev 1 RM0351 Serial peripheral interface (SPI) Figure 425. Master full duplex communication 166 6&. %6< 026, '7[ 06% '7[ 06% '7[ 06% 63( 7;( (QDEOH7[5['0$RULQWHUUXSWV '7[ )7/9/ '7[ '7[ '0$RUVRIWZDUHFRQWURODW7[HYHQWV '5[ 0,62 /6% '5[ /6% '5[ /6% 5;1( '0$RUVRIWZDUHFRQWURODW5[HYHQWV )5/9/ '0$7[7,&) '5[ '5[ '5[ '0$5[7,&) 06Y9 Assumptions for master full duplex communication example: • Data size > 8 bit If DMA is used: • Number of Tx frames transacted by DMA is set to 3 • Number of Rx frames transacted by DMA is set to 3 See also : Communication diagrams on page 1288 for details about common assumptions and notes. DocID024597 Rev 1 1289/1680 1307 Serial peripheral interface (SPI) RM0351 Figure 426. Slave full duplex communication 166 6&. %6< 06% '7[ 06% 0,62 06% '7[ '7[ 63( 7;( (QDEOH7[5['0$RULQWHUUXSWV '7[ )7/9/ '7[ '7[ '5[ 026, '0$RUVRIWZDUHFRQWURODW7[HYHQWV /6% '5[ /6% '5[ /6% 5;1( '0$RUVRIWZDUHFRQWURODW5[HYHQWV )5/9/ '0$7[7,&) '5[ '5[ '5[ '0$5[7,&) 06Y9 Assumptions for slave full duplex communication example: • Data size > 8 bit If DMA is used: • Number of Tx frames transacted by DMA is set to 3 • Number of Rx frames transacted by DMA is set to 3 See also : Communication diagrams on page 1288 for details about common assumptions and notes. 1290/1680 DocID024597 Rev 1 RM0351 Serial peripheral interface (SPI) Figure 427. Master full duplex communication with CRC 166 6&. %6< 026, '7[ 06% '7[ 06% &5& 06% 63( 7;( (QDEOH7[5['0$RULQWHUUXSWV '7[ )7/9/ '7[ '0$RUVRIWZDUHFRQWURODW7[HYHQWV '5[ 0,62 /6% '5[ /6% &5& /6% 5;1( '0$RUVRIWZDUHFRQWURODW5[HYHQWV )5/9/ '0$7[7,&) '5[ '5[ '5[ '0$5[7,&) 06Y9 Assumptions for master full duplex communication with CRC example: • Data size = 16 bit • CRC enabled If DMA is used: • Number of Tx frames transacted by DMA is set to 2 • Number of Rx frames transacted by DMA is set to 3 See also : Communication diagrams on page 1288 for details about common assumptions and notes. DocID024597 Rev 1 1291/1680 1307 Serial peripheral interface (SPI) RM0351 Figure 428. Master full duplex communication in packed mode 166 6&. %6< '7[ 026, '7[ '7[ 63( 7;( (QDEOH7[5['0$RULQWHUUXSWV '7[ '7[ '7[ '0$RUVRIWZDUHFRQWURODW7[HYHQWV )7/9/ 0,62 '5[ '5[ '5[ 5;1( '0$RUVRIWZDUHFRQWURODW5[HYHQWV '5[ '5[ )57+; '5[ )5/9/ '0$7[7,&) '0$5[7,&) 06Y9 Assumptions for master full duplex communication in packed mode example: • Data size = 5 bit • Read/write FIFO is performed mostly by 16-bit access • FRXTH=0 If DMA is used: • Number of Tx frames to be transacted by DMA is set to 3 • Number of Rx frames to be transacted by DMA is set to 3 • PSIZE for both Tx and Rx DMA channel is set to 16-bit • LDMA_TX=1 and LDMA_RX=1 See also : Communication diagrams on page 1288 for details about common assumptions and notes. 1292/1680 DocID024597 Rev 1 RM0351 38.4.9 Serial peripheral interface (SPI) SPI status flags Three status flags are provided for the application to completely monitor the state of the SPI bus. Tx buffer empty flag (TXE) The TXE flag is set when transmission TXFIFO has enough space to store data to send. TXE flag is linked to the TXFIFO level. The flag goes high and stays high until the TXFIFO level is lower or equal to 1/2 of the FIFO depth. An interrupt can be generated if the TXEIE bit in the SPIx_CR2 register is set. The bit is cleared automatically when the TXFIFO level becomes greater than 1/2. Rx buffer not empty (RXNE) The RXNE flag is set depending on the FRXTH bit value in the SPIx_CR2 register: • If FRXTH is set, RXNE goes high and stays high until the RXFIFO level is greater or equal to 1/4 (8-bit). • If FRXTH is cleared, RXNE goes high and stays high until the RXFIFO level is greater than or equal to 1/2 (16-bit). An interrupt can be generated if the RXNEIE bit in the SPIx_CR2 register is set. The RXNE is cleared by hardware automatically when the above conditions are no longer true. Busy flag (BSY) The BSY flag is set and cleared by hardware (writing to this flag has no effect). When BSY is set, it indicates that a data transfer is in progress on the SPI (the SPI bus is busy). The BSY flag can be used in certain modes to detect the end of a transfer so that the software can disable the SPI or its peripheral clock before entering a low-power mode which does not provide a clock for the peripheral. This avoids corrupting the last transfer. The BSY flag is also useful for preventing write collisions in a multimaster system. The BSY flag is cleared under any one of the following conditions: Note: • When the SPI is correctly disabled • When a fault is detected in Master mode (MODF bit set to 1) • In Master mode, when it finishes a data transmission and no new data is ready to be sent • In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between each data transfer. When the next transmission can be handled immediately by the master (e.g. if the master is in Receive-only mode or its Transmit FIFO is not empty), communication is continuous and the BSY flag remains set to '1' between transfers on the master side. Although this is not the case with a slave, it is recommended to use always the TXE and RXNE flags (instead of the BSY flags) to handle data transmission or reception operations. DocID024597 Rev 1 1293/1680 1307 Serial peripheral interface (SPI) 38.4.10 RM0351 SPI error flags An SPI interrupt is generated if one of the following error flags is set and interrupt is enabled by setting the ERRIE bit. Overrun flag (OVR) An overrun condition occurs when data is received by a master or slave and the RXFIFO has not enough space to store this received data. This can happen if the software or the DMA did not have enough time to read the previously received data (stored in the RXFIFO) or when space for data storage is limited e.g. the RXFIFO is not available when CRC is enabled in receive only mode so in this case the reception buffer is limited into a single data frame buffer (see Section 38.4.13: CRC calculation). When an overrun condition occurs, the newly received value does not overwrite the previous one in the RXFIFO. The newly received value is discarded and all data transmitted subsequently is lost. Clearing the OVR bit is done by a read access to the SPI_DR register followed by a read access to the SPI_SR register. Mode fault (MODF) Mode fault occurs when the master device has its internal NSS signal (NSS pin in NSS hardware mode, or SSI bit in NSS software mode) pulled low. This automatically sets the MODF bit. Master mode fault affects the SPI interface in the following ways: • The MODF bit is set and an SPI interrupt is generated if the ERRIE bit is set. • The SPE bit is cleared. This blocks all output from the device and disables the SPI interface. • The MSTR bit is cleared, thus forcing the device into slave mode. Use the following software sequence to clear the MODF bit: 1. Make a read or write access to the SPIx_SR register while the MODF bit is set. 2. Then write to the SPIx_CR1 register. To avoid any multiple slave conflicts in a system comprising several MCUs, the NSS pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits can be restored to their original state after this clearing sequence. As a security, hardware does not allow the SPE and MSTR bits to be set while the MODF bit is set. In a slave device the MODF bit cannot be set except as the result of a previous multimaster conflict. CRC error (CRCERR) This flag is used to verify the validity of the value received when the CRCEN bit in the SPIx_CR1 register is set. The CRCERR flag in the SPIx_SR register is set if the value received in the shift register does not match the receiver SPIx_RXCRCR value. The flag is cleared by the software. TI mode frame format error (FRE) A TI mode frame format error is detected when an NSS pulse occurs during an ongoing communication when the SPI is operating in slave mode and configured to conform to the TI mode protocol. When this error occurs, the FRE flag is set in the SPIx_SR register. The SPI is not disabled when an error occurs, the NSS pulse is ignored, and the SPI waits for the next NSS pulse before starting a new transfer. The data may be corrupted since the error detection may result in the loss of two data bytes. 1294/1680 DocID024597 Rev 1 RM0351 Serial peripheral interface (SPI) The FRE flag is cleared when SPIx_SR register is read. If the ERRIE bit is set, an interrupt is generated on the NSS error detection. In this case, the SPI should be disabled because data consistency is no longer guaranteed and communications should be reinitiated by the master when the slave SPI is enabled again. 38.4.11 NSS pulse mode This mode is activated by the NSSP bit in the SPIx_CR2 register and it takes effect only if the SPI interface is configured as Motorola SPI master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, CPOL setting is ignored). When activated, an NSS pulse is generated between two consecutive data frame transfers when NSS stays at high level for the duration of one clock period at least. This mode allows the slave to latch data. NSSP pulse mode is designed for applications with a single master-slave pair. Figure 429 illustrates NSS pin management when NSSP pulse mode is enabled. Figure 429. NSSP pulse generation in Motorola SPI master mode -ASTER CONTINUOUS TRANSFER #0/, #0(! .330 SAMPLING SAMPLING SAMPLING SAMPLING SAMPLING SAMPLING .33 OUTPUT 3#+ OUTPUT -/3) OUTPUT -3" -)3/ INPUT $/.4#!2% -3" ,3" ,3" $/.4#!2% T3#+ T3#+ T3#+ ELWVWRELWV -3" ,3" -3" ,3" T3#+ $/.4#!2% T3#+ ELWVWRELWV -36 Note: Similar behavior is encountered when CPOL = 0. In this case the sampling edge is the rising edge of SCK, and NSS assertion and deassertion refer to this sampling edge. 38.4.12 TI mode TI protocol in master mode The SPI interface is compatible with the TI protocol. The FRF bit of the SPIx_CR2 register can be used to configure the SPI to be compliant with this protocol. The clock polarity and phase are forced to conform to the TI protocol requirements whatever the values set in the SPIx_CR1 register. NSS management is also specific to the TI protocol which makes the configuration of NSS management through the SPIx_CR1 and SPIx_CR2 registers (SSM, SSI, SSOE) impossible in this case. In slave mode, the SPI baud rate prescaler is used to control the moment when the MISO pin state changes to HiZ when the current transaction finishes (see Figure 430). Any baud rate can be used, making it possible to determine this moment with optimal flexibility. However, the baud rate is generally set to the external master clock baud rate. The delay for the MISO signal to become HiZ (trelease) depends on internal resynchronization and on the DocID024597 Rev 1 1295/1680 1307 Serial peripheral interface (SPI) RM0351 baud rate value set in through the BR[2:0] bits in the SPIx_CR1 register. It is given by the formula: t baud_rate t baud_rate ---------------------- + 4 × t pclk < t release < ---------------------- + 6 × t pclk 2 2 If the slave detects a misplaced NSS pulse during a data frame transaction the TIFRE flag is set. If the data size is equal to 4-bits or 5-bits, the master in full-duplex mode or transmit-only mode uses a protocol with one more dummy data bit added after LSB. TI NSS pulse is generated above this dummy bit clock cycle instead of the LSB in each period. This feature is not available for Motorola SPI communications (FRF bit set to 0). Figure 430: TI mode transfer shows the SPI communication waveforms when TI mode is selected. Figure 430. TI mode transfer G M PL ER IN T 2%,%!3% SA IN G GG PL TR I M SA IN ER GG PL TR I M SA TRI GG ER G .33 3#+ -/3) -)3/ $/.4#!2% OR -3" ,3" -3" ,3" -3" ,3" -3" ,3" &2!-% &2!-% -36 38.4.13 CRC calculation Two separate CRC calculators are implemented in order to check the reliability of transmitted and received data. The SPI offers CRC8 or CRC16 calculation independently of the frame data length, which can be fixed to 8-bit or 16-bit. For all the other data frame lengths, no CRC is available. CRC principle CRC calculation is enabled by setting the CRCEN bit in the SPIx_CR1 register before the SPI is enabled (SPE = 1). The CRC value is calculated using an odd programmable polynomial on each bit. The calculation is processed on the sampling clock edge defined by the CPHA and CPOL bits in the SPIx_CR1 register. The calculated CRC value is checked automatically at the end of the data block as well as for transfer managed by CPU or by the DMA. When a mismatch is detected between the CRC calculated internally on the received data and the CRC sent by the transmitter, a CRCERR flag is set to indicate a data corruption error. The right procedure for handling the CRC calculation depends on the SPI configuration and the chosen transfer management. 1296/1680 DocID024597 Rev 1 RM0351 Note: Serial peripheral interface (SPI) The polynomial value should only be odd. No even values are supported. CRC transfer managed by CPU Communication starts and continues normally until the last data frame has to be sent or received in the SPIx_DR register. Then CRCNEXT bit has to be set in the SPIx_CR1 register to indicate that the CRC frame transaction will follow after the transaction of the currently processed data frame. The CRCNEXT bit must be set before the end of the last data frame transaction. CRC calculation is frozen during CRC transaction. The received CRC is stored in the RXFIFO like a data byte or word. That is why in CRC mode only, the reception buffer has to be considered as a single 16-bit buffer used to receive only one data frame at a time. A CRC-format transaction usually takes one more data frame to communicate at the end of data sequence. However, when setting an 8-bit data frame checked by 16-bit CRC, two more frames are necessary to send the complete CRC. When the last CRC data is received, an automatic check is performed comparing the received value and the value in the SPIx_RXCRC register. Software has to check the CRCERR flag in the SPIx_SR register to determine if the data transfers were corrupted or not. Software clears the CRCERR flag by writing '0' to it. After the CRC reception, the CRC value is stored in the RXFIFO and must be read in the SPIx_DR register in order to clear the RXNE flag. CRC transfer managed by DMA When SPI communication is enabled with CRC communication and DMA mode, the transmission and reception of the CRC at the end of communication is automatic (with the exception of reading CRC data in receive only mode). The CRCNEXT bit does not have to be handled by the software. The counter for the SPI transmission DMA channel has to be set to the number of data frames to transmit excluding the CRC frame. On the receiver side, the received CRC value is handled automatically by DMA at the end of the transaction but user must take care to flush out received CRC information from RXFIFO as it is always loaded into it. In full duplex mode, the counter of the reception DMA channel can be set to the number of data frames to receive including the CRC, which means, for example, in the specific case of an 8-bit data frame checked by 16-bit CRC: DMA_RX = Numb_of_data + 2 In receive only mode, the DMA reception channel counter should contain only the amount of data transferred, excluding the CRC calculation. Then based on the complete transfer from DMA, all the CRC values must be read back by software from FIFO as it works as a single buffer in this mode. At the end of the data and CRC transfers, the CRCERR flag in the SPIx_SR register is set if corruption occurred during the transfer. If packing mode is used, the LDMA_RX bit needs managing if the number of data is odd. Resetting the SPIx_TXCRC and SPIx_RXCRC values The SPIx_TXCRC and SPIx_RXCRC values are cleared automatically when new data is sampled after a CRC phase. This allows the use of DMA circular mode (not available in receive-only mode) in order to transfer data without any interruption, (several data blocks covered by intermediate CRC checking phases). DocID024597 Rev 1 1297/1680 1307 Serial peripheral interface (SPI) RM0351 If the SPI is disabled during a communication the following sequence must be followed: 1. Disable the SPI 2. Clear the CRCEN bit 3. Enable the CRCEN bit 4. Enable the SPI Note: When the SPI is in slave mode, the CRC calculator is sensitive to the SCK slave input clock as soon as the CRCEN bit is set, and this is the case whatever the value of the SPE bit. In order to avoid any wrong CRC calculation, the software must enable CRC calculation only when the clock is stable (in steady state). When the SPI interface is configured as a slave, the NSS internal signal needs to be kept low between the data phase and the CRC phase. 38.5 SPI interrupts During SPI communication an interrupts can be generated by the following events: • Transmit TXFIFO ready to be loaded • Data received in Receive RXFIFO • Master mode fault • Overrun error • TI frame format error • CRC protocol error Interrupts can be enabled and disabled separately. Table 203. SPI interrupt requests Interrupt event Event flag Enable Control bit TXE TXEIE Data received in RXFIFO RXNE RXNEIE Master Mode fault event MODF Transmit TXFIFO ready to be loaded Overrun error OVR TI frame format error FRE CRC protocol error 1298/1680 CRCERR DocID024597 Rev 1 ERRIE RM0351 Serial peripheral interface (SPI) 38.6 SPI registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). SPI_DR in addition by can be accessed by 8-bit access. 38.6.1 SPI control register 1 (SPIx_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 BIDI MODE BIDI OE CRC EN CRC NEXT CRCL RX ONLY SSM SSI LSB FIRST SPE rw rw rw rw rw rw rw rw rw rw 5 4 3 BR [2:0] rw rw rw 2 1 0 MSTR CPOL CPHA rw rw rw Bit 15 BIDIMODE: Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. 0: 2-line unidirectional data mode selected 1: 1-line bidirectional data mode selected Bit 14 BIDIOE: Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode 0: Output disabled (receive-only mode) 1: Output enabled (transmit-only mode) Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. Bit 13 CRCEN: Hardware CRC calculation enable 0: CRC calculation disabled 1: CRC calculation Enabled Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation. Bit 12 CRCNEXT: Transmit CRC next 0: Next transmit value is from Tx buffer 1: Next transmit value is from Tx CRC register Note: This bit has to be written as soon as the last data is written in the SPIx_DR register. Bit 11 CRCL: CRC length This bit is set and cleared by software to select the CRC length. 0: 8-bit CRC length 1: 16-bit CRC length Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation. DocID024597 Rev 1 1299/1680 1307 Serial peripheral interface (SPI) RM0351 Bit 10 RXONLY: Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. 0: Full duplex (Transmit and receive) 1: Output disabled (Receive-only mode) Bit 9 SSM: Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. 0: Software slave management disabled 1: Software slave management enabled Note: This bit is not used in SPI TI mode. Bit 8 SSI: Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in SPI TI mode. Bit 7 LSBFIRST: Frame format 0: data is transmitted / received with the MSB first 1: data is transmitted / received with the LSB first Note: 1. This bit should not be changed when communication is ongoing. 2. This bit is not used in SPI TI mode. Bit 6 SPE: SPI enable 0: Peripheral disabled 1: Peripheral enabled Note: When disabling the SPI, follow the procedure described in Procedure for disabling the SPI on page 1284. Bits 5:3 BR[2:0]: Baud rate control 000: fPCLK/2 001: fPCLK/4 010: fPCLK/8 011: fPCLK/16 100: fPCLK/32 101: fPCLK/64 110: fPCLK/128 111: fPCLK/256 Note: These bits should not be changed when communication is ongoing. 1300/1680 DocID024597 Rev 1 RM0351 Serial peripheral interface (SPI) Bit 2 MSTR: Master selection 0: Slave configuration 1: Master configuration Note: This bit should not be changed when communication is ongoing. Bit1 CPOL: Clock polarity 0: CK to 0 when idle 1: CK to 1 when idle Note: This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. Bit 0 CPHA: Clock phase 0: The first clock transition is the first data capture edge 1: The second clock transition is the first data capture edge Note: This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. 38.6.2 SPI control register 2 (SPIx_CR2) Address offset: 0x04 Reset value: 0x0700 15 14 13 12 Res. LDMA _TX LDMA _RX FRXT H rw rw rw 11 10 9 8 DS [3:0] rw rw rw 7 6 5 TXEIE RXNEIE ERRIE rw rw rw rw 4 3 2 FRF NSSP SSOE rw rw rw 1 0 TXDMAEN RXDMAEN rw rw Bit 15 Reserved, must be kept at reset value. Bit 14 LDMA_TX: Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). 0: Number of data to transfer is even 1: Number of data to transfer is odd Note: Refer to Procedure for disabling the SPI on page 1284 if the CRCEN bit is set. Bit 13 LDMA_RX: Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). 0: Number of data to transfer is even 1: Number of data to transfer is odd Note: Refer to Procedure for disabling the SPI on page 1284 if the CRCEN bit is set. Bit 12 FRXTH: FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) 1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) DocID024597 Rev 1 1301/1680 1307 Serial peripheral interface (SPI) RM0351 Bits 11:8 DS [3:0]: Data size These bits configure the data length for SPI transfers: 0000: Not used 0001: Not used 0010: Not used 0011: 4-bit 0100: 5-bit 0101: 6-bit 0110: 7-bit 0111: 8-bit 1000: 9-bit 1001: 10-bit 1010: 11-bit 1011: 12-bit 1100: 13-bit 1101: 14-bit 1110: 15-bit 1111: 16-bit If software attempts to write one of the “Not used” values, they are forced to the value “0111”(8bit). Bit 7 TXEIE: Tx buffer empty interrupt enable 0: TXE interrupt masked 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. Bit 6 RXNEIE: RX buffer not empty interrupt enable 0: RXNE interrupt masked 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. Bit 5 ERRIE: Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). 0: Error interrupt is masked 1: Error interrupt is enabled Bit 4 FRF: Frame format 0: SPI Motorola mode 1 SPI TI mode Note: This bit must be written only when the SPI is disabled (SPE=0). Bit 3 NSSP: NSS pulse management This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = ’1’, or FRF = ’1’. 0: No NSS pulse 1: NSS pulse generated Note: 1. This bit must be written only when the SPI is disabled (SPE=0). 2. This bit is not used in SPI TI mode. 1302/1680 DocID024597 Rev 1 RM0351 Serial peripheral interface (SPI) Bit 2 SSOE: SS output enable 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. Note: This bit is not used in SPI TI mode. Bit 1 TXDMAEN: Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set. 0: Tx buffer DMA disabled 1: Tx buffer DMA enabled Bit 0 RXDMAEN: Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set. 0: Rx buffer DMA disabled 1: Rx buffer DMA enabled DocID024597 Rev 1 1303/1680 1307 Serial peripheral interface (SPI) 38.6.3 RM0351 SPI status register (SPIx_SR) Address offset: 0x08 Reset value: 0x0002 15 Res. 14 Res. 13 Res. 12 11 10 9 FTLVL[1:0] FRLVL[2:0] r r r r 8 7 6 5 4 3 2 1 0 Res. Res. TXE RXNE r r FRE BSY OVR MODF CRC ERR r r r r rc_w0 Bits 15:13 Reserved, must be kept at reset value. Bits 12:11 FTLVL[1:0]: FIFO Transmission Level These bits are set and cleared by hardware. 00: FIFO empty 01: 1/4 FIFO 10: 1/2 FIFO 11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) Bits 10:9 FRLVL[1:0]: FIFO reception level These bits are set and cleared by hardware. 00: FIFO empty 01: 1/4 FIFO 10: 1/2 FIFO 11: FIFO full Note: These bits are not used in SPI receive-only mode while CRC calculation is enabled. Bit 8 FRE: Frame format error This flag is used for SPI in TI slave mode. Refer to Section 38.4.10: SPI error flags. This flag is set by hardware and reset when SPIx_SR is read by software. 0: No frame format error 1: A frame format error occurred Bit 7 BSY: Busy flag 0: SPI not busy 1: SPI is busy in communication or Tx buffer is not empty This flag is set and cleared by hardware. Note: The BSY flag must be used with caution: refer to Section 38.4.9: SPI status flags and Procedure for disabling the SPI on page 1284. Bit 6 OVR: Overrun flag 0: No overrun occurred 1: Overrun occurred This flag is set by hardware and reset by a software sequence. Bit 5 MODF: Mode fault 0: No mode fault occurred 1: Mode fault occurred This flag is set by hardware and reset by a software sequence. Refer to Section : Mode fault (MODF) on page 1294 for the software sequence. Bit 4 CRCERR: CRC error flag 0: CRC value received matches the SPIx_RXCRCR value 1: CRC value received does not match the SPIx_RXCRCR value This flag is set by hardware and cleared by software writing 0. 1304/1680 DocID024597 Rev 1 RM0351 Serial peripheral interface (SPI) Bits 3:2 Reserved, must be kept at reset value. Bit 1 TXE: Transmit buffer empty 0: Tx buffer not empty 1: Tx buffer empty Bit 0 RXNE: Receive buffer not empty 0: Rx buffer empty 1: Rx buffer not empty 38.6.4 SPI data register (SPIx_DR) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DR[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 DR[15:0]: Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section 38.4.8: Data transmission and reception procedures). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. 38.6.5 SPI CRC polynomial register (SPIx_CRCPR) Address offset: 0x10 Reset value: 0x0007 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CRCPOLY[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CRCPOLY[15:0]: CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required. Note: The polynomial value should be odd only. No even value is supported. DocID024597 Rev 1 1305/1680 1307 Serial peripheral interface (SPI) 38.6.6 RM0351 SPI Rx CRC register (SPIx_RXCRCR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r RxCRC[15:0] r r r r r r r r r Bits 15:0 RXCRC[15:0]: Rx CRC register When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. A read to this register when the BSY Flag is set could return an incorrect value. 38.6.7 SPI Tx CRC register (SPIx_TXCRCR) Address offset: 0x18 Reset value: 0x0000 15 14 13 12 11 10 9 r r r r r r r 8 7 6 5 4 3 2 1 0 r r r r r r r TxCRC[15:0] r r Bits 15:0 TxCRC[15:0]: Tx CRC register When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. A read to this register when the BSY flag is set could return an incorrect value. 1306/1680 DocID024597 Rev 1 0x18 SPIx_TXCRCR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SPIx_RXCRCR Res. 0x14 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SPIx_CRCPR Res. 0x10 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SPIx_DR Res. 0x0C Reset value Reset value Reset value Reset value DocID024597 Rev 1 0 0 0 0 FRXTH 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDMAEN 0 0 0 0 DR[15:0] 0 CRCPOLY[15:0] 0 RxCRC[15:0] 0 TxCRC[15:0] 0 RXNE SSOE TXDMAEN 0 TXE 0 Res. FRF NSSP 0 Res. 0 CRCERR 0 OVR 1 MODF ERRIE 0 RXNEIE 1 TXEIE DS[3:0] BSY 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOL 0 CPHA 0 BR [2:0] MSTR SSI LSBFIRST 0 SPE SSM 0 FRE CRCNEXT 0 CRCL BIDIOE CRCEN 0 RXONLY BIDIMODE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 FRLVL[1:0] FTLVL[1:0] LDMA_TX LDMA_RX 0 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SPIx_SR Res. 0x08 SPIx_CR2 Res. 0x04 SPIx_CR1 Res. 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. 38.6.8 Res. RM0351 Serial peripheral interface (SPI) SPI register map Table 204 shows the SPI register map and reset values. Table 204. SPI register map and reset values 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 68 for the register boundary addresses. 1307/1680 1307 Serial audio interface (SAI) RM0351 39 Serial audio interface (SAI) 39.1 Introduction The SAI interface (Serial Audio Interface) offers a wide set of audio protocols due to its flexibility and wide range of configurations. Many stereo or mono audio applications may be targeted. I2S standards, LSB or MSB-justified, PCM/DSP, TDM, and AC’97 protocols may be addressed for example. SPDIF output is offered when the audio block is configured as a transmitter. To bring this level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks. Each block has it own clock generator and I/O line controller. The SAI can work in master or slave configuration. The audio sub-blocks can be either receiver or transmitter and can work synchronously or not (with respect to the other one). The SAI can be connected with other SAIs to work synchronously. 1308/1680 DocID024597 Rev 1 RM0351 39.2 Serial audio interface (SAI) SAI main features • Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO. • 8-word integrated FIFOs for each audio sub-block. • Synchronous or asynchronous mode between the audio sub-blocks. • Possible synchronization between multiple SAIs. • Master or slave configuration independent for both audio sub-blocks. • Clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode. • Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit. • Audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 • SPDIF output available if required. • Up to 16 slots available with configurable size. • Number of bits by frame can be configurable. • Frame synchronization active level configurable (offset, bit length, level). • First active bit position in the slot is configurable. • LSB first or MSB first for data transfer. • Mute mode. • Stereo/Mono audio frame capability. • Communication clock strobing edge configurable (SCK). • Error flags with associated interrupts if enabled respectively. • • – Overrun and underrun detection, – Anticipated frame synchronization signal detection in slave mode, – Late frame synchronization signal detection in slave mode, – Codec not ready for the AC’97 mode in reception. Interruption sources when enabled: – Errors, – FIFO requests. 2-channel DMA interface. DocID024597 Rev 1 1309/1680 1353 Serial audio interface (SAI) RM0351 39.3 SAI functional description 39.3.1 SAI block diagram The SAI block diagram is shown in Figure 431. Figure 431. Functional block diagram $3%EXV $XGLREORFN$ ),)2FWUO ),)2 6$,B&.B$ &ORFNJHQHUDWRU $XGLREORFN$ &RQILJXUDWLRQ DQGVWDWXV UHJLVWHUV )60 ELWVKLIWUHJLVWHU $XGLREORFN% ),)2FWUO ),)2 6$,B&.B% &ORFNJHQHUDWRU $XGLREORFN% 6$,B%&5 6\QFKUR FWUORXW &RQILJXUDWLRQ DQGVWDWXV UHJLVWHUV LQWB)6 LQWB6&. )6B$ 6&.B$ 6'B$ 0&/.B$ )6B% 6&.B% 6'B% 0&/.B% )60 ELWVKLIWUHJLVWHU $3%,QWHUIDFH $3%EXV 6$,[B)6 6$,[B6&. )URPRWKHU6$,%ORFNV 6$,B$&5 6$,B*&5 ,2/LQH0DQDJHPHQW $3%,QWHUIDFH 6\QFKUR LQ 6$, 069 The SAI is mainly composed of two audio sub-blocks with their own clock generator. Each audio block integrates a 32-bit shift register controlled by their own functional state machine. Data are stored or read from the dedicated FIFO. FIFO may be accessed by the CPU, or by DMA in order to leave the CPU free during the communication. Each audio block is independent. They can be synchronous with each other. An I/O line controller manages a set of 4 dedicated pins (SD, SCK, FS, MCLK) for a given audio block in the SAI. Some of these pins can be shared if the two sub-blocks are declared as synchronous to leave some free to be used as general purpose I/Os. The MCLK pin can be output, or not, depending on the application, the decoder requirement and whether the audio block is configured as the master. If one SAI is configured to operate synchronously with another one, even more I/Os can be freed (except for pins SD_x). The functional state machine can be configured to address a wide range of audio protocols. Some registers are present to set-up the desired protocols (audio frame waveform generator). 1310/1680 DocID024597 Rev 1 RM0351 Serial audio interface (SAI) The audio sub-block can be a transmitter or receiver, in master or slave mode. The master mode means the SCK_x bit clock and the frame synchronization signal are generated from the SAI, whereas in slave mode, they come from another external or internal master. There is a particular case for which the FS signal direction is not directly linked to the master or slave mode definition. In AC’97 protocol, it will be an SAI output even if the SAI (link controller) is set-up to consume the SCK clock (and so to be in Slave mode). Note: For ease of reading of this section, the notation SAI_x refers to SAI_A or SAI_B, where ‘x’ represents the SAI A or B sub-block. 39.3.2 Main SAI modes Each audio sub-block of the SAI can be configured to be master or slave via MODE bits in the SAI_xCR1 register of the selected audio block. Master mode In master mode, the SAI delivers the timing signals to the external connected device: • The bit clock and the frame synchronization are output on pin SCK_x and FS_x, respectively. • If needed, the SAI can also generate a master clock on MCLK_x pin. Both SCK_x, FS_x and MCLK_x are configured as outputs. Slave mode The SAI expects to receive timing signals from an external device. • If the SAI sub-block is configured in asynchronous mode, then SCK_x and FS_x pins are configured as inputs. • If the SAI sub-block is configured to operate synchronously with another SAI interface or with the second audio sub-block, the corresponding SCK_x and FS_x pins are left free to be used as general purpose I/Os. In slave mode, MCLK_x pin is not used and can be assigned to another function. It is recommended to enable the slave device before enabling the master. Configuring and enabling SAI modes Each audio sub-block can be independently defined as a transmitter or receiver through the MODE bit in the SAI_xCR1 register of the corresponding audio block. As a result, SAIx_SD pin will be respectively configured as an output or an input. Two master audio blocks in the same SAI can be configured with two different MCLK and SCK clock frequencies. In this case they have to be configured in asynchronous mode. Each of the audio blocks in the SAI are enabled by bit SAIXEN in the SAI_xCR1 register. As soon as this bit is active, the transmitter or the receiver is sensitive to the activity on the clock line, data line and synchronization line in slave mode. In master TX mode, enabling the audio block immediately generates the bit clock for the external slaves even if there is no data in the FIFO, However FS signal generation is conditioned by the presence of data in the FIFO. After the FIFO receives the first data to transmit, this data is output to external slaves. If there is no data to transmit in the FIFO, 0 values are then sent in the audio frame with an underrun flag generation. DocID024597 Rev 1 1311/1680 1353 Serial audio interface (SAI) RM0351 In slave mode, the audio frame starts when the audio block is enabled and when a start of frame is detected. In Slave TX mode, no underrun event is possible on the first frame after the audio block is enabled, because the mandatory operating sequence in this case is: 39.3.3 1. Write into the SAI_xDR (by software or by DMA). 2. Wait until the FIFO threshold (FLH) flag is different from 000b (FIFO empty). 3. Enable the audio block in slave transmitter mode. SAI synchronization mode There are two levels of synchronization, either at audio sub-block level or at SAI level. Internal synchronization An audio sub-block can be configured to operate synchronously with the second audio subblock in the same SAI. In this case, the bit clock and the frame synchronization signals are shared to reduce the number of external pins used for the communication. The audio block configured in synchronous mode sees its own SCK_x, FS_x, and MCLK_x pins released back as GPIOs while the audio block configured in asynchronous mode is the one for which FS_x and SCK_x ad MCLK_x I/O pins are relevant (if the audio block is considered as master). Typically, the audio block in synchronous mode can be used to configure the SAI in full duplex mode. One of the two audio blocks can be configured as a master and the other as slave, or both as slaves with one asynchronous block (corresponding SYNCEN[1:0] bits set to 00 in SAI_xCR1) and one synchronous block (corresponding SYNCEN[1:0] bits set to 01 in the SAI_xCR1). Note: Due to internal resynchronization stages, PCLK APB frequency must be higher than twice the bit rate clock frequency. External synchronization The audio sub-blocks can also be configured to operate synchronously with another SAI. This can be done as follow: Note: 1. The SAI, which is configured as the source from which the other SAI is synchronized, has to define which of its audio sub-block is supposed to provide the FS and SCK signals to other SAI. This is done by programming SYNCOUT[1:0] bits. 2. The SAI which shall receive the synchronization signals has to select which SAI will provide the synchronization by setting the proper value on SYNCIN[1:0] bits. For each of the two SAI audio sub-blocks, the user must then specify if it operates synchronously with the other SAI via the SYNCEN bit. SYNCIN[1:0] and SYNCOUT[1:0] bits are located into the SAI_GCR register, and SYNCEN bits into SAI_xCR1 register. If both audio sub-blocks in a given SAI need to be synchronized with another SAI, it is possible to choose one of the following configurations: 1312/1680 • Configure each audio block to be synchronous with another SAI block through the SYNCEN[1:0] bits. • Configure one audio block to be synchronous with another SAI through the SYNCEN[1:0] bits. The other audio block is then configured as synchronous with the second SAI audio block through SYNCEN[1:0] bits. DocID024597 Rev 1 RM0351 Serial audio interface (SAI) The following table shows how to select the proper synchronization signal depending on the SAI block used. For example SAI2 can select the synchronization from SAI1 by setting SAI2 SYNCIN to 0. If SAI1 wants to select the synchronization coming from SAI2, SAI1 SYNCIN must be set to 1. Positions noted as ‘res’ shall not be used. Table 205. External Synchronization Selection Block instance 39.3.4 SYNCIN= 3 SYNCIN= 2 SYNCIN= 1 SYNCIN= 0 SAI1 res res SAI2 sync res SAI2 res res res SAI1 sync Audio data size The audio frame can target different data sizes by configuring bit DS[2:0] in the SAI_xCR1 register. The data sizes may be 8, 10, 16, 20, 24 or 32 bits. During the transfer, either the MSB or the LSB of the data are sent first, depending on the configuration of bit LSBFIRST in the SAI_xCR1 register. 39.3.5 Frame synchronization The FS signal acts as the Frame synchronization signal in the audio frame (start of frame). The shape of this signal is completely configurable in order to target the different audio protocols with their own specificities concerning this Frame synchronization behavior. This reconfigurability is done using register SAI_xFRCR. Figure 432 illustrates this flexibility. Figure 432. Audio frame )6/HQJWKXSWRELWV )6DFWLYHXSWRELWV )6 6&. 6' )62)) 6' )62)) 7KHIDOOLQJHGJHFDQRFFXULQWRWKLVDUHD 6ORW 6ORW 6ORW 6ORW 6ORW 6ORW 6ORW 6ORW 6ORW 6ORW « « 6ORW 6ORW 06Y9 In AC’97 mode or in SPDIF mode (bit PRTCFG[1:0] = 10 or PRTCFG[1:0] = 01 in the SAI_xCR1 register), the frame synchronization shape is forced to match the AC’97 protocol. The SAI_xFRCR register value is ignored. Each audio block is independent and consequently each one requires a specific configuration. DocID024597 Rev 1 1313/1680 1353 Serial audio interface (SAI) RM0351 Frame length • Master mode The audio frame length can be configured to up to 256 bit clock cycles, by setting FRL[7:0] field in the SAI_xFRCR register. If the frame length is greater than the number of declared slots for the frame, the remaining bits to transmit will be extended to 0 or the SD line will be released to HI-z depending the state of bit TRIS in the SAI_xCR2 register (refer to Section : FS signal role). In reception mode, the remaining bit is ignored. If bit NODIV is cleared, (FRL+1) must be equal to a power of 2, from 8 to 256, to ensure that an audio frame contains an integer number of MCLK pulses per bit clock cycle. If bit NODIV is set, the (FRL+1) field can take any value from 8 to 256. Refer to Section 39.3.7: SAI clock generator”. • Slave mode The audio frame length is mainly used to specify to the slave the number of bit clock cycles per audio frame sent by the external master. It is used mainly to detect from the master any anticipated or late occurrence of the Frame synchronization signal during an on-going audio frame. In this case an error will be generated. For more details refer to Section 39.3.12: Error flags. In slave mode, there are no constraints on the FRL[7:0] configuration in the SAI_xFRCR register. The number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame is 8. Frame synchronization polarity FSPOL bit in the SAI_xFRCR register sets the active polarity of the FS pin from which a frame is started. The start of frame is edge sensitive. In slave mode, the audio block waits for a valid frame to start transmitting or receiving. Start of frame is synchronized to this signal. It is effective only if the start of frame is not detected during an ongoing communication and assimilated to an anticipated start of frame (refer to Section 39.3.12: Error flags). In master mode, the frame synchronization is sent continuously each time an audio frame is complete until the SAIXEN bit in the SAI_xCR1 register is cleared. If no data are present in the FIFO at the end of the previous audio frame, an underrun condition will be managed as described in Section 39.3.12: Error flags), but the audio communication flow will not be interrupted. Frame synchronization active level length The FSALL[6:0] bits of the SAI_xFRCR register allow configuring the length of the active level of the Frame synchronization signal. The length can be set from 1 to 128 bit clock cycles. As an example, the active length can be half of the frame length in I2S, LSB or MSB-justified modes, or one-bit wide for PCM/DSP or TDM mode. Frame synchronization offset Depending on the audio protocol targeted in the application, the Frame synchronization signal can be asserted when transmitting the last bit or the first bit of the audio frame (this is 1314/1680 DocID024597 Rev 1 RM0351 Serial audio interface (SAI) the case in I2S standard protocol and in MSB-justified protocol, respectively). FSOFF bit in the SAI_xFRCR register allows to choose one of the two configurations. FS signal role The FS signal can have a different meaning depending on the FS function. FSDEF bit in the SAI_xFRCR register selects which meaning it will have: • 0: start of frame, like for instance the PCM/DSP, TDM, AC’97, audio protocols, • 1: start of frame and channel side identification within the audio frame like for the I2S, the MSB or LSB-justified protocols. When the FS signal is considered as a start of frame and channel side identification within the frame, the number of declared slots must be considered to be half the number for the left channel and half the number for the right channel. If the number of bit clock cycles on half audio frame is greater than the number of slots dedicated to a channel side, and TRIS = 0, 0 is sent for transmission for the remaining bit clock cycles in the SAI_xCR2 register. Otherwise if TRIS = 1, the SD line is released to HI-Z. In reception mode, the remaining bit clock cycles are not considered until the channel side changes. Figure 433. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) 1XPEHURIVORWVQRWDOLJQHGZLWKWKHDXGLRIUDPH $XGLRIUDPH +DOIRIIUDPH )6 VFN VORW 6ORW21 6ORW2)) 6ORW21 6ORW21 6ORW2)) 6ORW21 1XPEHURIVORWVDOLJQHGZLWKWKHDXGLRIUDPH $XGLRIUDPH +DOIRIIUDPH )6 VFN VORW 6ORW 6ORW 6ORW 6ORW 6ORW 6ORW 069 1. The frame length should be even. If FSDEF bit in SAI_xFRCR is kept clear, so FS signal is equivalent to a start of frame, and if the number of slots defined in NBSLOT[3:0] in SAI_xSLOTR multiplied by the number of bits by slot configured in SLOTSZ[1:0] in SAI_xSLOTR is less than the frame size (bit FRL[7:0] in the SAI_xFRCR register), then: DocID024597 Rev 1 1315/1680 1353 Serial audio interface (SAI) RM0351 • if TRIS = 0 in the SAI_xCR2 register, the remaining bit after the last slot will be forced to 0 until the end of frame in case of transmitter, • if TRIS = 1, the line will be released to HI-Z during the transfer of these remaining bits. In reception mode, these bits are discarded. Figure 434. FS role is start of frame (FSDEF = 0) $XGLRIUDPH VFN VORW 6ORW 6ORW 6ORW 6ORWQ 'DWD DIWHUVORWQLI75,6 6'RXWSXWUHOHDVHG +,= DIWHUVORWQLI75,6 069 The FS signal is not used when the audio block in transmitter mode is configured to get the SPDIF output on the SD line. The corresponding FS I/O will be released and left free for other purposes. 39.3.6 Slot configuration The slot is the basic element in the audio frame. The number of slots in the audio frame is equal to NBSLOT[3:0] + 1. The maximum number of slots per audio frame is fixed at 16. For AC’97 protocol or SPDIF (when bit PRTCFG[1:0] = 10 or PRTCFG[1:0] = 01), the number of slots is automatically set to target the protocol specification, and the value of NBSLOT[3:0] is ignored. Each slot can be defined as a valid slot, or not, by setting SLOTEN[15:0] bits of the SAI_xSLOTR register. When a invalid slot is transferred, the SD data line is either forced to 0 or released to HI-z depending on TRIS bit configuration (refer to Section : Output data line management on an inactive slot) in transmitter mode. In receiver mode, the received value from the end of this slot is ignored. Consequently, there will be no FIFO access and so no request to read or write the FIFO linked to this inactive slot status. The slot size is also configurable as shown in Figure 435. The size of the slots is selected by setting SLOTSZ[1:0] bits in the SAI_xSLOTR register. The size is applied identically for each slot in an audio frame. 1316/1680 DocID024597 Rev 1 RM0351 Serial audio interface (SAI) Figure 435. Slot size configuration with FBOFF = 0 in SAI_xSLOTR $XGLREORFNLVUHFHLYHU $XGLREORFNLVWUDQVPLWWHU 6ORWVL]H GDWDVL]H 6ORWVL]H GDWDVL]H VORW[ GDWDVL]H VORW[ GDWDVL]H GDWDVL]H GDWDVL]H VORW[ GDWDVL]H VORW[ GDWDVL]H ELW ELW VORW[ ;; GDWDVL]H VORW[ GDWDVL]H ;;;; ELW ELW ;GRQ¶WFDUH 069 It is possible to choose the position of the first data bit to transfer within the slots. This offset is configured by FBOFF[4:0] bits in the SAI_xSLOTR register. 0 values will be injected in transmitter mode from the beginning of the slot until this offset position is reached. In reception, the bit in the offset phase is ignored. This feature targets the LSB justified protocol (if the offset is equal to the slot size minus the data size). Figure 436. First bit offset $XGLREORFNLVWUDQVPLWWHU $XGLREORFNLVUHFHLYHU 6ORWVL]H GDWDVL]H 6ORWVL]H GDWDVL]H VORW[ VORW[ GDWDVL]H GDWDVL]H GDWDVL]H GDWDVL]H )%2)) )%2)) VORW[ ;; GDWDVL]H VORW[ ELW GDWDVL]H ;; ELW )%2)) 6/276='6 )%2)) 6/276='6 VORW[ GDWDVL]H VORW[ ;;;; GDWDVL]H ELW ;GRQ¶WFDUH ELW 069 It is mandatory to respect the following conditions to avoid bad SAI behavior: FBOFF ≤(SLOTSZ - DS), DS ≤SLOTSZ, NBSLOT x SLOTSZ ≤FRL (frame length), The number of slots must be even when bit FSDEF in the SAI_xFRCR register is set. In AC’97 and SPDIF protocol (bit PRTCFG[1:0] = 10 or PRTCFG[1:0] = 01), the slot size is automatically set as defined in Section 39.3.9: AC’97 link controller. DocID024597 Rev 1 1317/1680 1353 Serial audio interface (SAI) RM0351 Refer to Section 39.3.9: AC’97 link controller for details on clock generator programming in AC’97 mode and to Section 39.3.10: SPDIF output for details on clock generator programming in SPDIF mode. 39.3.7 SAI clock generator Each audio block has its own clock generator that makes these two blocks completely independent. There is no difference in terms of functionality between these two clock generators. When the audio block is configured as Master, the clock generator provides the communication clock (the bit clock) and the master clock for external decoders. When the audio block is defined as slave, the clock generator is OFF. Figure 437 illustrates the architecture of the audio block clock generator. Figure 437. Audio block clock generator overview 12',9 0&.',9>@ 0&/.B[ 6$,B&.B[ 0DVWHUFORFN GLYLGHU )5/>@ 12',9 12',9 %LWFORFNGLYLGHU 6&.B[ 06Y9 Note: If NODIV is set to 1, the MCLK_x signal will be set at 0 level if this pin is configured as the SAI pin in GPIO peripherals. The clock source for the clock generator comes from the product clock controller. The SAI_CK_x clock is equivalent to the master clock which can be divided for the external decoders using bit MCKDIV[3:0]: MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2), if MCKDIV[3:0] is not equal to 0000. MCLK_x = SAI_CK_x, if MCKDIV[3:0] is equal to 0000. MCLK_x signal is used only in TDM. The division must be even in order to keep 50% on the Duty cycle on the MCLK output and on the SCK_x clock. If bit MCKDIV[3:0] = 0000, division by one is applied to obtain MCLK_x equal to SAI_CK_x. In the SAI, the single ratio MCLK/FS = 256 is considered. Mostly, three frequency ranges will be encountered as illustrated in Table 206. 1318/1680 DocID024597 Rev 1 RM0351 Serial audio interface (SAI) Table 206. Example of possible audio frequency sampling range Input SAI_CK_x clock frequency 192 kHz x 256 44.1 kHz x 256 SAI_CK_x = MCLK(1) Most usual audio frequency sampling achievable MCKDIV[3:0] 192 kHz MCKDIV[3:0] = 0000 96 kHz MCKDIV[3:0] = 0001 48 kHz MCKDIV[3:0] = 0010 16 kHz MCKDIV[3:0] = 0110 8 kHz MCKDIV[3:0] = 1100 44.1 kHz MCKDIV[3:0] = 0000 22.05 kHz MCKDIV[3:0] = 0001 11.025 kHz MCKDIV[3:0] = 0010 MCLK MCKDIV[3:0] = 0000 1. This may happen when the product clock controller selects an external clock source, instead of PLL clock. The master clock can be generated externally on an I/O pad for external decoders if the corresponding audio block is declared as master with bit NODIV = 0 in the SAI_xCR1 register. In slave, the value set in this last bit is ignored since the clock generator is OFF, and the MCLK_x I/O pin is released for use as a general purpose I/O. The bit clock is derived from the master clock. The bit clock divider sets the divider factor between the bit clock (SCK_x) and the master clock (MCLK_x) following the formula: SCK_x = MCLK x (FRL[7:0] +1) / 256 where: 256 is the fixed ratio between MCLK and the audio frequency sampling. FRL[7:0] is the number of bit clock cycles- 1 in the audio frame, configured in the SAI_xFRCR register. In master mode it is mandatory that (FRL[7:0] +1) is equal to a number with a power of 2 (refer to Section 39.3.5: Frame synchronization) to obtain an even integer number of MCLK_x pulses by bit clock cycle. The 50% duty cycle is guaranteed on the bit clock (SCK_x). The SAI_CK_x clock can also be equal to the bit clock frequency. In this case, NODIV bit in the SAI_xCR1 register should be set and the value inside the MCKDIV divider and the bit clock divider will be ignored. In this case, the number of bits per frame is fully configurable without the need to be equal to a power of two. The bit clock strobing edge on SCK can be configured by bit CKSTR in the SAI_xCR1 register. Refer to Section 39.3.10: SPDIF output for details on clock generator programming in SPDIF mode. DocID024597 Rev 1 1319/1680 1353 Serial audio interface (SAI) 39.3.8 RM0351 Internal FIFOs Each audio block in the SAI has its own FIFO. Depending if the block is defined to be a transmitter or a receiver, the FIFO can be written or read, respectively. There is therefore only one FIFO request linked to FREQ bit in the SAI_xSR register. An interrupt is generated if FREQIE bit is enabled in the SAI_xIM register. This depends on: • FIFO threshold setting (FLTH bits in SAI_xCR2) • Communication direction (transmitter or receiver). Refer to Section : Interrupt generation in transmitter mode and Section : Interrupt generation in reception mode. Interrupt generation in transmitter mode The interrupt generation depends on the FIFO configuration in transmitter mode: • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO empty (FTH[2:0] set to 000b), an interrupt is generated (FREQ bit set by hardware to 1 in SAI_xSR register) if no data are available in SAI_xDR register (FLTH[2:0] bits in SAI_xSR is less than 001b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when the FIFO is no more empty (FLTH[2:0] bits in SAI_xSR are different from 000b) i.e one or more data are stored in the FIFO. • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO quarter full (FTH[2:0] set to 001b), an interrupt is generated (FREQ bit set by hardware to 1 in SAI_xSR register) if less than a quarter of the FIFO contains data (FLTH[2:0] bits in SAI_xSR are less than 010b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when at least a quarter of the FIFO contains data (FLTH[2:0] bits in SAI_xSR are higher or equal to 010b). • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO half full (FTH[2:0] set to 010b), an interrupt is generated (FREQ bit set by hardware to 1 in SAI_xSR register) if less than half of the FIFO contains data (FLTH[2:0] bits in SAI_xSR are less than 011b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when at least half of the FIFO contains data (FLTH[2:0] bits in SAI_xSR are higher or equal to 011b). • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO three quarter (FTH[2:0] set to 011b), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_xSR register) if less than three quarters of the FIFO contain data (FLTH[2:0] bits in SAI_xSR are less than 100b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when at least three quarters of the FIFO contain data (FLTH[2:0] bits in SAI_xSR are higher or equal to 100b). • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO full (FTH[2:0] set to 100b), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_xSR register) if the FIFO is not full (FLTH[2:0] bits in SAI_xSR is less than 101b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when the FIFO is full (FLTH[2:0] bits in SAI_xSR is equal to 101b value). Interrupt generation in reception mode The interrupt generation depends on the FIFO configuration in reception mode: • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO empty (FTH[2:0] set to 000b), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_xSR register) if at least one data is available in SAI_xDR register(FLTH[2:0] bits in SAI_xSR is higher or equal to 001b). This Interrupt (FREQ bit in SAI_xSR register) is 1320/1680 DocID024597 Rev 1 RM0351 Serial audio interface (SAI) cleared by hardware when the FIFO becomes empty (FLTH[2:0] bits in SAI_xSR is equal to 000b) i.e no data are stored in FIFO. • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO quarter fully (FTH[2:0] set to 001b), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_xSR register) if at less one quarter of the FIFO data locations are available (FLTH[2:0] bits in SAI_xSR is higher or equal to 010b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when less than a quarter of the FIFO data locations become available (FLTH[2:0] bits in SAI_xSR is less than 010b). • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO half fully (FTH[2:0] set to 010b value), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_xSR register) if at least half of the FIFO data locations are available (FLTH[2:0] bits in SAI_xSR is higher or equal to 011b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when less than half of the FIFO data locations become available (FLTH[2:0] bits in SAI_xSR is less than 011b). • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO three quarter full(FTH[2:0] set to 011b value), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_xSR register) if at least three quarters of the FIFO data locations are available (FLTH[2:0] bits in SAI_xSR is higher or equal to 100b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when the FIFO has less than three quarters of the FIFO data locations avalable(FLTH[2:0] bits in SAI_xSR is less than 100b). • When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO full(FTH[2:0] set to 100b), an interrupt is generated (FREQ bit is set by hardware to 1 in SAI_xSR register) if the FIFO is full (FLTH[2:0] bits in SAI_xSR is equal to 101b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware when the FIFO is not full (FLTH[2:0] bits in SAI_xSR is less than 101b). Like interrupt generation, the SAI can use the DMA if DMAEN bit in the SAI_xCR1 register is set. The FREQ bit assertion mechanism is the same as the interruption generation mechanism described above for FREQIE. Each FIFO is an 8-word FIFO. Each read or write operation from/to the FIFO targets one word FIFO location whatever the access size. Each FIFO word contains one audio slot. FIFO pointers are incremented by one word after each access to the SAI_xDR register. Data should be right aligned when it is written in the SAI_xDR. Data received will be right aligned in the SAI_xDR. The FIFO pointers can be reinitialized when the SAI is disabled by setting bit FFLUSH in the SAI_xCR2 register. If FFLUSH is set when the SAI is enabled the data present in the FIFO will be lost automatically. DocID024597 Rev 1 1321/1680 1353 Serial audio interface (SAI) 39.3.9 RM0351 AC’97 link controller The SAI is able to work as an AC’97 link controller. In this protocol: • The slot number and the slot size are fixed. • The frame synchronization signal is perfectly defined and has a fixed shape. To select this protocol, set PRTCFG[1:0] bits in the SAI_xCR1 register to 10. When AC’97 mode is selected, only data sizes of 16 or 20 bits can be used, otherwise the SAI behavior is not guaranteed. • NBSLOT[3:0] and SLOTSZ[1:0] bits are consequently ignored. • The number of slots is fixed to 13 slots. The first one is 16-bit wide and all the others are 20-bit wide (data slots). • FBOFF[4:0] bits in the SAI_xSLOTR register are ignored. • The SAI_xFRCR register is ignored. • The MCLK is not used. The FS signal from the block defined as asynchronous is configured automatically as an output, since the AC’97 controller link drives the FS signal whatever the master or slave configuration. Figure 438 shows an AC’97 audio frame structure. Figure 438. AC’97 audio frame )6 6', 7DJ 6'2 7DJ &0' &0' 3&0 3&0 /,1( 3&0 3&0 3&0 $''5 '$7$ /)5217 5)5217 '$& &(17(5 /6855 56855 67$786 67$786 3&0 3&0 $''5 '$7$ /()7 5,*+7 /,1( $'& 3&0 0,& 565 9' 565 9' 3&0 /)( /,1( '$& +6(7 '$& ,2 &75/ 565 /9' /,1( $'& +6(7 ,2 67$786 069 Note: In AC’97 protocol, bit 2 of the tag is reserved (always 0), so bit 2 of the TAG is forced to 0 level whatever the value written in the SAI FIFO. For more details about tag representation, refer to the AC’97 protocol standard. One SAI can be used to target an AC’97 point-to-point communication. Using two SAIs (for devices featuring two embedded SAIs) allows controlling three external AC’97 decoders as illustrated in Figure 439. In SAI1, the audio block A must be declared as asynchronous master transmitter whereas the audio block B is defined to be slave receiver and internally synchronous to the audio block A. The SAI2 is configured for audio block A and B both synchronous with the external SAI1 in slave receiver mode. 1322/1680 DocID024597 Rev 1 RM0351 Serial audio interface (SAI) Figure 439. Example of typical AC’97 configuration on devices featuring at least 2 embedded SAIs (three external AC’97 decoders) $&¶/LQN&RQWUROOHU %LWFORFNSURYLGHU $XGLREORFN$ 3ULPDU\FRGHF 0DVWHU 6'$ ),)2 %ORFN% V\QFKURQRXVZLWK EORFN$ 7UDQVPLWWHU )6$ 6&/.$ &ORFN JHQHUDWRU 6GDWDBRXW 6\QF %LWBFON 6GDWDBLQ 6ODYH 6'% ),)2 5HFHLYHU )6% 6&/.% 6HFRQGDU\FRGHF $XGLREORFN% 6GDWDBRXW 6\QF %LWBFON 6$, $XGLREORFN$ 6ODYH 6GDWDBLQ 6'$ ),)2 6\QFKURQRXVZLWK RWKHU6$,FORFNV 5HFHLYHU )6$ 6&/.$ 6HFRQGDU\FRGHF &ORFN JHQHUDWRU 6ODYH ),)2 5HFHLYHU 6'% )6% 6&/.% 6GDWDBRXW 6\QF %LWBFON 6GDWDBLQ $XGLREORFN% 6$, 06Y9 In receiver mode, the SAI acting as an AC’97 link controller requires no FIFO request and so no data storage in the FIFO when the Codec ready bit in the slot 0 is decoded low. If bit CNRDYIE is enabled in the SAI_xIM register, flag CNRDY will be set in the SAI_xSR register and an interrupt is generated. This flag is dedicated to the AC’97 protocol. Clock generator programming in AC’97 mode In AC’97 mode, the frame length is fixed at 256 bits, and its frequency shall be set to 48 kHz. The formulas given in Section 39.3.7: SAI clock generator shall be used with FRL = 255, order to generate the proper frame rate (FFS_x). DocID024597 Rev 1 1323/1680 1353 Serial audio interface (SAI) 39.3.10 RM0351 SPDIF output The SPDIF interface is available in transmitter mode only. It supports the audio IEC60958. To select SPDIF mode, set PRTCFG[1:0] bit to 01 in the SAI_xCR1 register. For SPDIF protocol: • Only SD data line is enabled. • FS, SCK, MCLK I/Os pins are left free. • MODE[1] bit is forced to 0 to select the master mode in order to enable the clock generator of the SAI and manage the data rate on the SD line. • The data size is forced to 24 bits. The value set in DS[2:0] bits in the SAI_xCR1 register is ignored. • The clock generator must be configured to define the symbol-rate, knowing that the bit clock should be twice the symbol-rate. The data is coded in Manchester protocol. • The SAI_xFRCR and SAI_xSLOTR registers are ignored. The SAI is configured internally to match the SPDIF protocol requirements as shown in Figure 440. Figure 440. SPDIF format "LOCK . "LOCK . &RAME &RAME &RAME &RAME 6XEIUDPH % &KDQQHO$ : &KDQQHO% 0 &KDQQHO$ : &KDQQHO% 623' 3/0$ " - 7 '' '' 0 &KDQQHO$ : &KDQQHO% % '' ' '' 93 BIT DATA 8 &KDQQHO$ : &KDQQHO% &6 3TATUS BIT #HANNEL -36 A SPDIF block contains 192 frames. Each frame is composed of two 32-bit sub-frames, generally one for the left channel and one for the right channel. Each sub-frame is composed of a SOPD pattern (4-bit) to specify if the sub-frame is the start of a block (and so is identifying a channel A) or if it is identifying a channel A somewhere in the block, or if it is referring to channel B (see Table 207). The next 28 bits of channel information are composed of 24 bits data + 4 status bits. 1324/1680 DocID024597 Rev 1 RM0351 Serial audio interface (SAI) Table 207. SOPD pattern Preamble coding SOPD Description last bit is 0 last bit is 1 B 11101000 00010111 Channel A data at the start of block W 11100100 00011011 Channel B data somewhere in the block M 11100010 00011101 Channel A data The data stored in SAI_xDR has to be filled as follows: • SAI_xDR[26:24] contain the Channel status, User and Validity bits. • SAI_xDR[23:0] contain the 24-bit data for the considered channel. If the data size is 20 bits, then data shall be mapped on SAI_xDR[23:4]. If the data size is 16 bits, then data shall be mapped on SAI_xDR[23:8]. SAI_xDR[23] always represents the MSB. Figure 441. SAI_xDR register ordering 6$,B['5>@ &6 8 9 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 'DWD>@ 6WDWXV ELWV 06Y9 Note: The transfer is performed always with LSB first. The SAI first sends the adequate preamble for each sub-frame in a block. The SAI_xDR is then sent on the SD line (manchester coded). The SAI ends the sub-frame by transferring the Parity bit calculated as described in Table 208. Table 208. Parity bit calculation SAI_xDR[26:0] Parity bit P value transferred odd number of 0 0 odd number of 1 1 The underrun is the only error flag available in the SAI_xSR register for SPDIF mode since the SAI can only operate in transmitter mode. As a result, the following sequence should be DocID024597 Rev 1 1325/1680 1353 Serial audio interface (SAI) RM0351 executed to recover from an underrun error detected via the underrun interrupt or the underrun status bit: 1. Disable the DMA stream (via the DMA peripheral) if the DMA is used. 2. Disable the SAI and check that the peripheral is physically disabled by polling the SAIXEN bit in SAI_xCR1 register. 3. Clear the COVRUNDR flag in the SAI_xCLRFR register. 4. Flush the FIFO by setting the FFLUSH bit in SAI_xCR2. The software needs to point to the address of the future data corresponding to a start of new block (data for preamble B). If the DMA is used, the DMA source base address pointer should be updated accordingly. 5. Enable again the DMA stream (DMA peripheral) if the DMA used to manage data transfers according to the new source base address. 6. Enable again the SAI by setting SAIXEN bit in SAI_xCR1 register. Clock generator programming in SPDIF generator mode For the SPDIF generator, the SAI shall provide a bit clock equal to the symbol-rate. The table hereafter shows usual examples of symbol rates with respect to the audio sampling rate. Table 209. Audio sampling frequency versus symbol rates (SHARK) Audio Sampling Frequencies (FS) Symbol-rate 44.1 kHz 2.8224 MHz 48 kHz 3.072 MHz 96 kHz 6.144 MHz 192 kHz 12.288 MHz More generally, the relationship between the audio sampling rate (FS) and the bit-clock rate (FSCK_X) is given by the formula: F SAI_CK_x F S = ------------------------64 39.3.11 Specific features The SAI interface embeds specific features which can be useful depending on the audio protocol selected. These functions are accessible through specific bits of the SAI_xCR2 register. Mute mode The mute mode can be used when the audio sub-block is a transmitter or a receiver. Audio sub-block in transmission mode In transmitter mode, the mute mode can be selected at anytime. The mute mode is active for entire audio frames. The MUTE bit in the SAI_xCR2 register enables the mute mode when it is set during an ongoing frame. 1326/1680 DocID024597 Rev 1 RM0351 Serial audio interface (SAI) The mute mode bit is strobed only at the end of the frame. If it is set at this time, the mute mode is active at the beginning of the new audio frame and for a complete frame, until the next end of frame. The bit is then strobed to determine if the next frame will still be a mute frame. If the number of slots set through NBSLOT[3:0] bits in the SAI_xSLOTR register is lower than or equal to 2, it is possible to specify if the value sent in mute mode is 0 or if it is the last value of each slot. The selection is done via MUTEVAL bit in the SAI_xCR2 register. If the number of slots set in NBSLOT[3:0] bits in the SAI_xSLOTR register is greater than 2, MUTEVAL bit in the SAI_xCR2 is meaningless as 0 values are sent on each bit on each slot. The FIFO pointers are still incremented in mute mode. This means that data present in the FIFO and for which the mute mode is requested are discarded. Audio sub-block in reception mode In reception mode, it is possible to detect a mute mode sent from the external transmitter when all the declared and valid slots of the audio frame receive 0 for a given consecutive number of audio frames (MUTECNT[5:0] bits in the SAI_xCR2 register). When the number of MUTE frames is detected, the MUTEDET flag in the SAI_xSR register is set and an interrupt can be generated if MUTEDETIE bit is set in SAI_xCR2. The mute frame counter is cleared when the audio sub-block is disabled or when a valid slot receives at least one data in an audio frame. The interrupt is generated just once, when the counter reaches the value specified in MUTECNT[5:0] bits. The interrupt event is then reinitialized when the counter is cleared. Note: The mute mode is not available for SPDIF audio blocks. Mono/stereo mode In transmitter mode, the mono mode can be addressed, without any data pre-processing in memory, assuming the number of slots is equal to 2 (NBSLOT[3:0] = 0001 in SAI_xSLOTR). In this case, the access time to and from the FIFO will be reduced by 2 since the data for slot 0 is duplicated into data slot 1. To enable the mono mode, 1. Set MONO bit to 1 in the SAI_xCR1 register. 2. Set NBSLOT to 1 and SLOTEN to 3 in SAI_xSLOTR. In reception mode, the MONO bit can be set and is meaningful only if the number of slots is equal to 2 as in transmitter mode. When it is set, only slot 0 data will be stored in the FIFO. The data belonging to slot 1 will be discarded since, in this case, it is supposed to be the same as the previous slot. If the data flow in reception mode is a real stereo audio flow with a distinct and different left and right data, the MONO bit is meaningless. The conversion from the output stereo file to the equivalent mono file is done by software. Companding mode Telecommunication applications can require to process the data to be transmitted or received using a data companding algorithm. Depending on the COMP[1:0] bits in the SAI_xCR2 register (used only when TDM mode is selected), the application software can choose to process or not the data before sending it on SD serial output line (compression) or to expand the data after the reception on SD serial DocID024597 Rev 1 1327/1680 1353 Serial audio interface (SAI) RM0351 input line (expansion) as illustrated in Figure 442. The two companding modes supported are the µ-Law and the A-Law log which are a part of the CCITT G.711 recommendation. The companding standard used in the United States and Japan is the µ-Law. It supports 14 bits of dynamic range (COMP[1:0] = 10 in the SAI_xCR2 register). The European companding standard is A-Law and supports 13 bits of dynamic range (COMP[1:0] = 11 in the SAI_xCR2 register). Both µ-Law or A-Law companding standard can be computed based on 1’s complement or 2’s complement representation depending on the CPL bit setting in the SAI_xCR2 register. In µ-Law and A-Law standards, data are coded as 8 bits with MSB alignment. Companded data are always 8-bit wide. For this reason, DS[2:0] bits in the SAI_xCR1 register will be forced to 010 when the SAI audio block is enabled (bit SAIXEN = 1 in the SAI_xCR1 register) and when one of these two companding modes selected through the COMP[1:0] bits. If no companding processing is required, COMP[1:0] bits should be kept clear. Figure 442. Data companding hardware in an audio block in the SAI 5HFHLYHUPRGH ELW02'(>@ LQ6$,B[&5 &203>@ ),)2 6' H[SDQG ELWVKLIWUHJLVWHU 7UDQVPLWWHUPRGH ELW02'(>@ LQ6$,B[&5 ),)2 FRPSUHVV 6' ELWVKLIWUHJLVWHU &203>@ 069 1. Not applicable when AC’97 or SPDIF are selected. Expansion and compression mode are automatically selected through the SAI_xCR2: • If the SAI audio block is configured to be a transmitter, and if the COMP[1] bit is set in the SAI_xCR2 register, the compression mode will be applied. • If the SAI audio block is declared as a receiver, the expansion algorithm will be applied. Output data line management on an inactive slot In transmitter mode, it is possible to choose the behavior of the SD line output when an inactive slot is sent on the data line (via TRIS bit). 1328/1680 • Either the SAI forces 0 on the SD output line when an inactive slot is transmitted, or • The line is released in HI-z state at the end of the last bit of data transferred, to release the line for other transmitters connected to this node. DocID024597 Rev 1 RM0351 Serial audio interface (SAI) It is important to note that the two transmitters cannot attempt to drive the same SD output pin simultaneously, which could result in a short circuit. To ensure a gap between transmissions, if the data is lower than 32-bit, the data can be extended to 32-bit by setting bit SLOTSZ[1:0] = 10 in the SAI_xSLOTR register. The SD output pin will then be tri-stated at the end of the LSB of the active slot (during the padding to 0 phase to extend the data to 32-bit) if the following slot is declared inactive. In addition, if the number of slots multiplied by the slot size is lower than the frame length, the SD output line will be tri-stated when the padding to 0 is done to complete the audio frame. Figure 443 illustrates these behaviors. DocID024597 Rev 1 1329/1680 1353 Serial audio interface (SAI) RM0351 Figure 443. Tristate strategy on SD output line on an inactive slot %LW75,6 LQWKH6$,B[&5DQGIUDPHOHQJWK QXPEHURIVORWV $XGLRIUDPH SCK 6ORWVL]H GDWDVL]H 3LOT /. VORW 6' RXWSXW 3LOT /&& 3LOT /&& $ATA 3LOT /. $ATA /. /. 3LOT N /. $ATA M 6ORWVL]H!GDWDVL]H VORW 3LOT /. 6' RXWSXW VORW 3LOT /&& 3LOT /&& $ATA $ATA 3LOT /. 3LOT /. 3LOT /&& 3LOT /&& 6' RXWSXW 3LOT /. $ATA /. /. /. /. 3LOT N /. $ATA M 3LOT N /. $ATA M %LW75,6 LQWKH6$,B[&5DQGIUDPHOHQJWK!QXPEHURIVORWV $XGLRIUDPH SCK 6ORWVL]H GDWDVL]H VORW 6' RXWSXW 3LOT /. 3LOT /&& 3LOT /&& $ATA /. 3LOT N /. $ATA M 6ORWVL]H!GDWDVL]H VORW 6' RXWSXW VORW 6' RXWSXW 3LOT /. 3LOT /&& 3LOT /&& $ATA 3LOT /. /. 3LOT /&& 3LOT /&& /. 3LOT N /. $ATA M /. $ATA M 069 When the selected audio protocol uses the FS signal as a start of frame and a channel side identification (bit FSDEF = 1 in the SAI_xFRCR register), the tristate mode is managed according to Figure 444 (where bit TRIS in the SAI_xCR1 register = 1, and FSDEF=1, and half frame length is higher than number of slots/2, and NBSLOT=6). 1330/1680 DocID024597 Rev 1 RM0351 Serial audio interface (SAI) Figure 444. Tristate on output data line in a protocol like I2S SCK 6ORWVL]H GDWDVL]H VORW 3LOT /. 6' RXWSXW 3LOT /&& $ATA 3LOT /. 3LOT /. $ATA $ATA 3LOT /&& 3LOT /. $ATA 6ORWVL]H!GDWDVL]H 3LOT /. VORW 6' RXWSXW 3LOT /&& $ATA 3LOT /. VORW 6' RXWSXW $ATA 3LOT /. $ATA 3LOT /&& 3LOT /. 3LOT /. 3LOT /&& $ATA 3LOT /. $ATA 3LOT /. $ATA 3LOT /&& 3LOT /. $ATA M 069 If the TRIS bit in the SAI_xCR2 register is cleared, all the High impedance states on the SD output line on Figure 443 and Figure 444 are replaced by a drive with a value of 0. 39.3.12 Error flags The SAI implements the following error flags: • FIFO overrun/underrun • Anticipated frame synchronization detection • Late frame synchronization detection • Codec not ready (AC’97 exclusively) • Wrong clock configuration in master mode. FIFO overrun/underrun (OVRUDR) The FIFO overrun/underrun bit is called OVRUDR in the SAI_xSR register. The overrun or underrun errors share the same bit since an audio block can be either receiver or transmitter and each audio block in a given SAI has its own SAI_xSR register. Overrun When the audio block is configured as receiver, an overrun condition may appear if data are received in an audio frame when the FIFO is full and not able to store the received data. In this case, the received data are lost, the flag OVRUDR in the SAI_xSR register is set and an interrupt is generated if OVRUDRIE bit is set in the SAI_xIM register. The slot number, from which the overrun occurs, is stored internally. No more data will be stored into the FIFO until it becomes free to store new data. When the FIFO has at least one data free, the SAI audio block receiver will store new data (from new audio frame) from the slot number which was stored internally when the overrun condition was detected. This avoids data slot dealignment in the destination memory (refer to Figure 445). DocID024597 Rev 1 1331/1680 1353 Serial audio interface (SAI) RM0351 The OVRUDR flag is cleared when COVRUDR bit is set in the SAI_xCLRFR register. Figure 445. Overrun detection error ([DPSOH),)2RYHUUXQRQ6ORW $XGLRIUDPH $XGLRIUDPH VFN GDWD 6ORW21 6ORW21 3LOT /. 6ORW21 6ORW21 21 6ORWQ21 ),)2IXOO 'DWDVWRUHGDJDLQLQ),)2 5HFHLYHGGDWDGLVFDUGHG 2958'5 &2958'5 069 Underrun An underrun may occur when the audio block in the SAI is a transmitter and the FIFO is empty when data need to be transmitted. If an underrun is detected, the slot number for which the event occurs is stored and MUTE value (00) is sent until the FIFO is ready to transmit the data corresponding to the slot for which the underrun was detected (refer to Figure 446). This avoids desynchronization between the memory pointer and the slot in the audio frame. The underrun event sets the OVRUDR flag in the SAI_xSR register and an interrupt is generated if the OVRUDRIE bit is set in the SAI_xIM register. To clear this flag, set COVRUDR bit in the SAI_xCLRFR register. The underrun event can occur when the audio sub-block is configured as master or slave. Figure 446. FIFO underrun event ([DPSOH),)2XQGHUUXQRQ6ORW $XGLRIUDPH $XGLRIUDPH VFN 3LOT SIZE DATA SIZE GDWD 6' RXWSXW 6ORW21 087( 087( 087( 6ORW21 21 6ORW21 ),)2HPSW\ 29581' 29581' -36 1332/1680 DocID024597 Rev 1 RM0351 Serial audio interface (SAI) Anticipated frame synchronization detection (AFSDET) The AFSDET flag is used only in slave mode. It is never asserted in master mode. It indicates that a frame synchronization (FS) has been detected earlier than expected since the frame length, the frame polarity, the frame offset are defined and known. Anticipated frame detection sets the AFSDET flag in the SAI_xSR register. This detection has no effect on the current audio frame which is not sensitive to the anticipated FS. This means that “parasitic” events on signal FS are flagged without any perturbation of the current audio frame. An interrupt is generated if the AFSDETIE bit is set in the SAI_xIM register. To clear the AFSDET flag, CAFSDET bit must be set in the SAI_xCLRFR register. To resynchronize with the master after an anticipated frame detection error, four steps are required: Note: 1. Disable the SAI block by resetting SAIXEN bit in SAI_xCR1 register. To make sure the SAI is disabled, read back the SAIXEN bit and check it is set to 0. 2. Flush the FIFO via FFLUS bit in SAI_xCR2 register. 3. Enable again the SAI peripheral (SAIXEN bit set to 1). 4. The SAI block will wait for the assertion on FS to restart the synchronization with master. The SAIXEN flag is not asserted in AC’97 mode since the SAI audio block acts as a link controller and generates the FS signal even when declared as slave. It has no meaning in SPDIF mode since the FS signal is not used. Late frame synchronization detection The LFSDET flag in the SAI_xSR register can be set only when the SAI audio block operates as a slave. The frame length, the frame polarity and the frame offset configuration are known in register SAI_xFRCR. If the external master does not send the FS signal at the expecting time thus generating the signal too late, the LFSDET flag is set and an interrupt is generated if LFSDETIE bit is set in the SAI_xIM register. The LFSDET flag is cleared when CLFSDET bit is set in the SAI_xCLRFR register. The late frame synchronization detection flag is set when the corresponding error is detected. The SAI needs to be resynchronized with the master (see sequence described in Section : Anticipated frame synchronization detection (AFSDET)). In a noisy environment, glitches on the SCK clock may be wrongly detected by the audio block state machine and shift the SAI data at a wrong frame position. This event can be detected by the SAI and reported as a late frame synchronization detection error. There is no corruption if the external master is not managing the audio data frame transfer in continuous mode, which should not be the case in most applications. In this case, the LFSDET flag will be set. Note: The LFSDET flag is not asserted in AC’97 mode since the SAI audio block acts as a link controller and generates the FS signal even when declared as slave. It has no meaning in SPDIF mode since the signal FS is not used by the protocol. DocID024597 Rev 1 1333/1680 1353 Serial audio interface (SAI) RM0351 Codec not ready (CNRDY AC’97) The CNRDY flag in the SAI_xSR register is relevant only if the SAI audio block is configured to operate in AC’97 mode (PRTCFG[1:0] = 10 in the SAI_xCR1 register). If CNRDYIE bit is set in the SAI_xIM register, an interrupt is generated when the CNRDY flag is set. CNRDY is asserted when the Codec is not ready to communicate during the reception of the TAG 0 (slot0) of the AC’97 audio frame. In this case, no data will be automatically stored into the FIFO since the Codec is not ready, until the TAG 0 indicates that the Codec is ready. All the active slots defined in the SAI_xSLOTR register will be captured when the Codec is ready. To clear CNRDY flag, CCNRDY bit must be set in the SAI_xCLRFR register. Wrong clock configuration in master mode (with NODIV = 0) When the audio block operates as a master (MODE[1] = 0) and NODIV bit is equal to 0, the WCKCFG flag is set as soon as the SAI is enabled if the following conditions are met: • (FRL+1) is not a power of 2, and • (FRL+1) is not between 8 and 256. MODE, NODIV, and SAIXEN bits belong to SAI_xCR1 register and FRL to SAI_xFRCR register. If WCKCFGIE bit is set, an interrupt is generated when WCKCFG flag is set in the SAI_xSR register. To clear this flag, set CWCKCFG bit in the SAI_xCLRFR register. When WCKCFG bit is set, the audio block is automatically disabled, thus performing a hardware clear of SAIXEN bit. 39.3.13 Disabling the SAI The SAI audio block can be disabled at any moment by clearing SAIXEN bit in the SAI_xCR1 register. All the already started frames are automatically completed before the SAI is stops working. SAIXEN bit remains High until the SAI is completely switched-off at the end of the current audio frame transfer. If an audio block in the SAI operates synchronously with the other one, the one which is the master must be disabled first. 39.3.14 SAI DMA interface To free the CPU and to optimize bus bandwidth, each SAI audio block has an independent DMA interface to read/write from/to the SAI_xDR register (to access the internal FIFO). There is one DMA channel per audio sub-block supporting basic DMA request/acknowledge protocol. To configure the audio sub-block for DMA transfer, set DMAEN bit in the SAI_xCR1 register. The DMA request is managed directly by the FIFO controller depending on the FIFO threshold level (for more details refer to Section 39.3.8: Internal FIFOs). DMA transfer direction is linked to the SAI audio sub-block configuration: 1334/1680 • If the audio block operates as a transmitter, the audio block FIFO controller outputs a DMA request to load the FIFO with data written in the SAI_xDR register. • If the audio block is operates as a receiver, the DMA request is related to read operations from the SAI_xDR register. DocID024597 Rev 1 RM0351 Serial audio interface (SAI) Follow the sequence below to configure the SAI interface in DMA mode: Note: 1. Configure SAI and FIFO threshold levels to specify when the DMA request will be launched. 2. Configure SAI DMA channel. 3. Enable the DMA. 4. Enable the SAI interface. Before configuring the SAI block, the SAI DMA channel must be disabled. DocID024597 Rev 1 1335/1680 1353 Serial audio interface (SAI) 39.4 RM0351 SAI interrupts The SAI supports 7 interrupt sources as shown in Table 210. Table 210. SAI interrupt sources Interrupt source Interrupt group Audio block mode Interrupt enable Interrupt clear Depends on: FREQ FREQ – FIFO threshold setting (FLTH bits in SAI_xCR2) FREQIE in SAI_xIM – Communication direction (transmitter register or receiver) Master or slave Receiver or transmitter For more details refer to Section 39.3.8: Internal FIFOs OVRUDR ERROR Master or slave Receiver or transmitter OVRUDRIE in SAI_xIM register COVRUDR = 1 in SAI_xCLRFR register AFSDET ERROR Slave (not used in AC’97 mode and SPDIF mode) AFSDETIE in SAI_xIM register CAFSDET = 1 in SAI_xCLRFR register LFSDET ERROR Slave (not used in AC’97 mode and SPDIF mode) LFSDETIE in SAI_xIM register CLFSDET = 1 in SAI_xCLRFR register CNRDY ERROR Slave (only in AC’97 mode) CNRDYIE in SAI_xIM register CCNRDY = 1 in SAI_xCLRFR register MUTEDET MUTE Master or slave Receiver mode only MUTEDETIE in SAI_xIM register CMUTEDET = 1 in SAI_xCLRFR register WCKCFG ERROR Master with NODIV = 0 in SAI_xCR1 register WCKCFGIE in SAI_xIM register CWCKCFG = 1 in SAI_xCLRFR register Follow the sequence below to enable an interrupt: 1336/1680 1. Disable SAI interrupt. 2. Configure SAI. 3. Configure SAI interrupt source. 4. Enable SAI. DocID024597 Rev 1 RM0351 Serial audio interface (SAI) 39.5 SAI registers 39.5.1 Global configuration register (SAI_GCR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYNCOUT[1:0] rw rw SYNCIN[1:0] rw rw Bits 31:6 Reserved, always read as 0. Bits 5:4 SYNCOUT[1:0]: Synchronization outputs These bits are set and cleared by software. 00: No synchronization output signals. SYNCOUT[1:0] should be configured as No synchronization output signals when audio block is configured as SPDIF 01: Block A used for further synchronization for others SAI 10: Block B used for further synchronization for others SAI 11: Reserved. These bits must be set when both audio block (A and B) are disabled. Bits 3:2 Reserved, always read as 0. Bits 1:0 SYNCIN[1:0]: Synchronization inputs These bits are set and cleared by software. Please refer to for information on how to program this field. These bits must be set when both audio blocks (A and B) are disabled. They are meaningful if one of the two audio block is defined to operate in synchronous mode with an external SAI (SYNCEN[1:0] = 01 in SAI_ACR1 or in SAI_BCR1 registers). 39.5.2 Configuration register 1 (SAI_ACR1 / SAI_BCR1) Address offset: Block A: 0x004 Address offset: Block B: 0x024 Reset value: 0x0000 0040 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. OUTD MONO RIV rw rw SYNCEN[1:0] rw rw 23 rw 21 20 MCKDIV[3:0] 19 NODIV rw rw rw rw rw 7 6 5 4 3 CKSTR LSBFIRST rw 22 DS[2:0] rw rw DocID024597 Rev 1 Res. rw 18 Res. 2 17 16 DMAEN SAIX EN rw rw 1 0 PRTCFG[1:0] MODE[1:0] rw rw rw rw 1337/1680 1353 Serial audio interface (SAI) RM0351 Bits 31:24 Reserved, always read as 0. Bits 23:20 MCKDIV[3:0]: Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. 0000: Divides by 1 the master clock input. Others: the master clock frequency is calculated accordingly to the following formula: F SAI_CK_x F SCK_x = ----------------------------------MCKDIV × 2 Bit 19 NODIV: No divider. This bit is set and cleared by software. 0: Master clock generator is enabled 1: No divider used in the clock generator (in this case Master Clock Divider bit has no effect) Bit 18 Reserved, always read as 0. Bit 17 DMAEN: DMA enable. This bit is set and cleared by software. 0: DMA disabled 1: DMA enabled Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. Bit 16 SAIXEN: Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. 0: SAIx audio block disabled 1: SAIx audio block enabled. Note: When SAIx block is configured in master mode, the kernel clock must be present on the input of SAIx before setting SAIXEN bit. Bits 15:14 Reserved, always read as 0. Bit 13 OUTDRIV: Output drive. This bit is set and cleared by software. 0: Audio block output driven when SAIXEN is set 1: Audio block output driven immediately after the setting of this bit. Note: This bit has to be set before enabling the audio block and after the audio block configuration. Bit 12 MONO: Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section : Mono/stereo mode for more details. 0: Stereo mode 1: Mono mode. 1338/1680 DocID024597 Rev 1 RM0351 Serial audio interface (SAI) Bits 11:10 SYNCEN[1:0]: Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. 00: audio sub-block in asynchronous mode. 01: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode 10: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode. 11: Reserved Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. Bit 9 CKSTR: Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. 0: Signals generated by the SAI change on SCK rising edge, while signals received by the SAI are sampled on the SCK falling edge. 1: Signals generated by the SAI change on SCK falling edge, while signals received by the SAI are sampled on the SCK rising edge. Bit 8 LSBFIRST: Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC’97 audio protocol since AC’97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. 0: Data are transferred with MSB first 1: Data are transferred with LSB first Bits 7:5 DS[2:0]: Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. 000: Reserved 001: Reserved 010: 8 bits 011: 10 bits 100: 16 bits 101: 20 bits 110: 24 bits 111: 32 bits DocID024597 Rev 1 1339/1680 1353 Serial audio interface (SAI) RM0351 Bit 4 Reserved, always read as 0. Bits 3:2 PRTCFG[1:0]: Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. 00: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol (such as I2S, LSB/MSB justified, TDM, PCM/DSP...) by setting most of the configuration register bits as well as frame configuration register. 01: SPDIF protocol 10: AC’97 protocol 11: Reserved Bits 1:0 MODE[1:0]: SAIx audio block mode. These bits are set and cleared by software. They must be configured when SAIx audio block is disabled. 00: Master transmitter 01: Master receiver 10: Slave transmitter 11: Slave receiver Note: When the audio block is configured in SPDIF mode, the master transmitter mode is forced (MODE[1:0] = 00). In Master transmitter mode, the audio block starts generating the FS and the clocks immediately. 1340/1680 DocID024597 Rev 1 RM0351 Serial audio interface (SAI) 39.5.3 Configuration register 2 (SAI_ACR2 / SAI_BCR2) Address offset: Block A: 0x008 Address offset: Block B: 0x028 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MUTE VAL MUTE TRIS FFLUS H rw rw rw w COMP[1:0] rw rw CPL rw MUTECNT[5:0] rw rw rw rw rw rw FTH rw rw rw Bits 31:16 Reserved, always read as 0 Bits 15:14 COMP[1:0]: Companding mode. These bits are set and cleared by software. The µ-Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section : Companding mode for more details. 00: No companding algorithm 01: Reserved. 10: µ-Law algorithm 11: A-Law algorithm Note: Companding mode is applicable only when TDM is selected. Bit 13 CPL: Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode 0: 1’s complement representation. 1: 2’s complement representation. Note: This bit has effect only when the companding mode is µ-Law algorithm or A-Law algorithm. Bits 12:7 MUTECNT[5:0]: Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section : Mute mode for more details. DocID024597 Rev 1 1341/1680 1353 Serial audio interface (SAI) RM0351 Bit 6 MUTEVAL: Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section : Mute mode for more details. 0: Bit value 0 is sent during the mute mode. 1: Last values are sent during the mute mode. Note: This bit is meaningless and should not be used for SPDIF audio blocks. Bit 5 MUTE: Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section : Mute mode for more details. 0: No mute mode. 1: Mute mode enabled. Note: This bit is meaningless and should not be used for SPDIF audio blocks. Bit 4 TRIS: Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section : Output data line management on an inactive slot for more details. 0: SD output line is still driven by the SAI when a slot is inactive. 1: SD output line is released (HI-Z) at the end of the last data bit of the last active slot if the next one is inactive. Bit 3 FFLUSH: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. 0: No FIFO flush. 1: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared. In this case data still present in the FIFO are lost (no more transmission or received data lost). Before flushing SAI, DMA stream/interruption must be disabled Bits 2:0 FTH: FIFO threshold. This bit is set and cleared by software. 000: FIFO empty 001: ¼ FIFO 010: ½ FIFO 011: ¾ FIFO 100: FIFO full 101: Reserved 110: Reserved 111: Reserved 1342/1680 DocID024597 Rev 1 RM0351 Serial audio interface (SAI) 39.5.4 Frame configuration register (SAI_AFRCR / SAI_BFRCR) Address offset: Block A: 0x00C Address offset: Block B: 0x02C Reset value: 0x0000 0007 Note: This register has no meaning in AC’97 and SPDIF audio protocol 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw Res. FSALL[6:0] rw rw rw rw rw 18 17 16 FSOFF FSPOL FSDEF FRL[7:0] rw rw rw rw rw rw Bits 31:19 Reserved, always read as 0. Bit 18 FSOFF: Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC’97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 0: FS is asserted on the first bit of the slot 0. 1: FS is asserted one bit before the first bit of the slot 0. Bit 17 FSPOL: Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC’97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 0: FS is active low (falling edge) 1: FS is active high (rising edge) Bit 16 FSDEF: Frame synchronization definition. This bit is set and cleared by software. 0: FS signal is a start frame signal 1: FS signal is a start of frame signal + channel side identification When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC’97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. DocID024597 Rev 1 1343/1680 1353 Serial audio interface (SAI) RM0351 Bit 15 Reserved, always read as 0. Bits 14:8 FSALL[6:0]: Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC’97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. Bits 7:0 FRL[7:0]: Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC’97 or SPDIF audio block configuration. 1344/1680 DocID024597 Rev 1 RM0351 Serial audio interface (SAI) 39.5.5 Slot register (SAI_ASLOTR / SAI_BSLOTR) Address offset: Block A: 0x010 Address offset: Block B: 0x030 Reset value: 0x0000 0000 Note: 31 This register has no meaning in AC’97 and SPDIF audio protocol 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SLOTEN[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. rw rw NBSLOT[3:0] rw rw rw SLOTSZ[1:0] rw rw rw Res. FBOFF[4:0] rw rw rw Bits 31:16 SLOTEN[15:0]: Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). 0: Inactive slot. 1: Active slot. The slot must be enabled when the audio block is disabled. They are ignored in AC’97 or SPDIF mode. Bits 15:12 Reserved, always read as 0. Bits 11:8 NBSLOT[3:0]: Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC’97 or SPDIF mode. DocID024597 Rev 1 1345/1680 1353 Serial audio interface (SAI) RM0351 Bits 7:6 SLOTSZ[1:0]: Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section : Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC’97 or SPDIF mode. 00: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register). 01: 16-bit 10: 32-bit 11: Reserved Bit 1 Reserved, always read as 0. Bits 4:0 FBOFF[4:0]: First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC’97 or SPDIF mode. 1346/1680 DocID024597 Rev 1 RM0351 39.5.6 Serial audio interface (SAI) Interrupt mask register 2 (SAI_AIM / SAI_BIM) Address offset: block A: 0x014 Address offset: block B: 0x034 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. LFSDET AFSDET CNRDY FREQ WCKCFG MUTEDET OVRUDR IE IE IE IE IE IE IE rw rw rw rw rw rw rw Bits 31:7 Reserved, always read as 0. Bit 6 LFSDETIE: Late frame synchronization detection interrupt enable. This bit is set and cleared by software. 0: Interrupt is disabled 1: Interrupt is enabled When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC’97, SPDIF mode or when the audio block operates as a master. Bit 5 AFSDETIE: Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. 0: Interrupt is disabled 1: Interrupt is enabled When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC’97, SPDIF mode or when the audio block operates as a master. Bit 4 CNRDYIE: Codec not ready interrupt enable (AC’97). This bit is set and cleared by software. 0: Interrupt is disabled 1: Interrupt is enabled When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC’97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC’97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. Bit 3 FREQIE: FIFO request interrupt enable. This bit is set and cleared by software. 0: Interrupt is disabled 1: Interrupt is enabled When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, DocID024597 Rev 1 1347/1680 1353 Serial audio interface (SAI) RM0351 Bit 2 WCKCFGIE: Wrong clock configuration interrupt enable. This bit is set and cleared by software. 0: Interrupt is disabled 1: Interrupt is enabled This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. Bit 1 MUTEDETIE: Mute detection interrupt enable. This bit is set and cleared by software. 0: Interrupt is disabled 1: Interrupt is enabled When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. Bit 0 OVRUDRIE: Overrun/underrun interrupt enable. This bit is set and cleared by software. 0: Interrupt is disabled 1: Interrupt is enabled When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. 1348/1680 DocID024597 Rev 1 RM0351 39.5.7 Serial audio interface (SAI) Status register (SAI_ASR / SAI_BSR) Address offset: block A: 0x018 Address offset: block B: 0x038 Reset value: 0x0000 0008 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. LFSDET AFSDET CNRDY r r r FREQ r 18 17 16 FLTH r r r 2 1 0 WCKCFG MUTEDET OVRUDR r r r Bits 31:19 Reserved, always read as 0. Bits 18:16 FLTH: FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: 000: FIFO empty 001: FIFO <= ¼ but not empty 010: ¼ < FIFO <= ½ 011: ½ < FIFO <= ¾ 100: ¾ < FIFO but not full 101: FIFO full If SAI block is configured as receiver: 000: FIFO empty 001: FIFO < ¼ but not empty 010: ¼ <= FIFO < ½ 011: ½ =< FIFO < ¾ 100: ¾ =< FIFO but not full 101: FIFO full Bits 15:7 Reserved, always read as 0. Bit 6 LFSDET: Late frame synchronization detection. This bit is read only. 0: No error. 1: Frame synchronization signal is not present at the right time. This flag can be set only if the audio block is configured in slave mode. It is not used in AC’97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register Bit 5 AFSDET: Anticipated frame synchronization detection. This bit is read only. 0: No error. 1: Frame synchronization signal is detected earlier than expected. This flag can be set only if the audio block is configured in slave mode. It is not used in AC’97 or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. DocID024597 Rev 1 1349/1680 1353 Serial audio interface (SAI) RM0351 Bit 4 CNRDY: Codec not ready. This bit is read only. 0: External AC’97 Codec is ready 1: External AC’97 Codec is not ready This bit is used only when the AC’97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. Bit 3 FREQ: FIFO request. This bit is read only. 0: No FIFO request. 1: FIFO request to read or to write the SAI_xDR. The request depends on the audio block configuration: – If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. – If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. Bit 2 WCKCFG: Wrong clock configuration flag. This bit is read only. 0: Clock configuration is correct 1: Clock configuration does not respect the rule concerning the frame length specification defined in Section 39.3.5: Frame synchronization (configuration of FRL[7:0] bit in the SAI_xFRCR register) This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. Bit 1 MUTEDET: Mute detection. This bit is read only. 0: No MUTE detection on the SD input line 1: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. Bit 0 OVRUDR: Overrun / underrun. This bit is read only. 0: No overrun/underrun error. 1: Overrun/underrun error detection. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. 1350/1680 DocID024597 Rev 1 RM0351 39.5.8 Serial audio interface (SAI) Clear flag register (SAI_ACLRFR / SAI_BCLRFR) Address offset: block A: 0x01C Address offset: block B: 0x03C Reset value: 0x0000 0000 31 Res. 15 Res. 30 29 28 27 26 Res. Res. Res. Res. Res. 14 13 12 11 10 Res. Res. Res. Res. Res. 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. CCNRDY Res. CWCKCFG CLFSDET CAFSDET w w w w CMUTE COVRUD DET R w w Bits 31:7 Reserved, always read as 0. Bit 6 CLFSDET: Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC’97 or SPDIF mode Reading this bit always returns the value 0. Bit 5 .CAFSDET: Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC’97 or SPDIF mode. Reading this bit always returns the value 0. Bit 4 CCNRDY: Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC’97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. Bit 3 Reserved, always read as 0. Bit 2 CWCKCFG: Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. Bit 1 CMUTEDET: Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. Bit 0 COVRUDR: Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. DocID024597 Rev 1 1351/1680 1353 Serial audio interface (SAI) 39.5.9 RM0351 Data register (SAI_ADR / SAI_BDR) Address offset: block A: 0x020 Address offset: block B: 0x040 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DATA[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 DATA[31:0]: Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. 39.5.10 SAI register map The following table summarizes the SAI registers. 1352/1680 FSDEF 0 0 0 DocID024597 Rev 1 0 0 0 0 0 0 0 0 0 SYNCIN[1:0] Reserved Reserved. 0 0 0 0 0 MODE[1:0] 0 0 0 0 FTH 0 FSALL[6:0] 0 PRTCFG[1:0] 1 FFLUS 0 MUTECN[5:0] 0 Reserved 0 TRIS LSBFIRST 0 DS[2:0] CKSTR 0 0 MUTE 0 0 0 MUTE VAL 0 SYNCEN[1:0] MONO 0 CPL OUTDRIV Reserved 0 Reserved FSPOL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved FSOFF Reset value Reserved SAI_xFRCR Reserved 0x000C or 0x002C 0 Reserved Reset value Reserved Reserved 0 COMP[1:0] Reserved SAIXEN Reserved 0 Reserved 0 DMAEN 0 Reserved 0 Reserved 0 Reserved NODIV MCJDIV[3:0] 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved SAI_xCR2 Reserved 0x0008 or 0x0028 Reserved Reset value Reserved Reserved Reserved Reserved Reserved Reserved Reserved SAI_xCR1 Reserved 0x0004 or 0x0024 0 Reserved Reset value SYNCOUT[1:0] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SAI_GCR 0x0000 Reserved Register and reset value Reserved Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 211. SAI register map and reset values 0 0 0 1 1 1 FRL[7:0] 0 0 0 0 0 0 0 0x001C or 0x003C 0x0020 or 0x0040 SAI_xCLRFR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 SAI_xDR 0 0 DocID024597 Rev 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVRUDR 0 MUTEDET 0 0 0 1 0 0 0 OVRUDR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved FREQIE MUTEDET OVRUDRIE Reserved WCKCFG Reserved CNRDYIE Reserved AFSDETIE Reserved LFSDET Reserved Reserved Reserved Reserved 0 MUTEDET Reserved 0 FREQ Reserved 0 WCKCFG Reserved 0 Reserved Reserved 0 WCKCFG Reserved 0 CNRDY CNRDY DATA[31:0] CAFSDET Reset value LFSDET Reserved Reset value AFSDET 0 Reserved SAI_xIM Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved Reserved 0 LFSDET 0 Reserved FLVL[2:0] Reserved Reserved Reserved Reserved Reserved Reserved 0 Reserved Reserved SLOTSZ[1:0} NBSLOT[3:0] Reserved Reserved Reserved Reserved SLOTEN[15:0] Reserved 0 Reserved Reset value Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset value Reserved SAI_xSLOTR Reserved Reserved Reserved Reserved SAI_xSR Reserved 0x0018 or 0x0038 Reserved 0x0014 or 0x0034 Reserved 0x0010 or 0x0030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register and reset value Reserved Offset Reserved RM0351 Serial audio interface (SAI) Table 211. SAI register map and reset values (continued) FBOFF[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. 1353/1680 1353 Single Wire Protocol Master Interface (SWPMI) RM0351 40 Single Wire Protocol Master Interface (SWPMI) 40.1 Introduction The Single Wire Protocol Master Interface (SWPMI) is the master interface corresponding to the Contactless front-end (CLF) defined in the ETSI TS 102 613 technical specification. The principle of the Single wire protocol (SWP) is based on the transmission of digital information in full duplex mode: • S1 signal (from Master to Slave) is transmitted by a digital modulation (L or H) in the voltage domain (refer to Figure 447: S1 signal coding), • S2 signal (from Slave to Master) is transmitted by a digital modulation (L or H) in the current domain (refer to Figure 448: S2 signal coding). Figure 447. S1 signal coding 7 7 9 /RJLFDO W 9 7 /RJLFDO DQGLGOHELW W 069 Figure 448. S2 signal coding s d ϯͬϰd s ^ϭ ϭͬϰd ^ϭ ƚ / / ^Ϯ >ŽŐŝĐĂůϭ ϭͬϰd ^Ϯ >ŽŐŝĐĂůϭ ƚ s ƚ d ϯͬϰd s ^ϭ ϭͬϰd ^ϭ ƚ ƚ / ^Ϯ ƚ / >ŽŐŝĐĂůϬ ^Ϯ ƚ >ŽŐŝĐĂůϬ ƚ D^ϯϯϯϰϯsϭ 1354/1680 DocID024597 Rev 1 RM0351 40.2 Single Wire Protocol Master Interface (SWPMI) SWPMI main features The SWPMI module main features are the following (see Figure 40.3.3: SWP bus states): • Full-duplex communication mode • Automatic SWP bus state management • Automatic handling of Start of frame (SOF) • Automatic handling of End of frame (EOF) • Automatic handling of stuffing bits • Automatic CRC-16 calculation and generation in transmission • Automatic CRC-16 calculation and checking in reception • 32-bit Transmit data register • 32-bit Receive data register • Multi software buffer mode for efficient DMA implementation and multi frame buffering • Configurable bit-rate up to 2 Mbit/s • Configurable interrupts • CRC error, underrun, overrun flags • Frame reception and transmission complete flags • Slave resume detection flag • Loopback mode for test purpose • Embedded SWPMI_IO transceiver compliant with ETSI TS 102 613 technical specification • Dedicated mode to output SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals on GPIOs, in case of external transceiver connection DocID024597 Rev 1 1355/1680 1383 Single Wire Protocol Master Interface (SWPMI) RM0351 40.3 SWPMI functional description 40.3.1 SWPMI block diagram Figure 449. SWPMI block diagram ELW$3%EXV 3&/. ,QWHUUXSW '0$UHTXHVWV +6, &RQWURO6WDWXV UHJLVWHUV 6:30,B5'5 6:30,B7'5 6:3&/. 6:30,FRUH 3&/. 6:30,B6863(1' 6:30,B5; 6:30,B7; 6:30, *3,2 *3,2 *3,2 6:30,B,2 6:3EXV 069 Refer to the bit SWPMI1SEL in Section 8.4.28: Peripherals independent clock configuration register (RCC_CCIPR) to select the SWPCLK (SWPMI core clock source). Note: In order to support the exit from Stop mode by a RESUME by slave, it is mandatory to select HSI16 for SWPCLK. If this feature is not required, PCLK1 can be selected, and SWPMI must be disabled before entering the Stop mode. 40.3.2 SWP initialization and activation The initialization and activation will set the SWPMI_IO state from low to high. The procedure is the following: 40.3.3 1. configure the SWP_CLASS bit in SWPMI_OR register according to the VDD voltage (3 V or 1.8 V), 2. configure SWPMI_IO as alternate function (refer to Section 9: General-purpose I/Os (GPIO)) to enable the SWPMI_IO transceiver, 3. wait for at least 20 microseconds, 4. set SWPACT bit in SWPMI_CR register to ACTIVATE the SWP i.e. to move from DEACTIVATED to SUSPENDED. SWP bus states The SWP bus can have the following states: DEACTIVATED, SUSPENDED, ACTIVATED. 1356/1680 DocID024597 Rev 1 RM0351 Single Wire Protocol Master Interface (SWPMI) Several transitions are possible: • ACTIVATE: transition from DEACTIVATED to SUSPENDED state, • SUSPEND: transition from ACTIVATED to SUSPENDED state, • RESUME by master: transition from SUSPENDED to ACTIVATED state initiated by the master, • RESUME by slave: transition from SUSPENDED to ACTIVATED state initiated by the slave, • DEACTIVATE: transition from SUSPENDED to DEACTIVATED state. ACTIVATE During and just after reset, the SWPMI_IO is configured in analog mode. Refer to Section 40.3.2: SWP initialization and activation to activate the SWP bus. SUSPEND The SWP bus stays in the ACTIVATED state as long as there is a communication with the slave, either in transmission or in reception. The SWP bus switches back to the SUSPENDED state as soon as there is no more transmission or reception activity, after 7 idle bits. RESUME by master Once the SWPMI is enabled, the user can request a SWPMI frame transmission. The SWPMI first sends a transition sequence and 8 idle bits (RESUME by master) before starting the frame transmission. The SWP moves from the SUSPENDED to ACTIVATED state after the RESUME by master (refer to Figure 450: SWP bus states). RESUME by slave Once the SWPMI is enabled, the SWP can also move from the SUSPENDED to ACTIVATED state if the SWPMI receives a RESUME from the slave. The RESUME by slave sets the SRF flag in the SWPMI_ISR register. DEACTIVATE Deactivate request If no more communication is required, and if SWP is in the SUSPENDED mode, the user can request to switch the SWP to the DEACTIVATED mode by disabling the SWPMI peripheral. The software must set DEACT bit in the SWPMI_CR register in order to request the DEACTIVATED mode. If no RESUME by slave is detected by SWPMI, the DEACTF flag is set in the SWPMI_ISR register and the SWPACT bit is cleared in the SWPMI_ICR register. In case a RESUME by slave is detected by the SWPMI while the software is setting DEACT bit, the SRF flag is set in the SWPMI_ISR register, DEACTF is kept cleared, SWPACT is kept set and DEACT bit is cleared. In order to activate SWP again, the software must clear DEACT bit in the SWPMI_CR register before setting SWPACT bit. Deactivate In order to switch the SWP to the DEACTIVATED mode immediately, ignoring any possible incoming RESUME by slave, the user must clear SWPACT bit in the SWPMI_CR register. DocID024597 Rev 1 1357/1680 1383 Single Wire Protocol Master Interface (SWPMI) Note: RM0351 In order to further reduce current consumption once SWPACT bit is cleared, configure the SWPMI_IO port as output push pull low in GPIO controller (refer to Section 9: Generalpurpose I/Os (GPIO)). Figure 450. SWP bus states 6 $&7,9$7(' PDVWHU(2) 6XVSHQGVHTXHQFH LGOHELWV 6863(1'(' 6 '($&7,9$7(' 6863(1'(' 6 6863(1'(' 5(680(E\PDVWHU LGOHELWV $&7,9$7(' PDVWHU62) WUDQVLWLRQVHTXHQFH 6 5(680( E\VODYH 6 WUDQVLWLRQVHTXHQFH 6863(1'(' $&7,9$7(' VODYH62) 069 40.3.4 SWPMI_IO (internal transceiver) bypass A SWPMI_IO (transceiver), compliant with ETSI TS 102 613 technical specification, is embedded in the microcontroller. Nevertheless, this is possible to bypass it by setting SWP_TBYP bit in SWPMI_OR register. In this case, the SWPMI_IO is disabled and the SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate functions on three GPIOs (refer to “Pinouts and pin description” in product datasheet). This configuration is selected to connect an external transceiver. 40.3.5 SWPMI Bit rate The bit rate must be set in the SWPMI_BRR register, according to the following formula: FSWP = FSWPCLK / ((BR[5:0]+1)x4) Note: The maximum bitrate is 2 Mbit/s. 40.3.6 SWPMI frame handling The SWP frame is composed of a Start of frame (SOF), a Payload from 1 to 30 bytes, a 16bit CRC and an End of frame (EOF) (Refer to Figure 451: SWP frame structure). 1358/1680 DocID024597 Rev 1 RM0351 Single Wire Protocol Master Interface (SWPMI) Figure 451. SWP frame structure 62) (K E 62) ' (2) )K E ' ' ͘͘͘ &5& E\WHV (2) 3$ K& džͲdžͲϭϯͲϭϮ ϭϰĚ ƐĞƚďLJ,t͕ĐůĞĂƌĞĚďLJ^t d& ƐĞƚďLJ,t͕ĐůĞĂƌĞĚďLJD ZyE ƐĞƚďLJ,t͕ĐůĞĂƌĞĚďLJ^t Zy&& ƐĞƚďLJ,t ^h^WE DƚƌĂŶƐĨĞƌƐĚĂƚĂĨƌŽŵ ^tWD/ͺZZƚŽZD DƚƌĂŶƐĨĞƌƐĚĂƚĂĨƌŽŵ ^tWD/ͺZZƚŽZD DƚƌĂŶƐĨĞƌƐĚĂƚĂĨƌŽŵ ^tWD/ͺZZƚŽZD DƚƌĂŶƐĨĞƌƐĚĂƚĂĨƌŽŵ ^tWD/ͺZZƚŽZD ϯͲϮͲϭͲϬ ϳͲϲͲϱͲϰ ϭϭͲϭϬͲϵͲϴ džͲdžͲϭϯͲϭϮ ZD D^ϯϯϯϱϭsϭ Multi software buffer mode This mode allows to work with several frame buffers in the RAM memory, in order to ensure a continuous reception, keeping a very low CPU load, using the DMA. The frame payloads are stored in the RAM memory, together with the frame status flags. The software can check the DMA counters and status flags at any time to handle the received SWP frames in the RAM memory. The Multi software buffer mode must be used in combination with the DMA in circular mode. The Multi software buffer mode is selected by setting both RXDMA and RXMODE bits in SWPMI_CR register. 1366/1680 DocID024597 Rev 1 RM0351 Single Wire Protocol Master Interface (SWPMI) In order to work with n reception buffers in RAM, the DMA channel or stream must be configured in following mode (refer to DMA section): • memory to memory mode disabled, • memory increment mode enabled, • memory size set to 32-bit, • peripheral size set to 32-bit, • peripheral increment mode disabled, • circular mode enabled, • data transfer direction set to read from peripheral, • the number of words to be transfered must be set to 8 x n (8 words per buffer), • the source address is the SWPMI_TDR register, • the destination address is the buffer1 address in RAM Then the user must: 1. Set RXDMA in the SWPMI_CR register 2. Set RXBFIE in the SWPMI_IER register 3. Enable stream or channel in the DMA module. In the SWPMI interrupt routine, the user must check RXBFF in the SWPMI_ISR register. If it is set, the user must set CRXBFF bit in the SWPMI_ICR register to clear RXBFF flag and the user can read the first frame payload received in the first buffer (at the RAM address set in DMA2_CMAR1). The number of data bytes in the payload is available in bits [23:16] of the last 8th word. In the next SWPMI interrupt routine occurrence, the user will read the second frame received in the second buffer (address set in DMA2_CMAR1 + 8), and so on (refer to Figure 457: SWPMI Multi software buffer mode reception). In case the application software cannot ensure to handle the SMPMI interrupt before the next frame reception, each buffer status is available in the most significant byte of the 8th buffer word: • The CRC error flag (equivalent to RXBERF flag in the SWPMI_ISR register) is available in bit 24 of the 8th word. Refer to Section 40.3.9: Error management for an CRC error description. • The receive overrun flag (equivalent to RXOVRF flag in the SWPMI_ISR register) is available in bit 25 of the 8th word. Refer to Section 40.3.9: Error management for an overrun error description. • The receive buffer full flag (equivalent to RXBFF flag in the SWPMI_ISR register) is available in bit 26 of the 8th word. In case of a CRC error, both RXBFF and RXBERF flags are set, thus bit 24 and bit 26 are set. In case of an overrun, an overrun flag is set, thus bit 25 is set. The receive buffer full flag is set only in case of an overrun during the last word reception; then, both bit 25 and bit 26 are set for the current and the next frame reception. The software can also read the DMA counter (number of data to transfer) in the DMA registers in order to retrieve the frame which has already been received and transferred into the RAM memory through DMA. For example, if the software works with 4 reception buffers, DocID024597 Rev 1 1367/1680 1383 Single Wire Protocol Master Interface (SWPMI) RM0351 and if the DMA counter equals 17, it means that two buffers are ready for reading in the RAM area. In Multi software buffer reception mode, if the software is reading bits 24, 25 and 26 of the 8th word, it does not need to clear RXBERF, RXOVRF and RXBFF flags after each frame reception. Figure 457. SWPMI Multi software buffer mode reception ^tW ŝŶƉƵƚ ^K& Ϭ ϭ ^tWD/ͺZZ džͲdžͲdžͲdž ^tWD/ͺZZ džͲdžͲdžͲdž Ϯ ϯ ϰ ϱ ϲ ϯͲϮͲϭͲϬ ϳ ϴ ϵ ϭϬ ϭϭ ϳͲϲͲϱͲϰ ϯͲϮͲϭͲϬ ϭϮ ϭϯ Z ϭϭͲϭϬͲϵͲϴ ϳͲϲͲϱͲϰ dž ^tWD/ͺZ&> K& ^K& ϭϭͲϭϬͲ ϵͲϴ Ϭ džͲdžͲϭϯͲϭϮ džͲdžͲϭϯͲϭϮ ϭϰĚ d& ZyE ƐĞƚďLJ,t͕ĐůĞĂƌĞĚďLJD Zy&& ƐĞƚďLJ,t͕ĐůĞĂƌĞĚďLJ^t ^h^WE ƐĞƚďLJ,t DƚƌĂŶƐĨĞƌƐĚĂƚĂ ĨƌŽŵ^tWD/ͺZZ ƚŽZD DƚƌĂŶƐĨĞƌƐĚĂƚĂ ĨƌŽŵ^tWD/ͺZZƚŽ ZD DƚƌĂŶƐĨĞƌƐĚĂƚĂ ĨƌŽŵ^tWD/ͺZZ ƚŽZD &ƌĂŵĞϭ &ƌĂŵĞϮ &ƌĂŵĞϯ &ƌĂŵĞϰ DƚƌĂŶƐĨĞƌƐĚĂƚĂ ĨƌŽŵ^tWD/ͺZZƚŽ ZD ϯͲϮͲϭͲϬ ϳͲϲͲϱͲϰ ϭϭͲϭϬͲϵͲϴ džͲdžͲϭϯͲϭϮ džͲdžͲdžͲdž džͲdžͲdžͲdž džͲdžͲdžͲdž džͲϭϰͲdžͲdž ϯͲϮͲϭͲϬ ϳͲϲͲϱͲϰ džͲdžͲdžͲdž džͲdžͲdžͲdž džͲdžͲdžͲdž džͲdžͲdžͲdž džͲdžͲdžͲdž džͲϴͲdžͲdž ϯͲϮͲϭͲϬ ϳͲϲͲϱͲϰ ϭϭͲϭϬͲϵͲϴ ϭϱͲϭϰͲϭϯͲϭϮ ϭϵͲϭϴͲϭϳͲϭϲ džͲdžͲdžͲϮϬ džͲdžͲdžͲdž džͲϮϭͲdžͲdž ϯͲϮͲϭͲϬ ϳͲϲͲϱͲϰ ϭϭͲϭϬͲϵͲϴ ϭϱͲϭϰͲϭϯͲϭϮ ϭϵͲϭϴͲϭϳͲϭϲ ϮϯͲϮϮͲϮϭͲϮϬ ϮϳͲϮϲͲϮϱͲϮϰ džͲϮϵͲdžͲϮϴ ZD D^ϯϯϯϱϮsϭ 40.3.9 Error management Underrun during payload transmission During the transmission of the frame payload, a transmit underrun is indicated by the TXUNRF flag in the SWPMI_ISR register. An interrupt is generated if TXBUNREIE bit is set in the SWPMI_IER register. If a transmit underrun occurs, the SWPMI stops the payload transmission and sends a corrupted CRC (the first bit of the first CRC byte sent is inverted), followed by an EOF. If DMA is used, TXDMA bit in the SWPMI_CR register is automatically cleared. 1368/1680 DocID024597 Rev 1 RM0351 Single Wire Protocol Master Interface (SWPMI) Any further write to the SWPMI_TDR register while TXUNRF is set will be ignored. The user must set CTXUNRF bit in the SWPMI_ICR register to clear TXUNRF flag. Overrun during payload reception During the reception of the frame payload, a receive overrun is indicated by RXOVRF flag in the SWPMI_ISR register. If a receive overrun occurs, the SWPMI does not update SWPMI_RDR with the incoming data. The incoming data will be lost. The reception carries on up to the EOF and, if the overrun condition disappears, the RXBFF flag is set. When RXBFF flag is set, the user can check the RXOVRF flag. The user must set CRXOVRF bit in the SWPMI_ICR register to clear RXBOVRF flag. If the user wants to detect the overrun immediately, RXBOVREIE bit in the SWPMI_IER register can be set in order to generate an interrupt as soon as the overrun occurs. The RXOVRF flag is set at the same time as the RXNE flag, two SWPMI_RDR reads after the overrun event occurred. It indicates that at least one received byte was lost, and the loaded word in SWPMI_RDR contains the bytes received just before the overrun. In Multi software buffer mode, if RXOVRF flag is set for the last word of the received frame, then the overrun bit (bit 25 of the 8th word) is set for both the current and the next frame. CRC error during payload reception Once the two CRC bytes have been received, if the CRC is wrong, the RXBERF flag in the SWPMI_ISR register is set after the EOF reception. An interrupt is generated if RXBEIE bit in the SWPMI_IER register is set (refer toFigure 458: SWPMI single buffer mode reception with CRC error).The user must set CRXBERF bit in SWPMI_ICR to clear RXBERF flag. Figure 458. SWPMI single buffer mode reception with CRC error ^tW ŝŶƉƵƚ ^K& ^tWD/ͺZZ Ϭ ϭ Ϯ ϯ ϰ ϱ džͲdžͲdžͲdž ϲ ϳ ϴ ϯͲϮͲϭͲϬ ϵ ϭϬ ϳͲϲͲϱͲϰ ϭϭ ϭϮ ϭϯ ϭϭͲϭϬͲϵͲϴ dž ^tWD/ͺZ&> Z K& džͲdžͲϭϯͲϭϮ ϭϰĚ VHWE\+:FOHDUHGE\6: d& VHWE\+:FOHDUHGE\6:RU'0$ ZyE Zy&& VHWE\+:FOHDUHGE\6: VHWE\+: ^h^WE VHWE\+:FOHDUHGE\6: ZyZ& ^tƌĞĂĚƐ ^tWD/ͺZZ ^tƌĞĂĚƐ ^tWD/ͺZZ ^tƌĞĂĚƐ ^tWD/ͺZZ ^tĚĞƚĞĐƚƐĞƌƌŽƌ ǁŝƚŚZyZ&ĨůĂŐ 069 Missing or corrupted stuffing bit during payload reception When a stuffing bit is missing or is corrupted in the payload, RXBERF and RXBFF flags are set in SWPMI_ISR after the EOF reception. DocID024597 Rev 1 1369/1680 1383 Single Wire Protocol Master Interface (SWPMI) RM0351 Corrupted EOF reception Once an SOF has been received, the SWPMI accumulates the received bytes until the reception of an EOF (ignoring any possible SOF). Once an EOF has been received, the SWPMI is ready to start a new frame reception and waits for an SOF. In case of a corrupted EOF, RXBERF and RXBFF flags will bet set in the SWPMI_ISR register after the next EOF reception. Note: In case of a corrupted EOF reception, the payload reception carries on, thus the number of bytes in the payload might get the value 31 if the number of received bytes is greater than 30. The number of bytes in the payload is read in the SWPMI_RFL register or in bits [23:16] of the 8th word of the buffer in the RAM memory, depending on the operating mode. 40.3.10 Loopback mode The loopback mode can be used for test purposes. The user must set LPBK bit in the SWPMI_CR register in order to enable the loopback mode. When the loopback mode is enabled, SWPMI_TX and SWPMI_RX signals are connected together. As a consequence, all frames sent by the SWPMI will be received back. 40.4 SWPMI low-power modes Table 212. Effect of low-power modes on SWPMI Mode Description Sleep No effect SWPMI interrupts cause the device to exit the Sleep mode. Stop A RESUME from SUSPENDED mode issued by the slave can wake up the device from Stop mode if the SWPCLK is HSI16 (refer to Section 40.3.1: SWPMI block diagram) Standby The SWPMI is stopped. 40.5 SWPMI interrupts All SWPMI interrupts are connected to the NVIC. To enable the SWPMI interrupt, the following sequence is required: 1370/1680 1. Configure and enable the SWPMI interrupt channel in the NVIC 2. Configure the SWPMI to generate SWPMI interrupts (refer to the SWPMI_IER register). DocID024597 Rev 1 RM0351 Single Wire Protocol Master Interface (SWPMI) Table 213. Interrupt control bits Event flag Enable control bit Exit the Sleep mode Exit the Stop mode Exit the Standby mode Receive buffer full RXBFF RXBFIE yes no no Transmit buffer empty TXBEF TXBEIE yes no no Receive buffer error (CRC error) RXBERF RXBEIE yes no no Receive buffer overrun RXOVRF RXBOVEREIE yes no no Transmit buffer underrun TXUNRF TXBUNREIE yes no no RXNE RIE yes no no Transmit data register full TXE TIE yes no no Transfer complete flag TCF TCIE yes no no Interrupt event Receive data register not empty Slave resume flag SRF SRIE yes yes (1) no 1. If HSI16 is selected for SWPCLK. DocID024597 Rev 1 1371/1680 1383 Single Wire Protocol Master Interface (SWPMI) 40.6 RM0351 SWPMI registers Refer to section 1.1 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). 40.6.1 SWPMI Configuration/Control register (SWPMI_CR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. SWP ACT LPBK rw rw Res. Res. Res. Res. Res. DEACT Res. Res. Res. rw TXMOD RXMO TXDMA RXDMA E DE rw rw rw rw Bits 31:11 Reserved, must be kept at reset value Bit 10 DEACT: Single wire protocol master interface deactivate This bit is used to request the SWP DEACTIVATED state. Setting this bit has the same effect as clearing the SWPACT, except that a possible incoming RESUME by slave will keep the SWP in the ACTIVATED state. Bits 9:6 Reserved, must be kept at reset value Bit 5 SWPACT: Single wire protocol master interface activate This bit is used to activate the SWP bus (refer to Section 40.3.2: SWP initialization and activation). 0: SWPMI_IO is pulled down to ground, SWP bus is switched to DEACTIVATED state 1: SWPMI_IO is released, SWP bus is switched to SUSPENDED state To be able to set SWPACT bit, DEACT bit must be have been cleared previously. Bit 4 LPBK: Loopback mode enable This bit is used to enable the loopback mode 0: Loopback mode is disabled 1: Loopback mode is enabled Note: This bit cannot be written while SWPACT bit is set. Bit 3 TXMODE: Transmission buffering mode This bit is used to choose the transmission buffering mode. This bit is relevant only when TXDMA bit is set (refer to Table 214: Buffer modes selection for transmission/reception). 0: SWPMI is configured in Single software buffer mode for transmission 1: SWPMI is configured in Multi software buffer mode for transmission. Note: This bit cannot be written while SWPACT bit is set. 1372/1680 DocID024597 Rev 1 RM0351 Single Wire Protocol Master Interface (SWPMI) Bit 2 RXMODE: Reception buffering mode This bit is used to choose the reception buffering mode. This bit is relevant only when TXDMA bit is set (refer to Table 214: Buffer modes selection for transmission/reception). 0: SWPMI is configured in Single software buffer mode for reception 1: SWPMI is configured in Multi software buffer mode for reception. Note: This bit cannot be written while SWPACT bit is set. Bit 1 TXDMA: Transmission DMA enable This bit is used to enable the DMA mode in transmission 0: DMA is disabled for transmission 1: DMA is enabled for transmission Note: TXDMA is automatically cleared if the payload size of the transmitted frame is given as 0x00 (in the least significant byte of TDR for the first word of a frame). TXDMA is also automatically cleared on underrun events (when TXUNRF flag is set in the SWP_ISR register) Bit 0 RXDMA: Reception DMA enable This bit is used to enable the DMA mode in reception 0: DMA is disabled for reception 1: DMA is enabled for reception Table 214. Buffer modes selection for transmission/reception Buffer mode No software buffer Single software buffer Multi software buffer RXMODE/TXMODE x 0 1 RXDMA/TXDMA 0 1 1 DocID024597 Rev 1 1373/1680 1383 Single Wire Protocol Master Interface (SWPMI) 40.6.2 RM0351 SWPMI Bitrate register (SWPMI_BRR) Address offset: 0x04 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw BR[5:0] rw rw rw Bits 31:6 Reserved, must be kept at reset value Bits 5:0 BR[5:0]: Bitrate prescaler This field must be programmed to set SWP bus bitrate, taking into account the FSWPCLK programmed in the RCC (Reset and Clock Control), according to the following formula: FSWP= FSWPCLK / ((BR[5:0]+1)x4) Note: The programmed bitrate must stay within the following range: from 100 kbit/s up to 2 Mbit/s. BR[5:0] cannot be written while SWPACT bit is set in the SWPMI_CR register. 1374/1680 DocID024597 Rev 1 RM0351 Single Wire Protocol Master Interface (SWPMI) 40.6.3 SWPMI Interrupt and Status register (SWPMI_ISR) Address offset: 0x0C Reset value: 0x0000 02C2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. DEACT F SUSP SRF TCF TXE RXNE r r r r r r Res. Res. Res. Res. TXUNR RXOVR RXBER TXBEF RXBFF F F F r r r r r Bits 31:11 Reserved, must be kept at reset value Bit 10 DEACTF: DEACTIVATED flag This bit is a status flag, acknowledging the request to enter the DEACTIVATED mode. 0: SWP bus is in ACTIVATED or SUSPENDED state 1: SWP bus is in DEACTIVATED state If a RESUME by slave state is detected by the SWPMI while DEACT bit is set by software, the SRF flag will be set, DEACTF will not be set and SWP will move in ACTIVATED state. Bit 9 SUSP: SUSPEND flag This bit is a status flag, reporting the SWP bus state 0: SWP bus is in ACTIVATED state 1: SWP bus is in SUSPENDED or DEACTIVATED state Bit 8 SRF: Slave resume flag This bit is set by hardware to indicate a RESUME by slave detection. It is cleared by software, writing 1 to CSRF bit in the SWPMI_ICR register. 0: No Resume by slave state detected 1: A Resume by slave state has been detected during the SWP bus SUSPENDED state Bit 7 TCF: Transfer complete flag This flag is set by hardware as soon as both transmission and reception are completed and SWP is switched to the SUSPENDED state. It is cleared by software, writing 1 to CTCF bit in the SWPMI_ICR register. 0: Transmission or reception is not completed 1: Both transmission and reception are completed and SWP is switched to the SUSPENDED state Bit 6 TXE: Transmit data register empty This flag indicates the transmit data register status 0: Data written in transmit data register SWPMI_TDR is not transmitted yet 1: Data written in transmit data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again Bit 5 RXNE: Receive data register not empty This flag indicates the receive data register status 0: Data is not received in the SWPMI_RDR register 1: Received data is ready to be read in the SWPMI_RDR register DocID024597 Rev 1 1375/1680 1383 Single Wire Protocol Master Interface (SWPMI) RM0351 Bit 4 TXUNRF: Transmit underrun error flag This flag is set by hardware to indicate an underrun during the payload transmission i.e. SWPMI_TDR has not been written in time by the software or the DMA. It is cleared by software, writing 1 to the CTXUNRF bit in the SWPMI_ICR register. 0: No underrun error in transmission 1: Underrun error in transmission detected Bit 3 RXOVRF: Receive overrun error flag This flag is set by hardware to indicate an overrun during the payload reception, i.e. SWPMI_RDR has not be read in time by the software or the DMA. It is cleared by software, writing 1 to CRXOVRF bit in the SWPMI_ICR register. 0: No overrun in reception 1: Overrun in reception detected Bit 2 RXBERF: Receive CRC error flag This flag is set by hardware to indicate a CRC error in the received frame. It is set synchronously with RXBFF flag. It is cleared by software, writing 1 to CRXBERF bit in the SWPMI_ICR register. 0: No CRC error in reception 1: CRC error in reception detected Bit 1 TXBEF: Transmit buffer empty flag This flag is set by hardware to indicate that no more SWPMI_TDR update is required to complete the current frame transmission. It is cleared by software, writing 1 to CTXBEF bit in the SWPMI_ICR register. 0: Frame transmission buffer no yet emptied 1: Frame transmission buffer has been emptied Bit 0 RXBFF: Receive buffer full flag This flag is set by hardware when the final word for the frame under reception is available in SWPMI_RDR. It is cleared by software, writing 1 to CRXBFF bit in the SWPMI_ICR register. 0: The last word of the frame under reception has not yet arrived in SWPMI_RDR 1: The last word of the frame under reception has arrived in SWPMI_RDR 1376/1680 DocID024597 Rev 1 RM0351 Single Wire Protocol Master Interface (SWPMI) 40.6.4 SWPMI Interrupt Flag Clear register (SWPMI_ICR) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. CSRF CTCF rc_w1 rc_w1 Res. Res. CTXUN CRXOV CRXBE CTXBE CRXBF RF RF RF F F rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits 31:9 Reserved, must be kept at reset value Bit 8 CSRF: Clear slave resume flag Writing 1 to this bit clears the SRF flag in the SWPMI_ISR register Writing 0 to this bit does not have any effect Bit 7 CTCF: Clear transfer complete flag Writing 1 to this bit clears the TCF flag in the SWPMI_ISR register Writing 0 to this bit does not have any effect Bits 6:5 Reserved, must be kept at reset value Bit 4 CTXUNRF: Clear transmit underrun error flag Writing 1 to this bit clears the TXUNRF flag in the SWPMI_ISR register Writing 0 to this bit does not have any effect Bit 3 CRXOVRF: Clear receive overrun error flag Writing 1 to this bit clears the RXBOCREF flag in the SWPMI_ISR register Writing 0 to this bit does not have any effect Bit 2 CRXBERF: Clear receive CRC error flag Writing 1 to this bit clears the RXBERF flag in the SWPMI_ISR register Writing 0 to this bit does not have any effect Bit 1 CTXBEF: Clear transmit buffer empty flag Writing 1 to this bit clears the TXBEF flag in the SWPMI_ISR register Writing 0 to this bit does not have any effect Bit 0 CRXBFF: Clear receive buffer full flag Writing 1 to this bit clears the RXBFF flag in the SWPMI_ISR register Writing 0 to this bit does not have any effect DocID024597 Rev 1 1377/1680 1383 Single Wire Protocol Master Interface (SWPMI) 40.6.5 RM0351 SWPMI Interrupt Enable register (SMPMI_IER) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. SRIE TCIE TIE RIE rw rw rw rw TXUNR RXOVR RXBEI TXBERI RXBFIE EIE EIE E E rw rw rw rw rw Bits 31:9 Reserved, must be kept at reset value Bit 8 SRIE: Slave resume interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever SRF flag is set in the SWPMI_ISR register Bit 7 TCIE: Transmit complete interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever TCF flag is set in the SWPMI_ISR register Bit 6 TIE: Transmit interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever TXE flag is set in the SWPMI_ISR register Bit 5 RIE: Receive interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever RXNE flag is set in the SWPMI_ISR register Bit 4 TXUNRIE: Transmit underrun error interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever TXBUNRF flag is set in the SWPMI_ISR register Bit 3 RXOVRIE: Receive overrun error interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever RXBOVRF flag is set in the SWPMI_ISR register Bit 2 RXBERIE: Receive CRC error interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever RXBERF flag is set in the SWPMI_ISR register Bit 1 TXBEIE: Transmit buffer empty interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever TXBEF flag is set in the SWPMI_ISR register Bit 0 RXBFIE: Receive buffer full interrupt enable 0: Interrupt is inhibited 1: An SWPMI interrupt is generated whenever RXBFF flag is set in the SWPMI_ISR register 1378/1680 DocID024597 Rev 1 RM0351 Single Wire Protocol Master Interface (SWPMI) 40.6.6 SWPMI Receive Frame Length register (SWPMI_RFL) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r r RFL[4:0] r r r Bits 31:5 Reserved, must be kept at reset value Bits 4:0 RFL[4:0]: Receive frame length RFL[4:0] is the number of data bytes in the payload of the received frame. The two least significant bits RFL[1:0] give the number of relevant bytes for the last SWPMI_RDR register read. DocID024597 Rev 1 1379/1680 1383 Single Wire Protocol Master Interface (SWPMI) 40.6.7 RM0351 SWPMI Transmit data register (SWPMI_TDR) Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TD[31:16] w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w TD[15:0] w w w w w w w w w Bits 31:0 TD[31:0]: Transmit data Contains the data to be transmitted. Writing to this register triggers the SOF transmission or the next payload data transmission, and clears the TXE flag. 1380/1680 DocID024597 Rev 1 RM0351 Single Wire Protocol Master Interface (SWPMI) 40.6.8 SWPMI Receive data register (SWPMI_RDR) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RD[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r RD[15:0] r r r r r r r r r Bits 31:0 RD[31:0]: received data Contains the received data Reading this register is clearing the RXNE flag. DocID024597 Rev 1 1381/1680 1383 Single Wire Protocol Master Interface (SWPMI) 40.6.9 RM0351 SWPMI Option register (SWPMI_OR) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWP_ CLASS SWP_ TBYP rw rw Bits 31:2 Reserved, must be kept at reset value Bit 1 SWP_CLASS: SWP class selection This bit is used to select the SWP class (refer to Section 40.3.2: SWP initialization and activation). 0: Class C: SWPMI_IO uses directly VDD voltage to operate in class C. This configuration must be selected when VDD is in the range [1.62 V to 1.98 V] 1: Class B: SWPMI_IO uses an internal voltage regulator to operate in class B. This configuration must be selected when VDD is in the range [2.70 V to 3.30 V] Bit 0 SWP_TBYP: SWP transceiver bypass This bit is used to bypass the internal transceiver (SWPMI_IO), and connect an external transceiver. 0: Internal transceiver is enabled. The external interface for SWPMI is SWPMI_IO (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs) 1: Internal transceiver is disabled. SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate function on GPIOs. This configuration is selected to connect an external transceiver 1382/1680 DocID024597 Rev 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWPMI_OR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWPMI_RDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD[31:0] 0 Reset value DocID024597 Rev 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWP_ TBYP 0 Res. SWPMI_TDR Res. 0 Res. SWPMI_RFL Res. CTXUNRF CRXBERF CTXBEF CRXBFF 0 0 0 RXBERIE TXBEIE RXBFIE 0 CRXOVRF 0 0 TXUNRIE 0 0 RXOVRIE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DEACTF SUSP. SRF TCF TXE. RXNE. TXUNRF RXOVRF RXBERF TXBEF RXBFF Reset value RIE TIE Res. CTCF 0 TCIE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DEACT Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Reset value LPBK RXMODE TXDMA RXDMA 0 TXMODE SWPACT 0 Res. Res. Res. Res. CSRF Reset value 0 SRIE Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWPMI_IER Res. SWPMI_ICR SWP_ CLASS 0 Res. 0x24 Reset value Res. 0x20 Res. 0x1C Res. 0x18 Res. 0x14 Res. 0x10 SWPMI_ISR Res. 0x0C RESERVED Res. 0x08 SWPMI_BRR Res. 0x04 SWPMI_CR Res. 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name reset value Res. Offset Res. 40.6.10 Res. RM0351 Single Wire Protocol Master Interface (SWPMI) SWPMI register map and reset value table Table 215. SWPMI register map and reset values Register size 0 0 0 0 0 BRR[5:0] 0 0 0 0 1 0 1 0 1 1 0 0 0 0 1 0 0 0 RFL[4:0] 0 0 0 0 TD[31:0] 0 0 0 0 0 0 0 1383/1680 1383 SD/SDIO/MMC card host interface (SDMMC) 41 SD/SDIO/MMC card host interface (SDMMC) 41.1 SDMMC main features RM0351 The SD/SDIO MMC card host interface (SDMMC) provides an interface between the APB2 peripheral bus and MultiMediaCards (MMCs), SD memory cards and SDIO cards. The MultiMediaCard system specifications are available through the MultiMediaCard Association website, published by the MMCA technical committee. SD memory card and SD I/O card system specifications are available through the SD card Association website. The SDMMC features include the following: Note: • Full compliance with MultiMediaCard System Specification Version 4.2. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit • Full compatibility with previous versions of MultiMediaCards (forward compatibility) • Full compliance with SD Memory Card Specifications Version 2.0 • Full compliance with SD I/O Card Specification Version 2.0: card support for two different databus modes: 1-bit (default) and 4-bit • Data transfer up to 48 MHz for the 8 bit mode • Data and command output enable signals to control external bidirectional drivers. 1 The SDMMC does not have an SPI-compatible communication mode. 2 The SD memory card protocol is a superset of the MultiMediaCard protocol as defined in the MultiMediaCard system specification V2.11. Several commands required for SD memory devices are not supported by either SD I/O-only cards or the I/O portion of combo cards. Some of these commands have no use in SD I/O devices, such as erase commands, and thus are not supported in the SDIO protocol. In addition, several commands are different between SD memory cards and SD I/O cards and thus are not supported in the SDIO protocol. For details refer to SD I/O card Specification Version 1.0. The MultiMediaCard/SD bus connects cards to the controller. The current version of the SDMMC supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. 41.2 SDMMC bus topology Communication over the bus is based on command and data transfers. The basic transaction on the MultiMediaCard/SD/SD I/O bus is the command/response transaction. These types of bus transaction transfer their information directly within the command or response structure. In addition, some operations have a data token. Data transfers to/from SD/SDIO memory cards are done in data blocks. Data transfers to/from MMC are done data blocks or streams. 1384/1680 DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) Figure 459. “No response” and “no data” operations )URPKRVWWRFDUG V 6'00&B&0' )URPKRVWWRFDUG &RPPDQG &RPPDQG )URPFDUGWRKRVW 5HVSRQVH 6'00&B' 2SHUDWLRQ QRUHVSRQVH 2SHUDWLRQ QRGDWD DLE Figure 460. (Multiple) block read operation )URPKRVWWRFDUG )URPFDUGWRKRVW GDWDIURPFDUGWRKRVW 6'00&B&0' &RPPDQG 6WRSFRPPDQG VWRSVGDWDWUDQVIHU 5HVSRQVH 6'00&B' &RPPDQG 'DWDEORFN FUF 'DWDEORFN FUF 5HVSRQVH 'DWDEORFN FUF %ORFNUHDGRSHUDWLRQ 'DWDVWRSRSHUDWLRQ 0XOWLSOHEORFNUHDGRSHUDWLRQ DLE Figure 461. (Multiple) block write operation )URPKRVWWRFDUG )URPFDUGWRKRVW GDWDIURPKRVWWRFDUG 6'00&B&0' 6'00&B' &RPPDQG 6WRSFRPPDQG VWRSVGDWDWUDQVIHU 5HVSRQVH &RPPDQG 'DWDEORFN FUF %XV\ %ORFNZULWHRSHUDWLRQ 'DWDEORFN FUF 5HVSRQVH %XV\ 'DWDVWRSRSHUDWLRQ 0XOWLSOHEORFNZULWHRSHUDWLRQ DLE Note: The SDMMC will not send any data as long as the Busy signal is asserted (SDMMC_D0 pulled low). DocID024597 Rev 1 1385/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 Figure 462. Sequential read operation )URPKRVWWR )URPFDUGWRKRVW FDUG V 6WRSFRPPDQG VWRSVGDWDWUDQVIHU 'DWDIURPFDUGWRKRVW 6'00&B&0' &RPPDQG 5HVSRQVH &RPPDQG 5HVSRQVH 'DWDVWUHDP 6'00&B' 'DWDVWRSRSHUDWLRQ 'DWDWUDQVIHURSHUDWLRQ DLE Figure 463. Sequential write operation )URPKRVWWR FDUG V )URPFDUGWRKRVW 6WRSFRPPDQG VWRSVGDWDWUDQVIHU 'DWDIURPKRVWWRFDUG 6'00&B&0' &RPPDQG 5HVSRQVH &RPPDQG 5HVSRQVH 'DWDVWUHDP 6'00&B' 'DWDVWRSRSHUDWLRQ 'DWDWUDQVIHURSHUDWLRQ DLE 41.3 SDMMC functional description The SDMMC consists of two parts: • The SDMMC adapter block provides all functions specific to the MMC/SD/SD I/O card such as the clock generation unit, command and data transfer. • The APB2 interface accesses the SDMMC adapter registers, and generates interrupt and DMA request signals. Figure 464. SDMMC block diagram 6'00& 6'00&B&. ,QWHUUXSWVDQG '0$UHTXHVW 6'00&B&0' $3% LQWHUIDFH 6'00& DGDSWHU 3&/. 6'00&&/. 6'00&B'>@ $3%EXV 1386/1680 DocID024597 Rev 1 DLE RM0351 SD/SDIO/MMC card host interface (SDMMC) By default SDMMC_D0 is used for data transfer. After initialization, the host can change the databus width. If a MultiMediaCard is connected to the bus, SDMMC_D0, SDMMC_D[3:0] or SDMMC_D[7:0] can be used for data transfer. MMC V3.31 or previous, supports only 1 bit of data so only SDMMC_D0 can be used. If an SD or SD I/O card is connected to the bus, data transfer can be configured by the host to use SDMMC_D0 or SDMMC_D[3:0]. All data lines are operating in push-pull mode. SDMMC_CMD has two operational modes: • Open-drain for initialization (only for MMCV3.31 or previous) • Push-pull for command transfer (SD/SD I/O card MMC4.2 use push-pull drivers also for initialization) SDMMC_CK is the clock to the card: one bit is transferred on both command and data lines with each clock cycle. The clock frequency can vary between 0 MHz and 20 MHz (for a MultiMediaCard V3.31), between 0 and 48 MHz for a MultiMediaCard V4.0/4.2, or between 0 and 25 MHz (for an SD/SD I/O card). The SDMMC uses two clock signals: • SDMMC adapter clock SDMMCCLK = 48 MHz) • APB2 bus clock (PCLK2) PCLK2 and SDMMC_CK clock frequencies must respect the following condition: Frequenc ( PCLK2 ) > ( ( 3xWidth ) ⁄ 32 ) × Frequency ( SDMMC_CK ) The signals shown in Table 216 are used on the MultiMediaCard/SD/SD I/O card bus. Table 216. SDMMC I/O definitions Pin Direction Description SDMMC_CK Output MultiMediaCard/SD/SDIO card clock. This pin is the clock from host to card. SDMMC_CMD Bidirectional MultiMediaCard/SD/SDIO card command. This pin is the bidirectional command/response signal. SDMMC_D[7:0] Bidirectional MultiMediaCard/SD/SDIO card data. These pins are the bidirectional databus. DocID024597 Rev 1 1387/1680 1441 SD/SDIO/MMC card host interface (SDMMC) 41.3.1 RM0351 SDMMC adapter Figure 465 shows a simplified block diagram of an SDMMC adapter. Figure 465. SDMMC adapter 6'00&DGDSWHU $GDSWHU UHJLVWHUV 7R$3% LQWHUIDFH ),)2 3&/. 6'00&B&. &RPPDQG SDWK 6'00&B&0' 'DWDSDWK 6'00&B'>@ &DUGEXV &RQWUROXQLW 6'00&&/. DLE The SDMMC adapter is a multimedia/secure digital memory card bus master that provides an interface to a multimedia card stack or to a secure digital memory card. It consists of five subunits: Note: • Adapter register block • Control unit • Command path • Data path • Data FIFO The adapter registers and FIFO use the APB2 bus clock domain (PCLK2). The control unit, command path and data path use the SDMMC adapter clock domain (SDMMCCLK). Adapter register block The adapter register block contains all system registers. This block also generates the signals that clear the static flags in the multimedia card. The clear signals are generated when 1 is written into the corresponding bit location in the SDMMC Clear register. Control unit The control unit contains the power management functions and the clock divider for the memory card clock. There are three power phases: 1388/1680 • power-off • power-up • power-on DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) Figure 466. Control unit &RQWUROXQLW 3RZHUPDQDJHPHQW $GDSWHU UHJLVWHUV &ORFNPDQDJHPHQW 6'00&B&. 7RFRPPDQGDQGGDWDSDWK DLE The control unit is illustrated in Figure 466. It consists of a power management subunit and a clock management subunit. The power management subunit disables the card bus output signals during the power-off and power-up phases. The clock management subunit generates and controls the SDMMC_CK signal. The SDMMC_CK output can use either the clock divide or the clock bypass mode. The clock output is inactive: • after reset • during the power-off or power-up phases • if the power saving mode is enabled and the card bus is in the Idle state (eight clock periods after both the command and data path subunits enter the Idle phase) The clock management subunit controls SDMMC_CK dephasing. When not in bypass mode the SDMMC command and data output are generated on the SDMMCCLK falling edge succeeding the rising edge of SDMMC_CK. (SDMMC_CK rising edge occurs on SDMMCCLK rising edge) when SDMMC_CLKCR[13] bit is reset (NEGEDGE = 0). When SDMMC_CLKCR[13] bit is set (NEGEDGE = 1) SDMMC command and data changed on the SDMMC_CK falling edge. When SDMMC_CLKCR[10] is set (BYPASS = 1), SDMMC_CK rising edge occurs on SDMMCCLK rising edge. The data and the command change on SDMMCCLK falling edge whatever NEGEDGE value. The data and command responses are latched using SDMMC_CK rising edge. DocID024597 Rev 1 1389/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 Figure 467. SDMMC_CK clock dephasing (BYPASS = 0) 6'00&&/. 6'00&B&. &0''DWD RXWSXW 1(*('*( 1(*('*( 06Y9 Command path The command path unit sends commands to and receives responses from the cards. Figure 468. SDMMC adapter command path 7RFRQWUROXQLW 6WDWXV IODJ &RQWURO ORJLF &RPPDQG WLPHU $GDSWHUUHJLVWHUV 6'00&B&0'LQ &0' $UJXPHQW &5& &0' 7R$3%LQWHUIDFH 6'00&B&0'RXW 6KLIW UHJLVWHU 5HVSRQVH UHJLVWHUV DLE • Command path state machine (CPSM) – 1390/1680 When the command register is written to and the enable bit is set, command transfer starts. When the command has been sent, the command path state machine (CPSM) sets the status flags and enters the Idle state if a response is not required. If a response is required, it waits for the response (see Figure 469 on page 1391). When the response is received, the received CRC code and the internally generated code are compared, and the appropriate status flags are set. DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) Figure 469. Command path state machine (SDMMC) 2QUHVHW &360HQDEOHGDQG SHQGLQJFRPPDQG ,GOH &360GLVDEOHG 3HQG 5HVSRQVHUHFHLYHGRU GLVDEOHGRUFRPPDQG &5&IDLOHG (QDEOHGDQG FRPPDQGVWDUW &360GLVDEOHG RUQRUHVSRQVH /DVWGDWD 6HQG &360GLVDEOHGRU FRPPDQGWLPHRXW 5HFHLYH 5HVSRQVH VWDUWHG :DLWIRUUHVSRQVH :DLW 069 When the Wait state is entered, the command timer starts running. If the timeout is reached before the CPSM moves to the Receive state, the timeout flag is set and the Idle state is entered. Note: The command timeout has a fixed value of 64 SDMMC_CK clock periods. If the interrupt bit is set in the command register, the timer is disabled and the CPSM waits for an interrupt request from one of the cards. If a pending bit is set in the command register, the CPSM enters the Pend state, and waits for a CmdPend signal from the data path subunit. When CmdPend is detected, the CPSM moves to the Send state. This enables the data counter to trigger the stop command transmission. Note: The CPSM remains in the Idle state for at least eight SDMMC_CK periods to meet the NCC and NRC timing constraints. NCC is the minimum delay between two host commands, and NRC is the minimum delay between the host command and the card response. DocID024597 Rev 1 1391/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 Figure 470. SDMMC command transfer DWOHDVW6'00&B&. F\FOHV 6'00&B&. &RPPDQG &RPPDQG 5HVSRQVH 6WDWH ,GOH 6HQG :DLW 5HFHLYH ,GOH 6HQG 6'00&B&0' +L= &RQWUROOHUGULYHV +L= &DUGGULYHV +L= &RQWUROOHUGULYHV DLE • Command format – Command: a command is a token that starts an operation. Command are sent from the host either to a single card (addressed command) or to all connected cards (broadcast command are available for MMC V3.31 or previous). Commands are transferred serially on the CMD line. All commands have a fixed length of 48 bits. The general format for a command token for MultiMediaCards, SD-Memory cards and SDIO-Cards is shown in Table 217. The command path operates in a half-duplex mode, so that commands and responses can either be sent or received. If the CPSM is not in the Send state, the SDMMC_CMD output is in the Hi-Z state, as shown in Figure 470 on page 1392. Data on SDMMC_CMD are synchronous with the rising edge of SDMMC_CK. Table 217 shows the command format. Table 217. Command format Bit position Width Value Description 47 1 0 Start bit 46 1 1 Transmission bit [45:40] 6 - Command index [39:8] 32 - Argument [7:1] 7 - CRC7 0 1 1 End bit – Response: a response is a token that is sent from an addressed card (or synchronously from all connected cards for MMC V3.31 or previous), to the host as an answer to a previously received command. Responses are transferred serially on the CMD line. The SDMMC supports two response types. Both use CRC error checking: Note: 1392/1680 • 48 bit short response • 136 bit long response If the response does not contain a CRC (CMD1 response), the device driver must ignore the CRC failed status. DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) Table 218. Short response format Bit position Width Value Description 47 1 0 Start bit 46 1 0 Transmission bit [45:40] 6 - Command index [39:8] 32 - Argument [7:1] 7 - CRC7(or 1111111) 0 1 1 End bit Table 219. Long response format Bit position Width Value Description 135 1 0 Start bit 134 1 0 Transmission bit [133:128] 6 111111 Reserved [127:1] 127 - CID or CSD (including internal CRC7) 0 1 1 End bit The command register contains the command index (six bits sent to a card) and the command type. These determine whether the command requires a response, and whether the response is 48 or 136 bits long (see Section 41.8.4 on page 1428). The command path implements the status flags shown in Table 220: Table 220. Command path status flags Flag Description CMDREND Set if response CRC is OK. CCRCFAIL Set if response CRC fails. CMDSENT Set when command (that does not require response) is sent CTIMEOUT Response timeout. CMDACT Command transfer in progress. The CRC generator calculates the CRC checksum for all bits before the CRC code. This includes the start bit, transmitter bit, command index, and command argument (or card status). The CRC checksum is calculated for the first 120 bits of CID or CSD for the long response format. Note that the start bit, transmitter bit and the six reserved bits are not used in the CRC calculation. The CRC checksum is a 7-bit value: CRC[6:0] = Remainder [(M(x) * x7) / G(x)] G(x) = x7 + x3 + 1 M(x) = (start bit) * x39 + ... + (last bit before CRC) * x0, or M(x) = (start bit) * x119 + ... + (last bit before CRC) * x0 DocID024597 Rev 1 1393/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 Data path The data path subunit transfers data to and from cards. Figure 471 shows a block diagram of the data path. Figure 471. Data path 'DWDSDWK 7RFRQWUROXQLW 6WDWXV IODJ &RQWURO ORJLF 'DWD WLPHU 'DWD),)2 6'00&B'LQ>@ 7UDQVPLW &5& 6'00&B'RXW>@ 6KLIW UHJLVWHU 5HFHLYH DLE The card databus width can be programmed using the clock control register. If the 4-bit wide bus mode is enabled, data is transferred at four bits per clock cycle over all four data signals (SDMMC_D[3:0]). If the 8-bit wide bus mode is enabled, data is transferred at eight bits per clock cycle over all eight data signals (SDMMC_D[7:0]). If the wide bus mode is not enabled, only one bit per clock cycle is transferred over SDMMC_D0. Depending on the transfer direction (send or receive), the data path state machine (DPSM) moves to the Wait_S or Wait_R state when it is enabled: • Send: the DPSM moves to the Wait_S state. If there is data in the transmit FIFO, the DPSM moves to the Send state, and the data path subunit starts sending data to a card. • Receive: the DPSM moves to the Wait_R state and waits for a start bit. When it receives a start bit, the DPSM moves to the Receive state, and the data path subunit starts receiving data from a card. Data path state machine (DPSM) The DPSM operates at SDMMC_CK frequency. Data on the card bus signals is synchronous to the rising edge of SDMMC_CK. The DPSM has six states, as shown in Figure 472: Data path state machine (DPSM). 1394/1680 DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) Figure 472. Data path state machine (DPSM) /N RESET $03- DISABLED 2EAD 7AIT $03- ENABLED AND 2EAD 7AIT 3TARTED AND 3$ )/ MODE ENABLED $ISABLED OR &)&/ UNDERRUN OR END OF DATA OR #2# FAIL )DLE $ISABLED OR #2# FAIL OR TIMEOUT %NABLE AND NOT SEND 2EAD7AIT 3TOP $ISABLED OR END OF DATA $ISABLED OR 2X &)&/ EMPTY OR TIMEOUT OR START BIT ERROR "USY .OT BUSY %NABLE AND SEND 7AIT?2 $ATA RECEIVED AND 2EAD 7AIT 3TARTED AND 3$ )/ MODE ENABLED %ND OF PACKET 7AIT?3 %ND OF PACKET OR END OF DATA OR &)&/ OVERRUN $ISABLED OR #2# FAIL 3TART BIT $ATA READY 3END 2ECEIVE AIB • Idle: the data path is inactive, and the SDMMC_D[7:0] outputs are in Hi-Z. When the data control register is written and the enable bit is set, the DPSM loads the data counter with a new value and, depending on the data direction bit, moves to either the Wait_S or the Wait_R state. • Wait_R: if the data counter equals zero, the DPSM moves to the Idle state when the receive FIFO is empty. If the data counter is not zero, the DPSM waits for a start bit on SDMMC_D. The DPSM moves to the Receive state if it receives a start bit before a timeout, and loads the data block counter. If it reaches a timeout before it detects a start bit, it moves to the Idle state and sets the timeout status flag. • Receive: serial data received from a card is packed in bytes and written to the data FIFO. Depending on the transfer mode bit in the data control register, the data transfer mode can be either block or stream: – In block mode, when the data block counter reaches zero, the DPSM waits until it receives the CRC code. If the received code matches the internally generated CRC code, the DPSM moves to the Wait_R state. If not, the CRC fail status flag is set and the DPSM moves to the Idle state. – In stream mode, the DPSM receives data while the data counter is not zero. When the counter is zero, the remaining data in the shift register is written to the data FIFO, and the DPSM moves to the Wait_R state. If a FIFO overrun error occurs, the DPSM sets the FIFO error flag and moves to the Idle state: • Wait_S: the DPSM moves to the Idle state if the data counter is zero. If not, it waits until the data FIFO empty flag is deasserted, and moves to the Send state. DocID024597 Rev 1 1395/1680 1441 SD/SDIO/MMC card host interface (SDMMC) Note: RM0351 The DPSM remains in the Wait_S state for at least two clock periods to meet the NWR timing requirements, where NWR is the number of clock cycles between the reception of the card response and the start of the data transfer from the host. • Send: the DPSM starts sending data to a card. Depending on the transfer mode bit in the data control register, the data transfer mode can be either block or stream: – In block mode, when the data block counter reaches zero, the DPSM sends an internally generated CRC code and end bit, and moves to the Busy state. – In stream mode, the DPSM sends data to a card while the enable bit is high and the data counter is not zero. It then moves to the Idle state. If a FIFO underrun error occurs, the DPSM sets the FIFO error flag and moves to the Idle state. • Busy: the DPSM waits for the CRC status flag: – If it does not receive a positive CRC status, it moves to the Idle state and sets the CRC fail status flag. – If it receives a positive CRC status, it moves to the Wait_S state if SDMMC_D0 is not low (the card is not busy). If a timeout occurs while the DPSM is in the Busy state, it sets the data timeout flag and moves to the Idle state. The data timer is enabled when the DPSM is in the Wait_R or Busy state, and generates the data timeout error: • – When transmitting data, the timeout occurs if the DPSM stays in the Busy state for longer than the programmed timeout period – When receiving data, the timeout occurs if the end of the data is not true, and if the DPSM stays in the Wait_R state for longer than the programmed timeout period. Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data lines. They are stored in a FIFO of 32 words, each word is 32 bits wide. Table 221. Data token format Description 1396/1680 Start bit Data CRC16 End bit Block Data 0 - yes 1 Stream Data 0 - no 1 DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) DPSM Flags The status of the data path subunit transfer is reported by several status flags Table 222. DPSM flags Flag Description DBCKEND Set to high when data block send/receive CRC check is passed. In SDIO multibyte transfer mode this flag is set at the end of the transfer (a multibyte transfer is considered as a single block transfer by the host). DATAEND Set to high when SDMMC_DCOUNT register decrements and reaches 0. DATAEND indicates the end of a transfer on SDMMC data line. DTIMEOUT Set to high when data timeout period is reached. When data timer reaches zero while DPSM is in Wait_R or Busy state, timeout is set. DTIMEOUT can be set after DATAEND if DPSM remains in busy state for longer than the programmed period. DCRCFAIL Set to high when data block send/receive CRC check fails. Data FIFO The data FIFO (first-in-first-out) subunit is a data buffer with a transmit and receive unit. The FIFO contains a 32-bit wide, 32-word deep data buffer, and transmit and receive logic. Because the data FIFO operates in the APB2 clock domain (PCLK2), all signals from the subunits in the SDMMC clock domain (SDMMCCLK) are resynchronized. Depending on the TXACT and RXACT flags, the FIFO can be disabled, transmit enabled, or receive enabled. TXACT and RXACT are driven by the data path subunit and are mutually exclusive: • – The transmit FIFO refers to the transmit logic and data buffer when TXACT is asserted – The receive FIFO refers to the receive logic and data buffer when RXACT is asserted Transmit FIFO: Data can be written to the transmit FIFO through the APB2 interface when the SDMMC is enabled for transmission. The transmit FIFO is accessible via 32 sequential addresses. The transmit FIFO contains a data output register that holds the data word pointed to by the read pointer. When the data path subunit has loaded its shift register, it increments the read pointer and drives new data out. If the transmit FIFO is disabled, all status flags are deasserted. The data path subunit asserts TXACT when it transmits data. DocID024597 Rev 1 1397/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 Table 223. Transmit FIFO status flags Flag Description TXFIFOF Set to high when all 32 transmit FIFO words contain valid data. TXFIFOE Set to high when the transmit FIFO does not contain valid data. TXFIFOHE Set to high when 8 or more transmit FIFO words are empty. This flag can be used as a DMA request. TXDAVL Set to high when the transmit FIFO contains valid data. This flag is the inverse of the TXFIFOE flag. TXUNDERR Set to high when an underrun error occurs. This flag is cleared by writing to the SDMMC Clear register. Note: In case of TXUNDERR, and DMA is used to fill SDMMC FIFO, user software should disable DMA stream, and then write DMAEN bit in SDMMC_DCTRL with ‘0’ (to disable DMA request generation). • Receive FIFO When the data path subunit receives a word of data, it drives the data on the write databus. The write pointer is incremented after the write operation completes. On the read side, the contents of the FIFO word pointed to by the current value of the read pointer is driven onto the read databus. If the receive FIFO is disabled, all status flags are deasserted, and the read and write pointers are reset. The data path subunit asserts RXACT when it receives data. Table 224 lists the receive FIFO status flags. The receive FIFO is accessible via 32 sequential addresses. Table 224. Receive FIFO status flags Flag 1398/1680 Description RXFIFOF Set to high when all 32 receive FIFO words contain valid data RXFIFOE Set to high when the receive FIFO does not contain valid data. RXFIFOHF Set to high when 8 or more receive FIFO words contain valid data. This flag can be used as a DMA request. RXDAVL Set to high when the receive FIFO is not empty. This flag is the inverse of the RXFIFOE flag. RXOVERR Set to high when an overrun error occurs. This flag is cleared by writing to the SDMMC Clear register. Note: In case of RXOVERR, and DMA is used to read SDMMC FIFO, user software should disable DMA stream, and then write DMAEN bit in SDMMC_DCTRL with ‘0’ (to disable DMA request generation). DocID024597 Rev 1 RM0351 41.3.2 SD/SDIO/MMC card host interface (SDMMC) SDMMC APB2 interface The APB2 interface generates the interrupt and DMA requests, and accesses the SDMMC adapter registers and the data FIFO. It consists of a data path, register decoder, and interrupt/DMA logic. SDMMC interrupts The interrupt logic generates an interrupt request signal that is asserted when at least one of the selected status flags is high. A mask register is provided to allow selection of the conditions that will generate an interrupt. A status flag generates the interrupt request if a corresponding mask flag is set. SDMMC/DMA interface SDMMC APB interface controls all subunit to perform transfers between the host and card Example of read procedure using DMA Send CMD17 (READ_BLOCK) as follows: Note: a) Program the SDMMC data length register (SDMMC data timer register should be already programmed before the card identification process) b) Program DMA channel (please refer to DMA configuration for SDMMC controller) c) Program the SDMMC data control register: DTEN with ‘1’ (SDMMC card host enabled to send data); DTDIR with ‘1’ (from card to controller); DTMODE with ‘0’ (block data transfer); DMAEN with ‘1’ (DMA enabled); DBLOCKSIZE with 0x9 (512 bytes). Other fields are don’t care. d) Program the SDMMC argument register with the address location of the card from where data is to be transferred e) Program the SDMMC command register: CmdIndex with 17(READ_BLOCK); WaitResp with ‘1’ (SDMMC card host waits for a response); CPSMEN with ‘1’ (SDMMC card host enabled to send a command). Other fields are at their reset value. f) Wait for SDMMC_STA[6] = CMDREND interrupt, (CMDREND is set if there is no error on command path). g) Wait for SDMMC_STA[10] = DBCKEND, (DBCKEND is set in case of no errors until the CRC check is passed) h) Wait until the FIFO is empty, when FIFO is empty the SDMMC_STA[5] = RXOVERR value has to be check to guarantee that read succeeded When FIFO overrun error occurs with last 1-4 bytes, it may happens that RXOVERR flag is set 2 APB clock cycles after DATAEND flag is set. To guarantee success of read operation RXOVERR must be cheked after FIFO is empty. DocID024597 Rev 1 1399/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 Example of write procedure using DMA Send CMD24 (WRITE_BLOCK) as follows: a) Program the SDMMC data length register (SDMMC data timer register should be already programmed before the card identification process) b) Program DMA channel (please refer to DMA configuration for SDMMC controller) c) Program the SDMMC argument register with the address location of the card from where data is to be transferred d) Program the SDMMC command register: CmdIndex with 24(WRITE_BLOCK); WaitResp with ‘1’ (SDMMC card host waits for a response); CPSMEN with ‘1’ (SDMMC card host enabled to send a command). Other fields are at their reset value. e) Wait for SDMMC_STA[6] = CMDREND interrupt, then Program the SDMMC data control register: DTEN with ‘1’ (SDMMC card host enabled to send data); DTDIR with ‘0’ (from controller to card); DTMODE with ‘0’ (block data transfer); DMAEN with ‘1’ (DMA enabled); DBLOCKSIZE with 0x9 (512 bytes). Other fields are don’t care. f) Wait for SDMMC_STA[10] = DBCKEND, (DBCKEND is set in case of no errors) DMA configuration for SDMMC controller a) Enable DMA2 controller and clear any pending interrupts b) Program the DMA2_Channel4 (or DMA2_Channel5) source address register with the memory location base address and DMA2_Channel4 (or DMA2_Channel5) destination address register with the SDMMC_FIFO register address c) Program DMA2_Channel4 (or DMA2_Channel5) control register (memory increment, not peripheral increment, peripheral and source width is word size) d) Enable DMA2_Channel4 (or DMA2_Channel5) 41.4 Card functional description 41.4.1 Card identification mode While in card identification mode the host resets all cards, validates the operation voltage range, identifies cards and sets a relative card address (RCA) for each card on the bus. All data communications in the card identification mode use the command line (CMD) only. 41.4.2 Card reset The GO_IDLE_STATE command (CMD0) is the software reset command and it puts the MultiMediaCard and SD memory in the Idle state. The IO_RW_DIRECT command (CMD52) resets the SD I/O card. After power-up or CMD0, all cards output bus drivers are in the highimpedance state and the cards are initialized with a default relative card address (RCA=0x0001) and with a default driver stage register setting (lowest speed, highest driving current capability). 1400/1680 DocID024597 Rev 1 RM0351 41.4.3 SD/SDIO/MMC card host interface (SDMMC) Operating voltage range validation All cards can communicate with the SDMMC card host using any operating voltage within the specification range. The supported minimum and maximum VDD values are defined in the operation conditions register (OCR) on the card. Cards that store the card identification number (CID) and card specific data (CSD) in the payload memory are able to communicate this information only under data-transfer VDD conditions. When the SDMMC card host module and the card have incompatible VDD ranges, the card is not able to complete the identification cycle and cannot send CSD data. For this purpose, the special commands, SEND_OP_COND (CMD1), SD_APP_OP_COND (ACMD41 for SD Memory), and IO_SEND_OP_COND (CMD5 for SD I/O), are designed to provide a mechanism to identify and reject cards that do not match the VDD range desired by the SDMMC card host. The SDMMC card host sends the required VDD voltage window as the operand of these commands. Cards that cannot perform data transfer in the specified range disconnect from the bus and go to the inactive state. By using these commands without including the voltage range as the operand, the SDMMC card host can query each card and determine the common voltage range before placing outof-range cards in the inactive state. This query is used when the SDMMC card host is able to select a common voltage range or when the user requires notification that cards are not usable. 41.4.4 Card identification process The card identification process differs for MultiMediaCards and SD cards. For MultiMediaCard cards, the identification process starts at clock rate Fod. The SDMMC_CMD line output drivers are open-drain and allow parallel card operation during this process. The registration process is accomplished as follows: 1. The bus is activated. 2. The SDMMC card host broadcasts SEND_OP_COND (CMD1) to receive operation conditions. 3. The response is the wired AND operation of the operation condition registers from all cards. 4. Incompatible cards are placed in the inactive state. 5. The SDMMC card host broadcasts ALL_SEND_CID (CMD2) to all active cards. 6. The active cards simultaneously send their CID numbers serially. Cards with outgoing CID bits that do not match the bits on the command line stop transmitting and must wait for the next identification cycle. One card successfully transmits a full CID to the SDMMC card host and enters the Identification state. 7. The SDMMC card host issues SET_RELATIVE_ADDR (CMD3) to that card. This new address is called the relative card address (RCA); it is shorter than the CID and addresses the card. The assigned card changes to the Standby state, it does not react to further identification cycles, and its output switches from open-drain to push-pull. 8. The SDMMC card host repeats steps 5 through 7 until it receives a timeout condition. For the SD card, the identification process starts at clock rate Fod, and the SDMMC_CMD line output drives are push-pull drivers instead of open-drain. The registration process is accomplished as follows: DocID024597 Rev 1 1401/1680 1441 SD/SDIO/MMC card host interface (SDMMC) 1. The bus is activated. 2. The SDMMC card host broadcasts SD_APP_OP_COND (ACMD41). 3. The cards respond with the contents of their operation condition registers. RM0351 4. The incompatible cards are placed in the inactive state. 5. The SDMMC card host broadcasts ALL_SEND_CID (CMD2) to all active cards. 6. The cards send back their unique card identification numbers (CIDs) and enter the Identification state. 7. The SDMMC card host issues SET_RELATIVE_ADDR (CMD3) to an active card with an address. This new address is called the relative card address (RCA); it is shorter than the CID and addresses the card. The assigned card changes to the Standby state. The SDMMC card host can reissue this command to change the RCA. The RCA of the card is the last assigned value. 8. The SDMMC card host repeats steps 5 through 7 with all active cards. For the SD I/O card, the registration process is accomplished as follows: 1. 41.4.5 The bus is activated. 2. The SDMMC card host sends IO_SEND_OP_COND (CMD5). 3. The cards respond with the contents of their operation condition registers. 4. The incompatible cards are set to the inactive state. 5. The SDMMC card host issues SET_RELATIVE_ADDR (CMD3) to an active card with an address. This new address is called the relative card address (RCA); it is shorter than the CID and addresses the card. The assigned card changes to the Standby state. The SDMMC card host can reissue this command to change the RCA. The RCA of the card is the last assigned value. Block write During block write (CMD24 - 27) one or more blocks of data are transferred from the host to the card with a CRC appended to the end of each block by the host. A card supporting block write is always able to accept a block of data defined by WRITE_BL_LEN. If the CRC fails, the card indicates the failure on the SDMMC_D line and the transferred data are discarded and not written, and all further transmitted blocks (in multiple block write mode) are ignored. If the host uses partial blocks whose accumulated length is not block aligned and, block misalignment is not allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card will detect the block misalignment error before the beginning of the first misaligned block. (ADDRESS_ERROR error bit is set in the status register). The write operation will also be aborted if the host tries to write over a write-protected area. In this case, however, the card will set the WP_VIOLATION bit. Programming of the CID and CSD registers does not require a previous block length setting. The transferred data is also CRC protected. If a part of the CSD or CID register is stored in ROM, then this unchangeable part must match the corresponding part of the receive buffer. If this match fails, then the card reports an error and does not change any register contents. Some cards may require long and unpredictable times to write a block of data. After receiving a block of data and completing the CRC check, the card begins writing and holds the SDMMC_D line low if its write buffer is full and unable to accept new data from a new WRITE_BLOCK command. The host may poll the status of the card with a SEND_STATUS command (CMD13) at any time, and the card will respond with its status. The READY_FOR_DATA status bit indicates whether the card can accept new data or whether the write process is still in progress. The host may deselect the card by issuing CMD7 (to 1402/1680 DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) select a different card), which will place the card in the Disconnect state and release the SDMMC_D line(s) without interrupting the write operation. When reselecting the card, it will reactivate busy indication by pulling SDMMC_D to low if programming is still in progress and the write buffer is unavailable. 41.4.6 Block read In Block read mode the basic unit of data transfer is a block whose maximum size is defined in the CSD (READ_BL_LEN). If READ_BL_PARTIAL is set, smaller blocks whose start and end addresses are entirely contained within one physical block (as defined by READ_BL_LEN) may also be transmitted. A CRC is appended to the end of each block, ensuring data transfer integrity. CMD17 (READ_SINGLE_BLOCK) initiates a block read and after completing the transfer, the card returns to the Transfer state. CMD18 (READ_MULTIPLE_BLOCK) starts a transfer of several consecutive blocks. The host can abort reading at any time, within a multiple block operation, regardless of its type. Transaction abort is done by sending the stop transmission command. If the card detects an error (for example, out of range, address misalignment or internal error) during a multiple block read operation (both types) it stops the data transmission and remains in the data state. The host must than abort the operation by sending the stop transmission command. The read error is reported in the response to the stop transmission command. If the host sends a stop transmission command after the card transmits the last block of a multiple block operation with a predefined number of blocks, it is responded to as an illegal command, since the card is no longer in the data state. If the host uses partial blocks whose accumulated length is not block-aligned and block misalignment is not allowed, the card detects a block misalignment error condition at the beginning of the first misaligned block (ADDRESS_ERROR error bit is set in the status register). 41.4.7 Stream access, stream write and stream read (MultiMediaCard only) In stream mode, data is transferred in bytes and no CRC is appended at the end of each block. Stream write (MultiMediaCard only) WRITE_DAT_UNTIL_STOP (CMD20) starts the data transfer from the SDMMC card host to the card, beginning at the specified address and continuing until the SDMMC card host issues a stop command. When partial blocks are allowed (CSD parameter WRITE_BL_PARTIAL is set), the data stream can start and stop at any address within the card address space, otherwise it can only start and stop at block boundaries. Because the amount of data to be transferred is not determined in advance, a CRC cannot be used. When the end of the memory range is reached while sending data and no stop command is sent by the SDMMC card host, any additional transferred data are discarded. DocID024597 Rev 1 1403/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 The maximum clock frequency for a stream write operation is given by the following equation fields of the card-specific data register: ( 8 × 2 writebllen ) ( – NSAC ) Maximumspeed = MIN (TRANSPEED,-------------------------------------------------------------------------) TAAC × R2WFACTOR • Maximumspeed = maximum write frequency • TRANSPEED = maximum data transfer rate • writebllen = maximum write data block length • NSAC = data read access time 2 in CLK cycles • TAAC = data read access time 1 • R2WFACTOR = write speed factor If the host attempts to use a higher frequency, the card may not be able to process the data and stop programming, set the OVERRUN error bit in the status register, and while ignoring all further data transfer, wait (in the receive data state) for a stop command. The write operation is also aborted if the host tries to write over a write-protected area. In this case, however, the card sets the WP_VIOLATION bit. Stream read (MultiMediaCard only) READ_DAT_UNTIL_STOP (CMD11) controls a stream-oriented data transfer. This command instructs the card to send its data, starting at a specified address, until the SDMMC card host sends STOP_TRANSMISSION (CMD12). The stop command has an execution delay due to the serial command transmission and the data transfer stops after the end bit of the stop command. When the end of the memory range is reached while sending data and no stop command is sent by the SDMMC card host, any subsequent data sent are considered undefined. The maximum clock frequency for a stream read operation is given by the following equation and uses fields of the card specific data register. ( 8 × 2 readbllen ) ( – NSAC ) Maximumspeed = MIN (TRANSPEED,------------------------------------------------------------------------) TAAC × R2WFACTOR • Maximumspeed = maximum read frequency • TRANSPEED = maximum data transfer rate • readbllen = maximum read data block length • writebllen = maximum write data block length • NSAC = data read access time 2 in CLK cycles • TAAC = data read access time 1 • R2WFACTOR = write speed factor If the host attempts to use a higher frequency, the card is not able to sustain data transfer. If this happens, the card sets the UNDERRUN error bit in the status register, aborts the transmission and waits in the data state for a stop command. 1404/1680 DocID024597 Rev 1 RM0351 41.4.8 SD/SDIO/MMC card host interface (SDMMC) Erase: group erase and sector erase The erasable unit of the MultiMediaCard is the erase group. The erase group is measured in write blocks, which are the basic writable units of the card. The size of the erase group is a card-specific parameter and defined in the CSD. The host can erase a contiguous range of Erase Groups. Starting the erase process is a three-step sequence. First the host defines the start address of the range using the ERASE_GROUP_START (CMD35) command, next it defines the last address of the range using the ERASE_GROUP_END (CMD36) command and, finally, it starts the erase process by issuing the ERASE (CMD38) command. The address field in the erase commands is an Erase Group address in byte units. The card ignores all LSBs below the Erase Group size, effectively rounding the address down to the Erase Group boundary. If an erase command is received out of sequence, the card sets the ERASE_SEQ_ERROR bit in the status register and resets the whole sequence. If an out-of-sequence (neither of the erase commands, except SEND_STATUS) command received, the card sets the ERASE_RESET status bit in the status register, resets the erase sequence and executes the last command. If the erase range includes write protected blocks, they are left intact and only nonprotected blocks are erased. The WP_ERASE_SKIP status bit in the status register is set. The card indicates that an erase is in progress by holding SDMMC_D low. The actual erase time may be quite long, and the host may issue CMD7 to deselect the card. 41.4.9 Wide bus selection or deselection Wide bus (4-bit bus width) operation mode is selected or deselected using SET_BUS_WIDTH (ACMD6). The default bus width after power-up or GO_IDLE_STATE (CMD0) is 1 bit. SET_BUS_WIDTH (ACMD6) is only valid in a transfer state, which means that the bus width can be changed only after a card is selected by SELECT/DESELECT_CARD (CMD7). 41.4.10 Protection management Three write protection methods for the cards are supported in the SDMMC card host module: 1. internal card write protection (card responsibility) 2. mechanical write protection switch (SDMMC card host module responsibility only) 3. password-protected card lock operation Internal card write protection Card data can be protected against write and erase. By setting the permanent or temporary write-protect bits in the CSD, the entire card can be permanently write-protected by the manufacturer or content provider. For cards that support write protection of groups of sectors by setting the WP_GRP_ENABLE bit in the CSD, portions of the data can be protected, and the write protection can be changed by the application. The write protection is in units of WP_GRP_SIZE sectors as specified in the CSD. The SET_WRITE_PROT and CLR_WRITE_PROT commands control the protection of the addressed group. The SEND_WRITE_PROT command is similar to a single block read command. The card sends DocID024597 Rev 1 1405/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 a data block containing 32 write protection bits (representing 32 write protect groups starting at the specified address) followed by 16 CRC bits. The address field in the write protect commands is a group address in byte units. The card ignores all LSBs below the group size. Mechanical write protect switch A mechanical sliding tab on the side of the card allows the user to set or clear the write protection on a card. When the sliding tab is positioned with the window open, the card is write-protected, and when the window is closed, the card contents can be changed. A matched switch on the socket side indicates to the SDMMC card host module that the card is write-protected. The SDMMC card host module is responsible for protecting the card. The position of the write protect switch is unknown to the internal circuitry of the card. Password protect The password protection feature enables the SDMMC card host module to lock and unlock a card with a password. The password is stored in the 128-bit PWD register and its size is set in the 8-bit PWD_LEN register. These registers are nonvolatile so that a power cycle does not erase them. Locked cards respond to and execute certain commands. This means that the SDMMC card host module is allowed to reset, initialize, select, and query for status, however it is not allowed to access data on the card. When the password is set (as indicated by a nonzero value of PWD_LEN), the card is locked automatically after power-up. As with the CSD and CID register write commands, the lock/unlock commands are available in the transfer state only. In this state, the command does not include an address argument and the card must be selected before using it. The card lock/unlock commands have the structure and bus transaction types of a regular single-block write command. The transferred data block includes all of the required information for the command (the password setting mode, the PWD itself, and card lock/unlock). The command data block size is defined by the SDMMC card host module before it sends the card lock/unlock command, and has the structure shown in Table 238. The bit settings are as follows: • ERASE: setting it forces an erase operation. All other bits must be zero, and only the command byte is sent • LOCK_UNLOCK: setting it locks the card. LOCK_UNLOCK can be set simultaneously with SET_PWD, however not with CLR_PWD • CLR_PWD: setting it clears the password data • SET_PWD: setting it saves the password data to memory • PWD_LEN: it defines the length of the password in bytes • PWD: the password (new or currently used, depending on the command) The following sections list the command sequences to set/reset a password, lock/unlock the card, and force an erase. Setting the password 1406/1680 1. Select a card (SELECT/DESELECT_CARD, CMD7), if none is already selected. 2. Define the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card lock/unlock mode, the 8-bit PWD_LEN, and the number of bytes of the new password. DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) When a password replacement is done, the block size must take into account that both the old and the new passwords are sent with the command. 3. Send LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line including the 16-bit CRC. The data block indicates the mode (SET_PWD = 1), the length (PWD_LEN), and the password (PWD) itself. When a password replacement is done, the length value (PWD_LEN) includes the length of both passwords, the old and the new one, and the PWD field includes the old password (currently used) followed by the new password. 4. When the password is matched, the new password and its size are saved into the PWD and PWD_LEN fields, respectively. When the old password sent does not correspond (in size and/or content) to the expected password, the LOCK_UNLOCK_FAILED error bit is set in the card status register, and the password is not changed. The password length field (PWD_LEN) indicates whether a password is currently set. When this field is nonzero, there is a password set and the card locks itself after power-up. It is possible to lock the card immediately in the current power session by setting the LOCK_UNLOCK bit (while setting the password) or sending an additional command for card locking. Resetting the password 1. Select a card (SELECT/DESELECT_CARD, CMD7), if none is already selected. 2. Define the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card lock/unlock mode, the 8-bit PWD_LEN, and the number of bytes in the currently used password. 3. Send LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line including the 16-bit CRC. The data block indicates the mode (CLR_PWD = 1), the length (PWD_LEN) and the password (PWD) itself. The LOCK_UNLOCK bit is ignored. 4. When the password is matched, the PWD field is cleared and PWD_LEN is set to 0. When the password sent does not correspond (in size and/or content) to the expected password, the LOCK_UNLOCK_FAILED error bit is set in the card status register, and the password is not changed. Locking a card 1. Select a card (SELECT/DESELECT_CARD, CMD7), if none is already selected. 2. Define the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card lock/unlock mode (byte 0 in Table 238), the 8-bit PWD_LEN, and the number of bytes of the current password. 3. Send LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line including the 16-bit CRC. The data block indicates the mode (LOCK_UNLOCK = 1), the length (PWD_LEN), and the password (PWD) itself. 4. When the password is matched, the card is locked and the CARD_IS_LOCKED status bit is set in the card status register. When the password sent does not correspond (in size and/or content) to the expected password, the LOCK_UNLOCK_FAILED error bit is set in the card status register, and the lock fails. It is possible to set the password and to lock the card in the same sequence. In this case, the SDMMC card host module performs all the required steps for setting the password (see Setting the password on page 1406), however it is necessary to set the LOCK_UNLOCK bit in Step 3 when the new password command is sent. DocID024597 Rev 1 1407/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 When the password is previously set (PWD_LEN is not 0), the card is locked automatically after power on reset. An attempt to lock a locked card or to lock a card that does not have a password fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register. Unlocking the card 1. Select a card (SELECT/DESELECT_CARD, CMD7), if none is already selected. 2. Define the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit cardlock/unlock mode (byte 0 in Table 238), the 8-bit PWD_LEN, and the number of bytes of the current password. 3. Send LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line including the 16-bit CRC. The data block indicates the mode (LOCK_UNLOCK = 0), the length (PWD_LEN), and the password (PWD) itself. 4. When the password is matched, the card is unlocked and the CARD_IS_LOCKED status bit is cleared in the card status register. When the password sent is not correct in size and/or content and does not correspond to the expected password, the LOCK_UNLOCK_FAILED error bit is set in the card status register, and the card remains locked. The unlocking function is only valid for the current power session. When the PWD field is not clear, the card is locked automatically on the next power-up. An attempt to unlock an unlocked card fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register. Forcing erase If the user has forgotten the password (PWD content), it is possible to access the card after clearing all the data on the card. This forced erase operation erases all card data and all password data. 1. Select a card (SELECT/DESELECT_CARD, CMD7), if none is already selected. 2. Set the block length (SET_BLOCKLEN, CMD16) to 1 byte. Only the 8-bit card lock/unlock byte (byte 0 in Table 238) is sent. 3. Send LOCK/UNLOCK (CMD42) with the appropriate data byte on the data line including the 16-bit CRC. The data block indicates the mode (ERASE = 1). All other bits must be zero. 4. When the ERASE bit is the only bit set in the data field, all card contents are erased, including the PWD and PWD_LEN fields, and the card is no longer locked. When any other bits are set, the LOCK_UNLOCK_FAILED error bit is set in the card status register and the card retains all of its data, and remains locked. An attempt to use a force erase on an unlocked card fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register. 1408/1680 DocID024597 Rev 1 RM0351 41.4.11 SD/SDIO/MMC card host interface (SDMMC) Card status register The response format R1 contains a 32-bit field named card status. This field is intended to transmit the card status information (which may be stored in a local status register) to the host. If not specified otherwise, the status entries are always related to the previously issued command. Table 225 defines the different entries of the status. The type and clear condition fields in the table are abbreviated as follows: Type: • E: error bit • S: status bit • R: detected and set for the actual command response • X: detected and set during command execution. The SDMMC card host must poll the card by issuing the status command to read these bits. Clear condition: • A: according to the card current state • B: always related to the previous command. Reception of a valid command clears it (with a delay of one command) • C: clear by read Table 225. Card status Bits 31 30 29 Identifier ADDRESS_ OUT_OF_RANGE ADDRESS_MISALIGN BLOCK_LEN_ERROR Type ERX Value Description Clear condition ’0’= no error ’1’= error The command address argument was out of the allowed range for this card. A multiple block or stream read/write C operation is (although started in a valid address) attempting to read or write beyond the card capacity. ’0’= no error ’1’= error The commands address argument (in accordance with the currently set block length) positions the first data block misaligned to the card physical blocks. A multiple block read/write operation (although started with a valid address/block-length combination) is attempting to read or write a data block which is not aligned with the physical blocks of the card. ’0’= no error ’1’= error Either the argument of a SET_BLOCKLEN command exceeds the maximum value allowed for the card, or the previously defined block length is illegal for the current command (e.g. the C host issues a write command, the current block length is smaller than the maximum allowed value for the card and it is not allowed to write partial blocks) DocID024597 Rev 1 C 1409/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 Table 225. Card status (continued) Bits Identifier Type Value Description Clear condition ’0’= no error ’1’= error An error in the sequence of erase commands occurred. C EX ’0’= no error ’1’= error An invalid selection of erase groups for erase occurred. C WP_VIOLATION EX ’0’= no error ’1’= error Attempt to program a write-protected block. 25 CARD_IS_LOCKED SR ‘0’ = card unlocked ‘1’ = card locked When set, signals that the card is locked by the host A 24 LOCK_UNLOCK_ FAILED EX ’0’= no error ’1’= error Set when a sequence or password error has been detected in lock/unlock card command C 23 COM_CRC_ERROR ER ’0’= no error ’1’= error The CRC check of the previous command B failed. 22 ILLEGAL_COMMAND ER ’0’= no error ’1’= error Command not legal for the card state B 21 CARD_ECC_FAILED EX ’0’= success ’1’= failure Card internal ECC was applied but failed to correct the data. C 20 CC_ERROR ER ’0’= no error ’1’= error (Undefined by the standard) A card error occurred, which is not related to the host command. C EX ’0’= no error ’1’= error (Undefined by the standard) A generic card error related to the (and detected during) execution of the last host command (e.g. read or write failures). C Can be either of the following errors: – The CID register has already been written and cannot be overwritten – The read-only section of the CSD does C not match the card contents – An attempt to reverse the copy (set as original) or permanent WP (unprotected) bits was made 28 ERASE_SEQ_ERROR 27 ERASE_PARAM 26 19 ERROR 18 Reserved 17 Reserved 16 CID/CSD_OVERWRITE EX ’0’= no error ‘1’= error 15 WP_ERASE_SKIP EX ’0’= not protected Set when only partial address space ’1’= protected was erased due to existing write 14 CARD_ECC_DISABLED S X 1410/1680 ’0’= enabled ’1’= disabled C C The command has been executed without A using the internal ECC. DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) Table 225. Card status (continued) Bits Identifier Type Value Description Clear condition ERASE_RESET ’0’= cleared ’1’= set An erase sequence was cleared before executing because an out of erase sequence command was received (commands other than CMD35, CMD36, CMD38 or CMD13) 12:9 CURRENT_STATE SR 0 = Idle 1 = Ready 2 = Ident 3 = Stby 4 = Tran 5 = Data 6 = Rcv 7 = Prg 8 = Dis 9 = Btst 10-15 = reserved The state of the card when receiving the command. If the command execution causes a state change, it will be visible to B the host in the response on the next command. The four bits are interpreted as a binary number between 0 and 15. 8 READY_FOR_DATA SR ’0’= not ready ‘1’ = ready Corresponds to buffer empty signalling on the bus 7 SWITCH_ERROR EX ’0’= no error ’1’= switch error If set, the card did not switch to the expected mode as requested by the SWITCH command B 6 Reserved 5 APP_CMD SR ‘0’ = Disabled ‘1’ = Enabled The card will expect ACMD, or an indication that the command has been interpreted as ACMD C 4 Reserved for SD I/O Card 3 AKE_SEQ_ERROR ER ’0’= no error ’1’= error Error in the sequence of the authentication process C 2 Reserved for application specific commands 13 1 0 C Reserved for manufacturer test mode DocID024597 Rev 1 1411/1680 1441 SD/SDIO/MMC card host interface (SDMMC) 41.4.12 RM0351 SD status register The SD status contains status bits that are related to the SD memory card proprietary features and may be used for future application-specific usage. The size of the SD Status is one data block of 512 bits. The contents of this register are transmitted to the SDMMC card host if ACMD13 is sent (CMD55 followed with CMD13). ACMD13 can be sent to a card in transfer state only (card is selected). Table 226 defines the different entries of the SD status register. The type and clear condition fields in the table are abbreviated as follows: Type: • E: error bit • S: status bit • R: detected and set for the actual command response • X: detected and set during command execution. The SDMMC card Host must poll the card by issuing the status command to read these bits Clear condition: • A: according to the card current state • B: always related to the previous command. Reception of a valid command clears it (with a delay of one command) • C: clear by read Table 226. SD status Bits Identifier Type Value Description Clear condition 511: 510 DAT_BUS_WIDTH S R ’00’= 1 (default) ‘01’= reserved ‘10’= 4 bit width ‘11’= reserved Shows the currently defined databus width that was defined by SET_BUS_WIDTH command A 509 ’0’= Not in the mode ’1’= In Secured Mode Card is in Secured Mode of operation (refer to the “SD Security Specification”). A ’00xxh’= SD Memory Cards as defined in Physical Spec Ver1.012.00 (’x’= don’t care). The following cards are currently defined: ’0000’= Regular SD RD/WR Card. ’0001’= SD ROM Card In the future, the 8 LSBs will be used to define different variations of an SD memory card (each bit will define different SD types). The 8 A MSBs will be used to define SD Cards that do not comply with current SD physical layer specification. Size of protected area (See below) (See below) A Speed Class of the card (See below) (See below) A SECURED_MODE S R 508: 496 Reserved 495: 480 SD_CARD_TYPE 479: 448 SIZE_OF_PROTE SR CT ED_AREA 447: 440 SPEED_CLASS 1412/1680 SR SR DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) Table 226. SD status (continued) Bits Identifier Type Value Description Clear condition 439: 432 PERFORMANCE_ SR MOVE Performance of move indicated by 1 [MB/s] step. (See below) (See below) A 431:428 AU_SIZE SR Size of AU (See below) (See below) A 427:424 Reserved 423:408 ERASE_SIZE SR Number of AUs to be erased at a time (See below) A 407:402 ERASE_TIMEOUT S R Timeout value for erasing areas specified by UNIT_OF_ERASE_AU (See below) A 401:400 ERASE_OFFSET Fixed offset value added to erase (See below) time. A 399:312 Reserved 311:0 Reserved for Manufacturer SR SIZE_OF_PROTECTED_AREA Setting this field differs between standard- and high-capacity cards. In the case of a standard-capacity card, the capacity of protected area is calculated as follows: Protected area = SIZE_OF_PROTECTED_AREA_* MULT * BLOCK_LEN. SIZE_OF_PROTECTED_AREA is specified by the unit in MULT*BLOCK_LEN. In the case of a high-capacity card, the capacity of protected area is specified in this field: Protected area = SIZE_OF_PROTECTED_AREA SIZE_OF_PROTECTED_AREA is specified by the unit in bytes. SPEED_CLASS This 8-bit field indicates the speed class and the value can be calculated by PW/2 (where PW is the write performance). Table 227. Speed class code field SPEED_CLASS Value definition 00h Class 0 01h Class 2 02h Class 4 03h Class 6 04h – FFh Reserved DocID024597 Rev 1 1413/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 PERFORMANCE_MOVE This 8-bit field indicates Pm (performance move) and the value can be set by 1 [MB/sec] steps. If the card does not move used RUs (recording units), Pm should be considered as infinity. Setting the field to FFh means infinity. Table 228. Performance move field PERFORMANCE_MOVE Value definition 00h Not defined 01h 1 [MB/sec] 02h 02h 2 [MB/sec] --------- --------- FEh 254 [MB/sec] FFh Infinity AU_SIZE This 4-bit field indicates the AU size and the value can be selected in the power of 2 base from 16 KB. Table 229. AU_SIZE field AU_SIZE Value definition 00h Not defined 01h 16 KB 02h 32 KB 03h 64 KB 04h 128 KB 05h 256 KB 06h 512 KB 07h 1 MB 08h 2 MB 09h 4 MB Ah – Fh Reserved The maximum AU size, which depends on the card capacity, is defined in Table 230. The card can be set to any AU size between RU size and maximum AU size. Table 230. Maximum AU size 1414/1680 Capacity 16 MB-64 MB 128 MB-256 MB 512 MB 1 GB-32 GB Maximum AU Size 512 KB 1 MB 2 MB 4 MB DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) ERASE_SIZE This 16-bit field indicates NERASE. When NERASE numbers of AUs are erased, the timeout value is specified by ERASE_TIMEOUT (Refer to ERASE_TIMEOUT). The host should determine the proper number of AUs to be erased in one operation so that the host can show the progress of the erase operation. If this field is set to 0, the erase timeout calculation is not supported. Table 231. Erase size field ERASE_SIZE Value definition 0000h Erase timeout calculation is not supported. 0001h 1 AU 0002h 2 AU 0003h 3 AU --------- --------- FFFFh 65535 AU ERASE_TIMEOUT This 6-bit field indicates TERASE and the value indicates the erase timeout from offset when multiple AUs are being erased as specified by ERASE_SIZE. The range of ERASE_TIMEOUT can be defined as up to 63 seconds and the card manufacturer can choose any combination of ERASE_SIZE and ERASE_TIMEOUT depending on the implementation. Determining ERASE_TIMEOUT determines the ERASE_SIZE. Table 232. Erase timeout field ERASE_TIMEOUT Value definition 00 Erase timeout calculation is not supported. 01 1 [sec] 02 2 [sec] 03 3 [sec] --------- --------- 63 63 [sec] ERASE_OFFSET This 2-bit field indicates TOFFSET and one of four values can be selected. This field is meaningless if the ERASE_SIZE and ERASE_TIMEOUT fields are set to 0. Table 233. Erase offset field ERASE_OFFSET Value definition 0h 0 [sec] 1h 1 [sec] DocID024597 Rev 1 1415/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 Table 233. Erase offset field ERASE_OFFSET 41.4.13 Value definition 2h 2 [sec] 3h 3 [sec] SD I/O mode SD I/O interrupts To allow the SD I/O card to interrupt the MultiMediaCard/SD module, an interrupt function is available on a pin on the SD interface. Pin 8, used as SDMMC_D1 when operating in the 4bit SD mode, signals the cards interrupt to the MultiMediaCard/SD module. The use of the interrupt is optional for each card or function within a card. The SD I/O interrupt is levelsensitive, which means that the interrupt line must be held active (low) until it is either recognized and acted upon by the MultiMediaCard/SD module or deasserted due to the end of the interrupt period. After the MultiMediaCard/SD module has serviced the interrupt, the interrupt status bit is cleared via an I/O write to the appropriate bit in the SD I/O card’s internal registers. The interrupt output of all SD I/O cards is active low and the application must provide pull-up resistors externally on all data lines (SDMMC_D[3:0]). The MultiMediaCard/SD module samples the level of pin 8 (SDMMC_D/IRQ) into the interrupt detector only during the interrupt period. At all other times, the MultiMediaCard/SD module ignores this value. The interrupt period is applicable for both memory and I/O operations. The definition of the interrupt period for operations with single blocks is different from the definition for multipleblock data transfers. SD I/O suspend and resume Within a multifunction SD I/O or a card with both I/O and memory functions, there are multiple devices (I/O and memory) that share access to the MMC/SD bus. To share access to the MMC/SD module among multiple devices, SD I/O and combo cards optionally implement the concept of suspend/resume. When a card supports suspend/resume, the MMC/SD module can temporarily halt a data transfer operation to one function or memory (suspend) to free the bus for a higher-priority transfer to a different function or memory. After this higher-priority transfer is complete, the original transfer is resumed (restarted) where it left off. Support of suspend/resume is optional on a per-card basis. To perform the suspend/resume operation on the MMC/SD bus, the MMC/SD module performs the following steps: 1. Determines the function currently using the SDMMC_D [3:0] line(s) 2. Requests the lower-priority or slower transaction to suspend 3. Waits for the transaction suspension to complete 4. Begins the higher-priority transaction 5. Waits for the completion of the higher priority transaction 6. Restores the suspended transaction SD I/O ReadWait The optional ReadWait (RW) operation is defined only for the SD 1-bit and 4-bit modes. The ReadWait operation allows the MMC/SD module to signal a card that it is reading multiple 1416/1680 DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) registers (IO_RW_EXTENDED, CMD53) to temporarily stall the data transfer while allowing the MMC/SD module to send commands to any function within the SD I/O device. To determine when a card supports the ReadWait protocol, the MMC/SD module must test capability bits in the internal card registers. The timing for ReadWait is based on the interrupt period. 41.4.14 Commands and responses Application-specific and general commands The SDMMC card host module system is designed to provide a standard interface for a variety of applications types. In this environment, there is a need for specific customer/application features. To implement these features, two types of generic commands are defined in the standard: application-specific commands (ACMD) and general commands (GEN_CMD). When the card receives the APP_CMD (CMD55) command, the card expects the next command to be an application-specific command. ACMDs have the same structure as regular MultiMediaCard commands and can have the same CMD number. The card recognizes it as ACMD because it appears after APP_CMD (CMD55). When the command immediately following the APP_CMD (CMD55) is not a defined application-specific command, the standard command is used. For example, when the card has a definition for SD_STATUS (ACMD13), and receives CMD13 immediately following APP_CMD (CMD55), this is interpreted as SD_STATUS (ACMD13). However, when the card receives CMD7 immediately following APP_CMD (CMD55) and the card does not have a definition for ACMD7, this is interpreted as the standard (SELECT/DESELECT_CARD) CMD7. To use one of the manufacturer-specific ACMDs the SD card Host must perform the following steps: 1. Send APP_CMD (CMD55) The card responds to the MultiMediaCard/SD module, indicating that the APP_CMD bit is set and an ACMD is now expected. 2. Send the required ACMD The card responds to the MultiMediaCard/SD module, indicating that the APP_CMD bit is set and that the accepted command is interpreted as an ACMD. When a nonACMD is sent, it is handled by the card as a normal MultiMediaCard command and the APP_CMD bit in the card status register stays clear. When an invalid command is sent (neither ACMD nor CMD) it is handled as a standard MultiMediaCard illegal command error. The bus transaction for a GEN_CMD is the same as the single-block read or write commands (WRITE_BLOCK, CMD24 or READ_SINGLE_BLOCK,CMD17). In this case, the argument denotes the direction of the data transfer rather than the address, and the data block has vendor-specific format and meaning. The card must be selected (in transfer state) before sending GEN_CMD (CMD56). The data block size is defined by SET_BLOCKLEN (CMD16). The response to GEN_CMD (CMD56) is in R1b format. DocID024597 Rev 1 1417/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 Command types Both application-specific and general commands are divided into the four following types: • broadcast command (BC): sent to all cards; no responses returned. • broadcast command with response (BCR): sent to all cards; responses received from all cards simultaneously. • addressed (point-to-point) command (AC): sent to the card that is selected; does not include a data transfer on the SDMMC_D line(s). • addressed (point-to-point) data transfer command (ADTC): sent to the card that is selected; includes a data transfer on the SDMMC_D line(s). Command formats See Table 217 on page 1392 for command formats. Commands for the MultiMediaCard/SD module Table 234. Block-oriented write commands CMD index Type Argument Response format Abbreviation Description CMD23 ac [31:16] set to 0 [15:0] number R1 of blocks SET_BLOCK_COUNT Defines the number of blocks which are going to be transferred in the multiple-block read or write command that follows. CMD24 adtc [31:0] data address R1 WRITE_BLOCK Writes a block of the size selected by the SET_BLOCKLEN command. CMD25 adtc [31:0] data address R1 Continuously writes blocks of data until a STOP_TRANSMISSION WRITE_MULTIPLE_BLOCK follows or the requested number of blocks has been received. CMD26 adtc [31:0] stuff bits R1 PROGRAM_CID Programming of the card identification register. This command must be issued only once per card. The card contains hardware to prevent this operation after the first programming. Normally this command is reserved for manufacturer. CMD27 adtc [31:0] stuff bits R1 PROGRAM_CSD Programming of the programmable bits of the CSD. 1418/1680 DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) Table 235. Block-oriented write protection commands CMD index Type Argument Response format Abbreviation Description CMD28 ac [31:0] data address R1b SET_WRITE_PROT If the card has write protection features, this command sets the write protection bit of the addressed group. The properties of write protection are coded in the cardspecific data (WP_GRP_SIZE). CMD29 ac [31:0] data address R1b CLR_WRITE_PROT If the card provides write protection features, this command clears the write protection bit of the addressed group. CMD30 adtc [31:0] write protect data address SEND_WRITE_PROT If the card provides write protection features, this command asks the card to send the status of the write protection bits. R1 CMD31 Reserved Table 236. Erase commands CMD index Type Argument Response format Abbreviation Description CMD32 Reserved. These command indexes cannot be used in order to maintain backward compatibility with older ... versions of the MultiMediaCard. CMD34 CMD35 ac [31:0] data address R1 Sets the address of the first erase ERASE_GROUP_START group within a range to be selected for erase. CMD36 ac [31:0] data address R1 ERASE_GROUP_END CMD37 Sets the address of the last erase group within a continuous range to be selected for erase. Reserved. This command index cannot be used in order to maintain backward compatibility with older versions of the MultiMediaCards CMD38 ac [31:0] stuff bits R1 Erases all previously selected write blocks. ERASE Table 237. I/O mode commands CMD index Type CMD39 ac Argument [31:16] RCA [15:15] register write flag [14:8] register address [7:0] register data Response format R4 Abbreviation FAST_IO DocID024597 Rev 1 Description Used to write and read 8-bit (register) data fields. The command addresses a card and a register and provides the data for writing if the write flag is set. The R4 response contains data read from the addressed register. This command accesses application-dependent registers that are not defined in the MultiMediaCard standard. 1419/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 Table 237. I/O mode commands (continued) CMD index Type CMD40 bcr Response format Argument [31:0] stuff bits R5 Abbreviation Description GO_IRQ_STATE Places the system in the interrupt mode. CMD41 Reserved Table 238. Lock card CMD index Type CMD42 adtc Response format Argument [31:0] stuff bits Abbreviation R1b Description Sets/resets the password or locks/unlocks the card. The size of the data block is set by the SET_BLOCK_LEN command. LOCK_UNLOCK CMD43 ... Reserved CMD54 Table 239. Application-specific commands CMD index CMD55 Type ac Argument [31:16] RCA [15:0] stuff bits Response format R1 [31:1] stuff bits [0]: RD/WR CMD56 adtc CMD57 ... CMD59 Reserved. CMD60 ... CMD63 Reserved for manufacturer. 41.5 Abbreviation APP_CMD - - Description Indicates to the card that the next command bits is an application specific command rather than a standard command Used either to transfer a data block to the card or to get a data block from the card for general purpose/application-specific commands. The size of the data block shall be set by the SET_BLOCK_LEN command. Response formats All responses are sent via the SDMMC command line SDMMC_CMD. The response transmission always starts with the left bit of the bit string corresponding to the response code word. The code length depends on the response type. A response always starts with a start bit (always 0), followed by the bit indicating the direction of transmission (card = 0). A value denoted by x in the tables below indicates a variable entry. All responses, except for the R3 response type, are protected by a CRC. Every command code word is terminated by the end bit (always 1). There are five types of responses. Their formats are defined as follows: 1420/1680 DocID024597 Rev 1 RM0351 41.5.1 SD/SDIO/MMC card host interface (SDMMC) R1 (normal response command) Code length = 48 bits. The 45:40 bits indicate the index of the command to be responded to, this value being interpreted as a binary-coded number (between 0 and 63). The status of the card is coded in 32 bits. Table 240. R1 response Bit position 41.5.2 Width (bits Value Description 47 1 0 Start bit 46 1 0 Transmission bit [45:40] 6 X Command index [39:8] 32 X Card status [7:1] 7 X CRC7 0 1 1 End bit R1b It is identical to R1 with an optional busy signal transmitted on the data line. The card may become busy after receiving these commands based on its state prior to the command reception. 41.5.3 R2 (CID, CSD register) Code length = 136 bits. The contents of the CID register are sent as a response to the CMD2 and CMD10 commands. The contents of the CSD register are sent as a response to CMD9. Only the bits [127...1] of the CID and CSD are transferred, the reserved bit [0] of these registers is replaced by the end bit of the response. The card indicates that an erase is in progress by holding SDMMC_D0 low. The actual erase time may be quite long, and the host may issue CMD7 to deselect the card. Table 241. R2 response Bit position Width (bits Value Description 135 1 0 Start bit 134 1 0 Transmission bit [133:128] 6 ‘111111’ Command index [127:1] 127 X Card status 0 1 1 End bit DocID024597 Rev 1 1421/1680 1441 SD/SDIO/MMC card host interface (SDMMC) 41.5.4 RM0351 R3 (OCR register) Code length: 48 bits. The contents of the OCR register are sent as a response to CMD1. The level coding is as follows: restricted voltage windows = low, card busy = low. Table 242. R3 response Bit position 41.5.5 Width (bits Value Description 47 1 0 Start bit 46 1 0 Transmission bit [45:40] 6 ‘111111’ Reserved [39:8] 32 X OCR register [7:1] 7 ‘1111111’ Reserved 0 1 1 End bit R4 (Fast I/O) Code length: 48 bits. The argument field contains the RCA of the addressed card, the register address to be read out or written to, and its content. Table 243. R4 response Bit position Value Description 47 1 0 Start bit 46 1 0 Transmission bit [45:40] 6 ‘100111’ CMD39 [31:16] 16 X RCA [15:8] 8 X register address [7:0] 8 X read register contents [7:1] 7 X CRC7 0 1 1 End bit [39:8] Argument field 41.5.6 Width (bits R4b For SD I/O only: an SDIO card receiving the CMD5 will respond with a unique SDIO response R4. The format is: Table 244. R4b response Bit position 1422/1680 Width (bits Value Description 47 1 0 Start bit 46 1 0 Transmission bit [45:40] 6 X Reserved DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) Table 244. R4b response (continued) Bit position Width (bits Value Description 39 16 X Card is ready [38:36] 3 X Number of I/O functions 35 1 X Present memory [34:32] 3 X Stuff bits [31:8] 24 X I/O ORC [7:1] 7 X Reserved 0 1 1 End bit [39:8] Argument field Once an SD I/O card has received a CMD5, the I/O portion of that card is enabled to respond normally to all further commands. This I/O enable of the function within the I/O card will remain set until a reset, power cycle or CMD52 with write to I/O reset is received by the card. Note that an SD memory-only card may respond to a CMD5. The proper response for a memory-only card would be Present memory = 1 and Number of I/O functions = 0. A memory-only card built to meet the SD Memory Card specification version 1.0 would detect the CMD5 as an illegal command and not respond. The I/O aware host will send CMD5. If the card responds with response R4, the host determines the card’s configuration based on the data contained within the R4 response. 41.5.7 R5 (interrupt request) Only for MultiMediaCard. Code length: 48 bits. If the response is generated by the host, the RCA field in the argument will be 0x0. Table 245. R5 response Bit position Width (bits Value 47 1 0 Start bit 46 1 0 Transmission bit [45:40] 6 ‘101000’ CMD40 [31:16] 16 X RCA [31:16] of winning card or of the host [15:0] 16 X Not defined. May be used for IRQ data [7:1] 7 X CRC7 0 1 1 End bit [39:8] Argument field 41.5.8 Description R6 Only for SD I/O. The normal response to CMD3 by a memory device. It is shown in Table 246. DocID024597 Rev 1 1423/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 Table 246. R6 response Bit position Width (bits) Value Description 47 1 0 Start bit 46 1 0 Transmission bit [45:40] 6 ‘101000’ CMD40 [31:16] 16 X RCA [31:16] of winning card or of the host [15:0] 16 X Not defined. May be used for IRQ data [7:1] 7 X CRC7 0 1 1 End bit [39:8] Argument field The card [23:8] status bits are changed when CMD3 is sent to an I/O-only card. In this case, the 16 bits of response are the SD I/O-only values: 41.6 • Bit [15] COM_CRC_ERROR • Bit [14] ILLEGAL_COMMAND • Bit [13] ERROR • Bits [12:0] Reserved SDIO I/O card-specific operations The following features are SD I/O-specific operations: • SDIO read wait operation by SDMMC_D2 signalling • SDIO read wait operation by stopping the clock • SDIO suspend/resume operation (write and read suspend) • SDIO interrupts The SDMMC supports these operations only if the SDMMC_DCTRL[11] bit is set, except for read suspend that does not need specific hardware implementation. 41.6.1 SDIO I/O read wait operation by SDMMC_D2 signalling It is possible to start the readwait interval before the first block is received: when the data path is enabled (SDMMC_DCTRL[0] bit set), the SDIO-specific operation is enabled (SDMMC_DCTRL[11] bit set), read wait starts (SDMMC_DCTRL[10] =0 and SDMMC_DCTRL[8] =1) and data direction is from card to SDMMC (SDMMC_DCTRL[1] = 1), the DPSM directly moves from Idle to Readwait. In Readwait the DPSM drives SDMMC_D2 to 0 after 2 SDMMC_CK clock cycles. In this state, when you set the RWSTOP bit (SDMMC_DCTRL[9]), the DPSM remains in Wait for two more SDMMC_CK clock cycles to drive SDMMC_D2 to 1 for one clock cycle (in accordance with SDIO specification). The DPSM then starts waiting again until it receives data from the card. The DPSM will not start a readwait interval while receiving a block even if read wait start is set: the readwait interval will start after the CRC is received. The RWSTOP bit has to be cleared to start a new read wait operation. During the readwait interval, the SDMMC can detect SDIO interrupts on SDMMC_D1. 1424/1680 DocID024597 Rev 1 RM0351 41.6.2 SD/SDIO/MMC card host interface (SDMMC) SDIO read wait operation by stopping SDMMC_CK If the SDIO card does not support the previous read wait method, the SDMMC can perform a read wait by stopping SDMMC_CK (SDMMC_DCTRL is set just like in the method presented in Section 41.6.1, but SDMMC_DCTRL[10] =1): DSPM stops the clock two SDMMC_CK cycles after the end bit of the current received block and starts the clock again after the read wait start bit is set. As SDMMC_CK is stopped, any command can be issued to the card. During a read/wait interval, the SDMMC can detect SDIO interrupts on SDMMC_D1. 41.6.3 SDIO suspend/resume operation While sending data to the card, the SDMMC can suspend the write operation. the SDMMC_CMD[11] bit is set and indicates to the CPSM that the current command is a suspend command. The CPSM analyzes the response and when the ACK is received from the card (suspend accepted), it acknowledges the DPSM that goes Idle after receiving the CRC token of the current block. The hardware does not save the number of the remaining block to be sent to complete the suspended operation (resume). The write operation can be suspended by software, just by disabling the DPSM (SDMMC_DCTRL[0] =0) when the ACK of the suspend command is received from the card. The DPSM enters then the Idle state. To suspend a read: the DPSM waits in the Wait_r state as the function to be suspended sends a complete packet just before stopping the data transaction. The application continues reading RxFIFO until the FIF0 is empty, and the DPSM goes Idle automatically. 41.6.4 SDIO interrupts SDIO interrupts are detected on the SDMMC_D1 line once the SDMMC_DCTRL[11] bit is set. When SDIO interrupt is detected, SDMMC_STA[22] (SDIOIT) bit is set. This static bit can be cleared with clear bit SDMMC_ICR[22] (SDIOITC). An interrupt can be generated when SDIOIT status bit is set. Separated interrupt enable SDMMC_MASK[22] bit (SDIOITE) is available to enable and disable interrupt request. When SD card interrupt occurs (SDMMC_STA[22] bit set), host software follows below steps to handle it. 1. Disable SDIOIT interrupt signaling by clearing SDIOITE bit (SDMMC_MASK[22] = ‘0’), 2. Serve card interrupt request, and clear the source of interrupt on the SD card, 3. Clear SDIOIT bit by writing ‘1’ to SDIOITC bit (SDMMC_ICR[22] = ‘1’), 4. Enable SDIOIT interrupt signaling by writing ‘1’ to SDIOITE bit (SDMMC_MASK[22] = ‘1’). Steps 2 to 4can be executed out of the SDIO interrupt service routine. 41.7 HW flow control The HW flow control functionality is used to avoid FIFO underrun (TX mode) and overrun (RX mode) errors. DocID024597 Rev 1 1425/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 The behavior is to stop SDMMC_CK and freeze SDMMC state machines. The data transfer is stalled while the FIFO is unable to transmit or receive data. Only state machines clocked by SDMMCCLK are frozen, the APB2 interface is still alive. The FIFO can thus be filled or emptied even if flow control is activated. To enable HW flow control, the SDMMC_CLKCR[14] register bit must be set to 1. After reset Flow Control is disabled. 41.8 SDMMC registers The device communicates to the system via 32-bit-wide control registers accessible via APB2. 41.8.1 SDMMC power control register (SDMMC_POWER) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PWRCTRL rw rw Bits 31:2 Reserved, must be kept at reset value. [1:0] PWRCTRL: Power supply control bits. These bits are used to define the current functional state of the card clock: 00: Power-off: the clock to card is stopped. 01: Reserved 10: Reserved power-up 11: Power-on: the card is clocked. Note: At least seven PCLK2 clock periods are needed between two write accesses to this register. Note: After a data write, data cannot be written to this register for three SDMMCCLK (48 MHz) clock periods plus two PCLK2 clock periods. 41.8.2 SDMMC clock control register (SDMMC_CLKCR) Address offset: 0x04 Reset value: 0x0000 0000 The SDMMC_CLKCR register controls the SDMMC_CK output clock. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1426/1680 DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) 15 14 13 Res. HWFC _EN NEGE DGE rw rw 12 11 WID BUS rw 10 9 8 7 6 5 BYPAS PWRS CLKEN S AV rw rw rw rw 4 3 2 1 0 rw rw rw CLKDIV rw rw rw rw rw Bits 31:15 Reserved, must be kept at reset value. Bit 14 HWFC_EN: HW Flow Control enable 0b: HW Flow Control is disabled 1b: HW Flow Control is enabled When HW Flow Control is enabled, the meaning of the TXFIFOE and RXFIFOF interrupt signals, please see SDMMC Status register definition in Section 41.8.11. Bit 13 NEGEDGE: SDMMC_CK dephasing selection bit 0b: Command and Data changed on the SDMMCCLK falling edge succeeding the rising edge of SDMMC_CK. (SDMMC_CK rising edge occurs on SDMMCCLK rising edge). 1b: Command and Data changed on the SDMMC_CK falling edge. When BYPASS is active, the data and the command change on SDMMCCLK falling edge whatever NEGEDGE value. Bits 12:11 WIDBUS: Wide bus mode enable bit 00: Default bus mode: SDMMC_D0 used 01: 4-wide bus mode: SDMMC_D[3:0] used 10: 8-wide bus mode: SDMMC_D[7:0] used Bit 10 BYPASS: Clock divider bypass enable bit 0: Disable bypass: SDMMCCLK is divided according to the CLKDIV value before driving the SDMMC_CK output signal. 1: Enable bypass: SDMMCCLK directly drives the SDMMC_CK output signal. Bit 9 PWRSAV: Power saving configuration bit For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV: 0: SDMMC_CK clock is always enabled 1: SDMMC_CK is only enabled when the bus is active Bit 8 CLKEN: Clock enable bit 0: SDMMC_CK is disabled 1: SDMMC_CK is enabled Bits 7:0 CLKDIV: Clock divide factor This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [CLKDIV + 2]. Note: 1 While the SD/SDIO card or MultiMediaCard is in identification mode, the SDMMC_CK frequency must be less than 400 kHz. 2 The clock frequency can be changed to the maximum card bus frequency when relative card addresses are assigned to all cards. 3 After a data write, data cannot be written to this register for three SDMMCCLK (48 MHz) clock periods plus two PCLK2 clock periods. SDMMC_CK can also be stopped during the read wait interval for SD I/O cards: in this case the SDMMC_CLKCR register does not control SDMMC_CK. DocID024597 Rev 1 1427/1680 1441 SD/SDIO/MMC card host interface (SDMMC) 41.8.3 RM0351 SDMMC argument register (SDMMC_ARG) Address offset: 0x08 Reset value: 0x0000 0000 The SDMMC_ARG register contains a 32-bit command argument, which is sent to a card as part of a command message. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CMDARG[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CMDARG[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 CMDARG: Command argument Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register. 41.8.4 SDMMC command register (SDMMC_CMD) Address offset: 0x0C Reset value: 0x0000 0000 The SDMMC_CMD register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. SDIO Suspend CPSM EN WAIT PEND WAIT INT rw rw rw rw rw rw Res. Res. Res. WAITRESP rw rw CMDINDEX rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bit 11 SDIOSuspend: SD I/O suspend command If this bit is set, the command to be sent is a suspend command (to be used only with SDIO card). Bit 10 CPSMEN: Command path state machine (CPSM) Enable bit If this bit is set, the CPSM is enabled. Bit 9 WAITPEND: CPSM Waits for ends of data transfer (CmdPend internal signal). If this bit is set, the CPSM waits for the end of data transfer before it starts sending a command. This feature is available only with Stream data transfer mode SDMMC_DCTRL[2] = 1 1428/1680 DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) Bit 8 WAITINT: CPSM waits for interrupt request If this bit is set, the CPSM disables command timeout and waits for an interrupt request. Bits 7:6 WAITRESP: Wait for response bits They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response. 00: No response, expect CMDSENT flag 01: Short response, expect CMDREND or CCRCFAIL flag 10: No response, expect CMDSENT flag 11: Long response, expect CMDREND or CCRCFAIL flag Bits 5:0 CMDINDEX: Command index The command index is sent to the card as part of a command message. Note: 1 After a data write, data cannot be written to this register for three SDMMCCLK (48 MHz) clock periods plus two PCLK2 clock periods. 2 MultiMediaCards can send two kinds of response: short responses, 48 bits long, or long responses,136 bits long. SD card and SD I/O card can send only short responses, the argument can vary according to the type of response: the software will distinguish the type of response according to the sent command. 41.8.5 SDMMC command response register (SDMMC_RESPCMD) Address offset: 0x10 Reset value: 0x0000 0000 The SDMMC_RESPCMD register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 5 4 3 2 1 0 r r 15 14 13 12 11 10 9 8 7 6 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RESPCMD r r r r Bits 31:6 Reserved, must be kept at reset value. Bits 5:0 RESPCMD: Response command index Read-only bit field. Contains the command index of the last command response received. 41.8.6 SDMMC response 1..4 register (SDMMC_RESPx) Address offset: (0x10 + (4 × x)); x = 1..4 Reset value: 0x0000 0000 The SDMMC_RESP1/2/3/4 registers contain the status of a card, which is part of the received response. DocID024597 Rev 1 1429/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r CARDSTATUSx[31:16] CARDSTATUSx[15:0] r r r r r r r r r Bits 31:0 CARDSTATUSx: see Table 247. The Card Status size is 32 or 127 bits, depending on the response type. Table 247. Response type and SDMMC_RESPx registers Register Short response Long response SDMMC_RESP1 Card Status[31:0] Card Status [127:96] SDMMC_RESP2 Unused Card Status [95:64] SDMMC_RESP3 Unused Card Status [63:32] SDMMC_RESP4 Unused Card Status [31:1]0b The most significant bit of the card status is received first. The SDMMC_RESP4 register LSB is always 0b. 41.8.7 SDMMC data timer register (SDMMC_DTIMER) Address offset: 0x24 Reset value: 0x0000 0000 The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. 31 30 29 28 27 26 25 24 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DATATIME[31:16] DATATIME[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 DATATIME: Data timeout period Data timeout period expressed in card bus clock periods. Note: 1430/1680 A data transfer must be written to the data timer register and the data length register before being written to the data control register. DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) 41.8.8 SDMMC data length register (SDMMC_DLEN) Address offset: 0x28 Reset value: 0x0000 0000 The SDMMC_DLEN register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. 31 30 29 28 27 26 25 Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 rw rw rw rw rw rw rw 24 23 22 21 20 19 18 17 16 DATALENGTH[24:16] rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DATALENGTH[15:0] rw rw Bits 31:25 Reserved, must be kept at reset value. Bits 24:0 DATALENGTH: Data length value Number of data bytes to be transferred. Note: For a block data transfer, the value in the data length register must be a multiple of the block size (see SDMMC_DCTRL). A data transfer must be written to the data timer register and the data length register before being written to the data control register. For an SDMMC multibyte transfer the value in the data length register must be between 1 and 512. 41.8.9 SDMMC data control register (SDMMC_DCTRL) Address offset: 0x2C Reset value: 0x0000 0000 The SDMMC_DCTRL register control the data path state machine (DPSM). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. SDIO EN RW MOD RW STOP RW START DMA EN DT MODE DTDIR DTEN rw rw rw rw rw rw rw rw DBLOCKSIZE rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bit 11 SDIOEN: SD I/O enable functions If this bit is set, the DPSM performs an SD I/O-card-specific operation. Bit 10 RWMOD: Read wait mode 0: Read Wait control stopping SDMMC_D2 1: Read Wait control using SDMMC_CK DocID024597 Rev 1 1431/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 Bit 9 RWSTOP: Read wait stop 0: Read wait in progress if RWSTART bit is set 1: Enable for read wait stop if RWSTART bit is set Bit 8 RWSTART: Read wait start If this bit is set, read wait operation starts. Bits 7:4 DBLOCKSIZE: Data block size Define the data block length when the block data transfer mode is selected: 0000: (0 decimal) lock length = 20 = 1 byte 0001: (1 decimal) lock length = 21 = 2 bytes 0010: (2 decimal) lock length = 22 = 4 bytes 0011: (3 decimal) lock length = 23 = 8 bytes 0100: (4 decimal) lock length = 24 = 16 bytes 0101: (5 decimal) lock length = 25 = 32 bytes 0110: (6 decimal) lock length = 26 = 64 bytes 0111: (7 decimal) lock length = 27 = 128 bytes 1000: (8 decimal) lock length = 28 = 256 bytes 1001: (9 decimal) lock length = 29 = 512 bytes 1010: (10 decimal) lock length = 210 = 1024 bytes 1011: (11 decimal) lock length = 211 = 2048 bytes 1100: (12 decimal) lock length = 212 = 4096 bytes 1101: (13 decimal) lock length = 213 = 8192 bytes 1110: (14 decimal) lock length = 214 = 16384 bytes 1111: (15 decimal) reserved Bit 3 DMAEN: DMA enable bit 0: DMA disabled. 1: DMA enabled. Bit 2 DTMODE: Data transfer mode selection 1: Stream or SDIO multibyte data transfer. 0: Block data transfer 1: Stream or SDIO multibyte data transfer Bit 1 DTDIR: Data transfer direction selection 0: From controller to card. 1: From card to controller. [0] DTEN: Data transfer enabled bit Data transfer starts if 1b is written to the DTEN bit. Depending on the direction bit, DTDIR, the DPSM moves to the Wait_S, Wait_R state or Readwait if RW Start is set immediately at the beginning of the transfer. It is not necessary to clear the enable bit after the end of a data transfer but the SDMMC_DCTRL must be updated to enable a new data transfer Note: After a data write, data cannot be written to this register for three SDMMCCLK (48 MHz) clock periods plus two PCLK2 clock periods. The meaning of the DTMODE bit changes according to the value of the SDIOEN bit. When SDIOEN=0 and DTMODE=1, the MultiMediaCard stream mode is enabled, and when SDIOEN=1 and DTMODE=1, the peripheral enables an SDIO multibyte transfer. 1432/1680 DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) 41.8.10 SDMMC data counter register (SDMMC_DCOUNT) Address offset: 0x30 Reset value: 0x0000 0000 The SDMMC_DCOUNT register loads the value from the data length register (see SDMMC_DLEN) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and the data status end flag, DATAEND, is set. 31 30 29 28 27 26 25 Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 r r r r r r r 24 23 22 21 20 19 18 17 16 DATACOUNT[24:16] r r r r r r r r r 8 7 6 5 4 3 2 1 0 r r r r r r r DATACOUNT[15:0] r r Bits 31:25 Reserved, must be kept at reset value. Bits 24:0 DATACOUNT: Data count value When this bit is read, the number of remaining data bytes to be transferred is returned. Write has no effect. Note: This register should be read only when the data transfer is complete. 41.8.11 SDMMC status register (SDMMC_STA) Address offset: 0x34 Reset value: 0x0000 0000 The SDMMC_STA register is a read-only register. It contains two types of flag: • Static flags (bits [23:22,10:0]): these bits remain asserted until they are cleared by writing to the SDMMC Interrupt Clear register (see SDMMC_ICR) • Dynamic flags (bits [21:11]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and deasserted as data while written to the FIFO) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. SDIOIT RXD AVL TXD AVL RX FIFOE TX FIFOE RX FIFOF TX FIFOF r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RX FIFO HF TX FIFO HE CMD ACT DBCK END Res. DATA END CMDS ENT DCRC FAIL CCRC FAIL r r r r r r r r RXACT TXACT r r CMDR RX TXUND DTIME CTIME END OVERR ERR OUT OUT r r r r r Bits 31:23 Reserved, must be kept at reset value. Bit 22 SDIOIT: SDIO interrupt received Bit 21 RXDAVL: Data available in receive FIFO DocID024597 Rev 1 1433/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 Bit 20 TXDAVL: Data available in transmit FIFO Bit 19 RXFIFOE: Receive FIFO empty Bit 18 TXFIFOE: Transmit FIFO empty When HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO contains 2 words. Bit 17 RXFIFOF: Receive FIFO full When HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the FIFO is full. Bit 16 TXFIFOF: Transmit FIFO full Bit 15 RXFIFOHF: Receive FIFO half full: there are at least 8 words in the FIFO Bit 14 TXFIFOHE: Transmit FIFO half empty: at least 8 words can be written into the FIFO Bit 13 RXACT: Data receive in progress Bit 12 TXACT: Data transmit in progress Bit 11 CMDACT: Command transfer in progress Bit 10 DBCKEND: Data block sent/received (CRC check passed) Bit 9 Reserved, must be kept at reset value. Bit 8 DATAEND: Data end (data counter, SDIDCOUNT, is zero) Bit 7 CMDSENT: Command sent (no response required) Bit 6 CMDREND: Command response received (CRC check passed) Bit 5 RXOVERR: Received FIFO overrun error Note: If DMA is used to read SDMMC FIFO (DMAEN bit is set in SDMMC_DCTRL register), user software should disable DMA stream, and then write with ‘0’ (to disable DMA request generation). Bit 4 TXUNDERR: Transmit FIFO underrun error Note: If DMA is used to fill SDMMC FIFO (DMAEN bit is set in SDMMC_DCTRL register), user software should disable DMA stream, and then write DMAEN with ‘0’ (to disable DMA request generation). Bit 3 DTIMEOUT: Data timeout Bit 2 CTIMEOUT: Command response timeout The Command TimeOut period has a fixed value of 64 SDMMC_CK clock periods. Bit 1 DCRCFAIL: Data block sent/received (CRC check failed) Bit 0 CCRCFAIL: Command response received (CRC check failed) 41.8.12 SDMMC interrupt clear register (SDMMC_ICR) Address offset: 0x38 Reset value: 0x0000 0000 The SDMMC_ICR register is a write-only register. Writing a bit with 1b clears the corresponding bit in the SDMMC_STA Status register. 1434/1680 DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. SDIO ITC Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 5 4 3 2 1 0 DCRC FAILC CCRC FAILC rw rw rw Res. Res. Res. Res. Res. DBCK ENDC rw Res. 6 CMD DATA CMD REND ENDC SENTC C rw rw rw RX TX DTIME CTIME OVERR UNDERR OUTC OUTC C C rw rw rw rw Bits 31:23 Reserved, must be kept at reset value. Bit 22 SDIOITC: SDIOIT flag clear bit Set by software to clear the SDIOIT flag. 0: SDIOIT not cleared 1: SDIOIT cleared Bits 21:11 Reserved, must be kept at reset value. Bit 10 DBCKENDC: DBCKEND flag clear bit Set by software to clear the DBCKEND flag. 0: DBCKEND not cleared 1: DBCKEND cleared Bit 9 Reserved, must be kept at reset value. Bit 8 DATAENDC: DATAEND flag clear bit Set by software to clear the DATAEND flag. 0: DATAEND not cleared 1: DATAEND cleared Bit 7 CMDSENTC: CMDSENT flag clear bit Set by software to clear the CMDSENT flag. 0: CMDSENT not cleared 1: CMDSENT cleared Bit 6 CMDRENDC: CMDREND flag clear bit Set by software to clear the CMDREND flag. 0: CMDREND not cleared 1: CMDREND cleared Bit 5 RXOVERRC: RXOVERR flag clear bit Set by software to clear the RXOVERR flag. 0: RXOVERR not cleared 1: RXOVERR cleared Bit 4 TXUNDERRC: TXUNDERR flag clear bit Set by software to clear TXUNDERR flag. 0: TXUNDERR not cleared 1: TXUNDERR cleared Bit 3 DTIMEOUTC: DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag. 0: DTIMEOUT not cleared 1: DTIMEOUT cleared DocID024597 Rev 1 1435/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 Bit 2 CTIMEOUTC: CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag. 0: CTIMEOUT not cleared 1: CTIMEOUT cleared Bit 1 DCRCFAILC: DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag. 0: DCRCFAIL not cleared 1: DCRCFAIL cleared Bit 0 CCRCFAILC: CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag. 0: CCRCFAIL not cleared 1: CCRCFAIL cleared 41.8.13 SDMMC mask register (SDMMC_MASK) Address offset: 0x3C Reset value: 0x0000 0000 The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1b. 31 30 29 28 27 26 25 24 23 22 20 19 18 17 16 TX FIFO EIE RX FIFO FIE TX FIFO FIE SDIO ITIE RXD AVLIE TXD AVLIE RX FIFO EIE rw rw rw rw rw rw rw 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 RX FIFO HFIE TX FIFO HEIE RX ACTIE TX ACTIE CMD ACTIE DBCK ENDIE DATA ENDIE CMD SENT IE CMD REND IE rw rw rw rw rw rw rw rw rw Res. 21 RX TX DTIME CTIME DCRC OVERR UNDERR OUTIE OUTIE FAILIE IE IE rw rw rw rw rw CCRC FAILIE rw Bits 31:23 Reserved, must be kept at reset value. Bit 22 SDIOITIE: SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt. 0: SDIO Mode Interrupt Received interrupt disabled 1: SDIO Mode Interrupt Received interrupt enabled Bit 21 RXDAVLIE: Data available in Rx FIFO interrupt enable Set and cleared by software to enable/disable the interrupt generated by the presence of data available in Rx FIFO. 0: Data available in Rx FIFO interrupt disabled 1: Data available in Rx FIFO interrupt enabled Bit 20 TXDAVLIE: Data available in Tx FIFO interrupt enable Set and cleared by software to enable/disable the interrupt generated by the presence of data available in Tx FIFO. 0: Data available in Tx FIFO interrupt disabled 1: Data available in Tx FIFO interrupt enabled 1436/1680 DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) Bit 19 RXFIFOEIE: Rx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO empty. 0: Rx FIFO empty interrupt disabled 1: Rx FIFO empty interrupt enabled Bit 18 TXFIFOEIE: Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty. 0: Tx FIFO empty interrupt disabled 1: Tx FIFO empty interrupt enabled Bit 17 RXFIFOFIE: Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full. 0: Rx FIFO full interrupt disabled 1: Rx FIFO full interrupt enabled Bit 16 TXFIFOFIE: Tx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO full. 0: Tx FIFO full interrupt disabled 1: Tx FIFO full interrupt enabled Bit 15 RXFIFOHFIE: Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full. 0: Rx FIFO half full interrupt disabled 1: Rx FIFO half full interrupt enabled Bit 14 TXFIFOHEIE: Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty. 0: Tx FIFO half empty interrupt disabled 1: Tx FIFO half empty interrupt enabled Bit 13 RXACTIE: Data receive acting interrupt enable Set and cleared by software to enable/disable interrupt caused by data being received (data receive acting). 0: Data receive acting interrupt disabled 1: Data receive acting interrupt enabled Bit 12 TXACTIE: Data transmit acting interrupt enable Set and cleared by software to enable/disable interrupt caused by data being transferred (data transmit acting). 0: Data transmit acting interrupt disabled 1: Data transmit acting interrupt enabled Bit 11 CMDACTIE: Command acting interrupt enable Set and cleared by software to enable/disable interrupt caused by a command being transferred (command acting). 0: Command acting interrupt disabled 1: Command acting interrupt enabled Bit 10 DBCKENDIE: Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end. 0: Data block end interrupt disabled 1: Data block end interrupt enabled Bit 9 Reserved, must be kept at reset value. DocID024597 Rev 1 1437/1680 1441 SD/SDIO/MMC card host interface (SDMMC) RM0351 Bit 8 DATAENDIE: Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end. 0: Data end interrupt disabled 1: Data end interrupt enabled Bit 7 CMDSENTIE: Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command. 0: Command sent interrupt disabled 1: Command sent interrupt enabled Bit 6 CMDRENDIE: Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. 0: Command response received interrupt disabled 1: command Response Received interrupt enabled Bit 5 RXOVERRIE: Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error. 0: Rx FIFO overrun error interrupt disabled 1: Rx FIFO overrun error interrupt enabled Bit 4 TXUNDERRIE: Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error. 0: Tx FIFO underrun error interrupt disabled 1: Tx FIFO underrun error interrupt enabled Bit 3 DTIMEOUTIE: Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout. 0: Data timeout interrupt disabled 1: Data timeout interrupt enabled Bit 2 CTIMEOUTIE: Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout. 0: Command timeout interrupt disabled 1: Command timeout interrupt enabled Bit 1 DCRCFAILIE: Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure. 0: Data CRC fail interrupt disabled 1: Data CRC fail interrupt enabled Bit 0 CCRCFAILIE: Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure. 0: Command CRC fail interrupt disabled 1: Command CRC fail interrupt enabled 41.8.14 SDMMC FIFO counter register (SDMMC_FIFOCNT) Address offset: 0x48 Reset value: 0x0000 0000 The SDMMC_FIFOCNT register contains the remaining number of words to be written to or read from the FIFO. The FIFO counter loads the value from the data length register (see SDMMC_DLEN) when the data transfer enable bit, DTEN, is set in the data control register (SDMMC_DCTRL register) and the DPSM is at the Idle state. If the data length is not wordaligned (multiple of 4), the remaining 1 to 3 bytes are regarded as a word. 1438/1680 DocID024597 Rev 1 RM0351 SD/SDIO/MMC card host interface (SDMMC) 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 23 22 21 20 r r r r 7 6 5 r r 19 18 17 16 r r r r 4 3 2 1 0 r r r r r FIFOCOUNT[23:16] 8 FIFOCOUNT[15:0] r r r r r r r r r Bits 31:24 Reserved, must be kept at reset value. Bits 23:0 FIFOCOUNT: Remaining number of words to be written to or read from the FIFO. 41.8.15 SDMMC data FIFO register (SDMMC_FIFO) Address offset: 0x80 Reset value: 0x0000 0000 The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIF0Data[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw FIF0Data[15:0] rw rw bits 31:0 FIFOData: Receive and transmit FIFO data The FIFO data occupies 32 entries of 32-bit words, from address: SDMMC base + 0x080 to SDMMC base + 0xFC. 41.8.16 SDMMC register map The following table summarizes the SDMMC registers. CLKEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKDIV PWRSAV 0 WIDBUS BYPASS Reset value 0 CMDARG SDMMC_ARG 0x08 0 NEGEDGE Reset value 0 HWFC_EN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SDMMC_ CLKCR Res. 0x04 Res. Reset value PWRCTRL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SDMMC_ POWER Res. 0x00 Res. Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 248. SDMMC register map 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID024597 Rev 1 0 0 1439/1680 1441 0x3C SDMMC_ MASK 1440/1680 RXFIFOFIE TXFIFOFIE RXFIFOHFIE TXFIFOHEIE RXACTIE TXACTIE CMDACTIE DBCKENDIE 0 0 0 0 Res. DocID024597 Rev 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTIMEOUTC CTIMEOUTC DCRCFAILC CCRCFAILC 0 0 0 0 0 0 0 0 0 DTIMEOUTIE CTIMEOUTIE DCRCFAILIE CCRCFAILIE 0 CCRCFAIL 0 DCRCFAIL 0 CTIMEOUT 0 DTIMEOUT 0 RXOVERR 0 TXUNDERR 0 0 0 DTEN 0 DTDIR 0 DMAEN 0 DTMODE Reset value RXOVERRC 0 TXUNDERRC 0 RXOVERRIE 0 0 TXUNDERRIE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBLOCKSIZE 0 0 CMDREND 0 0 0 CMDRENDC SDMMC_ DTIMER 0 0 CMDRENDIE 0 0 0 0 RWSTART 0 0 0 0 0 DATAEND SDMMC_ RESP4 0 0 CMDSENT 0 Res. 0 0 0 0 0 DATAENDC 0 Res. SDMMC_ RESP3 0 CMDSENTC 0 Res. 0 0 0 0 0 DATAENDIE 0 Res. 0 0 0 0 CMDSENTIE 0 Res. 0 0 0 RWMOD 0 Res. 0 0 RWSTOP 0 Res. SDMMC_ RESP2 SDIOEN 0 Res. SDMMC_ RESP1 Res. DBCKEND 0 DBCKENDC 0 CMDACT 0 Res. 0 TXACT 0 Res. 0 RXACT 0 Res. 0 TXFIFOHE 0 Res. 0 RXFIFOHF 0 Res. 0 TXFIFOF 0 Res. 0 RXFIFOF 0 Res. 0 TXFIFOE 0 Res. 0 RXFIFOE 0 Res. 0 Res. 0 CPSMEN WAITPEND WAITINT 0 0 0 0 0 Res. Res. Res. Res. Res. CMDINDEX WAITRESP SDIOSuspend Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. TXFIFOEIE Reset value RXFIFOEIE 0 TXDAVL 0 Res. Reset value TXDAVLIE 0 Res. 0 RXDAVL Res. 0 Res. 0 Res. Res. 0 SDIOIT Res. 0 0 RXDAVLIE Reset value 0 0 SDIOITC Reset value Res. 0 Res. 0 0 Res. 0 0 Res. 0 Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 0 0 0 SDIOITIE Reset value 0 0 0 Res. SDMMC_ICR 0 0 0 Res. 0x38 0 0 Res. SDMMC_STA 0 Res. 0x34 0 0 Res. 0x30 SDMMC_ DCOUNT Res. SDMMC_ DCTRL 0 Res. 0x2C 0 Res. 0x24 0 0 Res. Reset value 0 Res. 0x20 0 0 0 Res. Reset value 0 Res. 0 SDMMC_ DLEN Res. 0x28 Reset value Res. 0x1C 0 Res. Reset value Res. 0x18 0 Res. Reset value Res. 0x14 Res. SDMMC_ RESPCMD Res. SDMMC_CMD Res. 0x0C Res. 0x10 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. SD/SDIO/MMC card host interface (SDMMC) RM0351 Table 248. SDMMC register map (continued) 0 Reset value 0 0 0 0 0 RESPCMD 0 0 0 0 0 0 CARDSTATUS1 CARDSTATUS2 CARDSTATUS3 CARDSTATUS4 DATATIME DATALENGTH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATACOUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0351 SD/SDIO/MMC card host interface (SDMMC) Res. Res. Res. Res. Res. SDMMC_ FIFOCNT Res. 0x48 Res. Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 248. SDMMC register map (continued) FIFOCOUNT 0 Reset value 0 0 0 0 0 0 0x80 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIF0Data SDMMC_FIFO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. DocID024597 Rev 1 1441/1680 1441 Controller area network (bxCAN) RM0351 42 Controller area network (bxCAN) 42.1 Introduction The Basic Extended CAN peripheral, named bxCAN, interfaces the CAN network. It supports the CAN protocols version 2.0A and B. It has been designed to manage a high number of incoming messages efficiently with a minimum CPU load. It also meets the priority requirements for transmit messages. For safety-critical applications, the CAN controller provides all hardware functions for supporting the CAN Time Triggered Communication option. 42.2 bxCAN main features • Supports CAN protocol version 2.0 A, B Active • Bit rates up to 1 Mbit/s • Supports the Time Triggered Communication option Transmission • Three transmit mailboxes • Configurable transmit priority • Time Stamp on SOF transmission Reception • Two receive FIFOs with three stages • Scalable filter banks: – 14 filter banks • Identifier list feature • Configurable FIFO overrun • Time Stamp on SOF reception Time-triggered communication option • Disable automatic retransmission mode • 16-bit free running timer • Time Stamp sent in last two data bytes Management 1442/1680 • Maskable interrupts • Software-efficient mailbox mapping at a unique address space DocID024597 Rev 1 RM0351 42.3 Controller area network (bxCAN) bxCAN general description In today’s CAN applications, the number of nodes in a network is increasing and often several networks are linked together via gateways. Typically the number of messages in the system (and thus to be handled by each node) has significantly increased. In addition to the application messages, Network Management and Diagnostic messages have been introduced. • An enhanced filtering mechanism is required to handle each type of message. Furthermore, application tasks require more CPU time, therefore real-time constraints caused by message reception have to be reduced. • A receive FIFO scheme allows the CPU to be dedicated to application tasks for a long time period without losing messages. The standard HLP (Higher Layer Protocol) based on standard CAN drivers requires an efficient interface to the CAN controller. 0&8 $SSOLFDWLRQ &$1 &RQWUROOHU &$1 &$1 5; 7; &$1 7UDQVFHLYHU &$1 &$1 +LJK /RZ &$1QRGHQ &$1QRGH &$1QRGH Figure 473. CAN network topology &$1%XV 069 42.3.1 CAN 2.0B active core The bxCAN module handles the transmission and the reception of CAN messages fully autonomously. Standard identifiers (11-bit) and extended identifiers (29-bit) are fully supported by hardware. 42.3.2 Control, status and configuration registers The application uses these registers to: 42.3.3 • Configure CAN parameters, e.g. baud rate • Request transmissions • Handle receptions • Manage interrupts • Get diagnostic information Tx mailboxes Three transmit mailboxes are provided to the software for setting up messages. The transmission Scheduler decides which mailbox has to be transmitted first. DocID024597 Rev 1 1443/1680 1485 Controller area network (bxCAN) 42.3.4 RM0351 Acceptance filters The bxCAN provides 14 scalable/configurable identifier filter banks for selecting the incoming messages the software needs and discarding the others. Receive FIFO Two receive FIFOs are used by hardware to store the incoming messages. Three complete messages can be stored in each FIFO. The FIFOs are managed completely by hardware. 42.4 bxCAN operating modes bxCAN has three main operating modes: initialization, normal and Sleep. After a hardware reset, bxCAN is in Sleep mode to reduce power consumption and an internal pullup is active on CANTX. The software requests bxCAN to enter initialization or Sleep mode by setting the INRQ or SLEEP bits in the CAN_MCR register. Once the mode has been entered, bxCAN confirms it by setting the INAK or SLAK bits in the CAN_MSR register and the internal pull-up is disabled. When neither INAK nor SLAK are set, bxCAN is in normal mode. Before entering normal mode bxCAN always has to synchronize on the CAN bus. To synchronize, bxCAN waits until the CAN bus is idle, this means 11 consecutive recessive bits have been monitored on CANRX. 42.4.1 Initialization mode The software initialization can be done while the hardware is in Initialization mode. To enter this mode the software sets the INRQ bit in the CAN_MCR register and waits until the hardware has confirmed the request by setting the INAK bit in the CAN_MSR register. To leave Initialization mode, the software clears the INQR bit. bxCAN has left Initialization mode once the INAK bit has been cleared by hardware. While in Initialization Mode, all message transfers to and from the CAN bus are stopped and the status of the CAN bus output CANTX is recessive (high). Entering Initialization Mode does not change any of the configuration registers. To initialize the CAN Controller, software has to set up the Bit Timing (CAN_BTR) and CAN options (CAN_MCR) registers. To initialize the registers associated with the CAN filter banks (mode, scale, FIFO assignment, activation and filter values), software has to set the FINIT bit (CAN_FMR). Filter initialization also can be done outside the initialization mode. Note: When FINIT=1, CAN reception is deactivated. The filter values also can be modified by deactivating the associated filter activation bits (in the CAN_FA1R register). If a filter bank is not used, it is recommended to leave it non active (leave the corresponding FACT bit cleared). 42.4.2 Normal mode Once the initialization is complete, the software must request the hardware to enter Normal mode to be able to synchronize on the CAN bus and start reception and transmission. 1444/1680 DocID024597 Rev 1 RM0351 Controller area network (bxCAN) The request to enter Normal mode is issued by clearing the INRQ bit in the CAN_MCR register. The bxCAN enters Normal mode and is ready to take part in bus activities when it has synchronized with the data transfer on the CAN bus. This is done by waiting for the occurrence of a sequence of 11 consecutive recessive bits (Bus Idle state). The switch to Normal mode is confirmed by the hardware by clearing the INAK bit in the CAN_MSR register. The initialization of the filter values is independent from Initialization Mode but must be done while the filter is not active (corresponding FACTx bit cleared). The filter scale and mode configuration must be configured before entering Normal Mode. 42.4.3 Sleep mode (low-power) To reduce power consumption, bxCAN has a low-power mode called Sleep mode. This mode is entered on software request by setting the SLEEP bit in the CAN_MCR register. In this mode, the bxCAN clock is stopped, however software can still access the bxCAN mailboxes. If software requests entry to initialization mode by setting the INRQ bit while bxCAN is in Sleep mode, it must also clear the SLEEP bit. bxCAN can be woken up (exit Sleep mode) either by software clearing the SLEEP bit or on detection of CAN bus activity. On CAN bus activity detection, hardware automatically performs the wakeup sequence by clearing the SLEEP bit if the AWUM bit in the CAN_MCR register is set. If the AWUM bit is cleared, software has to clear the SLEEP bit when a wakeup interrupt occurs, in order to exit from Sleep mode. Note: If the wakeup interrupt is enabled (WKUIE bit set in CAN_IER register) a wakeup interrupt will be generated on detection of CAN bus activity, even if the bxCAN automatically performs the wakeup sequence. After the SLEEP bit has been cleared, Sleep mode is exited once bxCAN has synchronized with the CAN bus, refer to Figure 474: bxCAN operating modes. The Sleep mode is exited once the SLAK bit has been cleared by hardware. DocID024597 Rev 1 1445/1680 1485 Controller area network (bxCAN) RM0351 Figure 474. bxCAN operating modes 5HVHW 6OHHS 6/$. ,1$. 6/ 4 (( 5 ,1 1 6< /( 6 1RUPDO (( . (3 3 ,1 6/ & 5 3 ,1 $& (3 & 4 $ ( 6/ 4 $ 5 . & ,154$&. 6/$. ,1$. ,1546<1&6/((3 . ,QLWLDOL]DWLRQ 6/$. ,1$. DL 1. ACK = The wait state during which hardware confirms a request by setting the INAK or SLAK bits in the CAN_MSR register 2. SYNC = The state during which bxCAN waits until the CAN bus is idle, meaning 11 consecutive recessive bits have been monitored on CANRX 42.5 Test mode Test mode can be selected by the SILM and LBKM bits in the CAN_BTR register. These bits must be configured while bxCAN is in Initialization mode. Once test mode has been selected, the INRQ bit in the CAN_MCR register must be reset to enter Normal mode. 42.5.1 Silent mode The bxCAN can be put in Silent mode by setting the SILM bit in the CAN_BTR register. In Silent mode, the bxCAN is able to receive valid data frames and valid remote frames, but it sends only recessive bits on the CAN bus and it cannot start a transmission. If the bxCAN has to send a dominant bit (ACK bit, overload flag, active error flag), the bit is rerouted internally so that the CAN Core monitors this dominant bit, although the CAN bus may remain in recessive state. Silent mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits (Acknowledge Bits, Error Frames). 1446/1680 DocID024597 Rev 1 RM0351 Controller area network (bxCAN) Figure 475. bxCAN in silent mode E[&$1 7; 5; &$17; &$15; 069 42.5.2 Loop back mode The bxCAN can be set in Loop Back Mode by setting the LBKM bit in the CAN_BTR register. In Loop Back Mode, the bxCAN treats its own transmitted messages as received messages and stores them (if they pass acceptance filtering) in a Receive mailbox. Figure 476. bxCAN in loop back mode BX#!. 48 28 #!.48 #!.28 -36 This mode is provided for self-test functions. To be independent of external events, the CAN Core ignores acknowledge errors (no dominant bit sampled in the acknowledge slot of a data / remote frame) in Loop Back Mode. In this mode, the bxCAN performs an internal feedback from its Tx output to its Rx input. The actual value of the CANRX input pin is disregarded by the bxCAN. The transmitted messages can be monitored on the CANTX pin. 42.5.3 Loop back combined with silent mode It is also possible to combine Loop Back mode and Silent mode by setting the LBKM and SILM bits in the CAN_BTR register. This mode can be used for a “Hot Selftest”, meaning the bxCAN can be tested like in Loop Back mode but without affecting a running CAN system connected to the CANTX and CANRX pins. In this mode, the CANRX pin is disconnected from the bxCAN and the CANTX pin is held recessive. DocID024597 Rev 1 1447/1680 1485 Controller area network (bxCAN) RM0351 Figure 477. bxCAN in combined mode E[&$1 7; 5; &$17; &$15; 069 42.6 Behavior in Debug mode When the microcontroller enters the debug mode (Cortex®-M4 core halted), the bxCAN continues to work normally or stops, depending on: • the DBF bit in CAN_MCR. For more details, refer to Section 42.9.2: CAN control and status registers. 42.7 bxCAN functional description 42.7.1 Transmission handling In order to transmit a message, the application must select one empty transmit mailbox, set up the identifier, the data length code (DLC) and the data before requesting the transmission by setting the corresponding TXRQ bit in the CAN_TIxR register. Once the mailbox has left empty state, the software no longer has write access to the mailbox registers. Immediately after the TXRQ bit has been set, the mailbox enters pending state and waits to become the highest priority mailbox, see Transmit Priority. As soon as the mailbox has the highest priority it will be scheduled for transmission. The transmission of the message of the scheduled mailbox will start (enter transmit state) when the CAN bus becomes idle. Once the mailbox has been successfully transmitted, it will become empty again. The hardware indicates a successful transmission by setting the RQCP and TXOK bits in the CAN_TSR register. If the transmission fails, the cause is indicated by the ALST bit in the CAN_TSR register in case of an Arbitration Lost, and/or the TERR bit, in case of transmission error detection. Transmit priority By identifier When more than one transmit mailbox is pending, the transmission order is given by the identifier of the message stored in the mailbox. The message with the lowest identifier value has the highest priority according to the arbitration of the CAN protocol. If the identifier values are equal, the lower mailbox number will be scheduled first. By transmit request order 1448/1680 DocID024597 Rev 1 RM0351 Controller area network (bxCAN) The transmit mailboxes can be configured as a transmit FIFO by setting the TXFP bit in the CAN_MCR register. In this mode the priority order is given by the transmit request order. This mode is very useful for segmented transmission. Abort A transmission request can be aborted by the user setting the ABRQ bit in the CAN_TSR register. In pending or scheduled state, the mailbox is aborted immediately. An abort request while the mailbox is in transmit state can have two results. If the mailbox is transmitted successfully the mailbox becomes empty with the TXOK bit set in the CAN_TSR register. If the transmission fails, the mailbox becomes scheduled, the transmission is aborted and becomes empty with TXOK cleared. In all cases the mailbox will become empty again at least at the end of the current transmission. Non automatic retransmission mode This mode has been implemented in order to fulfill the requirement of the Time Triggered Communication option of the CAN standard. To configure the hardware in this mode the NART bit in the CAN_MCR register must be set. In this mode, each transmission is started only once. If the first attempt fails, due to an arbitration loss or an error, the hardware will not automatically restart the message transmission. At the end of the first transmission attempt, the hardware considers the request as completed and sets the RQCP bit in the CAN_TSR register. The result of the transmission is indicated in the CAN_TSR register by the TXOK, ALST and TERR bits. Figure 478. Transmit mailbox states %-049 21#08 48/+8 4-% 4821 0%.$).' 21#0 48/+ 4-% !"21 -AILBOX HAS HIGHEST PRIORITY -AILBOX DOES NOT HAVE HIGHEST PRIORITY %-049 21#0 48/+ 4-% #!. "US )$,% 4RANSMIT FAILED .!24 %-049 21#0 48/+ 4-% 3#(%$5,%$ 21#0 48/+ 4-% !"21 42!.3-)4 21#0 48/+ 4-% 4RANSMIT FAILED .!24 4RANSMIT SUCCEEDED -36 DocID024597 Rev 1 1449/1680 1485 Controller area network (bxCAN) 42.7.2 RM0351 Time triggered communication mode In this mode, the internal counter of the CAN hardware is activated and used to generate the Time Stamp value stored in the CAN_RDTxR/CAN_TDTxR registers, respectively (for Rx and Tx mailboxes). The internal counter is incremented each CAN bit time (refer to Section 42.7.7: Bit timing). The internal counter is captured on the sample point of the Start Of Frame bit in both reception and transmission. 42.7.3 Reception handling For the reception of CAN messages, three mailboxes organized as a FIFO are provided. In order to save CPU load, simplify the software and guarantee data consistency, the FIFO is managed completely by hardware. The application accesses the messages stored in the FIFO through the FIFO output mailbox. Valid message A received message is considered as valid when it has been received correctly according to the CAN protocol (no error until the last but one bit of the EOF field) and It passed through the identifier filtering successfully, see Section 42.7.4: Identifier filtering. Figure 479. Receive FIFO states %-049 &-0X &/62 6ALID -ESSAGE 2ECEIVED 2ELEASE -AILBOX 0%.$).'? &0-X &/62 2ELEASE -AILBOX 2&/- 6ALID -ESSAGE 2ECEIVED 0%.$).'? &0-X &/62 2ELEASE -AILBOX 2&/- 6ALID -ESSAGE 2ECEIVED 0%.$).'? &0-X &/62 6ALID -ESSAGE 2ECEIVED 2ELEASE -AILBOX 2&/- /6%225. &0-X &/62 6ALID -ESSAGE 2ECEIVED -36 1450/1680 DocID024597 Rev 1 RM0351 Controller area network (bxCAN) FIFO management Starting from the empty state, the first valid message received is stored in the FIFO which becomes pending_1. The hardware signals the event setting the FMP[1:0] bits in the CAN_RFR register to the value 01b. The message is available in the FIFO output mailbox. The software reads out the mailbox content and releases it by setting the RFOM bit in the CAN_RFR register. The FIFO becomes empty again. If a new valid message has been received in the meantime, the FIFO stays in pending_1 state and the new message is available in the output mailbox. If the application does not release the mailbox, the next valid message will be stored in the FIFO which enters pending_2 state (FMP[1:0] = 10b). The storage process is repeated for the next valid message putting the FIFO into pending_3 state (FMP[1:0] = 11b). At this point, the software must release the output mailbox by setting the RFOM bit, so that a mailbox is free to store the next valid message. Otherwise the next valid message received will cause a loss of message. Refer also to Section 42.7.5: Message storage Overrun Once the FIFO is in pending_3 state (i.e. the three mailboxes are full) the next valid message reception will lead to an overrun and a message will be lost. The hardware signals the overrun condition by setting the FOVR bit in the CAN_RFR register. Which message is lost depends on the configuration of the FIFO: • If the FIFO lock function is disabled (RFLM bit in the CAN_MCR register cleared) the last message stored in the FIFO will be overwritten by the new incoming message. In this case the latest messages will be always available to the application. • If the FIFO lock function is enabled (RFLM bit in the CAN_MCR register set) the most recent message will be discarded and the software will have the three oldest messages in the FIFO available. Reception related interrupts Once a message has been stored in the FIFO, the FMP[1:0] bits are updated and an interrupt request is generated if the FMPIE bit in the CAN_IER register is set. When the FIFO becomes full (i.e. a third message is stored) the FULL bit in the CAN_RFR register is set and an interrupt is generated if the FFIE bit in the CAN_IER register is set. On overrun condition, the FOVR bit is set and an interrupt is generated if the FOVIE bit in the CAN_IER register is set. 42.7.4 Identifier filtering In the CAN protocol the identifier of a message is not associated with the address of a node but related to the content of the message. Consequently a transmitter broadcasts its message to all receivers. On message reception a receiver node decides - depending on the identifier value - whether the software needs the message or not. If the message is needed, it is copied into the SRAM. If not, the message must be discarded without intervention by the software. To fulfill this requirement, the bxCAN Controller provides 28 configurable and scalable filter banks (27-0) to the application. In other devices the bxCAN Controller provides 14 DocID024597 Rev 1 1451/1680 1485 Controller area network (bxCAN) RM0351 configurable and scalable filter banks (13-0) to the application in order to receive only the messages the software needs. This hardware filtering saves CPU resources which would be otherwise needed to perform filtering by software. Each filter bank x consists of two 32-bit registers, CAN_FxR0 and CAN_FxR1. Scalable width To optimize and adapt the filters to the application needs, each filter bank can be scaled independently. Depending on the filter scale a filter bank provides: • One 32-bit filter for the STDID[10:0], EXTID[17:0], IDE and RTR bits. • Two 16-bit filters for the STDID[10:0], RTR, IDE and EXTID[17:15] bits. Refer to Figure 480. Furthermore, the filters can be configured in mask mode or in identifier list mode. Mask mode In mask mode the identifier registers are associated with mask registers specifying which bits of the identifier are handled as “must match” or as “don’t care”. Identifier list mode In identifier list mode, the mask registers are used as identifier registers. Thus instead of defining an identifier and a mask, two identifiers are specified, doubling the number of single identifiers. All bits of the incoming identifier must match the bits specified in the filter registers. Filter bank scale and mode configuration The filter banks are configured by means of the corresponding CAN_FMR register. To configure a filter bank it must be deactivated by clearing the FACT bit in the CAN_FAR register. The filter scale is configured by means of the corresponding FSCx bit in the CAN_FS1R register, refer to Figure 480. The identifier list or identifier mask mode for the corresponding Mask/Identifier registers is configured by means of the FBMx bits in the CAN_FMR register. To filter a group of identifiers, configure the Mask/Identifier registers in mask mode. To select single identifiers, configure the Mask/Identifier registers in identifier list mode. Filters not used by the application should be left deactivated. Each filter within a filter bank is numbered (called the Filter Number) from 0 to a maximum dependent on the mode and the scale of each of the filter banks. Concerning the filter configuration, refer to Figure 480. 1452/1680 DocID024597 Rev 1 RM0351 Controller area network (bxCAN) &"-X &"-X &3#X Figure 480. Filter bank scale configuration - register organization &ILTER .UM /NE "IT &ILTER )DENTIFIER -ASK )$ #!.?&X2;= #!.?&X2;= #!.?&X2;= #!.?&X2;= -ASK #!.?&X2;= #!.?&X2;= #!.?&X2;= #!.?&X2;= -APPING 34)$;= 34)$;= %8)$;= %8)$;= %8)$;= N )$% 242 4WO "IT &ILTERS )DENTIFIER ,IST )$ #!.?&X2;= #!.?&X2;= #!.?&X2;= #!.?&X2;= )$ #!.?&X2;= #!.?&X2;= #!.?&X2;= #!.?&X2;= -APPING 34)$;= 34)$;= %8)$;= %8)$;= %8)$;= N N )$% 242 &"-X 4WO "IT &ILTERS )DENTIFIER -ASK )$ -ASK )$ -APPING )$ )$ )$ )$ 34)$;= N #!.?&X2;= N #!.?&X2;= 34)$;= 242 )$% %8)$;= #!.?&X2;= #!.?&X2;= #!.?&X2;= #!.?&X2;= 34)$;= #!.?&X2;= #!.?&X2;= N N #!.?&X2;= N N #!.?&X2;= 34)$;= 242 )$% %8)$;= &ILTER "ANK -ODE -APPING &ILTER "ANK 3CALE #ONFIG "ITS #!.?&X2;= #!.?&X2;= #!.?&X2;= #!.?&X2;= &OUR "IT &ILTERS )DENTIFIER ,IST &"-X &3#X -ASK #!.?&X2;= #!.?&X2;= X FILTER BANK NUMBER )$)DENTIFIER 4HESE BITS ARE LOCATED IN THE #!.?&32 REGISTER 4HESE BITS ARE LOCATED IN THE #!.?&-2 REGISTER 069 Filter match index Once a message has been received in the FIFO it is available to the application. Typically, application data is copied into SRAM locations. To copy the data to the right location the application has to identify the data by means of the identifier. To avoid this, and to ease the access to the SRAM locations, the CAN controller provides a Filter Match Index. This index is stored in the mailbox together with the message according to the filter priority rules. Thus each received message has its associated filter match index. The Filter Match index can be used in two ways: • Compare the Filter Match index with a list of expected values. • Use the Filter Match Index as an index on an array to access the data destination location. For non masked filters, the software no longer has to compare the identifier. If the filter is masked the software reduces the comparison to the masked bits only. The index value of the filter number does not take into account the activation state of the filter banks. In addition, two independent numbering schemes are used, one for each FIFO. Refer to Figure 481 for an example. DocID024597 Rev 1 1453/1680 1485 Controller area network (bxCAN) RM0351 Figure 481. Example of filter numbering )LOWHU %DQN ),)2 )LOWHU 1XP )LOWHU %DQN ),)2 )LOWHU 1XP ,'/LVW ELW ,'0DVN ELW ,'0DVN ELW ,'/LVW ELW ,'/LVW ELW 'HDFWLYDWHG ,'/LVW ELW 'HDFWLYDWHG ,'/LVW ELW ,'0DVN ELW ,'0DVN ELW 'HDFWLYDWHG ,'/LVW ELW ,'/LVW ELW ,'/LVW ELW ,'0DVN ELW ,'0DVN ELW ,' ,GHQWLILHU 069 Filter priority rules Depending on the filter combination it may occur that an identifier passes successfully through several filters. In this case the filter match value stored in the receive mailbox is chosen according to the following priority rules: 1454/1680 • A 32-bit filter takes priority over a 16-bit filter. • For filters of equal scale, priority is given to the Identifier List mode over the Identifier Mask mode • For filters of equal scale and mode, priority is given by the filter number (the lower the number, the higher the priority). DocID024597 Rev 1 RM0351 Controller area network (bxCAN) Figure 482. Filtering mechanism - example ([DPSOHRIILOWHUEDQNVLQELW8QLGHQWLILHGPRGHDQG WKHUHPDLQLQJLQELW,GHQWLILHU0DVNPRGH 0HVVDJH5HFHLYHG ,GHQWLILHU &WUO 'DWD ,GHQWLILHU 0DVN ,GHQWLILHU/LVW )LOWHUEDQN 1XP ,GHQWLILHU ,GHQWLILHU ,GHQWLILHU ,GHQWLILHU ,GHQWLILHU 0DVN ,GHQWLILHU 0DVN 5HFHLYH),)2 ,GHQWLILHU0DWFK 0HVVDJH 6WRUHG )0, )LOWHUQXPEHUVWRUHGLQWKH )LOWHU0DWFK,QGH[ILHOG ZLWKLQWKH&$1B5'7[5 UHJLVWHU 1R0DWFK )RXQG 0HVVDJH'LVFDUGHG 069 The example above shows the filtering principle of the bxCAN. On reception of a message, the identifier is compared first with the filters configured in identifier list mode. If there is a match, the message is stored in the associated FIFO and the index of the matching filter is stored in the Filter Match Index. As shown in the example, the identifier matches with Identifier #2 thus the message content and FMI 2 is stored in the FIFO. If there is no match, the incoming identifier is then compared with the filters configured in mask mode. If the identifier does not match any of the identifiers configured in the filters, the message is discarded by hardware without disturbing the software. 42.7.5 Message storage The interface between the software and the hardware for the CAN messages is implemented by means of mailboxes. A mailbox contains all information related to a message; identifier, data, control, status and time stamp information. Transmit mailbox The software sets up the message to be transmitted in an empty transmit mailbox. The status of the transmission is indicated by hardware in the CAN_TSR register. DocID024597 Rev 1 1455/1680 1485 Controller area network (bxCAN) RM0351 Table 249. Transmit mailbox mapping Offset to transmit mailbox base address Register name 0 CAN_TIxR 4 CAN_TDTxR 8 CAN_TDLxR 12 CAN_TDHxR Receive mailbox When a message has been received, it is available to the software in the FIFO output mailbox. Once the software has handled the message (e.g. read it) the software must release the FIFO output mailbox by means of the RFOM bit in the CAN_RFR register to make the next incoming message available. The filter match index is stored in the MFMI field of the CAN_RDTxR register. The 16-bit time stamp value is stored in the TIME[15:0] field of CAN_RDTxR. Table 250. Receive mailbox mapping Offset to receive mailbox base address (bytes) Register name 0 CAN_RIxR 4 CAN_RDTxR 8 CAN_RDLxR 12 CAN_RDHxR Figure 483. CAN error state diagram :KHQ7(&RU5(&! (55253$66,9( (5525$&7,9( :KHQ7(&DQG5(& :KHQ UHFHVVLYHELWVRFFXU :KHQ7(&! %862)) DL 1456/1680 DocID024597 Rev 1 RM0351 42.7.6 Controller area network (bxCAN) Error management The error management as described in the CAN protocol is handled entirely by hardware using a Transmit Error Counter (TEC value, in CAN_ESR register) and a Receive Error Counter (REC value, in the CAN_ESR register), which get incremented or decremented according to the error condition. For detailed information about TEC and REC management, please refer to the CAN standard. Both of them may be read by software to determine the stability of the network. Furthermore, the CAN hardware provides detailed information on the current error status in CAN_ESR register. By means of the CAN_IER register (ERRIE bit, etc.), the software can configure the interrupt generation on error detection in a very flexible way. Bus-Off recovery The Bus-Off state is reached when TEC is greater than 255, this state is indicated by BOFF bit in CAN_ESR register. In Bus-Off state, the bxCAN is no longer able to transmit and receive messages. Depending on the ABOM bit in the CAN_MCR register bxCAN will recover from Bus-Off (become error active again) either automatically or on software request. But in both cases the bxCAN has to wait at least for the recovery sequence specified in the CAN standard (128 occurrences of 11 consecutive recessive bits monitored on CANRX). If ABOM is set, the bxCAN will start the recovering sequence automatically after it has entered Bus-Off state. If ABOM is cleared, the software must initiate the recovering sequence by requesting bxCAN to enter and to leave initialization mode. Note: In initialization mode, bxCAN does not monitor the CANRX signal, therefore it cannot complete the recovery sequence. To recover, bxCAN must be in normal mode. 42.7.7 Bit timing The bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the start-bit edge and resynchronizing on the following edges. Its operation may be explained simply by splitting nominal bit time into three segments as follows: • Synchronization segment (SYNC_SEG): a bit change is expected to occur within this time segment. It has a fixed length of one time quantum (1 x tq). • Bit segment 1 (BS1): defines the location of the sample point. It includes the PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration is programmable between 1 and 16 time quanta but may be automatically lengthened to compensate for positive phase drifts due to differences in the frequency of the various nodes of the network. • Bit segment 2 (BS2): defines the location of the transmit point. It represents the PHASE_SEG2 of the CAN standard. Its duration is programmable between 1 and 8 time quanta but may also be automatically shortened to compensate for negative phase drifts. The resynchronization Jump Width (SJW) defines an upper bound to the amount of lengthening or shortening of the bit segments. It is programmable between 1 and 4 time quanta. DocID024597 Rev 1 1457/1680 1485 Controller area network (bxCAN) RM0351 A valid edge is defined as the first transition in a bit time from dominant to recessive bus level provided the controller itself does not send a recessive bit. If a valid edge is detected in BS1 instead of SYNC_SEG, BS1 is extended by up to SJW so that the sample point is delayed. Conversely, if a valid edge is detected in BS2 instead of SYNC_SEG, BS2 is shortened by up to SJW so that the transmit point is moved earlier. As a safeguard against programming errors, the configuration of the Bit Timing Register (CAN_BTR) is only possible while the device is in Standby mode. Note: For a detailed description of the CAN bit timing and resynchronization mechanism, please refer to the ISO 11898 standard. Figure 484. Bit timing 120,1$/%,77,0( 6<1&B6(* [WT %DXG5DWH %,76(*0(17 %6 %,76(*0(17 %6 W%6 1RPLQDO%LW7LPH W%6 6$03/(32,17 75$160,732,17 1RPLQDO%LW7LPH [W TW%6W%6 ZLWK W%6 WT[ 76>@ W%6 WT[ 76>@ WT %53>@ [W3&/. ZKHUHWTUHIHUVWRWKHWLPHTXDQWXP W3&/. WLPHSHULRGRIWKH$3%FORFN %53>@76>@76>@DUHGHILQHGLQWKH&$1B%75UHJLVWHU 1458/1680 DocID024597 Rev 1 069 RM0351 Controller area network (bxCAN) Figure 485. CAN frames ,QWHU)UDPH6SDFH RU2YHUORDG)UDPH 'DWD)UDPH 6WDQGDUG,GHQWLILHU ,QWHU)UDPH6SDFH $UELWUDWLRQ)LHOG ,' '/& $&.)LHOG &5&)LHOG 1 $&. ,QWHU)UDPH6SDFH RU2YHUORDG)UDPH 'DWD)UDPH ([WHQGHG,GHQWLILHU 1 ,QWHU)UDPH6SDFH $UELWUDWLRQ)LHOG $UELWUDWLRQ)LHOG &WUO)LHOG 'DWD)LHOG 1 $UELWUDWLRQ)LHOG 5HPRWH)UDPH &5&)LHOG &WUO)LHOG '/& (QGRI)UDPHRU (UURU'HOLPLWHURU 2YHUORDG'HOLPLWHU $&. $&. (2) 'DWD)UDPHRU 5HPRWH)UDPH %XV,GOH ,QWHU)UDPH6SDFH RU(UURU)UDPH 2YHUORDG)UDPH 2YHUORDG 2YHUORDG (FKR )ODJ $&.)LHOG (UURU 'HOLPLWHU ,QWHU)UDPH6SDFH 6XVSHQG ,QWHUPLVVLRQ 7UDQVPLVVLRQ (2) ,QWHU)UDPH6SDFH RU2YHUORDG)UDPH (UURU)UDPH )ODJ(FKR ,QWHU)UDPH6SDFH RU2YHUORDG)UDPH &5& 575 ,'( U 62) ,' (UURU )ODJ &5& 575 U U 655 ,'( ,QWHU)UDPH6SDFH 'DWD)UDPHRU 5HPRWH)UDPH &5&)LHOG $&.)LHOG '/& 62) ,' $Q\)UDPH (2) &5& 575 ,'( U 62) 1 'DWD)LHOG &WUO)LHOG 2YHUORDG 'HOLPLWHU 1RWHV 1 62) 6WDUW2I)UDPH ,' ,GHQWLILHU 575 5HPRWH7UDQVPLVVLRQ5HTXHVW ,'( ,GHQWLILHU([WHQVLRQ%LW U 5HVHUYHG%LW '/& 'DWD/HQJWK&RGH &5& &\FOLF5HGXQGDQF\&RGH (UURUIODJGRPLQDQWELWVLIQRGHLVHUURU DFWLYHHOVHUHFHVVLYHELWV 6XVSHQGWUDQVPLVVLRQDSSOLHVWRHUURU SDVVLYHQRGHVRQO\ (2) (QGRI)UDPH $&. $FNQRZOHGJHELW &WUO &RQWURO DL DocID024597 Rev 1 1459/1680 1485 Controller area network (bxCAN) 42.8 RM0351 bxCAN interrupts Four interrupt vectors are dedicated to bxCAN. Each interrupt source can be independently enabled or disabled by means of the CAN Interrupt Enable Register (CAN_IER). Figure 486. Event flags and interrupt generation &$1B,(5 54&3 54&3 54&3 &$1B765 70(,( 75$160,7 ,17(55837 )03,( )03 )),( &$1B5)5 )8// ),)2 ,17(55837 )29,( )295 )03,( ),)2 ,17(55837 )03 )),( &$1B5)5 )8// )29,( )295 (55,( (:*,( (:*) (39,( &$1B(65 (39) %2),( %2)) (55,( 67$786&+$1*( (5525 ,17(55837 &$1B065 /(&,( /(& :.8,( :.8, &$1B065 6/.,( 6/$., 069 • • 1460/1680 The transmit interrupt can be generated by the following events: – Transmit mailbox 0 becomes empty, RQCP0 bit in the CAN_TSR register set. – Transmit mailbox 1 becomes empty, RQCP1 bit in the CAN_TSR register set. – Transmit mailbox 2 becomes empty, RQCP2 bit in the CAN_TSR register set. The FIFO 0 interrupt can be generated by the following events: – Reception of a new message, FMP0 bits in the CAN_RF0R register are not ‘00’. – FIFO0 full condition, FULL0 bit in the CAN_RF0R register set. – FIFO0 overrun condition, FOVR0 bit in the CAN_RF0R register set. DocID024597 Rev 1 RM0351 Controller area network (bxCAN) • The FIFO 1 interrupt can be generated by the following events: • 42.9 – Reception of a new message, FMP1 bits in the CAN_RF1R register are not ‘00’. – FIFO1 full condition, FULL1 bit in the CAN_RF1R register set. – FIFO1 overrun condition, FOVR1 bit in the CAN_RF1R register set. The error and status change interrupt can be generated by the following events: – Error condition, for more details on error conditions please refer to the CAN Error Status register (CAN_ESR). – Wakeup condition, SOF monitored on the CAN Rx signal. – Entry into Sleep mode. CAN registers The peripheral registers have to be accessed by words (32 bits). 42.9.1 Register access protection Erroneous access to certain configuration registers can cause the hardware to temporarily disturb the whole CAN network. Therefore the CAN_BTR register can be modified by software only while the CAN hardware is in initialization mode. Although the transmission of incorrect data will not cause problems at the CAN network level, it can severely disturb the application. A transmit mailbox can be only modified by software while it is in empty state, refer to Figure 478: Transmit mailbox states. The filter values can be modified either deactivating the associated filter banks or by setting the FINIT bit. Moreover, the modification of the filter configuration (scale, mode and FIFO assignment) in CAN_FMxR, CAN_FSxR and CAN_FFAR registers can only be done when the filter initialization mode is set (FINIT=1) in the CAN_FMR register. 42.9.2 CAN control and status registers Refer to Section 1.1 for a list of abbreviations used in register descriptions. CAN master control register (CAN_MCR) Address offset: 0x00 Reset value: 0x0001 0002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DBF rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET Res. Res. Res. Res. Res. Res. Res. TTCM ABOM AWUM NART RFLM TXFP SLEEP INRQ rw rw rw rw rw rw rw rw rs DocID024597 Rev 1 1461/1680 1485 Controller area network (bxCAN) RM0351 Bits 31:17 Reserved, must be kept at reset value. Bit 16 DBF: Debug freeze 0: CAN working during debug 1: CAN reception/transmission frozen during debug. Reception FIFOs can still be accessed/controlled normally. Bit 15 RESET: bxCAN software master reset 0: Normal operation. 1: Force a master reset of the bxCAN -> Sleep mode activated after reset (FMP bits and CAN_MCR register are initialized to the reset values). This bit is automatically reset to 0. Bits 14:8 Reserved, must be kept at reset value. Bit 7 TTCM: Time triggered communication mode 0: Time Triggered Communication mode disabled. 1: Time Triggered Communication mode enabled Note: For more information on Time Triggered Communication mode, please refer to Section 42.7.2: Time triggered communication mode. Bit 6 ABOM: Automatic bus-off management This bit controls the behavior of the CAN hardware on leaving the Bus-Off state. 0: The Bus-Off state is left on software request, once 128 occurrences of 11 recessive bits have been monitored and the software has first set and cleared the INRQ bit of the CAN_MCR register. 1: The Bus-Off state is left automatically by hardware once 128 occurrences of 11 recessive bits have been monitored. For detailed information on the Bus-Off state please refer to Section 42.7.6: Error management. Bit 5 AWUM: Automatic wakeup mode This bit controls the behavior of the CAN hardware on message reception during Sleep mode. 0: The Sleep mode is left on software request by clearing the SLEEP bit of the CAN_MCR register. 1: The Sleep mode is left automatically by hardware on CAN message detection. The SLEEP bit of the CAN_MCR register and the SLAK bit of the CAN_MSR register are cleared by hardware. Bit 4 NART: No automatic retransmission 0: The CAN hardware will automatically retransmit the message until it has been successfully transmitted according to the CAN standard. 1: A message will be transmitted only once, independently of the transmission result (successful, error or arbitration lost). Bit 3 RFLM: Receive FIFO locked mode 0: Receive FIFO not locked on overrun. Once a receive FIFO is full the next incoming message will overwrite the previous one. 1: Receive FIFO locked against overrun. Once a receive FIFO is full the next incoming message will be discarded. 1462/1680 DocID024597 Rev 1 RM0351 Controller area network (bxCAN) Bit 2 TXFP: Transmit FIFO priority This bit controls the transmission order when several mailboxes are pending at the same time. 0: Priority driven by the identifier of the message 1: Priority driven by the request order (chronologically) Bit 1 SLEEP: Sleep mode request This bit is set by software to request the CAN hardware to enter the Sleep mode. Sleep mode will be entered as soon as the current CAN activity (transmission or reception of a CAN frame) has been completed. This bit is cleared by software to exit Sleep mode. This bit is cleared by hardware when the AWUM bit is set and a SOF bit is detected on the CAN Rx signal. This bit is set after reset - CAN starts in Sleep mode. Bit 0 INRQ: Initialization request The software clears this bit to switch the hardware into normal mode. Once 11 consecutive recessive bits have been monitored on the Rx signal the CAN hardware is synchronized and ready for transmission and reception. Hardware signals this event by clearing the INAK bit in the CAN_MSR register. Software sets this bit to request the CAN hardware to enter initialization mode. Once software has set the INRQ bit, the CAN hardware waits until the current CAN activity (transmission or reception) is completed before entering the initialization mode. Hardware signals this event by setting the INAK bit in the CAN_MSR register. CAN master status register (CAN_MSR) Address offset: 0x04 Reset value: 0x0000 0C02 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. RX SAMP RXM TXM Res. Res. Res. SLAKI WKUI ERRI SLAK INAK r r r r rc_w1 rc_w1 rc_w1 r r Bits 31:12 Reserved, must be kept at reset value. Bit 11 RX: CAN Rx signal Monitors the actual value of the CAN_RX Pin. Bit 10 SAMP: Last sample point The value of RX on the last sample point (current received bit value). Bit 9 RXM: Receive mode The CAN hardware is currently receiver. Bit 8 TXM: Transmit mode The CAN hardware is currently transmitter. Bits 7:5 Reserved, must be kept at reset value. DocID024597 Rev 1 1463/1680 1485 Controller area network (bxCAN) RM0351 Bit 4 SLAKI: Sleep acknowledge interrupt When SLKIE=1, this bit is set by hardware to signal that the bxCAN has entered Sleep Mode. When set, this bit generates a status change interrupt if the SLKIE bit in the CAN_IER register is set. This bit is cleared by software or by hardware, when SLAK is cleared. Note: When SLKIE=0, no polling on SLAKI is possible. In this case the SLAK bit can be polled. Bit 3 WKUI: Wakeup interrupt This bit is set by hardware to signal that a SOF bit has been detected while the CAN hardware was in Sleep mode. Setting this bit generates a status change interrupt if the WKUIE bit in the CAN_IER register is set. This bit is cleared by software. Bit 2 ERRI: Error interrupt This bit is set by hardware when a bit of the CAN_ESR has been set on error detection and the corresponding interrupt in the CAN_IER is enabled. Setting this bit generates a status change interrupt if the ERRIE bit in the CAN_IER register is set. This bit is cleared by software. Bit 1 SLAK: Sleep acknowledge This bit is set by hardware and indicates to the software that the CAN hardware is now in Sleep mode. This bit acknowledges the Sleep mode request from the software (set SLEEP bit in CAN_MCR register). This bit is cleared by hardware when the CAN hardware has left Sleep mode (to be synchronized on the CAN bus). To be synchronized the hardware has to monitor a sequence of 11 consecutive recessive bits on the CAN RX signal. Note: The process of leaving Sleep mode is triggered when the SLEEP bit in the CAN_MCR register is cleared. Please refer to the AWUM bit of the CAN_MCR register description for detailed information for clearing SLEEP bit Bit 0 INAK: Initialization acknowledge This bit is set by hardware and indicates to the software that the CAN hardware is now in initialization mode. This bit acknowledges the initialization request from the software (set INRQ bit in CAN_MCR register). This bit is cleared by hardware when the CAN hardware has left the initialization mode (to be synchronized on the CAN bus). To be synchronized the hardware has to monitor a sequence of 11 consecutive recessive bits on the CAN RX signal. CAN transmit status register (CAN_TSR) Address offset: 0x08 Reset value: 0x1C00 0000 31 30 29 28 27 26 LOW2 LOW1 LOW0 TME2 TME1 TME0 r r r r r r 25 CODE[1:0] r 15 14 13 12 11 10 9 ABRQ1 Res. Res. Res. TERR1 ALST1 TXOK1 rc_w1 rc_w1 rc_w1 rs 1464/1680 24 23 22 21 20 19 18 17 16 ABRQ2 Res. Res. Res. TERR2 ALST2 TXOK2 RQCP2 rc_w1 rc_w1 rc_w1 rc_w1 r rs 8 7 RQCP1 ABRQ0 rc_w1 rs DocID024597 Rev 1 6 5 4 3 2 1 0 Res. Res. Res. TERR0 ALST0 TXOK0 RQCP0 rc_w1 rc_w1 rc_w1 rc_w1 RM0351 Controller area network (bxCAN) Bit 31 LOW2: Lowest priority flag for mailbox 2 This bit is set by hardware when more than one mailbox are pending for transmission and mailbox 2 has the lowest priority. Bit 30 LOW1: Lowest priority flag for mailbox 1 This bit is set by hardware when more than one mailbox are pending for transmission and mailbox 1 has the lowest priority. Bit 29 LOW0: Lowest priority flag for mailbox 0 This bit is set by hardware when more than one mailbox are pending for transmission and mailbox 0 has the lowest priority. Note: The LOW[2:0] bits are set to zero when only one mailbox is pending. Bit 28 TME2: Transmit mailbox 2 empty This bit is set by hardware when no transmit request is pending for mailbox 2. Bit 27 TME1: Transmit mailbox 1 empty This bit is set by hardware when no transmit request is pending for mailbox 1. Bit 26 TME0: Transmit mailbox 0 empty This bit is set by hardware when no transmit request is pending for mailbox 0. Bits 25:24 CODE[1:0]: Mailbox code In case at least one transmit mailbox is free, the code value is equal to the number of the next transmit mailbox free. In case all transmit mailboxes are pending, the code value is equal to the number of the transmit mailbox with the lowest priority. Bit 23 ABRQ2: Abort request for mailbox 2 Set by software to abort the transmission request for the corresponding mailbox. Cleared by hardware when the mailbox becomes empty. Setting this bit has no effect when the mailbox is not pending for transmission. Bits 22:20 Reserved, must be kept at reset value. Bit 19 TERR2: Transmission error of mailbox 2 This bit is set when the previous TX failed due to an error. Bit 18 ALST2: Arbitration lost for mailbox 2 This bit is set when the previous TX failed due to an arbitration lost. Bit 17 TXOK2: Transmission OK of mailbox 2 The hardware updates this bit after each transmission attempt. 0: The previous transmission failed 1: The previous transmission was successful This bit is set by hardware when the transmission request on mailbox 2 has been completed successfully. Please refer to Figure 478. Bit 16 RQCP2: Request completed mailbox2 Set by hardware when the last request (transmit or abort) has been performed. Cleared by software writing a “1” or by hardware on transmission request (TXRQ2 set in CAN_TMID2R register). Clearing this bit clears all the status bits (TXOK2, ALST2 and TERR2) for Mailbox 2. Bit 15 ABRQ1: Abort request for mailbox 1 Set by software to abort the transmission request for the corresponding mailbox. Cleared by hardware when the mailbox becomes empty. Setting this bit has no effect when the mailbox is not pending for transmission. Bits 14:12 Reserved, must be kept at reset value. DocID024597 Rev 1 1465/1680 1485 Controller area network (bxCAN) RM0351 Bit 11 TERR1: Transmission error of mailbox1 This bit is set when the previous TX failed due to an error. Bit 10 ALST1: Arbitration lost for mailbox1 This bit is set when the previous TX failed due to an arbitration lost. Bit 9 TXOK1: Transmission OK of mailbox1 The hardware updates this bit after each transmission attempt. 0: The previous transmission failed 1: The previous transmission was successful This bit is set by hardware when the transmission request on mailbox 1 has been completed successfully. Please refer to Figure 478 Bit 8 RQCP1: Request completed mailbox1 Set by hardware when the last request (transmit or abort) has been performed. Cleared by software writing a “1” or by hardware on transmission request (TXRQ1 set in CAN_TI1R register). Clearing this bit clears all the status bits (TXOK1, ALST1 and TERR1) for Mailbox 1. Bit 7 ABRQ0: Abort request for mailbox0 Set by software to abort the transmission request for the corresponding mailbox. Cleared by hardware when the mailbox becomes empty. Setting this bit has no effect when the mailbox is not pending for transmission. Bits 6:4 Reserved, must be kept at reset value. Bit 3 TERR0: Transmission error of mailbox0 This bit is set when the previous TX failed due to an error. Bit 2 ALST0: Arbitration lost for mailbox0 This bit is set when the previous TX failed due to an arbitration lost. Bit 1 TXOK0: Transmission OK of mailbox0 The hardware updates this bit after each transmission attempt. 0: The previous transmission failed 1: The previous transmission was successful This bit is set by hardware when the transmission request on mailbox 1 has been completed successfully. Please refer to Figure 478 Bit 0 RQCP0: Request completed mailbox0 Set by hardware when the last request (transmit or abort) has been performed. Cleared by software writing a “1” or by hardware on transmission request (TXRQ0 set in CAN_TI0R register). Clearing this bit clears all the status bits (TXOK0, ALST0 and TERR0) for Mailbox 0. CAN receive FIFO 0 register (CAN_RF0R) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FULL0 Res. RFOM0 FOVR0 rs 1466/1680 DocID024597 Rev 1 rc_w1 rc_w1 FMP0[1:0] r r RM0351 Controller area network (bxCAN) Bits 31:6 Reserved, must be kept at reset value. Bit 5 RFOM0: Release FIFO 0 output mailbox Set by software to release the output mailbox of the FIFO. The output mailbox can only be released when at least one message is pending in the FIFO. Setting this bit when the FIFO is empty has no effect. If at least two messages are pending in the FIFO, the software has to release the output mailbox to access the next message. Cleared by hardware when the output mailbox has been released. Bit 4 FOVR0: FIFO 0 overrun This bit is set by hardware when a new message has been received and passed the filter while the FIFO was full. This bit is cleared by software. Bit 3 FULL0: FIFO 0 full Set by hardware when three messages are stored in the FIFO. This bit is cleared by software. Bit 2 Reserved, must be kept at reset value. Bits 1:0 FMP0[1:0]: FIFO 0 message pending These bits indicate how many messages are pending in the receive FIFO. FMP is increased each time the hardware stores a new message in to the FIFO. FMP is decreased each time the software releases the output mailbox by setting the RFOM0 bit. CAN receive FIFO 1 register (CAN_RF1R) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FULL1 Res. RFOM1 FOVR1 rs rc_w1 rc_w1 FMP1[1:0] r r Bits 31:6 Reserved, must be kept at reset value. Bit 5 RFOM1: Release FIFO 1 output mailbox Set by software to release the output mailbox of the FIFO. The output mailbox can only be released when at least one message is pending in the FIFO. Setting this bit when the FIFO is empty has no effect. If at least two messages are pending in the FIFO, the software has to release the output mailbox to access the next message. Cleared by hardware when the output mailbox has been released. Bit 4 FOVR1: FIFO 1 overrun This bit is set by hardware when a new message has been received and passed the filter while the FIFO was full. This bit is cleared by software. DocID024597 Rev 1 1467/1680 1485 Controller area network (bxCAN) RM0351 Bit 3 FULL1: FIFO 1 full Set by hardware when three messages are stored in the FIFO. This bit is cleared by software. Bit 2 Reserved, must be kept at reset value. Bits 1:0 FMP1[1:0]: FIFO 1 message pending These bits indicate how many messages are pending in the receive FIFO1. FMP1 is increased each time the hardware stores a new message in to the FIFO1. FMP is decreased each time the software releases the output mailbox by setting the RFOM1 bit. CAN interrupt enable register (CAN_IER) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SLKIE WKUIE rw rw 15 ERRIE 14 Res. rw 13 Res. 12 11 10 9 8 Res. LEC IE BOF IE EPV IE EWG IE rw rw rw rw 7 6 5 4 3 2 1 0 Res. FOV IE1 FF IE1 FMP IE1 FOV IE0 FF IE0 FMP IE0 TME IE rw rw rw rw rw rw rw Bits 31:18 Reserved, must be kept at reset value. Bit 17 SLKIE: Sleep interrupt enable 0: No interrupt when SLAKI bit is set. 1: Interrupt generated when SLAKI bit is set. Bit 16 WKUIE: Wakeup interrupt enable 0: No interrupt when WKUI is set. 1: Interrupt generated when WKUI bit is set. Bit 15 ERRIE: Error interrupt enable 0: No interrupt will be generated when an error condition is pending in the CAN_ESR. 1: An interrupt will be generation when an error condition is pending in the CAN_ESR. Bits 14:12 Reserved, must be kept at reset value. Bit 11 LECIE: Last error code interrupt enable 0: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection. 1: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection. Bit 10 BOFIE: Bus-off interrupt enable 0: ERRI bit will not be set when BOFF is set. 1: ERRI bit will be set when BOFF is set. Bit 9 EPVIE: Error passive interrupt enable 0: ERRI bit will not be set when EPVF is set. 1: ERRI bit will be set when EPVF is set. 1468/1680 DocID024597 Rev 1 RM0351 Controller area network (bxCAN) Bit 8 EWGIE: Error warning interrupt enable 0: ERRI bit will not be set when EWGF is set. 1: ERRI bit will be set when EWGF is set. Bit 7 Reserved, must be kept at reset value. Bit 6 FOVIE1: FIFO overrun interrupt enable 0: No interrupt when FOVR is set. 1: Interrupt generation when FOVR is set. Bit 5 FFIE1: FIFO full interrupt enable 0: No interrupt when FULL bit is set. 1: Interrupt generated when FULL bit is set. Bit 4 FMPIE1: FIFO message pending interrupt enable 0: No interrupt generated when state of FMP[1:0] bits are not 00b. 1: Interrupt generated when state of FMP[1:0] bits are not 00b. Bit 3 FOVIE0: FIFO overrun interrupt enable 0: No interrupt when FOVR bit is set. 1: Interrupt generated when FOVR bit is set. Bit 2 FFIE0: FIFO full interrupt enable 0: No interrupt when FULL bit is set. 1: Interrupt generated when FULL bit is set. Bit 1 FMPIE0: FIFO message pending interrupt enable 0: No interrupt generated when state of FMP[1:0] bits are not 00b. 1: Interrupt generated when state of FMP[1:0] bits are not 00b. Bit 0 TMEIE: Transmit mailbox empty interrupt enable 0: No interrupt when RQCPx bit is set. 1: Interrupt generated when RQCPx bit is set. Note: Refer to Section 42.8: bxCAN interrupts. CAN error status register (CAN_ESR) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 REC[7:0] r r r r r 20 19 18 17 16 r r r TEC[7:0] r r r r r 6 15 14 13 12 11 10 9 8 7 Res. Res. Res. Res. Res. Res. Res. Res. Res. r r 5 4 LEC[2:0] rw DocID024597 Rev 1 rw rw r 3 2 1 0 Res. BOFF EPVF EWGF r r r 1469/1680 1485 Controller area network (bxCAN) RM0351 Bits 31:24 REC[7:0]: Receive error counter The implementing part of the fault confinement mechanism of the CAN protocol. In case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the CAN standard. After every successful reception the counter is decremented by 1 or reset to 120 if its value was higher than 128. When the counter value exceeds 127, the CAN controller enters the error passive state. Bits 23:16 TEC[7:0]: Least significant byte of the 9-bit transmit error counter The implementing part of the fault confinement mechanism of the CAN protocol. Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 LEC[2:0]: Last error code This field is set by hardware and holds a code which indicates the error condition of the last error detected on the CAN bus. If a message has been transferred (reception or transmission) without error, this field will be cleared to ‘0’. The LEC[2:0] bits can be set to value 0b111 by software. They are updated by hardware to indicate the current communication status. 000: No Error 001: Stuff Error 010: Form Error 011: Acknowledgment Error 100: Bit recessive Error 101: Bit dominant Error 110: CRC Error 111: Set by software Bit 3 Reserved, must be kept at reset value. Bit 2 BOFF: Bus-off flag This bit is set by hardware when it enters the bus-off state. The bus-off state is entered on TEC overflow, greater than 255, refer to Section 42.7.6 on page 1457. Bit 1 EPVF: Error passive flag This bit is set by hardware when the Error Passive limit has been reached (Receive Error Counter or Transmit Error Counter>127). Bit 0 EWGF: Error warning flag This bit is set by hardware when the warning limit has been reached (Receive Error Counter or Transmit Error Counter≥96). CAN bit timing register (CAN_BTR) Address offset: 0x1C Reset value: 0x0123 0000 This register can only be accessed by the software when the CAN hardware is in initialization mode. 31 30 29 28 27 26 SILM LBKM Res. Res. Res. Res. rw rw 15 14 13 12 11 10 Res. Res. Res. Res. Res. Res. 25 SJW[1:0] rw rw 9 8 23 22 Res. 7 21 20 19 18 TS2[2:0] 17 16 TS1[3:0] rw rw rw rw rw rw rw 6 5 4 3 2 1 0 rw rw rw rw BRP[9:0] rw 1470/1680 24 rw rw DocID024597 Rev 1 rw rw rw RM0351 Controller area network (bxCAN) Bit 31 SILM: Silent mode (debug) 0: Normal operation 1: Silent Mode Bit 30 LBKM: Loop back mode (debug) 0: Loop Back Mode disabled 1: Loop Back Mode enabled Bits 29:26 Reserved, must be kept at reset value. Bits 25:24 SJW[1:0]: Resynchronization jump width These bits define the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform the resynchronization. tRJW = tq x (SJW[1:0] + 1) Bit 23 Reserved, must be kept at reset value. Bits 22:20 TS2[2:0]: Time segment 2 These bits define the number of time quanta in Time Segment 2. tBS2 = tq x (TS2[2:0] + 1) Bits 19:16 TS1[3:0]: Time segment 1 These bits define the number of time quanta in Time Segment 1 tBS1 = tq x (TS1[3:0] + 1) For more information on bit timing, please refer to Section 42.7.7: Bit timing on page 1457. Bits 15:10 Reserved, must be kept at reset value. Bits 9:0 BRP[9:0]: Baud rate prescaler These bits define the length of a time quanta. tq = (BRP[9:0]+1) x tPCLK 42.9.3 CAN mailbox registers This chapter describes the registers of the transmit and receive mailboxes. Refer to Section 42.7.5: Message storage on page 1455 for detailed register mapping. Transmit and receive mailboxes have the same registers except: • The FMI field in the CAN_RDTxR register. • A receive mailbox is always write protected. • A transmit mailbox is write-enabled only while empty, corresponding TME bit in the CAN_TSR register set. There are 3 TX Mailboxes and 2 RX Mailboxes. Each RX Mailbox allows access to a 3 level depth FIFO, the access being offered only to the oldest received message in the FIFO. Each mailbox consist of 4 registers. DocID024597 Rev 1 1471/1680 1485 Controller area network (bxCAN) RM0351 Figure 487. Can mailbox registers &$1B5,5 &$1B5,5 &$1B7,5 &$1B7,5 &$1B7,5 &$1B5'75 &$1B5'75 &$1B7'75 &$1B7'75 &$1B7'75 &$1B5/5 &$1B5/5 &$1B7'/5 &$1B7'/5 &$1B7'/5 &$1B5+5 &$1B5+5 &$1B7'+5 &$1B7'+5 &$1B7'+5 ),)2 ),)2 7KUHH7;PDLOER[HV 069 CAN TX mailbox identifier register (CAN_TIxR) (x = 0..2) Address offsets: 0x180, 0x190, 0x1A0 Reset value: 0xXXXX XXXX (except bit 0, TXRQ = 0) All TX registers are write protected when the mailbox is pending transmission (TMEx reset). This register also implements the TX request control (bit 0) - reset value 0. 31 30 29 28 27 26 rw rw rw rw rw rw 15 14 13 12 11 10 25 24 23 22 21 20 19 rw rw rw rw rw rw rw 9 8 7 6 5 4 3 STID[10:0]/EXID[28:18] rw rw rw rw rw rw 17 16 rw rw rw 2 1 0 IDE RTR TXRQ rw rw rw EXID[17:13] EXID[12:0] rw 18 rw rw rw rw rw rw Bits 31:21 STID[10:0]/EXID[28:18]: Standard identifier or extended identifier The standard identifier or the MSBs of the extended identifier (depending on the IDE bit value). Bit 20:3 EXID[17:0]: Extended identifier The LSBs of the extended identifier. Bit 2 IDE: Identifier extension This bit defines the identifier type of message in the mailbox. 0: Standard identifier. 1: Extended identifier. Bit 1 RTR: Remote transmission request 0: Data frame 1: Remote frame Bit 0 TXRQ: Transmit mailbox request Set by software to request the transmission for the corresponding mailbox. Cleared by hardware when the mailbox becomes empty. 1472/1680 DocID024597 Rev 1 RM0351 Controller area network (bxCAN) CAN mailbox data length control and time stamp register (CAN_TDTxR) (x = 0..2) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x184, 0x194, 0x1A4 Reset value: 0xXXXX XXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TIME[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw DLC[3:0] rw rw Bits 31:16 TIME[15:0]: Message time stamp This field contains the 16-bit timer value captured at the SOF transmission. Bits 15:9 Reserved, must be kept at reset value. Bit 8 TGT: Transmit global time This bit is active only when the hardware is in the Time Trigger Communication mode, TTCM bit of the CAN_MCR register is set. 0: Time stamp TIME[15:0] is not sent. 1: Time stamp TIME[15:0] value is sent in the last two data bytes of the 8-byte message: TIME[7:0] in data byte 7 and TIME[15:8] in data byte 6, replacing the data written in CAN_TDHxR[31:16] register (DATA6[7:0] and DATA7[7:0]). DLC must be programmed as 8 in order these two bytes to be sent over the CAN bus. Bits 7:4 Reserved, must be kept at reset value. Bits 3:0 DLC[3:0]: Data length code This field defines the number of data bytes a data frame contains or a remote frame request. A message can contain from 0 to 8 data bytes, depending on the value in the DLC field. DocID024597 Rev 1 1473/1680 1485 Controller area network (bxCAN) RM0351 CAN mailbox data low register (CAN_TDLxR) (x = 0..2) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x188, 0x198, 0x1A8 Reset value: 0xXXXX XXXX 31 30 29 28 27 26 25 24 23 22 21 DATA3[7:0] rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 DATA1[7:0] rw rw rw rw 19 18 17 16 DATA2[7:0] rw rw 20 rw rw rw rw rw 4 3 2 1 0 rw rw rw 18 17 16 DATA0[7:0] rw rw rw rw rw rw rw rw Bits 31:24 DATA3[7:0]: Data byte 3 Data byte 3 of the message. Bits 23:16 DATA2[7:0]: Data byte 2 Data byte 2 of the message. Bits 15:8 DATA1[7:0]: Data byte 1 Data byte 1 of the message. Bits 7:0 DATA0[7:0]: Data byte 0 Data byte 0 of the message. A message can contain from 0 to 8 data bytes and starts with byte 0. CAN mailbox data high register (CAN_TDHxR) (x = 0..2) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x18C, 0x19C, 0x1AC Reset value: 0xXXXX XXXX 31 30 29 28 27 26 25 24 23 22 21 DATA7[7:0] 20 19 DATA6[7:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw DATA5[7:0] 1474/1680 rw DATA4[7:0] DocID024597 Rev 1 rw RM0351 Controller area network (bxCAN) Bits 31:24 DATA7[7:0]: Data byte 7 Data byte 7 of the message. Note: If TGT of this message and TTCM are active, DATA7 and DATA6 will be replaced by the TIME stamp value. Bits 23:16 DATA6[7:0]: Data byte 6 Data byte 6 of the message. Bits 15:8 DATA5[7:0]: Data byte 5 Data byte 5 of the message. Bits 7:0 DATA4[7:0]: Data byte 4 Data byte 4 of the message. CAN receive FIFO mailbox identifier register (CAN_RIxR) (x = 0..1) Address offsets: 0x1B0, 0x1C0 Reset value: 0xXXXX XXXX All RX registers are write protected. 31 30 29 28 27 26 25 24 23 22 21 20 19 STID[10:0]/EXID[28:18] r r r r r r 15 14 13 12 11 10 r r r r r r r r r r r r 9 8 7 6 5 4 3 r 17 16 r r EXID[17:13] EXID[12:0] r 18 r r r r r r r 2 1 0 IDE RTR Res r r Bits 31:21 STID[10:0]/EXID[28:18]: Standard identifier or extended identifier The standard identifier or the MSBs of the extended identifier (depending on the IDE bit value). Bits 20:3 EXID[17:0]: Extended identifier The LSBs of the extended identifier. Bit 2 IDE: Identifier extension This bit defines the identifier type of message in the mailbox. 0: Standard identifier. 1: Extended identifier. Bit 1 RTR: Remote transmission request 0: Data frame 1: Remote frame Bit 0 Reserved, must be kept at reset value. DocID024597 Rev 1 1475/1680 1485 Controller area network (bxCAN) RM0351 CAN receive FIFO mailbox data length control and time stamp register (CAN_RDTxR) (x = 0..1) Address offsets: 0x1B4, 0x1C4 Reset value: 0xXXXX XXXX All RX registers are write protected. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TIME[15:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. r r r r r r r r r FMI[7:0] r DLC[3:0] r r Bits 31:16 TIME[15:0]: Message time stamp This field contains the 16-bit timer value captured at the SOF detection. Bits 15:8 FMI[7:0]: Filter match index This register contains the index of the filter the message stored in the mailbox passed through. For more details on identifier filtering please refer to Section 42.7.4: Identifier filtering on page 1451 - Filter Match Index paragraph. Bits 7:4 Reserved, must be kept at reset value. Bits 3:0 DLC[3:0]: Data length code This field defines the number of data bytes a data frame contains (0 to 8). It is 0 in the case of a remote frame request. 1476/1680 DocID024597 Rev 1 RM0351 Controller area network (bxCAN) CAN receive FIFO mailbox data low register (CAN_RDLxR) (x = 0..1) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x1B8, 0x1C8 Reset value: 0xXXXX XXXX All RX registers are write protected. 31 30 29 28 r r r r 15 14 13 12 27 26 25 24 23 22 21 r r r r r r r r 11 10 9 8 7 6 5 4 DATA3[7:0] r r r r 19 18 17 16 r r r r 3 2 1 0 r r r 18 17 16 DATA2[7:0] DATA1[7:0] r 20 DATA0[7:0] r r r r r r r r Bits 31:24 DATA3[7:0]: Data Byte 3 Data byte 3 of the message. Bits 23:16 DATA2[7:0]: Data Byte 2 Data byte 2 of the message. Bits 15:8 DATA1[7:0]: Data Byte 1 Data byte 1 of the message. Bits 7:0 DATA0[7:0]: Data Byte 0 Data byte 0 of the message. A message can contain from 0 to 8 data bytes and starts with byte 0. CAN receive FIFO mailbox data high register (CAN_RDHxR) (x = 0..1) Address offsets: 0x1BC, 0x1CC Reset value: 0xXXXX XXXX All RX registers are write protected. 31 30 29 28 r r r r 15 14 13 12 27 26 25 24 23 22 21 r r r r r r r r r r r r 11 10 9 8 7 6 5 4 3 2 1 0 r r r DATA7[7:0] r r r r 19 DATA6[7:0] DATA5[7:0] r 20 DATA4[7:0] r r r r r r r r Bits 31:24 DATA7[7:0]: Data Byte 7 Data byte 3 of the message. DocID024597 Rev 1 1477/1680 1485 Controller area network (bxCAN) RM0351 Bits 23:16 DATA6[7:0]: Data Byte 6 Data byte 2 of the message. Bits 15:8 DATA5[7:0]: Data Byte 5 Data byte 1 of the message. Bits 7:0 DATA4[7:0]: Data Byte 4 Data byte 0 of the message. 42.9.4 CAN filter registers CAN filter master register (CAN_FMR) Address offset: 0x200 Reset value: 0x2A1C 0E01 All bits of this register are set and cleared by software. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FINIT rw Bits 31:1 Reserved, must be kept at reset value. Bit 0 FINIT: Filter initialization mode Initialization mode for filter banks 0: Active filters mode. 1: Initialization mode for the filters. 1478/1680 DocID024597 Rev 1 RM0351 Controller area network (bxCAN) CAN filter mode register (CAN_FM1R) Address offset: 0x204 Reset value: 0x0000 0000 This register can be written only when the filter initialization mode is set (FINIT=1) in the CAN_FMR register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 13 12 11 10 15 14 Res. Res. FBM13 FBM12 FBM11 FBM10 rw Note: rw rw rw 9 8 7 6 5 4 3 2 1 0 FBM9 FBM8 FBM7 FBM6 FBM5 FBM4 FBM3 FBM2 FBM1 FBM0 rw rw rw rw rw rw rw rw rw rw Please refer to Figure 480: Filter bank scale configuration - register organization on page 1453 Bits 31:14 Reserved, must be kept at reset value. Bits 13:0 FBMx: Filter mode Mode of the registers of Filter x. 0: Two 32-bit registers of filter bank x are in Identifier Mask mode. 1: Two 32-bit registers of filter bank x are in Identifier List mode. Note: Bits 27:14 are available in connectivity line devices only and are reserved otherwise. CAN filter scale register (CAN_FS1R) Address offset: 0x20C Reset value: 0x0000 0000 This register can be written only when the filter initialization mode is set (FINIT=1) in the CAN_FMR register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res FSC13 FSC12 FSC11 FSC10 FSC9 FSC8 FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:14 Reserved, must be kept at reset value. Bits 13:0 FSCx: Filter scale configuration These bits define the scale configuration of Filters 13-0. 0: Dual 16-bit scale configuration 1: Single 32-bit scale configuration Note: Bits 27:14 are available in connectivity line devices only and are reserved otherwise. Note: Please refer to Figure 480: Filter bank scale configuration - register organization on page 1453. DocID024597 Rev 1 1479/1680 1485 Controller area network (bxCAN) RM0351 CAN filter FIFO assignment register (CAN_FFA1R) Address offset: 0x214 Reset value: 0x0000 0000 This register can be written only when the filter initialization mode is set (FINIT=1) in the CAN_FMR register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res FFA13 FFA12 FFA11 FFA10 FFA9 FFA8 FFA7 FFA6 FFA5 FFA4 FFA3 FFA2 FFA1 FFA0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:14 Reserved, must be kept at reset value. Bits 13:0 FFAx: Filter FIFO assignment for filter x The message passing through this filter will be stored in the specified FIFO. 0: Filter assigned to FIFO 0 1: Filter assigned to FIFO 1 Note: Bits 27:14 are available in connectivity line devices only and are reserved otherwise. CAN filter activation register (CAN_FA1R) Address offset: 0x21C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res FACT1 3 FACT1 2 FACT1 1 FACT1 0 FACT9 FACT8 FACT7 FACT6 FACT5 FACT4 FACT3 FACT2 FACT1 FACT0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw Res Bits 31:14 Reserved, must be kept at reset value. Bits 13:0 FACTx: Filter active The software sets this bit to activate Filter x. To modify the Filter x registers (CAN_FxR[0:7]), the FACTx bit must be cleared or the FINIT bit of the CAN_FMR register must be set. 0: Filter x is not active 1: Filter x is active Note: Bits 27:14 are available in connectivity line devices only and are reserved otherwise. 1480/1680 DocID024597 Rev 1 RM0351 Controller area network (bxCAN) Filter bank i register x (CAN_FiRx) (i = 0..13, x = 1, 2) Address offsets: 0x240 to 0x2AC Reset value: 0xXXXX XXXX There are 14 filter banks, i= 0 to 13.Each filter bank i is composed of two 32-bit registers, CAN_FiR[2:1]. This register can only be modified when the FACTx bit of the CAN_FAxR register is cleared or when the FINIT bit of the CAN_FMR register is set. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FB31 FB30 FB29 FB28 FB27 FB26 FB25 FB24 FB23 FB22 FB21 FB20 FB19 FB18 FB17 FB16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FB15 FB14 FB13 FB12 FB11 FB10 FB9 FB8 FB7 FB6 FB5 FB4 FB3 FB2 FB1 FB0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw In all configurations: Bits 31:0 FB[31:0]: Filter bits Identifier Each bit of the register specifies the level of the corresponding bit of the expected identifier. 0: Dominant bit is expected 1: Recessive bit is expected Mask Each bit of the register specifies whether the bit of the associated identifier register must match with the corresponding bit of the expected identifier or not. 0: Don’t care, the bit is not used for the comparison 1: Must match, the bit of the incoming identifier must have the same level has specified in the corresponding identifier register of the filter. Note: Depending on the scale and mode configuration of the filter the function of each register can differ. For the filter mapping, functions description and mask registers association, refer to Section 42.7.4: Identifier filtering on page 1451. A Mask/Identifier register in mask mode has the same bit mapping as in identifier list mode. For the register mapping/addresses of the filter banks please refer to the Table 251 on page 1482. DocID024597 Rev 1 1481/1680 1485 0x180 1482/1680 0 0 0 CAN_BTR Reset value 0 0 CAN_TI0R Reset value x x x x x x 0 Res. x x x 1 0 0 0 1 1 Res. Res. x x x x x x STID[10:0]/EXID[28:18] x DocID024597 Rev 1 x x x x x 0 TMEIE 0 0 0 0 EWGF 0 EPVF 0 BOFF FMP1[1:0] Res. RQCP0 INRQ INAK 0 0 0 0 0 FMP0[1:0] TXFP SLEEP ERRI 1 ALST0 SLAK NART RFLM WKUI 0 SLAKI 1 Res. 0 0 TXOK0 FULL0 ABOM AWUM 0 Res. Res. Res. 0 Res. TXM Res. 0 0 Res. FOVR0 Res. RXM Res. TTCM SAMP Res. Res. Res. 0 Res. RX Res. Res. Res. DBF RESET Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 TERR0 RFOM0 0 Res. 0 FFIE0 FULL1 0 FMPIE0 FOVR1 0 FOVIE0 0 FMPIE1 0 Res. ABRQ0 Res. Res. RQCP1 Res. Res. TXOK1 Res. 0 0 0 0 x x x x x x x Res. 0 0 TXRQ 0 Res. Res. Reset value Res. 0 Res. Reset value RFOM1 ALST1 0 FFIE1 TERR1 Res. Res. 0 Res. Res. Res. 0 FOVIE1 ABRQ1 Res. 0 LEC[2:0] Res. Res. RQCP2 Res. 0 Res. 0 Res. EWGIE 0 Res. Res. TXOK2 Res. Res. ALST2 Res. Res. TERR2 Res. Res. Res. Res. Res. Res. ABRQ2 Res. 0 IDE 0 Res. EPVIE 0 Res. Res. Res. CODE[1:0] 0 Res. BOFIE 0 Res. Res. Res. Res. Res. Res. Res. 1 Res. LECIE Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 RTR 0 Res. x 0 Res. EXID[17:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. TME[2:0] 0 Res. Res. Reset value Res. TS1[3:0] Res. Res. Res. 0 Res. ERRIE Res. WKUIE 0 Res. Res. Res. LOW[2:0] 0 Res. 0 Res. Res. 0 Res. 0 0 Res. TS2[2:0] 0 0 Res. 0 Res. TEC[7:0] SLKIE Reset value 1 Res. 0 Res. Res. Reset value Res. 0 Res. REC[7:0] Res. CAN_RF0R Res. 0 Res. 0 Res. 0 Res. 1 Res. 1 Res. 1 Res. 0 Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. 0 Res. 0 Res. Res. CAN_ESR Res. CAN_IER SJW[1:0] 0 Res. 0x0200x17F 0 Res. 0x01C 0 Res. Reset value Res. 0x018 CAN_RF1R Res. 0x014 CAN_TSR Res. 0x010 CAN_MSR Res. 0x00C CAN_MCR Res. 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. 0x004 SILM 0x000 LBKM Offset Res. 42.9.5 Res. Controller area network (bxCAN) RM0351 bxCAN register map Refer to Section 2.2.2 on page 68 for the register boundary addresses. Table 251. bxCAN register map and reset values 0 0 0 0 0 0 0 BRP[9:0] x x 0 RM0351 Controller area network (bxCAN) x DATA2[7:0] x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x DATA7[7:0] x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Res. Res. Res. x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x DocID024597 Rev 1 x x x x x x x x x x 0 x x x x x x x x x x 0 x x x x x x x x x x x DATA0[7:0] x x x x x x x x DATA4[7:0] x x x x x x x x x x x x x x EXID[17:0] x x DLC[3:0] x DATA5[7:0] x x DATA4[7:0] DATA1[7:0] x x x DATA0[7:0] DATA5[7:0] x x DLC[3:0] x DATA1[7:0] STID[10:0]/EXID[28:18] x TGT x DATA6[7:0] x Res. x Res. x DATA7[7:0] x Res. x DATA2[7:0] x Res. x EXID[17:0] DATA3[7:0] x Res. x x TIME[15:0] x x x Res. x x Res. x x Res. x x TGT x x Res. x x Res. x x Res. x x x Res. x x x STID[10:0]/EXID[28:18] x x x DATA4[7:0] x DATA6[7:0] x x x Res. x DATA2[7:0] x x x EXID[17:0] DATA3[7:0] x Res. DATA5[7:0] TIME[15:0] x x Res. x x Res. x x Res. x x TGT x x Res. x x Res. x x Res. x x x DATA0[7:0] Res. x x DATA1[7:0] DATA6[7:0] x Res. Res. x TXRQ x x TXRQ x x Res. x x IDE x x RTR x x IDE x x RTR x IDE x DLC[3:0] RTR x Res. x CAN_RI0R Reset value x STID[10:0]/EXID[28:18] CAN_TDH2R Reset value 0x1B0 x CAN_TDL2R Reset value 0x1AC x CAN_TDT2R Reset value 0x1A8 x CAN_TI2R Reset value 0x1A4 x DATA7[7:0] CAN_TDH1R Reset value 0x1A0 x CAN_TDL1R Reset value 0x19C x CAN_TDT1R Reset value 0x198 x Res. 0x194 x CAN_TI1R Reset value x DATA3[7:0] CAN_TDH0R Reset value 0x190 x CAN_TDL0R Reset value 0x18C x Res. 0x188 TIME[15:0] Res. Reset value Res. CAN_TDT0R Res. 0x184 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 251. bxCAN register map and reset values (continued) 1483/1680 1485 Controller area network (bxCAN) RM0351 x x x x x x x x x x x x x x x x x x x x x DATA2[7:0] x x x x DATA7[7:0] x x x x x x x x DATA6[7:0] x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Res. Res. Res. x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CAN_FMR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FINIT DATA4[7:0] Res. x x Res. x x Res. x x Res. x x Res. x x Res. x x Res. x x DATA0[7:0] DATA5[7:0] x DLC[3:0] Res. x x x Res. x x x Res. x x x Res. x x x Res. x x x DATA4[7:0] Res. x x x x Res. x x x DATA0[7:0] DATA1[7:0] DATA6[7:0] x x x Res. x x x Res. x x x Res. x x Reset value 0x1D00x1FF x x Res. DATA7[7:0] x x FMI[7:0] DATA2[7:0] x x EXID[17:0] DATA3[7:0] x x DATA5[7:0] TIME[15:0] x x DATA1[7:0] STID[10:0]/EXID[28:18] CAN_RDH1R 0x200 x Res. x CAN_RDL1R Reset value 0x1CC x CAN_RDT1R Reset value 0x1C8 x IDE Reset value 0x1C4 x CAN_RI1R 0x1C0 x DATA3[7:0] CAN_RDH0R Reset value x RTR CAN_RDL0R Reset value 0x1BC x DLC[3:0] Res. 0x1B8 x FMI[7:0] Res. Reset value TIME[15:0] Res. CAN_RDT0R Res. 0x1B4 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 251. bxCAN register map and reset values (continued) x x x x x x x x Res. 1484/1680 Res. Res. Res. Res. Res. 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 FSC[13:0] 0 0 0 0 0 0 FFA[13:0] 0 DocID024597 Rev 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Reset value 0 Res. Res. Res. Res. CAN_FFA1R Res. 0x214 Res. 0x210 Res. Reset value 0 Res. Res. CAN_FS1R Res. 0x20C Res. 0x208 Res. Reset value FBM[13:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CAN_FM1R Res. 0x204 1 Res. Reset value 0 0 0 0 0 0 0 0 RM0351 Controller area network (bxCAN) 0x244 0x248 0x24C . . . . 0x318 0x31C Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 x x x x x x x x x x x x x x x x x x x x x x x x x FB[31:0] x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x FB[31:0] x x x x x x x x x x x x x x x x x FB[31:0] x x x x x x x x x x x x x x x x x . . . . CAN_F27R1 FB[31:0] x x x x x x x x x x x x x x x CAN_F27R2 Reset value 0 x x . . . . Reset value 0 x x CAN_F1R2 Reset value 0 x x CAN_F1R1 Reset value 0 FB[31:0] CAN_F0R2 Reset value 0 x CAN_F0R1 Reset value 0 Res. 0x240 0 Res. 0x2240x23F 0 Res. 0x220 0 FACT[13:0] Res. Reset value Res. Res. Res. CAN_FA1R Res. 0x21C Res. 0x218 Res. Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 251. bxCAN register map and reset values (continued) x x FB[31:0] x x x x x x x x x x x x x x x x DocID024597 Rev 1 x 1485/1680 1485 USB on-the-go full-speed (OTG_FS) RM0351 43 USB on-the-go full-speed (OTG_FS) 43.1 Introduction Portions Copyright (c) 2004, 2005 Synopsys, Inc. All rights reserved. Used with permission. This section presents the architecture and the programming model of the OTG_FS controller. The following acronyms are used throughout the section: FS Full-speed LS Low-speed MAC Media access controller OTG On-the-go PFC Packet FIFO controller PHY Physical layer USB Universal serial bus UTMI USB 2.0 Transceiver Macrocell interface (UTMI) References are made to the following documents: • USB On-The-Go Supplement, Revision 1.3 • USB On-The-Go Supplement, Revision 2.0 • Universal Serial Bus Revision 2.0 Specification • USB 2.0 Link Power Management Addendum Engineering Change Notice to the USB 2.0 specification, July 16, 2007 • Errata for USB 2.0 ECN: Link Power Management (LPM) - 7/2007 • Battery Charging Specification, Revision 1.2 The USB OTG is a dual-role device (DRD) controller that supports both device and host functions and is fully compliant with the On-The-Go Supplement to the USB 2.0 Specification. It can also be configured as a host-only or device-only controller, fully compliant with the USB 2.0 Specification. In host mode, the OTG_FS supports full-speed (FS, 12 Mbits/s) and low-speed (LS, 1.5 Mbits/s) transfers whereas in device mode, it only supports full-speed (FS, 12 Mbits/s) transfers. The USB OTG supports both HNP and SRP. The only external device required is a charge pump for VBUS in OTG mode. 43.2 USB_OTG main features The main features can be divided into three categories: general, host-mode and devicemode features. 43.2.1 General features The OTG_FS interface general features are the following: • 1486/1680 It is USB-IF certified to the Universal Serial Bus Specification Rev 2.0 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) • • • 43.2.2 It includes full support (PHY) for the optional On-The-Go (OTG) protocol detailed in the On-The-Go Supplement Rev 1.3 specification – Integrated support for A-B Device Identification (ID line) – Integrated support for host Negotiation Protocol (HNP) and Session Request Protocol (SRP) – It allows host to turn VBUS off to conserve battery power in OTG applications – It supports OTG monitoring of VBUS levels with internal comparators – It supports dynamic host-peripheral switch of role It is software-configurable to operate as: – SRP capable USB FS Peripheral (B-device) – SRP capable USB FS/LS host (A-device) – USB On-The-Go Full-Speed Dual Role device It supports FS SOF and LS Keep-alives with – SOF pulse PAD connectivity – SOF pulse internal connection to timer (TIMx) – Configurable framing period – Configurable end of frame interrupt • It includes power saving features such as system stop during USB Suspend, switch-off of clock domains internal to the digital core, PHY and DFIFO power management • It features a dedicated RAM of 1.25 Kbytes with advanced FIFO control: – Configurable partitioning of RAM space into different FIFOs for flexible and efficient use of RAM – Each FIFO can hold multiple packets – Dynamic memory allocation – Configurable FIFO sizes that are not powers of 2 to allow the use of contiguous memory locations • It guarantees max USB bandwidth for up to one frame (1 ms) without system intervention • It supports charging port detection as described in Battery Charging Specification Revision 1.2 • It supports Attach Detection Protocol (ADP) Host-mode features The OTG_FS interface main features and requirements in host-mode are the following: • External charge pump for VBUS voltage generation. • Up to 12 host channels (pipes): each channel is dynamically reconfigurable to allocate any type of USB transfer. • Built-in hardware scheduler holding: • – Up to 12 interrupt plus isochronous transfer requests in the periodic hardware queue – Up to 12 control plus bulk transfer requests in the non-periodic hardware queue Management of a shared Rx FIFO, a periodic Tx FIFO and a nonperiodic Tx FIFO for efficient usage of the USB data RAM. DocID024597 Rev 1 1487/1680 1635 USB on-the-go full-speed (OTG_FS) 43.2.3 RM0351 Peripheral-mode features The OTG_FS interface main features in peripheral-mode are the following: 43.3 • 1 bidirectional control endpoint0 • 5 IN endpoints (EPs) configurable to support Bulk, Interrupt or Isochronous transfers • 5 OUT endpoints configurable to support Bulk, Interrupt or Isochronous transfers • Management of a shared Rx FIFO and a Tx-OUT FIFO for efficient usage of the USB data RAM • Management of up to 6 dedicated Tx-IN FIFOs (one for each active IN EP) to put less load on the application • Support for the soft disconnect feature. USB_OTG Implementation Table 252. USB_OTG Implementation for STM32L4xx(1) USB features OTG_FS Device bidirectional endpoints (including EP0) 6 Host mode channels 12 Size of dedicated SRAM 1.2 KB USB 2.0 Link Power Management (LPM) support X OTG revision supported 1.3 & 2.0 Attach Detection Protocol (ADP) support X Battery Charging Detection (BCD) support X 1. “X” = supported 1488/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) 43.4 USB OTG functional description 43.4.1 USB OTG block diagram Figure 488. OTG full-speed block diagram !(" 0ERIPHERAL #ORTEX CORE 0OWER #LOCK #42, 53" SUSPEND 53" /4' &3 #ORE 3YSTEM CLOCK DOMAIN 54-)&3 /4' &3 0(9 $0 $)$ 53" CLOCK DOMAIN 2!- BUS 53" #LOCK AT -(Z 53" )NTERRUPT 6"53 5NIVERSAL SERIAL BUS +BYTES 53" DATA &)&/S -36 43.4.2 OTG core The USB OTG receives the 48 MHz ±0.25% clock from the reset and clock controller (RCC), via an external quartz. The USB clock is used for driving the 48 MHz domain at fullspeed (12 Mbit/s) and must be enabled prior to configuring the OTG core. The CPU reads and writes from/to the OTG core registers through the AHB peripheral bus. It is informed of USB events through the single USB OTG interrupt line described in Section 43.13: OTG_FS interrupts. The CPU submits data over the USB by writing 32-bit words to dedicated OTG locations (push registers). The data are then automatically stored into Tx-data FIFOs configured within the USB data RAM. There is one Tx FIFO push register for each in-endpoint (peripheral mode) or out-channel (host mode). The CPU receives the data from the USB by reading 32-bit words from dedicated OTG addresses (pop registers). The data are then automatically retrieved from a shared Rx FIFO configured within the 1.25 KB USB data RAM. There is one Rx FIFO pop register for each out-endpoint or in-channel. DocID024597 Rev 1 1489/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 The USB protocol layer is driven by the serial interface engine (SIE) and serialized over the USB by the transceiver module within the on-chip physical layer (PHY). 43.4.3 Full-speed OTG PHY The embedded full-speed OTG PHY is controlled by the OTG FS core and conveys USB control & data signals through the full-speed subset of the UTMI+ Bus (UTMIFS). It provides the physical support to USB connectivity. The full-speed OTG PHY includes the following components: Caution: 1490/1680 • FS/LS transceiver module used by both host and device. It directly drives transmission and reception on the single-ended USB lines. • integrated ID pull-up resistor used to sample the ID line for A/B device identification. • DP/DM integrated pull-up and pull-down resistors controlled by the OTG_FS core depending on the current role of the device. As a peripheral, it enables the DP pull-up resistor to signal full-speed peripheral connections as soon as VBUS is sensed to be at a valid level (B-session valid). In host mode, pull-down resistors are enabled on both DP/DM. Pull-up and pull-down resistors are dynamically switched when the device’s role is changed via the host negotiation protocol (HNP). • Pull-up/pull-down resistor ECN circuit. The DP pull-up consists of 2 resistors controlled separately from the OTG_FS as per the resistor Engineering Change Notice applied to USB Rev2.0. The dynamic trimming of the DP pull-up strength allows for better noise rejection and Tx/Rx signal quality. • VBUS sensing comparators with hysteresis used to detect VBUS Valid, A-B Session Valid and session-end voltage thresholds. They are used to drive the session request protocol (SRP), detect valid startup and end-of-session conditions, and constantly monitor the VBUS supply during USB operations. • VBUS pulsing method circuit used to charge/discharge VBUS through resistors during the SRP (weak drive). To guarantee a correct operation for the USB OTG FS peripheral, the AHB frequency should be higher than 14.2 MHz. DocID024597 Rev 1 RM0351 43.5 USB on-the-go full-speed (OTG_FS) OTG dual role device (DRD) Figure 489. OTG_FS A-B device connection 9'' 9WR9'' 9ROWDJH UHJXODWRU 9'' *3,2,54 (1 67036675 93ZU &XUUHQWOLPLWHGSRZHU 2YHUFXUUHQW GLVWULEXWLRQVZLWFK 9%86 '0 26&B,1 '3 ,' 26&B287 966 86%PLFUR$%FRQQHFWRU *3,2 06Y9 1. External voltage regulator only needed when building a VBUS powered device. 2. STMPS2141STR needed only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 43.5.1 ID line detection The host or peripheral (the default) role is assumed depending on the ID input pin. The ID line status is determined on plugging in the USB, depending on which side of the USB cable is connected to the micro-AB receptacle. 43.5.2 • If the B-side of the USB cable is connected with a floating ID wire, the integrated pullup resistor detects a high ID level and the default Peripheral role is confirmed. In this configuration the OTG_FS complies with the standard FSM described by section 6.8.2: On-The-Go B-device of the On-The-Go Specification Rev1.3 supplement to the USB2.0. • If the A-side of the USB cable is connected with a grounded ID, the OTG_FS issues an ID line status change interrupt (CIDSCHG bit in OTG_GINTSTS) for host software initialization, and automatically switches to the host role. In this configuration the OTG_FS complies with the standard FSM described by section 6.8.1: On-The-Go Adevice of the On-The-Go Specification Rev1.3 supplement to the USB2.0. HNP dual role device The HNP capable bit in the Global USB configuration register (HNPCAP bit in OTG_ GUSBCFG) enables the OTG_FS core to dynamically change its role from A-host to Aperipheral and vice-versa, or from B-Peripheral to B-host and vice-versa according to the host negotiation protocol (HNP). The current device status can be read by the combined values of the Connector ID Status bit in the Global OTG control and status register (CIDSTS bit in OTG_GOTGCTL) and the current mode of operation bit in the global interrupt and status register (CMOD bit in OTG_GINTSTS). DocID024597 Rev 1 1491/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 The HNP program model is described in detail in Section 43.16: OTG_FS programming model. 43.5.3 SRP dual role device The SRP capable bit in the global USB configuration register (SRPCAP bit in OTG_GUSBCFG) enables the OTG_FS core to switch off the generation of VBUS for the Adevice to save power. Note that the A-device is always in charge of driving VBUS regardless of the host or peripheral role of the OTG_FS. the SRP A/B-device program model is described in detail in Section 43.16: OTG_FS programming model. 43.6 USB peripheral This section gives the functional description of the OTG_FS in the USB peripheral mode. The OTG_FS works as an USB peripheral in the following circumstances: • OTG B-Peripheral – • OTG A-Peripheral – • 1492/1680 If the ID line is present, functional and connected to the B-side of the USB cable, and the HNP-capable bit in the Global USB Configuration register (HNPCAP bit in OTG_GUSBCFG) is cleared (see On-The-Go Rev1.3 par. 6.8.3). Peripheral only (see Figure 490: USB_FS peripheral-only connection) – Note: OTG A-device state after the HNP switches the OTG_FS to its peripheral role B-device – • OTG B-device default state if B-side of USB cable is plugged in The force device mode bit (FDMOD) in the Section 43.15.4: OTG USB configuration register (OTG_GUSBCFG) is set to 1, forcing the OTG_FS core to work as an USB peripheral-only (see On-The-Go Rev1.3 par. 6.8.3). In this case, the ID line is ignored even if present on the USB connector. To build a bus-powered device implementation in case of the B-device or peripheral-only configuration, an external regulator has to be added that generates the VDD chip-supply from VBUS. DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Figure 490. USB_FS peripheral-only connection 9'' 9WR9'' 9ROWDJH UHJXODWRU 9'' (1 *3,2 9%86 '0 26&B,1 '3 ,' 26&B287 966 86%PLFUR$%FRQQHFWRU *3,2,54 67036675 93ZU &XUUHQWOLPLWHGSRZHU 2YHUFXUUHQW GLVWULEXWLRQVZLWFK 06Y9 1. Use a regulator to build a bus-powered device. 43.6.1 SRP-capable peripheral The SRP capable bit in the Global USB configuration register (SRPCAP bit in OTG_GUSBCFG) enables the OTG_FS to support the session request protocol (SRP). In this way, it allows the remote A-device to save power by switching off VBUS while the USB session is suspended. The SRP peripheral mode program model is described in detail in the B-device session request protocol section. 43.6.2 Peripheral states Powered state The VBUS input detects the B-Session valid voltage by which the USB peripheral is allowed to enter the powered state (see USB2.0 par9.1). The OTG_FS then automatically connects the DP pull-up resistor to signal full-speed device connection to the host and generates the session request interrupt (SRQINT bit in OTG_GINTSTS) to notify the powered state. The VBUS input also ensures that valid VBUS levels are supplied by the host during USB operations. If a drop in VBUS below B-session valid happens to be detected (for instance because of a power disturbance or if the host port has been switched off), the OTG_FS automatically disconnects and the session end detected (SEDET bit in OTG_GOTGINT) interrupt is generated to notify that the OTG_FS has exited the powered state. In the powered state, the OTG_FS expects to receive some reset signaling from the host. No other USB operation is possible. When a reset signaling is received the reset detected interrupt (USBRST in OTG_GINTSTS) is generated. When the reset signaling is complete, the enumeration done interrupt (ENUMDNE bit in OTG_GINTSTS) is generated and the OTG_FS enters the Default state. DocID024597 Rev 1 1493/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Soft disconnect The powered state can be exited by software with the soft disconnect feature. The DP pullup resistor is removed by setting the soft disconnect bit in the device control register (SDIS bit in OTG_DCTL), causing a device disconnect detection interrupt on the host side even though the USB cable was not really removed from the host port. Default state In the Default state the OTG_FS expects to receive a SET_ADDRESS command from the host. No other USB operation is possible. When a valid SET_ADDRESS command is decoded on the USB, the application writes the corresponding number into the device address field in the device configuration register (DAD bit in OTG_DCFG). The OTG_FS then enters the address state and is ready to answer host transactions at the configured USB address. Suspended state The OTG_FS peripheral constantly monitors the USB activity. After counting 3 ms of USB idleness, the early suspend interrupt (ESUSP bit in OTG_GINTSTS) is issued, and confirmed 3 ms later, if appropriate, by the suspend interrupt (USBSUSP bit in OTG_GINTSTS). The device suspend bit is then automatically set in the device status register (SUSPSTS bit in OTG_DSTS) and the OTG_FS enters the suspended state. The suspended state may optionally be exited by the device itself. In this case the application sets the remote wakeup signaling bit in the device control register (RWUSIG bit in OTG_DCTL) and clears it after 1 to 15 ms. When a resume signaling is detected from the host, the resume interrupt (WKUPINT bit in OTG_GINTSTS) is generated and the device suspend bit is automatically cleared. 43.6.3 Peripheral endpoints The OTG_FS core instantiates the following USB endpoints: • • 1494/1680 Control endpoint 0: – Bidirectional and handles control messages only – Separate set of registers to handle in and out transactions – Proper control (OTG_DIEPCTL0/OTG_DOEPCTL0), transfer configuration (OTG_DIEPTSIZ0/OTG_DOEPTSIZ0), and status-interrupt (OTG_DIEPINT0/)OTG_DOEPINT0) registers. The available set of bits inside the control and transfer size registers slightly differs from that of other endpoints 5 IN endpoints – Each of them can be configured to support the isochronous, bulk or interrupt transfer type – Each of them has proper control (OTG_DIEPCTLx), transfer configuration (OTG_DIEPTSIZx), and status-interrupt (OTG_DIEPINTx) registers – The Device IN endpoints common interrupt mask register (OTG_DIEPMSK) is available to enable/disable a single kind of endpoint interrupt source on all of the IN endpoints (EP0 included) – Support for incomplete isochronous IN transfer interrupt (IISOIXFR bit in OTG_GINTSTS), asserted when there is at least one isochronous IN endpoint on DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) which the transfer is not completed in the current frame. This interrupt is asserted along with the end of periodic frame interrupt (OTG_GINTSTS/EOPF). • 5 OUT endpoints – Each of them can be configured to support the isochronous, bulk or interrupt transfer type – Each of them has a proper control (OTG_DOEPCTLx), transfer configuration (OTG_DOEPTSIZx) and status-interrupt (OTG_DOEPINTx) register – Device Out endpoints common interrupt mask register (OTG_DOEPMSK) is available to enable/disable a single kind of endpoint interrupt source on all of the OUT endpoints (EP0 included) – Support for incomplete isochronous OUT transfer interrupt (INCOMPISOOUT bit in OTG_GINTSTS), asserted when there is at least one isochronous OUT endpoint on which the transfer is not completed in the current frame. This interrupt is asserted along with the end of periodic frame interrupt (OTG_GINTSTS/EOPF). Endpoint control • The following endpoint controls are available to the application through the device endpoint-x IN/OUT control register (OTG_DIEPCTLx/OTG_DOEPCTLx): – Endpoint enable/disable – Endpoint activate in current configuration – Program USB transfer type (isochronous, bulk, interrupt) – Program supported packet size – Program Tx FIFO number associated with the IN endpoint – Program the expected or transmitted data0/data1 PID (bulk/interrupt only) – Program the even/odd frame during which the transaction is received or transmitted (isochronous only) – Optionally program the NAK bit to always negative-acknowledge the host regardless of the FIFO status – Optionally program the STALL bit to always stall host tokens to that endpoint – Optionally program the SNOOP mode for OUT endpoint not to check the CRC field of received data Endpoint transfer The device endpoint-x transfer size registers (OTG_DIEPTSIZx/OTG_DOEPTSIZx) allow the application to program the transfer size parameters and read the transfer status. Programming must be done before setting the endpoint enable bit in the endpoint control register. Once the endpoint is enabled, these fields are read-only as the OTG_FS core updates them with the current transfer status. The following transfer parameters can be programmed: • Transfer size in bytes • Number of packets that constitute the overall transfer size Endpoint status/interrupt The device endpoint-x interrupt registers (OTG_DIEPINTx/OTG_DOPEPINTx) indicate the status of an endpoint with respect to USB- and AHB-related events. The application must read these registers when the OUT endpoint interrupt bit or the IN endpoint interrupt bit in DocID024597 Rev 1 1495/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 the core interrupt register (OEPINT bit in OTG_GINTSTS or IEPINT bit in OTG_GINTSTS, respectively) is set. Before the application can read these registers, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers The peripheral core provides the following status checks and interrupt generation: 43.7 • Transfer completed interrupt, indicating that data transfer was completed on both the application (AHB) and USB sides • Setup stage has been done (control-out only) • Associated transmit FIFO is half or completely empty (in endpoints) • NAK acknowledge has been transmitted to the host (isochronous-in only) • IN token received when Tx FIFO was empty (bulk-in/interrupt-in only) • Out token received when endpoint was not yet enabled • Babble error condition has been detected • Endpoint disable by application is effective • Endpoint NAK by application is effective (isochronous-in only) • More than 3 back-to-back setup packets were received (control-out only) • Timeout condition detected (control-in only) • Isochronous out packet has been dropped, without generating an interrupt USB host This section gives the functional description of the OTG_FS in the USB host mode. The OTG_FS works as a USB host in the following circumstances: • OTG A-host – • OTG B-host • A-device – – • 1496/1680 OTG B-device after HNP switching to the host role If the ID line is present, functional and connected to the A-side of the USB cable, and the HNP-capable bit is cleared in the Global USB Configuration register (HNPCAP bit in OTG_GUSBCFG). Integrated pull-down resistors are automatically set on the DP/DM lines. Host only – Note: OTG A-device default state when the A-side of the USB cable is plugged in The force host mode bit in the 43.15.4 global USB configuration register (FHMOD bit in OTG_GUSBCFG) forces the OTG_FS core to work as a USB host-only. In this case, the ID line is ignored even if present on the USB connector. Integrated pull-down resistors are automatically set on the DP/DM lines. On-chip 5 V VBUS generation is not supported. For this reason, a charge pump or, if 5 V are available on the application board, a basic power switch must be added externally to drive the 5 V VBUS line. The external charge pump can be driven by any GPIO output. This is required for the OTG A-host, A-device and host-only configurations. DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Figure 491. USB_FS host-only connection 9'' *3,2,54 67036675 93ZU &XUUHQWOLPLWHG SRZHUGLVWULEXWLRQ 2YHUFXUUHQW VZLWFK 9%86 '0 26&B,1 '3 966 26&B287 86%6WG$FRQQHFWRU *3,2 (1 06Y9 1. STMPS2141STR needed only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 2. VDD range is between 2 V and 3.6 V. 43.7.1 SRP-capable host SRP support is available through the SRP capable bit in the global USB configuration register (SRPCAP bit in OTG_GUSBCFG). With the SRP feature enabled, the host can save power by switching off the VBUS power while the USB session is suspended. The SRP host mode program model is described in detail in the A-device session request protocol) section. 43.7.2 USB host states Host port power On-chip 5 V VBUS generation is not supported. For this reason, a charge pump or, if 5 V are available on the application board, a basic power switch, must be added externally to drive the 5 V VBUS line. The external charge pump can be driven by any GPIO output. When the application decides to power on VBUS using the chosen GPIO, it must also set the port power bit in the host port control and status register (PPWR bit in OTG_HPRT). VBUS valid When HNP or SRP is enabled the VBUS sensing pin should be connected to VBUS. The VBUS input ensures that valid VBUS levels are supplied by the charge pump during USB operations. Any unforeseen VBUS voltage drop below the VBUS valid threshold (4.25 V) leads to an OTG interrupt triggered by the session end detected bit (SEDET bit in OTG_GOTGINT). The application is then required to remove the VBUS power and clear the port power bit. When HNP and SRP are both disabled, the VBUS sensing pin does not need to be connected to VBUS and it can be used as GPIO. The charge pump overcurrent flag can also be used to prevent electrical damage. Connect the overcurrent flag output from the charge pump to any GPIO input and configure it to generate a port interrupt on the active level. The overcurrent ISR must promptly disable the VBUS generation and clear the port power bit. DocID024597 Rev 1 1497/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Host detection of a peripheral connection If SRP or HNP are enabled, even if USB peripherals or B-devices can be attached at any time, the OTG_FS will not detect any bus connection until VBUS is no longer sensed at a valid level (5 V). When VBUS is at a valid level and a remote B-device is attached, the OTG_FS core issues a host port interrupt triggered by the device connected bit in the host port control and status register (PCDET bit in OTG_HPRT). When HNP and SRP are both disabled, USB peripherals or B-device are detected as soon as they are connected. The OTG_FS core issues a host port interrupt triggered by the device connected bit in the host port control and status (PCDET bit in OTG_HPRT). Host detection of peripheral a disconnection The peripheral disconnection event triggers the disconnect detected interrupt (DISCINT bit in OTG_GINTSTS). Host enumeration After detecting a peripheral connection the host must start the enumeration process by sending USB reset and configuration commands to the new peripheral. Before starting to drive a USB reset, the application waits for the OTG interrupt triggered by the debounce done bit (DBCDNE bit in OTG_GOTGINT), which indicates that the bus is stable again after the electrical debounce caused by the attachment of a pull-up resistor on DP (FS) or DM (LS). The application drives a USB reset signaling (single-ended zero) over the USB by keeping the port reset bit set in the host port control and status register (PRST bit in OTG_HPRT) for a minimum of 10 ms and a maximum of 20 ms. The application takes care of the timing count and then of clearing the port reset bit. Once the USB reset sequence has completed, the host port interrupt is triggered by the port enable/disable change bit (PENCHNG bit in OTG_HPRT). This informs the application that the speed of the enumerated peripheral can be read from the port speed field in the host port control and status register (PSPD bit in OTG_HPRT) and that the host is starting to drive SOFs (FS) or Keep alives (LS). The host is now ready to complete the peripheral enumeration by sending peripheral configuration commands. Host suspend The application decides to suspend the USB activity by setting the port suspend bit in the host port control and status register (PSUSP bit in OTG_HPRT). The OTG_FS core stops sending SOFs and enters the suspended state. The suspended state can be optionally exited on the remote device’s initiative (remote wakeup). In this case the remote wakeup interrupt (WKUPINT bit in OTG_GINTSTS) is generated upon detection of a remote wakeup signaling, the port resume bit in the host port control and status register (PRES bit in OTG_HPRT) self-sets, and resume signaling is automatically driven over the USB. The application must time the resume window and then clear the port resume bit to exit the suspended state and restart the SOF. If the suspended state is exited on the host initiative, the application must set the port resume bit to start resume signaling on the host port, time the resume window and finally clear the port resume bit. 1498/1680 DocID024597 Rev 1 RM0351 43.7.3 USB on-the-go full-speed (OTG_FS) Host channels The OTG_FS core instantiates 12 host channels. Each host channel supports an USB host transfer (USB pipe). The host is not able to support more than 12 transfer requests at the same time. If more than 12 transfer requests are pending from the application, the host controller driver (HCD) must re-allocate channels when they become available from previous duty, that is, after receiving the transfer completed and channel halted interrupts. Each host channel can be configured to support in/out and any type of periodic/nonperiodic transaction. Each host channel makes us of proper control (OTG_HCCHARx), transfer configuration (OTG_HCTSIZx) and status/interrupt (OTG_HCINTx) registers with associated mask (OTG_HCINTMSKx) registers. Host channel control • The following host channel controls are available to the application through the host channel-x characteristics register (OTG_HCCHARx): – Channel enable/disable – Program the FS/LS speed of target USB peripheral – Program the address of target USB peripheral – Program the endpoint number of target USB peripheral – Program the transfer IN/OUT direction – Program the USB transfer type (control, bulk, interrupt, isochronous) – Program the maximum packet size (MPS) – Program the periodic transfer to be executed during odd/even frames Host channel transfer The host channel transfer size registers (OTG_HCTSIZx) allow the application to program the transfer size parameters, and read the transfer status. Programming must be done before setting the channel enable bit in the host channel characteristics register. Once the endpoint is enabled the packet count field is read-only as the OTG_FS core updates it according to the current transfer status. • The following transfer parameters can be programmed: – transfer size in bytes – number of packets making up the overall transfer size – initial data PID Host channel status/interrupt The host channel-x interrupt register (OTG_HCINTx) indicates the status of an endpoint with respect to USB- and AHB-related events. The application must read these register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read these registers, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. DocID024597 Rev 1 1499/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 The mask bits for each interrupt source of each channel are also available in the OTG_HCINTMSKx register. • 43.7.4 The host core provides the following status checks and interrupt generation: – Transfer completed interrupt, indicating that the data transfer is complete on both the application (AHB) and USB sides – Channel has stopped due to transfer completed, USB transaction error or disable command from the application – Associated transmit FIFO is half or completely empty (IN endpoints) – ACK response received – NAK response received – STALL response received – USB transaction error due to CRC failure, timeout, bit stuff error, false EOP – Babble error – frame overrun – data toggle error Host scheduler The host core features a built-in hardware scheduler which is able to autonomously re-order and manage the USB transaction requests posted by the application. At the beginning of each frame the host executes the periodic (isochronous and interrupt) transactions first, followed by the nonperiodic (control and bulk) transactions to achieve the higher level of priority granted to the isochronous and interrupt transfer types by the USB specification. The host processes the USB transactions through request queues (one for periodic and one for nonperiodic). Each request queue can hold up to 8 entries. Each entry represents a pending transaction request from the application, and holds the IN or OUT channel number along with other information to perform a transaction on the USB. The order in which the requests are written to the queue determines the sequence of the transactions on the USB interface. At the beginning of each frame, the host processes the periodic request queue first, followed by the nonperiodic request queue. The host issues an incomplete periodic transfer interrupt (IPXFR bit in OTG_GINTSTS) if an isochronous or interrupt transaction scheduled for the current frame is still pending at the end of the current frame. The OTG_FS core is fully responsible for the management of the periodic and nonperiodic request queues.The periodic transmit FIFO and queue status register (OTG_HPTXSTS) and nonperiodic transmit FIFO and queue status register (OTG_HNPTXSTS) are read-only registers which can be used by the application to read the status of each request queue. They contain: • The number of free entries currently available in the periodic (nonperiodic) request queue (8 max) • Free space currently available in the periodic (nonperiodic) Tx FIFO (out-transactions) • IN/OUT token, host channel number and other status information. As request queues can hold a maximum of 8 entries each, the application can push to schedule host transactions in advance with respect to the moment they physically reach the SB for a maximum of 8 pending periodic transactions plus 8 pending nonperiodic transactions. To post a transaction request to the host scheduler (queue) the application must check that there is at least 1 entry available in the periodic (nonperiodic) request queue by reading the 1500/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) PTXQSAV bits in the OTG_HNPTXSTS register or NPTQXSAV bits in the OTG_HNPTXSTS register. 43.8 SOF trigger Figure 492. SOF connectivity (SOF trigger output to TIM and ITR1 connection) 62)SXOVHRXWSXWWR H[WHUQDODXGLRFRQWURO 9%86 ,75 62)SXOVH ' ' 7,0 62)JHQ ,' 86%PLFUR$%FRQQHFWRU 670 966 06Y9 The OTG_FS core provides means to monitor, track and configure SOF framing in the host and peripheral, as well as an SOF pulse output connectivity feature. Such utilities are especially useful for adaptive audio clock generation techniques, where the audio peripheral needs to synchronize to the isochronous stream provided by the PC, or the host needs to trim its framing rate according to the requirements of the audio peripheral. 43.8.1 Host SOFs In host mode the number of PHY clocks occurring between the generation of two consecutive SOF (FS) or Keep-alive (LS) tokens is programmable in the host frame interval register (HFIR), thus providing application control over the SOF framing period. An interrupt is generated at any start of frame (SOF bit in OTG_GINTSTS). The current frame number and the time remaining until the next SOF are tracked in the host frame number register (HFNUM). An SOF pulse signal, generated at any SOF starting token and with a width of 12 system clock cycles, can be made available externally on the SOF pin using the SOFOUTEN bit in the global control and configuration register. The SOF pulse is also internally connected to the input trigger of the timer. 43.8.2 Peripheral SOFs In device mode, the start of frame interrupt is generated each time an SOF token is received on the USB (SOF bit in OTG_GINTSTS). The corresponding frame number can be read from the device status register (FNSOF bit in OTG_DSTS). An SOF pulse signal with a width of 12 system clock cycles is also generated and can be made available externally on the SOF pin by using the SOF output enable bit in the global control and configuration register (SOFOUTEN bit in OTG_GCCFG). The SOF pulse signal is also internally DocID024597 Rev 1 1501/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 connected to the TIM2 input trigger, so that the input capture feature, the output compare feature and the timer can be triggered by the SOF pulse. The TIM2 connection is enabled through the ITR1_RMP bits of the TIM2 option register (TIM2_OR). The end of periodic frame interrupt (OTG_GINTSTS/EOPF) is used to notify the application when 80%, 85%, 90% or 95% of the time frame interval elapsed depending on the periodic frame interval field in the device configuration register (PFIVL bit in OTG_DCFG). This feature can be used to determine if all of the isochronous traffic for that frame is complete. 43.9 Power options The power consumption of the OTG PHY is controlled by two bits in the general core configuration register: • PHY power down (OTG_GCCFG/PWRDWN) It switches on/off the full-speed transceiver module of the PHY. It must be preliminarily set to allow any USB operation. • VBUS detection enable (OTG_GCCFG/VBDEN) It switches on/off the VBUS sensing comparators associated with OTG operations. Power reduction techniques are available while in the USB suspended state, when the USB session is not yet valid or the device is disconnected. • Stop PHY clock (STPPCLK bit in OTG_PCGCCTL) When setting the stop PHY clock bit in the clock gating control register, most of the 48 MHz clock domain internal to the OTG full-speed core is switched off by clock gating. The dynamic power consumption due to the USB clock switching activity is cut even if the 48 MHz clock input is kept running by the application Most of the transceiver is also disabled, and only the part in charge of detecting the asynchronous resume or remote wakeup event is kept alive. • Gate HCLK (GATEHCLK bit in OTG_PCGCCTL) When setting the Gate HCLK bit in the clock gating control register, most of the system clock domain internal to the OTG_FS core is switched off by clock gating. Only the register read and write interface is kept alive. The dynamic power consumption due to the USB clock switching activity is cut even if the system clock is kept running by the application for other purposes. • USB system stop When the OTG_FS is in the USB suspended state, the application may decide to drastically reduce the overall power consumption by a complete shut down of all the clock sources in the system. USB System Stop is activated by first setting the Stop PHY clock bit and then configuring the system deep sleep mode in the power control system module (PWR). The OTG_FS core automatically reactivates both system and USB clocks by asynchronous detection of remote wakeup (as an host) or resume (as a device) signaling on the USB. To save dynamic power, the USB data FIFO is clocked only when accessed by the OTG_FS core. 1502/1680 DocID024597 Rev 1 RM0351 43.10 USB on-the-go full-speed (OTG_FS) Dynamic update of the OTG_HFIR register The USB core embeds a dynamic trimming capability of SOF framing period in host mode allowing to synchronize an external device with the SOF frames. When the OTG_HFIR register is changed within a current SOF frame, the SOF period correction is applied in the next frame as described in Figure 493. Figure 493. Updating OTG_HFIR dynamically KůĚKd'ͺ,/&ZǀĂůƵĞ сϰϬϬƉĞƌŝŽĚƐ Kd'ͺ,/&ZǀĂůƵĞ сϰϱϬƉĞƌŝŽĚƐн,/&ZǁƌŝƚĞůĂƚĞŶĐLJ EĞǁKd'ͺ,/&ZǀĂůƵĞ сϰϱϬƉĞƌŝŽĚƐ ^K& ƌĞůŽĂĚ >ĂƚĞŶĐLJ ͙ ͙ ͙ ͙ ϭ Ϭ ϰϱϬ ϰϰϵ ϰϱϬ ϭ Ϭ ϰϱϬ ϰϰϵ &ƌĂŵĞ ƚŝŵĞƌ ϰϬϬ ϰϱϬ ϰϰϵ ǀĂůƵĞ ϭ Ϭ ϰϬϬ ϯϵϵ Kd'ͺ,&/Z ǁƌŝƚĞ ϭ Ϭ ϰϬϬ ϯϵϵ Kd'ͺ,&/Z ͙ ĂŝϭϴϰϰϬ 43.11 USB data FIFOs The USB system features 1.25 Kbyte of dedicated RAM with a sophisticated FIFO control mechanism. The packet FIFO controller module in the OTG_FS core organizes RAM space into Tx FIFOs into which the application pushes the data to be temporarily stored before the USB transmission, and into a single Rx FIFO where the data received from the USB are temporarily stored before retrieval (popped) by the application. The number of instructed FIFOs and how these are organized inside the RAM depends on the device’s role. In peripheral mode an additional Tx FIFO is instructed for each active IN endpoint. Any FIFO size is software configured to better meet the application requirements. DocID024597 Rev 1 1503/1680 1635 USB on-the-go full-speed (OTG_FS) 43.11.1 RM0351 Peripheral FIFO architecture Figure 494. Device-mode FIFO address mapping and AHB FIFO access mapping 6LQJOHGDWD ),)2 ,1HQGSRLQW7[),)2[ '),)2SXVKDFFHVV IURP$+% 'HGLFDWHG7[ ),)2[FRQWURO RSWLRQDO 0$&SRS ,1HQGSRLQW7[),)2 '),)2SXVKDFFHVV IURP$+% 7[),)2[ SDFNHW 27*B',(37;)[>@ 27*B',(37;)[>@ 'HGLFDWHG7[ ),)2FRQWURO RSWLRQDO 7[),)2 SDFNHW 27*B',(37;)>@ 27*B',(37;)>@ 0$&SRS ,1HQGSRLQW7[),)2 '),)2SXVKDFFHVV IURP$+% 'HGLFDWHG7[ ),)2FRQWURO RSWLRQDO 7[),)2 SDFNHW 27*B',(37;)>@ 27*B',(37;)>@ 0$&SRS $Q\287HQGSRLQW '),)2SRSDFFHVV IURP$+% 'HGLFDWHG7[ ),)2FRQWURO RSWLRQDO 5[SDFNHWV 0$&SXVK 27*B*5;)6,=>@ $ 5[VWDUWDGGUHVVIL[HG WR 06Y9 Peripheral Rx FIFO The OTG peripheral uses a single receive FIFO that receives the data directed to all OUT endpoints. Received packets are stacked back-to-back until free space is available in the Rx FIFO. The status of the received packet (which contains the OUT endpoint destination number, the byte count, the data PID and the validity of the received data) is also stored by the core on top of the data payload. When no more space is available, host transactions are NACKed and an interrupt is received on the addressed endpoint. The size of the receive FIFO is configured in the receive FIFO Size register (OTG_GRXFSIZ). The single receive FIFO architecture makes it more efficient for the USB peripheral to fill in the receive RAM buffer: • All OUT endpoints share the same RAM buffer (shared FIFO) • The OTG_FS core can fill in the receive FIFO up to the limit for any host sequence of OUT tokens The application keeps receiving the Rx FIFO non-empty interrupt (RXFLVL bit in OTG_GINTSTS) as long as there is at least one packet available for download. It reads the packet information from the receive status read and pop register (OTG_GRXSTSP) and finally pops data off the receive FIFO by reading from the endpoint-related pop address. 1504/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Peripheral Tx FIFOs The core has a dedicated FIFO for each IN endpoint. The application configures FIFO sizes by writing the endpoint 0 transmit FIFO size register (OTG_DIEPTXF0) for IN endpoint0 and the device IN endpoint transmit FIFOx registers (OTG_DIEPTXFx) for IN endpoint-x. 43.11.2 Host FIFO architecture Figure 495. Host-mode FIFO address mapping and AHB FIFO access mapping 6LQJOHGDWD ),)2 $Q\SHULRGLFFKDQQHO '),)2SXVKDFFHVV IURP$+% 3HULRGLF7[),)2 FRQWURO RSWLRQDO 3HULRGLF7[ SDFNHWV 27*B+37;)6,=>@ 27*B+37;)6,=>@ 0$&SRS $Q\QRQSHULRGLF FKDQQHO'),)2SXVK DFFHVVIURP$+% 1RQSHULRGLF7[ ),)2FRQWURO 1RQSHULRGLF 7[SDFNHWV 27*B+137;)6,=>@ 27*B+137;)6,=>@ 0$&SRS 5[SDFNHWV $Q\FKDQQHO'),)2SRS DFFHVVIURP$+% 27*B*5;)6,=>@ 5[),)2FRQWURO 5[VWDUWDGGUHVVIL[HGWR $ 0$&SXVK 06Y9 Host Rx FIFO The host uses one receiver FIFO for all periodic and nonperiodic transactions. The FIFO is used as a receive buffer to hold the received data (payload of the received packet) from the USB until it is transferred to the system memory. Packets received from any remote IN endpoint are stacked back-to-back until free space is available. The status of each received packet with the host channel destination, byte count, data PID and validity of the received data are also stored into the FIFO. The size of the receive FIFO is configured in the receive FIFO size register (OTG_GRXFSIZ). The single receive FIFO architecture makes it highly efficient for the USB host to fill in the receive data buffer: • All IN configured host channels share the same RAM buffer (shared FIFO) • The OTG_FS core can fill in the receive FIFO up to the limit for any sequence of IN tokens driven by the host software The application receives the Rx FIFO not-empty interrupt as long as there is at least one packet available for download. It reads the packet information from the receive status read and pop register and finally pops the data off the receive FIFO. DocID024597 Rev 1 1505/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Host Tx FIFOs The host uses one transmit FIFO for all non-periodic (control and bulk) OUT transactions and one transmit FIFO for all periodic (isochronous and interrupt) OUT transactions. FIFOs are used as transmit buffers to hold the data (payload of the transmit packet) to be transmitted over the USB. The size of the periodic (nonperiodic) Tx FIFO is configured in the host periodic (nonperiodic) transmit FIFO size OTG_HPTXFSIZ / OTG_HNPTXFSIZ) register. The two Tx FIFO implementation derives from the higher priority granted to the periodic type of traffic over the USB frame. At the beginning of each frame, the built-in host scheduler processes the periodic request queue first, followed by the nonperiodic request queue. The two transmit FIFO architecture provides the USB host with separate optimization for periodic and nonperiodic transmit data buffer management: • All host channels configured to support periodic (nonperiodic) transactions in the OUT direction share the same RAM buffer (shared FIFOs) • The OTG_FS core can fill in the periodic (nonperiodic) transmit FIFO up to the limit for any sequence of OUT tokens driven by the host software The OTG_FS core issues the periodic Tx FIFO empty interrupt (PTXFE bit in OTG_GINTSTS) as long as the periodic Tx FIFO is half or completely empty, depending on the value of the periodic Tx FIFO empty level bit in the AHB configuration register (PTXFELVL bit in OTG_GAHBCFG). The application can push the transmission data in advance as long as free space is available in both the periodic Tx FIFO and the periodic request queue. The host periodic transmit FIFO and queue status register (OTG_HPTXSTS) can be read to know how much space is available in both. OTG_FS core issues the non periodic Tx FIFO empty interrupt (NPTXFE bit in OTG_GINTSTS) as long as the nonperiodic Tx FIFO is half or completely empty depending on the non periodic Tx FIFO empty level bit in the AHB configuration register (TXFELVL bit in OTG_GAHBCFG). The application can push the transmission data as long as free space is available in both the nonperiodic Tx FIFO and nonperiodic request queue. The host nonperiodic transmit FIFO and queue status register (OTG_HNPTXSTS) can be read to know how much space is available in both. 43.11.3 FIFO RAM allocation Device mode Receive FIFO RAM allocation: the application should allocate RAM for SETUP Packets: 10 locations must be reserved in the receive FIFO to receive SETUP packets on control endpoint. The core does not use these locations, which are reserved for SETUP packets, to write any other data. One location is to be allocated for Global OUT NAK. Status information is written to the FIFO along with each received packet. Therefore, a minimum space of (Largest Packet Size / 4) + 1 must be allocated to receive packets. If multiple isochronous endpoints are enabled, then at least two (Largest Packet Size / 4) + 1 spaces must be allocated to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 1 spaces are recommended so that when the previous packet is being transferred to the CPU, the USB can receive the subsequent packet. Along with the last packet for each endpoint, transfer complete status information is also pushed to the FIFO. Typically, one location for each OUT endpoint is recommended. 1506/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Transmit FIFO RAM allocation: the minimum RAM space required for each IN Endpoint Transmit FIFO is the maximum packet size for that particular IN endpoint. Note: More space allocated in the transmit IN Endpoint FIFO results in better performance on the USB. Host mode Receive FIFO RAM allocation: Status information is written to the FIFO along with each received packet. Therefore, a minimum space of (Largest Packet Size / 4) + 1 must be allocated to receive packets. If multiple isochronous channels are enabled, then at least two (Largest Packet Size / 4) + 1 spaces must be allocated to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 1 spaces are recommended so that when the previous packet is being transferred to the CPU, the USB can receive the subsequent packet. Along with the last packet in the host channel, transfer complete status information is also pushed to the FIFO. So one location must be allocated for this. Transmit FIFO RAM allocation: The minimum amount of RAM required for the host Non-periodic Transmit FIFO is the largest maximum packet size among all supported non-periodic OUT channels. Typically, two Largest Packet Sizes worth of space is recommended, so that when the current packet is under transfer to the USB, the CPU can get the next packet. The minimum amount of RAM required for host periodic Transmit FIFO is the largest maximum packet size out of all the supported periodic OUT channels. If there is at least one Isochronous OUT endpoint, then the space must be at least two times the maximum packet size of that channel. Note: More space allocated in the Transmit Non-periodic FIFO results in better performance on the USB. 43.12 OTG_FS system performance Best USB and system performance is achieved owing to the large RAM buffers, the highly configurable FIFO sizes, the quick 32-bit FIFO access through AHB push/pop registers and, especially, the advanced FIFO control mechanism. Indeed, this mechanism allows the OTG_FS to fill in the available RAM space at best regardless of the current USB sequence. With these features: • • The application gains good margins to calibrate its intervention in order to optimize the CPU bandwidth usage: – It can accumulate large amounts of transmission data in advance compared to when they are effectively sent over the USB – It benefits of a large time margin to download data from the single receive FIFO The USB Core is able to maintain its full operating rate, that is to provide maximum fullspeed bandwidth with a great margin of autonomy versus application intervention: – It has a large reserve of transmission data at its disposal to autonomously manage the sending of data over the USB – It has a lot of empty space available in the receive buffer to autonomously fill it in with the data coming from the USB DocID024597 Rev 1 1507/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 As the OTG_FS core is able to fill in the 1.25 Kbyte RAM buffer very efficiently, and as 1.25 Kbyte of transmit/receive data is more than enough to cover a full speed frame, the USB system is able to withstand the maximum full-speed data rate for up to one USB frame (1 ms) without any CPU intervention. 43.13 OTG_FS interrupts When the OTG_FS controller is operating in one mode, either device or host, the application must not access registers from the other mode. If an illegal access occurs, a mode mismatch interrupt is generated and reflected in the Core interrupt register (MMIS bit in the OTG_GINTSTS register). When the core switches from one mode to the other, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset. Figure 496 shows the interrupt hierarchy. Figure 496. Interrupt hierarchy /2 ENDP?MULTI?PROC?INTRPT !.$ )NTERRUPT /2 ENDP?INTERRUPT;= 'LOBAL INTERRUPT MASK "IT !(" CONFIGURATION REGISTER !.$ #ORE INTERRUPT MASK REGISTER #ORE INTERRUPT REGISTER $EVICE ALL ENDPOINTS INTERRUPT REGISTER /54 ENDPOINTS ). ENDPOINTS )NTERRUPT SOURCES $EVICE )./54 ENDPOINT INTERRUPT REGISTERS TO /4' INTERRUPT REGISTER $EVICE ALL ENDPOINTS INTERRUPT MASK REGISTER $EVICE )./54 ENDPOINTS COMMON INTERRUPT MASK REGISTER $EVICE EACH ENDPOINT INTERRUPT REGISTER %0/54 %0). $EVICE EACH ENDPOINT INTERRUPT MASK REGISTER $EVICE EACH )./54 ENDPOINT INTERRUPT MASK REGISTER (OST PORT CONTROL AND STATUS REGISTER (OST ALL CHANNELS INTERRUPT REGISTER (OST CHANNELS INTERRUPT REGISTERS TO (OST ALL CHANNELS INTERRUPT MASK REGISTER (OST CHANNELS INTERRUPT MASK REGISTERS TO -3V6 1. The core interrupt register bits are shown in OTG core interrupt register (OTG_GINTSTS) on page 1521. 1508/1680 DocID024597 Rev 1 RM0351 43.14 USB on-the-go full-speed (OTG_FS) OTG_FS control and status registers By reading from and writing to the control and status registers (CSRs) through the AHB slave interface, the application controls the OTG_FS controller. These registers are 32 bits wide, and the addresses are 32-bit block aligned. The OTG_FS registers must be accessed by words (32 bits). CSRs are classified as follows: • Core global registers • Host-mode registers • Host global registers • Host port CSRs • Host channel-specific registers • Device-mode registers • Device global registers • Device endpoint-specific registers • Power and clock-gating registers • Data FIFO (DFIFO) access registers Only the Core global, Power and clock-gating, Data FIFO access, and host port control and status registers can be accessed in both host and device modes. When the OTG_FS controller is operating in one mode, either device or host, the application must not access registers from the other mode. If an illegal access occurs, a mode mismatch interrupt is generated and reflected in the Core interrupt register (MMIS bit in the OTG_GINTSTS register). When the core switches from one mode to the other, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset. 43.14.1 CSR memory map The host and device mode registers occupy different addresses. All registers are implemented in the AHB clock domain. Global CSR map These registers are available in both host and device modes. Table 253. Core global control and status registers (CSRs) Acronym Address offset Register name OTG_GOTGCTL 0x000 OTG control and status register (OTG_GOTGCTL) on page 1513 OTG_GOTGINT 0x004 OTG interrupt register (OTG_GOTGINT) on page 1515 OTG_GAHBCFG 0x008 OTG AHB configuration register (OTG_GAHBCFG) on page 1517 OTG_GUSBCFG 0x00C OTG USB configuration register (OTG_GUSBCFG) on page 1517 OTG_GRSTCTL 0x010 OTG reset register (OTG_GRSTCTL) on page 1519 OTG_GINTSTS 0x014 OTG core interrupt register (OTG_GINTSTS) on page 1521 OTG_GINTMSK 0x018 OTG interrupt mask register (OTG_GINTMSK) on page 1525 DocID024597 Rev 1 1509/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Table 253. Core global control and status registers (CSRs) (continued) Acronym Address offset Register name OTG_GRXSTSR 0x01C OTG_GRXSTSP 0x020 OTG_FS Receive status debug read/OTG status read and pop registers (OTG_GRXSTSR/OTG_GRXSTSP) on page 1528 OTG_GRXFSIZ 0x024 OTG Receive FIFO size register (OTG_GRXFSIZ) on page 1530 OTG_HNPTXFSIZ/ OTG_DIEPTXF0(1) 0x028 OTG Host non-periodic transmit FIFO size register (OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0) OTG_HNPTXSTS 0x02C OTG non-periodic transmit FIFO/queue status register (OTG_HNPTXSTS) on page 1532 OTG_GCCFG 0x038 OTG general core configuration register (OTG_GCCFG) on page 1533 OTG_CID 0x03C OTG core ID register (OTG_CID) on page 1534 OTG_GPWRDN 0x058 OTG power down register (OTG_GPWRDN) on page 1539 OTG_GADPCTL 0x060 OTG ADP timer, control and status register (OTG_GADPCTL) on page 1539 OTG_HPTXFSIZ 0x100 OTG Host periodic transmit FIFO size register (OTG_HPTXFSIZ) on page 1541 OTG_DIEPTXFx 0x104 0x124 ... 0x184 OTG device IN endpoint transmit FIFO size register (OTG_DIEPTXFx) (x = 1..5 , where x is the FIFO_number) on page 1542 1. The general rule is to use OTG_HNPTXFSIZ for host mode and OTG_DIEPTXF0 for device mode. Host-mode CSR map These registers must be programmed every time the core changes to host mode. Table 254. Host-mode control and status registers (CSRs) Acronym Offset address Register name OTG_HCFG 0x400 OTG Host configuration register (OTG_HCFG) on page 1542 OTG_HFIR 0x404 OTG Host frame interval register (OTG_HFIR) on page 1543 OTG_HFNUM 0x408 OTG Host frame number/frame time remaining register (OTG_HFNUM) on page 1544 OTG_HPTXSTS 0x410 OTG_Host periodic transmit FIFO/queue status register (OTG_HPTXSTS) on page 1545 OTG_HAINT 0x414 OTG Host all channels interrupt register (OTG_HAINT) on page 1546 OTG_HAINTMSK 0x418 OTG Host all channels interrupt mask register (OTG_HAINTMSK) on page 1546 OTG_HPRT 0x440 OTG Host port control and status register (OTG_HPRT) on page 1547 1510/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Table 254. Host-mode control and status registers (CSRs) (continued) Acronym Offset address Register name OTG_HCCHARx 0x500 0x520 ... 0x660 OTG Host channel-x characteristics register (OTG_HCCHARx) (x = 0..11, where x = Channel_number) on page 1549 OTG_HCINTx 0x508 0x528 .... 0x668 OTG Host channel-x interrupt register (OTG_HCINTx) (x = 0..11, where x = Channel_number) on page 1551 OTG_HCINTMSKx 0x50C 0x52C .... 0x66C OTG Host channel-x interrupt mask register (OTG_HCINTMSKx) (x = 0..11, where x = Channel_number) on page 1552 OTG_HCTSIZx 0x510 0x530 .... 0x670 OTG Host channel-x transfer size register (OTG_HCTSIZx) (x = 0..11, where x = Channel_number) on page 1553 Device-mode CSR map These registers must be programmed every time the core changes to device mode. Table 255. Device-mode control and status registers Acronym Offset address Register name OTG_DCFG 0x800 OTG device configuration register (OTG_DCFG) on page 1554 OTG_DCTL 0x804 OTG device control register (OTG_DCTL) on page 1555 OTG_DSTS 0x808 OTG device status register (OTG_DSTS) on page 1557 OTG_DIEPMSK 0x810 OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK) on page 1558 OTG_DOEPMSK 0x814 OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) on page 1559 OTG_DAINT 0x818 OTG device all endpoints interrupt register (OTG_DAINT) on page 1559 OTG_DAINTMSK 0x81C OTG all endpoints interrupt mask register (OTG_DAINTMSK) on page 1560 OTG_DVBUSDIS 0x828 OTG device VBUS discharge time register (OTG_DVBUSDIS) on page 1561 OTG_DVBUSPULSE 0x82C OTG device VBUS pulsing time register (OTG_DVBUSPULSE) on page 1561 DocID024597 Rev 1 1511/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Table 255. Device-mode control and status registers (continued) Acronym Offset address Register name OTG_DIEPEMPMSK 0x834 OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK) on page 1562 OTG_DIEPCTL0 0x900 OTG device control IN endpoint 0 control register (OTG_DIEPCTL0) on page 1562 OTG_DIEPCTLx 0x920 0x940 ... 0x9A0 OTG device endpoint-x control register (OTG_DIEPCTLx) (x = 1..5 , where x = Endpoint_number) on page 1564 OTG_DIEPINTx 0x908 0x928 .... 0x9A8 OTG device endpoint-x interrupt register (OTG_DIEPINTx) (x = 0..5 , where x = Endpoint_number) on page 1570 OTG_DIEPTSIZ0 0x910 OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0) on page 1572 OTG_DTXFSTSx 0x918 0x938 .... 0x9B8 OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) (x = 0..5 , where x = Endpoint_number) on page 1575 OTG_DIEPTSIZx 0x930 0x950 ... 0x9B0 OTG device IN endpoint-x transfer size register (OTG_DIEPTSIZx) (x = 1..5 , where x= Endpoint_number) on page 1574 OTG_DOEPCTL0 0xB00 OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0) on page 1566 OTG_DOEPCTLx 0xB20 0xB40 ... 0xBA0 OTG device endpoint-x control register (OTG_DOEPCTLx) (x = 1..5 , where x = Endpoint_number) on page 1568 OTG_DOEPINTx 0xB08 0xB28 ... 0xBA8 OTG device endpoint-x interrupt register (OTG_DOEPINTx) (x = 0..5 , where x = Endpoint_number) on page 1571 OTG_DOEPTSIZ0 0xB10 OTG device OUT endpoint 0 transfer size register (OTG_DOEPTSIZ0) on page 1573 OTG_DOEPTSIZx 0xB30 0xB50 ... 0xBB0 OTG device OUT endpoint-x transfer size register (OTG_DOEPTSIZx) (x = 1..5 , where x = Endpoint_number) on page 1575 1512/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Data FIFO (DFIFO) access register map These registers, available in both host and device modes, are used to read or write the FIFO space for a specific endpoint or a channel, in a given direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the channel. Table 256. Data FIFO (DFIFO) access register map FIFO access register section Address range Access Device IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access Device OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access 0x1000–0x1FFC w r Device IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access Device OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access 0x2000–0x2FFC w r ... ... ... Device IN Endpoint x(1)/Host OUT Channel x(1): DFIFO Write Access 0xX000–0xXFFC Device OUT Endpoint x(1)/Host IN Channel x(1): DFIFO Read Access w r 1. Where x is 5 in device mode and 11 in host mode. Power and clock gating CSR map There is a single register for power and clock gating. It is available in both host and device modes. Table 257. Power and clock gating control and status registers Register name Acronym Power and clock gating control register PCGCR Reserved 43.15 Offset address: 0xE00–0xFFF 0xE00-0xE04 - 0xE05–0xFFF OTG_FS registers These registers are available in both host and device modes, and do not need to be reprogrammed when switching between these modes. Bit values in the register descriptions are expressed in binary unless otherwise specified. 43.15.1 OTG control and status register (OTG_GOTGCTL) Address offset: 0x000 Reset value: 0x0001 0000 The OTG_GOTGCTL register controls the behavior and reflects the status of the OTG function of the core. DocID024597 Rev 1 1513/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 31 30 29 28 27 26 25 24 23 22 21 20 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTG VER 15 Res. 14 Res. 13 Res. 12 EHEN rw 11 10 DHNP HSHNP EN EN rw rw 9 8 HNP RQ HNG SCS rw r 7 Res. 6 Res. 5 Res. 19 18 BSVLD ASVLD 17 16 DBCT CID STS r rw r r r 4 3 2 1 0 SRQ SRQ SCS rw r Res. Res. Res. Bits 31:21 Reserved, must be kept at reset value. Bit 20 OTGVER: OTG version Selects the OTG revision. 0:OTG Version 1.3. In this version the core supports Data line pulsing and VBUS pulsing for SRP. 1:OTG Version 2.0. In this version the core supports only Data line pulsing for SRP. Bit 19 BSVLD: B-session valid Indicates the device mode transceiver status. 0: B-session is not valid. 1: B-session is valid. In OTG mode, you can use this bit to determine if the device is connected or disconnected. Note: Only accessible in device mode. Bit 18 ASVLD: A-session valid Indicates the host mode transceiver status. 0: A-session is not valid 1: A-session is valid Note: Only accessible in host mode. Bit 17 DBCT: Long/short debounce time Indicates the debounce time of a detected connection. 0: Long debounce time, used for physical connections (100 ms + 2.5 µs) 1: Short debounce time, used for soft connections (2.5 µs) Note: Only accessible in host mode. Bit 16 CIDSTS: Connector ID status Indicates the connector ID status on a connect event. 0: The OTG_FS controller is in A-device mode 1: The OTG_FS controller is in B-device mode Note: Accessible in both device and host modes. Bits 15:13 Reserved, must be kept at reset value. Bit 12 EHEN: Embedded host enable It is used to select between OTG A device state machine and embedded Host state machine. 0: OTG A device state machine is selected 1: Embedded host state machine is selected 1514/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Bit 11 DHNPEN: Device HNP enabled The application sets this bit when it successfully receives a SetFeature.SetHNPEnable command from the connected USB host. 0: HNP is not enabled in the application 1: HNP is enabled in the application Note: Only accessible in device mode. Bit 10 HSHNPEN: host set HNP enable The application sets this bit when it has successfully enabled HNP (using the SetFeature.SetHNPEnable command) on the connected device. 0: Host Set HNP is not enabled 1: Host Set HNP is enabled Note: Only accessible in host mode. Bit 9 HNPRQ: HNP request The application sets this bit to initiate an HNP request to the connected USB host. The application can clear this bit by writing a 0 when the host negotiation success status change bit in the OTG_GOTGINT register (HNSSCHG bit in OTG_GOTGINT) is set. The core clears this bit when the HNSSCHG bit is cleared. 0: No HNP request 1: HNP request Note: Only accessible in device mode. Bit 8 HNGSCS: Host negotiation success The core sets this bit when host negotiation is successful. The core clears this bit when the HNP Request (HNPRQ) bit in this register is set. 0: Host negotiation failure 1: Host negotiation success Note: Only accessible in device mode. Bits 2:7 Reserved, must be kept at reset value. Bit 1 SRQ: Session request The application sets this bit to initiate a session request on the USB. The application can clear this bit by writing a 0 when the host negotiation success status change bit in the OTG_GOTGINT register (HNSSCHG bit in OTG_GOTGINT) is set. The core clears this bit when the HNSSCHG bit is cleared. If you use the USB 1.1 full-speed serial transceiver interface to initiate the session request, the application must wait until VBUS discharges to 0.2 V, after the B-Session Valid bit in this register (BSVLD bit in OTG_GOTGCTL) is cleared. This discharge time varies between different PHYs and can be obtained from the PHY vendor. 0: No session request 1: Session request Note: Only accessible in device mode. Bit 0 SRQSCS: Session request success The core sets this bit when a session request initiation is successful. 0: Session request failure 1: Session request success Note: Only accessible in device mode. 43.15.2 OTG interrupt register (OTG_GOTGINT) Address offset: 0x04 Reset value: 0x0000 0000 DocID024597 Rev 1 1515/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ID CHNG DBC DNE ADTO CHG HNG DET Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. HNSS CHG SRSS CHG Res. Res. Res. Res. Res. SEDET Res. Res. rc_w1 rc_w1 Res. Res. Res. Res. Res. rc_w1 Bits 31:21 Reserved, must be kept at reset value. Bit 20 IDCHNG: This bit when set indicates that there is a change in the value of the ID input pin. Bit 19 DBCDNE: Debounce done The core sets this bit when the debounce is completed after the device connect. The application can start driving USB reset after seeing this interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is set in the OTG_GUSBCFG register (HNPCAP bit or SRPCAP bit in OTG_GUSBCFG, respectively). Note: Only accessible in host mode. Bit 18 ADTOCHG: A-device timeout change The core sets this bit to indicate that the A-device has timed out while waiting for the B-device to connect. Note: Accessible in both device and host modes. Bit 17 HNGDET: Host negotiation detected The core sets this bit when it detects a host negotiation request on the USB. Note: Accessible in both device and host modes. Bits 16:10 Reserved, must be kept at reset value. Bit 9 HNSSCHG: Host negotiation success status change The core sets this bit on the success or failure of a USB host negotiation request. The application must read the host negotiation success bit of the OTG_GOTGCTL register (HNGSCS bit in OTG_GOTGCTL) to check for success or failure. Note: Accessible in both device and host modes. Bits 7:3 Reserved, must be kept at reset value. Bit 8 SRSSCHG: Session request success status change The core sets this bit on the success or failure of a session request. The application must read the session request success bit in the OTG_GOTGCTL register (SRQSCS bit in OTG_GOTGCTL) to check for success or failure. Note: Accessible in both device and host modes. Bit 2 SEDET: Session end detected The core sets this bit to indicate that the level of the voltage on VBUS is no longer valid for a B-Peripheral session when VBUS < 0.8 V. Note: Accessible in both device and host modes. Bits 1:0 Reserved, must be kept at reset value. 1516/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) 43.15.3 OTG AHB configuration register (OTG_GAHBCFG) Address offset: 0x008 Reset value: 0x0000 0000 This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. PTXFE LVL TXFE LVL Res. GINT MSK rw rw Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:20 Reserved, must be kept at reset value. Bit 8 PTXFELVL: Periodic Tx FIFO empty level Indicates when the periodic Tx FIFO empty interrupt bit in the OTG_GINTSTS register (PTXFE bit in OTG_GINTSTS) is triggered. 0: PTXFE (in OTG_GINTSTS) interrupt indicates that the Periodic Tx FIFO is half empty 1: PTXFE (in OTG_GINTSTS) interrupt indicates that the Periodic Tx FIFO is completely empty Note: Only accessible in host mode. Bit 7 TXFELVL: Tx FIFO empty level In device mode, this bit indicates when IN endpoint Transmit FIFO empty interrupt (TXFE in OTG_DIEPINTx) is triggered: 0:The TXFE (in OTG_DIEPINTx) interrupt indicates that the IN Endpoint Tx FIFO is half empty 1:The TXFE (in OTG_DIEPINTx) interrupt indicates that the IN Endpoint Tx FIFO is completely empty In host mode, this bit indicates when the nonperiodic Tx FIFO empty interrupt (NPTXFE bit in OTG_GINTSTS) is triggered: 0:The NPTXFE (in OTG_GINTSTS) interrupt indicates that the nonperiodic Tx FIFO is half empty 1:The NPTXFE (in OTG_GINTSTS) interrupt indicates that the nonperiodic Tx FIFO is completely empty Bits 6:1 Reserved, must be kept at reset value for USB OTG FS. Bit 0 GINTMSK: Global interrupt mask The application uses this bit to mask or unmask the interrupt line assertion to itself. Irrespective of this bit’s setting, the interrupt status registers are updated by the core. 0: Mask the interrupt assertion to the application. 1: Unmask the interrupt assertion to the application. Note: Accessible in both device and host modes. 43.15.4 OTG USB configuration register (OTG_GUSBCFG) Address offset: 0x00C DocID024597 Rev 1 1517/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Reset value: 0x0000 1440 This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. FD MOD FH MOD Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw 14 13 12 11 10 7 6 5 4 3 2 1 0 Res. PHY SEL Res. Res. Res. 15 Res. Res. 9 8 TRDT HNP CAP SRP CAP rw rw rw r TOCAL rw Bit 31 Reserved, must be kept at reset value. Bit 30 FDMOD: Force device mode Writing a 1 to this bit, forces the core to device mode irrespective of the OTG_ID input pin. 0: Normal mode 1: Force device mode After setting the force bit, the application must wait at least 25 ms before the change takes effect. Note: Accessible in both device and host modes. Bit 29 FHMOD: Force host mode Writing a 1 to this bit, forces the core to host mode irrespective of the OTG_ID input pin. 0: Normal mode 1: Force host mode After setting the force bit, the application must wait at least 25 ms before the change takes effect. Note: Accessible in both device and host modes. Bits 28:24 Reserved, must be kept at reset value. Bits 25:15 Reserved, must be kept at reset value for USB OTG FS Bit 14 Reserved, must be kept at reset value. Bits 13:10 TRDT: USB turnaround time Sets the turnaround time in PHY clocks. To calculate the value of TRDT, use the following formula: TRDT = 4 × AHB clock + 1 PHY clock Examples: if AHB clock = 72 MHz (PHY Clock is 48), the TRDT is set to 9. if AHB clock = 48 MHz (PHY Clock is 48), the TRDT is set to 5. Note: Only accessible in device mode. Bit 9 HNPCAP: HNP-capable The application uses this bit to control the OTG_FS controller’s HNP capabilities. 0: HNP capability is not enabled. 1: HNP capability is enabled. Note: Accessible in both device and host modes. 1518/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Bit 8 SRPCAP: SRP-capable The application uses this bit to control the OTG_FS controller’s SRP capabilities. If the core operates as a non-SRP-capable B-device, it cannot request the connected A-device (host) to activate VBUS and start a session. 0: SRP capability is not enabled. 1: SRP capability is enabled. Note: Accessible in both device and host modes. Bit 7 Reserved, must be kept at reset value. Bit 6 PHYSEL: Full Speed serial transceiver select This bit is always 1 with read-only access. Bits5:3 Reserved, must be kept at reset value. Bits 2:0 TOCAL: FS timeout calibration The number of PHY clocks that the application programs in this field is added to the fullspeed interpacket timeout duration in the core to account for any additional delays introduced by the PHY. This can be required, because the delay introduced by the PHY in generating the line state condition can vary from one PHY to another. The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this field based on the speed of enumeration. The number of bit times added per PHY clock is 0.25 bit times. 43.15.5 OTG reset register (OTG_GRSTCTL) Address offset: 0x10 Reset value: 0x8000 0000 The application uses this register to reset various hardware features inside the core. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AHB IDL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14 13 12 11 10 9 8 7 6 r 15 Res. Res. Res. Res. Res. 5 4 3 2 1 0 TXFNUM TXF FLSH RXF FLSH Res. FCRST Res. CSRST rw rs rs DocID024597 Rev 1 rs rs 1519/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Bit 31 AHBIDL: AHB master idle Indicates that the AHB master state machine is in the Idle condition. Note: Accessible in both device and host modes. Bits 30:11 Reserved, must be kept at reset value for USB OTG FS Bits 10:6 TXFNUM: Tx FIFO number This is the FIFO number that must be flushed using the Tx FIFO Flush bit. This field must not be changed until the core clears the Tx FIFO Flush bit. 00000: – Non-periodic Tx FIFO flush in host mode – Tx FIFO 0 flush in device mode 00001: – Periodic Tx FIFO flush in host mode – Tx FIFO 1 flush in device mode 00010: Tx FIFO 2 flush in device mode ... 01111: Tx FIFO 15 flush in device mode 10000: Flush all the transmit FIFOs in device or host mode. Note: Accessible in both device and host modes. Bit 5 TXFFLSH: Tx FIFO flush This bit selectively flushes a single or all transmit FIFOs, but cannot do so if the core is in the midst of a transaction. The application must write this bit only after checking that the core is neither writing to the Tx FIFO nor reading from the Tx FIFO. Verify using these registers: Read—NAK Effective Interrupt ensures the core is not reading from the FIFO Write—AHBIDL bit in OTG_GRSTCTL ensures the core is not writing anything to the FIFO. Flushing is normally recommended when FIFOs are reconfigured. FIFO flushing is also recommended during device endpoint disable. The application must wait until the core clears this bit before performing any operations. This bit takes eight clocks to clear, using the slower clock of phy_clk or hclk. Note: Accessible in both device and host modes. Bit 4 RXFFLSH: Rx FIFO flush The application can flush the entire Rx FIFO using this bit, but must first ensure that the core is not in the middle of a transaction. The application must only write to this bit after checking that the core is neither reading from the Rx FIFO nor writing to the Rx FIFO. The application must wait until the bit is cleared before performing any other operations. This bit requires 8 clocks (slowest of PHY or AHB clock) to clear. Note: Accessible in both device and host modes. Bit 3 Reserved, must be kept at reset value. 1520/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Bit 2 FCRST: Host frame counter reset The application writes this bit to reset the frame number counter inside the core. When the frame counter is reset, the subsequent SOF sent out by the core has a frame number of 0. When application writes '1' to the bit, it might not be able to read back the value as it will get cleared by the core in a few clock cycles. Note: Only accessible in host mode. Bit 1 Reserved, must be kept at reset value. Bit 0 CSRST: Core soft reset Resets the HCLK and PHY clock domains as follows: Clears the interrupts and all the CSR register bits except for the following bits: – GATEHCLK bit in OTG_PCGCCTL – STPPCLK bit in OTG_PCGCCTL – FSLSPCS bits in OTG_HCFG – DSPD bit in OTG_DCFG – SDIS bit in OTG_DCTL – OTG_GCCFG register – OTG_GPWRDN register – OTG_GADPCTL register All module state machines (except for the AHB slave unit) are reset to the Idle state, and all the transmit FIFOs and the receive FIFO are flushed. Any transactions on the AHB Master are terminated as soon as possible, after completing the last data phase of an AHB transfer. Any transactions on the USB are terminated immediately. When ADP feature is enabled, the power management module is not reset by the core soft reset. The application can write to this bit any time it wants to reset the core. This is a self-clearing bit and the core clears this bit after all the necessary logic is reset in the core, which can take several clocks, depending on the current state of the core. Once this bit has been cleared, the software must wait at least 3 PHY clocks before accessing the PHY domain (synchronization delay). The software must also check that bit 31 in this register is set to 1 (AHB Master is Idle) before starting any operation. Typically, the software reset is used during software development and also when you dynamically change the PHY selection bits in the above listed USB configuration registers. When you change the PHY, the corresponding clock for the PHY is selected and used in the PHY domain. Once a new clock is selected, the PHY domain has to be reset for proper operation. Note: Accessible in both device and host modes. 43.15.6 OTG core interrupt register (OTG_GINTSTS) Address offset: 0x014 Reset value: 0x1400 0020 This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. DocID024597 Rev 1 1521/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 The application must clear the OTG_GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization. 31 30 29 28 27 26 WKUP INT SRQ INT DISC INT CIDS CHG LPM INT rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 r 15 14 13 12 11 10 25 ISOO DRP ENUM DNE USB RST USB SUSP ESUSP rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 23 22 21 20 19 18 17 16 Res. IPXFR/ IN COMP ISO OUT IISOI XFR OEP INT IEPINT Res. Res. HPRT INT RST DET r r rc_w1 rc_w1 rc_w1 r r 9 8 7 6 5 4 3 2 1 0 Res. GO NAK EFF GI NAK EFF NPTXF E RXF LVL SOF OTG INT MMIS CMOD r r r r rc_w1 r rc_w1 r PTXFE HCINT EOPF 24 Res. Bit 31 WKUPINT: Resume/remote wakeup detected interrupt Wakeup interrupt during suspend(L2) or LPM(L1) state. – During suspend(L2): In device mode, this interrupt is asserted when a resume is detected on the USB. In host mode, this interrupt is asserted when a remote wakeup is detected on the USB. – During LPM(L1): This interrupt is asserted for either Host Initiated Resume or Device Initiated Remote Wakeup on USB. Note: Accessible in both device and host modes. Bit 30 SRQINT: Session request/new session detected interrupt In host mode, this interrupt is asserted when a session request is detected from the device. In device mode, this interrupt is asserted when VBUS is in the valid range for a B-peripheral device. Accessible in both device and host modes. Bit 29 DISCINT: Disconnect detected interrupt Asserted when a device disconnect is detected. Note: Only accessible in host mode. Bit 28 CIDSCHG: Connector ID status change The core sets this bit when there is a change in connector ID status. Note: Accessible in both device and host modes. Bit 27 LPMINT: LPM interrupt In device mode, this interrupt is asserted when the device receives an LPM transaction and responds with a non-ERRORed response. In host mode, this interrupt is asserted when the device responds to an LPM transaction with a non-ERRORed response or when the host core has completed LPM transactions for the programmed number of times (RETRYCNT bit in OTG_GLPMCFG). This field is valid only if the LPMCAP bit in OTG_GLPMCFG is set to 1. Bit 26 PTXFE: Periodic Tx FIFO empty Asserted when the periodic transmit FIFO is either half or completely empty and there is space for at least one entry to be written in the periodic request queue. The half or completely empty status is determined by the periodic Tx FIFO empty level bit in the OTG_GAHBCFG register (PTXFELVL bit in OTG_GAHBCFG). Note: Only accessible in host mode. 1522/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Bit 25 HCINT: Host channels interrupt The core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in host mode). The application must read the OTG_HAINT register to determine the exact number of the channel on which the interrupt occurred, and then read the corresponding OTG_HCINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the OTG_HCINTx register to clear this bit. Note: Only accessible in host mode. Bit 24 HPRTINT: Host port interrupt The core sets this bit to indicate a change in port status of one of the OTG_FS controller ports in host mode. The application must read the OTG_HPRT register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the OTG_HPRT register to clear this bit. Note: Only accessible in host mode. Bit 23 RSTDET: Reset detected interrupt In device mode, this interrupt is asserted when a reset is detected on the USB in partial power-down mode when the device is in suspend. Note: Only accessible in device mode. Bit 22 Reserved, must be kept at reset value for USB OTG FS. Bit 21 IPXFR: Incomplete periodic transfer In host mode, the core sets this interrupt bit when there are incomplete periodic transactions still pending, which are scheduled for the current frame. INCOMPISOOUT: Incomplete isochronous OUT transfer In device mode, the core sets this interrupt to indicate that there is at least one isochronous OUT endpoint on which the transfer is not completed in the current frame. This interrupt is asserted along with the End of periodic frame interrupt (EOPF) bit in this register. Bit 20 IISOIXFR: Incomplete isochronous IN transfer The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not completed in the current frame. This interrupt is asserted along with the End of periodic frame interrupt (EOPF) bit in this register. Note: Only accessible in device mode. Bit 19 OEPINT: OUT endpoint interrupt The core sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of the core (in device mode). The application must read the OTG_DAINT register to determine the exact number of the OUT endpoint on which the interrupt occurred, and then read the corresponding OTG_DOEPINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding OTG_DOEPINTx register to clear this bit. Note: Only accessible in device mode. Bit 18 IEPINT: IN endpoint interrupt The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the core (in device mode). The application must read the OTG_DAINT register to determine the exact number of the IN endpoint on which the interrupt occurred, and then read the corresponding OTG_DIEPINTx register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding OTG_DIEPINTx register to clear this bit. Note: Only accessible in device mode. Bits 17:16 Reserved, must be kept at reset value. DocID024597 Rev 1 1523/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Bit 15 EOPF: End of periodic frame interrupt Indicates that the period specified in the periodic frame interval field of the OTG_DCFG register (PFIVL bit in OTG_DCFG) has been reached in the current frame. Note: Only accessible in device mode. Bit 14 ISOODRP: Isochronous OUT packet dropped interrupt The core sets this bit when it fails to write an isochronous OUT packet into the Rx FIFO because the Rx FIFO does not have enough space to accommodate a maximum size packet for the isochronous OUT endpoint. Note: Only accessible in device mode. Bit 13 ENUMDNE: Enumeration done The core sets this bit to indicate that speed enumeration is complete. The application must read the OTG_DSTS register to obtain the enumerated speed. Note: Only accessible in device mode. Bit 12 USBRST: USB reset The core sets this bit to indicate that a reset is detected on the USB. Note: Only accessible in device mode. Bit 11 USBSUSP: USB suspend The core sets this bit to indicate that a suspend was detected on the USB. The core enters the Suspended state when there is no activity on the data lines for an extended period of time. Note: Only accessible in device mode. Bit 10 ESUSP: Early suspend The core sets this bit to indicate that an Idle state has been detected on the USB for 3 ms. Note: Only accessible in device mode. Bits 9:8 Reserved, must be kept at reset value. Bit 7 GONAKEFF: Global OUT NAK effective Indicates that the Set global OUT NAK bit in the OTG_DCTL register (SGONAK bit in OTG_DCTL), set by the application, has taken effect in the core. This bit can be cleared by writing the Clear global OUT NAK bit in the OTG_DCTL register (CGONAK bit in OTG_DCTL). Note: Only accessible in device mode. Bit 6 GINAKEFF: Global IN non-periodic NAK effective Indicates that the Set global non-periodic IN NAK bit in the OTG_DCTL register (SGINAK bit in OTG_DCTL), set by the application, has taken effect in the core. That is, the core has sampled the Global IN NAK bit set by the application. This bit can be cleared by clearing the Clear global non-periodic IN NAK bit in the OTG_DCTL register (CGINAK bit in OTG_DCTL). This interrupt does not necessarily mean that a NAK handshake is sent out on the USB. The STALL bit takes precedence over the NAK bit. Note: Only accessible in device mode. Bit 5 NPTXFE: Non-periodic Tx FIFO empty This interrupt is asserted when the non-periodic Tx FIFO is either half or completely empty, and there is space for at least one entry to be written to the non-periodic transmit request queue. The half or completely empty status is determined by the non-periodic Tx FIFO empty level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). Note: Accessible in host mode only. 1524/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Bit 4 RXFLVL: Rx FIFO non-empty Indicates that there is at least one packet pending to be read from the Rx FIFO. Note: Accessible in both host and device modes. Bit 3 SOF: Start of frame In host mode, the core sets this bit to indicate that an SOF (FS), or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to this bit to clear the interrupt. In device mode, in the core sets this bit to indicate that an SOF token has been received on the USB. The application can read the OTG_DSTS register to get the current frame number. This interrupt is seen only when the core is operating in FS. Note: Note: This register may return '1' if read immediately after power on reset. If the register bit reads '1' immediately after power on reset it does not indicate that an SOF has been sent (in case of host mode) or SOF has been received (in case of device mode). The read value of this interrupt is valid only after a valid connection between host and device is established. If the bit is set after power on reset the application can clear the bit. Note: Accessible in both host and device modes. Bit 2 OTGINT: OTG interrupt The core sets this bit to indicate an OTG protocol event. The application must read the OTG Interrupt Status (OTG_GOTGINT) register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the OTG_GOTGINT register to clear this bit. Note: Accessible in both host and device modes. Bit 1 MMIS: Mode mismatch interrupt The core sets this bit when the application is trying to access: – A host mode register, when the core is operating in device mode – A device mode register, when the core is operating in host mode The register access is completed on the AHB with an OKAY response, but is ignored by the core internally and does not affect the operation of the core. Note: Accessible in both host and device modes. Bit 0 CMOD: Current mode of operation Indicates the current mode. 0: Device mode 1: Host mode Note: Accessible in both host and device modes. 43.15.7 OTG interrupt mask register (OTG_GINTMSK) Address offset: 0x018 Reset value: 0x0000 0000 This register works with the Core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the Core Interrupt (OTG_GINTSTS) register bit corresponding to that interrupt is still set. 31 30 WUIM SRQIM rw rw 29 28 DISCIN CIDSC T HGM rw rw 27 26 LPMIN PTXFE TM M rw rw 25 24 23 22 21 20 HCIM PRTIM RSTDE TM Res. IPXFR M/IISO OXFR M IISOIX FRM rw r rw rw rw DocID024597 Rev 1 19 18 OEPIN IEPINT T rw 17 16 Res. Res. rw 1525/1680 1635 USB on-the-go full-speed (OTG_FS) 15 14 EOPF M ISOOD RPM rw rw 13 12 11 10 ENUM USBRS USBSU ESUSP DNEM T SPM M rw rw rw RM0351 9 8 Res. Res. rw 7 6 5 4 GONA GINAK NPTXF RXFLV KEFFM EFFM EM LM rw rw rw rw Bit 31 WUIM: Resume/remote wakeup detected interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both host and device modes. Bit 30 SRQIM: Session request/new session detected interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both host and device modes. Bit 29 DISCINT: Disconnect detected interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 28 CIDSCHGM: Connector ID status change mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both host and device modes. Bit 27 LPMINTM: LPM interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both host and device modes. Bit 26 PTXFEM: Periodic Tx FIFO empty mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in host mode. Bit 25 HCIM: Host channels interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in host mode. Bit 24 PRTIM: Host port interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in host mode. Bit 23 RSTDETM: Reset detected interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 22 Reserved, must be kept at reset value for USB OTG FS. 1526/1680 DocID024597 Rev 1 3 SOFM rw 2 1 OTGIN MMISM T rw rw 0 Res. RM0351 USB on-the-go full-speed (OTG_FS) Bit 21 IPXFRM: Incomplete periodic transfer mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in host mode. IISOOXFRM: Incomplete isochronous OUT transfer mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 20 IISOIXFRM: Incomplete isochronous IN transfer mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 19 OEPINT: OUT endpoints interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 18 IEPINT: IN endpoints interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bits 17:16 Reserved, must be kept at reset value. Bit 15 EOPFM: End of periodic frame interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 14 ISOODRPM: Isochronous OUT packet dropped interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 13 ENUMDNEM: Enumeration done mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 12 USBRST: USB reset mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 11 USBSUSPM: USB suspend mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 10 ESUSPM: Early suspend mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. DocID024597 Rev 1 1527/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Bits 9:8 Reserved, must be kept at reset value. Bit 7 GONAKEFFM: Global OUT NAK effective mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 6 GINAKEFFM: Global non-periodic IN NAK effective mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 5 NPTXFEM: Non-periodic Tx FIFO empty mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in Host mode. Bit 4 RXFLVLM: Receive FIFO non-empty mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both device and host modes. Bit 3 SOFM: Start of frame mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both device and host modes. Bit 2 OTGINT: OTG interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both device and host modes. Bit 1 MMISM: Mode mismatch interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both device and host modes. Bit 0 Reserved, must be kept at reset value. 43.15.8 OTG_FS Receive status debug read/OTG status read and pop registers (OTG_GRXSTSR/OTG_GRXSTSP) Address offset for Read: 0x01C Address offset for Pop: 0x020 Reset value: 0x0000 0000 A read to the Receive status debug read register returns the contents of the top of the Receive FIFO. A read to the Receive status read and pop register additionally pops the top data entry out of the Rx FIFO. The receive status contents must be interpreted differently in host and device modes. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x0000 0000. The application must only pop the Receive Status FIFO when the Receive FIFO non-empty bit of the Core interrupt register (RXFLVL bit in OTG_GINTSTS) is asserted. 1528/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Host mode: 31 30 29 28 27 26 25 24 23 22 21 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 DPID r 9 8 7 6 5 20 19 18 PKTSTS r r r r r 16 DPID r r r r r 4 3 2 1 0 BCNT r 17 CHNUM r r r r r r r r r Bits 31:21 Reserved, must be kept at reset value. Bits 20:17 PKTSTS: Packet status Indicates the status of the received packet 0010: IN data packet received 0011: IN transfer completed (triggers an interrupt) 0101: Data toggle error (triggers an interrupt) 0111: Channel halted (triggers an interrupt) Others: Reserved Bits 16:15 DPID: Data PID Indicates the Data PID of the received packet 00: DATA0 10: DATA1 Bits 14:4 BCNT: Byte count Indicates the byte count of the received IN data packet. Bits 3:0 CHNUM: Channel number Indicates the channel number to which the current received packet belongs. DocID024597 Rev 1 1529/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Device mode: 31 30 29 28 27 26 25 Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 DPID 9 24 23 22 21 20 FRMNUM 19 18 PKTSTS r r r r r r 16 DPID r r r r r r r r r 8 7 6 5 4 3 2 1 0 BCNT r 17 EPNUM r r r r r r r r r Bits 31:25 Reserved, must be kept at reset value. Bits 24:21 FRMNUM: Frame number This is the least significant 4 bits of the frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported. Bits 20:17 PKTSTS: Packet status Indicates the status of the received packet 0001: Global OUT NAK (triggers an interrupt) 0010: OUT data packet received 0011: OUT transfer completed (triggers an interrupt) 0100: SETUP transaction completed (triggers an interrupt) 0110: SETUP data packet received Others: Reserved Bits 16:15 DPID: Data PID Indicates the Data PID of the received OUT data packet 00: DATA0 10: DATA1 Bits 14:4 BCNT: Byte count Indicates the byte count of the received data packet. Bits 3:0 EPNUM: Endpoint number Indicates the endpoint number to which the current received packet belongs. 43.15.9 OTG Receive FIFO size register (OTG_GRXFSIZ) Address offset: 0x024 Reset value: 0x0000 0200 The application can program the RAM size that must be allocated to the Rx FIFO. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw RXFD rw rw 1530/1680 rw rw rw rw rw rw DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 RXFD: Rx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 Programmed values must respect the available FIFO memory allocation and must not exceed the power-on value. 43.15.10 OTG Host non-periodic transmit FIFO size register (OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0) Address offset: 0x028 Reset value: 0x0200 0200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NPTXFD/TX0FD rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw NPTXFSA/TX0FSA rw rw rw rw rw rw rw rw rw Host mode Bits 31:16 NPTXFD: Non-periodic Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 Programmed values must respect the available FIFO memory allocation and must not exceed the power-on value. Bits 15:0 NPTXFSA: Non-periodic transmit RAM start address This field configures the memory start address for non-periodic transmit FIFO RAM. Device mode Bits 31:16 TX0FD: Endpoint 0 Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 Programmed values must respect the available FIFO memory allocation and must not exceed the power-on value. Bits 15:0 TX0FSA: Endpoint 0 transmit RAM start address This field configures the memory start address for the endpoint 0 transmit FIFO RAM. DocID024597 Rev 1 1531/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 43.15.11 OTG non-periodic transmit FIFO/queue status register (OTG_HNPTXSTS) Address offset: 0x02C Reset value: 0x0008 0200 Note: In Device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue. 31 30 29 28 Res. 15 27 26 25 24 23 22 21 NPTXQTOP 20 19 18 17 16 NPTQXSAV r r r r r r r r r r r r r r r 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r NPTXFSAV r r r r r r r r r Bit 31 Reserved, must be kept at reset value. Bits 30:24 NPTXQTOP: Top of the non-periodic transmit request queue Entry in the non-periodic Tx request queue that is currently being processed by the MAC. Bits 30:27: Channel/endpoint number Bits 26:25: 00: IN/OUT token 01: Zero-length transmit packet (device IN/host OUT) 11: Channel halt command Bit 24: Terminate (last entry for selected channel/endpoint) Bits 23:16 NPTQXSAV: Non-periodic transmit request queue space available Indicates the amount of free space available in the non-periodic transmit request queue. This queue holds both IN and OUT requests. 0: Non-periodic transmit request queue is full 1: 1 location available 2: locations available n: n locations available (0 ≤ n ≤ 8) Others: Reserved Bits 15:0 NPTXFSAV: Non-periodic Tx FIFO space available Indicates the amount of free space available in the non-periodic Tx FIFO. Values are in terms of 32-bit words. 0: Non-periodic Tx FIFO is full 1: 1 word available 2: 2 words available n: n words available (where 0 ≤ n ≤ 512) Others: Reserved 1532/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) 43.15.12 OTG general core configuration register (OTG_GCCFG) Address offset: 0x038 Reset value: 0x0000 0000 31 Res. 15 Res. 30 Res. 14 Res. 29 Res. 13 Res. 28 Res. 12 Res. 27 Res. 11 Res. 26 Res. 10 Res. 25 Res. 9 24 Res. 23 Res. 8 Res. Res. 22 Res. 7 Res. 6 Res. 21 20 19 18 17 16 BCDEN PWR DWN VBDEN SDEN PDEN DCD EN rw rw rw rw rw rw 5 4 3 2 1 0 Res. PS2 DET SDET PDET DCDET rw rw rw rw Res. Bits 31:22 Reserved, must be kept at reset value. Bit 21 VBDEN: USB VBUS detection enable Enables VBUS sensing comparators to detect VBUS valid levels on the VBUS PAD for USB host and device operation. If HNP and/or SRP support is enabled, VBUS comparators are automatically enabled independently of VBDEN value. 0 = VBUS Detection Disabled 1 = VBUS Detection Enabled Bit 20 SDEN: Secondary detection (SD) mode enable This bit is set by the software to put the BCD into SD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly Bit 19 PDEN: Primary detection (PD) mode enable This bit is set by the software to put the BCD into PD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. Bit 18 DCDEN: Data contact detection (DCD) mode enable This bit is set by the software to put the BCD into DCD mode. Only one detection mode (DCD, PD, SD or OFF) should be selected to work correctly. Bit 17 BCDEN: Battery charging detector (BCD) enable This bit is set by the software to enable the BCD support within the USB device. When enabled, the USB PHY is fully controlled by BCD and cannot be used for normal communication. Once the BCD discovery is finished, the BCD should be placed in OFF mode by clearing this bit to ‘0’ in order to allow the normal USB operation. Bit 16 PWRDWN: Power down control Used to activate the transceiver in transmission/reception. When reset, the transceiver is kept in power-down. When set, the BCD function must be off (BCDEN=0). 0 = USB FS transceiver disabled 1 = USB FS transceiver enabled Bits 15:4 Reserved, must be kept at reset value. DocID024597 Rev 1 1533/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Bit 3 PS2DET: DM pull-up detection status This bit is active only during PD and gives the result of comparison between DM voltage level and VLGC threshold. In normal situation, the DM level should be below this threshold. If it is above, it means that the DM is externally pulled high. This can be caused by connection to a PS2 port (which pulls-up both DP and DM lines) or to some proprietary charger not following the BCD specification. 0: Normal port detected (connected to SDP, CDP or DCP) 1: PS2 port or proprietary charger detected Bit 2 SDET: Secondary detection (SD) status This bit gives the result of SD. 0: CDP detected 1: DCP detected Bit 1 PDET: Primary detection (PD) status This bit gives the result of PD. 0: no BCD support detected (connected to SDP or proprietary device). 1: BCD support detected (connected to CDP or DCP). Bit 0 DCDET: Data contact detection (DCD) status This bit gives the result of DCD. 0: data lines contact not detected 1: data lines contact detected 43.15.13 OTG core ID register (OTG_CID) Address offset: 0x03C Reset value:0x0000 2000 This is a read only register containing the Product ID. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PRODUCT_ID rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PRODUCT_ID rw rw rw rw rw rw rw rw rw Bits 31:0 PRODUCT_ID: Product ID field Application-programmable ID field. 1534/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) 43.15.14 OTG core LPM configuration register (OTG_GLPMCFG) Address offset: 0x54 Reset value: 0x0000 0000 31 Res. 15 SLP STS r 30 Res. 14 29 28 Res. EN BESL 13 LPMRSP r r 27 26 25 24 LPMRCNTSTS rw r r r rs 12 11 10 9 8 L1DS EN rw BESLTHRS rw rw 23 SND LPM rw rw 22 21 20 19 LPMRCNT rw 18 rw rw rw rw 5 4 3 2 7 6 REM WAKE rw rw/r BESL rw/r rw/r rw/r rw/r 16 L1RSM OK LPMCHIDX rw L1SS EN 17 rw r 1 0 LPM ACK LPM EN rw rw Bits 31:29 Reserved, must be kept at reset value. Bit 28 ENBESL: Enable best effort service latency This bit enables the BESL feature as defined in the LPM errata: 0:The core works as described in the following document: USB 2.0 Link Power Management Addendum Engineering Change Notice to the USB 2.0 specification, July 16, 2007 1:The core works as described in the LPM Errata: Errata for USB 2.0 ECN: Link Power Management (LPM) - 7/2007 Note: Only the updated behavior (described in LPM Errata) is considered in this document and so the ENBESL bit should be set to '1' by application SW. Bits 27:25 LPMRCNTSTS: LPM retry count status Number of LPM host retries still remaining to be transmitted for the current LPM sequence. Note: Accessible only in host mode. Bit 24 SNDLPM: Send LPM transaction When the application software sets this bit, an LPM transaction containing two tokens, EXT and LPM is sent. The hardware clears this bit once a valid response (STALL, NYET, or ACK) is received from the device or the core has finished transmitting the programmed number of LPM retries. Note: This bit must be set only when the host is connected to a local port. Note: Accessible only in host mode. Bits 23:21 LPMRCNT: LPM retry count When the device gives an ERROR response, this is the number of additional LPM retries that the host performs until a valid device response (STALL, NYET, or ACK) is received. Note: Accessible only in host mode. Bits 20:17 LPMCHIDX: LPM Channel Index The channel number on which the LPM transaction has to be applied while sending an LPM transaction to the local device. Based on the LPM channel index, the core automatically inserts the device address and endpoint number programmed in the corresponding channel into the LPM transaction. Note: Accessible only in host mode. DocID024597 Rev 1 1535/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Bit 16 L1RSMOK: Sleep State Resume OK Indicates that the device or host can start resume from Sleep state. This bit is valid in LPM sleep (L1) state. It is set in sleep mode after a delay of 50 μs (TL1Residency). This bit is reset when SLPSTS is 0. 1: The application or host can start resume from Sleep state 0: The application or host cannot start resume from Sleep state Bit 15 SLPSTS: Port sleep status Device mode: This bit is set as long as a Sleep condition is present on the USB bus. The core enters the Sleep state when an ACK response is sent to an LPM transaction and the TL1TokenRetry timer has expired. To stop the PHY clock, the application must set the STPPCLK bit in OTG_PCGCCTL, which asserts the PHY Suspend input signal. The application must rely on SLPSTS and not ACK in LPMRSP to confirm transition into sleep. The core comes out of sleep: – When there is any activity on the USB linestate – When the application writes to the RWUSIG bit in OTG_DCTL or when the application resets or soft-disconnects the device. Host mode: The host transitions to Sleep (L1) state as a side-effect of a successful LPM transaction by the core to the local port with ACK response from the device. The read value of this bit reflects the current Sleep status of the port. The core clears this bit after: – The core detects a remote L1 Wakeup signal, – The application sets the PRST bit or the PRES bit in the OTG_HPRT register, or – The application sets the L1Resume/ Remote Wakeup Detected Interrupt bit or Disconnect Detected Interrupt bit in the Core Interrupt register (WKUPINT or DISCINT bit in OTG_GINTSTS, respectively). 0: Core not in L1 1: Core in L1 Bits 14:13 LPMRST: LPM response Device mode: The response of the core to LPM transaction received is reflected in these two bits. Host mode: Handshake response received from local device for LPM transaction 11: ACK 10: NYET 01: STALL 00: ERROR (No handshake response) Bit 12 L1DSEN: L1 deep sleep enable Enables suspending the PHY in L1 Sleep mode. For maximum power saving during L1 Sleep mode, this bit should be set to '1' by application SW in all the cases. 1536/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Bits11:8 BESLTHRS: BESL threshold Device mode: The core puts the PHY into deep low power mode in L1 when BESL value is greater than or equal to the value defined in this field BESL_Thres[3:0]. Host mode: The core puts the PHY into deep low power mode in L1. BESLTHRS[3:0] specifies the time for which resume signaling is to be reflected by host (TL1HubDrvResume2) on the USB bus when it detects device initiated resume. BESLTHRS must not be programmed with a value greater than 1100b in host mode, because this exceeds maximum TL1HubDrvResume2. Thres[3:0]Host mode resume signaling time (μs) 0000:75 0001:100 0010:150 0011:250 0100:350 0101:450 0110:950 All other values:reserved Bit 7 L1SSEN: L1 Shallow Sleep enable Enables suspending the PHY in L1 Sleep mode. For maximum power saving during L1 Sleep mode, this bit should be set to '1' by application SW in all the cases. Bit 6 REMWAKE: bRemoteWake value Host mode: The value of remote wake up to be sent in the wIndex field of LPM transaction. Device mode (read-only): This field is updated with the received LPM token bRemoteWake bmAttribute when an ACK, NYET, or STALL response is sent to an LPM transaction. DocID024597 Rev 1 1537/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Bits 5:2 BESL: Best effort service latency Host mode: The value of BESL to be sent in an LPM transaction. This value is also used to initiate resume for a duration TL1HubDrvResume1 for host initiated resume. Device mode (read-only): This field is updated with the received LPM token BESL bmAttribute when an ACK, NYET, or STALL response is sent to an LPM transaction. BESL[3:0]TBESL (μs) 0000:125 0001:150 0010:200 0011:300 0100:400 0101:500 0110:1000 0111:2000 1000:3000 1001:4000 1010:5000 1011:6000 1100:7000 1101:8000 1110:9000 1111:10000 Bit 1 LPMACK: LPM token acknowledge enable Handshake response to LPM token pre-programmed by device application software. 1:ACK Even though ACK is pre-programmed, the core Device responds with ACK only on successful LPM transaction. The LPM transaction is successful if: – No PID/CRC5 Errors in either EXT token or LPM token (else ERROR) – Valid bLinkState = 0001B (L1) received in LPM transaction (else STALL) – No data pending in transmit queue (else NYET). 0:NYET The pre-programmed software bit is over-ridden for response to LPM token when: – The received bLinkState is not L1 (STALL response), or – An error is detected in either of the LPM token packets because of corruption (ERROR response). Note: Accessible only in device mode. Bit 0 LPMEN: LPM support enable The application uses this bit to control the OTG_FS core LPM capabilities. If the core operates as a non-LPM-capable host, it cannot request the connected device or hub to activate LPM mode. If the core operates as a non-LPM-capable device, it cannot respond to any LPM transactions. 0: LPM capability is not enabled 1: LPM capability is enabled 1538/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) 43.15.15 OTG power down register (OTG_GPWRDN) Address offset: 0x058 Reset value: 0x0000 0010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. ADPIF Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADPM EN rc_w1 rw Bits 31:24 Reserved, must be kept at reset value. Bit 23 ADPIF: ADP interrupt flag This bit is set whenever there is an ADP event Bits 22:1 Reserved, must be kept at reset value. Bit 0 ADPMEN: ADP module enable This bit enables or disables the ADP logic. 0: Disable ADP module 1: Enable ADP module 43.15.16 OTG ADP timer, control and status register (OTG_GADPCTL) Address offset: 0x060 Reset value: 0x0000 0000 The OTG_GADPCTL register must be accessed as follows: 31 30 • In order to read from the OTG_GADPCTL register, program AR=0b01 and keep polling till AR=0b00. The core updates the other fields of this register and makes AR=0b00. Read values of this register are valid only when AR=0b00. • In order to write to the OTG_GADPCTL register, program AR=0b10 along with the values for the other fields and keep polling till AR=0b00. When AR becomes 0b00, it means that the programmed value has taken effect inside the core. 29 Res. Res. Res. 15 14 13 28 27 26 ADP TOIM AR 25 24 ADP ADP SNSIM PRBIM rw rw rw rw rw 12 11 10 9 8 23 22 ADP TOIF ADP SNSIF rc_w1 rc_w1 rc_w1 7 6 RTIM r r r r r 21 20 19 18 17 16 ADP RST ENA SNS ENA PRB RTIM rw rs rw rw r 4 3 2 1 0 ADP ADPEN PRBIF 5 PRBPER r r r r DocID024597 Rev 1 r rw rw PRBDELTA PRBDSCHG rw rw rw rw 1539/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Bits 31:29 Reserved, must be kept at reset value. Bits 28:27 AR: Access request This bitfield define the requested access mode to the OTG_GADPCTL register: 00 Read / Write valid (updated by the core) 01 Read request 10 Write request 11 Reserved Bit 26 ADPTOIM: ADP timeout interrupt mask When this bit is set, it unmasks the interrupt from ADPTOIF. Bit 25 ADPSNSIM: ADP sense interrupt mask When this bit is set, it unmasks the interrupt from ADPSNSIF. Bit 24 ADPPRBIM: ADP probe interrupt mask When this bit is set, it unmasks the interrupt from ADPPRBIF. Bit 23 ADPTOIF: ADP timeout interrupt flag This bit is relevant only for an ADP probe. When this bit is set, it means that the ramp time has completed (RTIM has reached its terminal value of 0x7FF). This is a debug feature that allows the application to read the ramp time after each cycle. Bit 22: ADPSNSIF: ADP sense interrupt flag When this bit is set, it means that the VBUS voltage is greater than VADPSNS value or that VADPSNS is reached. Bit 21 ADPPRBIF: ADP probe interrupt flag When this bit is set, it means that the VBUS voltage is greater than VADPPRB or that VADPPRB is reached. Bit 20 ADPEN: ADP enable When set, the core performs either ADP probing or sensing based on ENAPRB or ENASNS. Bit 19 ADPRST: ADP reset When set, ADP controller is reset. This bit is auto-cleared after the reset procedure is complete in the ADP controller. Bit 18 ENASNS: Enable sense When programmed to 1, the core performs a sense operation. Bit 17 ENAPRB: Enable probe When programmed to 1, the core performs a probe operation. Bits 16:6 RTIM: Ramp time These bits capture the latest time it took for VBUS to ramp from VADPSINK to VADPPRB. The bits are defined in units of 32 kHz clock cycles as follow: 000: 1 cycle 001: 2 cycles 002: 3 cycles ... 7FF: 2048 cycles A time of 1024 cycles at 32 kHz corresponds to a time of 32 ms. 1540/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Bits 5:4 PRBPER: Probe period These bits sets the TADPPRD as follow: 00: 0.625 to 0.925 sec (typical 0.775 sec) 01: 1.25 to 1.85 sec (typical 1.55 sec) 10: 1.9 to 2.6 sec (typical 2.275 sec) 11: Reserved Bits 3:2 PRBDELTA: Probe delta These bits set the resolution for RTIM value. The bits are defined in units of 32 kHz clock cycles as follow: 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles For example if this value is chosen to be 01, it means that RTIM increments for every two 32 kHz clock cycles. Bits 1:0 PRBDSCHG: Probe discharge These bits set the times for TADP_DSCHG. These bits are defined as follow: 00: 4 ms 01: 8 ms 10: 16 ms 11: 32 ms 43.15.17 OTG Host periodic transmit FIFO size register (OTG_HPTXFSIZ) Address offset: 0x100 Reset value: 0x0200 0400 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PTXFSIZ rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw PTXSA rw rw rw rw rw rw rw rw Bits 31:16 PTXFD: Host periodic Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 Bits 15:0 PTXSA: Host periodic Tx FIFO start address This field configures the memory start address for periodic transmit FIFO RAM. DocID024597 Rev 1 1541/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 43.15.18 OTG device IN endpoint transmit FIFO size register (OTG_DIEPTXFx) (x = 1..5 , where x is the FIFO_number) Address offset: 0x104 + (FIFO_number – 1) × 0x04 Reset values: FIFO_number = 5 : 0x0200 0200 + (5 31 30 29 28 27 26 25 24 * 0x200) 23 22 21 20 19 18 17 16 INEPTXFD rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw INEPTXSA rw rw rw rw rw rw rw rw rw Bits 31:16 INEPTXFD: IN endpoint Tx FIFO depth This value is in terms of 32-bit words. Minimum value is 16 Bits 15:0 INEPTXSA: IN endpoint FIFOx transmit RAM start address This field contains the memory start address for IN endpoint transmit FIFOx. The address must be aligned with a 32-bit memory location. 43.15.19 Host-mode registers Bit values in the register descriptions are expressed in binary unless otherwise specified. Host-mode registers affect the operation of the core in the host mode. Host mode registers must not be accessed in device mode, as the results are undefined. Host mode registers can be categorized as follows: 43.15.20 OTG Host configuration register (OTG_HCFG) Address offset: 0x400 Reset value: 0x0000 0000 This register configures the core after power-on. Do not make changes to this register after initializing the host. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FSLSS r 1542/1680 DocID024597 Rev 1 FSLSPCS rw rw RM0351 USB on-the-go full-speed (OTG_FS) Bits 31:3 Reserved, must be kept at reset value. Bit 2 FSLSS: FS- and LS-only support The application uses this bit to control the core’s enumeration speed. Using this bit, the application can make the core enumerate as an FS host, even if the connected device supports HS traffic. Do not make changes to this field after initial programming. 1: FS/LS-only, even if the connected device can support HS (read-only) Bits 1:0 FSLSPCS: FS/LS PHY clock select When the core is in FS host mode 01: PHY clock is running at 48 MHz Others: Reserved When the core is in LS host mode 00: Reserved 01: Select 48 MHz PHY clock frequency 10: Select 6 MHz PHY clock frequency 11: Reserved Note: The FSLSPCS must be set on a connection event according to the speed of the connected device (after changing this bit, a software reset must be performed). 43.15.21 OTG Host frame interval register (OTG_HFIR) Address offset: 0x404 Reset value: 0x0000 EA60 This register stores the frame interval information for the current speed to which the OTG_FS controller has enumerated. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RLD CTRL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw FRIVL rw rw rw rw rw rw rw rw DocID024597 Rev 1 1543/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Bits 31:17 Reserved, must be kept at reset value. Bit 16 RLDCTRL: Reload control This bit allows dynamic reloading of the HFIR register during run time. 0: The HFIR cannot be reloaded dynamically 1: The HFIR can be dynamically reloaded during runtime. This bit needs to be programmed during initial configuration and its value must not be changed during runtime. Bits 15:0 FRIVL: Frame interval for USB OTG FS The value that the application programs to this field, specifies the interval between two consecutive SOFs (FS) or Keep-Alive tokens (LS). This field contains the number of PHY clocks that constitute the required frame interval. The application can write a value to this register only after the Port enable bit of the host port control and status register (PENA bit in OTG_HPRT) has been set. If no value is programmed, the core calculates the value based on the PHY clock specified in the FS/LS PHY Clock Select field of the host configuration register (FSLSPCS in OTG_HCFG). Do not change the value of this field after the initial configuration, unless the RLDCTRL bit is set. In such case, the FRIVL is reloaded with each SOF event. 43.15.22 OTG Host frame number/frame time remaining register (OTG_HFNUM) Address offset: 0x408 Reset value: 0x0000 3FFF This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FTREM r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r FRNUM r r r r r r r r r Bits 31:16 FTREM: Frame time remaining Indicates the amount of time remaining in the current frame, in terms of PHY clocks. This field decrements on each PHY clock. When it reaches zero, this field is reloaded with the value in the Frame interval register and a new SOF is transmitted on the USB. Bits 15:0 FRNUM: Frame number This field increments when a new SOF is transmitted on the USB, and is cleared to 0 when it reaches 0x3FFF. 1544/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) 43.15.23 OTG_Host periodic transmit FIFO/queue status register (OTG_HPTXSTS) Address offset: 0x410 Reset value: 0x0008 0100 This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue. 31 30 29 28 27 26 25 24 23 22 21 PTXQTOP 20 19 18 17 16 PTXQSAV r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r PTXFSAVL r r r r r r r r r Bits 31:24 PTXQTOP: Top of the periodic transmit request queue This indicates the entry in the periodic Tx request queue that is currently being processed by the MAC. This register is used for debugging. Bit 31: Odd/Even frame 0: send in even frame 1: send in odd frame Bits 30:27: Channel/endpoint number Bits 26:25: Type 00: IN/OUT 01: Zero-length packet 11: Disable channel command Bit 24: Terminate (last entry for the selected channel/endpoint) Bits 23:16 PTXQSAV: Periodic transmit request queue space available Indicates the number of free locations available to be written in the periodic transmit request queue. This queue holds both IN and OUT requests. 00: Periodic transmit request queue is full 01: 1 location available 10: 2 locations available bxn: n locations available (0 ≤ n ≤ 8) Others: Reserved Bits 15:0 PTXFSAVL: Periodic transmit data FIFO space available Indicates the number of free locations available to be written to in the periodic Tx FIFO. Values are in terms of 32-bit words 0000: Periodic Tx FIFO is full 0001: 1 word available 0010: 2 words available bxn: n words available (where 0 ≤ n ≤ PTXFD) Others: Reserved DocID024597 Rev 1 1545/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 43.15.24 OTG Host all channels interrupt register (OTG_HAINT) Address offset: 0x414 Reset value: 0x0000 000 When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the Core interrupt register (HCINT bit in OTG_GINTSTS). This is shown in Figure 496. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r HAINT r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 HAINT: Channel interrupts One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 43.15.25 OTG Host all channels interrupt mask register (OTG_HAINTMSK) Address offset: 0x418 Reset value: 0x0000 0000 The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw HAINTM rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 HAINTM: Channel interrupt mask 0: Masked interrupt 1: Unmasked interrupt One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 1546/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) 43.15.26 OTG Host port control and status register (OTG_HPRT) Address offset: 0x440 Reset value: 0x0000 0000 This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure 496. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in OTG_GINTSTS). On a Port Interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. PRST PSUSP PRES POC CHNG POCA PEN CHNG PENA rw rs rw rc_w1 r rc_w1 rc_w0 PTCTL rw rw PPWR rw rw PLSTS r r 18 17 PSPD 16 PTCTL PCDET PCSTS rc_w1 r Bits 31:19 Reserved, must be kept at reset value. Bits 18:17 PSPD: Port speed Indicates the speed of the device attached to this port. 01: Full speed 10: Low speed 11: Reserved Bits 16:13 PTCTL: Port test control The application writes a nonzero value to this field to put the port into a Test mode, and the corresponding pattern is signaled on the port. 0000: Test mode disabled 0001: Test_J mode 0010: Test_K mode 0011: Test_SE0_NAK mode 0100: Test_Packet mode 0101: Test_Force_Enable Others: Reserved Bit 12 PPWR: Port power The application uses this field to control power to this port, and the core clears this bit on an overcurrent condition. 0: Power off 1: Power on Bits 11:10 PLSTS: Port line status Indicates the current logic level USB data lines Bit 10: Logic level of OTG_FS_DP Bit 11: Logic level of OTG_FS_DM Bit 9 Reserved, must be kept at reset value. DocID024597 Rev 1 1547/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Bit 8 PRST: Port reset When the application sets this bit, a reset sequence is started on this port. The application must time the reset period and clear this bit after the reset sequence is complete. 0: Port not in reset 1: Port in reset The application must leave this bit set for a minimum duration of at least 10 ms to start a reset on the port. The application can leave it set for another 10 ms in addition to the required minimum duration, before clearing the bit, even though there is no maximum limit set by the USB standard. High speed: 50 ms Full speed/Low speed: 10 ms Bit 7 PSUSP: Port suspend The application sets this bit to put this port in Suspend mode. The core only stops sending SOFs when this is set. To stop the PHY clock, the application must set the Port clock stop bit, which asserts the suspend input pin of the PHY. The read value of this bit reflects the current suspend status of the port. This bit is cleared by the core after a remote wakeup signal is detected or the application sets the Port reset bit or Port resume bit in this register or the Resume/remote wakeup detected interrupt bit or Disconnect detected interrupt bit in the Core interrupt register (WKUINT or DISCINT in OTG_GINTSTS, respectively). 0: Port not in Suspend mode 1: Port in Suspend mode Bit 6 PRES: Port resume The application sets this bit to drive resume signaling on the port. The core continues to drive the resume signal until the application clears this bit. If the core detects a USB remote wakeup sequence, as indicated by the Port resume/remote wakeup detected interrupt bit of the Core interrupt register (WKUINT bit in OTG_GINTSTS), the core starts driving resume signaling without application intervention and clears this bit when it detects a disconnect condition. The read value of this bit indicates whether the core is currently driving resume signaling. 0: No resume driven 1: Resume driven When LPM is enabled and the core is in L1 state, the behavior of this bit is as follow: 1. The application sets this bit to drive resume signaling on the port. 2. The core continues to drive the resume signal until a pre-determined time specified in BESLTHRS[3:0] field of OTG_GLPMCFG register. 3. If the core detects a USB remote wakeup sequence, as indicated by the Port L1Resume/Remote L1Wakeup Detected Interrupt bit of the core Interrupt register (WKUPINT in OTG_GINTSTS), the core starts driving resume signaling without application intervention and clears this bit at the end of resume.This bit can be set or cleared by both the core and the application. This bit is cleared by the core even if there is no device connected to the host. Bit 5 POCCHNG: Port overcurrent change The core sets this bit when the status of the Port overcurrent active bit (bit 4) in this register changes. Bit 4 POCA: Port overcurrent active Indicates the overcurrent condition of the port. 0: No overcurrent condition 1: Overcurrent condition Bit 3 PENCHNG: Port enable/disable change The core sets this bit when the status of the Port enable bit 2 in this register changes. 1548/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Bit 2 PENA: Port enable A port is enabled only by the core after a reset sequence, and is disabled by an overcurrent condition, a disconnect condition, or by the application clearing this bit. The application cannot set this bit by a register write. It can only clear it to disable the port. This bit does not trigger any interrupt to the application. 0: Port disabled 1: Port enabled Bit 1 PCDET: Port connect detected The core sets this bit when a device connection is detected to trigger an interrupt to the application using the host port interrupt bit in the Core interrupt register (HPRTINT bit in OTG_GINTSTS). The application must write a 1 to this bit to clear the interrupt. Bit 0 PCSTS: Port connect status 0: No device is attached to the port 1: A device is attached to the port 43.15.27 OTG Host channel-x characteristics register (OTG_HCCHARx) (x = 0..11, where x = Channel_number) Address offset: 0x500 + (Channel_number × 0x20) Reset value: 0x0000 0000 31 30 CHENA CHDIS 29 28 27 26 ODD FRM 25 24 23 22 21 DAD 20 19 MCNT 18 EPTYP 17 16 LSDEV Res. rs rs rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw EPDIR rw EPNUM rw rw rw MPSIZ rw rw rw rw rw rw rw Bit 31 CHENA: Channel enable This field is set by the application and cleared by the OTG host. 0: Channel disabled 1: Channel enabled Bit 30 CHDIS: Channel disable The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. The application must wait for the Channel disabled interrupt before treating the channel as disabled. Bit 29 ODDFRM: Odd frame This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 0: Even frame 1: Odd frame Bits 28:22 DAD: Device address This field selects the specific device serving as the data source or sink. DocID024597 Rev 1 1549/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Bits 21:20 MCNT: Multicount This field indicates to the host the number of transactions that must be executed per frame for this periodic endpoint. For non-periodic transfers, this field is not used 00: Reserved. This field yields undefined results 01: 1 transaction 10: 2 transactions per frame to be issued for this endpoint 11: 3 transactions per frame to be issued for this endpoint Note: This field must be set to at least 01. Bits 19:18 EPTYP: Endpoint type Indicates the transfer type selected. 00: Control 01: Isochronous 10: Bulk 11: Interrupt Bit 17 LSDEV: Low-speed device This field is set by the application to indicate that this channel is communicating to a lowspeed device. Bit 16 Reserved, must be kept at reset value. Bit 15 EPDIR: Endpoint direction Indicates whether the transaction is IN or OUT. 0: OUT 1: IN Bits 14:11 EPNUM: Endpoint number Indicates the endpoint number on the device serving as the data source or sink. Bits 10:0 MPSIZ: Maximum packet size Indicates the maximum packet size of the associated endpoint. 1550/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) 43.15.28 OTG Host channel-x interrupt register (OTG_HCINTx) (x = 0..11, where x = Channel_number) Address offset: 0x508 + (Channel_number × 0x20) Reset value: 0x0000 0000 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure 496. The application must read this register when the host channels interrupt bit in the Core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. DTERR FRM OR Res. ACK NAK STALL Res. CHH XFRC rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 BBERR TXERR rc_w1 rc_w1 Bits 31:11 Reserved, must be kept at reset value. Bit 10 DTERR: Data toggle error Bit 9 FRMOR: Frame overrun Bit 8 BBERR: Babble error Bit 7 TXERR: Transaction error Indicates one of the following errors occurred on the USB. CRC check failure Timeout Bit stuff error False EOP Bit 6 Reserved, must be kept at reset value for USB OTG FS. Bit 5 ACK: ACK response received/transmitted interrupt Bit 4 NAK: NAK response received interrupt Bit 3 STALL: STALL response received interrupt Bit 2 Reserved, must be kept at reset value for USB OTG FS. Bit 1 CHH: Channel halted Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. Bit 0 XFRC: Transfer completed Transfer completed normally without any errors. DocID024597 Rev 1 1551/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 43.15.29 OTG Host channel-x interrupt mask register (OTG_HCINTMSKx) (x = 0..11, where x = Channel_number) Address offset: 0x50C + (Channel_number × 0x20) Reset value: 0x0000 0000 This register reflects the mask for each channel status described in the previous section. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. DTERR M FRM ORM Res. ACKM NAKM STALL M Res. CHHM XFRC M rw rw rw rw rw rw rw BBERR TXERR M M rw rw Bits 31:11 Reserved, must be kept at reset value. Bit 10 DTERRM: Data toggle error mask 0: Masked interrupt 1: Unmasked interrupt Bit 9 FRMORM: Frame overrun mask 0: Masked interrupt 1: Unmasked interrupt Bit 8 BBERRM: Babble error mask 0: Masked interrupt 1: Unmasked interrupt Bit 7 TXERRM: Transaction error mask 0: Masked interrupt 1: Unmasked interrupt Bit 6 Reserved, must be kept at reset value for USB OTG FS. Bit 5 ACKM: ACK response received/transmitted interrupt mask 0: Masked interrupt 1: Unmasked interrupt Bit 4 NAKM: NAK response received interrupt mask 0: Masked interrupt 1: Unmasked interrupt Bit 3 STALLM: STALL response received interrupt mask 0: Masked interrupt 1: Unmasked interrupt 1552/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Bit 2 Reserved, must be kept at reset value for USB OTG FS Bit 1 CHHM: Channel halted mask 0: Masked interrupt 1: Unmasked interrupt Bit 0 XFRCM: Transfer completed mask 0: Masked interrupt 1: Unmasked interrupt 43.15.30 OTG Host channel-x transfer size register (OTG_HCTSIZx) (x = 0..11, where x = Channel_number) Address offset: 0x510 + (Channel_number × 0x20) Reset value: 0x0000 0000 31 30 Res. 15 29 28 27 26 25 DPID 24 23 22 21 20 19 18 PKTCNT 17 16 XFRSIZ rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw XFRSIZ rw rw rw rw rw rw rw rw rw Bit 31 Reserved, must be kept at reset value. Bits 30:29 DPID: Data PID The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer. 00: DATA0 10: DATA1 11: SETUP (control) / reserved (non-control) Bits 28:19 PKTCNT: Packet count This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN). The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion. Bits 18:0 XFRSIZ: Transfer size For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic). DocID024597 Rev 1 1553/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 43.15.31 Device-mode registers These registers must be programmed every time the core changes to device mode. 43.15.32 OTG device configuration register (OTG_DCFG) Address offset: 0x800 Reset value: 0x0220 0000 This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. NZLSO HSK ERRAT IM Res. rw Res. PFIVL rw DAD rw rw rw rw rw rw rw rw rw DSPD rw rw Bits 31:16 Reserved, must be kept at reset value for USB OTG FS Bit 15 ERRATIM: Erratic error interrupt mask 1: Mask early suspend interrupt on erratic error 0: Early suspend interrupt is generated on erratic error Bits 14:13 Reserved, must be kept at reset value. Bits 12:11 PFIVL: Periodic frame interval Indicates the time within a frame at which the application must be notified using the end of periodic frame interrupt. This can be used to determine if all the isochronous traffic for that frame is complete. 00: 80% of the frame interval 01: 85% of the frame interval 10: 90% of the frame interval 11: 95% of the frame interval Bits 10:4 DAD: Device address The application must program this field after every SetAddress control command. Bit 3 Reserved, must be kept at reset value. Bit 2 NZLSOHSK: Non-zero-length status OUT handshake The application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during the OUT transaction of a control transfer’s Status stage. 1:Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application. 0:Send the received OUT packet to the application (zero-length or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device endpoint control register. 1554/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Bits 1:0 DSPD: Device speed Indicates the speed at which the application requires the core to enumerate, or the maximum speed the application can support. However, the actual bus speed is determined only after the chirp sequence is completed, and is based on the speed of the USB host to which the core is connected. 00: Reserved 01: Reserved 10: Reserved 11: Full speed (USB 1.1 transceiver clock is 48 MHz) 43.15.33 OTG device control register (OTG_DCTL) Address offset: 0x804 Reset value: 0x0000 0002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DS BESL RJCT Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. PO PRG DNE CGO NAK SGO NAK CGI NAK SGI NAK GON STS GIN STS SDIS RWU SIG rw w w w w r r rw rw rw Res. Res. Res. TCTL rw rw rw Bits 31:19 Reserved, must be kept at reset value. Bit 18 DSBESLRJCT: Deep sleep BESL reject Core rejects LPM request with BESL value greater than BESL threshold programmed. NYET response is sent for LPM tokens with BESL value greater than BESL threshold. By default, the deep sleep BESL reject feature is disabled. Bits 17:12 Reserved, must be kept at reset value. Bit 11 POPRGDNE: Power-on programming done The application uses this bit to indicate that register programming is completed after a wakeup from power down mode. Bit 10 CGONAK: Clear global OUT NAK A write to this field clears the Global OUT NAK. Bit 9 SGONAK: Set global OUT NAK A write to this field sets the Global OUT NAK. The application uses this bit to send a NAK handshake on all OUT endpoints. The application must set the this bit only after making sure that the Global OUT NAK effective bit in the Core interrupt register (GONAKEFF bit in OTG_GINTSTS) is cleared. Bit 8 CGINAK: Clear global IN NAK A write to this field clears the Global IN NAK. Bit 7 SGINAK: Set global IN NAK A write to this field sets the Global non-periodic IN NAK.The application uses this bit to send a NAK handshake on all non-periodic IN endpoints. The application must set this bit only after making sure that the Global IN NAK effective bit in the Core interrupt register (GINAKEFF bit in OTG_GINTSTS) is cleared. DocID024597 Rev 1 1555/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Bits 6:4 TCTL: Test control 000: Test mode disabled 001: Test_J mode 010: Test_K mode 011: Test_SE0_NAK mode 100: Test_Packet mode 101: Test_Force_Enable Others: Reserved Bit 3 GONSTS: Global OUT NAK status 0:A handshake is sent based on the FIFO Status and the NAK and STALL bit settings. 1:No data is written to the Rx FIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped. Bit 2 GINSTS: Global IN NAK status 0:A handshake is sent out based on the data availability in the transmit FIFO. 1:A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO. Bit 1 SDIS: Soft disconnect The application uses this bit to signal the USB OTG core to perform a soft disconnect. As long as this bit is set, the host does not see that the device is connected, and the device does not receive signals on the USB. The core stays in the disconnected state until the application clears this bit. 0:Normal operation. When this bit is cleared after a soft disconnect, the core generates a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration. 1:The core generates a device disconnect event to the USB host. Bit 0 RWUSIG: Remote wakeup signaling When the application sets this bit, the core initiates remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the Suspend state. As specified in the USB 2.0 specification, the application must clear this bit 1 ms to 15 ms after setting it. If LPM is enabled and the core is in the L1 (sleep) state, when the application sets this bit, the core initiates L1 remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the sleep state. As specified in the LPM specification, the hardware automatically clears this bit 50 µs (TL1DevDrvResume) after being set by the application. The application must not set this bit when bRemoteWake from the previous LPM transaction is zero (refer to REMWAKE bit in GLPMCFG register). Table 258 contains the minimum duration (according to device state) for which the Soft disconnect (SDIS) bit must be set for the USB host to detect a device disconnect. To accommodate clock jitter, it is recommended that the application add some extra delay to the specified minimum duration. Table 258. Minimum duration for soft disconnect Operating speed 1556/1680 Device state Minimum duration Full speed Suspended 1 ms + 2.5 µs Full speed Idle 2.5 µs Full speed Not Idle or Suspended (Performing transactions) 2.5 µs DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) 43.15.34 OTG device status register (OTG_DSTS) Address offset: 0x808 Reset value: 0x0000 0010 This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (OTG_DAINT) register. 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 r r r r r 21 20 19 18 17 16 r FNSOF r r r r r r r 7 6 5 4 3 2 1 Res. r 22 DEVLNSTS 8 FNSOF r 23 Res. r Res. Res. EERR r ENUMSPD r 0 SUSP STS r r Bits 31:24 Reserved, must be kept at reset value. Bits 23:22 DEVLNSTS: Device line status Indicates the current logic level USB data lines. Bit [23]: Logic level of D+ Bit [22]: Logic level of DBits 21:8 FNSOF: Frame number of the received SOF Bits 7:4 Reserved, must be kept at reset value. Bit 3 EERR: Erratic error The core sets this bit to report any erratic errors. Due to erratic errors, the OTG_FS controller goes into Suspended state and an interrupt is generated to the application with Early suspend bit of the OTG_GINTSTS register (ESUSP bit in OTG_GINTSTS). If the early suspend is asserted due to an erratic error, the application can only perform a soft disconnect recover. Bits 2:1 ENUMSPD: Enumerated speed Indicates the speed at which the OTG_FS controller has come up after speed detection through a chirp sequence. 01: Reserved 10: Reserved 11: Full speed (PHY clock is running at 48 MHz) Others: reserved Bit 0 SUSPSTS: Suspend status In device mode, this bit is set as long as a Suspend condition is detected on the USB. The core enters the Suspended state when there is no activity on the USB data lines for a period of 3 ms. The core comes out of the suspend: – When there is an activity on the USB data lines – When the application writes to the Remote wakeup signaling bit in the OTG_DCTL register (RWUSIG bit in OTG_DCTL). DocID024597 Rev 1 1557/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 43.15.35 OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK) Address offset: 0x810 Reset value: 0x0000 0000 This register works with each of the OTG_DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the OTG_DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. NAKM Res. Res. Res. Res. Res. Res. INEPN EM TOM Res. EPDM XFRC M rw rw rw rw INEPN ITTXFE MM MSK rw Bits 31:14 Reserved, must be kept at reset value. Bits 13 NAKM: NAK interrupt mask 0: Masked interrupt 1: Unmasked interrupt Bits 12:7 Reserved, must be kept at reset value for USB OTG FS. Bit 6 INEPNEM: IN endpoint NAK effective mask 0: Masked interrupt 1: Unmasked interrupt Bit 5 INEPNMM: IN token received with EP mismatch mask 0: Masked interrupt 1: Unmasked interrupt Bit 4 ITTXFEMSK: IN token received when Tx FIFO empty mask 0: Masked interrupt 1: Unmasked interrupt Bit 3 TOM: Timeout condition mask (Non-isochronous endpoints) 0: Masked interrupt 1: Unmasked interrupt Bit 2 Reserved, must be kept at reset value. Bit 1 EPDM: Endpoint disabled interrupt mask 0: Masked interrupt 1: Unmasked interrupt Bit 0 XFRCM: Transfer completed interrupt mask 0: Masked interrupt 1: Unmasked interrupt 1558/1680 DocID024597 Rev 1 rw rw RM0351 USB on-the-go full-speed (OTG_FS) 43.15.36 OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) Address offset: 0x814 Reset value: 0x0000 0000 This register works with each of the OTG_DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the OTG_DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EPDM XFRC M rw rw OTEPD STUPM M rw rw Bits 31:5 Reserved, must be kept at reset value for USB OTG FS. Bit 6 Reserved, must be kept at reset value for USB OTG FS. Bit 4 OTEPDM: OUT token received when endpoint disabled mask. Applies to control OUT endpoints only. 0: Masked interrupt 1: Unmasked interrupt Bit 3 STUPM: STUPM: SETUP phase done mask. Applies to control endpoints only. 0: Masked interrupt 1: Unmasked interrupt Bit 2 Reserved, must be kept at reset value. Bit 1 EPDM: Endpoint disabled interrupt mask 0: Masked interrupt 1: Unmasked interrupt Bit 0 XFRCM: Transfer completed interrupt mask 0: Masked interrupt 1: Unmasked interrupt 43.15.37 OTG device all endpoints interrupt register (OTG_DAINT) Address offset: 0x818 Reset value: 0x0000 0000 When a significant event occurs on an endpoint, a OTG_DAINT register interrupts the application using the Device OUT endpoints interrupt bit or Device IN endpoints interrupt bit of the OTG_GINTSTS register (OEPINT or IEPINT in OTG_GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits DocID024597 Rev 1 1559/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding Device Endpoint-x interrupt register (OTG_DIEPINTx/OTG_DOEPINTx). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OEPINT r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r IEPINT r r r r r r r r Bits 31:16 OEPINT: OUT endpoint interrupt bits One bit per OUT endpoint: Bit 16 for OUT endpoint 0, bit 18 for OUT endpoint 3. Bits 15:0 IEPINT: IN endpoint interrupt bits One bit per IN endpoint: Bit 0 for IN endpoint 0, bit 3 for endpoint 3. 43.15.38 OTG all endpoints interrupt mask register (OTG_DAINTMSK) Address offset: 0x81C Reset value: 0x0000 0000 The OTG_DAINTMSK register works with the Device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the OTG_DAINT register bit corresponding to that interrupt is still set. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OEPM rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw IEPM rw rw rw rw rw rw rw rw Bits 31:16 OEPM: OUT EP interrupt mask bits One per OUT endpoint: Bit 16 for OUT EP 0, bit 18 for OUT EP 3 0: Masked interrupt 1: Unmasked interrupt Bits 15:0 IEPM: IN EP interrupt mask bits One bit per IN endpoint: Bit 0 for IN EP 0, bit 3 for IN EP 3 0: Masked interrupt 1: Unmasked interrupt 1560/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) 43.15.39 OTG device VBUS discharge time register (OTG_DVBUSDIS) Address offset: 0x0828 Reset value: 0x0000 17D7 This register specifies the VBUS discharge time after VBUS pulsing during SRP. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw VBUSDT rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 VBUSDT: Device VBUS discharge time Specifies the VBUS discharge time after VBUS pulsing during SRP. This value equals: VBUS discharge time in PHY clocks / 1 024 Depending on your VBUS load, this value may need adjusting. 43.15.40 OTG device VBUS pulsing time register (OTG_DVBUSPULSE) Address offset: 0x082C Reset value: 0x0000 05B8 This register specifies the VBUS pulsing time during SRP. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DVBUSP rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DVBUSP: Device VBUS pulsing time Specifies the VBUS pulsing time during SRP. This value equals: VBUS pulsing time in PHY clocks / 1 024 DocID024597 Rev 1 1561/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 43.15.41 OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK) Address offset: 0x834 Reset value: 0x0000 0000 This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_OTG_DIEPINTx). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw INEPTXFEM rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 INEPTXFEM: IN EP Tx FIFO empty interrupt mask bits These bits act as mask bits for OTG_DIEPINTx. TXFE interrupt one bit per IN endpoint: Bit 0 for IN endpoint 0, bit 3 for IN endpoint 3 0: Masked interrupt 1: Unmasked interrupt 43.15.42 OTG device control IN endpoint 0 control register (OTG_DIEPCTL0) Address offset: 0x900 Reset value: 0x0000 0000 This section describes the OTG_DIEPCTL0 register for USB_OTG FS. Nonzero control endpoints use registers for endpoints 1–3. 31 30 EPENA EPDIS 29 28 27 26 25 24 23 22 Res. Res. SNAK CNAK w w rw rw rw rw rs TXFNUM 21 20 STALL Res. rs rs 15 14 13 12 11 10 9 8 7 6 5 USBA EP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r 1562/1680 19 18 EPTYP 17 16 NAK STS Res. r r r 4 3 2 1 Res. Res. Res. MPSIZ rw DocID024597 Rev 1 0 rw RM0351 USB on-the-go full-speed (OTG_FS) Bit 31 EPENA: Endpoint enable The application sets this bit to start transmitting data on the endpoint 0. The core clears this bit before setting any of the following interrupts on this endpoint: – Endpoint disabled – Transfer completed Bit 30 EPDIS: Endpoint disable The application sets this bit to stop transmitting data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the Endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint disabled interrupt. The application must set this bit only if Endpoint enable is already set for this endpoint. Bits 29:28 Reserved, must be kept at reset value. Bit 27 SNAK: Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on that endpoint. Bit 26 CNAK: Clear NAK A write to this bit clears the NAK bit for the endpoint. Bits 25:22 TXFNUM: Tx FIFO number This value is set to the FIFO number that is assigned to IN endpoint 0. Bit 21 STALL: STALL handshake The application can only set this bit, and the core clears it when a SETUP token is received for this endpoint. If a NAK bit, a Global IN NAK or Global OUT NAK is set along with this bit, the STALL bit takes priority. Bit 20 Reserved, must be kept at reset value. Bits 19:18 EPTYP: Endpoint type Hardcoded to ‘00’ for control. Bit 17 NAKSTS: NAK status Indicates the following: 0: The core is transmitting non-NAK handshakes based on the FIFO status 1: The core is transmitting NAK handshakes on this endpoint. When this bit is set, either by the application or core, the core stops transmitting data, even if there are data available in the Tx FIFO. Irrespective of this bit’s setting, the core always responds to SETUP data packets with an ACK handshake. Bit 16 Reserved, must be kept at reset value. DocID024597 Rev 1 1563/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Bit 15 USBAEP: USB active endpoint This bit is always set to 1, indicating that control endpoint 0 is always active in all configurations and interfaces. Bits 14:2 Reserved, must be kept at reset value. Bits 1:0 MPSIZ: Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. 00: 64 bytes 01: 32 bytes 10: 16 bytes 11: 8 bytes 43.15.43 OTG device endpoint-x control register (OTG_DIEPCTLx) (x = 1..5 , where x = Endpoint_number) Address offset: 0x900 + (Endpoint_number × 0x20) Reset value: 0x0000 0000 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 31 30 EPENA EPDIS 29 28 27 26 SODD FRM SD0 PID/ SEVN FRM SNAK CNAK 25 24 23 22 TXFNUM 21 20 STALL Res. rs rs w w w w rw rw rw rw rw/rs 15 14 13 12 11 10 9 8 7 6 5 USBA EP Res. Res. Res. Res. rw 19 18 EPTYP 17 16 NAK STS EO NUM/ DPID rw rw r r 4 3 2 1 0 rw rw rw rw rw MPSIZ rw rw rw rw rw rw Bit 31 EPENA: Endpoint enable The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: – SETUP phase done – Endpoint disabled – Transfer completed Bit 30 EPDIS: Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the Endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint disabled interrupt. The application must set this bit only if Endpoint enable is already set for this endpoint. Bit 29 SODDFRM: Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. 1564/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Bit 28 SD0PID: Set DATA0 PID Applies to interrupt/bulk IN endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. SEVNFRM: Set even frame Applies to isochronous IN endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. Bit 27 SNAK: Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a Transfer completed interrupt, or after a SETUP is received on the endpoint. Bit 26 CNAK: Clear NAK A write to this bit clears the NAK bit for the endpoint. Bits 25:22 TXFNUM: Tx FIFO number These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. Bit 21 STALL: STALL handshake Applies to non-control, non-isochronous IN endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit’s setting, the core always responds to SETUP data packets with an ACK handshake. Bit 20 Reserved, must be kept at reset value. Bits 19:18 EPTYP: Endpoint type This is the transfer type supported by this logical endpoint. 00: Control 01: Isochronous 10: Bulk 11: Interrupt Bit 17 NAKSTS: NAK status It indicates the following: 0: The core is transmitting non-NAK handshakes based on the FIFO status. 1: The core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the Tx FIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there are data available in the Tx FIFO. Irrespective of this bit’s setting, the core always responds to SETUP data packets with an ACK handshake. DocID024597 Rev 1 1565/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Bit 16 EONUM: Even/odd frame Applies to isochronous IN endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 0: Even frame 1: Odd frame DPID: Endpoint data PID Applies to interrupt/bulk IN endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID register field to program either DATA0 or DATA1 PID. 0: DATA0 1: DATA1 Bit 15 USBAEP: USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. Bits 14:11 Reserved, must be kept at reset value. Bits 10:0 MPSIZ: Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 43.15.44 OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0) Address offset: 0xB00 Reset value: 0x0000 8000 This section describes the OTG_DOEPCTL0 register. Nonzero control endpoints use registers for endpoints 1–3. 31 30 EPENA EPDIS 29 28 27 Res. Res. SNAK 26 CNAK 25 24 23 22 Res. Res. Res. Res. 21 20 STALL SNPM 19 18 EPTYP 17 16 NAK STS Res. w r w w rs rw r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 USBA EP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. r 1566/1680 MPSIZ r DocID024597 Rev 1 0 r RM0351 USB on-the-go full-speed (OTG_FS) Bit 31 EPENA: Endpoint enable The application sets this bit to start transmitting data on endpoint 0. The core clears this bit before setting any of the following interrupts on this endpoint: – SETUP phase done – Endpoint disabled – Transfer completed Bit 30 EPDIS: Endpoint disable The application cannot disable control OUT endpoint 0. Bits 29:28 Reserved, must be kept at reset value. Bit 27 SNAK: Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit on a Transfer completed interrupt, or after a SETUP is received on the endpoint. Bit 26 CNAK: Clear NAK A write to this bit clears the NAK bit for the endpoint. Bits 25:22 Reserved, must be kept at reset value. Bit 21 STALL: STALL handshake The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit’s setting, the core always responds to SETUP data packets with an ACK handshake. Bit 20 SNPM: Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. Bits 19:18 EPTYP: Endpoint type Hardcoded to 2’b00 for control. Bit 17 NAKSTS: NAK status Indicates the following: 0: The core is transmitting non-NAK handshakes based on the FIFO status. 1: The core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit, the core stops receiving data, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bit’s setting, the core always responds to SETUP data packets with an ACK handshake. Bit 16 Reserved, must be kept at reset value. Bit 15 USBAEP: USB active endpoint This bit is always set to 1, indicating that a control endpoint 0 is always active in all configurations and interfaces. Bits 14:2 Reserved, must be kept at reset value. Bits 1:0 MPSIZ: Maximum packet size The maximum packet size for control OUT endpoint 0 is the same as what is programmed in control IN endpoint 0. 00: 64 bytes 01: 32 bytes 10: 16 bytes 11: 8 bytes DocID024597 Rev 1 1567/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 43.15.45 OTG device endpoint-x control register (OTG_DOEPCTLx) (x = 1..5 , where x = Endpoint_number) Address offset for OUT endpoints: 0xB00 + (Endpoint_number × 0x20) Reset value: 0x0000 0000 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 31 30 EPENA EPDIS 29 28 27 26 25 24 23 22 21 20 SD1 PID/ SODD FRM SD0 PID/ SEVN FRM SNAK CNAK Res. Res. Res. Res. STALL SNPM rw/rs rw rw 5 4 rw rs rs w w w w 15 14 13 12 11 10 USBA EP Res. Res. Res. Res. rw 9 8 7 6 19 18 17 16 NAK STS EO NUM/ DPID rw r r 3 2 1 0 rw rw rw rw EPTYP MPSIZ rw rw rw rw rw rw Bit 31 EPENA: Endpoint enable Applies to IN and OUT endpoints. The application sets this bit to start transmitting data on an endpoint. The core clears this bit before setting any of the following interrupts on this endpoint: – SETUP phase done – Endpoint disabled – Transfer completed Bit 30 EPDIS: Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the Endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint disabled interrupt. The application must set this bit only if Endpoint enable is already set for this endpoint. Bit 29 SD1PID: Set DATA1 PID Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA1. SODDFRM: Set odd frame Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to odd frame. Bit 28 SD0PID: Set DATA0 PID Applies to interrupt/bulk OUT endpoints only. Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0. SEVNFRM: Set even frame Applies to isochronous OUT endpoints only. Writing to this field sets the Even/Odd frame (EONUM) field to even frame. Bit 27 SNAK: Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for OUT endpoints on a Transfer Completed interrupt, or after a SETUP is received on the endpoint. 1568/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Bit 26 CNAK: Clear NAK A write to this bit clears the NAK bit for the endpoint. Bits 25:22 Reserved, must be kept at reset value. Bit 21 STALL: STALL handshake Applies to non-control, non-isochronous OUT endpoints only (access type is rw). The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only (access type is rs). The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit’s setting, the core always responds to SETUP data packets with an ACK handshake. Bit 20 SNPM: Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. Bits 19:18 EPTYP: Endpoint type This is the transfer type supported by this logical endpoint. 00: Control 01: Isochronous 10: Bulk 11: Interrupt Bit 17 NAKSTS: NAK status Indicates the following: 0: The core is transmitting non-NAK handshakes based on the FIFO status. 1: The core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bit’s setting, the core always responds to SETUP data packets with an ACK handshake. Bit 16 EONUM: Even/odd frame Applies to isochronous IN and OUT endpoints only. Indicates the frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register. 0: Even frame 1: Odd frame DPID: Endpoint data PID Applies to interrupt/bulk OUT endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The application uses the SD0PID register field to program either DATA0 or DATA1 PID. 0: DATA0 1: DATA1 DocID024597 Rev 1 1569/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Bit 15 USBAEP: USB active endpoint Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. Bits 14:11 Reserved, must be kept at reset value. Bits 10:0 MPSIZ: Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. 43.15.46 OTG device endpoint-x interrupt register (OTG_DIEPINTx) (x = 0..5 , where x = Endpoint_number) Address offset: 0x908 + (Endpoint_number × 0x20) Reset value: 0x0000 0080 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure 496. The application must read this register when the IN endpoints interrupt bit of the Core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the Device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXFE INEP NE Res. EP DISD XFRC r rc_w1/ rw rc_w1 rc_w1 Res. Res. Res. Res. Res. Res. Res. Res. Res. ITTXFE TOC rc_w1 rc_w1 Bits 31:8 Reserved, must be kept at reset value. Bit 7 TXFE: Transmit FIFO empty This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG). Bit 6 INEPNE: IN endpoint NAK effective This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_DIEPCTLx. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit. Bit 5 Reserved, must be kept at reset value. 1570/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Bit 4 ITTXFE: IN token received when Tx FIFO is empty Applies to non-periodic IN endpoints only. Indicates that an IN token was received when the associated Tx FIFO (periodic/nonperiodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. Bit 3 TOC: Timeout condition Applies only to Control IN endpoints. Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint. Bit 2 Reserved, must be kept at reset value. Bit 1 EPDISD: Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the application’s request. Bit 0 XFRC: Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 43.15.47 OTG device endpoint-x interrupt register (OTG_DOEPINTx) (x = 0..5 , where x = Endpoint_number) Address offset: 0xB08 + (Endpoint_number × 0x20) Reset value: 0x0000 0080 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure 496. The application must read this register when the OUT Endpoints Interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. B2B STUP Res. OTEP DIS STUP Res. EP DISD XFRC rc_w1 rc_w1 rc_w1 rc_w1 Res. Res. Res. Res. Res. Res. Res. Res. rc_w1/ rw Bits 31:7 Reserved, must be kept at reset value. Bit 6 B2BSTUP: Back-to-back SETUP packets received Applies to control OUT endpoint only. This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. Bit 5 Reserved, must be kept at reset value. DocID024597 Rev 1 1571/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Bit 4 OTEPDIS: OUT token received when endpoint disabled Applies only to control OUT endpoints. Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received. Bit 3 STUP: SETUP phase done Applies to control OUT endpoint only. Indicates that the SETUP phase for the control endpoint is complete and no more back-toback SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet. Bit 2 Reserved, must be kept at reset value. Bit 1 EPDISD: Endpoint disabled interrupt This bit indicates that the endpoint is disabled per the application’s request. Bit 0 XFRC: Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. 43.15.48 OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0) Address offset: 0x910 Reset value: 0x0000 0000 The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using the endpoint enable bit in the device control endpoint 0 control registers (EPENA in OTG_DIEPCTL0), the core modifies this register. The application can only read this register once the core has cleared the Endpoint enable bit. Nonzero endpoints use the registers for endpoints 1–3. 31 30 29 28 27 26 25 24 23 22 21 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 Res. Res. Res. Res. Res. Res. Res. Res. Res. 6 19 PKTCNT rw rw 4 3 18 17 16 Res. Res. Res. 2 1 0 rw rw rw XFRSIZ rw Bits 31:21 Reserved, must be kept at reset value. 1572/1680 5 20 DocID024597 Rev 1 rw rw rw RM0351 USB on-the-go full-speed (OTG_FS) Bits 20:19 PKTCNT: Packet count Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0. This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. Bits 18:7 Reserved, must be kept at reset value. Bits 6:0 XFRSIZ: Transfer size Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the Tx FIFO. 43.15.49 OTG device OUT endpoint 0 transfer size register (OTG_DOEPTSIZ0) Address offset: 0xB10 Reset value: 0x0000 0000 The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using the Endpoint enable bit in the OTG_DOEPCTL0 registers (EPENA bit in OTG_DOEPCTL0), the core modifies this register. The application can only read this register once the core has cleared the Endpoint enable bit. 31 Res. 30 29 STUPCNT 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. PKTCNT Nonzero endpoints use the registers for endpoints 1–5 . Res. Res. Res. 2 1 0 rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 Res. Res. Res. Res. Res. Res. Res. Res. Res. 6 5 4 3 XFRSIZ rw rw rw rw Bit 31 Reserved, must be kept at reset value. Bits 30:29 STUPCNT: SETUP packet count This field specifies the number of back-to-back SETUP data packets the endpoint can receive. 01: 1 packet 10: 2 packets 11: 3 packets Bits 28:20 Reserved, must be kept at reset value. DocID024597 Rev 1 1573/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Bit 19 PKTCNT: Packet count This field is decremented to zero after a packet is written into the Rx FIFO. Bits 18:7 Reserved, must be kept at reset value. Bits 6:0 XFRSIZ: Transfer size Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. 43.15.50 OTG device IN endpoint-x transfer size register (OTG_DIEPTSIZx) (x = 1..5 , where x= Endpoint_number) Address offset: 0x910 + (Endpoint_number × 0x20) Reset value: 0x0000 0000 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the Endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the Endpoint enable bit. 31 30 Res. 15 29 28 27 26 25 MCNT 24 23 22 21 20 19 18 PKTCNT 17 16 XFRSIZ rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw XFRSIZ rw rw rw rw rw rw rw rw rw Bit 31 Reserved, must be kept at reset value. Bits 30:29 MCNT: Multi count For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints. 01: 1 packet 10: 2 packets 11: 3 packets Bit 28:19 PKTCNT: Packet count Indicates the total number of USB packets that constitute the Transfer Size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is read from the Tx FIFO. Bits 18:0 XFRSIZ: Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the Tx FIFO. 1574/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) 43.15.51 OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) (x = 0..5 , where x = Endpoint_number) Address offset for IN endpoints: 0x918 + (Endpoint_number × 0x20) This read-only register contains the free space information for the Device IN endpoint Tx FIFO. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r INEPTFSAV r r r r r r r r r 31:16 Reserved, must be kept at reset value. 15:0 INEPTFSAV: IN endpoint Tx FIFO space available Indicates the amount of free space available in the Endpoint Tx FIFO. Values are in terms of 32-bit words: 0x0: Endpoint Tx FIFO is full 0x1: 1 word available 0x2: 2 words available 0xn: n words available Others: Reserved 43.15.52 OTG device OUT endpoint-x transfer size register (OTG_DOEPTSIZx) (x = 1..5 , where x = Endpoint_number) Address offset: 0xB10 + (Endpoint_number × 0x20) Reset value: 0x0000 0000 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using Endpoint Enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the Endpoint enable bit. 31 Res. 15 30 29 28 27 26 25 RXDPID/ STUPCNT 24 23 22 21 20 19 18 PKTCNT 17 16 XFRSIZ r/rw r/rw rw rw rw rw rw rw rw rw rw rw rw rw rw 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw XFRSIZ rw rw rw rw rw rw rw rw rw DocID024597 Rev 1 1575/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Bit 31 Reserved, must be kept at reset value. Bits 30:29 RXDPID: Received data PID Applies to isochronous OUT endpoints only. This is the data PID received in the last packet for this endpoint. 00: DATA0 10: DATA1 STUPCNT: SETUP packet count Applies to control OUT Endpoints only. This field specifies the number of back-to-back SETUP data packets the endpoint can receive. 01: 1 packet 10: 2 packets 11: 3 packets Bit 28:19 PKTCNT: Packet count Indicates the total number of USB packets that constitute the Transfer Size amount of data for this endpoint. This field is decremented every time a packet (maximum size or short packet) is written to the Rx FIFO. Bits 18:0 XFRSIZ: Transfer size This field contains the transfer size in bytes for the current endpoint. The core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from the Rx FIFO and written to the external memory. 43.15.53 OTG power and clock gating control register (OTG_PCGCCTL) Address offset: 0xE00 Reset value: 0x0000 0000 This register is available in host and device modes. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. SUSP PHY SLEEP ENL1 GTG PHY SUSP Res. Res. GATE HCLK STPP CLK r r r/w r rw rw Bit 31:8 Reserved, must be kept at reset value. Bit 7 SUSP: Deep Sleep This bit indicates that the PHY is in Deep Sleep when in L1 state. Bit 6 PHYSLEEP: PHY in Sleep This bit indicates that the PHY is in the Sleep state. 1576/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Bit 5 ENL1GTG: Enable Sleep clock gating When this bit is set, core internal clock gating is enabled in Sleep state if the core cannot assert utmi_l1_suspend_n. When this bit is not set, the PHY clock is not gated in Sleep state. Bit 4 PHYSUSP: PHY Suspended Indicates that the PHY has been Suspended. This bit is updated once the PHY is Suspended after the application has set the STPPCLK bit. Bits 3:2 Reserved, must be kept at reset value. Bit 1 GATEHCLK: Gate HCLK The application sets this bit to gate HCLK to modules other than the AHB Slave and Master and wakeup logic when the USB is suspended or the session is not valid. The application clears this bit when the USB is resumed or a new session starts. Bit 0 STPPCLK: Stop PHY clock The application sets this bit to stop the PHY clock when the USB is suspended, the session is not valid, or the device is disconnected. The application clears this bit when the USB is resumed or a new session starts. 43.15.54 OTG_FS register map The table below gives the USB OTG register map and reset values. SRQ SRQSCS 0 Res. Res. Res. Res. Res. Res. Res. SEDET 0 0 0 0 0 Res. Res. Res. Res. Res. 0 Res. 0 0 0 CSRST 0 0 Res. 0 Res. Res. 1 TOCAL FCRST 0 Res. Res. PHYSEL 0 TXFNUM 0 DocID024597 Rev 1 0 0 RXFFLSH Res. 1 0 TXFFLSH 0 SRPCAP 1 HNPCAP 0 Res. TRDT Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 0 Res. Reset value FHMOD OTG_ GRSTCTL 0 Res. 0x010 AHBIDL Reset value Res. Res. OTG_ GUSBCFG FDMOD 0x00C Res. Reset value Res. VBVALOEN 0 GINTMSK AVALOEN VBVALOVAL 0 Res. BVALOEN AVALOVAL 0 Res. BVALOVAL 0 TXFELVL HNPRQ HNGSCS 0 SRSSCHG 0 HNSSCHG 0 Res. 0 PTXFELVL DHNPEN HSHNPEN 0 Res. 0 Res. Res. EHEN 0 Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. 0 Res. DBCT CIDSTS Res. 0 Res. ASVLD HNGDET 0 Res. BSVLD 1 DBCDNE 0 ADTOCHG 0 Res. 0 Res. OTGVER Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTG_ GAHBCFG Res. 0x008 Res. Reset value 0 IDCHNG Res. Res. Res. Res. Res. Res. Res. Res. Res. OTG_ GOTGINT Res. 0x004 Res. Reset value Res. Res. Res. Res. Res. Res. Res. OTG_ GOTGCTL Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x000 Res. Register Res. Offset Res. Table 259. OTG_FS register map and reset values 0 0 0 1577/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Register 0x014 OTG_ GINTSTS WKUINT SRQINT Reset value 0 0 OTG_ GINTMSK WUIM SRQIM DISCINT CIDSCHGM LPMINTM Reset value 0 0 0 0 0 OTG_ GRXSTSR (host mode) Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 GINAKEFF NPTXFE RXFLVL SOF OTGINT MMIS CMOD GONAKEFFM GINAKEFFM NPTXFEM RXFLVLM SOFM OTGINT MMISM Res. Res. GONAKEFF 0 0 0 0 0 0 0 0 BCNT 0 0 0 0 0 0 CHNUM 0 0 0 0 0 0 BCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNUM 0 0 0 0 0 0 BCNT 0 0 EPNUM BCNT 0 0 0 EPNUM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFD 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 Res. Res. Res. Res. VBDEN SDEN PDEN DCDEN 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 NPTXFSAV Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 1 Res. 0 Res. NPTQXSAV Res. NPTXQTOP 0 0 0 PDET 0 0 DCDET 1 0 Res. 0 0 Res. 0 Res. ESUSP ESUSPM 0 Res. USBRST USBSUSP USBRST USBSUSPM 0 Res. ISOODRP ENUMDNE ISOODRPM 0 1 PWRDWN 0 OTG_CID 1578/1680 0 0 BCDEN 0 Res. Res. Res. 0 Reset value Reset value 0 0 NPTXFSA/TX0FSA Res. 0 OTG_ HNPTXSTS Reset value 0x03C 0 NPTXFD/TX0FD Reset value OTG_ GCCFG 0 0 OTG_ HNPTXFSIZ/ OTG_ DIEPTXF0 0x038 0 DPID Res. PKTSTS Res. 0x02C 0 DPID Reset value 0x028 0 ENUMDNEM Res. 0 Res. FRMNUM 0 0 DPID PKTSTS 0 0 Res. Res. Res. Res. Res. Res. 0 0 SDET Res. Res. Res. Res. Res. Res. Res. 0x024 Res. Reset value OTG_ GRXFSIZ 0 0 Res. Reset value OTG_ GRXSTSPR (Device mode) 0 0 DPID PKTSTS Res. Res. Res. Res. FRMNUM 0 0 PS2DET Res. Res. Res. Res. Res. Res. Res. Res. Res. OTG_ GRXSTSR (host mode) PKTSTS EOPF 0 0 EOPFM 0 Res. IEPINT IEPINT 0 Res. OEPINT OEPINT 0 Res. IISOIXFR 0 IISOIXFRM Res. 0 0 Res. OTG_ GRXSTSR (Device mode) Reset value 0x020 IPXFR/INCOMPISOOUT 0 0 IPXFRM/IISOOXFRM 0 0 Res. RSTDET RSTDETM 0 Res. PRTIM 0 Res. HCINT HPRTINT 0 PTXFE 0 HCIM LPMINT DISCINT CIDSCHG 0 0 1 Reset value Res. 0x01C 0 1 PTXFEM 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Res. Table 259. OTG_FS register map and reset values (continued) 0 0 0 0 0 0 0 0 PRODUCT_ID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID024597 Rev 1 0 0 1 0 0 0 0 0 0 0 0 0 RM0351 USB on-the-go full-speed (OTG_FS) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADPPRBIM ADPTOIF ADPSNSIF ADPPRBIF ADPEN ADPRST ENASNS ENAPRB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTXSA 0 0 0 0 0 0 0 0 0 0 0 1 INEPTXFD 0 0 PTXSA INEPTXFD 0 0 0 0 0 0 INEPTXSA 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 . . . . Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 OTG_ HCFG Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FSLSS INEPTXSA Res. INEPTXFD Res. OTG_ DIEPTXF5 0 Res. 0x204 0 PRB DS CHG Res. . . . . 0 PRB DEL TA Reset value 0x408 0 OTG_ HPTXSTS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 OTG_ HAINT 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 1 1 0 1 0 1 0 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAINTM 0 DocID024597 Rev 1 0 HAINT 0 Res. 0 PTXFSAVL Reset value OTG_ HAINTMSK 1 PTXQSAV Res. PTXQTOP 0 Reset value 0x418 0 FRNUM Res. 0x414 0 0 FRIVL FTREM Res. 0x410 0 OTG_ HFNUM Reset value RLDCTRL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTG_ HFIR Res. 0x404 Res. Reset value FSLSPCS Reset value 1 PRB PER RTIM PTXFSIZ OTG_ DIEPTXF2 . . . . 0x400 0 OTG_ DIEPTXF1 Reset value 0x108 0 OTG_ HPTXFSIZ Reset value 0x104 AR ADPSNSIM Reset value 0x100 0 0 ADPTOIM Res. Res. 0x060 OTG_ GADPCTL 0 0 Res. Reset value BESL LPMEN 0 BESLTHRS LPMACK 0 Res. 0 LPM RSP Res. L1SSEN REMWAKE 0 Res. 0 LPMCHIDX ADPMEN SLPSTS 0 Res. 0 LPM RCNT L1DSEN L1RSMOK 0 SNDLPM 0 ADPIF 0 Res. LPMR CNTSTS Res. Res. Res. OTG_ GPWRDN Res. 0x058 Res. Reset value ENBESL OTG_ GLPMCFG Res. 0x054 Res. Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 259. OTG_FS register map and reset values (continued) 0 0 0 0 0 0 0 0 1579/1680 1635 . . . . . . . . 0x660 OTG_ HCCHAR11 CHENA CHDIS ODDFRM . . . . 1580/1680 DPID 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_ HCINT1 Res. Res. Res. 0 0 . . . . DocID024597 Rev 1 0 0 0 . . . . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value Reset value PKTCNT 0 0 Res. 0 0 0 0 0 0 0 0 0 0 0 0 EPNUM 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. DTERR FRMOR BBERR TXERR Res. 0 0 0 0 XFRSIZ 0 0 0 0 0 0 0 0 XFRSIZ . . . . MPSIZ 0 0 0 0 0 0 0 0 0 PSPD Res. PCSTS POCA PENCHNG PENA PRES PSUSP POCCHNG PRST Res. PLSTS PPWR PCDET XFRC Res. EPDIR LSDEV MPSIZ 0 0 0 0 0 0 Res. 0 CHH 0 0 0 0 0 0 Res. 0 MPSIZ 0 0 0 0 0 XFRCM 0 NAK 0 STALL 0 ACK 0 XFRCM Res. EPTYP 0 CHHM 0 NAKM Res. Res. Res. 0 0 0 0 0 0 Res. 0 STALLM Res. MCNT 0 Res. 0 ACKM Res. Res. Res. 0 CHHM XFRC 0 CHH 0 NAK 0 STALL EPNUM NAKM 0 Res. Res. EPNUM STALLM 0 TXERRM Res. Res. 0 ACK 0 BBERRM Res. Res. Res. Res. Res. Res. 0 ACKM 0 FRMORM Res. 0 Res. TXERR 0 TXERRM 0 BBERR PKTCNT FRMOR 0 DTERRM Res. 0 Res. Reset value BBERRM 0 Res. Res. 0 FRMORM 0 Res. Res. 0 DTERR 0 Res. Res. 0 DTERRM 0 Res. OTG_ HCINT0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 EPDIR 0 Res. 0 Res. LSDEV EPTYP MCNT 0 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. PTCTL Res. 0 Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. ODDFRM 0 Res. Res. Res. Res. Res. 0 DAD Res. Res. Res. Res. 0 Res. 0 Res. DPID 0 Res. Reset value Res. 0 Res. CHDIS 0 Res. 0 EPDIR OTG_ HCTSIZ1 0 Res. Reset value 0 Res. CHENA Reset value Res. Reset value LSDEV 0x530 Res. 0 Res. OTG_ HCCHAR0 DAD EPTYP OTG_ HCINTMSK1 Res. ODDFRM Reset value Res. OTG_ HCINTMSK0 Res. Reset value Res. 0x510 OTG_ HCTSIZ0 Res. 0x508 Res. 0x500 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OTG_ HPRT MCNT 0x52C CHDIS 0x528 OTG_ HCCHAR1 CHENA 0x520 Res. 0x50C Res. 0x440 Res. Register Res. Offset Res. USB on-the-go full-speed (OTG_FS) RM0351 Table 259. OTG_FS register map and reset values (continued) 0 0 0 0 0 0 0 0 0x814 0x818 0x81C OTG_ DOEPMSK Reset value Reset value 0 0 0 0 0 0 0 0 0 0 0 0 OTG_ DAINT OTG_ DAINTMSK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID024597 Rev 1 0 0 0 0 0 0 0 0 Res. 0 0 0 0 OEPINT 0 0 0 OEPM 0 0 0 0 0 Reset value EPDM XFRCM SDIS RWUSIG 0 0 0 0 0 0 0 0 0 DSPD XFRCM Res. NAKM STALLM 0 0 0 0 XFRC 0 0 0 1 0 SUSPSTS 0 CHHM XFRSIZ 0 Res. . . . . CHH 0 NZLSOHSK 0 XFRCM GINSTS 0 ENUMSPD NAK STALL Res. ACKM 0 Res. GONSTS 0 Res. TXERRM 0 EPDM 0 EERR BBERRM Res. FRMORM 0 0 0 0 Res. TOM 0 0 ACK 0 ITTXFEMSK 0 0 STUPM 0 0 OTEPDM 0 0 TCTL 0 Res. 0 Res. DTERRM Res. Res. 0 INEPNMM 0 TXERR 0 Res. Res. 0 Res. 0 Res. DAD 0 BBERR 0 FRMOR 0 DTERR 0 Res. Res. 0 INEPNEM SGINAK FNSOF 0 Res. 0 CGINAK PFIVL 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 SGONAK 0 0 Res. 0 Res. 0 CGONAK 0 0 Res. 0 Res. 0 POPRGDNE Reset value Res. 0 Res. Res. 0 Res. . . . . 0 Res. Res. PKTCNT Res. Reset value 0 Res. Res. Res. ERRATIM Res. Res. Res. Reset value Res. 0 NAKM 0 Res. 0 Res. Res. 0 Res. 0 Res. DEV LN STS Res. Reset value Res. 0 Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. DSBESLRJCT Res. Res. 0 Res. 0 Res. Reset value 0 Res. 0 Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. DPID Res. Res. Res. Res. Res. Res. 0 Res. OTG_ DIEPMSK 0 Res. 0x810 OTG_ DSTS 0 Res. 0x808 OTG_ DCTL Res. 0x804 OTG_ DCFG Res. 0x800 Res. OTG_ HCINT11 0 Res. 0x728 0 Res. . . . . Res. Reset value Res. . . . . Res. OTG_ HCTSIZ11 Res. 0x670 Res. . . . . Res. . . . . Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OTG_ HCINTMSK11 Res. 0x66C Res. Register Res. Offset Res. RM0351 USB on-the-go full-speed (OTG_FS) Table 259. OTG_FS register map and reset values (continued) 0 0 0 0 0 0 0 IEPINT IEPM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1581/1680 1635 OTG_ DIEPCTL2 EPDIS SODDFRM SD0PID/SEVNFRM SNAK CNAK 0x940 EPENA . . . . 1582/1680 Reset value 0 0 0 0 0 0 0 0 0 TXFNUM 0 0 0 OTG_ DIEPINT1 0 0 0 0 0 0 0 0 0 . . . . 0 0 DocID024597 Rev 1 0 Reset value . . . . 0 0 0 0 PKTCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 0 0 0 1 0 Res. Reset value 0 0 0 0 0 0 0 0 0 XFRSIZ 1 0 0 0 INEPTFSAV 0 0 0 0 0 0 0 0 0 MPSIZ 0 0 XFRC 1 TOC 0 0 0 0 0 0 1 Res. Res. Res. Res. Res. Res. MPSIZ 0 XFRC 0 EPDISD Res. ITTXFE Res. INEPNE 0 Res. 1 EPDISD 0 TXFE Reset value Res. 0 Res. 1 1 TOC 1 Res. 0 Res. 0 Res. Res. 0 Res. 1 ITTXFE 0 Res. 0 Res. 1 1 INEPNE 0 1 TXFE 0 Res. 0 Res. 0 Res. Res. 0 Res. Res. 0 Res. 0 0 Res. 0 Res. 0 Res. Res. Res. Res. 1 Res. Res. 0 USBAEP Res. Res. Res. 0 Res. Res. Res. Res. Res. NAKSTS EPTYP Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. STALL Res. Res. Res. 0 0 Res. Reset value Res. 0 Res. Res. Res. Res. 0 Res. USBAEP 0 Res. Res. Res. Res. Res. Res. 0 Res. EONUM/DPID 0 Res. 0 Res. PKT CNT Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. NAKSTS 0 Res. EPTYP 0 Res. Res. Res. Reset value 0 Res. 0 Res. 0 TXFNUM STALL Res. 0 Res. 0 Res. 0 Res. Res. Res. 0 Res. Reset value Res. 0 Res. 0 Res. Res. Res. 0 Res. Res. Reset value Res. 0 Res. 0 Res. Res. Res. CNAK 0 Res. 0 Res. Res. Res. SNAK 0 Res. Res. Res. Res. Res. Reset value USBAEP 0 Res. 0 Res. Res. Res. Res. 0 EONUM/DPID 0 Res. CNAK 0 Res. Res. Res. Res. Res. Res. Res. 0 NAKSTS 0 Res. SNAK 0 Res. Res. Res. OTG_ DIEPINT0 Res. EPDIS 0 Res. EPENA 0 EPTYP 0 Res. SD0PID/SEVNFRM 0 Res. Res. Res. Reset value TXFNUM Res. 0 Res. SODDFRM/SD1PID Reset value Res. Res. OTG_ DIEPCTL0 STALL 0x938 OTG_ DTXFSTS1 Res. Reset value Res. OTG_ DIEPTSIZ1 Res. 0x930 Res. 0x918 OTG_ DTXFSTS0 Res. 0x910 OTG_ DIEPTSIZ0 MCNT EPDIS 0x908 Res. EPENA 0x928 OTG_ DIEPCTL1 Res. 0x920 Res. 0x900 Res. 0x834 OTG_DIE PEMPMSK Res. 0x82C OTG_DVB USPULSE Res. Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x828 OTG_ DVBUSDIS Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Offset Res. USB on-the-go full-speed (OTG_FS) RM0351 Table 259. OTG_FS register map and reset values (continued) VBUSDT DVBUSP INEPTXFEM 1 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 XFRSIZ INEPTFSAV 0 0 0 0 0 0 0 0 0 0 0 0 MPSIZ 0 0 0 0 0 0 0 0 0 0 0 0 0 SNAK CNAK Reset value 0 0 0 0 0 0 0 0 0 0 DocID024597 Rev 1 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 MPSIZ 0 XFRC 0 EPDISD 0 Res. TOC 0 XFRC 0 Res. 0 EPDISD 0 Res. 0 ITTXFE 0 Res. INEPNE 0 0 Res. 0 Res. Res. 1 STUP 0 Res. 0 OTEPDIS 0 Res. 0 TXFE Res. 0 Res. 0 B2BSTUP 0 Res. 1 Reserved 0 Res. Reset value Res. 0 Res. USBAEP Res. Res. Res. Res. NAKSTS EPTYP Res. EONUM/DPID Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. . . . . 0 Res. 0 Res. 0 Res. 0 Res. PKTCNT Res. Res. 0 Res. 0 Res. Res. Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. 0 USBAEP 0 Res. 0 Res. 0 Res. Res. 0 NAKSTS Res. Res. STALL 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Reset value Res. 0 Res. Res. Res. Res. Res. 0 Res. USBAEP 0 Res. 0 Res. 0 Res. SNPM 0 EPTYP STALL 0 Res. Res. Res. Res. 0 NAKSTS 0 Res. Res. Res. SNAK CNAK 0 EONUM/DPID 0 Res. 0 EPTYP 0 Res. Res. Res. 0 PKTCNT Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. 0 0 Res. 0 0 0 SNPM 0 Res. SODDFRM SD0PID/SEVNFRM 0 TXFNUM STALL 0 Res. Res. EPDIS 0 0 Res. 0 SNAK 0 CNAK 0 Res. 0 Res. OTG_ DOEPINT0 Res. EPENA Reset value 0 Res. 0 Res. 0 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OTG_ DIEPCTL5 0 Res. Reset value Res. Res. 0x9A0 0 Res. OTG_ DOEPTSIZ0 Res. Register 0 Res. Reset value Res. OTG_ DIEPTSIZ5 Res. 0x9B0 Res. . . . . Res. . . . . Res. OTG_ DTXFSTS5 Res. 0x9B8 MCNT . . . . Res. . . . . Res. OTG_ DIEPINT5 Res. 0x9A8 Res. EPDIS . . . . STUPCNT EPENA Reset value Res. Offset 0 Res. OTG_ DOEPCTL1 SD0PID/SEVNFRM 0xB20 SODDFRM 0xB10 OTG_ DOEPCTL0 Res. . . . . Res. 0xB08 EPDIS 0xB00 EPENA RM0351 USB on-the-go full-speed (OTG_FS) Table 259. OTG_FS register map and reset values (continued) MPSIZ . . . . 0 0 INEPTFSAV . . . . XFRSIZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFRSIZ MPSIZ 0 0 0 0 0 0 0 0 1583/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 0 0 XFRC Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 Res. 0 B2BSTUP 0 Reserved 0 Res. 0 MPSIZ Res. 0 0 XFRC 0 EPDISD STUP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTEPDIS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SUSP PHYSLEEP ENL1GTG PHYSUSP Res. Res. GATEHCLK STPPCLK XFRSIZ Res. PKTCNT 0 0 0 0 0 0 Reset value Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. 1584/1680 EPDISD STUP Res. OTEPDIS 0 Res. OTG_ PCGCCTL Res. Reset value 0xE00 0 . . . . Res. OTG_ DOEPTSIZ5 0 Res. 0 EONUM/DPID 0 NAKSTS SNPM 0 EPTYP STALL 0 Res. 0 Res. 0 Res. 0 RXDPID/ STUPCNT 0xBB0 0 Res. . . . . B2BSTUP Res. 0 Reset value . . . . 0 XFRSIZ Res. 0 0 . . . . Res. OTG_ DOEPINT5 0 0 . . . . Res. 0xBA8 0 Res. 0 0 CNAK 0 . . . . 0 PKTCNT SNAK Reset value . . . . 0 SODDFRM OTG_ DOEPCTL5 0 0 SD0PID/SEVNFRM 0xBA0 EPDIS 0 . . . . EPENA Reset value 0 Res. OTG_ DOEPTSIZ2 . . . . 0 0 XFRSIZ Res. 0 PKTCNT USBAEP Res. Reset value Res. 0xB50 OTG_ DOEPTSIZ1 RXDPID/ STUPCNT 0xB30 RXDPID/ STUPCNT Reset value Reserved Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTG_ DOEPINT1 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0xB28 Res. Register Res. Offset Res. Table 259. OTG_FS register map and reset values (continued) DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) 43.16 OTG_FS programming model 43.16.1 Core initialization The application must perform the core initialization sequence. If the cable is connected during power-up, the current mode of operation bit in the OTG_GINTSTS (CMOD bit in OTG_GINTSTS) reflects the mode. The OTG_FS controller enters host mode when an “A” plug is connected or device mode when a “B” plug is connected. This section explains the initialization of the OTG_FS controller after power-on. The application must follow the initialization sequence irrespective of host or device mode operation. All core global registers are initialized according to the core’s configuration: 1. 2. 3. Program the following fields in the OTG_GAHBCFG register: – Global interrupt mask bit GINTMSK = 1 – Rx FIFO non-empty (RXFLVL bit in OTG_GINTSTS) – Periodic Tx FIFO empty level Program the following fields in the OTG_GUSBCFG register: – HNP capable bit – SRP capable bit – OTG_FS timeout calibration field – USB turnaround time field The software must unmask the following bits in the OTG_GINTMSK register: OTG interrupt mask Mode mismatch interrupt mask 4. The software can read the CMOD bit in OTG_GINTSTS to determine whether the OTG_FS controller is operating in host or device mode. DocID024597 Rev 1 1585/1680 1635 USB on-the-go full-speed (OTG_FS) 43.16.2 RM0351 Host initialization To initialize the core as host, the application must perform the following steps: 1. Program the HPRTINT in the OTG_GINTMSK register to unmask 2. Program the OTG_HCFG register to select full-speed host 3. Program the PPWR bit in OTG_HPRT to 1. This drives VBUS on the USB. 4. Wait for the PCDET interrupt in OTG_HPRT0. This indicates that a device is connecting to the port. 5. Program the PRST bit in OTG_HPRT to 1. This starts the reset process. 6. Wait at least 10 ms for the reset process to complete. 7. Program the PRST bit in OTG_HPRT to 0. 8. Wait for the PENCHNG interrupt in OTG_HPRT. 9. Read the PSPD bit in OTG_HPRT to get the enumerated speed. 10. Program the HFIR register with a value corresponding to the selected PHY clock 1 11. Program the FSLSPCS field in the OTG_HCFG register following the speed of the device detected in step 9. If FSLSPCS has been changed a port reset must be performed. 12. Program the OTG_GRXFSIZ register to select the size of the receive FIFO. 13. Program the OTG_HNPTXFSIZ register to select the size and the start address of the Non-periodic transmit FIFO for non-periodic transactions. 14. Program the OTG_HPTXFSIZ register to select the size and start address of the periodic transmit FIFO for periodic transactions. To communicate with devices, the system software must initialize and enable at least one channel. 43.16.3 Device initialization The application must perform the following steps to initialize the core as a device on powerup or after a mode change from host to device. 1. 2. Program the following fields in the OTG_DCFG register: – Device speed – Non-zero-length status OUT handshake Program the OTG_GINTMSK register to unmask the following interrupts: – USB reset – Enumeration done – Early suspend – USB suspend – SOF 3. Program the VBUSBSEN bit in the OTG_GCCFG register to enable VBUS sensing in “B” device mode and supply the 5 volts across the pull-up resistor on the DP line. 4. Wait for the USBRST interrupt in OTG_GINTSTS. It indicates that a reset has been detected on the USB that lasts for about 10 ms on receiving this interrupt. Wait for the ENUMDNE interrupt in OTG_GINTSTS. This interrupt indicates the end of reset on the USB. On receiving this interrupt, the application must read the OTG_DSTS register 1586/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) to determine the enumeration speed and perform the steps listed in Endpoint initialization on enumeration completion on page 1608. At this point, the device is ready to accept SOF packets and perform control transfers on control endpoint 0. 43.16.4 Host programming model Channel initialization The application must initialize one or more channels before it can communicate with connected devices. To initialize and enable a channel, the application must perform the following steps: 1. Program the OTG_GINTMSK register to unmask the following: 2. Channel interrupt – Non-periodic transmit FIFO empty for OUT transactions (applicable when operating in pipelined transaction-level with the packet count field programmed with more than one). – Non-periodic transmit FIFO half-empty for OUT transactions (applicable when operating in pipelined transaction-level with the packet count field programmed with more than one). 3. Program the OTG_HAINTMSK register to unmask the selected channels’ interrupts. 4. Program the OTG_HCINTMSK register to unmask the transaction-related interrupts of interest given in the host channel interrupt register. 5. Program the selected channel’s OTG_HCTSIZx register with the total transfer size, in bytes, and the expected number of packets, including short packets. The application must program the PID field with the initial data PID (to be used on the first OUT transaction or to be expected from the first IN transaction). 6. Program the OTG_HCCHARx register of the selected channel with the device’s endpoint characteristics, such as type, speed, direction, and so forth. (The channel can be enabled by setting the channel enable bit to 1 only when the application is ready to transmit or receive any packet). Halting a channel The application can disable any channel by programming the OTG_HCCHARx register with the CHDIS and CHENA bits set to 1. This enables the OTG_FS host to flush the posted requests (if any) and generates a channel halted interrupt. The application must wait for the CHH interrupt in OTG_HCINTx before reallocating the channel for other transactions. The OTG_FS host does not interrupt the transaction that has already been started on the USB. Before disabling a channel, the application must ensure that there is at least one free space available in the non-periodic request queue (when disabling a non-periodic channel) or the periodic request queue (when disabling a periodic channel). The application can simply flush the posted requests when the Request queue is full (before disabling the channel), by programming the OTG_HCCHARx register with the CHDIS bit set to 1, and the CHENA bit cleared to 0. The application is expected to disable a channel on any of the following conditions: DocID024597 Rev 1 1587/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 1. When an STALL, TXERR, BBERR or DTERR interrupt in OTG_HCINTx is received for an IN or OUT channel. The application must be able to receive other interrupts (DTERR, Nak, Data, TXERR) for the same channel before receiving the halt. 2. When a DISCINT (Disconnect Device) interrupt in OTG_GINTSTS is received. (The application is expected to disable all enabled channels). 3. When the application aborts a transfer before normal completion. Operational model The application must initialize a channel before communicating to the connected device. This section explains the sequence of operation to be performed for different types of USB transactions. • Writing the transmit FIFO The OTG_FS host automatically writes an entry (OUT request) to the periodic/nonperiodic request queue, along with the last DWORD write of a packet. The application must ensure that at least one free space is available in the periodic/non-periodic request queue before starting to write to the transmit FIFO. The application must always write to the transmit FIFO in DWORDs. If the packet size is non-DWORD aligned, the application must use padding. The OTG_FS host determines the actual packet size based on the programmed maximum packet size and transfer size. Figure 497. Transmit FIFO write task ^ƚĂƌƚ 5HDG27*B+37;67627*B+137;676 UHJLVWHUVIRUDYDLODEOH),)2DQGTXHXH VSDFHV :DLWIRU137;)(37;)(LQWHUUXSWLQ 27*B*,17676 1R ϭDW^ Žƌ>W^&/&KƐƉĂĐĞ ĂǀĂŝůĂďůĞ͍ ZRUGBFQWB@ UGBU[ILIR UGBGDWD(3180 ZRUGBFQW ZRUGBFQW %&17>@ %&17>@_%&17>@ DLE SETUP transactions This section describes how the core handles SETUP packets and the application’s sequence for handling SETUP transactions. • Application requirements 1. To receive a SETUP packet, the STUPCNT field (OTG_DOEPTSIZx) in a control OUT endpoint must be programmed to a non-zero value. When the application programs the STUPCNT field to a non-zero value, the core receives SETUP packets and writes them to the receive FIFO, irrespective of the NAK status and EPENA bit setting in OTG_DOEPCTLx. The STUPCNT field is decremented every time the control endpoint receives a SETUP packet. If the STUPCNT field is not programmed to a proper value before receiving a SETUP packet, the core still receives the SETUP packet and DocID024597 Rev 1 1611/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 decrements the STUPCNT field, but the application may not be able to determine the correct number of SETUP packets received in the Setup stage of a control transfer. – 2. The application must always allocate some extra space in the Receive data FIFO, to be able to receive up to three SETUP packets on a control endpoint. – The space to be reserved is 10 Words. Three Words are required for the first SETUP packet, 1 Word is required for the Setup stage done Word and 6 Words are required to store two extra SETUP packets among all control endpoints. – 3 Words per SETUP packet are required to store 8 bytes of SETUP data and 4 bytes of SETUP status (Setup packet pattern). The core reserves this space in the receive data. – FIFO to write SETUP data only, and never uses this space for data packets. 3. The application must read the 2 Words of the SETUP packet from the receive FIFO. 4. The application must read and discard the Setup stage done Word from the receive FIFO. • Internal data flow 1. When a SETUP packet is received, the core writes the received data to the receive FIFO, without checking for available space in the receive FIFO and irrespective of the endpoint’s NAK and STALL bit settings. – 2. The core internally sets the IN NAK and OUT NAK bits for the control IN/OUT endpoints on which the SETUP packet was received. For every SETUP packet received on the USB, 3 Words of data are written to the receive FIFO, and the STUPCNT field is decremented by 1. – The first Word contains control information used internally by the core – The second Word contains the first 4 bytes of the SETUP command – The third Word contains the last 4 bytes of the SETUP command 3. When the Setup stage changes to a Data IN/OUT stage, the core writes an entry (Setup stage done Word) to the receive FIFO, indicating the completion of the Setup stage. 4. On the AHB side, SETUP packets are emptied by the application. 5. When the application pops the Setup stage done Word from the receive FIFO, the core interrupts the application with an STUP interrupt (OTG_DOEPINTx), indicating it can process the received SETUP packet. 6. The core clears the endpoint enable bit for control OUT endpoints. • Application programming sequence 1. Program the OTG_DOEPTSIZx register. – STUPCNT = 3 2. Wait for the RXFLVL interrupt (OTG_GINTSTS) and empty the data packets from the receive FIFO. 3. Assertion of the STUP interrupt (OTG_DOEPINTx) marks a successful completion of the SETUP Data Transfer. – 1612/1680 STUPCNT = 3 in OTG_DOEPTSIZx On this interrupt, the application must read the OTG_DOEPTSIZx register to determine the number of SETUP packets received and process the last received SETUP packet. DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Figure 506. Processing a SETUP packet :DLWIRU673LQ27*B'2(3,17[ UHPBVXSFQW UGBUHJ 27*B'2(376,=[ VHWXSBFPG> PHP>± UHPBVXSFQW@ VHWXSBFPG>@ PHP>± UHPBVXSFQW@ )LQGVHWXSFPGW\SH 5HDG FWUOBUGZUVWDJH :ULWH VWDJH VHWXSBQSBLQBSNW 'DWD,1SKDVH VHWXSBQSBLQBSNW 6WDWXV,1SKDVH UFYBRXWBSNW 'DWD287SKDVH 06Y9 • Handling more than three back-to-back SETUP packets Per the USB 2.0 specification, normally, during a SETUP packet error, a host does not send more than three back-to-back SETUP packets to the same endpoint. However, the USB 2.0 specification does not limit the number of back-to-back SETUP packets a host can send to the same endpoint. When this condition occurs, the OTG_FS controller generates an interrupt (B2BSTUP in OTG_DOEPINTx). • Setting the global OUT NAK Internal data flow: 1. When the application sets the Global OUT NAK (SGONAK bit in OTG_DCTL), the core stops writing data, except SETUP packets, to the receive FIFO. Irrespective of the space availability in the receive FIFO, non-isochronous OUT tokens receive a NAK handshake response, and the core ignores isochronous OUT data packets 2. The core writes the Global OUT NAK pattern to the receive FIFO. The application must reserve enough receive FIFO space to write this data pattern. 3. When the application pops the Global OUT NAK pattern Word from the receive FIFO, the core sets the GONAKEFF interrupt (OTG_GINTSTS). 4. Once the application detects this interrupt, it can assume that the core is in Global OUT NAK mode. The application can clear this interrupt by clearing the SGONAK bit in OTG_DCTL. Application programming sequence: DocID024597 Rev 1 1613/1680 1635 USB on-the-go full-speed (OTG_FS) 1. RM0351 To stop receiving any kind of data in the receive FIFO, the application must set the Global OUT NAK bit by programming the following field: – SGONAK = 1 in OTG_DCTL 2. Wait for the assertion of the GONAKEFF interrupt in OTG_GINTSTS. When asserted, this interrupt indicates that the core has stopped receiving any type of data except SETUP packets. 3. The application can receive valid OUT packets after it has set SGONAK in OTG_DCTL and before the core asserts the GONAKEFF interrupt (OTG_GINTSTS). 4. The application can temporarily mask this interrupt by writing to the GONAKEFFM bit in the OTG_GINTMSK register. – 5. Whenever the application is ready to exit the Global OUT NAK mode, it must clear the SGONAK bit in OTG_DCTL. This also clears the GONAKEFF interrupt (OTG_GINTSTS). – 6. CGONAK = 1 in OTG_DCTL If the application has masked this interrupt earlier, it must be unmasked as follows: – • GONAKEFFM = 0 in the OTG_GINTMSK register GONAKEFFM = 1 in OTG_GINTMSK Disabling an OUT endpoint The application must use this sequence to disable an OUT endpoint that it has enabled. Application programming sequence: 1. Before disabling any OUT endpoint, the application must enable Global OUT NAK mode in the core. – SGONAK = 1 in OTG_DCTL 2. Wait for the GONAKEFF interrupt (OTG_GINTSTS) 3. Disable the required OUT endpoint by programming the following fields: 4. 5. – EPDIS = 1 in OTG_DOEPCTLx – SNAK = 1 in OTG_DOEPCTLx Wait for the EPDISD interrupt (OTG_DOEPINTx), which indicates that the OUT endpoint is completely disabled. When the EPDISD interrupt is asserted, the core also clears the following bits: – EPDIS = 0 in OTG_DOEPCTLx – EPENA = 0 in OTG_DOEPCTLx The application must clear the Global OUT NAK bit to start receiving data from other non-disabled OUT endpoints. – • SGONAK = 0 in OTG_DCTL Generic non-isochronous OUT data transfers This section describes a regular non-isochronous OUT data transfer (control, bulk, or interrupt). Application requirements: 1614/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) 1. Before setting up an OUT transfer, the application must allocate a buffer in the memory to accommodate all data to be received as part of the OUT transfer. 2. For OUT transfers, the transfer size field in the endpoint’s transfer size register must be a multiple of the maximum packet size of the endpoint, adjusted to the Word boundary. 3. – transfer size[EPNUM] = n × (MPSIZ[EPNUM] + 4 – (MPSIZ[EPNUM] mod 4)) – packet count[EPNUM] = n – n>0 On any OUT endpoint interrupt, the application must read the endpoint’s transfer size register to calculate the size of the payload in the memory. The received payload size can be less than the programmed transfer size. – Payload size in memory = application programmed initial transfer size – core updated final transfer size – Number of USB packets in which this payload was received = application programmed initial packet count – core updated final packet count Internal data flow: 1. The application must set the transfer size and packet count fields in the endpointspecific registers, clear the NAK bit, and enable the endpoint to receive the data. 2. Once the NAK bit is cleared, the core starts receiving data and writes it to the receive FIFO, as long as there is space in the receive FIFO. For every data packet received on the USB, the data packet and its status are written to the receive FIFO. Every packet (maximum packet size or short packet) written to the receive FIFO decrements the packet count field for that endpoint by 1. 3. – OUT data packets received with bad data CRC are flushed from the receive FIFO automatically. – After sending an ACK for the packet on the USB, the core discards nonisochronous OUT data packets that the host, which cannot detect the ACK, resends. The application does not detect multiple back-to-back data OUT packets on the same endpoint with the same data PID. In this case the packet count is not decremented. – If there is no space in the receive FIFO, isochronous or non-isochronous data packets are ignored and not written to the receive FIFO. Additionally, nonisochronous OUT tokens receive a NAK handshake reply. – In all the above three cases, the packet count is not decremented because no data are written to the receive FIFO. When the packet count becomes 0 or when a short packet is received on the endpoint, the NAK bit for that endpoint is set. Once the NAK bit is set, the isochronous or non- DocID024597 Rev 1 1615/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 isochronous data packets are ignored and not written to the receive FIFO, and nonisochronous OUT tokens receive a NAK handshake reply. 4. After the data are written to the receive FIFO, the application reads the data from the receive FIFO and writes it to external memory, one packet at a time per endpoint. 5. At the end of every packet write on the AHB to external memory, the transfer size for the endpoint is decremented by the size of the written packet. 6. The OUT data transfer completed pattern for an OUT endpoint is written to the receive FIFO on one of the following conditions: 7. – The transfer size is 0 and the packet count is 0 – The last OUT data packet written to the receive FIFO is a short packet (0 ≤ packet size < maximum packet size) When either the application pops this entry (OUT data transfer completed), a transfer completed interrupt is generated for the endpoint and the endpoint enable is cleared. Application programming sequence: 1. Program the OTG_DOEPTSIZx register for the transfer size and the corresponding packet count. 2. Program the OTG_DOEPCTLx register with the endpoint characteristics, and set the EPENA and CNAK bits. 3. – EPENA = 1 in OTG_DOEPCTLx – CNAK = 1 in OTG_DOEPCTLx Wait for the RXFLVL interrupt (in OTG_GINTSTS) and empty the data packets from the receive FIFO. – This step can be repeated many times, depending on the transfer size. 4. Asserting the XFRC interrupt (OTG_DOEPINTx) marks a successful completion of the non-isochronous OUT data transfer. 5. Read the OTG_DOEPTSIZx register to determine the size of the received data payload. • Generic isochronous OUT data transfer This section describes a regular isochronous OUT data transfer. Application requirements: 1. All the application requirements for non-isochronous OUT data transfers also apply to isochronous OUT data transfers. 2. For isochronous OUT data transfers, the transfer size and packet count fields must always be set to the number of maximum-packet-size packets that can be received in a single frame and no more. Isochronous OUT data transfers cannot span more than 1 frame. 3. The application must read all isochronous OUT data packets from the receive FIFO (data and status) before the end of the periodic frame (EOPF interrupt in OTG_GINTSTS). 4. To receive data in the following frame, an isochronous OUT endpoint must be enabled after the EOPF (OTG_GINTSTS) and before the SOF (OTG_GINTSTS). Internal data flow: 1616/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) 1. The internal data flow for isochronous OUT endpoints is the same as that for nonisochronous OUT endpoints, but for a few differences. 2. When an isochronous OUT endpoint is enabled by setting the Endpoint Enable and clearing the NAK bits, the Even/Odd frame bit must also be set appropriately. The core receives data on an isochronous OUT endpoint in a particular frame only if the following condition is met: – 3. EONUM (in OTG_DOEPCTLx) = FNSOF[0] (in OTG_DSTS) When the application completely reads an isochronous OUT data packet (data and status) from the receive FIFO, the core updates the RXDPID field in OTG_DOEPTSIZx with the data PID of the last isochronous OUT data packet read from the receive FIFO. Application programming sequence: 1. Program the OTG_DOEPTSIZx register for the transfer size and the corresponding packet count 2. Program the OTG_DOEPCTLx register with the endpoint characteristics and set the Endpoint Enable, ClearNAK, and Even/Odd frame bits. 3. – EPENA = 1 – CNAK = 1 – EONUM = (0: Even/1: Odd) Wait for the RXFLVL interrupt (in OTG_GINTSTS) and empty the data packets from the receive FIFO – This step can be repeated many times, depending on the transfer size. 4. The assertion of the XFRC interrupt (in OTG_DOEPINTx) marks the completion of the isochronous OUT data transfer. This interrupt does not necessarily mean that the data in memory are good. 5. This interrupt cannot always be detected for isochronous OUT transfers. Instead, the application can detect the INCOMPISOOUT interrupt in OTG_GINTSTS. 6. Read the OTG_DOEPTSIZx register to determine the size of the received transfer and to determine the validity of the data received in the frame. The application must treat the data received in memory as valid only if one of the following conditions is met: – RXDPID = DATA0 (in OTG_DOEPTSIZx) and the number of USB packets in which this payload was received = 1 – RXDPID = DATA1 (in OTG_DOEPTSIZx) and the number of USB packets in which this payload was received = 2 The number of USB packets in which this payload was received = Application programmed initial packet count – Core updated final packet count The application can discard invalid data packets. • Incomplete isochronous OUT data transfers This section describes the application programming sequence when isochronous OUT data packets are dropped inside the core. Internal data flow: 1. For isochronous OUT endpoints, the XFRC interrupt (in OTG_DOEPINTx) may not always be asserted. If the core drops isochronous OUT data packets, the application DocID024597 Rev 1 1617/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 could fail to detect the XFRC interrupt (OTG_DOEPINTx) under the following circumstances: 2. – When the receive FIFO cannot accommodate the complete ISO OUT data packet, the core drops the received ISO OUT data – When the isochronous OUT data packet is received with CRC errors – When the isochronous OUT token received by the core is corrupted – When the application is very slow in reading the data from the receive FIFO When the core detects an end of periodic frame before transfer completion to all isochronous OUT endpoints, it asserts the incomplete Isochronous OUT data interrupt (INCOMPISOOUT in OTG_GINTSTS), indicating that an XFRC interrupt (in OTG_DOEPINTx) is not asserted on at least one of the isochronous OUT endpoints. At this point, the endpoint with the incomplete transfer remains enabled, but no active transfers remain in progress on this endpoint on the USB. Application programming sequence: 1. Asserting the INCOMPISOOUT interrupt (OTG_GINTSTS) indicates that in the current frame, at least one isochronous OUT endpoint has an incomplete transfer. 2. If this occurs because isochronous OUT data is not completely emptied from the endpoint, the application must ensure that the application empties all isochronous OUT data (data and status) from the receive FIFO before proceeding. – 3. When all data are emptied from the receive FIFO, the application can detect the XFRC interrupt (OTG_DOEPINTx). In this case, the application must re-enable the endpoint to receive isochronous OUT data in the next frame. When it receives an INCOMPISOOUT interrupt (in OTG_GINTSTS), the application must read the control registers of all isochronous OUT endpoints (OTG_DOEPCTLx) to determine which endpoints had an incomplete transfer in the current microframe. An endpoint transfer is incomplete if both the following conditions are met: – EONUM bit (in OTG_DOEPCTLx) = FNSOF[0] (in OTG_DSTS) – EPENA = 1 (in OTG_DOEPCTLx) 4. The previous step must be performed before the SOF interrupt (in OTG_GINTSTS) is detected, to ensure that the current frame number is not changed. 5. For isochronous OUT endpoints with incomplete transfers, the application must discard the data in the memory and disable the endpoint by setting the EPDIS bit in OTG_DOEPCTLx. 6. Wait for the EPDISD interrupt (in OTG_DOEPINTx) and enable the endpoint to receive new data in the next frame. – • Because the core can take some time to disable the endpoint, the application may not be able to receive the data in the next frame after receiving bad isochronous data. Stalling a non-isochronous OUT endpoint This section describes how the application can stall a non-isochronous endpoint. 1618/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) 1. Put the core in the Global OUT NAK mode. 2. Disable the required endpoint – When disabling the endpoint, instead of setting the SNAK bit in OTG_DOEPCTL, set STALL = 1 (in OTG_DOEPCTL). The STALL bit always takes precedence over the NAK bit. 3. When the application is ready to end the STALL handshake for the endpoint, the STALL bit (in OTG_DOEPCTLx) must be cleared. 4. If the application is setting or clearing a STALL for an endpoint due to a SetFeature.Endpoint Halt or ClearFeature.Endpoint Halt command, the STALL bit must be set or cleared before the application sets up the Status stage transfer on the control endpoint. Examples This section describes and depicts some fundamental transfer types and scenarios. • Bulk OUT transaction Figure 507 depicts the reception of a single Bulk OUT Data packet from the USB to the AHB and describes the events involved in the process. Figure 507. Bulk OUT transaction +RVW 86% 'HYLFH $SSOLFDWLRQ LQLW BRXWBHS ;)56,= 3.7&17 E\WHV :UBUHJ 27*B'2(376,=[ 2 87 :UBUHJ 27*B'2(3&7/[ (3(1$ &1 $. E\WHV [DFWB $& . 5;)/9/ LLQWU (3&7/[ 1$. 3.7&1 7 27*B'2 ;)56,= U 28 7 1$ . LGOH XQWLO LQWU UFYBRXW BSNW ;) LQW U 5& 2Q QHZ [IHU RU 5[),)2 QRWHP SW\ LGOH XQWLO LQWU 069 After a SetConfiguration/SetInterface command, the application initializes all OUT endpoints by setting CNAK = 1 and EPENA = 1 (in OTG_DOEPCTLx), and setting a suitable XFRSIZ and PKTCNT in the OTG_DOEPTSIZx register. DocID024597 Rev 1 1619/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 1. host attempts to send data (OUT token) to an endpoint. 2. When the core receives the OUT token on the USB, it stores the packet in the Rx FIFO because space is available there. 3. After writing the complete packet in the Rx FIFO, the core then asserts the RXFLVL interrupt (in OTG_GINTSTS). 4. On receiving the PKTCNT number of USB packets, the core internally sets the NAK bit for this endpoint to prevent it from receiving any more packets. 5. The application processes the interrupt and reads the data from the Rx FIFO. 6. When the application has read all the data (equivalent to XFRSIZ), the core generates an XFRC interrupt (in OTG_DOEPINTx). 7. The application processes the interrupt and uses the setting of the XFRC interrupt bit (in OTG_DOEPINTx) to determine that the intended transfer is complete. IN data transfers • Packet write This section describes how the application writes data packets to the endpoint FIFO when dedicated transmit FIFOs are enabled. 1. 2. The application can either choose the polling or the interrupt mode. – In polling mode, the application monitors the status of the endpoint transmit data FIFO by reading the OTG_DTXFSTSx register, to determine if there is enough space in the data FIFO. – In interrupt mode, the application waits for the TXFE interrupt (in OTG_DIEPINTx) and then reads the OTG_DTXFSTSx register, to determine if there is enough space in the data FIFO. – To write a single non-zero length data packet, there must be space to write the entire packet in the data FIFO. – To write zero length packet, the application must not look at the FIFO space. Using one of the above mentioned methods, when the application determines that there is enough space to write a transmit packet, the application must first write into the endpoint control register, before writing the data into the data FIFO. Typically, the application, must do a read modify write on the OTG_DIEPCTLx register to avoid modifying the contents of the register, except for setting the Endpoint Enable bit. The application can write multiple packets for the same endpoint into the transmit FIFO, if space is available. For periodic IN endpoints, the application must write packets only for one microframe. It can write packets for the next periodic transaction only after getting transfer complete for the previous transaction. • Setting IN endpoint NAK Internal data flow: 1620/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) 1. When the application sets the IN NAK for a particular endpoint, the core stops transmitting data on the endpoint, irrespective of data availability in the endpoint’s transmit FIFO. 2. Non-isochronous IN tokens receive a NAK handshake reply – Isochronous IN tokens receive a zero-data-length packet reply 3. The core asserts the INEPNE (IN endpoint NAK effective) interrupt in OTG_DIEPINTx in response to the SNAK bit in OTG_DIEPCTLx. 4. Once this interrupt is seen by the application, the application can assume that the endpoint is in IN NAK mode. This interrupt can be cleared by the application by setting the CNAK bit in OTG_DIEPCTLx. Application programming sequence: 1. To stop transmitting any data on a particular IN endpoint, the application must set the IN NAK bit. To set this bit, the following field must be programmed. – SNAK = 1 in OTG_DIEPCTLx 2. Wait for assertion of the INEPNE interrupt in OTG_DIEPINTx. This interrupt indicates that the core has stopped transmitting data on the endpoint. 3. The core can transmit valid IN data on the endpoint after the application has set the NAK bit, but before the assertion of the NAK Effective interrupt. 4. The application can mask this interrupt temporarily by writing to the INEPNEM bit in OTG_DIEPMSK. – 5. To exit Endpoint NAK mode, the application must clear the NAK status bit (NAKSTS) in OTG_DIEPCTLx. This also clears the INEPNE interrupt (in OTG_DIEPINTx). – 6. CNAK = 1 in OTG_DIEPCTLx If the application masked this interrupt earlier, it must be unmasked as follows: – • INEPNEM = 0 in OTG_DIEPMSK INEPNEM = 1 in OTG_DIEPMSK IN endpoint disable Use the following sequence to disable a specific IN endpoint that has been previously enabled. Application programming sequence: DocID024597 Rev 1 1621/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 1. The application must stop writing data on the AHB for the IN endpoint to be disabled. 2. The application must set the endpoint in NAK mode. – SNAK = 1 in OTG_DIEPCTLx 3. Wait for the INEPNE interrupt in OTG_DIEPINTx. 4. Set the following bits in the OTG_DIEPCTLx register for the endpoint that must be disabled. 5. – EPDIS = 1 in OTG_DIEPCTLx – SNAK = 1 in OTG_DIEPCTLx Assertion of the EPDISD interrupt in OTG_DIEPINTx indicates that the core has completely disabled the specified endpoint. Along with the assertion of the interrupt, the core also clears the following bits: – EPENA = 0 in OTG_DIEPCTLx – EPDIS = 0 in OTG_DIEPCTLx 6. The application must read the OTG_DIEPTSIZx register for the periodic IN EP, to calculate how much data on the endpoint were transmitted on the USB. 7. The application must flush the data in the Endpoint transmit FIFO, by setting the following fields in the OTG_GRSTCTL register: – TXFNUM (in OTG_GRSTCTL) = Endpoint transmit FIFO number – TXFFLSH in (OTG_GRSTCTL) = 1 The application must poll the OTG_GRSTCTL register, until the TXFFLSH bit is cleared by the core, which indicates the end of flush operation. To transmit new data on this endpoint, the application can re-enable the endpoint at a later point. 1622/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) • Generic non-periodic IN data transfers Application requirements: 1. Before setting up an IN transfer, the application must ensure that all data to be transmitted as part of the IN transfer are part of a single buffer. 2. For IN transfers, the Transfer Size field in the Endpoint Transfer Size register denotes a payload that constitutes multiple maximum-packet-size packets and a single short packet. This short packet is transmitted at the end of the transfer. – To transmit a few maximum-packet-size packets and a short packet at the end of the transfer: Transfer size[EPNUM] = x × MPSIZ[EPNUM] + sp If (sp > 0), then packet count[EPNUM] = x + 1. Otherwise, packet count[EPNUM] = x – To transmit a single zero-length data packet: Transfer size[EPNUM] = 0 Packet count[EPNUM] = 1 – To transmit a few maximum-packet-size packets and a zero-length data packet at the end of the transfer, the application must split the transfer into two parts. The first sends maximum-packet-size data packets and the second sends the zerolength data packet alone. First transfer: transfer size[EPNUM] = x × MPSIZ[epnum]; packet count = n; Second transfer: transfer size[EPNUM] = 0; packet count = 1; 3. Once an endpoint is enabled for data transfers, the core updates the Transfer size register. At the end of the IN transfer, the application must read the Transfer size register to determine how much data posted in the transmit FIFO have already been sent on the USB. 4. Data fetched into transmit FIFO = Application-programmed initial transfer size – coreupdated final transfer size – Data transmitted on USB = (application-programmed initial packet count – Core updated final packet count) × MPSIZ[EPNUM] – Data yet to be transmitted on USB = (Application-programmed initial transfer size – data transmitted on USB) Internal data flow: 1. The application must set the transfer size and packet count fields in the endpointspecific registers and enable the endpoint to transmit the data. 2. The application must also write the required data to the transmit FIFO for the endpoint. 3. Every time a packet is written into the transmit FIFO by the application, the transfer size for that endpoint is decremented by the packet size. The data is fetched from the memory by the application, until the transfer size for the endpoint becomes 0. After writing the data into the FIFO, the “number of packets in FIFO” count is incremented (this is a 3-bit count, internally maintained by the core for each IN endpoint transmit FIFO. The maximum number of packets maintained by the core at any time in an IN endpoint FIFO is eight). For zero-length packets, a separate flag is set for each FIFO, without any data in the FIFO. 4. Once the data are written to the transmit FIFO, the core reads them out upon receiving an IN token. For every non-isochronous IN data packet transmitted with an ACK DocID024597 Rev 1 1623/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 handshake, the packet count for the endpoint is decremented by one, until the packet count is zero. The packet count is not decremented on a timeout. 5. For zero length packets (indicated by an internal zero length flag), the core sends out a zero-length packet for the IN token and decrements the packet count field. 6. If there are no data in the FIFO for a received IN token and the packet count field for that endpoint is zero, the core generates an “IN token received when Tx FIFO is empty” (ITTXFE) Interrupt for the endpoint, provided that the endpoint NAK bit is not set. The core responds with a NAK handshake for non-isochronous endpoints on the USB. 7. The core internally rewinds the FIFO pointers and no timeout interrupt is generated. 8. When the transfer size is 0 and the packet count is 0, the transfer complete (XFRC) interrupt for the endpoint is generated and the endpoint enable is cleared. Application programming sequence: 1. Program the OTG_DIEPTSIZx register with the transfer size and corresponding packet count. 2. Program the OTG_DIEPCTLx register with the endpoint characteristics and set the CNAK and EPENA (Endpoint Enable) bits. 3. When transmitting non-zero length data packet, the application must poll the OTG_DTXFSTSx register (where x is the FIFO number associated with that endpoint) to determine whether there is enough space in the data FIFO. The application can optionally use TXFE (in OTG_DIEPINTx) before writing the data. • Generic periodic IN data transfers This section describes a typical periodic IN data transfer. Application requirements: 1. Application requirements 1, 2, 3, and 4 of Generic non-periodic IN data transfers on page 1623 also apply to periodic IN data transfers, except for a slight modification of requirement 2. – The application can only transmit multiples of maximum-packet-size data packets or multiples of maximum-packet-size packets, plus a short packet at the end. To transmit a few maximum-packet-size packets and a short packet at the end of the transfer, the following conditions must be met: transfer size[EPNUM] = x × MPSIZ[EPNUM] + sp (where x is an integer ≥ 0, and 0 ≤ sp < MPSIZ[EPNUM]) If (sp > 0), packet count[EPNUM] = x + 1 Otherwise, packet count[EPNUM] = x; MCNT[EPNUM] = packet count[EPNUM] – The application cannot transmit a zero-length data packet at the end of a transfer. It can transmit a single zero-length data packet by itself. To transmit a single zerolength data packet: – transfer size[EPNUM] = 0 packet count[EPNUM] = 1 MCNT[EPNUM] = packet count[EPNUM] 2. 1624/1680 The application can only schedule data transfers one frame at a time. – (MCNT – 1) × MPSIZ ≤ XFERSIZ ≤ MCNT × MPSIZ – PKTCNT = MCNT (in OTG_DIEPTSIZx) DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) 3. – If XFERSIZ < MCNT × MPSIZ, the last data packet of the transfer is a short packet. – Note that: MCNT is in OTG_DIEPTSIZx, MPSIZ is in OTG_DIEPCTLx, PKTCNT is in OTG_DIEPTSIZx and XFERSIZ is in OTG_DIEPTSIZx The complete data to be transmitted in the frame must be written into the transmit FIFO by the application, before the IN token is received. Even when 1 Word of the data to be transmitted per frame is missing in the transmit FIFO when the IN token is received, the core behaves as when the FIFO is empty. When the transmit FIFO is empty: – A zero data length packet would be transmitted on the USB for isochronous IN endpoints – A NAK handshake would be transmitted on the USB for interrupt IN endpoints Internal data flow: 1. The application must set the transfer size and packet count fields in the endpointspecific registers and enable the endpoint to transmit the data. 2. The application must also write the required data to the associated transmit FIFO for the endpoint. 3. Every time the application writes a packet to the transmit FIFO, the transfer size for that endpoint is decremented by the packet size. The data are fetched from application memory until the transfer size for the endpoint becomes 0. 4. When an IN token is received for a periodic endpoint, the core transmits the data in the FIFO, if available. If the complete data payload (complete packet, in dedicated FIFO mode) for the frame is not present in the FIFO, then the core generates an IN token received when Tx FIFO empty interrupt for the endpoint. 5. 6. – A zero-length data packet is transmitted on the USB for isochronous IN endpoints – A NAK handshake is transmitted on the USB for interrupt IN endpoints The packet count for the endpoint is decremented by 1 under the following conditions: – For isochronous endpoints, when a zero- or non-zero-length data packet is transmitted – For interrupt endpoints, when an ACK handshake is transmitted – When the transfer size and packet count are both 0, the transfer completed interrupt for the endpoint is generated and the endpoint enable is cleared. At the “Periodic frame Interval” (controlled by PFIVL in OTG_DCFG), when the core finds non-empty any of the isochronous IN endpoint FIFOs scheduled for the current frame non-empty, the core generates an IISOIXFR interrupt in OTG_GINTSTS. Application programming sequence: 1. Program the OTG_DIEPCTLx register with the endpoint characteristics and set the CNAK and EPENA bits. 2. Write the data to be transmitted in the next frame to the transmit FIFO. 3. Asserting the ITTXFE interrupt (in OTG_DIEPINTx) indicates that the application has not yet written all data to be transmitted to the transmit FIFO. 4. If the interrupt endpoint is already enabled when this interrupt is detected, ignore the interrupt. If it is not enabled, enable the endpoint so that the data can be transmitted on the next IN token attempt. 5. Asserting the XFRC interrupt (in OTG_DIEPINTx) with no ITTXFE interrupt in OTG_DIEPINTx indicates the successful completion of an isochronous IN transfer. A DocID024597 Rev 1 1625/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 read to the OTG_DIEPTSIZx register must give transfer size = 0 and packet count = 0, indicating all data were transmitted on the USB. 6. Asserting the XFRC interrupt (in OTG_DIEPINTx), with or without the ITTXFE interrupt (in OTG_DIEPINTx), indicates the successful completion of an interrupt IN transfer. A read to the OTG_DIEPTSIZx register must give transfer size = 0 and packet count = 0, indicating all data were transmitted on the USB. 7. Asserting the incomplete isochronous IN transfer (IISOIXFR) interrupt in OTG_GINTSTS with none of the aforementioned interrupts indicates the core did not receive at least 1 periodic IN token in the current frame. • Incomplete isochronous IN data transfers This section describes what the application must do on an incomplete isochronous IN data transfer. Internal data flow: 1. An isochronous IN transfer is treated as incomplete in one of the following conditions: a) The core receives a corrupted isochronous IN token on at least one isochronous IN endpoint. In this case, the application detects an incomplete isochronous IN transfer interrupt (IISOIXFR in OTG_GINTSTS). b) The application is slow to write the complete data payload to the transmit FIFO and an IN token is received before the complete data payload is written to the FIFO. In this case, the application detects an IN token received when Tx FIFO empty interrupt in OTG_DIEPINTx. The application can ignore this interrupt, as it eventually results in an incomplete isochronous IN transfer interrupt (IISOIXFR in OTG_GINTSTS) at the end of periodic frame. The core transmits a zero-length data packet on the USB in response to the received IN token. 2. The application must stop writing the data payload to the transmit FIFO as soon as possible. 3. The application must set the NAK bit and the disable bit for the endpoint. 4. The core disables the endpoint, clears the disable bit, and asserts the Endpoint Disable interrupt for the endpoint. Application programming sequence: 1. The application can ignore the IN token received when Tx FIFO empty interrupt in OTG_DIEPINTx on any isochronous IN endpoint, as it eventually results in an incomplete isochronous IN transfer interrupt (in OTG_GINTSTS). 2. Assertion of the incomplete isochronous IN transfer interrupt (in OTG_GINTSTS) indicates an incomplete isochronous IN transfer on at least one of the isochronous IN endpoints. 3. The application must read the Endpoint Control register for all isochronous IN endpoints to detect endpoints with incomplete IN data transfers. 4. The application must stop writing data to the Periodic Transmit FIFOs associated with these endpoints on the AHB. 5. 6. 1626/1680 Program the following fields in the OTG_DIEPCTLx register to disable the endpoint: – SNAK = 1 in OTG_DIEPCTLx – EPDIS = 1 in OTG_DIEPCTLx The assertion of the Endpoint Disabled interrupt in OTG_DIEPINTx indicates that the DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) core has disabled the endpoint. – • At this point, the application must flush the data in the associated transmit FIFO or overwrite the existing data in the FIFO by enabling the endpoint for a new transfer in the next microframe. To flush the data, the application must use the OTG_GRSTCTL register. Stalling non-isochronous IN endpoints This section describes how the application can stall a non-isochronous endpoint. Application programming sequence: 1. Disable the IN endpoint to be stalled. Set the STALL bit as well. 2. EPDIS = 1 in OTG_DIEPCTLx, when the endpoint is already enabled – STALL = 1 in OTG_DIEPCTLx – The STALL bit always takes precedence over the NAK bit 3. Assertion of the Endpoint Disabled interrupt (in OTG_DIEPINTx) indicates to the application that the core has disabled the specified endpoint. 4. The application must flush the non-periodic or periodic transmit FIFO, depending on the endpoint type. In case of a non-periodic endpoint, the application must re-enable the other non-periodic endpoints that do not need to be stalled, to transmit data. 5. Whenever the application is ready to end the STALL handshake for the endpoint, the STALL bit must be cleared in OTG_DIEPCTLx. 6. If the application sets or clears a STALL bit for an endpoint due to a SetFeature.Endpoint Halt command or ClearFeature.Endpoint Halt command, the STALL bit must be set or cleared before the application sets up the Status stage transfer on the control endpoint. Special case: stalling the control OUT endpoint The core must stall IN/OUT tokens if, during the data stage of a control transfer, the host sends more IN/OUT tokens than are specified in the SETUP packet. In this case, the application must enable the ITTXFE interrupt in OTG_DIEPINTx and the OTEPDIS interrupt in OTG_DOEPINTx during the data stage of the control transfer, after the core has transferred the amount of data specified in the SETUP packet. Then, when the application receives this interrupt, it must set the STALL bit in the corresponding endpoint control register, and clear this interrupt. 43.16.6 Worst case response time When the OTG_FS controller acts as a device, there is a worst case response time for any tokens that follow an isochronous OUT. This worst case response time depends on the AHB clock frequency. The core registers are in the AHB domain, and the core does not accept another token before updating these register values. The worst case is for any token following an isochronous OUT, because for an isochronous transaction, there is no handshake and the next token could come sooner. This worst case value is 7 PHY clocks when the AHB clock is the same as the PHY clock. When the AHB clock is faster, this value is smaller. If this worst case condition occurs, the core responds to bulk/interrupt tokens with a NAK and drops isochronous and SETUP tokens. The host interprets this as a timeout condition for SETUP and retries the SETUP packet. For isochronous transfers, the Incomplete DocID024597 Rev 1 1627/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 isochronous IN transfer interrupt (IISOIXFR) and Incomplete isochronous OUT transfer interrupt (IISOOXFR) inform the application that isochronous IN/OUT packets were dropped. Choosing the value of TRDT in OTG_GUSBCFG The value in TRDT (OTG_GUSBCFG) is the time it takes for the MAC, in terms of PHY clocks after it has received an IN token, to get the FIFO status, and thus the first data from the PFC block. This time involves the synchronization delay between the PHY and AHB clocks. The worst case delay for this is when the AHB clock is the same as the PHY clock. In this case, the delay is 5 clocks. Once the MAC receives an IN token, this information (token received) is synchronized to the AHB clock by the PFC (the PFC runs on the AHB clock). The PFC then reads the data from the SPRAM and writes them into the dual clock source buffer. The MAC then reads the data out of the source buffer (4 deep). If the AHB is running at a higher frequency than the PHY, the application can use a smaller value for TRDT (in OTG_GUSBCFG). Figure 508 has the following signals: • tkn_rcvd: Token received information from MAC to PFC • dynced_tkn_rcvd: Doubled sync tkn_rcvd, from PCLK to HCLK domain • spr_read: Read to SPRAM • spr_addr: Address to SPRAM • spr_rdata: Read data from SPRAM • srcbuf_push: Push to the source buffer • srcbuf_rdata: Read data from the source buffer. Data seen by MAC The application can use the following formula to calculate the value of TRDT: 4 × AHB clock + 1 PHY clock = (2 clock sync + 1 clock memory address + 1 clock memory data from sync RAM) + (1 PHY clock (next PHY clock MAC can sample the 2 clock FIFO outputs) 1628/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Figure 508. TRDT max timing case 0ns 1 50ns 2 100ns 3 4 150ns 5 6 200ns 7 8 HCLK PCLK tkn_rcvd dsynced_tkn_rcvd spr_read spr_addr A1 D1 spr_rdata srcbuf_push srcbuf_rdata D1 5 Clocks ai15680 43.16.7 OTG programming model The OTG_FS controller is an OTG device supporting HNP and SRP. When the core is connected to an “A” plug, it is referred to as an A-device. When the core is connected to a “B” plug it is referred to as a B-device. In host mode, the OTG_FS controller turns off VBUS to conserve power. SRP is a method by which the B-device signals the A-device to turn on VBUS power. A device must perform both data-line pulsing and VBUS pulsing, but a host can detect either data-line pulsing or VBUS pulsing for SRP. HNP is a method by which the Bdevice negotiates and switches to host role. In Negotiated mode after HNP, the B-device suspends the bus and reverts to the device role. A-device session request protocol The application must set the SRP-capable bit in the Core USB configuration register. This enables the OTG_FS controller to detect SRP as an A-device. DocID024597 Rev 1 1629/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Figure 509. A-device SRP Suspend DRV_VBUS 6 1 5 2 VBUS_VALID VBUS pulsing A_VALID 3 D+ D- 4 Data line pulsing 7 Connect Low ai15681 1. DRV_VBUS = VBUS drive signal to the PHY VBUS_VALID = VBUS valid signal from PHY A_VALID = A-peripheral VBUS level signal to PHY D+ = Data plus line D- = Data minus line 1. To save power, the application suspends and turns off port power when the bus is idle by writing the port suspend and port power bits in the host port control and status register. 2. PHY indicates port power off by deasserting the VBUS_VALID signal. 3. The device must detect SE0 for at least 2 ms to start SRP when VBUS power is off. 4. To initiate SRP, the device turns on its data line pull-up resistor for 5 to 10 ms. The OTG_FS controller detects data-line pulsing. 5. The device drives VBUS above the A-device session valid (2.0 V minimum) for VBUS pulsing. The OTG_FS controller interrupts the application on detecting SRP. The Session request detected bit is set in Global interrupt status register (SRQINT set in OTG_GINTSTS). 6. The application must service the Session request detected interrupt and turn on the port power bit by writing the port power bit in the host port control and status register. The PHY indicates port power-on by asserting the VBUS_VALID signal. 7. When the USB is powered, the device connects, completing the SRP process. B-device session request protocol The application must set the SRP-capable bit in the Core USB configuration register. This enables the OTG_FS controller to initiate SRP as a B-device. SRP is a means by which the OTG_FS controller can request a new session from the host. 1630/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) Figure 510. B-device SRP Suspend VBUS_VALID 6 1 2 B_VALID 3 DISCHRG_VBUS 4 SESS_END 5 DP 8 Data line pulsing DM Connect Low 7 VBUS pulsing CHRG_VBUS ai15682 1. VBUS_VALID = VBUS valid signal from PHY B_VALID = B-peripheral valid session to PHY DISCHRG_VBUS = discharge signal to PHY SESS_END = session end signal to PHY CHRG_VBUS = charge VBUS signal to PHY DP = Data plus line DM = Data minus line 1. To save power, the host suspends and turns off port power when the bus is idle. The OTG_FS controller sets the early suspend bit in the Core interrupt register after 3 ms of bus idleness. Following this, the OTG_FS controller sets the USB suspend bit in the Core interrupt register. The OTG_FS controller informs the PHY to discharge VBUS. 2. The PHY indicates the session’s end to the device. This is the initial condition for SRP. The OTG_FS controller requires 2 ms of SE0 before initiating SRP. For a USB 1.1 full-speed serial transceiver, the application must wait until VBUS discharges to 0.2 V after BSVLD (in OTG_GOTGCTL) is deasserted. This discharge time can be obtained from the transceiver vendor and varies from one transceiver to another. 3. The OTG_FS core informs the PHY to speed up VBUS discharge. 4. The application initiates SRP by writing the session request bit in the OTG Control and status register. The OTG_FS controller perform data-line pulsing followed by VBUS pulsing. 5. The host detects SRP from either the data-line or VBUS pulsing, and turns on VBUS. The PHY indicates VBUS power-on to the device. 6. The OTG_FS controller performs VBUS pulsing. The host starts a new session by turning on VBUS, indicating SRP success. The OTG_FS controller interrupts the application by setting the session request success DocID024597 Rev 1 1631/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 status change bit in the OTG interrupt status register. The application reads the session request success bit in the OTG control and status register. 7. When the USB is powered, the OTG_FS controller connects, completing the SRP process. A-device host negotiation protocol HNP switches the USB host role from the A-device to the B-device. The application must set the HNP-capable bit in the Core USB configuration register to enable the OTG_FS controller to perform HNP as an A-device. Figure 511. A-device HNP 1 OTG core Host Device Suspend 2 DP 4 3 Host 6 5 Reset DM Traffic 8 7 Connect Traffic DPPULLDOWN DMPULLDOWN ai15683 1. DPPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DP line inside the PHY. DMPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DM line inside the PHY. 1. 1632/1680 The OTG_FS controller sends the B-device a SetFeature b_hnp_enable descriptor to enable HNP support. The B-device’s ACK response indicates that the B-device supports HNP. The application must set host Set HNP Enable bit in the OTG Control DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) and status register to indicate to the OTG_FS controller that the B-device supports HNP. 2. When it has finished using the bus, the application suspends by writing the Port suspend bit in the host port control and status register. 3. When the B-device observes a USB suspend, it disconnects, indicating the initial condition for HNP. The B-device initiates HNP only when it must switch to the host role; otherwise, the bus continues to be suspended. The OTG_FS controller sets the host negotiation detected interrupt in the OTG interrupt status register, indicating the start of HNP. The OTG_FS controller deasserts the DM pull down and DM pull down in the PHY to indicate a device role. The PHY enables the OTG_DP pull-up resistor to indicate a connect for B-device. The application must read the current mode bit in the OTG Control and status register to determine device mode operation. 4. The B-device detects the connection, issues a USB reset, and enumerates the OTG_FS controller for data traffic. 5. The B-device continues the host role, initiating traffic, and suspends the bus when done. The OTG_FS controller sets the early suspend bit in the Core interrupt register after 3 ms of bus idleness. Following this, the OTG_FS controller sets the USB Suspend bit in the Core interrupt register. 6. In Negotiated mode, the OTG_FS controller detects the suspend, disconnects, and switches back to the host role. The OTG_FS controller asserts the DM pull down and DM pull down in the PHY to indicate its assumption of the host role. 7. The OTG_FS controller sets the Connector ID status change interrupt in the OTG Interrupt Status register. The application must read the connector ID status in the OTG Control and Status register to determine the OTG_FS controller operation as an Adevice. This indicates the completion of HNP to the application. The application must read the Current mode bit in the OTG control and status register to determine host mode operation. 8. The B-device connects, completing the HNP process. B-device host negotiation protocol HNP switches the USB host role from B-device to A-device. The application must set the HNP-capable bit in the Core USB configuration register to enable the OTG_FS controller to perform HNP as a B-device. DocID024597 Rev 1 1633/1680 1635 USB on-the-go full-speed (OTG_FS) RM0351 Figure 512. B-device HNP 1 OTG core Device Host Suspend 2 DP 4 3 Device 6 5 Reset DM Traffic 8 7 Connect Traffic DPPULLDOWN DMPULLDOWN ai15684 1. DPPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DP line inside the PHY. DMPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DM line inside the PHY. 1. The A-device sends the SetFeature b_hnp_enable descriptor to enable HNP support. The OTG_FS controller’s ACK response indicates that it supports HNP. The application must set the device HNP enable bit in the OTG Control and status register to indicate HNP support. The application sets the HNP request bit in the OTG Control and status register to indicate to the OTG_FS controller to initiate HNP. 2. When it has finished using the bus, the A-device suspends by writing the Port suspend bit in the host port control and status register. The OTG_FS controller sets the Early suspend bit in the Core interrupt register after 3 ms of bus idleness. Following this, the OTG_FS controller sets the USB suspend bit in the Core interrupt register. The OTG_FS controller disconnects and the A-device detects SE0 on the bus, indicating HNP. The OTG_FS controller asserts the DP pull down and DM pull down in the PHY to indicate its assumption of the host role. The A-device responds by activating its OTG_DP pull-up resistor within 3 ms of detecting SE0. The OTG_FS controller detects this as a connect. The OTG_FS controller sets the host negotiation success status change interrupt in the OTG Interrupt status register, indicating the HNP status. The application must read the host negotiation success bit in the OTG Control and status register to determine host 1634/1680 DocID024597 Rev 1 RM0351 USB on-the-go full-speed (OTG_FS) negotiation success. The application must read the current Mode bit in the Core interrupt register (OTG_GINTSTS) to determine host mode operation. 3. The application sets the reset bit (PRST in OTG_HPRT) and the OTG_FS controller issues a USB reset and enumerates the A-device for data traffic. 4. The OTG_FS controller continues the host role of initiating traffic, and when done, suspends the bus by writing the Port suspend bit in the host port control and status register. 5. In Negotiated mode, when the A-device detects a suspend, it disconnects and switches back to the host role. The OTG_FS controller deasserts the DP pull down and DM pull down in the PHY to indicate the assumption of the device role. 6. The application must read the current mode bit in the Core interrupt (OTG_GINTSTS) register to determine the host mode operation. 7. The OTG_FS controller connects, completing the HNP process. DocID024597 Rev 1 1635/1680 1635 Debug support (DBG) RM0351 44 Debug support (DBG) 44.1 Overview The STM32L4x6 devices are built around a Cortex®-M4 core which contains hardware extensions for advanced debugging features. The debug extensions allow the core to be stopped either on a given instruction fetch (breakpoint) or data access (watchpoint). When stopped, the core’s internal state and the system’s external state may be examined. Once examination is complete, the core and the system may be restored and program execution resumed. The debug features are used by the debugger host when connecting to and debugging the STM32L4x6 MCUs. Two interfaces for debug are available: • Serial wire • JTAG debug port Figure 513. Block diagram of STM32 MCU and Cortex®-M4-level debug support 34- -#5 DEBUG SUPPORT #ORTEX - DEBUG SUPPORT "US MATRIX #ORTEX - #ORE $#ODE INTERFACE $ATA 3YSTEM INTERFACE *4-3 37$)/ %XTERNAL PRIVATE PERIPHERAL BUS 00" *4$) *4$/ 42!#%37/ .*4234 *4#+ 37#,+ "RIDGE 37* $0 %4- !(" !0 42!#%37/ )NTERNAL PRIVATE PERIPHERAL BUS 00" .6)# 4RACE PORT 40)5 42!#%#+ 42!#%$;= $74 &0" )4- $"'-#5 -36 Note: 1636/1680 The debug features embedded in the Cortex®-M4 core are a subset of the ARM® CoreSight Design Kit. DocID024597 Rev 1 RM0351 Debug support (DBG) The ARM® Cortex®-M4 core provides integrated on-chip debug support. It is comprised of: • SWJ-DP: Serial wire / JTAG debug port • AHP-AP: AHB access port • ITM: Instrumentation trace macrocell • FPB: Flash patch breakpoint • DWT: Data watchpoint trigger • TPUI: Trace port unit interface (available on larger packages, where the corresponding pins are mapped) • ETM: Embedded Trace Macrocell (available only on STM32L4x6 devices larger packages, where the corresponding pins are mapped) It also includes debug features dedicated to the STM32L4x6: • Flexible debug pinout assignment • MCU debug box (support for low-power modes, control over peripheral clocks, etc.) Note: For further information on debug functionality supported by the ARM® Cortex®-M4 core, refer to the Cortex®-M4-r0p1 Technical Reference Manual and to the CoreSight Design Kitr0p1 TRM (see Section 44.2: Reference ARM® documentation). 44.2 Reference ARM® documentation • Cortex®-M4 r0p1 Technical Reference Manual (TRM), search for “Cortex®-M4 Technical Reference Manual” at http://infocenter.arm.com 44.3 • ARM® Debug Interface V5 • ARM® CoreSight Design Kit revision r0p1 Technical Reference Manual SWJ debug port (serial wire and JTAG) The STM32L4x6 core integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an ARM® standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW-DP (2-pin) interface. • The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-AP port. • The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the AHP-AP port. In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG pins of the JTAG-DP. DocID024597 Rev 1 1637/1680 1669 Debug support (DBG) RM0351 Figure 514. SWJ debug port TRACESWO (asynchronous trace) SWJ-DP JTDO JTDI NJTRST TDO TDI nTRST TDO TDI nTRST JTAG-DP TCK TMS nPOTRST SWD/JTAG select nPOTRST DBGRESETn SWDITMS JTMS/SWDIO From power-on reset DBGDI SWDO DBGDO SW-DP SWDOEN JTCK/SWCLK SWCLKTCK DBGDOEN DBGCLK ai17139 Figure 514 shows that the asynchronous TRACE output (TRACESWO) is multiplexed with TDO. This means that the asynchronous trace can only be used with SW-DP, not JTAG-DP. 44.3.1 Mechanism to select the JTAG-DP or the SW-DP By default, the JTAG-Debug Port is active. If the debugger host wants to switch to the SW-DP, it must provide a dedicated JTAG sequence on TMS/TCK (respectively mapped to SWDIO and SWCLK) which disables the JTAG-DP and enables the SW-DP. This way it is possible to activate the SWDP using only the SWCLK and SWDIO pins. This sequence is: 44.4 1. Send more than 50 TCK cycles with TMS (SWDIO) =1 2. Send the 16-bit sequence on TMS (SWDIO) = 0111100111100111 (MSB transmitted first) 3. Send more than 50 TCK cycles with TMS (SWDIO) =1 Pinout and debug port pins The STM32L4x6 MCUs are available in various packages with different numbers of available pins. As a result, some functionalities (ETM) related to pin availability may differ between packages. 1638/1680 DocID024597 Rev 1 RM0351 44.4.1 Debug support (DBG) SWJ debug port pins Five pins are used as outputs from the STM32L4x6 for the SWJ-DP as alternate functions of general-purpose I/Os. These pins are available on all packages. Table 260. SWJ debug port pins JTAG debug port SW debug port SWJ-DP pin name Type 44.4.2 Description Type Debug assignment Pin assign ment JTMS/SWDIO I JTAG Test Mode Selection IO Serial Wire Data Input/Output PA13 JTCK/SWCLK I JTAG Test Clock I Serial Wire Clock PA14 JTDI I JTAG Test Data Input - - PA15 JTDO/TRACESWO O JTAG Test Data Output - TRACESWO if asynchronous trace is enabled PB3 NJTRST I JTAG Test nReset - - PB4 Flexible SWJ-DP pin assignment After RESET (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as dedicated pins immediately usable by the debugger host (note that the trace outputs are not assigned except if explicitly programmed by the debugger host). However, the STM32L4x6 MCUs offer the possibility of disabling some or all of the SWJ-DP ports, and therefore the possibility of releasing the associated pins for general-purpose I/O (GPIO) usage. For more details on how to disable SWJ-DP port pins, please refer to Section 9.3.2: I/O pin alternate function multiplexer and mapping. Table 261. Flexible SWJ-DP pin assignment SWJ IO pin assigned Available debug ports PA13 / PA14 / PA15 / JTMS/ JTCK/ JTDI SWDIO SWCLK PB4/ NJTRST X Full SWJ (JTAG-DP + SW-DP) - Reset State X X X X Full SWJ (JTAG-DP + SW-DP) but without NJTRST X X X X JTAG-DP disabled and SW-DP enabled X X JTAG-DP disabled and SW-DP disabled Note: PB3 / JTDO Released When the APB bridge write buffer is full, it takes one extra APB cycle when writing the AFIO_MAPR register. This is because the deactivation of the JTAGSW pins is done in two cycles to guarantee a clean level on the nTRST and TCK input signals of the core. • Cycle 1: the JTAGSW input signals to the core are tied to 1 or 0 (to 1 for nTRST, TDI and TMS, to 0 for TCK) • Cycle 2: the GPIO controller takes the control signals of the SWJTAG IO pins (like controls of direction, pull-up/down, Schmitt trigger activation, etc.). DocID024597 Rev 1 1639/1680 1669 Debug support (DBG) 44.4.3 RM0351 Internal pull-up and pull-down on JTAG pins It is necessary to ensure that the JTAG input pins are not floating since they are directly connected to flip-flops to control the debug mode features. Special care must be taken with the SWCLK/TCK pin which is directly connected to the clock of some of these flip-flops. To avoid any uncontrolled IO levels, the device embeds internal pull-ups and pull-downs on the JTAG input pins: • NJTRST: internal pull-up • JTDI: internal pull-up • JTMS/SWDIO: internal pull-up • TCK/SWCLK: internal pull-down Once a JTAG IO is released by the user software, the GPIO controller takes control again. The reset states of the GPIO control registers put the I/Os in the equivalent state: • NJTRST: input pull-up • JTDI: input pull-up • JTMS/SWDIO: input pull-up • JTCK/SWCLK: input pull-down • JTDO: input floating The software can then use these I/Os as standard GPIOs. Note: The JTAG IEEE standard recommends to add pull-ups on TDI, TMS and nTRST but there is no special recommendation for TCK. However, for JTCK, the device needs an integrated pull-down. Having embedded pull-ups and pull-downs removes the need to add external resistors. 1640/1680 DocID024597 Rev 1 RM0351 44.4.4 Debug support (DBG) Using serial wire and releasing the unused debug pins as GPIOs To use the serial wire DP to release some GPIOs, the user software must change the GPIO (PA15, PB3 and PB4) configuration mode in the GPIO_MODER register.This releases PA15, PB3 and PB4 which now become available as GPIOs. When debugging, the host performs the following actions: Note: • Under system reset, all SWJ pins are assigned (JTAG-DP + SW-DP). • Under system reset, the debugger host sends the JTAG sequence to switch from the JTAG-DP to the SW-DP. • Still under system reset, the debugger sets a breakpoint on vector reset. • The system reset is released and the Core halts. • All the debug communications from this point are done using the SW-DP. The other JTAG pins can then be reassigned as GPIOs by the user software. For user software designs, note that: To release the debug pins, remember that they will be first configured either in input-pull-up (nTRST, TMS, TDI) or pull-down (TCK) or output tristate (TDO) for a certain duration after reset until the instant when the user software releases the pins. When debug pins (JTAG or SW or TRACE) are mapped, changing the corresponding IO pin configuration in the IOPORT controller has no effect. 44.5 STM32L4x6 JTAG TAP connection The STM32L4x6 MCUs integrate two serially connected JTAG TAPs, the boundary scan TAP (IR is 5-bit wide) and the Cortex®-M4 TAP (IR is 4-bit wide). To access the TAP of the Cortex®-M4 for debug purposes: Note: 1. First, it is necessary to shift the BYPASS instruction of the boundary scan TAP. 2. Then, for each IR shift, the scan chain contains 9 bits (=5+4) and the unused TAP instruction must be shifted by using the BYPASS instruction. 3. For each data shift, the unused TAP, which is in BYPASS mode, adds 1 extra data bit in the data scan chain. Important: Once Serial-Wire is selected using the dedicated ARM® JTAG sequence, the boundary scan TAP is automatically disabled (JTMS forced high). DocID024597 Rev 1 1641/1680 1669 Debug support (DBG) RM0351 Figure 515. JTAG TAP connections 34- -#5 .*4234 *4-3 37 $0 3ELECTED 4-3 N4234 *4$) *4$/ 4$) 4$/ "OUNDARY SCAN 4!0 )2 IS BIT WIDE 4-3 N4234 4$) 4$/ #ORTEX - 4!0 )2 IS BIT WIDE AIC 44.6 ID codes and locking mechanism There are several ID codes inside the STM32L4x6 MCUs. ST strongly recommends tools designers to lock their debuggers using the MCU DEVICE ID code located in the external PPB memory map at address 0xE0042000. 1642/1680 DocID024597 Rev 1 RM0351 Debug support (DBG) 44.6.1 MCU device ID code The STM32L4x6 MCUs integrate an MCU ID code. This ID identifies the ST MCU partnumber and the die revision. It is part of the DBG_MCU component and is mapped on the external PPB bus (see Section 44.16 on page 1655). This code is accessible using the JTAG debug port (4 to 5 pins) or the SW debug port (two pins) or by the user software. It is even accessible while the MCU is under system reset. Only the DEV_ID(11:0) should be used for identification by the debugger/programmer tools. DBGMCU_IDCODE Address: 0xE004 2000 Only 32-bits access supported. Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 REV_ID r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r r DEV_ID r Bits 31:16 REV_ID[15:0] Revision identifier This field indicates the revision of the device. Bits 31 down to 28: full mask revision 0001: Cut 1.x 0010: Cut 2.x ... Bits 27 down to 16: mask revision, one bit by metal fix 00000000000: cut x.0 00000000001: cut x.1 00000000011: cut x.2 00000000111: cut x.3 00000001111: cut x.4 ... Bits 15:0 DEV_ID[15:0]: Device identifier The device ID is 0x6415 44.6.2 Boundary scan TAP JTAG ID code The TAP of the STM32L4x6 BSC (boundary scan) integrates a JTAG ID code equal to 0x06415041. 44.6.3 Cortex®-M4 TAP The TAP of the ARM® Cortex®-M4 integrates a JTAG ID code. This ID code is the ARM® default one and has not been modified. This code is only accessible by the JTAG Debug Port. DocID024597 Rev 1 1643/1680 1669 Debug support (DBG) RM0351 This code is 0x4BA00477 (corresponds to Cortex®-M4 r0p1, see Section 44.2: Reference ARM® documentation). 44.6.4 Cortex®-M4 JEDEC-106 ID code The ARM® Cortex®-M4 integrates a JEDEC-106 ID code. It is located in the 4KB ROM table mapped on the internal PPB bus at address 0xE00FF000_0xE00FFFFF. This code is accessible by the JTAG Debug Port (4 to 5 pins) or by the SW Debug Port (two pins) or by the user software. 44.7 JTAG debug port A standard JTAG state machine is implemented with a 4-bit instruction register (IR) and five data registers (for full details, refer to the Cortex®-M4 with FPU r0p1 Technical Reference Manual (TRM), for references, please see Section 44.2: Reference ARM® documentation). Table 262. JTAG debug port data registers IR(3:0) Data register Details 1111 BYPASS [1 bit] - 1110 IDCODE [32 bits] ID CODE 0x3BA00477 (ARM® Cortex®-M4 r0p1-01rel0 ID Code) DPACC [35 bits] Debug port access register This initiates a debug port and allows access to a debug port register. – When transferring data IN: Bits 34:3= DATA[31:0] = 32-bit data to transfer for a write request Bits 2:1 = A[3:2] = 2-bit address of a debug port register. Bit 0 = RnW = Read request (1) or write request (0). – When transferring data OUT: Bits 34:3 = DATA[31:0] = 32-bit data which is read following a read request Bits 2:0 = ACK[2:0] = 3-bit Acknowledge: 010 = OK/FAULT 001 = WAIT OTHER = reserved Refer to Table 263 for a description of the A(3:2) bits 1010 1644/1680 DocID024597 Rev 1 RM0351 Debug support (DBG) Table 262. JTAG debug port data registers (continued) IR(3:0) Data register Details 1011 APACC [35 bits] Access port access register Initiates an access port and allows access to an access port register. – When transferring data IN: Bits 34:3 = DATA[31:0] = 32-bit data to shift in for a write request Bits 2:1 = A[3:2] = 2-bit address (sub-address AP registers). Bit 0 = RnW= Read request (1) or write request (0). – When transferring data OUT: Bits 34:3 = DATA[31:0] = 32-bit data which is read following a read request Bits 2:0 = ACK[2:0] = 3-bit Acknowledge: 010 = OK/FAULT 001 = WAIT OTHER = reserved There are many AP Registers (see AHB-AP) addressed as the combination of: – The shifted value A[3:2] – The current value of the DP SELECT register 1000 ABORT [35 bits] Abort register – Bits 31:1 = Reserved – Bit 0 = DAPABORT: write 1 to generate a DAP abort. Table 263. 32-bit debug port registers addressed through the shifted value A[3:2] Address A(3:2) value 0x0 Description 00 Reserved, must be kept at reset value. 01 DP CTRL/STAT register. Used to: – Request a system or debug power-up – Configure the transfer operation for AP accesses – Control the pushed compare and pushed verify operations – Read some status flags (overrun, power-up acknowledges) 0x8 10 DP SELECT register. Used to select the current access port and the active 4-words register window. – Bits 31:24: APSEL: select the current AP – Bits 23:8: reserved – Bits 7:4: APBANKSEL: select the active 4-words register window on the current AP – Bits 3:0: reserved 0xC 11 DP RDBUFF register: Used to allow the debugger to get the final result after a sequence of operations (without requesting new JTAG-DP operation) 0x4 DocID024597 Rev 1 1645/1680 1669 Debug support (DBG) RM0351 44.8 SW debug port 44.8.1 SW protocol introduction This synchronous serial protocol uses two pins: • SWCLK: clock from host to target • SWDIO: bidirectional The protocol allows two banks of registers (DPACC registers and APACC registers) to be read and written to. Bits are transferred LSB-first on the wire. For SWDIO bidirectional management, the line must be pulled-up on the board (100 kΩ recommended by ARM®). Each time the direction of SWDIO changes in the protocol, a turnaround time is inserted where the line is not driven by the host nor the target. By default, this turnaround time is one bit time, however this can be adjusted by configuring the SWCLK frequency. 44.8.2 SW protocol sequence Each sequence consist of three phases: 1. Packet request (8 bits) transmitted by the host 2. Acknowledge response (3 bits) transmitted by the target 3. Data transfer phase (33 bits) transmitted by the host or the target Table 264. Packet request (8-bits) Bit Name Description 0 Start Must be “1” 1 APnDP 0: DP Access 1: AP Access 2 RnW 0: Write Request 1: Read Request 4:3 A(3:2) Address field of the DP or AP registers (refer to Table 263) 5 Parity Single bit parity of preceding bits 6 Stop 0 7 Park Not driven by the host. Must be read as “1” by the target because of the pull-up Refer to the Cortex®-M4 r0p1 TRM for a detailed description of DPACC and APACC registers. The packet request is always followed by the turnaround time (default 1 bit) where neither the host nor target drive the line. 1646/1680 DocID024597 Rev 1 RM0351 Debug support (DBG) Table 265. ACK response (3 bits) Bit 0..2 Name Description 001: FAULT 010: WAIT 100: OK ACK The ACK Response must be followed by a turnaround time only if it is a READ transaction or if a WAIT or FAULT acknowledge has been received. Table 266. DATA transfer (33 bits) Bit 0..31 32 Name Description WDATA or RDATA Write or Read data Parity Single parity of the 32 data bits The DATA transfer must be followed by a turnaround time only if it is a READ transaction. 44.8.3 SW-DP state machine (reset, idle states, ID code) The State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It follows the JEP-106 standard. This ID code is the default ARM® one and is set to 0x1BA01477 (corresponding to Cortex®-M4 r0p1). Note: Note that the SW-DP state machine is inactive until the target reads this ID code. • The SW-DP state machine is in RESET STATE either after power-on reset, or after the DP has switched from JTAG to SWD or after the line is high for more than 50 cycles • The SW-DP state machine is in IDLE STATE if the line is low for at least two cycles after RESET state. • After RESET state, it is mandatory to first enter into an IDLE state AND to perform a READ access of the DP-SW ID CODE register. Otherwise, the target will issue a FAULT acknowledge response on another transactions. Further details of the SW-DP state machine can be found in the Cortex®-M4 r0p1 TRM and the CoreSight Design Kit r0p1 TRM. 44.8.4 DP and AP read/write accesses • Read accesses to the DP are not posted: the target response can be immediate (if ACK=OK) or can be delayed (if ACK=WAIT). • Read accesses to the AP are posted. This means that the result of the access is returned on the next transfer. If the next access to be done is NOT an AP access, then the DP-RDBUFF register must be read to obtain the result. The READOK flag of the DP-CTRL/STAT register is updated on every AP read access or RDBUFF read request to know if the AP read access was successful. • The SW-DP implements a write buffer (for both DP or AP writes), that enables it to accept a write operation even when other transactions are still outstanding. If the write buffer is full, the target acknowledge response is “WAIT”. With the exception of DocID024597 Rev 1 1647/1680 1669 Debug support (DBG) RM0351 IDCODE read or CTRL/STAT read or ABORT write which are accepted even if the write buffer is full. • 44.8.5 Because of the asynchronous clock domains SWCLK and HCLK, two extra SWCLK cycles are needed after a write transaction (after the parity bit) to make the write effective internally. These cycles should be applied while driving the line low (IDLE state) This is particularly important when writing the CTRL/STAT for a power-up request. If the next transaction (requiring a power-up) occurs immediately, it will fail. SW-DP registers Access to these registers are initiated when APnDP=0 Table 267. SW-DP registers A(3:2) CTRLSEL bit of SELECT register Register Notes 00 Read - IDCODE The manufacturer code is not set to ST code 0x2BA01477 (identifies the SW-DP) 00 Write - ABORT - 01 Read/Write 0 DPCTRL/STAT Purpose is to: – request a system or debug power-up – configure the transfer operation for AP accesses – control the pushed compare and pushed verify operations. – read some status flags (overrun, powerup acknowledges) 01 Read/Write 1 WIRE CONTROL Purpose is to configure the physical serial port protocol (like the duration of the turnaround time) 10 Read - READ RESEND Enables recovery of the read data from a corrupted debugger transfer, without repeating the original AP transfer. 10 Write - SELECT The purpose is to select the current access port and the active 4-words register window READ BUFFER This read buffer is useful because AP accesses are posted (the result of a read AP request is available on the next AP transaction). This read buffer captures data from the AP, presented as the result of a previous read, without initiating a new transaction 11 1648/1680 R/W Read/Write - DocID024597 Rev 1 RM0351 44.8.6 Debug support (DBG) SW-AP registers Access to these registers are initiated when APnDP=1 There are many AP Registers (see AHB-AP) addressed as the combination of: 44.9 • The shifted value A[3:2] • The current value of the DP SELECT register AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP Features: • System access is independent of the processor status. • Either SW-DP or JTAG-DP accesses AHB-AP. • The AHB-AP is an AHB master into the Bus Matrix. Consequently, it can access all the data buses (Dcode Bus, System Bus, internal and external PPB bus) but the ICode bus. • Bitband transactions are supported. • AHB-AP transactions bypass the FPB. The address of the 32-bits AHP-AP resisters are 6-bits wide (up to 64 words or 256 bytes) and consists of: c) Bits [7:4] = the bits [7:4] APBANKSEL of the DP SELECT register d) Bits [3:2] = the 2 address bits of A(3:2) of the 35-bit packet request for SW-DP. The AHB-AP of the Cortex®-M4 includes 9 x 32-bits registers: Table 268. Cortex®-M4 AHB-AP registers Address offset Register name Notes 0x00 AHB-AP Control and Status Word Configures and controls transfers through the AHB interface (size, hprot, status on current transfer, address increment type 0x04 AHB-AP Transfer Address - 0x0C AHB-AP Data Read/Write - 0x10 AHB-AP Banked Data 0 0x14 AHB-AP Banked Data 1 0x18 AHB-AP Banked Data 2 0x1C AHB-AP Banked Data 3 0xF8 AHB-AP Debug ROM Address Base Address of the debug interface 0xFC AHB-AP ID Register Directly maps the 4 aligned data words without rewriting the Transfer Address Register. - Refer to the Cortex®-M4 r0p1 TRM for further details. DocID024597 Rev 1 1649/1680 1669 Debug support (DBG) 44.10 RM0351 Core debug Core debug is accessed through the core debug registers. Debug access to these registers is by means of the Advanced High-performance Bus (AHB-AP) port. The processor can access these registers directly over the internal Private Peripheral Bus (PPB). It consists of 4 registers: Table 269. Core debug registers Note: Register Description DHCSR The 32-bit Debug Halting Control and Status Register: This provides status information about the state of the processor enable core debug halt and step the processor. DCRSR The 17-bit Debug Core Register Selector Register: This selects the processor register to transfer data to or from. DCRDR The 32-bit Debug Core Register Data Register: This holds data for reading and writing registers to and from the processor selected by the DCRSR (Selector) register. DEMCR The 32-bit Debug Exception and Monitor Control Register: This provides Vector Catching and Debug Monitor Control. This register contains a bit named TRCENA which enable the use of a TRACE. Important: these registers are not reset by a system reset. They are only reset by a poweron reset. Refer to the Cortex®-M4 r0p1 TRM for further details. To Halt on reset, it is necessary to: 44.11 • enable the bit0 (VC_CORRESET) of the Debug and Exception Monitor Control Register • enable the bit0 (C_DEBUGEN) of the Debug Halting Control and Status Register. Capability of the debugger host to connect under system reset The STM32L4x6 MCUs’ reset system comprises the following reset sources: • POR (power-on reset) which asserts a RESET at each power-up • Internal watchdog reset • Software reset • External reset. The Cortex®-M4 differentiates the reset of the debug part (generally PORRESETn) and the other one (SYSRESETn). This way, it is possible for the debugger to connect under System Reset, programming the Core Debug Registers to halt the core when fetching the reset vector. Then the host can release the system reset and the core will immediately halt without having executed any instructions. In addition, it is possible to program any debug features under System Reset. 1650/1680 DocID024597 Rev 1 RM0351 Debug support (DBG) Note: It is highly recommended for the debugger host to connect (set a breakpoint in the reset vector) under system reset. 44.12 FPB (Flash patch breakpoint) The FPB unit: • implements hardware breakpoints • patches code and data from code space to system space. This feature gives the possibility to correct software bugs located in the Code Memory Space. The use of a Software Patch or a Hardware Breakpoint is exclusive. The FPB consists of: 44.13 • 2 literal comparators for matching against literal loads from Code Space and remapping to a corresponding area in the System Space • 6 instruction comparators for matching against instruction fetches from Code Space. They can be used either to remap to a corresponding area in the System Space or to generate a Breakpoint Instruction to the core. DWT (data watchpoint trigger) The DWT unit consists of four comparators. They are configurable as: • a hardware watchpoint or • a trigger to an ETM or • a PC sampler or • a data address sampler The DWT also provides some means to give some profiling informations. For this, some counters are accessible to give the number of: • Clock cycle • Folded instructions • Load store unit (LSU) operations • Sleep cycles • CPI (clock per instructions) • Interrupt overhead DocID024597 Rev 1 1651/1680 1669 Debug support (DBG) RM0351 44.14 ITM (instrumentation trace macrocell) 44.14.1 General description The ITM is an application-driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets which can be generated as: • Software trace. Software can write directly to the ITM stimulus registers to emit packets. • Hardware trace. The DWT generates these packets, and the ITM emits them. • Time stamping. Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate the timestamp. The Cortex®-M4 clock or the bit clock rate of the Serial Wire Viewer (SWV) output clocks the counter. The packets emitted by the ITM are output to the TPIU (Trace Port Interface Unit). The formatter of the TPIU adds some extra packets (refer to TPIU) and then output the complete packets sequence to the debugger host. The bit TRCEN of the Debug Exception and Monitor Control Register must be enabled before you program or use the ITM. 44.14.2 Time stamp packets, synchronization and overflow packets Time stamp packets encode time stamp information, generic control and synchronization. It uses a 21-bit timestamp counter (with possible prescalers) which is reset at each time stamp packet emission. This counter can be either clocked by the CPU clock or the SWV clock. A synchronization packet consists of 6 bytes equal to 0x80_00_00_00_00_00 which is emitted to the TPIU as 00 00 00 00 00 80 (LSB emitted first). A synchronization packet is a timestamp packet control. It is emitted at each DWT trigger. For this, the DWT must be configured to trigger the ITM: the bit CYCCNTENA (bit0) of the DWT Control Register must be set. In addition, the bit2 (SYNCENA) of the ITM Trace Control Register must be set. Note: If the SYNENA bit is not set, the DWT generates Synchronization triggers to the TPIU which will send only TPIU synchronization packets and not ITM synchronization packets. An overflow packet consists is a special timestamp packets which indicates that data has been written but the FIFO was full. Table 270. Main ITM registers Address @E0000FB0 1652/1680 Register ITM lock access Details Write 0xC5ACCE55 to unlock Write Access to the other ITM registers DocID024597 Rev 1 RM0351 Debug support (DBG) Table 270. Main ITM registers Address Register Details Bits 31-24 = Always 0 Bits 23 = Busy Bits 22-16 = 7-bits ATB ID which identifies the source of the trace data Bits 15-10 = Always 0 Bits 9:8 = TSPrescale = Time Stamp Prescaler Bits 7-5 = Reserved @E0000E80 ITM trace control Bit 4 = SWOENA = Enable SWV behavior (to clock the timestamp counter by the SWV clock) Bit 3 = DWTENA: Enable the DWT Stimulus Bit 2 = SYNCENA: this bit must be to 1 to enable the DWT to generate synchronization triggers so that the TPIU can then emit the synchronization packets Bit 1 = TSENA (Timestamp Enable) Bit 0 = ITMENA: Global Enable Bit of the ITM Bit 3: mask to enable tracing ports31:24 @E0000E40 ITM trace privilege Bit 2: mask to enable tracing ports23:16 Bit 1: mask to enable tracing ports15:8 Bit 0: mask to enable tracing ports7:0 @E0000E00 ITM trace enable @E0000000- Stimulus port E000007C registers 0-31 Each bit enables the corresponding Stimulus port to generate trace Write the 32-bits data on the selected Stimulus Port (32 available) to be traced out Example of configuration To output a simple value to the TPIU: • Configure the TPIU and assign TRACE I/Os by configuring the DBGMCU_CR (refer to Section 44.17.2: TRACE pin assignment and Section 44.16.3: Debug MCU configuration register (DBGMCU_CR)) • Write 0xC5ACCE55 to the ITM Lock Access Register to unlock the write access to the ITM registers • Write 0x00010005 to the ITM Trace Control Register to enable the ITM with Synchronous enabled and an ATB ID different from 0x00 • Write 0x1 to the ITM Trace Enable Register to enable the Stimulus Port 0 • Write 0x1 to the ITM Trace Privilege Register to unmask Stimulus Ports 7:0 • Write the value to output in the Stimulus Port Register 0: this can be done by software (using a printf function) DocID024597 Rev 1 1653/1680 1669 Debug support (DBG) RM0351 44.15 ETM (Embedded trace macrocell) 44.15.1 General description The ETM enables the reconstruction of program execution. Data are traced using the Data Watchpoint and Trace (DWT) component or the Instruction Trace Macrocell (ITM) whereas instructions are traced using the Embedded Trace Macrocell (ETM). The ETM transmits information as packets and is triggered by embedded resources. These resources must be programmed independently and the trigger source is selected using the Trigger Event Register (0xE0041008). An event could be a simple event (address match from an address comparator) or a logic equation between 2 events. The trigger source is one of the four comparators of the DWT module, The following events can be monitored: • Clock cycle matching • Data address matching For more informations on the trigger resources refer to Section 44.13: DWT (data watchpoint trigger). The packets transmitted by the ETM are output to the TPIU (Trace Port Interface Unit). The formatter of the TPIU adds some extra packets (refer to Section 44.17: TPIU (trace port interface unit)) and then outputs the complete packet sequence to the debugger host. 44.15.2 Signal protocol, packet types This part is described in the chapter 7 ETMv3 Signal Protocol of the ARM® IHI 0014N document. 44.15.3 Main ETM registers For more information on registers refer to the chapter 3 of the ARM® IHI 0014N specification. Table 271. Main ETM registers Address Register Details 0xE0041FB0 ETM Lock Access Write 0xC5ACCE55 to unlock the write access to the other ETM registers. 0xE0041000 ETM Control This register controls the general operation of the ETM, for instance how tracing is enabled. 0xE0041010 ETM Status This register provides information about the current status of the trace and trigger logic. 0xE0041008 ETM Trigger Event This register defines the event that will control trigger. 0xE004101C ETM Trace Enable Control This register defines which comparator is selected. 0xE0041020 ETM Trace Enable Event This register defines the trace enabling event. 0xE0041024 ETM Trace Start/Stop This register defines the traces used by the trigger source to start and stop the trace, respectively. 1654/1680 DocID024597 Rev 1 RM0351 44.15.4 Debug support (DBG) Configuration example To output a simple value to the TPIU: 44.16 • Configure the TPIU and enable the I/IO_TRACEN to assign TRACE I/Os in the STM32L4x6 debug configuration register • Write 0xC5ACCE55 to the ETM Lock Access Register to unlock the write access to the ITM registers • Write 0x00001D1E to the control register (configure the trace) • Write 0000406F to the Trigger Event register (define the trigger event) • Write 0000006F to the Trace Enable Event register (define an event to start/stop) • Write 00000001 to the Trace Start/stop register (enable the trace) • Write 0000191E to the ETM Control Register (end of configuration) MCU debug component (DBGMCU) The MCU debug component helps the debugger provide support for: 44.16.1 • Low-power modes • Clock control for timers, watchdog, I2C and bxCAN during a breakpoint • Control of the trace pins assignment Debug support for low-power modes To enter low-power mode, the instruction WFI or WFE must be executed. The MCU implements several low-power modes which can either deactivate the CPU clock or reduce the power of the CPU. The core does not allow FCLK or HCLK to be turned off during a debug session. As these are required for the debugger connection, during a debug, they must remain active. The MCU integrates special means to allow the user to debug software in low-power modes. For this, the debugger host must first set some debug configuration registers to change the low-power mode behavior: • In Sleep mode, DBG_SLEEP bit of DBGMCU_CR register must be previously set by the debugger. This will feed HCLK with the same clock that is provided to FCLK (system clock previously configured by the software). • In Stop mode, the bit DBG_STOP must be previously set by the debugger. This will enable the internal RC oscillator clock to feed FCLK and HCLK in Stop mode. • In Standby mode, the bit DBG_STANDBY must be previously set by the debugger. This will keep the regulators on, and enable the internal RC oscillator clock to feed FCLK and HCLK in Standby mode. A system reset is generated internally so that exiting from Standby is identical than fetching from reset. The DBGMCU_CR register can be written by the debugger under system reset. If the debugger host does not support these features, it is still possible to write this register by software. DocID024597 Rev 1 1655/1680 1669 Debug support (DBG) RM0351 Debug support for timers, RTC, watchdog, bxCAN and I2C 44.16.2 During a breakpoint, it is necessary to choose how the counter of timers,RTC and watchdog should behave: • They can continue to count inside a breakpoint. This is usually required when a PWM is controlling a motor, for example. • They can stop to count inside a breakpoint. This is required for watchdog purposes. For the bxCAN, the user can choose to block the update of the receive register during a breakpoint. For the I2C, the user can choose to block the SMBUS timeout during a breakpoint. The DBGMCU freeze registers can be written by the debugger under system reset. If the debugger host does not support these features, it is still possible to write these registers by software. 44.16.3 Debug MCU configuration register (DBGMCU_CR) Address: 0xE004 2004 Power-on reset: 0x0000 0000 System reset: not affected Access: Only 32-bit access supported 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. DBG_ STAND BY DBG_ STOP DBG_ SLEEP rw rw rw Res. Res. Res. Res. Res. Res. Res. Res. TRACE_ MODE [1:0] rw rw TRACE _ IOEN rw Res.. Bits 31:8 Reserved, must be kept at reset value. Bits 7:5 TRACE_MODE[1:0] and TRACE_IOEN: Trace pin assignment control – With TRACE_IOEN=0: TRACE_MODE=xx: TRACE pins not assigned (default state) – With TRACE_IOEN=1: – TRACE_MODE=00: TRACE pin assignment for Asynchronous Mode – TRACE_MODE=01: TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 – TRACE_MODE=10: TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 – TRACE_MODE=11: TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 Bits 4:3 Reserved, must be kept at reset value. 1656/1680 DocID024597 Rev 1 RM0351 Debug support (DBG) Bit 2 DBG_STANDBY: Debug Standby mode 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. From software point of view, exiting from Standby is identical than fetching reset vector (except a few status bit indicated that the MCU is resuming from Standby) 1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and FCLK and HCLK are provided by the internal RC oscillator which remains active. In addition, the MCU generate a system reset during Standby mode so that exiting from Standby is identical than fetching from reset. Bit 1 DBG_STOP: Debug Stop mode 0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all clocks (including HCLK and FCLK). When exiting from STOP mode, the clock configuration is identical to the one after RESET (CPU clocked by the 8 MHz internal RC oscillator (HSI16)). Consequently, the software must reprogram the clock controller to enable the PLL, the Xtal, etc. 1: (FCLK=On, HCLK=On) In this case, when entering STOP mode, FCLK and HCLK are provided by the internal RC oscillator which remains active in STOP mode. When exiting STOP mode, the software must reprogram the clock controller to enable the PLL, the Xtal, etc. (in the same way it would do in case of DBG_STOP=0) Bit 0 DBG_SLEEP: Debug Sleep mode 0: (FCLK=On, HCLK=Off) In Sleep mode, FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled. In Sleep mode, the clock controller configuration is not reset and remains in the previously programmed state. Consequently, when exiting from Sleep mode, the software does not need to reconfigure the clock controller. 1: (FCLK=On, HCLK=On) In this case, when entering Sleep mode, HCLK is fed by the same clock that is provided to FCLK (system clock as previously configured by the software). DocID024597 Rev 1 1657/1680 1669 Debug support (DBG) 44.16.4 RM0351 Debug MCU APB1 freeze register1(DBGMCU_APB1FZR1) Address: 0xE004 2008 Power on reset (POR): 0x0000 0000 System reset: not affected Access: Only 32-bit access are supported. 31 30 LPTIM1_ STOP 29 28 27 26 25 DBG_ CAN_ STOP 24 22 21 Res.. Res. Res. Res. Res. rw rw rw 15 14 13 12 11 10 9 8 7 6 5 Res. Res. Res. DBG_ RTC_ STOP Res. Res. Res. Res. rw Res. 23 rw DBG_ DBG_ IWDG_ WWDG STOP _STOP rw rw 20 DBG_ DBG_ DBG_ I2C3_ I2C2_ I2C1_ Res. STOP STOP STOP rw 4 19 18 17 16 Res. Res. Res. Res. 3 2 1 0 DBG_ DBG_ DBG_ DBG_ DBG_ DBG_ TIM7 TIM6 TIM5 TIM4_ TIM3_ TIM2_ _STO _STO _STO STOP STOP STOP P P P rw rw rw rw Bit 31 DBG_LPTIM1_STOP: LPTIM1 counter stopped when core is halted 0: The counter clock of LPTIM1 is fed even if the core is halted 1: The counter clock of LPTIM1 is stopped when the core is halted Bits 30:26 Reserved, must be kept at reset value. Bit 25 DBG_CAN_STOP: bxCAN stopped when core is halted 0: Same behavior as in normal mode 1: The bxCAN receive registers are frozen Bit 24 Reserved, must be kept at reset value. Bit 23 DBG_I2C3_STOP: I2C3 SMBUS timeout counter stopped when core is halted 0: Same behavior as in normal mode 1: The I2C3 SMBus timeout is frozen Bit 22 DBG_I2C2_STOP: I2C2 SMBUS timeout counter stopped when core is halted 0: Same behavior as in normal mode 1: The I2C2 SMBus timeout is frozen Bit 21 DBG_I2C1_STOP: I2C1 SMBUS timeout counter stopped when core is halted 0: Same behavior as in normal mode 1: The I2C1 SMBus timeout is frozen Bits 20:13 Reserved, must be kept at reset value. Bit 12 DBG_IWDG_STOP: Independent watchdog counter stopped when core is halted 0: The independent watchdog counter clock continues even if the core is halted 1: The independent watchdog counter clock is stopped when the core is halted Bit 11 DBG_WWDG_STOP: Window watchdog counter stopped when core is halted 0: The window watchdog counter clock continues even if the core is halted 1: The window watchdog counter clock is stopped when the core is halted Bit 10 DBG_RTC_STOP: RTC counter stopped when core is halted 0: The clock of the RTC counter is fed even if the core is halted 1: The clock of the RTC counter is stopped when the core is halted Bits 9:6 Reserved, must be kept at reset value. 1658/1680 DocID024597 Rev 1 rw rw RM0351 Debug support (DBG) Bit 5 DBG_TIM7_STOP: TIM7 counter stopped when core is halted 0: The counter clock of TIM7 is fed even if the core is halted 1: The counter clock of TIM7 is stopped when the core is halted Bit 4 DBG_TIM6_STOP: TIM6 counter stopped when core is halted 0: The counter clock of TIM6 is fed even if the core is halted 1: The counter clock of TIM6 is stopped when the core is halted Bit 3 DBG_TIM5_STOP: TIM5 counter stopped when core is halted 0: The counter clock of TIM5 is fed even if the core is halted 1: The counter clock of TIM5 is stopped when the core is halted Bit 2 DBG_TIM4_STOP: TIM4 counter stopped when core is halted 0: The counter clock of TIM4 is fed even if the core is halted 1: The counter clock of TIM4 is stopped when the core is halted Bit 1 DBG_TIM3_STOP: TIM3 counter stopped when core is halted 0: The counter clock of TIM3 is fed even if the core is halted 1: The counter clock of TIM3 is stopped when the core is halted Bit 0 DBG_TIM2_STOP: TIM2 counter stopped when core is halted 0: The counter clock of TIM2 is fed even if the core is halted 1: The counter clock of TIM2 is stopped when the core is halted DocID024597 Rev 1 1659/1680 1669 Debug support (DBG) 44.16.5 RM0351 Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2) Address: 0xE004 200C Power on reset (POR): 0x0000 0000 System reset: not affected Access: Only 32-bit access are supported. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DBG_ LPTIM2 _STOP Res. Res. Res. Res. Res. rw Bits 31:6 Reserved, must be kept at reset value. Bit 5 DBG_LPTIM2_STOP: LPTIM2 counter stopped when core is halted 0: The counter clock of LPTIM2 is fed even if the core is halted 1: The counter clock of LPTIM2 is stopped when the core is halted Bits 4:0 Reserved, must be kept at reset value. 1660/1680 DocID024597 Rev 1 RM0351 Debug support (DBG) 44.16.6 Debug MCU APB2 freeze register (DBGMCU_APB2FZR) Address: 0xE004 2010 Power on reset (POR): 0x0000 0000 System reset: not affected Access: Only 32-bit access are supported. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DBG_TI M17_ST OP DBG_TI M16_ST OP DBG_TI M15_ST OP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. DBG_ TIM8_ STOP Res. DBG_ TIM1_ STOP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw Bits 31:19 Reserved, must be kept at reset value. Bit 18 DBG_TIM17_STOP: TIM17 counter stopped when core is halted 0: The clock of the TIM17 counter is fed even if the core is halted 1: The clock of the TIM17 counter is stopped when the core is halted Bit 17 DBG_TIM16_STOP: TIM16 counter stopped when core is halted 0: The clock of the TIM16 counter is fed even if the core is halted 1: The clock of the TIM16 counter is stopped when the core is halted Bit 16 DBG_TIM15_STOP: TIM15 counter stopped when core is halted 0: The clock of the TIM15 counter is fed even if the core is halted 1: The clock of the TIM15 counter is stopped when the core is halted Bits 15:14 Reserved, must be kept at reset value. Bit 13 DBG_TIM8_STOP: TIM8 counter stopped when core is halted 0: The clock of the TIM8 counter is fed even if the core is halted 1: The clock of the TIM8 counter is stopped when the core is halted Bit 12 Reserved, must be kept at reset value. Bit 11 DBG_TIM1_STOP: TIM1 counter stopped when core is halted 0: The clock of the TIM1 counter is fed even if the core is halted 1: The clock of the TIM1 counter is stopped when the core is halted Bits 10:0 Reserved, must be kept at reset value. DocID024597 Rev 1 1661/1680 1669 Debug support (DBG) RM0351 44.17 TPIU (trace port interface unit) 44.17.1 Introduction The TPIU acts as a bridge between the on-chip trace data from the ITM and the ETM. The output data stream encapsulates the trace source ID, that is then captured by a trace port analyzer (TPA). The core embeds a simple TPIU, especially designed for low-cost debug (consisting of a special version of the CoreSight TPIU). Figure 516. TPIU block diagram 42!#%#,+). DOMAIN #,+ DOMAIN 40)5 %4- 42!#%#,+). !SYNCHRONOUS &)&/ 42!#%#+ 40)5 FORMATTER 4RACE OUT SERIALIZER 42!#%$!4! ;= !SYNCHRONOUS &)&/ )4- 42!#%37/ %XTERNAL 00" BUS AI 44.17.2 TRACE pin assignment • Asynchronous mode The asynchronous mode requires 1 extra pin and is available on all packages. It is only available if using Serial Wire mode (not in JTAG mode). Table 272. Asynchronous TRACE pin assignment Trace synchronous mode TPUI pin name Type TRACESWO • O Description TRACE Asynchronous Data Output STM32L4x6 pin assignment PB3 Synchronous mode The synchronous mode requires from 2 to 6 extra pins depending on the data trace size and is only available in the larger packages. In addition it is available in JTAG mode and in Serial Wire mode and provides better bandwidth output capabilities than asynchronous trace. 1662/1680 DocID024597 Rev 1 RM0351 Debug support (DBG) Table 273. Synchronous TRACE pin assignment Trace synchronous mode STM32L4x6 pin assignment TPUI pin name Type Description TRACECK O TRACE Clock PE2 TRACED[3:0] O TRACE Synchronous Data Outputs Can be 1, 2 or 4. PE[6:3] TPUI TRACE pin assignment By default, these pins are NOT assigned. They can be assigned by setting the TRACE_IOEN and TRACE_MODE bits in the Debug MCU configuration register (DBGMCU_CR). This configuration has to be done by the debugger host. In addition, the number of pins to assign depends on the trace configuration (asynchronous or synchronous). • Asynchronous mode: 1 extra pin is needed • Synchronous mode: from 2 to 5 extra pins are needed depending on the size of the data trace port register (1, 2 or 4) : – TRACECK – TRACED(0) if port size is configured to 1, 2 or 4 – TRACED(1) if port size is configured to 2 or 4 – TRACED(2) if port size is configured to 4 – TRACED(3) if port size is configured to 4 To assign the TRACE pin, the debugger host must program the bits TRACE_IOEN and TRACE_MODE[1:0] of the Debug MCU configuration register (DBGMCU_CR). By default the TRACE pins are not assigned. This register is mapped on the external PPB and is reset by the PORESET (and not by the SYSTEM reset). It can be written by the debugger under SYSTEM reset. Table 274. Flexible TRACE pin assignment DBGMCU_CR register TRACE IO pin assigned Pins TRACE assigned for: TRACE PB3 / JTDO/ PE2 / PE3 / PE4 / PE5 / PE6 / _MODE _IOEN TRACESWO TRACECK TRACED[0] TRACED[1] TRACED[2] TRACED[3] [1:0] 0 XX No Trace (default state) 1 00 Asynchronous TRACESWO Trace Released (1) - DocID024597 Rev 1 - Released (usable as GPIO) 1663/1680 1669 Debug support (DBG) RM0351 Table 274. Flexible TRACE pin assignment (continued) DBGMCU_CR register TRACE IO pin assigned Pins TRACE assigned for: TRACE PB3 / JTDO/ PE2 / PE3 / PE4 / PE5 / PE6 / _MODE _IOEN TRACESWO TRACECK TRACED[0] TRACED[1] TRACED[2] TRACED[3] [1:0] 1 01 Synchronous Trace 1 bit 1 10 Synchronous Trace 2 bit 1 11 Synchronous Trace 4 bit TRACECK TRACED[0] Released (1) - TRACECK TRACED[0] TRACED[1] - - - - TRACECK TRACED[0] TRACED[1] TRACED[2] TRACED[3] 1. When Serial Wire mode is used, it is released, but when JTAG is used, it is assigned to JTDO. Note: By default, the TRACECLKIN input clock of the TPIU is tied to GND. It is assigned to HCLK two clock cycles after the bit TRACE_IOEN has been set. The debugger must then program the Trace Mode by writing the PROTOCOL[1:0] bits in the SPP_R (Selected Pin Protocol) register of the TPIU. • PROTOCOL=00: Trace Port Mode (synchronous) • PROTOCOL=01 or 10: Serial Wire (Manchester or NRZ) Mode (asynchronous mode). Default state is 01 It then also configures the TRACE port size by writing the bits [3:0] in the CPSPS_R (Current Synchronous Port Size Register) of the TPIU: 44.17.3 • 0x1 for 1 pin (default state) • 0x2 for 2 pins • 0x8 for 4 pins TPUI formatter The formatter protocol outputs data in 16-byte frames: • seven bytes of data • eight bytes of mixed-use bytes consisting of: • Note: 1664/1680 – 1 bit (LSB) to indicate it is a DATA byte (‘0) or an ID byte (‘1). – 7 bits (MSB) which can be data or change of source ID trace. one byte of auxiliary bits where each bit corresponds to one of the eight mixed-use bytes: – if the corresponding byte was a data, this bit gives bit0 of the data. – if the corresponding byte was an ID change, this bit indicates when that ID change takes effect. Refer to the ARM® CoreSight Architecture Specification v1.0 (ARM IHI 0029B) for further information DocID024597 Rev 1 RM0351 44.17.4 Debug support (DBG) TPUI frame synchronization packets The TPUI can generate two types of synchronization packets: • The Frame Synchronization packet (or Full Word Synchronization packet) It consists of the word: 0x7F_FF_FF_FF (LSB emitted first). This sequence can not occur at any other time provided that the ID source code 0x7F has not been used. It is output periodically between frames. In continuous mode, the TPA must discard all these frames once a synchronization frame has been found. • The Half-Word Synchronization packet It consists of the half word: 0x7F_FF (LSB emitted first). It is output periodically between or within frames. These packets are only generated in continuous mode and enable the TPA to detect that the TRACE port is in IDLE mode (no TRACE to be captured). When detected by the TPA, it must be discarded. 44.17.5 Transmission of the synchronization frame packet There is no Synchronization Counter register implemented in the TPIU of the core. Consequently, the synchronization trigger can only be generated by the DWT. Refer to the registers DWT Control Register (bits SYNCTAP[11:10]) and the DWT Current PC Sampler Cycle Count Register. The TPUI Frame synchronization packet (0x7F_FF_FF_FF) is emitted: 44.17.6 • after each TPIU reset release. This reset is synchronously released with the rising edge of the TRACECLKIN clock. This means that this packet is transmitted when the TRACE_IOEN bit in the DBGMCU_CFG register is set. In this case, the word 0x7F_FF_FF_FF is not followed by any formatted packet. • at each DWT trigger (assuming DWT has been previously configured). Two cases occur: – If the bit SYNENA of the ITM is reset, only the word 0x7F_FF_FF_FF is emitted without any formatted stream which follows. – If the bit SYNENA of the ITM is set, then the ITM synchronization packets will follow (0x80_00_00_00_00_00), formatted by the TPUI (trace source ID added). Synchronous mode The trace data output size can be configured to 4, 2 or 1 pin: TRACED(3:0) The output clock is output to the debugger (TRACECK) Here, TRACECLKIN is driven internally and is connected to HCLK only when TRACE is used. Note: In this synchronous mode, it is not required to provide a stable clock frequency. The TRACE I/Os (including TRACECK) are driven by the rising edge of TRACLKIN (equal to HCLK). Consequently, the output frequency of TRACECK is equal to HCLK/2. DocID024597 Rev 1 1665/1680 1669 Debug support (DBG) 44.17.7 RM0351 Asynchronous mode This is a low cost alternative to output the trace using only 1 pin: this is the asynchronous output pin TRACESWO. Obviously there is a limited bandwidth. TRACESWO is multiplexed with JTDO when using the SW-DP pin. This way, this functionality is available in all STM32L4x6 packages. This asynchronous mode requires a constant frequency for TRACECLKIN. For the standard UART (NRZ) capture mechanism, 5% accuracy is needed. The Manchester encoded version is tolerant up to 10%. 44.17.8 TRACECLKIN connection inside the STM32L4x6 In the STM32L4x6, this TRACECLKIN input is internally connected to HCLK. This means that when in asynchronous trace mode, the application is restricted to use time frames where the CPU frequency is stable. Note: Important: when using asynchronous trace: it is important to be aware that: The default clock of the STM32L4x6 MCUs is the internal RC oscillator. Its frequency under reset is different from the one after reset release. This is because the RC calibration is the default one under system reset and is updated at each system reset release. Consequently, the trace port analyzer (TPA) should not enable the trace (with the TRACE_IOEN bit) under system reset, because a Synchronization Frame Packet will be issued with a different bit time than trace packets which will be transmitted after reset release. 1666/1680 DocID024597 Rev 1 RM0351 44.17.9 Debug support (DBG) TPIU registers The TPIU APB registers can be read and written only if the bit TRCENA of the Debug Exception and Monitor Control Register (DEMCR) is set. Otherwise, the registers are read as zero (the output of this bit enables the PCLK of the TPIU). Table 275. Important TPIU registers Address Register 0xE0040004 Current port size Description Allows the trace port size to be selected: Bit 0: Port size = 1 Bit 1: Port size = 2 Bit 2: Port size = 3, not supported Bit 3: Port Size = 4 Only 1 bit must be set. By default, the port size is one bit. (0x00000001) Selected pin protocol Allows the Trace Port Protocol to be selected: Bit1:0 = 00: Synchronous Trace Port Mode 01: Serial Wire Output - manchester (default value) 10: Serial Wire Output - NRZ 11: reserved 0xE0040304 Formatter and flush control Bit 31-9 = always ‘0’ Bit 8 = TrigIn = always ‘1’ to indicate that triggers are indicated Bit 7-4 = always 0 Bit 3-2 = always 0 Bit 1 = EnFCont. In Synchronous Trace mode (Select_Pin_Protocol register bit1:0 = 00), this bit is forced to ‘1’: the formatter is automatically enabled in continuous mode. In asynchronous mode (Select_Pin_Protocol register bit1:0 <> 00), this bit can be written to activate or not the formatter. Bit 0 = always ‘0’ The resulting default value is 0x102 Note: In synchronous mode, because the TRACECTL pin is not mapped outside the chip, the formatter is always enabled in continuous mode; this way the formatter inserts some control packets to identify the source of the trace packets). 0xE0040300 Formatter and flush status Not used in Cortex®-M4, always read as 0x00000008 0xE00400F0 DocID024597 Rev 1 1667/1680 1669 Debug support (DBG) RM0351 44.17.10 Example of configuration 1668/1680 • Set the bit TRCENA in the Debug Exception and Monitor Control Register (DEMCR) • Write the TPIU Current Port Size Register to the desired value (default is 0x1 for a 1-bit port size) • Write TPIU Formatter and Flush Control Register to 0x102 (default value) • Write the TPIU Select Pin Protocol to select the synchronous or asynchronous mode. Example: 0x2 for asynchronous NRZ mode (UART like) • Write the DBGMCU control register to 0x20 (bit IO_TRACEN) to assign TRACE I/Os for asynchronous mode. A TPIU Synchronous packet is emitted at this time (FF_FF_FF_7F) • Configure the ITM and write the ITM Stimulus register to output a value DocID024597 Rev 1 0xE004 2010 1. DBGMCU_ APB2FZR DBG_TIM15_STOP 0 0 0 DocID024597 Rev 1 0 Reset value Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. X X X X Res. Res. DBG_STOP 0 DBG_SLEEP 0 0 0 0 DBG_TIM2_STOP 0 DBG_TIM3_STOP 0 DBG_STANDBY 0 DBG_TIM4_STOP X DBG_TIM5_STOP X TRACE_IOEN X Res. Res. X Res. Reset value DBG_TIM6_STOP X DBG_TIM7_STOP X Res. X DBG_LPTIM2_STOP X Res. X Res. X TRACE_MODE[1:0] X Res. X Res. X Res. Res. Res. Res. X Res. Res. X Res. Res. Res. X Res. Res. Res. X Res. Res. Res. REV_ID Res. DBG_RTC_STOP Res. Res. DBG_WWDG_STOP 0 Res. DBG_IWDG_STOP Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. DBG_TIM1_STOP Res. DBG_TIM8_STOP Res. Res. DBG_TIM16_STOP Res. Res. 0 Res. DBG_I2C1_STOP 0 Res. Res. X X X X Res. Res. DBG_I2C2_STOP 0 Res. 0 Res. DBGMCU_CR Res. X DBG_I2C3_STOP X Res. X Res. X Res. DBG_CAN_STOP Res. X Res. Res. Res. Res. Res. Res. X Res. Res. Res. Res. Res. X Res. DBGMCU_ IDCODE DBG_TIM17_STOP Reset value Res. DBGMCU_ APB1FZR2 Res. Reset value(1) Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 . Res. 0 Res. Reset value Res. DBG_LPTIM1_STOP 0xE0042000 Register Res. DBGMCU_ APB1FZR1 Res. 0xE0042004 Addr. Res. 0xE004 2008 44.18 Res. 0xE004 200C RM0351 Debug support (DBG) DBG register map The following table summarizes the Debug registers Table 276. DBG register map and reset values DEV_ID 0 0 0 0 0 The reset value is product dependent. For more information, refer to Section 44.6.1: MCU device ID code. 1669/1680 1669 Device electronic signature 45 RM0351 Device electronic signature The device electronic signature is stored in the System memory area of the Flash memory module, and can be read using the debug interface or by the CPU. It contains factoryprogrammed identification and calibration data that allow the user firmware or other external devices to automatically match to the characteristics of the STM32L4x6 microcontroller. 45.1 Unique device ID register (96 bits) The unique device identifier is ideally suited: • for use as serial numbers (for example USB string serial numbers or other end applications) • for use as part of the security keys in order to increase the security of code in Flash memory while using and combining this unique ID with software cryptographic primitives and protocols before programming the internal Flash memory • to activate secure boot processes, etc. The 96-bit unique device identifier provides a reference number which is unique for any device and in any context. These bits cannot be altered by the user. Base address: 0x1FFF 7590 Address offset: 0x00 Read only = 0xXXXX XXXX where X is factory-programmed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UID[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r UID[15:0] r r r r r r r r r Bits 31:0 UID[31:0]: X and Y coordinates on the wafer expressed in BCD format 1670/1680 DocID024597 Rev 1 RM0351 Device electronic signature Address offset: 0x04 Read only = 0xXXXX XXXX where X is factory-programmed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UID[63:48] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r UID[47:32] r r r r r r r r r Bits 31:8 UID[63:40]: LOT_NUM[23:0] Lot number (ASCII encoded) Bits 7:0 UID[39:32]: WAF_NUM[7:0] Wafer number (8-bit unsigned number) Address offset: 0x08 Read only = 0xXXXX XXXX where X is factory-programmed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UID[95:80] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r UID[79:64] r r r r r r r r r Bits 31:0 UID[95:64]: LOT_NUM[55:24] Lot number (ASCII encoded) 45.2 Flash size data register Base address: 0x1FFF 75E0 Address offset: 0x00 Read only = 0xXXXX where X is factory-programmed 15 14 13 12 11 10 9 r r r r r r r 8 7 6 5 4 3 2 1 0 r r r r r r r FLASH_SIZE r r Bits 15:0 FLASH_SIZE[15:0]: Flash memory size This bitfield indicates the size of the device Flash memory expressed in Kbytes. As an example, 0x040 corresponds to 64 Kbytes. DocID024597 Rev 1 1671/1680 1672 Device electronic signature 45.3 RM0351 Package data register Base address: 0x1FFF 7500 Address offset: 0x00 Read only = 0xXXXX where X is factory-programmed 15 14 13 12 11 10 9 8 7 6 5 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 4 Bits 4:0 PKG[4:0]: Package type 00000: LQFP64 00010: LQFP100 00011: BGA132 00100: LQFP144, WLCSP81 or WLCSP72 Others: reserved 1672/1680 DocID024597 Rev 1 2 1 0 r r PKG[4:0] r Bits 15:5 Reserved, must be kept at reset value 3 r r Index RM0351 Index A ADCx_AWD2CR . . . . . . . . . . . . . . . . . . . . . .524 ADCx_AWD3CR . . . . . . . . . . . . . . . . . . . . . .525 ADCx_CALFACT . . . . . . . . . . . . . . . . . . . . . .526 ADCx_CCR . . . . . . . . . . . . . . . . . . . . . . . . . .530 ADCx_CDR . . . . . . . . . . . . . . . . . . . . . . . . . .533 ADCx_CFGR . . . . . . . . . . . . . . . . . . . . . . . . .506 ADCx_CFGR2 . . . . . . . . . . . . . . . . . . . . . . . .510 ADCx_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . .503 ADCx_CSR . . . . . . . . . . . . . . . . . . . . . . . . . .528 ADCx_DIFSEL . . . . . . . . . . . . . . . . . . . . . . . .525 ADCx_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . .520 ADCx_IER . . . . . . . . . . . . . . . . . . . . . . . . . . .501 ADCx_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . .499 ADCx_JDRy . . . . . . . . . . . . . . . . . . . . . . . . . .524 ADCx_JSQR . . . . . . . . . . . . . . . . . . . . . . . . .521 ADCx_OFRy . . . . . . . . . . . . . . . . . . . . . . . . .523 ADCx_SMPR1 . . . . . . . . . . . . . . . . . . . . . . . .511 ADCx_SMPR2 . . . . . . . . . . . . . . . . . . . . . . . .513 ADCx_SQR1 . . . . . . . . . . . . . . . . . . . . . . . . .516 ADCx_SQR2 . . . . . . . . . . . . . . . . . . . . . . . . .517 ADCx_SQR3 . . . . . . . . . . . . . . . . . . . . . . . . .518 ADCx_SQR4 . . . . . . . . . . . . . . . . . . . . . . . . .519 ADCx_TR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .513 ADCx_TR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .514 ADCx_TR3 . . . . . . . . . . . . . . . . . . . . . . . . . . .515 AES_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .731 AES_DINR . . . . . . . . . . . . . . . . . . . . . . . . . . .735 AES_DOUTR . . . . . . . . . . . . . . . . . . . . . . . . .735 AES_IVR0 . . . . . . . . . . . . . . . . . . . . . . . . . . .737 AES_IVR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .738 AES_IVR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .739 AES_IVR3 . . . . . . . . . . . . . . . . . . . . . . . . . . .739 AES_KEYR0 . . . . . . . . . . . . . . . . . . . . . . . . .736 AES_KEYR1 . . . . . . . . . . . . . . . . . . . . . . . . .736 AES_KEYR2 . . . . . . . . . . . . . . . . . . . . . . . . .737 AES_KEYR3 . . . . . . . . . . . . . . . . . . . . . . . . .737 AES_KEYR4 . . . . . . . . . . . . . . . . . . . . . . . . .739 AES_KEYR5 . . . . . . . . . . . . . . . . . . . . . . . . .740 AES_KEYR6 . . . . . . . . . . . . . . . . . . . . . . . . .740 AES_KEYR7 . . . . . . . . . . . . . . . . . . . . . . . . .740 AES_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .733 AES_SUSPxR . . . . . . . . . . . . . . . . . . . . . . . .742 C CAN_BTR . . . . . . . . . . . . . . . . . . . . . . . . . .1470 CAN_ESR . . . . . . . . . . . . . . . . . . . . . . . . . .1469 1673/1680 CAN_FA1R . . . . . . . . . . . . . . . . . . . . . . . . . 1480 CAN_FFA1R . . . . . . . . . . . . . . . . . . . . . . . . 1480 CAN_FiRx . . . . . . . . . . . . . . . . . . . . . . . . . . 1481 CAN_FM1R . . . . . . . . . . . . . . . . . . . . . . . . . 1479 CAN_FMR . . . . . . . . . . . . . . . . . . . . . . . . . . 1478 CAN_FS1R . . . . . . . . . . . . . . . . . . . . . . . . . 1479 CAN_IER . . . . . . . . . . . . . . . . . . . . . . . . . . . 1468 CAN_MCR . . . . . . . . . . . . . . . . . . . . . . . . . . 1461 CAN_MSR . . . . . . . . . . . . . . . . . . . . . . . . . . 1463 CAN_RDHxR . . . . . . . . . . . . . . . . . . . . . . . . 1477 CAN_RDLxR . . . . . . . . . . . . . . . . . . . . . . . . 1477 CAN_RDTxR . . . . . . . . . . . . . . . . . . . . . . . . 1476 CAN_RF0R . . . . . . . . . . . . . . . . . . . . . . . . . 1466 CAN_RF1R . . . . . . . . . . . . . . . . . . . . . . . . . 1467 CAN_RIxR . . . . . . . . . . . . . . . . . . . . . . . . . . 1475 CAN_TDHxR . . . . . . . . . . . . . . . . . . . . . . . . 1474 CAN_TDLxR . . . . . . . . . . . . . . . . . . . . . . . . 1474 CAN_TDTxR . . . . . . . . . . . . . . . . . . . . . . . . 1473 CAN_TIxR . . . . . . . . . . . . . . . . . . . . . . . . . . 1472 CAN_TSR . . . . . . . . . . . . . . . . . . . . . . . . . . 1464 COMP1_CSR . . . . . . . . . . . . . . . . . . . . . . . . 577 COMP2_CSR . . . . . . . . . . . . . . . . . . . . . . . . 579 CRC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 CRC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 CRC_IDR . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 CRC_INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 CRC_POL . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 D DAC_CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 DAC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 DAC_DHR12L1 . . . . . . . . . . . . . . . . . . . . . . . 556 DAC_DHR12L2 . . . . . . . . . . . . . . . . . . . . . . . 558 DAC_DHR12LD . . . . . . . . . . . . . . . . . . . . . . 559 DAC_DHR12R1 . . . . . . . . . . . . . . . . . . . . . . 556 DAC_DHR12R2 . . . . . . . . . . . . . . . . . . . . . . 557 DAC_DHR12RD . . . . . . . . . . . . . . . . . . . . . . 558 DAC_DHR8R1 . . . . . . . . . . . . . . . . . . . . . . . 557 DAC_DHR8R2 . . . . . . . . . . . . . . . . . . . . . . . 558 DAC_DHR8RD . . . . . . . . . . . . . . . . . . . . . . . 560 DAC_DOR1 . . . . . . . . . . . . . . . . . . . . . . . . . . 560 DAC_DOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 560 DAC_MCR . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 DAC_SHHR . . . . . . . . . . . . . . . . . . . . . . . . . . 564 DAC_SHRR . . . . . . . . . . . . . . . . . . . . . . . . . . 565 DAC_SHSR1 . . . . . . . . . . . . . . . . . . . . . . . . . 563 DAC_SHSR2 . . . . . . . . . . . . . . . . . . . . . . . . . 564 DAC_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 DocID024597 Rev 1 RM0351 Index DAC_SWTRIGR . . . . . . . . . . . . . . . . . . . . . . .556 DBGMCU_APB1FZR1 . . . . . . . . . . . . . . . . .1658 DBGMCU_APB1FZR2 . . . . . . . . . . . . . . . . .1660 DBGMCU_APB2FZR . . . . . . . . . . . . . . . . . .1661 DBGMCU_CR . . . . . . . . . . . . . . . . . . . . . . .1656 DBGMCU_IDCODE . . . . . . . . . . . . . . . . . . .1643 DFSDM_AWSCDyR . . . . . . . . . . . . . . . . . . . .625 DFSDM_CHCFGyR1 . . . . . . . . . . . . . . . . . . .622 DFSDM_CHCFGyR2 . . . . . . . . . . . . . . . . . . .624 DFSDM_CHDATINyR . . . . . . . . . . . . . . . . . .626 DFSDM_CHWDATyR . . . . . . . . . . . . . . . . . .626 DFSDMx_AWCFR . . . . . . . . . . . . . . . . . . . . .638 DFSDMx_AWHTR . . . . . . . . . . . . . . . . . . . . .637 DFSDMx_AWLTR . . . . . . . . . . . . . . . . . . . . .637 DFSDMx_AWSR . . . . . . . . . . . . . . . . . . . . . .638 DFSDMx_CNVTIMR . . . . . . . . . . . . . . . . . . .640 DFSDMx_CR1 . . . . . . . . . . . . . . . . . . . . . . . .627 DFSDMx_CR2 . . . . . . . . . . . . . . . . . . . . . . . .630 DFSDMx_EXMAX . . . . . . . . . . . . . . . . . . . . .639 DFSDMx_EXMIN . . . . . . . . . . . . . . . . . . . . . .639 DFSDMx_FCR . . . . . . . . . . . . . . . . . . . . . . . .634 DFSDMx_ICR . . . . . . . . . . . . . . . . . . . . . . . .633 DFSDMx_ISR . . . . . . . . . . . . . . . . . . . . . . . . .631 DFSDMx_JCHGR . . . . . . . . . . . . . . . . . . . . .634 DFSDMx_JDATAR . . . . . . . . . . . . . . . . . . . . .635 DFSDMx_RDATAR . . . . . . . . . . . . . . . . . . . .636 DMA_CCRx . . . . . . . . . . . . . . . . . . . . . . . . . .314 DMA_CMARx . . . . . . . . . . . . . . . . . . . . . . . . .317 DMA_CNDTRx . . . . . . . . . . . . . . . . . . . . . . . .316 DMA_CPARx . . . . . . . . . . . . . . . . . . . . . . . . .316 DMA_IFCR . . . . . . . . . . . . . . . . . . . . . . . . . . .313 DMA_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 DMA1_CSELR . . . . . . . . . . . . . . . . . . . . . . . .318 DMA2_CSELR . . . . . . . . . . . . . . . . . . . . . . . .320 E EXTI_EMR1 . . . . . . . . . . . . . . . . . . . . . . . . . .334 EXTI_EMR2 . . . . . . . . . . . . . . . . . . . . . . . . . .338 EXTI_FTSR1 . . . . . . . . . . . . . . . . . . . . . . . . .335 EXTI_FTSR2 . . . . . . . . . . . . . . . . . . . . . . . . .339 EXTI_IMR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .334 EXTI_IMR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .337 EXTI_PR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .337 EXTI_PR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .340 EXTI_RTSR1 . . . . . . . . . . . . . . . . . . . . . . . . .335 EXTI_RTSR2 . . . . . . . . . . . . . . . . . . . . . . . . .338 EXTI_SWIER1 . . . . . . . . . . . . . . . . . . . . . . . .336 EXTI_SWIER2 . . . . . . . . . . . . . . . . . . . . . . . .339 F FLASH_ACR . . . . . . . . . . . . . . . . . . . . . . . . .106 FLASH_CR . . . . . . . . . . . . . . . . . . . . . . . . . . 110 FLASH_ECCR . . . . . . . . . . . . . . . . . . . . . . . . 112 FLASH_KEYR . . . . . . . . . . . . . . . . . . . . . . . . 107 FLASH_OPTKEYR . . . . . . . . . . . . . . . . . . . . 108 FLASH_OPTR . . . . . . . . . . . . . . . . . . . . . . . . 113 FLASH_PCROP1ER . . . . . . . . . . . . . . . . . . . 115 FLASH_PCROP1SR . . . . . . . . . . . . . . . . . . . 114 FLASH_PCROP2ER . . . . . . . . . . . . . . . . . . . 117 FLASH_PCROP2SR . . . . . . . . . . . . . . . . . . . 116 FLASH_PDKEYR . . . . . . . . . . . . . . . . . . . . . 107 FLASH_SR . . . . . . . . . . . . . . . . . . . . . . . . . . 108 FLASH_WRP1AR . . . . . . . . . . . . . . . . . . . . . 115 FLASH_WRP1BR . . . . . . . . . . . . . . . . . . . . . 116 FLASH_WRP2AR . . . . . . . . . . . . . . . . . . . . . 117 FLASH_WRP2BR . . . . . . . . . . . . . . . . . . . . . 118 FMC_BCR1..4 . . . . . . . . . . . . . . . . . . . . . . . . 376 FMC_BTR1..4 . . . . . . . . . . . . . . . . . . . . . . . . 378 FMC_BWTR1..4 . . . . . . . . . . . . . . . . . . . . . . 381 FMC_ECCR . . . . . . . . . . . . . . . . . . . . . . . . . 394 FMC_PATT . . . . . . . . . . . . . . . . . . . . . . . . . . 392 FMC_PCR . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 FMC_PMEM . . . . . . . . . . . . . . . . . . . . . . . . . 391 FMC_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 FMPI2C_ISR . . . . . . . . . . . . . . . . . . . . . . . . 1161 FW_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 FW_CSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 FW_CSSA . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 FW_NVDSL . . . . . . . . . . . . . . . . . . . . . . . . . . 129 FW_NVDSSA . . . . . . . . . . . . . . . . . . . . . . . . 129 FW_VDSL . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 FW_VDSSA . . . . . . . . . . . . . . . . . . . . . . . . . . 130 G GPIOx_AFRH . . . . . . . . . . . . . . . . . . . . . . . . 283 GPIOx_AFRL . . . . . . . . . . . . . . . . . . . . . . . . 282 GPIOx_ASCR . . . . . . . . . . . . . . . . . . . . . . . . 283 GPIOx_BRR . . . . . . . . . . . . . . . . . . . . . . . . . 283 GPIOx_BSRR . . . . . . . . . . . . . . . . . . . . . . . . 280 GPIOx_IDR . . . . . . . . . . . . . . . . . . . . . . . . . . 280 GPIOx_LCKR . . . . . . . . . . . . . . . . . . . . . . . . 281 GPIOx_MODER . . . . . . . . . . . . . . . . . . . . . . 278 GPIOx_ODR . . . . . . . . . . . . . . . . . . . . . . . . . 280 GPIOx_OSPEEDR . . . . . . . . . . . . . . . . . . . . 279 GPIOx_OTYPER . . . . . . . . . . . . . . . . . . . . . . 278 GPIOx_PUPDR . . . . . . . . . . . . . . . . . . . . . . . 279 I I2C_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151 I2C_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154 I2C_ICR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163 I2C_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161 DocID024597 Rev 1 1674/1680 Index RM0351 I2C_OAR1 . . . . . . . . . . . . . . . . . . . . . . . . . .1157 I2C_OAR2 . . . . . . . . . . . . . . . . . . . . . . . . . .1158 I2C_PECR . . . . . . . . . . . . . . . . . . . . . . . . . .1164 I2C_RXDR . . . . . . . . . . . . . . . . . . . . . . . . . .1165 I2C_TIMEOUTR . . . . . . . . . . . . . . . . . . . . . .1160 I2C_TIMINGR . . . . . . . . . . . . . . . . . . . . . . .1159 I2C_TXDR . . . . . . . . . . . . . . . . . . . . . . . . . .1165 I2Cx_CR2 . . . . . . . . . . . . . . . . . . . 128-131, 1154 IWDG_KR . . . . . . . . . . . . . . . . . . . . . . . . . .1040 IWDG_PR . . . . . . . . . . . . . . . . . . . . . . . . . .1041 IWDG_RLR . . . . . . . . . . . . . . . . . . . . . . . . .1042 IWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . .1043 IWDG_WINR . . . . . . . . . . . . . . . . . . . . . . . .1044 L LCD_CLR . . . . . . . . . . . . . . . . . . . . . . . . . . . .680 LCD_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .673 LCD_RAM . . . . . . . . . . . . . . . . . . . . . . . . . . .680 LPTIM1_OR . . . . . . . . . . . . . . . . . . . . . . . . .1034 LPTIM2_OR . . . . . . . . . . . . . . . . . . . . . . . . .1034 LPTIMx_ARR . . . . . . . . . . . . . . . . . . . . . . . .1033 LPTIMx_CFGR . . . . . . . . . . . . . . . . . . . . . . .1029 LPTIMx_CMP . . . . . . . . . . . . . . . . . . . . . . . .1033 LPTIMx_CNT . . . . . . . . . . . . . . . . . . . . . . . .1034 LPTIMx_CR . . . . . . . . . . . . . . . . . . . . . . . . .1032 LPTIMx_ICR . . . . . . . . . . . . . . . . . . . . . . . . .1027 LPTIMx_IER . . . . . . . . . . . . . . . . . . . . . . . . .1028 LPTIMx_ISR . . . . . . . . . . . . . . . . . . . . . . . . .1026 LPUART_BRR . . . . . . . . . . . . . . . . . . . . . . .1265 LPUART_CR1 . . . . . . . . . . . . . . . . . . . . . . .1258 LPUART_CR2 . . . . . . . . . . . . . . . . . . . . . . .1261 LPUART_CR3 . . . . . . . . . . . . . . . . . . . . . . .1263 LPUART_ICR . . . . . . . . . . . . . . . . . . . . . . . .1269 LPUART_ISR . . . . . . . . . . . . . . . . . . . . . . . .1266 LPUART_RDR . . . . . . . . . . . . . . . . . . . . . . .1270 LPUART_RQR . . . . . . . . . . . . . . . . . . . . . . .1265 LPUART_TDR . . . . . . . . . . . . . . . . . . . . . . .1270 O OPAMP1_CSR . . . . . . . . . . . . . . . . . . . . . . . .590 OPAMP1_LPOTR . . . . . . . . . . . . . . . . . . . . .591 OPAMP1_OTR . . . . . . . . . . . . . . . . . . . . . . . .591 OPAMP2_CSR . . . . . . . . . . . . . . . . . . . . . . . .592 OPAMP2_LPOTR . . . . . . . . . . . . . . . . . . . . .593 OPAMP2_OTR . . . . . . . . . . . . . . . . . . . . . . . .593 OTG_CID . . . . . . . . . . . . . . . . . . . . . . . . . . .1534 OTG_DAINT . . . . . . . . . . . . . . . . . . . . . . . . .1559 OTG_DAINTMSK . . . . . . . . . . . . . . . . . . . . .1560 OTG_DCFG . . . . . . . . . . . . . . . . . . . . . . . . .1554 OTG_DCTL . . . . . . . . . . . . . . . . . . . . . . . . .1555 OTG_DIEPCTL0 . . . . . . . . . . . . . . . . . . . . .1562 1675/1680 OTG_DIEPCTLx . . . . . . . . . . . . . . . . . . . . . 1564 OTG_DIEPEMPMSK . . . . . . . . . . . . . . . . . . 1562 OTG_DIEPINTx . . . . . . . . . . . . . . . . . . . . . . 1570 OTG_DIEPMSK . . . . . . . . . . . . . . . . . . . . . 1558 OTG_DIEPTSIZ0 . . . . . . . . . . . . . . . . . . . . 1572 OTG_DIEPTSIZx . . . . . . . . . . . . . . . . . . . . . 1574 OTG_DIEPTXF0 . . . . . . . . . . . . . . . . . . . . . 1531 OTG_DIEPTXFx . . . . . . . . . . . . . . . . . . . . . 1542 OTG_DOEPCTL0 . . . . . . . . . . . . . . . . . . . . 1566 OTG_DOEPCTLx . . . . . . . . . . . . . . . . . . . . 1568 OTG_DOEPINTx . . . . . . . . . . . . . . . . . . . . . 1571 OTG_DOEPMSK . . . . . . . . . . . . . . . . . . . . . 1559 OTG_DOEPTSIZ0 . . . . . . . . . . . . . . . . . . . . 1573 OTG_DOEPTSIZx . . . . . . . . . . . . . . . . . . . . 1575 OTG_DSTS . . . . . . . . . . . . . . . . . . . . . . . . . 1557 OTG_DTXFSTSx . . . . . . . . . . . . . . . . . . . . 1575 OTG_DVBUSDIS . . . . . . . . . . . . . . . . . . . . 1561 OTG_DVBUSPULSE . . . . . . . . . . . . . . . . . 1561 OTG_GADPCTL . . . . . . . . . . . . . . . . . . . . . 1539 OTG_GAHBCFG . . . . . . . . . . . . . . . . . . . . . 1517 OTG_GCCFG . . . . . . . . . . . . . . . . . . . . . . . 1533 OTG_GINTMSK . . . . . . . . . . . . . . . . . . . . . 1525 OTG_GINTSTS . . . . . . . . . . . . . . . . . . . . . . 1521 OTG_GLPMCFG . . . . . . . . . . . . . . . . . . . . . 1535 OTG_GOTGCTL . . . . . . . . . . . . . . . . . . . . . 1513 OTG_GOTGINT . . . . . . . . . . . . . . . . . . . . . 1515 OTG_GPWRDN . . . . . . . . . . . . . . . . . . . . . 1539 OTG_GRSTCTL . . . . . . . . . . . . . . . . . . . . . 1519 OTG_GRXFSIZ . . . . . . . . . . . . . . . . . . . . . . 1530 OTG_GRXSTSP . . . . . . . . . . . . . . . . . . . . . 1528 OTG_GRXSTSR . . . . . . . . . . . . . . . . . . . . . 1528 OTG_GUSBCFG . . . . . . . . . . . . . . . . . . . . . 1517 OTG_HAINT . . . . . . . . . . . . . . . . . . . . . . . . 1546 OTG_HAINTMSK . . . . . . . . . . . . . . . . . . . . 1546 OTG_HCCHARx . . . . . . . . . . . . . . . . . . . . . 1549 OTG_HCFG . . . . . . . . . . . . . . . . . . . . . . . . 1542 OTG_HCINTMSKx . . . . . . . . . . . . . . . . . . . 1552 OTG_HCINTx . . . . . . . . . . . . . . . . . . . . . . . 1551 OTG_HCTSIZx . . . . . . . . . . . . . . . . . . . . . . 1553 OTG_HFIR . . . . . . . . . . . . . . . . . . . . . . . . . 1543 OTG_HFNUM . . . . . . . . . . . . . . . . . . . . . . . 1544 OTG_HNPTXFSIZ . . . . . . . . . . . . . . . . . . . . 1531 OTG_HNPTXSTS . . . . . . . . . . . . . . . . . . . . 1532 OTG_HPRT . . . . . . . . . . . . . . . . . . . . . . . . . 1547 OTG_HPTXFSIZ . . . . . . . . . . . . . . . . . . . . . 1541 OTG_HPTXSTS . . . . . . . . . . . . . . . . . . . . . 1545 OTG_PCGCCTL . . . . . . . . . . . . . . . . . . . . . 1576 P purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923 PWR_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 DocID024597 Rev 1 RM0351 Index PWR_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .167 PWR_CR3 . . . . . . . . . . . . . . . . . . . . . . . . . . .168 PWR_CR4 . . . . . . . . . . . . . . . . . . . . . . . . . . .169 PWR_PDCRA . . . . . . . . . . . . . . . . . . . . . . . .174 PWR_PDCRB . . . . . . . . . . . . . . . . . . . . . . . .175 PWR_PDCRC . . . . . . . . . . . . . . . . . . . . . . . .176 PWR_PDCRD . . . . . . . . . . . . . . . . . . . . . . . .177 PWR_PDCRE . . . . . . . . . . . . . . . . . . . . . . . .178 PWR_PDCRF . . . . . . . . . . . . . . . . . . . . . . . .178 PWR_PDCRG . . . . . . . . . . . . . . . . . . . . . . . .179 PWR_PDCRH . . . . . . . . . . . . . . . . . . . . . . . .180 PWR_PUCRA . . . . . . . . . . . . . . . . . . . . . . . .173 PWR_PUCRB . . . . . . . . . . . . . . . . . . . . . . . .174 PWR_PUCRC . . . . . . . . . . . . . . . . . . . . . . . .175 PWR_PUCRD . . . . . . . . . . . . . . . . . . . . . . . .176 PWR_PUCRE . . . . . . . . . . . . . . . . . . . . . . . .177 PWR_PUCRF . . . . . . . . . . . . . . . . . . . . . . . .178 PWR_PUCRG . . . . . . . . . . . . . . . . . . . . . . . .179 PWR_PUCRH . . . . . . . . . . . . . . . . . . . . . . . .180 PWR_SCR . . . . . . . . . . . . . . . . . . . . . . . . . . .173 PWR_SR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .170 PWR_SR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Q QUADSPI _PIR . . . . . . . . . . . . . . . . . . . . . . .420 QUADSPI _PSMAR . . . . . . . . . . . . . . . . . . . .420 QUADSPI _PSMKR . . . . . . . . . . . . . . . . . . . .419 QUADSPI_ABR . . . . . . . . . . . . . . . . . . . . . . .418 QUADSPI_AR . . . . . . . . . . . . . . . . . . . . . . . .418 QUADSPI_CCR . . . . . . . . . . . . . . . . . . . . . . .416 QUADSPI_CR . . . . . . . . . . . . . . . . . . . . . . . .411 QUADSPI_DCR . . . . . . . . . . . . . . . . . . . . . . .413 QUADSPI_DLR . . . . . . . . . . . . . . . . . . . . . . .416 QUADSPI_DR . . . . . . . . . . . . . . . . . . . . . . . .419 QUADSPI_FCR . . . . . . . . . . . . . . . . . . . . . . .415 QUADSPI_LPTR . . . . . . . . . . . . . . . . . . . . . .421 QUADSPI_SR . . . . . . . . . . . . . . . . . . . . . . . .414 RCC_APB1RSTR2 . . . . . . . . . . . . . . . . . . . . 236 RCC_APB1SMENR1 . . . . . . . . . . . . . . . . . . 251 RCC_APB1SMENR2 . . . . . . . . . . . . . . . . . . 253 RCC_APB2ENR . . . . . . . . . . . . . . . . . . . . . . 246 RCC_APB2RSTR . . . . . . . . . . . . . . . . . . . . . 237 RCC_APB2SMENR . . . . . . . . . . . . . . . . . . . 255 RCC_BDCR . . . . . . . . . . . . . . . . . . . . . . . . . 260 RCC_CCIPR . . . . . . . . . . . . . . . . . . . . . . . . . 257 RCC_CFGR . . . . . . . . . . . . . . . . . . . . . . . . . 214 RCC_CICR . . . . . . . . . . . . . . . . . . . . . . . . . . 229 RCC_CIER . . . . . . . . . . . . . . . . . . . . . . . . . . 225 RCC_CIFR . . . . . . . . . . . . . . . . . . . . . . . . . . 227 RCC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 RCC_CSR . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 RCC_ICSCR . . . . . . . . . . . . . . . . . . . . . . . . . 213 RCC_PLLCFGR . . . . . . . . . . . . . . . . . . . . . . 217 RCC_PLLSAI1CFGR . . . . . . . . . . . . . . . . . . 220 RCC_PLLSAI2CFGR . . . . . . . . . . . . . . . . . . 223 RNG_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 RNG_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 RNG_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 RTC_ALRMAR . . . . . . . . . . . . . . . . . . . . . . 1081 RTC_ALRMBR . . . . . . . . . . . . . . . . . . . . . . 1082 RTC_ALRMBSSR . . . . . . . . . . . . . . . . . . . . 1093 RTC_BKPxR . . . . . . . . . . . . . . . . . . . . . . . . 1095 RTC_CALR . . . . . . . . . . . . . . . . . . . . . . . . . 1088 RTC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073 RTC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072 RTC_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076 RTC_OR . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094 RTC_PRER . . . . . . . . . . . . . . . . . . . . . . . . . 1079 RTC_SHIFTR . . . . . . . . . . . . . . . . . . . . . . . 1084 RTC_SSR . . . . . . . . . . . . . . . . . . . . . . . . . . 1083 RTC_TR . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 RTC_TSDR . . . . . . . . . . . . . . . . . . . . . . . . . 1086 RTC_TSSSR . . . . . . . . . . . . . . . . . . . . . . . . 1087 RTC_TSTR . . . . . . . . . . . . . . . . . . . . . . . . . 1085 RTC_WPR . . . . . . . . . . . . . . . . . . . . . . . . . . 1083 RTC_WUTR . . . . . . . . . . . . . . . . . . . . . . . . 1080 R RCC_AHB1ENR . . . . . . . . . . . . . . . . . . . . . .238 RCC_AHB1RSTR . . . . . . . . . . . . . . . . . . . . .230 RCC_AHB1SMENR . . . . . . . . . . . . . . . . . . . .247 RCC_AHB2ENR . . . . . . . . . . . . . . . . . . . . . .239 RCC_AHB2RSTR . . . . . . . . . . . . . . . . . . . . .231 RCC_AHB2SMENR . . . . . . . . . . . . . . . . . . . .248 RCC_AHB3ENR . . . . . . . . . . . . . . . . . . . . . .241 RCC_AHB3RSTR . . . . . . . . . . . . . . . . . . . . .232 RCC_AHB3SMENR . . . . . . . . . . . . . . . . . . . .250 RCC_APB1ENR1 . . . . . . . . . . . . . . . . . . . . . .241 RCC_APB1ENR2 . . . . . . . . . . . . . . . . . . . . . .244 RCC_APB1RSTR1 . . . . . . . . . . . . . . . . . . . .234 S SDMMC_ARG . . . . . . . . . . . . . . . . . . . . . . . 1428 SDMMC_CLKCR . . . . . . . . . . . . . . . . . . . . . 1426 SDMMC_DCOUNT . . . . . . . . . . . . . . . . . . . 1433 SDMMC_DCTRL . . . . . . . . . . . . . . . . . . . . . 1431 SDMMC_DLEN . . . . . . . . . . . . . . . . . . . . . . 1431 SDMMC_DTIMER . . . . . . . . . . . . . . . . . . . . 1430 SDMMC_FIFO . . . . . . . . . . . . . . . . . . . . . . . 1439 SDMMC_ICR . . . . . . . . . . . . . . . . . . . . . . . . 1434 SDMMC_MASK . . . . . . . . . . . . . . . . . . . . . . 1436 SDMMC_POWER . . . . . . . . . . . . . . . . . . . . 1426 DocID024597 Rev 1 1676/1680 Index RM0351 SDMMC_RESPCMD . . . . . . . . . . . . . . . . . .1429 SDMMC_RESPx . . . . . . . . . . . . . . . . . . . . .1429 SDMMC_STA . . . . . . . . . . . . . . . . . . . . . . . .1433 SMPMI_IER . . . . . . . . . . . . . . . . . . . . . . . . .1378 SPIx_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . .1299 SPIx_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . .1301 SPIx_CRCPR . . . . . . . . . . . . . . . . . . . . . . . .1305 SPIx_DR . . . . . . . . . . . . . . . . . . . . . . . . . . .1305 SPIx_RXCRCR . . . . . . . . . . . . . . . . . . . . . .1306 SPIx_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . .1304 SPIx_TXCRCR . . . . . . . . . . . . . . . . . . . . . . .1306 SWPMI_BRR . . . . . . . . . . . . . . . . . . . . . . . .1374 SWPMI_CR . . . . . . . . . . . . . . . . . . . . . . . . .1372 SWPMI_ICR . . . . . . . . . . . . . . . . . . . . . . . . .1377 SWPMI_ISR . . . . . . . . . . . . . . . . . . . . . . . . .1375 SWPMI_OR . . . . . . . . . . . . . . . . . . . . . . . . .1382 SWPMI_RDR . . . . . . . . . . . . . . . . . . . . . . . .1381 SWPMI_RFL . . . . . . . . . . . . . . . . . . . . . . . .1379 SWPMI_TDR . . . . . . . . . . . . . . . . . . . . . . . .1380 SYSCFG_CFGR1 . . . . . . . . . . . . . . . . . . . . .288 SYSCFG_CFGR2 . . . . . . . . . . . . . . . . . . . . .297 SYSCFG_EXTICR1 . . . . . . . . . . . . . . . . . . . .290 SYSCFG_EXTICR2 . . . . . . . . . . . . . . . . . . . .292 SYSCFG_EXTICR3 . . . . . . . . . . . . . . . . . . . .293 SYSCFG_EXTICR4 . . . . . . . . . . . . . . . . . . . .295 SYSCFG_MEMRMP . . . . . . . . . . . . . . . . . . .287 SYSCFG_SCSR . . . . . . . . . . . . . . . . . . . . . .296 SYSCFG_SKR . . . . . . . . . . . . . . . . . . . . . . . .298 SYSCFG_SWPR . . . . . . . . . . . . . . . . . . . . . .297 T TIM1_OR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .834 TIM1_OR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .838 TIM1_OR3 . . . . . . . . . . . . . . . . . . . . . . . . . . .840 TIM15_ARR . . . . . . . . . . . . . . . . . . . . . . . . . .972 TIM15_BDTR . . . . . . . . . . . . . . . . . . . . . . . . .974 TIM15_CCER . . . . . . . . . . . . . . . . . . . . . . . . .969 TIM15_CCMR1 . . . . . . . . . . . . . . . . . . . . . . .966 TIM15_CCR1 . . . . . . . . . . . . . . . . . . . . . . . . .973 TIM15_CCR2 . . . . . . . . . . . . . . . . . . . . . . . . .974 TIM15_CNT . . . . . . . . . . . . . . . . . . . . . . . . . .972 TIM15_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . .958 TIM15_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . .959 TIM15_DCR . . . . . . . . . . . . . . . . . . . . . . . . . .976 TIM15_DIER . . . . . . . . . . . . . . . . . . . . . . . . .962 TIM15_DMAR . . . . . . . . . . . . . . . . . . . . . . . .976 TIM15_EGR . . . . . . . . . . . . . . . . . . . . . . . . . .965 TIM15_OR1 . . . . . . . . . . . . . . . . . . . . . . . . . .977 TIM15_OR2 . . . . . . . . . . . . . . . . . . . . . . . . . .977 TIM15_PSC . . . . . . . . . . . . . . . . . . . . . . . . . .972 TIM15_RCR . . . . . . . . . . . . . . . . . . . . . . . . . .973 1677/1680 TIM15_SMCR . . . . . . . . . . . . . . . . . . . . . . . . 961 TIM15_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . 963 TIM16_OR1 . . . . . . . . . . . . . . . . . . . . . . . . . . 996 TIM16_OR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 997 TIM17_OR1 . . . . . . . . . . . . . . . . . . . . . . . . . . 998 TIM17_OR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 999 TIM2_OR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 917 TIM2_OR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 918 TIM3_OR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 918 TIM3_OR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 919 TIM8_OR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 TIM8_OR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 TIM8_OR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 843 TIMx_ARR . . . . . . . . . . . . . . 826, 914, 992, 1014 TIMx_BDTR . . . . . . . . . . . . . . . . . . . . . . 829, 994 TIMx_CCER . . . . . . . . . . . . . . . . . 822, 911, 989 TIMx_CCMR1 . . . . . . . . . . . . . . . . 816, 906, 987 TIMx_CCMR2 . . . . . . . . . . . . . . . . . . . . 821, 910 TIMx_CCMR3 . . . . . . . . . . . . . . . . . . . . . . . . 836 TIMx_CCR1 . . . . . . . . . . . . . . . . . . 827, 914, 993 TIMx_CCR2 . . . . . . . . . . . . . . . . . . . . . . 828, 915 TIMx_CCR3 . . . . . . . . . . . . . . . . . . . . . . 828, 915 TIMx_CCR4 . . . . . . . . . . . . . . . . . . . . . . 829, 916 TIMx_CCR5 . . . . . . . . . . . . . . . . . . . . . . . . . . 836 TIMx_CCR6 . . . . . . . . . . . . . . . . . . . . . . . . . . 838 TIMx_CNT . . . . . . . . . . . . . . 826, 913, 991, 1013 TIMx_CR1 . . . . . . . . . . . . . . 805, 895, 982, 1010 TIMx_CR2 . . . . . . . . . . . . . . 806, 897, 983, 1012 TIMx_DCR . . . . . . . . . . . . . . . . . . . 833, 917, 996 TIMx_DIER . . . . . . . . . . . . . 812, 902, 984, 1012 TIMx_DMAR . . . . . . . . . . . . . . . . . 834, 917, 996 TIMx_EGR . . . . . . . . . . . . . . 815, 905, 986, 1013 TIMx_PSC . . . . . . . . . . . . . . 826, 914, 992, 1014 TIMx_RCR . . . . . . . . . . . . . . . . . . . . . . . 827, 993 TIMx_SMCR . . . . . . . . . . . . . . . . . . . . . 809, 898 TIMx_SR . . . . . . . . . . . . . . . 813, 903, 985, 1013 TSC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 TSC_ICR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 TSC_IER . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 TSC_IOASCR . . . . . . . . . . . . . . . . . . . . . . . . 698 TSC_IOCCR . . . . . . . . . . . . . . . . . . . . . . . . . 699 TSC_IOGCSR . . . . . . . . . . . . . . . . . . . . . . . . 699 TSC_IOGxCR . . . . . . . . . . . . . . . . . . . . . . . . 700 TSC_IOHCR . . . . . . . . . . . . . . . . . . . . . . . . . 697 TSC_IOSCR . . . . . . . . . . . . . . . . . . . . . . . . . 698 TSC_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 U USART_CR1 . . . . . . . . . . . . . . . . . . . . . . . . 1258 USARTx_BRR . . . . . . . . . . . . . . . . . . . . . . . 1223 USARTx_CR1 . . . . . . . . . . . . . . . . . . . . . . . 1212 DocID024597 Rev 1 Index RM0351 USARTx_CR2 . . . . . . . . . . . . . . . . . . . . . . . 1215 USARTx_CR3 . . . . . . . . . . . . . . . . . . . . . . . 1219 USARTx_GTPR . . . . . . . . . . . . . . . . . . . . . . 1223 USARTx_ICR . . . . . . . . . . . . . . . . . . . . . . . . 1231 USARTx_ISR . . . . . . . . . . . . . . . . . . . . . . . . 1226 USARTx_RDR . . . . . . . . . . . . . . . . . . . . . . . 1232 USARTx_RQR . . . . . . . . . . . . . . . . . . . . . . . 1225 USARTx_RTOR . . . . . . . . . . . . . . . . . . . . . . 1224 USARTx_TDR . . . . . . . . . . . . . . . . . . . . . . . 1232 W WWDG_CFR . . . . . . . . . . . . . . . . . . . . . . . . 1050 WWDG_CR . . . . . . . . . . . . . . . . . . . . . . . . . 1049 WWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . 1050 1678/1680 DocID024597 Rev 1 RM0351 46 Revision history Revision history Table 277. Document revision history Date Revision 28-May-2015 1 Changes Initial release. DocID024597 Rev 1 1679/1680 1679 RM0351 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 1680/1680 DocID024597 Rev 1
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No Author : STMICROELECTRONICS Create Date : 2015:05:28 09:05:22Z Keywords : Technical Literature, 024597, Product Development, Specification, Reference manual, STM32L476BL, STM32L476JE, STM32L476JG, STM32L476MG, STM32L476QG, STM32L476QE, STM32L476RC, STM32L476RE, STM32L476RG, STM32L476VC, STM32L476VE, STM32L476VG, STM32L476ZE, STM32L476ZG, STM32L486QG, STM32L486RG, STM32L486VG, STM32L486ZG, STM32L486JG Modify Date : 2016:03:25 00:38:39-04:00 Subject : - Has XFA : No XMP Toolkit : Adobe XMP Core 5.2-c001 63.139439, 2010/09/27-13:37:26 Format : application/pdf Creator : STMICROELECTRONICS Description : - Title : STM32L4x6 advanced ARM®-based 32-bit MCUs Creator Tool : C2 v2.1.0.1 build 007 - c2_rendition_config : Techlit_Active Metadata Date : 2016:03:25 00:38:39-04:00 Producer : Acrobat Distiller 9.0.0 (Windows) Document ID : uuid:7b021437-9d59-4eb2-a63e-42eea1656ac5 Instance ID : uuid:f25a7074-1b27-452a-91ee-b476d6d8b720 Page Layout : SinglePage Page Mode : UseNone Page Count : 1680EXIF Metadata provided by EXIF.tools