SWTBUG 6800 ROM MONITOR SWTBUG_Users_Guide Users Guide

User Manual: SWTBUG_Users_Guide

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6800 ROM MONITOR
VERSON 1.0

USERS GUIDE

Southwest Technical Products Corporation
219 W. Rhapsody San Antonio, Texas 78116

Scanned and edited by Michael Holley Sept 17, 2000 holleymj@aol.com

SWTPC SWTBUG® (SWATBUG) MONITOR ROM
One of the features of the SWTPC 6800 Computer System is that the conventional
programmer’s console has been replaced with a monitor ROM. The programmer’s console
consists of all the pretty switches and lights often found on similar microcomputers that are used
to bootstrap the system after power up. The programmer’s console not only raises the cost of the
system, but more often than not is confusing and tedious to use for both be-ginning and
experienced programmers. The monitor ROM on the other hand is a permanently stored program
that gives the computer the intelligence required to communicate with the operator thru an
interfaced terminal system immediately after power up without flipping switches for 10 minutes.
This technique makes the computer do the work of simplifying communication between itself and
the operator.
SWTBUG® is the name of the monitor program used in the SWTPC 6800 Computer
System. It might be thought of as kind of a mini-operating system since it gives the operator
command control over the computer system.
Features of the SWTBUG® ROM include:
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗

Memory Examine and Change
Program loading from cassette or paper tape thru the control interface or thru I/O port # 0.
Program saving to cassette or paper tape
Go to user program
Display contents of registers
Erase SWTPC CT-1 024 terminal system screen
SWTPC MF-68 floppy disk boot
Byte search
Breakpoint debugging
Vectored hardware and software interrupts to user defined addresses

SWTBUG® is a permanently stored program and cannot be erased or lost by either a loss of
power or user program error. It is always resident in the computer while power is ON and need
never be loaded into the machine. Subroutines within the ROM are documented and available to
the user to simplify programming and conserve on the use of user RAM memory. Character input
and output, string output and return to monitor are just a few subroutines available to the user.
SWTBUG® is a 1K byte program and is addressed high in memory, far above the amount of
RAM memory required for most user programs. Since SWTBUG® does require a small amount of
RAM memory for operation, a 128 byte scratchpad RAM has been implemented on the processor
board so that no external user RAM memory is required for monitor operation. There is even
enough extra room in this RAM so that short programs such as memory diagnostics can be
loaded into and run from the scratchpad RAM without requiring any external user RAM memory.
Extra care however must be exercised to avoid overstoring any memory locations required for
proper monitor operation. Complete de-tails on this are given later in this writeup. The
SWTBUG® ROM is located from memory addresses EOOO thru E3FF. The scratchpad RAM is
located from memory addresses A000 thru A07F. Both components are physically located on the
processor board and are functional any time the system is powered up. Whenever computer
control is transferred from SWTBUG® to the user program, there are only four ways to get back
into the SWTBUG® command mode. The first is to put a jump to the CONTRL entry point
address within SWTBUG® as the last step of your program. The second is to incorporate a
command or action within your program which transfers program control to the CONTRL entry
point address within SWTBUG’ The third is to depress the front panel RESET button. The fourth
is turn the computer OFF and then back ON again. The fourth method is rather drastic and wipes
out all RAM memory data, it is only mentioned to let you know that the computer always powers
up with the SWTBUG® monitor in the command mode.

SWTBUG® INSTALLATION
SWTBUG® is a MOS device and MOS integrated circuits are susceptible to damage by
static electricity. Although some degree of protection is provided internally within the integrated
circuits, their cost demands the utmost in care. Before opening and/or installing SWTBUG® you
should ground your body and all metallic tools coming into contact with the leads, thru a 1M ohm
¼ watt resistor. The ground must be an “earth” ground such as a water pipe, and not the circuit
board ground. As for connection to your body, attach a clip lead to your watch or metal ID
bracelet. Make absolutely sure that you have the resistor connected between you and the “earth”
ground, otherwise you will be creating a dangerous shock hazard. Avoid touching the leads of the
integrated circuits any more than necessary when installing it, even if you are grounded. Static
electricity should be an important consideration in cold, dry environments. It is less of a problem
when it is warm and humid.
When using SWTBUG® with an MP-A processor card, one board change is necessary since
SWTBUG® is a full 1 K ROM and MIKBUG® was a 1/2K device, If this ROM is replacing
MlKBUG, remove MIKBUG® from its socket. On the back side of the MP-A board you will notice
that pin 15 of IC-2 (ROM) is grounded. The land coming from pin 15 should be broken and a wire
added as shown below.

SWTBUG® should now be installed in the socket for IC-2. Be sure to orient the ROM
correctly when re-installing. The semicircle notch or dot should match with the MP-A board’s
component layout drawing. When installing SWTBUG® in the MP-A2 processor board no board
modifications are necessary. Follow the instructions supplied with the MP-A2 instruction set.
SWTBUG® OPERATION
The SWTBUG® firmware enables the computer to communicate with a terminal to perform
various programming and debugging functions. SWTBUG® will communicate with a terminal via
either a MP-C control interface or MP-S ACIA serial interface on I/O port 1. An optional MP-C
interface can be installed on I/O port 0 for punch and load functions. Although SWTBUG® is
essentially compatible with MIKBUG, be sure to read the COMPATIBILITY section before running
any programs written for MIKBUG. Below is a detailed description of each SWTBUG® command.
RESET
Upon receiving a RESET command, as during power up, SWTBUG® will initialize the
system to receive commands from a terminal. When the RESET button is pushed, control will
transfer to location E0D0 of SWTBUG®. The RESET button should be used for exiting loops or
malfunctioning programs. After resetting, the computer should respond with a carriage return, line
feed and a $ sign. At this point, SWTBUG® is waiting for commands. If breakpoints are being
used, the RESET function will not disable breakpoints. The BREAKPOINT function should be
referenced for additional information.

MEMORY EXAMINE AND CHANGE M (addr)
The Memory Examine and Change function can be used to enter machine code programs
and to display and/or change the contents of memory. The Memory Examine and Change
function should be used as follows:
1.) Type M. The computer should echo the M and output a space.
2.) Type in the four digit hexadecimal address that you wish to examine and/or change.
The computer should respond with a carriage return, line feed, $, the address and the
data that is stored at this address.
3.) At this point the user has the option of advancing, either forward or backward, to the
next memory location, or changing the data stored at the displayed address and
advancing to the next location or of exiting the M function.
a.) To display the next sequential address and data, a line feed or any character other
than 0123456789ABCDEF:;^=>? or a space or a carriage return may be entered.
Any leading spaces that are entered will be ignored by the memory change
function.
b.) To display the next sequential address going backward from the present location, a
^ should be entered.
c.) To change the data stored at the displayed location, enter the new data, either with
or without a leading space. If a non-hex value, such as a 3Q is entered the data will
remain unchanged and the memory change function will be exited. If the data is
unable to be changed (write protected memory, etc.) a ? will be output and the
memory change function will be exited.
d.) To exit the Memory Examine and Change function, type a carriage return.
Below is an example. The underlined parts are what was entered by the user.
$M 0100
$0100 00
$0101 BD
$0102 5D
$0103 C1
$0104 C9
$0105 15
$0104 23
$0105 15
$M 0105
$0105 15
$M E000
$E000 FE
$

.
.
.
01
23
^
.
3Q

56?

MEMORY LOCATION 0100 OPENED
DISPLAY NEXT LOCATION
DISPLAY NEXT LOCATION – SPACE IGNORED
DISPLAY NEXT LOCATION
CHANGE CONTENTS TO 01
CHANGE CONTENTS TO 23. SPACES IGNORED
READ PREVIOUS LOCATION
DISPLAY NEXT LOCATION
ENTER NON-HEX VALUE
SWTBUG CONTROL RESUMED. OPEN NEW LOCATION
EXIT BY HITTING CARRIAGE RETURN
OPEN ANOTHER LOCATION
ATTEMPTED TO CHANGE A WRITE PROTECTED MEMORY
SWTBUG CONTROL RESUMED

REGISTER DUMP FUNCTION R
The R command will display the current contents of the MPU's pushdown stack. “Current”
means the status of data stored on the stack immediately before SWTBUG® control is resumed.
The following is a typical register dump:
$R
$FF
16
23
17EC
0103
A042
$
CONDITION
CODES

ACC
B

ACC
A

INDEX
REG

PGM.
CTR.

STACK
PTR

The condition codes are as defined below:
BIT NO.
0
1
2
3
4
5

LABEL
C
V
Z
N
I
H

CONDITION CODE
Carry-borrow
Overflow
Zero
Negative
Interrupt mask
Half carry

In the above example the condition code of "3C" can be interpreted as follows:
3C16 =

0
BIT 7

0
BIT 6

1
BIT 5

1
BIT 4

1
BIT 3

1
BIT 2

0
BIT 1

0
BIT 0

Below are two examples of how the R command works. Assume that this small program was
entered to change certain registers.
$M 0100
$0100 CE
8E
LOADS STACK POINTER TO 100
$0101 12
10
$0102 34
00
$0103 86
CE
LOAD INDEX REGISTER WITH 1234
$0104 00
12
$0105 C6
34
$0106 FF
86
LOAD ACCUMULATOR A WITH 00
$0107 FD
00
$0108 08
C6
LOAD ACCUMULATOR B WITH FF
$0109 23
FF
$010A 67
7E
JUMP BACK TO SWTBUG CONTROL
$010B F7
E0
$010C 60
E3
$010D DD
AT THIS POINT THE STATUS WILL NOT BE PUSHED ON THE STACK

$R
$FF DC FC
$G
$R
$FF DC FC
$J 0100
$R
$FF DC FC
$M 010A
$010A 7E
$010B 50
$G
$F9 FF 00
$R
$F9 FF 00
$
$FF DC FC

6EFD 0100 A042

NOTE R DUMP THE SAME AFTER RUNNING

6EFD 0100 A042

THE SAME AFTER A JUMP
AT THIS POINT THE JUMP TO SWTBUG CONTROL
IS REPLACED BY A SWI. NOTE THE VALUE
OF THE REGISTERS AFTER THE NEXT DUMP.

1234 010A 0FF9

DUMP SHOWS PROGRAM CHANGES

6EFD 0100 A042

R DUMP AFTER RESET

In the above program you will notice that the register dump after running the program is the
same as before even though the program contained statements that changed the processor’s
registers. The register dump did not reflect these changes because the new conditions were not
pushed on the computer’s stack. Note, however, the register dump did reflect the change when
the last instruction was a software interrupt -- a SWI instruction will push the processor’s status
on the stack and then display the contents of the registers.
CT-1024 CLEAR SCREEN COMMAND C
The C command outputs a home-up (1016) and an erase to end of frame (1616) control
characters for the clearing of the screen on a SWTPC CT-1024 or equivalent terminal system.
GO TO USER’S PROGRAM FUNCTION G
Upon entering a G command, SWTBUG® will transfer control to the user’s program by
executing a RTI (return from interrupt) instruction. This effectively causes the computer to jump to
the memory address stored in memory locations A048 and A049 in the SWTBUG® RAM. A048
contains the most significant byte and A049 the least significant byte of the memory address. If,
for example, you wish to execute a program starting at 0100, change A048 to a 01 using the M
function and change A049 to 00. Typing a G will then cause the computer to execute the program
whose starting address is 0100, Upon entering a program using the G function, the stack pointer
will be set at A049. The G function is also used to restart a program after a breakpoint has been
moved. In this case A048 and A049 should not be changed. See the Breakpoint section for
further information.
JUMP TO USER’S PROGRAM J(addr)
The J command will cause the computer to execute the program whose starting address is
given in the entered address. The J command does not look at locations A048 and A049. The
stack pointer will be set at A042 upon entering a program with a jump command. Example: J
0100. If a non-hex character is entered, SWTBUG® control will resume.
ASCII TAPE PUNCH COMMAND P
The P command provides a means for storing the contents of specified memory on either
cassette or paper tape. Normal output from the computer during a punch is thru either an MP-C
or MP-S serial interface on I/O port 1, but a MP-C interface on I/O 0 can be selected. (See the
description of the 0 command.) To use the P command, the upper and lower limits of the range to
be punched must first be stored in locations A002-A005 of the SWTBUG@ RAM. If you wanted to
punch from addresses 0123 to 4567 (inclusive) you would use the memory examine and change
functions to set computer memory as follows.
6

A002 !
A003 !
A004 !
A005 !

01
23
45
67

MOST SIGNIFICANT BYTE OF LOWER ADDRESS
LEAST SIGNIFICANT BYTE OF LOWER ADDRESS
MOST SIGNIFICANT BYTE OF UPPER ADDRESS
LEAST SIGNIFICANT BYTE OF LOWER ADDRESS

Typing P would turn the punch on and output the specified memory data. A sample punch
output is as follows:
$M A002
$A002 02
01
MSB OF LOW ADDRESS
$A003 72
00
LSB OF LOW ADDRESS
$A004 EF
01
MSB OF HIGH ADDRESS
$A005 00
20
LSB OF HIGH ADDRESS
$A006 5F
$P
TAPE PUNCH COMMAND
S11301008E1000CE12348600C6FF3FE0E3DD005DB2
S11301108090E05160F73A8201F500FFC79771D1F2
S104012000DA
$
S1

0100

8E1000CE12348600C6FF3FE0E3DD005D

START OF
BLOCK
CHARACTER

BYTE
COUNT
(HEX)

BLOCK
STARTING
ADDRESS

DATA

CHECK
SUM

The S1 at the start of the block is used to tell the load routine that valid punch data follows.
Each punch block must begin with the S1. The 1316 is the number of bytes that follow in the block.
In this case two bytes are required for the starting address of the block (01 and 00), 1016 bytes
are required for the data (8E 10 00 CE 12 34 86 00 C6 FF 3F E0 E3 DD 00 50) and one byte is
required for the checksum (B2). The checksum is generated by adding the complement of the
start of block address and the data, 8 bits at a time. At load-in time another checksum is
generated by the load routine which must match with the one generated at punch time.
As the punch begins a PUNCH ON (1216) control character will be output to the punch
device. If a MP-C control interface is the selected interface unused lines on the PIA will be
strobed to turn on the punch function of a SWTPC AC-30 or equivalent tape interface. (See the
PIA Strobing section for more information.) When the punch is completed a PUNCH OFF (1416)
control character will be output and another PIA line will be strobed. User control is then returned
to SWTBUG. To complete the tape making procedure you will have to enter the end of tape
command described below.
END OF TAPE COMMAND E
The E command will punch the contents of the program counter (A048-A049) and an S9 to
tape. The S9 is decoded by the load routine as an “end of tape” marker. For example, if you wish
to save a program that resides from 000 to 000F and whose starting address is 005 you would
perform the following sequence:
$M A002
$A002 FC 00
$A003 3E 00
$A004 A0 00
$A005 49 0F
$A006 4C

$M A048
$A048 01 00
$A049 03 05
$A04A F4
$P
$S113OOOOOA0501001EF023FF01A01B351B37022443
$E
S105A04800050DS9
$
$
A048 and A049 are automatically transferred to A002-A005 and punched to tape by the E
command. A short delay follows the S9 to allow clean load-ins on cassette tape. Appropriate
punch on/off commands are automatically sent.
TAPE LOADER FUNCTION L
The L function is used to load either a MIKBUG® or SWTBUG® formatted program from
either paper or cassette tape. To use the L function, first set up the tape in the loading device and
type L. As with the punch command, a L function will load from an MP-S or MP-C on I/O port 1 or
if selected a MP-C on I/O port 0. A READER ON (1116) control character is output at the
beginning of the load and terminal echo is disabled. Again the PIA is strobed for use with a tape
interface. When the S9 end of tape marker is read, control will return to SWTBUG®. If a
checksum error is detected, a ? will be printed and control will return to SWTBUG® The load
routine verifies that the data being loaded is actually stored in the correct memory locations. If, for
some reason, a byte is not stored (bad memory, etc.) the computer will respond with a ?. To abort
the load function the RESET switch can be pressed. Before attempting to load a SWTPC binary
formatted tape, be sure to read the COMPATIBILITY section.
OPTIONAL PORT COMMAND 0 (not zero)
The 0 (not zero) command enables the user to load from or punch to a MP-C control
interface plugged on to port 0. To use the 0 command, type 0 followed by the desired option P, E
or L (punch, end of tape or load). The same rules apply for using the P, E and L functions as
described earlier. The 0 command will not support an ACIA type serial interface on port 0.
NOTE: When using a MP-C interface on port 0, a RESET will not, automatically turn off the
reader and punch as is done when installed on port 1. This makes it impossible to create or load
a binary formatted tape from an MP-C interface installed on I/O port 0 using existing binary load
and punch programs.
SOFTWARE BREAKPOINTS B(addr)
The B command enables the user to enter breakpoints (software interrupts) in a program for
debugging purposes. Breakpoints enable a program to be stopped at any point for register
examination, memory changing, etc. To use the breakpoint function, first load in your program
and set up A048 and A049 to the starting address of the program. Type B and then enter the
address where you want to set the first breakpoint. SWTBUG® will store the data that was at this
address and replace it with a 3F (software interrupt). Typing G for Go to User Program will start
program execution. When the program reaches the 3F, execution will stop and the processor’s
registers will be displayed. The B function can be used again to move the breakpoint to a new
location -- SWTBUG® automatically replaces the data at the old breakpoint location with the
original instruction. A G should be used to re-start the program -- do not reset A048 and A049 -SWTBUG® automatically pulls the restart location from the stack. To remove breakpoints, type B
followed by a carriage return. Breakpoints should always be removed in this way after using the
breakpoint function. If, while using breakpoints, the system is reset, the correct location on the
stack will be lost. After resetting, the program counter addresses (A048, A049) should be
reinitialized to the beginning of the program and execution restarted.

A previously set breakpoint will remain and may be changed or removed as described
earlier. If, when using the B command, a non-hex value is entered the previous breakpoint will be
removed and SWTBUG® control will resume.
There are several things that one must be aware of when using breakpoints to insure proper
operation.
1.) The breakpoint function uses the same locations as do vectored software interrupts;
therefore, vectored software interrupts should not be used with break points.
2.) The SWI jump location, A012, will be set to El24 when breakpoints are not in use, as
after power up, and will be set to El23 when breakpoints are in use. This location serves
as a pointer to tell the computer what to do when a 3F is seen. The RESET button will
not reset this location to the non-breakpoint state. The breakpoint-activated state can
only be exited by typing B followed by a carriage return. If you are using breakpoints in
a program that “bombs out” and you hit the RESET switch, you must clear the present
breakpoint before going on to another program. If this is not done before a new program
is loaded in, the first time the B command is used one byte of the new program will be
replaced by the stored byte from the last program.
3.) Do not set a breakpoint to an address where a breakpoint is already set. Doing so will
cause the computer to lose the original program data.
DO NOT
B 1377
G
B 1377

THIS IS OK
B 1377
B 0100
B1377
B carriage return

4.) The breakpoint routine uses SWTBUG® RAM locations A014-A016; therefore,
programs which use these three bytes should not be used in conjunction with
breakpoints.
DISK BOOT D
SWTBUG® contains the boot necessary to initialize a SWTPC MF-68 disk system. Typing D
will transfer control to the disk operating system, (if attached). If D is accidentally typed with no
disk attached, the RESET button must be pressed. Since the disk boot contains no error
detection, it may need to be typed more than once to do a boot.
JUMP TO PROM PROGRAM Z
Typing Z will transfer control to a program stored in PROM (if applicable) whose starting
address is at C000. Typing Z is equivalent of typing J C000
BYTE SEARCH F (high address) (low address) (byte)
The F (find] command will search memory from the specified low address to tile high
address, inclusive, and will display all memory locations containing the byte specified. For
example, to find all memory locations between 0100 and 0200 that contain 8E, the following
command should be used: F 020001008E. Note that no spaces may be used between addresses
and that the high address goes first.
$F 020001008E
If a non hex value is entered, SWTBUG® control will resume.

VECTORED SOFTWARE INTERRUPTS
Normally when encountering a SWI (3F) instruction, the computer will display the
processor’s registers and SWTBUG® control will be resumed. If desired, the 3F command can be
vectored to anywhere in memory, just like the NMI and IRQ interrupts. To use the vectoring
capability simply store the service routine address at location A012-A013 in the SWTBUG® RAM.
When a 3F is encountered, processor control will be transferred to the memory address stored in
A012-A013. Note: each time the system is RESET, A012 will be reset to the location of the
register dump routine. This means that any program which uses vectored SWl’s should set up
this location each time it is executed. If the location you wish to vector to is 10D0, for example,
the following statements at the beginning of the program will set up the vector correctly:
LDX # $10D0
LOAD VECTOR ADDRESS
STX $A012
STORE VECTOR
Vectored software interrupts should not be used in conjunction with breakpoints since the
breakpoint routine uses locations A012-A013.
VECTORED INPUT/OUTPUT
If desired, input and output can be vectored to a MP-S or MP-C interface on ports other than
#1. Locations A00A-A00B contains the port address that the subroutines INEEE and OUTEEE
use for inputting and outputting characters. To use vectored input/output your program must store
the desired I/O address in A00A–A00B before any I/O is done. Below is a list of I/O address
assignments for each port:
PORT
ADDRESS
0
8000
1
8004
2
8008
3
800C
4
8010
5
8014
6
8018
7
801C
The program statements that would set up the correct port would be as follows:
LDX #$8018
I/O on port 6
STX $A00A
Store
SWTBUG® will look at the port and will self-configure for either a MP-C or MP-S type
interface.
NOTE: Any time that SWTBUG‘s control sequence is initiated or when the RESET button is
pushed, the I/O address will be reset to port # 1. Therefore complete SWTBUG® monitor control
cannot be moved to another port.
USING NON-MASKABLE INTERRUPTS
Using non-maskable interrupts is very similar to using vectored software interrupts. A nonmaskable interrupt will occur whenever the NMI line on the computer’s bus is grounded either
through hardware or by an ACIA or PIA. When the NMI is seen, processor control will be
transferred to the location stored in A006 and A007. For example if an NMI service routine is
desired at location 1000 the following statements should be used at the beginning of your
program to set up the correct NM1 jump address.
LDX #$1000
STX $A006
USING MASKABLE (IRQ) INTERRUPTS
Using regular maskable interrupts is the same as using non-maskable interrupts except that
when the IRQ line is grounded processor control will jump to the address stored in A000 and
A001. The computer will only respond to the interrupt if the processor’s interrupt mask bit 1 is 0. A
CLI instruction at the beginning of your program will insure this condition.
10

PIA STROBING
Use of the Control Interface for Read/Punch-On/Off Decoding
SWTBUG® software contains subroutines to send out pulses to unused pins of the PIA
integrated circuit on the MP-C serial control interface that can be used for automatic reader /
punch controls. These pulses can be used if you are using a SWTPC AC-30 cassette interface
and a terminal in which access to the control command decoding is denied.
If you intend to use the read/punch control logic output on the MP-C control interface board,
make the following connections from the indicated pins of ICI on the MP-C control interface board
to the specified pins of a twelve pin male connector shell. The connector pinning shown below is
correct for a SWTPC AC-30 cassette interface and will need modifications for other units. Be sure
to make the wires long enough to reach your AC-30 where the connector will be plugged. If you
have access to your terminal’s 16X baud rate clock, the terminal’s clock bus should be broken
and the 16X clock IN and OUT lines brought out to the same connector.
MP-C IC1 pin 7 (read on)
12 pin male shell female pin 1
MP-C IC1 pin 4 (punch on)
12 pin male shell female pin 2
MP-C IC1 pin 6 (read off)
12 pin male shell female pin 3
MP-C IC1 pin 5 (punch off)
12 pin male shell female pin 4
Terminal’s 16X clock OUT
12 pin male shell female pin 5
Terminal’s 16X clock IN
12 pin male shell female pin 6
MP-C ground
12 pin male shell female pin 12
These signals are low going pulses and are about 15 microseconds wide. They are not
buffered and should drive a maximum of only one standard TTL load.
PIA stroking will work only on SWTBUG®‘s L, P and E functions. Strobing is not supported
in BASIC and some other SWTPC software.

OPERATING THE MP-A2 PROCESSOR BOARD
AT BAUD RATES HIGHER THAN 1200 BAUD
The MP-S Serial Interfaces available for the SWTPC 6800 Computer System are capable of
operating at baud rates up to 9600 baud. Although baud rate clocks for 110, 150, 300, 600 and
1200 baud are generated, buffered and fed onto the mother board by IC4 of the MP-A2 board,
clocks for additional baud rates are also available from IC4 as well. The table below gives the
baud rate and respective output pin number of IC4.
BAUD RATE
MP-A2 IC4 pin
75
9
200
6
1800
15
2400
3
3600
16
4800
2
7200
17
9600
1
To use the selected clock, run an insulated jumper between the specified pin and pin 13 of
IC10 on the MP-A2 board. Run another insulated jumper between pin 12 of IC10 and either the
UD1 or UD2 bus connections points at the connector edge of the MP-A2 circuit board. IC10 is a
low power TTL buffer which must be inserted between the baud rate clock generator and the
mother board bus. Since user defined lines UD1 and UD2 are carried on just the 50-pin main
board bus and lines UD3 and UD4 are carried on just the 30-pin interface board, it will be
necessary to jumper two of the buses together to provide the selected baud rate clock on the
interface card bus. Each serial interface card to be operated with the selected baud rate clock will
have to be jumpered so its clock is acquired from the selected user defined line rather than one of
the five original baud rate clocks already present.

OPERATING THE MP-A PROCESSOR BOARD
AT BAUD RATES HIGHER THAN 1200 BAUD
When using the MP-S serial interface with an MP-A processor board, baud rate clocks for up
to 9600 baud are available from the baud rate generator on the MP-A processor board. The table
below shows the baud rates available and from which pin of IC4 on the MP-A board they are
derived. These 16X baud rate clocks are best feed back to the interface boards via the user
defined lines provided on the mother board. These baud rates of course are in addition to the
110, 150, 300, 600 and 1200 baud rate clocks already provided on the mother board.
BAUD RATE
75
200
1800
2400
3600
4800
7200
9600

MP-A IC4 pin
9
6
15
3
16
2
17
1

COMPATIBILITY
Although SWTBUG® has been written to be as compatible as possible with MIKBUG® and
with software supplied by SWTPC, it can never be completely MIKBUG® compatible. All major
subroutines of SWTBUG® are address and function compatible with MIKBUG®, but if you have a
program that enters into the middle of a MIKBUG® routine for some reason, program
modifications will be necessary. The following is a list of the MIKBUG® compatible subroutines
and strings along with their entry point addresses.
E040
LOAD19
E0C8
OUT4HS
E047
BADDR
E0CA
OUT2HS
E055
BYTE
E0D0
START
E075
OUTCH
E0E3
CONTRL
E078
INCH
E19C
MCLOFF
E07B
PDATA2
E19D
MCL
E07E
PDATA1
E1AC
INEEE
E0BF
OUT2H
E1D1
OUTEEE
If any doubt exists as to the compatibility of a particular program, it should be disassembled
and any references to memory locations E000–E1FF be verified. Since SWTBUG® is more
complex than MIKBUG, more RAM area must be used in the 6810 SWTBUG® RAM. If vectored
software interrupts and breakpoints are not being used, the area from A014 to A033 and from
A04A to A07F can be used for small, temporary programs such as memory diagnostics. Note that
some programs written for MIKBUG® use locations A034-A036 - these locations are not available
for use in SWTBUG®
LOADING BINARY TAPES THRU SWTBUG®
SWTBUG® was written to accept the binary formatted tapes supplied by SWTPC. These
tapes include 4K BASIC, 8K BASIC, CORES and DESEMBLER. When loading these tapes the
following rules must be followed:
1.) The tape reading device (AC-30, etc.) must be locked in the read on mode during the
binary load.
2.) Binary tapes must be loaded in thru port # 1, the control port. The optional load from
port 0 command is not supported in binary. You may load in ASCII however.
3.) When using a PIA type interface to load binary tapes, the unused lines used for
reader/punch on/off strobing are not activated.

NOTE: This does not mean that SWTBUG® is equipped with a binary loader-only certain
SWTPC binary tapes that contain a special binary loader (in ASCII) will work correctly.
To load the tape simply follow the instructions given for loading an ASCII tape, but keep the
reader locked on.
SPECIAL NOTES ON USING AN ACIA AND PROGRAM MODIFICATIONS
Many available 6800 programs written for MIKBUG® assume that a PIA type MP-C control
interface is being used and may address this port directly. When using an ACIA type interface,
these references need to be changed. For example, some programs, such as BASIC and
CORES, poll the PIA periodically to see if a character has been typed in. This is done in order to
kick out of a loop or a print sequence. (BASIC uses CTL..C. and CO-RES uses CTL..X.) The
source statements that do this usually take the following form:
B6 8004
2B 03
7E XX XX

LDA A PIAD
LOAD A FROM DATA REG.
BMI PRINT
BRANCH IF NOT CHAR. SEEN
JMP READY or RESTART
PRINT REMAINDER OF SEQUENCE

To change to a MP-S serial interface, this code can sometimes be replaced as follows;
LDA A PIAD !
ASR A
SEE IF CHAR. LOADED
BMI PRINT !
BCS PRINT
BRANCH IF CHAR. INPUT
JMP READY
PRINT REMAINDER OF SEQUENCE
Before modifying any programs on your own, you should have a working knowledge of
SWTBUG'S ACIA input routine, ACIA operation, and your particular program. The following is a
list of patches to some SWTPC supplied programs.
BLKJAK - SWTPC 6800 Black Jack Program
LOCATION
0270
0647
064A
064D
064F
0652
0654
0657
065A
065B
065D

DATA
7E 064A
7E 026D
B6 E008
27 08
B6 8004
2B F3
7E 0275
B6 8004
47
24EA
20 F5

With the above modifications BLKJAK will be compatible with either an ACIA or PIA type
interface.
CO-RES Ver. 1.0 and 1.01 ACIA Modifications
LOCATION
1682
1683
1685

DATA
47
24 02
20 A0

BASIC 8K and 4K up to an including Ver. 2.0 cannot be modified for ACIA operation. Later
versions should be purchased.

GENERAL RULES FOR PROGRAM WRITING
Although for a user program to be functional it need only work with the exact system it was
written for, following a few simple rules reduces program modifications for 6800 systems using
other monitors. Following these rules will make your programs more professional and versatile.
Some general guidelines are as follows:
1.) Minimize the number of references made to the ROM.
2.) Do not use strange, in-between SWTBUG® addresses. Generally only the routines
BADDR, BYTE, PDATA1, INHEX, OUT4HS, OUT2HS, CONTRL, INEEE and OUTEEE
should be used.
3.) For large programs, vector I/O through a jump instruction for ease of change to match
other I/O packages. Example:
DON’T
JSR INEEE

DO
JSR INPUT

JSR INEEE

JSR INPUT

! INPUT: JMP INEEE

JSR INEEE

JSR INPUT

4.) Try not to use the SWTBUG® RAM any more than necessary. With the exception of
using it as stack storage and memory diagnostics, there is no real reason to use the
SWTBUG® RAM area.
5.) Define the stack area at the beginning of the program. Example: Start LDS #$ A042.
Relocating the stack location to A042 at the beginning of each of your programs will
prevent you from having to reload the program counter addresses A048 and A049 each
time you RESET and restart your program.
6.) Most programs should have a provision for exiting them without hitting the RESET
button. A jump to CONTRL (7E E0E3) instruction in your program will cause
SWTBUG® control to resume when executed.
MEMORY DIAGNOSTICS
The earlier memory diagnostics ROBIT, MEMCON and CDAT supplied by SWTPC were
compatible only with MIKBUG®. The new versions ROBIT 2, MEMCON 3 and CDAT 2 are
compatible with both MIKBUG® and SWTBUG®.
PROGRAM DESCRIPTION
Although the source listing of SWTBUG® is well commented, the following subroutine by
subroutine description should be of use to those who wish to gain the maximum advantage of its
routines.
TEMPORARY STORAGE LOCATIONS
IRQ (A000)

This location is used by the standard IRQ interrupt request feature. When an
interrupt is generated, processor control will jump to the location stored in
IRQ.

BEGA (A002)

This location is where the beginning address is stored for the punch and end
of tape routines.

ENDA (A004)

This location is where the ending address is stored for the punch and end of
tape routines. It is also used by the byte search routine.

NMI (A006)

NMI is used by the non-maskable interrupt (NMI) function. When an NMI is
generated, processor control will jump to the location stored in NMI.

SP (A008)

Temporary storage location for the stack pointer. SP is used in the register
dump subroutines and by the breakpoint function.

PORADD (A00A)

This location contains the port address used for SWTBUG’s I/O routines.

PORECH (A00C)

This byte tells SWTBUG® ‘s input routines whether or not to echo.

XHI (A00D)

Temporary index register storage used by numerous routines.

XLOW (A00E)

Temporary index register storage used by numerous routines.

XTEMP (A010)

Temporary index register storage for input and output routines.

SWIJMP (A012)

When a SWI instruction is encountered, processor control will transfer to the
location stored in SWIJMP.

BKPT (AQ14)

Temporary breakpoint address storage.

BKLST (A016)

Temporary data storage for the breakpoint routine.

TW (A044)

Temporary storage location for load/punch.

TEMP (A046)

Temporary storage location for punch and load.

BYTECT (A047)

Temporary storage location for load/punch.
SWTBUG@SUBROUTINE AND TEXT STRING DESCRIPTION

IRQV (E000)

This is the entry point for regular IRQ interrupts. Processor control is given of
the service routine whose address is stored in IRQ.

JUMP (E005)

This is the service routine for the J command. BADDR is used to input the
address and a jump then occurs to the correct address.

CURSOR (E009)

Home-up and erase to end of frame characters for CT 1024.

LOAD (E00C)

Load is the ASCII loading routine. Load uses a number of other SWTBUG®
subroutines.

BADDR (E047)

BADDR is a subroutine to input a 4-digit hexadecimal number, such as 137D,
from the control terminal. BADDR uses the subroutines BYTE, INCH and
INHEX and uses temporary storage locations XHI, XLOW, CKSM, both
accumulators and the index register. When BADDR is called it will look for
four hex numbers to be entered from the terminal. If a non-hex value, such
as H, is entered, SWTBUG® control will resume. If all characters entered are
valid hex, the results will be stored in XHI, XLOW and the index register.
Accumulator A will contain of XLOW. If 137D is entered the results will be as
followsACC A
7D
ACC B
CKSM
IXR
137D
XHI
13
XLOW
7D

CKSM and ACC B are used internally to generate a check sum for the
PUNCH routine.

BYTE (E055)

BYTE is similar to BADDR, but inputs only two hex characters from the
terminal to generate one 8-bit byte equivalent. BYTE uses the subroutines
15

INHEX and INCH, temporary storage locations CKSM and both
accumulators. If a non-hex value is entered, SWTBUG® control will resume.
When BYTE is called as a subroutine, the computer will wait for two hex
characters to be entered thru the control port. If a 3C is entered, the results
will be as follows:
ACC A
3C
ACC B
CKSM
IXR
UNCHANGED
CKSM
Prior CKSM + check sum generated inside
BYTE
OUTHL (E067)
OUTHR (E06B)

These subroutines are used by OUT2HS and OUT4HS to output
hexadecimal numbers

This is the character output routine used by PDATA1, OUT4HS, OUT2HS
and most programs written for SWTBUG/MIKBUG® to output one character
from the computer to the control port (I/O # 1). OUTEEE, OUTCH and
OUTEE1 are all functional equivalents- OUTEE1 is the main output routine
with OUT-CH and OUTEEE being jumps to OUTEE1. When using this
routine, OUTEEE (E1D1) should be used to maintain compatibility with
MIKBUG® systems.
To use OUTEEE the character to be output should be placed in the A
accumulator in its ASCII form. To output the letter A on the control terminal,
the following program could be used.
LDA A
#$41
JSR
OUTEEE
The processor’s registers are affected as follows.
ACC A
changed internally
ACC B
not affected
IXR
not affected
OUTEEE is an 8-bit output routine and does not generate a parity bit.
OUTEEE
OUTCH
OUTEE
(E1D1)

INEEE,
INCH,
INEEE1
(E1AC)

The locations are all functionally equivalent to SWTBUG® ‘s character input
routine. This routine will look for one character from the control terminal (I/O
# 1) and store it in the A accumulator. Once called, INEEE will loop within itself until a character has been input. Anytime input is desire, the call JSR
INEEE should be used.
INEEE automatically sets the 8th bit to 0 and does not check for parity.
When using INEEE the processor’s registers are affected as follows:
ACC A
loaded with the character input from the terminal
ACC B
not affected
IXR
not affected

INCH8 (E1F6)

INCH8 is functionally the same as INEEE except that the 8th bit is not set to
8. This subroutine should be used whenever full 8-bit input is desired, such
as in binary loader programs.

INHEX (E0AA)

INHEX is the subroutine used by BYTE and BADDR that will input one
hexadecimal character from the control terminal. If a non-hex character is
entered, SWTBUG® control will resume. If a hex character, such as an E is
entered, the results will be as follows:
ACC A
0E
ACC B
not affected
IXR
not affected

PDATA1 (E07E)

PDATA1 is the subroutine used to output a string of text on the control
terminal. PDATA1 will start outputting data that is pointed to by the index
register and will continue until a 04 is seen. For example, if you wanted to
print HELLO on the terminal the following could be used.
16

START

TEXT

ORG $100
LDX #TEXT
JSR PDATA1
JMP CONTRL
FCB $0D, $0A
FCC /HELLO/
FCB 4
END

The accumulator and register status after using PDATA1 is as follows:
ACC A
Changed during the operation
ACC B
UNCHANGED
IXR
Contains the memory location of the 04

CHANGE (E088)

CHANGE is SWTBUG‘s memory examine and change function. Change
uses a number of other SWTBUG® subroutines.

OUT4HS (E0C8)

OUT4HS is used to output a four-digit (16-bit) hexadecimal number onto the
control terminal. The address of the most significant byte to be output should
be loaded into the index register before calling OUT4HS. For example, to
out-put the 16-bit hex number stored in memory locations 1000 and 1001
whose most significant byte is in 1000 while the least significant byte is in
1001 the following sequence should be used:
LDX # $1000
JSR OUT4HS

If location 1000 contained a hex 3C and 1001 contained a hex 0B, an ASCII,
3C0B would be displayed on the screen when OUT4HS is called. Remember
memory data is handled in hex but must be output as ASCII characters which
have a different hex value than those stored in the computer’s memory. The
registers are affected as follows:
ACC A
Changed during the operation
ACC B
UNCHANGED
IXR
Incremented by two. (1002 in this example)

OUT2HS (E0CA)

OUT2HS is similar to OUT4HS, but outputs only two hex characters (one
byte). For example, to display the byte stored at 2008 the following sequence
would be used:
LDX # $2000
JSR OUT2HS

An ASCII 6C would be output to the control terminal if location 2001
contained a hex 6C. The registers are affected as follows:
ACC A
Changed during the operation
ACC B
UNCHANGED
IXR
Incremented by one. (1001in this example)

OUTS (E0CC) OUTS is a subroutine that outputs one space to the control terminal.
START (E0D0)

START is the beginning of a sequence of steps that initialize the system
during power up or reset. First, the stack pointer is set to be A042 and is
stored in SP. Next, an FF is stored in location A943. This sets the interrupt
mask bit in the stack so that when a G command is given the processor will
not respond to interrupts until told to do so. The type of port being used
(ACIA or PIA) is then determined by initializing it as a PIA and looking to see
if this worked. If not, an ACIA is assumed and the proper ACIA initialization
routine, AL2, is selected. The program then goes to CONTRL sequence.
17

CONTRL (E0E3)

This MIKBUG® equivalent sequence again resets the stack to A042.
PORECH is cleared to enable echo and the subroutine SAVGET is selected
to get the correct port number and type. Next, the routines PNCHOF and
RDOFF generate punch and reader off commands. A carriage return, line
feed, erase to end of line (1516) and a $ is then output to the control terminal.
At this point SWTBUG® is ready for command input.

SFEl (E124)

SFEl is the entry point for non user-vectored software interrupt instructions. If
vectored software interrupts are selected, a jump is executed to the proper
location. If breakpoints are in use the stack pointer is not changed, the
processor’s registers are displayed and SWTBUG® is instructed to look for
the next command. If neither breakpoints or vectored software interrupts are
selected a register dump occurs and the CONTRL sequence is initiated.

PRINT (E130)

PRINT is the routine that actually does the dumping of the processor’s
registers.

LOOK (E173)

LOOK is the routine that inputs a character from the terminal and jumps to
the appropriate location in SWTBUG® if it is a valid command.

SFE (E18B)

Entry point for software interrupt instructions.

S9 (E190)

S and 9 string for the end of tape routine.

MTAPE1 (E193)

This is the character string containing a carriage return, line feed, erase to
end of line, four nulls, a S1 for tape control and 04 for PDATA1 control.

MCL (E19D)

This string contains a carriage return, line feed, three nulls, a $ and a 04 for
PDATA1 control.

ElA5 (E1A5)

ElA5 is a special entry location which is used by the binary load routine on
some SWTPC binary tapes.

NMIV (E1A7)

This routine fetches the correct jump location for a NMI.

SEARCH (E1AE)

Byte searching routine.

GOT0 (E1D0)

GOT0 contains the RTI instruction that is used by the G command to execute
a user program.

SAVGET (E1D3)

This routine saves the index register in XTEMP and tests for the appropriate
interface location and type. The index register is then loaded with the
address of this interface.

ISACIA (E1D9)

ISACIA is the routine that sees if an ACIA or PIA is present.

BILD (E1F3)

BILD is a special sequence of increment stack pointer instructions used only
by the binary loader on some SWTPC binary tapes.

ACIAIN (E1FF)

This is the ACIA input routine. PORECH is polled for the desired echo/don’t
condition. The character in the A accumulator is then output, the index
register and B accumulator restored and an RTS instruction executed by the
RES routine.

ACIOUT (E212)

This is the ACIA output routine which outputs the character in the A
accumuator, and recovers the B accumulator and index register.

IN1 (E223)

IN1 is the PIA input routine which inputs a character from the control terminal
and stores it in the A accumulator. The correct echo/non echo condition is
selected and the B accumulator and index register are restored.
18

IOUT (E240)

IOUT is the PIA output routine which outputs the character in the A
accumulator.

OPTL (E269)

OPTL is the service routine that sets up PORECH for I/O on port 0. The
appropriate command P, E or L is then selected.

PIAECH (E27D)

This routine disables the echo on a PIA type interface.

PIAINI (E284)

This routine is used to initialize PIA type interfaces.

DELAY (E202)

DELAY is a general purpose delay loop. If desired, the index register can be
pre-loaded with a number other than FFFF for shorter delays. The entry point
in this case is DELAY1 (E2C5).

CLEAR (E2CC)

This routine generates a home up, erase to end of frame command for
SWTPC CT 1024 and similar terminal systems.

BREAK (E2D9)

BREAK is the routine that is used to enter software breakpoints. First, the address is input by BADDR. If breakpoints were previously in use the data is
replaced at the previous breakpoint address and the new breakpoint is
inserted.

PNCHS9 (E31E

This routine selects A048 and A049 as the beginning and ending address for
the punch routine and punches their contents. A S9 is then punched to tape
followed by a short delay.

RDON (E334)
RDOFF (E347)
PNCHON (E34D)
PNCHOF(E353)

These subroutines are used to turn a reader/punch on and off. At the
beginning of each routine the A accumulator is loaded with the ASCII value
of the particular function that is normally decoded by a Teletype or other
terminal system. The B accumulator is then loaded with a special bit pattern
that will cause a predetermined line to be toggled on PIA type interfaces.
ACC A is then out-put using OUTEEE and if a PIA type interface is being
used the proper PIA line is strobed by the STROBE routine. The proper line
is determined by the con-tents of ACC B. The subroutine RDON also clears
the location PORECH and re-configures PIA type interfaces to be sure that
the echo function of the character input routine is disabled. Both
accumulators and the index register are used and are not retained.
ACC A
ACC B
FUNCTION
11
20
Reader ON
13
10
Reader OFF
12
04
Punch ON
14
08
Punch OFF

STROBE (E357)

This is the routine that actually generates the pulses on the unused lines of a
PIA type interface for reader/punch control.

PUNCH (E376)

PUNCH is the ASCII punching routine of SWTBUG, PUNCH consists of
several parts and uses various SWTBUG’s subroutines.

TABLE (E3D1)

This is the command table used by the lookup routine. The table is arranged
in three byte blocks. The first byte is the ASCII value of the command. The
next two bytes are the address of the routine that will service the command.

SVVTBUG is a registered trademark of Southwest Technical Products Carp
MlKBUG is a registered trademark of Motorola Inc.
Teletype is a registered trademark of Teletype Corp.
19

NAM
SWTBUG
VERSION 1.00

OPT
PAG
****************************************************
*REPLACEMENT FOR MIKBUG ROM
*FOR SWTPC 6800 COMPUTER SYSTEM
*COPYRIGHT 1977
*SOUTHWEST TECHNICAL PROD. CORP.
*AUGUST, 1977
****************************************************

A000
A000
A002
A004
A006
A008
A009
A00A
A00C
A00D
A00E
A00F
A010
A012
A044
A046
A047
8004
C000
A014
A016
A042
A042

PORADD
PORECH
XHI
XLOW
CKSM
XTEMP
SWIJMP
TW
TEMP
BYTECT
CTLPOR
PROM
BKPT
BKLST

ORG
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
EQU
EQU
EQU
EQU
EQU
RMB
RMB

$A000
2
2
2
2
1
1
2
1
1
1
1
2
2
$A044
$A046
$A047
$8004
$C000
2
1

IRQ POINTER
BEGINNING ADDR PNCH
ENDING ADDR PNCH
NMI INTERRUPT VECTOR
S HIGH
S LOW
PORT ADDRESS
ECHO ON/OFF FLAG
XREG HIGH
XREG LOW
CHECKSUM
X-REG TEMP STGE
SWI JUMP VECTOR
TEMPORARY STORAGE
TEMPORARY STORAGE
BYTECT AND MCONT TEMP.
CONTROL PORT ADDRESS
JUMP TO PROM ADDRESS
BREAKPOINT ADDRESS
BREAKPOINT DATA

STACK

ORG
RMB

$A042
1

SWTBUG STACK

ORG

$E000

IRQ
BEGA
ENDA
NMI
SP

E000

E000 FE A0 00
E003 6E 00

*I/O INTERRUPT SEQUENCE
IRQV
LDX
IRQ
JMP
0,X

E005 8D 40
E007 6E 00

*JUMP TO USER PROGRAM
JUMP
BSR
BADDR
JMP
0,X

E009 10
E00A 16 04

E00C BD E3 34
E00F 8D 67
E011 81 53

CURSOR

FCB

$10,$16,4 CT-1024 CURSOR CONTROL

*ASCII LOADING ROUTINE
LOAD
JSR
RDON
LOAD3
BSR
INCH
CMP A #'S

READER ON, DIS ECHO, GET P#

SWTBUG
E013
E015
E017
E019
E01B
E01D
E01F
E022
E024
E026

26
8D
81
27
81
26
7F
8D
80
B7

TSC ASSEMBLER
FA
61
39
29
31
F0
A0 0F
31
02
A0 47
*BUILD

E029 8D 1C
E02B
E02D
E030
E032
E034
E036
E038
E039
E03B
E03E
E040
E042
E044

8D
7A
27
A7
A1
26
08
20
7C
27
86
8D
7E

28
A0 47
09
00
00
08

E047
E049
E04C
E04E
E051
E054

8D
B7
8D
B7
FE
39

0C
A0 0D
07
A0 0E
A0 0D

E055
E057
E058
E059
E05A
E05B
E05C
E05E
E05F
E060
E063
E066

8D
48
48
48
48
16
8D
1B
16
FB
F7
39

E067
E068
E069
E06A
E06B

44
44
44
44
84 0F

F0
A0 0F
CF
3F
31
E2 D4

A0 0F
A0 0F

*STORE
LOAD11

LOAD15
LOAD19
LOAD21

BNE
BSR
CMP A
BEQ
CMP A
BNE
CLR
BSR
SUB A
STA A
ADDRESS
BSR
DATA
BSR
DEC
BEQ
STA A
CMP A
BNE
INX
BRA
INC
BEQ
LDA A
BSR
JMP

LOAD3
INCH
#'9
LOAD21
#'1
LOAD3
CKSM
BYTE
#2
BYTECT

PAGE

1ST CHAR NOT S
READ CHAR

2ND CHAR NOT 1
ZERO CHECKSUM
READ BYTE
BYTE COUNT

BADDR
BYTE
BYTECT
LOAD15
0,X
0,X
LOAD19

ZERO BYTE COUNT
STORE DATA
DATA STORED?

LOAD11
CKSM
LOAD3
#'?
OUTCH
RDOFF1

*BUILD ADDRESS
BADDR
BSR
BYTE
STA A XHI
BSR
BYTE
STA A XLOW
LDX
XHI
RTS

READ 2 FRAMES

LOAD IXR WITH NUMBER

*INPUT BYTE (TWO FRAMES)
BYTE
BSR
INHEX
GET HEX CHAR
BYTE1
ASL A
ASL A
ASL A
ASL A
TAB
BSR
INHEX
ABA
TAB
ADD B CKSM
STA B CKSM
RTS
OUTHL

OUTHR

LSR
LSR
LSR
LSR
AND

A
A
A
A
A

OUT HEX LEFT BCD DIGIT

#$F

OUT HEX RIGHT BCD DIGIT

SWTBUG
E06D
E06F
E071
E073

8B
81
23
8B

TSC ASSEMBLER
30
39
02
07

ADD A
CMP A
BLS
ADD A

#$30
#$39
OUTCH
#$7

E075 7E E1 D1
E078 7E E1 AC

*OUTPUT ONE CHAR
OUTCH
JMP
OUTEEE
INCH
JMP
INEEE

E07B
E07D
E07E
E080
E082
E084

*PRINT DATA POINTED TO BY X REG
PDATA2 BSR
OUTCH
INX
PDATA1 LDA A 0,X
CMP A #4
BNE
PDATA2
RTS
STOP ON HEX 04

8D
08
A6
81
26
39

F8
00
04
F7

E085 7E E1 4A

E088
E08A
E08D
E08F
E092
E094
E097
E099
E09B
E09D
E09F
E0A1
E0A3
E0A5
E0A7
E0A9

8D
CE
8D
CE
8D
FE
8D
8D
8D
81
27
81
27
81
20
01

BD
E1 9D
EF
A0 0D
34
A0 0D
31
31
DB
20
FA
0D
E0
5E
2C

*MEMORY EXAMINE AND CHANGE
CHANGE BSR
BADDR
CHA51
LDX
#MCL
BSR
PDATA1
C/R L/F
LDX
#XHI
BSR
OUT4HS
PRINT ADDRESS
LDX
XHI
BSR
OUT2HS
PRINT OLD DATA
BSR
OUTS
OUTPUT SPACE
ANOTH
BSR
INCH
INPUT CHAR
CMP A #$20
BEQ
ANOTH
CMP A #$D
BEQ
C1
CMP A #'^
UP ARROW?
BRA
AL3
BRANCH FOR ADJUSTMENT
NOP

E0AA
E0AC
E0AE
E0B0
E0B2
E0B4
E0B6
E0B8
E0BA
E0BC
E0BE

8D
80
2B
81
2F
81
2B
81
2E
80
39

CC
30
4C
09
0A
11
44
16
40
07

*INPUT HEX CHARACTER
INHEX
BSR
INCH
INHEX1 SUB A #$30
BMI
C3
CMP A #$9
BLE
IN1HG
CMP A #$11
BMI
C3
CMP A #$16
BGT
C3
SUB A #7
IN1HG
RTS

E0BF
E0C1
E0C3
E0C5

A6 00
8D A4
A6 00
08

OUT2H
OUT2HA

JMP

PAGE

LDA A
BSR
LDA A
INX

SWTCTL

0,X
OUTHL
0,X

NOT HEX
NOT HEX

OUTPUT 2 HEX CHAR
OUT LEFT HEX CHAR

SWTBUG

TSC ASSEMBLER

E0C6 20 A3

PAGE

BRA

OUTHR

OUTPUT RIGHT HEX CHAR

E0C8 8D F5
E0CA 8D F3

OUT4HS
OUT2HS

BSR
BSR

OUT2H
OUT2H

OUTPUT 4 HEX CHAR + SPACE
OUTPUT 2 HEX CHAR + SPACE

E0CC 86 20
E0CE 20 A5

OUTS

LDA A
BRA

#$20
OUTCH

SPACE
(BSR & TRS)

E0D0 8E A0 42
E0D3 20 2C

*ENTER POWER ON SEQUENCE
START
LDS
#STACK
BRA
AL1
BRANCH FOR ADDRESS COMPATIBIL

E0D5
E0D7
E0D8
E0D9
E0DC
E0DE
E0E1

********************************************
*PART OF MEMORY EXAMINE AND CHANGE
AL3
BNE
SK1
DEX
DEX
STX
XHI
BRA
CHA51
SK1
STX
XHI
BRA
AL4

26
09
09
FF
20
FF
20

A0 0D
AC
A0 0D
02

E0E3 20 6D

EOE3

E0E5
E0E7
E0E9
E0EB
E0ED
E0EF
E0F2
E0F3
E0F5
E0F7
E0F9
E0FC
E0FF

AL4

81
25
81
22
8D
BD
09
A7
A1
27
7E
BE
20

30
A1
46
9D
BD
E0 57
00
00
91
E0 40
A0 08
49

E101 BF A0 08
E104 86 FF
E106 BD E3 08
E109
E10C
E10F
E111
E113

CE
BD
A6
A1
20

80 04
E2 84
00
02
02

CONTRL

BRANCH FOR MIKBUG EQUIV. CONT

CMP A #$30
BCS
CHA51
CMP A #$46
BHI
CHA51
BSR
INHEX1
JSR
BYTE1
DEX
STA A 0,X
CHANGE MEMORY
CMP A 0,X
BEQ
CHA51
DID CHANGE
JMP
LOAD19
DIDN'T CHANGE
C3
LDS
SP
BRA
SWTCTL
**************************************************
*CONTINUE POWER UP SEQUENCE
AL1
STS
SP
INIT TARGET STACK PTR.
LDA A #$FF
JSR
SWISET
*CONFIGURE FOR PIA AND SEE IF OK
LDX
#CTLPOR
JSR
PIAINI
INIT PIA
LDA A 0,X
CMP A 2,X
BRA
AL2

E115 20 19
E117 26 39

BRA

AL2

BRA

BNE

CONTRL

BRA FOR BILOAD

SWTBUG

E119
E11B
E11D
E11F
E121

86
A7
86
A7
20

TSC ASSEMBLER
*INITIALIZE
LDA
STA
LDA
STA
BRA

03
00
11
00
2F

E123 01
E124 BF A0 08
E127
E128
E12A
E12C
E12E

30
6D
26
6A
6A

E130
E133
E136
E139
E13A
E13C
E13E
E140
E142
E144
E147
E14A
E14D
E150

CE
BD
FE
08
8D
8D
8D
8D
8D
CE
BD
FE
8C
27

E1 9D
E0 7E
A0 08

E152
E155
E158
E15B
E15E
E160
E162
E165
E168
E16B
E16E
E171

8E
CE
FF
7F
8D
27
BD
BD
BD
CE
BD
8D

A0
80
A0
A0
73
03
E2
E3
E3
E1
E0
39

E173
E176
E178
E17A
E17D
E17F
E181
E182

CE
A1
26
BD
EE
6E
08
08

E3 D1
00
07
E0 CC
01
00

06
02
05
06

8E
8C
8A
86
84
A0
E0
A0
E1
19

08
C8
12
23

42
04
0A
0C

7D
53
47
9C
7E

AS
A
A
A
A

ACIA
#3
0,X
#$11
0,X
CONTRL

PAGE

ACIA MASTER RESET

*ENTER FROM SOFTWARE INTERRUPT
SF0
NOP
SFE1
STS
SP
SAVE TARGETS STACK POINTER
*DECREMENT P COUNTER
TSX
TST
6,X
BNE
*+4
DEC
5,X
DEC
6,X
*PRINT CONTENTS OF STACK.
PRINT
LDX
#MCL
JSR
PDATA1
LDX
SP
INX
BSR
OUT2HS
COND CODES
BSR
OUT2HS
ACC B
BSR
OUT2HS
ACC A
BSR
OUT4HS
IXR
BSR
OUT4HS
PGM COUNTER
LDX
#SP
JSR
OUT4HS
STACK POINTER
SWTCTL LDX
SWIJMP
CPX
#SF0
BEQ
CONTR1
CONTRL

POF1
CONTR1

LDS
LDX
STX
CLR
BSR
BEQ
JSR
JSR
JSR
LDX
JSR
BSR

#STACK
#CTLPOR
PORADD
PORECH
SAVGET
POF1
PIAECH
PNCHOF
RDOFF
#MCLOFF
PDATA1
INEEE

*COMMAND LOOKUP ROUTINE
LOOK
LDX
#TABLE
OVER
CMP A 0,X
BNE
SK3
JSR
OUTS
LDX
1,X
JMP
0,X
SK3
INX
INX

SET CONTRL STACK POINTER
RESET TO CONTROL PORT
TURN ECHO ON
GET PORT # AND TYPE
SET PIA ECHO ON IF MP-C INTER
TURN PUNCH OFF
TURN READER OFF
PRINT DATA STRING
READ COMMAND CHARACTER

SKIP SPACE

SWTBUG
E183
E184
E187
E189

TSC ASSEMBLER

08
8C E3 F8
26 ED
20 BF

E18B FE A0 12
E18E 6E 00
E190 53
E191 39 04

SWTL1

INX
CPX
BNE
BRA

0D
0A
00
00
31

E19C
E19D
E19E
E1A0
E1A2
E1A4

13
0D
0A 15
00 00
00 24
04

#TABEND+3
OVER
SWTCTL

*SOFTWARE INTERRUPT ENTRY POINT
SFE
LDX
SWIJMP
JUMP TO VECTORED SOFTWARE INT
JMP
0,X
S9

FCB

'S,'9,4

END OF TAPE

15
00
53
04
MCLOFF
MCL

E1A5 20 4C

FCB
FCB

$13
READER OFF
$D,$A,$15,0,0,0,'$,4

EIA5
BRA
BILD
BINARY LOADER INPUT
***************************************************

E1A7 FE A0 06
E1AA 6E 00

*NMI SEQUENCE
NMIV
LDX
JMP

NMI
0,X

E1AC 20 40

INEEE

INEEE1

BD
FF
BD
BD
16
A6
FF
11
27
20
CE
BD
CE
20

***************************************************
MTAPE1 FCB
$D,$A,$15,0,0,0,'S,'1,4 PUNCH FORMAT

E193
E194
E196
E198
E19A

E1AE
E1B1
E1B4
E1B7
E1BA
E1BB
E1BD
E1C0
E1C1
E1C3
E1C5
E1C8
E1CB
E1CE

PAGE

E0
A0
E0
E0

47
04
47
55

00
A0 0D
02
21
E1 9D
E0 7E
A0 0D
10

BRA

GET NMI VECTOR

*BYTE SEARCH ROUTINE
SEARCH JSR
BADDR
GET TOP ADDRESS
STX
ENDA
JSR
BADDR
GET BOTTOM ADDRESS
JSR
BYTE
GET BYTE TO SEARCH FOR
TAB
OVE
LDA A 0,X
STX
XHI
CBA
BEQ
PNT
BRA
INCR1
PNT
LDX
#MCL
JSR
PDATA1
LDX
#XHI
BRA
SKP0
***************************************************
*GO TO USER PROGRAM ROUTINE

SWTBUG

TSC ASSEMBLER

E1D0 3B
E1D1 20 3A

E1D3
E1D6
E1D9
E1DA
E1DC
E1DE
E1DF

FF
FE
37
E6
E1
33
39

A0 10
A0 0A

E1E0
E1E3
E1E6
E1E9
E1EB
E1EC

BD
FE
BC
27
08
20

E0 C8
A0 0D
A0 04
9E

01
03

GOTO
OUTEEE

RTI
BRA

BSR
AND A
RTS

E1F3 31
E1F4 31
E1F5 31

BILD

INS
INS
INS

DA
28
15
00
00
FB
01
A0 0C
07
11

E20D 37
E20E 8D C3
E210 26 2E
E212 C6 11
E214 E7 00
E216 E6 00

OUTEE1

*CONTINUATION OF SEARCH ROUTINE
SKP0
JSR
OUT4HS
LDX
XHI
INCR1
CPX
ENDA
BEQ
SWTL1
INX
BRA
OVE
INEEE1

37
8D
26
86
A7
A6
47
24
A6
F6
27
20

*SAVE IXR AND LOAD IXR WITH CORRECT
*PORT NUMBER AND TEST FOR TYPE
SAVGET STX
XTEMP
STORE INDEX REGISTER
GETPT1 LDX
PORADD
ISACIA PSH B
LDA B 1,X
CMP B 3,X
PUL B
RTS
***************************************************

E1EE 8D 06
E1F0 84 7F
E1F2 39

E1F6
E1F7
E1F9
E1FB
E1FD
E1FF
E201
E202
E204
E206
E209
E20B

PAGE

INCH8
INPUT 8 BIT CHARACTER
#%01111111 GET RID OF PARITY BIT

FIX UP STACK WHEN USING
BINARY LOADER ON SWTPC TAPES

*INPUT ONE CHAR INTO ACC
INCH8
PSH B
BSR
SAVGET
BNE
IN1
LDA A #$15
STA A 0,X
ACIAIN LDA A 0,X
ASR A
BCC
ACIAIN
LDA A 1,X
LDA B PORECH
BEQ
ACIOUT
BRA
RES
*OUTPUT ONE CHARACTER
OUTEE1 PSH B
BSR
SAVGET
BNE
IOUT
ACIOUT
ACIOU1

LDA B
STA B
LDA B

#$11
0,X
0,X

B
SAVE ACC B
SAVE IXR, GET PORT# AND TYPE
INPUT FROM PIA IF NOT
RECONFIG FOR 8 BIT, 1 SB

NOT READY
LOAD CHAR
ECHO
DON'T ECHO

SAVE ACC B

SWTBUG

TSC ASSEMBLER

E218
E219
E21A
E21C
E21E
E21F
E222

57
57
24 FA
A7 01
33
FE A0 10
39

E223
E225
E227
E229
E22B
E22D
E22E
E230
E231
E233
E234
E235
E237
E239
E23C
E23E

A6
2B
8D
C6
E7
58
8D
0D
69
46
5A
26
8D
F6
27
20

00
FC
3A
04
02

E240
E242
E244
E246
E248
E24A
E24C
E24D
E24E
E24F
E251
E253
E254
E256
E258
E25A
E25C
E25E
E260
E262

8D
C6
6A
8D
8D
A7
0D
46
5A
26
E6
58
2A
8D
20
6D
2A
6C
6A
39

23
0A
00
16
10
00

2A
00

F7
21
A0 0C
13
DE

F7
02
C8
02
C4
02
FC
02
02

E263 6F 02
E265 8D F7
E267 20 F1

E269 8D 83

RES

ASR
ASR
BCC
STA
PUL
LDX
RTS

CLR
BSR
BRA

B
B
A
B

ACIOU1
1,X

ACIA NOT READY
OUTPUT CHARACTER
RESTORE ACC B

XTEMP

*PIA INPUT ROUTINE
IN1
LDA A 0,X
BMI
IN1
BSR
DDL
LDA B #4
STA B 2,X
ASL B
IN3
BSR
DEL
SEC
ROL
0,X
ROR A
DEC B
BNE
IN3
BSR
DEL
LDA B PORECH
BEQ
IOUT2
BRA
RES
*PIA OUTPUT ROUTINE
IOUT
BSR
DDL1
LDA B #$A
DEC
0,X
BSR
DE
OUT1
BSR
DEL
STA A 0,X
SEC
ROR A
DEC B
BNE
OUT1
IOUT2
LDA B 2,X
ASL B
BPL
RES
BSR
DEL
BRA
RES
DEL
TST
2,X
BPL
DEL
DE
INC
2,X
DEC
2,X
RTS
DDL
DDL1

PAGE

2,X
DE
DEL

LOOK FOR START BIT
DELAY HALF BIT TIME
SET DEL FOR FULL BIT TIME
SET UP CNTR WITH 8
WAIT ONE CHAR TIME

WAIT FOR STOP BIT
IS ECHO DESIRED?
ECHO
RESTORE IXR,ACCB
DELAY ONE HALF BIT TIME
SET UP COUNTER
SET START BIT
START TIMER
DELAY ONE BIT TIME
PUT OUT ONE DATA BIT
SHIFT IN NEXT BIT
DECREMENT COUNTER
TEST FOR 0
TEST FOR STOP BITS
SHIFT BIT TO SIGN
BRA FOR 1 STOP BIT
DELAY FOR STOP BITS
IS TIME UP
RESET TIMER

HALF BIT DELAY

*OPTIONAL PORT ROUTINE
OPTL
BSR
INEEE1

SWTBUG

TSC ASSEMBLER

E26B
E26C
E26F
E272
E274
E276
E279
E27A

16
7F
FE
8D
8D
CE
17
7E

E27D
E27F
E281
E283

86 34
A7 03
A7 02
39

E284
E286
E288
E28A
E28C
E28E

6C
86
A7
6C
A7
39

00
07
01
00
02

E28F
E292
E294
E296
E298
E29A
E29C
E29E
E2A0
E2A2
E2A4
E2A6
E2A9
E2AB
E2AD
E2B0
E2B2
E2B3
E2B6
E2B8
E2BA
E2BD
E2BF
E2C1

7F
8D
C6
8D
E6
C5
26
6F
8D
C6
8D
CE
C5
27
B6
A7
08
F6
C5
26
7E
E7
8D
39

80 14
2E
0B
25
04
01
FA
06
1D
9C
17
24 00
02
06
80 1B
00

E2C2
E2C5
E2C6
E2C9
E2CB

CE FF FF
09
8C 80 14
26 FA
39

TAB
CLR
LDX
BSR
BSR
LDX
TBA
JMP

A0 0B
A0 0A
10
07
E3 EF
E1 76

80 18
01
EF
24 00
04
00

PIAECH

NOOPT

LDA A
STA A
STA A
RTS

SET I/O ADDRESS FOR $8000

OVER

LOOK AT TABLE FOR E, L OR P

#$34
3,X
2,X

SET DDR

INITIALIZE PIA
SET ECHO
P, L OR E

DISK BOOT
$8014
DELAY
B #$0B
RETT2
B 4,X
B #1
LOOP1
6,X
RETURN
B #$9C
RETT2
#$2400
B #2
LOOP3
A $801B
A 0,X
B
B

PORADD+1
PORADD
PIAINI
PIAECH
#TABLE1

*PIA INITIALIZATION ROUTINE
PIAINI INC
0,X
SET DDR
LDA A #$7
STA A 1,X
INC
0,X
STA A 2,X
RTS
*MINIFLOPPY
DISK
CLR
BSR
LDA
BSR
LOOP1
LDA
BIT
BNE
CLR
BSR
LDA
BSR
LDX
LOOP2
BIT
BEQ
LDA
STA
INX
LOOP3
LDA
BIT
BNE
JMP
RETT2
STA
RETURN BSR
RETT1
RTS

PAGE

$8018
#1
LOOP2
$2400
4,X
RETT1

*GENERAL PURPOSE DELAY LOOP
DELAY
LDX
#$FFFF
DELAY1 DEX
CPX
#$8014
STOP AT 8014
DUM
BNE
DELAY1
RTS

SWTBUG

TSC ASSEMBLER

E2CC
E2CF
E2D2
E2D4
E2D7

CE
BD
8D
BD
20

E0 09
E0 7E
F1
E3 47
58

E2D9
E2DC
E2DF
E2E1
E2E2
E2E4
E2E7
E2EA
E2EC
E2EF
E2F1
E2F3
E2F6
E2F8
E2FB
E2FE
E301
E303
E306

CE
BC
27
08
8D
BD
FF
A6
B7
86
A7
CE
8D
7E
FE
B6
A7
CE
20

E1 23
A0 12
1A

E308
E30B
E30E
E311
E313
E316
E319

B7
FE
8C
27
CE
FF
39

A0
A0
E1
06
E1
A0

32
E0
A0
00
A0
3F
00
E1
1E
E1
A0
A0
00
E1
DA

47
14
16

23
6B
14
16
24

E31E
E321
E324
E325
E327
E32A
E32D
E32F
E331

CE
FF
09
8D
CE
BD
8D
8D
7E

*BREAKPOINT
BREAK
LDX
CPX
BEQ
INX
BREAK0 BSR
JSR
STX
LDA
STA
LDA
STA
LDX
BSR
JMP
INUSE
LDX
LDA
STA
LDX
BRA
SWISET

24
12

STO
STO1
STORTN

A0 49
A0 04
52
E1 90
E0 7E
24
91
E1 52

E334 73 A0 0C
E337 86 11

*CLRAR SCREEN FOR CT-1024 TYPE TERMINALS
CLEAR
LDX
#CURSOR
JSR
PDATA1
BSR
DELAY1
DELAY
RDOFF1 JSR
RDOFF
BRA
C4

43
12
23

E31A 8D 5A
E31C 20 0F

PAGE

PUNCH1

ENTERING ROUTINE
#SF0
SWIJMP
BREAKPOINTS ALREADY IN USE?
INUSE

A
A
A
A

A
A

STO1
BADDR
BKPT
0,X
BKLST
#$3F
0,X
#SF0
STO1
CONTR1
BKPT
BKLST
0,X
#SFE1
BREAK0

STA A
LDX
CPX
BEQ
LDX
STX
RTS

STACK+1
SWIJMP
#SF0
STORTN
#SFE1
SWIJMP

BSR
BRA

PUNCH
POFC4

FIX POWER UP INTERRUPT

*FORMAT END OF TAPE WITH PGM. CTR. AND S9
PNCHS9 LDX
#$A049
STX
ENDA
DEX
BSR
PUNCH2
LDX
#S9
PDAT
JSR
PDATA1
POFC4
BSR
PNCHOF
BSR
DELAY
C4
JMP
CONTRL
RDON

COM
LDA A

PORECH
#$11

DISABLE ECHO FOR ACIA
RON CHAR.

SWTBUG
E339
E33B
E33D
E340
E342
E344
E346

C6
8D
BD
27
86
A7
39

TSC ASSEMBLER
20
1A
E1 D9
04
3C
03
RTNN

LDA B
BSR
JSR
BEQ
LDA A
STA A
RTS

#$20
STROBE
ISACIA
RTNN
#$3C
3,X

STROBE CHAR

TURN READER OFF

E347 86 13
E349 C6 10
E34B 20 0A

RDOFF

LDA A
LDA B
BRA

#$13
#$10
STROBE

E34D 86 12
E34F C6 04
E351 20 04

PNCHON

LDA A
LDA B
BRA

#$12
#4
STROBE

E353 86 14
E355 C6 08

PNCHOF

LDA A
LDA B

#$14
#$8

E357
E35A
E35D
E35F
E361
E363
E365
E367
E369
E36B
E36D
E36F
E371
E373
E375

E376
E379
E37C
E37E
E381
E384
E387
E38A
E38C
E38E
E390
E392
E394
E397
E399

BD
BD
27
86
CA
8D
8D
86
C6
E7
8D
86
A7
E7
39

FE
FF
8D
B6
B0
F6
F2
26
81
25
86
8B
B7
80
B7

E0 75
E1 D6
16
02
01
0C
08
02
01
00
02
06
01
00

A0
A0
CF
A0
A0
A0
A0
04
10
02
0F
04
A0
03
A0

02
44
05
45
04
44

47
46

PAGE

CHECK TO SEE IF PIA
DISABLE PIA ECHO IF PIA

*PIA STROBING ROUTINE FOR PUNCH/READ ON/OFF
STROBE JSR
OUTCH
JSR
GETPT1
BEQ
RTN1
LDA A #2
ORA B #1
BSR
STR2
BSR
STR1
LDA A #2
LDA B #1
STA B 0,X
BSR
STR2
STR1
LDA A #6
STR2
STA A 1,X
STA B 0,X
RTN1
RTS
*PUNCH FROM BEGINNING ADDRESS (BEGA) THRU
*ENDING ADDRESS (ENDA)
PUNCH
LDX
BEGA
PUNCH2 STX
TW
BSR
PNCHON
PUN11
LDA A ENDA+1
SUB A TW+1
LDA B ENDA
SBC B TW
BNE
PUN22
CMP A #16
BCS
PUN23
PUN22
LDA A #15
PUN23
ADD A #4
STA A BYTECT
SUB A #3
STA A TEMP
*PUNCH C/R L/F NULLS S1

SWTBUG

TSC ASSEMBLER

E39C CE E1 93
E39F BD E0 7E
E3A2 5F
E3A3 CE A0 47
E3A6 8D 24
E3A8 CE A0 44
E3AB 8D 1F
E3AD 8D 1D
E3AF
E3B2
E3B4
E3B7
E3B9
E3BC
E3BD
E3BE
E3BF
E3C1
E3C2
E3C5
E3C6
E3C9
E3CB

FE
8D
7A
26
FF
53
37
30
8D
33
FE
09
BC
26
39

A0 44
18
A0 46
F9
A0 44

0B
A0 44
A0 04
B3

LDX
#MTAPE1
JSR
PDATA1
CLR B
*PUNCH FRAME COUNT
LDX
#BYTECT
BSR
PUNT2
*PUNCH ADDRESS
LDX
#TW
BSR
PUNT2
BSR
PUNT2
*PUNCH DATA
LDX
TW
PUN32
BSR
PUNT2
DEC
TEMP
BNE
PUN32
STX
TW
COM B
PSH B
TSX
BSR
PUNT2
PUL B
LDX
TW
DEX
CPX
ENDA
BNE
PUN11
RTN5
RTS

PAGE

PUNCH 2 HEX CHARACTERS

PUNCH ONE BYTE

PUNCH CHECKSUM
RESTORE STACK

E3CC EB 00
E3CE 7E E0 BF

*PUNCH 2 HEX CHAR, UPDATE CHECKSUM
PUNT2
ADD B 0,X
JMP
OUT2H
OUTPUT 2 HEX CHAR AND RTS

E3D1
E3D2
E3D4
E3D5
E3D7
E3D8
E3DA
E3DB
E3DD
E3DE
E3E0
E3E1
E3E3
E3E4
E3E6
E3E7
E3E9
E3EA
E3EC
E3ED
E3EF
E3F0

*COMMAND TABLE
TABLE
FCB
FDB
FCB
FDB
FCB
FDB
FCB
FDB
FCB
FDB
FCB
FDB
FCB
FDB
FCB
FDB
FCB
FDB
FCB
FDB
TABLE1 FCB
FDB

47
E1
5A
C0
4D
E0
46
E1
52
E1
4A
E0
43
E2
44
E2
42
E2
4F
E2
50
E3

D0
00
88
AE
30
05
CC
8F
D9
69
1A

'G
GOTO
'Z
PROM
'M
CHANGE
'F
SEARCH
'R
PRINT
'J
JUMP
'C
CLEAR
'D
DISK
'B
BREAK
'O
OPTL
'P
PUNCH1

GOTO
GOTO PROM
MEMORY EXAM AND CHANGE
BYTE SEARCH
REGISTER DUMP
JUMP
CLEAR SCREEN
DISK BOOT
BREAKPOINT
OPTIONAL PORT
ASCII PUNCH

SWTBUG

TSC ASSEMBLER

E3F2
E3F3
E3F5
E3F6

4C
E0 0C
45
E3 1E

E3F8
E3F8
E3FA
E3FC
E3FE

E0
E1
E1
E0

TABEND

00
8B
A7
D0

A048
A048 E0 D0

FCB
FDB
FCB
FDB

'L
LOAD
'E
PNCHS9

ORG
FDB
FDB
FDB
FDB

$E3F8
IRQV
SFE
NMIV
START

ORG
FDB
END

$A048
START

ERROR(S) DETECTED

PAGE

ASCII LOAD
END OF TAPE

IRQ VECTOR
SOFTWARE INTERRUPT
NMI VECTOR
RESTART VECTOR

SWTBUG

TSC ASSEMBLER

PAGE

SYMBOL TABLE:
ACIAIN
AL3
BILD
BYTE
C4
CONTR1
DDL1
DISK
GETPT1
INCH
INHEX
IRQ
LOAD11
LOOK
MCLOFF
OPTL
OUT4HS
OUTHR
PDATA1
PNCHON
PORADD
PUN22
PUNCH2
RES
RTN5
SF0
SKP0
STO1
SWIJMP
TABLE
XLOW

E1FF
E0D5
E1F3
E055
E331
E16B
E265
E28F
E1D6
E078
E0AA
A000
E02B
E173
E19C
E269
E0C8
E06B
E07E
E34D
A00A
E390
E379
E21E
E3CB
E123
E1E0
E316
A012
E3D1
A00E

ACIOU1
AL4
BKLST
BYTE1
CHA51
CONTRL
DE
DUM
GOTO
INCH8
INHEX1
IRQV
LOAD15
LOOP1
MTAPE1
OUT1
OUTCH
OUTS
PDATA2
PNCHS9
PORECH
PUN23
PUNT2
RETT1
RTNN
SFE
SP
STORTN
SWISET
TABLE1
XTEMP

E216
E0E5
A016
E057
E08A
E152
E25E
E2C9
E1D0
E1F6
E0AC
E000
E03B
E298
E193
E248
E075
E0CC
E07B
E31E
A00C
E392
E3CC
E2C1
E346
E18B
A008
E319
E308
E3EF
A010

ACIOUT
ANOTH
BKPT
BYTECT
CHANGE
CTLPOR
DEL
EIA5
IN1
INCR1
INUSE
ISACIA
LOAD19
LOOP2
NMI
OUT2H
OUTEE1
OVE
PIAECH
PNT
PRINT
PUN32
RDOFF
RETT2
S9
SFE1
STACK
STR1
SWTCTL
TEMP

E212
E09B
A014
A047
E088
8004
E25A
E1A5
E223
E1E6
E2FB
E1D9
E040
E2A9
A006
E0BF
E20D
E1BB
E27D
E1C5
E130
E3B2
E347
E2BD
E190
E124
A042
E36F
E14A
A046

AL1
BADDR
BREAK
C1
CKSM
CURSOR
DELAY
ENDA
IN1HG
INEEE
IOUT
JUMP
LOAD21
LOOP3
NMIV
OUT2HA
OUTEEE
OVER
PIAINI
POF1
PROM
PUNCH
RDOFF1
RETURN
SAVGET
SK1
START
STR2
SWTL1
TW

E101
E047
E2D9
E085
A00F
E009
E2C2
A004
E0BE
E1AC
E240
E005
E044
E2B3
E1A7
E0C1
E1D1
E176
E284
E165
C000
E376
E2D4
E2BF
E1D3
E0DE
E0D0
E371
E189
A044

AL2
BEGA
BREAK0
C3
CLEAR
DDL
DELAY1
EOE3
IN3
INEEE1
IOUT2
LOAD
LOAD3
MCL
NOOPT
OUT2HS
OUTHL
PDAT
PNCHOF
POFC4
PUN11
PUNCH1
RDON
RTN1
SEARCH
SK3
STO
STROBE
TABEND
XHI

E117
A002
E2E2
E0FC
E2CC
E263
E2C5
E0E3
E22E
E1EE
E251
E00C
E00F
E19D
E283
E0CA
E067
E32A
E353
E32D
E37E
E31A
E334
E375
E1AE
E181
E313
E357
E3F5
A00D

SWTPC 6800 Short Memory Address Convergence MEMCON-3
MODIFIED FOR MIKBUG® OR SWTBUG®
This Memory Convergence diagnostic is one designed to check for and locate address
convergence problems in SWTPC 6800 Computer System memory boards. The program itself
uses 5610 words and is meant to be loaded within the 128 word RAM used by the SWTBUG®
operating system on the MPA Microprocessor System board making the program independent of
the MPM RAM memory. The diagnostic may be loaded from either tape or from the terminal
instruction by instruction using SWTBUG® starting from address A01416 thru A03316 and then
from A04816 thru A05116. The program must be loaded in two parts to avoid interfering with the
system’s pushdown stack. The section of memory to be tested is set by loading the most
significant byte of the lower memory address into A00216 the least significant byte of the lower
memory address into A00316 the most significant byte of the upper memory address into A00416
and the least significant byte of the upper memory address into A00516 using SWTBUG® just as
is done for SWTBUG® punch routine. The lower and upper addresses are inclusive and may be
any addresses between 000016 and FFFF16 with the only requirement that the lower address be
less than or equal to the upper address. Since addresses A05F16 thru A07F16 of the SWTBUG®
RAM are still available for program use, the diagnostic may run on these locations just to make
sure the diagnostic itself is functioning correctly, Since the program counter is set when the
program 1s initially loaded, the routine is initiated by typing G for “Go To User Program”. Once
initiated, the program can be stopped only by depressing the “RESET” button. The program may
then be restarted after setting the program counter to A01416 at A048 and A049.
The test sequence starts by loading a continuous stream of 256 sequential binary numbers
from the low memory address to the high memory address, inclusive. It then goes back and
sequentially reads the data in each of the locations and compares it to what actually should be
there. If it finds any discrepancies within the memory cycle, one X is printed and the cycle is
restarted, otherwise a # is printed to indicate successful cycle completion. Since the actual
location of any detected errors does not point to the source of the problem, no provision is made
for indicating the addresses of detected errors. It must also be noted that the program is not
100% effective. It would be possible to set bits in multiple locations that coincidentally would have
been set anyway. However, each cycle puts different data in each memory location, so the
chances of a missed problem are reduced. The program loops forever and may be exited when
desired by depressing the “RESET” switch which loads the SWTBUG® control program.
If you wish to eliminate the cyclic printout of the "# " sign you can do so by changing the data
in address locations A059, A05A and A05B to NOP instructions (0116) using SWTBUG®. This
way you only get a printout of the error cycles, if any.
MIKBUG® is a registered trademark of Motorola Inc.
SWTBUG® is a registered trademark of Southwest Technical Products Corporation.

NAM
MEMCON3
*SHORT MEMORY ADDRESS CONVERGENCE TEST
*FOR SWTPC 6800 COMPUTER SYSTEMS
*MIKBUG AND SWTBUG COMPATIBLE
A002
A004
E1D1

LOMEM
HIMEM
OUTEEE

A014
A014
A017
A01A
A01C
A01F
A021
A022
A023
A025
A028
A02B
A02D
A02F
A032

F7
FE
E7
BC
27
08
5C
20
F6
FE
E1
26
BC
20

A0 5F
A0 02
00
A0 04
04

A048
A048
A04A
A04C
A04D
A04E
A050
A052
A055
A057
A059
A05C
A05D
A05F

A0
27
08
5C
20
86
BD
20
86
BD
5A
20
00

14
0B

F5
A0 5D
A0 02
00
21
A0 04
16

DB
58
E1 D1
BD
23
E1 D1

START
LOOP1

CHECK
LOOP2

JUMP

ERROR

CYCLE

B5
BSTORE

EQU
EQU
EQU
ORG
STA
LDX
STA
CPX
BEQ
INX
INC
BRA
LDA
LDX
CMP
BNE
CPX
BRA
ORG
FDB
BEQ
INX
INC
BRA
LDA
JSR
BRA
LDA
JSR
DEC
BRA
FCB
END

$A002
$A004
$E1D1

B
B

STARTING ADDRESS
ENDING ADDRESS
CHARACTER OUTPUT

$A014
BSTORE
LOMEM
0,X
HIMEM
CHECK

STORE ACCCB
LOAD LOW MEMORY ADDRESS
END OF MEMORY?
CHECK IF FINISHED

B
B
B

LOOP1
BSTORE
LOMEM
0,X
ERROR
HIMEM
JUMP

CHECKS ALL LOCATIONS FOR CORR

$A048
START
CYCLE
B
A

LOOP2
#'X
OUTEEE
START
#'#
OUTEEE

B
START
0

PRINT X IF ERROR FOUND
START OVER
PRINT # FOR CORRECT CYCLE

Dual Address Memory Test CDAT
By John Christensen
The CDAT memory diagnostic can be used to help locate memory problems in a SWTPC
6800 computer system that MEMCON and ROBIT may miss. The program itself resides entirely
within the 128 byte SWTBUG® RAM. The program must be loaded in two parts to avoid
interfering with the systems push down stack. The contiguous section of memory to be tested is
set by loading the most significant byte of the lower memory address into A002, the least
significant byte into A003, the most significant byte of the upper memory address in A004 and its
least significant byte in A005. The low address must be less than or equal to the upper address.
The test starts from the low address and writes a 00 into all memory up to the high address.
An FF is then written into the first address and all other locations are checked to be sure they
contain 00. If all are OK the FF is replaced with a 00 and an FF is written in the next memory
location. This pattern continues until all memory is checked or an error is found. If the computer
returns to SWTBUG®, then no errors were found.
If the program displays a register dump then a problem was discovered on the board. The
register dump should look similar to the following:
ADDRESS
V
F3 00 FF 0400

ERROR MSG.
V
A079 A042.

The important parts of the dump are the ADDRESS and the ERROR MSG. areas, as
denoted above. The error messages are interpreted as follows:
A077
A078
A079
A07A

Error on initial test pattern (can't write 0's into mem.)
Error on second test pattern (can't write FF's into mem.)
Dual address error low
Dual address error high

If a dual address error is found then writing into one memory location affects another. For
example, if ADDRESS = 0400 and A016 contains 0410 then writing into 0400 will change the
contents of 0418 or vice-versa. (A014 is a temporary index register storage location within the
program that you can compare with ADDRESS in the register dump to see which two memory
locations caused the error). The IC assignments table included with the memory board
instructions can then be used to help locate the problem by comparing the bit pattern of the
locations in error.
The CDAT program takes some time to run, so run the diagnostic over only one complete
board at a time.
MEM. SIZE
1K
2K
3K
4K
8K

APPROX. RUN TIME
29 sec.
1 min. 53 sec.
4 min. 13 sec.
7 min. 29 sec.
more than 30 min.

MIKBUG® is a registered trademark of Motorola Inc.
SWTBUG® is a registered trademark of Southwest Technical Products Corporation.

E0E3
A002
A002
A004
A014
A014
A016
A019
A01C
A01E
A020
A022
A025
A027
A028
A02A
A02D
A030
A032
A048
A048
A04A
A04C
A04E
A051
A054
A056
A057
A059
A05B
A05D
A060
A063
A065
A066
A068
A06A
A06D
A06F
A072
A074
A075
A077
A078
A079
A07A
A07B

FE
B6
A7
A1
26
BC
27
08
20
FE
F6
E7
20

A0 02
A0 7E
00
00
55
A0 04
03

A0
E1
26
FF
BC
27
09
A1
26
20
FE
BC
27
08
A1
26
BC
26
FE
A7
08
20
3F
3F
3F
3F
7E

16
00
2A
A0 14
A0 02
07

A07E 00
A07F 00

F2
A0 02
A0 7F
00
16

00
1E
F4
A0 14
A0 04
16
00
10
A0 04
F6
A0 14
00
B9

E0 E3

NAM
CDAT-2
*MEM DIAGNOSTIC (JOHN CHRISTENSEN'S)
*MODIFIED FOR MIKBUG AND SWTBUG OPERATION
CONTRL EQU
$E0E3
ORG
$A002
LOTEMP RMB
2
STARTING ADDRESS
HITEMP RMB
2
ENDING ADDRESS
ORG
$A014
IXRTMP RMB
2
IXR TEMPORARY STORAGE
START
LDX
LOTEMP
LDA A INIPAT
LOOP1
STA A 0,X
CMP A 0,X
BNE
ERPNT1
CPX
HITEMP
BEQ
LOAPAT
INX
BRA
LOOP1
LOAPAT LDX
LOTEMP
LDA B TESPAT
LOOP4
STA B 0,X
BRA
CHECK
ORG
$A048
FDB
START
CHECK
CMP B 0,X
BNE
ERPNT2
CHKLOW STX
IXRTMP
LOOP2
CPX
LOTEMP
BEQ
CHCKHI
DEX
CMP A 0,X
BNE
ERPNT3
BRA
LOOP2
CHCKHI LDX
IXRTMP
CPX
HITEMP
BEQ
END
LOOP3
INX
CMP A 0,X
BNE
ERPNT4
CPX
HITEMP
BNE
LOOP3
RESTRE LDX
IXRTMP
STA A 0,X
INX
BRA
LOOP4
ERPNT1 SWI
ERROR ON INITIAL PATTERN
ERPNT2 SWI
ERROR ON TEST PATTERN
ERPNT3 SWI
DUAL ADDRESS ERROR LOW
ERPNT4 SWI
DUAL ADDRESS ERROR LO
END
JMP
CONTRL
INIPAT
TESPAT

FCB
FCB
END

0
0

SWTPC 6800 Rotating Bit RAM Memory Diagnostic ROBIT-2
Modified for MIKBUG® or SWTBUG® use
This rotating bit memory diagnostic is designed to check for and locate memory retaining
problems in SWTPC 6800 Computer System memory boards. The program itself uses 8510
words and is meant to be loaded within the 128 word RAM used by the SWTBUG® operating
system on the MP-A Microprocessor System board. This makes the program independent of
external RAM memory. The diagnostic may be loaded from either tape or from the terminal
instruction by instruction using SWTBUG® starting from address A01416 thru A067E16. The
program must be loaded in two parts to avoid interfering with the system’s pushdown stack. The
contiguous section of memory to be tested is set by loading the most significant byte of the lower
memory address into A00216, the least significant byte of the lower memory address into A00316,
the most significant byte of the upper memory address into A00416, and the least significant byte
of the upper memory address into A00516 using SWTBUG® just as is done for the SWTBUG®
punch routine. The lower and upper addresses are inclusive and may be any addresses between
000016 and FFFF16 with the only requirement being that the lower address be less than or equal
to the upper address. Since the program counter is set when the program is initially loaded, the
routine is initiated after loading by typing G for “Go To User’s Program”. Once initiated, the
program may then be restarted after setting the program counter to A01416 at A048 and A049.
The test sequence starts from the lower address and loads that address with a binary 0000
0001 or 0116 The data in this location is then read and verified. If accurate the “one” bit is shifted
left to form a binary 0000 0010 or 0216 and is then again tested. This shift left sequence continues
until a binary 1000 0000 or 8016 has been loaded and verified, at which time the entire sequence
is repeated at the next sequential memory address. This sequence continues until the selected
upper memory address is reached. The program then prints a "+" on the control terminal to
indicate cycle completion and proceeds to repeat Itself. The program loops forever and may be
exited when desired by depressing the “RESET” switch which loads the SWTBUG® control
program. When an error is detected, the memory address followed by what data should have
been followed by what the memory data was, are printed out on the control terminal in
hexadecimal (base 16) form. Example:
$0110 02 00
When converted to binary this means that when address 0110, which is located in the first
1,024 words of RAM memory, was loaded with a binary 0000 0010 it was read back as containing
a binary 0000 0000 which indicates a possible problem in the 21 bit memory chip in the lower
1,024 words of memory or a possible problem in the 21 bit of the memory board data transceiver
or a variety of other possibilities. The best way to tell for sure is to look for a pattern in the
indicated errors. Take note that once one bit error has been located at a specific memory
address, the one error is printed in the form shown above and the program increments to the next
address without searching for more errors in the already defective address.
If you wish to eliminate the cyclic printout of the "+" sign you can do so by changing the data
in address locations A076, A077 and A078 to NOP instructions (0116) using SWTBUG. This way
you only get a printout of the error locations; that is if there are any. The running time of this
program is very fast. It will cycle thru 2,048 words of memory in less than one second.

MIKBUG® is a registered trademark of Motorola Inc.
SWTBUG® is a registered trademark of Southwest Technical Products Corporation.

NAM
ROBIT-2
*PRTATING BIT MEMORY TEST FOR MIKBUG
*OR SWTBUG 6800 COMPUTER SYSTEM
A002
A004
E07E
E0C8
E0CA
E19D
E1D1
A014
A014
A017
A019
A01B
A01D
A01F
A020
A022
A024
A026
A028
A02A
A02C
A02F
A032
A048
A048
A04A
A04D
A050
A053
A056
A059
A05C
A05F
A062
A065
A068
A06B
A06E
A070
A071
A073
A076
A079
A07B
A07C
A07D
A07E

LOTEMP
HITEMP
PDATA1
OUT4HS
OUT2HS
MCL
OUTEEE

FE
86
A7
A1
26
48
68
A1
26
81
26
20
FF
CE
20

A0 02
01
00
00
0D

A0
B7
BD
CE
BD
CE
BD
FE
BD
CE
BD
FE
BC
27
08
20
B6
BD
20

14
A0
E0
A0
E0
A0
E0
A0
E0
E1
E0
A0
A0
03

START
LODREG

LOOP1
00
00
06
80
F5
3F
A0 7B
E1 9D
16

7D
7E
7B
C8
7D
CA
7B
CA
9D
7E
7B
04

A4
A0 7E
E1 D1
99

ERRPNT

SKIP1

INCR1

FINISH

INXMSB
INXLSB
ACCA
FLAG
END

EQU
EQU
EQU
EQU
EQU
EQU
EQU

$A002
$A004
$E07E
$E0C8
$E0CA
$E19D
$E1D1

ORG
LDX
LDA
STA
CMP
BNE
ASL
ASL
CMP
BNE
CMP
BNE
BRA
STX
LDX
BRA

$A014
LOTEMP
#1
0,X
0,X
ERRPNT

A
A
A

STORE 1 IN MEMORY
WAS 1 WRITTEN

A
A
A

ORG
FDB
STA A
JSR
LDX
JSR
LDX
JSR
LDX
JSR
LDX
JSR
LDX
CPX
BEQ
INX
BRA
LDA A
JSR
BRA
RMB
RMB
RMB
FCB

0,X
0,X
ERRPNT
#$80
LOOP1
INCR1
INXMSB
#MCL
SKIP1
$A048
START
ACCA
PDATA1
#INXMSB
OUT4HS
#ACCA
OUT2HS
INXMSB
OUT2HS
#MCL
PDATA1
INXMSB
HITEMP
FINISH
LODREG
FLAG
OUTEEE
START
1
1
1
'+

SHIFT UNTIL 80

PRINT C/R L/F

LOAD ERROR ADDRESS

OUTPUT WHAT SHOULD BE STORED

COMPARE TO END ADDRESS

SUMTEST - 2 -- Address Variable Memory Test
By Chris Courtney, RESPCO Inc.
The SUMTEST memory diagnostic can be used to supplement the ROBIT, MEMCON and
CDAT tests. The program itself resides entirely within the 128 byte MIKBUG®/SWTBUG® RAM
and must be loaded in two parts to avoid interfering with the system’s push down stack. The
contiguous section of memory to be tested is set by loading the most significant byte of the lower
memory address into A002, the least significant byte into A003, the most significant byte of the
upper memory address in A004 and its least significant byte in A005. When inputting the upper
address use 1+ (upper location you want to check). TO check the entire lowest 4K board, for
example, you would use an upper memory address of 1000, not OFFF. When loading the
diagnostic the program counter is automatically set to the starting address of the program. Typing
G will initiate the program.
If no errors are found in the memory being checked a + will be displayed on the screen. To
completely test an area of memory the diagnostic must be allowed to run until 256 +’s have been
displayed on the screen. Each time a + is displayed on the screen SUMTEST has successfully
cycled through memory storing and reading a different pattern. If an error is detected the output
wilt be similar to the following:
$G +++++
$06 20 16A0
(PATTERN #) (ERRANT BITS) (ADDRESS)

An error message such as this says that SUMTEST cycled thru memory five times without
error, but on the sixth try a pattern was used that detected an error. The 06 tells what pattern
number SUMTEST was working on when the error was detected. The 20 tells which bits were in
error. 2016 converted to binary is 00100000 - the location of the 1 is the bit that is in error, in this
case bit 5. Bit numbers start from 0 as shown:
2016 =

0 0 1 0 0 0 0 0
7 6 5 4 3 2 1 0 BIT#

The 16A0 is the address where the error was detected. This address may not store a
particular number or possibly writing into another address, such as 16B0, changed the contents
of 16A0.
The IC assignment table supplied with the memory board should be used to help locate the
problem. In the above case on an MP-8M 8K memory board the bit # 5 IC in the upper 4K of
memory should be suspected.
Be sure to re-load the program before testing another area of memory. SUMTEST runs fast
enough that it can be used on an entire 32K system in an acceptable amount of time.

MIKBUG is a registered trademark of Motorola, Inc.
®
SWTBUG a registered trademark of Southwest Technical Products Corp.

NAM
SUMTEST2
*IMPROVED MEMORY TEST FOR SWTPC 6800
*BYTES STORED IN MEMORY ARE THE SUM OF THE
*MSB AND LSB OF THE MEMORY POINTER, THEREFORE
*ADJACENT MEMORY LOCATIONS AND ADJACENT
*PAGES CONTAIN UNIQUE CONTENTS
*INITIALIZE LOWEST MEMORY ADDRESS IN LOTEMP
*AND HIGHEST MEMORY ADDRESS+1 IN HITEMP
*MODIFIED FOR MIKBUG OR SWTBUG
A002
A002
A004
E07E
E1D1
E0CA
E0C8
E19D

LOTEMP
HITEMP
PDATA1
OUTEEE
OUT2HS
OUT4HS
MCL

A014
A014
A015
A016
A017
A018
A01B
A01D
A01F
A020
A023
A025
A028
A02A
A02C
A02E
A02F
A032

00
00
00
00
FE
8D
A7
08
BC
26
FE
8D
A8
26
08
BC
20

A048
A048
A04A
A04C
A04E
A051
A054
A056
A059
A05C
A05F
A062
A063
A066
A069
A06C
A06F
A072
A075
A078
A07B

A0
26
86
BD
7C
20
FF
B6
BB
BB
39
B7
CE
BD
CE
BD
BD
BD
FE
20

A0 02
39
00
A0 04
F6
A0 02
2C
00
35

CTR
STORE
INXMSB
INXLSB
START
LOOP1

LOOP2

RETURN
A0 04
16

18
DC
2B
E1
A0
C2
A0
A0
A0
A0
A0
E1
E0
A0
E0
E0
E0
A0
B1

SKIP1
D1
14
16
16
17
14

INCRX

15
9D
7E
14
CA
CA
C8
16

ERROR

ORG
RMB
RMB
EQU
EQU
EQU
EQU
EQU

$A002
2
2
$E07E
$E1D1
$E0CA
$E0C8
$E19D

ORG
FCB
FCB
FCB
FCB
LDX
BSR
STA A
INX
CPX
BNE
LDX
BSR
EOR A
BNE
INX
CPX
BRA

$A014
0
0
0
0
LOTEMP
INCRX
0,X

HITEMP
SKIP1

BRANCH AROUND HOLE

ORG
FDB
BNE
LDA
JSR
INC
BRA
STX
LDA
ADD
ADD
RTS
STA
LDX
JSR
LDX
JSR
JSR
JSR
LDX
BRA

$A048
START
LOOP2
#$2B
OUTEEE
CTR
START
INXMSB
INXMSB
INXLSB
CTR

ADD IN ADDR LSB
ADD IN COUNTER

A
A
A
A

HITEMP
LOOP1
LOTEMP
INCRX
0,X
ERROR

STORE
#MCL
PDATA1
#CTR
OUT2HS
OUT2HS
OUT4HS
INXMSB
RETURN
41

PASS COUNTER
BIT MISMATCHED

INCREMENT INDEX

END OF MEMORY?

STORE ERRANT BIT
DO C/R L/F
COUNTER, IN HEX
ERRANT BITS, IN HEX
ADDRESS, IN HEX

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
Producer                        : Acrobat Distiller 4.05 for Windows
Creator                         : Microsoft Word 8.0
Modify Date                     : 2000:09:17 19:11:02-07:00
Author                          : Michael Holley
Title                           : SWTBUG 6800 ROM MONITOR
Create Date                     : 2000:09:17 19:09:59
Page Count                      : 41
Page Mode                       : UseNone

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SWTBUG 6800 ROM MONITOR SWTBUG_Users_Guide Users Guide

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