SY22 2842 3__40_FE_Diagram_Man_Jan70 3 40 FE Diagram Man Jan70
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Field Engineering
Diagram Manual
System/360 Model 40
2040 Processing Unit
SY22-2842-3
SY22-2842-3
FES: SY22-6827
PREFACE
This manual contains diagrams for use with System/360 Model 40 2040 Processing Unit, Field
Engineering Maintenance Manual, Order No. SY22-2841, and also with the following manuals:
System/360 Model 40 Comprehensive Introduction, Field Engineering Theory of Operation
Manual, Order No. SY22-2840.
System/360 Model 40 Functional Units, Field Engineering Manual of Instruction, Order No. SY22-2843.
System/360 Model 40 Theory of Operation, Field Engineering Theory of Operation Manual,
Order No. SY22-2844.
System/360 Model 40 Power Supplies, Features, and Appendix, Field Engineering Manual of
Instruction, Order No. S223-2845.
Power Supplies, SLT, SLD, ASLT, MST, Field Engineering Theory of Operation Manual, Order
No. SY22-2799. This manual may be used for maintenance or instruction purposes. It contains Data Flow
Charts, Simplified Logic Diagrams (SLD) , Condensed Logic Flow Charts (CLF), Malfunction Analysis
Procedures (MAP), and 1401/1460 Emulator Flow Charts.
The EC level of Control Automation System (CAS) Logic Diagrams referenced within this manual
is 255263. ALD references are at EC level 254814 for all diagrams except the 1401/1460 emulator
flow charts, which are at EC level 255264. The Mid-Pac power supply is at EC level 255055 and
the 2. 5 kHz HF Power Supply is at EC level 266316. Subsequent engineering changes may alter the contents of this manual.
Fifth Edition (January 1970)
This manual, Order Number SY22-2842-3, is a reprint of Y22-2842-2 incorporating
changes released in FE Supplement Y22-6809, November 28, 1969.
Changes are continually made to the specifications herein; any such changes will be
reported in subsequent revisions or FE Supplements.
This manual has been prepared by the IBM Systems Development Division, Product
Publications, Dept B96, PO Box 390, Poughkeepsie, N. Y. 12602. A form for
readers' comments is provided at the back of this publication. If the form has been
removed, comments may be sent to the above address.
© Copyright International Business Machines Corporation 1966, 1970
CONTENTS
Figure
Title
DATA FLOW CHARTS
011
Selector Channel Data Flow
012
CPU Data Flow
013
Microprogram Data Flow
014
CPU Microprogram Flow Chart
015
ROS Control Word
101
Multiplex and MS Unit Data and Control
SIMPLIFIED LOGIC DIAGRAMS (SLD)
501
LSAR Parity Generation
502
Clock Control (SP)
Main Storage Control and Timing Circuits (2 Sheets)
504
505
Function and Control Registers
506
Decimal Filler
507
Decimal Correction
508
Carry Latches
509
Selector Channel Controls (2 Sheets)
510
Mid-Pac Power Supply Wiring Diagram (2 Sheets)
510A
2040 Mid-Pac Wall Frame Wiring Diagram
511
2.5 kHz HF Power Supply Wiring Diagram
512
Multiplex Channel Controls
513
Main Storage X-Dimension Drive
CONDENSED LOGIC FLOW CHARTS (CLF)
599
How to Use Flow Charts
600
Instruction Matrix
601
Instruction Fetch Microprogram
602
2nd Level Instruction Fetch, RX Fixed Point
603
2nd Level Instruction Fetch, RX Floating-Point
604
2nd Level Instruction Fetch, RS and Sl Operations
605
2nd Level Instruction Fetcl)., SS Logical
606
2nd Level Instruction Fetch, SS Decimal
607
Machine Status at 1st and 2nd Level Function Branches
608
Branch and Link
609
Set and Insert Storage Key
610
Convert Decimal to Binary
611
RR Fixed Point Sign Operation
612
Branch on Count
613
Convert Binary to Decimal
614
Set Program Mask
615
RR and RX Fixed Point Arithmetic and Logic
616
RX Fixed Point Add and Subtract
617
RX Compare Algebraic
618
Branch on Condition
620
RR and RX Fixed Point Multiply
621
RR and RX Fixed Point Multiply, Notes
622
RR and RX Fixed Point Multiply, Detail of Loops
623
Fixed Point Divide Initialization
624
Fixed Point Divide Loop
625
RR Floating-Point Sign Operations
626
RR and RX Floating-Point Operation (2 Sheets)
627
Floating-Point Load and Store
628
Floating-Point Multiply/Divide Initialization (2 Sheets)
629
Floating-Point Multiply Loop
630
Floating-Point Divide Loop
631
Test Under Mask
632
Branch on Index
633
Set System Mask
634
RS Load and Store Multiple
635
Shifts
636
SIOperations, AND, OR, EXOR, MOVE
637
Read Direct and Write Direct
638
Load PSW (2 Sheets)
639
Diagnose Instruction
641
SS Translate
642
SS Translate and Test
643
Edit, Edit and Mark (2 Sheets)
644
SS Edit, Refill
647
SS Logical Operations, Move Zone and Numeric
648
SS Logical Operations, Move Complete
649
SS Logical Operations, Compare
650
SS Decimal Divide
651
Decimal Divide Example
652
Decimal Divide Add/Subtract Paths
653
SS Decimal Multiply
654
Decimal Pack
655
Decimal Unpack
656
Decimal Move with Offset
657
General Flow Chart for Decimal Add Sub Compare
658
SS Decimal Load and Process Operand 1
SS Decimal Load Zero and Add Entry
659
660
SS Decimal Load Operand 2 and Process
661
SS Decimal Terminate
662
SS Decimal Compare
665
Start I/O Instruction (Multiplex Channel)
666
I/O Codes, Common Decoding; Test Channel and
Mpx Halt I/O (2 Sheets)
667
Start I/O Microprogram Mpx Channel (2 Sheets)
668
Test I/O Multiplex Channel Microprogram
669
Multiplex Channel Microprogram (4 Sheets)
670
Multiplex Channel Status
671
I/O Interrupts and Update Timer Microprogram
674
Selector Channel Status
675
Selector Channel I/O Instructions Microprogram (4 Sheets)
686
Store PSW - General Flow
MALFUNCTION ANALYSIS PROCEDURES (MAP)
901
Interpret Errors (2 Sheets)
906
Control Check
Early Check
907
Late Check
908
Read Only Storage (3 Sheets)
911
Local Storage
912
Storage Protect
913
Main Storage (64K MAP)
914
Multiplex Channel
915
Selector Channel
916
Mid-Pac Power Supply
917
2.5 kc HF Power Supply
918
1401/1460 COMPATIBILITY FEATURE FLOW CHARTS
6200
1401 Instruction Fetch
1401 Instruction Fetch
6200A
1401 Instruction Fetch
6200B
1401 N Operation
6201
1401 Add and Subtract
6202
6202A
1401 Add and Subtract
1401 Compare
6203
1401 Compare
6203A
Store 1401 AAR or BAR
6204
Multiway Branch
6205
1401 Increment-Decrement
6206
Scatter--Gather
6207
Scatter--Gather
6207A
Scatter (OOS Compatibility Feature) (2 Sheets)
6207B
Gather (OOS Compatibility Feature)
6207C
6208
1401 Multiply and Divide
1401 Multiply and Divide
6208A
1401 Multiply and Divide
6208B
1401 Move, Load, Zero and Add, Zero and Subtract
6209
6209A
1401 Move, Load, Zero and Add, Zero and Subtract
6209B
1401 Move, Load, Zero and Add, Zero and Subtract
6210
1401 I/O M, L, U Operations
1401 Unit Record Operations
6211
6212
1401 Carriage Control and Stacker Select
1401 Address Modify
6213
6213A
1401 Address Modify
6214
1401 Set Word Mark, Clear Word Mark, Clear Storage,
and Special Clears
6215
1401 Move Characters and Suppress Zeros
6216
1401 1 and 2Byte Data Service
6217
Set Selector Channel to 1401 Mode
6218
1401 Tape Operations
6219
1401 Branch if: Word Mark or Zone, Bit Equal or
Character Equal
1401 Emulator Program Entry
6220
1401 Diagnose
6221
6222
1401 Branch Tests
6223
1401 Move and Binary Decode
6224
1401 Move and Binary Code
6225
1401 Read and Punch Column Binary
6226
1401 Index Factor Fetch
6227
1401 Index Add
1410/7010
6300
6301
6302
6303
6304
6305
6306
6307
6308
6309
6310
6311
6312
6313
6314
6315
6316
6317
6318
6319
6320
6321
6322
6323
6324
6325
6326
6327
6328
6329
6330
6331
6332
6333
6334
6335
6336
6337
6338
6339
6340
6341
6342
6343
6344
INDEX
X-I
X-2
X-3
COMPATIBILITY FEATURE FLOW CHARTS (CLF)
1410/7010 Operation Codes in EBCDIC-II
1410E Instruction Fetch-Overall
1410E Instruction Fetch Start
1410E X Control Field Readout
1410E Address Readout
1410E Instruction Fetch Ending
1410E NOP and Non-Interruptible Op Codes
1410E Chaining
1410E Indexing (Two Sheets)
1410E Branch on Channel Status
1410E Priority Test and Branch, Branch on Internal Indicator
1410E Branch if: Character, WM/Zone, or Bit Equal
1410E Store Address Register (Two Sheets)
7010E Store and Restore Status
1410E Set/Clear WM and Clear Storage
1410E Table Lookup
1410E Add, Subtract, Multiply, and Divide
1410E Add, Subtract-Initial Loop
1410E Add, Subtract-Main Loop
1410E Add, Subtract-Special Loop and Ending
1410E Multiply-First Scan
1410E Multiply Loop
1410E Divide Initial Loop
1410E Divide Loop and Ending
1410E Data Move, Zero Add/Subtract, and Compare
1410E Zero Add/Subtract-Initial Loop
1410E Zero Add/Subtract-Main and SpeCial Loops
1410E Data Move Minus Scan-Initial Loop
1410E Data Move Minus Scan, Zero Add/Subtract A Cycles
1410E Data Move Plus Scan-Initial Loop
1410E Data Move Plus Scan-Main Loop
1410E Compare-Initial Loop
1410E Compare-Main Loop
1410E Compare Character and Ending
1410E Unit Control, I/O Move/Load-Initial Loop
1410E X-control Field Translation
1410E I/O Unit Selection
1410E One-Byte Data Service
1410E Two-Byte Data Service
1410E Forms Control and Stacker Select
1410E Diagnose Instructions, I-Fetch Linkages
1410E Edit Diagnose
1410E Scatter/Gather Diagnose
1410E Gather Diagnose
1410E Disk Diagnose--End of Storage or GMWM Scan
Halds
Byte
Count
S Register
T Register
PC
PC
PO
SX
T1
TO
Channel
Key
SI
SO
7
7 PO
P4
-
7
Bus
Bus In
ALU Extention
Selector
Channel
Interface
ALU
Bus Out
ALU Compress
R Bus 2
and Extension
--
ROS Bus
6 Bits
N
CA Field from ROS
D~ll
tL2
Constant
Start Address
m
~
XOlll000XXXOO
~
...
...
0
1
1
12 11 10 9
Cond
1()
~
()
~
..,'"
8
7 6
()
~
()
~
o
-
"B'C
..,,,,
()()
~~
5 4 3
ROSCAR
2
1 0
-
~13 Bits and p~~"'",,",,~",,~~ ROSAB--~~~
I
FIGURE 011.
SELECTOR CHANNEL DATA FLOW
I/C OR STOR ADR DISPLAY
Byte
Byt. Byte 0 Byte I Byte I
X
Bits
Bits
Bits
Bit 7 0-7
0-6
X
Bit 7
I
5&6
r--
-
Prot
Store
4 Bits 128 Wds ~
..... 5 Bits
7 Storage Address Bits and Yl
Mpx
Stono
6 Bits
andYl
f
Select
!;.
'
Star
Any EX! I,p"
Mpx SCI SC2
I
Mpx
Manual AddreH
Entry Switches
MS Address Compare
6 Bits and VI
~
7
Interrupt Request Latch-J
o
I
1
r-
//////////I17~'~ Tr:t~Z
Logic
'/////
External Interrupts
~
T
12BWd.
I
I
Trans-
late
L1
l
i
Main storage.
PG
l
ic
Emit
Field
STAT/CIZER
Mpx Store
t
In
PSN
4-7
PSN
0-3
~
o
PSN 5-7
~
r -==.:~ f.} -%-
P..........AA~L'U~I.EPx.':lnU.'R••9......................................~......~===ALU~~P~~~~~~~~8y~te~=-"~~/'~+-"""""""""
PSNO-3.
t
PCPG
Data
PO-3
Ir;ESN4-
~
~
~
K.y
PC
PO-
Ister
__
'--_ _+_C:;:o;;:m=DO"~•.:B~U,I.._ _ _ _oIoI~"""~~
L..T"_ _
--
+-_...;......;....;..;;;:;.;;.'--_.....,I-_._~v_';'g_I~_.t1_~n
7 --
,----i E£ P -ed
I '---.!
~r2Ex";W"'t-+P...;0--ri-~-f:+~""~-~-~~"'~::-I- -i
I
I;::,',ry lpn.., pn _
I
7
AI
AO
AX
I
r-lu.-___yUI-.--
F61Mo!
t"
__
I
,-
I
I
I
I
I
~LU-
2
.----=---:-""'-_...,
II
Reg
C Register
CX
CO
1>5-7 Ipo -
I
~nar~
~PG _ut P/
'7ALtr.
I
I
~.:!jrollr,Dec,~al
I
n,
I
I
I
1-,--",D"::-:3ri;;'i"t.!...'----::::i
~ DO-~ Dl -
I
Cl
7
IPO -
-
f
Emit
Field
.RX~RO~
r
Error Entries
..
!!
r
,,,,,-"'!.: N ROS Bu. k""-""-""-""-""-""-""-""-""-""-""-""-""-""-""-""'-l
I
I
~.
-
_
a
lit
Read Only 5to,,"g.
,eid ROS Bit
-
PG
P1
ROBAR
P12
11
'1.
I
:
ROAR
_
0
ttl
f<:-..",-..-",,.,,-J
'~""-tJ.R05AB"""-""-""-""-""-""-""-""-""-""-"~-""
~
I
l
ROS Addre..
Compare
ManUal Data
Entry Switches
I
I
A
B
C
D
0 -3
4 -7
8- 11
:
12-13
H
21-25
J
ROS Next Address
B Condition Tests Special Controls
C Condition Tests
ROS Address Control
Locol Storage Address Control
26-2B
R-R.g;,t.rlnputConhol
29
32
33 - 36
Q
44-47
Skew Control Of ALU Q Entry
R-Register Output Control
ALU Output Control
StatAndFunctionReg.lnput-Ctrl.
AlU Input From P Bus
ALU Input From Q Bu,
R
S
48-50
51
Miscellaneous
Word Parity Bit
P
Jx
30 -
:5l-40
41 -43
l'-..""-""-""-""-""-""-""-""-""-""-""-""-""-""-""-""-""-""-""-""-""-""-'"
5254 53 JW.ld~~;on
~
--
~~ ~:~;ral
Function
1418 17 ~:~Fldl:,."Pa';'YB;'
G 19-20 ALU Funcl;an Control
K
L
M
N
-
Control
Decoder*
Latches
.,....---,
I
~~
~~
~
Ii'
B
C
~::o
I
t
--
"'""'!"""""
tt:!pq::j::lP';L;::t::j~
~
~
~
~ ~
-#- . . . .
1-+--.----i~Up ~
1-+--+----i+l::9: ~
~
t
.!R _:Reg.,.l7:
t·., •
Channel
Rl
-
P5-7
-
7
PO
-
7
PO
ontrol
~~~n:1
Are Checked Expect
LAnd M Indicators On
Internol CE Panel
PSNO-3
ROS Word
1
14- - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
- ''----'''Ch''''ec;;;.k_-''
FIGURE 012, CPU DATA FLOW
l
D;'.ct
Control
Pre~ent
I
I
/, Data
Mpx
PO -
I
LOCAL
STORAGE
144HALFWORDS
I
_
/
7
LEGEND
1 Bi t Data Path
Extension (PSN P5-7) Data Path
I
=
Reg Formot
~. ~s;~1IIIIj
~POG E'~" ~PG-7',
Incr
~
M Bu, I
RI
~N.4-7
~-
H
LSAR
PO-3 4-7
PO -
7
PO -
Half Byte Bus (4 Bits + Parity)
6 Bi t Address Bus
1 Byte Bus (8 Bits + Pority)
14 Bit Address Bus \13 Bits Plus Parity)
17 Bit Address Bus
2 Bytes Bus (16 Bits + 2 Parity Bits)
_
Data Flow
LP~X~~55~~P~FI~.~ld~ExN~~N~;on~__________~__~-----
L.J
~
I ~
I~-I PMA I I
I R~~_'*I=~*I=ll
II
" IMA
Wgit
II
-
22 BITS
* All Decoders
I_I D;sobl.1
:~OP5Nll-1
-2 ±j a
.i!
~~
t-~=:::t=~;;::=...L.=~---lJr-0g
Te,"
Conditions
ASCII I I
:=1-;:I==yc===I=:=1=:1
:
Adr
RO
~~;~c
RX
RO -.~c
''PC'
.~
I:
I
ROS Word
,6,ddress
~===t~·gI--':'-iJg=1~:I
1-1
I :::::::~~2~8y:t~~~::::::::::::::::::::::::::~II~I~IIIIIIII~~~~~~;;;;~~::::::~M~PX~Bu~,~~uut
X
~
,
r:===~~~~~dJ~c
~
H
c~~tr:~d
Logical
m
~ J-
r
C
I
j
IManual Control
~ Entry, Load Adr Entry,
Rl
l>~~~Q5Z~Q5Ji~;J~lJ~Z~Q2flIIData
2 Bytes Plus 3 Bits
I SelectEntry,
Entry Store
..1\.2 Bvtes P us 3 Bits
2~t~
~~""'~VY~'X~XS;>6("~xZ:;<,.~v:21)('Z7<.~,/V';2S;~'X~x~x.~V"X~X'ZY:~~lSI~RJB~u,J2l:!B~~t;e,!JP~'u;!'13!Ex!!:,'>(:sQQ~X~Q~~)(~')(2X~X~ZX6;~2lZ'2~~~'X~X~~ZX~SC362~~~?:2~~~Y~0Q11
~
i:
III
I
I
I
ALU Compress
I
II
II
yt.
Log-Out
,j.........._D.C_ln.'t.ru.ct.;o.n.'~)1
DC Out
rPO"--~-~7~~~PO~-~7~1~:=_;:I==Y=CD=;:I~1
7
I
(
To BO
II
I
~
ALU Output Bus
II
II
L: __
II
II
7
Bl
DC In
I[
i
_______
ALU Extn Output
r
BO
.."......1
L_ .-RO"-P,-"S",N,,,--6--,
Q-
~
7
7'-'--'Y7.L....L--'~ •
I
~
~l
h~7 ,LfWdJ
V
-
~
~B~~
I
D;,.ct-~
Control
Accept
Manual Adr
Entry Sw
LS,RBUS
2 Bytes + Ext Bus (19 Bits + 3 Pari!)' Bits~
Special Data Path For Dump log Out Or
Manual Display Operations
Crossing Buses
Bus Distribution
Parity Checker
Parity Generation
Indicator
r 1,
LTJ
¢
~
,
HARDWARE CYCLES
(T CLOCK STOPPED)
.---
jl.PROGRAM CYCLES (T CLOCK RUNNING)
STADB- .
CONSOLE SWITCHES
r /.
TERMI~'
~-
V·
SELECTOR CHANNEL BREAK IN. THEY CAN
r~OCCUR WHENEVER MAIN STORAGE FREE
//DUMPS CAUSED BY )J-PROGR INTERRUPTS
THESE CAN OCCUR BETWEEN ANY TWO
~"
MICRO INSTRUCTION PROVIDING THE INHIBIT
'DUMP(YB)STAT IS OFF E, MAIN STORAGE IS FREE
L/
----.
t
UPDATE
PSW INTO
LOCAL STORE
+
.-----'
~
~
PRI
~
I
~
FETCH
NEXT
CCW
+
~
i
ACCEPT
STATUS
;::.;.;:::-.........._ _.;..._ _ _.j.i.iW;.;;"AIT OR I FETCH
+
STORE PSW
FROM LSTOR
INTO MS
~
1
I FETCH
DISPLAY
ROUTINE
(STORE)
j
LOAD PSW
FROM MS
INTO L STOR
SUPERVISOR CALL INSTR.
t
EXECUTION
t
STATUS
AFTER
~~jEST
t
/
t
LOOP ON M.S.
(GENERATES PRJ SETS
HALT LATCH IF A REG
=ADDR.SW)
/
+
COM. CHAIN.
DEY. END
.J----
FETCH
CCW
.~
4
RE
SELECT
•
1
DATA
CHAINING
.~.
----::::..-
i
POWER
ON
(HALT)
LOOP
ON
ROS
HARDWARE
SYSTEM
RESET
~
1
IPL
ROUTINE
)J-PROGRAM
SYSTEM
RESET
CPUE, CHN.
CHECKOUT
/"- PROGRAM
LOG-OUT
FIGURE 013. MICROPROGRAM DATA FLOW
1
~
IPL END
HALT
Instruction
Fetch Start
223-2844
"Current" PSW is modified to indicate latest status (condition codes etc.) and is stored in main storage.
Main storage location is determined b the t e of intelTu t. The stored PSW is now the "old" PSW
To Load FiBt Customer PSW from MS Location 00000
{
V6 Set by
Start Key
Causes
Ignoring PRJ
223-2842
Fig 638
A "new l l PSW is transferred from main storage to local storage. Main storage location is determined by the type of interrupt.
Th is "new" PSW is now the "current' r PSW
{
Ves
No
Instruction
Fetch
223-2842
l'Igs 601 - 606
Ves
To PRI Scan
Microprogram
To Instruction
Fetch
To Program
Check
Microprogram
Manual Stop microinstruction
"Manual" light glowing on console
Exit only under console switch control
To Program Check Interrupt
Microprogram
223-2841
To Supervisor Call Interrupt
Flow Cha.... lor {
,?p Codes in
Microprogram
223-2842
Ves
No
To Program Check Interrupt
(To other built - in
diagnostic microprograms
selected by diagnostic
control switch)
Microprogram
These decisions are effective a
any time during the execution
of the instruction.
No
Stop or LOOP~
V
Hardware Controlled System Reset
J..
No
SAB=Addr
~----='--""'Keys During
Error Routine
Ref.r to
Mach ine Status
Charts
r---"=.
{
CPU and Ch~nnel Checkout Microprogram
Oiardstop on any Error)
.
M,S Write
.'V'
Microprogram Controlled System Reset
CD main storage validated
if Y15 on
® if log out, only channels in error
are reset
223-2841
Exit Conditions from System Reset. Take One Leg Only
Microprogram Controlled Log Out
of Local Storage and Data Flow into
lVoin Siorage - Set Y7 to Indicate
Log Out - Set Y4, Y5 and Y6
De endent on Channel errors
C_O~ t_~_t_c.~ ~_~~_m_l_n_N_~_p_t_(P_R_)
~Hb~lt_la~t~ch~~~~~~~
a.
CD Channel interrupt if masked to allow
b.
_N_m.
__
__nonzero
__(cancelled
__ __ by disable interval
___________________
QD_3
__ d.
®l_.__4 bit__lt_lorg
timer
timer switch)
L
f.
l_in_t_e~_u_p_b_m_~~
223-2842- Model 40 Diagrams Manual
223-2844- Model 40 Theory of Operations
223-2841- Model 40 Maintenance Manual
Hardstop on Control
Check Errors onl
Stop key
o.
Console attention (interrupt pushbutton on console depressed)
Instruction step mode
b.
Interval timer in main storage has timed out
Stop on MS ) • dd
.
h
External interrupts
3 to_a_I_IOW
through
7
QD_4___
Ex_te_ma
__
____
____________________
-J
loop on MS
via a __________________
ress compare SWltc
System reset pushbutton
Power on Pushbutton
FIGURE 014. CPU MICROPROGRAM flOW CHART (CHANNEL DATA SERVICE NOT SHOWN)
Interrupt Routine
1
223-2844
10
CA FielD
11
12
o
I
1
I
Port of next
lOS oddreu,
dependent on
CB & CD fields
y~
I
I
o
Function
o
I/O
rC"'S""'f;-.,-d...L'u-nc-';-on"""'
contents
o
o
I
I
I
2
3
VCO
5
VCD
L2,0
ALUfO
VO
6
V2
7
8
V4
9
10
11
12
13
14
15
IZT
IDQ
ASCII
Minus
'NO
CE FielD
I
4
ADR-I
ALUfO
5
6
7
Halt
8
V6
Lood
ALU7
9
10
11
12
13
14
15
17
18
CF
19
V.
22
21
20
Works with CB
CC field
contents
Function
field to determine
the next
ROS odeIress
and CD "" 1 013
o
I
I
When CD,.- 1 or3,
the CB field does
not control bit I.
It brings up
special control
lines as
shown below:
2
3
4
5
VCO
L4f
ALUfO
VI
6
7
8
~~-~C
'NS
0
CC field
contents
o
I
CH field
contents
I
2
3
4
5
I
0
I
2
YCD
3
•
5
"
ALUfO
DUll'
Y3
6
MSC
V5
V7
7
8
9
V5
V7
HLOfl
10
11
CDA
STA-I
9
10
AlU6
AllJO
11
QIljoIO
12
13
14
PIli
VCI
SAT
15
Q.TV
12
13
14
IS
BU
AND.
MINSPLUS+
o
I
2
3
CMD-O
I
SVC-O
Sel
ISO
1-+IR
O-+IR
2
3
4
5
6
6
7
33
34
35
36
37
38
,
H+l :L+H
AE+L Il.J
AE+LIL+J
BE+lIL+J
QE+L!L+J
J+l IL.....J
BE+L :~NT
16
17
18
H.a.
22
23
2'
25
Data source
for ALU Par Q
inputs as
controll.d by
CP or CQ fields
26
27
28
29
30
31
Z
I
lSTOR
2
S
6
VSQ
HJ
A
S
C
0
7
8
YD:1
YDO
9
VE:l
I
R bus input
control
CM field
contents
ALU
Yeo
o
Z
AX
I
2
3
4
5
6
I
7
AE+l:L+H
BE+l ,L+H
QE+l.ll+H
J-+I. IL-2+.J
V••
8
9
10
11
12
13
Manual
state-stot
VIO
14
15
No
gated to
AD
Al
DATA
80
SI
S'
CX
CO
CI
V
00
01
CM field
contenti
Function
o
O.
•
5
W,
0101
AND
Tl
0110
OS.
SUP
.NQ
CfL
6
7
8
9
CS'
10
11
12
13
SO
SX
14
15
SI
Y
I
Function function
register
0000
0001
0010
0011
0100
I
2
3
""to.
CP field
contenh
XO'
lOll
1100
QN'
OSH
LSH
DAD
1101
1110
1111
CO
CI
6
DO
7
8
9
01
EO
OE
V
DATA
CHI
EXI
SP
No
Goted
to P
CP field
contents
o
Q
1010
CX
4
Yeo
•
1000
1001
3
channel
DSQ
SUQ
0111
Z
15
Indirect
function
as set by
CE field
o
Gated
to P
Z
AX
I
2
SO
2
AD
3
•
5
Al
80
SI
6
7
EO
OE
I
3
SI
•
5
TO
Tl
6
CSB
7
WIl
CL-CH
,0.-0
7
HIO
8
9
10
11
12
13
'NS
15
ICC
REINT
Dump
14
• FIGURE 015. ROS CONTROL WORD
STAN
No
DC-IN
1.00
SSM
ADD
SWEA
STPCI
Monuol
O..... SlO
Edit
SMSC
OAT
SU'-O
UndlM'lP
'NO
CJ field
contenll
o
I
2
3
•
5
6
7
Gated
to'
fCJ
field
contenll
V••
Reinterpret
I
>-'=---~I
to'
CJ field
contents
o
Z
o
A
I
B
CIT
I
2
3
4
LSTOR
5
6
HJ
LSTOR
2
3
4
5
7
CIS
SAS
LAS
SDS
Note 1: Set Relocate Latches
G' 10 Byte 0
Gated
C
o
6
7
Gated
to'
CST
5
T
WIll
W2
W3.
Bih
Hex Base
o
o
o
I
I
I
I
0 I
I 0
I
0
0
I
I
I
0
I
0
I
Relocate latch (on)
1401 Bose
3 2 I
I 2 3
04000
08000
OCOOO
10000
14000
X - X
18000
X X -
ICOOO
X X X
-
- X
16k
-
X X X
32k
481<
X -
-
CT FIELD
55
EXTENSION
64k
10k
96k
112k
I
Pority of this ROS
word. Odd parity
is mointoined by a
o or 1 in this
position
Gated
to Q bu
5
12
13
14
52
CS
I
SO
SI
11
YCHO
YCH:l
Note 1
54
53
51
2
I
2
10
10
ALU output control
~L+I+H
1
o
VAn
..... YB
YB;!
Reinterpret
,
AE+LIL+I+J
8E+L :L.,.I+J
QE+LIL+I+J
J+L :l+I+J
JE+L ,l.....J
JE+LI
AE+ll
CO field
contents
-+YA
YA:1
11
12
13
14
15
50
49
CR FIELD
ALU input control
to Q bus
ALU input control
to P bus
Function
3
•
5
6
7
NO''----_,
CB field
contents
28
CJ FiElD
Local storage address
control, affects lSAR, J
Reg, K Reg, use CE field
to M!t addresW!s. Ule CJ
or CL field to
control reod or write
o
Function
27
I
CF field - is the
parity bit of the
current ROS
control wordmust match the
parity of the
ROAR address
Darn murce for
loco I store address
formation as
controlled by
the CH field
Bit I is set to
24
CH FIELD
CG FIELD
CPU
o if CB = 0-13
23
2
Emit field
I
V6
FXP TO
ALU7
16
~~I/O_
Q
10.3
2
3
4
IS
I
Controls bit
o of next
ROS address
Controh bit
I of next
ROS address
CPU
CB field
contents
14
CD FIELD
CC FielD
CB FIELD
13
Mise control
CR field
contents
o
1
2
3
4
5
6
7
Op
NoOp
Read
Write
TRAP
lOS
CPU
0 SK
ADCMP
I
ExtE:nds fields
Corry control
Op
CT field
contents
NoOp
M
o
I
J and P
I
LSAR Load LA Bits 0-3
E Field Parity
----'---fNI-...._----------------L_--1
RL401
Q Bits 0-3 Odd
LSAR Load LQ Bits 0-3 Plus Pty
LSAR Load LB Bits 0-3
Se leet SC 2 Early Thru Sw
I/O State Early
Register H Bit Pty
LSAR Load H Bits 0-3 PIus Pty
LSAR
Parity
Bit
LSAR Load J Bits 4-7
OR
FL
Register J Bit Pty
Reset
LSAR
LSAR Load LJ Bits 4-7
Register J Bit 6
Register J Bit 7
RL40l
E Field Bit 2 Powered
E Field Bit 3 Powered
Log Mem Call Reset Trap
Set LSAR From Data Sw
Addr Sw Rl Bit Parity
FIGURE 501. LSAR PARITY GENERATION
RL401
LSAR Odd Pty
_l_o..::g_O_ut_S_w_i_tc_h_ _ _~,...--,...-MSS 1 Early
A
~St~op~H~a~lf~C~lo~c~k~l~_~~
PI Del
A
~T~3~0~r~T~3~D~e~I~~~~~~
Repeating on ROS latch
A
~I~~k
Repeat ROS (Console)
latch
Stop Clock latch
h _ _~~ OR~-----------~~F7l-'---------'~~~~~~
_N~ot~l~~~l_l~a_tc_
P3 Del
A
Dump Stop
,--_ _-/......-Undump Stop T Clock
System Reset Stop T Clock
OR
Not Power Good
P3
Not Hardstop
_P~3~0~r~P~3~D~e~I_____~~
Manual Set ROS Addr
Not MSS 2
Hardstop
A
R-
1 A
~' - - - - '
Inhibit B Gate Clock
OR
Trap latch
Hardstop
Not T3 Dell
Not T4
1
Stop Half
Clock 1
L--
SlO or ICC
- 1
11---'------.:....
~
______
Cycle with T Clock Stop
'----'
Push Switch latch
and not MSS 2
~l~o..::g~l-la-t-ch----~1
1
Hardstop
~~E_rr_or_w_il_I_St_o~P_C_I_OC_k
A
I--'-~
OR I,
A
~P4~or~P4~D~e~1__~~~r---l~
Error will Stop Clock
-4_~~~
Inhibit
on Error
OR~--_t--~F~l~---~I~n~hi~b~it~o~n~E~r~ro~r
T4
---~--------.--------~~-------~
PI Del
Not B; 4
T1 Del
_N~0~t~Re7pe~a~to-n-RO~S-l-a-tc-h-r_,r--r-
Gate Hardstop
A
P3
ROS Address Compare
Gate Stop on ROS Compare
Stop ROS or Stop ROS and MS
Set ROS Inh ibit
Not Dump Cycle
Start T lS Write
Not D; 3
...;B~;---.:,,14______-l1
A OR!,B
~-
~
D- 3
I
_
Inhibit ROS (Inhibits
setting of ROS output
Sense latches)
Not
lswEA
OR
A
A
Set ROS Inh ibi t
Hardstop
OR
r-----ir~Fl,-}-~~~~
Stop Half Clock 2
_
Hardstop
Allows
Display
L- ~~1-----------~----~~
L . - - - - - - - - - - - - - - - -.....-~---l-A--'
A
~
Hardstop Allows Display
'---
Not Start log latch
Microprogram log
Microprogram Stop
I
log Out Switch
MSS 1
Not Error Stat Y12
P2
Start
Set Repeat ROS Address
Fl
A
L~
......---.
_E"'r_ro:..;,r--;S:-'-ta"-t--:Y'-:1;..:;2;--_ _ _-l1 OR
load Stat Y15
I Error Stop
I~
L ~
Hardstop
Allows Display
Start
~h
ORr---------------------------------~
Start log latch
Fl ~------~~---
_M_ic_r_op~r_'og~r_a~m~l~o~g_ _ _~r--r--
Not Hardstop
A
_p_4_D_e:...I______________----l1 A OR
System Reset B at P2 Del
L--
Repeat
ROS Addr
~----+-~ N~--~------~~~~----~
Repeating on ROS latch
Repeat ROS
P4
~_-I
TcOal
Start Switch
Stop Half Clock 2
A
Set Repeat ROS Address
---I'l
..:.M:;.:S=.S..:..l_ _ _
Stop Half Clock 2
Repeating
on ROS
A
Fl
P2
System Reset B at P2 Del
RY121
KC071
A
FIGURE 502. CLOCK CONTROL (KC071-KC081)
A
_ _ _ _ _....J
~~~~~~~---/
KC071
A
~
A
P2
~~
CPU Check Status
Stop on Error
Display ROAR-ROSCAR
OR
~M7a~n~u~a~1~Se~t~R~O~A~R~_ _ _~OR~--------rT-C~I~o-ck~~S~ta~rt-T~C~1o~c~k_ _ _ _ _ _ _ __4
Repeating on ROS latch
P2 or P2 Del
KcOai"
System Reset Bat P2 Del
r__
-:N:"o~t_'R:.:e:=-pe~a~t~R:..:O:::S~:___:____I,...--
N 1------------1
Repeating on ROS latch
......---.
Repeat ROS
'---1
Gate Hardstop
-.".-..:.-,---,,---,,......,--,-,-----------1I OR 1-----____:....Single Cycle Mode
,
log Out Start T Clock
Dump Cycle Start T l S Write
Trap Start T
Undump Start T
System Reset
0---
~----+--l-L.:.J
_
Single Cycle Mode
l OR
Not Repeat ROS (Console) I
lJ.-_--l
I
'----'
A
Fl
Repeating on
ROS latch
10
x R/W Term Gate Tmg
~
Ank-,
XR,ad
Term Gote
X Read
A
X Write
!
LrI
~
~
XWdt.
Term Gate
I
Y R/W Term
Gate Tmg
K
Y Read
LrI
~
~
Y Road
Term Gate
rh
I
Y
~
.
~
Lr
wri~
YWdt.
Term Gate
I
$
130
Diodes
IplOll 213141S16171pI0111213141s 6 7
OR•• ;n2040
l'7j 1611S 14113 112111 110 I9 Is 17 I6 IS 14 13 12 I' 0
Data 8u.
11
Z Drivers
SegA Z Tmg
~
Z Bit 00 Seg~:~
Sense Bit 00 Seg ::::::~
AR ~t---------~------~-------------------------iAR
256 X
~~_~
I - AR =~Sog 8
line,
~
AR -
\--
Oata-In
powering
-G--
AR
t-- OR
rSog:TO
L-.!
Sog C
r_
AR
f---~I--_+r---=-' ------------........,f-'>---------------------i---jl-,
r.-
AR -
Z Bit 00 Seg D
Data Bit
Nat 00
Final Amp
AR
'----
~
LIM
'-----
AR
MC 021
Gate Decade Output
~t--
x R/W StatUi
X Gate Decade
~O__________________--;~~-X~G~at~'~O~.~~o~OO~
1....-1:...-------------------.,
Gat.
1 of 16 Active
Gote Decode
r---
X Gate Decode 15
C
--
MBo7I
0 XROO
G
Y Gate Decode
Selection
1"":f---l-1-------------tr-:-l
14Nat IS
'--------------t-t
IS
Road
~~---'''------I
llll
-=~
rOXWOO
To X Ovn
t-- G 1--''-=-=----'
-8.
r-jW:'l
IS
~I----"-----\
14
4
5
2
-
t--
X Read
o
7XROO
G
H
)( R,fN TOIl
~
1..-..:.9________________- - ; Oecode
10
Y Gat. Decode 15
--
0
YR
00
G
F
1~1~1--~~----------iL-~
:~
Road
1.1.1.1.
IS
~-----------------+~~
YR
1..-~!O:"':-'~"-4--------+--_+_{J A J~-'St"'.abo=-"8Y"'tt.'-'0"-_I~
1-:J_.
G
__ --C;I-":O-,-YW
__.:::OO,-~____-,
00
--
SagA
Nat 6
Not 14
G
Bump Decode
Selection
Gate Decode 0
Bit 13
~:
~
It-____-'G'''a'''to:..:O,,.:::cad=• ..:....1
1..-.:.Not:=.:..;8::;lb::..;:IS'-___________I Decade
M8291
SAB
15
13
o
0
1
0
1
2
3
1
1
0
1
0
__ ~1-----'R"".a"'d-"8"'um=pI0-/
I
I r = - - - H - -1
l
Not 14
6
=L.J
.---.
Not 6
]
Ir-""'--"---H---l
I
14
=LJ
S•• 8
Y Read
o
Road
M Bump Ovr Trng
MB 291
See C
~.:.:14'-----------_I_-il
-
6
A
I Sog 0
=LJ
P0=--t
__ (;-I_--W
,,-'' ' '=-'::.:8u::;:mr..
o
YWrite
~ot 14
I
SAB
14
6
0
0
A
BOO
15
0
1
~t
-~
6
Ir'~-----------I--__t__i
COlO
DOlI
lt~
~
.>-____l-____________________________
Sheet
__________________________
~L_
14
A
TIMING CIRCUITS (SHEET 2 OF 2)
I
Strobe Bvte 0
f-L-J
Z Sense Segment
Selection
A
Strobe Byte 1
I
SogO
Ir-"14'---------------t--IJ
_________________________________________________________________________L______________
~7::_--------
______________________________--'
Strobe Timing
MA 041
Addressing
FIGIaE SCM. MAIN STORAGE CONTIOt. _
Strobe Byte 1
II-=:'==-":""-\
A~
I-"St"',ob"'"• ..,8"'t.'!....!!.0-\
L...L.J
j---------------------L__..J
Inhibit
1
a
Sog 8
Seg C
J
MB 371
~Add::~:.:.0:.:c:ad:.~8~;b~
A
~"-~4:------------i:---t---r--11
Write Bump 1
Write
Strobe By!e
Strobe Byte 1
Not 6
o
s::,r~
Strobe Byte 1
I~~----_+--T~-IA~==~~
Read Bump 1
c
I
~6"'Na-:t.."-;-4--------+---+r-rA-,,
J
I
O>,-Yc.W~'~1t~·---------{~O~j---------------------1-~-t~O=--Y~W~I~S---i
~
o
A
f-C-J
Write
Write
Strobe A Tmg
Strobe
15
____
7 XWOO
Strobe B Tmg
E
o
L)-Y~R~/w~T~~~ ~r-
X Driver
~
r--8~X~W~'~ite~--_+~--_r
16 Gate
>--- Inputs
~~s------------------'Gm'
R.ad
07
o
Y Gate Decod. 00
Y
C )-_Yc.Ro=ad=--____--,
15
S
A
Out~t
Y ~t!LStatu,
Driver Output
So""
14
6
A
0
0
8'
SA8
0
1
C
1
0
o
1
I
Strobe-Segement
Selection
-
CE
CK
~
0
P
Fun ction
Reg ister
I
0
I
0-3
4
I
.I I
,
,
~
,
P
To Skew
Control
r~
E Field 0- 3
Note 1
F
Register
0-3
Note 3
K Field
Bit 0
{
~
To Decoders For
AlU Control
A
A
OR
{ sel: Emit
{ F Re
4
Control
Register
0-3
To Function
Check Ckts
lood Reg
1
.
i
I
P
CG
~
123
CN=15
i
-
ROS Field
0-3
A
Note 2
Sel
F
KPOOI
Control Register
Set By CN = 15 At T4 Del
Reset By Relooding G
Control latches Reset At T4 Del Special
If Not Inhibit ALU Control
CG Field
Bits
0
Note 1
Set Direct
If CG = 0 (& Y8 =1)
Or CG = 1 - 3
P Or Q
0
P And Q
0
Boolean Expression
P Minus Q
Position 0
P Plus Q
Gland GO}
~
~~
3
Gl or GO
See Chart Opposite
Note 2
Select F Register
If CG = 0 (and Y8=0)
And CN 'f 15
Note 3
Select Emit
If CG = 0 (ond Y8=0)
AndCN=15
To Change Function Register & Use In Same Cycle,
Both Control And Function Resisters Set By Emit Field At T4 Delay.
Function Register Not Gated To Control Register Until After T4 Delay
During Normal Operation.
Calling Select Emit Avoids Waiting For Function Register To Be Set
And Then Setting The Control Register.
FIGURE 505. FUNCTION & CONTROL REGISTERS
0
0
Control Bits
0
0
0
5
0
3
0
15
1
0
2
3
0
0
0
0
CPU Logic
+J
2nd Level
J
A
A
Not PO
+ P1
r--
OR
PI
A
J
r-.
+ P2
-P~
+P~
...
- J
- PI
~
- P2
.....
OR
A
Not PO
r.-- A
+ PO
P2
OR
PO
J
Not PI
Not P2
'r-.
OR
f--A
OR
f.....-
Not J
AVOOI
r--
OR
AlU Input P Bit 0
A
r-A
PO
AVOOI
J
+J
A
Not P I
OR
Not P2
- P2
OR
PI
OR
J
P2
Not J
+ PI
A
-
OR
AlU Input P Bit I
A
A
- J
A
PI
+ P2
AVOOI
AVOOI
- J
- P2
+J
+P2
fBI
J
NotP2
+ P2
Not J
-
OR
A
P2
AVO 11
AVOOI
Note:
Boolean Expression
Decimal Add Operation
Normal
Operation
Bi t Position 0
Bi t Position 1
J PI P2 orJPI P2
or JPI
Bit Position 2 (Inversion)
JP2
or JP2
FIGURE 506. DECIMAL FILLER
A
Bit Position 3 Unchanged
Bits 4-7 Not Shown As
Logic Is Some As For
Bits 0-3
ALU Input P Bit 2
Binary Output Bit 0
A
Binary Output Bit 1
A
OR
Binary Output Bit 2
-
Binary Output Bit 0
Bino
Out ut Bit 6
ALU Out ut Bit
ut Bit 4
A
ALU Qutout Bit 0
A
Not MSD Correct
-
Not Binary Output Bit 0
A
AV212
Binary Output Bit 1
Not Binary Output. Bit 2
Binary Output Bit 3
MSD Correction
AV202
A
R
A
Not Bina
0
Out ut Bit 6
Not BinaIY. Outp-ut Bit 2
MSD Correction
Biner
A
A
Out ut Bit 2
Not Bina
Binor Out ut Bit 6
Out ut Bit
ALU Out ut Bit
LSD Correction
Not MSD Correct
tic
A
A
Binor Out ut Bit 1
Bi a
AV202
AV212
A
LSD Corre tion
Not Bi na
A
Out ut Bit 6
AV212
AV202
A
0
0
Binar Out ut Bit 2
Not Bina
Out ut Bit
MSD Correction
Not Bina
MSD
Out ut Bit 0
A
orrection
Not Bina
Out ut Bit 2
AV212
A
Not Binary Output Bit
Not Bino
a
Out ut Bit 2
AV202
A
AL~ '-ontrol H
A
OR
~D
Not ALU Carry Bit 0
Not ALU Car
Bit
Bit
Bit
Bit
FIGURE 507
0
1
2
3
0.1.2 + 0.1.2.3
1.2 + 1.2
Invert
No Change {Not 'Shown}
DECIMAL CORRECTION
LSD Correction
Bit 4
AV212
AV202
Baalean Expression MSD
R
Boolean Expression LSD
Bit
Bit
Bit
Bit
4
5
6
7
4.5.6
5.6 + 5.6
Invert
No Change {Not Shown}
Not ALU Control S
Not ALU Carry Bit 0
Not ALU Control V
YCD
Latch
Carry Condition
Not Indirect Function
Carry Stat YCD
FL
T3
ALU Control V
Not Indirect Function
AM321
AM321
T2 Del
System Reset
No YCD
Latch Carry Stat No YCD
A OR ~----- Fl
System Reset
Channe I Carry No YCD
Not Indirect Function
11 or T1 Del
Not T Field Bit 0
Not Indirect Function
A
No YC
Latch
Not T Field Bit 1
T2 Del
T Field Bit 0
T1 or T1 Del
Not T Field Bit 0
T1 or T1 Del
Indirect Function
T3
~N~ot~C-ar-r-y~C~o-n~d~it~io-n--; A
OR
No YCI
Latch
Indirect Function
A
OR
Carry Stat No YC
Fl
T1
A
AM311
Carry Stat No YCI
FL
System Reset
AM321
Indirect Function
T2 Del
Carry Condition
YCI
Latch
Indirect Function
Carry Stat YCI
FL
T3
Indirect Function
T1 or T1 Del
T Field Bit 0
T Field Bit 1
Not Indirect Function
Indirect Function
AM321
T2 Del
System Reset
A
YC
Latch
A
A
OR
FL
T1
AM311
T1 or T1 Del
Not T Field Bit 0
Not Select Channel Early
'---_ _~----, Channe I
Carry YCD
Not Carry Stat No YCD
Select Channel Early
Not CPU Carry Stat No YCD
AM331
r-- - - - - - - - - - -- - - - - ALU Ctrl
l
V
Not ALU Ctrl V
ALU Ctrl S
Not Carry Stat No YC
OR
A
Carry Into Bit 7
ALU Ctrl W
Not ALU Ctrl S
Not Carry Stat YC
Skew Select Bit 6
Not ALU Ctel W
L
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~m
_ _ .-...JI
FIGURE 508. CARRY LATCHES
Carry Stat YC
ROSCAR Interlock
-
-
Write
T=O
Buffers Empty
Not CDA Cand
TID
B-1
A
-
Channel End
~
Read
A
0=1
T4
OR
OR
-
J
GG521
OR
......
OR
ram SVO
A
Terminal Status
C
(CE)
Sheet I
GG531
In Tog
Latch
FL
0-
GG531
GC531
Address into ROSCAR
0
(Status in alter AD1)
Sheet I
(DE)
ADll B=3
0=0
FL
t"'--
Not ADI
Nat STI
Nt SV
Set Command
Out Latch
A
A
Microprogram SVO
A
T4
STI Tag
OPI
A
T3
['GGm
A
i·
Not Micr r
Not CMO
FL
Clear Channel
Inhibit SLO
FL
'--'-Not Data C2i>.. Latch
C
Address Out
Interface
FL
A _
r---- _
""'W
Service In
Not Service Out
Not ISO
T3
ADI
ADI TO ROSCAR
Command
Out
Sheet 1
Start
Latch
T4
STl Tag
Status In
A
T3D
C=l1 STI
FL
.-
I GGs23
Sheet I
Sel Chan Late
far Logout
ADI to
ROSCAR
ADI To
T4
GB506
ADI
STl
Clear Channel
FL
Not In T
Nat SVI
T4D
A
GG531
GG531
Microprogram CMO
wI
Select
Unit
A
B=3
OR
FL
o
ISO
I
I
-r:r
--.J
0=1
B=4
GGsi2
Nat OP-I
OR
'"_.,
;.-
J
~~
r~
GG511
A
".u~- to ROS~
O"SLO
SEL-O to Interface
FL
T3 Delayed
N
ADR-O
Clear Channel
,..--
-
J
System Reset
0=1
Reset
S~ut
l~
r-
~A lOR
1-A
I
~.~ ~"
. '"
TI Delayed
'GG5i1
rr -
GG512
Unit
Unobtainable
l
Address Out Latch
FL
IA
N
OR
r-
A
L~~
1
.-Select Unit Latch
Not OP-I
Not SE .-C
Not SEL-I
GGsi2
J;L
R..et WO
A
FL
WO Hold
T3
14 Delayed
A
-
Not SVI Tag
~
J
T3 Delayed
Not Data Service Out
Fl
-
A
I
A
OR
l
Hold Out
Gate 2
l
Hold Out
Gate 3
T3 DellA
FL
Interface Free
-'--
Reset WO
.-U.
] A
FL
-
A
GG524
OR
GG524
N
N ot Clear Channel
Hold Out
Gate I
FL
A
(0=1, B=O)
Address Out Latch
Clear Chonnel
Write
Dota Service Out Latch
A
TI
-,.--
Nat An....l'.. Chan ErrOl"$
REO -I
Not Inhibit ADO
T4DelaJfed
-
OR I - -
A
r----'--
T1
A
A
r--
~I-----<
OR
Bus Select In
r--r--
J1.De ~ed
Halt Latch
T4
Address Out Latch
Nat OP-I
Del5!)'Od Select Out
FL
TI
'--
l
~dOut
lA
t 4
FL
A
Dota
Operation
ATe Status.
SVC-O Latch
A
'--GG511
Fl
Clear Channe I
OR
Reset Buffer
T3
GG523
A
. . '" '" '"m
SCI Late far
~t
J
Transition
,.---,
Not Dump Cycle latch
PI Del~ed
J
EOR
A
N
~~
FL
l
Not Chan Select Late
r-rT2
DumE. Cycle Latch
A
L t-
OR
l-J
A
GD505
T2 Delayed
---r;:-r-
Channel Reset ROAR
SCI Select Late
T2De!ayed
Not ROSCAR Interlock
T1 Delayed
FIGURE 509.
SELECTOR CHANNEL CONTROLS (SHEET 2 OF 2)
OR
A
1
r-,
FL
ROAR to ROSAB
r-
-
''--'--
G
r-r- rl-
Condition
N
ROAR
Transition
SCI ROSCAR to ROSAB
'"Gi;So4
ROSCARI
Transition
A
Fl
OR
-A
OR
GD504
FL
P2Del"led
GD504
t----<
A
<--Set B Condition Latch
Set ROAR Bit I
OR t---'
ROAR Manual Set Bit I
Early B Condition frc:m Channels
-
A
t"-
J
OR
A
t-
.JA
ROSAB Bit I
r
Fan.
,-----------------,
Storage
TROS
l
LOG I C
VOLTAGES
CB 2
. -_ _ _ _ _ _ _ _ _ _ _ _.... +TBI }
Gate A {
Gate B
- TB I
(.i')--I-----j
CB 3
MID-PAC POWER SUPPLY
8EFORE (EC255055)
C84
Main Storage
Remote
Sense
T86
Fans
STORAGE AND 1052
VOL TAGES
T2
-3v
30 Amp
I Amp 1052
Rear PS
PS 5
48v
TB9
. -_______________________ +LBTB }Gat•
. -_ _ _ _ _ _ _ _ _ _,....-LBT8 R!ot.
T812
I
Sense
Fan.
Front PS
TB4
TBI6
__________.~-,-L-~~--~
20IN
I
I
I
--2-.
3\21
60Hz
KI
CB I
:1-_________________________ -L8T8
,1-_________________________ +LBTB
K2
}
;'110;Teh
vOC
Wall
Frome
-
Wain Storage
~:~s:te
XV Select
1 Amp
+3v
45 Amp
~----------------------- +TB I } TROS
Jill
{~~
}Got. A
~--------------------_ -T8 1
Remote
Sense
4 } -6/-9v Local Storage
1-__.....__________-=-1
C8 6
3
6 Amp Z Inhibit
T812
-----1
L3
F2
I
L __________________
J29
1052
Pwr Sup
Roll ...
Sw light
CE Panel
Clock
J
K9
K2
:cr:Tw~'!c-J1
~J28
l
H
EPO
Step
EPO
Logic
I/O
Voltages
etrl
FIGURE 510. MID-PAC POWER SUPPLY WIRING DIAGRAM (SHEET I OF 2)
I/OC,rI
Vo EPO
Th
Mach
Stort
Reset
Pwr
etr!
Mach
Start
Memory
Voltages
Nemory
Voltage
Delay
Stock
Pwr
Good
CB
Pwr
Goad
Tdp
Gate A
O/L
Lamp
Th
K3
Gate B
Th
K4
TROS
Th
K5
Th
Th
Pwr
Main
Storage
K6
Sup
Th
K7
Th Trip Sense
Gate A
------------------,
Gate B
LOG Ie
VOLTAGES
Main Storage
C82
.--___________________________ +T81} Main Storage
,-_____________ _ TB 1
TROS
Remote
Sense
T86
-3v
30 Amp
Fans
Rear PS
T2
T89
.----_____________________ +LBTB }Gate
, -____________________"'"T,.-L8T8
A
rr
t;::Il
STORAGE AND 1052
VOLTAGES
!1~.--.r-;::::=====~:~}+48v
0
1'".-.
I
""
K30
Remote
Sense
Fan.
C.
I Amp 1052
Front PS
TB4
T816
K2
Kl
S1l1----
I •
Al
208V
3S1l
S1l2---81
60Hz
Ll
I
L2
I'
I
0
• I
T1
L~ T1
T2
L2!
T2
T3
L3
T3
10
.-
I'
S1l3
Cl
C8 1
l3
--!....
,-611--------------------------- -LBT8
}
XV Select
I Amp
+3v
45 Amp
, -________________________ +T8 1 }
T88
N
M.ain Storage
}Gat. A
f---------------------------- +LBTB ~:~s~te
,----------:-----------__ -T8 1
TROS
~:~5~e
Cony
Outlets
110 vae
Wall
Frome
4 } -6/-9v Local Storage
3
6 Amp Z Inhibit
{~
T812
~----------~
--i
L~3_ _ _ _
T81-9
K2
J29
1052
Pwr Sup
WF Connections
WF Connections
PS 4
+18v
7
KI9
~rL4
I
L
__________________ J
~--'''''---'f-+---t--....
T5
14
L5
IIS/24v Transformer
K9
System Power Off
CPU Power Off
Railer
Sw Light
~J~8
CE Panel
Clock
K9
H
Note: With wall frame attached,
disconnect jumpers T813-1 through
T813-3 and T813-4 t~rou9~ T813-8.
EPO
Step
EPO
Logic
Voltages
. FIGURE 510. MID-PAC POWER SUPPLY WIRING DIAGRAM (SHEET 2 OF 2)
\.~
______y -_ _ _ _~
I/O
Ctrl
I/OCtrl
I/O EPO
Mach
T~
Start
Reset
Pwr
Ctrl
Memory
Voltages
Mach
Delay
Start
T81-7
WF
tv\emory
Voltage
T81-6
Wf
T81-8
WF
Stnck
Pwr
Good
Pwr
Good
C8
TrIp
T~
OIL
Lomp
Th Trip Sense
Note 2
TB4
Mecca
TBI
3
°
° f----c>(
1
2
60V
lA
1
O!-_-J
1---------I
I
1
....-_ _
Re_m_o_'_e_s_en_s_e_ _
I
9
Me'er
I
I
CPU
TB8~5
Kll
-t-
No'e2
TB3
1
2
3
4
5
6
CB5
l------A :
I
I
TB8-4
l------A-;
TB8-3
l------A
I
1
I
+
Remote Sense +
9
+6V de
Mecca
TB2
I
_-1
L ____ _
TB13-1
TB13-9
TB13-6
TB13-14
TBI
-3V
K2
+3V t=:K3
+18V t=:K4
TB6-4
+6V t=:K5
Mecca
TBl-13
Thermo I lamp
Pwr Sup Thermal
1. On HF power supply, K11 goes to
CPU TBll.
2. For 50-Hz connections, see ALD
peges YC500, YCS01, and YC502.
3. Refer to Figures 510 and 511 for
continuation of wall frame wiring.
4. On HF pewer supply, TBI and TB2
go 'a CPU TBIO.
24V Com
TBl-5
FIGURE 5l0A.
2040 MID-PAC WALL FRAME WIRING DIAGRAM
TB13-11
TB13-12
1
Me'er
T5
[[]
TB11
3
Indicator
Circuits
r--
To waH
Frame KII
i
l ---- -'fJ-~--~-9'----J
I
7653
I
- TB5
CI
-"---
5
,
,
'/
I
I
I
FI
F2
F3
F4
7
--(
6
5
t---I
,
,
!--~+~H}--l I---U-~~'}--I
7653
7653
"
I
,----4+-~'-{~-1 I-~~-~~'}--l
7653
-3V 40A
I
Gnd\----~
1J
,
_ Frame Ground
T' 7
Fans
I
-6/-' 4/6A
10 \1
TB 1-10
K2
0~1~---0-0---------r-1----r----1
F6
1052 and
Timer
0'"""'---___ 0-0 --------r-1--if"-
Gate A
LB TB 11
,os
II
'56Y 4A
• -
11 4
-
I
I
I
I
r--II
- ~-l
3
II
ttfJ
I
,I
-~H!}---
7653
+60V IA
1_
Bios
Control
Control
_________~~~---~_+----_+_+----4_r----_+~-~D~C~C~o~m
TB 1-11)
+ TB \-12
+ LB TB-8
LB TB 12
Remote Sense
Remote Sense
Remote Sense
Stock Thermistor
'41
,11
Mecca
Thermistor
'3'
O,V, Supply
CE Outlets
I~
ILtJ
Gote A
LB TB- 7
I
'OS
TS 1-9
__- - - - - - ,
765
I'
• I"-Iritr '
r---+---~-+-+---~-+-----+~~~-~--~----+----~~}-----~~~--~+-----+~+-+TB 12
7653
Bios
Control
~~'
I
I
I
I
it
I
,--11- H}--l r---41~
+6Y 25A
till
_J
F5
I
MY 40A
+ 10 II
7653
I,
J
I
I
1
I
1
Gnd Bus
I
K3
~
7
I
'J
'G
2R
IF
ID
IG
IE
-----------------~IH
IC
-,~
IJ
'40
L - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
___
lM_'_'____________________________________________I
Over Voltage / Under Voltoge Unit
____ § _______ I'_IO_ _ _ _
7 ___ _
~
r-----------o"o------1-~
TB 1
I
Com
TI
__
' ____
10_ _ _ _11_ _ _ _ 1_'_ _ _ _1_3__ _ 14 } Wall
Frome
TB I,
"
r -____________--o-U-~---~
TB'
~
~
-3V
~
Power Not Good
Power Good
~
~--~-------------~--------
TB2-8
4-1
~7-1
~9-1
'-I
48V
~
hlO-1
~1I-1
3
System Control
fiGURE 511, 2,5 kHz HF PONER SUPPLY WIRING DIAGRAM
CPU Start
c?--v
Power
Off
Power Control
Logic
Control
-3Y
12-1
Stack Sequence Contra!
M/C Ready
O/L Trip
Thermo!
Trip
Thermal
Trip
Indicator
Gote A
Thermo! Trip
Gote B
Thermal Trip
'OS
Thermal Trip
Mecco
Thermal Trip
Power Supply
Thermal Trip
2
CD=1
CB-3
Select Mox
A
ADR-O
Clear
Channel
4
3
SEL Select Unit
I
r--
A
1
OR
T2
Not SEL-O
Not OP-I
Not REQ-l
FL
A
';::: '---
~'---
Nnt Mox 1/0 Made
Not Dumo
FB031
I
~
OR
A
CB=4
CD=1
Select Mpx
Inhibit
Select
OR c---~r-
r8N
IF REQ-I
ADR-O Delay
Clear Channel
FB031
Unit
ADR-O
~obtainable
I
Select In
~r-
A
Set Se lect Out Latch
T3
I.....Not SEL-I or OP-I
I.....Not Halt I/O Mpx
FB009
Not CU Busy
A
A
OR
K3
Select In
o-SLO(Reset Sel Out)
ADR-I
Fs031
,.1.« Uo;' eo"h
~
I
Not Mpx I/O Made
A
fo- OR
ro
IfF
nter ace
A
Interrupt
FL
~~
Not Clear Mpx Error
Dump Not Trap Stop T~
Not MS Read Latch
ROAR to ROSAB
Not Disable Interrupt A
Not LO!l 1 Latch
Not YB (Inhibit Dump)
PI or PI Del
I
Dump Cycle
A
!L-J
FJOOI
FL
EJ-
Dump Stop T Clock
Not Inhibit On Error
FL
Undump Start T
~
StOP Half Clock 1
~
A
P2D
KM121
System Reset
A
I
OR
Set LSAR to 4F • ROAR to 001
Start T Clock
Set YB
1 R reQ to LS •
1
;w-- A
P4 Del or PI or Reset
Man Set R rea 0 iso/Store
Display And Store ROAR
C
t--
OR
ROAR to R Man or Dump
A
~ ~
Undump Stop T Clock
Clock Odd
St
Half Clock 1
Not Inhibit On Error
Undump Inhibi t
Cycle
FL
Undump
C cle
A
FL
Not Error Will St Clock
P4 Del or PI or PI Del
Not T2
P4 Del
KM121
Not System
Reset at P2
KM121
Not P4
Not Dum
Inhibit
CB=14
CD =3
Not Dum C de Start T
T3 or T3 Dela
o
A
Restore ROAR 0-11
Manual Set ROAR From Data Sw
T Cycle
1 2 3 4
1
P Cycle
234
RXOll
1
Microprogram Interrupt Latch
Stop Clock Latch
Stop Halfclock One
~ ROAR to R reg
.~
Dump Cycle Latch
}
Dump Latch
Reset Stop Clock Latch
~
Contents of ROAR transfer to R reg at T4 delay of last machine
cycle. T clock stops. During hardware cycle, LSAR is set to
4F; contents of ROAR (now in R reg) stored at address 4F in
local storage. ROAR is reset, then set to 001. The T clock
is restarted and the dump microprogram is executed.
FIGURE 512.
OR
I
ree or
~r---r--
P2
I
Dump Indicator
P4 Del
Undump Cycle Latch
B-
FBOll
Channel Microprogram
~'--
System Reset
FL
A
Unit Unobtainable
OR
A
Dump Latch
-f--
r-~
Clear Channel
Not Error Stat Y12
ADR-I Mox
B P2 or P2 Delay
Not Dump Latch
CB-12
CD=1
T2
Select Out
Hold Out
Not Any Chan Error
A
MULTIPLEX CHANNEL CONTROLS
Start T Clock
FJoo1
A
MPX I/o Mad e
4
3
2
SIMPLIFIED DRIVE SYSTEM
Write
Cl Boord
Write Gate
Driver
Transistor
A
Gate
Cores
B
~
POINT-TO-POINT EXAMPLE - GATE 05, DRIVER 04
-----,
Gate 05
C
X Gate
Decode
Jl0
B1M4
ME040
Brown
Wire
Coble Board
I
I
Brown
Wire
I
B07
D1G4
ME040
I
D1J2
ME030
I
I
I
I
I
I
D1J2
ME060
Driver 04
G03
Orange
Wire
MEOOO
Coble Boord
Bl0
Orange
Wire
MEOOO
ME040
I
MEOlO
L_ - -
---
Pictorial MD030
8035
ME060
--~
Array Pin
0
ME060
B035
Return Board
02
B094
Cl Boord
MD030
Array Pin
B213
ME060
E
,I
+60 v
007
BIM2
ME020
FIGURE 513.
J02
A2BOI
ME020
MAIN STORAGE X-DIMENSION DRIVE
J04
BIM2
ME020
Gray
Wire
Coble Boord
---X Read Gate
---,
0105
ME020
I
I
ME060
I
I Printed
Gray
Wire
Lond
002
CIH3
ME020
01
I
ME020
L __
MD030
ME060
I
-.J
Cores
Flow charts are provided for most machine instructions as tools
to assist in diagnosing errors. To be used effectively, their basic
philosophy and intended purpose must be understood.
Flow charts are a graphic representation of the complex sequence
of loops or routines in CAS diagrams. Insignificant CAS blocks are
not represented in the flow charts. In most cases, the notes in the
decision blocks are taken directly from CAS diagrams for quick
reference to actual CAS blocks. Flow charts guide the customer
engineer to the correct CAS block and shorten diagnostic time.
Each figure contains a flow chart, objectives, instruction and
data formats, the condition of STATS, the contents of registers at
reference points, and the CAS page numbers. When an instruction
has more than one format, all possibilities are shown. DMC version 4 was used to determine the data on these flow charts. The
top right chart gives the section and routine numbers for each flow
chart.
At several points (represented by circled numbers) in the flow
chart, the current status of the input data is recorded for reference.
These stop points can be duplicated with the use of Stop on ROS.
The use of predetermined data aids in checking the machine operation quickly. If a machine failure is data-sensitive, the data
can be changed to cause a failure.
Figure 618 is an example of how the flow charts and the DMC
test procedure can be used to isolate a machine trouble. If a
branch on condition failure that does not result in a hardstop occurs, Figure 618 may be used to locate the failure. First, load
DMC and call in the test section and routine indicated in the chart
(Section 120, Routine 10). When the DMC title prints on the console printer, enter the console keyboard Ll20/C.l0/B/. This will
read in and loop Section 120, Routine 10.
The flow chart (Figure 618) has four check points (circled numbers). These check points can be used by placing the proper ROS
address in the data switches and the address compare switch to
Stop on ROS. By comparing the actual data in the registers with
the predetermined data, the fai lure can be isolated to a small
section of CAS QE 031.
The flow charts are only a starting point; they do not replace
the need for a thorough understanding of CAS symbols and diagrams. These flow charts olso provide standard data for effective
communication when discussing machine problems with area
specialists or plant personnel.
FIGURE 599. HOW TO USE FLOW CHARTS
A
-0
-I
-2
-3
-4
-5
04
SPM 05
LCR 14
NR 15
-6
-7
-8
-9
-8
-A
-C
-D
-E
-F
BALR 06
BCTR 07
BCR 08
SSK 09
ISK OA
SVC
Branch
Set
Set
Branch
Branch
Insert
Supervisor
and
an
on
Program
Storage
Storage
Call
Mask
link
Count
Key
Key
Condition
609
614
609
608
618
612
OCool
388 OEOII
3BA Eool
38C QE031
38E OC041
390 OC041
392 OCOOI
394
0-
pE
10
LPR 11
Load
Negative
load
Positive
1-
611
OH071
LNR 12
611
381 OH071
LPDR 21
LNDR
Load
Load
Positive
Negative
(Fit Long)
(Fit Long)
625
625
AOO OKOII
OKOl1
A02
LPER 31
30
Load
Positive
3-
LNER 32
Load
Negotive
flo Store
STH 41
615
OH031
LTER 33
(Fit Sho,t)
LA 42
301 OH031
611
385 OHOOI
LCER 34
load
60
STD
615
38F OHOOI
Load
625
OKOl1
C
7-
load
CDR 2A
NADR
Add
Normalized
CER 3A
Add
Compare
MR 1D
615
620
OHOOI
397 OJ091
DR IE
623
399 OJ241
(Fit Sho,t)
625
625
A04 OKOII
A08 OKOl1
307 OEOOI
54
608
309 OEOIl
618
612
30D QE031
30B OE021
0
CL 56
Compare
Logical
615
308 OHOIl
OR
30F OH031
7
9
Compare
Exclusive
OR
Load
615
615
615
30A OHOII
30C OHOIl
30E OHOIl
616
616
317 QJOOI
313 OH081
315 OH081
C 5A
Compare
615
310 OHOII
LD 69
626
628
OK021
AI6 OJI21
628
626
626
AI8 OJI21
AlA OK021
AlC OK021 AlE
SH 4C
MH
AH 4B
CH 4A
Subtract
Multiply
Add
Halfword
Halfword
Halfword
L 59
Load
(Fit Long)
4E
CVD 4F
CVB
Convert
Convert
to
to
Decimal
Binary
610
613
OMOOI
31D OM021 31F
A 5B
Add
615
312 OHOIl
319
S 5C
Subtract
615
314 OHOII
M 5D
Multiply
620
316 OJ091
D 5E
623
318 OJ241
627
OKOOI
AOI
627
OKOOI
633
OC021
LPSW 83
Diagnose
load
PSW
628
OC021
340
639
344
LE 79
Compare
SL
Subtract
Logical
615
615
31A OHIOI
31C OHIOI
31E
626
AlB OK031
626
AID OK031 AIF
NSE 7C
NME 7D
NDE 7E
CE 7A
NAE 7B
AU 7F
SU
Subtract
Add
Multiply
Divide
Add
Subtract
Normalized
(Fit Sho,t)
(Fit Sho,t)
Normalized
Unnormalized Unnormalized
628
626
626
626
AI7 OJI21
All OK031
AI3 OK031
AI5 OK031
628
AI9 OJI21
626
626
AlB OK031
AID OK031
AIF
84
WRD 85
RDD 86
BXH 87
BXLE 88
SRL 89
SLL 8A
SRA 8B
SRDL 8D
SLA 8C
SLDL 8E
SRDA 8F
SLDA
Write
Read
Branch
Branch
Shift Right
Shift Left
Shift
Shift
Shift Right
Shift Left
Shift
Shift
Direct
Direct
Index High
Index
Right
Single
Single
Left
Double
Double
Right
Left
Lo-Eq
Logical
Logical
Single
Single
Logical
Logical
Double
Double
637
635
632
632
635
635
635
637
635
635
635
635
OCI51
348 OCI51
34A OE041
34C OE041
34E OLOOI
350 OLOOI
352 OLOOI
354 OLOOI
356 OLool
358 OLOOI
35A OLOOI
35C OLool
35E
MVI 93
TS 94
NI95
CLI 96
XI 98
LM
TM 92
01 97
Test
Move
Test
AND
Compare
OR
Exclusive
Load
and
Under
Multiple
Logical
OR
Mask
Set
636
631
634
636
631
636
636
OH041
341 OPOOI
343 OPOOI
345 OPOOI
347 OPOOI
349 OPOOI
34B OPOOI
34D OPOOI
34F OH041
351
90
Add
Logical
CD 6A
NAD 6B
NSD 6C
NMD 6D
NDD 6E
AW 6F
SW
Add
Compare
Subtract
Multiply
Divide
Add
Subtract
Normalized
Normalized
(Fit Long)
(Fit Long)
Unnorma I i zed Unnorma I i zed
78
Lood
(Fit Sho,t)
AL5F
Divide
STE
70
Store
(Fit Sho-:::::J
OOCC
H
~KEW
CI
II
AI
NJ
7
I
VA
J
4
!
NORMAL
4
I
OOCC
-
00
1ST HFWO OF INSN
VI
EXECUTE
H
1
I
I
FUNC
1000
VCI
VCO IZT
I>::J
I~
I
I
02
19
31
OBJECTIVES
fORM THE EFFECTIVE ADDRESS
OF OPND 2 AND PERfORM
A FUNCTION 8P.ANCH ON THE
LOW ORDER 4 BITS OF THE OP CODE
LONG
PRECISION
SHORT
PRECISION
UPDATE INSTRUCTION
AOOI\ESS TO NEXT
INSTRUCTION AND WRITE IN
LOCAL STORE 47
NO
UPDATE INSTRUCTION
ADDRESS TO NEXT
INSTRUCTION AND WRITE IN
LOCAL STORE 47
YES
YES
YES
NO
fORM A[)()p.£SS OF OPND 2
FROM CONTENTS OF
FORM ADDRESS OF OPND 2
FROM CONTENTS OF
82
X2
+
02
SHORT
NO
...
0:
0
l;;
e....
~
~
e....
~
~
g g e
~
~
~
~
~
~
YES
e....
~
~
+
02
LONG
NO
YES
0
::.
~
~
FIGURE 603. 2ND LEVEL INSTRUCTION FETCH, RX FLOATING POINT (Q0051)
0
c
0....
~
~
E
0
u
E
~
8c
E
~
!
'"
...0
>
0
Z
!i
z
Z
::;)
!
'"
ENTRY DATA
NJ
lNSN ADDER
Cl
lNSN AOOR PLUS 2
SKEW
H
l><1
NO EXAMPLE SHOWN.
co
Al
YA
!
'"
7
3
l><1
YB
~
FUNC
YCI
YCO IZT
RS
I op Code I
0
7
Rl
I
11
R3
I
82
IS
I
02
19
I
31
SI
lop Code
0
7
12
I
81
IS
I
19
OBJECTIVE
TO READ 2ND HFWD OF
INSTRUCTION FROM MAIN
STORE AND PERFORM A
FUNCTION. BRANCH ON
THE LOW ORDER 4 BITS
OF THE OP CODE.
01
I
31
SI
RS
INCREMENT INSTRUCTION
ADDRESS TO NEXT
INSTRUCTION.
SET Yb-I/)
INCREMENT INSTRUCTION
ADDRESS TO NEXT
INSTRUCTION.
SET Yb-!
WRITE NEXT INSTRUCTION
ADDRESS IN LOCAL
STORE (47)
YES
REWRITE 2ND HALFWORD
OF INSTRUCTION.
FETCH CONTENTS OF
B2 (RS OR 81 (S I)
51 f, 81:1/)
OO~~~~----------------------~-<
FIGURE 604.2NO LEVEL INSTRUCTION FETCH, RS AND 51 OPERATIONS (Q0031)
RS f, 82=1/)
10
NO EXAMPLE SHOWN.
ENTRY DATA
AD
Al
AODR OF 1ST HFWO
OF lNSN
SKEW
OPI
CO
Cl
AOOR Of 2ND HFWO
Of lNSN
H
YA
4
4
4
Y8
FUNC
YCI
SS
I
lZT
FIOM I" LEVU
I OP Cod. I L1 I L2 I 81 I
11
0
7
19
15
I
I
YCO
OOCC
lst HFWO
I
I
I
I
01
I 8235I
02
INSTlUCTICIN FETCH
I
47
31
I
2nd HFWO
I
I
I
Jrd HFWO
I
UPDATE INSTRUCTION
ADDRESS TO NEXT
INSTRUCTION AHD
WRITE IN LOCAL
STORE 47
OBJECTIVES
TO FORM THE EFFECTIVE ADDRESS
OP OPND 1 AND OPND 2. AND PERFORM
A FUNCTION
BRANCH ON THE LOW
BITS OF TIlE OP COOE
ORDER
<)
00101
------------------------------aD1IT
FORM ADORESS
OF OPND 1 HIGH
HFWD FROM
CONTENTS OF
81 PLUS 01
FORM ADDRESS
OF OPND 2 HIGH
HFWD FROM
CONTENTS OF
82 PLUS 02
FIGURE 605.2ND LEVEL INS1ItUCTION FETCH, SS LOGICAL
FORM ADDRESS
OF OPND 1 FROM
HIGH HFWD
FROM 01
FORM ADDRESS
OF OPND 2 HIGH
HFWD
FROM
02
NO EXAMPLE SHOWN.
H
SKEW
4
OPI
!
4
4
7
YA
YB
OOCC
0000
FUNC
YCI
YCO
IZl
I>
Q
~
~
~
ODm
FIGUIE 4106 2ND LEVEL INSllUCTION fETCH, SS DECIMAL
Q
9
c
~
...~...
::::;
~
~
If
2:
8
... ~
...'" ...:::>
.
~
Q
Q
c
:::>
'"
~
~
2:
~
:;
0
Q
0
-'
:;
~
~
~
~
FIRST LEVEL 0' DECODE (O~!)
XJ
All
AI
III
It' HFWD OF INSTR. ADORJ OP2 Ii
C~
8!
;:::::>x
X
lCfN BIT OF OI'NDl AIlOR
IDN BlTOF OPNO 2A11OR
(IF TRANSlATE OR TRANSLATE AND TEST GIVE A CARRY
INTO THE EX TENDE 0 BYTE OF OPND 2 ADDRESS, THE
romcT VALUE OF THE EXTENDED BYTE IS
OBTAINED FROM G + YCD)
I
RI
2""HFWD OF NSTI\UCTION
2""HFWDOF NSTIIUCTION
,(II
.0!
L2
I!>
I OPNDl ADDRESS+ Ll I
LOCAL STORE (40) CONTAINS L2 \Ill!> LI
LOCAL STOllE (41) CONTAINS OPND 1 ADDR+ U
MACHINE STATUS AT 1ST AND 2ND LEVEL FUNCTION BRANCHES
o P2
4 2
40
ENTRY DATA - RR
AI~~DO
M
01
Rl
I
BRANCH AND LINK
R2
....lR 01, 02
REG 2
00006268
00006268
00006268
ROS
38A
H
SKEW
U
J
o
VB
xooo
FUNC
VCI
VCO
JA8
3£2
IZT
I><1 IX!
0
AI EVEN = 0
Al ODD = 1
RR
I OP Code I RI I R2 I
o
7
i1 IS
RX
I
o
I
QP Code
7
Rl
I
11
X2
I
IS
82
I
D2
19
31
OBJECTIVE
RR ENTRY
THE RICHTMOST 32 BITS OF THE PSW
4RE STORED IN THE REGISTER
SPECIFIED BY Rl
THE BRANCH ADDRESS IS FORMED
TO REPLACE THE INSTRUCTION ADDRESS
IN THE RR FORMAT IF R2" 0'
THIS INDICATES· NO BRANCH
RX ENTRY
y----~(j)
OP CODE
05-RR
45-RX HALF
FORM BRANCH
ADDRESS FROM
REG SPECIFIED
BY R2
NO
YS=1
YES
FORM BRANCH
ADDRESS
1---0
NO
YES
WRITE INSN CT
INTO LO HFWD OF
Rl SET ILC FOR
HFWD INSN
WRITE INSN CT
INTO LO HFWD R I REG
SET ILC FOR
2 HFWD INSN LENGTH
1----13
---------
OE(ljU
OE¢:U
FIGUtE 6OS.BRANCH AND LINK
NO EXAMPLE SHOWN.
ENTRY DATA
MJ
Al
BO
INSN ADOR
BI
CO
H
YA
7
4
4
4
OOCC
RR
I OP Code I
o
7
RI
I
II
DO
01
I > < l > < I I N S N ADpR PLUS 2 IOP,1 OP2! RI I R2 I
SKEW
0000
CI
R2
I
15
oaJECTIVES.
SET STORE KEY.
THE KEY OF THE STORAGE BLOCK
ADDRESsED BY THE REGISTER
DESIGNATED BY R2 IS SET ACCORDING
TO THE REGISTER DESIGNATED BY Rl
lN5I:lfT STORAGE KEY
THE KEY OF THE STORAGE BLOCK
ADDR£SSED IIY THE REGISTER
DESIGNATED BY R2 IS INSERTED IN
THE REGISTER DESIGNATED IIY R1
SAVE PROTECTION KEY
FROM ST REGISTER.
REWRITE OPND 2
ItGH HFWD TRAP f ISA
. . . . ",SET AND INSEIT STOIAGI KIY
YB
xoool
c::
FUNC
YCI YCO IZT
11011
INSERT KEY = I
SET KEY = 0
ENTRY DATA
AD
AI
AOOR Of oPNO 2
LOW HEWO
BO
RI
BI
I !><1><1
2
CONVERT TO BINARY
ADD
YCI
YCO
IZT
LXIXIX1
RX
I
o
I
oP Code
7
RI
I
\I
I
X2
15
I
B2
19
ROS
31F
CD
02
~
2M
2AO
@
2CO
CVB
OMC
SECTION 167, ROUTINE 05
REG 5
REG 6
00006BC4
00006BCO
MAIN STORAGE 6BC4 ~ OOOOOOOOOOO1408C
MAIN STORAGE 6BCO ~ 0000000000000580
FFA42580
FFA42580
MAIN STORAGE MF8 = OOOOOOOOOOOl40BC
bbbb0580
A REG
MF8
B REG
2000
C REG
DREG
0000
0000
2040
0000
2001
2000
0000
0000
0000
0000
62C8
2000
0000
0580
31
OBJECTIVE
TO CONVERT 15 DECIMAL DIGITS
PLUS SIGN TO BINARY AND STORE
THEM IN A GENERAL REGI STER
OPND 2 NOT ON
DOUBLE WORD BOUNDA
THIS LOOP IS REPEATE
UNTILl All Ib DIGITS ARE
14-~_-ll~':~S~9: LOCATIONS
TWO DIGITS PER lOCAL
STOR WORD
READ NEXT HFWD
FROM MAIN STOR
- - ---
SECOND TWO
DIGITS OF HFWD
TO LOCAL qOR
Y0=0 ADD lEFT DIGIT NEXT
Y0 = 1 ADD RIGHT DIGIT NEXT
OF MOST
SIGNIFICANT BYTE
SET Y0~1
PLACE LEFT DIGIT
()F BI IN SKEW REG
Vi
Y7
~
32 BIT OFlO
~
SIGN
~
t--_--'Y..::ES"-< lEFT DIGIT
=0
RIGHT
>-:-::::__,
LEft
ADD Lff 1 1)1(.,11
10 PARI IAI "ur~
(IN RfGD)
SFT Y0" 0
01
=
NO CARRY NOT LAST DIGIT
00 = LAST DIGIT NO CARRY
1211
10
00
H
10
yeo
11
YF5
=
=
CARRY LAST DIGIT
CARRY NOT LAST DIGIT
NO
LASI
DIGIT
OM021
- OM041'0M011-
,
,
L SH PARTIAL SUM (X2)
RSH PARTIAL SUM (-;-2)
SKEW RSH VALUE TO GIVE
XB RESULT ADD TO lSH
VALUE TO GIVE XIO
,I
,
,
READ 1ST TWO
BYTES TO RESULT
REG SPECIFIED
BY Rl
I
I
I
,
I
,
YES
,
,
I
,
,
EPARE FOR NEXT
I FETCH READ FINAL
TWO BYTES TO RE('
SPECIFIED BY Rl
RESET Yl =0
=~":=~--I0
I
I
I
I
I
I
FIGURE 610 CONVERT DECIMAL TO BINARY
LOOP PERFORMED FOR EACH DIGIT
UNTIL ALL DIGITS HAVE BEEN CONVERTED
STAT SETTING FOR PROGRAM LOOP
[(PARTIAL SUM + NEXT DIGIT) X10]
PASS
1
2
3
4
5
b
7
lATER
Yb
H
''"" '" '"
''"" '"
15
15
15
15
14
13
12
12
Y4
1
1
1
1
1
1
Y5
I
1
''""
'"
0
121
1
1
1
1
ENTIY DATA
/IIJ
T
AI
H
SKEW
111X~XO
OP2
co
II
CI
J
$
YA
YI
OOCC
0000
FUNC
YCI YCD IlT
LOAD POSITIVE REGISTER DMC SECTION 160, ROUTINE 01, STOP ON MS 6100
A REG
I REG C REG
DREG
lOS GP REG 2
6100
2020
0001
1022
381 00000001
()O()W,bb
61
FF
0000
0001
0022
381
3FFFF
0000
0001
0022
IE8 bbbbOOOl
CONTINUED ON FLOW CHART NUMBER 615
@ IC9 00000001
~
lEE
6101
6108
00000001
7030
0000
0000
0001
RI
I OP Code I
o
7
RI
I
11
R2
I
15
OBJECTIVES
TO PERFORM THE RR FIXED POINT
SIGN ops. L£W) AND TEST, LOAD
COMPLEMENT. LQ\[) POSITIVE. L£W)
NEGATIVE.(FOI DESCRIPTION Of
OBJECTIVES OF EACH INSTRUCTION
SEE PRINCIPLES Of OPERATION
MANUAL)
LOAD
II«)
TEST
MSS OPND 2 BYTE 1
FOR LATER III TE ST.
FETCH OPND 2
HIGH HFWD
/
LOAD COMPLEMENT
LOAD POSITIVE
COMPLEMENT OPND 2
IIYTE 1 INTO Ai
fETCH OPND 2
HIGH HfWD
COMPLEMENT OPND 2
IIYTE 1 INTO A1 IN
CASE SIGN IS
FETCH OPND 2
HIGH HFWD
SET lCD-SIGN
Of OPND 2
REWRITE OPND 2
HIGH HFWD
PASS OP CODE 2
FROM SKEW lOX
TO SENATE LD
AND TEST AND LD
AND COMPLEMENT
REWRITE OPND 2
HIGH HFWD
LOAD NEGATIVE
COMPLEMENT OPND 2
BYTE 1 INTO Ai IN
CASE SIGN IS POSITIVE
FETCH OPND 2
HIGH HFWD
SET YCD -INVEItSf
OF SIGN OF OPND 2
REWRITE OPND 2
HIGH HFWD
lD PLUS TEST SIGN
OF OPND 2
LD MINUS TEST INVERSE
Of SIGN OF OPND 2
0~-LOAD AND TEST
LD<
AND OPND 2
IS PLUS
lD- AND OPND 2
IS MINUS
COMPLEMENT
PASS OPND 2 BYTE 1
FOR LATER III TEST.
WRITE OPND 2 lOW
(UNCOMPlEMENTED)
AS RESULT lOW
---0
PROCESS BYTE 0 FElCH INSTR
COUNT TEST SIGN FOR RESULT
TEST FOR ZERO RESULT
TEST FOR FIXED POINT OF LO'S
WRITE RESULT HIGH HFWD
FIGURE 611 FIXED POINT SIGN OPERATIONS (QH07I)
0000
0022
ENTRY DATA - RR
NJ
Al
SKEW
0000
10
81
CO
J
c::::±<: I::::::>:<:::J
H
DO
Cl
YA
YB
DOCC
BRANCH ON COUNT BCT 02,05 OMC
ROS
REG 2
REG ..
01
FUNC
YCl
YCO
IZT
YCI
YCO
IZT
38C
()()()()()(la!
00000oo I
3E8
00(lCbbbb
3C9
bbbboooo
SECTION 122,
REG 5
ROUTINE 25
A REG 8 REG
6546
6040
00000001
()()()()6542
()()()()6542
6S42
6002
00000oo I
()()()()6542
6542
0000
C REG DREG
6S48
6500
6500
I:::oJ C>PNO J FROM LOCAL
S TOR
NO
YES
CLEAR INSN ADDR
IN LOC AL STORE
PROCESS CARRY
THRU BYTE 2
CARRY
FROH BY TE
YES
2.
PR(;CES SCARRY
Oil BYTES 1 AND
BYTES 0 REWRITE
OPtJ[) 1 TO LOC AL
STOR
FE TCH NEXT INSN
USING ADDRESS
IN INSN ADDRESS
LOCATION (IC) IN
LOCAL STOR
--.9..E¢1!.
OE031
FIGURE 612. BRANCH ON COUNT (QEOll , QE02I, QEOI3)
0625
0625
0000
ENTRY DATA
1.0
OPND
ao
AI
~ ADDR
BI
CO
CI
DO
CONVERT TO DECIMAL CVD
ROS
REG 0
01
I !><
RI
~
0
31D
2CD
2FE
FFA42580
FFA42580
FFA42580
DMC
SECTION 167. ROUTINE 12
REG 8
A REG B REG C REG
00000010
6AF8 .eooo 0000
00000010
6AF 0 .eooo 1000
00000010
6AFE .eooo 0000
SKEW
o
OP2
RX
I
o
OP Code
I
7
RI
I
II
X2
I
15
B2
I
02
31
19
OBJECTIVES
TO CONYERT A ]I.IT a",ARY
WORD PLUS SIGN TO 15 .. BIT DECIMAL
DIGITS PLUS .. BIT SIGN
NO
SIGN AND
~CJ;CJ=========;-I~--<'HIGH ORDER :>----'f----=
to
BYTE = 0
(11115
''''''S$lkE)
CONDITION
'-../'
YES
LOAD J OlC· WITH
IS aUR LOCAL
STORE
O-IS
STORE OI'ND 2
ADDR IN LOCAL
STORE POSITIOI< 15
PLACE CONTEMTS
I
I
I
I
c" ••e .. ce
REDUCE
J REC
"'1
k
DECI_ ADO ,."
CAllY fIl()M
PlEYIOUS STEP
LOOP 2
)
C.Al·I+1
11
I
INTO " lEG. AUO
ADD at REC TO
ITSELF
REDUCE J REC
I--( ANS· .,+C. )
I
BYI
C'A
L ____________________ .,
D·
SET 01. DIICIMAI.
.+-~
IIlOM LAST
_..-'"
LOOP S
MAD ADONSS
Of OPND 2
IDCAL
$lOR
L __________________________________________O~J~,.!
OMn
FIGURE 613.CONV£RT BINARY TO DECIMAL
0 REG
0000
00 I 0
016C
ENTRY DATA
AO
Al
80
81
CO
CI
00
01
SET PROGRAM MASK
ROS
REG I
388
3FOOOOOO
3E4
3FOOOOOO
2J
READ OUT
IIISTRUCTION
ADDR TO A
REG
UPDATE INSN
ACDR WRITE
PSW BACK TO
LOCAL STORE
---<0
i
ENTRY DATA- RR
NJ
AI
SKEW
EXAMPLE CONTINUED FROM FIGURE 611
II
I
R2
CO
OPND2
0
LON HFWD
J
H
OP2
III X
!
YA
YB
FUNC
CI
00
01
YA
YB
FUNC
YCI
YCD IZT
XXXO
BI
I
C><\
H
J
ADDR OF OPND 2
~I
0
LON HFWD
__
SKEW
CI
CO
OP2
1 RI
r> AND THE SUo! IS
PlACED IN THE FIRST OPERAND
LOCATION. THE HFWO. 2ND 01'1'1>
IS EXPAI'CED TO A FULL WORD
BEFORE THE· AODITlON OR SUBTRACTION
IJt PROP~TING THE SIGN-BIT VALUE
THROUGH THE lb HIGH ORDER BITS
10
PROCESS BYTE J. WITH
fMX/Jflt/)(/)I/XlJ.
CHANGE CONSTANT
TO 0000QH/H/)0
SET CONDITION
REGISTER TO 9>1
HE WRITE OPND 1 HIGH
AS RESULT HIGH
r-----
r-----
YES
____ -.l
WRITE RESULT HIGH.
SET CONDITION
RE'jISTEk TO Ib 1
YES
NO
QH~J.
QHj"2T-------- - --- -
TRAP
-------------1
fiGURE 616.RX FIXED POINT ADD AND SUlTRACT
ROUTINE 20
C REG DREG
2222
IAl8
2222
2288
8888
0088
4780
0026
ENTRY OATA- RR
/>D
Al
~
SKEW
H
CO
CI
OMC SECTION 105, ROUTINE 46 STOP ON MS 618C
COMPARE
Y8
YA
J
01
DO
FUNC
YCI
ROS
312
~
YCO IZT
IF7
IEC
A REG I REG C REG 0 REG
REG 2
682E
682C
6820
00000010
bbbbOOIO
00000010.
2000
0000
0000
0000
0010
0022
CONDITION CODE = 00
1
ENTRY OAT A - RX
/>D
Al
AODR Of OPNO 2
lOW HFWO
SKEW
L:NORMAt:=O
EXECUTE = I
81
CO
CI
2
H
DO
01
YA
Y8
FUNC
OOCC
XOXI
ADD
YCI YCO IZT
I>OPND 2
01 IF OPND1q.l
QH~f
OPND1!
I
_.J
NO
CONDITION REGISTER
ALREADY = 111>
FIGURE 617. RX COMPARE ALGEBRAIC
-
0010
0000
4780
=
ENTRY DATA - RR
SKEW
o
DO
OPIIOP2!
ENTRY DATA - IX
/11)
AI
SKEW
YA
VB
OOCC
0001
J
H
e>8 "
2) 2ND MPLE. (I~ NEEDED) TO BE SUBTRACTED.
SET Y(lJal IF 2ND. I4'LE. NEEDED.
SET INDIRECT FUNCTION TO ADD·OR SUBTRACT
ACCORDING TO TABLE IN FIG. .
FETCH p.p.(a)Kl(IJ) F~M RESULT·REG.(.LJ)/(l(IJ)
IN LOCAL STOR.
,-
NO
OJ 1131
o
I
I
____ J
QJ0&11
THIS MEANS FETC~PAIAL PRODUCT
FROM RESULT REG.
IF WE ARE
DEALING WITH L
FWD OF MPLR
AND P.P.om> FROM .RESULT REG. a(IJ1 IF
MPLR.HfGI-l HFWD.
OJ041
_ _ _ _ _ _ _OJ07!J
DIGIT r-----------~--("
~ORl
OJ041
OJt)41
------,----
OJ071
OJ0l!1
IF LOW HFWD Of MPLR:
P.P.(l1)KEPT IN RESULT REG.(U) IN L. STOR;
P.P.(lC3)KEPT IN REG.A IN DATA FLOW;
PP(j2l1)KEPT IN RESULT REG.(10) IN L. STOR;
IF HIGH HFWD OF MPLE:
jp.P.(U)KEPT IN RESULT REG.(11)IN LSTOR]
P.P.(lC3)KEPT IN RESULT REG(1C3) IN L. STOR;
P.P.(IZll) KEPT IN REG. A IN DATA FLOW;
P.P.(00) KEPT IN RESULT REG.«(lJl) IN L STOR
NO
r
I
PROPAGATE CARRf/BORPOW
INTO LEFT ADJACENT BYTE Of
P.P." STOR IN RESULT REG.t<:J j ! R21
! c:::::::±<:J
L R2 =:J
RI
SKEW
0
J
H
01'2
XXXO
lllX
ENTRY DATA - RX
NJ
Al
ADDR~OPN02
! RI
LOW HF 0
i
01
DO
Q!
0
FIGURES 623 AND 624
YA
YB
OOCC
FUNC
0000
YCI YCO IZT
C> 2
NEXT (ORIST) BYTE
REWRITE OPND 201
l"D
PASS
1 ST PASS
2ND
PASS
PLUS
PASS OPND 2 BYTE 1
FORlATER I i!T
TEST CLEAR
OPND 1 (01)
SET CONDo REG.
10 FOR PLUS
ClEAR OPND 1 (\tl1)
1" PASS
ClEAR OPND 1 (u)
1"0 PASS
MINUS
PASS OPND 2
BYTE 1 FOR LATER
1i!T TEST
LEAR OPND 1 (12:11
SET CO NO. REG.
01 FOR MINUS
CD
LONG
SHORT
LONG PRECISION
lAD PASS OR
SHORT
PRECISION
PROCE SS OPND 2
NEXT BYTE
WRITE RESULT
(0!Z1) 1 ST PASS
(!ZI1) 2ND PASS
PROCESS OPND
NEXT BYTE
WRITE RESULT
(00)
SHORT
PRECISION
WRITE RE SULT
10)LONG PRECSION
lRD PASS
FETCH OPND 2 (10)
FIRST PASS
FETCH OPND 2 (11)
SECOND PASS
PROCESS OPND 2
LOW BYTE
FETCH INSN
COUNT
---10
TO WRITE RESULT (01)
(SHORT PRECISION) OR RESULT
(11) LONG PRECISION, AND
TEST III FOR lERO RESULT
fiGURE 625. RR FLOATING POINT SIGN OPERATIONS
ENTRY DATA
NJ
T
Al
R2
!
1100
DO
YI
YA
J
op Code
I
RI
I
11
7
01
NO EXAMPLE SHOWN.
XXOI
FUNC
YCI YCD IZT
OOXO
XORIIII
f
SHORT-O
L...---LONG = I
L:R2:J
RX
0
CO
CI
OPN02
HIGH HFWD
H
SKEW
I
II
X2 I 12 I
15
19
I
02
31
RR
I!Z~I
0
7
RI
I !2 I
11
15
QK{Z)31
QK¢21
FROM
INSTRUCTlON~
RX ENTRY)
FETCH
INSTRUCTIONS
SINGLE
INSTRUCTIONS
t. DOUBLE
SINGLE
I
DOUBLE
COMPARE
ADD} UNNOI\.MALIZED
SUB
AQD } UNORMALIZED
SUB
I
I
ADD
} NORMALIZED
SUBTRACT
COMPARE EXPONENTS TO ,I) CALCULATE EXPONENT DIFFERENCE(ED),
SEI STAT FOR EXPECTED RESULT SIGN;
SET ALU FN TO ADD OR SUBTRACT,
WITH OR WITHOUT SKEW.
COMPARE EXPONENTS TO ,I) CALCULATE EXPONENT DIFFERENCE (EO).
2) SET STAT FOR EXPECTED RESULT SIGN;'
3) SET ALU FN TO ADD OR SUBTRACT,
WITH OR WITHOUT SKEW.
2)
V
1
I
r---
I
..---'==-"-'==='-<
_
I
or ~~3i~E
SINGLE LENGTH
LENGT~ _ _ _ _ _
EXPONENTS
I
(OPND1~OPND
2)
_
op~~'~~S
DOUBLE LENGTH
LENGTH
I
EXPONENTS (OPND 1 < OPND 2)
1
'-/
1.-----'--------,
QK{Z)71
QK{Z)81
EXPONENTS
(OPND1OPND2)
2)
'-/
QK04.1
QK{z)Sl
OK.061
NO
I
TEST E.D.
FOR BYTE
SHIFT
YES
NO
TEST E.D.
FOR BYTE
SHIFT
YES
I
1
I
EXPONENTS
(OPND lBl TYPE)
LOOP
EXPONENTS
(OPND1;' OPND 2)
t. THERE IS BYTE SHIFT
(;. Dl=Alt>B0 TYPE)
LOOP
OK121
EXPONENTS
(OPND IDI TYPE)
LOOP
EXPONENTS
(OPND1< OPND 2)
t. THERE IS BYTE SHIFT
C;. Al=Blt>D\2) TYPE)
QK131
SH2
FIGURE 626.FLOATING POINT RR AND RX (QK02I, QK171)
(SHEET I OF 2)
SHI
QKIII
QKl21
QKl31
QKl41
QKl51
COMPARE
~EST
OVERFLOW
QKl51
EXPECTED RESU-LT---
SIGN STAT & IZT LATCH
& SET CONDITION
REGISTER ACCORDINGLY
RECOMPLEMENT
NO
UNNORMALlZED
II
NORMALIZED
I
YES
NO
~T
YES
INTERMEDIA-TE--
RESULT LEFT I DIGIT
QKl61
QKl71
TO
INSTRUCTION FETCH
NO
ON
OFF
OFF
OFF
YES
TRAP ROUTINE
TRAP ROUTINE
TO
INSTRUCTION FETCH
FIGURE 626. FLOATING POINT RR AND RX (QK021, QK171( (SHEET 2 OF 2)
INSTRUCTi8N
FEc.:.TC: :cH~
__
QKl51
ENTRV DATA
/IJJ
Al
ADDR OPND 2
HIGH HFWD
LOAD flOATING POINT SHORT
STOP ON MS 6158
ROS
All
H
SKEW
J
OP2
VA
VB
OOCC
OOXO
I
FUNC
VCI
VCD
IZT
BF9
174
lF5
XOR
LSHORT
LONG
DMC SECTION 195, ROUTINE 03,
FP REG 00
A REG
A86878184321OC8A 6E58
A868~IB4321OCBA 6E58
A868781843210CBA 6E58
A868781843210CBA 0939
0
=1
RX
I
o
op Code
I
Rl
7
I
11
I
X2
15
I
82
19
02
31
OBJECTIVES
STORE FLOATING POINT
THE FIRST OPND LOCATED IN THE FLTG POINT
REG SPECIFIED BY R1 IS STORED AT THE
EFFECTIVE ADDRS GENERATED BY X2,D2 AND B2.
THE STORED OPND AND THE CONDITION CODE
REMAIN UNCHANGED
LOAD FLOATING POINT
THE SECOND OPND WHICH IS LOCATED IN
MAIN STORE AT THE EFFECTIVE ADDRESS GENERATED
BY X2, B2 AND 02 IS PLACED IN THE FIRST OPND
POSITION WHICH IS THE FLTG. POINT REG.
SPECIFIED 8Y R1. THE LOADED OPND AND THE
CONDITION CODE REMAIN UNCHANGED
B0 =
1¢ CR 0010 FOR
SHORT OR
1¢ CR 01¢¢ FOR
LONG
SET B0 REGISTER
TRAP IF ISA
YES
YES
NO
HFWD
TO C REG AND
REWRITE
FETCH OPND 1
HIGH HFWDTO
o REGISTER FDR
STORING
INCREMENT MAl N
S10RE ADDRESS
CLEAROPND 1
HGH HFWD
STDRE OPND 1
HIGH HFWD AND
REWRITE
QPII[) 2 HIGH
QH¢H
LOAD
STORE
INCREMENT
MAIN STORE
ADDRESS
CLEAR OPND 1
INCREMENT
STORE ADDRESS
FETCH OPND 1
10 C REGISTER
L------------1--0
ADD STATS TO 8¢
AND TEST ALU6
FOR EXIT. LOAD
OPND 2 OR REWRITE
OPND 1 FROM C REG
FETCH NEXT
HFWD OF OPND 2
LOAD-EXIT
CLEAR OPND 1
LOW HFWD.
OPND 1 LOW HFW
INlO 0 REGISTER
FOR STORING
'-----r:~===-0
LOAD AND REWRITE
OPND 2 LOW HFWD
OR STORE AND
REWRITE OPND 1
lOW HFWD
LOAD R1 ADDRESS
IGH HFWD. OPND 2
INTO C REG. (FOR
LOAD)
STORE OPND 1 OR
REWRITE OPND 2
FIGURE 627, FLOATING POINT LOAD AND STORE (SHORT AND LONG)
8 REG
2000
0000
0000
011'0
C REG
DREG
0082
SS55
SS55
0000
SS55
SS55
SS55
SAFO
ENTRY DATA- RR
NJ
T
Al
81
R2
!
1100
OPND2
Cl
DO
01
Y8
FUNC
flOATING POINT MULTIPLY, SHORT NMER DMC SECTION ICC, ROUTJNE 01, STOP ON MS
6OF2. THIS OPERATION WILL USE FIGURES 628 AND 629.
HIGH HFWD
J
H
SKEW
CO
R21 9
YA
YCI
YCD
~
IZT
XXO
ROS
AI8
AA6
MIl
ADO
AF5
FP REG 00
45100000
45100000
45100000
45100000
45100000
FP REG 02
45100000
45100000
45100000
45100000
45100000
45100000
45100000
45100000
45100000
45100000
45100000
45100000
45100000
45100000
451(1,bbb
45I(1,bbb
451 (l,bbb
bbbbbbbb
bbbbbbbb
bbbboooo
bbbboooo
A REG
6OF2
6OF4
6OF4
4AF4
4AF4
8 REG
COO9
2040
200
0010
0010
C REG
4510
4510
4510
0020
0020
DREG
3C20
0000
4510
200c
200c
FIGURE 629
ADDROFOPND21
~
HIGHHFWD
• RIO~}
_ _
SKEW
J
H
YA
OP2
Y8
ooxc!
FUNC
XOR
YCI
YCD
lZT
lXlXIXJ
I
887
SF7
92F
930
93E
84C
8CE
9AE
0000
0000
0000
0000
0000
0000
0100
6OF4
0060
0000
0000
0000
0000
0000
0000
4910
4Al0
4510
4510
0000
0000
0010
0010
0100
RR
I OP Code I
o
7
RI
I
11
R2
I
15
RX
I
o
OP Code
I
7
Rl
I
11
X2 I 82 I
15
19
02
31
OBJECTIVE
TO SHOW THE INITIALIZATION FOR FLOATING POINT DIVIDE/MULTIPLY
RX~TING
~
FETCH
COf'Y OPERAND 2 FllACTION 10
lOCAl. SIORAGE LOCATIONS
2.3- MULTiPlY SHORT
9>.1 - DIVIDE SHORT
9>.1.2.3 MULTIPlY,DMDE LONG
SET '10 =OPERAND 2 SIGN.
~
10 SHOW THE INITW.JSATION FOR fl.Q\TING POINT DMDE/MULTIAl'
NO
YES
OJJ21
OJl31
YES
NO
DECREMENT OPERAND 2
CHARACTERISTIC.
SKEW OPERAND 2 FRACT ION
LEFT 1 DIG IT POSITION
NO
YES
DECREMENT OPERAND 1
CHARACTERISTIC.
SKEW OPERAND 1
FRACTIOO 1 DIGIT LEFT.
NO
YES
NO
TRAP
lOITlNE
OQIlU
MULTIPLY
~r-----------~~~
SH2
FIGURE 628.FLOATING POINT MULTIPLY/DIVIDE INITIALIZATION
(SHEET 1 OF 2)
SH2
SHI
0000
0000
0000
0000
4500
4500
4500
0000
QJI41
SH2
QJI41
COMPARE FRACTIONS. SET
FLAG (YI) IF FRACTION I ~
FRACTION 2. SKEW FRACTION
2 LEFT I DIGIT POSITION.
COMPUTE CHARACTERISTIC
OF RESULT
YES
NO
YE
SHI
NO
QJI71
FORM2 BYTES OF EACH MULTI PLE
OF FRACTION 2AND STORE IN
LOCAL STORAGE WORKSPACE.
FOR MULTIPLY THE MULTIPLES
ARE X2,3,6; FOR DIVIDE X2,4,8
YES
NO
DIVIDE
SHORT
LONG
QJI61
QJI61
INSERT INTERMEDIATE
CHARACTERISTIC IN RESULT
LOCATION. SET PARTIAL
PRODUCT TO ZERO
NO
DIVIDE
LOOP
QJ281
DIVIDE
LOOP
QJ281
FIGURE 628. FLOATING POINT MULTIPLY/DIVIDE INITIALIZATION (SHEET 2 OF 2)
COpy 5 MOST SIGNIFICANT
BYTES OF OPERAND I AND
INTERMEDIATE CHARACTERISTIC
TO LOCAL STORAGE WORKSPACE.
SET PARTIAL PRODUCT TO ZERO
THE FRACTION OF THE flOATING-POINT
OPERANDS ARE MULTIPLIED USING THE
SAME ALGORITHM AS FOR FIXED POINT
MULTIPLY. THE MICROPROGRAM IS
WIDELY SHARED; STAT Yo4 IS NORMALLY
SET FOR FLOATING-POINT.
FLOATING
POINT MULTIPLY
INITIALIZATION
OJ161
X
DI GIT =0 WITH NO
CARRY FROM RI GHT
ADJACENT DIGIT OR
F WITH CARRY FROM
RIGHT ADJACENT DI GIT
FUNCTION BRANCH ON DI GIT
VALUE WITH CARRY FROM RIGHT
ADJACENT DIGIT AS C COND
FETCH LOW HALFWORD OF MULTIPLE SELECTED
ACCORDING TO DIGIT VALUE AND CARRY FROM
ADJACENT DIGIT. SET YCD IF THIS DIGIT> 8 TO
INDICATE A CARRY FORWARD TO THE NEXT DIGIT
AND THAT IF 2 MULTIPLES ARE REOUIRED THEN
THE SECOND IS TO BE SUBTRACTED. SET YO IF 2
MULTIPLES ARE NEEDED.
OJ031
OJ041
11
10
NO SKEW
OFFSET
OFFSET SKEW
ADD/SUBTRACT MULTIPLE
TO/FROM PARTIAL PRODUCT
WITH MULTIPLE SHIFTED
12 BITS LEFT
11
01
SKEW
NO OFFSET
ADD/SUBTRACT MULTIPLE
TO/FROM PARTIAL PRODUCT
WITH MULTIPLE SHIFTED
8 BITS LEFT
00
10
01
00
NO SKEW
NO OFFSET
ADD/SUBTRACT MULTIPLE
TO/FROM PARTIAL PRODUCT
WITH MULTIPLE SHIFTED
4 BITS LEFT
ADD/SUBTRACT MULTIPLE
TO/FROM PARTIAL PRODUCT
LONG
LONG
n
SHORT
~~I
YES
OJ051
NO
----+---
I
OJ041
OJ051
--I
OJ041
OJ071
I
NO
.I
RESET YO. RE-ENTER LOOP TO
ADD/SUBTRACT X6 MULTIPLE
ACCORDING TO YCD
NO
o
_J
>---...,JD
D
NO
1'10
YES
EXTEND SIGN OF PARTIAL
PRODUCT OVER EXTRA BYTE.
SET NO SKEW, NO OFFSET,
SELECTLO DI GIT OF LO BYTE
FOR BRANCHING. USE YI
FOR BYTE CARRY
YES
SELECT XI MULTIPLE. REENTER LOOP TO ADD THIS
TO THE PARTIAL PRODUCT
WITH APPROPRIATE OFFSET
NO
YES
SET OFFSET, NOSKEW.
SE LECT LO DI GI T OF
HI BYTE FOR BRANCHING. USE YI FOR
BYTE CARRY
OJ081
SET EXIT FLAG (Y6).
FETCH HIGH ORDER BYTE
OF OPERAND I TO D. SET
SKEW, NO OFFSET. SELECT
HI DIGIT FOR BRANCHING
OJ061
NO
--+-
OJIII
NO
-l
YES
YES
RESHUFFLE RESULT FRACTION
TO FINAL FORMAT. INSERT
CHARACTERISTIC AND SIGN.
RESTORE CONDITION REGISTER
TO Y2, Y3
SHIFT PARTIAL PRODUCT
I HALFWORD RI GHT .
FETCH NEXT HALFWORD
OF OPERAND I TO D.
SET EXIT FLAG (Y6)
WHE N LAST BYTE IS
FETCHED. SET SKEW,NO
OFFSET. SELECT HI
01 GIT LO BYTE OF HALF
WORD FOR BRANCHING
OJ281
FROM DIVIDE
FIGURE 630
CHECK LS45
FOR OVERFLOW
or UNDERFLOW
NEITHER
TRAP ROUTI NE
OJIII
TRAP ROUTINE
I-FETCH
FIGURE 629. FLOATING POINT MULTIPLY LOOP
FLOATING POINT DIVIDE, SHORT DER DMC SECTION lC6, ROUTINE
09, STOP ON MS 6238
CD
CD
0)
@
EACH DIGIT OF THE QUOTIENT FRACTION IS FORMED BY COMPARING
PARTIAL REMAINDER IN TURN WITH THE X8, X4, X2, and XI MULTIPLES
OF THE DIVIDED. WHEN A MULTIPLE IS LESS THAN OR EQUALS THE
PARTIAL REMAINDER IT IS SUBTRACTED BETWEEN THE FORMATION OF
SUCCESSIVE QUOTIENT DIGITS. THE PARTIAL REMAINDER IS SKEWED
LEFT ONE DIGIT POSITION.
CD
0
0
®
G)
ROS
A56
FPREG 02
45150F75
FP REG 06
42345000
9D6
45150F75
986
45150F75
C REG
150F
DREG
7500
4700
150F
7500
4701
150F
7500
7500
A REG
IA28
B REG
4700
42345000
IA28
42345000
0000
9C9
45150F75
42345000
ODI4
4701
15FB
9E3
45150F75
42345000
068A
4702
07FB
7500
9DI
45150F75
42345000
068A
4703
0171
7500
9ED
bbbbOF75
42345000
0645
4515
0171
7500
9EF
bbbbOF75
42345000
6745
4515
0034
5000
A6F
45671000
42345000
0045
1000
0000
0000
ODD
FLOATING POINT
DIVIDE
INITIALIZATION
FIGURE 628
QJI61
NO
YES
FIGURE 629
SE LECT 8 MULTI PLE. COMPARE
HIGH ORDER BYTES OF MULTIPLE
AND PARTIAL REMAINDER
QJ281
QJ221
PR HIGH
PR LOW
COMPARE
II
10
II
Equal 00
SE LECT 4 MULTI PLE. DOUBLE
QUOTIENT BYTE COMPARE HI GH
ORDER BYTES OF MULTIPLE AND
PARTIAL REMAINDER
PR HIGH
00
4
PR LOW
11
01
Equal 00
SE LECT 2 MULTIPLE. DOUBLE
QUOTIENT BYTE COMPARE HIGH
ORDER BYTES OF MULTIPLE AND
PARTIAL REMAINDER
PR LOW
PR HIGH
11
10
EQUALOOr-------~-----L------__,
SELECT I MULTIPLE. DOUBLE
QUOTIENT BYTE COMPARE HIGH
ORDER BYTES OF MULTIPLE
AND PARTIAL REMAINDER
PR HIGH
II
PR LOW
PR HIGH
INCREMENT QUOTIENT BYTE
QJ221
QJ231
COMPARE REMAINING PARTS
OF PARTIAL REMAINDER AND
MULTIPLE
PR HIGH OR LOW
PR LOW
RESTORE QUOTIENT BYTE
FIGURE 630.
FLOATING POINT DIVIDE LOOP
PR LOW
DO
01
2ND HFWD OF INSN
SKEW
OP2
c:::::±:::: I:::::::+<:I
H
J
YA
YB
FUNC
Yel
TEST UNDER MASK
ROS
REG 6
REG 7
343
360
374
FFFFFFFF
OOOO508C
000060OO
OOFFFFFF
OOFFFFFF
OOFFFFFF
DMC SECTION
A REG
OIAl
olCB
4E24
YCD IZT
I xoox I>
...----4
LOAD INSN ADDP. 10
A REG
LOAD
INSN. ADOR. FROM
LOCAL STORE 10 A
REG.
NO
UPDATE 1N5N. ADOR.
READ FROM MAIN
~~&t.m1ON
REGlmR-l
FIGURE 631. TEST UNDER MASK (QPOOI)
YES
UPDATE INSN ADDR
READ FROM MAIN
STORE
134, ROUTINE 06
B REG C REG 0 REG
0100
1001
0000
0400
040 I
0000
0202
0200
F2FF
DO
01
BRANCH ON INDEX
ROS
REG. 6
304C
7FFFFFFO
3E5
7FFFbbbb
lCB
7FFFFFFI
lEC
800000OO
2ND HFWD OF INSN
H
SKEW
YA
J
YB
FUNC
YCI YCO IZT
01'2
NORMAL
EXECUTE = I
:::J
RS
I 01' Code I
o
7
RI
I
II
R3 I 12
IS
19
02
31
OBJECTIVES
TO ADO THE !ST OPND (IU) TO THE 2ND OPND (R3)
AND COMPARE THE RESULT WITH THE
3RD OPND. (Rl OR R3+ i). DEPENDENT ON THE
OPERATION (BRANCH ON INDEX HIGH OR BRANCH
ON INDEX LOW OR EaUAL) THE RESULT OF
THE COMPARE WILL CAUSE EITHER THE
BRANCH ADDRESS (B2 + 02) OR THE INSTRUCTION
COUNT TO CALL THE NEXT INSN.
!ST OPND
- R! (CONTENTS OF)
2ND OPND
= R3 (CONTENTS OF)
3RD OPND
- R3 IF R3 IS ODD (CONTENTS)
OR R3 +! IF R3 IS EVEN
BRANCH ADO - B2 + 02
COMPARE LO
HFWD OF RESULT
OF OPND.L AND OPNO
2 WITH LO HFWO
OPND 3
•
REWRITE SUM
OF OPND.I. AND
OPNO 2 INTO REG. I
LOW ORDER
RO HIGH ORDER
R! AND R3AOO
OPND .1 TO OPND 2
HIGH ORDER HFWD
II. 0 OPND 3 AND
COMP. IT WITH
RESULT OF OPND !
AND OPN02
FIGURE 632.BRANCH ON INDEX (QE0-4I)
CD
HIGH BXH 06, 08 OMC SECTION
REG 8
A REG B REG
00000001
62CE 6800
00000oo I
62CE OF20
00000001
62CE 0000
8O()()49AC
4E24 3000
172, ROUTINE 08
C REG
6602
0600
6000
3026
0 REG
F2CE
FFF I
7FFF
4180
DO
01
NO EXAMPLE SHOWN.
BYTES 2-3 OF INSN
SKEW
OP2
H
J
c::::::>!'<: I::::::::±<:::I
YA
OOCC
NORMAL - 0
EXECUTE = I
RS
I op Code I
o
7
ys-sn
RI
I
II
R3
B2
15
YB
FUNC
XOIO
o
OJ
YCI
YCO IZT
lXfXIX)
02
19
31
SYSTEM MASK
Ye. 10- INHIBIT DUMP
~.
MI • MASKABLE INTERRUPT
OIJECnVE
TO ALTER SYSTEM MASK PSW BITS ~""7
.1
RfAD SEeON) 0PfRAND FROM MAIN STORAGE
2
PlACE CONTENTS OF 2ND OPND
INTO PSW IITS fJ~7
READ NEW SYSTEM
MASK FROM
MAIN STORAGE
READ CURRENT SYSTEM
MASK TO BREG
Jl
XFR SYSTE M MASK
FROM OIlS TO BlIS
READ INSN ADDR
FROM LOCAL STOR
SH EXTERNAL
MASK
XFR SYSTEM MASK
FROM 0.1 TO Bt>
READ INSN ADDR
FROM LOCAL STOR
SET EXTERNAL
MASK
FIGURE 633 •. SET SYSTEM MASK (OC021)
ENTRY DATA
AI
/II)
I RI
ADM
OF OPND 2
HIGHHfWD
T f"::7'1
81
R3
CO
~0P2 I RI
CI
DO
DI
LOAD MUlTIPLE LM DMC SECTION 12C, ROUTINE 07, STOP ON MS 63CO
!><1>fj
00
AooR Of OPNoI
HIGH HFWo
01
AND NI
2ND HFWO Of INSN
H
SKEW
YA
J
Y8
FUNC
YCI
YCO
oMC
A REG
032C
032C
ROS
349
368
368
IZT
OP2
SECTION 137, ROUTINE 01
OlcO
SI
I op Code I
o
7
I
12
15
01
81
19
31
O&JECTIVES
TO AND, OR.. XOR OR MOVE THE
IMMEDIATE ~TA WITH THE BYTE
SPECifiED BY Bl, 01.
THE CONDITION CODE IS SET
ACCORDING 10 RE~LT FOR THE
AND, OR, XOR OPS. IT IS
UNCHANGED FOR THE MOYE OP
TA8LE 1
STAT SETTING
OP
INDIRECT
FUNCTOI
MOVE
AND
OR
XOR
PASS P
AND
OR
XOR
0
(II
81 REG C210CRX010 11111111
ATf'ONTA
YCO AT
FOINT A
STATS AT
0
~T 8 ~RX01!i'
1
o
QIlI/11I1t1X1IJ
~ STATS AT ~RX01(11
~1~ 000L~
FONTC
CR
(lJQJ0L~
iil
CR
RESULT
= 0(11
RESULT
=01
FROM
2ND lEVEL
INSN FETCH
QDIZ!Jl
SET FUNCTION
REG. 10 "AND"
SET YCO-l
SET 81 = L11L
000
EVEN
USE FUNCTION
REG 10 PROCESS
BYTE IN 01
USE FUNCTION
REG TO PROCESS
&YTE IN D!i'
YES
YES
NO
NO
NO
WRITE BACK RESUlT.
CR· gil FOR AND
OR XOR
STATE RESlORED
FOR MOVE
FIGURE 636 51 OPERATIONS, AND, OR, EXOR, MOVE (QPOOI)
SET FUNCTION
REG TO PASS P.
STORE STATS III
REG 81
>'YE;.;;.S_ _ _ _-,
-----<0
8 REG
0000
OOFF
oFFF
C REG
4003
4003
4001
0 REG
0000
0000
4400
DO
PI
2ND HFWO
OF INSN
H
SKEW
~
J
OP2
va
X010
I
FUNC
Q
NO EXAMPLE SHOWN.
VCI
VCP IZT
I><1 2ND HFW~ OF INSN I
-VA
YI
oocc
XOIO
I
c::
FUNC
YCI
NO EXAMPLE SHOWN.
YCD IZT
I I I I
NORMAL = 0
EXECUTE = I
RS
I op Code I
o
7
RI
I
II
R3 I 12
15
19
31
EFFECTIVE MICRO PROCI\AM ADDRESS
CONTENTS OF 82 + D2
R1 R3' STATS SETTINGS
THIS IS THE SYSTEM
PROTECT
PART OF LOCAl STORE
....~~-I MASK
OBJECTIVE
10 PERfORM THE DIAGNOSE INSTRUCTION
DETERMINED BY HI SETTING OF THE YA AND Y8
STATS
~SW BIT 15 a i2f)
FUNCTION
9)000 0001 XFER LOCAl STORE TO LOCAL SIORE TO ONE EXTENDeD WORD
i2f000 00!l XFER LOCAL STORE TO lOCAl STORE FROM ONE EXTEtaD WORD
0000 1001 CLEAR A LOCAL STORAGE WORD
0100 1000 XFER A LOCAl STORAGE WORD TO BUMP
0100 0000 XFER BUMP TO LOCAL STORE
0100 00!C21 CYCLE A lUMP WORD
0000 0!!0 CYCLE SPLS WORD CPU
£H00 (/IUS!! CYCLE SPLS VtORD MPX
(Al)
(Rl)
YA
YB
•
SET TRAP CODE 2 INTO 81
REG. RESET INHI81T DUMP
LATCH READ EFFECTIVE ADDR
INTO LOCAl STORE LOCATION
08
AX
0 ..3
STORE TAG
Y4
=I (CLEAR)
SET EXTENSION BITS FROM 1ST
LOCATION TO BI REG WRITE
THE CONTENTS OF 5T LOCAT~
TO THE LON alDER PART OF
THE 2ND lOCATION
CYCLE STORAGE PROTECT WORD
OPERATION
READ AGAN MAIN STORAGE TO
READ OUT SPLS STORAGE
SET NEW DATA INTO THE STOIVGE
PROTECT REGISTER.
WRITE BACK TO MAIN
STORE THE CONTENTS OF
FI XED POINT REGISTER
TWO OR FIXED POINT REG
1 IF Y4 = I
NO (LOCAL STORE TO BUMP)
YES
FIGURE 639. DIAGNOSE INSTRUCTION (QS 101)
DO
01
OMC
TR
TRANS LATE
SECTION 183, ROUTINE 02
STOP ON MS 617A
THEN STOP ON MS 617A
SKEW
VA
J
H
• !
0P2
CO.
A REG
6A68
6868
6798
C7C
6868
ROS
CI8
C70
2
8 REG
0000
0068
0098
FF68
ss
I OP Code I
o
7
L
I
15
I
81
19
01
I
31
82
I
35
02
47
OBJECTIVE
BYTES OF THE FIRST OPERAND, ARE
USED AS ARGUMENTS TO REFRENCE THE
LIST DESIGNATED BY THE SECOND OPERAND
ADDRESS. EACH RESULTING FUNCTION BYTE
REPLACES THE CORRESPONDING ARGUMENT
BYTE IN THE FIRST OPE RAND.
/
/
FROM 2nd LEVel
INSN FETCH
/
/
/
/
/
/
/
QP9}bl
- -- -
OP~71
- -
- - -
/
--./
INSN
FETCH
OPf/lH
QD!Il-r-==.:;
I
:r:~~~tl START
1 III • FELO SEPARATOR
U • MESSAGE NSERT
IL _ _ _ _ _ _ _ _ _ ..JI
SH2
FIGURE 643 EDIT, EDIT AND MARK (QP09I, QPIOI, QP121, QP131, QP141)
0 P 121
(SHEET
SH2
1 OF
2)
C REG
66C0
F040
F040
4().4()
4().4()
0 REG
666C
OF
8FBF
OF
4().4()
r---,
I
I
QP101
I
SHI
SHI
I
I
t
Y2
~
I - LAST CHAR OR 000 START CASE
~ MARK
Y3 -I-EDIT
Y4 : 1 - MARK fLAG
YS = 1 ~ CURRENT PAT r~RN ADOR ODD
Yo ~ I - S TRIGGER ON
Y7 - I -RESULT fiELD NON ZERO
"'' '
01
lGl
FIGURE 643, EDIT, EDIT AND MARK (QP091, QP10l, QP121, QP131, QP141)
(SHEET 2 OF 2)
OBJECTIVE
THIS SUBROUTINE IS USED fJ'( THE EDIT MICROPROGRAM TO FETCH
UP 10 4 DtGITSFROM THE SOURCE FIELD. THE FORMAT OF THE
DIGITS IS CHANGED FROM PACICID TO ZONED. THE DIGITS ARE
PUT IN A IDCAL STORAGE BUFFER FOR USE WHEN REOUJREO
IN THE MAIN EDIT LOOP. SPECIAL CODES ARE SET IN THE
BUFFER FOR SIGNS OR INVALID DIGITS.
READ 4 SOURCE DIGITS
IdiJIdlld21dli
FROM MAIN STORAGE
TO REGISTER D.
U't».TE SOURCE ADDRESS
USING REGISTER C
NO
YES
PREFIX DIGIT dl WITH ZONE
WORD
d2
TO IDCAl STORE LOCA TlON
(//S.2)
YES
FIGURE 64<4 SSEOll. REFill ( QP 091)
DO
01
MOVE NUMERIC
J
H
SKEW
OP2
I
VA
4
ROS
CO2
CB2
CBE
C7C
SS
lOP Code
o
I
I
7
15
BI
I
19
01
I B2 I
31
35
02
47
OPNO 1 = OEST
OPND 2 = SOURCE
OBJECTIVES
FOUR BITS FROM EACH BYTE OF THE SECOND
OPERAND FIELD. REPLACE THE CORRESPONDING
4 BITS IN THE FIRST OPERAND.
FOR MOVE NUMERIC THE LOW ORDER 4 BITS
ARE USED, FOR MOVE ZONES THE 4 HIGH
ORDER BITS. FOR OVERLAPPING FIELDS
MOVEMENT IS LEFT TO RIGHT THROUGH EACH
FIELD, ONE BYTE AT A TIME.
SET INDIRECT FUNCTION FOR
MASKING OPERATION 'ANO'
FOR MOVE NUMERIC 'ONP'
FOR MOVE ZONE
OVERLAP IS DEFINED AS
DESTINATION ADDI\-SOURCE
ADDR + L IN THIS CASE BITS FROM
THE FIRST SOURCE BYTE ARE
PROPAGATED THROUGHOUT THE
DESTINATION FIEL
YES
NO
OP¢41
OPj51- - - - - - - - - --
------l
:- - - - - - - - '---------1
I
I
I
I
I
I
I
COUNT= Cb
I
I
I
r---------- __ L_ -
NO
r------I
I
I
.L.1
QP¢51
____________________ ..1.I _ _ _ _ _ _ _ _ _ _ _ --,
OP¢ J1
0r-;::::::=:::::::.t,.---,-___~
FIGURE 647 SS LOGICAL OPERATIONS - MOVE NUMERIC, MOVE ZONE
I
- - -- ---- - ---
DMC
SECTION 170, ROUTINE 01, STOP ON MS 6108
A REG
6978
6978
6958
6958
B REG
0000
0000
FIOO
0001
C REG
6958
697A
69FF
6901
DREG
FIFI
FIFI
0000
0100
ENTRY DATA
NJ
Al
lAbOR OF OPNo 2
HIGH HFWD
SKEW
CO
Cl
AooR OF OPNo 1
HIGH HFWD
J
H
!
0P2
81
10
YA
c::::::>i' 8
CHARAClllIS
DIGITS + $)
4
I
I
REMAINDER
¢9 -9
1
21
1_- . _ _
I
7
9
9 S
.. I
3
7
9
2 {II
I
OPI
I {II(II:--__
REM.
{II9a,_4,J.I,S-I __ ua
GENERATE
9
QDlCilT9
3
7
2 \II
4
.!.......!..1J
9
S 9
3
7
!6
4
I
{II
1
!I
9
3
4
9
!..2J
3
7
I
'1
2
\III
4 CHARACTlRS 3 CHAMellRS
(7 DIGITS+S)
(5 DIGITS+$)
EXIT:
SO
-a··2t'tl
L. STOR
IVTE 9,2
GENERATE
ODIGITf
SO
GENERATE
Q DIGIT 4
L. STO:
IYTE
4
SO
Q DIGIT J
GENERATE
- 2 tit I
2 2
-2-2-2+1+1
-2+1
SO
GENERATE
Q DIGIT 1
~-2- 2-2 -HI + I
L STOR
IYTE ..
GENERATE
Q DIGIT S -2-2-2+1
'L STOR Q
IYTE S+
NO
PUOTIENT
S {II
.!..!..!J 7
t,II !6 .L!
t,IIl
GENERATE
Q DIGIT a
7
I 1
{II 1
- 2 -2 -2 -2 -2 +I
SO
491 so
-{II¢..i.,
I 1 4 9
...fi9 3 7
I
l ~ -- - - - - - - - -
SO
4
I
QUOTIENT
TRIAL
SUITRACT
2
!...!.J
S 9
I
DIVISOR
9
!I
(II
1_ - - .- -
4
2
9
9
MULTIPLES USED
10 FORM
QUOTIENT DIGIT
!6
I
I
11-
_ _ _ _ _ 11
.!.I
...!
17---1
I I
19999111
199991
I
1 1
I 1
1 I
2 {II
9
QUOTIENT
I
I
;, 4
SKEW
IN L. STORE
"/OR SEOUENCE
(eVTES ADORD.
OFFSET
UNDERLINED
4
9a{ll4!IS
92
PARTIAL REM
SO
OP.
EXIT
IcoMPLETm
ATTACH SIGNS TO
THEN MAIN STORE
TO
ORlbl
a
a
AND REM,
AND REI'!.
NO OFFSET PATHS
ADORES SING
L2
t
R
D
D
PART REM.
IS
R
R
R
R
R
R
R
R
D
D
D
R
R
I
I
(
NO OFFSET
NO SKEW
L2 EVEN
) (
I
I
I
D
D
D
R
R
R
:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
D
R
R
R
D
I
NO OFFSET
NO SKEW
L2 ODD
I
I
I
D
R
R
R
R
R
R
R
R
R
R
R
R
R
I
DECREMENT
NOA~,
I
(
NO OFFSET
SKEW
L2 ODD
I
I
I
I
I
~,~~m
I
ADD OR SUBTRACT
PENULTIMATE BYTE
ADD OR SUBTRACT
PENULTIMATE BYTE
WRITE DIVISOR BYTE
WRITE DI VISOR BnE
WRITE 0 IVISOR 'BYTE
NEXT BYTE
WRITE D IVISOR BYTE
TO l.OCAL STORE
TO LOCAL STORE
TO LOCAL STORE
ADD OR SUBTRACT
ADD OR SUBTRACT
ADD OR SUBTRACT
FINAL BYTE
FINAL BYTE
PENULTIMATE BYTE
ADD OR SUBTRACT
READ NEXT
REMA INDER BYTES
TO A REG.
'0'"
I(INITIAL)
ENTRY TO
OF FS ET
WRITE REMAINDER
BYTES IN
LOC A L STORE
.D
D
D
D
D
D
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
I
I
I
I
OFFSET
SKEW
L2 ODD
OFFSET
NO SKEW
L2 ODD
I
I
I
R
R
R
R
R
D
R
R
R
D
OFFSET
SKEW
L2 EVEN
R
R
(
I
I
I
OffSET
NO SKEW
L2 EVEN
I
I
I
I
I
I
WRitE REMAINDER
BYTE S TO
WRITE REMAINDER
BYTES TO
WRITE REMAINDER
BYTES TO
LOCAL STORE
LOCAL STORE
LOCAL HORE
READ NEXT
REMA INDER
BYTES TO A REG.
READ NEXT
REMAINDER
BYTES TO A REG.
READ NEXT
REMAINDER
BYTES TO A REG.
ADD OR SUBTRACT
PENULTIMATE BYTES
ADD OR SUBTRACT
FINAL BYTES
ADD OR SUBTRACT
FINAL BYTES
NOT
SKEW L2
ODD ORE
yrfJ YS
R
R
I
WRITE REMAINDER
WORD iN LOCAL
STORE
OOD
R
R
I
I
I
(
PART REM.
I5
R
R
I
I
I
I
/
r--0""'" . . ,
D
I
I
ADD OR SUBTRACT
BYTEl AND FOLLOWING
ODD BYTES
WRITE
DIVISOR MULTIPLE
IN LOCAL STORE
IN PAIRS UNTIL COUNT- 4>
.ocmID
THEN EXIT DOWN
PATH
APPROPRIATE TO REMAINDER
BYTES AND DIVISOR LENGTH
IN LOCAL STORE
D
I
I
I
I
I
I
I
I
(
D
DIVISOR
D
I
I
ADD OR SUBTRACT
BYTE ¢ AND FOLLOWING
EVEN BYTES
WRITE DIVISOR BYTES
TO LOCAL STORE
ADD OR SU BTRACT
BYTE 1 AND FOLLOWING
ODD BYTES
READ DIVISOR MULTIPLE
FROM LOCAL STORE
D
PASS
;:
NOT
LAST PASS
LAST PASS
R
R
R
D
I
(YCD)
ADD OR SUBTRACT
FINAL BYTE
R
R
R
COUNTER IN BL
I
ADDRESSING CASES (LOCAL STORE)
L2 EVEN
L2 ODD
ADD OR SUBTRACT
BYTE ¢ AND FOLLOWING
EVEN BYTE S
READ DIVISOR
BYTE TO 0 REG
D
LAST PASS
TO LOCAL STORE
DECREM ENT BYTE
COUNTER IN REG. &1
READ OUT
PARTIAL REMAINDER
BYTES
D
I
NO OFFSET
SKEW
L2 EVEN
ENT RY
'I
L2 ODD
D
DIVISOR
8
~VEN
OFFSET PATHS
I
Fk"'O""
QIUS!
CASES (LOCAL STORE)
EVEN
ADD OR SUBTRACT
ADD OR SUBTRACT
FINAl BYTES
FINA L BYTE
~
db
ORD SQ
PART REM PLUS
(] ~,,~,~,~,~,:.~,:,:,,~ ,:.~o ~,~ , -, :,~ .-,:
DIVISOR MULTIPLES ADDRESSED BY H REG. AND HELD IN DREG.
DIVISOR LENGTH COUNT HELD IN BJ. REG.
QUOTIENT DIGIT FORMED IN B ¢ LOW ORDER .. BITS
FIGURE 652 DECIMAL DIVIDE ADD/ SUlTRACT PATHS (QRI41)
SQ
PART REMrPUJ~
ANALYSE RESULT AND SET
UP FOR NEXT IX MULTIPLE
OR 2 X MULTIPLE OR
START NEXT Q DIGIT.
NOTE.- TO DISPLAY EIGHT ADDRESSING CASES
WITH CLARITY, BOXES HAVE Sf EN
REPEATED AND BRANCH SHARING IGNORED.
-0
DAD
ORDSQ
PART.EM PLUS
OR MINUS
T
t
8
00
H
SKEW
C><1
4
!
4
0
YA
YB
OOCC
0000
01
FUNC
YCI
YCO
DECIMAL MULT1PLY OMC SECT10N lE8, ROUT1NE 02, STOP ON MS 6192
ROS
A REG
B REG C REG
DREG
E02
6790
COOO
6771
F790
E06
678E
OOOC
670C
5C01
E3B
6787
0020
FOOC
0000
E47
6771
0300
IOC2
0060
E62
6771
5C00
0700
005C
EB2
6771
0700
0020
5COO
En
6771
0200
07FB
5CEO
4F7
6771
025C
025C
025C
I
III
C>8
OR321
OR331
.----------------;~--------CD
NO
DIGIT RECODE TABLE
. [6$)
Y4 Y5
Yb
Y7
SIGNS SECOND CARRY YB
EFF
DIGIT 1st 2nd CYCLE
- UP
(2)
- *0
{/)
¢
(2)
{/)
1
(2)
2
2
0 QI
1
-
J
(l)
1
1
4
(2)
(2)
-
¢
1
5
b
7
B
q
**A
B-F
1
1
1
1
(2)
(2)
0
1
1
1
-
0
- -
-
-
- .
¢
¢
b
(2)
(2)
1
1
1
q
1
1
1
E
F
q
-
INVALID
!If ¢ INVALID IF CARRY
**
OR 351
~
~:':"--"":":~i--'-"...,..-"-'-t
1
}
I-"::::'=~:":":"::'::::"':'::::':::':':''':''''-~~ 2
4 J
'------------'
ADD OR SUBTRACT LOOP
FORM PART1AL PRODUCT
IN LOCAL STORE BY ADDING
OR SUBTRACTING LX OR 4X
,~--------------l MULTIPLES.WHEN MULTIPLE IS
EXHAUSTED CARRIES AND
BORROWS ARE PROPOGATED
FROM PREVIOUS DIGIT
A INVALID IF CARRY
FROM PREVIOUS DIGIT
,----
----0
OR3bl
I
I
I
I
NEXT MULTIPLE DIGIT
NO
---
I
I
I
.--____---,-,.,...L___-..,.,..,........
STORE PRODUCT IN MAIN
STORE USING J AND Y7 FOR
PRODUCT CNT. H.ADDRESS'S
PARTIAL PRODUCT
I®flGlJRE 653
DECIMAL MULTIPLY
0 R3 71
ENTRY DATA
I ADM
NJ
(j!
PLUS l2
co
Al
CI I
ADDR OF OPND
PLUS LJ
OPND 2
c::?±<:J
PACK
DMC SECTION 181, ROUTINE 02, STOP ON MS 622C, THEN STOP ON
MS 6202. THIS WIll INSURE THAT THIS IS THE FIRST PASS THROUGH THE lOOP.
ROS
SKEW
..
H
.
o
YA
YB
OOCC
0000
FUNC
YCI
YCO IZT
C>
SOURCE
UNPACKED
L......;...JL-..;...JL-"'-''-......
REVERSE DIGITS Of DESTINATION
BYTE AND U~TE DEST A
DEST
Pl'.CKED BCD
READ OUT FI RST DEST BYTES
NO
YES
READ NEXT ooT WORD AND
UPDATE DEST ADDRESS
11
FIGURE 654 DECIMAL PACK (QRIOI, QRlll)
01
ENTRY DATA
NJ
Al
ADDR OF OPND 2
PLUS L2
SKEW
1><1
CO
11
L2
I
!
•
2
1
PLUS Ll
H
4
Cl
tOOR OF OPNO
0
0
I
I
YA
YB
OOCC
0000
FUNC
YCI
UNPACK DMC SECTION 181, ROUTINE 01, STOP ON MS 6OE., THEN STOP ON MS
618A. THIS WILL INSURE THAT THIS IS THE FIRST PASS THROUGH THE LOOP.
YCD lZT
C> 1 ~ 1 FOR ASCII
DATA FORMAT EXAMPLE
DESTINATION
ZONE -1111 EaDIC
ZONE' .1t>1 ASCII
SCOURCE=OPND 2
DEST. =OPNDl
STAT USAGE
H SCOURCE IIYTE POINTER
Vb DEST. BYTE POI N TE R
Y7 END OF SOURCE MARKER
ZERO
ZERO
ZERO
FIGURE 655 DECIMAL UNPACK (QR10l, QR121)
B REG
3010
1000
0000
FOEO
C REG
6500
65CF
6SCC
6SCF
DREG
2000
EFOO
0000
FEFO
ENTIV OATA
NJ
T
I lOOR OF OPND 2
AI
co
CI
AOOR OF o;NO ,
'PLUS LI
II
PLUS L2
SKEW
1><1
VA
H
" !
2
"
"
OOC:C
MOVE WITH OFFSET MVO OM( SECTION 17C, ROUTINE 10, STOP ON MS 658£
VI
FUNC
VCI
ROS
COl
855
868
8.-1
VCO IZT
I><1
CO
II
I0P2T
0
l21
. !
. !
2
c:?+<=1
PWSLl
J
H
CI
ADDI a: atNb 1
0
0
VA
VI
OOCC
0000
FUNC
DECIMAL
VCI
DI
t 1235t
31
VCD
IZT
I>----,
IDQ
TEST
00
SIGN OF OPND!
0,...1_ _ _ _ _ _ _ _ _ _ _~--__:_:::_=<.: AND TEST FOR ADD
11
10
01
11
OPERATION
SE T UP OPND 2 LOC AL
STORE COUNT IN Bl
fETCH FIRST BYTE OF OPNDI
FROM LOCAL STORE
INVALID DATA
(I DO)
FIGUIIE 658 55 DECIMAL LOAD OPND 1 (ADD, SUBTRACT, COMPARE) (QDI31, QROOI )
DMC SECTION IE2, ROUTINE
A REG
(£67
69AE
69A8
(£67
FIGURE
D2
ADO FIGURES 658 , 660, 661
MS _A
>--------.,
100F
lOEF
4000
OOOC
0000
0000
0000
0000
ICFF
1010
1010
ENTRY DATA
AO
Al
ADDR OF OPND 2
PWS l2
I
~o
DO
Cl
01
ZERO AND ADD ZAP
C><1
H
!
4
o
4
2
YA
Y8
OOCC
0000
FUNC
YCI
YCD
IZT
DMC
SECTION lE5, ROUTINE 01, STOP ON MS 6OFO
A REG
6<4A8
6<4A8
6<4A8
6<4A7
ROS
Cll
E81
EA2
028
8 REG
8000
OFOO
OFOO
OFOO
C REG
6-488
6-488
6<4A7
t>4F0
SS
I op Code I
0
7
II
!L2 I
11
I
81
01
I
82
I
02
47
19
15
OPND 1 = DEST
OPND 2 = SOURCE
OBJECTIVES
FROM
INSN
FETCH
TO CHECK FOR OVERlAPPI NG FIELDS, PROCESS THE
SIGN OF OPND 2 AND PROVIDE ENTRY TO SS DECIMAL
MAIN ADD LOOP (FIG bbO)
00131
INVALID O'IERLAP CASE
OP1 _ _ _~1s~1
.1
SET UP lENGTH COUNTS
ADDRESSES AND STATS
i
OP2 _ _ _ _ S....
FORM ADDR OF OPND 1 ADDR OF OPND 2
+ lENGTH OF OPND 2
(l2 )
TEST FOR THE
LENGTH OF OPND 1
FI ELD IS GREATER
THAN THE LENGTH
OF OPND 2 FIELD
YES
NO
SET YBzll~0
IFMINUS
SET YP>=1000
IF PLUS
DATA
TRAP
Il>Il>
01
10
Y4
PROCESS ONLY
SOURCE BYTE
PI¥XESS SOURCE
I!t1£ AND FETCH
NEXT SOURCE BYTE
FROM MAIN STORAGE
TO
TO
OR~1l
FIG bbO
FIGURE 659 SS DECIMAL LOAD ZERO AND ADD ENTRY (OR041)
DATA
TRAP
OR011
FIG bbO
0010
PROCESS ONLY
SOURCE BYTE
OR011
FIG bbO
TO
TO
OR011
FIG bbO
OR01l
FIG bbO
DREG
F<4A8
6<4A8
OCOO
OCOO
OBJECTIVE
TO SIfOW THE METHOD OF PROCESSING FOa THE DECIMAl.
OPERATIONS ADD, SUBTRACT,COMP, ZERO AND ADD.
(FOR THE OVERALL FLOWCHAltT SEE FIGURE 657)
(See Figure 658 for program)
SETTING OF YB STATS
1100 FOR ADD
1000 FOP. SUBT
0000 FOR COMPo
OPND 1= DEST
OPND 2 = SOURCE
: > - - - - - - - - - -..... ----0
ZERO
FROM
QR041
FIG
9
TO
QR031
FIG
FIGURE 660. SS DECIMAL LOAD OPND 2 AND PROCESS (ADD, SUIT ,'COMl, ZERO AND ADD) (OROII)
(See Figure 658 for programl
OIlJECTIVE
TO STORE RESULT OF THE DECIMAL ADD,
SU8TRACT OR ZERO ADD IN THE MAIN
STORE LOCATION OF OPND.l AND SET
CONDITION REGISTER ACCORDING TO RESULT.
FROM
FIG bl:f:)
NEG. RECOMP.
11
i!ERO RESULT
POS INSERT SIGN
SET YIP =1
=
12
iERO RESULT
POS INSERT SIGN
SET YcJ> = 1
=
12
INSERT NEG
SIGN = 13
SET YIP = 1
Y3 =.l
INSERT POS
SIGN
12
SET Y~ =.1
Y2 = 1
=
Y6
ODD
YES
LA ST
BYTE
~~------------------------~~<
TO
INSN
FETCH
FIGUIf 661. SS DECIMAL TERMINATE (ADO SUlTRACT AND ZERO AND ADD) (QR021)
ERROR
TRAP
DEC
OFtO
ADDR
DECIMAL COMPARE
STOP ON MS 6CFO
I
ROS
CI3
D7E
D18
D3C
OBJECTIVE
TO SHOW
THE
EXIT
TO
SETTING OF CONDITION
SS
DECIMAL
I
FETCH AND
REGISTER
FOR
COMPARE
SET CR=i¢!
FIGURE 662 SS DECIMAL COMPARE (QRooI)
DMC
A REG
6358
6348
6356
6116
SECTION IE4, ROUTINE 01,
• REG
9000
OfOf
0f00
Of00
C REG
6348
6346
00f0
0018
DREG
f358
DCoo
00P9
(710
I
OBIOI
(c
~~e
Purposes:
1. Identify Operation
2. Identify Channel,
Control Unit and I/O
Device
I II o;;l------>~~1
~
~~::~;~ct;on
Readout Start
Ignored
5
BI
12 low-Order xxxx xxxx xxxx
Bits of R
Add literal value of 01
field to obtain channel and
Control Unit and I/O Device Addr
Unit Address
Key
~Mach~:
C
Chk
II
I
0
T
B
Program
Yes
__
I
.-J
fie Id to content of General
Register specified by BI
Channel P.cIdress
Storage
Protect
Errol'S in CAW or CCW format
or addressing will set Y5
to indicate Program Check
\
Check on Start
I/O
01 Uteral Value xxxx xxxx xxxx
A
1
Progrom
Check.
1.
Invalid
CCW Address Specification
2. Invalid CON Address
3. Invalid Command Code
4. Invalid Count
5. Invalid CAW Fonnat
6. Invol id CCW Format
7. Invalid Data Address
~-....:..::=<
Interface Free
>----,
Errors in Unit or channel status
or Command Immediate and
not Command Chaining Flog
Note beginning here
all interface line names
are underlined
Enter Mpx channel
microprogrom to store
remaining UCW into
M x Store (sub chan)
Operational In
Should now be up to indicatethatthe Control Unit
has captured the channel
Purposes:
1. Identify Main Storage
Protect Key
2. Identify Location of First Channel
Command Word (CCW) in Main Storage
C
Channel Errors
IF
Ply
Chk
IF
Tag
Chk
Mpx
I/O
Mode
Chan
Data
Chk
Chan
Ctrl
Chk
I
C
C
D
Purposes:
I. Specify Command
2; Identify Main Storage Location
(Dota Address) of First Data Byte
3. Specify Number of Data Bytes Involved
in the I/O Operation
4. Indicate Action to be Taken upon
Completion of the Command
Will later be used to tell
channel that entry loop was
from Start I/O instruction
rather than Command Chainin&
Some of UCW is put into
local storage to allow
subsequent use of already
available microprogram steps
Generate some of the
Unit Control Word (UCW)
in Mpx Storage and
some of it in the working area of local storage
Sasic I/O Sequence
1. Initial Selection
2. Data Service
This figure shows this port of the basic I/O
sequence.
Operational Out
2. Setting of the Interrupt Code
3. Ending Procedure
3. Storing of the Channel Status Word
4. Interrupt Sequence
4. Setting of the Condition Code
A
No
Bus In
C
Select In
D
6. Branch to Next I-Fetch Routine
Operational In
G
Address In
H
E_ _ _ _ H
LandF
F
E__ J
F_H
I __ G
Command Out
FIGUlE 665. START I/O INSTRUCTION (MULTIPLEX CHANNEL) SEE FIG 667 FOR DETAIL
S~s
D_ _ _ C
D
Select Out
Start I/O
Add...,!!ss
Address Out
5. Branch to Program Trap Routine
7. Interface Lines used during
~mand
~
Bus Out
1. Logical Sequence
Status In
K
Service Out
L
K_Kand
3
2
4
Condition Code Setting on Multiplex Halt 1/0
Cond
Code
Action on CSW
o
Unchanged
A
Unit Status only is
stored.Channel
Status is zero
Test
1/0
9D
Start
1/0
9C
Test
Channel
9F
Halt
I/O
9E
Channel and unit
status is zero
Unchanged
_ .J! 1--= ~L!CJ:!_
B
No
interrupt
Channe I Busy or Channe I
not busy but control unit
busy
Channel and Control
Unit not busy (Normal
CU), or: Channel not
busy - device is stopped
by HIO command
(special CU)
Invalid Channel or
UCWaddress
Unit does not reply
3
Read Part of
PSW from
LS44
Channel busy with
Condition Code 2 is not set on the
Multiplex Channel Halt I/O
2
System Mask, Key
and AMWP
Notes
Unchanged
to initial selection - it
is stopped the next time
it requests service
Yes
Monitor
State
Set Interrupt
Code 2
In BlPrivi leged Op
Set YA ~
Channel #
Set YB ~
Instr Code
Op Code Set
to Stats
Program
Set Condition
Code 3
Trap
Routine
C
QC161
SC
Set CAW
Address in A
- Re-;;-d-UCW4-
Channel
Operation Code
Next
I-Fetch
Mpx or
SC
Set Up Mpx
Store Address
Using Unit #
QDOOI
Yes
D
Set Condition
Code 2
Next
I-Fetch
Code 1
Set Condition
Code 1
Set Condition
Code 0
Next
I-Fetch
Next
I-Fetch
Next
I-Fetch
Set Condition
Set Condition
Code 3
Next
I-Fetch
QDOOI
QDOOI
Test Op
Code Nonzero
TIO
Mpx
UCW
Not Busy
Fig 667
Set Condition
Code 2
Fig 668
Reset Y4
Set YO
Set Conditian
Code to Zero:
Yes
Next I-Fetch
QB121
Set ADR-O
Set Y4
.....-_-'-_--. QB121
Wait Up to
81ms for
Interface Free"
If Exceeded
Set ICC
Sheet 2
FIGURE 666. 1/0 CODES, COMMON DECODING; TEST CHANNEl AND MPX HALT 1/0 (SHEET 1 OF 2)
no
Mpx
End
Reached
Select Unit
Fig 668
Next
I-Fetch
(SEL -I)
Yes
No
Reset YO
After Test
:.\DR-I
or
STA-I
ADR - I
QBI71
CL ___ CH
Set Count zero
Flag in UCW4
Unit Status
to 01
O---SLO
Reset Select Out
QBISI
Unit Number
to BI
Unit Status
From 01 to CI
Set Condition
Code to 3
TlO Byte
(zeros) to
Read Out FI ags
and Op Code
from UCW4
QBI91
Bus Out
Set HIO
to Stop
Unit
Set A = 44
(Status Part of
QBI91
Revalue MI
Place Instruction Count in
ARe
!::..SW) _ _ _
Place Channel
Status in BI
Un it and Channe I
Status ta 0 Reg
Next I-Fetch
Set CC to I
Wri te Status
in CSW
Channel
Select Multi lex
CD = I
CB =13
HIO
Control Unit
HALT I/o
FL
ADR-O
Bus Address Out
HALT
Not OP-I
FB 021
OP-O POWERED
Start I/o Objectives
Figure
Objective
666-1
1. Test for UCW busy.
667-1
2. Fetch CAW.
3. Fetch CCW.
4. Begin initial selection.
5. Store partial UCW (UCW6 and UCWS).
6. Complete initial selection.
667-2
7. Exam i ne status.
S. Subtract I from count.
9. Test for burst mode.
669-1
669-4
10. Add I to count.
11. Store remaining UCW into multiplex storage (Y4 on).
667-2
12. Set conditi on code.
13. Next I-fetch.
FIGURE 666.
I/o CODES, COMMON DECODING; TEST CHANNEL AND MPX HALT I/O (SHEET 2 OF 2)
FF
From Fig 666
SIO
Fetch
CAW
Condition Code Setting on Start I/O
Cond
Code
Action on CSW
Notes
from
Unchanged
Operation Successfully Initiated at
the Device
CSW Stored
TIC on SIO - Program Check on SIOControl Un it Busy - Command
+lmC'~ediate Errors -Interrupt Conditions
A
1--_+_____
Unchanged
Path Busy
Unchanged
Channel or Device Unavailable
QBIII
QBI31
Call Storage to Read
Out First Halfword
of CAW
Prevents RQJ
Obtaining Selection
01
II
10
Increment CAW
Address +2
Call Storage to Read
Out the 2nd Half Word
of the CAW
from fig 670
Command Chaining
Fetch CCW
F;:;" QA251forMpx Channel
Y6 = 1 on Entry
Move the Command
Code and Top 8 Bits
of Data Address in
_ !LR~st~ _
Increment CCW
Address +2 to Read
TIC During
Command Chaining
the Lower 16 Bit
of Doto Address
C
Set Condition
Code I
Set A = 44
CSW Status Adr
Set Prog Ck
Ba MS44
Call Storage to Read
Out the 2nd Half
Word of the CCW
Put the Full Data
Address in lS09 Via (
Transfer IC to A
Restore CPU Key
and Command
Byte from Cl
If SIO Set Byte I of
LS48 to FF
QBI51
O_SLO Reset
Select Out
00
D
Set Channel and
Unit Status
_ _ i~D..!~_
lO
_~d~t~~_
Set UCW
Address In A
Wait for Fall
of STA-I
QBI31
II
10
QBI91
Bits
4 and 5 of
Command
Code
Set A = 44
CSW Status Address
- sto";iJ~t ~nd- Channel Status
in MS 44 and 45
- $;t Condit~n
Code I
00
01
Set Channel Key
in SP Data Reg and
Store in SP
-Ci;.r Mp;UCWin
LS26, 27, 29
Clear Channel
Revalue MI
----Trander IC to A
Restore CPU Key
The Next CCW Must be Fetched
at the Addr Given by the CCW
Specifying TIC
Next
I-Fetch
QOOOI
Operati on Code
to Flags in BO
Add 2 to Operation
Code if Skip Flag
Present
QSI91
SetA=44
CSW Status Address
Set Condition Code 1
Store Program Check
Bit Only in MS 44 & 45
Write or
lOl Rd Bkwd
010 Control
110 Rd Skip
100 Read
Sense
111 Rd Bkwd Skip
Clear Channel
Revalue MI
Transfer IC to A
Restore CPU Key
Next
I-Fetch
G
QDOOI
FIGURE 667. START I/O MICROPROGRAM MPX CHANNEL (SHEET I OF 2)
Increment CCW
Addr +2
Write CCW Address
in LS08
Move:
Mpx Store
Address from LS07
to LS27. Next
CCW Address
from LS08 to UCW6.
Count from
LS06 to LS29.
Data Address
from LS09 to 26
7
From Fig 667
Sheet I
Test
A
r--------------------r--:--~( for Status Non00
Zero and Prog
Ck
ALU
F0
11
01
Y5
SVC-O Accept
Status
-----Wait Up to 40!-'sec for
SVC-O to Fall
CDA Flag
If Exceeded
Set ICC
Yes
No
CC Flag
No
Yes
Yes
Channel
End and Device
End
11
No
TlR
Yes
C
Subtract 1 from Count
Set Y4
Set A
=
Data Address
Set Mpx Storage
Address in J
QA091/QA191
1--
---,
I Enter Mpx Read or I
I Wri~~e~tar ~;g4 669 I
L--I--~
1--
---,
I
Enter Restore
I
I Microprogram Fig 669 I
L~=-t 4 ~4_..-J
D
From Fig 669
Sheet 4 of 4
SVC-O Accept
Status
Subtract 1
Wait Up to
from Count
4OI-Isec for
Set Data
SVC-O to Fall
Address in A
If Exceeded
Store Flags and Op
Set ICC
Transfer
Ie
Code in lS29
Set J Reg = 27
to A
Restore CPU Key
510 Cleared Status
from Unit
QDOOI
NIF
CSW Status Addr
Store Unit and
Channel Status
in CSW
Set Condition Code 1
CL - CH
Revalue MI
Transfer
Ie
to A
QA131/QA251
I-~ter S~;--I
I
1.--]----,
I
I
I
Enter Channel Status
L
Microprogram
--I-Fig 670
I
Microprogram
Fig 669
L_S~et4~~_
Restore CPU Key
Next
Continue
Interrupted
Microprogram
FIGURE 667. START
I/o
MICROPROGRAM MPX CHANNEL (SHEET 2 OF 2)
J
I
rEnt; Mp:"Re-;tor;-l
I
QDOOI
I-Fetch
I
Loop Fig 669
L~!::.et3~~_J
I
J
4
3
2
From Fig 666
From Fig 666
Test I/O
Mpx UCW
Not Busy
OB601
Test I/O
Mpx End
Reached
OB601
A
YOCIOI
YOCIOI
Read Interrupt Buffer
Read Interrupt Buffer
_ _ fr~, ~2~ _ _
from LS2A
R:;'d"M; 5;;,r;U;;;t
from UCW 2
Clear CO if no
Unit # Equals
Buffer Unit #
Prevents TI 0
-
Device Sending
Status in Unti I
Device Selected
(
I
No~>-y_e_s
I
_______- ,
Bfr #
Set YI to Signify
No
r_
~-------
~ Reje.=!:~ _
no Unit
Status Previously
Accepted and
Located in UCW 2
Clear CO
ADR-I
ADR-I or
STA-I
J
OBI91
C
Next
I-Fetch
ODOOI
Interrupt Pending
\
Interface
Free
Reset IR Latch if Set
by TI 0 0'0 Entry
STA-I
Set Condition Code 2
----Set Instruction
\
Unit Status
he; Been Rejected
and Stacked in
Unit Since Other
Unit
Unavailable
Set Condition
Code 3
Subchannel
Count in A
and Set ADR-O
With Unit #
on Bus Out
Yes
Unit on a Shared
OBI21
Set Select
-W-;;it fur i;tfFre;--
r----
End for a Different
No
Yes
Unit Selection
( If Time Out'\
Set ICC
After End Reached
~
UCW
Unit # = no
Unit #
TIO and Allow
Exit After
I
B
Located in Data
Address Location
~
~es Set Y7 to Signify
OCIOI
~
' - -_ _ _ _ _.....J
0: ..
"
1
I _ r - -----<;,.N
IR
- - _ Set IR Latch
71
Test for Allowable
Interrupt. If
Allowed Set PRI
OBI21
i-
o _IR
r -Reset
- -Interrupt
----
Compare Unit # Sent
With Unit # Received
Req uest Latc h
OCIII
Unit #
Sent = Un it #
Next
I-Fetch
ODOOI
H
ISO - Inhibit
Select Out
)-'-N.::o=--_ _--;
I
Received
ClearUCW~_
Control)
,-.::.Un.::.i.::.t.::.Bu:..:sy~
Set CMD-O
With All Zero
Command Byte
From Mpx Store
to LS08-0C
and LSOA . ; - - -
Set
ICC
OBI51
Yes
1------Transfer UCW
CL-CH-Clear
Channel
r.-------Reset Sel ect Out
r------0 - SLO
Reset Select Out
r-------
D
Se7 Cl= Uni~St;;;u;
CO = SP Key
Unit Replies
With STA-I
I
(Clear Device
r-\.Off Interface
]--------
-----Set C hanne I and
Set Channel and
Unit Status in D
Set Channel Errors
in BI from
UCW 8 and Set
Bit 0 if PCI
Flag Present
Unit Status in D
l
Set SVC-O
Accept Status
I
Status in
BO
Status
~-..---'
OBI51
Wait 40~s
for Status
In to Fall
(If Time Out}-Set ICC
Set Unit
B Reg contains}
Unit and Channel
Set CI = Extn
Address
CO = SP Key
OCI41
Reset IR
Latch if Set
by TI 0 on Entry
No
End
Rejected
YI
Yes
Store Count from
LS08 into MS46
-----Store Unit and
Unit Status
Previously Rejected
and Stacked
in Unit
Yes
Modifie
Bit Alone
Channel Status from
B into MS44
- S!c;reN';-t CCW Add ress from
LSOB into MS42
- -Store
---SP Key
No
and Extn Address
into MS40
in Status
Yes
ICC
Bit in Channel
Status
I
No
Full CSW is
Stored in MS40MS47
1
OBI91
OClll
Set Condition Code I
Set C hanne I and
Unit Status Only
in CSW Remainder of
Set Condition
Code 0
_ _CJ:!:Il!.ZEo_ _
-Set
- Instruction
--- -
Set CC = I
Count in A
- -Set- Instruction
- ---
I
Control
Unit
Busy
Yes
No
Yes
No OCIOI
F
Unit
Status
Zero
-------
Revalue MI
-------Set Instruction
Count in A
OBI91
Revalue MI
Next
I-Fetch
ODOOI
Count in A
Next
I-Fetch
ODOOI
I
Next
I-Fetch
ODOOI
Condition Code Setting on Test I/O
Action on
CSW
0
Unchanged
I
Notes
Path to Unit
IS
Free
Local Storage
Channel Errors
CSW Stored
Interrupt was HeidI has Been
Cleared and CSW Stored
Refi II
Path Busy with Data Transmission
2
Unchanged
or has an Interrupt for Another
3
Unchanged
G
Unit
FIGURE 668. TEST I/O MULTIPLEX CHANNEL MICROPROGRAM
---
Channels or Unit Unobtainable
Extn Refi II Address
-
OC
- - --
Address
OB
Flags and Op Code
Extn Address
OA
Unit Number
Unit Status
09
Byte
Count
08
-
-
-
- - -- -
4
Request In
Dump Area in lS
A
locn
RX
RO
RI
Select Out
49
YCD
YA YB
Key Skew
Operational In
4A
AX
AO
Al
DO
DI
4B
4C
4D
CX
4E
BO
BI
CO
CI
Device Requests
Service
Address In
Store:
Hardware Operation
ROAR; PSA;
ISA; CPU
H
4F
CPU ROAR
PSA ISA
Store Hand J
_ _ R~i~e~_
~
~
Yes
_________<.
No
-5';, ycoT.;"cx
Microprogram
Operation
Enter Mpx
Address In
Sheet 4
Sk;p
Operation
Y6
Store C, D, B, A
Registers
YA and YB in CO
CPU Key ;n C I 0-3
S~e~R~ i~ s.!.
Reset YA
±:7
~_ _L _ _ _ _ _ _ _ _ _ _ _ _ _ _Y_e_s--<.. Address In
Gate Device #
from Intf
No
Form Sub-Channel
Address from
Unit #
No
Count
Negative
Y3
Yes
CDA
Flog
Restore: YCD, YA,
YB, Skew Register,
Microprogram
Operation
CPU Key, A, B,
"p,~,~:gi~r~
Reply to Device With
CMD-O and Proceed
Read Out ROAR,
CPU from LS4F
UCW Address not in
Available Stora e
Byte (00)
Read Count to DReg
$to;:; S~-Cha;-n;i
Undump Cycle
Address In lS27
and Unit # in
Restore from R: ROAR,
LS28
ISA, PSA, CPU.
Read Out lS4E and
Restore Hand J
Restart
Interrupted
Microprogram
C
Read Out UCW4 Flags, Op Code &
Ext Address
Enter
Data
Chaining
- Mo'7e Cou~ t-;; B Register and,
Decrement - 1
No
Sheet 2
Set Flags &
Enter
Stop
loop
_~p_C~~i~ __
Set Channel Key from
SP into Key Register
Yes
J
Enter
PSA or
Re;;d OutD~a- Address (UCW2)
SAT
ISA
Sheet 3
Routine
From Data
Chaining
Count
Sheet 3
Sheet 3
o
Insert Bit 5
in Op Code
Enter
Write
loop from
510 F;g
667
Test
>-,W~r~;t~e,-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _,
...-_-I._.L-I.=:::':"':'
Op Code
CO'Jnt
-.,!:N:'.'o~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---,
Negative
Exit to Set
CT
= 0 Flog
Set Y4 if Coming
OBI81
Enter
Read
~o~ ~t~ ~a~i~
Set Y6, Y7 to
00 H Read
01 if Read Back
10 ;f Read Sk;p
loop from
510
F;g 667
II ;f Read Bk-Sk
Reset YA
Sheet 3
Enter
Data
Chaining
Sheet 2
SVC-I
and
OP-I
No
Wa it for Rise of
SVC-I in Burst N\ode
Gate Data Byte from
Enter
Restore
G
Wait for Rise of SVC-I
in Burst Mode
Intf to CI
Enter
Restore
Decrement Count -1
G
Reply to Device
W;th SVC-O
Read MS
No
Enter
Stop
Loop
J
Time Out
Yes
Sheet 4
Set
ICC
Sheet 3
Sheet 3
G
>-------,00
Set
ICC
SVC-I=SVC-IoSVC-OCMD-O
OP-I= OP-IoSTA-loADR-1
FIGURE 669. MULTIPLEX CHANNEL MICROPROGRAM (SHEET I OF 4)
10
11
12
From
Sheet 3
Enter
Data
Chaining
Sheet 1
A
UCW 6 Contains Next
CCW Address
110 " Rd-Sk to
100 " Rd
Bit 6 in Channel
Op Code Indicate
010:: Write
or Control
Y6
Y7
Set 0 == CCW Address
Transfer Next CCW
_~~ni!...S~_
~~~s..fro~~t~
Set 0 :: Address j n
Increment D+8 to
TIC CCW
from C
Obtain Next
CCW Address
Increment D+8
C
Yes
Reset YA, Y6, and
Reset Y5 After Test
Get Extension of
Next CCW Address
Set Y6
(UCW8)
Set Next CCW
Increment SubChannel Addr +2
Address in A
No
Y5
Exit After
D
SAT Detected
No
SAT
r-~C~C=W~O~u-t~si~de---
Yes
Available Storage
Sheet 3
QA201
..l.etY5,:!! _
Y5
1st and 3rd Halfwords
of CCW Have
Been Read Out
_ R~t~40..6_
Read Next CCW
No
from LS26 to C
If CCW Address in TIC is
Invalid the Address of TIC +8
Must be Given When Channel
Interru ts With Pro ram Check
Return to Read Out
3rd Halfword of
CCW
Two Consecutive TIC'S
Sheet 3
Sheet 3
Sheet 3
Su b- Channe I Forma
This sheet starts data chaining routine-1) Fetch UCW addr and incr to loc of next CCW
2) Fetch next CCW address
W
L
R
UCW8
I 1 JI
I
Prog
Prot
Ck
Ck
C
C
Extention Next CCW Address
3) Repeot UCW letch lor ext byte of CCW addr
4) Incr CCW oddr by 8 for following CON addr and
rewrite in Mpx store UCW
~5) Fetch lst hlwd 01 CCW
6} Test for TIC,command
7) If TIC, fetch rmclr of data addr (is next CCW oddr)
incr this oddr by 8 and store in mpx store UCW
8) If no TIC continue fetch CCW in order 3rd, 4th, 2nd
hfwds and test errors (allan QA21l)
9) Then fetch new CON, test nc
10) If no second TI C, do as step 8
11) If second TIC, exit to error routine
Next CCW Address
UCW6
UCW4
C
D
A
C
C
S
I
L
S
K
I
P
I
P
C
End
OpCede
CT~
Data Address
UCW2
Unit Number at the End Time
Extenti on Data
Address
1
I
Unit Status at End Time
G
UCWO
t
CIT
FIGURE 669. MULTIPLEX CHANNEL MICROPROGRAM (SHEET 2 OF 4)
Stat
Rch
I
12
11
10
From
From
From
Sheet 2
Sheet 2
Sheet 2
A
QA211
A
incrementCCN Address
+2
for Lower
Hfwd of Address
QA211
Write Flags and
sp~de~n~S~
Call Storage to
Read Out Count
Read MS
Three
low Order
Zeroes in New
No
SAT
Yes
CCW Addr
Yes
Set CCW Addr in C
Set Y7
No
Call Write MS
Bits
37-39 All
Zero
Yes
Sheet 2
Call Storage for Second
Hfwd of Data
Address
----- Decrement Ct-l
From
From
Sheet I
Sheet 2
Count
Enter
Yes
PSA or
ISA
Zero
Routine
QA211
Reset YB
Enter Mpx
Data loop
Sheet 1
Call Write MS
Set Y4
C
Sub-channel Address
to A rrom LS27 and
Y4,Y5 = 1 to Set
CT
Count Zero
Flag On Entry
Sheet 1
Enter Stop
Loop Sheet 1
Increment +8
Channe I Errors
in UCW 8
= 0 Flag During
Restore UCW
Enter Stop
Loop from
Fig 667
o
/
SVC-I = SVC-I- SVC-O - CMD-O
OP-I = OP-I- STA-I - ADR-I
/
/
This sheet contains:
1)
Error routines
2)
Count:::: 0 routines
3)
Stop Loop
A}
B)
Invalid data address
Doto chaining errors
A)
On entry
B)
During data loops
Enter R€Store
Sheet 4
Enter Restore
FIGURE 669. MULTIPLEX CHANNEL MICROPROGRAM (SHEET 3 OF 4)
Sheet 4
Y7 Tests for Two
Consecutive TIC'S
14
13
16
15
Enter Restore
from Error or
Read Data Loop
Enter Restore from
Write Data Loop
Sheet 1
Sheet 1
Enter Restore From
CT = 0
Sheet 3
G
A
From Status
0::..;A231
o--'--_.....l_ _--L::
Reset YA
_
~e0°-,-
'C!. _
Increment
Count +1
Yes
Device End
or Attention
No
Status In
Gate Channel Errors
from I ntf to CO
Enter Status
Restore Count
Service
in Sub-Channel
Fig 670
Set Y6
;rY_e-'-s_ _ _ _ _- ._ _ _ _ _ _--.
Channel
OA211
Increment SubChannel Address +8
No
Store Errors
Y4
in UCWS
Set Y4, Y5
Yes
From Status
Service
Increment Sub-Channel
_____ _
_AM~t..±2
Y4 On Signifies
Restore Data Address (Un; t
Thot a New UCW 4
Number and Unit Status at
Must be Stored
E~~~ _ _ _ _ _
C
Set Flags and Op Code
in B from lS29
Fig 670
Decrement
Sub-Channel
Address -4
Clear Channel
No
Yes
No
PCI
Flog
Yes
TIR
OA211
OA231
Stop Device at Next
Service Request
Set IR Latch
No
Revalue MI
With System Mask
- Set-D~i~ Hand PCI
Flog in LS2A
Yes
Set End Status
Reached Flag
in B1 if
Present from
Status Service
LS48 Byte 1 Will
Contoin FF if
Coming from 510
D
SVC-O or
CMD-O
Store ICC Flag in
UCWS
Time
No
Yes
Start
Y5
I/O
No
Out
OB191
OAOOI
D
No
No
Mpx Retu rn to
Restore: yeD, YA,
Stort I/O
Fig 667
YB, Skew Reg ,
CPU Key,
Enter Mpx
3.L.BL~~Ro:l!' _
Address In
Read Out ROAR,
Sheet 1
PSA, ISA, CPU
from LS4F
Store New Flags,
Call Undump
Op Code ond
Extension Address
in UCW4
Undump Cycle
Decrement SubChannel Addr -4
Restore from R:
ROAR, ISA, PSA,
CPU. Reod Out
LS4E ond
Restore Hand
J
Data Chaining Objectives (Byte N\ode)
Restart
interrupted
Figure
Objective
Micro-
669-2
1. Set up next CCW address in UCW6.
program
2. Read UCW6.
3. Set up extension address in UCWB.
Data Service Objectives {Byte Mode}
Figure
669-1
4. Read UCWS.
Objective
1. I/O unit initiates selection with request-in.
5. Assemble full CCWaddress in C register.
2. Dump CPU.
6. Read first halfword of CCW.
3. Subtract 1 from count.
7
0
Test for TIC command.
a. If second consecutive TI C (Y7 on) , exit to error routine.
4. Test count zero flag.
669-3
b. If first Tic:
• Read second halfword (next CCW address), increment
address +8, and store in UCW6 and UCW8.
5. Test for read op code.
6. Subtract 1 from count.
669-2
• Fetch new CCW (step I).
7. Access ma; n storage.
c. If not a TIC, read out third halfword of CCW.
669-4
S. Add 1 to count.
669-3
9. Update UCW (Y4 and Y5 off except for last byte).
10.
Undumpo
11. Continue interrupted microprogram
S. Read fourth halfword of CCW (Y5 on).
9. Read second halfword of CCW (Y5 on).
669-1
10. Reset Y5 and set Y4
0
1 J • Test for burst mode.
669-4
G
1,2. Add 1 to count.
13. Store new data in UCWO, UCW2, and UCW4. (y4 on).
14. Undump.
FIGURE 669. MULTIPLEX CHANNEL MICROPROGRAM (SHEET 4 OF 4 )
This routine restores updated UCW to Mpx store.
ff during data service the count does not go to
zero, and there is no carry into extension byte
of data address, only the count and data address
are restored. (Y4, Y5:; 0)
This routine is mainly used for exit from either
data service or status routine.
Mpx Input Bus
3
IF
Tog
Mpx
Check
Mode
IF
Parity
4
Channel
Control
Channel
Data
Check
I/o
IF
Check
o
Check
A
Byte 0:;:: Channel Errors
.,
Bit
Bit
I
Bit
Contr
2
.
Bit
Bit
Bit
3
4
5
From Fig 669
Sheet 4
Bit
7
Bit
6
By tel:::: Data
Zero
Interface Status Byte
No
~
Orl
Status
Atn
Unit
Mod
Busy
Channe I
Device
End
End
End
Unit
Check
Unit
Except
-
- --Set Channel
Set System
Mask in 0
-I_IR
--
Set IR Latch
Set Bit 5
(Device End
or Attention)
In AO and Unit
Mpx Local Storage Working Space
Yes
Current Data Address
Yes
TIR
Transfer Mpx
Storage Address
to A and
_1~r~e~+8_
Read Out Mpx
Channe I Errors
26
27
Mpx Store Address
Bus
Unit
-In
Number
Channel
28
Set in DO Any
Channel Errors from 80
Yes
Mask Off
-----
C
D
A
K
I
P
C
C
C
Operation Code
CT
End
Stat
Rch
~O
Extension Data Address
Restore Channel Errors
from 0 to UCW 8
29
Chan
Or!
Check
On
Log
Out
C
Atn
Or
Dev
End
E
N
D
QA261
2A
CMD-O
Command
Chaining
Reject Stotus
No
Set Mpx Store
Address in A
Yes
Set Y4
QA251
Unit Check
DE Alone
or DE With
Channe I End and
or Modifiers
Fig 669
Channel
End Alone
Set A to Next
CCW Address
Sheet 4
Set SUP-O
to Indicate CC
Set Bit 6 (End
Bit) in AO
Set Y6
Propagate PCI
Flag if Present
Se"t Y5,Y6, Y7
-- -
--
Set SUP-O to
and Unit
Number
in Al
Indicate
Command Cha i ni ng
D
-
Accept Status
-
-
SVC-O
-
No
TlR
QA261
Read Mpx Store
and Update CCW
Address + 8
if Modifier
Set System
Mask in D
I--IR
Bit Present
Set Interrupt
Request latch
Save PCI Bitand
Unit # in LS26
Figure
670
Objectives
I. Test for command
chaining.
2. Accept status.
3. Set Y6 status.
667-1
4. Fetch new CCW.
(step 4 510 ob-
Fetch CCW
jectives)
Figure 667
~et
Y5, Y6, Y7
CMD-O
Re ject Status
MPX Store Format
W
UCW8
L
R
Prog
I
C
Prot
Check Check
Restore
Interrupt Buffer
Extension Next CCW Address
C
SVC-O
Accept Status
C
D
UCW4
Set Mpx Storage
Address in A
Next CCW Address
UCW6
A
5
C
K
C
P
C
I
Operation Code
CT
~
End
0 Stat
Rch
Extension Data
Address
Data Address
I
UCW2
Unit Status At End Time
Unit Number At End Time
UCWO
Count
To Fig 669
Sheet 4
FIGURE 670. MULTIPLEX CHANNEL STATUS
I-Fetch
QDOOI
110 Interrupts
Contents of CSW Stored
A
PCI
Treated_ as an end type interruptA fuJI CSW is stored but unit status is zero.
END
A full CSW is stored
Device
End
PRI
Device is selected to obtain in status. Only
the unit and channel status appear in the CSW.
The- remainder of the CSW is zero.
QC 051
Channel
Control
Check or
!Machine Chk
Treated as an end type interrupt. The CSW
contains unit and channel status only. The
remainder of the CSW is zero.
"And" interrupt request
latches with system mask
and set result in 01
Continue
J - Fetch
~
e,e'Mls,a,
"hat
Type af
r-------------<...
-
Pdad'y
1. External
2. I/O
, -__~3~.~U~~==a'~e~T~;m~e~,__/
1
Interrupt
}------~
I /0
,.------...
,,---------<61>---,--------4--,(
t---<
I
(,-_M_X___J-'
Clear YA and YB
Set Y2, Y3 (Timer)
Set A 52 (Timer
MS Address)
Set 4 Bit Timer in BO
Bits 4-7
=
=2
To Indicate
To Indicate
Channel
Channel
I I
Read Out
Interrupt Buffer
from lS 2A
Set Y5 Interrupt Indicator
Read UCW4
set Y5
Test Interrupt
Flags
Set External Interrupt
Latches in Bl
X5 fa, 60 CY
X6 fa, 50 CY
Y7 on ensures T10 ex i t
after unit selection
C
Timer)
QC061
Set YA
L
+--------------1 Update
External)
~
)
1
Set YA = 1
I
QC 101
sc
~
SC2
FOr.!!LX.2..ya~l.!1..BQ.. _ _
Subtract BO from byte 0
of the Timer value MS 52
Enter Store
~
~ubtractio.n.starts
It~;:;y~m~bt'roc~n~
PSW QCOII
The Timer is
32 Bit wide and
In
Bit position 23
one is subtracted from the
timer value in MSjO
PCI End or Chan
Control Check Interrupt
k ~ ~; (~ ~' :Y~ ~~7
val~ mge~e,
(Y5 and Y7)-
Ye,
0
Clear Interrupt
Buffer in lS 2A
+
'SEL
Enter TlO Routine to Select
Unit and obt!Jin Status
Yes
Contro1 Chec k
nterrup';
If end Interrupt unit
status is in UCW 2
Test I/O Routine to
Reselect Device for Device
End Interrupt
5EL
Q8121
Channel
0
Set Y5, Y6, Y7
Read Status
Register to Cl
Set A Register to 46
negative
O-IR
,_
I
~
~~~
Timer Interrupt
(00 - Chan Stat ) -_ _ _-;
01 = unit status i'Q'-'8'-'1c.:4~1___.J.______- ,
O-IR
Generates UCW Addr
from unit #
o..... IR -
Set Channel Control Check
Flag in
00
O-IR
Set IZl latch jf PCI type
Interrupt
Reset IR
Cl-CH - Clear Chonnel
I
Local Storage
QC 111
<;b
ISO - Inhibit Sel Out
Remove PCI Flag if present i n ) Transfer UCW from MPX
UCW 4 and set Y4 If no pcr
Store to lS 08 through
flag, clear UCW 4 lS OA
' -______O.:;.;:.C______--'
~o.!:!_
~~fill_ DC
~f~ _ _
~d~s~ _
Flags & Op
Ex Address
r Byte
~t-=--=-
oe
Set Channel errors in
00
~it2t~us
09
08
I
!
No
Address from UCW 2 to
C Register. Set A Reg to
40
SP Key to 00
---- OA
Count
Channel Status to 81
Count (T Reg) Put in
CSW at MS 46
Set Channel Control Chk
Bit in Bl put Count in
CSW at MS 46
NIF
Set Unit Status in SO
Set Chan Status in Bl
Register C is zero
f- $;"Ch-;;-n;;d &'0;'-;;;-81
from UCW 8 and set bit
is present
Set Unit Status in BO
Lfl~ister B now contains
i - , m t and channel status
Remainder of CSW is zero.
Put Unit Status
in BO
Set BO
to zero
CL-CH
I
I I
Write SP Key into MS 40
and Ext Addr to MS 41
Enter Store
PSW Routine
QC011
Clear Unit Status from SO
I
I
Set Y6
I
QC111
A Register Set to 44
I
Store Unit and Channel
Status into MS 44
-------Store next CCW Address
from UCW 2 into MS 42
Set CO = SP Key
~nd C1 extn addr.
=
I
Store Count from LS 08
~~!2...M.i42..
___ _
Store unit and channel
l_
__ JA full CSW is
~tt~s~:'f-~dWoCd~~~-~
from lS 08 into MS 42
Store SP Key and extraaddress from C (via B)
into MS 40
G
I
Enter Store
PSW Routine
QC011
FIGURE 671.110 INTERRUPTS AND UPDATE TIMER MICROPROGRAM
Ye,
Wait
Enter
Wait loop
Enter
Stop Loop
Qe071
QC081
No
o if PCI flog
Store Unit and Channel
status in CSW.
HALT
Ye,
QC111
Cl-CH - Clear Channel
No
Enter Store
PSW Routin
Stored
QC011
4
2
SC Status
In Forces
708
A
Set YCH 3
Dump D
Set DO~I
From
Fig 675
Sheet I
r-------------------<~>_------------------_.------------------_,I
QB511
II (D)
End Status
50 ~ 3
) - Reached. Irpt
(
51 ~ Unit No
Code and Unit
No to 5
QB511
Set ISO
(
(
(No Chaining
"- Boundary
l
QB451
Buffer
)
Empty
'-------i--'--"
Set Up
Chaining
,-Bo_u_n,da_ry.!--,
)
Accept
Interrupt
CBY
BU1
Reg A == 34
1
Reg A == 26
L-____
Reg A =58
Set Interrupt Code Into B
Register
Y4, Y5, Y6
Set Y4, Y5, Y6, Y7
Set Y4, Y5, Y6
Are On
I
I
Y4is On
Y6 Is On
Set Y6, Y7
I
I
I----,--_.......J L__-'-I_.......J
I
Reset Data And CPU Chan
Key Registers
.
r -__________________
~o~n ~~)_~O~I~I--------------------~--.
__
Set The New Interrupt
Code Ready To Write
into Main Storage
From DO - Dl
Set The New Interrupt
Code Ready To Write
Into Moin Storage
From DO - D I ~ith Zeros
9Write Into The 2nd Ha If
Word Location Of The
Old PSW The New
Interrupt Cede
00 OrOl
No
A
Yes
10 Or 11
2 Or 3
I
Change 00 To 01
Change 01 To 10
y
Set Up The Address Of
The 4th Ha If Word
01 The Old PSW
Into Main Storage
•
•
Set Y2, Y3 Stat
Value In Dataflow
Register (New CC)
Write Into The 4th Half
Word Location Of The
Old PSW Into Main
Storage, the Next
instruction Address. This
Next Instruction Addess
Comes From LS Location
47 (Hex)
1
Expand The Extention
Part Of The Next
Instruction Address
•
A
Set Up The Address
Of The 3rd Half Word
in Ma in Storage
Off
Read Out Loco I Store
Lac. 46 (Hex) And
tv\ask Off The ILC
And CC
Read Out
LS Location
46 (Hex)
Prepare ILC +CC +
Program Mask +
Expanded Extention
Bit New
Prepare ILC +CC+
Program Mask + IC
Bits 0-7 Old
I
Write Into The 3rd
Half Word Location
01 The Old PSW
This Prepared Information
Set Up The Address Of
The 1st Half Word Lac.
01 The Old PSW In
J\t\ain Storage
J.
Write Local Storage Loc
44 (Hex) Information Into
The 1st Holf Word Location
Of The Old PSW Into'lv\ain
Storage
Lood PSW
Figure
FIGURE 686 STORE PSW - GENERAL FLOW
(QCOll)
0,
638
BASIC HINTS FOR THE CE
Customer may be
rerunning a program
with smaller checkpoint
increment, or machine
is failing only on
particular program or
fault may have cleared
1.
The phi losophy behind MAPS is basically to guide the CE and to minimize wrong conclusions
2.
Analyse the console display carefully. Do not start logic page analysis until you are satisfied that
the information provided by the indicators has been fully utilized
3.
Locate the source check. This is particularly important in the case of channel checks
4.
Some checks are more explicit than others. Always establish the amount of hardware funneled into a
check by means of the appropriate ECAD. The amount of hardware involved will influence the procedure
adopted to pinpoint the fault Ii. e. in certain cases you can go straight to the card (s) involved
5.
Switch on your scope at the beginning of the cord-changing activity
6.
Where possible change cards in preference to scoping since this process of elimation is for less
susceptible to misleading conclusions
7.
Always look for some common relationship between fault symptoms
Consult customer.
Analyze any avai lable
logouts. Use MAPS
to prepare your
fault locating plan
Check voltages (on
Internal CE Panel) for
missing voltages or
extreme high or low
voltages. Do not adjust
small differences in
voltage at this time
Establish a common
link, e.g. check,
control signal, address
program, if possible
Was
Original Error
a Channel
To Sheet 2
Consult Program. Refer
to Last Log Out (S) or
program messages from
same or previous job (if
avai lab Ie) • Establish
common link
If you can identify
a suspect area with
information, examine
for loose connections
whi Ie trying to
reproduce error
To Sheet 2
>-Y_e_s_ _ _ _ _--,
Error
No
Ana lyse Report. Try to
find a common link,
e. g. Same Program,
I/O Un;t,
Channel,
Calculation.
No
Fail
Yes
I/O Un;'
CPU
Channel
Unknown
Yes
Run all external diagnostics of suspected unit
Load and run
diagnostic for failing
area or run common
fa iii ng program
No
Error
Yes
No
Yes
Yes
Error
Refer to MSC
or Diagn Doc
No
No
Yes
Error
(Hardstop)
Consider:
Intermittent
Failure (!),
Data Sensitive
Error
Loose Connect ion,
Power, Noise,
Close Timing,
EC Problems, etc.
Record error envi ronment
and then run
check circuit tests
I
----- ~
Customer Program
Documentation
Consult Programmer
(if necessary)
Figures 324,907
FIGURE 901. INTERPRET ERRORS (SHEET 1 OF 2)
Figures 314,906
Figures 343,908
Consider:
Program,
Power,
Noise,
Close Timing,
Warm-up,
EC Problems,
Loose Connec t ions,
etc.
To Sheet 2
From Sheet 1
From Sheet 1
From Sheet I
Examine printout to
determine where the
error was detected
Change Cards Before
Scoping when Feasible
,-
Was
No
Original
Error a Control
Check
I
Does
Indicated error
justify taking
off
I
I
I
No
I
H/Stop During
I
System Reset or
CPU Checkout
L
Was
original error
intermittent
Yes
Error
I-________-'-N"o'--
20
20
4
39
39
60
J:
5
~
40
6
59
59
The shaded positions are used for cable connections.
Note J: Numbers in parentheses refer to Mop
Chart Reference Notes, on Sheet 3.
FIGURE 911.
~:::J
0
READ ONLY STORAGE (SHEET 1 OF 3)
~
All l's Test Word Address = 020
All O's Test Word Address ~ 010
Incorrect Word Pattern
(16)
TI st
Patterns Correct
Test
pattern(i Incorrect
I
(20dJ,.)ncorr~ct
ord Pottern{s)
(20 ) 8 colec. Bas
C Picking or Dropping
(20b)4 Cotec. B; ts
(20)
Picking or Dropping
Check Error Word with
Tope listing
Random Efrors
I
I
Manually Select
All 'l's Test Word
(230)
(21 a) Error In Same
Bit Position
Change In Error
Bit Position (21b)
I
I
I
Random Pattern
Revert to Error Word Add
One Bit ;n Eccer (23b)
Select Word In M:)dule
Adiacent to Error Module With
I
Interchange Driver Decoder
and Gate Decoder Cards
(23)
A 'I' In Error
Bit Position
(24)
(220) Cho nge In
Error Bit Position
No chlge (24b)
In Erro~rpattern
(240) Errfr Pattern
Cha nges
Error In SOme (22b)
Bit Po~ition
I
I
Elimina te Faulty
Decode r Card
Inspect Sense Bus
Twisted Pair and
Connector Card
Check Output
Cable Cord
Interchange
Two Driver Cards
1
J
(250) No Sho nge
In Error Pattern
r
Interchange Other
Two Driver Cards
1
(30)
(300 11' out
I
;~I-------------'
A Channel Check 1 ~
r-______
A
Occured Before the
Start Latch was Turned
on. Check Error
Conditions 1,3,4,5
IF
No
¢
(
TO or 11
PTVCheck
WO PTV
Check
No Other Chonne I
(
IF Tag
Check
Error Indicated
)
Y
Occur on Se lector
Multiple
Out Tags
Failure
Yes
Check CLD's
ALD's Etc.
Chan Chec
Out
I
No
Refer to
ADR-I
or
STA-I
~
No
STA-I
Determine Which
Unit Operating
Write
Determine Bit in
Error by Rereadi ng.
However, First Try
to Create the
MSC's
and Which Bits (s)
are in Error
Failure With
Chonnel Checkout
or I/O Diagnostic
Whi ch Wi II Have
CCW Address
Attempt to Determine
the Expected Stotus
to Find Bit (Bits)
Tag Sequence
Check Has Occurred
in Error
Known Data
Check transfer paths
~~_v_es~I~ ~
C
Thi s Check is to
Irom W4 to WOo
(Good Pori ty was
generated in W4).
Yes
4P
__
No
Equal To
726
The count Ii e Id 01
present CCW should
be contents of T
Ensure That the In
Tag Rises Beforethe
No
Address
In
No
Status
Yes
In
l
Bus in PTV Check
Yes
register (l410E
No
on Incoming
Addr or Status
Program sets last byte
of count field equal
Out Tog, and Thot
In Tag Foils Belore
the Out Tag
The Following
Tags are Checked:
SVC-I, STA-I,
ADR-I, SVC-O,
CMD-O, ADR-O
to 0080 or FF)
D~~Sa
Address in Curren
CCW Equal to
S Reg
D
No
Yes
Intermediate Residual
Count is Equal to
Count in the CCW
I
ADR-O
and
CMD-O
I
I
ROBAR
Page
Cause
5C6
QB171
STA-I too Slow After
CMD-O
5E6
QB111
at initial sel
7C6
QB111
SVC-O Drops
Slow HIO
7AB
QB461
OP-I Drops
Slow HIO
776
QB501
Interface
not Free
726
QB541
ADR-I ".
ADR-O
7BB
QB551
Until too Slow
I/O
No
No
These Two Tags
Allowed in This Case
Check lor Other
Combination
Backward
Is~
Subtract Data Address
In 5 Registel from
Dato Addr in CCW
Yes
nitial~
StortLot~
for N umber of
Bytes T ransfered
I
0/
is in Error
Yes
I~d~ress
l
IS In
I
Out
Error
Subtract Number of
ST A-lor ADR-I
too Slow
~
Start Latch
on
o
OP-I
Bytes T ransfered
No
Address Out
~
Subtract Doto Address
in CCW from Data
Add in 5 Reg i ster
for Number of
•
CMD-O
and
SVC-O
'"0
'"
Yes
No
ADR-O
and
SVC-O
I/o
1
Read
Service Out
is in Error
Yes
Error Probably
Occured During
Termination of Data
Service. Check for
Proper Sequencing
of This Operation
I
Check Power
On in
Terminating
Unit
I c~m:"and I
Bytes T ransfered from
Out
the Count in the CCW
IS In
to Obtain Intermediate
Error
Residual Count
Fai lure
in One or Two
By.te Data Service
See QB401
or QB411
M~~O
~
2 Byte
Been Sent
to CU
1 Byte
•
If Read Bockward Add
1 to Residual Count.
If Not Subtract One
II Read Bockward Add
2 to Residual Count.
II Not Subtract 2
G
~r--'-V-o-u-H-a-vL...e--N-o...J!~---,
Calculated the Value
of the Residual Count
Wh ich Shou Id Appear
in TO and 11
FIGURE 916.
ADR-I
and
SVC-I
ADR-I
and
STA-I
l
No
SELECTOR CHANNEL
Yes
in Main Storage
Write
Obtoin CCW Relill
Address Irom LS22 (SC 1)
or LS32 (SC2). Subtract
8 IromRelil1 to Obtain
~resent
~
I
~
be Found by Looking
at the Present CCW
Reod
IF Tog
Check
)
Error Occured
at Sometime Other
Than Data Service
R-I
from the 0 Register.
The Correct Flags can
Read
or
WO PTV
Check
I
The F logs are Set by
CAS on Page QB531
No
Yes
Occur on Selector >_--------~
No Other
Check Indicoted
0-301 Flag Register
Chan Check
Out
'd
Cp
Parity Check on Bits
Late Check While
Operating the Channel.
Did
Check
(CCW Flags
CPU Control, Early or
Failure
Yes
Control
No
r------.J---.J__~
14XX Mode >--'-v=es'--_______---,I
No
Determine What Data
Should be by Comparing to Main
Storage Data Locati on
Indi cated by the
S Register
Determine what data should
be by examining contents of
storage location indicated in
S register (in decimal). Use
1410/1401 conversi on charts
or put CPU into hard stop
condition and force ROAR
bit 12 on; this activates address
translator. Use decimal
1410/1401 oddresses to
Display storage
ves~~Sta
Yes
>--------0...--------<
1
Oper Latch
On
Address
In is
in Error
No
Status In
Service In
is in
Error
is in
Error
SVC-I
and
STA-I
Check Control
Unit to Find
Proper
S",,-uence
No Power-On
li ht
Activate lamp Test
Switch and Replace
Burned Out lamps
Yes
No
1. Indi cated
area for
overheat
1.
2.
No
2. Fans
3. Filters
4. Thermal
Switches
Tripped
3. Pick Circuit
for K15
Cneck
K3 to K7
Check
K8 Points
Points
Yes
Yes
Check
Steppi ng Swi tch
lMT and INT
Switch Points
Determi ne from Index
Where Steppi ng Swi tch
Stopped.
Check
1. Power to CU in
that Position
2. EPa Cable or
Jumper
3. K21,K23,K25,K27
Points (Relay
Chart)
4. Stepping Switch
Contacts in that
Position
No
K2 Points
Check
I/O Stepping
Switch Contacts,
Position 25
Yes
Check
1. K9 N/O Points
2. K15 Njo Points
3. K20 N/O Points
Check
K12,K16,K31,
K32, K33 Point
Check
Undervoltage on
PS3 and Pick
Circuit of K16
Check
Power Off Switch
and
Power On Switch
Check
K3 to K7
NjO Points
Replace Burned
Out Thermal
Indicator
1.
2.
I Any
Check
K13 Points in
K12 Pick
Circuit
Check
K19,K16,K15,
K20 Points
FIGURE 917. MID - PAC POWER SUPPLY
Power Supply,
Whi ch Drops Vol tage
I After Power On,
I Causes System to
Power Down
Relay Chart
Switch
Position
EPa
Relay
Power Sequence
Relay
4-9
K27
K22
10-15
K25
K24
16-21
K23
K26
22-27
K21
K28
Check
1. EPa Swi tch
2. CBlTripped
3. Fuses F1 and
F2.
4. J3 EPa
Jumper
5. Check Wall
Panel Breakers
Yes
No
Ye
Yes
N
Check Indicated
Supply Module
O/C Cord.
Indicated Supply
Module Has O/V
Condition on
Ou ut
Check:
Module
O/V Unit
Distribution
Lads
Check Mains
Supply, Main
Contact Breaker
FusesF1 F2.
On' Pushbutton
Following Tests
Low Res.
Use of Ohmeter
Less Helpful
Use Ohmeter
Logically
Detailed Exam-
Disconnect
Branches at Ter-
ination of Load
Ci rcuits
minal boards and
test to isolate
Section
e.g. Power
Module?
TROS or
MECCA?
Gate lA' or
Gate 'B'?
Progressive Re-
Moval of Cards
In Sus ect Area
N
Inspect Indicated
If on Gate:
Area
Is alate at Laminar
Bus to Locate
of Overheati ng
Check Pick of
R15, R16, R 17
R1SandR19
Board
Isolate Card on
Board by Progress ive Remova I
for Signs
Check Relays
R15, R16, R17,
R1S, R19
Yes
of Cards
Repair or Re-
place faulty
Components
.Thermal Reset
Thermal Reset
When Ambient
Temp Perm i ts
* Check 24V Supply by
Measuring Between TB3-12
and TB3-6.
Yes
Abbreviations:
O/V = Overvoltage
O/C = Overcurrent
Oil = Overload
U/V = Undervoltage
No
None
Some
Check Relays
K3, R22, R24
R2
Check Individual
No-Output'
Modules
N
Check Complet
Operation of
Stepping Switch
Check J Socket
for Loose Plugs,
Missing Links
Check Cony
/Inv Fuses
Check J Socket
Cables up to
Cantrol Un its
Check Control
Units
Check Pick K2
Check K2
Contacts
Check F3, F4
F5 on 50 CIS
Check Pick R1
FIGURE 91S.2.5 KC HF POWER SUPPLY
I
I
I
6227
CiT 400
OT004
I
I
~
NSC5 Bits 0 - 3 in Hex
NSC6 Bits 0 - 3 in Hex
•
+
0,4
8-f
1,5
6 Char Op
OT009
6226
QT 401
QT 402
6226
QT 405
,-------1
>--4~--~!1__--;-1_ _-=.8--',f
OT 009
I
I
I
6 Char Op
I
I
/)
/'
I
I
I
I
OT003
I
I
I
I
I
TestY3
I
1
NSC4 to B Reg
Exclusive or B Reg
6227
QT 400
WIth (V8 Stat,) 0000
I
--l
NSC7
81 +
So Result to (1
WM
7 Character Op
)------,
I
Ll
L _ _ _ __
Reg
NSC4 to B Reg
Read Out NSCS, NSC9
Store d-Mod (NSC7) in
A-Character Reg
Exclusive OR (VB Stots) 0000
With 81 Register
Exclusive OR (VB Stats) 0000
Result to CO Reg
C Reg =' HDOD
Result to Co Reg
With B Reg
C Reg
0
HDDD
Store BAR in LS E3
Set Y4
I
NSC4 to B Reg
6227
QT 400
No WM
WM
1
(
I
I
Exclusive OR B -Reg
With (VB Stats) 0000
Result to Co Reg
C Reg'" HODD
Store C Reg In 8AR (LS E3)
I
I
I
I
I
I
I
Test Y3
>-------,
6227
QT 400
K
NoWM
Set lAR
0
NSC8
6226
QT 400
Set IAR to NSC7 Address
Address
SetY4,Y7
______ J
Store d-Mod
inA-Char Reg
NoWM
lOp
620L
6214
Clear
Storage
QT 229
Op Code to B Reg
LS EO-B
OT 005
OT005
Decode 1401 Operation Code
Addresses and Stats Set by I-Fetch
Function on Branch on Bits 0 - 3 and 4 - 7
Y4
Y5
Y6
Y7
Defines
For Results See Figure 6200B
OTOOI
3, 6 or More Than 8 Choracter op
1 Character op
2 Character op
4 Character op
5 Character op
7 Character op
8 Character op
Local Storage Contains
EO
14011AR
El
1401 A-Character Register
01
1401 AAR
E3
1401 BAR
EE
HDDD
(Old AAR In E2)
Sense Switches
1401 INSTRUCTION fETCH
A-Char - N/A
HDDD
HDDD
Status Indicators
YA Stots are set to 0000 at end of I-Fetch
*Y4 and Y7 set for jOp and, Op
fiGURE 6200A.
Format
Bits
Code
Bits 0 - 3
*
Bits 4 - 7
**
XXXXOOOO
XXXX1010
XXXXlO11
Halt
1000XXXX
_
Invalid Op QT 307 arQT 308
_
QT 502
_
1010XXXX
-
Invalid Op QT 307 or QT 308
~~~~
Invalid Op QT 307 or QT 308
?
Zero
and
Add
1l00XXXX
C ear
WM
QT 221
6214
Invalid
A
Add
Branch
Compare
QT 117
6203
L
Load
D
Move
Numeric
QT 500
QT 229
Move
Nop
QT 203
QT 203
QT 009
-
Op~
QT 307 or
QT 308
QT 223
62fT
QT 223
6211
1111XXXX
Read
Print
QT 223
6211
QT 222
6210
4
Punch
QT 223
6211
• Op code in EBC DIC-II representatian
** Bits 0 - 3 = 0000 - 0111 are invalid and exit to QT 307
1401 INSTRUCTION FETCH
Divide
Invalid
Op
QT 229
6214
QT 210
6208
or 308
Modify
Address
Multiply
QT 210
6213
6208
Invalid
Op
QT 308
~
~>
H
~
Invalid Op QT 307 or QT 308
~
~
Invalid Op QT 307 or QT 308
~
~
Invalid Op QT 307 or QT 308
~>
~
Invalid Op QT 307 or QT 308
~
N
1110XXXX
Read
SetWM
#
~>
6201
V
Branch
WM or Zone
QT 117
6202
2
Print
XXXXllll
>
1101XXXX
FIGURE 6200B.
XXXXll01
l~alidOpQTW7~QT300
100lXXXX
1011XXXX
XXXXll 00
QT 300
6219
5
Read
Punch
QT 223
6211
Zone
QT 300
6219
6
Print
Punch
QT 223
6211
QT 500
Read
Print
Punch
OT 223
6211
Z
Move and
Zero
Suppress
8
(Nop)
6215
9
(Nop)
QT 223
OT 223
Y
o
Means
Involid NSCI
Branch 0
Index
Local Storage Contains
EO
1401 IAR
El
1401 A Character Re ister
E2
1401 AAR
E3
1401 BAR
1401 I-Fetch
Branch Entry
Fonnat
HOOD
A Char-N A
HODD
HDDD
y~
601
QD 001
Mod 40
I-Fetch
Even IC
. -_ _ _ _ _ _ _.;O;,;d;;,d,;.140;.;.;..1.:;1A;:;R~_-+_ _ _ _:J:Odd'I~REven>_ _ _ _ _ _ _..;E;.;.,;;,e"..;1:.;40;.;1....:;1A.;;R~_ _ __ _..."
1 Character Op
QT 000
QT 002
NSC2 Bits 0-3 in Hex
l
6226
OT 405
I
I
I
6226
L ___________
QT 405
NSC2 Bits 0-3 in Hex
:ORe
g
NSC3 Bits 0-3
I
I
I
Reod Out,
NSC3,NSC4
"Increment IAR (+4)
JAR = ICS
Store IAR
NSC, to Bl Reg
I
I
I
I
---~
3 Chorocter Op
I
I
I
I
I
I
01, II
Ye,
00
I
~009 _ _ r_--J
QT 003
QT 004
6227
BO + C1 to Cl Reg
Exclusive OR NSCj
With (yB Stats) 0000
Result to Co Reg
QT 400
C Reg'" HDDD
4 Character Op
6200A
QT 001
6227
6200A
OT 400
QT 003
5 Character Op
6200A
aT 001
FIGURE 6200.
1401 INSTRUCTION FETCH
N Op
lS E2 - B Reg
Y6
OT 009
o
B Reg-lS E2
A Reg -lS E2
o
Y5
Length;::7
Reset YA and YB
Y7
o
EO -A Reg
length =4
length =5
00 -LS E3
A Reg -
x
FIGURE 6201.
1401 N OPERATION
6200
OT 000
1401 I-Fetch
Normal Entry
lS E3
Y
6200
OT 000
1401 I-Fetch
Branch Entry
Y
4
5
6
.i
A
Stats
Means
7 Char 0
4 Char 0
1 Char Op
OT 117
1 Char OP Use
Old AAR and BAR
4 Char Op
Decrement AAR (-1)
Address Test
Means
Address (A-B) = 1
5
B Address Odd
6
Both Addresses Odd
7
Address (A-B) Odd
Read Fi rst A-Char
Y
4
Read First B-Char
Decrement BAR (-1)
OT 114
No
Yes
OT 115
Stats
Y
o
2
3
6
Means
B Word Mark
Subtract
1401-Carry
A Word Mark
First B-Char Had Word Mark
00
01
Not Minus
Not Carry
Set Oflo
Indicator
in GPR-7
10
First B-Char Not Word Mark
11
6202A
Leave Sign as is
1---------I
A
Read 2 A-Chars
I
OT 116
6202A
I
I
OT 104
Set 9's Complement
of Digit
Set Zone Bits
to Zero (Olll-Hex)
6202A
OT 105
FIGURE 6202.
1401 ADD AND SUBTRACT
6202A
QTI06
Y
a
OT 105/107
2
3
5
6
Subtract
Add
Stats
Means
B Address Odd I
Subtract
1401 Carry
Al Ward Mark
A Word Mark
6202
OT 106
A-Field
WM
No
No
I
Yes
I
I
--~
Set Y5, Y6
to Indicate Which
Byte has WM
Set Y5, Y6
to Indicate Which
Byte has WM
A
6202
Read 2 B Chars
Decrement BAR (-2)
A-Char Now in B Reg
B-Char Now inD Reg
00
Test
01
OTI07
11
21--~
WM
WM
Add 9 Dec
to Zones of
C1 Reg. This
Sets YC I and
Leaves Zones
of C1 Reg
= 0111
WMDecrement
BAR
OTI08
Carry
/
r-r------I
00
01
Test
Carry and
Zones
10
11
I
I
I
a Add
OT 112/113
Add Final Char
Put Previous
Carry in Zones
Carry Sets
Ov fI a i nd icator
in GPR-7
Store Last Sum
X
Test Y2
Set YCI
Set Zone = 0111
Set Y3
Yes
I
I
I
I
OT 109
Set Zones
=0111 (Hex)
Add +2 to Digit
Test
Y5,Y6
6202
or 000
1401 I-Fetch
6202
FIGURE 6202A.
1401 ADD AND SUBTRACT
1 Char Op Use
Old AAR and BAR
OT 117
Double Chained
11
10
01
Set lS O(FO
Reset YA Stats
Reset Hi, Eq , La
OT 100
C Reg-lS 00
Reset YA Stats
Reset Hi, Eq , lo
B Reg-lS EF
Reset YB Stats
LS E3-B Reg
6203A
QT 102
Read A Chars
Decrement
AAR (-1)
Set Y7
Decrement
AAR (-1)
Set Y5,Y6
Read A Chars
Decrement
AAR (-2)
Read A Chars
Set Y6
A
Read A Chars
lS 01- B Reg
Decrement
AAR (-2)
Y6
OTIOI
Remove WM
from Bl Set 01=0
A Reg-lS E2
Set Y4, Y5
00-80
lS E3-A Reg
Remove WM
from Al Char
lS E2-D Reg
Set Y4
Y4 = Al Ward Mark
Y5 = A Ward Mark
Y6 = Skew (A-B Addr Odd)
6203A
QT 102
FIGURE 6203.
1401 COMPARE
C
6203A
QT 102
B
QTIOO
10
Y4, Y7
00
11
01
Sk;p
First
Compare
Reset Y4
Y5
DReg
- LS E2
Remove WM
CO¥- 80 -BO
DReg -
ANZ
LS E2
11
1,
Set Yl
Bl V80 -Bl
ANZ,ABO
00
QT 102
-------j
I
I
Decrement
BAR (-1)
Decrement BAR (-1)
YA- Sk Bfr
LS E2-D Reg
EO+Y'-Z
I
I
I
00
ANZ,ABO>-_I~O~________________________,
I
Y3
o
Y3
I
I
I
BO - A Cher
Bl - A Cher ¥ B Chcr
I
I
Y5
Y5
BO - A Chcr V B Chcr
B1 - A Chcr
I
I
A-WM
(B-H;)
A Reg -LS E2
I
Reset Y3
I
I
I
I
I
L
End
SetBO=O
Set Bl = 7F
,---------...!...,c Bl
BHs 2, 3
o
QTI03
00',-------<. ANZ, YCD' >------,1",1
B >A
FIGURE 6203A. 1401 COMPARE
o
H
Store
1401 AAR
l a i d AAR to BAR
Store
1401 BAR
I
I
Use Old BAR
J
Fonn Units Char
of Address and
Store in B1 Reg
Fonn Tens Char
of Address and
Stare in BO Reg
Length = 1
I
Use Old AAR
Length::.. 1
Insn
Length = 1
I
I
Use Insn A-Address
as AAR
l
Reset Y6 and Y7
Fonn Hundreds Char
of Address and Store
in L S Lac 03
Read out 1401 Storage
Use AAR and Decrement(-l)
Save Word Marks
.-_____o_o________
QT206
--<~>_--------1-0------,
Y6 and Y7
01
I
Store First Char
Set Y6 = 0 Y7 = 1
II
~,--------I
Store Second Char
Set Y6 = 1 Y7 = 0
II
L--...-----r----'
Store Third Char
Store AAR in LS E2
X
FIGURE 6204. STORE 1401 AAR OR BAR
I
~--r-------'
6200
OT 000
1401 I-Fetch
Op - 83 000 741
GPR-9
Multiway Branch is Entered
via a Diagnose Instruction
issued by the Emulator Program
Search Character
Address
GPR-8
~
Branch Table
Base Address
Read Search
Character from
Emu lator Program Storage
Loop
Use Search Table Address
Read Left Mast HalfWord from the
Search Table
Table Entries
QT204
Table Char
= Search
Char
No
Add Displacement to
Branch Table Base Address
Use as New Mod 40 IC
601
00001
Mod 40 I-Fetch
(New IC)
601
00001
Mod 40 l-Fetch
(Old IC)
FIGURE 6205.
MULTIWAY BRANCH
6221
OT 302
Increment - Op 83900741
Decrement - Op 83980741
LS FO- 8 Reg
GPR 8
(GPR 8)
QT207
Y4 Set By Diagnose Insn
Inc
Y4
o
Increment
Decrement
Increment
Decrement
1401 Addr (+1)
1401 Addr (-1)
Reset Stats
LS FO
B Reg -
601
00001
Mod 40 I-Fetch
Next Emulator Program Insn
FIGURE 6206.
1401 INCREMENT - DECREMENT
I
Table Character Displacement
Yes
1401 Address
6221
QT 302
Scatter/Gather
Scatter
Op 83100741
I
GPR-9
J
Read Out Control Byte,
Count, and 1401 Address
Store Control Byte
in Slats
Read Buffer
Storage Address
GPR-8
I
1
Control Count
Byte
1401
Storage Addr
0
4
7
Use GPR - 9
J
QT 207
Control Byte:
Bit
Scatter or Gather are
entered via a Diagnose
Instruction issued by
the Emulator Program
Read Out Emu Iator
Storage Address
Means
Use GPR - 8
Ward Mark Control
Use BAR
Scatter Operation
All Others =
0
o
Gather
6207A
Gather
QT 208
1 Scatter
Fetch Chara~ter
from Emulator Storage
Increment Emulator
Storage Address (+ 1)
QT 208
Translate Chars from
EBCDIC-III to EBCDIC-II
A EBCDIC-III Word Mark
Sets Y5
Transl ate Characters are
Tested for Valid EBCDIC-II
No
Yes
Set Y4
Change Character to all Zeros
00 or 80 Hex Stored
for Invalid Characters
QT241
YO Stat for Scatter Op
YO = 0 Use 1401 WM
YO = 1 Use EBCDIC - III
11
01
, - - - - - - - « Test YO, Y5 ">--------,
00 and 10
Retain EBCDIC-III Words Marks
in Translated Characters
QT 208
No
YO= 0
YO= 1
Retain 1401 Word Marks
Store Translated
Char in 1401 Storage
Increment 1401 Address (+1)
Count I 0
Y4= 1
Y4= 0
601
QD 001
Mod 40 I-Fetch
Emulator Program
Next Instruction
Emulator Program
Branch Table Entry 31
FIGURE 6207.
SCAITER-GATHER
QT 209
A
Gather
6207
QT 208
Op 83 100741
QT 208
GPR-8
Pch, Pr, P- K Buffer
Storage Addr
GPR-9
1401
Storage Addr
Fetch Character
from 1401 Storage
Increment 1401 Add':"'s (+1)
Y5 Used as
Word Mark Indicator
Control Byte:
Bit
Means
o
Test YO
o
Word Mark Control
4
Use BAR
YO Stat for Gather
NoWM
YO= 0 - Use 1401 WM
YO = 1 - Use No WM
WM
QT 209
Y5 On Forces
Bit 1 = 0
Store Char in
Emulator Storage
Increment Emulator
Storage Address (+1)
Bl + l - Bl
Effectively
Decrement Count (-1)
Set Y6 if Count = 0
Count
t- 0
Count = 0
601
QD 001
Mod 40 I-Fetch
Emulator Program
Next Instruction
FIGURE 6207A.
SCATlER-GATHER
QT 208
Stat
Figure 6221
1401 Diagnose
Meaning (Scatter)
YO
0= Move
1 = Laod
Y2
Error
Y3
LTM
Read GPR 9
Set Ctr! Byte to Stats
Count to Bl
LSAR = F2
1--------1WMGM
--------Cond Code
Y4
o = Update
GPR 9
1 = Update BAR
---------
Reset Stats 1,2,5,6
Read GPR 8
Mod 40 Addr to C Reg
LSAR = Fl
0= 1401 Addr Even
1 = 1401 Addr Odd
Y5
Y6
Y7
WM
o = Mod 40 Addr Even
1 = Mod 40 Addr Odd
Odd
0= Gather
1 = Scatter
~---------
LTM
Even
Read GPR 8
Set Ext Addr Bi ts into CX
LSAR = FO
Read GPR 9
1401 Addr to A Reg
LSAR = F3
On
Set H Reg to E3
(1401 BAR)
Restore LS to F3
o
Figure 6207 C
Set H Reg to F3
(GPR 9)
(Gather)
Figure 6207 C
B
Sheet
2
QT207
QT207
QT208
QT208
Read Main Store
(Two 1401
Charocters)
C
Sheet
2
Sheet
2
FIGURE 6207B. SCATTER (DOS COMPATIBILITY FEATURE) (PART 1 OF 2)
Read 1401
Storage
Incr Addr+ 1
Sheet
1
00
Set Skew for 1/2 WS
Read Mod 40 (2
Characters)
Incr Mod 40 Addr + I
10
01
II
Reset Y4
BO+80-+Dl
(Character and
WM)
Set Y4
80+DO
Set Y4
BO+80-+DO
(Character
and WM)
Reset Y4
BO+DI
DO-+BO
Set Y6
DI+BO
Reset Y6
00
Decrement Count
by I
10
Move
Reset Y5
Set CO to 08
ResetY7
Reset YO
Set CO to 08
Load
ResetY5, Y7
Set CO to 00
Set YO
Decrement
Figure
6207C
Countby I
Yes
No
Sheet
1
OT208
OT208
QTW- - -
OT241
AN·WM
SC ·WM
SC·WM
Set Y5
Delete WM
in BO
Delete WM
in BO
0100
Set Y2
Set BO to 00
Delete Bit 0
(BOnow Contains Xlated
Character)
Subtract
40 from BO
FIGURE 6207B. SCATTER (DOS COMPATIBILITY FEATURE) (pART 2 OF 2)
Set BO to 20
(Xlated to
Special Character 1401)
Set Y2
Set BO to 00
0111
Invalid
Set BO to 30
Set BO to 00
Set BO to 10
Set Y2
Set BO to 00
QT207
Stat
Meani ng
YO
0 = Load
1 = Mave
Y3
LTM
(Gather)
I
I
WMGM
Y4
x
0 = Update GPR 9
1 = Update BAR
Figure
6207B
Y
I
I
Figure
6207B
o = 140 1 Addr Even
1 = 1401 Addr Odd
Y5
WM
Y6
0 = Mad 40 Addr Even
1 = Mad 40 Addr Odd
Y7
0 = Gather
1 =Scatter
IQT209
I
00
I
8O+DO
I
Set Y6
10
CO+OO
SetY6
CO+Ol
ResetY6
80+01
ResetY6
I
Reset Y4
LTM'" -- -----
I
I
I
SetY4
I
____________ --.JI
Read 1401 Storage
(2 Characters)
Incr Addr by + 1
Incr Mod 40
Addr + 1
Set Zeros
into CO
Figure
6207B
Decrement
Count by I
W
Figure
6207 B
Yes
Equalize
Character
Set Y5
Equalize
Character
into GPR 8
Byte 0
(Split Op Flag)
Set Y3
Set CO to 00
Special
Character
Off
Test and
Translate 4
Numeric-Zera
Characters
Add 40 to Character (Character
is Xlated with
NaWM)
Add CO to Character (Character
is Xlated with
NaWM)
X lated Character
is in 80
I
Set Mad 40
Ext Addr Bits into
GPR 8. Reset
a II Stots Except
Y2, Y3
Off
10
MM
LTM
inta CO
MIL
LTM
Set Mad 40
Ext Addr Bits into
GPR 8. Reset
011 Stats Except
Y2, Y3
Character
into CO
ResetY5
Figure 601
(Mad 40 I-Fetch)
Set IF
into 01
Figure 6221
(Branch Table)
FIGURE 6207C. GATHER (DOS COMPATIBILITY FEATURE)
@
Bit
0
2
3
4
6
7
0
2
3
4
5
6
7
%
BO Byte
Means
Divide
Remainder Si n
A-WM
Minus Sign
RC MO
B-WM (Mult)
IZT Zera (Div)
Stats
Carry
First Scan
BAR Odd
AAR Odd
Camp Add
X orMO
X orY
Put AAR in CAR
Put BAR in DAR
Read A Field Sign Digit
Test AAR
QT 210
Even
Test BAR
Even
A Field
Minus
+0,....
QT 212
6208B
01
Test
r---------...::.;.~ Y6, BO Bit 0
----~---Invert Y5
Put DAR in A Reg
Read Out B-Field Sign Digit
Read Out A-Character
Minus
QT 213
6208B
Invert BO Reg Bits 4
and 6, Set Bit 2
Set Y2
B-Field
+ or-
Plus
I
I
I
I
I
I
QT 214
-~
I
I
I
I
6208B
1
QT 215
I
I
I
I
Complement
True
A
FIGURE 6208.
1401 MULTIPLY AND DIVIDE
I
I
6208A
Bit
0
2
3
4
5
6
7
BO B te
Means
Divide
Remainder Sign
A-WM
Minus Sign
R C MQ
B-WM (Multiply)
IZT Zero Divide)
WM
B Char
WM
N01WM
Y
0
3
4
5
6
7
Stats
Carry
First Scan
BAR Odd
AAR Odd
Comp Add
X orMQ
X orY
Add B1 Reg to Co Reg
Put Result in Bl Reg
if YO = 1 Add +1 (Carry)
OT214
Yes
First Loop
Others
10
, - - - - - - - - " ' Test Y2, Y7 ~--------~
Generote No Zone
Configuration (0111)
B 1 = 70 + CO (Hex)
o
o
OT 212
First
Multiply
Loop
Yes
Test Bit 2
of BO Reg
No
Use "No Zone"
Configuration
Cl = 70 + Cl (Hex)
Put Standard +
ar Standard Over Units Byte
af Product
OT 210
Put MQ A-Character
in Bl Reg With
"No Zone" Bit
Configuration
Store B1 Reg at BAR Address
Decrement BAR (-1)
Invert Y3
11
OT 211
10
01
Y
MQ
F
6208B
6208B
Test Bit 3
of BO Reg
6208
FIGURE 620SA.
00
r-------------~~---_< TestY6,Y7~-----~---------------
1401 MULTIPLY AND DIVIDE
o
Multiply
o
Divide
o
OT 211
Arith Oflo
OT215
Set Oflo Indicator
in GPR - 7
6208
6208
6208
I
Divide
Overflow
I
I
I
End
8
X 6200
QT 000
Decrement DAR (-1)
1401 I-Fetch
Reset YO,Y2,Y4,
Y5,Y7
Set Y6
Set Bl Reg = 00 Hex
~ ~ DAR in ~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
6208
End
X
BO
Bit
0
2
3
4
5
6
7
FIGURE 6208B.
I
I
I
I
I
6200
QT 000
1401 I-Fetch
OT 214
6208A
__ L ____________ _
Byte
Means
Y
Stats
Divide
Remainder Sign
AWM
Minus Sign
RCMQ
B WM (Multiply)
lZT Zero (Divide)
0
2
Cany
First Scan
3
BAR Odd
AAR Odd
Camp Add
XorMQ
X orY
1401 MULTIPLY AND DIVIDE
Read Out B-Char
Set Bit 6 of BoReg
if B-Word Mark
4
5
6
7
L
?
M
Stats
Means
Z A or Z S
Z A or Z SEnd
M LCWA
A-End 1
A-End 2
Skew
B-Odd
Y
0
2
3
4
5
6
7
OT 203
10
01
Address
Doubler
Length 11
No d-Mod
Clear Old AAR
01
00
YO Set if I - Fetch
Detects a % or @ in
The Second Position
of The Instruction
6210
QT 222
L-------------------r---~---
o
--- --- ---
WM
Yes
OT 217
No
6223/6224
Move-Binary Code/becode
QT 305
LOp
Reset Bits 2 ahd 3
of Char
Test Y3
Put Char inC Reg
~-
I
(- )
I
AAR-BAR=1
Yes
Special C~e
MR-BAR
A
OT203
OT 212
I
I
I
L __ , __
11
6209A
I
00
I
I
I
Invert Bit 4 BO Reg
Set Minus Sign in
Character
Read Out B-Char
Decrement BAR (1)
Set Y5
I
I
I
-----~
OT218
10
Read Out B Char
Decrement BAR (-1)
Use B-Char WM
01
6209B
00
01
10
11
6200
X QT 000
1401 I-Fetch
FIGURE 6209.
1401 MOVE, LOAD, ZERO AND ADD, ZERO AND SUBTRACT
Stats
Means
Z A or Z S
Z A or Z SEnd
M LCWA
A-End 1
A-End 2
Skew
B-Odd
Y
a
2
3
4
5
6
7
E,E
E,O
0,0
O,E
QT 217
First A-Char to Skew-Bfr
SetY6,Y7
Save BAR
Decrement AAR (-1)
Set Y6, Y7
6209B
Odd
AAR
Even
r-------------------------------,
10
M,ZA,ZS-OP
01 11
Test Y4
o
One Char to D 1 Reg
WithWM
Pair of Chars
to DO Reg
Pair of Chars
To DReg
With WM for
DO Char
QT 219
QT 219
2 )--------<1
00
.----------<
01
Test Y4, Y5
'>---------~
r---
6209A
Increment AAR and BAR (+1)
Put A Reg in AAR
WM
6209
01
Put Bl Reg in
Dl Reg with WM
Set Y4
Set B1 Reg = 01 (Hex)
WM
I
I
I
I
I
I
I
I
I
I
_ _ _ ...J
B-End 1 or 2
Test
End-I>
and End-2
~---------___________.....:.,6 (Hex)
4 (Hex)
Error
Set AO= 01
Emulator Program Branch Table
FIGURE 6210.
No
1401 I/O M, L,U OPERATIONS
Branch
(Y6)
Convert Op Code
to Binary Number,
Store in DReg
Y6 = 0
6200
QT 000
1401 I-Fetch
Y6= 1
d-Mod
Yes
=):(
No
Yes
>-___________________
---,
Yes
No
Yes
No
,..-_________
--<
d-Mod = S
OT223
No
Yes
Store DReg
in GPR-2
Set B1 Reg = OD {Hex}
Error
Store DReg
in GPR-2
Set D 1 Reg = 06 {Hex}
Store DReg
in GPR-2
Set D 1 Reg = 6F {Hex}
Store DReg
in GPR-2
Set B1 Reg = OE {Hex}
FIGURE 6211.
1401 UNIT RECORD OPERATIONS
A
B
6212
QT 224
6212
QT 224
K
d-Mod
Yes
.-----< d-Mod = n
= 0_9 Char>------,
Yes
, - - - - - - - - < d-Mod
=•
Yes
No
OT 225
OT 224
Pocket
Select
Yes
Yes
No
Yes
Yes
Yes
Pocket
8
No
Yes
Yes
6211
Unit Record Ops
QT 223
_I
Add 60 Hex to Contents of Bl Reg
Store Result in 01 Reg
6211
Unit Record Ops
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ --l
QT 223
Branch
o
y6
6220
C
QT 300
Emulator Program
Branch Table
,FIGURE 6212. 1401 CARRIAGE CONTROl AND STACKER SELECT
00.-----------------,
Use correct AAR, BAR
10
01
No Addr
Use Old AAR
(B-A)
Odd AAR
Sets Y7
1Add~r------L-----~
2 Addr
A Reg-LS E3
(New AAR-BAR)
Odd AAR Set Y7
Odd
BAR
6213A
QT 228
L -________________~------------
Loop
Y
0
2
3
4
5
6
7
~
QT 227
A-Field Char Fetch
Means
B-Field WM
BAR (Mod 2)
AAR (Mod 2)
Zone Carry
Tens
Hundreds
Numeric Carry
B1*-+tSO-Z
LS E3-A Reg
(BAR)
Special Char Test
YCD
o
Special Char
Remave Bit 4
Save AAR
~
B
6213A
QT 228
Adjust
~-----------------------~
Read Out
140 1 Storage
B-Field Char Fetch
Decrement
BAR(-l)
C Reg-LS E3
(BAR)
Char- C 1
o
Save B-Field Zones
YCD
QT 228
o
Previous Loop
Carry Test
Y7
o
Decimal Add A and B Field Numerics
FIGURE 6213.
1401 ADDRESS MODIFY
Y
0
2
3
4
5
6
7
Means
B-Field WM
Bar (Mod 2)
AAR (Mod 2)
Zane Carry
Tens
Hundreds
Numeric Carry
Hundreds Position Char/Carry from Decimal Add
01
00
11
10
Carry
Hundreds
Hundreds
BO+CQ-BO
Read Out B-Field Char
BO. 40- Z
Add A and B - Field Zones
Zone Carry/Word Mark
10
QT 228
11
10
01
00
Hundreds
Reset Y7
LS E3-C Reg
Store Char BO=20
Zone
Carry
LS E2-A Reg
Set Y4
Loop
Reg
Set Y5 B1=00
Invert Y2
Adjust
End
A 6213
or 227
FIGURE 6213A.
1401 ADDRESS MODIFY
B 6213
QT 227
X
6200
QT 000
1401 I-Fetch
Special Clear Storqge
Instructions are Entered
When A Diagnose Instruction is
A
Issued by the Emulator Program
-/
-
B
Set
Clear
Word Mark
Storage
6200A
6200A
01 Reg = 0 2 Hex
1
1
0', Reg = 34 Hex
1
1
Clear
Word Mark
I
I
6221
QT 302
,7
6221
7
Clear 1401
Storage
Locations 0-80
83400741
I
I
I
I
Clear All
1401 Storage
QT302
83300741
I
Generate 80
Generate F999
for Special BAR
L-___
ro_r_S~p~e~ci-a-I-BA--R--~
I
I
aT 229
A
Jr
I
11
I
I
00
I
.-+-____
7__-< Test Lenllth >-__. .:.4______,
I
I
10
Length 7
Length 8
101 Reg to Stats
I
I
101 Reg to Stats 1
Decrement IAR (-I)
I
YS
I
0
-- ------ ---- ~- - ' -
~
e
I
I
I
101 Reg to Stats 1
~,
1
Set Y2, YS
Set BO and B1 = 30 (Hex)
Reg Contains EBCDIC-II Blanks
___ J
Insn Length = 1
Insn Length = 7
Use New AAR from A Reg
Insn Length = 4
Use New AAR from A Reg
Set Y 4 to Indicate No-Branch
Put New AAR in BAR and Use
BAR for Storage Cycles
Set BO and B1 = 30 (Hex)
B Reg Contains EBCDIC-II Blanks
Save Old AAR
Set Y4 to Indicate No-Branch
Use BAR for Storage Cycles
Set BO and B1 = 30 (Hex)
B Reg Contains EBCDIC-II Blanks
Use BAR for Storage Cycles
Set BO and Bl = 30 {Hex}
B Reg Contains EBCDIC-II Blanks
Read Out 1401 Storage
Decreme nt 140 1
Set YCI if 'Barrow from
Address (-1)
Hundreds Character af Address
~
Ol
SW
00
Set Bit 0 = 1 of
1401 Char
Stats
10
CS
CW
Set Bit 0 = 0
of 1401 Char
1
On
I
I
Set Storage
to Blanks
Y
Means
2
3
4
S
6
7
Not End CS
Reg CS Op
CS No BR
CS
SW
End Not CS
Off
Test YCI
Set YCI if a Wrap Around Occurs,
aT 221
Wrap Around Indicates all Storage Cleared
Correct 140 1 Addr
Reset Y2
r -_ _ _
CS
I
,---,-1_<~>-
Not
I
I
~1
____
0
0
_ _ _-,
CS End
CS 1
Put Updated
Address in
__<~>-----0~--~--,
00
.--~=------<
~nd
Not CS
~
.-------<
Test Y3. Y4
'>-_ _
~
11
Put BAR
in A Reg
Set Y7
o
Off
Test Y7
Not End
>----,
A Reg
I
Not CS
Test YCI
On
Put Updated
Address in
A Reg
6011
QD 001
Mod 40 I-Fetch
Emulator Pragram
Next Instruction
FIGURE 6214.
Y 6200
QT 000
1401 I-Fetch
Branch Entry
1401 SET WORD MARK, CLEAR WORD MARK, CLEAR STORAGE, AND SPECIAL CLEARS
X
6200
QT 000
1401 I-Fetch
6200
X QT 000
1401 I-Fetch
Set BO=FO (Hex)
lS E3-C Reg
o
1 or 2 Addr Case
No Addr Case
OJ-CI-Y
lS E2-A Reg
1 Addr
Odd
OT 229
Even
Dl+Z- BI
C Reg-lS E2
Reset Y6
DO+Z-Bl
C Reg-lS E2
Set Y6
Odd Address/Word Mark
00
10
lS E3 -A Reg Read
Out 1401 Storage
Set Y2 Decrement
BAR (-1)
o
Store Char
C Reg-lS E3
BI=70
loop
OT 300
Emulator Program Branch Table Entry 123
FIGURE 6215.
1401 MOVE CHARACTERS AND SUPPRESS ZEROS
Save(O Id) DReg
Increment Addr(+I)
(SI+I)-Dl
Set Busy Stat
The total (S+I) is put in Dl to
allow decimal correction of
the address.
Storage
to DReg
Storage
to DReg
QT 252
D- W4
Reset End Stat
I
TO= SO-Move
TO= 01-Load
I
I
I
I
Load
I
I
J
QT 251
End
Set Count = 0
(Tl= 0)
Set YCHLI = 0
No End
Set Count = SO
(Tl= SO)
Set YCHLl = 1
Restore (Old) DReg
Reset Busy
Return to Previous
Operation
FIGURE 6216.
1401--1 AND 2 BYTE DATA SERVICE
xx
675
Put Contents af
LS 2F in A Reg
Low Count ta T1
Decrement CCW
Addr -2
Clear UCW2
* ADO
YCH3
ALU/o
10
00
r--(
Chain
Bit On
Decrement CCW
Addr -2
Clear UCW2
)
--
-{
First"
CCW
11
01
Decrement CCW
Addr -2
Clear UCW2
* ADO
)
Count to A Reg
Read CCW 3rd HW
Decrement CCW
Addr -2
Clear UCW2
Caunt to A Reg
Read CCW 3rd HW
Q8531
.--_ _ _ _---'-N""o'-I~O,--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--,
BCE
BWZ
01
- - - - - - -- --- --- ------ ---
------1-------
I
I
I
I
r------------< Test d-Mod '>----'0'--_ _ _ _ _ __
Bit 7
No
OT 301
WM
Yes
No
Put Char Zone Bits
in DI Reg
Put d-Mod, Zone Bits
in BO Reg
d-Mod = I
Yes
r - __________
I
I
Equal
I
EQUAL
L __
6200
QT 000
1401 I-Fetch
Save Char
in BO
Recycle With
d-Mod in BI
6200
QT 000
1401 I-Fetch
FIGURE 6219.
Y
6200
QT 000
1401 I-Fetch
Branch Entry
1401 BRANCH IF: WORD MARK OR ZONE, BIT EQUAL, OR CHARACTER EQUAL
Compare
Not Equal
I
Invert Character
Zone Bits
Store Char in DReg
OT 302
J
Y
6200
QT 000
1401 I-Fetch
Branch Entry
SY22-2842-3
FES: SY22-6827
A
6207
OT 209
C
D
6210
OT 226
6212
QT 224
6210
OT 222
G
6215
OT 229
6222
OT 303
H
6222
OT 304
OT 308
K
6225
OT 310
6200
OT 009
6210
OT 226
OT 601
File Op
Decode
QT 300
Use OAT function to address
emulator program branch table
FIGURE 6220.
1401 EMULATOR PROGRAM ENTRY
Mod 40 I-Fetch Diagnose
DOS
Compatibility Feature
Diagram
Diagram
YA
YA
Microprogram
Y8
YB
Microprogram
CAS Page
CAS Page
6205
0
0
C
Mul tiwoy Branch
0
Transfer O-Reg to BAR
OT 204
QT 304
6207
1
0
6200
D
Scatter-Gather
0
To 1401 I-Fetch
OT 207
OT 302
6200
6214
3
0
E
Clear 1401 Storage
0
Branch Satisfied
Return to 1401 I-Fetch
OT 221
QT 302
OT 302
6214
4
0
Clear
1401
Locations ~BO
F
0
Tape load Made
Insert GM in 1401 Storage
OT 221
OT 256
6206
9
0
F
Increment Address
3
Tape load Made
OT 256
6206
8
F
Decrement Address
8
Tape Move Mode
Insert GM in 1401 Storage
OT 207
0
F
Read Column Binary
QT 309
6225
B
0
Punch Column Binary
QT 309
.FIGURE 6221.
1401 DIAGNOSE
6218
OT 256
6225
A
6218
Insert TM and GM in 1401 Storage
OT 207
9
6218
B
Tape Move Mode
Insert TM and GM in 1401 Storage
6218
OT 256
Character at d for B I d Branch
Branch On
d
Unconditional
*
Carr Chan 9
T
"last Card" Switch
U
Sense Switch B
Z
Sense Switch C
? Reader Error
Sense Switch D
Sense Switch E
:j:
Printer Error
Sense Switch F
@ Carr Chan 12
Sense Switch G
d
b1
9
o
A
B
C
D
E
F
G
H
I
S
Test Y5
%
6219
Branch if
Character Equal
o
6200
OT 000
1401 I-Fetch
Branch Entry
Bits 0-3
of d-Mod
Bits 0-3 of d-Mod in Hex
~
o
6
4
Invalid
Set Dl Reg
~OF (Hex)
No
Set D1 Reg to
d Mod Digit (Hex)
Invalid
J!
~O}
~ 1
~ 2
l~3
P~7
~ 8
R~9
K
Hex
o
6220
OT 300
Emulator Program
Branch Table Entry
OT 303
Read Out
Indicators
from GPR-7
Read Out Sense
Switches
from GPR-7
X No!,
6200
mooo
Bits 4-7
of d-Iv'od
1401
I-Fetch
Bits 4-7 of d-Mod in Hex
*
+
Error
Reader
9
8
0
?
I
Store Ind
Set D1 Reg
~ 13 (Hex)
Set D1 Reg
~ 14 (Hex)
On
On
Set D1 Reg
~ 16 (Hex)
On
Emulator Program
Branch Table Entry
6220
OT 300
Emulator Program
Branch Table Entry
Bits 4-7 of d-Mod in Hex
6200
6200
OT 000
1401 I-Fetch
Y OT 000
1401 I-Fetch
Branch Entry
~
5,6,7,8
Invalid
Set Dl Reg ~ OF
Store Indicators
Yes
6220
OT 300
Emulator Program
Branch Table Entry
Emulator Program
Branch Table Entry
6200
X
OT 000
1401 I-Fetch
*A
Branch Entry
Branch to A-F (Hex) is Not Possible
OT 304
H
FIGURE 6222.
Machines Which Allow d Mod of , Set Dl"OB
1401 BRANCH TESTS
6209
Move and Bi nary Decode
M Op C ode
A d - Modifier
A
Clear Old AAR
Use AAR from A Reg
Set Y2, Y6
Reset Other Stats
Read Out A-Char to DReg
Put AAR - 100 in C Reg
OT 305
Use AAR
Put C Re~ in AAR
Invert Y2
Put A-Char in B Reg
Read Out B-Char
C Reg
-- -- --
-- - -
--
--
Use BAR
= BAR-l
--
---- ----
Put C Reg in BAR
Regen B-Char
Strip A-Char Word Mark
Put A and B-Chars
in C Reg
B-Char
WM
WM
NoWM
Set Word Mark in
B-Char
Set Y4
OT 306
I
Read Next B-Char
A-Char
WM
AWM
No
1
Test Y4
B WM
I
0
Regen B-Char
I
Regen B-Char
C Reg
= BAR -
1
Put AAR in A Reg
1
Test Y2
0
Read Out A-Char
Put AAR + 99 in
C Reg
X
FIGURE 6223.
1401 MOVE AND BINARY DECODE
6200
OT 000
1401 I-Fe tch
Move and Binary Code
MOp Code
B d-Modifier
Use AAR
OT 305
o
Test Y5
Read B-Char from
Storage
Put A-Char in B Reg
C Reg =BAR-lOO
Read B-Char from
Storage
Put A-Char in B Reg
C Reg = BAR +99
B-Char
Yes
WM
No
OT 306
A-Char
A-WM
WM
B-WM
Test Y4
o
Regen B-Char
C Reg=BAR-1
Put AAR in A Reg
X
FIGURE 6224.
1401 MOVE AND BINARY CODE
6200
QT 000
1401 I-Fetch
Use BAR
Data Address from
or 302
6221
or 302
6221
Read Column Binary
Punch Column Binmy
Op 83A00741
Op 83B00741
Set J Reg = Fl
Cleor LS 04
Set A Reg = 0401
Y61s On
LS Fl-A Reg
C Reg = 0401
Cleor LS 04
Set Y5
GPR9 to A Reg
Data in Emulator
Program Storage
Reset Y5
C Reg-LS 04
(1401 Addr)
Read Data from Rd Bfr
Increment Data
Addr (+1)
QT 309
<0
1_
o
Reod ....
Punch
Bl Reg- DReg
D Char to Pch Bfr
D-8 (Char)
Translate Char
Storage
to EBCDIC-Ii
Data Addr-LS Fl
1401 Addr-C Reg
No
End
Yes
Punch En
I
LS 04-A Reg
(1401 Addr)
I
Set Dl=05
6220
OT 300
0
1
Y6
Emulator Program
Branch Table Entry 5
I
Reod 1401
Add 100 to
1401 Address
I
Location
A+l00-C
Invert Y6
I
J
Read 1401
Locot;on
A-99 -C
I
Subtract 99
from 1401 Address
Invert Y6
"~,~'0
o
---------------------1------+------------------------Punch
Read
Regen 1401 Location
Translated Binary
Data Stored in
Char-BO Reg
Translate Char
to EBCDIC-III
Translated Char
to B1 Reg
Word Marks
Are Removed
Loop
1401 Storage
LS Fl-A Reg
(GPR 9)
No
1401 Storage
Word Marks
Are Retained
End
QT 310
Yes
Read End
A Reg-LS Fl
Set Dl=10
6220
OT 300
I
Emu lotor Program
Branch Table Entry 16
FIGURE 6225_
1401 READ AND PUNCH COLUMN BINARY
QT401
QT402
6200 C
Even B-Address
A Reg
A Reg = 86,87,97
- - - - --- --- --- --- --- --- ---
-:~~=:-'S~t-0-re=7N~-S"'C~2~,N-'S~C::-3-,~i-n--:--L:S""(l::~1)~~~----,- - - - - - - Read Out Hundreds Position of Index Factor
=86,
87, 92, 97
T ---- -:s::-,=ore~~N~S::-C:2=,~N~S-::C-3-:-in-.I.L-::S=(l::1:)~-----::-R-e~ad~""-o"'-u--,,-.
--- --- - - - - - -- -- - - -
Hundreds and Tens Positions of Index Factor
Clear L S (02),(06)
Store (Old) B Reg in L S (02)
Force on Bits 0 and 1 of Hundreds Character
Put Hundreds Char in 81 Reg
Fonn 60 + (Hundreds Char Digit) oqOO
Se' Address (A Re ) '0 0094
Put Tens Position of Index Factor in SO Reg
Read Out Units Position of Index Factor
Carry
(yCD)
No
Carry
(YCD)
Increment A Reg (+2)
S'ore (Old) B Reg in L S (02)
Put D Reg in B Reg
Read Out Tens and Units
No
Positions of Index Factor
QT 404
QT 403
Force Bits 0 and 1 of Hundreds Character
No
Put 0000 (Units Digit) in AT Reg
DReg
Now Contains (Tens Char), (Hundreds Char)
Put 0000 (Units Digit) in
Ai
Reg
Put (Tens Char) (Hundreds Char) in DReg
QT404
QT405
QT 405
6200
QT002
FIGURE 6226.
1401 INDEX FACTOR FETCH
6200 A
QT003
6200
QTOOO
6200A
QTOO4
NSC1 or NSC4
a Valid
Character
No
Yes
No
Put Tens and Units Positions
of Index Factor in B1 Reg
Store NSC1 or NSq in L S (06)
7 Char Even, 4 Chor Odd
o
Form Tens and Units Positions of Effective Address
Put Result in B1 Register
Tens or Units Invalid
Test Tens and
Units Positions
Address
for Valid Digits
Units
Valid
QT 400
Form Tens and Units Positions of Effective Address
Use Corrected Digits and Put Result in B1 Register
Tens or
-< Units Digit
' -_ _ _ _ _T_e_ns_o_r_U_n_its_ln_v-"ol_id_ _
Invalid
Tens and Units Positions
of Effective Address Valid
Form Hundreds Position of Effective Address
Put Tens and Units Positions of Effective Address
in
D1 Reg
o
7 Chor Even 4 Chor Odd
Form Hex Position of Effective Address
Put Hex and Hundreds Positions in Co Reg
Form Hex Position oJ Effective Address
Put Hex and Hundreds Positions in Co Reg
Transfer Tens and Units Positions from D1 Reg to C1 Reg
00
01
Effective Address (HDDD)
Effective Address (HDDD)
Y6,Y7
Transfer Tens and Units Positions from D1 Reg to C1 Reg
10
11
Effective Address (HDDD)
Effective Address (HOOD)
o
Effective Address (HDDD)
Effective Address (HDDD)
Now in C Reg
Now in C Reg
Now in C Reg
Now in C Reg
Now in C Reg
Now in C Reg
Restore B Reg
Restore B Reg
Restore B Reg
Restore B Reg
Restore B Reg
Restore DReg
Even B-Address
Odd B-Address
6200
QTOOO
FIGURE 6227.
Y5
1401 INDEX ADD
7 Chor
Odd A-Address
6200A
QT003
6200A
QT005
6200
QT004
6200 A
QTOO5
Odd A-Address
4 Chor
6200
QTOO3
Bits 0-3 *
Bits 4-7
1000XXXX
1001XXXX
1010XXXX
1011XXXX
1100XXXX
1101XXXX
1110XXXX
Zero and
Add
QU401**
6324***
QU311
6316
Zero and
Subtract
QU401
6324
/
Invalid
Op
QU506
Clear
Branch if
Char Equal
QU221
6311
Compare
J
K
Branch if
Int Ind On
QU211
6310
QU401
6331
Data
Move
QU401
6324
Move Char
and Edit
QU508
6341
Stkr Select
and Feed
QU507
6339
L
Rd or Wr
with WM
QU501
6334
M
Rd or Wr
without WM
QU501
6334
N
No Op
S
Subtract
T
Table
U
Unit
llllXXXX
Blank positions in matrix are invalid op codes; branch to QU506
* Bits 0-3 = 0000-0111 are invalid
**
***
FIGURE 6300.
CLD page for start of microprogram
Figure number of maintenance diagram
1410;7010 OPERATION CODES IN EBCDIC II
Forms
Control
QU507
6339
Branch if
I/O Ind On
QU201
6309
Invalid Operation Codes
QU506
QU506
6306
V
Store
Addr Reg
QU251
6312
W
X
Y
Z
Move Char
and Sup Zero
QU508
Stats
Y2
Odd Address
Y4
GOp Code
Y5
Second Address
Local Storage Contents
LS 01
LS 02
LS 05
I
Working Instruction Counter
Translated Op Code, TTh Position
Odd Character
QOOOI
00
01
10
I/O
QU104
QU506
QUI13
Error
Link
2400
Modify Ie + 1, Process
XI and X2
Modify Ie +2, Process
X3 Set Y4
r-----~----~
Use IC to Read MS
r--~~------~
Process Ten Thousands
end Thousands Address
Positions, Modify Ie +1
I/O B
Address
Write System Status
Address Odd
,..-_ _....L..._..L...,;:U:;se::...,:.IC:::...;to Read MS
Process Hand T Address
Positions, Modify IC +2,
Use IC to Read MS.
Process U and d
Modifier, Modify IC +2
Even
and d Modifier
at F8
Read d Modifier,
Modify IC +1,
FNB
I/O and
Non
00
01
and
6306
Interrupt
Ops
QUI51
,..----'---'-----,
See Fi gure 6308
Indexing
QUI51
00
.01
QU109
Non-Interruptible and I/O
Interruptible
FNB for
CPU
Inter-
ruptible
Ops
FIGURE 6301. 1410 E INSTRUCTION-FETCH OVERALL
6304
QUI04
2 Addr
1st Pass
Stats
Y1
Y2
Y6
First Return from Diagnose
Odd Start Add ress
2 Address Type Ops
QU101
Priority
Interrupt Use
Add ress 00101
Compute Disable
Use Original IC
Read Working
IC --A
Set Y4, 6, 7
Reset PRI Bi t, System
Stat B,
Original IC _ _ A
Read Working
IC--C
Read BAR
Buffer - Z
Off
Modify Original
IC +6 for Interrupt
IC Address
-
On
Store New System
Status with PRI
Alert Reset
Read Working
IC-ZSetY6
Read Original
IC_A
Reset Y6
(Y1 0 n for the
Fi rst Return from
a Diagnose)
Read Original
IC _ Z , SetY6
Read AAR
Buffer_A
Generate 00101 High
Order, Read Out
BAR Buffer
Generate 00101 Low
Order, Original
IC +6 to BAR
Buffer, Set Y6
Write Working
IC Original
IC, Modify
IC +2
--(
Set Y2
)
Yes
Modify IC (Hi)
- C O , Read
LS02 _ Z
- {
Reset Y2 )
11
Write Working
IC at F7
Reset Bit 12
of ROS
01
Write Working IC
at F7, Generate
20 for Table Address
Op Code Table Starts
at Hex 20XX
QD001
Y2
Move New Op Code
Move New Op Code
DO _ A 1 to Form
D1_A1 to Form
~
~
Table Address
Table Address
L--------r------~
'-___
Re_s_e_t_Y_4_-_7~.JL-------~------~
No
NOP
Test
WM
Read Storage Table,
LS 02
Write 11 Read Translated Op
at FO
Odd
11
NonInterrupt
Ops
FIGURE 6302. 1410 E INSTRUCTION-fETCH START
00
6306
QUl13
6306
QUl13
Even
10
01
Invalidor
CPU
6304
QU104
I/O
6303
QU102
Unas-
signed
Ops
Emulator
Program
Error Link
2400
{
YA Stats
0-3 are Reset
)
'-----'~-
Stats
Y2
Y5
Y6
Odd Start Address
2nd Pass of Address
2 Address Type Ops
6302
Read IC +2
from F7 A
QU102
QUI03
Read lS (2)
forOPNT CO
X Control Field Ops
2 Character Op-d Modifier
Even
Odd
Even
Odd
d Modifier - - CI
Read System
Status and
d Modifier at F8
Skew XI,
Subtract 12/0
Write Working IC
Modify IC +1
CI, Move
IC C
d Modifier - - CI
from C 1 Read System
Status and
d Modifier at F8
X I Invalid
Move IC +3 to A
Move X I to BI
X2 WM
WM
NoWM
X2 CO Write
OPNT and New X I
at FO
Write OPNT,
X I at FO
Modify IC +2
Write OPNT and
XI at FO
Reset Y4-7
Wri te System Status
and
d Modifier at F8
Set Y5
Write New
X2, X3 at FI
Read FI for
X2 and X3
X3 - C I
Modify IC +2 to A,
Write New X2, X3
atFI, SetY5
X I Error
Regenerate X I at FO
Reset Y6
o
o
6304
IBO QUI04
I/O B Address
Odd
FIGURE 6303.
XCE
6305
QUI09
Even X Control
Field
1410 E X CONTROl FiElD READOUT
IBE
6304
QU106
I/O B Address
Even
XC
6305
QU109
Odd X Control
Field
EL 23
QU506
Error link
2300
rco
6305
QUI12
2-Character
Ops
Stats
Y2
Y4
Y5
Y6
Y7
CPU
Start Address Odd
Na Index Op
2nd Address Pass
2 Address Type Ops
Zane in Hundreds Position
I
QU104
6302
I
I
Read Out IC +2
to A Register
I
Start Address Even
r -______________________________________________________
I
T'~d
Mask Test* Ten
Thousands from Cl ~
B1, Write Translated
Op/Xl in FO
6303
Second
Address
I/O B Address
Odd
6303
I
I/O B Address
IBE
Even
Start Address Odd
I
ART
Write Translated
Op and Xl to
G PR Buffer FO
Modify IC +5 C
6308
I
I
Return
Mask Test Ten
Thousands from C 1 - B1, Write Zero in F7
I
I
-<~a~~:~>-------------------------------+----__________________-,
I
I
I
I
Test Odd
(Y2)
IBO
QUlO6
I
Read Out AAR Buffer
Modify IC (Hi) -
I
I
I
C
Mask Test' Ten
Thousands from DO to B1
I
No
Odd
FXPTO
l§J
Yes
UII
Chain
Test
Odd/Even
I
Even
I
- - - - - ...I
,--
6307
QU1l4
Even
I
Write New AAR
in GPR lO (F5)
Modify IC +6
I
I
Mask Test Ten
Thousands from D 1_
Bl Write New AAR
I
No
FXPTO
L%J
UII
Chain
Odd
Yes
6307
QUl14
Modify IC (Hi) to CO
Set Y5
I
Modify IC +2 to A,
Read LS (2) to Z
I
Mask Test Ten
B1
Thousands Pas -
I
Hi IC ___ CO, Write
OPNT in LS (2) Modify
IC +4 _ C , Write
IC +2. in F7
~
I
I
NO
FXPTO
l3§J
Yes
I
Mask Test Thousands*
Write IC 6/11
in LS (1)
Modify IC + 4--C
Write OPNT and Ten
Thousands in LS (2)
Modify IC +2 to A
Modify IC (Hi) to C
Set Y5
alf
Chain
Odd
I
6307
QU1I4
I
I
I
0
I
Mask Test Thousands'
from Dl--BO Write
OPNT, Ten Thousands
_
LS (2)
I,------<.
N0
l§J
alf
Chain
Even
Yes
6307
QU1I4
Modify IC +2 to C,
Write LS (1) with
IC +6/12
Modify IC (Hi) to c,
Read LS (4) - Z
Modify IC +2-A
Read LS (2) - - Z
I
I
JI
I
-I-
--------------
I
Mask Test Hundreds'
from Dl ___ Bl
QUlO5
I
Mask Test Hundreds'
Move IC +6--A
QUlO7
Mask Hundreds
Zns to B1, Read
LS (4)-Z
Mask
Hundreds Zones
See Table
See Table
No Zones
No Zone
Hundreds
Zones
I
Zone
Mask Test Thousands'
from Dl - C l
Write IRA
to LS (4)
I
Generate IRA
50,70, or 90 ___ Cl
Test No Index
Op (Y4)
I
I
Skew Thousands,
Combine Hundreds to CO
Read LS ( 3 ) - Z
I
Skew Thousands,
Combine Hundreds to Cl
Set Y7 if Y4
Not On
Skew Thousands,
Combine Hundreds-CO Read LS (3) Z
I
I
Mask Test Thousands*
from DO---Cl
I
I
I
I
I
Mask Test Units'
from Dl--BO
Write LS (3)-Z
Mask Test Units'
from DO-BO
Write LS (3) with
Units, Ten Thousands
I
I
01, lO, 11
*EL
Branch
on FXPTO and
ALU 0
* Note:
00
>--------,
Skew T, Combine U,
Read OPNT, Ten Th
from LS (2) FNB on
Index Zones and Y7
Each address position is tested for WM or invalid
decimals. If either condition exists the microprogram links to Model 40 I-Fetch
IRA - partial base address of the index register
FXPTO--Fixed Point Overflow
Hundreds Zone Bits
B and A
~
rror
QU506
Link 210
Mod 40
I-Fetch
FIGURE 6304.
14lO E ADDRESS READOUT
IX
6308
QU151
Indexing
8-Leg Branch
00
01
10
Generated
Value
90
70
50
Hundred
Zones
Zones
Generate IRA
50,70, or 9O-Cl
Test No Index
Op (Y4)
Mask Test Thousands'
from D l ___C 1
Write IRA
to LS (4)
Skew Thousands;
Combine Hundreds -- CO
Set Y7 if Y4
Not On
QU108
Stats
FAP
Y2
Odd Start Address
Y4
No Index Op
Y6
2 Address Tape Ops
01
Y
6308
IAN 6308
Shift Op
Code Translated
Addr Obi? Test No
Index Op (Y4 and
AlU 6)
IAddr Dblr
Reod BAR Buffer at F4,
Write Address
to BAR Buffer,
Generate Address
of AAR Buffer
I
Start
log Out
If Errors
Enabled
I
I
~
I
Read at F8
Old d Modifier
Read at F8
Old d Modifier
I
II
Write Address
to AAR Buffer
00
Read lS (3)
for CAR
I
Generate Address
of AAR Buffer
I
10
Read Out
BAR Buffer
at F4
10
Move d Modifier
to BI, Read
Out AAR Buffer at F5
(GPR 10)
~----------<
Read F4 for I/O
Address Modify IC +1
ifY2isOn
STAR
UO
SAN 6308
for dT:;:'difier
II
Move d Modifier to BI
Reset Y3
Write Address
in BAR Buffer
OO-Even Start Address + d
Ol-Even Start Address + d
10-Odd Start Address +d
II-Odd Start Address + d
Modifier
Modifier
Modifier
Modifier
~
L . - - - -O
- I- - - - - - - - - - - -O-I- - - - '
II
for d
~:difier
Odd/Even
Odd/Even
(Y2)
(Y2)
I
Move New d
Modifier from BI
Move New d
Modifier from DO
Move New d
Mod from BI to CI
~
~
~yes
Yes
Move New d
Mod from DO to CI
~
No
10
00
Move Blank to d
r Modifier
Position
I I
Move Blank to d
Modifier Position
Yes
~ ~ ~ ~
No
Set Y6
Modify IC +0
Modify IC -2
No
Modify IC -I
Yes
Modify IC +1
No
WM and Modifier
Error linkage 21
QU506
Set Y5
Modify IC +0
~
QUI09
XCE
XCO
6303
Even X Control Field
Read Out F7
(Working IC) to Z
Read Old d Modifier/
System Stat at F8
Read Working IC to Z
Test Non-Interrupt
Ops
6303
Odd X .Control Field
Read d Modifier to CI,
Read F8 for System
Stat/d Modifier
Modify IC +1
Non-Interruptible
Write at F8
d Modifier/System
Status
QUI12
Write at F8 d Modifier
/System Status
Test 1410
Interrupt
I
~~~-
1
TCO 6303
~~
K, FOps
From CPU Chain Op
Non-Interruptible
I
Branch On 0-4 of
Translated Op Group
I/O, Non-Interrupt
Ops,Write Working IC
Branc h On 0-4 of
Translated Op Group
Write Working IC
(
Go to Execution of Instructions
(See Figure 6300 for ClF page number)
I
I
I
I
I
I
I
1410
Interrupt
No
I
6307
From CPU Chain
Interruptible
Save d Modifier in BI,
Reset Priority Alert
in System Status,Read
System Status/d
Modifier to Z
[29
1Interrupt
I ~~~ I
~/
Yes
6302
QUIOI
Go to 1410 I-Fetch,
Use MS Address 00 10 I
Figure 6302
FIGURE 6305. 1410 E INSTRUCTION FETCH ENDING
I
I
2 Character Ops
6307
QUI12
I
------,
----
I
I
I
I
Test
Interruptible
Ops
Interrupt,iible
Write System Status/
New d Modifier
at F8
Modify IC-I
Branch On
0-4 Translated
Op CPU Group
Write Working IC
(
Branch On
0-4 Tronslated
Op CPU Group
Write Working IC
1
Go to Execution of Instructions
(See Figure 6300 for ClF page number)
I
QUl13
Stats
Y4
6302
No Index Ops
Generate BB in B1
Subtract OPNT
from BB
00 (and)
Not NOP
NOP
o (Y)
QU506
Error
Link to
Mod 40
I-Fetch
No Index Op
No
6304
QU104
6302
QU10l
I-Fetch
FIGURE 6306.
1410 E NOP AND NON-INTERRUPTIBLE OP CODES
QU1J4
All Inputs from
Figure 6304
Stats
Y3
Set for Half Chained
Address Doub Ier
Type Operations
Y3
Also Set for
C Ie~r Storage and
No Branch Ops
Y4
Y5
Y6
Odd Start Address
2nd Address Pass
2 Address Type Ops
No
No
Modify IC -1 to Cl
Write Working
IC at F7
Read BAR -.. Z
(F4)
Read AAR
At F5 C
Modify IC -2 to A 1,
Read BAR Buffer
at F4 Z
Set Y3
Modify IC (Hi)
BAR F4
Write A Address
at F5 (AAR)
Write BAR at F4
Set Y3
Read System Status/
d Modifier to C Register
ResetY4, 5, 6
Wri te (Restore)
System Status
and d Modifier
6305
QU112
FIGURE 6307. 1410E CHAINING
6305
QU112
Modify IC -2 to A 1
Modify IC (Hi)
to AO
QU151
Stats
Y3
Y4
Y5
Y6
Y7
IX
Index Register Address Odd
No Index Op
2nd Add ress Pass
2nd Address Type Op
Algebraic Subtract
6304
Tens Zone Bits
B and A
Address Factor
00
01
10
11
+9
+4
-I
-6
Nh,
on Tens Pes>
Zones and
Y7
101
III
100
Read lS (4)
IRA to D
Emit 30 to DI
110
010
OIl
000
001
No
Inde\
Test Ten Thousands
Numeric 2:8
Ten
Thousands
Subtract I from IRA
Z to A
oAl
~
Add 4 to IRA,
Z to A
Test Ten Thousands
Numeric ~8
Read lS (4)
IRA to D
Emit 30 to D I
Write IC
oAI
~
I~
Read lS (4)
IRA to D
Emit 30 to BI
oAl
~
Subtract 6 from IRA
Z to A
Read LS (4)
IRA to D
~
Add 9 to IRA,
Z to A
Test Ten Thousands
Numeric L8
Test Ten Thousands
Numeric 2:8
Yes
Numeric
~8
Example: 99999
A5
Form Address lS 4
No
Before
TTh
1001
Th
X
HT
X X
U
1001
( ---------------
A
........"""------
........
Bits 4, 5 of units forced to II
after original bits are moved
to TTh Ext Bits 5, 6
Odd
,-------<
This bit lost when address is
translated, extension bit has
only 3 positions.
After
101
X
X
X
5
9
9
9
Odd/Even
>--------.1
Even
Reset Y3 Write lS (4)
with OPNT/Ten
Thousands
Set Y3, Write lS (4)
With OPNT/ Ten
Thousands
1101
D
Right Shift to A I
with Tens and Units
A 1 Save Only Bits
4, 5 of Units
~'-----,-----J
1
seeexamp~'---s-av-e-B~it-s-4-'-5-0-f---'
Modify IRA -2 to Bl,
Read lS (5) to Z
Units in BI
Odd
~>---------,1
Force in C1 an invalid
Decimal Digit 1 1 X X
(C 1 ~ New Units)
Even
r---------<
Odd/Even
Test Sign
Test Sign
J
10
Minus Sign
Move IRA -2 to A,
Write lS (5)
With Address
Move Units to C,
Set Y7(Subtract)
00
l
01
l2;oi 0
AlU;oiO
11
Plus Sign
Plus Sign
Move IRA -2 to A,
Write lS (5)
with Address
Move IRA -2 to A,
Write lS (5)
With Address
I
I
Plus Sign
Move IRA -2 to A,
Write LS (5)
with Address
1
Move Units to C,
Reset Y7 (Add)
0"'&'."
Odd/Even
Mask IXU
Zones to B1
Al
FIGURE 6308.
A2
1410 E INDEXING (SHEET 1 OF 2)
Mask IXU
Zones to BI
A3
I
A4
QU152
Stats
Y3
Y4
Y5
Y6
Y7
Index Register Address Odd
No Index Op
2nd Address Pass
2nd Address Op
Algebraic Subtract
A1
A2
A3
A4
Ten Thousands
Ten Thousands Not 2: 8
No Indexing
Skew Index Tens,
Combine with Index
Units to C1, Read
Address to B- LS (5)
Skew Index Tens,
Combine with Index
Units to C1, Read
Address to B- LS (5)
.2 8
Strip Index Hundreds
8 Bits if
Invalid Decimal
Decimal Add Index
Hundreds and Index
Units to Hundreds/Units
Address, Data to C
Decimal Subtract Index
Hundreds and Index
Units from Hundreds/
UnitsAddress,Data to C
Odd
or Even
(Y3)
Skew Index Thousands
Combine with
Index Hundreds to CO
Skew Index Thousands
Combine with
I ndex Hundreds to CO
Nat Carry
and Not Y
Not Carry
and Y7
Hundreds to Thousands
/Hundreds Address, Rea
PNT Ten Thousands
to B
o
Skew Index Thousands
Combine with
Index Hundreds to CO
Carry and
Y7
Decimal Subtract Index
Thousands and Index
Hundreds from Thousands
/Hundreds Address,
Read OPNT Ten
Thousands to B
Thousands and Index
Hundreds from Thousand
/Hundreds Address,
Read OPNT Ten
Thousands to B
Decima I Add/Subtract
Index Ten Thousands
to/from Ten Thousands
Read Un its/T en
Thousands to D
Skew Index Thousands
Combine with
Index Hundreds to CO
Carry and
Not Y7
Decimal Add Index
Thousands and Index
Hundreds to Thousands
/Hundreds Address,
Read OPNT Ten
Thousands to B
Decimal Add/Subtract
Index Ten Thousands
to/from Ten Thousands
Address, Read Units/
Ten Thousands to D
No
QU151
Put B1 in CX (CX ~
New Ten Thousands)
Read IC to A
Test 2nd Address
Test 2nd Pass
00
A5
6305
FAP QU108
01
6305
IAN QU108
First Address Pass
1410E INDEXING (SHEET 2 OF 2)
11
6305
SAN QU108
Second Address Pass
I/O Address End
FIGURE 6308.
Address/Pass
Y6 and Y5
10
6304
ART QU104
Address Return
Stats
QU201
Y6
Branch Ch 2 - X Op
No
No
Read LS to Get
Y Status
Reset Overlap
Complete Bit in
Y Status Ch 2
Read LS to Get
Y Status
Reset Overlap
Complete Bit in
Y Status Ch 1
6302
QU101
Yes
Ch 1
Ch 1
Ch 2
Reset System
Status Bit 7
Ch 1 Irpt
Set System
Status Bit 7
Ch 1 Irpt
Set System
Status Bit 3
Ch 2 Irpt
No Interrupt
10
00
Interrupt Ch 1 or Ch 2
Go to 00101
I-Fetch Irpt
01
11
Invert Zones
of
d Modifier
6302
QU101
*
of
d Modifier
to Numeric
R Op
No Branch
Reset Ch 1
Interlock to A
QU202
d Modifier =? ! 0
Numeric = 0000
Add 1010
Invert Zones
0
X Op
Branch
Branch
Reset Ch 1
Interlock to A
No Branch
Reset Ch 2
Interlock to A
Reset Ch 2
Interlock to A
No Branch
-Branch
Store R, X Branch
with Interlock Reset
Branch to A
GM
NoGM
Store R, X Branch
with Interlock Reset
I-Br
Store R, X Branch
with Interlock Not
Reset
6302
QU101
6302
QU101
FIGURE 6309.
1410E BRANCH ON CHANNEL STATUS
Stats
QU211
Y7
Branch Priority Test Op
(
(
Base
3000 Hex
}
--
Generate Base for J
Status in AO, Move
d Modifier to A,
Set Y6 and Y7
Read Storage for
Translated d Modifier,
Read J Status at F9
YOp
)
Generate Base for Y
Status in AO, Move
d Modifier to A Register
Read Storage
for Translated
d Modifier,
Read Y Status at F9
Odd
Even
Move Trans lated d
Modifier to C1
Set Y2
Move Translated d
Modifier to C1
r--------- 11
10
Conditional Branch
Byte 1
I
01
Branch Restore
Byte 0
QU212
00
Conditional
Branch Byte 0
Miscellaneous
Set Y5
11
00
Compare
Not Equal
01
No
Compare Equa I
Yes
Cond
Ch 2
No Branch
Store J jY Status
Reset Bit Being Tested
Save Original Status
in A
Compare d Modifier
to Original Status Byte 0
Store JjY Status
Reset Priority
Alert Mode
Reset System/Status
Bit 2
Set System/Status
Bit 5
Yes
Yes
Error-
No Branch
Branch
6302
QU101
No BranchI-Fetch
Use Working lC
FIGURE 6310.
Write System Status/
d Modifier
Reset Y6
I-Br
BronchI-Fetch
Use AAR
1410E PRIORITY TEST AND BRANCH, BRANCH ON INTERNAL INDICATOR
6302
QU101
QU506
Error Li nk 2200
Select Priority
Alert Mode
Set System/Status
Bit 2
Reset System/Status
Bit 5
BranchWrite System Status/
d Modifier
I-Br
6302
QU101
I-Fetch
Branch Use AAR
(
Stats
Y2
Y6
Y7
WOp
(Bit Equal)
v Op
0NM/Zn Equal)
QU221
BCE in Process (for Compare Op)
BOp-Character Equa I
V Op-WM/Zn Equal
Move d Modifier
to B Register
Set Y7
I Move d MOdifier-..B!
d Modifier NT ~ d Modifier Translated
00
10
I
I
Test
d Modifier
for Translate
to BCD
I nvert Zones
Invert Zones
of d Modifier
of d Modifier
BOp
(Character Equal)
II
Move d Modi fi er
to B Register
Set Y6
01
I
I
d Modifier ~ ? !i 0
Numeric ~ 0000
Add 8 and 2
Invert Zones of d
Modifier ond Bit I
Bits to Numeric
1
I
I
I
BO
Storage Character
I
I I
Read BAR
Buffer to A
Modify BAR
-I to C Register
BI
d-Modifier
I
0>----------.1
Modify BAR Hi
o
Due to Borrow
I
Write BAR -I to F4
r-______________
J
~O~d~d~~)_~E~v~e~n--------------,
Odd/Even
Move Odd Character
to BO
(d Modifier Translated) f - - - ___ {
I
Move Even Character
Set Y2
}
to BO
(d Modifier Translated)
____ _
wo,b.o,
00
r----------------------------<
Op~6,
10
>-----------------------------------------------,
Y5)
Strip WM from
Storage Character
V Op 0NM/Zn)
Generate
01
13/0 in CO
1,
~QU445
,n3
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --- - - - - - - - - - - - - - - - - - - QU222
00,10
Storage Character ~
? ! if' 0,
Numeric is 0000, Add 8
and 2 Bits to Numeric
II
Stats
Move d Modifier NT
Bits 6, 7 in
Y Stats 6, 7
Test
Storage Char
for Translate
to BCD
01, 10
II
I
Y6
Y7
k
I
d Modifier Bit 2
d Modifier Bit I
00
d Mod NT for
7 Bit or Any
Bit
[
Exclusive OR d
Modifier and Storage
Character for Zone Tes
Invert Zones and
Invert Zones of
Bit I of
d Modifier
d Modifier
No WM
Test
Storage Char
forWM
WM
Compare
d Modifier and
B Character
ALUif'O
Unequal
No Zone
Test Y6
Zone
for Zones
Pass Zones of
Exclusive OR
Character
Equal
No Match
A'OMo,eh
r-------------------------------------<
are Matched
ALUIO
I-Br
I-Fetch
Branch
FIGURE 6311.
6302
QUIOI
IV I
I-WIC
6302
QUIOI
I-Fetch
No Branch
1410E BRANCH IF: CHARACTER, WM/ZONE, OR BIT EQUAL
'J":Brl
V
I-Fetch
Branch
6302
QUIOI
IV
I-WIC I 6302
QUIOI
I-Fetch
No Branch
QU251
Stats
Y6
Y7
LS 03
O/H
OfT
I Second Address in Loop
C,-_G
C Address Odd at Start
C Address Register
Original Hundreds Pasition
Original Tens Position
.,....:.op_ _)
Store Address Register
A
B
E
F
Generate Address of
Storage Table
20 DHDL
A
= BAI = 4 and "2
= BA2 = 4 and 2
= BA5 = 4 and "2
= BA6 = 4 and 2
Storage ,Test
d Modifier
Odd
Even
Translate Character
for Valid d Modifier
(Bit 7) Read
Address to C
Translate Character
for Valid d Modifier
(Bit 7) Read
Address - C
Yes
No
Reset Y6
Invalid d Modifier,
Error 22,
Write Address
Read CAR to A Reg,
Move T/U Address to
BI Reset Y2 and Y3
IOQ Indicates
add ress to be stored
is ?
80K
See Figu re 6308
on Indexing
No
,..-...l-.--'QU506
Error Line 2200
Keep in BI
Bits 6,7 of U
Odd
Yes
Bit 7
Force Bit 4, 5 of
Units with 00
No
TTh=8
Put Ext Bit 7 in CX,
Move Ext Bits 5 and 6 to BI
Bits 4 and 5 to Reconstruct
Set Y3
Units
CAR
Odd/Even
Skew Tens and Units,
Put Tens in Skew Buffer
Set Y7 if Odd
Skew Tens to
OfT in BO,
Read LS (4)
AI
To Loop
Even
Mask Storage Units
Character Numeric
Combine Storage Units
Zanes and Address Units
Num and Num Made
1------I
I
I
I
I
I
I
QU252
Mod CAR-I to BI ,
Read Address ta C,
Mod CAR HI,
Move ta A Reg
Write Address
to LS (4)
Tens to Skew Bfr
I
I
I
I
I
Skew Tens Again
(O/T to BI) Mask
Th/H to O/H to BO
I
I
I
I
I
I
I
I
I
I
I
FIGURE 6312. 1410E STORE ADDRESS REGISTER (SHEET I OF 2)
AI
To Loop
QU252
Al
Loop
Mask Odd
Storage Character
to CI, Write
Address to LS (4)
Mask Even Storage
Character to CO
Combine Odd Mask
Character and
Address in BI to BI
Combine Even Mask
Character and
Address in BO to DO
Move BI to 01
QU253
Stats
Y3
Y6
Y7
Read Address to C,
Modify CAR -2 to BI
Move CAR Hi to
AO, Move CAR
Low to Al
1410 Address > 80K
Second Pass in loop
C Address Start Odd
Odd
Write Address to
LS (4), Move
Ten Thousands to BI
Mask Thousands/
Hundreds to O/H to BI
Skew Thousands/
Hundreds Put Thousands
in Skew Buffer,
Set Y6 for 2nd Pass
Skew Thousands to
O/Th N to BO
Write CAR -5
to LS (3)
Skew Thousands/
Hundreds, Put
Thousands in Skew Bfr
Skew Thousands to
O/ThN to BI
Set Y6 = 2nd
To I-Fetch
Use Working IC
2nd Pass
Move Ten ThousandsN
to BO
Move Ten ThousandsN
to BO by Adding 8
2nd Pass
Modify CAR
Low -I to CI
Mask Ten Thousands
Storage Character to BO
Combine Ten Thousands
and Mask Character
to 01
Modify CAR Hi
to CO
Write Back CAR -5
to LS (3)
6302
QUIOI
To I-Fetch
Use Working IC
FIGURE 6312. 1410E STORE ADDRESS REGISTER
(SHEET 2 OF 2)
Translated d Modifier - Stats
Bit 4
Bit 5
Bit 6
QU261
(
Store Status
'----r---../
Internal or Ch 2 - Set Y6
Status
- Set Y7
Store Status
1/0
Generate 2/0 in AO,
Move d Modifier to Al
for Storage Table
Read Storage Table
Generate F4 for BAR
o"A,-"
,--------<
Odd/Even Gen
Address of
Status
>------Shift Translate
Character Right
Test Bits 5, 6
Shift Translate
Character Right
Test Bits 5, 6
, -______________________________. -______
11
10
CPU
1/0
Shift Translate
Character Right,
Put in Y, Read
1/0 Status at FB
~S~to~r~e_<~)-~Re~s~to~re~----~~-----------CPU
Shift Translate
Character Right,
Put in Y, Read
CPU Status at FA
~
Yes
No
1/0
Shift Translate
Character Right,
Put in Y,
Read Out BAR
(I n Ik/
Ch 2)
No
No Y5, Y6, Y7
Error Li nk 2200
Ch 1
in Process
Bit
Read 1/
Status Ch 1 in
Process
No
I
V
I
Reset Interlock
Bit in Ch 2
Status
~~
Reset Interlock
Bit in Ch 1
Status
I
01
it4
~
---<
es
r -_________Y
__
Bit4~
Yes
1
Shift Translate
Character Right,
Put in Y,
Read Out BAR
",,,A ...
Ch 2
in Process
Bit
____________,
00
CPU
Yes
Yes
Read 1/0
Status Ch 2 in
Process
No
No
QU506
No
Ch 1
Interlock
Bit
Yes
Yes
Ch 2
Interlock
Bit
No
Interlock Bit On or
In Pr6cess, Mise-Error
Link 2100
Return to I-Fetch,
Use Original lC
IV I
I-OIC
I
6302
QU10l
V
- - - - - - - - - - - ------ t---- ----- - - - - - - - - - - - - - - - - - - - - - - - - -
Yes
Test
Status Wd for
Invalid
Dec
QU262
Num 0000
I
Invert Zones and Bi t 1
for Bits 8 and 2 ~ 10
I
QU506
--------- - - - - - - - - - -
Modify BAR -1 to C,
Read Storage Test
Odd/Even
Modify BAR High
Order to C
No
Subtract Bits 8 and 2
from NumericWrite Status
z"o~
;~
Invert Zones
Write Status
Nonzero
>-----,
~
r----~----_,
Invert Zones for
Zero
Test Odd/Even Storage
Character to Translate
Store BAR
-~----,
Y5)
Modify A Address
by -2 if Op is
Multiply, by 0 if
Op is Divide
Modify A Address
by -2 if B Start
Address is Even I
by 0 if Odd
I
Save A Char
in A Data
Buffer (LS 3)
. -____________________
N~o';~ ~ Po.";~
Sign
Set Y2
Clear CAR
Save B Field
Sign in Skew Bfr
~N~o<~~Y~esL-------------------__,
Skew Buffer Contents:
B Field Sign + All Zeros
B Field Sign - Non Zero
Reset Y2
Clear CAR
Save B Field
Sign in Skew Bfr
rPO: :S" it"-iv:. :e,- -<~
Neaative
Sign
Set Y2
Clear CAR
Save B Field
Sign in Skew Bfr
Reset Y2
Clear CAR
Save B Field
Sign in Skew Bfr
~--------------------~~--------~~>-----------~~------------------,
01
Multiply
MI
6322
QU381
FIGURE 6316. 1410E ADD, SUBTRACT, MULTIPLY, DIVIDE
11
Divide
Div
6322
QU381
Y5
00
Add/Subtract
ASI
6317
QU301
10
Start Logout
Inval id Exit
6317
InvX QU301
Call Moin
Storage
Read
Stats
Y2
Y3
Y5
Y6
Y7
From Add/Subtract Entry
6316
From Inval id Exit,
QU301
Common Routine
True Add Case
Skew Case
Numeri c Resul t Non-Zero
B Field Start Address Odd
BAR = AAR -1 Case (Ovlp)
Start Logout
6316
Strip 8 Bit from
First A Character
if Invalid Decimal
Skew Case - A field starting address even, B field starting
address odd or vice versa (AO/BE).
Overlap Case - Data fields overlap (BAR
requ-ires special loop.
= AAR -1);
10
11
Modify B Address
by 1, Write Updated A Address
to AAR
Transfer A Address
in C to A Register
for Read in Main Loop
To Special Add/Subtract Loop
6319
QU304
ASL
To Main Loop
6318
QU302
True
Set DADN in
Functi on Reg
for True Add
Complement
N Suffix
Indicates
1410 Numeric
Mode
Set DSPN in
Function Reg
for Compl Add
Add A and B
Field Characters
Reset Y6
No BWM
AAR
10
00
10
11
01
Zero Bal
Non Zero
Non Zero
Zero Bal
----..c
Set Y5
Reg
11
Set Y5
MR~Reg
·C"se
01
00
('(,7)
Set Y7
Zero A Field
Y7 Now Set for
Al WM Found
BAR-.A Reg
Zero A Field
in B Register
Reset Y3
Reset Y7
BAR_A Reg
Reset Y7
C Reg_A Reg
C Reg
to AAR
(F4)
ANE Even A WM End
6318
QU303
FIGURE 6317. 1410E ADD, SUBTRACT-INITIAL LOOP
SL
Specia I Loop
6319
QU304
ASL
Main Loop
6318
QU302
BWM B WM Found
6318
QU303
Stats
Add/Subtract Main loop
6317
QU302
Y2 True Add
Y3
Y4
Y5
6317
Skew Case
Recomplement Cycle
Numeric Resul t Non Zero
BWM
6317
Read MR,
Update AAR
by 2
Y7 A Field WM Found
Yb
NE
Recomplement Cycle
Read A Dolo
Buffer to
B Register
from lS(03)
Strip 8 Bit of Even
A Character in
BO if Invalid
Decimal
Second B character refers to the
second character processed in the
1410 B field operand.
Save New AChar in
Save New AChar in
A Data Bfr. Strip 8 Bit
of Odd A Char in Dl,
A Dolo Bfr. Strip 8 Bit
of Odd A Char in Dl,
Transfer to B1
Transfer to
BO
Read Out BAR
Strip 8 Bit of Even
Read Out BAR
B Char in DO
Transfer to BO
Y4 and Y7
= 00
J
com
Done (Y 4) A r..:.Y..:4..:a:::n=-d...;Y..:.7_*:....:.00::,.-------__----N-o-"
Fld< B Fld
('0/
4
Yes
No
Decrement
B Address
Decrement
B Mdress
by 2
by 2
Set Up
DSQN in
Complement
Function Reg
for Recomp,
Set Up
DSPN in
Set Up
DADN in
Function Reg
Function Reg
forTrue Add
for Compl Add
Yes
No
QU303
Stats
Y3
Y4
Y5
Y6
Y7
Skew Case
Recomplement Cycle
Not Zero Balance
Recomplement Cycle
A Mdress End Modification
Done
No
A Field
WM
Yes
o
Dl
=
Dl@ Bl
Dl = Dl @ Bl
Set Y7
Zero A Field
No
Even
BWM
Ending
BNE
6319
QU305
BNE 6319
Even B WM Ending
QU305
FIGURE 6318. 1410E ADD, SUBTRACT-MAIN lOOP
Go Back to
B Cycle Start of
Add/Subtract
loop
6319
BNO Odd B WM Ending
QU305
QU304
Stats
Y2
Y3
Y5
True Add
No A WM before BWM
Non Zero Result
This loop handles overlapping
fields. B cycles only are used.
True
True or
~==--< Complement
Add (Y2)
Complement
"-.,/
Set DADN
in Function
Register for
Set DSPN
in Function
Register for
Compl Add
True Add
Y3 = a Now Means
No A WM before
BWM
A WM Not Found
Ending B
Address +1
to AAR
Reset Y6
QU305
Stats
Y2
Y3
Y4
Y5
Y6
Y7
6318
Odd B WM
Ending
True Add
Skew
Result has been recornplemented
6318
Even BWM
Ending
Cleor BAR
for Ending
Address, Modify
BAR+I to DAR
Num Result Non Zero
Recomplement Done
A Field WM Found
for Ending
Address,
Write
MSD == Most Significant Digit
ZSI == Zero Balance Indicator
True
Complement
Read DAR to
C Reg to
Write Ending
Address to BAR
Write Corrected
Ending B .Address
to BAR
Arith
Recomplement
Even B Character
DO=Z@DO
'.)-'N..:.o,,--_-,
Yes
No
Set Y4 ond Y6
Reset YC N Latch
Write B Field to
Main
Return to I-Fetch
6302
QUIDI
FIGURE 6319. 140lE ADD, SU8TRACT-SPECIAllOOP AND ENDING
6318
To Add/
Subtract
Main loop,
Compl
Entry
Stats
Y2
Y3
Y4
Y6
Y7
Y5
1
~ 6316 from Common
QU341
A Field Sign Negative
Skew Case
First Pass in First Scan Loop
B Starting Address Odd
Pointer to First Multiplier Digit
A Starting Address Odd
Routine Multiply Exit
Update A Address
Move to CAR
Reset Y7
C Reg ister Con ten ts:
A field starting address if AO
A field starting address minus 1 if AE
,_
~,>--=O-=d-=d
Ir - - - - - - - - - - < . .
dOdd
_ ___,
Ex;/'
Save A Character
from 1st Memary
Reference in LS(l)
Reset Y5
Reset Y5
Modify AAR ta Paint
to Next Odd Address A Char
L J v 4 = 0 at End of
~ommon Routine
I
I
Save A Character
from 1st Memory
Reference in LS(I)
I
Save New A Address in AAR (F5)
Zero B Field Numeric, Save WM
A
Field
WM
Yes
r-----------~
No
Read Out
BAR
Set Y4 for
First Scan
I I
QU342
Modify AAR
by -2, Put
A Char in
Skew Bfr
No
A
Yes
Skew
I
Transfer A
Character in
D Reg to BReg
Transfer A
Character in
DO to Bl
I
r -_ _ _ _ _ _ _ _ _ _ _ _
N_o-<~~Y-e-s-----------__.
r-_..:.N.:.::o:,..(L
B WM >-Y,-,e;::.s_--,
Zero the B
Zero the B
Numeric, Insert
Numeric,
00 Zone, Save
WM
Insert 00 Zone
.- - -'N. ; O"- <~>-Y'-'ec:. s
Pass
Zero the B
Zero the B
Numeric,
Insert 11 Zone
Numeric, Insert
11 Zone, Save
BWM
NO~Y~
I.----=-<..
BWM
"'>--'-=~--'I
Zero the Second
B Character,
Insert 11 Zone
Zero the Second
B Character,
Insert 11 Zone,
Save WM
I
l
~
SkewBfr
Contains 1st A
Char Zone Bi
Firs
No WM
or
.-I________-< AWM
nd A WMN"
L.:...::::....:~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Second A WM
Set Y7, Y4,
Zero Out 1 More
B Character,
Read Out DAR
BAR Naw
Points to 1st
Multiplier Digit
~ 6321
ML
FIGURE 6320. 1410E MULTIPLY FIRST SCAN
Reset Y7,
Read Out DAR,
Set Y4
I
I
Update BAR by +1
to Point to 1st
Multiplier Digit
I
I First A WM
'(B,g)/
Y4 Indicates
lst Pass in
Multiply Loop
To Multiply Loop
QU343
I
_ __,
Stats
Y2
Y4
Y5
Y6
Y7
Y3
A Field Sign Positive
First Poss in Multiply Loop
A Starting Address Odd
Presently Developed Portial
Product AI igned with Previous
Partial Productin Storage
Use Even-Addressed Char as
Multiplier Digit
Product Sign Negative
~
First Pass - Units Position
Y4= 1
;f~
Analyze
Multipl icand (A) and
Multiplier (B)
Sigm
'-/
Zero the Multiplier
Digit, Insert II Zane,
Retain WM, Set Y2
if WM Found on
Multiplier Digit
QU344
Stots
Multiply End
A Field Starting Address Odd
MUL TIPl Y ABBREVIATIONS
TRI
Address Translator
Disabled - Table in
Emulator Program
PH
PL
WH
WL
TIH
T2L
High-Order Byte--Partial Product
from Product Field
Low-Order Byte--Partial Product
from Product Field
High-Order Byte-- LS(6)
Low-Order Byte--LS(6)
High-Order Byte--First Selected
Table
Entry
Low-Order Byte--Second
Selected Table Entry
Local Storage Contents
LSI
LS2
LS3
LS4
LS5
LS6
First Two Multiplicand Digits
C Address Register
Multiplicand Digits from Each
Storage Read
D Address Register
Multiplication Table Base Address
Partial Product, High Order
Stars
Y2
Y3
Y4
YS
Y6
Y7
WMon MultiplierDigit (End)
Imert Minus Sign
First Pass in Multiply Loop
'A' Starting Address Odd
Aligned Case
Use Even-Addressed B Character as Multipl ier Digit
oo~-----------------------------------------------irst
No
:~; ~~i:>>-Y:..:e,,-,---l-'
(~)
-,--...l===;='-<
Yes
r
"'-
Test Y3 for
Sign Insert
Reset Y3
>-=-;::==::J.__--.
No
'V'
Ye,
WMin
FirstA
Char
~NO
'V"
WM
2nd A
Char
'V"
To Beginning of
M.lltiply loop
QU343
FIGURE 6321. MULTIPLY lOOP
No
Stats
QU381
Y
Y2
Y3
Y4
Y5
MDL (Divide End)
Skew Case
Complement Add Cycle
Look for B Bit On B Char
to Set MDL Latch
Y6 B Starting Addr Odd
Y7 W M Found on Even A
Char
Divide Exit of
6323
S'm'
iV
~
",,"0'
Y4
Common Routine
6316
=1
Regen CAR, Transfer
A Address from
C Reg to A Reg
Save A Fld Sign
in Skew Buffer
Regen CAR
I
I
r -___________________________________
Y~e~s~~>_N-O~--~
CAR Canto ins A Start
Addr (-lor -2) Depending on A Start
Address E/O
I
Stri p 8 Bi t from
First A Char if
Invalid Dec
Read Out BAR
Use A Address in A
Reg to Reference
Storage if Skew. Use
A+ 1 if Non-Skew
This First
A Char is
in B1 Reg
I
Set Y5 for
Testing B Bit on
Dividend Digit
BAR -l_BAR
Reset Y5
.L"
Cyc~le >-__- .: :C~A
I '-----=-=-------..
WM
Read Out BAR
Set Y7
Zero B Reg
_.1... ____________ _
QU382
Divide
Loop
DL
6323
Saved A Char
from LS(3)
to B Reg
Regen LS(3)
All A Characters are } Stri pped of 8 Bit if
Invalid Decimal
AI ign Proper A
Chars in B Reg
Save New A
Char in LS(l)1
AAR -2_AAR, Read
Out BAR Zero 80 Reg
if A Char in B1 has
Reset Y5
if Y2 = 1
r e/Compl
Add
(Y4)
TA
True Add
First A and
B Character
No
CA
Complement
Add First A
and B Char
~>-ye~s ~
__
aWM
Read Out
DAR to
C Reg
True/Campi
Add 2nd A
and B Chars
BAR -2.-. BAR
Reset Y5 if
Y2 = 1
6323
DTC QU383
Divide
True/Complement
FIGURE 6322.
1410E DIVIDE INITIAL LOOP
Divide
End Test
DET
6323
QU383
QU382
Stats
Y2
Y3
Y4
Y5
Y6
Y7
QU383
MDl (Multiply/Divide last Cycle)
Skew
Complement Add
B Bit in B Character to Set MDllatch
B Starting Address Odd
WM Found on Even A Character
B Bit = 0
.----'-=---''------<
1
DTC 6322
Yes
No
Y5
B Bit = 1
Dig it B Bi t
etY
Analyze B Fld Sign
and Recover A Fld
Sign from Skew Bfr
Set Y2
00 No WM
I
:b
Both
AChars
WM
WM on
lstAChar
10,11
All Zeros to Skew
Buffer if A and B
Fld Have Same Sign
Read Out AAR
Reset Y5, '(7
I
I
WM Only on
01 Second AChar
Read Out BAR
Set Y7
Zero Bl Reg
Read Out DAR
to C Reg
~ 6322
I
_____ ..JI
Dl
~ Start
of
DBC B Cycle in
loop
6322
Back to Divide loop
QU382
(5EfJ Divide End Test
y
11
6322
A1:Add~~;~de.
CA Cycle
No Carry
10
MQ-CACycie
and Carry
00
Carry
01
overdraw)Case
Regen True
Add latch (Y4 = 0)
Update DAR to BAR
No
)-
Read Out lS(3)
to B Reg
Regen lS(3)
Clear lS(3)
Transfer Even
Char from lS(3)
to B Reg
Read CAR to C
Start
~escan
DR
6322
QU381
r-(
Read Out
Quotient Fld
Update DAR
to BAR
Inval id Branch
Start logout
Ay.,
~--------~-<
lS(3) Contains
the UP and/or TP
of the Divisor
I
TACycie
Regen Camp Add latch
(Y4= 1)-Comp Y3, Y6
Update DAT to BAR
-Shift + 1
(Y2)
~~--------------~----------------------------.
Reset Y7 )
No
Yes
Y7
Increment
Increment
Odd-Addressed
Char in Quotient
Field by 1
Even-Addressed
Char in Quotient
Field by 1
r----
Divide End
QU384
I
I
I
I
I
r-'---'---<~>------'-,'
No C o , " , C [
Carr"
,
Use Skew Bfr
as Skew latch
Read Out UP
of Quotient
I
I
Reset Y7, Read Out
lS(3} to B Reg
Regen lS(3)
Clear lS(l)
r - - - - ____ ..J
I
Read Out
I
I
I
I
I
I
I
Insert + Sign if
Skew Bfr Contains all O's
-Sign Otherwise
CPU Indicator
Set Divide
Overflow
Divide Overflow
I
Update AAR by:
+ 1 if Y3, Y7 (01 ,10)
+2 if Y3, Y7 (11)
+0 if Y3, Y7 (00)
Update BAR by:
-lifY7=0
-2 if Y7 = 1
Return to
I-Fetch
V
- ....... 6302
QUIOI
L _________________ _
FIGURE 6323. 1410E DIVIDE lOOP AND ENDING
1410 d Modifier Numeric Bits
Bit and
Data Move Function
Status
1
0
1
1
1
8
4
2
1
QU401
PI us Scan Data Move
Minus Scan Data Move
Move WM Bit
Move Zone Bits
Read Out
d Modifier,
Set Y2 and
Y3 to 11
Move Numeric Bits
I
Stats
Y2
and
Y3
Y4
Y5
Y6
Y7
Zone Bits of Data Move
d Modifi er used Later for
Ending Conditions
00 Zero Add
10 Zero Subtract
01 Compare
11 Data Move
Skew Case
Plus Scan Data Move
B Start Address Odd
(BAR = AAR 1)
I
Set Hex A to LowOrder 4 Bi ts of d
Mod if it is in
? ! '*' 0 Group
7.
y,"'.""
10
o~~~1----_,
~c~"'''
Z.m S.b,."
11
r-____
Modifier
00
Set Y2 and Y3
to 10
Set Y2 and Y3
to 00
Save Zone Bits
of d Modifier in
Skew Buffer
Set Y2 and Y3
to 01
1
[
I
Reset Y5
I
Set Y5
1
Bit 1 of Mask Always On
When Numeric is Moved
for Valid EBCDIC II Char
~
Zn
N
Zn,N
FNB
WM
-
WM,N
WM,Zn
WM,Zn,N
~~--------------~~--------------~~--------------~~_(ondModifier·~--~~--------------~~--------------~~--------------~
1000
001
010
011
B VI
100
101
110
1111
,...-_--1.._ _.....,
Set Mask to
00000000
Set Mask to
01001111
Set Mask to
00110000
Set Mask to
01111111
I
M;om
Set Mask to
10000000
Set Mask to
11001111
Set Mask to
10110000
Set Mask to
11111111
A~p':':IU::!.S________________________________________- -,
r-------------~~~_(
I
Scan
Transfer the
Mask to BO,
Read Out AAR
QU402
Odd
I
St~r~
Ad
Odd/
Eve
Even
Set Y6
Save BAR
Address (F4)
I
/'..
.-_______---.-----------J~------"lFField Conditions
Condition Non
.-_ _ _....L..;:C;:;a:::se::......_.....,
"
Skew
Set Y4, Write Mask
Case
Test Th/H
Buffer with Mask on
BARi AAR-l ..... of A,B, Addr Th/H of Addresses Equal
the Even Side and
for Ovlp case~
2nd A Character on
Set ~4
the Odd Side
Test
r-__________B_A_R~i_A_A_R_-_-~Eq~u~a~I__________~
B Addresses
BAR =J-AR-l
Set Y7,
I
Set Numeric
Carry Latch
(YCN)
I
I
Write Mask
Buffer with
Mask on the
Even Side
I
Modify A Address by:
-2 if A Odd/B Even
o if A Odd/B Odd
-1 if A Starting
Address Even
Y2 = A Field Sign
Minus
--
Test Sign of 1st
A Char, Set Y2
for -Sign
rO ~,_10 <~)-------0~1------------__.11
~
V
____
6325
QU411
ZA/ZS Initial Loop
FIGURE 6324. 1410E DATA MOVE, ZERO ADD/SUBTRACT, AND COMPARE
~
V
6331
QU441
Compare Initial Loop
*
V
6327
QU421
Data Move Minus
Scan Initial Loop
DPI
6329
QU424
Data Move PI us Scan
Initial Loop
QU411
Stats
Y2
Y3
Y4
Y5
Zero Add/Subtract Entry
from ZA/ZS Exit of
A Field Sign Negative
Zero Add/Subtract
Skew Case
AAR End Address, Madification Completed after WM
is Found
Starting B Address Odd
Ovlp FieldCase (BAR~ AAR-U
Y6
Y7
Common Routi ne
6324
Insert Proper Zones
Sign Insert
Y2~ 1, Minus
Y2~0, Plus
in -he 1st A Field
Char for Sign Generation in 1st Z A/ZS Op
BAR Odd
Modify BAR by -1,
Set Y6 if NonZero Be lance
Set 0001
in Skew Buffer
for Skew Case
Set 0001
to Skew Buffer
if Skew Case
No
Modify End A
Address by -1
Set Y5
Yes
Update
A Address
by -2
QU412
Set Y2 for WM
on 2nd Char A
Y2
~
Yes
Reset Skew Buffer
if Non Skew Case
Modify Mask in BO
to 00001111 to Use
A Field Numeric
R t Y6
WM in Second
A Char
ZA/ZS
A, B, Fields,
Retain WM
Zero Add/
Subtract A,
B Fields
Update End
A Address
in C Reg
Yes
Update End A
Address, Set
Y5, Reset Y7
Zero A Field
Read Out CPU
Indicator, Set
Zero Balance
Bit if Y6 ~ 0
Modify Mosk in BO
to 00001111 to Use
A Field Numeric
Reset Y7
6302
I-WIC I-Fetch
QU10l
'V
6328
DMZ QU422
Data Move
ZA/ZS
FIGURE 6325. 1410E ZERO ADD/SUBTRACT --INITIAL LOOP
To Special
SL2 Loop, Entry 2
6326
QU414
6328
ZBC ZAjZS
B Cycle
QU422
SLl
To Special
Loop, Entry 1
6326
QU414
Ta Main
ZL2 Loap 2
6328
QU422
Stats
QU413
Y2
WM Found on 2nd AChar-
Y5
AAR End Address has been
Updated after W M Found
Nnn Zero Be lance
Stats
~
I
acter
Y6
6328
Zero Add/Subtract
QU414
Y5\ A WMhas
been Found
Main Loop
Special Loop for Overlapping Fields
DADOll10000 to
A Character, Save
Unused A Character in LS(I)
Y
First ZA/ZS
,-_O_p~e_r_a_ti_on__in__L_oo~p__,
r-(
~
I
DAD Operation also
Strips 8 Bit of Result
if Invalid Decimal
L--------r-I------~
6325
Special Loop
Entry 2
SLI
6325
Special Loop
Entry 1
Zero Add/Sub
the 1st A Char
to B Field with
Proper Sign
Set Y6 if Non-Zero
Balance, Zero the A
Field in B Register if A
W M has been Detected
I
A
Put the Present
Result of ZA/ZS
in Bl, Read B Fld
Second Char
.-----------<~M
> - - - - - First Char
BWM
BWM
No B WM
Zero Add/Sub the
2nd A,B, Char,
Retain WM, SetY6
if Non-Zero Bel
Add 10000000
to Result Char in
Cl, Restare WM
to 1st B Char
Zero Add/Sub the
2nd A, B, Char,
Set Y6 if NonZero Balance
Modify B
Address
by -2
Modify End
B Address
by -1
QU415
I
Modify B
Address by-2
Set A Fld =0
in C Reg
Modify B
Address
by -2
Modify AAR
by the Amount
in Skew Buffer
Zero the
A Field
in Bl
Put Proper
Zone in A
Char in Bl
- - - - - - - - - - - - - - - - ---- - ---- --------1
I
Read Out AAR
I
Set Y6 if
Non-Zero Bel
Updote AAR by
Amount in Skew
Buffer + 1 if
Y5 = 0
Move Character
in Bl to DO
Read Out
CPU Indicator,
Set Zero Bel
Bit if Y6= 0
Y.,
I
PutWM
Beck in
B Field
Write B Field,
Modify BAR
by -2
I
I
Write B Field,
Update Ending
AAR and BAR
.Addresses
ZA/ZS A Cycle
DMZ 6328
QU422
FIGURE 6326.
141OE, ZERO ADD/SUBTRACT MAIN AND SPECIAL LOOP
Start of B
ZBC Cycle in Loop
6328
QU422
6302
L-WI<; I-Fetch
"-/' QU101
~>-_N_O_,I
I
Stats
Y2
Y4
Y6
Y7
QU421
End Mark Found
Skew Case
B Start Add~ess Odd
BAR = AAR -1 (Ovlp Fields)
Restore BAR
Read Out AAR
Reset Y3
According to
Zone Bits of
d Modifier
Set Y6, Y7
According to
Zone Bits of
d Modifier
Modify B
Address
by -1
Mask A Character Using
Mask Pattern
Mask B Char
Using Complement
of Mask Pattern
Set Y2
Mask B
Character
Reset Y2
No
Combine
Masked A and
B Characters
Combine First
Masked A and
B Characters
Yes
Read Out AAR,
Put 0001 in Skew
Buffer, Reset Y3
Read Out
AAR
Reset Y3
Yes
Modify A Address
by Amount in
Skew Buffer
Save the Combined
Masked A and B
Character in low
Byte of lS(1)
DM2 Second End
of Main loop
6327
QU423
FIGURE 6327.
1410E DATA MOVE MINUS SCAN-INITIAL lOOP
DMl To Main loop
6328
QU422
Stats
ZBC 6326
ZA/ZS
B Cycle
ZL2
QU422
Minus Scan Data
Move, Zero Add/Subtract A Cycle
Y2 Terminate after Processing
First Character
Y3 Zero Add/Sub
Y4 Skew Case
Y5 Terminate after Processing
Second Character
00 -Move to AWMarBWM
Y6 01 -Move to BWM
Y7 10 -Move to A WM
11 - Move Sin Ie Position
6325
From ZA/ZS
Initial loop
10
(Y4 and
and
Y7
Vi)
Transfer Odd A
Character in
D Reg to CO
Mask Pattern
ANDed with
A Character
Bits to be
Moved
and
Y5
DO
10
01,11
..\-\ask B Char in D1
with Complement of
Mask Pattern
Mask 8 Char in Dl
with Complement of
tl.ask Pattern
,\Aosk B Char in Dl
with Complement of
,\Aosk Pattern
Ye,
ingle
Char
Move
Mask 2nd B
Character in
DO to 80
DM2
Write Result with
the Even-Addressed
B Field Char Un-
6327
Second
End
Update AAR
by />,mount in
Skew Buffer
Update AAR by
/>,mount in Skew
Buffer +1
Ye,
To Beginning
loop
To First
End
QU429
and BChors in Bl and
C 1 and Mcve to B Fld
Set Skew 8fr Equal to NonZero, Move and Combine
A· B Char in BO and CO and
Move to B Field
The mask buffer has the
mask in the high-order byte and
the last unused A character
in the low-order b te
To
ZA/ZS
!-WI<; Return to I-Fetch
' - / QU10l
FIGURE 6328. 1410E DATA MOVE MINUS SCAN, ZERO ADD/SUBTRACT A CYCLES
This loop is an extension of
the main loop to allow handling
of overlapped fields. The main
loop will handle these cases;
one character is processed per
cycle.
Stats
QU424
DPI
6324
Y4 Skew Case
Y7 B Starting Address Even
B
Even
Start Addr ")-O_dd_ _-.
Odd/Eve
I
1
Set Y7
I
.-:;-_________...-,:-;--;:,_-<
I
Skew
Non Skew
Transfer A Character
in 01 to BO for
Writing Back to
fv'IcIsk Buffer
I
1
AR
= AAR + I
or Skew
Set Y4, Transfer
A Character
in 01 to SO
Possible Overlapping
Field Conditions
BAR:;;; MR +1
Th/HofA
B Addre),]s
E ual
BAR = MR
a~d
'0/
I
I
TT of A
BAR = AAR + I ad B Addre~e, BAR" AAR + I
AR=AAR
L -_ _ _ _ _ _ _ _ _ _~---------~----~
+1
Modify A Add by,
+2 A Even/B Odd
o A Even/B Even
+1 AAR Odd
Reset Y5,
Set Numeric
Carry Latch
(YCN)
Write MaskBfr,~sk
on the Odd Side and
Odd A Character on
the Even Side
1
Set Y6 and Y7
with Zone Bits
of d Modifier in
Skew Buffer
r-_ _ _ _ _
-6
QU42
~E~v~e~n-<~)_O~dd~-------------,
"~~;n_S;ld
-----II'---TI _
_______________________ _
~
I
Set Y3 jf Y6
and Y7= 11,
Terminate on
A/B WM Case
I
Y6andY7
Test for
RM,GM,WM
on First A
Character
Test for RM
on First A
Character
I
1
Stats
Y4
Y5
Y6
Y7
End Mark Found
Look for A/B WM
as End fv'IcIrk
Skew Case
Not Overlapped Flds
00 - Move to RM,
GM, WM
01 - ~,;;e to GM,
>-__~G~M~====~~__~A~fiWM
Test for GM
on First A
Character
N~O~~~
~~ ~Y~e~s
, -__
I
fv10sk pattern ANOed
with A character bits
-_--S'-'O;--.
to be moved
10 - Move to RM
'----' II - Move to A/B WM
1
1
I
QU425
Y3
RM
RM,GM,WM
:
_ _ _ _ _ _ _ _ _ _ -.J
Y2
dMOdifier
Zone Bits Tested for
Ending Condition
J
__- .
Found
fv\ask First
A Character
Set Y2
Mask First
A Character
yeS~NO
1
I
1
Nbsk First
B Character
yes~
BWM
I
I
No
1
Combine fv\asked
A and B Chars
Set Y2
No
I
o~er-
~~")-YL!e",s
(Y5)
___..,
I
Set Y5, Read Out LS(I)
Update B
.Address +1
Save the fvt.asked A and
B Char in High-Order
Byte of LS(I)
I
r -__
1
~Ye~s-<~
Put ooOJ in
Skew Buffer for
Ending .Addr
M.odification
I~
I
L-_ _ _ _ _ _ _ _ _ _
~---~N~a~(~a)-Y~e~s----_,I
(Y2)
Decrement
A Addr by
Amount in
Skew Buffer
DPL
6330
QU426
To Iv\ain loop
FIGURE 6329. 1410E DATA MOVE PLUS SCAN-INITIAL LOOP
1
Combi ne IYbsked
A and B Chars
I
I
Mask First
B Character
-WIC
~
I-Fetch
6302
QUIOI
lS(l) contains the mask in the
low byte and the last unused
A Char in the high byte
I
SetY3
Test for A/B
WM on First
A Character
I
QU426
Stats
Y2
Terminate after Processing
First Character
AlB WM os End
Y3
Look for
Y4
Y5
Skew Case
Terminate after Processing
Second Character
Y6,Y7
Mork
Read Out
Saved A Char
and fv\ask to B Reg
fv'.ask in B1 and
Unused A Char in BO
Modify MR +2
OO-MovetoRM/GMWM
01 -Move to GM WM
10-Move to RM
II - Move to A;1l WM
QU427
A;1l WM
Non Skew
Skew
10
Transfer
A Char in
in DReg
to C Reg
DO to CI
Transfer A Char
in Dl to BO to
Write Back to
Mask Buffer
00
No GM WM/RM
Set Y2 to
Remember First
End fv\ark Found
Set Y5
Transfer A Char
in Dl to BO for
Writing Back to
Transfer
A Char in
Mosk Buffer
DI to 80
QU428
End Mork
No End Mark
Set Y5 to
fv\ask First
A Char and
Read Out
Remember
Second End
fv\ark Found
f.Acsk 2nd A Char,
Write f.Acsk and
Odd-Addressed
AChor in LS(l)
No First End f.Acrk
First End Iv\ark Found
Complement of mask pattern
used to mask B char bi ts
not retained.
Combine First
Masked A and
B Chars
Combine First
.Mosked A and
B Chars
Set Y5
,- -
-- --- -
-
--Thls::n7xte:'ion-;;F'ti;"moinloop:-h:dI;-------overlapping fields.
Only one character is
>-'-='-_ _ _ _ _ _ _-;-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'p:...ro'-c:..:e"ss:..:,ed per cycle.
QU431
No
Set Skew to 0
A and B Char in
Se t Skew Bfr to Non Zero
Combine A and B Char
in Bl, Cl to B Field
BO, CO to B Fld
Combine Second
Masked A and
B Chars
Decrement
IVIask in Low-Order
A Addr by
Byte of Mosk Buffer
A Char in High-Order
Save the
Present Result
in Mlsk
Save
the Present
Result in
Amount in
Skew Bfr +1
Byte
Buffer LS(l)
Mosk Buffer
No
Update Ending Address
00
Update A ond
B to Address
Update Ending Address
Next Character
I-Fetch
I-WIC 6302
QU401
V
FI GURE 6330. 14lOE DATA MOVE PLUS SCAN - MAl N LOOP
Return to
Main Loop
I-Fetch
I-WIC 6302
VQUIOI
Y2
Y4
Y5
Y6
6324
Compare Ex i t from
QU441
Stats
Common Routj ne
A Field Sign Negative
Skew Case
0 = Compare
1 = Table Look-Up (TLU)
B Start Address Odd
Read Out BAR,
Put 0001 in Skew
Buffer, Reset Y7
BAR Odd
BAR Even
Update B
Address by - 1
Zero Y A Stats
Restore BAR
Read Out AAR
Reset Skew Buffer
Zero Y A Stats
Reset Y6,7
Yes
No
Strip WM from
First B Char,
DO to BO
B Character
in DO to BO
Set Y2
No
Yes
Set Y6 for A WM
before B WM
Set Y 4 for TLU
Strip WM from B
Char, Set Y4 if
AWM and BWM
Strip WM from A
Character, Update AAR by Amount
in Skew Buffer
FIGURE 6331.
Yes
Y4 On Now Indicates
othWM'satSame Time
Put Zeros in
Character Buffer
Characters in
B Reg, Store
,in LS(2)
CC
CL
6333
QU445
To Compare
Character Routine
6332
QU442
To Compare Loop
1410E COMPARE INITIAL LOOP
OU442
Stats
Y2
Y3
Y4
Y5
Y6
CL
A WM on Second Character
A WM on First Character
Skew Case
Table Look-up (TLU)
AWMbefore BWM (B > A)
6331
Compare Loop
Update A Address
by -2, Read A Data
Buffer to B Reg
Reset Y2 and Y3
~
r---------------------------~~~>-I--------------------,
I ~~ ~
Y4 = 0
Transfer A
Character in
Dl to Bl
WM
Y4 = 1 and A WM
Set Y3,
Transfer A
Character in
Dl to BO
Transfer A
Character in
Dl to BO
y.,~
lr---~
A WM
Set Y2,
Transfer the
Unused AChor
in DO to Dl
No
>-'--'----,
Transfer the
Unused A Char
in DO to Dl
1
Update B
Address by -2,
Strip WM from
2nd B Char
.l.---.----------'N-"o'-<~~Yc..::e::...s~~----------~-=~--==_-_
-_O=U=443_-_-_=='1-- - - - - -
01
No B WM,
Char Unequal
B WM
10
Yes
andChars~--~OO~----------------------~,~I~I----~--~_<
Unequal
No B WM
Characters Equa I
Transfer
1st B Char
to CO
Yes
Y2
Stri p WM from BChar
Strip WM and A and
B Char, Compare A
and B Char, Set Y4
for TLU if A and B
WM at Same Time
Compare 2nd A
and B Char Pair,
Read Char Bfr
to C Reg
NO~YeS
+----'-'-'-<:
Char Pai r
Equal
2nd A and
Update BAR by +1,
Read Out Charocter
Buffer to B Reg
"'t:aracters Equal
Strip WM from B
Char, Set Y4 for
TLU if A WM and
BWMat Same Time
~>-,Yc..::e~s_~_ _ _ _ _ _ _ _~
L~_
Update AAR by
Amount in
Skew Buffer
CC
6333
OU445
Compare Char Routine
FIGURE 6332. 1410E COMPARE MAIN LOOP
Write Last
Unequal Char
Pair in Char
Buffer
Read Out AAR
Character Buffer,
LS(2), Has Last
Unequal Pair
Not Equal
""'--T:-ra-ns..,...fe...L.
r -Pre-s-en-t--,
Unequal A and
B Char Pair to
Char Buffer
~
-----;--
and B2 WM
Transfer Last
Unequal Char
Pair to B Reg
for Compare
>-c...:..;.__--.,
'V
Update BAR by +1,
Unequal Char Pair
to B Register
rB~W~M~-----<~BCharEqual)>--------,
Put Last Unequal A
and B Char Pair in
B Reg for Compare
No
SetY6 to Remember
A < B (Set High)
Set Y4 for TLU
L ______ _
Compare 2nd Aand
B Character Pair,
Reset Y2
--
No
Compare 2nd A
and B Character,
C lear Character
Buffer, Reset Y4
Set Y6 (A < B)
Update AAR by
Amount in
Skew Buffer
-
B WM
------..,
OU444
Bl WM
-
l
Reset Y2
I
QU445
Stats
Y2
Y4
Y5
Y6
Y7
BCE
6311
Branch Character Equa I Op
0 = End of Table for TLU Op
Table Look-up Op
A WM before B WM (Set High)
A Character is Alpha-Numeric
01 10
Test Character
Groupi ng for
A Char in
BI Reg
Zeros to BI Reg,
Prepare to Set
High CPU Indicator
Special
Char
? !
+ - ¢ bl Group
Zones are shifted I Position
so Order Becomes bl + - ¢
After the Operation
Add 01 to Zones
of Character
No
Yes
Strip Bit I
of Character
+ - ¢ bl Group
Special
Character
Add 01 to Zones
of Character
? !
*
0 Group
Yes
Strip Bit I of
Character, Set Low
Indicator if Y7 = I
Read Out CPU
Indicator, Reset
Bits 5,6,7
QU446
Binary Subtract
A Char (BI) from
B Char (BO)
High
Equal
Y5 Set by TLU, Y2
by B Op before
Entry to Compare
Set Bit 5 of
CPU Indicator
Set Bit 6 of
CPU Indicator
Set Bit 7 of
CPU Indicator
BCE
00
No
I
WI
6302
QUIOI
Return to
I Fetch Entry
FIGURE 6333. 1410E COMPARE CHARACTER AND ENDING
TXC
6315
QU291
Return to TLU Microprogram
I-Br
6302
QUIOT
*
0 Group
QU501
Stats
Y3
Y4
Y5
Y6
Nan-overlap
F Channel Op
Unit Control Op
Overlap
BO
CO
Cl
DO
Dl
H
Translated Op
System Status
d Modifier
Ch 1 Branch Conditions (R)
Ch 2 Bronch Conditions (X)
Hex Fl
Hex Fa
Register Contents
J
Read X Ctl 1, X
Ctl 2 to B
Register
Set Y2
F Ch
E Ch
Interlock Error,
Link to Hex 2100
in Emulator
Program
Set Y3
QU506
Op Code Analysis
Bits
o and
00
01
10
11
1
Format
Not used
X-control field plus addr plus d-mod (M/L)
d-Modifier only (F, K)
X-control plus d-mod (U)
Overlap
d-Modifier Translated Ch ... acter
Bit
0
1
2
3
Valid for
X2
- M/L
d-Mod - M/L
d-Mod - U
d-Mod - F
Disable Address
Translator (DAT)
SO to Al
Set Y3, Read
Choracter
Table A to B
Unit Control,
Go to Check
dMod
Yes
in Emulator
Program
DMC
6335
QU502
d Mod Check
FIGURE 6334. 1410E UNIT CONTROL, I/O MOVE/LOAD, INITIAL LOOP
QU506
Invalid I/O
X-Control Field
QU502
Move/Load
Stats
Y2
Y3
Y4
Y5
Y6
Y7
Write WM as 1
End of Core Op
Load Made
I/O No Op
Overlap
F Channel Op
d Mod Check
Access Storage for
Valid Char Table, Set
YCI = 1 for Input,
YC 1= 0 for Outpuf
I
Branch on Odd
Byte Unit Control
Register Contents
A
B
C
D
20 and d Modifier
Xl and X2
System Status and d Modifier
Table Character for d Modifier
H
J
Hex Fl
Hex F2, F3, or F4
M/L Op
00,10
Reset Y6
Yes
Yes
Force A=2503, CReg to D
Reg, C to B Field Address.
Reset Y7, BO = Command
01 if YCI = 0, 02 ifYCI = 1.
Disable Address Translator
Store CCW Data Address
d Mod Error,
Link to Hex 2200
d Mod
Valid for
U Op
in Emulator
Program
QU506
11
00
01
r
I
I
I
I
I
QU505
AO
Al
BO
B1
CO
Cl
Reset Y4 and Y5
20
d Modifier
d Modifier
X2
System Status
d Modifier
I
I
I
d Mod=_, X
Extension
Address to C 1,
Set Y7
I/O No Op,
Set Y5
No
I
I
I
Store Data
Address, Ext
Address to C 1
Unit Control
X-Control Field
Register Contents
4 or 2
Yes
Not 4 or 2
6 or 4
Not 6 or 4
I
I
•
X Control 2 Error,
Link to 2300
_ _ _ _ ....J
Generate CCW
Address in A Reg,
Put d Mod High Byte
in Skew Buffer
QU506
Odd
6336
QU503
X2 Field Equals 2,B,F,
or 4,U
6336
QU504
X2 Field Equals 1 or T
Even
B,M,U
A,E,R
A= 41
E = 45
R = 49
DAT,
Store CCW
B Reg to C Reg,
Skew
B = 42
M= 54
U= 64
00
10
M
Set Count
Field Bits for
Ovlp, WTM
11
Li nk to Hex 3BOO
for Unit Control,
Not Write Tape
Mark
F Chan, Odd
Parity, Link to
Hex 4100
10
E Chan, Odd
Parity, Link to
Hex 3100
6336
QU504
Unit Control
FIGURE 6335. X-CONTROL FIELD TRANSLATION
01
F Chan, Even
Parity, Link to
Hex 3400
00
E Chan, Even
Parity, Li nk to
Hex 3300
Device
Punch
Tape Even
Tape Odd
Printer
Disk
X2
Code
4
U
B
2
F
74
64
42
72
46
6335 X2 Field Equals
2, B, F or 4, 0
QU503
Bl Cantains X2 Character
of 1410 X Control Field.
D Reg Contains Translated
X2 Character
Branch on
Translated
X2
2, B, F
A
,-------<
X2
Character
Disk, Either Channel,
link to Hex 5100 in
Emulator
~
>-------,
,----<
X2
Character
>-----,
'V
'J,--printer
F--Disk
4, U
B--Tape Odd
Printer, Test X3 for
Write WM as a 1
4--Punch
6.
Tape Even Parity
Punch -- DI
Contains Pocket
Select Character
Tape Odd Parity
Chl
U--Tape Even
Ch 1
Ch2
~e~>-~~-------------------'
Set Y2 for Write WM
asal,DAT
Tape Odd Parity
Channe I 1, li nk to Hex
3100 in Emulator
Disable Address
Translator
Test
Y3for
Channel
-
Tape Even Parity
Channell, link to Hex
1300 in Emulator
Tape Odd Parity
Channel 2, Link to Hex
4100 in Emulator
Ch 2
Tape Even Parity
Channel 2, Link to Hex
1900 in Emulator
Pri nter Channe I 1,
Link to Hex 2FOO
in Emulator
I
QU504
Pocket
Cmnd Byte
NR
1
2
02
42
82
I
i
B
C Reg to D Reg Store
CCW, Store Command
Ext Address
r-_-,-y""es<~
6335
Unit Control
Put Modifier Bits into
BO wi th Read Command
BO_ CO
ut
~
N~
Input
or Output
I/O
No Op
(Y5)
No <&
'vi'
I
E Chan No Op, Reset
R/W Bits Y2, Y3,Link
to Hex 4FOO
E Chan, Not No Op,
Set R/W Bits Y2, Y3
Typewriter Output
Set Carry for Link
Typewriter Input
Reset Carry for link
No Feed, Command
Byte = C2
J
I
Set E Chan Bit in Count
Field, Store Count Fielc
QI
In
(ALU7)
NoOp
Reader or >-..:.R:::e.::a"'de"'r________--,
pewriter/
Bit in Command Byte
Insert Carrier Return
Put Op Stats into
BO for Count
C
Typewriter
6335, X2
Field Equals 1
Ta Model 40 I-Fetch Per
New IC (link Address)
QU506
FIGURE 6336. 1410E I/O UNIT SELECTION
Main Starage Read, Link
Read =4400 Write =45OC
Link to Hex 2DOO in
Emulatar Program
QU601
Set YCH 3,
Dump DReg
1410 Channel Mode, Emulator,
and Skew Select Forces Decimal Add. TO Bit 7: 1 for Read/
Write to End of Stora e
SO to AO
Dump A
SO to AO
Dump A
Even
Odd
No
Yes
GM·WM
Move Mode Input,
T1 : 80, Load Mode
Input, T1 : 00
Output T1 : FF
Move Mode Input,
T] :80, Load Mode
Input, T1 : 00
Ouput T1 : FF
Set T : 0
Restore ROAR
Control
Read
Output
Character
toW4
Output
Character
to W4
Input
Character
to DI
Input
Charocter
to DO
Restore
ROAR
Control
Restore
ROAR
Control
Yes
No
No
Restore
RO AR Control
Restore
RO AR Contra I
Undump D
Restore
ROAR Control
L Stor to A
Update Data Address
Reset YCH3
Zero TO
Undump D
Update
Data Address,
Undump A
End Operation
FIGURE 6337. 1410E, ONE-BYTE DATA SERVICE
Two Byte Data Service,
Generated Address = 1704
(
QU602
I
Dump D Reg, Pretest Add 1----:;;;;;;;::::.---- 1410 Channel Mode and
for 799XX, Set YCH3
~=
Skew Select Forces
with 1410 Dec Add and
Carry from ALU Ext
Decimal Add. YCH3 Stat
On Prevents Extra One
Byte Data Service Requests
I
r-___Nc:O-<~>_-Y:..e:.:s---------------------...,
Overflow
I
A
Write
1
I
Dump A Reg
00
1
Test GM·WM
in DO for Read
Test GM·WM
in DO for Write
No
AY~
GM'WM
Tl Bit 1 Equals
RjW to End of
Core, Dump A
Read
ReadjWrite
01
y.,A
Transfer Two Bytes
to Buffer, Test for
End of Core Wrap D
to W Reg 3 and 4
No
GM'WM
I
GM.WM in DO,
Set T=O to End Op
Transfer One
Byte to Buffer
DO to W4 Reg
6
~o
w".
Roo'
End of Core Write
D to LS 3,4
Transfer WO, 1 to D
End of Core Read
LS 0,1 to D
Y~ANO
Ir---~-< GM·WM
I
Restore GM' WM
I
>-~~--------------------------------~
Vl
I
YCD and
CH1, Test for
End of Core
Wrap
10
I
00,01
...----..1....----,
End of Core
Wraporound
Set TO to End
Operation
Reset YCH1,
Set TO =0
Update Address
and Restore
ROAR Control
Restore ROAR
Control
I
Restore ROAR Control
Loco I Store to A.
Update Address, Undump D
Undump Loco I
Stare to DReg
End
Operation
FIGURE 6338. 1410E, TWO-BYTE DATA SERVICE
I
Undump D
I
( FOp)
QU507
K Op
Register Contents
Al
BO
Bl
CO
Cl
Put 03 in Bl for Low
Order Command Cade,
R,X Condition
Byte 5 to D
<
Test fa
Channel
Interlock
d-Modifier
Channe I 1 Status Byte
Channel 2 Status Byte
System Status Byte
d-Modifier
Reset Y4-7, d Modifier
to AI, R,X Condition
Bytes to B Reg
'"
Test for
Channel
Interlock
I/O Interl ock
I/O Interl ock
NYteriOCk
Add 20 to AO for
d Mod Table
Address, Store R,X
Condition Bytes
Error Set Y2,
Put 20 in CO
Not
Interlock
Store R,X Condition
Status Bytes, Develop
Command Code in BO
Skew d Mod to BO
Register, SO Bits
0-3 = d Mod Numeric,
Bits 4-7 = 6, Read d
Mod Table Char
est
Mod for
Yalidity
Valid
T~l,.
Invalid
Invalid
I
I
Reset Y6
Put 22 in CO
d Modifier Error,
Put 22 in CO
I
I
Char for
Yaliditx
Valid
Put 2500 inA Reg
for CCW Cmnd
Byte Address
Zero A1 Add 20
to AO, Call Main
Storage Read
o~
Modifier for
Zero
I
Not 0
Put 10 in BO
for Carriage
Tape Chan 10
I
00
10
2
6
Test
Mod Bit 7,c, fa
Pocket
11
01
~
01
Delayed
Command Code = 23
for Pocket N
Command Code = 63
for Pocket 1/4
Command Code = A3
for Pocket 2/8
QU506
Stacker Select Link 3COO
FIGURE 6339. 1410E FORMS CONTROL, STACKER SELECT
Set Y2 & Y3
Command Code
Char = 3
Set Y6
Put 22 in CO
QU506
Error Link
Space
10
Test d Mod
......Zones for Carriag
Operation
Bit 7 & 6)
Immediate
00
Skip
Delayed--''-_ _-..
Set Y2
Command Code
Char = 2
Set Y3
Command Code
Char = 1
L..-_
QU506
Fonms Control Li nk 3FOO
11
Immediate
Reset YO-3
Command Code
Char = 0
Diagnose
C
,-__
QU511
~I~ns~tr~urc~ti~o~ns~-/
:::::::'i:::
1110
~
0111
0101
1000
1001
83500740
SG
DS
1010
r-~----------~------------'-----~y'mmediateField~------~------------.-------------.-------------,
Bits 0-3
C
( 83700740 )
ED
QU509
Edit
Character
Translate
6341
QU508
Edit Store
and load
0110
83 600740
Set YB
Stats
4,5,6
Set YB
Stats
4,5
Set YB
Stats
4,5,7
QU539
Disk
Binary to
Decimal
6344
QU538
Disk
Scan
6342
QU531
Scatter/Gather
Reset YA Stats 0-3
Transfer Y Op Status Byte
(lS F9) to C Register
Set Inhibit Dump Stat (V8)
Register Contents
BO
BI
System Status Byte
d-Modifier
CO
CI
Y Op Status Byte
Communication Byte
Mpx
Channel Interrupt
Pending
Yes
I
Stats
Use WIC
Use AAR
I
Set Y9
Maskable
Interrupt
No
DO
DI
Y6
Y7
J Op - CPU Status
J Op - I/O Status
I
Set YI
Set System Mask to Allow All Interrupts
Reset Y8 (Inhibit Dump)
Transfer J Op Status Bytes to DReg
Channell_Set/Reset~
Overlap in Process
00
10
01
Reset Ch Ii0VIP in Proc
Tronsfer System Status
Byte (lS F8) to B Reg
Reset Ch I Ovlp in Process
Bit in Y Op Status Byte
Tronsfer System Status
Byte (lS F8) to B Reg
Reset Ch I Ovlp in Process
Bit in Y Op Status Byte
I
J
I
Transfer System
Status Byte (lS F8)
to B Register
Reset Ch I in Process Bits
in System Status Byte and
Ch I Ovlp in Process
Bit in J Op Status Byte
TesHor Ch I Interrupts
Set Bit 7 in System
Status Byte if No
Interrupts Pending
I
QU512
~
Test
Bits 7 and I
inComm
Byte
10
II
Reset Ch 210vlp in Proc
Set Ch 2 Ovlp Complete
Bit in Y Op Status Byte
SetCh 2 Ovlp Complete
Bit in Y Op Status Byte
I
I
ChanneI2-Reset/Set
Overlap in Process
J Op Status to A Reg
01
00
/---------~--------------------------,
Set Ch 2 Ovlp in Proc
Bath
Bits
Set Ch 20vlp in Process
Bit in J Op Status Byte
Bits 2,3
inY Op
Status
Test for
Ch 2 Interrupts
Pending
Reset Ch 2 Not in Process and
Set Ch 2 Interrupt Pending in
System Status Byte. Reset Ch 2
Ovlp in Process in J Op
Status Byte
Off~
Yes
I
No
Set Bit 3 in
System Status Byte
(Interrupt Pending)
I
Y6o"AY'o"
~'Br------<
6302
QUIOI
1410 I-Fetch Use AAR
Y6 andY7 >------lv-,wIC
6302
QUIOI
1410 I-Fetch Use Working
Instruction Counter
FIGURE 6340. 1410E DIAGNOSE INSTRUCTION, I-FETCH LINKAGES
QU508
6340
Edit Diagnose
New B Character,
Backward Scan
Transfer BAR to A Reg,
Set Y4 for Forward Scan
Set DAD Function for
Plus Address Modification
Transfer BAR to A Reg,
Set DSQ Function for
Minus Address Modification
Transfer AAR to A Reg,
Set DSQ Function for
Minus Address Modification
Transfer BAR to A Reg,
Set P Function for
No Modification
Transfer GPR Byte
(specified by X in diagnose
instruction) to C Reg
Read Ma i n Storage
Reset Y A Stats Transfer
GPR (specified by X in
diagnose instruction) to C
Reg. Read Main Storage
Odd
Odd
Reset Y6
Move GPR
Byte from
Cl to 01
Even
Move GPR
Byte from
Cl to DO
Move Storage
Character in
DO to Cl
Move Storage
Character in
01 to Cl
Set Y6
(Another Storage
C ycl e Requ ired)
Transfer
GPR Byte
to Cl Reg
SetY6
(Another Storage
Cycle Required)
Transfer
GPR Byte
to Cl Reg
No
Reset YA Stats
Update Decimal
Address, Restore
GPR
Set Y3, Update
Decimal Address
Restore GPR
Yes
Another
Cycle Required
\'(6)
Restore 1410 Address
Register. CaliMain
Storage Read. Transfer GPR to C Reg
Restore 1410
Address Register
Move Storage
Character to
C Register.
Restore GPR
QDOOI
2040 I-Fetch
FIGURE 6341. 1410E EDIT DIAGNOSE
No
Control Byte 0
Y4
Y5
Y6
Y7
QU531
Stats
I
I
Bit
{ 10
\I
0,
Transfer 1410 Starting
Address to C Reg (See
Control Byte Bits 0, I)
Store 1410 Starting Addr
in GPR 7 B tes 2 3
Off
Unassigned
Unassigned
Move Mode
Write EBCDIC "1"
for EBCDIC II WM
Stop on GM' WM
6
Unassigned
Unassigned
load Mode
Translate Data
Stop on End of
Storage
Gather
7
QU535
I
I
I
Use BAR
Use EAR
Use FAR
Use Expanded Address
in GPR 1
g'i
Mov, Mod,
Write l's for WM
Stop on GM • WM
Scatter
Scatter or
Gather >--,Go='h"",-c_ _ _ _ _ _-,
I
I
I
I
I
No GM·WM
M
14i~age
I
I
EBCDIC
Yes
No
Character >--'-"~--------,.----=(
I
(Y7)
WM
I
Scatter
No
I
6343
QU531
Generate Word Sep
Character in SO Store
1410 Mdress, Disable
Address Translator,
Read 2040 Storage
GM'WM
M
Move or load
r----~~--_ve Mode, 0 '" Load Mod
Temporary Data Check
1", Stop on GM 'WM
o eo Stop on End of Storage
1 = 1410 End of Storage
o '" 2040 End of Storage
I
Scatter End
I
~-------
QooOi
2040 I-fetch
QU536
I
I
I
I
I
I
I
No
I
10
I
I
\I
y~
GNI 6343
Correct length
Record (2040
No
nd of Storage'>-=--+--_._-----,
and Y7)
I
I
Nvm >lO(A)
I
I
I
2040
End of
Storog
No
Correct lengtf.
___--Y~.~,-"N"o'-~---+--+----'
GM-WI/O
Move
Mod,
No
V
(Y4)
Y3 On Indicates
Previous Character
i5a Word Separator
q
Word
parator >-"N"-o_ _ _ _ _ _ _ _
Control
Y
INs,Orl
Ws,&1
WS, Ori
WS,O;:-I
-+_____----,
Y"
FIGURE 6342. 1410E SCATTER/GATHER DIAGNOSE
WLR 6343
QOOOI
2040 I Fetch
Stats
Y4
Y5
Y6
Y7
On
Move Mode
Write I '5 for WM
Stop on GM·WM
Scatter
QU531
Off
Load Mode
Translate Data
Stop on End of Storage
Gather
Gather Diagnose Exit
from Common Scatter,
Gather Routine
II
00
10
Set Y4
Meaning Write
lsforWMs
Generate Word
Separator Character
(Hex 6D) in BO
Read 14 JO Storage
Modify 1410 Address +1
EBCDIC II Char to Bl
QU532
Stats
Y2
Y3
4
Y5
y
Y6
Y7
On
Off
/1410,
r -_ _ _ _Yc:e='--'N-'o=--_ _ _~
Word Mark Found
Word Separator Found
(EOM)
Move Mode
Load Mode
I for WM
Translate Data
Stop on GM ·WM Stop ,on End of Storage
1410 End of Stor 2040 End of Storage
Set Y7
Regen EBCDIC II
Character
Regen EBCDIC II
Character
Translate
00
01
Error
Start Logout
if Errors
are Enabled
Land Tslt
Load and
Translate
StripWM
Ye,
WM
in EBCDIC II
Char
No
Ye,
No
EBCDIC II
Character)
a Word Sep
Ye,
Correct
Length
Record
Ye,
No
EBCDIC II Char
GM·WM and 1410
Eoo of Storage,
Reset Y2
Emit EBCDIC
Blank (Hex 40) inBI Reg
Disable Address Xltr
to Read 2040 Storage
6342
QU536
Qu533"---Translate Char
from EBCDIC II
to EBCDIC
Read Emulator
(2040) Storoge
Modify 2040
Address +1
Mode
r"'==='----------t--<
No Word Sep
Move
Character
or Blank
to DReg
Reset Y2,3
Move Word
Sep to DReg
Reset Y3
Move Word
Sep to DReg
and Word
Separator
(Y'SY3)
Move Generated
Wand Sep in BO
to DReg
Move
Character
to DReg
Store EBCDIC
Character
in Emulator
(2040) Storage
Store EBCDIC
Character
in Emulator
(2040) Storage
No
Na
6342
QU536
Set Wrong
Length Recond
FIGURE 6343. 1410E GATHER DIAGNOSE
Move Generated
Wand Sep in BO
to 0 Reg
6342
QU536
Gather
End of Operation
DS
6340
OU538
Disk Diagnose
83 90 0740, Scan for
End of Storage (EOS)
on GMWM
Transfer Control
Byte from GPR 7
(LS EE), Byte 0
to B Register
BAR
Branch
on Bits 6,7 for
1410 Starting
Address
11
00
r
EAR
FAR
Error
Error
Start
Logout
Transfer BAR at
LS F4 to A Reg
10
01
Transfer EAR at
LS F2 to A Reg
Transfe r FAR at
LS F3 to A Reg
Modify 1410
Starting Address by +2
Move Result to C Reg
r -____________________________
~O~d~d_(~~E~ve~n~--------------------------_,
Odd/Even
Reset All Y Stats
Except Y5, Modify
High-Order Digits
of Starting Address
Modify Starting
Address by -1
Move Result to C Reg
No
Even
Character
aGMWM
Yes
Neither
GMWM nor EOS
------
Test
Odd Char
forGMWM
and EOS
End of Storage Only
I
GMWMor Both
Force Ending Address
to All Zeros
r
Store Ending
Address in GPR7
Bytes 0 and 1
00001
2040 I-Fetch
FIGURE 6344. 1410E DISK DIAGNOSE--END OF STORAGE OR GMWM SCAN
Modify 1410
Address by -1
1
Add flow charts
add (1401) .
fixed-point
general flow chart
zero and add (1401)
AND flow chart
6202
616
657
6209
636
Branch flow charts
branch and link
branch on bit equal
branch on character equal (1401).
branch on condition
branch on count
branch on index
branch on word mark
branch on zone.
multi-way (1401) .
tests (1401) .
1st and 2nd level function branches
608
6219
6219
618
612
632
6219
6219
6205
6222
607
Carry latches .
Clock control .
Compare flow charts
compare (1401)
RX algebraic .
SS decimal.
SS logical operation
Condensed logic flow charts (CLF)
branch and link
branch on condition
branch on count
branch on index
convert binary to decimal
convert decimal to binary
decimal divide add/subtract paths
decimal divide example.
decimal move with offset
decimal pack .
decimal unpack
diagnose instruction .
edit and mark .
fixed-point divide initialization
fixed-point divide loop .
floating-point divide loop .
floating-point load and store
floating-point multi divide initialization
floating-point multiply loop
flow chart for decimal add sub compare
how to use flow charts .
I/O codes, common decoding.
I/O interrupts.
instruction fetch microprogram
instruction fetch, RS and SI operations
instruction fetch, RX fixed-point
instruction fetch, RX floating-point.
instruction fetch, SS decimal .
instruction fetch, SS logical
instruction matrix
load PSW
machine status at function branches
multiplex channel microprogram
multiplex channel status
read direct and write direct .
RR and RX fixed-point arith and logic
RR and RX fixed-point multiply .
RR and RX fixed-point multiply, loops.
RR and RX fixed-point multiply, notes.
RR and RX floating-point operation .
RR fixed-point sign operation.
RR floating-point sign operations
RB load and store multiple.
RX compare algebraic .
RX fixed-point add and subtract
sel channel I/O instructions microprogram
selector channel status .
set and insert storage key.
set program mask
508
502
6203
617
662
649
608
618
612
632
613
610
652
651
656
654
655
639
643
623
624
630
627
628
629
657
599
666
671
601
604
602
603
606
605
600
638
607
set system mask .
shifts.
SI operations - AND, OR, XOR, move.
SS decimal compare .
SS decimal divide
SS decimal load and process operand 1
SS decimal load operand 2 and process
SS decimal load zero and add entry.
SS decimal multiply .
SS decimal terminate
SS edit, refill .
SS logical operation, compare
SS logical operations, move complete
SS operations - move, zone, and numeric
SS translate
SS translate and test
start I/O instruction (multiplex channel)
start I/O microprogram Mpx channel
store PSW -general flow.
test channel and Mpx halt I/O
test I/O multiplex channel microprogram.
test under mask . .
update timer microprogram
CPU data flow.
Data flow charts
CPU data flow.
CPU microprogram flow chart
microprogram data flow
multiplex and MS unit data and control
ROS control word.
selector channel data flow
Decimal operations flow charts
add
compare, decimal add sub .
compare.
convert binary to decimal
convert decimal to binary
divide
divide, add/subtract paths
divide example
instruction fetch
load and process operand 1
load operand 2 and process
load zero and add entry.
move with offset
multiply.
pack
subtract
terminate
unpack
Divide flow charts
decimal divide example
decimal paths
fixed-point initialization
fixed-point loop
floating-point initialization
floating-point loop
SS decimal
Dump.
633
635
636
662
650
658
660
659
653
661
644
649
648
647
641
642
665
667
686
666
668
631
671
012
012
014
013
101
015
011
657
657
662
613
610
650
652
651
606
658
660
659
656
653
654
657
661
655
651
652
623
624
628
630
650
669
669
670
637
615
620
622
621
626
611
625
634
.617
616
675
674
609
614
Edit flow charts
edit
edit and mark
SS edit, refill
Error check MAP's
control
early.
late
Fetch CAW
I/O flow charts
carriage control (1401)
common decoding
halt
interrupts
643
643
644
906
907
908
667
6213
666
666
671
X-I
SY22-2842-3
FES: SY22-6827
M, L, U operation ( 1401)
read and punch column binary (1401)
selector cham1el instructions
stacker select (1401).
start I/o instruction
start microprogram Mpx channel
test channel
test I/O microprogram
Instruction fetch
instruction fetch .
instruction fetch (1401)
RS operations (2nd level)
RX fixed-point (2nd level)
RX floating-point (2nd level)
SI operations (2nd level)
SS decimal.
SS logical (2nd level)
Load fixed-point flow charts
complement
negative
positive
test
Load floating-point flow charts
complement
halve.
load .
negative
positive
test
Load PSW
Local storage
Logical operations flow charts
compare
move complete
move zone and numeric.
SS instruction fetch .
Main storage
Main storage X --dimension drive.
Malfunction analysis procedure (MAP)
control check .
early check.
interpret errors
late check .
local storage
main storage
Mid-Pac power supply
multiplex channel .
read only storage.
selector channel .
storage protect
2.5 kc HF power supply
Microprograms
CPU flow chart
data flow
I/O instructions (selector cham1el)
I/O interrupts
instruction fetch .
multiplex cham1el
start I/O Mpx channel
test I/O Mpx channel
update timer
Move flow chart .
Mpx channel
channel control
channel MAP
channel status
halt I/o .
multiplex and MS unit data and control
multiplex channel microprogram.
start I/O instruction (Mpx chan)
start I/O microprogram
test I/o microprogram.
Multiply flow charts
floating-point initialization
floating-point loop
multiply (1401)
RR and RX fixed point
RR and RX fixed point, detail of loops
X-2
6210
6225
675
6213
665
667
666
668
601
6200
604
602
603
604
606
605
611
611
611
611
625
625
625
625
625
625
638
912
649
648
647
605
914
513
906
907
901
908
912
914
917
915
911
916
913
918
014
013
675
671
601
669
667
668
671
636
912
915
670
666
101
669
665
667
668
628
629
6208
620
622
RR and RX fixed point, notes .
SS decimal.
621
653
Objectives,channel microprogram
OR flow chart .
.666,669,670
636
Power supplies
divide (1401)
Mid- Pac MAP
Mid-Pac wiring diagram
2.5 kc HF MAP
2 . 5 kc HF wiring diagram .
Read only storage
Relocate feature (1401)
Relocate latches (1401)
ROS control word
RR instruction flow charts
fixed-point arithmetic and logic
fixed-pOint multiply .
fixed-point multipy, detail of loops
fixed-point multiply, notes
fixed-point sign operation
floating-point operations
floating-point sign operations.
RS instruction flow charts
instruction fetch
load and store multiple
RX instruction flow charts
compare algebraic
fixed-point add and subtract
fixed-point arithmetic and logic
fixed-point multiply .
fixed-point multiply, detail of loops
fixed-point multiply, notes.
fixed-point, instruction fetch .
floating-point operation.
floating-point, instruction fetch
Selector channel
cham1el data flow .
channel MAP
channel control
channel status
I/O instructions microprogram
set channel to 1401 mode (1401)
SI instruction flow charts
AND
instruction fetch
move
OR
XOR
Simplified logic diagrams (SLD)
carry latches
clock control (SP)
decimal correction
decimal filler .
function and control registers
LSAR parity generation
main storage control and timing circuits
main storage X --dimension drive.
Mid-Pac power supply wiring diagram.
multiplex channel controls.
selector channel controls
2.5 kc HF power supply wiring diagram
SS instruction flow charts
compare.
decimal compare .
decimal divide.
decimal load and process operand 1
decimal load operand 2 and process
decimal load zero and add entry.
decimal multiply .
decimal terminate
edit
instruction fetch, decimal
instruction fetch, logical
move complete
move numeric
move zone
refill .
translate
6208
917
510
918
511
911
6221
015
015
615
620
622
621
611
626
625
604
634
617
616
615
620
622
621
602
626
603
011
916
509
674
675
6217
636
604
636
636
636
508
502
507
506
505
501
504
513
510
512
509
511
649
662
650
658
660
659
653
661
644
606
605
648
647
647
644
641
SY22-2842-3
FES: SY22-6827
translate and test
Storage MAP's
local storage
main storage
read only storage
storage protect
Store CSW .
Store PSW .
Subtract flow charts
general flow chart
RX fixed-point
subtract (1401)
zero and subtract (1401)
642
912
914
911
913
668
686
657
616
6202
6209
Undump .
669
XOR flow chart
X -
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