SY26 4137 1_2841_Storage_Control_Stage_2_Diagram_Manual_Jan68 1 2841 Storage Control Stage 2 Diagram Manual Jan68
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I 2211784
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"ELD ENGINEERING DIAGRAM MANUAL
FOR
2841 STORAGE CONTROL - STAr,E 2
MACHINE TY'E NUMBER, MODEL NUMBER (IF APPLICABl!) AND M~CHINE NAME
CONSISTS 0' THE
FOLLOWING:
Y26-4137-1
FORM NUMBER (BASE FEOMI* _____________
_
FORM NUMBER
e FES 1*
*
NOTU
~ THE nDM AND ITS n:s's INClUOE A SYSTEM OATA FLOW DIAGRAM, UNI" "ATA AND CONTROL
DIAGRA~. 1/0 OPERATION ~IAGRAMS. AND CONDENSED LOGIC FLOW CHARTS AS APPLICA8LE
TO THE UNITeS) BEING SHIPPED.
WHEN A FEDM IS ORDERED FROM M~CHANICSBURG, ALL APPLICA8LE SUPPLEMENTS WILL 9E
AUTOMATICALLY SUPPLIED. SU'PLEl4ENTS CAN IE ORDERED S[PARATElY BY APPLICABLE
FORM NUMBER.
m
•
**
'IELD ENOINURING DIAGRAM MANUAL
FIELD ENGINEERING SUPPLEMENT
I_TEl.AliSUl 'Y:'IESS IAC.IIES CI.,.
DAT[
DIIlI
CRUll 110.
1I0ll
C...." 110.
t-:::-::7"I'--:=-=·=-:-:--:-:~==----'-.....;;..;~-u------+--,--::-~::-:-~-1t------+---------il. "'lIT
!lAME
D(sIG"
DiiAll
eN'CI
A".C
_._.
FEOM 10 DWG
413343
-
1 - - - - - - - - - - 1 ....,
....,
-
....,
f--D..-I
me. 110.
1-----------1 _
MODILI
tclif el,
TO E....
J
I
---~~-----+----
----
1----------1 :
Field Engineering
Maintenance Diagrams
~@~ ~ Storage Control-Stage 2
SY26-4137-1
l?W~.
~ ~ ~ Field Engineering
Maintenance Diagrams
~@~ ~ Storage Control-Stage 2
SY26-4137-1
PREFACE
This manual contains flow charts, timing charts, and specialpurpose diagrams to assist in the maintenance activity on the
IBM 2841 Storage Control -Stage 2.
Simplified drawings have been prepared for functions which
are not readily perceptible in the system diagrams, or for which
the logic requires multiple pages.
The system diagrams at the engineering level of the equipment should be used in preference to the maintenance diagrams
wherever there is a conflict between the two types of diagrams.
Second Edition
This edition (Form Y26-4137-1) is a merge reprint of form
Y26-4137-0 and supplement Y26-060S.
Specifications contained herein are subject to change from time to
time. Any such change will be reported in subsequent revisions or
Field Engineering Supplements.
Copies of this and other IBM publications can be obtained through IBM Branch Offices.
A form is provided at the back of this publication for your comments.
This manual was prepared by the IBM Systems Development Division,
Product Publications, Dept. 455, Bldg. 014, San Jose, California 95114.
©
International Business Machines Corporation, 1967
ii (1/68)
CONTENTS
Date
Title
LEGEND . . . . . . . . . . . . . . . . . . . . . . . . . . . v
UNIT DATA AND CONTROL DIAGRAMS
Storage Control and I/O Channel Interface . . .
2311 Attachment Circuits . . . . . . . . . . . . . .
2321 and Optional Attention . . . . . . . . . . . . .
Dual ehannel Seek Complete and Interrupt ...
2302/2303 Attachment Circuits . . . . . . . . . . .
1202
1211
1221
1222
1231
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
ERROR CHECK ANALYSIS DIAGRAM . . . . . . . . 1301
(7/67)
I/O OPERATIONS DIAGRAMS
Storage Control - ALU . . . . . . . . . . . . . . . .
2311 Seek . . . . . . . . . . . . . . . . . . . . . . . . .
Write/Write A1I . . . . . . . . . . . . . . . . . . . .
2303 Attachment SiD - Write . . . . . . . . . . . .
2303 Attachment SiD - Read . . . . . . . . . . . .
Channel Data Transfer - Write· . . . . . . . . . .
SERDES - Read . . . . . . . . . . . . . . . . . . . . .
SERDES - Read Address Mark . . . . . . . . . . .
2303 Attachment SiD - Burst
Check Data Flow . . . . . . . . . . . . . . . . . . .
Channel Data Transfer - Read . . . . . . . . . . .
Two Channel Interface - Part 1 . . . . . . . . . .
Two Channel Interface - Part 2 . . . . . . . . . .
Two Channel Interface - Part 3 . . . . . . . . . .
Two Channel Interface - Part 4 . . . . . . . . . .
1401
1411
1421
1422
1423
1426
1431
1433
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
1434
1436
1450-1
1450-2
1450-3
1450-4
(7/67)
(7/67)
(10/67)
(10/67)
(10/67)
(10/67)
SIMPLIFIED LOGIC
Serializer/Deserializer . . . . . . . . . . . . . . . 1501
(7/67)
FLOW CHARTS
Storage Control - ALU . . . . . . . . . . . . . . . . 1601
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604
Initial Selection . . . . . . . . . . . . . . . . . . . . . 1605
End Procedure - Part 1 . . . . . . . . . . . . . . . 1607-1
End Procedure - Part 2 . . . . . . . . . . . . . . . 1607-2
End Procedure - Part 3 . . . . . . . . . . . . . . . 1607-3
End Procedure - Part 4 . . . . . . . . . . . . . . . 1607-4
End Procedure - Part 5 . . • • . . . . . . . . . . . 1607-5
(7/67)
(10/67)
(10/67)
(10/67)
(10/67)
(10/67)
(10/67)
(10/67)
Title
Date
. End Procedure - Part 6 . . . . . . . . . . . . . . .
End Procedure - Part 7 . . . . . . . . . . . • . . .
2311 Seek . . . . . . . . . . . . . . . . . . . . . . . . .
2321 Seek . . . . . . . . . . . . . . . . . . . . . . . . .
2303 Seek . . . . . . . . . . . . . . . . . . . . . . . . .
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2303 Write . . . . . . . . . . . . . . . . . . . . . . . .
Write Address Mark . . . . . . . . . . . . . . . . . .
2303 Write Address Mark . . . . . . . . . . . . . .
Channel Data Transfer - Write . . . . . . . . . . .
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2311 Read . . . . . . . . . . . . . . . . . . . . . . . .
Read Address Mark . . . . . . . . . . . . . . . . . .
2303 Read . . . . . . . . . . . . . . . . . . . . . . . . .
2302 Bead Address Mark . . . . . . . . . . . . . . .
Channel Data Transfer - Read . . . . . . . . . . .
Microprogram Logic . . . . . . . . . . . . . . . . .
Dual Channel Microprogram . . . . . . . . . . . .
TIMING CHARTS
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start-Stop Timing . . . . . . . . . . . . . . . . . . .
T. R. O. S. Scan . . . . . . . . . . . . . . . . . . . . .
Storage Control - ALU . . . . . . . . . . . . . • . .
2311 Seek . . . . . . . . . . . . . . . . . . . . . . . • .
2321 Seek . . . . . . . . . . . . . . . . . . . . . . . . .
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2303 Attachment SID Write . . . . . . . . . . . . .
Write Address Mark . . . . . . . . . . . . . . . . . .
Channel Transfer - Write . . . . . . . . . . . . . .
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Address Mark (Page 1 of 3) . . . . . . . . .
Read Address Mark (Page 2 of 3) . . . . . . • . .
Read Address Mark (Page 3 of 3) . . . . . . . . .
2303 Attachment SID Read AM (Page 1 of 2) ..
2303 Attachment SID Read AM (Page 2 of 2) ..
Channel Data Transfer - Read . . . . . . . . . . .
2302 - 2311 Track Format . . . . . . . . . . . . .
2321 Track Format . . . . . . . . . . . . . . . . . .
2303 TracK Format . . . . . . . . . . . . . . . . • .
1607-6
1607-7
1612
1613
1614
1621
1622
1623
1624
1626
1631
1632
1633
1634
1635
1636
1691
1692
(10/67)
(10/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(10/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(10/67)
1701
1702
1703
1704
1711
1712
1721
1722
1723
1725
1731
1733
1733
1733
1734
1734
1735
1736
1737
1738
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
(7/67)
2841 Stage 2 FEMDM (10/67)
iii
This page intentionally left blank.
iv
(1O/67)
LEGEND
In positive logic representation, signal levels are disregarded. The negator (N block symbol) is used
to invert logic, not level. Passive elements (such as drivers and pulse shapers) generally are not shown,
since they contribute nothing to the logic.
TIMING ELEMENTS
LOGICAL ELEMENTS
SWITCHES
Name
2.Sms
E-
fl
AND
E-
Momentary
10 kHz
Name
NOT
(Negator)
FS=
: SW :
-B-
-8-
Exclusive-OR
0-
-GSingle-Shot
OR
I
I
~
Er
Multi-Position
Single-Throw
Oscillator
PASSIVE ELEMENTS
xx Abbreviations
SPD
-G-
--BRX
Sample-Pulse
Driver
Schmitt
Trigger
Differential
Amplifiers
Single-Ended
Amplifiers
=Voltage Amplifier
= Line Driver
=Line Terminator
V
LD
LT
MD=
HD=
ID =
CD
=
Magnet Driver
Head Driver
Indicator Driver
Core Driver
STORAGE ELEMENTS
Data
FL
Control
Clear
AC 123~AID
Flip-Flop
Page
Flip-Latch
Polarity Hold
(Complement Input)
REGISTERS AND COUNTERS
Partial ~
Transfer ~
Clear
0
Full
Transfe~
3
--------_·I.
(Reset)
,..------ -. .Name
Register
AA123
o
High Order
/
Logic
Page Number
15
Parity
Generator
For DOWN Count
Gate--1<
I
Multiple Line Transfer
1
Number
of lines
in Bus
-
High Order
12 115
MI SC ELLAN EOU S
Parity Check on
Data Flow
I
+1
Clear .....- - - . - - -...
Counter
<:.arry
o
8C321
7
I~cator
~
i
l£~counter
Advance
~
+ For UP Count
I
Gate~
--~
.pC-·~·-16-.
...
~~-.~.
Full-Time
Pluggable or
Switchable
Off-Page Connector
With Alphameric
Locations
2
Indi.catable Bus
On-Page Connectors
-0 0-
3
B4
A3
~
2
3
With line-of s~
114093 B
2841 Stage 2 FEMDM (10/67)
v
I
s
)
2
CHAt"-IEL TAGS OUT
1
6
CHANNEL TAGS IN
n
j
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BRANCH DECODE
DHOOI-OII
ALU BYPASS (YBY)
42
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r-USPI21
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HSTA~!~:r SET
H
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GBI61
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GB031
7
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GB081
GB161
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L1fJ lf1 Y Lf1 LfJ
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BBOOI-OII
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I
n
~
N
W
o
N
N
......
w ....
OW
w~
OPTIONAL
INTERFACE
I
JX:A
(X)
+
,
PART IAL SUM T /C
RBOOI-002
ALU
ERROR
"U
A REG ASSEMBLER
BAOOI-OBI
~
L..-"5========-I1 CL
L!..
A REG. 1 B+P
RAOOI
r--ALU
".,.
m
A REG ER IE IH ASHB
BA091,IOI,III
MAN OR FEAT ENTRy!
BAl21
en
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HBI51
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(CAS II ONLY)
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N
W
I ~fUR I
IH GATE
GB051,053,055
I All 01-14 I I
REG
RBOO 1-002
'"
7
1
IG REGISTER
p
1
CO~
0 BUS DECODE
o 0
UNIT DATA AND CONTROL DIAGRAM - Storage Control and I/O Interface
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~~LTJ__~----~I__----__~
YCD ALT
1 r.=::::;-----;=====::t--:l... DVOO 1
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~
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~C-A-R-RY-A-ND--I
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>
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0
CB
BRANCH OECODE
l6
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~
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A REG SOURCE
DECODE
19
17
n
SELECTION
GBIOI
~ ~
I,..
1
READ LATCH
•
DBOOI
5
o
OUT
CARRY OUT
CH FILE ENT
1CAS II ONLY)
B REG SOU"CE
DECODE
r;l
I
r--t i •
I'iiPP
CL FI LE ENT
6J
ADDRESS
COMPARE
GB081
~S~E~R~V~IC~E~~~OU~T__________-+-4__~
r31
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3
COMMAND OUT
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GB041
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CHANNEL OUT TAG
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7
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I BYPASSI
t .J
BIT 46
t P
PARITY I
COMPARE r-~
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_
L
' - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
--r---:-A:-:'LU~F---.--..L--
ALDOl
A L071
'--
AL20 I
STORAGE COffTROL AND I/O CHANNEL IffTERFACE
STORAGE CONTROL AND I/O CHANNEL
INTERFACE UNIT DATA
& CTRL
DATE
Z84IR
IBM
1202
OIAG
E
I
I
2
..
3
1
1
5
I
6
7
REFER TO PAGES FA021, 022, 023
FOR INTERFACE INPUT & OUTPUT LI NES
......
FROM UR
REG
,~
MOD I A3B4DI2 ...,
MOD 2 A3B4DII
.~
MOD 3 A3B4B09
J
DR I VE SELECT
)
MOD 6 A3B4B04
~
MOD 7 A3B4B05
CDI3
HBOOI
......
....
CNS
NOT 2311 SEL
("D" BUS S OR 6
......
0
J
J
SERIAL WRITE DATA (SD271)
I
FTO
A3G4BIO ((CONTROL)
FT1
A3G4D11
'CELL ADDR SET
FT2
A3G4DI2
HEAD ADDR SET
FT3
A3G4B13
FINGER ADDR SET
FT4
A3H2BOS
HEAD POS ADDR SET
FTS
A3H2D04
SUBCELL ADDR SET
FT6
A3H2D09
~
....
2321
FILE
......
.....
.....
.......
J
FT7
A3KSD09
r
)
DRIVE READY
A3C5B03
DRIVE OPERATIVE
A3C5B02
READ SAFETY
A3C5B05
WR I TE SAFETY
A3C5B 12
STR I P READY
A3D2BI2
I NVAL I D ADDRESS
A3E5D02
AUTO RESTORE
A3D2B02
CE CELL LOCATED
A3E5BI2
USABLE AREA
A3ESB02
EARLY INDEX
A3D2BOS
2321 ON LINE
A3D2B03
...
FTO
AM
CONTROL
FC7
I
)
~DESTINATION
COlq-D ISBUSFC REG
~
A
CDI4
HBOII
CNS
FT S OR 6
.
.....
...
-FCO
A3F4B05
WRITE GATE ,',
-FC1
A3F4B03
MACH RESET ,'(
-FC2
A3F4D06
SEEK START
-FC3
A3F4DD4
-Fc4
A3F4B04
-FC5
A3F4D02
-FC6
A3F4D07
REST. ,',
-FC7
A3F4B02
r
J
HBOl1
I
-FCP
,.
..
*
,', = GATED BY FTO
(CONTROL)
JR STA ,',
HD SEL >'<-
FROM
FC REG
~
A
r-
c
.....
FT2
J
HB141
HB142
S
A3J4B2
ALT CAI4
FS7
B
I--
rMOD 0 ATTN
A3C2D04
~ MOD I ATTN
A3C2D07
~
MOD 2 ATTN
A3CSD04
MOD 3 ATTN
A3C5D07
r MOD 4 ATTN
A3 ESD04
~
A3ESD07
MOD S ATTN
6 ATTN
A3D2D04
~ MOD 7 ATTN
A3D2D07
,MOD 8 ATTN
...
.
-
~
FRO~
..
...
..........
I E GATE
CNTL
A
I E6-2321 CA 14
BA III
SEEK
COMP
GATING
0-3..
....
A3C6B03
.....
A
ENTRY
0-3
C
HA 121
(SC)
.
~-II ..
....
....
HBI41
+
4
0
ADD'TL
2302
.
A
ENTRY
4-7
...
....
......
12-IS ...
10 ATTN A3BSD04
HB142
t
MOD II ATTN A3B5D07
~ MOD
~ MOD
~ MOD
A3C6B 12
A3C6B02
A
ASM
0-1-2
I-A
ASM
3-4-S
0
HAI31
A
ASM
6-7
I--
rMOD 12 ATTN A3B5DI2
A3C6B09
...
)
A3C6DI2
A3c6ol1
HB041
A3B3D04
~ MOD 9 ATTN A3B3D07
~MOD
f
DATA
LI NE
DVRS
....
SEEK
ADDRESSES
SERIAL RD DATA
13 ATTN A3B5B05
USE AL T
14 ATTN A3B5B02
NOT INH I BII
IS ATTN A3B5B03
CA 12
...... C2E~B02
HAI41
A
...
-
E
HBI06
A3C6B04
A3C6BOS
HB042
GATE ADR REG BYTE
2321. AND OPTIONAL ATTENTION
DATE
HBI31
NOTES;
I. ALL SCOPING POINTS, EXCEPT READ & WRITE DATA, ARE ON 2841 A3 PANEL AND ARE NOT NECESSARILY
DIRECTLY ON REGISTER OR BUS LINE AS INDICATED BY THIS DIAGRAM.
UNIT DATA AND CONTROL DIAGRAM - 2321 and Optional Attention
FS6
HBI41
HBI42
S
T
A
T
U
S
HBIOI
---
-
FS4
FS5
FT 5 OR 6
HBI51
~ MOD
...
..
CELL
PAR ITY BIT
HB031
A
(ATTN RES)
FS3 HB091
(STATUS)
...
(FROM FC7
FT 5 OR
.....:..
FS2
....
HEAD
ADR
REG
(OLD HD
ADDRESS
STORAGE)
.....
FSI
~
A
AlT CA13
..
.....
TO PAGE HADOI
HB021
FC
REG
RD021
PROCESS TIME
A3A3D12
F
I
L
E
FSO
.........
FT S OR 6
FT 5 OR 6
(-
A
CAI5
HBI31
)
HBOOI
( IS 2)
FILE SAFE
BA 131
....
RD021
FT
REG
A
...
(I LINE PER DRIVE)
MOD 5 A3B4B02
USE ALT
FAIL
SAFE
LOGIC
C2J5Bl0
A
~~
MOD 0 A3B4BI2 ,
MOD 4 A3B4B03
HB071
HB081
~
CDl3-D BUS
~
DESTINATION IS FT REG
" D" BUS
ACC &
MOD
ENCODE
A ENTRY
I
I
11M
I
TYPE
I 2841R
1221
I
I
2
I
3
It
1
1
5
I
6
7
WIO DUAL
JUMPER
CHANNEL
ANY
ATTN
2311
ATTN
,.
OUT
~
~
HA091
-..
~
SW TO A
B
SW TO B
Wlo DUAL CHANNEL
..-
GB091
CHAN A
TAGS
ANY
ATTN
OPT
I--
HBI16
I NTERRUPT A
-
HAIII
CHNL
SELECT
SWITCH
ADD'NL
2302
A
-
....
.-
HBI11
,It
QUEUED
IGG LATCH
..-
POLL ENABLE
.,.
..
.
GBI61
~
r
CHNL
INTPP
CTRL
A.;i3
~
INTERRUPT B
~
GB236
C
A ENTRY
(SEEK COMPLETE)
OPT
ATTN
0-3
-
.#'
jl'
UNIT
ATTN
0-3
ATTN
0-3
0-3
~
GB246
HB10J
GROO6
GROl6
GR026
GR036
~
S.C. AND
CHNL
REG
ASH
~
BA206
BA216
BA226
BA236
0
4-7
4-7
..
.
UNIT
ATTN
4-7
~
GB247
ATTN
4-7
GR046
GR056
GR066
GR076
..
~
S.C. AND
CHNL
REG
ASM
BA246
BA256
BA266
BA276
E
DPAL CHANNEL SEEK
COMPLETE AND INTERRUPT
I
DATil
UNIT DATA AND CONTROL DIAGRAM - Dual Channel Seek Complete and Interrupt
1
11M
TYPI
I 284IR
1222
......
V>
o
......
I
I
2
TROS SAL.
OUTPUT
LINES
ODD BIT
I~
14 7
I
OEOOI
TROS SAL.
OUTPUT
LI NES
EVEN BIT
10
I
I
J
s
I
It
I
SENSE AH'
YCH, YCl, YCA, YCB, YCK
I
YPA
I
YPS
;
YCN, YPN, YCD, YCV, YCC, YCS
CONT REG
PAR lTV
I CHK
I
YPC
•
•
KKOll
DR REG
RD041
•
INDICATOR
DR IVER
liND
SPI41
SPI41
ERROR
LATCH
INDICATOR
DRIVER
A
CONT REG MRITY
I INO
I
CN PARI TY
SPI31
SPl41
S.P141
ADDRESS
CHK
ERROR
LATCH
INDICATOR
DRIVER
SP121
SP141
SPI41
~
I
8
PA
I
I
I' N'
PX
0
ADDRESS
PW
7
IP
I""-
ALU
ERROR
I
SUM P BIT
I:
A REG P BIT
NOT SUM P BIT
C
AL211
NOT A REG P BIT
4 I
BUS OUT
PARITY
CHK
I:
I
I
2 J
I
GB121
o
I
ER REG
•
REOOI
INDICATOR
DRIVER
I
I'N'
-
DATA
SP141
I
0
IP
BP
I
0
I
I
CONT REG
BUS OUT
LI NE
RCVRS
GA031
ERROR
LATCH
I
IP
KK321
TROS ADDR
W REG
7
I
I
I
TROS ADOR
X REG
I
6
SENSE AMP
SPill
SPI21
J
142
DEOII
PAR lTV
CHK
I
38
\40
I
0
ONE
FILE
DATA
REG
7
7
5D141
5D142
BIT RING
SD131
SD132
oI
7
I
PAR/SER
WR ITE
DATA
oI
7
I
-
4 POS
B I NARY
COUNTER
Ir
WRITE
DATA
CONVERS I (}I
CHK
INHIBIT
CONTROL
I NO I CATOR
DRIVER
I
lIN'
50171
-
MACHINE STOP
SPIOI
SP141
CE AID
INDICATOR
DRIVER
REOOI
SP141
NOT ONE
SD151
5D201
E
I IN, I
PROBE
ERROR CHECKANAlVSIS
DIAGRAM
DATE
I
I
.....
V>
o
.....
ERROR CHECK ANALYSIS DIAGRAM
18r.,
TYPE
I
I 2841R
1301
.....
tI>-
o
.....
I
2
DE011
I
3
YCC BITS
I
"
5
.....
.-
BY
REGISTER
YCV 0
*
COMPLEMENT
I
..':
...
RB021
RB022
L
PART IAL
SUM 0-3
~
DR
REGISTER
......
....
RD041
.-..
YCK 0-7
DEOOI
0-7
.....
AL081
AL091
r
r
AL21!
.....
---.
SUM P BIT
»
I
0
~
I
CARRY IN
NOT CARRY IN
NOT SUM P BIT
z
-I
»
z
'70
•
'70
'70
" " "
~
SPI51
......
.......
--...
...
ALOOI - AL071
A TO D
XFER
OR
ENTER
~~
A
~
B
D BUS
POWER
........
ALIOI
AL 141
.....
--..
ALU
OUTPUTS
.....
D
BUS
-
ALIOI
A
REG ISTER
~
SP061
-
A INPUT
ENTER
RAOOI
f---
REOOI
-
0-7 SUM
A
BUS
ASMB
...
110...
DATA
SWITCH
ALU
RB002
ALU ERROR
AL211
-<
......
ALU
ERROR
RSOII
0
RBOOI
PART IAL
SUM 4-7
...
......
NOT A REG P BIT
0
1:1
0
»
"
--.....
A REG P BIT ...
»z
("")
....
7
CARRY OUT TO ST3
FUNCTION
DECODE
CARRY IN
DECODE
AND
LATCH
I
6
BIT ZERO CARRY
NOT INH I BIT
3
SET ALU
A
OUTPUT
BAOII
BA081
...
--.....
~,
......
....
...~
C
D EQUAL ZERO
SUM P BIT
CARRY OUT
AL201
~
B3 CLOCK 3
AL ]l·11
0
C C FI ElD 3 BITS
AlU CO NTROl liNES
BIT 0 BIT I BIT 2
AND
0
0
a
ADD OPR - NO FORCED CAR IN - NO CAR OUT TO ST3
0
0
I
ADD aPR - FORCE CAR IN - NO CAR OUT TO ST3
0
I
0
AND OPERATION
ADD
EXCLUS I VE OR
OFF
OFF
"Amr
ON
ON
A7mf
ON
ON
D POWER
ALYYY
0
ALOOI
ALlOI
I
ALOII
All II
2
AL021
ALII I
BIT N
A/OR
m'R'V
OFF
OFF
OFF
ALU
ALXXX
ON
CARRY
ON
OFF
0
I
1
OR 0 PERA TI ON
3
AL031
ALl21
I
0
0
ADD OPR - NO FORCED CAR IN - LAT CAR OUT TO ST3
4
AL041
ALl21
I
0
I
ADD OPR - FORCE CAR IN - LAT CAR OUT TO 5T3
5
AL051
ALl31
I
I
0
ADD OPR - ADD IN ST3 - LATCH CARRY OUT TO ST3
6
AL061
ALl31
I
1
1
EXCLUSIVE OR
7
AL071
AL141
AND
OR
ON
OFF
OFF
ON
OFF
OFF
ON
ON
ON
ON
OFF
OFF
~
E
1/0 OPERATIONS DIAGRAM
STORAGE CONTROL ALU
DATIl
/0 OPERATIONS DIAGRAM - Storage Control - ALU
1
11M
,nl
I
12841R
1401
I
I
2
-
UR
UR
UR
UR
UR
UR
UR
UR
REG
REG
REG
REG
REG
REG
REG
REG
0
I
2
3
4
5
6
7
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
-----
-------------
RUODI
RUDDI
RUDDI
RUDDI
RUDDI
RUDOI
RUOOI
RUOOI
-
- - - RD031
r---
D BUS
D BUS
D BUS
D BUS
D BUS
D BUS
D BUS
D BUS
OBIT
I BIT
2 BIT
3 BIT
4 BIT
5 BIT
6 BIT
? BIT
-----
-------
-----
---
ALIDI
ALlII
ALlll
ALl21
ALl21
ALl31
ALl31
ALI41
HADDI
FT REG
FT REG
FTREG
FT REG
0
I
2
3
-
2311
2311
2311
2311
-
2311 SELECTED
-
+
+
+
+
+
+
+
+
I
6
2311
MOD
SELECT
FT REG
+ DEST. IS FT
s
I
It
3
BIT
BIT
BIT
BIT
2311
INTERFACE
EX IT
HA041
HAD31
2311 TAG
LINE DRVRS
-Q. CONTROL
_Q SET CYL
-Q SET SIGN
-Q SET DIFF
&.
2311
INTERFACE
EXIT
HEAD
-Q
-Q
-Q
-Q.
-Q.
-Q
-Q.
-Q.
MOD
M()D
MOD
MOD
MOD
MOD
MOD
MOD
0
I
2
3
4
5
6
7
SELECT
SELECT
SELECT
SELECT
SELECT
SELECT
SELECT
SELECT
A
FAD I I
FADII
FADII
FADII
-Q. CDNTROL
-Q SET CYLINDER
-Q SET HEAD & 0 IFFERENCE
-Q SET DIFFERENCE
FAD 11
FAOII
FAD I I
FAD I 1
FAD I I
FAD 1I
FAD I 1
FAD 1I
-Q.
-Q.
-Q
-Q.
-Q.
-Q
-Q.
B
HA041
+ 2311 SELECTED
I
~
2311 BUS
DRIVERS
231 I
INTERFACE
EX IT
HA021
I
L....-
---
FADII
FAD II
FADII
FADII
FAD 11
FAOII
FAOII
FAOII
1
-
HA021
FC REG
HA041
FILE
FILE
FILE
FILE
FILE
FILE
FILE
-Q FILE
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
0
I
2
3
4
C
5
6
7
~
-
HAOII
+ DEST. IS FC
RD031
+ CN5 BIT LATCHED - - - DVOOI
1
~
HAI41
0
-Q CYLINDER ADDR
-Q. CYLINDER ADDR
-Q CYLINDER ADDR
-Q CYLINDER ADDR
-Q CYLINDER ADDR
-Q CYLINDER ADDR
-Q. CYLINDER ADDR
-Q CYLINDER ADDR
REG 128 - FAD 11
REG 64 - FADi I
REG 32 - FADII
REG 16 - FAOII
REG
8 - FADII
REG
4 - FADII
REG
2 - FAOII
REG
I - FADII
+ CA 14 DECODE
+ USE ALT CA DECODER PI-
---
DA041
DADOI
SEL SEEK INCOMPLETE--SEL ON LINE
FILE UNSAFE
SEL END OF CYL
-Q SEL FILE READY
FADI I
FAOI I
FADII
FAOII
FADI I
-Q
-Q
-Q
-Q
---
2311
INTERFACE
ENTER
HAD51
-Q OA 128
-Q OA 64
-Q OA 32
-Q OA 16
-Q OA
8
-Q OA
-Q OA
-Q OA
2311
LINE
RECEIVERS
4
2
I
HADll
+
+
+
+
+
+
+
+
OA 128
OA 64
OA 32
OA 16
OA
8
OA 4
OA
2
OA
I
IC INPUT
TO A REG
ASSEMBLER
SELECTED
SELECTED
SELECTED
SELECTED
+ SELECTED
+
2311
INTERFACE
ENTER
2311
LINE
RECEIVERS
HA051
HA081
+
+
+
SEEK INC
ON LINE
UNSAFE
END OF CYL
READY
BAOII
BAD21
BAD31
BA041
BAD51
BA061
BAO?I
BAD81
-
FILE
FILE
FILE
FILE
FILE
FILE
FILE
FILE
ENTRY
ENTRY
ENTRY
ENTRY
ENTRY
ENTRY
ENTRY
ENTRY
.....
.....
.....
I/O OPERA TIONS DIAGRAM - 2311 Seek
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
-
HAI21
HAI31
HAI41
£
BAI31
+ 2311 OPERABLE
HA091
I/D OPERATIDNS DIAGRAM
2311 SEEK
DATE
II'>
0
I
2
3
4
5
6
7
I
I
IBM
rYPE
I
I 2841R
1411
I
J
2
I
3
OPTIONAL FILE SEL.
HB081
2311 MOD N SELECTED
HB061
DR REG BITS 0-7
RD041
I
5
I
6
7
1
A
0
7
I
SET FOR
FOR RESET
FILE
DATA
REGISTER
H
7
PAR/5ER
CONVERSION
7
r---
DATA
WR I TE TR G5 D18 I
0
SDI41
SD142
A
SER OUTPUT DATA
~'l
SD151
7
10-
B I T5
RS 021-- BIT RING 0 (ST 4)
0':875 KC
2.5 MC
OSC
PHASE X
SELECTED
WRITE OSC
J..------... WRITE
TRIGGERS
PHASE Y
BIT
RING
DRIVE
BIT RING ADV
A RING ADV
J
0
BIT
RING
....
1
2
FDR SET
& RESET I - -
~
3
0
WRITE
CLOCK
& DATA
DBl FREQ
WR DATA
~
4
SD181'
SD181
~
SD121
SD131
SD132
WRITE GATE
(M ICROPROGRAM CONTROL) HA 071
7
I~
7
~
....
FILE
WRITE
DATA
DRIVERS
SD181
5D161
WR ITE GATE
SD111
,'r
B
I:
HOD 0-7 WRITE DATA
I
MOD 0-7 WRITE DATA
OPTIONAL FILES
'"'"""
SD166
c
0
WRITE
CLOCK
GATE
~
INHIBIT
~ CLOCK
~ WRITE
NOT INHIBIT CLOCK WR ~
(C LOC K B I T5)
5D091
ADDRESS MARK
L
~
(MICROPROGRAM CONTROL) HA 001
NOT WRITE TRIGGER
J
5D181.
L....--
SD151
L
COUNTER
DRIVE
COUNTER DRIVE
4 POS
BINARY
COUNTER
COUNTER 1
NOT COUNTER 1 WR DATA
!(DNVERSION
CHECK
o
RE 001 - - SER IAL WR ITE DATA ERROR
COUNTER RESET
SD191
DR REG BIT P
RO 041
*:
2321 REFERENCE
5D201
f
5D171
I/O OPERATIONS DIAGRAM
WRITEjWRITE AM
DATE
I
I
TYPE
I/O OPERA TIONS DIAGRAM - Write/Write AM
II",
j2841R
1421
2
3
5
BIT RING
CLOCK TRACK
(FROM SELECTED 2303)
ClK TRK 50 NSEC DlY
PHASE ZERO
ClK TRK 120 NSEC DlY
TO
..::B;..=U~F.:....FE?'R.:. . . . : B. .I..!. .T-'0'--__-1
A
~B~U~F_F~ER~B_I_T____---1
A
BIT RING 2
~F~R....2~________-i
BIT RING 3
FOR 3
BIT RING 4
FOR 4
"':B"71"::'T-:R~I~N:':'G-5:-------t
FOR 5
r-______~C~l_K_T~R_K~18~5~N~S~EC~D~l~Y__~r_--~--~L_LJ
PHASE TWO
ClK TRK 200 NSEC DlY
°
BIT RING I
PHASE ONE
-B~I~T"':R;"'I-N-G-6-::-------t
ClK TRK 2 0 NSEC DlY
ClK TRK
BIT RING 7
FOR 7
PHASE THREE
NOT PHASE THREE
PHASE FOUR
BIT RING SEVEN
NOT WRITE AM
WR ITE GATE
PHASE FOUR
~I'HASE
WR CLOCK GATE
..
N
-HC 161
A
OR
SD161
A
TO DR GATING
HC211
A
FT 0
60
BIT RING
FC 7
NOT FDR P
~------------~
A
r---;::F~DR::-::P~--1 A
8
FL
BIT RING 0
NOT ADDRESS
HC051
NOT WRITE GATE
WR ITE FF
BIT RING 0
WR AM
HC071
~--r--------------+------------~~OR
FF
~~7:IT~S~~~1~:7:~~E':::O---rA~A11---L.....IIl...H-C-07-1-.J
HC 131
BIT RING DRIVE
DELTA BIT RING
MOD X WRITE DATA
HC061
WRITE DATA SAMPLE
J __ DELTA BIT RING
DRIVE BIT RING 7
A
A
A
WRITE PHASE DATA
FIVE
OPT MOD X WR DATA
(TO DEVICES)
-IA
20 NSEC DlY
1
PHASE THREE
WRITE DATA
NOT WR AM
~F~D~R~6~________
HCOOI
PHASE ZERO
6
DBl
DR REG 0
BUFFER
REGISTER
~ _ ~~ _
FOR
0
..
WRITE DATA ERROR
(ER REG BIT I
I'
c
WR I TE GATE
..
I r---
FOR I •
FL
---FDR 2 ...
FL
Fl
- --BIT RING 1
-JA-
BIT RING 2
FL
---FL
Fl
----
BIT RING 3..
.. WRITE GATE
I
---A5
Fl
1600NS
WR GATE
----
JsSI v~~
BIT RING
~A ----
--
Fl
..
~
1T
HCI61
~
_:L__
~ _~L__
DELTA BIT
RING RESET
BIT RING RESET
I/O OPERA TrONS DIAGRAM - 2303 Attachment SID - Write
~ _~l__
FL
FL
-HC091
FOR 4 ..
SD091
FL
SET FOR
----
DR REG 5
FOR 5 ..
Fl
RESET FOR
WR ITE CLOCK GATE
RESET ST 4
---FDR 6 ..
OR REG 6
2303 DATA
TRANSFERRED
(SET ST 4)
DELTA BIT RING 7
VFO RESET
A
I--
OR
FL
DR REG 7
HC231
He221
HC231
po
- --E
FDR 7 ..
...
----
-
DR REG P
r
2303 ATTACH SiD WRITE
FOR P •
.PO
FL
..
FL
HCIOI
DATE
---IB~
He221
o
----
FL
BUIITJRUI~N£GJ6~__~::t==f==I-----~~A~7~__+=~::=f==I-----¥BUIITJR~I~N~G~7y"~
Lt _F~__
WR CLOCK GATE
WR ITE GATE
----
~~ ~ B~I~T_R~IN~G~5~__~==+=~==I-----~~6~6~__4=~::=f==I-----~B~I~T~R~I~N~G~6~,~~
50091
FDR 3 ..
po
WR ITE GATE ...........
~PH7:A;;;::S~E-:-:o~m~E:;:--,1 A
BIT RING 0 1
Fl
BIT RING 4
_
50201
BI T RI NG 4 ..
-
DR REG 3
DR REG 4
]A ~RITE
NOT WR CK GATO START
----
BIT RING 3
MISSING
NOT AM GOOD 1 A L
SEARCH NA, 1 I
HCI61
HC 171
DR REG 2
I
BIT RING 2
AM BIT
----
1422
I
z
I
,
I
)
s
I
I
6
1
7
A
+0 BUS 0 BIT
WRITE
LA TCH
ALlO1
r--
"-
RDO~l
DEST. IG
KCO~1
C3 D TIME
I
A
A
GB131
RESET A TIME
SVC
REQUEST
LATCH
SVC IN
LATCH
r-H
r---
-
GB141
,..-
GB141
~
+ C3 A TIME
8
+CA 15 DECODE
+uS E NORM L CA
--
00'041
DAOOI
+SET D TIME
-RESET C TIME
TRF
ONE
+SET D TIME
-RESET B TIME
GB131
"---
TRF
TWO
RESETS
i....-
GB061
r----
GB131
-
~
- SVC REQUEST
GB1Sl
C
OUT CTI
+SERVICE
_READ LATCH
-
--
to-
GB061
SVC IN
RESET 1
GB131
+
0
A TIME
GB1Sl
+CA 13 DECODE
+USE NORMAL CA
+C3 A TIME
--
---
DAo4l
DAOOI
KelOl
~
SVC IN
RESET 2
GB15l
E
OPERA T IONS DJACM"
CHANNEL DATA TRANSFER - WR JTE
DATIl
I/O OPERATIONS DIAGRAM
-
1
OM
Channel Data Tr nasfer - Write
'''I
1
j2841A
1426
l
I
2
I
3
1
4
I
5
I
6
7
A
BIT RING
PHASE X
VFO ose
BIT
RING
DRIVE
PtV'.SE
r--
PHASE Y
GENERATION
ADV
BIT
DELTA RING ADV
RING
RS 021 ---- BIT RING 0 (ST 4)
J -1
~
RD 041 __ GATE FOR TO DR REG
FOR SET
-..
&
2
RESET
3
8
If
50181
50131
50132
50121
5
6
7
SET FOR
-....
50111
FOR RESET
J
-
L
r--
HA091
READ GATE
(BROUGHT UP BY "PROG)
---
VFO eTl
-
FILE
DATA
REGISTER
C
RD 041 ---- DR REG BITS 0-7
50091
50141
50142
L
DELAYEO DATA ---- SO 061
-{,so066
t
DATA
SEPARATION
& eTl
GENERATION
SO 061
,0(50066
DATA GAP
-
DATA
GOOD
50191
-
-
SEPARATED DATA
DATA GOOD
l
READ
CLOCK
GATE
READ CLOCK GATE
0
50101
~
* 2321
ONLY
E
I/o OPERATIONS
DIAGRAM
READ
DATE
I
I
J/ o OPERATIONS
IB~
DIAGRAM-Read
I
TY'E
12841R
1431
(
I
2
..
I
3
I
I
5
I
6
7
A
VFO OSC
r-
PHASE
GENERATlON
PHASE X
BIT
RING
DRIVE
PHASE Y
50121
50181
BIT RING ADV
DELTA RING ADV
1_
BIT
RING
_'
i---i----
...
SO III
L.....-
BIT RING 4
SDI91
VFO CTL
BU"RY
COUNTER DECODE 8
&
DECODE
DECODE 14
I--SD201
CTR DRIVE
I
--
~
--
SP091
I
*
(ST 4)
& RESET
l
A
a
RO 041-- GATE FOR TO DR REG
FOR SET
i----
I
SDI31
50132
RS 021 _ _ BIT RING
10-
SET FOR
FOR RESET
B
FilE
DATA
REGISTER
~gltJ
r-RD~I-
~
DR REG BITS 0-7
C
SO 061
so 066
SEPARATED DATA
READ ClK GATE
ZEROS
COUNT
CONTROL I -
READ GATE HA 071
ADDRESS MARK HA 001
ZEROS COUNT
ONES RESET
I
L DATA
'---
SEPARATION
t---
DATA GAP
CLOCK GAP
SO 061
,'r 50066
-
DATA
GOOD
-
~
DATA GOOD
......
.....
50191
READ
CLOCK
GATE
-
50101
50191
AM GOOD
0
I
SELECTED RAW DATA
50081
ZEROS
DETECTOR
AM
~TECTION
t-
L RESTART
AM NOT FOUND
RESET
LATCH
10-
*50036
SO 031
* 2321
I-.
L...-.-
50211
50101
E
ONLY
1/0
DATE
I
I
I/O OPERATIONS DIAGRAM - Read Address Mark
IB~
OPERATIONS DIAGRAM
READ ADDRESS MARK
TYPE
I
I
2841&
1433
.....
2
~
C/.)
~
~
......
C>
.::J
5
3
BX BURST GATE
LINE NAME
SET ax
A
SET BYTE IN REGS
6
7
1ST OA TA BYTE
3RD DATA BYTE
BURST LATCH
(SET DR)
BURST FF
BY BURST GATE
BY BURST GATE
BX BURST GATE
aURST LATCH
~
~~6 _____________~A SET BB
!.IT__RING
L.J
....
SET BB
h
FL
BURST FF
DELTA
BX BUR 5T GATE
NOT 2 0
RESET FOR
BY BURST GATE
READ GATE
HC2 1
L.-LJ
BUS P
A
I--
1 BIT
-- -
A
-A OR
--
~
BY 2 81T
BX 2 BIT
BX 3 BIT
-
-A OR
~
I--
A
-- ......
r-- i - - OR
BY 4 81T
~~
OR
~~
ax 5 BIT
~
BX 6 BIT
BY 7 BIT
BX 7 BIT
-
A
I-- OR
A
I--
~
PH
-
f
t---
PH
r--
-
f
f
t---
J
t---
~
-
~
~
BB 3
PH
FOR 3
BB 4
BB 5
t--~
PH
BB 6
A
t---
I--
I
OR
A
___ L.....-
r-~
IDE
--.--.
FOR 6
A.
r1L
.--.
FOR 5
r
8t
Eh
--
PH
PH
IOE
IOE
.........
BUS 1
--
BURST 2 BIT
~
r--
BURST 3 BIT
-r-
FOR 7
SET BB
1\8036
Eh
RB021
I
I
r--- OR
A
r--
---
-
I
OR
~~
BURST 4 BIT
t--
~
~
D BUS 0
PH
BY 0 BIT
--..
r--
PH
BY 1 BIT
r--
PH
BY 2 BIT
--.
-
.-
I
OR
I
I-- OR
A
o
p- ~ t-A
~
r--
-
r--
PH
BY 3 BIT
po.-
BY 4 BIT
PH
BUS 7
'----
L
BURST I BIT
A
~
I
OR
--'A r-- OR
A
":'":"": ':-:-
RB021
~
r--
BURST 2 BIT
-
o
BUS 3
.~
J
~
PH
J
~
PH
J
~
PH
J
~
PH
I
~
PH
I
~
PH
BX P BIT
......
po
BX 0 BIT
.....
po
i---
-A OR
-A -
OR
ax 1 BIT
.
c
P"
BX 2 BIT
A
-..
I-- t---
A
I--
BURST 3 BIT
OR
A
~
D BUS 2
PH
A
o BUS
4
.-
r-- r-- OR
A
A
I-- OR
~ r--
BX 3 BIT
--
-""
~
PH
BY 5 BIT
......-
r- r~
t--
r--
PH
BY 6 BIT
1
t---
BY 7 BIT
PH
--.
-
..
BURST 6 BIT
D BUS 7
.-
BURST 7 BIT
SET BY
I--
BX 5 BIT
.......
o
OR
I-- t--
I
A
--- -
-- I-A
OR
A
-
po
A
J
OR
A
-'---
RB021
.........
I-- t - -
A
D BUS 5
D BUS 6
BX 4 BIT
A
~
t--
A
BURST 6 BIT
D BUS 1
r--
L.....- i---
BURST 5 BIT
BURST 5 BIT
BUS 6
--A
BURS T 4 BIT
A
~~
BX BURST GATE
I
r--
~
A
BUS 5
D BUS P
~
p-- ~ t""""""
BURST 7 BIT
r--
A
A
BUS 4
o
BB 7
.......
.-
NOT BURST LATCH
A
A
BUS 3
'"'-
PH
BY P BIT
~
A
~~
0
PH
BURST 0 BIT
-- -
BUS 2
0
I
r- r--- I"'A
r-- OR
~
BURST I BIT
o
Ir
A
BURST OBIT
0
BB 2
FOR 2
OR
IOE
D
FOR I
I-- I-A
-
FOR 0
FOR 4
...... I-- I-BY 5 BIT
--
BB 1
A
BX 4 BIT
BY 6 BIT
I
~ ~
~
BB 0
NOT BURST LATCH
r- r- I-o BUS 0
A
BY BURST GATt: L - r- t--- OR
I--
A
A
f'H
A
...
I--
A
~
BY 3 BIT
r--
~ ~
P-
ex
OR
A
BX BURST GATE
BY I BIT
I-
r--r--
BUFFER
BURST REG
r--
B
BX REG
BY REG
A
HC241
0
BY BURST GATE
BX u BII
SET DR
FF
NOT FC
BY 0 BIT
______________r-l _________________
SET ST 4
RB036
BURST LATCH
GATE
BX
SET BX-BY
RBOII
~
BX 6 BIT
PH
-
-.a.
E
BX 7 BIT
PH
...-
SET BX
RBOII
BURST CHECK DATA FLOW
2303 ATTACHMENT
DATE
2841R
I/O OPERATIONS DIAGRAM - 2303 Attachment SiD - Burst Check Data Flow
11M
1 434
I
1
2
,
T
)
s
I
I
6
I
7
A
SERVICE OUT CTI --GB061
D BUS 2 BIT
--ALIII
READ
LATCH
+ SET B TIME
A
SVC IN
LATCh
-
~
r--
GBI41
GBI31
IG
RD031 DEST
SVC
REQUEST
LATCH
GB141
+(3 A TIME
KCD71 C3 D TIME
B
A
[
~
+ CA 12 DECODE
+ USE
~HAL
CA
TRF
ONE
--MOItI
--DAOOI
+ SET D TIME
TRF
TWO
- RESET BTl ME
+SET D TIME
~
GBI31
GBI31
f------'
)
)
GB061
-
-SVC REQUEST
) GBI51
C
-RESET C TIME f
SVC IN
RESET 1
+ SEIWICE OUT CTI -GB061
0
-LATCH 2
GBI51
~
+ CA 13 DECODE
- - M041
+ USE NORML CA
- - DAODI
+ C3 A TIME
--KCIOI
SVC IN
RESET 2
E
GBI51
I/O OPERATIONS DIAGRAM
CHANNEL
~TA
TRANSFER - READ
DATil
I
/0 OPERA TrONS DIAGRAM - Channel Data Transfer - Read
IBM
Tnl
I
I 2841R
1436
....
~
9
8
7
6
5
4
3
2
I
N
-....
Tags Out A
-
CH and C L Branch Control
o
Operational Out Chan A
0'1
Operational Out A
~
AG
r-~~--------------~G
Enabled A
A
Command Out Chan A
Disc + Busy
GB041
Connector
Branch Condition COMMO
Gated Command Out A or B
Gated Command Out B
A
B
C
D
E
PH
Gated Command Out A
Switched to A
AN}------------------------.--~
Servi ce Out B
Gated Service Out
Service Out A
Service Out Chan A
F
Branch Condition SERVO
G
H
I
J
K
L
M
N
0
P
Q
R
S
T
U
V
PH
Gated Suppress Out B
IG5 Bit Status In Latch
Address Out A
Address Out Chan A
Gated Addr Out A
FL
Gated Addr Out
B
Suppress Out Chan A
Initial Select A
Hold Out Chan A
Initial Select B
Select Out A
Branch Condition SUPPO
PH
GB061
Dlyd Select Out A
Select Out Chan A
Branch Condition SELTO
Not Disc + Busy
Connector
From
4,E4
2,06; 4,B7
2,B4,C6
4,B2,AS
3,B4; 4,C7
I,E5
3,02
I,A4,E6
4,A7
I,B6,05
I,A6
I,C5
3,02
I,C4
3,OS
I,C5
Not Shown
1,05
1 ,E6; 3,B6
3,02
I,C5
1,A4,A6,E5i 4,C2,A7
W
2,C9
2,E9
3,05
3,A4
3,B4
3,B4
3,C3
3,C3
3,A9
3,B9
3,BS
3,C9
3,09
3,E9
3, E9
3,E9
I,C9
1,09
2,09
2,08
1,89
4,88
X
Y
Z
AA
A8
AC
AO
AE
AF
AG
AH
AI
AJ
AK
AL
AM
AN
AO
AP
AQ
AR
SCU
PH
Fl
(From Selection Relay
1450-4, E9)
Logic Start
c
Initial Select A or B
K
To
I,A9
I,A9
I,B9
1,09
I,E9
3,D9
2,A3
2,B4
2,B4
2,84
2,C5
2,C5
2,C3
2,04
4,09
2, E4
2, E5
2, E5
2,A6
2,A6
3, E5
2,C9
SCU ~Circuits for the basic 2S41
N.S. ~ Not Shown
----. Lines to the Channel -Lines from the Channel
125 ns
Select Out
Latch
From
SCU
GB041
Tags Out B
Operational Out Chan B
Gated D Iyd or Se lOut A
Branch Condition SORSP
SVC Request PI
AF
Switched to A
SCU
PH
Operational Out B
N.S.
M
Enabled B
IG? Bit Addr In Latch
GB061
GB046
~~-RO--S-E-r~ro~r--------------~
Command Out Chan B
Gated Command Out B
AM
Initial Select A
~~~~~~------------~
Switched to 8
(Not) Propagate Sel Out A
A
Switched to B
OR'~-------4'---;"
}-__~(_N_o~t)~P_r_o~p_ag~o~t_e_S_e_I~O~u~t~B~____~ A
Service Out B
Service Out Chan B
Initial Select B
N
D
erotionol In Latch
Address Out Chan 8
Gated Address Out B
Switched to B
Gate D Bus to IGReg
4
Suppress Out Chan B
D Bus 1 Bit
Gated Operational In A or B
Steering Latch A
Hold Out Chan 8
Select Out B
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
ORr----------------+~~
. Select Out B
125 ns
Select Out Chan B
E
(From Selection Relay)
CU
Logic Start
'!Wo ChaDDel IDterface - Part 2
Holt 1+0
GB191
GB211
GB216
>-________-4.:0:.,:R.:..
Switched to 8
GBI91
OR
A
FL
GB046
A
IG 5 Bit Status In Latch
>-_S_t_ee_r.;..in-'g'--Lo_t_c_h...;B_____~ A
D Iyd Se lect Ovt B
Select Ovt
Latch
~~--~
Select Out A
(Not Responding On A or 8)
FL
ER7
To
I,C4
I,E6
1,05
2,C4; .,A7
2,85,E7; .,A7
I,C5; 4,C7
4,C6
4,86
4,A7
2,C6
I,A6; 2,A2; .,87
4,88
4,A3
4,A3
4,B3
4,83
2,02; 3,02; .,86
2,A2; 3,02; 4,86
3,02
3,C7
2,05
I,A5
3
2
Not) Reset Control Chnl A Latch
-....
-
Togs In A
Switch Register Unit 4
(One of Eight)
Reserve Unit 4-A
PH
AA
>-____________________r-'-A__
o
9
8
7
6
5
4
•
IG 5 Bit Status In Latch
>------------1
Status In Chnl A
Status In Coble
ChnlA
Address In Chnl A
Address In Cable
ChnlA
Service In Chnl A
Service In Coble
ChnlA
CD Alt Bit Latch
0\
~
*
Device End
A
A
IG 7 Bit Addr In Latch
Pack
Change 4-A
PH
Gated Addr Out A
D Bus' Bit
Servi ce In
SCU>-------------~
Operational In A
SCU)-_D_B_u_s_2_B_i_t__________~--+_~A~
The module that is
selected controls
which SW register
is read into.
+' Busy 4-A
PH
GBI61
Operational In A
Ta A Regi ster Entry
IG 6 Bit Latched
Seek In Progress
D Bus 3 Bit
A
PH
A
PH
Request In Coble
ChnlA
Switched to A
AM
+ Busy 4-A
>-+-.....----------1
Operational In
Coble Chnl A
B
Request In Chn I A
Gate SW 4 Reg
Metering In Cable
Chnl A
A
AK )-_SW
__R_e..::g~C
__
hn_I_B__
Re_s_e_t____- I
RW046
Power Off Gate
BUS IN A
CU Busy Status A
•
Device End * Pack
SCU>-_D_B_u_s~5_B_i_t___________+--r_~A
__
AD~~~~~~~~----~
Change 4-B
PH
GB161
IG 6 Bit Latched
AC
>--------1
Device End * S.C.
D Bus 6 Bit
A
~
+ Busy 4-B
PH
The following circuits
are repeated for
channel B: In Cables B
(GB 176), In Chnl B
lines (BGI66), Attention Unit lines (GB236,
GR046)
Switched To A
______________~A
Poll Enable
AB
OW
~----'
Interrupt Chnl A
Queued
Operational
In A
AH
GBI71
Metering
In A
OR
A
OWP
GB236
C
D Bus 7 Bit
OWO
+
PH
CU End A
Busy 4-B
Attention Unit 0 Ch A
Attention Unit I Ch A
CAO Decode
Attention Unit 2 Ch A
OWl
I CA16 Unit
Alt CA Decoder
Attention Unit 3 Ch A
4 Decode
OR
Attention Unit 4 Ch A
(Not) Switched to B
OW2
(Not) Rc,erve Unit 4 B
REG
I
I
I
is se lee ted controls which SW
register is read
out.
DW3
0
The SW registels
hold the statu; of
each module as
refel enced to
channel A or B.
GB236
N.S. Attention Unit4Chni B
Attention Unit 4 Chnl A
r-_D_e_vi_c_e_E_n_d_*__
Pa_c_k__
C_ha_n..:g~e_4__A__+---i A
Device End * S.C. + Bus
DW4
4 A
Attention Unit 4
hr----------------~SCU
A
(Not) Meter Block
>-U_n_it_4~A_tt..:e..:n..:ti~o~n____________.....~ A
H--~-";"'---";';~O
N
OW5
Seek In Progress + Busy 4A
(Not) Seek In Progress + Busy 4B
OW6
E
23
21
19
16
14
12
B02
B09
+6v
Coil
+3v
GBII'
24
22
Note: Circuits for bus in, P through 7 bits,
for Channel B are the same as for Channel A
(GBII6).
•
•
BIO
B 12
Power Off Gate
•
•
•
•
Incoming Sel Out Cable A (From Channel Or Previous Unit)
20
15
13
11
B09
BIO
D12
D13
•
•
•
•
(Not) Power Off
+6v (+3v If isolation feoture
is not insta lied)
Degate
SP041
DJ3
• •
RD021
•
20
,
24
Sel In Out Coble Chnl A (From Next to Last Priority Unit)
13
GB031
Sel Out Receiver Chnl A (5.1 Out Chnl A
15
Sel In Driver Chnl A (Propagate Sel Out A) (Up if This Unit Not Selected)
Outgoing Sel. Out Coble A (To N.xt UnIt)
Jumpers For Lowest Priority Unit
Jumpers For Other Units
Two Channel Interface - Part 4
Interface
II
OW7
(Not Poll Enable)
GR046
The selectior, relay circuit for Chnl
B is the same as Chnl A (GB036).
Selin Cable Chnl
A (Back to Chnl)
c
ca
1
u
I
I
c
I
WJ
!:
3
iN
...J
Q
~
I!:
<
~ z
~
U
.
C
0
A
e
""
+C
:!,B
I
#'~
E
I
...J
-0
11'1
H
~
:;:)
'a:""
ALU OPERATION
DC • A0 B+C
DNST21
~
Q
a:
~
e>a:
>-a:
a: 0(
Q
Q
~
-~
SALS OUTPUT'S
BECOME GOOD
+.
'""
:)
5
:;:)
5>-
~
II ""
~!OJ
co
11'111'1
~II.
!OJ
I.)
Q
VI
11'1
~
)(
'a:""
III:U
~u
~
DEOOI, OIl
I.)
z
~-
""z
i
!
~
Q
Q
z
<
Q
Q
0(
0(
~
U
10.1
U
III:
:;:)
Q
11'1
~
-...
~
C
C
.....
.....
~
e
."'
U
!
-..
Q
II
!
!
III:
III:
1:1:1
Q
l-
~
i
:;
11'1
II.
I.)
t
0
\I:)
~ '-'
'""
...J
AL.U OPERATION
I"'-
0
-
>-
5
\oD
~~ & CB
FIELDS ARE
DECODED
DAXXX, DBOOI
-
A & B REGS
ARE SET
ALU SUM AND CARRY OUTPUTS
FROM INDIVIDUAL. BIT POSITIONS
ARE NOW PRESENT"
RA, RBOOI
,
,
CS FLO IS
DECODED
05001
'"
CC ,C 0, CVHDS
ARE DECODED
DC, DO, DVOOI
ALU OUTPUT
IS SET
AL141
'ICARRY OU'" AND 110 EQUAL ZERO"
LATCHES ARE SET
1
..-
RESULT IS SET
INTO DEST REG
DESTINATION REGISTER IS SPECIFIED
BY CD FIELD IN AL.U OPERATION
RS-XXX
,
BRANCH ON RESULT
OF PREVIOUS
BLOCK
CO; DOX71
~
-
/'
\..
I--
-~
00
. 10
.. ,01
~
1"
SET ST(2)
,
RSOll
IF PRESCIU BED IN ALU STATEtlENT.
CARRY OUT SETS ST (3)-1
IF PRESCRIBED BY DNST21, D NOT
EQUAL ZERO IN AL.U OPERATION
SETS ST(2)-1
1
-
OELA YEO BRANCH
ST(2); ST(3)
-
.)
SET STO)
RSOll
f"'I
'"'"
I
~
--,
CO • CH BRANCH ON CARRY OUT
FROM IMMEDIATEL.Y PRECEDING
AL.U OPERATION
DOX71 - CL. BRANCH ON IMMEDIATEL.Y
PRECEDING ALU ZERO OUTPUT
1
00
-I"
01
...
~
10
,~
11
N
FLOW CHART - Storage Control- ALU
1601
(7/67)
2841 Stage 2 FEMDM (7/67)
1601
3
2
•
4
5
Reset
QS070
A
Post status and sense
information.
08030
Post zero status.
05081
Turn off the op-in FL
if it is on.
Turn off the contro I tag.
B
QS081
Turn the flag register
bits off.
Turn off the fi Ie mosk
bits.
c
QS091
Deselect the device.
Turn off all the fi Ie bus
and tag lilies.
D
Deselect the File interface.
To OB010 wait
loop waiting for
SELlOUT
Note: Machine reset and system reset operations are recognized by the ST7 bit.
ST7-1 means not system reset. ST7 is also turned on to end reset operation.
The 2841 loops from 05030 to 05091 unti I all outstanding attentions are reset.
E
F
G
H
FLOW CHART - Reset
1604
(lO/67)
6
3
2
5
4
6
( 1604-E5)
A
Select the device.
No
Yes
QB050
Q8010
Address out and se lect
out are up.
Gate address byte into
the 2841 .
QBOlO
B
Address in rises when
address out falls.
No
Raise the operational
in line and enable the
address in line.
QB040
Convert the oddress
byte to module select
address.
No
Unit check in status
byte. Unselected file
status on sense command.
Check for device busy,
safe, seek inep,
on-I ine, and end of
cye.
Yes
QB040
c
Convert the module
select number to device
type.
Indicate device end in
initial status byte.
No
No
QB020
Turn off the address
in FL.
Go to end procedure
o"d post status.
D
Go to command decode
QPOIO
E
F
G
H
Fl.O\\' CHART - Initial Selection
2841 Stage 2 FEMDM (10/67)
1605
2
•
3
4
5
A
End procedure determines if a chained ar uncha ined end of operotion ex ish end presents the ending status. Also, in end procedure the 2841 does some of its internal
housekeeping in order to seve time. For example, erese gate must be dropped 40 }Jsec efter write gate. Instead of just counting 40 )Jsec, the 2841 starts to process
ending procedure but keeps track of the time end turns off erase gete at the proper time. And if the operations are chained, the 2841 must keep track of the time in
order to make sure the channel presents the next instruction in time. For example, when doing 0 seorch I D equal chai ned to read data, the read data instruction
must be presented in 60 ).Isec because of device speed or else the 2841 reads the wrong deto .
The 2841 keeps track of time by bumping a counter every other micro program word (I.E. every microsecond). (BX + 0 + 1 --.. BX). By initially setting BX
equol to a number ond bronch i ng on corry (counter overflow), the 2841 con keep track of time. The size of the number set in BX vories depend ing on the amount
of time delay needed For a device or an instruction operation.
B
Therefore all through ending procedure, the 2841 is continually checking corry and index. If either corry or index is detected, the 2841 bronches to these routines.
When entering these rautines, the program is under control of the ST register bits 0, 6, & 7 as shown in chort below.
ST
..
0
6
7
Formatting: Do nothing
Turn off write gate
0
0
C
0
Turn off erase gate
0
Check safe
0
0
0
Head selected: Read
0
Read gate on
0
Heod is not se I ected
I
wri te, both off
Entrance to end procedure is done on QS010 or QS020 for the mo jority of the j nstruc tions.
o
E
F
G
H
FLO\\' CHART - End Procedure - Part 1
1607-1
( 10/67)
6
2
3
6
5
4
Entrance to
Ending Procedure
A
QS020
Yes
No
B
Q5030
Yes
c
Sheet 4, A3
Yes
cb
Sheet 3, A3
Yes
D
~
Sheet 4, A3
No
Sheet 3, A3
Regenerate address of
previous instruction.
Yes
E
Untimed Exit
Sheet 6, A3
Na
Timed Exit
Sheet 5, A3
F
G
H
FLOW CHART - End Procedure - Part 2
2841 Stage 2 FEMDM (10/67)
1607-2
3
2
4
6
5
Corry (Counter Overflow)
Sheet
Sheet
Sheet
Sheet
A
2, 86
2, D2
2, D3
5, C3
No
No
No
Yes
0(040
Read gate is on; reset
B
the timer.
Yes
c
D
E
F
G
H
FLOW CHART - End Procedure - Part 3
1607-3
(10/67)
2
5
3
Index
Sheet
Sheet
Sheet
6
Sensed
2, C6
2, 02
5, C3
A
No
No
No
B
OC070
OC070
Read gate is on: Turn off
the index latch.
Read, write and erasE'
gate ore off; Turn off
the index latch .
•
Yes
No
Store constant in DR to
keep track of ti me.
c
OC070
OC070
Index passed, set OP4 =0.
D
OC040
Return to the program
at the point left.
E
F
G
H
FWW CHART - End Procedure - Part "
2841 Stage 2 FEMDM (10/67)
1607-4
2
3
~
~
Timed Exit
Sheet 2, E5
D
A
QS050
Increment the timer.
No
B
No
Yes
Turn :>ff the op2rational
in latch.
c
Go to chained
reselection OC010
No
o
E
F
G
H
FLOW CHART - End Procedure - Part 5
1607-5
(10/67)
Sheet 4, A3
4
5
6
2
3
4
5
6
Untimed Exit
Sheet 2, E3
A
Yes
OS061
No
Stack the status byte.
8
Yes
No
Yes
Reset the operational
in latch.
C
Sheet 7, A3
Yes
o
Yes
Yes
E
No.
Yes
Not chaining on channe I end; turn off the
device oddress .
Go bock to start of end
procedure. Go through
OG162.
Sheet 7, A3
F
G
H
FLOW CHART - End Procedure - Part 6
2841 Stage 2 FEMDM (10/67)
1607-6
2
..
3
5
4
Sheet 6, C4
Sheet 6, F3
A
Chaining
f
Ye5
No
No
No
B
05070
Tromfer seme into DH
maintain contingent
contection.
Raise the address in line.
OB050
05081
Go to select device
routine. QB050
c
Yes
Ye5
No
Yes
D
No
Dese lee t the dev i ce .
No
No
E
F
G
H
FLOW CHART - End Procedure - Part 7
1607-7
( 10/(7)
Yes
6
u
!:
-=r
ClO
N
2311 ADDRESS BYTES
BYTE 0
BYTE I
BYTE 2
BYTE 3
BYTE 4
N
\0
...
BYTE 5
&.
~
~
HEAD
CYL
0
0
a
~
0-202
0
ct:
0-9
~
u
BIT DESIGNATION OF SELECTED MODULE
IS SET INTO DR REG. CONTENT OF UR
IS GATED TO FILES BY FT:1.
FT=I SETS 1E .. I.
FILE SELECT I ON
QB050
:ao::
....
....
'"
~-
....J
~
""
N
......
C
Q
•."...
MOD SELECT
HA031
SELECTED ON LINE
SELECTE 0 READY
SEL NOT END OF CYL
SEL NOT SEEK INCOMPLETE
SEl NOT UNSAFE
23 I I OPERABLE
HA091
NO
+
2311 SEEK OPERATION
PURPOSE: SELECT 2311 INTERFACE
SELECT MODULE
TRANSFER CYLINDER AND
HEAD ADDRESS TO SELECTED
MODULE
START SEEK
,r
COMMAND
DECODE
BREAKOUT
FILE NOT
OPERATIVE
~B082
QD040
1
t
TRANSFER
ADDRESS
BYTES
TO END
PROCEDURE
QG030
+
CALCULATE CYL
ADDRESS DIFF
AND SIGN
QG070
~
ERRORS
QG060
,.
NO
YES
STATUS NOT CK
QGo60
TFR HEA 0 RE SET
BIT TO FC,
RAISE eTL TAG
QGI30
RESET HEAD
REG
r
HAOOI-OOI
TRF. HEAD ADDR
TO FC RA ISE SET
SIGN & HEAD TAG
QG130
.r
~
HOLD FOR 2 USEC, THEN SET FT (2)
OFF AND RESET Fe
FC=DH
FT= 32
5
FC=GL
FT=64
~
5
STORE HD
ADDR. IN
FILE
HAOOI-Oll
TFR en ADR
TO FC, RA ISE
SET CYL TAG
HOLD FOR 2 USEC, THEN SET FT (I)
OFF AND RESET Fe.
QGI30
.Ir
STORE CYL
ADR IN
FILE
HAOOI-Ol1
SET SIGN BIT
INTO FC RA ISE
SET HD & SIGN
TAG QG 130
·Ir
TFR CYL DIFF
ADR TO FC.
RA ISE SET 0 IFF
TAG QG 130
FC=KL
FT=32
~
5
HOLD FOR 2 USEC, THEN SET FT (2)
OFF AND RESET FC,
SET CY L
SIGN
HADOI-OII
t----------------.. . . ----------........f
~
~
FC=DW
HOLD FOR 2 USEe, THEN SET FT (3)
FT=165 OFF AND RESET Fe.
SET CYL
COUNTER. RESET
ATT LINES
HAOO 1-0 11
~
TFR SEEK START
FC=32
BIT TO Fe.
~---------------TT"""-----------I
-128
RAISE CTl TAG
"
FTQGI30
N
HOLD 2 USEC. THEN SET FT (0) OFF.
TEST FOR READY AND GO TO END
PROCEDURE.
'INITIATE
ACCESS
MOVEMENT
HADOI-Oll
END PROCEDURE
QS020
FLOW CHART - 2311 Seek
1612
(7/67)
2841 Stage 1 FEMDM (7/67)
1612
u
2321 SEEK (BBCCHH)
'I'"
!:=
SELECT 2321
INTERFACE
QOO4O
,
FILE SELECTION
QBOSO
t
~
2321
OPERABLE
QB050
COMMAND DECODE
BREAKOUT
QE060
MODULE
SELECT
t
FILE NOT
OPE RAT IVE
QOO50
~
L..-
J,
00
N
2321 AD DRESS BYTES
~BIT
DESIGNATION OF
SELECTED FILE IS
SET INTO UR, AFTER
WHICH, FILE BECOMES
SELECTED
TFR ADDR
BYTES FROM CHAN.
CHECK SEEK LIMITS
DURING TRANSFER
QG030, 040, 050
0
0-9
NOT USED
CELL
BYTE 3 BYTE 4
CYl
HEAD
0-19
0-9
SUBCELL FINGER
0-4
...
BYTE 5
HEAD
0-19
HD POS HD ELEHE
M
\.D
L
...
~
~
c:(
:J:
u
~
w
w
VI
~
N
~
N
...J
""'
...C
III
D
...•:E"'
SELECTED ON LINE
SELECTED DRIVE READY
DR IVE OPE RAT IVE
SEL NOT UNSAFE
K
END PROCEDURE
DL ~ HEAD ADDRESS
DH = HEAD POSITION
GL = FINGER ADDRESS
KL = SUBCELL
OW = CELL
PRESENT
STATUS
QE010
SET SEEK
LIMIT
QG020
BYTE 1 BYTE 2
BIN
CYL
BYTE 0
BIN
HB071
2321
OPERABLE
HB091
~
)
FT(6) SELECTS 2321
INTERFACE
TEMPORARY LOCATION OF
ADDRESSES APPEAR IN
ABOVE REGISTERS ENTERING
QG110
,CELLSUBCELL -
} RECE IVED FROM CHANNEL
IN THIS ADDRESS
0-19 0-19 0-19 0-19 0-19 0-19 0-19 0-19 0-1 9 0-19
FORMAT
00
02
01
I
.
I
I
I
I
I
I
I
.
I
I
I
I
I
04
03
I
06
05
I
I
I
I
I
I
I
I
I
I
I
09
08
07
-+----f
II
I
1
CELL- 00 01 02 03 04 05 06 07 08 09 10 11 12 13 141 15 16 17 1819 } CONVERTED TO THIS
ADDRESS FORMAT
SUBCELL - 0-9 ~9 0-9 ~9 P-9 ~ 0-9 o~ 0-5 Q.9 O~ ().9 Q.9 P-9 0-91 ~().9 ~ 0-90-9
CONVERT
FINGER AND
HD POS ADDR.
IHEAD POS & FINGER ADDR''WE IGHTED"
PER CHART ON CLD PAGE QAOO7
NOTE:
ADDRESSES ON THIS CHART ARE
EXPRESSED IN DECIMAL ALTHOUGH
THEY ARE ACTUALLY RECEIVED
FROM CHANNEL IN "HEX" FORM
QGll0
TFR HD ADDR TO
FC, RAISE "SET
HD ADDR"
QG130, 131, 140
•
FT
= 32. HOLD FOR 3 USEC
THEN SET FT (2) OFF
FT
= $. HOLD FOR 3 USEC,
THEN SET FT (4) orr
HD ADDR SET
HB061
TFR HD POS TO
FC, RAISE "SET
HD POS"
QG130, 131, 140
/
•
HD POS SET
HBO~1
FAO 3
TFR FNGR ADDR
TO FC, RAISE
"SET FNGR ADDR"
QG130, 131, 140
FT =16. HOLD FOR 3 USEe,
THEN SET FT (3) OFF
•
FNGR ADDR
SET
HB051 FA023
TFR SUBCELL ADDR
TO FC, RAISE
IISET SUBCELL
ADDR"
QG130, 131, 140
i
r
FT = 4. HOLD FOR 3 USEC,
THEN SET FT (5) OFF
SUBCELL ADDR
SET
HB051 FA023
TFR CELL ADDR
TO Fe, RAISE
"SET CELL ADDR"
QG 130, 131, 140
•
FT = 64. HOLD FOR 3 USEC
CELL ADDR SET
HB052 FA023
TFR "SEEK START"
TO FC, RAISE
CONTROL TAG
QG130
•
rC=32 )
\.FT=128
~~~D~~P6jo~~tfEliE~2R
EADY. G TO
~ND
RO
SEEK START
HB061 FA021
N
END
PROCEDURE
(1S020
L
FLOW CHART - 2321 Seek
1613
(7/67)
2841 Stage 2 FEMDM (7/67)
1613
I
c
u
I
CD
I
...
I
c
~
~
00
N
""'-
2303 ADDRESS BYTES
BYTE 0 BYTE I
T
,...
BYTE 2
BYTE 3 BYTE 4
BYTE 5
0
0
FILE SELECTION
QB050
0
/lC
HEAD
0
0-79
.. .:t
\0
III
I-
CYL
-
~
(,.)
0-9
~
~
~
....
....
V)
~
!...J ""
0
"-
BIT DESIGNATION OF SELECTED MODULE
IS SET INTO UR REG. CONTENT OF UR
IS GATED TO FILES BY FT=2.
FT=2 SETS IE 3 BIT AND IE 6 BIT
t
...J
""
:::I
N
"")
"':"'
~
c
a
- ...:IE
•
MOD SELECT
HB071
-
~~
2303 OPERABLE
HBI21
SELECTED ON LINE
SELECTED OPERATIVE
23~ NO
~
OPERABLE
QB071
YES
~~
•
•
COMMAND
DECODE
BREAKOUT
QD040
~
1
•
TRANSFER
ADDRESS
BYTES FROM
CHANNEL
QG030
11\
FILE
NOT
OPERAT IVE
QB082
2303 ADDRESS DECODE
ADDRESS
FROM
CHANNEL
TO END
PROCEDURE
WEIGHT
BYTE 5
0-9
BYTE 3
0-79
128
64
32
16
8
4
2
1 128 64
BIT
0
1
2
3
4
5
6
7
0
1
32
2
BIT
-
1
2
3
4
5
6
7
-
-
-
16
8
4 2
2303
TO
0-19
1
WE IGHT
ADDRESS
TO
2303
16
8
4
2
I
3
4
5
6
7
-
4
5
6
7
8
4
2
1
2
1
2303
SECTOR
0-3
2303
RACK
0-9
~
~
-
FI~ YES
UNSAFE
QG060
NO
.If'
STATUS NOT OK
QG060
TFR RACK ADR
TO 2303
QG130
I
~
TO END
PROCEDURE
~
J
Fe-"
FT=128
1
Fe=DH
FT=16
~
HOLD FOR 2 USEC, THEN SET OFF
STORE RACK
ADR IN FILE
TFR HEAD AND
SECTOR TO
ADDRESS REG
QGI30
HOLD FOR 2 USEC, THEN SET OFF
FT(3) AND RESET FC.
~
TFR ADR REG
TO 2303
I'f'\
+
QGI30
FT~ ~
HOLD FOR 2 USEC, THEN SET FT(2)
OFF AND RESET FC.
FT-128~
LEAVE ON
STORE HEAD
AND SECTOR
ADR IN FILE
RAISE
CONTROL
TAG
~
T
N
END PROCEDURE
QS020
--FLOW CHART - 2303 Seek
1614
(7/67)
2841 Stage 2 FEMDM (7/67)
1614
u
CD
,a::
..
WRI TE
..;t
00
N
~
C"J
...•
...
\.0
~
,...
!rT-128 AND FC-128 RA ISES "WR ITE GATE.
FT=128 AND Fc ..8 RAISES "ERASE GATE"
CN 5 BIT LATCHED MUST BE ON TO RAISE
()'r WRITE STATUS)
TURN ON
WRITE GATE
& ERASE GATE
QE080
I-
a::
oCt
:I:
u
t
UJ
~
l-
LL
~
...I
a::
......c
0
--'
(-:: WR STATUS)
WR ITE GATE &
ERASE GATE
CTL TO MODULE
HA011
PUT
APPROPR lATE
BYTE IN DR
QP050
X-
•...
WRITE GATE
IS UP
50171
*HB061
BIT RING
IS RESET
BIT RING IS RESET TO ~5 AND ALL
OTHER POSITIONS OFF.
50091
\Q
RISE OF "WRITE CLOCK GATE" IS
DELAYED TO ENSURE TIME FOR FALL OF
ANY PREV I OUS "READ CLOCK GATEII
WRITE CLOCK
GATE COMES
UP
SD091
2.5 MC OSC
DRIVES WRT
TR I G(~"875KC)
S0181
"WRITE TRIGGER" ON GATES WRITING OF
CLOCK PULSES. "WRITE TRIGGER"OFF
GATES WRITING OF DATA PULSES.
BIT RING
IS DRIVEN
"WRITE TRIGGER" ON GATES PHASE X
PULSES. ·WRITE TRIGGER"OFF GATES
PHASE Y PULSES.
50121
l t
TFR DATA
FROM DR TO
FOR
SDI41
FOR IS RESET BY "PHASEX"ANO ABIT O.
I--~I-----""" FOR IS SET WITH NEW DATA BY 6BIT 0
NO BIT O.
.---...........- ------- --...,
I
I
I
~(4)
WR ITE DATA
I
50161
I
I
I
I
~5D
YES
ST (4) IS
SET ON
I
ST (4) ISS ET AT" BIT 0" T I ME • IT
SIGNIFIES THAT THE PREVIOUS BYTE
OF DATA HAS BEEN WRITTEN.
I
RS021
L ______ _
TURN OFF ST
I
(4 )
QPOSO
NO
LAST BYTE
QPOSO
,
YES
YES
WR ITE GATE
TURN OFF
WR ITE GATE
QCOSO
NO
END
WA IT -.uSEC
QC050
{302 . . ~, '\
2311-lj8~5
2321-11.,.5 )
WRITE GATE
OFF AT
MODULE
HA011
t
(*
TURN OFF
ERASE GATE
WR STATUS)
QC050
()'r WR STATUS)
ERASE GATE
OFF AT
MODULE
HA011
N
....
~':2321
ONLY
FLOW CHART - Write
1621
(7/67)
2841 Stage 2 FEMDM (7/67)
1621
u
Q
2303 WR I TE
«:
~
00
N
...
l-
'"
,...
TURN ON
WRITE GATE
& ERASE GATE
o.E080
FT=128 AND FC .. 128 RAISES"WRITE GATE.
FT=128 AND Fc:8 RAISES'ERASE GATE:
CN 5 BIT LATCHED MUST BE ON TO RAISE
PUT
APPROPR lATE
BYTE IN DR
WR ITE GATE '&
ERASE GATE
CTl TO MODULE
HAOll
'It HB061
I-'
>-
~
a::
~
..J
"-
::s
('t'\
0
('t'\
...
~
«
.-
c
...:I"
III
WRITE GATE
IS UP
HB091
WRITE START
COMES ON TO
TFR 1ST BYTE
FR DR TO FOR
S0201
,
~
lL
W
~ !::
u
N
,
N
N
\0
THIS IS DONE TO INSURE THAT THE
FIRST BYTE WRITTEN CONTAINS All
ONES
L..B IT
RING
IS RESET
S0091
BIT RING IS RESET TO A 1 AND ALL
OTHER POSITIONS OFF.
WR ITE CLOCK
GATE COMES
UP
S0091
RISE OF WRITE CLOCK GATE IS
DELAYED TO ENSURE TIME FOR FALL OF
ANY PREVIOUS READ CLOCK GATE.
PHASE ~
DRIVES BIT
RING
HC161
TFR DATA
FROM DR TO
FOR
HC171
FOR IS RESET BY PHASE J AND BIT 0
FOR IS SET WITH NEW DATA BY BIT 0
AND PHASE-2
WRITE DATA
Hco61
ST (4) IS
SET ON
ST (4) IS SET AT DELTA BIT Z TIME.
IT SIGNIFIES THAT THE PREVIOUS BYTE
OF DATA HAS BEEN WRITTEN.
RS021
,
ST (4)
SET OFF
IS
RS021
.J
YES
WRITE GATE
NO
-
END
II
WAIT 8
)lSEC
o.s050
TURN OFF
ERASE GATE
(* WR STATUS)
o.C050
WRITE GATE
OFF AT
MOOUlE
HB061
'--y--I
HARDWARE
WR STATUS,
ERASE GATE
OFF AT
MODULE
HB061
(*
•1 - - - - - - - - '
N
'----.y--I
HI CROPROGRAM
FLOW CHART - 2303 Write
1622
(7/67)
2841 Stage 2 FEMDM (7/67)
1622
I
c
u
I
II)
1
Q
I
"'"
WRITE· AM
ac::
..-:r
co
....
,.~
~
%:
<
~
~
TURN ON
WRITE GATE
&- ERASE GATE
QE 080
"
WITH CN 5 lATCHED ON;
FTal28 AND FC-128 RAISES WRITE GATE
FT-128 AND Fc.8 RAISES ERASE GATE.*
'I:
u
-~
...
t:
~
ac::
:s
~
-'
....
a
+
;.
~
QP 030
."
•
'" ...
......
~
WRITE GATE
& ERASE GATE 'I<
CTl TO MODULE
HA all
N
\0
til
w
r
WR ITE VAR IABLE
AREA OF ONES.
C't\
WRITE GATE
IS UP
SDI71
*HB061
~
REFER TO FLOW CHART,
WRITE, PAGE 621.
NORMAL HOW
WRITE
OPERATIONS
WR ITE 4 BYTES
OF ZEROS
QP 090
r
WRITE I BYTE
OF ONES
QP 080
I--
WITH CN S LATCHED ON:
FTal28 AND FC-t RAISES
ADDRESS I¥.RK.
TURN ON
ADDRESS HARK
QP 080
U"\
WR ITE 2 BYTES
OF ONES.
QP 080 QP 090
ADDRESS HARK
GATE IS UP
50171
t..-.
i
~
WRITE AM
LATCH COMES
UP
50151
TURN OFF
ADDRESS MARK
QP 090
CLOCK PULSES
ARE INHIBITED
FOR BITS 0-4
501.51
WRITE SYNC BYTE
~
WR ITE AM LATCH IS TURNED ON BY
WRITE GATE, ADDRESS MARK, AND
BIT RING O.
WRITE AM IS ANOEO WITH BIT RING
0,1,2.3.4 TO INHIBIT CLOCK PULSES
..
QP 090
r+
WRITE AM
LATCH DROPS
WRITE AM IS TURNED OFF BY BIT
RING 6 AND b.. BIT RING 7
SOISI
WRITE DATA
QP 040,50,60
-
ADDRESS
MARK
,
rV
MICROPROGRAM
,
YES
NO
NORMAL WR ITE
"'"
;. SEE fAGES 736 & 737 FOR TRACK FORMATS
1'"-
"
V
HARDWARE
-
,
~c
.. ERASE GATE" BECOHES "WRITE STATUS" ON 2321
UJ
U
Z
w
ac::
w
w
ac::
....
-....
N
t'\
•
iC
N
~
FLOW CHART - Write Address Mark
1623
(7/67)
2841 Stage 2 FEMDM (7/67)
1623
cc
I
CD
u
I
I
c
I
w
...:t
2303 WRITE AM
~
-
...
&.
...a:::
,....
:!:
,.~
U
:z:
c:(
I>J
~
~ ~
""
0
~ I--
=
"" 0C
N
-
TURN ON
WR GATE &
ERASE GATE
r
QE070
~
...•X
jWITH CNS LATCHED ON: FT=128 AND FC=
\128 RAISES WRITE GATE.FT=128 AND FC=
8 RAISES ERASE GATE
QE080
WRITE S
BYTES OF
ONES
-
\0
>~
-I
La..
N
+
WRITE AND
ERASE GATES
TO MODULE
HB061
WR ITE GATE
I S UP
HB091
WRITE 19
BYTES OF
ONES
NORMAL HOW
WRITE
OPERATIONS
/REFER TO FLOWCHART, 2303 WRITE,
\PAGE 622
QP319
-
)
r
TURN ON
ADDRESS
MARK
/ WITH CNS LATCHED ON: FT=128 AND FC=
\ J RAISES ADDRESS MARK
QP320
11'\
WR ITE 4
BYTES
~DDRESS MARK
GATE IS UP
QP320
HB02]
-
WR ITE AM
LATCH COMES
ON
I
WR ITE AM LATCH IS TURNED ON AT BIT
\ RING 3 TIME
)
HCOSI
TURN OFF
ADDRESS
MARK
~
QP320
GATE 1.667MC
OSC I LLATOR
TO WR lTE DATA
LINE TO 2303
I
THE SERIALIZER OUTPUT IS DEGATED
)
\ FROM THE WRITE DATA LINE TO THE 2303
HCOSI
-,
WRITE:
BYTE OF ONES
BYTE OF ZEROS
SVNCH BYTE
~
WR JTE AM
LATCH TURNS
OFF
{WRITE AM LATCH TURNS OFF AT BIT RING
\ 0 T I ME
HC051
QP320
,
WR ITE DATA
QP330
""
SERIALIZER
OUTPUT DATA
IS GATED TO
THE WR ~ATA
LN TO TH 2303
Hc061
(THE I .667MC OSC I LLATOR IS DEGATED
\ WRITE DATA LINE TO THE 2303
)
,
r
.... tI
NORMAL HOW
WR ITE
OPERATION
~
( REFER TO FLOWCHART, 2303 WR ITE,
\ PAGE 622
MICROPROGRAM
~
..... L"
'-----v-----I
HARDWARE
N
FLOW CHART - 2303 Write Address Mark
1624
(7/67)
2841 Stage 2 FEMDM (7/67)
1624
2
3
4
...---_......._--......,-- -- -- -- ---
5
6
I Write latch is turned on
I a~d turned off by the
micro program.
A
GB141
SVC request latch is
turned on.
GB131
B
Latch 2 is turned on.
GB141
SVC in latch is turned
on.
Signifies that control unit
I is ready to receive a byte
I from the chonne I.
c
SVC out is raised by the
to signify that a
I new byte is ready on the
bus out lin~s.
I channel
Yes
GB061
SORSP notifies the micro
SORSP is turned on.
I program that a new byte
I is ready on bus. SORSP
I meons SVC out response
has been giv~n.
D
Control unit tokes the
current byte from the bus
lout lines and stores the
byte.
Yes
I
GB131
Latch 1 is turned on.
GB151
E
Yes
SVC/ln latch is turned
off.
Yes
Turn off write latch via
IG =0.
No
End
F
G
H
FLOW CHART - Channel Data Transfer - Write
2841 Stage 2 FEMDM (10/67)
1626
o
READ
ee:
"',...
i
,....
.::roo
N
FT""128 AND Fc-64 RA ISES "READ GATE" BOTH
IN THE 2841 OESERIALIZER AND IN THE
SELECTED MDUlE. "READ GATE" BECOMES
• TTENT I ON RESET· IN 2321.
UPDATE
ORIENTATION
QQ010
~
III
+
~
.
READ GATE TO
DESER IALIZER
READ GATE
CTL TO
MODULE
HAOOI
~
~
t-
ee:
~
u
HA09l
:s
0
..J
u..
,
GAP SPACING
N'\
Q
:5
...
a::
~
C
G
X-
•....
VFO IS RESET
:.;::
SD091
QQOIO
SEl READ DATA
,
+r
TURN ON
READ GATE
ONES RESET
LATCH IS SET
~
KES
SD031
QC040
.ESET" lATCH IS SET BY THE FIRST
SEPARATED DATA. PULSE FOLL~ ING THE
VFO SYNC AREA OF ZEROS (CLOCK PULSES).
~
DATA GOOD
"DATA GOOD" I S SET BY THE "QA TA GA P SENSE"
LATCH IS SET ~WHICH OCCURS DURING THE FIRST HALF OF
THE SYNC BYTE (00001110).
50191
:~
~
~
f4------------,
"READ CLOCK GATE" IS SET BY THE FIRST
SERARATEO DATA BIT IN THE SYNC BYTE.
THIS DROPS "BIT RING RESET" AND ALLOWS
PHASE X AND Y GENERATION.
READ CLOCK
GATE IS SET
SDIOI
~(4)
QK020
1
START BIT
RING
YES
K
SOl21
M
THE BIT RING HAS BEEN HELD RESET TO
POSITION AND THE FIRST PHASE X STEPS THE
BIT RING INTO POS. 5, ALLOWING REMAINDER
OF SYNC BYTE TO BE READ INTO FOR.
~
NO
DR=6
QK020
SYNC IS
COMPLETE
-
't
ERROR
STORE DATA
IN FOR AND
TFR TO DR REG
50141
YES
{
lAST 3 "X POSITIONS OF THE SYNC BYTE
AR'E GATED INTO THE FOR REGISTER (110). FOR
I S TRANSFERRED TO OR AT AO TIME. IF GAP &
YNC IS CORRECT DR-6 (00000110).
t
SET ST (4)
OFF
ST (4) IS
SET ON
QK020
RS021
L
~(4)
~E
----
- -- - -- -l
,
I
QL010
I
STORE DATA
IN FOR AND
IrFR TO DR REG
SD141
I
YES
I
I
QW=DR
I
QLOIO
I
I
LAST BYT
QR040
YES
BIT RING IS SYNCED TO THE VFO AND FOR
XFER OCCURS EVERY "BIT RING 0" TIME
UNTI L PROGRAM TURNS OFF READ GATE.
.~
I
ST (4) IS
SET ON
I
RS021
IL... _ _ _
NO
AT BIT RING POSITION 0, THE FOR IS
RESET AND ST (4) IS SET ON. THIS
CONTINUES 'AS LONG AS READ GATE IS UP.
--
r
~~
~
READ Q\TE
TURN OFF
READ GATE
QR040
NO
END
N
'
...
~~------~ r------~/
V
MICROPROGRAM
\~--------~ r-------J1
V
HARDWARE
SEE PAGES 736 & 737
FOR TRACK BIT CONFIGURATION.
FLOW CHART - Read
1631
(7/67)
2841 Stage 2 FEMDM (7/67)
1631
u
c
0<:
•
READ GATE
CTL TO
MODULE
HA 001
~
FT;128 AND Fc:64 RAISES READ GATE BOTH
IN THE 2841 DESERIALIZER AND IN THE
SELECTED 2311 MODULE.
,
00
N
IIX
....
READ GATE TO
DESERIALIZER
~
....-' .....
N
HA 071
...
~
c
c
~
;~
CV\
>
~
CI
ex:
x ILl
U
0<:
ct
""
""
...
X·
VFO IS RESET
S0091
.....
SEL READ DATA
TURN ON
READ GATE
QC 040
•
r
ONES RESET ~ ONES RESET LATCH IS SET BV THE FIRST
SEPARATED DATA PULSE FOLLOWING THE
LATCH IS SET
VFO SYNC AREA OF ZEROS (CLOCK PULSES).
50031
~
,
DATA GOOD
LATCH IS SET
=:
SOl91
..
~
DATA GOOD IS SET BY THE DATA GAP SENSE
WHICH OCCURS DURING THE FIRST HALF OF
THE SYNC BYTE (00001110).
,
--
READ CLOCK GATE IS SET BY THE FIRST
SEPARATED DATA BIT IN THE SYNC BYTE.
THIS DROPS BIT RING RESET AND ALLOWS
PHASE X AND Y GENERATION.
READ CLOCK
GATE IS SET
,
S0101
~~
QK 020
START BIT
RING
, YES
--
50121
NO
DR ..6
QK 020
SYNC IS
COMPLETE
YES
SET ST (4)
OFF
~
,
-
ERROR
STORE DATA
IN FOR AND
TFR TO DR
REG.
SDI41
~
ST4 IS
SET ON
RS 021
--
THE BIT RING HAS BEEN HELD RESET TO 6 5
POSITION AND THE FIRST PHASE X STEPS
THE BIT RING INTO POSITION 5.
,
ST4 IS
SET OFF
THE LAST 3 BITS OF THE SYNC BYTE ARE
GATED INTO THE FOR REGISTER (110). FOR
IS TRANSFERRED TO DR AT TIME .0.0. IF
SYNC IS CORRECT DR-6 (00000110).
AT BIT RING POSITION 0, THE FOR IS
RESET ANO ST (4) IS SET ON. THIS
CONTINUES AS LONG AS READ GATE IS UP.
o
o
o
ct
ILl
IX
ct
ct
ct
o
....
CI
o
o
o
.,
RS 021
~T~
o
ULLI
Z
TSEL READ DATA
Ql 010
YES
WT~
III
z
0
RE~0141
...
ct
0
IX
ILl
IX
ex:
ST4 IS
SET ON
u
RS 021
....0
z
>
II)
0
...
IX
N
>
II)
0
-'
....IX
N
~
READ GATE
TURN OFF
READ GATE
QR 060
o
LLI
II)
YES
0
0
o
STORE DATA
IN FOR AND
TFR TO DR
DR~DW
QL 010
>
Ii)
....
>
NO
....ex:
IX
ex:
0
IX
ILl
N
<:I
ex:
ILl
II)
0
-' IX
ILl
N
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
END
N
.....
FLOW CHART - 2311 Read
1632
(7/67)
2841 Stage 2 FEMDM (7/67)
1632
u
READ ADDRESS MARK
..,:
, ..:t
co
N
...
CV\
CV\
'"
L
~
~
TURN ON
ADDRESS MARKt-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1
QC040
"
FT-I RAISES THE ADDRESS HARK GATE
IN THE 2841 DESERIAlIIER.
...
~
cg
TURN ON
READ GATE
QC04a
...
~.'
FT=128 AND Fc=64 RAISES·READ GATEBOTH IN THE 2841 DESERIALIZER AND
IN THE SELECTED MODULE. ~READ GATEBECOMES "ATTENTION RESET" IN 2321.
RAISING"READ GATE"ALSO FIRES
1600NS SS (*4600NS) WHICH RESETS
DESERIALIZER.
"
HAOOI
IN
50101
00
ONES RESET
FALLS
50031
*SD036
THE VARIABLE AREA ON ONES IS
FOLLOWED BY 4 BYTES OF ZEROS
DURING WHICH ·ZEROS COUNT" PULSES
AREA EMITTED.
THE BINARY
CTR IS
DRIVEN
THE EFFECT OF "ONES RESET" IS
TO RESET THE BINARY COUNTER.
THE EFFECT OF -ZEROS COUNT" IS
TO DRIVE THE BINARY COUNTER.
NO
TURN OFF
AM CONTROL
QJOIO
CLOCK GAP
SENSE DETECTS
AM BYTES
SD061 ''5D066
TO FLAG BYTE
PROCESS ING
QJ010
THIS SETIING OF "READ ClK GATE"
IS UlTIHATElY RESET BY RISE OF
GAP SENSE~ COUNTER NOW
STEPPED BY BIT RING 4.
~DATA
AM GOOD
LATCH IS SETt--------4
SD211
TURN OFF
READ GATE
0 :
DATA GOOD
LATCH IS SET
READ ClK GATE
IS TURNED ON
AGAIN
- -_ _~I
V
A SEQUENCE OF lATCHES (AM 1, AM 2,
AM 3) ARE SET. BY THE RISE AND FAll
OF "CLOCK GAP SENSE "
CONDITIONS WHICH WilL TURN ON "RESTART LATCH" (SD211)
WHICH IN TURN WILL INITIATE A RESTART AT
DATA GAP
SENSE DETECTS
SYNC BYTE. '1'
SD061*SD066
TURN OFF
AM CONTROL
\
READ CLK GATE
COMES UP AT
COUNT 8.
SDIOI
I. "COUNT 14" (NO "DATA GAP SENSE" IN SYNC BYTE)
2. "ONES RESET" WITH" RD CLOCK GATE" OFF (LESS THAN
9 ZEROS IN A ROW) (RESETS BINARY COUNTER ONLY
DOESN'T TURN ON .. RESTARTi .
3. qDEcODE 8-10" AND "ONES RESET P
(LESS THAN 4 BYTES OF ZEROS IN A ROW)
4. "AMI" ON "DATA GAP SENSE" NOT "AM GOOD"
(MISSING'DATA BITS IN AM BYTES)
5. -AMI","CLOCK AND DATA GAP SENSE" (AREA WHERE NO
CLOCK OR DATA BITS HAVE BEEN WRITTEN)
READ CLK GATE IS NOW SET BY THE
FIRST SEPARATED DATA BIT IN THE
SYNC BYTE AS IN READ.
MICRO PROGRAM
BIT RING IS
RESTARTED
SD121
STORE DATA IN
FDR AND TFR
a DR REG.
BIT RING RESET TO 6 5 WAS
INITIATED BY PREVIOUS FALL OF READ
ClK GATE. THE FtRST PHASE X STEPS
BIT RING .TO POSITION 5. "8~BIT
IN SYNC BYTE NOT SET INTO FOR.
SAME HERE AND HEREAFTER AS IN
READ
ST (4) IS
SET ON.
RS021
I' 2321 READ HA IS AN ADDRESS HARK OPERATION. BIT
RING SYNC BYTE IS 00001001. DR WILL BE CHECKED
FOR A "I" (Q.JOIO). BY WILL HAVE BEEN SET TO "I"
ON ~031. READ GATE AND ADDRESS HARK CONTROL
ARE BROUGHT UP ON ~031 ALSO.
,~---~ r----~I
V
HARDWARE
N
*
2321 ONLY
REFER TO PAGES 736 , 737
FOR BETA GAP BIT CONFIGURATION.
FLOW CHART - Read Address Mark
1633
(7/67)
2841 Stage 2 FEMDM (7/67)
1633
2303 READ
a:
~N
FT=128 AND Fc=64 RAISES~READ GATE:
IN THE 2841 DESERIALIZER READ GATE IS
RAISED ONLY IN AN ALL ONES AREA.
N'\
l-
ar::
...
lL
C(
u
a:
~
UJ
...a ............
"-
HB021
0
N
...
~
c
0
0.0.010
...•:E"
VFO IS RESET
-
GAP SPAC ING
-.0
>
0
C(
:z::
READ GATE TO
DESERIALIZER
UPDATE
OR IENTAT ION
o.Q010
..:t
,
SO 091
SEL READ DATA
TURN ON
READ GATE
o.C040
SET SELECT i - G N E OF THE 6 CLOCK A-iASES IS SELECTED
PHASE AND
THAT ~TCHES FILE DATA. TH IS .. SELECTED
HOLD PHASE
PHASE" DRIVES BIT RING AFTER "READ CLOCK '1
HCI41
GATE COMES ON.
-
'-----------------------------'
\D
ZEROS COUNT
DRIVES
BIT RING
:~
THIS OCCURS DURING THE BYTE OF ZEROS
THE SYNCH BYTE
~PRECEEDING
HC 161
.
'------,.---'
:...------------,
,
,
~T
8 BITS LATCH
COMES ON
BIT RING ZERO, DELTA BIT RING ONE
--I~IME OF SYNCH BYTE
HC161
~(4)
~20
READ CLOCK
GATE COMES
ON
HCIOI
YES
I
>-NO_..... ERROR
DR.14
o.K320
SYNC IS
CONPLETE
SELECTED
PHASE DR IVES
BIT RING
~
HC 161
YES
SET BITS"
THROUGH 7
OF SYNCH
BYTE INTO DR
SET ST (4)
OFF
o.K320
HC091
SET ST4
ON
HCIOI
L ... ___ _
o
~
----l
I
ST (4)
o.L30b
I
I
I
I
I
I
I
YES
DW=DR
o.L300
I
~ST~
FDR
ST (4) IS
SET ON
I
I
IL
BIT RING IS SYNCED TO SELECTED PHASE AND
XFER OCCURS EVERY" BIT RING 0" TIME
UNT I L MPROGRAM TURNS OFF READ GATE.
STORE DATA
IN FOR AND
TFR TO DR
REGH,C 171
RS 021
_____
~
..
o.R300
~
YES
READ GATE
TURN OFF
READ GATE
0.0.010
NO
,
N
\
.....
V
MICRO PROGRAM
END
/
\
V
HARDWARE
I
SEE PAG[ 738
FOR TRACK BIT CONFIGlRATION,
FLOW CHART - 2303 Read
1634
(7/67)
2841 Stage 2 FEMDM (7/67)
1634
u
1
I
Q
I
2303 READ ADDRESS MARK
,....
TURN ON
READ GATE
J
J----------------------'""'i\
)
FT=128 AND FC=64 RAISES READ GATE
IN THE 2841 SERDES
QC040
TURN ON
ADDRESS
MARK
1----------+-------------1' FC=8
RA IS ES A DDRESS !'ARK GATE IN TH E
~ 2841 SERDES
QC040
jvFO RESET LINE
CAUSES BIT
RING TO RESET
5D091
o
......
I-
U
...... <1:
SET "SEARCH
AM" LATCH
~I
W
....CO,
FLOW CHART - Microprogram Logic
I.~
I
TYPE
I 2841R
1691
.0\
2
\0
-.0
0\
.
J
(\.)
.-,"
~
RESET
_
CU NOT
BUSY
(AKE)
.::::J
POST CU
END RESET
OP IN
(ME)
•
QS030
QS040
QS061
Q5070
QtOOO
(APE)
_
ADDRESS
REGENERATED
S
(ANE)
ENDING
STATUS
INTO OW
I
-
I
QF040
QF041
(ABE)
RA ISE
STATUS
IN
6
~
7
QFOIO
QF030
SEND BLANK __ (AFE)
SENSE 81TES
TO CHNL
PREPARE TO _ (ANE)
PRESENT FILE
STATUS
4 SENSE
8YTES
O'S IN REG
b
(ALE)
0.80)0
DETERMINE
DEVICE WITH
OUTSTANDING
ATTENTION
(AQE)
DETERMINE
CHNL A OR B
DEVICE SEL
2.
3.
~
([)
~
(i)
QS020
(AHE)
QB060
DETERMINE
FILE STATUS
AND POST
(FGE)
QB052
RESET SIP
[, ATTENT ION
DEl DEVICE
END
cb
QB060
SET DE
SC POSITION
IN DR
QB051
DETERMINE
I S PROPER
DEVICE IS
SELECTED
• (ARE)
END
PROCEDURE
SORSP
SIIC RESP
(AAE)
COM'ND
IS IN OP
REG
XXXOXXXO
SW
CHNL A XXIXXXXX
CHNL B XXXXXXIX
I
0.0100
QGI60
Q8060
BUSY STATUS
POSTED
DE PLACED
IN SW
~
o
GP
COMMAND
REJECT
PLACE
SIP INSW
SEEK IN PROGRESS·
CHNL A XXXIXXXX
(AAE)
CHNL B XXXXXXXI
PLACE DE
IN SW
CHN A XXIXXXXX
CHN B XXXXXXIX
QE030
CONTROL
OPERATION
(AKE)
BLOCKS REPRESENT CLD PAGES
(XXX) IS EX IT SYMBOL ON PAGE
~PROGRAM FUNCTION DESCRIBED IN BOXES.
RESET
READ LATCH
I F ON
COMMAND
REJECT
ERROR
0
POST DEVICE
STATUS
+(AQE)
OB070
QDOIO
QB071
~
LOAD
COMMAND
IN OF REG
~
COMMAND
DECOD E
TVP. RES ER IIEI
RELEASE
r
COMMAND
VALIDITY
CHECK
(ANE)
lqEOIO
STATUS
PRESENTED
~ (APE)
QD040
OD030
(ARE)
o
I~
QGOOO'030'040:
050.060,
061.120 3 }-_ _ _ _ _ _ _ _+ _____.....J
~RESERIIE/RELEASE
130
,
COMMAND NOT
RESERVE 10110100
VALID. SINCE
RELEASE 10010100
FILE MASK
COMMAND PRECEDED
QB060
CHECK
DEVICE
OPERABLE
(lE020
QDI10
QG 1 3 1
(FGE)
QB052
CHECKS FOR ~
(FGE) _
DEVICE END
AND RESERVE
CHNL AlB
c
(ABE)
•(ANE)
QB052
QB051
RECHECK
DEVICE FOR
OUTSTAND ING
ATTN
(AEE)
QE050
SEEK
DECODE
SEEK INSTRUCTIONS TO DEIIICE
TERMINATION OF SEEK OPERATION
CHNL AlB ADDRESSES DEli ICE RESERIIED TO CHNL B/A
RESE~VE ON OTHER CHNL REMOIIED
PACK CHANGE
•
BRANCH
ON OP
6 , 7
(A~
(ARE)
(ASE)
7
(FGE)
QE060
QB060
CHNL A XIXXXXXX
CHNL B XXXXXIXX
(FBE)
FLOW CHART - Dual Channel Microprogram
nS020
DEl I F DE
ISS C OR
PACK CHANGE
DE SC
TYPE
(ARE)
I
CHECK FOR
DE SC
TYPE
(AEE)
j
SUBLOOPS:
([) MAIN LOOP RESERVE/RELEASE COMMAND
([) RELEASE/RESERIIE COMMAND REJECTED WHEN PRECEDED BY FILE MASK COMMAND
(])
QB020
BUSY
STATUS INTO
OW
(AHE)
QB060
(FGE)
o.B052
DETERMINE
IF DEIIICE
END IS SC
OR PC
(AJE)
LEGEND:
I.
.
DR
(AJE)
QB050
(AEE)
SHIFT
(AQ.E)
(Ao.E)
0.80 10
WA IT FOR
CHNL A/8
o.B050
SEL OUT LRAISE OP IN _SEL CU
CHECK DEIIICE
, ADDR IN
' DEIIICE
STATUS
DETERMINE
(AJE)
IF CH A/B
DETERMINE
DEVICE AND
TYPE
(ALE)
(AME)
(ASE)
OB070
PIC INTO
SELECT
DEVICE
INTERFACE
10.8040
ClE061
XXOXXXOX
XOXXXOXX
(ALE)
o.B060
, o.B040
It
DETERMINE
IF TEST 1/0
COMMAND
.~
(ATE)
-
A
(FAE)
RESET
OR
QB020
QB020
PRESENT
DE STATUS
REMOIIE PIC
IN SW
(ATE)
~ Q.S091
RESET
DESELECTI ON
OF ALL
DEVICES
PLACE
RESERVE/
RELEASE IN SW
(FHE)
(ALE)
CU
INI TlATED
SELECTION
~
--
SW REG
RESERVE CHNL A IXXXOXXX
CHNL 8 OXXX1XXX
RELEASE
OXXXOXXX
t 0.5081
RESn
Q.FOOO
'- ____
(ADE)
COHM IN
BY REG
I-FOR DECODE
E
IlDIOO
)'----~-'~
COf1MAND
DECODE
.lO.A.;.:.:K:.:,.E
(ALE)
~--------------------~~--~
SCHEMATIC FLOW DIAGRAM FOR
DUAL CHANNEL MICROPROGRAM
DATI
tV"
11M
2841R
1692
2
s
3
1
6
TIME SCALE OR CYCLE
NO.
SP
SIGNAL NAME
LOGIC
1C
LEVEL
+3,0
I
MACHINE CYCLES
2
{ SELECT! VE
RESET
GENERAL
MANUAL
3
RESET I
C1L4
004
KGOOI
+3,0
4
W REG RESET
C1E4
004
KGOOI
0,+3
5
REG RESET I
cl06
007
KGOOI
+3,0
6
REG RESET 2
Cl06
B08
KGOOI
+3,0
7
RESET 2
cl04
007
KGOOI
+3,0
8
INHIBIT I
CI B5
012
SPIOI
+3,0
9
INHIBIT 2
Cl B5
BIO
SPIOI
+3,0
10
INHIBIT 3
CIF3
B07
SPIOI
+3,0
0
~~M~~~~~
~'
.c;~
~~
OCCURS AT RANDOM
--
-
IME
-- - -
B
-
II
II
c
II
12
13
o
14
15
16
17
18
E
19
20
TIMING CHART
RESET
NORMAL & CE MODE
CE MODE ONLY
RANDOM TIME
TIMING CHAR T - Reset
1
DATE
VIZlllUlllua
~~~--~~--~------~7
~__L-____~T_YP_E__~2_8_4_IR~~0
IB~
1701
5
3
2
6
7
TIME SCALE OR CYCLE
NO.
I
SP
SIGNAL NAME
LOGIC LEVEL
~
MACHINE CYCLES
+3,0
500 NANOSEC PER MACHINE CYCLE
A
A
(125 NANOSEC PER PULSE A, B, C, D)
~~~=~~
2
3
ADDRESS REGISTER
(SAMPLE ADDRESS SHOWN)
4
SALS OUTPUT
(ADDRESSED LOCATION)
514
514
513
8
9
515
516
517
-
514
'\'\
515
516
,\.
514
515
516
ALO OPERATION
-
B
{ ADDRESS STOP ONLY)
6
7
't\
\.\
513
5
515
./
/
TIMED STOP
(STOP KEY, ERROR, ETC)
I NHI BI T I
INHIBIT 2
CD
CD
Q)
10
INHIBIT 3
11
TIMED START (START
KEY, NORMAL RESET)
SPIOI
........
tlBS
012
SPIOI . +3,0
C1BS
BIO
SPIOI
CI F3
B07
"
'\'\
,\.
+3,0
"\'\
SPIOI
+3,0
\.\.
SPIOI
H
12
c
-
/"2841 IS FUNCTIONALLY STOPPED.
""\.
W &. X REGISTER SHOW NEXT ADDRESS (515).
PREVIOUS OPERATION AT ADDRESS 514 HAS BEEN FULLY COMPLETED)
SALS RETAIN INFROMATION FROM 514.
,CA, CB CD LATCHES ARE RESET.
./
13
14
/
15
...-{
"'-
2841 IS FUNCTIONALLY STARTED.
o
""
)
:/
16
17
18
E
19
20
TJ MI NG CHART
START - STOP TIMING
NOTES:
CD
CD
Q)
TIMING CHART - Start - Stop Timing
BLOCK SALS RESET & SET, TURN ON MACHINE STOP INDICATOR.
BLOCK CA, CB, CD LATCH SET; BLOCK W& X REGISTER SET.
BLOCK ALU OUTPUT.
~D_A_T_E+-____-+____-4~~__~ I
~--L---
IB~
TYPE
__-+____
2~41
R
____
~~
1702
7
~O
2
I
2
I
I
3
s
I
It
I
J
6
7
A
A
SAL CONTENTS
C
A
D
B
I(~O~T:
-
GP REG (NORMALLY, GP WILL BE RESET AT START OF SCAN OP)
RECYCLE LATCH (TRANSFER START ADDRESS SWITCH TO X REG)
B
C
A
D
~-
-
I~---
I- -
-'r- - -
t-- - -
t- -
-
-
_ G: : :: +
(C L-6)
-
-
-
G P - - - - - .. - - - - - .... - - -
-
-
-
GP-
C
B
A
D
o
C
B
SCAN
CONTROL
OT L
__________ _~v~OL
ALU OUTPUT
A
D
L / ' GP
CONTROL
~
OPERATION
C
SCAN
..
W/X REG
B
L / ' GP
+
1 SCAN
LV
CONTROL
~--~----~--~
l~tV__ SC_A1'~
U_::_:_]t-:_N__
- - -
-
GP + I
---[2S:.
-t-L
___-tV(ROL. ::N~R:: ~v ::::c SCAN
~-------
GP+Ir.---
\'-----+---+--+---+--+~I
l~O~'i
____
?
(C
1\~-+---+--:1
I
B
L-6)
r--------
GP + 2
r---~-----------X
\'----+--+--+--+~_____fl
r- - -
I
I- - - -
GP+2 - - - - ....
---
--
I
I
c
\~-+---+---+-
V
CD LATCHES
~--~----_+----_r----~--~
o
TROS SCAN
700
[
1
-J
GP - GP + 0 +
XXXXX
x
E
TYPICAL SCAN CONTROL WORD
TlttlNG CHART
T.R.O.S. SCAN
DATE
I
J
1
~-+-----r---~-----;7
~~IL---__~'-Y'-E__J~2-84-I-R--~0
TIMING CHART - T.R.O.S. Scan
II",
1703
3
5
2
6
7
TIME SCALE OR CYCLE
NO.
SIGNAL NAME
SP
LOGIC LEVEL
A
~
I
MACHINE CYCLES
2
SALS OUTPUTS
OEOOI
OE01I
3
CA
DADO 1
OBOOI
4
A BUS GOOD
5
SET A & B REG.
6
A
7
ec, CV, CD DECODE
8
SUM BIT
9
SET ALU OUTPUT
B2G4
004 AL141 +3-0
10
SET SOURCE REG
BIL7
002
&
&.
+3-0
CB DECODES
BAOOI
B2HS
010,
004
RAOOl
RBOOl
oeOOI
DVOOI
00001
B REG
11
&.
RAOII +3-0
CARRY BIT
~~~~~~~
- -
-
B
ALXXX
Ke021 +3-0
-
-
-
c
12
13
o
14
15
16
17
18
E
19
20
TlMI NG CHART
STORAGE CONTROL ALU
DATE
I
r---~----~T-Y-PE--~28~4~I-R--~7
~--~-----+----~------~O
TIMING CHART - Storage Control - ALU
IBM
1704
4
I
I
2
3
,.
1
1
I
5
I
6
7
TIME SCALE OR CYCLE
NO.
I
2
SIGNAL NAME
MOD SELECT
1311 0 PERABLE
SP
LOGIC LEVEL
UR REG SET AT ANY D TI~E,
HA031
HA091
A
OVERALL TIME SCALE IS FUNCTION OF MICROPROGRAM AND FILE DELAYS
~
RISE DEPENDS ON 2311 STATUS
r~
,
( t
( ,I
,,
~
( ~
f !i
r
f
I
~
-
3
4
TRANSFER HEAD RESET
5
TRANSFER CYLINDER
ADDRESS
6
SET SIGN BIT AND
HEAD ADDRESS
7
TRANSFER CYLINDER
DIFFERENCE ADDRESS
8
TRANSFER SEEK START
i CYCLES
i CYCLES
5 CYCLES
5 CYCLES
~
9 CYCLES
~
9
10
B
~
C
A
II
MACHINE CYCLES
12
CN 5 LATCHED
13
FT REG
14
Fe REG
~L5:L5:L5:L5:
0
15
16
"""""
17
18
E
19
20
DATE
I
I
TIMING CHART-2311 Seek
IB~
TIMING CHART
2311 SEEK
I
TYPE
I 2841R
1711
I
7
1
1
I
I
2
3
..
I
I
I
5
6
I
7
TIME SCALE OR CYCLE
SIGNAL NAME
NO.
SP
LOGIC
,
UR REG SET AT ANY 0 TliE
1
MOD SELECT
HB071 QB050
2
2321 OPERABLE
HB091 QB070
A
OVERALL TIME SCALE IS FUNCTION OF MICROPROGRAM AND FILE DELAYS
CLD
PAGE
,
I
RISE DEPENDS ON 2321 STATUS
Ir
f
t
~
~
<
,
I
f
f J
I
10-
3
TRANSFER HEAD ADDR
& SET
A3A2
B12 HB062 QG130
5
TRANSFER HEAD POS
ADDRESS & SET
A3N7 HB051 QGI30
005
6
TRANSFER FINGER
ADDR. & SET
A3N7
004 HBD51 QG130
4
7
TRANSFER SUBCELL
ADDR. & SET
A3N7 HBD51 QG130
D02
8
TRANSFER CELL
AOOR & SET
A3N7
013
9
TRANSFER SEEK
START
A3A2
B10
HB052 QGI3D
HBD61 QGI30
I
j05
I
I
I
10
I
11
I
12
I
13
FT REG
HBDDI QG13D
14
Fe REG
HBOll QG130
B
I
I
II
I
APPROX ~s
DEPENDING ON
WHICH ADDR IS
BE ING SET
...1
I
I
I
1
I
joE
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
i
I
I
I
I
I
3IJ. s
;a.
I
10-
I
I
I
I
I
I
I
1
I
I
I
I
I
I-
C
I
I
10-
1
I
~
0
15
16
I--
17
18
E
19
20
TlMI NG CHART
2321 SEEK
I
DATEl
I
TIMING CHART - 2321 Seek
IBM
TYfIE
I
2841R
1712
1
7
1
2
I
I
2
..
I
3
I
I
5
I
6
7
TIME SCALE OR CYCLE
SIGNAL NAME
NO.
SP
LOGIC lEVEL
*
~I
6.4~SEC
* IS.2
uSEC
BYTE TIME -
A
C2E3
~OISI 0, +3
B02
I
2.5 MC WRITE OSC
,': 875 KC
2
WR ITE ,GATE
3
SERIALIZER RESET SS
C2B4
S0091
004
4
WRITE CLOCK GATE
C2B6
50091
004
5
WR ITE TR IGGER
C2C4
BIO SDISI
6
~
~I ~
400 HANOSEC
I 143 uSEe
0
1600 NS
-
*4600 NS
A
50131
BIT RING
~ ~ ~ hsuU~ ~
I
I
5
6
1 7
10
1 I
1213
I
415
161710
I
I
1 2
I
3 14
I
5 1 6
o
1 I
I
2
1 3
I
4
15
I
""
7
10
...
1 I
1 2 13/ (4 1 5
o I
I
I
6 ( 7 10
I
aI
1[2J3J 4J5161
3
I
I
I
2
I
I
1 I
4
5
6
7
n..n..
(a
I
I
7
a
1 I
... ...
7
50131
BIT RING
S
FOR RESET
B3G6
50111
B07
9
SET FDR
B3G6
50111
009
10
SET ST (4)
BIH3
~S021
B07
II
SER IAL OUTPUT DATA
BITS GATED OUT OF
FOR BY BIT RING
B3G7
50151
004
12
PHASE X
C2B7
SOISI
BI3
13
ALLOW PHASE Y
B3E4
50121
002
14
PHASE Y
C2B7
SOISI
B04
1 5 1 6 1 7
a
1 I
121314151617
0
~
L.sf
I
0
0
0
0
0
0
I
V (31
"-
..
4151617
...
I
I
I
I
I
I
1
I
•
I
I
)
)
'
\
I
I
I
I
0
a
a
o J
I
I
1
L..Q....
DBl FREQ WRITE DATA
C2C6
SOISI +3. 0
BIO
STAYS ON
OF WRITE
.nJLS nIl.,
FO~
0
180
C
11...L
I--
OUT FROM PHASE X
-
rtnrutnm~
LOGIC BLOCK AT 5H GATES "CLOCK BITS"
TO LOGIC BLOCK AT 6G (50271)
LOGIC BLOCK AT 5G GATES "SERIAL
OUTPUT OATA", WHEN PRESENT, TO LOG IC
BLOCK AT 6G. (50271)
LOGIC BLOCK AT 6G MIXES "CLOCK" &
to OATA"
(50271)
IS
-
REMAINDER
--u-Lnn.n..n.J
17
-
SAME AS WRITE TRIGGER
15
16
12
•
•
•
•
~
0
1 2
..
..
I
I
6 1 7
•
•
•
-
I
B
0
-
19
E
20
TIMING CHART
NOTES:
Q
'*
TIMING CHART - Write
WRITE
TURNED ON VIA MICROPROGRAM
2321 REFERENCE
(QEOSO)
I
I
18'4
I
DATE
TYPE
12841R
1721
I
7
2
1
f-'
-=1
2
l>:)
l>:)
5
3
6
7
~
"Ol
~
LOG IC PAGE
SIGNAL NAME
NO
TEST POINT
LVL
LEAD BYTES
I
OF ONES - 65 BYTES
START AM
lEND MIl
BYTE OF ONES
I
JUUl.n.JU\fl..JU1.Il.IlJt
~~
2303 CLOCIC,
2/3 FREQUENCY OSC.
=S
U
W
WRITE GATE
VFO RESET
I
I
WRITE CLOCK GATE
I
DELTA BIT RING
I
~
~
( (
( (
( ~
q
I 5 I 6 I 7 I 0 : ~ 7 I o I 1 I 2 I 3 I 4 I ~ ~ 21 3 I 4 I 5 I 6 I 7 I 0 11 I 2 I 3 I 4 I 5 I 6 I 7 I 0
14:: I 31 4 1 5 16 1 7 lo~ ~ 61 7 1 0 1 1 1 2 13 14 ~ : I 2 13 I 4 1 5 1 6 I 7 1 0 I d 2 I 3 I 4 I 5 1 6 I 7
3
I
if
(~
(
.
sfl..flJU1.Jl.1~
WR ITE PHASE DATA
~~(
(~
~~
WR ITE AM
<
UP FOR EACH BYTE
~-(
RESET FOR
..J
2303 DATA TRANSFERRED
(SET ST 4)
A
,
( ~
BIT RING DRIVE
SET FOR
I
SYNC BYTE = 9 OR 14
B
J 1 12 I
..J
,
I
1 21314 ~~314
1
BIT RING
BIT RINGS RESET
I
BYTE OF ZEROS
L
~~
~r--fl
UP FOJ EACH BYTE
.i
SET
AN~
RESET EACH BYTE
~(
I
( ~ MICROPROGRAM CONTROL
~--
r
n
c
i
<~
~ ~
n
n
I
(i
o
E
TIMING DIAGRAt-I
2303 ATTACHMENT SID WRITE
DATE
TYPE
TIMING CHART - 2302 Attachment
sin Write
IBM
2841R
1 722
2
,.
3
5
1
6
TIME SCALE OR CYCLE
NO.
I
'if
2
SP
SIGNAL NAME
lOGIC lEVEL
400 NANSEC
>"1.143 IlSEC
~
~
J.-
BYTE TIME-6.4}JSEC
oj: 18 .288 ~SEC
~
C2E3 50181
B02
2.5 MC WRITE OSC
875 KC
(2)
WRITE GATE
0, +3
3
4
WRITE CLOCK GATE
C2B6
004 50091
5
WR ITE TR I GGER
c2c4
BIO 50181
6
t:::. BIT RING
50131
I 3 I 4 I 5 I 6
50131
2 \ 3 \ 4 \ 5 \ 6 \ 7
Lfl..JL.fl..Jl. ~ ~ ~ ~ ru-L
I
I
7 10
I
I
2
I
3 I 4
I
5
I
6
I
7 10
I I I 213 1415161710
1112131415161710
I
o \ 1\2\3\4151617
o 1 112131 4 151 6 17
o \ 1\2\3\4\5\6\7
7
BIT RING
8
FOR RESET
B3G6
B07 SDIII
•
•
9
SET FOR
B3G6
009 50111
•
•
SET ST (4)
BIH3
B07 RS021
10
II
SERIAL OUTPUT DATA
B3G7
(BITS GATED OUT OF FOR 004 SDI51
BY BIT RING)
ZEROS
0\1\2\3\4\5\6\7
-
ONES
-
I
I
2
I
3 1 4 1 51 6 \ 7 \0
•
•
0
ONES
ONES
\
o \
I
II
•
•....
•....
\ I
B
0
0
oJ
I
I
I
I 0
0
c
0
12
0)
13
ADDRESS MARK
14
WR ITE AM LATCH
15
B3A6
INHIBIT CLOCK WR DATA B08 50151
16
DBl FREQ WRITE DATA
B3C5
B08 SD151
c2c6
BIO 50181 +3, 0
o
1rfnJ--Lr-trlr- ~ ~
LOGIC BLOCK AT 5H JSDI811
GATES CLOCK BITS TO LOGlt
BLOCK AT 6G
17
LOGIC BLOCK AT 5G.(SOI81) GATES
'-.
SERIAL OUTPUT DATA, WHEN PRESENT, TO
LOGIC BLOCK AT 6G
LOGIC BLOCK AT 6G MIXES CLOCK &
DATA BITS RESULTING IN 2F
18
/
D
0
D
~
J)
11frtrfrf.rf
I,
rr-tr
/
'V"
FIRST ADDRESS HARK
SECOND ADDRESS HARK
INHIBIT CLOCK WRITE DATA
BLOCKS CLOCK BITS AT LOGIC BLOCK
5H DURING BIT RING 0,1,2,3,4
E
19
20
TIMING CHART
WRITE AM
NOTES:
~ TURNED ON VIA MICROPROGRAM - WRITE GATE ON QE080, AM ON QP080
*
TIMING CHART - Write Address Mark
2321 REFERENCE
I
DATE
~--r-----~T-Y-PE--~2~8~47IR--~ 7
~
__~____~____~______~ 2
IBM
1723
3
s
)
2
6
7
TIME SCALE OR CYCLE
NO.
SP
SIGNAL NAME
LOGIC
LEVEL
~~~~~~~r-;....~~,..~r-.~~~~
A
I
MACHINE CYCLES
500 NANDSEC MACHINE CYCLES (125 NANOSEC PER PHASE A,B,C,D)
A
~
2
3
WR ITE LATCH
£t
A SOURCE - IH
C3F3
D04
GBl31
o.
' I
I
I
+3
GBl31
5
6
TRANSFER 1
C3H3
B08
GBI31
7
SVC REQUEST
C3 H3D05
GBI41
8
TRANSFER 2
~~JP
GBI31
9
SVC IN
C3H3
B02
GBI41
SVC OUT
C3J6
B13
GBQ) I
II
SERV I CE REQUEST
C3 fiLl.
B09
GBI51
12
SVC/IN RESET 1
10
--•
GBI51
I
-.
B
;,..
,....
'1
I
~
:~
I
+3. 0
-.
,,
I
I
,
r. .
,r--
•
•
,
~,...
c
,...
I,
•
13
o
I~
15
16
17
18
[
19
20
TI HI NG CHART
I
DATE
t-----t----+-yy-H-4-2.,..,84~I-R- ...... 7
1-_.L.-_ _--f-_ _-'-_ _ _~2
TIMING CHART - Channel Data Trnasfer - Write
11M
1725
5
2
5
3
6
7
TIME SCALE OR CYCLE
NO.
SIGNAL NAME
SP
lOG IC LEVEL
BYTES OF ZEROS
SEE t«>TE 1
~EADING
MuUuL
RAW DATA
C207
D09 50081
READ GATE
B3J4
010 50171
3
VFO RESET
C2B4
D04 50091
-
4
VFO SYNC
C2E6
B02 50091
-
5
VFO GATE
C2E6
B07 50091
+
I
+
GAP } - 2r4~s OF HISSING DATA BLlS
SENSE * 6.~s
1
2
6
7
8
9
C2H6
DATA GAP SENSE
* C2J4JII_ f.-JII 50061
C207
B07 50191
BIT RING SYNC LATCH
SEP DATA
*
DATA GOOD
+
I
+
-
IZZ
2m
BYTE OF
OHfS
6.4~S (*18.28~S
SYNC BYTE (00001110)
~
VL ~LJLhltfuifulfLrL
""---'"
+
C2B6
007 50101
+
tJLl4.
800 NS
*2.28~s
8
r
I
I
+
C2H6
50061
C2J4JI2_ ~12
C2B6
BIO 50191
FIRST DATA BYTE
I
r
R2
ooE--
I
PUlSEWIOTH
APPROX 250N~
-
I
••••••••
I
~
I
I
t
,.
•
J
-'"
c
I
10
H
READ ClK GATE
~
BIT RING
13
PHASE X
C2B7
B13 50181
+
14
ALLOW PHASE Y
B3E4
002
50121
-
PHASE Y
C2B7
B04
50181
+
16
RESET FOR
B3G6
B08
50111
17
SET FDR
B3G6
B09
50111
18
GATE FOR TO DR
B3G6
B07
50111
19
SET STAT 4
63C7
B02
50131
FDR BIT 5
B3G7
DOg
5014,
-
FOR BIT 6
B3G7
DOg
S014~
-
15
20
21.
iRES) TO I POSI 5 I BYI NOTIREAOlclK I GATE!'
I
...
.
5 I 6 I 7 I 0 I 1 1 2 1 3 1 4 1 5 1 6 1 7 1 0 1 1 1 2 II
...
I
I
I
I
I
IRES I TO I NOTJHINGJ BY JNOT I READ! ClKJGA}E
~I
I
J
L
1
1
J
1
1
I
I
I 5
L6
I
1
.
I
..
J
I
+
I
I
I
I
I
!
+
I
+
I
I
NOTES:
1. SEE PAGES 736 &737
FOR GAP BIT CONFIGURATION
2.
PHASE Y PULSES MAY OCCUR
BEFORE ALLOW PHASE Y, BUT
THESE ARE NOT FUNCTIONAL
0
I 7
.1.'I •
-
,', 2321 ONLY
TIMING CHART - Read
'I 5
'IIc
12
,
I
I I 5
...
50131
50132
--'"
I
.
50131
50132
BIT RING
I
• • • • • • • ,. • • ..
••••••••••••
1
I
o
I
I
.
~
I
I
W.
I
I
~
f
I
I
1
...
I J 2 J 3 J 4 1 5 1 6 17 I 0 I 1 1 2 J
~
~
•..
I
I
I
I
I
E
TIMING CHART
DATE
TYPE
18,.,
1731
2841 R
s
3
2
6
7
SHEET 1 OF 3
S IfiNAL "ME
NO
SCOPE POINT
s
LOG IC PAGE
, I
VARIABLE AREA-BYTES OF ONES
4 BYTES OF ZERO
so_0_11_--+_-+~~~
I
I
...--+_ _
c2_E5_B_02_-+__
RAW _
DATA_ _ _ _ _-+-__
2
VFO RESET SS
C2B4D04
. fiR-U.s" ,RWl.QATE
50091
,1.=
:S], ..
.• r .
it
I
.
I
I
I
I I
I'
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4
VFO GATE
5
SEP CLOCK GATE
6
SEP DATA GATE
7
SPEARATED DATA
8
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9
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10
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12
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TIMING CHART - Read Address Mark (Page 1 of 3)
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4 BYTES OF ZEROS
LOGIC PAGE
AM BYTE #1
~
RAW DATA
C2E5B02
50011
2
AM I
B3H6B04
50211
3
AM 2
B3H6B07
50211
4
AM 3
B3H6BI2
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AM GOOD
B3H3011
B
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FROM HERE
I
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DATA GOOD
7
SEPARATED DATA
C2B6Bl0
50191
C2M6J12
50061
"<50066
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C2M6Jll
50061
8
DATA GAP SENSE
~tC2J4Jll
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9
CLOCK GAP SENSE
C2M6J13
"ltC2J4JI3
50061
"<50066
10
ONES RESET
c2M6002
"ltC2J4002
50031
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II
ZEROS COUNT
c2M6B04
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50031
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12
B I NARY COUNTER
13
READ CLOCK G!\TE
C2B6007
50101
PHASE X
C287813
50181
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DATE
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TIMING CHART - Read Address Mark (Page 2 of 3)
IBM
1733
3
I-'
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5
3
2
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6
7
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SHEET 3 OF 3
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SIGNAL NAME
NO
SCOPE POINT
1
RAW DATA
C2E5B02
50011
2
AM I
B3H6B04
50211
3
AM 2
B3H6S07
50211
4
AM 3
B3H6BI2
50211
5
AM GOOO
B3H3011
50211
6
DATA GOOO
7
c286BIO
50191
5 EPARA TEO OA TA
C2M6JI2
'l'tC2J4J12
~~so066
8
DATA GAP SENSE
C2M6Jll
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so061
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9
CLOCK GAP SENSE
C2M6J13
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~"50066
n
E
• 2321 ONLY
TIMING CHART READ AODRESS HARK
~D_A_T~E~____~__~~~__~l
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TIMING CHART-Read Address Mark (Page 3 of 3)
I.~
1733
3
3
2
5
1
6
SHEET 1 OF 2
SIGNAL NME
NO
LOGIC PAGE
TEST PO I NT
ADDRESS' HARK
A
2303 ClOCK
________~~----------ra1------~
2303 DATA
P---------------------~P_------------~s~,------~p----------------------~,pt---------------------------
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TIMING DIAGRAM
DATE
TYPE
TIMING CHART - 2303 Attachment SiD Read AM (Page 1 of 2)
IBM
1734
E
2
3
5
1
6
SHEET 2 OF 2
NO
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SIGNAL NAME
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2303 ATTACHMENT
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READ AM
DATE
TYPE
TIMING CHART - 2303 Attachment SiD Read AM (Page 2 of 2)
IBM
1 734
2
5
3
6
7
TIME SCALE OR CYCLE
NO.
I
SP
SIGNAL NAME
MACHINE CYCLES
LOGIC
LEVEL
A
500 NANOSEC MACHINE CYCLES (125 NANOSEC PER PHASE A.B.C.D)
A
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C3H3D04
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9
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C3H3B02
GB141
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2
I
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SVC OUT
C3J6B'13
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II
SERV ICE REQUEST
c3ti4e09
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C3G3B08
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WHEN IT HAS TAKEN BYTE FROM SVC/IN
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15
16
17
18
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:rl,..INC CHART
CHANNEL DATA TRANSFER-READ
DATI
TYPI
284IR
1735
TIMING CHART - ChalUlel Data Transfer-Read
u
Q
2302 - 2311 TRACK FORMAT
a::
.:;:
00
ZEROS
ZEROS
ZEROS
ZEROS
ZEROS
000 000 0 0 0 00000 000
o0
ZEROS
o0
0 0 0 0 0
~
BIT RING
SYNC AREA
I BYTE
VFD AREA-4 BYTES
LEAD AREA-36 BYTES
0000000 1 1 1 1 1 1 I 1 0
o0
0 1 1
~
CI::
~
u
0
, 1 0 0 1 I 0 0
o0
0 0 0 0
o0
000 000
ZEROS
ZEROS
ZEROS
ZEROS
o0 o0
000 0
o0
LEAD AREA
9 ONES
LEAD BYTE
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N
I
N
0
N
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4 BITS ZEROS
3 BITS ONES
I B IT ZERO
0 1 1 1 1 1 1 1 1 0 o 0 0 1 I I 0
ONES
o
BIT RING
SYNC AREA
I BYTE
4 BITS ZEROS
ONES
ZEROS
ZEROS
3 BITS ONES
1 BIT ZERO
0 0 0 0 000 000 0 0 0 0 0 1 I 1 I 1 1 1 1 00001110
VFO AREA-7 BYTES
6 BYTES ZEROS
ZEROS
ONES
ONES
I 1 1 1 I 1
1 1 I
ZEROS
000000000 0
x
BIT RING
SYNC AREA
1 BYTE
VFO AREA-4 BYTES
...
u
(0
c(
~
LEAD BYTE
'"-
:.:
Z
LEAD AREA
12 ZEROS
..
CI::
0
4 B ITS ZEROS
3 e ITS ONES
1 BIT ZERO
ONES
N
~
o0
0 0 0 000
o
1
B
Y
41
(5
BYTES
18
+ 2) BYTES BYTES
(9 + 2) BYTES
18
BYTES
COUNT FIELD
18
BYTES
2
(9 + 2) BYTES
BYTES
VARIABLE
LENGTH
VAR IABLE
LENGTH
T
E
VARIABLE
LENGTH
(1+2) TO
FULL TRACK
o TO 255.
+2 BYTES
#
(3625 + 2)
18
BYTES MAX.
BYTES
r-----------------~---L----------~~~--~~~--------------~~--~--------~--~--------~--------~
NORIoIAL RECORD
R 0 RECORD
HA or Alpha Gap Bit Configurat ion- 2302
VAR IA BLE AREA
LEAD BYTE
*
ONES
5 BITS MISSING
CLOCK PLUSE
NO CLOCK
11001100111111 I 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ' l ' 11111 I 1111
VAR IABLE AREA=21 +
.49 (KL + DL)
r
ZEROS
ZEROS
ZEROS
ZEROS
ONES
BIT RING SYNC
BYTE
ADDRESS MARK AREA
2 BYTES
VFO AREA-5 BYTES
21 BYTES MIN.
OF GOOD DATA
ONES
ONES
4 B ITS ZEROS
5 BITS HISSING
3 BITS ONES
CLOCK PLUSES
1 BIT ZERO
NO ClOCK
11 I 1 I 1 I 1 0 0 0 0 1 ' 10
r;::J
FOLLOWING A DATA FIELD MAY HAVE A "GLITCH" IN IT DUE TO THE DROPPING OF WRITE
GATE FOLLOWING A REWRITE OF THE DATA FIELD.
IN~D~E_X~~~~
FC
A.M.
HOME
ADDRESS
R 0 COUNT FIELD
18
BYTES
18
(5 + 2) BYTES BYTES
R 0 DATA
FIELD
(9 + 2) BYTES
VARIABLE
LENGTH
(1 + 2) TO
FULL TRACK
B
2
BYTES
B
Y
T
E
COUNT FIELD
VAR IABLE
LENGTH
(9 + 2) BYTES
R 0 RECORD
18
BYTES
o TO 255,
+2 BYTES
VARIABLE
LENGTH
18
BYTES
II
(3625+2)
BYTES MAX.
NORMAL RECORD
Beta Gap Bit Configuration-2311-2302
LEAD AREA-30 BYTES
ZEROS
o
BIT RING
SYNC AREA
1 BYTE
VFO AREA-4 BYTES
ZEROS
ZEROS
4 BITS ZEROS
3 BITS ONES
1 BIT ZERO
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 1 1 1 1 1 1 I 1 0 000 I 1 1 0
ZEROS
LEAD AREA
12 ZEROS
LEAD BYTE
o
0
o0
0 0 0 000
o0
ONES
1 1 0 0 1 1 0 0 1 1 1 I 1
ZEROS
ZEROS
ZEROS
0 0 0 000 000 0 0 0 0 0 00000 0 0 0
ONES
BIT RING
SYNC AREA
1 B TE
o
ONES
4 BITS ZEROS
3 BITS ONES
I BIT ZERO
0 0 0 0 000 1 1 1 I I 1 1 1 00001110
BIT RING
SYNC AREA
I BYTE
VFO AREA-7 BYTES
LEAD AREA
9 ONES
LEAD BYTE
ZEROS
VFO AREA-4 BYTES
ZEROS
ZEROS
1 1 0 0 1 1
ZEROS
6 BYTES ZEROS
ONES
ZEROS
I I 1 I 1 , 000 0 0 0 0 0
ZEROS
o
ZEROS
4 BITS ZEROS
ONES
3 B ITS ONES
1 BIT ZERO
0 0 0 0 0 0 0 000 0 0 000 1 1 I I 1 1 1 I 00001110
# = ON LAST RECORD OF TRACK,
"ONES" ARE WRITTEN AFTER
2nd BURST BYTE UNTIL
INDEX.
HOME
ADDRESS
N
R 0 COUNT FIELD
COUNT FIELD
VARIABLE
LENGTH
VAR IABLE
LENGTH
#
HA and Alpha Gap Bit Configurat ion-2311
~
= CYCLIC CHECK
TIMING CHART - 2302/2311 Track Format
1736
(7/67)
2841 Stage 2 FEMDM (7/67)
1736
u
2321 TRACK FORMAT
.:
r-
i "'
rN
LEAD AREA
36 BYTES
ONES
ZEROS
ZEROS
BIT RING
SYNC AREA
1 BYTE
ADDRESS MARK AREA
2 BYTES
VFO AREA-5 BYTES
ONES
ZEROS
ONES
ONES
5 BITS MISSING 5 BITS MISSING
CLOCK PULSES
CLOCK PULSES
NO CLOCK ~
NO CLOCK ~
1 1 1 1 1 1 I 1 000 0 0 0 0 0 0 000 0 0 0 0 0 0 0 0 0 000 1 111 I 1 I 1 1 1 I 1 1 1 1 1 1 I 1 1 1 1 1 1
LEAD AREA
8 ZEROS
LEAD BYTE
ZEROS
1 100 1 100 0
ZEROS
ZEROS
ZEROS
o0
1M
~
~
~
~
BITS ZEROS
BIT ONE
BITS ZEROS
BIT ONE
u
!i
0 0 1 001
~
0
L>..
~
c.J
~
l-
::E:
N
l-
""
N
:1-
•...
III
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C
ICII
BIT RING
SYNC AREA
1 BYTE
VFO AREA-4 BYTES
ZEROS
4
1
2
I
..
i
4 BITS ZERO
3 BITS ONES
1 BIT ZERO
ONES
0 0 0 0 0 0 0 0 000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 100 0 0 1 1 1 0
ONES
BIT RING
SYNC AREA
1 BYTE
VFO AREA-9 BYTES
LEAD AREA
3 ONES
LEAD BYTE
8 BYTES ZEROS
ZEROS
ONES
ZEROS
11001100 1111111111111111000000000000
ZEROS
ONES
4 BITS ZERO
3 BITS ONES
I BIT ZERO
00000000000111111110000111
INDEX
1
VARIABLE
VARIABLE
~N~H
LENGTH
14
14
14
0 TO 255,
(2000 + 2)
BYTES
(~2) BYTES
BYTES
(9+2) BYTES
BYTES +2 BYTES
BYTES MAX.
r-----------~--~-------L+_~L------------L--~----~~-L----~
R 0 RECORD
NORMAL RECORD
B
COUNT FIELD
Y
41
2
T
BYTES BYTES E
(5+2) BYTES
HA or Alpha Gap Bit Configurat ion- 2321
VAR IABLE AREA
48 BYTES MIN.
OF GOOD DATA
LEAD BYTE
....:
ZEROS
ONES
ONES
ZEROS
ZEROS
BIT RING SYNC
BYTE
ADDRESS HARK AREA
2 BYTES
VFO AREA-5 BYTES
,. BITS ZEROS
3 BITS ONES
1 BIT ZERO
ONES
5 BITS HISS I ...
CLOCK PL SES
NO CLOCK
000000000000000000000000111111111111111
1 1 0 0 1 1 0 0
VAR IABLE AREA=
48+.49 (KL+DL)
;<
LEAD BYTE FOLLOWING A DATA FIELD W\Y HAVE A "GLITCH u IN IT DUE TO THE DROPPING
OF WRITE GATE FOLLOWING A REWRITE OF THE DATA FIELD.
INDEX
1 ......---~
8
COUNT FIELD
B
Y
41
YTES
2
T
BYTES E
14
BYTES
(5+2) BYTES
14
~
(9 + 2)________
BYTES
BYTES
__
-L
__
~
~
Y
2 T
14
B
IWTS
(9+2) BYTES
BYTES
________
__ E ______________
__
~
~
RO RECORD
~
VARIABLE
LENGTH
0 TO 255,
+2 BYTES
~~~~~
__
VARIABLE
LENGTH
(2000 + 2)
BYTES MAX
If
~~~~
NORAAL RECORD
Beta Gap Bit Configurat ion-2321
m.
CYCLIC CHECK
# = ON LAST RECORD OF TRACK,
BYTES OF "ONES" ARE WRITTEN
AFTER 2nd BURST BYTE (ee),
UNTIL INDEX.
0
1
X
X
2
f.+-
3
4
NOT USED
~
5
6
7
---...
X
X
~
L
FLAG BYTE - ALL FILES
o=
NOT ALTERNATE TRACK
I = ALTERNATE TRACK
o=
GOOD TRACK
I = DEFECTIVE TRACK
N
i....--O = NORMAL
I = RECORD OVERFLOW FEAT URE
o=
1ST RECORD • THEN ALT ERNATES.
USED TO DETECT HISSING
ADDRESS MARKS
TIMING CHART-2321 Track Format
1737
(T/67)
2841 Stage 2 FEMDM (7/67)
1737
u
I
I
~
2303 TRACK FORMAT
~
lEAD AREA
65 BYTES
ONES
,....
ADDRESS MARK AREA
4 BYTES - 2/3 FREQUENCY
ONES
ONES
I I I I I
I I I I I
BIT RING SYNC AREA
3 BYTES
ONES
ONES
I I I I I
-'"
00
I-~
ONES
1 I I I I
a:
0
u...
I-
a:
-
Ilol
L
~
'"
I-
CJ
4 BITS ZEROS
I BIT ONE
2 BITS ZEROS
I BIT ONE
1111111100000000 00001001
......
...
~ v
v
~
ZEROS
CO
C"I'\
Z
"'"
:E:
0
"'"
I-
'"
-=-...c - X"
...•
0
r -________~__- -__------------------_\(l~--------------------------------------------~
)l
-
BIT RING
SYNC AREA
~_ _ _ _ _ _ _ _ _ _; -_ _ _ _ _ _ _ _ _ _- T_ _ _ _ _ _ _ _ _ _~~_ _ _~lfr-____r -__________' -__________- r____________r-__2__
B_YT_E_S__~
lEAD AREA 33 BYTES
lEAD BYTE
ONES
ONES
ONES
ONES
ONES
ZEROS
4 BITS ZERS
3 BITS ONES
I BIT ZERO
IIOOIIOCIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOOOOO0000001110
______~________~~________~__~JL
~~
I
J
INDEX
B
Y
R 0 COUNT FIELD
HOME
ADDRESS
65
4
T
BYTES BYTES ~ (5+2) BYTES
36
BYTES
36
BYTES
(9+2) BYTES
R 0 DATA
FIELD
VAR IABlE
lENGTH
(I +2) TO
FUll TRACK
3
10
Y
T
COUNT FIELD
B BVIS E
(9+2) BYTES
Bt-------'
4
11m
KEY FIELD
VAR IABLE
lENGTH
0 TO 255
+2 BYTES
NORMAL RECORD
VAR IABlE
lENGTH
(4892+2)
BYTEX MAX.
36
BYTES
S
R 0 RECORD
(
DATA FIELD
)
#
(
)
HA OR ALPHA GAP BIT CONFIGURATION 2303
ONES
ONES
I I I I I
I I I I I
ONES
I I 0 0 I I 0 0 I I I I I I I I
ONES
ONES
I I I I I
ONES
I I I I I
I11111 I 10000000000001110
~BYT~~~~~N~~E~~l~aDMAYHA~A"G~~~~NF:~~Ero~E~~
~'NG A REWRITE OF ~
~
mm 11m (
RO RECORD
VARIABLE
lENGTH
o TO 255.
+2
BYTES
______
DATA FIELD
VAR IABlE
lENGTH
(4892+2)
BYTES
MAX.
____L-______
)
#
~
36
BYTES
__
~
KEY FIELD
~
~
3
ID
BI---~---'
Y
COUNT FIELD
T
E
S _ _(9+2)
_ _BYTES
__
~
~
~
~
RODATA
FIELD
VAR IABlE
lENGTH
36
(1+2) TO
4
BYTES _
FUll
TRACK
__
_ _ BBYTES
~
1111 ~ ;;;- :":1"'1+ ~Im~
~
(9+2) BYTES
___
~
36
BYTES
(5+2) BYTES
COUNT FIELD
~
~
R
_
'1'1+a "" ~ ~ n~~
HOME
ADDRESS
~
.
4
65
BYTES BYTES
·Icic H~
H
3
B
Y
T
~
H.A.
A.M.
~
r--
r
_
INDEX
.
~
~R~~EAAEA
48 +.49 (KL+DL)
BIT RING SYNC AREA
ADDRESS MARK AREA
3 BYTES
ZEROS
4 BITS ZEROS
3 BITS ONES
I BIT ZERO
ADDRESS MARK AREA 4 BYTES
2/3 FREQUENCY
lEAD AREA
51 BYTES
lEAD BYTE
NORWll RECORD
(
)
BETA GAP BIT CONFIGURATION 2303
m.
CYCll C CHECK
#
o
7
•
X i4- NOT USEDr----
X
•
•
-
X
~
0 = NOT ALTERNATE TRACK
I - ALTERNATE TRACK
""'----0
I
-
= GOOD
=
TRACK
DEFECTIVE TRACK
0 = NORMAL
I - RECORD OVERFLOW FEATURE
o
N
LAST RECORD OF TRACK.
BYTES OF "ONES~ ARE WRITTEN
AFTER 2ND BURST BYTE (CC).
UNTI L INDEX.
FLAG BYTE - All FilES
I
X
= ON
= 1ST
RECORD. THEN ALTERNATES.
USED TO DETECT MISSING
ADDRESS MARKS
TIMING CHART - 2303 Track Format
1738
(7/67)
2841 Stage 2 FEMDM (7/67)
1738
INDEX
I/O Channel Interface and Storage Control, UDCD
2302 Read Address Mark, F. C. 1635
2302/2303 Attachment Circuits, UDCD 1231
2302 - 2311 Track Format, T. C. 1736
Microprogram, Dual Channel, F. C.
Microprogram Logic, F. C. 1691
2303
2303
2303
2303
2303
2303
2303
2303
2303
2303
2303
Attachment SiD - Burst Check Data Flow, I/O O. D.
Attachment S /D Read AM - Part 1, T. C. 1734
Attachment SiD Read AM - Part 2, T. C. 1734
Attachment S/D - Read, I/O O. D. 1423
Attachment SiD - Write, I/O O. D. 1422
Attachment SiD Write, T. C. 1722
Read, F. C. 1634
Seek, F. C. 1614
Track Format, T. C. 1738
Write Address Mark, F. C. 1624
Write, F. C. 1622
2311
2311
2311
2311
2311
Attachment Circuits, UDCD
Read, F. C. 1632
Seek, I/O O. D. 1411
Seek, F. C. 1612
Seek, T.C. 1711
2321
2321
2321
2321
And Optional Attention, UDCD
Seek, F. C. 1613
Seek, ,T. C. 1712
Track Format, T. C. 1737
Read, 2303, F. C. 1634
Read, 2311, F.C. 1632
Read - 2303 Attachment SiD, I/O O. D. 1423
Read, F. C. 1631
Read, T.C. 1731
Read Address Mark, 2302, F. C. 1635
Read AM, 2303 Attachment S/D - Part 1, T. C. 1734
Read AM, 2303 Attachment S/D - Part 2, T. C. 1734
Read Address Mark, F. C. 1633
Read Address Mark - Part 1, T. C. 1733
Read Address Mark - Part 2, T. C. 1733
Read Address Mark - Part 3, T. C. 1733
Read Address Mark - SERDES, I/O O. D. 1433
Read - Channel Data Transfer, F. C. 1636
Read - SERDES, I/O O. D. 1431
Reset, T. C. 1701
1211
1221
Scan, T. R. O. S. , T. C. 1703
Seek, 2303, F. C. 1614
Seek, 2311, F. C. 1612
Seek, 2311, I/O O. D. 1411
Seek, 2311, T.C. 1711
Seek, 2321, F. C. 1613
Seek, 2321, T. C. 1712
Seek Complete and Interrupt, Dual Channel, UDCD 1222
SERDES - Read Address Mark, I/O O. D. 1433
SERDES - Read, I/O O. D. 1431
Serializer/Deserializer, S. L. 1501
Start - Stop Timing, T. C. 1702
Storage Control - AL U, F. C. 1601
Storage Control - AL U, I/O o. D. 1401
Storage Control - AL U, T. C. 1704.
Storage Control and I/O Channel Interface, UDCD 1202
Burst Check Data Flow - 2303 Attachment SiD, I/O O. D.
Data
Data
Data
Data
Dual
Dual
Data
Data
Data
Data
Data
Transfer
Transfer
Transfer
Transfer
Transfer
-
Read, F. C. 1636
Read, I/O O. D. 1436
Read, T. C. 1735
Write, I/O O. D. 1426
Write, To C. 1725
Transfer, Channel - Read, I/O O. D. 1436
Transfer, Channel - Read, T. C. 1735
Transfer, Channel - Write, I/O O. D. 1426
Transfer, Channel - Write, T. C. 1725
Channel Microprogram, F. C. 1692
Channel Seek Complete and Interrupt, UDCD
Error Check.Analysis Diagram
1692
1434
Address Mark, Read, F. C. 1633
Address Mark, Read - Part 1, T. C. 1733
Address Mark, Read - Part 2, T. C. 1733
Address Mark, Read - Part 3, T. C. 1733
Address Mark, Write, F. C. 1623
Address Mark, Write, T. C. 1723
ALU - Storage Control, F. C. 1601
ALU - Storage Control, I/O O. D. 1401
ALU - Storage Control, T. C. 1704
Attachment Circuits, 2302/2303, UDCD 1231
Attachment Circuits, 2311, UDCD 1211
Attention, 2321, UDCD 1221
Channel
Channel
Channel
Channel
Channel
1202
1434
Timing, Start - Stop, T. C. 1702
Track Format, 2302 - 2311, T. C.
Track Format, 2303, T. C. 1738
Track Format, 2321, T. C. 1737
T. R. O. S. Scan, T. C. 1703
1736
Write, 2303, F. C. 1622
Write - 2303 Attachment S/D, I/O O. D. 1422
Write - 2303 Attachment S/D, T. C. 1722
Write, F. C. 1621
Write Address Mark, 2303, F. C. 1624
Write Address Mark, F. C. 1623
Write Address Mark, T. C. 1723
Write/Write AM; I/O O. D. 1421
1222
1301
2841 Stage 2 FEMDM (7/67)
X-I
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