SY33 1042 1_2020_FEMDM_Vol_2_Nov69 1 2020 FEMDM Vol 2 Nov69
SY33-1042-1_2020_FEMDM_Vol_2_Nov69 SY33-1042-1_2020_FEMDM_Vol_2_Nov69
User Manual: SY33-1042-1_2020_FEMDM_Vol_2_Nov69
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Field Engineering
Maintenance Diagrams
Processing Unit
System/360 Model 20
(Machines with serial no. 50,000 and above)
Volume 2
SY33-1042-1
Preface
This publication (Volume 2) and its companion publication (Volume 1,
Form Y33-1024) constitute the Field Engineering Maintenance Diagrams
manual for the IBM 2020 Processing Unit (machines with serial number
50,000 and above) in the IBM System/360 Model 20. Volume 2 contains
operations information (Section 5) and Volume 1 contains information on
the following:
Diagnostic techniques (Section 1)
Error conditions (Section 2)
Data flow (Section 3)
Functional units (Section 4)
Power (Section 6)
Microprograms (Appendix B)
Both volumes are used for maintenance, instruction, and recall.
The material in these volumes supplements the information contained
in the following manuals:
1. Field Engineering Theory of Operation, 2020 Processing Unit,
System/360Model20 (Machines with serial no. 50,000 and above),
Form Y33-1021.
2. Field Engineering Maintenance Manual, 2020 Processing Unit,
System/360 Model 20 (Machines with serial no. 50,000 and above),
Form Y33-1035.
Associated Publications
The follOWing Field Er•.. neering Maintenance Diagrams manuals contain
information on the features which may be installed on the 2020 Processing
Unit:
1. 1403 Printer Models 2, 7, Nl Attachment Feature, System/360 Model 20
(Machines with serial no. 50,000 and above), Form Y33-1018.
2. 2152 Printer-Keyboard Attachment Feature, System/360 Model 20
(Machines with serial no. 50,000 and above), Form Y33-1026.
3. 2203 Printer Attachment Feature, System/360 Model 20 (Machines
with serial no. 50,000 and above), Form Y33-1022.
4. 2520 Card Read Punch Attachment Feature, System/360 Model 20
(Machines with serial no. 50,000 and above), Form Y33-1028.
5. 2560 Multi-Function Card Machine Attachment Feature, 2501 Card
Reader Attachment Feature, 1442 Card Punch ModelS Attachment
Feature, System/360 Model 20 (Machines with serial no. 50,000 and
above), Form Y33-1033.
6. Binary Synchronous Communications Adapter, System/360 Model 20
(Machines with serial no. 50,000 and above), Form Y33-1039.
7. Input/Output Channel Feature, System/360 Model 20 (Machines with
serial no. 50,000 and above), Form Y33-1017.
8. Storage Control Feature, System/360 Model 20 (Machines with serial
no. 50,000 and above), Form Y33-1037.
Information on the serial I/O channel feature is contained in Field
Engineering Theory of Operation, Maintenance Diagrams, Serial 1/0
Channel A ttachment Feature, System/360 Model 20 (Machines with serial
no. 50,000 and above), Form Y33-1040.
The associated Field Engineering Theory of Operations manual for the
features are:
1. 1403 Printer Models 2, 7, Nl Attachment Feature, System/360 Model
20 (Machines with serial no. 50,000 and above), Form Y33-1020.
2. 2152 Printer-Keyboard Attachment Feature, System/360 Model 20
(Machines with serial no. 50,000 and above), Form Y33-1025.
3. 2203 Printer Attachment Feature, System/360 Model 20 (Machines
with serial no. 50,000 and above), Form Y33-1027.
4. 2520 Card Read Punch A ttachment Feature, System/360 Model 20
(Machines with serial no. 50,000 and above), Form Y33-1029.
5. 2560 Multi-Function Card Machine Attachment Feature, 2501 Card
Reader Attachment Feature, 1442 Card Punch Model 5 Attachment
Feature, System/360 Model 20 (Machines with serial no. 50,000 and
above), Form Y33-1034.
6. Binary Synchronous Communications Adapter, System/360 Model 20
(Machines with serial no. 50,000 and above), Form Y33-1038.
7. Input/Output Channel Feature, System/360 Model 20 (Machines with
serial no. 50,000 and above), Form Y33-1019.
8. Storage Control Feature, System/360 Model 20 (Machines with serial
no. 50,000 and above), Form Y33-1036.
Second Edition (November 1969)
This volume is a major revision of, and obsoletes, Y33-1042-O.
Changed diagrams are denoted by the symbol- to the left of the caption, small changes being also indicated
by vertical lines to the left of the changes.
Changes are continually made to the specifications herein; any such changes will be reported in subsequent
revisions or FE Supplements.
A form for readers' comments is provided at the back of this publication. If the form has been removed,
comments may be addressed to IBM Laboratories, Product Publications, Dept 784, 703 Boeblingen/Wuertt,
P.O. Box 210, Germany.
© Copyright International Business Machines Corporation 1969
ii
Contents
Operations
CPU Operations (Part 1)
CPU Operations (Part 2) Microinstructions
Microprogram List Explanation •
5- 1
5- 1
5- 2
Microinstruction Charts
(Flowchart = Part 1; Timing Chart = Part 2)
RI Fornuzts
Load Byte Intennediate (2 parts) .
Insert Byte Left (2 parts) • • .
AND-OR-Exclusive OR Immediate (2 parts).
Add Immediate (2parts) • •
Test under Mask and Skip if Zero and Not Zero (2 parts)
Translate and Branch Short (Direct Addressing) (2 parts)
Translate and Branch Short (Indirect Addressing) (2 parts)
Translate and Branch Long (Direct Addressing) (2 parts) •
Translate and Branch Long (Indirect Addressing) (2 parts)
5555555-
3
4
5
6
7
8
9
5-10
5-11
RDFormats
Load Halfword (Direct Addressing) (2 parts)
Load Halfword (Indirect Addressing) (2 parts)
Store Halfword (Direct Addressing) (2 parts)
Store Halfword (Indirect Addressing) (2 parts)
Branch and Store (Direct Addressing) (2 parts) •
Branch and Store (Indirect Addressing) (2 parts) • . .
Branch on Binary Zero-Minus-Plus, Address Check (Direct Addressing)
(2 parts). • • . • . . • • . • . • . • . • • .
Branch on Binary Zero-Minus-Plus, Address Check (Indirect Addressing)
(2 parts). • • • • • • •
Branch Unconditional (Direct Addressing) (2 parts)
Branch Unconditional (Indirect Addressing) (2 parts)
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
FFFormats
Store Zone Register (2 parts). . • •
Load Zone Register (2 parts)
Move Halfword and Split (DD) (2 parts) .
Move Halfword and Split (DX) (2 parts) •
Shift Left/Right and Move (DD) (2 parts)
Shift Left/Right and Move (DX) (2 parts)
Shift Left/Right and Move (XD) (2 parts)
Shift Left/Right and Move (XX)
Move Halfword (DD) (2 parts)
Move Halfword (DX) (2 parts)
Move Halfword (XD) (2 parts)
Move Halfword (XX, ALC) (2 parts) .
Move Byte (DD) (2 parts). •
Move Byte (DX) (2 parts). . •
Move Byte (XD) (2 parts). • •
Move Byte (XX, ALC) (2 parts) •
Move Numeric/Zone (DD) (2 parts)
Move Numeric/Zone (DX) (2 parts)
Move Numeric/Zone (XD) (2 parts)
==
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
5-36
5-37
5-38
5-39
5-40
Move Numeric/Zone (XX, ALC) (2 parts) • • . . . • . . • . .
Add/Subtract Halfword, Add/Subtract Halfword and Set Carry (DD) (2 parts) •
Add/Subtract Halfword, Add/Subtract Halfword and Set Carry (DX) (2 parts) •
Add/Subtract Halfword, Add/Subtract Halfword and Set Carry {XD) (2 parts) •
Add/Subtract Halfword, Add/Subtract Halfword and Set Carry (xx, ALC)
(2 parts). . . . .
. • • • ••
.
AND-OR-Exclusive OR Byte or Halfword (DD) (2 parts). .
AND-OR-Exclusive OR Byte or Halfword (DX) (2 parts) •
AND-OR-Exclusive OR Byte or Halfword (XD) (2 parts). •
AND-OR-Exclusive OR Byte or Halfword (XX, ALC) (2 parts)
Compare Logical Byte or Halfword (DO) (2 parts). .
Compare Logical Byte or Halfword (OX) (2 parts) .
Compare Logical Byte or Halfword (XD) (2 parts). .
Compare Logical Byte or Halfword (xx, ALC) (2 parts)
Add/Zero and Add Packed Byte (DO) (2 parts). .
Add/Zero and Add Packed Byte (OX) (2 parts) •
Add/Zero and Add Packed Byte (XD) (2 parts). .
Add/Zero and Add Packed Byte (XX, ALC) (2 parts). • . •
Subtract Packed Byte/Perfonn Packed Complement (DO) (2 parts)
Subtract Packed Byte/Perform Packed Complement (OX) (2 parts)
Subtract Packed Byte/perform Packed Complement (XD) (2 parts)
Subtract Packed Byte/Perfonn Packed Complement (XX, ALC) (2 parts)
Set Decimal Sign (DO) (2 parts)
Set Decimal Sign (OX) (2 parts) •
Set Decimal Sign (XD) (2 parts) •
Set Decimal Sign (XX) (2 parts) .
Halt and Display Halfword (2 parts)
5-41
5-42
5-43
5-44
5-45
5-46
5-47
5-48
5-49
5-50
5-51
5-52
5-53
5-54
5-55
5-56
5-57
5-58
5-59
5-60
5-61
5-62
5-63
5-64
5-65
5-66
I/O Instructions
SENS CPU I/O (Direct Addressing) (2 parts)
SENS CPU I/O (Indirect Addressing) (2 parts)
SENS I/O (ALC) (2 parts). . • . .
Control I/O (Direct Addressing) (2 parts)
Control I/O (Indirect Addressing) (2 parts)
Control I/O (ALC) (2 parts) • • •
5-67
5-68
5-69
5-70
5-71
5-72
MANOP Charts
(Flowchart =Part 1; Timing Chart =Part 2)
Storage Display/Scan (2 parts)
Storage Alter/Fill (2 parts) •
Local Store Display (2 parts) •
Local Store Alter (2 parts) .
Initial Control Program Load. • .
Storage Test Run 1 and 3 (Load Runs) (2 parts) •
Storage Test Run 2 and 4 (Compare Runs) (2 parts)
CPU LOG IN (2 parts) •
5-73
5-74
5-75
5-76
5-77
5-78
5-79
5-80
Cycle-Stealing Charts
(Flowchart =Part 1; Timing Chart =Part 2)
CPU Cycle Steal Operation (2 parts). • •
.
•
.
.
•
5-81
Note: The diagrams in this manual have a code number to the ~ht of the caption.
This is a publishing control number and is unrelated to the subject matter.
:c.
Legend
T
1. Logic Diagrams
(Gate) X 00:00
1
Gate
Numerals against gate symbol give page or diagram
number of gating circuit.
Multiple line Transfer
Register, Counter
Input side is denoted by thick line. A partial transfer of
contents is shown by numbered input and/or output lines.
Shift Input
H~}
Singleshot
2. Timing Charts
~
~
(5.,)
TIL
Flip Latch
AC 12:
IT'
(Off/O)
~~ ;h:nra~i~~:~r right corner.
Numerals at beginning and end of the bar identify the
signal(sHalso on the same chart) thot activate and
deactivate this line "Not" with the number
indicates that lack of the signal conditions the line.
,('Er),
(0011)
Input side is denoted by thick line. Circuit multiples shown
(Reset)
Active Stote
~
Oscillator
ALD reference page may
3. Flowcharts
(Time)
(Se')
(Complement) ~P
(0011)
(Re",)
(Off/O)
Flip~Flop
~~t;i:re ~s.denoted by thick line. Shift signal is shown
~
Time Delay
Terminal
Indicates beginning or end of event
Indi eotor lomp
(Dolo)
IT
(Ou'pu')
PH
(Control)
(Clear)
Polarity Hold
Input side is denoted by thick line.
i"-r
G~
Identifies indieatable bus, register,
latch, ect. such as: Indicatable bus
with number of bus lines indicated
Process
Indicates a major function or event. The upper portion
of a divided block specifies where a detailed flowchart
of the process is located.
See Diagram 1-3
AND
Indicatable flip latch
OR
Annotation
Gives descriptive comment or explanatory note.
Exclusive OR
Parity Check data bus
Parity Generate data bus
Negotor (Inverter)
Amplifier
Negative Polarity wedge
M
Y
Adder
XX Abbreviations:
CD = Core Driver
HD = Head Driver
ID = Indicator Driver
lD '" Une Driver
IT '" line Terminator
MD = Magnet Driver
V = Voltage Amplifier
Interface
Denotes interface between two units.
<>
Decision
Indicates a point in a flowchart where a branch to
The upper portion of a
dIVIded block specifies where a detailed flowchart
is located.
a!~rnate paths is possible.
4. General
\ I '~
16
On-Page Connector
Indicotes connection between two parts of the 5Clme
diagram. Arrow leaving symbol points (Iine-of-sight)
to correspondi ng Iy-nvmbered symbol.
18
17
~
I
11
13
12
14
1J
6. Standard Signal Arrangement
Signal grouping
according to
funclionol units
AI ignment of functionol blocks with bosic timing
lS zone selection
No
Name
1--','+,S",,",,,,,,-1,,,,,,,,-,0'''''''''''''''''''''''';''''''-'---jf-LA='°",3'-----1
f---:,+"",S-,::N",w"-,-,P",-,Z,=,o,"""G,,,oC:"'---I KA511
3 lS Current Pl Zone Gote
1--'"4+N""",w/,-,C",,,,,,,,,",-,"Pl~_ _+
S CE lS Select
On-Poge Conneclor
Indicates connection between two porh of the some
diagram. Alphomeric grid coordinate of complemenklry
connector shown beneoth.
8
A3
~o"
"0'0"
\
~
LA412
'To Reg' Select
'From Reg' Select
LA402
LA411
Spore
Entry line
Dato bus out
{low order byte}
Test for packed dedmol format (dgta,sign)
foAAR/modifier
control
5. Special Symbols
Shift Unit
Normoliz:e sign function
-YRegister definition
,
Data expreS5ed In hex
r--,r--r-,.-,--,--!
[:...-~ ~~;r::~~i;:ti:~o(~o~~ds~;;r~v~:b~;~ suppressed)
Spore
16
17
lS Write
LA302/31J
lB
Set Address Check
RA501
19
20
Branch Go
Increment by 1
RA502
RA402
2'
Increment by 2
RA403
22
Decrement by I
23
24
Decrement by 2
Prevent Mod-SAR-Inh Check
RA40'
RA402
KA51l
26
SDR tontrol
Spare
Prevent Storage Use
MA402
f-'=7+.S:=D,,-':.::'oc::I':::h~_ _ _---jf'MAc=40='- - - l
29
30
32
AlU result (includes corry)
Exit l i n - - r - - - - . . . I - - - - ,
Invert
Switch
Entry
linC'--L-====;~=='-J
Performed function (true,
invert, zeras, ones)
KB402
Shift by 2 or 4
RB161
f-3
TDR/shift unit
control
AlU
=-=c=-----t-::=cc---IVi
SDR to TOR
=,+',"';,7-h,"'S"'h;::'ft"'C"',"-tro-'-1--+'='''-'6''2'---1
r-=+'~="'-'=:':::-'--+~"----l
Six correction (dedmal op only)
Exchange of bytes
(croS5 shift)
i JC~b;""
25
34
Test Pocked Byte or Sign
J5
Normalize Sign Active
RA502
comprising:
FOR/invert switch
control
Spore
logical unit comprising shift unit, AlU, and invert switch.
Functions not used within a specified operation ate deleted.
The whole logical unit b controlled by Si9nol$ timed by
cycles (ego FOR true 0-15 during cycle I). For charts
representing more than one different operation, the
different functions are repeated and identified by mnemonics
AlU control
AlU Control Gale
Additional Corry
45
Sel Corry latch
46
Set Condition Code latches
AlU to Inh
48
49
50
AlU to SAR
Data Switch to Op Reg
AA402
I/O bus control
Subfunction, e,g.
Address checking (AC)
Combined signal comprising:
MA401
KB4 J 1
KB402
54
55
SENS Strobe/Control Strabe
Sense Reset/CTRl Strobe
BAI02
56
57
Prevent AlU and SU Check
I/O Bus to FOR
BAIOJ
65
66
67
Carry
Set ALU Test lotch
(CI21
6'
Set CPU checks
Partial use of data
(byte, half byte, or bit)
68
Set Process Check
CCI22
69
Set lSA Check
CC221
70
Set Mod Check
71
72
Set SU Check
Set AlU Check
CCIOI
CCl02
73
Set Bus Check
L
S"OO" p"r".d by "S,,"
;",mo' oo,d ,;,",,,
which cannot be measured. They indicate when the
specified function is executed.
<
L
,
Combined signal comprising: Adder gate
AND gate
OR gate
OE '" no gote active
64
Depending function
(e.g.Modifier can only increment or
decrement data in MAR)
bit 4-7
bitS-II
bit 12-15
bi18-9
bit 10-11
~
FOR invert 0-7 is forced by FOR invert 8-\5. Iinvert and true'= force z:eros
If fOR invert 0-7 is not required, it is
INot invert not true = force one5
suppressed.
I
62
63
Mod
I
:~::~; ~:;5 li~~:r;
:r~nevert
______________
60
MA'
SU
SU
SU
SU
SU
C,mb;", ';,001 oompd.;"" FO' ,," 0-15
58
59
Spore
No shift 0-15
~~::: ~~ ~:~ ~:~
Suppr
Suppr
Suppr
Suppr
Suppr
__
1-5:.:'+O,-,P:..:"'::,,-,:.:0.:..A:=dd:::"::":..:'::::"''-----I KA541
52
I/O Display Address Out
53 Allow Strobe
Halfword
7}
1-~~~~~~~~~~AA~:Jl~' -4\~= = = =;= = = ~ ~=~p=~pr:=~=~;g:=:=; =i;=:=i;~
42
43
47
Spore
left by 21
leit by 4
right by 2
right by 4
No shrft brt 8-15
~~__':0_:..:FD:.:',-._ _ _ _-+-,-M:..::Jl=3_---l
39 Reset FDVRetoin FDRO-7
AA3)3/KMII
40
Invert Switch Control
RB3)I
~
41
r.:;+;:'::;:==.=';",.,.=..,.,..-l
M:Jl'
44 Six Correction 8-11/12-15
D
h'r
0 s r t
0-7 to SU 8-15}
.
8-15 to SU 0-7
Cross shrft
Combined signal comprising: Shift
Shift
Shift
Shift
33 No Shift
RBI62
~ Cam b
r-::+':"-'~'--:--:---::--+~",-----1
i.n~, signa 1 N a sh ~ rt ° ~
r-___-;::Sp:-:-O_,,+=~+5::,"'Pp::.:'~:::.-----+:::RB::.'7:..:'----1-
FD'
Information blocks showing
which data (hex) is on 0
line, and on input or output
of 0 functional unit
'J
TD' 8-15
0-7 to
'0 SU
SU 0-7}N
8-15
,;,"" oompd.;"" TOR
TOR
TOR
r-____~--_+~W~S~D~'~'o~O~p~'=',~------~K'~'~02~~
Exit line
Decision by circuits
Combined signal. The number
above the signal shows which
lS register is addressed.
f-7:'4'-1-'MA='",""",lS'=c-c-co---1 lA702-712
15 Set AlU (I/O Bus) to lS
TOR/Eight Shift
x
Fixed X-Address
sources (e.g. ALU-SOR)
Diog 1-2
o
7
8
9
Inhibit (write)
Indicate5 connection between diagram5 loeated on
separate pages. location of correspondingly-fettered
symbol shown adjacent.
I
_ _ _--l
CC222
~~fo~;:dfr~~~~~::~~~
Sense doto
(read)
Off-Page Connector
H,lfw,,' "';,'"
(e.g. SAR, MAR,
lS reg)
::~~e;I~;e~e~he;~~:~ j~~~r~;~i:n
is finished in the currently
selected lS zone while the next
instruction is olreody initiated
using the new LS zone.
Spore
l _____ •_______ I___~---j
\
_I
;i~~~i~;~;;;~;~I~;~~:~:~
AlD
Reference to (I single AlD page or
to the first of (I group of pages.
:s.
.Abbreviations
AC
ADDR, Addr, ADR
ALC
ALU
ASCII
Aux
BSCA
Address Check
Address
Auto Length Count
Arithmetic and Logic Unit
American Standard Code for Information Interchange
Auxiliary
MANOP
MAR
MFT
Mnem
(Circuit-Controlled) Manual Operation
Modify Address-Register
Machine Function Test
Mnemonic
NSI
Next Sequential Instruction
OE
OpReg
Oprnd
Exclusive OR
Operation
Operation Register
Operand
PL
Pri
PSW
Program Level
Primary
Program Status Word
Rd
Reg
Req
Rst
Read
Register
Request
Reset
SAR
SC
SDR
Stor
SU
Sw
Syst
Storage Address Register
Set Carry
Storage Data Register
Storage
Shift Unit
Switch
System
T
TOR
Time (pulse)
To-Data Register
u-instr
Microinstruction
Wkg
Working
6.CY
Delta Cycle
/..../
Representation of Hexadecimal Numbers
Binary Synchronous Communications Adapter
Op
CC
CE
Chk,Ck
CLD
Col Bin
CPL
CPU
CS
Cust
CY
Condition Code
Customer Engineer
Check
Control Logic Diagram (microprogram list)
Column Binary
Control Program Load
Central Processing Unit
Cycle Steal
Customer
Cycle
Diag
Displ, Dply
DR
Diagnostic, Diagram
Display
Data Register (display customer console)
EBCDIC
Ex
Extended Binary-Coded:Decimal Interchange Code
Execution
FDR
FL
From-Data Register
Flip Latch (Latch)
IAR
ICPL
ICR
Indir
Inh
Insn, Instr
IOC
I/O
I-Recall Addr
(Micro) Instruction Address Register
Initial Control Program Load
Impulse Check Routine
Indirect
Inhibit (switch)
Instruction
Input/Output Channel
Input/Output (Device)
Instruction-Recall Address
LC
LS
Length Count
Local Store
G~uikoo~I~~~~ ~.
_____________________
~~~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _••
~~~=tioo-
Documented by microprogram lists (CLD's)
and by flowcharts. The CLD's are available in
binders COl to C03. Flowcharts are given in
2020 FEMDM, Volume I, Appendix B. Flowcharts for special E-phases of I/O instructions
(XIO, TIO, TlOB, CIO), special parts of
service phases, and special routines (I/O lag
in, CE) are given in the corresponding
"Attachment"-FEMDM. Maintenance programs
are documented in binders labeled TlO,
T30, and T40.
controlled operations
Mode Switch (customer console)
PROCESS
-
INSNSTEP STOR DPLY
STOR ALTER _ _ _....
"'J
[
STOR SCAN - - - -
I
Execution of 43 basic
microinstructions
ADR STOP
DPLY REG
ALTER REG
STOR FILL-
I
Depending upon direct or indirect
operand addressing, 113 varieties of
the 43 basic microinstructions are
possible
l
Additionally, 18 of the microi nstr's
can operate in auto-length-count
mode (ALC)
CPL
semeter
key to CE and
CE mode switc
on
Yes
No
~
,---..1.-
_-,
I The microinstructions are linked to the
(Documented by
Diagrams 5-3 to 5-72)-
I
I.
(Documented by Diagram 5-81)
micro-control-program.
The whole micro-control-program consists
of routines. The routines are designed
to execute following main CPU functions:
I
Control Program Load (CPL). Micro-,
instruction-controlled loading of the
micro-control-program after the first
loader cord has been read into core
storage by MANOP ICPL. In customer
mode, CPL is performed using the
core resident absolute loader in core
storage (Aux storage)
~ System Reset Routine
3
Manual Routines. Micro-controlprogram to display or alter the 8
general registers (customer), PSW,
I-recall address, and machine
language instruction op code, or
to perform instruction step, and
address stop
,
CPU cycle steal operation
I
I
I
I
~
I
I MANOP's I
L -________________________
Storage Display
Storage Seon
Storage AI ter
___ l ___ -,
Storage Fill
Storage Test
ICPU cycle steal (CS) operations con be
requested by the storage control feature,
10C, and BSCA (CS requests). Consider
the operations as circuit controlled service
phases which allow rapid data transfer from
lor to CPU. CS operations are of highest
priority
L_______
----J
I
I
I
I
I
Local Store Display
Loca I Store AI ter
I
I--
CE storage test
switch on
.- Initial Control Program Loadl4-_ _-"(af=te::.r-'C=P'-'U"--'=Lc::O::.:G::...:.I:..:N:.L)_ _ _ _ _~Y...:e..:.s__<
(iCPL)
L
4
Usemeter
key to CE and
CE mode switc
on
I+-Initially performed if: 1. Power on, or
_ _ _ _ _ _ _ _ _---J
2. System reset key, or
3. Load key operated (lCPL, CPL,
customer program load).
CPU LOG IN
~
I
No
I
~---------------------~
I
Load Routine. Micro-control-program""1
which simulates an XIO machine
language instruction to read the first
loader card of the customer program
-i
Instruction Phase (I-Phase) and Execute
Phase (E-Phase) of the Machine
Language Instructions
L
f - - - - - - - - - - - - - - - - - - + 1l 6 I/O Service Phases
I
--.J
I
I - - - - - - - - - - - - - - - - - - . . . - I ? Interrupt Handling
-~
-I 8 Program Error Handling
(Documented by Diagrams 5-73 to 5-80)
L - - - - - - - - - - - - - - - - - - . . . - I 9 Maintenance. I/O log in routines
(detailed and count type log)
~
CPU micro test, CPU loader test.
Worst case paltern test (core storage
adjustments)
Machine function tests (MFT's) and
impulse check routine (iCR). Both
tests run on a mixture of special
mi cro-eontrol-program routines and
machine language instructions
I _. _ _ _ _ _ _ _ _ --lI
L
• Diagram 5-1. CPU Operations (Part I
of 2)
(03705A)
2020 ~50,000 FEMDM Vol 2
(8/69)
-------,
Microinstruction Layout
I
Halfword
High-order Byte
RI Format
Immediate Byte Instructions
Mnemonic
Load Byte Immediate
Insert Byte Left
AND Immediate
OR Immediate
Exclusive OR Immediate
ADD Immediate
Test Under Mask and Skip if Zero
Test Under Mask and Skip if Not Zero
Translate and Branch Short
Translate and Branch Lona
{
{
oI
I
LBI
IBL
ANDI
ORI
EORI
ADDI
TMSZ
TMS
TRBS
TRBL
~ ~c.J
I 2 I3
/0/
4
Condition
Code
Setting
Low-order Byte
5
I6
8 1 91 10
1 7
J" 112 113114115
Updating
OperandAddresses
Auto
Length Count
(ALe)
~
/1/
/2/
~
/3/
~
/4/
~
I
(5 - ••• )
3
~
~ ~e.g.
I
~
Diagram Number
Remarks
5-3)
r------'--
To Reg
5
Immediate Data Byte
~
r----
I
7
I
TRBS} Indirect address if bit 15 of branch
TRBL address is on
I
8
10
,:,
9
"
t t
Direct Indirect
~
RD Format
I
Load/Store
I
Load Halfword
Store
Ha Ifword
.- --_._.-- --- .. _--- ._- -.. -Branch and Store
Branch on Binary Zero
Branch on Binary Minus
Branch on Binary Plus
Branch on Address Check
Branch Unconditional
Branch Type Instructions
I (.!
'"/1
~. ,If.
t'
;~
,.
~i'Jl ..'
.,.!.
,',
LH
5TH
BST
BZ
BM
BP
SAC
B
/5/
~
~
I
/6/
~
/7/
~
I
/8/
0
I
i
12
14
16
IJ:::C [I
To Reg
18
I
:~
010
o~~
~
FF instruction bits ~
~lvo;,
0= DD '
0
"1!oJ ~ O·
1 = DX type
"'IV!; I
0= XD
I =XX
'J.\H4 \'114]JSI
r!i
FF Format
Move Type Instructions
Binary Arithmetic
Instructions
Logical Instructions
P",kod
o.o;.oll~'~o>;~
CPU Stop Instruction
{
{
I{
/8/
/9/
/A/
/B/
/C/
/D/
0
0
1
~
1
0
I
1
I
0
0
1
1
0
0
1
1
0
0
0
0
1
1
I
0
0
1
1
0
Split lAC
Shift
Amount
I f'\ddr
0 +or1
0
1
1
G
0
~
II>
1
-a
0
(3 -"uQ)
..I:
1
I:
U
.~
0
'0
~
1
I:
-a
0
-a
0
U
«
1
0
0
0
1
1
0
1
I
0
0
0
1
0
Operand addressing:
if bits 0 = direct
if bits 1 = indirect
I/o Instructions
~
0
0
0
I
I
I
I
I
I
I
Diagram 5-1. CPU Operations (Part 2 of 2) Microinstructions
(03706)
I
(8/69)
+1
38
34
To Reg
I
I
ALC
-2
I
Conditional
(instruction
bit 6 on)
Fram Reg
I
I
I
+1
I
I
I
I
I
and Ito reg 1=3,
~
"'"
I
,
,
,,
I
27
,
I
28
29
32
36
33
37
40
41
43
44
45
47
48
31
35
39
I
I
I
I
50
54
58
54
58
62
66
-1
Unconditional
'"
I
I
I
I
46
'from reg '=5
I
~
0/'"
25
I
If XX-type
I
I
I
I
I
I
42
instruction
I
I
I
I
I
I
I
51
i 52
59
55
59
63
I
: 55
I
,
I
I
I
II
+1
I
ALC
if indir address
+
67
70
and 'to reg' = 7
'TO REG', 'FROM REG'.
These fields may contain any binary value from 0 to 7. This binary value is used to
select one of eight local storage registers in a local store zone. For FF and I/o
instructions, the selected register is used as data register if the high-order bit in the
'to or from reg' field is off (direct addressing). The selected register is used as
address register for a core storage operand if the high-order bit is on (indirect
addressing),
When the 'to reg' specifies local store register 7 (lAR, instruction address register),
instructions which set data into a local store register as a result of their operation- (load
type instruction) are treated as no operation.
,
,
I
I
I
49
I
I
I
I
Direct Indirect
SHIFT AMOUNT (bits 5, 6, and 7 of SLM, SRM).
The pattern in these bits specifies the number of bits by which the operand halfword has
to be shifted.
Bits 5 6 7
000 Shift by 0 (No shift, only move)
001
Shift by 2
010 Shift by 4 No shift by 6 (bits 6 and 7 on simultaneously)
100 Shift by 8
I 0 1 Shift by 10
1 1 0 Shift by 12
2020 '" 50,000 FEMDM Vol 2
30
I
XX
(ALe)
I
I
15
SPLIT (bits 5 and 6 of MVHS).
During MVHS, a halfword is split. The result of the split is set into two adjacent
registers. The binary value of bits 5 and 6 (0-3) defines the split mode. Details of
split are given in the MVHS flowchart.
+/- 2
+/-1
I
I
Sense I/o
Control I/O
ADDRESS CHECK (AC, bit 7 of FF format instructions).
When the bit is on, the operand addresses (in 'to' or 'from reg' if indirect address) are
checked that they are not outside customer storage area. For halfword instructions (e.g.
MVHS, MVH, AH), the addresses are also checked for halfword boundary (oddress must
be even). An address check stops the CPU by program check (trap request 2).
~
26
I
I
Instruction Type
DX
XD
I
I
(+ if 1.
- if 0)
21
DD
I
I
I
I
19
23
~
24 ,
+2
I
I
I
I
I
20
Dire ct addressing if 0
Indi rect addressing if 1
STR
LR
MVHS
SLM
SRM
MVH
MVB
MVN
MVZ
AH
AHSC
SH
SHSC
AND
OR
EOR
CLC
AP
SP
ZAP
PPC
SDS
HALT
I
I
\
Store Zone Register
Load Zone Register
Move Halfword and Spl it
Sh ift Left and Move
Sh i ft Right and Move
Move Halfword
Move Byte
Move Numeric
Move Zone
Add Halfword
Add Halfword and Set Carry
Subtract Halfword
Subtract Ha Ifword and Set Carry
AN D Byte or Halfword
OR Byte or Halfword
Exclusive OR Byte or Halfword
Compare Logical Byte or Halfword
Add Packed Byte
Subtract Packed Byte
Zero and Add Packed Byte
Perform Packed Complement
Set Decimal Sign
Halt and DisDlav Halfword
I
I
Displacement Address
I
I
oI
+
13
15
17
71
I
I
1
I
I
ALC
+
+
68
56
60
56
60
64
I
I
I
69
72
I
53
57
61
57
61
65
Example of Microprogram list
LU
JK7C
SUTFMEN~CCnRnJNG
MNFM OPFRANO$
_..,..,.
JK746164
JK7' 29FF
JK7A 11M
JK7A 69Rn
--
ftnOJ
l,SnRT
I, SIGNST
FIFLO SfPARATION
•
Jit\66
B~
SH
JK7F MM
JK66
JKR" 76"4
J'014
RP
JKAA
orC;SFL RM
(~ARArrr.R
JKA",
JKAR
rr,
6,6,Cr:
JK
The statement is represented by a formula which defines the detailed CPU functions required to perform
a microinstruction. The detailed CPU functions are
also outlined in the operation flowcharts.
---
Rf,
*=
p~
-
EXAMPLE
AP
r,k
r4F,1
~VH~
symbor-:~J
JJ\R.(j-7/1N~T."-14
"R. Tn
(1,1
Rh
fl, SrNDGT
~R
*: R6 ,DR,Pl
TO JAR.O-7/INST.R-14 TF Rn .LT, fl
Rn
*=
n,n,l
,,
,,
!
IF Flh ,Gr, 0
AC,
+1)
*=
1 •
PAGf
16
-~---'
~Hex Contents of the Addressed
Halfword
X
X
X
X
X
X
X
IBl
ANDI
ORI
EORI
ADDI
TMSZ
TMS
'To reg', X 'aa'
X
TRBS
'To reg', label [X 'a']
Block~
4
A
C
D
The real values of the symbolic block addresses
depend upon system configuration ':Ind mainstorage size.
The references of symbolic and real block addresses ore given in the LINK UST which can
only be printed immediately following the
loading of the microprogram.
Microinstructions
X
X
lH
STH
BZ
BM
BP
BAC
X
X
BST
B
label [.nll, 11
X
X
X
LR
STR
HALT
'To reg', 'from reg'
~
~~~
'To reg'[I],'from reg' [1], n
X
MVHS
'To reg ' , 'from reg' [I]~ ~
X
MVH
'To reg'
X
MVB
or
'To reg' [JJ,'from reg' [1], DEC [,Ad
X
X
MVN
MVZ
AP
ZAP
SP
PPC
SDS
X
X
--+---+---+---+---+---+---+---+---+---+---+---+--~
X
X
BI~ck of !56 bytes
X
X
X
AH
AHSC
SH
SHSC
AND
OR
EOR
CLC
X
SENS
X
X
X
X
A
i
I
~dre""
X
X
I: DS, o~ adv,!nced
count
C
D
.r-t,xt bl ?ok rOl
Byti I
I
A (label l.nl )
X
DC
DDCC'
E (label, label)
B (label)
o (label [.nl )
C 'ABCDEFGH........
X 'aaaa .•••••.••• '
DC
DC
t
Assembler
Instructions
X
X
X
X
X
X
(03707)
2020250,000 FEMDM Vol 2
(8/69)
°
to 3 (Split mode)
label
label
D:.i
DS
DS
DS
n
OH
OQ
OM
EQU
EQU
X 'aaaa'
Lobel [±nl
I/;
/;
~
~
I
,/
/
1-______________
/
I-_____________~
or*
l
Display
;::: Program level
R
= Local Storage Register
SKIP
= Skip
Sl
SR
TOR
UNTIL
= Shift left
= Shift Right
VALID SIGN
+
/()
8 -15
X
*=
'XXXX'
Over the Next
I nstructi on
= Dataflow Register
== lenQth's-count
Reduction Until •••...
::: Decimal Sign
Hex A to F
;::: Binary Add
= Binary Complement Add
= Precedes a Bit Notation
= S,eparator
;::: Connection of Values
= Contains an Address
= Bits 8-15 (Example)
;::: Secondary Defined
Value
== Direction of Data
Transfer I¢::)
;::: Hexadec i rna I
Representation
Summary
The byte addressed by LS reg 2 and
a present previous carry are decimal
added to the byte addressed by LS
reg 4. The addresses are decremented
by 1 and checked.
NOTE: AC specification is valid for
all indirect addresses in an instruction.
°
n=-O through 255, hawever,
the result of label ± n must be
em address inside block
boundary
__
ENTRY
EXTRN
= Customer Consol e
PL
°
g~g ~:~el
1---------f--===--+==-----------i,
_____________--1
X STAl--
I KB412
16 I LSW,lte
\---
ILA302/313
17
18 I Se. Add.." Check
IRA501
19 18..nch Go
I RA502
20 Iincoemen. by 1
I RA402
21 ~~by2
I RA403
22
Dec ..men. by 1
I RA401
23 I Oec ..men. by 2
I RA402
24
I KA511
!
P.. ven' ModHie' Check
---
....
i---
I....-
25
26 I P..ven' S'o"",e U..
27
~R'o
IMA402
Inh
n:i<
IMA401
28 I SOR to Op Reg
"-
I KB102
=
29
30 I SOR to TOR
I KB402
31 lEigh. ShH. Con.~1
IRBI62
32 LShlf. by 2 0' 4
I RB161
33
~
- - f-
I....-
-,;;;;- illtB
n.
I RB162
34 i Tes' Packed Byte
35
~-
0' Sign
RAS02
NonnaU.e Sign Active
I RB171
36 IS'pp....
./
:r7
38 I ALU.o FOR
AA303
39 I ".e' FOR/Retoln FOR 0-7
IInvert Switch Con...1
RB301
True md Invert 0-15 -ttlc 00/
42 I ALU Con.",1 Gate
AA301
C'E
43 I Additional Co"y
AA302
40
41
44 I Six Co'''ctlon 8-11/12-15
,AA402
45 I Se. Co", Latch
46 I Set Condition Code Latch.,
47 IALU to Cnh
IMA401
, 48 IAWtoSAR
KB411
: 49
'0 Op Reg
I KB402
51 I Op Reg to Add"" Su,
KA541
Iso I Data Switch
0,.
, 52 11/0 ObpCoy Add ....
~
II---
53 I Allow Shobe
I S""b. IBA102
54 I SENS
.1
()I,ploy SE :'S ,.mba)
I....-
l....-
55 I Se... Re,e./CTRL Srrobe
:1 56 I P.. ven' ALU and SU Check
157 Ivo Su,
IBA103
'0 FOR
lse
1 59
60
61
I 62
63
164
65
66
67 I Se. ALU
68
Ze~
Latch
ISe. Prac... Check
69 I Se. LSA Check
I
70 I Se. Mod Check
71
ISe. SU Check
ICCl2l
ICC221
ICC10l
ICC102
72 I Se. ALU Check
73
~
ICC122
. Any:check
ISet Su, Check
74 I Set SAR Check
75 I Set Inh Check
Function lignals: .6.Cycle _
ICC101
Cycle _
.
" Do not care " sIgnals:
• Diagram 5-3. Load Byte Intennediate (Part 2 af 2)
ACycie c:::J
Cycle-=:l
(03708A)
---
~
~
I..:i:..
l....~A~ Ii.,;"
- ....
:Cycle 0 ; next
I.....-
202O.:! 50,000 FEMDM Vol 2
(8/69)
. .
Microinstruction La out
The immediate dota byte is
loaded into the high-order
byte of the lS register specified
in the 'to reg' field of the
instruction. The low-order byte
remains unchanged.
I
o
Ope~ation
9
:
B
,s".,I,:,
5
:
5
Instruction
Code
To Reg
10 11
12 13
Immediate Doto
14
15
IBl
1
before execution
LS reg 1
after execution
right-nand byte remains unchanged
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O.1046.xXX
099B
IBL
l,xt9BI
Rl~9B1/RI.8_15
RI
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
b.Cycie c=:J
Cycle -=:J
CORE STORAGE - - + -
Read out and
regenerate micro_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ \ ~tru(;tjon _
,
~--!---,I
: SDR
L~_?J.~_~J"'------1
SU
Suppress
OE
AlU
Invert sw
(lS reg 1)
f-IAR------,
~-·1
:
addr
... u-instr
---r---I
I
I
I
I
I
I
I
rMA,t- --
:
I
+2
1-_______-1
L.!l:~s.!!_o~~r_.
• ___ .t,____ _
.L
I
SAR
~~~t! ~d..d!. j
:
'
by full lines and function$ performed during A cyc:le time are shown by dotted lines.
Aagram ~ Insert ~ Left (~ af 2) ~(03709~
2O~O.OOO~M Val~(8/691
-
AlD
No
Name
I
5,,,, T,ap R,.,e.' lin••
2
lS New Pl Zon. Go"
3
lS C,,,en' Pl Zone Go"
.T4
T5
-
T'
ILAI03
-===
KASII
•
N,w/C,,,,,. Pl
5
CE lS Sel,,'
CC222
,wl,u,,,,n 'Pl. may
T2
7
Flx.d X-Ad......
lA412
'TaRe~.,,'
lA402
"
'F,om R.g' 5.1.,.
lM11
10
lS'a SAR
KB411
L5
lS'a FOR
13
lS'a TOR
==
KB401
----
LA702-712
14 ' MAR'a lS
evo Bu.) '0 lS
=
1:::::::::::=
'5
5•• AlU
16
lSW,;'e
lA302/313
18
Set Add".. Chock
RASOI
I"
Bo-an,h Go
RAS02
20
In,..m.n' bv I
RM02
21
In"emen' bv 2
RM03
122
De,,,,men' bv
17
T1_
T5
T'
Ta
T2
T~
T7
---
---
--
---
IMOI
, RA402
23
De...... nLby 2
24
P"von' Mod-SAR-Inh Ch"k , KASI'
.25
26
Pr.v.n' 5.",... U••
IMA402
27
SOR.a_lnh
IMMOI
28
SOR to Op Reg
I K8102
30
SOR'a TOR
I K8402
31
EIGht Shift Can.al,
IR8162
32
SMI'by2",4
I R8161
33
No Shift
I R8162
----
29
'34
T'
-
~
'0 MAR
II
12
T'
me<
•
8
T3
35
N«maliz. Sian Actlv.
36
Suoo....
,15
RAS02
T." Packed Byt. '" Sign
I RBI71
37
38
_3'1
40
LU to FOR
0.A303
Rere. FOR/Retoin FOR 0-7
IAA303/K8411
Inv'" Switch Cant",1
IR~Ql
Tru. ~-15, Inve;' 0-7 = /0) tru./
41
42
AlU Can.al Gat.
,A3QI
43
Addmanal Carry
AA302
44
Six C...ectian 8-11112-
45
Set Ca"y latch
46
Set Candman Code latche.
47
AlU to Inh
MA401
48
AlU to SAR
K8411
C
AA402
4"
50
Data Swlt,h to ()P Reo
51
()P Re" to Ad......
52
VO
53
Allow S.abe
55
Senre 'e.e./CTRl St",b.
56
O..v.n' LU
57
VO
K8402
au.
KAS41
Or--
E---
Di.play Add"" Out
SENS
IS.",,,
I SU Ch.ck
'I.play
BAI02
SE" """e)
BA103
-
-
I
B" 'aFOR
58
_02
60
!
61
"
62
63
64
65
~
CCI21
67
Set AlU Teot lateh
6B
Set 0'00'" Cheek
CCI22
6"
Set lSA Chock
CC221
70
Set Mod Cheek
CCIOI
71
Set SU Chock
CCI02
72
Sat AW Check
73
Set Bu. Check
74
Set SAO Check
75 Set Inh Check
Function signals: .6.Cycle
~
\
I
I
>
An:: ch"k
I
CCIOI
)
rzza
Cycle _
"Do not care" SIgnals: ACycle c:J
• Oiagram 5-4. Insert Byte Left (Part 2 of 2)
(03709A)
Cycle-=:J
-
2020 .<: 50,000 FEMDM Vol 2
~
ATa
(8/69)
-...
--
~
..ii
Cyde I of next, ,
Ta
Microinstruction Layout
ANDl
The immediate data byte is
ANDed, ORed, or exclusive
ORed with the low-orcler byte
in the 'to reg'. The result is
set into the 'to reg'.
.Instruction
F
:
0
0
EORI
ORI
I
3
4
I
I
2
5
6
7
To Reg
Op Code
i
j
2
0
I
0
8
9
10
II
12
13
14
ANDI
15
Immediote Dota
AND"
ORI
LS reg 1
For ANDI the high-order
byte is set to zero. The highorder byte remains unchanged
for ORI and EaRl.
before execution
EORI
:
•
LS reg 1
after execution
ORI
EORI
I
AND
rNST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O_1046_XXX
!
lIFO
19FO
ZIFO
ANDl
ORr
EORl
1,X'F()t
Rl*=Rl.A.IOOF()f
Rl*=Rl,OR.IOOFO'
Rh=Rl.OE.100FO'
C
I
1.x.tFOI
l,X'FO'
f--'-="---!
RI
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
.9
Set LSA Check
I CC221
70
.21
S.
I CCIOJ
I Ch,
Set SU Check
72
Set AW Check
73
Set Bu, Check
74
Set SAR Check
75
Set loh Check
Function 5lgnals: aCycle
~
CCI02
Aoy' :heck
CC101
m
Cycle _
"00 not care" Signals: .>lCycle 0
Cy<:le-=:t
• Diagram 5-5. AND-OR-Exclusive OR Immediate (Part 2 of 2)
(03710A)
......
......
~
...iii..
--
' TB...ii
---
2020 ~ 50,000 FEMDM Vol 2
-....---
(8/69)
Cy",'O at o"t
I
T4
T1
T4
._-----------_._------
Instruction
The immediate data byte is
added to the halfword in the
'to reg'. The result is set into
the 'to reg'.
LS ,og 1
I
IOperftion
1 : I
~
8 bit of the instruction is zero,
therefore set to zero
Instruction
F
Microinstruction layout
JO
Op Code
12:212:21
before execution
~.. Add
To Reg
11
12
13
14
15
ADDI
Immediate Do to
2
~7:h~rde~b;eteone"-,-,,l'l!!,o,--,!!!ho'--r=?--:o-r;,..t.-;:"'"1
LSregl
---_.- ._--
I
8 bit of the instruction is one,
L
for subtraction the immediate
E
~
~I"i2",=:,e,2dlpe,2,":=2~1
before execution
I Ope{otio~
-
FE
-----..
,,-;-,~,--.....;~,---,,-
Add_
data byte must be in two's
complement
(hi9h~order
bit on).
If so, the immediate data byte is
extended to a halfward by highorder ones.
LS 'og 1 1 2 : 2
after execution
f
3 :
3
LS' reg 1
[112:::::1:2
after execution
jfQ::::::11JI
l
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O_I046_~XX
2911
ADDI
ADDI
l,X'IJ1
1,_1
RI*=RI+lOOll' '
Rl*=Rl+lFFFF'
No condition code is set
No carry will be stored
Overflow condition is not indicoted
RI
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:·
.6.Cycle c::::J
Cycle -=:J
CORE S,TORAGE - - - .
Reed out and
regenerate microinstruction
-
-1---
-
-
-
-
-
-
-
I
1
Add true"'.Add
Add complement"" Subtract
SU
ALU
Invertsw
(LS cog 1)
For subtroct, the result is in
two's complement when the
immediate data byte is greater
than the value in 'to reg' (before op)
Increased by 1
if corry out of
low-order byte
1
I
r--t--
I
Lu.:!n.s!!:..~~
I
I
+2
I
,... __1 __ ,
I SAR
I
I
0
L~!!!.$tt.~~J
and functions performed during .6. cycle time are shown by dotted lines.
Functions performed during
I
Diagram 5-6. Add Immediate (Pa.rt 1 of 2)
4 = 0100
Add -5 = 1011
1111 =-1
I
I MAR
I
e.g. 4-5=-1
(03711)
2020 ~ 50,000 FEMDM Vol 2
(8/69)
-
-
-
-
-- -
- - -- -
- -
-
-
-
-
- -
-
-
- - - - -
- - - - -
-
- -
-
-
-
-
- -
- -
--- -
AlO
Name
INo
To
I
· Sen.e T,ap Req, ••t Une.
T4
T6
i....-
ILAI03
2 · lS New Pl Zon. Gate
lor-
KA511
lS C,,,.nt Pl Zone Gate
3
4
New/C,,,ent Pl
5
CE lS Select
N., '/c"".nt
, may dH.,
I CC222
6
7 : Fixed X-Add,e ..
lA412
8
'To Re,' Select
9
'F,om Reg' Select
lA411
LS to SAR
KB411
110
I...-
IlA402
'"'"'"""
· LS to MAR
112
LS to FOR
113
LS to TOR
II.
MAR to lS
lA702-712
LS W,lte
0....-
>---
I---
lis I Set AW. (VO B"l to lS
116
---
~
KB401
....
~
I...-
l...-
LA302I313
11l
Ch~k
118
Set Add,...
119
a..,
120
In..ement bv
121
I.aoment bv 2
RAS01
,G,
RAS02
..""
I RA403
I 22
o."ement bv
I 23
o...ement bv 2
I RA402
I 2.
P..vent Mod-SAR-Inh Check
I KASll
Wli
125
126
P,event St..._
127
SOR to Inh
U.e
IMA401
I 28
SOR to 00 Rea
I K8102
SOR to TOR
I KB402
Elaht Shift Con"ol
I RBI62
I MA402
0-15
i.o...-
129
I 30
31
Shift by 2 ....
I RBI61
33
No Shift
I RBI62
34
Te.t Packed Bvte ... Sian
35
N...mallze Sign Active
36
Su.......
132
,
10.......
---
15
Not.,
RA502
I
, pooltlve: no '"ppre ,If nega.,.
,
I RBI71
;;:th'i~~'hl
\ on!., SU;~;;n~~11
; to, lion, '~F~
37
.3a l-J&!.fPR
""03
39
lIe.. t FO!VRelaln FOR 0-7
I AA303/KB411
40
Inv..t Switch Cont",1
I R8301
T",. 0-15
41
42 · All I Con"ol Ga••
'A301
AA302
43
Addltlonol Corry
44
Six Correction 8- 1112-
45
Set Cony latch
..
47
AA402
Set Condition Cad. Lntc ....
:MA401
AI Ito Inh
I K8411
J to SAR
48
49
. 50
Dota Switch to 00 Reo
I KB402
151
()P Re, to Add,...
au.
KAS.I
~
(----
I 52 VO Ol.olav Add.... o,t
I 53 Allow St,,,,,"
154
SENS
I S5
Sen.. Re ..t/CTRl St,obe
156 I p,
1St,,,,,"
.Allt
«II n
(I);,olay SEI 'S .t",bel
BAI02
l....-
0....-
&AlO3
I 57 VO Bu, to FOR
158
.-59
,60
'61
62
_63
,64
165
~
l£ · Set AlU Te,t latch
Set P
o.T8~ ~epa
- ....
At, check
173 I Set Bu, Check
I 7. I Set SAR Ch~k
7S Set Inh Check
function IIgnals: ACyel. IfOJ
'--
CCIOI
Cycle _
~
~
~
-
IDo not care " Signals: aCyele
• Diagram 5-6. Add Immediate {Part 2 of 2}
CJ
{03711A}
0....-
Cycle-=:J
2020 ~ 50,000 FEMDM Vol 2
{8/69}
",ve; u,
~"
ayte
i,atiVe
Cyd ,Oofnex
,
,
° :
lA'
1
1
address
of the TMSZ instruction
°:
,-.::o"'P:J.~,::.:at:.::;a::.a-,==3~:~F=1
Instruction
The immediate data byte is used
as a mask. Turned on bits in the
mask test the corresponding bits
in the low-order byte of the 'to
reg' for being off.
lS "g I
LS leg lemain
The next sequential microinstruction is skipped:
Example 2: Successful TMSZ
Example 1: Unsuccessful TMSZ
2
",,,hoag.d
F
:
CI.m.~
9
Op~,atlaa
:~
~3
I
F
I
I
Att
CI.m.d
IAR
-LI_O'-L:'....::..._lt~O-~O-~1-3-~3!""""
,
:
,
Result IS not zero
Continue with NSI,
Address 0104.
(Example not shown in the
Flowchart)
IAR
5
TMSZ
10 11
12 13
14
Immediate Data (Mask)
~l
-~:o
1
TMSZ
TMS
TMS
1
C
15
AND
C ° 1°
L...:0'-L.:-,-I
2. If TMS, when any tested bit
is on.
:
~
..--~~~to "CO~.j.
I. If TMSZ, when q!! tested bits
are off.
3
Microinstruction La out
1 3 : F1
.j.
0I
Result is zero, i.e. all bits selected
by the mask are zero.
Skip ov('r the NSI, continue with
address 0106.
INST
MNEM
OPERANDS
STATEME:NTS ACCORDING TO STANDARD GEB O_1046_XXX
313F
393F
TMSZ
TMS
1,X'3F'
1,X13FI
Skip if RI,A,'003F'=O
Skip if RI,A,'003F',NE,O
1----'-'--''''--
"
[1~O~==~1=IC=o~::J6==~I~f:----------~----Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
t..Cycle~
Cycle
Read out and
regenerate micro~truction _
CORE STORAGE -
TMSZ Wo""':'-'".-!:'.J
TMS
,
(No action)
'No
AlU
ALU zero
Suppress
SU
/003F/ := 0000 0000 0011 JIll
AND
f----..I-:...t- -
(Not used)
AND
/35CO/:= 0011 0101 1100 0000
result := 0000 0000 0000 0000
Invert sw
,..-------liAR
:
,,:-iAR - - --~,,
, u-instr addr •
----r ---"
~ --(Not used)
,.. ___ t. __ _
: MAR
l ~-~n!.t':.. ~~r_:
+2
r-SAR ---:
L!:!:!~S~2~d.!:_:
Functions performed during cycle time are shown by fuJI lines ond functions performed during a cycle time are shown by dotted lines •
~iagram 5:::2.
Test un..d.er Mask 0119 Skip if Z.IlI.O and NaLZero IPart.l of 21
.....LQ3712A) _
202O~,OOO FE~
Vol 2 ~/69)
-=:J
ALD
Nom.
INo
I
Sen.e T,op Reque" Uno,'
LAI03
2
LS New PL Zone Gote
KASII
3
LS Current PL Zone Got.
4
New/Current PL
5
CE LS Sel.ct
7
Flx.d X-Add,...
'To Reo' Select
9
'F,om Reo' Select
LS to SAR
LS to MAR
I.
LS to TOR
14
MAR to LS
IS
Set ALU
16
LSWdte
TB
T3
18
20
T4
Tl
'-=:::
.."
w"",
""""'-
~
"'II
I---
K8411
""""""""
K8401
-
...---:1
LA702-712
-
eve Su.) to LS
r--
-
~302/'"
c......
Set ,\dd,...
T2
T8
--
17
,. ,,,
T(,
T4
LA402
LStoFDR
13
T7
I CC222
8
10
,2
Cyd.O
I.
.moy ,.'t.,
•
III
-.
I---
'=
--
-
,,----',.
-'---'
,...<01
,G,
TMSZ
TMS
--
if ALU
latch
If ALU teot lotch of
(see
I no 67)
-
I...""
In«ement bv
W02
121
Inaement bv 2
122
DecMm.nt bv
i 23
DecMment bv 2
I RA402
I ••
P~vent
I 8
SDR to
1.6
e. Re.
-
I KB102
29
,30
SDR to TOR
K8402
31
Hoht ShUt Con"ol
.BI6.
32
Sh;ft by 2 .. 4
R0161
33
No Shift
RBI62
34
Te" Poc.ed 1M. . . SI.n
RAS02
Un'~Aned
0-15 'to 0-1'
-
,
,
0,
3S
NO------1
I SOR
r
SDR
i---~-----j
I
L!..1J.~!.J
L6.!oJ.. I_U
Not intern SU bit 15 .. TRBS direct addressing
{End op cycle I}
r-----,
I
I
I
Suppress I
SU
Suppress
I
I
I
1
A
I
I
I
AlU
r-----.L----- l
OE
i----*-+-- - --,
OE
I
I FOR 8-11 to intem SU 4-lJ
I for parity correction
I
I
I
L----T----...J
I
I
Invert
A
I
5W
(LS reg I)
r- ---,
liAR
Lu+uJ
1
1
1
1
1
I
1
I
I
I
I
I
I
I
I
I
I
r - .1_-,
.---1.--,
I
L.8_0..1.~..!J
SAR
I
I
rSA'I.- -,
I SAR
I
LL9J.Ll...J
(Intermedioteaddr)
T
SARIS
Functions
during cycle time are shown by full lines and functions performed during Il. cycle time are mown by dotted lines.
Diagram 5-8. Translate and Branch Short (Direct Addressing) (Part 1 of 2)
(03713)
Cycle if single micrainstr swan
2020 250,000 FEMDM Vol 2 ) (8/69)
:
I
L ~ ~ ~ _Aj
(Branch addr)
INo
AlD
Name
1 I Sen.. Trap ReQue.' ll;".
LAl03
2 I lS New Pl Zane Gate
KA511
~T.
aead
T7
.......
-=-
, dIffer
I New/Cu"ent Pl
5 I CE lS Sel."
I CC222
•
7 I FIxed X-Addre..
•
~
~
lA412
~
L..L-
---
--=
...m
8 I 'To Re.' Select
I 'From Reg' Select
110
---
18
3 I lS Current Pl Zane Ga'e,
4
--'-
i---
IlA411
.......
.......
f----
111 IlS.a MAR
12 I LS aFDR
i---
~
KB411
HaSAR
KB401
i---
I--
~
10.-
113 , lS.o TOR
lli IMAR.o lS
W02-712
f----
lIS I Se. AlU (VO Bu.) 10 lS
~
Lls WrIte
---
I----
LA302i313
117
118 ! Set Addr... o-k
IRASOI
I. I Branch G,
---
~
IRAS02
120
,I
121
1.00ement by 2
RA403
I"
Do
RMOI
I RA402
n' I
123
o.c~ment
1.24
P..".n' Mod-SAR-Inh Check
bv 0
RA402
I KA511
125
12.
Pr.ven. Stor.,.. U..
MA402
127
SDR to Inh
MA401
lOR
SOR 10 00 Rea
K8102
---
12.
SDR toTOR
KB402
Eight SWt Control
R8162
132
Shift by 2 or 4
R8161
133
No ShIft
130
31
.M..
d.fin.d
-
I-
0-l5 0-f5
~
I-- - 1 - - - f--
=
'DifB-t iiOSlTl!=
---
=
,No.hll., If SAR 15 ,.ro."hll tif no
"
I R8162
Te.t Packed Byte or SIgn
0-15 ,0-15
0"15
RAS02
135
Normalize SI. . Active
i36
50......
I RBI71
38
AlU t. FOR
IAA303
39
_ t FOR/Retain FOR 0-7
I AA303/KB411
40
Invert Switch Contr.1
18301
42
AlU Control Gate
AA301
43
Addltlonol Corr,
AA302
44
SIx Correction 8-11112-15
45
Set Corrv latch
46
Set Condition Cod. lotch..
47
ALII to Inh
, 37
=mRi
TNe '0-15,
Inv~rt 8-11
" Ne 0
'N~/
Tru, 0-15, In'~rt8-15
Itrue 00/
41
..
OE
OE
AA402
IMA40I
"'== I (Cycl.
b".""",
I KB411
SAR
~pendlng
f Slngl.
• ..,ltel .:on)
,
4.
Iso I Oat. Switch
'0 Clp Reg
I KB402
I Clp Ro. to Addreu Suo
152
r-----
t--
KA541
I/O 01...1_ AddM.. Out
I Stmba
154
SENS
Iss
Se",e ....t/C1T (8/69)
SAR
:
~_!..,...!_!'-J
IBranchaddr)
c:::::J
-=:J
ALO
Name
INo
Req~.'
1
Sen.e T,a.
2
LS New PL Zone Ga'e
3
LS Curren' PL Zone Ga'e
4
New/Cu"en' .L
5
CE LS Sele"
Une.
I LAl03
KASll
•
,
,
Cyc ,0
T8
17
Ne.'/,",~n'
L', mav
T4
......
I
T5
T6
17
T5
T8
T8
T6
111'--==
, 'fe,
--
T2
......
13
7
Fixed X-Add....
'412
8
'To Reg' Sol".
'-402
9
'F,om Rea' Sol""
10
LS '0 SAR
--
"oMAR
ito FOR
r--
"'==
- -
t--KB401
13
LS '0 TOR
MAR.o LS
'5
So. ALU
16
LS WoI'e
LA302/313
18
Se, Add.... ChKk
RAS01
19
Boonch Go
IAS02
LA702-712
evo Bud to LS
r---
I--
21
r--
r--
--
-==
17
2.
r---
t---
'-41
14
~
,--..!..-
KB411
11
TS
T6
17
T8
17
CC222
6
12
T4
r--
I--
---
---
--
~
~
......
----
-
IM02
IRM03
In""...n' by 2
IRA""
" '"
I RA402
23
Oo,,_en' bv 2
24
P,even' Mod~';'lnh Cheok
(ASI
26
".ven' S''''age U..
MA402
27
SOR
'0 Inh
MM01
2.
SOR to O. Reo
K8102
30
SOR 'oTOR
KB402
31
Elgh. Shift Con"ol
RB162
32
ShU. bv 2 '"
RB16'
33
No Shift
RB162
34
To., P",ked &V'e'" SI.n
RAS02
25
29
35
N",mall .. Sign AoHve
36
SuPP'."
-~ 'I~
-
--
,0-1:
,0-15'
-No,hlft:B(T0IB-15.oSUB 15
f-
-
I
"hi, 8 if SAR 15,
,~
--
rlftlf no c..R 15
U-!,
- No .hlft
(SAR 15
15
I
RB171
37
38
ALU.o FOR
AA303
39
Re... FOIVRetoln FOR 0-7
AA303/KB411
40
Inv..-' Switch Con"ol
R8301
",~:7
True 0~15, Inve, ,8-15 -, rue 00/
T,ue 0-1 , Inve," -11 -/'n ,0 lrue/
T"e 0-15, In.,rt 0-15' (0000/
41
42
43
_44
lU
c.
AA302
Six CarrecHon 8-11/12-15
45
Sol Corrv latch
46
So ,Co ,dltic, Coo
AA402
d.
47
I'olnh
'MA401
4B
Ito SAR
KB411
Dolo Switch 10 00 Reg
KB402
'0 Add,... au.
KAS41
51
Op Reg
52
I/O OI•• lav Add,... Oul
53
~
56
.2
ISh
r--=
(01 .. 1 SE'" .'robe)
BAI02
Se"," Ro..,!CTRL St,obe
.,. enl ALU
I SU Check
==
t:::::=
Allow SI,.be
SENS
==
""""'"""
49
50
OE
OE
OE
iAA301
I Gote
Addmonol Co""
-
-
BAI03
-
-
I/O Bu••• FOR
/
58
.M.
60
~1
62
63
64
.M.
---
66
69
Sot SA Check
I CC121
I CC122
I C021
70
Sot Mod Check
I CC10l
71
Set SU Check
67
So. All I Te.' latch
~ .Jot P,ae... Check
B.. _Set AW
~
'\
I
CC102
>Any:check
Check
73
Sot Bu. Cheok
74
Sot SAR Chock
CC10l
j
75
Sot Inh Cheok
Function Signals: 4Cycle £?22,1
Cycle _
"Do not care" Signals: aCyele c::J
Cycle-=::l
• Diagram 5-9. Translate and Branch Short (Indirect Addressing) (Part 2 of 2)
- --
(03714A)
~
~
-
1==
"==
""""=
I~
~
~
!=:=
2020 ~ 50,000 FEMDM Val 2
(8/69)
~
~
1==
- ......
!=:=
-===
~
~
==
--
---
~
':a
Cvcle 0 fnex ,
_TU
I
LS reg 1
remains unchanged
A branch address is combined
with the current block address
and an even byte read out by an
intermediate address (even byte=
direct addressing).
I
Instruction
The intermediate address
consists of the immediate data
byte as block address and the
low-order byte of the 'to reg'.
The 'to reg' remains unchanged.
:c I
Ope~ation
3
B
:
E
:
E
L-=-~-=--+I_3"-.L-=-E-J
address
S
lA'
:
0
I
0
2
No bit 15 = direct addressing
L--------d
I
I
Result:
branch address
(IAR and SAR)
I
S
!
I
0
A
!
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O-I046-XXX
41)BE
TRBL
I, B(LABEL)
BR TO IAR. 0-7/BY(INST.8_1S/Rl. 8_15). IF MY.IS=l BR !NDIR.
'I
A
Direct
Addressing
Note: For "Do not care" functions
refer to timing chart below.
CORE STORAGE - - +
-
-
-
-
-
-
-
-
-
Read out and regenerate
halfword addressed by
intermediate address
Read out and
regenerate microinstruction
-I I
I
-[-[-
I
r-j---,
I SD'
-------- ---t------------ --- ---------------------
r-l---.
I SDR
I
L4_ 2.., 1._E--.I'C--,---1
I
L-A_ ~ 1.. 1.J~1- - - - - I
Not intern SU bit 15 = TR8L direct addressing
(End op cycle l)
Suppress
Suppress
SU
A
A
--I
ALU
OE
I
I
I
I
I
I
Invert sw
I
I
I
(LS reg 1)
jIA'--l
I
~
_ _ _ _ _ _ _- - J
L.~.2.t2_2..J
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
j --.,
rSA'
I
r--!'--,
L8_2.J£_2J
L~~Ll_EJ
~ SAR
I
L ~ .2. ~ _AJ
(Intermediate addr)
T
SAR15
Functions performed during cycle time are shown by full lines and functions performed during A cycle time are shown by dotted lines.
Diagram 5-10. Translate and Branch Long (Direct Addressing) (Part 1 of 2)
(03715A)
Cycle if single microinstr swan
r-"!--,
I SA'
I
202O~50,000 FEMDM Vol 2'
(8/69)
(Branch addr)
"Do not care" signals:
Ll.Cycle C=:J
Cycle -=:J
INa
ALo
Nome
Seme T",p Req.... Une.
I
~ _LSNew PL Zone G•••
4
N",
,/e.".n'
Tl
---
KASII
New/C."en' PL
I CE LS Seloe-,-
---
18
LS C.".n' PL Zone G.'e
_3
5
I LAI03
~
,
ROOd-
L', may di 'fe,
ICC222
T2
Cyol
T4
T5
T6
T2
18
T4
T5
T6
6
7
Fixed X-Add,o..
8
'To Roo' Selee.
9
'F,om Reg' Selee'
LMII
LS.o SAR
KB411
III
LS.o MAR
112
LS'o FOR
LS to TOR
LI4
MAR.o LS
>--
"===
---
~
KB401
LA702-712
~
115 I Se. ALU (VO Bu.) to LS
ill.
~
~
~
----
---
...",
110
113
~
LA412
_LSW,;'e
I--
117
118
Se. Add,e.. Check
I RASOI
119
"","ehGo
I RAS02
1.0
f--
>---
---
---
""'--
----
I LA302/313
>--
I RM02
121
I."omen' by 2
I RM03
I"
n.
I RMOI
i 23
Dec.omen. hv •
I RM02
124
p,..en. Mod-SAR-Inh Check I KASII
125
"'..en' S....ose U..
IMA402
127
SDR'olnh
IMA401
...28
SoR to Op Reg
I K8102
!
26
""'--
29
30
SoR.o TOR
I KB402
31
E1gh. Shift Con"ol
rRBI 62
~ _Shlf' by 2 ar 4
I RBI61
No Shift
IRBI62
33
_34
T••• Pack.d
By'. ar Sign
-
C,... ~hlf'
,-
-
No shift
Narmolize SI.n Ac,;••
36
S. __ •
I RBI71
1AA303
if no SA <15
0-15
:15
I
RAS02
3S
If SA. I ,c.",••hi
'8
37
38
AI Ito FDR
39
Re... FoR/Retoin FOR 0-7
I AA303/1(B4I'
40
In.... 'Switch C",'",I
I R8301
ALU Con"ol Got.
I AA301
Tru.0-1 , 'n.."
1-7 =/00
T..o 0-15, iOY ".8-15 = I' .. e
.. 01
00/
..ft
_42
43
144
Addi,;....l Corry
Six C.....e,;... 8-11112-15
4S
Se. Can-. ,,",eh
46
Se. C...dltion Code Lotehe.
: 47
lAs.
OE
OE
AA302
AA402
ALU
IMA40I
b"."."",."
I KB411
,ALU'o SAR
~
149
1SO
!
51
'0 Oa Reg
'0 Adm-... B••
Dota Switch
Oa Re.
I KB402
KAS41
I--
I---
~ .JLQ oi••I•• Ad...... Ou.
Lll
_Allow S.,obe
I 54
SENS
155
Sen.. Re .../CTRL Sh'obe
I s•..he
156
P,.•• n' A J end SU Check
I 57
1/0
Di .. I'SEN! : ••",be)
BAI02
BAI03
-
""'--
~
,FOR
158
I 59
160
I 61
162
163
lM.
65
166
167 I Se. ALU T... Latch
68 I S.t _ ... Chock
I CCI21
I 69
Set LSA Check
I CC221
I CCIOI
Lm
Set Mod Check
171
Set SU Check
172
Set AL J Check
173
Set Bu. Check
74
Se. SAR Check
75 Set Inh Check
Function Signals; 4.Cycle
I
~
I ('('I?>
'\
~
~
--
i..-.",."
~
""--
CCIOI
/
"Do not care" signals: ACycie c:J
!
~
'> An~ check
f'lliJ Cycle _
~
"===
i..-.",."
,
CCI02
"---
(ihk
"""Cycle-=:J
• Diagram 5-10. Translate and Branch Long (Direct Addressing) (Part 2 of 2)
(03715A)
2020 ~ 50,000 FEMDM Val 2
(8/69)
-
lor-
~
"""-
~
"'"'"'"'"
Cyel, 0 .f .he ~ox. ,
,
,
T3
LS,egl
remains
IB:C
3:E
UnChanged~~:~~=~g~~_ _ _ _ _ _ _ _ _ _l
Instruction
This operation is similar to that
described in Diagram 5-10, pdrt I,
except that the resulting branch.
address is used as secand intermediate
address if the byte read aut by the first
intermediate address is add (bit 15 on).
OP5ration
B:
E
I
Generate intermediate
addreSs
The second intermediate address
reads out a halfword used as branch
address.
o 1
IAR
2
Microinstruction La out
o
Code
To Re
10 11
12
13 14
Immedi"ate Data Addr
15
r--+---.--+-....,
Bit 15 :::: indirect addr
I
.-_..-_'.,
I
1
I
L ______ ~
!~ ~.";!
;,te'med;ate
:
1
Read out branch address
(ha Ifword in
80201
I-~~=A~:=1::;:_
=::=A::I
----i!--.--.ft----.
i
L_________ J
r-I
A
I
:
f
A~CORDrNG
INST
!4NEM
OPERANDS
S'l"ATEMENTS
49BE
TRBL
I,B(LABEIt
BR TO lAR.O_7/BY(INST.8.15/Rl.B.15). &- BY.I5=I BR INDUl.
TO STANDARD CEB O.1046.xxx
RI
A 1 Result: branch address
(lAR and SARl
Branch address
Indirect
Addressing
Note: For "Do not care" functions
refer to timing chart below.
Read out and
regenerate microinstruction
CORE STORAGE -
Read out and regenerate
halfword addressed by
first intermediate address
l-,--
-1---
- - - -- - -- --
"Do not care" signals:
.6.Cycle C=:J
Cycle -=:J
Read out and regenerate
Tbrh...<'An?
Inaemen. by 2
..03
•.u"
I" ""
I 23
Dec,ement bv 2
I RA402
'24
PteYen' Mod-isAR~lnh Check I KASI·
125
I 26
IMA402
P'event 5t",age U,e
rI2~7S~DRtt~0'~lnh~=-~+'=~u~01-+--~--~~---4---+--~--~--~--~n __ 115~0-15
28
SDR
10
Op "g
,0-15
0-15
K8102
29
I 30
31
SDR to TOR
Elaht Shift C.n".1
KM02
R8162
.....
0....-
_
; h l l . ._
No ,hlft
If SAR 15 "0" ,hlft If no SAR
-No ,hlf,8 (SAR "
32 Shift by 2 '" 4
RB161
r"~='~Shhi~,,~----+iR~81~---+---r--1---~--+---+-~~~~-4---+---n~,,-+---+---~~~-4---+---+--nO_15-4---+---+---~--~--I---+----0~5-+---+---r---r-~---+---+--~--~--4---+---+---~~
34
Te.' P.ck.d By'e '" Sign
35
N",mallze Sian Ac.lye
36
SU"'e"
RAS02
u-
R8171
37
38
All' t. FOR
AAJ03
39
.... t FDRI""'ln FOR 0-7
AA303/KB411
40
Inv",t Switch Con".1
R8301
AI' Can".1 Gate
AA301
True 0-15, Inye;' 0-7 ~ /0 I '"e/
T"e O· 15, Inve,' 8-15 ~ /,,",00/
41
42
10E
OE
OE
f-'43"+-,Add=itl",,,,-onal=C.rrv~_--l AA302
44
Six Con-octi .. 8-11112-15
4S
Set Canv Intch
46
Set Candltion Code
.,
I 48
AA402
late'"
LU to Inh
MA401
AlU to SAR
I KB411
I 50
Data Switch to (Jp Rea
I KB402
I 51
(Jp
52
Rea to ......._....
I/O Dlmla......._
KAS41
II--
Out
53
Allow St,abe
54
SENS
55
Sen......t/CTRL 5mbe
56
P,event ALU and SU Check
57
110 '"
I "mhe
m.;;I SEN; .tmbe)
BA102
-
-
-
.....
BAl03
, FOR
58
59
60
61
63
64
6S
---
66
67
Sot ALU ro.t latch
68
Set P,oee" Chock
69
Set LSA Check
CC121
rrlO1
1-'7-'-1--"S",,-8t:,..,
SUU,-,,'
IC=heck_ _--I CCI02
72
Sot ALU Chock
73
Sot Bu. Check
~heck
1
1-'7"'+4.......
SOt ~;""-"ARC""""hock_ _--ICCIOI
75 , Set Inh Chock
Function slgnols: ACycle
)
m
Cycle_
Do not care" signals: 6.Cycle CJ
Cycle-=::J
• Diagram 5-11. Translate and Branch Lang (Indirect Addressing) (Part 2 of 2)
(03716A)
2020~50,OOO FEMDM Vol 2
(8/69)
-
-
Ope~atioll
Instluction
A halfword, read out by an address
comprising a combinatio"n af the
current block address and the
displacement addreu tlow-order byte1,
is loaded iAto" 'to regl.
A
:
A
I
OpCode
I
IAR
°I
8
Microinstruction La
ut
To Reg
10 11
12 13.
Displacement Addr
LH
14
15
0
Indicates Direct addre5Sing
No loading is performed if 'to reg'
::: lS register 7 OAR\,
Generate halfword address L-"--'-....::..-+-'-'-'-~-'
I
~ -+iL=A=,:=8::::~=C::::=:::::D::::!I
LS reg 1
Read
halfword to be loaded
befol·e execution
Remains unchanged
mST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CBB O_1046_XXX
51AA
LH·
l.LABEL
.R.ltt:::HW(IAR. 0-7/INST. 8_14)
RD
Note: For "Do not care" functions
refer to timing chart below.
CORE STORAGE
-----------t------------------------------------
Read out and
~
regenera~e micro~
instruction
-1--1
1
.--j--,
I SDR
1
LL!.l~~
Not op reg bit 15'" direct addr
SU
Suppress
A
ALU
OE
I
I
I
C
A
1
'nvertI'W
(LS feg 1)
r----'
liAR
INS!)
1-1-,-_ _ _ _ _ .
L8_0f'?..
~
I
1
1
I
1
1
1
performed during cycle time are shown by
-2
lines and functions performed during A cycle time are shown by dotted lines.
I"tiagram ' " Loa
Set AW Check
I 73
~
~
0"""",.,.
(8/69)
--
I-
Cycl, " of n.x'
,
,
TO
TS
T2
Instruction
I
OpeTtion
Microinstruction Layout
5
o
A halfword Is read out and loaded
into the 'to reg' (not if 'to reg' =
LS. register 7, IAR).
IAR
The halfword address was
previously read out by an address
comprising a combination of the
current block address and tile
displacement address (low-order
byte).
l5,•• 1
5
before. executi on
8
:
Code
6
a
10 11
12 13
Dis lacement Addr
To Re
0
Indicates indirect addressing
Generate halfword address
and store in SAR
I
:
c
IE:
2
14
15
lH
~
Contains address of the core storage
position which is ta be loaded into
specified register
I
ReadautL--~
A
:
B
I
c
D
I Remoins unchanged
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O.I046.XXX
SlAB
LH
1. LABEL. I
'U·=HW(HW(IAR. 0_7/INST. 8_14»
00
halfword to be loaded
I
lS,.. '
A
after execution
:
B
Note: For "Do not care" functions
refer to timing chart below.
Read out and
regenerate microInstruction
CORE STORAGE - -
-
Read out and regenerate
address of the halfword to
-ibld~
-1
, --,
~~Trol~ed-
---,---.,
SDR
_O__
~-
Read out and regenerate
.. --j---,
I
t~2__L!-:-----1
: SDR
I
,
f-,
I
----i
L.A._B"",S_'!>J
I
I
Op reg bit 15 "" indire<;r addr
I
I
Suppress
SU
OE
AlU
A
r--~-t----------,
o
2
4
2
4
I I II
I
OE
I
DE
I
I
I
A
oI
Invert sw
I
I
I
I
(LS reg 1)
fiAR----:
r-.---------~
I
I
L~_~+~-3J
,
I
,,
,,
,,
,,
r--- Y
--I
MAR
I
,,
,,
I
I +2
t_8__~_O.}_1
I
I
r---t~--,
I SAR
,
I
f----------'
I
I
•L ___
8 0.J ____
0 2 II
performed during cycle time are shown by full lines and functions performed during .6. cycle time are shown by dotted lines.
I
I
,,
,
.----*----,
: 5AR
:
L~_E-1-A_..Bj
____t. ___ ,
SAR
!
_O__ Ll.~_~J
"Do not care" signals:
e..Cycie c::==J
Cycle
-=r
1
AlD
Name
INo
Sen.e T,ap Req,e" Une.
2
lS New Pl Zone Gote
3
lS C",",. Pl Zone Gate
4
New/C,,,ent Pl
5
CE lS Select
ILA103
KASll
I
T8
Ne /c,,,ent
t,. may dl Ffe'
I CC222
~
7
Fixed X-Add,e..
....,
B
'To Reg' Select
l ....02
9
'F'am Rea' Select
l ....l1
110
lS to SAR
KMll
III
lS taMAR
112
lS to FOR
113
lS to TOR
T3
T6
T'
T8
T'
---
I----
---
10.--
I---
......
I----
r----
I----
-
I.r---
---
~
I RASOl
19 I "'aneh Go
I RAS02
120
In«oment by 1
I R....02
121
Inaement by 2
I RA403
I~ _ Dec,eme.t bv 1
I R....Ol
123
Do
124
P..vont Mod-SAR-Inh Check I KASll
,2
I RA402
125
ITevent St",age U.e
IMA402
27
SDR to Inh
IMA401
28
SOR to O. Reg
I K8102
SDR to TOR
I KM02
29
30
--
~
117
126
--
12
"---
f--
----
LA302I313
.ment
T8
T6
I
,."."""",
e.,,) to lS
118 I Set Add,... Check
:ycle
T5
r--
lA702-712
lSW';te
12
~
KB401
115 I Set AlU 11/0
-Tl
Cyde 0
\---l---
~
114 I MAR to lS
116
•
w;rte
31
Eight Shift Con"ol
32
Shift by 2 '" 4
I RB161
33
No Shift
I RB162
34
Te" Packed Byte" Sign
I_un~ ~a_
I RBI62
--
---
, n.
15 ,0-15
--
,,1:1ft 8
-0:15
35
N",mall .. Sian Active
36
S,,,,,,e..
u-" ,0-15
--
-No. :IftB
u-;"
-No. 1ft B
:"
RAS02
I Ral7l
37
Ito FOR
3B
I AA303
39
Re.. t FDR/Retoln FOR 0-7
40
Inv.,t Switch Cont..1
I AA3031KB41'
TNeO~'
'83Ol
Invert: -15 ~ /tn, 00/
TNe O~;'5, Invert,O-15
T", 0-15,ln'~rt 0-15
=/0 lOO/
'/0000/
....4!.
42
'43
44
IAAJOI
AlU Con"ol Gate
Additional Cany
10E
'=='
1:0=
10E
Six C....ctlon B-11112-15
45
Set C...v Latch
46
Set Condition Code latch..
47
AlU ta Inh
IMA401
AlU .SA'
I KMll
...
10E
AAJ02
AA402
49
50
Data Switch to ()P Reg
I KB402
au.
KAS41
()P Rea to Add....
52
~ _ Allow St..be
54
I St,abe
SENS
I(D;,pl SE :'S .t",be)
BAl02
55 I Sen.. Re..t/CTRl S"cb.
56
","vent AW and SU Check
57
I/O 80
......
'---
f--
--
It--
I/O 01•• 10, Add.... Oot
'-
BAl03
,FO'
LM
I 59
L6Q. '
I 61
~
163
I ..
65
---
-.~67
Set AlU T••t latch
i CC121
68
Set P""... Chock
I CC122
69
Set LSA Chock
I CC221
70
Set Mod
C~~k
I cr,IOl
71
Set SU Check
In
Set AW Check
173
Set Bu. Check
I 74
Set SAR Chock
75
CC102
,
I
>
Any :check
CC101
J
Set Inh Check
Function sIgnals: 4.Cycle f2ZZJ
\
~
Cycle_
Dc not eare " sIgnals:
ACycie c::J
--......
~
~
~
~
b-m
b-m
:....-
Cycle-=:J
• Diagram 5-13. Load Halfword (Indirect Addressing) (Port 2 of 2)
(03718A)
2020 ~ 50,000 FEMDM Vol 2
~
'===
'===
(8/69)
~
----
~
~
--0_
~
i...-
-
""-
~
~
"==
...... ......
I...
C;;
;o;;rne~t
Instruction
10
11
12
13
14
15
STH
Displacement Addr
The 'to reg' halfword is stored
in core storage, The address
comprises 0 combination of the
current block address and the
displacement address (low-order
b,te).
I
lA'
8
Indicates direct addressing
A
GenE;rate ha-lfward address
and store in SAR
~
A
I
I
I
LS ,eg I
II.:=A,::::::,::=A=!==B::::::=B:::1
remains unchanged
Re;-;;U~
C
:
c Ie: c
Addressed halfword
before execution
!NST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O_1046_xXX
5,AA
STH
1. Lo\.BEL
HW(IAR. O. 7/INST. 8.14)*=Rl
RD
addressed ha Ifword
B
I
Addressed halfword
after execution
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
ACycle c::::J
Cycle -=:J
CORE STORAGE - - - .
Read out and
regenerate mi croStore holfword
instruction
-1
--I
I
JrDR-
---,
LA_~'!JlJ
Not op reg bit 15 = direct addr
SU
I
Suppress
Suppress
I
I
I
A
------l
ALU
OE
A
I
I
A
Invert sw
I
r-I FOR - - - ,
I
!"'A A 8 B!
~~--"
I
i,;l--l'"~ .,
L~~!!J
r----'
lIAR
I
I
r
LB_O_iE. .L.I
I
I
~_.J'
I SA'
__ ,
I
J
LS_0.J..O_ 2
Functions performed during cycle time ore $hown by full lines ond functions performed during a cycle time are shown bv dotted lines.
>
.Diagram 5-1.4. Store~fword (~ct Addr~g) (Part.w 2)
.19)
.-2020 ~ 5Q.Jl..00 FEMD..b:\...Vol 2
~9)
R.ad
ALD
Name
INo
I
S.m, T,op R'qoe,' [;0"
2
lS New Pl ZoO< Got,
3
lS Co,,,ot Pl Zooe Gate
4
New/Co,,'" Pl
5
CE lS 5,1,01
-,i
T6
T8
IlAI03
KASll
/co""t Pl', ma" I;ffec
N
I CC222
Cv<
14
--
r;;:;;;J
,615
--
LV'"
16
-==
Cycl.
T4
T5
T6
T8
T3
_6
7
F;"d X-Add""
.4l?
8
'To R'g' Select
.. 02
9
'F,om R,,' Select
Ml
brmm;,
KB411
110
lS to SAR
11
lS to MAR
I 12
lS to FOR
~
KB401
; '0 TOR
11
lA702-712
114
MAR to lS
Lt5
5" AIJJJI/O Bo,) to lS
116
lS W,;',
~
~
--
<302/313
I 17
liB
Se' Add"" Check
ASOI
119
"coch G,
AS02
I 20
lo"emeo' b" I
M02
21
lo"emeo' by 2
..03
22
Dec"meo' b"
'23
I KASI
26
p,,"eo' S'ocage U"
I MA402
27
'0 loh
SDR '0 Op Reg
25
28
I MA401
SDR
I KBl02
29
30
SDRto TOR
I K8402
31
E;,h, ShH, Coorral
32
Shift by 2·" 4
I RB161
No Shift
I RB162
~3
~
--
~
"---
-
I...-
---
I RA402
p,,"eo' Mod-SAR-Ioh Ch"k
24
l-
<--
MOl
,by 2
0.
~
\-L~
t-- -
I RB162
34
T", Packed BY'e '" Sigo
35
N",mailze Si" Acti"e
36
SoP"e"
-
-'--
-
,-
----
-0·15
0-15
M,
-No ;;f,8
f--
I
15
RAS02
I
I RB171
37
'0 FOR
M303
38
ALII
39
Re,,' FDR/Retalo FOR 0-7
AA303/K8411
40
10"'" Swl'ch Coo',ol
'''01
Teo, 0-15, 10"",8-15" /t~, 00/
Teo, 1-15, 10"' t 8-lS/tn ,00/
41
ALII Coot,,1 Gate
43
Addltlaool Ca"y
44
Six C",,,ctlao 8-11/12-15
45
Set CO,," Lotel
46
Set Caodltion Code latch"
47
All' to loh
I MA401
ALU to SAR
I KB411
L48
OE
10E
I AA301
42
AA302
AA402
O-lS ,0-lS
"""=
49
I 50
Doto Switch
'0 Op Reg
I K8402
I 51
Op Reo to Add,e" ""
KA541
I 52
I/O 01"1,, Add"" Oot
I
53
I 54
Iss
._56
57
II--
I SENS
ISt"be
)I,pl SENI, ,t"b,)
BA102
I Seo" Re",/CTRl St,abe
P"yoot ALU cod SU Check
BAlO3
I/O"" ,FOR
f--
--
10......
10......
58
, 59
L6Q
61
~.
63
164
-
65
166
67 I Se, ALU Te,t latch
68
_69
I CCl22
Set lSA Check
! CC221
, rh
70
S.
71
Set SU Check
72
Set ALU Check
73
Set So, Check
_74
\
eel 02
5., SAR (h ,.k
Diagram 5-14.
~
I (ClOl
>Aoy ~h,ck
)
Cycle _
--
I.r~
~
~
~
, .
"Do not care' signols: .).Cycle c::J
~
~
Cycle-=::J
Store Hallword (Direct Addressing) (Part 2 01 2)
(03719A)
2020? 50,000 FEMDM Vol 2
I
(8/69)
~
-----Uiili.
~
lot....
(elO!
75 Set loh Check
Function SIgnal!: .6.Cycle EZZI
•
I CC121
Set P,oe... Check
~
---
IM8...ii
iIti..
Cycl;Oaf"xt. '
T4
f5
1'6
T7
,I
Instruction
The 'to reg' halfword is stored
into core storage. The stare
address was previously read out
by an address compri sl ng a
combination of the current block
addi-ess and the displacement
address (Iow-order byte).
I
Operetion
I
IAR
:
8
I
0
A
:,
0
2
Generate halfword address
and store in SAR
LSreg1
remains unchanged
I
L __
Microinstruction La out
5TH
10
Op Code
I
Bit 15 ;s not used for core
/ / storage addressing
11
12
13
14
15
To Reg
Indica'les indirect addressing
A
Rea~-o~t'"
A:A!B:8
Contain's address of- the core
0
:
addressed holfword
and store in SAR
2
I
:
4
position in which the
I storage
register contents are to be
stored
Read out
addressed ha I fword
c
I
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB 0_1046_xxx
59AB
8TH
I, LABEL. I
HW(HW(IAR. 0_7/INST. 8_14))*=RI
c
RD
Addressed halfword r--~-+--:-~----:---'
after execution
,--",A~--"A~,--,----~-,,--,
Indirect
Addressing
Note: For "Do not care" functions
refer to timing chart below.
CORE STORAGE
~
Read out and
regenerate microinstruction
- - - --il-
Read out
store position
- TT---
Read out and regenerate
store address
Store halfword
I
r---LSDR
,---'---,1
,
~,----~
: SDR
~-
I
I
~~_~I- ':._":.
L9._ 1_,l_ ~J
I
--------,
TDR
:
A
A
B
B
I
1
---t--~
Op reg bit 15'" indirect addressing
I
I
,i
I
:
5
SU
Suppress
9
A
I
B
AIAIiIi
~IIII
o
0
A
B
A
A
B
B
I
A
ALU
0'
0'
OE
~-~-t---------,
I
I
A
A
oI
Invert sw
0
0
I
I
0
0
I0
0
I
I
I
I
I
,,
jTo-R;;-- -~
I
I
(LS reg 1)
I
I
I
L!-_~.L.~_~J
I
irA-R----l
I
rl-,-----------~
-t ___
0 2 JI
1..
I _
8 _0
I
,I
I
I
I
I
I
r--j---
MAR
I
I
I
~~_~....O_?. I
I
+2~---------~
I
,
,
,
r--
I
I
SAR
r---t-,
SAR
r---t.---,
SAR
j ---,
I
I
I
I
I
I
I
,
L~_2.L.9._':.J
I
I
I
L.£_~J..~_4_~
8 0 .J ___
A B-JI
1
L.. ___
I
Functions performed during cycle time are shown by full lines and functions performed during A cycle time are shown by dotted lines •
• Diagram 5-15. Store Halfword (Indirect Addressing) (Part 1 of 2)
(03720A)
2020 2:50,000 FEMDM Vol 2
(8/69)
"Do not care" signals:
6.Cycl e c::::=J
Cycle -=:J
AlD
Nome
INa
I
Seme Tcap R.av"t Un"
2
lS New Pl Zone Gate
3
lS Cvnent PlZ~n; Gate'
4
N.w/Coc"n;P'C'
5
CE lS Sel"t
~T4
,
Re'
Read
T.
T7
18
ILAI03
KA511
" may
Hee
Wcit,
yd,
,0
12
---
Read
:yole-
c,'
T2
13
T4
T.
T?
.......
T8
---
-==
:yd,
T.
T8
T3
1'6
T4
I CC222
6
7
Fixed X-Addce"
1412
8
'To Rea' Seled
\407
9
'Fc= Reg' Seled
--L-
"a SAR
11
lS to MAR
==
KB401
"13
lS to TDR
14
MAR to LS
IS
Set AlU 11/0 ... ,) to lS
16
lS Wcite
LA302/313
18
Set Add"" Cheok
RASOI
19
",onch Go
-
-
""==
,FO'
f----
f----
IlMII
17
,
f----
==
---
.----
-
r--
I---
i-------1
r--
LA702-712
~
---L....
==
t---
KIWI I
10
~
----=I
---
-
~
.M02
2O
• ho 1
RA402
RM03
21
Inaement b, 2
"23
n.
Deceement ho ,
24
Pce,ent
Mod-tA.. lnh Check
I RA402
I KASlI
"'e,ent
St~age
I MA402
RA401
25
26
I 27
I ,.
U..
SDR to Inh
I MA401
SDR to 00 Rea
I K8102
-
29
SD' to TDR
KM02
31
EI.ht Shift Con.ol
R8162
32
Shift b, 2
30
33
34
~
Und ,floed _
1--
R8161
R8162
, Shift
Te,t Packed Byte a Sign
35
Namallze SI.n Active
36
Svpoce"
0-15
--
,0=1:<;-
No
0-15
,0-
-
1ft 8
No, hlft 8
O-IS
D-
RAS02
u,
I R8171
37
38
AlU to FOR
39
.... t FOR/Retain FOR 0-7
40
Invect Switch
AA303
1A303!l
Any ch"k
Check
- --
Set ..., Check
74
Set SAR Check
75
S. t Inh C....k
Function Signals. aCycie
CC101
m
Cycle_
I
7
Do not care "
.
~19nals.
LlCyde
c:J
Cycle-=:J
• Diagram 5-15. Store Halfword (Indirect Addressing) (Part 2 of 2)
-
~
(03720A)
~
==
~
==
2020250,000 FEMDM Vol 2
~
==
~
(8/69)
---
=
==
""""""'"
~
~
---
~
.......
.......
~
--
-
' TO •
~
Cycle I of next
I
I
IAR I 8 : ° I ° : '
Instruction
I
Op Code
Microinstruction Layout
F
I
The updated microinstruction
address (IAR + 2) is stored in
core storage. lne store address
comprises a combination of the
current block address and the
displacement address (low-order
byte). lne store address i~
incremented by 2 and used to
read out the next- microinstruction
(branch to store address + 2).
The contents of lS register 4 are
destroyed.
10 11
12 13
Displacement Addr
Op Code
To Reg-7
+'-ft-_.,.-_..,
IAR =8=::,:=0=1;:::=0=::,:=4=
UPdated;-_.,.-_ _
,::1
Direct- AddreSSlng
14
15
l
B51
f
;~;::~ed ,<-_s--,_o_+-I_'--''-'--II
Read 0"' ~
:
:
:
.
_
_
.
Add""ed ho If.w"d
e
::f:::,,::e:::~::'d
I _~~~~~~+II-_-_-_-.2!o~'~ l-_-~=L..:~C~~C~cL....C~~L....C;.
L
'
I
+'
:
aHer execution
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB 0_1046_XXX
5FFE
fiST
LABEL
HW(LAR. 0_ 7/INST. 8_14)1r=R7, BR TO HW (TAR. 0_ 7 /rNST. 8_14)+2
RD
I
IAR
--,0--,
--'S'--':...--'..'-1..t---,-o--L:
LI
Direct
Addressing
Updated combined address
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
c;Cycle c::=:J
Cycle -=::J
Read out and
regenerate microinstruction
CORE STORAGE ------+-
-
-
-
-
-
-
-
-
-
Read aut
stare posi ti on
-I-
Store
~-:-I-
I
I
rI SDR
I
..!-
r-! -.,
l
I SDR
I
I
I
LC_CLC_'-.J
1-,-----1
L'_'..L'_ '...J
r------,
I
BST - 'to reg' '" /7/
r
TOR
I 8
L-
4 t
f - ...J
0
0
Not op reg bit 15 == Direct address
Suppress
Suppress
SU
ALU
--l
0'
I
I
I
I
I
I
I
I
Invert sw
I
Ir-1--:-J
FOR
L.Jl-OtO- 4...J
liAR - --,
I
I
I
I
I
L8_0.L0_'
r
Diagram 5-16.
To Reg
I
r
I
I
I
I
+'
--, '" IAR
°
I
;LsRe94 ~
L 8_Ot'_E-.J
: I
,-.1MAR
~S_ 0..LF_'
.. _i_ l
I SAR
I
l..S_0..Lr:...EJ
LS_0.10_'-.J
Functions performed during
L S_ 0..l. _4J
I
L~~t-F_E~
_i_..,
SA'
I
I
I
r-.!MAR
I
r
_1_
rlSReg4
I
I
I
I
I
I
_t_
ILS_O+O_'JI
I
I
lines ond functions perform{'ri during 8 cycle time are shown by dotted lines.
Branch and Store (Direct fl.ddressing) (part 1 of 2)
(03721)
20202> 50,000 FEMDM Vol 2
(8/69)
~dated IA~
-
,
i
ALO
Name
INo
T3
I I Se ... T,oo 'equ.,' L1."
LAI03
2
LS N,w PL Zoo, Ga.e
KA511
3
LS Cu"en' PL Zone Ga"
4
New/Cu"en' PL
T4
T5
N,w/,u"•• ' 'L', mav
5 I CE LS 5.1.,.
--
T6
ilff.'
I CC222
--
T3
----
,
Cyel,
m
T2
T4
r.l
Is
m
6
7
Flx.d X-Add,."
,AI?
8
'To .... 5.1".
...02
9
'00' Seled
'F,am
LS
III
LS.o MAR
II.
5'0 FD.
113
LS.o TDR
: 'To ~g' de,od. '7)
(X~dd " 7 blo,k,,'d)
~
~
LA702-712
A=h"
1,8
Set Add"" C,,".k
A'"'
I,.
..••• h
ro.
AR~_ _- I K8411
11
"
(> -add, 7 bl ~ck'd)
LS'o MAR
f-'-'12"-f-'L...,S".!!..!0,IF=-DR_ _ _-l K8401
13
LS'oTDR
f-'-14"-f-"M"",-"AR'.0::..:'IL"--S_ _--llA702-712
IS
Se. ALU (f/O Bud to LS
16
LS
"'I••
-
LA302I313
17
18
5•• Add,... Check
RASOI
19
"oneh G,
RAS02
I ,n
,I
RA402
I 21
In ...men' bv 2
, RA403
I"
no
,I
I RA401
I 2l
0..._ _. . . ,
I RA402
I 24
h,v.n' ModW and SU Check
<7
11n~,
i An, ch.ck
j
Cycle-=:J
• Diagram 5-17. Branch and >tore (Indirect Addressing) (Part 2 of 2)
(0 3722A)
2020 ~ 50,000 FEMDM Vol 2
(8/69)
---
---
-
I
"Do not care M signals: aCyel. r=J
-
--
Cycl~ 0 of nexl
Example 2: Unsuccessful 8M
Example I: Successful 8M
Microinstruction Layout
BZ
10
Instruction
The 'to reg' is tested for being
zero, minus, plus (not zero), or
an invalid address (outside
customer area). Successful
testing causes c' branch. The
branch address is a combination
of the current block address and
the displacement address (Iaworder byt-e). if no bronch, the
updated microinstruction address
is used.
Op Code
I'~
IAR
before execution
~~
L_
LS reg 1
This is
12
13
14
1S
BZ
0
F
(1
I
:
:
~
°I
I8 ° I °
negative binary number, therefore branch
SM
SM
BP
j
SAC
BP
Direct addressing
A
I Branch address
SAC
LS reg 1
I
18:0!O:AI
IAR (and SAR)
after execufiorl
11
Dis lacernen! Add,
To Rea
This is a positive binary number r therefore
IAR
after execution
(Modified by +2)
I
8
°
c=:
4
I NSI
--¥
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CE:I3 O-1046_XXX
610A
690A
7IOA
790A
BZ
BM
BP
BAG
I,LABEL
I,LABEL
I,LABEL
I,LABEL
BR
BR
BR
BR
TO
TO
TO
TO
LAR.O_7/INST.8_14
LAR. 0-7!INST. 8_14
IAR. 0_7/INST. 8_14
LAR.O_7/INST.8_14
IF
IF
IF
IF
Rl=O
RI,LT,O
RI, GT, 0
Rt INVALID
RD
Direct
Addressing
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
t>Cycle c=:::J
Cycle -=:J
Read out and
regenerate microinstruction
CORE STORAGE -
-
-
-
-
-
-
-
-
-1-
-
-
t
I
t
r-J--,~.-____~
I SDR
~6_ ~ E._AJ
(7) (9)
No op reg bit 15 =
direct addressing
SU
A
OE
ALU
Invert sw
iiAR----,~1
__
L8_ 0-t.£._2J
J
I
6"'"
I
I
:
I
I
I
....--L-
I
8 0 0 A
I
I Branch go
-,--~
I
~...Q....!
I
I
No branch (NSI)
r-L_J,
I
I
IL
t
r-J--,
I SAR
:
SAR
I
____ JI
I
Branch Go
~lL ~.Q.2J
FL
Functions performed during cycle time ore shown by full I
Diagram 5-18.
and functions performed during
a
cycle time ore shown by dotted lines.
Branch on Binary Zero-M~nus-Plus, Address Check (Direct Addressing) (Part 1 of 2)
(03723)
2020150,000 FEMDM Vol 2
(8/69)
..
AlO
Nom.
INo
.T4
I
So... T,op Req.,.,1 Uno.
2
lS New Pl Zoo> Gol.
3
lS Curr•• ' Pl Zo••
4
New/Curr••fPl
I
T5
I LAI03
KASII
Go,.
,
N., ' "
5 I CE lS Sol."
Cv< ;0
--
T6
Ic022
12
""'--
6
7
Flx.d X-Addo-."
8
'To Reg' Sol."
9
'1Tom Reo' Sol."
lA411
110
lS '0 SAR
K8411
III
LS '0 MAR
112
lS 10 FOR
113
lS 10 TOR
114
MAR '0 lS
115 I So. AlU
116
~ Ilf b",n,h
..12
lA402
~
~
K8401
LA702-712
evO Bu.1 to lS
f--
lS Writ.
f--
--
117
So. Add",.",.",... If.o b. ~,h
"---
RASOI
~
I RAS02
I
U02
121
I....me•• by 2
122
o.,..me.' ....
123
O" .....nl bv 2
124
P"",••• Mod-SAR-I.h Cho,k IusI'
1RM03
.....1
I RAA02
125
126
Fr..... S...... U..
127
SOR.olnh
I MA402
IMMol
128
SOR to 0 ....
I K8102
SDR.o TOR
I K8402
L31
Elghl Shin Con"ol
IR8162
132
Shift bv 2 ... 4
IR8161
-
129
130
I 33
No Shift
R8162
134
T••• P.oked Bvt.... 51••
RAS02
35
N..mallze 51"" Ao.lv.
36
Su~.
R.171
AA303
1-
-
I- I-
--
0.:15
37
3B
ALU.o FOR
39
..... FORl .... I. FOR 0-7
AA303IK8411
40
I..... Swlt,h Con...1
R8301
T",e'
:,:;s.-I.ve ;e-;s=. '",e'OO/
41
42
'43
"',
Al" Co
AA302
44
Six Corre,'lon 8-11/12-15
45
So. Corr. lotoh
u. ""C, odlll,
47
...
dE'
IAA30I
Additional Corry
,C~
-""'
AA402
..
,LU '0 I.h
IMA401
,lU oSAR
I K84l1
""""'-
If b",",
49
150
Data Swlteh 10 Op "g
I 51
Oa Reo '0 Addo-... Bus
I 52
I/O 01..10. Add... Ou.
S3
KA541
It-
All ........
I Skabe
54 I SENS
55
I K8402
IIDI..ISE ~S .In>b.l
BAI02
Sense Reset/CTRl Skob.
c..56.
.
157
I/O Bu. '0 FOR
A'It
, .. ,
c,
BAI03
I--
--
"---
; 58
I 59
l60
I 61
162
163
1601
165
---
166
I CCI21
167 I So. AW Te.. Lateh
168 I So. Proc. . Chock
I CClO.
169
Icc"l
I So' LSA Chock
170 I So ..., 'Ch
Lz!
I Sot SU Chook
In
So.AW Check
173
So. Bus Chook
74
...
So. SAO Check
75 So. Inh Cheek
Function Ilgnals: 6.Cycl. Ell
~
1\
I eelo,
\
CCI02
I
-
>A.y:'h.d~
I
CCIOI
I
Cycle _
I
.J
liDo not care" Slgnals1 6Cycle 0
Cycle-=:l
---
I ""ill!<
----
• Diagram 5-18. Branch on Binary Zero-Minus-Plus, Address Check (Direct Addressing) (Part 2 of 2)
---
"
~
L..-
~""h
•
~
1".,. ..J iii.., ,
'","'n) b"""",
~I
-
branch
Cy~l. 0 of .~x'
(03723A)
2020 ~ 50,000 FEMDM Vol 2
(8/69)
o: 8 I
Instruction
Example 1: Successful SAC
Example 2: Unsuccessful RAC
I
The 'to reg' is tested for beil'lg
zero, minus, plus (not zero). or
an Invalid oddress (outside customer
area).
4
IAR
before execution
I
8
I
2
J
:::;8=~~=.:..o~-r!;~~~_-.::..8-=,~(
_
Successful testing causes a branch.
The branch address is read out by an
address comprising a combination of
the current block oddress and the
displacement address (Iow~order byte).
If no branch the update microinstruction
address is used.
:
C
I
2
3
Op Code
Microinstruction Layout
6
7
10 Jl
12
13
To Reg
Displacement Addr
I~o I
lS reg 1
8
:
BZ
BM
BM
BP
BP
BAC
Indirect addressing - - - - '
I 0
0 I
======~======
I
F
15
ThO"''''';~-'=r
Sit 15 is not used for core
// storage addressing
:1
:::c~u~ddrJs-----I
BZ
14
0
Remains
unchanged
8 :
IAR
after execution
(modified by 2)
0
to:
BAC
4
1 NSI
This is an invalid address, therefore branch
fAR (and SAR)
after execution
INST
MNE::M
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O.1046.XXX
610B
690B
710B
790B
BZ
BM
BP
BAC
I, LABEL,!
I,LABEL,!
I,LABEL,!
1.LABEL,!
BR
BR
BR
BR
TO HW {IAR. O.7/INST. 8_14)
TO HW {IAR. 0_7/INST. 8_14)
TO HW (IAR.O~7/INSl'.8~14)
TO HW (lAR. O~7/INST. 8~14)
IF
IF
IF
IF
Rl:::O
Rl,LT,O
RI,OT,a
Rl INVALID
RD
Indirect
Addressing
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
A Cycl e
Read out and
regenerate mi cro~
instruction
CORE STORAGE -
-
-
-
-
-
-
-
-
-+---
Read out and regenerate
- b=r
-II
add I.'!....
I
I
I
I
r---t.---,
SDR
I
I
I
I
h--~
I
6
lOB I
L.(7i(9)--- •
r-;::-+---,
I
I
Op reg bit 15 '" Indirect address
(7) (9)
6
1
su
Suppress
I@I%il
o
0
0
o
8
I I 8I I
o
0
0
I
0
1111
0
0
I
ALU
DE
------~---1
I
Invert sw
r-------,
liAR
Ii--,-_ _ _ _ _ _ _ _-'
L~_~rO--2~J
I
I
I
I
I
I
I
---L
:
I
I
r---I-- -
I MAR
I
8ranch go
I
I +2
L!J_~J,E_~_'
9000
-----,I
1----------'
I
I
-.--
I
"___1___ ,
I
SAR
IL. ___
8 0
0 2
I
cyc~
I SAR
I
I
IL. _______
I
time are shown by full lines and functions performed during .6. cycle time are shown by dotted lines.
Diagram 5-19. Branch on Binary Zero-Minus-Plus,
I
I
"_1. ___ 1_,
I
~_~_~,J
Func!ions performed during
I
8 0 0 4 No branch (NSI)
I
I
I
~
Addre~ Check (i"direct Addressing) (Part 1 of 2)
(03724)
2020'~ 50,000 FEMDM Vol 2
(8/69)
I
I
...JI
Cycle
c::::::J
-=:J
2
LS New PL Zone Gat.
3
LS Cunent PL Zone Gat.
4
New/Cu"ent PL
5
CE LS Select
KAlil
Ne
Cunent
,m.y
lie,
ICC222
-
6
7
Fh
Any:ch.ck
I
au. Cheak
74
cel0l
j
I'lJJ Cycl. _
~
....iiQ..
CCl22
J
"Do not care" signals: ACycle c:J
Cycle-=:J
• Diagram 5-20. Branch Unconditional (Direct Addressing) (Part 2 of 2)
{03725A)
-~
---
~
~
2020 ~ 50,000 FEMDM Vol 2
Cy~le 0 of n"t ,
(8/69)
T6
TS
T'
o ;
Instruction
B
I
Microinstruction Layout
7
OpCode
An unconditiollQl branch is
performed. The branch address
is read out by an addre$S comprising
a combination
the current block
address and the displacement
address (Iow-order by",)
18;00;2
==::==:'--"---L.""::'-l
IA'
before execution
of
, 1 12
13
10
Displacement Addr
14
I'J
,Bit 15 is not u$ed for core
/ storage addressi n9
/
Indirect oddrening
Generate he Ifword address
and store in SAR
L- - - ::~e;t branch
-..t
9
:
0
0':
I
0
~=::=~====
~mains unchanged
IA'
after execution
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD Cf:B O.104{,.XXX
800B
B
LABEL,!
BR TO HW (IAR.O.7!INST.8.14)
'D
Indilect
Addlessing
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
.6. Cy cI e c:::::J
Cycle -=:J
Read out and
CORE STORAGE -
regenerate micro-
-
-
-
-
-
-
-
-
-
Read out and regenerate
branch address
-----i-'--
InstructIon
-II
I
I
r-.J.-...,
I SDR
r - -'--,
I SDR
Ii-,-------j
L~2.J.2_o..!
~8_0...L~}J
Op reg bit 15 = indirect addressing
SU
Sopp","
o
------1
ALU
0
11I11
o 0
~II
o 0 0
OE
I
00 00
00 I00
Invert sw
I
I
r--L -,
I
r-!'-,
I SAR
I
I
I
r- j
I SAR
I SAR
L. 8_ 0...1" 0_ B.J
L8_0.J.'!..~
Functions perfonned during cycle time are shQwr:' by full lines and functions performed during .Co cycle time are shown by dotted lines •
•
.J)iaqram 5.::.2.1. Brancll-lJncondiHanal (lndire~ddressi~(Part 1 ou)
(03~)
2llZQ2:50,O.llll..FEMDM
--,
I Cycle if single
$W on
L9_O~O_ oj microinstr
~2
(8/6.2l..
No
AlO
Nom.
I
Se... T,ap Req...., lin..
2
lS N.w Pl Zone Go ..
3
lS Cu"en' Pl Zan. Ga'•
•
N.w/Co.,.n' Pl
5
CE lS Sel."
I LAI03
~
~
KASlI
N",/,u""n' l'. may dl FF.,
W,U.
T'
-
R.ad
Cyd.o
TO
T5
T6
7
FlKed X-Add,."
..12
~To
<402
9
'From Rea' Sel."
12
13
Re.' Selec'
.---,
~
"1'
K84l1
LS to SAR
"'-=
lStoMJ.~
r---
; to TOR
'0 LS
liS
Se. AlU (VO Bu.) to lS
116
LS Wrl••
r---::=::
I---0.3021313
17
18
Se. Add.... Check
RASOI
19
......h Go
RAS02
20
Incnmen' by
RAA02
I.".men' by 2
RA403
122
Ooaemen.
RA401
123
OO....ment by 2
RA402
12,
Pnwen. Mod-SAR-Inh Check I KA:!Jl
~
T6
T'
r--
-
re
T2
T3
~
r-
-- -
---
---
-
LA702-712
MAR
-----
-
K8401
LS'o FDR
114
21
T3
I CC222
8
111
-
T8
6
110
I,
01.
--=-
I
125
126
Preven' 5....... U..
I MA402
127
SDR tolnh
IMA401
128
SOR to ()p Rea
KBI02
SDR.o TDR
K8402
3J
Eigh. Shift Con"ol
RBI 62
32
Shlf. by 2· "' ..
RBI61
--
129
30
33
No Shift
RBI62
34
T••• Packed Byt.... Sian
RAS02
35
N_allze Sign Activo
:16
Su~_
-
-
I
~' n~ ~= ~
RBI}!
37
3B
ALU to FDR
AA3113
39
Ro... FOIVRetoln FOR 0-7
AA303/K8411
40
Inver. SwU,h Con",,1
RB301
.
Tru. )-15, In.. '0"1.5 =
Tru.O- 15,lnve,' 8-15: /" ,00/
I0000/
41
143
.LU Con'"I Got.
OE
AKJ02
44
Six C"""'lon 8-11/12-15
45
Se'~la..h
...
OE
'A301
Add1t1onal Co"y
AAA02
,Conditl. ,Code lQtcheo
47
ALU.olnh
48
ALU'oSAR
MA401
~
~
I K84l1
49
'0 Op Reo
I K8402
Bu.
KA541
50
Dota Switch
51
Op
52
VO 01..lav AddnoIS Ou.
Reo '0 _
53
.lIewS......
,54
SINS
55
Se... Re.../CTRl Stnobo
.6
....
57
VO au..o FOR
.,~
I Strobe
• 5U Ch,
t=---
OI.pl SEN' i .,..b.)
BAI02
BAI03
1-:::::-=
--
-
-
58
59
60
61
62
·63
64
65
166
167 • Se. ALU Toot latch
Or-:--
CCI2t
Set_Check
CCI22
JH
Set LSA Check
CC221
'"
-.Z!
,,,,,C.ck
CCIOI
,
CCI02
I
68
Set.i!!! Check
72
Set ALU Check
73
Set Bus Check
74
Sel SAR Check
75 Set Inh Checlc
Function .....1.: 4.Cycl.
\
}
-
A "h.,k
I
CCIOI
I
.J
FIlJJ Cycle _
~
....IiQ.
...
-00 not care sIgnals: 6Cycle
t::l Cycle ~
• Diagram 5-21. Branch Unconditional (Indirect Addressing) (Part 2 of 2)
""""""'"
----
(03726A)
~
~
~
~
""""""'"
~
""""""'"
2020 ~ 50,000 FEMDM Vol 2
(8/69)
-
-
---
~
""""""""
Cy~le 0 of n~. ,
Microinstruction la out
Op Code
(Current zone)
lS register 4 of the current
lS zone (defined by the current
program level) is stored into the
'from reg' of the lS zone
specified in the 'to reg' field.
lS reg 4
lS ceg 1
zone 2
before execution
remains unchanged
;~::g2'
I' : I°
2
1
I
10
To Reg
11
12
13
14
From Reg
15
STR
Zone
L-'---L"":--'--'---'''''':':.......J
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O_1046_XXX
8221
STR
2.1
Rt
PL2*=R4
FF
after execution
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
b.Cycl e c=::::J
Cycle -=:J
Read out and
regenerate microinstruction
CORE STORAGE ----+
-
-
-
-
-
-
-
-
-
-1- - -
I
I
ISOR 1. - l
I
i-r---'
L!' -' 13 -"- J
lS zane
From Reg
SU
A
AlU
0'
Invert sw
(lS reg 1 of LS zone selected
by the 'to reg' field)
fJAR - ,
I
LB_0.L.£
I
I
I
U
1-1
I
Note: Zone selected by the 'to reg' field
in the instruction
I
I
I
I
I
Functions
+2
cycle time are shown by fuJ[ lines and functions performed doring
Diagram 5-22. Store Zone Register (Part"1 of 2)
"(03727)
a
cycle time are shown by dotted lines.
2020250,000 FEMDM Vol 2
(8/69)
No
ALO
Nome
Req~,t
Sen.. T,op
,I
Uno,
I LA103
~- .. LS New PL Zone Gote
•
TO
T5
TS
LS C,,,.nt PL Zone Gat.
,3
S
KA511
-.
i
,:!,w/'''''''C'. L', may Hfe,
New/C,,,ent PL
I CE
Ly'
---- -
,,v
-'0
T8
-----
ICC222
LS Selo3
34
35
NO FOR,
58
59
60
.A!
62
63
',64
.M.
I 66
67
Set ALU T.,t latch
68
Set""
69
Set LSA Chock
I CC221
Set Mod Cheek
ICC10l
70
,Ch~k
171
Set SU Check
..Z£
,SetAW Chook
73
Set Bu, Cheek
7.
Set SAR Check
75 Set Inh Check
function ligna II: aCyel. 11m
-==
CC121
~
CCI22
'\
\
I
;> A" ,he,k
CC1D2
I
I
CC10l
/
Cycle _
"00 not care" signals: 6.Cycle c:J
Diagram 5-22. Store Zone Register (Part 2 of 2)
Cycle-=:J
(03727A)
-----
~
---
--
I"T8_
0.-
2020 ~ 50,000 FEMDM Vol 2
(8/69)
~
I Cyde 0 ~f next
,
T6
17
TIl
T3
T'
T5
T6
Microinstruction La out
The: 'to reg' field specifies an
LS zone (0 to 7), the 'from reg'
af which is leaded into LS
register 4 of the current LS
zone (defined by the current
program level ,Pll '.
LS reg 1
zone 2
I
A
:
.1 ° : 1
B
lS ""
before operation
1
o
2
:
3
LR
10
Code
°,
To Re
11
12
13
14
15
Frcm Reg
Zone
remains unchanged
LS reg"
=':::--'--'--'-""::'--'--'--'
!NST
MNEM
OPERANPS
STATEMENTS ACCORDING TO STANDARD CEB O-1046_XXX
8321
LR
2,1
R4*=Rl
PL2
FF
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
ACycle r:=:::J
Cycle -=:J
-
-
-
-
-
-
-
-
-
Read out and
regenerate miCfOinstruction
-1- -
-
-
-
-
----. - - -
1
1
r-l--,
r''r----'
I SDR
LS_3.12_1-J
LS zone
From reg
SU
AlU
0'
c
A
Invert sw
.---~~
rlAR--l
-t
I'I
:
I
1
1
(LS reg 1 of zonf' defined
by the 'to reg' field in
the I.nstr)
Note: Zone selected by the
'to reg' field in the instruc.tion.
1
L8_ 0 0_ 2 .J
1
1
1
1
~_.I_-,
I
SAR
1
LS_0.J.0 _ 2.J
Function~ performed during cycle time are shown
by fUll lines and functions performed during
Diagram 5~23, Laad Zane Register (Pa~ I af 2)
• (03728)
.o:l.
cycle time are shown by dotted lines •
~20 ~
50,000 FEMDM 'lol 2
(8/69)
(Current zone)
-
-
-
-
-
-
-- ------------
~----
-
-- ---
I'"
Name
I
So... Trap Roq.... U....
AlO
2
lS Now Pl Zone Gate
3
lS C....n. Pl Zan. Ga••
4
Now/Curron. Pl
5
CE lS Sol•••
ILAI03
KASII
·14
WI313
18
So._Chock
1•
.....hG.
_
... ·1
......
LA1Q2.712
-
,...---..i
-
17
20
121
122
I ..
..
i 24
,
, 26
07
T8
T2~
....a...
-
-
..----.
........
.....,.
..."
1RM02
,~
P_n. Mod-5AIt-Inh Chock lun
Proven.S..... U..
1-
.DR •• '.h
I ......... ,
2B I SOl 10 ()P Roo
......
I K6102
29
I KB402
30
SOl'o TOR
31
EI.h. ShlR
32
Shlft ... 2 .. 4
I RBI.I
N."i I. 0 ofn~t
T4
T5
T6
1'4
-,.s
Microinstruction layout
LS reg 5
remains unchonged
The 'from reg' is split according
to the selected split mode (0 to 3).
The result of the split is set into the
'to reg' and the next highest LS
register ('to reg' + 1). The 'to reg'
must be an even numbered register
(but not 6) othelWise the data to be
placed into the next highest LS
register will be lost.
o
Code
Slit
AC
10
To Reg
MVHS
11
12
13
14
From Reg
15
MVHSO
MVHS 1
Split mode
o
1
I
---C~~
Address check is ignored. The
'from reg' remoins unchanged.
'From reg' and 'to reg' may be the
same lS register.
MVHS 2
MVHS 3
__________________________
~
!NST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB 0_1046_xxx
8825
8A25
8e25
BE25
MVHS
MVHS
MVHS
MVHS
Z,S.O
2,5,1
2,5,2
2,5,3
R2*=100'/RS. 0_7 .R3 ='00' /RS. 8_15
R2*='0001/R5. 12_15, R3 ='0' IRS. 0_11
R2*=SL 2 '0001/R5.0_3, R3 ='0'/R5.4_15
R2*=SL 2 '0001/R5.1Z_15, R3 "'01/R5.0_11
FF
DD
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
CORE STORAGE ---+
Read out and
regenelale micro..1.!!!truction _
,
~----~-------------
f---
iSDRL-i
L,----~
I
MVHSO '"
1=
I
~I!. _8-, ~ _5_~
2=
(A)
(C)
3 =
(E)
A
~Shift
MVHSO
o
0
C
MVHSO
C
No AC
I~
MVHS 1
-
A
A
I
A
MVHS2
SU
No Shift
MVHS 2
I
0
I~
MVHS 3
DE
AlU
oI
(lS reg 5)
r-------,
IAR
I
:
2:
- ;I
L8
__0
-+0
___
..1
,
,,
I
I
I
rI
_.1___ .
MAR
!8
L'lCycie 2-Cycle 2
I
0 0 2: +2
'- __ ::..1 ___ _
I----------------l
A Cycle 0 - Cycle 0 (read out next microinstr)
Functions performed during cycle time are shown by full lines and functions performed d",ri"s A cycle time are shown by dot~d lines.
Diagram 5-24. Move Halfword and Split'{DD) (Part I'of 2)
(03729)
A
DE
Invert sw
t
I~
B
A
2020 ~ 50,000 FEMDM Vol 2
(8/69)
0
0
I
~Cycle
c:=::J
Cycle
-=:J
ALO
Name
INo
I
S.n,. T.oO Req,.,t U,.,
LAI03
2
LS New PL Zon. Got.
KA511
3
LS C,rr.,t PL Zone Gat.
4
N.w/C,,,.nt PL
5
CE LS S.I.,t
-
,.
~T4
Tl
T6
18
N. fo"rent L'. moy, ff••
-
-
'To Rea' Sel."
9
'F.om 'og' Seleet
LA411
10
LS to SA'
KB411
112
LS to FOR
113
LS to TOR
'I,
'I:
LA402
~
=
KB401
MARtoLS
LA702-712
-
I Set ALU (I/O IN,) to LS
~ JSWdt.
r--
---
LA302/313
17
18
S.t Add••" Check
'AS01
19
i!then
0-1
Cycl. O' of next
Microinstruction Layout
9
Example: Shift left by 2
The 'from reg' is shifted left or
right as specified in the shiftamount field (bils S, 6, 7 or the
microinstruction). The shift
result is set into 'to reg'. The
'from reg' remains unchanged.
'From reg' and 'to reg' may be
the some lS register.
10
11
12
13
14
15
SlM
SRM
LS reg 3
before execution
.. Shift left by 2 bits
Set to zero
Lost
LS reg 3
rt-.-L---'T--''-----'<,-L-L,--L-L,
Il':S]
MN£1
OP.c::RANDS
STATEMENTS ACCORDING TO STANDARD CEB O_1046_XXX
LIE. >-"'-'-"+-'-'---'-+=-4=~
9033
SLM
3,3,0
R3*=SLO R3
FF
after execution
DD
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
t>.Cycle C:=J
Cycle -=:J
-- --- -J ---- -- -- - -- ----
Read out and
regenerate micro-
CORE STORAGE -
I
I
I
+
SlM (0-6)
SRM (S-E)
- -----r---------- ----- ---I
I
------t
SU
TOR
Shift Result
8 shift
Lost
t
OE
AlU
I
I
I
Invert sw
0
0
I
0
D
000
001
10
100
SlM
SLM
SlM
SlM
SLM
SLM
10
12
SRM
t
SRM
SRM
I
t
(LS reg 3)
(LS reg 3)
Functions performed during cycle time are shown by full tines and fvnctions performed during 6. cycle time are shown by dotted lines.
Diagram 5-26.
Shift Left/Right and Mov/: (DD) (Part 1 of 2)
(03731)
20202: 50,000 FEMDM Vol 2
(8/69)
101
110
D1
D2 D3
D2 D3 0
D1
D1 D2
D3
0
D2 D3
0
2
0
D3
D3
0
0
0
I
I
I
X
~
Lost
SRM
SRM
SRM
I
DO
0
o
10
12
000
001
01 0
1 00
101
110
D1
D2
D3
DO
0 DO D1
D2
D
D2
DO D1
D1
DO
DO
0 0
0
DO
0
0
I
I
I
~
N._
INo
..LO
1
Son.. T,ap 11eqw.t U....
2
LS New PL Zone Gale
3
LS C.......t PL Zone Gale
4
New/C....nt PL
5
CE LS Solect
7
Fixed X-Add<...
'To Ilea' Solect
9
'm... Ilea'
110
LS to SAlt
111
LStoMAl
12
IS to FOR
-'~
14
MAR to LS
~T4
TS
~~
T6
18
K..,l1
.
-
.....
Y02
Solect
IWll
~
KB411
~
-==
KB401
LS to TOR
LA7D2-712
15
Sot ..LU (VO Bu.) to LS
I.
LS W,lte
r----
-
r--
<302/313
17
18 I 50
;19
..,... Chock
-T3
T6
18
TS
T4
TI
T6
T7
18
18
-
-
Iotr--
--
--
RA5C)1
RA502
Branch Go
I........nt by 2
. ""
.
23
Dec",ment bv 2
RM02
2.
P_nt .... "SA ... ,nh Check
K..,l1
26
Prevent St...... U..
MM02
27
SOR to Inh
MMOI
R......
.20
i 21
12
ICC222
6
8
. LAl03
.
Cycle 0
T4
TS
RMOO
...",
25
.
I SORto 00 Ilea
- --
K8102
129
SOR to TDR
K8402
31
Eight Shih Con".1
RBI62
32
Shift bv 2 ... 4
RB161
30
No Shirt
34
Te" Packed lIvte '" Sian
135
""
10
Shift Right
by,
by,
4
B
-xx
-
X
I RB171
37
38
..LU t. FDR
AA3D3
Roset FORiRoialn FOR 0-7
M303I1<
><
Microinstruction Layout
,
1LJ
Op Code
The halfword read out by the
'from reg' is shifted left or
right as specified in the shiftamount field (bits 5,6,7 of the
microinstruction) .
Shift
From reg
LS '" 2 1 1
:
2
I
3
--JIoi
Ie:
A: B
Remolo; "",hOO"7:7:I I
... Shiff- left by 4 bits
To reg
LSregl16:7
before execution
8
:
12
13
14
11M
15
From Reg
Remains unchanged
: 4
Read out addressed halfword
The core storage halfword
read out by the 'from reg'
remains unchanged.
11
SLM
SRM
Example: Shift left by 4
The shift result is set into
the 'to reg'.
To Reg
D
I
c--
-r:-C-'-rl-D'-r-:~OI-'
LS "9 T ' I--',
after execution
9 1
Set to zero
S
Shhllftft,',.01,
INST
MNEW
OPERANDS
STATF:1c,fF;NTS ACCORDING TO STANDARD CUl O_I046_XXX
90IA
SLM
I, ZI, 0
Rh=SLO HW(RZ)
FF
DX
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals~
t:.Cycle C=::J
Cycle -=:J
CORE STORAGE -
---------,-L''''']
Read Qut and
regenerate micro-
Read out and
regenerate
-
-
-
--
J
._-':fro..!!!..2pe!Q.!ld'
I
I
r-l----,
I SDR
I SDR
L9_ O....~ _AJ
LPO_Dl-LP~.P~--
I
SLM (0-6)
SRM (8-E)
/
---,
I
- --1
SU
I
OE
ALU
SRM
SRM
SRM
SRM
SRM
Invert sw
r-----,I
I From Reg
I
(LS reg 1)
(LS reg 2)
I
L1_~I~~J
I
I
I
I
I
1
Functions performed during cycle time are shown by fvlliines and functions performed during A cycle time are shown by dotted lines.
Diagram 5-27. Shift Left/Right and Move (OX) (Part i of 2)
(03732)
SLM
SLM
SLM
SLM
SLM
SLM
2020 ~ 50,000 FEMDM Vol 2
(8/69)
10
12
u-instr
bits
TOR
8 shift
Shift Result
I
I
I
000
001
o1 0
100
101
1 10
000
001
010
100
101
X
X
X
Lost
I
I
I
I
X
X
X
W,He
Nam.
I
Se ... T,ap Reque •• Line.
~y,'.
T5
-.T4
_LS
~
__3
4
5
12
KASII
LS C"".n' PL Zan. Ga ••
N., j,.".nt L'. may dn.,
New/C.".n' PL
I CE LS S.I.,t
•
7
F'xed X-Addo-...
'Ta Rea' Sel.,t
9
'F,,,,,, R•• ' Sel."
LS to SAR
III
LS to MAR
12
, 13
LS to FOR
14
MAR.o LS
"'12
1LA402
-==
",r
K8411
""""""'"
--
""""""'"
K8401
LS to TDR
LA702-712
Se. ALU (VO Bu.)
1-----=
LS
10
LS W.I••
LA302i313
18
S•• Add,... Check
IASOI
19
...
116
[---
17
,G,
IAS02
120
In""",,,n' by I
121
In "omen'
I RA402
I RA403
122
Dec..men'
by
123
Doo,omen'
by
124
P....n. Mod-SAR-Inh Chad<
KASII
126
p'e..n' S."'... u..
MA402
'27
SDR.olnh
MA40I
SOR
<8102
by
,I.
TO
T.
Tl,
TS
--- -
TJ
T4
T1
TS
ICC222
8
110
u
-
I LAI03
New PLZan. Ga ••
T4
T3
,
Read
ALO
INa
2
--
f...-L-
----"""""""
-
f...--!--,
r----
~
1-----=
1==
---=
-==
-=---
.....
.....
---
RA401
RM02
2
125
28
10
O. Re.
-
29
30
• 31
, 32
SDR.o TDR
, K8402
EI.h. Shift Can"ol
118162
ShIft by 2 '" 4
I RBI61
i 33
No ShIft
I R8162
I 34
Te •• P.,ked By•• '" SIon
L1.5,
N_.U.. SI ... Actlv.
, 36
S.......,
-
---
,
f- - f--
-
-
-
---2-
-
RAS02
,~
-----=
by:
12
f-- -
-
-= -
10
4
8
-- - >< X X
- >< X
-
r--- - r--,-
38
><.
RBI71
.lU to
fl:J!\
lA303
Ie... FDlVlelaln FDR Cl-7
M303/K8411
140
In_' Switch Can.",1
RB301
J
TN. 0 -15, In .., 0-15 -;I 000/
TN. C',-IS, Inve,' 0-15', loOO/
41
42
143
Addltlan.1
eo"y
AA302
44
SIx Canoctlan 8- 1112-15
45
Se. ea..v Latch
...
AA402
Se. Candltlan Cod. Lat,h..
IMA401
K8411
47
AlI"olnh
48
All' •• SAR
i
4"
50
Data Switch •• 00 Re.
' K8402
51
00 Reo
52
I/O DI••I•• Add.... Ou.
53
Allow S"....
'0 Add.... Bu.
KA541
IS......
M. ..slliS'
-"
OE
OE
~I
ALU Can"ol G...
r----
l==
(m",1 SE "S .""".)
BAI02
Sen......./CTRL _be
56
....
UU
57
I/O Bu.
'0 FDR
'SUCh
BAI03
-
-
-
58
..s2..
60
61
62
lM.
I ..
I 65
I 66
Ii7
So. ALI , T... Latch
So._... Chock
69
So. lSA Check
CC221
110
So. Mod Check
CCIOI
171
Sot SU Check
CCI02
In
So. AW Check
173
So. Bus Check
'74
So. SAR Check
So.
100 Cheok
75
function ,ignol'l 6Cycl. I21J
----
I CCI21
68
!
~
I CCI22
1\
(
)Any ,h.,k
CCIOI
.J
Cycl. _
- Is:
" Do not care " sIgna
aCyele c::::J
• Diagram 5-27. Shift Left/Right and Move (OX) (Part 2 of 2)
Cycle-=::J
(0~732A)
-
I
y~
"""""""
-...
--.....
2020 ~ 50,000 FEMDM Vol 2
~
~
""=
.""",.",
(8/69)
--
-----
~
-...
CY' ,0
0' ne~'
2
0
12
10
,;><... ,;><...
37
,39
Shift Right
by,
Shift Left
,
>< ><
><
X
8
4
2
0
><.
>< X >< X
><
SlM
Microinstruction Layout
Example: Shift right by 4
The 'from reg' is shifted left
or right 05 specified in the shift
amount field (bits 5, 6, 7 of the
o
I 1 I2 I3 I4
microinstruction), The shift
result is stored into the core
storage holfword addressed by the
'to reg'. The 'from reg' remoins
unchanged.
LS reg 3
I
4
:
3
,
2
:
9
9
2
5
I6 I7
8
I9
Shift
Op Code
To reg
1'0 1"
To Reg
0
1
11
1
121131'4115
From Reg
I
o
S'M
SlM
0
I
S'M
c : D
LS reg 4
FF
Set to zero _ _ _ _ _,
Addressed he Ifword
after execution
INST
MNEV
OPERANDS
STATEMENTS ACCORDING TO STAN"DA.RD C:B O_I046_XXX ~---"~----l
90B4
SLIv,
31,4,0
HW(R3)*=SLO R4
XD
Note: For "Do not care" functions
refer to timing chart below.
CORE STORAGE ----+
"Do not care" signals:
Ll. Cy c I e c::::==:J
Cycle -=:J
Store halfword
into position
Read out and
regenerate microinstruction
I
addressed by
~toregl
-----
I
I
I
SlM (0-6)
SRM (8-E)
I
I
I
I
SU
TD'
8 shiff
AlU
SlM
SlM
SlM
SlM
SlM
SlM
OE
o
o
Invert sw
0
0
I
0
0
0
0
iTo""Re;- -
S'M
S'M
S'M
S'M
S'M
i
f- c.J
(LS reg 3)
I
L4- 3
I
[sA'
t - .,
I
L8_0 -L0 _ 2
J
I
Functions performed during cycle time are shoWl'1 by full lines cnd functions performed during 6. cycle time are shown by dotted lines.
-Piagram 5,;1?
Shift .wt/Right alJ..\i Move (XJ:l.L(Part 1 o.l.2l
(O~3)
2C20L50.Ol.l.Il.FEMDM~[
2
is/6.\Il
I
I
~
~
10
000
001
010
100
101
I
I
I
~
~
--
-
Name
INa
.5.'"" -,,,,1' Req''''
2.
--':s.C,,,,~,
2
4
-'-
L;o"
T3
lB
KASTl
PL ZOO< Go"
N",/",ceo' . " may d; 'fee
New/C,,,,", PL
CE LS S"ed
T4
T6
I CC222
-
T8
---
I LA103
LS N,w PL Zoo< Go"
;
Cy",O
T7
-'-
,
""0
ALD"
.~
-==
:y'"
T6
-'4
lB
T2
. lB,
T4
6
F;xed X-Add,,,,
7
"'2
'To Rea' Se',d
9
W
11
12
I LA402
'F,am Reg' S,'ed
~411
=
LS 'a MAR
;'0
KB401
FDR
13
LS 'a lOR
14
MAR '0 LS
15
Se' All I('/O',~-,,,-,S.
16
LS Wd',
LA302/313
,.
S,t Add,." Ch"k
RA501
19
"am ,G,
RA502
20
,oc,.m,", by 1
RA402
21
'oaem,"' by 2
I RA403
-
1=>:=
KB411
LS 'a SAR
LA702-712
,--
C=::-c::
17
-
~
"'==
=-
r--
---
---
---
-===
~401
22
Deccemeo' by
23
by 2.
LRA4.D1.
'"
Pee"ot Mod-SAR-'oh Ch,ck I KA51'
12'
-
f.--Lr--
I
125
I 26
J>.-","' SOo'0ge U"
I MM02
I 27
SDR '0 'oh
IMM01
i 28
SDR 'a 01' Reg
I K.'02
l1J.
30
'0 lOR
SDR
......
K8402
"0'
RB162
31
E;qh, Sh;n Coo
32
Sh;ft by 2 a 4
RB161
33
No Sh;n
RB162
34
T", Pack.d By" a S;go
RA502
35
Nama!;ze S;qo Ac!;"
36
5"'0'."
Shift Right
Shift Left
by:
by:
---
12
,
r-- - - -i - - -
-
I - f--
r--0f?--
I-- -
- - r--
-
-
- -- - -
X
8
10
X X
>< ><
X
4
2
°
X X
X
RB171
_37
3B
I
'0 FDR
<303
39
Re", FDR/Reta;o
40
,,,"" Sw;'ch Coo',o'
R8301
"0'
AA301
FOR 0-7
<303/K'411
Teo, 0 ,15,
;0""; 0-15 =/t'000/
Teo. 0-:,5, ;""t 0-15
=/e 100/
41
42
L43
W Coo
Go'.
Add;!;=a' eo"y
S;x Ca,.c!;oo
45
I
OE
10E
AA302
11/12-1:
Co, • Latch
AM02
5" Cood;!;oo Cod, La'ch"
_47
4B
ALU
'0 'oh
D·
MA401
ALU to SAR
K84l1
00'0 Sw;,ch '0 01' Reg
'0 Add,,,, .,"
KA541
,0-
_49
50
K8402
51
00 R."
52
I/O D;,p'oy Add,,,, Out
53
Allow S',obe
55
S.ru. R."tlCTRL Steob,
56
P'"e", IU am I SU Ch"k
57
1/0'e
SENS
Sic
,--
t---
(Dl,p' SENS ;'cab.)
BAI02
......
-
-
BA103
,FDR
58
59
60
61
62
63
64
66
67
Set,
I Te.t Latch
I CC121
Set Piace.. Ch.ck
I CC122
69
Set SA Check
I CC221
70
Set Mod Check
I CC101
71
Set SU Check
.~
..R __Se' ALU
~
\
(el02
>Aoyh"k
Check
'0> Check
73
Set
74
Set SAR Check
75
Set 'oh Check
Function signals: 6Cycle tz;ZI
CClOl
Cycle _
"Do not core" slgno1s:
.~Cycle
t:::J
• Diagram 5-28. Shift Left/Right and Move (XD) (Part 2 of 2)
Cycle-=::l
(03733A)
-......
!~
=
~
---
~
~
"
......
2020 ~ 50,000 FEMDM Vol 2
---
..
--
~
(8/69)
--
....I.1.i:..
--
>l8_
r.-
Cyc ,0 of
o.~t
;
;
12
10
8
>< X ><
>< X
X
4
2
>< ><
0
><
The halfword read out by the 'from reg'
is shifted left or right as specified in
the shift-amount fields (bits 5, 6, 7 of
the microinstruction). The shift result
h stored into the halfword addressed by
'to reg'.
Microinstruction Layout
10
Op Code
LS ,eg 4 1.:..,
.... -1-2=-+1..:;3--,-:-,-4...J
From reg
L
Shift
To Reg
11
12
13
14
From Re
15
SLM
SRM
_ _ _ Reod out oddressed holfwo,-d-
The halfword addressed by 'from reg'
remains unchanged. 'From reg' and 'to
reg' may be the same LS register (same
address) or both registers may contain the
same address.
It
Shift right by 2 bits
Set to zero
1 1 1 1 001 1
LS
To 'reg'-r--,-r-:---r-.,-,
'eg 3 1 4 : 3 2 : 2
I
L _
INST
90BC
~L":C.:..L:"::':"L.::--'-"-'
execution I
Read out addressed half wOld
Before
SLM
OPERANDS
STATEMENTS ACCORDING T'J .ST.\NDARD CEE O_I046_XXX
31,41,0
HW(R3)~"'SLO
FF
xx
A
After execution
HW(R4)
Note: For "Do not care" functions
refer to timing chart below.
CORE STORAGE -
Read out and
"Do not care" signals:
.6.Cycle c::::::J
Cycle -=:J
Reod o"t and
regenerate
-:-1 'fo~erand'
r-i-~
ISDR
I
I
I-----j
L.P~DL.PLD1.J
SLM (0-6)
SRM (8-Fl
I
I
SU
TDR
8 shift
ALU
Invert sw
I
o
0
0
0
0
0
1 0
0
I
ilLS reg 4\
I
~2-f~.J
I
I
I
I
I
I
I
r-l-l
15AR
I
L! .2 .1. 3_
Functions performed during cycle time are shown by full lines and functions performed during,:, cycle time are shown by dotted lines.
~agram ~
Shift~RiQht ~ove (~Pnrt 1 ......
!nI"IIl)
f"To R: g- - I
I
I
l.!. .1 +'_'.J
I
I
I
4...J
I
I
~
~
000
001
SRM
SRM
SRM
SRM
rFr~ R;'g -
I
SLM
SLM
SLM
SLM
SIM
SLM
\LS reg 31
4
8
10
0' 0
I 00
10'
I
I
I
>(
?t
-
......
INo
Nome
I
5.... T,oo Rea • ." Lin••
2
LS New PL Zone Go.e
3
,
LS C.""n' PL Zon. Go••
5
CEL~I.~
A L O " T•
-
T6
T5
T7
--
,
,.
ey,
I LAI03
-----
KASII
N."/,.,,,... L's may dl Fre,
New/C.".n' PL
Wd ..
Cyd.
T6
T'
0.--
,.
Cyd.3
-
-18
TI
T'
I CC222
6
7
.,.... y-""......
L... 12
B
'T. ".' Sel."
,AMI>
•
' ••-
LA.II
' - ' SeIK'
1,0
L••• 'AO
III
LS •• MAR
I ..
,e • enD
113
LS to TOtt
KB411
17
..""'''"
IB I Se.......... a-k
RASOI
L.
Wo-'..
,,_hG.
_.,
I RA502
I.n
121
In"....n. by 2
I RA4D3
I ••
n.
II.
"""""""
LA702-712
115 I Se. ALU (VO lusl to LS
I'A
~
KB401
II • . MAO •• LS
~
f-!-
.--
~
--
-=-
-
f--L....,:
~
lor-~
'===
==
----
~
f---
~
I---
~
~
r---
-
~
-----
----
-----
lor--
UIl?
_.,
UlI'
I " I 1>00••• _ . bv'
I
I RM02
I " ' "_•• , ......._.AII..'.h Check I KASII
I ..
I.A
Pnuen. 51"""", Use
I_
1.7
so. I. Inh
IMA40I
I .. ISORtoo....
I KBI02
I ..
' 30
I KB402
SDR
I 31
132
I.
TDR
Elahl Shlfl Con".1
I RBI62
Shlfl bv 2 " .
I ••IAI
i ..,
N.chlll
I",
T...
........
I RBI62
P~k.d
.... '" SIan
135
!
N_all .. Sian Actluo
I ...
1
. . ._ _
~-
0-l,1
--f--
RAS02
-
-
o:l5 0-15'
~
I - I-- - f - -
-
-
......
---
12
"hlf.1 ;fl 0' ,IOh'
.= X
leli7riOIit .20"
I-- -
O.,S
~-
I-- - f - -
I-- -
-
~-
-
-
-
Twe 0 :15,lnve, :O-IS
=/0000/
10
-
ALU 10 FOtt
.... , FORl.... ln FOR 0-7
140
In••1 Switch Conl...1
I AA303
I AA303iKB411
I R8301
True ( '~IS,;nY. to-IS
Tw, ,:0-15,lm ~,. O-IS =10000/
=I \1000/
I ••
..
A'
,r_w. I "'.,.
!
Additional Cony
I
1m
171
Selr-a-k
... L<
r:5<
B
10
IX X
X
X
I-
r_•• ,,"" B_II/12_15
.
.... .....
.,
IAAlOI
2
>< X
141
143
•
B
I'>< r><
1..171
139
by,
by,
137
138
Shift Right
Shift Left
><
X
X
,
><
2
0
X
r:5<
Microinstruction La out
10
o
The 'from reg' is moved into
The 'from reg' remains
'to reg'.
c
unchanged. Address check and the
increment/decrement specification
of operand' addresses are ignored.
D
A
I
Code
To reg
I
'.g 4
9
:
8
I
7
:
6
before execution
INST
MNEM
OPERANDS
A441
MVH
4.1
12
13
14
15
MVH
F'om Reg
0
'goocod
lS
11
To Reg
AC
~
L
DD
~
STATEMENTS ACCORDING TO STANDARD CEB O_I046_XXX
fF
DO
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
~Cycle c:::J
Cycle -=:J
Read out and
regenerate micro-
CORE STORAGE -
-
-
-
-
-
-
-
-
-
instruction
-1- - 1
I
.--.1_,
I SDR
I
h----'
LA_ 4 .t4 _'...J
SU
AlU
Invertsw
1T::o.:~-,
(LS reg J)
FvnctiofU performed during cycle time a~ shown
~iagram~.
full lines and fu~ctions performed during .0. cycle time are shown
Mov~lfword ~ (Part 1~)
(~5)
lines •
..il.20 ~ 50~ FEMD~I 2
(8~)
(lS '.9 4)
No
Nome
AlD
1
Sen.. T,op Reque.' Une.
LAl03
2
lS New Pl Zone Gole
KA511
3
lS Current Pl Zone Go.e
4
New/Cu,,.nl Pl
5
CE lS Sele"
•
I
10
-
I~
---
I
I.
I)
TO
I CC222
--
6
7
Fixed X- 'd FDR
--
""
>.402
IlA411
-
~
KB411
"'==
KB401
13
lS.o TDR
14
MAR 10 lS
15
Se. AlU 1
R8301
TNe 0 15,
,,,",i 0-15 ~ /Iiooo/
41
42
AlU Con"ol Go,"
'A301
143
Addillonol eorry
AA302
OE
Six C..,.,lIan 8- 1/12-15
45
Set Carry lal,h
46
Se. Condillon Code lot,,,",
47
Alii '0 Inh
MA401
48
AlII.o SM
K8411
50
Do'o Swil,h '0 Op Rea
KB402
51
()p R.g 10 Add"," Bu,
KA541
52
I/O OI,.lav ,'ddte.. Qui
AA402
49
53
M.
r--
Allow Sitobe
~S
IS'tobe
55
Sen......t/CTRl Stn>be
56
Pr
57
1/0 .... ,0 FOR
'ALli
I Sli
~h
(DI'pl SE"S ,.tobe)
BAI02
--
.......
BAl03
r--
58
59
60
61
62
63
64
65
----
66
67
So , AU IT. ,latch
I CCI21
68
Set Pr..... Check
69
Set LSA Check
I CCI22
I CC221
:70
171
,Mod Chock
Set SU Cho,k
~
.'\.
CCIOI
CCI02
n
Set AW Check
>
,73
Set Bu, Check
I
7'
Set SM Check
75
Se. Inh Cho,k
function signall: 4Cycle r;:a
An" ,h.,k
I...-.
CCIOI
j
Cycl._
--
"Do not care" signals: aCyel. c::j
Diagram 5-30. Move Halfword (DO) (Part 2 of 2)
Cycle-=::J
(03735A)
~
-...
-
2020 ~ 50,000 FEMDM Vol 2
~
C~ 1.0 ofn.x"
(8/69)
I
T3
T4
T5
T6
T8
T2
Microinstruction La out
LS ceg 1 I 1 : 2
The halfword read out by the
before execution
'from reg' is mOved Into 'to
reg'.
I
2
3
Op Code
4 I
3
L. _. -r-Read out addressed hOlfword
+k
Modify
or -2
(depends in bi t 6)
n
If the AC bit (instruction bit
is on, an address check occurs
when the 'from reg' address is
outside customer area or not on
halfword boundary (not even). The
'from reg' address Is incremerltedby 2 (instruction bit 6 on) or decremented by 2 (instruction bit 6 off).
lS reg I
after execution
11
:
;
~ I! : ~ I:::
LSceg419:sI7;.
10
+
-+!A;'lc:D I
Remains unchanged
The 'from oddr' is: incr by 2 if on
deer by 2 If off
"~,I
AC
11
12
To Reg
o
A
13
14
From Reg
15
MVH
1
~ LDX~
If on, the 'from addr' is checked
that it is not outside customer area
before execution
after execution
If bit 7 of the instruction is on, address checking is performed.
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O.1046_xXX
A749
MVH
4,lI.INC.AC
R4.= HW(Rl.AC.+2)
FF
1--::----1
DX
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
~ Cycl e c:::::J
Cycle -=:l
Read out and
regenerate microinstruction
CORE STORAGE -
-
-
-
- -
-
-, -
- - -
-
-
Read out and
regenerate
-
-
-
-
-1 __:.Jrom..,Sl8~'
I
1
1
I
I
1
r -.J--,
SDR
I
r-i.- 1
I SDR
1 - ,- , - - - - - - '
!----
L.A_B ...C_DJ
L~_7..J!:!'"
SU
D
ALU
[nvertsw
(LS "'. 4)
I
1
I
;sARLl
L'!..9.L...°_~
during cycle time are 1hown by full lines and functions
Diagram 5-31. Move Halfword (DX) (Part 1 of 2)
during a cycle time are shown by dotted lines.
• (03736)
2020 2 50,000 FEMDM Vol 2
(8/69)
...
,
ALD
Nome
INa
.T4
~ I Sen.e T,op Req...t Uno.
LS Now PL Zone Gate
2
T6
T5
T7
KASII
I Now/Cu"ent PL
N ,w/current L's may me,
5 I CE LS Select
Cv< ;0
1'4
T5
---
LAI03
3 I LS Current PL Zone Gote
4
13
T2
T8
---
-------
Cycle
T6
I CC222
6
7 I FI.ed X-Add,e..
lA412
B I 'To Rea' Sel~t
1LA402
9 I'M-am Req' Select
110
LS to SAR
111
LS to MAR
112
LS to FOR
113
LS to TOR
lIS I Set ALU
..,."".",
KB411
~
~
KB401
............
............
............
I"",.".",
I-
I..-~
-----
LA702-712
114 I MAR to LS
116
I..--
lMIi
---
~
I---l
I.r--
evo Bu.) to LS
---
~
f--
LS Write
LA302i:113
~1
lIB I Set Add,... Chock
I RASOI
IJ? IBronc~ Go
I RAS02
120
I.c.eme.t bv
121
In"ement by 2
RA403
122
Dec~ment
RMO'
123
Dec......t bv 2
RA402
I",."".",
L........... lAC bHo
IRAA02
12. . P....nt Mod.sAR.tnh Chack
-----
i--
~
,
'f-.wemen,
KASII
125
L26
I "'event 5",,_ U..
'MA402
127 ' SOR to I.h
I 28
---
MA401
SDR to 00 Rea
K8102
129
130 . SDR to TOR
31
I KB402
33
~35
36
0-15 ,0-15
---
N,;! !illtB'
I RBI61
I RBI62
32 ' Shlftbv2 ... 4
34
~
~' 'lflJ!!L f-- - l -
I RBI62
Eight Shift Con"ol
o:l5 ;0:]5
> Shift
,hHtB
0-
RAS02
Te.t Pocked Byte ... Sign
N...mallze Sian Active
' RB171
Su.......
I 37
3B
AlU to FOR
39
.... t FDRiReta'n FOR 0-7
. AA303IKB4I·
AA303
40
Inv"'t Switch Contml
' R8301
42
ALU Con"ol Gat.
,AA301
43
Additional Ca"y
AA302
~~ O-i5.-;.iJ 0001
T,uel-15, Inve to-15', ~OOO/
41
44
51. Correction B- 1111-15
45
Set Corry Latch
46
Set Condlt'on Code late he.
47
AlU to Inh
IMA401
4B
ALU to SAR
I KB411
Dato Switch to 00 Rea
I KB402
'QE
loe
AA402
49
50
00 Reo to ......... Bu.
I 52
VO DI.play Addre.. Out
153
Allow SIAny check
Set SAl! Check
CCIOI
rza
Cycle_
.
00 not care " 5lgnals: aCyele c::J
• Diagram 5-31. Move Halfword (OX) (Part 2 of 2)
Cycle IE:::J
(03736A)
------
2020 z: 50,000 FEMDM Vol 2
I
I.r-y~
............
~
Set Bu, Check
75 Set Inh Check
Function Slgnol.: ACyel.
~
~
CCI02
In I Set A 'Check
173
I..--
I CCI21
6B
I",."".",
(8/69)
I...
------
---....
~
-
Cycle 0 :of .ext ,
T8
T8
LS ...
41
~
before execution
The 'from reg' is moved into
the core storage halfword addressed
by the 'to reg'. The 'from reg'
remoins unchanged. If the AC bit
(instruction bit 7) is on, an
address check occurs when the
'to reg' address is outside
customer area or not on halfword
boundary (not even).
Microinstruction Layout
I2 : 2 I
L_ ~
4 : 3
~"'-C-'-:-c""I'-c':-c'l
Read out addressed halfword - before execution I
ce. 41 : : ;
after execution
1; :
The 'to reg' address is incremented by 2 (instruction bit 6 on)
or decremented by 2 (instruction
bit 6 off).
~
I:
10
To Reg
MVH
11
12
13
14
15
If on the 'to addr' is checked
that it is not outsIde customer area
after execution L-"A,--,--,--l..-"'C~!!..J
c:ol
LS ... l ! A : '
7
AC
The 'to oddr' is: incr by 2 if on
decr by 2 if off
I
...
' -:-r-:-+."-..,....,,.";'
(depends ;n bi t 6)
6
_
A
I
Modify +2 or -2
LS
Op Code
remoins unchanged
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O_1046_XXX
ASCI
MVH
4I,I.DEC.AC
HW{R4.AC •• Z)*=Rl
FF
If bit 7 of the instruction is on, address checking is performed
xo
Note: For "Do not care" functions
refer to timing chart below.
CORE STORAGE - - - +
-
-
-
-
-
-
-
-
-
Read out and
regenerate mi croinstruction
-1-
-
Store halfword
into position
addressed by
Read out
-'il'
-
I
I
I
I
~reg'
r---t---,
:so'.!---1>-r-----!
I SDR
I
I
I
•L. (_ _ _
C l... (_ _('
:J
-+--I
I
I
I
SU
ALU
Invertsw
(LSregT)
¥INSI)
r------l
liAR
I
•
t--1
I
--t--_JI
,
I
,,
r
r-,
r---- -~--- .....
I
r--- I
I
I
---,
SAR
I
..
I
~~_~ ~_~J
time are shown by full lines and' functions performed during a cycle time are shown by dotted lines.
Diagram 5-32. Move Halfword (XD) (Pat! 1 of 2)
,
~
I -2 !----...l
L_ ......
I
L.~_~.l...0__2_~
Functions
To Reg
• (03737)
2020 ~ 50,000 FEMDM Vol 2
~,
I
I 4 3 2 4 I
L
__ ~ ___ J
I __
4 3., ___
2 2 II
L
,
I
I
I
, ___t. __ ,
I SAR
,
I
I
j'
8 0 0 2
L.._
, ______
r------,
I To Reg
(8/69)
A( I
L_ .....
I
(LS reg 4)
"Do not care" signals:
.-:1Cycle C:=:J
Cycle -=::J
>ad
ALD
Name
INo
.T4·
I
S.n'e T,ap ' •• ,e,' Un..
2
LS New PL Zane Ga'e
3
LS C,,,en' PL Zane Ga"
4
New/C,,,en' P-L
5
CE LS Selec.
--
Cyc"O
T8
T6
T3
T4
T5
T6
T8
--
I LAI03
KAS11
Ne~/c,,,en' 'L', mav dl ff"
-==
,
T4
Cvc'
T5
T6
--17
T8
T4
T5
T6-
TS
17
TS
T2
I CC222
6
7
Fl ••• X_A......
8
'Ta Rea' Se'ed
9
'F'am 'ea' Sel.c'
110
12
LA411
6"""."
KB411
; 'a
""'"'"""
III I LS'a MA'
112
KB401
LS.o FD'
113 I LS.o TO'
---
W02-712
114 I MA'to LS
I.
I Set ALU 11/0 B"I ta LS
116 I LS Wdte
I LA302/313
1.7
I ... ~h"
1--2-
~
I""""""
----
-==
==
i---
lor--
~
-==
lor--
""'"'"""
~ Ar. bl.
'AdO?
If Inmment
'fdwemen.
1"'-402
I 23
Dwemen. bv 2
124
P"vent Mod_SA'_I.h Check 1.A5 11
125
I
MA402
I 26
"'event S'..-ao. U..
I 27
SD'.olnh
MA401
I ,"
50"0 D. Re.
K"I02
----
129
I 30
SO, t. TD'
I KB402
I 31
E1aht Shift Con",,1
I.BI62
I 32
ShIft bv 2
10"61
I"
I,.
T... Packed Bvt.
~
~
~ :e- -
lor--
:15
1.8162
N.Shlft
~
Sla.
I 35
Nonnollze SIan Actlve
136
S, ••'e"
,
N•• ,h;f,S
'A502
1.8171
137
AL Ita FD.
I AA3D.1
139
..... FDRI .. ",I. FD. 0_7
I AA3n.1IKRAII
I 40
I...,. Switch Cant,al
1 ••101
ALU Con"ol Ga••
IAAJOI
3D
hoe '-15, Inv' to-15=. :.0000/
Tru.O :15, Inv", i 0-15 = j\ iooo/
I 41
42
143
44
AS
46
I 47
Addltlonal Co".
DE
DE
AA302
51. C.,.,ectlon 8-11/12-15
• r.~ .t.h
AA402
s.t Condltl .. eM. I ntc,,"..
0-
IMA401
ALU'a Inh
.0-1
I KB411
Jta SAR
4B
49
I 50
Da'a SwItch ta "" Rea
I 3'-11.....-'--'2'-'1
=r:
before execution
12
A
-
+
6
II
Code
~ - - _. Read out addressed halfword - - - -.,j
c : C
Modify + or·2
Before execution
-".-'-"-L-':....L"':::'...J
(depends n bit 6)
I
INST
!-I
A5C9
A7BD
I
A
C
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB
MVH
4I,lI,DEC,AC
3I.5I,me. AC
HW(R4.AC •• Z)*=HW(RI,AC,.Z)
HW(R.3.AC.+Z. UNTIL Rl.LT, O}.",aw(R5,AC.+Z)
_H
0_1046~XXX
FF
D
Note: For "Do not care" functions
refer to timing chart below.
Read out and
regenerate microinstruction
CORE STORAGE -
-
-
- - -
-
-
- - -,:,
-
Read out and
regenerate
'from operand'
-----j-I -
-
,I
-
-
--
-TT--
I
r,---J
I A
5 C
9-'I
L.
___
___
-:-
r---t---,
SDR
I
I
'
L ___ J..C
___
ICC
C JII
L~_B_L'-_~.J
~
Store halfword
into position
addressed by
'to reg'
Read out
'to operand'
- -- -
,iSDR-'---,,,
iSDR-L--l
,
-- -
"Do not care" signals:
Ll.Cycle c:::J
Cycle -=:J
I
r
I
DR D
ABC
D
II
II : I : I ~ I D
SU
I
,--
D
C
B
I
I-
~
ALU
IA
"-
Invert sw
(lS reg 1)
II
r------,
From Reg
•
rFr;m-~g- -1
+___
I
I
I
LI ___
1 2 3 .4 JI
riA'R----i
I
,
:
,
J
I
L !_~.L~_~
r ___ t
,
I
SAR
No
,~~----------~C
No action
I
0 0 0 8
,,i
,,,
,,
I
Ve.
J
i
r+;w,
L
No action
,...-,
I
r-'
I
Decrement Carry 0
forces Ale end op
time are shown by fuJIITn •• and functions- performed durina .6. cycle time are shown by dotted lines.
202O~50,OOO FEMDM Vol 2
r-2"t---..J,
I
(8/69)
J
,
I..
• -4___
3 L.:2_ _2 .JI
(NSI)
I
L!!-~tQ.-~J
Ii
I
1 __ -
Ve.
J
I
r---'---,
SAR
I
L._.J
I
I
,I,
L_.J
rL ________ ... AC.
L_..1
___
3 4 ..1I
:
,,
,
I
,,
,
,,
.J
:
L~_~-f!-~J
,
___
1 2..1
fI liAR
r-------,I
:
r---t--,
,
I MAR
r--- Y---,
IL.
~~_~ ~_2J
:
:I
I---------~AC
SAR
,rTo-Re~---i,
~~-~t~-~J
1
.J__ _
I
(03738A)
(LS,.. 4)
L---t--- J
I
I
I
,ifo-Reg-- -;,
I
,
:
,
0
0
: ilSRegl--:
,,
•
Diagram 5-33. Move Halfword (XX, AL,C) (Part 1 of,2)
I
0
I0
• ___
I 2 : 3___
4 JI
L.
I
L
I 8___
0 J.. 0___
2 .&I
Functions
I
L--~t---J
r---L--,
,I MAR •
I
___ ,
1 2 3 2
,,
,
:,
,J,
:I
r--i--I MAR
I
:,
(NSI)
1--1
I 8 0 0 2 I
L
__ -t- __ .J
I
0 0
0 0
L_.J
No action
Nom,
INo
ALD
I
Seo .. T,op Reque" Uo"
2
LS Now PL Zoo. Got,
3
LS Curr.ot PL Zooe Got,
4
New/Cu",ot PL
~14
W~
Wdte'
-"""'-
Cyd,
15
T8
16
T2
14
Cyd,3
15
16
-
I LAI03
----
KA511
L', may ,II..
Ne'
5 I CE LS S,l'ct
-==
------
14
T5
T6
T8
CC222
6
~
X~d,."
F;xed
8
'To Rea' Sel.ct
9
'F,am Reg' Sel,ct
l!o
LS to SAR
111
LS to MAR
112
ito FDR
-
<412
LM02
<411
===
KB4l1
KB40l
==
------
113 I LS to TDR
'0 LS
114 I MAR
LA702-712
r---
~ LSet ALU,JiLQBu.) to LS
116
LS Wdt,
~
LA302/313
, 17
II
I S.t Add,,,, Chock
AS02
-2!J
10c"m,"U,yJ ,
<402
21
I,a-.meo' by 2
~
P..v."
~
--- -==
""""=
"'==
~
1=
"'==
-==
~ I AC b;,
l....j.
""=
DO
---
"'==
----
I ALC
1=
---
1 =lAC b;t,o, I
-
,LC-eod op
---
---
I,
I RMOI
,.,Li>Yl
, Dog...
24
~
""=
~
<403
Doc"meoU",
~,
I Not AlC
"==
H;.h/lo, , hallwo,d booodo,y
ASOI
119 I S.anch G
-=
......
~
d,.",.,.;
IiIr::=
~
Mod·~-Ioh
Check I KASI'
~
26
p.,v'"t St",... U..
I MA402
27
SDR to loh
IMA4eck
Function signals: 6Cyele &m
......
~
~
1=
11'8
~ :heck
au. Check
eyel. _
~
r--
I CCI21
Icem
"Do not care" signals: dCycle c::J
• Diagram 5-33. Move Halfword (XX, ALe) (Part 2 of 2)
Cycle-=:J
(03738A)
2020
~
---
50,000 FEMDM Vol 2
-....
"'==
(8/69)
"-
---
~
,r
............
"""=
...
--.....
~
~
....
lC eod
--
~
ITS_
'_18_
~
'-==
~
......
0.-
-
Cycl.O,;foo~
Cycle I. ;1 ALC noy end op (',epe,;,;on)
-
MVB
From reg
I
I
LS ceg 1
A
:
remains unchanged
The low-order byte of the 'from
reg' is moved into the low-order
byte of the 'to reg'.
'From reg' and high-order byte of
'to reg' remain unchanged.
Address check and increment/
decrement specification of operand
addresses are ignored.
:
~L_ _ _ _ _ _ _ _ _ _ _ _ _ _~
To reg
LS ceg 4
I
D
:
C
B
:
A
I
before execution ' -_ _ _ _ _ _ _ _ _ _ _- ,
LS reg 4
JNST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEE O_1046_XXX
A!>41
MVB
4,1
R4+=R4. 0_7/RI. 8_15
FF
DD
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
t.Cycle [===:J
Cycle -=:J
Read out and
regenerate micro-
CORE STORAGE -
5U
ALU
Invert sw
(LS reg 4)
I
I
I
I
r--t-.,
: ,SAR
I
L§....9..l...°_~J
Functions performed during cycle time are shown by full lines and functions performed during'" cycle time are shown by dotted lines.
Diagram 5-34. Move Byte (DD) (Part 1 of 2)
(03i'39)
20202: 50,000 FEMDM Vol 2
(8/69)
.
Write
INo
""me
I I Se... T.ap
AlD
.T4
"que" Uno.
T6
T5
I 2 I l5 New Pl Zone Ga"
I..--
KASll
3 I lS Current Pl Zan. Gate
4
12
18
ILAI03
......
T3
New/Current Pl
X-M,j,e..
....,
·F.am Reg' Select
lA411
110
LS ta S!I,R,
KB411
111
LS taMAR
112
l5 ta FOR
113
l5 to TOR
I....-
==
13
......
I....-
'===
I....-
I..--
KB4DI
I....W02-712
114
MAR t. l5
115
I Set AL J (Va
116
7
lA412
I 'Ta .... Select
9
T6
I CC222
6
8
T4
,
5 I CE lS Select
.7 I FIxed
Cyd.O
l5 W,lt.
......
>---
~
Bu.) 10
'-302/313
117
118
Set Add..... Chock
RASOI
119
.....c,Go
RAS02
120
Inc.....nt by I
M02
21
Inc.....nt by2
1A403
22
Oo",....nt
23
Doc.....nt by 2
I RA402
24
P..vent Mod-sAl-lnh Chock
I KAS11
26
_.ntSt..... U..
l_
27
SDR to Inh
IMA401
by
.....
i----
'--
""'I
25
128
SDRIoO. . . .
it; 0-1
l.....-
K8102
I 29
130
31
SDR to TDR
I KB402
Eight SMIt Con".1
I R8162
SMIt by 2 '"
I R8161
33
NoSMIt
I R8162
34
T••t Pocked 1M. '" SIan
35
Nannollz. SIgn ActlYe
36
50_
132
~
~
- -I-
-
hHI'
RA502
I R8171
37
38
ALU to FOR
1AA303
39
Re.. t FDRI .... ln FOR 0-7
40
In••rt Switch Con...1
I AA303/KB41
I RB301
ALU Con"ol Gat.
IAA30I
T.u. O-Il, love.' a-15 = /t", 00/
141
42
[43
44
,~
46
ICE
AA302
AddItional Carry
SIx Corr.ctlon 8-11112-15
AM02
Set Carry Latch
Set Condition Code Lotc,,",
MA401
I 47
ALU t. Inh
148
ALU to SAl
I KB411
Iso
Data SwItch to 00 ...
I KB402
151
Op ... to Add.... Bu.
149
KM41
I~
I--
I 52 Va 01",1 . . Ad,ke.. Out
153
LM
Allow S"ob
,IStn>bo
, SENS
lo000o-
1(01 ••1 SE NS .trobel lo000o-
BAI02
Iss I Se......../CTRLSh"obe
56
57
I~
«lIr<
BAI03
I/O Bu. to FOR
,58
159
L@
161
~
163
164
65
L66
L67 I Se' ALU T••• Latch
I CCI21
68 I So._Chedo
I CCI22
69
Set
'Chock
I CC221
70
So
leh
I CC101
71
Sot SU Chock
: 72
.......
~
\
1
I
CCI02
So. "'Chock
74
So. SAl Chock
CCIOI
J
75- Sot Inh Chock
Function
ligna I.:
.6.Cycl. E3
Cycle _
I
I
I.....-
.. Do not care...sIgnalS! .6.Cycle 0
• Diagram 5-34. tv'ove Byte (DO) (Part 2 of 2)
(03739A)
Cycle-=:J
~
'--
-....
iI.i..
·"T8..ii
>Any:chk
Set AW Chock
73
......
~
-
2020 ~ 50,000 FEMDM Vol 2
Cycle 0 ~f next
(8/69)
T4
T5
T6
18
T6
17
Microj~struction Layout
LS ... 1
The byte addressed by the
'from reg' is moved into the
law-arder byte of the 'to reg'.
The 'from' byte and the high-order
byte of 'to reg' remain unchanged.
If the AC bit (instruction bit 7) is
on, an address check occurs when
the 'from reg' address is outside
customer area.
I4
: 3
before execution
I
2 : 1
T
I
L _ -1-
Op Code
Read out addres~d byte -
Modify +1 or _I
Remains unchanged
LS ... 1
14 : ~
after execution
10
To Reg
11
I'
13 14 15
From Reg
MV.
1
OX
(depends in bit 6)
The 'from reg' address is incremented by 1 (instruction bit 6 on)
or decremented by 1 (instruction
bit6 off)
7
AC
A
- "- ~
-
+
--.-J
If on, the 'from'addr is checked
thot it is not outside customer area
I' :~ IT
lS reg 4 A B
after execution
LS,e.4IA;.lc;ol
before execution
2
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O_1046_XXX
AA49
MVB
4.11, mc
R4*=R4.0_7!BY(RI.+l)
FF
OX
Note: For "Do not care" functions
refer to timing chart beiow.
-----!l--
Read out and
regenerote microinstruction
CORE STORAGE -----
"Do not care" signals:
t>.Cycle r:::::::::J
Cycle -=:J
Read out and
regenerate
'from operand'
----------1--I
I
I
r-
r-j-- ,
I SDR
_t..._,
f-----1
L~!..2_~
lSD'
L~~I!.?.J
I
SU
ALU
0'
A
Invert sw
rF;;~: 4
L_
,-----,
I
,
I
L~~.!!_~ :
I
I
I
I
I
I
I
rw..!--,
I
L~~11_1~
,
I
r: _i_-,
I
I SAR
,-__ tL------~;.~l
__ ,
L __ J
I
L!J!12 _2J
I SA'
I
L~'!,1_1J
T
SAR 15
Functions perfonned during cycle time are shown by full lines and functions performed during .6. cycle time are shown by dotted lines.
Diagram 5-35. Move Byte (OX) (Part 1 6'1' 2)
(03740)
2020 ~ 50,000 FEMDM Vol 2
(8/69)
i
,!
';4.--"
I
~_
lA'
3
(lSreg 1)
I
(lS reg 4)
AlD
Nom.
INo
I
Son.. T,,'P Req...' Uno.
2
L5 Now Pl Zono Gale
3
L5 Currenl Pl Zon. Gal.
4
N.w/Currenl Pl
5
CE lS Solecl
CC222
LA412
I LAI03
KASll
•
Read
--
,icurronl l'. may, ff••
IZ
I.
TO
7
Fh,.d X-Add....
'To
9
'F.om Rea' Solect
lMll
L5 to SAR
KB411
110
Rea'
111
L5 to MAR
i12
l5 10 'DR
! 13
L5 10 TOR
~
~loL5
·15
Sot AlU
WOO
Sol.cl
-==
~
~
LA702-712
evo Bu.) 10 lS
-
r--
r--
'J§_. lS Writ.
LA302I;113
17
18
.19
Sot Adoh.. Check
RASOI
a.anch Go
RAS02
In....... nl b. I
21
Incnomonlbv2
IRM03
22
Do....monl bv I
IRMOI
23
24
,
""
-
.
T7
T3
==
Cycle
~
TO
~
~
""""'""'"
Tl
T5_
-
==
---- --
r--
-
--
==
--
~ IAcbH,
I
1RM02
20
TO
"""""'"
-===
KB401
T>
---
•
8
-
Cycl.O
,If de ,'''_,
Li!A402
p...,.nl Mad-SAR-Inh Check I KASI'
25
26
p...,.nISI.._U..
27
SOR 10 Inh
28
SOR 10 O.
I MA402
-
MA401
Rea
K8102
29
30
SDR to TOR
31
Eighl Shih Con"ol
. R8162
32
Shift bv 2 ..
I R8161
No Shill
I R8162
33
, 34
KB402
35
N",moU. . Sign Actl.o
Su......
-
lor---
==
0-15
RAS02
T." Pocked Me '" SI.n
36
tl:::~ 'I~ !---:=
I R8171
37
38
ALU 10 FDR
AA303
39
Re.. t FORlRe"'ln FOR 0-7
M3Q3iKB4l'
40
In.o.t Switch Cont.ol
R8301
42
All I Con"ol Gal.
AAlOI
43
Addltlon.1 Corr.
AA302
TN. ~-15, Inveri_ 8-15: ~Ne
TN. 0 ~15, In ... • 8-15 :.
00/
NOOO!
41
44
Six Correction 8-11112-15
45
Set e .."
46
Set Condilion Code lolche.
47
AlU 10 Inh
48
em,
10E
OE
AA402
IMA401
I KB411
110 SAR
49
50
Dal. Swllch 10 00
Rea
I KB402
51
00 Rea 10 i\d10:f11
L-
9
Op Code
-~
Reod out oddresred byte-- -
- before execution I
t
lS''9'\ ~:~ I~!~
)
I+
after execution
11
12
13
14
15
From Reg
The 'to oddr' is; incr by 1 if on
deer by 1 if off
j
Modify +1 or -1
(depends on bit 6)
10
To Reg
A
If on, the 'to addr' is checked
that it is not outside customer area
2
ofter execution
The 'to reg' address is incremented by 1 (instruction bit 6 on)
or decremented by 1 (instruction
bit 6 off).
LS reg I
I
I : 1
2: 2
I
IN.:'::iT
remains unchanged
A9Cl
MVB
OPi:;RANDS
STATEMENTS ACCORDING TO STANDARD CEB O_1046_XXX
4I,l,l),'.":,AC
BY(R4,AC. _l)"=Rl. 8_15
FF
XD
Note: For "Do not care" functions
refer to timing chart below.
Read out and
regenerate micloinstruction
CORE STORAGE ----+
Store halfwotd
into position
addressed by
Read out
JJ ~11-
-1---
I
I
LA
1 _ __
£J
t-tr f t
8.,LC
I
SU
AlU
Invert sw
(LS reg I)
r----'+-- __
r - - --,
Fi{NSIl
: IAR.
IL... gOO
_ _ 1_ _ 2:....II
~
,
I
1
I To Reg
I
1,-O_A-t
~_IJ
I
1
I
fMR
1
,+2
~
,,_L-,
I MAR
_ _ __
lOA
L.8 _0 J-0.l 1
0
1:
L _ -I--~
I
.- __t..._,
I SAR
I
'
I
I
I
I
1
r-L-a
I
1
LtL 9..,.2. J.J
FunctiOlls
during cycle time are mown by full line~ and functions perfr)rmed during 6. cycle lime are shown by dotted lines.
~agram~:
MovWte (XD)
kt 1 of 2J.....
(0374~
20~50,OOO ~DM
"Do not care" signals:
.6.Cycle c:::::=:::J
Cycle -=:J
Vo].,a",. (8/69)...
2 2 C DAB 2 2
f
-
-
Name
INo
=
AlO
I
Se"", bop Roque,' line,
2
lS New Pl Zone Go'e
3
lS Currao' Pl Zone Go'e
•
T.
T5
T6
ILAIOO
N.w/,",,,,n' l'. moy ,ffe,
i New/Curren. Pl
7 I Fixed X-Add-r-----'--'
Store halfword
into position
addressed by
c.n--?-I
• Read out and
regenerate
"Do not care" signals:
6Cycle c:=J
Cycle -=:J
ISAR
I
I
I
L
IDE
___ L 1__
9 JI
T
SAR15
L.._.J
-
No
~
Name
ALoY-
I
Sense T,•• Re...... Uno.
2
L5 New PL Zane Ga••
3
LS C"".n' PL Zane Ga••
4
New/Cum.n. PL
5
CE LS Selec'
8
'T. Re.' Selec.
•
'F,am Rea' 5010.'
Cycle 0
T5
T6
T8
T3
--
I LAI03
KASII
'. may' fie,
... MAR
,.
... FOI
..11
KII4I1
-==
KII40I
13
L5 10 TOR
MAR •• LS
15
Se. ALU (VO Bu.) to LS
16
LS
W02-712
-
w.1t.
-
r-
, ...l:Ill
17
""'01
Se.......... ~.....
, . . . . . . .hG.
......"
20
Inc.....n. bv I
lAA02
21
In ......n.bv2
LOO3
I 22
I ..
I 24
Ilo«e..... bv
..01
••
RM02
P...... Mad-I
.Ilf
'--
de< .....
n.
63
64
65
-
66
67
Se' AW T... Latch
CCI21
68
Se.",-"""".
..
Set tSAC.....
"","
...,.",
7D
Set ..... " ....
C"'01
71
Set SU Check
CCID2
=
_ N •• AI
73
Se..... Check
CCIOI
75 Set Inh Check
Functfon sf nals: 4.Cycle
I
f'I'lI Cycl. _
"Do not care" si na/sl 4.Cycle 0
• Diagram 5-37. Move Byte (XX, ALe) (part 2 of 2)
Cycle-=:J
(03742A)
- 2020 ~ 50,000 FEMDM Vol 2
_AL~
--
, ,...,check
~
(8/69)
-
--
-
=
_ALCon
Ar• ...Ii "-
-
-
--
-
",T8 _ _
--
-
I
I
MVN
Microinstruction Lavout
LSc.gll,;II,
The numeric (zone) of the loworder byte of the 'from reg' is
remains unchanged
I
2
MVN
0111213141516
7
Op Code
AC
T
moved into the numeric (zone) of
the low-order byte of the 'to reg'.
The 'from reg', the highorder
byte of the 'to reg', and the
zone (numeric) of low-order byte
of the 'to reg' remain unchanged.
Address check is ignored.
;
A
A
I
0
I
111111
8
I
9
I 10 I JJ
A:
A
I5
:
I 13~14~ 15
To Reg
0
01
. t t
Ignored
LS c.g 4
12
00
From Reg
MVZ
0
MV~
01
MVZ
t
5
before execution
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O_I046_XXX
AC41
AE41
MVN
MVZ
4,1
4,1
R4*=R4.0_11/Rl.1Z_15
R4*=R4. 0_7/Rl. 8_11/R4. 12_15
FF
before execu Ii on
DO
Note: For "Do not care" functions
refer to timing chart below.
- -- I - ---- ---
Read out and
regenerate micro-
CORE STORAGE ' -
instruction
--
t-----------------------------------I
A
SU
MVN
MVZ
MVN
MVZ
MVN
MVZ
MVN
MVZ
A
5
5
I I ~
A
A
A
A
MVN/Z
2 5
DE
ALU
MVN/Z
Invert sw
, ,
I , 'I' , I
MVN
MVZ
I
True
MVN
MVZ
Reset FOR
(LS reg 1)
,..I .
W
. To
Functions performed during
.£>iagram
U8.
time are shown by full lines and functions performed d.,,"ing 6. cycle lime ore shown by dotted lines.
Mov~umeric/~e (DD)
(f.aI;t 1 of 2)_ (037431-.
2020l50,000 E.f.ty\DM VaiL. (8/69)
(LS
c.g
4)
True
5
,
A
A
A
A
"Do not care" signals:
l:.Cycle c::::J
Cycle -=:J
INo
Nome
ALO.
T4
I
I 5.... Tn,!, Reque.. Uno.
T5
T2
T8
T6
T3
T4
T5
T6
17
T8
I LAI03
2 I LS New PL Zone Gote
KASII
, 3 I LS Current PL Zone Gote
-
Cvd.
T4
n
T6
17
T8
T4
T5
4 I New/Cu".nt PL
5 I CE LS S.I•• t
ICC222
-
6
7
Fho,d X-Ad"'_
8
'To ".' Select
9
'F,om Reo' Sel •• t
t .... 17
LAA02
I LMII
LS to SAR
110
III
I--
KB411
LStoMAR
Ln
~ to FllR
113
LS tomR
114
MAR to LS
Set ALU
.......
lor___
WOO-7I2
.......
eva Su,) to LS
LS w,it.
116
or___
KB401
LA302i'313
117
I 18 I S.t ......... Chock
I RASOI
I 19 I.... , G.
IRASOO
I 20 In"""",nt b.
I RA4m
I 21 In",....n' bv 2
I RA403
I 22 Dec~...nt
11 .....1
I 23 Deaement bv 2
I IM02
I 2. I _.nt Mod- Reo
K8100
129
KB402
I 30 I SOR'o TOR
31
Eigh. Shift Con"ol
I RBI62
32
Shlf.bv2«4
I RBI 61
No Shlf'
I RBI62
33
. 34
T••• Pocked Byt. . . Sign
1--15
15
RA502
35
Nonnoll.e Sign Active
36
50......
I RBI71
3B
ALU,o FOR
I AA303
39
_ . FOR/Retoln FOR 11-7
I A.A303/l(B411
40
Inv.,' Switch Con.rnl
I RB3D1
ALU eon"ol Gat.
IA.A3OI
MVII
= 12-1
MV;~
=
..... -
41
42
I 43
Additional
ea"y
AA302
,\01
51. C~tlon 8-11112-15
45
Se. Cony .....h
46
Se. Condition Code lnte ....
AA4m
I 47
ALU'a Inh
I MA40I
I 48
ALU to SAR
I KB411
149
I 50
Dalo Switch
I 54
SENS
'0 Cl!> Reg
I KB402
,I S.,abe
.......
BAI02
I 55 I Sen......./cTRL Sh'cb.
I 56 I ~ven' A J and SU Chock
I 57 110
,FOI
BAI03
59
160
61
62
,63
los
La"'"
I eel21
So. AW TH'
So. _ _ Check
I eCI22
i 69
501 LSA Chock
I CC221
I 70
So. Mad Chock
I CCIOI
I 67
; 68
7,",+1501,."-,,,-,
SUJ Chock"l!!:!!~_---l eelO2
'T8....il
(-'I
I 72
I Any
I 501 AW Check
~h..k
;l;l..
-~
LL3 I So. au. a...i.
_...
(-'7~4So!!!t:'~
SAR'~'
d.-"!!..--_---l CCIOI
. 75
I)
501 Inh Chock
Function
lignall~
ACycl. I2llJ
Cycle _
"00 not care" signals: b.Cycie 0
• ~iagram 5-38. Move Numeric/Zone (DO) (Port 2 of 2)
Cyde
Cycle
~
(03743A)
20202: 50,000 FEMOM Vol 2
(8/69)
i of the ne~'
;
;
T6
n
T8
~!r:~ !xecution
The numeric (zone) of the byte
addressed by the 'from reg' is
moved into the numeric (zone)
of the low-order byte of the 'to
reg'.
The 'from' byte, high ""Order
byte of the 'to reg', and the
zone (numeri c) of the low-order
byte of the 'to reg' remain
unchanged.
The 'from reg' address is
incremented by 1.
If the AC bit {instruction
bit 7} is on, an address check
occurs when the 'from reg'
address is outside customer area.
MVZ
_0'----':r-l'--...L1--"2_:'=3':::::'
LI
L--f,
Z
+
Read out addressed byte
-
--/
F
:
2
0111213141516
Op Code
Remains unchanged
Modify +1
LS reg 1
after execution
°:
1
I
2
:
MVN
Microinstruction layout
N
A
11 11
A
11 11
4
if 0 n, the 'from addr' is checked
that it is not outside customer area
7
8
I9
AC
110 111
To Reg
12
0
0
1
1
oI
1
~
L
I
ox
I
I
13 14
From Reg
I 15
MVZ
MVN
I
MVZ
~
IlIIST
l.f.an:)f
OPER..A.NDS
STATEMENTS ACCOanINO TO STANDAltD CEe O.1046·XXX
AD49
AF49
MVN
MVZ
4.lI,AC
4,lI,AC
R4*"'R4. OMll/;SY(Rl.AC,+l). 4M 7
R4--R<. 0.7!jlY(RI,AC,+l). O.3/R<. lZ.IS
LS reg 4
after execution
FF
ox
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
CO~E STO~G£--
-+----
Read out and
regenerate
'from operand'
Read out and
regenerate microinstruction
-----1-1--
-1---
.6..Cycle c=::J
Cycle -=::J
1
i--
r-I.--,
1--~-1
I SO,
!..!_122J
I
I
I
su
MVN
MVZ
I
I
ALU
I
Invert sw
I
MVN
MVZ
°
F
True
F
MVN
MVZ
I
True
I:l
T
Reset FOR
MVN
(NSi)
iF;; Reg-l
L2 ..2J1..lJ
1
1
I
+2
Functions
time ore shown by ft1ll lines and functions performed during .6 cycle time are shown by dotted lines.
• Diagram 5-39. Move Numeric/Z,.ne ([IX) (Part 1 of 2)
(03744A)
2020 2 50,000 FEMDM Vol 2
(8/69)
'-'-i...:..:...o..::.....:...J
ALO
No...
INo
I I Sense T..p Reque.t Lin••
2
LS Now PL Zone Gole
3
LS C""ont PL Zan. Go..
4
~
17
T6
111
Newl cumont PL • mo. dill,
Now/""'.nt PL
7
FI.... X- .......
'To Re.' Select
9
'F,am Reg' Select
u"
lA402
0.--
Ull
..."""""
K8411
111
LS to MAR
II.
LS • FDR
~
I K8401
113
LS to TOR
114
MAR to LS
r--
I---
115 I Se' AW fllO ...) to LS
U6_
LSW,I,.
--- ---
---
I--
IRA501
119 !.....,hGo
I RASa!
1.20 i l _ . l w l
I RAAC\2
121
......_.1w2
I RA403
L22
Docnment Iw I
IRA401
,
'"
.
~
f--
0.--
0...---
..""""" I ACblt~
IHI.lVlow
IMAAOI
Rea
1K8102
1.29
1K8402
1R8162
; SOR to TOR
Elaht Shift Con",,1
132
Shift by 2 or.
133
No Shift
34
• 'ndeflned
1R8161
1R8162
-u- ; t ~ O~l
--- ---
0-15 ,0-J5'
--
t.hlft'l
- -
0-15
Normollze Slon Activo
136
Suon_
R0171
ALU to FOR
AA303
'-Fj
140
io, .h'ft 8 '(by no "o';'.e u••)
0-15
1=8-'
MVZ= 12-15
U-'I,
'=8-1
MVZ
137
39
-
,,.,lft III SAR I ' c ..... h 'ft II no 5, 115
RAS02
Toot Pecked I\yt. or SI.n
1_35
13B
---
---
'"""'""
----
----- ------
1==
0.--
1_
.....n.S •..--U..
I 28 I SOR to Op
31
r--
I RA402
127 , SDR to Inh
130
----
r--
P...... Mod-sAll-lnh Check I KA511
125
126
IIor-'--
'"""'""
~
lo000o-
11A3IIZI313
118 , S e . _ a - k
12.
--
111
17
.....-r--
~
117
I ..
T6
T4
I CC222
8
LS to SAR
12
iII:::::=
6
liD
T6
TS
---
KASll
5 I CE LS Sel.ct
14
13
12
I LAI03
,
"
Cv< 1,0
Ro.. t FOR/Rotaln FOR 0-7
AA303/K8411
I..ert Switch Con...1
RB301
R....
N;;;- 'rue.
nOt inve..
~ /f 'FF/
M.
12-15
---
-
Not true, nol • love" =, FFFF/
'=12-15 MVZ- ~1
TrueO-15=/t,ue!
41
n,
42
ALUCn
43
Additional Cony
OE
,AA301
AA302
44
Six C"",,"on 8-11/12-15
4S
Set
c..... Lotch
AA402
..M S.t Condition Code Lotchos
.
47
,LU to Inh
IMA401
.LU • SAIl
I K841l
49
150
Doto Switch to Op Re.
I K8402
151
Op Re. to Add.......
KAS41
152
I/O 01.010. Add.... Out
t----
~ ,Allow Sh-obe
54
,ISt,obe
SENS
I (Ol.pl SE NS "robe)
BAl02
155 I Se... Reset/CTRL Strebe
I 56
..... nt ALU ond SU Check
I 57
110 ..
BAI03
n.""
--
~
---
---
----
158
I ..
160
161
162
1 63
164
65
166
167 I Set AL J TOIt Latch
1CCI21
68 I Set """'-Cheek
169
Set LSAa-k
1CCI22
1CC221
170
Se. Mod Cheek
1CCIOI
171
Sot SU Check
10..-
~
L72
Set AW Cheek
YAny, ;heck
Set ... Cheek
I
7.
Set SAl Check
]5 Se. Inh C _
function ';8nclll.: 4.Cycle
CCIOI
m
Cycle _
"Do not core" signals, .6.Cycle c::J
• Diagram 5-39. Move Numeric/Zone (OX) (Part 2 of 2)
,chk
----
CCI02
173
I
Cycle
~
(03744A)
~
- "--
~
(8/69)
----
~
~
-...
'T~~
-- ---2020 ~ 50,000 FEMDM Vol 2
==
, TB...iI L
---
~
lo000o-
~
~
--
---
---...
----
~
Cycle 0
'next
The numeric (zone) of the low-order byte
of rhe 'from reg' is moved into the numeric
(~ne) of the byte addressed by the 'to reg'.
MVN
LS reg 4
before operation
:
I0
1
The 'from reg' and the zone (numeric)
of the 'to' byte remain unchanged.
The 'to reg' address is incremented.
by 1. If the AC bit (instruction bit
is
on, an address check occurs when the 'to
reg' address is outside customer area.
n
I2
: 2
--I
Read out addressed byte
-
-
LS"",4
after operation
I0
~~sl unchanged!
: 1
I
2 : 3
II
AC
-
N
---~
I
I
A
A
J
11 110
111111
If on the 'to addr' is checked tnat
it is not outside customer area
I
8
I
9
I 10 I 11
MVN
12 113 1'141 15
To Reg
From Reg
oI
I
oI
~ ~ XD ~
11
1
MVN
MVZ
MVZ
I
Z
1
F
--
7
Op Code
<:
before execution
ModifYi 1
Mi crolnstruction LaYOUt
011121314151_
N
: I
--=
IF
2
after execution
,
I
I
~
Z
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD GEB
ADCi
AFCI
MVN
MVZ
4I.l.AC
4I.l.AC
BY(R4.AC.+l). 4~7·"'Rl.IZ_15
BY(R4.AC.+l). O~3""'Rl~ 8_11
O~1046~xXX
FF
XO
Note: For "Do not care" functions
refer to tim ing chart be Iow .
CORE STORAGE -
Read out and
regenerate
'to operand'
Read outond
regenerate microinstruction
--1-1-
--II
I
,, __ 1 __ ,
I SOR
LA_..!?....C_2.J
-"~: I 11~--
tJ.
r:-- 1
, SOR
I SOR
(F)
MVN
MVZ
MVN
MVZ
I
ALU
I
MVN
MVZ
Invert sw
i
WMVN'-'ir.J...:.....:....
MVZ '--"-".L.!....::....
Reset FOR
(LS reg 1)
r,:':-Re-; - - i
1
I
:"'~2.t-2_~
fT;':;; --"1
1L 0- _.
1 ___
2 3 •I
I
I
I
I
I
I
I
r-- l --r--l
I MAR
1
0
L. -
1 +1
L- - -
I SA'
I
Lo_ LL2_~J
T
SAR15
ines and functions performed
Diagram 5-40. /lk)ve Numeric/Zone (>ID) (Part 1 of 2)
.6. cycle
time are shown by dotted "I inas.
(03745A)
2020 ~ 50,000 FEMDM Vol 2
(8/69)
I-_~
1 2 2_11 __ •I
-/-' -
r-.J--,
Functions performed during cycle time ani shown
--,
1
IA A 5 5
LA_ ~.1-5_~
MVN
MVZ
MVN
MVZ
Store halfword
into position
addressed by
Read out
r;--1--,
SU
"Do not care" signals:
':;'Cycle c::::J
Cycle -=:J
-..rA~l
L_ ...
I
A 2 5 5 - - - MVN
tF A 5 5
MVZ
No
AlD
No~
Req~,t
1
Sen,. T,op
Un"
2
lS N.w Pl Zon, Go ..
3
lS Curr.nt Pl Zone Gate
4
New/Cu,,,nt Pl
5
CE lS Sel.ct
LAl03
W,lt,
~T4
T5
,.
'I
T6
KA5ll
N" Im"nt
; may dl Fee
"
--
T3
W,.,
',ad
Cyet, U
T5
T'
T6
T7
T8
TS
T'
T6
T2
flxed X- "'d"..
,M~
'To Reo' Select
lA402
9
'F,om Reg' Select
lA411
10
lS to SAR
KB411
11
lS to MAR
~!.:;
toLllK
13
lS to 10R
MAR to lS
15
-'6
-==
LA702-712
-
Set AlU (VO ",,,) to lS
lS Welte
LA302/313
......
-
17
18
Set Add".. Check
RASOl
19
"'onch G,
RAS02
L20
Inc"~nt
by 1
RA402
121
In"e~nt
by 2
RA403
1~2
Dec"...nt by 1
123
De
,2
~~
1 24
Peevent Mod-5AIHnh Check
(ASl
1 26
"'event Sto SAR
48
.-"
MA401
49
_50
Doto Switch to Op Reg
51
Op Reo to Add"" Bu,
52
I/O D;,.lov 'dd"" Out
53
All, ,Sic
54
SENS
55
Se... Retet/CTRl S"abe
_5.
57
1 KB402
KA541
ISt,obe
Peevent ALU and SU Check
I/O Bu
~
(I)I,pl SENS ,tmb,)
SAlOl
BAI03
.----
--
-
......
-
> FOR
_58
59
60
61
1.2
63
L64
65
I ..
167
Set ALU T..t latch
1 CCI21
L68
Set "'ac... Check
1 CC122
69
Set SA Check
170
Set Mod Check
I CC221
I CC101
171
Set SU Check
]2
Set ALU Check
73
Set Bu. Check
74
\
(
CC102
t
,SAR Check
~75
Set lnh Check
Function Signals: aCycle
....li:i..
Any
~heok
-
CC101
j
~
Cyele_
.
Do not care " Signals:
aCyele c::l
• Diagram 5-40. Move Numeric/Zone (XD) (Part 2 of 2)
-
Cycle-=:J
(03745A)
.....
~
~
-
....
'T8~ iii..
-
2020250,000 FEMDM Vol 2
--
lor--
~
(8/69)
......
-
==
~
I
lor-y~
~
--
"'"=
...
-
,ra_
- --
...Iiiii.
Cycl, I of ",xt ,
,
,
1
MVZ
Microinstruction layout
'--.:--'---=-1-1-,-1--':L0,-,Ibefore execution
L
,+
The operarion is performed in
AlC mode when 'to reg' == 3 and
'from reg' =5. LS register 1
contaim the field length. The
field length is the real number of
numerics (zones) to be moved
reduced by 1.
The numeric (zone) of the byte
addressed by the 'from reg' is
maved into the numeric (zone)
of the byte addressed by the
'to reg'.
The 'from' byte or,d t-he zone
(numeric) of the 'to' byte remain
unchanged.
Z
Rood oct odd"".d byte
-
-
-
0
1
A
I ofter execution
A
I
: I
L
: 3
,+
I
I
I
I
I
I
I
I
I
I
°
8
I9
AC
I
I
1
~
110
11
13
12
To Reo
I
I
14
M\lN
15
From Re
I
I
L_xx __ J
I
I
MVN
MVZ
MVZ
Z
-TR.od oct odd,.".d by"
MOdify
Code
If on, th e 'from' and 'to' addr's are checked
that they are not outside customer area
I before execution
7
0111,13141516
I
1
Both- operand addresses are
incremented by 1. If the AC bit
(instruction bit 7) is on, an
address check occurs when the
'from reg' or 'to reg' address is
outside customer area.
N
- ~ Remains unchanged
Modify
I2
For ALC, the operand addresses
are incremented by 1 every time
one numeric (zone) has been moved.
- -
-
-
-
-
-
~ Before execution
~~
1
L:.~,-,-1-,,2~:-,-4--,1 after execut-ion
~
Z
INST
MNEIV,
OPF-RANDS
STATEMENTS ACCORDING TO STANDARD CEB 0_1046_XXX
ADCA
AFCA
AFBD
MVN
MVZ
MVZ
4I.2I.AC
4I,21.AC
31,SI,AC
BY(R4.AC, +1). 4_7*=BY(R2,AC. +1). 4_7
BY(R4.AC.+l). 0_3 *=nY(R2.AC.+l). 0_3
BY(R3.AC.+l. UNTIL Rl, LT. 0). 0_3*=BY(RS.AC, tl). 0_3
Ff
Aft., .x.oct,,"
N
Note: For "Do not care" functions
refer to timing chart below.
-
-
-
-
-
-
-
-
-
Reod out ond
regenerate
'from operand'
Read out and
regenerate microinstruct-ion
CORE STORAGE - - +
-I -
-
-
I
1
I
I
I
r-l--,
,
r-I.
-,I
SDR
~A_AL5_5J
~~~5_~..1
LF__1J..£_2--.!
LA_£tS_AJ
Store holfword
into position
addressed by
: I
I
'------I
I
~~;'"""" -I~I
I
r--LSDR
'SDR ..L -1
1--,-------'
Read out
~o~r~ _ _
-1- - -
1
1 SDR
Read out and
regenerate
"Do not care" signals:
6.Cycle C=:::J
Cycle -=:J
-1- -
AA 5 1
A A F 5
IF)
SAR 15
No
SU
MVN
MVZ
MVN
MVZ
I I ~
A
A
5
°
N
Z
ALU
MVN
MVZ
Invert sw
1
MVN
MVZ
(LS reg 2)
r; - - --,
1 From
Reg
I
I 3 2 1 a I
~--t-CJ
I From Reg
I
I
,
L...3_2t~ 1-1
L'l.
1
I
I
I
I MAR
13
~
Y.,
I
I
I
I
I
I
- 2i 1- 0-~I....J
-
_....J
r
I MAR
Y.,
I
,-- i -..,
0
I SAR
No action
Decrement carry 0
forces end op ALC
Functions performed during cycle time are mown by f!J:lIlines and fun<::tions performed during .6. <::ycle time ore shown by dotted lines.
(8/69)
Y.,
,-""
AC I
--
~L_J
I
L-,~
~_1...L~!J
T
2020'::: 50,000 FEMDM Vol 2
r;I SAR
I
SARI5
(03746)
r.-! -...,L
I
~ 2-L1-~~
Diagram 5-41. Move Numeric/Zone (Xl;(, ALe) (Pari I of 2)
INSI)
~.Jt2_3~
ci
-l '-' _U - -
'--~
I
I MAR
I - - - - - - .... ACI
No action
I
1
,-I-too
I
I
I
I
I + 1 }-
I To Reg
,-0-1~].J
-'-t-'--"J
~_°-t~S
I
r;-'!--r-...,
ALC
I
rLsR;g T-'
I
No
r----'
rT~;g--l
I
I
(LS reg 4)
(LS reg 4)
r-----I
T
SARIS
No action
r--'-- .,
I SAR
I
2_
LI 0_ _1 I_
3...JI
T
SAR 15
MVN
MVZ
,
R.,
Alo
Name
INa
t
W,He
Cy,'.O
T5
.T.
"que" Uno.
I
Sen.. T,Of>
2
[S New Pl Zone Gate
3
lS Current Pl Zone Gat._
•
New/Cu".nt Pl
5
CE lS Sele"
T7
T6
18
T3
T.
ole
18
T6
T2
-==
NeW ',urrent
- --
I
T.
T6
18
T7
ILA!Q!
KASII
R.ad
18
-==
-===
,may dif'e,
I CC222
6
Fixed X-Ad"",
lA412
'To ..,,·_~Ieot
lM!lt
'lTam .... Select
lA411
110
lS to SAR
--- ,.- 0"P' If end op F_on
58
Ski. Cycl. 3 to Cycl. I
KMII
60
oec_nt Cony 0
~l
61
End Op Gate
KA412
62
End Op latch
KMil
59
-
-
63
_64_
..
65·
67
Set ALU T••t latch
~ ~t_Check
Set [SA Check
I CC221
70
Set Mad Check
I CCIOI
71
Set SU Chook
74
Set SAR Check
>Any :heck
CCIOI
~
Set Inh Cheok
function slgnall: .6.Cycl. E3
Cycle _
~
Ale
CCI02
~ _Set AW Check
Set Iluo Chook
~
I Cel22
69
73
---
I CCI21
"00 not care" signals: .6.Cycte 0
Cycle-=:J
• Diagram 5-41. Move Numeric/Zone (XX, ALC) (Part 2 of 2)
(03746A)
----
2020 250,000 FEMDM Vol 2
---
== ~
.18..l1ii
=
(8/69)
-==
.=.=.
~
~
~
---
~
"""""'"
~
--==
1=»=
'TO
=
--
,m_
...!!;,
--
~
-
---
.=.=.
'~end
----
,
---
,m_
~
The 'from reg' is added to
(or subtracted from) the 'to reg'.
The result is set into 'to reg'.
The 'from reg' remains unchanged.
The condi tion code latches are set
if the CC bit (instruction bit 6)
is on.
For SHSC a previous
carry must be simulated by
turning on the corry latch (cux
carry latch). The carry latch
can be turned on by a CTRL.
microinstruction.
(ctrl /10/, bit 11).
Lsce94IA:B!C
AH/AHSC
D
I
Microinstruction Layout
oI
(Negative binary number)
1
I
before execution
LS ceg 2
1
1 : 1 !
remains un'=,i"ha='9=.o!;d==='=="==='
Add to
I
3
4
5
Op Code
I
For set carry (SC) instructions
a carry out of the halfword turns
on the carry latch, and a previous
carry is implemented in the
addition {or subtraction}.
2
---~
LSreg4t
after execution )---'------"---'---'
-
-
IfCCbiton-
•
o
o
I
1
I
2
I
3
I
1
I
o
I
0
8
I
9
I 10 III
12
To Reg
13
AH
I 14 1,5
From Reg
0
0
0
0
AH
B
0
1
0
0
AHSC
B
1
0
0
B
1
1
0
ifon~
"'I'
0
0
Q
SH
LDD~
MUM
OPERANDS
STATEMENTS ACCORDING TO STANDAaD CEB ODI046_XXX
BZ4Z
B64Z
BA42
BE42
AH
4.Z,ee
4,Z,Ge
4.2,Ce
Ce,R4"'=R4+R2
GC,C/R4.=R4+R2+C
CC.R4*=R4_R2
CC.C/R4*=R4_RZ.NOT C
4.Z,ee
SH
SHSC
FF
!R8T
AHSC
8H
8H8C
AHSC
SHSC
Ignored
Result less than zero
~ ~ No carry (carry latch off)
7
AC
B
Set condition code
Condition Code
No previous carry
6
CC
DD
Note: For "Do not care" functions
refer to timing chart below.
CORE STORAGE - - +
"Do not care" signals:
bCycle c:=J
Cycle -=:J
-1-- -
Read aut and
regenerate microinstruction
---
Condition Code
Result is zero
ALU zero
o
Result is less than zero
ALU bit 0 on
Result is greater than zero
ALU bit 0 off and ALU not zero
Overflow
Exclusive OR of ALU Carry Bi t 1
and ALU carry bit 0
I 0 0
o0
1 0
XXXI
A
C
D
1 11111
SU
A
Required Circuit Condition
1 0 0 0
No action
D
SH uncond
~C ---t----+--~
if cux carry FL
Add
ALU
Invert sw
AH/AHSC
SH/SHSC
AH/AHSC
SH/SHSC
True
Invert
No action
I
I
I
,I
Functions performed during cycle time are shown by full lines and functions performed during A cycle time are shown by dotted lines.
Diagram 5-42. Add/Subtract Halfword, llldd/Subtrac'r Halfword and Set Carry (DO) (Part 1 of 2)
(03747A)
I
2020 «'50,000 FEMDM Vol 2
(8/69)
No
ALO
Name
I
Son.. T,ao Reaua.' Un..
LAI03
2
LS N.w PL Zon. Go ..
KASII
3
LS Curr.n. PL Zon. Ga••
~
,
Rea
12
lB
-----
,
• ICELS~
New/Curr.n. PL
5
T3
7 I Flx.d X-Add,...
LA412
•
'To ".' Sol~ •
I AAlI?
9
'F,om Rea' Sol.,.
•n
i<.o ,
I""
In.._n.bvl
U02
12.
Intt.m.n. b. 2
AA03
I"
""... moo' b.
; 0A40'
I ..
n-
1RA402
I,.
P~.on'
'A502
,2
Mod-sAR-lnh Che,k I KA.<1
125
126
",".on' 5...... U..
IMA402
I ..
.n.
IMA40I
I ..
SOR"; 00 Re.
I K8102
I
-.5
.......
129
I 30
SOR.o TOR
I K8402
I"
"oh. ShI" Con ..ol
I R8162
I 32
Shift bv 2 «.
I R8'61
N«moilz. Sian
I ... 1<,, _ _ •
t - - f-
-----
-fo-
•• 1:lft a
I R8162
I " N. Shlf'
I", IT... Po,k.d .... « Sian
135
r- r---2-
RAS02
k.,••
10.17.
137
138 I ALU.o FOR
1M303
139 I 11e... FOR/Retal. FOR 0-7
1M30311<8411
1R8301
140
..
In••'' Switch Can',ol
,0-'5 =
to-I.
- S~ iSHSC
I ..
143
I ..
.or,
eo".
,'" r,
Addltlonol
A:1O.
Lateh
45
Se.
46
5•• CandlUon Code Lotehe.
47
AlII '0 loh
...
';~tH' ,andltl :nallf
,au~ ,.rry
,~n
:/SHSC
bTa
AA402
....
-
/..HScIsHsC
..... ,f
MA401
,,,,",
••
: bit on
K8411
'0 00 Reo
50
Data Switch
5.
00 Roo
5•
lIn 01'.'00 lui ...." Ou.
54
SON<
55
S.n•• R....ICTRL St..b.
5.
"'..en' A', I .nd SU C"",,k
<7
"n~
..
,
AA3IY1.
Six C""eeUan 8-11112-15
C.~
.e"
K8402
'0 Add.... Bu.
KAS.'
-
~
",. , •..
S.,.bo
10;'.ISE' , ",obo)
BAIOl
BA1D3
--
-
,on.
58
..,
S•• CC ond
60
Allow CC SetUna La.,h
eo""
AA411
AA4'2
I 61
I 62
I .3
:
164
~.
166
I .7 I So. AC I Teo. Lateh
I CC'2'
I .. I s.,,,,~c,,",,.
I CC.22
169
Se. LSA Check
I CO2.
170
Se. Mod Choo.
CCIDI
171
Set SU Chook
CCI02
172
Se.AWCh...
173
Se..... Che••
I,.
Se. SAR Cheek
I " ..., ,oh".....
Function slgnall: ACyel.
I..--
"\
I)
"00 not care" signals: aCycle t::J
Cycle-=::J
----
Diagram 5-42. Add/Subtract Halfword, Add/Subtract Halfword and Set Carry (DO) (Part 2 of 2)
~
.....
- .....
I"'Ta-
CCIDI
Cycle _
........
~
;Any:,heek
m
~
Ui:i..
c";',.
(03747A)
0 of
2020 ~ 50,000 FEMDM Vol 2
n~t
(8/69)
1'4
T5
T6
T7
lB
T.
T5
T6
11!
T'
T7
11!
LS reg 4
I
A : B
I
Microinstruction Layout
C : D
0
I' : I ; : : :~E~:::'d
r;;:-,--;--",--.---;-iReads oUr'-;--r-;---r-;--rb,".,ore execution
For SHSC a previous carry
must be simulated, if not already
present, to obtain a valid two's
complement of the 'from operand',
The carry latch can be turned on
by a ctrl /10/, bit 11, oswell as
during arithmetical ALU operations.
For SC instructions a caTry
during addition (subtraction) turns
on the carry latch.
The halfword addressed by the
'from reg' is added to (or subtracted
from) the 'to reg', The result is set
into 'to reg '. The 'from' halfword
remains unchanged. The condition
code latches are set if the CC bit
(instruction bit 6) is on.
A previous corry (aux corry
latch on) is implemented in the
addition (subtraction).
~~,::: :",I",~o?
The 'from reg' address is
decremented by 2. If the AC bit
(instruction bit 7) is on, on
address check occurs when the
'from reg' address is outside
customer area or not on halfward
boundary.
2
'\
LS reg 2 I 0 : I
after execution
SH un~ond _ + 1
11
SHSC - carry (Complement)
add to
Condition Code
1
2
o
LS reg 4 I-'-~-,-A,-,--,---,---,,--,
after execution
2 : 2
3
Op Code
SH/SHse
q --
AH
2
1
4
6
7
ee
Ae
5
Resu)t less than zero
9
10
11
12
To Reg
13 14
From Reg
15
B
0
0
0
1
AH
B
B
B
0
1
1
1
0
1
0
0
0
1
1
1
AHSC
~
Set condition code if on
If on the 'from addr' is checked
that it is not outside customer area
- - - If CC bit on
8
j
SH
SHSC
AHSC
SH
L-DX~
SHSC
For SC, corry (carry latch on)
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARf> CEB O_1046_xxx
B34A
B74A
BB4A
BF4A
AH
AHSC
SH
SHSC
4,2I.CC,AC
4,21, CC,AC
4,2I,CC,AC
4,2I,CC,AC
CC, R4*=R4+HW(R2,AC, _2)
CC, C/R4""=R4+HW(R2,AC. -2)+C
CC,R4*=R4_HW(R2,AC. _2)
CC,C/R4*=R4_HW(R2,AC,_2)_ NOT C
FF
DX
Note: For "Do not care" functions
refer to timing chart below.
Read out and
regenerate microinstruction
CORE STORAGE -
"Do not care" signals:
6.Cycle C=:J
Cycle -=:J
Read out and
regenerate
'from operand'
r--:L
I SDR
~--
+----
--1-1-,
I
----1
i-'
LI_..!.J..!...._l~
Condition Code
1000
0100
I
Result is zero
+-----------~r----------------4
Result is less than zero
ALU bit 0 on
00 J 0
Result is !;lreater than zero
ALU bit 0 off and ALU not zero
x xx I
Overflow
Exclusive OR of ALU carry bit 1 and ALU
carry bit 0
+-------------~--------------~
I
I
SU
No action
SH uncond.
I
AHSe/SHSe --+----I-~
if aux carry FL
AND
ALU
AH/AHse
SH/SHSe
AH/AHSe
Invert sw
SH/SHSe
~
T
No action
Reset FDR
r- ----,
r-----'
: From Reg
: From Reg
:
'0__1 +2__ 4;.JI
L:
r-----'
JAR
I
I
t--,
I
18
0 0
'- __
2 I
~--:...J
I0
I 2
I (LS reg 2)
2I
'--1--"
(LS reg 4)
I
AH/AHse
I
I
:
I
Functions performed during cycle time are shown
full lines and functions performed during .6. cycle time are shown by dotted fines.
Diagram 5-43. Add/Subtract Halfword, Add/~ubtracr Halfward and Set Carry (DX) (Part 1 of 2)
(03748)
2020 ~ 56,000 FEMDM Vol 2
(8/69)
Required Circuit Condition
ALU zero
,-'-""-'-=
- -
1 I Sen.. T,... Reque" Line'
T6
17
lB
4
N • •/eu".n' L', moy
New/Cumon. PL
1
cy,
CE LS Sel."
7
Fh,.d X-Addo-...
'To Rea' Selec.
9
'F,om Reg' Sel.e'
LA411
10
LS'oSAR
KB411
LS'o MAR
LS'o FOR
13
LS'o TOR
fI"
--
..!...
LM12
j.~
"=='m.
r---
LS Write
==
==
'"===
r----1
-
---
lor--
=
20
Inc.....n' bv
RM02
In ...men' by 2
RM03
22
Iloc!emen,bvl
R....,1
23
o."....nt bv 2
RA402
••
P....n. Mod-isAR-lnb CMck
KASll
25
P,...n' 5....... U..
MM02
27
SD'.olnh
MMOI
28
SO. to O. Reo
KalO2
SD••o TOR,
KB402
31
Elgh. ShiR eon"ol
.al62
32
Shift bv 2 ...
.al,
l3
NoShl1t
R8162
34
T.,. Pocked BYte .. Sign
RA502
35
Nomoll .. Sign Ac.lve
36
5.........
Ito FOR
t--
'~'I~
------
0- is to 0-1:
: 0-15'
-
---
0-10
--
,h;n,
0-15
0-
10-15
\A303
110... FDR/lIomln FDR 0-7
\A303/KB411
40
I..... Switch C""".I
RB301
Re •••
,o-n·,
Not troe, no' mv..' •
.0-15 -/in ..,',
1.1
AU
..
4S
...
......
.....
R8171
39
42
-
-
-
I 37
L43
.....
RAS02
.21
'38
-
: bit
I.ASaI
Se. ""..... Check
,.---
,...----,
~
-
c:::::----
LA302I313
~ -".o!1Cb Go
29
,30
""""""'"'
""""""'"
......
lor-'--
r---
LA702-712
.lL
.26
-==
lor-'--
15 I Se. ALU WO Bu,) .. LS
18
~
~
KB401
14 I MAR.o LS
16
0.-,---
T.
I CC222
8
11
......
y,'e
---=
6
12
,0
12
---=
I KAS1I
LS C.....n. PL Zon. Ga••
3
5
T5
i LAl03
LS Now PL Zone Gate
~.
-, -
ALD~T4
Nome
INo
~1
ALU eon".1 Gat.
Addltl""ol Cony
',ro.O-W·,
,O-I~
, AI~D
~"
ronven,
AD[ :ER
Uncondm';'.1 U SH, candltlon, i If AHSC 'SHSC If
AA302
'"!' cony FL an
Six C....ell"" 8-11112-15
Se. Cony Latch
-
If 'FF/
-
.T8_ _
_
AM02
Se. Condltl"" Code La.c ....
47
ALU.olnh
MMOI
4B
ALU.o SAR
KB411
AH~ClSHSC
CC
bit on
.9
50
Dato Swll-c----'
: SDR
Read out
'to operand'
Exclusive OR of AlU carry bit 1 and ALU
carry bit 0
- -
No
-
--
-
R.ad
Name
R.q~"
I
Sen,. T,Of'
2
LS New PL Zan. Ga'e
3
LS Curren. PL Zan. Ga.e
4
New/Curren. PL
5
CE LS Sel".
lin..
--
ILAI03
KASll
N, '/,",,,n' L', may
ff.,
TJ
Cycl. U
T4
T5
T6
T8
T2
T4
--
-
T3
T3
T4
1 CC222
6
7
F;xed X- "'d""
"'12
8
'To Reg' Selec'
"'02
9
'F,om Rea' Sel.c'
=
-I K8411
j-!I,,+,OL,,-Si'",-0'S"""--AR_ _ _
~
'0 MAR
11
LS
12
LS, FOR
13
LS.o TOR
14
15
16
MAR
1
-
K8401
'0 LS
LA702-712
Se. ALU (VO Bu.) to LS
li,!o~3
LSWd'e
---
17
~
19
S••
Add"" Check
'"===1 ACba
.ASOI
Ilo-anch G,
RAS02
~
In
.lr.
I S.,
aAI02
'oi •• 1 SEN; .. robe)
_
So......../CTRL S"abe
r"'-+-""",""""n'-"""
All.!!!!!!.'""
SLIC'=""
Ch.flL-j SAI03
57
VO Bu. to FOR
58
y ____-; AA411
I-'~'Y-IS=-:e"
Cc;:.C:-==..
andI C=an
60 I Allow CC Setting La.ch
AA412
61
62
63
64
65
----
66
~
67
Set ALU T... Latch
1 CCI21
68
Se. P'o<... Check
I CCI22
~
Se. L5A Check
1
CC221
10
Se. Mod Check
1
cC12L
1-']..,...,1Se",".-'"
SiLU,-,1C=heck_ _--I CCI02
~ ~.
73
ALU Check
Se. Bu. Check
1-'7",+-4Se..,••c.:
SS,AR""'"",,,'
Chec2-k____1 CCIOI
~ ~. Inh Check
Function signols: oI1Cyde fl/.lJ
•
Cycle _
"Do not care" signols: ACycle
t::l
Cycle-=::J
--
Diagram 5-44. Add/Subtract Halfward, Add/Subtract Halfward and Set Carry (XD) (Part 2 af 2)
-~
==
(0 3749A)
-
2020 £ 50,000 FEMDM Vol 2
"""""'""
(8/69)
--
-~
Cyde 0 of-"~xt ,
,
The halfword addressed by the
'from reg' Is added to (subtracted
fram) the halfward addressed by
the 'to reg'. The result is set
into the halfword addressed by
the 'to reg'. The 'fram' holfword
remains unchanged.
The condition code latches are
set if the ee bit (instruction bit 6)
is on.
A previous corry (aux: corry
latch on) is implemented in the
additIon {subtraction}.
For SHSC a previous corry
must be simulated, if not already
present, tq.obtoin a valid two's
complement of the 'from operand 1 •
The corry latch can be tumed on
by a ctrl /TO/, bit 11, as well as
during orlthmetica.1 ALU operations.
For se instructions a corry
during addition (subtractlon) of
the two holfwords turns on the
corry latch.
number of bytes to be operated
(always on even number) reduced
by 2.
For ALe, the operand addresses
are updated by -2 every tIme a
halfword is added (subtroded).
LS ... 4
Both operand addresses are
decremented by 2. If the AC
bit (instruction bit 7) is on, on
address check occurs when the
'from reg' or 'to reg' address Is
outside customer area or not on
halfword boundary.
INST
M.NEM.
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O_lO.6_XXX
B3CA
B7CA
BBCA
MCA
BTBD
AH
AlISC
SH
SHSC
AIISC
4I,ZI,CC,AC
41, ZI, CC,AC
4I,ZI,CC.AC
4I.2I.CC.AC
n.SI.cc.AC
CC.HW(R4.AC).. HW(R4. _2)+HW(R2,AC, _2)
CC, C/HW(R4.AC).=HW(R4. _2)+HW(RZ.AC. _Z)+C
CC.HW(R4.AC).=HW(R4. _Z)_HW(R2.AC. _2)
CC. C/HW(R4.AC).=HW(R4. _Z)_HW(RZ.AC. _Z)_NOT C
CC.C/HW(R3.AC}....HW(R3._Z. UNTIL Rl.LT.O)+I-IW (RZ,AC,_Z)+C
T
I0
I
: I
2 :
before execution
SH/sHse
41- Re-"d.."ut_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .-IA : B
LS reg 2
I
LS reg 4
I0
Remoh. uncho ..... d
E
-
; 1 t2 : 2
I
I0
: 2
E
I
4
6
CC
7
AC
8
9
10
II
12
To Reg
13
14
15
AH
From Reg
I
I
AH
B
B
0
I
I
0
I
I
AHse
I
I
B
I
I
J '--
I
SH
SHSC
I
~,
S.t conditIon code If on
If an, th • 'from' and 'to' addr.... cre checked
that they ore not outtlde CUltomar CI'8CI
lli.lm--
SH uncond
AHSC/SHSC
If aux corry FL
ALU
AND
Invert sw
r::l
T
Reset FDR
r To- Re;
rFr;; R;g -,
-.,
1
(LS ... 4)
1
I
1
I
r. - - - -,
I To Reg
I
.J
...o..Ji2-U
,
1 2 4 I
I
fTo-Ro; --~
...o..J t 2_4
. . . -t-.J
10
I
I MAR
I8 0
i
0
I- _
' - _.J_
I
~
2 4
_
r-- ~..... AC__ J:
:.J
,.., - I -
T - ,
I MAR
10 I 2
1 -2
41
L ____
L~.!.I!jJ
LO_ ,!"J_1I
. Decrement carry 0
forces end op ALe
during cycle time are shown by full lines and functions performed during 6 cycle time are shown by dotted lines.
¥
•
(0375.2al
• 2QZ9~50,000 FEMDM y.!!.! 2
I
.---'--,
1 SAR
1
I
(8/6fl..
1
1
L __ l
I
I..:--I-- ..... --J
- L..,
r SAR
I
Diagram 5-45. Add/Subtract Halfword, AddLSubtract Halfword and Set Carry (XX, ALe) (Part 1 of 2)
I
_2J
1
r--,
1
No action
liAR --,
1
1
r-J-,
MAR
1
'+2
0 2'
1
1
I
No
,
1 I
:.!.~,.E
I
I
1
.J __
1
1
I
I
1
r -
.,......--~------I
L -,1
1 SDR
r-1:.-.,
II II I
I
I
L02~_8J
-- ----
1
1
1
r - I __
1 MAR
18 0
v••
1 +2
0 21
r-''-----
-~ACI
~_J
No action
No action
ALO
I Some T,. . "q.,..t Line.
T5
3
4
T6
TS
17
KA511
ItS Current PL Zone Gate
I New/Cu"ent PL
N.w, ,u"ent PI • mav dl!
13
12
---
LA103
; 2 I LS New PL Zane Gate
T'
Cycl.
T5
T6
Cv, ,2
T7
17
T'
---
ICC222
5 I CE LS Select
Read
Cyde 0
.T4
1
-ROad
Wrii8
'ead
Name
INa
TS
""'-lor--
I.r---
6
7 I Fixed X-Addre..
8
LA411
1 LS ta SAR
111
ito FOR
13
LS to TOR
~
-----
K8401
LA702-712
114 I MAR to LS
15 I Set ALU (VO
116
"===
K8411
LS ta MAR
12
-----
I LA402
'F.am Reg' Select
9
110
~
A412
'Ta "a' Select
a.,,) 10 LS
I----
LS Write
~
~
""==
~
--
.....
lor--
"'=
""'-- I NotALC
17
18 I Set Add.... Check
I RAS01
_ 19 I ... ,eh Go
HI,
i,;'ow,
he ifword
bou~do'Y
" - lAC bit 00-
IRA5O'l
120
Inenment bv 1
I RA402
121
In ....ment bv 2
I RA403
122
Dec,ement by
IRMOI
123
Dec......nt by 2
I RM02
124
Poevent Mod-SAR-Inh Check I KA511
~
bbm,
"-
I.r---
'=
"===
"===
f---
LA302I313
1...1..
~
~
b"",."""
~
~
---
lor-IALC
~
lor--
........I
I.r---
~
"== lAC bit 0,
-
I.r--ALC end
~ lAC bit or
125
126
27
Poevenl Stor_ U.e
I MA402
SOR to Inh
'MA401
2B IsOR ..
o ....
0-15
10...-
K8102
29
30
_3J
32
SDR to TOR
K8402
Eight Shift ton"ol
R8162
Shift by 2 .. 4
RB161
33
Na Shift
R8162
34
Te.t Pocked Me .. Sian
RAS02
35
Ncwmall .. Sign Active
36
5..., ...
--
---
15
RB171
38
AlU to FOR
....t
40
Inv..t Switch Con",,1
AA303
mOl..
, 'n~ 0-7
AA303/K8411
,ue 0-1. i =rtNer
,:1:
R8301
Notll ve, "ot In~." = /FFI F/
inve,' 0-1 ; = /'
0,'15
-
37
39
---
Not hi" •
,.-
0-15
~i=,
.o-u=/toue/
~
,0-1: !=/Inv."
41
42
-43
1.0..0.301
AlU eon"ol Gate
Additional
Co,,,,
AA302
44
Six C ...ectlon 8-11112-15
45
Set Carr. Latch
46
Set Condition Code Latch••
47
ALII to Inh
,FL-';"
;
SH
155
F AHS( (SHSCI
0-1:
IMA401
0. Rea
I K8402
KA541
Doto Switch to
,I St,""
SENS
Poevent
I/O"
:C bit on
~
It--
i
01,.1 SEN ."'obe)
8Al02
........
---
""'--
I Se... ".t/CTOL St,"".
I 57
,0_15
I K8411
0. Rea to Addreu ...
l56
-_,f
,TS_ 0.- AHSC/SHSC
ill _VO DI.play Addr." Out
U3 Allow St,obe
154
condltlon~1
AA402
U!i .ALU to SAR
Lft
;50
I_ ca,,,,
I ""d SU Check
8Al03
""'--
i.-
,FOR
~
Set CC and Corry
,AA411
AU';; CC: Setth" latch
AA412
~
Skip Cycl. 3 to Cycl. 1
KA411
163
Dec......nt Corry 0
RA301
164
End OP Gate
KA412
I 65
End Op latoh
KA411
59
L60
·Dr •.,lfend
I 61
._-
~Cyci.
1.0.
---
---
166
167
Set AW T••t Latch
i CC121
I 68
Set Frace.. Check
I CC122
, 69
Set LSA Check
I CC221
_70
Set Mod Check
Set SU Check
1("("101
,71
I 72
Se,AW Check
- 73
Set .... Check
,74
Set SAR Check
.1!
Se. Inh Cheek
Function signal.: ACycl. f'll.I
~
~
~
---I""
-....
CC102
>Any ,heck
I
CC10l
""'--
I
I
Cycl._
,FLon
Do not care " signaisl
'
aCycie CJ
Cycle-=:J
~
........
• Diagram 5-45. Add/Subtract Halfword, Add/Subtract Halfword and Set Carry (XX, ALe) (Part 2 of 2)
(03750A)
~
-----I
y:!!!.
'=
0 . - IALC
2020 ~ 50,000 FEMDM Vol 2
-
-.
--
~
b"",."""
0.,.""""
(8/69)
- .....
~
~
""'-""'-- I ALC .nd
>T8_ 0.-
,rs_
~
---
~
~
""'--
---
~
-----
...
-....
I"rs_
i..-
""'--
~
LS reg 2
remains unchanged
The 'from reg' is ANDed,
ORed, or exclusive ORed with the
'to reg'. The result is set into
'to reg'. The 'from reg' remains
unchanged. The condition code
latches are set if the CC bit
(instruction bit 6) is on.
LS reg 4
before execution
I
I :
1
4
8
C
D
I : I
8
I
01,12131415
6
7
Op Code
CC
AC
I0 I0
C
OR
B
EOR
B
The address check is ignored.
:
I :
: I :
8
C
?
I
I
I
I
T4
0
B
B
: i
: Li
B
C
9
I
:
:
8
D
5
C
D
I
5
I
S.t condition code if on
0
1
I
I
1
0
.---J
Ignored
I AND result
I OR result
I EOR result
-
I
I
C
AND
LS reg 4
after execution
AND
MI croinstruction· layout
A
-If CC bit on
i
8
I9
1,0 111
'2T13T14T'5
To Reg
oI
oI
oI
OR
From Reg
oT
oI
oT
AND
OR
LDD-1
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O_1046.XXX
CZ4Z
C64Z
CA4Z
AND
OR
EOR
4.Z,CC
4.Z.CC
4.Z.CC
ce. R4w=R4.A. RZ
CC.R4w:R4.0R.RZ
CC.R4w=R4.0E.RZ
EOR
EOR
FF
DD
Note: For "Do not care" functions
refer to timing. chart below.
"Do not care" signals:
.c,.Cycie c:::::::::J
Cycle -=:J
CORE STORAGE - - -
Reod out and
regenerate micro~tructlon
_
Required Circuit Condition
Condition Code
A
SU
A
C
D
C
D
I II II
8
Result is zero
ALU zero
Result is not zero
ALU not zero
No action
/A B C D/-l0l0 1011 1100 1101
/1 248/- 0001 0010 0100 1000
D 5
Result:
4 C 8
AND 0000 0010 01001000-/0248/
ALU
2
B 9
Invertsw
AND '-'1....o.=--"-.J
Functions performed during cycle time are $hewn
Diagram 5-46.
by Full line;s and functions performed during a cycle time are shown by dotted lines.
AND-OR-Exclus~
OR
Byt~
Halfwor.sL{DD}
(Part~of 2)
.JQ3751)
,
2020 ~ .@.,OOO FEM~ Vol 2 jg/69}
OR
~~-/B8CD/
OE
1011 1001 1000 0101 - /8 985/
--w;u.
ALo
Nome
INo
·T4
I I S.n.o T,op ReQue" Uno.
LAI03
2 I LS New PL Zone Go'e
KASll
TS
T6
T8
Tl
12
I..----
.......
T3
~'
Cycle 0
TS
T'
T6
T7
T8
T3
3 I IS Curren. PL Zone Go'o
New/,u".n' PL • may diff,
4 I Now/Cu".n' PL
5 I CE LS Seleo.
I CC222
6
7 I Fixed X,Add'e"
'To Reo' Seloo.
LM02
9
'F,om Reg' Seloo'
LA411
LS '0 SAR
K8411
110
Im==
""'"""'"
111 : 1S'0 MAR
112
K8401
I LS '0 FOR
----
113 I 1S'0 TOR
LA702-712
114 I MAR'o LS
liS I Se. ALU
.............
.............
LMI2
8
evO 8u.)
>----
to LS
116 I LS w,ite
......
I----
>.3021313
......
"---
117
18
I Se I\dd,u. eheel
ASOI
I RAS02
,19
a...,h Go
120
Inae...n. h,
1.AA02
121
I,,,,,men' by 2
I RA403
122
o.,..men'
123
o."emen' hv 2
12,
AAOI
I RA402
I p,..ent .... '_SA._lnh Chock 1'''"<1
125
126
P,even. S...... U..
IMA402
127
Sol'olnh
IMA401
12.
I SOl to 00 Rea
......
I K.I02
129
Sol.o TOR
I K8402
31
Eigh. Shift eon"ol
I R8162
32
Shift hv 2
1 ••161
130
~
f-- I -
f--
I-
IS 'n
-
"No' hift 8
11.162
33
No Shlf'
34
Te•• Pooked IIyte
3S
N~molize
36
SU......
~
Sign
IAS02
Sian Aotive
I R.171
37
38
ALU '0 Fol
I AA303
39
Ro... FoR/Rotain FOR 0-7
I AA3031K84I'
40
Inve,' Swit,h Con....1
T". 0-15·
18301
I. ru./
41
IAA301
42
ALU Con"ol Go'e
43
Addi.lonol
44
Six C~'e"ion 8-11112-15
4S
Se.e....
46
Se. Condition Code La"ho.
47
ALU '0 Inh
Co,,,
AA302
'ch
AA402
I K8411
J.o SAR
148
If' : bit on
MA401
149
I SO
151
152
I 53
I ~4
Iss
I
Ooto Swlt,h '0 00 Reo
I K8402
Op Reg '0 Add,." Bu.
KAS41
VO
Allow S',obe
I S.,obe
ISENS
I (oi.pl SENS ,';obe) i . -
BAI02
i.-
I Se......../CTRL Strobe
156
57
~-
#--
oi,plov Add.... Ou.
All.
""
r'
BAI03
I/O Bu. '0 FOR
58
I 59
I AA411
S.t CC and Co,,,,
160 i Allow Ce Setting La.,h
AMI2
161
62
I 63
164
165
166
167 I Set'ALU T... "'''h
168
I Set Procau Check
~
I CCI21
~
I eel22
"\
169 I Se. LSA Check
I CC221
lZll I.SeI Mod Check
I r<"I01
\
CCI02
I
171 I Set SU Cheek
In
I Set A 'Cheok
173
Set Bu. Check
74
Set SAR Chook
-1
CCIOI
1
75 I Set Inh Check
functIon signed,: 4.Cycl.
~iagram
>Any:,h«k
r2'lJII Cyele _
Do not care " Signals:
'
.6.Cycle c::J
......
......
Cycle-=:J
5-46. ANO-OR-Exclusive OR Byte or Halfword (DO) (Part 2 of 2)
(03751 A)
~
-
---
~
-....
Cycle
2020 ~ 50,000 FEMOM Vol 2
(8/69)
~
of next
T4
T6
T7
T8
'T5
T3
-I4
TS
The 'from reg' address is incremented
by 1. If the AC bit (instruction bit 7)
is on, an address check occurs when
the from reg address is outside customer
The byte addressed by the 'from reg' is
ANDed, ORed, or exclusive ORed with
the holfword in 'to reg'. The 'from' byte
is extended to 0 halfword by high--order
zeros. Th. result is set into 'to reg'. The
from byte remains unchanged.
The condition code latches or, set if
the CC bit \instruction bit 6) is on.
I
I
I
lS ",g 2
0 : 1
2 : 3
before exeLc-'ot:-:-;oLo-'-t-L""-_'==r-::=
__
t
lS reg 2
0: 1
after execution
I
lS"g4IA:B
before execution
IC
2 : 4
~d::;:.t ~r~ed ~e
_ _ ~ma4"s t~chinged
J:
;l
Extended to holfword by
highorder zeros
_
I
10
Microinstruction layout
o
0~1
;0
'f,~
{
I 5
6
7
CC AC
° °1
J °1 I °
Set condition code if on - "
r _________=A==r===5=OE
lS;e g
I 2 13 I 4
OpCode
C
C
C
4
8
L.:.:....L..:....r=-__
l.-::_...J
__
Condition Code
1
2
3
o
If CC bit on
1
after execution
0
9
10
To Reg
11
12
1
°I
1
°
1
°
LDX~
13 14
From Reg
AND
15
AND
OR
EaR
OR
EO'
result
AND
h~'-+.:;-H~--+~~-I~~R
J
8
If 00, the
odd,' ;, checked
that it is not outside customer orea
~~-++-H-+-!!g_l6~~e:SI~lt
0
I 1
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O.1046.XXX
C34A
AND
OR
EOR
4, 2I. CC.AC
4,ZI,CC,AC
4,ZI,CC,AC
eC.R4*=R4.A. IOOI!BY{R2.AC,+l)
ce, R4*=R4. OR, '00 1 /BY(RZ,AC. +1)
Ce.R4*=R4. OE.'OO'!BY(RZ,AC. +1)
C74A
CB4A
0
result not zero
FF
ox
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
~Cycle
-1------------ 1--
Read out and
regenerate
regenerate microinstruction
CORE STORAGE ----+
~'O~il'r:-
Cycle
i _,
I SoR
L!..1.L '!- ~
Required Circuit Condition
ALU zero
ALU not zero
su
AlU
Suppress
AND
Invertsw
AND
W
bf
IiAR---'
r-,
I
~.!t°..2.J I
I
I
I
I
I
I
I
I
I
+2
..,_1_,
ISAR
l!"'£.L°2J
SAR 15
Functions performed during cycle time are shown. by full lines ond functions performed during ll. cycle time are shown by dotted lines.
,
,
Diagram 5-47. AND-OR-Exclusive OR Byte or Halfword (DX) (Part 1 of 2)
(03752)
2020 2: 50,000 FEMDM Vol 2:t- .@/69)
c:=::J
-=:J
,
.T4
1
I Sen.. Trop Re,,,,,.t Un••
I LA103
2
1
LS Now PL Zone Got.
KASll
3
1
LS Curr.nt PL Zon. Got.
18
T6
12
T7
18
lor--
lor--
iII'"-=
NOI ,/current 'L', mav dl fler
CE LS Select
I CC222
7 I Fixed X-Addre..
L""2
1
T5
0.....-
4 ~~C"".ntPL
5
,.
ALO
No ...
INo
6
8
I 'To Reg' Select
9
'From Reg' Select
L... ll
KB411
i 10
LS to SAR
111
LS
112
LS to FDtl
113
14
15
7
---
~
'0 MAR
~
0..---
KB401
lor--
LS to TOR
I MAR to LS
I Set ALU eva Bu.) to LS
16
LSWrlt.
LA702-712
I--
10-
~
............
f--
.""""",
c .....
Se ....r.n
119
Bronch Go
120
Increment ..
121
Increment by 2
~ I AC bit
HI,;h/low
'A!l01
""-
---
---
~
~
. 17
118
"--
r-I--
~
"--
LA3ll2I:1Il
-
Ioor-'--
r--
f--
............
i>=m
---
~
~
...!
LA402
--
---
.....
IRA502
...,
1RM03
."'"
122
Do
123
Decrement bv 2
12,
Prevent ..... '-SAR-Inh Check I KASI
IRA402
I 25
I 26
1 MA402
Preven' St..... U..
127 I SOR to Inh
IMA401
I 28 I SOR to O. Reg
I K8102
--
""-
129
'0 TOR
30
SOR
31
EI.ht Shift Control
32
Shift by 2 or4
'"34
0..---
1 KB402
Und, nned _
IR8162
IR8161
I RB162
, Shift
Te.t Packed Byte or Sign
35
N..mallze Sian Actlv.
36
SUOD''''
I-- -
NOt iIillflf
f-
'DC1S
Not
,1ft 8 if
115,
, ,
,SAR
---
1~
0-15
10-15
RAS02
'e7
RB171
37
38
ALII to FOR
AA!103
3.
l10set FOII/Re",ln F.OR 0-7
.AA303Ii.412
61
62
.63
~
I 65
166
69
Set LSA Chock
l70
SetMcd C.....
I CC121
ICCI22
I CC221
I CCIOI
171
Set SU Chock
CCI02
167
Set AW T••t Latch
• 68
Set_Check
~
I Set .... Chec.
174
Set SAR Choc.
Functlon signall: .6.Cycl.
~
"--
-....
Any ;,r.eck
""-
CCIOI
J
1'223 Cycle _
~
~
~
""-
~
~
lli. ~lnhCheck
~
~
'\
~ ~Set AW Check
173
['i~
~
"Do not care" Signals: .6.Cycle c:J
0.....-
""""'""'"
Cycle-=::J
• Diagram 5-47. AND-OR-Exclusive OR Byte or Halfward (OX) {part 2 of 2)
(03752A)
2020 ~ 50,000 FEMDM Vol 2
(8/69)
----
- ....
ATR...Ii.
..",."",."
~
-----
~
- .....
""-
Cvcle a ,f next
,
,
Microinstruction Layout
Before execution
Read out addressed byte
The 'to reg' address is
incremented by I. If the AC bit
(instruction bit 7) is on, an
address check occurs when the
'to reg' address is outside
custom er area.
The halfword in the from reg
is AN Ded,ORed, or exclusive ORed
with the byte addressed by the 'to
reg'. The 'to' byte is extended to
a halfuc rei by high-order zeros. The
low-order result byte is set into the
byte addressed by the 'to reg'. The
'from reg' remains unchanged.
The condition code latches are
set according to the halfword result
if the CC bit (instruction bit 6) is on.
0
--------~
l-=:r-----i
I
L5 , .. '
3 : 2
after execution
I
1
8
AND
OR
After execution
AND-OR-OE
AND result
H-++-H-++\ ~~ ::~:~
Condition Code
5
0
0
0
C
1
0
6
7
CC
AC
1
Set condition code if on ----1
If on, the to oddr is checked
that it is not outside customer area
EOR
L5",,211:214:8
remains unchanged
I
4
C
C
Store
I
2
3
Op Code
1
o 1 2 3
'===~=f'~~~~==~------------------J
tjO±±'±~O±~O:1--lf
CC bit on- _____ J
J
8
9
10
To Reg
11
1
1
1
12
0
0
0
I.
13
From Reg
AND
15
AND
OR
OR
EOR
L--- XD---===::J
mST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O.1046.XXX
C3C2
C7C2
CBC2
AND
OR
EOR
41,2, CC,AC
4I.2.CC.AC
4I.2,CC.AC
CC. BY(R4,AC)*=BY(R4,+I),A,R2. 8.15
CC. BY(R4,AC)*=BY(R4.+l). OR, R2. 8.15
CC, BY(R4,AC)*=BY(R4.+1). OE,R2. 8.15
EOR
FF
XD
Result not zero
Note: For "Do not care" functions
refer to timing chart below.
Read out md
regenerate microinstruction
CORE STORAGE - - - .
Read out and
regenerate
'to operand'
Read out
'to operand'
r--
i --,
ISDR
-n
TT--
--:l-
- ,, ,
r-
~'_ _ _--j
_!_-.,
~ SDR
I ABC
0_ ~.I.<:,,_DJ
Store hal fword
into position
addressed by
'tareg'
:
D'D 8 C D
E BCD
l,; __ .J. _ _ .J
E 3
C D
"Do not care" signals:
l>. Cyel e c:::::=:J
Cycle -=:i
~-
AND
OR
EOR
I
Required Circuit Condition
AN Dc::...-':""':"-=.J
ALU zero
OR
EOR
ALU not zero
5U
ALU
True
2
•
Invert sw
,... -
r-----'
: To Reg
13_ _2 1
1...
liAR
+ __
'8__0 0
L
I
t"'--,
I
I +2 1-------------------'
I
L8__0... 0__2 '
,
,
I
I
i
MAR
°°
I
1
I
I
r--t--T-"
: +1 ~
~..3__2tL_2~_~
,...--,
: MAR
AC I
L.._.J
I
,-,
I----------~ AC I
I
L._.J
r--'--,
, __ i __ .,
L3__2J.!._~
I SAR
I
I
13
1 0-JI
... __2.J. __
'- __ :..l _ _ 21
;'"
18
SAR15
I ines and functions perfonned during .6. cycle time are shown by dotted lines.
Diagram 5-48. AND-OR-Exclusive OR'8yte or HalflVord (XD) (Part 1 of 2)
(03753)
2020250,000 FEMDM Vol 2'
I
T
T
SAR15
Functions performed during cycle time are shawn by
I
I
I
1------ ...
SAR
1
I
,
I
:
t-_eJ
I
I
I
I
L~_~!_~
--,
,
'
2
L __
I
,
1
r-----'
:ToReg
13
I
I
I
I
r-SAR
;
0...JI
,I
:,
,...-_1--,
I
.... --'---
13
L. __2 1
,
2.JI
: MAR
----.,
: To Reg
-+ __
+__0-'I
:
.-----,
I
(L5 '"" 4)
:
(8/69)
1 I
I
AlD
Name
INo
Se"o T,a. Roque,' U"",
2
L5 New Pl Za"" Ga'.
3
lS Curr•• ' Pl Zone Ga"
..
~T6
CE lS S.loc'
7
FI ••d X-Ad"'o..
8
'Ta Roa' Sel.c'
-wrrtO
Cye ,"0
TB
KASll
New ' cu,,",' I
T1
T2
,mav dH
•
"~
11
"'0 MAR
I"
13
"'''
IlA402
LA411
-
"'==
K8401
"." ,DR
LS .. TOR
LA702-7'2
MAR 'alS
115
Se' AlU (VO Bu.) to lS
I ••
lS "" ••
f---
,.. AM._. Chock
II.
.....neh Ga
I ?n
,.,,_••• hv
'
121
I.".mon' bv 2
IRA403
I..All.
R"'OI
17
T8
---
T2
T3
~
I
T4
T5
T6
T'
..
--
~
l----L
~
f---
""""""
==
~
k==!
---
HI ;h/law
<=
f---
"""""'"
_.
~
...-Z-
-
"""""'"
AC bit
""""""'"
---
-
---
AC bit
.AS02
I?? no __.,
I .. n....m.n. hv.
I ?A • __•• , ..... '-SAR-Inh Chock
I,.
.".,
IRMo.
I KASll
126
Proven'S...... U..
IMA402
127
,nR •• Inh
IMA40.
I?
I 29
SOR ..
130
SDR'a TDR
I K8402
I 31
Elah. Shift Con"ol
I .BI62
132
Shlftbv2 .. 4
I Ral61
I ..
"'- ,"
I RBI62
o.
-
f---
0302!:'"
I ••
Roc
0-
it-.
I KBIo.
..
134 I To•• Packed M ... SI.n
135
~
K8411
114
1.7
T6
I CC222
Roc' Soloc'
LS 'a SAR
T3
---
•
110
Read
:vcle 2
T5
---
ILAI03
Now/C,,,.. , Pl
•
R~
Und .flned _
f- -I-
---
,
10-
t....-
--,. tsF.ift a-i -sAR
Not !hIlt 8
Ino SAl
I
~j,
:15
tI.
IS
RASo.
N ..mallze Sian Active
136 Isu~
1-7
I RBI71
137
". ,DR
I""
I ... I "-t FD!VRo\aln FDR 0-7
An I ,.__ • Switch C......I
AA!I03
I AA3Q3/K8411
I True 0-1
1.11301
:Tru.0-15~
5:/'Ne/
Tru.O-
5:/.",e/
I ..
A?
A'"
AA
I St, r~••,,"" 0_1111 ••. 15
AA402
,r_ . . . . ,IC :
I ... .-....."' __ C""", ,."' ....
47
ALU'olnh
'MMOI
...
AR
All"" SAR
• K6411
.<0
""•• ,-----'
L~.i.l..c;,..!J
SU
~-
I
I
~--~
I
L£~..L~.!o~
I
Condi tion Code
1 0 0 0
o1
A
AND
2
ADD
A
Invertsw
I
I
,...-----,
From Reg
I
I
IFrom Reg
I (lS reg 2)
r
I
I
I
LQ. Ji!..jJ
I
I
L..Q..J*?.l ....
,,
I
,
,,
r--'!--,.-,
I MAR
I
L.
I _
0 _1
:
I
I
+1 t - - - - oJ
I __ .JI
r-'
~------- ...... AC I
L._.J
I
r--.t--..,
, SAR
,
r --,j- --,
I
I
I
,
, SAR
I
+2___
4
,
I
I
I
LQ..J.J,tt
L~_°..1Q.J"':
SARTS
Functions
and functions performed during .6. cycle time are shown by dotted lines.
Diagram 5-51. Compare Logical Byte or 'Halfword (DX) (Part 1 of 2)
(03756)
2020?: 50,000 FEMDM Vol 2
(8/69)
F
F
F
F IFF
F
F
~
by
Reset FDR
(lS",g 4)
Required Circuit Condition
ALU zero and AlU carry bit 0 on
+-__'..:.To:..o"p..:.,",..:.".::d_'':::m..:.or..:.re:..'..:.th..:.o"~"",..:.m..:.·.::oP.::•.::"",:::d:..'_+_ _A..:.LU:....::,o:::,,:..y..:.b·..:.,'..:.0..:.0'..:.'_ _ _ _ _ _ _-1
No action
Force ---+----+---.1+1
(two's complement)
r------,
0 0
'To operand' equals 'from operand'
'To operand' greater than 'from operand'
Suppress
AlU
"Do not care" signals:
.6.Cycle C==:J
Cycle -=:J
AlU not zero and AlU carry bit 0 on
- -
IN.
AlO~
Name
I i S,n" '
5 : CE lS Solo,t
TO
T7
........
T8
---
---
ILAI03
KA:511
T5
T4
Cycle
T8
T1
12
0
Reg' Select
"0
•
'F,om R.o' Sele,t
lMIl
10
lS to SAR
KB41l
lor--
IlA402
lor--
12
; to FOR
13
ito TOR
lor--
lor--
KB40l
f-f--
I---
""==
~
LSW,;te
>--
f---
t5 I Set AlU IVO &..) to LS
I..--
10.--
........
LAJOO/313
"""==
17
18 I Set ""d" ,Chook
, I.
'A5Ol
........
......
lor--
lor--
lor--
IF AC bl on
I RASOO
Beonch Go
oment b,
120
'===
HI, jlow
r----
-
lor-LA702·712
I. I MAR to lS
10
"""==
"""==
~
; taMAR
f--
t---
""==
~
l--Z-
\.--!---
I----'--
7 I Fixed X-Add'e"
8
..",
21
In",ment by 2
"
0.
23
Deceement bv 2
2'
P"vont Mod-SAR-Inh Check I KASII
I RM03
. .01
I RA.02
25
20
"event St",o,e U..
IMA400
27
SOR to Inh
I MA401
28
SOR to Op Reg
I KalOO
-
; 2.
I 30
31
I 32
SOR to TOR
KB400
EI,ht ShiFt Cont,ol
Ral02
ShUt by 2 '" 4
; R8101
33
No Shift
i Ral02
34
Te,t Pockod BYte", Sian
0-1, to 0-'
-
~
Undefin.d
I--
0,
-15
RASOO
35
N"'mali.o Sign Active
36
Sv. .,e..
Ra171
Al
AA303
37
38
to FDR
Re •• t FOR/Retain FOR 0-7
AA303/Ka411
40
Inve" Switch Cont,ol
R830l
42
AlU Con"al Gate
~
,
lor--
R..et
I~vert 0-1: :-/Inve,t,
...... -
Inv"t'0-15 - /1, ve,tl
Not ""e, not In' ." - /m'F/
AI
' AAJOI
AA302
43
Additional eo"y
4.
Six C",,"ctlon 8-11/12-15
45
Set Ca"y Latch
46
Set Condition Code Latche.
.7
AMOO
,'0_ " - I f
'hi> on
I MA401
Ito Inh
I KB41l
AlU to SAR
I ..
Uncondi tl anal
A.
00 Reo
50
Doto Switch to
51
00 Reo to Add"" Bu.
52
I/O OI<.loy Add,e.. Out
I 53
I KB402
KAS41
>-----
1....--
Allow St'abe
LM
-->!:NS
I 55
Se~
I 50
I 57
I 58
I 5.
p,
IS"obe
DI .. I SEN:; ",abe)
aAlOO
" " rh
---
---
........
........
Re.et/CTRL St,ob.
BAl03
I/O'" toFOR
I Set CC and Co"y
I AMII
I
I AM12
160 Allow CC Setting latch
i
01
02
03
164
I ..
166
I Set AL J Te.. La",h
I CC121
Set P'oc"" Chock
I CCI22
O.
LSA Check
I 70
'Ch ,.k
I CC221
I CC10l
67
168
171
Set SU Check
7:
Set AW Chock
73
Set Bu. Check
7'
Set SAR Check
JS_ Set Inh Check
Function signals! .6.Cycle
~
......
CCIOO
f Any
CC10l
'heck
........ ........
I
I
Im?J Cycle _
"Do not core" Signals: 6.Cycle 0
~
...
--
'===
(03756A)
2020 ~ 50,000 FEMDM Vol 2
(8/69)
........
I"".,."",
"""""""
ili.
, TO"::;
,TR_
-----
-
~
"-
~
~
~
~
6""""
.Cycle-=:J
• Diagram 5-51. Compare Logical Byte or Holfword (DX) (Part 2 of 2)
0.--
lor--
I A fOI'I<
......
-
"levcle 0
Fnoxt ,
LSreg413:
The halfword in the 'from reg'
is compared with the byte
addressed by the 'to reg'. The
'from reg' and the 'to'byte remain
unchanged.
The result of the comparison sets
the condition code latches if the CC
bit (instruction bit 6) is on.
+_______ _
211:0
~ __
before execution
The 'to reg' address is
incremented by 1.
I
lS
If the AC bit (instruction
bit 7) is on, on address check
occurs when the 'to reg'
address is outside customer
co, 4 I 3
I
: 2
1
1
10
~
+1
t
o
B
Ie:
o
11
12
13
14
15
From Re
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O_I046_xxx
CFC2
CLC
4I,2.CC,AC
CC. t OO I /BY(R4,AC.+l),COMP, R2
FF
t
Condition Code
2
0
To Re
E
Compore
o
AC
Set condition code if on
remains unchanged I
The comparison is done by
subtracting the 'from operand' from
the 'to operand'. The 'to' byte is
extended to a halfword by high-order
CC
If on, the 'to addr' is checked
that il is not outside cuslomer area
'From'
IA :
Code
To
I
ofter execution
lS eeg 2
ele
Microinstruction Lo out
Remains unchanged
Read out addressed byte
3
0
If CC bit on ___ Read out byte smaller than LS reg 2
XD
'To operand' smaller than 'from operand'
Note: For "Do not care" functions
refer to timing chart below.
~------------
Read out and
regenerate
Read out and
regenerate micro_
CORE STORAGE -
-:~r~eo"~
~ruction
-
I
I
-
-
-
"Do not care" signals:
6..Cyc!e c:=J
Cycle -=:1
---
---------------------
I
I
I
I
r--t---.,I
r--t--,
I
SDR
i-'~----'
I SDR
,
I
>------1
~~_B.J. ~ _~~
Condition Code
Required Circuit Condition
I 0 0 0 +---,'T:e.o~op~e!.::eo~nd!..':::,q;::":!!ol:..,..::'fc"'om=op~e!.::eo~"d!..·_ _ _ _-+_--'A~l'"U..!'=:ec:co",o"~d..:A:::l:e.U::,o::::cc~y.::b::.;t.::o.::O"~_ _ _-1
o 1 0 0 +---,'T£.o!lo~,~eo!!;"d!..·~'m~o~II,,,e~th~o!!."..!.'f",~m=op~,~",~"d!..'_ _ _+_--,A~l:oU.::,~oe2ey:.!b~II-,O:.:0:!Cff----------l
'To operand' greater than 'fram operand'
SU
b~~ r(~C)
Suppress
Force --------+--l~+1 D
(two's complement)
AlU
ADD
Invert sw
r-----'I (LS reg 4)
(LS reg 2)
I To Reg
I
I
~3_2ILl"';
r-----..,
liAR
I
I
I
~-
~~..9+0_1J
, __ 1 __ , __ ,
MAR
+, I- ___
I
I
I
I
I
~:t 1+'_ Q ~ __ ~
I- - - -
-
r--.I--.,
I
I
SAR
I
.J
r-,
- - - - ....
AC I
L_..J
I
I
!....3_1..Ll_.9~
Functions performed during cycle time are shown by full line~ and functions performed during ~ cycle time are shown by dotted line ••
"'iiagram ~
Com~Logica~e Or Ha,hd (XD).Kt 1 of 2~ (0375~
20~50,OOO~DM
Vol...... (8/69)
,.N"o.
No action
ALU not zero and ALU corry bit 0 on
INo
Name
1
2
ALD
Se... T... Re...... LI"".
LAl03
LS Now PL Z.... Gate
KAS11
~T6
-
oad
~PL
CE LS S.I.c~
ICC222
7
Fixed X-Add....
I LA412
•
'T. R••' Sel" •
5
T-
Cy, ,0
T2
T8
T?
T3
vol.
T4
T3
--
-
~ PL Z;;;;;-~;~
3
4
-
Ne (,",,,,n' L'. may
ff"
T6
"'--
6
9
'"am Rea' Sol.,.
LA411
.n
1< ••
IMA401
i KII402
I ..If.... 2 .. 4
I Te.' Packed Byte or Si.n
,,. I
f-- I---=-u~ ~.d_
IROI62
I R8161
I ROI62
.. "'- ..,"
34
-
~
Ez==
I""
I 35
---
-
"" bit
RA402
I ..............o
-
-Not ,hlft S
1-
-Not,h, tS If SAR is, " ... ,If. If no AR 15
I
0,15
u~"
I
RAS02
-0~7
Normalize Sian Actl.e
I ROl71
So,noM"
io 0-15
137
I""
I ...
140
All". FIlR
AA303
.._. Fn./Rom,_ FOR 0-7
IAA303/K1I411
In_' Swit.h Can'''''
I RB301
I"
"_w., r. •••
I ..
At"
143
Addm...al Carry
I ....
<0. " _ _ "on 8-11112-15
I ....
Sot
AI.
..
c:....
AA301
latch
MA401
KII411
SO
Doto Switch '0 00 Reo
KII402
5.
"" ... t.Add,.......
KAS41
4'
53
CA'
,/oR,_ I
, Ou.
Allow S".bo
. OF""
.... "'_n'
",.,
55
...
AA402
If
: bit on
• ". ·."i ,Cod. Lo•• he.
." •• CA.
..
I in.ondi.io ;01
AA302
All". '.h
A7
~ .. "O-IS~
In .. ,' 0-15. = /on ..,',
• S......
(Displ
BAI02
SE~
..
; "",.)
--
II-
So... Re...ICTRL SO""'.
A.
• •• SII rj,...
BAI03
, FDR
-
se
co
"'C'.".nd,,"~
AM11
60
Allow CC Sottlno Latch
AMI2
61
,.,
I ••
164
I ..
166
&7
168
I ..
1711
I Co. All 1T••tI.~.
1",,121
I Se.Pmc... Check
1""122
....... "....
1"",21
So•• 54"......
171
.... 511"....
In
Se.4W Check
173
174
• So. S4R Che.k
1""101
CC102
~
,
'\
I
'>A;;: :-.heck
Se. Bus Check
CCIOI
J
I 75
I So.'nh " ......
Function signals: 4Cycle
I'lS Cycle _
"Do not care",-siQnQls: aCvcle c::J
Cycle-=::l
• Diagram 5-52. Compare logical Byte or Halfword (XD) (Part 2 of 2)
(03757A)
----
i.r-
~
2020 ~ 50,000 FEMD.M Vol 2
~
==
- ....
~
(8/69)
------
~
-....
'T8...£
-
~
0...-
iii..
Cy.l.o of next
T?
T8
LS...,4
before
I
II
1
exec'''uti:'o=""'-''-\L-'-_~T-_''-'_
,
Microinstruction Layout
_ _
Read out addressed byte
-----~
CLC
+1
The byte addressed by the 'from
reg' ts compared with the byte
addressed by the 'to reg'. Both
bytes remain unchanged. The
compare reSl,lIt sets the condition
code latches If the CC bit (instruction bit 6) is on. The compare is
done by'subtracting the 'from
operand' from the 'to operand'.
The 'from reg' and 'to reg'
addresses are incremented by 1,
If the AC bit (instruction bit 7) Is
on, on c:n:fdress check occurs when
the 'from' or 'to' address is outside
customer orea.
The operation is performed in
ALC mode when 'to reg' "" 3 and
'from reg' '" 5. lS register 1
conto'ins the field length. The field
length is the reol number of bytes
to be compared reduced by 1. The
operand addresses ore incremented
by 1 every time a byte has been
.compared.
.
The ALC operation ends when
either the field length is decremented
below zero or the compare result
becomes unequol.
LS"",4
13
: 2
I ' : ,
ofter execution
LS "'.
before
The operand bytes remoin unchanged
2execu':t"'lon:-'"-'-+L"':_~T-=:!
10:'12;31__
,
_
Read out addressed byte
+,
LS
'eo 2
~
F~
:,,0-1..:..:1-L-,,-~:...;4,,-,
LI
after execution
ComlXlre
+
ms')'
MNEM OPERAND!
5TAT:&MENTS ACCORDING TO STANDARD CEB O-I046.XXX
GI!~CA
C'L.e
-4I.2I.CC,AC
ce,
CFBD
CLC
3I,SI.CC.AC
ee, BYfR3.AC.+l),COMP. BY(R5,AC.+l).
BY(R4.AG,+l), qOlv.P, BY(RZ.AC.+l)
UNTIL Rl,LT,O,OR BY I,NE,BYl
FF
° °
1
Byte addressed by LS reg 4 smaller thon_...Jr - If CC bit on __
byte addressed by LS reg 2
'To operand' smaller,
than 'from operand'
XX
(ALe)
>---"l'l.Cyt:leO
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
Read out ond
regenerate microinstruction
CORE STORAGE -
Reed out and
regenerate
'to operand'
Read out and
regenerate
'from operand'
-11--
---,
I
I
I
r:-.! -
r:- 1 --,
I SDR
1 SDR
LA_~~_E
LA_! ...C__DJ
I
For condition code setting in ALe
mode, the condition code latches
should be set to 1000 (result zero)
by a preceding control Instruction,.
Further condition code setting is
suppressed when a condition code
other than zero is detected. In
ALe mode the condition code can
only be result zero or not zero.
SU
Suppress
Force
(two's complement)
ALU
Invert sw
~
+
Reset FOR
(LS ...
2l
1
I
I
LO.
r-----'1-_,
I
I
I
(LS ". 4) II To Reg
-'i'=- -3.J
I
I
,...----"1
: To Reg
!_L~'_..!J
I
I
I
I
I
I
I
I
I
I
I
I
I
I
r--'---T"--'
I r--LI
rMAR
I
L_-l I MAR
No
I
,..-----..,
liAR
"Tl
I
I
:
L3__2t'__O.J
I
liAR
ts.._O+'!._~
r----'
. - - - --I
1 F""" Reg
I
1321
1..:_
=+ __0 1 _+1j. ,... __ , ~_~..LO_JI
~
f-- -- - -~L AC__ JI
.I.
r;--'-...,I
I SAR
No action
No action
r- - _t. --,
I SAR
I
Ls_!J. _~
___0..L 0__ 21
-'
18
Decrement carry 0
forces end op ALC
T
SAR'S
Functions
(,
....Diagram 5~. CornP...llm Logica~e or Ha~rd (XX/~C) (Part~f 2)
-
2020 ~OOO FE~ Vol 2 ~69)
No action
~Cycle
c::::J
Cycle
-=:J
,;;:j-
Wdte
No
ALD
Nome
·T4
T,ap Reoue,t Une,
1
Sen~
2
LS New PL Zone Gote
3
LS Cu"entPlZo;;eGot';
4
New/C,,,ent PL
5
CE LS Select
LAl03
16
"
T8
~
KAS11
---
12
Fixed X-Add'e"
'To Reo' Select
9
'F,am Reg' Select
LA411
LS to SAR
K8411
11
LS to MAR
12
LS to FDR
~
13
LS to TDR
MAR to LS
15
Set ALU 11/0 Bu,1 to LS
16
LS Wdte
---
==
K8401
I.
LA702-712
r----1
LA3021313
17
18
Set Add,.., Check
IASOl
19
",oneh G,
IAS02
20
lnc..ment bv 1
IA402
21
'n"ement bv 2
..,,3
22
Deceement bv 1
..",
Deceement bv 2
I RA402
p,.vent Mod-SAR-Inh Ch.ck
I 4D?
-
f--
-
~
-
-----
---
-
----- ------
. .01
125
28
.......
29
36
~-,-
---
'-0-=15 ;0::]5
---
·No. , ;;ftb
---
, u-"
0-15
"=== AP only
'AS02
SoPOco"
o 7,
0-7
'Bl71
37
'0 FD'
AA303
38
All'
39
Re,e' FDRlRe""n FD. 0-7
AAlO3/<8."
40
.,
Inve,' Swlt,h Con.cal
RRJOl
.2
All Conlt.1 Ga',
AA30J
43
Addlt'onal eo"y
AA302
M
S'x Ca,e,tI"" 8- 1/12-15
.5
Se. Ca"y Lo.eh
46
Set Cond'tI"" Cod. , oteh••
'7
ALU
48
0-15
R"e'
No. rue, no' ',ve"
- -
"1FfFF/
Inve" 0-" • /'nvect,
I
AD OER"
OE
Jneondlt'~,al
I
~AP·O-I
I If a",
"IC",
FL on
I' no ea'ey bit 8 oc "
(OE" no ,a'r; bi'8 and 12
,T8_ _
-
AA402
'0 Inh
MA401
_
If 'a'r; b,. 8
U",~ndlt'onal
I K8411
J.o SAR
49
1
50
I 51
52
'0 Op Reg
'0 Add .." ,,,
Do'o Swlt,h
Op Reg
I K8402
KAS.,
It----
--
1/0 Dholov Add,e" 0".
53
Allow St,o'"
54
SENS
55
Sen.. 'e,e./CTRL St,ebe
56
Pcoven' AI I and SU Check
57
,/0 Bo,'o m.
I Shobe
-
!cD"pl SENS
BAI02
BAI03
,--
58
AA411
59
Set CC and Cam'
60
Allow CC Selt'ng Lo.,h
i AA412
1
61
62
63
64
65
66
67
Se. All , Te.. Lateh
68
Set P,oee" Cheek
CCI22
6.
Se. LSI, Cheek
CC221
70
Set Mod Ch.ek
, CCIOJ
71
Set SU Cheek
72
Se. "LU Cheek
73
Se. Bo, Cbe,k
7.
Se. lAR Ch.
75 Se. Inh Cheek
Fo nc;tlon
. signals. .6Cyele
~-
CCI21
~
'\
\
CCI02
I
CCIOI
J
'>,;,;;; ,heck
(
m
Cycle_
7
"
Do not core " signals.
6Cycle 0
Cycle-=:J
• Diagram 5-54. Add/Zero and Add Packed Byte (DO) (Part 2 of 2)
(03759A)
-
~
- --
~
~
==
=
2020 250,000 FEMDM Vol 2
--
Tn.
""""""'"
(8/69)
-
-
----
~
,TA_ _AP, '-IS, no ,heck ZAP
--
Cy:'e 0 of
ne~'
,
T3
1'4
Microinstruction Layout
ZAP
The twei decimal digits in the byte
addressed by the 'from reg' are
added to the two decimal digits in
the low~arder byte of the 'to reg'
(AP) or to zero (ZAP). The result,
which may consist of three decimal
digits, is set into 'to reg'. The
'from' byte remains unchanged.
+_____ _
-"-+1..2-,=:=:3=11
LS reg 2 LI-"0.......
before execution
A data check occurs when the
low-order byte of the 'to reg' is
not in packed format.
L __
Read out addressed byte
10:
:rl
LSreg2
I
after execuL,.i'c,o-n"-'-'-~"'-".....
lSreg417:76:61
A previous corry (aux carry latch
on) is implemented in the addition.
A corry, out of the low-order byte,
turns on the carry latch. The
condition code latches are set.
LS ,eg4 1 0
after execution
II
12
13
14
From Reg
AP
15
If on, the 'from addr' is checked
that it is not outside customer area
ZAP
1------1
5 5
r---
before execution
9 10
To ...
AC
r---~~------~O-+~~~--~~--------~-+-------4~~p
T
-I
The 'from reg' address is decremented by I. If the AC bit
(instruction bit 7) is on, an address
check occurs when the 'from reg'
address is outside customer area.
Op Code
Remains unchanged
-----::-: - - - - . .
Set to zero
Set to zero } - - - add ----JII.. ..Q....Q...
No carry occurs
~
0
1
2
3
~~c~onEdtU~;o~n
~codf·fl
0
Set
L.._-unconditional ..
!au !5
Result not zero
INST
MNEM
OPERANDS
STATEMENTS A(!;CORDING TO STANDARD CEB O_1046_XXX
Dl4A
D54A
AP
4,2.I.AC
4,2.I,AC
CC.C/R4*='OOl/R4. 8_15,D+.IOO'/BY(R2..AC. _I), D+. C
CC,C/R4*:::·00'/:SY(R2.,AC, _l).D+, C
ZAP
FF
ox
Note: For "Do not care" functions
refer to timing chart below.
CORE STORAGE -----...
- --- -! --,- --
- - - - - - - - - -i-
r--:L-,
I
SDR
-+---
Read out and
regenerate
'from operand'
Read out and
regenerate micro~
instruction
r--.t--,
SDR
L~_t....i~_5-11-,- - - - I
I
I
:L.. D
1 4 A!-'- , - - - - - '
__ .1. _ _ ....
I
"Do not care" signals:
.6.Cycle c:::J
Cycle -=:J
17.-;;]------ ---tra re
I
(5)
1---'1
Data error
I
~-----
Required Circuit
Condition
Condition Code
1 0 0 0
Result is zero
ALU zero
o
Result is not zero
AlU not zero
I 0 0
x x 0 1 Overflow
ALU carry bit 8 on
~
CC-Iatches
:- ~~_J~----------------'~
AP
ZAP '-..,.,.,-'----'
I
SU
/55/ = 0101
1111
0101
1111
OE result .. 1010
-6 (odd) '" 1010
1010
1010
;1"/
=
No
j,y
Forces trap request 2.
PL switching is performed
after the following microinstruction.
(Sense trop-requ T3 before
setting data error FL T7
AP
Suppress
Suppress
/0066/ =
;!loBB/
= /AA/
=
'Add'result =
= 0 ' / ' 0 0 = /44/
Result
AP and ZAP must be preceded
by a control instruction which
resets a previous carry (latch off)
and sets the condition code to
1000 (result zero)
0000
0000
0000
0000
0110
1011
0110
1011
0000
0001
0010
0001
"--..I
"--..I
!
!
Carry 8
1faux corry Fl
handling
= /0121/
Corry 12
No six correction
ALU
ZAP
/0000/
Invert sw
;!loBB/ =
0000
0000
'Add' result =
0000
=
0000
0000
0000
1011
0000 '.._ ... }011 , .. _)011
No carry 8
!
L:J
T
,..------,
From Reg
,------,
I From Reg
I
I
I
10
I
~0_.l+2_1J
..
:,
,
1
2
(LS reg 2)
I
2'
--f--~
,
,
I
I
I
:,
I
,... __ t ___,..._,
I,MAR
"
1-1
I- ___ ...J
'-' __I +2___3 L_..o
10
,
I
I
I
I
I
,..-,
1----- --- .... AC I
I
r--:L -...,,
,..--.1--.,
SAR
I
I
I
I SAR
L.._..J
I
I
I
'0
L.. _ _1 .L.. 2__3 ",I
L.. _ _
..J
'8
0 ..1. 0_ _2'
T
SAR 15
Functions performed during
functions performed during A cycle time are shown by dotted lines.
Diagram 5-55. Add/Zero and Add_ Packed By,~ (DX) (Part 1 of 2)
_ (03760)
2020 ~J.O,OOO FEMl'M Vol 2 _(8/69)
~
"'../
No carry handling
(LS ..g 4)
AP
ZAP
= ;!loBB/
No carry 12
Six correction
lOll
1011
-6 (Add)
1010
1010
0101
0101
Reset FDR
I
,
0000
1011
=
/55/
Reod
A Cycle
No
Nome
ALD.
Cyde 0
T4
li,.,
I
5.,.. T,op R.qu.,'
2
lS New Pl Zooe Go"
3
lS Curre,' Pl Zo,e Go'e
T6
T8
T3
T4
ole
T6
TB
lAI03
KASII
4
New/Cune,' Pl
5
CE LS 5.1."
CC222
7
Flx.d X-Add....
lA412
8
'To Re.' Sel.c'
lM02
6
9
'eo' Seleo'
'F,~
II
'0 SAR
lS '0 MAR
12
; " FOR
10
13
114
KB411
KB401
'0 TOR
'0 lS
MAR
LA702-712
15
... , ,lll 11/0 Bu.)
16
LS Wd'.
_
lA411
lS
lS
f----
f--
'0 lS
-
___
-
LA302/313
-
-
-
----
17
18
s., Add'M' Check
I RASOI
••
0..
I RAS02
I 20
I 21
, ,""
omo.' b.
H191/low
: ba 0'
I RA402
I ' ...
I,~.me.' bv 2
I RMOO
I,., "-..ome.'"
I 'A40'
I 23
,,",.. me.' bv 2
IRM02
"'eve,' 5,...... U..
IMA402
125
I 26
I 27
0-15
0-15 ,0-15
IMA401
'0 I,b
SO.
0-
I K8102
'R I 50'10 00 Reo
29
'30
'0 TOR
SDR
I KB402
31
Elah, Shll, Con"ol
32
Shift"" 2 '"
,.".
A,y heok
I-'''~''!!U!''''l!!..''C~h'L-_--l CCIOI
75
Set I,h Chock
Function signol.: ~Cyele
m
Cvcle _
"Do not care" signals, 6.Cycle 0
Cycle-=::J
• Diagram 5-55. Add/Zero and Add Packed Byte (DX) (Part 2 of 2)
(03760A)
2020 ~ 50,000 FEMDM Vol 2
(8/69)
-
_.....
,;0,
-
--
'.~,5,
'0
eok ZAP
M",crOInS
" t ruc rIon Layou
The two decimal digits in the Jow-order
byte of the 'from reg' ore added to the
two decimal digits in the byte addressed
by the 'to reg' (AP) or to zero (ZAP). The
result (Jow-order two decimal digits) is
set into the byte addressed by the 'to reg' ,
The 'from reg' remoins unchanged.
A previous carry (oux carry latch on)
is implemented in the addition. A carry
out of the low-order byte turns on the
cony latch. The condition code latches
are set.
A data check occurs when the low-order
byte of the 'from reg' or the byte addressed
by the 'to reg' is not in packed decimal
format.
The 'to reg' address is decremented by 1.
If the AC bit Onstruction bit 7} is on, an
address check occurs when the 'to reg' address
is outside customer area.
I
LS ,e941 4 : 3
before execution
I
0
II
2
-
3
4
5
6
D
I0 I
0
I0
D
0
Op Code
2 : I
L - -
ZAP
-
-
-
.
Read out oddre5Sed byte - - -
-I
----eLi]]
Before execution
I
t
I
I
I
7
AC
I
-,-
LS 'e9 4r-1-:4--'-;-=3--'-1-=2--'-:7
0 -'1
cHer executi on
LS,e92IB: B
I
If on, the 'to addr' is checked that
it is not outside customer area
B 19 110111
To Reg
I
0
I
I
~
L
12
L'3J 14
AP
115
From Reg
0
0
AP
ZAP
ZAP
XD - - - "
Set to zero
I • I
15 :51
Add_~ I
remains unchanged ~
No carry occu~
5 5 Result
~Sto~e
Condition Code
1
o
5
W<0-'-..!.'-'-"-Wl....r~- Set unconditional
5
INST
MNEM
OPERANDS
Dlez
D5CZ
AP
4I,Z,AC
4I,Z,AC
ZAP
STATEMENTS ACCORDING TO STANDARD CEB O.1046.XXX
. CG o C/:SY(R4,AG).=BY(R4,-1),D+.RZ. 8.15.D+.C
ce, e/BY{R4,AC, .1)'f<=RZ. 8.15, D+, C
FF
After execution
--- - -
Result not zero
XD
Note: For "Do not care" functions
refer to timing chart below.
Read out and
regenerate micro·
instruction
CORE STORAGE -----
Tr
Read out and
regenerate
Read out
'to operand'
~OOP'i~1
-,I
I
t::':-.t-~
pDR
I
r-
I
I
p~-
I
LJ'...l -LL6...J
L.7--" -L Q_A_J
;- -lDat~'~J
i-1
I
I
I
I
I
Data error
I
I
__
Force trap req 2;
PL switching after the
current instruction
I
Ft
:
__ J
Force trap-req 2;
PL switchin.a after the
current instruction
I
I
_1-
su
AP
r
----- --- --
_i_ I
'SDR
!------1
Sto", halfwo", Into
position addressed
by 'to reg'
"Do not care" signals:
A. Cyel e c::::::J
Cycle -=:J
77
21
AP
ZAP
,--l
Da
I
I
7"e.!r.01I Force
trap-req
PL switching after the
L
I following
_...J
2;
microinstruction
I
I
I
_ _ _ _ _ --.J
Condition Code
1 0
o1
Suppress
a
a
0
0
X X 0 I
ZAP
AP
Ifaux carry FL
----1;---GDEEDJt,l-----------~~---J
Invert sw
i:l
1
Reset FOR
~;;9- - i(lS "'941
rroReg- --,
I
I
I
I
I
I
I
I
I
IMAiit--,
'-I
U2tLI...J
L_...J
f--~Aci
I
+2
I
L4..1tL'....J
L4...1+2...1...J
I
'SAR
I
L42
i --,
I
J.L'...J
T
SAR 15
Functions perfonned duri.,g cycle time are shown by
SAR 15
and functions performed during .6. cycle time ore shown by dotted lines.
Diagram 5-56. Add/Zero and Add Pocked Byte (XD) (Port 1 of 2)
(03761)
2020 ~ 50,000 FEMDM Vol 2
(8/69)
I
I
Required Circuit Condition
Result is zero
ALUzero
Result is not zero
ALU not zero
Ov.,flow
ALU carry bit 8 on
CC-Iatches
ZAP
ALU
I
AP and ZAP must be preceded by a control
instruction which resets a previous carry
(latch oft) and sets the condition code to
1000 (result zero).
.
Cy~
INo
Nam.
Cyde 0
ALD.
T4
I I Se.... T,.o Rea_' Un••
2 i LS N.w PL Zon. Ga ••
T5
T7
T6
12
T3
T4
T5
T6
T4
T6
111
T4
T5
111
T6
I LAI03
KA511
LS Cu...n. PLZono Ga••
3
4
Now!C...entPL
5
CE LS Selec.
N. Icu,..n' 'L'. may
fie,
CC222
6
....
7
Fixed X-......_
8
'To Rea' Selec.
•
'F,nm Rea' ... ,•••
OA.
I-'II~O!:.LS;.!!!
Ia.~
S.SAR~_ _ _~K8411
I---
LS.oMAR
111
1.0 I t< •• FnR
K8401
1,3 I LS'o TOR
1,4 I MAR '0 LS
1,5 I Se. ALU IVa Bu.1 to LS
LA702-712
I LS W.lle
.""""' . .
1.7
IRA.501
1,8 I Se. Add.... Chock
10.
I 21
' In ...
I, 22
I ..
I 24
n.
.1
,~
mon' bv 2
1."",,-,
Doc.emen. bv I
..."
_.0
I P................-.nh Check
I.Am.
I nm
10.
I 26 I Preven. St..... U..
I MM02
rI2~7'S~~I~.a"n~h~~-4I==~~,-+---+--~--~--~--~--+---+---~--~-un__ ""
I211
.0-1
1"'02
SDR to 00 Rea
129
I 30 I so. to TDR
I K8402
132 Shiftbv2 .. 4
I ••,..
~n!!!~_I-_
rl,,~'N~00~Shlft~-----¥I.~R1~--~--+---~~~-4---+--~--+---+-~~_·:1,5
I 34
TH' Pocked ...... Sion
I 35
Nwmallze Sian Acnve
I... <,
·15
1...."".",.1 AP only
.A502
lAP only
p. 0-7, ~p. 0-1
10.. 7.
"0-7, 'AP'O-
137
138
AlU.o
F~
I.. ..... FDRI .... in 'FO. 0_7
I 40
Inv.t Switch C~t~1
I AA303
I AA.""''''''l1
...e.o...-
I ••,n,
141
I 42
Al J Con"ol Got.
10E
AA301
4~3=Addit=ionoll~
CO...
!L..-_---l AA302
(-:1
44
Six
c~.cn~
Ilf aux cony Fl on
is
8_11112_15
12)
,T _ _ II co,,,, bit 8
1-''''!:4-'~''''C",!!!!l.~.!.!!'!E!L"'_ _~ AA402
...
Se.
C~d"l~
C"..... , ... 10.,
I 47
ALU to Inh
' MA401
I 4R
AlU.o SAO
I K8411
I SO
Dnto Switch
I 51
Qp
'0 00 Rea
I .....
R•••o Add.e" Bu.
KAS41
52
1/0 Di.olav Ad...... Ou •
.S>
;'''owSl.obo
54
SENS
55
Se... Re.../CTRL St.obe
ISt.obe
.. ..
57
"lOr'
; 10 0-7 no SAR
10,8-'
SAR
15\
It---
I(Di",1 SENS """'ej
RAI02
0...-
RAI03
1/0 ....n Fn.
!ill
I AMl1
I...
Se. CC and
I 60
Allow CC SeHlno Latch
,
.,
cOn'Y
AMI2
I~
I ..
166
I 67 I
Set AW T.,. , ....h
I CCI7'
I 68
Sot _
1,.,.170
Check
I rco?l
I rr'n'
7W-f-'11Set2!!'~
SUI o..ck~'----_--I CCl02
I .. I Set [SAc......
170
So...... ,......
..,1
I 72 I So. AW Chock
)Any
~.ck
17315o.... c.....k
7~41So2!!.lSl.!!!IAR',!,!!!!;
n...
....
!L.-_--I CCIOI
1-'1
I 75 I 50. Inh Chod<
Function sfgnolr. 4.Cycle
lJ
FlJ2.I Cycle_
Do not core" signals1 ACycle c:J
Cycle.:=J
• Diagram 5-56. Add/Zero and Add Packed Byte (XD) (Part 2 of 2)
(03761 A)
-----
2020 ~ 50,000 FEMDM Vol 2
_....
--
,TO_ ~AP I-IS, no
~eck ZAP
---
, TO,
i-IS. no
:'ck ZAP
Cycl~ 0 01
(8/69)
lS reg 2
The two decimal digits in the byte
addressed by the 'from reg' are added
to the two decimal digits in the byte
addressed by the 'to reg' (AP) or to
zero (ZAP). The result (two decimal
digits) is set into the byte addressed
by the 'to reg'. The 'from' byte
remains unchanged.
The operation is performed in Ale
mode when 'to reg' = 3 and 'from reg' = 5.
Each operand has its own field length and
the field lengths may be different. lS
register 0 contains the field length of the
'from operand'. lS register 1 contoins the
field length of the 'to operand'.
lSreg2
I0
after execution
:
1
Microinstruction layout
AP
:1
~-- TRead out addressed byte ~
LSreg4
14:3120
after execution
I Add
Set carr; latch
Condition Code
1
2
3
0
1
Before execution
:~:5
5
:
~66
*
o
o
Set
unconditional
II
12
13
14
15
I
0_ _ _ No previous carry
~
I
~
ZAP
ZAP
If on, the 'from' and 'to' oddr's are checked
that they are not outside customer area
: 3 3:2::;:~1;;J1
rr::::::Jq::,
If the 'to operand' field is too small to
accept all digits of the 'from operand' field
the condition code is set to overflow (Ce
latch 3 on).
10
o
t====3t==~O~P~Cio~1E!1=t~tA~C~~~TO~R~.~9====~~~F~'O~m~~~g~j
o
AP
lS reg 4
I4
before exeCl.'tion
The operand addresses are incremented
by 1 every time a byte is operated.
Both operand addresses are decremented by 1. If the AC bit (instruction
bit 7) is on, an address check occurs when
the operand addresses are outside customer
0
7
The field length is the real number of
bytes in an operand field reduced by 1.
A previous carry (aux carry latch on)
is implemented in the addition. A
corry, out of the low-order byte, turns
on the carry latch. The condition code
latches are set. A data check occurs
when the 'from' byte or the 'to' byte
is not in packed decimal format.
I
before execution
mST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB OMI046_XXX
DICA
D5CA
DIBD
AP
ZAP
AP
4I,2I,AC
41,21, AC
31.5I,AC
CC. C/BY(R4.AC)",=BY(R4, _I), D+, BY(R2., AG, _I), D+, C
CC, C/BY(R4.AC. _1)*",BY(R2.AC. -l).D+, C
CC. C/BY{R3.AC. UNTIL RI.LT .O)*<=BY(R3. _1),D+, BY(R5,AC,-I,UNIu.. RQ,
LT,O),D+.C
Result dec add
F,
i ~
=::- =~ ____ --II!:::fJ
After execution
xx
Result not zero and carry
(ALe)
Note: For "Do not care" functions
refer to timing chart below.
-i-,--
Read out and
regenerate microinstruction
CORE STORAGE ---+
Read out and
regenerate 'from operand'
---------TT--
. . __ t __ . .
r-: SDR
~'_ _ __
:SDR
I
. . . _------+--
Read out
'to operand'
Read out and
regenerate 'to operand'
I -- ....
~'_ _ _~
AP
ZAP
L~1l.6_S..t
L
1---,
Data error
r----Data error
I
I
i---l~l-~
I,
,,
,I
,
I
I'
I
,
I
I
,,
,I
--~
Force trap-req 2;
PL switching after the
current instruction
I
I
I
I
N~
__________
Data error
I
,i-----l;l--1,
I
I
I
I
I
I
Fl'
I
---..I
I
I
,
__ Mol
,
Force trap-req 2;
PL switching after the
current instruction
Fqrce trop-req 2;
PL switching after
the following
microinstruction
I
I
I
-.1. ______________________ _
,I
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ JI
I
,I
Suppress
SU
If aux carry Fl
AlU
Invertsw
r:l
(lS reg 2)
(LS reg 4)
...
r-----',
, IAR
,
IL. 8__
0 0
I--l
II
I To Reg
I
'4__
3 '}
L
J
I
+__I ..tI
lToReg:
r-----'
Ir-----'
To Reg
:
L-L.1+2_1J
I
'4
~ 3
I
I
I
I
,,I
I
I
r--L: MAR
I
I
,
,I
La_ ~J..0_ ~
a a a
L4_~+2_..!.J
r--t--,,
I
No action
1
I
L~~.J.~2J
Decrement corry 0
turns on LC FL2
sIs
Decrement carry 0
I'\,rns on aux LC FL1 ....LC FLl
LC FL I
Functions performed dvring cycle time are shown by
and functions performed dvring .6. eyell' time ore shown by dotted 1ines.
Diagram 5-57. Add/Zero and Add Packell Byte (XX, l!.LC) (Part 1 of 2)
(03762)
2020 ~ 50,000 FEMDM Vol 2
(1r/69)
: L':.~+~~J
(I
:
iI
I
(NSI, AlC)
a a
0
Result is zero
o
1 0
a
Result is not zero
x
x 0
1
Overflow
CC-Iatches
I
AP and ZAP must be preceded by a control
instruction which resets a previous corry
(latch off) and sets the condition code to
1000 (result zero).
r-- Y---
~
LC FL2 force ehd ap ALC
In ALC mode, further condition code
setting is suppressed when a code other than
zero is detected. ALC condition code call
be result zero or not zero.
r-,
L_..J
I
ISAR
I
:
+__
L_..t
I
IL.. _ _ .J. _ _2 ...J,
I
I
I.MAR
I
1-1 I- _____ J
I
1
4 3 2 1.l._.J
'
I
'aoo
L __
L. __ ..l. _ _ _
I
No action
lIAR
I
r--I--T-,
'I
I
No action
I
I
,MAR
L---t..fACi
: MAR
Y.,
1
I
AlC
1
. . --.1--,
,SAR
2 a '_____ .,
__ *_;_..J
I
I
.- __ t __ ,
No
:+-21-------_<
Conditi on Code
1
I
I
I
+__2 .JI
I
(LS reg 4)
r-----'I
rF-;o;Re~-l
I
'
~O__I-+~_3
T
~-------~AC
I
. . -_1-- ,
ISAR
1
I
,
L-:'':.J.~T
SARIS
I
No action
In AlC mode, overflow condition is set
(beside ALU carry bit a) if the 'to-field' !ellgt],
is smaller than the 'from-field' length and the
additional 'from' data are nat all zero.
"Do not care" signals:
.6. Cyel e c::=:::J
Cycle ~
'INo
Nam.
-.L
Sen.. T..". lIo.....t Uno.
ALD.
T6
T4
2
~
LS New PL Zone Gate
17
18
KASll
--'S C.....nt PL Zone Gote
4
New/Cum>nt PL
5
CE LS Seloot
CC222
LA412
Read
Read
ACyde
f2
--
];I
T4
Read
A :yde
--
Cyde
Ly". U
T5
T6
T8
17
1'3
--
T4
1711L
17
--
1'3
18
---
T4
T5
6
7
Fixed X-Ado......
8
'To Reo' Select
9
'F,om Reg' Select
111
==
LStaMAR
rllLP2LS~;t~a.'F~DR_ _ _~K~1
113
IIr:--=
LStoTOR
-
rll"-t-'4MAR"",,-,1t=-:o.L=-S_ _-;LA702-712
15
Set ALU (I/O Bu.) ta LS
16
LS W.lt.
r--LA302I313
17
18
Set Add.... Check
19
......ch Go
iRAS02
20
Inc"ment by 1
1
21
I• ...ment by 2
1
22
Dec"ment by 1
i RA401
23
o.",.ment by 2
IRA402.
24
_ent Mod-SAR-Inh Check
I
------ =
---
==
LA411
f-!ll~OJ,~S;t~o.S""'--AR_ _ _-J KB411
RASOI
. Nat ALC
~
26
.MA401
K8102
i KB402
SDR to TDR
c:~
~~'~,=
I R8162
31
Elaht Sh;ft
32
Shift by 2 .. 4
I R8161
IR8162
33
No Shift
34
Test Pocked Byt. . . Sion
35
Na Latch
'T8_ . . . . lfca"ybU8
AA402
~~~_Se~t'C~~;t~lon,~C-,~L~~che.+_-__I~_+-~-+_-~_+-~-4_-~_4-~-4_-+___I---+--~--+_--~_+--~--+_--~~--_r--~-r___I--_+--_I_--r___I~-+:,••--11'5ito'~~SAII~ .. 8-15~Rl
47
ALU to Inh
MA401
..
ALU
KB411
5AR
--~~. .~~~--~
49
50
Dota Switch ta Op Reg
KB402
51
Co Reg to Add,...
au.
KAS41
52
110 nt_ I
, Out
..R _All... SI,obe
54
SENS
55
Son.. lIo..t/cTRL St,oIo.
I St,aba
5b.Preven. ALU and SU Chock
57
'AMll
59 IAll... CC Setting Latch
61
SAlOl
ISkip Cycl. 3 ta Cycle 1
Dec..m.nt Cony 0
-
KA414
63 AU>< LC Latch 1
.M. ,LC
AM12
I KA41'
IWIOJ
62 Set LC Oatch..)
KA413
Latch 1
KA41·
65
LC Latch 2
KA413
66
End Op Gate
KA412
67
Set ALU Test Latch
--
ICC121
69
501 L5A Chock
I CC221
70
Set Mad Check
I CCI0l
1-'7"+1501"",-,,,,-,:
SUI C""""'heck_ ___I CC102
ALC
I
cE...Se. AW Check
So.
au. Check
7,..45o,.,t''-'''''SARI",.,..
Choc!L-k--'-__I CCI0l
I-'i
.:&.Se' Inh Check
Function . .nail: 6Cycle
-
Ifto o"rond ,
ICCI22
.... _Sot"""" Check
I 73
-
-
-
-
__
I/O B" to FOR
...s!l LSet CC and Cony
60
o1.,1 SENS ....be)
SAl02
m
Cycle _
-00 not care" slgnals2 6Cycle 0
Cycle-=::J
• Diagram 5-57. Add/Zero and Add Packed Byfe (XX, ALe) (Part 2 of 2)
--
(03762A)
2020 ~ SO,OOO FEMDM Vol 2
~
_....
(8/69)
--
-
--
-"""=
_....
-
I
r
-IS. no cl~ck ZAP
LC und
"I'..S"I
--
-
CIS.
:eck ZAP
Microinstruction Layout
7
lSceg4
Before
SP or PPC, the
previous corry must
simulated by
turning on the corry latch by a
control/lO/, bit 11 to obtain the
correct complement.
A carry, out of the low-order byte,
turns on the carry latch. The condition
code latches are set. A data check
occurs when the low-order byte of the
't-o reg' is not in pocked decimal
format. Address check is ignored.
For SP, the two decimal digits in
the low-order byte of the 'from reg'
are subtracted from the two decimal
digits in the low-order byte of the
'to reg'. The result is set into
'to reg'.
For ppe, the tens complement of
the two decimal
in the 'Ioworder' byte of the
reg' is set
into 'to reg'. The 'from reg' remains
unchanged.
A previous corry (aux carry latch
on) is implement-ed in the operation.
Op Code
7;71661
AC
10
11
12
To Reg
13
14
15
0
before executi on
SP
From Reg
0
SP
ppe
ppe
LS reg 2
Ignored
remains unchanged
Invert
~Add~
00 if result true
(FF if complement result)
~~,:~ge:eoJH~' ! ,!
0
1
+
66
AA,
DD-.-t
1
~ ~11-
Complement
Condition Code
Subtract result
\. :,:,:,
~o~~ ~o~:
Set
uncond
Result not z:ero
IN.::i'l'
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O-1046_XXX
0242
0642
SP
4,2
4,2,
ee, C/R4*'"
PPC
'00' /R4. 8_1S.D_.'00'/R2. 8_15.0_.C
ee.ejR4·.*= 'FF'jX,X = '99'.D_.R2.8_15.0+.C
FF
DD
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
6. C yc Ie c::::::::J
Cycle -=:J
Read out and
regenerate microinstruction
CORE STORAGE -
--~~J
r--L -,
I SDR
ID
I
24
21T
" - --~
(6)
Data error
~[-FLlI
I
I
SP
ppe '---(-6)----'
I Force trap-reg 2;
I
I
__
J
I
PL switching after
the following microinstr
Condition Code
1 0 0
o
J 0
SP
.lW.l1.JlJ
C(-Iatches
SP
ppe
SP
SU
SP and pec must be preceded
by a control Lnstruction which
sets a previous carry (lotch on)
and sets the condition code to
1000 (result zero).
ppe
If aux carry Ft;------
AlU
Invert sw
F::l
T
(LS reg 4)
(LS reg 2)
. Packed complement
~'AR
0 0 4.
r-1--o
f-----.
liVlAR
l'_ -" _0 _ ~
I
I
'2
,
r--~--'
I SAR
~_.::. ~
I
_2J
Functions performed during cycle time are showl) by full lines and functions performed during .6. cycle time are shown by dotted lines.
Diagram 5-58.
Subtract Packed Byte/PerForm Packed Complement (DD) (Part 1 of 2)
(03763)
~20 2 50,OO..QFEMDM Vi'I 2
(8/69)
Required Circuit Cond
01--.:':::e':.:'-.:"-.:;':::":::ec:::o_ _+ __A_lU_"_e_co_ _---j
0 I--.:R:::e:.:,,:::''-.:;'-.:':::.o'-.:":.:e:.:co_+_A-'-l:.:U_o-'-o_'"-'-e_co_---j
AlD
Name
INo
I I Se"e T,ap R.que,t Un..
2
lS N.w Pl Zoo. Gote
3
lS Con.nt Pl Zone Gate
4
IlAl03
,
~T4
-Wdt,-
Re<
I
Cyd,O
T6
T5
KA511
T3
T4
New/Coneot Pl
Cye
---
T6
-==
lor-Ne~/c~
5 I CE lS Seled
T2
T8
I',
16
T4
I CC222
7
FI.ed X-Add""
'To Reo' Seled
9
~
lA412
'F,om Reg' Sel"t
lMIl
110
lS to SAR
KB411
III
lS to MAR
112
lS to FOR
1,3
lS to TOR
I,.
MAR to lS
It?_
Set AlUl!LO B"i to lS
116
lS Wdte
i...-
f--
"=
"===
i----
f.-
lor---
----
"LA702-712
i----
f--
I.-
A302/313
lIB
Set Add"" ChKk
I RA501
119
","ooch Go
I RA502
120
In«ement bv
121
Inaement by 2
123
I 2.
RM03
"'01
' RA.02
bv
De«e~nt
P~vent
Ioto:::::=
RA402
i
.nt
'"
---
--
lor---
KB401
117
122
.-L-
i----
<.02
T4
---
6
8
T8
Mod-SAlt-lnh Check
KA51l
125
I 26
"event St"'age U..
MA402
I 27
SDR to Inh
MA401
~
SDR to O. Rao
KBI02
-------
129
SDR to TOR
KB402
31
Eloht SWt Con"ol
RBI62
32
Shift by 2 "'.
RBI61
33
No Shift
RBI 62
34
Te,t Packed Byt. a Sign
RA502
35
NamaHze Sian Adlve
36
Suo",e"
130
_0-1
,Qc"
-==
r= ,',=- 1--- f-
15
== SP only
se ,0-7, PPC" 0-1
RBI71
37
38
AlU to FOR
39
Raret FDWRotoln FOR 0-7
I AA303/KB411
40
Inv.,t Switch Cont,ol
, RBlOI
I Con"ol Gate
I AA301
"
42
. 43
Additional Cony
~
Six Ca"ctlon B-Il/12-15
45
~
I....-
AAJ03
I.-
Not"" not
In~"t "/FF~F/-
I'nv"t 0-15 " /Inv"t,
If aox eonyFL on
AA302
I
Set Cony latch
,
--
,TR_ _
AM02
Set Condition Cad, lat~he,
47
J to Inh
I MA401
48
J to SAR
I KMII
If cony blt8
.49
50
Data Switch to Op Rog
I KM02
Op R. o to Add'e" B"
KA541
I 52
I/O DI.olav Add"" o,t
~
Allow St'obe
I 54
SENS
" S"obe
Sen .. R...t/CTR l S"obe
BAlO2
P"vent A J and SU Check
BAlO3
I 55
I 56
I 57
I/O~
II--
--
I....-
I(DI>pISEN5
i----
, mR
I 58
59
I 60
Set CC and Cony
I AMI
Allow CC S,ttlng latch
I AA412
~l
62
63
164
-~
66
67
I Set Al J Te.t latch
68
Set P'ac'" Check
69
Set SA Check
70
Set Mod Ch,,",
71
Set SU Check
, 72
CC102
~
\
I
) A.":eheck
Set AW Check
'23
Set Bu. Check
..2.
. Set SAR Check
75
I CC121
I CCl22
I CC221
I CClOI
Functron SIgnals: dCycie
-
CC101
J
Set Inh Check
~
Cycle _
"Do not care" Signals:
--
~Cycle
0
Cycle-=:J
• Diagram 5-58. Subtract Packed Byte/perform Packed Complement (DO) (Part 2 of 2)
----
~
'===
=.=.
~
b",.".
-...
'TR~ili..
-
(03763A)
---
f--
2020 ~ 50,000 FEMDM
Vol
2
(8/69)
--
I.-
--....
----
~
'8:,5,
.0 ch~ck PPC
Cyd ;Oof.exl,
T5
T6
T8
T7
11!
Microinstruction Layout
For SP, the two decimal digits in the
byte addressed by the 'from reg' are
subtracted from the two decimal digits
in the low-order byte of the 'to reg',
The result is set into 'to reg'. For
PPC, the tens complement of the two
decimal digits in the byte addressed
by the 'from reg' is set into 'to reg'.
The 'from' byte remains unchanged.
PPC
A carry, out of the low-order byte, turns
on the carry latch, The condition code
latches are set.
LS",2
~ __
before execution
A data check occurs when the low-order
byte of the 'to reg' is not in packed decimal
format.
- 1
.,
reg 2
'I~O~:~1~I~2~:~2~1
after execution
lS
The 'from reg' address is decremented by 1.
A previous corry (aux corry latch on)
is implemented in the operation.
+_
I
I
LS reg 4
7 : 7
before execution
If the AC bit (instruction bit 7) is on, an
address check occurs when the 'from address'
is outside customer area.
6
6
I
Op Code
Read out addressed byte
Extended to halfword
Invert
~
Two's complement
A
-6
11
12
13
14
15
From Reg
IF:FI4
PPC
PPC
If on, the 'from oddr' is checked that
it is not outside customer orea
A
+1
B
-6
on ition
ode
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O_I046_XXX
D34A
D74A
SP
PPC
4,2I,AC
4,2I,AC
CC, C/R4N:o 'OOI!R4. 8_15, D_,'OO' !BY(RZ,AC, _1). D_. C
CC,C/R4¥<=IFFI/X ,X = J99 I ,D_,BY(R2,AC,_I),O+,C
Set
uncond
r
LS",4
To Reg
SP
~:ES¢~~2
A
AC
Remains unchanged
"~~_l==-;:=~T~':"'~'
:,o:m:pl~em:e:"~tJ~~~L~_~_~_~_____
:t
Before initiating SP or PPC, the
previous corry must be simulated by turning
on the carry latch by a control/10/, bit 11,
to obtain the correct complement.
SP
10
10:112:31
51
FF
Result not zero
after execution
DX
Note: For "Do not care" functions
refer to timing chart below.
-
-
-
-
-
-
-
-
-
Read out and
regenerate
'from operond'
Read out and
regenerate microinstrucHon
CORE STORAGE -
-1I
I
- -
--------
---1- ---
---~----
I
I
r--l---
r--t--,
: SDR
Data error
,-'~_ _-'
I
I
I
L~_3.J~_~J
(7)
FL
1I Force
trap-req 2;
r PL switching after the
I following microinstruction
I
I
I
---01
SP
PPC
Condition Code
(7)
Result is zero
ALU zero
o
Result is not zero
ALU not zero
1 0 0
5P and PPC must be preceeded by a
control instruction which sets a
previous carry (latch on) and sets
the condition code to 1000 (result zero)
SU
If aux carry FL
--i----t---t.~~.:jl,
ALU
Invert sw
f::l
T
Reset FDR
r-----'I
r----- .,
I From Reg
I
I From Reg
,
I
I
I 0 1
2 3 I
'---t---~
r-----'
liAR
I 0
*__
1 2
L __
(LS reg 4)
,
SP
2 I
...t
PPC
I
t--l
0 2-'
+__
I
II
INSI)
I
,
,
,
r--t--T-'
I MAR
I
I 0__I
L
I 5AR
t
I
1-11------"
I
,
...1.._.J
r-'
I
,
IL--------.r AC I
L_.J
, __ t __ -,
, __ i __ ,
•
I
+2__3
I SAR
I
I
I
a
IL __1.J.
IL.. 8_ _0 .l. 0__2 ....I
I
t
2 3....Jr
__
T
SAR15
Functions performed during cycle time are shown by
lin~$
and functions performed during .6. cycle time are shown by dotted fines.
Diagram 5-59. Subtract Packed Byte/PeHorm Packed' Complement (DX) (Part 1 of 2)
(03764)
2020 ~ 50,000 FEMDM Vol 2
(8/69)
Required Circuit Condition
1 0 0 0
0:iliJ2I
CC-Iatches
I
1 8__0
L
"Do not care "signals:
l:t.Cycle r==:J
Cycle -=:J
Pocked complement
,
,cie
T5
.T4
I I Some T.ap Requ•••, Une.
2
3
5
----
lor--
KASll
N., ;;cu.~n' ;L'. may d' 'fe.
New/Cu""n' PL
I CE LS S.I.c'
.......
T6
I LAI03
I LS New PL Zon. Gole
I LS C....n. PL Zone Go••
4
W'!k
ALO
Nom.
INo
~
Cycle 2
I CC222
6
7
I Fb,.d X- ........
lAAI2
8
'To 11<.. ' SeI.cO
LA402
9
'F._ Reo' SeI.cO
lAAll
110
LS,o SAR
K8411
111
LS,o MAR
II>
IS , FOR
113
LS'o TOR
114
MAR.o LS
..",."".",
""""=
K8401
ILA702-712
~
I---
LSWdt.
I LA302/313
118
Se. Add.... Check
I RASOI
119
I1l
118301
40
No. ""e, not
i~ve" =/FFFF/
Not 'ue, not ~vert
=/FI'FF/
ill
42
ALU eon".1 Gal.
AA301
143
Addition.1 Corry
M302
44
Se. c..n. Lmch
46
Se. Candi.ion Code Laiche<
147
ALU •• Inh
148
ALU 10 SAR
=0-7,
PPC
=0-
'Invert 0-1 ; = /inve.
'f ou. carry Fl on
I
,
51. C,,"octlon 8-11112-15
4S
Isp
Isp only
,TR_ _ _ If ca;~ bit "
AA402
,
MA401
I K84H
149
Iso
W
I 52
I 53
LM
Dolo Swllch
'0 00 Reo
I KB402
KAS41
..Qo ..",. Add.... Bus
It---
VO D'splay Addreu Cu.
411_ 5"....
1<0,
~NS
BAI02
I (01..1 SENS ,t""",)
155 ' Some ...../CTRL Sln>be
I 5.
I 57
Iss
'''' e, ••k
I ..
--
......
BAI03
I/O Bus '0 FDR
I Set CC and Ca...
I AA411
159 I Allow CC Setting Lalch
I AA412
--
-
~
60
I 61
l.62.
163
164
6S
166
167 I Set AL , T..t lalch
68
70
50
I C021
ICClol
I Chock
Ln
Set SU Check
In
Set AW Check
eCI02
Any 'check
173 , Set Bus Chock
lJ'4
Se. SAR Chock
I 7S SetlnhChod<
Functton lignalt: 6Cycl.
o...l;L
I CCI22
JH.. Se. lSA Chock
celol
FlIJJ
Cycle _
~
~
I Cel21
Se._Check
I
I
I
liDo not care" signals: aCyele c::J
Cycle-=:J
• Diagram 5-59. Subtract Packed Byte/Perfann Packed Camplement (OX) (part 2 of 2)
---
~
----
(03764A)
~
~
"""=
' T•
--....£ L
'===
2020 ~ 50,000 FEMDM Vol 2
-....
,=,
--......
(8/69)
~
~
~
~
b""."""
~
ll.
......
----...
~
""- . . . . SP 1-15_ no
-
~.ck ppe
Cy~l. 0 of ne~t ,
For SP I the two decimal digits in the
fow-order byte of the 'from reg' are
subtrocted from the two decimal digits
in the byte addressed by the 'to reg'.
The result is set into the byte addressed
by the 'to reg' .
For PPC, the tens complement of the
two decimal digits in the low-order byte
of the 'from reg' is set into the byte addressed by the 'to reg'. The 'from reg'
remains unchang~d.
A previous carry {aux carry latch on}
is implemented in the operation. Before
initiating SP or PPC, the previous corry
must be simulated by turning on the carry
latch by a control/WI, bit 11, to obtain
the correct complement. A corry out of
M"lcrolnstructlon
• L,ayout
,PC
the low-order byte turns on the carry
latch. The c.ondition code latches are set.
A data check occurs when the low-order
byte in the 'from reg' or the byte addressed
by the 'to reg' is not in pllcked decimal
format.
The 'to reg' Ilddress is decremented by ,.
If the AC bit (instruction bit 7) is on,
an address check occurs when the 'to address'
is outside customer area.
LS reg 4
14
: 3
before execution
!
L
2
~
-1 -
0/1/2/3/4/5/6
Op Code
Before execution
-
D
1
1
-r--L..-----Ten's complement _ _ _ _---"
8
9
10
To Reg
1
1
If on, the 'to
addr' is checked that
it is not outside the
customer area
8:815:51
remains unchanged
0
1
~
*
LS e.g 4 [4
2 :'-".3-'--"2_:L...::.0....1
after execution
LSc.g2
0
0
D
~
Read out addressed byte - -
-1
7
AC
L
11
12
0
0
XD
SP
13 /14 l15
From Reg
SP
ppe
PPC
---.t
lNST
MNEM
OPJ!:RANDS
STATEMENTS ACCORDING TO STANDARD CEB O-I046_XXX
D3CZ
D7CZ
SP
PPC
4I.Z.AC
4I,Z.AC
CC. C/BY(R4.AC)*=BY(R4. ~l).D~.RZ. a-15.D_,C
ce. C/BY(R4.AC. _1)*=199'.D •• RZ. 8.15, D+,C
FF
~e
l...i...:.2J
XD
After execution
Note: For "Do not care" functions
refer to timing chart be/ow.
"Do not care" signals:
fl. Cyc /e c::::=:J
Cycle
Read out and
regenerate microinstruction
CORE STORAGE - - .
Read aut and
regenerate
-,-
~toop·r~1
I
iT
I
rsD,t-..,1----1
_.1 -,
SDR
r;:
I
I
tJ--".1~6.J
r-1
Stare halfward into position
addressed by 'to reg'
Read out
'to operand'
I
I-PIE.r
7 7
J
r
7LiI
__
J
J
I
Force trap-req 2; Pl
switching after the
current instruction
FL -,I Force
trap-req 2;
Pl switching after the
I
folbwing instruction
I
_..J
1
I
NoJ
/
I
----'
SP
SU
-1
Data error
Data error
I
I
I
1 1 SP
ppe
L7...l.L L6J
Suppress
SP
ppe
SP
SP
PPC
pce
ALU
lnvertsw
F::l
1
r:: - - - ,
I To Reg
I (lS reg 4)
U..Jt 2_ U
rraReg- - ,
rroRe;- - ,
I
I
I
L4_3+L
l.J
~.!tO_2J~
I
/
I
I
I
1
I
rw:):
- T-'
I
-1 t- -
I
+2
f----~Ae I
L4_3.J..2_'J
T
SAR15
time are shown by fulrlines and functions performed during 4 eyele time are shown by dotted lines.
,(,
....I2iogrom~.
J
u..J+2..- 11_J r-l
I
r: _.1.._-,
I SAR
I
Functions
I
L4-1f-OJ
I
'TAR --.,
I
I
,
Subt~Pocked..il6t.e/Perfo~cked C.-Jement ~ (Port l.o1H.2)
~5)
-"120 ~ 50~ FEMD~I 2
SP and ppe must be preceded by a
control instruction which sets a
previous carry (latch on) and sets
the condition code to 1000 (result
zero).
If aux carry Fl
I
I
CC-Iatches
(~)
L_J
-=:J
ALO
Name
INo
I
Sen.. T,ap Reque" line.
LAI03
2
lS New Pl Zone Gate
KASII
3
lS Cu....nt PL Zone Got.
•
N.w/Cumont Pl
5
CE lS Select
CC222
7
Fixed XcA
15u,,,,",- !",' •.may
Ife'
0
9
110
.~ toS.M.
III
LS to MAR
112
LS to FOR
13
II.
KB411
""""""""
=
KB401
-==
lS to TOR
lA7OO-712
MAR to LS
r---
15
Set ALU (VO Bu.) to LS
16
LS YMt.
LA302/313
I--
17
18
Set Add_ Check
RASOI
19
",,,ch Go
RASOO
20
Inc'ement by I
RA402
121
In ...ment by 2
RA403
22
De....ment by
RA40I
23
Decnment by 2
RA402
24
p,".ent Mod- SAR-Inh Check , KASII
HIg~ /Iow
I.
12
----
.W'' _.
Read
-
,cle 2
14.
"
TO
T8
17
T3
T4
-~
-==
~
..-Z-
,.....1-
==
r---
==
T4
=
='-"
r--
==
-
lor-
-
b=
r--
==
=
AC bit,
-
---
---
ACblt,
25
26
"'e.ent St..... Use
,MA402
27
SDR to Inh
'MA401
28
SOR to O. Re.
I
SOR to TOR
I KB400
KBIOO
29
30
31
EI.ht Shift Con..ol
I RBI62
32
Shlftbv2 .. 4
I RBI61
33
No Shift
I RBI62
34 .le.t Pac.k~ 8yte~19n
35
N ..monze Sign Actl. .
36
Su.., ...
~nd.
~
---
-
-----.,
-= -
37
AI Ito FDR
Re.. t FOR/Retoln FOR 0-7
woa/KB411
40
In.e,t Switch Cont,ol
R8301
WOl
Re.. ,
42
44
145
ALU
eon ..ol Gate
im=
--
-
Not !rue, not I~v.rt = IF FF/
I 41
143
0-1>
"""""""
I RBI71
39
' .""'-'" c'",,-,hift 'no SAR
U-J5
RASOO
38
-0-7 to 0-7 fSAR IS, H5toB- 15 If no SI ,R 15'
-"
'= U-/I
~.ert
==
! SP only
SP only
; = u"",-,
wert 0-15 = IIn .. ,t,
0-1' : = Iinvert,
~A301
Additional Cony
; If aux ca'" FL on
AA300
,ca=
Six Con-.ctlon 8-11112-15
Set c:..,.!.atch
-
>rs_ . . .
AA402
Ilcan-ybltB
. . . Un' ,ndWonal
46
Set Condition Code Latches
47
ALU to Inh
MA401
48
AlU to SAR
KB411
3-15
10,8-1
(SAl: 15)
49
Co
50
Doto Switch to
51
Co
52
VO OI••lay Add,... Out
53
'liow St,
i..
"""""""
-==
b=
----
15. no ch"kPPC
----
-...
~
'8~15. no c~ "k PPC
T5
:
I
For SP, the two decimal digits in the
byte address by the 'from reg' are
subtracted from the two decimal digits
in the byte addressed by the 'to reg'.
The result is set into the byte addressed
by the 'to reg'.
A corry out of the low-order byte turns
on the corry latch. The condition code
latches are set. A data check occurs when
one of the operand bytes is not in packed
decimal format.
lS reg 4
4
before execution
The field length is the real number of
bytes in on operand field reduced by 1.
The operand addresses are decremented
by 1 every time one byte has been operated.
The 'from' and 'to' addresses are decremented by I. If the AC bit (instruction
bit
is on, on address check occurs when
the 'from' or 'to' address is outside
customer area.
For PPC, the complement of the two
decimal digits in the byte addressed by
the 'from reg' is set into the byte
addressed by the 'to reg'.
The 'from' byte remains unchanged.
8efore initiating SP or PPC, the
previous corry must be simulated by turning
on the corry latch by a control /10/, bit 11,
to obtain the correct complement.
:
I
:
1
I
:
1
lS reg 2
0
after executi on
The operation is perfOf'med in AlC mode
when 'to reg' '" 3 and 'from reg' '" 5.
Each operand has its own field length. The
field length may be different. lS register 0
contains the field length of the 'from
operand'. lS register 1 contains the field
length of the 'to operand'.
A previous carry (aux carry latch on)
is implemented in the operation.
I
lS reg 2
0
before execution
n
1
Before execution
Microinstruction layout
----~
5
6
Op Code
3
lS reg 4
4
after execution
:
3
I
2
7
AC
10
11
12
To Re
13
14
15
From
PPC
SP
If on, the 'from' and 'to' addr's are checked
that they are not outside customer area
t2
I2
A
A
-:-;-;-r-:
I
6
Add~
Carry
Condition Code
~
6
A+1A} Complement
•
B;
-1--1 Subtract result
II
sets corry latch
Store
________
1 I
Set
uncond
After execution
Result not zero
INST
MNEM
OPERANDS STATEMENTS ACCORDING TO STANDARD CEB O_I046_XXX
D3CA
D7CA
D3BD
SP
PPC
SP
4I.ZI.AC
4I,2.I.AC
3I.5I.AC
CC.C/BY(R4.AC)*=:RY(lH •• 1), 0., 'RV~~7.,AC,_I),D_,C
CC,C/BY(R4.AC,_l)*=' 'i'f'.u-, li:i. (K4:,AC._I),D+.C
CC,C/BY(R3.AC,UNTIL Rl,LT,O)*",BY(R3,.1).D_,BY(R5.AC._I,
UNTIL RO,LT.O),D_.C
FF
XX
(Alc)
Note: For "Do not care" functions
refer to timing chart below.
-
-
-
-
-
-
-
-
Store halfword
Read out and
regenerate microinstruction
CORE STORAGE -
-1-
-
Read out and
regenerate 'to operand'
Read out and
regenerate 'from operand'
I SDR
r--'- -,
L~2LC_~
~_8_1~
I
I
I
I
I
I
I
- -,
I
I
- -,- -.,
Read out
I'to operand'
---,
-I-
-
I
I
....
"Do not care" signals:
~Cycle C=::J
Cycle -=:J
r--.t--,
;-_ _ _.-,
SDR
r - -,- - -,
I SDR
r'---~
I SDR
I
L7_ L'2 _6J
L7_ ~~~...J
_5
(7)
SP
PPC
1--,
7 7
4 5
Data error
r~--
Data error
I
~---l~L-iI
II
1- - -
-1
I
I
Force trop-req 2;
Pl switching after the
current instr
Force trap-req 2;
Pl switching after the
current instr
-l;l
I
I
I
__ J
1
__ ...JI
I
Data error
I
:
I
I
Fl
__
J
I
Force trap-req 2:
Pl switching after
the (allowing instr
I
I
I
_____ JI
su
Suppress
ALU
Invert sw
f::l
T
Reset FDR
(lS reg 2)
....
r--- -,
I From Reg
I
I To Reg
Lu,uJ
- - --,
liAR
L...,
LB _O_I~.J J I
- -
--,
I
(lS reg 4)
I To Reg
I
I
I
I
L4_3f_l...J
I lS Reg 1
I 0
I
I
I
I
I
_L_
L!l_~10_2
0
1.,;_
I
No
; <2
Ye,
f - - - - - -....<
. . - _t-_.,
r-'
I MAR
I 4 3
L-
IL __ J
L---~AC
2 TJ I
_1 __
I- - --
--,--..,
I
No action
....
T
SAR 15
I
.... __ t __
Lo_O... O_S:
~.?ia9ram 5-~1. Subtra~! Packed B)!te/PertarmYacked 'tomplement (XX, ALe) (Part 1 of 2)
(03766)
2020 ~50,000 FJ;l:tIDM Vol
2
(8/69)
,---,
No action
I
L __ '
r--'----,I
1 SAR
~4_3.1~.!J
°
Decrement carry
turns on oux ~C FlI.1C Fli
T
SAR 15
1 0
°
Condition Code
0
Result is zero
°
Result is not zero
1
Overflow
llli.LiliI
Ye,
I
°
CC-Iatches
SP and PPC must be preceeded by a control instruction
which sets a previous carry (latch on) and sets the
condition code to 1000 (result zero).
I MAR
lC Fl 1..mld. lC Fl2 force end op Ale
lines and functions performed during .6. cycle time are snown by dotted lines.
I
I
I
I
I
T
°
r-----'I
liAR
LB_~,fl_2--J
L~~,3_1J
Decrement carry
turns on lC FL2
o
In AlC mode, further condition code setting is
suppressed when a code other than zero is detected.
AlC condition code can be result zero or not zero.
In AlC mode, overflow condition is set if the
'to field' length Is smaller than the '(rom field' lelllth
and the additional 'from' data is not all zero.
L ______ . . ACI
r--t--.,
I SAR
1 0
I
C I
I
No action
LO_ !...1"..2J
SAR 15
I
!
I
I
LUr-iLJ
I
I
I
I
ISAR
Functions performed during
_:!'tLU
I To Reg
I
I
I
I MAR
L4
r----'
°;---1
~
r
r-----,
r----- ,
I (lS reg 4)
No action
ALD
Nome
INa
I
T,ap~
Sen ..
_l~
~ ~Ne",~
~~
Reod
CycleD
Reod
T6
T4
T8
4
New/Curren. Pl
5
CEl~
7
T8
T2
~
~
T5
T6
Cycle
T4
T2
-
Pl', moy Hffeo
Fixed X-Add,."
lA412
'Ta'eg~
LtMAIL
I KB411
!
50
Do.o Switch to Op Reg
51
00 Re" to Add..,,~
52
I/o Ol'play Add.."
53
Allow St,obe
54
SENS
-
KAS41
£!!fI. SEN; ",obe)
BAI02
-
___
~ -'."'......~LSt'ob.
56
_ 57
P..v.nt
lSU Ch,
BAI03
Set CC ond Co"y
~-
-"lIow~ Settlng_
-
, . . .11
lAA412
o.«ement Co"y 0
!Mill.
163 I Aux lC_la.!£h.l
I KA413
164
i lC latch 1
IK~
165
166
I lC latch 2
I KA413
• End 0, Gote
lKA412
67 ISetAL~
I CCI22
, Check
I CC221
t Mod Check
I CC10i
Set SU Check
In
Set AW Check
LB
.Set"",~
~
_Set SAR Check
75 Set Inh Check
Function signals: aCycle
-== ~
~
168 I Set "cee.. Check
I 71
IF to ape,,"d Held I
I .A301
i 62 I Set lC (latche,)
69 ISe
.....
ItAny
u
~
.....
, T8"'::;
~eck
~
CC10l
m
ili..
J
Cycle_
00 not care" signals: t..Cycle 0
Cycle-=::J
• Diagram 5-61. Subtract Packed Byte/Perform Packed Complement (XX, ALe) (Part 2 of 2)
(0 3766A)
2020
2:
50,000 FEMDM Vol 2
--
~
""'""'- IAlC
100.....
----
(8/69)
~
1=
-
~iii.
.....
~
..
~
~ ~
-- ---....
when, ond op F , tum, on
.J!. not
~
.....
---
~
~
"""""=
,lC
------
k==
Ie, lC ;nd
'.lIS, n.o cI ,~ck
~
----
~
--------
0, got,
u,
.....
~
_'0 ~15,
no d ,~ck PPC
Microinstruction La out
LSreg214 : 6
high-order four bit position of the.
low-order byte in the 'to reg' and
the 'from reg' remain unchanged.
The high-order byte of the 'to
reg' is set to zero. 'From reg' and
'to reg' may be the same LS register.
Address check is ignored.
The packed decimal sign (Ioworder four bits) in the 'from reg'
is translated into the standard sign
according to the selected code.
The code is selected by the
USASCII latch (on'" USASCII,
off' EBCDIC). Tho USASCII
latch con be turned on by a
control/11/., bit 14, not bit 12;
and it can be turned off by a
controVl1/, not bit 14, not
bit 12.
7
AC
10
To Reg
11
12
13
14
15
SDS
From Reg
Ignored
LS,"" 4! 5 : 7
The sign is not checked for
validity. If the sign pattern is
invalid, the normalize function
is inhUmed. The invalid sign
is 'set into the 'to reg'
/'
OpCode
LS reg 4
before execution
[Joc:::r:d=:b
after execution
INST
MNEM
DB4Z
SDS
OPERANDS
• 4.Z
STATEMENTS ACCORDING TO STANDARD CEB O-1046_XXX
R4ff.",R"'. O_1l/RZ.IZ_1S 'l'ES'X FOR VALID SIGN AND NORMALIZE
FF
The standardized sign is set
into the low-order four bit
posi ti on of the 'to reg'. The
DD
Note: For "Do not care" functions
refer to timing chart below.
CORE STORAGE -
-
-
-
- - - -
-
Read out and
regenerate micro-
- :instruction
- - -
-
-
I
I
----~--- ~---
I
I
r--!'--,
I SDR
I
I
f--,~----!
LQ_BL4...lJ
SU
Suppress
~1!¥1~~fpt--- Normalize sign
B 0-.0
Suppress
BD_
ALU
Invert sw
I:l
-rReset FOR
(LS res 4)
(LS"o2)
iIAR---l
1--,
r
Ll..9+11.1J
I
I
:
I
I
I
I
I
I
:
:
: r---t-~
:
: MAR
I +21-_ _ _ _ _ _ _-..J
: L! _0.J.2.._2_'
I
I
I
rSAi!--l
I
I
L~_O_dL.1J
Functions
cycle time are shawn by full lines and 'unctions perfonnecf during .4 cycl. time are shown by dotted lines.
• Diagram 5-62. Set Decima! Sign (DO) (Port 1 of 2)'
(03767A)
2020 ~ 50,000 FEMDM Vol 2
(8/69)
---t------------------------------------
"Do not care" signals:
A Cy cI e r::::=:J
Cycle -.=J
--
Wdt,
n
I
Seo", T"p R'q,,,t Uo"
lAI03
2
lS N.w Pl Zoo. Got.
KASII
3
lS C,n.ot Pl Zoo. Got.
4
N.w/C""ot Pl
5
CE lS S,I.,t
CC222
-'
Fixed X-Add,,,,
lMI2
8
'To Roo' S,I.d
lA402
9
'F,om Reg' Sel.d
lA411
10
lS to SAO
KlWll
11
lS to MAR
T4
I
,.
Alo
Nome
INo
T5
,/
,.
N,w/,"",ot eL', mey dlff"
Cl'ili.
Cyole U
T3
TI
-
T6
T'
T8
-==
Cyol,
T4
T6
T8
17
T5
T'
6
112
I to FOR
13
lS to roR
lis
~
I1z=
K8401
LA7D2-712
MAR to lS
114
...~ Al.LJJI/O B,,) to lS
116
-
l::=::
lS Wdt.
r--
--- - ---
lA302/313
U7
118
Set Add,,,, Check
IRASOI
IJ9
il
47
I MMOI
Ito 'nh
, SAR
4R
I KB411
49
50
Doto Swit,h to Op Reg
I KB402
51
00 Reo to Add"" "",
KAS41
.52
JLO
53
Al1~
54
SENS
55
Sen.. Re,et/CTRl St.obe
56
..,7
'==
It--
o;'.'oy Add"" o.,t
St,obe
I StePbe
P"vent .lU and SU Cheok
(oi'pi SEt'S ,trobe)
BAI02
BAI03
-
-
0-
I/o "", to FOR
58
.59
60
61
62
63
64
,-
65
.66
.67
Set AlU Te.. lotch
CCI21
68
Set P,.."" Check
CCI22
.~9
70
LZL
~t
LSACheck
CC221
So IMd Check
, CCIOI
.~.• t
SU Check
72
Set AW Check
73
Set"" Check
74
Set SAR Check
75 Set Inh Check
Function Signals: o.Cycle Em
~
1\
CCI02
>Any,hook
CCIOI
Cycle _
"Do not core" signals: LlCycle
• Diagram 5-62. Set Decimal Sign (DO) (Part 2 of 2)
c:J
Cycle
II::::J
(03767A)
----
~
2020 250,000 FEMDM Vol 2
~
-- -
' TB...IIi~
==
(8/69)
.=.=.
-
-=-= ~
-...-
-
, TB...IIi~
I-
Cyol, 'ofn,xt
I
I
T6
T3
T'
T5
Microinstruction l.oyout
SOS
10
.The pocked decimal sign in the
low-order four bit position of the
byte addressed by the 'from reg'
is standardized, according to the
selected code, and set into the
low-order four bits of the 'to reg'.
The high-order four bits of the
low-order byte in 'to reg' as well
as the 'from' byte remern unchanged.
The high-order byte in 'to reg' is set
ta zero.
If the AC bit (in3truction bit 7)
is on, an address check occurs when
the 'from address' is outside customer
area. The 'frdm address' is not
updated.
LS",g211:21 3 : 41
remains unchanged L _ _ _ _ _
The code is specified by the USASell
latch (on = USASCII, off"" EBCDIC).
The USASCII latch can be turned on by
a controVll/, bit 14, not bit 12, and
can be turned off by control /11/,. not
bit 14 and not bit 12.
Read out addressed byte
Tested for being A to F
otherwise data error
-
--a:
Normalize sign (EBCDIC)
~:~"~';t; :
The sign Is not checked
for validity. If the sign
pattern is Invalid, the
normalize function is
inhtbited. The invalid
sIgn is set into the 'ta reg'
LSreg4 0 · 0
after execution
o
Remains unchanged
~ (+)
C
o
11
12
13
14
15
From Reg
Code
I
If on, the 'from addr' is checked
that it is not outside customer area
(+)
T
9:C
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O_I046.xxx
D94A
SDS
4.2I,AC
R4*=R4.0.11/BY(R2,AC).4.7 TEST FOR VALID STGN ANn NORMALIZE
FF
ox
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
6. Cy cI e c::::::::r
CORE STORAGE -
-
- - - - - - -
,,
,
----
Read out and
regenerate microinstruction
-1-
- -
r
r
r-
_:1 __ ,
Read out and
regenerate
-i-T~~'
-----------t---
Cycle
S;;;e
trap req
------ ---
r--'!--,
I SDR
I SDR
I
I
I---r---'
L~_9..J!_AJ
I
I
!-----j
Lt !.d. ..2J
~~~~tp1--~
SU
c
Normalize Sign
Suppress
BD--.D
BD-+
AND
ALU
Invert sw
E:J
,---
T
Reset FOR
----,I (LS reg 2)
(LS reg 4)
I From Reg
r
I
I
r
Ll_2+:!._4.J
r
(NSI)
,
r
,i
i ---,I
,..-,
Ll_2-t 1 _!J
L_..J
r-I MAR
t----'"
I
,,
r--.t--,
SAR
I
r
I
r
r
LL~..L!_4J
T
SARIS
Functions performed during cycle time are shown by faJilines and functions performed during
• Diagram 5-63. Set Decimal Sign (OX) (l6art I af 2) ,
a
cycle time are sI'towrl by dotted lines •
(03768A)
2020 ~~,OOO FE~M Vol 2
(8/69)
AC I
~--------------------
-=:J
R"ad
.
W6'e
ALO
Nome
INo
T6
.T4
,
Se'" T,op Req'",' U,e,
2
LS New PL ZO," Go.e
3
LS C,"eo' PL Zo,e Go'e
4
New/C,,,e,' PL
5
CE LS Sele"
,
,
IZ
T8
T3
T4
Cyole
T6
T8
I LA'03
r-
KA511
',moy dl 'fe,
N"I""e,'
--
. ",Cyole
Cyol" 0
T3
---
T6
T4
.Tt!.
r-
I CC22,-
7
F;xed X-Add,."
LA4'2
'To Reo' S.lee.
LA402
9
'F'am R.a' <;.,Ie"
LMll
LS
'0
SAR
KB41l
LS
'0
MAR
,
I"
I
"""==
KB401
\ •• FOR
"
13
~
;'a TOR
114 I MAR
'0
LA702~712
LS
115 I s.. ALU (I/O B,,)
LS W,lte
'6
~
I----
LS
'0
LA302i3'3
'7
,
,. Is••
""A,"n
I RASO'
(,h.,'
1'9 I "aneh Ga
I '"
--
0.--
~
2-
~
I----
~
~
---
---
I----
f--
--
---
----
i- -
"'==
~
f--
I----
T6
TB
T8
---
~
0...-
AC bit
...02
I
In"emen' bv 2
12'
HI, :h/low
I RAS02
--
---- -------
...---2---
T5
--
6
8
'"
T4
I RM03
...a,
I??
n.
I"
Oo,,"_n' hv ,
I RA402
124 ' P,ev.n' Mod-SAR-I,h Cheek I KASll
I"
m, •• I.h
I MA402
IMA4O'
SO. to O. Reo
I KB'02
Preve,'
126
27
,.
S'~O!Ie
U,e
I '9
1KB402
I 30 I SO'.o TO.
3' I Ei.h. Shift ('nno.1
I 32
I ShUt bv 2
~4
I RB'6'
34
35
N~mollze
I-- -
- ---
Bv•• ~ Slo,
-lS'aO-15
;'0
---
~hif'
U-."
I R8162
Na Shift
" I Te,' Poek.d
~
1.8162
defl,ed
I-
-0-15., O-lS
I Na' ,hi"
8 if SAR Ii,
0-15
I"
I R817'
37
38
ALU to FOR
'9
Re~.
40
Invo" Swl"h Ca"ml
I AA303
I AA303/KB4"
I R8301
FDIV .. "", FO. 0_7
42
-A
AL' I ('~0.1 Gat.
Addit;onal
44
Six
s.t Corrv Loteh
e~ed;~
47
--
I True 0-" -/.rue/
-AIA,y ~heek
CC10'
)
Cycle_
...
Do not core signals: 6.Cycle c::::J
• Diagram 5-63. Set Decimal Sign (OX) (part 2 of 2)
Cycle ~
(0 3768A)
---
~
- ....
'T8~ ~
----
2020 ~ 50,000 FEMDM Vol 2
~
Ii:
~
~
(8/69)
-
, TS....Ij;
---
--
"'==
L
"-
~
~
--
---
---=
--
~
, rs..:iiiiii.
"-
Cy~le
a of n;x'
I
The code is specified by the USASCII
(on = USASCII, off = EBCDIC). The
USASCII lotch can be turned on by a
control/l1/, bit 14, not bit 12, and
can be turned off by a control 1 1/,
not bit 14 and not bit 12.
The pocked decimal sign in the laworder four bits of the 'from reg' is
standardized according to the selected
code and set into tne low-order four
bit position of the byte addressed by
the "to reg". The high-order four
bits of the 'to' byte as well as the
'from reg' remain unchanged. If the
AC bit \instruction bit 7) is on, an
address check occurs when the 'to
address' is outside customer area.
The 'to address' is not updated.
F 1(+)
LSreg214;61s
remains unchanged
c=
Tested for being
C
A data check occurs when the loworder four bits in the from reg do not
contain any hexadecimal value / AI to
lS
~9 4
I0
: 1
remains unchanged
Normalize sign (EBCDIC)
is not outside customer area
[~~ ~ ,_
- _ Read out addressed byte
IF/·
INS'!'
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O_1046_xxX
D9C2
SDS
4I,Z,AC
BY(R4,AC).4_7*=R2.12_1S TEST FOR VALID SIGN AND NORMALIZE
FF
After execution
XD
Note: For "Do not care" functions
refer to timing chart below.
Read out and
regenerate microinstruction
CORE STORAGE ----+
Read out and
regenerate
'to operand'
-,-
Read out
'to operand'
-
I
I
I
I
~ - j-....,
J
SDR
~5_:..L9_~
'--lFe
Data error
I
:
1
I
I
__ J
I
I
I
SU
ALU
Invert sw
~
4~
Reset FOR
r-----..,I
t'-----,
'AR
L8_
I To Reg
I (LS reg 4)
1 To Reg
I
I
~O_~J.2_~-.1
LO_'_I~~.J
r.----,
J
J
,--1
~,.£}~
I
I
I
I
I
I
I
:
I
I
I
I
I
I
I
I
1 +2
I
I
n-- L
rMARt. -~_ _ _ _ _ _ _----'
L8_0_1~ 1_1
-.L __ ~r----,
AC I
I MAR
'0
1
2 3 1
I
L---t--.J
L. _ _ _
J
J
rMARj --..,
: 0
L
,
I
,
I
I
15AR
I
L0_ 1_J.~
~J
~
T
Diagram 5-64.
time are shown by full lines and functions performed during 6 cycle time ore shown by dotted lines.
Set Decimal Sign (XD) (Purt 1 of 2)
(03769)
2020':: 50,000 FEMDM Vol 2
I
J 0_____
1 2 3:
L
SAR15
Functions performed during
I
1
r--J- -,
-..,
(8/69)
r--..,
2 3 :- - - -...; AC
_ _ I _ _ ..J
L __ ..J
I
I
rSA' 1_
Store holfword into
position addressed
by 'to reg'
T
SAR15
-
-
-
-
-
-
- -
~
"Do not care" signals:
llCycle c:::::::::J
Cycle -=:J
-
-
-
-
-
- -
-
---
-
-
-
--
_Re",,,AlD
Name
INo
:"
13
I
Seme T,op Reque.t Une.
Z~e
2
lS New Pl
3
lS Cu"ent Pl Zon. Gote
4
New/Cu"eot Pl
5
CE lS S.I.,t
T5
I7
T6
Gote
He,
ccm
~~
---
---
KASll
.N, "",u"."",- L'. moy
c:yd
T3
T8
LAl03
.
W,lte,
Re~od
Wdt,,-
,0
T2
~I!
T5
T2
T3
T4
0-...~
6
2
~"'ed X~~d,."
lM12
8
'To Reo' S,leet
lM02
9
'F,om R•• ' Seleet
. I()
l~oS~
11
lS to MAR
12
lS to FOR
.....
IlA411
=
KB411
-==
13
lS to TOR
14
MAR to lS
'5
Set ALU (1/0 Bu.) to lS
16
lS Wdte
LA302/313
18
Set Add,." Ch.,k
RASOI
19
"on< ,Go
RAS02
120
In".m.nt by 1
RM02
21
In"emeot by 2
22
De"emeot by 1
I---
17
~
=
---
--
.....
LA702-712
,--
0-...-
-===
~
~
I--
==
"=='"
K8401
~
,-l~
I AC blt,~
=
Hlgi/low
"'=
r----
-
---
---
---
'C bit
RM03
I RMOI
! 23
0.
LM4~
! 24
P,e'ent Mod-lsAR-lnh Ch.,k
I KASI
26
P,e'ent StO>'o•• U..
I MA402
27
SDR to Inh
MA40l
28
SDR to Op Reg
KB102
30
SDR to TOR
K8402
31
Eight Shift Con"ol
RB162
32
Shift by 2 a 4
RBI,
33
N" Shift
RB162
34
Te.t Pocked Byte a Sign
RAS02
35
No,mollze Sign A,II,e
25
-
29
.lQ
SUOD
Und, FIned
=I-- =- I--
15 t~ 0-15'
---
"0,
u-,o
~lft
0-...-
:
;'"
"'=
O·
ALU to FOR
I AAJ03
39
Re.et FDWReteln FDR 0-7
I AAJ03/K8411
40
Inve,t Swlt,h Cont,ol
I R8301
42
ALU Cont,ol Gote
AA301
43
Addltlonol CD"y
AA302
44
Six Ca,.,tlon 8-11/12-15
45
Set Con, lot,h
46
Set Condition Code lot,h..
.£
AJ,~
f),
I
err,
FL turns :.n jf bits 2-15 are
-=.,::
Not tc~e, not In ,,,t = IFF~FI
to 8-15 il ,no
SAR 1:
"0" Ih;H If nl\l<
~
50
Doto Swlt,h to Op Reg
51
00 Reo to o.ddee" Bu>
52
I/O D;,ploy Add"" Out
53
I K8402
KA541
I--
t----
-
Allow S"obe
SENS
ISh
(o;.pl SENS
SAl 02
~~ ~ S~,"" R..et/CTRl St,obe
56
P"vent "U
,,!il
I/O Bu. to FOR
I SU Che,k
BA103
-
0-...-
58
.2!
60
61
62
~
64
~5
---
~
67
Set ALII Ta" lot,h
CC121
68
Set P'oc." Che,k
CCI2"
69
Set lSA Cheek
CC221
70
Set Mod Ch.
71
Set SU Che,k
72
Set ALU Cheek
73
Se" Bu~he,k
74
Set SAR Cheek
75 Set Inh Che,k
Function Signals: o.Cycle IZi2I
i
CelOl
CC102
~
~
I
-'
• Any Cheek
CelO1
Cycle _
"Do not core" Signals: .6.Cyc::le c:::J
• Diagram 5-64. Set Decimal Sign (XD) (Part 2 af 2)
Cycle-=:J
(03769A)
-
~
- .....
2020 L 50,000 FEMDM Vol 2
=
(8/69)
~
-- .....
-
,TO,
..!l;;
-
~
~
~
=
~
"=='"
==
....
I.i..
, 'T8..Jii
~
iii.
....
-
, T8...ii;
..........
Cyde,O of nex>
"'mln"~,,,on
'I
The packed decimal sign in the faur lawarder bits of the byte addressed by the 'from
reg' is standardized accarding to the selected
code and set Into the four low-order bits of
the byte addressed by the 'to reg'. The four
high-order bits of the 'to' byte as well as the
'from' byte remain unchanged. 'Fran ref!
and 'to reg' may contain the same address
ar may be the same LS register
If the AC bit (instruction bit 7) is on, an
addrus check occurs when one of the operand
addresses is outside customer area. The
operand addresses are not updated.
The code is specified by the USASCII
latch (on"" USASCII, off "" EBCDIQ.
The USASCII latch can be tumed on
by a ctrl/ll/, bit 14, not bit 12, and
can be nrmed off by ctrl/11/, not bit
14 and not bit 12.
A data check occurs when the fout '
low-arder bits of the 'fran' byte do
not contain any hexadecimal value
lA/to IFI
Microinstruction Layout
L~_~~_
14:
LSreg2 unchanged 2
remains
Read out addressed byte
Remains unchanged
- - - - ~ (+)
----I
D
10:
112:3
Normalize sign (EBCDIC)
:
C
SDS
11
12
13
14
From Reg
15
1
If on, the 'from' and 'to' addr's are
checked that they are not outside customer area
Tested for being
A to F, otherwise data error
LSreg4
remains unc~h::'on':-:.~edr'--t,............"....J
10
To Reg
AC
Op Code
(+)
Before execution
L ____ _
Reod out 'addressed byte
- ~
I
FF
• Store
After execution
xx
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
Read out and
regenerate microInstruction
CORE STORAGE - - .
Read out and
regenerate
'from operand'
-II
r.--J.--,
ISDR
Read out
Ito operand'
-- TT---
I
I
r--t--,
,
,SDR
,
r-r---~
L~2J..f_AJ
l I-~rl ~"
r--t--,
'SDR
,
""1
1-'_ _ _ _ _
L5_.?.J.!._~
.------l-FLI
___ J
Force trap-req 2;
PL switching after
the current instr
SU
C
AND
Invert sw
F::l
1
Reset FDR
r-----' (LS
: From
fiAR----l
~-,
L.. _ll..tQ.1-1
!
,
I
I
I
I
I
I
I
,
I
I
~8_Q..J.'O_t.'
,SAR
,i
I
.J
L.._.J
.
(03770)
I
: MAR
~----':-;-cl
1+2_~J
~_..J
LO__
r--:t--,
'MAR
,
:
: SA~
:
1I
LO__l.L2_]j
SARIS
SARI5
--~-r
T
2020 L 50,000 FEMDM Vol 2
(8/69)
I
r-
j-'
AC I
~---- ...
I
r--t- -,
-,
I
L~_1+~2J
I
I
and functions perfonned durinR .:1 cycle time are shown by dotted
Diagram 5-65. Set Decimal Sign (XX) (!'art 1 of 2)"
,I
I
I
I
:
2 1
I
,
r--j---,
,...-,
I-----.,..AC I
r-- L
'4
I
I
I
I
+__1 1
I SAR
I
I
,,
I
I
L8_,402
1A03
122
o.c..m.nt bY
LR
I RA402
'"
P...,.nt Mad-SAR-Inh Check I KASI
124
==
LA702-712
1.4_ MAR to LS
16
-==
ILMll
~
IMOI
, 2
125
~
126
".v.nt St ...... U..
127
SOl to Inh
MA401
128
SDR to O. Ilea
KBiOO
30
SDR to TOR
K8402
31
Eloht SWt Con"al
RBI 62
32
ShUtbY2",4
RBI6·
33
No Shift
-
I 29
f::= t-:'~
Un~
I--
r-
. 0-15
--
~ot
",~ign
RASOO
35
N«malize Sign Actlv.
36
50..,. .
RBI71
AA303
. 0-15
IS
-
.hHt
-
3B
ALU to FOR
IIe.. t FDR/IIetoin FOR 0-7
o.A303lK8411
40
Invert Switch Con",,1
RB301
O·
Re.et
Not ,1oue, not !nvert = /f ,FFF/
AL'I Conlrol Gat.
43
Additionol Co"y
'if bib
,
I
,if
) SAR 15
. 0~15
, to IS a,,; not 'ion. 'A/to/F/
-- --
U-I,
IAA301
.2-15
0-7,
TNe 0-15. = /tNe/
Not Ioue, not inve,t = /FI'FF/
41
42
,'noSARI5
·0.i5
~ I Data .'" . FL tu'n.
(T.t.iE/»
37
39
Not
~
RBI 62
.M. .J.!t P"",,,ed.lhl.
0-15
I T,u. O-I! =/tNe/
[0'-
OE
AA302
44
Six Correction 8-11112-15
45
Set Cony Latch
46
Set Condition Code Latche.
47
ALU to Inh
IMA401
48
ALII to SAR
I K8411
LK~
AA402
~dtaO-
'(no SAR 15) 0,8-1., (SAR 15)
49
50
Oato Switch", Op~.
51
Do Reo to Add,. . Bu.
52
I/O Di•• lav ,"doe.. Out
53
,11,
M
SENS
55
Sen.e R..et/CTRL Strnbe
KA541
,Simi>
ISt'abo
.56
","vent. LU and SU Check
, 57
110
..
I~
SAlOO
(Dbpi SE ~S ."ab.)
SAl 03
• FOR
r--
--
--
--
-
-
58
60
~
62
63
64
~
----
66
67
Set AU I T••t Latch
CCI21
6B
Set Process Check
CCI22
69
Set LSA Check
CC221
70
Set Mod Check
CCIOI
71
Set SU Check
CCIOO
n
Set AW Check
.Z!
Set
..Iiij.
• Any heck
au. Check
.R ~,
'Check
75 Set Inh Check
Function .ignols: ACycle
CCIOI
m
C)':Cle _
.
"Do not core " SIgnals:
.6.Cycl~
• Diagram 5-65.. Set l>ecimal Sign (XX) (part 2 of 2)
c:J
Cycle-=:J
(DmDA)
-
~
---
2020 ~ 50,000 FEMDM Vol 2
~
t>z=
.T8..ii
=""
(8/69)
Ii..
~
0.---
~
~
t>z=
--...
==
..!::JL
----
~
~
~
----
~
~
--
".,
~
;.l.il.
---...
;!..l..
---
~
HALT
Microinstruction La out
10
Op Code
The CPU stops after executing
the instruction. The 'from teg'
is displaye.d in data register P,
I, U, L. The 'to reg' Is
displayed in data register E, 5,
T, R. The CPU can be started.
again by operating the start key.
The next microinstruction to be
executed will be that addressed
by the updated tAR (HALT
instruction address + 2).
To Reg
11
12
13
14
15
From Reg
lS«g411:213:4
remains unchanged
c:
lS",g2IA: B I
D
remains unchanged
Display
A
C
D
CPU stops
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O_1046_xXX
DC4Z
HALT
4,Z
FDR=E,S, T,R:*=R4, TDR=P,I, U,L*=RZ
FF
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
ACycle c==J
Cycle -=:J
CORE STORAGE ---....
-
-
- -
-
Read out and
regenerate microinstruction
-(-
- - - -
-
-
I
I
,.-_!_-,
I SDR
I
I
!--1,-----'
LQ._C.J..1..1J
SU
-
Display
retained
during
CPU stop
----------------
Invert sw
~
CPU stop
fiAR"---l
I
(LS reg 4)
1--.,
I
L~_0+.Q_2J
:
i
:
~
~
I
:
I
I
I
I
I
I
I
:
I
r--'!--,
I SAR
I
I
I
L~.E.L~JJ
Functions performed during crda time ore shown by full lines and functions performed during t.. cycle time ore shown by dofted lines.
Diagram 5-66. Halt and Display Halfwarll (Part 1 of 2)
(03771)
2020 ~ 50,000 FEMDM Vol 2
(8/69)
_1
ALD
Name
INo
S.n" T,ap '.q""" Lin.,
2
~ N.w -"'-
lS Co".n' Pl Zan. Go"
-'
CE LS 5.1."
T6
-=--=
KAS11
,w/m,.n' PL ; may
N.w/Co".n' PL
r--
'm.,
7
F'x.d X-Add,."
8
'To '.g' S.I.,t
•
'F,am 'eo' Sel."
LS to SA'
Ul
lS to MA'
-
--
<412
LM02
<411
==
KB411
KB401
12
> FD'
1-'3
LS to TO'
1,4
MAR to LS
i 15
Set ALU (I/O Bu.) to LS
==
-==
LA702-712
r--
'W,it.
.--
LLA30Um
17
118
,.
S.t Add,." Check
I 'ASOl
,"on,h Go
0.502
120
In"emont by 1
~402
121
In "emont by 2
<403
122
De"oment by 1
I 23
nent
I 24
'"
T5
T4
T6
I CC222
6
110
--
T4:YdeT5~~
-
T8
LA103
Zan.Ga'.
--'4
~T4
'eo'
- - ----
,----
f--
1::::==
,----
f--
~40\
I RA402
,2
P,o,.nt Mod-SA'-Inh Check I KAS1
I 25
126
P,event Sto,OO. U..
I 27
SDR
'0 Inh
I MA402
I MMO\
I 28
SO, to Op Re.
I KOl02
SO, to TO'
I KB402
-
2.
30
31
Eight Sh.ft Con"ol
"'62
32
Sh;n by 2 '"
'01,
33
:J4
I""-" F~ 1 -
-
-
'BI62
> Sh.ft
RA502
Te.t Pocked Byt." S'9n
35
N",mal'ze S'gn A,t've
36
SoPP""
'BI71
'}Z
38
ALII to FOR
AAJ03
3.
Re.. t FDRlReta'n FD' 0-7
AA303/KB41'
40
Inve,t Switch Cont,ol
'8301
True 0-1 ; = /t"e/
T", 0-"" = /true/
41
42
. 43
AA302
44
S'x C",.,tlon 8- 1112-15
45
Set Catty latch
,Conditl,
> Code
10E
10E
I AAJO\
W Con"ol Got•
Addit'onal Catty
AA402
lat,he,
47
ALII to Inh
I MA40\
48
ALII to SAR
I KB411
50
Data Sw'kh to Op Reg
I KB402
51
Op Reo to Add,e" Boo
52
I/o OI.,loy
4.
KA541
t---
~dd,." Oot
-.53
\I
54
SENS
55
Sen.. Retet /CTRI. St,obe
56
p,.vent AlU and SU Ch"k
57
liD So
·51<
ISt,obe
I(OI.pl SENS .',obe)
BA102
BA103
,FDR
--
58
.,.
End Op Cyde 0
I KM03
60
Hold 'oo Condit'on
I KA521
61
Delta P,o,"" lal,h
KA303
62
P"" ... Lat,h
.--
-
,
> 'n
op
---
Cg
-
- -- -
-
~art=
r-=
--
----j
---I
./
L63
64
--
65
66
I CC121
_67
Set ALU T..t Lat,h
68
Set P,oo... Check
CCI22
Set lSi< Chook
CC221
70
S,'M,ICh
CCIOI
_:>1
.~t S~ Check
CCI02
6.
n
Set AW Check
73
Set Bu. Check
74
Set SAR Check
75 Set Inh Check
Function signals: ACycle
~
\
Ani ,hook
CCIOI
)
~
Cycle _
"Do not core" signals: LlCyde t:=l
• Diagram 5-66, Halt and Display Halfward (Part 2 of 2)
Cycle-=:l
(03771 A)
----
~
2020 250,000 FEMDM Vol 2
~
-Cyde 'of ",xl
(8/69)
~kro'"'t,",!'on
(If
"0:',)
T3
T4
T5
Microinstruction layout
SENS
A byte or holfword provided by a
sense source (CPU or attachment)
is set into 'to reg'. The sense
source is selected by the SENS/
CTRl address in the low-order byte
of the instruction (256 different
sources are possible). The SENS/
CTRl address is set on the address
bus. The sense byte is set on the
data bus in the attachment to
which the current SEN~CTRl
address is co-ordinated. Except
for the halfword SENS's (SENS/
CTRl addresses /14/ qnd /IS!), the
SENS/CTRl address on the
returning address bus is exclusive
ORed with the original SENS/
CTRl address in the instruction. If
both addresses are identical the
result is zero. The result is set
into the high-order byte of the
'to reg'.
I Op
Instruction
tode~
OpCode
10
11
12
13
SENS/Ctrl Addr
To Reg
14
15
SENS/CTRL address to attachment - - - .Activates sense source
mL
1-.-0
2501
- Wk g
lS",4
I-',ed
Check
I
Ceed
'"
Preread
I'd
eo y
13:AIB:41
::f::"C:UH:": 0: , ;C-0-
1
direct addressing
2560
',ed
"I P~",h
"y
1442
',edy
and
not ck
I
Wkg
_ _ _ _ _ _ _ _ _ _----.l
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB
E423
SENS
4. X'Z3I
R4
,,=
O_I0-46~XXX
loor/SENSE 23
I/O
after execution
Direct
Addressing
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
Ll.Cycle c::=::J
Cycle -=:J
Read out and
regenerate microinstruction
CORE STORAGE - - .
Halfword SENS
SU
No action
AlU
Invert sw
""':";"--"'--, - - - - - - - r'D--"~-,
In
Out
Add, B"
~ ~ ~ ~:,->.
'----,.-,.---'
CPU SENS
'/0 SENS
(Data if halfword SENS)
Data Bus
r-----.,
: IAR
~_,
L~_O+~_2J
!
,
Halfword
,,
Note: Except for halfword SENS, the high-order byte in
'to reg' must be zero. Otherwise an even number
of bits may be lost or forced on the oddr bus.
Compare the DR-P, I display with the original
microdevice addr (op reg display)
I
,,
r--t-: MAR
: +2 \ -_ _ _ _ _ _ _--'
L.
18_ _0 0_ _21
~
,--I SAR
I
--,I
I
:"'8_-9.Lt?._~
Functions performed during cycle time are shown by
I lines and functions performed during .:1 cycle time are shown by dotted lines.
Diagram 5-67. SENS CPU I/O (Direct Addressing) (PI,.t 1 of 2)
(03772A)
2020 L 50,000 FEMDM Vol 2
(8/69)
No
ALD
Nome
I
Sen,e T,a. R'q,,,t Line'
LAI03
2
LS New PL Zone G""
KASll
3
LS C,"ent PL Zone-"at__
4
N.w/C,,,ent PL
5
CE LS S.leol
~
~T4
Wdte
T5
,.
T6
Lyo I,u
13
"'"==
No> ~'''.nt
,.
-
'"
H
T6
7
Flx.d X-Add""
'To Rea' Sel."
LM02
9
'F,om R.g' S.le,'
LMII
I to SAR
II
LS to MAR
-
KB4ll
"""""'"'"
K8401
13
LS to TOR
14
MAR to LS
'5
Set ALV (I/O 80.) to LS
16
LS Wdt.
LA302/313
IS
Set Add'e" Che,k
RASOI
19
",on,h Go
-
==
LA702-712
r--
c-::--
17
---
-
----
1/0 b"
; if 1/( i SENS
_RAS!l2
120
In«ement by I
>402
121
'n"ement by 2
; RA403
22
De"ement
23
De"ement by 2
24
>401
P'ev.nt Mod-SAR-Inh Check : KASI'
by
i
RA402
25
26
P"vent Stocoge V..
i MA402
27
SDR to Inh
IMA401
2S
SDR to 0. Reg
I KSI02
30
SDR to TOR
I K8402
31
Elaht ShHt Control
I RBI62
32
Shift by 2 oc 4
I RBI61
33
No Shift
I RB162
34
Te" Pack.d Byt. oc Sign
---
29
36
---
12
ll~ LS to FOR
~
Vnde >ad
=:-
0-1
,
,0-1
I
RAS02
NocmaBz. Sign Actlv.
8-15, I SENS/C
I RB171
5'00'""
, odd,
'0' I"
0-"
Not" / '4/
0' 115/
defln., h"lfwocd SE,",',
37
38
39
'40
I to FD.R
: M303
.... t FD~Re"'ln FOR 0-7
, M303/KB411
Inv.. t Switch Cont,ol
I RB301
ALV Control Go..
I AA301
T,",O-' ,5~e~
41
42
, 43
Additional Ca"y
Six Coneetlon
45
19E
M302
1/12-
Set Ca"y Latch
AA402
, Condition Cod. Latch••
46
47
AL
48
ALU to ;AR
MA401
to Inh
K841l
49
50
Data Switch to ()p Rea
K8402
51
0. Reg to Add"" 80.
KA541
52
I/O O;,.lay Add"" Oot
53
.M
55
f::::::=
Allow St,obe
~ENS
IS"abe
SI~
~
BA102
,T8~;:"
Sen .. R...t/CTRL Strob.
p"
57
.ell
, SV Ch
:=,
BA103
f
I/O So. to FOR
{
58
CPU
((CPV SE "5'.)
~
SEN~
a,w.
I/o SENS
'T8~ iiii.
59
60
61
62
63
64
65
66
67
Set ALU T..t latch
CC121
68
Set "'ace.. Check
CCl22
~9
Set LSA Check
CC221
70
.L!
T6
; may IHee
6
-'-"-
T5
T4
CC222
S
S. 'M, ,Ch
CC10l
Set S.l! C""ck
CC102
n
Set AW Check
73
Set 80. Check
74
Set SAR Check
75
Set Inh Check
Function 5lgnals: .6.Cycle
• Diagram
~
,\
\
!
'>
!
CC101
j
r2Z?I
Cycle_
I
'
Do not core " ~Ignols:
~Cycle
CJ
Cycle-=::J
5-67. SENS CPU I/O (Direct Addressing) (Part 2 of 2)
--
~
--
An; chock
(03772A)
2020
~
-
r
P"v.nted
' SEN S
\p;mnt AL~;nd-
~
C;"' {
---I
"
I
I
50,000 FEMDM Vol 2
(8/69)
--
~
: no check If halfwo" i SENS
_ I f .om bit, 0-7
I
!
\lUi
0' .. n.. bit, 8-15 .ven 0; do,ble .. loct
I
Cycle 0 of ne0t
I
I
T5
T6
T.
A byte provided by a sense source
'(CPU or attachment) is stared into
the byte addressed by the 'to reg' •
The 'to address' is incremented by
1. The sense source is selected by
the SENS/CTRL address in the laworder byte of the instruction (256
different sources are possible). The
SENS/CTRL address is set on the
address bus. The sense byte is set
on the data bus in the attachment
to which the cl,I'I'ent SENS/CTRl
adchss Is co-ordihated. The
SENS/CTRL add"ess on the returning
addreu bus is exclusive ORed with
the original SENS/CTRl address in
the Instruction. If both addresses are
InstructionlOp (:ade
identical the result is zero. The
result can be displayed in the
high-order ALU byte.
I
2 : 3
Sens/CTRL address to attachment
10 11 12 13
SENS/Ctrl Addr
- - - . Activates sense source
23
LS , .. 4 12 : E
before execution
LE
: 2
T
I
rNwt
M N EM
OPERANDS
STATEMENTS ACCORDING TO STANDARD GEB O.I046_XXX
BCll
SENS
4I.X'Z3'
BY(R4.+l) * = SENSE 23
14
15
Before execution
Read out addressed byte
+1
~
I
I
I
'
1/0
Indirect
Addressing
Note: For "Do not care" functions
refer to timing chart below.
Read out and
regenerate microinstruction
CORE STORAGE -
Store halfword into
~il- ~l~~
-,,
,
I
r.-,SDR
-- ------t-------------------------------------
I --..,
I
I
I
L~.8.J..I.!i.J
FOB B
SU
ALU
"'1
\~
Note: The high-order result byte must be zero;
otherwise an even number of bits may be
/O$t or forced on the addr bus. Compare
P-I displqy with the original microdevice
address (op reg display)
[
../
Invert sw
AdHu.
~= =-=-_~L.:_-'_;:;~_-:i-:;{_-:_-:~:_-:_-lIf--_-:_-_-_-_-_-_-:_-:_-_-_-_-_-_-I{_-_-_-_-_-_-_-_-:_-:_-_-_-_-:_-_-_-_-_-_-_-_-:_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-:_-_-_-_-_-_-_-_-_-_-_-_-_.,.. :
_ L __ _
=.,---___
=- =- ~ =-=- -=- =J
...L._ _ _ _ _ _ _ _ _-, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - - - - - - - -
-
-
- --.,
~Dat~a;b"'~,;;,=.::;----L./.!::FO:LV------lli--,r;=--::-:-:-::-!--.: :..,- ______ -- _ - - - - - _- - - - - - -- - - - - - - - - - - - - - - - ...
SENSstrobe
L
rr;o.;;- -i
fjAR----i
I
.... -..,
L'L~~.QJJ
:
I
rr;R"";-- i
I '
~~l;I~J
L!!..JL..,rJ!-;L.I (NSI)
,
I
I
I
I
,
,
I
,
I
,
I
I
I
,
I
I
I
I
,
'
,,--!-,MAR
I
r +2
I
L~.Q..LQ..£
:
r.--!_":'r-,
I,
,MAR
1-_ _ _ _ _ _ _- '
(LS , •• 4)
I
L~l*~1J
I
:
1+] 1------'
I
, 2 E
E 2 I
I
L._-t-_.L._-'
I
,,
I
I
.. __ :t __ ,
r:--~--,
tSAR
I
I
I
L!.2-J.t!..lJ
.SAR
I
I
0
L£.£J..t.£J
T
SAR 15
Functions performed during cycle time are shown
performed during .6. cycle time are shown by dotted lines.
;
_.J>iagram~.
SEN~PU I/O .!I.a.direct ~ssin9)
;
(ear.t.' of 2) _
(03773~
2O~50.000~DM Vo~ (8/69) ..
_ _ _ _ _ _ _ oJ
"Do not care" signals:
.6.Cycle c:::::J
Cycle -=:J
I I S.n,. T,,,, ReO'." Un.,
2
3
14
5
~
ALD
Nom.
INo
I
Cycl.O
17
12
TO
T3
T4
f5
1'6
I LS New PL Zone Go'e
I LS C,"en' PL Zon. Go'e
-=
I.r--
KASII
I New/c,,,en' PL
......
TO
I LAI03
17
TO
17
TO
Now/c,,,en' PL, moy lilf..
I CE LS Selec'
ICC222
6
7
Hxed X-Ad.,,""
8
'To Reg' Selec.
9
'F,om
R~'
111
LS'o MAl
~
b""""""
KII411
LS.o SAl
r-
KB401
;'0 TOR
13
I I_ I MAR.o LS
---
LA702-712
f---
Set ALU (I/O B,,) to LS
1,6 • LS Wd'e
f---
Set Add,e.. Check
I RAS01
I 19
lI
I RBI62
33
NoSh;f.
34
Te,' Pack.d &v•• '" Sian
RA502
as
N_all.. Sign AcU..
~
s,PP''''
I RB171
38
ALU'o FDR
IMa03
39
.... FDRI"";n FOR 0-7
I AA303iKII4I'
40
In.... Swl.ch Can"ol
I RB301
8-15
'SI
I T",e 0-1: , =/'",e/
IT",e 0-1:; =/,,"-e/
oil
42
ALII
..
_3
c.
'''',
'OE
lOE
lAA301
Additional Corry
AA302
Six Carr.. Uon 11-11/12-15
4S
Se. Conv lmch
46
Se. Condition Code Latc,,",
AA402
147
AL Ito Inh
IMA401
~
..A!.U to_SAl
I KMII
6- 5 to 0-7
,SA.R
lo,6~l,
49
Data Switch '0 0.
Iso
151
W
W
Reo
I KII402
au.
lILo OI",lay Ad~ 0,.
00 Roc '0 Add,...
KA541
-
It---
Allow S"abe
1501 i .sENS
IS"....
BAI02
~
Iss I Sen.. ..... ICrRL Stn>b
56
p,..en' ALU and SU Check
57
110'"
BAI03
JCPU:SENS
lvo :SENS
,FOR
58
Am~ l!!:lIL
~
~
~
~
~
I~NS',l.
~
Bit.
,~ ~
~
59
I
60 I End 0. Gate
I KA,'2
61 I End 0. La.ch
I KA411
62
63
64
66
I 67
Set ALU Te•• Latch
I eCI21
I 68
Se......... Cheek
I CCI22
169 'Set LSA Check
I
I CO.l
Lzo
• Set Mad eheek
I CCIOI
171
172
I 73
,74
I
I
I
Set SU Check
lor-~
Cel02
Set A J Cheek
Set
au. Check
CCIOI
Se. SAl Check
I 75 Se' Inh Check
Function signals. 4Cycl.
m
'
Do not care " signals.
aCycle 0
Cycle _
• Diagl'Clll 5-68. SENS CPU
I/o
Cycle-=:J
(Indirect Addressing) (Part 2 of 2)
(03773A)
~
~
......
...... -
~
~
~iNH-~h:;~ :,71-~~~~' If-'~: .,:~~;~: ~~~) ~;.:',',: ~~:~~,:;
b,.".,.",
--
~
(
~n;- ~;a;uSE ~{
2020 ~ SO,OOO FEMDM Vol 2
(
AT •
....IiI
b""""""
(8/69)
.-....--
I "TO....Iii
4-
_,r >um bi" 0-7 0' ,e"e bl" i-15 e.en 0' do,bl.
~
~
I
Cy;,.O of n~xt
.
If the Ito reg l field contains /7/
(Ill), an indirectly addressed
SENS (see Diagram 5-69) Is executed in ALC mode. LS register ,
contains the field length (real
number of bytes to be sensed reduced
by 1). LS register 6 contains the
address of the byt, tnto which the
first sense byte must be stored. The
field length is decremented by I,
ond the store address Is incremented
by 1, every time a sense byte Is stored.
Microinstruction layout
This SENS ALe can be used to
question a sense source with a
repetition rate of 2 microseconds
(diagnostic applications, ICR).
10 II 12 13
SENS/Ctrl Acldr
AlC
INST
MNEM
OPERANDS
STATEMF.NT~
EF200
SENS
71.Xl2oO'
}j Y(R6.
At:r:rm.nING TO STANDARD CEB O.1046.XXX
+1. UNTIL RI. LT. 0) '*
=SENSE 20
vo
AlC
Note: For "Do not care" functions
refer to timing chart below.
Read out halfwonl
regenerate mia-ainstruction
CORE STORAGE -
~:I~, ~~~
-,,
LA_A-J!. ~J
01
L
------- --------------------1-------------------I
St",. halfw",d Into
88
T~
SU
I
r-....
I
AlU
Repeat common
port cycle 3
I
Invert sw
T4
Acceptance of first SENS byte
(CVO)
'" 18
Acceptance of the second and following
14
S!.N~by!!s <:.r~)
b. 18
FDR
__ -_-..:..:------,
-=: -:.-~
~~~--~L----------------~~--------~--------JL---------------------------------------------------,----Add, bu. [_- _-_ -: _ _ _
L/~20/L:__;::::-::-::-::=====~;:::==::::jl:=====:/=20:V===::;r======:::;~;::::====I:==========:;-_::-:_:-:_-:_::-:_:-:_:_:_:-::_:-:_-:_::-:_::-:_::-:_:--::_:-:_:-::_-:_:-~
Dal~::s
r,----,I
S:6~
-.;:'i-::s:C';=.-=':-::-:-:':;'1c;0!l.1'rr=lS-::...
:-:-=-=6-:c-=-::i'--;I'----c=:S:::EN:::S!.!.l:::h'O=bo::::;I-----f.).:o~~---------;-------~ - - - - -
l
L4_21'_~J
L4_21'_ ~J
I
I
I
liAR
°r-°_2 I
I 8_ L.
.J
-1
~UfReg 1,
I
LO _0-1 0:. ~ J
rIAR--
i
,I
I
I
I
rMAR-'- - rI -+1 -,L __ :
L4_~112 l_J
r.--'-,MAR
.J
I
,
:""O_!!..£.£
I
. . __T__ .,
I SAR
L4_2.J
I
!.. ~J
I
SARIS
Functions
during cycle time are shown by fuji lines Qnd functions performed during A cycle time are shown by
_..piagram ~9. SENJ./LO (ALc.l.Jtart 1 af.Jo\...
(O37~)
~ ~ SO.!m.FEMDM \loJ. :2
/'II/6!!\..
Decrement carry 0
forces end op Ale
I
,
!L .U
L8_0 i
I
I
-1
LS_O_I_O_2_
~
- - - -- - - -
---,
- ___ J
_
"Do not care" signals:
~Cycl e c::::::J
Cycle -=:J
-
.No
ALO~
Name
I i Sen.. T,,,,, Reque.t line.
Cycle
--
, LAI03
2
LS New PL Zone Gate
3
LS Current PL Zone Gate
4
New/Cu"ent PL
5
CE LS Select
CC222
Fh,ed X-Addte..
lMI2
T4
KASII
Ne dcu"ent L'. may' Hfe,
°
-T6
-
18
cle
T7
T8
T6
T7
18
I
6
7
_~~
7
9
'F,am Reg' Select
lA411
I-'I"+,OL",-SH,,,-a,S='-AR_ _ _-i KII4II
II
1-'1,,+,2L~Sit~a'F~OR_ _ _-iK~1
13
==
--
=
LS to MAR
6
-
'To Rea' Select
LS to TOR
1-'1-'-f-'4M=.:..;AR:t.:..;a,L=-S_ _-----llA702-712
LS Write
lA302/313
17
18
Set Add,... Check
RASOI
19
",ooch Go
RAS02
20
In ..emen' by I
RA402
21
I.aement by 2
RM03
22
De..e ....t blLl
RMOI
..
De,
.me" ,2
RA402
24
P",ye" Mod-MR-Inh Check
- -
---
15 I Set ALU IVO Bu.) to'
16
I---
-
KASII
25
Stot..e U..
MA402
rI 262T7 S"event
=ORlto""'oIn=h"'-='---rMA4Q:'=I'---t---t---t---t---t---t---+---t---t---t--Ou--IIS
28
SOR to 0, Reg
30
SDR to roR
-
I Kal02
31
EI.ht SMft Con"ol
32
SMft by 2 ot 4
33
No ShHt
34
Te" Packed Byte
IKB402
IRBI 62
IRal61
IRBI62
at
-0-!5--+--1--~--~-+--4---~-+--+--4--~--~-+--~
u-
RA502
Sign
~~~N~_a~lliu~,~S~'~~~'~-t----t---t---t---t---t---t---+--~-~-~-o
Suoo,...
36
0-15
I RaI7l
.. -4--4--4--+--4--4--4---R_i,-~~~~~~~r--r--r--r--o_,<-~-~-~-~-~-~-~--+--+--+--+--+--+--4
00
s-.',
0-
37
ALI I to FOR
38
AA303/K1I411
. 40
Iny.,t Switch Con,,"1
I T,ue 0-1
. RB301
,= /true/
ITrue O-I! =/t,ue/
I T,ue O-Ii
= /nue/
41
W
42
eon" , Gat.
10E
OE
IAA301
10E
4~3Ad=diH='on::::.011=
Carrr'--_-i AJ>3IJ2
1-1
Six Carr..Hon 8-11112-15
1-'45"-1-'Se",-tl.=
'Conv"",La-=.tch_ _-l AA402
46
Set
47
ALU to Inh
48
ALU to SAR
CondiH~,
Code latc....
, to J-7 (no'" R 15) 0,8:15 (SAR 5)
IMA401
I KII411
49
50
Dato Switch to, Opo..
51
Op Reg to Add,...
52
VO OI••loy Add"", Out
56
"
57
58
1/0 Bu. to FOR
Skip Cycle 0 to 3/End Op CYF'e h.w2/403
I
. AIU
au.
I SU
("h
LKB402.
t-=
KAS41
BAI03
64
-
65
67
Set ALU T. 1 Latch
I CCI21
68
Set _
I CCI22
69
Set LSH Check
,CC221
70
Set Mad Check
I CCIOI
... Check
~7",+ISet"",=->
SUI C~heck~_---t CCI02
72
Set AW Check
...
"\
==
,
f---f-"An=-tYh==-eck-+_-+-_+-_+--~_-+_-+_+••",.y.nt
'0"
_
,ra..lli ...
'T8...11...
'" )
~!~t~:;;:~:,~,;~c~~c"-~k====~t-C-CI-OI--+-+----t---+---+---+---+---t---I_
I---~~---t---t---"_
(--\=---'-....,----"'9
+~=I"ff .umC::.:r .en.. bHj
75 . Sellnh Check
Function Slgnoll: 6Cycle
~
__
F2ZI
Cycle _
"00 not care" signals: ·aCycle D
• Diagram 5-69. SENS I/O (ALC) (part 2 of 2)
(03774A)
Cycle-=:J
2020 ~ 50,000 FEMDM Vol 2
(8/69)
; eyer' c daubl, .elect
--If:.ra~_
--
=jl=~~~y~----j___
-----j--I-----j-----j--I--+--+---j----j----j---+--+--+---I--+---I---I
Cycle: 0 of ne",
;
i
·The low-order byte in 'to reg' is
set onto the DATA BUS. The
SENS/CTRL add-ess (low-order byte
of the instruction) is set on the
address bus and selects the circuit
group (in CPU or attachment)
which shall be controlled according to the CTRL data on the data
bus. The 'to reg' remains unchanged.
Instruction
The returning addreu and data
bus are set into FDR for display (E-S :::
returning SENS/CTRL add!", T-R returning
ctrl data) if the CPU stops after the
instruction.
I Op
:Codel 2
a
---rL __
SENS/CTRl address to ottachment
-
-
...... Selects circuit gl"Qup
/20/
t
L_ _ _ _ Direct addressing
LI.::A~:"'::"'-l:=!:::::"~,...J
LS 'eo 4
remains unchonged
The data bus output is displayed in
U-L.
INST
MNEM
OPERANDS
STATEMENTS ACCORDING TO STANDARD CEB O_1046_xxx
F4Z0
CTRL
4.X'ZO'
CONTROL ZO/R4. 8_15
I/O
Direct
Addressing
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
~ Cye! e c:::::J
Cycle -=::J
CORE STORAGE -
regenerate mIcroinstruction
-1- -
r- - - -
-
-
I
r::-t. -,
hr---~
I SDR
L..!'_41.2_0J .~
l
I
Op Reg
F
4
2
01
I.
TDR
ABO
I
111-----,
lEis rid
11
1
Invert sw
I
f3
f4
FDR
2 0
{)oln
Out
-I
---
1-
" f8
1FDR
12
0
1201
/01
1
IAR
8
0 0
41
'I Sense reset I (Clear data bus)
f3
Functions performed during
time are shown by full lines alld functions performed durlng A cycle time are shown
-2.iagram 5-70. ControlJ/O
(Dire~ Addr~ssil!!l)
(Part
i of 2)
(0:E75A)
dotted lines.
_.2020 ~ 50,.000 FEMDM Vol 2
(8/.h9l
I
-
-
-
-
-
-
-
-
.- -
-
---.-
-
- -
-- -
- - -
- -
-
-
-
-
-
- -
-
-
-
- -
-
-
- - - -
-
- - -
-
-
- - -
-
,
AlD
Nom.
INo
.T4
I . Sen•• T,ap Reqv.,t line,
Z
LS New Pl Zane Gat.
3
lS Cv"ent Pl Zane Gat.
4
New/Cv"ent Pl
5
CE lS Sel.ct
T8
T6
T~
E
.Ii
T6
T4
""--
ILAI03
KA5ll
N ••/cv".nt
" may
------
If"
,
Iccm
6
7
F'x.d X-Add'e"
8
'T~Rea'
9
lA4IZ
S.I.ct
IlMOZ
'F,am '.g' Solect
lMII
110
lS to SA•.
KB411
III
LS ta MAR
liz
LS ta FD.
113
lS'a TD'
114
MARtalS
11 I So. AlU
LJ~
~
---
~
K8401
LA70Z-71Z
I---
(I/O ,,,I .a LS
lS'Wd••
........
........
f--
lAJOZ/313
~
------
[ 17
118
Set Add,... Check
[ 19
a.anch Ga
I.ASOI
ASOZ
[ 20
'MOZ
121
In"'e~n'
by Z
[ .M03
["
[ 23
'"Dec.emen. bv 2
[ RA40Z
I~
p,.vent Mad-SAO-Inh Check [ KASI
[ .A401
[ ZS
I Z6
"'ev.n' 5....... U..
I MA40Z
[ Z7
SD"a Inh
[MA401
[20
SD. to
O. Rea
[ K810Z
[ Z9
30
SD' to TO.
I KB40Z
31
E'ght Shift Can"al
I '816Z
3Z
Sh'f. bv Z '" 4
[ .8161
33
Na Sh'ft
1.8162
34
T••t Packed Bvte '" S'on
f---
--
O-f To1f'15
~
,
0-15
'ASOZ
3S
N...malize S'.n Active
36
S,
1.8171
I AAJ03
37
38
AlU'a FD.
39
""... FDIVReto'n FD. 0-7
[ AA303/K8411
40
Inv.,.' Switch C",,"al
I '8301
I Tw. O-I! - /"v./
41
~
. AU!
C,
'G,
10E
AAJOI
43
Addit'""al Ca"Y
44
S'xC""ecti"" 8-11/12-15
45
So. Ca,,,, La.ch
AA30Z
AMOZ
,C""d't' ,Code nteh.,
46
MA401
[ 47
AlU 'a Inh
[48
AlU ta SAR
I K8411
I K840Z
[ 49
[ 50
Deta Switch ta Oa Rea
151
Op Re. ta Add'e" Bv.
I 52
I/O D',plav Addn.. Oa'
[ 53
Allow S"abo
[54
SENS
Iss
Some "".etjCT.l Sh"abe
[ 56 . p,.• • A
KAS41
., s..
If----
IA"
7
Fi"d X-Add""
8
'To R.g' S.I"t
9
'Fcom Reo' S.I.ot
10
LS to SAR
I LA402
'4'
KB411
12
; to FDR
13
. to TDR
-
I::::::=::
LS to MAR
KB401
MAR to LS
15
S.t ALU (I/O B"I to LS
16
LS Wdt.
"=
17
18
S.t Add"" Cheok
~~;~;:'O!C'yd. ~ ~:th'
o,xt
~co''':io; p.6 ,d
~
~
6
r---
==
"""""""
--- -
r---
=
~
--
--
-=
~
"OJ
,r.,
B,
'4'
~
---
.--
r-->301/313
....:...
_9.
~
LA702-712
14
~
T7
i-
~
I CC222
6
III
~
---=--
T6
T~_
I RA502
120
lo,,,m.ot bv
121
lo,,,m.ot by 2
A40?
I 22
D",.m.o
I 23
D",.m.ot bv
12.
P"v.ot Mod-SAR-Ioh Cheok IKA"
I 'A403
A40J
I RA402
1 - - - ~'~'~ I - -
125
P"v.ot Stoz.LS;
r.SDR
OrI - ~~~~'p:~i:':~Cd
odd,~,d b ~,i..2.
f --,
Suppress
I SDR
i_,
~F_E..L3_4.J
(Regenerate)
SU
Suppress
E
1 - - 1
-
-
-
-
-
-
-
'
OE
OE
ALU
rrd~~'90
-
r-
I
L'_2 3...1 J
SU
Read out and
regenerate halfword
)
I
AC
"Do not care" signals:
~Cycle C=::J
Cycle -=:J
y
X
Invert sw
Invert sw
Addr bus
Address switches (customer)
10
CE select sw's
CI
IX
Y
SENS/l3
Data sw's (cust.)
EI
~
I/O display address
lS zone 7
Functions performed during cycle time ore shown by full Jines and functions performed during A cycle time are shown by dotted lines.
Diagram 5-74.
Storage Alter/Fill (Part l' of 2)
(53779)
2020 2 50,000 FEMDM Vol 2
(8/69)
--
for alter}
No
ALO
""me
1
S.n.. T,ap Req....t Uno.
2
LS Now PL Zan. Got.
3
LS Cu".nt PL Zane Gate
4
N.w/Cu".nt PL
I LAI03
KAS11
'PL7
_CELS~.ct
5
~
fa~
IbvMAI OP
.
Read
-
,.
Read
W,;'e'
~y"e
-'"-
"
T6
TB
N. ,and conent PL'. , '.ntlcal
TIl
-
T~
T.
TB
T5
-
I
--
T6
I CC222
T6
T'
TB
T7
..-------,
6
7
Fixed X-Add,e..
.~ _'To R.....Select
9
'F,am Reg' Select
LA411
LS to SAR
KB411
L5 to MAR
112
L5 to FOR
c--~
KB401
13
LS to TOR
14
MAR,. LS
LA702-712
liS
S.t ALU (VO Bu.) to LS
ill
LS w,lte
~
=
r---
---
~
Wm=
=
Pz==
~
--
-=--
LA302i313
18
S.t Add..... Chock
I RASOI
19
&.onch G.
IRAS02
l.2!L
~
Q
r-
17
-'n_~yl
1RA402
Inaemont
bv 2
1 RA403
I"
no
Ilw.l.
1 RA401
123
Dac~~nt
,2
1 RA402
124
P,"••nt Mod-SAR-Inh Ch.ck 1 KAS11
121
-"-
,--!L-
1LA402
10
111
~
,--!L-
LA412
N t U CE ~e, fa~.. ,"••n .f, ~a ..ed '
~
-
Ill::=-:
-
~
-
~
-
---
-
125
126
27
Pr...nt St..... U..
I MA402
SOR ,. Inh
'.to 0-7 'SAR IS,
MA40I
.28 ISOR to Op Reg
----.,
KBI02
30
SOR t. TOR
31
Eight Shift Con".1
.32. . Shift
KB402
' R8162
bv 2 .. 4
I RBI61
No Shl"
34
T••t P.ck.d Byte '" Sign
36
to 8-
U no
S~
,15
0-1
-
-==
, 0-1>.
I
15
I RBI62
33
·35
-
---
29
~15
I"-SAR 'ang..
RAS02
N..m.llze Sign Actl ••
Su-.o.
I RB171
38
ALU t. FDR
1 AA303
39
Reoet FORlRe,,'n FOR 0-7
1 AA3031KB4I'
40
In... t Switch Con ...1
1R8301
0-
37
FOR
FOR t, ,0-15
FOR tn ,.0-15
,.0-15
FOR" ,a-IS
ill
~
r 43
. ALU Con"ol Gat.
IAA301
Additional Corry
AA302
44
51. CaToetion 8-11/12-15
4S
Set CaT. Latch
.~
OE
OE
OE
OE
AA402
Set Condition Code Latches
47
ALU to Inh
48
ALU
-IS If
IMA401
'0 SAR
I,,_~
IS, S-
t. 0-' If
'SAR hon." at '
49
~
Data Switch ,. Op Reg
1KB402
Qg Reg to Add....
au.
KAS41
52
von.-
,Out
53
AllowS",
51
54
SONS
55
Sonoe ...../CTRL Sh'obe
56
57
.
I Shobe
All
t SlJ Chock
BAI02
r---
-
-
BAIOl
I/O Bu. to FOR
58
.9l
MANOP
I 60
St._OASF
I 61
St..... Soa.vFlII
KA53¥532
62
Sto_ ., L5 Reg AI .., 01",1
63
MANOP In Bu. to FOR
---
(01 ••1 SEI.S,
-
10-L'
MANOPSENS
I BAIOI
1CCI21
66
67
Sot ALI I T••, Latch
LA
Sot P,..... Chock
1CCI22
'69
Sot
• Chock
1CC221
'70
Sot Mod Chock
1CCIOI
1 71
Sot SU Chock
J,-
SotAW Choek
--
-----
rw
SEN
~
CCI02
~
au. Chock
73
Sot
74
Sot SAO Chock
75 Sot Inh Chock
function slgnall: .b.Cycle
~
CCIOI
rz.I
Cycle _
"Do not core" signals: llCycle c:J
• Diagram 5-74. Storage Aiter/Fill (Part 2 of 2)
Cycle-=:l
(O:r779A)
2020 ~ 50,000 FEMDM Vol 2
(8/69)
~
~
FALU too lotch off ?' any
a-Is
ch.~k
=
---
-
-
-IS
164
~
-
~
---
~
-
~
~
----
~
--
-- --
'""'"'"'
---
~
-...
Io.T8..ii
i..
--
Due to the complexity of the operotion and the
limited space ovailable on this page, refer to
Chapter 6, Field Engineering Theory of Operotion,
2020 Processin Unit 5 stem/360 Model 20
(Machines with serial no 50,000 and above,
Form Y33-1021, for description.
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
!l.Cycle c=::::J
Cycle -=:J
CORE STORAGE - - - .
------------ --- f-----------------Data sw's
Regi ster
Zone
®®
J
Op Reg
a a
3 7
I
TDR
A B
C D
CPU stop
I
I
II
A
A
/A
B~C
D/
I I r I u I, I
p
rTTT,
t!-,-S..LT..L'.J
Display of addr sw's
("00 not care")
'From reg' decode 7
L-.J
Force select LS Y 3
.>
LS zone 3
>
Functions perfonned during cycle time are shown by full lines and functions performed during .6. cycle time are shown by dotted lines.
• Diagram 5-75. Local Store Display (Part 1 of 2)
, (03780A)
2020 ~ 50,000 FEMDM Vol 2
(8/69)
IFrom Reg I(lAR zone 3)
I A B leD
No
1
_2
3
4
5
ALD
Name
Sem. T,op R'q""t lio"
LAlO~
LS N.w PL Zo", Got.
KA5l1
~.T4
~Cy~
T6
T7
12
T3
"I.
T4
T6
~
I
Cyd.
TS
T8
T4
T6
n
ra'
T7
T3
---
T6
T4
lS C""eot Pl Zo", Got.
I
New/C""eot PL
CE lS Sel"t
I CC222
6
7
Flxod X· 'dd""
.. 1:
8
'To Rea' S.led
lA402
9
'F,om Reo' Select
lA411
10
ito SAR
11
lS to MAR
12
lS to TDR
14
MAR to lS
r--
----
r--
t---lA302/313
17
18
19
---
lA702-712
lS Welte
-
-=
KMOI
15 I Set AlU (I/O B",) to lS
16
"o'wit,h
t----
r-~
> FDR
13
'om "9 "'ected ocoo,dl09 to, ettl09 of
KB411
r---
r-r--
t----
----
~
-----"
--
~
-==
RAS01
"'dee" Ch"k
RAS02
"'o",h Go
20
""me", by
RA402
21
lo".ment by 2
RM03
22
De
RM01
23
De",meot by 2
2'
P",.nt Mod·
.m.
RA402
-Inl, Ch"k
KASI
25
J6
MA402
Y,."ot Stoco,. U..
27
SOR to Inh
28
SOR to Op Rea
, KB102
30
SOR to TDR
I KM02
31
Eight Shift Conrrol
I RB162
32
Shift bv 2 oc 4
I RB161
33
No Shift
I RB162
34
T"t Po,k.d Bvt. oc 5100
---==
MA401
29
-
No, ,1ft 8
0-
0-
RAS02
35
Nocmoll,. 5190 Actl"
36
5,
I RB171
38
ALU to FDR
, AA303
39
.... t FDo/Retei .. FOR 0-7
' AAJ03/KM11
40
In,,,,t Swl"h C""teol
, R8301
C""rrol G,
I AA301
,IS
37
FDR
t,~.
0-15
FDRtn ,0-15
FORte
,0-15
FDRt,
,0-15
41
.2
i 4J
Addltl""ol Corry
10E
10E
OE
DE
AA302
51, Coc,ectlon 8-11/12-15
'5
S.t Co"v lo" h
AA402
, Condl'lon Cod< lo1<
'7
ALI' to loh
I MA401
48
ALU to ;AR
I KM11
50
Ooto Swl"h to Qp R'a
IK~
51
_Op R.g to Add"" Bo,
---
49
52
53
\l1~
54
SENS
.2S.
KA541
I/O D;,plav Add"" Out
=
St,obe
I
I St.
p", "t
;7
I/O B", to FOR
'-
",abe)
I SU Ch
:Pl lENS
i
BA103
--
--
e-=--;
,
I
_S.n.. Re.. I/ORl St,ol"
56
I
(OI'pl SENS
8Al02
~
r---
-
5B
,59
MANOP
60
lS DI,olt
KA531/532
61 _LS DI,olt o. LOG
62 I StO.09' oc lS Reg Altee/Dply
63
Aoy ,heck
s.t AW Cheek
73
-
~
~
CC10l
tz:2J
Cycle _
"Do not core" Signals:
• Diagram 5-75. Local Store Display (Part 2 of 2)
.~Cycle
c::J
Cycle-=:J
(0 3780A)
2020 L 50,000 FEMDM Vol 2
(8/69)
--
~
lor--
~
~
-
~
-...
r--~
~
1:==
---
-----
,TB_
==
~
---
~
~
--
'00,
- --
r
Due to the complexity of the operation and the
limited space available on this pogs, refer to
Chapter 6, Field Engineering Theory of Operation,
2020 Processing Unit, System/360 Model 20
(Machines with serial no. 50 000 and above),
Form Y33-1021, for description.
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
.6. Cyc Ie c::::::=J
Cycle -=:J
CORE STORAGE -
SU
SU
ALU
DE
ALU
ALU
OE
Z...o
Y.,
No
No action
Invert sw
No action
Invert sw
Proc chk FL
NotALU test FL
Address switches (customer)
/90 C
E/
----------'From re ' decode 7
Force select LS V3
LS Zone 3
------------ - -
Functions
during cycle time are shown
full lines and functions performed during .0. cycle time are shown by dotted lines.
(O:W>
~ ~ 50,RfEMD~
2
(8iMil..
---
I
\
2
ALD
Nom'
INo
S,m, T,op R,o"" U""
-~T4
:yol,
I
:Y'
T8
T6
~
I
Cyol,
,D
T4
T6
T5
T8
T8
T6
T4
T7
T6
LA1D3
KA511
. LS N,w PL Zo", Go"
3
LS C,rr,"' PL Zoo, Go"
4
N,w/C",,", PL
5
CE LS 5,1,,'
CC222
7
Fixod X-Add""
LM12
-.!
'To R,o' 5,1,01
LMD2
'F,om Reg' Seled
LMII
5':'
; W"'
"I"',d 0"oedi"9 to "ti"g
ot
,
6
9
10
III
LS '0 MAR
i 12
LS
LS to TOR
MAR '0 LS
115
S,t ALU 11/0 B"I to LS
LA302/313
, 18
Set Add"" Che,k
; 19
","o",h Go
22
I 2'
I 25
I---
I---
I---
r---
----
~
--
----
'A5Dl
--
----
I RA502
'402
""
'""eme"' by 2
I RA403
'"
I RA402
'401
De,,,me"t by 2
-Ioh Chook
Pee,,"t Mod-
KA511
126
Pee,,"' Sto'age U"
MA402
I 27
SoR '0 '"h
MA401
SoR to 0, Re.
KB1D2
28
=
r--
----
---
LA702-712
;Wdte
123
~
KB401
,FDR
I 13
20
=
=
~
r--
11,
, 21
I to "It 09 of dot, ,wit,h
KB4l1
Ito
-
29
3D
SoR to TOR
I KB4D2
31
Eight Shift Co"',ol
I RB162
32
Shift by 2 0' 4
33
No ShHt
34
Te,t Po,ked Byte oc "00
0-\ :
---
.----,
IBl61
I
Not ,hHt
'"0' hilt 8
Not hlft 8
O-I
D-
I RB162
,0-15
15
RAS02
35
Nocmoll,. "g" Aotive
36
5'00'"
I RBI 71
: AA303
15
37
38
ALU '0 FOR
39
R,,,e' FOR/Reto;" FOR 0-7
AA3D3/KB411
40
,",," Swit,h Co"ttol
R8301
FOR
FOR tn ,0-15
t,~,
FOR
0-15
'0 ' 0-15
FOR
Ie
,0-\5
41
42
I Co,
Additio"o\ Corry
44
Six Coc,,,tion 8-11/12-15
45
Se' Corry Lo"h
46
C
!A3Dl
I G,
43
AA302
AA402
, Co"dition Cod, Lot,h"
47
ALU to \"h
IMMOI
48
ALII to SAR
I KB411
Doto Swit,h to ()p Reg
I KB4D2
00 R", to Add,,,, Boo
KA541
--
49
50
52
I/O oi,ploy Add"" O,t
53
'"ow S',obe
SENS
I Sttobt
55
Seme R.. "/CTRL Stmb,
56
Pee,,"' AI I o"d SU Ch"k
57
I/O Boo '0 FD.R
.t:::=
Di,pl SEN' ,t,ob"l
BA102
BA103
-
-
58
KA531/532
SO
MANOP
60
LS Di,ol'"
61
LS Di,ol'"
62
S'ocog, ot LS Reg Altee/Di,pl
64
MANOP S'OP'e"
DC
--
--
-
I---
10-\5
I
LOG
MANOP \0 S" '0 FOR
\
SEN' '\4/
65. _MANO-'S~
66
MANOP T", ALU Z'co
Icc",
67
Set
I CC\21
I 68
Te" ,toh
Set P,oce" Che,k
Set LSA Che,k
I CC221
70
Set Mod Cheok
I CC10l
71
Set SU Che,k
69
72
Se' AW Ch"k
73
Se, "'" Che,k
74
Set SAR Ch"k
'\
/
-- --==
.=.=.
=
(Cl02
I,>"oy,h ~'k
,
\
CClOl
Set '"h Che,k
Function signals: ACycle
I:zz=
)
.15
• Diagram 5-76.
-
~
I CCI22
IZ:ZI
Cycle _
.
"Do not core " signal;; .:'I.Cycle
Local Store Alter (Part 2 of 2)
c:J
(03781 A)
Cycle-=::J
2020 L 50,000 FEMDM Val 2
(8/69)
~
----
~
-
I---
--
t:-:=
-
~
~
,.....-----,
---
,TS_
-
~
~ot
~
--
---
ALU Ie ' 'otoh o',ooy ,hk
---
,T8_
Due to the complexity of the operation and the
limited space available on this page, refer to
Chapter 6, Field Engineering Theory of Operation,
2020 Processing Unit, System/360 Model 20
(Machines with serial no. 50.000 and above).
Form Y33-1021, for description.
Note: For "Do not care" functions
refer to timing chart below.
R.ad aot halfwa,d
l
Sto," halfwa,d
-'''' I
CORE STORAGE ----+
,~.,"-
-"~,~[_, ~~-ri~-
Data sw's
ISDR
I
I
I
LQ.._0..J.2._oJ
Note: CPU log in is performed before
ICPL (see Diagram 5-80).
For ICPL loop the operation
stops after cycle when the
stop kfity is operated (stop
FL on). To restart ICPL
loop press start key.
°
~
o
0
0
~
0
~
° ° °
0
OE
OE
AlU
Stop ond wait
Suppress
Suppress
° ° ° °
OE
°
Stop and wait
SU
Suppress
1 0
Perform cycle 2
and cycle 3
Perform cycle 1
Stop ond wait
Note: No single cycle during ICPL
°
-----------r --
Invert sw
Perform cycle 3
2d:~~~
Data
___
®®®®
®®®®
Check stop
CE select switches
Address switches (customer)
~~L~____~/~C~0~0~0~/~/~20~/~______________
____________~____~/~0~1~4~F~;~2~0~/----------------I·--------------------JL---~/~20~/~----------~------~-----------------------------------------------,
5/ _ _ _;::::::===;12'-! OCLI __--,:::;:::::::;:::::;- =::J*""_,;:;:==:::;-_-<..:/0:c.
b"t.--_---;::::;:::==:;--_f2
Sense reset
Ctrf strobe
Sense reset
r-----L----~-~;~E~~S;,=t,=Ob=.~~--~/~O~I~/------~==c;o="t=,O=,=",=~=.==~----------------------------------------------------l
Ctrf strobe
Force /20/
LS zone 7
Switch-Settings
Data
Sw's
CE-Sel -Sw's
Load Device
1
2520/60- Hopper 1
0
2
2560- Hopper 2
7
2501
2
3
4
1
Address
Sw's
2
1
2
3
r-- ---.,
-
: LS Reg
i
I
~--'--
4
~f ~
I
LS Reg 4
I MAR
I
J'A\
00
.
T.-'
I
I
1+0
I
I
L<1...E+4_!:J
r--:L -
I MAR
I 1
Lo_ :2.1..4_ L'-
L'-. i'L..0_ 2.C_·.J
J4
F
2
0
C
0
0
°
0
lS reg is unchanged and moved ihto
IAR when CPU is started by the first
trap-req 5 (cycle 1 overfaps ~ cycle 2)
Controls the forcing
and functions performed during 6 cycle time are shown by dotted lines •
• Diagram 5-77. Initial Control Program LoadJPort 1
r-----,
I
Table I
Functions performed during cycle time are mown
° :
L~_o+£.~J
(03782A)
2020 ~ 50,000 FEMDM Vol 2
(8/69)
°
Decrement cal ry
farces end op, ICPl
"Do not care" signals:
.6. Cyc Ie c:::::::J
Cycle .::J
I
2
, 3
ALO
Nome
INo
I 5.,,, T,op Re".,t U,.,
I lS Now PL Zo,e Gat.
I LS C'"'"t PL Zo", Got.
LAIOJ
KAS11
-.
CPU dop if any 1/0 working
or stop FL (tCPL loop)
T.
17
18
Tl
T4
cya.O
T5
+
T.
T4
-
I CC222
•I
7
Fixed X-Add.."
LMl2
8
'To Reo' 5.1",
LA402
'F,~R.. 'S.I
LA411
·10
9
LS to SAR
KMI1
ill
LStoMAR
12
,13
j
14
15
I.
K8401
LS to TDR
LA702-712 •
MARto
I Set
1(1/0,,,110
f---
LSW""
LA302/313
1,8
Se' Add'M, Ch"k
RASOl
1,9
",o,ch Go
---
C::::=-c::
17
i '0
I,a.me,' by 2
122
'"
123
124
..'"''''""
, by
121
'A403
~
0
~
-----
-
-.......-
PIeY." M d-llAR,
Stap after cyde 3
~
--
~
'--
r----
=
=
""=
--
------
-
lor--
h Ch.,k [ K""
,
I
--
"""""" ----
'hI, i"a' ',",~ applied "he modI .Ie, whe, ,yd. 'oy,;,la" ,yo ,2, b" i"teme,ll, 9 by 2 I. :,,,""ed,
"eYe,t
51"'0'. U..
27
SDR to ',h
28
SDR to 0.'"
'"
I
lor--
I---
~ Dw" ;." cony
.....
MA401
0-710
30
SDR to TDR
KB402
.31
"oht Shift Coo'ol
R8162
32
Shift Iw 2 ",4
R81"
'" SAR
!S,8-15
0..---
--
29
33
I,ll 'Cyole
I MA402
. K"'"
lor--
111:::=
125
12.
+
==
-
-
....,...".....
,
-0
~
r--,--,--
--
'--
4
0
~
..0'
'"
=
T'
RA402
'by 2
r--- !{estart by ttap request,
,Stop after eyde I
.---.----
---
I--
'0 FDR
LS
f.-:.-.L
r---
I/O working drops
---
4 I N.w/C,,,.,' PL
5 ICE LSS.le,t
r - CPU start if any
0..---
-No ,;ft8·
Ir-
-No '1ft 8·
lor--
'No hilt 8·
'SARIS
,,~ •• h I
,'0 SAR .15' '0,
1ft 8
I RBI.2
,
True 0, ; a,d '"in 0-7 ' /
,0-7';1 iO'ru.1
!Jo'ruel
I Tru.O-1 5=d
"vo ,0-7,;1 ,--;;;;;;
141
42
143
44
145
lCo
" G,
AA30l
Addltl",al
eo""
AA302
I Six Carre,"", 8-11/12-15
I Set Cat,v La"
46
Set C~dlt'oo Code La'ch
47
All. to I,h
48
I MA401
I K.. II
SAR
Oa Reo to Add,."
152
VO D;,.lay Add.... o,t
I 53
b.
I~
I P..y.,'
1.R
.Ji0 Bu. to FOR
I 58
I 59
160
-
I K..07
Data Swlt,h 'a Op Re.
I 51
I 54 I SENS Sh
'a,d SU C..
'COlLa"h
I Fo~. I'ven 0-7
MANOP
>AI 02
---
>AI OJ
KAS31
KA541
KA531j532
MANOPs"......
"
I .3
MAN'." "',, ,FDR
ICOl-Cm
I ..
ICOl-SENS
I ..
MANOP SENS
BA10I
67
Set ALU T." Lat,h
CCI21
68
5., P'OCM' Che,k
CCI22
.9
5., LSIoCh.
CC221
70
5•• ,,- 'Ch,
CCIOl
S.,SU Ch"k
CCI02
120/
KAS42
.--
Se, ... Che,k
' 7'
,SAliCh
Se, I,h Che,k
FunctIon sIgnals, I1.Cycie r'Zla
Cc10l
Cycle_
-~
~;:.rk
Se' AWCh.. k
I 75
----
10-15
"8~
~
::..
,~- ~
~
0-1'
6.
In
I 73
'''..; ::..-
....::;.
I 61
I 71
10E
lOE
AM02
49
50
rOE
lOE
,blr
• 8-1
I
I
Do not care" SIgnals: I1.Cycle c::J
• Diagram 5-77. Initial Control Program Load (Part 2 of 2)
andsum;bits
,
0~7)
I
[ SENS
----
==
-~
b"""",
~
-lor--
~
~
I
[Note:
l,is
I
!byt. "
Cycle-=:J
(03782A)
2020 ~ 50,000 FEMDM Vol 2
(8/69)
I
'"~o='t
ALU byte
INH cheek occurs if the
0.--
lor-L'~
.:::::.::.
""'=
---
~
0.....-
b"""",
-
~
,"-S,m' 8'" 0-7
0; S~•• 81t
8-15 • ...; '" o.,bl .S.lec'
I
'---'
'---'
-...
Due to the complexity of the operation and the
limited spoce available on this page, refer to
Chapter 6, Field Engineering Theory of Operation,
2020 Processing Unit, System/360 Model 20
(Machines with serial no. 50,000 and above),
Form Y33-1021, for description.
Repeat A Cycle and cycle-I, 2, 3
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
.6.Cycle c:::::::::J
Cycle -=:J
CORE STORAGE -----+
__
su
Suppress 0-15
Store true or inverted
address into its own
~tion
__ _
Suppress 0-15
Run 1
Run 3
OE
ALU
Invert
5W
OE
Run 1 '" true
Run 3 '" invert
Force zeros
Pori ty inverted
-
LS zone 7
Increment carry 0 if /FFFE/+2 (run end)
Functions performed during cycle time ore shown by fuJI lines and functions performed during ll. cycle time are shown by dotted lines.
Diagram 5-78. Storage Test Run 1 and 3 (Load Runs) (Part 1 of 2)
(03783)
2020 L ~O,OOO FEMDM Vol 2
(8/69)
Read
:yole
ALD
Nome
INa
T3
I I S'",e T,ap Req.e" Llao<
T4
T5
T7
T6
TS
ILAID3
KA511
2 I LS New Pl Zooe Gate
3 I lS C."eat Pl Zone Gate
4
Ne' Pl' fa",
New/C",,,at Pl
5 I CE lS Sel«t
j
T3
......
by MA OP
Cyol, D
T4
T5
T6
T3
......
T6
T4
T7
TS
Cyole
T6
TS
---
"rewao TO",e;;' b'd",'"
~ O;,,,Io,ag,'to---
I--~
K8401
LA702-712
MAR to lS
I----
IS Wolte
J......
J......
I.r--
f--
IlA302/313
"""'=
b",..""
i===
'===
----==
I---
I---
Set A J (I/O S,,) to LS
116
!.-"--
f..-2-
0
0
lA411
KS411
SA~
lS to
0
IlA402
'F,om Reg' Seled
110
~
.. ,2
'To Rea' Seleot
t---.
--
I.r--
117
lIS
Set Add"" Ch.ck
I RA501
119
1I<00ch Go
~O
'ngem.nLby I
I RA502
I RA402
I RA403
21
lacremeat by 2
L22
o."emeat bv I
lA401
23
De,
,7
I RA402
24
P,event Mod-SAR-Inh Cheok
I KA51
26
"eveot Sto,oge U"
I MA402
27
SDR to lah
I MA401
2S
SDR to Op Reg
I KSI02
SDR to TOR
I K6402
31
Eloht Shift Coat,ol
I RBl62
32
Shift by 2 '" 4
I RSI61
No Shift
I RSI62
""--
---
~
"""--
'ac,""eot cony'
I~
----
'19
_~D
.~3
34
T"t Packed Byte", Siga
35
N"'mallze Sian Active
36
S.PO ....
,
-
~
No hlft
~
~
~ :hiii8
I
RA502
0-
I RSI71
~
Ito FOR
38
; M303
39
Re",t FDR/Retala FOR 0-7
M303/K'41
40
In",t Switch Cont,ol
'8301
, Con"ol Gate
AA301
T,•• oad Inv, to-IS = ~OOO/
Tru~ 0-15 run , laveet 0: 15 rua 3
T,., a,~15 run I; la",t 0-1 ; rua 3
FOR ,.. 0-15
41
42
43
Additional Cony
44
Six C",,,cllon S-1I/12-"
45
Se t Carrv Late h
46
Set Condition Cod. latch"
47
~48
,lU
OE
OE
OE
OE
AA302
AA402
Inh
0-1
IMA401
AlU to SAR
IK6411
Data Switch to ()p Reo
I K6402
, 0-15
,49
I 50
KA541
0. Reo to Add"" 80<
I.r--
I---
~2 --'L'O D;,ploy Add"" Out
C;;3
54
Allow S"obe
1St,
SENS
Sea" Ro,
,73
Set Bv, Check
I
]4
Set SAR Check
75 Set Inh Check
Function Signals: ACycJe
, check
b"""""
eClOI
)
m
---
I...-
~
I CCIOI
SU Check
R"n 3: ,to," Invo';, only
11
I CCI22
I CCI21
I CCI22
I CC221
Set lSA Check
So
-
'/
I KMI4
67 I Set AL J Te" lotch
70
SEN
Sto,,,,e FH I/Altee oat CE Ma
'ahlblt FDR True 0-15
_69
---
---
---
KA531/532
Maaop
68
---
I BAIOI
, 62
166
BAlO3
~
,FOR
I 63
65
(DI,pl SE~ 5,t,ob,,)
BAI02
I 55
Cycle _
"Do not care" signols: 6.Cycle
~
Cycle-=:J
• Diagram 5-78. Storage Test Run 1 and 3 (Load Runs) (Part 2 of 2)
(03783A)
2020 2 50,000 FEMDM Vol 2
(8/69)
----- -
-.... ---......
'===
~
~
~
~
-
b",..""
-....
'===
10....-
---......
-...
Cyol, D
---
Due to the complexity of the operation and the
limited space available on this page, refer to
Chapter 6, Field Engineering Theory of Operation,
2020 Processing Un it, System/360 Mode I 20
(Machines with serial no. 50,000 and above),
Form Y33-1021, for description.
Continue with load run
Repeat 6.cyc!e and cycle -1,2,3
Note: For "Do not care" functions
refer to timing chart below.
"Do not care" signals:
.6.Cycle C=:J
Cycle -=:I
Read out
halfword addressed
CORE STORAGE -----
by LS reg 0
I
Regen holfword
-------------~T--
:I
IsDR-' -1
r
I
Run 2 ----Jt.. L9]....Q ~..2.J
Run
I
4--------... LF -F . .1...F ~ J
I
I
~,
~:
L...LE.l.LLJ
I
I
Suppress 0-15
o
SU
I I III
0
o 0
~L'£ ...
0
I 0I I 0I I ~
I
.L...E
_F_...J
I
Display storage halfword in
P-I-U-L =/0000/
ALU
Force zeros
I
o
0
0
0
0
OE
Roo 2=',,"
Invert switch
I 0 I0 I
Roo 4
=
ioooc'
I
I
No action
I
I
LS zone 7
~~c...Jl
I
I
I
I
I
-
iLSR;90--'IL-_ _ _ _ _ _ _
I
L"-
~__"
2tO_Q.~
I
I
I
SlOp
if
I
check or
$top key op
r--+---
I MAR
Lo_olo_o_
Increment carry 0 if /FFFE/+2 (run end)
I
fSA,l- -,
I
I
I
L!? .JC.tQ. .LI
Functions performed during cycle time are shown by full lines and functions performed during tJ. cycle time are shown bv dotted fines.
Diagram 5-79.
Storage Test Run 2and 4 (Comj'are Ru~s)(Part 1 of 2)
(03784)
2020.~
50,000
F~MDM
Vol
2
(8/69)
I
ISARt. -1
I
~ .L 0 .L 0 -L OJ
,
R,od
Cyol,
ALO
Nome
INa
T6
.T4
I I S,m. Tcop Req,.,t L;oe>
T7
T8
3 ' LS C""" PL Zo", Got,
ood ",ne ,PLlfo"
4 , N,w/C,n"t PL
S
CE LS S,I.ot
T4
T6
l'bvMAi Of
T3
T8
---
KA511
2 , LS N,w PL Zoo, Got,
T3
T2
ILAI03
Wdt,
01,
Cyd.O
T6
T4
Reod
I
T8.
Tl
---
T3
T4
Ts
d,
-T.
T8
----
---
........
I CC222
Cyd
T4
T5
---
6
Fixed X-Add""
7
9
~
LA412
'To "0' 5.1.01
'F,om '.0' Seleot
ILMll
f---
KB411
;'0 SA'
n FD.
KB401
1,3 I LS to TO.
lA702-712
I,. I MAR to LS
16
f-----
f---
I t5 I S.t ALU 11/0 B,,) to LS
LS Wdt.
---
~
---
LA3D2/313
17
tR
Is., ..",," rh."
1,9 I Btoooh Go
121
loa.meot by 2
I,.
""",men' h.
123
o.".m.ot b. 2
I RM02
I 7,
~
""""-
I"""""",
~
""""=
-==
I>m:= Ilf CE m,
-----
lor--
"wlt,h
---
---
I.r--
P"veo' MM_SA'_I.h Check
I KASI
P"veot Sto,oo' U..
LMA402_
M02
I.M03
: lo;,~-;';,"t·" f'y 0
MOl
125
I,.
~
I.AS02
I.",m.ot h.
SO, to loh
27
~
~
'ASOI
170
126
-----
f--f----
111 I LS to MA.
17
~
~
0
M02
--
I MA401
I KB102
I SO. to 00 "0
I 29
13D , SO, to TO'
I KB402
I 31 I Etoht Shift Coo"nl
132 i Shlftbv2oc4
I RBI62.
I RB161
I 33
I RB162
No Shift
134 I Te" P",k.d Bvt. a Sioo
lor--
------
-No ;hlft 8
--
- N"hlf, 8
lor--
No hlft
-No 'hlft
0-',5
'AS02
135 . Nocmollze Sioo Actlv.
-0-; 5
·I?
136 I S'oo,~,
I.Bl71
I 37
138
A•• to FOR
I",
Re~t FDRI"~I.
I AA303
I AA303jKB411
FO' 0-7
'OVNt Swl"h Cootm'
40
T,u,: ood lov.,; 0-15 ~ /iooo/
'8301
TtU.O-
is 'uo 21 I ;v.tt 0-","" 4
TtU' 0-15 '"" ,Iovett 0~15 tVO 4
I DE
10E
FO'In,O-15
141
42
AlU Coo"ol Got.
'A301
43
Addltloool Cony
AA3'J2
44
Six Coc,.dloo 8-11/12-L
t
45
Inkh
10E
AA402
S.t Coodllioo Cod. lotche,
46
i
C~"
10E
47
4R
'"I
I
I MA401
'"'
-
Controlled by CS incr/decr
Controlled by CS byte/haffword
CS byte/halfword --r___-'4-~'__t_--'--'--_;_--+--+_--!_+_t--_+--+--+--t__--r___-__+--+--+--+_-___I!_-_t--_1
f--___I___I-_t--=---,-~__c:,-__,O___:=O,___:_-+_--!_-___I--_+--+--+_--+_--!_-_t--_+--+--+--ond
51
lor 3
(5112
20
52
2
.....
Any che..:k
CC101
J
Only if no CS read (CS write)
l~
Addressed Holfword in SDR
CS Data Out Gate
CS111
Force Regen SDR
CS501
Note: The out actes remain accordina to the last reauested CS format._.
_.
CS byte gating is controlled Iby SAR 15. Tnus, t e gate changing is undefined.
_
•
__ 1__
... _ _
0-151fC5hal~ro;HCS
,.0-7HnoSAR15-8-15HSAR15
0":15
.
Force Regen SDR
f---+",S."-,,,,C,,-5,,,In,,,hl,,bl,,,'""h""'''''-_-l CS111
~
1
r
I
_
CS checks do not couse prac;ess c;heck
Interface or address chec;k resets CS read
Set CS interface check
Any CS request
1
1
1
i
Function signals: 6.Cycle
m
Cycle _
"Do not core" Signals:
.~Cyc;le
c:J
Diagram 5-81. CPU Cycle Steal Operation (Part 2 of 2)
Cyc:ie a::::::J
(03786)
2020250,000 FEMDM Vol 2
(8/69)
0 7 if no SAR 15 8-15 if SAR 15
0-7 if SAR 15 8-15 if nO SAR 15
(Only if CS byte)
CS501
I.
il CS wrIte
0-15 if CS halfword· if CS byte
CS501
CS Store
__1 __1____
_
Cycle steal (CS)
CS read only
_ _ _ _ _ _
READER'S COMMENT FORM
2020 Processing Unit, System/360
Model 20 (Machines with serial no.
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