Series 3000 Reference Manual Feb76

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inter
Series 3000 Family Of
Computing Elements The Total System Solution.
Since its introduction in September, 1974, the Series 3000 family of computing
elements has found acceptance in a wide range of high performance
applications from disk controllers to airborne CPU's.
The Series 3000 family represents more than a simple collection of bipolar
components, it is a complete family of computing elements and hardware/software
support that greatly simplifies the task of transforming a design from concept
to production.
The Series 3000 Component Family

A complete set of computing elements that are designed as a system requiring
a minimum amount of ancillary circuitry.
3001
3002
3003 .
3212
3214
3216/26
ROMs/PROMs
RAMs

Microprogram Control Unit.
Central Processing Element.
Look-Ahead Carry Generator.
Multi-Mode Latch Buffer.
Interrupt Control Unit.
Parallel Bi-directional Bus Driver.
A complete set of bipolar ROMs and PROMs.
A Complete family of MOS and bipolar RAMs.

rhe Series 3000 Support

A comprehensive support system that assists the designer in writing
microprograms, debugging hardware and microcode, and programming
prototype and production PROMs.
CROMIS

Cross microprogram assembler.

MDS-800

Microcomputer development system with TTY/CRT,
line printer, diskette, PROM programmer and high
speed paper tape reader facilities.

ICE-30

In-circuit emulation for the 3001 MCU.

ROM-SIM

ROM simulation for all of Intel's Bipolar ROMs
and PROMs.

Application
Notes

Central processor and disk controller designs and
system timing considerations.

Customer
Course

Comprehensive 3 day course covering the component
family, CPU and controller designs, microprogramming
and the MDS-800, ICE-30 and ROM-SIM operation.

The Series 3000 family is designed to provide a Total System Solution: high
performance, minimum package count and total commitment to support.

Contents

Series 3000
Reference
Manual

INTRODUCTION ........................ 1-1
COMPONENT FAMILY .................. 2-1
3001 Microprogram Control Unit ....... 2-1
3002 Central Processing Element ...... 2-15
3003 Look-Ahead Carry Generator .... 2-31
3212 Multi-Mode Latch Buffer ......... 2-39
3214 Interrupt Control Unit . . . . . . .. . .. 2-49
3216/3226 Parallel Bi-Directional
Bus Driver. . . . . . . . . . . . . . . . . . . . . . . . . .. 2-61
APPLICATIONS ......................... 3-1
3000 Family System Timing ............ 3-1
Disk Controller Designed With Series 3000
Computing Elements. . . . . . . . . . . . . . . . .. 3-9
Central Processor Designs Using The
Intel® Series 3000 Computing
Elements . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-19
ORDERING AND PACKAGING
INFORMATION ......................... 4-1
Ordering Information .................. 4-1
Package Outlines ...................... 4-2

Series 3000 Family

INTRODUCTION
A family architecture

busses to be formed simply by connecting inputs and
outputs together.
Each CPE represents a complete two-bit slice through
the data-processing section of a computer. Several CPES
may be arrayed in parallel to form a processor of any
desired word length. The MCU, which together with the
microprogram memory, controls the step-by-step operation of the processor, is itself a powerful microprogramed state sequencer.
Enhancing the performance and capabilities of these
two components are a number of compatible computing
elements. These include a fast look-ahead carry generator, a priority interrupt unit, and a multimode latch
buffer. A complete summary of the first available members of this family of LSI computing elements and memories is given in the table on this page.

To reduce component count as far as practical, a
multi-chip LSI microcomputer set must be designed as a
complete, compatible family of devices. The omission of
a bus or a latch or the lack of drive current can multiply
the number of miscellaneous SSI and MSI packages to a
dismaying extent-witness the reputedly LSI minicomputers now being offered which need over a hundred extra TIL packages on their processor boards to
support one or two custom LSI devices. Successful integration should .result in a minimum of extra packages,
and that includes the interrupt and the input/output
systems.
With this objective in mind, the Intel Schottky bipolar LSI microcomputer chip set was developed. Its two
major components, the 3001 Microprogram Control
Unit (MCU) and the 3002 Central Processing Element
(CPE), may be combined by the digital designer with
standard bipolar LSI memory to construct high-performance controller-processors (Fig.!) with a minimum
of ancillary logic.
Among the features that minimize package count and
improve performance are: the multiple independent
data and address busses that eliminate time multiplexing and the need for external latches; the three-state
output buffers with high fanout that make bus drivers
unnecessary except in the largest systems, and the separate output-enable logic that permits bidirectional

3001

Microprogram control unit

3002

Central processing element

3003
3212
3214
3216
3226
3601
3604
3301 A

Look.-ahead carry generator
Multimode latch buffer

3304A

CONTROL TO

MEMORY

DATA BUS

MEMORY 110

AOORESS BUS

TO MEMORY

Priority interrupt unit
Noninverting bidirectional bus driver
Inverting bidirectional bus driver
256-by-4-bit programable read-only memory
512-by-8-bit programable read-only memory
256-by-4-bit read-only memory
512-by-8-bit read-only memory .

MICRO
NE~T

ADDRESS

PROGRAM

MEMORY

CONTROL

CLOCK
181T

1 BIT

8 BITS

FROM EXTERNAL
110 DEVICES

DATA IN FROM
MEMORY

1. Bipolar microcomputer. Block diagram shows how to implement a typical 16-bit controller-processor with new family of
bipolar computer elements. An array of eight central processing elements (CPEs} is governed by a microprogram control unit
(MCU} through a separate read-only memory that carries the microinstructions for the various processing elements. This ROM
may be a fast, off-the-shelf unit.
Intll Corporation ... mll no responsibility for the u. of any circuitry or microprogram other than circuitry or microprograms embodied in an Intel product. No other circuit patent licenas Ire implied.

1-1

Series 3000 Family
ePEs form a processor
Each CPE (Fig. 2) carries two bits of five independent
busses. The three input busses can be used in several
different ways. Typically, the K-bus is used for microprogram mask or literal (constant) value input, while
the other two input busses, M and I, carry data from external memory or input/output devices. D-bus outputs
are connected to the CPE accumulator; A-bus outputs
are connected to the CPE memory address register. As
the CPES are wired together, all the data paths, registers,
and busses expand accordingly.
Certain data operations can be performed simply by
connecting the busses in a particular fashion. For example, a byte exchange operation, often used in datacommunications processors, may be carried out by wiring the D-bus outputs back to the I-bus inputs, exchanging the high-order outputs and low-order inputs.
Several other discretionary shifts and rotates can be
accomplished in this manner.
A sixth CPE bus, the seven-line microfunction bus,
controls the internal operation of the CPE by selecting
the operands and the operation to be performed. The
arithmetic function section, under control of the microfunction bus decoder, performs over 40 Boolean and
binary functions, including 2's complement arithmetic
and logical AND, OR, NOT, and exclusive-NOR. It increments, decrements, shifts left or right, and tests for zero.

Unlike earlier MSI arithmetic-iogic units, which contain many functions that are rarely used, the microfunction decoder selects only useful CPE operations.
Standard carry look-ahead outputs, X and y, are generated by the CPE for use with available look-ahead devices or the Intel 3003 Look-ahead Carry Generator. Independent carry input, carry output, shift input, and
shift output lines are also available.
What's more, since the K-bus inputs are always
ANDed with the B-multiplexer outputs into the arithmetic function section, a number of useful functions
that in conventional MSI ALUs would require several
cycles are generated in a single CPE microcycle. The
type of bit masking frequently done in computer control
systems can be performed with the mask supplied to the
K-bus directly from the microinstruction.
Placing the K-bus in either the aU-one or all-zero
state wiU, in most cases, select or deselect the accumulator in the operation, respectively. This toggling effect of
the K-bus on the accumulator nearly doubles the CPE's
repertoire of microfunctions. For instance, with the
K-bus in the all-zero state, the data on the M-bus may
be complemented and loaded into the CPE's accumulator. The same function selected with the K-bus in the
all-one state will exclusive-NOR the data on the M-bus
with the accumulator contents.

MEMORY DATA BUS

MEMORY AOORESS BUS OUTPUTS

MEMORY
ADDRESS
ENABLE

CARRY
LOOK-AHEAD
OUTPUTS

{_j
__--========~lL-l=t:==~==TTll
--:-------------1
x

MICRO-

!+--+-+--+-+--j:>---CARRY INPUT

y

RIPPLE CARRY - OUTPUT
./
SHIFT RIGHT./"
INPUT

EA

CLIO-~-----------+t"'T'"T"""_ _ _ _ _-r-.-J
vee

.-J

{;;O-i

FUNCTION;'
BUS
INPUTS
F,'

I
FUM~g~N

I
I

DECOOER

F,

~

SHIFT RIGHT
OUTPUT

I

CLK.....I

L __ _

__.-J
M,

Mo

~

~--.--­

MEMORY OATA
BUS INPUTS

EXTERNAL MASK BUS
BUS I NPUTS
INPUTS

2. Central processing element. This element contains all the circuits representing a two-bit-wide slice through a small computer's central processor. To build a processor of word width N, all that's necessary is to connect an array of NI2 CPEs together.

1-2

Series 3000 Family
Threelnnovatlonl
other approach would require some type of program
counter. To simplify its logic, the MCV (Fig. 4) uses the
classic approach and requires address control information from each microinstruction. This information is
not, however, simply the next microprogram address.
Rather, it is a highly encoded specification of the next
address and one of a set of conditional tests on the MCV
bus inputs and regist(:rs.
The next-address logic and address control functions
of the MCV are based on a unique scheme of memory
addressing. Microprogram addresses are organized as a
two-dimensional array or matrix. Unlike in ordinary
memory, which has linearly sequenced addresses, each
microinstruction is pinpointed by its row and column
address in the matrix. The 9-bit microprogram address
specifies the row address in the upper 5 bits and the
column address in the lower 4 bits. The matrix can
therefore contain up to 32 row addresses and 16 column addresses for a total of 512 microinstruction
addresses.
The next-address logic of the MCV makes extensive
use of this addressing scheme. For example, from a particular row or column address, it is possible to jump either unconditionally to any other location in that row or
column or conditionally to other specified locations, all
in one operation. For a given location in the matrix
there is a fixed subset of microprogram addresses that
may be selected as the next address. These are referred
to as a jump set, and each type of MCV address control
jump function has ajump set associated with it.
Incorporating a jump operation in every microinstruction improves performance by allowing processing functions to be executed in parallel with program
branches. Reductions in microcode are also obtained
because common microprogram sequences can be
shared without the time-space penalty usually incurred
by conditional branching.
Independently controlled lIag logic in the MCV is
available for latching and controlling the value of the
carry and shift inputs to the CP array. Two lIags, called
C and Z, are used to save the state of the lIag input line.
Under microprogram control, the lIag logic simultaneously sets the state of the lIag output line, forcing the
line to logical 0, logical I, or the value of the C or Z lIag.
The jump decisions are made by the next-address
logic on the basis of: the MCV'S current microprogram
address; the address control function on the accumulator inputs; and the data that's on the macroinstruction
(X) bus or in the program latch or in the lIags. Jump decisions may also be based on the instantaneous state of
the lIag input line without loading the value in one of
the !lags. This feature eliminates many extra microinstructions that would be required if only the lIag lIip1I0p could be tested.
Microinstruction sequences are normally selected by
the operation codes (op codes) supplied by the microinstructions, such as control commands or user instructions in main memory. The MCV decodes these commands by using their bit patterns to determine which is
to be the next microprogram address. Each decoding results in a 16-way program branch to the desired microinstruction sequence.

The power and versatility of the CPE are increased by
three rather novel techniques. The first of these is the
use of the carry lines and logic during non-arithmetic
operations for bit testing and zero detection. The carry
circuits during these operations perform a word-wide
logical OR (oRing adjacent bits) of a selected result from
the arithmetic section. The value of the OR, called the
carry OR, is passed along the carry lines to be ORed with
the result of an identical operation taking place simultaneously in the adjacent higher-order CPE.
Obviously, the presence of at least one bit in the logical I state will result in a true carry output from the
highest-order CPE. This output, as explained later, can
be used by the MCV to determine which microprogram
sequence to follow. With the ability to mask any desired
bit, or set of bits, via the K-bus inputs included in the
carry OR, a powerful bit-testing and zero-detection facility is realized.
The second novel CPE feature is the use of three-state
outputs on the shift right output (RO) and carry output
(CO) lines. During a right shift operation, the CO line is
placed in the high-impedance (Z) state, and the shift
data is active on the RO line. In all other CPE operations,
the RO line is placed in the Z state, and the carry data is
active on the CO line. This permits the CO and RO lines
to be tied together and sent as a single rail input to the
MCV for testing and branching. Left shift operations utilize the carry lines, rather than the shift lines, to propagate data.
The third novel CPE capability, called conditional
clocking, saves microcode and microcycles by reducing
the number of microinstructions required to perform a
given test. One extra bit is used in the microinstruction
to selectively control the gating of the clock pulse to the
central processor (CP) array. Momentarily freezing the
clock (Fig. 3) permits the CPE microfunction to be performed, but stops the results from being clocked into
the specified registers. The carry or shift data that results from the operation is available because the arithmetic section is CQmbinatorial, rather than sequential.
The data can be used as a jump condition by the MCV
and in this way permits a variety of nondestructive tests
to be performed on register data.

Microprogram control
The classic form of microprogram control incorporates a next-address field in each microinstruction-any
MICIIOINSTRlICTlDN WORD .

CPARRAY

3. Conditional clock. This feature permits an extra bit in
microinstruction to selectively control gating of clock pulse
to CP array. Carry or shift data thus made available permits
tests to be performed on data with fewer microinstructions.

1-3

Series 3000 Family
MICROPROGRAM
ROW AOORESS
COLUMN AOORESS

ENABLE ROW AODRESS "'"

r----

INTERRUPT STROBE ENABLE

NEXT
AODRESS
CONTROL
FUNCTION
INPUTS

l

•
._ .... MA.

"

,.------A..---MA J - • . MAo

:~:~

AC.

---f-------l I

AC,----1f-------,
AC, - I f - - - - - - - ,
AC, ----1r-----.,
AC,----1f---.

MICROPROGRAM LO
AOORESS LOAO

PR, }
PR,
PR,

PROGRAM
LATCH
OUTPUTS

__ -.J
FC o Fe,

FI

~

INPUT

FLAG LOGIC
CONTROL

Fa

Fe .. Fe J

PX 7

• · .•• -

px.

~'
•
CONTROL PRIMARY
FLAG LOGIC ---"
INSTRUI~TlONS

\

OUTPUT

,I

SX 3

·· ....

sXo

~

SECONOARY
INSTRUCTIONS
IN

4. Microprogram control unit. The MCU's two major control functions include controlling the sequence of microprograms
fetched from the microprogram memory, and keeping track of the carry inputs and outputs of the CP array by means of the
flag logic control.

Cracking the op cod••

For instance, the Meu can be microprogramed to directly decode conventional 8-bit op codes. In these op
codes the upper 4 bits specify one of up to 16 instruction
classes or address modes, such as register, indirect, or
indexed. The remaining bits specify the particular subclass such as ADD, SKIP IF ZERO, and so on. If a set of op
codes is required to be in a different format, as may occur in a full emulation, an external pre-decoder, such as
ROM, can be used in series with the X-bus to reformat
the data for the Meu.
In rigorous decoding situations where speed or space
is critical, the fu)] 8-bit macroinstruction bus can be
used for a single 256-way branch. Pulling down the load
line of the Meu forces the 8 bits of data on the X-bus
(typically generated by a predecoder) directly into the
microprogram address register.
The data thUs directly determines the next microprogram address which should be the start of the desired microprogram sequence. The load line may also
be used by external logic to force the Meu, at power-up,
into the system re-initialization sequence.

From time to time, a microprocessor must examine
the state of its interrupt system to determine whether an
interrupt is pending. If one is, the processor must suspend its normal execution sequence and enter an interrupt sequence in the microprogram. This requirement is
handled by the Meu in a simple but elegant manner.
When the microprogram flows through address row 0
and column IS, the interrupt strobe enable line of the
Meu is raised. The interrupt system, an Intel 3214 Interrupt Control Unit, responds by disabling the row address outputs of the Meu via the enable row address
line, and by forcing the row entry address of the microprogram interrupt sequence onto the row address bus.
The operation is normally performed just before the
macroinstruction fetch cycle, so that a macroprogram is
interrupted between, not during, macroinstructions.
The 9-bit microprogram address register and address
bus of the Meu directly address 5 12 microinstructions.
This is about twice as many as required by the typical
16-bit disk-controller or central processor.

1-4

Series 3000 Family
STANOARO fUNCTION flELOS

USER·DEfINABLE fUNCTION flELOS

A

r~-------------------#A~------------------~\ r
CPARRAY
fUNCTION

I

fLAG LOGIC
fUNCTION

I --

JUMP
fUNCTION

:::S-;" flELO

' - -_ _ _ _---L_ _ _ _ _ _ _ _ _---L. _ _ -

I-- 7

I"I.~

BITS - - _ a

-+1,_--7

4 BITS ........

-TI

____

\

-::O:L7R:s:R-l
fUNCTIONS
I

J.- - -

-+1. . ---

BITS--_.I"I.>---- N BITS - -.....

-4~

__ J

n'BITS---.j

5. Microinstruction format. Only a generalized microinstruction format can be shown since allocation of bits for the mask
field and optional processor functions depends on the wishes of the designer and the tradeoffs he decides to make.
Moreover, multiple 512 microinstruction memory
planes can easily be implemented simply by adding an
extra address bit to the microinstruction each time the
number of extra planes is doubled. Incidentally, as the
number of bits in the microinstruction is increased.
speed is not reduced. The additional planes also permit
program jumps to take place in three address dimensions instead of two.
Because of the tremendous design flexibility offered
by the Intel computing elements, it is impossible to describe every microinstruction format exactly. But generally speaking. the formats all derive from the one in Fig.
5. The minimum width is 18 bits: 7 bits for the address
control functions. plus 4 bits for the flag logic control:
plus 7 bits for the CPE microfunction control.
More bits can be added to the microinstruction format to provide such functions as mask field input to the
CP array. external memory control. conditional clocking.
and so on. Allocation of these bits is left to the designer
who organizes the system. He is free to trade off
memory costs. support logic. and microinstruction
cycles to meet his cOSt/performance objectives.

The cOlt/performance spectrum

The total flexibility of the Intel LSI computing elements is demonstrated by the broad cost/performance
spectrum of the controllers and processors that can be
constructed with them. These include:
• High-speed controllers. built with a stand-alone ROMMCV combination that sequences at up to 10 megahertz; it can be used without any CPES as a system state
coniroller.
• Pipelined look-ahead carry controller-processors,
where the overlapped microinstruction fetch/execute
cycles and fast-carry logic reduce the l6-bit add time to
less than 125 nanoseconds.
• Ripple-carry controller processors (a l6-bit design
adds the contents of two registers in 300 nanoseconds).
• Multiprocessots. or networks of any of the above controllers and processors, to provide computation, interrupt superviSion. and peripheral control.
These configurations represent a range of microinstruction execution rates of from 3 million to 10 million instructions per second, or up to two orders of
magnitude faster, for example, than p-channel microprocessors. Moreover, the increases in processor performance are achieved with relative simplicity. A
ripple-carry l6-bit processor uses one MCV, eight CPES.
plus microprogram memory. One extra computing element, the 3003 Look-ahead Carry Generator, enhances
. the processor with fast carry. Increasing speed further
by pipe lining, the overlap of microinstruction fetch and
execute cycles, requires a few D-type MSI flip-flOps.
At the multiprocessor level, the microprogram
memory, MCV. or CPE devices can be shared. A l6-bit
processor. complete with bus control and microprogram
memory. requires some 20 bipolar LSI packages and
half that many small-scale ICs. In this configuration. it
replaces an equivalent MSI TIL system having more
than 200 packages.
Furthermore. systems built with this large-scale integrated circuitry are much smaller and less costly and
consume less energy than equivalent designs using
lower levels of transistor-transistor-logic integration.
Even allowing for ancillary logic circuits. the new bipolar computing elements cut 60% to 80% off the package
count in realizing most of today's designs made with
small- or medium-scale-integrated TIL.

Microprograming technology
• Microprogram: A type of program that directly
controls the operation of each functional element in a
microprocessor.
• Mlcrolnllrucllon: A bit pattern that is stored in a
microprogram memory word and specifies the operation of the individual LSI computing elements and related subunits, such as main memory and input loutput interfaces.
• Mlcrolnllrucllon lequence: The series of microinstructions that the microprogram control unit (MCU)
selects from the microprogram to execute a single
macroinstruction or control command. Microinstruction sequences can be, shared by several macroinstructions.
• Macrolnllructlon: Either a conventional computer
instruction (e.g. ADD MEMORY TO REGISTER, INCREMENT, and SKIP, etc.) or device controller command (e.g., SEEK, READ, etc.).

1-5

intel"

SCHOTTKY
BIPOLAR LSI
MICROCOMPUTER

3001
MICROPROGRAM
CONTROL UNIT

SET
The INTEL ® 3001 Microprogram Control Unit (MCU) controls the sequence in
which microinstructions are fetched
from the microprogram memory. Its
functions include the following:
Maintenance of the microprogram
address register.
Selection of the next microinstruction
based on the contents of the microprogram address register.
Decoding and testing of data supplied
via several input busses to determine
the microinstruction execution
sequence.
Saving and testing of carry output data
from the central processor (CP) array_
Control of carry/shift input data to
the CP array.
Control of microprogram interrupts_

High Performance - 85 ns Cycle
Time
TTL and DTL Compatible
Fully Buffered Three-State and Open
Collector Outputs
Direct Addressing of Standard Bipolar
PROM or ROM
512 Microinstruction Addressability
Advanced Organization
9-Bit Microprogram Address Regjster
and Bus
4·Bit Program Latch
Two Flag Registers
Eleven Address Control Functions
Three Jump and Test Latch
Functions
16·way Jump and Test Instruction
Bus Function
Eight Flag Control Functions
Four Flag Input Functions
Four Flag Output Functions
40 Pin DIP

2-1

PACKAGE CONFIGURATION

px.
PX 7
PX6
PX 5
sX 3
SX 2
PR 2
sx,
PR,
sXo
PRo
FC3
FC 2
FO
FC o
FC,
FI
ISE
ClK
GND

vcc
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

INTEl@

3001

~~
30
29

28
27
26
25
24
23
22
21

ACo
AC,
AC5
lD
ERA
MAs
MA7
MA6
MA.
MA.
MAo
MA3
MA2
MA,
EN
AGo
AC.
AC3
AC2

3001
PIN DESCRIPTION
NAME AND FUNCTION

TYPE 111

1-4

Primary Instruction Bus Inputs
Data on the primary instruction bus is tested by the JPX function to
determine the next microprogram address_

active LOW

5,6,8,10

Secondary Instruction Bus Inputs
Data on the secondary instruction bus is synchronously loaded into the
PR-Iatch while the data on the PX-bus is being tested (JPX)_ During a
subsequent cycle, the contents of the PR-Iatch may be tested by the
JPR, JLL, or JRL functions to determine the next microprogram address_

active LOW

7,9,11

PR-Latch Outputs
The PR-Iatch outputs are asynchronously enabled by the JCE function_
They can be used to modify microinstructions at the outputs of the
microprogram memory or to provide additional control lines_

open collector

PIN

SYMBOL

12,13,15,
16

·FC O- FC3

Flag Logic Control Inputs
The flag logic control inputs are used to cross-switch the flags (C and Z)
with the flag logic input (FI) and the flag logic output (FO).

14

FO

Flag Logic Output
The outputs of the flags (C and Z) are multiplexed internally to form the
common flag logic output_ The output may also be forced to a logical 0
or logical 1_

active LOW
three-state

17

FI

Flag Logic Input
The flag logic input is demultiplexed internally and applied to the inputs
of the flags (C and Z). Note: the flag input data is saved in the F-Iatch
when the clock input (CLK) is low_

active LOW

18

ISE

Interrupt Strobe Enable Output
The interrupt strobe enable output goes to logical 1 when one of the JZR
functions are selected (see Functional Description, page 6). It can be used
to provide the strobe signal required by the INTEL 3214 Priority Interrupt
Control Unit or other interrupt circuits_

19

CLK

Clock Input

20

GND

Ground

21-24
37-39

ACo-ACs

Next Address Control Function Inputs
All jump functions are selected by these control lines.

25

EN

Enable Input
When in the HIGH state, the enable input enables the microprogram
address, PR-Iatch and flag outputs.

26-29

MAo-MA3

Microprogram Column Address Outputs

three-state

30-34

MA,j-MAa

Microprogram Row Address Outputs

three-state

35

ERA

Enable Row Address Input
When in the LOW state, the enable row address input independently
disables the microprogram row address outputs. It can be used with the
INTEL 3214 Priority Interrupt Control Unit or other interrupt circuits
to facilitate the implementation of priority interrupt systems.

36

LD

Microprogram Address Load Input
When in the active HIGH state, the microprogram address load input
inhibits all jump functions and synchronously loads the data on the
instruction busses into the microprogram registllr. However, it does not
inhibit the operation of the PR-Iatch or the generation of the interrupt
strobe enable.

40

VCC

+5 Volt Supply

NOTE:
111 Active HIGH unless otherwise specified_

2-2

3001
LOGICAL DESCRIPTION
The MCU performs two major control
functions. First, it controls the sequence
in which microinstructions are fetched
from the microprogram memory. For
this purpose, the MCU contains a microprogram address register and the
associated logic for selecting the next
microinstruction address. The second
function of the MCU is the control of
the two flag flip·flops that are included
for interaction with the carry input and
carry output logic of the CP array.
The logical organization of the MCU
is shown in Figure 2.
NEXT ADDRESS LOGIC
The next address logic of the MCU pro·
vides a set of conditional and uncondi·
tional address control functions. These
address control functions are used to
implement a jump or jumpltest opera·
tion as part of every microinstruction.
That is to say, each microinstruction
typically contains a jump operation field
that specifies the address control
function, and hence, the next micro·
program address.

In order to minimize the pin count of
the MCU, and reduce the complexity of
the next address logic, the microprogram
address space is organized as a two
dimensional array or matrix. Each
microprogram address corresponds to
a unit of the matrix at a particular
row and column location. Thus, the 9bit microprogram address is treated as
specifying not one, but two addresses the row address in the upper five bits
and the column address in the lower
four bits. The address matrix can therefore contain, at most, 32 row addresses
and 16 column addresses for a total of
512 microinstructions.

possible jump target addresses are referred
to as a jump set. Each type of MCU
address control (jump) function has a
jump set associated with it. Appendix
C illustrates the jump set for each
function.
FLAG LOGIC
The flag logic of the MCU provides a
set of functions for saving the current
value of the carry output of the CP
array and for controlling the value of
the carry input to the CP array. These
two distinct flag control functions are
called flag input functions and flag
output functions.

The next address logic of the MCU
makes extensive use of this two component addressing scheme. For example,
from a particular row or column
address, it is possible to jump uncon·
ditionally in one operation anywhere in
that row or column. It is not possible,
however, to jump anywhere in the
address matrix. In fact, for a given location in the matrix, there is a fixed sub·
set of microprogram addresses that may
be selected as the next address. These

The flag logic is comprised of two
flip·flops, designated the C-flag and the
Z-flag, along with a simple latch, called
the F-Iatch, that indicates the current
state of the carry output line of the
CP array. The flag logic is used in conjunction with the carry and shift logic
of the CP array to implement a variety
of shift/rotate and arithmetic functions.

ENABLE

ROW

MICROPROGRAM MEMORY
ADDRESS

ADDRESS

MAo - - -

ERA

.....

MAo - - MAo

INTERRUPT
STROBE
ISE
ENABLE
EN

ACe

MCUOUTPUT
ENABLE

AC,
ADDRESS
CONTROL
fUNCTION

AC,
AC,
AC,
AC,
AC.

LOAD

LD

GND-,

~l-l--f~::~~+--PR2

vee ---.I

MOGRAM

I

PR, LATCH
' -_ _ _l""T"-PRO OUTPUTS

I
I
I

I
I

I
---~

FCo Fe,
FLAG

FLAG

FLAG

FLAG

PRIMARY

LOGIC

INPUT

OUTPUT

LOGIC

INSTRUCTION

CONTROL

BUS

CONtROL

F,

FO

FC2 FC3 PX, - - PX4

Figura 2. 3001 Block Diagram

2-3

SX3

-

-

SXo

SECONDARY
INSTRUCTION

aus

3001
FUNCTIONAL DESCRIPTION
ADDRESS CONTROL FUNCTIONS
The address control functions of the
MCU are selected by the seven input
lines designated ACO-ACS. On the
rising edge of the clock, the 9-bit microprogram address generated by the next
address logic is loaded into the microprogram address register. The next
microprogram address is delivered to the
microprogram memory via the nine
output lines designated MAo-MAs. The
microprogram address outputs are organized into row and column addresses
as:

JZR

Jump to zero row.
ACO-AC3 are used to
select 1 of 16 column
addresses in rowO, as the
next address.

JCR

Jump in current row.
ACO-AC3 are used to
select 1 of 16 addresses
in the current row, specified by MA4-MAS, as
the next address.

JCE

Jump in current column/
row group and enable
PR-Iatch outputs. ACoAC2 are used to select 1
of 8 row addresses in the
current row group, specified by MA7-MAs, as
the next row address. The
current column is specified by MAo-MA3. The
PR-Iatch outputs are
asynchronously enabled.

MAS MA7 MAs MA5 MA4
row address
MA3 MA2 MA, MAo
column address
Each address control function is specified by a unique encoding of the data on
the function input lines. From three to
five bits of the data specify the particular function while the remaining bits
are used to select part of either the row
or column address desired. Function
code formats are given in Appendix A,
"Address Control Function Summary."
The following is a detailed description
of each of the eleven address control
functions. The symbols shown below
are used throughout the description to
specify row and column addresses.
Symbol

Meaning
5-bit next row address
where n is the decimal row
address.

coin

4-bit next column address
where n is the decimal
column address.

FLAG CONDITIONAL ADDRESS
CONTROL (JUMP/TEST)
FUNCTIONS
The jump/test flag functions use the
current microprogram address, the contents of the selected flag or latch, and
several bits from the address control
function to generate the next microprogram address.
Mnemonic
JFL

UNCONDITIONAL ADDRESS CONTROL (JUMP) FUNCTIONS
The jump functions use the current
microprogram address (i.e., the contents
of the microprogram address register
prior to the rising edge of the clock) and
several bits from the address control inputs to generate the next microprogram
address.
Mnemonic

Function Description

JCC

Jump in current column.
ACo-AC4 are used to
se Iect 1 of 32 row addresses in the current
column, specified by

row group, specified by
MA7 and MAs, as the
next row address. If the
current column group
specified by MA3 is
coIO-coI7, the C-flag is
used to select col2 or
col3 as the next column
address. If MA3 specifies
column group cols-col,5,
the C-flag is used to select
col,O or col" as the next
column address.

MAO-MA3, as the next
address

JCF

JZF

Jump/test Z-flag. Identical
to the JCF function described above, except
that the Z-flag, rather
than the C-flag, is used to
select the next column
address.

PX-BUS AND PR-LATCH CONDITIONAL ADDRESS CONTROL
(JUMPITEST) FUNCTIONS
The PX-bus jump/test function uses the
data on the primary instruction bus
(PX4-PX71. the current mircoprogram
address, and several selection bits from
the address control function to generate
the next microprogram address. The
PR-Iatch jump/test functions use the
data held in the PR-Iatch, the current
microprogram address, and several selection bits from the address control
function to generate the next microprogram address.

Function Description

Mnemonic

Function Description

Jump/test F-Latch.
ACO-AC3 are used to
select 1 of 16 row addresses in the current
row group, specified by
MAs, as the next row
address. If the current
column group, specified
by MA3, is colo-coI7,
the F-Iatch is used to
select col2 or col3 as the
next column address. If
MA3 specifies column
group coIS-col,5, the
F-Iatch is used to select
col1O or col" as the
next column address.

JPR

Jump/test PR-Iatch.
ACO-AC2 are used to
select 1 of 8 row addresses in the current
row group, specified by
MA7 and MAS, as the
next row address. The
four PR-Iatch bits are
used to select 1 of 16
possible column addresses as the next
column address.

Mnemonic

Function Description

JLL

Jump/test leftmost PRlatch bits. ACO-AC2 are
used to select 1 of 8 row
addresses in the current
row group, specified by
MA7 and MAS, as the
next row address. PR2
and PR3 are used to

Jump/test C-flag.
ACO-AC2 are used to
select 1 of 8 row addresses in the current

2-4

3001
FUNCTIONAL DESCRIPTION (con't)
select 1 of 4 possible
column addresses in col4
through col7 as the next
column address.
JRL

JPX

Jump/test rightmost P R·
latch bits. ACo and ACl
are used to select 1 of 4
high·order row addresses
in the current row group,
specified by MA7 and
MAS, as the next row
address. PRo and PRl are
used to select 1 of 4 possible column addresses in
col12 through coilS as the
next column address.
Jump/test PX·bus and
load PR-Iatch. ACo and
ACl are used to select 1
of 4 row addresses in the
current row group, specified by MAs-MAS' as the
next row address. PX4PX7 are used to select 1
of 16 possible column
addresses as the next
column address. SXO. SX3 data is locked in the
PR-Iatch at the rising
edge of the clock.

FLAG CONTROL FUNCTIONS
The flag control functions of the MCU
are selected .by the four input lines
designated FCO-FC3. Function code
formats are given in Appendix B, "Flag
Control Function Summary."
The following is a detailed description
of each of the eight flag control
functions.
FLAG INPUT CONTROL FUNCTIONS
The flag input control functions select
which flag or flags will be set to the current value of the flag input (FI) line.
Data on FI is stored in the F-Iatch when
the clock is low. The content of the Flatch is loaded into the C and/or Z flag
on the rising edge of the clock.
Mnemonic

Function Description

SCZ

Set C-flag and Z-flag to
FI. The C-flag and the Zflag are both set to the
value of FI.

STZ

Set Z-flag to F I. The Zflag is set to the value of
FI. The C-flag is
unaffected.

STC

Set C-flag to F I. The Cflag is set to the value of
FI. The Z flag is
unaffected.

HCZ

Hold C-flag and Z-flag.
The values in the C-flag
and Z-flag are unaffected.

FLAG OUTPUT CONTROL
FUNCTIONS
The flag output control functions
select the value to which the flag output (FO) line will be forced.
Mnemonic

Function Description

FFO

Force FO to o. FO is
forced to the value of
10gicalO.

FFC

Force FO to C. FO is
forced to the value of
the C-flag.

FFZ

Force FO to Z. FO is
forced to the value of
the Z-flag.

FF1

Force FO to 1. FO is
forced to the value of
logical 1.

2-5

LOAD AND INTERRUPT
STROBE FUNCTIONS
The load function of the MCU is controlled by the input line designated LD.
If the LD line is active HIGH at the
rising edge of the clock, the data on
the primary and secondary instruction
busses, PX4-PX7 and SXO-SX3, is
loaded ·into the microprogram address
register. PX4-PX7 are loaded into
MAo-MA3 and SXO-SX3 are loaded
into M~-MA7. The high-order bit of
the microprogram address register MAs
is set to a logical O. The bits from the
primary instruction bus select 1 of 16
possible column addresses. Likewise,
the bits from the secondary instruction
bus select 1 of the first 16 row addresses.
The interrupt strobe enable of the MCU
is available on the output line designated
ISE. The line is placed in the active high
state whenever a JZR to COl15 is selected
as the address control function. Customarily, the start of a macroinstruction
fetch sequence is situated at rowo and
COl15 so that the INTEL 3214 Priority
Interrupt Control Unit may be enabled
at the beginning of the fetch/execute
cycle. The priority interrupt control
unit may respond to the interrupt by
pulling the enable row address (ERA)
input line down to override the selected
next row address from the MCU. Then
by gating an alternative next row address
on to the row address lines of the microprogram memory, the microprogram
may be forced to enter an interrupt
handling routine. The alternative row
address placed on the microprogram
memory address lines does not alter
the contents of the microprogram
address register. Therefore, subsequent
jump functions will utilize the row
address in the register, and not the
alternative row address, to determine
the next microprogram address.
Note, the load function always overrides
the address control function on ACoACe. It does not, however, override the
latch enable or load sub-functions of the
JCE or JPX instruction, respectively. In
addition, it does not inhibit the interrupt
strobe enable or any of the flag control
functions.

3001
D.C. AND OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , O°C to· 70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +160°C
All Output and Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ;).5V to +7V
All Input Voltages

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +5.5V

Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 mA
·COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanont damage to tho device. Thi. i•••tro•• rating only

of

and functional operation
the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

TA = O°C to 70°C

Vec = 5.0V ±5%

SYMBOL

PARAMETER

Vc

Input Clamp Voltage (All
Input Pins)

IF

Input Load Current:
CLK Input
EN Input
All Other Inputs

IR

MIN

TYP(1)

MAX

--o.B

-1.0

--0.075
--0.05
--0.025

Input Leakage Current:
ClK
EN Input
All Other Inputs

V

Ic =-5.mA

--0.75
--0.50
--0.25

mA
mA
mA

VF =0.45V

120

j.lA
j.lA
j.lA

VR

80
40

VIL

Input low Voltage

VIH

Input High Voltage

Icc

Power Supply Current (21

170

240

VOL

Output low Voltage
(All Output Pins)

0.35

0.45

VOH

Output High Voltage
(MAo-MAs. ISE. FO)

los

Output Short Circuit Current
(MAo-MAs. ISE. FO)

10 (of!)

O.B
2.0

2.4
-15

CONDITIONS

UNIT

V

= 5.25V

Vcc

= 5.0V

V

3.0
-28

Off-State O~tPut Current:
MAo-M.AS. FO
MAo-MAs. F.O. PRo-PR2

NOTES:
(1) Typical values are for TA = 25°C and nominal supply voltage.
(2) EN input grounded. all other inputs and outputs open.

2-6

mA
V

10L = 10mA

V

10H =-1 mA

--60

mA

Vec = 5.0V

-100
100

j.lA
j.lA

Vo = 0.45V
Vo = 5.25V

3001
A.C. CHARACTERISTICS AND WAVEFORMS
SYMBOL

TA ..

o·c to 70·C. vcc

PARAMETER

= 5.0V ±5%

MIN

Typl'l

MAX

UNIT

tCY

Cycle Time (21

85

60

ns

twp

Clock Pulse Width

30

20

ns

tSF
tSK
tsx
tSI

Control and Data Input Set·Up Times:
lD. ACo-ACS
FCO.FC,
SXO-SX3. PX4-PX7
FI

10
0
35
15

0

ns
ns
ns
ns

tHF
tHK
tHx
tHI

Control and Data Input Hold Times:
lD. ACo-ACs
FCo. FC,
SXO-SX3. PX4-PX7
FI

5
0
20
20

0

10

30

45

ns

25
5

ns
ns
ns
ns

5
8

tco

Propagation Delay from Clock Input (ClKI to Outputs
(MAo-MAs. Fa)

tKO

Propagation Delay from Control Inputs FC2 and FC3 to Flag
Out (Fa)

16

30

ns

tFO

Propagation Delay from Control Inputs ACo-ACs to latch
Outputs (PRo-PR2)

26

40

ns

tEO

Propagation Delay from Enable Inputs EN and ERA to Outputs
(MAo-MAs. Fa. PRo-PR2)

21

32

ns

tFI

Propagation Delay from Control Inputs ACo-ACS to Interrupt
Strobe Enable Output (lSE)

24

40

ns

NOTE:
I1l Typical values are for TA • 25°C and nominal supply voltage.
121 tCY = twp + tSF + tco

TEST CONDITIONS:

TEST lOAD CIRCUIT:
vee

Input pulse amplitude of 2.5 volts.
Input rise and fall times of 5 ns between 1 volt and 2 volts.
Output load of 10 mA and 50 pF.
Speed measurements are taken at the 1.5 volt level.

soon
OUT
1 Kfl

50pF

-=CAPACITANCE(21 T A .. 25·C

TYP

MAX

UNIT

Input Capacitance:
ClK.EN
All Other Inputs

11
5

16
10

pF
pF

Output Capacitance

6

12

pF

SYMBOL
CIN

CoUT

MIN

PARAMETER

NOTE:
(21 This parameter is periodically sampled and is not 100% tested. Condition 01 measurement is 1·1 MHz. VBIAS· 2.SV. Vcc = SV and
TA=2SoC.

2·7

3001
D.C. AND OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -i55°C to +160°C
All Output and Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -il.5V to +7V
All Input Voltages

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +5.5V

Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 mA
'COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sactions of this specification is not
implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

SYMBOL

PARAMETER

Vc

Input Clamp Voltage (All
Input Pins)

IF

Input load Current:
ClK Input
EN Input
All Other Inputs

IR

MIN

Typ (1 )

MAX

-0.8

-1.2

V

IC =-5mA

-75
-50
-25

-750
-500
-250

IJ.A
IJ.A
IJ.A

VF = 0.45V

120
80
40

IJ.A
IJ.A
IJ.A

VR = 5.5V

Input Leakage Current:
CLK
EN Input
All Other Inputs

VIL

Input Low Voltage

VIH

Input High Voltage

Icc

Power Supply Current (2)

170

250

VOL

Output Low Voltage
(All Output Pins)

0.35

0.45

VOH

Output High Voltage
(MAo-MA8. ISE. FO)

los

Output Short Circuit Current
(MAo-MAs. ISE. FO)

10 (off)

Off·State Output Current:
MAO-MA8. FO
MAo-MA8. F.O. PRo-PR2

0.8
2.0

UNIT

V

CONDITIONS

Vcc = 5.0V

V

2.4

3.0

-15

-28

NOTES:
(1) Typical values are for TA = 2SoC and nominal supply voltage.
(2) EN input grounded. all other inputs and outputs open.

2-8

mA
V

10L = 10 mA

V

10H =-1 mA

-60

mA

Vcc = 5.0V

-100
100

IJ.A
IJ.A

Va = 0.45V
Va = 5.5V

4f'L/lr~

3001

A.C. CHARACTERISTICS AND WAVEFORMS
SYMBOL

PARAMETER

MIN

Typ (1 )

MAX

UNIT

tCY

Cycle Time (2)

95

60

ns

twp

Clock Pulse Width

40

20

ns

tSF
tSK

Control and Data Input Set-Up Times:
lD. ACo-AC6
FCo. FC,
SXO-SX3. PXot-PX7
FI

10
0
35
15

0

ns
ns
ns
ns

Control and Data Input Hold Times:
lD. ACO-AC6
FCo. FC,
SXO-SX3. PX4-PX7
FI

5
0
25
22

0

8

10

30

45

ns

Propagation Delay from Control Inputs FC2 and FC3 to Flag
Out (FO)

16

50

ns

Propagation Delay from Control Inputs ACO-AC6 to latch
Outputs (PRo-PR2)

26

50

ns

Propagation Delay from Enable Inputs EN and ERA to Outputs
(MAo-MAs. FO. PRo-PR2)

21

35

ns

Propagation Delay from Control Inputs ACO-AC6 to Interrupt
Strobe Enable Output (lSE)

24

40

ns

tsx
tsl

Propagation Delay from Clock Input (ClK) to Outputs
(MAo-MAs. FO)

NOTE:
II) Typical.alues are lor TA
121 tCY = twp + tSF + tco

25
5

ns
ns
ns
ns

5

= 25°C and nominal supply voltage.

TEST CONDITIONS:

TEST lOAD CIRCUIT:
Vee

Input pulse amplitude of 2.5 volts.
Input rise and fall times of 5 ns between 1 volt and 2 volts.
Output load of 10 mA and 50 pF.
Speed measurements are taken at the 1.5 volt level.

500n

OUTo-......- - i
1 Kfl

50pF

CAPACITANCE (2 ) TA = 25°C

SYMBOL
CIN

COUT

TYP

MAX

UNIT

Input Capacitance:
ClK.EN
All Other Inputs

MIN

11
5

16
10

pF
pF

Output Capacitance

6

12

pF

PARAMETER

NOTE:
121 This parameter is periodically sampled and is not 100% tested. Condition 01 measurement is I
TA = 25°C.

2-9

= 1 MHz. VBIAS = 2.5V. Vcc = 5V and

3001
3001 WAVEFORMS

CLK
CLOCK INPUT

~

/
\

1/

\
\

J

/

~IW~
ICY

EN. ERA
ENABLE INPUTS

V

1\
E-tco
---l

-----l>

f\1
11\

lEO

MAO·MAS
CONTROL MEMORY
ADDRESS OUTPUTS

E---- -IHF

ISF-----)

\f

ACO-AC6. LD
ADDRESS CONTROL
INPUTS

/\
'f---IEO- -----l>
----'l

IFO

E--

V
1\

PRO-PR2
"PR" LATCH OUTPUTS
iE-IHK

tsK

\V
11\

FCO-FC3
FLAG CONTROL
INPUTS
IHI

lSI

E--

\1
1\

FI
FLAG INPUT
iE--IKO
E--IEO-

E-tco

V

FO
FLAG OUTPUT

"E--IFI---J

\/
\

ISE
INTERRUPT STROBE
ENABLE OUTPUT
IHX

ISX

SXO-PX7
INSTRUCTION
BUS INPUTS

2-10

)1

3001
TYPICAL AC AND DC CHARACTERISTICS
CLOCK PULSE WIDTH Vs. VCC AND TEMPERATURE

ICC VS. TEMPERATURE
190

40

Vee·5.0V

190
126'C

-~

V

170

0

~

26'C

0

5.0

4.75

4.6

160

&.60

6.26

"'

-56 C

O'C

70 C

26"C

126"C

TEMPERATURE (OC)

Vee

CLOCK TO mA OUTPUTS VS. LOAD CAPACITANCE

OUTPUT CURRENT VS. OUTPUT LOW VOLTAGE
6O.-------,--------r------~------_,

40

Vee - I.OV
30

-56°C

--

1

12&°C
26'

E
a:

0

6Or--------r--------r--------r--~~~

a

.r--------r------~~--~~~------_;

~

3Or-------+-----~~~----_t------~
25'C
70'C
126'C

0
4.6

5.0

4.7&

5.5

5.25

°0~----~~~----~0.~4------~0.8~----~0~

5.75

Vee

OUTPUT VOLTAGE (VOLTSI

CLOCK TO MA OUTPUTS VS. LOAD CAPACITANCE

OUTPUT CURRENT VS. OUTPUT HIGH VOLTAGE

60

we

-----

1MAo

r- Vee -

5.0V -

TA • WC

~

.--

Vee

~

160

300

260

300

~

-40

350

LOAD CAPACITANCE (pFI

".

IJ

~r'

~
o

1.0

2.0

3.0

OUTPUT VOLTAGE (VOLTS)

2-11

r"-?O'C
26"c

/

5

-35
100

~ 1"26'C
~

0

60

-6&'C
O'C

~

5

0

-~.ov

4.0

5.0

3001
APPENDIX A

ADDRESS CONTROL FUNCTION SUMMARY
FUNCTION

MNEMONIC

NEXT ROW

AC6 S

m,

mo

d2

d,

dO

mS

m4

d3

d2

d,

dO

d2

d,

dO

m3

m2

m,

mo

d3

d2

d,

do

m3

0

ma m7

d2

d,

dO

m3

0

ma m7

d2

d,

do

m3

0

do

ma m7

d2

d,

do

P3

P2

do

ma m7

d2

d,

do

0

d,

dO

d,

do

do

d4

d3

d2

d,

do

0

0

0

d3

d2

d,

dO . ma m7

m6

0

d2

d,

dO

d3

d2

d,

do

ma

0

d2

d,

dO

d2

d,

do

d2

d,

d2

d,

0

JCE

Jump in column/enable

JFL

Jump/test F-Iatch

0

JCF

Jump/test C-flag

0

JZF

Jump/test Z-flag

0

JPR

Jump/test PR-Iatches

0

JLL

Jump/test left PR bits

0

JRL

Jump/test right PR bits

JPX

Jump/test PX-bus

0

0

0

SYMBOL

MEANING

dn

Data on address control line n
Data in microprogram address register bit n
Data in PR-Iatch bit n
Data on PX-bus line n (active LOW)
Contents of F-Iatch. C-flag. or Z-flag. respectively

0

ma m7

dO

ma m7

1

d,

do

ma m7

mS

DESCRIPTION

MNEMONIC

FC,

0

0

SCZ

Set C-flag and Z-flag to f

0

STZ

Set Z-flag to f

0

STC

Set C-flag to f

HCZ

Hold C-flag and Z-flag

0

DESCRIPTION

MNEMONIC

FC3

2

Force Fa to 0

0

0

FFC

Force Fa to C-flag

0

FFZ

Force Fa to Z-flag

FFl

Force Fa to 1

LOAD
FUNCTION
LD

MAs

0

see Appendix A
0

7

x3

s

x2

S

4

MA3

2

0

see Appendix A
x,

Xo

x7

Xs

SYMBOL

MEANING

xn

Contents of the F-Iatch
Data on PX- or SX-bus line n (active LOW)

1
0

NEXT COL

NEXT ROW

Xs

2-'2

6

d,

FLAG CONTROL FUNCTION SUMMARY

FFO
Flag
Output

m2

d3

d,

d2

Jump in current row

TYPE

m3

d2

d3

JCR

Flag
Input

do
0

d3

0

0

APPENDIX B

d,
0

d4

0

Jump to zero row

Pn
xn
f. c. z

MA3

2

Jump in current column

mn

4

3

JZR

0

MAS 7

4

JCC

TYPE

NEXT COL

DESCRIPTION

X4

S

X7

2

Xs

0

c

p,

Po

P3

P2

p,

Po

Xs

x4

3001
APPENDIX C

JUMP SET DIAGRAMS

JCC
Jump in Current Column

JZR
Jump to Zero Row

The following ten diagrams illustrate
the jump set for each of the eleven
jump and jump/test functions of the
MCU. Location 341, indicated by the
black square, represents one current
row (row21 ) and current column (COI5)
address. The grey boxes ind icate the
microprogram locations that may be
selected by the particular function as
the next address.
row31---i>

t t

colo current

column
JCF, JZF
Jump/Tlit C-FI8g
Jump/Test Z-FI8g

JFL
Jump/Tlit F·Lau:h
JCR
Jump in Current Row

JCE
Jump Column/En.....

current row

current
row
group

group

Ma7
10

Ma7
10

current column

JLL
Jump/Tlit Left Latch

JPR

Jump/Tlit PR·Latch

JRL
Jump/Tlit Right Latch

currant
.ow

JPX

Jump/Tlit PX-Bul

:,rentL

group

Ma7
10

group

M,~tJ

2-13

3001
TYPICAL CONAGURATIONS

r'S-,--~'~R7A~M~A~'~""~"'~""-"'~"'~""~M~A-0--------"N~
AC.
360.
PROM

A,
ClK

TO 3002 CP ARRAY
3604
PROM

1

~8
Non-Pipelined Configuration with
512 Microinstruction Addressability

IIIII

sv

cs,··cs. AO

Os

°5 ..... 0 ,

3604
PROM

3604
PROM

cs, ··CS4 Ao

·················A8

············--·A8

PROM

CS,.-CS4 AO'"

···.0,

t

'"'"'

360'

PROM

. ···-A8

CS,··CS. AO ················-Aa

sv

II
.11

AS"

···········AOCS4-·CS'

A8 ········ __ ······-AOCS4--CS'

-.ll

A8 ·················.4.0 CS4"CS,

360.

3604

PROM

380.

PROM

PROM

08 ··········· .. ··0,

08 ···············0,

Os ·····.. ·······0,

II

A8·················AOCS4··CS'

360'

PROM
Oa ·············0,

MAa··· ........... MAo

IS'

lllI_~_~ACO

AC,
AC,
AC3
AC,
ACs
AC.

'NW

3001

MCU

TO MEMORY DATA BUS

U§~sv~~~~~~r;:-:JI
ig
2D

3D

2Q~

30-

L=::j:=!==/

~~-======:::::::...J

eLK
NOTE;

5V

Two O-Iype flip-flops of the '5174 pipeline register ate used as the
microprogram address reglst.r 81(1I1'1S1on.

Pipelined Configuration with

2048 Microinstruction Addressability

2-14

CLK

0-- CLR
~

PIPELINE
REGISTER

TO 3002 CPARRAV

SCHOTTKY
BIPOLAR LSI
MICROCOMPUTER
SET

The INTE L® 3002 Central Processing
Element contains all of the circuits that
represent a 2·bit wide slice through the
data processing section of a digital com·
puter. To construct a complete central
processor for a given word width N, it
is simply necessary to connect an array
of N/2 CPE's together. When wired
together in such an array, a set of CPE's
provide the following capabilities:
2's complement arithmetic
Logical AND, OR, NOT and
exclusive·OR
Incrementing and decrementing
Shifting left or right
Bit testing and zero detection
Carry look·ahead generation
Multiple data and address busses

High Performance - 100 ns Cycle Time

3002
CENTRAL
PROCESSING
ELEMENT

PACKAGE CONFIGURATION

TTL and DTL Compatible
N·Bit Word Expandable Multi·Bus
Organization
3 I nput Data Busses
2 Three·State Fully Buffered Output
Data Busses

Ko

3

11 General Purpose Registers

K,
X
y

Full Function Accumulator
Independent Memory Address Register
Cascade Outputs for Full Carry
Look·Ahead
Versatile Functional Capability
8 Function Groups
Over 40 Useful Functions
Zero Detect and Bit Test
Single Clock
28 Pin DIP

2·15

vee

10

I,
26

F2
F,

4

25

Fo

5

24

F3
ED

6

co

7

RO

8

LI

9

CI

10

19

EA

11

18

Do
CLK

A,

12

17

F.

Ao

13

16

Fs

GND

14

15

F6

INTEL@
3002

Mo
M,
0,

3002
PIN DESCRIPTION
PIN

SYMBOL

1,2

NAME AND FUNCTION
External Bus Inputs

Active lOW

The external bus inputs provide a separate input port for external input
devices.

3,4

Active LOW

Mask Bus Inputs
The mask bus inputs provide a separate input port for the microprogram
memory, to allow mask or constant entry.

5,6

X,Y

Standard Carry Look-Ahead Cascade Outputs
The cascade outputs allow high speed arithmetic operations to be
performed when they are used in conjunction with the INTEL 3003
Look-Ahead Carry Generator.

7

CO

Ripple Carry Output
The ripple carry output is only disabled during shift right operations.

Active LOW
Th ree-state

B

RO

Sh ift Right Output
The shift right output is only enabled during shift right operations.

Active LOW
Three-state

9

LI

Shift Right Input

Active LOW

10

CI

Carry Input

Active LOW

11

EA

Memory Address Enable Input
When in the LOW state, the memory address enable input enables the
memory address outputs (AO-A1)'

Active LOW

12-13

Ao-A1

Memory Address Bus Outputs
The memory address bus outputs are the buffered outputs of the
memory address register (MAR).

Active LOW
Th ree-state

14

GNO

Ground

15-17,
24-27,

Fo-F6

Micro-Function Bus Inputs
The micro-function bus inputs control ALU function and register
selection.

18

ClK

Clock Input

19-20

00-0 1

Memory Data Bus Outputs
The memory data bus outputs are the buffered outputs of the full
function accumulator register (AC).

Active LOW
Three-state

21-22

Mo-M1

Memory Data Bus Inputs
The memory data bus inputs provide a separate input port for
memory data.

Active LOW

23

ED

Memory Data Enable Input
When in the LOW state, the memory data enable input enables the
memory data outputs (00-01)

Active LOW

28

Vee

+5 Volt Supply

NOTE:
1. Active HIGH, unless otherwise specified.

2-16

3002
LOGICAL DESCRIPTION
The CPE provides the arithmetic, logic
and register functions of a 2·bit wide
slice through a microprogrammed central
processor. Data from external sources
such as main memory, is brought into
the CPE on one of the three separate in·
put busses. Data being sent out of the
CPE to external devices is carried on
either of the two output busses. Within
the CPE, data is stored in one of eleven
scratch pad registers or in the accumula·
tor. Data from the input busses, the
registers, or the accumulator is available
to the arithmetic/logic section (ALS)
under the control of two internal multi·
plexers. Additional inputs and outputs
are included for carry propagation,
shifting, and micro·function selection.
The complete logical organization of the
CPE is shown below.
MICRO·FUNCTION BUS AND
DECODER
The seven micro·function bus input
lines of the CPE, designated Fa-Fa,
are decoded internally to select the
ALS function, generate the scratch pad
address, and control the A and B
multiplexers.
M·BUS AND I·BUS INPUTS
The M·bus inputs are arranged to bring
data from an external main memory
into the CPE. Data on the M·bus is
multiplexed internally for input to
the ALS.
The I·bus inputs are arranged to bring
data from an external I/O system into
the CPE. Data on the I·bus is also mul·
tiplexed internally, although indepen·
dently of the M·bus, for input to the
ALS Separation of the two busses per·
mits a relatively lightly loaded memory
bus even though a large number of I/O
devices are connected to the I·bus.
Alternatively, the I·bus may be wired
to perform a multiple bit shift (e.g., a
byte exchange) by connecting it to one
of the output busses. In this case, I/O
device data is gated externally onto the
M·bus.
SCRATCH PAD
The scratchpad contains eleven registers
designated Ra through Rg and T. The
output of the scratch pad is multiplexed
interl'lally for input to ALS. The ALS
output is returned for input into the
scratch pad.
ACCUMULATOR AND D·BUS
An independent register called the
accumulator (AC) is available for storing
the result of an ALS operation. The
output of the accumulator is multi·
plexed internally for input back to the

ALS and is also available via a three·
state output buffer on the D·bus
outputs. Conventional usage of the
D·bus is for data being sent to the
external main memory or to external
I/O devices.
A AND B MULTIPLEXERS
The A and B multiplexers select the two
inputs to the ALS specified on the
micro·function bus. Inputs to the A·
multiplexer include the M·bus, the
scratchpad, and the accumulator. The
B·multiplexer selects either the I·bus,
the accumulator, or the K·bus. The
selected B·multiplexer input is always.
logically ANDed with the data on the
K·bus (see below) to provide a flexible
masking and bit testing capability.
ALS AND K-BUS
The A LS is capable of a variety of
arithmetic and logic operations, in·
cluding 2's complement addition, in·
crementing, and decrementing, plus
logical AND, inclusive·OR, exclusive·
NOR, and logical complement. The
result of an ALS operation may be
stored in the accumulator or one of the
scratchpad registers. Separate left input
and right output lines, designated LI
and RO, are available for use in right
shift operations. Carry input and carry
output lines, designated CI and CO are
provided for normal ripple carry propaga·

tion. CO and RO data are brought out via
two alternately enabled tri·state buffers.
In addition, standard look ahead carry
outputs, designated X and Y, are available
for full carry look ahead across any word
length.
The ability of the K·bus to mask inputs
to the ALS greatly increases the versa·
tility of the CPE. During non·arithmetic
operations in which carry propagation
has no meaning, the carry circuits are
used to perform a word·wise inclusive·
OR of the bits, masked by the K·bus,
from the register or bus selected by the
function decoder. Thus, the CPE pro·
vides a flexible bit testing capability.
The K·bus is also used during arithmetic
operations to mask portions of the field
being operated upon. An additionalfunction of the K-bus is that of supply·
ing constants to the CPE from the
microprogram.
MEMORY ADDRESS REGISTER
ANDA·BUS
A separate ALS output is also avail·
able to the memory address register
(MAR) and to the A·bus via a three·
state output buffer. Conventional usage
of the MAR and A·bus is for sending ad·
dresses to an external main memory.
The MAR and A·bus may also be used
to select an external device when
executing I/O operations.

MAIN MEMORY
ADDRESS
A,

D,

..

D,

ED ENABLE

ENABLE EA
ADDRESS

LOOK AHEAD

DATA

CI CARRY IN

{X

-+------l
CARRY OUT co --

..:s"'

&0

~

r----

i..

,

E

26:::-

40

~K

&.0

Vee (VOLTS)

Vee (VOLTSI

PROPAGATION DELAY - CLOCK TO "A" AND "0"
DATA OUTPUT VS.
AND TEMPERATURE

PROPAGATION DELAY - CLOCK TO
"A" AND "0" DATA OUTPUT VS. LOAD CAPACITANCE

"-CC:

10

1Or--------r------~--------r_------~

!

5
~

UDY

PROPAGATION DELAY FROM FUNCTION INPUTS TO
CASCADE OUTPUTS VS. Vee AND TEMPE_R!'TURE

CARRY IN SET UP TIME vs. Vee AND TEMPERATURE

I

&.2&V

vee (VOLTS)

OUTPUT VOLTAGE

I

5 &0

1Or-------;-------~--------+_------~

~

~

~

!

I,

40 1----+-::;_.....

IE,

:P

:P
Vee (VOLTSI

LOAD CAPAC'T ANCE (pFI

2-26

3002
TYPICAL CONRGURATIONS
MEMORY ADDRESS BUS
(ZH L1NESI
DATA BUS TO MEMORY
(2N llNESI

LAD

'--v' F.-F. ClK

l+-

3002

CARRY FROM
3001

i-

CI

CO
II

3002
RO

--::>F o-F3
I

CARRY TO 3001
MICROPROGRAM
CONSTANTIMASK
INPUT BUS
(ZH llNESI

1,

M K

""""

-

r--

~

r-------.-

ir>
"rt=

'---

r-

1-

I

.J

+
+

- - - - l l - I ' - - - - - , DATA BUS FROM
MEMORY

- - - - l l - - - - - - ' (2N llNESI
EXTERNAL DATA BUS
(2N L1NESI

Rippltl-Carry Confi.,ration

IN 3002 CPE's)

+5V

EC n +8

ECn +8

CARRY
FROM
3001

CARRY
TO
3001

+-~------------------------------------------------------------------------------~

Carry Look-Aha. Confi.,retion
With Ripple Through tho Left Slice
(32 Bit Array)

2-27

3002
APPENDIX A MICRO-FUNCTION SUMMARY
F·GROUP

R·GROUP

MICRO·FUNCTION
Rn + (AC A K) + CI ... Rn , AC

o

II

M + (AC A K) + CI'" AT

III

ATL A (lL A Kd'" RO
II V [(IH A KH) A ATHl "'ATH
[AhA (lLA Kdl V [ATHV(lH A KH)l"'Ah
K V Rn "'MAR

Rn + K + CI ... Rn

II

K V M "'MAR

M+K+CI"'AT

III

(AT V K) + (AT A K)+CI"'AT
(AC A K) -1 + CI ... Rn

2

II

(AC A K) -1 + CI'" AT

III

(I A K) -1 + CI'" AT

II

M + (AC A K) + CI ... AT

III

AT + (I A K) + CI ... AT
CI V (R n A AC A K) ... CO

Rn A (AC A K) ... Rn

II

CI V (M A AC /\ K) ... CO

M A (AC A K)'" AT

III

CI V (AT A I A K)->CO

AT A (I A K)'" AT

1

(see Note 1)

Rn + (AC ,\ K) + CI ... Rn

3

4

5

6

7

CI V (R n A K)'" CO

K A Rn ... Rn

II

CI V (M A K) ... CO

K AM'" AT

III

CI V (AT A K)'" CO

K A AT'" AT

CI V (AC A K) ... CO

Rn V (AC A K)'" Rn

II

CI V (AC A K) ... CO

MV(ACAK)"'AT

III

CI V (I A K) ... CO

AT V (I A K)

CI V (Rn A AC A K) ... CO

Rn iii (AC A K) ... Rn

CI V (M A AC A K) ... CO

M iii (AC /\ K)'" AT

III

CI V (AT A I A K) ... CO

AT iii (I A K)'" AT

1. 2'5 complement arithmetic adds 111 ... 11 to perform subtraction of 000 ... 01.
2. Rn includes T and AC as source and destination registers in R-group 1 micro-functions.
3. Standard arithmetic carry output values are generated in F-group 0, 1, 2 and 3 instructions.

SYMBOL

MEANING

I, K,M
CI, II
CO, RO
Rn
AC
AT
MAR
L, H

Data on the I, K, and M busses, respectively
Data on the carry input and left input, respectively
Data on the carry output and right output, respectively
Contents of register n including T and AC (R-Group I)
Contents of the accumulator
Contents of AC or T, as specified
Contents of the memory address register
As subscripts, designate low and high order bit, respectively
2's complement addition
2's complement subtraction
Logical AND
Logical OR
Exclusive-NOR
Deposit into

/\
V

(ji

AT

II

NOTES:

+

-~

2-28

3002
APPENDIX B ALL-ZERO AND ALL-ONE K-BUS MICRO-FUNCTIONS
K·BUS

=00

MICRO·FUNCTION

MNEMONIC

K·BUS

= 11

MICRO·FUNCTION

MNEMONIC

Rn + CI .... Rn. AC

ILR

AC + Rn + CI .... Rn. AC

ALR

M + CI .... AT

ACM

M + AC + CI .... AT

AMA

SRA

(See Appendix AI

LMI

11 .... MAR

Rn - 1 + CI-- Rn
M - 1 + CI .... AT

AT L .... RO

ATH .... ATL

Rn .... MAR

Rn + CI .... Rn

M .... MAR

M+CI-+AT

CI-1--AT

DSM

LMM

11 .... MAR

CIA

AT-1 + CI->AT

See Note 1

CSR

AC - 1 + CI-> Rn

See Note 1

SDR

See Notes 1,4

CSA

AC -1 + CI'" AT

See Notes 1.4

SDA

AT+ CI .... AT
CI-1 .... Rn

LI .... ATH

(See CSA above)
INR

Rn + CI -- Rn
(See ACM above)
AT + CI .... AT

LDM
DCA

1- 1 + CI-- AT

LDI

AC + Rn + CI -- Rn

ADR

(See AMA above)
INA

I+AT+CI->AT

AlA

CI .... CO

0 .... Rn

CLR

CI v (R n II AC) -> CO

Rn II AC -> Rn

ANR

CI->CO

0"" AT

CLA

Cl.v (M II ACI ... CO

MIIAC""AT

ANM

(See CLA above)

CI v (AT II I)'" CO

AT II I'" AT

ANI

(See CLR above)

CI v Rn'" CO

Rn'" Rn

TZR

(See C LA above)

CI v M "'CO

M"'AT

LTM

(See C LA above I

CI v AT'" CO

AT -+AT

TZA

CI"'CO

Rn'" Rn

NOP

CI v AC"'CO

Rn v AC'" Rn

ORR

CI"'CO

M""AT

LMF

CI v AC"'CO

M v AC"'AT

ORM

CI v I'" CO

I v AT'" AT

ORI

(See NOP above)
CI--CO

R;; .... Rn

CMR

CI v (R n

CI""CO

M"'AT

LCM

Clv (M

CI""CO

AT"" AT

CMA

Clv (AT

Rn iii AC'" Rn

XNR

AC)"'CO

Miii AC"'AT

XNM

I)--CO

I iii AT--AT

XNI

AC)"'CO

4. The more general operations. CSR and SDR. should be used in place of the CSA and SDA operations. respectively.

2·29

3002
APPENDIX C
FUNCTION
GROUP

0
1
2
3
4
5
6
7

REGISTER
GROUP

FUNCTION AND REGISTER GROUP FORMATS

F6

5

4

0
0
0
0

0
0

0
1
0
1
0
1
0
1

1
0
0
1
1

REGISTER

RO
R,
R2
R3
R4
RS
R6
R7
RS
Rg

F3

2

0
0
0
0
0
0
0
0
1

0
0
0
0

1
0
0
1
1

T

AC
II

III

T

0
0

AC
T

0

0
0
1
0
0
1
0
0
0
0

0
1
0
1
0
1
0
1
0
1
0
1
0

0
1

AC

2-30

SCHOTTKY
BIPOLAR LSI
MICROCOMPUTER
SET

The INTEL (!) 3003 Look·Ahead Carry
Generator (LCG) is a high speed circuit
capable of anticipating a carry across a
full 16-bit 3002 Central Processing
Array. When used with a larger 3002
CP Array multiple 3003 carry generators
provide high speed carry look·ahead
capability for any word length.
The LCG accepts eight pairs of active
high cascade inputs (X, V) and an active
low carry input and generates active
10\'11 carries for up to eight groups of
binary adders.

High Performance - 10 ns typicel
propagation dalay
Compatible with INTEL 3001 MCU
and 3002CPE
DTL and TTL compatible

3003
LOOK-AHEAD
CARRY
GENERATOR

PACKAGE CONFIGURATION

Y7

Vee

x7

YI

ECn+ 8

28

Full look-ahead across 8 adders

Xs

Xl
Y2

X.

Low voltage diode input clamp

INTEL-

Ys

3003

28-pin DIP

Cn+S

X,

X3

"0

Y3

11

Yo

,.

en +3

en

Cn+"

en +2
GND

2-31

Cn+.

Y,

Y.

Expandable

Xs
Cn+ 7

Cn+1

'3

Cn+ 1

3003
LOGIC DIAGRAM

EC n+ 8

SYMBOL

1,7,8,11
18,21,23
27

Y O-Y7

2,5,6,10
19,20,24
26
17

X7

NAME AND
FUNCTION

TYPE
Active
HIGH

XO-X7

Standard carry
look-ahead
inputs

Active
HIGH

Cn

Carry input

Active
LOW

Cn+8

3

ECn+8

Cn+l-

Carry outputs

Cn+8 carry
output enable

}--

:;;;;

Standard carry
look-ahead
inputs

4,9,12
13,15,16

R==
=;= ~

V7

PIN DESCRIPTION
PIN

.........

Active
LOW
Active
HIGH

~

Vs

Xs
Vo

en+8

en+7
en+8

Xs
v.
X.

Cn+5

V3

28
14

Vee

+5 volt supply

GND

Ground

Cn+~

X3
V2

Cn+3

X2

v,

en+ 2

X,
Vo
Xo
Cn

....
to'"

-rt=r>-

3003 LOGIC EQUATIONS
The 3003 Look-Ahead Generator is implemented in a compatible form for direct connection to the 3001 MCU and 3002 CPE.
Logic equations for the 3003 are:

Cn +.7 = Y SXS + Y SY 5 X 5 + Y SY 5Y 4X 4 + Y SY 5 Y 4Y 3X 3 + Y SY 5Y 4Y 3Y 2 X 2 + Y6Y5Y4Y3Y2Y1Xl + Y SY 5Y 4Y3Y 2Y lYOXO
+YSY5Y4Y3Y2Y1YOCn
Cn + 8 = High Impedance State when EC n + 8 Low
Cn + 8 = Y 7 X 7 + Y 7Y SX S + Y 7Y SY 5 X 5 + Y7YSY5Y4X4 + Y 7 Y SY 5 Y 4Y 3X3 + Y 7Y SY 5 Y 4Y 3Y 2 X 2 + Y7YSY5Y4Y3Y2Y1Xl
+ Y 7Y SY 5 Y 4Y 3Y 2Y l YOXO + Y 7 Y SY 5 Y 4Y3Y2Y 1YOGn when EC n + 8 high

2-32

en+ 1

3003
D.C. AND OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias

.

Storage Temperature

-65°C to +160°C
-0.5V to +7V

All Output and Supply Voltages.

-1.0V to +5.5V

All Input Voltages
Output Current

. o°C to 70°C

100mA

.

·COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is
not implied.

T A = O°C to +70°C
SYMBOL

VCC = 5.0V ±5%
PARAMETER

Vc

Input Clamp Voltage (All
Input Pins)

'F

Input Load Current:
X6,X7Cn,ECn + 8
Y7,XO,X5,
YO'Y6
Input Leakage Current:
Cn and EC n + 8
All Other Inputs

'R

V,L

Input Low Voltage

V,H

Input High Voltage

ICC

Power Supply Current

VOL

Output Low Voltage (All
Output Pins)

VOH

Output High Voltage (All
Output Pins)

lOS

Short Circuit Output Current
(All Output Pins)

'O(off)

MIN.

TYP.(1)

MAX.

-O.B

-1.0

-0.07
-0.200
-0.6

-0.25
-0.500
-1.5
40
100
0.8

2.0
80

0.35

2.4

-15

130

0.45

3

-40

Off·State Output Current
(C n + 8)

UNIT

CONDITIONS

V

'C = -5 mA

mA
mA
mA

VF = 0.45V

jJ.A
jJ.A

VR = 5.25V

V

VCC = 5.0V

V

VCC = 5.0V

mA

All Y and EC n + 8 high,
All X and Cn low

V

10L = 4 mA

V

10H = -1 mA

-65

mA

VCC = 5V

-100
+100

jJ.A
jJ.A

Vo = 0.45V
Vo = 5.25V

NOTE:
Typical values are for TA = 25°C and nominal supply voltage.
(11

A.C. CHARACTERISTICS
TA = O°C to 70°C, VCC = +5V ± 5%
SYMBOL

MIN.

PARAMETER

3

TYP.(1)

MAX.

UNIT

10

20

ns

txc

X, Y to Outputs

tcc

Carry I n to Outputs

13

30

ns

tEN

Enable Time, Cn + 8

20

40

ns

NOTE:
Typical values are for T A = 25°C and nominal supply voltage.
(11

2-33

3003
D.C. AND OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias

-55·C to +125·C

Storage Temperature

-65·C to +160·C

All Output and Supply Voltages.

-0.5V to +7V

All I nput Voltages
Output Current

-1.0V to +5.5V

.

100mA

·COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is
not implied.

TA = -55·Cto +125·C, Vee = 5.0V ±10%.
SYMBOL

PARAMETER

MIN.

Vc

Input Clamp Voltage (All
Input Pins)

IF

Input Load Current:
X6,X7,Cn,ECn+8
Y 7,XO,X5,
YO'Y6
Input Leakage Current:
and EC n + 8
All Other Inputs

IR

TYP.(I)

MAX.

-0.8

-1.2

-0.07
-0.200
-0.6

-0.25
-0.500
-1.5

en

VIL

Input low Voltage

VIH

Input High Voltage

ICC

Power Supply Current

VOL

Output Low Voltage (All
Output Pins)

VOH

Output High Voltage (All
Output Pins)

lOS

Short Circuit Output Current
(All Output Pins)

10(off)

40
100
0.8
2.1
80

0.35

2.4

-15

130

0.45

3

-40

Off·State Output Current
(C n + 8)

CONDITIONS

UNIT
V

IC = -5 mA

mA
mA
mA

VF = 0.45V

IJA
IJA

VCC = 5.25V, VR = 5.5V

V

VCC= 5.0V

V

VCC = 5.0V

mA

All Y and ECn + 8 high,
All X and Cn low

V

10l

=4 mA

V

10H

=-1

-65

mA

-100
+100

IJA
IJA

VCC

mA

=5V

VO=0.45V
VO= 5.5V

NOTE:
Typical values are for T A = 25°C and nominal supply voltage.

(1)

A.C. CHARACTERISTICS
TA

=-55·C to +125·C, Vee =+5.0V ±10%

SYMBOL

MIN.

PARAMETER

3

TYP.(I)

MAX.

UNIT

10

25

ns

txc

X. Y to Outputs

tcc

Carry I n to Outputs

13

40

ns

Enable Time. Cn + 8

20

50

ns

NOTE:
(11

Typical values are for TA

= 25°C and

nominal supply voltage.

2-34

3003
WAVEFORMS

G . =*.....---

X,V INPUTS

________________
Cn INPUT

~*~I~.~---------~----------~-e------~----.--!

____________

NOTE: ALTERNATE TeST LOAD:

-------

Vee

----.-;~-tEN1-r--..,~,J::.::"-1-j
____~
T

Cn.a OUT

VOH

I

Cn .8 OUTPUT

.

_

__________ J

tt

~

~

'0'
,.

VOL

O.SV

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

Input Capacitance

All inputs

12

20

pF

Output Capacitance

Cn

+8

7

12

pF

NOTE:
(21 This parameter is periodically sampled and is not 100% tested. C.ondition 01 measurement is 1 = 1 MHz, VBIAS
VCC = S.OV and TA = 25°C.

= S.OV,

TEST LOAD CIRCUIT:

TEST CONDITIONS:

Input pulse amplitude of 2.5V.
Input rise and fall times of 5 ns between 1 and 2 volts.
Output loading is 5 mA and 30 pF.
Speed measurements are made at 1.5 volt levels.

Vee

"
OUT

o--~---+

=3O.F

2-35

2.

3003
TYPICAL A.C. AND D.C. CHARACTERISTICS
OUTPUT CURRENT vs. OUTPUT LOW VOLTAGE

ICC VS. TEMPERATURE
80

8Or_----,-----~------r_--~

L..L

8O~-----+------~------~~~~

!Jj

-

70

m~----~----.,,~------+-----~

~75

-50

-26

25

50

75

100

°0~--~~~-----7------~----~

125

OUTPUT (V)

TEMPERATURE (OCI

x, Y TO OUTPUTS VI. Vee AND TEMPERATURE

OUTPUT CURRENT VS.OUTPUT.HIGH VOLTAGE

30
t

-.
!.

..
z
a:
a:

::l
U

~

!

-'0

m

~
~

.

-,.

::l

0

-m

x

0

---

_55°C

/ / O"c}5'C
//

~

:e>

'0

'\).:c
125'1

-26

-30

....

o

0

Vee (VOLTS)

x, Y TO OUTPUT DELAY VS. LOAD CAPACITANCE

..

x, Y TO OUTPUTS VS. VCC AND TEMPERATURE
30

Vee

J

ls.ov

TA " 26°C

30

>

~
Q

!;

I!:
::l

m

0

:e>

x '0

~

0..

!

-

.

txc_+

~

"- "-

0

x

,

25'\ '"

~

:e>

1-"

70'C

m

~

~
,-+
I--"
...-:::
p-- ~

'00

5."

5.25

5.00

4.75

OUTPUT IV)

!

xc ._

'0

~

\'C

-5T

260

....

o

300

LOAD CAPACITANCE (pFI

4.75

5.00
Vee (VOL TSI

2·36

5.26

....

3003
TYPICAL CONFIGURATIONS
The 3003 LCG can be directly tied to the 3001 MCU and a 3002 CP array of any word length. The following figures represent
typical configurations of 16· and 32-bit CP arrays. Figures 1 and 2 illustrate use of the 3003 in a system where the carry output
(CO) to the 3001 MCU is rippled through the high order CPE slice. Figure 3 illustrates use of the 3003 in a system where tri·state
output Cn+8 is connected directly to the flag input on the 3001 MCU. Cn+8 is disabled during shift right by decoding that instruction
externally. thus multiplexing Cn+8 with the shift right (RO) output of the low order CPE slice.

Ee n + 8

CARRY
FROM

3001

TO
+-~--________________________________________~
CARRY
3001

Figure 1. Carry Look-Ahead Configuration with Ripple through the Left Slice U6-Bit Array)

...
...

F;"

-5V

F3

F,
F,

Ec" +8

CARRY

FROM

M3IlOl

~~RRV~-+

______________________________________________________________________________________

M3IlOl

Figure 2. Carry Look-Ahead Configuration with No Carry Ripple through the Left Slice (32-Bit Array)

2·37

~

SCHOTTKY
BIPOLAR LSI
MICROCOMPUTER
SET
The INTE~3212 Multi-Mode Latch
Buffer is a versatile 8-bit latch with
three-state output buffers and built-in
device select logic. It also contains an
independent service request flip-flop
for the generation of central processor
interrupts. Because of its multi-mode
capabilities, one or more 3212's can
be used to implement many types of
interface and support systems for Series
3000 computing elements including:

High Performance - 50 ns Write Cycle
Time
Low Input Load Current - 250 JJ.A
Maximum
Three-State Fully Buffered Outputs

PACKAGE CONFIGURATION

24

•

OSI

23

MO

22

011

High Output Drive Capability
Independent Service Request FlipFlop
Asynchronous Data Latch Clear

001

4

21
INTEL@
3212

01 2

IS

01 3

17
16

01 4

Gated data buffers

004
5TB

Multiplexers

GNO

20
19

002

003

24 Pin DIP

Simple data latches

3212
MULTI-MODE
LA TCH BUFFER

10

15

11

14

12

13

Bi-directional bus drivers

Vcc
INT

DiS
DOS
01 7
007
01 6
006
01 5
005
CLR

OS2

Interrupting input/output ports

CQNTROL " 0
MEMORV 110

M'fMOR'"
"');l-:''''''~S

aus

MICRO
PROGRAM
MEMORV

INSTRUCTION BUS

't)Ptt..~ l!trr.. ~V'..o""

""'t'W\o""

Figure 1_ Block Diagram of a Typicel System

2·39

u ...~ po., ~"()V\
't)'C........ ,c'C..'S.

3212
PIN DESCRIPTION
PIN

2

SYMBOL

NAME AND FUNCTION

OS1

Device Select Input 1

MO

Mode Input

active LOW

When MO is high (output mode) the output buffers are enabled and the
write signal to the data latches is obtained from the device select logic.
When MO is low (input mode) the output buffer state is determined bV
the device select logic and the write signal is obtained from the strobe
(STB) input.

3,5,7,9,
16, lB, 20,
22

011- 01 S

4,6, B,10,
15,17,19,
21

001- 00 S

11

STB

Data Inputs
The data inputs are connected to the O-inputs of the data latches.
three-state

Data Outputs
The data outputs are the buffered outputs of the eight data latches.
Strobe Input
When MO is in the LOW state, the STB input provides the clock input
to the data latch.

12

GNO

13

Ground
Device Select Input 2
When OS1 is low and OS2 is high, the device is selected.

14

CLR

23

INT

Clear

active LOW

Interrupt Output

active LOW

The interrupt output will be active LOW (interrupting state) when
either the service request flip-flop is low or the device is selected.

NOTE:
(1) Active HIGH, unless otherwise specified.

2-40

3212
FUNCTIONAL DESCRIPTION
The 3212 contains eight D·type data
latches, eight three·state output buf·
fers, a separate D·type service request
flip·flop, and a flexible device select!
mode control section.

DATA LATCHES
The Q·output of each data latch will
follow the data on its corresponding
date input line (DI,-Dls) while its
clock input is high. Data wi II be
latched when the internal write line WR
is brought low. The output of each
data latch is connected to a three·state,
non·inverting output buffer. The in·
ternal enable line EN is bussed to each
buffer. When the EN is high, the buf·
fers are enabled and the data in each
latch is available on its corresponding
data output line (DOo-DO S )'

The Q output of the SR flip·flop is
logically ORed with the output of
device select logic and then inverted
to provide the interrupt output INT.
The 3212 is considered to be in the in·
terrupting state when the INT output
is low. This allows direct connection
to the active LOW priority request in·
puts of the INTEL3214 Interrupt
Control Unit.

When operated in the input mode (i.e.,
MD low) the strobe input STB is used
to synchronously write data into the
data latch and place the SR flip·flop in
the interrupting (reset) state. The in·
terrupt is removed by the central pro·
cessor when the interrupting 3212 is
selected.

1---------------1
I
I
I
I
I
I
I
I

STB::+===::t::;:===!f:>
~

D~
05 2

I
I
INT

DEVICE SELECT LOGIC
Two input lines DS, and D'S2 are pro·
vided for device selection. When DS,
is low and DS2 is high, the 3212 is
selected.

0"

I-++--r>-~DOI

012

1-4--1--1'">4- 002

MODE CONTROL SECTION
The 3212 may be operated in two
modes. When the mode input line MD
is low, the device is in the input mode.
In this mode, the output buffers are
enabled whenever the 3212 is selected;
the internal WR line follows the STB
input line.
When MD is high, the device is in the
output mode and, as a result, the out·
put buffers are enabled. In this mode,
the write signal for the data latch is
obtained from the device select logic.

01 3

01.

DiS

01.

01,

H-+--f>-"':"'-oo,

01,

1-4--1'">........ DO,

SERVICE REQUEST FLIP·FLOP
AND STROBE
The service request flip-flop SR is used
to generate and control central proces·
sor interrupt signals. For system reset,
the SR flip·flop is placed in the non·
interrupting state (i.e., SR is set) by
bringing the CLR line low. This simul·
taneously clears (resets) the 8·bit data
latch.

CLR
L

M3212 Logic Diagram

2·41

3212
D.C. AND OPERATING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .O°C to 70°C
Storage Temperature . . . . . . .

.. _65°C to +160°C

All Output and Supply Voltages.

. ... -0.5V to +7V

All Input Voltages

. -1.0V to +5.5V

Output Currents

. . . . . 100mA

·COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

T A .. aOc to +75°C
Symbol

Vee

=+5V ±5%

Parameter

Typ.

Min.

Max.

Conditions

Unit

IF

Input Load Current
STB, 052, CLR, 01,-0IS Inputs

-.25

mA

VF

= .45V

IF

Input Load Current
MO Input

-.75

mA

VF

.45V

IF

I nput Load Current
OS, Input

-1.0

mA

VF

.45V

IR

Input Leakage Current
STB, OS,CLR, 01,-0ISlnputs

10

IlA

VR

5.25V

IR

I nput Leakage Current
MO Input

30

IlA

VR

5.25V

IR

I nput Leakage Current
05, Input

40

IlA

VR

5.25V

Ve

Input Forward Voltage Clamp

-1

V

Ie

VIL

Input "Low" Voltage

VIH

Input "High" Voltage

VOL

Output "Low" Voltage

VO H

Output "High" Voltage

Ise

Short Circuit Output Current

1101

Output Leakage Current
High I mpedance State

lee

Power Supply Current

.85

-5 mA

V
V

2.0

V

10L

15mA

V

10H

-1 mA

-75

mA

Vee

= 5.0V

20

IlA

Vo

= .45V/5.25V

130

mA

.45
4.0

3.65
-15

90

2042

3212
A.C. CHARACTERISTICS
Symbol

TA -

ooc to 75°C, VCC = +5.0V ± 5%

Paramatar

Min.

Max.

Typ.

Unit
ns

tpw

Pulse Width

tpD

Data To Output Delay

30

ns

twE

Write Enable To Output Delay

40

ns

tSET

Data Setup Time

15

ns

tH

Data Hold Time

20

ns

tR

Reset To Output Delay

40

ns

ts

Set To Output Delay

30

ns

tE

Output Enable Time

45

ns

tc

Clear To Output Display

45

ns

25

CL = 30 pf

TEST LOAD CIRCUIT:

TEST CONDITIONS:
Input pulse amplitude of 2.5 volts.
Input rise and fall times of 5 ns between 1 volt and 2 volts.
Output load of 15 mA and 30 pF.
Speed measurements are taken at the 1.5 volt level.

Vee
300n

our 0--_--+
30pF

CAPACITANCE(1I
Symbol

LIMITS

Test
Min.

Typ.

Max.

Units

CIN

OS,. MD Input Capacitance

9

12

pf

CIN

DS2, CLR, STB, 0I 1-DI S
Input Capacitance

5

9

pf

COUT

D01-DOS Output Capacitance

B

12

pf

NOTE:
11) This parameter is periodicallv sampled and is not 100% tested. Condition 01 measurement is 1 = 1 MHz. VSIAS = 2.SV. VCC
TA = 25°C.

2-43

=

SV and

3212
D.C. AND OPERATING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . .
. .. -0.5V to +7V

All Output and Supply Voltages.
All Input Voltages

. -1.0V to +5.5V

Output Currents

. . . . . 100 mA

·COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

TA

=_55°C to +125°C;

Symbol

Vee

=5.0V ±10%

Parameter

Typ.

Min.

Max.

Conditions

Unit

IF

I nput Load Current
STB, OS2, CLR, OI,-OIS Inputs

-.25

mA

VF = .45V

IF

Input Load Current
MO Input

-.75

mA

VF

.45V

IF

I nput Load Current
OS, Input

-1.0

mA

Vrf.

.45V

IR

I nput Leakage Current
STB, OS, CLR, OI,-OIS Inputs

10

f.l.A

VR

5.5V

IR

I nput Leakage Current
MO Input

30

f.l.A

VR

5.5V

IR

Input Leakage Current
OS, Input

40

f.l.A

VR

5.5V

Ve

Input Forward Voltage Clamp

V

Ie

-5 mA

V 1L

Input "Low" Voltage

VIH

Input "High" Voltage

VOL

Output "Low" Voltage

VO H

Output "High" Voltage

Ise

Short Circuit Output Current

1101

Output Leakage Current
High Impedance State

lee

Power Supply Current

1.2
.80

V
V

2.0

V

10L

= 10mA

V

10H

= .5mA

mA

Vee

= 5.0V

20

f.l.A

Va = .45V/5.5V

145

mA

.45
4.0

3.5
-15

-75

90

2-44

ArIL/~
A.C. CHARACTERISTICS
Symbol

TA = -55°C to +125°C. Vee = 5.0V ± 10%

Parametar

Typ.

Min.

Max.

Unit

40

tpw

Pulse Width

tpo

Data To Output Delay

30

ns

tWE

Write Enable To Output Delay

50

ns

tSET

Data Setup Time

20

ns

tH

Data Hold Time

30

ns

tR

Reset To Output Delay

55

ns

ts

Set To Output Delay

35

ns

tE

Output Enable Time

50

ns

tc

Clear To Output Display

55

ns

ns

TEST CONDITIONS:

CL

30 pf

TEST LOAD CIRCUIT:

Input pulse amplitude of 2.5 volts.
Input rise and fall times of 5 ns between 1 volt and 2 volts.
Output load of 15 mA and 30 pF.
Speed measurements are taken at the 1.5 volt level.

Vcc
300n

OUTo--_--t
30 pF

600n

CAPACITANCE I1 }
Symbol

LIMITS
Test
Min.

Typ.

Max.

Units

CIN

05 1• MD Input Capacitance

9

12

pf

CIN

DS2. CLR, STB, Oil-Dis
Input Capacitance

5

9

pf

COUT

DO I-DOS Output Capacitance

8

12

pf

NOTE:
111 This parameter is periodicallv sampled and is not 100% tested. Condition of measurement is f = 1 MHz. VSIAS = 2.SV. Vee = SV and
TA = 2Soe.

2-45

3212

3212
WAVEFORMS

,o5vX-------------y5v

DATA

- - - - - - - '

'o5Vl

STBodis,. DS2

'I'

I;=='PW

°

\'5V
'_W_E=j , __________ _
X'-'_o5V__________

I

~---------------

____________
I4
_-_
-

OUTPUT

'H ~'------

_______________ --'

OUTPUT

DO

,5VX- ------------- --Y'5V

DATA

- - - - - - - . . . / I--

STB ..

r

'SET

'H

'.I '----

'5V\'-_____________

OS, • 052

'PDo-j

!,------------

X'-:_5V________________

OUTPUT

_ _ _ _ _ _ _ _ _ __ - I

STB

_____-J~~'o_5V_____________________

-~l

NOTE: ALTERNATIVE TEST LOAD

-<

VCC'0K

OUT

~

_0 'R

CL

lK

2-46

3212
TYPICAL A.C. AND D.C. CHARACTERISTICS

vs.

INPUT CURRENT
Vee"

~~

~5.DV

-so
~ -100

~

OUTPUT CURRENT VS. OUTPUT "LOW" VOLTAGE
'00r------,-------,------,-------,

INPUT VOLTAGE

Vee" +5.0V
8O~----~------_+------~----~

~

c

I
TA .. ere

!

V TA • 2."C
VVTA ·'S"C

/'

>-

~ -150

il

i

!

~

60

>-

00

rr:
rr:
:>
u

~

-200

0

20
-250

-300

-3

.,

-,

-2

.2

°o~--~~~-----L------~------J

.3

INPUT VOLTAGE IV)

OUTPUT "LOW" VOLTAGE (VI

OUTPUT CURRENT vs.
OUTPUT "HIGH" VOLTAGE

DATA TO OUTPUT DELAY
VS. LOAD CAPACITANCE

so
Vee" +5.0V

Vee ,·~s.ov
TA .. 25G e

-s
00

C
!
>-

~

rr:
rr:

!

-'0

>

TA " 75°C

";;j

-,S

0

....
T...

:>

u
>-

:>
0
0

TA -O"C

-20

i>-

:>
0

30

~

-a"c

>-

20

"!<

-25

0

~-

'0

00

so

'00

DATA TO OUTPUT DELAY
vs. TEMPERATURE

0

30

~

25

z

20

>-

I

>-

;I

80

's
'0
-25

'00

TE_ER"TURE C·CI

2-47

-- .

I

0
0

.
...~
a:

.-- r--....
211

35

..

,;':"",""'"""

... ......

1
>
~

",,'

0

-211

300

Vee" +5.0V

20

0

250

00
Vee" +I.GV

,

-

WRITE ENABLE TO OUTPUT DELAY
VS. TEMPERATURE

22

2

'so

...

~

LOAD CAPACITANCE (pFI

OUTPUT "HIGH" VOLTAGE (VI

•
•

--

--::. ~ f.-\---;. ..........

I

~~

_-- ---

\-

........;:-i

1---~~~<' ......

.--

DS~< I--

I--

I

I
26

80

'00

3212
TYPICAL CONFIGURATIONS
GATED BUFFER (TRI·STATE)

BI·DIRECTIONAL BUS DRIVER

VCC---r-------.----;:~~_,

.I..

STB

INPUT
DATA
(250 "A)

STB

OUTPUT
DATA
(!5mAI
(3.65V MINI

;3212

L-__________

~

DATA
BUS

I.

CLR

'"

1
~

DATA BUS
CONTROL
(0: L - RI
(I: R - LI

GND
----------------'

,L

"
r-<

GATING {
CONTROL
(DS1.DS2)

;3212

CLR

--

G~D

L..-

STB

INTERRUPTING INPUT PORT
DATA
BUS

INPUT
STROBE

;3212

L

STB

CLR

L-...J
SYSTEM
INPUT

SYSTEM
RESET

t---DR

T~c~~~~ IE~W)
TO CPU
INTERRUPT INPUT

OUTPUT PORT (WITH HAND·SHAKING)
DATA
BUS
,....------ OUTPUT STROBE
STB

SYSTEM OUTPUT

SYSTEM RESET

SYSTEM
INTERRUPT

~
GND

1........::..:'--____-

PORT SELECTION
} (LATCH CONTROL)
(DS\.DS21

2-48

V....

DATA
BUS

The Intel"'3214 Interrupt Control Unit
(ICU) implements multi-level interrupt
capability for systems designed with
Series 3000 computing elements.
The ICU accepts an asynchronous interrupt strobe from the 3001 Microprogram Control Unit or a bit in
microprogram memory and generates
a synchronous interrupt acknowledge
and an interrupt vector which may be
directed to the MCU or CP Array to
uniquely identify the interrupt source.
The ICU is fully expandable in 8-level
increments and provides the following
system capabilities:

SCHOTTKY
BIPOLAR LSI
MICROCOMPUTER
SET

3214

High Performance - 80 ns Cycle Time

PACKAGE CONFIGURATION

INTERRUPT
CONTROL
UNIT

Compatible with Intel 3001 MCU and
3002 CPE
8-Bit Priority I nterrupt Request Latch
4·Bit Priority Status Latch
3-Bit Priority Encoder with Opan
Collector Outputs
DTL and TTL Compatible
8-Level Priority Comparator
Fully Expandable

.,••
.,

ECS

SGS

R.

IA

R,

ClK

R,

ISE

R,

At

R,

A,

R,

Vcc
R,

A,

R.

EtR

24-Pin DIP

GNo

Eight unique priority levels per ICU
Automatic Priority Determination
Programmable Status
N-Ievel expansion capability
Automatic interrupt vector generation

2-49

ENLG

"

"

ETLG

3214
PIN DESCRIPTION
PIN

NAME AND FUNCTION

SYMBOL

1-3

Current Status Inputs

Active LOW

The Current Status inputs carry the binary value modulo 8 of the current
priority level to the current status latch.

4

SGS

Status Group Select Input

Active LOW

The Status Group Select input informs the ICU that the current priority
level does belong to the group level assigned to the ICU.

5

IA

Interrupt Acknowledge
The Interrupt Acknowledge Output will only be active from the ICU
(multi·ICU system) which has received a priority request at a level
superior to the current status. It signals the controlled device (usually
the processor) and the other ICUs OR·tied on the Interrupt Acknowledge
line that an interrupt request has been recognized.

Active LOW
Open·Coliector
Output

The IA signal also sets the Interrupt Disable flip·flop (it overrides the
clear function of the ECS input).

6

CLK

Clock Input
The Clock input is used to synchronize the interrupt acknowledge with
the operation of the device which it controls.

7

ISE

Interrupt Strobe Enable Input
The Interrupt Strobe Enable input informs the ICU that it is authorized
to enter the interrupt mode.

8-10

Request Level Outputs
When valid, the Request Level outputs carry the binary value (modulo 8)
of the highest priority request present at the priority request inputs or
stored in the priority request latch. The request level outputs can become active only with the ICU which has received the highest priority
request with a level superior to the current status.

11

ELR

Enable Level Read Input

Active LOW
Open·Coliector

Active LOW

When active, the Enable Level Read input enables the Request Level
output buffers (Ao-A2)'

12

GND

13

ETLG

Ground
Enable This Level Group Input
The Enable This Level Group input allows a higher priority ICU in multiICU systems to inhibit interrupts within the next lower priority ICU
(and all the following ICUs).

14

ENLG

Enable Next Level Group Output
The Enable Next Level Group output allows the ICU to inhibit interrupts within the lower priority ICU in a multi-ICU system.

15-22

Priority Interrupt Request Inputs

Active LOW

The Priority Interrupt Request inputs are the inputs of the priority
Interrupt Request Latch, The lowest priority level interrupt request
signal is attached to Ro and the highest is attached to R 7 .

23

ECS

Enable Current Status Input
The Enable Current Status input controls the current status latch
and the clear function of the Interrupt Inhibit flip-flop.

24

Vee

+5 Volt Supply

NOTE:
(1) Active HIGH, unless otherwise noted.

Active LOW

3214
FUNCTIONAL AND LOGICAL DESCRIPTION
The ICU adds interrupt capability to
suitably microprogrammed processors
or controllers. One or more of these
units allows external signals called
interrupt requests to cause the pro·
cessor/controller to suspend execution
of the active process, save its status,
and initiate execution of a new task
as requested by the interrupt signal.
It is customary to strobe the ICU at
the end of each instruction execution.
At that time, if an interrupt request is
acknowledged by the ICU, the MCU is
forced to follow the interrupt micro·
program sequence.
Figure 1 shows the block diagram of
the ICU. Interrupt requests pass
through the interrupt request latch
and priority encoder to the magnitude
comparator. The output of the pri·
ority encoder is the binary equivalent
of the highest active priority request.
At the comparator, this value is com·
pared with the Current Status (cur·
rently active priority level) contained
in the current status latch. A request,
if acknowledged at interrupt strobe
time, will cause the interrupt flip·flop
to enter the "interrupt active" state
for one microinstruction cycle. This
action causes the interrupt acknowl·
edge (lA) signal to go low and sets the
interrupt disable flip·flop.

The IA signal constitutes the interrupt
command to the processor. It can
directly force entry into the interrupt
service routine as demonstrated in the
appendix. As part of this routine, the
microprogram normally reads the reo
questing level via the request level out·
put bus. This information which is
saved in the request latch can be en·
abled onto one of the processor input
data buses using the enable level read
input. Once the interrupt handler has
determined the requesting level, it
normally writes this level back into the
current status register of the ICU. This
action resets the interrupt disable flip·
flop and acts to block any further
request at this level or lower levels.
Entry into a macro level interrupt ser·
vice routine may be vectored using the
request level information to generate a
subroutine address which corresponds
to the level. Exit from such a macro·
program should normally restore the
prior status in the current status latch.
The Enable This Level Group (ETLG)
input and the Enable Next Level Group
(EN LG) output can be used in a daisy
chain fashion, as each ICU is capable
of inhibiting interrupts from all of the
following ICUs in a multiple ICU
configuration.

I

I

J

",
",
",
",
",
",
",

.,
.,

.,

An active request level (Ro-R7) is
greater than the current status
Bo-B2
The interrupt mode (lSE) is active
ETLG is enabled
The interrupt disable flip·flop is reset
When active, the IA signal asynchron·
ously sets the disable flip·flop and
holds the requests in the request latch
until new current status information
(BO-B2, SGS) is enabled (ECS) into
the current status latch. The disable
flip·flop is reset at the completion of
this load operation.
During this process, ENLG will be en·
abled only if the following conditions
are met:
ETLG is enabled
The current status (SGS) does not
belong to this level group
There is no active request at this level
The request level outputs Ao-A2 and
the IA output are open·collector to
permit bussing of these lines in multi·
ICU configuration.

.......-

El"

ETlG

",

The interrupt acknowledge flip-flop
is set to the active LOW state on the
rising edge of the clock when the
following conditions are met:

1
I
I

I

-

REaUEST ACTIVITY

I

I

....r:-

:r-

INTERRUPT
REQUEST

::c.....

LATCH

•

I

PRIORITY

ENCODER

I
I

I
I
I

~ '--

I
CURRENT

STATUS

F=
I---

COMPARATOR

FD

LATCH

I

I
I

INT
ACK
FF

.........

'I'

'CS

I
I
I
I

-

I
I
I

I
I
I
I
I

I
I
I
I
I
I

r~
DIS

"

I

-.:.l........

I

I

IS'
CLK

At

I

L

___________________________________

Figure 1. 3214 Block Diagram.

2·51

A,

A,
ENlG

r--c.S.!......

SGS

I

~r;--;;

I

I

~~
PRIORITV

I

~

3214
D.C. AND OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
Ceramic. . . .
Plastic . . . .

. -65°C to +75°C
. . O°C to +75°C

Storage Temperature

_65°C to + 160°C

All Output and Supply Voltages.

.-0.5V to +7V

All Input Voltages

-1.0V to +5.5V
.

Output Currents .

. . 100mA

·COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

TA

= oOe

SYMBOL

to +75°C, Vcc

= 5.0V

±5%

PARAMETER

MIN

Vc

Input Clamp Voltage (all inputs)

IF

I nput Forward Current:

LIMITS
Typ(1)

MAX
-1.0

ETLG input
all other inputs

-.15

-.OS

CONDITIONS

UNIT
V

IC = -5 mA

-0.5
-0.25

mA
mA

VF = 0.45V

IR

Input Reverse Current:

ETLG input
all other inputs

80
40

iJ.A
iJ.A

VR = 5.25V

VIL

Input LOW Voltage:

all inputs

0.8

V

VCC = 5.0V

VIH

Input HIGH Voltage:

all inputs

V

VCC = 5.0V

ICC

Power Supply Current (2)

VOL

Output LOW Voltage:

all outputs

VOH

Output HIGH Voltage:

ENLG output

lOS

Short Circuit Output Current: ENLG output

ICEX

Output Leakage Current:

2.0

= 25°C and

130

mA

.3

.45

V

10L = 15 mA

V

10H = -1 mA

2.4

3.0

-20

-35

IA and
AO-A2 outputs

NOTES:
11)Typical values are for T A

90

nominal supply voltage.

12)80-82, SGS, ClK, R0-R4 grounded, ali other inputs and ali outputs open.

2·52

= 5.0V

-55

mA

VCC

100

iJ. A

VCEX = 5.25V

3214
A.C. CHARACTERISTICS
TA z DoC to +75°e. Vee - +5V ± 5%
SYMBOL

PARAMETER

MIN

liMITS
TYP(1)

MAX

UNIT

ttv

ClK Cycle Time

80

tpw

ClK, ECS, IA Pulse Width

25

15

ns

ns

Interrupt Flip-Flop Next State Determination:
tlSS

ISE Set-Up Time to ClK

16

12

ns

tlSH

ISE Hold Time After ClK

20

10

ns

tETCS 2

ETlG Set-Up Time to ClK

25

12

ns

tETCH 2

ETlG Hold Time After ClK

20

10

ns

tECCS 3

ECS Set-Up Time to ClK (to clear interrupt inhibit prior to ClK)

80

25

ns

tECCH 3

ECS Hold Time After ClK (to hold interrupt inhibit)

0

tECRS 3

ECS Set-Up Time to ClK (to enable new requests through the request latch)

3

110

ECS Hold Time After ClK (to hold requests in request latch)

0

tECSS 2

ECS Set-Up Time to ClK (to enable new status through the status latch)

75

tECSH 2

ECS Hold Time After ClK (to hold status in status latch)

tDCS 2

SGS and B0-82 Set-Up Time to ClK (current status latch enabled)

70

tDCH 2

SGS and 80-B2 Hold Time After ClK (current status latch enabled)

0

tRCS 3

R0-R7 Set-Up Time to ClK (request latch enabled)

90

tRCH 3

R0-R7 Hold Time After ClK (request latch enabled)

0

tiCS

IA Set-Up Time to ClK (to set interrupt inhibit F_F. before ClK)

55

tCI

ClK to IA Propagation Delay

tECRH

ns
70

ns

70

ns
ns

0
50

ns
ns

55

ns
ns

35
15

ns
25

ns

Contents of Request Latch and Request Level Output Status Determination:
tRIS4

R0-R7 Set·Up Time to IA

10

0

ns

tRIH4

R0-R7 Hold Time After IA

35

20

ns

tRA

R0-R7 to A0-A2 Propagation Delay (request latch enabled)

80

100

ns

tELA

ElR to A0-A2 Propagation Delay

40

55

ns

tECA

ECS to A0-A2 Propagation Delay (to enable new requests through request latch)

100

120

ns·

tETA

ETlG to A0-A2 Propagation Delay

35

70

ns

2-53

3214
A.C. CHARACTERISTICS (CON'T)
SYMBOL

LIMITS

PARAMETER

UNIT

MIN

Typ(l)

SGS and B0-B2 Set-Up Time to ECS

15

10

ns

SGS and 80-82 Hold Time After ECS

15

10

ns

MAX

Contents of Current Priority Status Latch Determination:

Enable Next Level Group Determination:
R0-R7 to EN LG Propagation Delay

45

70

ns

ETLG to EN LG Propagation Delay

20

25

ns

ECS to ENLG Propagation Delay (enabling new request through the
request latch)

85

90

ns

ECS to ENLG Propagation Delay (enabling new SGS through status latch)

35

55

ns

NOTES:
(11 Typical values are for TA

= 25°C and nominal supply voltage.

(2) Required for proper operation if ISE is enabled during next clock pulse.
(3)

The~e

times are not required for proper operation but for desired change in interrupt flip-flop.

(4) Required for new request or status to be properly loaded.

(5) tCY = tiCS + tCI

TEST LOAD CI RCUIT

TEST CONDITIONS:
Input pulse amplitude: 2_5 volts_
Input rise and fall times: 5 ns between 1 and 2 volts_

300n

Output loading of 15 mA and 30 pf_
OUT

Speed measurements taken at the 1_5 V levels_

0---..--------;
lOOn

3001

CAPACITANCE(5)

SYMBOL

LIMITS

PARAMETER

UNIT

Typ(l)

MAX

Input Capacitance

5

10

pf

Output Capacitance

7

12

pf

TEST CONDITIONS:
VBIAS =2_5V, Vee = 5V, TA

MIN

=25°C, f = 1 MHz

NOTE:
(5)This parameter is periodically sampled and not 100% tested_

2-64

D.C. AND OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
CerDip . . . . .
Storage Temperature

-55°C to +125°C
-65°C to +160°C

All Output and Supply Voltages.

.

All Input Voltages

. -1.0V to +5.5V

Output Currents .

. • . • . 100mA

. -0.5V to + 7V

·COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device: This is a stress rating only
and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

TA =_55°C to +125°C; Vee
SYMBOL

=5.0V ± 10%

PARAMETER

MIN

Vc

Input Clamp Voltage (all inputs)

IF

I nput Forward Current:

LIMITS
TYPO)

MAX
-1.2

ETLG input
all other inputs

-.15

-.08

UNIT

CONDITIONS

V

IC = -5 mA

-0.5
-0.25

mA
mA

VF = 0.45V

IR

I nput Reverse Current:

ETLG input
all other inputs

80
40

/lA
/lA

V R =5.5V

V IL

Input LOW Voltage:

all inputs

0.8

V

VCC = 5.0V

VIH

Input HIGH Voltage:

all inputs

V

VCC = 5.0V

ICC

Power Supply Current(2 )

VOL

Output LOW Voltage:

all outputs

VOH

Output HIGH Voltage:

ENLG output

lOS

Short Circuit Output Current: ENLG output

ICEX

Output Leakage Current:

2.0

= 2S

Cl

130

mA

.3

.45

V

10L = 10mA

V

10H = -1 mA

2.4

3.0

-15

-35

IA and
A0-A3 outputs

NOTES:
(1)Typical values are for T A

90

C and nominal supply voltage.

12)80-82' SGS. elK. R0-R4 grounded. all other inputs and all outputs open.

2·55

-55

mA

VCC= 5.0V

100

/lA

VCEX = 5.5V

3214

M41
. ~r4RV·

A.C. CHARACTERISTICS
TA=-55°Cto+125°C;
SYMBOL

vee =5.0V± 10%
PARAMETER

MIN

LIMITS
Typ(l)

MAX

UNIT

tcy

ClK Cycle Time l51

85

tpw

ClK. ECS. IA Pulse Width

25

15

ns

ns

Interrupt Flip-Flop Next State Determination:
tlSS

ISE Set-Up Time to ClK

16

12

ns

tlSH

ISE Hold Time After ClK

20

10

ns

tETCS 2

ETlG Set-Up Time to ClK

25

12

ns

tETCH 2

ETlG Hold Time After ClK

20

10

ns

tECCS 3

ECS Set-Up Time to ClK (to clear interrupt inhibit prior to ClK)

85

25

ns

tECCH 3

ECS Hold Time After ClK (to hold interrupt inhibit)

tECRS 3

ECS Set-Up Time to ClK (to enable new requests through the request latch)

3

110

ECS Hold Time After ClK (to hold requests in request latch)

0

tECSS 2

ECS Set-Up Time to ClK (to enable new status through the status latch)

85

tECSH 2

ECS Hold Time After ClK (to hold status in status latch)

tDCS 2

SGS and B0-B2 Set-Up Time to ClK (current status latch enabled)

90

tDCH 2

SGS and B0-82 Hold Time After ClK (current status latch enabled)

0

tRCS 3

R0-R7 Set-Up Time to ClK (request latch enabled)

100

tRCH 3

R0-R7 Hold Time After ClK (request latch enabled)

0

tiCS

IA Set-Up Time to ClK (to set interrupt inhibit F.F_ before ClK)

55

tCI

ClK to IA Propagation Delay

tECRH

ns

0
70

ns

70

ns

0

ns
50

ns
ns

55

ns
ns

35
15

ns
30

ns

Contents of Request Latch and Request Level Output Status Determination:
tRIS4

R0-R7 Set-Up Time to IA

10

0

ns

tRIH4

R0-R7 Hold Time After IA

35

20

ns

tRA

R0-R7 to A0-A2 Propagation Delay (request latch enabled)

80

100

ns

tELA

ElR to A0-A2 Propagation Delay

40

55

ns

tECA

ECS to A0-A2 Propagation Delay (to enable new requests through request latch)

100

130

ns

tETA

ETlG to A0-A2 Propagation Delay

35

70

ns

2-56

A.C. CHARACTERISTICS (CON'T)

MIN

LIMITS
TYP(1)

SGS and B0-B2 Set-Up Time to ECS

20

10

ns

SGS and B0-82 Hold Time After ECS

20

10

ns

SYMBOL

PARAMETER

MAX

UNIT

Contents of Current Priority Status Latch Determination:

Enable Next Level Group Determination:

tECSN

R0-R7 to EN LG Propagation Delay

45

70

ns

ETLG to ENLG Propagation Delay

20

30

ns

ECS to ENLG Propagation Delay (enabling new request through the
request latch)

85

110

ns

ECS to EN LG Propagation Delay (enabling new SGS through status latch)

35

55

ns

NOTES:
111 Typical values are for TA

= 25°C and

nominal supply voltage.

121 Required for proper operation if ISE is enabled during next clock pulse.
(3) These times are not required for proper operation but for desired change in interrupt flip-flop.
(4) Required for new request or status to be properlv loaded.

(51 tCY

= tiCS + tCI

TEST CONDITIONS:

TEST LOAD CIRCUIT

Vce

Input pulse amplitude: 2.5 volts.
Input rise and fall times: 5 ns between 1 and 2 volts.

300n

Output loadi ng of 15 rnA and 30 pf.
OUT O--~-------1

Speed measurements taken at the 1.5V levels.

30 pI

CAPACITANCE(5)

LIMITS
TYP(1)

MAX

Input Capacitance

5

10

pf

Output Capacitance

7

12

pf

SYMBOL

PARAMETER

TEST CONDITIONS:
VBIAS = 2.5V, VCC = 5V, TA

MIN

= 25°C, f = 1 MHz

NOTE:
(S)This parameter is periodically sampled and not 100% tested.

2-57

UNIT

3214
WAVEFORMS

'OCS

• ______ J

~

'ocH','-.;;;;---;07/1

------- --,
~

r--- -----------

X
-J1''-----r----------

-------+--Ji~--------teres

'ETCH

--------ylX----------------

ISE - - - - - - -

------4---~------J.;I~ _J

1

'ISS

IISH

r-~

r---- ,

SGS '0',

JI~+~EJ~ -------J~~,~D~HJ '-I-.-~.-EC-SS-.-EC-SH-I-"""\

ECS

Ir+---+~,

i'--J

~--+,I

lEeRS

CLK

"CRN

-----

=±

I-~."""~--f

'PW

_.j::~::j:::j:==1==1==~EC~C"-S---

IA

x-------

'(u---------------x

0 0 0,

_________

~i

--

'-_+--J

tecRH

leeCH

'CI

ICY

~

r-----, __ _

__________ J~

I~

tpw

I

-:~~-- ------)(I~--------------

ELO

-+--...j::j::-:::-=I=I-:-:,!.,-ar +----- ~L: __ ,I~____
------ -.-- .... -IETEN.I '--+-________
tecsN
ENLG

J

OEN

'- _ _ _ _ _ _ _ _

-------------------------~)(--------------)(------

TYPICAL CONFIGURATIONS
The ICU has been designed for use
with the INTEL Series 3000 Bipolar
Microcomputer Set. It operates from
the single common system clock and
can accept an interrupt strobe (lSE)
generated by the 3001 Micropgoram
Control Unit or by a bit in micropro'
gram memory as shown in Figures 2
and 3.
The ICU responds to interrupt reo
quests of sufficient priority by enter·
ing the interrupt active mode. Its
output (lA) can be tied to the row
enable input (ERA) of the 3001 MCU.
This gates an alternate row address
onto the microprogram memory ad·

dress bus which forces the system to
execute an interrupt handling routine.
Alternatively, the ICU output can be
used to directly modify the MCU jump
instruction (AC inputs) so that the
next microprogram address corresponds
to the start of the interrupt routine
rather than the start of the macroin·
struction fetch sequence. Of course,
in the case of this particular imple·
mentation, the interrupt strobe must
be generated one clock period earlier
and the ISE output of the MCU
should not be used.
As shown in Figure 4, when several
ICUs are used together to provide a

2-58

multiple of 8 priority levels, most con·
trollines will be bussed. The Intel
3205 Decoder may be used to decode
the high order bits of the request level,
the information being derived from
the daisy·chain group level signals.
As mentioned in the functional description, the request level information
(Ao-A2) may be sent to the 3001 MCU
or the 3002 CP array as a constant
through the Mask (K) bus or as data
through the memory (M) or data (I)
busses. Similarly, the status information can be generated by the CP array
and carried to the ICU by the data (D)
output bus of the CP array.

3214
TYPICAL CONFIGURATIONS (CON'T)
MlCRO·INSTRUCTION

MICROPROGRAM
MEMORY

TOct'ARRAY,
110 AND MAIN MEMORY

RAM -3101,3107

MIC;:AOf'ROGRAM

MICRO·INSTRUCTION

MEMORY

"OM-3301A, 3304"
I'ROM -1801.3104

TOct'ARRAY.

AAM-31G1.lI01
ROM-3)(11,\,3304.
"ROM-lIIIl,3IIM

110 AND M"IN MEMOFlY

AC'I===::;l

Figura 2. Interfacing 3214 with 3001.

Figura 3. Interfacing 3214 with 3001.

Interrupt strobe generated by MCU.
Interrupt routine start address at column 15 row 31.
Macro-instruction fetch start address at column 15 row 0.

I nterrupt strobe generated by the microprogram memory.
Interrupt routine start address at column 14 row 0Macro-instruction fetch start address at column 15 row 0.

...

~J
.

.."VHOW{
INTERRUPT

RIOUIS"
IHIO"II'
PRIORITY
OROlWl

:

r--

.,
,.

ICU1.t.o

..

rnI

'G,

OI.

l:r

m-

r-~
r;-.'

.."V, LOW {

.

"UOfUTY

GROUPI

_.

112

_,v
A,

r;:::=:

ICUI AO

I.

ENlG

-~

r-

1

~f-[J
.,

INTERRUPT
REOUESTS
ILOWEST
I'RIORITY
GROUPI

.
:

'GS

::'.'

.,

ICUO

Ao

1CUfi'R_

-

I.

ISE~

~l

L..J...

AC"VHOW{

.,.,

32.4

r;:::
r- A.

"" OS.

INT STROBE FROM MCU OR
MICROPROGRAM MEMORY

r---ETlO

.,.,

SG$

-

ENABLE LEVEL READ

INT ACKNOWLEDGE
{TO ERA"'" Of MCUI

ElLG

INTEIIHU"

REOUESTS
12ND HIGHEST

r-r--

III

ENLO-

e--'

}a~.

-

1m

Ao

"" f-rrI.

ISE

...

f- r-

ENLG

~

l

"..

,III

I
i

CU""IJIITITATUS
I f " " CI' ""RAYI

I

tHAIU CURRENT
STATUI

Figura 4. Using Several 3214 Interrupt Chips to Provide more than Eight Priority Levels.
(The 3214 at the upper right is used to encode the high order bits of the requesting level)

2-59

intel

SCHOTTKY
BIPOLAR LSI
MICROCOMPUTER
SET

The INTE~3216 is a high-speed 4-bit
Parallel, Bidirectional Bus Driver. Its
three-state outputs enable it to isolate
and drive external bus structures
associated with Series 3000 systems

High Performance- 25 ns typical
propagation delay
Low Input Load Current-O_25 mA
maximum
High Output Drive Capability for
Driving System Data Busses
Three-State Outputs
TTL Compatible
16-pin DIP

The INTEL 3226 is a high-speed 4-bit
Parallel, Inverting Bidirectional Bus
Driver_ Its three-state outputs enable
it to isolate and drive external bus
structures associated with Series 3000
systems_

3216/3226
PARALLEL
BIDIRECTIONAL
BUS DRIVER
PACKAGE CONFIGURATION
cs

vcc

000

DCE

DBa

'4

003

01 0

'3

DB3

DO,

INTEl@

3216

'2

01 3

DB,

11

0°2

01,

'A

GND

The 3216/3226 driver and receiver gates
have three state outputs with PNP
inputs_ When the drivers or receivers
are tri-stated the inputs are disabled,
presenting a low current load, typically
less than 40 /lamps, to the system bus
structure_

3216

3226

LOGIC DIAGRAM 3216

LOGIC DIAGRAM 3226

010 o----~I>-~---,

DIOO------jl>o>---j---,

DOoo-----i----<>--+--,

0" o----j---jl>---j---,

01,

oo,o-----i----O---j----'

01, o-----i-~I>----i---,

OI,o----j---jI>o>---j---,

DO,o----j-------j---,

DD,o----j--o===r
I

~

-----------'

I

O.5V

2-65

OH
V
VOL

System Timing

Series 3000
System Timing
Considerations
by Gary Fielland
While the timing for each component in Intel's 3000
Series Schottky Bipolar Microcomputer Set is clearly
specified, the composite system timing must be derived. This system timing is highly dependent on the
particular configuration implemented, and hence,
must be carefully considered for each implementation.
Though Intel cannot generate the system timing for
every possible configuration, an effort has been
made to study a few simple variations. By examining
these examples and taking note of considerations
given, it should be easier for the system designer to
realize those times which are critical, and to generate the appropriate timing for his particular system.
The designer must consider many different factors in
determining this "proper" system timing. Several
simplifications are made to facilitate this discussion.
Intel commercial grade parts are specified over a
wide temperature range (O°C - 70°C) and so variations in timing due to temperature will not be considered, except for a short note at the end.
Whenever a signal must traverse a conductor between
two points, there is a finite delay introduced into
the signal path that is not accounted for by any data
sheet. This is the delay due to such factors as the

Aside from these simplifications, it should be realized
that this note is not an extensive study of the timing
of any particular system, but rather a compendium
of typical considerations which a designer might
examine.
Consider the basic "data sheet" I6-bit processor configuration as shown in Figure 1. It utilizes pipeline
registers, full carry look-ahead, and a priority interrupt mechanism. To implement any such system the
designer must be very careful to provide the proper
timing for all components under all possible operating conditions. Such a system is highly complex and
the analysis is best approached in a piecemeal fashion.

t

MICRO·
PROGRAM

PIPELINE

MEMORY
16 3601·1·S
OR
4 3604'S

length of the conductor, its transmission properties,
and the characteristics of the driver and receiver.
When a TTL totempole output drives a TTL input a
short distance away this delay is usually negligible
compared to other delays in the signal path. However, if there are many loads (increasing the capacitance), or the driver is of the open-collector type
(limiting the drive), or if the receiver is physically far
removed, the designer should consider and allow for
any possible deleterious effects of this delay. For this
discussion, except in one special case, the delay introduced by interconnection is not considered.

K BUS
CK

I---

, . . - LI

CI

VECtOR

j

E

C"

Cn+8

l

1

CK MA8·4 MA3·B
AC6-9
MCU FC9·3
3214
3001
FO
IAI------ ERA
FI
B8'·2
RiI·7
SX9·PX7
CK

AB·2

ICU

INTEJRUPT
REQUESTS

ISE

t

J~"+'

+Vcc

I - - ISE

"N
M,N I--ROI---

XY

t

I

INTERRUPT

DOUT

16 BIT
CPE ARRAY
3OO2'S

CK

ADDRESS

SY STEM
CL OCK

t

F)1.6 "oUT

REGISTERS
74S174

1

CARRY XY
LOOK-AHEAD
3003

Cli-

C"~

--

t
I
MEMORY

DATA

Figure 1. Basic 16-Bit Processor Configuration

3-1

OTHER
DATA

System Timing
ARITHMETIC DELAY PATHS
First an analysis will be made of the arithmetic paths
and delays. Imagine cycles in which arithmetic is
being done within the CPE array. The carrys must
have time to propagate through the arithmetic portion and reach the MCU so that a conditional jump
may be made based on that carry out bit. For the
moment ignore other critical paths, and examine
Figure 2 which illustrates these arithmetic cycles.

Keeping the same train of thought, consider individually the effects of variants from the configuration
of Figure 1. If full carry look-ahead is not used and
the carry is allowed to ripple through only the last
slice, an additional delay path is introduced. After
the 3003 has generated the carry outputs there is the
CPE carry-in setup time (tSS) which must be met as
before. However, the carry-out of the last slice will
not be available to the MCU flag input until it has
rippled through (tCe> that slice. Finally, the MCU
flag input setup time (tsI) must be satisfied.

The cycle begins with the rising edge of the system
clock as it clocks the pipeline registers. After the delay (tpLR) introduced by the pipeline, the function
is available at the CPE array. There is a delay (tXF)
while all the CPE's decode the function and generate
their X and Y outputs for the operation. Once the X
and Y outputs are stable, the Carry Look-Ahead circuit takes some time (txC> to simultaneously generate all the carry outputs, including the one which
goes to the MCU flag input. Time must be provided
to allow for the carry-input setup time of the CPE's
(tss) and the MCU (tsI). Finally, adding in enough
time for the clock pulse, which acts as a write pulse
for the CPE register array, the cycle time is determined. Note the time for the MCU flag output to
stabilize (tKO) was ignored as it is not a limiting
specification for this configuration.

tCYCLE = tpLR + tXF + txc + tcc + tsI + twp
If the 3003 Look-Ahead Carry circuit is not used,
there will be considerable delay added to the basic
cycle due to ripple carry time. Once the CPE function-inputs are stable, the function must be decoded
and the carry-out of the least significant slice generated (tCF)' The carry must ripple through six slices
(6* tCC) and meet the carry setup time (tsS) of the
most significant slice. However, it must also ripple
through this last slice (tCC) and meet the MCU flag
input setup time which is a more severe restriction.

tCYCLE = tPLR + tXF + txc + tss + twp

CLOCK

u

FUNCTION
INPUTS

•

tcYCLE = tPLR + tCF + (7* tCC) + tSI + twp

u

1

~~~

i

----------- I

j-----tXF~:
X. Y. RO
OUTPUTS

C

r--------------------------

i
I
i'xc---+\---'sS-1
CARRY
INPUTS

'

~~~

*-------------------..;.I--

------------------------~------~

t-'SI--~-i----------i

_ t cc

FLAG
INPUT

l

--'

==================================
tPLR

elK t to pipeline register outpUts (745174)

'XF

function inputs to X,Y,RD outputs

17
52

'XC

Lookahead - X. V inputs to carry OUtputl

20

'SS

Data set-up time, LI &: CI

27

'CC

Ripple carry lei to CO) delay

25

'SI
'WP

NOTE: tce included only if carry ripples through lalt slice.
Flag input set"lJP time

'5

Clock pulse width

33

tCYCLE

Full fast carry

tpLA + tXF + txc + tss + tw'P

last slice ripple

tPLR

'49

+ tXF + txc + tce + tSI + tw'P

If pipeline ragistersare not used; replace tPLA with the sum of teo (eLKt to

'62
M~

outputs,

44 nsec) plus tROM (access time; 50 nsec for 3601-1, 70 nsec for 3604).
If 3003 fast carry is not used; replace tXF with teF (function IN to eo output, 85 nsec);
replac8tXe + tee with (N-l)-tee. where "N" is the number of stices used.

Figure 2. Non-Interrupt 16-Bit Processor Cycle Timing

3-2

"sec

System Timing
Consider first a special case. Namely, the data is input via an LTM instruction and no test will be made
on the carry-output. This implies that for this specific
instruction, carry propagation is unimportant and it
is acceptable to have an erroneous carry-output. For
such a case, it is sufficient to only allow for the
CPE data setup time (tDS)'

If pipeline registers are not used, there will be additional delay. It takes some time (tCO) after the rising edge of the clock for the next address to propagate through the MCU address register and buffers.
Then, when this address is stable the ROMs must be
accessed and there will be a delay (tROM' access
time) before their output and hence the CPE function-input is stable. Thus, the cycle time for a nonpipelined system with carry look-ahead is:

tCYCLE

tSETUP = tDS
For the more general case where arithmetic is done
on input and the carry-output may be tested, the
above analysis is incomplete. While the above condition must be met, it is no longer the determining factor. Time must be allowed for carry propagation.
See Figure 3, which illustrates this case.
From the point in time when the data becomes stable
at the CPE inputs, there is a delay (tXD) while the
CPE generates the X and Y outputs. If Ripple Carry
is employed, the delay (tCD) is in waiting for the
carry-output of the least significant slice. After
either of these delays the rest of the setup time is
allocated analogously to that depicted in Figure 2
and discussed previously in relation to arithmetic
cycle times.

= tco + tROM + tXF + txc + tss + twp

In the previous discussion it was assumed that the
operands in the arithmetic operations were internal
registers and the K-bus as implemented. If one of the
operands is the M-bus or the I-bus, additional consideration should be given. This situation will typically arise at the completion of a Memory-Read or
Input cycle. Typically, these cycles are implemented
such that the processor clock stops in its high state
to wait for the data to be available, while the processor is in the midst of executing an LMM or similar
instruction. Thus, it is often the case that the pipeline registers have long since been accessed and the
function decoded.
Then, when the data becomes available a clock pulse
is issued and normal operation continues. It is the
time from the point the data becomes available until
the clock pulse is issued (Data Input Setup Time)
that is of concern here.

tSETUP (Basic) =tXD + txc + tss
tsETUP (Last Slice Ripple) = tXD + txc + tcc + tsI
tsETUP (Ripple Carry) = teD + (7* tCe> + tSI
tsETUP (No Pipeline) - Same as Basic

CLOCK

DATA

INPUTS

-t

I

'xo"-

x, V
OUTPUTS

-'xc-I'
X

CARRY
INPUTS

'"

·I~,cc~

I

FLAG
INPUT

\'=t

SI - _

I

tXD

Data inputs to X.V outputs

tHX

SX,PX input hold time

tSET-UP

Full fast carry
LIlt slice ripple

42 nsec
20

89

txo + txc + t55
tXD + txc + tee + tSI

102

If 3003 fast carry is not used; replace tXD with tCD (data input to CO output, 55 nsec);
replace txc + tee with (N-ll-tCC then tSET-UP fripple carryl.
NOTE: This diagram is UMJ.lly of concern only in relation to memory-read, or input
cycles.

Fillur.3. 16-Bit Processor Data Input Set-Up Times

3-3

245

t=

System Timing
CONTROL DELAY PATHS

control inputs. Some consideration must be given to
the additional requirements on timing imposed by
the use of this ISE output. After the ROM has been
accessed and the MCU address control inputs are
valid, it takes the MCU some time (tFI) to decode the
JZR 15 operation and raise the ISE output. This output is used as the 3214 ISE input and must be valid
early enough to meet that input setup time (tISS).
As this setup time is relative to the rising edge of the
clock, the clock pulse width need not be added in.

After carefully examining the arithmetic paths and
delays it is appropriate to push all of this information onto your "mental stack" and begin again with
a consideration of the control paths and delays_
After this study the stack can be popped and information merged to yield overall system requirements_
Consider the MCU as it cycles in normal operation
(see Figure 4). At the rising edge of the clock the
new microprogram address is loaded into its holding
register and through the output buffers. Thus, the
new address reaches the ROM after a delay (teo).
Then there is a wait (tRaM) while the ROMs are accessed before the outputs are valid. At this time the
MCU address control inputs (which are never pipelined) are valid and this must be early enough in the
cycle to satisfy the MCU address control input setup
time (tSF). Adding the time for the clock pulse
(twp) yields the cycle time requirement. Note this
paragraph has ignored the generation of the ISE
output.

tcYCLE = teo + tRaM + tFI + tISS
Recalling the basic configuration depicted in Figure
1 and the situation described in the last paragraph,
imagine that an interrupt request had been active
long enough to meet the request setup time (tRCS)
of the ICU. Then since the ISE input went high and
satisfied the input setup time, the Interrupt Acknowledge flip-flop within the 3214 will change state
and lower the MCUs ERA input after a delay (tCI).
After the row address outputs are disabled (tEO)'
the pull-up resistors will begin to pull these lines high
and after the voltage on these lines rises to 2.0V
(tRISE) the ROM address will be valid. The remainder
of this cycle is the same as previously described and
usually will not be required to again generate an ISE
pulse.

tCYCLE = teo + tRaM + tSF + twp
In the basic configuration shown in Figure 1 the ISE
output is used to strobe the 3214 Interrupt Control
Unit each time a JZR 15 (usually a jump to macroinstruction fetch) is recognized at the MCU address

tCYCLE

=

tCI + tEO + tRISE + tRaM + tSF + twp

CLOCK

ROM
ADDRESS

AC 16-61

INPUTS

ISE
OUT

:

,t°-1

',I

1--t

c

ERA
INPUT

I

F==---tM-U-X~--~-----------------

tco

elK t to MA [8 ..... 4>1 outputs

44 nsec

tROM

ROM access time (70 nsec for 3604) 3601- 1

50

tSF
tFI

ACIS .....1/.l1 input set-up time

10

ACI6-¢1 input to ISE output

40

tlSS

ISE input (3214) set-up

16

tc,

elKI to IAoutput (3214)

25

tEO

ERA input to MA 18 ..... 4J output

tRISE

RISE time to 2.0 V with 1 KH pull-ups: (16"3601-1)

32
84
21

tMUX

Multiplexer switch time (7451581

tCYCLE

Ignoring ISE output

teo + tROM + tSF + twp \3601-11

Using ISE output

teo + tROM + tFI

14"36041

12
(3604)

+ llSS 13601-1)

137
157

150

Interrupt using pull-upstCI + tEO + tRISE + tRaM + tSF + twp (3601-11

234

Interrupt using MUX" tel + tMUX + tROM + tSF + twp (3601-11

130

("MUX adds tMUX-PROP [6 nsec] to

Figure 4. MCU & Interrupt Cycle Timing

3-4

tcol

System Timing
Examining the times shown on Figure 4 for this case
of an interrupt cycle using pull-up resistors, it is clear
that unless something is done this will be the limiting cycle time requirement. There are several techniques which may be used to ease this requirement.
Since interrupt cycles are relatively infrequent in
comparison with other cycles, one solution might be
to extend just that cycle. In other words, the system
cycle time would be determined by all considerations
previously mentioned, but ignoring the abnormal interrupt cycle requirement. Then the clock circuit
would be designed such that it could extend a cycle
in response to a signal from the 3214 Interrupt Control Unit (see Figure 5).

teYCLE (Interrupt with MUX)

tCI + t MUX + t ROM + tSF + twp

MICRO·
PROGRAM
MEMORY

ADDRESS

l
MULTIPLEXER
SELECT
A'N

+Vcc
SYSTEM
CLOCK

I
ClK
OUT
CLOCK
GENERATOR

r

j
CK

CYCLE
EXTEND

i----

B'N

r
MAB-4

'SE

MA3-O

'SE

ICU

CK
'SE

'CU
3214

=

MCU
IA

f.--

+Vcc

--"

ERA

'SE
MCU
3001

~

TERA

1

Figure 6. Multiplexer to Reduce Address Rise Time

A third alternative to solve the long interrupt cycle
requirement is to implement the interrupts in quite
a different way. Rather than changing the MCU address outputs, the MCU address control input least
significant bit (AO/» may be altered (see Figure 7).
Using this technique an extra ROM bit (Interrupt
Strobe) is required to strobe the 3214 ICU since the
MCUs ISE output occurs one cycle too late. Implementing the same mechanism (interrupt strobe on
JZR 15) could be done by using the interrupt strobe
bit to strobe the ICU (see Figure 7) the cycle before
the JZR 15 code appears. An added benefit of this
method is that the interrupt structure may be strobed
at points other than the beginning of an instruction
fetch cycle, facilitating PAUSE or WAIT instructions.
Examining the timing diagrams in Figure 7, it can be
seen that this implementation of interrupts does not
limit the system cycle time. Rather, this interrupt
mechanism's timing is less restrictive than timing for
a normal cycle. The only requirements are that the
interrupt strobe bit from the ROM reaches the 3214
ICU ISE-input within its setup time (tISS ). In the
next cycle it is only necessary that the lA-output has
gone low (tCI) early enough to meet the MCU address control input setup time (tSF). Thus, for the
price of one bit of ROM interrupts can be implemented with no penalty in time.
At this point both major delay paths (arithmetic and
control) have been examined for the implementation
in question. After the designer has assured himself

Figure 5. Interrupt Cvcle Extension

The interrupt cycle would still be exactly as depicted
in Figure 4, but the length of the interrupt cycle
would be longer than a normal cycle, and in fact long
enough to accommodate the interrupt cycle requirement.
It can be seen that a significant portion of the interrupt cycle is lost waiting for the pull-up resistors to
charge the capacitance on the address lines. Thus,
another method of easing the interrupt cycle requirement would be to reduce the address line rise time
(tRISE). Reducing the resistance of the pull-ups
would help but this technique is limited by the available MCU address output fanout. Alternatively, the
MCU row address outputs (MA8-4) could be connected to the ROM address lines through a multiplexer such as the 74S158 (see Figure 6). With such
a connection the interrupt cycle time is reduced
since the MCU enable time (tEO) plus the address
line rise time (1RISE) may be replaced with simply
the multiplexer select time (tMUX) as shown in Figure 4. However, it should be noted that such a connection adds delay to the MCU address outputs, thus
effectively lengthening this existing delay (teo) by
the multiplexer propagate time (tMUX.PROP) and
hence lengthening any cycle which was dependent on
the MCU delay (teo).

3·5

System Timing

MICROPROGRAM
MEMORY
(OPEN·
COLLECTOR)

ISEI-----I
ICU

+Vcc

IA

teo + tROM + tSF + twp
tco + tROM + 1155
Modification) > teo + tROM + tSF + twP. and

tCYCLE (Non-Interrupti ;>

+Vcc

tCYCLE (Interrupt Strobel

MCU

tCYCLE IAC[411

+Vcc

AC6-11----4o-AJlIv--'

ERA

)0

;;;.otel + tBUF + tSF + twP
tCYCLE (Interrupti - Same as Non-Interrupt

CLOCK

Ir-

L

'-J

~

'w.- -

'wp- ~ _ t c o _

~'co--ROM
ADDRESS
__ t

ROM

___

1\

-'S.-

I--'ROM

t
'ISS

IA
OUTPUT

7417
OUTPUT

.-

'

JZR 15 CODE
FROM ROM

INTERRUPT STROBE
BIT APPEARS
CI

__

MODIFIED TO JZR 14
BY IAOUTPUT

J

---

tauF

[-

Figure 7. Interrupt Using AC (1/» Modification

there are no other delays which he may have overlooked, such as introducing external circuitry into
the paths, he may merge the various requirements
generated into a uniform set of system requirements.
Any change introduced after these requirements have
been generated must be closely examined that it does
not subtly alter any system requirements. Delays that
are negligible in one configuration may be dominant
in a slightly different structure.

WHAT HASN'T BEEN MENTIONED?

1. In the introduction it was explained that temperature would not be considered in the examples
since Intel specifies products over the 0° C to 70° C
temperature range. This deserves further comment.
A quick glance at an Intel Data Sheet will verify
that Intel parts are specified and guaranteed over
the O°C to 70°C ambient temperature range and
concurrently with a five percent tolerance power
supply. This is a reasonable range and allows the
designer to guarantee circuit operation.
.

Unfortunately, the standard Schottky MSI line
(74SXX) is only specified at 25°C ambient and
Vee = 5V. The variance of parameters over the
allowable temperature and supply voltage is un·
specified and left to the designer's experience. Due
to this uncertainty the designer should "appro·
priately" modify any times attributable to nonIntel parts to allow for variations over temperature and supply voltage.
2. In the examples given it was always assumed that
setup times would be honored. Though most of a
computing system is synchronous, it typically has
to interface with asynchronous events. It is at this
interface that difficulty may be encountered. Consider a popular circuit (Figure 8) used to "synchronize" asynchronous signals.
In this circuit the output delay is guaranteed only
if the input setup time is met. But since the input
is asynchronous, this setup time may not always
be satisfied, as at the second event depicted in
Figure 8. What happens? Though the results are
highly dependent on the flip-flop circuit design,

System Timing
Recall the 3214 Interrupt Control Unit and its request setup time (tRCS) and its IA output delay
(tCI)' This delay is in several critical system paths
as shown by the examples. Of course, the IA output delay specified also presumes the IA flip-flop
setup time was met. When deliberately violating
the IA flip-flop setup time, a hang-up of 50 nsec
has been observed. What is a designer to do?
Slowing down the system such that it could tolerate any expected hang-up would be the easiest
solution. This may not always be as bad as it
sounds. Recalling the situation depicted in Figure 7, note that some flip-flop hang-up is tolerable. [tIA-HANG = tCYCLE - (tSF + twp )]. An alternative would be to "synchronize" the asynchronous interrupt requests using the technique
previously described. An octal D flip-flop such as
the 74S374 would be suitable. .

some general observations may be made. Typically,
the effect is to stretch out the flip-flop delay time
as the event approaches arbitrarily close to the
clock edge. Theoretically, the delay will go to infinity if the event falls precisely on the clock edge.
Some flip-flops also exhibit a characteristic in
which the output may change state and some time
later return to the original state. This phenomena
is known as "hang-up" and has been observed to
last for twenty nanoseconds on a 7 4S7 4. It cannot be absolutely prevented when asynchronous
signals are introduced into a synchronous system,
but the probability of the "hung" flip-flop causing
an error can be reduced without limit. The technique is simply to cascade these interfaces.
If two such flip-flops are cascaded there is some
probability PI (Pj <1) that the asynchronous event
will fall close enough to the clock edge to hang
the first flip-flop. Given that it hangs, there is
some probability 1'2 that it will hang for very nearly an entire clock period and into the hang-up
zone of the second flip-flop. Then, there is a
probability Pa that the second flip-flop will hang
long enough to cause an error. Thus, the probability of error is I'E = PI *P2*Pa. Hence, by cascading flip-flops the probability of error can be
reduced without limit.

ASVNCHRONOUS I
SVSTEM

3. In the examples given it has been assumed that
the system, including all the CPEs, the MCU, and
the ICU, operates from a single clock. If a circuit,
such as in Figure 9, that provides a separate clock
for different components is used, the possible
clock skew must also be considered when determining system timing.

INTERFACE

74874

----+-----~D
ASV-;;;;::ONOUS I
EVENT

I SYNCHRONOUS
I SVSTEM
I

Q~------~-----

I~CK
"'1J"'"'U""
SYSTEM
CLOCK

SYSTEM
CLOCK

ASVNC
EVENT

Q

OUTPUT

LJ

U
*'OU1

{:'"j

U

~l,"+;:t" .I.

tsu - 74574 oa1a input set-up time" 3 nsec.
tFO - 74574 Delay hom clock t ·9 nsec.
tHU - Heng up due to set-up time violation.

Figure 8. Synchronizing Circuit Exhibiting Hang-Up

3-7

~

U

1-'oU1

X

t

HU ---

System Timing
SUMMARY
Generating the correct timing for a complex system
in which parameters may vary with temperature,
power supply voltage, lead length and the like is no
trivial task. Fortunately, large scale integration such
as Intel's 3000 family is making the task much easier.
With the 3000 family of compatible parts the designer need only worry about the interfaces and may
be assured the internal timing is correct. Such a system is best analyzed by separately considering the
various delay paths and later combining the sundry
results. And of course, with Murphy on vacation the
designer can be confident of a flawless design on the
first pass.

TWICE
CLOCK - - - . . _ - - - - - - - ,
RATE

MCUANO
SYSTEM

"RUN"---+-~

CLOCK

CPE
CLOCK
CPE CLOCK
INHIBIT
BIT FROM PIPE LINE

REGISTER

Figure 9. CPE Clock Inhibit Circuit

4. Though not explicitly mentioned, it has been assumed that all input hold times would be observed.
Usually these times are satisfied with no conscious
effort required of the system designer. However,
parameters such as the MCU SX and PX input
hold time must be carefully considered. These inputs are used for macro instruction decoding and
typically are used at the end of an instruction
fetch cycle. When using these inputs the designer
must provide the necessary data hold time before
allowing the data to change.

3-8

Disk Controller Design

Disk Controller Designed
With Series 3000
Computing Elements
by Glenn Louie

Figure 1. Bipolar Microprogrammed Disk Controller

speed microprocessors that together with a minimum of external logic perform the intricate program sequences required by high speed peripheral
controllers.

With the introduction of the first microprocessor, digital designers began a massive switch to
programmable LSI technology, away from hardwired random logic. Designers found that with
these new LSI components and the availability of
low cost ROMs they could easily implement structured designs which were both cost effective and
flexible. However, not all digital designs were
amenable to the microcomputer approach. One of
the basic limitations was the speed at which a particular critical program sequence could be executed
by a microprocessor. The early P-channel MOS
microprocessors, such as Intel's 4004 and 8008,
were able to solve a broad class of logic problems
where speed was not essential. With the introduction of the more powerful n-channel MOS microprocessors, such as the Intel@8080, the range of
applications was significantly broadened, but there
still existed a class of applications that even these
newer devices were not fast enough to handle.

A multi-chip bipolar microprocessor differs from
the single chip MOS microprocessor in that the
bipolar microprocessor is programmed at the· microinstruction level rather than at the macroinstruction level. This means that instead of specifying
the action via a macro program using a fixed instruction set, a designer can specify the detailed
action occurring inside the microprocessor hardware via a microprogram using his own customized
microinstructions.
In general, microinstructions are wider than
macroinstructions (e.g. 24 to 32 bits) and have a
number of independent fields that specify simultaneous operations. In a single microcycle, an arithmetic operation can be executed while a constant is
stored into external logic and a conditional jump is
being performed.

Recently, two new Schottky bipolar LSI computing elements, members of the Intel Bipolar
Microcomputer Set, were introduced which expand
the range of microcomputer applications to include
high speed peripheral controllers and communication equipment. The new elements are the 3001
Microprogram Control Unit (MCU) and the 3002
Central Processing Element (CPE). These two components facilitate the design of specialized, high

A bipolar LSI microprocessor design is )im. ilar to
a general MSI/SSI microprocessor design where
the intricacies of the application are imbedded in
the program patterns in ROM. However, the large
amount of logic necessary to access the microcode
has been replaced by the LSI MCU chip. Also,
3-9·

Disk Controller Design
the MSI logic required to provide the arithmetic
and register capabilities has been replaced by the
functionally denser LSI CPE slices. Because of
these new LSI chips, microprogramming with all
its advantages can now be applied to designs which
previously were unable to justify microprogramming
overhead.

The bipolar LSI microcomputer in the BMDC
performs the necessary command decoding, address checking, sector counting, overlap seeking,
direct memory accessing, write protection, password protection, overrun detection, drive and read
selection, and formatting. External hardware assists
the microprocessor in updating the sector counter,
performing parallel-to-serial and serial-to-parallel
conversion, and generating the CRC data checking
information. The BMDC uses a special purpose
microprocessor, configured with the components
listed in Table A. The LSI microprocessor uses an
MCV, an 8: I multiplexer, eight 360 I PROMs, a
command latch, a data buffer, and an array of
eight CPE slices (Fig. 2). The characteristics of
this design, only one of many possible with the
3000 family, are as follows:

The effectiveness of these new LSI components
in a high speed peripheral controller design has
been demonstrated by the Applications Research
group at Intel with the design of a 2310/5440
moving head disk controller (BMDC). The BMDC
has a total of 67 IC chips and is packaged on a
printed circuit board measuring 8" x IS", as shown
in Figure I. Disk controllers of equivalent complexity realized with conventional components
typically require between 150 and 250 I.C.'s. The
BMDC performs all the operations required to
interface up to four "daisy chained" moving head
disk drives, with a combined storage capacity of
400 megabits, to a typical minicomputer. It is fast
enough to keep up with the drive's 2.5 MHz bit
serial data stream while performing the requisite
data channel functions of incrementing an address
register, decrementing a word count register, and
terminating upon completion of a block transfer.

•
•
•
•
•
•
•

400 nsec system clock
16-bit wide CP array
Ripple carry CPE configuration
Non-pipelined architecture
One level subroutining
230 32-bit microinstructions
Word to 4-bit nibble serialization

The MCV controls the sequence in which microinstructions are executed. It has a set of unconditional and conditional jump instructions which is
based on a 2-dimensional array for the microprogram address spece called the MCV Jump Map. (I)

The BMDC interacts with the minicomputer's
disk operating system (DOS) via I/O commands,
interrupts and direct memory access (DMA) cycles.
The I/O commands recognized by the BMDC's
microprogram are:

PART #

Conditions In
Seek Cylinder
Write Data
Read Data
Verify Data
Format Data
The BMDC sends an interrupt to the minicomputer when either a command is successfully executed, a command is aborted, or a drive has finished
seeking. The DOS then interrogates the BMDC
with a Conditions In command. The following
flags specify the conditions which the BMDC can
detect:
Done flag
Malfunction flag
Not Ready flag
Change In Seek Status flag
Program Error flag
Address Error flag
Data Error flag
Data Overrun flag
Data transfers between the minicomputer and
the disk BMDC occur during DMA cycles. DMA
cycles are also used for ·passing command information from the minicomputer to the BMDC.

DESCRIPTION

QUANTITY

3001

MCU

1

3002

CPE

3212

8 bit 1/0 Port

3205

1 of 8 Decoder

8
6
2
8

3601

lK PROM

3404

6 bit Latch

74173

4 bit Gated D F/F

74174

6 bit D F/F

74175

4 bit D F/F

74151

8: 1 Multiplexer

8233

Dual 4: 1 Multiplexer

9300

4 bit Shift Register

9316

4 bit Binary Counter

2

8503

CAe Generator

1

7474

Dual D F/F

5
2

7473

Dual J·K F/F

7451
7404

And-Dr-Invert Gate
Hex Inverter

Quad 2 Input Nand Gate

1
6
9

7400
74H08

Quad 2 Input And Gate

1

7403

Quad 2 Input Nand O.C. Gate

2

7438

Quad C.C. Drivers

4

74Hl03

Dual J·K F/F

2
Total

67 I.C. Packages

Table A. I.C. Component List for Disk Controller
3·10

Disk Controller Design
MICROPROGRAM MEMORY

OUTPUT PORTS

8·36015

~
.1

8

8

ACQ·6

Fe
Fa

,001
SX

PX

2

7

2

F1

-7";

1

t
I' It·····
,I ,I

8

----I

~IIIIIIIII

MAO.
MCU

J'

8:1 MUX

I

INPU~ PORT

y

O-l-DATA
MUX

......-'

t..... t

PORTA

t

I II 1·····1'

I

,

PORTe

PORT B

t

I

I

f8

LeI
' - - - eo

,.

I

LI

o OUTPUTS

18
MAB

I

M

,.

,.

I
•

K

AO

CP ARRAY
8 - 3OO2's

A OUTPUTS

4

COMMAND
LATCH

FO-6

8

NIBBLE OUT

4
4
NIBBLE IN

EXTERNAL LOGIC

J.

27

,

DATA BUFFER

,.

18
MOB

DISK DRIVE
SIGNALS

Figure 2. Disk Controller - The various elements of a specialized microprogrammed processor is shown with the external logic
which together is the entire disk controller.

In addition, the MCV is connected in such a manner as to perform command decoding, external
input testing, and one level subroutining.

upon exiting, a subroutine with a JPR instruction,
control can be returned to the procedure which
called it (Fig. 4). This technique saves a significant
amount of microcode in the BMDC because some
long sequences do not have to be repeated.

Command decoding is achieved by connecting
the command latch to the Primary Instruction (PX)
bus inputs and using the JPX instruction (Fig. 3).
The testing of external input signals is performed
by routing the least significant bit (LSB) of the
seven bit jump code through an eight-to-one multiplexer (Fig. 2). The mUltiplexer is controlled by a
3-bit Input Select Code which selects either the
LSB of the jump code or one of 7 external input
signals to be routed to the MCV. This technique
has the effect of conditionally modifying an unconditional jump code so that the next address will
either be an odd or even location (Fig. 3). A one
instruction wait for external signal loop can be
simply implemented in this fashion.

The microprogram control store is an array of
eight 360 I PROMs organized to give 256 words x
32 bits (230 words were required for the BMDC).
The 32-bit wide word is divided into the following
sub control fields:
I.
2.
3.
4.
5.
6.
7.

Jump Code field
Flag Control field
CPE Function field
Input Select field
Output Select field
Mask or Data field
Mask Control field
TOTAL

7 bits
2 bits
7 bits
3 bits
3 bits
8 bits
2 bits
32 bits

The command latch and data buffer retain command information from the computer so that the
memory bus will not be held up if the BMDC
should be busy performing an updating task. The
data buffer also retains the next data word during
a Write Data to disk operation.

One level subroutining is achieved by feeding the
four least significant bits of the address microprogram outputs back into the secondary instruction
(SX) inputs. Enough program status information
can then be saved in the internal PR latch when a
subroutine is called with a JPX instruction so that

3-11

Disk Controller Design
The CP array is connected in a ripple carry configuration as shown in Figure 5. The eight CPE
slices provide the BMDC with a l6-bit arithmetic,
logic and register section. Word to nibble serialization is made possible by connecting the Shift
Right Outputs (RO) of the first, third, fifth, and
seventh CPE to the Nibble Out bus. By using only
four shift right operations a word in a register can
be converted into four 4-bit nibbles. The final
serialization of these nibbles is done in the external

logic. Similarly, the Shift Right Inputs (LI) of the
second, fourth, sixth, and eighth CPE are connected
to the Nibble In bus so that with only four shift
right operations, a word can be assembled from
four nibbles.
COLUMN

o

,

2

3

4

5

6

1

8

9

10

11

12

13

1415

COLUMN

2

3

4

5

6

7

8

9

10

"

12

13

14

15

0

V" CALL
i

.... '

-!UBROUTlN~

CALL

CAL~

C

~
B

CAL~

ROW

(WAIT FOR EXTERNAL INPUT)

RET

,.

SHItWAlnlltAOVAlfVfOR.. AT
DAnOATAOATADATA
D"TA

..,

\
DESIGNATED
RETURN ROW

~

~
B"

r--

C.,

-

0"

"

ROW
(INSTRUCTION DECODING)

13

I

JCC

'--+-+H-CJNDITIION~L
BRANCH ON EXTERNAL INPUTS -t-t-+--i
r
USING JUMP CURRENT COLUMN (Jec) AND
JUMP CURRENT ROW (JeRI INSTRUCTION

1T

,,~t=~~=l~~JC3R~~~~~~~t=J==t=l~

Figure 4. MCU Jump Map for one level subroutine call and
return. A subroutine is called from four different
places in the program each with a unique column
number. Upon returning from the subroutine,
control will be transferred back to the portion of
program which called it. A subroutine may be
called from a maximum of 16 different places.

13

Figure 3. MCU Jump Map for instruction decoding and
conditional branching on external inputs

,

NIo
{, '.
•
NI IN
,--!r- CO CII--'-LI
RO I----

,

BBlE

ur

BBLE

4

1',

1',

{,

I

1

~~y-

~K

300'

,

L-L

-

r300'

I---

300'

-

,

,

---.l
I----

'r--

,

,

1

---.l

300'

,

,

,
,

-

,

{,

{,

{,

---.l

L.J..

-..l

r300'

'-

-

1-

:...-

--:r.T

Tz

,
,

,

,

,

{2'6

e-

BUS

CATA
OUTPUT
BUS

,~

CI - r- IN
_LI RO M-t,-K
n;-r
300'

CARRY

300'

.

I

I

, ,

16

-co

3002

l-

ADDRESS

,

"

,

I

I

,
,
01 DATA MUX

,
MASK CONTROL
FIELD

}.

DISK

DRIVE

co NOITIONS

DATA

, ,

16

INPUT
BUS

I

FIELD

Figure 5. CPE Array - A 16-bit arithmetic, logic and register section is built up with 8 CPE slices connected in a ripple carry
configuration. The K, I, and M bus is used for loading information into the CPE slices. The LI inputs and RO outputs
are connected to make up the Nibble In and Nibble Out buses.

3-12

Disk Controller Design
MCV chip via the carry out line. Finally, the eleven
scratch pad registers allow the controller to retain
data and status for the processor.

An eight bit mask bus is connected to the mask
inputs of the least significant half of the array. The
mask inputs of the most significant half of the CP
array are all tied to the eighth mask bit. A constant
with a value between +127 and -128 can therefore
be loaded into the array from the microprogram.
The mask bus comes from the data field of the
microprogram via a 0-1 data multiplexer. When the
CP array requires either an all one or all zero mask,
the data field is freed to provide data to external
logic.

The CP array in the microprocessor performs the
following for the BMDC with its registers and
arithmetic functions.
I.
2.
3.
4.
5.
6.
7.
8.

Sector counting
Word to nibble serialization
Drive seek status monitoring
Header checking
DMA address incrementing
Word counting
Multi-sector length counting
Automatic resynchronization of sector
counter
9. Accessing of additional information from
memory
10. Time delays

The 3002 CPE is an extremely flexible component which makes it particularly attractive for
controller designs. The Memory Address Register
makes an ideal DMA address register.(!) The accumulator (AC) register, which also has its own
output bus can be used as a data word buffer
during a write DMA cycle. Concurrently, another
word can be assembled in the T register using the
shift right operation. The three separate input buses
provide a mUltiplexing capability for routing different .data into the CPE. In the BMDC, the I-bus
is used for loading disk drive conditions, the K-bus
for loading mask or constant information, and the
M-bus for reading an external data buffer. The
arithmetic logic section performs zero detection
and bit testing with the result delivered to the

The organization of the microprocessor was
chosen to maximize the use of the MCV and CPE
in performing the various tasks required for disk
control. However, there are some specialized tasks
which are more economically performed by external logic. The microprocessor controls this external logic by output ports whiclr are selected by
the output select field in the microinstruction. The

EXT BUS RD

B~~!~~~LE

BUS
CONTROL II

I
I

DAT~EOT~~~RUN t-R!!:E'-:A='~~::":':':;'::::TE,-J

t--'-';6f:--_-i-C_______~------..:'+6_>--<--.1
t---,7A-----------t~----,._____+._=__........._ j
16

16

•

-

-

-

BIPOLAR LSI
MICROPROCESSOR

-

•
4

MEM ADO BUS
MEM DATA BUS
BUS INTERFACE

+DISK

DRive INTERFACE

CYLINDER ADD

I PLATTERHEAD SELECT
UNIT SELECT

WR GATE
NIBBLE OUT

t--f-..,

NIBBLE IN

t-,4---'

DISK
CABLE
DRIVER

3 I

;~T~~TL~NDER

I

OF DATA

OUTPUT PORTS

DISK DATA

FOR CONTROLLING

~

r;;t---J

TOP INDEX PULSE

~ BOTTOM INDEX

EXTERNAL LOGIC

INPUT PORT

I;;;-l

FOR TESTING
OR SVNCHRONIZING

~

~~

TO EXTERNAL LOGIC

L -_ _ _ _ _ _ _ _ _ _ _ _D_R_'V~E~C~0~ND~I_Tl~ON_S~/~8---------~I

PULSE
TOP SECTOR PULSE
BOTTOM SECTOR
PULSE

Figure 6. External Logic - Microprocessor monitors and controls external logic via input-output port to perform sPeCialized
disk controller functions.

3-13

Disk Controller Design
data to these ports is delivered from the shared data
field.
The external logic section of the BMDC (Fig. 6)
has a double buffered 4-bit shift register which is
used for initial packing and the final serialization
of data. It is controlled by a modulo-4 counter
circuit. During a write operation, serial data from
the shift register is encoded by the clock controlled
double frequency encoder and sent to the drive. As
data is being transferred to a cyclic redundancy code
(CRC) is generated and then appended to the end of
the data stream to be recorded on the disk. The external logic also contains addressing latches and
flag flip-flops to capture sector and index pUlses.
It also contains main memory bus·control circuitry
for performing bus protocol, bus acquisition, and
data overrun detection.

~-_

SET NOT HEADY flAG 80 AHORT

GET FROM MEMORY THE
HEADER. STARTING ADDRESS,
BLOCK LENGTH, & PASSWORD

SET PROGRAM ERROR FLAG 8. ABORT

The microprogram for the BMDC microprocessor
directly implements the six I/O commands. The
program controls the sequential action of the various elements of the microprocessor and of the
external logic needed to decode and execute the
commands. In Figure 7, the flow chart of the Read
command shows the actions required to read a file
off the disc. The BMDC first selects the drive specified by the command and checks its ready status.
It then uses a memory pointer passed to it by the
command to access four more words from the main
memory using DMA cycles. The first word is the
Header, which contains the track address and sector
address information. The second word is the Starting Address specifying the first location in memory
where the data is to be stored. The third word is the
Block Length of the file to be retrieved. All of the
address information and the Block Length are
stored in several CPE registers for further processing. The fourth word is the Password which is compared against a microprogram word to insure that
the command from the computer is a valid one and
not a program error. The password can prevent an
erroneous command, due to a user programming
error, from destroying important files on the disc.

' - - - - SET ADDRESS ERROR FLAG & ABORT

PACK NIBBLES TO FORM WORDS
INCREMENT MEM ADD COUNT

DECREMENT WORD COUNT
INITIALIZE CHANNEL OPERATION

CRITICAL
TIMING

lOOP

NO
SET OATA ERROR FLAG l!. ABORT

After the password check, the BMDC resynchronizes the sector counter if necessary and waits
for the desired sector by monitoring the sector
pulse flag. When the desired sector arrives, the
BMDC synchronizes itself to a start nibble and
reads the header which it compares to the desired
header to insure that the head is positioned
properly. It then reads and stores 128 words of
data at sequential locations in memory. A cyclic
redundancy code is compiled during the read oper-

YES
seT DONE flAG

Figure 7. Read Command Flowchart - This flowchart is
coded in the microprogram which when executed
performs the disk Read operation.

3·14

Disk Controller Design
ation and compared against the CRC word read in
after the data. At the end of each sector the block
length is decremented to see if it is the last sector.
If it is not, the sector address is incremented and
another sector is read.
In addition to the command routines, the microprogram has an idle loop routine (Fig. 8) which the
BMDC executes when it is not busy with a command. While in the loop, the BMDC updates the
sector count, monitors the drives seeks status lines
and decodes any disc commands from the disc
operating system in the minicomputer.
The design process for the BMDC began with an
evaluation of what disc controller operations could
effectively be handled by the microprocessor. This
also determined what had to be performed by
external logic. A microprocessor configuration was
then established and certain critical sequences were
programmed to verify that the configuration was
fast enough. A flow chart was produced and the
microprogram coded directly from it. All attempts
were made to use the MCU and CPE slices effectively and keep the microprogram within 256
words. The assignment of MCU addresses which
initially appeared difficult, was, with a little experience, quite straight forward and less restrictive
than a state counter design. After the coding, the
microprogram was assembled and loaded into the
microprocessor's control memory.
The BMDC design demonstrates how a specialized high speed microprocessor can be designed
using standard bipblar LSI devices and microprogrammed to perform disc control functions with
the addition of a small amount of external logic.
The flexibility of Series 3000 allows a designer
to optimize the configuration for his application.
For extremely high speed applications, the designer
can add fast carry logic and microinstruction pipelining to his microprocessor to achieve alSO nsec
16-bit microprocessor.
At Intel, our design experience with the BMDC
design exercise has shown that the use of the MCU
and CPE results in a clean, well structured design.
The complexity of the design resides primarily in
the microprogram leaving the external logic relatively simple. During debugging, most of the problems encountered were restricted to the microprogram which was easily modified and debugged
using l:)ipolar RAM for the control memory.
Figure 8. BMDC Flowchart - The BMDC runs in the idle
loop when it is not busy doing command processing.

References
I. J. Rattner, J. Cornet, M. E. Hoff, Jr., "Bipolar
LSI Computing Elements Usher In New Era of
Digital Design," ELECTRONICS, September 5,
1974, pp 89-96.

3·15

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CPU Design

Contents

Central Processor Designs
Using The Intel® Series 3000
Computing Elements
by
M.E. Hoff, Jr.,
James Sugg,
Ron Yara

INTRODUCTION .. . . . . . . . . . . . . . . . . . . . . . . . . ..
THE SERIES 3000 F AMILY . . . . . . . . . . . . . . . . . . ..
AN INTRODUCTION TO MICROPROGRAMMING..
CONSTRUCTING CENTRAL PROCESSING
UNITS .....................................
Basic Design Steps . . . . . . . . . . . . . . . . . . . . . . . . ..
Hardware Organization ......................
Writing of Microprograms .... . . . . . . . . . . . . . . ..
DEFINITION OF CONTROL FIELDS . . . . . . ..
ASSIGNMENT TO CONTROL MEMORY. . . . ..
PROGRAMMING TECHNIQUES . . . . . . . . . . ..
A DESIGN EXAMPLE ........................
Initial Specifications ........................
Macro-Instruction Decoding ..................
Microprogram Implementation. . . . . . . . . . . . . . ..
MEMORY REFERENCE AND
IMMEDIATE GROUP .....................
JUMP GROUP. . . . . . . . . . . . . . . . . . . . . . . . . ..
REGISTER MOVE AND SUBROUTINE
GROUP ................................
SPECIAL FUNCTION GROUP. . . . . . . . . . . . ..
INPUT/OUTPUT GROUP ..................
INTERRUPTS. . . . . . . . . . . . . . . . . . . . . . . . . ..
Microprogram Memory Assignment. . . . . . . . . . . ..
CONCLUSION ..............................
APPENDIX A - DESIGN EXAMPLE
INSTRUCTION SET. . . . . . . . . . . . . . . . . . . . . . . . ..
Memory Reference Group . . . . . . . . . . . . . . . . . . ..
Immediate Group ..........................
Jump Group ..............................
Subroutine Call Group. . . . . . . . . . . . . . . . . . . . . ..
Subroutine Return Group ........ . . . . . . . . . . ..
Register Manipulation Group. . . . . . . . . . . . . . . . ..
Byte Load and Store Group. . . . . . . . . . . . . . . . . ..
Special Memory Reference Instruction ..........
Base and Status Register Move Group . . . . . . . . . ..
Input/Output Group . . . . . . . . . . . . . . . . . . . . . . ..
Stack Push and Pop Group ...................
APPENDIX B - MICROPROGRAM LISTINGS . . . ..
APPENDIX C - CENTRAL PROCESSOR
SCHEMATIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3·19

3-21
3-21
3-21
3-23
3-23
3-23
3-26
3-26
3-27
3-28
3-29
3-30
3-33
3-34
3-34
3-43
3-46
3-49
3-52
3-52
3-53
3-58
3-62
3-62
3-62
3-63
3-63
3-64
3-64
3-64
3-64
3-64
3-64
3-64
3-65
3-76

CPU Design

INTRODUCTION
Unit (MCU) and the 3002 Central Processing Element (CPE). The MCU determines the sequence of
micro-instruction execution and controls carry /
shift data to and from the CPE array. The CPE
provides a complete two-bit wide slice through the
data processing section of a central processing unit.
CPEs may be arrayed in parallel to form a processor
of any desired word length. For example, to produce a l6-bit wide data path, eight CPEs would be
used.

Until recently, the area of high performance, general purpose and special purpose central processors
was unaffected by the microprocessor revolution.
Although they covered a broad range of applications, the P-channel and N-channel microprocessors' performance limitation prevented their use in
applications where high speed was necessary.
The introduction of the Series 3000 Computing
Elements has expanded the spectrum of microprocessor applications to include both high performance central processors and controllers. Utilizing Intel's Schottky bipolar technology, the Series
3000 components realized a level of performance
that was not possible with MaS microprocessors.
For example, a l6-bit processor with a microinstruction cycle time of 150 nanoseconds can be
built with the 3000 components. In addition, the
components of the family can be arranged into a
number of different configurations and microprogrammed by the system designer to perform in a
variety of processing environments from front end
processing to arithmetic intensive computation. I

All of the above components use standard TTL
logic levels, as some designers may wish to utilize
SSI and MSI TTL logic to control external circuitry, or to add functions not included in the
basic set to increase the speed of certain operations.
Other members of the family currently include the
following computing elements:
•
•
•
•
•

3003
3212
3214
3216
3226

Look-Ahead Carry Generator
Multi-Mode Latch Buffer
Interrupt Control Unit
Bidirectional Bus Driver
Inverting Bidirectional Bus Driver

This application note describes a systematic procedure for designing central processors with the Series
3000. Using a CPU design example, simple guidelines are given for tasks such as macro-instruction
opcode assignment, macro-instruction decoding and
execution and microprogram memory assignment.

The control and main memory portion of the
central processor may be implemented with any of
the standard bipolar or MaS memory components
shown on page 2.

THE SERIES 3000 F AMIL Y

AN INTRODUCTION TO
MICROPROGAMMING

The Intel® Series 3000 Bipolar Microcomputer Set
is a family of Schottky bipolar LSI computing elements which simplify the construction of microprogrammed central processors and device controllers. These processors and controllers are truly
microprogrammed in the sense that their control
functions are determined by the contents of a control memory. This control memory may be realized
with standard read-only (ROM) memory, read/
write (RAM) memory or programmable read-only
memory (PROM) elements.

The central processing unit of a general purpose
computer usually consists of two portions: an
arithmetic portion and a control portion. The control portion determines the sequence of instructions to be executed and presides over their fetching and execution while the arithmetic portion
performs arithmetic and logical operations.
The basic operation of the control portion consists
of selecting the next instruction from memory,
!hen executing a series of states based upon the
instruction fetched. This sequence may be implemented via a combination of flip-flop and random
logic, or by the use of tables in control memory.

The two most important computing elements in
the family are the 3001 Microprogram Control

I J. Rattner, J. Cornet, and M. E. Hoff, Jr., "Bipolar LSI Computing Elements Usher In New Era of Digital Design,"
ELECTRONICS, September 5, 1974, pp 89-96.

3-21

CPU Design

Standard Bipolar and MOS Memory Components
PART
NUMBER

NUMBER
OF PINS

DATA
ORGANIZATION

TECHNOLOGY

ACCESS
TIME

CONTROL MEMORY

3601

16

Bipolar PROM

256X4

70 nS'

3602

16

Bipolar PROM

512X4

70 nS

3604

24

Bipolar PROM

512X8

70 nS

3624

24

Bipolar PROM

512X8

70 nS

3301A

16

Bipolar ROM

256X4

45 nS

3302

16

Bipolar ROM

512X4

70 nS
70 nS

3304A

24

Bipolar ROM

512X8

3324A

24

Bipolar ROM

512X8

70 nS

3106A

16

Bipolar RAM

256X1

60 nS

3107A

16

Bipolar RAM

256X1

60 nS

256X8

1000 nS

MAIN MEMORY

1702A

24

Static MOS EPROM

2704

24

Static MOS EPROM

512X8

500 nS

2708

24

Static MOS EPROM

1024X8

500 nS
1000 nS

1302

24

Static MOS ROM

256X8

2308

24

Static MOS ROM

1024X8

500 nS

2316

24

Static MOS ROM

2048X8

850 nS

2101

22

Static MOS RAM

256X4

1000 nS'

2102

16

Static MOS RAM

1024X1

1000 nS'

2111

18

Static MOS RAM

256X4

1000 nS'

2112

16

Static MOS RAM

256X4

1000 nS'

2104

16

Dynamic MOS RAM

4096X1

2107B

22

Dynamic MOS RAM

4096X1

200 nS

5101

22

Static CMOS RAM

256X4

650 nS

*Higher speed versions of these devices are available. Consult the Intel Data Catalog.

When the latter technique is used, the central
processor is said to be microprogrammed.

memory. Each macro-instruction is then executed
as a series of micro-instructions. Main memory contains macroprograms, while control memory contains microprograms which define the realized
central processor.

The functions of the control portion of a microprogrammed central processing unit are very similar
to that of a central processing unit itself. To avoid
confusion, the terms "micro" and "macro" are
used to distinguish those operations in the control
unit from those of the realized central processorFor example, the central processor, under the
direction of micro-instructions read from its control memory, fetches macro-instructions from main

Figure I shows a block diagram of a microprogrammed central processing unit (defined by the
dotted boundary). The control unit issues addresses
to the control memory and fetches micro-instructions. This control unit uses the contents of control
memory (micro-instructions) to drive the data
processing unit, external circuits, and to select the
3-22

CPU Design
finds it necessary to alter or enhance the basic
macro-instruction set in some fashion. The tabular
or programming approach offered by the microprogrammed architecture makes such changes far
easier than would be possible in a processor realized
via hardwired logic.

EXTERNAL CONTROL
SIGNALS

r------1

1.----...,

DATA
PROCESSING
UNIT

1
1

IALU, REGISTERS.

1'---?O:~-'
1

1...-...,

1.--.........

I MAIN MEMORY
I (MACROPROGRAMSI

CONSTRUCTING CENTRAL PROCESSING
UNITS

BUS CONNECTIONS)

1

L----.,..~-' I1 L---::oo::--'

1

Basic Design Steps

1

1
I'--.....".,~-'

To realize a central processor with the Series 3000
computing elements, several steps are necessary:

1
1

1

1. Definition of hardware organization.
2. Definition of the central processor macroinstruction set.
3. Implementation of microprograms which realize
the desired macro-instruction set.

1
MACRO·INSTRUCTION
MACRO-I'l'STRUCTIONSIDATA
1
OPCODE
11.. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ...l
CENTRAL PROCESSING UNIT

Figure 1. Block Diagram - Microprogrammed
Computer

Hardware Organization
A typical CPU constructed utilizing the Series 3000
computing elements will consist of an array of CPE
chips, one MCU, and a control memory. The array
of CPE chips realizes the arithmetic, logical functions and registers of the CPU, while the combination of the MCU and control memory realizes the
control portion. The microprogram contained in
control memory initializes the machine when power
is first turned on and supervises the fetching and
execution of macro-level instructions. In addition,
routines to handle such special functions as interrupts will also be contained within the control
memory.

next micro-instruction. The data processing unit
performs the actual computations, logical operations, etc.
In the Intel® Bipolar Microcomputer set, the 3001
MCU performs the control unit function, while the
3002 CPE is the basic building block for the data
processing section.
Thus, within a microprogrammed machine, there
are at least two levels of control and two levels of
programming to be considered. The designer of a
central processor is usually concerned with the
definition of the macro-instruction set and its
realization as a microprogram. The Intel® Series
3000 Bipolar Microcomputer Set establishes a
micro-instruction set which is used as a base for the
microprograms which generate macro-instruction
sets.

The 3002 CPE array contains six buses for communication with external circuitry. Four of these
buses are used primarily to communicate with
memory and I/O devices while the remaining two,
the function control bus (F-Bus) and the control
memory data bus (K-Bus), enable the control portion of the processor to drive the CPE array. The
function control bus is driven by control memory
outputs which direct the CPE array to execute the
desired operation. The K-Bus allows the control
memory to supply various constants and/or masks
to the CPE array.

The reason for using this microprogrammed approach is that very complex macro-instruction
sets can be realized as sequences of relatively primitive micro-instructions. The logic of the final
macro-machine remains relatively simple, with most
of the design complexity residing in the microinstruction sequences contained in control memory.

Because 8 bits of operation code information can
be passed directly to the MCU, the set is best
adapted to macro-instruction sets in which all of
the operation code information is defined by 8 bits
(256 unique macro-instructions). However, larger
macro-instruction sets can be realized by saving any
remaining bits of the operation code in the CPE
array or in an external register. The saved bits can

The final user of the computer seldom needs to be
aware that the CPU was realized with microprograms rather than hardwired logic. A functional
description of the macro-instruction set is usually
sufficient for his purposes. However, the user will
benefit from the microprogrammed approach if he
3-23

CPU Design
then be tested later by routing them to the MCV,
through its 8-bit input port.

• The address bus (A-Bus) to main memory
• The data bus (D-Bus) to memory
• The data bus (M-Bus) from memory with its
path for operation code data to the MCU
• The external device input bus (I-Bus), not
shown
• The micro-function bus (F-Bus) from the
pipeline register
• The constant bus (K-Bus) from the pipeline
register

A "pipelined" mode of operation may be implemented by placing a register of edge triggered D
flip-flops between control memory outputs and the
circuitry controlled by those outputs. This register
causes the execution of a micro-instruction to overlap the fetching of the next micro-instruction. The
control lines which issue micro-instruction sequence
information to the MCV are not routed through
the pipeline register when the pipelined mode is
used; they are routed directly from the microprogram memory outputs to the ACO-AC6 inputs of
the MCV.

In addition, the carry logic bus to and from the
MCV and the micro-instruction sequence logic bus
from control memory to the MCV are shown. Ad-

ditional control fields to such external logic as
memory and I/O control are shown as an output
bus from control memory.

Microprograms written to realize a given macroinstruction set will differ for pipelined and nonpipe lined machines. The major differences are associated with conditional jumps in the microprogram
which test the results of arithmetic or logical operations executed by the CPE array. In a pipelined
machine, these results are delayed by one microinstruction, so that conditional jumps must be
delayed by at least one micro-instruction before
execution. More detailed information concerning
these differences is contained in the microprogramming section of this application note.

The number of bits required for each word of
control memory, i.e., each micro-instruction, is
determined by the number of logical functions the
micro-instruction controls. A minimum of 18 bits
is usually required for basic hardware control:
7 bits of micro-instruction sequence control to the
MCV, (ACO-AC6), 4 bits of carry control to the
MCV, (FCO-FC3), and 7 bits of micro-function
selection to the CPE array, (FO-F6). That is, the
basic hardware requires at least three control word
fields of 7 bits, 4 bits, and 7 bits width respectively.
Almost every processor will require additional
fields to control other logical functions such as
main memory control, I/O control, and constant
generation. Figure 3 illustrates a typical microinstruction word format with several typical user
defined control fields added.

Figure 2 shows block diagrams illustrating the
organization of standard and pipelined central
processing units. The block diagrams show the
basic modules of standard and pipelined CPVs:
the MCV, CPE array, microprogram memory and
the pipeline register. The six buses associated with
the CPE array are shown:

MEMORY ADDRESS

DATA BUSTO

BUS

MEMORY

CLOCK

CONTROL TO
MEMORY,IID

MEMORY ADDRESS

DATA IUS TO

IUS

MEMORY

CLOCK

DATA IN FROM MEMORY

DATA IN fROM MEMORY

Figure 2. Bipolar Microcomputer Non-Pipelined
Organization

Figure 2. Bipolar Microcomputer Pipelined
Organization

3-24

CPU Design
As an example of the use of additional logic to
enhance the set, consider the use of a control field
(I-bit width) to inhibit the CPE clock. This operation allows non-destructive testing of CPE registers
via the MCU carry logic. The carry logic in the
MCU responds just as if the micro-instruction were
executed, but the fact that the CPE clock was inhibited leaves the CPE registers unaltered. An example of conditional clocking is given in a later
section called "Programming Techniques."

The constant bus to the CPE array seldom needs to
be as wide as the data buses. For example, consider
a l6-bit machine where an array of eight CPEs is
used. While the constant bus is nominally 16 bits
wide, if a limited set of masking operations are
used, the number of bits can be reduced significantly. Figure 4 shows how 4 bits can be used to
generate the masks for such a machine where the
only masks needed are for separating high and low
order data bytes, for testing the sign and magnitude
of the data word, and for testing the least significant bit of the word.

MCU

CPE

CPE

MCU

MAIN
MEMORY

1/0
SYSTEM

Figure 3. General Micro-Instruction Format

co

LI
03
02o-----_4----_4--~----_+--~----~~

01 O-----------------------------------------4-__

~----~_4----~~_+

____

~

OOo-------------------------------------------------------------------------~

O.

03 02 01
!BINARV. LOW TRUE)
1

1
1

K·BUS
(HEXADECIMALI

1

• ••
•
•
• • • •
1

MASK FUNCTION

0000
0001

SELECT lse

•a

ooFF

SELECT LOW ORDER BYTE

1

FFOO

SELECT HIGH ORDER BYTE

1

1

7FFF
8000
FFFF

SELECT ENTIRE WORD

SELeCT WORD MAGNITUDE

SELECT WORD SIGN

Figure 4. Wiring the K-Bus Using 4-Bits

MICRO-INSTRUCTION WORD
CONDITIONAL CLOCKING
CONTROL BIT

---J=0,VCLETIME

MASTER
CLOCK

CONDITIONING

CO~~~~I:~

_____-J!

Figure 5. Conditional Clocking

3·25

CPU Design
Writing of Microprograms

Each symbol is associated with only one field, so
that the various symbols can be uniquely interpreted by the assembler. A number of symbols are
predefined for the assembler, and are not to be
used except as provided by the assembler. These
reserved symbols include the standard symbols for
the MCU and CPE functions, and a number of
directives to the assembler.

Once the hardware design is established and the
macro-instruction set chosen, the designer should
proceed to implement the microprograms for the
system. To assist in the writing of these microprograms, Intel has developed CROMIS, a complete
microprogramming system for Series 3000 computing elements.
CROMIS consists of two major software subsystems, XMAS and XMAP. XMAS is a symbolic
microassembler which is extensible in both microinstruction length and memory address space.
XMAP is a complementary subsystem which maps
the micro-instruction bit patterns produced by
XMAS into compatible ROM/PROM programming
files for use with standard memory components.

DEFINITION OF CONTROL FIELDS
Each control field added by the hardware designer
must be declared to the microprogram assembler.
In addition, each bit pattern to be assembled into a
word in the control field may be symbolically
designated. A FIELD definition statement in the
declaration part of the microprogram is used to
declare the field by name and define any states.

Programs written in the microassembly language
have two main parts, a declaration part in which
various aspects of the micro-instruction word are
defined and a specification part in which microinstruction contents are symbolically declared. Provision is made for comment statements throughout
the program so that the programmer may explain
the functions being performed.

As an example, let a 2-bit field be defined for
memory control. If the programmer wishes to
name this field MEMC, and define symbols for the
states with 0 I corresponding to READ, 10 corresponding to WRITE, and II signalling RMW (readmodify-write) and default to 00 if READ, WRITE
or RMW is not specified, the statement:

The main body of the program, the specification
part, defines the sequences of states to be executed,
and the operations which take place for each state.
The main effort in writing a microprogram will be
expended in developing this section.

MEMC

Each statement of the specification part of the
program defines the action (and location) of one
micro-instruction, i.e., one word of control memory. The statement will declare, either directly or
by default, the contents of each control field for
the specified micro-instruction. Furthermore, the
statement will include assignment information designating the address in control memory where the
statement is located.

MICROPS (REAO-01B, WRITE-lOB, RMW-l1BI

DEFAULT-ooB;

would perform the definition. The words FIELD,
MICROPS, LENGTH, and DEFAULT are directives
to the microprogram assembler.
Additional directives include IMPLY, STRING,
KBUS, and ADDRESS. The use of these words,
and other features of CROMIS are covered in the
Series 3000 Cross Microprogramming System Specification.

A specification statement consists of one or more
labels followed by a series of control field specifications. A colon after an entry indicates that it is a
label. The contents of the control fields are indicated symbolically, using either standard MCU or
CPE symbols or user-defined symbols, or by an
equation of the type

FNM

FIELD

LENGTH-2

A typical statement of the specification section
might take the form:

7BH:

IOIB

LAB:

ILRIR3)

FFO

STZ

JFllNC lei;

The number 7BH (hexadecimal) followed by a
colon tells the assembler that the micro-instruction
is assigned to row 7 column II of control memory
(when control memory is treated as an array of 32
rows and 16 columns). The symbolic label LAB

where FNM is a name associated with the field.
The entry 10lB implies the binary value 101.
3·26

CPU Design
3. Using the flowchart as a guide, perform the
assignment. In general, conditional jumps should
be assigned first, with clusters of conditional
jumps assigned before isolated jumps. Leave long
chains of unconditional sequences for last. The
process of assignment can be assisted by using a
diagram of the control memory showing the 32
rows and 16 columns. As each state is assigned,
the control memory diagram is marked to show
occupancy of that word and the flowchart
marked to show the assignment of the state.
With the assignment complete, the addresses are
copied from the memory diagram.

(the colon indicates a label) is also associated with
this location. ILR(R3) indicates that the contents
of register 3 are to be conditionally incremented
and copied to the AC register, while FFO forces the
carry input to a logic zero, so that the increment
operation does not take place. STZ indicates that
the Z flip-flop is to be set by the results, so that,
as no carry can result, the Z flip-flop will be set to
a logic zero. These symbols are standard symbols,
with ILR associated with the CPE and FFO and
STZ associated with the MCU carry logic. The JFL
tests the carry output line for a conditional jump
to either the statement labeled NC or to the statement labeled Te. JFL is also a standard symbol.
Note that, if the machine is pipelined, the conditional jump tests the results of the previous instruction, not of the present one. The semicolon indicates the end of the statement.

One other procedure in microprogram memory
assignment has been found to be useful. When the
control memory diagram is marked as each state is
assigned, it is helpful to include state linkage information in the diagram, i.e., memory location(s)
that reference the current location and memory
location(s) referenced by the current location.
With the additional information, micro-instruction
sequences can be easily traced on the control
memory diagram.

In the statement above, no information was provided for the K-Bus. It is assumed the assembler
will provide the appropriate default value associated with the ILR operation, i.e., the K-Bus at all
zeros.
The reader is referred to the Intel® Series 3000
Cross Microprogramming System Specification for
detailed information concerning CROMIS.

The state linkage information can be quite useful
when most of the microcode has been assigned and
only a few locations are left to assign the remaining
states. If reassignment of memory locations becomes necessary in order to assign the remaining
microcode, or modify the existing microcode, the
state linkage information will greatly simplify the
task.

ASSIGNMENT TO CONTROL MEMORY
The nature of the MCU next state address control
requires the programmer to assign control memory
locations to each micro-instruction. While this may
at first seem unfamiliar, it can usually be easily
accomplished if the following sequence is followed:

When reassignment becomes necessary, sequences
of unconditional micro-instructions should be considered first since they are the easiest to move.
Therefore, these types of states are useful to
annotate.

1. The microprogram should be written without
regard to address assignment. Then conditional
jumps are assigned using the basic conditional
jumps provided by the MCU (JFL, JCF, JZF,
JPR, JLL, JRL, JPX), noting the number of
possible destinations for the conditional jumps
chosen. When a sequence of instructions is to be
executed unconditionally and does not indicate
what jump codes will be used to advance to the
next state (unless the JCE enable feature is required), use the non-committal code JMP rather
than selecting a JCC, JZR or JCR.

In some cases, a particular sequence may be impossible to assign as written. For example, consider the
following section of microprogram:

r

ENTER WITH INSTRUCTION DISPLACEMENT "0" IN AC, SAVE AT R9 -,

175:

r

2. Prepare a state sequence flowchart for the program (see example, Figure 7). According to the
programmer's preference, this may be done before, during or after the actual writing of the
code. Label the conditional jump points on the
flowchart.
3·27

SQR(9) FFI .PX(MO,Ml, M2, M3. M4, MS, MS, M7, MS, M9, MA. MS, Me,
MD. ME. MFI;
ALSO TESTS HIGH 4 BITS OF MACRO-INSTRUCTION .,

r

MO- MACRO INSTRUCTION GROUP 1, FETCH R2 -,
128:

MO:

ILRIR21

FFO

129

Ml:

ILRIR3}

FFO;

M1P;

ADRIR91

FFO;

JMP(M1PI:

CPU Design
1. Forcing a fixed address to access a predetermined
location in memory or to select a specific I/O
device. (Also may be used to load literals.)

"

MIP

M2

I I: D
M3 I M41·:"G

ClRtN)
LMIIN)

The first operation clears the register selected by
N, while the second loads the logical OR of the
contents of N and the contents of the K-Bus to
the memory address register (MAR) of the CPE
array and into register N. DESAD is a symbol
for the desired address value previously defined
by the programmer. The pair of micro-ops above
may also be used to set any register to any
desired constant, although the contents of the
MAR are destroyed.

ROWp

Figure 6. Operation MIP Can Be Reached From
Both MO and M1 by Locating MIP in
Row 0 or Duplicating it in Both
Column 0 and Column 1

In the above example, MIP follows both MO and
M1. Since the row in which MO and MI reside is
completely filled, MIP must be located in row zero
(because the JZR jump operation allows a location
in row zero to be reached from anywhere in memory). If row zero were already fully occupied, the
assignment could not be made. However, in this
case the state represented by MIP might be duplicated so that it can be reached from state MO and
M1. No extra execution time is added by this
modification, although one more memory location
is used.
When assigning
should be used
cause only they
in the program

KB"OESAD;

2. Any register may be set to all I's by the operation
CSR(N)

FFO

3. A value read from memory or I/O into the AC
may be split into bytes and stored in another
register as follows:
SOR{N)

FFl

KFFOO;

f" STORE RIGHT BYTE IN REG N • /

SORIAe)

FFl

KOOFF;

r

SET lEFT BYTE OF ACTOZERQ ./

where KFFOO is a symbol which causes the KBus to be set to IIII IIII 0000 0000 in binary,
and KOOFF is a symbol for setting the K-Bus to
0000 0000 II1I 1I1I in binary. The high order
byte is placed in the upper byte of register N
while the low order byte remains in the low
position of the AC. The low byte of register N
and high byte of the AC are cleared.

to memory, row zero locations
judiciously, but not sparingly, becan be reached from anywhere else
using a single JZR jump function.

Finally, in a 512-word microprogram memory
there are 64 possible destination pairs for the JCF,
JZF and JFL conditional jump functions, since all
three use columns 2 and 3 or columns 10 and II as
their jump target. It is therefore important to
insure that enough destination pairs are available
for the conditional jumps used in a microprogram.

4. Sign Testing and Absolute Magnitude - To test
sign bits most effectively, an inhibit operation at
the CPE clock is very desirable. In the following
examples the symbol INH implies a signal from
the control memory to inhibit the CPE clock.
This prevents modification of the AC register.

PROGRAMMING TECHNIQUES

The operations

Because of the flexibility of both the micro-operations and the architecture of the Series 3000 computing elements, a number of programming "tricks"
can be used to implement a desired operation. As
the programmer becomes more familiar with the
set, he will find new ways to perform different
functions. The list of operations given here are
intended as examples. In general, the labels indicating assignments to memory are not shown. In
all of the examples, KB is the name associated with
the K-Bus field of the micro-instruction. Statements bounded by /* ... * / are comments and do
not affect the assembly.

TZAtAC)
AN:

K8000

INH

JFl(AP,AN);

CtA(AC)

AP:

generate the absolute magnitude of AC in AC
for the non-pipelined case (note K8000 implies
1000 0000 0000 0000 on the K-Bus) while
TZR(AC)
NOP
AN:

KSOOO

INH
JFLiAP,ANI;

CIA(ACI

AP:

performs the same operation for the pipelined
case.

3·28

CPU Design

r

When two numbers in AC and T must be converted to positive numbers and the signs saved,
as well as the sign of the product, the following
routine may be used for a pipelined machine.

CL

Mel+1

Mel +:~

/' ENTER WITH VALUES IN T,AC "
,"

fiRST CLEAR SIGN AREA

MCl+J

REGISTER 9 FOR THIS EXAMPLE 'f

CLR(R91.

MLP

"NEXT TEST SIGNS OF AC. THEN T "
K8000

TZRIACI

INH.

TlRm

r

JfL(AP,ANI:

LMI(R91

K8000

CIA(ACI

«000

LMHR91

M8'~~--------~'---~
JFL

TEST AC SIGN SIT "

,'TESTTSIGNBIT "

JFL(TP,TNI.

I" SET HIGH AND LOW ORDER BIT "

JFL(TP,TN).

"

COMPLEMENT AC "

JMP(NXOPI:

r

SET BIT 15 'f

M81+1

M81+2

o-________-to~"'M8::::Z~>=JZ"'F

,. COMPLEMENT T 'f

ClAm.

MEX

Figure 7. State Sequence Flow Diagram Multiply Loop

Upon reaching label NXOP, both AC and T will
contain positive numbers (high order bit = 0)
and register 9 will contain a I in the high order
bit if and only if AC was originally positive, a I
in the second bit from the top if and only if T
was originally positive, and a zero in the low
order bit if and only if the signs were the same.
A one will appear in the second lowest order bit
if and only if both numbers were originally
positive. Execution of the sequence takes 5
micro-instruction cyeles.

ROW 10

CSRIRBI

1(0000.

"SET R8TOFFFF HEX'

TZFHR81

KFFFO.

/' SET R8TOFFFOHEX •

!" CLEAR PARTIAL PRODUCT lAC) "
ClRIACI.
/' fETCH AND TEST MULTIPLIER LOWQAOER BIT "
SRA(TI;

" MAIN LOOP - EXECUTE MULTIPLIER BIT TEST, ADD IF NECESSARY',
MLP:

LMUR81

FF 1

STZ

SDRIRll

FFI

,. SAVE AC IN REGl "

JFLIMBZ.MBll.

,. INCREMENT LOOP COUNTER SAVE IN Z .,

ILR(R91

FFO.

I" PLACE MULTIPLICAND. R9.IN AC "

ALR(R7I

FFO

r

" A.oD SEQUENCE "
MBI'

ADO MULTIPLICAND TO PARTIAL PRODUCT ./

" NOW ROTATE. THEN TEST LOOP COUNT - SAveD IN Z .,
,'NOTE

r

COL
2

COL
3

COL
4

COL
5

MCl

.,

MlP

MEX

MCl

MCl

'2

'3

MB'

MBZ

MB,

,

MB1

Because MLP and MEX are the two destinations
of a JZF jump function, they must be in the
same row, in columns two and three respectively
or in columns 10 and II respectively. Since MLP
executes a lFL to MBZ, MBI, then MBZ and
MBI must be in the same pair of columns as
MLP and MEX. For the example, rows 9 and 10
were chosen, and columns 2 and 3, and the four
states MLP, MEX, MBZ, MBI are assigned first.
Next the states following MBL (indicated by
MBI+I and MBI+2) and MBZ are assigned. As
all of these jumps are unconditional, the operations lCC, lCR, and lZR are used. As the lZR
is usually reserved for entry to commonly used
routines, only the JCC and JCR jumps are used
here.

SET UP LOOP COUNTER 'f
MGl

COL

MCl

Figure 8. An Assignment of the Multiply Loop
to Control Memory

5. Pipelined Multiply - Assume that AC and T
represent the partial product and multiplier
respectively, while register 9 contains the multiplicand and register 8 will be used as a loop
counter. Register 7 is used for temporary storage. It is assumed that both numbers are positive.
r

COL

o

ROW 9

PIPELINE ALLOWS USE OF Z FOR SHIFT BIT PROPAGATION '/

To demonstrate the techniques introduced above,
a central processing unit design cycle will be carried
through from initial specification to final microprogram memory assignment.

NOTE THE SoRIR7I. ILRIR91. AND ALRIR11 MICRO-INSTRUCTIONS CAN BE
REPLA.CEo WITH AN A¥A MICRO·INSTRUCTION ELIMINATING Z INSTRUCTIONS
FROM THE INNER LOOP IF OATA IS LATCHEO ON THE M BUS .,
SRAIACI

FFOSTZ.

I' SHIFT PARTIAL PRODUCT. SAVE LSB .,

SRAtTI

FFZ JZFIMLP.MEXI.

I' Z TEST IF OF LOOP CDUNTI "

MEX:

Note that the pipeline causes the lZF (or a lCF)
to test the contents of the flip-flop as set two or
more instructions earlier.
A state sequence flow diagram for the multiply
sequence might be drawn as shown in Figure 7.
Note that in Figure 7, each symbolically labeled
state is noted, and each conditional jump is indicated and the conditions corresponding to each
jump are noted. A flowchart like that of Figure
7 contains sufficient information to perform the
assignment to memory. An assignment might be
as shown in Figure 8.

A DESIGN EXAMPLE
The following design example illustrates some of
the basic techniques which may be used in developing a central processor with the Intel® Series 3000
Bipolar Microcomputer Set. The basic design sequence consists of stating the machine objectives,
then designing the hardware configuration and
microprograms. For this example, it is assumed
that the designer has the freedom to specify operation code assignments, and to modify the instruction set to take greatest advantage of the chip set's
capabilities.

3-29

CPU Design
Initial Specifications

P register with the starting address of the
routine. Similarly, a return instruction restores
the appropriate registers. Some jumps may
also be conditional, checking the status of the
C flip-flop, or the sign or magnitude of the A
register.

Let the following list of design objectives represent
the initial specifications for a central processor
instruction set.
I. The machine should use a 16-bit data path,
with instructions containing an opcode portion and a data or displacement portion.

8. Additional operations may involve manipulations of data in the A and X registers and the
ability to move data between the X and the
W, B, E or S registers.

2. Machine registers should include a program
counter, P, a stack pointer, S, an accumulator,
A, an index register, X, and two base registers,
Band E. B is a base register for data and E is
a base register for program. In -addition, a
carry flip-flop may be a bit in the status word,

W.
3. References to memory for data should be
relative to the B register, using the displacement portion of the instruction (designated
D). Memory reference modes include direct
(Address=B+D), indirect (address equals the
contents of B+D), and indirect indexed (address equals the value given by the sum of X
and the contents of the word at address B+D).
Indirect and indirect-indexed modes should
include both absolute and B relative (Le., the
address is relative to the contents of the B
register) forms so that indirections may be
computed both at time of assembly and during prog~am execution.
4. Memory reference instructions include: load
address to A, load data to A, AND data to A,
OR data to A, XOR data to A, add data to A,
subtract data from A, push address to stack,
push data to stack, store A at computed
address, pop stack to computed address, load
address to X, load data to X, add data to X,
subtract data from X, store X at computed
address (operations involving X may not need
to implement indirect-indexed modes).
5. Immediate instructions using the displacement
portion of the instruction as the data, include,
load A, load X, add to A, add to X. A two
word "load immediate" instruction may also
be implemented.
6. Jump instructions include a short relative
jump (Address=P+D-K, where K is a constant), an indirect jump to an address relative
to the E base register, and an indirect call
operation.
7. The call (to a subroutine) operation saves the
P, E, B, and W registers (global call), or the P
register (local call) on the stack and loads the

9. Byte load and store operations should include
automatic packing and unpacking of bytes in
a 16-bit memory location.
10. Input/output instructions should use either
the displacement or the X register to specify
the I/O device address.
In addition to the definition of the macro-instruction set, the designer should also prepare descriptions of the initialization operations (Le., at "power
on") and interrupt handling to be used. For this
machine, let it be considered necessary for the
machine to start at power up with W, A, and X
cleared and for S to be set to the contents of word
0, B to be set to the contents of word 1 of memory, E set to the contents of word 2, and P set to
the contents of the memory location pointed to
by E.
Let I/O device 0 represent a source of interrupt
level information (level requesting in) and a destination for current level out, consistent with the use
of the 3214 Interrupt Control chip. In addition,
let the low order bits of W contain current interrupt level information.
When servicing an interrupt, the processor will
execute a jump to subroutine which will reload P
and E while saving all registers except S on the
stack. The service routine will interrogate the interrupt hardware to determine the level of the request
and will restore former status upon exit from the
interrupt program. For this purpose, a return and
restore status instruction will be provided.
In parallel with the specification of the design
objectives, a first pass at the CPU's architecture can
be made. The block diagram in Figure 9 shows a
general CPU architecture as defined in the initial
specification above.
The design example machine uses a pipelined
architecture and includes a control structure which
implements eight basic memory bus and clock
operations. A 3-bit field is used to control this
structure. The states for this field are designated

3-30

CPU Design

\

MEMORY 8. I 0 ADDRESS BUS

\

BIDIRECTIONAL DATA BUS

\

CONTROL BUS

---------------,
3002 CPE ARRAY

AC REGISTER

I I

MAR

ARITHMETlC:LOGIC

UNIT
P[AFOIl.MSADDf:lESSCALCU

I

I

'MEMORY AND I 0
BUS CONTROL

IMSISSI!

I " " - - - - - - - - r - - - - - - - - - - - - I MICROPROGRAM
MEMORY
1\,-_ _ _ _--,

(ROMS PROMSr

LATIONS AND AHITHMETIC

lOGIC OPERATIONS UNDER
CONTROL OF THE MICRO
PROGRAM

r--------------- - -------1

-H'
I

REGISTER FILE
X _ INDEX REGISTER (RlI

W - STATUS REGistER IR11
B
E
P
S

3001 MCU

I

A - ACCUMULATOR 11'101
- BASE REGISTER, DATA (1'151
- BASE REGISTER, PROGRAMIR61
- PROGRAM COUNTER IR31
- STACK POINTER IR41
MICROPROGRAM WORKING

I
I

,

I

SHIFT CARRY

MICROPROGRAM

LOGIC

CONTROL UNIT

SEQUENCE

I

I

IL _________________ _

REGISTERS RB. 1'19, T

,,
L _____________________________

~

OPCQDE FIELD

Figure 9. Block Diagram of CPU Architecture

stack pointer and a push decrementing it. This
direction is preferred, as it leaves the stack pointer
pointing at the topmost entry in the stack. In
addition, pops usually appear more often than
pushes (pushes share code), and the increment
operation requires fewer micro-instructions.

NBO (No Bus Operation), INH (Inhibit CPE Clock),
CNB (CPE uses bus), RMW (read modify write
signal to memory - starts a read cycle and prevents
release of bus until the CPU executes a write cycle),
RRM (Request read cycle from memory), RWM
(Request write to memory), RIN (Request input
from an I/O device), and ROT (Request an output
to an I/O device).

The designer must select the actual instructions to
be used. Let the instructions and their associated
mnemonics shown in Table I be selected in the first
design pass.

The stack has been designed to run "backwards"
through memory, with a pop incrementing the

:j:.31

CPU Design
Table I. Proposed Instruction Set
MEMORY REFERENCE GROUP
MNEMONIC

JUMP GROUP (continued)

FUNCTION

MNEMONIC
RELATIVE
INDIRECT

FUNCTION

LAA

Load address to A

LDA

Load data to A

JRCZ

JICZ

Jump if C=O

ADA

Add data to A

JRXL

JIXL

Jump if X';;;A

SDA

Subtract data from A

JRLE

JILE

Jump if A';;;O

AND data to A

JRGT

JIGT

Jump if A>O

ODA

OR data to A

JRCN

JICN

Jump ifC*O

XDA

Exclusive OR data to A

JRXE

JIXE

Jump if X=A

NDA

PAS

Jump relative:
Jump indirect:

Push address to stack

PDS

Push data to stack

SAM

Store A into memory

PSM

Pop stack into memory

LAX

Load add ress to X

P=P+D-128
P=(E+D)+E

STACK PUSH AND POP GROUP
MNEMONIC

FUNCTION

LDX

Load data to X

PHAX

Push A and X onto stack

ADX

Add data to X

PPAX

Pop A and X from top of stack

SDX

Subtract data from X

SXM

Store X in memory

SPECIAL MEMORY REFERENCE INSTRUCTION
MNEMONIC

IMMEDIATE GROUP
MNEMONIC

ISZ

FUNCTION

LAI

I ncrement location B+D and skip if zero
SUBROUTINE CALL GROUP

Load to A immediate

AAI

Add to A immediate

NAI

AND to A immediate

OAI

OR to A immediate

XAI

Exclusive OR to A immediate

PSI

Push to stack immediate

LXI

Load to X immediate

AXI

Add to X immediate

MNEMONIC

FUNCTION

CLS

Call local subroutine, push P onto stack
P=E+(E+D)

CVS

Call value subroutine, push W, B, E, P
onto stack
E=E+(E+D)
P=E'+(E')

CAS

Call absolute subroutine, push W. B. E, P
onto stack
P=(D)

where E'=E+(E+D)

If D is equal to zero, the contents of the memory location
following the instruction is used as the immediate value.
JUMP GROUP
MNEMONIC
RELATIVE
INDIRECT

FUNCTION

SUBROUTINE RETURN GROUP
FUNCTION
MNEMONIC

JRU

JIU

Jump unconditional

JRGE

JIGE

Jump if A;;'O

JRLT

JILT

Jump if AA

JREZ

JIEZ

Jump if A=O

JRNZ

JINZ

Jump if A*O

3-32

FUNCTION

RLS

Return from local subroutine, pop P from
stack

RVS

Return from value subroutine, pop P, E,
B, W from stack

RSA

Return from subroutine, restore all, pop
A, X, P, E, B, W from stack

CPU Design
Table I. Proposed Instruction Set (continued)
BYTE LOAD AND STORE GROUP
MNEMONIC

INPUT/OUTPUT GROUP

FUNCTION

MNEMONIC

FUNCTION

LBA

Load byte absolute

IND

Input one word to the A register

LBR

Load byte relative

OTO

Output one word from the A register

SBA

Store byte absol ute

SBR

Store byte relative

Absolute mode:
Relative mode:

D serves as the address for the I/O port.

Byte address = (B+D)+X12
Byte address = (B+D)+B+X12

Input one word to the A register

OTX

Output one word from the A register

The X register provides the address for the I/O port.

The least significant bit of the X register is treated as the
byte pointer in main memory as follows:
X Reg. LSB = 0
= 1

INX

Given the basic design objectives, the next step is
to write the sequences of micro-instructions to implement the macro-instruction described above.
Each macro-instruction must be assigned a unique
operation code. The operation code (opcode) will
be used by the 300 I MCV to generate the appropriate address for the micro-instruction which executes that macro-instruction.

the left or high order byte is selected
the right or low order byte is selected

For load operations, the selected byte is loaded into the
right byte position of the A register and the left byte is
cleared. For store operations, the right byte of the A regis·
ter is stored at the selected byte location leaving the un·
selected byte of the word unaltered.

Macro-Instruction Decoding
To take full advantage of the 3001 MCV's eight
input lines (SXO-3, PX4-7) for instruction decoding, all macro-instruction operations should be
completely specified in an 8-bit opcode field and
use the remaining 8 bits for displacement values.
In Figure 10 the 8-bit opcode of a macro-instruction being read in on the memory data bus is gated
directly to the 3001 MCV. While the displacement
is being stored in the CPE array, a JPX operation is

REGISTER MANIPULATION GROUP
MNEMONIC

FUNCTION

RAR

Rotate A right, include CF F

RAX

Rotate A and X right, include CFF

SAX

Shift A and X right, preserve sign

SAL

Shift A left, fill with zeros

The shift count is given by D if D is non· zero or by the
least significant seven bits of the X register if D is zero.

300'

Meu

300'

I'PR1

CPE ARRAY

~
SXO-l

OPCODE FIELD

BASE AND STATUS REGISTER MOVE GROUP
MNEMONIC

FUNCTION
MEMORY DATA
INPUT BUS

MSX

Move S to X, adjust

MBX

Move B to X, adjust

MEX

Move E to X, adjust

MWX

Move W to X, adjust

MXS

Move X to S, adjust

MXB

Move X to B, adjust

MXE

Move X to E, adjust

MXW

Move X to W, adjust

Figure 10, Macro-Instruction Decoding with
the 3001
executed by the 300 I. The JPX operation executes
a 16 way branch based on the 4 bits of the PX lines
and also stores the 4 bits on the SX lines in the PR
latches for later decoding. For best microcode
efficiency then, the opcode field should be arranged
in such a manner that the first 4 bits tested (by the
JPX operation) select the initial processing (usually
an address calculation) of the macro-instruction. A
possible instruction format is shown in Figure II.

The destination register is adjusted by D-128 (i.e., D-128
is added to the destination register).

3-33

CPU Design
15 14 13 12 11 10 9 8
I
I
I
I
I
I

I

I

ADDRESS
MODE

I

7

6
I

OPERATION
MODE

5
I

4
I

3
I

2
I

1
I

0
I

In addition to the initial address mode processing
input/output, register to register, and other special
function operations can be specified in the first 4
bits, as shown in Table III.

I

DISPLACEMENT

Figure 11. possible Macro-Instruction Format
In the case of the CPU design example, the initial
processing involves address calculations and/or
operand fetching. Table II contains the initial
processing modes for the design example.

Microprogram Implementation
Having assigned the first 4 bits of the macroinstruction operation code, the next 4 may be
tentatively assigned. These 4 bits will have different
meanings for different instruction classes. To improve microcode efficiency it is desirable to share
as much code as possible between different microprogram segments. For example, the ADA and AAI
instructions might share the add operation once the
data has been fetched.

Table II. Memory Modes
In the description below, the letters A, X, B, S, P, W, and E
represent the contents of the respective registers. 0 represents the 8-bit displacement treated as a positive number
ranging from 0 to 255. 0' represents 0-128. ( ) are used to
designate contents of memory. For example, (B+O) means
the contents of the memory location whose address is equal
to the sum of the contents of B and the displacement O. It
is assumed that, when the instruction is fetched, P is incremented prior to instruction execution.

MEMORY REFERENCE AND IMMEDIATE
GROUP
The assignment shown in Table IV might be used
for the memory reference and immediate group
instructions. The clustering has been chosen in a
way that should allow JPR and JLL and JRL
micro-operations to be used effectively and to
allow code sharing between the two groups.

MEMORY REFERENCE MODES
1.

Direct: Address = B+O

2.

Indirect: Address = (B+O)

3.

Indirect relative: Address = (B+O)+B

4.

Indirect indexed: Address = (B+O)+X

5.

Indirect indexed relative: Address = (B+O)+B+X

An initial flowchart for the memory reference and
immediate group instructions is shown in Figure
12. In the flowchart, the boxes indicate the operations performed. The appropriate jump operations
(JPX, JLL and JRL) are indicated along with the
bit patterns that select each box.

IMMEDIATE MODES
6.

If 0*0, Data = 0-128

It is possible that when the actual code for the
sequence is written, some improvements in efficiency may still be made_ In addition, some of the
boxes shown as dummies may be eliminated by
suitable placement of the JLL and JRL instructions.

If 0=0, Data = (P), P=P+l
JUMP MODES
7.

Jump relative: P=P+0-128

8.

Jump indirect: P=(E+O)+E

g.

Call relativ\!: P=(E+O)+E

10.

Knowledge of the MCU assignment restrictions
may also influence some choices here. For example,
the MCU provides twice as many possible JLL
jump destinations as JRL jump destinations, while
the sequence shown uses twice as many JRLs as
JLLs. As a result, an easier assignment might be
obtained if the JLLs and JRLs were exchanged,
which is equivalent to a reassignment of the macrooperation codes.

Call indirect: P=E'+(E') where E'=E+(E+O)
REGISTER MODE

11.

Fetch source register

Using the instruction format shown in Figure 11,
the high order 4 bits (bits 12 to 15) will be used to
select one of the modes listed in Table II. Thus, by
executing a JPX operation, a 16 way branch on the
PXQ-PX3 bus can be performed to determine the
address mode specified. At the same time the SX
bus bits (the Operation Code field) will be stored
in the PR latches for later use. A possible assignment of the first 4 bits (bits 12 through 15) might
be as shown in Table III.

Also, recognizing that the MCU's JCC type jump
facilitates jumping from one JLL destination to
another, it is desirable to assign the macro-operation codes so that operations which share final
segments are aligned in columns. For example, the
SDA instruction would typically be achieved by
complementing the data, then adding it to A,
which may share the code for ADA. As a result, a

3-34

CPU Design
Table III. Mode Bit Assignments
ADDRESS MODE
BITS

INITIAL PROCESS

MODE

0000

No operation

0001

Jump relative

P+D'

0010

Jumps (index, etc.)

(E+D)+E

0011

Immediate

D' or (P)

0100

Direct memory reference

B+D

0101

Indirect memory reference

(B+D)

0110

I ndirect index

(B+D)+X

0111

Indirect index relative

(B+D)+X+B

1000

I/O input

D->MAR

1001

I/O input

X->MAR

1010

I/O output

D->MAR

1011

I/O output

X->MAR

1100

Move group

1101

Special function group

1110

Indirect relative memory reference

1111

No operation

OP FIELD
BITS

MEMORY
REFERENCE
FUNCTION

IMMEDIATE
FUNCTION

0000

ADA

AAI

0001

ADX

AXI

0010

NDA

NAI

0011

ODA

OAI

0100

LDA

LAI

0101

LOX

LXI

0110

PDS

PSI

0111

XDA

XAI

1000

LAA

1001

LAX
PAS

1011

SDA

1100

SAM

1101

SXM

1110

PSM

1111

SDX

Condition testing

LAI, AAI, etc.

LAA, LDA, etc.

Shift A

Table IV. Memory Reference and Immediate
Op Code Assignment

1010

SUBSEOUENT PROCESSING

(B+D)+B

better assignment of opcodes might be achieved by
placing ADA and SDA in the same column. For
example, see the assignment shown in Table V.
Table V also assumes exchange of the JLL and JRL
instructions.
Table V. Modified Memory Reference Op Code
Assignments
0000 = NDA

0100 = ODA

1000 = XDA

0001 = LDA

0101 = LDX

1001 = PDS

1100 = ADA
1101 = ADX

0010=LAA

0110=LAX

1010=PAS

1110=SDA

0011 = SAM

0111 =SXM

1011 =PSM

1111 =SDX

Except for those considerations mentioned above,
the code is most easily written without regard to
memory assignment. Also, it is assumed that reassignments of macro-operations codes are made
when efficiency can be improved.
Let the CPE register assignments be made as shown
in Table VI.
The code which follows represents the specification
portion of the microprogram in which the various
fields are identified, and symbols defined.

3-35

CPU Design

fETCH

FeTCH

FETCH

FeTCH

JRL
JRL

FETCH

FETCH

FETCH

FETCH

FETCH

FETCH

FETCH

FETCH

JRL

JRL

FETCH

FETCH

FETCH

FETCH

Figure 12. First Pass of Memory Reference Group Flowchart

/* BIPOLAR MICROCOMPUTER MACRO-MACHINE
REGISTER MACHINE- -12/13/74
UPDATED 3/18/75
MACHINE HAS 7 REGISTERS AS FOLLOWS:
A
ACCUMULATOR
RD
X
INDEX REGISTER
R1
P
PROGRAM COUNTER
R3
S
STACK POINTER
R4
B
DATA BASE REG
R5
E
PROG_ BASE REG.
R6
W
STATUS WORD
R7
C=CARRY,LlNK FLiP-FLOP=HOB OF W
DEFINITION OF KBUS FIELD *1

3-36

CPU Design
FIELD
LENGTH=4
M ICROPS( KOOOO=O
K8000=8
KBUS;

KB

KB

DEFAULT=O
K007F=1
KOOOFF=3
K7FFF=7
KFFOO=12
KFF80=14
KFFFF=15);

/* DEFINITION OF BUS CONTROL FIELD *f
FIELD
LENGTH=3
MICROPS(NBO=OOOB
RIN=100B

MCF

/*

DEFAULT=O
INH=OOlB
RMW=010B
ROT=101B
RRM=110B

CNB=OllB
RWM=lllB);

NBO
NO BUS OPERATION
INHIBIT CPE ARRAY
READ-MODIFY-WRITE
CPU NEEDS BUS
REQUEST INPUT
REQUEST OUTPUT
REQUEST READ MEM.
REQUEST WRITE MEM.

INH
RMW
CNB
RIN
ROT
RRM
RWM

SET UP FOR SYMBOLIC REPRESENTATION OF REGISTER DESIGNATIONS *j

A
X
P
S
B
E
W

/*

STRING
STRING
STRING
STRING
STRING
STRING
STRING

'RO';
'Rl';
'R3';
'R4';
'R5';
'R6';
'R7';

SET UP A SPECIAL NO.OP STRING *f

NO.OP

STRING

'NOP(R3)';

/* NEXT WE SPECIFY A DEFAULT TO FFl IN THE FO FIELD FOR THE SDR
MICROP IN THE CPE FIELD. SDR IS NORMALLY USED AS A STORE
OPERATION. WHEN A DECREMENT OPERATION IS ALSO DESIRED, FFO
WILL HAVE TO BE EXPLICITLY SPECIFIED */
SDR

IMPLY

FO=llB;

Table VI. Register Assignments
RO = A
Rl =

X

R3 = P
R4 = S
R5 =

B

R6 = E
R7 = W (C is high order bit of W)

The next portion of the code represents the machine initialization (in which registers are set to
initial values during power up), and the memory
reference and immediate group of instructions. The

elementary flowchart followed is that of Figure 13,
reflecting the reassignment shown in Table V.
A number of programming "tricks" can be found
in the microcode. For example, the C flag of the
MCU (not to be confused with the C flip-flop of
the macro machine) is set each time the machine
executes a fetch instruction by the SDR microoperation. SDR adds 111 ... 1 to the AC (as masked
by the K-Bus) so that whenever the carry input of
the CPE array is a I, the masked AC register will be
stored unchanged into the designated register, and
the carry output of the CPE array will be I.
Similarly, a ILR micro-operation (KBUS = 0) with
a carry-in of zero never generates a carry, so that it
can be used to clear the C flag if so desired.

3-37

CPU Design

FETCH

FETCH

FETCH

FETCH
JLL
JLL

FETCH

FETCH

FETCH

FETCH

FETCH

FETCH

FETCH

FETCH

FETCH

FETCH

FETCH

FETCH

JLL

JLL

Figure 13. Second Pass of Memory Reference Group Flowchart

The C flag is used to implement a type of microcode subroutine where code is shared by two
"calling" routines, one which leaves the C flag
unchanged and the other which clears it. Upon exit
from the shared code sequence, the C flag is tested
giving a unique exit for each of the two calling
routines (see Figure 14).
The inhibit operation, indicated by the "INH"
micro-operation, inhibits the clock to the CPE
array. For these operations the carry function and
conditional jump results are the same as if the operation were executed. However, none of the CPE
registers are altered when the clock is inhibited.

Figure 14. Microcode Subroutine Using the C-Flag
to Determine Exit

3-38

CPU Design
The result is a number of "compare" or test
micro-operations.

As an example of this situation, consider the tollowing sequence of micro-instructions (only labels
and jumps shown):

In general, row zero locations should be used
sparingly because they are the only locations that
can be reached from anywhere in microprogram
memory using a single JZR micro-operation. During the first pass of the microprogram implementation, notes can be added to indicate where code
might be saved if row zero locations are used.

TST:
DO:

In the sequence above, DO through D 15 occupy an
entire row. The micro-instruction labeled DIA
unconditionally follows both of those labeled DO
and D I. Since the row containing DO through D 15
is fully occupied, DlA cannot be assigned to that
row. The only other unconditional jump which can
reach a common location from more than one column is the JZR. However, such conditional jumps
as JCF and JZF, where the condition is pre-set,
can jump to a given location from up to eight sites
in a given row, as illustrated in Figure 15.

A common case of such microcode saving follows
the execution of a JPR or JPX micro-operation. If
the datum being tested by the JPR or JPX represents a macro-instruction operation code in which
less than 16 modes are used, there is always the
possibility that an invalid code might be encountered. Rather than have the machine behave
unpredictably, it is better to have the machine execute some designated sequence for invalid macrooperation codes. As a result, all 16 locations
reached by the JPX or JPR micro-operation must
be considered occupied. Therefore, when it is
desirable to have a single state follow each of
several states reached by a single JPX or JPR microoperation, two possible methods can be used which
do not require additional jump micro-operations:

COLUMN

012345678

ROWn

100 I0+21 1 106 1 107108109 f
03

WITHIN CURRENT
ROW GROUP

t

Figure 15. Special Use of the Conditional Jump
Functions

/* ZERO T AS TEMPORARY POINTER, WRITE W TO INTERRUPT STRUCTURE
CLR(T);
LMI(T);
ILR(W) ROT;

*/

LMI (T) FF 1 RRM;
ACM(AC) ;
SOR(S);

/* SET B = (1), T = 2 FOR NEXT OPERATION */
LMI(T) FF1 RRM;
ACM(AC);
SOR(B) STC;

/*

>

COLUMN 2 FOR C·FLAG" 0

CLR(A);
CLR(X);
GLR(W);

/* SET S = (0), T = 1 FOR NEXT OPERATION

06

8

ROWn+1

INITIALIZATION SEQUENCE
ZERO A, X, AND W */
INIT:

04

+_+_L+_L+_+_+_'
-!---JCF MICRO"()PERATI'lN

I. Locate the single state in the row zero
2. Locate the single state in a column reached by a
JCF or JZF micro-instruction and insure the
corresponding (C or Z) flag is in the desired
state.

'*

,R IDO. 01. 02. D•... D151
.IMP ID1A)

01:
01A:

THIS SETS THE C FLAG TO INSURE
A CORRECT JUMP TO XRTN */

3-39

*/

CPU Design
/* GET (2), JUMP TO XRTN TO SET E = (2), P = (E)
LMI(T) RRM;
ACM(AC)

*j

JCF (*,XRTN);

/* FETCH SEQUENCE & START OF MACRO-INSTRUCTION PROCESSING
P IS ISSUED TO MAR AND INCREMENTED, MACRO-INSTRUCTION
IS FETCHED AND TESTED BY JPX MICRO-OPERATOR_ NOTE
FETCH IS IN LOCATION 15 TO STROBE INTERRUPT ON ENTRY_ *j
FETCH:

LMI(P) FFl RRM;

/* LOAD DISPLACEMENT AND TEST FOR ZERO USING Z FLAG * j
LTM(AC) STZ KOOFF;

/* SAVE DISPLACEMENT, TEST 4 BITS OF MACRO-OP_ TEST IS
DELAYED TO ALLOW PIPELINE PROPAGATlON_ ALSO C FLAG IS
SET FOR LATER USE IN PSEUDO-SUBROUTlNES_ *j
SDR(R9) STC

JPX(NAO,JREL,JIG,IMMD,DMRF,IMRF,IXMA,IXMB,IND,
I NX,OTD,OTX,MVGP ,SPFG,I R BM,NA 15);

/* UNASSIGNED OP-CODE GROUPS- -NOPS FOR THIS VERSION
NAO:
NA15:

NO_OP
NO_OP

*j

JZR(FETCH);
JZR(FETCH);

/* IMMEDIATE GROUP OF MACRO-INSTRUCTIONS- -TEST FOR LONG OR SHORT
FORM- -D IS IN AC AND R9- -ADJUST AC BY -128 *j
IMMD:

LMI(AC) KFF80

/* LONG FORM: FETCH NEXTWORD TO AC
IMML:

LMI(P) FFl RRM;
ACM(AC)

/* SHORT FORM: NO PROCESSING NEEDED
IMMS:

NO_OP

JZF(lMML,IMMS);
*j

JRL(lLGA,ILPX,NAll,NAI2);
*j

JRL(ILGA,ILPX,NAll,NAI2);

/* PREPROCESSING FOR ARITHMETIC AND LOGIC ROUTINES? NONE NEEDED
ILGA:
ILPX:

NO_OP
NO_OP

JLL(NDA,ODA,XDA,ADA);
JLL(LDA,LDX,PDS,ADX)

/* NOTE: NAil AND NAI2 ARE NON-VALID INSTRUCTIONS!! THEY ARE
MADE INTO NO-OPS IN THIS VERSION OF THE MACRO-MACHINE *j
NAil:
NAI2:

NO_OP
NO_OP

JZR(FETCH);
JZR(FETCH);

/* BASIC ARITHMETIC AND LOGIC PROCESSING- -UPDATE C FF OF MACROMACHINE FOR ADA--TOGGLE ITON CARRY FROM ADA *j
ADA:
ADA1:
NCY:
SCY:

/* LOGICALS
NDA:
ODA:
XDA:

ADR(A);
NO_OP
NO_OP
LMI(W) K8000

JFL(NCY,SCY);
JZR(FETCH);
JZR(FETCH);

*j

ANR(A)
ORR(A)
CMR(AC);
XNR(A)

JZR(FETCH);
JZR(FETCH);
JZR(FETCH);

3-40

*j

CPU Design
/* LOA AND LOX OPERATIONS *j
LOA:
LOX:

SDR(A)
SDR(X)

JZR(FETCH);
JZR(FETCH);

/* STACK PUSH- -ADVANCE STACK POINTER TO NEXT LOCATION (FOR THE
REVERSE DIRECTION STACK- -A DECREMENT OF S), THEN WRITE *j
PDS:
PDS1:

/*

DSM(S);
LMI(S) RWM

JZR(FETCH);

ADX - SHARES CODE FOR ADA - ALSO TOGGLES C FF OF MACRO MACHINE *j
ADX:

ADR(X)

JMP(ADA1);

/* MEMORY REFERENCE INSTRUCTION GROUPS
DIRECT--GETB+D INTO AC--ALSO R9 *j
DMRF:

/*

ILR(B);
ALR(R9)

JRL(MRV1,MRV2,MRAD,STPG);

INDIRECT-ABSOLUTE- -GET (B+D) INTO AC- -C FLAG USED FOR PSEUDO-SUBROUTINE *j
IMRF:
IMRF1:
MLOAD:

ILR(B);
ALR(R9);
LMI(R9) RRM
ACM(AC)

JCF(MADD,MLOAD);
JRL(MRV1,MRV2,MRAD,STPG);

/* NOTE: MADD WILL BE USED FOR OTHER INDIRECT OPERATIONS WHERE
B, X, ETC_ HAS BEEN LOADED TO R8 *j
MADD:

/*

ACM(AC);
ALR(R8)

JRL(MRV1,MRV2,MRAD,STPG);

INDIRECT INDEXED ABSOLUTE - CLEAR C FLAG, MOVE X TO R8 *j
IXMA:

ILR(X) STC;
SDR(R8);

/* NOTING THAT ASSIGNMENT RULES WOULD NOT ALLOW THE DESIRED
JUMP TO IMRF UNLESS IXMA+l WERE IN ROW ZERO- -AN EXTRA STATE
IS ADDED HERE *j
IXMA2:

/*

ILR(B)

JMP(lMRF1);

INDIRECT INDEXED RELATIVE - CLEAR C FLAG, PUT B+X IN R8 *j
IXMB:

ILR(X) STC;
SDR(R8);
ILR(B);
ADR(R8)

JMP(lMRF);

/* INDIRECT RELATIVE (TO B) - CLEAR C FLAG, PUT B IN R8 *j
IRBM:

/*

ILR(B);

AGAIN ASSIGNMENT RULES PREVENT JUMPING TO IXMA+l UNLESS IT IS
LOCATED IN ROW ZERO- -PLACEMENT THERE COULD FREE TWO WORDS *j
SDR(R8)

/*

JMP(lXMA2);

THE FOLLOWING PROCEDURES IMPLEMENT THE BASIC PREPROCESSING FOR
VALUE AND ADDRESS LOADING_
VALUE-GROUP 1: GET (AC) IN AC
MRV1:

LMI(AC) RRM;
ACM(AC)

*'
JLL(NDA,ODA,XDA,ADA);

3-41

CPU Design
/*

VALUE GROUP 2 *f
MRV2:

LMI(AC) RRM;
ACM(AC)

JLL(LDA,LDX,PDS,ADX);

f* MRAD GROUP INCLUDES ADDRESS LOADS AND SUBTRACT FROM A *f

/*

MRAD:

NO.OP

JLL(LAA,LAX,PAS,ISDA);

LAA:
LAX:
PAS:

SDR(A)
SDR(X)
DSM(S)

JZR(FETCH);
JZR(FETCH);
JMP(PDS1);

FOR SUBTRACT, ADD l'S COMPLEMENT PLUS 1 * f
ISDA:

/*

/*

JMP(ADA1);

STPG GROUP INCLUDES STORES AND SUBTRACT FROM X *f
STPG:

LMI(AC)

JLL(SAM,SXM,PSM,SDX);

SAM:
SXM:

ILR(A) RWM
ILR(X) RWM

JZR(FETCH);
JZR(FETCH);

POP STACK TO MEMORY - SAVE ADDRESS, POP STACK' f
PSM:

/*

LMI(AC) RRM;
LCM(AC);
ADR(A) FF1

SDR(T);
LMI(S) FF1 RRM;
ACM(AC);
LMI(T) RWM

JZR(FETCH);

SUBTRACT FROM X *f
SOX:

LMI(AC) RRM;
LCM(AC);
ADR(X) FF1

JMP(ADA1);

Thus the initialization procedure requires 16 words
of microcode, the fetch sequence 3, and the memory reference and immediate groups use a total of
57 words. In addition, two dummy locations
(NAI I and NAI2) are needed for unassigned macrooperation codes.

Sample execution times for some of the instructions may be estimated by counting the number of
micro-instructions in the sequences and the number
of read and write memory cycles. Allowing I SO
nsec for each micro-instruction, and 400 nsec for
each memory cycle, some representative execution
times would be as shown in Table VII.

Table VII. Representative Execution Times
INSTRUCTION
ADA, direct

MICROCYCLES

READ CYCLES

10

2

2.3J.1S

2

2.0 JJS

3

3.45 J.lS

ADI, short

9

LOA

8

LAI, short
LOA, indirect index relative

EXECUTION TIME

1.75J.1S

7
15

WRITE CYCLES

1.45 J.lS

3-42

CPU Design
the conditional jumps, X>A, X~, X=A and X=t-A
which share a common subroutine and exit via a
JLL jump, the opcode values were assigned arbitrarily.

JUMP GROUP
The next section shows the realization of the jump
group instructions. Two basic classes, a jump relative to the program counter and an indirect jump
through a table stored at the beginning of the program are represented. Conditional jumps include
A>O, ,900, A=O, A~O, A~, AO,
X~, C=O and c=t-o.

A flowchart representing the jump coding is shown
in Figure 16. During the microcoding of the sequence, two methods were evaluated. One used
the JRL, JLL sequence of testing 2 bits of macrooperation code at a time, while the one actually
selected uses a JPR macro-operation. The JPR test
selected uses no more code than the JRL, JLL
sequence method, and executes more rapidly. At
one point (for the X=A, X=t-A, X>A, X";A tests),
code is shared as if it were part of a subroutine,
then a JLL instruction is used to resolve the exit.
This method is another example of a pseudosubroutine that saves microprogram memory. Use
of this technique does put a constraint on the
assignment of macro-operation codes.

In addition, two classes of subroutine calls are provided; a local call which pushes P onto the stack,
and jumps relative to E, and a global subroutine
call which stores the W, B, E, and P registers on
stack and computes new values for E, the program
base register, and P. Also, included in this section
of microcode is the operation that pushes both A
and X onto the stack.
Table VIII shows the opcode assignments for the
various jump operations implemented. Except for

Table VIII. Jump Instruction Group
MNEMONIC

RELATIVE
M
0

FUNCTION

INDIRECT
M
0

JRU, JIU

Jump unconditional

0001

0000

0010

JRGE, JIGE

Jump if A;;'O

0001

0001

0010

0000
0001

JRL T, JILT

Jump if AA

0001

0011

0010

0011

JREZ, JIEZ

Jump if A=O

0001

0100

0010

0100

JRNZ, JINZ

Jump if A*O

0001

0101

0010

0101

JRCZ, JICZ

Jump if C=O

0001

0110

0010

0110

JRXL, JIXL

Jump ifX,A

0001

0111

0010

0111

JRLE, JILE

Jump if A';;;O

0001

1000

0010

1000

JRGT, JIGT

Jump if A>O

0001

1001

0010

1001

JRCN, JICN

Jump ifC*O

0001

1010

0010

1010

0001

0010

1011

JRXE,JIXE

Jump if X=A

CVS

Call subroutine, push W, B, E, P

PHAX

Push A, X onto stack

CLS

Call subroutine, push P

JRXN, JIXN

1011
N.A.

0001

1101
N.A.

0001

)ump if X"=foA

Subroutine calls

1111

0010

1100

0010.

1101

0010

1110

0010

1111

Unconditional and conditional jumps

Local:

Push P to stack
P=E+(E+D)

Value:

Push W, B, E, P to stack
E=E+(E+O)
P=E'+(E') where E'=E+(E+O)

Relative:
Indirect:

3-43

P=P+O'
where D'=0-128
P=E+(E+O)

CPU Design

FETCH

FETCH

FETCH

FETCH

FETCH

FETCH

FETCH

FETCH

Figure 16. Jump Group Flowchart

/* JUMP GROUPS- -USE JPR MICRO-OPERATION TO RESOLVE CONDITION SELECTION
DESTINATION ADDRESS IS COMPUTED FIRST - -PLACED IN AC AND R9
JUMP RELATIVE TO P- -ADDRESS=P+D-12S * f
JREL:
JRDR:

ILR(P);
LMI(AC) KFFSO;
ALR(R9)

JPR(JUNC,JAGE,JAL T,JXGA,JAEO,JANE,JCEZ,JXLA,
JALE ,JAGT,JCNZ,JX EA,CPSS,PXA,C LOP,JX NA);

/* JUMP INDIAECT - GET E+(E+D) IN AC AND R9 *f
JIG:

ILR(E);
ADR(R9);
LMI(R9) RRM;
AMA(AC);
SDR(R9)

JPR (JUNC,JAGE,JAL T,JXGA,JAEO,JAN E,JCEZ,JX LA,
JALE,JAGT,JCNZ,JXEA,CPSS,PXA,CLOP,JXNA);

1* UNCONDITIONAL JUMP *f
JUNC:

SDR(P)

JZR(FETCH);

/* TESTS FOR A_GE_O, ETC_ *f
JAGE:
JALT:
JAEO:
JANE:

TZR(A) KSOOO INH
TZR(A) KSOOO INH
TZR(A)
TZR(A)

JMP(TTRU);
JMP(TFAL);
JMP(TTRU);
JMP(TFAL);

3-44

FETCH

FETCH

CPU Design
TZR(A) K8000 INH;
TZR(A)

JFL(APRE,ANPE);

APRE:
ANPE:

NO.OP
NO.OP

JFL(JNT2,JTR2);
JZR(FETCH);

JALE:

TZR(A) K8000 INH;
TZR(A)

JFL(APE2,AN2);

NO.OP
SDR(P)

JFL(JTR1,JNT1);
JZR(FETCH);

JAGT:

APE2:
AN2:

/* TESTS OF C FLlp·FLOP (HIGH ORDER BIT OF W)
JCEZ:
JCNZ:

TZR(W) K8000lNH
TZR(W) K8000 INH

*j

JMP(TTRU);
JMP(TFAL);

/* TEST EXECUTION FOR ABOVE TESTS - ROW ZERO USED * j
TTRU:

NO.OP

JFL(JTR1,JNT1);

JTR1:
JNT1:

SDR(P)
NO.OP

JZR(FETCH);
JZR(FETCH);

TFAL:

NO.OP

JFL(JNT2,JTR2.);

JNT2:
JTR2:

NO.OP
SDR(P)

JZR(FETCH);
JZR(FETCH);

/* TESTS FOR X.GT.A, X.LE.A, X.EQ.A, X.NE.A- -SHARED PSEUDO·
SUBROUTINE USES JLL FOR AN EXIT TEST - -ROUTINE ENTRY IN ROW 0
C FLAG IS SET FOR X.GT.A, FL TEST FOR X.EQ.A * j
JXGA:
JXLA:
JXEA:
JXNA:

ILR(X)
ILR(X)
ILR(X)
ILR(X)

JMP(XATS);
JMP(XATS);
JMP(XATS);
JMP(XATS);

/* SAVE X AT T, FETCH AND COMPLEMENT A
XATS:

SDR(T);
ILR(A) STC;
CMA(AC);

*j

/* CLEAR C FLAG * j

/* ADD HOB'S OF A' AND X - CARRY MEANS X NEG., A.GE.O

*j

ADR(T) K8000;

/* EXECUTE PREVIOUS TEST, SET UP TO TEST HOB OF RESULT - -IF I,
THE SIGNS OF A AND X WERE THE SAME *j
TZR(T) K8000lNH

JFL(TFEQ,TXNG);

/* TXNG IMPLIES X NEG AND A.GE.O- -I.E. X.NE.A AND X.L T.A- -DO A
DUMMY OPERATION TO FORCE THE PROPER F FLAG *j
TXNG:

JLL(JXGX,JXLX,JXEX,JXNX);

ILR(A)

/* PERFORM A TEST ADDITION AND EXECUTE SIGN·EQUAL TEST
C WILL BE SET IF SIGNS WERE THE SAME AND X.GT.A *j
TFEQ:

ADR(T) STC K7FFF

JFL(SNEQ,SWEQ);

/* SNEQ IMPLIES SIGNS NOT EQUAL- -I.E. X.GE.O, A NEG- -X.GT.A
SNEQ:

SDR(AC) STC;
NO.OP

/* DUMMY OPIO SET C FLAG

*j

*j

JLL(JXGX,JXLX,JXEX,JXNX);

345

CPU Design
/*

FOR SIGNS EQUAL,IF X=A RESULT WOULD BE 1111 ... 1. INCREMENT
WILLGENERATEACARRYIFSO *f
SWEQ:

/*

JXGX:
JXLX:
JXEX:
JXNX:

/*

ILR(AC) FF1

JLL(JXGX,JXLX,JXEX,JXNX);

EXECUTION OF JUMP TESTS * f
ILR(R9)
ILR(R9)
ILR(R9)
ILR(R9)

JCF(JNT2,JTR2);
JCF(JTR1,JNT1);
JFL(JNT2,JTR2);
JFL(JTR l,JNT1);

SUBROUTINE CALLS
CALL LOCAL AND PUSH W, B, E, P =CPSS
CALL LOCAL AND PUSH P ONL Y=CLOP
CL FLAG IS USED FOR EXIT TEST AFTER PUSHING P *f
CPSS:

DSM(S);
ILR(W);
LMI(S) RWM;

CPG2:

DSM(S);
ILR(B);
LMI(S) RWM;
DSM(S);
ILR(E);
LMI(S) RWM;

CLOP2:

/*

DSM(S);
ILR(P);
LMI(S) RWM;

E+(E+D) INTO AC *f
ILR(R9)

/*

JCF(LRTN,XRTN);

XRTN:

SDR(E);
LMI(E) RRM;
AMA(AC);

LRTN:

SDR(P)

JZR(FETCH);

CLOP:

DSM(S);
ILR(P) STC

JMP(CLOP2);

PUSH INSTRUCTION *f
PXA:

DSM(S);
ILR(X);
LMI(S) RWM;
DSM(S);
ILR(A);
LMI(S) RWM

JZR(FETCH);

REGISTER MOVE AND SUBROUTINE
RETURN GROUP
In this section of code, the Register Move and Subroutine Return group instructions are implemented.
Both groups share the same IPX entry point,
I 100B. Table X shows the opcode values assigned
to the macro-instructions.

To simplify the decoding for register selection (S,
B, E or W) in the Register Move group, the two low
order bits of the PR latch are used to modify the
micro-instruction as it is strobed into the pipeline
register. By tying the two PR latch outputs of the
300 I to the two low order bits of the CPE control
field, a ICE jump function (which enables the PR

CPU Design
latch outputs) can be used to provide a wire OR of
PRO, PR I and FO, F I (see Figure 17).

Table X. Register Move and Subroutine
Return Group
MNEMONIC

Figure 17. Wire-OR of POa-1 and FO-1

Thus, in the micro-instruction
SDR(Rl)

FUNCTION

M

0

RLS

Pop P

1100

1111

RVS

Pop P, E, B, W

1100

1101
1100

RSA

Pop A, X, P, E, B, W

1100

PPAX

PapA, X

1100

1110

MSX

Move S to X, adjust

1100

0100

MBX

Move B to X, adjust

1100

0101

MEX

Move E to X, adjust

1100

0110

MWX

Move W to X, adjust

1100

0111

MXS

Move X to S, adjust

1100

0000

MXB

Move X to B, adjust

1100

0001

MXE

Move X to E, adjust

1100

0010

MXW

Move X to W, adjust

1100

0011

NO.OP

Nothing implemented

1100

10XX

JCE (MXRXI

the register group field FO-F3 is modified as
shown in Table IX.
The microprogram sequence is shown in Figure 18.

Table IX. Register Group Field FO-F3 Modification
MICROPROGRAM
MEMORY OUTPUT
(FO-F3)

PR LATCH
OUTPUT

RESULT STORED IN
PIPELINE REGISTER

SELECTED REGISTER

0111

00

0100

S

0111

01

0101

B

0111

10

0110

E

0111

11

0111

W

FETCH

FETCH

FETCH

FETCH

Figure 18, Register Move and Subroutine Return Group Flowchart

3-47

FETCH

FETCH

CPU Design
/* MOVE GROUP OF INSTRUCTIONS- -USES JCE TO SELECT REGISTER- -NOTE
THAT REGISTER ASSIGNMENT BECOMES IMPORTANT
FIRST MODIFY D TO GET D-12B ./
MVGP:

LMI(R9) KFFBO

JLL(MVXR,MVRX,MOD,PGRP);

/* MOVE X TO REG. - GET X, MODIFY BY D'=D-12B ./
MVXR:

MXRX:

ILR(X);
ALR(R9);
SDR(R7)
NO.OP

JCE(MXRX);
JZR(FETCH);

/* REGISTER OVERRIDE ./

/* MOVE REG TO X - FETCH REG USING JCE OVERRIDE ./
MVRX:
MRXX:

ILR(R7)
ALR(R9)

JCE(MRXX);
JMP(LDX);

/* MOD NOT IMPLEMENTED IN THIS VERSION ./
MOD:

NO.OP

JZR(FETCH);

/* ADJUST STACK AND RETURN GROUP
PPAL- -POPS A, X, P, E, B, AND W
PPRA- -POPS P, E, B, AND W
PPAX- -POPS ONLY A AND X
POPP- -POPS ONLY P • /
PGRP:

PPAL:

PAXC:
PPRA:

ILR(R9);
ADR(S)

JRL(PPAL,PPRA,PPAX,POPP);

LMI(S) FF1 RRM;
ACM(AC);
SDR(A);
LMI(S) FF1 RRM;
ACM(AC)
SDR(X);

JCF(PAXE,PAXC);

LMI(S) FF1 RRM;
ACM(AC);
SDR(P);
LMI(S) FF1 RRM;
ACM(AC);
SDR(E);
LMI(S) FF1 RRM;
ACM(AC);
SDR(B);
LMI(S) FF1 RRM;
ACM(AC);
SDR(W);

/. RESTORE INTERRUPT STRUCTURE ~
CLR(T);
LMI(T) ROT

JZR(FETCH);

PAXE:

SDR(X)

JZR(FETCH);

PPAX:

ILR(AC) STC

JMP(PPAL);

POPP:

LMI(S) FF1 RRM;
ACM(AC)

JMP(JUNC);

3-48

CPU Design
SPECIAL FUNCTION GROUP

Table XI. Special Function Groups

The JPX entry point 110 I B is used as an entry
point for the special function groups which include
byte load and store, register manipulation, and the
absolute subroutine call and increment and skip if
zero instructions. Table XI lists the opcode values
assigned to the instructions. A flowchart of the
sequences is shown in Figure 19.

MNEMONIC

In order to execute a byte load or store operation
efficiently, a byte swap capability (which exchanges
the high and low order byte positions) is necessary.
By wiring the data outputs of the high order byte
to the I inputs of the low order byte, and the low
order outputs to the high order I inputs, a byte
swap operation can be performed (see Figure 20).
Note that with the configuration shown in Figure
20, a byte swap can be performed on either a
memory word or the AC register of the CPE array
by reading data in on the I-Bus inputs while performing a memory read or enabling the D-Bus,
respectively.

REGISTER
SHIFTIROTATE
GROUP

Figure 19. Special Function Groups Flowchart

3-49

FUNCTION

M

0

LBA

Load byte absolute

1101

0000

LBR

Load byte relative

1101

0100

SBA

Store byte absol ute

1101

1000

SBR

Store byte relative

1101

1100

RAR

Rotate A right, include
CFF

1101

0001

RAX

Rotate A and X right,
include CFF

1101

0101

SAX

Shift A and X right,
preserve sign

1101

1001

SAL

Shift A left, fill with
zeros

1101

1101

ISZ

I ncrement and skif ip
zero

1101

XX10

CAS

Call absolute, push
P, E, W, B
P <- (D)

1101

XXll

CPU Design

BIDIRECTIONAL
DATA BUS

{J-::======~.2:.~
f-

Figure 20. I-Bus Wired for Byte Swap

/* SPECIAL FUNCTION GROUP
BYTE OPERATORS- -ADDR=(B+D)+B+X/2 OR (B+D)+XI2
CALL TO (D) AND PUSH ALL
SHIFT AND ROTATE GROUP
INCREMENT AND SKIP
FETCH B JUST IN CASE */
SPFG:

/*

JRL(BYTE,RSGP,SCJG,ISJG);

BYTE GROUP- -COMPUTE ADDR, STORE B IN CASE NEEDED */
BYTE:

SDR(R8);
ADR(R9);
ILR(X);
SRA(AC) STC;
LMI(R9) RRM;
ACM(AC)

LBYR:
LBYA:
LBYT:
RBYT:
DBIA:

ALR(R8);
LMI(AC) RRM
LDI(AC) FFl KOOFF
L TM(AC) KOOFF;
SDR(A)

SBYR:
SBYA:

ALR(R8);
LMI(AC);
ILR(A);
TZR(AC) KOOFF RRM
L TM(T) KFFOO;
ALR(T) RWM

STRB:
SRB1:
STLB:

/*

ILR(B)

LTM(T) KOOFF;
LDI(AC) FFl CNB

JLL(LBYA,LBYR,SBYA,SBYR);

JCF(LBYT,RBYT);
JMP(DBIA);
JZR(FETCH);

/* LOAD MAR FOR LATER USE */
JCF(STLB,STRB);
JZR(FETCH);

JMP(SRB1);

ROTATE GROUP
ROTATE A WITH C- -ROTATE A AND X WITH C- -SHIFT A, X RIGHT, FILL
WITH SIGN- -SHIFT A LEFT, FILL WITH ZEROES

3-50

CPU Design
AT ENTRY, Z FLAG IS ZERO IF D=O. DUE TO PIPELINED OPERATION, IT IS
THIS CONDITION THAT IS TESTED BY THE FIRST JZF *f
RSGP:
SZDS:
SNZD:
RACI:
RAXI:
SAXI:
SLZI:

TZR(W) STZ K8000lNH
ILR(X);
SDR(R9) FFO K007F
DSM(R9)

JZF(SZDS,SNZD);

ILR(A)
ILR(X);
SDR(T)
TZR(A) STZ K8000 INH
ILR(A)

JMP(RUNR);

JLL(RACI, RAXI,SAXI,SLZI);
JLL(RACI,RAXI,SAXI,SLZI);

JMP(RACI);
JMP(RAXI);
JMP(RUNR);

f* MAIN ROTATION LOOP *f
RUNR:

DSM(R9)STC

JLL(RACR,RAXR,SAXR,SLZR);

RACR:
RAXR:

JFL(RSEX,RUNR);

SLZR:

SRA(AC) FFZ STZ
SRA(AC) FFZ STZ;
SRA(T) FFZ STZ
SRA(AC) FFZ STC;
SRA(T) FFC
ADR(AC) STZ

JCF(RSEX,RUNR);
JFL(RSEX,RUNR);

RSEX:

SDR(A)

JLL(RACF,RAXF,SAXF,SLZF);

RACF:
SNCF:
SSCF:
RAXF:
RXF1:
SAXF:
SLZF:

TZR(W) K7FFF
NO.OP
LMI(W) K8000
ILR(T);
SDR(X)
ILR(T)
TZR(W) K7FFF

JZF(SNCF,SSCF);
JZR(FETCH);
JZR(FETCH);

SAXR:

JCF(RSEX,RUNR);

JMP(RACF);
JMP(RXF1);
JZF(SNCF,SSCF);

/* SPECIAL CALL AND JUMP GROUP- -CURRENTLY CONTAINS ONLY THE
CALL TO (D) AND PUSH W,B,E,P- -ALL 4 OPCODES DO THE SAME THING * f
SCJG:

LMI(R9) RRM;
ACM(AC);
SDR(R9)

JMP(CPSS);

f* INCREMENT AND SKIP GROUP- -AGAIN 4 OPCODES ARE USED FOR ONE
INSTRUCTlON- -LOCATION AT B+D IS INCREMENTED *f
ISJG:

NOSK:
SKIP:

ALR(R9);
LMI(R9) RMW;
ACM(AC) FFl RWM;
NO.OP
NO.OP
LMI(P) FFl

JFL(NOSK,SKIP);
JZR(FETCH);
JZR(FETCH);

3-51

CPU Design
generates a Request Input or Request Output to
select an I/O port and specify the operation to be
performed. Table XII lists the opcode values assigned to the macro-instructions. The flowchart in
Figure 21 shows the microcode sequence used.

INPUT/OUTPUT GROUP
In this section of code, the input/output instructions are implemented. In conjunction with the
memory address register, the bus control field
Table XII. Input/Output Group
MNEMONIC

INTERRUPTS
M

FUNCTION

0

IND

I nput one word
A+- (D)

1000

XXXX

OTD

Output one word
(D) +-A

1001

XXXX

INX

I nput one word
A+- (X)

1010

XXXX

OTX

Output one word
(X) +-A

1011

XXX X

A basic means for microcoding interrupts when
using the 3214 Interrupt Control Circuit involves
forcing an alternate microprogram address which
then leads to an interrupt handling routine. The
interrupt handling routine interrogates the interrupt structure to determine the interrupting level.
This level is rewritten to the interrupt structure to
block further interrupts at the interrupting priority
level or lower levels while enabling interrupts at
higher levels.

• FOR NOW FOUR OPCOOE GROUPS Will BE
ASSIGNED FOR INPut AND OUTPUT'
LMIIR9)RIN
ACM(ACI.
SORIA)

LMIIXI RIN
ACM(AC)
LMIIR9)

JZRIFETCHI

wx--~----------~~----------~----------~----

FETCH

FETCH

FETCH

Figure 21. Input/Output Flowchart

/* INTERRUPT- -UTILIZED CALL ROUTINES FOR REGISTER SAVING
I/O DEVICE #0 REPRESENTS EXTERNAL INTERRUPT STRUCTURE
START BY PUSHING OLD VALUE OF STATUS */
INTER:

DSM(S);
ILR(W);
LMI(S) RWM;

/* READ INTERRUPTING LEVEL FROM EXTERNAL STRUCTURE */
CLR(T);
LMI(T) RIN;
LTM(AC) KOOFF ROT;

/* NOTE LEVEL REWRITTEN */

/* STORE PRIORITY IN W - SET C FLAG FOR PROPER LOADING OF REGISTERS */
SDR(W) STC;

/* INTERRUPT ROUTINE STARTING ADDRESS IS COMPUTED IN R9 */
LMI(W) RRM;
ACM(AC);
SDR(R9)

JMP(CPG2);

3·52

CPU Design
Microprogram Memory Assignment

below. Conditional jumps should be labeled as to
type and condition corresponding to each destination. This information will be necessary when performing an assignment. No other information is
needed on the flowchart, but it is quite useful to
show any symbolic label that may be associated
with a state.

Having written the actual code with minimal regard
to memory assignment, the actual assignment to
ROM must be performed. To assist in this function,
a complete state (Le., microcode instruction) flowchart should be prepared. Each machine state is
represented by a dot in the state diagrams shown

INITIALIZATION GROUP

INIT=OO
ENTRV POINT
FROM OTHEA
ROUTINES

FETCH

=

OOOFH

JPX

NAO

JREL

JIG

IMMO

DMRf

IMRF

IXMA

IXMB

IND

INX

OTD

aTX

MVGP

SPFG

tRBM

IMMEDIATE GROUP

IMML

IMMS

JRL

00
lLGA

01

ILPX

NAI2
FROM MRXX

JLL
JLL

00

01

NDA

aDA

FETCH

10

00

11

xaA

ADA

LOA

10

LOX

PDS

FETCH

PDSl

FETCH

FROM MEMORY
REFERENCE GROUP
"ISOA" AND "SOX"

FETCH

FETCH

3-53

ADX

FROMMEM
REF "PAS"

FETCH

FETCH

11

NA1S

CPU Design
MEMORY REFERENCE
GROUP

OMRF

IXMB

IRBM

•0
MADO

JRL

JRL

JRL

00

01

10

11

MRVl

MRV2

MRAD

STPG

JLL
JLL

00

01

SAM

SXM

10

PSM

11

sox

11

LOA

LOX

PDS

ODA

XDA

ADA

FETCH

ADX

FETCH

JLL
00

NDA

11

FETCH
TO "ADA'"

10

11

PAS
FETCH

FETCH

ISOA

PDS'

JUMP GROUP
JREL
TO "ADA'"

JROR

JIG

n

~

r-oooo-----1~~~~--~--t------,------~--~--t-,O~IO~--~I~OO~I~-1-,~OO~O--~~~---r~~--,------,-,-ll~, ~
JUNe

JCNZ

JAGT

FROM

"pop,,",","

FETCH
'1

ANPE

• 0

JTRI

FETCH

FETCH

FETCH

FeTCH

3-54

JALE

JXNA

CPU Design

JUMP GROUP (CONTINUE'"

--1.

"R
1110

1101

1100

PXA

CPIS

CLOP

FROM
INTER +9
CLOP2

CPO'
JCF

LRTN

FETCH

XRTN

FETCH

MOVE GROUP

11
PGRP

00
MVXR

MRXX

FETCH

JRL

.t

00
'PAL

t.

PPRA

PPAX

MXRX
FETCH

TO "LDX"
FETCH

FETCH

TO "JUNC"

"

POPP

CPU Design
SPECIAL FUNCTION GROUP
SPECIAL FUNCTION GROUP
JOL

SP F.

00

0'
RSGP

BYTE

11

'0
SCJ.

'SJG

---m- -,
'0

SZOS

SNZO

~
-0

- - . . TO "CPSS"

>JLL

JCF

kJ:11

LBVR

·0

.,

LBYT

R8VT

SBYA

JCF
-0

STLB

SBVR

RAel

~:Y

STRB

JLL

00
RACF

0'
RAXF

~

(

10
SAXF

SLZI

JCF
"0

SRBl

FETCH

SKIP

.,
JFL

DBtA

.,

FETCH

FETCH

JLL

u~'
LBVA

NOSK

'"1

RUNR

~RSEX

FETCH

JLL

11

SLZF

U~ACO

0'

RAXR

"-

SAXO
'0

11

SLZR

JZF
·0
SNCF

FETCH

t~F
FETCH

INTERRUPT SERVICE ROUTINE

If0 GROUP

INTER = 255

FETCH

3-56

CPG'

CPU Design
executes a JCE jump which uses an additional
location within the JLL destination columns. However, the basic jump micro-operation characteristics
do allow all of these conditional jumps to be placed
within one block of eight rows.

Once all of the state diagrams have been prepared,
a number of steps may be followed to simplify the
assignment procedure. First, the basic hardware
characteristics dictate that INIT, FETCH, and
INTER be located in microprogram memory locations 0, 15, and 255 (decimal), respectively. Then,
note that each conditional jump has a limited
range.- As a result, when several conditional jumps
follow one another in sequence, all may have to be
located within a restricted range in microprogram
memory. For JCF, JZF, JLL and JRL microinstructions, the calling instruction must be in the
same block of eight rows as the destinations.

To retain row zero, the conditional jumps of
clusters one and five are placed in the last eight
rows of the microprogram memory. In addition to
the destinations, space must be reserved for the
"calling" micro-instructions for each of the conditional jumps listed in the clusters.
Chart I shows an assignment of the conditional
jumps of clusters one and five, together with some
of the immediately related states. For the assignment procedure, a form like that of Chart I is used
to show which microprogram memory locations
are occupied and which are available. The format
also aids visualization of valid jump micro-operations. As each state is assigned to its location in
micro memory, the corresponding position on the
state diagram is marked to show assignment. In this
way, unassigned states are easily located on the
state diagrams.

To do the best assignment, the most restricted set
of micro-instructions should be assigned first. The
most restricted groups of micro-instructions are
usually associated with clusters of conditional
jumps which must be located within a given range
of memory. It is therefore very useful to catalog all
such clusters of conditional jumps. Table XIII lists
the clusters associated with this machine. In each
case the conditional jump is identified by the jump
micro-operation and the first of its destinations.
Thus in Table XIII the symbol JRL(MRVI) really
refers to the code JRL(MRVI, MRV2, MRAD,
STPG). For this machine, there are only five
clusters.

The information placed in the memory maps includes the state label or, for strings of states with
no assigned label, the label of the nearest previously
labeled state plus information to indicate how far
from that labeled state the present state is. For
example, INIT+2 is the second state after INIT.

Table XIII. Conditional Jump Clusters
1.

JPX
JRL
JLL
JZF

(NAO)
(lLGA). JRL (BYTE)
(NOA). JLL (LOA). JLL (MVXR). JLL (RACI)
(IMML). JZF (SZOS)

2.

JRL (MRV1)
JLL (SAM). JLL (LAA)
JCF (MAOO)

3.

JLL (JXEX)
JFL (JTR 1). JCF (JNT2)

4.

JRL (PPAL)
JCF (PAXC)

5.

JLL (RACR). JLL (RACF)
JCF (RSEX)
JZF (SNCF)

The state assignment can proceed, with conditional
jumps and short unconditional sequences being assigned before long unconditional sequences. Chart
2 shows the state assignment at a point when all
states except those between INIT and FETCH,
those between PPRA and FETCH, and those associated with IND, INX, OTD and OTX have been
assigned.
For those states which have only one calling state
(Le., a state which has only one state jumping to it
with a non-conditional jump) and only one target
state (i.e., it makes a non-conditional jump to
another state), two hexadecimal numbers are also
written on the memory map. The number in the
lower left-hand corner is the address of the calling
state (first hex digit is the row, second hex digit is
the column), and the number in the lower righthand corner is the address of the target state. This
information will tell the designer at a glance which
states can be easily moved in the process of memory assignment, and to which locations they can be
moved. For instance, a state with its calling state
and target state in the same row (or column) can be
moved anywhere in that row (or column), and a

An examination of the flowcharts indicates that a
simpler code might result if clusters one and five
were combined because of the coupling between
JLL(RACI) of cluster one and the JCF(RSEX) of
cluster five. The combination of these two clusters
represents the greatest degree of restriction, as
within the same block of rows there would be one
JPX, six JLL, two JRL, one JCF and three JZF
micro-operations. In addition, the JLL(MVXR)

3-57

CPU Design
may then be used freely. In those cases where extra
states were used to avoid the use of row zero
locations, the assignment may be reconsidered. For
this machine, the operations IND, INX, OTD and
OTX were rewritten to utilize row zero locations.
Figure 22 shows the revised flow diagram for these
four operations.

state with its target state in the row zero can be
moved anywhere in the same row or column as its
calling state.
As an example of how this information can be
used, note that in Chart 2 state RAXI+ I has been
assigned to location 090H. However, when the
INIT sequence is assigned, it becomes convenient
to locate INIT+ I somewhere in column O. Since
there are no available spaces in column 0, the
designer notes that state RAXI+ 1 has both its
calling and target states in row 9, and so RAXI+ I
can be moved anywhere in row 9. In Chart 3,
RAXI+ I has been reassigned to location 098H,
and INIT+ 1 has been assigned to location 090H.
This moving process will typically be frequently
necessary in the assignment procedure, and thus it
is quite useful to have this information right on the
working memory map.

The final assignment is as shown in Chart 3. Two
locations remain.

FETCH

FETCH

Figure 22. IND, INX, OTD and OTX
Revised Flow Diagram

The final state assignments consist mostly of the
long unconditional sequences. Row zero locations

/* INPUT AND OUTPUT - -CURRENT VERSION DOES NOT DECODE INTO
SUBGROUPS- -ALSO ROW ZERO IS USED TO SAVE CODE */
IND:
IND1:
INX:
OTD:
OTD1:
OTX:

LMI(R9) RIN;
ACM(AC);
SDR(A)
LMI(X) RIN
LMI(R9);
ILR(A) ROT
LMI(X)

JZR(FETCH);
JMP(lND1);
JZR(FETCH);
JMP(OTD1);

CONCLUSION
In the central processor design example described
above, the final definition of the central processor
macro-instruction set evolved as the microprograms
were being implemented. In many instances, it was
necessary to modify the macro-instruction opcode
assignment in order to take full advantage of the
capabilities of the Series 3000 architecture. Macroinstruction operations were also redefined to add
more flexibility as microprogramming techniques
improved.

ability to decode macro-instruction opcodes and
large repertoire of conditional and unconditional
jump operations resulted in both efficient microprograms and complete memory utilization. Only
two memory locations remained unused after the
microcoding was complete.
The central processor developed in this application
note is used as a design example only, and therefore does not represent a complete central processor or an instruction set designed for a specific
application. However, because of the microprogrammability of the Series 3000 family, the same
basic organization can be tailored to a wide range
of operating environments from I/O processing to
data processing and dedicated arithmetic computation.

The microprograms were implemented without
regard to memory assignment except in cases where
code sharing between micro-instruction opcode
assignments were critical. Actual assignment of the
micro-instructions to memory involved a very small
portion of the design cycle. The 3001 MCU's

3·58

Chart 1
JFL, JCF, JZF
COLUMN RESTRICT

0
00

,

f,e,<=O

f,e,<=1

2

3

JFL, JCF, JZF
COLUMN RESTRICT

JLL COLUMN RESTRICT

4

5

6

8

7

9

f,e,<=O

f,e,<=1

A

B

JRL COLUMN RESTRICT

C

0

E

F
FETCH

IN IT

01
02
03

04
05
06
07
08

NAO

09

RAXI+l
95 94

OA

RAXR+l
A4
RXFI

JREL

JIG

IMMD

DMRF

IMRF

IXMA

IXMB

RSEX

RUNR

RACI

RAXI

SAXI

SLZI

SAXR+l
A6

SNCF

SSCF

RACR

RAXR

SAXR

SLZR

IMML+l
B2

IMML

IMMS

RACF

RAXF

SAXF

SLZF

OC

MVXR

MVRX

MOD

PGRP

OD

NDA

ODA

XDA

ADA

OE

LDA

LDX

PDS

ADX

OB

OF

MRXX

IND

INX

OTD

OTX

SZDS+l
9A

SZDS

SNZD

PAXC

PAXE

MVGP

SPFG

IRBM

NA15

BYTE

RSGP

SCJG

ISJG

PPAL

PPRA

PPAX

POPP

ILGA

ILPX

NAil

NAI2
INTER

o"CJ

c:
C

m
cs·
:::J

o"0

c:
c

Chart 2
JFL, JCF, JZF
COLUMN RESTRICT

0

1,<,.=1

2

3

4

JTRI

JNTI

TFAL

TTRU

1
JAGT+l

JLL COLUMN RESTRICT

1,<,.=0

6

5

7

8

1,<,.=0

1,<,.=1

9

A

B

MAOO+l

IMRF1+l

XATS

SBYA+2
18

STLB

STRB

00

INIT

01

SNEO+l
12

SNEO

SWEO

LBYA

LBYR

SBYA

SBYR

02

OBIA

LBYT

RBYT

-JXGX

JXLX

JXEX

JXNX

03

JUNC

JALT

JXGA

JAEO

JANE

JCEZ

JXLA

04

PXAt2
40 70

APE2

AN2

IXMB+3
47 85

IXMA+l
86 56

IXMB+2
57 45

05

JIG+3
EO 60

XATS+4
5A

TFEO

TXNG

OMRF+l
84

IMRFI

IXMA2

IXMB+l
87 47

INTER+3
5F 59

INTER+4
58 69

06

JIGt4
50

JROR+ 1
71

JNT2

JTRI

LAA

LAX

PAS

ISOA

ISOA+l
67 F8

07

PXA+3
40 FO

JROR
81 61

APRE

ANPE

SAM

SXM

PSM

SOX

PSM+1
76 A8

08

NAO

JRLE

JIG

IMMO

OMRF

IMRF

IXMA

IXMB

INO

09

RAXI+1
95 94

OA

RAXR+ 1
A4

SAXRt 1
A6

SNCF

SSCF

RACR

RAXR

SAXR

OB

RXFI

IMML+l
B2

IMML

IMMS

RACF

RAXF

oc

MVXRtl
C4 Cl

MVXRt2
CO

NCY

SCY

MVXR

00

POPP+l
OF 30

XOA+l
06 OF

CPG2+7
F2 00

PPAL+l
OC 08

OE

JIGt2
E2 50

MXRX

JIGtl
82 EO

OF

PXAt4
70 Fl

PXAt5
FO OF

CPG2+6
FB 02

JAGE

RSEX

RUNR

I

JFL, JCF, JZF
COLUMN RESTRICT

JALE+l
SBYA+l
16 79

JALE

cS'
:J

JRL COLUMN RESTRICT

C

STLB+l
lA 10

0

E

F

CLOP2

FETCH

SRBI

FETCH+l
OF 9F

PPRA+l
DO 2F

BYTE+5
AE

JXEA

CPSS

PXA

CLOP

XATS+l
OB 5B

SCJG+2
4E 3C

PXA+l
3D 40

SCJG+l
CE 4C

XATS+3
5B 51

XATS+2
4B 5A

CPSS+l
3C 50

CPSS+2
5C AO

IRBM+l
8E 56

INTER+2
BF 58

INTER+5
59 6C

MAOO

MLOAO

INTER+6
69 60

INTER+7
6C 6F

CLOP+l
3E 00

INTER+8
60 AF

SOX+l
77 F9

CPG2+2
AA 7B

CPG2+3
7A EB

MRVI

MRV2

MRAO

STPG

INX

OTO

OTX

MVGP

SPFG

IRBM

MRV2+1
7D

JAGT

JCNZ

JXNA

NA15
FETCH+2
IF

SZOS+l
9A

SXOS

SNZO

MRV1+l
7C

SLZR

PSM+2
78 B8

ISJG+3
09

CPG2+1
AO 7A

BYTE+3
AC AE

BYTEt2
BC AB

CPG2

BYTEt4
AB 2E

INTERt9
6F AO

SAXF

SLZF

PSM+3
A8 OF

XRTN+2
B9 BA

LRTN

XRTN

BYTE+l
CC AC

CLOP2tl
00

XRTN+l
BB B9

INTER+!
FF 5F

MVRX

MOO

PGRP

PGRP+l
C7

ISJG+l
CF 09

NOSK

SKIP

BYTE

RSGP

SCJG

ISJG

NOA

aOA

XOA

AOA

PPAL+2
03 E8

ISJG+2
09 A9

PAXE

PAXC

PPAL

PPRA

PPAX

POPP

LOA

LOX

POS

AOX

PPAL+3
08 E9

PPAL+4
E8

CPG2+4
7B FB

ILGA

ILPX

NAil

NAI2

AOAI

ISOA+2
68 F7

SOX+2
79 F7

CPG2+5
EB F2

RACI

RAXI

MRXX

SAXI

POSI

SLZJ

INTER

Chart 3
JFL. JCF. JZF
COLUMN RESTRICT

0

f.e •• =O

f.e ••=1

2

3

4

5

6

1

JFL. JCF. JZF
COLUMN RESTRICT

JLL COLUMN RESTRICT

7

8

f.e ••=O

f,c,z=l

9

A

B

JRL COLUMN RESTRICT
C

0

E

F

00

INIT

JAGT+l

JTRl

JNTl

TFAL

TTRU

OTOl

JALE+l

IN01

MAOO+l

IMRF1+l

XATS

INIT+12
FC

CLOP2

PPRA+4
lE

FETCH

01

SNEO+l
12

INIT+4
21 41

SNEO

SWEO

LBYA

LBYR

SBYA

SBYR

SBYA+l
16 79

SBYA+2
lB

STLB

STRB

STLB+l
lA 10

SRBI

PPRA+5
OE 9E

FETCH+l
OF 9F

02

OBIA

INIT+3
91 11

LBYT

RBYT

JXGX

JXLX

JXEX

JXNX

os

INOl+l
OF

PPRA+13 PPRA+ll
2B OF
EA 2B

PPRA+12
2A 29

PPRA+l
00 2F

BYTE+5
AE

PPRA+2
20 4F

03

JUNC

JAGE

JALT

JXGA

JAEO

JANE

JCEZ

JXLA

JALE

JAGT

JCNZ

JXEA

CPSS

PXA

CLOP

JXNA

04

PXA+2
40 70

INIT+5
11 44

APE2

AN2

INIT+6
41 F4

IXMB+3
47 85

IXMA+l
86 56

IXMB+2
57 45

INIT+ll
49 OC

INIT+10
4A 48

INIT+9
FA 49

XATS+l
OB 5B

SCJG+2
4E 3C

PXA+l
30 40

SCJG+l
CE 4C

PPRA+3
2F OE

05

JIG+3
EO 60

XA1'S+4
5A

TFEO

TXNG

OMRF+l
84

IMRFl

IXMA2

IXMB+l
B7 47

INTER+3
5F 59

INTER+4 XATS+3
58 69
5B 51

XATS+2
4B SA

CPSS+l
3C 50

CPSS+2
5C AO

IRBM+l
BE 56

INTER+2
BF 5B

06

JIG+4
50

JROR+l
71

JNT2

JTRl

LAA

LAX

PAS

ISOA

ISOA+l
67 F8

INTER+5
59 6C

MAOO

MLOAO

INTER+6
69 60

INTER+7 CLOP+l
6C 6F
3E 00

INTER+8
60 AF

07

PXA+3
40 FO

JROR
81 61

APRE

ANPE

SAM

SXM

PSM

SOX

PSM+l
76 A8

SOX+l
77 F9

CPG2+2
AA 7B

CPG2+3
7A EB

MRVl

MRV2

MRAO

STPG

OS

NAO

JRLE

JIG

IMMO

OMRF

IMRF

IXMA

IXMB

INO

INX

OTD

OTX

MVGP

SPFG

IRBM

NA15

09

INIT+l
00 91

INIT+2
90 21

RSEX

RUNR

RACI

RAXI

SAXI

SLZJ

RAXI+1
95 94

SZOS+l
9A

SXOS

SNZO

MRV1+l
7C

MRV2+1
7D

PPRA+6
lE FE

FETCH+2
IF

OA

RAXR+l
A4

SAXR+l
A6

SNCF

SSCF

RACR

RAXR

SAXR

SLZR

PSM+2
78 B8

ISJG+3
09

CPG2+1
AO 7A

BYTE+3
AC AE

BYTE+2
BC AB

CPG2

BYTE+4
AB 2E

INTER+9
6F AO

OB

RXFI

IMML+l
B2

IMML

IMMS

RACF

RAXF

SAXF

SLZF

PSM+3
A8 OF

XRTN+2
B9 BA

LRTN

XRTN

BYTE+l
CC AC

CLOP2+1
00

XRTN+l
BB B9

INTER+l
FF 5F

OC

MVXR+l
C4 Cl

MVXR+2
CO

NCY

SCY

MVXR

MVRX

MOO

PGRP

PGRP+l
C7

ISJG+l
CF 09

NOSK

SKIP

BYTE

RSGP

SCJG

ISJG

00

POPP+l
OF 30

XOA+l
06 OF

CPG2+7
F2 00

PPAL+l
OC 08

NOA

OOA

XOA

AOA

PPAL+2
03 E8

ISJG+2
09 A9

PAXE

PAXC

PPAL

PPRA

PPAX

POPP

OE

JIG+2
E2 50

MXRX

JIG+l
82 EO

PPRA+9
F3 EA

LOA

LOX

POS

AOX

PPAL+3
08 E9

PPAL+4
E8

PPRA+l0 CPG2+4
E3 2A
7B FB

ILGA

ILPX

NAil

NAI2

OF

PXA+4
70 Fl

PXA+5
FO OF

CPG2+6
FB 02

PPRA+8
FE E3

INIT+7
44 FA

MRXX

POSl

AOAl

ISOA+2
68 F7

SOX+2
79 F7

INIT+8
F4 4A

PPRA+7
9E F3

INTER

CPG2+5
EB F2

INIT+13
OC

o'V

c:

c

I

CS·
::s

CPU Design
The operations supported under these five modes
are as follows:

APPENDIX A
THE DESIGN EXAMPLE INSTRUCTION SET
The basic machine uses a 16-bit word. All instructions are single word instructions except the long
immediate forms. Macroprograms are fully reloeatable without reassembly. The data segment is
also independently relocatable. There are five basic
instruction catagories: memory reference, immediate data, jumps (including calls and returns), register moves and manipulations, and input-output
functions.

MNEMONIC

ASSIGNED
CPE
REGISTER

(A)

Accumulator

RO

0

AND data to A

0000

LOA

Load data to A

0001

LAA

Load address to A

0010

SAM

Store A in memory

0011

ODA

OR data to A

0100

LOX

Load data to X

0101

LAX

Load address to X

0110

SXM

Store X in memory

XoA

Exclusive OR data to A

POS

Push data to stack

0111
1000
1001

PAS

Push address to stack

PSM

Pop stack to memory

1010
1011

ADA

Add data to A

1100

NoA

The machine has seven registers as follows:

REGISTER

FUNCTION

(X)

Index Register

Rl

(B)

Data·Base Register

R5

AoX

Add data to X

1101

(E)

Program Execution Base Register

R6

SoA

Subtract data from A

1110

(P)

Program Counter

R3

SOX

Subtract data from X

1111

(S)

Stack Pointer

R4

(W)

Status Word Register'

R7

Immediate Group

• A carry flip·flop designated C is. the high order bit of the status
word register W.

MNEMONIC

Memory Reference Group
ADDRESS MODE

ADDRESS
COMPUTATION

M·FIELD
CODES

FUNCTION

M·
O·
FIELD FIELD

LAI

Load to A immediate

0011

0001

AAI

Add to A immediate

0011

1100

NAI

AND to A immediate

0011

0000

OAI

OR to A immediate

0011

0100

XAI

Exclusive OR to A
immediate

0011

1000

Direct

B+o

0100

Indirect

(B+D)

0101

Indirect Relative

(B+o)+B

1110

PSI

Push to stack immediate

0011

1001

Indirect Indexed

(B+o)+X

0110

LXI

Load to X immediate

0011

0101

Indirect Indexed Relative

(B+o)+X+B

0111

AXI

Add to X immediate

0011

1101

SUMMARY OF MEMORY REFERENCE MODES

If D is equal to zero, the contents of the memory
location following the instruction is used as the
immediate value.

Note: Values enclosed in ( ) designate indirect
addresses.

3.&2

CPU Design

Jump Group
MNEMONIC

RELATIVE
M
0

FUNCTION

INOIRECT
M
0

JRU,JIU

Jump unconditional

0001

0000

0010

0000

JRGE,JIGE

Jump if A.GE.O

0001

0001

0010

0001

JRLT,JILT

JumpifA.LT.O

0001

0010

0010

0010

JRXG,JIXG

Jump if X.GT.A

0001

0011

0010

0011

JREZ,JIEZ

Jump if A.EQ.O

0001

0100

0010

0100

JRNZ,JINZ

Jump if A.NE.O

0001

0101

0010

0101
0110

JRCZ,JICZ

Jump if C.EQ.O

0001

0110

0010

JRXL,JIXL

Jump if X.LE.A

0001

0111

0010

0111

JRLE,JILE

Jump if A.LE.O

0001

1000

0010

1000

JRGT,JIGT

Jump if A.GT.O

0001

1001

0010

1001

JRCN,JICN

Jump if C.NE.O

0001

1010

0010

1010

JRXE,JIXE

Jump if X.EQ.A

0001

1011

0010

1011

JRXN,JIXN

Jump i·f X.NE.A

0001

1111

0010

1111

M

0

Unconditional and conditional jumps:
Relative:
Indirect:

P = P+D'
P = E+(E+O)

where 0'=0-128

Subroutine Call Group
MNEMONIC
CAS

FUNCTION
Call absolute, push
P, E, W, B
P +- (0)

ABSOLUTE
0
M
1101

XXll

M

0

CLS

Call local subroutine,
push P

N.A.

0010

1110

CVS

Call global subroutine,
push W. B, E, P

N.A.

0010

1100

Local:

Push P to stack
P = E+(E+O)

Value:

Push W, B, E, P to stack
E = E+(E+O)
P = E'+(E')
where E'=E+(E+O)

CPU Design
Subroutine Return Group
M

0

RLS

Pop P

1100

1111

RVS

Pop P, E, B, W

1100

1101

RSA

Pop A, X, P, E, B, W

1100

1100

MNEMONIC

FUNCTION

The shift count is given by D if D is non-zero or by
the least significant seven bits of the X register if D
is zero.

Base and Status Register Move Group
MNEMONIC

Register Manipulation Group
MNEMONIC

FUNCTION

M

0

RAR

Rotate A right, include
CFF

1101

0001

Rotate A and X right,
include CFF

1101

RAX

0101

SAX

Shift A and X right,
preserve sign

1101

1001

SAL

Shift A left, fill with
zeros

1101

1101

LBA

FUNCTION

Move B to X, adjust

1100

0101

MEX

Move E to X, adjust

1100

0110

MWX

Move W to X, adjust

1100

0111

MXS

Move X to S, adjust

1100

0000

MXB

Move X to B, adjust

1100

0001

MXE

Move X to E, adjust

1100

0010

MXW

Move X to W, adjust

1100

0011

NO.OP

Nothing implemented

1100

10XX

0

MNEMONIC

M

0

0000

INO

I nput one word
A<- (0)

1000

XXXX

OTD

Output one word
(0) +-A

1001

XXXX

INX

I nput one word
A+- (X)

1010

XXXX

OTX

Output one word
(X) +-A

1011

XXXX

Load byte relative

1101

0100

Store byte absol ute

1101

1000

SBR

Store byte relative

1101

1100

Byte address

MBX

M

LBR

Relative mode:

0100

1101

SBA

Byte add ress

1100

FUNCTION

Input/Output Group

Load byte absol ute

Absolute mode:

0

Move S to X, adjust

The destination register is adj us ted by D-128.

Byte Load and Store Group
MNEMONIC

M

MSX

=
=

FUNCTION

(B+0)+X/2
(B+O)+B+X12

Special Memory Reference Instruction
MNEMONIC
ISZ

FUNCTION
Increment and skip if
zero

M
1101

0
XX10

Stack Push and Pop Group
M

o

M

0

PHAX

Push A, X onto stack

0001

1101

0010

1101

PPAX

Pop A, X

1100

1110

MNEMONIC

FUNCTION

3-64

CPU Design
APPENDIX B
MICROPROGRAM LISTING
RECORD
NUMBER
1
2

© Intel Corporation, 1975

1* BIPOLAR MICROCOMPUTER MACRO-MACHINE

REGISTER MACHINE--12/13/74
UPDATED 3/18175

3

4
5
6

7
B

9

10
11

12
13

MACHINE HAS 7 REGISTERS AS FOLLOWS:
ACCUMULATOR
RO
A
INDEX REGISTER R1
X
P
PROGRAM COUNTER R3
S
STACK POINTER
R4
DATA BASE REG
R5
I:i
g
PROG. BASE REG. R6
W
STATUS WORD
R7

14
15
16
17

C=CARRY,LINK FLIP-rLUP=HOB OF W

113
19
.!O

KB

FIELD
LENG'lH=4
MICROPS(KOOOO=O
KIiOOO=B

KB

KBUS:

DErINIrl~H

Or KBUS fIELD

*/

DEfAULT=O
K007f=1
KOOfF=3
K7FFF=7
KFFn-=15);
KfFOO=12
KfFBO=14

21
22

23

.i!4

25
20
27
28
.!9

30
31
32
33
34

35
36
37
31i
39

,* DEFINITION OF BUS CONTROL FIELD
MCr

/*

INH
RMW
CNB
RIN
ROT
RRM
RWM

FIELD
LENG1'H=3
MICROPS(NMO=0008
RHi=100B

*/

DEFAULT=O
INH=OOlB
RMW=010B
ROT=10lB
RRM=lI0B

CNB=OIIB
RWM=111B);

NBO
NO BUS OPERATION
INHIBIT,CPE ARRAY
READ-MODIFY-wRITE
CPU NEEDS BUS
REQUEST INPUT
REQUEST OUTPUT
REQUEST READ MEM.
REQUEST WRITE MEM.

40
41
42
43

SEt UP FOR SYMBOLIC REPRESENTATION OF REGISTER DESIGNATIONS *1

44

P
S
B
E

45
4b

47
48

STRING
STRING
STRING
STRING
STRING
STRING
STRING

A
X

w

'RO',
'Rl',
'R3';
'R4',
'RS',
'Ro';
'R7',

49

50
51
52
53
54
55
56
57

1* SET UP A SPECIAL NO.OP STRING *1

NO.OP
/*

STRING

'NOP(R2)',

NEXT WE SPECIFY A DEFAULT TO rFl IN THE Fa FIELD tOR THE lOR
MlCROP IN" THE CPE FlELD. lOR 18 NORMALLY USED AS A STORE
OPERATION. WHEN A DECREMENT OPERATION II ALIO DESIRED, "0
WILL HAVE TO BE EXPLICITLY SPECIFIED *1

511

59
60

SDR

IMPLY

FO-11B'

CPU Design
RiCORD
NUMIER
61

62
63
64
65

66
b1

be

69
10
11

'* ZERO
INITIALIZATION SEQUENCE
A, X, AND W *'
INIT:

OOOH:
090H:
091H:

,. ZERO

f

AS TEMPORARY POINTER, WRITE W TO INTERkUPT STRUCTURE

12
13

021H:

74
75
76

01lH:

17

ao

81
82
83

84
85
86
87

041H:

/. SET S

= CO),

T

=1

fOR NEXT

92
93

94
95
96
97
98

LMlCT) fFl RRMJ
ACMCAC)

044H:
OF4H:
OFAH:

SDR(S);

/. SET B

= (1),

r =

~

FUR NEXT OPERATION *1

L~ll(T) Ff1 RRM;
ACMCAC);
SDRCB} src;

04AH:
049H:
048H:

/. THIS SETS THE C fLAG TO INSURE
A CORRECT JUMP TO XRIN */

/. GET (2), JUMP TO XRTN TO SET E

= (2),

LMI(T) RRM;
ACM(AC)

OOCH:
OFCH:
/*

./

OPERATIO~

88

89
90
91

*'

CLRCT) ,
LMl(l'H
ILR(W) Ron

78
H

CLR(A) J
CLR(X);
CLRCW)J

P

= CE)

./

JCF C*,XRTN);

FETCH SEQUENCE & START Of MACRO-INSTRUCTION PROCESSING
P IS ISSUED TO MAR AND INCREMENTED, MACRO-INSTRUCTION
IS fETCHED AND TESTED BY JPX MICRO-OPtRATION. NOTE
fETCH IS IN LOCATION 15 TU STROBE INTERRUPT ON ENTRY. *'

99
100
101
102

10l

104
105
106

107
108
1()':/
110
111
112
113
114
11!)
110
117
116
119
120
121
12.1
123
124
125

OOFH:

fETCH:

LMI(P) ffl RRM;

/* LOAD DISPLACEMENT AND TEST fOR ZERO USING Z FLAG

*'

LTMCAC) STZ KOOfF;

0IFH:

'* SAVE DISPLACEMENT, TEST 4 BITS OF MACRO-OP. TEST IS
DELAYED TO ALLOW PIPELINE PROPAGATION. ALSO C FLAG IS
SET FOR LATER USE IN PSEUDO-SUBROUTINES.

*'

09FH:

SOH(RII) S'fC

J~X(NAO,JR~L,JIG,IMMO,OM~f,lMRF,lXMA,lx~~,IhO,

INX,OIO,OTX,MVGP,SPfG,IRbM,NAI5);
/.

~~ASSIGN~D

080H:
u8F'ti:
/'

:'lAO:
NAl~:

UP-CODE

GHUUPS--NOP~

fUH 1HIS

V~RSION

./

JZRnTfCH) ;
JZR(nl'Cit);

1000.OP
NO.UP

IMM~()lATE GROUP Uf MACRU-INSTRUCTIONS--TEST fOR LONG
F'URN--O IS IN AC AND H9--AOJUSl AC bY -128 ./

0.3tll

/. LUNG
O~lh:

IMMO:
F'O~M:

lMML:

LIH(AC) KfF'I!O
FETCH NEXI WURD TU AC */
LMl(P) Hi

RR~I:

JZHIMML,IMMS);

O~

SHORT

CPU Design
IlECOtlD
NU~tlt:R

OBIH:

12b

ACI-l( AC)

JRLIILGA,ILPX,~AII,NAI2);

U7
12i!

129
13,)
131
132

"

SHURf fORM: NO PROCESSING NEEDEU "
Otl3ti:

"

IMMS:

Pk~PRJCESSING

JRLIILGA,ILPX,~All,NAI2);

fUR ARITHMETIC

A~U

LOGIC ROuTINES?

NONE NEEDED "

133

Ol:H:
Ot:DH:

134
Ij~

136
137

"

NO.UP
NO.OP

~OTE:
NAIl AND NAil ARE
~AD£ l~rU ~U-UPS IN lHIS

13b

139
140
141
142
143
144

ILGA:
ILPX:

OHH:

OEfH:

NAll :
NAI2:

JLLINDA,DUA,XDA,ADA);
JLLILDA,LDX,PDS,ADX);
NUN-VALID INSTRUCTIOhSll THt:1 ARE
VERSIUN Of fHE MACHO-MACHINE "

NO.OP
NO.UP

JZRlfETCH);
JZRlfETCH);

BASIC ARITHMETIC AND LOGIC PROCt:SSING--UPUATE C ff
MACHINE fOR ADA--TOGGLE IT ON CARRY fROM ADA '1

"

O~

MACRU-

1 .. ~

OD/H:
Of7H:
OC2H:
OC3H:

146

147
14~

1411

ADA:
AUAl:
NCY:
scr:

AURIA);
NU.OP
NO.UP
LMIIW) K8000

JfL INcr, scn;
JZRlfETCH);
JZRlfETCH);

I~O

151
152
153
154
155
156
157
158
159
160

161
162
163

164

"

LOGICALS "
OD4H:
OU5H:
OD6H:
ODIH:

NDA:
ODA:
XDA:

ANH(A)
ORRIA)
CMR(AC l:
XNR(A)

JZRlfETCH):
JZH(fETCH);
JZR(fETCH) I

LDA AND LOX OPERATIONS '1

"

OE4H:
OE5HI

LDA:
LDX:

SDR(A)
SDR(X)

J:l.R(FETCH) ,
J:l.R(FETCHl/

/. STACK PUSH--ADVANCE STACK POINTER TO NEXT LOCATION (fOR THE
REVERSE DIRECTION STACK--A DECREMENT Of S), THEN WRITE '1

165

OE6H:
OfbH:

166
167
168

169
170
171
172
173
114
175
176
177
178

179

PDS:
PDSI:

DSM(S);
LMHS) RWM

JZR(fETCH);

I' ADX - SHARES CODE fOR ADA - ALSU TOGGLES C ff Of MACRO MACHINE '1
OE7H:
"

AUX:

JMP(ADAl);

ADHIX)

MEMONI REFERENCE INSTRUCTION GRUUPS
DIRECT--GET 8tD INTO AC--ALSO R9 '1
0&4H:

DMRf:

054H:

ILRIS);
ALRIR9)

JRLIMRVl,MRV2,MRAU,STPG);

/. INDIRECT-ABSOLUIE--GET (8+D) INfO AC--C fLAG USED fOR PSEUDO-SUBROUTINE ./

180

l~i
182
181
184

O·~5H:

055H:
UOAH:
ObBH:

IMRf:
IMRr1:
MLOAD:

ILR(B);
ALH(R9);
LMIIR9) RRM
ACM(AC)

JCf"( MADD, MLOAD);
JRL(MRVl,MRV2,MRAD,SIPG);

18~

180
1~7

If

~OIE:
kADD WILL bE USED fUR orHER IhDIPECT
S, X, ETC. HAS BEEN LOADED TU RB '1

OPERATION~

WHERE

188
1~9

I!lO

ObAH:
009H:

MADU:

ACiHAC);
ALI« 1'\8)

JRL(MRVl,MRV~,MRAD,STPG);

1~1

\1/2

If INDIRECT INDEXlD

Atl~OLUT~

- CLEAR C fLAG, MUVE X TO H8 '1

l~j

194

oa6H:

195

04bH:

lXMA:

ILR(X) ~TC;
SDR(RS);

196

3-67

CPU Design
RECORD
NUMBER
197
198
19':1

200
lOI
202
203
204
205
:l06
207
2011
209
210
211
212

j* NOriNG r~AT ASSIGNMENT RULES WOULD NOT ALLOW ThE DESIRED

JUMP ro IMRF UNLESS IIMA+l WERE IN
IS ADDED HERE */
U5bH:

UMA2 :

ILR(B)

RO~

ZERO--AN EXTRA STATE
JMP (lHRf'1);

/* INDIRECT INDEXED RELATIVE - CLEAR C FLAG, PUT B+X IN R8 */

01l7H:
057H:
047H:
045H:
/*

IXHB:

lLR(X) STC;
SDR(R8);
ILR(BJ;
ADIHR8)

JMP1'1:
/~

245
246
247
248

249
250
251
252
253
lS4
255
256
257
258
259
260
2,,1
264/
263
264
265
266
267

LMllAC) RRM;
ACM(AC)

JLL(LDA,LDX,PDS,ADX)/

MRAD GROUP INCLUDES ADDRESS LOAOS AND SUijTRACT FROM A */

OIEH:

MRAU:

NO.OI'

JLL(LAA,LAX,PAS,ISDA);

064H:
065H:
066H:

LAA:
LAX:
PAS:

SDI
2"'6
2'J7
29ij
2':1':1
300

301
30l

OHH:
OOIH:

JAGT:

072n:

IIPkE:

07Jti:

AI~PE:

038H:
U07H:

JALE:

04211:
043tl:

Ak'E2:
AN2:

303
304
305
30b

307
308
309
310
311
H.o!
311
314
315
316
317

1* TESTS OF C fLIP-fLOP (HIGH ORDER BIT or W) *1

UJbH:
03AH:

JCEZ:
JCNZ:

TZR(w) K800u INH
TZR(W) Keooo INH

JMP(TTRU);
JMP(TFAL);

1* TESI EXECUTION fUR ABuVE TESTS - ROW ZERO USED *1

005H:

'HRU:

NO.OP

JFL(JTRI,JNTl)1

002H:
003H:

JIRl:
JNTl:

SIlR(P)
NO.OP

JZRIFETCH);
JZR(FETCH);

319

004H:

TfAL:

320
321
322

NO.UP

JFL(JNT2,JTR2)I

OblH:
063H:

JNT2:
JTR2:

NO.OP
SDR(P)

JZRCfETCH)I
JZR(FETCH)I

31ij

323

324
325
326
321
32ij
329
330
331
332
333
334
335
He>
3J7
338

/* TESTS fOR X.GT.A, X.LE.A, X.EO.A, X.NE.A--SHARED PSEUDOSUBROUTINE USES JLL ~OR AN EXIT TEST--kOUTINE ENTRY IN ROW 0

C

FLA~

033H:
037H:
03BH:
03FH:

IS SET FOR X.GT.A, FL TEST FOR X.EQ.A *1
JXGA:
JXLA:
JXEA:
JXNA:

ILRCX)
ILR(X)
ILR(X)
ILR(X)

JMP(XATS);
JMP(XATS);
JMP(XATS);
JMP(XATS);

/* SAVE X AT r, fETCH ANIl cmlPLEMENT A *1

OOBH
04BH
05bH

XATS:

SOR(T) ;
lLRCA) STC;
CMA(AC);

1* CLEAR C FLAG *1

3-69

CPU Design
RECORD
NUfoIBER
33~

1* ADD Hoa'S Of A' AND X - CARRY

~EANS

1 NEG •• A.GE.O *1

340

341
342
343
344

AOR(,£) K80UO;

u~AH:

1* EXEcurE PREVIOUS TEsr, SET UP TO TEST HOB OF RESULT--IF 1.
THE SIGNS OF A AND X ~ERE THE SAME *1

345
HI>
34/
348
34':1

J50
J!>l
3::.:.1
J~J

051H:

TZR(T)

~8000

INH

JFL(TFEQ,TXNG) ;

1* rXNG IMPLIES x NEG AND A.GE.O--I.E. X.NE.A AND X.LT.A--DO A

DUMMY OPERATION TO FURCE THE PkUPER
053H:

lLRCA)

F

fLAG .,
JLLCJXGX,JXLX,JXEX,JXNX);

1* PERfORM A TEST ADDITION AND EXECUTE SIGN-EQUAL TEST

C

354

~ILL

BE SEf IF SIGNS WERE THE SAME AND X.GT.A .,

3::'~

356
J~

052H:

rFEQ:

I. SNEQ

IM~L1ES

012H:
010H:

SNEQ:

ADR(T) STC K7FfF

JFL (SNEQ, SWEQ) ;

I

35i!
J59
360
361
J02
3td
J64

365
Jb6
367
368
369
370
311
372
373
374
375

376
317
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393

394
395
390
397
398

SIGNS NOT EQUAL--I.E. X.GE.O, A NEG--X.GT.A *1
SDR(AC) STC;
NU.UP

I.

DUMMY UP TO SET C fLAG .,
JLLCJXGX,JXLX,JXEX,JXNX);

1* FOR SIGNS EQUAL, IF X=A RESULT wOULD SE 1111 ••• 1.
wILL GENERATE A CARRY IF SO *1

OllH:

Sf/EQ:

JLLeJXGX,JXLX.JXEX,JXNX);

ILkCAC) "1

1* EXECUTION OF JUMP TESTS .,

024H:
U2::'H:
02bH:
027H:

JXGX:
JXLX:
JXEX:
JXNX:

lLR(R9)
lLR(R9)
ILR(R9)
ILR(R9)

JCf(JNT2,JTR2) ;
JCf(JTR1,JNTl) ;
Jf'L(JNT2,JTR2);
Jf'L(JTR1,JNT1);

1* SUBROUTINE CALLS

CALL LOCAL AND PUSH W, S, E, P =CPSS
CALL LOCAL AND PUSH P ONLY-CLOP
C FLAG IS USED FOR EXlT TEST AFTER PUSHING P
03CH:
05CH:
OSDH:

CPSS:

DSM(S);
ILR(W);
LMI(S) RWM;

OADH:
OAAH:
07AH:

CPG2:

DSM(S);
ILR(S);
LMICS) RWM;
DSM(S);

07BH:
OEBH:
OFSH:

LMlCS) RwM;

OF2H:
0l>2H:
OODH:

DSM(S);
ILH(P);
LMI(S) RWM;

I.

"~I

!LROd;

CLOP2:

t:tCE+D) l",ro AC

.,

ILR(R9)

OIlDH:

JCFCLRTN,XRTN);

399

400
401
402
403
4114
40':)
4U6

407
40b
409

INCREMENT

OSSH:
OBEH:
OS9H:

XRTI~

UBAH:

LRTN:

SDR(P)

JZR(HTCH) ;

CLOP:

DSM(S) ;
lLR(P) STC

JMPCCLOP2);

031:.H:
OoEH:

:

SORCE);
LMl(E) RRM;
AMA(AC) ;

1* PUSri INSTRuCTION

.,

3-70

CPU Design
RECORD
NUMBER
410

030H:
04DH:
040H:

Ul
41~

413

PXA:

OSM(S):
IL~(X):

LMI(S) 1'.\1114:

414
415
411>

O~·OH:

OSM(S):
ILIHA);

417

OFIH:

L~ll(S)

070H:

RWM

JZR(FETCH);

4111

419
420
421
422
42.3
4:l4
425

421>

1* MUVE GROUP OF

INSTI'.UCTIO~S--USES JCE TO SELECT REGISTER--NOTE
THAT REGISTER ASSIGNMENT BECOMES IMPORTANT
FIRST MUOIF¥ 0 to GET D-128 *1

08CH:

OC4H:
OCOH:
OCIH:
OEIH:

428
429

U8

MVXR:
MXRX:

1* MOVE Rt:G TO

OCSH:
01'"5H:

435
436

437

LMI(R9) KFF80

JLL(MVXR,MVRX,MOO,PGRP):

1* MOVE X TO REG. - GET X, MODIfY BY 0'=0-128 "

421

430
431
432
433
U4

MVGP:

"

439

MVRX:
MRXX:

ILR(X);
ALR(R9):
SOR(R7)
NO.OP

x-

JCE(MXRX);
JZR(FETCH) ,

"

REGISTER OVERRIDE *1

FETCH REG USING JCE OVERRIDE *1

ILR(R7)
ALR(R9)

JCE(MRXX);
JMP(LOX) :

MOO NOT IMPLEMENTED IN THIS VERSION *1
OCbH:

MUD:

JZR(FETCH):

NO.OP

440
441
44J

443

444
44!)
441>

"

ADJUST STACK AND RETURN GROUP
A, X, P, E, B, AND W
PPHA--POPS P, E, B, AND w
PPAX--POPS UNLr A AND X
POPP--POPS ONLr P "

PPAL--~OPS

447
448
449

OC7H:
OC8H:

PGRP:

lLR(R9);
ADIHS)

450
451
452

OOCH:
003H:
OOSH:

PPAL:

LMl(S) FFl RRM;
ACM(AC):
SORIA):

453
454

Olo:llH:

4!)5

451>

OE9H:
OOBH:

PAXC:

JRL(PPAL,PPRA,PPAX,POPP);

LMI(S) n·1 RRM;
ACM(AC)
SDR(X);

JCF(PAXE,PAXC) :

4!)7

45S
459
460
41>1

ODOH:
02UH:
02~·H:

LtU(S) HI· RRM;
ACM(AC):
SDR(P):

4b2

04FH:
OOEH:
011::11:

LMI(S) FF1 kRM;
ACIH AC );
SORCE):

09EI1:
OFEH:

LMHS) Fn RRM:
ACM(AC):
SOIHB) ;

463
404
46~

,*b6

46"/
468
41>9
470

471
4U

O~jH:

01::311:
OEAH:
O~AH:

LMI(S) FFI RRM;
ACM(AC) :
SOlleW);

4·/j

474
475
476

471

1* RESTORE

INTE.R~UI'T

STRUCTURE

*'

02t!H:
029H:

CLR(T);
LMI(T) HOT

JZR(FETCH) ;

ODAIH

50Rl1.)

J'Z.R l rE'tC~) ;

478

419
480

3-71

CPU Design
RECORD
NUMBER
PPAX:
JMP(PPALl:
OOEH:
ILIHAC) STC
482
ODFH:
POP!':
LMHS) FFl RRM;
483
JMP(JUNC);
OOOH:
ACM(AC)
484
485
48b I ' SPECIAL FUNCTION GROUP
481
BYTE OPERATORS--AODR=(B+0)+S+X/2 OR (B+D)+X/2
488
CALL TO (D) AND PUSH ALL
4119.
SHIFT AND ROTATE GRUUP
490
INCREMENT AND SKIP
491
FETCH B JUST IN CASE *1
492
493
ILR(B)
SPFG:
JRL(BYTE,RSGP,SCJG,ISJG);
494
49~
1* BYTE GROU!'--COMpUtE AOOR, STORE B IN CASE NEEDED *1
49i1
SOR(k8);
491
OCCH:
tinE:
AOR(R9);
498
OBCri:
499
OACH:
ILR(X);
500
OABri:
SRA(AC) STC;
501
OAEH:
LtoIHR9) RRM;
)02
AMA(AC)
02EH:
JLL(LBYA,LBYR,SB~A,SBYR);
503
ALR(R8);
1.115ri:
LBYk:
504
LMI(AC) RRM
014H:
LIHA:
505
JCrtLBYT,RBYT);
50E>
LDI(AC) FFI KOOFF
JMp (lJllIA);
022H:
LilYT:
SCI')
02JH:
KbYT:
LT'UAC) KOOFF;
5011
SOH(A)
020H:
DBIA:
JZH(Ft::TCH);
509
510
017H:
ALI«k8) ;
SbYR:
01bH:
511
SlltA:
LMUAC) ;
1* LOAD MAR FUR LATER US~ *1
ILldA) ;
512
01t1H:
019H:
T~R(AC) KOOFF RRM
S13
JCnSTLB,STRB);
)14
STRb:
01bH:
LTM('r) "'FrOO;
010H:
515
JZR(FETCH) ;
ALRlT) RwM
SRBI:
51&
517
OlAH:
Sl'LS:
L'fMlT) KOOfF;
JMp(SRBI);
518
OleH:
LOHAC) Ffl CNS
519
/f
ROfArE
GROUP
~lO
521
RUTArE A WITH C--ROIATE A AND I WITH C--SHIfT A, X RIGHT, FILL
5U
~ITH SIGN--SHIFT A LEFT, FILL WITH ZEROES
52J
524
AT ENTRY, Z FLAG is ZERO IF 0=0. DUE TO piPELINt::O OPERATION, IT IS
)l5
CHIS CUNOITION THAT IS TESTED bY THE fIRST JZF *1
5lE>
HSGp:
527
OCDH:
TZR(W) STZ K8000 INH
JZHSZOS, SNZD);
09AH:
528
ILRlX):
SZDS:
52~
SDR(R9) FFO K007f
099H:
JLL(RACI,RAXI,SAII,SLZI);
5JO
SIIIZD:
DSM(R9)
09BH:
JLL(RACI,RAXI,SAII,SLZI)7
481

531

532
533

534

535
53E>
537
538
539
540
541
542
543
544
54::;
54&
547
548
54\1

094H:
095H:
098H:
09bH:
097H:

RACI:
RAil:
SAXI:
SLZI:

ILR(A)
ILR(I);
SDiHT)
TZR(A) STZ K8000 INH
ILR(A)

JMP(RUNR);
JMp(RACI);
JMP (RAXI J:
JMP(RUNR);

1* MAIN ROTATION LOOP ' I

093H:

RUNR:

OSM(R9) STC

JLL(RACR,RAXR,SAXR,SLZR),

OA4H:
OA5H:
OAOH:
OA&H:
OA1H:
OA7ri:

RACR:
RAXR:

JFL(RSEI,RUNR);

SLZR:

SRA(AC) FfZ STZ
SRA(AC) FFZ STZ;
SRA(T) FFZ lOTZ
SRA(AC) FFZ STC;
SRA(T) FFC
AOR(AC) STZ

O\l2H:

RSI::X:

lOLJR(A)

JLL(RACf,HAXF,SAXf,SLZf);

OB4H:

RACF:

TZR(w) K7FFF

JZH SNCF, SSCF);

SAXR:

JCf'( RSEX, RUNR) 7
JC~' (RSEI, RliNIO ;
JFL(RSEX,RUNR);

550

551

3-72

CPU Design
RECORD
NUMBER
OA2H
uAJH
085H
OSOH
08bH
vS"/H

55~

553
554
5~5

55b
557
55d

559
5&0
5&1

"

~b4
SO~

50&

SLZ~

NO.Up
LMl(W) K~OOO
ILRtl);
SDIHX)
ILRtT)
TZIHw) K7fH

JZIHFETCH) ;
JZRtFETCH);
JMp(RACF);
JMp t RXF 1);
JZF (SNCF , SSCf') ;

SPECIAL CALL AND JUMP GRO~p--CURRENTLY CUNTAINS ONL~ tHE
CALL TO to) A~D PUSH ~,B,E,p--ALL 4 UpCOD~S DO THE SAMg THING "
OCgll:
04EH:
04Cti:

5&~

Soj

SNCF
SSCF
RAXf
RXF1
SAXf

SCJii:

LMl(R9) RRM;
ACrHAC);
SOR(M!f)

JI'!P(CPSS);

INCR~MENT AND SKIP GROUp--AGAIN " OpCUDES ARE DSED FOR ONE
INS1RUCTION--LOCATIUN AT b+D IS l~CREMENTED "

"

~67

!)6a

569

OCFH:
OC9H:
ODIIH:
OA9H:
OCIIH:
OC8H:

570

571
572
5"/3
574

ISJG:

NUSK:
SKU':

ALRtR9);
LMI(R9) RMW;
ACM(AC) Ffl;
NU.Up R.. M
IW.OP
LMItp) ffl

Jf'L (NOSII, 51111');
JZIH fETCH);
JZRtFEl'CH) ;

57~

57&

"

INpur AND OuTPUT--CURRENT VERSION DOES NOT DECODE INTO
SUBGROUpS--ALSO ROW ZgRO IS USED TU SAVE CUDE "

577
51d

579

08~H:

580

008H:
028H:
089H:
OIlAH:
006H:
088H:

581
58~

583

584
585

INO:
IND1:
INX:
OtD:
OTD1:
OTX:

LMltR9) RIN;
AC"! tAC J;
SDRtA)
LMItX) IUN
LMltR9);
ILlltA) ROT
LMIlX)

JZRtHTCH);
JMp t IND1);
JZRtFETCH) ;
JMp(OTD1);

580
~87

"

INTERRUpT--UTILIZES CALL ROUTINES FOR REGISTER SAVING

588

110 DEVICE 10 REPRESENTS EXTERNAL INTERRUPT STRUCTURE

START 8Y PUSHING OLD VALUE OF STATUS "

589

590
591

592
593

OFFH:
OBFH:
05FH:

INTER:

DSM(S);
ILR(Wl;
LMItS) RioIM;

594
595

"

READ INTERRUPTING LEVEL FROM EXTERNAL STRUCTURE "

59&
058H:
059H:
0&9H:

597
598

599
600
601

CLR(T);
L!H(Tl R1N;
LTM(AC) KOOFF ROT; "

NOTE LEVEL REWRIrTEN "

STORE PRIORITY IN W - SET C FLAG FOR PROPER LOADING OF REGISTERS "

"

602
O&CH:

603

604
&05
60b
ou7
60d
609

SDR(W) STCI

INTERRUPT RUUfINE STARTING ADDRESS IS COMPUTED IN R9 "

"

U6DH:
OoFH:
OA~'H:

[.~i l ( w) RRM;
ACIHAC);
SDRtIl9)

JMPtCpG2);

610
b11

612

EOF

NO PROGRAM EMRORS
END Uf PROGRAM

3·73

o"'D

c:

Mle~OP~O~~A~

OH

~E~ORY

IMA~E

JCC
0090H

C

2H

IH

1H

JfL'
JZR
0072H • OOOFH

OOOri
b7

o

- - -JLL- 0024H

I

JZN'
JFL
UOOFH • 0062H

OOP2H

319

314

317
4 •

7H

6H

JfL

584

8H

9H

JFL
0042H

JCC
0028H

302

580

AH

8H

• 18.1 • 335 * 92
4
1
1 *
.-------.-------.
- JCR
JCF'
JCR'
JCR'

3

2

1

2

JCR
0018H

JC~

JC~

0016H

0019H

504

511
2

510

512

513 *

517 •

1

1

1 •

1 •

74

I

I

OOOtH

JCC
0011H

5UiI

7J

~

I

*
*

JoO
I

*

36b

505
2

1

.-------f------·.
- JCf
*
JCII'
JCR *
UO.OH' 0020H
SOb

*

1 •

*

507

1

001AH * 001CH

•

JCt'
0002f!

J.L
OU02H

370

371

J72

3

J

373
. 3

OOOAH

0055H

0047H

0059"

182

201

206

597

598'

2

2

1

1

l'

OOOfH

JZII
OOOFH

JCC
OOn.H

JCR
006aH

1

JZR
OOOFH

JfL

514 •
1

*

JZt<'*-------f-----~-*
JCR *
JeR

0062H

000.2H

OOIOH

OH

EH

FH

JCC
OOBOH

JCC
001EH

JCC
001FH

394

463

2

1

100
38

001UH

JZR
OOOFH

Jce
OU9lH

JCC
009t'H

51a

515

4b4

104

1

2

I

I

JCR
002.H

JLL
0014H

Jee
004t'H

190 •
1 •

JCII
0014H

t-------.-------.

eH

JRL'
JCF'
JCC'
JCC
007CH * OOoAH • 004BH • OOFCH

3

301
J~H

OU2"

SH

JCC'
JC~'
JLL'
JCF
0041H * uOIOH * u024H * 0022H

001H

-----

•

31b •
4 •

2~b

4H

-

OOOFH • 002BH • 0029H

581

•
477'

•
472'

476'

459

502

460

I

l'

1*

I'

I

1

1

- JZ~
*t-------f-------.
JZR
J~R *
JZR
JZR
JZ~
JZII
Jec
JCC
JZR
JZII'*-------*-------.
JZR *
Jec'
JCC
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