Southern_Programming_The_6800_Microprocessor_1977 Southern Programming The 6800 Microprocessor 1977
User Manual: Southern_Programming_The_6800_Microprocessor_1977
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PROGRAMMING THE
6800 MICROPROCESSOR
-
Bob Southern Algonquin College
Ottawa Ont. Canada
A self-instructional workbook
for assembly language and machine code programming
01 the 6800 family of microprocessors and peripherals
Chapter 1 -
Binary and Hex Numbers
2-
Accumulator Operations
3-
Symbolic Addressing
4-
Index Register
5-
Branching -
Assembly Language
6-
Branching -
Machine Code
7-
ACIA -
8-
PIA -
9-
Subroutines
Asynchronous Communications
Interface Adapter
Peripheral Interface Adapter
10 -
Stack Operations
11 -
Interrupt
AppendICes
A ._.
B ....
el, C2
D
.
. Hex Codes
ASCII Codes
Instruction Set
.. Machme Code
E1. E2 . .. ACIA
F1. F2 . .. PIA
®
G _._.
H .._
.
. C)laraeter Set
Common losll\lctJons
~
".." Glossary
J 1, J2
Assembler Error Codes
K
OM Instruction
MOTOROLA Semiconductor Products 100.
HB211
Acknowledgments
-
Many people helped make this workbook possible. I would like to thank Peter
Booler, Brian Bradley, Michel Brule and Bill Foster of Algonquin College, and
Don Lindsay of Dynalogic Limited for their advice and comments. I also would
like to thank Lynne Hall who formatted and typed this book. Lastly, I would like
to thank Richard Leir, John Oldfield and John Quarterman for their time in
testing the final version of this book.
-
The program on the front cover was written by Don Lindsay of Dynalogic
Limited, Ottawa.
Bob Southern
Disclaimer
-
The information contained in this workbook has been carefully checked and is
believed to be correct. However the author and publisher cannot assume
responsibility for errors or omissions or liability for any damages or
consequential damages arising from the use of this workbook.
Copyright © 1977 R.W. Southern
All rights reserved
This book or parts thereof may not
be reproduced in any form without
the permission of the copyright
holder.
9 8 7 6
Printed in Canada
PROGRAMMING THE 6800 MICROPROCESSOR
ABOUT THIS WORKBOOK
This workbook has one purpose only, to help you to
learn the fundamentals of assembly language and machine code
programming of the 6800 microprocessor and its peripheral
devices.
Considerable coverage is given to programming of
input/output devices, an essential part of microprocessor
applications.
The ACIA and PIA, each with their various modes
of operations, are explored in detail in both non-interrupt
and interrupt modes.
Program design and documentation is
emphasized, enabling others to understand the purpose and
operational details of your programs.
Programming hints and
aids are included along with the answers.
FOR WHOM
This workbook was designed primarily for use by students
at the community college level, although it has been successfully
used by at least one capable high school student.
Previous
programming experience is not necessary •. Early high school
mathematics is adequate, although mathematical competence beyond
this level is a good predictor of success.
THIS WORKBOOK IS
AVAILABLE FROM
Motorola Semiconductor Products Inc.
Literature Distribution Center
P.O. Box 20924
Phoenix, AZ 85036
Copyright ~ 1977 R. W. Southern.
HOW TO USE THIS WORKBOOK
The programmed notes in this workbook are for your
use at your own pace. Take your time, proceeding to the next
frame when you are satisfied with your answer, after
comparison with the answer given.
To use these notes effectively.
(a)
Cover the given answer shown below the
horizontal line following each question.
A data card is very convenient for this.
(b)
Read the text material given in the frame.
(c)
Write your answer to the question asked.
( d)
Compare your answer with the answer given and
when you fully understand any differences, if
any, proceed to the next paragraph.
For practice attempt the following question, after
covering the answer below the line.
Write your answer here.
"After answering the question what should the student do?"
_ _------1/
Answers
The student should compare his/her answer with the one
given in the workbook and, when satisfied with any
\
.
d1fferences, move on to the next paragraph.
I
BINARY AND HEX NUMBERS
Before starting please read the left page to get the
most benefit from this programmed instruction workbook.
PRE-TEST
If you are familiar with binary and hexadecimal
arithmetic operations, try the test below. If this is not
familiar to you, turn the page and start the instruction in
frame 1-1.
(a) Calculate 75 - 41, after first converting each decimal
number to its hexadecimal value, then performing the
subtraction. Verify by converting your answer back to
decimal. Write your answer on this page.
(b) Repeat (a) in binary rather than hexa~ecimal. Solutions
are on the next page.
Contd •••
PRE-TEST
Contd.
(a)
Solutions
2
W
2
2
2
2
2
L1Z
75 - 41
= 34 (decimal)
1001011
2
--.,.-~
4
+ 1
ill + 1
U+ 0
U+ 1
U+ 0
2 L! + 0
o+ 1
B
W
101001
"--w-' "-v-'
2
~+
2
2
2
L1Q
+ 0
U+ 0
U+ 1
2
L!
o
1
2
9
+ 0
+ 1
Calculate -29 then add 75. all in hex.
FF
-~
D6
+-1
D7
+4B
22
hex
~:::
o
16 = 2} "
16 1 = )2
)4
decimal
----------------------------~------------------------------
(as an 8 bit number)
75
= 01001011
41 = 00101001
one's complement of 41 = 11010110
1
+
---~
two's complement of 41 = 11010111
01001011
plus 75
1 00100010
overflow
J
~~
x
1
= 2
25 = E
x 2
34 decimal
If your answers are correct skip over to Chapter 2,
otherwise start Chapter 1 instruction on the opposite page.
---
1-1
The number system most familiar to us is the decimal one,
in which a character has ten possible states, 0 to 9. Adding 1
to 9 results in 10, that is "0" with "1 to carry" or simply
"0 with a carry".
A decimal number 527 means I
plus
plus
7 units
=
7
2 tens
= 20
5 hundreds = 500
Total
= 527
Another decimal concept to note is that 10 3 = 10 x 10 x 10 = 1000.
Similarly 10 2 = 10 x 10, 10 1 = 10 and 10 0 = 1. In fact any value,
raised to the power of zero, equals 1.
The decimal number 527 may then be expressed as,
527
~
~10
used with decimal numbers.
~'572 xx
~
1001 = 7 x 1
=
7
10 = 2 x 10 = 20
x 10 2 = 5 x 100 = 500
527
Computers use the binary or two-state number system, that
is each "binary digit" or IJbit" has only two states,' 0 or 1.
Adding 1 to 1 results in 0 with a carry.
The first 3 numbers in the binary number system are 0, 1
and 10. This is seen by adding
0
1
+1
then +1
=1
=10
= 2 (decimal)
In binary add 2 + 1. Your answer should be written above
this line. Then check your answer.
_ _ _--J/
10
+ 1
=11
= 3 (decimal)
11 (binary) : J (decimal)
-1-2
Now calculate the binary values for 4, 5 and 6, starting
from the binary equivalent of 3.
11
U
100
=J
100 =
U
=4
101
~
1
1
-----/
4
101 = 5
U
=5
=0
+
1
+
c~rry
110 = 6
+ carry
= 0 + carry.
In summary the binary equivalents of 0 to 6 are.
Decimal
0
1
2
3
4
5
Binary
0
1
10
11
100
101
6
110
Leading zeros could be used with the above binary numbers, if
desired, e.g., 110 = 0110 if a 4 bit number is required.
A subscript will be used from now on to denote the number
system, e.g., 1102 is the binary number 110, while 110 10 is the
decimal number 110. When the number system is obvious the
subscript may be omitted.
Interpretation of the binary number 101 iSI
101
~:
~ 2 used with binarl numbers
x 20 = 1
x 21 = 0
x 22 =..2t...
5
--1-3
Determine the binary value for 8 and 9.
_ _ _--J/
8 = 1000
9 = 1001
To verify
110
=6
~
111
+ 1
=7
OR
1000 = 8
~
1001
110 = 6
+10 = 2
1000 = 8
+ 1
1001 = 9
=9
The second solution is more direct and also demonstrates binary
addition with a carry.
-
1-4
In the binary number 101, the ri"ght bit carries the
least weight and is therefore called the Least Significant
Bit or LSB. The left bit carries the most weight (2 2 in this
case) and is the Most Significant Bit or MSB.
In binary, calculate 6 + 4.
your answer to decimal.
6
+4
10
=
=
---~/
110
100
1010
~l-
Verify by converting
:
~ ~~
= 0
:
= 2
2
a x 2 =0
1 x 23 = 8
10 10
Yes!
It works.
....
1-5
Calculate 8 + 7 in binary.
converting it back to decimal.
Verify your answer by
/
1000 = 8
+0111 = 7
1111 = 15
1111
lS::
x
x
x
1 x
In summary the binary equivalents for
1000 = 8
0100 = 4
0000 = a
1001 = 9
0101 = 5
0001 = 1
1010 = 10
0110 = 6
0010 = 2
1011 = 11
0111 = 7
0011 = 3
20 = 1
1
2 = 2
22 = 4
23 =...L
15
a to 15 are:
1100 = 12
1101 = lJ
1110
1111
= 14
= 15
--
1-6
Each bit of a binary number is assigned a bit number
which is the same as its binary exponent as shown below.
1011
"t:~~
:~
~(:bit #2
' - bit #J
What is another name for bit #J in this binary number lOll?
---_/
MSB or Most Significant Bit.
The bit number is also useful in determining the weight of each
bit in a binary number, e.g.,
.--bit
5)~same.
110110
~1
#@,
x
2~
1-7
.
Let's look at a method to convert from decimal to binary.
This method involves successive division of the decimal number
by 2, noting the remainder at each stage. Conversion of 19 10 to
binary is illustrated.
2
.---- remainder
2 l2+ 1
10011. This is obtained by reading
2 IJ!.+ 1
the remainders, bottom to top.
2
13. + 0
2 l!.+ 0
o+1
To verifyc 10011
0
2 = 1
1
2
2
l.!2
r
LS~:
=
1 x 2 4 = 16
19 10
Now calculate the binary equivalent of 69 and verify your answer.
2
l§2
2
(l!±+ 1
lJ2+ 0
l§.+ 1
2
2
1000101
~+
2
0
~+ 0
2
l!.+
2
o
0
+ 1
~
/
To verify
:11 xx 22°2 ==
1
4
1 x 2 6 = 64
69 10
--1-8
Convert 117 10 to binary and verify your answer by
reconverting to decimal.
2
2
2
2
2
2
2
111 7
1110101
~:
~+ 1
(29
(14
+
+
11. +
f1.+
L!.+
o+
0
1
0
1
1
1
\......,
117 10
~
x
x
x
1 x
1 x
20
22
24
25
26
= 1
= 4
= 16
= 32
= 64
= 1110101 2
117 10
If you are satisfied with your progress proceed to the
next frame. If not, try another number of your own choice now.
Let's look at binary addition now. Add 6 +
and verify your answer by converting it to decimal.
-
1-9
7 in binary
/
----------------~ Note that here 1 1 plus
+
111
1101
~'-
=7
= 1)10
a carry
:
:~ ~~
------1..~ 1
=
=
=1
plus a carry.
1
4
x 23 = ~
13 10
13 10
=
1101 2
1-10
Calculate 5 + 7 in binary and convert your answer to
decimal to verify it.
5
Z
_ _ _----J/
= 101
= 111
1210 = 110°2
~~
x 22 =
x 23 =
4 )
) ...... 12 10 = 110°2
8 )
1-11
Values less than 1 can be expressed in binary as in the
example below
1010 binary point
The 1 on the right side of the binary point carries the weighting
of 2- 1 (or 0.5 10 ); since the binary exponent continues to decrease
by 1 for each move to the right. The decimal value is then
~1
101.1
x 22 =
1
x 2
x 2°
x 2
-1
4
=
=
°1
=
~
5·5
Express 110.11 in decimal.
-------'/
The weight of each bit of a binary number can be summarized by.
11111
4 ~J
~~;I ~
~
• 24
23
22
21
2°
Bina:yexponent
orB~t#
Binary Value
Decimal
- -.... 16
Equivalent
8
4
2
1
111
\,,~
-1
-2
-)
2- 1
2-2
2-)
1/2
1/4
1/8
1-12
We'll return to the binary number system later. Meanwhile let's look at another way to express binary numbers, in
hexadecimal form (hex for short) meaning 16 possible states.
A
4 bit binary number has 16 possible states, 0000 to
1111. Expressing each of the first ten values as a single
character is quite familiar now.
0000
0001
0010
0011
0100
=
a
= 1
= 2
= J
= 4
0101
0110
0111
1000
1001
= 5
= 6
= 7
= 8
= 9
The problem now is that we need 6 more characters to
express the next values, 1010 to 1111. Arbitrarily the letters
A to F are assigned to express the missing values, that iSI
A = 1010
B = 1011
C = 1100
D = 1101
E = 1110
F = 1111
The even values, A, C and E can be
remembered by the word "ACE"
Appendix A summarizes the binary
equivalents of the hex values, 0 to F.
Without looking in Appendix A, what is the decimal equivalent of
hex code E?
---_/
1-13
By breaking up longer binary numbers into groups of 4
bits each we can express them in their hex equivalents e.g.,
the 8 bit binary number
10011010 can be grouped as
1001
"'-y--'
1010
.~
9
A or 9A as the hex equivalent.
Each of the 2 characters can then be a number (0 - 9) or a letter
(A - F). Express 11000011 in hex and mark bit #6 of this
binary number.
_ _ _-1/
,
C3
~
C
~ ---iJ'
3
-bit #6
11000011
76543210 4-bit
#
Hex codes are very popular with 8 bit microprocessors,
such as the 6800, with 2 hex characters equalling 8 bits or
1 byte. If for some reason only 7 bits are used in a binary
number, a leading zero may be added to fill out the 8 bits, e.g.,
1011101
= ~~!l~
5
D
1-14
Express each of the following binary numbers in hexi
11000101
1111000
111011
_ _ _--.J/
11000101
~1~10~
~
C
5
7 8
With a base of 16 the hex number 78 equals,
~-v--'----.....'
78
l'- :
,-;:- 16 used here for
8 x 16° =
7 x 16
1
~
numbers.
8
= 112
120
10
The hex number 78 can be expressed as 78 16 to avoid confusion
with the decimal number 78 10 , a different value.
1-15
Express each of the following hex numbers in binary
and in decimal.
D4
39
6A
D4 = ~91~
D 4
D4
\ ~D4 x= 16
'-.
13
39=~~
3
0
'1.
= 4
13 x 16 1 = 208)
9} 57
9
48
212 10
10
6A = W10!Q,
6
A
10
10 x 16° = 10} 106
.... 6 x 16 1 = 96
10
1-16
Addition in hex can be challenging, although the problem
does not exist for computers since they work in binary. Hex is
for our convenience in expressing binary numbers.
One solution is to convert to binary, add the numbers
and convert the answer back to hex, possible but not the fastest
way. If we had 8 toes on each foot we could count on our toes
to add. Did you ever consider why our number system has a base
of ten?
The solution proposed is the use of the number line.
until you become more familiar with hex addition.
For example. 9 + 3 = C
start here~"';",--count J to the right to get "C
o 1 2 J 4 5 678 9 ABC D E F 0 1 2 345 6 7 8 9 ABC D E F
II
Going beyond F produces a carry
e.g., D + 5 = 12 16 , that is 2 plus a carry.
start~
o
1 2 J 4 5 6 7 8 9 ABC D E Ff F1 2 J 4 5 6 7 8 9 ABC D EF
to
o.
Contd .•.
1-16
Contd-
Using this principle show that A
start
+
9
= 13 16-
--_--.J/
1 2 3 4 5 6 7 8 9
8 9 ABC DEFt 0 1 2 J 4
To verifyl
A
9
' - carry produced
in going from
F to o.
= 1010
= 1001
1 0011
~
1 3
= 13 16
1-17
Now add C + 9 and verify your answer by adding the
decimal equivalents.
_ _ _---..J/
start·
1 2 3 4 5 6 7 8 9~~------5 plus carry = 15 16
ABC D E F 0 1 2 345 6 7
C
9
= 12 10
= -2..21 10
~----
agrees
1-18
Now add 7 + D and verify your answer by adding in
decimal.
1 2 J 4 5 678 9 ABC D
start
7 8 9 ABC D E
To verify
14 16
,,-~4
x 16°
1 x 16 1
= 4
= 16
FlO
,~
1 2 3 4 5 6 7 8
~4 plus carry = 14 16
7 =7
D
2010
= 13 10
2010
....... agrees ~
It would have been easier to add 7 to D rather than D to 7.
The answer still is 14 16 •
1-19
Add the hex numbers C and D.
Verify your answer.
start
c
c =
D=
4--
agrees
~
1-20
To add 2 column hex numbers each column is added
separately, as in decimal. If the right column produces a
carry it is added to the left column
e.g..
2F
ill
42
(: : F
~ 2
Add the hex numbers JE + 27.
++
J
1
+==
2 plus carry
carry = 4
_ _ _---.J/
JE
+27
65
l: :E
+ 7 = 5 plus carry
= 6
J + 2 + carry
....
1-21
Add the hex numbers 4D and 25.
72 16
4D
--_----.1/
~
72 16
~.
:: D + 5 = 2 plus carry
4 + 2 + carry = 7
To verify we'll convert all data to decimal
4D 16 = 4 x 16 1 + 1J x 16° = 64 + 1) = 77 10
77
25 16 = 2 x 16 1 + 5 x 16 0 = )2 + 5 = J7 10
!-12
0
1
72 16 = 7 x 16 + 2 x 16 = 112 + 2 = 114 10 ~1f~------~"~ 114 10
agrees
1-22
Subtraction involves moving to the left on the number
line, e.g., D - 5 = 8 as seen below
54 ) 2 1
start
~
o 1 2 ) 4 5 6 7 8 9 ABC D
For the moment we will avoid "borrow" operations.
Calculate B - 7.
---~/
4
7 6 5 4 )
start
o 1 2 ) 4 5 678 9 A B
1-2)
If we are to handle subtraction we have to recognize
negative numbers since 9 - ) is actually 9 + ( - ) . Consider the
number line for an 8 bit binary number. Expressed in hex it
extends from 00 to FF (0 to 255 10 )
t
00
01
- - - FD
02 - - -
FE
FF
However, if 1 is added to FF the result, still using 2 hex
characters (8 bits), is
FF
+01
1 00
carry---1{
or 00, the carry being lost as an overflow, outside the 8 bit
limit. The question now asked is "What number, when 1 is
added to it, becomes O?" The answer is -1. By definition
therefore FF = -1. We now reconstruct our number line
-1
----
FD
I
I
FE
FF
0
+1
I
00
,
+2
01
02
-
-------
What is the value of FD based on this number line?
_ _ _-J/
-)
Since FD + ) = 00 (carry is outside the 8 bit limit)
This new number line is called a signed number line since it
permits both positive and negative values.
1-24
Continuing with the signed number line if the leading
bit (MSB) of the 8 bit number = 1, that is 8 or more for the
first hex character, the number by definition is negative. The
extent of this signed number line is shown below in decimal,
hex and binary.
-127 ~
10
-128 10
~•
80
~
81
-..............
~
~--.......
........--.. __
-) -::2 -:'1 - - - + 1 - +2 -
II
\..10000000 2
I
FD
FE
I
FF
00
+)
l
01
02
OJ
~
-... +127
+12~10 ~
II
1-
I
7E
7F
01111111
2
10
J
The extent of this signed number line is then -128 10
to +12710, Based on this number line which of the following
hex values are negative,
00
8E
CA
7A
94
F2
-----'/
All except 7A and 00 are negative. having a leading hex
character 8 or larger. If converted to binary all except 7A and
00 would have 1 as a leading bit.
If a larger range is needed for the signed number line
16 bits (2 bytes) could be used, again providing negative
values if the leading bit equals 1. This is sometimes referred
to as a double precision value.
1-25
To determine the negative value for the hex number 31
is more difficult. A procedure shown below is based on the 2's
complement arithmetic used in binary subtraction.
The procedure then iSI
- Start with the largest possible hex value
(ignoring the sign) -----I...... FF
- then subtract the number
F-1~
.::1!
CE
ABCDEF
using the number line approach
~,
- then add 1
F -3 = c
CF
OF now equals -3116
To prove it the sum of OF and 31 should be zero in 2 character
hex format. Prove it.
_ _ _---J/
CF
ill
100
~
=
F + 1 = 0 + carry
C + 3 + carry = 0 + carry
carry, which is ignored as an overflow
CF
= -3 116
1-26
Determine the hex value for -5D and prove that it is
correct by adding +5D to it.
/
FF
-5D
A2
DC B A 9 8 ? 6 5 4 3 2 1
start
2 J 4 5 678 9 ABC D E F
~start
.:!:....!
AJ = -5D
To check
carry~
AJ
+.2Q
1 00
In the top row a more direct subtraction
is seen in that F and D are separated by
2, hence F -D = 2.
1-27
Now calculate -6C and verify it.
-6c
= 94
------/
To checkl
FF
~start
-6C
9ABCDEF
93
~start
U
94
4
6c
E
100
carry)
1-28
The "two hex character" value of -) is FD. If 4
characters are used to express -3. prove that -3 = FFFD.
----'/
FFFD
.:..-..J
Similarly a 6 character representation would be
FFFFFD.
1 0000
~ carry.
To determine the value of _.) using 4 hex characters, the
procedure is
FFFF
FFFFFF
3
=---1
FFFC
~
= FFFD
Using 6 hex characters
-) equals
FFFFFC
+
1
FFFFFD
Almost all our work will employ 2 hex characters only.
For 6 hex characters () bytes) the signed number line would
extend from 800000 16 (most negative) to 7FFFFF16 (most positive) ..
1-29
We now have the capability to subtract in hex since
72 -JD is actually 72 +(-JD). Once -3D has been calculated the
hex addition will produce the answer. Try it.
_ _ _ _-----J/'
FF
To checkl
If 72 -)D
largest hex value
-JQ
C2
+ 1
plus 1
CJ
= -3D
= 35
then 35
+
3D
= 72
35
+3D
72
+1£
1 J5
now add the 72
answer
~overflow ignored
Iro verify further we will
0
72 = 7 x 16 1 + 2 x 16
=
0
3D = 3 x 16 1 + 13 x 16 =
0
1
35 = 3 x 16 + 5 x 16
=
convert all data to decimal.
112 + 2
48
+
13
48 + 5
= 11410~
= 61 10
= 53 10
114 10 -61 10
~agrees
= 5)10
~
1-;0
Let's try one more subtraction.
-----/
FF
-DC
2;
E; is already a negative number
FF
-E3
Ej
.!...1
24
Calculate E; -DC.
= -lD 16 = -29 10
1C
.!...1
= -DC
+E3
07
1D
DC is already a negative number too
DC = -24 16
Therefore -DC = 24 16
FF
-DC
=
36 10
2;
.!...1
24
To verify.
OR
EJ - DC =
07
-29 - (-j6) = 7
This shows that subtraction is valid with positive negative or
mixed numbers. Errors will occur if the result goes beyond the
range of -128 10 to 12710, the limit of an 8 bit signed number.
1-31
Now calculate 57 -2C and verify your answer in decimal.
FF
To check
-2C
=2
U
D4
ill
+
7 x 16 0
x 16 1
+
12 x 16 0 = 32 +
57 16 = 5 x
2C
D3
16 1
2B
=2
x 16 1 + 11 x 16 0
= 80
=
+
/
7 = 87 10
12 = 44 10
Total 43 10
32 + 11 = 43 10
1 2B
1-32
As a variation, let's reverse the data in the last
question. Calculate 2C -57.
D5 or -2B
FF
-
_ _--J/
.:.i'Z
A8
U
A9
+2C
D5
But D5 is a negative number.
To find its positive equivalent.
FF
-D5
2A
.!.J.
-2B
Therefore D5 = -2B, the same answer but the opposite sign,
compared to the previous question, since the data was reversed.
1-))
To complete this section let's review it all within
several questions. Given two decimal numbers, 47 and 7),
calculate the sum by converting to hex, adding, then converting
back to decimal. Verify by decimal addition.
--_-----.J/
I 47
2
2
I 2)
+1
2
l!!
+1
2
U
+1
2U
2 L!
o
2
l.1£
+1
=
2
W
+0
~~
2
F
2
+1
+0
2
2
+1
2
2F
start
+49
1 2
L...2
L2t
U
+0
+1
+0
L...!
+0
o
+1
J 4 56 7 8 9
~-v--.""~I"~V~
F 0 1 2 J 4
78
l~
2 17)
101111
= 00101111
0
8
:7 x 16 1
x 16
= 8
= ill
120 10
5 678
1001001
= '---v-01001001
.-....--'
=
4
9
1-34
Now perform the following decimal subtraction 83 -52
by converting to hex, subtracting, then converting to decimal.
Verify in decimal.
_ _ _-----J/
2W
L2£
1010011
2
2 ; 26 +0
= 53 16
2
I 41
2 I 20
2 L1Q
+1
2U
+0
2U
U
+1
2
L.!.
+0
a
+1
2
2
2
+1
+0
W
+0
2U
+1
L.!
o
110100
= )4 16
FF
+0
\.
)
~/
+1
+1
CB
.:!:..-!
CC
= -)4 16
ill
1
1F
=1
x 16
1
+
15 x 16° = 3110
At last!
1F
It agrees.
1-35
Binary subtraction is not essential if you can subtract
in hex. However it is included to complete the arithmetic
operations in both formats. From a previous hex example,
D -5 = 8
1101
D = 13 = 1101
-0101
5 = 5 = 0101
1000
As in hex subtraction start with the number to be subtracted,
0101 in this example. Complement it , that is each 0 becomes 1
and each 1 becomes o. Then add 1. This will produce the negative value of the original number (-5 = 1011 below).
0101
becomes 1010
plus 1 .:!:..-!
= 1011 =-5
Now add the
+1101
ill
minuend 1101
1 1000 = 8
{overflow or carry is ignored.
This subtraction is limited to 4 bits as shown above.
Now calculate 12 10 - 7 10 in binary.
12 10
710
= 1100
= 0111
-7
= 1000
+
1
--------'/
1100 = 12
= =2.
1 0101 = 5
~+1001
1001.-J
Perform the following 8 bit subtraction &
11010111
(215 decimal)
-10110100
(180 decimal)
--_/
Contd ...
1-36
Contd.
10110100
= 180 10
complemented = 01001011
plus 1
+
1
01001100
= -180 10
+11010111
+ 21 510
1 00100011
35 10
( overflow
If your data is in hex form already it is more direct
to subtract in hex. If the data is in decimal and conversion
has to be made to binary first, it is your choice whether you
subtract in binary or hex. If the answer is needed in hex, then
hex is preferred.
1-37
Here is the last question for this chapter.
in binary.
10110100
-11010111
Calculate
-------/
11011101 which equals -35 10 •
This is the previous question with the order reversed.
e.g., 180 10 - 21 510 = -35 10
Details are.
( 21 510 )
(complemented)
11010111
00101000
+
1
00101001
(two'S complement) = ~21510
+10110100
(+18°10)
(which is a negative answer)
11011101
To calculate its positive value.
11011101
00100010
+
1
00100011
= 35 10
Therefore the answer 11011101 2
= -35 10
-
2-1
ACCUMULATOR OPERATIONS
The 6800 microcomputer is capable of a simple task such as
the addition of two numbers or a complex task such as the control
of a piece of electronic equipment. In both cases the task is
defined by a series of instructions to the computer, usually
referred to as a program.
Many program formats exist, the most fundamental being
machine code in which a series of 8 bit words are entered in the
computer via switches on the front panel of the computer.
The next level up is the expression of each instruction as
2, 4 or 6 hex characters, permitting entry via a keypad which ha~
one key for each hex character. This still is a form of machine code.
For longer programs it is very tedious to generate hex
codes for each machine language instruction. The solution is
to write the program in assembly language, in which each
instruction is in an abbreviated English format. The computer
itself then converts this assembly language program to machine
code, using a ready-made program called an assembler.
Higher still in the hierarchy of program format~. are
languages like BASI~, oriented to mathematical calculations in which
algebraic-like statements, including trigonometric functions, are
interpreted into many bytes of machine code for execution by the
computer.
Our interest in this workbook is in assembly language and
machine code programs which link the computer to keyboards, printers,
displays, communication devices and external electronic instruments.
Within the 6800 microprocessor (computer without memory or
interfaces to external equipment) there are two "accumulators", A
and B. Within each accumulator 8 bits of data can be added, subtracted or modified via many different arithmetical and logical
operations.
2-1
Contd.
One of the simplest assembly language instruction is
"CLR A", formed from "CLeaR accumulator A', meaning "put a zero in
each of the 8 bits of accumulator A." The machine code for CLR A,
expressed in hex, is 4F. (You don't have to remember the machine
code. )
Write what you think is the assembly language instruction
to clear accumulator B.
-------'/
CLR B, which in machine code is 5F. This instruction
can be written CLRB, omitting the space. Similarly CLR A can be
written CLRA. Machine codes for all assembly language instructions
are provided in Appendix C, at the end of this workbook. Instructions involving accumulators are on the first page of Appendix C.
--
2-2
If a hex value such as 2C is to be loaded into accumulator
A the instruction is
LDA A #$2C
(LDA A = LoaD Accumulator A) •
The # symbol denotes that data follows immediately within the
instruction. The $ symbol denotes that the data is in hex format.
After this instruction is executed, the contents of ACC·A is
---' '-- C
.7
since the LDA A instruction overwrites any previous contents of
ACC A.
The instruction LDA A #$2C is formed of 2 parts.
LDA A (called the operator)which tells
what happens (loading of ACC A),
#$2C (called the operand) which provides
the data to be loaded.
Contd. • •
2-2
Contd .
•
Such an instruction requires 2 bytes of machine code.
LDA A, when followed by the # symbol is known as an immediate
mode instruction; its machine code, 86, is found under the
"IMMED" column, opposite LDAA in Appendix C. The second byte
of the instruction contains the data to be loaded, 2C. Hence
86 2C = LDA A #$2C. Write the assembly language instruction
and machine code to load ACC B with the hex value 7D.
---~/
LDA B #$7D
C6 7D
Appendix G summarizes the use of special symbols such as # and $.
2-)
4D.
Write the instruction to load ACC A with the hex value
Also write the machine code.
--_--....../
86 4D
t 86, the machine code for the "operator" part of
the instruction is also known as an operation code, commonly
called the "op code".
LDA A #$4D
The operand value, 4D, is also the code for the letter 00,
based on the ASCII (American Standard Code for Information
Interchange) code, listed in Appendix B at the back of this
workbook.
For practice use this table now to confirm that the
ASCII code for Z is 5A, under column 5 opposite row A.
A spare copy of the Instruction Set is provided at the
end of this workbook. It may be convenient to cut out this
sheet, for use with each problem, instead of continually looking
in the appendices.
-
2-4
Write the assembly language instruction and machine code
to load ACC A with the ASCII code for the number 8. See Appendix B.
LDA A #$38
86 38
~from Appendix
ASCII codes.
The ASCII codes for the numbers 0 to 9 are easy to remember,
being 30 + N where N = 0 to 9.
B -
Another form of the immediate instruction to load an
ASCII code is seen in
LDA A #'Z
(note the apostrophe)
in which the apostrophe denotes that the ASCII code for the letter
Z is to be loaded. Hence the computer on assembling (converting to
machine code) the above instruction automatically provides the
desired ASCII code for the second byte of the machine code instruction. The resultant machine code is still 86 SA since this is still
an immediate mode instruction. Such an instruction in which the
computer provides the appropriate code for the desired character is
often referred to as a "literal" instruction.
Write the literal instruction and the resultant machine code
to load ACC B with the ASCII code for the number 7.
LDA B #'7
c6 37
' - opposi te LDAB under Il'fiMED in Appendix C
2-6
.--.
Now write two instructions, the first to load ACC A with
the hex value OF, the second to load ACe B with the ASCII code
for the letter F (using a literal). For each instruction provide
the machine code on the left side of the assembly language
instructions.
_ _ _----.J/
86 0F
C6 46
LCtA A #$0F
LCtA B #"'F
The first instruction loads a hex value, OF, into Ace A.
The second loads an ASCII code for the letter F into Aec B. If
the difference is not clear, please reread the question and answer.
If the above two instructions were executed in the order
listed ACe A would take on a value, OF, and ACC B a value of 46.
This example although trivial shows the beginning of a program,
a series of instructions executed by the computer which modifies
the contents of an accumulator or a memory location (discussed
later).
.....
2-7
Write the assembly language instructions to load ACC A
with the ASCII code for A and load ACC B with the hex value OA.
For each provide the machine code.
86 41.
C6 0A
LCtA A #'''A
LCtA E: #$0A
_-----J/
OF.: LDA A #$41.
Again note the distinction between a hex value and an ASCII code.
The above machi~e code and instructions are part of an
assembler listing, the printout produced by the assembler when
converting assembly language instructions to machine code.
The addition of 2 hex values, JF and 27,
performed by
4F
E:B 3F
88 27
\....Y-'
elf;,: A
ADD A
ADD A
2-8
........
in ACC A can be
(Adds JF + 0 = )F in ACe A)
#$27 - (JF + 27 = 66 16 in ACC A)
#$3F'"
.~
machine
code
assembly
language
instructions
Rewrite the. above, using 2 rather than
providing the machine code.
86 3:F
88 27
LOA A
ADD A
#$3:F
#$27
J instructions, again
-----~/
This method is preferable to the one
above since it is shorter.
2-9
~
The memory of a computer, where data is stored, can be
envisaged as a series of mail boxes, each with a 4 character hex
address, e.g. l4D5, and the capability to store one byte of data.
'rhe instruction
LDA A $12B7
(no # this time)
loads ACC A with the 8 bit contents of address 12B7, without
destroying the contents of 12B7. Such an instruction is known as
an EXTENDED mode instruction, requiring one byte for the operator
(LDA A) and 2 bytes for the operand ($12B7). Hence LDA A $12B7
becomes B6 12B7. The B6 is found under the EXTND heading, opposite
the LDAA instruction in Appendix C. The total number of bytes
required {J} is found two columns to the right of B6, under
the # column.
Contd •.•
2-9
Contd.
Write the assembly language instructions and machine code
to load accumulator B with the contents of address 06E4.
F6 06E4
LDA B
$e6E4
-------.1./
If address 06E4 contains JF then ACe B will contain )F after
execution of this instruction. In the above instruction
LDA B is the operator while 06E4 is the operand, denoting
the data source.
2-10
Write the assembly language instructions to add the
contents of memory addresses lCOO, lCOl and lC02, the answer
residing in ACC B. ...Provide the machine code •
F6 1.cee
FB 1.C01.
FB 1.C"32
LDA B
ADD B
ADD B
$1.C~10
-------'/
$1.CI2I1.
$1.Ce2
2-11
The accumulators are used for many purposes within a
program. Data, after being processed in an accumulator, usually
is stored in a memory location, e:',g.,
STA A $064c
which stores the contents of ACC A in address 0640 but does not
destroy the contents of ACC A. This instruction, referencing a
4 character hex address, also is "extended" mode. Write the
machine code for the above instruction.
_ _ _--J/
87 12164(:
·l.. address
·'
STA A (extended mode)
2-12
Write the assembly language instructions and machine code
to add the hex contents of addresses 14no and 14D1. then store
the sum in address 14D2. without using ACC A.
If 14no contains JE (14DO/JE) and 14Dl contains B5 (14Dl!BS) ,
what will the hex value in address 14D2 be when this program is
executed?
_ _ _--J/
$14De
$1.4D1.
$1.4D:2
LOA B
ADD B
F6 1.400
FB :1.40:1.
F7 1402
STA B
(ACe B/JE)
)E +
B5 = F)
14D2/FJ
(ACC B still contains F3)
JE
start
BeD E
1
2
FlO
+B5
FJ
start-~4
2-1J
To place a particular value in a particular memory address
it is first necessary to set it into Aee A or B. With this in mind
write the assembly language instructions and machine code to put
the hex value JB in address 12EJ.
_ _ _--J/
86 3B
87 1.2E3
LDA A
STA A
#$38 }_ assuming use of ACC A.
$1.2E3
Such a procedure is known as initializatio~, providing a particular
memory address with an initial value, for use during a program.
2-14
Write the assembly language instructions and machine code
to initialize address 0439 with the ASCII code for the letter G,
with the computer providing the ASCII code.
86 47
87 (1439
LDA A
# ..013
STA A
$0439
---~/
Again it is not necessary to memorize the machine code for the
instructions. However, the 86 and B7 values will soon become
quite familiar.
2-15
The instruction SUB A $1524 subtracts from accumulator A
the contents of address 1524. Write the assembly language
instructions and machine code tOI
(a) ADD the contents of addresses 13C4 and 13C8
(b) then SUBTRACT from this the contents of address 13CA
(c) then STORE the result in address 1)CC.
_------..1/
B6 :1.3C4
BB 1.3C8
Be 1.3CA
87 :1.3CC
Lr..A A
Ar..[) A
SUB A
STA A
$1.3C4
)
$:1. -"-'8
:-~~ ) -assuming use of ACC A
$1.J:I_oA )
$13CC
2-16
An instruction which will produce the negative value of
the contents of ACC A is
NEG A
(NEGate accumulator A).
If ACC A contained 04 before execution of NEG A it would contain
FC (-04) after execution. The machine code or operation
code (op code) is 40 as seen in Appendix C opposite the
2's complement (Negate) instruction.
Like the CLR A instruction NEG is under the
INHERent column, being complete within itself; that is it
does not require another byte for the operand.
Write the assembly language instructions and machine code
to store the value -JC in address 095A.
_ _ _-----J/
86 3C
40
87 1!:195A
LDA A
NEG A
STA A
#$3C
$t195A
Address 095A now contains 04 (-JC)
2-17
Memory addresses referenced in an instruction normally
require 2 bytes (4 hex characters) to describe them, e.g.,
LOA A $12A6, requiring an EXTENDed mode instruction. Memory
addresses below 100 16 require only 1 byte to describe them, as
is seen in a DIRECT mode instruction, e.g.,
LDA A $4A
which loads ACC A from address 004A. The machine codes for
DIRECT mode instructions are in Appendix C. For the above
instruction the machine code is
96
4A
'-v-' "-v-'
address 004A
LDA A (DIREC'! mode)
L
Contd ..•
2-17
Contd .
•
Write the instruction to store ACC B in address 66 using a
DIRECT mode instruction. Write its machine code.
STA
E:
---_/
$66
Aside from requiring fewer memory locations to stor~ the
instruction a DIRECT mode instruction requires fewer machine
cycles to execute as seen in Appendix C. Large programs often
use addresses below 100 as a "scratch pad" storage area, e.g.,
for storage of counter values, or temporary storage of a byte
of data. Use of this area of memory saves memory bytes and
reduces execution time.
2-18
The instruction TAB transfers the contents of ACC A to
ACC B. Similarly TBA provides the reverse transfer. Using as
few instructions as possible, swap the contents of the two
accumulators. Memory addresses below 100 16 are available (use
DIRECT mode only). Write the assembly language instructions
and machine code.
---_/
97 50
1.7
[)6 5~3
STA A
$50
(or your choice of address)
TBA
LDA
$5~
(or your choice of address)
E:
Q)
50~
B
4Q)
A/
Counter-clockwise execution of the above flow diagram would
utilize TAB (op code 16).
2-19
Accumulator A can be incremented (1 is added to it) via
the instruction
INC A (INCrement accumulator A)
for which the op code is 4C.
Similarly DEC A (DECrement accumulator A) will decrease
its contents by 1. Its op code is 4A. Accumulator B also can
be incremented or decremented.
Calculate the contents of each accumulator after the
following instructions are executed.
CLR A
CLR B
INC B
ADD A
ADD A
TAB
NEG A
#$2C
#$16
INC A
Ace
ClF.: A
ClF.: E:
INC E:
ACC A/BF
ACC B/42
ADD A
ADD A
TAB
NEG A
FF
-42
INC A
BD
.±-!
BE
Therefore -42
= BE
A
Ace
fl
#$2C
#$16
0
f:t
2C
f,1
4'-'
.::.
i
:1
1
42
BE
4'-:'
0::..
ElF
4'::..-
42
/
E:
2-20
Sometimes it is necessary to clear (force to 0) or set
(force to 1) specific bits of an accumulator, without disturbing
the other bits of the accumulator. This is accomplished via the
AND and ORA operating on the accumulator. The AND instruction
clears specific bits while the ORA instruction sets specific
bits. The instruction
AND A #i5A
(machine code 84 SA)
performs the "logical AND" operation (not addition) bit by bit
with ACC A and the data SA being inputs and ACC A holding the
result.
In the "logical AND" operation each bit of the result
will be 1, if and only if both the corresponding inputs are 1.
Looking first at bit #7, below, one of the two inputs has a zero.
Therefore bit #7 of the result is zero. Complete the bottom line
showing the contents of ACC A after the AND A #$5A instruction is
executed ~
bit #7 J r11
1
1
0 - ACC A (before)
1
1
0
0
0
1
1
0
1
1
1
0
0
1
0
0
1
"'---
0
1
-5A
0
,-
0
~
1
ACC A (after)
---~/
1
1
0
0
1
1
0
0
0
0
1
0
1
0
\.
\.
\,,,
0
1.. at
result
0 since
leas is
t one
of the
inputs is o.
~_.;z-..-_ _--a._-.a_~
2-21
If address 14A2 contains 70, what will ACC A contain
after execution of
LDA A $ 14A2
AND A #$BF
JC
----/
7
6
543
2
1
o ...-bit II
1
1
1
1
0
1
1
1
L{Contents of 14A2
to ACC A
1
0
= 3C
7C
=
0
1
BF
=
1
0
0
0
1
1
1
1
1
1
0
0
Bit #6 is guaranteed to be zero regardless of the
of address 14A2 since the "mask word", BF contains a zero
The result can be shown as
XOXXXXXX
where X denotes the original data in ACC A before the AND
operation. If the purpose of this operation was to clear
of the data in address 14A2, the modified data would then
back in address 14A2 by another instruction, STA A $14A2.
contents
in bit #6.
bit #6
be stored
2-22
Write the assembly language instructions and machine code
to clear bit #3 of the contents of address 1256.
-------'/
Contd •••
2-22
Contd.
86 :1256
L[:IA A
84 F7
87 1.256
AND A
5TA A
4
7
$:1256
#$F7
$1.256
3
2
1
x
o ...bit #
Contents
of 1256
1
~I---X-=---~~~-T--~
contents
~
X represents undisturbed data
· # = 0
.
X"-• 0 = 0
B1t3
S1nce
symbol for
logical AND
J
could be 0 or 1
If X = 0, then 0.0 = 0
If X = 1, then 1.0 = 0
Therefore X.O = 0
" X
All other bits are unchanged since
X.l = X
If X = 1, then 1.1 = 1
If X = 0, then 0.1 = 0
Therefore X.l =,X
same as before
~
2-23
Similarly all bits, except a specific bit, of a
particular. address can be cleared by the appropriate "mask word".
Write the assembly language instructions and machine code to clear
all bits, except bit #6, of address 065E.
86 f165E
84 40
87 t165E
LOA A
AND A
5TA A
$065E
#$40
---_/
$~~165E
iii
bit #6
(40 = 01000000)
Since only bit #6 of the mask word = 1, then only bit #6
of the original contents of 065E will be retained. All other bits
of the result will be zero. This technique will be used extensively
later in this workbook.
The above AND instruction could be rewritten in terms of the
binary value of the mask word e.g.,
AND A #%01000000
The % symbol indicates that a binary value will follow. This form
is often useful to both the programmer and the user in quickly
determining which bits are cleared.
----
2-24
An ASCII code, produced by an external device, such as
a keyboard requires only 7 bits to describe it. The 8th bit
(bit #7) may be 1 or 0 depending on the particular data source.
Assume that an ASCII code is now in ACC A. Write the assembly
language and machine code instruction to clear bit #7 of the
ASCII data. Use the binary version of the mask word in your
answer.
_ _ _----J/
84 7F
AND A
#~0~11~~1~
Note that the machine code instruction is still expressed in hex
even though the assembly language instruction uses a binary mask
word.
In summary a 0 is used in the mask word of an AND
operation for each bit that is to be cleared. All other bits of
the mask word are 1.
2-25
We have seen how to clear specific bits. Let's look at
a method to set specific bits. For this purpose the "logical
OR" operation is used (sometimes called INCLUSIVE OR). Given 2
bits as inputs the logical OR output will be 1 if either the
first input OR the second input OR both inputs are 1. Stated in
logical form
~z ~C + D ~
output 'one tlOgical
other
input
OR
input
symbol
(not addition)
The instruction ORA A #$08 will perform the logical OR operation
with ACC A contents and the mask word, 08, as inputs. The result
will reside in ACC A. If 144A contains $CA, what will be the
result after execution of
B6 144A
IDA A $144A
8A 5C
ORA A #$5C
Contd •..
2-25
Contd.
Ace A/DE
2
0
1
O~bit
0
3
1
1
1
1
1
0
1
1
1
1
0
0
0
7
6
5
4
CA =
1
1
5C
0
1
0
0
1
1
0
=
#
DE
The mask word 5C (01011100) with a 1 in bits #2, J, 4 and 6
ensures that these bits are set, regardless of the original
data in address 144A. All other bits remain the same.
2-26
Write the assembly language instruction and machine
code to set bits #2 and #7 of the data in address o6A4, without
changing the other bits of this data. Use binary format for
the mask word.
----_/
86 06A4
E:A E:4
87 €16A4
LDA A
$€16A4
OF.:A A
STA A
#~'-;::t ~~1 ~j~~UZ1:t (10
$06A4
In summary a 1 is used in the mask word of an ORA operation for
each bit that is to be set. All other bits in the mask word are O.
2-27
Now set bit #3 and clear bit #5 of address 16n6.
binary format for the mask words.
86 1.6D6
E:A 08
84 DF
LDA A $1.6D6
87 16D6
$:16D6
OF.~A
A
AND A
5TA A
----'/
#:..~00001.000
#~·~:11.0:11.:111
Ix [
X
X
Use
set bit #3
clear bi t #5
10 I X 11 I X I X I
= unchanged
xl
bit
2-28
Once more now! Set bits #7, 6 and 2 of address lA42
and clear bits #1 and 4. Assume that each bit controls the
lights for one room in an 8 room house. Provide both assembly
language and machine code instructions.
86 1.A42
:3A
C4
f=:~+
ED
6''7
:1A42
.'1
LDA A
OF.: A A
$:lA42
------'/
AND A
#~'~110~~n~1100
# ~.~ 1 :11€1:11 ~~11.
5TA A
$:1A42
(Set 7, 6 and 2)
(Clear 4 and 1)
Although this is the end of the "Accumulator Operations"
chapter several other accumulator operations will be introduced
at a more appropriate place, later in this workbook. You are
probably ready for a change from "bit bashing". Time for a coffee!
--)-1
SYMBOLIC ADDRESSING
So far we have used absolute addresses e.g., 1A42 for
storage of data. When writing in assembly language this is not
desirable for several reasonsl
- until the program is assembled the addresses available
for data storage may not be known.
- if many addresses are used for different purposes it
becomes difficult to remember the purpose of each
address while preparing the program.
- if a program is later modified certain addresses now
used for data storage may not be available, requiring
re-assignment of storage addresses.
The solution is the" use of a "symbolic address" rather
than an absolute address e.g.,
STA A COUNTR
which stores ACe A contents in an address carrying the symbolic
address eOUNTR. ~e absolute address will be determined when the
instructions are assembled into machine code and printed on the
resultant listing. Meanwhile the programmer can continue to use
the symbolic address as if it were an absolute address.
To present an everyday analogy one might suggest meeting
for lunch at "Dan's Place" (a symbolic address), whereas Dan's
Place might be at 146J Main Street (the absolute address).
Write the assembly language instructions to initialize
the symbolic address COUNTR with the hex value JC.
LDA A
STA A
#$3C
COUNT~:
------.;/
3-2
......
Symbolic addresses generated by the programmer can be
up to 6 characters long, the first character being a letter and
all subsequent characters being a letter or a number. It is
good practice to choose a symbolic address which describes the
function, COUNTR perhaps being a counter to keep track of the
number of events that take place when the program is executed.
The only illegal symbolic addresses are A, B and X, the first two
being previously assigned to accumulators. Single letters for
symbolic addresses are almost meaningless and should be avoided.
Write the assembly language instructions to set bit #5
of STATUS, without changing any other bits.
LDA A STATUS
ORA A
#~0010e000
STA A STATUS
Only after the above instructions are assembled into machine code
will we know the absolute address for STATUS.
-
)-)
When the computer assembles an assembly language
program, it needs to know at what address to start. in assigning
each byte of machine code to a memory address. The ORG (origin)
directive to the assembler, in the example below, designates the
starting address. e.g .•
O~:G
$0200
LOA A
STA A
#$3C
COUNTR
This will cause the following address assignments for the
resultant machine code, assuming that COUNTR corresponds to
address 024)
0200/86
}- LDA A #$JC
0201/;C
0202!B7
0203/02 } - STA A COUNTR
0204/4)
To minimize the amount of paper, produced by the assembler. the
address printed is for the first byte of each instruction. e.g.,
LOA A
STA A
0200 :36 3C
02~12 87 0243
#$3C
COUNTR
Write the assembly language instructions and machine code
to clear bit #4 of STATUS, which corresponds to address 124E.
Start the instructions at address 1200. Show the addresses.
_ _ _----J/
:1.200 86 124E
1.2~13 84 EF
1.205 87 1.24E
ORG
LOA A
AND A
STA A
$1200
STATUS
#~~1.1.1.011.11.
STATUS
A very common error is omission of the $ symbol. which
causes the assembler to interpret 1200 as a decimal number
in the above example.
......
3-4
To reserve a memory byte for a specific symbolic
address, the assembler MUST be directed to do so. In this
program
0200
0200 86 3C
0202 87 0243
$0200
ORG
LDA A #$3C
STA A COUNTR
,
J
I
I
0243 0001
COUNTR RM8
1
The last line, COUNTR RMB 1 (Reserve Memory Byte - 1 only)
causes one byte (address 0243) to be reserved and recognized as
the symbolic address COUNTR.
This symbolic address, COUNTR, contains data and must not
be embedded in the middle of a group of instructions where its
contents would be interpreted as an instruction, rather than data.
Such an error is seen in this examples
0200
0200 86 4F
0202 87 0205
0205
ORG
$0200
LOA A
STA
COUNTR RM8
#$4F
A COUNTR
1
Here COUNTR (address 0205) contains 4F after the first
instructions are executed. The next instruction would
from the next address, 0205, whose contents is now 4F,
instruction. It is the execution of the program which
whether the contents of a memory address is treated as
instruction or data.
two
then be
a CLR A
determines
an
To avoid the above p~oblems the symbolic address
COUNTR is located outside the group of instructions forming this
part of the program, as in the first example.
No answer is required in this frame
3-5
~
Write the instructions to initialize DATA5 with the
value A4. Start this program at address 0400 and show a complete
listing, noting" that DATA5 corresponds to address 0462.
_ _ _-----.J/
040f1
t14~~1t1
86 A4
13402
E:7
OF.:Ci
LDA A
STA A
~3462
13462 0130:1.
"
:1.
F.:MB
DATA5
$t:.::140~Z1
#$A4
[)ATA5
• " , ""...,I"
..
J
Label Operator Operand Comment
Field Field
Field
Field
The 4 fields of an assembly language program are seen above.
The operator and operand have been discussed previously. In
the bottom line we see DATA5. a "label". that is a "symbolic
address in the label field". In preparing assembly language
programs. labels start in the first column of the line, while
operators (LDA etc.) start in the 8th column. It is only
necessary to space over 1 column rather than 7 to start the
operator (LDA etc.) since the assembler, on noting the absence
of a label. will automatically print the operator in the 8th
column. Similarly short labels (less than 6 characters) need
only to be terminated by one space; the assembler again will
start the operator in the 8th column. A sample source program
before assembly is shown below.
NAt'1 CiENPF.:O
OPT 0 .. 5
ind"ented one
space to start
in the Operator
Field.
OF~Ci
$12~n3
LDA A STATUS
AND A
#;'~:1:1.:t€11.1:t1
STA A STATUS
for Label Field
start first column
r
:
,
ORG $:t24E
'~STATUS FeE: $FF
END
t
1
st
column
.-:..-.-
It is legal to
have more than
one ORG directive
within a program.
--3-6
The comment field, mentioned on the previous page,
permits entry of comments to improve the readability of a
program. e.g.,
L.DA A #$2£1
STA A NU'·.. ALU
INITIALIZE NUVALU
WITH :2£1 (DECIMAL
.... Commenf Field
Such comments are ignored by the assembler but printed on the
resultant listing. One space is all that is needed to separate
such a comment from the operand field.
A good program should begin with a brief description of
its purpose and perhaps some of its internal details. Whole
lines of comments are legal if the * symbol appears in column 1
of each comment line. These too are ignored by the assembler
but printed on the listing. Both examples are seen below.
:+:
:+:
:+:
:+:
PROGRAM TO OUTPUT TEN CHARACTERS
TO THE LINE PRINTER.
VERSION 38 77/11/12 RWS
:+:
LDA A #$£1A
STA A COUNTR
INITIALIZE COUNTER
WITH 0A (1£1 DECIMAL)
One assumption to make when programming is that someone
else without your help will have to modify your program several
years from now. For this, documentation in the form of good
comments is essential. To put it more bluntly. if it is not
worth documenting it is not worth doing. There will be lots
of opportunity to practice this in the next chapter. No answer
is required in this frame.
3-7
~
Three other directives are needed to form a complete
program. These plus the ORG directive are illustrated below.
NAM
OPT
HEXCHK
0. 5
ORG
$04013
•I
I
I
Program
Instructions
END
The entry following NAM, up to 6 characters long, is a program
name, generate. by the programmer. It will be reproduced at the
top of each page of the assembler's listing, aiding in program
recognition.
The OPT (option) directive has many possible entries.
The 0, above, requests an object (machine code) file to be
produced. Depending on the computer system this file may be
stored on paper tape, cassette, diskette or some other medium.
The S entry requests a symbol table, a list of all symbolic
addresses along with the corresponding absolute addresses, at
the end of the listing.
The last directive is END which terminates the assembly
language program. Without looking up, try to list the 4
necessary directives for a program.
NAM OPT ORG and END.
-
_ _---J/
--3-8
To practice use of these directives write a program
called CLRALL, starting at address 0400, to clear both
accumulators. Yes, it is a ridiculous program.
_ _-----...1'/
NAt1
Cl~:ALl
OPT
OF.:G
0., S
:+:
:+:ClRALl. . . CLEARS 80TH ACCUMULATORS.
:+:
1214121121 4F
121401 5F
ClR A
ClR 8
END
A TRIVIAL PROGRAM
To save space in this workbook the directives will not normally
be shown in the listing, but will be assumed.
Note that END only tells the assembler that this is the end
of the program. It does not halt the program, when it is
later executed.
)-9
~
01121121
:+:
:+:
NAM
PROG68
OPT
OF.:G
0 .. S
$1211121121
F'3:-9
:+:
12Ij,0~3
e1~:::11
EF~ROR
12111212
€11~35
4F
5F
ClF.: A
elF.: E:
In this listing
the assembler has noted
ERROR 209 for the
instruction LDA #$4A.
Can you find the error?
2~39
~:::1€1 0£1€1€1
87 £1427
:+:
lOA #$4A
STA A
$~3427
END
The instruction should be LDA A #$4A or LDA B #$4A.
Assembler Error Codes, such as ERROR 209. are explained in
Appendices Jl and J2.
4-1
INDEX REGISTER
Each accumulator is capable of holding 1 byte, represented
by 2 hex characters. If 2 bytes are to be referenced we use the
Index Register which holds 16 bits (2 bytes or 4 hex characters).
The instruction
LDX #$lF2D
(an
Il~~Diate
mode instruction)
loads the Index Register with the hex value lF2D.
The instruction sequence
021Z10 CE 1.F2D
0203 FF 131.6C
LC'::-::
#$:1.F2D
ST:x:
$016C
initializes 2 bytes of memory with iF and 2D via the Index
Register. Address 016c receives 1F while address 016n
receives 2D, as shown below.
I I
016B 0160 016D ~memory address
Machine codes for Index Register instructions are on the second
page of Appendix C.
Write the instruction sequence to initialize 2 bytes of
memory, 14C4 and 14C5, with the hex value 0640. Include the
corresponding machine code.
1!:11.0~3 CE ~:::164€1
1Z11.03: FF 1.4C4
LD:X:
sr::<
---~/
#$1Z164f.1
$1.4C4
4-2
Initialize 2 bytes of memory, lC80 and lC81, with the
hex value 2C40. Include the m~chine code.
~
----/
#$2C4121
$1.C8121
LDX
ST>::
CE 2C4e
FF 1.C8£1
(lC80 contains 2C)
(lC81 contains 40)
1C80/2C
1C'81/40
The result iSI
~
A symbolic rather than an absolute address may be used
to store the value, e.g.,
CE 1.5D6
FF 1211.6121
LDX
STX
1211211212
•
•
RMB
#$1.5D6
LISTOP
f
(a)
(b)
LISTOP
2
Why does the above example use RMB 2 rather than RMB 11
Initialize a symbolic address POINTR with the hex value
1C60. Omit machine code this time.
_ _ _---J/
(a)
(b)
2 bytes are necessary to store the 2 byte value 1506.
LD>::
#$1.C6£1 (an lOOMED instruction)
ST>~
POI NT F.:
I
F.:t18
2
,
POINTR
le
(an
EXfND instruction)
goes into POINTR
60 goes into the next address above POINTR.
--
4-4
The instruction STX POINTR+l stores the contents of
the Index Register in the next address above POINTR. Write an
instruction to store the Index Register contents in memory, 3
addresses below CONREG.
5r::·::
FF 14A2
CONREG-3
--~/
If CONREG correponds to address 14A5, the Index Register contents
are stored in address 14A5 - 3 = 14A2, as is seen in the machine
code of this listing.
This could be accomplished, one byte at a time, via
accumulator operations; however the above approach is preferred
because of its simplicity.
Another use of the index register is seen in
LD::-::
#t1E55ACi
5T::·::
PO I NTFt~
-4-5
which stores the address, not the contents of MESSAG in the
2 byte address, headed by POINTR. If MESSAG corresponds to
address lBJ4, what will be the contents of POlNTR after
execution ofl
LD~<
#t1ES5AG-1
5T::-::
PO I NT F.:
Write the machine code for these two instructions assuming
POINTR corresponds to address lB6A.
-----------"/
lB3J
Since MESSAG corresponds to address lB34, then
MESSAG-l corresponds to address lBJJ.
132130 CE 1833
121203 FF 186A
LDX
STX
#MESSAG-1
POINTR
~
lMMED MODE (USES #)
4-6
If TOPBLK corresponds to address lAOO and contains 0)
while TOPBLK+l contains 80, what is the 2 byte contents of
U~MPNT (and MEMPNT+l) for each example below?
~
#TOPE:LJ(-:1
t'lEt'1PNT
I
LD>~
ST>::
TOPE:LK
t1Et'1PNT
I
,
I
I
t
t'1Et'1PNT F.:t1E:
2
t'1Et'1PNT F.:t1E:
2
_ _ _---i/
19FF
lAOO -1 = 19FF, one
address below lAOO,
now stored in MEMPNT
and MEMPNT+ 1.
0)80
The 2 byte contents of
TOPBLK and TOPBLK+l is
0)80, now stored in
MEMPNT and MEMPNT+l.
4-7
~
The instruction
CLR :3,X
is interpreted as "Calculate a new address which is the sum of
the Index Register contents and the offset, :3 in this example,
then clear that memory address." The above instruction could
be written as
CLR $3,X
although the $ is redundant for values of 7 or less.
If the Index Register contains l)E4, what address has
its contents cleared by CLR :3,X?
_ _ _---.-.1,/
l)E7
1)E4
X/
+
3
IJE7
= address
operated upon by CLR ),X
This mode of instruction is known as Index Mode. The
instruction CLR X is also an Index Mode instruction, being
a legal contraction of CLR O,X. If X contains 2400, the
instruction CLR X will clear the contents of address 2400.
Similarly LDA A X is a contraction of LDA A O,X loading
ACe A with the contents of the address now in X.
-
4-8
Write the assembly language instruction to store the
contents of ACC A in address 24C0 when the Index Register
contains 24AO.
STA A
$20..
>~
--_/
24Co
-24AO
20
Offsets are positive only, 00 to FF, the offset FF producing a
new address 255 10 above the address contained in X. Symbolic
offsets, e. g. ,
LDA A OFFSET,X
are valid, the value of OFFSET being determined at assembly time.
If OFFSET equals $14 via the assembler directive
OFFSET EQU $14
the result would be the same as execution of LDA A $14,X.
Assembler directives are normally located at the top of a
program, to improve readability
4-9
..-Machine code for Index mode instructions are found
under the INDEX column in Appendix C. Note that
LDA A 3,X (op code A6)
requires 2 bytes as seen by the 2 under the # column, 2 columns
to the right of A6. What does the second byte denote? Take
a guess. Attempt to encode the above instruction in machine
code.
--------/
The second byte contains the offset value, 03 in this case,
e.g.,
~~~
LDA A offset
(Index Mo de)
4-10
The 2 byte contents of
incremented (1 is added to it)
INX
INcrement
Similarly,
DEX
DEcrement
will decrement it.
the Index Register can be
via the instruction
indeX register (08)
indeX register (09)
Write the assembly language instructions to increment
the contents of MEMPNT which now contains the hex value 19FF.
What will its new contents (2 bytes) be after the above
incrementing?
_ _ _---J/
LD>!.
INX
STX
t'1EMPNT
t'1EMPNT
t
I
I
(If not already present in
the rest of' ·the program.)
This J line sequence will be used many times in this workbook to
increment a 2 byte value in memory. Note that the Index Register
(X) still contains the incremented value, 1A00 in the above
example, after STX MEMPNT is executed.
MEMPNT RMB
2
Another application of Index Mode is seen in code
conversion, such as ASCII to Baudot, where each ASCII value
is separated in memory from its Baudot value by 80 16 addresses.
Once the address of the ASCII value is known, the corresponding
Baudot value is obtained by the instruction LDA A $80,X
4-11
To store a message such as "START CARD READER" in
memory, it is not necessary to load and store each ASCII
character of the message. The sequence below will store each
required ASCII code and terminate the message with a null (00).
MESSAG FCC
FeB
ISTART CARD READERI
~3
FCC (Form Constant Character) is a directive to the assembler.
ordering the storing of the appropriate ASCII codes. Two
identical characters are required to define the boundaries of
the message. The slash (/) is popular for this since it is
not usually used within a message.
FCB (Form Constant Byte) directs the storage of a hex value.
00 in this example, to denote the end of the message. Note
the difference between null (00) and the ASCII code for
zero (JO).
Such message entries generate a lot of unnecessary
printing at assembly time as each ASCII character of the
message is listed. The OPT directive NOG (NO Generate)
eliminates the ASCII code listings but includes the printed
message. e.g., OPT O.S,NOG (at ~he top of the program).
Noting the above message, intialize POINTR with the
address one below the start of the message.
LD>c:
STX
I
#MESSACi-1.
POIr'~T~:
I
I
POINTR Rt1B
2
-----/
4-12
Store the message "ENTER DATA" in memory headed by the
label MESS04, and terminated by a null. Initialize MESPNT with
the address one below the start of this message.
LDX
ST>!'
-----/
#MESS(14-:1.
t'1ESPNT
I
I
I
t1ESF'NT F.:t1B
t'lESS04 FCC
FCE:
2
/ENTEF.: DATA/
~~1
One other assembler directive, available but not required above
is FDB (Form Double Byte) e.g.,
FDB $1433,$7
which in this case stores 14 and 33 in 2 bytes, then 00 and 07
in the next 2 bytes. This directive stores an open ended
string of 4 character data, each separated by a comma.
4-13
What will be the contents of ACe A after execution of
the instructions shown below?
LDX
STX
LD::'!,
#MESS04-1
INITIALIZE POINTER WITH
POINTR
ADDRESS MESS04-1
PO I NTF.:
I~~i::
ST::<
LDA A
PO I NTF.:
>!,
GET CHAR VIA
:;.~
~
i
POI NT F.: Rt1B
MESS(14 FCC
FCE:
.-..::.
.·...ENTER DATA/
~3
---_/
Contd ...
4-1:3
Contd.
45, the ASCII code for E in the message ENTER DATA.
POINTR initially contains the address MEsso4-1. After
the second STX POINTR is executed, both POINTR and X contain
the address corresponding to MESSo4. Hence E (ASCII code 45)
is the first data retrieved via LDA A X.
The above sequence, with additions, will be used many
times in this workbook. The advantage of starting with
MEsso4-1 rather than MESSo4 is that X points to the start of
the message when LDA A X is executed the first time.
4-14
contains C4 (12A6 / c4) the instruction
If address 12A6
LDA A $12A6
loads ACC A with C4, the contents of address 12A6.
If address 14AS and the next address contain l2A6
(14A5 / 12 and l4A6 / A6) then
LD::·::
LDA A
$:14A5
::.~
X.·...:12A6
A,.··C4
also places e4 in ACe A, this time via an "indirect" manner,
with X containing the address of the data, 12A6, after execution
of LDX $14A5. Hence this is commonly known as an "indirect" or
"deferred" memory reference.
This process can be extended further.
following initial conditionsl
lCSO / l4A5
14A5 / 12A6
l2A6 / C4
the instructions
LDX
$lC50
LDX
X
LDA A X
Given the
will also place C4 in ACC A via a "double deferred" memory
reference. Before execution of LDX X, X contains 14A5t This
instruction, LDX X, loads X with the contents of the address
now in X, that is with l2A6 the contents of l4A5. The last
instruction then loads C4, the contents of 12A6, into ACC A.
4-15
--
The main point of this chapter probably needs review again.
If X / 13C4 where is the data stored when STA A X is executed?
----....,,/
in address 13C4. The best way to interpret this instruction is
"store the data in Accumulator A via X". that is X points to the
destination •
4-16
~
If X / 02AE and 02AE / B5 what will ACe B contain after the
instruction LDA B X is executed?
---_/
B5
Accumulator B is loaded via X, that is from the address
now in X. This time X points to the source of the data.
.....
4-17
If X / 267E what is compared when the instruction
is executed?
eMP A X
----/
The contents of Accumulator A is compared with the contents
of address 267E.
-
5-1
BRANCHING - ASSEMBLY LANGUAGE
Computer programs in which instructions are executed in
a simple linear manner are almost non-existent. In fact many
decisions are made by computers, in executing a typical program,
to determine what to do next. A program with decisions in it is
described as follows.
The computer may be required to determine if the ASCII
code, now in Ace A corresponds to a valid hex chal'acter t
e.g., 30 to 39 for 0 to 9 or 41 to 46 for A to F. Invalid
characters are to be rejected. Valid ASCII codes are to be
converted to their corresponding hex value, e.g., 39 becomes 9
or 46 becomes OF.
In eliminating invalid ASCII codes the computer must
first eliminate all values below 30. The instructions
COOP A #$2F
(CoMPare acc A to 2F)
BLS
BADHEX (Branch if Lower or Same to BADHEX)
will do this. If the value in Ace A is lower than 2F or the
same as 2F, the program will branch to BADHEXa that is the
next instruction executed will be the one carrying the label
BADHEX.
If the value in ACC A is JO, the ASCII code for 0,
what will happen "after execution of the above 2 instructions?
Take a guess if necessary.
---~/
No branching will take place. The next instruction executed
will be the one following BLS BADHEX.
-5-2
If the first test was passed (no branch since the ASCII
value was 30 or greater), the next test is to check for values
greater than 39, the ASCII code for 9. If the value is 39 or
lower, the program should branch to NUMOK. otherwise it should
continue. Write the instructions to ·do this noting the availability of the instructions I
BLS - Branch if Lower than or Same
BHI - Branch if HIgher than
BRA - BRAnch unconditionally.
Ct'1F' A
#$39
BLS
NUt10K
---_/
o
TO 9.
VALID HEX
The conditional branch instructions BLS and BHI treat
the ACe A contents as an unsigned number, that is all values,
00 to FF are considered positive.
By having available both BLS and BHI (opposite instructions)
the programmer can either choose to branch or not to branch when a
specific condition is met.
So far the program is.
HEXCHK CMP A #$2F
8LS
8ADHEX
••
•
Nur'10K,
I
BAD HE}!,
Cr·1P A
#$39
BLS
NUMOK
MUST BE BELOW 30
MUST BE 30-39
-
5-)
For ASCII codes )0 - 39 we want the hex values 0 - 9 in
ACC A. What instruction, starting at the label NUMOK will do
this, e.g., when key 5 on a keyboard is struck the final contents
of ACe A will be 5, not 35. The program should go to GOODHX when
the correct value is in ACC A. Again assume that the ASCII
code is already in Ace A when the program starts. Show only
the program additions.
SUE: A
E:F.: A
NUt10.:::
#$3:~3
--_----.J/
1100DH~-::
or
NUt'10K
SUB A
#···0
BF.:A
GOODH::<
We now have a
HEXCHK Ct1P A
E:LS
Cr'1P A
E:LS
GOO[)H:X:
#$2F
E:ADHE:X:
#$3S1
NUr'10k:
I
I
I
NUNOK
BADHE>::
SUE: A
#$30
BRA
GOODH:X:
t'lUST BE
E:ELOl,~
NUST BE
3:~~1-3:9
3:(1
--5-4
Now scree n for valu es A to F. Vali d char acte rs in this
grou p shou ld be conv erted from thei r ASCII code to thei
r true
hex valu e, e.g. , OA when A is struc k. For valid char acte
rs
cont inue to GOODHX, the next line, afte r this conv ersio
n. For
inva lid char acte rs branc h to BADHEX.
_ - - - - .. J /
cr'lP A
#$40
BLS
BA[)HE >~
Ct1F' A
#$46
BHI
BADHE>::
SUE: A
#$37
t1UST BE
3:A-4~3
MUST BE GREATER THAN 46
41-46 NOt,J 0A-~3F
END OF ROUT I NE.
The ASCII code for A is 41, for whic h the hex value is
OA. The ~i:ference is 37, whic h when subt racte d from 41
give s
us OA. S~m~larly when F is struc k, 46 - 37 = OF. Calc
ulati ons
are shown below .
FF
41
-OA
.+F6
+C9
37
1 OA
F5
U
F6
j
= -OA
1
When A is struc k
41
ASCII for "A"
(-37)
~ hex code for
A
The fina l versi on of this routi ne (let 's call it
HEXCHK) iss
-
5-5
HEXCHK. .. CHECKS IF CHAR NOW IN ACC A
IS VALID HEX CHAR~ THAT IS 121-9 OR A-F.
ENTER WITH ASCI I CHAR IN ACC A.
RETURNS WITH 4 BIT EQUIVALENT HEX IN ACe A IF VALID
HE::-::CHK C\"'lP A
BADHE~ '::
Ct'lP A
#$3:9
BLS
Ct1P
#$4~3
NUt'10K
A
BLS
Ct'1P A
BHI
SUE: A
CiOODH::·::
NUt10K
BADHE::·::
#$2F
BLS
BADHE::·::
#$46
BADHE>::
#$3:7
,
I
t'lUST BE BELOl.oJ
3:f~
t'lUST BE 3:€1-3:9
t'lUST BE
3:A-4~ 3
t'lUST BE CiF:EATEF~
4:1-4 6 NOf..J f1A-0F
END OF ROUT INE.
THAr·~
46
I
l
SUB A
#$3:121
BF.:A
CiOODH~'::
,
I
I
BADt1ES
IFCC
FCB
lNOT
I",'ALID
HE::·::..···
~3
END
What would happ en if the firs t line was CMP A #$301
---_/
When 0 is struc k on the keyb oard the ASCII code 30 woul
d resu lt.
The firs t 2 line s would then cause a bran ch to BADHEX (norm
ally
reser ved for inva lid char acte rs), since BLS BADHEX reco
gniz es
that the code prod uced is the same as 30. Such an erro
r where
a bran ch instr uctio n is inco rrect for one valu e, is very
common.
Hence a progr amm er shou ld manu ally check for boun dary valu
es,
0, 9, A and F in the abov e progr am.
The labe l GOODHX could prov ide an instr uctio n JMP NEXT,
jump ing to the next progr am segm ent. The BADHEX secti on
could
be temp orari ly term inate d by the instr uctio n BADHEX BRA
BADHEX,
an instr uctio n whic h loop s back to itse lf, prev entin g exec
ution
of "lef t over " code in that memory addr ess.
-.5-6
Modify this HEXCHK program to include the necessary
assembler directives, this time calling the program HEX2C and
starting it at address 1E40. Show only the first and last
lines of the program.
NAr'1
HE::-::2C
OPT
0 .. 5
OF.:G
$1E4€1
HE;<:CHI< Cr'1P A
i
-------'/
#$;~:F
I
BADHE>::
END
Note that all 4 directives appear in the operator field. The
first label of the program does not have to agree with that
used with NAM. The latter usually designates which version is
listed, e.g., version 2C in this example. Updating the version
number when changes are made is a very effective way of denoting
which listing is the latest, an absolute essential as programs
evolve.
.5-7
~
To understand better how the branch instructions
operate one must be aware of the Condition Code Register (CCR)
in which each of the 6 assigned bits may be set or cleared
according to each instruction executed.
5
4
:3
2
1
'I""----::'-~---+----r-__+-__r-
°....-Condition
bit #
Code
__- _ _ r
Register
For example bit #0 is the CARRY or C bit which will be set if an
8 bit addition produces an overflow, the C bit behaving as the
9th bit. The C bit can be set under other conditions, seen later.
Bit #1, the oVerflow or V bit, is set if a 2's complement
(signed number) arithmetic operation produces an answer exceeding
the range of -128 10 (8016) to +127 10 (7F16)' the available range
using an 8 bit signed number.
Contd •••
5-7
Contd.
b
The Z or Zero bit (bit #2) is set when a zero is produced
in a memory or accumulator operation, e.g., CLR A or CLR MEMPNT.
The N or Negative bit (#3) is set when a resultant
leading bit = 1, implying a negative value in the accumulator or
memory.
The I bit will be treated in the Interrupt chapter.
The H bit is used internally by the DAA instruction for
BCD arithmetic operations. (Details in Appendix K )
Each instruction executed affects the CCR bits as noted
in the right column of Appendix C where the state of each CCR
bit, after the execution of each instruction, is shown. For
example, CLR A will clear or reset (R) the N, V and C bits and
set (5) the Z bit. The dot implies no change. The vertical
arrows for the eMP instruction imply conditional setting or
clearing of these bits. For example, CMP A #$72 produces a
subtraction (ACC A minus 72) which sets the Z bit if the result
is zero or sets the N bit if the answer is negati~e an~or sets
the V bit if a two's complement overflow took place_
Detection of the Z bit status is achieved via
BEQ - Branch if EQual (Equal to Zero if no other
.
reference named)
or BNE - Branch if Not Equal
as seen in
DEC A
ALLDUN
which branches to ALLDUN if ACC
on non-zero results when
BEQ
LDA A
AND A
BNE
A = 0-
Similarly
BNE
branches
SUBTOT
#$C2
t'1ATCH
is executed. Will branching occur assuming SUBTOT/JE?
the Z bit state,
What is
_ _ _-.--J/
Yes branching will occur since C2-3E = 2 (not equal to zero),
clearing the Z bit and causing a branch via BNE MATCH.
~
Will the following instructions cause a branch to HIT
if KEDATA contains 291
LDA A
I::
~3260
ST::<
e0
CLF.:
240F
CF'>~
F2
E:NE
t1Et1ADD
X
THIS F'F.~OGf;.:At'1 CLEAF~S
AND LOOPS BACK
UNTIL t1Et10F~'T' A(:l(:tF~ESS
240F Ie
-' CLEAF.:ED
AFTEF~ I.oJHICH E~,::IT
TAKES PLACE
#$240F
t10RCLR
:+:
026~3
~3260
~~U~102
OF.:G
t1Et1ADD F.:t1B
$~1260
2
END
While it is true that the Index Register could remain the pointer
throughout this program, without using MEMADD, we are looking
ahead to programs where the Index Register is used for several
purposes inside one loop, requiring retrieval and storage of
each memory address pointer each time it is used.
--5-14
How many memory locations will be cleared by the
previous program?
---_/
10 16 or 16 10
After CLR X is executed
1st time
2nd time
Jrd time
JL
2400
2401
2402
Hof addresses cleared
1
2
3
15th time
240E
OF 16 (1510)
16th time
240F
1016 (16 10 )
Tables like this are useful to ensure that the exit from a loop
takes place at the correct point, not one loop too soon or late.
For example, if the problem was to clear 2016 locations such a
table ensures that 241F is the correct reference address for the
exit.
-
5-15
Modify the previous program to clear 100 10 memory
addresses, starting at address 2400. Show only the changes.
-----"/
CPX #$2463 is the only change.
10010 = 64 16
Memory Address
2400
2401
2462
2463
# of addresses cleared
1
2
5-16
....What would be the effeci~ if the label MORCLR appeared
opposite the first instruction, e.g.,
MORCLR LDX #$2400-1
rather than in its present location? Refer back several frames
for the program.
---_/
The program would be re-initialized after each loop, hence it
would clear address 2400 each time in a continuous loop. This
is a fundamental error which ev~ybody makes at least once,
including you and me. The only question is when. More important
though is to be aware of this potential problem. The solution
can be summarized by
LOOPBACK IS ALWAYS BELOW INITIALIZATION
Initialization in the previous program sets up MEMADD with 2;FF,
its initial value. The program loops back to MORCLR, below the
initialization in the original program.
5-17
Good programming requires good planning. While many
planning methods are advocated today, one of the simplest and
most effective is the flow chart, shown below.
\N'T'AL.lZE
A t>t>ResS
POIWTE'R
Note that a flow
chart depicts
functions, not
specific instructions.
PO, NTEs:l-r X
INCPo..EMENT
ANI>
SToRE
CLEAR
MEMORY
IU)I>R£SS
HAMEl>
v,~
X
Here operations such as initialization, clearing,
storing, etc., are shown inside rectangles. Decisions are
depicted by diamonds which have multiple exits, the chosen
path depending on the decision made.
A good flow chart represents the major effort in
preparing a program. Converting it to instructions, once you
are familiar with the instruction set, should take less time
than flow charting. A flow chart is also useful in documenting
a program for use by future users.
No answer is required in this frame.
5-18
The program to clear 64 16 locations could be handled by
using a counter, with an initial value of 64 16 , which is
decremented after each address is cleared. Exit would then take
place when the counter is zero. Flow chart such a program.
---------/
IN'T"'L.12G
- COUNTE'I\
- ADI>P.'ESS
><.= UPDATE E>
At>OR6SS
CLEAR MSM
AOl>RESS
DECReME'NT
COU~Te~
To next part of longer program.
5-19
Now write the program to clear 100 10 (64 16 ) locations,
starting at address 1200. The program itself is called MEMCLR
and should start at address 0800. Include the necessary
assembler directives. The instructions INC or DEC may be
useful to you.
~
--_-----..1/
NAt'1
OPT
OF.:G
1218121121
t1Et·1CLF.:
0 .. S
MEMCLR... CLEARS 1121121 (DECIMAL)
STARTING AT 12121121. USES X.
1!:18f1f1 B6 64
t1Et'1CLR LOA A
121:=:1212 87 12126121
STA A
f18~35 CE 1iFF
LD>::
ST::·~
0:=:1218 FF 121261
(1E:eB FE 121;;;:61 t'10F~CLR LO::-::
eE:eE 1-3::::
IN::~
0E:I-3F FF 0261
ST>~
1!:1812 6F e~3
CLF.:
1218:14 7A 12126(1
DEC
1218:17 26 F2
8NE
#$64
COUNT
MEMORY LOCATIONS
OR LDA A #:1.(1121
INIT COUNTEF.:
#$12e~3-1
t1Et'1ADD
t1Et'1AOD
SET UP ADDF.:ESS PO I NTEF.:.
r1Et'1A[:'D
GET ADDF.:ESS
AND CLEAF.: IT
LAST ADDF.:ES5?
NO. TF.:'T' AGAIN
::.~
COUNT
t10F.:CLF.:
f
t
1!:126~3
12126121 01211211
0:;~61.
00~:::12
ORG
COUNT Rt1E:
t'1Et1ADD F.:t1B
END
$12126(1
:1
2
COUNT could have been incremented from 0, exit taking place when
count equals 64. Down counting is preferred since it is easier
to detect zero than a specific value (CMP A #$64). Both,
however. are valid.
5-20
In the previous program the task was to clear an
address. In the next program the task is to count the number
of addresses, 0900 to 09FF inclusive, which contain zero. This
time the task itself will contain a decision, to count or not
to count. First flow chart, then write the program.
---~/
C\.1:AR COUNTeR.
".'T f\DDRESS
POIMTSR
X =UPbATE.D
ADDRESS
0200 7F 0262 ZCOUNT CLR
0203 CE 0::::FF
LD:~
ST::-::
1212"~6 FF ~126121
0209 FE €126£1 t'10~:CHK LD;:'::
020C £1::::
IN:>::
£12£1(:1 FF 026121
ST::-::
"32:1£1 A6 "3121
LDA A
£12:12 26 ..3 3
BNE
1212:14 7C 121262
INC
02:17 E:C e9FF SI~
STX
BLANK
SKIPIT
If BLANK is to be tested or compared later. the Index Register
will be needed... for that operation. Hence the second solution,
using the Index Register. is preferred.
The second solution shows how the Index Register can be
used for many tasks within a program since the updated value
(after INX) is immediately stored in memory. releasing the Index
Register for another task.
5-23
Assume that the instruction JSR GETCHR, a subroutine
call which we'll examine in detail in a later chapter, puts the
ASCII code for the key, struck on a keyboard, into ACC A. Use
this instruction within a looping type program to store in memory
the ASCII codes for the keys struck. Start storing data at
address 1200. When the! key is struck. exit from the loop
without storing this terminator character. First flow chart
your program.
_ _ _-----01'/
\NIT
"1)1)RESS
PO'"T&~
GET CHAR
GETCH~: EG~U
$~F00
STOASC... STORES ASCII CODES FROM KEYBOARD
IN SUCCESIVE MEM ADDR STARTING AT ~200.
! TERMINATES PROGRAM.
CALLS GETCHR. USES A AND X.
STOASC
L[:'~:
#$1.2f10-1.
5T:)~
ADDRES
GETCHR
INIT POINTER
GET ASCII CODE
ALLDUN
MUST BE
GETt'10F.: JSF.:
Ct'1F' A
BEG!
LD::"~
# .., !
!
A[:'D~:ES
IN::·::
x: UPoA,eo
PO'HTER
STORE CH"~
ST::<
ADDRES
.....
STA A ....
GETt10~:
BRA
UP[:'ATE ADDF.:ESS
AND STORE ASCII CODE
AN [:a BACK AGA I N.
ALLDLIN
ADDF.:ES Rt1B
2
Here the test takes place before
the task, to avoid storing the !
character.
5-24
Branching instructions recogn~z~ng signed (~) values area
BGE - Branch if Greater or Equal
BGT - Branch if Greater Than
BLE - Branch if Less than or Equal
BLT - Branch if Less Than
BPL - Branch if PLus
BMI - Branch if MInus
Flow chart a program to count the number of
occurrences of values between! 26 16 inclusive, within the
memory range 0800 - OBFF inclusive. Manually check your program
for proper branching for values of !26 and ±27.
---_/
SET up L'M'TS
I N I" ADOk POINT
CLEAR COUNTER
)(: UPDATED
ADDRESS
GET CONTE"'TS
5-25
From your flow chart on the previous page, write the
program.
_ _ _..----.J/
MEMCHK. . . COUNTS OCCURRENCES OF +26 TO -26 HEX
IN MEM ADDR 0800-0BFF INCLUSIVE
02121121 86
£12~32 87
0205 4~3
021216 E:7
02~39 7F
1-320C "("F
t!.120F CE
~:::1212 FF
121215 FE
"32:18 fiE:
~3219 FF
021C A6
t12:tE 8:t
£1221 2E
£1223: 8i
~1;;;::26 2(:'
..:::122:=: FE
='
- t_,
"3228 121'
€122C FF
"::1~:2F FE
0232 8C
k1;;::3:5 ~:6
26
t1Et'1CHK LDA
£1271
STA
NEG
02;~0
STA
1-3274
eLF.:
&::1275
CL~:
L.D>::
07FF
ST~-.::
0272
0272 GET8'T'T L[:IX
A
A
A
A
#$26
HILIt1
SET UPPER CHECK VALUE
SET LOI.a~EF.: CHECt< '·.·'ALUE
LOLIt'l
HIT
HIT+:t
#$080121-1
INIT PO I NTEF.:
t'1Et'1PNT
t'lEt1PNT
IN>-~
..:::12?2
&::10
£1271
~:::1C
"32(?~:::1
€1~::'
€1274
ST~<:
t1Et'lPNT
LDA A
Ct1P A
BGT
eMP A
BLT
LD::<
>~
HILIt'1
NOHIT
LOLIt'1
NOHIT
HIT
GET NE>::T ADDF.:E5S
GET CHAF.:
..
....
_... - -....
'f
~t.:.
IF SO IGNOF.:E IT
<26?
IF SO IGNOF.:E IT
IN~<:
£1274
(127:2 NOHIT
€1BFF
ST~"t,
DE
BNE
£12';:'0
02710 '3(11.::11
10271 121001.
0272 a;:n3f12
0274 ~:::n3f12
LD:~
CF'>~
LOLIt.., F~t"'B
HILIt1
F.:t·lB
t1Et'lPNT Rt1B
HIT
F.:~18
HIT
t'1Et1PNT
#$0E:FF
GETBIT'T
1
:1
.-.2
~
ADD i
NO..
TO HIT
BACI< AGAIN
5-26
Previously we saw how to store a message in memory. It
is time to print such a message. For now, assume that the
instruction JSR PRINT, a subroutine call, prints the contents of
ACC A as one ASCII character on a printer. Assume that the
label MESSAG heads a stored message, in ASCII format, terminated
by a null. Flow chart and write a program to print this message,
using the JSR PRINT instruction. If you are stuck, look at the
first two instructions of the solution
IN'T POINTER
TO MESSAGE
------J/
MESSPR... PRINTS MESSAGE THAT IS STORED IN MEMORY.
CALLS PRINT SUBROUTINE FOR EACH CHARACTER PRINTED.
USES A AND X PLUS PRINT SUBROUTINE.
Lei?::
ST:X:
MORPRT LD>::
INX
ST>::
LDA A
BEG!
.JSF.:
BF.:A
ALLDUN
t1ESSPF.~
x= UPDATED
PO\NTER
GeT CHAR.
#t1ESSAG-:1.
POI~TR
INIT MEM POINTER
POINTF~
GET ADDRESS OF CHAR
GET ASC I I CHAF.: INA.
POINTF.:
'.J
....,
ALLDUN
PF.:I NT
PF.: I NT IT
t'10F.~PF.:T
BACI<
FOF~
MOF~E
I
I
POINTF.~
~:t1B
t1ESSAG FCC
FeB
PR'NT CHAR
2
. . . FILENAME?...1
o
Note the test before printing
to avoid trying to type a null
which cannot be printed.
5-27
Data stored on a diskette, a magnetic mass storage
device, is usually written in blocks of 80 16 characters at a
time from a buffer. which is a specific block of memory. In
such an operation the X register must be used both for
retrieving data from the "source" memory address and for storing
it in the "destination" address. For this 2 pointers must be
initialized. For each byte moved. each pointer must then be
updated for use by X. With this in mind, flow chart and write
a program to move the memory block 0600 - o6FF to 0800 - 08FF.
, N\T SOURCE
ANO DESTIN.
POINTER.S
UPPATE
SourtcE
P01NTER
G-Ei
8YTE
---~/
t'10VEIT LDX
ST:X:
L[:.:>::
ST::-::
t'l0 1",1 E:'T1T L[:e::-::
IN::-::
ST::-::
LOA A
LD;·::
IN::·::
UPDATE
ST::-~
DES-rlWAT lOti
STA A
POIr.'TE~
STORE 8'C'TE
#$(160(1-1.
SOURCE
OEST
SOUF.:CE
INIT DESTINATION ADDRESS
SOURCE
X
DEST
GET NEXT SOURCE ADDRESS
GET A BYTE
DEST
GET DESTINATION ADDRESS
AND STOF.:E 8'T' TE
LAST B'r'TE?
NO. AROUN[) AGA I N
CP::·::
#$"~1:3FF
BNE
t10VB'r'T
I
,
I
I
SOUF~CE
DEST
F.:t·lE:
Rt'lE:
END
INIT SOURCE ADDRESS
#$~~1:30€1-:1
2
2
-5-28
Earlier we saw how to increment a 2 byte counter
without using the X Register. Similarly a 2 byte counter can
be decremented without using the X Register. A special
condition, shown below, exists when the least significant byte
is zero, before decrementing, since both bytes will have to be
decremented this time.
Least Significant Byte
Before Decrementing
After Decrementing
.~
00111011 00000000
~ ,111~111.1
Count
Count +1
Write the instructions to decrement the two byte counter COUNT,
recognizing the special condition above. The instruction TST
(TeST or "compare to zero") is useful here.
--_----.J/
TST
BNE
r.. EC
DECLOW DEC
COUNT+1.
DECLOW
COUNT
COUNT+1
CHECK LEAST SIG BYTE FOR ZERO
IF NOT e IGNORE MOST SIG BYTE
IF LEAST SIG BYTE e DEC MOST
ALWAYS DEC LEAST SIG BYTE
This sequence of instructions is most useful if a 2 byte counter
must be decremented when the Index Register is not available to
do it. This process also can be extended to a 3 byte counter.
5-29
The program listed below is a slightly shorter version
of HEXCHK, developed earlier in this chapter. This one uses
signed branch instructions which had not been discussed when
the original program was developed.
HE>::CH~(
#$30
BADHE>::
#$09
ENDHE>::
#$137
#$0F
BELOI.oJ -.
-::.3.
BHI
BADHE~-::
46-30-7=€1F.
Cr-1p A
#$09
BADHE>(
4:1-30=0A 8ELOl.oJ A
SUB A
BMI
Ct-1F' A
BLE
SUB A
Ct-1P A
BLE
BELOleJ 313
ABO.....E 313
ABO.....E F
ENDHE:x:
BAC'HE::·(
Since either 30 or 37 had" to be subtracted to convert
to hex, )0 was subtracted immediately. Branching on a minus
value is now possible, eliminating a COOP instruction. While
the purpose of this workbook is to help you learn fundamentals
rather than write "tight" programs, the above listing is
included to point out that the shortest programs are not
necessarily the most readable and vice versa.
Time for a break.
This was a long chapter.
BRANCHING - MACHINE CODE
Even when writing very short machine code programs it
is highly desirable to start with assembly language instructions
and then assemble them into machine code. Manual assembly of a
program raises a problem in that the address for MEMADD in the
instruction STX MEMAOO is often not known until MEMADO RNIB 2 is
encountered, perhaps many instructions later. The solution
proposed is the one used by the computer when it assembles a
program, that of processing the assembly language program twice.
When the assembly language program is read the first time, an
absolute address is assigned to each label (symbolic address in
label field). During the second reading, machine code is
produced for each instruction.
To assign absolute addresses to labels requires knowing
how many bytes each instruction requires. This data is available
in Appendices C1 and C2, under the # column, for each mode available. Assuming Extended Mode for the instruction LDX MEMPNT, we
see J in the # column for the "EXTNO" mode opposite the LDX
instruction.
For the program below assign the appropriate addresses,
starting at 0618. Addresses already are assigned to the first
2 instructions.
06:18
(161A
INIT
LOA A
#$1.7
STA A
END VAL
L.[:,~<
#$€16D7
ST>~
t1Et1ADD
RTS
ENDVAL F~t'1B
tolEt'1ADD Rt1B
0618
061A
061.0
062€1
0623
0624
0625
INIT
END...·'AL
t'lEt'lADD
:t
2
l.DA A
#$17
STA A
END'·lAL
LO~'~
#$0607
ST:X:
RTS
t1Et1ADD
F~t18
:t
~:t'1B
2
/
-
6-2
Now that all addresses are known, complete the assembly
operation by assigning the machine code for each instruction.
No entry is required for the labels ENDVAL and MEMADD at the
end of this program.
06:L:=:
INIT
LDA A
#$1.7
ti6iA
STA A
EN[:IVAL
":361D
L())·::
#$06D7
"~1620
STX
t1Et'1A[)[:'
103623
~~TS
0624
EN[:IVAL Rt1B
:1
0625
t,otEtil AD[:r Rt1B
2
/
0618 86 17
INIT
LDA A
#$17
STA A
ENDVAL
LDX
#$06()7
ST::-::
t'lEt1ADD
:+:
e61.A B7 0624
:+:
1o:::161.D CE €16D7
:+:
e620
FF
121625
:+:
~:TS
€i623 39
0624 ":300:1
:+:
EN[)VAL Rt18
1
:+:
1216~~5
01211212
t1Et1A[:t[:' Rt18
2
6-3
...In general it is easy to work with the machine code for
the 6800 microcomputer. Only one area, that of encoding branch
instructions, requires extra care. In the instruction sequence.
CPX
BNE
1.36
1.872 26
L[:'X
1874 CE 1.E:78
.JSR
1877 8D 1.F0C
F.~TS
STOF.:TN
:t:=:7A 39
:186F 8C 1.A7F
ISTART
STORTN
#8IGSOR
OUTt'1ES
the code for BNE is 26. The next byte, 06, is a forward
reference to STORTN, 6 bytes beyond the byte following 06.
Better read that again! When the microprocessor has fetched
06 from memory and is processing it, to determine the address
to which to branch, the program counter (PC) contains the
address of the next byte, 1874. It is 6 bytes (hence the 06)
from 1874, the PC contents, to 187A, the address of STORTN.
2
4
5.-~ 6
1874
1873
1876
1878
1879
187A
06
while proCeSSing" PC. points
address of
this byte
:J here
STORTN
t
t
If STORTN is at address 187E instead of 187A, while the
BNE instruction remains at the same address, what value is in
address 1873, the forward reference to STORTN for the BNE
instruction?
OA
--_---..J/
187E - 1874 = OA ~ branch offset
target address~ addtess following branch offset
-
6-4
Backward branching is somewhat more challenging. e.g ••
1.A8aa
:1.A83
iA85
1.A87
7FF6 t10RTES LDA A
~~11.
AND A
27 F9
8E(;J.
86 7FF7
LDA A
86
SEF~CSf;.:
84
#$131
t'10RTES
SERBUF
While processing the branch offset F9 (address lAS6) the PC
contains lAS? the address of the next byte. The target
address is lASO, ? bytes backward from the PC value. Hence
F9 (-7) is the branch offset.
To determine this value, F9. the most direct method is
to calculate lA80 - lAS? resulting in FFF9 as a 2 byte negative
value which contracts to F9 as a one byte negative value (refer
to the first chapter for 2 versus 1 byte negative numbers).
For short backward branches the number of bytes can be determined by counting from lASO to lAS7. e.g ••
@ CD®
iA8aa 86 7FF6
iA85
:3fjJ t1fY
® @
27 _
iAB?
86 7FF7
:tA83:
CD
Since the separation is 7 bytes then -7 can be converted to F9.
The missing value above then becomes F9. For more than a dozen
bytes this may become tedious. For short branches, however, it
is simple and quick.
No answer is required in this frame.
-
6-5
With more experience in using machine code, you may
prefer to count the number of bytes backwards instead of forward
to obtain the branch offset directly. Using the previous program
this would bea
~~l@
1.A80 ~ 7FFt'
1.A83
1.A85
1.A87
&?fi>
@@
2(
--
~...)
F9 then follows the 27
..
Using the above technique determine the machine code for
the backward branch below. The address for LOOPNO is lA60.
02013
7A :1A60 NOTYET DEC
lOOPNO
02133 27
BEQ
NOTYET
(12£15 4F
ClF.: A
/
G>~e
*
@~
2,·
F:
4(i):J *
*
02013 7H :1 60 NOTl.r'ET (:.EC
lOOPNO
BEQ
NOT'r'ET
02€13
02~35
ClF.: A
-
6-6
NEXCHR JSR
GETCHR
LDX
MEt1A[)D
IN>::
STX
t1Et1ADD
LDA A
X
CMF'
A
#$00
BEQ
ENDLIN
.JSR
OUTERt1
BRA
NEXCH(;:
Manually assemble the program
(opposite) using both the first
and last methods to determine
each branch offset. Machine
code for JSR GETCHR is BD tFOO
and for JSR OUTERM is BD lFOJ.
Start at address 0740.
ENDLIN RTS
12:1740
a.3f1 FF FE
BD
:1Fa.~n~1
/
2
MEMADO Rt'1B
GETCHF.:
NEXCHF.: .JSR
*=
FD Fe FE:
L[:a>::
12:1743: FE 0756
t1Et'1ADD
:+:
IN>~
0746 1.38
FA
:+:
F9 F8 F7
(1747 FF 121756
ST>::
t1Et1AD[:a
LDA A
'.}
.'.,
C~1P
#$&;:1[:1
:+:
F6 F5
(174A A6 0(1
F4 F3
1-~174C
:+:
:=::1 a.3D
A
:+:
F2 F:1
F0 EF
ED
074E 27 1-35
@*
f
:1~..z,~.
(1750 B ~
EE
Q)
EC
®
BEG~
ENDLIN
JSR
OUTEF.:t'1
:+:
(1753 20 EB
:+:
EE:
\
V
+
Backward
branch
counting
(last
method)
,/
(1755
RTS
0756 0002
Rt'1B
END
~~
i t
address machine
2
0740
-.Q.Z.5..2
-.Q.Z.5..2
+---1
0755
-.Q.ZjQ
5
~
=F8AA
code
(forward reference)
FFFF
F8AB
+0740
~FFEB
~
but FFEB (in 2 byte format) becomes EB in 1 byte format (see
Chapter 1). Normally JMP NEXCHR rather than BRA NEXCHR would
be used to avoid offset calculations.
-
6-7
Branch instructions use a one byte signed offset,
limiting the branching range to !127 (decimal) addresses.
Attempted branches beyond this range produce an error at assembly
time. Sometimes programs which were previously error-free now
will cause a branching error when new instructions, inserted
between the branch instruction and the target address, now
produce too great an offset. One solution is to branch to the
end of the present routine, or some other appropriate place
where a ~~P (JuMP) instruction, which can jump anywhere, jumps
to the target address.
Such a solution is also one way to avoid backward
branching in machine code, a pragmatic if not aesthetic solution.
Similarly BSR should be replaced by JSR when writing in machine
code unless memory locations are scarce.
Assume that NUCHAR, at address 0608 is beyond branching
range of BEQ NUCHAR, below. Modify the program to reach NUCHAR.
Show your changes in machine code.
~:)2~Je~
E:1
~~1A
Ct'1P A
#:f.~]A
BEG!
r·JUCHAF.:
.JSF.:
STOF.:E
:+:
1;:,2t!~~::
'-,-:0
.:::.,'
:+:
~12~34
BCI iA64
:+:
Cl2~:f?
3:9
02~~1'j
E:1
/
F.:TS
~~1A
~+.
213(,27 134) ..
11:1
BEG!
.JUr'lPNU
.JSF.:
STOF.:E
:+:
02~Z14
BD :1A64
F.:TS
.Jt1P
NUCHAF.:
Changed lines
are circled.
--
6-8
A problem often encountered in writing machine code
programs is the need to insert a few instructions in the middle
of a program. This results in new addresses for all labels
below the insert (on the listing) requiring re-encoding of the
program.
To prevent or minimize such problems it is desirable to
leave memory address gaps between subroutines or program segments,
typically 1/4 the length of the code written. Where instructions
follow one another continuously for more than ten lines, insert
several Nap (No OPeration) instructions (OP CODE 01) which do
absolutely nothing except to occupy memory locations. These are
easily removed when extra addresses are required for later
changes. The only cost is the extra memory used and slower
execution.
When re-assembly is undesirable or impossible a PATCH is
recommended. This involves a jump to some external address,
where the extra instructi"Ons are placed, followed by a "jump back"
to the address just below the first "jump out". The cost is
usually 6 bytes (2 jumps) plus the inserted code. In the program
below a CLR COUNT instruction is needed just after STX ~mMADD.
Modify the program below to patch in the extra instruction
assuming that COUNT is address OOFF and that addresses 0680 - o68F
are available. Write both .the assembly language instructions and
the machine code for the patch.
1361313
0603
13606
06139
CE i34E
FF 136213
FE 0620
08
0620
0600
0603
0606
0609
0680
0680
13683
13686
CE i34E
7E 0680
FE 062€1
08
t'lEt1ADD
r
.
FF 136213 PATCH
7F e0FF
7E 0606
LOX
STX
LOX
INX
#$i34E
MEMAOO
MEMAOO
EG~U
$0620
LDX
, ~Tt1P
LDX
IN>::
ORG
STX
CLR
.JMP
l$i~4E
PATCH ,
MEt1ADO
$06813
t'lEt1ADD
COUNT
$0606
/
-
6-9
The problem below presents a condition where memory
locations for a patch are very limited. Assume that 5 bytes
are available (0470 - 0474). The instruction CLR B is now needed
between the first 2 instructions. In your solution show assembly
language and machine code for changes made. If you are stuck,
look at the hint in the first line of the answer.
£14£10 8D 1.F0(1
134133: 84 5F
.JSF.~
TEF.~t1 IN
ANCI A
0405 :=::1 4C
Ct1P A
*$5F
*··-L
---~/
Hint. Use branch rather than jump instructions.
Calculations
(1)
0470 - 0405
FFFF
-0405
FBFA
+__
1
BD
l.F~::10
04~(:t
~;~~~~
68
~14~15
::::t
BACK
5F
PATCH
£14-;::'121
~14?t1
FBFB
+0470
006B
(2)
€14~]f1
0471 84
121473:
JSF.:
BF.:A
Ct'lF' A
TEF.:t'l I N
PATCH
#'·L
OF.~G
$047~3
CLR 8
AND A
#$5F
E:F.~A
BACK
0405 - 0475
FFFF
-~
FB8A
1
+ __
FBBB
+0405
FF90
.
90
Since only 5 locations are available
branch instructions (2 bytes per branch)
would just fit. Such situations are quite
common when modifying old programs,
particularly if source listings are
unavailable.
6-10
.......
The previous example shows how the program counter
contents, when added to the branch offset, produces the address
of the next instruction to be executed, e.g.,
0405 = PC
+ 6B = branch offset
0470 = new address (where PATCH begins)
Reverse branching calculation is slightly different. Since 90
is a negative value, its 2 byte equivalent is then FF90
0475 = PC
+FF90 = branch offset (2 byte format)
0405 = new address (BACK)
Given the following machine code, convert it to assembly
language producing absolute rather than symbolic addresses.
Appendix D gives the instruction for each operation code.
:iF49
1F48
1F4D
1F4F
81
~:;'4
27 (14
8D (19
2(1
EC
_ _ _----.J/
lF4D
lF49 :::1 (14
1F48 27 1-:;'4
lF4D 8D (19
lF4F 2(1 EC
+~
Cr'1P A
#$04
8EG'~
$:1F5:1 ~~~$1F58
$1F3D
8SF.~
E:~~A
lF4F
-...,,"f"---lF51 _lF58
")
+~
lF51
Only negative values must be
~+FFEC note Ee becomes FFEC
IF)D in 2 byte format.
preceded by FF in 2 byte
format.
If more practice is needed, there are lots of listings
in the last half of this workbook.
--7-1
- ACIA ASYNCHRONOUS COMMUNICATIONS INTERFACE ADAPTER
A computer, to perform any useful function, must be able
to communicate with the "outside world", that is to and from
external devices such as keyboards, printers, teletypes, remote
computers, etc. Two forms of information transfer are available,
serial and parallel. Parallel format, in which 8 bits are
transferred at one time, requires 8 external data lines, plus
control lines. For transmission of data beyond several hundred
feet the large number of wires in a cable makes this parallel
transmission impractical. In such cases serial transmission is
preferable. For data transmission over a telephone line serial
format is essential, since only one channel is available.
In serial format data is transmitted at a predetermined
data rate, one bit after another. Each character or byte
(usually 8 bits) is self contained, preceded by a start bit
(always 0) and terminated by one or two stop bits (always 1).
In between successive characters the signal remains in the 1
state, if there is a pause. A typical character is seen below.
rime ---...
r,(l is also known as MARK, 0 as SPACE)
'ol~~-LiJ
STAll
a,r
,-Si\
"',
"'1..
.. ~
"'t
tl5
q.~
~7
St'oP
P.uT
~,\-(iP
'~,1
The ACIA acts as the interface between the serial device
and the computer, communicating with the serial device in serial
format and with the computer in parallel format.
Associated with the ACIA are 2 consecutive memory
addresses, the lower one (even) controlling and indicating the
status of the ACIA and the higher one (odd address) containing
data transmitted or received by the ACIA. The actual addresses
are usually in the top half of memory and are assigned by the
hardware designer.
Contd.
7-1
Contd.
Let's look at the Data Buffer first, assuming an address
of 7FF5 for the ACIA Data Buffer "SERBUF". This single buffer
services 2 internal buffers, receiving data from the "read only"
RECEIVE BUFFER. and transmitting data to the "write only"
TRANSMIT BUFFER. The same address is used for both buffers
(see below). Hence the instruction LDA A SERBUF automatically
gets its data from the RECEIVE BUFFER. while STA A SERBUF
automatically passes its data to the TRANSMIT BUFFER.
RECe\ve ~\JFFe~
( i).EA 0 ONL.'()
TRA NSM IT B"Fi=E.R
ACtA
D"7A
l
BUFF i:R..
~4cl~e~~ "IFF S \>~\c)",,)
~V'Clns ~;11 eeA set ..o.l dc:..tCc
"itAIVS~11
'""N'e
Write an instruction which sends data, now in ACC A to
the ACIA where it will be automatically put into serial form
and transmitted to some external device.
----'/
STA A $7FF5
All that for one instruction!
Symbolic addresses are preferable when working with the ACIA.
lrhe statement
SERBUF EQU $7FF5
directs the assembler to substitute 7FF5 for the symbolic
address SERBUF. To improve readability of programs it is
usual practice to place all "EQU" assembler directives at
the beginning of a program.
Address 7FF4 is known as the Control and Status Register,
described in detail later in this chapter. Arbitrarily it is
called SERCSR (SERial Control and Status Register).
7-2
Write an instruction to read serial data from the ACIA
into Ace B. Assume previous symbolic definition of the Data
Buffer.
LDA B SERBUF
----'/
Note that if
STA A SERBUF
LDA A SERBUF
is executed, the data in ACC A will normally change since data
is stored in the TRANSMIT buffer but loaded from the RECEIVE
buffer, even though both carry the same symbolic address SERBUF.
----7-)
If serial data is being received by the ACIA, some
method is necessary to inform the computer when parallel data
is ready. If data is read too soon it would be erroneous; if
too late it could be lost, since the ACIA has only one 8 bit
RECEIVE buffer where parallel data is stored after being
formed from the incoming serial bit stream. At high serial
data rates, e.g. 9600 bits/sec, the "lifetime" of data in the
RECEIVE buffer is approximately 1 millisecond, after which it
is overwritten by the next byte.
When an incoming data byte is ready, bit #0 of the
Status Register (7FF4) automatically changes from 0 to 1. The
AND or BIT instructions permit us to examine this bit #0, or
"READY" bit, of the ACIA Receiver. It is normal practice to
to test this bit in a looping manner, exit from the loop
taking place when bit #0 = 1, that is when data is ready.
Write the instructions to examine bit #0 of the Status
Register. (No branching yet.)
LDA A
SE~:CSR
AND A
#$121:1
----.-,,/
7-4
.....-.
Now add instructions to cause continuous testing of
bit #0 until data is ready, whereupon the data is to be
transferred to ACC A.
---~/
INLOOP LDA A SEF.:CSF.:
AND A #$0:1
BEG!
INLOOP
L.DA A SE~:E:UF
lJ)51) .,
-DATA READY.
Reading of the data from the RECEIVE buffer, SERBUF, clears the
READY bit, sometimes referred to as a READY FLAG or DONE FLAG.
A timing diagram of these events is shown here.
RECEIVER
READY
BIT
few
microseconds
1
bit#
o
--fJ
~
~
if repeated in a looping
type program
n
,...,-__--.A.------..
{
1/ -_........
~utomatically Data'\
~
---
Goes to 1'\
\Data is read
when dat~} cleared when
READY
into ACC A
is READY
data is read,
(LDA A SERBUF)
in Data
e . g. ,
Buffer.
LDA A SERBUF.
Although the rate of transmitting and receiving data bits is fixed
ther~ may be long time gaps between successive characters.
Hence
the term "asynchronous" in the ACIA, meaning no specified number
of characters per second.
7-5
.
Data to be transmitted in serial form by the ACIA should
not be transferred to the ACIA's TRANSMIT data buffer until this
buffer is empty and therefore ready to accept a new byte. Bit #1
of the Status Register is the transmitter's READY bit. When in
the 1 state, it denotes this READY condition.
Write a short program to put the byte now in ACC A into
the TRANSMIT buffer when the transmi·~ter is READY. Warning.
Don't destroy data now in ACC A while testing for the READY
condition.
OLOOP
LDA B
ANCI B
SEQ
STA A
-----'/
SEF::CSR
I
#$02
T~< F::EAD'r ?
OLOOF'
SER8UF
OUT
TO TX
E~~Ca
The use of ACC ~ preserves the data in ACC A
printing time, based on
predetermined data rate
Transmi tter READY
bit normally 1
while waiting for
data.
STA A SERBUF
j
';
of
~t:'CIA
_
~
I
t
,
0
READY bit goes to 1
when transmission of
character is complete.
Note that the transmitter, while dormant, is normally READY,
waiting for data from the computer. In contrast, the receiver
in the dormant state is normally not READY, since it is waiting
for new serial data from the external device.
7-6
Now write a s~ries of instructions to echo serial data
from the ACIA RECEIVE line out on the ACIA's TRANSMIT line.
--------/
$132013
:+:
:+:
:+:
7FF4
7FF5
SEF.:CSF.: EG!U
SEF.:BUF EfJ.U
$7FF4
$7FF5
:+:
86 7FF4 INLOOP LCJA A
13203 84 €Ii.
AND A
020f~
€12€15 27 F9
1212137 86 7FF5
020A F6 7FF4 OLOOP
020() C4 02
02€1F 27 F9
12121:1 87 7FF5
BEQ
LDA
LDA
AND
BEG!
STA
END
SEF.:CSF~
#$131.
INLOOP
R:ECE I VEF.: F.:EAD'-r'?
A
SEF~E:UF
GET CHAR IN A
B
8
SEF.:CSF.:
#$f:l2
OLOOP
SEF.:BUF
A
T:xi F.:EADY?
....
OUT TO T·"J.
This is often known as an ECHO routine, permitting data which
is entered on the keyboard to be viewed by the user.
To
AND A #$01
RXREDY EQU
AND B #$02
make this program more readable, the instruction
could be replaced by AND A #RXREDY, if
$01 is included in the above definitions. Similarly
could be replaced by AND B #TXREDY.
7-7
--
Sometimes data, received by the ACIA must be stored,
byte by byte, in memory. Flow chart and write a program to do
this, the first byte going into address 1000. For now assume
no end to this looping type program.
----'/
I N'T'A~'%E
ADDRess
pOIN1'eR
L[):)'~
5TX
t10F.:TES LDA A
AND A
8EQ
LI)A A
NO
OUTER
~OOP
SToRe IT
IN
LD~·!.
IN::-::
5TX
STA A
BRA
RME:
#$1.000-1.
MEMADD
SET UP ADDF.:ESS POINTEF.:
SERCSF~
#$~31.
F~:X:
MOF.:TE5
5ERE:UF
t'1Et1ADD
GET
t'1Et1A [:1 D
>~
t10F.:TES
DATA REAr..y?
CHAF~
AND NEI.oJ ADDF~ESS
AND STORE CHAF.:
BACt< FOR r·10F.:E
2
END
HE t.-r AODRESS
Here we see an inner loop testing the READY bit and an outer loop
storing data. 'fhis is known as a "nested" loop format.
.ll
Modify your program such that receipt of 5A will cause
storage of this byte, then exit from the loop. Show changes only.
---_./
After
Before
BRA
MORTES
cr1P A
BNE
1$5A
t"10RTES
IS IT Z?
If your modification looked like thisl
CMP A
BEQ
BRA
1$5A
NEXT
MORTES
IS IT Z?
note that a conditional branch (BEQ NEXT) followed by an
unconditional branch (BRA) can usually be replaced by a
single branch instruction (BNE MORTES) of the opposite sense
(BNE vs BEQ).
Although the ASCII code for Z is 5A some terminals
produce "mark parity", that is the leading bit is always set,
resulting in DA rather than 5A. Other terminals may produce
"space parity" (leading bit is zero) or odd or even parity,
discussed a few pages later.
-7-9
The computer when connected via the ACIA to some output
device such as a printer or CRT terminal could send a specific
message to the computer operator.
Flow chart and write a program to output the message
BAD HEX CHAR to such an output device via the ACIA. Terminate
the message with a null.
7FF4
7FF5
IN IT'''L''Z.&
ADI>RESS
----"/
SERCSR EQU
SERBUF EI~U
*
POINT&R
P~:Tt'10R
LOX
ST:>::
LD>::
$7FF4
$7FF5
#t1ESBAD-1
MEMPNT
INIT MESS POINT
MEMF'NT
IN>~
GET HE",.
BYT~ F5\OM
l1eMORY
:0
STX
L(:IA A
BEQ
OUTEST LDA E:
AND B
BEQ
STR A
BRA
t1Et1PNT Rt1B
MESBAD FCC
FeE:
ALLDUN
t1Et1PNT
x
ALL[:IUN
GET POINT ADDRESS
GET CHAR FROM MEM
G~UIT IF NULL
SERCS~:
#$02
OUTEST
SERBUF
PRTt10F.:
OUTPUT DEVICE READY?
NOT 'TIET
YES OUTPUT IT
. . . BAD HE:>:: CHAR.. .
&3
7-10
To operate the ACIA correctly the data rate at the
receiving end must be within 1 or ~; (5% would produce errors)
of the transmitted data rate. Hence the frequency of external
oscillator which determines the basic data rate for each ACIA
is usually crystal-controlled. as in modern electronic watches.
Selection of data rates and control operations are
possible via the Control Register. a "WRITE ONLY"
register which shares the same address as the
"READ ONLY" Status Register. The diagram at the
left depicts these registers. assuming 7FF4 as the
assigned address. Hence LDA A $7FF4 reads from
the Status Register, while STA A $7FF4 stores in
7FF't
\" ~iS
exaDlplt
the Control Register. The common symbolic address
in previous examples has been SERCSR.
The data rate of the ACIA is determined by dividing
the external oscillator's frequency by 64, 16 or 1, under
control of bits #0 and 1 of the Control Register (see App. E1).
For example, if bit #1 is 0 and bit #0 is 1 (i16 mode) an
oscillator frequency of 9600 bps would produce a data rate
of 9600/16 = 600 bps.
Assuming that all other control bits are correctly set
ensure that the ACIA will operate at a data rate of JOO bps
when the oscillator frequency is 19200 Hz (cycles/sec).
Since the Control Register cannot be read to be modified. assume
that it is updated from ACIACR. a symbolic address in memory.
_ _ _----J/
01.1313 B6 738E
131.03: 84 FE
0:1'.::15 SA 02
131.1217 87 738E
01.0A 87 7FF4
LDA
AND
ORA
STA
STA
A
GET ORIGINAL STATUS
CLEAR BIT 0
SET BIT :1
#~~000000:10
UPDATE OF~IGINAL
ACIACR
A
SERCSF~
A
A
A
ACIAC~~
#~:11.:1:1:11.:10
19200/300 = 64
Therefore bit #1 = 1 ) See
bit #0 = 0 )- Appendix
in the Control Register} E.
If both bits are 1 RESET takes place. This is necessary when
power is first turned on, before changing speed, parity, etc.
7-11
Bits 2, 3 and 4 (see Appendix E) determine the number
of data bits and stop bits of the data format. It also
determines the parity options for the data. Parity control
determines whether each transmitted data byte carries an even,
odd or unspecified number of ones, bit #7 of the data being
modified to produce odd or even parity.
The number of data bits and stop bits, plus parity
options must be agreed upon for both ends of the data link.
Although programmable, they are not usually changed once a
data link is set up.
Without disturbing unspecified Cpntrol Register bits,
set the ACIA for 1200 bps operation using a 19200 bps oscillator.
The data formed is to be 7 data bits plus l' odd parity bi t plus
1 stop bit. Again use ACIACR as the original for the Control
Register.
121:1.013 86 738E
0:1.03 84 ED
&Z1:1.05 8A e[)
01.07 B7 738E
0:1.0A 87 7FF4
LOA A
AND A
OF.:A A
STA A
STA A
---_/
ACIACR
GET ORIGINAL STATUS
CLEAR BITS :1. AND 4
#%01210e1101 SET BITS 0~2 AND 3
ACIACR
UPDATE ORIGINAL
SERCSR
CHANGE CONTROL REGISTER
#~~:1.1e1:1.01
I
7 6 5 4 3 2 1 0 1 - bi t /I
X X X 0 110 1[
'--v-' "v-'"
7 data
odd
1 stop
-:16
For your first few programs, which are not part of a larger
program, simply place the desired value in the Control
Register e.g.
LDA A #%00001101
STA A SERCSR
7-12
Serial data processed by the ACIA essentially follows
the RS-232-C Specifications of the Electronic Industries
Association (EIA). Voltage levels, source and load resistances,
connector type and pin assignments for data and control signals
are contained within this specification. Some of these control
signals are produced by the ACIA for the serial device. Others
are produced by the serial device for the ACIA.
One control signal is RTS (Request To Send)t which is
produced by the ACIA when requesting permission of the serial
device, a printer perhaps, to send data to it. This signal
is active when low hence is called RTS, the bar over RTS
indicating inversion, that is when RTS = 1, RTS = 0. RTS
is determined by Control Register bits #6 and 5.
The usual response by a serial device (printer) upon
receiving RTS = is to activate a control line to the ACIA
called CTS (Clear To Send), also active when low.
°
This exchange of control signals, usually preceding data
transmission, is often called "hand shaking" and can be used to
permit data transfer only when a device is turned on and
operational. The RTS line can alternately be used as a control
line without feedback (CTS is ignored), perhaps controlling a
function in an external device.
Control Register bits #7! 6 and 5 remain to be discussed.
Bit #7 controls receiver "Interrupt" operations (Chapter 11) and
is assumed to be 0 for now. Similarly bit #5 is assumed to be 0
since it controls transmitter "Interrupt" and "Break" operations.
With bit #5 = 0, bit #6 controls the RTS line; RTS = when
bit #6 = 0, and 1 when bit #6 = 1. See Appendix E for details.
°
The following program is to.
initialize the ACIA for operation with.
(a)
- 7 data bits, even parity and 1 stop bit.
- data rate of 600 bps when the oscillator
frequency is 38400 bps.
(b)
set RTS = o.
send the ASCII code ACK (acknowledge) after the
(c)
external device (printer) clears eTS.
Contd.
7-12
Contd.
SEF.:CSF.~
7FF4
7FF5
73::=:E
EG!U
SEF.:E:UF EG!U
ACIACF.: EG!U
$~::'FF4
$7FF5
$73:=:E
:+:
J.)1J3t1 E:6
(1:1J.~f3: :=:4
01t15 :=:A
10311217 E'"'?
'I
J.~11(1A Eo"'
'I ?
J.~1:1J.~1D F6
t1:1:1J.3 C4
103:1:12 C:1
c..t.:.
1211:14 .-,.(11.1.6 :=:6
1211.:1:=: E:7
-;:'3::=:E
LDA A
:::A
AND A
(1A
OF.:A A
73::=:E
STA A
STA A
7FF4
7FF4 NOT.,.IET LDA E:
0A
AND E:
J.~12
Ct'1F' E:
F7
BNE
(16
LDA A
7FF5
STA A
ACIACF.:
#;'~1 (1J.~10:10 1 0
#;·~(10t1J.~11 (1:1 J.~1
UPDATE OF.: I Ci I NAL
ACIACF.:
SEF.:CSF.:
SEr.:CSF.:
#~~ t1J.~1 t1J.~11 (11(1
#i~ 0J.~1(1J.:10t1:1
t1
NOTITIET
#$(16
SEF.:E:UF
Explain the function of the 4 instructions starting
with LDA B SERCSR
--------.",/
7 6 5 4 J 2 1 0
10 -..,0 0 0
1 0 1 0
~
_
RTS = 0
Ix
I
r
I Control
Register
I
7 data.
even
.;.64
parity.
1 stop bit.
XXX
CTS=l
#
"~
0 X 1 01
Status
Register
4
"fTransmitter
lREADY
"=C=T=S-=0-J-- - --
or
~bi t
j
LDA B SERCSR and
AND B #~~000010 10
expose"
Status Register bits #3 & 1.
CdlP B i;~ooooOO 10 tests for
o in bit #3 (CfS=O) and
1 in bit #1 (Tx READY).
BNE NOTYET branches back if
either condition is not met.
II
7-1J
Returning to the Status Register, other bits not yet
discussed are,
- Bit #2 - Data Carrier Detect or DCD an input to the ACIA from
a "modem" used to transmit serial data over a telephone
line. DCD = 1 if loss of tone occurs on the telephone line.
- Bit #4 - Framing Error goes to 1 when a stop bit is missing,
usually due to an erroneous start bit.
- Bit #5 - Receiver Overrun - goes to 1 when data is lost due to
too slow reading of the Data Buffer. It is cleared by reading
the Data Buffer.
- Bit #6 - Parity error,goes to 1 when the parity of the
received data differs from that expected, based on the Control
Register contents.
- Bit #7 - Interrupt Request state (Chapter 11).
Write a few instructions to ensure that the Framing Error,
Receiver Overrun and Parity Error bits are all normal (zero). If
one or more is wrong, branch to ERROR.
7FF4
7FF5
EQU
SERBUF EQU
86 7FF4
*
SE~:CSF.:
$7FF4
$7FF5
---_/
:=:4 70
LDA A
ANI) A
#t~~111100~30
26 59
BNE
EF.:~:OF.:
SE~:CSF~
CHEC.<
FOF~
3 T',..PES OF ERROR
7 6 5 4 :3 2 1 0 ... bi t #
1X
0 0 0 X X X
t I I
P 0 F
xl
--8-1
- PIA PERIPHERAL INTERFACE ADAPTER
In the previous chapter we worked with the ACIA which
transmits and receives serial data in a fixed format at a
predetermined rate. This chapter involves the Peripheral
Interface Adapter (PIA), a device which transmits and receives
data in parallel form at an unspecified data rate.
The PIA is comprised of 2 almost identical sections,
A and B, each capable of transmitting or receiving 8 bits of
data. A block diagram of the "An half of the PIA is shown
below. For each section there is a Control Register (CR) and
a Data Buffer, both having similar functions to those in the
ACIA, plus a Data Direction Register (DDR) which determines
which bits of the Data Buffer are inputs and which are outputs.
Both the Data Buffer and the Data Direction Register share the
same official memory address, the selection between the two
depending on the state of bit #2 of the Control Register.
Assume address 7FFO for the DDR and Data Buffer for the
A half of the PIA. Automatically its Control Register address
would be 7FF1. For the "B" half of the PIA the addresses would
be 7FF2 and 7FFJ (Data Buffer and DDR = 7FF2, CR = 7FFJ).
iFFO
I
~ CONT~OL
7Ffl ~_ _~
)
R1:G\S'TER
.
-4.-----------B~it\#2 of Oontrol Register
determines if DDR or Data
Buffer is served via 7FFO.
(Bit #2 = 0 --serve DDR)
(Bit #2 = 1 --serve Data Buffer)
Let's assign symbolic addresses to these two memory
addresses, PIABFA being the nA" half Data Buffer (and DDR too)
at address 7FFO. Similarly PIACRA would be the "A" half of
Control Register at 7FF1. For the "B n half the corresponding
symbolic addresses would be PIABFB (Data Buffer and DDR) at 7FF2,
and PIACRB (Control Register) at 7FFJ.
Contd •.•
8-1
Contd.
As noted in the previous diagram, if bit #2 of
PIACRA = 0, then data destined for PIABFA goes to the "A"
Data Direction Register. If this bit #2 = 1, the data will go
to the "A" Data Buffer.
The Data Direction Register stores 8 bits, each bit
independently controlling the data direction for the
corresponding bit of the Data Buffer; 1 = output, 0 = input.
Write the instructions to ensure that all PIA data
lines for the itA" half of the PIA will be input lines. Note
that the first task is to address the Data Direction Register,
via bit #2 of the Control Register.
7FF0
7FF:1
0:1€n3 B6
01€(s 84
13:1135 B7
01138 7F
7FF:1.
FB
7FF1.
7FF0
-------/
*
F'IABFA
EI)U
PIACF~A
EG~U
*
$7FFe
$7FF1
LDA A PIACRA
AND A
#~1111101:1.
STA A PIACRA
CLF~
PIABFA
CLEAR BIT 2 TO ACCESS DDR
SET A HALF FOR INPUT
-
8-2
The routine in the previous frame would normally be
found within a RESET program which is automatically executed
when the microprocessor power is first applied or when the
RESET button is depressed. More details on such initializing
operations are contained in the Interrupt Chapter.
Write the instructions for a RESET routine to set up
the "A" half of the PIA for input and the "B" half for output.
This routine should leave the PIA ready to load and store data.
/
7FF0
7FF1
7FF2
7FF3
*PIA8FA
EG'~U
PIACRA EQU
PIABFB EI~U
PIACRE: EG'~U
$7FF0
$7FF1
$7FF2
$7FF3
:+:
01(10
0103
01.05
01.0S
01.£18
e1£1D
0110
01.13
0115
01.:1.8
01.:1.A
01.1.0
01213
86
84
87
7F
SA
87
F6
84
B7
86
7FF1 AHALF
FE:
7FF1
7FF0
04
7FF1
7FF3 BHALF
FE:
7FF3
FF
7FF2
7FF3
87
86
8A 134
01.22 B7 7FF3
LDA A
PIACF~A
AND A
STA A
#~~1.1111011
PIACRA
PIABFA
CLEAR BIT
--,
.:!.
TO ACCESS DDR
CLR
SET A HALF FOR INPUT
OF::A A #~'-;:00£10£110£1 BIT 2 = 1 FOR DATA
STA A PIACRA
LDA A PIACRE:
AND A # %111.11 ~31. 1 CLEAR BIT 2 TO ACCESS DDR
STA A PIACRB
LDA A # ~.~ 1.:1.1.:1.1.1.1.:1.
STA A PIABFB
SET 8 DCIF~ FOR OUTPUT
LDA A PIACF~E:
GET CR AGAIN
ORA A #;-;:(113000100 BIT 2 = 1 FOR DATA
STA A PIACRB
Assuming that the B half of the PIA is already
initialized for output (see previous frame), set bit #5 and
clear bit #J of Data Buffer B, without disturbing other Data
Buffer bits. From now on assume PIA Register definition
(PIABFA EQU $7FFO etc.), unless otherwise requested.
----_/
LDA A PIABFB
ORA A #:Y.001.00000
AND A
#~1111e111
STA A
PIABFB
SET BIT 5
CLEAR BIT 3
The PIA could be controlling a machine tool, with the changes
in bits #J and #5 representing control signals for the next
machine process.
-
8-4
What is the state of bit #2 of PIACRB during the
previous frame?
---~/
Bit #2 of PIACRB = 1 permitting communication with the Data
Buffer rather than the Data Direction Register.
..§.;.l
The PIA could be used with a 6800 microcomputer in an
automobile sensor and alarm system. Assume INDATA as Data
Buffer A, at address 7FFO. Also assume the following bit
assignments for INDATA.
Contd •. ·
8-5
Contd.
The input Buffer, INDATA, has the following bit
assignments.
Bit #
o
Function
Status if 0
Status if 1
Seat Belt Monitor
disconnected
fastened
Door Monitor
closed
opened
1
Oil Pressure Monitor
low
normal
2
Ignition Monitor
ignition off
ignition on
J
4
Gear Shift Monitor
park/neutral
all others
Engine Monitor
not running
running
5
Day/Night Monitor
night
day
6
Headlight Monitor
lights off
lights on
7
The output Buffer, OUTDAT, has the following bit
assignments.
Bit #
Function
Status if 0
Status if 1
o
Buzzer
off
on
1
Bell
on
off
2
Panel Alarm Light
on
off
3
Starter Control
starting
starting
disabled
enabled
Flow chart and write the in~tructions to ring the bell
if the ignition is off and the headlights are on. (I wish
that I had that on my car.) Assume previous initialization of
the PIA for input on Buffer A and output on Buffer B.
_ _ _--J/
*
€1:100 B6 7FF0 CARCHK
LDA A
~1:1.03 85 0'-'
BIT
c'
A
0:105 .-,.oe:.t.:. 49
BNE
€1:1.07 85 8~:::1
BIT A
~1:109 27 45
SEQ
0:1.0B 86 7FF2
LDA A
0:1.€1E E:A €12
OF.:A A
1211.:1.0 87 7FF2
STA A
ExaT
R'WG BELL
01.50
*
*
NOBELL
INDATA
#%01300:11210121
NOBELL
IGN?
#:"'~:1.0€100000
LIGHT?
NOBELL
OUTDAT
#::-~0~3000e1.€1
OUTDAT
BELL?
RING BELL
-
8-6
This time permit the car to be started if and only ife
(a) seat belt is fastened and
(b) gear shift is in Park or Neutral and
(c) door is closed.
otherwise turn on the buzzer.
First flow chart your solution.
_ _ _-.1/
O"fHe~S ( l '
OPE"
(I)
Your order of checking
the functions may correctly
be different. The order
shown here leads to
slightly easier testing
as seen in answer in the
next frame.
-8-7
Now write the program, preferably using the flow chart
shown in the previous frame.
0:1.22
01.25
01.27
01.29
0:1.28
0:1.20
0:1.313
0132
0135
0:1.37
013A
0:1.3(:
0:1.3F
86 7FF0
85 01.
27
85
27
86
8A
87
20
B6
8A
87
20
LDA
BIT
8EQ
1214
:1.2
BIT
BEQ
etA
LDA
7FF2 BUZZ
(11.
ORA
STA
7FF2
08
BRA
7FF2 OKTOGO LDA
138
ORA
STA
7FF2
E:1.
DONE
TESCA~:
A
A
---------/
IN[)ATA
#%000000€11.
BELT ON?
BUZZ
A
#%12100:1.00:1.et
OKTOGO
OUTDAT
A
A #~~000000(11
A OUTDAT
[)ONE
A OUTDAT
A
A
#"~0(1e01.000
GEAR SHIFT AND DOOR?
BUZZ
OK TO START
OUT[)AT
7 6 .5 4
I~
IX
J
2 1 0 bit
X X 0 X X
#
o ijBelt on
L-Door
closed
Park or Neutral
1
OVT
\J
3
Istart
I
;J.
Light
0
Bell I Buzz
By grouping the Gear Shift and Door checks together the single
instruction BIT A #$00010010 will cause a branch via BEQ OKTOGO
if and only if both bits are o.
I
8-8
Transfer of data between the PIA and an external device
takes place at an unspecified rate; hence control lines are
needed between the PIA and the external device to indicate to
the PIA when the data is ready and to the external device when
the data has been read. This provides a "hand shaking" linkage
similar to that possible via RTS and CTS in the ACIA.
For the A half of the PIA two control lines, CAl (input
to the PIA) and CA2 (input or output) are available. CAl could
inform the PIA, acting as a
CAt
--...
data receiver, that data is
now available. When this
?lA
D" ,A
E"Xi'cftt1AL
data is read by the PIA, CA2
BVrFER
bcV'':E
A
could inform the external
\...
device that data has been read;
CA1..
therefore another byte could be
placed on the data lines. GBl and CB2 could perform similar
functions for the B half. Both CAl and CA2 are controlled by
specific bits of Control Register A as shown below.
(
~
#
CAl
CONTROL
CAl READY Bit
goes to 1 when
CAl goes ACTIVE
-------~----
~
If 1 CA1 goes ACTIVE in going HIGH.
If 0 CA1 goes ACTIVE in going LOW.
The J bits associated with CA1 are shown above. We are
not using interrupt at this time; hence bit #0 = o. Bit #1
determines whether CAl sets the READY bit (#7) when CAl goes
LOW (if bit #1 = Q) or HIGH (if bit #1 = 1). The CAl READY
bit (also called IRQAl in Motorola literature) indicates, when
going to the 1 state, that CAl has gone ACTIVE.
If bi t #1
=0
in the
Control
Register
~H'G"
CAi
If bi t #1
=
LOw
'Batt.,.
eM
~~A01
- -..... 0
""i',t\G~
1
in the
Control
•
Reg1ster
,~\~"
cA1
I
__
,I.D~
~
W
_
_
6_1t_
_l_ _....I1. "
_ <:1\\ il-=AO'1'
Contd •••
8-8
Contd.
The PIA READY bi t (similar to the ACIA ',' READY bit)
will be cleared automatically when data is read from the Data
Buffer, e.g. LDA A PIABFA. Bit #7 of the Control Register
is a READ ONLY bit, and therefore cannot be set or cleared
by a STA A PIACRA instruction.
It
II
It
Initialize Control Register A so that CAl's READY bit
is set when CAl goes HIGH. Do not disturb the other Control
Register bits.
xXXXXX1
t
X
~
Set
01.£10 B6 7FF1
LDA A PIACF.:A
0::1..1213: BH (1:2
~~~t~Z15 B? '?FFl
OJ;.:A A
#~.~ (n30£1€,n:;:110
STA A
PI ACF.:A
Assume 0
(no interrupt)
SET E:IT 2
Note that it is the transition (LOW to HIGH or HIGH to LOW)
which causes the input Control Lines to become ACTIVE, rather
than the final level of these lines
8-9
--
When bit #5 of Control Register A = 0, CA2 also acts
as an input line similar to CAl. Bit assignments for PIACRA
are as follows.
654
J
t
lo
for "no interrupt"
(0 = CA2 ACTIVE in going LOW
(1 = CA2 ACTIVE in gOillf..~ HIGH
o for input operation of CA2
CA2 READY bit (read only) 1 = REAux
Bit #5
=0
for input.
and 0 for CAl.
Bits #4 and
J behave the same as bits
#1
Assume that both CAl and CA2 are to be in~ut Gontrol
lines, CAl being ACl'IVE in going LOW and CA2 being AC'I'IVE in
going HIGH. Write the instructions to produce this. Also
set up the A Data Buffer for input operation.
---~/
°
xx°
1 0
?FF~3
PIABFA
EOU
?FF:;:~
~11.~:::1~:3
t1:1.ff::' ::::4
D~:::1
B7 7FF:l
(11.(18 '?F 7FF~3
0:1t1E: ::::A :1.4
~:3:tf15
~~:1.~~[)
E:~:O
·?FF1.
AND A
# :'.~:1 :1. ~:1:1 ~] ~:::10 ~:::1
eLf;,:
PIACRA
F'IABFA
OPA A
#%00010100
:::;TA A
PIACRA
STA A
tt
0 ctf-Control Reg. A
\..CAl no Interrupt
CAl ACTIVE LOW
o to set direction
{ then 1
CA2 no Interrupt
CA2 ACTIVE HIGH
CA2 Input
$'?FF ~.:~
$?F F:.I..
$7'FF;;::
$?FF3:
P I ACF.~A EG!U
F'IAE:FE: EG!U
P I ACF.~E: EOU
7FF3:
LDA A F'IACF.:A
E:6 7FF:l
?FFl
x
SET FOR DDR
INPUTS FOR A HALF
DATA
8UF NQW
8-10
There are J possible modes for CA2, acting as an output
(bit #5 = 1). The first is seen when bit #4 = 1. CA2 will now
act as an output line whose state will be determined by bit #3,
(0 produces LOW, 1 produces HIGH).
7
6
4
J 2 1 0
1
Assume that to communicate with some external device CA2
is to go to the HIGH state for 1 millisecond, then go LOW.
Also assume that the instruction JSR MILSEC (subroutines will be
covered in the next chapter) will cause a delay of 1.0 milliseconds. Write the necessary instructions assuming that CA2 is
presen"tly LOW.
7FF~3
F'IABFA EGHJ
'?FF:1
PIACF.:A EG!U
7FF2
PIABFB Et:;"~'-'
7FF3
PIACF.:8 EG!U
~31~~10 86 7FF:1
LOA A
(1:103: :3A 3:='
OF.:A A
0:1~35 87 7FF:1
STA A
€11J3:::: 8D ~3113
.JSF.:
L[)A A
131.08 E"·b 7FF1
~310E 84 F7
AND A
~:::11.1.~3 87 7FF:1
STA A
--------'/
$7FF0
$7FF:1
$7FF2
$7FF3
PIACRA
SET 8ITS 5 .. 4 AND
CA2=1
ONE t'1ILLISEC DELA'r'
#~'~~Z1€1:111 €n3~3
PIACF.:A
t'1ILSEC
PIACF.:A
t1ILSEC t1AY USE ACe A
#~";1:11:101.1.:t
PIACF.:A
7
..>.
NO~o.I
CLEAF.~
BIT '3
CA2=~3
Such an output control signal on CA2 could be produced after
data reception on the A half of the PIA to order the data
source to change mode of operation. For lack of a better name
let's call this the PROGRAMMED mode, since the state of CA2 is
determined by program control.
8-11
CA2 may be used as an output control line in a "hand
shaking" mode when bit #5 = 1 and bits 4 and J = o. In this
mode the A half acts as a data receiver. CA2 will go HIGH
automatically when CAl goes ACTIVE (HIGH in this example) and
will go LOW automatically when Data Buffer A is read.
n:::'
CAt
_C_A_l__
L-Data Ready
p
k'::
STORE IT
LDA
AND
STA
CLF.:
OF.:A
STA
INl·JAIT LDA
E:F'L
LOA
LOX
#$0800-1.
t1Et'lPNT
INIT POINTER
R F'IRCF~A
A #:Y.1.1.1.0001.0 BITS 4.. 3.. 2.. 0 = 0
A PIACRA
F'IABFA
INPUT t10DE NOIo~
A #~·~e01.001.1.0 SET ElITS 5.. 2 AND 1.
A PIACRA
DATA ElUF NOlo!
A F'IACRA
INl·~AIT
WAIT FOR F.:EAD1T1 FLAG
A PIABFA
GET DATA
t'lEt'1F'NT
IN~'~
ST}::
t1Et'lPNT
STR A >~
Ct'lF' A #$FF
BNE
INWAIT
Hp~
Bp~A
HR
t1Er1F'NT Rt18
2
GET STOF.:E AD[)F.:ESS
AND STOF~E DATA
NOT LAST DATA
ALL DONE SPIN FOREVER
8-12
In the same hand shaking mode (bit #5 = 1, bits
#4 and 3 = .0), the B half of the PIA acts as a transmitter.
Here CB2 will go HIGH when CBl goes ACTIVE (HIGH in this example)
and will go LOW when data is written out (stored) in Data Buffer B.
Sketch timing diagrams for CBl and CB2 indicating the
reason or significance of each change. When working this out
think of what information the PIA (transmitter) and the external
device (e.g., printer) need to know to transmit data without
loss of data or loss of time.
_ _ _-1/
CB 1 (in)
nf..;.~.~':------\
data received by printer,
therefore new data
can be put on data lines by PIA
I I1-----------
CB2
(out)"
CB2'
~new data now available in
follows
PIA, therefore CB2 goes LOW
OBl state
Again the hand shaking operation permits optimum data
flow. Although the printer would not normally store more than
132 characters for one complete line of text, the data rate within
this line could be as high as 50 000 characters/second, limited
by the computer's clock and the number of instructions per loop.
8-13
One last mode, the STROBE mode is available when
bit #5 = 1, bit #4 = 0, and bit #3 = 1. It is similar to the
previous HANDSHAKE mode in that CA2 goes low when data is read
(LDA A PIABFA) into the A Data Buffer. It differs in that CA2
automatically returns to the 1 state several microseconds (one
instruction) later. Similarly, in the B half of the PIA, CB2
goes low when a write operation (STA A PIABFB) takes place and
returns to the 1 state automatically, several microseconds
later. This mode of operation releases CAl and CBl for other
tasks, but assumes that data is always ready for the "A" half
and that the external device is always ready to receive data
from the "B half. A summary of control line operations is
shown below.
II
CAl (CB 1)
(input only)
7
543
6
2
I
!
CAl (CB1)
READY BIT
(read only)
"'O=DDR access ~
via Data Buff
l=Data Buffer
access
bit #5
o=
,..-__...._---".,A..--°
input
6
5
4
3
2
I
..
f
+
I
I
(0 =
°CAlfor (CB1)
no interrupt
ACTIVE in
(
going LOW
(1 = CAl (CD1) ACTIVE in
(going HIGH
= output
_
,
bit #4
=1.&...._ _-_0..........
,...,..
0 for no
interrupt
BIT
~.,
,
CA2 (CB2) ACTIVEJ
~~~nfci~~~ 'ACTIVE
go~ng HIGH
•
L
PROGRAMMED mode
CA2 (CB2)
t
0 1
1
1
~I/] /Id/h). 10)~1 '?///}
~ >~'(, I a;;1;/t-r i~PI/l
~
j
1~~2)
READY
l
0
I
CA2 (CB2)
7
1
fO_l_IO_W_S_b_i_t_II_3
_
r
HANDSHAKE mode
CA2 (CB2) goes HIGH
following CAl (CB1).
CA2 goes LOW after
READ from A BUFFER.
CB2 goes LOW after
WRITE to B BUFFER.
No answer is required in this frame.
-
"
I
bit #3
=_o_l=
1
r
STROBE mode
CA2 goes LOvl
momentarily after
READ from A Buffer.
CB2 goes LO~l1
momentarily after
~RlrE to B Buffer.
8-14
Here is an application of the PIA to
detect which of the 4 keys, A. B. C or
D was depressed. CA2 provides logic 0
o ~.--tA
to all 4 intersections, the depressed
.....+&
1
key passing on this 0 state to the
Pt f\ 3
P
appropriate input. The symbol at the
top of the diagram is an ~
"inverted input OR gate"
~,.
whose output goes to the 1 state if
one or more of the inputs go to o.
PIA lines 4 to 7 are not needed.
Write the initialization instructions for the PIA to
set up CAl as an input (ACTIVE high) and CA2 as an output.
following bit #3. The Data Buffer should be set up as an input.
~_-a-+--w-«;
--_---..J/
XXllo'M'10
~
'-v-J
CAl
output" input
= bit #3 active
CA2
hi.gh
:+:
*
:+:
:+:
PIA PROG FOR FOUR KEY KEYBOARD.
CA2 IS OUTPUT TO SWITCHES. CAi IS
INPUT TO PIA. DATA GOES TO LOW 4 BITS.
86 7FFi KE1TIPIA LOA A
AND A
:=~·4 F;;'-::
PIACRA
~:::1:l03:
~~1:t~~15
E:~:t
STA A
PIACRA
PIA8FA
~:::11.~::'1f1
0:t~?1S
~;:OFF1.
?F 7FFf1
~:::11J1E: SA 3:6
(1:1(1[) E'?
7FF:t
'I
CLF.~
OF.~A
A
STA A
~* ~,~ :t 1 :1 :1 ~:1 ~~11 ~:::1
ACCESS DDR
DATA INPUT MODE
#~'~~?1~3:1.1~';):1 i~:::1
PIACRA
DATA MODE NOW
8-15
Now flow chart and write the instructions to branch to
KEYA, KEYB, KEYC, or KEYD, corresponding to a depression of
keys A, B, C or D.
-----"/
TR'T'AGN LDA
BPL
LDA
AND
BIT
A
A
A
A
SEQ
BIT A
BEGJ.
BIT A
BEI;J,
BIT A
BEG!
PIACF.:A
Tf;,:'T'ACiN
PIABFA
#$~)F
#$f1::L
KE'r'A
#$02
KE'T'S
#$04
I:: DE:X:
BNE
t'10RDE>~
t'10RDE>::
4 CYCLES
4 C'r'CLES
------"'/
:+:
:+:
8 CYCLES TOTAL
8-17
To get 10 msec., then the # of loops required =
10 / ~6
10 3
10
=
125010 loops
Initialize the counter for this value and write the
complete delay routine.
-----/
NAt1
PF.:OG68
OPT
0.. S
OF.:G
$~j1.€nj
CE 04E2 TIMER LDX
09
MORDEX DEX
#1.25~]
26 FD
MORDEX
:+:
:+: P8-1.7
:+:
BNE
:+:
:+:
4--
No $ silZll for decimal #.
4 C'T'CLES
4 CYCLES
1::1
C'T'CLES TOTAL
This routine would then be executed when CAl first detects
a key hit, which would occur when the key is depressed, and
probably upon release, which also produces transient pulses. Hence
the state of CAl should be checked after the delay. If CAl is still
1 it is a legal key hit. If 0, it is probably due to "bounce" upon
key release, which could then be ignored by the program.
8-18
A stepping motor is another application of a PIA.
Imagine 3 electromagnets or coils, A, B and C, placed at equal
angles around a magnet which is free to turn.
A:~
~;:e~
Each of electromagnets At B and C are directly under control
of a PIA Data Buffer bit, as shown in the diagram below.
A magnet is ON when the appropriate bit is in the 1 state,
and OFF when the bit is o. Energizing magnet C causes the
North pole of the central magnet to rotate to the South pole
at c.
[
C
B
[I
PIA Data Buffer B
A
Set up the PIA to cause the central magnet's North pole
to point to A. Assume that PIABFB is already initialized for
output. Also assume that the South pole of each energized
electromagnet is the closest pole to the magnet, as in electromagnet C.
_ _ _...---J/
0~00
86
~1
0:1€12 87 7FF0
MAGA
LDA A
#:$:~~1~
STA A F'IABFB
Bit #0 (electromagnet A) is ON.
8-19
How would you suggest having the N pole of the central
magnet point to a half way between A and B? Write the
instructions.
------/
€1:10E: 86 ~:1:$
t'lAGA8
0:10A 87 7FF0
LDA A
STA A
#$03
PIA8FB
Both A and B are ON and equally attracting the N pole, causing
it to point between the two electromagnets, at about the 2
o'clock position.
8-20
~
Write the instructions to cause the central magnet to
move clockwise continuously, starting at A. Assume a delay
subroutine call JSR DELAY, which introduces a delay between
each change to slow down the computer changes to acceptable
rotational rates.
---_/
Data Buffer
01.1313
01.132
01.135
131.08
..31.eA
(11.0D
(1:11.(1
(11.1.2
13:1:1.5
€I1.18
13:1.1A
0:1.:1.D
..::t120
86
B-:O
,
80
86
"~tl22
E'?
'I
(
E'"?
'I
8D
86
B7
BC'
86
87
BD
86
(11.
7FF2
€11.32
0-"
..=:.
7FF2
13:1.32
02
7FF2
0132
(16
7FF2
(11.32
04
?FF2
(11.32
MAGA
t1AGA8
MAGE:
'.
A
A
A
A
A
A
.J5~:
t1AGBC
LOA A
STH A
t1AGC
LDA A
5TFt A
JS~:
BD
t'1AGCA
0:1.28 E:6 &.35
€1:12A E''? 7FF2
e:12D BD 0:1.32
13:130 2€1 CE
~~1125
LDA
STA
JSF.:
LOA
STA
J5R
LOA
STA
.J5~:
L[:eA A
STA A
.JSR
BRA
#$131.
PIABFB
C'ELAY
#$03
PIAE:FE:
DELA'T'
#$02
PIABFB
DELA'T'
#$06
PIABFB
DELA'T'
#$134
PIABFB
DELA..,'
#$135
PIABFE:
DELAY
MAGA
-8-21
How would you modify the angular velocity for this
stepping motor, under program control?
---_/
The constant used for the delay could be entered via a keyboard
e.g., using the keys 1 - 9, each producing a different constant
and therefore a different angular velocity. The smaller
constant would then be down-counted sooner, producing a shorter
delay, hence a higher speed.
Modern stepping motors usually have many (dozens) of
coils around 'the circumference I alternating between A, B and C
groups, each group being driven by one specific line, hence
PIA bit. An output of the sequence 001, then 010, then 100
would represent one cycle, usually a few degrees. Reversing
the order would reverse rotational direction.
9-1
.......
SUBROUTINES
In previous chapters we have used subroutine calls
e.g., JSR GETCHR which caused the ASCII code, for the key struck
on keyboard, to appear in Ace A. Such a subroutine call causes
execution of a group of instructions, headed by the label GETCHR
and terminated by
RTS - ReTurn from Subroutine.
After this subroutine has been executed, the next instruction
executed is that following the subroutine call, e.g •
.JSF.:
STA A
CiETCHF.:
KE'T'[:tAT
A program can be made up of a series of subroutine calls,
each causing execution of a particular subroutine, ito carry out a
specific task. Each subroutine should have only one entry point
and one exit point. Entry and exit conditions should be well
documented in the accompanying comments, e.g., IIEnter with X
pointing to the head of a message, and exit when the message has
been printed, with Ace A and Ace B contents being overwritten."
Each subroutine can be individually tested and then used with
confidence when called within the main program.
Program planning should be in IItop-down format, with
overall tasks being defined first, and from these tasks the subtasks defined. Each task can then be assigned to a subroutine
which in turn can call lower level subroutines to carry out the
sub-tasks. Subroutine calls can be many levels deep, if
necessary, those at the lowest level being responsible for the
simplest tasks, like checking a READY bit in an ACIA or a
control line in a PIA. The overall result is a hierarchical or
pyramidical structure, the top levels being general or "global",
the lowest levels looking after detail.
ll
Contd •••
9-1
Contd.
A typical subroutine. properly documented, is
shown here,
7FF4
7FF5
* GETCHR... SUBROUTINE
* ASCII CHAR IN ACC A.
*
$7FF4
SEF.:CSF.:
EG!L1
SEF.:E:UF EG!U
WHICH RETURNS WITH
X AND B NOT CHANGED.
$7FF5
:+:
(11(17 86 7FF4
:=:4 01
(110C 27 F9
~310A
~Z11(1E
86 7FF5
(1:1.11. 39
J3ETCHf;.: LDA A SEF.:CSR
AN[) A
BEG!
#$1211
CiETCHF.:
LDA A SERBUF
F.:TS
[:tATA F.:EA[:tIT'?
NOT 'TIET.
'TIES. GET DATA
AND E::·::1T.
Such a subroutine can be called from anywhere within a program,
avoiding duplication of the above instructions.
A subroutine call JSR ECHO is to cause the character,
struck on the keyboard, to be printed or displayed on the
terminal used. ECHO itself could call 2 other subroutines.
Based on this information write the subroutine ECHO, using only
3 instructions. A subroutine called PRINT is available, to
print the ASCII character in ACC A.
--------/
~31.~3~Z1
SD 01.07
€1:103 SD 1-3:1:12
e1.e6 39
* ECHO... SUBROUTINE TO ACCEPT ASCI
* RECEIVER AND ECHO IT ON THE ACIA
* CALLS GETCHR AND PRINT SUBS..
*ECHO .JSF.:
GETCHF~
GETS INPUT
JSF.:
RTS
PF.:INT
CODE FROM ACIA
TRANSMITTER.
Ar·~D OUTPUTS IT.
AND RETURNS
At this point the details of GETCHR and PRINT are not necessary
except that they both use ACe A.
~
Assuming co.mrnunication to the printing device via the
ACIA, convert the instructions shown below to a well documented
subroutine called PRINT.
PF.:INT
LDA B
AND B
E:Ef~
STA A
SERCSF.:
#$02
PRINT
SEF.:E:UF
READY TO PF.: I NT""!'
NOT 'TIET.
PRINT CHAF.:.
___-------J/
*
0112
0:115
0:1:17
0:1:19
0:1:1C
F6 7FF4
C4 02
27 F9
87 7FF5
39
PRINT... SUBROUTINE TO PRINT ASCII CONTENTS
OF ACC A ON ACIA OUTPUT DEVICE. USES A AND B.
*
*
PF~INT
LDA B SEF.:CSF.:
AND E: . #$1212
BEt]
PF.: I NT
STA A SERBUF
F~TS
F.:EAD'TI TO PF.: I NT?
NOT 'T'ET.
PF.: I NT CHAR.
AND F~ETUF~N.
The documentation is just as important as the instructions
written. Fight off the sometimes overwhelming urge to write
undocumented programs, which usually end up in the waste basket.
six months later.
We could depict the subroutine hierarchy ass
ECHO
"
GETCHR~
PRINT
implying that ECHO calls both GETCHR and PRINT. For lack of a
better name let's call this a "subroutine tree".
-9-)
Imagine a system where the computer is to receive
inputs from 2 ACIA's. It would not be feasible to have the
computer wait in a loop for ACIA #1 since it could lose data
from ACIA #2. The computer could alternately check ACIA #1,
#2, #1 etc., receiving data from an ACIA that is ready. (The
Chapter on "Interrupt" presents another solution.) A
subroutine to check the READY status of ACIA #1, without
reading data, is shown here.
01€10
0103
01.05
01.07
e1.08
01.09
010A
SEFC:CSl
AND A #$01
NODATA
BEG'J.
SEC
SE1RTN RTS
NO[)ATA CLC
E:F~A
SE1RTN
86 7FF4 I NCHK1. LDA A
84 01.
27 02
0D
39
0(:
20 FC
DATA FC:EAD',..?
GOES HERE IF DATA READY
GOES HERE IF NOT READY
Upon exit from this subroutine what is different, when data is
ready, compared to when data is not ready?
-----/
The C bit is set when data is ready, and cleared when data is
not ready.
~
In Appendix C find 2 instructions, each of which branch
conditionally, depending on the state of the C bit. Use one of
them in the main program below, upon return from the subroutine
INCHKl to determine whether or not to store data, MEMADl being
the pointer. If that is not too difficult repeat for ACIA #2,
where MEMAD2 is the pointer within INCHK2, which similarly checks
if ACIA #2 is ready.
BCC - Branch if Carry
bit Cleared
or BCS - Branch if Carry
bit Set
CHECK:.1. JSR
I NCHK1.
BCC
CHEC.:::2
LOX
t'1Et1AD:.1.
INX
STX
t'1Et1ADi
LOA A SEF~BF1.
STA A >~
CHECK2 ,JSF.:
I NCHI<2
BCC
CHECK1.
LO~:
t'1EMAC'2
IN>::
ST>::
t'lEt'lAD2
LDA A SEF.:BF2
STA A X
BRA
CHECK1.
/
ACIA #:.1. READY?
NO DATA HERE
GET POINTER
GET I~~PUT DATA
AND STOF~E IT.
ACIA #--,o:!- F.:EAO'T'?
NO r,lATA HERE
GET POINTER
GET DATA FROt1
AND STORE IT.
#2
The use of the C bit permits decisions' to be made within
a subroutine, without violation of the requirement for a single
return to the mainline program, via one RTS instruction. The RTS
should be the only means of exiting from a subroutine. To violate
this rule, e.g., via a branch instruction, destroys the modular
design of your program and makes de-bugging a nightmare.
-
9-5
Let's look at a subroutine HEXADD which expects 4 hex
keys to be struck. and stores the corresponding 4 character
hex value in 2 consecutive bytes of memory. For example if
keys 2. 3. C and 5 are struck. the 2 bytes of memory would look
like this.
r
1 byte
"' r
1 byte
,
10
1 0
11
I 0 I 0 1 0 1 1 I 1
I1
I 1 I 0 I 0 1 0 1 1 I 0
I1I
'-- 2
Approaching this from a "top-down" direction. assume that we have
a subroutine INBYTE which would return with 23 16 in ACC A when
two keys. 2 and 3. are struck. Write the subroutine HEXADD which
calls INBYTE and produces the 16 bit binary contents in the two
memory locations. ADORES and ADDRES+1.
_ _--c/
:+:
=+:
=+:
£1101'21
1'21103
01£16
131£19
010C
e:1.eD
HEXADO. . . STORES 2 BYTES IN MEf1 AT LABEL ADDRES
CALLS INBYTE TWICE. USES ACC A.
INB'r'TE
BC' 01.13 HEXAr..D JSR
ADORES
1-31.130
STA
A
87
INBYTE
JSR
SD e113
AD[:'~~ES+1.
A
STA
87 e10E
RTS
39
Ar)DRES
Rt1B
2
0£102
GET 8 BITS IN ACC A.
AND STORE THEt-1.
8 t10RE BITS
INTO NE~"~T ADDRESS.
=+:
13113
INB'T'TE EQU
$0:1.13
This "top-down" approach assumes that we could write the INBYTE
subroutine, if it is not already available.
.2=.2.
Now also assume that INBYTE returns with the C bit set
if an invalid hex key was struck; otherwise C is cleared.
Modify the HEXADD subroutine to check for this abnormal condition,
restarting the HEXADD subroutine when such an error is detected.
Modify the documentation accordingly.
:+:
:+:
:+:
---~/
HEXADD... STORES 2 BYTES IN MEM AT LABEL ADORES
CALLS INBYTE TWICE, CHECKING FOR ERROR WITHIN BYTE
SUB VIA SET C BIT. ACe A USED.
:+:
:+:
0::1-£1£1 BD ~]:1:13
~3:1~~13 25 FE:
~1:1~~15 87 '.:11.:1:1
£11.£18 BD '.:1:11.3
€1:1(1B c:..._1 F3
f1:10D 87 €1:1.:1.2
~J:t:1€1 39
!::11.:1:1 1-~1(1f12
INB'T'TE
BCS
HEXADD
STR A ADDRES
.JSR
INB'T'TE
BCS
HE>::ADD
STA A ADDF.~ES+:1
RTS
HE:~-::ADD
..TSR
ADDF.~ES
F.~t1B
.-.~
GET 8 E:ITS IN Ace A.
RESTART IF ERROF.:.
ELSE STOF.:E THEt1.
8 t10F.:E BITS
RESTART IF ERROR
ELSE STORE IN NEXT ADDRESS.
2
A better solution would be to print the message BAD HEX before
restarting HEXADD. This improves communcation between the
computer and the user, an important consideration in program
design.
j;;J.
A subroutine HEXCHR is now available to acquire an ASCII
character in ACC A, when a key is struck, and to convert it to
its 4 bit hex equivalent, e.g., OB results when B is struck.
This 4 bit result will be right-justified (against the right edge
or as far right as possible) in ACC A. Is this where you
ultimately want the first 4 bits inside ACC A when the INBYTE
subroutine, which receives two such characters, is executed?
---..----.-1/
No. If 5 is the first of two keys struck, the 0101 result
must be moved to the left half of ACC A, to make room for
the next 4 bits, which go in the right half when the second
key is struck.
~
Write the first half of the INBYTE subroutine to place
the first 4 bits in the left half of ACC B. Useful instructions
might be ASL A and TAB. Why is ACC B needed? The HEXCHR
subroutine is still available and returns with the C bit set if
an invalid hex key was struck. Such a condition should cause
an immediate return from INBYTE to HEXADD, with the C bit still
set.
~3:t1~~:
BO
~Z11.25
~Z1:t.16
25
1~1C
01:1::: 4':'
'-'
0119
~::11.:1A
4':'
'-'
4':'
'-'
4':'
'-'
0:118
(111C 16
INBIT'TE .JSF.:
Be::;
---------.1/
HE::·::CHF.:
BITITF.:TN
GET 4 BITS
BRD HEX. RETURN NOW.
ASL A
ASl.. A
ASL A
ASL A
TAB
SHIFT 4 BITS LEFT.
STOF.:E IN B
Ace B is used to store the first 4 bits when HEXCHR, which uses
ACC A, is called to get the second 4 bits. RTS passes the C bit,
undisturbed, to the calling subroutine HEXADD.
--9-9
Now finish the INBYTE subroutine including documentation.
The instruction ABA may be useful to you.
_ _ _-J/
The complete INBYTE subroutine might bes
*
*
*
€1113:
13:11.6
e:1.:t8
1!:1:1:t9
e11A
1!:111.B
€1::t:1C
1!:111D
~~112J.3
"~1:122
0:123
13124
ACC
INBYTE... PRODUCES 8 BITS IN ACC A CORRESPONDING
TO TWO 4 BIT HEX VALUES} EACH PRODUCED BY
HEXCHR SUB} WHICH IS CALLED TWICE. USES A AND B
HEXCHR
GET 4 BITS
BD 13125 IN8YTE JSR
.::.,._1 ec
BCS
BYTRTN
BAD HEX. RETURN NOW.
4:=:
ASL A
4'-'
ASL A
.=.
4:=:
ASL A
40::'
ASL
A
SHIFT 4 BITS LEFT.
'-'
TAB
STOF.:E IN B
16
JSR
HEXCHR
GET 4 t10F.:E BITS.
BC' 01.25
IF BAD HE>::
25 02
BCS
BYTRTN
ABA
MERGE BOTH 4 BIT SETS OF DATA
:1B
1!:1t::
CLC
TELL THEM ITS GOOD DATA
E:'T'TF.:TN F.~TS
39
'-,e:'
A
0 0 0 0 1 1 1 0
A"""
vv B
1 1 1 0 0 0 0 0
Ace A
0 0 0 0 1 0 0 1
ACe A
1 1 1 0 1 0 0 1
After the first JSR HEXCHR if E
was struck.
After therAB instruction.
After the second JSR HEXCHrl if 9
was struck.
After ABA. ACe B is added to
ACe A to merge both 4 bit codes.
So far we have HEXADD calling INBYTE twice.
9-10
The HEXCHR subroutine could be formed from the hex
checking program shown early in the Branching Chapter. Write
this subroutine including the following changes I
(a) At the beginning of the subroutine get the ASCII code for
the struck key into ACC A.
(b) Set the C bit if an invalid hex key is struck; otherwise
clear the C bit and return from the subroutine with the
4 bit hex code in ACC A.
Refer to the Branching Chapter for the original hex checking
program. Assume that the GETCHR subroutine i~ available
to receive an ASCII code in ACC A. when a key is struck.
*=
*=
**=
121125 BD 0143
13128 81 2F
012A .-,-.. 14
012C 81 39
0:12E 23 fi(:
121:13121 E::1 4121
€1:t32 23 ec
0134 :::1 46
01.36 22 138
oe:.~
£1138
8~1
37
0:t3A 0C
013B ::~9
et13C 80 3=121
~313E 2~3
0::1.4~3
~1:14:1
HE:X:CHR.
RECEIVES ASCII eODE IN Ace A VIA GETCHR
CONVEF.:TS TO 4 BIT HEX EQUIVALENT IF VALID
AND CLEARS C BIT. ELSE RETURNS WITH C SET.
HE>~CHF~
€1D
.J5F.:
eMF' A
GETCH~~
#$2F
BLS
BADHEX
#$39
cr'1P A
BL.S
NUt10K
#$40
A
er'1P
BADHE::-::
BLS
Ct1F' A #$46
BADHEX
BHI
#$37
SUB A
GOODH:X: CLC
HE>!'F.~Tr·~
F.~TS
NUt10K
SUB
E:ADHE:)~
BRA
SEC
FA
;;::€i F::::
---~/
BF.:A
A
#$3€1
(ECHO WOULD BE BETTER STILL)
BEL.OW 3121, NOT HEX
121 TO 9.
VALID HEX
3A TO 4121.
ILL.EGAL
ABOVE 46. ILLEGAL
TO F IN 4 BIT FORMAT
TELL THEM IT/5 GOOD
A
121 TO 9 IN 4 BIT FORMAT.
GOO[:IH>::
BAD
HE::::
ONE BELOW FIRST CHAR ADDR
STX
MEt1PNT
LDA A #1.6
STA A LINCNT
NULINE JSR
LINE
DEC
LINCNT
BNE
NULINE
RTS
1
\ \ LINCNT Rt18
'---........- - MEt'1PNT Rt1B
2
"--
INIT POINTER.
SET UP COUNTER.
PF.:INT LINE
LAST LINE?
NO. PRINT ANOTHER
LAST ONE.
Note the double vertical bar here
indicating a subroutine.
The address for the first memory address could be produced by
the previous subroutine HEXADD.
9-14
The next task, working downward, is to write the
subroutine LINE, which prints 8 words, each comprising the
contents of 4 addresses. Flow chart and write the subroutine
LINE, assuming that 2 subroutines are available as follows.
- ~ORD, to print one word.
- CRLF, to produce a Carriage Return ~~d Line Feed, to start
the next character on a new line.
_____---J/
*
SET UP
,""OR.O
c.o~N'TER
:+:
:+:
LINE... SUBROUTINE TO PRINT 64 (DECIMAL) CHAR
FROM 32 MEMORY ADDRESSES. CALLS WORD. USES A.
LINE
.JSR
C~:LF
LDA A
STA A
#$~Z1:=:
.JSF~
L·JORD
DEC
BNE
L·JF.~DNUt'1
l·JF~DNUt·1
NULaJORD
RTS
l·JF.:DNUt·1 Rt1B
*
:1.
START NEW LINE
SET
UP
COUNTER
LAST laJORD?
NO. BACK AGAIN.
LAST ONE.
9-15
next subroutine proceeding downward is WORD, which
prints the contents of 4 memory locations, then skips one space.
The subroutine OBYTE, to print the contents of ACe A as 2 ASCII
.
characters is available. SPA~E, a~other subroutine will pr~n"
(or skip over) one space. Flow chart and write the NORD
subroutine.
~he
.
---------J/
~ WORD... SUBROUTINE TO PRINT CONTENTS OF 4 MEM
*
:+:
:+:
ADRESSES AS
ACe A.
USES
l.oJO F.: D
LDA A
R
.JSP
DEC
STA
B'T'TCNT
RETURN
8 HEX
CHAR.
CALLS OBYTE AND SPACE.
#$~:::14
B'T'TeNT
OB'T'TE
B'T'Te~·~T
E:NE
NUB'T'TE
JS~:
SPACE
F.:TS
F.:t18
:1.
INIT
PPINT
COUNTER
1 BYTE AS 2 CHAF.:.
NOT LAST B'T'TE
'T'ES. LAST B'T'TE.
DONE
ONE SPACE.
9-16
The OBYTE subroutine is next. It gets one byte from
memory via the pointer MEMPNT and calls HEXPRT twice to print
it as 2 ASCII characters. HEXPRT is entered with 4 bits
right-justified in ACC A. Flow chart and write the OBYTE
subroutine.
--------/
* DBYTE... SUBROUTINE
* ADDRESS AS 2 ASCII
* ENTER WITH ADDRESS
*OBYTE LD~'::
MEMPNT
TO PRINT CONTENTS OF ONE MEM
CHAR. CALLS HEXPRT. USES A JX.
IN MEMPNT.
IN>-~
TEMP
STX
LDA
STA
ASF.:
ASF.:
ASF.:
ASR
ANC'
.JSF.:
Le'A
AND
.JSF.:
RTS
RMB
MEMPNT
A >::
A TEMP
A
A
A
A
A
#$(1F
HE>::PF.:T
A TEt'1P
A #$0F
HE~·::PF.:T
GET ADDRESS
GET BYTE
SA.. . E COP'T'.
F.:IGHT
.JUSTIF'T'
LEFT
HALF
ZAP LEFT HALF
PF.:INT IT
GET CLEAN COP'T'
ZAP LEFT HALF
PF.:INT IT
DONE
1
Re"'URN
Note the use of TEW~ rather than ACC B. It is not good practice
to tie up an accumulator, when calling a subroutine which may
need the accumulator.
9-11
HEXPRT is entered with 4 bits right-justified in Ace A.
It prints the corresponding ASCII character. Flow chart and
write this subroutine noting that PRINT is available to print
the ASCII contents of ACC A.
~oo
30 TO
ACt " CON'Tetm
*
*
_----J/
HEXPRT... SUB TO PRINT ASCII CHAR. CALLS PRINT SUB.
ENTER WITH 4 BITS RIGHT JUSTIFIED IN ACC A.
HE>::PF.~T
ADD A
#$3~3
CONVEF.~T
Cf1P A
#$]:9
NUt1BEF.~?
TO ASC I I
BLS
OUTPUT
ADD A
#$07
LETTEF.~.
PRINT
OUT IT GOES.
OUTPUT JSR
RTS
A[:ID 7
t'10RE.
PR\NT CHRIl.
Check this routine by testing it first with values 0 and 9.
then with values A and F. plus the 4 values just outside these
legal values.
9-18 ..
Next we need the PRINT subroutine. The printer, via
the CTS control line back to the ACIA, will inform the computer
to stop transmitting while Carriage Return and Line Feed
functions take place. Flow chart and write the subroutine to
transmit data via the ACIA when CTS = 1 (CTS = 0).
----..1/
*
*
*
PRINT... SUBROUTINE TO PRINT CHAR IF DEVICE
IS ON LINE VIA CTS=~ CCTS NOT=0). USES ACC A AND B
ENTER WITH ASSCII CODE IN Ace A.
SERCSR EQU
$7FF4
SERBUF EQU
$7FF5
*PRINT
PIUNT CHAR
LDA
BIT
BHE
BIT
BEQ
STA
B
8
8
A
SERCSR
#$08
PRINT
#$02
PRINT
SERBUF
CTS NOT=0?
NO. TRY AGAIN.
READY?
PRINT IT
F.~TS
RETURN
Loopback for the second test is to the top to ensure that CTS
has not gone to 1, while waiting for the printer to become READY.
9-19
SPACE and CRLF now remain. A problem exists in using
the ACIA with the printer in that the ACIA will transmit the
last character in its TRANSMIT Buffer even though the printer
requests a halt to more data by clearing CTS (Clear To Send).
eTS is normally cleared during a Carriage Return or Line Feed
operation or when the printer is not ready to print data. The
above problem results in the loss of the last transmitted
character. The solution is to send a 2 nulls (ae) to the ACIA
after both the CR and LF characters. ;rhe nulls are then
"sacrificed" to preserve the next legal character printed.
With this in mind, write the CRLF and SPACE subroutines. Flow
charts are not necessary for these.
*
:+:
--_---J/
SPACE... SUBROUTINE TO OUTPUT ONE SPACE CHAR.
CALLS PRINT SUB. USES ACC A.
*
SPACE
LDA A #$20
.JSF.:
I::'R I NT
ASCII FOR SPACE
~:TS
*
*
:+:
:+:
CRLF... SUBROUTINE TO OUTPUT CARRIAGE RETURN
AND LINE FEED CHAR TO PRINTING DEVICE. PADS EACH
WITH 2 NULLS CHAR. CALLS PRINT SUB. USES ACC A.
CRLF
LDA
.JSF.:
CLR
.JSR
.JSR
LDA
. T. SR
CLR
,JSR
,JSF~
RTS
A #$eD
PF.:INT
A
PRINT
PF.:INT
A #$~3A
PRINT
A
PF.:INT
PF.:INT
C~:
OUTPUT NULL
LF
NULL
9-20
To complete the subroutine PAGE, draw the "subroutine
tree" to show the subroutine's hierarchy.
PAGE
---------/
~
LINE
/ "CRLF
WORD
/ "SPACE
OBYTE
HE~p0
In only a few words, the
overview of PAGE is depicted
here.
PRINT
A program could call both the HEXADD and PAGE
sUbroutines, the former to define the starting address and the
latter to print the page of data.
9-21
Near the end of the PIA chapter is a program in which
a delay is used to "de-bounce" a switch before its state is
read by the PIA. This delay could be achieved more easily if
subroutine format was used.
Flow chart and write a subroutine which produces a
delay of N milliseconds, where N is the binary contents of
ACC A. This subroutine should call a subroutine MILSEC which
produces a delay of 1 millisecond each time it is called.
Write the ruILSEC subroutine, assuming 1 microsecond per MPU
cycle. If necessary refer to the PIA chapter for the previous
delay routine.
----~/
tHaT cou,,"ER
'.0 M\LLlSEC
t>E~"Y
10:1130 B7 ~1:10C
~3:103 BD e:113D
0:1~16 7A e:113C
0:1~39
0:10E:
0:113C
* DELAY... SUBROUTINE TO PRODUCE DELAY
* OF N MILLISECONDS~ WHERE N= BINARY
* CONTENTS OF ACC A ON ENTRY. CALLS MILSEC.
*DELA'T' STA A COUNT
STO~~ES N
t10~:t'1
I L .JSF.:
26 F8
39
~~10e:1
COUNT
DEC
BNE
RTS
Rt'1B
t1ILSEC
COUNT
t10Rt1IL
ONE t1ILLISEC
NOT LAST YET
:1
*=
* MILSEC... SUB TO P~:O""'IDE
* ONE MILLISECOND DELA'T'.
*t1 I LSEC LDA A #:113121
e:10D 86 64
STA A t'1ILCNT
13:113F 87 ~1:1:1.8
~1:1:12 7A ~~1:1:1.::: t'10RDEC DEC
t'1ILCNT
t10RDEC
BNE
~:1:15 26 FB
0:1:17 39
~:TS
10:1:18 131313:1
t1 I LCNT RME:
:1
The 2 loop instructions DEG ~ILCNr and BNE MORDEe take 6 + 4 = 10 10
MPU cycles or 10 microseconds. Therefore 100 10 or 64 16 loops
provide a delay of 1000 microseconds or one millisecond.
9-22k&
I
In the previous frame MIIJCNT could have been given an
initial value of 64 16 sim~ly via
MILCNT FeB $64
eliminating the need for the 2 lines of initialization at the
start of the MILSEC subroutine. Would this be acceptable? Why?
------/
No! The subroutine would execute properly the first time it is
called, MILCNT being decremented from 64 to o. The second time
(and all subsequent times) that it is called MILCNT would start
at FF, after first being decremented from 0 by DEC MILCNT. This
subroutine MILSEC would then go through 25610 loops to reach zero,
instead of 100 10 loops, producing an incorrect delay. Selfinitialization is required within the subroutine to reset MILCNT
to 64 every time the subroutine is called. Lack of selfinitialization is a common catastrophic error when coverting a
program, which runs correctly once, into a subroutine which is
called many times within a larger program.
This concept should be ext~nded to all programs, as well
as subroutines enabling faulty programs to be restarted during
de-bugging without the necessity of being reassembled or reloaded.
Enough said for now about subroutines!
10-1
STACK OPERATIONS
Previously we have seen data storage in which the Index
Register was used as a pointer. Another 16 bit register. the
Stack Pointer (Sp) is also used to store and retrieve data.
employing a user-defined block of memory, called the stack, for
the storage operations. 'rhe Stack Pointer may be initialized
to point to the address lC40 ·J'ia
LDS #$lC40 (LoaD the Stack pointer)
Another instruction
PSH A (PuSH accumulator A)
performs a "push" operation, that is it stores the contents of
ACC A in the address now contained in the Stack Pointer. The
Stack Pointer is automatically decremented after the storage
operation.
"PuSH" is an appropriate description, similar to the
"pushing" of individual serviettes into a metal holder, each
new serviette now being on the top of the stack.
Initialize the Stack Pointer to lAFF, then store the
contents of Ace A and Ace B on the stack in that order.
01.00 8E 1.AFF
LDS
01.03 36
0104 37
PSH A
PSH B
---_/
#$:1.AFF
Stack Status
lAF r:
lAF E
lAF F
Diagr~ns
lAr' " " ' ) - - - - - f
lAF -""---'11
~SP
Before P3H A
SP/lAFF
lAF.,·~_...... 3P
lAF-,:.=._.=--::::ot
lAF
After PSH A After PSH B
lAF·
~~.;.;;lI
~~~
10-2
Data can be retrived from the top of the stack via
PUL A
which "pulls" the data off the stack into ACC A. 'rhis is
similar to retrieving a stored serviette from the holder, the
last one in being the first one out. In the PUL operation the
stack pointer is incremented automatically, before each byte is
retrieved. Assuming the 2 PSH operations in the previous fr~~e
the instructionsl
PUL B
PUL A
32
first transfers the data, stored in lAFE, into Ace B, then
transfers the data from lAFF into Ace A. Note that the PUL
operations are in the reverse order to the PSH operations,
respecting the "Last In First Out" (LIFO) sequence.
Use of the stack permits temporary storage of data without
the need for a symbolic address or an accumulator usage. Modify
this now familiar subroutine to operate without ACe B. Assume
previous stack pointer initialization.
PF.:INT
L.DA E:
SEF.:C5 F.:
AND E:
BEG!
#$(12
5TA
A
PF.:INT
SEPBUF
TO PF.: I t·JT?
NOT 'T'ET.
F~ERDITI
PP I NT CHAF.:.
AND PETUF.:N.
F.:TS
-----------------7FF4
7FF5
SEF.:C5R EI~~U
SEF.:E:UF EG!U
:t?FF4
$7FF5
:+:
..:1:1tUj
t11J::'1!
\.31\.34
":1:1":16
3:6
E"'I::,
:::4
27
01.0::: 3:2
\.3:t(19 E'-;:O
'I
1~1~l(1C
39
WARNINGs
PF.:I NT
PSH A
7FF4 NOT'T'ET LDA A
\.32
AN[:t A
F9
BEG!
SEF.:CSF.:
#$02
NOT'T'ET
PUL
'7FF5
A
5TA A
F.:T5
SEF.:E:UF
For every PSH there must be a corresponding PUL to
restore the stack pointer to its original state.
/
10-)
Assume that the main line program which calls this
PRINT subroutine iSI
.JSR
07C3: 8[) :1.3:5E:
07C6 FE 077E
LDX
PF.:INT
t1Et1PNT
If the stack pointer contains lAFF just before JSR PRINT
is executed, the address of the next main line instruction, 07C6
in this example, is stored on the stack. The low byte (C6) goes
into lAFF and the high byte (07) goes into lAFE. The stack
status at this point is depicted by this diagram.
The RTS instruction at the end of the subroutine
automatically performs two PUL operations,
restoring the 07C6 value in the Program Counter.
lAFO
~SP
The next instruction executed is then from 07C6,
lAFE 07
the LOX MEMPNT instruction following the
lAFF c6
subroutine call.
Assume that the first byte of JSR PRINT resides in 0426,
and that the stack pointer contents is 13CB just before JSR PRINT
is executed. Draw the stack diagram showing stack contents and
SP value for each stack change, starting just before JSR PRINT is
executed and finishing when LOX MEMPNT is executed. The PRINT
subroutine is the one given in the answer of the previous frame.
--_/
r--...,
...SP
13C 7 04
....SP 13C 8 29
lJC 8
before
JSR PRINT
just after
JSR PRIN'r
1
~SP
13C5
. lJC 6
the next PSH
overwrites 29
~CC
SP
A
04
13C8 29
after
PSH A
lJe
after
PUL A
after
RTS
-
10-4
Examination of data stored on the stack is achieved vial
TSX - Transfer Stack pointer to indeX register.
which transfers the Stack Pointer to the Index Register, then
increments the. Index Register. In this way the Index Register
points at the last byte stored on the stack. This permits
direct access to the data, storea l)n the stack, wi thout
disturbing the Stack Pointer. Wri tl~ the instructions to print
the value of the last byte, stored on the stack. The subroutine OBY'l'E is available.
-------..;l'/
0203 30
0204 A6 0€1
02€16 E:D €1142
TSX
LDA A X
.JSR
OBYTE
10-5
Assume' that 4 bytes have been stored on the stack. It
is now desired to increment the first of these 4 bytes without
disturbing the stack pointer or other data on the stack. Write
the necessary instructions.
_ _ _----.II
~11 ~3 ~:::1
~31"31
J: ~:::1
6C
~~f3:
INC
'rsx
SP + 1
=
~
X
-+-SP
7JF5
x
4
7JF6
1
• ••••••••• 1, X
7JF7
2 • ••••••••• 2. X
7JF8
Iii ·
J, X
7JF9
More stack operations will be seen in the next chapter, Interrupt,
where the stack is used extensively.
·
.
11-1 (a~
INTERRUPT
The simplest type of "interrupt" operation is that
produced when you start the 6800 microcomputer by pushing the
RESET button. This starts execution of a permanently stored
program or "service routine". as interrupt initiated programs are
called, this one servicing the RESEr button. When this button
is pushed the RESET line to the MPU is grounded. This causes
the computer to look in addresses FFFE and FFFF (called "vector"
addresses) for the address of the RESET service routine. The
RESET service routine is then started. typically clearing all
READY bits, initializing the stack pointer and setting up
input/output devices such as the PIA or ACIA for the required
mode of operation.
The RESET line also can be converted to force a restart
of this service routine automatically when power is first
applied, eliminating the RESET button. This is particularly
useful when the microcomputer controls an electronic subsystem
or an appliance (e.g., microwave oven).
Another form of interrupt provides the solution to the
problem of determining when a peripheral device has data or
requires data, without the continuous check of READY bits in an
ACIA or PIA. Under interrupt operation, such devices are ignored
by the computer until the device demands service, whereupon the
computer suspends its present operation. known as a "background"
program and executes the service routine or IIforeground program
for the device which demanded service.
ll
Such service may involve the transfer of one byte of data
or the change of several bits in a status register. When the
service routine is completed the computer resumes execution of
the background program.
11-l(b)
Several points are relevant to interrupt operations.
(a) As stated above, READY bit polling or testing, as a routine
operation, is now eliminated permitting more flexible and
efficient use of the computer. With interrupt operation
the peripheral devices essentially say to the computer
"Don't call us. v~e' 11 call you.
It
(b)
The service routine is entered each time that a character
is transmitted or received by the interrupting device or
each time that a push button activates a PIA Control Line.
Such a service routine is short, typically requiring )0 to
60 microseconds to execute.
(c)
The elapsed time between successive interrupts by a
particular device is usually long, compared to the execution
time for a service routine. Even at high data rates such as
960 Characters/sec., the time between successive interrupts
is approximately 1 millisecond. For push button activated
interrupts this time could be seconds to hours. Consequently
it is possible to service many devices via interrupt and
still execute background programs for a large percentage of
the computer's available time.
(d)
Interrupt programs are not recommended initially because
programming errors are more difficult to find. Orderly
de-bugging, possible with nested subroutine type programs,
is less applicable here because the occurrence of interrupts
is essentially random in time. This makes it difficult to
determine the conditions of various registers at interrupt
time, if a service routine occasionally fails.
11-1 (c)
Interrupt serv~c~ng of interfaces such as the ACIA or
PIA usually involves "Interrupt ReQuest" or "IRQ" operation, also
known as "Maskable Interrupt". Such an interrupt
request is made by grounding of the IRQ line to the
~SP
MPU by the interrupting interface. This causes the
present contents of the Program Counter, Index
CCR
Register, ACC A, ACe B and the CCR to be pushed
Ace B
automatically on the stack in the above order.
Ace A
IXH
After p~oviding service to the interrupting device
the IRQ service routine is terminated by the
IXL
PCH
instruction
RTI (ReTurn from Interrupt)
PCL
which automatically pulls the stored values from the
stack, restoring the above registers and accumulators to their
state when IRQ operation was requested. Resumption of the background program takes place as if nothing happened (except for the
slight delay to provide IRQ service).
IRQ operation first requires initialization of the IRQ
Vector Addresses, FFF8 and FFF9, with the address of the IRQ
Service Routine. IRQ operation (interrupt service) will then take
place if all the following are truel
(a) The Control Register of the appropriate interface (ACIA or
PIA) has been permitted to interrupt. For example bit #7 of
the ACIA Control Register is set to permit ACIA Receiver
Interrupt. PIA interrupt via CAl is permitted by setting
Control Register bit #0.
(b)
The interface (ACIA or PIA) must activate (ground) the IRQ
line. This happens automatically when the READY bit is set,
indicating that data is ready from the ACIA Receiver, or
that data is needed by the ACIA T·ransmi tter, or that an input
Control Line in the PIA is now ACTIVE.
(c)
The I (Interrupt) bit of the CCR must be cleared, e.g., via
the instruction
CLI (CLear Interrupt)
which permits all IRQ-connected interfaces to interrupt.
Hence IRQ operation is controlled "globally" via the I bit
and locally via each Control Register.
ll-l(d)
The PIA and ACIA. connected for interrupt operation. are shown
in the block diagram below.
I
DEVICE
sera•Q \ d0.t CI.
0. \
d a. tel
ou t
f!A _
-1 &'T (bit.oal)
XRQ
I c:,,, I 51! TS
EXTE~NAL
I
.7
-
'"
I
r'
ACtA
I
m
fR~
'800 MPU
I(~ierr"pt EMbled)
Before the I bit is cleared to permit IRQ operation,
several preparations for interrupt operation must be made,
usually referred to as "background initialization". These area
(a) Set up the IRQ vector addresses FFF8 and FFF9 with the service
routine address.
(b) Set the Control Register bits of the appropriate interface
(ACIA or PIA) to permit an IRQ request via the receiver,
transmitter or Control Line.
(c) Set up any data pointers for storing or retrieving data.
Only now can the I bit be cleared to permit IRQ operation.
Write the background initialization to set the address
of ACIARX, the start of the ACIA service routine, in addresses
FFF8 and FFF9.
---"/
LDX
STX
IACIARX
$FFF8
INIT VECTOR FOR IRQ
When an interrupt occurs, the contents of the accumulators
and registers will be pushed on the stack. Then the address of
the next instruction to be executed will be obtained from FFF8
and FFF9, the IRQ vector address. In other words the next
instruction to be executed will be the first instruction of the
the IRQ service routine.
11-2
....Continuing with the background initialization, set
the ACIA Receiver Interrupt bit, to permit interrupt to occur.
Then initialize MEMADD with the address one below address lAOO,
to permit storage of data from the ACIA Receiver. Assume, as
before, that ACIACR is the "original" for the "write only"
Control Register of the ACIA.
-----.;/
LDA A
ACIACF.:
O~:A
#~10e00000
A
ENABLE RX INT
STA A ACIACR
STA A SERCSR
LD::.-::
#$1A0~1-1
STX
MEMADD
SET UP STORAGE POINTER.
So far the background initialization is.
131121121
121103
011216
011219
01€1B
010E
011:1
12111.4
CE 011C
FF FFF8
86 738E
8A 80
B7 73E:E
B7 7FF4
CE 19FF
FF 01.1.A
LDX
STX
LDA
ORA
STA
STA
LDX
STX
#ACIARX
$FFF8
A ACIACR
A
INIT VECTOR FOR IRQ
#::-~1000001210
A ACIACR
A SERCSR
#$:1A013-:1
l'1El'lADD
SET
ENABLE
UP
R>-~
INT
STORAGE POINTER.
Now complete the background initialization by clearing
the interrupt bit in the Condition Code Register. At this point
a background task could be started. Since we have no background
task to do at this time, put the computer in an endless loop,
which will be interrupted from time to time by the ACIA, when
it receives another character.
-----..,,/
CLI
HF.:
E:F.:A
ENABLE INTERRUPT
BACKCiF.:OUNO LOOP
HF.:
The complete background initialization to provide
interrupt service for the ACIA Receiver is then
10:1.12110
10:1.103
0:1.06
10:1.1219
12I:1.I2IB
12I:1.0E
121:1.:1.:1.
1211:1.4
0:1.17
121:1.:1.8
e:1.:1.A
CE e:1.:1.C
FF FFF8
86 73SE
SA 8121
B7 738E
B7 7FF4
CE :1.9FF
FF 011.A
€IE
2121 FE
HR
1211211212
t1Et1ADD
LL">~
STX
LDA
ORA
STA
STA
LDX
STX
CLI
BRA
RMB
#ACIARX
$FFF8
INIT VECTOR FOR IRQ
A ACIACR
A #~~:1.0012112112100 ENABLE R>:: INT
A ACIACR
A SEF.:CSR
#$:1.A00-1.
t1EMADD
SET UP STORAGE POINTER.
ENABLE INTERRUPT
BACKGROUND LOOP
HR
2
11-4
Now write the service routine ACIARX, which stores ~
byte via MEMADD each time that the service routine is entered.
Terminate this service routine with RTI, which returns control
to the interrupted background program.
--_----J/
0:1:1C FE 0:11A
01.iF 08
0120 FF 01:1.A
0:123: 86 7FF5
0:126 A7 00
0128 38
* INTERRUPT SERVICE ROUTINE FOR ACIA RX.
* STORES ONE CHAR IN MEM VIA MEMADD POINTER.
*ACIARX LDX
t'1Et1ADD
INX
ST>::
t"lEt'lADI)
L[:IA A SEF~BUF
STA A>::
F.~T I
GET NEXT ADDRESS
GET DATA
AND STORE VIA MEMADD
AND RETURN TO BACKGROUND.
Each time that the ACIA's Receiver is READY with another byte of
data, bit #0 of its Status Register will go to 1, indicating the
READY condition. Since bit #7 of the ACIA Control Register is
also set, permitting ACIA Receiver Interrupt, the setting of the
READY bit automatically activates the IRQ line to the iJIPU,
causing execution of the service routine whose starting address
is in FFF8 and FFF9. After the RTI instruction of this service
routine the background task, if there is one, will be resumed.
A long story isn't it?
11-i
Printing a message via the ACIA under interrupt is
similar to data reception in the previous frame. Here the
ACIA Control Register bits #6 and 5 must be initialized to
provide "RTS = low, Transmitting Interrupt Enabled". (See
Appendix E).
Write the background initialization to permit printing
of the message INVALID HEX via the ACIA under interrupt.
Include the message in the background initialization.
/
-----------------~1:.1.. &.3~3
&':::':1&.Z1]:
":::':1&.36
.31.(19
":::'1 .:::,8
(11.1-3D
(':1.1&,:::,
01.13
1-)1:16
CE &.Z1:12A
FF FFF8
E".t,::• 73::=:E
84 SF
:=:A 2(1
E'-.,::O 73E:E
Eo"::'
., 7FF4
CE &.3:1.:1.8
FF &.312S
1-:::':1:1.9 "3E
":;:'1:tA 213 FE
HP
LD>~
#MESPRT GET INT ROUTINE ADDRESS
ST;:-::
IRQVEC
INIT MESSAGE POINTER
LDA A ACIACF.:
AND A #%1.0:1:1111:1. CLEAR BIT 6
oF.:A A #%130100000 SET BIT 5 TX INT ENABLED
STA A ACIACR
UPDATE ORIGINAL
STA A SERCSR
SET UP ACIA
LD::·::
#8ADHE::-::-:1.
ST::-::
MEMADD
SET UP POINTER
eLI
8 F.: A
HR
SPIN FOREVER
:+:
\.311C 49
a.Z1:1.27 1.: :,&.:;:,
&.3:12S &.3(1&.32
BADHE::·:: FCC
FeE:
t'lEt'lAO[) F.:t·18
••••1
I N\,'AL I D HE::·::.····
1-3
2
11-6
Within the service routine how will you ensure that the
ACIA Transmitter will stop sending characters to the printer,
after the last character of the message is printed?
/
---Contd •••
11-6
Peptd.
Disable the transmitter interrupt by clearing bits #6 and 5 of
the ACIA Control Register (see Appendix E). If another device
is still operating under interrupt, the above operation will
affect only the ACIA transmitter. If the ACIA transmitter was
the only interrupting interface, then all IRQ interfaces could
be interrupt disabled by the instruction SEI (SEt Interrupt),
the opposite to eLI.
11-7
Now write the service routine. entered each time ~o
print one character of the message. Assume the background
initialization shown in the previous fr~ne.
---_/
~3:12A
0:12(:1
0:12E
(11.3:1
(1:13:3
~~1:13:5
FE
(18
FF
A6
.-0::..'...,.
.
E:7
38
86
84
6'-::'
8-:0
,.'
(1:13:::
(11.39
01.3C
(1:1.3E
(1:141.
(1:1.44 20
'.
(1:128 t'1ESPF.:T L(:I;:'::
IN::-~
0:128
"~10
04
7FF5
73:=:E
9F
73:=:E
7FF4
F'-'
c..
ST>::
LDR
BEG!
STA
PF.~TF.:T I F.:TI
NOt10F~E LDA
AN[)
5TA
STA
E:F.:A
t'1F'U CYCLES
5
4
MEMADD
6 GET CHAR ADDRESS
X
5 GET CHAR
4
NOt10F.~E
5 PF.:INT IT
SEF.:8UF
:1.0 TOTAL 39 MPU CYCLES
ACIACF.:
t1Et'1A()D
A
A
A
A
A
A
#;·~:1.(u~1:t:1.:t:11
RCIACR
DISABLE TX INT
SEF.~CSF.~
PF.~TF.~T
I
At slow terminal rates e.g. 10 Characters/sec one character is
printed every 100 msec. At higher data rates e.g. 960 char/sec,
one character is printed every 'millisecond. The above service
routine requires 39 MPU cycles plus 9 to push and interrupt.
Assuming approximately 50 MPUcycles per interrupt, this is
still only 50 microseconds, using a 1MHz MPU clock. Hence
10 000 to 20 000 interrupts per second are theoretically
possible, supporting dozens of devices. Therein lies the power
of interrupt.
-
11-8
So far we have looked at only one device operating undeL'
interrupt at one time. Consider an ACIA connected to a printer
(output) and a keyboard (input), both operating under interrupt.
When an IRQ operation is demanded by one of these devices, the
first task of the service routine is to determine which device
produced the in terrupt. Irhis is done by consecutively checking
the READY bit of each device capable of IRQ operation.
Write the first part of the IRQ service routine IRQSER
which determines whether the ACIA's receiver or transmitter
requires service, branching to KEYSER to service the keyboard or
PRTSER to service the transmitter.
:fi
0200
12121213
12121215
12121217
86
85
26
85
7FF4 IRQSER LDA A
1211
8IT A
49
BNE
1212
BIT A
121209 26 65
8NE
0208 38
INTRTN RTI
--=-----~/
SE(;'~CSR
#$1211
R>~
READ.,.'?
KE'r'SER
#$1212
TX READY?
PRTSER
RETURN POINT FOR ALL
Both servifYe
routines would
branch back
to here.
Although all IRQ controlled devices are theoretically equal for
interrupt service it is normal to poll the READY bit of the
fastest device first, if one is significantly faster than the
other to avoid losing data from the faster device while servicing
a slower device. Hence the first device polled effectively has a
slightly higher priority, this advantage increasing as more
devices requiring IRQ service are added to the system.
11-9
PIA Control Lines acting as inputs can produce IRQ
operation if enabled for interrupt via the PIA's Control
Register. When bit #0 of Control Register A (or B) is set,
interrupt is then possible via CAl (CB1). Similarly CA2 (CB2)
is enabled via bit #3. CA2 (CB2) as an output line does not
produce an interrupt since interrupts originate with the external
device such as a keyboardttelling the computer that data is ready
to be moved or that some control action is needed.
Write the background initialization to permit CAl of the
PIA to interrupt when going high (1) and CA2 as an input to
interrupt when going low (O). The A half of the PIA should be
set to receive 8 bit parallel data.
------.1/
* PROG TO SET UP PIA A HALF AS INPUT
:+:
PINPUT
L.[:tA A
A t-J [:t A
5TA A
CLF.:
OF.: A A
5TA A
l_[:':;::
5T::-::
CLI
HR
E:~:A
PI ACF.:A
# ~-~ 1.1I-Z1\.~11. ~1 :1.1.
PI ACF.:A
CLEAF.: BIT 2
PIABFA
INPUT t'100E
# ::-~ ~3 ~1I-:::n31.1.1.1.
PIACF.:A
#PIASER
$FFF8
to
!
x
X 0
o
Buffer
~Al Active high
Data
1 1 1 1
t ~ tCAl interrupt
REA:r
•
BITS
, " ~enabled
CA2 CA2
CA2 Interrupt
input Acti va enabled
line low
11-10
When an interrupt is produced by CAl of the PIA the
service routine is to store bits #0 to J of the Data Buffer in
LODATA. An interrupt by ~A2 should store bits #4 to 7 in
HIDATA. Assume that CAl and CA2 are the only source of interrupts.
Write the service routines.
0350
0352
0100
0103
0105
0107
0109
0i0A
010D
0i0F
0112
01i4
0117
0119
0iiC
86
2B
85
26
38
B6
84
87
20
86
84
87
20
-------.i/
$0350
$0352
HICJATA EQU
LODATA EQU
*
7FF1 PIASER
LDA A
05
BMI
40
BIT A
0B
SHE
PIARTN RTI
7FF0 CAiINT LOA A
OF
AND A
0352
STA A
F5
BRA
7FF0 CA2INT LOA A
F0
AND A
0350
STA A
EB
BRA
PIACRA
CA1.INT
CA1 INT F.:EGJ.UEST VIA BIT 7
#~. ~010e0000
CA2INT
CA2 INT F.:EQUEST VIA BIT 6
PIABFA
#$0F
LODATA
PIARTN
PIABFA
#$F0
HIDATA
PIARTN
ZAP HI BITS
ZAP LO BITS
If several PIA's are connected as IRQ devices. but capable of
interrupt via CAl only. the skip chain becomesl
LDA A PIACR5
BMI
PIA5
LDA A PIACR6
BMI
PIA6
etc.
11-11
Another major use of IRQ operation is in controll1ng
the timing of specific computer operations. For example a
digital voltmeter m~y be required to make a measurement in a
lab experiment or in a process-control operation at the rate
of 10 measurements per second. Aside from the inaccuracy of
using timing loops for control of these measurements, the
computer is not available for other tasks.
The solution is in the use of a "Real Time Clock",
a device which produces interrupts at specific times or rates.
The service routine for the real time clock would then determine
which devices. get service at what times. In the example above,
the real time clock could be driven by the 60Hz line signal
producing 60 interrupts/sec. Write the background initialization
and service routine for this clock which causes the digital voltmeter to make 10 measurements per second via the subroutine
DVMSER.
_ _ _-.--J/
0:1.£10
0:1£12
1211.1215
0:108
86 06
87 0:11C
CE 0:1.0E
FF FFF8
01.08 0E
01.0C 2121 FE
HERE
LDA A
STA A
LOX
STX
CLI
BRA
#$(16
COUNT
#CLKSER
$FFFE:
HERE
*'CL~(SER
COUNT
DEC
CLKRTN
BNE
121:111. 26 08
LOA A #$06
£1113 E:6 1216
STA A COUNT
121:1:15 87 0:11C
DVt'1SER
JSR
0:11.8 BD 0240
CLKRTN RTI
£11.18 38
e1.0E 7A e1.1.C
12I:1:1C 121001.
*'
COUNT
Rt'18
SPIN IN BACK
NOT THIS TIME
'TIES. RESET COUNTER
AND MEASURE VOLTAGE
ALL DONE
1
This line frequency-controlled clock is a very simple timer.
Real Time Clocks, much more complex than this, are commercially
available.
11-12
The Non Maskable Interrupt (NMI) is essentially the
same as the IRQ with the following exceptionsl
(a) It is always enabled (capable of interrupting), independent
of the I bit status.
(b) Its vector addresses are FFFC and FFFD.
(c) It will interrupt only when the MPU's NMI line changes
state from 1 to o. It will not re-interrupt until after
NMI has gone high and then is grounded again.
NMI operation is needed when a high speed device requires
high priority service, even if an IRQ service routine is
presently being executed, in which case the IRQ service routine
is interrupted to provide M~I service.
During an NMI service routine all other interrupts are
automatically disabled, hence NMI service routines cannot be
interrupted even for another NMI device. Upon return from an
NMI service routine, service will be provided for another NMI
device, if one is waiting; otherwise it will resume service to
an interrupted IRQ service routine, if one was interrupted.
If
none of these are waiting,service will be provided to other
waiting IRQ devices, or to a background program, in that order.
Assuming that an NMI device interrupted an IRQ service
routine, show the state of the stack (in general terms) during
the NMI service routine.
_ _ _--.-J/
t-----1
. . SP
}
DURING NMI
IRQ Status
7 bytes
UPON RETURN TO IRQ
SERVICE ROU'rINE
1---1
Background Status
7 bytes
}
J...--
__
Background Status
7 bytes
11-13
In de-bugging a faulty program it is sometimes necessary
to know the status of internal registers (A, B, X, etc.) after
execution of a specific instruction within a program. This is
possible via the instruction
SWI (SoftWare Interrupt - operation code JF)
If JF (SWI) is placed in memory, in the byte following a specific
instruction, normal program execution will take place until this
)F is encountered, whereupon all internal registers will be
stored on the stack, as if entering an IRQ or NMI service routine.
In this case the program will transfer control via vector
addresses FFFA and FFFB to the SWI service routine, which usually
prints out the contents of the internal registers from the stack.
Insertion of the )F code destroys the original program, hence
most systems require RESET after an SWI service routine is
executed. An exception to this exists in some de-bugging programs
which save the byte which was replaced by 3F, and then restore it
after execution of the SWI service routine.
In some 6800 systems where the SWI routine is provided in
permanent or "Read Only Memory" (ROM) the vectors for SWI may also
be in ROM, rather than in Read/Write Memory, usually called R~~
(Random Access Memory), which can be initialized via RESET. If
vectors are permanent a user-written SWI routine cannot be
implemented.
Why is the stack essential to SWI operation?
------/
Data must be saved by MPU hardware rather than via software
(program) which itself would use some of these registers and
therefore modify their contents.
11-14
Write the background initialization and the SWI serv~ce
routine to print the contents of CCR, ACe B, and ACC A simply as
6 ASCII characters, one after the other, when SWI is encountered
within the program. Assume an available subroutine, OBYTE,
which prints 2 ASCII characters, based on the 8 bit contents of
ACe A.
_ _ _-----J1,/
:+:
:+:
:+:
:+:
FFFA
SWIVEC EQU
:+:
:+:
0200 CE 0240
~321-33:
~3206
SOFTWARE INTERRUPT SERVICE TO PRINT CCRJ
ACC A AND B ON CONSOLE TERMINAL. CALLS OBYTE SUB.
BACKGROUND INITIALIZATION FOR SWI.
LD>::
#Sl'~ I SEF.:
FF FFFA
HF.:
2"3 FE
:+:
:+: S~·JI
:+:
024..:::'
-..::.....:::,- ,
0241. BD
~3240
0244
0245
024:3
..3 249
024C
~11.42
3:2
BD 01.42
32
B[)
~11.42
20 FE
HEF.:E
E:F.~A
OBYTE
HF.~
SER'·lICE ROUTINE
OF.:G
$0240
PUL A
.JSF.:
OB'T'TE
PUL A
.J 5F.:
OB'r'TE
PUL. A
.JSF.:
OB'T'TE
HEF.:E
BF.:A
:+:
01.42
$FFFA
EQU
END
GET CCR FF.~Ot'1 STACK
PF~INT CCF.:
PF.:INT B
PRINT A
11-15
Now write the first part of a different SWI service
routine SOFINT, which prints a more readable output of the
stored data, e.g.,
CCR= XX (where XX = stored CCR value)
Assume the following a~ailable subroutines I
OBYTE - prints contents of ACC A as 2 ASCII
character.
OUTMES - prints ASCII message terminated by
null. X = pointer.
CRLF
- Carriage Return and Line Feed.
:+:
:+:
:+:
0200 CE 0250
02103 FF FFFA
:+:
:+:
0250
0250
0253
10256
0259
025A
8D 0:179
CE 028:1
---------/
PRINTOUT OF REGISTERS AFTER SOFTWARE INTERRUPT
LDX
ISOFINT
STX
$FFFA
INIT SWI VECTOR.
NOW JUMP TO TARGET PROGRAM
OF.:G
SOFINT JSR
LDX
$02510
CRLF
ICCRt1ES
OUTMES
PRINT CCR=
..JSF.:
OBYTE
PRINT CCR CONTENTS
CCF.:t1ES FCC:
FCE:
. . . eCR=
BD 1.F0C
JSF.~
PUL A
3:2
8D 0142
:+:
:+:
0281 43
0286 1Zn.3
I
~3
Note that entry to OBYTE is at 0142, rather than at 0139, in
the original OBYTE routine (Subroutine Chapter), since the data
to be printed is already in ACC A. The CRLF routine is also
from the Subroutine Chapter. The OUTMES routine is from the
ACIA Chapter, bu~ in subroutine format.
11-16
Execution of the OBYTE subroutine involves use of the
stack. Will this destroy data now on the stack, yet to be
printed within the SWI service routine? Use stack diagrams to
prove your answer.
No.
-_-------.#/
Data to be printed will not be destroyed •
. .SP
. .SP
RH
RH
RL
RL
CCR
CCR
B
B
B
B
A
A
A
A
IXH
IXL
IXH
IXL
IXH
IXL
IXH
IXL
PCH
PCR
PCL
peL
Within SWI
service
routine
before
I?rintout
begins.
~SP
After
first
PUL A.
peH
peL
Within OBYTE sub.
RH and RL are
return address
bytes. H = high,
L = low. CCR data
on the stack is
overwritten but
only after it is
in ACC A for
printing.
~SP
PCH
peL
After return
from OBYTE
subroutine.
RL and RH will
be overwritten
in future use
of the stack.
11-17
Cont inuin g with the same serv ice rout ine. assum e that
eCR. ACC B and ACe A have been pulle d and prin ted on one
line.
How woul d you prin t the Index Regi ster cont ents. stil l
cont inuin g
on the same line? Inclu de the mess age in your answ er.
0271.
0274
121277
13278
027E:
027C
CE
~1291
LD::-::
BD
1.F~3C
.JSR
PlIL A
JSF::
PUL A
32
-BD
.....-.
0:1.42
.::or:!.
BD 13:1.42
JSF~
- - - - - .. 1 /
# I ~·::t1ESS
OUTt1ES
PRINT ::.(=
OB'r'TE
PF.:INT
HI B'T'TE OF
OB'r'TE
PF:~INT
LO B'r'TE OF ::-::
::.::
:+;
:+;
13291 213
121295 13(1
I >f,t1ESS FCC
FeB
/ ~
X= ~
Note spac e befo re
0'
and afte r mess age
to make mess age
read able .
Such a routi ne is norm ally inclu ded in the comp uter
syste m softw are and is esse ntial in "de-b uggin g" faul ty
prog rams .
By setti ng SWI (JF) in the main progr am. just afte r a
subr outin e
call. the resu lts of the subr outin e can be exam ined in
deta il to
deter mine how it perfo rmed . The place in the main progr
am wher e
the SWI occu rs is often calle d a brea kpoi nt.
More soph istic ated de-bu g rout ines perm it mult iple brea
kpoin ts for testi ng of part ially comp leted prog rams . e.g
••
subr outin e calls for whic h the subr outin es have not yet
been
writ ten. The "loos e ends" or unwr itten code can be caug
ht by
brea kpoi nts.
11-18
The complete listing for the SWI de-bug routine is
shown below.
:+:
1.F0C
[1179
~3142
OUTMES EQU
CRLF
EQU
OB'T'TE EQU
:+:
:+:
:+:
:+: NOl·~
:+:
~325e
121253
t1256
13259
e25A
€125D
1212613
8D
CE
BD
32
BD
CE
BD
AVOIDS X.
#SOFINT
LD>!'
$FFFA
INIT Sl'~I VECTOFt
STX
,JUto1P TO TAF::CiET PROCiRAt1
~3179
ORCi
SOFINT .JSR
[12E:l
1F£1C
LD~'~
.JSF~
0142
12128C
1FeC
12126::::~
3:2
0264
0267
026A
12126D
026E
0271
0274
0277
121'0:::;,.
-' '? C''_'
0278
80 13142
~327C
SO 13142
2~3 FE
HEF.:E
1!:127F
LATE ENTRY.
PRINTOUT OF REGISTERS AFTER SOFTWARE INTERRUPT
€120e CE ~~125~3
021213 FF FFFA
12125121
$lF0C
$0179
$0142
CE ~3287
8D 1F0C
32
8D ~3142
CE 0291
BD 1F~3C
32
8[) 121142
<.-.
_.~
$~325€1
CRLF
#CCRt1ESS
OUTt1ES
PF.:INT CCF.:=
PUL A
,JSR
08'r'TE
#8t1ESS
LD>~
SSR
OUTt'1ES
PUL A
.JSR
OB'T'TE
#At1ESS
LDX
.JSR
OUTt1ES
PUL A
.JSF.:
OB'r'TE
# I :x:t'1ESS
LDX
.JSR
OUTt'1ES
PUL A
08'r'TE
.JSF.:
PUL A
OB'r'TE
.JSF~
HEF.:E
BF.:A
PF.:INT CCF.: CONTENTS
PF~INT
6',-
PF.:INT B CONTENTS
PRINT A=
PF.:INT A CONTENTS
PRINT ::.::=
PF.:INT HI B'TITE OF
:)~
PRINT LO B'r'TE OF X
:+:
13281
0286
0287
028B
028C
132913
0291
0295
4~
.::.
00
20
0121
2£1
01!:1
21!:1
~~n3
CCRt'1ES FCC
FCB
At1ESS FCC
FCB
Bt1ESS FCC
FeB
I::-::t1ESS FCC
FeB
END
ICCR=
0
I A= I
,,/
€I
,~J
,E'-
(.J
:X:=
(".,
~3
/
~3
The final printout of this could then look like.
CCR= 2F B= D3 A= F2 X= lC5S
Congratulations! You have completed the workbook.
with your programs.
Good luck
APPENDIX. A AND B
APPENDIX A
Hex Codes - 4 bits
0000
=
0
1000
=
8
0001
=
1
1001
=
9
0010
=
2
1010
=
A
0011
= J
1011
B
0100
=
4
1100
0101
=
5
1101
0110
=
6
1110
0111
=
7
1111
=
=
=
=
=
C
D
E
F
----~~-~-~-~~---------------~~~-
----~-----~---~-~~------~-~-
APPENDIX B
ASCII Code s
BIrrS 4 thru 6
0
1
2
3
4
5
0
NUL
p
!
0
1
@
SOH
STX
ETX
DLE
DCI
DC2
DC3
DC4
N.AK
SP
1
"
Q
2
#
$
3
4
5
A
B
C
SYN
&
2
BITS 0 thru 3
3
4
5.
6
7
8
9
A
B
C
D
E
F
EOT
Et\Q
ACK
BEL
BS
CAN
HT
E~1
LF
SUB
VI
ESC
FF
FS
CR
SO
51
GS
%
ETB
RS
US
(
)
6
7
V
P
q
r
c
s
d
t
u
e
f
g
h
H
I
J
K
[
<
L
=
I
j
k
I
>
M
N
]
(
m
n
?
0
8
9
*
Courtes y
E
F
S
T
U
M~t0rol a
G
7
a
b
W
X
Y
Z
+
I
D
R
6
0
v
w
x
Y
z
{
I
}
=
DEL
Sc@ico nductor Produc ts, Inc.
APPENDIX Cl
Instruction Set (2 pages)
ADORI. . ., MODIS
ACCUMULATOR AND MEMORY
OPERATIONS
Add
Add AcmltlS
Add with Carry
And
Bit Test
Clear
Compare
Co mparl Acmltrs
Complement. l's
Complement, 2's
(Negate)
Decimal Adjust. A
Oecrement
IMMED
DIRECT
INDEX
MNEMONIC
OP
-
#
0'
-
#
0'
-
ADOA
ADDS
ABA
AOCA
AOCS
ANOA
88
CB
2
2
2
2
98
3
2
AS
5
DB
3
2
EB
5
,;,&,
0'
2
2
BB
FB
ANOa
BITA
81TB
85
CS
81
Cl
2
2
2
2
2
2
3
2
A9
3
2
2
2
95
3
3
3
E9
A4
05
3
2
2
2
2
2
2
94
2
2
2
2
2
99
09
04
91
01
3
3
2
2
2
E4
AS
E5
6F
Al
E1
63
5
5
2
#
4
3
A+M-A
4
3
B+Y"&
A+B"A
A+M+C-A·
B +M + C"S
A.M-A
B· M-"8
A.M
B.M
5
2
2
5
7
2
2
F5
4
7F . 6
5
5
5
5
7
2
2
2
Bl
Fl
13
4
3
4
3
4
4
3
4
4
4
S
7
2
10
S
6A
1
2
7A
S
3
Incremena
Load Ac:mhr
0,. Inclusive
Push Data
Pull Data
Rotate Left
Rotate Right
Shih left. Arithmetic
Shift Right. Arithmetic
Shift Right, logic.
Store Atmltr.
Subtract
Subract Acmltrt.
Subtr. with Carry
Transfer Ac:mltrs
Test. Zero or Minus
4F
5F
2
2
1
11
2
1
43
2
2
1
1
88
C8
2
2
2
2
98
08
3
2
3
2
A8
E8
6C
5
5
7
2
2
2
B8
F8
7C
4
4
S
C6
SA
CA
2
2
2
2
2
2
2
2
96
06
9A
DA
3
3
3
3
2
2
2
2
AS
E6
AA
EA
5
2
5
5
5
2
2
2
86
F6
SA
FA
3
3
1
50
2
2
19
2
1
4A
SA
2
2
1
66
68
7
1
7
2
2
2
19
76
78
6
2
77
6
7
2
74
6
80
CO
2
2
2
2
82
2
C2
2
2
2
A7
3
3
92
3
2
A2
02
3
2
E2
4
E7
AD
EO
6
6
5
5
2
2
2
2
S.
5
2
2
7
2
B +1-8
49
59
2
2
1
46
56
2
1
1
1
1
,1
1
2
1
2
2
1
3
1
3
2
2
1
1
3
5
F7
5
80
FO
4
4
3
3
3
3
82
4
3
F2
4
3
6
A+'l~A
1
3
87
70
1
2
3
2
2
1
1
A+M-A
S+M-B
A-MSp, SP-l-SP
B -MSp,SP-l-SP
SP+ I-SP, MSp-A
SP + 1 -SP, MSp-B
:1 ~-:1 ~ :1
MI'
o ..C
B
:}
b7
~
B-M-B
16
11
2
2
1
A-B .... A
A-M-C-A
B-M-C-B
A-B
1
8-A
40
liD
2
1
A-DO
2
1
B -00
3
tlo
;:J
1'1"'11
b7
bo
~
..111111111"-0
b7
bo
M-OO
0
c
- -
0-1111111"
A-M~A
1
D7
bo
B-M
2
..
111111' 11:1
=} 01117"" A-M
10
60
2
31
32
33
54
2
2
2
2
4
A-l-A
8-1-a
M-B
44
97
07
90
DO
00 - B-'B
Converts Binary Add. of BCD Characten
into BCD Fo,mat
M-A
47
57
64
00 -M-M
00 -A-A
M+l-M
58
7
i-B
B$M-B
48
67
M-M
A-A
3
4
4
4
4
S
4
H
I
•
I •
l •
I •
t •
• •
• •
• •
• •
• •
• •
• •
• •
•
• •
• •
• •
• •
• •
• •
• •
~
A-B
A~M-A
3
3
3
6
-
3
4
4
6
1
COlO. COOi REG.
t
00 -M
00 -A
00 -8
A-M
3
3
to ClHltewts»
M -1-M.
36
69
1
3
4
4
rtfff
B-M
3
4C
SC
86
1
3
OECA
Exclusive OR
1
3
40
OEC
2
#
3
3
DAA
DeCa
EORA
eDRB
INC
INCA
INCB
LDAA
LOA8
DRAA
DRAB
PSHA
PSHB
PULA
PUlB
RDl
ROLA
ROLB
RDR
RORA
RORB
ASL
ASLA
ASlB
ASR
ASRA
ASRB
LSR
lSRA
LSRB
STAA
STAB
SUBA
SUBS
SeA
SBCA
S8C8
TAB
TBA
TST
TSTA
lSTa
OP
53
60
-
-
89
f9
B4
f4
SS
2
2
BOOLEAN/ARITHMETIC OPERATIOft
(AII'..ist. . . . .
INHER
1B
89
C9
84
C4
CLA
ClRA
CLRB
CMPA
CMPB
CBA
COM
COMA
COMB
NEG
NEGA
NEGB
EXTND
bo
0
c
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
.
•
•
•
•
•
•
•
•
•
•
•
•
3
2
I
0
"t
Z
v
C
t
~
t
t
t
:
S
t t t
I t t ~
~
J
J
:
R
J R
•
•
•
•
~
+ t
t
t t
t t
R
t t
t
R
R 5 R R
R S R R
R ~ If R
t f t :
t
t : t
~
t
I
I
t R S
t R S
t R S
t
t Zero
Branch I f Higher
+
DE
9E
I
.OPERATIONS
Clear Carry
Clear Interrupt Mask
Clear Overflow
Set Carry
Set Interrupt Mask
Set Overffow
Acm~tr A-CCR
CCR -Acmltr A
INOEX
:F
09
JUMP AND BRANCH
,.OPE~ATIO~S
DIRECT
11
5
4
3
2
1
0
H
I
N
Z
V
C
Advances Prog. Cntr. Only
5 4
3
H I
N Z V C
2 1
I
• • (!)l @.
• • • t • •
• • • •• •
• • • ~ • •
• •• •• •
• • @t R •
• • @~ R •
• • @S R •
• • @t R •
• • • •• •
• • • • •
-
5
4
3
H
I
N Z V C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2 1
0
- •• •• •• ••
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• •
• • •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
-
•
•
•
•
-
•
•
•
•
--@--
} See special Operation.
-I-fl-I-r
•
S ••••
• @ ••••
CONDITION CODE REGIST£R NOTES:
(Bit set if test's true .nd cleared otherwise)
R CD (Bit V) Test: Result.= 100000001
@ (Bit C) Test: Result: 000000001
R
@ (Bit C) Test: Decimal value of mOlt significant BCD Character gr~.ter than nine?
R
INot cleared if previously set.)
S
@ (Sit V) Test: Operand = 10000000 prior to execution?
S
® IBitV) Test: Opennd: 01111111 prior to execution?
S
- - - @ - - ® (Bit V) Test: Set equal to rewlt of N $ Caft" shitt has occurred.
0~ (Bit N) Test: Sign bit of ",ost significant (MS) byte of result :II 1?
8
Bit
V Test: 's com plement overflow from sub traction f lS bytes?
@
()
® (Bat N) Test: Resun less than zero? (Bit 15 - 1)
@ (AU) load Condition Code Register from Stack. (Se. Special Oplfations)
(Bit I) Set when int!mJpt occun. If previously Sit, a Non-Maskabl, Interrupt is
required to exit the wait state:
• • • • •
•
• • • •
• • • •
•
• • • •
-• • • • --• - •
-1·1-1·1-1·
Half-carry from bit 3;
Interrupt mask
Negative lsign bit)
N
Zero (byte)
Z
V
Overflow. 2's complement
Carry from bit 1
C
Reset Always
R
Set Always S
Test and 'itt if true. cleared otherwise
~
Not Affected
CCR Condition Cod. Register
Least Significant
lS
MS Most Significant
o
o
(ALL) Set accordif'g to the contents of Accumulator A.
•
Courtesy Motorola Semiconductor Products. Inc.
APPENDIX D
Machine Code
00
01
02
03
04
05
06
*
07
08
TPA
INX
40
41
42
43
44
45
46
47
48
09
DEX
OA
08
CLV
SEV
CLC
SEC
CU
SEI
49
oc
OD
OE
OF
10
11
12
13
14
15
16
NOP
•
•
•
•
TAP
•
•
•
•
18
19
lA
*
IB
IC
ID
ABA
IF
20
21
*
•
•
BRA REL
•
25
BCS
26
2A
BNE
BEQ
BVC
BVS
BPL
2B
2C
BGE
28
29
20
2E
2F
30
31
32
33
34
35
B~fi
REL
REL
REL
REL
REL
REL
REt
REL
LSR
5F
60
NEG B
•
•
•
CLR
NEG L'iD
•
ROR l'l>
ASR L~D
ASL 1."0
ROL IXD
6A
DEC L':D
68
6C
INC
*
3C
•
7A
78
7C
3D
3E
*
7D
WAI
SWI
7E
3F
7F
l~fM
ADC A
I~I~1
8A
ORA
A
l!\-IM
C9
C.t\
ADC
ORA
IM~I
88
8e
80
8E
8F
90
91
ADD A
CPX A
B
B
ADD B
I~'f
LOX
IMM
C3
BSR
LDS
•
SUB A
CMP
A
92
93
94
SBC A
95
BIT A
LDA A
STA A
EOR A
•
Al~D
A
9F
DE
DF
AO
DIR
DIR
SUB A
Al
CMP A
IND
IND
IND
A3
A4
AS
A6
A7
AS
•
sac A
•
AND A
BIT A
LOA A
STA A
EOR A
I~D
AE
AF
LOS
STS
SUB A
C~fP A
sac A
LSR EXT
•
BO
Bl
B2
B3
B4
85
ROR
EXT
B6
ASR
ASL
EXT
EXT
B7
88
ROL
DEC
E.XT
B9
•
INC
TST
EXT
DIR
LDS
STS
9:\
98
CLR I~D
NEG EXT
.:.~
DIR
CF
00
01
D2
03
D4
D5
D6
D7
D8
D9
JSR
Cb.~f EXT
DIR
DIR
CD
CE
DIR
DIR
DIR
DIR
DIR
AD
•
DIR
DIR
DIR
CD
CC
ADC A
ORA A
ADD A
CPX
99
I~D
J~1P
I~t~l
I!\1M
REL
IM~t
L"D
•
·
*
EOR B
89
•
ORA A
ADD A
71
RTI
C7
C8
C~fP
A9
AA
AB
AC
70
78
IM!\.t
A2
INS
Notes: 1. Addressing ~Iodes;
B
67
68
69
79
EOR A
•
L\1M
90
9E
TST
•
C6
88
88
..
I~f~f
B
•
66
RTS
LOA A
BIT B
LDA B
l~fM
8S
86
AND A
BIT A
TST
4:
39
I~t~{
CS
C2
9C
65
A
B
1~IM
I~tM
B
LSR L'-;O
8
A~D
Cl
INC
COM ISO
PSH
C4
1t\1~1
I~t~f
97
98
64
73
74
75
76
77
IMM
It-1M
A
A
SSC A
96
61
62
63
72
Sl~B
II
CMP 8
S8C B
SUB
81
82
883
84
ASR B
ASL B
ROL B
DEC B
*
6D
6E
6F
DES
B
co
80
ROR, B
BLT REL
BGT REL
BLE REL
TSX
PUL c.A
PUL B
A
54
36
37
38
38
CLR
COM B
TXS
PSH
3A
•
A
A
50
52
52
53
SE
23
24
27
TST
5A
BID REL
BLS REL
Bce REL
22
4D
58
5C
50
•
A
ROR ....
ASR A
ASL A
ROL A.
DEC A
L~C
59
*
•
•
58
DAA
LSR
48
55
56
57
TAB
TBA
A
COM A
4C
4E
4F
SBA
CBA
17
IE
4A
~EG
•
•
BA
BB
ADC A
CPX
INO
INO
IND
IND
IND
IND
IND
IND
IND
IND
IND
AND B
BIT B
LOA B
STA B
EOR B
ADC B
ORA B
ADD B
•
•
LDX
AND B
a
IND
BIT
I~JD
LDA B
STA B
I~'D
E7
E8
E9
EA
EB
EC
ED
EE
EF
B
IND
IND
ADC B
ORA B
ADD B
IND
IND
EOR
•
•
F2
F4
F5
F6
F7
F8
sac a
•
AND B
BIT B
LDA B
STA B
ADe
B
ORA
Fll
J~1P
EXT
BE
BF
STS
Fe
B
ADD B
•
•
EXT
FD
FE
LDX
EXT
FF
STX
Immediate
Direct
Extended
DIR
DIR
ES
E6
•
FA
CLR
DIR
IND
IND
EXT
EXT
EXT
DIR
DIR
DIR
DIR
DIR
DIR
OIR
IND
EXT
CPX
JSR
DIR
DIR
DIR
Clw1P B
sac B
ADC B
BC
I,.tM
El
E2
E3
E4
EO
F9
BD
EXT
B
CMP B
EXT
DIR
•
FO
EXT
EXT
EXT
EXT
EXT
EXT
l~tM
sac
B
FI
AND A
BIT A
LDA A
STA A
lns
C~·fP
I!\tM
STX
SllB B
F3
A
SUB B
EXT
EXT
ADC A
ORA A
ADD A
•
EXT
EXT
EXT
A = Ac:cumul,uor A
B = Accumulator B
2. Unassigned code indicated by"."
DD
•
•
LOX
STX
SUB B
IND
..
EOR
DA
DB
DC
•
I~l~f
REL
IND
IND
~O
L"D
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
Relative
Indexed
Hexadecimal Values of Machine Codel
Courtesy Motorola Semiconductor Products. Inc.
APPENDIX El
- ACIA Asynchronous Communications
Interface Adapter
DEF'INITION OF ACIA REGISTER CON·TENTS
Buffer Address
D~ta
Bus
Line
Numb~r
Transmit
Data
Register
Receive
Data
Regist..
Control
Register
Status
Register
(Write Only)
(Read Only')
(Write Only)
(Read Only)
0
Data Bit O·
Qata Bit 0
Counter Divide
Select 1 (CRO)
Receive Data Register
Fuil (RORF)
;
, Data Bit 1
Dat8 Bit 1
Counter 0 ivide
Select 2 (CR 1)
2,
Data Bit 2
Data Bit 2
Word Select 1
(-CA2)
Data Carr ier Detect
3
Data' Bit 3
Data Bit 3
Word Select 2
(CR3)
Clear-to·Send
(CTS)
4
Data Bit 4
Data Bit 4
Word Select 3
(CR4)
Framing Error
(FE)
5
Data Bit 5
Data Bit 5
Transmit, Control 1
(CRS)
Receiver Overrun
(OVRN)
6
Data Bit 6
Data Bit 6
Transmit Control 2
(CA6)
Parity. Error (PE)
7
Data Bit 7···
Data Bit 7··
Receive Interrupt
Enable (CR7)
I nterrupt Request
(IRQ)
,. Leading bit ~ LSB '-= Bit 0
•• Data bit will be zero in 7·bit plus parity modes.
• •• Data bit is "don't care" in' 7-bit plus parity modes.
Transmi~ .Data
Register
Empty (TORE)
(~CD)
---'
ACtA Control Register Format
Counter ratio and Master reset select used
in both transmitters and receiver sections
Enable tor Receiver In terrupt
b7
c: \ :
b7 =
O~
Int errupt Output in
Receiving Mode
Enable~
Disables Interrupt Output In
Receiving M ode
Function (Tx, Rx)
b1
bO
0
0
+1
0
1
+16
1
0
+64
1
1
MASTER RESET
I
l
b7
b6
b5
b4
b3
b2
bl
bO
RIE
TC2
TC1
\~S3
'y'''S2
WSl
CDS2
CDSl
J
I
Word Length, Parity, and Stop Bit Select
b4 b3 b2 Word Length
Transmitter Control Bits: Controls the Interrupt Output· and RTS
Output, and providei for Transmission of a Break
Fu nction
+ Parity + Stop
0
7
Even
2
0
1
7
Odd
2
1
0
7
Even
1
0
1
1
7
Odd
1
0
8
None
2
1
0
0
0
0
b6
b5
o
o
o
Sets RTS = 0 and inh ibits Tx interrupt (TI E)
1
Sets RTS = 0 and en abies Tx interrupt (T' E)
1
o
Sets RTS = 1 and inh ibits Tx interrupt (TIE)
1
0
1
1
Sets RTS = 0, Transm its Sreal< and inhibits Tx
interrupt (T IE)
1
0
1
8
None
1
1
0
8
Even
1
1
1
1
8
Odd
1
-Tie is the enable for the interrup t output in transmit mode.
I
Bits
APPENDIX E2
- ACIA Asynchronous Communications
Interface Adapter
~;~~arri;:~:~:::
carrip.r is
b2
= 1:
presc~
t.
-
ACI A Status Register Format
--l
Indicates the: I()$'; of carrier.
1. The low-to·high transition of the OeD input C~\Jscs b2= 1 and g'::nera\es an interrupt
(b7=1), (IRQ=O)
2. Reading the Status Registe, ~r.d Rx Data
Register or master res~ttlng the AC~A
causes b2=O and b 7~O .
...-._---
Receiver Data Register Full
Indicates that the Receiver Data
Register is ernpty.
Indicates that data has been transferred to the Receiver Data Register
and status bits states are set (PE,
bO == 0:
,---!
bO = 1:
Interrupt Request
OVRN, FE).
1. The Read Data Command on the high-tolow E transition or a master reset causes
bO = O.
2. A "high" 011 the OCD input causes bO-=O
and the receiver to be reset.
1
The interrupt request bit is the complement of
I the i AQ Ol.'tput. Any in1errl.pt that is set and
, enabled '.vill bE:. available in th~ status register
{ in addition to the norrnal I RQ output.
L_---
I
I
b7
b6
IRQ
PE
I
T
b5
b4
OVRN
FE
I
1
I
T
b3
1
CTS
I I
b2
OeD
I
bl
TxDAE
I
bO
RxDRF
I
I
Framing Error
Indicates the absence of the first stop
bit resulting from character synchro·
nization error, faulty transmission, or
a Break condition.
1. The internal Rx data transfer signal causes
b4=1 due to the above conditions and causes
b4=O on the next Rx data transfer signal if
conditions ha'ie been rectified.
I
b4 = 1:
'--
Transmitter Data Register Empty
b1
1.
2.
Overrun Error
Indicates that a character or a number of characters V\'ere received but
not read from the R x data register
prier to subsequent characters being
received.
1. The Read Data Command on the high-to10V\' E transition causes b5=1 and bO=1 if an
overrun condition exists. The next Read
Data Command on the high-to-Iow E transition causes b5=O and bO=O.
b5 = 1:
~
l
Parity Error
Indicates that a parity error exists.
The parity error bit is inhibited if no
parity is selected.
1. The parity error status is updated during
the Interna! receiver data trans1er signal.
b6 = 1:
'ndicates that tha transmitter data
Register is empty.
:: 0:
Indicates t~at the transmitter data
Register is full.
The internal Tx transfer signal forces b1==1.
The Write Data Command on the high·tolow E transition causes b1 =0.
A Uhigh" on the CTS input causes b1=O.
b1 = 1:
3.
Clear to Send
The CTS bit reflects the CTS input status for
use by the MPU for interfacing to a modem.
NOTE: The CTS input does not reset the
transmitter.
Courtesy Motorola Semiconductor Products, Inc.
APPENDIX Fl
- PIA Peripheral Interface Adapter
DATA DIRECTION REGISTER
Accessed via Data Buffer address when bit #2 of the Control
Register is o•.
1 = output)
.
o = J.nput
J~ for each of the 8 data lines on the Data Buffer.
-------CONTROL REGISTER
CAl (CB'l)
(input o~ly)
7
5
6
4
3
2
~
O=DDR access
,READY BIT
(read only)
via Data Buff
l=Data Buffer
access
bit #5
INPurr mOde.,....__·O_=.......i_n....
Plllllllu_t_..-.",A..
6
5
4
J
2
1
~~llt~)~~JrgA
t
1~~2) J
READY
BIT
I
l
0 for no interrupt
(0 = CAl (CB1) ACTIVE in
L(
goin@; LOW'
(1 = CAl (CB1) ACTIVE in
(going, HIGH .
I
CA2 (CB2)
7
0
~~ft9?1
~
I
CA1(CB 1)
1
t
CA2 (CB2) ACTIVE
goin~ LOW
CA2 (CB2) ACTIVE
going HIGH
= outPu~
bit #4
0
=1,....J..
=0
1
PROGRAMMED mO-d-e----.......
~
0 1 0 for no
t
interrupt
+
1
CA2 (CB2)
f.ollows bi t /13
l=
bit #)
=0
1
_
f
mode
CA2 (CB2) goes HIGH
(
)
following CAl CBl ·
CA2 goes LOW after
READ from A Buffer.
CB2 goes LOW after
WRITE to B Buffer.
HANDSHAKE
STROBE mode
goes LOW'
momentarily after
READ from A Buffer.
CB2 goes LOW
'momentarily after
WRITE to B Buffer.
CA2
APIENDIX F2
PIA Peripheral Interface Adapter
01 :.: 0 : I AQA(9, 1 se~ by high-to-tow transi'tion on
CAt (CB1).
bl·c, 1 : 1RCA(S" se! by low-to·high tr:tns;tion on
CAl (CB1).
'-------
1____
.
r
I
~A1 (Cal) Inter~JPt
lI
IRQA(B) 1 Interrupt Flag (bit b7)
bO = 1 : Enable I AQA{B} MPU Interrupt by CA 1 (CB 1)
a~:tive tran~i'dor,.
'=1_
---=t-
'---.
,
IRQA{B)l
b6
_~J
b5
b3
f_'a_g_._~
p
I
CA2(CB2)
IRCA(B)2
Flag
t--_b__l----.i_b_6--f
DDR
--Jt=
.--.---__,J~_~
CA2 (C82) Estobl!shed as Input (bS = O}- Goes high on active
transition of CA2 (CB2); Automa~icaJl" clcared by MPU Read
of Output Register A(B). May also be cieared by hardware
Detcuoines VJhether Data Direction Register Or
Re~~i is Addressed
Reset.
b2
CA2 (CB2) Established as OutPut (bS = 1): ~ RQA(B)2 ::: O.
not affected by CA2 (C82) trans,tior,s.
b4
b3
o
T
[hDt
operat~on ~" f
u
_
_
.,
Re~S trobe \N~t~CA ~.:.!~
,CA2 goes 10.... on first high-to..
low E transition follO'Ning an
f\,1PU Read of Output Register
A; returnee high by next
ac tive CA 1 transi tion.
CB~
'IJrite
Stro~e
With Cal Restore
CS2 goes on low on 1irst !OVJt~ hi~ E ~rai\sitio., foiiowing
an MPU \A.'n~e into Output
Reg:stcar B; n:~urned high by
th~ ne;
b3
I
C.A.2 (C82~ Intarrupt A9Guest Enablel
'O;sable
b3 = 0:
b3 = 1:
Reed Strobe wi ttl E Restore
CA"2 gees IO~"1 on first hi9h·t~
low E vansiticn following an
MPU Read of Output Register
A; returned high by next
high-to-Iow E tr"nsition.
b3 = 1:
R~gister seJe~teCS.
Disables IAQA(B) MFU
Interrupt by CA2 (CB2)
active transit.;on. 1
Enables I RQA{B) MPU
Interrupt by CA2 {C82)
= 1:
b3 = 0:
0 : Data Direction
b2 :.: 1 : Outpu t Register seiected.
CA2
b3
::II
au tput
"'------------_._-------------'
CA2 :;.nd Co
.. 2
(Note t
output fonct;ons are not identic-31)
b3 = 0 :
C_o_n_t_r_o_1__
- .Io._ _
I RQA(B)2 Interrupt Flag (bit b6)
CA2 (~B21 Establislled as Output by 1,5 ~ 1
CA1(CS1)
C_'~~~~..-L~._c_c_e_s_s
__~_=r__..
b5
DisdbJa:i I RCAtB) r~1PU Interrupt by CAl (Cal)
active transition.'
transit:~n of bO if CA 1 (CB1) active transition occurred
, V ' . ' h i l e interrupt was rjisabled.
cleared by "',PU Read of Output Regtsti!r A(B). May also be
cleared by hardware Reset.
b7
= 0:
bO
REtQuest Enable/Disable
'tiri ... ~
Str'.j~e
'Nith E Restore
CB2 goe$ 10\'1 0" fi,.st Ivw-tohigh E transition following an
MPU \"Jt;te ;nto Output
Rc~;5ter B; returned hi~h by the
next io~·,.to-high E transition.
S'?t/Res~t
active tran~ition.
I
IL -...
1. I ROA,B) w:ii occur ~n next (M?U
getlerat~d) p~itive trc:.i'\!ai~~on of b3
if CA2 (CB2) -Jo..v
transition on C,o\2 {CB2).
b4 = 1:
I R OA( 8)2 set by ! o't/-to-high
transition on CA2 fCB2).
---------
CA2 (C32)
CA2 (C62) ~C~~ lew as ~'PU vvriteos
b3 := 0 in to C,=,ntrof Aegi~ter.
CA2 (CB2i 9(.":\ high
a~ ~'PU writes
b3 = 1 into Control Register.
Courtesy Motorola Semiconductor Products
APPENDIX G & H
APPENDIX G
CHAR ACTE R SET
The characters used in the source language for the Motorola assembler form
a
sub-set of ASCII (American Standard Code for Information Interchange,
1968).
The ASCII Code is shown-in App B •. The follo\ving characters are recogn
ized
by the assembler:
I. The alphabet A through Z
2. The integers 0 through 9
3. Four arithmetic operators:
+ - * ,.
4.
5.
6.
Characters used as special prefixes:
# (pounds sign) specifies the immediate mode of addressing
$
(dollar sign) specifies a hexadecimal number
@ (commercial at) specifies an octal number
% (percent) specifies a binary number
(apostrophe) specifies an ASCII liter-dl character
Characters used as special suffices:
B (letter B) specifies a binary number
H (letter H) specifies a hexadecimal number
o (letter 0) specifies an octal number
Q (letter Q) specifies a octal number
Four separating characters:
SPACE
Horizontal TAB
CR (carriage return)
, (comma)
The use of horizontal TAB is always optional, and can be replaced by
SPACE.
Courtos y Motoro la
Se~icon ductor
Produc ts, Inc.
APPENDIX H
Commonly Used Instr uctio ns
As a quick refer ence
guide some of the more commonly
used instr uctio ns, along
with thei r mach ine codes~
are shown here .
:+:
86 4[:
Le'A A
#$4[:
STA A
$1.2F 3
LDA A
$:12F 3
LDX
$1.2A 7
:+:
E:7 1.2F3
:+:
86 1.2F3
:+:
FE :12A7
:+:
08
I
t·~>(
:+:
FF 1.2A7
·ST>::
$12A 7
STA A
>(
STA A
$:1.2 [:a 5
L[:aA A
X
:+:
A7 00
:+:
87 1.2[)5
:+:
A6 00
MICROPROCESSOR GLOSSARY
ACCUMULATOR: 1"he register where arithmetic or
logic re~ults are held. Most MPU instructions
manipulate or test the accumulator contents.
ACCESS TIME: time take for specific byte of storage
to become available to processor.
ACIA: ; Asynchronous Communication Inter-face
Adapter. Inter-face between asynchronous peripheral and an M PU.
ALU: Arithmetic and logic Unit. The part of the MPU
where arithmetic and logic functions are
~~m~.
.
ASCII: American Standard Code for Information
Interchange. Binary code to represent alphanumeric, special and control characters.
ASSEMBLER: Software which converts assembly
language statements into machine code and
checks for non valid statements or incompl~te
definitions.
ASSEMBLY LANG: Means of representing programme statements in mnemonics and conveniently handling memory addressing by use of
symbolic terms.
ASYNCHRONOUS: Operations that initiate.a new
operation immediately upon completion of current
one - not timed by system clock.
BASIC: iBeginner's All Purpose Symolic Instruction
Code. An easy to learn, widely used high level
language.
BAUD: Measure of speed of transmission line~
Number of times a line changes state per second.
Equal to bits per second if each ,line state
rep(esents logic 0 or 1.
BAUDOT CODE: 5-bit code used. to encode
alphanumeric data.
BCD: Binary Coded Decimal. Means of representing
decimal numbers where each figure is replaced by
a binary equivalent.
BENCHMARK: A common task. for the
implementation of which programmes can be
written for different MPUs in order to determine
the efficiency of the different M PUs in the
particular application.
BINARY: The two base number system. The digits are
o or 1. They are used inside a computer to
represent the two states of an electric circuit.
BIT: A single binary digit.
BREAKPOINT: Program address at which execution
will be halted to allow debugging or data entry.
BUFFER: Circuit to provide isolation between
sensitive parts of a system and the rest of that
system.
j
BUG: A program error that causes the program to
malfunction.
BUS: 'The interconnections in a system that carry
parallel binary data. Several bus users are
connected to the bus, but generally only one
"sender" and one "receiver" are active at anyone
instant.
BYTE: A group of bits - the most common byte size
is eight bits.
CLOCK: The basic timing for a MPU chip.
COMPILER: Software which converts' high level
language statements into either assembly
language statements, or into machine code.
CPU: Central processor unit. The part of a system
which performs calc,..lation and data manipulation
'functions.
CROM: Control Read Only Memory.
CRT: Cathode Ray Tube. Often taken to mean
complete output device.
CUTS: Computer Users Tape System. Definition of
system for storing data on cassette tape as series of
tones to represent binary l's and O·s.
DEBUG: The process of checking and correcting any
program errors either in writing or in actual
function.
DIRECT ADDRESSING: An addressing mode where
the address of the operand is contained in the
instruction. (Ad4rcss below 100 in 6800)
DMA: Direct Memory Access.
DUPLEX: Transfer of data in two di(ections
simultaneously.
ENVIRONMENT: The conditions of all registers,
flags, etc., at any instant in program.
EPROM: Electrically Programmable Read Only
Memory. Memory that may be erased (usually by
ultra violet light) and reprogrammed electrically.
EXECUTE: To perform a sequence of program steps.
EXECUTION TI M E: 'The time taken to perform an
. instruction in terms of clock cycles.
FIRMWARE: Instructions or data permanently ~tored
in ROM.
FLAG: A flip flop that may be set or reset ·under
software control.
FLIP-FLOP: two state device that changes state when
clocked.
FLOPPY (DISK): Mass storage which makes use of
flexible disks made of a material similar to
magnetic tape.
FLOW CHART: A diagram representing the logic of a
computer program.
GLITCH: Noise pulse.
HALF DUPLEX: Data transfer in two directions but
only one way at a time.
HAND SHAKE: System of data transfer between CPU
and peripheral whereby CPU "asks" peripheral if!t
will accept data and hnly transfers data If
'·answer'··is yes.
HARD COPY: System output that is printed on paper.
_HARDWARE: All the electronic and mechanical
components making up a system.
HARD WIRE: Circuits that are comprised of logic
gates wired together, the wiring pattern
. determining the overall logic ·operation.
HASH: Nois.y signal.
HEXADECIMAL: The base 16 number system.
Character set is decimal 0 to 9 and letters A to F.
HIGH LEVEL LANGUAGE: Computer language that is
easy to use, but which requires compiling into
. machine code before it can be used by an M PU.
HIGHWAY: As BUS.
IMMEDIATE ADDRESSING: Addressing mode which
uses part of the instruction itself as the operand
data.
INDEXED ADDRESSING: A form of indirect
addressing which uses an Index Registe.r to hold
the address of the operand.
INDIRECT ADDRESSING: Addressing mode where
the address of the location where the address of
the operand may be found is contained in the
instruction.
INITIALISE: Set up all registers, flag, etc., to defined
conditions.
INSTRUCTION: Bit pattern whith must be supplied
to an MPU to cause it to perform a particular
function.
INSTRUCTION REGISTER: MPU. register which is
used to hold instructions fetched from memory.
INSTRUCTION SET: 'The repertoire of instructions
that a given MPU can perform.
INTERFACE: Circuit which·connects different parts of
system together and performs any processing of
signals in order to make transfer possible (ie,
serial - parallel conversion).
INTERPRETER: An intArpreter is a software routine
which accepts and executes a high level language
program, but unlike a compiler does not produce
intermediate machine code listing but converts
each instruction as received.
INTERRUPT: A signal to the MPU which will cause it
to change from its present task to another.
I/O: Input/Output.
K: Abbreviation for 2 10 = 1024
KANSAS CITY (Format): D~finition of a CUTS based
cassette interface system.
LANGUAGE: 'A systemmatic means of communicating with an MPU.
LATCH: 'Retains previous input state until overwritten.
LIFO: last In First Out. Used to describe data stack.
LOOPING: Program technique where one section of
program (the loop) is performed many times over.
MACHINE LANG: The lowest level of program. T-he
only language an MPU can understand without
interpreter.
.
MASK: Bit pattern used in conjunction with a ·Iogic
operation to select a particular bit or bits from
machine word.
MEMORY: The part of a system which stores data
(working data or instruction object code).
MEMORY MAP: Chart showing the memory
allocation of a system.
MEMORY MAPPED I/O: A technique of implementing I/O facilities by addressing I/O ports as if they
were memory locations.
.
MICRO CYCLE: Single program step in an MPUs
Micro program. The smallest level of machine
pro~ram step.
MICRO PROCESSOR: A CPU implemented by use of
large scale integrated c~rcuits. Frequently
implemented on a single chip.
MICRO PROGRAM: Program inside MPU which
controls the M PU chip during its basic
fetch / execute sequence. _
MNEMONIC: A word or phrase which stands for
another (longer) phrase and is easier to remember.
MODEM: Modulator / demodulator used to send and
receive serial data over an audio link.
NON VOLATIVE: ;Memory which will retain data
content after power supply is removed, e.g. ROM.
OBJECT CODE: To- bit patterns that are presented to
the M PU as instructions and data.
O/C: Open Collector. Means of tieing together O/P's
from different devices on the same bus.
OCTAL: Base 8 number system. Character
decimal 0-8.
OP CODE: Operation Code. A bit pattern which
specifies' a machine operation in the CPU.
OPERAND: Data used by machine operations.
PARALLEL: Transfer of two or more bits at the same
time.
PARITY: Check bit added to data, can be odd or even
parity. In odd parity sum of data 1's + parity bit is
odd.
PERIPHERAL: Equipment for inputing to or
outputting from the system (e.g., teletype, VDU,
etc.).
PIA: Peripheral Interface Adapter.
POP: Operation of removing data word from LIFO
stack.
PORT: A terminal which _the MPU uses to
communicate with the outside world.
PROGRAMS: Set of MPU instructions which instruct
the MPU to carry out a particular task.
PROGRAM COUNTER: Register which holds the
address of next instruction (or data word) of the
program being executed.
PROM: Programmable read only memory. Proms are.
special form of ROM. which can be individually
programmed by user.
.
PUSH: Operation of putting data to LIFO stack.
RAM: Random Access Memory. Read write memory.
Data may be written to or read from' any location in
this type of memory.
REGISTER: 'General purpose MPU storage location
that will hold one M PU word.
RELATIVE ADDRESSING: Mode of addressing
whereby address of operand .is formed by
combining current program count with a
displacement value which is part of the instruction.
ROM: Read Only Memory. Memory device which has
its data content established as part o{ manufacture
and cannot be changed.
.
SCRATCH PAD: Memory that has short access time
and is used by system for short t~rm data storage.
SERIAL: Transfer of data one bit at a time.
SIMPLEX: Data transmission in one direction only.
SOFTWARE: Programs stored on any media.
SOURCE CODE: The list of statements that make up a
program.'
STACK: A last in first out store made up of registers
or memory locations used for stack.
STATUS REGISTER: Register that is used to store the
condition of the atcumulator after an instruction
has been performed (e.g., Acc = 0).
SUB ROUTINE: A sequence of instructions which
perform an often required function, which can be
called from any point in the main program.
SYNTAX: The grammar of a programming language.
TRAP (Vector): Pre-defined location in memory which
the processor will read jiS a result of particular
condition or operation.
TRI STATE: Description of logic devices whose
outputs may be disabled by placing them in a high
impedance state.
TTY: Teletype.
TWO'S COMPLEMENT ARITHMETIC: System of
performing signed arithmetic with binary numbers.
UART: 'Universal Asynchronous Receiver Transmitter.
VDU: Video Display Unit.
VECTOR: Memory address, provided to the processor
to direct it to a new area in memory.
VOLATILE: Memory devices that will lose data
content if power supply removed (Le., RAM).
WORD: Parallel collection of binary digits much as
byte.
Reprinted from the September 1917 edition of Electronics Today International magazine. Toronto. Ontario_
APPENDIX Jl
Asse mble r Erro r Codes
281
NA" DIRECT lYE ERROR
"ESSACE:
** •• ERROR 2e1 AAAAAA
REAMING:
THE H~M DIREC1IVE IS NOT THE FIRST SOURCE STATEMENTJ
11
IS I1ISSIH C ..
OR IT OCCURS )l!ORE TH~N ONCE IN THE
SA"E SOURCE PROCRA".
282
LABEL OR OPCODE ERROR
"ESSAGE:
•••• ERROR 292 AAAAAA
"EAMING: THE ~ABEL OR OPCODE SY"BOl DOES HOT BEGIN
WITH AH
ALPHABETIC CHARACTER.
283
STATEMENT ERROR
"ESSACE:
****ERROR 2e3 AAAAAA
"EAMINe:
THE STATE"EKT IS BLANK OR ONLY COHTAIHS A LABEL.
284
SYHT4X ERROR
"ESS~CE:
•••• ERROR 294 AAAAAA
KEAHIHG:
THE STATEKEHT IS SYNTACTICALLY INCORRECT.
295
L~BEl ERROR
"ESS~CE:
•••• ERKOR
"EAHIHG:
286
REDE~IHED
"ESSAGE:
"EAHIHC~
29S AAAAAA
THE STATEMENT LABEL FIELD IS HOT iER"IHATED
WITH A SPACE.
SV"BOl
•••• ERROR 286 AAAAAA
THE SVM9QL HAS PREVIO USLY BEEN DEFIN ED.
VALUE IS SAYED IN SY"BOL TABLE.
297
THE FIRST
UHDEFINED OPCODE
•••• £RROR 291 AAAAAA
"EAHIHC: THE SY"B~l IH THE OPCODE FIELD IS NOT A VAllO
OPCODE "HE"OMIC OR DIRECTIVE.
"ESS~CE:
)8~
BRANCH ERROR
··P1ESSAGE:
"EAHIHG:
•••• ERROR 298 AAAAAA
THE BRANCH COUNT IS BEYOND THE RELATIYE 8YTE·S
RAHGE.
THE ALLOWABLE RANCE IS:
<*+2> - 128 < D < <*+2) + "127
WHERE: • = ~DDRESS OF THE FIRST BYTE OF
THE
D •
BRANCH INSTRUCTION
OF THE DESTINATION OF THE
BRANCH INSTRUCTION.
~DDRESS
~
289
"'ILLEC AL ADDRESS "ODE
~iSSACE:
"EAHIHG:
••• *ERROR 289 AAAAAA
THE "ODE OF AD~RESSIHC IS HOT ALLOWED WITH THE
CODE TYPE.
218
op-
BYTE OVERFLOW
•••• ERROR 219 AAAAAA
AN EXPRESSION COHVERTED TO A YALUE ~REATER THAN
255
Zero
BGT
2E
4
2
BHI
22
4
C + Z ::
BlE
2F
4
2
2
BlS
23
4
2
C + Z:: 1
BLT
20
4
N'E-V:: 1
Branch If MInus
8MI
2B
4
2
2
Branch If Not Equal Zero
BNE
26
4
2
Z=O
Branch If Overflow Clear
BVC
28
4
2
v=o
B, anch II Overflow Set
BVS
29
4
2
V:: 1
Branch If Plus
BPL
2A
4
2
N=O
BSR
80
8
2
Branch If HIgher - "I\Sl!1\ del
Blanch If ~ Zero
Branch If Lower Or Same
Branch If
< Zero
Branch T0
-u""9"e'
Subroulln~
2
Z + (N.; V):: 0
N:: 1
Jump
JMP
6E
4
2
1E
3
3
Jump To Subrouhnt!
No Operation
JSR
NOP
AD
8
2
BD
9
3
01
2
1
Return From Interrupt
RTI
3B
10
1
Return From Subroutine
RTS
39
1
Sohware Interrupt
SWI
3F
5
12
Wait for Interrupt
WAI
3E
9
t
CONDITIONS CODE REGISTER
INHER
MNEMONIC
OP
-
=
Clear Caery
ClC
OC
2
1
O-C
OPERATIONS
Clear Interrupt Mask
CLI
OE
2
1
0-1
Clear Overflow
CLV
OA
2
1
O-V
Set Carry
SEe
00
2
1
l-e
1-1
Set Interrupt Mask
SEI
OF
2
1
Set Overflow
SEV
OB
2
I
1-V
Acmlt( A - CCR
TAP
06
1
A -CCR
CCR -Acmltr A
TPA
07
2
2
1
CCR -A
5
4
3
2
1
a
H
I
N
Z
V
C
} See SpeCIal Operauons
Advances
Pro~.
Cntt. Only
(Bit set ,f test
IS
-I-fl-rlS
•
•
•
•
tBlt NI. Test: Sign bil of most Significant (MS) byte of result:: P
lBlt V) Test: 2's complement overflow from subtraction of LS bytes?
--@--
®
=00000000'1
(Bit V) Test: Operand:: 10000000 ;lrior to oecutlon?
(BIt VI Test: Operand = 011 till t prior to execution?
(BIt V) Test: Set equal to result of N.; Cafter shIft has occurred.
(Bit
NumbEr of MPU Cycles;
I
Interrupt mask
Number of Program Bytes;
N
NegatIve (sign bitl
Anthmetlc Plus;
Z
Zero (byte)
Arithmetic Minus;
V
Overflow, 2·s complement
Boolean AND;
C
R
Carry from bit 7
S
Set Always
Test and set if true. cleared otherwise
eCR
·· ••
· · ·•
··
- ··
•
·
•
· ·· •
•
· · · · · ••
· · ·· ·•
·.
· ·-I-. ··· ··•
• • • •
• • • •
• • •
• • • • •
• • •
• • • •
• • • •
• • •
• • • •
• • • •
•
•
• • • •
•
•
• •
• •
•
• • • •
CD
-1·1·1-1·1· ®
·
(Bit C) Test: Result
([9
Complement of M;
-• •• •• •• ·• ··
(Bit CI Test: Oeclmal value of most sigl\lficant BCD Character greater than nrne'
(Not cleared .f prevIously set.)
Half·carry from bit 3;
M
0
C
true and cleared otherwlsei
H
t
1
Z V
(Bit V) Test: Result = 10000000'1
Operation Code IHexadecimal);
•
2
N
• • • • • R o
• R • • • • @
• • R • @
•
• • • • • S
• S • • • • o
• • • • S • ®
(Bit N) Test: Result less than zero? (BII 15 = 1)
Boolean InclUSIve OR;
3
I
CONDITION CODE REGISTER NOTES:
(All)
Boolean Exclusive 0 R:
4
•
@
oB
5
H
• @ ••••
®
+
·· ·· ·
·
-- · · ··
} See special Operations
1
Byte:: Zero;
MSp Contents of memory location
pointed to be Stack Pointer;
• 0 t @.
• • t • •
• •
•
t •
•
• • • •
® t R •
• • @ t R •
• • ® : R •
• • ® : R
• • • • •
• •
•
•
•
•
•
•
--@--
00
LEGEND:
OP
a
Z +,N .;V) = 1
BOOLEAN
OPERATION
a
C
BRANCH TEST
;:;
Branch If
4
1
INHER
:;
Branch If
Branch If :: Zero
2
Z V
+- 1) -SP l
XH -M,Xl-(M+-1)
SP H -M, SP L -(M ~ 1)
EXTNO
=
3
N
5
OP
OP
8C
MNEMONIC
Compare Indel Reg
4
H I
INHER
Load Condition Code Register from Stack. (See SpeCial Opp.!a(lons)
I)
(ALL)
Set when Interrupt occurs. If p,eviously ser, a Non·Maskabie Inlerruct
reqUIred ro eXIt (he walt slate.
Set according
10
I~
the conlenls of Accumulato, A.
Reset Always
Not Affected
ConditIon Code Register
Transfer Into;
lS
least SignIficant
Bit = Zero;
MS
Most SigO/ficant
Courtesy Motorola Semiconductor Products, Inc.
APPENDIX K
DAA INSTRUCTION
Decimal Adjust Accumulator
-K-l
A decimal digit may be represented as a 4 bit binary
number e.g. 9 = 1001. Similarly a 2 digit decimal number can be
represented by 8 bits, e.g. 49 10 = 01001001. This form is known
as Binary Coded Decimal or BCD, and is not to be interpreted as
a normal binary number.
Addition of decimal numbers, expressed in BCD, is
possible via the DAA ( Decimal Adjust Accumulator) instruction
as seen in this example:
L[)A A
#$08
AD[) A
#$(16
[)AA
The DAA instruction converts the normal hex sum, OE, to 14, the
expected decimal sum in BCD. This is accomplished internally by
adding 6 in this example (OE + 06 = 14). Details of the internal
operation of the DAA instruction are not essential to its use,
but are given at the bottom of this page. What is important is
that this instruction operates on ACC A, only after execution of
the ADD, ADC or ABA instructions.
Assuming that symbolic addresses OLDATA and NUDATA each
contain one BCD digit, write the instructions to produce the BCD
sum in ACC A.
----/
L[)A A
OLDATA
ADD A NUDATA
DAA
DAA Details: When two 2 digit BCD numbers are added a "carry",
produced by the addition of the "least significant column, sets
the H bit of the CCR, e.g. 7 + 5 produces a carry and sets H,
while 7 + 2 clears H. This H bit is added to to the "most
significant" column, all operations being internal to the DAA
instruction.
lJ
K-2
"2 digit
Decimal addition in~BCD is equally valid for
decimal data, e.g. 47 10 + 78 10 , Here the BCD sum is 125, that is
25 plus a carry into the third column.
lJ
Write the instructions to add OLDATA and NUDATA, the
sum going to TOTAL+1 and the carry going to TOTAL. Assume that
OLDATA and NUDATA each contain 2 decimal digits in BCD form.
0100 7F
€11.€13: 86
€11.~36 88
€11€19 19
(11.0A B'{
~3:10(:t 24
(11.0F 7C
01:12
0150
0:152
€11.54
0:15:1
((?
~315(1
FINI
eLF.:
LOA A
ADD A
DAA
STA A
TOTAL
OLOATA
NUOATA
E:CC
INC
FIN!
(u302
k1:152 0~302
121:154 012102
TOTAL
I
,I
~3:150
TOTAL+1
F~t18
TOTAL
OL[)ATA F.:t18
NliDATA F.:t1B
.-:.
c..
.
2
.-.:!.
Lab instruments, such as digital voltmeters and
frequency counters, often use BCD format to present data to a
computer. Hence the DAA instruction vastly simplifies manipulation of this data, directly in BCD form.
-K-J
Addi tion of 114 digiti' decimal data also requires the
detection of the carry bit after the 2 least significant columns
are added. Use of the ADC (Add with Carry) instruction permits
this carry to be added in when the next 2 most significant digits
are added. Assume that OLDATA and NUDATA each contain 4 BCD
digits in 2 bytes. Write the instructions to produce the 4
digit sum in the 2 bytes labelled TOTAL.
_ _-----J/
:+:
:+: ADDITION OF 4
:+:
l1:1l10 7F t1i50
E:6 ~:::11.5]:
t11.£16 BE: (11.55
_.
~31.(19 i'=t
01.~3A Eo?
0:151"
01.li[) E:6 ~:::11.52
~31.~:::13
~31.1.0
89
~31.54
ttl1.3 1.9
011.4 B7 l31.5£1
eLF.:
L[)A
ADD
DAA
STR
LDA
ADC
DAA
STA
CHAf;.: BCD DATA.
A
A
TOTAL
OLDATA+1.
NU[)ATA+1.
A
A
A
TOTAL+1.
OLDATA
NU[)ATA
SUt'1 IN TOTAL.
BCD SUr1 OF 2 LO DIGITS
BCD SUr1 OF
A
.-.
~
HI
DIGITS
TOTAL
I
•
I
This process could be extended to 6, 8 or N digit BCD addition.
Note that the above program does not detect a carry beyond 4
digits; hence input should be limited to J BCD digits.
I NDE X
Accumulator
ACIA
Addition - Binary
- Hexadecimal
AND
ASCII
Assembler
Background
Binary Number
Bit
Branch Offset
Breakpoint
Byte
2- 1
7- 1
1- 2
1-16
2-20
2- 3
2- 1
11- 1
1- 1
1- 1
6- 6
11-17
1-13
CCR-Condition Code Reg
Character Set- #
- $
2-23
2- 1
3- 6
to
to
to
to
Dec
Bin
Hex
Dec
DAA
Data Buffer
DDR-Data Direct. Reg.
Deferred
Delay
DEX
Direct Mode
END
EQU
Extended Mode
FCB
FCC
FDB
Foreground
Handshake Mode- PIA
Hexadecimal (Hex)
Mask Word
Maskable Interrupt
Machine Code
MSB
J- 5
2- 2
4- 1
2- 5
2-20
1- 3
2-21
11- 1
2- 2
1- 3
2-16
NEG
4-11
NOG
Non Maskable Interrupt 11-12
4-11
Null
2- 2
2- 2
- %
CLR
Comment
Contact Bounce
Conversion-Bin
-Dec
-Dec
-Hex
CTS
5- 7
Label
LDA
LDX
Literal
Logical AND
LSB
8-16
1- 2
1- 7
1-33
1-14
7-12
App.
K
1
8- 1
7-
4-13
9-21
4-10
2-17
3- 7
7- 1
Operand
2- 3
Operation Code (Op Code) 2- 3
Operator
2- 3
OPT
3- 7
ORA
2-25
ORG
3- 3
Parity
PC (Program Counter)
PIA
Programmed Mode- PIA
PSH
PUL
Read Only Buffer
READY Bit
Read Only Buffer
RlVIB
7- 8
6- 3
8- 1
8-10
10- 1
10- 1
7-
1
7- 5
7- 1
3- 4
11- 1
RTI
RTS (Return from Sub.) 9- 1
RTS (Request to Send)
7-12
2- 9
4-11
4-11
4-12
11- 1
8-11
1-12
Immediate Mode
2- 2
INC
2-19
Inclusive OR
2-25
Index Mode
4- 7
Index Register
4- 1
Initialization
2-13
4-10
INX
IRQ- Interrupt Request 11- 1
Service Routine
Signed Number
SP (Stack Pointer)
STA
Start Bit
Stop Bit
Strobe lVIode- PIA
Subtraction- Binary
- Hex
SWI (Software Int.)
Symbolic Address
11- 1
1-23
10- 1
2-11
TSX
10- 4
Vector Address
11- 1
Write Only Buffer
7-
1
7- 1
8-13
1-35
1-29
11-13
3-
7-
1
1
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.4 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c321 44.398116, Tue Aug 04 2009 14:24:30 Modify Date : 2010:11:18 14:28:47-08:00 Create Date : 2010:11:18 11:21:38-08:00 Metadata Date : 2010:11:18 14:28:47-08:00 Creator Tool : Adobe Acrobat 8.2 Combine Files Format : application/pdf Document ID : uuid:69a8350b-16a5-464e-97f7-a8f4e1c063f5 Instance ID : uuid:c7e97e76-e391-ed4e-8b9d-903d4b16da15 Producer : Adobe Acrobat 8.25 Paper Capture Plug-in Page Count : 202 Creator : Adobe Acrobat 8.2 Combine FilesEXIF Metadata provided by EXIF.tools