Sridhar Gangadharan, Sanjay Churiwala (auth.) Constraining Designs For Synthesis And Timing Analysis A%

User Manual:

Open the PDF directly: View PDF .
Page Count: 245 [warning: Documents this large are best viewed by clicking the View PDF Link!]

Scroll down to view the document on your mobile browser.

Foreword
Preface
- Book Organization
- Conventions Used in This Book
- Additional Resources
- Feedback
Acknowledgements
Contents
List of Figures
List of Tables
Chapter 1: Introduction
- 1.1 ASIC Design Flow
- 1.2 FPGA Design Flow
- 1.3 Timing Constraints in ASIC and FPGA Flow
- 1.4 Timing Constraint Issues in Nanometer Design
- 1.5 Conclusion
Chapter 2: Synthesis Basics
- 2.1 Synthesis Explained
- 2.2 Role of Timing Constraints in Synthesis
- 2.3 Commonly Faced Issues During Synthesis
- 2.4 Conclusion
Chapter 3: Timing Analysis and Constraints
- 3.1 Static Timing Analysis
- 3.2 Role of Timing Constraints in STA
- 3.3 Common Issues in STA
- 3.4 Delay Calculation Versus STA
- 3.5 Timing Paths
- 3.6 Setup and Hold
- 3.7 Slack
- 3.8 On-Chip Variation
- 3.9 Conclusion
Chapter 4: SDC Extensions Through Tcl
- 4.1 History of Timing Constraints
- 4.2 Tcl Basics
- 4.3 SDC Overview
- 4.4 Design Query in SDC
- 4.5 SDC as a Standard
- 4.6 Conclusion
Chapter 5: Clocks
- 5.1 Clock Period and Frequency
- 5.2 Clock Edge and Duty Cycle
- 5.3 create_clock
- 5.4 Virtual Clocks
- 5.5 Other Clock Characteristics
- 5.6 Importance of Clock Specification
- 5.7 Conclusion
Chapter 6: Generated Clocks
- 6.1 Clock Divider
- 6.2 Clock Multiplier
- 6.3 Clock Gating
- 6.4 create_generated_clock
- 6.5 Generated Clock Gotchas
- 6.6 Conclusion
Chapter 7: Clock Groups
- 7.1 Setup and Hold Timing Check
- 7.2 Logically and Physically Exclusive Clocks
- 7.3 Crosstalk
- 7.4 set_clock_group
- 7.5 Clock Group Gotchas
- 7.6 Conclusion
Chapter 8: Other Clock Characteristics
- 8.1 Transition Time
- 8.2 set_clock_transition
- 8.3 Skew and Jitter
- 8.4 set_clock_uncertainty
  - 8.4.1 Intraclock Uncertainty
  - 8.4.2 Interclock Uncertainty
- 8.5 Clock Latency
- 8.6 set_clock_latency
- 8.7 Clock Path Unateness
- 8.8 set_clock_sense
- 8.9 Ideal Network
- 8.10 Conclusion
Chapter 9: Port Delays
- 9.1 Input Availability
- 9.2 Output Requirement
- 9.3 set_input_delay
- 9.4 set_output_delay
- 9.5 Relationship Among Input and Output Delay
- 9.6 Example Timing Analysis
- 9.7 Negative Delays
- 9.8 Conclusion
Chapter 10: Completing Port Constraints
- 10.1 Drive Strength
  - 10.1.1 set_drive
- 10.2 Driving Cell
  - 10.2.1 set_driving_cell
- 10.3 Input Transition
  - 10.3.1 Input Transition Versus Clock Transition
- 10.4 Fanout Number
- 10.5 Fanout Load
- 10.6 Load
- 10.7 Conclusion
Chapter 11: False Paths
- 11.1 Introduction
- 11.2 set_false_path
- 11.3 Path Specification
- 11.4 Transition Specification
- 11.5 Setup/Hold Specification
- 11.6 Types of False Paths
- 11.7 set_disable_timing
- 11.8 False Path Gotchas
- 11.9 Conclusion
Chapter 12: Multi Cycle Paths
- 12.1 SDC Command for Multi Cycle Paths
- 12.2 Path and Transition Specification
- 12.3 Setup/Hold Specification
- 12.4 Shift Amount
- 12.5 Example Multi Cycle Specification
- 12.6 Conclusion
Chapter 13: Combinational Paths
- 13.1 set_max_delay
- 13.2 set_min_delay
- 13.3 Input/Output Delay
- 13.4 Min/Max Delay Versus Input/Output Delay
- 13.5 Feedthroughs
  - 13.5.1 Feedthroughs Constrained Imperfectly
- 13.6 Point-to-Point Exception
- 13.7 Path Breaking
- 13.8 Conclusion
Chapter 14: Modal Analysis
- 14.1 Usage Modes
- 14.2 Multiple Modes
- 14.3 Single Mode Versus Merged Mode
- 14.4 Setting Mode
- 14.5 Other Constraints
- 14.6 Mode Analysis Challenges
  - 14.6.1 Timing Closure Iterations
  - 14.6.2 Missed Timing Paths
- 14.7 Conflicting Modes
- 14.8 Mode Names
- 14.9 Conclusion
Chapter 15: Managing Your Constraints
- 15.1 Top-Down Methodology
- 15.2 Bottom-Up Methodology
- 15.3 Bottom-Up Top-Down (Hybrid) Methodology
- 15.4 Multimode Merge
- 15.5 Challenges in Managing the Constraints
- 15.6 Conclusion
Chapter 16: Miscellaneous SDC Commands
- 16.1 Operating Condition
- 16.2 Units
- 16.3 Hierarchy Separator
  - 16.3.1 set_hierarchy_separator
  - 16.3.2 -hsc
- 16.4 Scope of Design
  - 16.4.1 current_instance
- 16.5 Wire Load Models
- 16.6 Area Constraints
- 16.7 Power Constraints
- 16.8 Conclusion
Chapter 17: XDC: Xilinx Extensions to SDC
- 17.1 Clocks
- 17.2 Timing Exceptions
- 17.3 Placement Constraints
- 17.4 SDC Integration in Xilinx Tcl Shell
- 17.5 Conclusion
Bibliography
Index

Navigation menu