Synertek_1981 1982_Data_Catalog Synertek 1981 1982 Data Catalog
User Manual: Synertek_1981-1982_Data_Catalog
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. .SYNERTEK
,\ 1981-1982
. DATA CATALOG
.
Table of Contents
Index
SYNERTEK
1981-1982
DATA CATALOG
SYNERTEK
A SUBSIDIARY OF HONEYWELL
•
P.O. BOX 552 - MS/34
TEL. (408)988-5600
0
SANTAClARA,CA95052
lWX:910-338-0135
Random Access Memories
1
Read Only Memories
2
Microprocessors
3
Systems
5
Quality Assurance
6
Generallnformation
7
Contents
CHAPTER 1
Random Access Memory
Page
RAM Selector Guide ................................................................ 1-2
SY2101, 256 x 4-Bit Static RAM .................................................... 1-3
SY2111, 256 x 4-Bit Static RAM .................................................... 1-7
SY2112, 256 x 4-Bit Static RAM .................................................. 1-11
SY2114, 1024 x 4-Bit Static RAM ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-17
SY2114LV, 1024 x 4-Bit Static RAM .............................................. 1-21
SY2128, 2048 x 8-Bit Static RAM ......................................... , ....... 1-25
SY2142, 1024 x 4-Bit Static RAM ................................................. 1-26
SY2142LV, 1024 x 4-Bit Static RAM ............................................... 1-30
SY2147, 40£16 x 1-Bit Static RAM .................................................. 1-34
SY2147H, 4096 x 1-Bit Static RAM ................................................ 1-38
SYM2147, 4096 x 1-Bit Static RAM ................................................ 1-39
SY2148H, 1024 x 4-Bit Static RAM ................................................ 1-40 .
SYM2148, 1024 x 4-Bit Static RAM ................................................ 1-44
SY2149H, 1024 x 4-Bit Static RAM ................................................ 1-45
SYM2149H, 1024 x 4-Bit Static RAM ........................ . . . . . . . . . . . . . . . . . . . . . .. 1-49
CHAPTER 2
Read Only Memory
ROM Selector Guide ............................................................... 2-2
SY2316A1B, 2048 x 8-Bit ROM ..................................................... 2-3
SY2316B-2, 2048 x 8-Bit ROM .................................. , ................... 2-7
SY2316B-3, 2048 x 8-Bit ROM .................................................... 2-11
SY2332/3, 4096 x 8-Bit ROM ..................................................... 2-15
SY2332/3-3, 4096 x 8-Bit ROM ..................................................... 2-19
SY2364/A, 8192 x 8-Bit ROM ..................................................... 2-23
SY2365/A, 8192 x 8-Bit ROM ..................................................... 2-27
SY23128, 16,384 x 8-Bit ROM .................................................... 2-31
SY3308, 1024 x 8-Bit ROM ....................................................... 2-35
SY3316/A, 2048 x 8-Bit ROM ................................................... :. 2-36
SYM3316/A, 2048 x 8-Bit ROM ................................................... 2-40
CHAPTER 3
Microprocessors
Microcomputers
Z8, Single Chip Microcomputer
................................................... 3-3
Microprocessors and Peripherals
Floppy Disk Controller ..................................... 3-23
SY2661, Enhanced Programmable Communications Interface ....................... 3-39
SY6500, 8-Bit Microprocessor Family ............................................. 3-53
SY6520, Peripheral Interface Adapter ............................................. 3-67
SY6521/SY6821, Peripheral Interface Adapter ...................................... 3-81
SY6522, Versatile Interface Adapter ............................................... 3-95
SY6530, Memory, 1/0, Timer Array .............................................. 3-117
SY6532, RAM, 1/0, Timer Array ................................................. 3-129
SY6545, CRT Controller ........................................................ 3-139
SY6551, Asynchronous Communication Interface Adapter ......................... 3-169
SY6591, Floppy Disk Controller ........................ : ........................ 3-179
SY6691/SY6692, ANSI Rigid Disk Controller ...................................... 3-183
SY68045, CRT Controller ......................... _. . . . . . . . . . . . .. . . . . . . .. . . . . . .. 3-185
SY1791-02/SY1793-02,
Contents (Contd.)
CHAPTER 4
Page
Logic Capabilities ... .............................................................. 4-1
CHAPTER 5
Systems
CP110, Super Jolt CPU Board ..................................................... 5-2
AS200, Universal Card ........................................................•.... 5-2
EPS-1, SYM-1 Diagnostic Program .................... , ............................ 5-2
SYM-1, Single Board Computer .................................................... 5-3
SYM-1/68; SYM-1/69, Single Board Computers ...................................... 5-3
MOD-68; MOD-69, Adapter Boards for SYM-1 ....................................... 5-4
PEX-1, Port Expansion and Connector Kit ........................................... 5-4
SRM-1/SRM-3, Static RAM Memory Kit ............................................. 5-4
SM100, OEM Version of SYM-1 .................................................... 5-5
BAS-1, Full Function BASIC ....................................................... 5-5
RAE-1, Resident Assembler/Editor .................................................. 5-5
KTM-2, Keyboard Terminal Module ................................................. 5-6
KTM-3, Keyboard Terminal Module ................................................. 5-7
MBC010, CPU Board .............................................................. 5-9
MBC020, CPUlVideo Board ........................................................ 5-9
MBC01A2/MBC01A2-1, Single Board Computer Motorola Micromodule Replacement . 5-11
MBC008/016, Static RAM Modules ................................................ 5-13
MBC016D, MBC032D, MBC048D, MBC064D, Dynamic RAM Boards ................. 5-14
MBC081, EPROM Pwgrammer ................................................... 5-15
MBC091, Prototyping Board ................................................... " 5-15
MOC092/93, Extender Boards .................................................... 5-15
MBC210, Floppy Disk Controller ........................................... , ..... 5-16
MBC510, Combo I/O Board ....................................................... 5-16
MDT2000, Micro Development System for Z8 and SY6500 Microprocessors .......... 5-17
CHAPTER 6
Quality Assurance ................................................................ 6-1
CHAPTER 7
General Information
Ordering Information ...............................................................7-2
Packaging Information .............................................................. 7-3
ii
Numerical Index
Page
Page
Z8'"
SY1791-021
SY1793-02
SY2101-1
SY2101A
SY2101A-2
SY2101A-4
SY2111-1
SY2111A
SY2111A-2
SY2111A-4
SY2112-1
SY2112A
SY2112A-2
SY2112A-4
SY2114
SY2114-1
SY2114-2
SY2114-3
SY2114L
SY2114L-1
SY2114L-2
SY2114L-3
SY2114LV
SY2114LV-2
SY2114LV-3
SY2128
SY2142
SY2142-2
SY2142-3
SY2142L
SY2142L-2
SY2142L-3
SY2142LV
SY2142LV-2
SY2142LV-3
SY2147
SY2147-3
SY2147-6
SY2·147L
SY2147H
SY2148H
SY2148H-2
SY2148H-3
SY2148HL
SY2148HL-3
SY2149H
SY2149H-2
SY2149H-3
SY2149HL
SY2149HL-3
SY2316A
SY2316B
SY2316B-2
Single-Chip Microcomputer ................. 3-3
2048x8 Bit Static.MOS ROM (300 nsec)
2-11
4096x8 Bit Static MOS ROM (450 nsec)
2-15
4096x8 Bit Static MOS ROM (300 nsec)
2-19'
4096x8 Bit Static MOS ROM (450 nsec)
2-15
4096x8 Bit Static MOS ROM (300 nsec)
2-19
8192x8 Bit Static MOS ROM (450 nsec)
2-23
8192x8 Bit Static MOS ROM (200 nsec)
2-23
8192x8 Bit Static MOS ROM (300 nsec)
2-23
8192x8 Bit Static MOSROM(450 nsec)
2-23
8192x8 Bit Static MOS ROM (200 nsec)
2-23
8192x8 Bit Static MOS ROM (300 nsec)
2-23
8192x8 Bit Static MOS ROM (450 nseci
2-27
2-27
8192x8 Bit Static MOS ROM (200 nsec)
8192x8 Bit Static MOS ROM (300 nsec)
2-27
2-27
8192x8 Bit Static MOS ROM (450 nsec)
8192x8 Bit Static MOS ROM (200 nsec)
2-27
8192x8 Bit Static MOS ROM (300 nsec)
2-27
16,384x8 Bit Static MOS ROM (200 nsec) .... 2-31
Enhanced Programmable ,Communications
Interface ............................... 3-39
1024x8 Bit Static MOS ROM (70 n~ec)
2-32
SY3308
2048x8 Bit Static MOS ROM (80 nsec) ....... 2-36
SY3316
2048x8 Bit Static MOS ROM (80 nsec) ....... 2-36
SY3316A
8~Bit Microprocessor Family ............. 3-53
SY6500
8-Bit Microprocessor Family
SYE6500/6500A
(Extended Temperature) ................ 3-65
SY6520/6520A
SY6820/68B20
Peripheral Interface Adapter (PIA) ........ 3-67
SYE6520/6820
Peripheral Interface Adapter
SYE6520A/68B20 (Extended Temperature) ................ 3-79
SY6521/6821
Peripheral Interface Adapter (PIA) ......... 3-81
SY6521 A/68B21
Peripheral Interface Adapter
SYE6521/6821.
SYE6521 A168B21 (Extended Temperature) ................ 3-93
Versatile I nterface Adapter ............ " 3-95
SY6522/6522A
Versatile Interface Adapter
SYE6522/6522A
(Extended Temperature) .............. 3-115
Memory, 1/0, Timer Array ............. 3-117
SY6530
RAM, 1/0, Timer Array ................ 3-129
SY6532
RAM, 1/0, Timer Array
SYE6532
(Extended Temperature) .............. 3-137
SYE6532A
CRT Controller ....................... 3-139
SY6545
CRT
Controller ....................... 3-155
SY6545-1
Asynchronous Communication Interface
SY6551
Adapter.............................. 3-169
Asynchronous Communication Interface
SYE6551/6551A
Adapter (Extended Temperature) ...... 3-177
Floppy Disk Controller (FDC) .......... 3-179
SY6591 16591 A
ANSI Rigid Disk Controller (ARDC'") ... 3-183
SY6691 16692
CRT Controller (CRTC) ............... 3-185
SY68045
SY2316B-3
SY2332
SY2332-3
SY2333
SY2333-3
SY2364
SY2364-2
SY2364-3
SY2364A
SY2364A-2
SY2364A-3
SY2365
SY2365-2
SY2365-3
SY2365A
SY2365A-2
SY2365A c3
SY23128
SY2661
Floppy Disk Controller (FDC) .............. 3-23
1-3
256x4 Bit Static MOS RAM (500 nsec)
1-3
256x4 Bit Static MOS RAM (350 nsec)
256x4 Bit Static MOS RAM (250 nsec)
1-3
256x4 Bit Static MOS RAM (450 nsec)
1-3
256x4 Bit Static MOS RAM (500 nsec)
1-7
256x4 Bit Static MOS RAM (350 nsec)
1-7
256x4 Bit Static MOS RAM (250 nsec)
1-7
256x4 Bit Static MOS RAM (450 nsec)
1-7
1-11
256x4 Bit Static MOS RAM (500 nsec)
256x4 Bit Static MOS RAM (350 nsec)
1-11
256x4 Bit Static MOS RAM (250 nsec)
1-11
256x4 Bit Static MOS RAM (450 nsec)
1-11
1024x4 Bit Static MOS RAM (450 nsec)
1-17
1024x4 Bit Static MOS RAM (150 nsec)
1-17
1024x4 Bit Static MOS RAM (200 nsec)
1-17
1024x4 Bit Static MOS RAM (300 nsec)
1-17
1024x4 Bit Static MOS RAM
Low Power (450 nsec) ................... 1-17
1024x4 Bit Static MOS RAM
Low Power (150 nsec) ................... 1-17
1024x4 Bit Static MOS RAM
Low Power (200 nsec) ................... 1-17
1024x4 Bit Static MOS RAM
Low Power (300 nsec) ................... 1-17
1024x4 Bit Static MOS RAM
Power Down (450 nsec) .................. 1-21
1024x4 Bit Static MOS RAM
Power Down (200 nsec) .................. 1-21
1024x4 Bit Static MOS RAM
Power Down (300 nsec) .................. 1-21
2048x8 Bit Static MOS RAM (120 nsec)
1-25
1024x4 Bit Static MOS RAM (450 nsec)
1-26
1024x4 Bit Static MOS RAM (200 nsec)
1-26
1024x4 Bit Static MOS RAM (300 nsec)
1-26
1024x4 Bit Static MOS RAM (450 nsec)
1-26
1024x4 Bit Static MOS RAM (200 nsec)
1-26
1024x4 Bit Static MOS RAM
Low Power (300 nsec) ................... 1-26
1024x4 Bit Static MOS RAM (450 nsec)
1-30
1024x4 Bit Static MOS RAM (200 nsec) .... 1-30
1024x4 Bit Static MOS RAM (300 nsec) .... 1-30
4096x1 Bit Static MOS RAM (70 nsec)
1-34
4096x1 Bit Static MOS RAM (55 nsec)
1-34
4096x1 Bit Static MOS RAM (85 nsec)
1-34
4096x1 Bit Static MOS RAM (70 nsec)
1-34
4096x1 Bit Static MOS RAM (35-70 nsec) .. 1-38
1024x4 Bit Static MOS RAM (70 nsec)
1-40
1024x4 Bit Static MOS RAM (45 nsec)
1-40
1-40
1024x4 Bit Static MOS RAM (55 nsec)
1024x4 Bit Static MOS RAM
Low Power (70 nsec) .................... 1-40
1024x4 Bit Static MOS RAM
Low Power (70 nsec) .................... 1-40
1024x4 Bit Static MOS RAM (70 nsec)
1-45
1024x4 Bit Static MOS RAM (45 nsec)
1-45
1024x4 Bit Static MOS RAM (55 nsec)
1-45
1024 x4 Bit Static MOS RAM
Low Power (70 nsec) .........•.......... 1-45
1024x4 Bit Static MOS RAM
Low Power (55 nsec) ...•................ 1-45
2048x8 Bit Static MOS ROM (550 nsec)
2-3
2048x8 Bit Static MOS ROM (450 nsec)
2-3
2048x8 Bit Static MOS ROM (200 nsec)
2-7
Military Grade Products: T A = -55 0 C to +125 0 C
SYM2147
SYM2147-6
SYM2148
SYM2148-6
SYM2149H
SYM2149H-3
SYM3316
SYM3316A
iii
4096x1
4096x1
1024x4
1024x4
1024x4
1024x4
2048x8
2048x8
Bit Static MOS RAM (70 nsec)
Bit Static MOS RAM (85 nsec)
Bit Static MOS RAM (70 nsec)
Bit Static MOS RAM (85 nsec)
Bit Static MOS RAM (70 nsec)
Bit Static MOS RAM (55 nsec)
Bit Static MOS ROM (1()0 nsec)
Bit Static MOS ROM (100 nsec)
1-39
1-39
1-44
1-44
1-49
1-49
2-40
2-40
Numerical Index (Contd.)
Page
Systems:
CP110
AS200
EPS-1
SYM-1
SYM-1/68;
SYM-1/69
MOD-68;
MOD-69
PEX-1
SRM-1/SRM-3
SM100
BAS~1
RAE-1
KTM-2
KTM"3
MBC010
MBC020
MBC01A21
MBC01A2-1
MBC008/016
MBC016D
MBC032D
MBC048D
MBC064D
MBC081
MBC091
MBC092/93
. MBC210
MBC510
MDT2000
Super Jolt CPU Board ••..••..••.••••..
Universal Card •..•..••.••.•••..•••..
SYM-1 Diagnostic Program ............ ..
Single Board Computer ••.••••••.••••..
5-2
5-2
5-2
5-3
Single Board Computers
5-3
••.•.••..•••••.
Adapter Boards for SYM-1 ••••••....••.• 5-4
Port Expansion and Connector Kit •...••.. 5-4
Static RAM Memory Kit .••••.••.•..•••. 5-4
OEM Version of SYM-1 .•••••••••..•••• 5-5
Full Function BASIC •.••.••.•.•••..••• 5-5
Resident Assembler/Editor ..•••••...•.•. 5-5
Keyboard Terminal Module .•.••.•..•••• 5-6
Keyboard Terminal Module •••.•.•...••• 5-7
CPU Board ••..•••••... .'............ 5-9
CPUlVideo Board •.•.••..•.••.••.•.•• 5-9
Single Board Computer.
Motorola Micromodule Replacement ••..•• 5c11
Static RAM Modules .••..•.•..•••••..• 5-13
Dynamic RAM boards .•.. : ...••••••... 5-14
EPROM Programmer .••.••.•...•.•••••
Prototyping Board •••••..• , ............
Extender Boards •••..••.•..•••••••••.
Floppy Disk Controller ••••.•..••..•••••
Com bo I/O Board •.•••••.••••..••••••
Micro Development System for Z8
and SY6500 Microprocessors ••••••.••• :.
5-15
5-15
5-15
5-16
5,16
5-17
iv
The information contained in this document has
been carefully checked and is believed to be
reliable; however, Synertek shall not be responsible for any loss or damage of whatever nature
resulting from the use of, or reliance upon, the
information contained in this document. Synertek
makes no guarantee or warranty concerning the
accuracy of such information, and this document
does not in any way extend Synertek's warranty
on any product beyond that set forth in Synertek's
standard terms and conditions of sale. Synertek
does not guarantee that the use of any information contained herein will not infringe upon
the patent or other rights of th!rd parties, and no
patent or other license is implied hereby.Synertek
reserves the right to make changes in the product
without notification which would render the information contained in this document obsolete or
inaccurate. Please contact Synertek for the latest
information concerning this product.
v
vi
Commercial: T A = 00 C to +70 0 C
Part No.
No. of Pins
22
22
22
22
18
18
18
18
16
16
16
16
500
350
250
450
500
350
250
450
500
350
250
450
70
55
55
55
70
55
55
55
70
55
55
55
-
18
18
18
18
18,
18'
18
18
18
18
18
20
20
20
20
20
20
20
20
20
18
18
18
18
18
18
18
18
18
18
450
150
200
300
450
150
200
300
450
200
300
450
200
300
450
200
300
450
200
300
70
45
55
70
55
70
45
55
70
55
100
100
100
100
70
70
70
70
70
70
70
100
100
100
70
70
70
70
70
70
150
150
150
125
125
150
150
150
125
125
-
x1
x1
x1
x1
x1
18
18
18
18
18
70
55
85
70
35-70
160
180
160
140
180
2048 x 8
24
120-200
100
Organization
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
256
256
256
256
256
256
256
256
256
256
256
256
SY2114
SY2114-1
SY2114-2
SY2114-3
SY2114L
SY2114L-1
SY2114L-2
SY2114L-3
SY2114LV
SY2114LV-2
SY2114LV-3
SY2142
SY2142-2
SY2142-3
SY2142L
SY2142L-2
SY2142L-3
SY2142LV
SY2142LV-2
SY2142LV-3
SY2148H
SY2148H-2
SY2148H-3
SY2148HL
SY2148HL-3
SY2149H
SY2149H-2
SY2149H-3
SY2149HL
SY2149HL-3
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
SY2147
SY2147-3
SY2147-6
SY2147L
SY2147H, 2 1
4096
4096
4096
4096
4096
2
Maximum Current (mA)
Access Time
(ns)
Max.
SY2101-1
SY2101A
SY2Hi1A-2
SY2101A-4
SY2111-1
SY2111A
SY2111A-2
SY2111A-4
SY2112-1
SY2112A
SY2112A-2
SY2112A-4
SY2128
RAM Selector Guide
Operating
Standby
-
-
-
-
-
Power Supply
(Volts)
Page
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
1-3
1-3
1-3
1-3
1-7
1-7
1-7
1-7
1-11
1-11
1-11
1-11
+5
+5
+5
+5
+5
+5
+5
+5
+51 11
+51 11
+51 11
+5
+5
+5
+5
+5
+5
+51 1,
+5!1,
+51 11
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
1-17
1-17
1-17
1-17
1-17
1-17
1-17
1-17
1-21
1-21
1-21
1-26
1-26
1-26
1-26
1-26
1-26
1-30
1-30
1-30
1-40
1-40
1-40
1-40
1-40
1-45
1-45
1-45
1-45 .
1-45
20
30
20
10
30
+5
+5
+5
+5
+5
1-34
1-34
1-34
1-34
1-38
30
+5
1-25
-
-
-
-
-
-
-
30
30
30
20
20
-
-
Military: T A = -55 C to +125 C
0
SYM2148 2
SYM2148-6 2
SYM2149H 2
SYM2149H-3
SYM2147 2
SYM2147-6
2
2
0
x4
x4
x4
x4
4096 x 1
4096 x 1
1024
1024
1024
1024
-
+5
+5
+5
+5
1-44
1-44
1-49
1-49
30
30
+5
+5
1-39
1-39
18
18
18
18
70
85
70
55
150
150
150
150
30
30
18
18
70
85
180
180
1. +2.5V Data Retention
2. To Be Announced.
1-2
256x4Stadc
SY2101
Random Access Memory
MEMORY
PRODUCTS
SYNERTEK
A SUBSIDIARV OF HONEYWELL
•
•
•
•
•
•
256x4 Organization to Meet Needs For Small System Memories
Access Time - 250/350/450/500/ns
Single +5V Supply Voltage
Directly TTL Compatible - All Inputs and Outputs
Static MOS - No Clocks or Refreshing Required
Simple Memory Expansion - Two Chip Enable
Inputs
The SY2101 is a 256 word by 4 bit static random
access memory element using N-channel MOS devices
integrated on a monolithic array. It uses fully DC
stable (static) circuitry and therefore requires no
clocks or refreshing to operate. The data is read out
nondestructively and has the same polarity as the input data.
The SY2101 is designed for memory applications
where high performance, low cost, large bit storage,
and simple interfacing are important design objectives.
It is directly TTL compatible in all respects: inputs,
outputs, and a single +5V supply. Two Chip Enables
allow easy selection of an individual package when
outputs are OR-tied. An. output disable is provided
•
•
•
•
•
Inputs Protected - All Inputs Have Protection
Against Static Charge
Low Cost Packaging - 22 Pin Plastic Dual-In-Line
Configuration
Low Power - Typically 150 mW
Three-State Output - OR-Tie Capability
Output Disable Provided For Ease of Use in
Common Data Bus Systems
so that data inputs and outputs can be tied for common I/O systems. Output disable is then used to eliminate any bi-directionallogic.
The SY2101 is fabricated with N-channel ion implanted silicon gate technology. This technology
allows the design and production of high-performance,
easy-to-useMOS circuits and provides a higher functional density on a monolithic chip than either conventional MOS technology or N-channel silicon gate
technology.
Synertek's ion implanted silicon gate technology also
provides excellent protection against contamination.
This permits, the use of low cost plastic packaging.
BLOCK DIAGRAM
PIN CONFIGURATION
A3
Vee
@
-Vee
A2
A'
R/W
A,
AD
ffi
A,
A'
00
AS
CE2
A7
DO'
GNO
01,
01,
003
DO'
01 3
~GND
MEMORY ARRAY
32 ROWS
32 COLUMNS
Oh
01,
002
0'3
ORDERING INFORMATION
01,
Order
Number
Package
Type
Access
Time
Temperature
. Range
SYP2101-1
SYC2101-1.
SYP2101A-2
SYC2101A-2
SYP2101A
SYC21 01 A
SYP2101 A-4
SYC2101A-4
Plastic DIP
Ceramic DIP
Plastic DIP
Ceramic DIP
Plastic DIP
Ceramic DIP
Plastic DIP
Ceramic DIP
500 ns
500 ns
250 ns
250 ns
350 ns
350 ns
450 ns
450 ns
O°C to
OOC to
OOC to
O°C to
O°C to
O°C to
O°C to
OOC to
70°C
70°C
70°C
70°C
70°C
70°C
70°C
70°C
a=
PIN NUMBERS
PIN NAMES
DIN
AO-A7
R/W
CE1. CE2
1-3
DATA INPUT
ADDRESS INPUTS
READ/WRITE INPUT
CHIP ENABLE
00
DOUT
VCC
OUTPUT DISABLE
OAT A OUTPUT
POWER (+5VI
SY2tOt
ABSOLUTE MAXIMUM RATINGS
COMIViENT:
Stresses above those listed under "Absolute Maximum Rating" may'cause permanent damage to the device. This is a stress rating' only ,and"' functional
operation of the device at these or at any other condition above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
- 10b C to +80°C
-6SoC to +lS0°C
~mbient
Temperature Under Bias
Storage Temperature
Voltage On Any Pin With
Respect to Ground
Power Dissipation
-O.SV to +7V
1 Watt
D.C. AND OPERATING CHARACTERISTICS
T A = O°C to 70°C, VCC = SV ±S% unless otherwise specified.
210tA·2
2101·1
Symbol
Min.
Parameter
III
Input Current
Typ.!H
Max.
2101A,2101A-4
Min. Typ.(1) Max.
10
10
Unit
Test Conditions
p.A
VIN=Oto5.25V
ILOH
I/O Leak~geCurrent(2)
15
10
p.A
CE = 2.2V, VOUT = 4.0V
ILOL
I/O Leakage Current(2)
-50
-10
p.A
C.E= 2.2V: VOUT =O.45V
ICC1
Power Supply CiJrrent
50
rnA
ICC2
Power Supply Current
55
rnA
VIL
Input Low
Voltag~
-0.5
+0.65
-0.5
+0.8
V
VIH
Input High Voltage
2.2
VCC
2.0
VCC
V
VOL
Output Low Voltage
+0.4
V
VOH
Output High Voltage
30
30
60
70
+0.45
2.2
2.4
NOTE: .1. Typical Values are for TA = 25°C and no")inal supply voltage.
V
VIN = 5.25V, 10 = OrnA
TA = 25°C
VIN = 5.25V, 10 = OrnA
TA.=O°C
10L =3.2rnA
(lOL = 2.0rnA 210,.,)
IOH=-150p.A
2. Input and Output tied together ..
CAPACITANCE TA = 25°C, f =lMHz
..
Symbol
CIN
COUT
Test
Input Capacitance (All Input Pins) VIN = OV
·Output Capacitance VOUT= OV
Typ.
Max.
Unit
4
8
8
12
pF
pF
Min.
Max.
Unit
A.C. CHARACTERISTICS - SY2101·1
T A = O°C to 70°C, VCC = SV ±S% unless ~therwise specified.
Symbol
I
.
Parameter
READ CYCLE
tRCY
tA
tco
too
tDF[l)
tow
Read Cycle
500
Access Time
Chip Enable To Output
Output Disable To Output
Data Output to High Z State
Previous Data Read Valid after change of Address
0
0
ns
SOO
3S0
ns
ns
300
lS0
ns
ns
ns
WRITE CYCLE
twCY
tAW
tcw
tDW
tDH
twp
tWR
Write Cycle
Write Delay
SOO
100
400
Chip Enable To Write
pata Setup
. Data Hold
Write Pulse
Write Recovery
ns
280
ns
ns
100
ns
300
ns
ns
50
1-4
r;lS '
SY2101
A.C. CHARACTERISTICS - SY2101A-2
T A = O°C to 70°C, VCC = 5V ±5% unless otherwise specified.
Parameter
Symbol
Min.
Max.
Unit
250
ns
ns
READ CYCLE
Read Cycle
tRCY
tA
250
Access Time
Chip Enable To Output
Output Disable To Output
Data Output to High Z State
Previous Data Read Valid after change of Address
0
40
tWCY
tAW
tcw
Write Cycle
250
Write Delay
Chip Enable To Write
20
150
ns
ns
ns
tow
Data Setup
150
ns
tDH
twp
Data Hold
0
ns
150
0
20
ns
tco
tOD
tDF[1]
tOH
180
130
180
ns
ns
ns
ns
WRITE CYCLE
Write Pulse
Write Recovery
twR
tDS
Output Disable Setup
ns
ns
A.C. CHARACTERISTICS - SY2101A
T A = O°C to 70°C, VCC = 5V ±5% unless otherwise specified.
Symbol
I
Min.
Parameter
Max.
Unit
350
240
180
150
ns
READ CYCLE
tRCY
tA
tco
too
tDF[1]
tOH
Read Cycle
ns
350
Access Time
Chip Enable To Output
Output Disable To Output
Data Output to High Z State
Previous Data Read Valid after change of Address
0
40
ns
ns
ns
ns
WRITE CYCLE
tWCY
tAW
tcw
Write Cycle
Write Delay
Chip Enable To Write
350
20
200
ns
ns
ns
tDW
tDH
Data Setup
200
ns
Data Hold
0
twP.
twR
Write Pulse
Write Recovery
200
0
ns
ns
ns
tDS
Output Disable Setup
20
ris
NOTE: 1 tDF is with respect to the trailing edge of CE1, CE2, or OD, whichever occurs first.
1-5
SY2101
A.C. CHARACTERISTICS - SY2101A-4
T A = ODC to 70DC, VCC·= 5V ±5% unless otherwise specified,
I
Symbol
. Min •.
Parameter
. Max .
Unit
READ CYCLE
450
Read Cycle
tRCY
tA
Access Time
Chip Enable To Output
tco
too
tDF[1]
tOH
"
Output Disable To Output
.'
Data Output to High Z State
Previous Data Read Valid after change of Address
0
40
Write Cycle
450
Write Delay
Chip Enable To Write
Data Setup
Data Hold
Write Pulse
Write Recovery
20·
250
250
,0
•..
ns
450
ns
310
ns
250
200
ns
ns
'ns
WRITE CYCLE
twCY
tAW
tcw
tow
tDH
twP
twR
tDS
250
0
Output Disable Setup
A.C. CONDITIONS OF TEST
ns
ns
ns
ns
ns
ns
20
2101A-2
2101A
TIMING DIAGRAMS
READ CYCLE
ns
2101-1
.2101A4
Input Pulse Levels: . . . . . . . . . . . . . • . . . • . . . . . . . . .. +O.BV,to 2.0V
Input Pulse Rise & Fall Times: . . . . . . • . . . . . . . . . . . . . . . . ,., .. 10ns
Inputs:· . . . . . . . . . . . . • . : 1.5\/
Timing Measurement Reference Level:
Outputs: •...•... ; O.BV & 2.0V
Output Load: . . . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate & CL = 100pF
ns
"
·
·
·
·
. . . . . . . . . . . +0.65V to 2.2V
. . . . . . . . . . . . . . . . . . 10ns
..........•. , ........ 1.5V
. . . . . . . . . . . . . O.BV & 2.0V
1 TTL Gate & CL = 100pF
WRITE CYCLE
_---~-,..."WCV
1-...,..-----tRCV-------I
_ _ _ _ ___I
ADDRESS
I----tcw----.I
CE2
CE2
14---'·tcw----t
12)
00
00
(COMMON 1/01(3)
DATA
OUT
NOTES:
rn,
1. tOF is with respect to the trailing edge of
CE2, or DO, whichever occurs first.
2. During the write cycle, 00 is a logical 1 for common 110 and "don't'care" for separate
I/O operation.
3, 00 should be tied low for separate I/O operation.
1-6
256x 4 Static
SY21t1
RandQm Access Memory
MEMORY
PRODUCTS
SYNERTEK
A SUBSIDIARY OF HONEYWELL
o Organization 256 Words By 4 Bits
o Common Data Input And Output
o Single +5V Supply Voltage
CI Directly TTL Compatible - All Inputs and Outputs
o Static MOS - No Clocks or Refreshing Required
o Access Time - 250/350/450/500ns
o Simple Memory Expansion - 2 Chip Enable Inputs
o Fully Decoded - On-Chip Address Decode
o Inputs Protected - All Inputs have Protection
Against Static Charge
o Low Cost Packaging - 18 Pin Plastic Dual-I n-Line
Configuration
o Low Power - Typically 150mW
o Three - State Output - OR - Tie Capability
The SY2111 is a 256 word by 4 bit static random access memory element using N-channel MOS devices integrated on a monolithic array. It uses fully DC stable
(static) circuitry and therefore requires no clocks or
refreshing to operate. The data is read out nondestructively . and has the same polarity as the input data.
Common input/output pins are provided.
outputs, and a single +5V supply. Separate Chip Enable
leads allow easy selection of an individual package
when outputs are OR-tied.
The SY21 i 1 is fabricated with N-channel ion-implanted
silicon gate technology, which allows the design and
production of high performance, easy-to-use MOS circuits and provides a higher functional density on a
monolithic chip than either conventional MOS technology or N-channel silicon gate technology.
The SY2111 is designed for memory applications in
small systems where high performance, low cost, large
bit storage, and simple interfacing are important design
objectives.
Synertek's silicon gate technology also provides excellent protection against contamination. This permits
the use of low cost plastic packaging.
It is directly TTL compatible in all respects: inputs,
PIN CONFIGURATION
BLOCK DIAGRAM
Ao
Vcc
A3
A2
A4
A,
R/W
®
®
----.oGND
- - - - . 0 Vee
A,
MEMORY ARRAY
32 ROWS
32 COLUMNS
A,
AJ
AO
CE,
A5
1/04
A6
1/0 3
A7
1/02
GND
I/o,
OD
CE2
A,
I/O,
@
@
1/0 2
@
INPUT
DATA
CONTROL
1/03
@
1/04
ORDERING INFORMATION
Order
Number
SYP2111-1
SYD2111-1
SYP2111A-2
SYD2111A-2
SYP2111A
SYD211 iA
SYP2111A-4
SYD2111A-4
Package
Type
Plastic DIP
eerdip
Plastic DIP
Cerdip
Plastic DIP
eerdip
Plastic DIP
eerdip
Access Temperature
Time
Range
500
500
250
250
350
350
450
450
ns
ns
ns
ns
ns
ns
ns
ns
ooe
ooe
O°C
ooe
ooe
ooe
ooe
ooe
to
to
to
to
to
to
to
to
70°C
70°C
70°C
70°C
70°C
70°C
70°C
70°C
0= PIN NUMBERS
PIN NAMES
1-7
CE,
Ao-A7
00
ADDRESS INPUTS
OUTPUT DISABLE
eE2
Rlw
READ/WRITE INPUT
1101'110 4
CHIP ENABLE 1
CHIP ENABLE 2
DATA INPUT/OUTPUT
SY2t t t
ABSOLUTE MAXIMUM RATINGS
COMMENT
_10°C to +80°C
-65°C to +150°C
Ambient Temperature Under Bias
Storage Temperature
Voltage on Any Pin
With Respect to Ground
Power Dissipation
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device.
This is a stress rating only and functional operation
of the device at these or at any other condition .above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
-0.5V to +7V
1 Watt
D.C. AND OPERATING CHARACTERISTICS
T A; O°C to 70°C, VCC; 5V ±5%, unless otherwise specified.
Symbol
III
ILOH
Parameter
Input Load Current
I/O Leakage Current
ILOL
I/O Leakage Current
ICCl
Power Supply Current
ICC2
Power Supply Current
VIL
VIH
Input Low Voltage
Input HighVoltage
VOL
Output Low Voltage
VOH
Output High Voltage
2111-1
Min. Typ.(1) Max.
10
2111A
2111A-2 2111A-4
Min. Typ.(1) Max.
10
15
-50
10
JlA
-10
JlA
50
mA
55
mA
30
60
30
70
-0.5
2.2
J1,A
Test Conditions
VIN; 0 to 5.25V
CE; 2.2V, VI/O '" 4.0V
CE; 2.2V, VI/O ; 0.45V
VIN; 5.25V
11/0; OmA, TA; 25°C
\fIN; 5.25V
11/0,; OmA, T A; O°C
+0.65
-0.5
+0.8
VCC
2.0
VCC
V
V
0.4
V
10L; 3.2mA
(lOL; 2.0mA - 2111-1)
V
10H ='-150J1,A
Min.
Max.
0.45
2.2
Unit
2.4
NOTES: 1. Typical values are for T A; 25°C and nominal supply voltage.
A.C. CHARACTERISTICS- SY2111-1
T A; O°C to 70°C,VCC; 5V ±5%, unless otherwise specified.
Symbol
Parameter
1
I.
Unit
READ CYCLE
tRCY
tA
tco
too
tDF [1]
tOH
Read Cycle
ns
500
Access Time
Chip Enable To Output
500
ns
350
ns
Output Disable To Output
300
ns
150
ns
Data Output To High Z State
Previous Data Read Valid After Cl)ange Of Address
0
0
ns
WRITE CYCLE
tWCY
tAW
tcw
tow
tDH
twp
tWR
tDS
Write Cycle
Write Delay
Chip Enable To Write
Data Setup
Data Hold
Write Pulse
Write Recovery
Output Disable Setup
500
100
400
280
100
ns
ns
ns
300
50
20
. ns
ns
ns
NOTE: 1. tOF is with respect to the trailing edge of CE1! CE2, or 00, whichever comes first.
HI
ns
ns
SY2ttt
A.C. CHARACTERISTICS - SY2111A-2
TA = O°C to 70°C, VCC= 5V ±5%, unless otherwise specified.
Symbol
I
Parameter
Min.
Max.
Unit
READ CYCLE
tRCY
tA
Read Cycle
Access Time
250
250
ns
tco
Chip Enable To Output
ns
too
tDF[1]
Output Disable To Output
180
130
180
tOH
Previous Data Read Valid After Change Of Address
40
ns
ns
Data Output To High Z State
0
ns
ns
WRITE CYCLE
twCY
Write Cycle
250
ns
tAW
Write Delay
20
ns
tcw
Chip Enable To Write
150
ns
tow
Data Setup
150
ns
tDH
twp
Data Hold
0
ns
Write Pulse
150
ns
0
20
ns
Write Recovery
tWR
tDS
Output Disable Setup
ns
A.C. CHARACTERISTICS - SY2111A
T A = O°C to 70°C, VCC = 5V ±5%, unless otherwise specified.
Symbol
I
Min.
Parameter
Max.
Unit
READ CYCLE
Read Cycle
ns
350
tRCY
tA
Access Time
350
ns
tco
Chip Enable To Output
240
ns
too
tDF [1]
Output Disable To Output
180
ns
150
ns
tOH
Previous Data Read Valid After Change Of Address
Data Output To High Z State
0
40
ns
WRITE CYCLE
tWCY
Write Cycle
350
ns
tAW
Write Delay
20
ns
tcw
Chip Enable To Write
Data Setup
200
ns
200
ns
ns
tow
tDH
twp
Data Hold
0
Write Pulse
200
ns
tWR
Write Recovery
0
ns
20
ns
tDS
. Output Disable Setup
NOTE: 1. tDF is with respect to the trailing edge of CE1, CE2, or 00, whichever comes first.
1-9
SY21 1 1
A.C. CHARACTERISTICS - SY2111A·4
T A = O°C to 70°C, VCC = 5V ±5%, unless otherwise specified.
Symbol
I'
'Max.
Min.
Parameter
Unit
READ CYCLE
450
tRCY
Read Cycle
tA
Access Time
teo
Chip Enable To Output
too
tDF [1]
tOH
'ns
450
310
250
200
' Output Disable To Output
Data Output To High Z State
0
Previous Data Read Valid After Change ()f Address
ns
ns
ns
ns
40
WRITE CYCLE
tWCY
Write Cycle
450,
ns
tAW
Write Delay
20
ns
tcw
Chip Enable To Write
ns
tDW
Data Setup
250
. 250
tDH
Data Hold
0'
twp
Write Pulse
250
ns
tWR
Write Recovery
0
ns
tDS
Output Disable Setup
20
ns
A.C. CONDITIONS OF TEST
,
ns
"
ns
2111·1
2111A, 2111A'2, 2111A·4
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . , +0.8V to 2.0V . . . . . . . . . . . . +0.65V to 2.2V
Input Pulse Rise & Fall Times: . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns . . . . . . . . . . . . . . . . . . . 10ns
Timing Measuremnt Reference Level
Inputs: . . . . . . . . . . . . . . . 1.5V .. ' ... : .... ; . . . . . . . . 1.5V
Outputs: . . . . . . . . . 0.8V & 2.0V . . . . . . . . . . . . . . 0.8V & 2.0V
Output Load: . . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate & CL = 100pF ..... 1 TTL Gate & CL = 100pF
CAPACITANCE T A = 25°C f = 1 MHz
Symbol
CIN
COUT
Test
Input Capacitance (All Input Pins) VIN = OV
Output Capacitance VOUT = OV
Typ.
Max
Unit
4
10
8
15
pF
pF
TIMING DIAGRAMS
READ CYCLE
WRITE CYCLE
tRCy-----_1
ADDRESS
1_-----tWCy
ADDRESS
CHIP
ENABLES
~'~
____________________
CHIP
ENABLES
ICE, CEzl
OUTPUT
DISABLE
DISABLE
OUTPUT
DATA 1/0
tA_
-------~~------------~
DATA
OUT_
VALID
__ - - ___ ...11'_ _
__
_ _ _; -
DATA 1/0
READ/-+----"\I
NOTE: 1. tOF is with respect to the trailing edge of CE1, CE2
or OD, whichever comes first.
WRITE
1-10
JI~_
256 x 4 Static. Rarmdom
SY2t 12
Access Memory
ME.MORY
PRODUCTS
SYNERTEK
A SUBSIDIARY OF HONEYWELL
Organization 256 Words by 4 Bits
Common Data Input and Output
Single +5V SupplyVoltage
Directly TTL Compatible - All Inputs and Outputs
Static MOS - No Clocks or Refreshing Required
Access Time - 250/350/450/500 ns
Simple Memory Expansion - Chip Enable Input
o Fully Decoded - On-Chip Address Decode
o Inputs Protected - All Inputs Have Protection
Against Static Charge
II Low Cost Packaging - 16 Pin Plastic Dual-I n-Line
Configuration
o Low Power - Typically 150 mW
o Three-State Output - OR-tie Capability
The SY2112 is a 256 word by 4 bit static random
access memory element using N-channel MOS devices
integrated on a monolithic array_ It uses fully DC
stable (static) circuitry and therefore requires no clocks
or refreshing to operate. The data is read out nondestructively and has the same polarity as the input data.
Common input/output pins are provided.
Enable lead allows easy selection of an individual
package when outputs are OR-tied.
III
o
o
o
o
o
o
The SY2112 is fabricated with ion implanted Nchannel silicon gate technology. This technology
allows the design and production of high performance,
easy-to-use MOS circuits and provides a higher functional density on a monolithic chip than either conventional MOS technology or N-channel silicon gate
technology.
The SY2112 is designed for memory applications in
small systems where high performance, low cost,
large bit storage, and simple interfacing are important
design objectives.
Synertek's ion implanted silicon gate technology also
provides excellent protection against contamination.
This permits the use of low cost plastic packaging.
It is directly TTL compatible in all respects: inputs,
outputs, and a single +5V supply. A separate Chip
PIN
CONFIGURATION
A3
BLOCK DIAGRAM
AO
Vec
A4
A2
A1
@)
~-=-,-...-,
---<>Vcc
A,
'®OGND
~=.-,-...-,
ROW
R/W
A3
CE
A5
MEMORY ARRAY
32 ROWS
32 COLUMNS
1/04
A6
1/03
A7
1/02
GND
I/O,
1/0'0....:::;................
1/02
1/03 - __ T I ,,_"'--'
1/04
ORDERING INFORMATION
Order
Number
SYP2112A-2
SYD2112A-2
SYP2112A
SYD2112A
SYP2112A-4
SYD2112A-4
SYP2112-1
SYD2112-1
Package
Type
Access
Time
Plastic DIP
Cerdip
Plastic DIP
Cerdip
Plastic Dip
Cerdip
Plastic DIP
Cerdip
250nsec
250nsec
350nsec
350nsec
450nsec
45Dnsec
5DDnsec
500nsec
Temperature
Range
O'C to
D'C to
D'C to
O'C to
D'C to
D'C to
D'C to
D'C to
70'C
70'C
70'C
70'C
70'C
70'C
70'C
70'C
0" PIN NUMBERS
PIN NAMES
AO·A7
RIW
CE
1/0,·1/04
Vcc
1-11
ADDRESS INPUTS
READ/WRITE INPUT
CHIP ENABLE INPUT
DATA INPUT/OUTPUT
POWER 1+5V)
SY2112
ABSOLUTE MAXIMUM R.ATINGS*
*COMMENT
_10°C to +80°C
-65°C to +150°C
Ambient Temperature Under Bias
Storage Temperature
Voltage On Any Pin
With Respect to G rou nd
Power Dissipation
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device.
This is a stress rating only and functional operation
of the device at these or at any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
-0.5V to +7V
1 Watt
D. C. AND OPERATING CHARACTERISTICS - SY2112A, SY2112A-2, SY2112A-4
T A = O°C to 70°C, VCC = 5V ±5% unless otherwise specified
Symbol
Parameter
Min.
III
Input Current
ILOH
ILOL
I/O Leakage Current
I/O Leakage Current
ICCl
Power Supply Current
ICC2
Power Supply Current
VIL
Input "Low" Voltage
VIH
Input "High" Voltage
VOL
Output "Low" Voltage
VOH
Output "High" Voltage
NOTES: 1. Typical values are for TA
Typ. (1)
Max.
10
10
-10
Unit
/lA
/lA
Test Conditions
= 0 to 5.25V
CE = 2.2V, VI/O = 4.0V
CE = 2.2V, VI/O = 0.45V
VIN = 5.25V, 11/0 = OmA
TA = 25°C
VIN = 5.25V, 11/0 = OmA
TA = O°C
VIN
50
/lA
mA
55
mA
-0.5
+0.8
V
2.0
VCC
+0.4
V
10L = 3.2mA
V
10H
30
2.4
V
= -150/lA
= 25°C and nominal supply voltage.
D. C. AND OPERATING CHARACTERISTICS - SY2112-1
T A = O°C to 70°C, VCC = 5V ±5% unless otherwise specified.
Symbol
Min.
Parameter
Typ. (1)
Max.
III
Input Current
10
/lA
ILOH
I/O Leakage Current
15
/lA
-50
60
/lA
mA
70
mA
ILOL
I/O Leakage Current
ICCl
Power Supply Current
ICC2
Power Supply Current
VIL
Input "Low" Voltage
-0.5
+0.65
V
VIH
Input "High" Voltage
2.2
V
VOL
Output "Low" Voltage
VCC
+0.45
VOH
Output "High" Voltage
NOTES: 1. Typical values are for T A
30
2.2
= 25°C and nominal supply voltage.
1-12
Test Conditions
Unit
= 0 to 5.25V
= 2.2V, VI/O = 4.0V
CE = 2.2V, V I/O = 0.45V
VIN = 5.25V, 11/0 = OmA
TA = 25°C
VIN = 5.25V, 11/0 = OmA
TA = O°C
VIN
CE
V
10L = 2mA
V
10H
= -150/lA
SY1111
A. C. CHARACTERISTICS - SY2112A-2
READ CYCLE TA = ODC to 70DC, VCC = 5V ±5% unless otherwise specified.
Symbol
Parameter
Min.
Max.
Unit
tRCY
tA
Read Cycle
Access Time
250
ns
ns
tco
Chip Enable to Output Time
180
ns
tCD
Chip Enable to Output Disable Time
0
120
ns
tOH
Previous Read Data Valid After Change
40
250
ns
of Address
WRITE CYCLE NO.1 T A = ODC to 70DC, VCC
= 5V ±5%
Symbol
Parameter
Min.
tWCYl
tAW 1
Write Cycle
Address to Write Setup Time
250
ns
20
ns
tDWl
Write Setup Time
180
ns
tWPl
Write Pulse Width
180
ns
tCSl
Chip Enable Setup Time
0
tCHl
Chip Enable Hold Time
0
ns
tWRl
Write Recovery Time
0
ns
tDHl
tCWl
Data Hold Time
Chip Enable to Write Setup Time
0
180
ns
ns
Max.
100
Unit
ns
WRITE CYCLE NO.2 T A = ODC to 70DC, VCC = 5V ±5%
Symbol
Parameter
Min.
Max.
Unit
tWCY2
Write Cycle
250
ns
tAW2
Address to Write Setup Time
20
ns
tDW2
Write Setup Time
180
120
ns
tWD2
Write To Output Disable Time
tCS2
Chip Enable Setup Time
0
ns
tCH2
Chip Enable Hold Time
0
ns
tWR2
Write Recovery Time
0
ns
tDH2
Data Hold Time
0
ns
100
ns
A. C. CHARACTERISTICS - SY2112A
READ CYCLE TA = ODC to 70 DC, VCC = 5V ±5% unless otherwise specified.
Symbol
tRCY
tA
Parameter
Min.
Max.
350
Read Cycle
tco
Access Time
Chip Enable to Output Time
tCD
Chip Enable to Output Disable Time
0
tOH
Previous Read Data Valid After Change
40
of Address
1-13
Unit
ns
350
240
ns
200
ns
ns
ns
SY2112
A. C. CHARACTERISTICS - SY2112A (Cont.)
WR ITE CYCLE NO.1 T A =O°C to 70°C. VCC = 5V ±5%
Symbol
Parameter
Write Cycle
Address to Write Setup Time
Min.
350
20
Unit
ns
ns
tDW1
tWP1
Write Setup Time
250
ns
Write Pulse Width
250
tCS1
Chip Enable Setup Time
0
tCH1
tWR1
tDH1
Chip Enable Hold Time
Write Recovery Time
0
0
tCW1
Chip Enable to Write Setup Time
tWCY1
tAW 1
Data Hold Time
Max.
ns
100
ns
0
ns
ns
ns
250
ns
WRITE CYCLE NO.2 TA = (j°C to 70°C. VCC = 5V ±5%
Symbol
Min.
Parameter
Max.
Unit
tWCY2
tAW2
Write Cycle
350
Address to Write Setup Time
20
tDW2
Write Setup Time
tWD2
tCS2
Write To Output Disable Time
Chip Enable Setup Time
250
200
0
ns
tCH2
Chip Enable Hold Time
0
ns
tWR2
Write Recovery Time
0
tDH2
Data Hold Time
0
ns
ns
ns
ns
ns
130
ns
A. C. CHARACTERISTICS - SY2112A-4
READ CYCLE TA = O°C to 70°C. VCC'; 5V ±5% unless otherwise specified.
Symbol
tRCY
tA
Parameter
Min.
Read Cycle
Max.
450
tco
Access Time
Chip Enable to Output Time
tCD
Chip Enable to Output Disable Time
tOH
Previous Read Data Valid After Change
of Address
0
40
Unit
ns
450
ns
200
260
ns
Max.
Unit
ns
ns
WRITE CYCLE NO.1 TA = O°C to 70°C. VCC = 5V ±5%
Symbol
Parameter
tWCY1
Write Cycle
tAW1
tDW1
Address to Write Setup Time
Write Setup Time
tWP1
tCS1
tCH1
Write Pulse Width
Chip Enable Setup Time
Chip Enable Hold Time
Write Recovery Time
tWR1
tDH1
tCW1
Min.
450
20
ns
ns
300
300
ns
0
0
Data Hold Time
Chip Enable to Write Setup Time
1-14
0
0
300
100
ns
ns
ns
ns
ns
ns
A. C. CHARACTERISTICS - SY2112A-4 (Cont.)
WRITE CYCLE NO.2 T A = o°c to 70°C, VCC = SV ±S%
Symbol
Parameter
Min.
tWCY2
tAW2
Write Cycle
Address to Write Setup Time
450
tDW2
tWD2
tCS2
tCH2
Write Setup Time
Write To Output Disable Time
Chip Enable Setup Time
Chip Enable Hold Time
tWR2
Write Recovery Time
0
ns
ns
tDH2
Data Hold Time
0
ns
Max.
Unit
ns
ns
20
300
2&0
ns
ns
ns
150
0
0
A. C. CHARACTERISTICS - SY2112·1
READ CYCLE TA = O°C to 70°C, VCC = SV ±S%, unless otherwise specified.
Symbol
Parameter
Min.
Read Cycle
Max.
Unit
t r , tf ";;20ns
0.6SV;" VIN;" 2.2V
Test Conditions
tRCY
tA
Access Time
500
ns
ns
tco
Chip Enable To Output Time
Chip Enable To Output Disable Time
0
ns
ns
Timing Reference
tCD
3S0
1S0·
tOH
Previous Read Data Valid After Change
of Address
0
ns
CL
SOO
Load
= 1.5V
= 1 TTL Gate
= 100pF
WRITE CYCLE NO.1 T A = O°C to 70°C, VCC = SV ±S%
Symbol
Parameter
tWCY1
Write Cycle
tAW1
Address To Write Setup Time
Write Setup Time
tDW1
tWP1
tCS1
tCH1
tWR1
tDH1
tCW1
Min.
Chip Enable Setup Time
Chip Enable Hold Time
Write Recovery Time
0
100
Test Conditions
t r , tf ";;20ns
0.65V;" VIN;" 2.2V
= 1.SV
= 1 TTL Gate
Timing Reference
ns
Load
ns
CL = 100pF
ns
ns
Data Hold Time
Chip Enable to Write Setup Time
200
ns
ns
= OoC to 70°C, VCC = SV ±S%
Parameter
Min.
tWCY2
Write Cycle
SOO
tAW2
Address To Write Setup Time
Write Setup Time
100
200
100
tCS2
ns
ns
0
SO
100
Symbol
tCH2
tWR2
tDH2
Unit
ns
200
300
Write Pulse Width
WRITE CYCLE NO.2 TA
tDW2
tWD2
Max.
SOO
100
Write To Output Disable Time
Chip Enable Setup Time
Write Recovery Time
Data Hold Time
1-1S
Unit
Test Conditions
ns
ns
tr, tf ";;20ns
0.65V.;" VIN;" 2.2V
ns
ns
Timing Reference
ns
ns
CL = 100pF
0
SO
100
ns
ns
0
Chip Enable Hold Time
Max.
Load
= 1.SV
= 1 TTL Gate
SY2112
READ CYCLE WAVEFORMS
CAPACITANCE
1~--------tRCY--------~
Symbol
Test
Input Capacitance
CIN
CI/O
WRITE CYCLE #1
TA
(All Input Pins) VIN = OV
I/O Capacitance V I/O = OV
WR ITE CYCLE #2
= aOe to 7aoe, vee = 5V±5%
TA
Limits (pF)
Typ.
Max.
4
8
10
18
= aOe to 7aoe, Vee = 5V±5%
NOTE 1. Data Hold Time. (TOH) is reference to the trailing edge of CHIP
ENABLE (GE}or READIWRITE (R/W) whichever comes first.
A.C. CONDITIONS OF TEST
0.8 to 2.0 Volt
. .... 10 nsec
. . . . . . . . 1.5 Volt
. .... 0.8 and 2.0 Volt
.. 1 TTL Gate and CL = 100 pF
Input Pulse Leads . . . . . . . . : .. .
Input Pulse Rise and Fall Times .. .
Timing Measurement Reference Level: Input .
Output .
Output Load . . . . . . . . .
PACKAGE DIAGRAM
CERDIP PACKAGE
PLASTIC PACKAGE
P"~~~T --?: : : : : : : :1 ~~ :~:~~!:TI.
1
0.060 (1.524)
Ij--- 0.780 119.8121 MAX --jI
38
I
!!
I I
,..-I
~~~!g :;:~~:l
'1
~EI ~
=t -,-JI. ~'508l· :g~~i:
0.615 I O1)L ·m T I 1 W : .
-I
1~
0.180
0.140 (3.556)
I
0.125 13.175}
f..-- ---I
~.
g:g~g :~:;~~l
g:g~; :g:;~~:
I
0.015
0.008
!
!
--J
t
I
0.400 110.16}
I
0.330 {a3B2) - - -
1-16
1024 x4 Static Random
Access Memory
SYNf.RTf.~
SY2114
MEMORY
PRODUCTS
A SUBSIDIARY OF HONEYWELL
• 150 ns Maximum Access
Low Operating Power Dissipation
0.1 mW/Bit
'-~
Vee" 5V
300
1.
............. ~
:!
1.0
200
0.5
200
o
150
20
40
60
80
100
o
40
TA ICI
60
80
100
TA ICI
CERDIP PACKAGE
MOLDED PACKAGE
0.320
0.290
18.1281
17.3661
0.310
~ 0.900 (22.860) MAX---l
0.060 I 1.5241.r:;::::::::::::::::=====:::::j ~o.;;iO(4.57:
r"¥WWWW,:;.;:::===
0.260
17.8741
[6.604j
--
I
~ ~ ~ -I~"""'-'--
-! .
0.11012.7941 0.07011.7781
0.02310.5841
0.090 (2.286) '0.030 (0,762)
0.015 {a.38ll
1-24
100
200
300
CL IpFI
PACKAGE DIAGRAM
0",
4.5
TA lei
400
500
600
2048 x 8 Static Random
Access Memory
SY2128
MEMORY
PRODUCTS
SYNERTEK
PRELIMINARY
A SUBSIDIARY OF HONEYWELL
• 120nsec Maximum Access Time
• Fully Static Operation:
No Clocks or Strobes Required
• Automatic CE Power Down
• Identical Cycle and Access Times
• Single +5V Supply (± 10%)
• Pin Compatible with 2716 16K EPROM
• Totally TTL Compatible:
All Inputs and Outputs
• Common Data Input and Output
• Three-State Output
• JEDEC Approved Pinout
The Synertek SY2128 is a 16,384 bit static
Random Access Memory organized 2048 words
by eight bits and is fabricated using Synertek's
new scaled n-channel silicon gate technology. It
is designed using fully static circuitry, therefore
requiring no clock or refreshing to operate. The
common data input and three-state output pins
optimize compatibility with systems utilizing a
bidirectional data bus.
chip, the device will automatically power down
and remain in a standby power mode as long as
CE remains high. This feature provides significant system level power savings.
The SY2128 is configured in the JEDEC
approved pinout for 24 pin byte organized
memories and is pin compatible with 16K
ROMs, EPROMs and EEPROMs. This offers the
user the flexibility of being able to switch
. between RAM, ROM, EPROM, or EEPROM as his
needs dictate with a minimum of board changes.
The SY2128 offers an automatic power down
feature under the control of the chip enable
(CE) input. When CE goes high, deselecting the
PIN CONFIGURATION
BLOCK DIAGRAM
Vee
As
Ag
WE
DE
Ao
A3
As
A6
A,
As
A,
DECODER
A,
A,
A,
AlO
COLUMN
ADDRESS
DECODER
DRIVER
ROW
ADDRESS
16.384 BIT ARRAY
(128 x 128)
DRIVER
AlO
A,
CE
I/OS
I/O,
I/O,
1/0 3
GND
1/0 7
1/0 6
1/05
I/O,
WE
CE
.>--::--+t+t-t-H-t-- I/O,
L7--t-l =~t-I-f-H+--I/O,
>I-7--t+ttH+-1/03
L-..-7--+-I
I/O 4
>l....::....-f-~+--1/05
L-..--:--+Drl---~r----- 1/0 6
>1-7,---<+-1/0,
' - - - - - - H .>-t----+..-
DE
1-25
liDs
1024 x 4 Stadc Random
Access Memory
SY2142
MEMORY
PRODUCTS
SYNERTE~
A SUBSIDIARY OF HONEYWELL
• 200ns Maximum Access
• Low Operating Power Dissipation
0.1 mW/Bit
• Totally TTL Compatible:
All Inputs, Outputs, and Power Supply
The 2142 is a 4096-bit static Random Access
Memory organized 1024 words by 4-bits and is fabricated using Synertek's N-channel Silicon-GateMOS
technology. It is designed using fully DC stable (static)
circuitry in both the memory array and the decoding
and therefore requires no· clock or refreshing to
operate. Address setup times are not required and
the data is read out nondestructively with the same
polarity as the input data. Common Input/Output
pins are provided to simplify design of bus oriented
systems, and the outputs can drive 2 TTL loads.
The SY2142 is designed for memory applications
where high performance, low cost, large bit storage,
and simple interfacing are important design objectives. It is totally TTL compatible in all respects:
inputs, outputs, and the single +5V supply.
Two Chip Selects (CS 1 and CS 2 ) are provided to
simplify systems where memory expansion' is
implemented by OR-tying several 2142's. Also an
Output Disable directly controls the output stages.
The SY2142 is packaged in a 20-pin DIP and is
fabricated with N-channel, Ion Implanted, SiliconGate technology - a technology providing excellent
performance characteristics as well as protection
against contamination allowing the use of low cost
packaging techniques.
PIN CONFIGURATION
A6
Vee
A5
A7
A,
A.
A3
Ag
CS2
00
Ao
I/O,
A,
1/02
A2
1/0 3
CS,
I/O,
GNO
WE
Common Data 1/0
400mv Noise Immunity
High Density 20 Pin Package
Two Chip Selects and Output Disable
Functions Simplify Memory Expansion
•
•
•
•
• No Clocks or .Strobes Required
• Identical Cycle and Access Times
• Single +5V Supply
BLOCK DIAGRAM
AO
GNO
A2
A4
ORDERING INFORMATION
.-
A5
Supply
SYD2142
SYP2142
SYD2142-3
SYP2142-3
SYD2142l
SYP2142L
SYD2142L-3
SYP2,142L-3
SYD2142-2
SYP2142-2
SYD2142L-2
SYP2142L-2
Paotage
Type
Cerdip
Plastic
Cerdip
Plastic
Cerdip
Plastic
Cerdip
Plastic
Cerdip
Plastic
Cerdip
Plastic
MEMORY ARRAY
64 ROWS
A3
Order
Number
Vee
A,
Acces.
Tir:ne
Current
(Max)
Temperature
Range
450ns8c
450nsee
300nsee
300nsec
450nsee
450nsee
300nsec
300nsec
200nsec
200nsec
200ns8e
200nsee
100mAmp
100mAmp
100mAmp
100mAmp
70mAmp
70mAmp
70mAmp
70mAmp
100mAmp
100mAmp
70mAmp
70mAmp
O'C to 70'C
O'C to 70'C
1/0 1
1/°2
ooe to 70°C
1/°3
O'C to 70'C
O'C to 70'C
O'C to 70'C
1/°4
aae to 70°C
O'C io 70'C
O'C to 70'C
ooe to 70°C
O'C to 70'C
O'C to 70'C
CS,
es,
WE
00
1-26
64 COLUMNS
SY2t42
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature Under Bias ......... -10°C to 80°C
Storage Temperature ........... -65°C to 150°C
Voltage on Any Pin with
Respect to Ground .............. -0.5V to +7V
Power Dissipation ........................ 1.0W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the.
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied.
D.C. CHARACTERISTICS TA = O°C to +70°C, VCC = 5V ±5% (Unless Otherwise Specified)
2142,2142-2
2142·3
Symbol
Parameter
Min
2142L,2142L·2
2142L·3
Max
Min
Unit
VIN
CS = 2.0V,
V I/O = OAV to VCC
VCC - 5.25V, 11/0 - 0 mA,
TA = 25°C
VCC - 5.25V, 11/0 - 0 mA,
TA = O°C
10
10
ILO
Input Load Current
(All input pins)
I/O Leakage Current
p.A
10
10
p.A
ICC1
Power Supply Current
95
65
mA
ICC2
Power Supply Current
100
70
mA
VIL
VIH
VOL
VOH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-0.5
2.0
0.8
VCC
204
VCC
V
V
V·
V
III
-0.5
2.0
0.8
VCC
204
VCC
004
Conditions
Max
004
= 0 to 5.25V
10L - 3.2 mA
10H = -1.0 mA
CAPACITANCE T A = 25°C, f = 1.0 MHz
Symbol
CI/O
CIN
Typ
Test
Max
Units
5
5
pF
pF
Input/Output Capacitance
Input Capacitance
NOTE: This parameter is periodically sampled and not 100% tested.
A.C. CHARACTERISTICS TA = O°c to 70°C, VCC = 5V ±5% (Unless Otherwise Specified)
2142·2,2142L·2·
Symbol
Parameter
Min ..
Max.
2142·3,2142L·3
Min.
Max.
2142,2142L
Min.
Max.
Unit
READ CYCLE
tRe
tA
tOD
tODX
teo
tex
tOTD
tOHA
Read Cycle Time
Access Time
Output Enable to Output Valid
Output Enable to Output Active
Chip Selection to Output Valid
Chip Selection to Output Active
Output 3·state from Disable
Output Hold from Address Change
200
Write Cycle Time
Address to Write Setup Time
Write Pulse Width
Write Release Time
Output 3·state from Disable
Data to Write Time Overlap
Data Hold from Write Time
200
0
120
0
0
120
0
300
200
70
450
300
100
20
20
70
20
0
50
60
450
120
20
120
100
20
0
50
80
20
0
50
100
ns
ns
ns
ns
ns
ns
ns
ns
W RITE CYCLE
twe
tAW
tw
tWR
tOTD
tDW
tDH
300
0
150
0
80
60
150
0
See following page for A.C. Test Conditions
1-27
450
0
200
0
100
200
0
ns
ns
ns
ns
ns
ns
ns
SY2142
A.C. Test Conditions
Input Pulse Levels ....................................................................... O.8V to 2.0V'
Input Rise and Fall Time ....................................'................................... 10nsae
Timing Measurement Levels: Input .......... , ..........................................". . . . .. . .. .. 1.5V
Output ..........' •.....................,.................. ".: O.8V and 2.0V
Output Load ............................................'......................... 1TTL Gate and 100pF
TIMING DIAGRAMS
Read Cycle!1]
'RC
'A
ADDRESS
00
~
,N'x
I--'- '00 - ; - "
I--tooxAN'
,)<.lV'..
0A
CS2
;w<,
~
~'co~'cx
___
I---
~+=l
tOHA
~
Write Cycle[2]
twc
ADDRESS
twR
-~
00
!--'OTO ....
~
CS2
~~
~
~
~
.lVVVVV<" i.>V<.
tw
~~
[31
'AW
H
DOUT
DIN--------'-{E----,l~~~·
'OW.,--oo I--'OH
NOTES:
1. A Read occurs during the overlap of a low
cs;; high CS2 and a high WE.'
2. A Write occurs during the overlap of a low CS1. high CS2 and a low WE.
3. WE must be high during all address transitions.
1-28
SY2142
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
VS VOLTAGE
120,---r---,---,:----Y---,
SUPPLY CURRENT
VS TEMPERATURE
120
A1
I/Oz
A a - - - . . . I .....
Az
1/03
cs
1/0 4
Ao
GND
A,
WE
ORDERING INFORMATION
Order
Number
SYC2148H
SYD2148H
SYC2148H-2
SYD2148H-2
SYC2148H-3
SYD2148H-3
SYC2148HL
SYD2148HL
SYC2148H L-3
SYD2148HL-3
Access Operating
Time
Current
(Max)
(Max)
70ns
70ns
45ns
45ns
55ns
55ns
70ns
70ns
55ns
55ns
150mA
150mA
150mA
150mA
150mA
150mA
125mA
125mA
125mA
125mA
Standby
Current
(Max)
30mA
30mA
30mA
30mA
30mA
30mA
20mA
20m A
20mA
20mA
Package
Type
Ceramic
Cerdip
Ceramic
Cerdip
Ceramic
cs
---.--<>r-'
Cerdip
Ceramic
Cerdip
Ceramic
WE -----I_oJ
Cerdip
1-40
MEMORY ARRAY
64 ROWS
64 COLUMNS
SY2148H
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature Under Bias
· . -10°C to 85°C
Storage Temperatu re . . .
· -65°C to 150°C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied.
Voltage on Any Pin with
Respect to Ground ..
-3.5V to +7V
Power Dissipation
· .......
D.C. CHARACTERISTICS
1.0W
TA = OOeto +70 o e, VCC = 5V ±10% (Unless otherwise specified) (note 8)
2148H/H·2/H·3
Symbol
Min.
Parameter
2148HL/HL·3
Max.
Min.
Max.
Unit
Conditions
III
Input Load Current
I All input pins)
10
10
I'A
VCC = Max, VIN = Gnd to VCC
ILO
Output Leakage Current
50
50
I'A
CS = VIH, VCC = Max
VOUT = Gnd to 4.5V
ICC
Power Supply Current
140
150
115
125
rnA
rnA
TA=25°C
TA =OoC
I Vcc=Max,CS=VIL
I Outputs Open
ISB
Standby Current
30
20
rnA
VCC = Min to Max, CS = VIH
IpO
Peak Power·on Current
50
30
rnA
VCC = Gnd to VCC Min
CS = Lower of VCC or VIH Min
V
Note 9
VIL
Input Low Voltage
-3.0
0.8
-3.0
0.8
VIH
Input High Voltage
2.1
6.0
2.1
6.0
V
VOL
Output Low Voltage
0.4
V
IOL =8mA
VOH
Output High Voltage
V
IOH= -4mA
0.4
2.4
2.4
CAPACITANCE
Symbol
Test
Typ.
Max.
Unit
COUT
Output Capacitance
7
pF
CIN
Input Capacitance
.5
pF
NOTE:
This parameter is periodically sampled and not 100% tested.
A.C. CHARACTERISTICS
TA = oOe to +70 o e, VCC = 5V ±10% (Unless otherwise specified) (note 8)
READ CYCLE
2148H·2
Symbol
tRC
Parameter
Read Cycle Time
Min.
Max.
45
2148H·3/H L·3
Min.
Max.
55
2148H/HL
Min.
Max.
Unit
70
Conditions
tAA
Address Access Time
45
55
70
ns
ns
tACSl
Chip Select Access Time
45
55
70
ns
Note 1
tACS2
Chip Select Access Time
55
60
80
Note 2
tOH
Output Hold from Address Change
5
ns
ns
tLZ
Chip Selection to Output in Low Z
20
ns
Note 7
tHZ
Chip Deselection to Output in High Z
0
20
ns
Note 7
tpu
Chip Selection to Power Up Time
0
tpD
Chip Deselection to Power Down Time
30
ns
5
5
20
20
0
20
20
0
30
0
0
30
ns
WRITE CYCLE
twc
Write Cycle Time
45
55
70
ns
tew
Chip Selection to End of Write
40
50
65
ns
ns
ns
tAW
Address Valid to End of Write
40
50
65
tAS
twp
Address Setup Time
0
0
0
Write Pulse Width
35
40
50
tWR
Write Recovery Time
5
5
5
ns
ns
ns
tow
Data Valid to End of Write
20
20
25
tDH
Data Hold Time
0
0
0
twz
Write Enabled to Output in High Z
0
tow
Output Active from End of Write
0
15
0
0
20
0
0
25
ns
ns
Note 7
ns
Note 7
(See follOWing page for notes)
1-41
SY2t48H
TIMING DIAGRAMS
READ CYCLE NO.1 (NOTES 3AND 4)
AD~~S~~~~~~tR~C~~~~~
~ ~ V-I-O-U~S~D~A=T-~-O-:=A=L-I:_A - _-_-~ -I- )(- -)(- ~ ~- - - - - - - -D-A-T-A-V-A-L-I-D- - - - - - - - - - - __
DATA OUT
READ CYCLE NO.2 (NOTES 3AND 5)
tRC
~
tACS
r---tHZ~
·ttZ
HIGH IMPEDANCE
DATA OUT
~~~PLY
m~r--
XX
HIGH
DATA VALID
t-
IMPEDANCE
~tpo
I+-tpu
IICSCBm
CURRENT
J
=1
_____________________
~
WRITE CYCLE NO.1 (WE CONTROLLED) (NOTE 6)
twc
ADDRESS
~
---.J
.
tcw
LL~
\
tAS
-J
tAW
twp
J
IIII
I--- tWR ----
~L\
tow
DATA IN
tOH---'
DATA VALID
"C
---twz-
DATA OUT
.
i----tow----HIGH IMPEDANCE
DATA UNDEFINED
NOTES: 1. Chip deselected f~r greater than 55n5 prior to selection.
2. Chip deselected for a finite time that is less than 55n5 prior to selection. (If the deselect time is Ons, the chip is by
definition selected and access occurs according to Read Cycle No.1 J
3. WE is high for Read Cycles.
4. DeVice is continuously selected,
CS = V,L'
5. Addresses valid prior to or coincident with CS transition low.
6. If CS goes high simultaneously with WE high, the outputs remain in the high impedance state,
7. Transition is measured ±500mV from low or high impedance voltage with load B. This parameter is sampled and not 100% tested.
8. The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute.
9. A pullup resistor to Vee on the CS input is required to keep the device deselected: otherwise, power-on current approaches Icc active.
1-42
SY2148H
WRITE CYCLE NO.2 (CS CONTROLLED) (NOTE 6)
twe
.~
ADDRESS
-.I
i--tAS
.
tew
,~
~
tAW
!--twR---oo
tw.
'\
\ \ \ \ \ \ \ \ \ \
-,
tow
DATA IN
-}
////////,
tOH-
f-
DATA VALID
DATAOUT-------------------D-A-T-A-U-N-D-E-FI-N-ED-------------~~----~H~I~G~H~IM~P~E~D~A~NC~E~
"':"---twz
__________________
<5V
A.C. TEST CONDITIONS
480U
480U
GND TO 3.0 VOLTS
INPUT PULSE LEVELS
+5V
INPUT RISE AND FALL
TIMES
10nsec
INPUT AND OUTPUT
1.5 VOLTS
DOUl ----+---'-~
DOUl ~-~-+--~
30 pF
!iNCLUDING
SCOPE AND
JIGI
255n
TIMING REFERENCE
LEVELS
5 pF
25511
SEE LOAD A.
OUTPUT LOAD
LOADA.
LOAD B.
PACKAGE DIAGRAMS
CERDIP PACKAGE
CERAMIC PACKAGE
1.910'
3
j
tE
'1_ '_1
1.870)
'490
1.400)
r:::7.l : : : :: : :]
PIN NO.1
IDENT
~j-l~
I
_I I _
I
(.110)
1.0901
1.1,
I loiffii
~~
1 - . 9 0 0 (22.8601 MAX-/
!I
(.060)
t.020)
.180 (4.5721
.060(1.5241~~~61
~
015(3811
wi
t
--mar-I
(.320)
-I 1-
r ,01~(3811
-L
-11- .200 (5.0 81
.070 (1.7781.023 (5841.125 (3.1751
.110 (2.7941
090 (2,2861 ,030 (.7621 .015 (.3811
(.021)
(1i'15i
.032 REF.
1-43
H:==~
-
I
,008 (.203)
.400 (10.161
330 (8.382)
~
SYM2148
Military.024 x4 Static·
Random Access Memory
MEMORY'
PRODUCTS
Extended Temperature
SYNERTEIt Range (-55°C 'to' + t 25° C)
PRELIMINARY
A SUBSIDIARY OF HONEYWELL
"
"
"
..
I
III
• Industry Standard 2114 Pinout
• Totally TTL Compatible All Inputs and Outputs
• Common Data Input and Output
• High Density.18,Pin Package
• Three-State Output
70 ns Maximum Access
No Clocks or Strobes Required
Automatic CS Power Down
Identical Cycle and Access. Times
Single +5V Supply (±10%)
The Synertek SYM2148 is a 4096-Bit Static Random
Access Memory organized 1024 words by 4 bits and
is fabricated using Synertek's new N-Channel SiliconGate HMOS ,technology, It is designed using fully static circuitry, therefore requiring no clock or refreshing
to operate. Address set-up times are not required and
the data is read out non-destructively with the sarne
polarity as the input data. Common data input and
output pins provide maximum design flexibility.The
three-state output facilitates memory expansion by
allowing the outputs to be OR-tied to other devices.
The SYM2148 offers an automatic power'downfeature_ 'Power down is controlled by the Chip Select
input. When Chip Select (CS) goes high, thus de.
selecting the SYM2148, the.device will automatically
power down and remain, in a standby power mode as
long as CS remains high. This unique feature provides
system level power savings as much as 85%.
The SYM2148 is packaged in an l8-pin DIP for the
highest possible density. The device is fully TTL compatible and has a single +5V power supply. ,
PIN CONFIGURATION
A6
Vee
A5
A7
A4
As
A3
A9
Ao
I/OT
AT
1/02
A2
1/03
cs
_Vee
ROW
SELECT
1/04
GND
.Cc
BLOCK DIAGRAM
WE
ORDERING INFORMATION
Order
Number
SYMC2148
SYMD2148
SYMF2148
SYMC2148-6
SYMD2148-6
SYMF2148-6
Access Operating Standby
Cu'rrent Current
Time
(Max)
(Max)
(Max)
70n.
70n.
70n.
85n.
85n.
85n.
150mA
150mA
150mA
150mA
150mA
150mA
30mA
30m A
30mA
30mA
30mA
30mA
Package
Type
Ceramic
Cerdip
' Flatpak
cs
--..--<1-'
Ceramic
Cerdip
Flatpak
WE -*---1_J
1-44
MEMORY ARRAY
64 ROWS
64 COLUMNS
SY2149H
MEMORY
PRODUCTS
A SUBSIDIARY OF HONEYWELL
•
•
•
•
•
• Industry Standard 2114 Pinout
• Totally TTL Compatible:
All Inputs and Outputs
• Common Data Input and Outputs
• High Density 18-Pin Package
• Three·State Output
45 ns Maximum Address Access
Fully Static Operation:
No Clocks or Strobes Required
Fast Ch ip Select Access Time: 20ns Max.
Identical Cycle and Access Times
Single +5V Supply
The Synertek SY2149H is a 4096·Bit Static Random
Access Memory organized 1 024words by 4 bits and is
fabricated using Synertek's new N-Channel Silicon·
Gate HMOS technology. It is designed using fully static circuitry, therefore requiring no clock or refreshing
to operate. Address set·up times are not required and
the data is read out non·destructively with the same
polarity as the input data. Common data input and
output pins provide maximum design flexibility. The
three·state output facilitates memory expansion by
allowing the outputs to be OR-tied to other devices.
The SY2149H offers a chip select access that is faster
than its address access. In a typical application, the
address access begins as soon as the address is val id.
At this time,. the high order addresses are decoded
and the desired memory is then selected. With the
faster chip select access, this decode time wil) not
add to the overall access time thus significantly im·
proving system performance.
The SY2149H is packaged in an 18-pin DIP for the
highest possible density. The device is fully TTL com·
patible and has a single +5V power supply.
PIN CONFIGURATION
BLOCK DIAGRAM
A6
Vee
As
A7
_Vee
A4
As
_GND
A3
A9
An
I/O,
MEMORY ARRAY
64 ROWS
64 COLUMNS
A,
1/02
A2
1/03
A8---'~
cs
1/04
A,---...-c.---,
GND
WE
ORDERING INFORMATION
Order
Number
SYC2149H·2
SYD2149H·2
SYC2149H·3
SYD2149H·3
SYC21 49H L·3
SYD2149HL·3
SYC2149H
SYD2149H
SYC2149HL
SYD2149HL
Access
Time
(Max)
45nsec
45nsec
55nsec
55nsec
55nsec
55nsec
70nsec
70nsec
70nsec
70nsec
I/O,
Supply
Current
(Max)
150mA
150mA
150mA
150mA
125mA
125mA
150mA
150mA
125mA
125mA
Package
Type
Ceramic
Cerdip
Ceramic
Cerdip
Ceramic
Cerdip
Ceramic
Cs
--..,....-<1-,
WE
--~-t_J
Cerdip
Ceramic
Cerdip
1-45
SY2t49H
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature Under Bias
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied.
. . . • • . . . -10°C to 85°C
Storage Temperature . . . . . . . . . . -65°C to 150°C
Voltage on Any Pin with
Respect to Ground . . . . . . . . ..
Power Dissipation
-3.5V to +7V
...•........•.•..•
D.C. CHARACTERISTICS
1.0W
TA = O°C to +70°C, VCC = 5V ±10% (Unless otherwise specified) (Note 6)
2149H·2,2149H·3,
2149H
2149HL·3,2149HL·
Symbol
Max.
Unit
III
Input Load Current
(All input pins).
Min.
10
10
JlA
VCC = Max, V,N = Gnd to VCC
ILO
Output Leakage Current
50
50
JlA
CS = V'H, VCC = Max
VOUT = Gnd to 4.5V
ICC
Power Supply Current
115
125
140
150
mA
mA
TA = 25°C
TA = 0 C
V,L
I nput Low Voltage
-3.0
0.8
V
V,H
Input High Voltage
2.0
6.0
V
VOL
Output Low Voltage
VOH
Output High Voltage
lOS
Output Short Circuit
Current
Parameter
CAPACITANCE
Min.
Max.
0.8
-3.0
6.0
2.0
0.4
0.4
2.4
2.4
±200
·±200
Conditions
J VCC = Max, CS = V,L
1 Outputs Open
V
'OL =8mA
V
10H =-4.0 mA
mA
VOUT = GND to VCC
TA = 25°C, f= 1.0MHz
Symbol
Max.
Unit
COUT
Output Capacitance
7
pF
CIN
Input Capacitance
5
pF
NOTE:
Typ.
Test
-
This parameter is periodically sampled and not 100% tested.
A.C. CHARACTERISTICS
TA = O°C to +70°C, VCC = 5V ±10% (Unless otherwise specified) (Note 6)
READ CYCLE
2149H·2
Symbol
Parameter
Min. Max.
2149HL·3
2149H·3
Min.
Max.
2149HL
2149H
Min.
Max.
Unit
tRC
Read Cycle Ti me
tAA
Address Access Time
45
55
70
ns
tACS
Chip Select Access Time
20
25
30
ns
tOH
Output Hold from Address Change
5
5
5
tLZ
Chip Selection to Output in Low Z
5
5
5
tHZ
Chip Deselectio to Output in High Z
0
45
55
15
0
15
0
Conditions
ns
70
ns
15
ns
Note 5
ns
Note 5
WRITE CYCLE
twc
Write Cycle Time
45
55
70
ns
tew
Chip Selection to End of Write
40
50
65
ns
tAW
Address Valid to End of Write
ns
Address Setup Time
50
0
65
tAS
40
0
0
twp
Write Pulse Width
40
twR
Write Recovery Time
35
5
50
5
ns
ns
ns
tow
Data Val id to End of Write
20
20
tDH
Data Hold Time
0
twz
Write Enabled to Output in High Z
0
0
tow
Output Active from End of Write
0
5
15
0
0
ns
25
0
20
0
0
ns
25
ns
Note 6
ns
Note 5
(See follOWIng page for notes)
SY2t49H
TIMING DIAGRAMS
READ CYCLE NO.1 (Notes 1 and 2)
'""~~t
DATA OUT
IRC
IAA
IOH
PREVIOUS DATA VALID
IXX ~
DATA VALID
*
READ CYCLE NO.2 (Notes 1 and 3)
IRC
CS~
lACS
i--IHZ-
ILZ
HIGH IMPEDANCE
DATA OUT
XX
HIGH
DATA VALID
IMPEDANCE
WRITE CYCLE NO.1 (WE controlled) (Note 4)
IWC
ADDRESS~
.
ICW
cs
II
\
lAW
lAS
WE
-IWRIWp
I
\\
lOW
-;
DATA IN
tOH --.
DATA VALID
-IWZ-
DATA OUT
.
' - - - IOW -
HIGH IMPEDANCE
DATA UNDEFINED
NOTES:
1. WE is high for Read Cycles.
2. Device is continuously selected, CS = VIL.
3. Addresses valid.
4. If CS goes high simultaneously with WE high, the outputs remain in the high impedance state.
S. Transition is measured t500mV from low or high impedance voltage with load B. This perameter is
sampled and not 100% tested.
6. The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear
feet per minute.
1-47
IIII
SYZ149H
WRITE CYCLE NO.2 (CS controlled) (Note 4)
twe
,~
ADDRESS
'-..J
_tAS
----
tew
-'
~
tAW
-IwR-
twp
..,
\\\\\\\\\\\
t
tow
DATA IN
-l
OH
_
DATA VALID
...--twz
_______________________________________________
=-=:1
DATA DUT
////////,
HIGH IMPEDANCE
=:))0----.....;.;;.;;;;.;..;;;;;..:;;;.;;.;.:;;-----------
DATA UNDEFINED
+5V
+5V
A.C. TEST CONDITIONS
INPUT PULSE LEVELS
GND TO 3,0 VOLTS
INPUT RISE AND FALL
TIMES
5nsec
INPUT AND OUTPUT
1.5 VOLTS
480n
TIMING REFERENCE
30 pF
(INCLUDING
SCOPE AND
JIG)
255n
LEVELS
SEe LOAD A.
OUTPUT LOAD
480n
Dour
DOUT
5 pF
255n
":"
":"
LOAD A,
LOADB,
PACKAGE DIAGRAMS
CERAMIC PACKAGE
CERDIP PACKAGE
:;:~,j::::::
PIN NO.1
IDE NT
1-,900 (22,860)
]
MAX~
-
=t
180 (4 572)
,140 (3 556)
060 (1 524)
015(381)~
I
(.3201
I
~
(.110)
(.0901
(.021)
f0151
.032 REF.
1-48
t
~ ~ ~ ~ ~ I~I ~ ~ ~_
,320
128)j
,290 (8
(7,366)
310 (7,874)
,260 (6,604)
I----J
Military 1024 x 4 Static
Random Access Memory
SYM2149H
MEMORY
PRODUCTS
Extended Temperature
SYNERTEK Range (-55°C to +t25°C)
PRELIMINARY
A SUBSIDIARY OF HONEYWELL
• 55 ns Maximum Address Access
• Fully Static Operation:
No Clocks or Strobes Required
• Fast Chip Select Access Time: 25 ns Max.
• Identical Cycle and Access Times
• Single +5V Supply (±10%)
•
•
Industry Standard 2114 Pinout
Totally TTL Compatible:
All Inputs and Outputs
• Common Data Input and,Outputs
• High Density 18·Pin Package
• Three·State Output
The Synertek SYM2149H is a 4096·8it Static Random
Access Memory organized 1024 words by 4 bits and is
fabricated using Synertek's new N·Channel Silicon·
Gate HMOS technology, It is designed using fully stat·
ic circuitry, therefore requiring no clock or refreshing
to operate. Address set·up times are not required and
the data is read out non·destructively with the same
polarity as the input data. Common data input and
output pins provide maximum design flexibility. The
three·state output facilitates memory expansion by
allowing the outputs to be OR·tied to other devices.
The SYM2149H offers a chip select access that is fast·
er than its address access. In a typical application, the
address access begins as soon as the address is valid.
At this time, the high order addresses are decoded
and the desired memory is then selected. With the
faster chip select access, this decode time will not
add to the overall access time thus significantly im·
proving system performance.
The SYM2149H is packaged in an 18'pin DIP for the
highest possible density. The device is fully TTL compatible and has a single +5V power supply.
PIN CONFIGURATION
BLOCK DIAGRAM
A6
Vee
A5
A7
_Vee
A4
As
_GND
A3
Ag
Ao
I/O,
A,
I/Oz
Az
1/03
cs
GND
ROW
SELECT
1/04
WE
I/O, -t,--C~-;
ORDERING INFORMATION
Order
Number
SYMC2149H-3
SYMD2149H-3
SYMC2149H
SYMD2149H
Access Supply
Time
Current Package
(Max)
(Max)
Type
55 nsec 150mA Ceramic
55 nsec 150mA Cerdip
70 nsec 150mA Ceramic
70 nsec 150mA Cerdip
110 3
cs
--..,....-- £ ==J
'"''
0060 (1 524)
00f5f0381l
_I
mmlW
I~ -
-)1-
Oro:-,5:
0,125 i31i5)
1 ".
1 290 (327661 MAX-_I
j
-:::;;:;;-1
~~~ II
_J_ff1=:
IDENT
PIN
NO 1
1_- -
I·
I (3556) I
j i U=~I
I
I
II
I
II
!
i
I
I I
;;:;70 (2.;;;,;;
-::
1 '
1
~01!5~3~1j~_
oos (0203)
II
0.0-15
1240 (3149SI MAX -
!
(D:38TI
-J (~~~I
I
I
0.700 (17,780)
I
0.630 (16.002) ~
r
.110 (2.794)
.095 (2.286)
2-14
iI
'L
I
.520 (13.208)
JL~~=+=L'015
:WoW~:
1
-A
r···~ (13,9701
I~+:;~~::~±f
0
O~ (1-;81--0,~,5841
0.090 (2.2B6i 0.030 (ojiI21
__
t-:~¥o~!~--
(O'3811j
.008(0.02032)
.680 (17.272)
.060 (1.524)
.045 (1.143)
.023 (.5842)
.015 (.3810)
.610 (15A94)
4096 x 8 Static
Read Only Memory
SY2332j33
MEMORY
PRODUCTS
SYNERTE~
A SUBSIDIARY OF HONEYWELL
•
•
SY2333-2732 EPROM Pin Compatible
4096 x 8 Bit Organ ization
Single +5 Volt Supply
Access Time-450ns (max)
Totally Static Operation
Completely TTL Compatible
CD
•
0
CD
CD
•
0
0
The SY2332/3 high performance read only memory
is organized 4096 words by 8 bits with access times
of less than 450 ns. This ROM is designed to be compatible with all microprocessor and similar applications where high performance, large bit storage and
simple interfacing are important design considerations.
This device offers TTL input and output levels with
a minimum of 0.4 Volt noise immunity in conjunction
with a +5 Volt power supply.
SY2332-2532 EPROM Pin Compatible
Three-State Outputs for Wire-OR Expansion
Two Programmable Chip Selects
2708/2716/2532/2732 EPROMs Accepted
as Program Data Inputs
The SY2332/3 operates totally asynchronously. No
clock input is required. The two programmable Chip
Select inputs allow four 32K ROMs to be OR-tied
without external decoding. Both devices offer threestate output buffers for memory expansion.
Designed to replace either the 2732 or 2532 32K
EPROMs, the SY2332/3 can eliminate the need to
redesign printed circuit boards for volume mask programmed ROMs after prototyping with EPROMs.
PIN
CONFIGURATIONS
BLOCK DIAGRAM
SY2333
SY2332
A,
vee
A,
A6
A,
A6
Aa
A5
Ag
A5
A,
A4
A4
A"
A3
cs,
cs,
A3
cs,
A,
A10
A,
A10
Vee
A,
A"
AD
0,
a,
a,
0
0
06
a,
06
0,
05
03
05
0,
04
GND
04
GND
03
A,
CS,
Ao
a,
AD
A,
A2
A3
A4
AS
A6
ORDERING INFORMATION
Order
Number
Package
Type
Access
Time
Temperature
Range
SYD2333
SYP2333
SYD2332
SYP2332
Cerdip
Plastic
Cerdip
Plastic
450ns
450ns
450ns
450ns
O°C
O°C
O°C
O°C
to +70°C
to +70°C
to +70°C
to +70°C
A custom number will be assigned by Synertek.
2-15
Vee
GND
r
r
SY2332/33
ABSOLUTE MAXIMUM RATINGS*
COMMENT*
Ambient Operating Temperature
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional opera'ticn of
this device at these or any other conditions above
those indicated on the operational sections of this
specification is not implied and exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Storage Temperature
-65°C to +150°C
Supply Voltage to Ground Potential
-0.5V to +7 .OV
Applied Output Voltage
-0.5V to +7.0V
Applied Input Voltage
-0.5V to +7.0V
Power Dissipation
1.0W
D.C. CHARACTERISTICS
T A = DoC to +70°C, VCC = 5.0V ±5% (unless otherwise specified)
Symbol
Parameter
VOH
VOL
VIH
Vil
III
IlO
Output HIGH Voltage
Output lOW Voltage
Input HIGH Voltage
Input lOW Voltage
Input load Current
Output leakage Current
ICC
Power Supply Current
Min.
Max.
Units
2.4
VCC
0.4
VCC
0.8
10
10
Volts
Volts
Volts
Volts
I1A
I1A
100
mA
2.0
-0.5
Test Conditions
VCC = 4.75V, IOH = -20011A
VCC = 4.75V, IOl = 2.1 mA
See Note 1
VCC = 5.25V, OV «VIN «5.25V
Chip DeselectedVOUT = +0.4 V to VCC
Output Unloaded, Chip Enabled
VCC = 5.25V, VIN = VCC
Note 1: Input levels that swing more negative than -0.5V will be clamped and may cause damage to the device.
A.C. CHARACTERISTICS
TA = DoC to +70°C, VCC = 5.0V ±5% (unless otherwise specified)
Symbol
SY2332/33
Min.
Max.
Parameter
Address Access Time
Chip Select Delay
Chip Deselect Delay
Previous Data Valid After
Address Change Delay
tACC
tco
tDF
tOH
Units
450
150
150
ns
ns
ns
ns
Max.
Units
7
10
pF
pF
20
Test Conditions
Output load: 1 TTL load and lOOp F
Input Pulse Levels: 0.8 to 2.4V
Input transition time: 20ns
Timing reference levels:
Input: 1.5V
Output: 0.8V and 2.0V
CAPACITANCE
tA
= 25°C,f = 1.0MHz, See
Symbol
C,
Co
Note 2
Parameter
Min.
Input Capacitance
Output Capacitance
Test Conditions
All pins except pin under
test tied to AC ground
Note 2: This parameter is periodically sampled and is not 100% tested.
TIMING DIAGRAM
~.."p~~~SS ~,--
_ _ _ _ _ _ _V_A_Ll_D_ _ _ _ _
CHIP
SELECT
INPUTS
~~
ENABLED
I
teo
OUTPUTS
DATA
--HiG:;;-;-;m,~~t-----~~~~~~~
HIGH lMPEDENCE
INVALID
2-16
:"-_ _ _J'
HtGH IMPEDANCE
§1f1331/33
34-41
43·50
52·59
61·68
70·77
79·80
PROGRAMMING INSTRUCTIONS
All Synertek read only memories utilize computer aided techniques to manufacture and test custom bit patterns. The custom bit pattern and address information is supplied on standard 80 column computer cards or 1" wide paper tape.
CARD FORMAT
INTEL PAPER TAPE FORMAT
All addresses and related output patterns must be completely
defined. Each deck of cards defining a specific ROM bit pat·
tern consists of 11 four Title Cards and 21 address and bit pat·
tern Data Cards. Positive logic is generally used on all input
cards: a logic "1" is the most positive or HIGH level, and a
logic "0" is the most negative or LOW level. Synertek can
also accept ROM data in other formats, compatible with
most microprocessors and PROMs. Consult your Synertek
representative for details.
The paper tape which should be used is 1'~ wide paper tape
using 7 or 8 bit ASCII code, such as a model 33ASR teletype
produces.
BPNF Format
The format requirements are as follows:
1. All word fields are to be punched in consecutive order,
starting with word field Iil lall addresses lowl. There must
be exactly N word fields for the N x 8 ROM organization.
2. Each word field must begin with the start character Band
end with the stop character F. There must be exactly 8
data characters between the Band F for the N x 8 organ·
ization.
NO OTHER CHARACTERS, SUCH AS RUBOUTS, ARE
ALLOWED ANYWHERE IN A WORD FIELD. If in pre·
paring a tape, an error is made, the entire word field, including the Band F must be rubbed out. Within the word
field, a P results in a high tape level output, and an N results in a low level output.
3. Preceding the first word field and following the last word
field, there must be a leaderltrailer length of at least 25
characters. This should consist of rubout punches (te~ter
key for Telex tapes I
4. Between word fields, comments not containing B's or F's
may be inserted. Carriage return and line feed characters
should" be inserted (as a "comment") just before each word
field (or at least between every four word fields). When
these carriage returns, etc. are inserted, the tape may be
easily listed on the teletype for purposes of error checking.
The customer may also find it helpful to insert the word
number (as a comment) at least every four word fields.
5. Included in the tape before the leader should be the cus·
tomer's complete Telex or TWX number and if more than
one pattern is being transmitted. the ROM pattern number.
6. MSB and LSB are the most and least significant bit of the
device outputs. Refer to the data sheet for the pin numbers.
TITLE CARDS
A set of four Title Cards should accompany each data deck.
These cards give our computer programs additional information necessary to accurately produce high density ROMs. These
four Title Cards must contain the following information:
COLUMN
INFORMATION
First Card
1·30
31·50
60·72
Second Card
1·30
31-50
1-6
Customer name
Customer part number
Synertek part number {punch
2333 or 23321
Customer contact (name)
Customer telephone number
Leave blank - pattern number to
be assigned by Synertek
CS21CS2 chip select logic level (if
LOW selects chip, punch "0"; if
HIGH selects chip, punch "1 "; if
DON'T CARE, punch "2"
CS11CSl chip select logic level.
Data Format. Punch "Intel" starting
in column one.
Logic Format; punch "POSITIVE
LOGIC" or NEGATIVE LOGIC."
Truth table verification code; punch
either "VERIFICATION HOLD"
(manufacturing starts after customer
approval of bit pattern data supplied
by Synertekl or "VERIFICATION
NOT NEEDED" Imanufacturing
starts immediately upon receipt of
customer card deck)
Third Card
30
Fourth Card
31
1·8
15·28
35-37
HEXADECIMAL PROGRAM TAPE FORMAT
The hexadecimal tape format used by the INTELLEC 8 sys'
tem is a modified memory image, blocked into discrete records.
Each record contains record length, record type, memory
address, and checksum information in addition to data. A
frame by frame description is as follows:
INTEL DATA CARD FORMAT
Output data is punched as either a lip" or an "N"; a "P" is
defined as a HIGH and an "N" is defined as a LOW. Output
8108 or071 is the MSB and Output 1101 or 001 is the LSB.
The four Title Cards listed above must accompany the Intel
card deck.
Data Cards
COLUMN
INFORMATION
1·5
Punch the 5·digit decimal equivalent
of the binary coded a'ddress which
begins each card. This is the inital
input address. The address is right
justified, i.e. 00000, 00008, 00016,
etc.
Output data IMSB·LSBI for initial
input address.
Output data for initial input address +1
Output data for initial input address +2
7·14
16-23
25·32
Output data for initial input address +3
Output data for initial input address +4
Output data for initial input address +5
Output data for initial input address +6
Output data for initial input address +7
ROM pattern number Imay be left
blankl
Frame 0
Frames 1,2
10·9, A·FI
Frames 3 to 6
2-17
Record mark. Signals the start of a
record. The ASCII character colon I":"
HEX 3A) is used as the record mark.
Record length. Two ASCII characters
representing a hexadecimal number in
the range a to 'FF' 10 to 2551. This is
the count of the actual data bytes in
the record type or checksum. A record
length of a indicates end of file.
Load Address. Four ASCII characters
that represent the initial memory will
be loaded. The first data byte is stored
in the location pointed to by the load
address, succeedin.g data bytes are
loaded into ascending addresses.
SY2332/33
Frames 7,8
Record type. Two ASCII characters.
Frames 9 to 9+2*
(Record Length) -1
ing al r carries out of an 8-bit sum, then
add the checksum, the result is zero .
Currently all 'records are type 0, this
. field is reserved for future expansion.
. Data. Each 8 bit memory word is repre-
Example: If memory locations 1 through 3 contain 53F8EC,
the format of the hex file produced when these locations are
punched is:
sented by two frames containing the
ASCII characters (0 to 9, A to F) to
:0300010053F8ECC5
represent a hexadecimal value 0 to 'FF'
(0 to 255).
Frames 9+2*
Checksum. The checksum is the nega-
(Record Length) to
9+2* (Record
Length) +1
tive of the sum of all 8 bit bytes 'in the
record since the record mark (":" )
evaluated modulus 256. That is, if you
add together all the 8 bit bytes, ignor-
Send bit pattern data to the following special address:
Synertek - ROM
P.O. Box 552
3050 Coronado Drive
Santa Clara, CA 95051
TYPICAL CHARACTERISTICS
ACCESS TIME VS. CAPACITIVE LOAD
ACCESS TIME
600
600
500
500
400
300
".
200
I
tl
S
"
300
-
200
300
400
500
600
~L • '~OPF
3.5
700
4.0
4.5
140
6.0
6.5
7.0
140
120
120
-
100
E
I
5.5
SUPPLY CURRENT VS. SUPPLY VOLTAGE
SUPPLY CURRENT VS. AMBIENT TEMPERATURE
""
5.0
VCC - VOLTS
CL - pF
"
6000 "'-TA = 25°C
1 TTL LOAD
a
100
TYPICAL
~
100
1 TTL LOADCL = 100pF
a
400
200
Vee - 4.75V
TA = 2SoC
100
a
c
.::::~~ I""-"
vs. SUPPLY VOLTAGE
80
100
_~AL
60
t-
"E
80
""
60
:
!
-r-r-r
I
I
I
TYPICAL
"
40
40
20
20
Vee'" 5.25V
I I
a
0'
10'
20'
30'
40"
50"
60"
a
70"
3.5
TA - AMBIENT TEMPERATURE _ O°C
J---
i
4.0
--
4.5
5.0
f-
5.5
TA:'25'f6.0
Vee - VOLTS
PACKAGING DIAGRAMS
PLASTIC PACKAGE
CERDIP PACKAGE
2-18
6.5
7.0
4096 x 8 Stade
SY2332-3
SY2333-3
Read Only Memory
MEMORY
PRODUCTS
SYNERTEK
A SUBSIDIARV OF HONEYWELL
•
•
•
q
SY2333-2732 EPROM Pin Compatible
4096 x 8 Bit Organization
Single +5 Volt Supply (±10%)
Access Time-300ns (max)
Totally Static Operation
Completely TTL Compatible
•
iii
0
iii
0
•
The SY2332-3 and SY2333-3 high performance read
only memories are organized 4096 words by 8 bits
with access times of less than 300 ns. They are designed to be compatible with all microprocessor and
similar applications where high performance, large bit
storage and simple interfacing are important design
considerations. These devices offer TTL input and output levels with a minimum of 0.4 Volt noise immunity
in conjunction with a +5 Volt power supply.
SY2332-2716 EPROM Pin Compatible
Three-State Outputs for Wire-OR Expansion
Two Programmable Chip Selects
2708/2716/2732 EPROMs Accepted as
Program Data Inputs
The SY2332-3 and SY2333-3 operate totally asynchronously. No clock input is required. The two programmable Chip Select inputs allow four 32K ROMs
to be OR-tied without external decoding. Both devices offer three-state output buffers for memory
expansion.
Designed to replace 2716 or 2732 32K EPROMs, the
SY2332-3 and SY2333-3 can eliminate the need to redesign printed circuit boards for volume mask programmed ROMs after prototyping with EPROMs.
PIN
CONFIGURATIONS
SV2332-3
BLOCK DIAGRAM
SV2333-3
A,
Vee
A,
Vee
A,
A,
Ao
A,
A5
Ag
A5
Ag
A4
CS2
A4
A"
A3
cs,
A3
cs,
A2
AlO
A2
AlO
A,
A,
CS 2
Ao
A"
0,
Ao
0,
0,
0,
00
0,
02
00
0,
°5
03
05
°2
GND
04
GND
°4
03
AD
A,
A2
A3
A4
A5
A,
ORDERING INFORMATION
Order
Number
Package
Tvpe
Access
Time
Temperature
Range
SYC2333-3
SYP2333-3
SYC2332-3
SYP2332-3
Ceramic
Plastic
Ceramic
Plastic
300ns
300ns
300ns
300ns
O°C
DoC
O°C
DoC
to
to
to
to
+70°C
+70°C
+70°C
+70°C
A custom number will be assigned by Synertek.
2-19
Vee
GNO
r
!
SY2331-3jSY.l333-3
ABSOLUTE MAXIMUM RATINGS*
COMMENT*
Ambient .operating Temperature
_10°C to +80°C
Storage Temperature
-65°C to +150°C
Supply Voltage to Ground Potential
-0.5V to +7.0V
Applied .output Voltage
-0.5V to +7.0V
Applied Input Voltage
-0.5V to +7.0V
Power Dissipation
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated on the operational sections of this
specification is not implied and exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
1.0W
D.C. CHARACTERISTICS
TA
= DoC
to +70°C,
Symbol
Vee = 5.0V
±10% (unless otherwise specified)
Parameter
VIH
VIL
III
ILD
.output HIGH Voltage
.output LDW Voltage
Ihput HIGH Voltage
Input LDW Voltage
Input Load Current
.output Leakage Current
ICC
Power Supply Current
VDH
VDL
Min.
Max.
Units
2.4
VCC
0.4
Volts
2.0
-0.5
Volts
Volts
Volts
VCC
0.8
10
10
/lA
/lA
Test Conditions
VCC
VCC
= 4.5V,
= 4.5V,
IDH
IDL
= -400/lA
= 2.1 mA
See Note 1
VCC
= 5.5V, OV';; VIN';; 5.5V
Chip Deselected
= +0.4 V to VCC
.output Unloaded, Chip Enabled
VDUT
mA
100
VCC
= 5.5V, VIN = VCC
c
Note 1: Input levels that swing more negative than -0.5V will be clamped and may cause damage to the device.
A.C. CHARACTERISTICS
T A = DoC to +70°C, VCC = 5.0V ±10% (unless otherwise specified)
Symbol
Parameter
Address Access Time
Chip Select Delay
Chip Deselect Delay
Previous Data Valid After
Address Change Delay
tACC
tCD
tDF
tDH
SY2332·3 and SY2333·3
Min.
Max.
Units
300
100
100
ns
ns
ns
ns
Max.
Units
7
10
pF
pF
20
Test Conditions
.output load: 1 TTL load
and 100pF
Input transition time: 20ns
Timing reference levels:
Input: 1.5V
.output: 0.8V and 2.0V
CAPACITANCE
tA = 25°C,f = 1.0MHz, See Note 2
Symbol
Parameter
Min.
Input Capacitance
.output Capacitance
CI
CD
Test Conditions
All pins except pin under
test tied to AC grou nd
Note 2: This' parameter is periodically sampled and is not 100% tested.
TIMING DIAGRAM
~.:'p~~~SS ~
_ _ _ _ _ _ _ _V_A_Ll_D_ _ _ _ _
CHIP
SELECT
INPUTS
OA1A
OUTPUTS
~~
I
_
_
HK~;U~;-~____~==~~~'C~O~~~~~~~~~~
HIGH IMPEDENCE
1 - - - - - - - tAce
------j
2-20
~~QQ~1Q::;o"
H!GH IMPEDANCE
§Y133S1-3S/§Y71333-3
34-41
43-50
52-59
61-68
70·77
79-80
PROGRAMMING INSTRUCTIONS
All Synertek read only memories utilize computer aided techniques to manufact-ure and test custom bit patterns. The custom bit pattern and address information is supplied on standard 80 column computer cards or 1" wide paper tape.
CARD FORMAT
Output data for initial input address +3
Output data for initial input address +4
Output data for initial input address +5
Output data for initial input address +6
Output data for initial input address +7
ROM pattern number Imay be left
blank)
INTEL PAPER TAPE FORMAT
All addresses and related output patterns must be completely
defined. Each deck of cards defining a specific ROM bit pattern consists of 1) four Title Cards and 2) address and bit pat-
The paper tape which should be used is 1" wide paper tape
using 7 or 8 bit ASCII code, such as a model 33 ASR teletype
tern Data Cards. Positive logic is generally used on all input
cards: a logic "1" is the most positive or HIGH level, and a
logic "0" is the most negative or LOW level. Synertek can
also accept ROM data in other formats, compatible with
most microprocessors and PROMs. Consult your Synertek
produces.
BPNF Format
The format requirements are as follows:
1. All word fields are to be punched in consecutive order,
starting with word field iil lall addresses lowl. There must
be exactly N word fields for the N x 8 ROM organization.
representative for details.
TITLE CARDS
2. Each word field must begin with the start character Band
end with the stop ·character F. There must be exactly 8
A set of four Title Cards should accompany each data deck.
These cards give our computer programs additional informa·
tion necessary to accurately produce high density ROMs. These
four Title Cards must contain the following information:
NO OTHER CHARACTERS, SUCH AS RUBOUTS, ARE
ALLOWED ANYWHERE IN A WORD FIELD. If in·pre.
INFORMATION
COLUMN
First Card
data characters between the Band F for the N x 8 organization.
paring a tape, an error is made, the entire word field, in-
cluding the Band F must be rubbed out. Within the word
1·30
31-50
60-72
Customer name
Customer part number
Synertek part number (punch
1-30
31-50
1-6
Customer contact (name)
Customer telephone number
Leave blank - pattern number to
field, a P results in a high tape level output, and an N results in a low level output.
3. Preceding the first word field and following the last word
field, there must be a leaderltrailer length of at least 25
2333 or 2332)
Second Card
Third Card
key for Telex tapes)
4. Between word fields, comments not containing B's or F's
may be inserted. Carriage return and line feed characters
be assigned by Synertek
CS2/CS2 chip select logic level lif
LOW selects chip, punch "0"; if
HIGH selects chip, punch "1 "; if
DON'T CARE, punch "2"
CS1/CS1 chip select logic level.
30
Fourth Card
characters. This should consist of rubout punches (letter
31
1·8
should be inserted (as a "comment ") just before each word
field lor at least between every four word fields). When
these carriage returns, etc. are inserted, the tape may be
easily listed on the teletype for purposes of error checking.
The customer may also find it helpful to insert the word
Data Format. Punch "Intel" starting
number (as a comment) at least every four word fields.
5. Included in the tape before the leader should be the customer's complete Telex or TWX number and if more than
one pattern is being transmitted, the ROM pattern number.
in column one.
15-28
35-37
Logic Format; punch "POSITIVE
LOGIC" or NEGATIVE LOGIC."
Truth table verification code;punch
either "VERIFICATION HOLD"
6. MSB and LSB are the most and least significant bit of the
(manufacturing starts after customer
device outputs. Refer to the data sheet for the pin numbers·.
approval of bit pattern data supplied
by Synertek) or "VERIFICATION
NOT NEEDED" Imanufacturing
HEXADECIMAL PROGRAM TAPE FORMAT
The hexadecimal tape format used by the INTELLEC 8 sys-
starts immediately upon receipt of
customer card deck)
tem is a modified memory image, blocked into discrete records.
Each record contains recorq length, record type, memory
address, and checksum information in addition to data. A
frame by frame description is as follows:
INTEL DATA CARD FORMAT
Output data is punched as either a "P" or an "N"; a lip" is
defined as a HIGH and an UN" is defined as a LOW. Output
Frame 0
8 108 or 07) is the MSB and Output 1 101 or 00) is the LSB.
The four Title Cards listed above must accompany the Intel
card deck.
Data Cards
COLUMN
INFORMATION
1-5
Punch the 5-digit decimal equivalent
of the binary coded address which
Frames 1,2
10-9, A·F)
Record mark. Signals the -start of a
record. The ASCII character colon I":"
HEX 3A) is used as the record mark.
Record length. Two ASCII characters
representing a hexadecimal number in
the range
a to
'F F' 10 to 255). This is
the count of the actual data bytes in
the record type or checksum. A record
begins each card. This is 'the inital
input address. The address is right
justified, i.e. 00000, 00008, 00016,
Frames 3 to 6
length of a indicates end of file.
Load Address. Four ASCII characters
th?t represent the initial memory will
etc.
initial
be loaded. The first data byte is stored
16·23
input address.
Output data for initial input address +1
25·32
Output data for initial input address +2
in the location pointed to by the load
address, succeeding data bytes are
loaded into ascending addresses.
7-14
Output data
IMSB-LSB)
for
2-21
SY2332-3jSY2333-3
Frames 7, 8
ing all carries out of an S-bit sum, then
add the checksum, the result is zero.
Record type. Two ASCII characters.
Currently all records are type 0, this
field is reserved for future expansion.
Frames 9 to 9+2*
Example: If memory locations 1 through 3 contain 53F8EC,
the format of the hex file produced when these locations are
Data. Each 8 bit memory word is represented by two frames containing the
(Record Length) -1
punched is:
ASCII characters (0 to 9, A to F) to
represent a hexadecimal value 0 to 'FF'
(0 to 2551.
Frames 9+2*
Checksum. The checksum is the nega-
(Record Length) to
9+2* (Record
Length) +1
tive of the sum of all 8 bit bytes in the
:0300010053F8ECC5
Send bit pattern data to the following special address:
Synertek - ROM
P.O. Box 552
3050 Coronado Drive
Santa Clara, CA 95051
record since the record mark ( ":" )
evaluated modulus 256. That is, if you
add together all the 8 bit bytes, ignor·
TYPICAL CHARACTERISTICS
ACCESS TIME
vs. CAPACITIVE LOAD
ACCESS TIME VS. SUPPLY VOLTAGE
700
600
500
500 I - - - + - + - t - - + - + - t - - - I
400
1--+-+--::;;1
c
l
;::~
I
400
U
u
3001---+~~~t--+-+-·t---I
S
"."
~
TYPICAL
300
200
200 I---+-+--t--+--'----,-,=---I
Vee = 4.75V
TA= 25 C
TA=25°C
1 TTL LOAD
Q
100
100 I - - - + - + - t - - + - , TTL LOAD-
~L' '~OPF
CL'" 100pF
o
o~~~--~-L--~~~
o
100
200
300
400
500
600
3.5
700
4.0
4.5
E
I
u
u
140
140
120
120
80
-
100
~
_~4l
60 )--40
~
E
-
"
u
u
t-
20
10"
20 0
30°
40°
7.0
50°
60°
I
!
T-+--I--
80
I
TYPICAL
60
40
20
I I
0"
6.5
,
Vee = 5.2SV
o
6.0
SUPPLY CURRENT VS. SUPPLY VOLTAGE
SUPPLY CURRENT VS. AMBIENT TEMPERATURE
100
5.5
Vee - VOLTS
CL -pF
~
5.0
o
3.5
70 0
TA - AMBIENT TEMPERATURE _ o°C
j
TA)=25°r-
I
4.0
4.5
5.0
5.5
6.0
Vee - VOLTS
PACKAGE DIAGRAMS
PLASTIC PACKAGE
CERAMIC PACKAGE
2-22
6.5
7.0
8192 x 8 Static
Read Only Memory
SY2364/SY2364A
MEMORY
PRODUCTS
SYNERTEIt
A SUBSIDIARY OF HONEYWELL
•
•
•
•
•
•
2564 EPROM Pin Compatible
8192 x 8 Bit Organization
Single +5 Volt Supply
Access Time - 200/300/450 ns (max)
Totally Static Operation
Completely TTL Compatible
• 24 Pin JEDEC Approved Pinout
• SY2364A - Automatic Power Down (CE)
• SY2364 - Non Power Down Version
- Programmable Chip Select
o Three State Outputs for Wire-OR Expansion
• EPROMs Accepted as Program Data Input
The SY2364A offers an automatic power down feature.
Power down is controlled by the Chip Enable (CE) input.
When CE goes high, the device will automatically power
down and remain in a low power standby mode as long as
CE remains high. This unique feature provides system level
power savings as much as 90%.
The SY2364 and SY2364A high performance Read Only
Memories are organized 8192 words by 8 bits with access
times from 200 ns to 450 ns. The ROMs are designed to be
compatible with all microprocessor and similar applications
where high performance, large bit storage and simple
interfacing are important design considerations. Both
ROMs conform to the JEDEC approved pinout for 24 pin
64K ROMs.
Both the SY2364 and SY2364A are pin compatible with
the 2564 EPROM thus eliminating the need to redesign
printed circuit boards for volume mask programmed ROMs
after prototyping with EPROMs.
The SY2364 offers the simplest operation (no power
down.) Its programmable chip select allows two 64K ROMs
to be OR-tied without external decoding.
PIN CONFIGURATIONS
BLOCK DIAGRAM
SV2364
SV2364A
AJ
A,
Vee
A,
A.
As
""
A,
Vee
Ao
A,
A,
As
A,
A,
A12
CS
A.
A12
A,
A3
A3
CE
tv,
AlO
A2
A,.
AB
Ag
A,
An
A,
An
A"
A.
0,
0,
A.
D.
A.
O2
03
0,
0,
0,
0.
°2
03
GNO
0.
°s
0.
GNO
65.536 BIT
AOMAAAAY
1256 x 2561
AD
A,
°s
0.
A2
ORDERING INFORMATION
Orde,r
Number
SYD2364
SYP2364
SYD2364-3
SYP2364-3
SYD2364-2
SYP2364-2
SYD2364A
SYP2364A
SYD2364A-3
SYP2364A-3
SYD2364A-2
SYP2364A-2
Access
Time
450
450
300
300
200
200
450
450
300
300
200
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Operating
Current
100
100
100
100
100
100
100
100
100
100
100
100
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
Standby
CUrrent
N.A.'
N.A.
N.A.
N.A.
NA
N.A.
12 rnA
12 rnA
12 rnA
12 rnA
12rnA
12 rnA
A"
A"
Package
Type
0,
:>,--:--02
Cerdip
0,
Plastic
D>:-~~04
0,
'-------'-D-,.---!-- 0,
Cerdip
Plastic
Cerdip
0,
Plastic
L-------:...D.:--:--OB
Cerdip
cs
Plastic
POWEA DOWN
OUTPUT ENABLE
Cerdip
Plastic
Cerdip
Plastic
'CHIP SELECT ICS) IS PROGRAMMABLE LOW ACTIVE OR HIGH ACTIVE
2-23
SY2364jSY2364A
ABSOLUTE MAXIMUM RATINGS
Ambient Operating Temperature
Storage Temperature
Supply Voltage to Ground Potential
Applied Output Voltage
Applied Input Voltage
Power Dissipation
COMMENT
-10°C to +80 o C
-65°C to +150°C
-0.5V to +7.0V
-0.5V to +7.0V
-0.5V to +7.0V
1.0W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress ratings only. Functional operation of this device at
these or any other conditions above those indicated on the
operational sections of this specification is not implied and
exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
D.C. CHARACTERISTICS
Symbol
Parameter.
VOH
Output HIGH Level
VOL
V IH
Output LOW Level
Input HIGH Level
2.0
V IL
Input LOW Level
-0.5
III
ILO
Icc
Operating Supply Current
ISB
los
Typ.
Max.
Unit
Vcc
0.4
V
10H = -1.0 mA
V
10L = 3.2 mA
Vcc
0.8
V
Input Leakage Current
10
/J. A
V IN = OV to Vcc
Output Leakage Current
10
/lA
V OUT = OV to Vcc
100
mA
Note 1
Standby Supply Current
12
mA
Note 2
Output Short Circuit Current
90
mA
Note 3
Min.
2.4
Conditions
V
CAPACITANCE
TA = 25°C. f= 1.0 MHz
Note: This parameter is periodically sampled and is not 100% tested.
Symbol
Parameter
Max.
Unit
CI
Input Capacitance
5
pf
V IN = OV
Co
Output Capacitance
5
pf
V OUT = OV
Min.
Conditions
A.C. CHARACTERISTICS
Parameter
2364-2
2364A-2
Min.
Max.
2364-3
2364A-3
Min.
Max.
2364
2364A
Min.
Max.
tCYC
Cycle Time
200
300
450
tAA
Address Access Time
tOH
Output Hold After Address
Change
tACE
Chip Enable Access Time
200
300
450
ns
tACS
Chip Select Access Time
85
100
150
ns
tLZ
Ouput LOW Z Delay
tHZ
Output HIGH Z Delay
tpu
Power Up Time
tpo
Power Down Time
Symbol
10
10
10
150
100
85
0
0
0
100
85
Notes:
1. Measured with device selected and outputs unloaded.
2. Applies to "A" versions only and measured with CE = 2.0V.
3. For a duration not to exceed 30 seconds.
4. Applies to "A" versions (power down) only.
5. Output low impedance delay (tLZ) is measured from CE going low or CS going active.
6. Output high impedance delay (tHZ) is measured from CE going high or CS going inactive.
2-24
ns
ns
10
10
10
Conditions
ns
450
300
200
Unit
150
Note 4
ns
Note 5
ns
Note 6
ns
Note 4
ns
Note 4
SY2364jSY2364A
TIMING DIAGRAMS
Propagation Delay from Address (CE LOW or CS = Active)
ADDRESS
INPUTS
VALID ADDRESS
DATA
OUT
Propagation Delay from Chip Enable, Chip Select or Output Enable (Address Valid)
,,
4
{6}
cs
DATA
OUT
_{S}
'ee
---- ------
)
-
{S}
Vee CURRENT
~l-
VALID
11\
..,
ISB
I_z~
I---
--'--
1A.C. TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Timing Measurement Levels: Input
Output
Output Load
2.0V to 2.2V
10 nsec
1.5V
0.8V and 2.0V
See Figure 1
+5V
1250n
DOUT------~------~
100pf (INCLUDING SCOPE AND JIG)
775n.
PROGRAMMING INSTRUCTIONS
Figure 1.
All Synertek read only memories utilize computer aided techniques
to manufacture and test custom bit patterns. The custom bit pattern
Third Card
and address information is supplied on standard 80 column com-
1-6
32
All addresses and related
outP1Jt
Leave blank -
pattern number to be
assigned by Synertek
puter cards in the format described below.
patterns must be completely de-
fined. Each deck of cards defining a specific ROM bit pattern
consists of 1) four Title Cards and 2) address and bit pattern Data
Cards. Positive logic is generally used on all input cards: a logic "1"
Fourth Card
is the most positive or HIGH level, and a logic "0" is the most nega-
1-8
CS chip select logic level (if LOW
selects chip, punch "0"; if HIGH
selects chip, punch "1 "). If 2364A,
leave blank.
Data Format. Synertek, or Intel data
card format may be used. Specify for-
tive or LOW level. Synertek can also accept ROM data in other
mat by punching "Synertek," or"lntel"
formats, compatible with most microprocessors and PROMS. Con·
starting in column one.
suit your Synertek representative for details.
15-28
TITLE CAROS
35-57
A set of four Title Cards should accomp~ny each data deck. These
Logic format; punch "POSITIVE
LOGIC" or "NEGATIVE LOGIC."
Truth
table
verification
code;
punch
cards give our computer programs additional information necessary
either "VERIFICATION HOLD" (man-
to accurately produce high density ROMS. These four Title Cards
ufacturing starts after customer approval
must contain the following information:
of bit pattern data supplied by Synertek)
or "VERIFICATION NOT NEEDED"
COLUMN
First Card
1-30
31-50
60-72
INFORMATION
(manufacturing starts immediately upon
receipt of customer card deck)
Customer name
Customer part number
Synertek part number (punch
"2364" or "2364A ")
Second Card
1-30
31-50
Customer contact (name)
Customer telephone number
2-25
SY2364/SY2364A
SYNERTEK DATA CARD FORMAT
All addresses are coded in decimal form (0 through. 2047). All out·
put words are coded both in binary and octal forms, Output 3 (08)
is the MSB, and Output 1 (01) is the LSB,
COLUMN
Data Cards
1-4
6-13
15-17
22-25
27-34
36-38
43-46
48-55
57-59
64-67
69-76
78-80
Data Cards
COLUMN
INFORMATION
1-5
Punch the 5-digit decimal equivalent of
the ,binary coded address which begins
each card. This is the initial input
address. The address is right justified,
i.e. 00000, 00008, 00016, etc.
Output data (MSB·LSB) for initial input
INFORMATION
Decimal address
Output (MSB·LSB)
Octal equivalent of
Decimal address
Output (MSB·LSB)
Octal equivalent of
Decimal address
Output (MSB·LSB)
Octal equivalent of
Decimal address
Output (MSB·LSB)
Octal equivalent of
7-14
address.
output data
16-23
25-32
34-41
43-50
52-59
61-68
70-77
output data
output data
79~8o
Output
Output
Output
Output
data
data
data
data
for
for
for
for
Output data for
Output data for
Output data for
ROM pattern
blank)
initial
initial
initial
initial
input addr~ss +1
input address +2
input address +3
input address +4
initial input address +5
initial input address +6
initial input address +7
nUniber (may be left
output data
INTEL DATA CARD FORMAT
Output data is punched as
as a HIGH, and an "N" is
MSB and Output 1 (0,)
above must accompany the
either a "P" or an "N"; a "P" is defined
defined as a LOW. Output 8 (OB) is the
is the LSB. The four Title Cards listed
Intel card deck.
Send bit pattern data to the following special address:
Synertek - ROM
P,O, Box 552
Santa Clara, CA 95052
PACKAGE DIAGRAMS
CERDIP PACKAGE
PLASTIC PACKAGE
2-26
8192 x 8 Static
Read Only Memory
SY2365/SY2365A
MEMORY
PRODUCTS
SYNERTEK
A SUBSIDIARV OF HONEYWELL
•
•
•
•
•
•
•
• SY2365A - Automatic Power Down (CE)
- Output Enable Function (OE)
- Two Programmable Chip Selects
• SY2365 - Non Power Down Version
- Four Programmable Chip Selects
o Three State Outputs for Wire-OR Expansion
• EPROMs Accepted as Program Data Input
2764 EPROM Pin Compatible
8192 x 8 Bit Organization
Single +5 Volt Supply
Access Time - 200/300/450 ns (max)
Totally Static Operation
Completely TTL Compatible
28 Pin JEDEC Approved Pinout
When CE goes high. the device will automatically power
down and remain in a low power standby mode as long as CE
remains high. This unique feature provides system level
power savings as much as 90%. An additional feature of the
SY2365A is the Output Enable(OE)function.This eliminates
bus contention in multiple bus microprocessor systems. The
two programmable chip selects allow up to four 64K ROMs to
be OR-tied without external decoding.
Both the SY2365 and SY2365A are pin compatible with the
2764 EPROM thus eliminating the need to redesign printed
circuit boards for volume mask programmed ROMs after
prototyping with EPROMs.
The SY2365 and SY2365A high performance Read Only
Memories are organized 8192 words by 8 bits with access
times from 200 ns to 450 ns. The ROMs are designed to be
compatible with all microprocessor and similar applications
where high performance. large bit storage and simple
interfacing are important design considerations. Both ROMs
conform to the JEDEC approved pinout for 28 pin 64K ROMs.
The SY2365 offers the simplest operation (no power down.)
Its four programmable chip selects allow up to sixteen 64K
ROMs to be OR-tied without external decoding.
The SY2365A offers an automatic power down feature.
Power down is controlled by the Chip Enable (CE) input.
PIN CONFIGURATIONS
Ne
A12
A,
A.
As
A,
A3
A,
A,
AD
a,
0,
03
GNO
Vee
CS,
es,
A.
A,
Al1
eS3
A"
es,
a.
a,
a.
as
a,
BLOCK DIAGRAM
Ne
A12
A,
A.
As
A,
A3
A,
A,
AD
a,
0,
03
GNO
Vee
es,
es,
As
A,
Al1
iiE
65.536 BIT
ROM ARRAY
(256x2561
A"
EE
a.
a,
a.
as
a,
COLUMN SELECT
CIRCUITRY
(BOf2561
ORDERING INFORMATION
Access
Time
Operating
Number
Current
Standby
Current
SYD2365
SYP2365
SYD2365·3
SYP2365·3
SYD2365·2
SYP2365·2
SYD2365A
SYP2365A
SYD2365A·3
SYP2365A·3
SYD2365A·2
SYP2365A·2
450ns
450ns
300ns
300ns
200ns
200 ns
450ns
450 ns
300ns
300 ns
200ns
200 ns
100mA
100mA
100mA
100mA
100mA
100mA
100mA
100mA
100mA
100mA
100mA
100mA
N.A.*
NA
N.A.
NA
N.A.
N.A.
12mA
12 mA
12 mA
12 mA
12 rnA
12 rnA'
Order
0,
Package
I.!..I~:"-'....!..-O,
Type
03
L-_~~=--!._ 0,
Cerdip
Plastic
0,
Cerdip
L------!'-l~~...!..-o,
Plastic
0,
Cerdip
Plastic
Cerdip
L-..,--------!'-l~~...!..-o.
POWER DOWN
Plastic
OUTPUT ENABLE
Cerdip
Plastic
Cerdip
Plastic
'CHIP SELECTS ,CS, ARE PROGRAMMABLE LOW ACTIVE. HIGH ACTIVE OR
DON'T CARE,
2-27
SY2365/SY2365A
ABSOLUTE MAXIMUM RATINGS*
COMMENT*
-10°C to +80 o C
-65°C to +.1 50°C
-0.5V to +7.0V
-0.5V to +7.0V
-0.5V to +7.0V
1.0W
Ambient Operating Temperature
Storage Temperature
Supply Voltage to Ground Potential
Applied Output Voltage
Applied Input Voltage
Power Dissipation
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress ratings only. Functional operation of this device at
these or any other conditions above those indicated on the
operational sections of this specification is not implied and
exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
D.C. CHARACTERISTICS
.-.
Symbol
Parameter
VOH
Output HIGH Level
VOL
Out'put LOW Level
V'H
Input HIGH Level
2.0
V'l
lu
Input LOW Level
-0.5
ILO
Typ.
Min.
,
2.4
Max.
Units
Vcc
0.4
V
Conditions
10H= -1.0 mA
V
10l = 3.2mA
V
Vcc
0.8
V
Input Leakage Current
10
iJ.A
V'N=OVtoVcc
Output Leakage Current
10
.vOUT = OV to Vcc
Icc
' Operating Supply Current
100
/lA
mA
158
. Standby Supply Current
12
'mA
Note 2
70
mA
Note 3
Output Short Circuit Current
los
Note 1
CAPACITANCE
'Note: This parameter is periodically sampled and is not 100% tested.
Symbol
Parameter
Max.
Unit
C,
Input Capacitance
5
pf
V'N=OV
Co
Output Capacitance
5
pf
VOUT=OV
Min.
Conditions
A.C. CHARACTERISTICS
Parameter
2365-2
2365A-2
Min.
Max.
2365-3
2365A-3
Min.
Max.
2365
2365A
Min.
Max.
tCYC
Cycle Time
200
300
450
tAA
Address Access Time
tOH
Output Hold After Address
Change
tAcE
Chip Enable Access Time
200
300
450
ns
tACS
Chip Select Access Time
85
100
150
ns
150
ns
Symbol
tAOE
tll
tHZ
.:,
,
10
Output Enable Access Time
Ouput LOWZ Delay
Power Up Time
tpD
Power Down Time
10
85
10
Output HIGH Z Delay
tpu
300
200
100
85
0
0
85
150
0
100
ns
ns
10
100
Condition
ns
450
10
10
Unit
150
NoteA
Note 4
ns
Note 5
ns
Note 6
ns
Note 4
ns
Note 4
Notes:
1. Measured with device selected and outputs unloaded.
2. Applies to "A" versions only and measured with CE =2.0V.
3. For a duration not to exceed 30 seconds.
'
,
4. Applies to "A" versions (power down) only.
5. Output low impedance delay (t[2) is measured from 'CE ,and DE a2!ng I~ and CS going active. whichever occurs last.
,6. Output high impedance delay (tHZ) is measured from either CE or OE going high or CS going inactive. whichever occurs first ..
2-28
SY2365/SY1365A
TIMING DIAGRAMS
Propagation Delay from Address (CE
=OE =LOW, CS/CS =Active)
ADDRESS
INPUTS
VALID ADDRESS
DATA
OUT
Propagation Delay from Chip Enable, Chip Select or Output Enable (Address Valid)
J41
\
{51
V
/1\
cs/cs
V
/1\
1-
VALID
_ 161
V
_{5{I~tLZ!.:!......
DATA
OUT
_ t,' {51
----
{cc
Vee CURRENT
(5B
- - - - - - 'I
I---'"z~
-~
\---
~
-,
+5V
A.C. TEST CONDITIONS
1250Q
Input Pulse Levels
Input Rise and Fall Times
Timing Measurement Levels: Input
Output
Output Load
O.BV to 2.2V
10 nsec
1.5V
O.BV and 2.0V
See Figure 1
DOUT------~------_i
77sn
100pl UNCLUD{NG SCOPE AND J{GI
Figure ,.
PROGRAMMING INSTRUCTIONS
All Synertek read only memories utilize computer aided techniques
Third Card
1-6
to manufacture and test custom bit patterns. The custom bit pattern
and address information is supplied on standard 80 column com·
puter cards in the format described below.
29
All addresses and related autp'Jt patterns must be completely de·
fined. Each deck of cards defining a specific ROM bit pattern
consists of 1) four Title Cards and 2) address and bit pattern Data
30
Cards. Positive logic is generally used on all input cards: a logic "1"
is the most positive or HIGH level, and a logic "O";s the most negative or LOW level. Synertek can also accept ROM data in other
formats, compatible with most microprocessors and PROMS. Consult your Synertek representative for details.
Fourth Card
31
32
1-8
A set of four Title Cards should accompany each data deck. These
Data Format. Synertak, or Intel data
starting in column one.
cards give our computer programs additional information necessary
1S-28
to accurately produce high density ROMS. These four Title Cards
must contain the following information:
COLUMN
3S-S7
1-30
31-S0
60-72
Customer name
Customer part number
1-30
31-S0
Customer contact (name)
Customer telephone number
Logic format; punch "POSITIVE
LOGIC" or "NEGATIVE LOGIC."
Truth table verification code; punch
either "VERIFICATION HOLD" (man-
INFORMATION
ufacturing starts after customer approval
of bit pattern data supplied by Synertek)
or "VERIFICATION NOT NEEDED"
Synertek part number (punch
(manufacturing starts immediately upon
"236S" or "236SA")
Second Card
pattern number to be
card format may be used. Specify format by punching "Synertek," or"lntel"
TITLE CARDS
First Card
Leave blank -
assigned by Synertek
CS4 chip select logic level (if LOW
selects chip, punch "0"; if HIGH
selects chip, punch ","; if DON'T
CAR E, punch "2"). If 236SA, leave
blank.
CS3 chip select logic level. If 236SA,
leave blank.
CS2 chip select logic level.
CS1 chip select logic level.
receipt of customer card deck)
2-29
SY2365/SY2365A
SYNERTEK DATA CARD FORMAT
All addresses are coded in decimal form (0 through 2047). All out·
put words are coded both in binary and octal forms. Output 11 (08).
is the MSB, and Output 1 (0,) is the LSB.
COLUMN
Data Cards
Data Cards
COLUMN
INFORMATION
1-5
Punch the 5·digit decimal equivalent of
the binary coded address which begins
each card. This is the initial input
address. The 'addr~ss is right justified,
INFORMATION
1-4
6-13
15-17·
22-25
27-34
36-38
43-46
48-55
57-59
64-67
69-76
78-80
Decimal address
Output (MSB·LSB)
Octal equivalent of output dataDecimal address
Output (MSB·LSB)
Octal equIvalent of output data
Decimal address
Output (MSB·LSB)
Octal equivalent of output data
Decimal address
Output (MSB·LSB)
Octal equivalent of output data
7-)4
i.e. 00000, 00008, 00016, etc.
Output data (MSB·LSB) for initial input
address.
16-23
25-32
34-41
43-50
52-59
61-68
70-77
79-80
Output data for initial input address +1
Output data for initial input address +2
Output data for initial input address +3
Output data for initial input add'ress +4
Output data for
Output data for
Output data for
ROM pattern
blank)
initial input address
initial input address
initial input address
number (may be
+5
+6
+7
left
INTEL DATA CARD FORMAT
Output data is punched as
as a HIGH, and an "N" is
MSB and Output 1 (0,)
above must accompany the
either a "P" or an "N"; a "P" is defined
defined as a LOW. Output 8 (08) is the
is the LSB. The four Title Cards listed
Intel card deck,
.
Send bit pattern data to the following special address:
Synertek - ROM
P,O. Box 552
Santa Clara, CA 95052
PACKAGE DIAGRAMS
CerDIP Dual In-Line
28 Leads
Plastic Dual In-Line
28 Leads
~.~~~~~:~~~~:]~
!_,.460TYP±.030
I
I
0.0.0
_0.600:1: .010_ ~
gEl I I~~
0.009_ _
0.015
_
I,
I
I- i l l ! -I--'1:
-O.D50TYP
f
•
I_0.660±.010~1 M~~"'" I~
0.145
±.010
1
0.Q15
(1625
.- .
2-30
~~
= ~. .~=
~
0.009~_ t I
j t
+0.025_1
-0.015
0.075
:1:0.015-
+1
1__I 1_
0.,00
0.018
TYP
10.003
_11_
0.125
MIN
16,384 x 8 Stade
Read Only Memory
SY23128
MEMORY
PRODUCTS
SYNERTEK
PRELIMINARY
A SUBSIDIARY OF HONEYWELL
•
•
•
•
2764 EPROM Pin Compatible
16,384 x 8 Bit Organization
Single +5 Volt Supply
Access Time - 200 ns (max)
o Totally Static Operation
• Completely TTL Compatible
•
•
•
•
•
•
The SY23128 high performance Read Only Memory is
organized 16,384 words by 8 bits with an access time of
200ns. The ROM is designed to be compatible with all
microprocessor and similar applications where high performance large bit storage and simple interfacing are
important design considerations. It conforms to the
JEDEC approved pinout for 28 pin 128K ROMs.
standby mode as long as CE remains high. This unique
feature provides system level power savings as much
as 90%. An additional feature of the SY23128 is the
Output Enable (OE) function. This eliminates bus contention in multiple bus microprocessor systems. The
programmable chip select allows up to two 128K ROMs
to be OR-tied without external decoding.
The SY23128 offers an automatic power down feature.
Power down is controlled by the Chip Enable (CE)
input. When CE goes high, the device will automatically power down and remain in a low power
The SY23128 is pin compatible with the 2764 EPROM
thus eliminating the need to redesign printed circuit
boards for volume mask programmed ROMs after prototyping with EPROMs.
PIN CONFIGURATION
BLOCK DIAGRAM
NC
Vee
A12
CS,
A,
An
A,
As
As
A.
A,
An
A3
OE
A,
A"
A,
CE
Ao
Os
0,
0,
0,
0,
03
05
GND
0,
28 Pin JEDEC Approved Pinout
Automatic Power Down (CE)
Output Enable Function (OE)
Programmable Chip Select
Three State Outputs for Wire-OR Expansion
EPROMs Accepted as Program Data Input
131,012 BIT
ROM ARRAY
(512x2561
COLUMN SELECT
CIRCUITRY
IBOF 2561
0,
>---'--0,
0,
'----'-I">~..:--04
0,
'-----'-1.)>:------'--0,
0,
'-------'>--=--0,
DE
POWEROOWN
CS,
OUTPUT ENABLE
·CHIP SELECT (es) IS PROGRAMMABLE LOW ACTIVE OR HIGH ACTIVE
2-31
SY3308
1024 x 8 High Speed
Read Only Memory
MEMORY
PRODUCTS
SYNERTEH
A SUBSIDIARY OF HONEYWELL
•
•
•
•
•
•
Access Time - 70 ns (max)
Single +5 Volt Supply
Contact Programming
Four Week Prototype Turnaround
Completely TTL Compatible
Totally Static Operation
• Pin Compatible with 8K Bipolar PROMsReplaces 7681 or 82S181
• Three-State Outputs for Wire-OR Expansion
• Four Programmable Chip Selects
• 8K Bipolar PROMs Accepted as Program
Data Inputs
The Synertek SY3308 is a high speed 8192-bit static
mask programmable Read Only Memory organized
1024 words by 8 bits_ Designed to be compatible
with industry standard 8K bipolar PROMs, it eliminates the need to redesign printed circuit boards for
volume production after prototyping with PROM's.
The device offers full TTL compatibility on all inputs
and' outputs and operates on a single +5V power
supply. The three-state output buffers facilitate system expansion by allowing outputs to be wire-O Red
together. These features, combined with a maximum
, access time of 70 nsec, make the SY3308 suitable for
application where high performance, large bit storage
and simple interface are important' design considerations.
The SY3308 utilizes fully static circuitry and operates
asynchronously so no clocks are required. The four
chip select buffers are mask programmable to, be any
combination of high active, low active or don't care
that is desired. This allows up to sixteen ROM's to be
OR-tied without external decoding.
The SY3308 is fabricated using Synertek's scaled,
high performance N-channel MaS technology, This,
combined with innovative design techniques, provides the high performance and ease-of-use features
associated with non-clocked static memories.
BLOCK DIAGRAM
PIN CONFIGURATION
A,
Vee
A,
A,
A5
A,
A,
A3
cs,
cs,
A,
CS3
A,
CS,
Ao
0,
0,
0,
02
0,
Vee
GND
r
r
8192 BIT
ROM
CELL ARRAY
05
0,
ORDERING INFORMATION
Order
Number
Package
Type
Access
Time
Temperature
Range
SYC3308
Ceramic
70 ns
O°C to +75°C
SYD3308
Cerdip
70 ns
O°C to +75°C
AO
A custom number will be assigned by Synertek,
2-32
A,
SY3308
ABSOLUTE MAXIMUM RATINGS*
COMMENT*
_10°C to +85°C
Ambient Operating Temperature
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. These are stress ratings only. Functional
operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure
to absolute maximum rating conditions for extended
periods may affect device reliability.
-65°C to +150°C
Storage Temperature
Supply Voltage to Ground Potential
-1.5V to +7.0V
Applied Output Voltage
-1.5Vto+7.0V
Applied Input Voltage
-1.5V to +7.0V
1.0W
Power Dissipation
D.C. CHARACTERISTICS
T A = 0 ° C to +75°C, Vee = 5.0V ± 10% (unless otherwise specified) (Note 1)
Symbol
VOH
VOL
V,H
V,L
ILl
!Lo
Ise
lee
Parameter
Min.
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Output Short Circuit Current
Power Supply Current
Typ.
2.4
2.0
-1.0
-10
-80
Max.
Units
Vee
0.45
Vee
0.8
10
10
Volts
Volts
Volts
Volts
f.1A
f.1A
mA
mA
120
Test Conditions
Vee
Vee
= 4.5V,
= 4.5V,
IOH
IOL
= -2.4mA
= 10mA
Vee = 5.5V, OV <; Vin <; Vee
Chip Deselected, Vout = OV to Vee
Duration not to exceed 30 sec.
Output Unloaded
Vee = 5.5V, Vin = Vee
A.C. CHARACTERISTICS
T A = O°C to +75°C, Vee = 5.0V ± 10% (unless otherwise specified) (Note 1)
Symbol
tAee
teo
tOF
tOH
Parameter
Min.
Address Access Time
Chip Select Delay
Chip Deselect Delay
Previous Data Valid Aiter
Address Change Delay
0
5
Max.
Units
70
40
40
ns
ns
ns
ns
Max.
Units
Test Conditions
See A.C. Test Conditions
CAPACITANCE
tA = 25°C, f = 1.0MHz
Symbol
CI
Co
Parameter
Min.
Input Capacitance
Output Capacitance
5
8
pF
pF
Test Conditions
Vin = OV
V out = OV
NOTE: This parameter is periodically sampled and is not 100% tested.
TIMING DIAGRAM
ADDRESS
INPUTS
~~
____________V_A_L_'D_______________
CHIP
SELECT
INPUTS
DATA
OUTPUTS
HIGH IMPEDANCE
i--------tAcc------+i
(See following page for notes.)
2-33
SY3308
+5V
A.C. TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Levels
Output Load
470n
GND to 3.0 Volts
5 nsec
DOUT------~~----_+
--+
T 30pF (INCLUDING SCOPE AND JIG)
1.5 Volts
See Figure 1
'KnfL....____
~
Figure 1.
PROGRAMMING INSTRUCTIONS
All Synertek read only memories utilize computer aided techniques
to manufacture and test custom bit patterns. The custom bit pattern
and address information is supplied on standard 80 column computer cards in the format described below.
All addresses and related outP1Jt patterns must be completely defined. Each deck of cards defining a specific ROM bit pattern
consists of 1) four Title Cards and 2) address and bit pattern Data
Cards. Positive logic is generally used on all input cards: a logic "1"
is the most positive or HIGH level, and a logic "0" j's the most negative or LOW leveL Synertek can also accept ROM data in other
forma'ts, compatible with most microprocessors and PROMS. Consult your Synertek representative for details.
SYNERTEK DATA CARD FORMAT
All addresses are coded in decimal form (0 through 2047). All output words are coded both in binary and octal forms. Output {3 (Oa)
is the MSB, and Outpu, 1 (O,).is 'he LSB.
TITLE CARDS
A set of four Title Cards should accompany each data deck. These
cards give our computer programs additional information necessary
to accurately produce high density ROMS. These four Title Cards
must contain the following information:
INFORMATION
1-30
31-50
60-72
Second Card
1-30
31-50
1-6
Customer name
Customer part number
Synertek part number (punch
"3308")
Customer contact (name)
Customer telephone number
Leave blank - pattern numbEr to be
assigned by Synertek
29
Fourth Card
30
31
32
1-8
15-28
35-57
1-4
6-13
15-17
22-25
27-34
36-38
43-46
48-55
57-59
64-67
69-76
78-80
Decimal address
Output (MSB·LSB)
Octal equivalent of
Decimal address
Output (MSB·LSB)
Octal equivalent of
Decimal address
Output (MSB·LSB)
Octal equivalent of
Decimal address
Outpu, (MSB·LSB)
Octal equivalent of
output data
output data
output data
output data
INTEL DATA CARD i'ORMAT
COLUMN
First Card
Third Card
INFORMATION
COLUMN
Data Cards
CS4 chip select logic level (if LOW
selects chip, punch "0"; if HIGH
selects 'chip, punch "1"; if DO·NT
CAR E, punch "2").
CS3 chip select logic level.
CS2 chip select logic level.
CS1 chip select logic level.
Data Format. Synertek, or Intel data
card format may be used. Specify format by punching "Synertek," or"lntel"
starting in column one.
Logic format; punch "POSITIVE
LOGIC" or "NEGATIVE LOGIC."
Truth table verification code; punch
ei,her "VERIFICATION HOLD" (man·
ufacturing starts after customer approval
of bit pattern data supplied by Synertek)
or "VERIFICATION NOT NEEDED"
(manufacturing starts immediately upon
receipt of customer card deck)
Output datrl is punched as
as a HIGH, and an "N" is
MSB and Output 1 (01)
above must accompany the
Data Cards
either a "p" or an "N"; a "P" is defined
defined as a LOW. Output 8 (Oa) is the
is the LSB. The falir Title Cards listed
Intel card deck.
COLUMN
INFORMATION
1-5
Punch the 5-digit decimal equivalent of
the binary coded address which begins
each card. This is the initial input
address. The address is right justified,
i.e. 00000, 00008,00016. e'c.
Output data (MSB-LSB) for initial input
address.
Output data for initial input addr%s +1
Output data for ,initial input address +2
Output data for initial input address' +3
Output data for initial input address +4
Output' data for initial input address +5
Output data for initial input address +6
Output data for initial input addre-ss +7
ROM pattern nunlber (may be left
blank)
7-14
16-23
25-32
34-41
43-50
52-59
61-68
70-77
79-80
Send bit pattern data to the following special address:
Synertek - ROM
P.O. Box 552
Santa Clara, CA 95052
NOTES:
1. The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per
minute.
2-34
SY3308
PACKAGING DIAGRAM
CERAMIC PACKAGE
P'"NO
IDENT
~
...
I
D
0.610
il5Bo
~
1.230
CERDIP PACKAGE
2-35
SY3316/SY3316A
MENiORY
PR.ODUCTS
A SUBSIDIARY OF HONEYWELL
•
•
•
•
•
•
Access Time - 80ns (max)
Single +5 Volt Supply (± 10%)
Contact Programming
Four Week Prototype Turnaround
Completely TTL Compatible
Totally Static Operation
•
•
SY3316A - Automatic PowerDown (EE)
Pin Compatible with 16K Bipolar PROMs Replaces 3636 or 82S191
o Three-State Outputs for Wire-OR Expansion
o Three Programmable Chip Selects (two on SY3316A)
o 16K Bipolar PROlllls Accepted as Program Data Inputs
The SY3316 and SY3316A are high speed 16,384 bit static
mask programmable Read Only Memories organized 2048
words by 8 bits. Designed to be pin compatible with 16K
bipolar PROMs, they eliminate the need to redesign printed
circuit boards for volume production after prototyping with
PROMs.
power savings of as much as 80%. The two programmable
chip selects (CS) allow as many as four ROMs to be OR-tied
without external decoding.
The SY3316A offers an automatic power down feature.
Power down is controlled by the Chip Enable (EE) input.
When CE goes high, the device will automatically' power
down and remain in a standby power mode as long as CE
remains high. This unique feature provides system level
Both devices are fabricated using Synertek's scaled high
performance N-channel MOS technology. This, combined
with innovative design techniques, provides the high performance and ease-of-use features associated with static
memories.
PIN CONFIGURATIONS
BLOCK DIAGRAM
The SY3316 offers somewhat simpler operation than the
SY3316A. It's three programmable chip selects allow up to
eight ROMs to be OR-tied without external decoding.
A,
Vee
A,
Vee
A.
A,
A.
A,
As
A,
As
A,
A,
AlO
A,
A,.
A,
cS,
A,
CE
A2
CS2
A2
CS,
A,
A,
cs,
A,
CS2
A,
A.
0,
A.
0,
As
0,
0,
0,
0,
02
o.
02
0,
0,
05
0,
05
GND
0,
GND
0,
Vee
GND
r
r
16.384 BIT
A,
ROM
CELL ARRAY
A,
A,
A,
ORDERING INFORMATION
Order
Number
SYC3316
SYD3316
SYC3316A
SYD3316A
Access
Time
80
80
80
80
ns
ns
ns
ns
Operating
Current
Standby
Current
Package
Type
120mA
120mA
120mA
120mA
NA
NA
20mA
20mA
Ceramic
Cerdip
Ceramic
Cerdip
AO
A custom number will be assigned by Synertek.
2-36
SY33t6/A
ABSOLUTE MAXIMUM RATINGS*
Ambient Operatfng Temperature
COMMENT*
_10°C to +S5°C
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. These are stress ratings only. Functional
operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure
to absolute maximum rating conditions for extended
periods may affect device reliability.
_65°C to +150°C
Storage Temperature
Supply Voltage to Ground Potential
-1.5V to +7.0V
Applied Output Voltage
-1.5V to +7.0V
Applied Input Voltage
-1.5V to +7.0V
1. OW
Power Dissipation
D.C. CHARACTERISTICS
TA = o°c to +75°C, Vee = 5.0V ± 10% (Note 1)
Symbol
VOH
VOL
VIH
VIL
III
ILO
Ise
Icc
ISB
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Output Short Circuit Current
Power Supply Current
Standby Supply Current
Typ.
Min.
2.4
2.0
-1.0
-10
-100
Max.
Units
Vee
0.45
Vee
O.S
10
10
Volts
Volts
Volts
Volts
/lA
/lA
mA
mA
mA
120
20
Test Conditions
Vee = 4.5V, IOH = -2.4mA
Vee = 4.5V, IOL = 10mA
Vee = 5.5V, OV .;; Vin .;; Vee
Chip Deselected, Vout = OV to Ve e
Note 5
Note 2
Note 3
A.C. CHARACTERISTICS
TA = O°c to +75°C, Vee = +5V ± 10% (Note 1)
Symbol
tAee
tAeE
tAes
tOFF
tOH
tpu
tpD
Parameter
Min.
Address Access Time
Chip Enable Access Time
Chip Select Access Time
Chip Deselect Time
Output Hold Time
Power Up Time
Power Down Time
Typ.
Max.
Units
SO
SO
40
40
ns
ns
ns
ns
ns
ns
ns
0
5
0
40
Test Conditions
Note 4
Note 4
Note 4
CAPACITANCE
tA = 25°C, f = 1.0MHz
Symbol
CI
Co
Parameter
Min.
Input Capacitance
Output Capacitance
Max.
Units
5
S
pF
pF
Test Conditions
Vin = OV
V out =OV
NOTE: This parameter is periodically sampled and is not 100% tested.
NOTES:
1. The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute.
2. Device selected with outputs unloaded.
3. Applies to SY3316A only with eE = 2.0V.
4. Applies to SY3316A only.
5. Output short circuit current is measured with VOUT = OV, one output at a time with a maximum duration of 30 seconds.
2-37
SY33t6/A
TIMING DIAGRAMS
Address to Output Delay (CS Active and CE Low)
VALID
ADDRESS
b"'3
OUTPUTS
VALID
Chip Enable/Chip Select to Output Delay (Address Valid)
v
'I
1\
I - - -t o , , 1 4 I -
!--------tACE(41---------I
'IV
CHIP SELECTS
\11
VALID
I--to,,~
!----tAcs----+!
_ _ _ =£
____.
OUTPUTS-------------t-------------------------------K\~____________+_----~v-A-L-rD------JI~
ICC" -
CURRENT
___
-...:~~ul-
po
----..,.-I---t
50%
50%
Is. --------------------+5V
A.C. TEST CONDITIONS
470n
Input Pulse Levels
Input Rise and Fall Times
Timing Reference Levels: Input
Output
Output Load
DOUT-------,~J------.
O.4V to 2.4V
5 nsec
1.5V
O.8V and 2.0V
See Figure 1
lKll
tL..____.....t
30pF (INCLUDING SCOPE AND JIG)
~
Figure 1.
PROGRAMMING INSTRUCTIONS
All Synertek read only memories utilize computer aided techniques
Second Card
to manufacture and test custom bit patterns. The custom bit pattern
and address information is supplied on standard 80 column computer cards in the format described below.
Third Card
30
All addresses and related outP'jt patterns must be completely defined. Each deck of cards defining a specific ROM bit pattern
consists of 1) four Title Cards and 2) address and bit pattern Data
Cards. Positive logic is generally used on all input cards: a logic "1"
is the most positive or HIGH level, and a logic "0" is the most nega·
tive or LOW level. Synertek can also accept ROM data in other
formats, compatible with most microprocessors and PROMS. Can·
suit your Synertek representative for details.
1-30
31-50
1-6
Fourth Card
31
32
1-8-
TITLE CARDS
A set 'of four Title Cards should accompany each data deck. These
cards give our computer programs additional information necessary
to accurately produce high density ROMS. These four Title Cards
must contain the following information:
COLUMN
First Card
1-30
31-50
60-72
INFORMATION
Customer name
Customer part number
Synertek part number (punch
"3316" or "33'6A")
2-38
15-28
35-57
Customer contact (name)
Customer telephone number
Leave blank - pattern number to be
assigned by Synertek
CS3/CSO chip select logic level (if LOW
selects chip, punch "0"; if HIGH selects
chip, punch ","; if DON'T CARE,
punch "2")
CS2/CS2 chip select logic level.
CS, /CS, chip select logic level.
Data Format. Synertek, or Intel' data
card format may be used. Specify format by punching "Synertek," or"lntel"
starting in column one.
Logic format; punch "POSITIVE
LOGIC" or "NEGATIVE LOGIC."
Truth table verification code; punch
either "VERIFICATION HOLD" (manufacturing starts after customer approval
of bit pattern data supplied by Synertek)
or "VERIFICATION NOT NEEDED"
(manufacturing starts immediately upon
receipt of customer card deck)
SY3316/A
SYNERTEK DATA CARD FORMAT
Data Cards
All addresses are coded in decimal form (0 through 2047). All out·
COLUMN
1-5
INFORMATION
Punch the 5-digit deCimal equivalent of
put words are coded .both in binary and octal forms. Output 13 (Os)
the binary coded address which begins
is the MSB. and Output 1 (01) is the LSB.
each
Data Cards
COLUMN
1-4
6-13
15-17
22-25
27-34
36-38
43-46
48-55
57-59
64-67
69-76
78-80
card.
This
is the initial input
address. The address is right justified, .
INFORMATION
Decimal address
7~14
Output (MSB·LSB)
i.e. 00000, 00008, 00016, etc.
Output data (MSB-LSB) for initial input
address.
Octal equivalent of output data
Decimal address
16-23
25-32
34-41
43-50
52-59
61-68
70-77
79-80
Output (MSB·LSB)
Octal equivalent of output data
Decimal address
Output (MSB·LSB)
Octal equivalent of output data
Decimal address
Output (MSB·LSB)
Output data for initial input address +1
Output data for initial input address +2
Output data for initial input address +3
Output data for initial input address +4
Output data for initial input address +5
Output data for initial input address +6
Output data for initial input address +7
ROM
pattern number (may be left
blank)
Octal equivalent of output data
INTEL DATA CARD FORMAT
Output data is punched as either a "P" or an "N"; a "P" is defined
Send bit pattern data to the following special address:
as a HIGH, and an "N" is defined as a LOW. Output 8 (Os) is the
MSB and Output 1 (01) is the LSB. The four Title Cards listed
Synertek - ROM
P.O. Box 552
Santa Clara, CA 95052
above must accompany the Intel card deck.
PACKAGE DIAGRAMS
Cera mic Package
:::~I::[:::J:]]
I
I
1.230
Cerd ip Package
2-39
2048 x 8 High Speed
Read Only Memory
SYM3316/
SYM3316A
MEMORY PRODUCTS
Extended Temperature
SYNERTE~ Range (-55°C t0 +tzsOC)
PRELIMINARY
ASUBSIDIAAYOFHONEYWELl
•
•
o
•
•
•
Access Time - lOOns (max.)
Single +5 Volt Supply (± 10%)
Contact Programming
Four Week Prototype Turnaround
Completely TIL Compatible
Totally 'Static Operation
•
•
SYM 3316A - Automatic Power Down (CE)
Pin Compatible with 16K Bipolar PROMs Replaces 3636 or 82S191
o Three-State Outputs for Wire-OR Expansion
• Three Programmable Chip Selects (two on SYM 3316A)
o 16K Bipolar PROMs Accepted as Program Data Inputs
The SYM 3316 and SYM3316A are high speed 16,384 bit
static mask programmable Read Only Memories organized
2048 words by 8 bits. Designed to be pin compatible with
16K bipolar PROMs, they eliminate the need to redesign
printed circuit boards for volume production after prototyping with PROMs,
power savings of as much as 80%, The two programmable
chip selects (CS) allow as many as four ROMs to be OR-tied
without external decoding,
The SYM3316 offers somewhat simpler operation than the
SYM3316A. It's three programmable chip selects allow up to
eight ROMs to be OR-tied without external decoding,
The SYM3316A offers an automatic power down feature.
Power down is controlled by the Chip Enable (EE) input
When CE goes high, the device will automatically power
down and remain in a standby power mode as long as CE
remains high. This unique feature provides system level
Both devices are fabricated using Synertek's scaled high
performance N-channel MaS technology. This, combined
with innovative design techniques, provides the high performance and ease-of-use features associated with static
memories,
PIN CONFIGURATIONS
BLOCK DIAGRAM
A,
A,
A5
A,
AJ
A2
A,
Ao
Vee
0,
a,
a,
a,
a,
05
02
oJ
a,
GND
A,
Vee
A,
A5
A,
AJ
A2
A,
Ao
0,
02
oJ
A8
A,
A10
cs,
CS2
CSJ
a,
GND
r
A10
CE
cs,
CS2
08
AJ
A,
A5
A,
SYMC3316
SYMD3316
SYMC3316A
SYMD3316A
Access
Time
100
100
100
100
ns
ns
ns
ns
05
A8
A,
a,
Operating Standby Package
Type
Current Current
120 mA
120 mA
120mA
120 mA
NA
NA
20 mA
20 mA
~
"0
:::
~
"
0
A,
ORDERING INFORMATION
Order
Number
GND
Vee
A8
A,
Ceramic
Cerdip
Ceramic
Cerdip
A custom number will be assigned by Synertek,
2-40
frl
"s:0
a:
16,384 BIT
ROM
CELL ARRAY
r
Microprocessors
Page
Microcomputers
Z8'"
Single-Chip Microcomputer ................................ 3-3
Microprocessors and Peripherals
SY1791-021
SY1793-02
Floppy Disk Controller (FDC)
SY2661
Enhanced Programmable Communications Interface ........ 3-39
3-23
SY6500
8-Bit Microprocessor Family .............................. 3-53
SYE6500/6500A
8-Bit Microprocessor Family (Extended Temperature) ....... 3-65
SY6520/6520A;
SY6820/68B20
Peripheral Interface Adapter (PIA) ......................... 3-67
SYE6520/6820;
SYE6520A/68B20
Peripheral Interface Adapter (Extended Temperature) .: ..... 3-79
SY6521 16821 ;
SY6521 A/68B21
Peripheral Interface Adapter (PIA) ......................... 3-81
SYE6521/6821 ;
SYE6521 A/68B21
Peripheral Interface Adapter (Extended Temperature) ....... 3-93
SY6522/6522A
Versatile Interface Adapter ................................ 3-95
SYE6522/6522A
Versatile Interface Adapter (Extended Temperature)
SY6530
Memory, 110, Timer Array
SY6532
RAM, 110, Timer Array
SYE6532/6532A
RAM, 110, Timer Array (Extended Temperature)
..........
3-137
SY6545
CRT Controller ........................................
3-139
SY6545-1
CRT Controller ........................................
3-155
SY6551
Asynchronous Communication Interface Adapter .........
3-169
SYE655116551 A
Asynchronous Communication Interface Adapter
(Extended Temperature) ................... .i . . . . . . . . . . . .
3-177
SY659116591 A
Floppy Disk Controller (FDC)
3-179
SY6691 16692
ANSI Rigid Disk Controller (ARDC'")
SY68045
CRT Controller (CRTC)
3-2
......
3-115
..............................
3-117
.................................
3-129
............. ,.............
....................
3-183
................................
3-185
ZSTM
Single-Chip
Microcomputer
PRODUCT
SPECIfiCATION
SYNERTEK:
A SUBSIDIARY OF HONEYWELL
PRELIMINARY
Description
The Z8 microcomputer introduces a
new level of sophistication to single-chip
architecture. Compared to earlier singlechip microcomputers, the Z8 offers
faster execution; more efficient use of
memory; more sophisticated interrupt,
input/output and bit-manipulation capabilities; and easier system expansion.
Under program control, the Z8 can
be tailored to the needs of its user. It can
Features
o
Pin
Description
Complete microcomputer with on-chip
RAM, ROM and VO
o 128 bytes of on-chip RAM
o 2K bytes of on-chip ROM
o 32 I/O lines
o Two programmable 8-bit counter/timers,
each with a 6-bit programmable prescaler
o Full-duplex UART clocked by an internal
timer
o 144-byte register file includes:
o 124 general-purpose registers, each of
which can be used as an accumulator,
index register, storage element, address
register or part of the internal stack
o Four I/O port registers
o Sixteen status and control registers
for programming and polling the Z8
Microcomputer
o Register pointer permits shorter, faster
instructions to access one of nine workingregister groups
o Vectored, prioritized interrupts for I/O,
counter/timers and UART
o Expandable bus interfaces up to 62K bytes
each of external program memory and
external data memory
o On-chip oscillator can be driven by a
crystal, RC, LC or external clock source
o High-speed instruction execution
POa-P07. Pla-PI7. P2a-P27. P3a-P37' I/O Port
Lines (Input/Outputs, TTL compatible). These
32 lines are divided into four 8-bit VO ports
be configured as a stand-alone microcomputer with 2K of internal ROM, a
traditional microprocessor that manages
up to 124K of external memory, or a
parallel-processing element in a system
with other processors and peripheral
controllers linked by the Z-Bus. In all configurations, a large number of pins remain
available for I/O.
XTAL
OUTPUT INPUT
110
(BIT PROGRAMMABLE)
3-3
os RIW RESET
ADDRESS OR 110
ADDRESS/DATA OR I/O
(NIBBL.E PROGRAMMABLE) (BYTE P~OGRAMMABLE)
ngure 1. Z8 Block Diagram
o Working-register operations = 1.5 JI.S
o Average instruction execution = 2.2 JI.S
o Longest instruction = 5 JI.S
o Low-power standby mode retains contents of
general-purpose registers
o Single + 5 V supply
o All pins TTL compatible
that can be configured under program control
for I/O or external memory interface.
Copyright 1979 by Zilog. Inc. All rights reserved. No part of this publication may be
reproduced, stored in a retrieval system, or transmitted, in any form or by any means,
electronic, mechanical, photocopying, recording. or otherwise, without the prior written
permiSSion of Zilog. Reproduced by pe"rmission.
Z8, Z-UPC, Z-Bus are trademarks of ZlIog, Inc.
AS
Pin
Description
(Cont.)
AS. Address Strobe (output, active Low),
Address Strobe is pulsed once at the
beginning of each machine cycle.
Addresses are output via Ports 0 and 1
for internal and external program
fetches and external data memory
transfers. The addresses for all external
program or data memory transfers are
valid at the trailing edge of AS. Under
program control, AS can be placed in
the high-impedance state along with
Ports 0 and 1" Data Strobe and
, 'Read/Write. '
RlW. Read/Write (output). RIW is Low when
the Z8 is writing to external program or data'
memory.
XTALI. XTAL2. Crystal 1, Crystal 2 (time-base
input and output). These pins connect a seriesresonant crystal (8 MHz maximum), LC network, RC network or an external single-phase
clock (8 MHz maximum) to the oncchip clock
oscillator and buffer.
RESET. Reset (input, active Low). RESET initializes the Z8 .. When, RESET is deactivated,
the Z8 begins program execution from internal
program location POOCH.
OS. Data Strobe (output,.active Low). Data
Strobe is activated once for each external
memory transfer.
'
XTAL2
XTALI
39 P3,
3
38 P27
P37 4
37 P2, .
P3" 5
36 P2s
REm 6
35 P2"
34 P23
RJW
RESET
TIMIIIOI
AIIO
CONTROL
40 P3,
Vee
7
PORTO
(NIBBLE
PROGRAMMABLE)
RJW
liS
Vee
GND
XTAL1
AS
XTAL2
Po.
P20
PO,
P2,
Po.
P20
Po"
P2,
PO,
P2,
P2,
~ 8
33 P22
AS 9
32 P2,
PD,
P3s 10
31 P20
Pile
P20
GN,D 11
3D P33
Po,
P2,
Pa,
IJOOR~-A'5
P3, 12
29 P3..
P1.
Po. 13
28 Pi 7
P1,
P31
PO, 14
27 Pi,
P1,
P3,
~02
.15
26 P1 s
P1,
Pa,
PD3 16
P1,
P3,
POs 18
25 P1"
24 P1 3
23 P1 2
P1,
P3.
PO, 19
22 P1,
Po, 20
21 P1 0
PO.. 17
PORT 1
(BYTE
PROGRAMMABLE)
110 OR ADo-AD7
P1,
P3,
P1,
P3,
Figure 2. Pin Asslgaments
} CLOCK
PORTa
(BIT PRO·
GRAMMABLE)
110
PORTa
(FOUR INPUT:
FOUR OUTPUT).
SEAIALAND
PARALLEL 1/0
ANDCONTAOL
Figure 3. Pin FunctlODB
Architecture
Z8 architecture is characterized by a flexible
I/O scheme, an efficient register and address
space structure and a number of ancillary
features that are helpful in many applications.
Microcomputer applications demand powerful I/O capabilities. The Z8 fulfills this with
32 pins dedicated to input and output. These
lines are grouped into four ports of eight lines
each and are configurable under software control to provide timing, status Signals, serial or
parallel I/O with or without handshake, and an
address/data bus for interfacing external
memory.
Because the niultiplexedaddress/data bus
is merged with the I/O-oriented ports, the Z8
can assume many different memory and va
configurations.' These confii;Jiirations range
from a self-contained microcomputer to a
microprocessor that can address 124K of exter.
nal memory. ,
The Z8 offers' three basic address spaces to
support this Wide range of configurations: program memory (internal and external), data
memory (external) and the register file (internal). The 144-byte random-access register file
is composed of 124 general-purpose registers,
4 I/O'port registers, and 16.control and status
registers.
,
To unburden the program from coping with
real-time problems such as serial data communication and counting/timing, the Z8, offers
an on-chip asynchronous receiver/transmitter
{UARTi, and two counter/timers with a large
number of user-selectable modes. Hardware
support for the UART is minimized because
one of the on-chip timers supplies the bit rate.
Address
Spaces
Program Memory. The 16-bit program
counter addresses 64K bytes of program
memory space. Program memory can be
located in tWo areas: one internal and the
other external (Figure 4). The first 2048 bytes
consist of on-chip mask-programmed ROM. At
addresses 2048 and greater, the Z8 executes
external program memory fetches.
The first 12 bytes of program.memory are
reserved for the interrupt vectors. These locations contain 'six 16-bit vectors that correspond
to the six available interrupts.
,
3-4
'
Address
Spaces
(Cont.)
Data Memory. The ZBcan address 62K bytes
of external data memory beginning at locations
2048 (Figure 5). External data memory may be
included with or separated from the external
program memory space. DM, an optional I/O
function that can be programmed to appear on
pin P3 4 , is used to distinguish between data
and program memory space.
Register File. The 144-byte register file
includes four 1/0 port registers (RO-R3), 124
general-purpose registers (R4-RI27) and sixteen control and status registers (R240-R255).
These registers are assigned the address locations shown in Figure 6.
Z8 instructions can access registers directly
or indirectly with an 8-bit address field. The Z8
also allows short 4-bit register addressing
6553Sr-----------,
using the register pointer (one of the control
registers). In the 4-bit mode, the register file
is divided into nine working-register groups,
each occupying sixteen contiguous locations
(Figure 7). The register pointer addresses the
starting locatio~ of the active working-register
group.
Stacks. Either the internal register file or the
external data memory can be used for the
stack. A 16-bit stack pointer (R254 and R255)
is used for the external stack, which can reside
anywhere in data memory between locations
2048 and 65535. An 8-bit stack pointer (R255)
is used for the internal stack which resides
within the 124 general-purpose registers
(R4-RI27).
65535 , - - - - - - - - - - .
eXTERNAL
ROM OR RAM
;~!~ 1-----------1
ON·CHIP
ROM
lo~atlonor
Hrs!
b~'e
at
i:~r~Uc~~~:~~ ~
11
10
___________ _
EXTERNAL
DATA
MEMORY
IROS
lAOS
IR04
IRQ4
lRCJ
Interrupt
Vector
(lower 8~tel
6
Interrupt
Vector
IUppe, Bylel
[RCJ
5
IR02
4,
IRQ2
3
IRQ1
~g:~ I - - - - - - - - - - - l
IRQ1
NOT ADDRESSABLE
IROO
IROO
Figure 5. Data Memory Map
Figure 4. Program Memory Map
IDENTIFIERS
LOCATION
255
STACK POINTER (6ITS 7·0)
SPL
254
STACK POINTER (BITS 15-8)
SPH
'"
REGISTER POINTER
252
PROGRAM CONTROL FLAGS
FLAGS
251
INTERRUPT MASK REGISTER
IMR
INTERRUPT REQUEST REGISTER
IRa
249
INTERRUPT PRIORITY REGISTER
IPR
246
PORTS 0-' MODE
247
PORT 3 MODE
P2M
TO PRESCALER
PREO
244
TIMER/COUNTER 0
11 PRESCAlER
242
TIMER/COUNTER 1
240
>----provided by the r8gisle, poinler speeilin
Iheaelivewo,king·regl.lerg,oup.
......_ _ _ _ _ _ _ _--.127
--1
--11------1
--11----------1
--11----------1
P3M
PORT 2 MODE
245
243
L...._ _ _ _ _ _ _ _....I 240
,Ttle\lppernlbbl801 the legister1iIeaddreu
P01M
246
T,
PRE1
T1
TIMER MODE
TMR
SERIAL 110
510
1-1~=3:=::::;====:::::j255
--11--""-'' -'.: ",-,': . '--,-,-,':....:.,',::'..:'_-1"3
RP
NOT
IMPLEMENTED
Ttletowe,
nibbtacl
~1
__ ll---------l
ttleregiste'
!ite.ddIUs
SPECIFIED WORKING·
REGISTER GROUP
127
GENERAL· PURPOSE
REGISTERS
PORT 3
P3
PORT 2
P2
PORT 1
P1
PORTO
P'
provided by
ttlelnstructlon
point. 10 the
specilied
.egister.
--11----------115
--1
f----'/OPORTS-----
3
REGISTER FILE
Figure 7. The Register Pointer
Figure 6. The Register File
3-5
I/O
Ports
Port 1
Port 0
The Z8 has 32 lines dedicated to input and
output. These lines are grouped into four ports
of eight lines each and are configurable as
input, output or address/data. Under software
control, the ports can be programmed to provide address outputs, timing, status signals,
Port 1 can be programmed as a byte I/O
port or as an address/data port for interfacing
external memory. When used as an I/O port,
Port 1 may be placed under handshake control. In this configuration, Port 3 lines P33 and
P34 are used as the handshake controls RDYI
and DAVI (Ready and Data Available).
Memory locations greater than 2048 are
referenced through Port 1. To interface external memory, Port 1 must be programmed for
the multiplexed address/data mode (ADoAD7). If more than 256 external locations are
required, Port 0 must output the additional
lines.
Port 1 can be placed in the high-imp~dance
state along with Port 0, AS, DS and R/W,
Port 0 can be programmed as a nibble
I/O port, or as an address port for interfacing
external memory. When used as an I/O
port, Port 0 may be placed under handshake control. In this configuration, Port 3
lines P32 and P35 are used as the handshake controls DA VO and RDYO.
For external memory references, Port 0
can provide address bits As-All (lower nibble)
or As-AI5 (lower and upper nibble) depending on the required address space. If the
address range requires 12 bits or less, the
upper nibble of Port 0 can be programmed
independently as I/O while the lower nibble is
Port 2
PORT 1
(110 OR AD o-AD1)
HANDSHAKE CONTROLS
} DAV1 AND ROYl
(P3, AND P3J
Pori 1
allowing the Z8 to share common resources in
multiprocessor and DMA applications. Data
transfers can be controlled by assigning P33 as
a Bus Acknowledge input, and P34 as a Bus
Request output.
I
PORT •
(110 OR A ,-A,s!
Pori 0
used for addressing. When Port 0 nibbles are
defined as address bits, they can be set to the
high-impedance state along with Port 1 and the
control signals AS, DS and R/W.
Each bit of Port 2 can be programmed
independently as an input or an output,
and is always available for I/O operations.
In addition, Port 2 can be configured to
provide open-drain outputs.
Like Ports 0 and 1, Port 2 may also be
placed under handshake control. In this configuration, Port 3 lines P3l and P36 are used as
the handshake controls lines DAV2 and RDY2.
The handshake signal assignment for Port 3
lines P3l and P36 is dictated by the direction
Port 3
serial I/O, and parallel I/O with or without
handshake. All ports have active pull-ups and
pull-downs compatible with TTL loads.
Port 3 lines can be configured as I/O or controllines: In either case, the direction of the
eight lines is fixed as four input (P30-P33) and
four output (P34-P37). For serial I/O, lines P30
and P37 are programmed as serial in and serial
out respectively.
Port 3 can also provide the following control
functions: handshake for Ports 0, 1 and 2
(DAVand RDY); four external interrupt request
signals (IRQO-IRQ3); timer input and output
signals ffiN and TOUT) and Data Memory
Select (DM).
3-6
HANDSHAKE CONTROLS
} OAV2 AND RDY2
(P3, AND P3,)
Pori 2
(input or output) assigned to bit 7 of Port 2.
PORT 3
(110 OR CONTROL)
Port 3
Serial
Input/
Output
Port 3 lines P30 and P37 can be programmed
as serial I/O lines for full-duplex serial asynchronous receiver/transmitter operation. The
bit rate is controlled by counter/timer 0, with a
maximum rate of 62.5 kilobits per second.
The Z8 automatically adds a start bit and two
stop bits to transmitted data (Figure 8). The Z8
can also provide odd parity. Eight data bits are
always ttansmitted, regardless of parity selecTransmitted Data - No Parity
tion. If parity is enabled, the eighth bit is the
odd parity bit. An interrupt request (IRQ4) is
generated on all transmitted characters.
Received data must have a start bit, eight
data bits and at least one stop bit. If parity is
on, bit 7 of the received data is replaced by a
parity error flag. Received characters generate
the IRQ3 interrupt request.
Received Data - No Parity
1~1~1~1~1~1~1~1~1~lnl
~STARTBIT
LSTARTBIT
' - - - - - - - - - E I G H T DATA BITS
TWO STOP BITS
' - - - - - - - - E I G H T DATA BITS
L--_ _ _ _ _ _ _ _ _ _ _ ONE STOP BIT
Transmitted Data- With Parity
Received Data - With Parity
I~I~I pl~I~I~I~I~I~I~lnl
1~lpl~I~I~I~I~I~I~lnl
1I,_ _ _
LSTARTBIT
' - - - - - - - - S E V E N DATA BITS
II, _ _ _
LSTARTB,T
' - - - - - - - - S E V E N DATA BITS
ODD PARITY
TWO STOP BITS
PARITY ERROR FLAG
' - - - - - - - - - - - - - O N E STOP BIT
Figure 8. Serial Data Formats
Counter/
Timers
The Z8 contains two 8-bit programmable
counter/timers (To and Tj), each driven by its
own 6-bit programmable prescaler. The T j
pres caler can be driven by internal or external
clock sources; however, the To prescaler is
driven by the internal clock only.
The 6-bit prescalers can divide the input frequency of the clock source by any number
from I to 64. Each prescaler drives its counter,
which decrements the value (l to 256) that has
been loaded into the counter. When the
counter reaches the end of count, a timer
interrupt request-IRQ4 (To) or IRQ5 (Tj)-is
generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be programmed to stop upon reaching zero (single-
3-7
pass mode). or to automatically reload the
initial value and continue counting (modulo-n
continuous mode). The counters, but not the
prescalers, can be read any time without
disturbing their value or count mode.
The clock source for Tj is user-definable
and can be the internal microprocessor clock
(4 MHz maximum) divided by four, or an
external signal input via Port 3. The Timer
Mode register configures the external timer
input as an external clock (I MHz maximum).
a trigger input that can be retriggerable or
non-retriggerable, or as a gate input for the
internal clock. The counter/timers can be programmably cascaded by connecting the To output to the input of Tj. Port 3 line P36 also
serves as a timer output (TOUT) through which
To, Tj or the internal clock can be output.
Inhlrrupts
The Z8 allows six different interrupts from
eight sources: the four Port 3 lines P30-P33,
Serial In, Serial Out, and the two counter!
timers. These interrupts are both maskable and
prioritized. The Interrupt Mask Register
globally or individually enables or disables the
six interrupt requests. When more than one
interrupt is pending, priorities are resolved by
a programmable priority encoder that is controlled by the Interrupt Priority Register.
All Z8 interrupts are vectored. When an
interrupt request is granted, the Z8 enters an
interrupt machine cycle that disables all subse-
quent interrupts, saves the program counter
and status flags, and branches to the program
memory vector location reserved for that interrupt. This memory location and the next byte
contain the l6-bit address of the interrupt
service routine for that particular interrupt
request.
The Z8 also supports polled systems. To
accommodate a polled structure, any or all of
the interrupt inputs can be masked and the
Interrupt Request Register polled to determine
which of the interrupt requests needs service.
Clock
The on-chip oscillator has a high-gain,
series-resonant amplifier for connection
to a crystal or to any suitable external
clock source (XTALI = Input, XTAL2 =
Output).
The crystal source is connected across
XTALI and XTAL2, using the recom-
mended capacitors (C l = 15 pF) from
each pin to ground. The specifications for
the crystal are as follows:
Power Down
Standby
Option
The low-power standby mode allows
power to be removed without losing the
contents of the 124 general-purpose registers. This mode is available to the user as a
bonding option whereby pin 2 (normally
XTAL2) is replaced by the VMM (standby)
power supply input. This necessitates the
use of an external clock generator (input =
XTALl) rather than a crystal source.
+5V
rr
TRICKLE
CHARGE
~l
-...:-
~~
• AT cut, series resonant
• Fundamental type, 8 MHz maximum
• Series resistance, Rs:::; 100 n
The removal of power, whether intended
or due to power failure, must be preceded
by a software routine that stores the
appropriate status into the register file.
Figure 9 shows the recommended circuit
for a battery back-up supply system.
VDO
Z8
XTAL2
(VMAX)
I
Figure 9. Recommended Driver Circuit
for Power Down Operation
3-8
ZS-02
Development
Device
ZS-02
Pin
Description
The 64-pin development version of the
40-pin mask-programmed ZB allows the user to
prototype the system in hardware with an
actual ZB device, and develop the code that is
eventually mask-programmed into the on-chip
ROM of the Z8-01.
The Z8-02 is identical to the Z8-01 with the
following exceptions:
o
o
The internal ROM has been removed
The ROM address lines and data lines are
buffered and brought out to external pins
o
Control lines for the new memory have been
added
The functions of the Z8-02 110 lines, AS, DS,
R/W, XTALl, XTAL2 and RESET are identical
to those of their Z8-01 counterparts. The functions of the remaining 24 pins are as follows:
Ao-All- Program Memory Address (outputs).
P2,
Ao-A 11 access the first 2K bytes of program
memory. All is a reserved pin.
P2,
00-07- Program Data (inputs). Program data
from the first 2K bytes of program memory is
input through pins Do-D7.
P3,
10
P1,
MOS. Program Memory Data Strobe (output,
active Low). MDS is Low during an instruction
fetch cycle when the first 2K bytes of program
memory are being accessed. MDS remains High
during other program memory read cycles.
11
12
13
1.
1S
1.
PO,
PO,
Z8-02
17
P1,
PO,
18
1.
20
21
SYNC. Instruction Sync (output, active Low).
This strobe output is forced Low during the
internal clock period preceding the beginning
of an opcode fetch.
0,
SCLK. System Clock (output). SCLK is the
internal clock output through a buffer. The
clock rate is equal to one- half the crystal
frequency.
A,
22
SYNC
23
0,
2.
MDS
2S
A,
2.
27
IACK_ Interrupt Acknowledge (output, active
The following notation is used to describe the
A,
30
A"
A,
31
32
A.
shown in the instruction summary.
addressing modes and instruction operations as
IRR
Irr
X
DA
Symbols
0,
Figure 10. Z8-02 Pin Assignments
High). lACK is driven High in response to an
interrupt during the interrupt machine cycle.
Addressing
Modes
28
2.
Indirect register pair or indirect working~register
pair address
Indirect working-register pair only
RA
Indexed address
Direct address
Relative address
1M
Immediate
dBt
arc
cc
Destination location or contents
Source location or contents
Condition code (see list)
Indirect address prefix
@
R
Register or working-register address
Working-register address only
Indirect-register or indirect wC?rking-register
IR
Ir
RR
address
Indirect working-register address only
Register pair or working register pair address
Assignment of a value is indicated by the symbol
"_". For example,
Stack pointer (control registers 254-255)
PC
Program counter
FLAGS Flag register (control register 252)
RP
Register pointer (control register 253)
IMR
Interrupt mask register (control register 251)
SP
3-9
'
dst - dst + src
indicates that the source data is added to the
destination data and the result is stored in the
destination location. The notation "addr(n)" is used
to refer to bit "n" of a given location. For example,
dst (7)
refers to bit 7 of the destination operand.
Flags
Control Register R252 contains the following six
flags:
C
Z
Affected flags are indicated by:
o
Carry flag
Zero flag
Sign flag
Overflow flag
DeCimal-adjust flag
Half-carry flag
5
V
D
H
Condition
Codes
*
x
Condition Codes
Mnemonic
Flags Set
Meaning
Value
1000
alII
IIII
OlIO
IlIa
1101
0101
0100
1100
OlIO
IlIa
1001
0001
1010
0010
IIII
alII
lOll
0011
0000
Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined
Always true
Carry
No carry
Zero
C
NC
Z
NZ
PL
Not zero
Plus
MI
Minus
OV
NOV
EO
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE
C
Z
S
S
Overflow
No overflow
V
Equal
Z
Not equal
Greater than or equal
Less than
Z
ope
I
I
a
V
I
a
(S XOR V) = a
(S XOR V) = I
IZ OR (S XOR V»
IZ OR (S XOR V)]
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
'
Unsigned greater than
Unsigned less than or equal
Never true
Instruction
Formats
I
a
I
a
a
C
Z
=a
=I
C ,,0
C = I
(C
= a AND Z = 0)
=I
(C OR Z)
CCF, 01, EI, IRET, NOP,
ReF, RET, SCF
dst
ope
INC r
One-Byte Instructions
ope
MODE
CLR, CPL, CA, DEC,
dst/src
OR
1 1
01 dstlsrc I
~~~~'~~~Rt~~~A,POP,
ope
f---'.,",-",---lOR
/11 1 0
I
MODE
"c
RRC, SRA, SWAP
I
ope
11
d"
JP, CALL (Indirect)
ope
Ace, ADD, AND,
CP, OR,
."
sac, SUB,
TeM, TM, XOR
MODE
ope
dst/src
srcldst
dst,
ADC, AOD, AND, CP,
LD. OR, sec, SUB,
TCM, TM, XOR
Ace, ADD, AND, CP.•
OR
11
1 1
01
dst·
VALUE
MODE
MODE
"c
MODE
d"
SRP
d"
1 1 1 0
1 1 1 0
dst
ope
8tH
OR
OR
LD, LDE, LDEI,
LOC, LOCI
MODE
ope
LD, OR,
sac, SUB,
TeM, TM, XOR
LO
OR
OR
ope
1 1 1 0
1 1 1 0
d"
LO
dst/src
ADDRESS
dst/src
ope
,---------=".::c/",.',,-'_ . J
dst
lope
LO
OR
11
1 1
01
opc
JP
OA,
OA,
LO
VALUE
Idst/CCR~ ope
OPC
OA,
OA,
OJNZ. JR
CALL
Three-Byte Instructions
Two-Byte Instructions
Figure 11. Instruction Formats
3-10
Z80pcode
Map
Lower Nibble (Hox)
A
6,5
DEC
R,
..
><
:;;
:!!
:z:
~
lR,
A
B
C
D
E
F
6,5
ADD
ADD
ADD
ADD ADD
fl.U
H,lrz
H2,RI
10,5
1Hz, HI
Hl,IM
lRl,IM
6,5
6,5
10,5
10,5
10,5
10,5
10,5
10,5
10,5
6,5
6,5
RLC
Il,r2
ll,hz
H2.RI
1H2,HI
HI,IM
6,5
6,5
6,5
6,5
IG,5
10,5
10,5
10,5
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
lRI,IM
lR,
C
D
6,5
12/10,0
6,5
LD
LD
DJNZ
JR
lO
JP
INC
ll,H2
f2,RI
fl,RA
cC,RA
n,lM
ce, DA
6,5
6,5
12/10,5
12/10,0
F
E
" r--
ADC ADC ADC ADC ADC ADC
lRI,IM
H,
lR,
[1,r2
[1,IrZ
HZ,R,
IHz,HI
Hl,lM
8,0
6,1
6,5
6,5
10,5
10,5
10,5
10,5
)P
SRP
SBC
SBC
SBC
SBC
SBC
SBC
IRRl
1M
n,lZ
r1,lrz
Hz, HI
IRz,Rl
HI,IM
IRdM
8,5
8,5
6,5
6,5
10,5
10,5
10,5
10,5
DA
R,
DA
OR
OR
OR
OR
OR
lR,
rl,l2
n,lrz
H2,RI
OR
IRz,RI
HI,lM
rHI,IM
10,5
10,5
6,5
6,5
10,5
10,5
10,5
10,5
POP
R,
POP
lR,
AND
AND
AND
AND
AND
!I,I2
n,Irz
AND
Hz,RI
IHz,HI
Hl,IM
IBI,IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
COM
R,
COM
TCM
TCM
TCM
TCM
TCM
lR,
11,12
11,IrZ
HZ,RI
1H2,HI
R!,IM
TCM
1R1,IM
10/12.1
12/14,1
6,5
6,5
10,5
10,5
10,5
10,5
PUSH
R,
PUSH
TM
TM
TM
TM
TM
TM
lR,
n,12
II,Ir2
H2,H.
IHz,HI
Hl.IM
lRl,IM
10,5
10,5
12,0
18,0
LDE
lOEl
1},lrr2
IIl.1rr2
12,0
18,0
DECW DECW
RR,
lR,
a.
a.
::>
6,5
ADD
RLC
R,
e
6,5 .
DEC
B
6,5
6,5
RL
R,
RL
lOE
lOEI
lR,
IZ,hn
hz,IrI!
r-r-r-r-r-r--
6,1
Dl
6.l
EI
10,5
10,5
6,5
10,5
10,5
10,5
10,5
1"4":""0
INCW
RR,
INCW
CP
CP
RET
n,lrz
CP
lRz,HI
CP
n,ll
CP
H2, HI
CP
lR,
Ri,lM
IR\,IM
6,5
6,5
6,5
6,5
10,5
16:0
CLR
R,
CLR
IR,
XOR
XOR
XOR
XOR
XOR
XOR
IRET
II,I2
II,II2
H2, RI
1R2, HI
RI,IM
IRI,IM
---o:s
6,5
10,5
10,5
10,5
6,5
6,5
12,0
RRC
R,
RRC
lR,
lOC
lOCI
LD
RCF
II,III2
III,Iu2
n, x, R2
6,5
6,5
12,0
SRA
R,
SRA
lR,
12,lIII
II2,IrI!
IRRI
6,5
6,5
6,5
10,5
---o:s
---o:s
RR
R,
RR
IR,
LD
LD
lO
lO
lO
II,In
H2,RI
1R2,RI
HI,IM
IRi,lM
6,7
6,7
6,5
SWAP SWAP
R,
lR,
LDC
18,0
10,5
°
lOCI ~~~L*
°
CALL
18,
20,
10,5
10,5
SCF
LD
DA
12, x, HI
10,5
10,5
CCF
10,5
6,"0
LD
LD
NOP
IIl,I2
R2, IRI
". . _---'y--.. --_. . ../"
. . . _---'y--..----./". . _----..'y--..----_...~-..-'-----.--_/
Bytes Por
Instruction
Lower
Exocution Cycles
Upper Opcodo Nibble-... A
Nibble
Pipeline Cycles
Mnemonic
Legend:
R = 8· Bit Address
r = 4- Bit Address
R I or r 1 = Dst Address
R2 or r2 = Src Address
Sequence:
Opcode, First Operand, Second Operand
Note: The blank areas are reserved
First Operand
Second Operand
• 2-byte instruction; letch cycle appears uS u 3-byte instruction.
3-11
instructions .
Z8™
Instruction
Summary
Instruction
and Operation
Addr Mode
ADC ds!,src
dst-dst + src + C
(No!e I)
ds.
src
Opcode Flags Affected
Byte
(Hex)
CZSVDH
• 0 •
ID
ADD ds!,src
dst - dst + src
(Note I)
00
AND dst,src
ds! - ds! AND src
(Note I)
50
o•
Instructlon
dBt
Bre
LDEldst,src
Ir
Irr
dst - src
r + 1; rr - rr + 1
Irr
Ir
- •• 0
\)~---
CCF
C - NOTC
COM ds!
ds! - NOT dst
R
IR
60
61
CP ds!,src
dst - src
(Note I)
DA ds!
ds! - DA dst
R
IR
40
DEC dst
dst-ds!-I
R
IR
00
DECW dst
ds! - ds! - I
RR
IR
80
81
RRC dst
8F
SBC dst,src
ds! - dst " src - C
o
AD
* * *"X
rA
r=O-F
*
EI
IMR (7) - I
9F
INC ds!
ds! - dst + I
RET
PC - @ SP; SP - SP + 2
AF
RL ds!
90
91
RLC ds!
10
II
RR dst
EO
EI
20
RR
AD
IR
Al
RA
I
(Note !)
SRAdst ~R
"~L':D--" IR
DO
DI
1M
- - - - - -
cB
c=O-F
------
I - - -
31
20
****1*
IR
FO
Fl
x
TCM dst,src
(NOT ds!) AND src
(Note !)
60
- •• 0
TM dst,src
dst AND src
(Note !)
70
XOR dst,src
dst - dst XOR src
(Note !)
BO
(Note !)
"--C':::r"
cD
c=O-F
30
• I
3D
DF
SWAPdst·~ R
IRET
BF
FLAGS - @SP; SP - SP + I
PC - @ SP; SP - SP + 2; IMR (7) - I
DA
o-
CO
CI
SCF
C -I
SUB dst,src
dst - dst - src
21
IRR
.LEl=E:SlJ I~
SRP src
RP - src
rE
r=O-F
R
IR
70
71
CF
01
DJNZ r ,dst
RA
r - r - 1
if r 0 PC - PC + dst
Range: + 127, -128
* * X
* 0 - -
Note I
r
R
1M
R
r
X
r
Ir
R
R
R
IR
IR
X
r
Ir
r
R
IR
1M
1M
R
r
Irr
Irr
LDCI ds!, src
Ir
Irr
dst - src
r - r + 1; rr-rr + 1
LDE ds!,src
dst - src
LDC dst,src
dst - src
R
IR
C - 0
IMR (7) - 0
LD ds!,src
dst - src
50
51
RCF
BO
BI
JR cc,ds!
if cc is true
PC - PC + dst
Range: + 127, -128
R
PUSH src
SP-SP-I; @SP-src
R
IR
JP cc,ds!
if cc is true
PC - ds!
40
IR
CLR ds!
ds! - 0
DI
93
(No!e I)
EF
41
83
FF
ORds!,src
ds! - dst OR src
POP dst
ds! - @SP
SP - SP +
D4
Opeode Flags Affected
Byte
(Hex)
CZSVDH
r -
NOP
CALL ds!
DA
SP-SP"2
IRR
@SP - PC; PC - ds!
INCW ds!
dst - ds! +
Addr Mode
and Operation
r
Irr
rC
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
E6
E7
- - - - - -"
These instructions have an identical set of addressing
modes, which ·are encoded for brevity in this table. The
higher opcode nibble is found in the instruction set table
above. The lower nibble is expressed symbolically by a L;
in the table above, and its value is found in the following
table to the right of the applicable addressing mode pair.
For example, the opcode of an ADC instruction using
the addressing modes r (destination) and Ir (source) is 13.
Addr Mode
dst
F5
C2
D2
------
Irr
Ir
C3
------
Irr
82
92
sre
Ir
D3
------
3-12
Lower
Opeode Nibble
rn
rn
rn
R
R
R
IR
~
R
1M
ffil
IR
1M
[1]
R240 510
Serial I/O Register,
(FOH ; Read/Write)
R244 TO
CouDter/Tlmer 0 Register
(F4H; Read/Write)
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
L----SERIALDATAIDo '" LSS)
To INITIAL VALUE (WHEN WRITTEN)
L----(RANGE: 1 256 DECIMAL 01 DO HEX)
To CURRENT VALUE (WHEN READ)
R241 TMR
Timer Mode Register
(FI H ; Read/Write)
R245 PREO
Proscaler 0 Register
(F5H; Write Only)
I~I~I~I~I~I~I~I~I
l~t~l~t~t~t~t~t~1
TO"' M
ODES'j
RESERVED
= 00
: ~~11
INTERNAL CLOCK OUT
~~ g~i
lS~o.
.
==
T
MODES
INP'Or = 00
GATE INPUT = 01
INON'R~~~~g~~~~:~~1 = 10
=
..
= DISABLE To COUNT
1 = ENABLE To COUNT
COUNTMODE
.'
'0 :' To SINGlE·PASS
1
1 = LOAD T 1
0 = DISABLE T1 COUNT
1 = ENABLE T 1 COUNT
.
= To MODUlO·N
RESERVED
0 ::; NO FUNCTION
EXTERNAL CLOCK
TRIGGER INPUT
(RETRIGGERABlE)
~[
FUNCTION
1 = NO
LOAD
To
0
.
.
.
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
11
R242 TI
CouDter Timor I Reglotor
(F2H; J1.ead/Write)
R246 P2M
Port 2 Mode Rogistor
(F6 H; Write Only)
10,10,10,10.10,10,10, I0.1
I~I~I~I~I~I~I~I~I
T, INITIAL VALUE (WHEN WRITIEN)
L----(RANGE 1-256 DECIMAL 01-00 HEX)
I, CURRENT VALUE (WHEN READ)
R243 PREI
Prescaler I Register
(F3H; Write Only)
R247 P3M
Port 3 Mode Register
(F7H; Write Only)
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
~L
B~~
COUNTMODE
o '"
1
T 1 SINGLE·PASS
= 1,
MODULQ·N
CLOCK SOURCE
o=
T, EXTERNAL TIMING INPUT
(TIN) MODe
1 = T,INTERNAL
DO
OPORT2PULL'UPSOPEN DRAIN
1 PORT 2 PUll·UPS ACTIVE
RESERVED
o P32 = INPUT
P3S = OUTPUT
1 P32 :: DAVOJRDYo P3S = RDYOI~
P33:: INPUT
~ ~ 1P33
PRESCAlER MODULO
(RANGE: 1-64 DECIMAL
::: INPUT
P34 = OUTPUT
P34
= [j'g
1 1 P33:: DAV1/RDY1 P34 = RDY1/DAYl
01-00 HEXI
o P31 = INPUT ITIN) P36 '" OUTPUT (TOUT)
1 P31 = DAV2IRDY2 P36 = RDY2IDAV2
'--------~~~ ~ ~~~~ZlIN ~~~ ~ ~~~I~~TOUT
'-________
ZB Control Registers
3-13
~ ~:=:~~ g~F
R248 POIM
Port 0 and 1 Mode Register
R252 FLAGS
Flag Register
(F8H ; Write Only)
(FCH; Read/Write)
I~I~I~I~I~I~I~I~I
-r- ~~
.-J
L
PD.-PO, =M
ODE:]
00
OUTPUT
INPUT = 01
A'2-A'5 = 1X
EXTERNAL MEMORY TIMING
NORMAL = 0
~~~
I
PD.-PO,
MODE
00 = OUTPUT
LUSER FLAG Fl
LUSER FLAG F2
01 '" INPUT
1X '" A,-A11
STACK SELECTION
0 = EXTERNAL
.
1 = INTERNAL
EXTENDED::: 1
HALF CARRY FLAG
DECIMAL ADJUST FLAG
OVERFLOW FLAG
SIGN FLAG
P10·Pl 1 MODE
=
00
BYTE OUTPUT
01 ;: BYTE INPUT
10 = ADo-AD,
ZERO FLAG
_
_
CARRY FLAG
_
11 = HIGH IMPEDANCE ADo-AD7. AS, OS, R/W,
As-A1l. A12-A15 IF SELECTED
R253 RP
Register Pointer
R2491PR
Interrupt Priority Register
(F9H; Write Only)
(FDH ; Read/Write)
I~I~I~I~I~I~I~I~I
1~I~t~I~I~I~I~I~1
II
"_om:]
IRD3, IROS PRIORITY (GROUP A)
o = IRoS > IRD3
1 = IRD3 > IROS
11
1"-"-'.-
IRDO, IRQ2 PRIORITY (GROUP B)
o = IRQ2 > IROO
1 = IRao > IRQ2
RESERVED = 000
, C > A > B = 001
A > B > C = 010
A> C > B '" 011
B>C>A=l00
C > D > A = 101
B > A > C = 110
REGISTER POINTER
WjdJ
f1
f6
[llil
L OON ' T CARE
LDON'T CARE
DON'T CARE
_
DON'T CARE
f5
'.
RESERVED:::: 111
IRQt, IRQ4 PRIORITY (GROUP C)
IRQt > IRQ4
1 = IRQ4 > IRQt
o ::
R250 IRQ
Interrupt Request Register
R254 SPH
Stack Pointer
(FAH ; Read/Write)
(FEH ; Read/Write)
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
RESERVED
c=
T
IROO
IR01
IRQ2
IR03
IRO"
IROS
=
=
=
=
::
=
P321NPUT
P33 INPUT
P31 INPUT
P30 INPUT, SERIAL INPUT
To. SERIAL OUTPUT
T1
R251lMR
Interrupt Mask Register
R255 SPL
Stack Pointer
(FB H ; Read/Write)
(FF H ; Read/Write)
1~1~1~1~1~1~I~t~1
I~I~I~I~I~I~I~I~I
II
c=
I'-___ ~~~~~~~~~~~R
1 ENABLES IROO-IROS
100 = IRCO)
' -_ _ _ _ _ _ RESERVED
' -_ _ _ _ _ _ _ 1 ENABLES INTERRUPTS
Z8 Control Registers
3-14
LOWER
Absolute
Maximum
Ratings
Stresses greater than those listed under Absolute Maxi-
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature .................. 0°Cto +70°C
mum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
Storage Temperature ........ -65°C to +150°C
Standard
Test
Conditions
DC
Characteristics
device reliability.
The characteristics below apply for the
following standard test conditions, unless
otherwis.e noted. All voltages are referenced to
GND. Positive current flows into the reference
pin. Standard conditions are as follows:
Symbol
Parameter
o
+4.75 V ~ Vee ~ +5.25 V
o
GND = 0 V
o
O°C ~ TA ~ +70°C
Min
Max
Unit
Condition
VeH
Clock Input High Voltage
3.8
Vee
V
Driven by External Clock Generator
VCL
Clock Input Low Voltage
-0.3
0.8
V
Driven by External Clock Generator
VIH
Input High Voltage
2.0
Vee
V
VIL
Input Low Voltage
-0.3
0.8
V
VRH
Reset Input High Voltage
3.8
Vce
V
VRL
Reset Input Low Voltage
-0.3
0.8
V
VOH
Output High Voltage
VOL
Output Low Voltage
IlL
Input Leakage
±IO
IOL
Output Leakage
±IO
IIR
Reset Input Current
Iec
IOH
= -250 IlA
V
IOL
=
IlA
OV::; VIN ::; +5.25V
~
OV::; VIN ::; +5.25V
-50
Il A
Vee
=
Vee Supply Current
180
rnA
Vee
= 5.25V
IMM
VMM Supply Current
10
rnA
Power Down Mode
V MM
Backup Supply Voltage
Vce
V
Power Down Mode
1. For
2.4
0.4
3.0
AO-All. MDS. SYNe. SeLK and lACK on the
Test Load
Circuits
V
28·02 version.
IOH
~
-100"
+2.0 rnA
+5.25 V, VRL
A and IOL
~
1.0 mAo
Vee
18K
2.1K
Toni Load 2
Test Load 1
Vee
Vee
CLOCK IN
L.._ _ _....._
I
XTAL 1
CL :: 15 pF MAX.
External Clock Interface Circuit
3-15
=0V
Notes
Ii
Z8™
I
External 1/0
or Memory
Rec:idand
Write Cycle
Parameter
Min,
Unit
Condition
TdA(AS)
Address Valid to ,Address Strobe Delay
SO
ns
Test Load]
TdAS(A)
Address Strobe to Address Float Delay
60
ns
Test Load]
TdAS(DI)
Address Strobe to D~ta In Valid Delay
ns
Test Load]
TwAS
Address Strobe Width
80
ns
Test Load I
TdA(DS)
0
ns
Test Load]
TwDS
Address Float to Data Strobe Delay
(Read)
Data Strobe Width (Write)
ns
Test Load·]
2
TdDS(DI)
Data Strobe to Data In Valid Delay
ns
Test Load]
3
ThDS(DI)
Data In Hold Time
TdDS(A)
Data Strobe to Address Change Delay
Symbol
Max
320
250
160
200,
0
ns
80
ns
Test Load I
TdDS(AS)
Data Strobe to Address Strob!, De]ay
70
ns
Test Load]
TdR(AS)
Read Valid to Address Strobe Delay
SO
ns
Test Load]
TdDS(R)
Data Strobe to Read Change Delay
60
ns
Test Load]
TdDO(DS)
Data Out Valid to Data Strobe Delay
SO
ns
Test Load]
TdDS(DO)
ns
Test Load]
Data Strobe to Data Out Change Delay
80
TdW(AS)
Write, Valid to Address Strobe Delay
SO
ns
Test Load]
TdDS(W)
Data Strobe to Write Change Delay
60
ns
Test Load I
1. Delay times are specified for an input clock frequency of
8 MHz. When operating at a lower frequency, the inera'ase in
input clock period must be added to the specified delay time.
2. Data Strobe Width Is specified for an input clock frequency of
8 MHz. When operating at a lower frequency, the increase in
three input clock periods must be added to the specified width.
pata Strobe Width varies according to the instruction being
executed.
PORT 0,
Notes
3
.]
3. Address Strobe and Data Strobe to Data In Valid delay times
represent memory system access times and are given for an
S MHz crystal Input frequency. For lower frequencies; the
change ~ four clock periods must be added to TdAS(DI) and
the change in three clock periods added to TdDS(DI).
4. All timing references assume 2.0 V for ,a logic "1" and 0.8 V
for a logic "0."
/\a-An OR /\a-A,.
6M
PORT 1
Ilo-D,IN
ThDS(DI)
----"T--'~::3.J~-TwDS--~C-----
::>(t_______________________________
TdR(AS)
TdW(AS)
~w
TdDs(R)t
TdDS(W) _
3-16
Z8™
Additional
Timing
Symbol
Parameter
Min
Max
Unit
Condition
125
1000
ns
25
ns
From External Clock
Generator
ns
From External Clock
Generator
Notes
TpC
Input Clock Period
TrC, TfC
Input Clock Rise and
Fall Times
TwC
Input Clock Width
TdSC(AS)
System Clock Out to Address
Strobe Delay Time
TdSY(DS)
Instruction Sync Out to Data
Strobe Delay Time
200
ns
1,2
TwSY
Instruction Sync Out Width
160
ns
1,2
TwI
Width 01 Interrupt Request via
Port 3 Input
100
ns
37
ns
1. Test Conditions use Test Load 1 for SCLK when o~
through Pori 3 and Tesl Load 2 on the SCLK and SYNC
direct outputs on the 28-02.
lower frequencies, the change in two clock periods must be
added.
3. All timing references assume 2.0 V for a logic "1" and 0.8 V
2. Times given assume an 8 MHz crystal input frequency. For
for a logic "0."
CLOCI{
SCLI{
~
AS~1-1---
''--_-Jf
Ji--_....If
\ ___
\,....,_ _ _.....IIYTdSC(AS)
3 -----""
READ CYCLE
r-TdSY(DS)
~---TWSY---f
3-.17
' ; - WRITE CYCLE
r
§
Z8™
Handshake
Timing
Symbol
Parameter
TsDI(DA)
Data In Setup Time
ThDA(DI)
Min
Max
Condition
Unit
0
ns
Data In Hold Time
230
ns
TwDA
Data Available Width
175
ns
Input Handshake
Test Load 1
ns
Data Available Lbw to Ready
Delay Time
Input Handshake
Test Load 1
TdDAL(RY)
ns
Output Handshake
Test Load 1
ns
Input Handshake
Test Load 1
0
ns
Output Handshake
Test Load 1
50
ns
Test Load 1
ns
Test Load 1
20
175
0
150
Data Available High to Ready
Delay Time
TdDAH(RY)
TdDO(DA)
Data Out to Data Available
Delay Time
TdRY(DA)
Ready to Data Available Delay
Time
0
205
DATA IN
TsDI(DA)
DAY
(INPUT)
RDY
(OUTPUT)
PORT
READ
Input Handshake
DATA OUT
DATA OUT VALID
---...;.-tTdDO(DA)
DAY
(OUTPUT)
TdDAL(RY)
\
RDY
(INPUT)
Output
Z8.02,·03
Memory Port
Timing
Symbol
Parameter
TdA(Dl)
Address Valid to Data In
Valid Delay Time
ThDI(A)
Data In Hold Time
1.
\
Handshake\"_~
Min
Max
Unit
Condition
460
ns
Test Load 2
o
ns
Delay times are specified for an input clock frequency of
8 MHz.
2. All timing references assume 2.0 V for a logic "}" and 0.8 V
for a logic "0."
.
· .....
00-07
~~:::::::::::::_T_dA_(_DI_)::===A_D__D_R~E~S_S~V___AL_I~D----------------------~-D-J(-A)----------------DON'TeARE
DATA IN VALID
3-18
DON'T CARE
Ordering
Information
Temperature
Range
Part Number
Z8-01 PS
O°C
O°C
O°C
O°C
Z8-01 CS
Z8-02 QS
Z8-03 RS
to
to
to
to
Number
of Pins
Package
Description
40
40
64
40
Plastic
Ceramic
CeramiC
Ceramic
8-Bit Single-Chip Microcomputer Circuit
8-Bit Single-Chip Microcomputer Circuit
8-Bit Microcomputer Development Device
B-Bit Microcomputer Protopack Emulator
+70°C
+70°C
+70°C
+70°C
Package
Information
4(}-Pin Ceramic Package Dimensions (CS Package)
L -_ _
1-
~
12.04O!
_---------I
-I
4(}-Pin Plastic Package Dimensions (PS Package)
Notice: Z8 and Z·bu$ are trademarks of Zilog, Inc.
3-19
ZS™-O3
Microcomputer
Protopack™-Emulator
PRODUCT
SPECIFICATION
SYNERTEIt
A SUBSIDIARY OF HONEYWELL
PRELIMINARY
• Vectored priority interrupt system.
41 Up to 62K of external d.ata memory.
• Up to 62K of external program memory.
41 On-chip crystal, RC, or LC oscillator.
• High-speed instruction execution.
Working-register operations = 1.5j.ls
Average instruction = 2.2j.ls
o Single +5V supply voltage.
III All inputs/outputs TTL compatible.
• Prototyping version of Synertek Z8.
• Piggyback 2716 EPROM program memory.
• Pin-compatible with Z8-01 masked-ROM for
hardware debugging or low-volume production.
• Complete microcomputer on-chip
128 bytes of on-chip data RAM
32 I/O lines
Socket for 2716 2Kx8 EPROM
• Two 14-bit counter/timers.
• Duplex UART and baud-rate generator.
into the 24-pin "piggy-back" socket atop the Z8-03
allows pin-compatible emulation of the Z8-01 maskedROM version.
The Synertek Z8-03 Microcomputer Protopack Emulator is a ROM-less version of the Synertek Z8 single-chip
microcomputer. A removable 2716 EPROM plugged
BLOCK DIAGRAM
OUTPUT INPUT
110
(BIT PROGRAMMABLE)
XTAL AS
PACKAGE DRAWING
os R/W RESET
ADDRESS DR 110
ADDRESS/DATA OR 110
(NIBBLE PROGRAMMABLE) (BYTE PROGRAMMABLE)
Z8 and Protopack are trademarks of Zilo9i Inc.
3-20
Ordering
Information
Number
of Pins
Temperature
Range
Part Number
Package
Description
------------------~-----------------------------------------
ZB-03 RS
ooe to +70 oe
40
B-Bit Microcomputer Proto pack Emulator
Ceramic
Package
Information
40
21
IT~DDDDDDDDDDDD
DD
=~D
L1~oooooooooooo
o
M
PIN 1
\DENTI FICATION
1
- F
9.SYNERTEK
za·03
~
20
2.020 MAX
0.050::!: ,020
1.220 MAX
I
D.r.-
~:g~~J~~~4
r-o.5~~~a'--j
MAX
I
I D.050±.015 BOTH ENDS
r--O.10D::!: ,OlD TYP
II
0.018
-ir--::!:.003
TYP
f-----------~i~
3-21
---,-
.
0.040 + .001 TYP
-.002
0.125
MIN
3-22
SY1 791 -02/SY1 793-02
Floppy Disk
Controller (FDC)
MICROPROCESSOR
PRODUCTS
SYNERTEK
ASUBSIOIARV OF HONEYWELL
•
0
•
•
Pin and function compatible with Western-Digital
FD1791-02 and FD1793-02
Single 5-volt power supply
Accommodates both Single Density (FM) and Double
Density (MFM) formats
The SY1791-02/SY1793-02 Floppy Disk Controller is a
fully programmable device intended for microprocessor
based systems. Autonomous operation permits complete
control of floppy disk functions with minimum CPU intervention required. Programmability is provided to allow
•
IBM format compatibility:
IBM 3740 Single-Density
IBM System-34 Double-Density
Numerous automatic control functions
either single-density (FM) or double-density (MFM)
formats compatible with IBM stan.dards. or formats
uniquely defined by the user. The SY1791-02 uses
negative-true data bus logic; the SY1793-02 uses
positive-true.
WG
TG43
WPRT
OATA
BUS
BUFFERS
DBo-Dil7
(DBo-DB71
wF!iil'5E
fi'
DISK
INTERFACE
LOGIC
AND
CONTROL
iiiiii
cs
fIE
TROD
READY
STEP
DlRC
EARLY
LATE
RG
HLD
HLT
RCLK
RAW READ
WD
i5llEN
WE
ffif
PROCESSOR
INTERFACE
CONTROL
Ao
PIN ASSIGNMENTS
NC**
WE
cs
ORa
fIE
OBI
Di5EiiI
WPRf
iP
TRlili
Wi'/iTi'OE
DB2
READY
DB3
WD
Ao
A,
DBO
A,
INTRa
ORa
CLK
( I DENOTES SY1793·02 SIGNALS
.Figure 1. SY1791-02/SY1793-02 Block Diagram
ORDERING INFORMATION
DB4
WG
DB5
TG43
DBS
HLD
DB7
RAW READ
STEP
RCLK
DIRC
RG
EARLY
PART
NUMBER
SYC1791-02
SYD1791-02
SYP1791-02
SYC1793-02
SYD1793-02
SYP1793-02
PACKAGE
LATE
DATA BUS LOGIC
iiiiii
CERAMIC
CERDIP
PLASTIC
CERAMIC
CERDIP
PLASTIC
NEGATIVE-TRUE
NEGATIVE-TRUE
NEGATIVE-TRUE
POSITIVE·TRUE
POSITIVE-TRUE
POSITIVE-TRUE
NC"
INTRa
GND
CLK
HLT
TEST
vee (+5vl
*1793·02 HAS POSITIVE·TRUE DATA BUS LOGIC.
**NC PINS ARE INTERNALLY OPEN CIRCUITED.
VOLTAGES APPLIED TO THESE PINS HAVE NO
AFFECT.
3-23
Syt 79t-02jSyt 793-02
DETAILED LIST OF FEATURES
• Replaces Western-Digital FD1791-02 and
FD1793-02
• Single 5-volt power supply
• 40-pin DIP package
.
.•. Automatic track seek with verification
• Accommodates single-density (FM) and
double-density (MFM) formats
• . Soft-sector format compatibility
• IBM 3740 (single-density) and System 34
(double-density) compatible
• Single or multiple record read with automatic
sector search or entire track read
• Selectable record length (128, 256, 512, 1024
bytes)
1.0 GENERAL DESCRIPTION
• Single or multiple record write with automatic
sector sea rch
• Entire track write for initialization
• Programmable Controls
Selectable track-to-track stepping time
Selectable head settling and engage times
Head position verification
Side verification .
• Double-buffered read and write data flow
• DMA or programmed data transfers
• TIL-compatible inputs and outputs
• Write precompensation (FM and MFM)
• Comprehensive Status Register
•
DATA SHIFT REGISTER (DSR) - As part of the Disk
Interface Logic and Control, this 8-bit register assembles
serial data from RAW READ input during READ operations, prior to transfer to the DR. During WRITE operations it accepts parallel data from the DR and serially
transfers it to the Write Data output.
•
CRC LOGIC - This logic, part of Disk Interface Logic and
Control, does the checking or the generating of the 16bit Cyclic Redundancy Check (CRC). The polynominal is:
G(X) = X I6 + XI2 + X5 + 1. The CRC logic checks all
information, starting with the address mark, uptothe
CRC characters. The CRG register is preset to ones
before data is shifted through the circuit.
1.1 Functional Blocks in the SY1791-02/SY 1793-02
The SY1791-02/SY1793-02 Floppy Disk Controller (FDC)
consists of several functional sections, as shown in
Figure 1. Detailed operation of each section is described
below.
•
DATA REGISTER (DR) - This 8-bit read/write register is
used as a holding register during Disk Read and Write
operations. During Disk Read operations, serial data is
assembled in the Data Shift Register then transferred in
parallel to the DR, where it is made available to the data
bus. In a Disk Write operation, parallel data is transferred
from the data bus to the DR to await transfer to the Data
Shift Register. The DR is also used, while executing a
Seek command, to hold the Track address.
• TRACK REGISTER (TR) - This 8-bit read/write register
holds the track number of the current Read/Write head
position. It can be incremented (decremented) by one
each time the head is stepped in (out), toward track 76
(00). The TR's contents are compared with the track
number (recorded in the disk's ID field) during Read,
Write, or Verify operations. This register should not be
loaded when the device is busy.
•
•
•
SECTOR REGISTER (SR) - This 8-bit read/write register holds the address of the desired sector position. The
contents of the register are compared with the recorded
sector number in the 10 field during disk Read or Write
operations. This register should not be loaded when the
device is busy.
COMMAND REGISTER (CR)- This8-bit write only register holds the command which is being executed. This
register should not be loaded when the device is busy
unless the execution of the current command is to be
overridden. This is accomplished with the Interrupt
command.
• ARITHMETIC/LOGIC UNIT (ALU) - A part of Disk Interface Logic and Control, the ALU does serial comparisons, increments, and decrements. It is used for register
modification and comparisons with the 10 field recorded
on the disk.
• TIMING AND CONTROL - All Processor and Floppy
Disk interface controls are generated through this logic.
The internal device timing is generated from an external
clock.
• AM DETECTOR - The Address Mark Detector, part of
Disk Interface Logic and Control, detects 10, Data and
Index Address Marks during read and write
operations.
1.2 MPU Interface Pin Functions
• MASTER RESET (MR) - A low on this input resets the
device and loads hex 03 into the command register. The
Not Ready status bit (status bit 7) is reset during MR low.
When MR is driven high, a Restore command is executed regardless of the state ofthe Readysignal, and hex
01 is loaded into the Sector Register.
STATUS REGISTER (STR) - This 8-bit read only register
holds device status information. The meaning of the STR
bits is a function of the contents of the Command
Register.
3-24
•
CHIP SELECT(CS) - A low level on this input selects the
FDC and enables processor communications with the
FDC.
•
DATA 8US LINES (080-087 on SY1791-02 and DBODB7 on SY1793-02)- Bi-directional data bus used for
transfer of data between· the system MPU and the FDC
(negative-true for the SY1791-02, positive-true for the
SY1793-02).
.
Syt 19t-02jSYt 193-02
o
REGISTER ADDRESS LINES (AO-A 1) - These inputs
address the internal registers for access by the Data Bus
lines under RE an<;t WE control.
o EARLY - A high EARLY output indicates to external
circuitry that the WD pulse should be shifted early
for write precompensation.
REGISTER ADDRESS CODES
Al
AO
READ
0
0
1
STATUS
I
I
o
TRACK GREATER THAN 43 (TG43) - This output
informs the drive that the Read/Write head is positioned
between tracks 44-255 inclusive. This output is valid
during Read and Write commands.
o
WRITE GATE (WG) - The WGoutput is set high when
writing to the disk if all the Write prerequisites have been
met. WG is used to enable the drive's write circuitry.
o
READY - This input indicates disk readiness to perform
any Read or Write command. READY must he high for a
Read or Write com ma nd to be accepted. If READY is low
and the FDC receives any such command, the command
is not executed and an interrupt is generated if the
Not-Ready status bit is set.
o
WRITE FAULT (WF)/vFO ENABLE (VFOE) - This pin is
used as both an input and output. During Write operations afterWG i.s high, this pin acts as an inputto sense a
negative transition indicating a Write Fault. If a Write
Fault is detected, the Write command is terminated, the
Write Fault status bit is set, and INTRQ goes high.
WRITE
0
1
0
SECTOR
1
1
DATA
TRACK
READ ENABLE (RE) - If CS is low, a low on this input
enables the addressed internal register to output data
onto the data bus.
o
WRITE ENABLE (WE) -If CS is low, then a low on this
input gates data from the data bus into the addressed
register.
o
INTERRUPT REQUEST(INTRQ)- Thisopen drain output
is set high at the' completion'or termination of any operation and is reset when a new command is loaded into the
Command Register or when the Status Register is read.
Use 1OKO pull-up resistor to Vee.
o
LATE.- A high LATE output indicates to external
circuitry that the WD pulse should be shifted late
for write precompensation.
COMMAND
o
o
o
DATA REQUEST(DRQ) - DRQ is an open drain output.
DRQ high during read operations indicates that the Data
Register (DR) contains data. When high during write
operations, DRQ indicates that the DR is empty and
ready to be loaded. DRQ is reset by reading or loading the
DR during read or write operations, respectively. Use
10K pull-up resistor to Vee.
During Read operations, WE/VFOE is an output used to
synchronously control external RCLK circuitry. VFOE
will go true (low) when the following are all true:
1. HLD and HLT are true;
2. settling time, if programmed, has expired;
3. the SY1791-02/SY1793-02 is inspecting
data from the disk.
CLOCK (ClK) - This input requires a square wave clock
for internal timing reference (2 MHz for 8-inch drives,
1 MHz for 5-inch drives).
1.3 Floppy Disk Interface Pin Functions
o READ GATE (RG) - A high on this output indicates that
a field of zeroes (zeroes or ones) has been detected in FM
(MFM) encoded information. This can be used to indicate
to a data separator thai a sync field has been found.
o
TRACK 00 (TROO) - This input, when low, indicates
to the FDC that the Read/Write head is positioned
over track 0.
o
This output to the disk drive
electronics supplies one pulse per required flux
transition.
INDEX PULSE (IP)- This input is generated by the drive
electronics to indicate the start of a track.
o
READ CLOCK (RCLK) - The RCLK input is a nominal
square-wave clock signal derived from the data
stream. Phasing (RCLK relative to RAW READ) is
important, but polarity (RCLK high or low) is not.
WRITE PROTECT (WPRT) - This input is sampled
whenever a Write command is received. A low terminates the command and sets the Write Protect status bit.
o
DOUBLE DENSITY (DDEN) - This input selects either
single or double density operation. When DDEN is low,
double density is selected. When DDEN is high, single
density is selected.
o
TEST (TEST) - This input is used for testing purposes
and should be tied to +5V, or left open, by the user unless
interfacing to voice coil motors. When low, the motor
stepping rate is increased (see Figure 3b).
o WRITE DATA (WD) -
o
•
RAW READ (RAW READ) -'- This is the data input to the
FDC from the drive. This input must be a negative pulse
for each recorded flux transition.
o
HEAD LOAD (HLD) - The HLD output notifies the drive
to engage the Read/Write head against the medium.
•
HEAD LOAD TIMING (HLT) - The HLT input, which is
generated by external logic, indicates that a sufficient
time has elapsed for the head to have engaged.
•
STEP- The step output provides a pulse to the disk drive
electronics to cause each incremental head movement.
•
DIRECTION (DIRC) - The DIRC output defines the
direction of the step. It is high for stepping the head in
towards track 76, and low for stepping the head out
towards track O.
2.0 FUNCTIONAL OPERATION
2.1 Single/ Double Density Selection
The SY1791-02/SY1793-02 has two selectable data
densities, determined by input DDEN.
2.2 Clock Selection
In addition to DDEN, the CLK input determines overall
circuit timings, and must be properly selected. A 1 MHz
ClK input is normally used for 5" mini-diskette drives
and 2MHz for standard 8" drives.
3-25
SY1 791 -02/SY1 793-02
2.3 ORO Operation
2.7 Write Precompensation
The ORO output indicates that a data transfer operation is
required. For disk read operations, ORO signifies that the
Data Register needs to be read sothatthe next data byte can
be received. For disk write operations, ORO signifies that a
data byte has been transmitted and another must be
entered. ORO maybe used as a "handshake" control signal
in a OMA based system.
EARLY and LATE are two additional signals which are
generated by the SY1791-02/SY1793-02 during write
operations. They are used for write precompensation functions. Both signals are active-high. The EARLY signal is
active when the WD pulse is to be written early; the LATE
signal is active when WD is to be written late. If neither
signal is active, then WO is to be written at its normal time.
EARLY and LATE are valid for both single and double
density modes.
2.4 DMA Sequences
In disk read operations, ORO goes high when a serial data
byte is assembled in the Oata Register. ORO is reset when
the byte is read by the OMA controller (or system processor).
If a newly assembled byte is transferred into the OR (from
the DSR) before the'DR has been read, then the overwritten
byte in the OR is lost. Furthermore, the Lost Data status bit
in the Status Register is set, to indicate this condition. Read
operations continue until the end of sector is encountered.
Disk write operations are similar. ORO is activated when
the data byte is transferred from the Oata Register to the
Data Shift Register, indicating that the OR is ready to be
loaded with another byte. It is cleared when the new
byte is loaded by the DMA controller (or system processor). However, if the new byte is not loaded by the
time the prior byte is shifted out, then a byte of all zeroes
is written on the diskette and the Lost Oata status bit in
the Status Register is set.
3.0 COMMAND WORDS
The FOC accepts eleven commands. Command words
should be loaded in the Command Register only when the
Busy status bit (status bit 0) is low. The sole exception is the
Force Interrupt command. Whenever a command is being
executed, the Busy status bit is set. When a command is
completed, an interrupt is generated and the Busy status bit
is reset. The Status Register indicates whether the
completed command encountered an error or was fault
free. For ease of discussion, commands are divided into
"four types. Commands and types are summarized in
Figure 2.
BIT
TYPE
COMMAND
7
RESTORE
SEEK
2.5 Disk Read Operations
I
For disk read operations, the FDC requires RAW READ and
RCLK inputs. RAW READ is a low going pulse for each flux
transition. The FOC detects the rising and falling edges of
RCLK and uses these edges to frame RAW REAO datal
clock inputs. RCLK is provided by some drives, but if not it
must be provided externally (phase-lock-loops, one-shots,
counters, etc.) To assist in generating RCLK, the FDC has a
RG (Read Gate) output, which may be used to acquire
synchronization. Whenever two bytes of zeroes are
detected in read operations (in single-density mode), RG
is activated (high) and the FOC must find a valid AM
(Address Mark) within the next 10 bytes. If the AM is not
found, RG is deactivated (low) and the search for two
bytes of zeroes is re-started. If the AM is found, RG
remains active as long as the FOC is deriving data from
the diskette. For double-density mode, RG is activated
when 4 bytes of hex 00 or hex FF are detected and the
FDC must find the AM within 16 bytes.
STEP
STEP IN
STEP OUT
II
READ SECTOR
WRITE SECTOR
READ ADDRESS
III
READ TRACK
WRITE TRACK
IV
FORCE
INTERRUPT
1 = HIGH LEVEL
0
0
0
0
0
6
0
0
0
1
1
5
0
0
1
0
1
1
1
0
a
1
1
4
0
1
3
2
1
0
h
V
'1
'0
h
V
u
h
V
'1
'0
u
h
V
u
h
V
"'1
'0
0
1
m
m
S
E
C
0
S
E
C
·0
a
a
a
a
a
E
0
E
a
0
0
1
0
E
0
a
1
13
12
I,
10
1
1
1
1
1
1
1
1
0
"
'0
'0
a = LOW LEVEL
Figure 2. Command Summary
3.1 Type I Commands
The Type I Gommands are Restore, Seek, Step, Step-In,
and Step-Out.
•
2.6 Disk Write Operations
The fundamental signals in write operations are: WO (Write
Oata) output, WG (Write Gate) output, WPRT (Write Protect)
input, and WF (Write Fault) input. When writing to the
diskette, WG goes high enabling the disk drive write electronics. However, WG will not be activated until the first
data byte has been loaded in the Data Register. This
ensures that false writing will not occur. Writing is inhibited
when WPRT is low. This sets the Write Protect status bit
and an interrupt (INTRa) is generated.
The WF input signifies a fault condition at the disk drive.
When low, it causes the current command to terminate,
sets the Write Fault bit in the Status Register, and generates the INTRa interrupt.
3-26
RESTORE - The RESTORE command is used to position
the Read/Write head to track 0 of the diskette. Upon the
receipt of this command, the TROO input is sampled. If
TROOis low, indicating the Read/Write head is positioned over track 0, the rrack Register is loaded with
zeroes and an interrupt is generated. 1fT ROO is not low,
step pulses at a rate specified by the r,ro field are issued
until the TROO input is asserted. Atthistime, the TR is
loaded with zeroes and an interruptisgenerated.lfthe
TROO input does not go low after 255 stepping pulses,
the FOC terminates operation, interrupts and sets the
Seek Error status bit. A verification operation takes place
if the V bi! is set. The h bit allows the head to be loaded at
the start of the command. Note that the Rest.ore
command is executed when MR goes from low (true)
to high (false).
SY1791-02/SYt 793-02
o SEEK - This command assumes that the Track Register
contains the track number of the current position of the
Read/Write head and the Data Register contains the
desired track number. The FDG will update the Track
Register and issue stepping pulses until the contents of
the Track Register are equal to the contents of the Data
Register(the desired track location). A verification operation' takes place ifthe V bit is on. The h bit allows the head
to be loaded at the start of the command. An interrupt is
generated at the completion of the command.
o
o
o
BIT
7
6 5
4
3
2
1
0
0
0
0
0
h
V
RESTORE
0
0
0
1 h
V
"
'0
SEEK
0
0
1 u
h
V
"
'0
'0
STEP
0
1
0 u
h
V
"
STEp·IN
1
1 U h
V
"
'0
0
"
'0
STEP·OUT
COMMAND
U
STEP - Upon receipt of this command, the FDG issues
one stepping pulse to the disk drive. The stepping motor
direction is the same as in the previous step command.
After a delay determined by the r1rO field, a verification
takes place if the V bit is on. If the u bit is on, the TR is
updated. The h bit allows the head to be loaded at the
start of the command. An interrupt is generated at the
completion of the command.
STEPPING MOTOR RATE
(See Table of Figu,e 3b) ,
VERIFY {O = No Ye'ifi cation
1 =Verofyat destination track
-
~ HEAD lOAD{O = HlD Reset
1 =HlDSet
STEP-IN - Upon receipt of this command, the FDG sets
DIRG high and issues one stepping pulse. If the u bit is
on, the Track Register is incremented. After a delay
determined by the r1rO field, a verification takes place if
the V bit is on. The h bit allows the head to be loaded at
the start of the command. An interrupt is generated at
the comilletion of the command.
o = No update of T,ac.k Registe,
- UPDATE {
1 = Update T,ack ReglSte,
each step pu Ise
Figure 3a. Type I Command Option Bit
STEP-OUT - This command is identical to the Step-In
command, except that DIRG is set low and the Track
Register is decremented for each step pulse if the u bit is
high.
STEPPING RATE
TEST
3.1.1 Type I Command Option Bits
"
'0
ClK = lMHz
ClK = 2M Hz
The operation of the option determining bits for Type I
commands is summarized in Figures 3a and 3b.
H
0
0
6 ms
3 ms
H
0
,1
12 ms
6 ms
The detailed descriptions of the Type I option bits follow.
H
1
0
20 ms
10 ms
H
1
'1
30 ms
15 ms
l
- -
-400/,s
-200/,s
•
r1rO (Step Rate) - These bits select the rate at which
step pulses are issued. Notethatthestepping rates are
independent of DDEN select. Both single and doubledensity modes step at the same rate.
Figu,e 3b. Stepping Motor Rates
o V (VERIFY) - This bit is used to select track verification at
the end of the stepping sequence. During verification,
the head is loaded and after an internal 15*ms delay,
the HLT input is sampled. Note: IfTEST=O, the internal
delay to HLT sampling is < = 3001o's. When HLT is true,
the first encountered ID field is read from the disk. The
track address of the ID field is then compared to the Track
Register. If there is a mat,ch and a valid ID GRG, the
verification is complete, an interrupt is generated and
the Busy status bit is reset. If there is not a match, but
there is a valid ID GRG, an interrupt is generated, the
Seek Error status bit (status bit 4) is set, and the Busy
status bit is reset. 1fthere is a match but not a valid GRG,
the GRG Error status bit (status bit 3) is set, and the next
encountered ID field is read from the disk forthe verification operation. If an ID field with a valid eRG cannot be
found after four revolutions of the disk, the FDG terminates the operation and gerierates an interrupt.
o
the FDG receives a command to disengage the head. If
the FDG is idle(not Busy) for 15 disk revolutions, then the
head is automatically disengaged (HLD goes 10w).lftrack
verification is selected (V = "1 "), then the head loading is
affected, as follows:
-
h=O,V=1
HLD is activated near the end of the sequence, an
internal 15* msec delay occurs, and the FDG waits
for the HLT input to go active (high) before verifying
track identification.
-
h=1,V=1
HLD is activated at the start of the sequence. Then
an internal 15* msec delay occurs and the FDG
waits for HLT to go acti,ve befQre verification.
u (Update) - With Update selected (u = "1 "), the Track
Register is updated at each step pulse. The update operation increments the Track Register for stepping in
toward track 76 and decrements it for stepping out
, , toward track 0,
*30 msec delay for 1 MHz elK.
'0
h (Head Load) - This bit determines if the head is to be
loaded at the beginning of the command. If so, the HLD
output goes high (active) and remains in this state until
3-27
SY1791-02/SY1793-02
3.2.1 Type I Command Signals
3.2 Type" Commands
Type I commands control the operation of the STEP and
DIRC (Direction) output signals of the. FDC.
The Type II commands, Read Sector and Write Sector,
pe'rmit actual data to be read from or written onto the
disketie. Before the command is entered, it is necessary
for the processor to have loaded the Sector Reg'ister with
the number of the desired sector. Figure 5 is useful for
understanding the operation of Type II commands.
•. STEP - A 2 p.s (MFM) .or 4 p.s (FM) positive-true
output pulse is generated at a rate determined by the
r,ro field of the command (see Figure 3b). Each step
pulse moves the Read/Write head one track location
in a direction controlled, by the DIRC ·output.
•
DIRC - The DIRC output determines the direction of
the track stepping. A high level indicates step direction IN' towards track 76, a low level indicating direction OUT towards track 0. '
3.2.1 Type" Command Basic Operation Sequence
The basic operation of Type II commands is oLitlined as
the following sequence:
- The ID field is located by the detection of the ID AM
(ID Address Mark).
.
In addition, the Type I commands use the. following
signals:
•
HLD (Head Load) - This output is used to control
movement of the Read/Write head against the recording medium. HLD is set at the beginning of a Type I
command if h = "1", near the end of a Type I command if V = "1".and h = "0", or immediately when a
TYPE II or TYPE III command is executed. Once HLD is
set it remains high until a subsequentTypel command
with h = "0" and V= "0" is loaded~ or until the FDC goes
into its non-busy state after 15 index pulses.
-
The. Track Number in the ID field is compared to the
contents of the Track Register. If it does not,match,
then the ID AM search begins again.
-
As a selectable option, the Side Number is checked
for a match. If selected, a failure to match again
causes the ID AM search to re-star!.
-
The' Sector Number is compared to the contents ofthe
Sector Register. If there is not a match, the IDAM
.. search is again begun.
.
-
The Sector Length field is entered into the FDC and
stored internally for use in Read or Write operations.
The value of the Sector Length byte is determined
when the diskette' is formatted (initialized) and must
have one of the values in the table of Figure 6.
-
The ID field CRC1 and CRC2 bytes are checked with
internally generated .CRC. If they match, then the
command (Read or Write) is permitted; if not, the CRC
Error status bit is set and the search for the ID AM is
begun again.
• HLT (Head Load Timing) - The low to high transition
of this input indicates that a sufficient time has
elapsed for the drive's head to become engaged. It
typically follows HLD going high, by a time delay
which is dependent on the particular drive's characteristics. If not available from .the drive electronics,
this input must be generated by the user (typically by
means of one-shot timers). Figure 4 illustrates an
example of HLD and HLT timing.
If the Track Number, Side Number, Sector Number, and
CRC all check properly within 4 disk revolutions (5 index
pulses), then the commal1d gontinues; otherwise the
Record-Not-Found status bit is set and the command is
terminated with an interrupt (INTRQ).
The logical AND of HLD and HLTis status bit 5 for
Type I commands, and it controls the operation of the
disk read a'nd write functions.'
'
HLD
(OUTPUT)
...;.J~A~
.
. .... ' .
I
ti
' .. -..
HLT
(INPUT)
; .
--
. .
.
.
.
DUlENGAGE HEAD
SECTOR LENGTH
FIELD (hex)
NUMBER OF BYTES
IN SECTOR
00
128
256
512
1024
1---0\- - - - ... - HEAD
ENGAGED
\
HEAD DISENGAGED
\,,;,;---.--
.0'
02
03
HEAD RESPONSE TIME
(30ms - lOOms)
Figure4. HLD/HLTTiming Example
Figure 6. Sector Length Field Codes.
I
.1
10 FIELD
DATA FIELD
.Figure 5. General Track Format
3-28
§'V1 19~-02/SYt 193-02
BIT
4
2
7
6
5
1
0
1
0
0 m S
E C
0
READ SECTOR
1
0
1 m S
E C
ao
WRITE SECTOR
3
COMMAND
L
DATAADDRESSM
-
ARK ( ) So = Write hex FB (data) into Data Address Mark field
ao -U = Write hex F8 (deleted data) into Data AM field
COMPARE ENABL E (C)
---.ro = Side number not tested
U
= Side number tested
No delay between HLD activation and HLT Salnpling
' - - - DELAY (E)i]: 15 ms delay between HLD activating and HLT Sampling
SIDE NUMBER(S)
So = Compare SIDE Number LSB to 0
MULTIPLE SECTO
RS ( ) So = Read'(or Write) Single Sectors
m
= Read (or Write) Multiple Sectors
LJ = Compare SIDE,Number LSB to 1
L1
Figure 7. Type II Command Option Bits
3.2.2 Type II Command Option Bits
3.2.3 Type II Command Operation
Several bits in the Type II command words are used to
select various options. Figure 7 summarizes the special
control bits which are outlined, as follows:
The specific operation of the Read, Sector and Write
Sector commands, once the ID field is properly encountered, is outlined below:
o ao (Data AM) - The ao bit is used to select which of
two Data Address Mark bytes is to be stored in the
Data AM field for Write Sector operations. A "'" in ao
causes hex F8 to be stored, indicating that the data
field is actually deleted data. A "0" in ao causes hex
FB to be stored, indicating undeleted data.
o READ SECTOR - When the correct Track Number,
Side Number (if selected), Sector Number, and CRC
have been identified, the Data Field check commences. The Data AM must be found within 30 bytes for
single-density (or 43 bytes for double-density) from
the time the last CRC byte forthe ID field was encountered. If not, the Record-Not-Found bit in the Status
Register is set and the command is terminated. After
the Data AM is found, the data bytes are entered
through the internal Data Shift Register and transferred to the Data Register. Each byte transferred
results in a DRQ. The Data Register must be unloaded
(read) by the MPU or DMA controller before the next
byte is fully received. If not, then the new byte is
written over the previous byte in the Data Register,
the previous byte is lost, and the Lost Data status bit is
set. At the end of the Data Field, the CRC bytes are
compared to the internal CRC generated by the FDC.lf
they do not match, the CRC Error status bit is set and
the command is terminated, even'if it is a multiple"record command (m = ","). At the end of the
sequence, the Data AM encountered in the Data Field
determines bit 5 olthe Status Register. lithe Data AM
was hex FB (undeleted), then bit 5 is set to "0"; hex F8
(deleted data) causes bit 5 to be set to "'''.
o S (Side) - The S bit is compared with the LSB of the
Side Number (in the ID field), if the side number compare option has beim enabled by the C bit.
o
C (Compare) - This bit enables the comparison of the
Side Number (in the ID field) with the S bit of the
Type II command.
o E (Delay) - The E bit causes a '5 msec delay to be
inserted between the time the HLD (Head Load) output is activated and the time the HLT (Head Load
Timing) input is strobed and checked,
•
m (multiple Records) - ' This bit is used to select
whether one sector (m = "0") or more than one
sector (m = ",") is to be read or written. For single
sector operation, the interrupt is generated and the
command is terminated immediately after the sector
operation is complete. Multiple sector operation,
however, is somewhat different. After the first sector
operation is complete, the FDC Sector Register is
incremented and the sequence is re-started. In this
way, the next sequential sector number is read 'or
written. Likewise, after it is complete, the Sector Register is again 'updated and the sequence re-started.
This continues until the Sector Register has incremented to a number higher than any sector on the
current track. At this point, the sequence terminate's.
o WRITE SECTOR - The Write Sector cOrimiand operates in a fashion very similar to Read Sector. When
the correct Track Number, Side Number (if selected),
Sector Number, and CRC have been identified, a DRQ
is generated, requesting the first data byte which is to
be written on the diskette. The FDC then counts "
bytes for single-density (or 22 bytes for double"density) to account for part of the gap between the ID
SY1791-02/SY1793-02
and DATA fields (Gap 2 in Figure 5). At this point, if
the DRO has been serviced and a data byte stored in
the Data Register, the WG output goes true (high) and
6 bytes of zeroes for single-density (12 bytes for
double-density) are written on the diskette. This
accounts for the remainder of Gap 2. (If the DRO had
not been serviced, the Lost Data status bit would have
been set and the command terminated). Following
Gap 2, the Data AM is written. This byte is either hex
FB (undeleted data) or hex Fa (deleted data) and is
determined by the state of the ao bit in the command byte, (see Figure 7). Finally, the data is written
on the diskette, starting with the byte already loaded
in the Data Register. As each byte is transferred from
the Data Register to the Data Shift Register to be
stored on the diskette, a DRO is generated tothe MPU
or DMA control unit requesting the next data. If any
DRO is not serviced in time, the Lost Data status bit is
set and a byte of zeroes is stored on the diskette, but
the command is not terminated. After the last data
byte is stored on the diskette, the two-byte CRC (generated in the FDC) is then stored on the diskette.
Finally, after the CRC bytes, the FDC stores one more
byte (hex FF), the WG output goes low (false), and the
command is terminated.
·Busy status bit to be set. Reading of the track starts
with the next encountered Index pulse and continues
until the following Index Pulse. Each byte is
assembled and transferred tothe Data Register. As in
any normal read operation, a DRO output is generated
with each byte, signalling to the MPU or DMA control
unit that the byte is ready. CRC and Gap bytes are
treated as any other byte. No CRC checking is performed. When all bytes are transferred, the Busy status bit is cleared, and INTRa goes high.
• WRITE TRACK - The start of this command causes
the head to be 10aded(HLD active) and the Busy status
bit to be set. Data is written onto the track when the
first Index pulse is encountered, and terminated at
the subsequent Index Pulse. DRO is activated immediately after the command is issued to permit
adequate time for the first byte to be made available
before the Index is found. If this time is not enough
and the Index Pulse occurs before the Data Register is
loaded, then the command is terminated. Once the
data' transfers begin, the DRO is generated for each
byte as needed. Any byte which is nottransferred into
the FDC in time causesa byte of all zeroes to be stored
on the diskette instead. Address Marks and CRC bytes
are generated by the FDC in response to format
control bytes supplied by the system MPU or DMA
control unit. When all bytes are transferred, the
command is terminated, the Busy status bit is
cleared, and INTRa is set high.
3.3 Type III Commands
There are three Type III Commands:
•
READ ADDRESS into the FDC.
Read the next ID field (6 bytes)
•
READ TRACK inti udi ng gaps.
Read all bytes of the entire track,
• WRITE TRACK including gaps.
Write all bytes to the entire track,
3.4 Type IV Command
Force Interrupt is the only Type IV command. This
command permits the MPU to terminate (abort) any
command in progress. Figure a tabulates the Type IV
command option bits.
The four bits. 10-13. are used to select the condition of the
interrupt occurrence. Regardless of which bit is set. any
command currently being executed is immediately
terminated and the Busy status bit is cleared. indicating
"Not Busy". Then. when the condition is met •. INTRa·
goes high. causing the required interrupt.
3.3.1 Type III Command Option Bit
There is one option bit for type III commands.
•
E (DELAV) - This option bit acts the same for Type III
commands as it does for Type II commands. See
section 3.2.2 for further informati·on.
If lo-Is are all "0", no interrupt occurs. but any currently
executing command is immediately terminated. If more
than one condition is selected. then the interrupt occurs
when any of the conditions is met.
3.3.2 Type III Command Operation
•
•
READ ADDRESS - When this command is issued.
the head is loaded (HLD high) and the Busy status bit
is set. The next ID field encountered on the diskette is
then read a byte at a time, using DRO initiated data
transfers to the MPU or DMA controller. Six bytes are
entered; comprising the entire ID field. They are:
Track Number (1 byte); Side Number (1 byte); Sector
Number (1 byte); Sector Length (1 bv.te); and CRC (2
bytes). Although the CRC bytes are passed unaltered,
the FDC checks their validity and sets the CRC Error
status bit accordingly. Part of the operation of this
command causes the Track Number to be stored in
the Sector Register of the FDC. The. command ends
with the generation of an interrupt (INTRa) and the
clearing of the Busy status bit.
To clear the interrupt. it is necessary to read the Status
Register or towrite the Command Register. An exception.
however. is for 137' 1 (Immediate Interrupt). Forthis case.
the interrupt is cleared with another Force Interrupt
command with 10-13 all O.
3.5' Status Register
The Status Register permits the MPU to monitor a variety
of conditions in the FDC. For each command. the individual status bits have their own meaning. When a
command is .initiated (except for the Force Interrupt
command). the Busy status bit is set and the others are
cleared or updated. If the Force Interrupt command is
entered when a nother comma nd is in progress. the Busy
status bit is cleared. but the others remain unaffected.
However. if the Force Interrupt command is initiated
READ TRACK - The initiation of this command
causes the head to be loaded (HLD active) and the
3-30
Syt 79t-Ol/Syt 793-02
BIT
d d 5 [4'[ 3
, [ , [0 [ ,
COMMAND
[2 [ , [0
[13 [12 [11 [10
FORCE INTERRUPT
L
So = No effect
READY TRANSITION
--U = Forces INTRO when READY input goes low·to·high
' - - - NOT-READY TRANSITIO N
So = No effect
L:! = Forces INTRO when READY input goes high·to·low
effect
INDEX PULSE -G=NO
, = For ces INTRQ on next INDEX pulse input
IMM.EDIATE
---IO0= No effect
L.! -- Forces INTRO immediately
Figure 8. Force Interrupt Command Flags
4
3
2
,
0
Head
Loaded
Seek
CRC
Error
Track
Index
Busy
Record
Type
Ree not
Found
Ree not
Found
CRC
Lost
Data
ORO
Busy
Lost
Data
DRO
Busy
Rec not
Found
CRC
Lost
Data
ORO
Busy
STATUS
COMMAND
7
5
6
ALL TYPE I
Not
Ready
READ SECTOR
Not
Ready
0
Not
Ready
Write
Write
Protect
Fault
Not
Ready
0
READ TRACK
Not
Ready
0
WRITE TRACK
Not
Ready
WRITE SECTOR
READ ADDRESS
Write
Protect
Write
Protect
Error
0
BIT
Error
CRC
Error
Error
0
0
0
0
Lost
Data
ORO
Busy
Write
Fault
0
0
Lost
Data
ORO
Busy
Figure 9. Status Register Summary
when there is not another command in progress, the
other status bits are cleared or updated and represent
the Type I Command status. Figure 9 illustrates the
meaning of the status bits for each command.
o BUSY
0= Not Busy
1 = Busy (Command sequence in progress)
o RECORD TYPE
0= Non-deleted data mark
1 = Deleted data mark
Detailed descriptions of each status bit function follow:
•
•
•
•
•
•
NOT READY
Drive is Ready
1 = Drive is Not Ready
o=
o WRITE FAULT
0= No write fault
1 = Write fault has occurred
WRITE PROTECT
0= WPRT input is high (unprotected)
1 = WPRT input is low (protected)
HEAD LOADED
0= Head is not currently loaded
1 = Head is loaded and engaged (both HLD and HLT
are active)
SEEK ERROR
0= Desired track was found. Updating clears this bit
1 = Desired track was not found
TRACK 0
0= TROO input is high
1 = TROO input is low (Read/Write head is on
Track 0)
INDEX
o = fP input is high (no index mark)
1=
fP input is low (index mark)
3-31
•
RECORD NOT FOUND
0= Desired track and sector properly found.
Updating clears this bit
1 = Desired track and sector not found
•
CRC ERROR
0= No CRC error. Updating clears this bit
1 = CRC check error encountered
•
LOST DATA
0= No data lost. Updating clears this bit
1 = MPU did not respond to DRO. Data was lost
•
DATA REOUEST (DRO)
0= DRO not in progress. Updating clears this bit.
1 = DRO currently in progress
Syt 79t-02jSyt 793-02
r-
w----.,u
TRACK
N~~B=E:::~O
- 4A
COMPLETE SECTOR-i
J)
SINGLE SIDED: NUMBER = 00
DOUBLE SIDED. SIDE 0 = 00
DOUBLE SIDED. SIDE 1 = 01
SECTOR NO.
BYTES/SECTOR
FM
MFM
01-1A
01 - OF
256
256
512
01- 08
512
1024
128
SECTOR LENGTH
00 = 128
01 = 256
02 = 512
03 = 1024
* 38YTESOF Al;DR:: F5
Figure 10. IBM Compatible Sector/Track Format
4.0 DISK FORMATTING
with the last gap bytes at the end of the track. Figure 10
illustrates the IBM standard for track formatting.
Disk formatting (initialization) is accomplished by ~he
Write Track command. Each byte for the entire track
must be provided for proper formatting. This includes
gap as well as data bytes.
Normally. each data byte stored on the diskette mustbe
generated by the system MPU and passed intothe FDC
Data Register. However. there are exceptions to this
rule. If a data byte of hex F5 through FE is entered into
the Data Register. then the FDC recognizes this as Data
AM with missing clocks or CRC generation code. Consequently. F5 through FE must not be used in gaps. data
fields. or 10 fields. as'this will disrupt norm'al operation of
the FDC during formatting.
The sequence required to format a diskette begins with.
positioning the Read/Write head at the desired track.
Once this has been done. it is necessary to perform a
Write Track command to store all the information on a
track. The Write Track command uses ORO to request
each byte from the system MPU. starting with Hie byte at
the beginning of the physical Index Pulse and ending
3-32
Syt 19t-02/5Y1 793-02
4.1 IBM 3740 Format
DATA
BYTE
(hex)
This single-density (FM) format utilizes 128 bytes/
sector. The bytes to'be generated by the system MPU for
use in the execution of the Write Track command are
shown in Figure 11.
4E
00
F6
FC
4E
00
4.2 IBM System 34 Format
This double-density (MFM) format utilizes 256 bytes/
sector. The bytes to be generated by the system MPU for
use in the execution of the Write Track command are
shown in Figure 12.
NO. OF
BYTES
COMMENTS
Gap 5
(Post Index)
8:}12
Writes C2
3
1
Index AM
5~J12
Gap 1
F5
3
Writes 10 AM
Sync Bytes
Unique (non-IBM) formats are permissible providing the
following restrictions are understood.
FE
XX
1
1
• Sector length may only be 128, 256, 512, or 1024
bytes.
OX
1
IDAM
Track Numuer
(00-4C)
Side Number
(00 or 01)
XX
1
01
1
F7
1
4.3 Non-IBM Formats
•
Gap sizes must conform to Figure 13.
DATA
BYTE
(hex)
ONE
SECTOR
NO. OF
BYTES
FF
00
FC
FF
00
ONE
SECTOR
8
4:t
1
COMMENTS
Gap 5
(Post Index)
OX
1
XX
1
00
1
F7
1
l~r
lOAM
Track Number
(00-4A)
Side Number
(00 or 01)
Gap 2 (lD Gap)
3
Writes ID AM
Sync Bytes
FB
40
F7
1
256
1
4E
54
4E
598
Data AM
Data Field
Causes 2-Byte
CRC to be
Written
Part of Gap 3
(Data Gap)
Gap4
(Pre Index)
0
Sector Number
(OI-IA)
Sector Length
(128 bytes)
Causes 2-Byte
CRC to be
Written
Gap 2 (lD Gap)
FF
00
FB
E5
F7
1
128
1
Data AM
Data Field
Causes 2-Byte
CRC to be
FF
27
FF
247
Part of Gap 3
(Data Gap)
Gap 4
(Pre Index)
NOTES: 1. THIS PATTERN MUST BE
WRITTEN 26 TIMES PER
TRACK.
2. CONTINUE WRITING HEX
4E UNTIL FDC COMPLETES
SEQUENCE AND GENERATES
INTRQINTERRUPT.
Figure 12. Byte Sequence for IBM System-34 Formatting
GAP
Gap 1
Gap 2
Written
0
2~J
12
Index AM
2:t
1
1
(OI-IA)
Sector Length
(256 Bytes)
Causes 2-Byte
CRC to be
Written
4E
00
F5
Gap 1
FE
XX
Sector Number
Gap 3
NOTES: 1. THIS PATTERN MUST BE
WRITTEN 26 TIMES PER TRACK.
2. CONTINUE WRITING HEX FF
UNTI L FDC COMPLETES
SEQUENCE AND GENERATES
INTRQ INTERRUPT
Gap4
SINGLE
DENSITY
(FM)
16 bytes FF
11 bytes FF
6 bytes 00
10 bytes FF
4 bytes 00
16 bytes FF
DOUBLE
DENSITY
(MFM)
16 bytes 4E
22 bytes 4F
12 bytes 00
3 bytes Al
16 bytes 4E
8 bytes ·00
3 bytes Al
16 bytes 4E
NOTE
NOTES: 1. THESE BYTES COUNTS ARE EXACT.
2. THESE BYTES COUNTS ARE MINIMUM
EXCEPT FOR 3 BYTES A1. WHICH IS
EXACT;
Figure 11. Byte Sequence for IBM 3740 Formatting
Figure 13. Gap Size Limitations
3-33
2
1
2
2
SY179. -02jSY1793-02
5.0 ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Symbol
Allowable Range
Supply Voltage
Rating
Vee
-O.3V to +7 .OV
Input/Output
Voltage
VIN
-O.3V to+7.0V
Operating Temp.
Storage Temp.
Top
O°C to 70°C
TSTG
-55°C to 1500 e
All inputs contain protection circuitry to prevent damage to high
static charges. Care should be'exercised to prevent unnecessary application of voltages in excess of the allowable limits.
Stresses above those listed under "Absolute Maximum
Ratings"may cause permanent damage to the device. This is a
stress rating only and functional operation olthe device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied.
D.C. CHARACTERISTICS (Vee = 5V ± 5%, TA = 0-70 0 e)
SYMBOL
MIN
MAX
UNIT
VIH
2.6
-
ij
VIL
-
0.8
V
IlL
-
±10
J1.A
VOH
2.8
-
V
Output Low Voltage, ILOAD = 1.6 rnA
VOL
-
0.45
V
Output Leakage Current, VOUT = Vee
IDL
-
10
J1.A
Po
-
525
rnW
CIN
-
15
pF
CHARACTERISTIC
Input High Voltage
lriput Low Voltage
Input Leakage Current, V IN
= OV to Vee
Output High Voltage, ILOAD
Power Dissipation (Vee
Input Capacitance
= -100 J1.A
= 5.25V)
3-34
5)yn 719n-01/SYt 7/93-01
MPU READ CYCLE TIMING
MPU WRITE CYCLE TIMING
AO.Al
AD,A1
Cs
cs
WE
jfE
DBGDB7
DBODB7
ORO
ORO
INTRa
INTRa
MPU READ CYCLE REQUIREMENTS (Vcc = 5V ± 5%, TA
CHARACTERISTIC
SYMBOL
Address and CS Setup Time
TSET
RE Pulse Width
TRE
MIN
= 0-70°C)
MAX
UNIT
50
-
ns
400
-
ns
NOTE
Address and CS Hold Time
THLO
Data Access Time
TOACC
-
300
ns
CL
Data Hold Time
TOOH
50
150
ns
CL
DRO Reset Delay
TORR
-
500
ns
3000
ns
INTRa Reset Delay
TIRR
10
ns
= 50pF
= 50pF
1
1. Timing shown is for 2M Hz CLK frequency. For 1 MHz, this parameter is doubled.
MPU WRITE CYCLE CHARACTERISTICS (VCC
= 5V ± 5%, TA = 0-70°C)
CHARACTERISTIC
SYMBOL
MIN
MAX
UNIT
Address and CS Setup Time
TSET
50
ns
WE Pulse Width
TWE
350
-
ns
Address and CS Hold Time
THLO
10
-
ns
Data Setup Time
Tos
250
ns
Data Hold Time
TOH
20
-
DRO Reset Delay
TORR
-
500
ns
INTRa Rest Delay
TIRR
-
3000
ns
1. Timing shown is for 2MHz CLK frequency. For 1MHz, this parameter is doubled.
3-35
NOTE
ns
1
Syt 79t-02/Syt 793-02
SYSTEM CLOCK REFERENCE
INDEX PULSE INPUT
_---"'\.r-TIP---1~
.L--...t
IP
~TCYC----l
CLK~~
WRITE FAULT INPUT
_---"'\. r--- ---1 ~
'----I
TWF
I - T c 0 1 - - TC02-
~
WF
MASTER RESET INPUT
_---"'\.r--
TMR------j~
~
MR
MISCELLANEOUS TIMINGS (Vee = 5V ± 5%, TA = 0 -70 0 C)
CHARACTER ISTIC
SYMBOL
MIN
MAX
UNIT
NOTE
Clock Low Time
TeD1
230
20000
ns
2
Clock High Time
TCD2
200
20000
ns
D I RC Setup Time
TDIR
12
STEP Pulse Width
TSTP
2,4 or 8
/.Is
2
2
1
Index Pulse Width
TIP
10
-
/.Is
2
Write Fault Pulse Width
TWF
10
-
/.Is
2
TMR
50
-
/.IS
2
Master Reset Pulse Width
/.IS
1. Depends upon FM/MFM mode and ClK frequency. See timing figure below.
2. Timing shown is for 2 MHz clock: Minimum time doubles for 1 MHz clock.
STEP AND DIRECTION MOTOR CONTROL TIMING
DIRC
ETEPIN
(OUTPUT) _ _........
STEP
(OUTPUT)
STE;;..P;;;OU:;.:T_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
TOIR-~t~~- T S T P - : j ' - -_ __
l-
'-
~
TSTP PULSE WIDTH
MODE
FREQ.
MFM
FM
elK
1MHz
2MHz
3-36
(:}.TSTP
SY1791-01jSY1793-02
INPUT DATA TIMING CHARACTERISTICS
Tae
RAW READ
~
T'-r--
RCLK
If
i'-1
~ r--
J~
T,
~V
JI\
~~
Jr-..
Ta_
I----TA
Te
SYMBOL
DESCRIPTION
COMMENTS
Tc
Tc, RCLK's period, must be
greater than 1.5 J.lsec.
ClK
FREQ.
MODE
TA
Ts
T A and T s must each be
greater than 800 nsec.
lMHz
MFM
FM
2MHz
MFM
FM
RAW READ Pulse Width. Normally is
100·300 ns. May be any width providing
Tpw
Tsc
it is entirely within RCLK stable time. If
it extends beyond RC LK transition, then it
must be constrained by the values in the
table.
ClK
FREQ.
lMHz
2MHz
RAW READ Pulse Period
1.6 J.ls min. at 2 MHz
3.2 J.ls min. at 1 MHz
T" T2
ClK
FREQ.
lMHz
2MHz
NOMINAL RClK TIMES
TA
TB
Tc
2
2
4
4
4'
8
1
2
1
2
MODE
MFM 1 FM
.; GOOns I.; 1200ns
.; 300ns I.; GOOns
MODE
MFM I
FM
4, Gor 8~s 1 4 or 8~s
2,3 or 4~s 1 2 or 4~s
T, and T 2 must each be greater than 40 ns.
/
3-37
2
4
UNIT
~s
~s
~s
~s
SY. 79. -02/SY. 793-02
DISKETTE DATA TIMING CHARACTERISTICS
READ ENABLE TIMING
WRITE ENABLE TIMING
t--~-- TDW
-----I
DRO
WE--+---..
READ
DATA REGISTER
READ
DATA REGISTER
ClK
FREQ.
lMHz
2MHz
TRO
Tow
Two
max.
nom.
max.
32
27.0
32
23.0
jlS
64
55.0
64
47.0
JlS
MFM
16
13.5
16
11.5
jlS
FM
32
27.5
32
23.5
JlS
MODE
TOR
nom.
MFM
FM
WRITE DATA TIMING
WRITE GATE TIMING
WR1TE-i
WD
(OUTPUT)
UNIT
GATE
_
-1
............J
EARLY, LATE
(OUTPUTS)
WD
\1
Tw,
Twf- .
~S--5--11\,,--_
LASTWD
FIRSTWD
ClK
FREQ
MODE
Twp
Ts
Th
Twg
Twf
min.
max.
min.
min.
nom.
nom.
250
2000
4000
2000
4000
nsec
nsec
1000
2000
1000
2000
nsec
1 MHz
MFM
FM
300
900
500
1100
250
2 MHz
MFM
FM
150
450
250
550
125
-
-
-
3-38
t
1-
125
-
UNIT
nsec
SYNERTEK
A SUBSIDIARY OF HONEYWELL
SY2661
Enhanced
Programmable
Communications
Interface
MICROPROCESSOR
PRODUCTS
PRELIMINARY
SYNCHRONOUS OPERATION
• Automatic serial echo mode (echoplex)
• Local or remote maintenance loop back mode
o Baud rate: dc to 1 M bps (1 X clock)
dc to 62.5K bps (16X clock)
- dc to 15.625K bps (64X clock)
• 5 to 8-bit characters plus parity
• Single or double SYN operation
• Internal or external character synchronization
• Transparent or non-transparent mode
• Transparent mode DLE stuffing (Tx) and detection (Rx)
• Automatic SYN or DLE-SYN insertion
• SYN, DLE and DLE-SYN stripping
• Odd, even, or no parity
• Local or remote maintenance loop back mode
• Baud rate: dc to 1 M bps (1 X clock)
OTHER FEATURES
•
•
•
o
•
•
o
•
•
o
o
ASYNCHRONOUS OPERATION
•
•
•
•
•
•
Internal or external baud rate clock
• 3 ba ud rate sets (2661 -1, -2, -3)
5 to 8-bit characters plus parity
1, 1V, or 2 stop bits transmitted
Odd, even, or no parity
Parity, overrun and framing error detection
Line break detection and generation
False start bit detection
16 internal rates for each set
Double buffered transmitter and receiver
Dynamic character length switching
Full or half duplex operation
TTL compatible inputs and outputs
RxC and TxC pins are short circuit protected
3 open drain MOS outputs can be wire-ORed
Single 5V power supply
No system clock required
28-pin dual-in-Iine package
PIN CONFIGURATION
D,
D,
D3
Do
DATA BUS
0 0 -°7
RxD
RxC/BKDET
GND
D4
DTR
RESET
D5
RTS
AO
D6
DSR
D,
RESET
TxC/SYNC
BRCLK
A,
TxD
CE
TxEMT/DSCHG
Ao
CTS
RIW
RxRDY
CE
DCD
ClK
TxRDY
hC
RxC
---
---c
---
---c
DCD - - c
CTS ---c
RTS ---c
DTR ---c
Part No.
SYP2661·X
SYD2661-X
SYC2661·X
Package
Plastic
---v
BUFFER
.....
t
OPERATION
CONTROL
MODE
REGISTER 1
MODE
REGISTER 2
COMMAND
REGISTER
STATUS
REGISTER
BAUD-RATE
GENERATOR
AND CLOCK
CONTROL
SYN/DlE
CONTROL
SYN 1
REGISTER
SYN 2
REGISTER
DlE
REGISTER
.;"l-
y-
-
.....
-'"
Y
'-
TIMING
TRANSMITTER
TRANSMIT
DATA
HOLDING
REGISTER
TRANSMIT
SHIFT
REGISTER
.....
-
MODEM
CONTROL
TxEMT/.--c
DSCHG
Figure 1. Block Diagram
(See Table 1)
3-39
-
TxO
RECEIVER
Cerdip
Cerami,c
X=l,2or3
:>--
~
Vt-
DSR
ORDERING INFORMATION
"-
DATA BUS
RECEIVE-
DATA
:r--
HOLDING
REGISTER
RECEIVE
SHIFT
REGISTER
-
RxD
!i
SY2661
Table 1
Baud Rate Generator Characteristics
2661-1 (BRCLK=4.9152 l1liHz)
3
MR2
2
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Baud Rate
Actual Frequency
16X Clock (KHz)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
50
75
110
134.5
150
200
300
600
1050
1200
1800
2000
2400
4800
9600
19200
0.8
1.2
1.7598
2.152
2.4
3.2
4.8
9.6
16.8329
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2
. Percent Error
Divisor
-
-
6144
4096
2793
2284
2048
1536
1024
512
292
256
171
154
128
64
32
16
Percent Error
Divisor
0.005
6752
6144
4096
2793
2284
2048
1024
512
256
171
154
128
64
32
16
8
-0.01
-
0.196
-0.19
-0.26
-
-
2661-2 (BRCLK = 4.9152 MHz)
3
MR2
2
1
0
Baud Rate
Actual Frequency
16X Clock (KHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
.1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
45.5
50
75
110
134.5
150
300
600
1200
1800
2000
2400
4800
9600
19200
38400
0.7279
0.8
1.2
1.7598
2.152
2.4
4.8
9.6
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2
614.4
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
-0.01
-
-0.19
-0.26
-
2661-3 (BRCLK = 5.0688 MHz)
3
MR.2
2
1
0
Baud Rate
Actual Frequency
16X Clock (KHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
50
75
.110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
0.8
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Percent Error
0.016
-
0.253
-
-
3.125
Divisor
6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16
Note: 16X ClK is used in asynchronous mode. In synchronous mode. clock multiplier is 1X and BRG can be used only for TxC.
3-40
$\'1661
are sampled on the rising edge. If internal Receiver Clock is
programmed this pin will provide an output, either a 1 X/16X
clock or Break Detect signal determined by programming
Mode Register 2.
SIGNAL DESCRIPTIONS
CPU INTERFACE
RESET (Reset)
A high on this input performs a master reset on the SY2661.
This signal asynchronously terminates any device activity
and clears the mode, command and status registers. The
device assumes the idle state and remains there until initialized with the appropriate control words.
TxC/XSYNC (Transmitter Clock/External SYNC)
When the EPCI is programmed for External Transmitter
clock, this pin will act as an input and control the rate at
which the character is transmitted. The frequency is programmed in Mode Register 1 and may be 1 X, 16X or 64X the
baud rate. Data changes on the falling edge of this clock. If
the UPCI is programmed for Internal Transmitter clock, this
pin can be either an output providing a 1 X/16X clock or an
input for External Synchronization determined by Mode Register 2 programming.
A o, A, (Address 0, 1)
Address lines used to select the internal registers.
R"/W (Read/Write)
The direction of data transfers between the EPCI and the
CPU is controlled by the "R/W input. When CE and R"/W are
both low the contents of the selected registers will be transferred to the data bus. With CE low and R"/W high a write to
the selected register is performed.
RxD (Receive Data)
RxD is the serial data input to the receiver.
TxD (Transmit Data)
CE (Chip Enable)
When low, the selected register will be accessed. When high
the 0 0 -0 7 lines will be placed in the high impedance state.
TxD is the serial data output from the transmitter. When the
transmitter is disabled the output will be in the high, "Mark",
state.
DBo-DB7 (Data Bus)
DSR (Data Set Ready)
An 8-bit three-state positive true data bus used to transfer
commands, data and status between the EPCI and the CPU.
DSR is an input that can be used to indicate to the UPCI Data
Set Ready or Ring Indicator. Its complement appears in the
Status Register as bit SR7. A change of state on DSR will
cause TxEMT IDSCHG to go low if either CRO or CR2 = 1.
TxRDY (Transmitter Ready)
This output is the complement of status register bit SRO.
When low, it indicates that the transmit data holding register
(TxHR) is ready to accept a data character from the CPU. It
goes high when the data character is loaded. This output is
valid only when the transmitter is enabled. It is an open drain
output which can be '·wire-ORed" to the CPU interrupt.
DCD (Data Carrier Detect)
The DCD input must be low for the receiver to operate. If
DCD goes high while receiving, the RxC is internally inhibited. The complement of DCD appears in the Status
Register as bit SR6. A change of state in DCD will cause
TxEMTIDSCHG to go low if either CRO or CR2 = 1.
RxRDY (Receiver Ready)
CTS ( Clear To Send)
This output is. the complement of status register bit SR1.
When low, it indicates that the receive data holding register
(RxHR) has a character ready for input to the CPU. It goes
high when the RxHR is read by the CPU and also when the
receiver is disabled. It is an open drain output which can be
"wire-ORed" to the CPU interrupt line.
The CTS input must be low for the transmitter to operate. If
CTS goes high while transmitting, the character currently in
the Transmit Shift Register will be transmitted before termination TxD will then go to the high level (Mark).
DTR (Data Terminal Ready)
TxEMT IDSCHG
The DTR output is the complement of CR1. It is normally
used to indicate Data Terminal Ready.
This output is the complement of status register bit SR2.
When low, it indicates that the transmitter has completed
serialization of the last character loaded by the CPU, or that a
change of state of the DSR or DCD inputs has occurred. This
output goes high when the status register is read by the CPU
if the TxEMT condition does not exist. Otherwise, the TxHR
must be loaded by the CPU for this line to go high. It is an
open drain output which can be "wire OR-ed" to the CPU
interrupt line.
RTS (Request To Send)
The RTS output is the complement of CR5. If the Transmit
Shift Register is not empty when CR5 is reset, RTS will not
go high until one TxC after the last serial bit is transmitted.
FUNCTIONAL DESCRIPTION
The internal organization of the EPCI consists of six major
blocks, (see Fig. 1). These are the Transmitter, Receiver,
Clock Control, Operation Control, Modem Control and SYNIDLE Control. These blocks internally communicate over
common data and control buses. The data bus is also linked
to the CPU via a bi-directional three-state interface.
TRANSMITTER/RECEIVER SIGNALS
BRCLK (Baud Rate Clock)
Clock input to the internal baud rate generator. This is not
required when external receiver and transmitter clocks are
used.
Briefly, these blocks perform the following functions:
RxC/BKDET (Receiver Clock, Break Detect)
Transmitter
When the EPCI is programmed for External Receiver Clock,
this pin will act as an input and control the rate at which a
character is received. The frequency is programmed in Mode
Register 1 and may be 1 X, 16X or 64X the baud rate. Data
The Transmitter receives parallel data from the CPU and
converts it to a serial bit stream, inserting Start, Stop, and
Parity bits, as selected by the user, and outputs a composite
serial data stream.
3-41
SY1661
Receiver
The Receiver accepts serial data from the sending device,
converts it to a parallel format checking for appropriate Start,
Stop and Parity bits and Control Characters, as selected by
the user, and sends the assembled character to the CPU.
Timing Control
The Timing Control block contains a programmable Baud
Rate Generator (BRG) which is able to accept external
Transmit (TxC) or Receive (RxC) clocks or to divide external
clock (BRCLK) for controlling data transfers. The BRCLK input
allows the user to program one of 16 commonly used baud
rates.
Operating Control
The Operation Control block contains four registers; Mode
Registers 1 and 2, (MR1, MR2) the Command Register (CR)
and Status Register (SR). These registers are used to store
configuration and operation commands from the CPU. They
generate the necessary internal control signals for proper
device operation, and maintain status information for the
CPU.
Modem Control
The modem control section provides interfacing for three
input signals and three output signals used for "handshaking" and status indication between the CPU and a modem.
SYN/OLE Control
This section contains control circuitry and three 8-bit registers storing the SYN1, SYN2, and DLE character provided by
the CPU. These registers are used in the synchronous mode
of operation to provide the characters required for synchronization, idle fill and data transparency.
OPERATION
The EPCI's operation is determined by programming the
Mode and Command Registers. Baud rate, asynchronous or
synchronous communication, and SYN characters are determined before enabling the transmitter or receiver.
Asynchronous Receiver Operation
After the Mode Registers are configured the receiver is
enabled when the RxEN bit in the Command Register (CR2)
is set to a 1 and DCD is low. The EPCI then monitors the RxD
input waiting for a high to low transition. If a transition is
detected, the RxD input is again sampled one-half bit time
later. If RxD is now high, a search for a valid start bit is begun
again. If RxD is still Iowa valid start bit is assumed and the
receiver continues to sample the RxD input at one bit time
intervals until the correct number of data bits, parity bit and
one stop bit have been assembled. The character is then
transferred to the Receive Data Holding Register (RxHR);
RxRDY in the status Register is set (SR1); the RxRDY output
goes low. If the character length is less than 8 bits, the high
order unused bits in the holding register are set to zero. The
parity error, framing error, and overrun error status bits are
strobed into the status register on the positive going edge of
RxC corresponding to the received character boundry. See
Figure 6 and 8.
If the stop bit is present, the receiver will immediately begin
its search for the next start bit. If the stop bit is absent (fram-
ing error), the receiver will interpret a space bit if it persists
into the next bit time interval. If a break condition is detected
(RxD is low for the entire character as well as the stop bit),
only one character consisting of all zeros (with the FE status
bit set) will be transferred to the holding register. The RxD
input must return to a high condition before a search for the
next start bit begins. See Figure 9.
Pin 25 can be programmed as a Break Detect (BKDET) output
by setting both bits 4 and 7 of Mode Register 2 (MR2). When
these bits are set and a break is detected, the BKDET output
will go high. If RxD returns high for at least one RxD time,
BKDET will return low.
Synchronous Receiver Operation
When the EPCI is programmed for synchronous operation
the receiver will remain idle until the receiver enable bit
(CR2) is set. At this time the EPCI enters the hunt mode. Data
are shifted into the receive data shift register (RxSR) one bit
at a time. The contents of RxSR are then compared to the
contents of the SYN1 register. If the two are not equal, the
next bit is shifted in and the comparison is repeated. When
the two registers match, the hunt mode is terminated and
character assembly mode begins. If single SYN operation is
programmed, the SYN DETECT status bit is set. If double SYN
operation is programmed, the first character assembled after
SYN1 must be SYN2 in order for the SYN DETECT bit to be
set. Otherwise the EPCI returns to the hunt mode. (Note
that the sequence SYN1-SYN1-SYN2 will not achieve
synchronization). See Figure 6.
When synchronization has been achieved, the EPCI continues to assemble characters and transfer them to the
holding register, setting the RxRDY status bit and asserting
the RxRDY output each time a character is transferred. The
PE and OE status bits are set as appropriate. Further receipt
of the appropriate SYN sequence sets the SYN DETECT sta1us bit. If the SYN stripping mode is commanded, SYN
characters are not transferred to the holding register. Note:
the SYN characters used to establish initial synchronization
are not transferred to the holding register in any case.
By setting MR24 (MR2 bit 4) and MR27 = 1 pin 9
(RxC/XSYNC) will be programmed as an external jam synchronization input. When XSYNC is selected internal SYN1,
SYN1-SYN2 and DLE-SYN1 detection is disabled. Each positive going signal on XSYNC will cause the receiver to
establish synchronization on the rising edge of the next RxC
pulse. Character assembly will start with the RxD input at
this edge. XSYNC must be lowered prior to the next rising
edge of RxC. This external synchronization will cause the
SYN DETECT status bit to be set until the status register is
read. Refer to XSYNC timing diagram.
ASYNCHRONOUS TRANSMITTER OPERATION
When the EPCI is programmed to transmit the transmitter
will remain idle until CTS is low and the TxEN bit (CRO) is set.
The EPCI will respond by setting status register (SR) bit 0 and
asserting the TxRDY output. When the CPU writes a character into the transmit data holding register (TxHR), SRO is
reset and TxRDY returns high. The character is then transferred to the transmit shift register (TxSR) when it is idle or
has completed transmission of the previous character. SRO
is again set, and TxRDY goes low. See Figure 7.
3-42
In the asynchronous mode, the transmitter automatically
sends a start bit· followed by the programmed number of data
bits, the least significa[1t bit being sent first It then appends
an optional odd or even parity bit and the programmed
number of stop bits. If, following transmission of the data bits,
a new character is not available in the transmit holding register, the TxO output remains in the marking (high) condition
and the TxEMT/OSCHG output and its corresponding status
bit are asserted. Transmission resumes when the CPU loads
a new character into the holding register. The transmitter
can be forced to output a continuous low (BREAK) condition
by setting CR3.
SYNCHRONOUS TRANSMITTER OPERATION
When the EPCI is initially programmed for synchronous
transmission it will remain in the idle state (RxO high) until
TxEN is set At this point TxO remains high, TxROY will go
low and both will stay in this state until the first character
(usually a SYN character) is written into the TxHR. This starts
transmission, with TxROY going low each time a character is
shifted from the TxHR to the TxSR. If TxROY is not serviced
before the previous character is shifted out of the TxSR, the
TxEMT output will go low and the EPCI will automatically fill
the pending gap with SYN1, SYN1, SYN2 doublets, or OLESYN1 doublets, depending on the state of MR6 and MR17.
Transmission will be continuous until TxEN is reset to O.
See Figure 7.
If the send OLE bit (CR3) is set. the OLE character is automatically transmitted prior to the transmission of any character
stored in the TxHR. Since this is a one time command, CR3
does not have to be reset.
EPCI PROGRAMMING
Before data communications can be started the EPCI must be
programmed by writing to its mode and command registers.
Additionally, if synchronous communication has been selected the appropriate SYN1, SYN2 and OLE registers must be
loaded. Reference the Register Addressing Table and Initialization Flow Chart for address requirements and. programm i ng proced ure.
The Register Addressing table shows MR1 and MR2 at the
same address. The EPCI has an internal pointer that initially
directs the first read or write to MR1, then on the next access
at that same address the pointer directs the operation to
MR2. A similar sequence occurs for the SYN and OLE registers; first SYN1 then SYN2 then OLE. If more than the
required number of accesses are made the internal pointer
resets to the first register. The pointer is also reset to MR1
and SYN1 by a RESET input or a read of the Command Register, but unaffected by any other read or write operation.
MODE REGISTER 1 (MR1)
MR11 and MR1 0 select the communication mode and baud
rate multiplier. Note: the multiplier in asynchronous mode
applies only if the external input option is selected by MR24
and MR25.
MR13 and MR12 select Character length. Character length
does not include the parity bit, when selected, and does not
include the start and stop bits in asynchronous operation.
MR14, when set, selects parity. A parity bit will be transmitted with each character, and a parity check will be performed
on each character received.
MR15 selects either odd or even parity.
In the asynchronous mode MR16 and MR17 select the
number of stop bits; 1, 1.5 or 2. If 1 X baud rate is programmed 1.5 stop bits defaults to 1 on transmit.
In the synchronous mode MR17 controls the number of SYN
characters used to establish synchronization, and the
number of fill characters to be transmitted when TxROY and
TxEMT are O.
MR16 controls selection of the transparent mode. When
MR16 is set (transparent selected) OLE-SYN1 is used for
character fill and SYN detect (SR 5), but the normal synchronization sequence is used to establish character sync.
When transmitting in the synchronous transparent mode, a
OLE character in the TxHR will cause a second OLE character
to be transmitted. Note: if the send OLE command (CR3) is
active when a DLE character is in the TxHR only one additional OLE will be transmitted.
The bits in the mode register affecting character assembly
and disassembly (MR12-MR16) can be changed dynamically
(during active receive/transmit operation). The character
mode register affects both the transmitter and receiver;
therefore in synchronous mode, changes should be made
only in half duplex mode (RxEN = 1 or TxEN = 1, but not both
simultaneously = 1). In asynchronous mode, character
changes should be made when RxEN and TxEN = 0 or when
TxEN = 1 and the transmitter is marking in half duplex mode
(RxEN =0).
To effect assembly/disassembly of the next received/transmitted character, MR12-15 must be changed within n bit
times of the active going state of RxROY /TxROY. Transparent
and non-transparent mode changes (MR16) must occur
within n-1 bit times of the character to be affected when the
receiver or transmitter is active. (n = smaller of the new and
old character lengths.)
MODE REGISTER 2 (MR2)
MR20 through MR23 select the internal Baud Rate Generator (BRG). There are sixteen selectable rates for each version
as outlined in Table 1.
MR24 through MR27 define the receive and transmit clock
source and the function of pins 9 and 25. Reference Figure 3.
REGISTER FORMATS
The register formats are summarized in Figures 2 through 5.
MR1 and MR2 define the general operating characteristics.
The Command Register controls the basic operation defined
by MR1 and MR2. The Status Register indicates the EPCI
operating status and the condition of external inputs. These
registers are cleared by a RESET input (SR6 and SR7
excepted).
3-43
!5
SY2661
Table 2
CE
A,
1
0
0
0
0
0
0
0
0
X
0
0
0
0
1
1
1
1
SY2661 Register Addressing
Ao
X
0
0
1
1
0
0
1
1
R/W
X
0
1
0
1
0
1
0
1
Function
Three-state Data Bus
Read Receive Holding Register (RxHR)
Write Transmit Holding Register (TxHR)
Read Status Register (SR)
Write SYNl ISYN2/DLE Registers
Read Mode Registers (MR1, MRl IMR2)
Write Mode Registers (MR1, MRl IMR2)
Read Command Register
Write Command Register
EPCI Initialization Flow Chart
INITIAL RESET
NOTE: MODE REGISTER 1 MUST BE
WRITTEN BEFORE 2 CAN BE WRITTEN. MODE REGISTER 2 NEED NOT
BE PROGRAMMED IF EXTERNAL
CLOCKS ARE USED.
3-44
SY2661
n
1716151413121'101
ASYNC MODE
7
0
0
1
1
STOP BITS
6
INVALID
1
1%
2
0
1
0
1
Lo,,,,=
PARITY
5
4
TYPE
CONTROL
0
0
1
1
o·
x
ODD
x
EVEN
DISABLED
ENABLED
DISABLED
ENABLED
1
0
1
~
1
0
MODE
0
0
1
1
0
1
0
1
SYNC
6
0
0
1
1
0
1
0
1
NO. OF
SYNC
CHAR.
TRANSPARENCY
CONTROL
FILL
CHAR.
SYN1-SYN2
NORMAL
TRANSPARENT
NORMAL
SYN1-SYN2
DLE-SYNl
SYNl
TRANSPARENT
DLE-SYNl
SYN1-SYN2
SYNl
SYN1
ASYNC
1x
1x
16x
64x
CHARACTER LENGTH
SYNC MODE
7
ASYNC
ASYNC
BAUD RATE
FACTOR
SYNC
MODE
DOUBLE
SINGLE
3
2
BITS
0
0
0
1
1
1
0
5
6
7
1
B
Figure 2. Mode Register 1
ter still in the TxSR. TxD will then go tO,the marking state and
TxRDY and TxEMT will go high. Refer to Transmit timing
diagram.
[ 7 [ 6 [ 5 [4 [ 3 [ 2 [1 [ 0 [
I
SEE BAUD RATE TABLES
7
6
5
4
TxC
RxC
PINS
PlN25
MODE
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
I
0
0
1
1
0
E
E
I
I
E
E
I
I
I
E
I
I
I
E
I
I
E
I
E
I
E
I
E
I
E
I
E
I
E
I
E
I
TxC
TxC
1x
1x
TxC
TxC
RxC
1x
RxC
Ix
RxC
16x
RxC
16x
RxC
BKDET
RxC
SYNC/ASYNC
SYNC/ASYNC
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
I
0
1
0
I
0
1
0
1
0
1
0
0
0
1
1
0
1
1
CR1 controls the DTR output. The DTR output is a logical
complement of CR1.
I
I
16x
16x
XSYNC
TxC
XSYNC
1x
XSYNC
TxC
XSYNC
16x
SKDET
RxC
SKDET
RxC
BKDET
CR2 (RxEN) will enable or disable the receiver. When RxEN =
0, the receiver is in an idle mode with RxRDY high. A 0 to 1
transition of RxEN will initiate a start bit search in asynchronous mode or initiate the hunt mode in synchronous
transmission. A 1 to 0 transition of RxEN immediately terminates receiver operation.
SYNC!ASYNC
SYNC!ASYNC
SYNC/ASYNC
In the asynchronous mode setting CR3 will force the TxD
output low (break condition) at the end of the current transmitted character. TxD will then remain low until CR3 is
cleared; at that time TxD will go high for a minimum 1 bit
time before resuming normal transmission.
SYNC!ASYNC
SYNC!ASYNC
SYNC/ASYNC
SYNC
ASYNC
SYNC
ASYNC
SYNC
ASYNC
In the synchronous mode setting CR3 will force the transmission of the DLE character prior to sending the character
in the TxHR. Because this is a one-time command, bit 3 will
automatically reset.
SYNC
ASYNC
Figure 3. Mode Register 2
CR5 controls the state of the RTS output. When CR5 = 1,
RTS will go low and the transmit logic will be enabled. A 1 to
o transition of CR5 will cause RTS to go high one TxC time
after the last serial bit is transmitted, (if the TxSR was not
already empty).
CR7 and CR6 provide four alternate modes of operation in
both synchronous and asynchronous operation. When both
bits are 0 normal operation is selected.
COMMAND REGISTER (CR)
CRO (TxEN) will enable or disable the transmitter. When
TxEN = 0, TxD, TxRDY and TxEMT are all high, the transmitter is disabled. When TxEN goes active, TxRDY will go low
requesting the first character to be written to the TxHR, and
the TxD output will be enabled to transmit. When TxEN goes
inactive, the UPCI will complete transmission of any charac-
In the asynchronous mode, when only CR6 is set automatic
echo mode is selected. Clocked, regenerated received data
are automatically directed to the TxD line while normal
receiver operation continues. The receiver must be enabled
3-45
SY2661
(CR2 = 1), but the transmitter need not be enabled. CPU to
receiver communications continues normally, but the CPU to
transmitter link is disabled. Only the first character of a break
condition is echoed. The TxD output will go high until the
next valid start is detected. The following conditions are true
while in automatic echo mode:
1. Data assembled by the receiver are automatically placed
in the transmit holding register and retransmitted by the
transmitter on the TxD output.
2. Transmit clock = receive clock.
3. TxRDY output = 1.
4. The TxEMTIDSCHG pin will reflect only the data set
change condition.
5. The TxEN command (CRO) is ignored.
In the synchronous mode, when only CR6 is set automatic
SYN/DLE stripping is performed. The state of MR17 and
MR16 controls which characters are stripped. Reference
Figure 6 for a detailed example of the characters stripped.
Note: automatic stripping does not affect setting of the SYN
and DLE detect status bits.
Two diagnostic modes are achievable in both synchronous
and asynchronous operation; local loop back with CR7 = 1
and CR6 = 0, and remote loopback with both bits = 1.
Local Loop Back
1.
2.
3.
4.
5.
The transmitter output is connected to the receiver input.
DTR is connected to DCD and RTS is connected to CTS.
Transmit clock is connected to the receive clock.
The DTR, RTS and TxD outputs are held high.
The CTS, DCD, DSR and RxD inputs are ignored.
Note: CR bits 0, 1 and 5 must be set, CR2 is a don't care.
Remote Loop Back
1. Data assembled by the receiver are automatically placed
in the transmit holding register and retransmitted by the
transmitter on the TxD output.
2. Receive clock is connected to the transmit clock.
3. No data are sent to the local CPU, but the error status
conditions (PE, OE, FE) are set.
4. The RxRDY, TxRDY, and TxEMTIDSCHG outputs are held
high.
5. CRl (TxEN) is ignored.
6. All other signals operate normally.
STATUS REGISTER
SRO is the transmitter ready (TxRDY) status, it is the logical
complement of the TxRDY output. This bit indicates the state
of the TxHR when the transmitter is enabled (TxEN = 1). A 0
indicates TxHR is full, a 1 indicates TxHR is empty and
requires servicing by the CPU. This bit is cleared by writing to
TxHR or by disabling the transmitter (Ti0-'--. SYSTEM
CLOCK
3-64
SYE6500
8-BitMicroprocessor
SYE6500A
family
MICROPROCESSOR.
PRODUCTS
i Extended Temperature
SYNERTEK· (-40°C to +85° C)
A SUBSIDIARY OF HONEYWELL
o Single 5 V ±5% power supply
o N channel, silicon gate, depletion load technology
o Eight bit parallel processing
o 56 Instructions
o Decimal and binary arithmetic
o Thirteen addressing modes
o True index.ing capability
o Programmable stack pointer
o Variable length stack
o Interrupt capability
o Non-maskable interrupt
o Use with any type or speed memory
oBi-directional Data Bus
o
o
o
o
o
o
o
o
Instruction decoding and control
Addressable memory range of up to 65 K bytes
"Ready" input
Direct memory access capability
Bus compatible with MC6800
Choice of external or on-board clocks
1 MHz and.2 MHz operation
On-chip clock options
• External single clock input
• Crystal time base input
o 40 and 28 pin package versions
o Pipeline architecture
o Operation over wide temperature range
(_40°C to +85°C)
The SYE6500 Series Microprocessors represent the first totally software compatible microprocessor family_ This family of
products includes a range of software compatible microprocessors which provide a selection of addressable memory range,
interrupt input options and on-chip clock oscillators and drivers_ All of the microprocessors in the SYE6500 family are
software compatible within the group and are bus compatible with the MC6800 product offering_
The family includes six microprocessors with on-board clock oscillators and drivers and four microprocessors driven by
external clocks_ The on-chip clock versions are aimed at high performance, low cost applications where single phase inputs
or crystals provide the time base_ The external clock versions are geared for the multi-processor system applications where
maximum timing control is mandatory_ All versions of the microprocessors are available ·in 1 MHz and 2 MHz maximum
operating frequencies_
MEMBERS OF THE FAMILY
PART NUMBERS
PINS
IRQ
NMI
RDY
ADDRESSING
On-Chip
40
28
.J
.J
16 (64 K)
12 (4K)
SYEC6504
SYEC6505
"
28
.J
.J
.J
.J
.J
.J
"
"
.J
12 (4 K)
.J
.J
13 (8 K)
.J
12 (4K)
Plastic
Cerdip
Ceramic
SYEP6502
SYED6502
SYEC6502
SYEP6503
SYED6503
SYEC6503
SYEP6504
SYED6504
SYEP6505
SYED6505
CLOCKS
28
SYEP6506
SYED6506
SYEC6506
"
28
SYEP6507
SYEP6512
SYED6507
SYED6512
SYEC6507
"
28
SYEC6512
External
40
SYEP6513
SYED6513
SYEC6513
28
SYEP6514
SYED6514
SYEC6514
SYEP6515
SYED6515
SYEC6515
"
"
"
28
28
3-65
.J
.J
.J
.J
13 (8 K)
12 (4K)
.J
.J
16 (64 K)
12 (4K)
13 (8 K)
SYE6500/SYE6500A
D.C. CHARACTERISTICS
MAXIMUM RATINGS
Rating
COMMENT
Symbol
Value
Unit
Supply Voltage
Vee
-0.3 to +7.0
V
Input Voltage
Vin
-0.3 to +7.0
V
TA
TSTG
-40 to +85
°c
-55 to +150
°c
Operating Temperature
Storage Temperature
This device contains. input protection against damage due to high
static voltages or electric fields; however, precautions should be
taken to avoid application of voltages higher than the maximum
rating.
D.C. CHARACTERISTICS (Vee = 5.0V ± 5%, TA = _40°C to +85°C)
(.p"
2 applies to SYE651 X,
.po (jn)applies to SYE650X)
Symbol
V IH
Logic, 00 lin)
0" O2
V IL
Logic, 00 lin)
I.In
Max.
Unit
(650X)
(651X)
+2.4
Vee - 0.5
Vee
Vee + 0.25
V
(650X)
(651X)
-0.3
-0.3
+0.4
+0.2
V
-10
-300
J.1A
-
J.1A
J.1A
J.1A
Input Low Voltage
0" O2
'lL
Min.
Characteristic
Input High Voltage
Input Loading
(Vin = 0 V, Vee = 5.25 V)
ROY, S.O.
Input Leakage Current
(Vin = 0 to 5.25 V, Vee = 0)
Logic (Excl. ROY, S.O.)
(651X)
0" O2
(650X)
00 lin)
-
2.5
100
10.0
Three·State (Off State) Input Current
(Vin = 0.4 to 2.4 V, Vee = 5.25 V)
OBO-OB7
-
10
J.1A
2.4
-
V
-
0.4
V
-
700
mW
RES, NMi, ROY,IRQ, S.O., OBE
-
10
OBO-OB7
-
15
Cout
AO-A15, R/W,SYNC
-
12
C0alin )
C0 ,
001in )
0,
O2
' TSI
-
V OH
Output High Voltage
(I LOAD = -100J.1Adc, Vee = 4.75 V)
SYNC, OBO:OB7, AO-A15, R!W
VOL
O,_'tput Low Voltage
(lLOAD
PD
C
C in
CO2
= 1.6mAde, Vec = 4.75
V)
SYNC, OBO-OB7, AO-A 15, R!W
Power Dissipation
1 MHz and 2 MHz
Capacitance
(Vin = 0, T A
= 25°C, f
Vee = 5.25V
= 1 MHz)
(650X)
-
15
(651X)
-
50
(651X)
-
80
Note: IRQ and NMI require 3 K pull-up resistors.
3-66
pF
SY6510j6510A
SY6810j68B10
Peripheral Intetface
Adapter (PIA)
MICROPROCESSOR
PRODUClS
SYNERTEK
/\ SUBSIDIAflY OF HONEYWELL
• Direct Replacement for MC6820
., Single +5V Power Supply
• Two 8-bit Bi-directional I/O Ports with Individual
Data Direction Control
• CMOS-Compatible Peripheral Port A Lines
•
•
o
•
Automatic "Handshake" Control of Data Transfers
Programmable Interrupt Capability
Automatic Initialization on Power Up
1 and 2 MHz Versions
The SY6520 Peripheral Interface Adapter (PIA) is designed to provide a broad range of peripheral control
to microcomputer systems_ Control of peripheral devices is accomplished through two 8-bit bi-directional
I/O ports. Each I/O line may be programmed to be
either an input or an output. In addition, four peripheral control lines are provided to perform "handshaking" during data transfers.
PIN ASSIGNMENTS
BASIC SY6520 INTERFACE DIAGRAM
Vss
CONTROL
8·BIT
DATA BUS
8·BIT
DATA PORT
MICROPROCESSORS
SY6520
SV650X
8-B1T
PERIPHERAL
DEVICESPRINTERS,
DISPLAYS, ETC.
DATA PORT
CONTROL
CONTROL
ORDERING INFORMATION
Part Number
SYC6520/6820
SYD6520/6820
SYP6520/6820
SYC6520A/68B20
SYD6520A/68B20
SYP6520A/68B20
Package
Speed
Ceramic
lMHz
lMHz
1MHz
2MHz
2M Hz
2MHz
Cerdip
Plastic
Ceramic
Cerdip
Plastic
3-67
CA,
PAD
CA2
PA,
IROA
PA2
IROB
PA3
RSo
PA4
RS,
PA5
RES
PA6
Do
PA,
D,
PBo
D2
PB,
D3
PB2
D4
PB3
D5
PB4
D6
PB5
D,
PB6
<)2
PB,
CS,
CB,
CS2
CB2
CSo
Vee
R/W
SY6520/6520A
SY6820/68820
MAXIMUM RATINGS
Rating
Symbol
Value
Supply Voltage
Vee
-0.3 to +7.0
V
Input Voltage
Yin
-0.3 to +7.0
V
Operating
Temperature Range
TA
o to +70
°c
Storage
Temperature Range
Tstg
-55 to +150
°c
D.C. CHARACTERISTICS (Vee
This device contains circuitry to protect the inputs
against damage due to high static voltages, however,
it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated
voltages to this circuit.
Unit
= 5.0V ± 5%, Vss = 0, TA = 0-70°C unless otherwise noted)
Characteristic
Symbol
Min.
Max.
Unit
Input High Voltage
VIH
+2.0
Vee
V
Input Low Voltage
VIL
-0.3
+0.8
V
Input Leakage Current
VIN = 0 to 5.0 V
R/W. Reset; RSo. RS" CSo. CS" CS2, CAl. CB" 2
CS1
I
CB1
-------~-------
R/W
CS2
CA2
LATCH
(T1L·L)
I
I
(T1L·H)
RES
CA1
CHIP
ACCESS
I
I
I
CB2
COUNTER
(T1C·L)
TIMER 1
CONTROL
RS1
RS2
BUFFERS
(PB)
RS3
DATA OIR.
(DORB)
Figure 1. SY6522 Block Diagram
3-95
PORT B
SY6522jSY6522A
ABSOLUTE MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltage
Operating Temperature
Range
Storage Temperature
Range
Symbol
Value
Unit
Vee
VIN
-0.3 to +7.0
-0.3 to +7.0
V
V
TA
o to +70
°c
Tstg
-55 to +150
°c
ELECTRICAL CHARACTERISTICS (Vee
Symbol
This device contains circuitry to protect the inputs
against damage due to high static voltages. However,
it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated voltages.
= 5.0V ± 5%, TA = 0-70°C unless otherwise noted)
Characteristic
Min.
Max.
Unit
VIH
Input High Voltage (all except 2)
2.4
Vee
V
VeH
Clock High Voltage
2.4
Vee
V
VIL
Input Low Voltage
-0.3
0.4
V
liN
Input Leakage Current - VIN = 0 to 5 Vdc
RNV, RES, RSO, RS1, RS2, RS3, CS1, CS2,
CAl, 2
-
±2.5
pA
ITSI
Off-state Input Current - VIN = .4 to 2.4V
Vee = Max, DO to 07
-
±10
pA
IIH
Input High Current - VIH = 2.4V
PAQ-PA7, CA2, PBO-PB7, CB1, CB2
-100
-
pA
IlL
Input Low Current - VIL = 0.4 Vdc
PAO-PA7, CA2, PBO-PB7, CB1, CB2
-
-1.6
mA
VOH.
Output High Voltage
Vee = min, Iload = -100 pAdc
PAO-PA7, CA2, PBO-PB7, CB1, CB2
2.4
-
V
VOL
Output Low Voltage
Vee = min, Iload = 1.6 mAdc
-
0.4
V
IOH
Output High Current (Sourcing)
VOH = 2.4V
VOH = 1.5V (PBO-PB7)
-100
-1.0
-
pA
mA
IOL
Output Low Current (Sinking)
VOL = 0.4 Vdc
1.6
-
IOFF
Output" Leakage Current (Off state)
IRQ
-
10
pA
CIN
Input Capacitance - T A = 25°C, f = 1 MHz
(RNV, RES, RSO, RS1, RS2, RS3,CS1,CS2,
00-07, PAQ-PA7, CAl, CA2, PBO-PB7)
-
7.0
pF
-
10
20
pF
pF
10
pF
700
mW
(CB1, CB2)
(2 Input)
COUT
Output Capacitance - TA = 25°C, f = 1 MHz
PD
Power Dissipation (Vee = 5.25V)
3-96
mA
SY6511/SY6522A
Vee
Figure 2. Test Load (for all Dynamic Parameters)
<1>,
CLOCK
CHIP SELECTS,
REGISTER SELECTS,
R/W
PERIPHERAL
DATA
DATA BUS
---------H~_+O(
Figure 3. Read Timing Characteristics
READ TIMING CHARACTERISTICS (FIGURE 3)
SV6522A
SV6522
Symbol
Parameter
TCY
Cycle Time
TACR
Address Set-Up Time
TCAR
Address Hold Time
TpCR
Peripheral Data Set-Up Time
Min.
Max.
Min.
Max.
Unit
1
50
0.5
.50
f.1s
-
90
0
-
ns
300
-
ns
180
0
300
ns
TCDR
Data Bus Delay Time
-
340
-
200
ns
THR
Data Bus Hold Time
10
-
10
-
ns
NOTE: tr, tf
= 10 to
30n5.
3-97
SY6522/SY6522A
<1>,
CLOCK
CHIP SELECTS,
REGISTER SELECTS
RIW
DATA
BUS
---------------~
PERIPHERAL
DATA
Figure 4. Write Timing Characteristics
WRITE TIMING CHARACTERISTICS (FIGURE 4)
SY6522
Symbol
Parameter
SY6522A
Min.
Max.
Min.
Max.
Unit
1
50
0.50
50
/1S
¢2 Pulse Width
0.44
25
0.22
25
/1S
TACW
Address Set· UpTime
180
-
90
-
ns
0
-
0
-
ns
-
90
ns
0
-
0
300
-
200
1.0
/1S
2.0
/1s
Tcy
Cycle Time
Tc
TCAW
Address Hold Time
Twcw
R/W Set· Up Time
Tcww
R/W Hold Time
TDCW
Data Bus Set-Up Time
180
...
THW
Data Bus Hold Time
10
-
10
Tcpw
Peripheral Data Delay Time
-
1.0
-
TCMO S
Peripheral Data Delay Time
to CMOS Levels
-
2.0
-
NOTE: tr, If ~ 10 to 30ns.
3-98
.
ns
ns
ns
§V6521/§V6511A
PERIPHERAL INTERFACE CHARACTERISTICS
Symbol
Characteristic
"
Min.
Max.
Unit
Figure
-
1.0
IlS
-
tr, tf
Rise and Fall Time for CA 1, CB 1, CA2, and CB2
Input Signals
TCA2
Delay Time, Clock Negative Transition to CA2 Negative
Transition (read handshake or pulse mode)
-
1.0
Ils
5a,5b
T RS1
Delay Time, Clock Negative Transition to CA2 Positive
Transition (pulse mode)
-
1.0
Il s
5a
TRS2
Delay Time, CAl Active Transition to CA2 Positive
Transition (handshake mode)
-
2.0
IlS
5b
TWHS
Delay Time, Clock Positive Transition to CA2 or CB2
Negative Transition (write handshake)
0.05
1.0
Ils
5c,5d
TDS
Delay Time, Peripheral Data Valid to CB2 Negative
Transition
0.20
1.5
IlS
5c,5d
TRS3
Delay Time, Clock Positive Transition to CA2 or CB2
Positive Transition (pulse mode)
-
1.0
IlS
5c
T RS4
Delay Time, CA 1 or CBl Active Transition to CA2 or
CB2 Positive Transition (handshake mode)
-
2.0
Il s
5d
T21
Delay Time Required from CA2 Output to CAl
Active Transition (handshake mode)
400
-
ns
5d
TIL
Set·up Time, Peripheral Data Valid to CA 1 or CBl
Active Transition (inpuflatching)
300
-
ns
5e
TSR1
Shift·Out Delay Time - Time from ifJ2 Falling Edge
to CB2 Data Out
-
300
ns
5f
TSR2
Shift-In Setup Time,- Time from CB2 Data In to
ifJ2 Rising Edge
300
-
ns
5g
TSR3
External Shift Clock (CB 1) Setup Time Relative To
ifJ2 Trailing Edge
100
Tcy
ns
5g
Width~
PB6 Input Pulse
2x TCY
-
5i
2 x Tcy
-
5h
2 x TCY
-
5i
2 x Tcy
-
5h
TIPW
Pulse
TICW
Pulse Width - CBl Input Clock
TIPS
Pulse Spacing - PB6 Input Pulse
TICS
Pulse Spacing - CBl Input Pulse
TAL
CAl, CBl
Set Up Prior to Transition to Arm Latch
3)0
-
ns
5e
TpDH
Peripheral Data Hold After CAl, CBl Transition
150
-
ns
5e
3-99
SY6522/SY6522A
READ IRA
OPERATION
CA2
"DATA TAKEN"
Figure 5a. CA2 Timing for Read Handshake, Pulse Mode
.................
..'.....
; - - - \ . . .
;.J
..
.•.. . "-----
READ IRA
OPERATION
/
CA2.
.
"DATA TAKEN"
CAt'
"DATA READY"
======:=:>tTf
L'ACTIVE
TRANSITION
Figure 5b. CA2 Timing for Read Handshake, HandshakeMode
WRITE ORA, ORB
OPERATION
CA2, CB2
"DATA READY"
PA, PB
PERIPHERAL
DATA
Figure 5c. CA2, CB2 Timing for Write Handshake, Pulse Mode
3-100
SY6511/SY6511A
WRITE ORA, ORB
OPERATION
CA2, CB2
"DATA READY"
PA, PB
PERIPHERAL
DATA
CA1,CB1
"DATA TAKEN"
ACTIVE
TRANSITION
Figure 5d. CA2, CB2 Timing for Write Handshake, Handshake Mode
PA,PB
PERIPHERAL
INPUT DATA
CA1,CB1
INPUT LATCHING
CONTROL
~-------~L--------~
ACTIVE
TRANSITION
Figure 5e. Peripheral Data Input Latching Timing
CB2
SHIFT DATA
(OUTPUT)
CB1
SHIFT CLOCK
ClNPUTOR
OUTPUT}
DELAY TIME MEASURED FROM THE FIRST ,
FALLING EDGE AFTER CB1 FALLING EDGE,
Figure 5f. Timing for Shift Out with Internal or External Shift Clocking
3-101
SY6522/SY6522A
CB2
SHIFT DATA
(INPUT)
CBI
SHIFTCLDCK
(INPUT DR
OUTPUT)
SETUP TIME MEASURED TO THE FIRST "',
RISING EDGE AFTER CBI RISING EDGE.
Figure 5g. Timing for Shift In with Internal or External Shift Clocking
CBI
SHIFT CLOCK
INPUT
Figure 5h. External Shift Clock Timing
PB6
PULSE COUNT
INPUT
1
rl
T,pw
Figure 5i. Pulse Count Input Timing
3-102
-TIPS
t
,
SY6522/SY6522A
PIN DESCRIPTIONS
DBa-DB7 (Data Bus)
RES (Reset)
The eight bi-directional data bus lines are used to
transfer data between the SY6522 and the system
processor, During read cycles, the contents of the selected SY6522 register are placed on the data bus lines
and transferred into the processor. During write
cycles, these lines are high-impedance inputs and data
is transferred from the processor into the selected register. When the SY6522 is unselected, the data bus
lines are high-impedance.
The reset input clears all internal registers to logic 0
(except T1 and 12 latches and counters and the Shift
Register). This places all peripheral interface lines in
the input state, disables the timers, shift register, etc.
and disables interrupting from the chip.
2 (Input Clock)
The input clock is the system 2 clock and is used to
trigger all data transfers between the system processor
and the SY6522.
CS1, CS2 (Chip Selects)
The two chip select inputs are normally connected to
processor address lines either directly or through decoding. The selected SY6522 register will be accessed
when CS1 is high and CS2 is low.
Riw (ReadlWrite)
The direction of the data transfers between the
SY6522 and the system processor is controlled by the
R/W line. If R(W is low, data will be transferred out
of the processor into the selected SY6522 register
(write operation). If R!Wishigh and the chip is selected, data will be transferred out of the SY6522 (read
operation).
RS Coding
RS2
RS1
RSa- RS3 (Register Selects)
The four Register Select inputs permit the system processor to select one of the 16 internal registers of the
SY6522, as shown in Figure 6.
Description
RSO
Register
Desig.
0
0
ORB/IRB
Output Register "B"
Input Register "B"
0
0
1
ORA/IRA
Output Register" A"
Input Register "A"
Data Direction Register "B"
Register
Number
RS3
0
0
0
1
0
Read
Write
2
0
0
1
0
DDRB
3
0
0
1
1
DDRA
Data Direction Register "A"
4
0
1
0
0
T1C-L
T1 Low·Order Latches
5
0
1
0
1
T1C-H
T1 High·Order Counter
6
0
1
1
0
T1L-L
T1 Low-Order Latches
7
0
1
1
1
T1L-H
T1 High-Order Latches
8
1
0
0
0
T2C-L
T2 Low-Order Latches
9
1
0
0
1
T2C-H
T2 High-Order Counter
10
1
0
1
0
SR
Shift Register
11
1
0
1
1
ACR
Auxil iary Control Register
12
1
1
0
0
PCR
Peripheral Control Register
13
1
1
0
1
IFR
Interrupt Flag Register
T1 Low-Order Counter
T2 Low-Order Counter
14
1
1
1
0
IER
Interrupt Enable Register
15
1
1
1
1
ORA/IRA
Same as Reg 1 Except No "Handshake"
Figure 6. SY6522 Internal Register Summary
3-103
SY6522jSY6522A
TRCi (Interrupt Request)
PA port. In addition, the PBl output signal can be
controlled by one of the interval timers while the
second timer can be programmed to count pulses
on the PB6 pin. Peripheral B lines represent one
standard TTL load in the input mode and will drive
one standard TTL load in the output mode. In addition, they are capable of sourcing 1.DmAat 1.5VDC
in the output mode to allow the outputs to directly
drive Darlington transistor circuits. Figure 8 is the
circuit schematic.
The Interrupt Request output goes low whenever an
internal interrupt flag is set and the corresponding interrupt enable bit is a logic 1. Th is output is "opendrain" to allow the interrupt request signal to be
"wire-or'ed" with other equivalent signals in the
system_
PAD-PAl (Peripheral A Port)
The Peripheral A port consists of 8 lines which can
be individually programmed to act as inputs or outputs under control of a Data Direction Register_ The
polarity of output pins is controlled by an Output
Register and input data may be latched into an internal register under control of the CA 1 line_ All of
these modes of operation are controlled by the system processor through the internal control registers_
These lines represent one standard TTL load in the
input mode and will drive .one standard TTL load in
the output mode_ Figure 1 illustrates the output
circuit_
CB1, CB2 (Peripheral B Control Lines)
The Peripheral B control lines act as interrupt inputs
or as handshake outputs. As with CA 1 and CA2, each
line controls an interrupt f~ag with a corresponding interrupt enable bit. In addition, these lines act as a
serial port under control of the Shift Register. These
lines represent one standard TTL load in the input
mode and will drive. one standard. TTL load in the
output mode. Unlike PBD-PBl, CB1 and CB2 cannot
drive Darl ington transistor circuits.
CA 1, CA2 (Peripheral A Control Lines)
The two Peripheral A control lines act as interrupt inputs or as handshake outputs_ Each line controls an
internal interrupt flag With a corresponding interrupt
enable bit_ In addition, CA 1 controls the latching of
data on Peripheral A port input lines. CA 1 is a highimpedance input only whileCA2 represents one standard TTL load in the input mode. CA2 will drive one
standard TTL load in the output mode.
+5V
INPUTI
OUTPUT - - -_ _
~
CONTROL
+5V
INPUT DATA
Figure 8. Peripheral B Port Output Circuit
PAO-PA7,
CA2
FUNCTIONAL DESCRIPTION
I
I/OCQNTRQL
~
Port A and Port B Operation
OUTPUTDATA~
Each 8-bit peripheral port has a Data Direction Register (DDRA,DDRB) for specifying whether the peripheral pins are to act as inputs or outputs. A 0 in a
bit of the Data Direction Register causes the corresponding peripheral pin to act as an input. A 1 causes
the pin to act as an output.
I
--------1
INPUT DATA __
Figure 7. Peripheral A Port Output Circuit
PBD-PBl (peripheral B Port)
The Peripheral B port consists of eight bi-directional
lines which are controlled by an output register and a
data dirjlction register in much the same manner as the
When programmed as an output each peripheral pin
is also controlled by a correspond ing bit in the Output Register (ORA, ORB). A 1 in the Output Register causes the output to go high, and a "0" causes the
output to go low. Data may be written into Output
Register bits corresponding to pins which are pro-
3-104
SY6511/SY6522A
grammed as inputs. In this case, however, the output
signal is unaffected.
REG 1 - ORA/IRA
171.6151413121'101
Reading a peripheral port causes the contents of the
Input Register (I RA, I RB) to be transferred onto the
Data Bus. With input latching disabled, IRA will always
reflect the levels on the PA pins. With input latching
enabled. and the selected active transition on CAl
having occurred, I RA will contain the data present
on the PA lines at the time of the transition. Once
I RA is read, however, it will appear transparent, refleeting the current state of the PA lines until the
next "latching" transition.
IL
PAO
PA'
PA2
OUTPUT REGISTER "A" (ORA)
PA'3
OR
PA4
PAS
PA6
PA7
Pin
Data Direction
INPUT REGISTER "A" (IRA)
WRITE
READ
Selection
The IRB register operates similar to the IRA register.
However, for pins programmed as outputs there is a
difference. When reading I RA, the level on the pin
determines whether a a or a 1 is sensed. When reading
I RB, however, the bit stored in the output register,
ORB, is the bit sensed. Thus, for outputs which have
large loading effects and which pull an output "1"
down or which pull an output "0" up, reading IRA
may result in reading a "0" when a "1" was actually
programmed, and reading a "1" when a "0" was programmed. Reading I RB, on the other hand, will read
the "1" or "0" level actually programmed, no matter
what the loading on the pin.
Figures 9,10, and 11 illustrate the formats of the port
registers. In addition, the input latching modes. are
selected by the Auxiliary Control Register (Figure
16.)
DORA" "'" (OUTPUT)
(Input latching disabled)
DORA = "1" (OUTPUT)
(Input latching'enabled)
DORA ~ "O"'(lNPUT)
(Input latching disabled)
DORA = "0" (INPUT)
(Input latching enabled)
MPU writes Output Level
(ORA).
MPU reads level on PA pin.
MPU reads' IRA bit which is
the level of the PA pin at the
time of the last,CAl active
transition.
MPU wrihls into ORA, but MPU reads level on ~A pin.
no effect on pin level, until
DORA changed.
MPU reads IRA bit which is
the level of the PA pin at the
time of the last CA 1 active
transition.'
Figure 10. Output Register A (ORA),
Input Register A (I RA)
REG:2 (DDRSI AND REG 3 (DDRAI
1+1+1+1+1
~-"
PB1/PAl
.
:.
.'
I
Handshake Control of Data Transfers
PB2/PA2
PB3/PA3
PB4/PA4
DATA DIRECTION REGISTER'
"S" OR "A" (DDRB/DDRA)
PB5/PA5
The SY6522 allows positive control of data transfers
between the system processor and peripheral devices
PBG/PAG
PB7/PA7
"0" ASSOCIATED PB/PA PIN IS AN
(HIGH·IMPEDANCE)
REG 0 - DRS/IRS
"1"
1716151413121'101
lL
Pin
Data Direction
Selection
DDRB
= "'" (OUTPUT)
DDRB = "0" (INPUT)
(Input_latching disabled)
DDRB = "O~' (INPUT)
(Input latching enabled)
INP~T
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
WRITE
ASSOCIATED PB/PA PIN IS AN OUTPUT,
WHOSE LEVEL IS DETERMINED BY
ORB/ORA REGISTER BIT.
Figure 11. Data Direction Registers (DDRB, DDRA)
OUTPUT REGISTER "B" (ORB)
OR
INPUT REGISTER "B".(ORB)
through the operation of "handshake" lines. Port A
lines (CAl, CA2) handshake data on both a read and
a write operation while the Port B lines (CB1, CB2)
handshake on a write operation only.
Read Handshake
READ
MPU writes Output Level
(ORB)
MPU reads output register bit
in ORB. Pin level has no affect.
MPU writes int~ ORB, but MPU reads input level on PB
no effect on pin level, until pin.
DDRB changed.
MPU reads I RB bit, which is
the le,vel of the PB pin at the
time of the last CBl active.
transition.
_.
Figure 9. Output Register B (ORB),
Input Register B (lRB)
3-105
Positive c~ntrol of data transfers from peripheral devices into the system processor can be accomplished
very effectively using Read Handshaking. In this case,
the peripheral device must generate the equivalent of
a "Data Ready" signal tothe processor signifying that
valid data is present on the peripheral port. This signal
normally interrupts the processor, which then reads
the data, causing generation of a "Data Taken" signal.
The peripheral device responds by making new data
avallable. This process continues until the data transfer is complete.
SY6511/SY6522A
;g:,~A
"'2~~,dL..FLJL
READY
f///Z///Z//ZZZ/J
III
IRQ O U T P U T .
READ IRA OPERATION _ _
I I
!f-----
•
1
----,----~---1
•.. '
~
I,
"DATA TAKEN"
I ,"
_
.
HANDSHAKE MODE
(CA2)
~~~i: J~~:N"
(CA2}
-...,------------------'--.....L-.....J'.
Figure 12. Read Handshake Timing (Port A, Only)
,"'2~~~
r~~~;;~:::
~~~;::~~~Y"
==
----" ~ .
·'1'
-------..LJ
I
;g:,~~;,rEN
"
.
r l i
V///00ZWA
I
IRQ OUTPUT
rL
II
~
Figure 13. Write Handshake Timing
Timer Operation
In the SY6522, automatic "Read" Handshaking is
possible on the Peripheral A port only. The CA lin·
terrupt input pin accepts the "Data Ready" signal
and CA2 generates the "Data Taken" signal. The
"Data Ready" signal will set an internal flag which
may interrupt the processor or which may be polled
under program control. The "Data Taken" signal can
either be a pulse or a level which is set low by the system processor and is cleared by the "Data Ready"
signal. These options are shown in Figure 12 which
illustrates the normal Read Handshaking sequence.
Interval Timer Tl consists of two 8-bit latches and a
16-bit counter. The latches are used to store data
which is to be loaded into the counter. After loadin'g,
the counter decrements at tjJ2 clock rate. Upon reaching zero, an interrupt flag will be ~et, and IRQ will go
low if the interrupt is enabled. The timer will then
disable any further interrupts, or'(when programmed
to) will automatically transfer the contents of the
latches into the counter and begin, to decrement
again. In addition, the timer may be programmed to
invert the output signal on a perif)heral pin each time
it "times-out", Each of these modes is discussed separately below.
Write Handshake
The seque~ce of operations; wh ich allows handshaking
data from.the system processor to a peripheral device
is very similar to that describedfor Read Handshaking.
However, for Write .Handshaking, the SY6522 generates the "Data Ready" signal and the peripheral device must respond with the "Data Taken" signal. This
can be accomplished on both the PA port, and the
PB port on the SY6522. CA2 or CB2 act as a"Data
Ready" output in either the handshake mode or pulse
mode and CA 1 or CBl accept the "Data Taken" signal from the peripheral device, setting the ',interrupt
flag and cleaning the "Data Ready" output:This
sequence is shown in Figure 13. "
::
-,)
Selection of operating modes for CAl, CA2, CB1,
and CB2 .is accomplished by the Peripheral Control,
Register(Figur~ 14.).
"
The Tl counter is depicfed in Figure 15 and the
latches in Figure 16.
REG 12 - PERIPHERAL CONTROL REGISTER
CB2 CONTROL
~
7 6 5 OPERATION
0 0 INPUT·NEGATIVE ACTIVE EDGE
o 0 1 INDEPENDENT INTERRUPT
INPUT-NEG EDGE
o 1 0 INPUT·POSITIVE ACTIVE EDGE
1 ,. INDEPENDENT INTERRUPT
INPUT-PQS EDGE
1 0 0 HANDSHAKE OUTPUT
o
o
1 0
1 PULSE OUTPUT
1 1 0 LOW OUTPUT
1 1 " HIGH OUTPUT
CBllNTERRUPTCONTROL
o·", NEGATIVE ACTIVE EDGE I
1 1 = POSITIVE ACTIVE EDGE J
3 2 1 OPERATION'
0 0 INPUT·NEGATIVE ACTIVE EDGE
0 1 INDEPENDENT INTERRUPT
INPUT·NEG EDGE
o 1 0 INPUT·POSITIVE ACTIVE EDGE
o 1 1 INDEPENDENT INTERRUPT
INPUT-POS EDGE
, 0 0 HANDSHAKE OUTPUT
1 0 1 PULSE OUTPUT
1 1 0 LOW OUTPUT
1 1 1 HIGH OUTPUT
o
o
*SEE NOTE ACCOMPANYING FIGURE 25.
Figure 14. CAl, CA2,GB1,CB2 Control
3 ... 106
§Y6S11/SY6511A
Two bits are provided in the Auxiliary Control Reg-
ating modes. The four possible modes are depicted
ister (bits 6 and 7). to allow selection of the T1 oper-
in Figure 17.
REG 5 - TIMER 1 HIGH-ORDER COUNTER
REG 4 - TIMER 1 LOW-ORDER COUNTER
1+1+lr(~:
7
+1 1 1' 1 1
6
3
~"C'W"
::
2
0
~~:
1024
2048
COUNT
VALUE
VALUE
4096
8192
64
163B4
12B
32768
-WAITE - 8 BITS LOADED INTO T1 LOW-ORDER
LATCHES. LATCH CONTENTS ARE
TRANSFERRED INTO LOW-ORDER
COUNTER AT THE TIME THE HIGH·
ORDER COUNTER IS LOADED (REG 5).
READ - 8 BITS FROM T1 LOW-ORDER COUNTER
TRANSFERRED TO MPU, IN ADDITION,
T1 INTERRUPT FLAG IS RESET (BIT 6
WRITE - 8 BITS LOADED INTO T1 HIGH·ORDER
LATCHES. ALSO, AT THIS TIME BOTH
HIGH AND LOW·ORDER LATCHES
TRANSFERRED INTO T1 COUNTER,
AND INITIATES COUNTDOWN. T1
INTERRUPT FLAG ALSO IS RESET.
READ""': 8 BITS FROM T1 HIGH·ORDER COUNTER
TRANSFERRED TO MPU,
IN INTERRUPT FLAG REGISTER).
15. Tl Counter Registers
Figure
REG 6 - TIMER 1 LOW-ORDER LATCHES
REG 7 - TIMER 1 HIGH-ORDER LATCHES
1+1+1+1,101
1+1+1+1+1
~i.
I~;~
~'""
204B
COUNT
VALUE
4096
32
COUNT
VALUE
B192
64
16384
'2B
32768
WRITE - 8 BlTS LOADED INTO T1 HIGH-ORDER
LATCHES. UNLIKE REG 4 OPERATION
NO LATCH-TO-COUNTER TRANSFERS
TAKE PLACE.
READ - 8 BITS FROM T1 HIGH-ORDER LATCHES
TRANSFERRED TO MPU.
WRITE - 8 BITS LOADED INTO T1 LOW-ORDER
LATCHES. THIS OPERATION IS NO
DIFFERENT THAT A WRITE INTO
REG4.
READ - 8 BITS FROM T1 LOW-ORDER LATCHES
TRANSFERRED TO MPU. UNLIKE REG 4
OPERATION, THIS DOES NOT CAUSE
RESET OF T1 INTERRUPT FLAG.
Figure
16. T1 .Latch Registers
REG 1.1 - AUXILIARY CONTROL REGISTER
E . ."
11161+13121'10
'
T1 TIMER CONTROL
1 6 OPERATION
o 0 TIMED INTERRUPT
EACH TIME T1 IS '
LOADED
o
I
'
PB
~""'"
0 '" DISABLE ~"
1
d
' '" ENABLE LATCHING
DISABLED
1 CONTINUOUS
INTERRUPTS
0 TIMED INTERRUPT
EACH TIME T1 IS
LOADED
CONTINUOUS
INTERRUPTS
,
PB1
,,
ONE·SHOT
OUTPUT
SHIFT REGISTER CONTROL
4 3 2 OPERATION
0 0 DISABLED
0 o , SHIFT IN UNDER CONTROL'OF T2
0 , 0 SHIFT IN UNDER CONTROL OF 02
SHIFT IN UNDER CONTROL OF EXT.CLK
0
o 0 SHIFT OUT FREE· RUNNING AT T2 RATE
1 0
SHIFT OUT UNDER CONTROL OF T2
1 1 0 SHIFT OUT UNDER CONTROL OF 02
SQUARE
WAVE
OUTPUT
o
,",
T2 TIMER CONTROL
5 OPERATION
TIMED INTERRUPT
o
1 COUNT DOWN WITH
PULSES ON PB6
I
,,,
Figure
SHIFT OUT UNDER CONTROL OF EXT. CLK.
17. Auxiliary Control Register
Note: The processor does not write directly into the low order counter (T1C-L). Instead, this half ofthecounter is loaded auto'
matically from the low order latch when the processor writes into the high order counter. In fact, it may not be necessary'·to·
write to the low order counter in some applications since the timing operation is triggered by writing to the high order counter.
3,..107
SY6522/SY6522A
<1>2
WRITE T1C-H
OPERATION
W
----J
1f---'------------:}rJjl..'______-+_~~_________
/I
II
IRQ OUTPUT
PB7 ONLY)
OUTPUT
IT1.
I
-------;1
-1'/-_ _ _....,.....,_...
;'/
L.. _ _ _....,. _ _ _ _ _ _ _ _
T1 COUNT
N
T2 COUNT
N,
N-1
I
N-1
I
J
N-2
N-3
N-2
N-3
I'
N + 1,5 CYCLES
FFFF
N
N-1
N-2
FFFF
FFFE
FFFO
FFFC
.1
Figure 18. Timer 1 and Timer 2 One-Shot Mode Timing
Timer 1 One-Shot Mode
The interval timer one·shot mode, allows generation
of a single interrupt for each Timer load operation.
In addition, Timer 1 can be programmed to produce
a single negative pulse on PB7.
To generate a single interrupt ACR bits 6 and 7 must
be 0 then either TI L-L or TIC-L must be written with
the low-order count value. (A write to TIC-Lis effectively a Write to II L-U. Next the high-order count
value is written to TIC-H, (the value is simultaneously written into TIL-H), and TIL-L is transferred
to TIC-L Countdown begins on the 2 rate. Figure 20 illustrates the T2 Counter Registers.
As an interval timer, T2 operates in the "one-shot"
mode similar to Timer 1. In this mode, T2 provides a
single interrupt for each "write T2C-H" operation.
After timing out, (reading 0) the counters "roll-over"
to all 1 's (FFFF 16 ) and continue decrementing, allowing the user to read them and determine how long
T2 interrupt has been set. However, setting of the
interrupt flag will be disabled after initial time-out
so that it will not be set by the counter continuing to
decrement through zero. The processor must rewrite
T2C-H to enable setting of the interrupt flag. The
interrupt flag is cleared by reading T2C-L or by
writing T2C-H. Timing for this operation is shown in
Figure 18.
REG 8 - TIMER 2 LOW-ORDER COUNTER
REG 9 - TIMER 2 HIGH-ORDER COUNTER
1716151413121'101
~~
l:==2048
COUNT
VALUE
'------16
L-_ _ _ _ _
L-_ _ _ _ _ _
COUNT
VALUE
4096
32
64
L - - - - - - - 8'92
' - - - - - - - - 16384
L--------128
WAITE -
8 BITS LOADED INTO T2 LOW-ORDER
LATCHES.
READ -
8 BITS FROM T2 LOW-ORDER COUNTER
TRANSFERRED TO MPU. T2 INTERRUPT
FLAG IS RESET.
'---------32768
WRITE -
8 BITS lOADED INTO T2 HIGH-ORDER
COUNTER. ALSO, LOW-ORDER LATCHES
TRANSFERRED TO LOW·ORDER
COUNTER. IN ADDITION, T2 INTERRUPT
FLAG IS RESET.
READ -
8 BITS FROM T2 HIGH·ORDER COUNTER
TRANSFERRED TO MPU.
Figure 20. T2 Counter Registers
3-109
SY6522/SY6522A
Timer 2 Pulse Counting Mode
Interrupt Operation
In the pulse counting mode, T2 serves primarily to
count a predetermined number of negative-going
pulses on PB6. This is accomplished by first loading
a number into T2. Writing into T2C-H clears the interrupt flag and allows the counter to decrement each
time a pulse is applied to PB6. The interrupt flag will
be set when T2 reaches zero. At th is time the cou nter
will continue to decrement with each pulse on PB6.
However, it is necessary to rewrite T2C-H to allow
the interrupt flag to set on subsequent down-counting
operations. Timing for this mode is shown in Figure
21. The pulse must be low on the leading edge of <1>2.
Controlling interrupts within the SY6522 involves
three principal operations. These are flagging the interrupts, enabling interrupts and signaling to the processor that an active interrupt exists within the chip.
Interrupt flags are set by interrupting conditions
which exist within the chip or on inputs to the chip.
These flags normally remain set until the interrupt
has been serviced. To determine the source of an interrupt, the microprocessor must examine these flags
in order from highest to lowest priority. This is accomplished by reading the flag register into the processor accumulator, shifting this register either right
or left and then using conditional branch instructions.
to detect an active interrupt.
Shift Register Operation
Associated with each interrupt flag is an interrupt
enable bit. This can be set or cleared by the proces·
sor to enable interrupting the processor from the corresponding interrupt flag. If an interrupt flag is set to
a logic 1 by an interrupting condition, and the corresponding interrupt enable bit is set to a 1. the Interrupt Request Output (I RO) will go low. I RO is an
"open-collector" output which can be "wire~or'ed"
with other devices in the system to interr!Jpt the
processor.
The Shift Register (SR) performs serial data transfers
into and out of the CB2 pin under control of an internal modul0-8 counter. Shift pulses can be applied
to the CB1 pin from an external source or, with the
proper mode selection, shift pulses generated internally will appear on the CB1 pin for controlling external devices.
The control bits which select the various shift register
operating modes are located in the Auxiliary Control
Register. Figure 22 illustrates the configuration of the
SR data bits and the SR control bits of the AeR.
In the SY6522, all the interrupt flags are contained
in one register. In addition, bit 7 of this register will
be read as a logic 1 when an interrupt exists within
the chip. This allows very convenient polling of several devices with in a system to locate the sou rce of
an interrupt.
Figures 23 and 24 illustrate the operation of the various sh ift register modes.
WRITE
T2C-H
OPERATION
----Ir---,11......_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
u
PB61NPUT
//
U
u
U
IRQ OUTPUT
N·'
I
II
N·2
Figure 21. Timer 2 Pulse Counting Mode
REG 10 - SHIFT REGISTER
REG 11 - AUXILIARY CONTROL REGISTER
1+1+1+1+1
J.J..1
L
. SHIFT
REGISTER
BITS
SHIFT REGISTER
MODE CONTROL
4
0
0
0
0
2
,
,, ,
0
0
,
, ,
,,
NOTES:
0
0
1. WHEN SHIFTING OUT. BIT 7 IS THE FIRST BIT
OUT AND SIMUL TANEOUSLY IS ROTATED BACK
INTOBITO.
2.
3
0
0
0
0
~I~EON;~6F:~~~lftF~~T~ +~~1~~'sYB~~~~R
1
1
1
OPERATION
DISABLED
SHIFT IN UNDER CONTROL OF T2
SHIFT IN UNDER CONTROL OF <"2
SHIFT IN UNDER CONTROL OF EXTCLK
SHIFT OUT FREE·RUNNING AT T2 RATE
SHIFT OUT UNDER CONTROL OF T2
SHIFT OUT UNDER CONTROL OF (1'2
SHIFT OUT UNDER CONTROL OF EXT elK
Figure 22. SR and ACR Control Bits
3-110
SY6512/SY6522A
SR Disabled (000)
The 000 mode is used to disable the Shift Register. In this mode the microprocessor can write or read the SR, but the
shifting operation is disabled and operation of CBl and CB2 is controlled by the appropriate bits in the Peripheral
Control Register '(PCR). In this mode the SR Interrupt Flag is disabled (held to a logic 0).
Shift in Under Control of T2 (001)
In the 001 mode the shifting rate is controlled by the low order 8 bits of T2. Shift pulses are generated on the CBl pin
to control shifting in external devices, The time between transitions of this output clock is a function of the system
clock period and the contents of the low order T2 latch (N).
The shifting operation is triggered by writing or reading the shift register. Data is shifted first into the low order bit
of SR and is then shifted into the next higher order bit of the shift register on the negative'going edge of each clock
pulse. The input data should change before the positive-going edge of the CBl clock pulse. This data is shifted into
the shift register during the 2 (110)
In mode 110, the shift rate is controlled by the <1>2 system clock.
<1>2
CLOCK
WRITE SR
OPERATION
I
I
,.....-,
-------I
--+--+--+-+-+--f---f----l---+---I--t----l------
I....
CB10UTPUT
SHIFT CLOCK
CB2 OUTPUT
DATA
Shift Out.Under Control of External CBl Clock (111)
In mode 111 shifting is controlled by pulses applied to the CBl pin by an external device. The SR counter sets the SR
Interrupt flag each time it counts 8 pulses but it does not disable the shifting function. Each time the microprocessor
writes or reads the shift register, the SR Interrupt flag is reset and the SR counter is initialized to begin counting the
next 8 shift pulses on pin CB1. After 8 shift pulses, the interrupt flag is set. The microprocessor can then load the
shift register with the next byte of data.
Figure 24. Shift Register Output Modes
3-112
SY6522/SY6522A
The Interrupt Flag Register (lFR) and Interrupt En·
able Register (I ER) are depicted in Figures 25 and
26, respectively.
The IF R may be read directly by the processor. In ad·
dition, individual flag bits may be cleared by writing
a "1" into the appropriate bit of the IF R. When the
proper chip select and register signals are applied to
the chip, the contents of this register are placed on
the data bus. Bit 7 indicates the status of the I RQ out·
put. This bit corresponds to the logic function: IRQ =
IFR6x IER6+IFR5x IER5+IFR4x IER4+ IFR3x
IER3 + IFR2 x IER2 + IFR1 x IER1 + IFRO x IERO.
Note: X = logic AND, + = Logic OR.
The IFR bit 7 is riot a flag. Therefore, this bit is not
directly cleared by writing a logic 1 into it. It can
only be cleared by clearing all the flags in the register
or by disabling all the active interrupts as discussed
in the next section.
by writing to address 1110 (I E R address). If bit 7 of
the data placed on the system data bus during this
write operation is a 0, each 1 in bits 6 through 0
clears the corresponding bit in the Interrupt Enable
Register. For each zero in bits 6 through 0, the cor·
responding bit is unaffected.
Setting selected bits in the Interrupt Enable Register
is accomplished by writing to the same address with
bit 7 in the data word set to a logic 1. In this case,
each 1 in bits 6 through 0 will set the corresponding
bit. For each zero, the corresponding bit will be un·
affected. This individual control of the setting and
clearing operations allows very convenient control of
the interrupts duringsystem operation.
In addition to setting and clearing IER bits, the pro·
cessor can read the contents of this register by placing
the proper address on the register select and chip
be
select inputs with the R/W line high., B,it }
read as a logic 1.
will
REG 13.- INTERRUPT FLAG REGISTER
REG 14 - INTERRUPT ENABLE REGISTER
171SIsH312111 0 1
I
LCA2 CA2
A;~~V:YEDGE
11s1sI+H+1
CLEARED BY
7
READ OR WRITE
REG 1 (ORAl'
~~"'~
lCA1_ CAt ACTIVE EDGE
SHIFT REG COMPLETE 8 SHIFTS
READ OR WRITE
SHIFT REG
C B 2 - CB2 ACTIVE EDGE
CBl
CSl ACTIVE EDGE
TIME-OUT OF T2
TIMER 2
READ OR WRITE ORB*
READ OR WRITE ORB
READ T2 LOW OR
WRITE T2 HIGH
0= INTERRUPT DISABLED
1'" INTERRUPT ENABLED
TIMER 2
L--------TIMER 1
* IF THE CA2/CB2 CONTROL IN THE peR IS SELECTED AS
"INDEPENDENT" INTERRUPT INPUT, THEN READING OR
WRITING THE OUTPUT REGISTER ORA/ORB WILL NOT
BE
CLEAR THE FLAG BIT. INSTEAD. THE BIT MUST
CLEARED BY WRITING INTO THE IFR, AS DESCRIBED
PREVIQUSL Y.
Figure 25. Interrupt Flag Register (I FR)
L---------SET/CLEAR
NOTES:
1.IF BIT7ISA"O". THEN EACH "1" IN BITSO-S DISABLES THE
CORRESPONDING INTERRUPT.
2. IF BIT 7 IS A "1", THEN EACH "'" IN BITS 0 - 6 ENABLES THE
CORRESPONDING INTERRUPT.
3_IF A READ OF THIS REGISTER IS DONE. BIT 7 WILL BE "1" AND
ALL OTHER BITS WILL REFLECT THEIR ENABLE/DISABLE STATE.
Figure 26. Interrupt Enable Register (lER)
For each interrupt flag in IFR, there is a corres·
ponding bit in the Interrupt Enable Register. The
system processor can set or clear selected bits in
this register to facilitate controlling individual inter·
rupts without affecting others. This is accomplished
3-113
SY6522/SY6522A
PACKAGE OUTLINE
ORDERING INFORMATION
10,,·'max.
,
I
40
\
DO
'" DOT O. R NOTCH
I
1
TO LOCATE
I
20
600m:-[I.!s"7J
(1524mm)
(1511)
I~~
t
, - - 2,020 max. - -
15130 mmJ
1
r'
Type
Option
~
Plastic
Plastic
1 MHz
--L
SYC 6522
SYC 6522A
595
190 rna
82
m~J
1r!~l~T~t= ';f:':'
~
-.
--f1Q1"I 040 TVP
-.;:.
-~: ~~ri
(;~~ :'~)
1.890 (48.00 mm)
Ceramic
Ceramic
2 MHz
1 MHz
2 MHz
PIN CONFIGURATION
VSS
CAl
PAO
CA2
PAl
RSO
. PAZ
RSl
PA3
RS2
PM
RS3
PAS
RES
PAB
DO
PA7
01
.PBO
02
PBl
03
PB2
0'
PB3
05
PB'
DB
010 min.
PBS
07
(.25 mm)
PBB
'1'2
TVP
1.910 (48.51 mm)
2
ITSI
Clock Frequency
';·5.0V ± 5%, TA = -40°C to +85°C unless otherwise noted)
VIH
"
Package
Off-state Input Cu~reni: - VIN = .4 to 2.4V
Vee =Max,DOt~ 07
..
"
.
..
,
IIH
Input High Current - VIH= 2.4V
PAO-PA7, CA2, PBO-PB7, CB1, CB2
-100
-
J.l.A
III
Input Low Curre~t - Vll= 0.4 Vdc
PAO-PA7, CA2, PBO-PB7. CB1. CB2
-
-1.6
mA
VOH
Output High Voltage
Vee = min, Iload = -100 J.l.Adc
PAO-PA7. CA2. PBO-PBl. CB1. CB2
2.4
-
V
VOL
Output Low Voltage
Vee = min, lload = 1.6 mAde
-
0.4
V
IOH
Output High Current (Sourcing)
VOH = 2.4V
VOH = 1.5V (PBQ-PB7)
IOl
Olltput Low Current (Sinking)
VOL = 0.4 Vdc
IOFF
Output Leakage Current (Off state)
,
IRQ
CIN
:
'
Input Capacitance - TA = 25°C. f= 1 MHz
(R/W. RES. RSO. RS1. RS2. RS3. CS1. CS2.
00-07. PAO-PA7; CA1,CA2, PBO-PB7)
(CB1,CB2)
(<1>2 Input)
,.
I
A
.
'
.
-
-100
-1.0
'-
J.l.A
"mA
1.6
-
mA
-,
lQ
J.l.A
-
7:0
pF
-
10
20
pF
pF
..
COUT
Output Capacitance ~ ;- = 25°C. f = 1 MHz
-
10
Po
Power Dissipation . Vee'" 5.25V
-
750
i
.,
pF
mW
"
SY6530
MICROPROCESSOR
PRODUCTS
A SUBSIDIARY OF HONEYWELL
•
8 bit bi-directional Data Bus for direct communication
with the microprocessor
o 1024x8ROM
o 64 x 8 static RAM
• Two 8 bit bi-directional data ports for interface to
peripherals
o Two programmable 1/0 Peripheral Data Direction
Registers
o Programmable Interval Timer
Programmable Interval Timer Interrupt
I) TTL & CMOS compatible peripheral lines
o Peripheral pins with Direct Transistor Drive Capability
o High Impedance Three-State Data Pins
• Allows up to 7K contiguous bytes of ROM with no
external decoding
I)
The SY6530 isdesignedtooperate inconjunction with
theSY6500 microprocessor Family.lt iscomprised ofa
mask programmable 1024 x 8 ROM, a 64 x 8 static
RAM, two software controlled 8 bit bi-directional data
ports allowing direct interfacing between the micro-
processor unit and peripheral devices, and a software
programmable interval timer with interrupt, capableof
timing in intervals from 1 to 262,144 clock periods.
FIGURE 1. SY6530 BLOCK DIAGRAM
DATA
CONTROL
REGISTER
A
OUTPUT
REGISTER
A
PERIPHERAL
DATA BUFFER
A
INTERVAL
TIMER
PERIPHERAL
DATA BUFFER
B
OUTPUT
REGISTER
B
t
DATA
BUS
BUFFER
DO
ADDRESS
DECODER
D7
AD
A9 RS
CHIP
SELECT
R/W
CSl CS2
02
64 X 8
1KX8
RAM
ROM
DATA
CONTROL.
REGISTER
B
RNi RES
3-117
SY6530
ABSOLUTE MAXIMUM RATINGS
COMMENT
Supply Voltage (Vee! •.•••.....•...• -.3 to +7.0V
Input/Output Voltage (VIN) .••.••.••. , -.3 to +7.0V
Operating Temperature (Top). • • . . • . . . . .. 0 to 70°C
Storage Temperature Range (TSTG)" ..• -55 to +150°C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the de·.
vice at these or any other conditions above those indicated
in the operational sections of this specification is not
implied.
D.C. CHARACTERISTICS (Vee = 5.0V ±5%, VSS ';' OV, TA = O°C to 70°C)
Input High Voltage
Input Low Voltage
Input Leakage Current; VIN - VSS +5V
A0·A9, RS, R/W, RES, 02, PB6*, PB5*
I nput Leakage Current for High I mpedence State
(Three State); VIN = .4V to 2.4V; 00·07
Input High Current; VIN = 2.4V
Symbol
Min.
VIH
2.4
VIL
-0.3
Low Input Current; VIN =.4V
Output High Voltage
V
V
2.5
J.1A
ITSI
±1.0
±10.0
J.1A
-100.
-300.
1.0
J.1A
1.6
mA
V
VOH
2.4
VCC = MIN, ILOAO';;; -100J.1A (PM-PA7, PB0-PB7, 00-07)
1.5
ILOAO';;; -3mA (PA0, PB0)
Output Low Voltage
V
IOH
VOH ~ 2.4V (PA0-PA7, PB0-PB7, 00-07)
1.5V Available for other than TTL
(Oarlingtons) (PA0, PB0)
Output Low Current (Sinking); VOL';;;.4V
IOL
Clock Input Capacitance
I nput Capacitance
Output Capacitance
Power .Dissipation (Vee= 5.25V)
'When Programmed as address pins
0.4
VOL
VCC = MIN, ILOAO';;; 1.6mA
Output High Current (Sourcing);
~
Unit
VCC
0.4
1.0
IlL
PM·PA7, PB0·PB7
Max.
liN
IIH
PA0'PA7, PB0·PB7
Typ.
-100
-1000
J.1A
-3.0
-5.0
mA
mA
1.6
CCLK
30
pF
CIN
10
pF
COUT
10
pF
Po
700
mW
All values are D.C. readings
WRITE TIMING CHARACTERISTICS
Symbol
Min.
Clock Period
TCYC
1
Rise & Fall Times
TR, TF
Clock Pulse Width
TC
Characteristic
R/W valid before positive transition of clock
TWCW
Typ.
Max.
Unit
10
J.1s
25
ns
470
ns
180
ns
Address valid before positive transition of clock
TACW
180
ns
Oata bus valid before negative transition of clock
TOCW
300
ns
Oata Bus Hold Time
THW
10
Peripheral data valid after negative transition of clock
TCPW
1
J.1s
TCMOS
2
J.1s
Peripheral data valid after negative transition of clock driving CMOS
ns
(Level = VCC -30%)
R/W hold time after negative clock transition
TCWW
0
ns
Address hold time
TCAH
0
ns
3-118
SY6530
READ TIMING CHARACTERISTICS
C ha racte ristic
Symbol
Min.
Typ.
Max.
Unit
R/W valid before positive transition of clock
TWCR
180
ns
Address valid before positive transition of clock
TACR
180
ns
Peripheral data valid before positive transition of clock
TpCR
300
Data bus valid after positive transition of clock
TCDR
ns
395
ns
Data Bus Hold Time
THR
10
ns
I RQ (I nterval Timer I nterrupt) valid before positive transition of clock
TIC
200
ns
R!W hold time after negative clock transition
TCWR
0
ns
Address hold time
TCAH
0
ns
Loading = 30 pF + 1 TTL load for PA0-PA7, PB0-PB7
= 130 pF + 1 TTL load for 00-07
INTERFACE SIGNAL DESCRIPTION
Reset (RES)
During system initialization a 10w«0.4V)on the RES
input will cause a zeroing of all four I/O registers. This
in turn will cause all I/O buses to act as inputs,
protecting external components from possible damage and erroneous data while the system is being
configured under software control. The Data Bus
Buffers are put into an OFF-STATE during reset.
Interrupt capability is disabled with the RES signal.
The RES signal must be held low for at least one clock
period when reset is required.
Data Bus (00-07)
The SY6530 has eight bi-directional data lines (0007). These lines connect to the system's data bus and
allow transfer of data to and from the microprocessor.
The output buffers remain in the off state except when
a Read operation occurs.
Peripheral Data Ports (PAO-PA7, PBO-PB7)
The SY6530 has two 8-bit peripheral I/O ports, PortA
(lines PAO-PA7) and Port B (lines PBO-PB7). Each line
is individually software programmable as either an
input or an output. Bywriting a "0" to a nybit position of
the Data Direction Register (DORA or DDRB) the
corresponding line will be programmed as an input.
Likewise, by writing "1 "to any bit position in the DDR
will cause the corresponding line to act as an output.
Input Clock (1J 2)
The input clock is a system Phase Two clock.
Read/Write (R/W)
R/W is supplied by the microprocessor and is used to
control the transfer of data to and from the SY6530. A
high on the R/W pin allows the processorto read(with
proper addressing)the SY6530. A lowon the R/W pin
allows a write (with proper addressing)totheSY6530.
When the Ports are programmed as inputs and their
output registers (ORA and ORB) are read by the MPU,
the level onthe portlineswill betransferredtothe Data
Bus. When the ports are programmed as outputs the
lines will reflect the data written by the MPU into the
output registers.
Interrupt Request (IRQ)
The IRQ output is derived from the interval timer. The
same line, if not used as an interrupt, can be used as a
peripheral I/O (PB7). When used as an interrupt, the
pin should be set to an input in the data direction
register. As IRQ the output will be normally high with a
low indicating an interrupt from the SY6530. An
external pull-up device is not required; however, if
collector-OR'd with other devices, the internal pull-up
may be omitted with a mask option.
PAO and PBO are capable of direct transistor drive
(source 3mA at 1.5V).
Address and Select Lines (AO-A9, RS, PB5 and PB6)
AO-A9 and ROM SELECT (RS) are always used as
addressing lines. There are 2 additional lines which
are mask programmable and can be used either
individually or together as CHIP SELECTS. They are
PB5 and PB6. When used as peripheral data lines they
cannot be used as chip selects.
3-119
SY6530
FIGURE 2. WRITE TIMING CHARACTERISTICS
CLOCK INPUT
RiW
ADDRESS
DATA BUS
VCC -30%
------,--
TDCW--+-~~~-
2.0V
PERIPHERAL
DATA
0.8V
TCMOS
FIGURE 3. READ TIMING CHARACTERISTICS
CLOCK INPUT
RIw
ADDRESS
PERIPHERAL'
DATA
'DATA BUS
~~T_IC
_______________________
3-120
_____________ _
SY6530
INTERNAL ORGANIZATION
A block diagram of the internal architecture is shown
in Figure 1. The SY6530 is divided into four basic
sections, RAM, ROM, 1/0 and TIMER. The RAM and
ROM interface dire~tly with the microprocessor
through the system data bus and address lines. The
liD section consists of two 8-bit halves. Each half
contains a Data Direction Register (DDR) and an 1/0
Register.
The Interval Timer can be programmed to count up to,
256 time intervals. Each time interval can beeither H,
8T, 64T or 1024rincrements, where T is the system
clock period. When a full count is reached, the
. interru'pt flag is set to a logic "1". After the interrupt
flag is set the internal clock continues counting down
at a H rate toa maximum of -255T. This allows the
user to read the counter and then determine how long
the interrupt has been set.
ROM 1 K Byte (B K Bits)
The 8K ROM is in a 1024 x 8 configuration. Address
lines AO-A9, as well as RS are needed to address the
entire ROM. With the addition of CSl and CS2, seven
SY6530's may be addressed, giving 7168 x 8 bits of
contiguous ROM.
The 8-bit system Data Bus is used to transfer data to
and from the Interval Timer. If a count of 52 time
intervals were to be counted, the pattern 0 01 10100
would be put on the Data Bus and written into the
Interval Time register.
RAM-64 Bytes (512 Bits)
A 64 x 8 static RAM is contained on the SY6530. It is
addressed by AO-A5 (Byte Select), RS, A6, A7, A8, A9,
and, depending on the number of chips'in the system,
CSl andCS2.·
At the same time that data is being written into the
IntervalTimer, the counting intervalsot'l,8,64, 1024T
are decoded from address lines AO and A 1. During a
Read or Write operation.address line A3 controls the
interrupt capabilityofPB7, i.e., A3 = 1 enables IRQ on
PB7, A3= 0 disables IRQ on PB7. When PB7 is used as
IRQ with the Interval Timer it should be programmed
as an input. If PB7 is enabled by A3 and an interrupt
occurs PB7 will go low. Whe'nthe Timer isreadpriorto
the interrupt flag being set, the number of time
intervals remaining will be read, i.e., 51, 50, 49, etc.
Internal Peripheral Registers
There are four 8-bit internal registers, two data
direction registers (DDRA and DDRB) and two
peripheral 110 data registers (ORA and ORB). The two
data direction registers control the direction of the data
into and out of the peripheral line. A "1" written into
the Data Direction Register sets upthe corresponding
peripheral buffer line as an output. Therefore,
anything then written intothellO Registerwillappear
on that corresponding peripheral pin. A "0" written
into the DDR inhibits the output buffer from
transmitting data to or from the 1/0 Register. For
exa mple, a "1 " loaded into data di rection A, position 3,
sets up peripheral line PA3 as an output. If a "0" had
been loaded, PA3 would be configured as an inputand
remain in the highstate. Thetwodata 1/0 registers are
used to latch data from the Data Bus during a Write:
operation until the peripheral device can read the data
supplied by the microprocessor.
When the Timer has counted down to 0 OOOOOOOan
interrupt will occur on the next count and the counter
will read 1 1 1 1 1 1 1 1. After interrupt, the timer
register decrements at a divide by "1" rate of the
system clock. If after interrupt, the Timer is read and a
valiJeof"1-1 00111 isread,thetimesinceinterruptis
28T.The value read is in two's complement.
Value Read = 1 1 1 00 1 00
Complement = 00011011
ADD 1
= 000 1 1 1 00 = 28.
. Thus, to arrive at the total elapsed time, merely do a
two's complement and add to the original time written
into the Timer. Again, assume time written as0011 0
1 00 (= 52). With a divide by8, total time to interrupt is
(52 x 8) + 1 = 417T. Total elapsed time would be
416T + 28T = 444T, assuming the' value read atter
interrupt was 11 1 001 0 O.
During a read operation by the microprocessor the
SY6530 transfers the TTL level on the peripheral data
lines to the data bus. For the peripheral data lines
which are programmed as outputs the microprocessor
will read the corresponding data bits of the 1/0
Register. The only way the 1/0 Register data can be
changed is by a microprocessor Write operation. The
liD Register is not affected by a Read ofthe data onthe
peripheral lines.
.
After an interrupt, whenever'the Timer is written or
read the interrupt is reset. However, the readingofthe
Timer at the same time the interrupt occurs will not
~eset the interrupt flag.
Figure 5 illustrates an 'example of inter·rupt.
Interval Tinier
The Timer section of the SY6530 contains three basic
parts: preliminary divide down register, programmable 8-bit register and interrupt logic. These are
illustrated in Figure 4.
3-121
SY6530
FIGURE 4. BASIC ELEMENTS OF INTERVAL TIMER
R/W
A3
D7 D6 D5 D4 D3 D2 Di DO
Riw
Al
02
REGISTER
D6D5 D4 D3 D2 Dl DO
D7
FIGURE 5. TIMER INTERRUPT TIMING
WRITET
~~__________________________________________________________~__~__~___
1. Data written into Interval Timer is 001 1 0 1 00= 5210
2. Data in Interval Timer is 0 0 0 1 1 0 0 1 = 2510
52
-~-1
8
= 52-26-1 = 25
3. Data in Interval Timer is 0 0 0 00000 = 010
52 - 415_ 1 = 52-51-1 = 0
8
4. Interrupt has occured at ¢2 pulse #416
Data in Interval Timer = 1 1 1 11 1 1 1
5. Data in Interval Timer is 1 0 1 0 1 1 00
two's complement is 0 1 0 1 0 1 00= 8410
84 + (52 x 8)= 50010
When reading the Timer after an interrupt, A3 should be low so as to disable the IRQ output. This is done so as'to
avoid future interrupts until'another Write timer operation,
ADDRESSING
Because the address, decode matrix is maskable the
SY6530 offers many variations to the user, RAM,
ROM and the 1/0 - Interval Timer block may be
enabled individually byanycombination of A6-A9 plus
RS, CS1 and CS2 (refer to Figure 6 for a typical
configuration). Because CS1 and CS2 are mask
options and act independently neither, either; or both
may be masked as Chip Selects orPort B lines.
One-Chip Addressing
Figure 6 illustrates a 1 -chip system for the SY6530,
and Figure 8details address decoding.
3-122
SY6530
FIGURE 6. SY6530 ONE CHIP ADDRESS ENCODING SCHEME •
'-,
rV
'l----------..,...INT"JIMER SEL,
r--~-IA3
INTERVAL
r - A1 TIMER
A0
liD TiMER SEL.
~
RAM SEL,
A5
r-------------; ~-------------- --------~
A4
HCS2
CS1
I/O SEL,
A1 liD
A0
~>o+++-+-++-t-++-t-Hr-++-+++
~
A3, RAM
A2
A1
A0
-r~-_+~~+_+_~_+~_r~+_~ri_+-r
lp
RS0-r~--r~~~-+-r4-~~-+~+-~r+
~~+rHK++~~~~
ROM SEL.
A9-+~~~~~-+-r-r~~~+_~~~~---~~r;-+-+-r~~ A9
,~~~~++~~+-
...
A8~~7--~-+~4-~~-+~+-~-+-~-r-4-~~-+~ A8
A7-r~,~"'-~-+~~~~-+~+-~-+---r-~~~-+~ A7
4>
A6
A5~___~_-_-___-_-___-_-_-___-_-___-_-_~
__-_-_-__-_-_-___-_-_-__-_-_-___-_-___-_-_--~1-+-+-~~ A5
A4--------------~-----+_ri_~r; A4
A3
A2
A1------------~---~----~-------~~ A1
A0------------------------------------------------~ A0
A3---------------------~~+_~
A2------------~--------------------~+_~
A.
X indicates mask programming
ROM select '= CShRSO
RAM select = Cs"ioR'S'O-Ag-A7.A6
110 TIMER SELECT = CS1.RSO.A9.A8.A7.A6
i.e.
B.
Notice that AS is a don't care for
RAM select
C.
The CS2/PB5 pin functions as PB5 in this example.
Seven Chip Addressing
In the 7-chip system the objective would beto have 7K
of contiguous ROM, with RAM in low order memory.
The 7K of ROM could be placed between addresses
65,535 and 1024, Forthiscase, assumeA 13, A 14, and
A 15 are all 1 when addressing ROM, and D when
addressing RAM or 1/0. This would place the 7K ROM
between addresses 65,535 arid 58,367. The 2 lines
designated as chip-select or 1/0 would be mask
programmed as chip select. RS would be connected to
address line AlD. CSl and CS2 would beconnectedto
address linesAl i and A12 respectively. See Figure 7.
- Timer Block. AO' thru A3 specify which of the four
I/O registers are selected and select the',;"odes of
operation for the Timer. Figure 8 illustrates the internal
decoding of these address bits and their function.
Address line A2 selects 1/0, or Timer. If I/O-Timer
Select is enabled and A2 is low the 1/0 registers are
. selected and bits AD and A 1 are decoded to select the
individual register.
During a write when I/O-Timer Select isenabled and
A2 is high the Timer is selected. BitsAO andA1 select
the + by rate (the data lines should at-this time have,
the count value ,to be written); and A3 determines if
PB7 is to act as an IRQ output.
1/0 Register - Timer Addressing
The previous two examples have illustrated how to
address the ROM, RAM and the general 110 Register
3-123
§.
SY6530
'f( ",
The addressing of the ROM 'select, RAM select and I/O timer select lines would be as ,follows:
FJGURE 7. SY6530 SEVEN CHIP ADDRESSING SCHEME
:' .
SY6530 #1,
SY6530 #2,
SY6530 #3,
SY6530 #4,
SY6530 #5,
SY6530
#6,
SY6530 #7,
ROM SELECT, '
RAM SELECT'
I/OTIMER
ROMSELECT:
RAM SELECT
I/O TIMER
ROM SELECT
RAM SELECT
I/O TiMER"
ROM SELECT
RAM SELECT
, I/OTIMER'
ROM SELECT
RAM SELECT
"lloTIMER
ROM SELECT
RAM SELECT'
IIOTIMER
ROM SELECT
RAM SELECT'
I/O TIMER
;,'"
AS
CS2
A12
CSl
All
0
0
0
0
0,
0
0
0
0
1
0
0
·1
'0
0,
1
0
0
1
0
0
0
0
1 '
0
0
"
0
Al0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
A9
AS
A7
A6
x
x
x
X
0
0
0
0
0
x
x
0
0
x
0
0
0
0
0
X
X
X
X
0
0
0
1
0
0
"x0
x
x
X
X
X
X
1
0
.0
0
0
'
'"K
0
0
0
0
',>(
0
0'
0
0
0
* RAM select for SY6530 #5 ~6ul~ read = A12. A 11 • A 10. A9 • AS. A7
0
0
,
0
0
;1
0
1 "
0
O.
X
x
x
"
x
0
0
" ,1
0':
~" A6 '
x
x
X
X
1
0
0
'
FIGURE 8." ADDRESSING DECODE FOR,I/O REGISTER ANDTIMER
ADDRESSING DECODE
,
'
ROM
SELECT
.RAM
SELECT
I/O.TIMER
SELECT
' 1
0
o
o
o
0
1
0
READ ROM
WRITE RAM
0
READ RAM
0
WRITE DDRA
0
0
READ DDRA
0
WRITE DDRB
0,
0
0,
R/W
1
1'
,1
READ DDRB
0
0
1
0
1
W~ITEORA
0
0
1'
0
WRITE9RA
WRITE ORB
0
0
0
0
WRITE'ORB
0
0
0
0
b.
0
0
+64T
0
0
+ 1024T
0
0
:READ TIMER'
0,
0
REAt) INTER RUPl' FLAG
0
0
'. :;
0
A3
A2
A1
AO
X
X
X
X
X
X
X
X
,X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
1
0
0
0
0
0
0
X
X,
0
1
0
0
0,
0,
*
1
0
*'
1
1
,1
l'
0
*
X
1
X
X
0
1
.. ' ,~
"0'"
0'
0
WRITE TIMER
',',' +,1T
, +ST
,:.,;',
, X
= Don't care condition"
1
*
:r"
=1 Enables I RQ to PB7
A3 =0 Disables, I RQ to PB7
* A3
·3-124
0
,,1
1
SY6530
40
21
10° max.
~
~
D D T O R N O T C H - D D .600 max. [(15,87) .615
TO LOCATE
(15.24 mm)
(15.11) .595
PIN NO.1.
1
20
t
t
.155 max.
(3.93 mm)
2.020 max.
(51.30 mm)
qpw ~-+-+-r-'------T--+-
~I
(1.65)
M1)
(.55)
(.45)
.040
065 TYP. -
:~~~ TYP.~
L ~
----
-+-
ADDRESS
DECODER
••••
DO
OUTPUT
REGISTER
A
• •••
07
AO
A6
Rs
PERIPHERAL
DATA BUFFER
A
PERIPHERAL
DATA BUFFER
B
128 x 8
STATIC
RAM
CHIP SELECT
~OGIC
1
CS1 CS2
02
PB7
0000
0000
DATA
DIRECTION
REGISTER
A
PBO
RNV RES
3-129
OUTPUT
REGISTER
B
!I'lIlktnU tlllle.
LPEN REGISTER FUll
"0" This bit goes to "0" whenever either register
R16 or R17 is read by the ~~PU.
"1" This bit goes to "'" whenever a LPEN strobe
' - - - - UPDATE READY
"0" This bit goes to "0" when register R31 has
been either read or written by the MPU.
"1" This bit goes to "1" when an Update Strobe
Horizontal Total (RO)
DESCRIPTION OF INTERNAL REGISTERS
Figure 1 illustrates the format of a typical video display
and is necessary to understand the functions of the
various SY6545 internal registers. Figure 2 illustrates
vertical and horizontal timing. Figure 3 summarizes the
internal registers and indicates their address selection
and read/write capabilities.
Address Register
This is a 5-bit register which is used as a "pointer" to
directSY6545 data transfers to and from the system
MPU. Its contents is the number of the desired register
(0-31). When RS is low, then this register may be
loaded; when RS is high, then the register selected is the
one whose identity is stored in this register.
Status Register
This 3-bit register is used to monitor the status of the
This 8-bit register contains the total of displayed and
non-displayed characters, minus one, per horizontal line.
The frequency of HSYNC is thus determined by this
registe r.
Horizontal Displayed (R 1)
This 8-bit register contains the number of displayed characters per horizontal line .
Horizontal Sync Position (R2)
This 8-bit register contains the position of the HSYNC
on the horizontal line, in terms of the character location
number on the line. The position of the HSYNC determines the left-to-right location of the displayed text
on the video screen. In this way, the side margins are
adjusted.
HOR TOTAL
I
VERT
NUMBER OF
SCAN LINES
PER
DISPLAYED
VERT
TOTAL
CHARACTER
ROW
Figure 1_ Video Display Format
3-160
W1
l
1 COMPLETE FIELD (VERTICAL TOTALI
,~'"''~'''
DISPLAY
ENABLE
HSVNC
"11
cE'
c
;
!'J
~
~
c'i'
Col
I
~
~
VSVNC
RAO-RA4
!!!..
III
:::I
c..
:J:
1 COMPLETE SCAN LINE (HORIZONTAL TOTAL)
...0j;j'
HORIZONTAL DISPLAYED
0
:::I
i.
-I
CCLK
§'
S'
I
eQ
DISPLAY
ENABLE
I.
I
r---
HSVNC
MAO-MA13
~
AAO-RA4
C\
~
•
.......
U'I
Horizontal and Vertical SYNC Widths (R3)
interfaced to a variety of CRT monitors, since the
HSYNC and VSYNC timing signals may be accommodated without the use of external one-shot timing.
This 8-bit register contains the widths of both HSYNC
and VSYNC, as follows:
Vertical Total (R4)
VSYNC WI DTH+
HSYNC WIDTH
I
(NUMBER OF SCAN
LINES)
The Vertical Total Register is a 7-bit register containing
the total number of character rows in a frame, minus
one. This register, along with R5, determines the overall
frame rate, which should be close to the line frequency
to ensure flicker-free appearance. If the frame. time is
adjusted to be longer than the period of the line frequency, then RES may be used to provide absolute
synchronism.
I
(NUMBER OF CHARACTER
CLOCK TIMES)
·,F BITS 4·7 ARE ALL "0", THEN VSYNC WILL BE
16 SCAN LINES WIDE.
Control of these parameters allows the SY6545 to be
Address Reg.
Reg.
No.
Register Bit
CS
RS
4 3 2 1 0
1
-
0
0
-
Address Reg.
0
0
- - - - - - - - - - - - -
_.
Status Reg.
0
1
0 0 0 0 0
RO
Horiz. Total - 1
0
1
0 0 0 0 1
Rl
Horiz. Displayed
# Charac.
0
1
.0 0 0 1 0
R2
Horiz. Sync
# Charac.
0
1
0 0 0 1 1
R3
VSYNC, HSYNC
Widths
# Scan Lines and
# Char. Times
V
0
1
0 0 1 0 0
R4
Vert. Total - 1
# Charac. Row
0
1
0 0 1 0 1
R5
Vert. Total Adjust
# Scan Lines
0
1
0 0 1 1 0
R6
Vert. Displayed
# Charac. Rows
0
1
0 0 1 1 1
R7
Vert. Sync Posit ion
# Charac.Rows
0
1
0 1 0 0 0
R8
Mode Control
V
V
V
V
V
V
V
V
V
Stored Info.
Register Name
RD
WR
V
U L
J
V
V
# Charac.
Position
0
1
0 1 0 0 1
R9
Scan Lines - 1
# Scan Lines
1
0 1 0 1 0
R10
Cursor Start
Scan Line No.
0
1
0 1 0 1 1
Rl1
Cursor End
Scan Line No.
0
1
0 1 1 0 0
R12
Display Start
Addr IH)
0
1
0 1 1 0 1
Rl3
Display Start
Addr ILl
0
1
0 1 1 1 0
Rl4
Cursor Position IH I
0
1
0 1 1 1 1
Rl5
Cursor Position ILl
V
V
V
V
V
1
1 0 0 0 0
R16
Light Pen Reg IHI
1
1 0 0 0 1
R17
Light Pen Reg III
0
1
1 0 0 1 0
Rla
Update Address
Reg IH)
V
0
1
1 0 0 1 1
Rl9
Update Address
Reg III
V
0
1
1 1 1 1 1
R3l
Dummy Location
0
0 0 0 0 0 0
V3 V2 V1 Va H3 H2 Hl Ha
~
o
o 0 0
0
0
~ ~ ~o
0
0 0 0
0
~o
0 0 0 0 0 0
~o
0 0 0
o 0 0
0 0 0 0
0 0 0
0
~ ~ ~O 0 0 0
~ B1 So 0 0 0 0
~ ~ ~e e e e
~ ~O
,
0
0
e
0 0 0 0 0
o 0 0 0 0
0 0 0
0
0
0 0
0
0
0
0 0
(I
0 0
0 0 0
000 o 0 0
o 0
~ ~o
0
0
0
$
00 0
0
0
0
0 0
0
~~~~~~~~
~ Designates unused bit. Reading this bit is always °0", except for
3-162
0
0 0 0 0 0 o 0 0
[!] Designates binary bit
R3l, which does not drive the data bus at all, and for CS
which operates likewise.
V~ ~ ~ ~ ~
0 0 0 0 0 o 0
~ ~O
0
Figure 3. Internal Register Summary
3 2 1 0
0
V ~ ~o
V 000
0
Notes:
5 4
~~ ~~~~~ ~
V ~ ~ ~ A,j A3 A2 A1 Ao
Reg. No.
0
7 6
= "1"
Vertical Total Adjust (R5)
Cursor Start (H10) and Cursor End (R11)
The Vertical Total Adjust Register is a 5-bit write only
register containing the number of additional scan lines
needed to complete an entire frame scan and is intended
as a fine adjustment for the video frame time.
These 5·qit registers select the starting and ending scan
lines for the cursor .. In addition, bits 5 and 6 of R 1 Oare
used to select the cursor mode, as follows:
Vertical Displayed (R6)
This 7-bit register contains the number of displayed
character rows in each frame. In this way, the vertical
size of the displayed text is determined.
BIT
CURSOR MODE
I
6
5
0
0
No Blinking
i
Vertical Sync Position (R7)
0
1
No Cursor
This 7-bit register is used to select the character row
time at which the VSYNC pulse is desired to occur and,
thus, is used to position the displayed text in the vertical
direction.
I
1
0
Blink at 1/16 field rate
1
1
Blink at 1/32 field rate
Mode Control (R8)
This register is used to select the operating modes of the
SY6545 and is outlined as follows:
i
j
Note that the ability to program both the start and end
scan line for the cursor enables either block cursor or
underline to be accommodated. Registers R 14 and R 15
are used to control the character position of the cursor
over the entire 16K address field.
Display Start Address High (R12) and Low (R13)
Lt,
I
ITTil
1
x
NTEALACE MODE CONTROL
OPERATION
0
IxI 0 I
1
These registers together comprise a 14-bit register whose
contents is the memory address of the first character of
the displayed scan (the character on the top left of the
video display, as in Figure 1). Subsequent memory
addresses are generated by the SY6545 as a result of
CCLK input pulses. Scrolling of the display is accomplished by changing R 12 and R 13 to the memory address
associated with the first character of the desired line of
text to be displayed first. Entire pages of text may be
scrolled or changed as well via R 12 and R 13.
Non·lnterlace
Invalid (Do Not Usel
vIDeo DIS PLAY RAM ADDRESSING
"0" for stra ight binary
"1" for Ao w/Column
_VIDEODIS PLAY RAM ACCESS
"0" for sha red memory
"1" for tran sparent memory addressing.
Cursor Position High (R14) and Low (R15)
' - - - - - DISPLAY ENABLE SKEW
"0" for no delay
"1" to dela y Display Enable one character time
CURSOR SKEW
"0" for no delay
"1" to dela y Cursor one character time
UPDATE STROBE (TRANSPARENT MODE, ONLY)
"0" for pin 34 to function as memory address
"1" for pin 34 to function as update strobe
UPDATE/R EAD MODE (TRANSPARENT MODE, ONLY)
"0" for updates to occur during horizontal and vertical
blani2
CLOCK
MAO-MA13
Figure 8. ¢11¢2 Transparent Interleaving
Il
.>2
CLOCK
VIDEO
DISPLAY
MEMORY
ADDRESSES
Figure 7. ¢1/¢2 Interleaving
•
Vertical Blanking
With this approach, the address circuitry is identical
to the case for MPU Priority updates. The only difference is that the Vertical Retrace status bit (bit 5 of
the Status Register) is used by the MPU sO that access
to the video display memory is only made during
vertical blanking time (when bit 5 is a "1"). In this
way, no visible screen perturbations result.
- - 1 - - MPU CYCLE
HorizontallVertical Blanking
In this mode, the Update Address is loaded by the
MPU, but is only gated onto the MA lines during
horizontal or vertical blank times, so memory accesses
do not interfere with the display appearance. To
signal when the update address is on the MA lines, an
update strobe (STB) is provided as an alternate function of pin 34. Data hold latches are necessary to
temporarily retain the character to be stored until
the retrace time occurs. In this way, the system MPU
is not halted waiting for the blanking time to arrive.
Figure 9 illustrates the address and strobe timing for
this mode.
Transparent address modes are qu ite complex and offer
significant advantages in system implementation. The
details of their application are covered thoroughly in
related Technical Notes available from Synertek.
SY6545-t
CCLK
~
BLANKING -- - - - _ _ _ _ _ _ _ __
I:HORIZO:NTALIVERTICAL
I
DISPLAY
DISPLAY
I
ENABLE
I
NON-D\f-SP_L_A_Y_ _ _ _--I.
CRT DISPLAY ADDRESSES
CRT DISPLAY ADDRESSES
~~~3 ~1----+t_6g~~~s,"---,~\ \ \ \ s:\ \\\\\ \~
I
I
I
I
:n
:
UPSTB
------------------~Ir_-JI
I~~------------~------------------~---
Figure 9. Retrace Update Timings
Cursor and Display Enable Skew Control
Bits 4 and 5 of the Mode Control register (R 8) are used
to delay the Display Enable and Cursor outputs, respectively. Figure 10 illustrates the effect of the delays.
CCLK
CURSOR {-":I;'::NO=D':::EL::::A:':Y..!.)....Jh!-;- - - ; - . - - -
_~IW~I~T~H~D~E: : LA. !.Y~I~ ....Jh~:
__
~~~~riE{
_ _ __
INO DELAY)
EDGE
_~I~W~IT_H~D_E_LA~Y~I_ _ __ _ I
~ S~:~ VE {
EDGE
INa DELAY)
-~I:::W:-::IT:;:H-;:D:-;:E-:-LA~Y:::)-----,
Figure 10. Cursor and Display Enable Skew
3-167
SY6545-t
FRAME
VERTICAL DISPLAYED
FRAME
VERTICAL
BLANKING
DISPLAY
ENABLE
VERTICAL
BLANKING
STATUS
BIT
{STATUS
:I~G~~TER
~
I
"0" '" DISPLAY ACTIVE
'--------------l
\
SWITCHES STATE AT
END OF LAST DISPLAYED
SCAN LINE.
1 - - '_
_- - - - '
"1" '" VERTICAL
BLANKING
ACTIVE
Figure 11. Operation of Vertical Blanking Status Bit
3-168
SY6SS1
MICROPROCESSOR
PRODUCTS
,\ SUBSIDIARY OF HONEYWELL
GI
On-chip baud rate generator: 15 programmable baud
rates derived from a standard 1.8432 MHz external
crystal (50 to 19,200 baud)_
•
Programmable interrupt and status register to simplify software design_
Single +5 volt power supply_
Serial echo mode_
False start bit detection_
tI
•
GI
o 8-bit bi-directional data bus for direct communication
with the microprocessor_
• External 16x clock input for non-standard baud rates
(up to 125 Kbaud).
o Programmable: word lengths; number of stop bits;
and parity bit generation and detection_
• Data set and modem control signals provided_
• Parity: (odd, even, none, mark, space).
G Full-duplex or half-duplex operation.
o 5,6, 7, 8 and 9 bit transmission.
The SY6551 is an Asynchronous Communication Adapter (ACIA) intended to provide for interfacing the 6500/
6800 microprocessor families to serial communication
data sets and modems. A unique feature is the inclusion
of an on-chip programmable baud rate generator, with
a crystal being the only external component required_
PIN CONFIGURATION
.'
RM
GND
cs"
CS,
ffi
IRQ
DB,
RES
RxC
DB,
XTAL1
OBs
XTAL2
DB.
RTS
DB3
CTS
DB,
iRO
DCD
¢2--
DB,
TxD
RiW-_
DTR
DBo
RxD
DSR
RSo
DCD
~o
CS,
RS o
RS,
RS,
vcc
RES
DSR
SELECT
AND
CONTROL
LOGIC
RxC
XTALl
XTAL2
RxD
DBo
DB,
L._ _ _ _ _ _ _ _ _ _ _ DTR
ORDERING INFORMATION
Part No.
Package
Clock Rate
SYC6551
SYD6551
SYP6551
SYC6551A
SYD6551A
SYP6551A
Ceramic
Cerdip
Plastic
Ceramic'
Ceramic
Plastic
1 MHz
1 MHz
1 MHz
' - - - - - - - - - - - - - - - RTS
Figure 1. Block Diagram
2 MHz
2 MHz
2 MHz
3-169
SY6551
ABSOLUTE MAXIMUM RATINGS
Symbol
Allowable Range
Supply Voltage
Vee
-0.3V to +7.0V
Input/Output Voltage
VIN
-0.3V to +7.0V
Rating
Operating Temperature
Storage Temperature
Top
O°C to 70°C
TSTG
_55°C to 150°C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied.
All inputs contain protection circuitry to prevent damage to
high static charges. Care should be exercised to prevent unneces-
sary application of voltages in excess of the allowable limits.
D.C. CHARACTERISTICS (Vee
= 5.0V ± 5%, TA = 0-70°C, unless otherwise n~ted)
Symbol
Characteristic
Input High Voltage
Min
Typ
Max
Unit
VIH
2.0
-
Vee
V
Input Low Voltage
VIL
-0.3
-
0.8
V
I nput Leakage Current: VIN = 0 to 5V
(1)2, R/W. RES, CS o ' CS 1, RS o ; RS 1 , CTS, RxD, DCD, DSR)
liN
-
±1.0
±2.5
pA
Input Leakage Current for High Impedance State (Three State)
I TSI
-
±2.0
±10.0
pA
VOH
2.4
-
-
V
Output Low Voltage: I LOAD = 1.6mA
(DBa - DB 7, TxD, RxC, RTS, DTR, IRQ)
VOL
-
-
0.4
V
Output High Current (Sourcing): VOH = 2.4V
(DB o - DB 7, TxD, RxC, RTS, DTR)
IOH
-100
-
-
pA
IOL
1.6
-
-
rnA
Output Leakage Current (Off State): VOUT= 5V (IRQ)
IOFF
-
1.0
10.0
pA
Clock Capacitance (1)2)
CeLK
-
-
20
pF
Output High Voltage: ILOAD = -100pA
(DBa - DBr TxD, RxC, RTS, DTR)
Output Low Current (Sinking): VOL = O.4V
(DB o - DB 7, TxD, RxC, RTS, DTR, IRQ)
Input Capacitance (Except XTAL 1 and XTAL2)
Output Capacitance
Power Dissipation (See Graph) (TA .= O°C) Vee = 5.25V '
CIN
-
-
10
pF
COUT
-
-
10
pF
Po
-
170
300
mW
POWER DISSIPATION vs TEMPERATURE
200
175
TYPICAL
POWER
DISSIPATION
I'---.
150
"----
(mW)
r-
125
100
o
20
40
3-170
60
80
1----------
teye --------~
1-----V'H
02
r--------- V'H
R/Vi
t=t
VIL
~I~
Dew
DATABus~I<---------~:,:
Figure 2. Write Timing Characteristics
WRITE CYCLE (Vcc
= 5.0V ± 5%, TA
= 0 to 70°C,
unless otherwise noted)
SY6551
Characteristic
Symbol
Cycle Time
tCYC
SY6551A
Min
Max
Min
Max
Unit
1.0
-
0.5
.-
J,ls
200
ns
70
-
ns
0
-
ns
70
-
ns
0
ns
20
-
R/W Hold Time
tCWH
0
Data Bus Set-Up Time
tocw
150
-
Data Bus Hold Time
tHw
20
-
2)
tc
400
200
tACR
120
Address Hold Time
tCAR
0
R/W Set-Up Time
t WCR
120
-
ns
Address Set-Up Time
-
tCDR
-
Read Access Time (Valid Data)
200
Read Data Hold Time
tHR
20
Bus Active Time (Invalid Data)
tCDA
40
-
70
0
70
-
20
40
150
-
vee
2.4kn
SY6551 PIN
I
-----,-----1r-----lKr-+---130pF
24kn
TEST LOAD FOR DATA BUS (DBO - DB71.TxD, DTR, RTS OUTPUTS
ns
ns
ns
ns
ns
ns
SY6551
.
tcCY
~
tCH------l
XTAL1
(TRANSMIT
CLOCK INPUT)
\
\
¢2
,-
_t
j
-~cL_1
-----
-"oj-
TxD
NOTE:
TxD rate is 1/16 TxC rate.
IRQ
Figure 4a. Transmit Timing with External Clock
tccy
(CLEAR)
.
_
j,r-
DTR. RTS
~tDDx
OlY
Figure 4b. Interrupt and Output Timing
l~tcH_
~
RxC
(INPUT)
l-tCL-1
NOTE:
RxD rate is 1/16 Rxe rate.
Figure 4c. Receive External Clock Timing
TRANSMIT/RECEIVE CHARACTERISTICS
SY6551
Characteristic
Transmit/Receive Clock Rate
Transmit/Receive Clock High Time
Transmit/Receive Clock Low Time
Min
Max
Min
Max
Unit
tCCY
-
ns
500
ns
500
-
500
ns
500
-,
500
ns
400*
-
400*
·tcH
175
-
175
tCl
175
-
175
Propagation Delay (RTS, DTR)
too
t OlY
I RQ Propagation Delay (Clear)
tlRQ
XTAL 1 to TxD Propagation Delay
(t r, tf = 10 to 30 nsec)
*The baud rate with external clocking is:
SY6551A
Symbol
Baud Rate =
-
500
ns
ns
1
16 x TcCY
INTERFACE SIGNAL DESCRIPTION
several devices to be connected to the common IRQ
microprocessor input. Normally a high level, IRQ goes
low when an interrupt occurs.
RES (Reset)
During system initialization a low on the RES input will
cause internal registers to be cleared.
DBo' DB7
(Data Bus)
The DBo·DB7 pins are the eight data lines used for trans·
fer of data between the processor and th e SY 6551.
These lines are bi·directional and are normally high·im·
pedance except during Read cycles when selected.
¢2 (I nput Clock)
The input clock is the system ¢2 clock and is used to
trigger all data transfers between the system micropro'
cessor and the SY6551.
CS o , CS,
R!W (ReadIWrite)
(Chip Selects)
The two chip select inputs are normally connected to
the processor address lines either directly or through de·
coders. The SY6551 is selected when CSo is high and
CS1 is low.
The R!W is generated by the microprocessor and is used
to control the direction of data transfers .. A high on the
R!W pin allows the processor to read the data supplied
by the SY6551. A low on the R!W pin allows a write to
the SY6551.
RS¢, RS 1
(Register Selects)
The two register select lines are normally connected to
the processor address lines to allow the processor to
select the various SY6551 internal registers. The follow·
ing table indicates the internal register select coding:
IRO (I nterrupt Request)
The I RO pin is an interrupt signal from the interrupt
control logic. It is an open drain output, permitting
3-173
SY65S1
RS 1
Write
RSo
0
0
Transmit Data
Register
Receiver Data
Register
0
1
Programmed
Reset (Data is
"Don't Care")
Status Register
1
0
1
1
DTR
Read
Command Register
Control Register
The table shows that only the Command and Control
registers are read/write. The Programmed Reset operation does not cause any data transfer, but' is used to clear
the SY6551 registers. The Programmed Reset is slightly
different from the Hardware Reset (R ES) and these
differences are described in the individual register definitions.
DSR
Note: If Command Register Bit 0 = 1 and a change of
state on DSR occurs, iFiO will be set, and Status Register Bit 6 will reflect the new level. The state of DSR
does not affect either Transmitter or Receiver operation.
DCD (Data Carrier Detect)
The DCD input pin is used to indicate to the SY6551
the status of the carrier-detect output of the modem. A
low indicates that the modem carrier signal is present
and a high, that it is not. DCD, like DSR, is a highimpedance input and must not be a no-connect.
XTAL 1, XTAL2 (Crystal Pins)
TxD (Transmit Data)
:The TxD output line is used to transfer serial N RZ (nonreturn-to-zero) data to the modem. The LSB (least
significant bit) of the Transmit Data Register is the first
data bit transmitted and the rate of data transmission is
determined by the baud rate selected.
RxD
Note: If Command Register Bit 0 = 1 and a change of
state on DCD occurs, iRO will be set,and Status Register Bit 5 will reflect the new level. The state of DCD
does not affect Transmitter operation, but must be low
for the Receiver to operate.
INTERNAL ORGANIZATION
The Transmitter/Receiver sections of the SY6551 are
depicted by the block diagram in Figure 5.
(Receive Data)
The RxD input line is used to transfer serial NRZ data
into the ACIA from the modem, LSBfirst. The receiver
data rate is either the programmed baud rate or the rate
of an externally generated receiver clock. This selection
is made by programming the Control Register.
RxC
(Data Set Ready)
The DSR input pin is used to indicate to the SY6551 the
status of the modem. A low indicates the "ready" state
and a high, "not-ready." DSR is a high-impedance input
and must not be a no-connect. If unused, it should be
driven high or low, but not switched.
ACIA/MODEM INTERFACE SIGNAL
DESCRIPTION
These pins are normally directly connected to the external crystal (1.8432 MHz) used to derive the various baud
rates. Alternatively, an externally generated clock may
be used to drive the XTAL 1 pin, in which case the
XTAL2 pin must float.
(Data Terminal Ready)
This output pin is used to indicate the status of the
SY6551 to the modem. A low on DTR indicates the
SY6551 is enabled and a high indicates it is disabled.
The processor controls this pin via bit 0 of the Command Register.
Rxe
---------<..-..1
XTAL1
(Receive Clock)
o
TheRxC is a bi-directional pin which serves as either the
receiver 16x clock input or the receiver 16x clock output. The latter mode results if the internal baud rate
generator is selected for receiver data clocking.
XTAL2
1-----TxO
RTS
(Request to Send)
The RTS output pin is used to control the modem from
the processor. The state of the RTS pin is determined
by the contents of the Command Register.
Figure 5. Transmitter/Receiver Clock Circuits
Bits 0.-3 of the Control Register select the divisor used
to generate the baud rate for the Transmitter. If the
Receiver clock is to use the same baud rate as the Transmitter, then RxC becomes an output pin and can be
used to slave other circuits to the SY6551.
CTS (Clear to Send)
The CTS input pin is used to control the transmitter
operation. The enable state is with CTS low. The transmitter is automatically disabled if CTS is high.
3-174
SY6551
CONTROL REGISTER
The Control Register is used to select the desired mode
for the SY6551. The word length, number of stop bits,
and clock controls are all determined by the Control
Register, which is depicted in Figure 6.
CONTROL REGISTER
171615141312
I ,I I
STOP BITS
0
0
1 ::: 2 Stop Bits
1 Stop Bit if Word Length
0
0
0
::: 8 Bits and Parity·
1% Stop Bits if Word Length
::: 5 Bits and No Parity.
0
WORD LENGTH
0
0
DATA WORD
LENGTH
0
0
8
0
1
1
0
7
6
1
1
5
RECEIVER CLOCK SOURCE
o - External
Receiver Clock
o1
ll II
o ~ 1 Stop Bit
r/'T
1
I
0
1
1
1
16x EXTERNAL CLOCK
50
BAUD
0
0
0
1
1
1
0
1
0
0
0
1
1
0
300
600
1200
1800
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
1
1
1
1
1
1 ::: Baud Rate Generator
0
0
0
BAUD RATE
GENERATOR
1
75
109.92
134.58
150
2400
3600
4800
0
1
7200
0
9600
1
19.200
*This allows for 9-bit transmission (B data bits plus parity).
HARDWARE RESET
PROGRAM RESET
Figure 6. Control Register Format
COMMAND REGISTER
The Command Register is used to control Specific TransmitIReceive functions and is shown in Figure 7.
COMMAND REGISTER
1716151413
I I I
PARITY CHECK CONTROLS
6
q
1
1J
OJ
I
I
- .-
5
0
0
0
1
0
1
1
1
0
1
1
1
1
DATA TERMINAL READY
0
OPERATION
BIT
7
J.
Disable Receiver and All
Interrupts (OTR high)
' ::: Enable Receiver and All
Parity Disabled - No Parity Bit
Generated· No Parity Bit Received
Interrupts (OTR lowl
Odd Parity Receiver and Transmitter
Ev~n
I
Parity Receiver and
Transmitter
Mark Parity Bit Transmitted,
Parity Check Disabled
Space Parity Bit Transmitted,
Parity Check Disabled
1 ::: IRQ Interrupt Disabled
TRANSMITTER CONTROLS
~'l,NORMAL/ECHO MODE
FOR RECEIVER
O·
Normal
I
1 '" Echo (Bits 2 and 3
3
2
0
0
0
1
1
0
1
1
TRANSMIT
INTERRUPT
RTS
LEVEL
Disabled
Enabled
Disabled
Disabled
High
must be "0")
HARDWARE RESET
PROGRAM RESET
RECEIVER INTERRUPT ENABLE
0 • I RQ Interrupt Enabled from Bit 3
of Status Register
I~ I~ I I I I I~ I I
Figure 7. Command Register Format
3-175
Low
Low
Low
TRANSMITTER
Off
·On
On
Transmit BRK
SY6551
STATUS REGISTER
TRANSMIT AND RECEIVE DATA REGISTERS
The Status Register is used to indicate to the processor
the status of various SY6551 functions and is outlined
in Figure 8.
These registers are used as temporary data storage for
the 6551 Transmit and Receive circuits. The Transmit
Data Register is characterized as follows:
• Bit 0 is the leading bit to be transmitted.
171S15H31+1 1
0
~
STATUS
0= No Error
1"" Error
Parity Error·
Framing Error·
Overrun*
Receive Data'
Register Full
Transmit Data
Register Empty
Self Clearing**
1"" Error
0- No Error
1 = Error
Self Clearing··
• Bit 0 is the leading bit received.
Read Receive
• Unused data bits are the high-order bits and are
"0" for the receiver.
0" Not Full
1 '" Full
Data Register
0= Not Empty
1 '" Empty
Write Transmit
1 = OCD High
0;:: eSR low
1 = eSR High
5SR
o=
IRQ
The Receive Data Register is characterized in a similar
fashion:
Self Clearing**
0= No Error
0'" OeD Low
DCD
• Unused data bits are the high-order bits and are
"don't care" for transmission.
CLEARED BY
SET BY
No Interrupt
Data Register
• Parity bits are not contained in the Receive Data
Register, but are stripped-off after being used for
external parity checking. Parity and all unused
high-order bits are "0".
Not Resettable
Reflects oeD
State
Not Resenable
Refrects eSR
State
Figure 9 illustrates a single transmitted or received
data word, for the example of 8 data bits, parity, and
1 stop bit.
Read
Status Register
1 = Interrupt
*NO INTERRUPT GENERATED FOR THESE CONDITIONS.
uCLEARED AUTOMATICALLY Af:TER A READ OF RDR AND
THE NEXT ERROR FREE RECEIPT OF DATA.
"MARK"
"MARK"
-LJol
7
I5 IS I7 IPI :
I'
5
DATA BIT'S
PA)ITY
BIT
START
BIT
I~
STOP BIT
Figure 9_ Serial Data Stream Example
Figure 8. Status Register Format
PACKAGE OUTLINES
28 LEAD CERAMIC
28 LEAD PLASTIC
":~1~:: :::::::::]}
1.1151
OI
'I
(1.4201
(1.3801
'
(.or!
(.1S01
-
(1.4701
~~i-'~r--I
~
_
I
t
)
:
g
·
~
'
;
C
:
;
:
~
·
~
g
l
J
~~"'
:~:
~-::=:
~~~-~
J~~
I~ ~ !jIU
t ~ ~ ~ ~ ~ ~~
[
I
U(.0701
(.0551
i:~;~i
(.0101
(.0151
II
---+j H:~~~:
1--(.S201
I
(.5901-----'"
(.OS51
(.1551 (.0651
1.1251 (.0151
3-176
(.0151
(.0901
(.1251 (.0201
Asynchronous
Communication
Interface Adapter
SYNERTEK Extended Temperature
(-40°C to +85°C)
SYE6551
SYE6551A
MICROPROCESSOR
PRODUClS
A SUl3Sl0IARY OF HONEYWELL
G
On-chip baud rate generator: 15 programmable baud
rates derived from a standard 1.8432 MHz external
crystal (50 to 19,200 baud).
•
•
o Programmable interrupt and status register to simplify software design.
o Single +5 volt power supply.
• Serial echo mode.
• False start bit detection.
o 8-bit bi-directional data bus for direct communication
with the microprocessor.
•
G
•
•
o
The SYE6551 is an Asynchronous Communication Adapter (ACIA) intended to provide for interfacing the 6500/
6800 microprocessor families to serial communication
External 16x clock input for non·standard baud rates
(up to 125 Kbaud).
Programmable: word lengths; number of stop bits;
and parity bit generation and detection.
Data set and modem control signals provided.
Parity: (odd, even, none, mark, space).
Full-duplex or half-duplex operation.
5, 6, 7, 8 and 9 bit transmission.
Operation over wide temperature range
(-40°C to +85°C)
data sets and modems. A unique feature is the inclusion
of an on-chip programmable baud rate generator, with
a crystal being the only external component required.
PIN CONFIGURATION
CS1
.'
GND
es,
RtW
ffi
IRQ
RES
DB,
R,e
DB.
XTAL1
DBs
XTAL2
DB4
RTS
DB,
eTS
DB,
hD
.'
T,D
DB,
DTR
DB,
R,D
DSR
es.
CS 1
SELECT
AND
CONTROL
RS,
DeD
RS.
RS,
LOGIC
RS,
Vee
RES
RNi--
R,e
XTALl
XTAL2
DB.
DB,
ORDERING INFORMATION
Part Number
Package
SYEC6551
SYED6551
SYEP6551
Cordip
Plastic
SYEC6551A
SYED6551A
SYEP6551A
Cordip
Plastic
Ceramic
Ceramic
'---------
Clock Frequency
1 MHz
1 MHz
1 MHz
Figure 1. Block Diagram
2 MHz
2MHz
2MHz
3-177
-~
SYE6551/SYE.655 t A
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Allowable Range
Vee
-0.3V to +7.0V
Input/Output Voltage
VIN
-0.3V to +7.0V
Operating Temperature
TOp
-40°C to +85°C
Storage Temperature
TSTG
-55°C to 150°C
Supply Voltage
5,
POWER DISSIPATION vsTEMPERATURE'
22
20o
TYPICAL
,
175
POW.ER
All inputs contain protection circuitry to prevent damage to
DISSIPATION
ImW.1
high static charges. Care should be exercised to prevent unneces-
150
sary application of voltages in excess of the allowable limits.
'"
~
I'-.
,'.
125
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification
is ncit implied.
100
-40
-20
20
40
'TAMBIENT
60
BO
100
reI
D.C. CHARACTERISTICS (Vee = 5.0V± 5%, TA = _40°C to +85°C, unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Input High Voltage
VIH
2.0
-
Vee
V
Input Low Voltage
Vil
-0.3
-
0.8
V
Input Leakage Current: VIN = 0 to 5V
(rf>2, R/W. RES, CSo' CS" RS o ; RS" CTS, RxD, DCD, DSR)
liN
-
±1.0
±2.5
/J.A
Input Leakage Current for High Impedance State (Three State)
ITSI
-
±2.0
±10.0
/J.A
VOH
2.4
-
-
V
Output Low Voltage: IlOAD = 1.6mA
(DBa - DB 7, TxD, RxC, RTS, DTR, IRQ)
VOL
-
-
004
V
Output High Current (Sourcing): VOH = 2AV
(DB o - DB 7, TxD, RxC, RTS, DTR)
IOH
-100
-
-
/J.A
Output Low Current (Sinking): VOL = OAV
(DBa - DB 7, TxD, RxC, RTS, DTR,IRQ)
IOl
1.6
-
-
mA
Output Leakage Current (Off State): VOUT = 5V (I RQ)
IOFF
-
1.0
10.0
/J. A
Clock Capacitimce (rf>2)
CelK
-
-
20
pF
C IN
-
-
10
pF
COUT
-
-
10
pF
PD
-
220
350
mW
Characteristic
Output High Voltage:l lOAD = -100/J.A
(DBa - DB 7, TxD, RxC, RTS, DTR)
Input Capacitance (Except XTAL 1 and XTAL2)
Output Capacitance
Power Dissipation (See Graph) (TA = OOC) Vee = 5.25V
3-178
floppy Disk
SY6591/SY6591 A
Controller (fDe)
MICROPROCESSOR
PRODUCTS
SYNERIEIK
PRELIMINARY
,\ SUBSIDIARY OF HONEYWELL
o Accommodates both single-density (FM) and
double-density (M FM) formats
o Functionally compatible with SY1791-02/SY1793-02
o MPU bus interface directly compatible with
SY6500 and MC6800 microprocessors.
o IBM format compatibility:
- IBM 3740 Single-Density
- IBM System-34 Double-Density
o Single 5 volt power supply
described in the SY1791 -02/SY1793-02 data sheet. The
SY6591 version is different only in the MPU bus interface
characteristics.
The SY6591 Floppy Disk Controller is a fully programmable device intended for SY6500 or MC6800
microprocessor-based systems. Floppy disk control
functions are fully autonomous and are thoroughly
BLOCK DIAGRAM
DBO·DB7
WG
TG43
WPRT
DATA
BUS
BUFFERS
WFIVFOE
iP
TROQ
READY
STEP
DISK
INTERFACE
lOGIC
AND
CONTROL
eLK
RES
RAW READ
WD
q,2
AD
RG
HLD
HLT
RCLK
cs
RM
DIRe
ODEN
TEST
PROCESSOR
INTERFACE
CONTROL
Al
PIN ASSIGNMENTS
EARLY
LATE
NC
Ne
RM
IRQ
cs
DRQ
'1'2
DO EN
AD
WPRT
Al
iP
DBD
TROO
DBl
WFNFOE
DB2
READY
IRQ
DB3
WD
DRQ
DB4
WG
DB5
TG43
DB6
HLD
DB7
RAW READ
ORDERING INFORMATION
Part Number
Package
MPU Clock
Rate
SYC6591
SYD6591
SYP6591
SYC6591A
SYD6591A
SYP6591A
Ceramic
Cerdip
Plastic
Ceramic
Cerdip
Plastic
1MHz
1MHz
1MHz
2MHz
2M Hz
2MHz
3-179
STEP
RCLK
DIRe
RG
EARLY
LATE
elK
HLT
REs
TEST
GND
vee
(+5V)
SY659t/SY659tA
DETAILED LIST OF FEATURES
•
e
•
•
Single 5 volt (±5%) power supply
40-pin package
Automatic track seek with verification
Accommodates single-density (FM) and doubledensity (MFM) formats
•
•
Soft-sector format compatibility
IBM 3740 (single-density) and System-34
(double-density) compatible
•
Single or multiple record read with automatic
sector search or entire track read
Selectable record length (128, 256, 512 or
1024 bytes)
•
•
Single or multiple record write with automatic
sector search
•
Entire track write for initialization
• Programmable controls:
- Selectable track-to-track stepping time
- Selectable head settling and engage times
- Head position verification
- Side verification
• Double-buffered read and write data flow
• DMA or programmed data transfers
• TTL-compatible inputs and outputs
• Write precompensation (FM and MFM)
• Comprehensive status register
PROCESSOR INTERFACE SIGNALS
•
¢2 (¢2) - The ¢2 signal is combined with CS to gate
the processor interface signals AO, Aland R/W into
the floppy disk controller (FOG).
• DATA BUS (DBO-DB7) - This 8-bit non-inverting
bidirectional data bus is used for transferring data,
control, and status words. The outputs are three-state
buffers, capable of driving one standard TIL load and
130 pF.
" READ/WRITE (R/W) - This input signal is used to
control the direction of data transfers. A high on the
R/W pin allows the processor to read data supplied by
the FDC. Alowonthe R/Wpin allows data tobewritten
to the FDC.
• INTERRUPT REOUEST(IRO)- ThelROisanopendrain
output. This signal goes low at the completion or
termination of any operation and is reset when a new
command isloaded into the command register or when
the status register is read. An external pull-up resistor
to Vee is required when using the SY6591 with a
SY6500 or a MC6800 MPU.
• RESET (RES) - This signal is identical to MR on the
SY1791-02/SY1793-02. A low on this input resets
the device and loads hex03 into the command register.
The Not Ready status bit (status bit 7) is reset during
RES low. When RES isdriven high,a Restorecommand
is executed regardless of the state ofthe Ready signal,
and hex 01 is loaded into the Sector Register.
• READ/WRITE(R/W)-lfCS is low,ahighonthisinput
enables the addressed internal register to output data
onto the data bus when ¢2 is nigh.lfCS is low, then a
low on this input gates data from the data bus into the
addressed register when ¢2 is high.
• CHIP SELECT (CS) - A low level on this input selects
the FDC and enables processor communications with
the FDC.
• DATA REOUEST(DRO)- ORO is anopendrainoutput.
ORO high during read operations indicates that the
Data Register (DR) contains data. When high during
write operations; ORO indicates that the DR is empty
and ready to be loaded. ORO is reset by reading or
loading the DR during read or write operations,
respectively. Use 10K pull-up resistor to Vee.
• CLOCK(CLK)- Thisinputrequiresasquarewaveclock
for internal timing reference (2 MHz for 8-inch drives,
1 MHz for 5-inch drives).
FLOPPY DISK CONTROL FUNCTIONS
• REGISTER ADDRESS LINES (AO-A 1) - These inputs
address the internal registers for access by the Data
Bus lines under R/iiii and 2 control.
REGISTER ADDRESS CODES
A1
AO
0
0
1
1
0
1
0
1
J
WRITE
READ
STATUS ~ COMMAND
TRACK
SECTOR
DATA
3-180
These functions are identical tothoseoftheSY1791-021
SY1793-02, and are fully described in the corresponding
data sheet.
SY659t/SY659tA
D.C. CHARACTERISTICS (Vee = 5V ± 5%, TA = 0-70°C) PRELIMINARY
SYMBOL
MIN
Input High Voltage
V IH
Input Low Voltage
VIL
= OV to Vee
Output High Voltage, I LOAD = -100 IlA
Output Low Voltage, I LOAD = 1.6mA
Output Leakage Current, VOUT - Vee
CHARACTERISTIC
Input Leakage Current, V IN
MAX
UNIT
2.0
-
V
0.8
V
IlL
-
±10
IlA
VOH
2.4
-
V
VOL
-
0.4
V
IOL
-
10
IlA
525
mW
15
pF
Power Dissipation (Vce = 5.25 V)
PD
Input Capacitance
CIN
READ CYCLE (Vee = 5.0V ±5%, TA = 0 to70°C, unless otherwise noted)
6591
Characteristic
Symbol
6591A
Mm.
Max.
Min.
470
-
235
Max.
-
Units
cl>2 Pulse Width
te
DRQ Reset From cl>2
tDRR
-
500
-
500
ns
IRQ Reset From cl>2
tlRR
-
3
-
3
IlS
Address Setup Time
'ns
tACR
180
-
90
-
ns
Address Hold Time
teAR
0
0
-
ns
90
-
ns
0
-
ns
200
ns
-
ns
R/W Setup Time
tweR
180
-
R/W Hold Time
tCWH
0
-
Data Bus Access Time
teDR
-
395
-
tHR
10
-
10
Data Bus Hold Time
(tr and tf
=;
10 to 30 ns)
READ TIMING
OROJ
IRO
DATA
3-181
SY6591 jSY6591 A
WRITE CYCLE (Vcc
= 5.0V ± 5%, TA = 0 to 70°C, unless otherwise noted)
6591
I
6591A
Min.
Max.
Min.
Max.
470
-
235
-
ns'
500
-
500
ns
tlRR
-
3
.-
3
/J.s
Address Setup Time
tAcw
180
90
-
Address Hold Time
tCAH
0
-
0
-
ns
RIW Setup Time
twcw
180
-
90.
--
ns
Characteristic
~
~ 1-~:"~~"O~
~c;~~~O
and Performance. as the
.<:\!:',..
cost.
• Compatible with SVM-1 or SM100
Resides in ROM, always available
.. I/O Supported by SUPERMON
•
o
Assembleri~L
The SM100.isd~~i9nElde~pecially forOEM . "
controller or ()f~~Tapplications where. tlw ·r:
microcomputenq:oa\:d is an integralpifrgof 1i'. .•
user's systeril.~[lfh~l:iowerand fleXioin~*:cjf
SYM-1 is retaioElci'but;without the overneaaof
'board.keyooard'a:od:,gi!5play;;>.·.'
,,, " '"""~,, -
,>~~ ,~,
• Macro Capability
:'r):l
• Conditional Assembly
• Source Input from RAM or Tape
o Produces Relocatable Object Code
.. Relocating Loader
~
0'
II
Assemble with Source Listing or Errors-Only
Listing
II Hex, Binary, Decimal or Mixed Data Types
.. 16 Assembler Pseudo-Ops
o 23 Error Codes
o
o Resides in ROM, Always Available
o
Storage of Hex or ASCII
iext ~dltor\' .:,,, ..•%',;;......
I/O Supported by SUPERMON on SVM-1
or SM100
o
o
o Full Floating-Point 9-Digit, Extended BASIC
Edits Line Numbered Text
Upper and Lower Case
o Character String Search with Optional Replace,
o Standard Dartmouth BASIC Statements
LET
READ PRINT DATA IF
THEN FOR
NEXT DIM
END
GOTO
o
o Extended BASIC Statements
o Delete Line(s)
RESTORE
RETURN
ON ... GOTO
REM
STOP
ON ... GOSUB
STEP
Display or Show Number of Occurrences
o Line Edit
o Delete File
GOSUB DEF
INPUT
FN
o Renumber Text File
o Tabbing
.. Scientific Functions
SGN
INT
ABS
SQR
LOG
o Free Format Command Input
RND
EXP
o Output to Hard Copy Device With or Without
Line Numbers
.. Logical Operators
AND
OR
o Load and Record in High Sp!;!ed Format; Entire
NOT
File or Range of Lines
• Operation Commands
RUN
NEW
CLR
Block Insert
LIST
CONT
o Automatic Cassette Motor Control or Manual
FRE
Control through ON and OFF Commands
o Formatting Functions (TAB, POS, SPC)
RAE-1 is a full features Resident Assembler/
Editor. Many powerful text editing functions are
available with error messages giving error type
and location. The user has complete control over
all editor and assembler functions as well as
editor controlled entry to SYM BASIC or SYM
SUPERMON. The user also has control over
cassette recorders for file I/O, or control may be
left to software. The relocating loader maystore
executable code in memory during assembly or
may store object code offset from its proper
execution address.
• Peek, Poke, JSR to Machine Code Subroutines
• String Functions
• Cassette SAVE and LOAD Statements
.. Decimal, Hexadecimal and String Constants
• Real, Integer and String Variables
BAS-1 is a full function BASIC developed for
Synertek Systems by Microsoft Corporation.
BASIC provides higher level language
capabilities, always instantly available from ROM.
5-5
" Programmable Device Control Output
c
Interlaced Screen (Switch Selectable)
" European (50Hz) Compatible (Switch Selectable)
" Choice of Character Screen Sizes:
24 x 80 Character Screen Size
(KTM-2180)
24x 40 Character Screen Size
(KTM-2140)
" Full ASCII Upper and Lower Alphanumeric
Character Set with Descenders
" Control and Special Characters
• 128 Graphics Characters
" Reverse Video
" Scrolling
" Cursor Blanking
" Full Cursor Control
" Absolute and Relative Cursor Addressing
" Auto CR at End of Line (Switch Selectable)
" 110 to 9600 Baud
" Even, Odd, or No Parity
• Complete RS-232-CHandshaking
• Auxiliary RS-232-C I/O Port
• Typewriter Style Keyboard 54 Keys
• Aut!)mat.ic Character Repeat
" Alpha Lock
• Erase - Partial Line, Partial Screen, Full Screen
• Programmable Bell Output
" Requires Single +5V Supply
The KTM-2 provides a keyboard and all the logic
circuitry for a full keyboard terminal. The display
interface provides composite video for user
provided monitor or for a standard TV set
equipped with an RF modulator.
The design of the KTM-2 incorporates 8 MaS-LSI
integrated circuit chips, including two dedicated
microprocessors. Twenty TTL devices are used,
resulting in a total chip count of 28 devices.
The use of standard LSI devices results in a
highly cost effective design with great flexibility
allowing modifications for custom OEM
applications. More features are available at lower
cost than if a CRT controller chip or other
approach had been used.
o New design with
Case
Additional Keys
Built-In Power Supply
-
o 110 to 19.2K Baud
o Choice of Character Screen Sizes:
24 x 80 Character Screen Size (KTM-3/80)
24 x 40 Character Screen Size (KTM-3/40)
o
7
x
9 Character Matrix in 8
x
o Built-In Diagnostics
o KTM-3/40 Will Attach to Standard TV
Set Using RF Modulator
10 Field
o 50/60 Hz Operation
o Typewriter Style Keyboard-58 Keys
D
o 220 Volt Version Available
CAPS LOCK Key
o Upper and Lower Case Alphanumeric
Character Set with Descenders
Newly designed to incorporate the best features of
the popular KTM-2 series, the KTM-3 uses the latest
LSI technology with two microprocessors to provide
a highly reliable, ready-to-use terminal minus the
. CRT monitor. The dual microprocessor design is
highly cost-effective with great flexibility, providing
more features at lower cost than other approaches
used today. For volume usage, Synertek Systems can
customize the KTM-3 to your O.E.M. specifications.
The display interface provides composite video
output and complete video control including
scrolling, full cursor control, and absolute and
relative cursor positioning. A choice of screen sizes
is offered-either 24 x 40 characters, or 24 x 80
characters .
The unit is now in stock and available from your
local distributor.
o Generates and Displays 128 ASCII Characters
o Full and Half Duplex with Modem Controls
D
Built-In Power Includes On/Off Switch
o Scrolling
o Full Cursor Control
o Absolute and Relative Cursor Positioning
o Clear to End-of-Screen, End-of-Line
o Even, Odd, or No Parity
o One or Two Stop Bits
o Framing and Parity Errors Displayed
• Auto Key Repeat
• Debug Mode (Displays Control Characters)
• Cables Included
5-7
Synertek Systems' Micromodules
Awhole new world
of support from
Synertel~ Systems
From single board computers
to single-purpose speciol usage
boards, Synertel~ Systems offers
a growing line of Micromodules that are Motorola
EXORcisor ™ and Micromodule
bus compatible. These boards
provide high quality yet are
low in cost for maximum utility
in any microprocessor application.
Three types of boards are
available: CPU and Single 130ard
Computers, Memory 13oards, and
Peripheral 13oards.
5-8
Synertel~· Systems'
Development Stations can be utilized
for prototyping, product development, and learning. The MDT
series is designed for ease of
use and easy expansion with
our Micromodules. 130th a lowcost cassette-based system and
a floppy-disl~-based system are
available.
MBCO 10 CPU Boord
MBC020 CPUjVideo Boord
.
DESCRIPTION
FEATURES
The M!3C010 and M!3C020 CPU
!3oards provide complete computers
on a single board. !3oth are fully
compatible with the Motorola
EXORcisor™/Micromodule bus and
support MM, I/O, and analog
boards.in those families. !3oth offer a
choice of microprocessors - either
SY6512 or MC6800 - for use in a
full range of systems or development applications.
o Choice of Microprocessors -
The M!3C020 may be used as a costeffective alternative single board
computer, or, with the video
circuitry, it can replace two or more
boards and operate as the heart of
a complete system.
SY6512 (M!3C01 0-65;
M!3C020-65) or MC6800
(M!3C010-68; M!3C020-68)
o Fully !3uffered Data and Address
lines
• Dynamic Memory Refresh
Controls
o Power-on Reset
o
M!3C020 Includes Complete
Video Interface Circuitry for Direct
Attachment to a CRT Monitor
o 1024 bytes of User MM
o . 1 or 2 MHz Versions
o SY6551 ACIA for PS-232-C Serial
Video Features for MBC020
Interface with Crystal-Controlled,
Programmable !3aud Rate
o
SY6522 VIA Provides 20 I/O lines
(with 7 lines optionally buffered),
and 2 16-!3it Counter/Timers
o Full 65K Programmable Memory
Map in 2K Increments, using
32 x 8 !3ipolar PROM
o Direct Memory Access (DMA)
Controls
5-9
• Duallntensily Video Levels
• SY6545 Programmable CRT Controller for User Definable Screen
Formats
o light Pen Input
o Composite or Separated Video
Outputs
•
0
MBCO 10 CPU Boord
MBC020 CPUjVideo Boord
SPECIFICATIONS
Power Requiremerits
+5 YDC @ 1.5 A (max) MBC010
+5 YDC @ 1.75 A (max) MBC020 .
+12 YDC @ 50 mA (max)
-12YDC@50mA(max)
Bus Signals
ADDRESS BUS: Three-state TTLcompatible buffered outputs
DATA BUS: ffi-compatible buffered
inputs/outputs
CONTROL BUS:
R/W, VMA. VUA: Three-state
ffi-compatible buffered outputs
BA. REF GRANT, MEMCLK, SYNC,
Baud Rate: TTL-compatible
J2.I:lffered outputs
IRQ, NMI, RESET, HALT, REF REQ,
RDY, DMA: TTL-compatible
buffered inputs with .3 ..3K ohm
pull-up resistors
Operating Temperature
ODC to 70 DC
MBC020 DIAGRAM
5-10
Physical Characteristics
Width: 9.75 in.
Height: 6.00 in.
Board Thicl~ness: .0625 in.
Connectors
86 pins:
Stanford Applied Engineering
SAC-4.3 D/1-2
50 pins:.3M type .3415-0001
20 pins: .3M type .3461-0001
/v\O(O 1A2 MOC01 A2··1 Single Boord COfllputer
Motorola Micromodule Replacement
DESCRIPTION
FEATURES
The MBC01A2 board is a direct
replacement for Motorola's
M1J8MM01A2 MICfoinO(ful£l. Additional ROM and IV>M capaci1y has
been added for increased system
requirements~ Up to 4096 bytes of
static IV>M and .32K bytes of ROM
can be utilized on the M~C01A2
Micromodule.
o
The MBC01A2 Micromo9ule includes
a serial communications interface
using the MC6850 and two MC6821
PIA's for parallel interfacing.
Exact Replacement for Motorola
M68MM01 A2 MicromodlJle with
additlonallV>M and ROM
capacity
o
o Four ROM/EPROM/IV>M Socl~ets
for interfacing with 1K-8K ROM's;
1K-4K EPROMs; or compatible 1K
and 2K lV>M's
o EXORcisor™/Micromodule Bus
Compatible
o
Serial Communication Port using
MC6850 ACiA with RS-2.32-C
interface
o Four Parallel Ports using MC6821
PIA 5
o 1 MHz operation (2 MHz available
on special order)
1024 Bytes of Static IV>M with
for up to 4096 Bytes total
Socl~ets
o
Power-On Reset Circuitry
o
Dynamic Memory Refresh
Circuitry
o
Four mating connectors supplied
with M!3C01 A2-1
Mf3C01 A2 M13C01 A2-1 Single f30ard Computer
Motorola Micromodule Replacement
SPECIFICATIONS
Power Requirements with 1K
of RAM and no EPROMs
+5 VDC @ 1.1 A (max)
+12 VDC @ 25 mA (max)
-12VDC@25mA(max)
Bus Signals
ADDRESS BUS: Three-state ITL
compatible buffered outputs
DATA BUS: ITL-compatible buffered
inputs/outputs
CONTROL BUS:
R/W. YMA. YUA: Three-state
ITL-compatible buffered outputs
OTHERS:
ITL compatible
Operating Temperature "
O°C to 70°C
Physical Characteristics
Width: 9.75 in.
Height: 6.00 in.
l30ard Thicl~ness: ~0625 in.
MBC01 A2 DIAGRAM
5-12
Connectors
(supplied with MBC01A2-1 only)
86 pins:
Stanford Applied Engineering
SAC-4.3 D/1-2"
50 pins:.3M type .3415-0001
20 pins:".3M type .3461-0001
DESCRIPTION
FEATURES
SPECIFICATIONS
The MI3C008/MI3C016 Static IWv\
Modules are directly compatible
with Motorola EXORcisor'"/
Micromodule bus. The modules
include address decoding, write protection. and data buffering circuitry.
The M13C008 contains 8K bytes of
read/write memory, implemented
with 16 SY2114 1024 x 4 static IWv\
memory devices, while the M13C016
contains 16K bytes of memory,
implemented with .32 SY2114
devices. Address select switches
allow each 8K memory section to
be independently placed in any 8K
address range. On the MI3C016.
each 8K section can be independently write-protected through the
write-protect lines.
• Two Speed Versions - 500ns
access and 300ns access
Power Requirements
+5 YOC @ 3.5A (max.)
• Two Power Versions - 3.5A max.
and 2.5A max.
Low Power Version:
+5 YOC @ 2.5A (max.)
• M13C016 has 16K bytes of Random Access Memory address in
8K sections
Operating Temperature
o Separate Write-Protect of Each 8K
Section of Memory
• Static - No Clocks or Refresh
Required
• Single +5V Power Supply
Required
oaCto 70 aC
Physical Characteristics
Width:'
9.75 in.
6.00 in.
Height:
Thickness: .0625 in.
Connectors
86 pin - Stanford Applied
Engineering
SAC-43D/1-2
PART NUMBERS
Power
Consumption
5-13
Speed-nsec
500
300
2.5 Amps (Typ.l
M13CO08 MI3C008·3
M13C016 MI3C016·3
1.75AmpsCTyp.l
M13CO08L MI3C008L·3
Ml3C016L MI3C016L-3
-
"-~
Dynamic RAM ~13€c)16D Dynamic ~ ~13€C)4SD
~··D~namic ~ 'fSI\l3€®0!LD:;T1Dyna:rilttJc ~ (B€c)6Z1fD
DESCRIPTION
The Dynamic RAM Boards with
hidden refresh are available in
16K, 32K, 48K, and 64K memory
arrays in either 1 or 2 MHz versions.
Memory refresh is performed onboard during 1 when the processor
is not accessing memory. On-board
circuitry generates and detects
even parity through the use of an
additional memory bit. Whenever a
parity error is detected, a signal is
output to the system which is jumper
selectable as a parity 'error ar nonmasl~able interrupt. The memory
array can be deselected in 4096
byte blocl~ to meet any system
requirements. As with all SSC
Micromodules, the Dynamic RAM "
Boards are directly compotible with
Motorola EXORcisor™/Micromodule
bus.
FEATURES
SPECIFICATIONS
o Available in 16K, 32K, 48K, or
Power Requirements (64K of RAM)
+5 VDC @ 0.7 A (max)
+12 VDC @ .12 A (max.)
-12 VDC.@ 8 mA (max)
64K Memory Arrays
o 1 or 2 MHz V~rsions
• Hidden Refresh (without processor interruption)
• Fully Buffered Address, Data, and
Control Lines
o Any 4K Blocl~ Memory can be
Deselected by Jumpers
• 20 Pin Header for Implementation of Priority Interrupts, MultiPaged Memory, and I/O Systems
• Even Parity Error Checl~ing with
Jumper Selectable Output
o Power saving selective refresh
during 1 of every fourth
processor cycle
Operating Temperature
O°C to +70°C
Physical Characteristics
Width: 9.75 in.
Height: 6.00 in.
Board Thicl~ness: .0625 in.
Connectors
86 pin:
Stanford Applied Engineering,
SAC-43D/1-2 or equivalent
Read Access Time
2 MHz operation 210 ns after leading edge Cif 2
1 MHz operation 350 ns after leading edge of 2
Write Data Available
2 MHz operation 110 ns after leading edge of 2
1 Ml-jz operation 220 ns after leading edge of 2
5-14
MBC081, MBC081-1
DESCRIPTION
MBC091
DESCRIPTION
MBC092, MBC093
DESCRIPTION
The MBC081 EPROM PROGRMVv\ER
provides two EPROM socl~ets for
copying one EPROM to another,
verifying contents of one EPROM
against another, or simultaneous
programming of two EPROMs.
Programs 2716,2532, or 2732
EPROMs.
The MBC091 PROTOlYPING BOARD
plugs directly into the standard'
Micromodule bus and provides
space for prototyping user developed circuits. To aid prototyping,
ground and power buses are provided with locations for decoupling
capacitors;
FEATURES
FEATURES
• Two EPROM Socl~ets, Each Capable of Programming 2716, 2532,
and 2732 EPROMs
o Provides Space for Developing
EXTENDER BOARDS are available in
two versions. The MBC092 is an
extender only, allowing the user
access to all points on the Circuit
board under test. The MBC093, in
addition to its role as an. extender,
also has switches in each line to
allow opening selected .lines
between the board in test and the
bacl~plane bus. Labeled test pOints
are also provided between the
board in test and the bacl~plane bus
for monitoring system signals.
Experimental or Custom Circuits
o Standard Spacing for Wirewrap IC
Socl~ets
o On-Board DC to DC Converter
Provides +25V Regulated Supply
Voltage with Short Circuit
Protection
o Address Switch Selectable in 256
Byte Blocl~s
o
MBC081-1 includes special cable
for installing board in MDT2000
Micro. Development System
FEATURES
o
One 20-Pin and Two 50-Pin Edge
Finger Connectors are Provided at
Top of Board
o
All Wirewrapping Hardware for
Edge Finger Connectors is
Provided
o
Useful forTroubleshooting and
Testing
o Allows Access to All Points on
Circuit Board
o Built-In Test Points and In-Line
Switches
o Interfaces with All MBC Boards
and Micromodules
MOC081
MOC093
MOC091
5-15
MBC51 0
DESCRIPTION
MBC21 0
DESCRIPTION
The MBC21 0 FLOPPY DISK
CONTROLLEIVFOPMAlTER is an intelligent interface between the
Micromodule bus and up to seven .
floppy drives - four 8" drives and
three 5" mini floppies. Sixteen RAM
locations provide a control/status
block for simplified processor independent interfacing to the MBC210.
• Extensive Error/Status Reporting
• Self-Contdined On-Board Disk
Formatting Software
• Data Transfers, Control and Status.
Information Communicated
through On-Board RAM Buffer/
Status Blocl~ Providi.ng Processor
Independent Interface
The MBC51 0 COMBO I/O BOARD
provides three. serial ports using
SY6551 ACiAs with complete
1\5-232-C compatibility and two
parallel ports with buffers and
socl~ets for resistor terminators. The
MBC51 0 also contains four 16-bit
counter/timers to provide several
operating modes.
• Interrupt and/or Status Bit Buffer
FEATURES
Handshal~ing
FEATURES
Address Space Switch Selectable
on 2K Boundaries
• Address Switch Selectable in 256
Byte Blocl~
• Handles up to Four 8" Drives and
Three 5" Mini Floppies
.
o
• Single or Double Sided
• Simple "Daisy Chain" Drive
Connection
• Single or Double Density
• Two 8-Bit Parallel I/O Ports with
Handshal~e using SY6522 VIA s
• Nibble Programmable with ·Buffer
Option
• On-Boord Processor Controller
• IBM Format Compatible
• Expanded Handshal~e Capability
for Positive and Negative Data
Transfer Control
• On-Board Diagnostics
• Socl~ets for Terminators Provided'
• Three Serial Ports using CrystalControlled SY6551 ACIAs
• 16 Programmable Baud Rates
from 50 to 19.2K Baud
• Full RS-232-C Compatibiliiy
MBC210
MBC51 0
5-16
'Mf)]t'~eee
forZ6and
DESCRIPTION
THE MDT 2000 MICRO DEVELOPMENT SYSTEM provides the user
with 0 flexible, powerful, development and emulotion system for
SYl8 and SY6500 series microprocessors. Debugging is facilitated
with in-circuit emulation which
provides a separate and nonconflicting execution environment. Optional Debug mreal~
point/Ttace) boards permit an
execution halt, or real-time trace
events to be qualified by
complex breal~point conditions.
These events can include usersystem status.
Emulation control is achieved with
a screen-oriented Supervisor which
provides various prompting bacl~
ground displays and parameter
toggle fields.
Assembly language source and
object program generation is
supported with a PASCAL-Based
Operating System (PBOS). PBOS
provides a powerful screenoriented editor and floppy disl~ file
FEATURES
manager with user-controlled
operations on file name families
(i.e., wildcords). User-adaptable
CRT terminal and printer configuration utilities are available to
tailor the system to various
terminal and printer characteristics.
A versatile ROM Bootstrap
provides power-up access to RAM
and/or disl~ diagnostics, usercontrolled booting of PBOS, and
an elementary RAM-oriented
debugger for pre-disl~ boot
utilization. Remote Communications software (optional) provides
access to other systems for
terminal interaction or file transfer
(binary/ASCII) with error detection
and recovery capability.
The intelligent floppy disl~ controller maintains a log of soft
(recoverable) disl~ errors for user
request via a PBOS utility. Self-test
of ROM and RAM is automatically
performed at power-up and
system reset time, and the results
are reported.
• Supports both SY6500 and SYl8
Microprocessors
• Supports Up to Three Debug
Cards, Providing Four Breal~point
Registers and Trace
o Intelligent Floppy Dish Controller
with Two 8" Drives
o Three Serial and One Pa~allel
Interfaces
o PASCAL Disl~-Based Operating System with Command Prompting
o Powerful CRT Screen-Oriented
Editor
o Versatile Disl~ File Operations with
"Ignore Character" Selection
o Opfional PASCAL Compiler
o Optional Remote Communications Software
o ROM-Based RAM/Disl~ Diagnostics
and Mini-Debugger
o Supports Disl~ Booting of UserGenerated Operating Systems
o Supports Single or Double Density
8" Data Disl~s
o User Configuration of CRT
Terminal/Printer Attributes
o PASCAL Access to Serial or Parallel
Printer (mutually exclusive)
o
Disl~
File Hexadecimal Patch Utility
o 230 Volt Option Available
o 2K User RAM (Expandable to 4K)
for SYl8 Internal ROM Emulation
Option
• 64K User DynamiC RAM for
SY6500 Emulation Option
o Screen Graphics Control of
Emulation
G>
Optional EPROM Programmer
Board
'" Two Socl~ets for Programming
2716,2732,2532 EPROMs
• Optional Assemblers for 6800,
6809,Z80, 8080, 9900, and
LSI-11
5-17
STANDARD PRODUCT FLOW
Lead Trim
Receiving
Inspection
Wafer Fabrication
Hermeticity Testing
Electrical Wafer Sort
1 st Optical
Inspection for Sort/Fab ......._~..
Defects a.A. Gate
Tin Plate
Saw& Break
Centrifuge
2nd Optical Inspection
2nd Optical
......_ _ _ _ _-1
QAGate
Temp Cycle
Die Attach
oA Die Attach Monitor
Stabilization Bake
Seal
Hermetic
Lead Bond
QA Lead Bond Monitor
For detailed information on Synertek's Quality Program, contact your local Synertek Representative.
6-2
SYNERTEK
A SUBSIDIARY OF HONEYWELL
Visual Inspection
Mark
Electrical Testing to test
conditions and limits
which guarantee AC.
DC and functional
performance.
Trim & Form
Solder Dip
Stabilization Bake
Deflash. Trim & Form
Tin Plate
QA Acceptance
AC. DC F-unctional Tests to guarantee performance
over full specified
temperature
range.
Mold
QA Final
Visual Acceptance
Plastic
Plant Clearance
Precap Visual
Inspection
6-3
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Ordering Information
SY
M
C
2114
3
.------dJ U-----'
l
_L
Prefix
Temperature Range
No Designator - O°C to 70°C
M - -55°C to +125°C
X - Special
E - -40°C to +85°C
Package Type
C - Ceramic
P - Molded
D - Cerdip
X - Dice
F - Flat Pac
T - TO Can
4 Digit Device
Code
3 Digit Performance
or Processing Designator
For specially programmed devices (ROM's, 6530 Combo, etc.) Synertek will assign a special custom
number. This number must be used when ordering these devices.
EXAMPLE: SYP 2316B, C28000: 2048 x 8 Read Only Memory, plastic 24 pin Dip, O°C to +70°C,
bit pattern as defined by C28000.
I
7-2
Packaging Informadon
Plastic Dualln-Line16 Leads
.032 REF
CerDIP16 Leads
r:~~~i ' - [ : : : : ]
0.06011.5241
r
I
:: :::
-++-------11
L
0.780119.8121 MAXJ
·1
I
II
L ~ --Q.~(~llI ~
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Packaging Informadon
Plastic Dual In-line18 Leads
H
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L()901
L06S)
(.0401
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Ceramic Dual In-line18 Leads
~-+- .~
~
1.008)
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13201
1.290)
-.Jl
1.0901
CerDIP18 Leads
0.320
0.290
18.128)
17.366)
I---
0.310
0.260
17.874)
(6.604)
0.900 (22.860) MAX----I
0.060 (1.524),..--.,.-_ _ _ _- - - - - . . - _
0'015(0'381)~~
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0.09012.286) 0.030 (0.762)
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0.125 (3.175)
0.015
0.008
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0.015 (0.381)
7-4
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0.180(4.572)
0.140 13.556)
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___ 0.400 (10.16) _____
0.330 (8.382)
Packaging Information
Plastic Dualln-Line20 Leads
~~~t
:::::::::1
-----
(.145)
(.135)
1
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11
_(.020)
(.010)
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(,260)
(1.040)
(1.020)--
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(.022)
(.012)
(.008)
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tr:::::1
o.320~
0.260
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0.110
0.090
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0.070
0.030
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0.023
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7-5
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Packaging Information
Plastic Duall n-Line24 Leads
Ceramic Dualln-Line- F="-"~~~~~-....==...~=-==tT
24 Leads
1.610)
T.5BoT
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~~~{~~~~~~~~~] .~~
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.090 (2.286) .030 (.762) .015 (.381)
I
.630 (16.002)
i
7-6
Packaging Information
Plastic Dual In-line28 Leads
;,::t'--~::::: :::::::] +
i,
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1.470 MAX
~130
0 . 6 21 0 .
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0.145
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Packaging Informadon
Plastic Dual In-Line40 Leads
ffi
1.1701
.
1.1501
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(.600)
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1.0151
L0081
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Ceramic Dual In-Line40 Leads
Protopack ™ 40 Leads
40
.LC~
MAX
MAX
IJ
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0.1.5
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-.002
Protopack is a trademark of Zilog. Inc.
7-8
Packaging Informadon
Quad In-Line Package (QWIP)64 Leads
1.65 ± .020 _ _'--_ __
f - - - - - - - - ( 4 1.9 ± .508)
r
-
1.00 ±. .020
(25.4 ±. .508)
.060
1~52)
I
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J
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(-'.6-5) MIN.
.040
(1.01) REF.
.385
455
(9.78) (;1.55)
f-m77t'7i?;'7i?;~~P'{1';rnnnl\\\\~..m~~~~"i1
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J (2)
I
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.045 SQ. MIN. TYP 64
(1.14)
.003
DIEPADFLATWI TH IN (.076)
.085 ± .009
(2.16±..:::)
(.635)
I
J:
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-rI rT
.020 X45 0 CHAMFERTYP. 6
~ (.508)
ro~
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0
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IL (1.01)
.040
TYP.
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SYNE.RTEIt
A SUBSIDI ARY O F HO,NEYWElL
Printed in U .S.A.
~
TMP - SD K - 6/81
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:04:05 09:21:52-08:00 Modify Date : 2013:04:05 10:52:27-08:00 Metadata Date : 2013:04:05 10:52:27-08:00 Producer : Adobe Acrobat 9.52 Paper Capture Plug-in Format : application/pdf Document ID : uuid:b94b2fb2-95ab-4c39-9ff1-997c99a138cc Instance ID : uuid:088a2d41-2985-40bd-ac1f-78fb3097e2f3 Page Layout : SinglePage Page Mode : UseNone Page Count : 326EXIF Metadata provided by EXIF.tools