TD 4102_VT3_Theory_of_Operation_Feb82 4102 VT3 Theory Of Operation Feb82
TD-4102_VT3_Theory_of_Operation_Feb82 TD-4102_VT3_Theory_of_Operation_Feb82
User Manual: TD-4102_VT3_Theory_of_Operation_Feb82
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_1_
MOHAWK
::t DATA
••••.
SCIENCES
SERVICE DIVISION
VT3
Theory of Operation
TD-4102
Technical lv1anual
Fl
~F
TH
T PR NT NG: JUNE 1980
NO P IN ING: AUGUST 1981
0 PR NT NG: FEBRUARY 1982
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Y
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Thpnr\/ nf
111'-"'-'1'
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np r;:l t inn
_.-"1'-"-'-1'-'1 •
©
First Printing: June 1980
lp
Qantel Corporation
Table of Contents
•
HARDWARE
Physical Description ....................................... 1-1
Block Diagram Explanation .................................. 1-3
Explanation of the Logic Drawings:
Sheet 1 (Microprocessor and Input Ports) ............. 1-8
Sheet 2 (Program ROM and Utility RAM) ................ I-11
Sheet 3 (Address Counter, MUX, and Display RAM) ...... I-13
Sheet 4 (Horizontal Timing) .......................... 1-15
Sheet 5 (Vertical Timing and Interrupt Control) ...... 1-19
Sheet 6 (Character Generator and CRT Interface) ...... 1-22
Sheet 7 (Baud Rate Generator and UART) ............... 1-25
Sheet 8 (Keyboard Interface and DC Voltage) .......... 1-27
Sheet 9 (Signal and DC Power Distribution) ........... 1-29
Sheet 10 (Transformer and Wiring Diagrams) ........... I-29
PS-9 Power Supply .......................................... 1-30
VT3 Documen ts .............................................. 1-32
IC List ing for the VT3 ..................................... 1-33
•
OPERATIONAL DESCRIPTION
Display Screen ............................................. 11-1
Keyboard ................................................... 11-5
Microcode Summary .......................................... I 1-7
Data Paths and Translation ................................. 11-18
Typewri ter Mode .............
11-19
Kat akana Keyboard .......................................... I 1-20
0
•
• • • • • • • • • • • • • • • • • • • • • • • • • • • •
0
•
CONFIGURATION INFORMATION
Network Types ..........................
Logic Board Jumper Settings ............
0
•••••
0
•••••••••••••
0
•••••••••••••••••••
111-1
111-4
P 1 Co nne c tor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I I I - 6
P2 Connector ............................................... I I 1-7
•
TEST PROCEDURES
Manual Test ................................................ IV-1
Available VT3 Test Programs ................................ IV-3
TABLE OF CONTENTS CONTINUED
• APPENDIX
UART Pin Designations ........................................ V....: 1 '
IC Specifications ............................................ V-4
VT3 Domestic Character Set ................................... V-13
Keyboard Status .............................................. V-14
UART St'atus Register ......................................... V-14
Terminal Information Word .................................... V-14
. VT3 Status Byte .............................................. V~15
Memory and I/O Decoding ...................................... V-16
PS-9 Logic Drawing ........................................ Foldout
VT3 Logic Dra.wings ........................................ Foldouts
•
FIGURE LIST
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
F'igure
1
2
3
4
5
Major Components of the VT3 ...................... I-1
7
8
Block Diagram .................................... 1-4
Horizontal Timing ................................ 1-17
Horizontal Timing ................................ 1-18
Vert ical Timing .................................. 1-20
Interlaced Character Slices ...................... I-24
VT3 Keyboard ..................................... I 1-4
Data Paths and Translation ....................... 11-18
9
10
11
12
13
14
15
16
17
18
Katakana Keyboard ................................ II-19
Data Conversion for Storage ...................... II-21
Katakana Character Set ........................... 11-22
Direct String Network ............................ III-1
Hub Unit Network ................................. 111-2
Remote Network ................................... III-3
Jumper Placement ................................. 111-4
VT3 Pedestal Back Panel .......................... III-5
Control Logic Board: P1 ............
111-6
Control Logic Board: P2 .......................... I I 1-7
6
-
w
ii
•••••••••••••
Hardware
PHYSICAL DESCRIPTION
The various components of the Qantel Video Terminal 3 reside
within three separate enclosures: the display cabinet, the pedestal base, and the keyboard.
play cabinet are the
Z-8~
Within the fully pivoting dis-
based control logic board and the
CRT with its monitor board.
The supporting pedestal base con-
tains the PS-9, a standard linear power supply providing the
DC voltages for VT3 operation.
The keyboard, with interchange-
able key tops to match different character sets, contains a
single board featuring a small speaker (for the alarm).
Three
variations of character sets are available - domestic, Swedish,
and Japanese.
Other sets are planned for the future.
il II II
IIIIII I
II I I I I
II II
1 11 11 / . /.
VT3 CONTROL
LOGIC BOARD
II I I I
!
I
.
I
.I
1/
/
I 1/ / / /
'I
II
,1// 1 .
1/111
1/1/
/1/
IIII
IIIII
/
11//1/
111/
.
.
DISPLAY
CABI N ET -----II~:
I
Jill/III
'111111
IIII
II II II I
1/ /1 I I
IIIII
II
I I .,
!/
/1
MONITOR
BOARD
DETACHABLE
KEYBOARD
PS-9 POWER SUPPL
TRANSFORMER
PEDESTAL BASE
and
INPUT VOLTAGE
TERMINAL STRI P
Fig. 1
1-1
PHYSICAL DESCRIPTION CONTINUED
Convection cooling is used in each of these enclosures to
maintain normal operating temperatures.
External controls are minimal; the back of the pedestal features
an on-off switch and brightness control.
The J6 and J7 con-
nectors, also on the back panel, permit system interfacing and
daisy-chaining of additional VT3's.
tachable.
The AC power cable is de-
The main power fuse, rated at 1 amp, 250 volts, is
also located on this back panel.
Switch settings provided within the display cabinet condition
the VT3 for variables in operation.
The control logic board
allows switch setting of asynchronous communication speeds
ranging from 300 bps to 19,200 bps; 50 Hz or 60 Hz operation;
individual VT3 address within the communication network; and
initial display screen parameters (27 lines of 64 characters
or 24 lines of 80 characters).
Input voltages can be matched to transformer capabilities by
means of a ten-position terminal strip connecting with the
primary windings of the transformer.
Thus, operation is pos-
sible with input voltages of 100, 115, 215, 230, and 240 VAC.
A maximum of thirty-one VT3's may be configured off a single
controller through direct connection, hub units, line drivers,
and modems.
The IOU-39Q performs the role of controller in
conjunction with the VT3.
1-2
BLOCK DIAGRAM EXPLANATION
The block diagram illustrates the components of the control
logic board in relation to the keyboard, the communications
line, and the CRT.
The basic operations, as dictated by the
instructions in the Program ROM, are carried out by the
microprocessor.
The
Z-8~
Z-8~
must continually update the Display
RAM with character information derived from the keyboard and
central processor.
Each character space on the CRT display
screen is represented by a memory location within the Display
RAM.
By actively monitoring the communications line through
the UART (Universal Asynchronous Receiver-Transmitter), and
the keyboard interface, and loading arriving characters into
the RAM, the
Z-8~
is able to ensure the display screen pre-
sentation is current within the realm of system program activities.
The
Z-8~
microprocessor directs data on the 8-bit DB bus by
selectively enabling the appropriate components upon the control logic board.
The 16-bit AD (Address) bus carries this
directional information to one of the following (depending
on the address value):
• A decoder network which provides chip select signals
to activate specific components.
• The address inputs of the Program ROM or Private
Utility RAM.
• The Address circuitry for the Display RAM, tied into
the CRT's video timing network through a Character
Counter and Multiplexer.
The timing network is designed to allow the Z-89 access to the
Display RAM during a brief period between individual character
accessing by the scan circuitry.
Access is available as well
during the horizontal and vertical blanking periods.
1-3
BLOCK DIAGRAM EXPLANATION CONTINUED
DECODER
NETWORK
CHIP SelECT
Z-80
MICRO
PROCESSOR
INTERNAL
STA TUS
BUFFER
SERIAL
I ~iE-R~~iE
~--:.._ _. .
Z-8~
Fig. 2
INTERFACE
clock periods are regulated by a 4.0 Megahertz oscillator.
This results in a 0.25 microsecond duration for each T-state.
The Decoder Network generates chip select signals based on inZ-8~
formation the
provides along the AD bus and certain control
lines (MREQ, MaNE, and IORQ).
As illustrated on Sheet 7 of the
logic drawings, two high-speed 1-of-8 Decoder chips handle selection of memory
(CSC~
- CSC7).
(CSA~
- CSA5) and selection of I/O ports
The specific chip select information is pre-
sented in the Appendix of this manual.
The Program ROM contains 6K bytes of microcode used to structure the activities of the
of the VT3.
Z-8~
in performing basic operations
Three 2K by 8 bit memory chips are used, selected
or CSA1 and address lines
AD1~
and ADll.
The Utility RAM acts as a storage area for the
Z-8~
for pro-
by chip selects
CSA~
gram variables and scratchpad space during various program sequences.
It consists of four lK by 4 bit memory chips accessed
I-4
BLOCK DIAGRAM EXPLANATION CONTINUED
in pairs for a total memory area of 2K by 8 bits.
The Internal Status Buffer is a tri-state buffer (7B seen on
Sheet 1 of the logic drawings) which, when enabled, can supply
the
Z-8~
with the following information: selected VT3 address
as represented by jumpers J8 through J12; presence of the DRV+
signal and ODDCT+, both indicative of key aspects of video
timing; and the 60HZ signal, showing the condition of jumper
J14 - the 50 or 60 Hz switch.
The Character Counter supplies the address to the Display RAM
for accessing a particular location, akin to a position on the
CRT display screen.
Consisting of three 4-bit presettable
counters, the Character Counter is loaded by the
the appropriate address to start each row.
Z-8~
with
The counter is in-
cremented throughout the horizontal scan automatically.
Z-8~
The
may bypass addressing the Display RAM through the Charac-
ter Counter, addressing instead directly through the Multiplexer.
When a specific signal is present as a result of
timing considerations (SMEN-), the
Z-8~
can use this mode of
addressing.
The Multiplexer, three Quad 2-Input Data Selector/Multiplexer
chips, feeds the inputs to the Display RAM chips with addresses from either the Character Counter or directly off the
Z-8~'s
AD bus.
The Display RAM consists of four lK x 4 bit memory chips accessed in pairs to create a 2K by 8 bit display memory.
Char-
acters encoded in ASCII values
represent a one-to-one relationship with the CRT display
screen.
A timing signal releases accessed characters to the
1-5
BLOCK DIAGRAM EXPLANATION CONTINUED
DS bus (Display Bus) where the ASCII value is applied to a
Character ROM to produce the correct dot matrix pattern.
A
pair of octal latches, one for input and the other for output,
act as a buffer between the Display RAM and the DA bus.
The Character Generator, 16K of ROM, receives the 8-bit ASCII
value from the DS bus and produces a portion of the dot pattern,
one slice of the matrix, based on the horizontal scan row information received from a line counter.
The line counter con-
sists of a Dual-D flip-flop and 4-Bit Synchronous Counter that
maintains count of the slice of a particular character being
produced, one row of a possible fifteen.
During the course of
each horizontal scan row, eight slices of a character are assembled (all even or all odd lines).
The interlaced scan re-
turns after finishing the rest of the frame and inserts the
slices that were missed the first time.
The Shift Register (Parallel In - Serial Out/Serial In Serial Out 8-Bit Shift Register) accepts a parallel byte from
the Character Generator and shifts it out serially to form the
video signal sent directly to the CRT.
A LOAD+ signal genera-
ted as a part of the horizontal timing controls the rate of
the video signal.
The Horizontal and Vertical Timing circuitry is based on the
clock signal sent from an 11.25 MHz oscillator.
The result-
ing signals are used to control access of the Display RAM,
clock the shift register, produce specific interrupts to the
Z-8~,
create the horizontal and vertical inputs to the video
monitor board, produce the blanking signals, and generate the
odd-even interlace flag.
1-6
BLOCK DIAGRAM EXPLANATION CONTINUED
The Keyboard Interface allows the
Z-8~
through a tri-state
buffer to receive incoming strobe signals from the keyboard,
detect the New Key Pressed flag, and receive serial bits from
the keyboard on the DKEY+ data line.
clocked by the
board.
The
Z-8~
Z-8~
Incoming data bits are
sending out the signal CLOCK+ to the key-
may also sound the alarm, the keyboard audio
signal, by setting the Alarm Latch.
The UART (Universal Asynchronous Receiver-Transmitter) provides
the link to the RS-232 serial communication line, directly interfacing the UART of the managing IOU-39Q controller.
Z-8~
The
monitors the state of the UART to detect the Data Ready
condition (indicating incoming data) or Transmit Holding Register Empty (allowing the
Z-8~
to transmit data).
1-7
EXPLANATION OF THE LOGIC DRAWINGS - SHEET 1
MICROPROCESSOR AND INPDT PORTS
In the upper lefthand corner of Sheet 1, the IC chip 6C, a
4.00 MHz clock oscillator, provides the
Z-8~
with a square-
wave clock input resulting in a basic T-state period of 0.25
microseconds.
The diode-clamped driver network provides edge-
shaping and voltage control for the clock signal to meet
Z-8~
~equirements
The
(necessary at higher frequency operation).
4 MHz signal also is routed to a timing network to control the
DART's baud rate.
The RC network located at A8 on the sheet remains low for 50
microseconds after power up to reset the
Z-8~
microprocessor
and the DART.
The connector P2, shown at the far left and right of the sheet,
allows access to the
Z-8~
control, data, and address lines
through test panel interface.
The
Z-8~,
operating according to the microprogram stored in
the 6K ROM, must coordinate tasks on two levels.
Data and
control characters must be received and properly channeled as
they arrive from the DART and the keyboard.
The functions re-
quired to accomplish this may be thought of as a foreground
operation.
freshed.
Also, the display screen must be continually reThe
Z-8~
performs this as a background level task
by generating addresses and timing control signals at regular
intervals.
1-8
MICROPROCESSOR AND INPUT PORTS CONTINUED
The Interrupt line (INT-) is used to notify the Z-8~ of the
conclusion of a horizontal scan, vertical scan, or act as a
prompt for the
Z-8~
to check communications line activity
through the UART. The method by which these interrupts are
generated is discussed further on the sheets on which they
originate (see Sheets 4 and 5).
The WAIT line when activated produces a condition within the
Z-8~
suspending all operations until the line goes inactive.
WAIT in this case is used to prevent the Z-8~ from accessing
the Display RAM during certain periods of the memory access
cycle.
The 8-bit Data Bus,
DA~
through DA7, links the
Z-8~
significant components of the control logic board.
to the
Refer to
the block diagram on page 1-4 for an overview of which components
are interfaced.
Tri-state buffer 7B ~s used by the Z-8~ by activating Chip
Select CSC5 to obtain the following information. DRV+ (the
Vertical Drive signal) when absent indicates the presence of
the vertical blanking period. ODDCT+, a product of the vertical timing network, differentiates between the odd and even
scan as dictated by the interlace pattern.
60Hz- denotes the
presence of jumper J14, necessary for operation with 60Hz power
input.
(Jumper J14 removed conditions the timing for 50Hz
operation.)
Jumpers J8-J12 are used to select the address for the video
terminal within a terminal network:
The address $lF may not be
used as it is reserved for broadcast messages (to all terminals
simultaneously). The Z-8~ thus derives the terminal identity
by reading the state of these jumpers.
1-9
MICROPROCESSOR AND INPUT PORTS CONTINUED
Tri-state buffer 7A allows the
Z-8~
upon sensing an Interrupt
to determine the nature of the Interrupt (Scan Interrupt or
Timer Interrupt).
The
Z-8~
reacts to its INT line being pulled
by issuing active IORQ and MI.
These signals ANDed create
INTAK (Interrupt Acknowledge) which clocks Buffer 7A, loading
restart vector at its inputs.
This restart vector will be an
$FF if the signal INTS+ is present (a timing indication that a
Scan Interrupt is occuring).
The absence of INTS+ result in
$CF, denoting a Timer Interrupt.
1-10
EXPLANATION OF THE LOGIC DRAWINGS - SHEET 2
PROGRAM ROM AND UTILITY RAM
Three 2716 programmable read only memory chips store the microprogram for the Z-89, providing a maximum of 6K bytes (by 8-bit)
storage area.
Address lines
AD~
through
AD1~
from the
Z-8~
interface the address inputs of the chips.
AD11 in combination with chip select signals
CSA~
and CSA1
select the individual IC for the chosen portion of memory.
CSA~,
when AD11 is low, selects Ie i1A.
when AD11 is high at the same time as
addresses
$~~~~
through
AD11 selects lC 13A.
$~FFF.
IC 12A is accessed
CSA~.
This covers memory
CSA1 in combination with a low
This begins memory addressing at
$1~~~.
Although only 6K of ROM is currently used, space is allotted
so that the addition of another memory IC would expand addressing through $lFFF.
The decoding that produces
CSA~
and CSAl
can be seen on Sheet 7 of the logic drawings.
Microinstructions are drawn from ROM (via the 8-bit DA bus)
during an instruction fetch cycle preceding each
tion.
The microprogram as executed by the
Z-8~
Z-8~
opera-
is examined
in the Operational Description segment of this manual.
The four 2114 random access memory chips shown on the right
half of the sheet represent the Utility RAM.
Each memory IC
has a capacity of lKx4 bits; they are accessed in pairs to
produce a total RAM storage area of 2K by 8 bits.
Pins 11,
12, 13, 14 offer bidirectional data inputs and outputs, interfacing with the DA bus.
The signal CSA4 selects RAM chips 11B and 12B.
lOB and 13B.
CSA5 selects
Pin 10 acts as the Write Enable, activated by
the Z-89 (by the signal WR) whenever data is to be loaded into
the RAM.
Each chip select signal provides 1K (1024 bytes) of
1-11
PROGRAM ROM AND UTILITY RAM CONTINUED
storage area; CSA4 from
$4~~~
to $43FF and CSA5 from
$5~~~
to
$53FF.
The Utility RAM allows the
Z-8~
a "scratchpad" area to mani-
pulate program variables, maintain flags, keep track of counts
during transfer operations, and provide buffer space for transmit and receive handling.
Qantel document #L30786, the micro-
code listing, describes labels associated with the various
Utility RAM addresses.
1-12
EXPLANATION OF THE LOGIC DRAWINGS - SHEET 3
ADDRESS COUNTER, MUX, and DISPLAY RAM
The Display RAM stores characters in a one-to-one ratio corresponding with the characters to appear on the video screen.
The
scan logic circuitry accesses these characters in a manner synchronized to the horizontal and vertical timing signals; the
Z-8~
need only intervene to provide a starting address at the
advent of each horizontal scan row.
The character information
in the Display RAM is updated by the Z-89} during "window periods",
times when the scan logic is not actively accessing Display RAM
or during free time at horizontal or vertical retrace intervals.
LOAD+, a signal originating in the horizontal timing network,
acts as a clock for IC
l~F,
an Octal D flip-flop, storing the
data outputs of the Display RAM in preparation for sending the
character data out on the Display Bus to be converted to an appropriate dot pattern on the screen.
LOAD+ will vary in fre-
quency (see Sheet 4) depending on whether a 64 or 80 character
line is being employed.
This coordinates character generation
with the fixed time of the electron beam scan across the screen
to accomodate the number of characters per line.
The Address Counter consists of three 74LS193 chips, asynchronously parallel-loading 4-bit up-down counters.
Timing hardware
generates a maskable interrupt before each horizontal or vertical
retrace.
Within the microcode, the scan interrupt routine ac-
cesses a table to acquire an address which is parallel-loaded
into the counters.
CSA3-, a signal produced by decoding ad-
dress lines AD12+, AD13+, AD14+,
and AD15+, is generated when-
ever the Z-89} produces an address between
$38~~
$39}9~
to $37FF or
(to create a blank scan row) and triggers the parallel-
loading.
sults in
Note that outputting
$~~~
$38~~
on the address lines re-
being loaded into the counters.
1-13
Actual Display
ADDRESS COUNTER, MUX and DISPLAY RAM CONTINUED
RAM addresses range between
$2~~~
and $27FF.
Once the 4-bit
counters are loaded, they increment automatically, clocked
by the LOAD- signal, thus stepping through each address of
the horizontal row a character at a time.
BLANK+, present
during blanking intervals, inhibits clocking at AND-gate 7D.
'The signal SMEN-, Scan Memory Enable, controls the Select pin
of multiplexers 13D, 12D and 11D.
This determines whether
addressing to the Display RAM will be gated through directly
off the Address lines or through the 4-bit counters.
When
SMEN- is active (low), during execution of scan logic, the
Address Counter outputs are gated through.
allows the
Z-8~
SMEN- going true
to directly address any location in the Dis-
play RAM.
The
Z-8~
$2~~~
directly addressing the Display RAM, using addresses
to $27FF, creates the decoded signal CSA2-.
CSA2- sets
a flip-flop (5D) in the horizontal timing network to activate
the WAIT line to the
Z-8~
inputs to the faster
Z-8~).
timing.
(synchronizing the slow RAM memory
WRE+ is then produced by horizontal
WRE+ and SMEN- dictate the period of the "window" dur-
ing which the
Z-8~
can write to the RAM.
combined with WR- (from the
Z-8~)
the DA bus into Octal Latch 13F.
At the same time CSA2-
are ANDed to latch data from
The output is enabled through
this latch to the Display RAM (by pin 1 - the output enable pulled active by the WRE+ signal).
A READ of the Display RAM
can be accomplished in similar fashion by the
Z-8~
activating
the RD- line rather than WR-, thus enabling Octal Latch 12F,
gating Display RAM output lines to the DA bus for reading by
the
Z-8~.
1-14
EXPLANATION OF THE LOGIC DRAWINGS - SHEET 4
HORIZONTAL TIMING
All video operation depends on the synchronizing of a dot pattern, produced by the character generator network, with the
movement of an electron beam across the face of the video monitor.
Thus, the horizontal timing must not only send out a hori-
zontal drive signal to the video monitor and a similarly derived vertical drive signal; but must tell the control logic
hardware when characters are to be loaded, what the dot clock
rate should be, when Scan and Timer Interrupts should occur,
when the
Z-8~
is clear to load new data into the Display RAM
without interfering with Scan Logic, and where blanking periods
should take place.
The scanning rate of the video screen electron beam is constant
for a given input voltage to the VT3.
Obviously, if 80 charac-
ters are going to be compressed into a horizontal row rather
than 64 characters, the dot clock must operate at a faster frequency and the LOAD+ signal, which draws characters out of
Display RAM, must be faster.
This is the purpose of flip-flop
3F - to select one of two crystal oscillators to regulate timing of these factors.
The
Port
Z-8~
$8~.
flop 3F.
activates
CSC~
by performing an I/O function to I/O
Outputting, DA4+ high, when
CSC~
clocks sets flip-
The Q output will thus be high allowing AND-gate 1F·
to channel the upper crystal oscillator output (lE) through to
the horizontal timing network.
therefore, become 11.25 MHz.
The CLST (dot clock) will,
The Q output also goes to 74LS161,
a parallel-loading 4-bit counter, presetting it to $C.
This
adapts the rest of the timing chain to the requirements of a
64 character per line screen format.
1-15
HORIZONTAL TIMING CONTINUED
TINT- and SINT- are routed to the clock inputs of two flip-flops
seen on Sheet 5, used to regulate the intervals that the Timer
Interrupt and the Scan Interrrupt occur.
TINT- is generated
every 32 microseconds, but the actual Interrupt to the
Z-8~
occurs less frequently as controlled by the data input pin 2
of flip-flop 2C (see Sheet 5).
Interrupt to the
Z-8~
SINT- invariably results in an
each 64 microseconds (the data input at
pin 12 of 2C is held low).
CTH+ (Count Horizontal) produces a positive-going pulse for
each horizontal raster row (15.625 KHz) and provides the primary clock for the vertical timing chain.
The BLH- (Horizontal Blanking) and DRH+ (Horizontal Drive) signals are created by 4-bit counter 2F.
As the pin 15 carry-out
of counter 4F goes low, counter 2F is clocked.
When counter
2E carry out is active, counter 2F is preset to $8, counts to
$F causing the carry-out at pin 15 to load a preset value of
$4.
By a count of $5, CTH+ goes inactive and disables counter
2F.
Horizontal Blanking (BLH-) occurs at pin 12, Horizontal
Drive at pin 11.
See the timing chart, figure
,for details.
If an 80 character per line format is selected, by the
pulling DA4+ low with
CSC~,
the bottom oscillator, 1D, is
channeled through AND-gate 1F.
comes 14.0625 MHz.
Z-8~
The dot clock in this case be-
LOAD+ occurs at a faster rate and counter
4F is preset with a $B, thus changing the timing relationship
of the rest of the chain to ensure that BLH-, DRH+, and CTH+
are the same as with 64 C.P.L. format.
1-16
HORIZONTAL TIMING CONTINUED
@
pin15
@
pin 15
pin
®
®
©
2F
-I
--tr
n
r-
8~
pin 14
5:
I
BLANK HORIZONTAL
I
@
@
rL
15
12.8}"SEC
n
I-
25.6JLSEC
..
Fig. 3
HORIZONTAL DRIVE
64. Of"'SEC - - - - -.......~I
HORIZONTAL
TIMING
CSA2-, seen at the top of the sheet, is activated whenever the
Z-8~
RAM).
tries to access address
$2~~~
The factors allowing the
through $27FF (the Display
Z-8~
to access the Display
RAM are as follows.
SMEN- must be inactive - the output of flip-flop 5E pin 8 high.
WAIT+ is set in response to CSA2- and flip-flop 5D pin 8 going
low as that flip-flop is set.
WAIT+ being active removes the
reset to Pin 1 of flip-flop 5D which then can set at a positive
clock from 5E pin 9.
duces the WRE+ signal.
The ANDing of 5D pin 6 and 5E pin 5 proWRE+ routes data into (or out of) the
Display RAM through the appropriate Octal Latch to the address
1-17
HORIZONTAL TIMING CONTINUED
multiplexed off the Address lines (as permitted by SMEN- high).
Pin 6 of flip-flop 5D will go high as the timing chain continues, thus clocking 5D pin 8 to a reset condition.
The re-
sulting high from pin 8 removes the WAIT+ condition to the
Z-8~.
CSA2- will be dropped, once again setting flip-flop 5D
pin 9.
[640 or 800
nanosecond~
, O N E CHARAC.TER
TlME~
:7
ClS~.
~~
~~
~n,-
_______. . n,-;
. W
________ W
_________
--Jn~;
~
~
"'::===i
~~~\--------~
\:~r-'
~------------~--~
,~.
~ ~:i-i
_________---;-_________________
I @j{bMft:fM:
-----I
WRE~:i_:-----------------;---___________-+~
CSA2~!
~~~~~~.~~~.~~_ _ _ _ _~---_ _~@~W%~%~;~~~
WAIT~;~-----....t<:~~~~""~~:
~~~~
SMEN~i
r--
,
I.....-_ _ _ _.....
lOAD+--~:--------~~~---------LJ
HORIZONTAL
Fig. 4
1-18
TIMING
U--
EXPLANATION OF THE LOGIC DRAWINGS - SHEET 5
VERTICAL TIMING AND INTERRUPT CONTROL
The signal CTH+, derived from the horizontal timing chain and
oscillating at 15,625 Hertz, is the basis for all vertical
timing chain activity.
CTH+ clocks the 4-bit counter 4E.
The value preset into 4E is dependent on the state of jumper
J14, the 50 or 60 Hz select, seen in the upper left of the
sheet.
The IL- (Initial Load) signal is also a component of
the preset to 4E, occurring once for the first horizontal
scan frame.
Notice that the signal 60Hz is accessible to the
Z-8~
(see
Sheet 1) through Tri-State Buffer 7B.
Thus, the three primary elements of the vertical timing network, 4-bit counters 4D and 4E, and flip-flop 6F, tailor the
vertical drive signal to the monitor, DRV+, by counting a
specific number of horizontal scans to fit within the frame
rate.
With 60Hz selected (the timer counts 59.98 Hz at this
rate), 260.5 horizontal scans appear per 1 frame.
312.5 horizontal scans appear per frame.
At 50Hz,
The vertical timing
diagram, figure 5 , illustrates the relationship of these
signals.
ODDCT- (Odd Count) is produced to mark the sequence of the
interface pattern sent to the video screen.
A complete
fram~
requires two complete Vertical Drives, one to display the even
horizontal scan rows; one to display the odd.
ODDCT- is
directed to the slice counter, 4-bit counter 9E on Sheet 6,
and becomes a part of the address to the Character ROM to
select an odd or an even slice.
The reciprocal of this sig-
nal, ODDCT+, is sent to Tri-State Buffer 7B (seen on Sheet 1)
to cue the
Z-8~
to whether an odd or an even scan is in pro-
gress.
1-19
VERTICAL TIMING AND INTERRUPT CONTROL CONTINUED
The signals BLANK+ and BLANK- are created to inhibit the video
output to the monitor during horizontal retrace or vertical
retrace periods.
Notice that BLH- (Blanking Horizontal) and
the complement to the Drive Vertical signal (4C pin 9) are
ORed at 3C to ensure the video is inhibited in both instances.
BLANK+ is routed to the Scan RAM Address Counter to prevent
counting during blanking periods.
BLANK- is sent to the
Character Generator network (Sheet 6) as the actual video
inhibit signal.
At periodic intervals in the timing cycle, two maskable interrupts to the
Z-8~
occur.
Flip-flop 2C regulates the incidence
and the nature (timer or scan interrupt) of these interrupts.
The Scan Interrupt has a higher priority - the
Z-8~
must be
notified at the end of each horizontal scan to load an address
for the next scan row.
A Scan Interrupt occurs every 64
microseconds - before each horizontal and vertical retrace.
SINT- (Scan Interrupt) from the horizontal timing network or
the Vertical Drive Flip-flop (4C pin 9) clock 2C pin 9 low
to generate the signal INTSD+ to the
which simultaneously
Z-8~,
sets 2C pin 8 high identifying it as a Scan Interrupt.
A Timer Interrupt occurs less frequently, roughly every 256
microseconds, and is a cue for the
Z-8~
Z-8~
transmit or receive activity.
to check the UART for
Interrupts are enabled
as soon as a Timer Interrupt is recognized to allow the higher
priority Scan Interrupt to take place if necessary.
The
clock for Timer Interrupt also comes from Horizontal Timing
at the rate of once per 32 microseconds.
However, notice
the origin of the data input, 2C pin 2.
The signal CTH- and
the B output of counter 4E are
A~~ed
1-20
at 3C.
Since 4E counts
VERTICAL TIMING AND INTERRUPT CONTROL CONTINUED
intervals which vary according to its preset value, the data
input 2C pin 2 will be active at varying intervals ranging
from 64 to 320 microseconds.
Identity of a Timer Interrupt
is based on the fact 2C pin 8 will be low.
The
Z-8~
responds
to its Interrupt line being pulled by checking Tri-State
Buffer 7B.
The INTS+ line will create a value of $FF for
Scan Interrupt; $CF for a Timer Interrupt.
The
Z-8~
issues
INTAK to read the buffer; the inversion of this signal sets
both sides of 2C, clearing INTSD+.
(6F
pin 6 ___
®--pin
14-....;.:----.----.
®--13- .......---.----,
@--15--Sl--------------..!1L..·--------------J!1L.....:---
~L------~~·----------------~U~~:--------------~U~.-----pin5_--.J~~------------~ _ _ _ _ _ _ _ _ _ _ _ _ _S - - - -
(
'4C
~r-:[QQQQ],...."D-D-::-C---,T
. .
n:
pin l __ JlL-:i---------------~-----------.......I
3E
::~~::~4·E5u. 1-·
33.344 m
SEC
L....:'--_ _ __
-I .
@RV~~L....:-------------------'rlL....:-----------~rlL.....:______
~C
pin9-L...J
LJ
VERTICAL TIMING
Fig. 5
1-21
LJ
EXPLANATION OF THE LOGIC DRAWINGS - SHEET 6
CHARACTER GENERATOR AND CRT INTERFACE
The ASCII values from the Display RAM are converted to dot
patterns synchronized with the horizontal and vertical timing
signals.
The Character ROM, 9F, receives the ASCII value on
the Display Bus and raster row orientation from the Slice
Counter 9E.
The resulting 8-bit "slice" of visual character
information is loaded into a shift register in parallel form,
and shifted out serially at the Dot Clock rate.
The ninth
bit of the slice comes from the DS pin input (pin 1).
To maintain a valid raster row address, Slice Counter 9E receives the signals DRV+ (Vertical Drive), ODDCT- (Odd Count),
and DRH+ (Horizontal Drive).
The Slice Counter is preset to
1 initially, but the outputs are wired to the Character ROM
address inputs in a manner to simulate counting by two's.
DRV+ clocks the value of ODDCT- into flip-flop 4E, thus
resulting in an $8 being loaded into counter 9E for the first
scan of every other frame.
The Slice Counter appears to count
by two's because of the configuration of its outputs with the
Character ROM address inputs.
9E pin 11 (D output) connects
with the low order ROM address input.
Pins 14, 13, 12 (A,
B, C) of 9E connect with the next significant address inputs.
This causes the interlacing of the alternate line to occur.
With a $1 preset into it, the Slice Counter will present
a '2' to the address inputs.
The next horizontal slice,
triggered by DRH+, clocks the Slice Counter to '4'.
Counting
continues ... 6, 8, A, C, E ... until the completion of one
character row triggers the loading of a '2' to start a fresh
character row.
With flip-flop 8E changing with the next DRV+
clock, the Slice Counter receives an '8' preset value and proceeds to count the odd lines ... 1, 3, 5, 7, 9, B, D, F of each
character row.
1-22
CHARACTER GENERATOR AND CRT INTERFACE CONTINUED
Shift register BF loads an B-bit parallel "dot pattern" each
time it receives a LOAD+ signal from the horizontal timing
network.
Additionally, the bit in the eighth position is
serially loaded into pin 1, the DS input, where it becomes
the first bit in the stream to be serially clocked out.
Thus, dots in the first and ninth position of each character
slice will be identically displayed.
Two signals ORed provide the data input to the Inverse Video
Flip-Flop.
DS7+, the uppermost bit of the character informa-
tion word, is one of these signals.
The other is derived
from the A, B, and C outputs of the Slice Counter, ANDed at
2D so that a count of 14 or 15 produces the active low output.
The inverse video function is a result of a high 'not Q' output from 8E applied to exclusive-OR gate 7F.
This effectively
inverts the video signal, turning highs to lows and lows to
highs.
The CRT's video brightness is adjusted by R24, the potentiometer at the rear of the pedestal base.
Flip-flop 6F is set by the
Z-8~
accessing memory location
$38XX (creating the decoded CSA3+ clock and making data input
AD11+ high).
This flip-flop controls blanking, a low from
pin B inhibits all video signals to the monitor.
The signal
BLANK- from the Vertical Timing network also inhibits the
video during horizontal and vertical retrace times.
Junction P1 illustrates the interface with the video monitor
circuitry.
The monitor converts the DRHC+ and DRVC- signals
into sawtooth waves driving the yokes to regulate the motion
of the CRT's electron beam.
The video signal determines
1-23
CHARACTER GENERATOR AND CRT INTERFACE CONTINUED
which dot positions will be illuminated during scanning to
produce the displayed characters and graphics.
INTERLACED
ODD SLICES
1-000000000
-000000000
3-0.00000.0
-000000000
5-00.000.00
-000000000
7-0000.0000
-000000000
9-0000.0000
-000000000
11-0000.0000
-000000000
13-000000000
-000000000
15-000000000
CHARACTER
SLICES
CHARACTER
AS DISPLAYED
EVEN SLICES
~OOOOOOOO
2-000000000
-000000000
4~.00000.0
-000000000
6-000.0.000
-000000000
8-0000.0000
-000000000
10-0000.0000
-000000000
12-000000000
-000000000
14-000000000
-000000000
Fig. 6
1-24
1--000000000
2-000000000
3-0.00000.0
4-D.00000.0
5-00.000.00
6-000.0.000
7-0000.0000
8-0000.0000
9-0000.0000
10-0000.0000
11-0000.0000
12-000000000
13-000000000
14-000000000
15-000000000
EXPLANATION OF THE LOGIC DRAWINGS - SHEET 7
BAUD RATE GENERATOR AND UART
The UART (Universal Asynchronous Receiver-Transmitter) links
the VT3 to the serial communications line, interfacing an
IOU-39Q controller which contains an identical UART at its
communication line junction.
At turn on, the RESET+ pulse
activates the UART's Master Reset.
The microprogram then
dictates the parameters of UART operation by sending out a
control word selecting number of data bits and type of parity
to be used.
It is through the UART that the
cation line activity.
tion, the
Z-S~
register.
Z-S~
By issuing an
becomes aware of communiIN9~
Input/Output instruc-
receives the contents of the UART's status
Information conveyed includes presence of data in
the Receive Register (Service Request), Transmit Holding
Register cleared (Ready for Transmitting Data), Transmit
Register empty (Data Transmitted), Clear to Send, and error
notification.
status word.
See the Appendix for the actual bit map of this
An
IN9~
also cues the
Z-8~
to the state of the
64 / 80 character per line jumper (J13) by enabling the buffer
5A on Sheet S.
The baud rate is selectable through the group of jumpers J1
J7 in the lower left portion of the sheet.
The 4MHz clock
signal ,channelled into 4-bit counter 6D's clock input produces
a Pin 15 Carryout frequency of 307.7 KHz.
Since the UART
clock input responds with one receiver shift pulse for every
16 received cycles, this corresponds to a baud rate of i9.2K.
For lower baud rates, the selection of J2 - J7 connects the
outputs of 12-bit ripple counter 7C to the UART's clock
input.
Within the BS grid on the sheet, the interface with the
1-25
BAUD RATE GENERATOR AND UART CONTINUED
conwunication lines at connector P1 is shown.
Incoming data
at RS-232-C levels (+12, -12 volts) is translated to TTL
levels (+5, 0 volts) by the circuit surrounding comparator
2B.
The data is then serially shifted into the UART's
Receive Register utilizing the predetermined format of stop
bits, character length, parity, and baud rate.
Data being
transmitted out the UART's Transmit Register undergoes the
reverse of this operation.
TTL levels from Pin 25 of the
UART are translated to RS-232-C levels by the comparator
circuit and channelled to the communication line through Pin
9 of connector Pl.
The Appendix contains a list of pin descriptions further detailing UART operation.
Two octal decoders, 9C and 10C, using 8 address lines and 4
Z-8~
control lines, create the chip select signals to steer
addresses and data to proper destinations on the control logic
board.
selects.
The following diagram details the nature of the chip
Note that Decoder 10C is used for memory decoding;
Decoder 9C is used for input/output decoding.
1-26
EXPLANATION OF THE LOGIC DRAWINGS - SHEET 8
KEYBOARD INTERFACE AND DC VOLTAGE
The Tri-State Buffer 5A has two individual sections consisting of four input-outputs.
chip selects, the
Z-8~
By activating one of the two
accesses the desired lines obtaining
information about keyboard activities (CSC6-) or status of
the UART (CSC1-).
The top portion of the buffer, as illustrated, allows the
Z-8~
to read the New Key Pressed Latch (3A), the STROBE+
signal, and the DKEY+ line where character information bits
are clocked in from the keyboard.
STROBE+ becomes active
whenever the operator depresses a key.
This signal also
clocks in the tied-low data line (Pin 2) of Flip-flop 3A,
the New Key Pressed Latch.
Pin 6 of this flip-flop is tied
around to the input of buffer 5A for reading by the Z-89.
Repeat keys are detected when STROBE+ and the New Key Pressed
Latch remain active beyond a specified time.
The
Z-8~
will,
in such -an instance, enter the keyboard repeat routine.
Character information bits are clocked in the DKEY+ line by
the
Z-8~
toggling the'Clock Latch 4A.
Pin 11 is clocked by
CSC7- while the Data input, Pin 12, is varied by the
Z-8~
manipulating DA7+ (seen at 1A on the sheet).
Flip-flop 4A also contains the elements of the ALARM latch.
CSC7- provides the clock to pin 3 while DA5+ provides the
Data input to Pin 2.
With ALARM activated, a 3.5 KHz signal is
generated on the keyboard circuit board to sound the audio
speaker.
The ALARM latch is reset by the
Z-8~
microprogram
after approximately i of a second, stopping the speaker tone.
1-27
KEYBOARD INTERFACE AND DC VOLTAGE CONTINUED
The
Z-8~
notifies the controller of data ready to be
transmitted over the communication line by setting
Request to Send to the modem.
Chip select CSC4- clocks
pin 11 of Flip-flop 3A while DA1+ is high to accomplish this.
A driver network converts the TTL output of 3A to RS-232-C
levels.
The bottom third of the sheet illustrates the diode isolated
+15 volt and -12 volt levels which connect with the external
terminator shoe.
The +5V and Ground connections between
Pl and P2 are also illustrated.
1-28
EXPLANATION OF THE LOGIC DRAWINGS - Sheet 9
SIGNAL AND DC POWER DISTRIBUTION
The logic control board fingers at P1 plug into junction J1
illustrated at the left hand side of Sheet 9.
The intercon-
nections between elements of the VT-3 are shown on this page.
EXPLANATION OF THE LOGIC DRAWINGS - Sheet 10
TRANSFORMER AND WIRING DIAGRAMS
Sheet 10 illustrates the AC power input as fed to the transformer terminal strip.
To accomodate the various possible in-
put voltages (100, 115, 215, 230, 240), the jumper wires to
the terminal strip must be placed according to the table on
the sheet.
1-29
PS-9 POWER SUPPLY
The PS-9 functions as a normal, linear power supply within
the VT3, providing three DC outputs: +5 volts (3.0 amps);
+15 volts (1.5 amps); and -12 volts (.05 amps).
Physically,
it consists of a printed circuit board and a transformer,
both residing within the pedestal base of the VT3.
Input voltages are variable and selected through connections
made to the terminal strip of the transformer.
Refer to
'Sheet 10 of the Logic Drawings for configuration of~~ the
winding points.
Operation is regulated at the expressed
voltages between 47 and 63 HZ.
Output voltages are variable by altering the value of the
adjustment resistor corresponding to the specific DC output.
Outputs when tested should comply to the following parameters.
Minimum
Maximum
Adjusted by
+5V
4.75 ....... 5.25
R11
+15V
14 . 85. . . . .. 15. 15
R6
-12V
-10.8 ...... -13.2
Fixed
Specific procedures for selecting resistor values are
detailed in Qantel Document #A30903 . .
Overvoltage protection is provided on the +5 VDC output,
dropping the voltage output to
5.8 VDC.
~
V if the value reaches
Each output line is equipped with current
protection -- the +5V and +15V to 120% of full load; the
-12V to 400% of full load.
Pin designations for J3 and J4 follow.
1-30
PS-9 POWER SUPPLY CONTINUED
I
Signal
Color
Pin
16V SEC
Yellow
4
16V SEC
Yellow
6
16V Center
Tap
Yellow/
White
3
34V SEC
Gray
5
34V SEC
Gray
2
34V Center
Tap
Gray/
White
1
I
Signal
Pin
+5VDC
1
+5VDC
2
+5VDC
3
GND
4
GND
5
GND
6
+15VDC
8
+15VDC
9
-12VDC
12
1-31
I
I
VT3 DOCUMENTS
A30694
IOU-39 Design Specification
A30730
IOU-39Q Design Specification
A30786
VT3 Functional Specification
A30809
PS-9 Design Specification
A30822
Qantel Standard Protocol
A30880
VT3/QSP Driver Specification
A30901
Character Set Dot Matrix:
ASCII
A30902
Character Set Dot Matrix:
Kana
A30903
PS-9 Test Procedures/Theory of Operation
A30917
Character Set Dot Matrix:
A30935
IOU-39Q Cabling
A31022
VT3 Test Procedures
A31023
VT3 Control Logic
D30785
VT3 Logic Drawings
D30807
PS-9 Logic Drawings
F30730
IOU-39Q Functional Specifications
F30786
VT3 Firmware
L30730
IOU-39Q Microcode Listing
L30786
VT3 Microcode Listing
1-32
Swedish
IC LISTING FOR THE VT3
1863B . . . . . . . . . . . . . . . . . Universal Asynchronous ReceiverTransmitter
2114-2 . . . . . . . . . . . . . . . . 1K X 4 bit RAM
2716-1 . . . . . . . . . . . . . . . . 16K Erasable Programmable Read-Only
Memory
4040 . . . . . . . . . . . . . . . . . . 12-Bit Ripple Counter
74LS~~
. . . . . . . . . . . . . . . . 2-Input NAND gate
74LS~2
. . . . . . . . . . . . . . . . 2-Input NOR gate
7426 . . . . . . . . . . . . . . . . . . 2-Input NAND gate, open collector
74LS74 . . . . . . . . . . . . . . . . Dual-D Flip-Flop
74LS138 . . . . . . . . . . . . . . . Octal Decoder
74LS158 . . . . . . . . . . . . . . . Quad 2-Input Data Selector/Multiplexer
74LS161 . . . . . . . . . . . . . . . 4-Bit Synchronous Counter
74LS166 . . . . . . . . . . . . . . . PI-SO/ SI-SO, 8-Bit Shift Register
74LS193 . . . . . . . . . . . . . . . Presettable 4-Bit Binary Up/Down
Counter
74LS244 . . . . . . . . . . . . . . . Octal Bus Buffer, Non-Inverting
Tri-State
74LS273 . . . . . . . . . . . . . . . Octal D-Type Flip-Flop
74LS373 . . . . . . . . . . . . . . . Octal Latch with Tri-State Output
CM2000 . . . . . . . . . . . . . . . . Crystal Oscillator
Z-8~A . . . . . . . . . . . . . . . . .
Microprocessor
1-33
Operat i anal
Descri ptian
DISPLAY SCREEN
The character sets, English and KANA, illustrated in the Appendix demonstrate the range of VT3's display capabilities.
Most
of these characters are available to the keyboard operator;
however, the graphic symbols (shown as
$1~
through 1F) may be
entered only through a Write from the main CPU.
The actual display presented on the CRT is subject to a number
of variables.
Display format, field parameters, cursor posi-
tion, transmit marks, data display, and other elements are
structured in ways discussed in the following section.
The aspect ratio of the display screen, the number of lines by
the number of characters per line, varies according to two considerations.
A jumper switch, J13, sets screen format at turn-
on or reset to 27 lines by 64 characters (1728 display characters) or 24 lines by 80 characters (1920 display characters).
This switch-selected format may be changed by computer command
at any time.
Characters stored in the Display RAM fit within set classifications.
Foreground characters appear on the screen as posi-
tive, green on black, images.
Background characters appear on
the screen as negative, black on green, images.
Suppressed
background characters are represented by foreground spaces.
Within the Display RAM, certain control information is stored
in the locations seen as suppressed background characters.
Fields further define data display, offering boundaries within
which characters may be entered.
A normal field is distinguished
by a lack of any special background character before it.
It may
encompass any area of the screen not limited by background or
suppressed background characters.
II-1
DISPLAY SCREEN CONTINUED
A Right-justified field follows an $OB.
Only numeric charac-
ters may be entered into it, including one decimal and one
minus sign.
To the operator at the keyboard, data being en-
tered occurs at the far right portion of the screen, and shifts
to the left as additional data is entered.
Kana fields are available with the Japanese VT3.
A $OF pre-
ceding provides identification in the Display RAM.
The main CPU conditions the Display Screen as is appropriate
to the User Program being utilized by writing background areas.
The operator cannot enter data into these areas.
They general-
ly contain information structuring data entry into foreground
fields.
The cursor is a blinking character notifying the operator of
the location of the next position for data entry.
The cursor
skips over any background areas as it proceeds left to right
a space at a time across the display screen.
During right-
justified entry, however, the cursor remains stationary, marking the righthand point at which new data will appear before
being shifted right.
The cursor is not displayed during Blind Entry Mode, a method
by which the operator may enter password information without
displaying it on the screen.
this mode.
32 characters may be entered in
Read Request to the main CPU is
by
'P!\O
.1..0..1..),
or TRANSMIT through the used of Transmit Stop characters at
both ends of the blind buffer.
Following password entry and
main CPU recognition, the cursor is positioned
foreground field on the display screen.
11-2
~_
.LU
+.1....,.....
L.UC
.,p..;".. ...... +-
.l...1...1.i:)l,.
DISPLAY SCREEN CONTINUED
The control line occupies the last line of the display screen;
the 28th line of a 64 character per line screen or the 25th
line of the 80 character per line screen (a line is skipped
following the 24th line).
tem messages.
The control line is used for sys-
Flag 2 and Flag 3 states are stored as the first
6 characters of the control line.
Information used in test
sequences is also stored within this line.
CONTROL CODES RECCGNIZED BY THE VT3
DESCRIPTION
CODE
CHARACTER
00
01xxyy
~ ... ll
Ignored, except causes write initialization.
Set Cursor
04
Escape
Causes the terminal to place the cursor at the Row xx, Column yy; xx between 1 and 27 (24),
yy between 0 and 63 (79).
Escape - next character Is a control character.
0401
Remember Cursor
Saves current value of cursor for Restore Cursor command(09).
0402
Select 64
Sets the display mode to 64 characters per line and 27 lines. The screen is cleared to
blanks and the cursor is positioned to home (or the 27th line if typewriter mode).
0403
Select 80
Sets the display mode to 80 characters per line and 24 lines. The screen is cleared to
blanks and the cursor is positioned to home (or the 24th line if typewriter mode).
0404
Select Default
Sets either the 64 or 80 character display mode depending on the hardware default switch.
The screen is cleared to blanks and the cursor is positioned to home (or the last line
if typewriter mode).
0405
Set Bl ind Entry
Clears the 32-byte blind buffer to blanks. At the completion of the write, the cursor
is positioned to the beginning of the blind buffer.
0406
Blank Fi I I line
Replaces all characters from cursor position to end of line with blanks (foreground, background, or suppressed-background). Positions cursor to beginning of next line (or home).
0407
Clear Field
Replaces all characters in field where cursor resides with foreground blanks.
cursor to first entry in field (right-most position If RJ field).
0408
Force Transmit
Causes the VT3 to set 'Read Request'.
after the completion of the Write.
0409
Transmit Stop
Stored on the screen as a suppressed background character. When the operator presses TAB
or RETURN and the cursor advances past a Transmit Stop, the VT3 posts Read Request. In
addition SHIFT/TAB and SHIFT/RETURN will not back up over a Transmit Stop character.
040A
Rollup
Moves the screen portion below the cursor line up one line. The cursor line is lost; blank
foreground is inserted at the bottom. The cursor is positioned to the beginning of the
bottom line. The control line Is not affected.
040B
Roll Down
Hoves the screen portion below the cursor line down one line. The cursor line is lost. A
blank foreground line Is Inserted at the cursor line. The cursor is positioned to the beginning of the current line. The control line Is not affected.
040C
Set SuppressedBackground
Causes terminal to accept subsequent data characters as suppressed-background (displayed
as spaces).
05
Clear Screen
Clears the screen to foreground blanks and posItions the cursor to home.
is not affected.
11-3
Positions
The VT3 acts as If the operator pressed TRANSMIT
The control line
CONTROL CODES CONTINUED
CODE
CHARACTER
DESCRIPTION
06
Clear Foreground
Clears all foreground positions on screen to blanks and positions cursor to first foreground position on screen. The control line is not affected.
07
Alarm
Causes audible alarm to sound.
08
Set Background
Causes terminal to accept subsequent characters as background (displayed as black on green).
09
Restore Cursor
Positions the cursor to the position it occupied at the start of the write or to the last
'remembered' cursor location.
OA
Set Foreground
Causes terminal to accept subsequent characters as foreground (displayed as green on black).
OB
Ri gh t-Just i f i ed
When placed as the character immediately preceding a foreground field, it designates the
field to be right-Justified. It Is stored on the screen as suppressed-background.
OC
Transmit
Mark
Stored on screen as suppressed-background. When the operator presses TAB or RETURN and
the cursor advances past a Transmit Delimiter, the VT3 posts Read Request.
00
Cursor Return
Causes terminal to position cursor to beginning of the next line on screen (or home).
OE
Escape
Next character is control character.
OE02
Reset F2
Resets Flag 2.
OE03
Reset F3
OE04
Reset F2
OEOS
Enter Typewriter
Resets Flag 3.
&
F3
Resets Flag 2 and Flag 3.
Sets typewriter mode for writing.
OE06
Enter Normal Mode
Sets normal mode.
OE07
Write Control Line
Clears the control line to blanks.
OEOF
Execute Test
Program
The remainder of the data is used as a z80 program to execute.
the program.
OF
Kana Field
On English systems it is ignored except as a screen place-holder. On Kana systems it
causes the field to be declared a Kana field. Characters from the keyboard are interpreted
as being in Kana mode until the 'ALPHA HaDE' key is pressed or the cursor is n~ved to a new
field.
Clears typewriter mode.
Subsequent data is written to the control line.
Use a RETURN to exit
VT3 KEYBOARD
l
J
Fig. 7
1I-4
KEYBOARD
73 momentary contact keys with N-key rollover are incorporated
into the VT3 keyboard.
Repeat capabilities are possible with
some keys and any character key may be repeated if preceded by
simultaneously depressing SHIFT and the decimal point key on
the numeric cluster.
Control keys provide a means for editing
(BACKSPACE, CLEAR, and INS CHAR)
and data capture when entry
is complete (TRANSMIT, TAB, and RETURN).
Two flag states,
stored in flip-flops, are provided to allow the main CPU to
initiate escape sequences: FLAG 2 (F2) and FLAG 3 (F3).
Fol-
lowing turn-on or reset, all alphabetic characters will be uppercase; depressing LTRS allows control of upper and lowercase
generation.
The SHIFT key alters the control function of sev-
eral keys as shown in the following description:
CONTROL KEY
NORMAL FUNCTION
WITH SHIFT
BACKSPACE
Moves cursor one position left. Stops at
first foreground in field or at beginning of
screen. In right-justified (RJ) fields it
removes the last number entered and shifts
the remaining characters one position right.
Moves cursor one position right. stops
at last foreground in screen. Illegal in
RJ fields.
I
TAB
I
I
f40ves cursor to beginning of next foreground
field (may be several lines or less than one
I line)
• Sets "Read Request" at end of screen
Moves cursor to beginning of present
foreground field, or if already there (or
RJ field), to beginning of previous foreground field. Will not pass beginning of
screen or Transmit Stop character.
or transmission delimiter (Transmit Mark or
Transmit Stop).
INS CHAR
Inserts blank character at cursor position
and shifts all characters to the end of the
field one position right. The last character is lost. Illegal in RJ fields.
Deletes character at cursor position and
shifts all characters to the right of the
cursor in the same field, one to the left.
A blank is inserted at the end of the field.
Illegal in RJ field.
Replaces all characters in field where cursor resides with blanks. Cursor is positioned to normal position of first entry
in field (left if normal, right if RJ).
Clears foreground. Resets all foreground
characters on the screen to blanks. Cursor is positioned to first foreground field
on screen. In blind entry mode, it acts
like CLEAR.
RETURN
Moves cursor to first foreground position
after end of line. Sets "Read Request" at
end of screen or if a transmission delimiter
is encountered. If RJ field, same as TAB.
Moves cursor to first foreground position
in line, or if already there, to first foreground position on last previous line containing foreground. Will not pass the beginning of the screen or a Transmit Stop.
If RJ field, then same as SHIFT/TAB.
F2
Toggles "Flag 2", a switch tested by the
software.
I
CLEAR
I
I
I
I Performs a terminal reset.
I
L-__________L -______________________________________
11-5
I
!
~
____________________________________
I
~_j
KEYBOARD CONTINUED
CONTROL KEY
NORMAL FUNCTION
WITH SHIFT
NUt·tERIC
Produces decimal point display.
Starts keyboard repeat mode. The following key is repeated at a rate of 15 cps as
long as it is depressed by the operator.
Note that this applies to the numeric cluster
only.
ADDITIONAL CONTROL KEYS
TRANSt~IT
F3
LTRS
FUNCTION
Sets "Read Request" in order to transmit data to the computer.
Toggles "Flag 3". This is used by the operating system as an escape
condition to abort the current program.
Allows upper and lOvler case alphabetic characters to be entered.
pressed a second time, it restores 'upper case' mode.
11-6
11hen
MICROCODE SUMMARY
It is beyond the scope of this manual to provide a detailed
description of the VT3's firmware. Further information, including flowcharts, may be found in Qantel document #F30786
and by studying the actual microcode listing, document # L30786.
This description will cover in a general way the basic processes carried out by the microcode.
The firmware can be examined most easily by reducing the routines
to four, logically independent groups.
1 MAIN
ROUTINES
:~~:n@:.~:ffi~~~::~:*=:~~:~g9: prepares the logic elements (flags, RAM variables,
operation modes) to proceed with the program sequence.
~~::i:*:::!:;·g~:~::~!~[~J-.:·:·!~.p:!~i mon it or s f or in comi ng data an d bran ch es to
. routines to process it.
~~tlg~t·~····:·:g~9;~:~:~!~;~:~r\\\hnd Input handles keyboard data arriving
as a result of operator input.
:\fi¥\*~~\:::~·processes data sent from the main CPU.
::f:l:i~~:::: turns display screen information into a QSP data stream
for sending to the main CPU.
2SCAN INTERRUPT HANDLER
Provides a new address for each line of the Display RAM to
initiate the refresh process of the display screen.
3TIMER INTERRUPT HANDLER
Provides periodic checking of the communication line, processes QSP data streams, and handles data transmission.
11-7
4 TEST
PANEL INTERRUPT HANDLER
Handles the input from the
Z-8~
test panel interface at the
P2 junction.
INITIALIZATION
Initialization occurs immediately following power on or whenever a reset action is performed.
Essentially, initialization
is designed to set up program variables (represented by internal
Z-8~
flags, RAM storage locations, and applicable flip-flops,
and other variables) to allow execution of the program from the
beginning stage.
The steps during Initialization include the £ollowing:
•
Z-8~
•
Maskable Interrupts are disabled.
•
Keyboard speaker turned off.
•
Request to Send flip-flop cleared.
•
Index register IX is set to start of Private RAM ($4000).
•
Private RAM cleared to zeroes.
•
Keyboard line accessed for random characters.
•
Screen format is set according to jumper J13.
•
Display RAM cleared.
•
Auxilliary
Stack Pointer set to top of stack.
Z~8~
registers (which are used for Scan Interrupt
information) are prepared for the first scan.
•
Terminal Address is read (from control board Address Switches)
and stored.
•
UART received register cleared.
11-8
INITIALIZATION CONTINUED
•
Receive routine prepared (through RAM variables) to expect
EOT character from communications line.
•
Z-8~
•
Maskable Interrupts enabled.
•
Main Control Loop entered.
Interrupt Mode 0 set.
MAIN CONTROL LOOP
The Main Control Loop consists of a very basic sequence.
The
keyboard is checked to determine if a key has been pressed.
If so, the incoming information is processed.
If not, the
Main Control Loop checks Private RAM to determine if a Write
or a Read command has been received from the main CPU.
appropriate branch is carried out.
The
When the necessary opera-
tions are completed, the program returns to the start of the
Main Control Loop.
11-9
KEYBOARD ROUTINE
The Keyboard Routine is designed to respond to operator input
from the keyboard: each key pressed initiates either a display
or a control sequence.
The Kinput Subroutine is contained with-
in the Keyboard Routine and is used for recognizing and clocking in serial keyboard data; translating data to ASCII; handling
certain control key functions (LTRS, F2, REPEAT); and turning
off the audio alarm after a set time.
The essential processes in the Keyboard Routine are:
~Checks
the READ PENDING flag in Private RAM.
- If true, call KINPUT searching for the key pressed
indication.
- If a key is pressed, the audio alarm is sounded
keys cannot be processed while the Read Pending is
active.
- If false, checks the FORCE TRANSMIT flag (equivalent to the operator pressing TRANSMIT).
~Blinks
the cursor.
~Checks
for key pressed.
~Responds
to the type of key by initiating the correct se-
quence.
- Character keys are processed by entering display
sequence.
- Control key functions are carried out.
The setting of the READ PENDING flag results in a READ REQUEST
being delivered to the IOU-39Q during its scanning cycle, thus
notifying the main CPU that data is available for reading.
The
operator can cause READ PENDING to be posted in three ways.
The most straightforward way is by simply pressing the TRANSMIT
key.
This causes the program to scan backwards on the display
screen.
All the intervening data is transferred to the trans-
mission buffer in Private RAM for eventual passage through the
communication line.
11-10
KEYBOARD ROUTINE CONTINUED
TAB and RETURN may also set READ PENDING if they cause the program to encounter a Transmission Delimiter.
In such a case, the
program sequence acts like the TRANSMIT sequence.
KINPUT SUBROUTINE
This subroutine performs the manipulations required to input and
process the encoded data from the keyboard.
Once a key depres-
sion is recognized (through the Buffer 5A on Sheet 8 of the Logics),
the character is shifted in a bit at a time by toggling a flipflop that generates the keyboard clock.
The most significant bit
arrives first and represents the shift condition.
The next 7
bits are the keyboard code - they are translated to ASCII for
processing and display.
All coded values translated to $80 or
higher are recognized as control keys.
Characters are saved as received until the Repeat flag (initially
cleared) is updated to reflect any upcoming repeat function.
Of the available control keys, KINPUT internally handles the
following F2; SHIFTjF2; F3; LTRS; REPEAT; ALPHA MODE; and KANA
MODE.
READ
A READ command from the main CPU is realized by the VT3 through
a structured data sequence from the IOU-39Q.
From the Main Con-
trol Loop, READ is entered whenever the READ IN PROGRESS flag
is high.
This flag is set during another routine, RECEIVE,
which handles communicaiton line activities.
Once the first
three bytes of the formatted message stream are established by
RECEIVE, the READ routine proceeds to continue transmission,
11-11
READ CONTINUED
. taking data from the Transmit Buffer, formatting it according to
Qantel Standard Protocol, and releasing it onto the communications line.
Compression and transparency of the data is taken
care of during this process.
The message format in response to a READ command is as follows:
DEVICE
STX
STATUS
CURSOR X
CURSOR Y
TEXT
ETX
BCC
The cursor position is transmitted, both X and Y coordinates as
positioned when the READ PENDING was encountered.
(Cursor values
are ORed with $80 so as not to be transparent.)
Each byte in the Transmit Buffer is then sent.
When the data
has been transmitted, the message format is concluded with a
ETX character and BCC (Block Check Character) to ensure data
integrity.
The READ PENDING state is maintained if the VT3 does not receive
a positive acknowledgement (ACK -- $06).
The entire sequence
is then repeated when signaled by the IOU-39Q.
If the transmission succeeds, flags are reset (READ PENDING,
F2, and F3) and the cursor is positioned to the next foreground
field.
The routine returns to the Main Control Loop.
11-12
WRITE
Characters coming in the DART's receive buffer are processed by
the WRITE routine to be placed on the display screen.
WRITE
commands are received in formatted QSP message streams by RECEIVE routine at which time the WRITE PENDING flag is set.
As
the program is progressing through the Main Control Loop, detection of WRITE PENDING instigates the WRITE routine.
Characters are examined as they are inputted from the receive
buffer for specific characteristics.
After the write initiali-
zation sequence is performed, any characters between $00 and
$OF are considered control commands; characters higher than $OF
are data characters.
Each control character results in a program branch to accomplish
the assigned task.
sequences.
Commands may consist of one, two or three-byte
At the conclusion of processing the command, the
program branches back to handle the next character in the receive buffer.
Data characters are stripped of their highest significant bit.
Any resulting values between $00 and $03 are converted to $20.
This prevents the user program from placing control characters
onto the display screen directly.
Characters are placed on the screen in the position denoted by
the cursor (which is incremented after each display).
Fore-
ground and background characters are distinguished when the
character value is ORed with the mode of display.
Whenever
the cursor is extended beyond the edge of the screen, it is
repositioned to the beginning of the screen.
The exception to
this is typewriter mode in which case the write is truncated
when the cursor reaches the edge.
11-13
WRITE CONTINUED
Following character processing the routine performs a Write
Cleanup if the Write Setup flag indicates the screen was modified for display.
When in typewriter mode, a Transmit Mark is
situated at the end of the data.
The cursor is moved forward
until it encounters a foreground field, where it is halted awaiting operator entry.
The Write Pending flag is set to 0
and the program resumes in the Main Control Loop.
SCAN INTERRUPT HANDLER
The Z-89 utilizes its set of auxiliary registers (AF'; BC';
DE'; and HLT) to keep track of horizontal and vertical trace
progress across the CRT.
When the Scan Interrupt routine is
entered, these registers are immediately accessed and will contain the information to orient the Z-89.
B
Raster Row Counter (0 through 8)
C
7 indicates odd scan; 8 indicates even scan
DE
Next Address to start scanning row
HL
Pointer for the Scan Address Table (used to find
the address to be loaded into DE).
The hardware timing circuits initiate a Scan Interrupt every
64 microseconds.
Each time this happens the Z-89 has 16 micro-
seconds to load the correct address for the next starting horizontal row.
Maskable Interrupts are disabled and the Z-89,
through a hardware buffer, recognizes the branch to address
$0038 where the Scan Interrupt Routine is stored.
Each character is composed of 15 raster lines.
Since inter-
lacing is employed in VT3 scanning pattern, the character is
11-14
SCAN INTERRUPT HANDLER CONTINUED
"sketched in" in two subsequent passes of the entire display
screen.
A horizontal row address is presented for 7
times on an alternating basis.
or 8
The signal ODDCOUNT obtained
from the hardware dictates, if true, that the first row be
presented 7 times.
The next row will be presented 8 times
followed by a row 7 times and so on.
When ODD COUNT is false,
the first row is presented 8 times, the second 7 times, and
so on.
A separate Scan Address table exists for 64 characters per
line operation and one for 80 characters per line operation.
After delivering the correct address to the hardware, updating
the data in the auxiliary registers, the program exchanges registers to the normal set, enables the interrupts, and resumes
the program from the location indicated by the stack pointer.
TIMER INTERRUPT HANDLER
Roughly every 256 microseconds, a timer interrupt is generated
from the hardware timing network.
The
Z-8~
distinguishes this
interrupt from the higher priority scan interrupt by reading
a Tri-state buffer, 7B, seen on Sheet 1 of the Logic Drawings.
This causes a RESTART 8 instruction; the program branches to
location $008 where the Timer Interrupt Handler begins.
Interrupts are enabled during the Timer Interrupt sequence,
allowing the Scan Interrupt to be generated and recognized at
any time.
This is necessary to ensure that the correct Scan
Address will be delivered to the Scan RAM to start the refresh
of a horizontal row on the display screen.
11-15
TIMER INTERRUPT HANDLER CONTINUED
The ININT flag is used to keep track of whether or not the
Z-8~
had begun processing a timing interrupt.
If it had been
processing the timing interrupt and was diverted by another timer
interrupt, the flag would be true.
In this case, the program
would return so that interrupts would not be nested.
The ININT is set, otherwise, and the routine checks to see if
data is arriving on the communications line.
is processed by the RECEIVE routine.
is checked for activity.
than
~
Incoming data
Then the 10 Flag Byte
If the flag contains any bits other
the IOCHECK routine is entered.
Following processing
of this sequence, the program returns to the address stored in
the stack register.
The ININT flag is reset in preparation
for the next Timer Interrupt.
RECEIVE
The QSP formatting of data transmissions and reception of incoming message strings is handled by this RECEIVE routine.
An
inputted data byte is dealt with according to what is expected next based on protocol sequences.
An address is reserved to
guide the program to the special purpose routine for handling
the expected byte.
This saves time in the processing of QSP
sequences.
RECEIVE is entered out of the Timer Interrupt Handler whenever
a byte has been received on the communication line.
11-16
IOCHECK SUBROUTINE
Modem control signals are monitored and manipulated by this
subroutine.
Three separate operations take place according
to bits in the 10 Flag signalling the state of activities.
One segment of the routine checks for the Clear to Send bit
detected through the hardware.
Once the CTS is detected, it
is reset in the 10 Flag.
While data is being transmitted, the IOCHECK subroutine monitors for the arrival of Transmit Service Request from the modem.
Once received, the next byte in the 10 buffer is fetched and
outputted on the communication line.
The total number of bytes
in the buffer is stored in IOCOUNT, a location in Private RAM.
When the bytes are all transmitted, the bit in the 10 Flag denoted date ready to be transmitted is reset.
Ready to Send is dropped by this routine following the transmission of all data out of the DART.
The combination of
Transmit Service Request with the Transmit buffer empty causes
the routine to drop Request to Send.
11-17
DATA PATHS and TRANSLATION
1)
A key position code is generated for each key pressed on the keyboard.
This code must be translated to ASCII by the
is stored
2)
Z-8~
before the characrer
in RAM or recognized as a conrrol code.
The Display RAM is rhe ulrimare storage locarion for all characters
ro be placed on rhe screen.
and graphic information t;hat is
the characrer ROM responds
Since
ro ASCII values placed ar irs address in-
puts, all display RAM characrers musr be ASCII encoded.
3)
Dara channeled over rhe communication line musr be formered according
to QSP requiremenrs.
This discipline increases efficiency of rhe
co~
munication process by srrucruring data compression, rransparency, and
main raining message integriry by a block checking process.
4)
The Video Signal is a serial bit strea1Jl.
Dots are placed on rhe CRT
during scanning represenring slices of characrers; rhe slices are inrerlaced
ro create t;he assembled characrer in rwo successive sweeps of
rhe display screen.
conrained within
The visual represenration of rhese characters is
me characrer ROM in the form of a dor marrix parrern.
---------,
Control
IZ-SO I
<===)
~§c::J
IOU-39Q
Iz-sol
0
<
To Main CPU
logic Board
QSP
Communication.
line
~D~5;1~; ~
)
: RAM
I
I
\
o
:
L ____ ...J
o
/".-\
U
~)
Video
Signal
Key
f]\
V
r
CRT
Position
Code
I
0
c=J
\. . . t . . L,UUH~H\~
-'-.L.L.1.
.L
::-)0
..L
I_L.1...J...
fJ -~.1...L..L..L..
Fig. 8
.J...
..J.....J....J.--L..l.....1.
r
Keyboard
I
EJ
t+
VT3
____
I-
11-18
-1
TYPEWRITER MODE
Typewriter Mode provides a simplified means of writing to the
VT3 when complicated screen formats are not required.
The
display screen mimics a typewriter; the lines of characters
are entered as background at the bottom of the screen and "rollup" as entry continues. The handling of the write process in Typewriter Mode is somewhat different and includes the following:
•
As part of the Write Initialization, the display screen
is rolled-up, the cursor is positioned at the beginning
of the bottom line, and background display mode is set.
•
SOD (Carriage Return) within the written data is an indication for the VT3 to roll-up the entire screen, clear
the bottom line to blanks, and position the cursor at
the beginning of the bottom line.
•
A write is terminated if data characters run off the end
of the display area.
Use of Carriage Return ($OD) allows
a number of lines to be written for one write command.
•
Transmit Marks are placed at the end of the Write.
(
I
I
Fig.9
Katakana Keyboard
11-19
KAT AKANA KEYBOARD
The Japanese character set consists of 124 characters including
Katakana and uppercase English.
Z-8~
During a write to the VT3, the
recognizes a $OF as the last background character before
a field of Kana characters.
This value is converted to a $83
for storage in the Display RAM.
The cursor being positioned
into a Kana field results in data entered from the keyboard
being interpreted as Kana.
The ALPHA key, once depressed, al-
lows uppercase English characters to be entered.
The keyboard is equipped with both ALPHA and KANA mode keys -the default value is ALPHA mode.
Whenever KANA is depressed,
subsequent keys are interpreted as KATAKANA code.
Because ASCII values
as
stored in the Display RAM are limi ted
to seven bits (the eighth bit is used to identify foreground
and background display), the values assigned to the KANA character set from $8F up must be translated to lower values for
RAM storage.
This translation takes place according to the
following table:
,rage
For Display
Value from
Kana Character
Set
Display RAM
Stored Value
RAM
Ax
Bx
Cx
Dx
Ox
1x
6x
7x
For Kana
Transmission
of Data
x - Value between ~ and F as
ed by vertical column on the
ter set chart.
11-20
charac~
DATA CONVERSION FOR STORAGE
Another type translation takes place with particular control
code characters that are transmitted in one form and converted
to another form for Display RAM storage.
These characters
are:
$80
SUPPRESSED
BACKGROUND
NULL
Used by the main CPU to write data in
suppressed background mode.
$81
Appears as $OC in a data stream.
TRANSMIT MARK
82
Appears as $OB in a data stream.
I RIGHT-JUSTIFIED
FIELD
Transmit Stop appears as $0409 in a
data stream.
In the KANA version, the
same $83 means the following foreground
field is KANA and appears as $OF in the
data stream.
$83
TRANSMIT STOP
or KANA
Applying these translations to a segment of a typical data
transmission to a VT3 would result in the following conversions:
Sent t hrough the
IOU-39 Q
.-
C5 AA
Displa y RAM Will
Contai n
65 GA
.
Displa yed on
Screen
•
T
0C
21/)
20
81
2fJ
20
,--------,'.
I
: Transit:
.L
: Mark:
\
""'-----_."
Fig. 10
11-21
I
f)C
47
81
47
."-------"',
..----- ......
(~~~~:.)
,-- ---,
(Space;
,-------,
jTransit ":
Mark)
_-- ---'
I
I,
....
G
KATAKANA CONTINUED
5
6
7
8
9
P
a
R
s
T
U
V
W
x
y
z
C
¥
)
Fig. 11
KATAKANA CHARACTER SET
11-22
A
B
C
0
E
F
Configuration
Information
VT3 CONFIGURATION GUIDE
VT3's attached to a single IOU-39Q may be arranged in the configurations described in the following section.
A network in-
volving one 10U-39Q may contain a maximum of 31 VT3's.
All Baud
rates should be identical within the network as set by jumper
switches J1 through J7.
DIRECT STRING NETWORK
TERMINATOR
Fig. 12
•
A string of 1 to 31 VT3's connected by 232jV24 cables.
•
Total length of string no more than 250 feet.
•
No more than 50 feet between individual VT3's.
•
Communication speed: 19,200 bits per second.
•
10U-39Q timeout:
•
Terminator plug (M42540-001) should be attached to
15 milliseconds.
female connector of the last VT3 in the string.
111-1
VT3 CONFIGURATION GUIDE
HUB UNIT NETWORK
232/ V24
TERMINATOR
~
N
>
*,
"'"
N
M
N
TO CONTROllER
TERMINATOR
Fig. 13
•
In conjunction with Line Drivers, the Hub Unit extends
the range of direct strings (1 mile at 19,200 bps; 2 miles
at 9600 bps).
•
Allows more than one string of VT3's to be connected.
•
Connection between Hub Unit and Line Driver should be 4wire cable (M42851).
•
A maximum of 7 Line Drivers may be attached to the Hub Unit.
•
Additionally, a local string, without a Line Driver, may
be attached.
•
Maximum communication speed: 19,200 bps.
•
IOU-39Q timeout: 15 milliseconds -
•
Terminator plugs should be attached to female connector
of the last VT3 in any given string.
111-2
VT3 CONFIGUATION GUIDE CONTINUED
REMOTE NETWORK
o
w
Z
I
I
I
I
is loaded into the counter and
appears on the outputs regardless of the
conditions of the clock inputs when the Parallel Load (PL) input is LOW. A HIGH level on
the Master Reset (MR) input will disable the
parallel load gates, override both clock inputs,.and set all outputs LOW. If one of the
clock inputs is LOW during and after a reset
or load operation, the next LOW-to-HIGH
transition of that Clock will be interpreted as
a legitimate signal and will be counted.
VCC
DO
MA
CPo
Teo
CPu
Teu
a
O2
MODE SELECT -FUNCTION TABLE
OPERATING
MODE
MR
PL CPU CPO 00. 0 1. 0 2. 0 3
00. 0 1. 0 2. 0 3
TCU
TCO
X
L
X X X X
L
L
L
L
H
L
H
X
X
H
X X X .X
L
L
L
L
H
H
L
L
X
L
L
L
L
L
L
L
L
L
H
L
L
L
X
H
L
L
L
L
L
L
L
l
H
H
L
L
L
X
H
H
H
H
H
H
H
H
L
H
L
L
H
X
H
H
H
H
H
H
H
H
H
H
Count up
L
H
T
H
X X X X
H(b)
H
Count down
L
H
H - HIGH voHage level
L - LOW voHag. level
X '"' Don'I car.
I -
OUTPUTS
X
Parallel load
I
INPUTS
H
Reset (clear)
The Terminal Count Up (TCU> and Terminal
Count Down (TCO) outputs are normally
HIGH. When the circuit has reached the
maximum count state of "15", the next HIGHto-LOW transition of CPU will cause TCU to
go LOW. TCU will stay LOW until CPU goes
HIGH again, duplicating the Count Up Clock
although delayed by two gate delays. likewise, the TCO output will go LOW when the
circuit is in the zero state and the CPO goes
LOW. The TC outputs can be used as the
clock input signals to the next higher order
circuij in a rnuiiistage cOtAniar, since they
LOGIC SYMBOL
FEATURES
LOW·lo·HIGH clock Iransition
NOTES
b.
TcU -
CPU al terminal count up (HI-Hi)
c.
fcc
CPO attarminal counl down (LLll)
so
V-R
Count up
Count down
74LS244
Octal Three-State Buffers
FUNCTIONAL DESCRIPTION
DISTINCTIVE CHARACTERISTICS
The lS241 and lS244 are octal buffers fabricated using
advanced low-power Schottky technology. The 20-pin package provides improved printed circuit board density for use
.in memory address and clock driver applications.
•
•
•
•
•
•
•
•
Three-state outputs are provided to drive bus lines directly.
The Am25lS241 and Am25lS244 are specified at 48mA and
24mA output sink current, while the Am54lS174lS241 and
Am54lSI74lS244 are guaranteed at 12mA over the military
range and 24mA over the commercial range. Four buffers are
enabled from one common line and the other four from a
second enable line.
Three-state outputs drive bus lines directly
Hysteresis at inputs improve noise margin
PNP inputs reduce D.C. loading on bus lines
Data-to-output propagation delay times - lans MAX.
Enable-to-output - 30ns MAX.
Am25lS241 and 244 specified at 48mA output current
20 pin hermetic and molded DIP packages
100% product assurance testing to Mll-STD-883
requirements
The lS241 has enable inputs of opposite polarity to allow
use as a transceiver without overlap. The LS244 enables are
of similar polarity for use as a unidirectional buffer in which
both halves are enabled simultaneously.
Improved noise rejection and high fan-out are provided by
input hysteresis and low current PNP inputs.
lOGIC DIAGRAMS
lS244
lS241
lAI
lYI
lAI
2Vl
lAl
lY2
2A2
2V2
IYl
2Al
2Vl
IYl
2Al
lV2
lS244
lS241
INPUTS
1G
IoU
1M
iG
lYJ
IV4
2VJ
2Al
2M
2G
INPUTS
OUTPUTS
A
Y
H
L
X
Z
L
H
H
H
L
H
L
L
G
lYl
IV4
2V4
lVJ
lA3
OUTPUT
A
H
X
Z
L
H
H
L
L
L
2Y4
2M
2G
2G
Note: All devices have input hysteresis.
lOGIC SYMBOLS
CONNECTION DIAGRAMS
Top Views
11
Vee
2G
IAI
2G
2"f4
IVI
2V4
IVI
IAl
2M
tAl
2M
2"fJ
tV2
2"fJ
IVl
IoU
2AJ
IAl
2AJ
2"f2
IYl
2Y2
IV)
1M
lA2
1M
2A2
2"fl
IV4
2VI
IV4
IG
LS241
IVI IVl
IY3
IY4
11
14
12
I.
IAI
lAI
GND
17
IAl
lAl IA4
2G
It
lVI 2Y2 2VJ 2Y4
11
IG
GND
15
Vee
10
lAI
10
13
13
15
17
2Al
LS244
lG
19
lAl
IVI
IV2 IVJ
IV4
18
18
12
lVl 2V2 2YJ 2V4
Vee
Note: Pin 1 is ma,ked for orientation.
V-9
14
GND
= Pin 20
= Pin 10
.
74LS273
DESCRIPTION
FUNCTIONAL DESCRIPTION
The "273" is an Octal 0 Flip-Flop used primarily as an 8-bit positive-edge-triggered
storage register. Data on the 0 inputs is
transferred to storage during the LOW-toHIGH transition of the clock pulse. The Master Reset (MR) input asynchronously clears
all flip-flops when LOW.
The "273" has eight edge-triggered Ootype
flip-flops with individual 0 inputs and Q outputs. The common buffered Clock (CP) and
Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge triggered. The
state of each 0 input. one setup time before
the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.
FEATURES
All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage
level on the MR input. The device is useful
for applications where the true output only is
required and the <;:Jock and Master Reset
are common to all storage elements.
• Ideal buffer for MOS Microprocessor
or Memory
• Eight edge-triggered 0 flip-flops
• High speed Schottky version available
• Buffered common clock
• Buffered, asynchronous Master Reset
• Slim 2o-Pin plastic and ceramic DIP
packages
• See "371" for Clock Enable version
• See "373" for transparent latch version
• See "374" for 3-state version
LOGIC SYMBOL
11
MODE SELECT - FUNCTION TABLE
13
,.
11
18
12
15
16
19
CP
lolA
INPUTS
OPERA TlNG MODE
PIN CONFIGURATION
OUTPUTS
MR
CP
On
On
Reset (clear)
L
X
X
L
Load "1"
H
t
h
H
Load -0"
H
t
I
L
Vee = PIn 20
GND = PIn 10
H = HIGH voltage level steady state
h = HIGH voltage level one setup lime pnor to the LOW-to-HIGH clock transltoon
L = LOW voltage level steady state
I = LOW voltage level· one setup lime pnor to the LOW·to·HIGH clock transItIon
X = Don'I care
= LOW-Io-HIGH clock Iranslllon.
t
LOGIC DIAGRAM
Do
Dl
(3)
D3
(4)
D4
(I)
Os
D5
(13)
(14)
(17)
CP
w:-:' ~~ ~.o ~r:--:' ~~ ~~ roo ~r:--:w
~I,~
CP
iiR~
Vee = Pin 20
GNO
( )=
= Pin
10
Pin numbers
CP
~
~
J
J
CP
CP
~
I",
0,
J
CP
~
I. ,
V-iO
1
CP
~
I~
J
CP
~
I""
1
CP
~
I""
05
1
~
I""
I
I""
74LS373
OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS
MODE SELECT-FUNCTION TABLE
FUNCTIONAL DESCRIPTION
The -373" is Octal Transparent Latch coupled to eight 3-state output buffers. The two
aections of the device are controlled independently by Latch Enable (E) and Output
Enable (OE) control gates.
The data on the 0 inputs transferred to the
latch outputs when the Latch Enable (E) input Is HIGH. The latch remains transparent
to the data inputs while E is HIGH, and
alores the data present one setup time bafore the HIGH-to-LOW enable transition. The
enable gate has about 400mV of hysteresis
built in to help minimize problems that signal
and ground noise can cause on the latching
operation.
The 3-state output buffers are designed to
drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors. The
active LOW Output Enable (OE) controls all
eight 3-state buffers independent of the
latch operation. When OE is LOW, the
latched or transparent data appears at the
outputs. When OE is HIGH, the outputs are in
the high impedance "off" state, which
means they will neither drive nor load the
bus.
INPUTS
OUTPUTS
OPERATING MODES
Enable & read register
Latch & read register
Latch register &
disable outputs
OE
E
On
INTERNAL REGISTER.
00-07
L
H
H
L
L
H
l
H
H
L
l
l
l
I
h
L
l
H
H
H
H
L
I
h
l
(Z)
H
(Z)
l
L
H • HIGH vonao" lev..
h • HIGH votlage oneselup lime prior 10 the HlGH-to-lOW enmle t,anlitioft
l • LOW vl)lta~e level
I • lOW vollage level one selup liIM prior to the tiGH-lo-lOW enable transi:ioft·
(2) • High impedance -off- Ilate
LOGIC DIAGRAM
121
Vee· Pift20
00
I~I
0,
GNO· Pili 10
PIN CONFIGURATION
lOGIC SYMOOL
"
(If
"
Vec· P,"2O
uNO. "" to
..
II
II
Z-SOA
FEATURES
• Single chip, N-channel Silicon Gate CPU.
• 158 instructions-includes all 78 of the 8080A instructions with total software compatibility. New instructions include 4-, 8- and l6-bit operations with more
useful addressing modes such as indexed, bit and relative.
• 17 internal registers.
• Three modes of fast interrupt response plus a nonmaskable interrupt.
• Directly interfaces standard speed static or dynamic
memories with virtually no external logic.
• 1.0 IlS instruction execution speed.
• Single 5 VDC supply and single-phase 5 volt Clock.
• Out-perfonns any other single chip microcomputer in
4-, 8-, or 16-bit applications.
• All pins TTL Compatible
• Built-in dynamic RAM refresh circuitry.
I.
('-
o
;:a
..,
"
20
A3
SYSTE"l' Wi!
CONTROt.
litO
A.o
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0.
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0.
0,
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~BIT
MAIN REG SET
~
~
/
DATA BUS
ALTERNATE REG SET
ACCUMULATOR
A
FLAGS
F
I
C
o
H
/
ACCUMULATOR
A'
FLAGS
f'
I'
e-
E
0'
E'
l
H'
l'
I
,~''''G''''.
INTERRuPT
VECTOR
GENERAL
PURPOSE
REGISTERS
]
/
MEMORY
REFRESH
INDEX REGISTER
..I W"'M
STACK POINTER
SI'
PROGRAM COUNTER
PC
I
"
R
IV
PURPOSE
REGISTERS
1)
CPU AND
SYSTEM
CONTROL
SIGNALS
----------
/
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·~v
lao, laOA CPU REGISTERS
GND
I'
16111T
ADDRESS BUS
lao,
V-12
Z80A CPU BLOCK DIAGRAM
VT3 DOMESTIC CHARACTER SET
o
1
2
3
4
5
6
7
8
9
B
c
o
E
F
V-13
KEYBOARD STATUS
a.-_ _ _ Key
"'-_ _ _ _ _ New
Present
Key Pressed
"'-_ _ _ _ _ _ _ _ Undefined
~
"'-_________________ Undefined
___________________ Undefined
....________________________ Test
t~ode
"'-_________________________ Ur.defined
~
____________________________________ Ser ial Data from Keyboard
UART STATUS REGISTER AND 64 / 80 SWITCH
eceiver Parity Error
eceiver Framing Error
eceiver Overrun
Receiver Service Request (Data in UART)
Transmit Holding Register Empty
Transmit Register Empty (All Data Sent)
Clear to Send
"-______________________________ 64 / 80 Character Per Line De fault
(1 means switch is off)
TERMI NAL INFOm1ATI ON WORD
Terminal Address from Board SI'ii tches
Terminal 4ddress
Terminal Address
Terminal Address
Terminal Address
Vertical Retrace On
- - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Odd Count in Progress
______________________________ 50 Hz Switch Set
V-14
VT3 STATUS BYTE
L.-_ _
Read Enabled (Set by Controller)
_ _ _ _ _ _ Busy (Writing)
""-_ _ _ _ _ _ _ Undefined
....._ _ _ _ _ _ _ _ _ bO CHARAClER t·100E
SET
....._ _ _ _ _ _ _ _ _ _ _ _ Read Request
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ Flag 2 Set
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Flag 3 Set
....._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ lnoperable (Set by Controller)
This byte is produced during QSP exchanges by the VT3 to inform
the IOU-39Q of status changes.
V-15
MEMORY DECODING
FOR SELECTING ...
AD bus
CSA{a
Program ROM
$0000 - OFFF
4K
CSAl
Program ROM
$1000 - 1FFF
4K
CSA2
oi sp 1ay RAM
$2000 - 27FF
2K
CSA3
Initialize Scan Row
$3000 - 37FF
2K
CSA3
Blank Scan Row
CSA4
Utility RAM
$4000 - 43FF
lK
CSA5
Utility RAM
$5000 - 53FF
lK
CHIP SELECT SIGNAL ...
i~
,'~
1/0
$38xx
x
=
Don I t ca re
DECODING
CHIP SELECT SIGNAL ...
FOR SELECTING ...
AD bus
$8x
CSCO
SELECT LINE LENGTH and CONTL-N
- Load Status Register -
CSCl
STATE-N
- Read UART Status Register -
$9x
TRANL-N
- Load Transmit Register
$Ax
RECE-N
- Read Receive Register -
$Bx
CA
- Set Request to Send
$Cx
CSC5
TERMINAL STATUS
$Dx
csc6
KEYBOARD IN
$Ex
CSC7
KEYBOARD OUT
$Fx
CSC2
CSC3
CSC4
I
Capacity
Address Lines used:
AD04 - AD07 and AD12 - AD15
V-16
7
5
6
4
3
2
NOTES
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Source Exif Data:
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