Tiva™ C Series TM4C123GH6PM Microcontroller Data Sheet (Rev. E) User Manual
TM4C123GH6PM%20mcu%20manual
User Manual:
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- Tiva™ TM4C123GH6PM Microcontroller
- Table of Contents
- Revision History
- About This Document
- 1. Architectural Overview
- 1.1. Tiva™ C Series Overview
- 1.2. TM4C123GH6PM Microcontroller Overview
- 1.3. TM4C123GH6PM Microcontroller Features
- 1.4. TM4C123GH6PM Microcontroller Hardware Details
- 1.5. Kits
- 1.6. Support Information
- 2. The Cortex-M4F Processor
- 2.1. Block Diagram
- 2.2. Overview
- 2.3. Programming Model
- 2.3.1. Processor Mode and Privilege Levels for Software Execution
- 2.3.2. Stacks
- 2.3.3. Register Map
- 2.3.4. Register Descriptions
- Register 1: Cortex General-Purpose Register 0 (R0)
- Register 2: Cortex General-Purpose Register 1 (R1)
- Register 3: Cortex General-Purpose Register 2 (R2)
- Register 4: Cortex General-Purpose Register 3 (R3)
- Register 5: Cortex General-Purpose Register 4 (R4)
- Register 6: Cortex General-Purpose Register 5 (R5)
- Register 7: Cortex General-Purpose Register 6 (R6)
- Register 8: Cortex General-Purpose Register 7 (R7)
- Register 9: Cortex General-Purpose Register 8 (R8)
- Register 10: Cortex General-Purpose Register 9 (R9)
- Register 11: Cortex General-Purpose Register 10 (R10)
- Register 12: Cortex General-Purpose Register 11 (R11)
- Register 13: Cortex General-Purpose Register 12 (R12)
- Register 14: Stack Pointer (SP)
- Register 15: Link Register (LR)
- Register 16: Program Counter (PC)
- Register 17: Program Status Register (PSR)
- Register 18: Priority Mask Register (PRIMASK)
- Register 19: Fault Mask Register (FAULTMASK)
- Register 20: Base Priority Mask Register (BASEPRI)
- Register 21: Control Register (CONTROL)
- Register 22: Floating-Point Status Control (FPSC)
- 2.3.5. Exceptions and Interrupts
- 2.3.6. Data Types
- 2.4. Memory Model
- 2.5. Exception Model
- 2.6. Fault Handling
- 2.7. Power Management
- 2.8. Instruction Set Summary
- 3. Cortex-M4 Peripherals
- 3.1. Functional Description
- 3.2. Register Map
- 3.3. System Timer (SysTick) Register Descriptions
- 3.4. NVIC Register Descriptions
- Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100
- Register 5: Interrupt 32-63 Set Enable (EN1), offset 0x104
- Register 6: Interrupt 64-95 Set Enable (EN2), offset 0x108
- Register 7: Interrupt 96-127 Set Enable (EN3), offset 0x10C
- Register 8: Interrupt 128-138 Set Enable (EN4), offset 0x110
- Register 9: Interrupt 0-31 Clear Enable (DIS0), offset 0x180
- Register 10: Interrupt 32-63 Clear Enable (DIS1), offset 0x184
- Register 11: Interrupt 64-95 Clear Enable (DIS2), offset 0x188
- Register 12: Interrupt 96-127 Clear Enable (DIS3), offset 0x18C
- Register 13: Interrupt 128-138 Clear Enable (DIS4), offset 0x190
- Register 14: Interrupt 0-31 Set Pending (PEND0), offset 0x200
- Register 15: Interrupt 32-63 Set Pending (PEND1), offset 0x204
- Register 16: Interrupt 64-95 Set Pending (PEND2), offset 0x208
- Register 17: Interrupt 96-127 Set Pending (PEND3), offset 0x20C
- Register 18: Interrupt 128-138 Set Pending (PEND4), offset 0x210
- Register 19: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280
- Register 20: Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284
- Register 21: Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288
- Register 22: Interrupt 96-127 Clear Pending (UNPEND3), offset 0x28C
- Register 23: Interrupt 128-138 Clear Pending (UNPEND4), offset 0x290
- Register 24: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300
- Register 25: Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304
- Register 26: Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308
- Register 27: Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C
- Register 28: Interrupt 128-138 Active Bit (ACTIVE4), offset 0x310
- Register 29: Interrupt 0-3 Priority (PRI0), offset 0x400
- Register 30: Interrupt 4-7 Priority (PRI1), offset 0x404
- Register 31: Interrupt 8-11 Priority (PRI2), offset 0x408
- Register 32: Interrupt 12-15 Priority (PRI3), offset 0x40C
- Register 33: Interrupt 16-19 Priority (PRI4), offset 0x410
- Register 34: Interrupt 20-23 Priority (PRI5), offset 0x414
- Register 35: Interrupt 24-27 Priority (PRI6), offset 0x418
- Register 36: Interrupt 28-31 Priority (PRI7), offset 0x41C
- Register 37: Interrupt 32-35 Priority (PRI8), offset 0x420
- Register 38: Interrupt 36-39 Priority (PRI9), offset 0x424
- Register 39: Interrupt 40-43 Priority (PRI10), offset 0x428
- Register 40: Interrupt 44-47 Priority (PRI11), offset 0x42C
- Register 41: Interrupt 48-51 Priority (PRI12), offset 0x430
- Register 42: Interrupt 52-55 Priority (PRI13), offset 0x434
- Register 43: Interrupt 56-59 Priority (PRI14), offset 0x438
- Register 44: Interrupt 60-63 Priority (PRI15), offset 0x43C
- Register 45: Interrupt 64-67 Priority (PRI16), offset 0x440
- Register 46: Interrupt 68-71 Priority (PRI17), offset 0x444
- Register 47: Interrupt 72-75 Priority (PRI18), offset 0x448
- Register 48: Interrupt 76-79 Priority (PRI19), offset 0x44C
- Register 49: Interrupt 80-83 Priority (PRI20), offset 0x450
- Register 50: Interrupt 84-87 Priority (PRI21), offset 0x454
- Register 51: Interrupt 88-91 Priority (PRI22), offset 0x458
- Register 52: Interrupt 92-95 Priority (PRI23), offset 0x45C
- Register 53: Interrupt 96-99 Priority (PRI24), offset 0x460
- Register 54: Interrupt 100-103 Priority (PRI25), offset 0x464
- Register 55: Interrupt 104-107 Priority (PRI26), offset 0x468
- Register 56: Interrupt 108-111 Priority (PRI27), offset 0x46C
- Register 57: Interrupt 112-115 Priority (PRI28), offset 0x470
- Register 58: Interrupt 116-119 Priority (PRI29), offset 0x474
- Register 59: Interrupt 120-123 Priority (PRI30), offset 0x478
- Register 60: Interrupt 124-127 Priority (PRI31), offset 0x47C
- Register 61: Interrupt 128-131 Priority (PRI32), offset 0x480
- Register 62: Interrupt 132-135 Priority (PRI33), offset 0x484
- Register 63: Interrupt 136-138 Priority (PRI34), offset 0x488
- Register 64: Software Trigger Interrupt (SWTRIG), offset 0xF00
- 3.5. System Control Block (SCB) Register Descriptions
- Register 65: Auxiliary Control (ACTLR), offset 0x008
- Register 66: CPU ID Base (CPUID), offset 0xD00
- Register 67: Interrupt Control and State (INTCTRL), offset 0xD04
- Register 68: Vector Table Offset (VTABLE), offset 0xD08
- Register 69: Application Interrupt and Reset Control (APINT), offset 0xD0C
- Register 70: System Control (SYSCTRL), offset 0xD10
- Register 71: Configuration and Control (CFGCTRL), offset 0xD14
- Register 72: System Handler Priority 1 (SYSPRI1), offset 0xD18
- Register 73: System Handler Priority 2 (SYSPRI2), offset 0xD1C
- Register 74: System Handler Priority 3 (SYSPRI3), offset 0xD20
- Register 75: System Handler Control and State (SYSHNDCTRL), offset 0xD24
- Register 76: Configurable Fault Status (FAULTSTAT), offset 0xD28
- Register 77: Hard Fault Status (HFAULTSTAT), offset 0xD2C
- Register 78: Memory Management Fault Address (MMADDR), offset 0xD34
- Register 79: Bus Fault Address (FAULTADDR), offset 0xD38
- 3.6. Memory Protection Unit (MPU) Register Descriptions
- Register 80: MPU Type (MPUTYPE), offset 0xD90
- Register 81: MPU Control (MPUCTRL), offset 0xD94
- Register 82: MPU Region Number (MPUNUMBER), offset 0xD98
- Register 83: MPU Region Base Address (MPUBASE), offset 0xD9C
- Register 84: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4
- Register 85: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC
- Register 86: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4
- Register 87: MPU Region Attribute and Size (MPUATTR), offset 0xDA0
- Register 88: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8
- Register 89: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0
- Register 90: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8
- 3.7. Floating-Point Unit (FPU) Register Descriptions
- 4. JTAG Interface
- 5. System Control
- 5.1. Signal Description
- 5.2. Functional Description
- 5.2.1. Device Identification
- 5.2.2. Reset Control
- 5.2.3. Non-Maskable Interrupt
- 5.2.4. Power Control
- 5.2.5. Clock Control
- 5.2.5.1. Fundamental Clock Sources
- 5.2.5.2. Clock Configuration
- 5.2.5.3. Precision Internal Oscillator Operation (PIOSC)
- 5.2.5.4. Crystal Configuration for the Main Oscillator (MOSC)
- 5.2.5.5. Main PLL Frequency Configuration
- 5.2.5.6. USB PLL Frequency Configuration
- 5.2.5.7. PLL Modes
- 5.2.5.8. PLL Operation
- 5.2.5.9. Main Oscillator Verification Circuit
- 5.2.6. System Control
- 5.3. Initialization and Configuration
- 5.4. Register Map
- 5.5. System Control Register Descriptions
- Register 1: Device Identification 0 (DID0), offset 0x000
- Register 2: Device Identification 1 (DID1), offset 0x004
- Register 3: Brown-Out Reset Control (PBORCTL), offset 0x030
- Register 4: Raw Interrupt Status (RIS), offset 0x050
- Register 5: Interrupt Mask Control (IMC), offset 0x054
- Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
- Register 7: Reset Cause (RESC), offset 0x05C
- Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
- Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C
- Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
- Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C
- Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
- Register 13: System Properties (SYSPROP), offset 0x14C
- Register 14: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150
- Register 15: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154
- Register 16: PLL Frequency 0 (PLLFREQ0), offset 0x160
- Register 17: PLL Frequency 1 (PLLFREQ1), offset 0x164
- Register 18: PLL Status (PLLSTAT), offset 0x168
- Register 19: Sleep Power Configuration (SLPPWRCFG), offset 0x188
- Register 20: Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C
- Register 21: LDO Sleep Power Control (LDOSPCTL), offset 0x1B4
- Register 22: LDO Sleep Power Calibration (LDOSPCAL), offset 0x1B8
- Register 23: LDO Deep-Sleep Power Control (LDODPCTL), offset 0x1BC
- Register 24: LDO Deep-Sleep Power Calibration (LDODPCAL), offset 0x1C0
- Register 25: Sleep / Deep-Sleep Power Mode Status (SDPMST), offset 0x1CC
- Register 26: Watchdog Timer Peripheral Present (PPWD), offset 0x300
- Register 27: 16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER), offset 0x304
- Register 28: General-Purpose Input/Output Peripheral Present (PPGPIO), offset 0x308
- Register 29: Micro Direct Memory Access Peripheral Present (PPDMA), offset 0x30C
- Register 30: Hibernation Peripheral Present (PPHIB), offset 0x314
- Register 31: Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART), offset 0x318
- Register 32: Synchronous Serial Interface Peripheral Present (PPSSI), offset 0x31C
- Register 33: Inter-Integrated Circuit Peripheral Present (PPI2C), offset 0x320
- Register 34: Universal Serial Bus Peripheral Present (PPUSB), offset 0x328
- Register 35: Controller Area Network Peripheral Present (PPCAN), offset 0x334
- Register 36: Analog-to-Digital Converter Peripheral Present (PPADC), offset 0x338
- Register 37: Analog Comparator Peripheral Present (PPACMP), offset 0x33C
- Register 38: Pulse Width Modulator Peripheral Present (PPPWM), offset 0x340
- Register 39: Quadrature Encoder Interface Peripheral Present (PPQEI), offset 0x344
- Register 40: EEPROM Peripheral Present (PPEEPROM), offset 0x358
- Register 41: 32/64-Bit Wide General-Purpose Timer Peripheral Present (PPWTIMER), offset 0x35C
- Register 42: Watchdog Timer Software Reset (SRWD), offset 0x500
- Register 43: 16/32-Bit General-Purpose Timer Software Reset (SRTIMER), offset 0x504
- Register 44: General-Purpose Input/Output Software Reset (SRGPIO), offset 0x508
- Register 45: Micro Direct Memory Access Software Reset (SRDMA), offset 0x50C
- Register 46: Hibernation Software Reset (SRHIB), offset 0x514
- Register 47: Universal Asynchronous Receiver/Transmitter Software Reset (SRUART), offset 0x518
- Register 48: Synchronous Serial Interface Software Reset (SRSSI), offset 0x51C
- Register 49: Inter-Integrated Circuit Software Reset (SRI2C), offset 0x520
- Register 50: Universal Serial Bus Software Reset (SRUSB), offset 0x528
- Register 51: Controller Area Network Software Reset (SRCAN), offset 0x534
- Register 52: Analog-to-Digital Converter Software Reset (SRADC), offset 0x538
- Register 53: Analog Comparator Software Reset (SRACMP), offset 0x53C
- Register 54: Pulse Width Modulator Software Reset (SRPWM), offset 0x540
- Register 55: Quadrature Encoder Interface Software Reset (SRQEI), offset 0x544
- Register 56: EEPROM Software Reset (SREEPROM), offset 0x558
- Register 57: 32/64-Bit Wide General-Purpose Timer Software Reset (SRWTIMER), offset 0x55C
- Register 58: Watchdog Timer Run Mode Clock Gating Control (RCGCWD), offset 0x600
- Register 59: 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER), offset 0x604
- Register 60: General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO), offset 0x608
- Register 61: Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA), offset 0x60C
- Register 62: Hibernation Run Mode Clock Gating Control (RCGCHIB), offset 0x614
- Register 63: Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART), offset 0x618
- Register 64: Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI), offset 0x61C
- Register 65: Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C), offset 0x620
- Register 66: Universal Serial Bus Run Mode Clock Gating Control (RCGCUSB), offset 0x628
- Register 67: Controller Area Network Run Mode Clock Gating Control (RCGCCAN), offset 0x634
- Register 68: Analog-to-Digital Converter Run Mode Clock Gating Control (RCGCADC), offset 0x638
- Register 69: Analog Comparator Run Mode Clock Gating Control (RCGCACMP), offset 0x63C
- Register 70: Pulse Width Modulator Run Mode Clock Gating Control (RCGCPWM), offset 0x640
- Register 71: Quadrature Encoder Interface Run Mode Clock Gating Control (RCGCQEI), offset 0x644
- Register 72: EEPROM Run Mode Clock Gating Control (RCGCEEPROM), offset 0x658
- Register 73: 32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating Control (RCGCWTIMER), offset 0x65C
- Register 74: Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD), offset 0x700
- Register 75: 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER), offset 0x704
- Register 76: General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO), offset 0x708
- Register 77: Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA), offset 0x70C
- Register 78: Hibernation Sleep Mode Clock Gating Control (SCGCHIB), offset 0x714
- Register 79: Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control (SCGCUART), offset 0x718
- Register 80: Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI), offset 0x71C
- Register 81: Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C), offset 0x720
- Register 82: Universal Serial Bus Sleep Mode Clock Gating Control (SCGCUSB), offset 0x728
- Register 83: Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN), offset 0x734
- Register 84: Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC), offset 0x738
- Register 85: Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP), offset 0x73C
- Register 86: Pulse Width Modulator Sleep Mode Clock Gating Control (SCGCPWM), offset 0x740
- Register 87: Quadrature Encoder Interface Sleep Mode Clock Gating Control (SCGCQEI), offset 0x744
- Register 88: EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM), offset 0x758
- Register 89: 32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating Control (SCGCWTIMER), offset 0x75C
- Register 90: Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD), offset 0x800
- Register 91: 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER), offset 0x804
- Register 92: General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO), offset 0x808
- Register 93: Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA), offset 0x80C
- Register 94: Hibernation Deep-Sleep Mode Clock Gating Control (DCGCHIB), offset 0x814
- Register 95: Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control (DCGCUART), offset 0x818
- Register 96: Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI), offset 0x81C
- Register 97: Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C), offset 0x820
- Register 98: Universal Serial Bus Deep-Sleep Mode Clock Gating Control (DCGCUSB), offset 0x828
- Register 99: Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN), offset 0x834
- Register 100: Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC), offset 0x838
- Register 101: Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP), offset 0x83C
- Register 102: Pulse Width Modulator Deep-Sleep Mode Clock Gating Control (DCGCPWM), offset 0x840
- Register 103: Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control (DCGCQEI), offset 0x844
- Register 104: EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM), offset 0x858
- Register 105: 32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCWTIMER), offset 0x85C
- Register 106: Watchdog Timer Peripheral Ready (PRWD), offset 0xA00
- Register 107: 16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER), offset 0xA04
- Register 108: General-Purpose Input/Output Peripheral Ready (PRGPIO), offset 0xA08
- Register 109: Micro Direct Memory Access Peripheral Ready (PRDMA), offset 0xA0C
- Register 110: Hibernation Peripheral Ready (PRHIB), offset 0xA14
- Register 111: Universal Asynchronous Receiver/Transmitter Peripheral Ready (PRUART), offset 0xA18
- Register 112: Synchronous Serial Interface Peripheral Ready (PRSSI), offset 0xA1C
- Register 113: Inter-Integrated Circuit Peripheral Ready (PRI2C), offset 0xA20
- Register 114: Universal Serial Bus Peripheral Ready (PRUSB), offset 0xA28
- Register 115: Controller Area Network Peripheral Ready (PRCAN), offset 0xA34
- Register 116: Analog-to-Digital Converter Peripheral Ready (PRADC), offset 0xA38
- Register 117: Analog Comparator Peripheral Ready (PRACMP), offset 0xA3C
- Register 118: Pulse Width Modulator Peripheral Ready (PRPWM), offset 0xA40
- Register 119: Quadrature Encoder Interface Peripheral Ready (PRQEI), offset 0xA44
- Register 120: EEPROM Peripheral Ready (PREEPROM), offset 0xA58
- Register 121: 32/64-Bit Wide General-Purpose Timer Peripheral Ready (PRWTIMER), offset 0xA5C
- 5.6. System Control Legacy Register Descriptions
- Register 122: Device Capabilities 0 (DC0), offset 0x008
- Register 123: Device Capabilities 1 (DC1), offset 0x010
- Register 124: Device Capabilities 2 (DC2), offset 0x014
- Register 125: Device Capabilities 3 (DC3), offset 0x018
- Register 126: Device Capabilities 4 (DC4), offset 0x01C
- Register 127: Device Capabilities 5 (DC5), offset 0x020
- Register 128: Device Capabilities 6 (DC6), offset 0x024
- Register 129: Device Capabilities 7 (DC7), offset 0x028
- Register 130: Device Capabilities 8 (DC8), offset 0x02C
- Register 131: Software Reset Control 0 (SRCR0), offset 0x040
- Register 132: Software Reset Control 1 (SRCR1), offset 0x044
- Register 133: Software Reset Control 2 (SRCR2), offset 0x048
- Register 134: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100
- Register 135: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104
- Register 136: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108
- Register 137: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110
- Register 138: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114
- Register 139: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118
- Register 140: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120
- Register 141: Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124
- Register 142: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128
- Register 143: Device Capabilities 9 (DC9), offset 0x190
- Register 144: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0
- 6. System Exception Module
- 7. Hibernation Module
- 7.1. Block Diagram
- 7.2. Signal Description
- 7.3. Functional Description
- 7.3.1. Register Access Timing
- 7.3.2. Hibernation Clock Source
- 7.3.3. System Implementation
- 7.3.4. Battery Management
- 7.3.5. Real-Time Clock
- 7.3.6. Battery-Backed Memory
- 7.3.7. Power Control Using HIB
- 7.3.8. Power Control Using VDD3ON Mode
- 7.3.9. Initiating Hibernate
- 7.3.10. Waking from Hibernate
- 7.3.11. Arbitrary Power Removal
- 7.3.12. Interrupts and Status
- 7.4. Initialization and Configuration
- 7.5. Register Map
- 7.6. Register Descriptions
- Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000
- Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004
- Register 3: Hibernation RTC Load (HIBRTCLD), offset 0x00C
- Register 4: Hibernation Control (HIBCTL), offset 0x010
- Register 5: Hibernation Interrupt Mask (HIBIM), offset 0x014
- Register 6: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018
- Register 7: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C
- Register 8: Hibernation Interrupt Clear (HIBIC), offset 0x020
- Register 9: Hibernation RTC Trim (HIBRTCT), offset 0x024
- Register 10: Hibernation RTC Sub Seconds (HIBRTCSS), offset 0x028
- Register 11: Hibernation Data (HIBDATA), offset 0x030-0x06F
- 8. Internal Memory
- 8.1. Block Diagram
- 8.2. Functional Description
- 8.2.1. SRAM
- 8.2.2. ROM
- 8.2.3. Flash Memory
- 8.2.3.1. Prefetch Buffer
- 8.2.3.2. Flash Memory Protection
- 8.2.3.3. Execute-Only Protection
- 8.2.3.4. Read-Only Protection
- 8.2.3.5. Permanently Disabling Debug
- 8.2.3.6. Interrupts
- 8.2.3.7. Flash Memory Programming
- 8.2.3.8. Basic Program / Erase Operations
- 8.2.3.9. 32-Word Flash Memory Write Buffer
- 8.2.3.10. Non-Volatile Register Programming
- 8.2.4. EEPROM
- 8.3. Register Map
- 8.4. Flash Memory Register Descriptions (Flash Control Offset)
- Register 1: Flash Memory Address (FMA), offset 0x000
- Register 2: Flash Memory Data (FMD), offset 0x004
- Register 3: Flash Memory Control (FMC), offset 0x008
- Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C
- Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010
- Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014
- Register 7: Flash Memory Control 2 (FMC2), offset 0x020
- Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030
- Register 9: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C
- Register 10: Flash Size (FSIZE), offset 0xFC0
- Register 11: SRAM Size (SSIZE), offset 0xFC4
- Register 12: ROM Software Map (ROMSWMAP), offset 0xFCC
- 8.5. EEPROM Register Descriptions (EEPROM Offset)
- Register 13: EEPROM Size Information (EESIZE), offset 0x000
- Register 14: EEPROM Current Block (EEBLOCK), offset 0x004
- Register 15: EEPROM Current Offset (EEOFFSET), offset 0x008
- Register 16: EEPROM Read-Write (EERDWR), offset 0x010
- Register 17: EEPROM Read-Write with Increment (EERDWRINC), offset 0x014
- Register 18: EEPROM Done Status (EEDONE), offset 0x018
- Register 19: EEPROM Support Control and Status (EESUPP), offset 0x01C
- Register 20: EEPROM Unlock (EEUNLOCK), offset 0x020
- Register 21: EEPROM Protection (EEPROT), offset 0x030
- Register 22: EEPROM Password (EEPASS0), offset 0x034
- Register 23: EEPROM Password (EEPASS1), offset 0x038
- Register 24: EEPROM Password (EEPASS2), offset 0x03C
- Register 25: EEPROM Interrupt (EEINT), offset 0x040
- Register 26: EEPROM Block Hide (EEHIDE), offset 0x050
- Register 27: EEPROM Debug Mass Erase (EEDBGME), offset 0x080
- Register 28: EEPROM Peripheral Properties (EEPROMPP), offset 0xFC0
- 8.6. Memory Register Descriptions (System Control Offset)
- Register 29: ROM Control (RMCTL), offset 0x0F0
- Register 30: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200
- Register 31: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204
- Register 32: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208
- Register 33: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C
- Register 34: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400
- Register 35: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404
- Register 36: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408
- Register 37: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C
- Register 38: Boot Configuration (BOOTCFG), offset 0x1D0
- Register 39: User Register 0 (USER_REG0), offset 0x1E0
- Register 40: User Register 1 (USER_REG1), offset 0x1E4
- Register 41: User Register 2 (USER_REG2), offset 0x1E8
- Register 42: User Register 3 (USER_REG3), offset 0x1EC
- 9. Micro Direct Memory Access (μDMA)
- 9.1. Block Diagram
- 9.2. Functional Description
- 9.3. Initialization and Configuration
- 9.4. Register Map
- 9.5. μDMA Channel Control Structure
- 9.6. μDMA Register Descriptions
- Register 4: DMA Status (DMASTAT), offset 0x000
- Register 5: DMA Configuration (DMACFG), offset 0x004
- Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008
- Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C
- Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010
- Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014
- Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018
- Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C
- Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020
- Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024
- Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028
- Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C
- Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030
- Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034
- Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038
- Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C
- Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C
- Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500
- Register 22: DMA Channel Interrupt Status (DMACHIS), offset 0x504
- Register 23: DMA Channel Map Select 0 (DMACHMAP0), offset 0x510
- Register 24: DMA Channel Map Select 1 (DMACHMAP1), offset 0x514
- Register 25: DMA Channel Map Select 2 (DMACHMAP2), offset 0x518
- Register 26: DMA Channel Map Select 3 (DMACHMAP3), offset 0x51C
- Register 27: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0
- Register 28: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4
- Register 29: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8
- Register 30: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC
- Register 31: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0
- Register 32: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0
- Register 33: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4
- Register 34: DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8
- Register 35: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC
- 10. General-Purpose Input/Outputs (GPIOs)
- 10.1. Signal Description
- 10.2. Functional Description
- 10.3. Initialization and Configuration
- 10.4. Register Map
- 10.5. Register Descriptions
- Register 1: GPIO Data (GPIODATA), offset 0x000
- Register 2: GPIO Direction (GPIODIR), offset 0x400
- Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404
- Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
- Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C
- Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410
- Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414
- Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
- Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C
- Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
- Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
- Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504
- Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508
- Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C
- Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
- Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514
- Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518
- Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
- Register 19: GPIO Lock (GPIOLOCK), offset 0x520
- Register 20: GPIO Commit (GPIOCR), offset 0x524
- Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528
- Register 22: GPIO Port Control (GPIOPCTL), offset 0x52C
- Register 23: GPIO ADC Control (GPIOADCCTL), offset 0x530
- Register 24: GPIO DMA Control (GPIODMACTL), offset 0x534
- Register 25: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0
- Register 26: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4
- Register 27: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8
- Register 28: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC
- Register 29: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0
- Register 30: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4
- Register 31: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8
- Register 32: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC
- Register 33: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0
- Register 34: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4
- Register 35: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8
- Register 36: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC
- 11. General-Purpose Timers
- 11.1. Block Diagram
- 11.2. Signal Description
- 11.3. Functional Description
- 11.4. Initialization and Configuration
- 11.5. Register Map
- 11.6. Register Descriptions
- Register 1: GPTM Configuration (GPTMCFG), offset 0x000
- Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004
- Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008
- Register 4: GPTM Control (GPTMCTL), offset 0x00C
- Register 5: GPTM Synchronize (GPTMSYNC), offset 0x010
- Register 6: GPTM Interrupt Mask (GPTMIMR), offset 0x018
- Register 7: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
- Register 8: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
- Register 9: GPTM Interrupt Clear (GPTMICR), offset 0x024
- Register 10: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028
- Register 11: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C
- Register 12: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030
- Register 13: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034
- Register 14: GPTM Timer A Prescale (GPTMTAPR), offset 0x038
- Register 15: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C
- Register 16: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040
- Register 17: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044
- Register 18: GPTM Timer A (GPTMTAR), offset 0x048
- Register 19: GPTM Timer B (GPTMTBR), offset 0x04C
- Register 20: GPTM Timer A Value (GPTMTAV), offset 0x050
- Register 21: GPTM Timer B Value (GPTMTBV), offset 0x054
- Register 22: GPTM RTC Predivide (GPTMRTCPD), offset 0x058
- Register 23: GPTM Timer A Prescale Snapshot (GPTMTAPS), offset 0x05C
- Register 24: GPTM Timer B Prescale Snapshot (GPTMTBPS), offset 0x060
- Register 25: GPTM Timer A Prescale Value (GPTMTAPV), offset 0x064
- Register 26: GPTM Timer B Prescale Value (GPTMTBPV), offset 0x068
- Register 27: GPTM Peripheral Properties (GPTMPP), offset 0xFC0
- 12. Watchdog Timers
- 12.1. Block Diagram
- 12.2. Functional Description
- 12.3. Initialization and Configuration
- 12.4. Register Map
- 12.5. Register Descriptions
- Register 1: Watchdog Load (WDTLOAD), offset 0x000
- Register 2: Watchdog Value (WDTVALUE), offset 0x004
- Register 3: Watchdog Control (WDTCTL), offset 0x008
- Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C
- Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010
- Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014
- Register 7: Watchdog Test (WDTTEST), offset 0x418
- Register 8: Watchdog Lock (WDTLOCK), offset 0xC00
- Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0
- Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4
- Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8
- Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC
- Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0
- Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4
- Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8
- Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC
- Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0
- Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4
- Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8
- Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC
- 13. Analog-to-Digital Converter (ADC)
- 13.1. Block Diagram
- 13.2. Signal Description
- 13.3. Functional Description
- 13.4. Initialization and Configuration
- 13.5. Register Map
- 13.6. Register Descriptions
- Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000
- Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004
- Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
- Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C
- Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010
- Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014
- Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018
- Register 8: ADC Trigger Source Select (ADCTSSEL), offset 0x01C
- Register 9: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020
- Register 10: ADC Sample Phase Control (ADCSPC), offset 0x024
- Register 11: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028
- Register 12: ADC Sample Averaging Control (ADCSAC), offset 0x030
- Register 13: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034
- Register 14: ADC Control (ADCCTL), offset 0x038
- Register 15: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040
- Register 16: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044
- Register 17: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048
- Register 18: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068
- Register 19: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088
- Register 20: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8
- Register 21: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C
- Register 22: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C
- Register 23: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C
- Register 24: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC
- Register 25: ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050
- Register 26: ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054
- Register 27: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060
- Register 28: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080
- Register 29: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064
- Register 30: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084
- Register 31: ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070
- Register 32: ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090
- Register 33: ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074
- Register 34: ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094
- Register 35: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0
- Register 36: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4
- Register 37: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0
- Register 38: ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4
- Register 39: ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00
- Register 40: ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00
- Register 41: ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04
- Register 42: ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08
- Register 43: ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C
- Register 44: ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10
- Register 45: ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14
- Register 46: ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18
- Register 47: ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C
- Register 48: ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40
- Register 49: ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44
- Register 50: ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48
- Register 51: ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C
- Register 52: ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50
- Register 53: ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54
- Register 54: ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58
- Register 55: ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C
- Register 56: ADC Peripheral Properties (ADCPP), offset 0xFC0
- Register 57: ADC Peripheral Configuration (ADCPC), offset 0xFC4
- Register 58: ADC Clock Configuration (ADCCC), offset 0xFC8
- 14. Universal Asynchronous Receivers/Transmitters (UARTs)
- 14.1. Block Diagram
- 14.2. Signal Description
- 14.3. Functional Description
- 14.4. Initialization and Configuration
- 14.5. Register Map
- 14.6. Register Descriptions
- Register 1: UART Data (UARTDR), offset 0x000
- Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004
- Register 3: UART Flag (UARTFR), offset 0x018
- Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020
- Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024
- Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028
- Register 7: UART Line Control (UARTLCRH), offset 0x02C
- Register 8: UART Control (UARTCTL), offset 0x030
- Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
- Register 10: UART Interrupt Mask (UARTIM), offset 0x038
- Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C
- Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
- Register 13: UART Interrupt Clear (UARTICR), offset 0x044
- Register 14: UART DMA Control (UARTDMACTL), offset 0x048
- Register 15: UART 9-Bit Self Address (UART9BITADDR), offset 0x0A4
- Register 16: UART 9-Bit Self Address Mask (UART9BITAMASK), offset 0x0A8
- Register 17: UART Peripheral Properties (UARTPP), offset 0xFC0
- Register 18: UART Clock Configuration (UARTCC), offset 0xFC8
- Register 19: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0
- Register 20: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4
- Register 21: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8
- Register 22: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC
- Register 23: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0
- Register 24: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4
- Register 25: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8
- Register 26: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC
- Register 27: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0
- Register 28: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4
- Register 29: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8
- Register 30: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
- 15. Synchronous Serial Interface (SSI)
- 15.1. Block Diagram
- 15.2. Signal Description
- 15.3. Functional Description
- 15.3.1. Bit Rate Generation
- 15.3.2. FIFO Operation
- 15.3.3. Interrupts
- 15.3.4. Frame Formats
- 15.3.4.1. Texas Instruments Synchronous Serial Frame Format
- 15.3.4.2. Freescale SPI Frame Format
- 15.3.4.3. Freescale SPI Frame Format with SPO=0 and SPH=0
- 15.3.4.4. Freescale SPI Frame Format with SPO=0 and SPH=1
- 15.3.4.5. Freescale SPI Frame Format with SPO=1 and SPH=0
- 15.3.4.6. Freescale SPI Frame Format with SPO=1 and SPH=1
- 15.3.4.7. MICROWIRE Frame Format
- 15.3.5. DMA Operation
- 15.4. Initialization and Configuration
- 15.5. Register Map
- 15.6. Register Descriptions
- Register 1: SSI Control 0 (SSICR0), offset 0x000
- Register 2: SSI Control 1 (SSICR1), offset 0x004
- Register 3: SSI Data (SSIDR), offset 0x008
- Register 4: SSI Status (SSISR), offset 0x00C
- Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
- Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
- Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
- Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
- Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
- Register 10: SSI DMA Control (SSIDMACTL), offset 0x024
- Register 11: SSI Clock Configuration (SSICC), offset 0xFC8
- Register 12: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0
- Register 13: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4
- Register 14: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8
- Register 15: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC
- Register 16: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0
- Register 17: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4
- Register 18: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8
- Register 19: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC
- Register 20: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0
- Register 21: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4
- Register 22: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8
- Register 23: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC
- 16. Inter-Integrated Circuit (I2C) Interface
- 16.1. Block Diagram
- 16.2. Signal Description
- 16.3. Functional Description
- 16.4. Initialization and Configuration
- 16.5. Register Map
- 16.6. Register Descriptions (I2C Master)
- Register 1: I2C Master Slave Address (I2CMSA), offset 0x000
- Register 2: I2C Master Control/Status (I2CMCS), offset 0x004
- Register 3: I2C Master Data (I2CMDR), offset 0x008
- Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C
- Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010
- Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014
- Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018
- Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C
- Register 9: I2C Master Configuration (I2CMCR), offset 0x020
- Register 10: I2C Master Clock Low Timeout Count (I2CMCLKOCNT), offset 0x024
- Register 11: I2C Master Bus Monitor (I2CMBMON), offset 0x02C
- Register 12: I2C Master Configuration 2 (I2CMCR2), offset 0x038
- 16.7. Register Descriptions (I2C Slave)
- Register 13: I2C Slave Own Address (I2CSOAR), offset 0x800
- Register 14: I2C Slave Control/Status (I2CSCSR), offset 0x804
- Register 15: I2C Slave Data (I2CSDR), offset 0x808
- Register 16: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C
- Register 17: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810
- Register 18: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814
- Register 19: I2C Slave Interrupt Clear (I2CSICR), offset 0x818
- Register 20: I2C Slave Own Address 2 (I2CSOAR2), offset 0x81C
- Register 21: I2C Slave ACK Control (I2CSACKCTL), offset 0x820
- 16.8. Register Descriptions (I2C Status and Control)
- 17. Controller Area Network (CAN) Module
- 17.1. Block Diagram
- 17.2. Signal Description
- 17.3. Functional Description
- 17.3.1. Initialization
- 17.3.2. Operation
- 17.3.3. Transmitting Message Objects
- 17.3.4. Configuring a Transmit Message Object
- 17.3.5. Updating a Transmit Message Object
- 17.3.6. Accepting Received Message Objects
- 17.3.7. Receiving a Data Frame
- 17.3.8. Receiving a Remote Frame
- 17.3.9. Receive/Transmit Priority
- 17.3.10. Configuring a Receive Message Object
- 17.3.11. Handling of Received Message Objects
- 17.3.12. Handling of Interrupts
- 17.3.13. Test Mode
- 17.3.14. Bit Timing Configuration Error Considerations
- 17.3.15. Bit Time and Bit Rate
- 17.3.16. Calculating the Bit Timing Parameters
- 17.4. Register Map
- 17.5. CAN Register Descriptions
- Register 1: CAN Control (CANCTL), offset 0x000
- Register 2: CAN Status (CANSTS), offset 0x004
- Register 3: CAN Error Counter (CANERR), offset 0x008
- Register 4: CAN Bit Timing (CANBIT), offset 0x00C
- Register 5: CAN Interrupt (CANINT), offset 0x010
- Register 6: CAN Test (CANTST), offset 0x014
- Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018
- Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020
- Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080
- Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024
- Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084
- Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028
- Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088
- Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C
- Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C
- Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030
- Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090
- Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034
- Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094
- Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038
- Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098
- Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C
- Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040
- Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044
- Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048
- Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C
- Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0
- Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4
- Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8
- Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100
- Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104
- Register 32: CAN New Data 1 (CANNWDA1), offset 0x120
- Register 33: CAN New Data 2 (CANNWDA2), offset 0x124
- Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140
- Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144
- Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160
- Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164
- 18. Universal Serial Bus (USB) Controller
- 18.1. Block Diagram
- 18.2. Signal Description
- 18.3. Functional Description
- 18.3.1. Operation as a Device
- 18.3.2. Operation as a Host
- 18.3.3. OTG Mode
- 18.3.4. DMA Operation
- 18.4. Initialization and Configuration
- 18.5. Register Map
- 18.6. Register Descriptions
- Register 1: USB Device Functional Address (USBFADDR), offset 0x000
- Register 2: USB Power (USBPOWER), offset 0x001
- Register 3: USB Transmit Interrupt Status (USBTXIS), offset 0x002
- Register 4: USB Receive Interrupt Status (USBRXIS), offset 0x004
- Register 5: USB Transmit Interrupt Enable (USBTXIE), offset 0x006
- Register 6: USB Receive Interrupt Enable (USBRXIE), offset 0x008
- Register 7: USB General Interrupt Status (USBIS), offset 0x00A
- Register 8: USB Interrupt Enable (USBIE), offset 0x00B
- Register 9: USB Frame Value (USBFRAME), offset 0x00C
- Register 10: USB Endpoint Index (USBEPIDX), offset 0x00E
- Register 11: USB Test Mode (USBTEST), offset 0x00F
- Register 12: USB FIFO Endpoint 0 (USBFIFO0), offset 0x020
- Register 13: USB FIFO Endpoint 1 (USBFIFO1), offset 0x024
- Register 14: USB FIFO Endpoint 2 (USBFIFO2), offset 0x028
- Register 15: USB FIFO Endpoint 3 (USBFIFO3), offset 0x02C
- Register 16: USB FIFO Endpoint 4 (USBFIFO4), offset 0x030
- Register 17: USB FIFO Endpoint 5 (USBFIFO5), offset 0x034
- Register 18: USB FIFO Endpoint 6 (USBFIFO6), offset 0x038
- Register 19: USB FIFO Endpoint 7 (USBFIFO7), offset 0x03C
- Register 20: USB Device Control (USBDEVCTL), offset 0x060
- Register 21: USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ), offset 0x062
- Register 22: USB Receive Dynamic FIFO Sizing (USBRXFIFOSZ), offset 0x063
- Register 23: USB Transmit FIFO Start Address (USBTXFIFOADD), offset 0x064
- Register 24: USB Receive FIFO Start Address (USBRXFIFOADD), offset 0x066
- Register 25: USB Connect Timing (USBCONTIM), offset 0x07A
- Register 26: USB OTG VBUS Pulse Timing (USBVPLEN), offset 0x07B
- Register 27: USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF), offset 0x07D
- Register 28: USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF), offset 0x07E
- Register 29: USB Transmit Functional Address Endpoint 0 (USBTXFUNCADDR0), offset 0x080
- Register 30: USB Transmit Functional Address Endpoint 1 (USBTXFUNCADDR1), offset 0x088
- Register 31: USB Transmit Functional Address Endpoint 2 (USBTXFUNCADDR2), offset 0x090
- Register 32: USB Transmit Functional Address Endpoint 3 (USBTXFUNCADDR3), offset 0x098
- Register 33: USB Transmit Functional Address Endpoint 4 (USBTXFUNCADDR4), offset 0x0A0
- Register 34: USB Transmit Functional Address Endpoint 5 (USBTXFUNCADDR5), offset 0x0A8
- Register 35: USB Transmit Functional Address Endpoint 6 (USBTXFUNCADDR6), offset 0x0B0
- Register 36: USB Transmit Functional Address Endpoint 7 (USBTXFUNCADDR7), offset 0x0B8
- Register 37: USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0), offset 0x082
- Register 38: USB Transmit Hub Address Endpoint 1 (USBTXHUBADDR1), offset 0x08A
- Register 39: USB Transmit Hub Address Endpoint 2 (USBTXHUBADDR2), offset 0x092
- Register 40: USB Transmit Hub Address Endpoint 3 (USBTXHUBADDR3), offset 0x09A
- Register 41: USB Transmit Hub Address Endpoint 4 (USBTXHUBADDR4), offset 0x0A2
- Register 42: USB Transmit Hub Address Endpoint 5 (USBTXHUBADDR5), offset 0x0AA
- Register 43: USB Transmit Hub Address Endpoint 6 (USBTXHUBADDR6), offset 0x0B2
- Register 44: USB Transmit Hub Address Endpoint 7 (USBTXHUBADDR7), offset 0x0BA
- Register 45: USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0), offset 0x083
- Register 46: USB Transmit Hub Port Endpoint 1 (USBTXHUBPORT1), offset 0x08B
- Register 47: USB Transmit Hub Port Endpoint 2 (USBTXHUBPORT2), offset 0x093
- Register 48: USB Transmit Hub Port Endpoint 3 (USBTXHUBPORT3), offset 0x09B
- Register 49: USB Transmit Hub Port Endpoint 4 (USBTXHUBPORT4), offset 0x0A3
- Register 50: USB Transmit Hub Port Endpoint 5 (USBTXHUBPORT5), offset 0x0AB
- Register 51: USB Transmit Hub Port Endpoint 6 (USBTXHUBPORT6), offset 0x0B3
- Register 52: USB Transmit Hub Port Endpoint 7 (USBTXHUBPORT7), offset 0x0BB
- Register 53: USB Receive Functional Address Endpoint 1 (USBRXFUNCADDR1), offset 0x08C
- Register 54: USB Receive Functional Address Endpoint 2 (USBRXFUNCADDR2), offset 0x094
- Register 55: USB Receive Functional Address Endpoint 3 (USBRXFUNCADDR3), offset 0x09C
- Register 56: USB Receive Functional Address Endpoint 4 (USBRXFUNCADDR4), offset 0x0A4
- Register 57: USB Receive Functional Address Endpoint 5 (USBRXFUNCADDR5), offset 0x0AC
- Register 58: USB Receive Functional Address Endpoint 6 (USBRXFUNCADDR6), offset 0x0B4
- Register 59: USB Receive Functional Address Endpoint 7 (USBRXFUNCADDR7), offset 0x0BC
- Register 60: USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1), offset 0x08E
- Register 61: USB Receive Hub Address Endpoint 2 (USBRXHUBADDR2), offset 0x096
- Register 62: USB Receive Hub Address Endpoint 3 (USBRXHUBADDR3), offset 0x09E
- Register 63: USB Receive Hub Address Endpoint 4 (USBRXHUBADDR4), offset 0x0A6
- Register 64: USB Receive Hub Address Endpoint 5 (USBRXHUBADDR5), offset 0x0AE
- Register 65: USB Receive Hub Address Endpoint 6 (USBRXHUBADDR6), offset 0x0B6
- Register 66: USB Receive Hub Address Endpoint 7 (USBRXHUBADDR7), offset 0x0BE
- Register 67: USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1), offset 0x08F
- Register 68: USB Receive Hub Port Endpoint 2 (USBRXHUBPORT2), offset 0x097
- Register 69: USB Receive Hub Port Endpoint 3 (USBRXHUBPORT3), offset 0x09F
- Register 70: USB Receive Hub Port Endpoint 4 (USBRXHUBPORT4), offset 0x0A7
- Register 71: USB Receive Hub Port Endpoint 5 (USBRXHUBPORT5), offset 0x0AF
- Register 72: USB Receive Hub Port Endpoint 6 (USBRXHUBPORT6), offset 0x0B7
- Register 73: USB Receive Hub Port Endpoint 7 (USBRXHUBPORT7), offset 0x0BF
- Register 74: USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1), offset 0x110
- Register 75: USB Maximum Transmit Data Endpoint 2 (USBTXMAXP2), offset 0x120
- Register 76: USB Maximum Transmit Data Endpoint 3 (USBTXMAXP3), offset 0x130
- Register 77: USB Maximum Transmit Data Endpoint 4 (USBTXMAXP4), offset 0x140
- Register 78: USB Maximum Transmit Data Endpoint 5 (USBTXMAXP5), offset 0x150
- Register 79: USB Maximum Transmit Data Endpoint 6 (USBTXMAXP6), offset 0x160
- Register 80: USB Maximum Transmit Data Endpoint 7 (USBTXMAXP7), offset 0x170
- Register 81: USB Control and Status Endpoint 0 Low (USBCSRL0), offset 0x102
- Register 82: USB Control and Status Endpoint 0 High (USBCSRH0), offset 0x103
- Register 83: USB Receive Byte Count Endpoint 0 (USBCOUNT0), offset 0x108
- Register 84: USB Type Endpoint 0 (USBTYPE0), offset 0x10A
- Register 85: USB NAK Limit (USBNAKLMT), offset 0x10B
- Register 86: USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1), offset 0x112
- Register 87: USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2), offset 0x122
- Register 88: USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3), offset 0x132
- Register 89: USB Transmit Control and Status Endpoint 4 Low (USBTXCSRL4), offset 0x142
- Register 90: USB Transmit Control and Status Endpoint 5 Low (USBTXCSRL5), offset 0x152
- Register 91: USB Transmit Control and Status Endpoint 6 Low (USBTXCSRL6), offset 0x162
- Register 92: USB Transmit Control and Status Endpoint 7 Low (USBTXCSRL7), offset 0x172
- Register 93: USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1), offset 0x113
- Register 94: USB Transmit Control and Status Endpoint 2 High (USBTXCSRH2), offset 0x123
- Register 95: USB Transmit Control and Status Endpoint 3 High (USBTXCSRH3), offset 0x133
- Register 96: USB Transmit Control and Status Endpoint 4 High (USBTXCSRH4), offset 0x143
- Register 97: USB Transmit Control and Status Endpoint 5 High (USBTXCSRH5), offset 0x153
- Register 98: USB Transmit Control and Status Endpoint 6 High (USBTXCSRH6), offset 0x163
- Register 99: USB Transmit Control and Status Endpoint 7 High (USBTXCSRH7), offset 0x173
- Register 100: USB Maximum Receive Data Endpoint 1 (USBRXMAXP1), offset 0x114
- Register 101: USB Maximum Receive Data Endpoint 2 (USBRXMAXP2), offset 0x124
- Register 102: USB Maximum Receive Data Endpoint 3 (USBRXMAXP3), offset 0x134
- Register 103: USB Maximum Receive Data Endpoint 4 (USBRXMAXP4), offset 0x144
- Register 104: USB Maximum Receive Data Endpoint 5 (USBRXMAXP5), offset 0x154
- Register 105: USB Maximum Receive Data Endpoint 6 (USBRXMAXP6), offset 0x164
- Register 106: USB Maximum Receive Data Endpoint 7 (USBRXMAXP7), offset 0x174
- Register 107: USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1), offset 0x116
- Register 108: USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2), offset 0x126
- Register 109: USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3), offset 0x136
- Register 110: USB Receive Control and Status Endpoint 4 Low (USBRXCSRL4), offset 0x146
- Register 111: USB Receive Control and Status Endpoint 5 Low (USBRXCSRL5), offset 0x156
- Register 112: USB Receive Control and Status Endpoint 6 Low (USBRXCSRL6), offset 0x166
- Register 113: USB Receive Control and Status Endpoint 7 Low (USBRXCSRL7), offset 0x176
- Register 114: USB Receive Control and Status Endpoint 1 High (USBRXCSRH1), offset 0x117
- Register 115: USB Receive Control and Status Endpoint 2 High (USBRXCSRH2), offset 0x127
- Register 116: USB Receive Control and Status Endpoint 3 High (USBRXCSRH3), offset 0x137
- Register 117: USB Receive Control and Status Endpoint 4 High (USBRXCSRH4), offset 0x147
- Register 118: USB Receive Control and Status Endpoint 5 High (USBRXCSRH5), offset 0x157
- Register 119: USB Receive Control and Status Endpoint 6 High (USBRXCSRH6), offset 0x167
- Register 120: USB Receive Control and Status Endpoint 7 High (USBRXCSRH7), offset 0x177
- Register 121: USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset 0x118
- Register 122: USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset 0x128
- Register 123: USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset 0x138
- Register 124: USB Receive Byte Count Endpoint 4 (USBRXCOUNT4), offset 0x148
- Register 125: USB Receive Byte Count Endpoint 5 (USBRXCOUNT5), offset 0x158
- Register 126: USB Receive Byte Count Endpoint 6 (USBRXCOUNT6), offset 0x168
- Register 127: USB Receive Byte Count Endpoint 7 (USBRXCOUNT7), offset 0x178
- Register 128: USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1), offset 0x11A
- Register 129: USB Host Transmit Configure Type Endpoint 2 (USBTXTYPE2), offset 0x12A
- Register 130: USB Host Transmit Configure Type Endpoint 3 (USBTXTYPE3), offset 0x13A
- Register 131: USB Host Transmit Configure Type Endpoint 4 (USBTXTYPE4), offset 0x14A
- Register 132: USB Host Transmit Configure Type Endpoint 5 (USBTXTYPE5), offset 0x15A
- Register 133: USB Host Transmit Configure Type Endpoint 6 (USBTXTYPE6), offset 0x16A
- Register 134: USB Host Transmit Configure Type Endpoint 7 (USBTXTYPE7), offset 0x17A
- Register 135: USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1), offset 0x11B
- Register 136: USB Host Transmit Interval Endpoint 2 (USBTXINTERVAL2), offset 0x12B
- Register 137: USB Host Transmit Interval Endpoint 3 (USBTXINTERVAL3), offset 0x13B
- Register 138: USB Host Transmit Interval Endpoint 4 (USBTXINTERVAL4), offset 0x14B
- Register 139: USB Host Transmit Interval Endpoint 5 (USBTXINTERVAL5), offset 0x15B
- Register 140: USB Host Transmit Interval Endpoint 6 (USBTXINTERVAL6), offset 0x16B
- Register 141: USB Host Transmit Interval Endpoint 7 (USBTXINTERVAL7), offset 0x17B
- Register 142: USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1), offset 0x11C
- Register 143: USB Host Configure Receive Type Endpoint 2 (USBRXTYPE2), offset 0x12C
- Register 144: USB Host Configure Receive Type Endpoint 3 (USBRXTYPE3), offset 0x13C
- Register 145: USB Host Configure Receive Type Endpoint 4 (USBRXTYPE4), offset 0x14C
- Register 146: USB Host Configure Receive Type Endpoint 5 (USBRXTYPE5), offset 0x15C
- Register 147: USB Host Configure Receive Type Endpoint 6 (USBRXTYPE6), offset 0x16C
- Register 148: USB Host Configure Receive Type Endpoint 7 (USBRXTYPE7), offset 0x17C
- Register 149: USB Host Receive Polling Interval Endpoint 1 (USBRXINTERVAL1), offset 0x11D
- Register 150: USB Host Receive Polling Interval Endpoint 2 (USBRXINTERVAL2), offset 0x12D
- Register 151: USB Host Receive Polling Interval Endpoint 3 (USBRXINTERVAL3), offset 0x13D
- Register 152: USB Host Receive Polling Interval Endpoint 4 (USBRXINTERVAL4), offset 0x14D
- Register 153: USB Host Receive Polling Interval Endpoint 5 (USBRXINTERVAL5), offset 0x15D
- Register 154: USB Host Receive Polling Interval Endpoint 6 (USBRXINTERVAL6), offset 0x16D
- Register 155: USB Host Receive Polling Interval Endpoint 7 (USBRXINTERVAL7), offset 0x17D
- Register 156: USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1), offset 0x304
- Register 157: USB Request Packet Count in Block Transfer Endpoint 2 (USBRQPKTCOUNT2), offset 0x308
- Register 158: USB Request Packet Count in Block Transfer Endpoint 3 (USBRQPKTCOUNT3), offset 0x30C
- Register 159: USB Request Packet Count in Block Transfer Endpoint 4 (USBRQPKTCOUNT4), offset 0x310
- Register 160: USB Request Packet Count in Block Transfer Endpoint 5 (USBRQPKTCOUNT5), offset 0x314
- Register 161: USB Request Packet Count in Block Transfer Endpoint 6 (USBRQPKTCOUNT6), offset 0x318
- Register 162: USB Request Packet Count in Block Transfer Endpoint 7 (USBRQPKTCOUNT7), offset 0x31C
- Register 163: USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS), offset 0x340
- Register 164: USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS), offset 0x342
- Register 165: USB External Power Control (USBEPC), offset 0x400
- Register 166: USB External Power Control Raw Interrupt Status (USBEPCRIS), offset 0x404
- Register 167: USB External Power Control Interrupt Mask (USBEPCIM), offset 0x408
- Register 168: USB External Power Control Interrupt Status and Clear (USBEPCISC), offset 0x40C
- Register 169: USB Device RESUME Raw Interrupt Status (USBDRRIS), offset 0x410
- Register 170: USB Device RESUME Interrupt Mask (USBDRIM), offset 0x414
- Register 171: USB Device RESUME Interrupt Status and Clear (USBDRISC), offset 0x418
- Register 172: USB General-Purpose Control and Status (USBGPCS), offset 0x41C
- Register 173: USB VBUS Droop Control (USBVDC), offset 0x430
- Register 174: USB VBUS Droop Control Raw Interrupt Status (USBVDCRIS), offset 0x434
- Register 175: USB VBUS Droop Control Interrupt Mask (USBVDCIM), offset 0x438
- Register 176: USB VBUS Droop Control Interrupt Status and Clear (USBVDCISC), offset 0x43C
- Register 177: USB ID Valid Detect Raw Interrupt Status (USBIDVRIS), offset 0x444
- Register 178: USB ID Valid Detect Interrupt Mask (USBIDVIM), offset 0x448
- Register 179: USB ID Valid Detect Interrupt Status and Clear (USBIDVISC), offset 0x44C
- Register 180: USB DMA Select (USBDMASEL), offset 0x450
- Register 181: USB Peripheral Properties (USBPP), offset 0xFC0
- 19. Analog Comparators
- 19.1. Block Diagram
- 19.2. Signal Description
- 19.3. Functional Description
- 19.4. Initialization and Configuration
- 19.5. Register Map
- 19.6. Register Descriptions
- Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000
- Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004
- Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008
- Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010
- Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020
- Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040
- Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x024
- Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x044
- Register 9: Analog Comparator Peripheral Properties (ACMPPP), offset 0xFC0
- 20. Pulse Width Modulator (PWM)
- 20.1. Block Diagram
- 20.2. Signal Description
- 20.3. Functional Description
- 20.4. Initialization and Configuration
- 20.5. Register Map
- 20.6. Register Descriptions
- Register 1: PWM Master Control (PWMCTL), offset 0x000
- Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004
- Register 3: PWM Output Enable (PWMENABLE), offset 0x008
- Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C
- Register 5: PWM Output Fault (PWMFAULT), offset 0x010
- Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014
- Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018
- Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C
- Register 9: PWM Status (PWMSTATUS), offset 0x020
- Register 10: PWM Fault Condition Value (PWMFAULTVAL), offset 0x024
- Register 11: PWM Enable Update (PWMENUPD), offset 0x028
- Register 12: PWM0 Control (PWM0CTL), offset 0x040
- Register 13: PWM1 Control (PWM1CTL), offset 0x080
- Register 14: PWM2 Control (PWM2CTL), offset 0x0C0
- Register 15: PWM3 Control (PWM3CTL), offset 0x100
- Register 16: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044
- Register 17: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084
- Register 18: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4
- Register 19: PWM3 Interrupt and Trigger Enable (PWM3INTEN), offset 0x104
- Register 20: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048
- Register 21: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088
- Register 22: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8
- Register 23: PWM3 Raw Interrupt Status (PWM3RIS), offset 0x108
- Register 24: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C
- Register 25: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C
- Register 26: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC
- Register 27: PWM3 Interrupt Status and Clear (PWM3ISC), offset 0x10C
- Register 28: PWM0 Load (PWM0LOAD), offset 0x050
- Register 29: PWM1 Load (PWM1LOAD), offset 0x090
- Register 30: PWM2 Load (PWM2LOAD), offset 0x0D0
- Register 31: PWM3 Load (PWM3LOAD), offset 0x110
- Register 32: PWM0 Counter (PWM0COUNT), offset 0x054
- Register 33: PWM1 Counter (PWM1COUNT), offset 0x094
- Register 34: PWM2 Counter (PWM2COUNT), offset 0x0D4
- Register 35: PWM3 Counter (PWM3COUNT), offset 0x114
- Register 36: PWM0 Compare A (PWM0CMPA), offset 0x058
- Register 37: PWM1 Compare A (PWM1CMPA), offset 0x098
- Register 38: PWM2 Compare A (PWM2CMPA), offset 0x0D8
- Register 39: PWM3 Compare A (PWM3CMPA), offset 0x118
- Register 40: PWM0 Compare B (PWM0CMPB), offset 0x05C
- Register 41: PWM1 Compare B (PWM1CMPB), offset 0x09C
- Register 42: PWM2 Compare B (PWM2CMPB), offset 0x0DC
- Register 43: PWM3 Compare B (PWM3CMPB), offset 0x11C
- Register 44: PWM0 Generator A Control (PWM0GENA), offset 0x060
- Register 45: PWM1 Generator A Control (PWM1GENA), offset 0x0A0
- Register 46: PWM2 Generator A Control (PWM2GENA), offset 0x0E0
- Register 47: PWM3 Generator A Control (PWM3GENA), offset 0x120
- Register 48: PWM0 Generator B Control (PWM0GENB), offset 0x064
- Register 49: PWM1 Generator B Control (PWM1GENB), offset 0x0A4
- Register 50: PWM2 Generator B Control (PWM2GENB), offset 0x0E4
- Register 51: PWM3 Generator B Control (PWM3GENB), offset 0x124
- Register 52: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068
- Register 53: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8
- Register 54: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8
- Register 55: PWM3 Dead-Band Control (PWM3DBCTL), offset 0x128
- Register 56: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C
- Register 57: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC
- Register 58: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC
- Register 59: PWM3 Dead-Band Rising-Edge Delay (PWM3DBRISE), offset 0x12C
- Register 60: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070
- Register 61: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0
- Register 62: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0
- Register 63: PWM3 Dead-Band Falling-Edge-Delay (PWM3DBFALL), offset 0x130
- Register 64: PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074
- Register 65: PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4
- Register 66: PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4
- Register 67: PWM3 Fault Source 0 (PWM3FLTSRC0), offset 0x134
- Register 68: PWM0 Fault Source 1 (PWM0FLTSRC1), offset 0x078
- Register 69: PWM1 Fault Source 1 (PWM1FLTSRC1), offset 0x0B8
- Register 70: PWM2 Fault Source 1 (PWM2FLTSRC1), offset 0x0F8
- Register 71: PWM3 Fault Source 1 (PWM3FLTSRC1), offset 0x138
- Register 72: PWM0 Minimum Fault Period (PWM0MINFLTPER), offset 0x07C
- Register 73: PWM1 Minimum Fault Period (PWM1MINFLTPER), offset 0x0BC
- Register 74: PWM2 Minimum Fault Period (PWM2MINFLTPER), offset 0x0FC
- Register 75: PWM3 Minimum Fault Period (PWM3MINFLTPER), offset 0x13C
- Register 76: PWM0 Fault Pin Logic Sense (PWM0FLTSEN), offset 0x800
- Register 77: PWM1 Fault Pin Logic Sense (PWM1FLTSEN), offset 0x880
- Register 78: PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804
- Register 79: PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884
- Register 80: PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904
- Register 81: PWM3 Fault Status 0 (PWM3FLTSTAT0), offset 0x984
- Register 82: PWM0 Fault Status 1 (PWM0FLTSTAT1), offset 0x808
- Register 83: PWM1 Fault Status 1 (PWM1FLTSTAT1), offset 0x888
- Register 84: PWM2 Fault Status 1 (PWM2FLTSTAT1), offset 0x908
- Register 85: PWM3 Fault Status 1 (PWM3FLTSTAT1), offset 0x988
- Register 86: PWM Peripheral Properties (PWMPP), offset 0xFC0
- 21. Quadrature Encoder Interface (QEI)
- 21.1. Block Diagram
- 21.2. Signal Description
- 21.3. Functional Description
- 21.4. Initialization and Configuration
- 21.5. Register Map
- 21.6. Register Descriptions
- Register 1: QEI Control (QEICTL), offset 0x000
- Register 2: QEI Status (QEISTAT), offset 0x004
- Register 3: QEI Position (QEIPOS), offset 0x008
- Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C
- Register 5: QEI Timer Load (QEILOAD), offset 0x010
- Register 6: QEI Timer (QEITIME), offset 0x014
- Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018
- Register 8: QEI Velocity (QEISPEED), offset 0x01C
- Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020
- Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024
- Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028
- 22. Pin Diagram
- 23. Signal Tables
- 24. Electrical Characteristics
- 24.1. Maximum Ratings
- 24.2. Operating Characteristics
- 24.3. Recommended Operating Conditions
- 24.4. Load Conditions
- 24.5. JTAG and Boundary Scan
- 24.6. Power and Brown-Out
- 24.7. Reset
- 24.8. On-Chip Low Drop-Out (LDO) Regulator
- 24.9. Clocks
- 24.9.1. PLL Specifications
- 24.9.2. PIOSC Specifications
- 24.9.3. Low-Frequency Internal Oscillator (LFIOSC) Specifications
- 24.9.4. Hibernation Clock Source Specifications
- 24.9.5. Main Oscillator Specifications
- 24.9.6. System Clock Specification with ADC Operation
- 24.9.7. System Clock Specification with USB Operation
- 24.10. Sleep Modes
- 24.11. Hibernation Module
- 24.12. Flash Memory and EEPROM
- 24.13. Input/Output Pin Characteristics
- 24.14. Analog-to-Digital Converter (ADC)
- 24.15. Synchronous Serial Interface (SSI)
- 24.16. Inter-Integrated Circuit (I2C) Interface
- 24.17. Universal Serial Bus (USB) Controller
- 24.18. Analog Comparator
- 24.19. Pulse-Width Modulator (PWM)
- 24.20. Current Consumption
- Appendix A. Package Information