TMS32010_Users_Guide_1985 TMS32010 Users Guide 1985
User Manual: TMS32010_Users_Guide_1985
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S32010
User's Guide
",
TEXAS
NSTRUMENTS
TMS32010
User's Guide
Digital Signal Processor Products
."
TEXAS
INSTRUMENTS
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes in the
devices or the device specifications identified in this publication
without notice. TI advises its customers to obtain the latest version
of device specifications to verify, before placing orders, that the
information being relied upon by the customer is current.
TI warrants performance of its semiconductor products, including SNJ
and SMJ, devices, to current specifications in accordance with TI's
standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems such testing necessary to support this
warranty. Unless mandated by government requirements, specific
testing of all parameters of each device is not necessarily performed.
In the absence of written agreement to the contrary, TI assumes no
liability for TI applications assistance, customer's product design, or
infringement of patents or copyrights of third parties by or arising from
use of semiconductor devices described herein. Nor does TI warrant
or represent that any license, either express or implied, is granted
under any patent right, copyright, or other intellectual property right
of TI covering or relating to any combination, machine, or process in
which such semiconductor device might be or are used.
Copyright © 1985, Texas Instruments Incorporated
INTRODUCTION
ARCHITECTURE
INSTRUCTIONS
METHODOLOGY FOR APPLICATION DEVELOPMENT
PROCESSOR RESOURCE MANAGEMENT
INPUT/OUTPUT DESIGN TECHNIQUES
MACRO LANGUAGE INSTRUCTIONS
DIGITAL SIGNAL PROCESSING
TMS32010 DATA SHEET
SMJ32010 DATA SHEET
DEVELOPMENT SUPPORT/PART ORDER INFORMATION
TMS32020 DATA SHEET
TABLE OF CONTENTS
SECTION
PAGE
1.
INTRODUCTION............................................................
1 . 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.2 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Key Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.4 How To Use the TMS32010 Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.4.1 Glossary of Basic TMS32010 Hardware Terms ..........................
1 .4.2 References.....................................................
1-1
1-1
1-1
1-2
1-2
1-4
1-6
2.
ARCHITECTURE............................................................
2.1
Architectural Overview .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2. 1. 1 Harvard Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.2 Arithmetic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 AlU..........................................................
2.2.1.1
Overflow Mode (DVM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.2.2 Accumulator....................................................
2.2.2.1
Accumulator Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.2.3 Multiplier.......................................................
2.2.4 Shifters........................................................
2.2.4.1
Barrel Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.2.4.2 Parallel Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.3. 1 Data Memory Addressing ..........................................
2.3.1.1
Indirect Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.3.1.2 Direct Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.3.1.3 Immediate Addressing .....................................
2.4 Registers.............................................................
2.4.1 Auxiliary Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.4.2 Auxiliary Register Pointer ...........................................
2.5 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1.1
Microcomputer Mode ......................................
2.5. 1.2 Microprocessor Mode ......................................
2.5.2 Using External Program Memory ., ...................................
2.6 Program Counter and Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2 Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2.1
Stack Overflow ..........................................
2.7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7. 1 Saving Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Input/Output Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.1
IN and OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.2 Table Read (TBlR) and Table Write (TBlW) .............................
2.8.3 Address Bus Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 BID Pin ...............................................................
2.10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-12 Clock/Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.13 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.14 Interrupt and BIO System Design ...........................................
2-1
2-1
2-3
2-3
2-4
2-4
2-4
2-5
2-5
2-5
2-6
2-7
2-7
2-7
2-8
2-8
2-9
2-9
2-9
2-10
2-10
2-11
2-11
2-11
2-12
2-13
2-13
2-13
2-14
2-14
2-15
2-15
2-15
2-17
2-18
2-18
2-18
2-19
2-20
2-21
2-24
iii
3.
INSTRUCTIONS .....................................................................
3. 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.2 Addressing Modes. ....... ........ .... ... .... .. ..... ....... . . .. .... . .. .. .. ... ....
3.2.1 Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.2.2 Indirect Addressing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.2.3 Immediate Addressing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.3
Instruction Addressing Format ............ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.3.1 Direct Addressing Format. . . .. . . . . . .. .. . . .... . . . . .. .. . . . . . . . . . . . .. . . . . . . . ..
3.3.2 Indirect Addressing Format. . . . . . . . . ... . . .... . . . . .. .. . . . . . . . . . . . .. .. . . . . . ..
3.3.3 Immediate Addressing Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.3.4 Examples of Opcode Format. .... ... ...... ..... .. . .. .. .. .. ... .. .. .. .. . . . ....
3.4
Instruction Set .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.4.1 Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.4.2 Instruction Set Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.4.3 Instruction Descriptions.. . . . . . . . . . . ... . . . ... . . . . .. .. . . .. . . . .. .. .. .. . . . . . ..
3-1
3-1
3-1
3-1
3-1
3-2
3-2
3-2
3-2
3-2
3-3
3-3
3-3
3-5
3-8
4.
METHODOLOGY FOR APPLICATION DEVELOPMENT ..................... ' ............. . 4-1
Outline of Development Process .................................................. . 4-1
4.1
4.2
Description of Development Facilities .............................................. . 4-2
4.2.1 TMS32010 Evaluation Module ............................................ . 4-2
4.2.2 XDS/320 Macro Assembler/Linker ........................................ . 4-2
4.2.3 XDS/320 Simulator ...................................................... . 4-3
4.2.4 XDS /320 Emu lator ...................................................... . 4-4
4.3 Application Development Process Example ......................................... . 4-4
4.3.1 System Specification ..................................................... . 4-4
4.3.2 System Design .......................................................... . 4-5
4.3.3 Code Development ...................................................... . 4-5
4.3.3.1
Discrete-Time Filter Flowchart .................................... . 4-5
4.3.3.2 FORTRAN Program ............................................. . 4-6
4.3.3.3 Assembly Language Program Using Relocatable Code ............... . 4-6
4.3.3.4 Assembly Language Program Using Absolute Code ................. . 4-13
5.
PROCESSOR RESOURCE MANAGEMENT ............................................. .
5.1
FundamentalOperations ........................................................ .
5.1.1 Bit Manipulation ......................................................... .
5.1.2 Data Shift .............................................................. .
5.1.3 Fixed-Point Arithmetic ... " ............................................... .
5. 1.3.1 Multiplication .................................................. .
5. 1 .3.2 Addition ....................................................... .
5.1.3.3 Division ....................................................... .
5.1.4 Subroutines ............................................................ .
5.1.5 Computed GO TOs ....................................................... .
5.2
Addressing and Loop Control with Auxiliary Registers ............................... .
5.2.1 Auxiliary Register Indirect Addressing ...................................... .
5.2.2 Loop Counter ........................................................... .
5.2.3 Combination of Operational Modes ........................................ .
5.3
Multiplication and Convolution ................................................... .
5.3.1 Pipelined Multiplications .................................................. .
5.3.2 Moving Data ............................................................ .
5.3.3 Product Register ......................................................... .
5.4
Memory Considerations of Harvard Architecture .................................... .
5.4.1 Moving Constants into Data Memory ....................................... .
5.4.2 Data Memory Expansion .................................................. .
5.4.3 Program Memory Expansion .............................................. .
iv
5-1
5-1
5-1
5-1
5-2
5-3
5-5
5-5
5-11
5-12
5-13
5-13
5-13
5-14
5-14
5-14
5-15
5-16
5-16
5-16
5-17
5-18
6.
INPUT/OUTPUT DESIGN TECHNIQUES. . . . .. .. . . .. .. . . . .. .. . .. .. . .... .. . . .. . . . . . .. . . . . .
6.1
Peripheral Device Types.. .. .. .. ... . . .. .. .. ... . . .. .. ....... . .... .. . . .. . . . . . .. .. . . .
6.1.1 Registers .............. ~. . . . .. .. .. . . . . . . . .. .... . .. . .... .. . . .. . . . . . .. . . . . .
6.1.2 FIFOs......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.3 Extended Memory Interface. . . .. .. . . .. . .. . . .. .. . . . .. . .... . . . . .. . . . . . .. . . . . .
6.2 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.1 Software Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.2 Hardware Methods .......................................................
6-1
6-1
6-1
6-2
6-2
6-3
6-3
6-4
7.
MACRO LANGUAGE EXTENSiONS..................................................... 7-1
7. 1 Conventions Used in Macro Descriptions ........................................... 7-1
7.2 Macro Set Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.3 Macro Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.4 Structured Programming Macros .................................................. 7-148
7.5 Utility Subroutines ............................................................... 7-151
8.
DIGITAL SIGNAL PROCESSING ....................................................... .
8.1
A-to-D and D-to-A Conversion ................................................... .
8. 1 . 1 Sample Analysis ......................................................... .
8.1.2 Sample Quantization ..................................................... .
8.2 Basic Theory of Discrete Signals and Systems ...................................... .
8.2.1 Linear Systems .......................................................... .
8.2.2 Fourier Transform Representations ......................................... .
8.3 Design and Implementation of Digital Filters ........................................ .
8.3.1 Digital Filter Structures ................................................... .
8.3.2 Digital Filter Design ...................................................... .
8.4 Quantization Effects ............................................................ .
8.5 Spectrum Analysis .............................................................. .
8.5.1 Discrete Fourier Transform (DFT) .......................................... .
8.5.2 Fast Fourier Transform (FFT) .............................................. .
8.5.3 Uses of the DFT and FFT ................................................. .
8.5.4 Autoregressive Model .................................................... .
8.6 Potential DSP Applications for the TMS32010 ..................................... .
8.6.1 Speech and Audio Processing ............................................. .
8.6.2 Communications ........................................................ .
8.7 References .................................................................... .
8-1
8-1
8-2
8-5
8-6
8-6
8-7
8-9
8-9
8-13
8-18
8-19
8-19
8-20
8-20
8-23
8-24
8-24
8-26
8-28
v
LIST OF APPENDICES
APPENDIX
A
B
C
D
TMS32010
SMJ32010
TMS32010
TMS32020
PAGE
Digital Signal
Digital Signal
Development
Digital Signal
Processor Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support and Part Order Information . . . . . . . . . . . . . . . . . . . . . . ..
Processor Data Sheet .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
A-1
8-1
C-1
D-1
LIST OF ILLUSTRATIONS
FIGURE
PAGE
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-1 5
2-16
2-17
Block Diagram of the TMS320M 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Harvard Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Indirect Addressing Autoincrement/Decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-9
TMS320 Family Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
External Program Memory Expansion Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
TMS32010 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Status Word as Stored by SST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
External Device Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Input/Output Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Table Read and Table Write Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Simplified Interrupt Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
External Frequency Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
TMS3201 0 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Interrupt and BIO Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
4-1
4-2
Flowchart of Typical Application Development ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Flowchart of Filter Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-1
5-2
5-3
Division Routine I Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-7
Division Routine II Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-9
Techniques for Expanding Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
6-1
6-2
6-3
Communication Between Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Typical Analog System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
TMS32010 Extended Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
Block Diagram of Digital Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-1
Analog-to-Digital Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-2
Two Cosine Waves Sampled with Period T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-3
Frequency Components of Three Cosine Waves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-3
D-to-A Conversion Using a Zero-Order Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
An Eight-Level (Three-Bit) Quantizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-5
Quantization as Additive Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-6
Fourier Transform Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-8
Direct Forms I and II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
Cascade Structure for N = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 2
vi
4-1
4-5
8-11
8-12
8-13
8-14
8-15
8-16
8-17
8-18
Fourth-Order Elliptic Digital Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Frequency Response of FIR Lowpass Filter ............... . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Impulse Response of Equiripple Lowpass Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
A Discrete Convolution Using the FFT .................................................
Estimation of Fourier Transform of an Analog Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Short-Time Fourier Analysis of a Doppler Radar Signal .......... . . . . . . . . . . . . . . . . . . . . . . . ..
Spectrum Estimation for Speech Signals ...............................................
Block Diagram of a Digital Modem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8-14
8-17
8-18
8-21
8-22
8-22
8-24
8-27
LIST OF TABLES
TABLE
PAGE
1-1
TMS32010 Hardware Terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-5
2-1
2-2
2-3
2-4
Accumu lator Results ................................................................ 2-4
Accumulator Test Conditions. . . . . .. . . . . .. . . . . . . . . . .. . . .. . . . . . .. .. . . . . .. .. . . .. . . . . . . .. 2-5
Program Memory for the TMS320 Family .............................................. 2-11
TMS32010 Pin Descriptions .......................................................... 2-21
3-1
3-2
Instruction Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Instruction Set Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-4
3-5
4-1
Filter Specifications .................................................................
4-4
7 -1
7-2
Macro Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Macro Set Summary ................................................... , .. ...... .. ..
7-2
7-4
vii
viii
FOREWORD
Digital Signal Processing (DSP) is concerned with the representation of signals (and the information that
they contain) by sequences of numbers, and the transformation or processing of such signal
representations by numerical computation procedures.
Since the late 1950's, scientists and engineers in research labs have been touting the virtues of digital signal
processing, but practical considerations have prevented widespread application. Now, with the availability
of integrated circuits, such as Texas Instruments' TMS320, digital signal processing is leaving the
laboratory and entering the world of application. The reasons for this are numerous and compelling.
Perhaps the most important reason is that extremely sophisticated signal processing functions can be
implemented using digital techniques. Indeed, many of the important DSP techniques are difficult or
impossible to implement using analog (continuous-time) methods. It is almost equally important that VLSI
technology is best suited to the implementation of digital systems, which are inherently more reliable, more
compact, and less sensitive to environmental conditions and component aging than analog systems.
Another advantage of the discrete-time approach is the possibility of time sharing a single processing unit
among a number of different signal processing functions. This is particularly efficient and cost effective in
large systems having many input and output channels. Indeed, until recently, digital processing was only
cost effective where it could be applied in large systems. Now, however, with VLSI techniques, low-cost
processors such as the TMS32010 are available and a wealth of opportunities exist for the application of
DSP techniques.
The potential applications will be found in any area where signals arise as representations of information. In
many cases, the signals represent information about the state of some physical system (including human
beings). Often, the objective in processing the signal is to prepare the signal for digital transmission to a
remote location or for digital storage of the information for later reference. On the other hand, the signal
may be processed to remove distortions introduced by transducers, the signal generation environment, or
by a transmission system. Still another important class of applications arises when information is
automatically extracted from the signal so as to control another system or to infer something about the
properties of the system which generated the signal. Some of the more important areas where the above
types of processing are of interest include speech communication, geophysical exploration,
instrumentation for chemical analysis, image processing for television, audio recording and reproduction,
biomedical instrumentation, acoustical noise measurements, sonar, radar, automatic testing of systems,
and consumer electronics.
In areas such as speech communication research and geophysical exploration, digital signal processing
techniques already have been widely applied using general-purpose digital computers. In other areas,
eConomic factors or processing speed have had limited applications up to recent times. Now, however,
these limitations are subsiding rapidly and digital signal processing will soon be widely used in all the above
mentioned areas and many more.
Ronald W. Schafer
Russell M. Mersereau
Thomas P. Barnwell, III
Atlanta Signal Processors, Inc.
and
Georgia Institute of Technology
School of Electrical Engineering
ix
x
I
INTRODUCTION
1.
INTRODUCTION
1.1
GENERAL DESCRIPTION
The TMS32010 is the first member of the new TMS320 digital signal processing family, designed to
support a wide range of high-speed or numeric-intensive applications. This 16/32-bit single-chip
microcomputer combines the flexibility of a high-speed controller with the numerical capability of
an array processor, thereby offering an inexpensive alternative to multichip bit-slice processors.
The TMS320 family contains the first MOS microcomputers capable of executing five million
instructions per second. This high throughput is the result of the comprehensive, efficient, and
easily programmed instruction set and of the highly pipelined architecture. Special instructions have
been incorporated to speed the execution of digital signal processing (DSP) algorithms.
Development support is available for a variety of host computers. This includes a macro assembler,
linker, simulator, emulator, and evaluation module.
1.2 TYPICAL APPLICATIONS
The TMS320 family's unique versatility and power give the design engineer a new approach to a
variety of complicated applications. In addition, these digital signal processors are capable of
providing the multiple functions often required for a single application. For example, the TMS320
family can enable an industrial robot to synthesize and recognize speech, sense objects with radar
or optical intelligence, and perform mechanical operations through digital servo loop computations.
Some typical applications of the TMS320 family are listed below.
SIGNAL PROCESSING
TELECOMMUNICATIONS
IMAGE PROCESSING
•
Digital filtering
•
Adaptive equalizers
•
Pattern recognition
•
Correlation
•
JL/A law conversion
•
Image enhancement
•
Hilbert transforms
•
Time generators
•
Image compression
•
•
Windowing
Fast Fourier transforms
•
High-speed modems
•
Homomorphic processing
•
Multiple-bit-rate modems
•
Radar and sonar processing
•
Adaptive fiJtering
•
Amplitude, frequency, and phase
•
Waveform generation
•
Speech processing
•
Data encryption
•
Servo links
•
Radar and sonar processing
•
Data scrambling
•
Position and rate control
•
Electronic counter measures
•
Digital filtering
•
Motor control
•
Seismic processing
•
Data compression
•
Missile guidance
•
Spread-spectrum communications
•
Remote feedback control
•
Robotics
INSTRUMENTA TlON
modulation/demodulation
NUMERIC PROCESSING
HIGH-SPEED CONTROL
SPEECH PROCESSING
•
Spectrum analysis
•
Fast multiply/divide
•
Speech analysis
•
Digital filtering
•
Double-precision operations
•
Speech synthesis
•
Phase-locked loops
•
Fast scaling
•
Speech recognition
•
•
Averaging
Arbitrary waveform generation
•
Non-linear function
•
Voice store and forward
•
Transient analysis
computation
•
Vocoders
(i.e., sin x, eX)
•
Speaker authentification
1-1
I
1.3
KEY FEATURES
With an excellent combination of features, the TMS320 family of high-peformance digital signal
processors is a cost-effective alternative to custom VLSI devices and bit-slice systems.
• 200-ns instruction cycle
• 2SS-byte on-chip data RAM
• Microprocessor version - TMS3201 0
I
• Microcomputer version - TMS320M10 -
(3K-byte on-chip program ROM)
• External program memory expansion to a total of SK bytes at full speed
• 16-bit instruction/data word
• 32-bit ALU/accumulator
• 16 x 16-bit multiply in 200 ns
• 0 to 15-bit barrel shifter
• Eight input and eight output channels
• 16-bit bidirectional data bus with 40-megabits-per-second transfer rate
• Interrupt with full context save
• Signed two's complement fixed-point arithmetic
• 2.7-micron NMOS technology
• Single 5- V supply
• 40-pin DIP
The TMS320M10 and the TMS32010 are exactly the same with one exception: the TMS320M10
contains an on-chip masked ROM while the TMS32010 utilizes off-chip program memory.
NOTE
Throughout this document, TMS32010 will refer to both the TMS32010 and the
TM S320 M 10 except where otherwise indicated.
1.4
HOW TO USE THE TMS32010 MANUAL
It is the intent in the design of this user's guide that it be an effective reference book that provides
information for both the hardware and the software engineer about the TMS32010 digital signal
processor, its architecture, instruction set, electrical specifications, interface methods, and
applications.
1-2
(mnemonic)
(mnemonic)
(title of instruction)
Addressing:
Operands:
Operation:
Encoding:
15
14
13
12
11
10
9
8
7
6
5
4
3
I
a
2
Description:
Words:
Cycles:
Example:
BEFORE INSTRUCTION
31
a
AFTER INSTRUCTION
31
a
In the architecture section (Section 2), the design of the device and its hardware features are
described. The instruction section (Section 3) explains individual instructions in detail. The
following format is used for the instruction descriptions in Section 3.4.3 to provide ease of reading
and application.
Section 4 on methodology for application development describes the tools, such as an emulator or
evaluation module, that are available for developing an individual system and gives an example of
TMS32010 software development. In the processor resource management section (Section 5), the
engineer finds a description of the common algorithms or practices to be used for any application.
He becomes familiar with interface techniques in the input/output design techniques section
(Section 6).
The set of macros in the macro language extensions section (Section 7) aids the engineer in
programming and in providing templates for further software development. Another special format
is used for the macro descriptions in Section 7.2. Each macro instruction is named, followed by a
summary table. A flowchart serves to clarify the macro source which is given. Examples of macro
use are also presented. This macro description format is as follows:
1-3
(mnemonic)
TITLE:
(macro)
NAME:
(mnemonic)
(mnemonic)
(title of macro)
OBJECTIVE:
I
ALGORITHM:
CALLING
SEQUENCE:
ENTRY
CONDITIONS:
EXIT
CONDITIONS:
PROGRAM
MEMORY
REQUIRED:
(#words)
DATA
MEMORY
REQUIRED:
STACK
REQUIRED:
(# levels)
EXECUTION
(# cycles)
TIME:
(#words)
FLOWCHART:
SOURCE:
EXAMPLE 1:
EXAMPLE 2:
Section 8 on digital signal processing contains an overview of signal processing theory, algorithms,
and potential applications. The TMS32010 data sheet appears as Appendix A and the SMJ32010
data sheet as Appendix B. Data descriptions of the evaluation module, macro assembler/linker,
simulator, and emulator are presented in Appendix C.
1.4.1
Glossary of Basjc TMS32010 Hardware Terms
Table 1-1 lists in alphabetical order the TMS3201 0 basic hardware units, the symbol for the unit (if
any), and the function of that particular unit.
1-4
TABLE 1-1 - TMS32010 HARDWARE TERMINOLOGY
UNIT
SYMBOL
FUNCTION
Accumulator
ACC
32-bit accumulator
Arithmetic Logic Unit
ALU
Two-port 32-bit arithmetic logic unit
Auxiliary Registers
ARO, AR1
Two 16-bit registers for indirect addressing of data
memory and loop counting control. Nine LSBs of each
register are configured as bidirectional counters
Auxiliary Register Pointer
ARP
Single-bit register
auxiliary register
Data Bus
D Bus
16-bit bus routing data from random access memory
Data Memory Page Pointer
DP
containing
address
of
current
Single-bit register containing page address of data RAM
(1 page
128 words)
=
144 X 16 bit word on-chip random access memory
containing data
Data RAM
Interrupt Flag Register
INTF
Single-bit flag register that indicates an interrupt
request has occurred (is pending)
Interrupt Mode Register
INTM
Single-bit mode register that masks the interrupt flag
16 X 16-bit parallel hardware multiplier
Multiplier
Overflow Flag Register
Overflow Mode Register
P Register
Program Bus
Program Counter
I
OV
Single-bit flag register that indicates an overflow in
arithmetic operations
OVM
Single-bit mode register that defines a saturated or
unsaturated mode in arithmetic operations
P
32-bit register containing product of multiply operations
P Bus
16-bit bus routing instructions from program memory
PC
12-bit register containing address of program memory
Program ROM
1 536 X 1 6-bit word read only memory containing program code (TMS320M 10 only)
Shifter
Two shifters: one is a variable 0-15-bit left-shift barrel
shifter that moves data from the RAM into the ALU.
The other shifter acts on the accumulator when it is
being stored in data RAM; it can left-shift by 0, 1, or 4
bits.
Stack
4 X 12-bit registers for saving program counter contents
in subroutine and interrupt calls
T Register
T
16-bit register containing multiplicand during multiply
operations
1-5
1.4.2
References
The following list of references, including textbooks, contains useful information regarding
functions, operations, and applications of digital processing. These books, in turn, list other
references to many useful technical papers.
Andrews, H.C., Hunt, B. R., DIGITAL IMAGE RESTORATION. Englewood Cliffs, N.J.:
Prentice-Hall, Inc., 1977 .
I
Brigham, E. Oran, THE FAST FOURIER TRANSFORM. Englewood Cliffs, N.J.: Prentice-Hall,
Inc., 1974.
Hamming, R.W., DIGITAL FILTERS. Englewood Cliffs, N.J.: Prentice-Hall, Inc., 1977.
Morris, L. Robert, DIGITAL SIGNAL PROCESSING SOFTWARE. Ottawa, Canada: Carleton
University, 1983.
Oppenheim, Alan V. (Editor), APPLICATIONS OF DIGITAL SIGNAL PROCESSING.
Englewood Cliffs, N.J.: Prentice-Hall, Inc., 1978.
Oppenheim, Alan V., Schafer, R.W., DIGITAL SIGNAL PROCESSING. Englewood Cliffs,
N.J.: Prentice-Hall, Inc., 1975.
Rabiner, Lawrence R., Gold, Bernard, THEORY AND APPLICATION OF DIGITAL SIGNAL
PROCESSING. Englewood Cliffs, N.J.: Prentice-Hall, Inc., 1975.
Rabiner, Lawrence R., Schafer, R.W., DIGITAL PROCESSING OF SPEECH SIGNALS.
Englewood Cliffs, N.J.: Prentice-Hall, Inc., 1978.
1-6
I
ARCHITECTURE
2.
ARCHITECTURE
The TMS320 family utilizes a modified Harvard architecture for speed and flexibility (see Figure 2-1).
In a strict Harvard architecture, program and data memory lie in two separate spaces, permitting a
full overlap of the instruction fetch and execution. The TMS320 family's modification of the Harvard
architecture allows transfers between program and data spaces, thereby increasing the flexibility of
the device. This modification permits coefficients stored in program memory to be read into the
RAM, eliminating the need for a separate coefficient ROM. It also makes available immediate
instructions and subroutines based on computed values.
The TMS32010 utilizes hardware to implement functions that other processors typically perform in
software. For example, the TMS3201 0 contains a hardware multiplier to perform a multiplication in
a single 200-ns cycle. There is also a hardware barrel shifter for shifting data on its way into the
ALU. Finally, extra hardware has been included so that the auxiliary registers, which provide
indirect data RAM addresses, can be configured in an autoincrement/ decrement mode for singlecycle manipulation of data tables. This hardware-intensive approach gives the design engineer the
type of power previously unavailable on a single chip.
2.1
ARCHITECTURAL OVERVIEW
The TMS32010 microcomputers combine the following elements onto a single chip:
•
Volatile 144 x 16-word read/write data memory
•
Non-volatile 1536 X 16-word program memory (TMS320M10 only)
•
Double-precision 32-bit ALU/accumulator
•
Fast 200-ns multiplier
•
Barrel shifter for shifting data memory words into the ALU
•
Shifter that shifts the accumulator into the data RAM
•
16-bit data bus for fetching instruction words from off-chip at full speed
•
4 X 12-bit stack that allows context switching
•
Autoincrementing/decrementing registers for indirect data addressing and loop counting
•
Single-vectored interrupt
•
On-chip oscillator
This section provides a description of these elements. The generic term JTMS3201 0' is used to refer
collectively to the TMS32010 and TMS320M10.
2-1
I
z
~
~
=>
.....J
0
U
~
.....J
X
U
WE
DEN
MEN
BIO
I
MC/MP
INT
RS
N
X
+++
....
---.......
j6
~ 12 LSB
a:
..-
UJ
.....J
.....J
....
-...
~
0
a:
\
,12
0
u
......
I
'~16
PC (12)
INSTRUCTION
...
)'12
-
A ll-AO/
PA2-PAO
MUX
T
I
~
z
..
4~
t ~,
~r
fx -....
w
a:
Cl
Cl
STACK
4 x 12
....
(j)
CJ)
<{
PROGRAM
ROM
(1536 x 16)
I~
............
3
D15-DO
PROGRAM BUS
/
/
4~
~16
~ r 16
16
,
ARO (16) :
ARP .....- - + - - -........---11----1
ARl (16) I
~.
,V
,
T(16)
16
SHIFTER
(0-15)
I
./8
MULTIPLIER
,
P(32)
~
7 32
ADDRESS
DATA RAM
(144 x 16)
N OTE:
ACC
ARP
ARO
AR1
DP
PC
P
T
=
=
=
=
=
=
=
=
,
DATA
Accumulator
I
'\
+
~
32
r
I
/
ALU (32)
"I" 32
32
,~
Auxiliary register pointer
Auxiliary register 0
ACC (32)
Auxiliary register 1
Data page pointer
32
Program counter
P Register
~
+
if'
16
T Register
I
DATA BUS
FIGURE 2-1 -
/32
SHIFTER (0. 1, 4)
16
/
2-2
~ 32
~r
BLOCK DIAGRAM OF THE TMS320M10
,V
16.
~
2.1.1
Harvard Architecture
The TMS320 10 utilizes a modified Harvard architecture in which program memory and data memory
lie in two separate spaces. This permits a full overlap of instruction fetch and execution.
Program memory can lie both on-chip (in the form of the 1536 X 16-word ROM) and off-chip. The
maximum amount of program memory that can be directly addressed is 4K X 16-bit words.
Instructions in off-chip program memory are executed at full speed. Fast memories with access
times of under 100 ns are required.
Data memory is the 144 X 16-bit on-chip data RAM. Instruction operands are fetched from this
RAM; no instruction operands can be directly fetched from off-chip. However, data can be written
into the data RAM from a peripheral by using the IN instruction or read from program memory by
using the TBlR (table read) instruction. The OUT instruction will write a word from the data RAM
to a peripheral, while a TB lW instruction will write a data RAM word to program memory
(presumably, off-chip).
Figure 2-2 outlines the overlap of the instruction prefetch and execution. On the falling edge of
ClKOUT, the program counter (PC) is loaded with the instruction (load PC2) to be prefetched while
the current instruction (execute 1) is decoded and is started to be executed. The next instruction is
then fetched (fetch 2) while the current instruction continues to execute (execute 1). Even as
another prefetch occurs (fetch 3), both the current instruction (execute 2) and the previous
instruction are still executing. This is possible because of a highly pipelined internal operation.
CLKOUT
1..__. . .
L
LOAD
PC 1
.....
•
FETCH 1
•
•LOAD
EXECUTE 1
•
PC 2
......
•
FETCH 2
••
LOAD
PC 3
........
•
EXECUTE 2
FETCH 3
•
..
EXECUTE 3
• ~--------------------~.
FIGURE 2-2 - HARVARD ARCHITECTURE
2.2 ARITHMETIC ELEMENTS
There are four basic arithmetic elements: the AlU, the accumulator, the multiplier, and the shifters.
All arithmetic operations are performed using two's complement arithmetic (see Section 5.1.3).
Most arithmetic instructions will access a word in the data RAM, either directly or indirectly, and
pass it through the barrel shifter. This shifter can left-shift a word 0 to 15 bits, depending on the
value specified by the instruction. The data word then enters the ALU where it is loaded into or
added/subtracted from the accumulator. After a result is obtained in the accumulator, it can be
stored in the data RAM. Since the accumulator is 32 bits, both halves must be stored separately. A
parallel left-shifter is present at the accumulator output to aid in scaling results as they are being
moved to the data RAM.
2-3
2.2.1
ALU
The ALU is a general-purpose arithmetic logic unit that operates with a 32-bit data word. The unit
will add, subtract, and perform logical operations. The accumulator is always the destination and
the primary operand. The result of a logical operation is shown in Table 2-1 . A data memory value is
the operand for the lower half of the accumulator (bits 15 through 0), Zero is the operand for the
upper half of the accumulator.
TABLE 2-1 - ACCUMULATOR RESULTS
FUNCTION
I
e (ACC
XOR
(zero)
AND
(zero) . (ACC bits 31-16)
OR
2.2.1.1
ACCUMULATOR RESULT
ACC BITS 15 THROUGH 0
ACC BITS 31 THROUGH 16
(zero)
+
bits 31-16)
(ACC bits 31-16)
(data memory value)
e
(ACe bits 15-0)
(data memory value) . (ACC bits 15-0)
(data memory value)
+ (ACC
bits 15-0)
Overflow Mode (OVM)
The OVM register is directly under program control, i.e., it is set by the SOVM instruction and reset
by the ROVM instruction. If an overflow occurs when set, the most positive or the most negative
representable value of the ALU will be loaded into the accumulator. Whether it is the most positive
or the most negative value is determined by the overflow sign. If an overflow occurs when reset, the
accumulator is unmodified. (See the SOVM instruction in Section 3.4.3 for further information and
an example.)
In signal processing, arithmetic overflows can create special problems. Since overflows can cause
swings between very large and very small numbers, they will often result in erratic system behavior.
The TMS3201 0 has been designed with a special overflow mode to compensate for this behavior.
When the overflow mode register (OVM) is set by the SOVM instruction (i.e., 1 -+ OVM), an
overflow will cause the largest/smallest representable value of the ALU to be loaded into the
accumulator. This models the saturation processes inherent in analog systems. When the overflow
mode register (OVM) is reset by the ROVM instructions (i.e., 0 --+ OVM), overflow results are loaded
into the accumulator without modification.
The OVM register can be stored in data memory as a single-bit register that is part of the status
register (see Section 2.7). It should not be confused with the overflow flag (OV), explained in
Section 2.2.2.1.
2.2.2
Accumulator
The accumulator stores the output from the ALU and is also often an input to the ALU. It operates
with a 32-bit word length. The accumulator is divided into a high-order word (bits 31 through 16)
and a low-order word (bits 15 through 0). Instructions are provided for storing the high and loworder accumulator words in data memory (SACH and SACL).
2-4
2.2.2.1
Accumulator Status
Accumulator overflow status can be read from the accumulator overflow flag register (OV). This
register will be set if an overflow occurs in the accumulator. Since the OV register is part of the
status register (see Section 2.7), OV status can be stored in data memory. Once the overflow flag
register is set, only the execution of the branch on overflow (BV) instruction or direct modification
of the status register can clear it. This feature permits the examination of overflow results outside of
time-critical loops.
A variety of other accumulator conditions can be tested by the branch instructions given in Table
2-2. These instructions will cause a branch to be executed if the condition is met.
TABLE 2-2 -
INSTRUCTION
Bll
BlEl
BGl
BGEl
BNl
Bl
2.2.3
I
ACCUMULATOR TEST CONDITIONS
ACCUMULATOR CONDITION TESTED
<0
~O
>0
~O
<>0
=0
Multiplier
The 16 X 16-bit parallel multiplier consists of three units: the T register, the P register, and the
multiplier array. The T register is a 16-bit register that stores the multiplicand, while the P register is
a 32-bit register that stores the product.
In order to use the multiplier, the multiplicand must first be loaded into the T register from the data
RAM by using one of the following instructions: LT, LTA, or LTD. Then the MPY (multiply) or the
MPYK (multiply immediate) instruction is executed. If the MPY instruction is used, the multiplier
value is a 16-bit number from the data RAM. If the MPYK instruction is used, the multiplier value is
a 13-bit immediate constant derived from the MPYK instruction word; this 13-bit constant is right
justified and sign extended. After execution of the MPY or MPYK instruction, the product will be
found in the P register. The product can then be added to, subtracted from, or loaded into the
accumulator by executing one of the following instructions: APAC, SPAC, LTA, LTD, or PAC.
Pipelined multiply and accumulate operations at 400-ns rates can be accomplished with the
LTAIL TO and MPY IMPYK instructions (see Section 3.4.3 for greater detail).
There is no convenient way to restore the contents of the P register without altering other registers.
For this reason, special hardware has been incorporated in the TMS32010 to inhibit an interrupt
from occurring until the instruction following the MPY or MPYK instruction has been executed.
Thus, the M PY or M PYK instruction should always be followed by instructions that combine the P
register with the accumulator: PAC, APAC, SPAC, LTA, or LTD. This is almost always done as a
logical consequence of the TMS3201 0 instruction set.
2.2.4
Shifters
There are two shifters available for manipulating data: a barrel shifter for shifting data from the data
RAM into the ALU and a parallel shifter for shifting the accumulator into the data RAM.
2-5
2.2.4.1
Barrel Shifter
The barrel shifter performs a left-shift of 0 to 15 places on all data memory words that are to be loaded into, subtracted from, or added to the accumulator by the LAC, SUB, and ADD instructions.
The barrel shifter zero-fills the low-order bits and sign-extends the 16-bit data memory word to 32
bits by what is called an arithmetic left-shift. An arithmetic left-shift means that the bits to the left of
the M S B of the data word are filled with ones if the M S B is a one or with zeros if the M S B is a zero.
This is different from a logical left-shift where the bits to the left of the MSB are always filled with
zeros. A small amount of code is required to perform an arithmetic right-shift or a logical right-shift
(see Section 5.1.2).
The following examples illustrate the barrel shifter's function:
I
EXAMPLE 1:
Data memory location 20 holds the two's complement number:
> 7EBC
The load accumulator (LAC) instruction is executed, specifying a left-shift of 4:
LAC 20,4
The accumulator would then hold the following 32-bit signed two's complement number:
31
16 15
000
Since the MSB of
7
0
E
> 7EBC is a zero,
B
C
0
the upper accumulator was zero-filled.
EXAMPLE 2:
Data memory location 30 holds the two's complement number:
> 8EBC
The LAC instruction is executed, specifying a left-shift of 8:
LAC 30,8
The accumulator would then hold the following 32-bit signed two's complement number:
F
Since the MSB of
2-6
>
o
16 15
31
F
8
E
B COO
8EBC is a one, the upper accumulator was filled with ones.
There are also instructions that perform operations with the lower half of the accumulator and a
data word without first sign-extending the data word (i.e., treating it as a 16-bit rather than a 32-bit
word). The mnemonics of these instructions typically end with an liS," indicating that signextension is suppressed (e.g., ADDS, SUBS). Along with the instructions that operate on the
upper half of the accumulator, these instructions allow the manipulation of 32-bit precision
numbers.
2.2.4.2
Parallel Shifter
The parallel shifter is activated only by the store high-order accumulator word (SACH) instruction.
This shifter left-shifts the entire 32-bit accumulator and places 16 bits into the data RAM, resulting
in a loss of the accumulator's high-order bits. This shifter can execute a shift of only 0, 1, or 4.
Shifts of 1 and 4 were chosen to be used with multiplication operations (see Section 5.1.3.1). No
right-shift is directly implemented. The following example illustrates the accumulator shifter's
function:
EXAMPLE:
The accumulator holds the 32-bit two's complement number:
31
o
16 15
A
3
4
B
7 8
C 0
The SACH instruction is executed, specifying that a left-shift of four be performed on the
high-order accumulator word before it is stored in data memory location 40:
SACH 40,4
Data memory location 40 then contains the following number:
retains> A34B78CD.
2.3
>
34B7. The accumulator still
DATA MEMORY
Data memory consists of the 144 words of 16-bit width of RAM present on-chip. All non-immediate
data operands reside within this RAM.
Sometimes it is convenient to store data operands off-chip and then read them into the on-chip
RAM as they are needed. Two means are available for doing this. First, there are the table read
(TBlR) and the table write (TBlW) instructions. The table read (TBlR) instruction can transfer
values from program memory, either on-chip ROM or off-chip PROM/RAM, to the on-chip data
RAM. The table write (TBlW) instruction transfers values from the data RAM to program memory,
presumably in the form of off-chip RAM. These instructions take three cycles to execute. The IN
and OUT instructions provide another method. The IN instruction reads data from a peripheral and
transfers it to the data RAM. With some extra hardware, the IN instruction, together with the OUT
instruction, can be used to read and write from the data RAM to large amounts of external storage
addressed as a peripheral (see Section 3.4.3). This method is faster since IN and OUT take only two
cycles to execute.
2.3.1
Data Memory Addressing
There are three forms of data memory addressing: indirect, direct, and immediate.
2-7
I
2.3.1.1
Indirect Addressing
Indirect addressing uses the lower eight bits of the auxiliary registers as the data memory address
(see Section 2.4.1). This is sufficient to address all 144 data words; no paging is necessary with
indirect addressing. The current auxiliary register is selected by the auxiliary register pointer (ARP).
In addition, the auxiliary registers can be made to autoincrement/ decrement during any given
indirect instruction. The increment/decrement occurs AFTER the current instruction is finished
executing.
Some examples of indirect addressing are given below. ARO and AR 1 are predefined assembler
constants with values of 0 and 1, respectively.
Each of the following examples should be viewed as a complete program sequence, rather than
separate isolated statements. Indirect addressing is indicated by an asterisk (*) in these examples
and in the TMS32010 assembler.
I
EXAMPLE 1:
LARP ARO
Load ARP with a zero. This sets ARO as the
current auxiliary register.
Load ARO with a 5.
Add contents of data memory location 5 to
accumulator.
Add contents of data memory location 5 to
accumulator and increment ARO. ARO now
equals 6.
Add contents of data memory location 6 to
accumulator and decrement ARO. ARO now
equals 5.
Add contents of data memory location 5 to
accumulator.
LARK ARO,5
ADD *
ADD *+
ADD *-
ADD *
EXAMPLE 2:
LARK ARO,10
LARK AR1,20
LARP 1
ADD *,O,ARO
ADD * + ,0,AR1
2.3.1.2
Load ARO with the value 10.
Load AR1 with the value 20.
Set ARP to one. This selects AR1 as the current
auxiliary register.
Add contents of data memory location 20 to
accumulator with no shift, then load ARP with
0, selecting ARO as the current auxiliary register.
Add contents of data memory location 10 to
accumulator with no shift, then increment ARO
to have value 11, and load AR P with 1, selecting
AR 1 as the cu rrent auxiliary register.
Direct Addressing
In direct addressing, seven bits of the instruction word are concatenated with the data page pointer
(DP) to form the data memory address. Thus, direct addressing uses the following paging scheme:
DP
o
1
2-8
MEMORY LOCATIONS
0 - 127
128 - 144
Usually the second page of data memory contains infrequently accessed system variables, such as
those used by the interrupt routine.
DP is part of the status register and thus can be stored in data memory (see Section 2.7).
2.3.1.3
Immediate Addressing
The TMS32010 instruction set contains special "immediate" instructions, such as MPYK, LACK,
and LARK. These instructions derive data from part of the instruction word rather than from the
data RAM.
2.4
2.4.1
REGISTERS
I
Auxiliary Registers
There are two 16-bit hardware registers, the auxiliary registers, that are not part of the 144 X 16-bit
data RAM. These auxiliary registers can be used for three functions: temporary storage, indirect
addressing of data memory, and loop control.
Indirect addressing utilizes the least significant eight bits of an auxiliary register as the data memory
address (see Section 2.3.1.1).
The branch on auxiliary register not zero (BANZ) instruction permits these registers to also be used
as loop counters. BANZ checks if an auxiliary register is zero. If not, it decrements and branches.
Thus, loops can be implemented as follows:
LOOP
LARP
ARO
LARK
ARO,5
Load ARP with 0, selecting ARO as the current auxiliary
register.
Load ARO with 5.
ADD
BANZ
*
Indirectly add data memory to accumulator.
LOOP
The above program segment adds data memory locations 5 through 0 to the accumulator.
When the auxiliary registers are autoincrementedl decremented by an indirect addressing
instruction or by BANZ, the lowest nine bits are affected, one more than the lowest eight bits used
for indirect addressing (see Figure 2-3A). This counter portion of an auxiliary register is a circular
counter, as shown in Figures 2-3B and 2-3C.
COUNTER
15
o
INDIRECT ADDRESS
FIGURE 2-3A - AUXILIARY REGISTER COUNTER
2-9
15
AR
o
8
UNAFFECTED
1 1 1 1 1 1 1 1 1
INCREMENT
AR
o
8
15
UNAFFECTED
0 0 0 0 0 0 0 0 0
FIGURE 2-38 - AUTOINCREMENT
15
I
AR
o
8
UNAFFECTED
111111111
DECREMENT
15
AR
UNAFFECTED
FIGURE 2-3C - AUTODECREMENT
FIGURE 2-3 -
INDIRECT ADDRESSING AUTOINCREMENT/DECREMENT
The upper seven bits of an auxiliary register (i.e., bits 9 through 15) are unaffected by any
autoincrement/decrement operation. This includes autoincrement of 111111111 (the lowest nine
bits go to 0) and autodecrement of 000000000 (the lowest nine bits go to 111111111 ) ; in each case,
bits 9 through 15 are unaffected.
The auxiliary registers can be saved in and loaded from the data RAM with the SAR (store auxiliary
register) and LAR (load auxiliary register) instructions. This is useful for performing context saves.
SAR and LAR transfer entire 16-bit values to and from the auxiliary registers even though indirect
addressing and loop counting utilize only a portion of the auxiliary register.
2.4.2
Auxiliary Register Pointer
The auxiliary register pointer (ARP) is a single bit which is part of the status register. It indicates
which auxiliary register is current as follows:
ARP
CURRENT AUXILIARY REGISTER
o
ARO
1
AR1
As part of the status register, the ARP can be stored in memory.
2.5
PROGRAM MEMORY
Program memory consists of up to 4K words of 16-bit width. The TMS320M1 0 has 1536 words of
on-chip ROM, while the TMS32010 is ROMless. Program memory mode of operation is controlled
by the MC/MP pin.
2-10
2.5.1
Modes of Operation
There are two modes of operation defined by the state of the MC/MP pin: the microcomputer
mode and the microprocessor mode. A one (high) level on this pin places the device in the
microcomp'uter mode, and a zero (low) level places a device in the microprocessor mode.
Table 2-3 illustrates the program memory capability of the TMS3201 0 microcomputers for each of
the two modes of operation enabled by the MC/MP pin. Figure 2-4 shows the memory map for
each setting of the MC/MP pin.
2.5.1.1
Microcomputer Mode (TMS320M10)
The microcomputer mode is defined by a one level on the MC/MP pin. Even though the
TMS320M10 has a 1536 X 16-bit on-chip ROM, only locations 0 through 1523 are available for the
user's program. Locations 1524-1535 are reserved by Texas Instruments for testing purposes. The
device architecture allows for an additional 2560 words of program memory to reside off-chip.
2.5.1.2
Microprocessor Mode (TMS320M10 and TMS32010)
The microprocessor mode is defined by a zero level on the MC/MP pin. All 4K words of memory
are external in this mode.
TABLE 2-3 -
MODEL
PROGRAM MEMORY FOR THE TMS320 FAMILY
PROGRAM
MEMORY OPTIONS
MICROCOMPUTER
MODE MEMORY
MC/MP= 1
MICROPROCESSOR
MODE MEMORY
MC/MP=O
TMS320M10
Microcomputer and
microprocessor modes
1 536 words on-chip ROM
and 2560 words of external
memory
4096 words of external
memory
TMS32010
Microprocessor mode only
Not available
4096 words of external
memory
After reset, the TMS3201 0 microcomputers will begin execution at location O. Usually a branch
instruction to the reset routine is contained in locations 0 and 1. Upon interrupt, the TMS32010
microcomputers will begin execution at location 2.
2-11
I
ADDRESS
0
MICROCOMPUTER MODE
MICROPROCESSOR MODE
MC/MP = 1
MC/MP = 0
16-BIT WORD
ADDRESS
RESET 1 ST WORD
RESET 2ND WORD
2
INTERRUPT
I
o
16-BIT WORD
RESET 1 ST WORD
RESET 2ND WORD
INTERNAL
2
INTERRUPT
MEMORY
SPACE
1523
1524
I
-1
,
EXTERNAL
INTERNAL
MEMORY
MEMORY
SPACE
SPACE
RESERVED
1535
1536
FOR TESTING
EXTERNAL
MEMORY
SPACE
,:.;
~
4095
4095
FIGURE 2-4 - TMS320 FAMILY MEMORY MAP
2.5.2
Using External Program Memory
Twelve output pins are available for addressing external memory. These pins are coded Al1 (MSB)
through AO (LSB) and contain the buffered outputs of the program counter or the I/O port address.
When an instruction is fetched from off-chip, the MEN (memory enable) strobe will be generated to
enable the external memory. The instruction word is then transferred to the TMS3201 0 by means of
the data bus. (See Section 2.8.)
When in the microcomputer mode, the TMS320M10 will internally select address locations 1535
and below from the on-chip program memory. The MEN strobe will still become active in this mode,
and the address lines A 11 through AO will still output the current value of the program counter
although the instruction word will be read from internal program memory.
Figure 2-5 gives an example of external program memory expansion. Even when executing from external memory, the TMS3201 0 performs at its full 200-ns instruction cycle. Fast memories under
100-ns access time must be used.
MEN is never active at the same time as the WE or DEN signals. In effect, MEN will go low every
clock cycle except when an I/O function is being performed by the IN, OUT, or TBLW instructions.
In these multicycle instructions, MEN goes low during the clock cycles in which WE or DEN do not
go low.
2-12
TMS32010
-
I
I
16
ADDRESS LINES
MC/MP
-WE
DATA LINES
4K X 16
,
STATIC RAM
12
ANDIOR PROM
-MEN
OUTPUT
ENABLE
CHIP
SELECT
(Only for
RAM)
~W RITE
EN ABLE
-T
I
FIGURE 2-5 - EXTERNAL PROGRAM MEMORY EXPANSION EXAMPLE
2.6
PROGRAM COUNTER AND STACK
The program counter (PC) and stack enable the user to perform branches, subroutine calls, and
interrupts, and to execute the table read (TBlR) and table write (TBlW) instructions (see Section
3.4.3).
2.6.1
Program Counter
The program counter (PC) is a 12-bit register that contains the program memory address of the next
instruction to be executed. The device reads the instruction from the program memory location
addressed by the PC and increments the PC in preparation for the next instruction prefetch. The PC
is initialized to zero by activating the reset (RS) line.
In order to permit the use of external program memory, the PC outputs are buffered to the output
pins, A 11 through AO. The PC outputs appear on the address bus during all modes of operation.
The nine MSBs (A 11 through A3) of the PC have unique outputs assigned to them, while the three
lSBs are multiplexed with the port address field, PA2 through PAO. The port address field is used
by the I/O instructions, IN and OUT.
Program memory is always addressed by the contents of the PC. The contents of the PC can be
changed by a branch instruction if the particular branch condition being tested is true. Otherwise,
the branch instruction simply increments the PC. All branches are absolute, rather than relative,
i.e., a 12-bit value derived from the branch instruction word is loaded directly into the PC in order to
accomplish the branch.
2.6.2
Stack
The stack is 12 bits wide and four layers deep. The PUSH instruction pushes the twelve lSBs of the
accumulator onto the top of stack (TOS). The POP instruction pops the TOS into the twelve lSBs
of the accumulator. Following the POP instruction, the TOS can be moved into data memory by
storing the low-order accumulator word (SACl instruction). This allows expansion of the stack into
the data RAM. From the data RAM, it can easily be copied into program RAM off-chip by using the
TBlW instruction. In this way, the stack can be expanded to very large levels.
If the XDS/320 Emulator is used, one level of the stack is reserved by the emulator, reducing the
number of available stack levels to three.
2-13
2.6.2.1
Stack Overlow
Up to four nested subroutines or interrupts can be accommodated by the device without a stack
overflow if the TB LR and TB LW instructions are not executed. Since TB LR and TB LW utilize one
level of the stack, only three nested subroutines or interrupts can be accommodated without stack
overflow occurring if TBLR or TBLW are executed. If there is a stack overflow, the deepest level of
stack will be lost. If the stack is overpopped, the value at the bottom of the stack will become
copied into higher levels until it fills the stack.
To handle subroutines and interrupts of much higher nesting levels, part of the data RAM or
external RAM can be allocated to stack management. In this case, the top of the stack (TOS) is
popped immediately at the start of a subroutine or interrupt routine and stored in RAM. At the end
of the subroutine or interrupt routine, the stack value stored in RAM is pushed back onto the TOS
before returning to the main routine.
I
2.7
STATUS REGISTER
The status register, shown in Figure 2-6, consists of five status bits. These status bits can be
individually altered through dedicated instructions. In addition, the entire status register can be
saved in data memory through the SST instruction. New values can be reloaded into the status
register using the LST instruction, with the execption of the INTM bit. The INTM bit cannot be
changed through the LST instruction. It can only be changed by the instructions, EINT and DINT
(enable, disable interrupts).
OV
OVM
INTM
ARP
DP
FIGURE 2-6 - TMS32010 STATUS REGISTER
2-14
Accumulator Oveflow Flag Register
(OV)
- Zero indicates that the accumulator has not
overflowed. One indicates that an overflow in the
accumulator has occurred. (See Section 2.2.2.1).
The BV (branch on overflow) instruction will clear
this bit and cause a branch if it is set.
Overflow Mode Bit (OVM)
- Zero means the overflow mode is disabled. One
means the overflow mode is enabled (see Section
2.2.1 .1 ). The SOVM instruction loads the OVM bit
with a one; the ROVM instruction loads the OVM bit
instruction with a zero.
Interrupt Mask Bit (INTM)
- Zero means an interrupt is enabled. One means an
interrupt is disabled. The EINT instruction loads the
INTM bit with a zero; DINT loads the INTM bit with
a one. When an interrupt is executed, the INTM
register is automatically set to one before the
interrupt service routine begins. (See Section 2.10.)
Note that the INTM bit can only be altered by
executing the EINT and DINT instructions. Unlike
the rest of the status bits, the INTM bit cannot be
loaded with a new value by the LST instruction.
2.7.1
Auxiliary Register Pointer (ARP)
- Zero selects ARO. One selects AR 1. The AR P also
can be changed by executing the MAR or LAR P
instruction, or by instructions that permit the
indirect addressing option.
Data Memory Page Pointer (DP)
- Zero selects first 128 words of data memory, i.e.,
page zero. One selects last 16 words of data
memory, i.e., page one. The DP can also be
changed by executing either the LDP or the LDPK
instruction.
Saving Status Register
The contents of the status register call be stored in data memory by executing the SST instruction.
If the SST instruction is executed using the direct addressing mode, the device automatically stores
this information on page one of data memory at the location specified by the instruction. Thus, an
SST instruction using the direct addressing mode can only specify an address less than 16, since
the second page of memory contains only 16 words. If the indirect addressing mode is selected,
then the contents of the status register may be stored in any RAM location selected by the auxiliary
register.
The SST instruction does not modify the contents of the status register. Figure 2-7 shows the
position of the status bits as they appear in the appropriate data RAM location after execution of the
SST instruction.
15
OV
14
13
OVM INTM
12
11
1
10
9
8
7
6
5
4
3
ARP
o
2
///
DP
/ / / = don't care
FIGURE 2-7 - STATUS WORD AS STORED BY SST INSTRUCTION
The LST instruction may be executed to load the status register. LST does not assume status bits
are on page one, so the DP must be set to one for the LST instruction to access status bits stored
on page one. The interrupt mask bit cannot be changed by the LST instruction. However, all other
status bits can be changed by this instruction.
2.8
2.8.1
INPUT/OUTPUT FUNCTIONS
I N and OUT
Input and output of data to and from a peripheral is accomplished by the IN and OUT instructions.
Data is transferred over the 16-bit data bus ~and from the data memory by two independent
strobes: data enable (DEN) and write enable (WE).
The bidirectional external data bus is always in a high-impedance mode, except when WE goes low.
WE will go low during the first cycle of the OUT instruction and the second cycle of the TBLW
instruction.
As shown in Figure 2-8, 128 1/0 bits are available for interfacing to peripheral devices: eight 16-bit
multiplexed input ports and eight 16-bit multiplexed output ports.
2-15
I
DATA BUS (16)
TMS32010
A2-AO /
PA2-PAO
I
PORT
ADDRESS
t------........ I DECODER
174LS138)
---t.IIIIIIIIII" III"
DEN
1 _U
0
T_2
WE
16110 BITS PER PORT
FIGURE 2-8 - EXTERNAL DEVICE INTERFACE
Execution of an IN instruction generates the DEN strobe for transferring data from a peripheral
device to the data RAM (see Figure 2-9A). The IN instruction is the only instruction for which
DEN will become active. Execution of an OUT instruction generates the WE strobe for transferring
data from the data RAM to a peripheral device (see Figure 2-9B). WE becomes active only during
the OUT instruction and the table write (TBLW) instruction. See Appendix A, the TMS3201 0 Data
Sheet, for further timing information.
DATA IN
IN INSTRUCTION
•
PREFETCH
•
.
NEXT INSTRUCTION
VALID
...--~.,.
PREFETCH
.,
DEN
FIGURE 2-9A - INPUT INSTRUCTION TIMING
2-16
.
OUT INSTRUCTION
MEN
PREFETCH
..
DATA OUT
VALID
NEXT INSTRUCTION
PREFETCH
1.._____-'
WE
FIGURE 2-9B - OUTPUT INSTRUCTION TIMING
FIGURE 2-9 - INPUT/OUTPUT INSTRUCTION TIMING
The three multiplexed LSBs of the address bus, PA2 through PAO, are used as a port address by the
IN and OUT instructions. The remaining higher order bits of the address bus, A 11 through A3, are
held at logic zero during execution of these instructions.
2.8.2
Table Read (TBlR) and Table Write (TBlW)
The TB lR and the TB lW instructions allow words to be transferred between program and data
spaces. TBlR is used to read words from on-chip program ROM or off-chip program ROM/RAM
into the data RAM. TBlW is used to write words from on-chip data RAM to off-chip program
RAM.
Execution of the TBlR instruction generates MEN strobes to read the word from program memory
(see Figure 2-1 OA). Execution of a TBlW instruction generates a WE strobe (see Figure 2-10B).
Note that the WE strobe will be generated and the appropriate data transferred even if the
TMS320M10 is in the microcomputer mode and a TBlW is performed to a program location less
than 1535.
The dummy prefetch is a prefetch of the instruction following the TBlR or TBlW instructions and
is discarded. The instruction following TBlR or TBlW is prefetched again at the end of the
execution of the TB lR or TB lW instructions.
DATA TRANSFERRED
NEXT
INSTRUCTION
DUMMY
FROM PROGRAM
INSTRUCTION
PREFETCH
PREFETCH
MEMORY
TBLR
•
PREFETCH
MEN~~________~
FIGURE 2-10A - TABLE READ INSTRUCTION TIMING
TBLW
INSTRUCTION
DUMMY
PREFETCH
PREFETCH
•
DATA
NEXT
TRANSFERRED TO
INSTRUCTION
PROGRAM MEMORY
••
PREFETCH
MENI~_________
FIGURE 2-10B - TABLE WRITE INSTRUCTION TIMING
FIGURE 2-10 - TABLE READ AND TABLE WRITE INSTRUCTION TIMING
2-17
I
2.8.3 Address Bus Decoding
Since all three interface strobes, MEN, WE, and DEN, are mutually exclusive, there are some very
important considerations for those designs that utilize external program memory. Since the OUT and
TBLW instructions use only the WE signal to indicate valid data, these instructions cannot be
distinguished from one another on the basis of the interface strobes. Unless the address bus is decoded,
execution of TBLW instructions will write data to peripherals and execution of OUT instructions will
overwrite program memory locations 0 through 7. See Section 5-4 for an example of this decoding logic.
No matter what decoding logic is used, it will not be possible to use TBLW to uniquely write to program
memory locations 0 through 7. This is because the address bus will be identical for OUT and TBLW,
and there will be no way to distinguish between the two instructions .
•
2.9
BIO PIN
The BIO pin is an external pin which supports bit test and jump operations. When a low is
present on this pin, execution of the BIOZ instruction will cause a branch to occur. This pin is sampled
every clock cycle and is not latched.
The BIO pin is useful for monitoring peripheral device status. It is especially useful as an
alternative to using an interrupt when it is necessary not to disturb time-critical loops. See Section 2.14
for BIO system design recommendations.
2.10
INTERRUPTS
The TMS3201 O's interrupt is generated either by applying a negative-going edge to the interrupt (lNT)
pin or by holding the INT pin low. A diagrammatic explanation of the TMS3201 O's internal interrupt
circuitry is presented in Figure 2-11.
RS
INTERRUPT
ACKNOWLEDGE
EINT
TMS32010
CLR
CLOCK
CLR
5V
D
Q
INTERRUPT
FLAG
Q
INTERRUPT
MODE
REGISTERt
Q
D
INT
D
a indicates
interrupts enabled.
= 1 indicates interrupts disabled.
* (j> = phase of internal clock.
=
FIGURE 2-11 - SIMPLIFIED INTERRUPT LOGIC DIAGRAM
2-18
INTERRUPT
PROCESSOR
Q
SYNC
FF
to
a
INTERNAL
---_........
INTERRUPT
ACTIVE
The Sync FF is a synchronizing flip-flop used to synchronize the external interrupt signal to the
TMS32010's internal interrupt circuitry. When interrupts are enabled, an interrupt becomes active
either due to a low voltage input on the INT pin or when a negative-edge has been latched into the
interrupt flag.
If the interrupt mode register (lNTM) is set, then an interrupt active signal to the internal interrupt
processor (liP) becomes valid. The liP begins interrupt servicing by causing a branch to location 2 in
program memory. It will delay interrupt servicing in each of the following cases:
1) Until the end of all cycles of a multicycle instruction,
2) Until the instruction following the MPY or MPYK has completed execution,
3) Until the instruction following EINT has been executed (when interrupts have been pre-I
viously disabled). This allows the RET instruction to be executed after interrupts become
enabled at the end of an interrupt routine.
When the interrupt service routine begins, the liP sends out an internal interrupt acknowledge
signal. This presets the INTM register (disabling interrupts) and clears the interrupt flag.
Figure 2-11 also shows that DINT or a hardware reset will set the INTM register, disabling
interrupts, while EINT will clear the INTM register. Interrupts will continue to be latched while they
are disabled. Note that DINT or EINT do not affect the interrupt flag.
Figure 2-12 shows the instruction sequence that occurs once an interrupt becomes active. The
dummy fetch is an instruction that is fetched but not executed. This instruction will be fetched and
executed after the interrupt routine is completed.
CLKOUT
INT
I'--__~
\,
'1 CLOCK CYCLE MIN
FETCH
INSTRUCTION N
/
FETCH
INSTRUCTION N + 1
EXECUTE N
DUMMY FETCH
INSTRUCTION N + 2
EXECUTE N+ 1
FETCH
INSTRUCTION
002
DUMMY CYCLE
EXECUTE 002
FIGURE 2-12 - INTERRUPT TIMING
See Section 2.14 for interrupt system design recommendations.
2.11
RESET
The reset function is enabled when an active low is placed on the RS pin for a minimum of five clock
cycles (see Figure 2-13). The control lines for DEN, WE, and MEN are then forced high, and the
data bus (015 through DO) is tristated. The PC and the address bus (A 11 throug!!.. AO) a~then
synchronously cleared after the next complete clock cycle from the falling edge of RS. The RS pin
also disables the interrupt, clears the interrupt flag register, and leaves the overflow mode register
unchanged. The TMS32010 can be held in the reset state indefinitely.
2-19
~.1---5
CLOCK CYCLES MIN ~
Rsl_____----'I
FIGURE 2-13 - RESET TIMING
2.12
CLOCK/OSCILLATOR
The TMS32010 can use either its internal oscillator or an external frequency source for a clock.
Use of the internal oscillator is achieved by connecting a crystal across X1 and X2/ClKIN. The
frequency of CLKOUT and the cycle time of the TMS3201 0 is one-fourth of the crystal fundamental
frequency (see Figure 2-14).
I
X1
X2/CLKIN
----lOt---...
CRYSTAL
FIGURE 2-14 - INTERNAL CLOCK
An external frequency source can be used by injecting the frequency directly into X2/ClKIN with
X1 left unconnected. If an external frequency source is used, a pull-up resistor may be necessary
(see Figure 2-15). This is because the high-level voltage of the ClKIN input must be a minimum of
2.8 V while a standard TTL gate, for example, can have a high-level output voltage as low as 2.4 v.
The size of the pull-up resistor will depend on such things as the frequency source's high-level
output voltage and current and the number of other devices the frequency source will be driving.
The resistor should be made as large as possible while still having the ClKIN input specification
met.
X2/CLKIN
+VCC
SIGNAL
GENERATOR
FIGURE 2-15 - EXTERNAL FREQUENCY SOURCE
The delay time between ClKIN and ClKOUT is not specified. This delay time can vary by as much a
one CLKOUT cycle and is very temperature dependent. Hardware designs which depend upon this
delay time should not be used.
2-20
2.13
PIN DESCRIPTIONS
Definitions of the TMS32010 pin assignments and descriptions of the function of each pin are
presented in Table 2-4. Figure 2-16 illustrates the TMS3201 0 pin assignments.
TABLE 2-4 - TMS32010 PIN DESCRIPTIONS
SIGNAL
PIN
DESCRIPTION
I/O
POWER SUPPLIES
30
Supply voltage ( + 5 V NOM)
10
Ground reference
CLOCKS
X2/CLKIN
8
IN
Crystal input pin for internal oscillator (X2). Also input pin for external oscillator (ClKIN).
X1
7
OUT
Crystal input pin for internal oscillator
CLKOUT
6
OUT
Clock output signal. The frequency of ClKOUT is one-fourth of the
oscillator input (external oscillator) or crystal frequency (internal
oscillator). Duty cycle is 50 percent.
CONTROL
WE
31
OUT
Write Enable. When active (low), WE indicates that valid output
data from the TMS3201 0 is available on the data bus. WE is only
active during the first cycle of the OUT instruction and the second
cycle of the TBlW instruction (see Section 3.4.3), MEN and DEN
will always be inactive (high) when WE is active.
32
OUT
Data Enable. When active (low), DEN indicates that the
TMS32010 is accepting data from the data bus. DEN is only active during the first cycle of the IN instruction (see Section 3.4.3).
MEN and WE will always be inactive (high) when DEN is active.
33
OUT
Memory Enable. MEN will be active low on every machine cycle
except when WE and DEN are active. MEN is a control signal
generated by the TMS3201 0 to enable instruction fetches from
program memory. MEN will be active on instructions fetched from
both'internal and external memory.
2-21
TABLE 2-4 -
SIGNAL
PIN
TMS32010 PIN DESCRIPTIONS (CONTINUED)
DESCRIPTION
I/O
INTERRUPTS
RS
-
INT
-
BIO
4
IN
Reset. When an active low is placed on the RS pin for a minimum
of five clock cycles, DEN, WE, and MEN are forced high, and the
data bus (D15 through DO) is tristated. The program counter (PC)
and the address bus (A 11 through AO) are then synchronously
cleared after the next complete clock cycle from the falling edge of
RS. RS also disables the interrupt, clears the interrupt flag register,
and leaves the overflow mode register unchanged. The TMS3201 0
can be held in the reset state indefinitely.
5
IN
Interrupt. The interrupt signal is generated by applying a negativegoing edge to the INT pin. The edge is used to latch the interrupt
flag register (lNTF) until an interrupt is granted by the device. An
active low level will also be sensed. (See Section 2.10.)
9
IN
I/O Branch Control. If BIO is active (low) upon execution of the
BIOZ instruction, the device will branch to the address specified by
the instruction (see Section 2.9).
PROGRAM MEMORY MODES
-
MC/MP
3
IN
Microcomputer/Microprocessor Mode. A high on the MC/MP pin
enables the microcomputer mode. In this mode, the user has
available 1524 words of on-chip program memory. (Program
memory locations 1 524 through 1535 are reserved.) The
microcomputer mode also allows an additional 2560 words of
program memory to reside off-chip. A Iowan the MC/MP pin
enables the microprocessor mode. In this mode, the entire
memory space is external, i.e., addresses 0 through 4095. (See
Section 2.3.1 .)
BIDIRECTIONAL DATA BUS
015
014
013
012
D11
010
09
08
07
06
05
D4
03
02
D1
00
2-22
18
17
16
15
14
13
12
11
19
20
21
22
23
24
25
26
I/O
liD
liD
liD
liD
liD
liD
liD
liD
liD
liD
liD
liD
liD
liD
liD
015 (MSB) through DO (LSB). The data bus is always in the highimpedance state except when WE is active (low).
TABLE 2-4 - TMS32010 PIN DESCRIPTIONS (CONCLUDED)
SIGNAL
PIN
DESCRIPTION
I/O
PROGRAM MEMORY ADDRESS BUS AND
PORT ADDRESS BUS
All
A10
A9
A8
A7
A6
A5
A4
A3
A2/PA2
Al/PAl
AD/PAD
27
28
29
34
35
36
37
38
39
40
1
2
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Program memory A 11 (MSB) through AD (LSB) and port
addresses PA2 (MSB) through PAD (LSB). Addresses A 11
through AD are always active and never go to high impedance. During execution of the IN and OUT instructions,
pins A2 through AD carry the port addresses PA2 through
PAD.
A1/PA 1
AO/PAQ
A2/PA2
A3
MC/MP
A4
A5
RS
INT
CLKOUT
X1
X2/CLKIN
910
Vss
OS
09
010
I
A6
A7
AS
MEN
O~N
WE
vCC
A9
A10
011
012
A11
013
01
014
02
015
07
03
04
06
05
DO
FIGURE 2-16 - TMS32010 PIN ASSIGNMENTS
2-23
2.14
INTERRUPT AND 810 SYSTEM DESIGN
For systems using asynchronous inputs to the INT and BIO pins on the TMS32010, the external
hardware shown in Figure 2-17 is recommended to ensure proper execution of interrupts and the
BIOZ instruction. This hardware synchronizes the INT and BIO input signals with the rising edge
of CLKOUT on the TMS32010. The pulse width required for these input signals is tc(C), which is
one TMS32010 clock cycle, plus sufficient setup time for the flip-flop (dependent upon the flip-flop
used).
I
p
I
Q
0
1NT
SN74ALS74
r-- ~
C
TMS32010
I
+5V
CLKOUT
1
P
0
Q
810
SN74ALS74
r--
>
TMS32010
C
1
+5 V
FIGURE 2-17 -
2-24
CLKOUT
INTERRUPT AND
mo HARDWARE DESIGN
I
INSTRUCTIONS
I
3.
INSTRUCTIONS
The TMS3201 O's comprehensive instruction set supports both numeric- intensive operations, such
as signal processing, and general-purpose operations, such as high-speed control. The instruction
set, shown in Table 3-2, consists primarily of single-cycle single-word instructions, permitting execution rates of up to five million instructions per second. Only infrequently used branch and I/O
instructions are multicycle.
The TMS32010 also contains a number of instructions that shift data as part of an arithmetic operation. These all execute in a single cycle and are very useful for scaling data in parallel with other
operations.
3.1
INTRODUCTION
The instruction set contains a full set of branch instructions. Combined with the Boolean operations and shifters, these instructions permit the bit manipulation and bit test capability needed for
high-speed control operations. Double-precision operations are also supported by the instruction
set. Some examples are ADDH (add to high-order accumulator) and ADDS (add to accumulator
with sign extension suppressed), which allow easy manipulation of 32-bit numbers.
The TMS32010's hardware multiplier allows the MPY instruction to be executed in a single cycle.
The SUBC (conditional subtract for divide) instruction performs the shifting and conditional
branching necessary to implement a divide efficiently and quickly.
Two special instructions, TBLR (table read) and TBLW (table write), allow crossover between data
memory and program memory. The TB LR instruction transfers words stored in program memory to
the data RAM. This eliminates the need for a coefficient ROM separate from the program ROM,
thus permitting the user to make efficient trade-offs as to the amount of ROM dedicated to program or coefficient store. The accompanying instruction, TBLW, transfers words in internal data
RAM to an external RAM. In conjunction with TBLR, this instruction allows the use of external
RAM to expand the amount of data storage.
When a very large amount of external data must be addressed (i.e., > 4K words), TBLR and TBLW
can no longer serve as a means of expanding the data RAM. Then it becomes necessary to address
external data RAM as a peripheral by using the IN and OUT instructions; these instructions permit a
data word to be read into the on-chip RAM in only two cycles. This procedure requires a minimal
amount of external logic and permits the accessing of almost unlimited amounts of data RAM. This
is very useful for pattern recognition applications, such as speech recognition or image processing.
3.2
ADDRESSING MODES
Three main addressing modes are available with the TMS3201 0 instruction set direct, indirect, and
immediate addressing.
3.2.1
Direct Addressing Mode
In direct addressing, seven bits of the instruction word concatenated with the data page pointer
form the data memory address. This implements a paging scheme in which the first page contains
128 words and the second page contains 16 words. In a typical application, infrequently accessed
variables, such as those used when performing an interrupt service routine, are stored on the second page.
3.2.2
Indirect Addressing Mode
Indirect addressing forms the data memory address from the least significant eight bits of one of
two auxiliary registers, ARO and AR1 . The auxiliary register pointer (ARP) selects the current auxiliary register. The auxiliary registers can be automatically incremented or decremented in parallel
with the execution of any indirect instruction to permit single-cycle manipulation of data tables.
3-1
I
3.2.3.
Immediate Addressing Mode
The TMS3201 0 instruction set contains special lIimmediate" instructions. These instructions derive
data from part of the instruction word rather than from the data RAM. The constant in all immediate
instructions may refer to values supplied by an external reference symbol. Some very useful immediate instructions are multiply immediate (MPYK), load accumulator immediate (LACK), and
load auxiliary register immediate (LARK).
3.3
INSTRUCTION ADDRESSING FORMAT
The following sections describe the opcode format for the various addressing modes of the
TMS32010.
3.3.1
Direct Addressing Format
15
14
13
I
12
11
10
9
8
7
6
5
4
3
2
1
0
dma
OPCODE
Bit 7 = 0 defines direct addressing mode. The opcode is contained in bits 15 through 8. Bits 6
through 0 contain data memory address.
The 7 bits of the data memory address (dma) field can directly address up to 128 words (1 page) of
data memory. Use of the data memory page pointer is required to address the full 144 words of data
memory.
Direct addressing can be used with all instructions requiring data operands except for the immediate
operand instructions.
3.3.2.
Indirect Addressing Format
15
14
13
12
11
10
OPCODE
9
8
7
6
5
4
3
2
1
0
0 IINCIDECIARPI 0 I 0 I ARP I
Bit 7 =
defines indirect addressing mode. The opcode is contained in bits 15 through 8. Bits 6
through 0 contain indirect addressing control bits.
Bit 3 and bit 0 control the Auxiliary Register Pointer (ARP)' If bit 3 = 0, then the contents of bit 0
are loaded into the ARP after execution of the current instruction. If bit 3
1, then the contents of
the ARP remain unchanged. ARP = 0 defines the contents of ARO as a memory address. ARP =
1 defines the contents of AR1 as a memory address.
=
Bit 5 and bit 4 control the auxiliary registers. If bit 5 = 1, then ARP defines which auxiliary register is
to be incremented by 1 after execution. If bit 4 = 1, then the ARP defines which auxiliary register is
to be decremented by 1 after execution. If bit 5 and bit 4 are zero, then neither auxiliary register is inc'remented or decremented. Bits 6,2, and 1 are reserved and should always be programmed to zero.
Indirect addressing can be used with all instructions requiring data operands, except for the immediate operand instructions.
3.3.3
I mmediate Addressing Format
Included in the TMS32010's instruction set are five immediate operand instructions (LDPK, LARK,
MPYK, LACK, and LARP). In these instructions, the operand is contained within the instruction
word.
3-2
3.3.4
Examples of Opcode Format
1)
Add to accumulator the contents of memory
location 9 left-shifted 5 bits.
ADD 9,5
15
14
13
\ 0
0
0
12
11
10
0 \ 0
9
8
7
6
5
4
01\01 0 0
0
3
2
1
o
0
0
Note: Opcode of the ADD instruction is 0000 and appears in bits 15 through 12. Shift code of 5 appears in bits 11 through 8. Data memory address 9 appears in bits 6 through
o.
2)
ADD *+,8
15
14
Add to accumulator the contents of data memory address defined by
contents of current auxiliary register. This data is left-shifted 8 bits
before being added. The current auxiliary register is auto-incremented
by 1.
13
12
000
0
11
10
9
8
7
6
5
4
3
2
1
0
o
1
000
Other variations of indirect addressing are as follows:
3.4
3)
ADD *, 8
As in example 2, but with no auto-increment; opcode would be
>0888
4)
ADD * -, 8
As in example 2, except that current auxiliary register is decremented
by 1; opcode would be > 0898
5)
ADD *
+ , 8, 1
As in example 2, except that the auxiliary register pointer is loaded
with the value 1 after execution; opcode would be> 08A 1
6)
ADD *
+
As in example 2, except that the auxiliary register pointer is loaded
with the value 0 after execution; opcode would be> 08AO
,8,0
INSTRUCTION SET
The following sections include the symbols and abbreviations that are used in the instruction set
summary and in the instruction descriptions, the complete instruction set summary, and a description of each instruction.
All numbers are assumed to be decimal unless otherwise indicated. Hexidecimal numbers are
specified by the symbol II>" before the nu mber.
3.4.1.
Symbols and Abbreviations
DATn and PRGn are assumed to have the symbolic value of n. They are used to represent any symbol with the value n.
3-3
TABLE 3-1 - INSTRUCTION SYMBOLS
SYMBOL
ACC
AR
ARP
D
DATn
dma
DP
I
INTM
K
>nn
OVM
P
PA
I
PC
pma
PRGn
R
5
T
T05
X
-
II
< >
[ ]
( )
{}
<>
3-4
MEANING
Accumulator
Auxiliary register (ARO and AR 1 are predefined assembler symbols equal to 0 and 1,
respectively. )
Auxiliary register pointer
Data memory address field
Label assigned to data memory location n
Data memory address
Data page pointer
Addressing mode bit
Interrupt mode flag bit
. Immediate operand field
Indicates nn is a hexadecimal number. All others are assumed to be decimal values.
Overflow (saturation) mode flag bit
Product (P) register
Port address (PAO through PA7 are predefined assembler symbols equal to 0 through
7, respectively)
Program counter
Program memory address
Label assigned to program memory location n
1-bit operand field specifying auxiliary register
4-bit left-shift code
T register
Top of stack
3-bit accumulator left-shift field
Is assigned to
Indicates an absolute value
Items within angle brackets are defined by user.
Items within brackets are optional.
Indicates contents of"
Items within braces are alternative items; one of them must be entered.
Angle brackets back-to-back indicate "not equal".
Blanks or spaces are significant.
II
3.4.2
Instruction Set Summary
The instruction set summary in the following table consists primarily of single-cycle single-word instructions. Only infrequently used branch and 1/0 instructions are multicycle.
TABLE 3-2 -
INSTRUCTION SET SUMMARY
ACCUMULATOR INSTRUCTIONS
MNEMO!,)!IC
DESCRIPTION
OPCODE
INSTRUCTION REGISTER
NO.
NO.
CYCLES WORDS
15 14 13 12 11 10
ABS
ADD
ADDH
ADDS
AND
LAC
LACK
OR
SACH
SACL
SUB
SUBC
SUBH
SUBS
XOR
ZAC
ZALH
ZALS
Absolute value of
accumulator
Add to accumulator
with shift
Add to high-order
accumulator bits
Add to accumulator
with no sign extension
AND with accumulator
Load accumulator
with shift
Load accumulator
immediate
OR with accumulator
Store high-order
accumulator bits with
shift
Store low-order
accumulator bits
Subtract from
accumulator with
shift
Conditional subtract
(for divide)
Subtract from highorder accumulator bits
Subtract from accumulator with no sign
extension
Exclusive 0 R with
accumulator
Zero accumulator
Zero accumulator and
load high-order bits
Zero accumulator and
load low-order bits
with no sign extension
9
8
7
6
5
4
3
2
1
0
1
1
1
a
0
0
1
a
0
0
I
<
D
:>
1
1
a
1
1
1
1
1
1
a
0
0
0
~S--7
1
1
a
1
1
0
0
0
0
a
I
<
D
:>
1
1
0
1
1
0
0
0
0
1
I
<
D
:>
1
1
1
1
a
1
0
1
1
1
0
1
~
0 0 1
S -----7
I
I
<
<
D
D
:;:.
0
1
1
a
1
1
1
1
1
K
:>
1
1
1
1
0
a
1
1
1
0
1
1
1
1
1
1
0
1
0
1
0
0
1
1
a
0
0
1
1
a
1
1
1
a
1
1
1
1
:>
1
a <
0
1
0
~
X~
I
I
<
(
D
D
:>
:;:.
0
0
I
<
D
:>
1
~S~
I
<
D
:;:.
1
0
a
1
0
a
I
<
D
:>
1
1
0
0
0
1
0
I
<
D
:>
a
1
1
0
0
0
1
1
I
<
D
:>
1
0
1
1
1
1
0
0
a
I
<
D
:>
1
1
1
1
a
a
1
1
1
1
a
1
1
1
1
0
1
1
1
I
0
0
<
D
:;:.
1
1
a
1
1
0
0
1
1
a
I
<
D
:>
1
0
0
1
I
a
0
1
3-5
TABLE 3-2 - INSTRUCTION SET SUMMARY (CONTINUED)
AUXILIARY REGISTER AND DATA PAGE POINTER INSTRUCTIONS
MNEMONIC
DESCRIPTION
NO.
NO.
CYCLES WORDS
OPCODE
INSTRUCTION REGISTER
15 14 13 12 11 10
LAR
LARK
LARP
LOP
LDPK
I
MAR
SAR
Load auxiliary
register
Load auxiliary
register immediate
Load auxiliary
register pointer
immediate
Load data memory
page pointer
Load data memory
page pointer
immediate
Modify auxiliary
register and pointer
Store auxiliary
register
9
8
7
6
oE
5
4
3
2
1
0
1
1
0
0
1
1
1
0
0
R
I
1
1
0
1
1
1
0
0
0
R
oE
1
1
0
1
1
0
1
0
0
0
1
0
1
1
0
1
1
0
1
1
1
1
I
oE
1
1
0
1
1
0
1
1
1
0
0
0
1
1
0
1
1
0
1
0
0
0
I
oE
0
>
1
1
0
0
1
1
0
0
0
R
I
oE
0
>
0
0
0
~
K
~
0
0
0
:>
0
0
0
0
K
0
0
K
BRANCH INSTRUCTIONS
MNEMONIC
DESCRIPTION
NO.
NO.
CYCLES WORDS
OPCODE
INSTRUCTION REGISTER
15 14 13 12 11 10
B
BANZ
BGEZ
Branch unconditionally
2
Branch on auxiliary
register not zero
2
Branch if accumulator
2
2
2
2
~O
BGZ
BIOZ
BLEZ
Branch if accumulator
>0
Branch on BIO
=0
Branch if accumulator
2
2
2
2
2
2
~O
BLZ
BNZ
BV
BZ
CALA
CALL
RET
3-6
Branch if accumulator
<0
2
Branch if accumulator
10
2
Branch on overflow
2
2
2
2
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
0
1
0
1
0
1
0
1
1
0
<
1
0
1
0
1
0
1
0
<
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
1
1
0
0
<
1
1
0
9
8
3
2
1
0
1 0 0 0 0 0
BRANCH ADDRESS
0
0
0 0 0 0 0 0
BRANCH ADDRESS
0
1 0 0 0 0 0
BRANCH ADDRESS
0
<
1
0
oE
1
0
1
1
1
0
0
1
<
1
<
0
0
1
1
<
1
1
<
1
<
0
Branch if accumulator
=0
2
Call subroutine from
accumulator
Call subroutine
immediately
2
1
0
1
1
1
1
1
1
2
2
1
0
1
1
0
1
0
1
0
0
0
<
Return from subroutine
2
0
1
1
1
1
2
1
1
1
1
1
7
6
5
4
0 0 0 0 0 0
BRANCH ADDRESS
0 0 0 0 0 0
BRANCH ADDRESS
1 0 0 0 0 0
BRANCH ADDRESS
0
0
0
0
0
0
1 0 0 0 0 0
BRANCH ADDRESS
0
0
0
0
0
0
0
0
1
0
0
~
0 0 0 0 0 0
BRANCH ADDRESS
0
0
:>
0
0
0
:>
1
0
0
:>
1
1
0
--~
0
1
0
:>
1 0 0 0 0 0
BRANCH ADDRESS
0
0
--~
0
0
0
:>
0 0 0 0 0 0
BRANCH ADDRESS
0
0
>
0
1
0
>
0 0 0 0 0 0
BRANCH ADDRESS
1
0
0
0
:>
1
0
1
TABLE 3-2 - INSTRUCTION SET SUMMARY (CONCLUDED)
T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS
MNEMONIC
DESCRIPTION
OPCODE
INSTRUCTION REGISTER
NO.
NO.
CYCLES WORDS
15 14 13 12 11 10
APAC
LT
LTA
LTD
MPY
MPYK
PAC
SPAC
Add P register to
accumulator
Load T register
LTA combines L T and
APAC into one instruction
LTD combines LT,
APAC, and DMOV into
one instruction
Multiply with T
register; store product
in P register
Multiply T register
with immediate operand; store product in
P register
Load accumulator from
P register
Subtract P register
from accumulator
9
8
7
6
5
4
3
2
1
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
1
1
0
0
0
I
I
tE
D
D
:?>
<
1
1
0
1
1
0
1
0
1
1
I
tE
D
')
1
1
0
1
1
0
1
1
0
1
I
<
D
:>
1
1
1
0
0
<
1
1
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
3
2
1
0
0
0
0
1
1
0
0
1
0
0
0
1
:>
I
:>
K
CONTROL INSTRUCTIONS
MNEMONIC
DINT
EINT
LST
NOP
POP
PUSH
ROVM
SOVM
SST
DESCRIPTION
Disable interrupt
Enable interrupt
Load status register
No operation
Pop stack to
accumulator
Push stack from
accumulator
Reset overflow mode
Set overflow mode
Store status register
NO.
NO.
CYCLES WORDS
OPCODE
INSTRUCTION REGISTER
15 14 13 12 11 10
9
8
7
6
5
4
0
0
0
0
0
0
D
0
1
1
1
1
1
2
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
1
1
0
0
0
0
0
0
0
1
2
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
I
0
0
0
0
0
0
1
1
0
0
1
1
0
1
1
1
0
<
<
:>
:>
D
I/O AND DATA MEMORY OPERATIONS
MNEMONIC
DESCRIPTION
NO.
NO.
CYCLES WORDS
OPCODE
INSTRUCTION REGISTER
15 14 13 12 11 10
DMOV
IN
OUT
TBLR
TBLW
Copy contents of data
memory location into
next location
I nput data from port
Output data to port
Table read from
program memory to
data RAM
Table write from
data RAM to program
memory
4
9
8
7
6
0
1
I
<
D
:>
<
<
D
tE
D
D
:>
:>
:>
<:
D
')
1
1
0
1
1
0
1
0
2
2
3
1
1
1
0
0
0
1
1
1
0
0
1
0
0
0
0
1
~PA~
~PA~
0
1
1
1
I
I
I
3
I
0
1
1
1
1
1
0
1
I
5
3
2
1
0
3-7
3.4.3
I nstruction Descriptions
Each instruction in the instruction set summary is described in the following pages. The instructions
are listed in alphabetical order. An example is provided with each instruction.
Each instruction begins with an assembler syntax expression. Since the comment field which concludes the syntax is optional, it is not included in the syntax expression. A syntax example is given
below that shows the spaces that are included and required in the syntax expression, and the optional comment field along with its preceding spaces that has been omitted.
[< label>]
I
3-8
LACK
f
~spaces
[ ]
Spaces and comment
field not included
in the syntax expressions
for this section.
ABS
ABS
Absolute Value of Accumulator
Assembler Syntax:
[< label>]
Operands:
None
Operation:
If (ACC) < 0
Then - (ACC)
Encoding:
15
I
14
13
-+
ACC
12
11
0
ABS
10
9
8
7
6
5
4
1
1
1
0
0
0
3
2
1
0
0
0
0
Description: If accumulator is greater than zero, then the accumulator is unchanged by the execution of
this instruction. If the accumulator is less than zero, then the accumulator will be replaced
by its two's complement value. Note that the hexadecimal number> 80000000 is a special
case. When the overflow mode is not set, the ABS of> 80000000 is > 80000000. When in
the overflow mode, the ABS of> 80000000 is> 7FFFFFFF.
Words: 1
Cycles: 1
Example: ABS
31
BEFORE INSTRUCTION
0
ACC I> 0
0 0
0
1 2
AFTER INSTRUCTION
31
0
3 4
ACC I> 0
0
0
0
1 2 3
ACC I> F F F F F F F F
ACC I> 0
0
0
0 0 0
4
and
0
1
3-9
I
ADD
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
Operands:
ADD
Add to Accumulator with Shift
ADD
ADD
[ ]
[ ]
[, ]
{* 1* + 1* -}[, [, ]]
0 ~ shift ~ 15
127
ARP
0 or 1
O~ dma~
=
I
+
(dma) X 2 shift
Operation:
(ACC)
Encoding:
15
14
13
12
Direct:
o
o
o
o
SHIFT
DATA MEMORY
ADDRESS
Indirect:
o
000
SHIFT
SEE SECTION 3.3
11
--+
ACC
10
9
8
7
6
5
4
3
2
o
Description: Contents of data memory address are left-shifted and added to accumulator. During
shifting, low-order bits are zero-filled, and high-order bits are sign-extended. The result is
stored in the accumulator.
Words: 1
Cycles: 1
Example:
ADD DAT1,3
or
If current auxiliary register contains the value 1 .
ADD *,3
BEFORE INSTRUCTION
AFTER INSTRUCTION
DATA
MEMORY
1
21
DATA
MEMORY
1
ACC
71
ACC
21
23
1
Note: If the contents of data memory address DAT2 is > 8BDE, then the following instruction sequence
will leave accumulator with the value> FFF8BOEO.
ZAC
ADD
3-10
DAT2,4
Zero accumulator
ACe = > FFF8BOEO
ADDH
ADDH
Add to High-Order Accumulator
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
ADDH
ADDH
[< label>]
[ ]
Operands:
O~dma~
Operation:
(ACC)
{ * I * + I * - } [, < ARP > ]
127
ARP = 0 or 1
Encoding:
15
Direct:
0
Indirect:
0
+
14
1
(dma) x 2 16 -+ ACC
13
12
11
10
9
8
7
1
0
0
0
0
01
0
1
0
0
0
0
01
5
6
4
3
2
0
DATA MEMORY
ADDRESS
1
I
SEE SECTION 3.3
Description: Add contents of data memory address to upper half of the accumulator (bits 31 through 16).
Words:
Cycles:
1
1
Example: ADDH DAT5
or
If current auxiliary register contains the value 5.
ADDH *
BEFORE INSTRUCTION
DATA
MEMORY
5
ACC
>41
>0 0 0 0 0 0 1
31
AFTER INSTRUCTION
DATA
MEMORY
5
ACC
>41
>0 0 0 4 0 0 1
31
Note: This instruction can be used in performing 32-bit arithmetic.
3-11
Add to Low Accumulator
with Sign-Extension Suppressed
ADDS
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
Operands:
{ * I * + I * - } [, <"ARP > ]
O~dma~127
ARP
I
ADDS
ADDS
[< label>]
[ ]
ADDS
=
Operation:
(ACC)
Encoding:
15
Direct:
0
Indirect:
0
0 or 1
+
14
(dma) - ACC
13
1
12
11
10
9
0
0
0
0
0
0
0
0
8
7
1
I0 I
1
I
5
6
4
3
2
0
DATA MEMORY
ADDRESS
SEE SECTION 3.3
Description: Add contents of specified data memory location with sign-extension suppressed. The data is
treated as a 16-bit positive integer rather than a two's complement integer. Therefore, there
is no sign-extension as there is with the ADD instruction.
Words:
Cycles:
Example:
1
1
ADDS DA T11
or
ADDS *
If current auxiliary register contains the value 11 .
BEFORE INSTRUCTION
DATA
MEMORY
11
ACC
>F
0
0
AFTER INSTRUCTION
DATA
MEMORY
11
6
>0 0 0 0 0 0 0 3
ACC
>F
0 0 6
>0 0 0 0 F 0 0
91
Notes: The following routines illustrate the difference between the ADD and ADDS instructions. Data
memory location DATl contains> E007.
ZAC
ADDS
DAT1
ZeroACC
ACC = > OOOOE007
ZAC
ADD
ZeroACC
DAT1,0 ACC = > FFFFE007
The ADDS instruction can be used in implementing 32-bit arithmetic.
3-12
AND
AND
AND with Low-Order Bits of Accumulator
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
AND
AND
[ ]
[ ]
{* I* + 1* -
}[,]
0 ~ dma ~ 127
ARP = 0 or 1
Operands:
Operation:
Zero. AND. high-order ACC bits: (dma). AND. low-order ACC bits -+ ACC
Encoding:
15
14
Direct:
0
1
Indirect:
0
1
Description:
13
10
9
8
7
1
0
0
1
II
1
0
0
1
I
12
11
6
0
5
4
3
2
0
DATA MEMORY
ADDRESS
SEE SECTION 3.3
The low-order bits of the accumulator are ANDed with the contents of the specified data
memory address and concatenated with all zeroes AN Oed with the high-order bits of the
accumulator. The AND operation follows the truth table below.
DATA MEMORY BIT
ACC BIT (BEFORE)
ACC BIT (AFTER)
0
0
0
1
1
0
0
0
0
1
1
1
Words: 1
Cycles: 1
Example: AND DAT16
or
AND *
If current auxiliary register contains the value 16.
AFTER INSTRUCTION
BEFORE INSTRUCTION
DATA
MEMORY
16
ACC
>0 0 F F
DATA
MEMORY
16
>0 0 F F
>1 2 3 4 5 6 7 8
ACC
>0 0 0 0 0 0 7 8
Note: This instruction is useful for examining bits of a word for high-speed control applications.
3-13
APAC
[ < label>]
Assembler Syntax:
Operands:
None
Operation:
(ACC)
Encoding:
15
+
14
APAC
(P)-+ ACC
13
12
11
10
1
1
o
I
APAC
Add P Register to Accumulator
9
8
7 6
5 4
3
2
o
000
Description: The contents of the P register, the result of a multiply, are added to the contents of the
accumulator and the result is stored in the accumulator.
Words: 1
Cycles: 1
Example:
APAC
BEFORE INSTRUCTION
P
Ace
64
3_2----J
L - I_ _ _ _ _ _
AFTER INSTRUCTION
P
AcelL--_________9_6----J
Note: This instruction is a subset of the LT A and LTO instructions.
3-14
64
B
B
Branch Unconditionally
Assembler Syntax:
[]
Operands:
o ~ pma<
Operation:
pma-+ PC
Encoding:
15
14
1
1
0
0
13
0
B
212
12
11
10
9
1
1
0
0
01
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
PROGRAM MEMORY ADDRESS
Description: Branch to location in program is specified by the program memory address (pma). Pma can
be either a symbolic or a numeric address.
Words: 2
Cycles: 2
Example:
B PRG191 191 is loaded into the program counter and program continues running from
that location.
3-15
I
BANZ
BANZ
[ ]
Assembler Syntax:
Operands:
o ~ pma<
Operation:
If (AR bits 8 through 0) < > 0
Then (AR) - 1 - AR and pma - PC
Else (PC) + 2 - PC
(AR) - 1 - AR
Encoding:
15
I
BANZ
Branch on Auxiliary Register Not Zero
14
212
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0\
0
0
0
0
PROGRAM MEMORY ADDRESS
Description: If the lower nine bits of the current auxiliary register are not equal to zero, then the auxiliary
register is decremented, and the address contained in the following word is loaded into the
program counter. If these bits equal zero, the current program counter is incremented and
AR also is decremented. Branch to location in program is specified by the program memory
address (pma). Pma can be either a symbolic or numeric address.
Words: 2
Cycles: 2
Example: BANZ PRG35
BEFORE INSTRUCTION
AFTER INSTRUCTION
AR
PC
ARL...-1 _ _ _ _----'0I
46
1
PC
I
35
1
or
AR
PC
01
46
ARI
PC
1
>1
F FJ
48
1
Note: This instruction can be used for loop control with the auxiliary register as loop counter. The auxiliary
register is decremented after testing for zero. The auxiliary registers also behave as modulo 512
counters.
3-16
Branch if Accumulator Greater Than
or Equal to Zero
BGEZ
Assembler Syntax:
Operands:
o ~ pma < 212
Operation:
If (ACC) ~ 0
Then pma -. PC
Else (PC) + 2 -. PC
Encoding:
15
0
BGEZ
[ ]
14
0
13
0
12
01
11
10
9
1
1
0
BGEZ
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
I
PROGRAM MEMORY ADDRESS
Description: If the contents of the accumulator are greater than or equal to zero, branch to the specified
program memory location. Branch to location in program is specified by the program
memory address (pma). Pma can be either a symbolic or a numeric address.
Words: 2
Cycles: 2
Example:
BGEZ PRG217 217 is loaded into the program counter if the accumulator is greater than
or equal to zero.
3-17
BGZ
[]
Assembler Syntax:
BGZ
Operands:
O~ pma< 212
Operation:
If (ACe) > 0
Then pma -+ PC
Else (PC) + 2 -+ PC
Encoding:
15
14
13
12
11
1
1
1
1
1
0
0
0
01
I
BGZ
Branch if Accumulator Greater Than Zero
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
PROGRAM MEMORY ADDRESS
Description: If the contents of the accumulator are greater than zero, branch to the specified program
memory location. Branch to location in program specified by the program memory address
(pma). Pma can be either a symbolic or a numeric address.
Words: 2
Cycles: 2
Example: BGZ PRG342 342 is loaded into the program counter if the accumulator is greater than zero.
3-18
BIOZ
Assembler Syntax:
[ < label> ]
Operands:
o ~ pma< 212
Operation:
If BIO
0
Then pma~ PC
Else (PC) + 2 ~ PC
Encoding:
15
14
13
1
1
1
0
0
0
Description:
BIOZ
Branch on I/O Status Equal to Zero
. BIOZ
=
12
11
0
oI
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
I
PROGRAM MEMORY ADDRESS
If the BIO pin is active low, then branch to specified memory location. Otherwise, the
program counter is incremented to the next instruction. Branch to location in program is
specified by the program memory address (pma). Pma can be either a symbolic or a numeric
address.
Words: 2
Cycles: 2
Example: BIOZ PRG64 If the BIO pin is active low, then a branch to location 64 occurs. Otherwise, the
program counter is incremented.
Note: This instruction can be used in conjunction with the BIO pin to test if peripheral is ready to deliver an
input. This type of interrupt is preferable when performing time-critical loops.
3-19
Assembler Syntax:
[ ]
BLEZ
Operands:
O~ pma< 212
Operation:
If (ACC) ~ 0
Then pma -+ PC
Else (PC) + 2 -+ PC
Encoding:
15
14
13
12
11
10
1
1
1
1
1
0
0
0
0
0/
I
Description:
BLEZ
Branch if Accumulator Less Than
or Equal to Zero
BLEZ
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
PROGRAM MEMORY ADDRESS
If the contents of the accumulator are less than or equal to zero, branch to the specified
program memory location. Branch to location in program is specified by the program
memory address (pma). Pma can be either a symbolic or a numeric address.
Words: 2
Cycles: 2
Example:
3-20
BLEZ PRG63 63 is loaded into the program counter if the accumulator is less than or
equal to zero.
BlZ
BlZ
Branch if Accumulator Less Than Zero
Assembler Syntax:
[]
Operands:
o ~ pma< 212
Operation:
If (ACC) < 0
Then pma'" PC
Else (PC) + 2 ... PC
Encoding:
15
14
13
12
1
0
0
0
01
11
BLZ
10
9
8
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
0
0
0
PROGRAM MEMORY ADDRESS
Description: If the contents of the accumulator are less than zero, branch to the specified program
memory location. Branch to location in program is specified by the program memory
address (pma). Pma can be either a symbolic or numeric address.
Words: 2
Cycles: 2
Example: BLl PRG481 481 is loaded into the program counter if the accumulator is less than zero.
3-21
•
BNZ
[]
Assembler Syntax:
Operands:
O~ pma< 212
Operation:
If (ACC) < > 0
Then pma -. PC
Else (PC) + 2 -. PC
Encoding:
15
•
BNZ
Branch if Accumulator Not Equal to Zero
14
12
1
1
a
13
0
0
01
11
BNZ
10
9
8
7
6
5
4
3
2
1
1
0
0
0
0
0
0
0
0
a
0
PROGRAM MEMORY ADDRESS
Description: If the contents of the accumulator are not equal to zero, branch to the specified
program memory location. Branch to location in program is specified by the program
memory address (pma). Pma can be either a symbolic or numeric address.
Words: 2
Cycles: 2
Example: BNZ PRG320 320 is loaded into the program counter if the accumulator does not equal zero.
3-22
BV
BV
[ ]
Assembler Syntax:
Operands:
o ~ pma <
Operation:
If overflow flag = 1
Then pma-PC and O-overflow flag
Else (PC) + 2 -+ PC
Encoding:
BV
Branch on Overflow
15
14
1
0
0
212
13
12
11
1
1
0
0
01
10
9
0
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
I
PROGRAM MEMORY ADDRESS
Description: If the overflow flag has been set, then a branch to the program address occurs and the
overflow flag is cleared. Otherwise, the program counter is incremented to the next instruction. Branch to location in program is specified by the program memory address (pma).
Pma can be either a symbolic or a numeric address.
Words: 2
Cycles: 2
Example: BV PRG610 If an overflow has occurred since the overflow flag was last cleared, then 610 is
loaded into the program counter. Otherwise, the program counter is
incremented.
3-23
BZ
Assembler Syntax:
[ ]
Operands:
o ~ pma<
Operation:
If (ACC) = 0
Then pma -. PC
Else (PC) + 2 -. PC
Encoding:
15
I
BZ
Branch if Accumulator Equals Zero
0
BZ
212
14
13
12
1
1
1
0
0
01
11
10
9
1
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
PROGRAM MEMORY ADDRESS
Description: If the contents of the accumulator are equal to zero, branch to the specified program
memory location. Branch to location in program is specified by the program memory
address (pma). Pma can be either a symbolic or numeric address.
Words: 2
Cycles: 2
Example: BZ PRG102 102 is loaded into the program counter if accumulator is equal to zero.
3-24
CALA
CALA
Call Subroutine Indirect
Assembler Syntax:
[<,label> ]
CALA
Operands:
None
Operation:
(PC) + 1 -+ TOS
(ACC bits 11 through 0)
-+
15
10
Encoding:
I0
14
13
12
11
1
PC
9
8
7
1
6
5
4
000
3
2
1
0
o
0
Description: The current program counter is incremented and pushed onto the top of the stack. Then,
the contents of the 12 least significant bits of the accumulator are loaded into the PC.
Words: 1
Cycles: 2
Example: CALA
AFTER INSTRUCTION
BEFORE INSTRUCTION
PC
25
PC
83
ACC
83
ACC
83
STACK
32
75
84
49
ST ACK
IL---______!I-----'
Note: This instruction is used to perform computed subroutine calls.
3-25
I
CALL
CALL
Call Subroutine Direct
Assembler Syntax:
Operands:
o ::5
pma < 21 2
Operation:
(PC)
pma
+2
--+
15
14
Encoding:
-+
•
TOS
PC
13
12
1
0
CALL
[ ]
0
0
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
oJ
0
0
0
PROGRAM MEMORY ADDRESS
Description: The current program counter is incremented and pushed onto the top of the stack. Then,
the program memory address is loaded into the PC.
Words: 2
Cycles: 2
Example: CALL PRG109
AFTER INSTRUCTION
BEFORE INSTRUCTION
PC
STACK
33
109
71
48
16
80
3-26
PC
STACK
L . - 1_
_
_
_
_
_
4_~i_ _ l
DINT
DINT
Disable Interrupt
Assembler Syntax:
Operands:
None
Operation:
1-INTM
Encoding:
15
I0
14
[]
DINT
13
10
12
1
11
1
9
8
7
6
5
4
1
1
000
3
2
1
0
000
1
Description: The interrupt-mode flag (lNTM) bit is set to logic 1. When this flag is set, any further
maskable interrupts are disabled.
Words: 1
Cycles: 1
Example: DINT
3-27
I
DMOV
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
Operands:
DMOV
Data Move in Memory
[ ]
[ ]
DMOV
DMOV
{* 1* + 1* - }[, ]
o~ dma~ 127
ARP=Q or 1
I
~
dma
+
Operation:
(dma)
1
Encoding:
15
14
13
12
11
10
9
a
7
Direct:
0
1
1
0
1
0
0
1
I0 I
Indirect:
0
1
0
1
0
0
1
I
5
6
4
3
2
0
DATA MEMORY
ADDRESS
SEE SECTION 3.3
Description: The contents of the specified data memory address are copied into the contents of the next
higher address.
Words: 1
Cycles: 1
Example: DMOV DATa
or
DMOV *
If current auxiliary register contains the value 8.
BEFORE INSTRUCTION
DATA
~----------------~
431
1L.-.-_ _ _ _ _---'21
ME~O RY
ME~ORYI
DATA
MEMgORY
AFTER INSTRUCTION
DATA
MEMORY
a
I
43 1
DATA
1'"--_ _ _ _ _ _
43---1,
Note: DMOV is an instruction that can be associated with Z-l in signal flow graphs. It is a subset of the LTD
instruction. See LTD for more information.
3-28
EINT
EINT
Enable Interrupt
Assembler Syntax:
[ ]
Operands:
None
Operation:
O-INTM
Encoding:
15
14
I0
1
13
12
1
EINT
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
0
0
0
0
0
1
01
Description: The interrupt-mode flag (lNTM) in the status register is cleared to logic O. When this flag is
not set, maskable interrupts are enabled.
Words: 1
Cycles: 1
Example: EINT
3-29
I
IN
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
I
IN
Input Data from Port
IN
IN
[]
[]
Operands:
O::;;dma::;;127
O::;;PA::;;7
ARP=O or 1
Operation:
PA-address lines PA2-PAO
Data bus D15-DO-dma
Encoding:
15
Direct:
Indirect:
Description:
,
{* I * + I * - }, < PA > [, < ARP >]
7
13
12
11
0
0
0
0
0
0
0
oIAbg=~ssll I
14
10
9
8
PORT
ADDRESS
6
5
4
3
2
1
0
DATA MEMORY
ADDRESS
SEE SECTION 3.3
The IN instruction reads data from a peripheral and places it in data memory. It is
a two-cycle instruction. During the first cycle, the port address is sent to address
lines A2/PA2-AO/PAO. DEN goes low during the same cycle, strobing in the data
which the addressed peripheral places on the data bus, D 15-DO.
Words: 1
Cycles: 2
Example:
IN
STAT,PA5 Read in word from peripheral on port address 5.
Store in data memory location STAT.
LARK
LARP
IN
1,20
1
*-,PA 1,0
Load AR 1 with decimal 20 .
Load ARP with 1.
Read in word from peripheral on port address 1 .
Store in data memory location 20. Decrement
AR1 to 19. Load the ARP with O.
Notes: When the TMS32010 outputs address onto the three LSBs of address lines, the nine MSBs are
zeroed.
Instruction causes the DEN line to ~w during the first clock cycle of this instruction's execution. MEN remains high when DEN is active.
3-30
LAC
LAC
Load Accumulator with Shift
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
Operands:
[< label>]
[ ]
LAC
LAC
< dma > [, < shift> ]
{* 1* + 1* - }[, [, ]]
0 ~ shift ~ 15
O~dma~
127
ARP=Q or 1
Operation:
(dma) X 2shift -+ACC
Encoding:
15
14
o
o
o
SHIFT
DATA MEMORY
ADDRESS
001
0
SHIFT
SEE SECTION 3.3
Direct:
Indirect:
13
12
11
10
9
8
7
6
5
4
3
2
o
I
Description: Contents of data memory address are left-shifted and loaded into the accumulator. During
shifting, low-order bits are zero-filled and high-order bits are sign-extended.
Words: 1
Cycles: 1
Example:
LAC DAT6,4
or
LAC *,4
If current auxiliary register contains the value 6.
BEFORE INSTRUCTION
DATA
MEMORY
6
ACC
1
AFTER INSTRUCTION
1
~----------------~.
01
DATA
MEMORY
6
1
I
ACC
3-31
LACK
Assembler Syntax:
o:::;;constant:::;; 255
Operation:
constant-ACC
15
14
o
I
13
1
12
11
LACK
[]
Operands:
Encoding:
LACK
Load Accumulator with Eight-Bit Constant
10
9
8
o
1
7
6
5
4
3
2
o
8-BIT CONSTANT
Description: The eight-bit constant is loaded into the accumulator right-justified. The upper 24 bits of the
accumulator are zeros (i.e., sign extension is suppressed).
Words: 1
Cycles: 1
Example: LACK 15
BEFORE INSTRUCTION
ACC
31
AFTER INSTRUCTION
ACC
15
I
Note: If a constant longer than eight bits is used, the XDS/320 assembler will truncate it to eight bits. No
error message will be given.
3-32
LAR
LAR
Load Auxiliary Register
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
[ ]
[ ]
Operands:
0 ~ dma ~ 127
AR = 0 or 1
ARP = 0 or 1
Operation:
(dma) - AR
LAR
LAR
,
,{*I * + 1* - }L]
Encoding:
15
14
13
12
Direct:
0
0
1
1
AUXILIARY
1 REGISTER
0
0
1
1
1
Indirect:
11
10
9
8
7
6
5
4
3
o
2
0
DATA MEMORY
ADDRESS
AUXILIARY 1
REGISTER
SEE SECTION 3.3
I
Description: The contents of the specified data memory address are loaded into the designated auxiliary
register.
Words: 1
Cycles: 1
Example:
LAR
ARO,DAT19
BEFORE INSTRUCTION
DATA
ME~~RY
lsi
I
61
ARO
also,
DATA
lsi
M~~~RYI
ARO
LARP 0
LAR ARO,*-
ME~ORY 1~
ARO
AFTER INSTRUCTION
DATA
______32---J1
71
DATA
MEM 0RY
7
ARO
L . . . - 1_
_
_
_
_
32~1
_
321
Notes: ARO is not decremented after the LAR instruction. Generally as in the above case, if indirect
addressing with autodecrement is used with LAR to load the current auxiliary register, the new
value of the auxiliary register is not decremented as a result of instruction execution. The analagous
case is true with autoincrement.
LAR and its companion instruction SAR (store auxiliary registers) should be used to store and load
the auxiliary during subroutine calls and interrupts.
If an auxiliary register is not being used for indirect addressing, LAR and SAR enable it to be used
as an additional storage register, especially for swapping values between data memory locations.
3-33
LARK
Assembler Syntax:
I
LARK
Load Auxiliary Register with Eight-Bit Constant
[ ]
Operands:
o ~ constant ~ 255
AR = 0 or 1
Operation:
constant-AR
Encoding:
15
14
13
12
Direct:
0
1
1
1
11
LARK
9
10
8
AUXILIARY
0 REGISTER
,
7 6
5
4
3
2
o
8-BIT CONSTANT
Description: The eight-bit positive constant is loaded into the designated auxiliary register right-justified
and zero-filled (i.e., sign-extension suppressed).
Words: 1
Cycles: 1
Example: LARK ARO,21
BEFORE INSTRUCTION
ARO
01
AFTER INSTRUCTION
ARO
21
I
Notes: This instruction is useful for loading an initial loop counter value into an auxiliary register for use
with the BANZ instruction.
If a constant longer than eight bits is used, the XDS/320 assembler will truncate it to eight bits. No
error message will be given.
3-34
LARP
LARP
Load Auxiliary Register Pointer Immediate
Operands:
o ~ constant ~ 1
Operation:
constant -+ ARP
Encoding:
15
14
0
1
13
< constant>
LARP
[ ]
Assembler Syntax:
12
11
10
9
8
0
1
0
0
0
7
6
5
4
3
2
0
0
0
0
0
0
0
I. CONSTANT.
l-BIT
I
Description: Load a one-bit constant identifying the desired auxiliary register into the auxiliary register
pointer.
Words: 1
Cycles: 1
Example: LARP 1 Any succeeding instructions will use auxiliary register 1 for indirect addressing.
Note: This instruction is a subset of MAR.
3-35
LOP
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
I
LOP
Load Data Memory Page Pointer
LDP
LDP
[]
[ ]
Operands:
O~dma~ 127
ARP=O or 1
Operation:
LSB of (dma) --. DP (DP
Encoding:
15
14
Direct:
0
1
Indirect:
0
13
12
11
=0
10
9
{*I * + 1* -
}L]
or 1)
8
7
0
1
1
I0 I
0
1
1
I
6
5
4
3
2
0
DATA MEMORY
ADDRESS
SEE SECTION 3.3
Description: The least significant bit of the contents of the specified data memory address is loaded into
the data memory page pointer register (DP). All higher-order bits are ignored in the data
word. DP = 0 defines page 0 which contains words 0-127. DP = 1 defines page 1 which
contains words 128-143.
Words: 1
Cycles: 1
Example:
3-36
LOP
or
LOP
DAT1
LSB of location DAT1 is loaded into data page pointer.
*,1
LSB of location currently addressed by auxiliary register is loaded into
data page pointer. AR P is set to one.
LDPK
Assembler Syntax:
[]
Operands:
o~ constant ~ 1
Operation:
constant- DP
Encoding:
LDPK
Load Data Page Pointer Immediate
15
14 13 12 11
o
1
1
0
1
LDPK
10
9
8
7
6
5
4
3
2
1
o
1
1
0
0
0
0
0
0
0
0
ICO~:~:NTI
I
Description: The one-bit constant is loaded into the data memory page pointer register (DP). DP = 0
defines page 0 which contains words 0-127. DP = 1 defines page 1 which contains words
128-143.
Words: 1
Cycles: 1
Example:
LDPK
0
Data page pointer is set to zero.
3-37
LST
LST
Load Status from Data Memory
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
LST
LST
[]
[ ]
{* 1* + 1* - }[, ]
Q~dma~127
Operands:
ARP=Q or 1
(dma) -status bits
Operation:
I
Encoding:
15
14
Direct:
0
1
Indirect:
0
1
13
12
11
8
7
0
1
I0 I
0
1
I
10
9
6
5
4
3
2
0
DATA MEMORY
ADDRESS
SEE SECTION 3.3
Description: Restores the contents of the status register as saved by the store status (SST) instruction
from a data memory word.
Words: 1
Cycles: 1
Example:
The data memory word addressed by the contents of auxiliary
register 0 replaces the status bits. The auxiliary register pointer
becomes 1.
LARP 0
LST *,1
Note: This instruction is used to load the TMS32010's status bits after interrupts and subroutine calls.
These status bits include the Overflow Flag (OV) bit, Overflow Mode (OVM) bit, Auxiliary Register
Pointer (ARP) bit, and the Data Memory Page Pointer (DP) bit. The Interrupt Mask bit cannot be
changed by the LST instruction. These bits were stored (by the SST instruction) in the data memory
word as follows:
15
See SST.
3-38
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LT
LT
Load T Register
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
[ ]
[ ]
Operands:
O::;dma::;127
ARP=O or 1
Operation:
(dma)- T
Encoding:
15
Direct:
0
14
13
12
0
11
LT
LT
10
0
{* I * + I * - }L < ARP > ]
9
8
7
6
0
1
0
0
3
2
1
01 0
DATA MEMORY
ADDRESS
o 11
SEE SECTION 3.3
1
Indirect:
4
5
1
0
I
Description: LT loads the T register with the contents of the specified data memory location.
Words: 1
Cycles: 1
Example: LT
or
LT
DAT24
*
If current auxiliary register contains the value 24.
BEFORE INSTRUCTION
DATA
MEMORY
24
T
621
AFTER INSTRUCTION
DATA
MEMORY
24
T
I
62
~.----------------~
62
Note: LT is used to load the T register in preparation for a multiplication. See MPY, LTA, and LTD.
3-39
LTA
LTA
Load T Register and Accumulate Previous Product
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
LTA
LTA
[ ]
[ ]
{*I * + 1* -
}[,]
O~dma~127
Operands:
ARP=O or 1
Operation:
I
(dma)- T
(ACC) + (P) - ACC
12
11
10
9
8
1
0
1
1
0
o 101
1
0
1
0
o 11
15
14
Direct:
0
Indirect:
0
Encoding:
13
5
6
7
4
3
2
0
DATA MEMORY
ADDRESS
I
SEE SECTION 3.3
Description: The contents of the specified data memory address are loaded into the T register. Then, the
P register, containing the previous product of the multiply operation, is added to the accumulator, and the result is stored in the accumulator.
Words: 1
Cycles: 1
Example: LTA DAT24
or
LTA *
If current auxiliary register contains the value 24.
BEFORE INSTRUCTION
AFTER INSTRUCTION
DATA.
MEMORY
24
621
DATA
MEMORY
24
T
31
T
62 1
p
15
I
ACe
20
I
p
15
1
ACC
51
Note: This instruction is a subset of the LTD instruction.
3-40
1
62
1
~.----------------~.
Load T Register, Accumulater Previous
Product, and Move Data Memory
LTD
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
Operands:
Osdmas127
ARP=O or 1
Operation:
(dma)-T
(ACC) + (P)-ACC
(dma) -dma + 1
Encoding:
15
Direct:
0
14
LTD
LTD
[ ]
[]
{ * I * + I* -
13
12
11
10
9
8
7
1
0
1
0
1
1
0
1
Indirect:
0
1
0
1
0
H, < ARP > ]
4
3
2
1
I
0
DATA MEMORY
ADDRESS
1
1 11 1
1
5
6
LTD
SEE SECTION 3.3
Description: The T register is loaded with the contents of the specified data memory address. Then, the
contents of the P register are added to the accumulator. Next, the contents of the specified
data memory address are transferred to the next higher data memory address.
Words: 1
Cycles: 1
Example: LTD DAT24
or
LTD *
IF current auxiliary register contains the value 24.
BEFORE INSTRUCTION
DATA
MEMORY
24
AFTER INSTRUCTION
621
DATA
MEMORY
24
DATA
MEMORY
25
01
DATA
MEMORY
25
62
T
31
T
62
p
15
p
ACe
15
1
51
ACC
621
~--------------~
1
1
I
20 1
3-41
MAR
Assembler Syntax:
{* 1* + 1* - }[, ]
MAR
[]
Operands:
ARP=Q or 1
Operation:
Current auxiliary register is incremented, decremented, or remains the same. Auxiliary register pointer is loaded with the next ARP.
Encoding:
15
Direct:
0
14
13
12
11
10
9
8
7
1
0
1
0
0
0
0
1
I
MAR
Modify Auxiliary Register
Indirect:
0
1
0
1
0
0
6
1
0 11 1
5
4
3
2
0
DATA MEMORY
ADDRESS
SEE SECTION 3.3
Description: This instruction utilizes the indirect addressing mode to increment/decrement the auxiliary
registers and to change the auxiliary register pointer. It has no other effect.
Words: 1
Cycles: 1
Example:
MAR *, 1
MAR *MAR *+,0
Load ARP with 1.
Decrement current auxiliary register (in this case, AR 1 )
Increment current auxiliary register (AR1), load ARP with O.
Note: In the direct addressing mode, MAR is a NOP. Also,the instruction LAR'P is a subset of MAR (i.e.,
MAR *,0 performs the same function as LARP 0).
3-42
MPY
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
O:::;;dma::5127
ARP=O or 1
Operation:
(T) x (dma)-P
Encoding:
15
Direct:
0
Description:
0
14
MPY
MPY
[< label>]
[ ]
Operands:
Indirect:
MPY
Multiply
13
12
11
10
9
1
0
1
1
0
{*I * + 1* -
8
1
0
1
0
6
7
0
4
5
}L]
3
2
0
I
DATA MEMORY
ADDRESS
1
11 1
SEE SECTION 3.3
The contents of the T register are multiplied by the contents of the specified data memory
address, and the result is stored in the P register.
Words: 1
Cycles: 1
Example: MPY DAT13
or
If current auxiliary register contains the value 13.
MPY *
AFTER INSTRUCTION
BEFORE INSTRUCTION
DATA
MEMORY
13
I
71
DATA
MEMORY
13
T
T
p
p
I
71
Note: During an interrupt, all registers except the P register can be saved. However, the TMS32010 has
hardware protection against servicing an interrupt between an MPY or MPYK instruction and the
following instruction. For this reason, it is advisable to follow MPY and MPYK with LTA, LTD, PAC,
APAC, or SPAC.
No provisions are made for the condition of
will be > COOOOOOO.
>8000 X >8000. If this condition arises, the product
3-43
MPYK
Operands:
(-212 ) ~ constant < 212
Operation:
(T) x constant- P
Encoding:
15
I
MPYK
[ ]
Assembler Syntax:
I
MPYK
Multiply Immediate
14
13
o
0
1
12
11
10
9
8
7
6
5
4
3
2
o
13-BIT CONSTANT
Description: The contents of the T register are multiplied by the signed 13-bit constant and the result
loaded into the P register.
Words: 1
Cycles: 1
Example: MPYK - 9
AFTER INSTRUCTION
BEFORE INSTRUCTION
T
71
T
p
4~
p
71
Note: No provision is made to save the contents of the P register during an interrupt. Therefore, this
instruction should be followed by one of the following instructions: PAC, APAC, SPAC, l TA, or
l TO. Provision is made in hardware to inhibit interrupt during MPYK until the next instruction is
executed.
3-44
NOP
Operands:
None
Operation:
None
Encoding:
15
I
NOP
[ ]
Assembler Syntax:
Description:
NOP
No Operation
0
14
13
12
11
1
1
1
10
9
8
7
6
5
4
3
2
o
000
0
o
0
0
No operation is performed.
I
Words: 1
Cycles: 1
Example: NOP
Note: NOP is useful as a IIpad" or temporary instruction during program development.
3-45
OR
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
I
OR
OR with Low-Order Bits of Accumulator
[]
[]
OR
OR
{* 1* + 1* - }[, ]
Operands:
O:5dma :5127
ARP=O or 1
Operation:
Zero. OR. high-order ACC bits: (dma). OR. low-order ACC bits-ACC
Encoding:
15
Direct:
o
Indirect:
o
Description
14
10
11
12
13
9
8
7
6
5
3
2
o
1
DATA MEMORY
ADDRESS
o
1
4
o 11
o
I
SEE SECTION 3.3
The low-order bits of the accumulator are ORed with the contents of the specified data
memory address concatenated with all zeroes ORed with the high-order bits of the accumulator. The result is stored in the accumulator. The OR operation follows the truth
table below.
DATA MEMORY BIT
ACC BIT (BEFORE)
ACC BIT (AFTER)
0
0
1
0
1
1
1
1
0
0
1
1
Words: 1
Cycles: 1
Example: OR DAT88
or
OR *
Where current auxiliary register contains the value 88.
AFTER INSTRUCTION
BEFORE INSTRUCTION
DATA
MEMORY
>F
0
0
DATA
MEMORY
0
88
88
ACC
>0 0 1 000 0
21
ACC
I
>F
0
0
>0 0 1 OF0021
Note: This instruction is useful for comparing selected bits of a data word.
3-46
0
OUT
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
Operands:
OUT
Output Data to Port
[< label>]
[< label>]
OUT
OUT
,
{* I * + I * - }, < PA > [, < ARP > ]
0~dma:5127
0~PA~7
ARP=O or 1
Operation:
PA- address lines PA2-PAO
(dma)-data bus 015-00
Encoding:
15
Direct:
Indirect:
14
0
0
1
13
12
11
0
0
1
0
0
10
9
8
7
6
PORT
ADDRESS
IA6g~~ssI1 I
5
4
3
2
0
I
DATA MEMORY
ADDRESS
SEE SECTION 3.3
Description: The OUT instruction transfers data from data memory to an external peripheral. The
first cycle of this instruction places the port address onto address lines A2/PA2-AO/PAO.
During the same cycle, WE goes low and the data word is placed on the data bus D15-DO.
Words: 1
Cycles: 2
Example:
OUT 120,7
OUT *,5
Output data word stored in memory location 1 20 to
peripheral on port address 7.
Output data word referenced by current auxiliary
register to peripheral on port address 5.
Notes: When the TMS32010 sends the port address onto the three LSBs of the address lines, the nine
MSBs are set to zero.
The OUT instruction causes the WE line to go low during the first clock cycle of this instruction's execution. MEN remains high during the first cycle.
3-47
PAC
PAC
Load Accumulator with P Register
Assembler Syntax:
Operands:
None
Operation:
(P) -ACe
Encoding:
15
I0
PAC
[ ]
14
13
12
11
1
1
1
10
9
1
8
7
6
5
4
1 000
3
2
o
o
Description: The contents of the P register resulting from a multiply are loaded into the accumulator.
I
Words: 1
Cycles: 1
Example: PAC
AFTER INSTRUCTION
BEFORE INSTRUCTION
3-48
p
144
p
ACC
23
ACC
1441
POP
POP
Pop Top of Stack to Accumulator
Assembler Syntax:
[]
Operands:
None
Operation:
(TOS)'" ACC
Encoding:
15
o
14
13
12
1
1
11
POP
10
9
8
7
6
5
1
1
100
4
3
2
1
a
1
a
1
Description: The contents of the top of stack are loaded into the accumulator. The next element on the
stack becomes the top of the stack.
Words: 1
Cycles: 2
Example: POP
BEFORE INSTRUCTION
ACC
STACK
82
AFTER INSTRUCTION
1
!! I
ACC
451
STACK
Note: The 12 bits of the stack are put into the accumulator in bits 11 through 0, and bits 31 through 12 are
zeroed. There is no provision to check stack underflow.
3-49
I
PUSH
Assembler Syntax:
None
Operation:
(ACC) -+TOS
Encoding:
15
I
I
[< label>]
Operands:
Description:
Words:
Cycles:
PUSH
Push Accumulator onto Stack
14
13
12
PUSH
11
10 9 8
7 6
111
o
0
5 4 3
0
1
o
2
o
0
I
The contents of the lower 12 bits (11-0) of the accumulator are pushed onto the top of the
hardware stack.
1
2
Example: PUSH
AFTER INSTRUCTION
BEFORE INSTRUCTION
ACC
STACK
71
ACC
II
STACK
II
Note: There is no provision for detecting a stack overflow. Therefore, if the stack is already full, the
contents of the bottom stack element will be lost upon execution of PUSH.
3-50
RET
RET
Return from Subroutine
Assembler Syntax:
Operands:
None
Operation:
(TOS)
Encoding:
15
I0
RET
[]
-+
14
PC
13
12
11
10
9
8
7
1
6
5
4
3
000
1
o
2
o
1
I
Description: The top element is popped off of the stack and loaded into the program counter.
I
Words: 1
Cycles: 2
Example: RET
BEFORE INSTRUCTION
PC
STACK
961
AFTER INSTRUCTION
PC
371
STACK
Note: This instruction is used in conjunction with CALL and CALA for subroutines.
3-51
ROVM
[]
Assembler Syntax:
Operand:
None
Operation:
O-OVM
Encoding:
15
Ia
I
ROVM
Reset (Clear) Overflow Mode Register
14
13
12
11
ROVM
10 9 8 7 6
5 4 3 2
a a a
o
1 a
a
Description: This instruction will reset the TMS32010 from the overflow mode it was placed in by the
SOVM instruction. The overflow mode will set the accumulator and the ALU to their highest
positive/negative value when an overflow occurs.
Words: 1
Cycles: 1
Example: ROVM
Note: See SOVM.
3-52
SACH
SACH
Store Accumulator High with Shift
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
[ ]
[ ]
SACH
SACH
[, ]
{* 1* + 1* - H, [, ]]
Osdmas127
shift = 0, 1, or 4
ARP=O or 1
Operands:
Operation:
(ACC) x 2 - (16-shift)
Encoding:
15
Direct:
o
o
SHIFT
Indirect:
o
o
SH 1FT 11
14
13
12
11
-+
dma
10
9
8
7
6
101
I
5
4
3
o
2
I
DATA MEMORY
ADDRESS
SEE SECTION 3.3
Description: Store the upper half of the accumulator in data memory with shift. The shift can only be 0,
1,or4.
Words: 1
Cycles: 1
Example: SACH
or
SACH
DAT70,1
*,1
If current auxiliary register contains the value 70.
BEFORE INSTRUCTION
ACC
>0 4 2 0 8 0 0 1
AFTER INSTRUCTION
ACC
1
DATA
MEMORY
DATA
MEMORY
70
70
>0 4 2 0 8 0 0
>0
8
4
Notes: The SACH instruction copies the entire accumulator into a shifter. It then shifts this entire 32-bit
number 0, 1, or 4 bits and copies the upper 16 bits of the shifted product into data memory. The
accumulator itself remains unaffected.
For example, the following instruction sequence will store> 8 F35 in data memory location DAT1 .
Location DAT2 contains the number> A8F3. DAT3 contains> 5000.
ZALH
DAT2
ADDS
DAT3
SACH
DAT1,4
= > A8F30000
ACC = > A8F35000
DAT1 = >8F35
ACC
ACC
=
> A8F35000
3-53
SACL
Assembler Syntax:
Direct Address-ing:
Indirect Addressing:
Operands:
SACL
SACL
[< label>]
[< label>]
[, ]
{* 1* + 1* - }[, [, ]]
0::5dma::5127
ARP=O or 1
Shift = 0
Operation:
(ACC bits 15 through 0)
Encoding:
15
I
SACL
Store Accumulator Low
14
13
12
11
-+
dma
10
9
8
7
6
Direct:
010
o
0 0 01 01
Indirect:
010
o
0
0
0
I
5
4
3
2
1
0
DATA MEMORY
ADDRESS
SEE SECTION 3.3
Description: Store the low-order bits of the accumulator in data memory.
Words: 1
Cycles: 1
Example: SACL
or
SACL
DAT7l
*
If current auxiliary register contains the value 71.
AFTER INSTRUCTION
BEFORE INSTRUCTION
ACC
DATA
MEMORY
71
>0 4 2 0 8 0 0 1
I
>0 4 2 0 8 0 0 1
ACC
DATA
MEMORY
71
I
>8
0
0
1
Note: There is no shift associated with this instruction, although a shift code of zero MUST be specified
if the ARP is to be changed.
3-54
SAR
SAR
Store Auxiliary Register
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
[ ]
[]
Operands:
O~dma~ 127
AR=O or 1
ARP=O or 1
Operation:
(AR)
Encoding:
SAR
SAR
,
,{* 1* + I * - }L]
-+
dma
15
14
13
12
Direct:
0
0
1
1
AUXILIARY
0 REGISTER 0
DATA MEMORY
ADDRESS
Indirect:
0
0
1
1
0 AUXILIARY 1
SEE SECTION 3.3
11
10
9
8
7 6
REGISTER
5
4 3
2
o
I
Description: The contents of the designated auxiliary register are stored in the specified data memory
location.
Words: 1
Cycles: 1
Example: SAR
ARO,DAT101
AFTER INSTRUCTION
BEFORE INSTRUCTION
371
ARO
101
LARP
SAR
371
DATA
MEMORY
101
DATA
MEMORY
also,
ARO
ARO
ARO,*+
ARO
51
ARO
61
DATA
MEMORY
01
DATA
MEMORY
61
5
5
WARNING
Special problems arise when SAR is used to store the current auxiliary register with indirect addressing if autoincrement/decrement is used.
(continued)
3-55
SAR
SAR
LARP
LARK
SAR
ARO
ARO,10
ARO, * +
or
SAR ARO, *-
In this case, SAR ARO, * + will cause the value 11 to be stored in location 10. SAR
ARO, * - will cause the value 9 to be stored in location 1O.
Note: For more information, see LAR.
I
3-56
SOVM
SOVM
Set Overflow Mode Register
Assembler Syntax:
[ ]
Operands:
None
Operation:
1-0VM
Encoding:
15
I0
14
SOVM
13
12
11
10
1
1
1
1
9
8
7
6
5
4
3
2
1
0
1
1
0
0
0
1
0
1
1
I
Description: When placed in the overflow mode, the TMS3201 0 will set the accumulator and ALU
to their highest positive/negative value if an overflow/underflow occurs. The highest
positive value is > 7FFFFFFF, and the lowest negative value is > 80000000.
Words: 1
Cycles: 1
Example: SOVM
3-57
I
SPAC
Assembler Syntax:
[ ]
Operands:
None
Operation:
(ACC) - (P) -+ ACe
Encoding:
15
I
I
SPAC
Subtract P Register from Accumulator
14
13
SPAC
12
11
10
9
8
7
6
5
4
3
2
1
0
111100100001
0
Description: The contents of the P register are subtracted from the contents of the accumulator, and the
result is stored in the accumulator.
Words: 1
Cycles: 1
Example:
SPAC
AFTER INSTRUCTION
BEFORE INSTRUCTION
p
ACC
3-58
36\
1L....--_ _ _ _ _6---J01
p
ACC
36\
24
---J
L - - I_ _ _ _ _
1
SST
SST
Store Status
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
Operands:
[]
[]
SST
SST
{* 1* + I * - }[, ]
O:5dma:515
ARP=O or 1
Operation:
status bits -. specified data memory word on page 1
Encoding:
15
14
Direct:
0
1
Indirect:
0
12
13
11
10
1
1
1
1
9
8
0
0101
DATA MEMORY
ADDRESS
0
01
SEE SECTION 3.3
7
5
6
4
3
2
0
I
Description: The status bits are saved into the specified data memory address on page 1 .
Words: 1
Cycles: 1
Example: SST
or
SST
DAT1
IF current auxiliary register contains the value 1.
*,1
Note: This instruction is used to load the TMS32010's status bits after interrupts and subroutine calls.
These status bits include the Overflow Flag (OV) bit, Overflow Mode (OVM) bit, Interrupt Mask
(INTM) bit, Auxiliary Register Pointer (ARP) bit, and the Data Memory Page Pointer (DP) bit. These
bits are stored (by the SST instruction) in the data memory word as follows:
15
14
13
12
IOV 1OVM IINTM 1
1
11
10
1
9
8
I
7
1 ARP 11
6
5
1
4
3
I 1 11
2
1
0
1 1 11 1 DP
I
Note: See LST.
3-59
SUB
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
[]
[]
SUB
SUB
[, ]
H, < shift> [, < ARP > ]]
{ * I* + I* -
O:::;shift :::;15
O:::;dma:::;127
ARP=O or 1
Operands:
I
SUB
Subtract from Accumulator with Shift
Operation:
(ACC) - [(dma) X 2 shift]
Encoding:
15
14
13
Direct:
000
Indirect:
000
12
1
11
-+
10
ACC
9
8
7
6
5
4
3
2
1
SHIFT
DATA MEMORY
ADDRESS
SHIFT
SEE SECTION 3.3
0
Description: Contents of data memory address are left-shifted and subtracted from the accumulator.
During shifting, the low-order bits of data are zero-filled and the high-order bit is signextended. The result is stored in the accumulator.
Words: 1
Cycles: 1
Example: SUB
or
SUB
DAT59
*
If current auxiliary register contains the value 59.
AFTER INSTRUCTION
BEFORE INSTRUCTION
ACC
DATA
MEMORY
59
3-60
361
ACC
DATA
MEMORY
59
191
SUBC
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
Operands:
Operation:
SUBC
Conditional Subtract
[]
[ ]
SUBC
SUBC
{*I * + 1*- }L]
0 ~ dma ~ 127,
ARP = 0 or 1
(ACC) - [(dma) x 2 15 ]-adder output
If (hig h-order bits of adder output) > 0
Then (adder output) * 2 + 1 -+ ACC
Else (ACC) x 2 -+ ACC
Encoding:
15
14
13
12
11
Direct:
o
o
0
Indirect:
o
o
0
10
1
9
8
7
00101
o
0
I 1I
6
5
4
3
2
1
I
0
DATA MEMORY
ADDRESS
SEE SECTION 3.3
Description: This instruction performs conditional subtraction which can be used for division in
algorithms.
Words: 1
Cycles: 1
Note: The next instruction after SUBC cannot use the accumulator.
3-61
SUBH
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
I
SUBH
Subtract from High-Order Accumulator
[ ]
[]
SUBH
SUBH
Operands:
O=::;;dma=::;; 127
ARP=O or 1
Operation:
(ACC) -
[(dma) x 2 16 ]
-+
ACC
Encoding:
15
13
12
11
10
9
1
0
0
0
1
0
0
0
Direct:
0
Indirect:
0
14
1
1
{ * I * + I * - } [, < ARP > ]
8
7
6
5
4
3
2
01 01
DATA MEMORY
ADDRESS
o 11
SEE SECTION 3.3
1
0
Description: Subtract the contents of specified data memory location from the upper half of the
accumulator. The result is stored in the accumulator.
Words: 1
Cycles: 1
Example: SUBH
or
SUBH
DAT33
If current auxiliary register contains the value 33.
*
AFTER INSTRUCTION
BEFORE INSTRUCTION
DATA
MEMORY
33
51
31
ACC
16 15
171
DATA
MEMORY
33
31
0
01
I
ACC
Note: The SUBH instruction can be used for performing 32-bit arithmetic.
3-62
51
16 15
121
0
01
SUBS
Subtract from Low Accumulator
with Sign-Extension Suppressed
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
[ ]
[ ]
SUBS
SUBS
SUBS
{*I * + 1* -
}[,]
Q~dma~127
Operands:
ARP=Q or 1
Operation:
(ACC) - (dma)
Encoding:
15
Direct:
0
13
1
0
Indirect:
Description:
14
-+
ACC
12
11
10
0
0
0
0
0
0
9
7
8
0
1
5
6
1
1
11
I
4
3
2
1
0
DATA MEMORY
ADDRESS
SEE SECTION 3.3
Subtract contents of a specified data memory location from accumulator with signextension suppressed. The data is treated as a 16-bit positive integer rather than a two's
complement integer.
Words: 1
Cycles: 1
Example: SUBS
or
SUBS
DAT61
*
If current auxiliary register contains the value 61 .
AFTER INSTRUCTION
BEFORE INSTRUCTION
ACC
DATA
MEMORY
61
>0 0 0 0 FlO 5
>F
0 0 3
ACC
>0 0 0 0 0 1 0 2
DATA
MEMORY
61
>F 0 0 3
I
3-63
TBLR
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
Operands:
TBLR
Table Read
TBlR
TBlR
[]
[]
{ * I * + I * - } [, < ARP > ]
O~dma~127
ARP=O or 1
Operation:
I
(PC) + 1 --. TOS
(ACC) --. PC --. address lines A 11 through AO
data bus 015 through 00--' dma
(TOS) --. PC
Encoding:
15
14
13
12
11
Direct:
o
1
1
o
0
DATA MEMORY
ADDRESS
Indirect:
o
1
1
o
0
SEE SECTION 3.3
10
9
8
7
6
5
4
3
2
1
0
Description: This instruction transfers a word from anywhere in program memory (i.e., internal ROM,
external ROM, external RAM) to the specified location in data memory. The three-cycle
instruction is as follows:
Prefetch:
MEN goes low and the TBlR instruction opcode
is fetched. The previous instruction is executing.
Cycle 1:
MEN goes low. The address of the next instruction is placed onto address bus, but data bus is
not read. Program counter is pushed onto stack.
Twelve lSBs of the accumulator contents are
loaded into the program counter.
Cycle 2:
MEN goes low. Contents of program counter are
buffered to address lines. Address memory location is read and is copied into specified RAM location. The new program counter is popped from
the stack.
Cycle 3:
MEN goes low. Next instruction opcode is
prefetched.
Words: 1
Cycles: 3
Example: TBLR
TB LR
OAT4
*
If current auxiliary register contains the value 4.
(Continued)
3-64
TBLR
TBLR
AFTER INSTRUCTION
BEFORE INSTRUCTION
ACC
PROGRAM
MEMORY
17
DATA
MEMORY
4
171
I
I
3061
751
ACC
PROGRAM
MEMORY
17
DATA
MEMORY
4
17
I
I
I
3061
3061
Note: This instruction is useful for reading coefficients that have been stored in program ROM, or timedependent data stored in RAM.
I
3-65
TBLW
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
Operands:
TBLW
Table Write
[ ]
[ ]
TBLW
TBLW
{*J * + J* -
}L]
0~dma~127
ARP=O or 1
Operation:
I
(PC) + 1 -+ TOS
(ACC) -+ PC -+ address lines A 11 through AO
(dma) -data bus D15 through DO
(TOS)-PC
Encoding:
15
14
Direct:
0
1
13
12
11
10
9
8
0
0
1
Indirect:
0
1
1
1
6
7
1
0
5
4
3
2
1
0
DATA MEMORY
ADDRESS
SEE SECTION 3.3
Description: This instruction transfers a word from the specified location in data memory to a location in
external program RAM. The three-cycle instruction is as follows:
Prefetch:
MEN goes low and the TBLR instruction opcode
is fetched. The previous instruction is executing.
Cycle 1:
MEN goes low. The address of the next instruction is placed onto address bus, but data bus is
not read. Program counter is pushed onto stack.
Twelve LSBs of the accumulator contents are
loaded into the program counter.
Cycle 2:
WE goes low. Contents of program counter are
buffered to address lines. Contents of specified
data memory address are placed on the data bus.
The new program counter is popped off of stack.
Cycle 3:
MEN goes low. Next instruction opcode is
prefetched.
Words: 1
Cycles: 3
Example: TBLW DAT4
TBLW *
If current auxiliary register contains the value 4.
(Continued)
3-66
TBLW
TBLW
AFTER INSTRUCTION
BEFORE INSTRUCTION
ACC
DATA
MEMORY
4
I
PROGRAM
I
MEMORY
17
171
ACC
751
DATA
MEMORY
4
I
PROGRAM
I
3061
MEMORY
17
171
751
751
Note: The TBLW and OUT instructions use the same external signals and thus cannot be distinguished when writing to program memory addresses 0 through 7.
I
3-67
XOR
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
I
XOR
Exclusive-OR with Low-Order Bits of Accumulator
XOR
XOR
[ ]
[< label>]
{* 1* + 1* - }[, ]
Operands:
O::;dma::;127
ARP=O or 1
Operation:
Zero. XOR. high-order ACC bits: (dma). XOR. low-order ACC bits-ACC
Encoding:
15
Direct:
0
Indirect:
0
14
13
12
11
1
7
10
9
8
0
0
0101
0
0
o 11
6
1
5
4
3
2
0
DATA MEMORY
ADDRESS
SEE SECTION 3.3
Description: The low-order bits of the accumulator are exciusive-ORed with the specified data memory
address and concatenated with the exclusive-OR of a" zeroes and the high-order bits
of the accumulator. The exclusive-OR operation follows the truth table below:
DATA MEMORY BIT
ACC BIT (BEFORE)
ACC BIT (AFTER)
0
1
0
1
0
1
1
0
0
0
1
1
Words: 1
Cycles: 1
Example: XOR
or
XOR
DAT45
*
If current auxiliary register contains the value 45.
BEFORE INSTRUCTION
DATA
MEMORY 1
45
ACC
>F
F
0
0
>0 F F F 0 F F F
AFTER INSTRUCTION
DATA
MEMORY
45
ACC
>F
F
0
0
>0 F F F F 0 F F
I
Note: This instruction is useful for toggling or setting bits of a word for high-speed control. Also, the one's
complement of a word can be found by exclusive-DRing it with all ones.
3-68
ZAC
ZAC
Zero the Accumulator
Operands:
None
Operation:
0 -+ ACC
Encoding:
15
14
o
Description:
ZAC
[< label>]
Assembler Syntax:
13
12
11
10
9
8
1
7
6
5
4
3
2
0
o
000
0
The accumulator is cleared (zeroed).
I
Words: 1
Cycles: 1
Example: ZAC
BEFORE INSTRUCTION
ACe
IA
F
F
F
F
F
F
F
AFTER INSTRUCTION
I
ACC
I
0
0
0
0
0
0
0
0
I
3-69
ZALH
ZALH
Zero Accumulator and Load High
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
[ ]
[ ]
ZALH
ZALH
{ * I * + I * - } [, < ARP > ]
Q~dma~127
Operands:
ARP=Q or 1
I
Operation:
(dma) X 216
Encoding:
15
Direct:
Indirect:
-+
ACC
13
12
11
10
9
8
0
1
0
0
1
0
0
1
0
0
1
0
I0 I
1I
14
7
6
5
4
3
0
2
DATA MEMORY
ADDRESS
1
SEE SECTION 3.3
Description: ZALH clears the accumulator and loads the contents of the specified data memory location
into the upper half of the accumulator. The lower half of the accumulator remains clear.
Words: 1
Cycles: 1
Example: ZALH
or
ZALH
DAT29
*
If current auxiliary register contains the value 29.
AFTER INSTRUCTION
BEFORE INSTRUCTION
DATA
MEMORY
29
ACC
>3
F
0
0
>0 0 7 7 F F F F
DATA
MEMORY
29
ACC
Note: ZALH can be used for implementing 32-bit arithmetic.
3-70
>3
F 0
0
>3 F 0 0 0 0 0 0
I
ZALS
Zero Accumulator and Load Low
with Sign-Extension Suppressed
Assembler Syntax:
Direct Addressing:
Indirect Addressing:
[]
[ ]
ZALS
ZALS
ZALS
{* 1* + 1* - }[, ]
Q~dma:::;;127
Operands:
ARP=Q or 1
Operation:
(dma)
Encoding:
15
Direct:
Indirect:
-+
ACC
12
11
10
9
8
0
0
0
1
1
01 0 I
0
0
0
1
01
14
13
7
6
5
4
3
2
0
DATA MEMORY
ADDRESS
I
SEE SECTION 3.3
Description: Clear accumulator and load contents of specified data memory location into lower half of the
accumulator. The data is treated as a 16-bit positive integer rather than a two's complement
integer. Therefore, there is no sign-extension as with the LAC instruction.
Words: 1
Cycles: 1
Example: ZALS
or
ZALS
DAT22
*
If current auxiliary register contains the value 22.
AFTER INSTRUCTION
BEFORE INSTRUCTION
DATA
MEMORY
22
>F
7
F
DATA
MEMORY
22
F
>7 F F 0 0 0 3 3
ACe
ACC
>F
7
F
F
>0 0 0 0 F 7 F FI
Notes: The following routine reveals the difference between the ZALS and the LAC instruction. Data
memory location 1 contains the number> FA37.
ZALS
ZAC
DAT1
LAC
DAT1
(ACC) = > OOOOFA37
ZeroACC
(ACC)
> FFFFFA37
=
ZALS is useful for 32-bit arithmetic operations.
3-71
I
3-72
I
METHODOLOGY
FOR APPLICATION DEVELOP'MENT
I
4.
METHODOLOGY FOR APPLICATION DEVELOPMENT
4.1
OUTLINE OF DEVELOPMENT PROCESS
A number of development tools are required for designing a system with a microprocessor. This
section describes the facilities which are available for the TMS3201 0 and illustrates how to use them
for developing an application. A typical application development flowchart is shown in Figure 4-1.
SYSTEM SPECIFICATION
I
CODE PROGRAM
SOFTWARE LIBRARIES
TRANSLATE TO MACHINE CODE
EXECUTE XDS/320 ASSEMBLER
HARDWARE/SOFTWARE INTEGRATION
XDS/320 EMULATOR
FIGURE 4-1 - FLOWCHART OF TYPICAL APPLICATION DEVELOPMENT
After defining the specifications of the system, the designer should draw a flowchart of the
software and a block diagram of the hardware. The processor's performance is then evaluated to
determine the feasibility of implementing the algorithm via the TMS32010 Evaluation Module. The
full algorithm is coded using assembly language. The program is assembled and then verified using
the XDS/320 Macro Assembler and Linker and, optionally, the XDS/320 Simulator. Several
iterations of the program are usually required to correctly code the algorithm. The verified program
is integrated into the hardware, and the prototype system is debugged by using the XDS /320
Emulator.
4-1
4.2
DESCRIPTION OF DEVELOPMENT FACILITIES
Five development facilities aid in the design and implementation of TMS32010 applications. Each of
the following five development facilities provides a tool for one of the steps involved in developing
an application:
4.2.1
•
The TMS32010 Evaluation Module is used to appraise the performance of the processor. A
software library capability is used to simplify and standardize code development.
•
The XDS/320 Assembler and Linker translates an assembly language program into a loadable
object module.
•
The XDS/320 Simulator accepts downloaded object code and executes the program via a
simulated TMS32010 in a debug mode, thus allowing software debug before attempting
hardware debug.
•
The XDS/320 Emulator integrates the processor into the hardware design by providing a
means to debug both software and hardware together.
TMS32010 Evaluation Module
The TMS32010 Evaluation Module (EVM) is a single board which enables a user to determine
inexpensively if the TMS32010 meets the speed and timing requirements of his application. The
EVM is a stand-alone module which contains all the tools necessary to evaluate the TMS32010.
I
Communication to a host computer and to several peripherals is provided on the EVM. Dual EIA
ports allow the EVM to be connected to a terminal and a host computer. The EVM can also be
configured with a line printer on one port; the other port is connected to either a terminal or a host
computer. As either the host computer or the terminal feeds the assembly language program to the
EVM, the EVM assembles the code. A built-in cassette tape interface can also be used to save code
on tape to be reloaded at a later time. An EPROM programmer is also provided for saving code.
Alternatively, code can be executed directly by the EVM through its target connector.
The EVM can accept either source or object code from a host computer or terminal. A line-oriented
text editor, an assembler which permits symbolic addressing of memory locations, and a reverse
assembler that changes machine code back into assembly language instructions are provided for
programming ease. The debug mode gives access to all of the TMS3201 O's registers and memory.
Eight breakpoints on program addresses and the ability to single-step program execution have been
incorporated for monitoring device operation.
4.2.2
XDS/320 Macro Assembler/Linker
The XDS/320 Macro Assembler translates TMS32010 assembly language into executable object
code. The assembler allows the programmer to work with mnemonics rather than hexadecimal
machine instructions and to reference memory locations with symbolic addresses. This allows
software to be designed more efficiently and reliably.
The XDS/320 Macro Assembler supports macro calls and definitions along with conditional
assembly. It provides the user with a comprehensive set of error diagnostics. The XDS/320 Macro
Assembler produces a listing and an object file, and will optionally print a symbol tablel crossreference listing.
Assembler directives which affect program assembly are provided for the user. Some directives
affect the location counter and make sections of the program relocatable. Constants for data and
text are defined by using directives. Symbols defined in one assembly can be used in another
assembly with the REF and DEF directives. These external symbols allow separate modules to be
linked together.
4-2
The XDS/320 Linker permits a program to be designed and implemented in separate modules which
will later be linked together to form the complete program. This allows the same modules (i.e., a
filter module) to be used in many programs. The linker assigns values to relocatable code, creating
an object file which can be executed by the simulator or emulator.
The linker resolves external definitions and references from different assemblies, and thereby links
several modules together. More than one assembly may be linked together to create a module
which may be linked again to the main program. An intermediate partial linkage does not require
that all external references be resolved, but in the final linking process, there should be no
unresolved references. Another function of the linker is to assign absolute values to relocatable
code. The final output of the linker can then be loaded into either the simulator or the emulator.
A source code macro library can be maintained in a directory to be assembled with the main
program. This allows commonly used routines to be accessed by more than one program and to be
used to decrease program development time. The mnemonics are macro calls which expand into
assembly code.
The macro library typically should contain user-defined macros and the macros defined in Section
7. These macros simplify the generation of an assembly language program. Examples include
comparing a word in memory to a word in the accumulator, shifting right, and moving numbers
between registers.
The XDS /320 Macro Assembler and Linker are currently available on several host computers,
including the TI990(DX10) VAX(VMS) and IBM MVS and eMS operating systems. Currently in
development is software to support the VAX(UNIX), DEC PDP11(RSX), IBM PC(DOS) and TI
professional computer (DOS) operating system. Contact your local TI representative for availability
or further details.
4.2.3
XDS/320 Simulator
The XDS/320 Simulator is a software program that simulates operation of the TMS32010 to allow
program verification. The debug mode enables the user to monitor the state of the simulated
TMS32010 while the program is executing.
The simulator program uses the TMS32010 object code, produced by the XDS/320 Macro
Assembler/ Linker. Input and output files may be associated with the port addresses of the I/O
instructions in order to simulate I/O devices which will be connected to the processor. The interrupt
flag can be set periodically at a user-defined interval for simulating an interrupt signal. Before
initiating program execution, breakpoints may be defined, and the trace mode set up.
During program execution, the internal registers and memory of the simulated TMS32010 are
modified as each instruction is interpreted by the host computer. Execution is suspended when
either 1) a breakpoint or error is encountered, 2) the step count goes to zero, or 3) a branch to 'self'
is detected. Once program execution is suspended, the internal registers and both program and
data memories can be inspected and/or modified. The trace memory can also be displayed. A
record of the simulation session can be maintained in a journal file, so that it may be replayed to
regain the same machine state during another simulation session.
The XDS/320 Simulator is currently available for the VAX(VMS).
4-3
I
4.2.4 XDS/320 Emulator
The XDS/320 Emulator is a self-contained system that has all the features necessary for real-time
in-circuit emulation. This allows integration of the user hardware and software in the debug mode.
Three EIA ports have been provided on the emulator to interface with a host system. The first EIA
port provides a connection for a computer, the second port for a terminal, and the third port for a
printer or a PROM programmer. Using a standard EIA port, the object file produced by the macro
assembler/linker can be downloaded into the emulator, which can then be controlled through a
terminal. In addition, source code can be downloaded to the emulator. A line-by-line assembler with
forward and reverse referencing labels is provided on the XDS to assemble the source.
A pin-compatible target connector plugs into the TMS3201 0 socket to enable real-time emulation.
Three clock options are available. First, a 20-MHz clock is available on the emulator. In addition, an
external clock source can be used by attaching a crystal to the target connector, or by connecting a
signal generator to the emulator.
The emulator operates in one of three memory modes: 1) software development mode, 2)
microcomputer mode, or 3) microprocessor mode. In the software development mode, the entire
8K bytes of program memory reside within the emulator. In the microcomputer mode, 3K bytes
reside within the emulator while 5K bytes reside on the target system. The microprocessor mode is
used when all 8K bytes of program memory exist on the target system.
I
By setting breakpoints based on internal conditions or external events, execution of the user's
program can be suspended and control given to the XDS monitor. While in the monitor, all registers
and memory locations can be inspected and modified. Single-step execution is also available. A
single read or write to an I/O port can be performed to test peripheral devices in the prototype
system. Full trace capabHities at full speed and a reverse assembler that translates machine code
back into assembly instructions are also included to increase debugging productivity.
4.3 APPLICATION DEVELOPMENT PROCESS EXAMPLE
The design and implementation of a TMS32010-based discrete-time filter is presented below to
illustrate the development process. The filter design is derived from the system specification, using
digital signal processing theory. A macro library is used to help code the program. The assembler
and simulator verify that the program executes the filter properly. The processor is then integrated
into the prototype system by using the emulator.
4.3.1
System Specification
Table 4-1 defines the specifications of the discrete-time filter.
TABLE 4-1 - FILTER SPECIFICATIONS
PARAMETER
VALUE
UNIT
Sample frequency (fs)
10
kHz
Corner frequency (f co)
2
kHz
-2
dB
Attenuation at f = 1.2 fco
-15
dB
Passband ripple
± 1.5
dB
Attenuation at f = feo
4-4
4.3.2
System Design
The equation for the above discrete-time filter was derived as follows:
y(n)= -.2302699x(n) + .1559177x(n-1) + .2211667x(n-2) + .1119031 x(n-3)
- .1124507 x( n-4) - . 1485743 x( n-5) + .2046856 x( n-6) + .7409326 x( n-7)
+ 1.0 x(n-8) + .7409326 x(n-9) + .2046856 x(n-1 0) - .1485743 x(n-11)
- .1124507 x(n-12) + .1119031 x(n-13) + .2211667 x(n-14)
+ .1559177 x(n-15) - .2302699 x(n-16).
where x(n) is the current sample,
x(n -1) is the sample from the previous period,
~
x( n - 16) is the sample from the previous 16th period.
4.3.3
Code Development
The TMS32010 software development cycle is generally a three-step process for the purpose of
translating the filter equation into TMS32010 assembly language. First, a flowchart of the program
is drawn. Then, the example is coded in a high-level language, FORTRAN, to provide structure and
to test if the algorithm is correct before implementing it in assembly language. Finally, the program.
is coded and tested in assembly language using some of the macro library routines.
4.3.3.1
Discrete-Time Filter Flowchart
Figure 4-2 is a flowchart for the software implementation of the discrete-time filter.
OUTPUT FILTERED DATA
FIGURE 4-2 - FLOWCHART OF FILTER IMPLEMENTATION
4-5
4.3.3.2
FORTRAN Program
The following FORTRAN program implements the specified digital filter and provides 1000 outputs.
PROGRAM FILTER
e
C y(n)=-.2302699 x(n) + .1559177 x(n-1) + .2211667 x(n-2) +.1119031 x(n-3)
- .1124507 x(n-4) - .1485743 x(n-5) + .2046856 x(n-6) + .7409326 x(n-7)
e + 1.0 x(n-8) + .7409326 x(n-9) + .2046856 x(n-10) - .1485743 x(n-11)
C - .1124507 x(n-12) + .1119031 x(n-13) + .2211667 x(n-14)
e + .1559177 x(n-15) - .2302699 x(n-16).
e
e
REAL*4 X(17),CX(17),Y
C
e
Initialize the constants for the filter equation
C
DATA
ex
1
1
1
II
C
I
100
=0
I
/-.2302699,.1559177,.2211667,.1119031,-.1124507,
-.1485743,.2046856,.7409326,1.0,.7409326,
.2046856,-.1485743,-.1124507,.1119031,.2211667,
.1559177,-.2302699/
=I
+ 1
C
C
Input sampled data
C
110
READ (55,110) IX
FORMAT (16)
X(l) = IX
C
C
Filter data
C
Y
=0
DO J = 1,17
Y = Y + CX(J)*X(J)
END DO
C
C
Shift data to new variables
C
DO J = 16,1,-1
X(J)
END DO
= X(J-1)
C
C
Output filtered data
C
TYPE *,Y
c
200
4.3.3.3
IF (1 .LE. 1000) GO TO 100
END
Assembly Language Program Using Relocatable Code
The same discrete-time filter can be implemented in TMS32010 assembly language using
relocatable code. The FORTRAN program should not be directly translated into assembly language.
Assembly language code can be made more efficient than the FORTRAN implementation by taking
advantage of the processor's architecture. The assembly language implementation of the
FORTRAN program is described in the following paragraphs.
4-6
Two library macros (PROG and MAIN) have been used in the example program to simplify the
coding process and to standardize the program structure. One advantage of using macros for
standardizing program structure is that different programmers can easily trade relocatable modules
if they have used the same structure. The PROG macro begins the module with an lOT directive.
This directive gives the module a name to be used later during link and also initializes some values in
the assembler's symbol table. The macro MAIN labels the beginning of the main routine, initializes
the constants ONE and MINUS, and defines the variables XRO and XR1.
The coefficients in the equation are converted to integer arithmetic for this program. To maintain a
maximum amount of accuracy, the coefficients should be factored by 2** - 15, which will create a
Q15 number. After factoring the filter equation, it becomes:
y(n) = [ - 7545x(n) + 5109 x(n-1) + 7247 x(n-2) + 3667 x(n-3)
- 3685 x(n-4) - 4868x(n-5) + 6707 x(n-6) + 24279 x(n-7)
+ 32767 x(n-8) + 24279 x(n-9) + 6706 x(n-10) - 4868 x(n-11)
- 3685 x(n-12) + 3667 x(n-13) + 7247 x(n-14) + 5109 x(n-15)
- 7545 x(n-16)]*2** - 15.
Contants are listed in program memory in a table so as to define the coefficients in data memory. •
Constants are then read into data memory using the TB LR instruction. The user loads a one in the T
register to access the table. The MPYK instruction puts the address of the table into the P register.
Then, the PAC instruction loads it into the accumulator. A loop is set up to move all of the
constants into data memory.
The BIO pin is connected to the FIFO empty line. A BIOZ instruction is used to synchronize the
external hardware with the program. As long as the FIFO buffer is empty, the processor polls the
device until data is available.
The sampled data is read into data memory, and the filter equation is calculated. If the equation is
coded in a loop, both of the auxiliary registers must be used as pointers. By starting one of the lists
at location zero in data memory, the pointer for that list can also be used as the loop counter. The
calculation time can be reduced by a factor of two if the equation is implemented using straight-line
code. The user must decide whether program size or execution time is more important in his
application.
The data is shifted in memory as the equation is computed, making a separate loop to do the shift
operation unnecessary. A 0.5 is added to the result to round up the number before storing the
result. The output is written to a 0/ A converter. Then the whole process is repeated.
The following assembly language program implements the digital filter:
*
*
*
*
The MLIB directive is used to reference a file containing
source code for the two macros, PROG and MAIN.
*
*
*
Xl
X17
CX1
eX17
MLIB
'MACRO.SRC'
PROG
FLTR
REAL
4 X(17),CX(17),Y
DSEG
BSS
BSS
BSS
BSS
16
1
16
1
the
BEGIN DATA SEGMENT
16 WORDS NAME Xl
1 WORD NAME X17
16 WORDS NAME eX1
1 WORD NAME eX17
4-7
Y
1
B
RET
FLTR
DATA
DATA
DATA
-7545,5109,7247,3667,-3685,-4868
6707,24279,32767,24279,6707
-4868,-3685,3667,7247,5109,-7545
MAIN
FLTR
*
*
COEF
1 WORD NAME Y
END DATA SEGMENT
BSS
DEND
*
********************************************************************
DATA
CX /-.2302699,.1559177,.2211667,.1119031,-.1124507,
*
*
1
-.1485743,.2046856,.7409326,1.0,.7409326,
*
1
.2046856,-.1485743,-.1124507,.1119031,.2211667,
*
1
.1559177,-.2302699/
********************************************************************
*
*
*
*
*
*
I
ONE is a data memory location containing a 1. COEF is the address
where the filter coefficient table begins. The next four lines of
code put the value of COEF in the accumulator so that TBLR can be
used for reading in the coefficients.
ReONST
LT
MPYK
PAC
LARK
LARK
LARP
TBLR
ADD
BANZ
ONE
COEF
ARO ,16
AR1,CX1
1
*+,ARO
ONE
RCONST
* Test FIFO to see if it is empty. The next line of code branches
* itself till the BIO pin goes low.
*
WAIT
BIOZ
WAIT
* Input sampled data
*
*
IN
Xl,PAO
*
*******************************************************************
= 1,17
* DO YJ =
Compute filter equation
Y + CX(J)*X(J}
*
*
*
END DO
*
*
DO J = 1,16
*
X(J) = X(J-l)
Shift variables
*
END DO
*******************************************************************
*
*
*
*
*
LOOP
4-8
X17 is the data memory address of X(17}.
CX17 is the data memory address of CX(17}.
LARK
ARO,X17
LARK
ZAC
LT
MPY
LTD
MPY
ARl,CX17
*-,AR1
*-,ARO
*,AR1
*-,ARO
on
BANZ
APAC
*
*
*
*
*
*
LOOP
Round up
ONE,14
ADD
Output results
SACH
OUT
B
4.3.3.3.1
Y,l
Y,PA1
WAIT
Assembler Output
The XDS/320 Macro Assembler requires a source file which contains the assembly language
program. Two output files are created by the assembler. One output file is a listing file that prints
the object code and the source statement for each instruction. The other output file contains the
object code in standard 990 tagged format. The listing file for the filter program is shown below,
although certain comment statements have been deleted. Object code followed by an apostrophe
indicates that the code is relocatable (i.e., the B FLTR statement).
LISTING FILE
320 FAMILY MACRO ASSEMBLER 2.0 83.010
FLTR
0001
0002
0003
0004
0005
0006
0001
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0000
0000
0000
0010
0011
0021
0022
0023
*
*
*
*
*
*
*
Xl
X17
CX1
CX17
Y
*
0000 F900
0001 0014'
0019 0002 7F8D
0020
*
0021 0003 E287 COEF
0004 13F5
0005 1C4F
0006 OE53
0007 F19B
0008 ECFC
0022 0009 1A33
OOOA 5ED7
OOOB 7FFF
OOOC SED7
0000 1A33
0023 OOOE ECFC
OOOF F19B
9:20:28
2/21/83
PAGE 0001
The MLIB directive is used to reference a file containing source code for the two macros, PROG and MAIN.
MLIB
'MACRO.SRC'
PROG
lOT
FLTR
'FLTR'
REAL
4 X(17),CX(17),Y
DSEG
BSS
BSS
BSS
BSS
BSS
DEND
16
1
16
1
1
B
FLTR
BEGIN DATA SEGMENT
16 WORDS NAME Xl
1 WORD NAME X17
16 WORDS NAME CX1
1 WORD NAME CX17
1 WORD NAME Y
END DATA SEGMENT
RET
DATA
-7545,5109,7247,3667,-3685,-4868
DATA
6707,24279,32767,24279,6707
DATA
-4868,-3685,3667,7247,5109,-7545
4-9
I
~
0010
0011
0012
0013
0024
0025
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
0044
0045
0046
0047
II
OE53
1C4F
13F5
E287
*
MAIN FLTR
PROG SEG
PSEG
ENTRY POINT
DEF FLTR
0014 1 FLTR
EQU $
MAKE CONSTANT ONE
LACK 1
0014 7E01
SAVE IT
SACL ONE,O
0015 5023 11
ZERO ACCUMULATOR
ZAC
0016 7F89
SUB ONE,O
MAKE -1
0017 1023"
SAVE IT
SACL MINUS,O
0018 5024 11
DSEG
0023
BSS 1
CONSTANT ONE
ONE
0023
CONSTANT -1
MINUS BSS 1
0024
BSS 1
TEMP 0
XRO
0025
BSS 1
TEMP 1
XR1
0026
DEF ONE,MINUS
ALLOW EXTERNAL USE
DEF XRO,XR1
OF VARIABLE
DEND
END OF DATA
0027
************************************************************
DATA
CX /-.2302699,.1559177,.2211667,.1119031,-.11
*
*
1
-.1485743,.2046856,.7409326,1.0,.7409326
*
1
.2046856,-.1485743,-.1124507,.1119031,.2
*
1
.1559177,-.2302699/
************************************************************
0014
*
*
*
*
*
*
0019
001A
001B
001C
0010
001E
001F
0020
0021
0022
6A23
8003
7F8E
7010
7111
6881 RCONST
67AO
0023"
F400
001E'
11
0048
0049
0050
0051
0052 0023 F600
0024 0023 1
0053
0054
0055
0056 0025 4000"
0057
0058
0059
0060
0061
0062
0063
0064
0065
0066
4-10
ONE is a data memory location containing a 1. COEF is the
address where the filter coefficient table begins. The next
four lines of code put the value of COEF in the accumulator
so that TBLR can be used for reading in the coefficients.
LT
MPYK
PAC
LARK
LARK
LARP
TBLR
ADD
BANZ
ONE
COEF
ARO ,16
AR1,CX1
1
*+,ARO
ONE
RCONST
*
* Test FIFO to see if it is empty. The next line of code
* branches on itself till the BIO pin goes high.
*
WAIT
*
*
*
BIOZ
WAIT
Input sampled data
IN
X1,PAO
*
************************************************************
* DO yJ == y1,17
Compute filter equation
* END DO + CX(J)*X(J)
*
* DO J = 1,16
*
Shift variables
= X(J-1)
* END X(J)
DO
*************************************************************
0067
0068
0069
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
0090
*
* X17 is the data memory address of X(17).
* CX17 is the data memory address of CX(17).
*
0026 7010 ,
LARK
ARO,X17
*
0027 7121
LARK
AR1,CX17
0028 7F89
ZAC
0029 6A91
LT
*-,AR1
002A 6090
MPY
*-,ARO
002B 6B81 LOOP
LTD
*,AR1
002C 6090
MPY
*-,ARO
BANZ
LOOP
002D F400
002E 002B'
APAC
002F 7F8F
*
Round up
*
*
ADD
ONE,14
0030 OE23"
*
Output results
*
*
SACH
Y,l
0031 5922"
OUT
Y,PA1
0032 4922"
0033 F900
B
WAIT
0034 0023'
•
THE FOLLOWING SYMBOLS ARE UNDEFINED
*+
*$$LAB
*
NO ERRORS,
NO WARNINGS
Although the symbols above are undefined, this is a natural result of the macros used and should be
ignored.
The following example is the tagged object code produced by the XDS/320 Assembler. The tags
are used by the linker when it is producing a link module.
TAGGED OBJECT CODE
K0035FLTR
M0027$DATA 000050014FLTR W00230NE
00007F43AF
W0025XRO
0000W0026XR1
0000W0024MINUS 0000AOOOOBF900C0014B7F8D7F1A9F
BE287B13F5B1C4FBOE53BF19BBECFCB1A33B5ED7B7FFFB5ED7B1A33BECFCBF19B7F036F
BOE53B1C4FB13F5BE287A0014B7E01#5023007FB7F89#1023007F#5024007F7F281F
A0019#6A23007FB8003B7F8EB7010B7111B6881B67AO#0023007FBF400C001E7F250F
BF600C0023#4000007FB7010B7121B7F89B6A91B6D90B6B81B6D90BF400C002B7F1D5F
B7F8F#OE23007F#5922007F#4922007FBF900C00237F6E6F
FLTR
2/21/83
9:20:28
ASM320 2.0 83.010
4.3.3.3.2
FLTR
FLTR
FLTR
FLTR
FLTR
FLTR
FLTR
FLTR
Program Linkage
The linker must be executed even if the program is contained in a single module. The control file
required by the linker specifies the task name, defines the starting location for the data and program
4-11
segments, and indicates the object files to be linked. The control file which was used to link the
example program is as follows:
FORMAT ASCII
TASK DEV
PROGRAM> 0000
DATA >0000
INCLUDE S4USR.LVK111 .FLTR.OBJ
END
Two files are produced by the linker. The linked object file is an output file containing the load
module. The link listing file is an output file containing a listing of the command control file, a map
of the segments and modules which were linked, and a cross-reference listing of the externally
defined variables. The link listing file and the linked object file are shown below. The object file can
be loaded into the simulator or emulator for program debugging.
LINK LISTING FILE
I
DX/9900 LINKER
COMMAND LIST
VERSION 2.0.0
FORMAT ASCII
TASK DEV
PROGRAM >0000
DATA >0000
INCLUDE S4USR.LVK111.FLTR.OBJ
END
DX/9900 LINKER
VERSION 2.0.0
LINK MAP
82.312
2/21/83
9:29:30
PAGE
1
82.312
2/21/83
9:29:30
PAGE
2
9:29:30
PAGE
3
= S4USR.LVK111.FLTR.CF
LINKED OUTPUT FILE = S4USR.LVK111.FLTR.LINKOBJ
LIST FILE = S4USR.LVK111.FLTR.LINKLIS
OUTPUT FORMAT = ASCII
CONTROL FILE
1 ---->OVERWRITTEN SEGMENTS IN MODULE DEV
DX/9900 LINKER
VERSION 2.0.0 82.312 2/21/83
PHASE 0
MODULE
FLTR
$ DATA
DEV
MODULE
ORIGIN
=
0000
LENGTH
= 0000
NO
ORIGIN
LENGTH
TYPE
DATE
TIME
1
1
0000*
0000*
0035
0027
INCLUDE
2/21/83
9:20:28
CREATOR
ASM320
D E FIN I T ION S
NAME
*FLTR
*XR1
VALUE NO
0014*
0026*
1
1
NAME
*MINUS
LENGTH OF REGION FOR TASK
4-12
VALUE NO
0024*
1
NAME
*ONE
= 0000
VALUE NO
0023*
1
NAME
*XRO
VALUE NO
0025*
1
NUMBER OF WARNINGS MESSAGES PRINTED
NUMBER OF RECORDS FOR MODULE DEV
TOTAL CARDS PRINTED
****
LINKING COMPLETED
2/21/83
=
=
=
1
6
6
9:29:34
The following object file is an output produced by the linker:
LINKED OBJECT FILE
KOOOODEV
90000BF900B0014B7F8DBE287B13F5BIC4FBOES3BF19BBECFC7F1C4F
B1A33BSED7B7FFFBSED7B1A33BECFCBF19BBOES3B1C4FB13FSBE28790014B7E017FOAOF
B5023B7F89BI023BS02490019B6A23B8003B7F8EB7010B7111B688IB67AOB00237F1B8F
BF400BOOIEBF600B0023B4000B7010B7121B7F89B6A91B6D90B6B8IB6D90BF4007F177F
B002BB7F8FBOE23BS922B4922BF900B00237F80BF
DEV
2/21/83
9:29:30
MPPLINK· 82.312
DEV
DEV
DEV
DEV
DEV
DEV
I
4.3.3.4 Assembly Language Program Using Absolute Code
Through the use of the macros, PROG and MAIN, the above program is well structured and
relocatable. During link time, the program and data memory locations for the coefficient ex (Le.,
the value for the constant COEF), the data memory location of the variable X, and the program
memory location of the MAIN program, FLTR, can be established.
In contrast to the relocatable code approach is one that uses absolute code. Although the use of
absolute code makes it somewhat easier to write a single program, this program is not relocatable.
The same program that was coded in relocatable code in Section 4.3.3.3 is shown below coded in
absolute code.
SOURCE FILE
IDT
*
*
*
*
*
*
*
*
Xl
IDT is a directive which assigns a name to the module. The EQU
directive assigns values to constants. The constants below
will refer to locations in data memory. Unlike the above
program, these data memory locations are fixed and cannot be
changed at link time. As a result, this module would be very
difficult to use as part of another program.
X17
CX17
Y
ONE
*
**
*
*
*
*
*
'FLTR'
EQU
EQU
EQU
EQU
EQU
17
33
16
34
127
AORG
10
The AORG directive establishes the location in program memory where
the code sequence will begin. In this case, the following section
of code will begin at program memory location 10. This contrasts
with the above program (Section 4~3.3.3) which allows the block of
memory the program will occupy to be established during link time.
4-13
*
ReONST
*
WAIT
*
LARK
LARK
ARO,16
AR1,0
LARP
TBLR
ADD
BANZ
1
*+,ARO
ONE
RCONST
BIOZ
WAIT
IN
Xl, PAO
LARK
LARK
ZAC
LT
MPY
ARO,X17
AR1,CX17
LTD
MPY
BANZ
APAC
*,AR1
*- ,ARO
LOOP
ADD
ONE,14
SACH
OUT
B
Y,l
Y,PA1
WAIT
*
*
LOOP
I
*- ,AR1
*-,ARO
*
*
Below is the listing file for this program using absolute code.
LISTING FILE
FLTR
320 FAMILY MACRO ASSEMBLER
1.0
10:16: 5
12/22/82
PAGE 0001
0001
IDT
'FLTR'
0002 *
0003 * IDT is a directive which assigns a name to the module. The EQU
0004 * directive assigns values to constants. The constants below *
0005 * will refer to locations in data memory. Unlike the above *
0006 * program, these data memory locations are fixed and cannot be
0007 * changed at link time. As a result, this module would be very
0008 * difficult to use as part of another program.
0009 *
0010
0011 Xl
17
EQU
0021 X17
0011
EQU
33
0010 CX17
16
0012
EQU
0022 Y
0013
EQU
34
007F ONE
0014
127
EQU
0015
*
AORG 10
0016 OOOA
0017 *
0018 * The AORG directive establishes the location in program memory
0019 * where * the code sequence will begin. In this case, the fol0020 * lowing section of code will begin at program memory location
0021 * 10. This contrasts with the above program (Section 4.3.3.3)
0022 * which allows the block of memory the program will occupy to
0023 * be established during link time.
0024 *
LARK ARO,16
0025 OOOA 7010
LARK AR1,0
0026 OOOB 7100
4-14
0027
0028
0029
0030
0031
DOOC
0000
OOOE
OOOF
0010
6881
67AO
007F
F400
OOOC
*
RCONST
*
0032
0033 0011 F600 WAIT
0012 0011
0034
*
0035 0013 4011
0036
*
0037 0014 7021
0038 0015 7110
0039 0016 7F89
0040 0017 6A91
0041 0018 6090
0042
*
0043 0019 6B81 LOOP
0044 001A 6D90
0045 001B F400
001C 0019
0046 0010 7F8F
0047
*
0048 001E OE7F
0049
*
0050 OOIF 5922
0051 0020 4922
0052 0021 F900
0022 0011
0053 0023
0054 0023
NO ERRORS, NO WARNINGS
LARP
TBLR
ADD
BANZ
1
*+,ARO
ONE
RCONST
BIOZ
WAIT
IN
X1,PAO
LARK
LARK
ZAC
LT
MPY
ARO,X17
AR1,CX1
LTD
MPY
BANZ
*,AR1
*-,ARO
LOOP
*-,AR1
*-,ARO
I
APAC
ADD
ONE,14
SACH
OUT
Y,l
Y,PA1
WAIT
B
4-15
•
4-16
I
PROCESSOR RESOURCE MANAGEMENT
I
5. PROCESSOR RESOURCE MANAGEMENT
5.1
FUNDAMENTAL OPERATIONS
An understanding of how to use the instructions to perform common tasks is necessary in order to
make efficient use of the instruction set. The following sections discuss implementations of some
fundamental operations using the TMS3201 0 instruction set.
5.1.1
Bit Manipulation
A specified bit of a word from data memory can either be set, cleared, or tested. Such bit
manipulations are accomplished by using the built-in shifter and the logic instructions, AND, OR,
and XOR. In the first example, operations on single bits are performed on the data word VALUE. In
this and the following examples, data memory location ONE contains the value 1 and MINUS
contains the value-1 (all bits set).
**
*
Clear bit S of data memory location VALUE
LAC
XOR
AND
SACL
ONE,S
MINUS
VALUE
VALUE
*
*
*
Set bit 12 of VALUE
**
*
Test bit 3 of VALUE
LAC
OR
SACL
LAC
AND
BZ
ONE,12
VALUE
VALUE
ONE,3
VALUE
BIT3Z
ACC = >00000020
Invert accumulator; ACC
Bit 5 of VALUE is zeroed
= >OOOOFFDF
I
ACC = >00001000
Bit 12 of VALUE is set
ACC = >00000008
Test bit 3 of VALUE
Branch to BIT3Z if bit is clear
More than one bit can be set, cleared, or tested at one time if the necessary mask exists in data
memory. In the next example, the six low-order bits in the word VALUE are cleared if MASK
contains the value 127.
*
*
*
5.1.2
Clear lower six bits of VALUE
LAC
XOR
AND
SACL
MASK
MINUS
VALUE
VALUE
ACC = >0000003F
Invert accumulator; ACC = >OOOOFFCO
Clear lower six bits
Data Shift
There are two types of shifts: logical and arithmetic. A logical shift is implemented by filling the
empty bits to the left of the MSB with zeros, regardless of the value of the MSB. An arithmetic shift
fills the empty bits to the left of the MSB with ones if the MSB is one, or with zeros if the MSB is
zero. The second type of bit padding is referred to as sign extension.
The hardware shift which is built into the ADD, SUB, and LAC instructions performs an arithmetic
left shift on a 16-bit word. This feature can also be used to peform right shifts. A right shift of n is
implemented by peforming a left shift of 16-n and saving the upper word of the accumulator.
5-1
The first example performs an arithmetic right shift of seven on a 16-bit number in the accumulator.
SACL
LAC
SACH
LAC
Move number to memory
Shift left (16-7)
Save high word in memory
Return number back to accumulator
TEMP
TEMP,9
TEMP
TEMP
The second example performs a logical right shift of four on a 32-bit number stored in the
accumulator. The 32-bit results of the shift are then stored in data memory. In this example, the
accumulator initially contains the hex number> 9084C1 B2. The variables, SHIFTH and SHIFTL, will
receive the high word (> 0908) and low word (> 4C1 B) of the shifted results.
I
**
*
Shift the lower word
**
*
Shift the upper word
SACH
SACL
LAC
SACH
LAC
XOR
AND
ADD
SACL
SACH
LAC
XOR
AND
SACL
SHIFTH
SHIFTL
SHIFTL,12
SHIFTL
MINUS,12
MINUS
SHIFTL
SHIFTH,12
SHIFTL
SHIFTH
MINUS,12
MINUS
SHIFTH
SHIFTH
SHIFTH = >9D84
SHIFTL = >C1B2
Ace = >FC1B2000
SHIFTL = >FC1B
Ace = >FFFFFOOO
Ace = >FFFFOFFF
Ace = >00000C1B
Ace = >F9D84C1B
SHIFTL = >4C1B
SHIFTH = >F9D8
Ace = >FFFFFOOO
Ace = >FFFFOFFF
Ace = >00000908
SHIFTH = >09D8
Initial values
Final low-order value
Final high-order value
An arithmetic right shift of four can be implemented using the same routine as shown above, except
with the last four lines omitted.
5.1.3
Fixed-Point Arithmetic
Computation on the TMS32010 is based on a fixed-point two's complement representation of
numbers. Each 16-bit number is evaluated with a sign bit, i integer bits, and 15-i fractional bits. Thus
the number:
o 00000l0fOl00000
decimal point
has a value of 2.625. This particular number is said to be represented in a Q8 format (8 fractional
bits) . Its range is between -128 ( 1000000000000000) and 127.996 (0111111111111111) . The
fractional accuracy of a as number is about .004 (one part in 2**8 or 256).
Although particular situations (e.g., a combination of dynamic range and accuracy requirements)
must use mixed notations, it is more common to work entirely with fractions represented in a Q15
format or integers in a QO format. This is especially true for signal processing algorithms where
multiply-accumulate operations are dominant. The result of a fraction times a fraction remains a
fraction, and the result of an integer times an integer remains an integer. No overflows are possible.
5-2
The difficulty comes during accumulations of the resulting products. In these situations, the
programmer must understand the physical process which underlies the mathematics in order to take
care of potential overflow conditions. The following sections discuss some of the techniques involved
in using this kind of number representation.
5. 1.3. 1 Multiplication
There are a wide variety of situations which might be encountered when multiplying two numbers.
Three of these scenarios are illustrated below:
CASE I -- FRACTION * FRACTION
015 * 015
= 030
0100000000000000 = 0.5 in 015 notation
* 0100000000000000 = 0.5 in 015
00 01000000000000 0000000000000000 = 0.25 in 030
Ldecima, point
Note: Two sign bits remain after the multiply.
I
Generally, the programmer will not want to maintain full precision. In fact, he will probably want to
save a single-precision 06-bit) result. Unfortunately, the upper half of the result does not contain a
full 15 bits of fractional precision since the multiply operation actually creates a second sign bit. In
order to recover that precision, the product must be shifted left by one bit. The following code
excerpt illustrates an implementation of this example:
LT
MPY
PAC
SACH
OPl
OP2
OPl
OP2
= >4000
= >4000
(0.5 in Ql5)
(0.5 in Ql5)
ANS/l
ANS
= >2000
(0.25 in Ql5)
The MPYK instruction in the TMS320 will allow the programmer the ability to multiply by a 13-bit
signed constant. In fractional notation, this means he can multiply a Q15 number by a Q12 number.
This case requires the programmer to shift the resulting number left by four bits to maintain full
precision.
LT
MPYK
PAC
SACH
OPl
2048
OPl
OP2
)4000 (0.5 in Q15)
)0800 (0.5 in Q12)
ANS,4
ANS
)2000 (0.25 in Q15)
5-3
CASE II -- INTEGER * INTEGER
00*00
= 00
= 17
=5
0000000000010001
* 1111111111111 0 11
11111111111111111111111110101011
in 00
in 00
I =85
in 00
......_ _ _ _ _ decimal point
Note: In this case, the extra sign bit does not come into play, and the desired product is entirely in the lower half of the product. The
following program illustrates this example.
LT
MPY
PAC
SACL
OP1
OP2
OP1
OP2
)0011 (17 in QO)
)0005 ( 5 in QO)
ANS
ANS
)0055 (85 in QO)
CASE III -- MIXED NOTATION
I
014 * 014 = 028
0110000000000000
* 0011000000000000
OOlO1 001 0000000000000000000000000
= 1.50
=
in 014
0.75 in 014
= 1. 125 in 028
decimal point
The maximum magnitude of a 014 number is just under two. Thus, the maximum magnitude of the
product of two 014 numbers is four. Two integer bits are required to allow for this possibility, leaving a maximum precision for the product of 13 bits. In general, the following rule applies:
The product of a number with i integer bits and f fractional bits and a second number with j
integer bits and g fractional bits will be a number with (i + j) integer bits and (f + g) fractional
bits. The highest precision possible for a 16-bit representation of this number will have (i + j)
integer bits and (15- i - j) fractional bits.
If, however, the programmer has a prior knowledge of the physical system which is being
modelled, he may be able to increase the precision with which the number is modelled. For example, if he knows that the above product can be no more than 1.8, he could represent the product as
a 014 number rather than the theoretical worst case of 013. The following program illustrates the
above example:
OP1
OP2
OP1
OP2
= >6000
MPY
PAC
SACH
ANS , 1
ANS
=
LT
5-4
= >3000
(1.5 in Q14)
(.75 in Q14)
>2400 (1.125 in Q13)
The techniques which have been illustrated above all truncate the result of the multiplication to the
desired precision. The error which is generated as a result amounts to minus one full LSB. This is
true whether the truncated number is positive or negative. It is possible to implement a simple
rounding technique to reduce this potential error by a factor of two. This is illustrated by the
following code sequence:
LT
MPY
PAC
ADD
SACH
OPI
OP2
OPI
ONE,14
ANS,l
*
OP2
ROUND UP
The error generated in this example is plus one-half LSB whether ANS is positive or negative.
5.1.3.2 Addition
During the process of multiplication, the programmer is not concerned about overflows and needs
only to adjust his decimal point following the operation. Addition is a much more complex process.
First, both operands of an addition must be represented in the same Q-point notation. Second, the
programmer must either allow enough head room in his result to accomodate bit growth or he must
be prepared to handle oveflows. If the operands are only 16 bits long, the result may have to be
represented as a double-precision number. The following example illustrates two approaches to
adding 16-bit numbers:
I
Maintaining 32-Bit Results:
LAC
ADD
SACH
SACL
OPl
OP2
ANSHI
ANSLO
Ql5
Q15
High-order 16 bits of result
Low-order 16 bits of result
Adjusted Decimal Point to Maintain 16-Bit Results:
LAC
ADD
SACH
OPl,lS
OP2,15
ANS
Q14 number in ACCH
Q14 number in ACCH
Q14
Double-precision operands present a more complex problem. In this case, actual arithmetic
overflows or underflows might occur. The TMS32010 provides the programmer with the facility to
check for the occurrence of these conditions using the BV instruction. A second technique is the
use of saturation mode operations which will saturate the result of overflowing accumulations to
the most positive or most negative number. Unfortunately, both techniques will result in a loss of
precision. The best technique involves a thorough understanding of the underlying physical process
and care in selecting number representations.
5.1.3.3
Division
Binary division is the inverse of multiplication. Multiplication consists of a series of shift and add
operations, while division can be broken down into a series of subtracts and shifts. The following
example illustrates this process:
Given an 8-bit accumulator, suppose the problem is to divide the number 10 by 3. The process
consists of gradually shifting the divisor relative to the dividend, subtracting at each stage, and
inserting bits into the quotient if the subraction was successful.
5-5
1. First line up the lSB of the divisor with the MSB of the dividend.
00001010
-00011000
11110010
2. Since the result is negative (the subtraction was unsuccessful), throwaway the result, shift
the dividend, and try again.
00010100
-00011000
11111000
3. The result is still negative. Throwaway the result, shift, and try again.
00101000
-00011000
00010000
4. The answer is now positive. Shift the result and add one to set up the fourth and final
subtraction.
I
00100001
-00011000
00001001
5. The answer is again positive. Shift the result and add one. The most significant four bits
represent the remainder, while the least significant four bits represent the quotient.
00010011
\
"---- Quotient = 0011
.....--Remainder
= 0001
The TMS32010 does not have an explicit divide instruction. However it is possible to implement an
efficient flexible divide capability using the conditional subtract instruction, SUBC. The only
restriction for the use of this instruction is that both operands be positive. It is also very important
that the programmer understand the characteristics of his potential operands, such as whether the
quotient can be represented as a fraction and the accuracy to which the quotient is to be computed.
Each of these considerations can affect how the SUBC is used.
The examples below illustrate two different situations.
DIV1
CASE 1 - NUMERATOR < DENOMINATOR
TITLE:
Division Routine I
NAME:
DIV1
OBJECTIVE:
To divide two binary two's complement numbers of any sign where the
numerator is less than the denominator
5-6
DIV1
ALGORITHM: ((((((A - B)*2) + 1) - B)*2) + 1) - B ... = C
if,A-B> =0,(((A-B)*2)+1)-B> =0 ...
where A
CALLING
SEQUENCE:
=denominator, B = numerator, C =quotient
CALL DIV1
ENTRY
CONDITIONS: Numerator < Denominator
EXIT
CONDITIONS: Quotient stored in data memory location labe"ed QUOT
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
22 words, excluding macros
DATA
MEMORY
REQUIRED:
None
EXECUTION
TIME:
61-64 machine cycles
4 words
FLOWCHART: DIV1
I
SUBTRACT DENOMINATOR ...._ _ _ __
CONDITIONALLY
CALCULATE SIGN
OF QUOTIENT
NO
COUNT =
COUNT -1
MAKE NUMERATOR AND
DENOMINATOR POSITIVE
ALIGN NUMERATOR
NO
FOR DIVISION
INITIALIZE
LOOP COUNTER
FOR 15 CYCLES
NEGATE
QUOTIENT
RETURN
FIGURE 5-1 - DIVISION ROUTINE I FLOWCHART
5-7
SOURCE:
*
DIV1
LARP
LT
MPY
PAC
SACH
LAC
ABS
SACL
ZALH
ABS
LARK
*
KPDVNG
*
*
*
DONE
I
0
NUMERA
DENOM
Get sign of quotient
TEMSGN
DENOM
Save sign of quotient
DENOM
NUMERA
Make denominator positive
Align numerator
Make numerator positive
0,14
SUBC
BANZ
DENOM
KPDVNG
1S-cycle divide loop
SACL
LAC
BGEZ
QUaT
TEMSGN
DONE
Done if sign positive
ZAC
SUB
SACL
QUaT
QUaT
Negate quotient if negative
RET
EXAMPLE:
CALL DIV1
BEFORE INSTRUCTION
AFTER INSTRUCTION
NUMERA
21
NUMERA
21
DENOM
42
DENOM
42
QUaT
o
QUOT
.5
(0.1 0 0)
DIV2
CASE 2 - SPECIFY ACCURACY OF QUOTIENT
TITLE:
Division Routine II
NAME:
DIV2
OBJECTIVE:
To divide two binary two's complement numbers of any sign, specifying the
fractional accuracy of the quotient
ALGORITHM: ((((((A - B)*2) + 1) - B)*2)
5-8
+ 1) -
Boo.
=C
DIV2
if A - B> = 0, (( (A - B )*2)
+ 1) -
B > = 0, ...
where A = numerator, B = denominator, C = quotient
CALLING
SEQUENCE:
CALL DIV2
ENTRY
CONDITIONS: FRAC specifies accuracy of quotient
EXIT
CONDITIONS: Quotient stored in data memory location labelled QUOT
PROGRAM
MEMORY
REQUIRED:
24 words, excluding macros
DATA
MEMORY
REQUIRED:
STACK
REQUIRED:
None
EXECUTION
TIME:
67 - 70
FLOWCHART:
5 words
+
3*FRAC clocks
DIV2
SUBTRACT
CALL DIV2
DENOMINATOR
NO
CONDITIONALL Y
CALCULATE SIGN
OF QUOTIENT
COUNT =
MAKE NUMERATOR
COUNT -1
AND DENOMINATOR
POSITIVE
INITIALIZE
NO
LOOP COUNTER
(15
+ ACCURACY),
LOAD
NUMERATOR
NEGATE
QUOTIENT
RETURN
FIGURE 5-2 - DIVISION ROUTINE II FLOWCHART
5-9
SOURCE:
*
DIV2
*
KPDVNG
*
*
I
*
DONE
LARP
LT
MPY
PAC
SACH
LAC
ASS
SACL
LACK
ADD
SACL
LAC
ASS
LAR
0
NUMERA
DENOM
Get sign of quotient
TEMSGN
DENOM
Save sign of quotient
DENOM
15
FRAC
FRAC
NUMERA
Make denominator positive
Compute loop count
Align numerator
Make numerator positive
O,FRAC
SUBC
SANZ
DENOM
KPDVNG
16 + FRAC cycle divide loop
SACL
LAC
BGEZ
QUOT
TEMSGN
DONE
Done if sign positive
ZAC
SUB
SACL
QUOT
QUOT
Negate quotient if negative
RET
EXAMPLE:
CALL DIV2
AFTER INSTRUCTION
BEFORE INSTRUCTION
NUMERA
11
NUMERA
11
DENOM
8
DENOM
8
FRAC
3
FRAC
3
QUOT
17
QUOT
1.375
(1.0 1 1)
5-10
5.1.4
Subroutines
When a subroutine call is made using the CAll or CAlA instruction, the PC + 1 (return address)
is saved on the top of the stack. At the end of the subroutine, a RET instruction is executed which
updates the PC with the value saved on the stack. The program will then resume execution at the
instruction following the subroutine call.
There are two occasions in which a level of stack must be reserved for the machine's use. First, the
TBlR and TBlW instructions use one level of stack. Second, when interrupts are enabled, the PC
is saved on the stack during the interrupt routine. If a system is designed to use both interrupts and
a TBlR or TBlW instruction, only two levels of stack are available for nesting subroutine calls.
NOTE
If the hardware emulator will be used for system development, the level of stack which is
reserved for TBlR and TBlW will be used by the emulator to store a return address
whenever the program execution is suspended by the emulator. Therefore, if neither the
TBlR or TBlW instruction is used, one level of stack must still be reserved for use by the
emulator.
Subroutine calls can be nested deeper than two levels if the return address is removed from the
stack and saved in data memory. The POP instruction moves the top of stack (TOS) into the
accumulator and pops the stack up one level. The return address can then be stored in data memory
until the end of the subroutine when it is put back into the accumulator. The PUSH instruction will
push the stack down one level and then move the accumulator onto the TOS. Therefore, when the
RET instruction is executed, the PC is updated with the return address. This procedure will allow a
second subroutine to be called inside the first routine without using another level of stack.
The POP and PUSH instructions can also be used to pass arguments to a subroutine. DATA
directives following the subroutine call create a list of constants and/or variables to be passed to the
subroutine. After the subroutine is called, the TOS points to the list of arguments following the CAll
instruction. By moving the argument pointer from the TOS into the accumulator, the list of
arguments can be read into data memory using the TBlR instruction. Between each TBlR
instruction, the accumulator must be incremented by one to point to the next argument in the list. To
create the return address, the argument pointer is incremented past the last element in the argument
list. The PUSH instruction moves the return address onto the TOS, and the RET instruction updates
the PC.
The following example illustrates a call which passes two arguments to a subroutine.
CALL
DATA
DATA
CBlTS
VALUE
>OFFF
**********************************************************
*
Clear Bits
*
*
*
*
*
*
This subroutine clears the bits of a data word designated by a mask. The bits set to one in the mask
indicate the bits in the data word to be cleared. All
other bits remain unchanged. Two arguments are passed
to this subroutine:
*
*
*
*
*
5-11
1st argument = address of data word
*
*
2nd argument = mask
*
*
*
*
CBITS
*
* Calling sequence: CALL
1st argument
DATA
*
*
2nd argument
DATA
*
*
**********************************************************
CBITS SAR
POP
TBLR
LAR
ADD
TBLR
ADD
PUSH
XRl
ARO,XRl
ONE
XRl
ONE
LARP
LAC
XOR
AND
SACL
XRl
MINUS
LAR
RET
I 5.1.5
ARO,XRO
Save ARO in temporary location
Hold return address
1st argument = pointer to data
Put 1st argument into ARO
2nd argument = mask
Put return address on TOS
°
*
*
ARO,XRO
Load mask into accumulator
Invert mask
Clear bits
Restore ARO
Computed GO TOs
The CALA instruction executes a subroutine call based on the address contained in the
accumulator. This instruction can be used to perform a computed GO TO. The address of the
subroutine can be computed from a data value to determine which one of several routines will be
executed. The return at the end of each of these routines will cause program execution to resume
with the instruction following the CALA command. It should be noted that the CALA instruction
will use a level of stack, because it is an indirect subroutine call and not just an indirect branch.
The example below illustrates how to compute a call to one of several routines. The subroutines are
defined first, and then a table of branches to each subroutine is created. The main part of the
program inputs a data value of 0, 1, or 2. The appropriate address in the table is calculated in the
accumulator. An indirect subroutine call causes the proper branch in the table to be executed.
5-12
SUBI
IN
RET
DATl,PAO
SUB2
IN
RET
DATI ,PAl
SUB3
IN
RET
DATl,PA2
TBLI
B
B
B
SUBI
SUB2
SUB3
LT
HPYK
PAC
IN
LT
ONE
TBLI
Get address of table
VALUE,PA4
VALUE
Input data from PA4
MPYK
APAC
CAL A
LAC
5.2
2
Calculate offset
DATI
Go to designated subroutine
Return here after subroutine
ADDRESSING AND LOOP CONTROL WITH AUXILIARY REGISTERS
There are two auxiliary registers on the TMS3201 O. The auxiliary registers can be used either as loop
counters or as pointers for indirect addressing.
5.2.1
Auxiliary Register Indirect Addressing
In the indirect addressing mode, the auxiliary register pointer (ARP) is used to determine which
auxiliary register is selected. The LARP instruction sets the ARP equal to the value of the immediate
operand. The value of the ARP can also be changed in the indirect addressing mode; the ARP is
updated after the instruction has been executed.
The contents of the auxiliary register are interpreted as a data memory address when the indirect
addressing mode is used. A sequential list of data can easily be accessed in the indirect mode by
using the autoincrement or autodecrement feature of the auxiliary registers. If the auxiliary register
contains a data memory address, the counter can be used to increment through the entire address
space. The auxiliary register should not be used as a general purpose incrementer, because only the
lower nine bits of the register actually count. A special instruction, MAR, allows the auxiliary
register which is selected by the ARP to be incremented or decremented without implementing any
other operation in parallel.
There are three instructions (LARK, LAR, SAR) which either load or store a value into an auxiliary
register, independent of the value of the ARP. The first operand in each of these instructions
determines which auxiliary register is to be either loaded or stored. This operand does not affect the
value of the ARP for subsequent instructions.
The example below illustrates using an auxiliary register in the indirect addressing mode to input
data into a block of memory.
LOOP
5.2.2
LARK
ARO,DATBLK
LARP
LACK
°8
IN
SUB
*+,PAO
ONE
BNZ
LOOP
Initialize ARO as a pointer to
DATBLK (an area of 8 words in
data memory)
Select ARO
Initialize accumulator as a counter
Input data
Decrement counter (ONE contains
value 1)
Repeat until count=O
Loop Counter
An auxiliary register can also be used as a loop counter. The BANZ instruction will test and then
decrement the auxiliary register selected by the ARP. Because the test for zero occurs before the
auxiliary register is decremented, the value loaded into the auxiliary register must be one less than
the number of times the loop should be executed. The maximum number of loops which can be
counted is 512, because only nine bits of each auxiliary register are implemented as counters.
5-13
The example below inputs data and calculates the sum while the auxiliary register is used to count
the number of loops. The accumulator will contain the result.
LOOP
5.2.3
LARK
LARP
ZAC
ARO,3
0
Initialize ARO as a counter
Select ARO
Clear accumulator
IN
ADD
BANZ
DATAl,PA2
DATAl
LOOP
Input data value
Add data to accumulator
Repeat loop four times
Combination of Operational Modes
Both indirect addressing and loop counting can be performed at the same time to implement loops
efficiently. If the data block is defined to start at location 0 in data memory, the same auxiliary which
is counting the number of loops can also be the pointer for indirect addressing.
The example below illustrates using the same auxiliary register as both a counter and a pointer. Data
locations 0 through 7 are loaded with input data.
I
LOOP
LARK
IN
BANZ
ARO,7
*,PAO
LOOP
ARO points to end of data block
Input data
Repeat loop 8 times
The data block does not have to start at zero if one auxiliary register is used for counting and the
other auxiliary register is used as a pointer. The following example iIIu,strates how both auxiliary
registers can be used at once.
LOOP
5.3
LARK
LARK
ARO,7
ARl,DATBLK
ZAC
LARP
ADD
Initialize ARO as a counter
ARI points to start of DATBLK,
data memory area
1
*+,ARO
BANZ
LOOP
Point to ARI
Calculate sum of data in block;
point to ARO
Repeat loop 8 times
MULTIPLICATION AND CONVOLUTION
The hardware multiplier will peform a 16 X 16-bit multiply and produce a 32-bit result. This section
will discuss the features of the multiplier and give examples which illustrate how to efficiently use
the multiply instructions.
5.3.1
Pipelined Multiplications
A single multiply operation consists of three steps on the TMS32010. First, one of the operands is
loaded into the T register from data memory using the LT instruction. The second step is performed
by specifying the second operand using either the MPY or MPYK instruction. MPY obtains the
second operand from data memory, and MPYK uses an immediate operand as the other operand to
be mUltiplied. The third step moves the output from the (product) P register to the accumulator by
using one of three instructions, PAC, APAC, or SPAC. The PAC instruction loads the accumulator
5-14
with the value from the P register; the APAC instruction adds the product register to the
accumulator; and the SPAC instruction subtracts the P register from the accumulator. Since each
of the steps is a one-clock cycle, a single multiply-accumulate operation takes 600 ns.
If several multiplies are to be performed consecutively, the first and third steps of the multiplication
process can be done in parallel. This method reduces the time of a multiply-accumulate operation to
400 ns. Multiplication can be pipelined by using the LTA instruction. This instruction loads the T
register with the first operand for the next multiplication and adds the P register to the accumulator
for the current multiplication.
The example below performs a pipelined multiplication.
**********************************************************
*
*
The equation to be calculated is:
t = Aw + Bx + Cy + Dz
*
*
**********************************************************
ZAC
LT
MPY
LTA
MPY
LTA
MPY
LTA
MPY
APAC
SACH
SACL
W
A
X
ACC = Aw
B
Y
ACC = Aw+Bx
I
C
Z
ACC = Aw+Bx+Cy
D
ACC = Aw+Bx+Cy+Dz
Tl
T2
Store results
5.3.2 Moving Data
When implementing a digital filter, the variables in the equation represent the inputs and outputs at
discrete times. Typically this type of data structure is implemented as a shift register where the data
at time t is shifted to the position previously occupied by the data at time t-l. If consecutive
addresses in data memory correspond to consecutive time increments, then shifts can be
accomplished simply by moving the data item at location d to that corresponding to d + 1. The
DMOV command allows a data word to be written into the next higher memory location in a single
cycle without affecting the accumulator. Therefore, if the variables are placed in consecutive
locations, a DMOV command can be used to move each of the variables before the next calculation
is peformed.
The data move operation is combined with the LTA instruction to create the LTD instruction. This
instruction performs three operations in parallel. The operand of the instruction is loaded into the T
register; the operand is also written into the next higher memory location; and the P register is
added to the accumulator. When using the LTD instruction, the order of the multiply and
accumulate operations becomes important because the data is being moved while the calculation is
being performed. The oldest input variable must be multiplied by its constant and loaded into the
accumulator first. Then the input, which is one time-unit delay less, is multiplied and accumulated.
This process is repeated until the entire equation has been computed.
The following example illustrates the input variables being moved in memory as the results are
calculated :
5-15
**********************************************************
*
The following equation is used to implement a filter:
*
*
y(n)=[Ax(n-1)+Bx(n-2)+cx(n-3)+Dx(n-4)1 * 2**-16
*
****************************************** ***************
START IN
ZAC
LT
MPY
LTD
MPY
LTD
MPY
LTD
MPY
APAC
SACH
OUT
B
XI,PAO
Input sample
X4
D
X3
C
X2
B
Xl
A
x(n-4)
ACC=Dx4; x(n-4)=x(n-3)
ACC=Dx4+Cx3; x(n-3)=x(n-2)
ACC=Dx4+Cx3+Bx2; x(n-2)=x(n-l)
ACC=Dx4+Cx3+Bx2+Ax1
Y
Y,PAI
START
Output results
5.3.3 Product Register
The product register stores the results of a multiplication until another multiplication is peformed. A
user may want to use the multiplier during the interrupt routine, but the product register must be
restored with the value it contained before the interrupt occurred. It is easy to save the product
register in data memory, but it is very difficult to restore the product register with the value that was
saved in memory. A hardware feature has been built into the interrupt logic to prevent an interrupt
from occurring immediately after a multiply instruction (MPY or MPYK). If the contents of the
product register are always transferred into the accumulator on the instruction following the
multiply, the product register could be changed during the interrupt routine without having to be
restored before returning from the interrupt. Therefore, a PAC, APAC, SPAC, LTA, or LTD should
always follow a MPY or MPYK instruction. This rule should be followed whenever the multiplier is
being used during the interrupt routine.
I
The value of the product register can be restored if the contents are saved in memory, but it is a very
time-consuming process. If the magnitude of the value saved in memory is greater than fifteen bits,
it must be factored into two smaller numbers in order to restore the product register.
5.4
MEMORY CONSIDERATIONS OF HARVARD ARCHITECTURE
The memory organization on the TMS32010 is referred to as a Harvard architecture. This means
that the program memory is separate from the data memory. This type of architecture allows the
next instruction fetch to occur while the current instruction is fetching data and executing the
operation. While the concept of a Harvard architecture increases the speed of the machine, there
are disadvantages in having the program memory totally separate from data memory. The
instruction set, therefore, includes instructions which transfer a word between data memory and
program memory. The following sections illustrate how to make efficient use of the ablility to
exchange data between memories.
5.4.1
Moving Constants into Data Memory
Most signal processors have a separate memory space for storing constants. By allowing communication between data and program memory, the TMS32010 is able to incorporate a constant
memory capability with its program memory. This method allows a more efficient use of memory
space. The portion of memory not used for storing constants is available for use as program space.
5-16
There are five immediate instructions in the instruction set which provide an efficient way to
execute operations using constants. Two immediate instructions, lARP and lDPK, modify the
program context.
LARP changes the auxiliary register pointer, and lDPK changes the data page pointer. Three other
immediate instructions, lACK, lARK, and MPYK, allow constants to be used in calculations.
LACK and lARK both require an unsigned operand with a magnitude no greater than eight bits.
The MPYK instruction allows a 13-bit signed number as an operand.
A 16-bit data value can be moved from program memory to data memory using the TB lR
instruction. TBlR requires that the program memory address (the source) be in the accumulator,
while the data memory address (the destination) is obtained from the operand of the instruction.
The TBlR instruction is commonly used to look up values in a table in program memory. The
address of the value in the table is computed in the accumulator before executing the instruction.
TBlR then moves the value into data memory. TBlR is a three-cycle instruction and, therefore,
takes longer than an immediate instruction. However, it has more flexibility since it operates on
16-bit constants.
The example below illustrates bringing the cosine value of a variable into data memory.
*
*
First, a table containing the cosine values is created in
program memory.
COSINE
START
I
DATA
IN
LACK
X,PAO
COSINE
ADD
X
TBLR
COSX
Load table address
Calculate program memory address
Move value into data memory
Note: If the address of COSINE is larger than 255, the address can be loaded into the accumulator by loading the T register with a
one and then "multplying by the constant COSINE.
5.4.2
Data Memory Expansion
Often it is necessary to expand data storage capability by using external memory. If the storage
requirements are small, additional memory can be added as a RAM extension of the program
memory address space. This technique is very efficient in terms of additional hardware
requirements, but it has two drawbacks. It requires that the combination of the memory required to
store the program and accomodate data be limited to 4096 words. It also tends to limit system
throughput, since access to data in program memory is relatively slow. The minimum memory
access time using this technique is four clocks (800 ns), but six clocks (1200 ns) is a more likely
average.
A system requIring larger memories or faster data access can be implemented by treating the
expanded data memory as an liD device. Since the TMS32010 lacks the capability to address a
large liD address space (it is limited to eight devices), this technique also requires the use of an
external address register. This register can be implemented as a counter to allow efficient access to
contiguous data buffers. See Section 6.1.3 on liD design techniques for more details.
5-17
5.4.3
Program Memory Expansion
Using the Mel MP pin on the TMS32010, the applications engineer can choose between two
distinct techniques for structuring his program memory address space. (See Figure 5-3.) In the
microcomputer mode, the internal masked ROM is active and consumes the low 1536 words of the
address space. The remaining 2560 words can be implemented using external memory. If the
microprocessor mode is selected, the entire 4096 word address space is assumed to exist external to
the chip.
MC MODE
TMS32010
(1.5K PM)
FIGURE 5-3A - USE OF INTERNAL PROGRAM MEMORY
I
DATA LINES
,I
..-
~
16
TMS32010
ADDRESS LINES
I
MC/MP
,'2
..-
MEN
WE
4K X 16
STATIC RAM
ANDIOR PROM
OUTPUT
ENABLE
(ONLY FOR
-
CHIP
WR ITE
SELECT
EN ABLE
RAM)
FIGURE 5-38 - USE OF EXTERNAL PROGRAM MEMORY
FIGURE 5-3 - TECHNIQUES FOR EXPANDING PROGRAM MEMORY
In the microcomputer mode, only the upper 2.SK words of external program memory are used. In
the microprocessor mode, all4K words of external memory are used. With some types of memory
elements, additional chip-select logic may be necessary.
External program memory may utilize either RAM or ROM. In either case, system operation at the
fullS-MHz clock rate requires that the memory exhibit an access time of less than 100 ns. If RAM is
used, it may be loaded either via the TMS32010 itself using a boot ROM, or via a dual RAM port
from an independent controller.
5-18
INPUT/OUTPUT DESIGN TECHNIQUES
I
I
6.
INPUT/OUTPUT DESIGN TECHNIQUES
An interrupt-driven sampled data interface is the most common for signal processing applications,
but other types of peripherals can also be used. This section illustrates several examples and
discusses some of the hardware and software issues which should be considered when designing
an I/O system for the TMS3201 O.
6.1
PERIPHERAL DEVICE TYPES
Using a three-bit port address, the TMS3201 0 is capable of accessing eight different input devices
and eight different output devices. The port number is placed on the external address lines during
the second cycle of the instruction. The address lines can be decoded to select one of several
devices attached to the data bus or to activate a single control line. Three classes of peripherals are
discussed below.
6.1.1
Registers
A register can be used for several different functions. The most simplistic interface uses a 16-bit
dual port transceiver. Such a register allows two-way communication between the TMS32010 and
another processor. Handshaking between the processors can be implemented by using interrupts
on the TMS3201 O. In Figure 6-1, the acknowledge line from the other processor is connected to the
BID pin in order to synchronize the TMS32010.
ADDRESS BUS
P
R
0
C
R
T
E
M
G
DATA BUS
E
,
S
16
I
S
-
• • •u
t
~
-
3
--
INTERRUPT
I
,I
74LS138
0
R
I
S
T
DATA BUS
I
,
16
~
S
3
2
0
E
1
R
0
- BIo
~
ACKNOWLEDGE
-
FIGURE 6-1 - COMMUNICATION BETWEEN PROCESSORS
In a more complicated configuration, a shift register can be used to convert a serial data stream into
parallel data to be compatible with the liD instructions. An analog device which can be interfaced
to this processor is a codec. It is simply an AID converter and 01 A converter which is designed to
operate in a telecommunications environment. This serial device produces eight-bit logarithmicallyweighted digital data. Consequently, a codec interface must include a mechanism for serial to
parallel conversion and a facility for code conversion. A shift register can provide the parallel input
to the TMS3201 O. The code converter for AID data can be implemented either in hardware using a
256 X 16-bit ROM or in software.
6-1
Another example of a register-based liD system is a very simple AID channel where the output of
an AID converter is buffered using a single parallel register. This requires that the AID system be
serviced before the next data sample overwrites the previous sample stored in the register.
Unfortunately, a routine which only services a single data word for every interrupt can be very time
consuming. The service overhead time can be reduced by multiword buffering (see Section 6.1 .2
for discussion of FIFOs and interrupts).
6.1.2
FIFOs
The use of FIFOs instead of registers offers three definite advantages as follows:
1) Single address access to multiple data words,
2) Reduction of 1/0 overhead (since several words can be accessed for each interrupt),
3) Preservation of temporary information in data stream.
Figure 6-2 illustrates the use of a FIFO in a typical analog subsystem.
ANALOG
ANALOG
SIGNAL
.a
ANTI-ALIASING
DIGITAL
DATA
DATA
AID CONVERTER
FILTER
..
I
CLOCK
74LS222
INPUT
FIFO
SAMPLE READY
I
DATA
BUS 10016
~
OU TPUT
ENA BLE
~
BIO
TMS32010
DEN
~
FIGURE 6-2 - TYPICAL ANALOG SYSTEM INTERFACE
6.1.3
Extended Memory Interface
The peripheral which requires the most hardware to implement is a large memory. Because the
address lines only access locations 0-7 during an 1/0 operation an external address counter must be
used to provide an address for the memory. It is also advisable to provide a buffer between the data
bus of the TMS3201 0 and that of the memory itself. Although this buffer is probably not necessary
for high-speed static memories, it is required for slower devices and large arrays where the drive
capacity of the TMS3201 0 may be marginal.
Figure 6-3 gives an example of one way to extend data memory by using the IN and OUT
instructions. The design consists of 16K words of static RAM, addressed by the lower 14 bits of a
16-bit counter. The location to address in this RAM is loaded into the counter by doing an OUT
instruction to port O. This loads the data bus into the counters. The appropriate data memory
location is addressed by the lower 14 bits of the data. Bit 15 (MSB) of the data is loaded into the
counters to determine whether to count up or down through data memory. Memory can then be
read from or written to sequentially by doing an IN or OUT instruction to port 1. The MSB in the
counters determines whether the memory address should be incremented (MSB = 0) or
decremented (MSB = 1) after a read or write of data memory. Memory will continue to be
addressed sequentially until new data is loaded into the counters.
6-2
------------------------------------~:~LOAD
16 X 16 DATA RAM
ADDRESS
COUNTER
(72LS 193)
(4 units)
....,.......-IA 1 3-AO
14
(lMS1420)
(16 units)
(16Kx1 70-ns SRAM)
A15 (MSB) __
CS
WE
U
0
-«(}
L.--1=~
~l
.'-0--+-----J
: -I
WRITE RAM
...--.
READ RAM
--
-
- .r
• ~I
COUNT UP
COUNT DOWN
," 16
j)
PA
DECODER
(74LS138)
.
~
t
.
jl
J:l
16
PA
DECODER
(72LS138)
u
,I
! .-
3
WE
00-015
~3
.~
A2-AO
DEN
D15-DO
TMS32010
A 11-A3
3
DATA BUS
16
I--........I------------~. .~:........------. ADDRESS BUS....
-9
r2
__I
EXTERNAL
READ ONLY
PROGRAM
MEMORY
TBP28S166)
(2/4 units)
I
A 11-AO
MEN ~------------------------------~~ CS
~------------------~
~-------------
FIGURE 6-3 - TMS32010 EXTENDED MEMORY INTERFACE
Dynamic memories can also be used. However, those devices may impose software constraints on
the system designer. For example, memory cycle times may not allow consecutive IN/OUT/IN
instruction sequences. Memory refresh represents another problem. Since this processor has no
capability to enter a "wait" state, memory refresh must be generated with external hardware.
6.2
INTERRUPTS
An interrupt routine allows the current process to be suspended while an I/O device is being
serviced. The processor's execution may be suspended on a high-priority basis by using the INTpin.
Otherwise, a lower priority interrupt can be serviced by using a software polling technique.
6.2.1
Software Methods
The BIOZ instruction can be used to poll (or test) the BIO pin to see if a device needs to be serviced.
This method allows for a critical loop or set of instructions to be executed without a variation in
execution time. Because the test for interrupts occurs at defined points in the program, context
saves requirements are minimal.
The BIO pin can be used to monitor the status of a peripheral. If the FIFO full status line is
connected to the BIO pin, the FIFO is serviced only when the FIFO is full. In the following example,
the FIFO contains 16 data words. The BIO pin is tested after each time-critical function has been
executed.
6-3
BIOZ
CALL
SKIP
SERVE
SKIP
The subroutine does not have to save the registers or the status, because a new procedure will be
executed after the device is serviced.
SERVE LACK
LACK
LOOP LARP
IN
BANZ
RET
ARO ,15
ARl,TABLE
1
PAO,*+,ARO
LOOP
The FIFO must be serviced before another word is input or data may be lost. This fact determines
the frequency at which the polling must take place.
6.2.2
Hardware Methods
The INT pin causes execution to be suspended at any point in the program except after a multiply
instruction (see Section 4.1.3.3). The hardware interrupt can be masked at critical points in the
program with the DINT instruction. If an interrupt occurs while the INTM (disabled interrupt mask)
equals one, the interrupt will not be serviced until the interrupts are enabled again. If an interrupt is
pending when an enable interrupt operation occurs, the interrupt is serviced after the execution of
the instruction following the EINT command.
I
When an interrupt is serviced, the INTF (interrupt flag) is cleared, INTM is set to one, the current PC
is pushed on the TOS, and the PC is set to 2. The user must save the context of the machine before
servicing the peripheral. The context should be restored and the interrupts enabled prior to
returning from the interrupt routine. The following paragraphs illustrate a technique for
implementing an interrupt-driven analog input channel. It also shows the impact of multiple-level
data buffering on system I/O overhead.
Generally, the class of analog systems which can be reasonably supported by the TMS32010 will
have information bandwidths of less than 20 kH~. The desired\ sample rate can be generated by
dividing the 5 MHz CLKOUT signal from the TMS32010. It is advisable to provide at least a one-level
data buffer to insure the integrity of the data which is read by the processor. If an a-kHz sample rate
is used (for example), the system must then respond to an analog interrupt every 125 ms. The I/O
overhead incurred by this arrangement can be computed by determining the number of clock times
the TMS3201 0 will spend in the interrupt routine servicing each sample, and dividing by 625. For
example, a typical interrupt routine might look like the following:
INT
6-4
SST
SACL
SACH
IN
LAC
ADD
SACL
LACK
SUB
BGZ
STATUS
ACCL
ACCH
SAMP,ADC
COUNT
ONE
COUNT
LIMIT
COUNT
OK
Save status
Save accumulator low
Save accumulator high
Read from ADC
Update sample counter
Check whether LIMIT clocks
received
DONE
OK
LACK
SACL
ZALH
ADDS
LST
EINT
RET
1
FLAG
ACCH
ACCL
STATUS
YES ===> Set flag
Restore accumulator high
Restore accumulator low
Restore status
Enable subsequent interrupts
The overhead required to service this system is 18/625 = 2.9 percent. This overhead burden can be
reduced by using a FIFO to buffer the data. In this case, the TMS3201 0 need only be interrupted
when the buffer has filled. If a 16-level FIFO is used in our example above, this interrupt will occur
every 2 ms, and the overhead burden will be reduced to about 0.5 percent.
If two different kinds of devices are being serviced by the same interrupt routine, the BIO pin can be
used to determine which device needs to be serviced.
•
6-5
I
6-6
MACRO LANGUAGE INSTRUCTIONS
•
I
7.
MACRO LANGUAGE EXTENSIONS
The basic instruction set of the TMS3201 0 has been extended via the XDS/320 Macro Assembler to
facilitate coding of commonly used assembly language constructs. In this section, a set of macros
designed to ease assembly language coding is described. Some macros call routines from the set of
utility routines described in Section 7.5.
7.1
CONVENTIONS USED IN MACRO DESCRIPTIONS
In the macro descriptions, the following conventions are used:
A
A previously definedt memory label
B
Another previously definedt label
A:A
+
1
Like A, except refers to a double word
B:B
+
1
Like B, except refers to a double word
TMP
A temporary location (previously defined)
AR
Auxiliary register 1 or auxiliary registor 0
@AR
Data RAM location pointed to by the selected auxiliary register
@AR: @AR
@AR -
+
1
1: @AR
Double word, starting at location pointed to by the selected auxiliary
register
Double word, starting at one before the location pointed to by the
selected auxiliary register
AR1
Auxiliary register 1
@AR1
Data RAM location pointed to by AR 1
ARO
Auxiliary register 0
@ARO
Data RAM location pointed to by ARO
AC
Accumulator
AClow
Low-order 16 bits of the accumulator
AC high
High-order 16 bits of the accumulator
@AC
Data RAM location pointed to by the accumulator
p
P register
T
T register
ARP
Auxiliary register pointer
•
7-1
*
Indirect operand
* +
Indirect reference and increment
*
Indirect reference and decrement
[fl
Field f optional (i.e., may be replaced by a null operand)
C
Constant. (It may be written as C{n< C< m} to indicate a range limit
between nand m. C1 and C2 will be used as constants when two are
required in a description.
t Some macros generate different code sequences for constant operands and memory operands. Memory operands can be confused with
constants unless the memory labels (operand names) have been defined to the assembler prior to their use in a macro call. This limitation
corresponds to the requirement in some higher-level languages like PASCAL that variables be declared prior to their use in expressions.
7.2
MACRO SET SUMMARY
Table 7-1 lists alphabetically all the macros described in Section 7-3.
TABLE 7-1 - MACRO INDEX
MNEMONIC
ACTAR
ADAR
ADDX
ARTAC
BIC
BIS
BIT
CMP
CMPX
DEC
DECX
INC
INCX
LACARY
I
LASH
LASX
LAXARY
LCAC
LCACAR
LCAR
LCAX
LCAXAR
LCP
LCPAC
7-2
DESCRIPTION
Move Accumulator to Auxiliary Register
Add Variable to Auxiliary Register
Double-Word Add
Move Auxiliary Register to Accumulator
Clear Bits in Data Word
Set Bits in Data Word
Test Bits in Data Word
Compare Two Words
Compare Two Double Words
Decrement Word
Double-Word Decrement
Increment Word
Double-Word Increment
Load Accumulator from Address in
Accumulator
Arithmetic Left Shift
Double-Word Arithmetic Left Shift
Load Double Word into Accumulator from
Address in Accumulator
Load Constant into Accumulator
Load Constant to Accumulator from Program
Address in Accumulator
Load Constant into Auxiliary Register
Load Double-Word Constant into Accumulator
Load Double-Word Constant to Accumulator
from Program Memory
Load Constant into P Register
Load Constant into P Register and
Accumulator
PAGE
7-7
7-9
7-11
7-14
7-16
7-18
7-20
7-22
7-24
7-26
7-28
7-31
7-33
7-36
7-38
7-40
7-42
7-44
7-48
7-50
7-53
7-55
7-57
7-59
TABLE 7-1 - MACRO INDEX (CONTINUED)
MNEMONIC
LDAX
LTK
MAX
MAXX
MIN
MINX
MOV
MOVCON
MOVDAT
MOVE
MOVROM
MOVX
NEG
NEGX
NOT
RASH
RASX
REPCON
RIPPLE
RLSH
RLSX
SACX
SAT
SBAR
SBIC
SBIS
SBIT
STOX
SUBX
TST
TSTX
XTOS
DESCRIPTION
Load Double Word
Load Constant into T Register
Select Maximum of Two Words
Select Maximum of Two Double Words
Select Minimum of Two Words
Select Minimum of Two Double Words
Move Word in Data Memory
Move Constants to Data Memory
Move Words to Data Memory
Move Data Array
Move Words to Program Memory
Move Double Word
Arithmetic Negation
Double-Word Arithmetic Negation
Boolean Not
Arithmetic Right Shift
Double-Word Arithmetic Right Shift
Move One-Word Constant into Array
Ripple Data Array One Position
Right Logical Shift
Double-Word Logical Right Shift
Store Double Word
Saturate Data Word between Upper and Lower
Bounds
Subtract Variable from Auxiliary Register
Clear Single Bit in Data Word
Set Single Bit in Data Word
Test Single Bit in Data Word
Convert Single Word to Double Word
Double-Word Subtract
Test Word
Test Double Word
Convert Double Word to Single Word
PAGE
7-61
7-64
7-66
7-68
7-70
7-72
7-74
7-76
7-80
7-85
7-90
7-95
7-98
7-100
7-103
7-105
7-107
7-109
7-111
7-115
7-117
7-119
7-122
7-126
7-129
7-131
7-133
7-135
7-137
7-140
7-142
7-145
I
Table 7-2 summarizes all the legal parameters of the macros described in Section 7-3.
7-3
TABLE 7-2 - MACRO SET SUMMARY
MACRO
INSTRUCTION
ACTAR
ADAR
ADDX
ARTAC
BIC
BIS
BIT
CMP
CMPX
DEC
DECX
INC
INCX
LACARY
LASH
LASX
I
LAXARY
LCAC
LCACAR
OPERAND
NUMBER
1
2
1
2
3
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
##
1
1
2
3
1
2
3
##
1
2
##
1
LCAR
LCAX
LCAXAR
LCP
LCPAC
LDAX
LTK
MAX
MAXX
MIN
MINX
MOV
MOVCON
MOVDAT
program data
7-4
2
1
2
1
##
1
1
1
1
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
3
0
P
T
OPERAND
SIZEt
OPERAND TYPES:t:
C
X
1
X
1
1
2
S
*
*+
*-
AC
CONSTANT RANGE
AR
X
LOWEST
X
X
X
X
X
X
- 32768
X
X
X
X
X
X
X
X
32767
X
1
1
1
1
1
1
1
1
1
2
2
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2
1
X
X
X
X
X
X
X
X
I
2
1
X
X
X
X
X
X
temporary
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
X
X
15
0
15
0
15
- 32768
0
32767
15
0
15
X
X
X
2
1
0
X
X
2
2
X
X
X
1
X
X
I
temporary
X
X
HIGHEST
I
temporary
X
X
1
X
temporary
X
X
X
1
2f
2
2
1
1
2
1
1
1
2
2
1
1
2
2
1
1
?
?
?
?
X
X
X
-32768
-2**31
32767
2**31-1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
temporary
X
X
X
X
X
X
-4096
-4096
4095
4095
-32768
32767
-32768
32767
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
TABLE 7-2 - MACRO SET SUMMARY (Concluded)
MACRO
INSTRUCTION
MOVE
data data
MOVROM
data program
MOVX
NEG
NEGX
NOT
RASH
RASX
REPCON
RIPPLE
RLSH
RLSX
SACX
SAT
SBAR
SBIC
SBIS
SBIS
SBIT
STOX
SUBX
TST
TSTX
XTOS
NOTES:
t
:!:
f
?
##
OPERAND
NUMBER
1
2
3
1
2
3
1
2
1
1
1
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
1
2
3
1
2
3
1
2
1
2
1
2
1
2
1
2
1
1
1
1
2
0
P
T
OPERAND TYPES:!:
OPERAND
SIZEt
C
?
?
X
*+
*-
X
X
AC
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
AR
X
?
?
X
X
*
S
X
X
CONSTANT RANGE
X
2
2
1
2
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
2
2
HIGHEST
-32768
32767
-32768
32767
0
15
0
-32768
15
32767
-32768
32767
X
X
X
X
X
?
X
X
?
X
-32768
32767
dummy argument
X
1
1
X
X
X
2
2
0
15
0
15
-32768
-32768
32767
32767
X
X
X
2
1
1
1
LOWEST
X
X
X
X
X
X
X
X
X
I
X
X
1
1
X
-32768
32767
temporary
0
15
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
1
X
1
1
2
2
1
2
2
1
X
X
0
15
0
15
0
15
Blank in size field means that operand is not a data (program) location, but is a field in an instruction (Le., has no word size).
C
S
Constant
Symbolic address
* , * + ,* Indirect through the selected address register (ARP)
AC
Operand is the AC (usually shown in the instruction as null or blank operand: MOV,A)
AR
An address register (ARO or AR 1 )
32-bit constant expressed as a two-word constant list: (C1,C2)
Variable length operand (length given by argument 3)
Implied operand in accumulator
7-5
7.3 MACRO DESCRIPTIONS
Each macro instruction is named, followed by a summary table. A flowchart for clarifying the macro
source then follows and specific examples of all legal forms.
The macros described in this section use a number of assembler symbols for internal purposes
during macro expansion. Most of these internal symbols and any operands the user supplies to the
macros are entered into the assembler symbol table as undefined (unless they are user-defined
already) and will be printed at the end of the assembler printed output as undefined. This is not an
error. Only undefined symbol errors flagged under assembly language statements in the program
listing are actual fatal errors. Only these errors will be tallied in the assembly error count. Undefined
symbols listed after the program are for information only.
I
7-6
ACTAR
Move Accumulator to Auxiliary Register -
Macro
TITLE:
Move Accumulator to Auxiliary Register
NAME:
ACTAR
OBJECTIVE:
Pass data word to named auxiliary register from accumulator
ALGORITHM:
(ACC) -+ temp (XRO)
(temp) -+ AR
CALLING
SEQUENCE:
ACTAR
ACTAR AR [,TEMP]
ENTRY
CONDITIONS: AR = 0,1; 0
~
TEMP
~
127
EXIT
CONDITIONS: Accumulator stored in auxiliary register;
ARP now points to auxiliary register specified
PROGRAM
MEMORY
REQUIRED:
3 words
DATA
MEMORY
REQUIRED:
1 word
STACK
REQUIRED:
None
EXECUTION
TIME:
3 cycles
FLOWCHART:
ACTAR
NO
I
ASSIGN XRO TO
TEMPORARY
SAVE ACC IN
TEMPORARY
MOVE VALUE FROM
TEMPORARY TO
AUX. REGISTER
SET ARP
7-7
ACTAR
ACTAR
SOURCE:
*MOVE AC TO AR
*
ACTAR
$MACRO A,T
ASSIGN XRO AS TEMP
$IF T.L=O
$ASG IXR0 1 TO T.S
$ENDIF
SACL :T: ,0
STORE AC TO :T:
LAR :A:, :T:
RE-LOAD :A:
LARP :A:
LOAD AR POINTER
$END
EXAMPLE 1:
0013
0001 0009 5004 11
0002 OOOA 3804"
0003 OOOB 6880
ACTAR ARO
SACL XRO,O
LAR ARO,XRO
LARP ARO
STORE AC TO XRO
RE-LOAD ARO
LOAD AR POINTER
ACTAR O,C
SACL C,O
LAR O,C
LARP 0
STORE AC TO C
RE-LOAD 0
LOAD AR POINTER
EXAMPLE 2:
0015
0001 OOOC 5000"
0002 0000 3800"
0003 OOOE 6880
7-8
ADAR
Add Variable to Auxiliary Register -
TITLE:
Add Variable to Auxiliary Register
NAME:
ADAR
OBJECTIVE:
Add data word to named auxiliary register
ALGORITHM:
(AR) + (dma) - ACC
(ACC) -AR
CALLING
SEQUENCE:
Macro
ADAR
ADAR AR, 8 [,TEMP]
ENTRY
CONDITIONS: AR
= 0,1; 0 ~ 8 ~ 127; a ~ TEMP ~ 127
EXIT
CONDITIONS: Sum of memory location and auxiliary register is stored in named auxiliary
register
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
5 - 7 words (plus LDAC$
routine)
a-
2 levels
DATA
MEMORY
REQUIRED:
2 words
EXECUTION
TIME:
5 -17 cycles
I
FLOWCHART: ADAR
NO
LET XRO BE
TEMPORARY
ADD TEMPORARY
TO ACC
SAVE ACC IN
TEMPORARY
STORE AUXILIARY
REGISTER IN
TEMPORARY
STORE TEMPORARY
IN AUXILIARY
REGISTER
YES
CALL LCAC TO
LOAD CONSTANT
INTO ACC
LOAD VARIABLE
INTO ACC
7-9
ADAR
ADAR
SOURCE:
*ADD TO AR
*
ADAR
$MACRO A,B,T
$IF T.L=O
USE XR1 AS TEMP
$ASG 'XR1' TO T.S
$ENDIF
SAR :A:, :T:
STORE :A:
$IF B.SA&SUNDF
LCAC :B:
LOAD CONST :B: INTO AC
$ELSE
LAC :B:,O
LOAD VAR :B: INTO AC
$ENDIF
ADD :T:,O
ADD TEMP :T: TO AC
SACL :T:,O
STORE :T:
LAR :A: , :T:
LOAD BACK INTO :A:
$END
EXAMPLE 1:
0007
0001
0002
0001
0002
0003
0004
0005
0006 3103 11
0007
0008
0009
OOOA
0003
7E03
0003 11
5003 11
3903 11
A,3
ADAR
SAR A,XR1
LCAC 3
V$l EQU 3
LACK V$l
ADD XR1,0
SACL XR1,0
LAR A,XR1
STORE A
LOAD CONSTANT 3 INTO AC
LOAD AC WITH V$l
ADD TEMP XR1 TO AC
STORE XR1
LOAD BACK INTO A
EXAMPLE 2:
0009
0001
0002
0003
0004
0005
I
OOOB
OOOC
0000
OOOE
OOOF
3008
2004 11
0008
5008
3808
ADAR
ARO,C,B
SAR ARO,B
LAC C,O
ADD B,O
SACL B,O
LAR ARO,B
STORE ARO
LOAD VARIABLE C INTO AC
ADD TEMP B TO AC
STORE B
LOAD BACK INTO ARO
3003 11
2005 11
0003 11
5003"
3803"
ADAR
O,D
SAR 0,XR1
LAC D,O
ADD XR1,0
SACL XR1,0
LAR 0,XR1
STORE 0
LOAD VARIABLE D INTO AC
ADD TEMP XR1 TO AC
STORE XR1
LOAD BACK INTO 0
EXAMPLE 3:
0011
0001
0002
0003
0004
0005
7-10
0010
0011
0012
0013
0014
ADDX
Double-Word Add -
ADDX
Macro
TITLE:
Double-Word Add
NAME:
ADDX
OBJECTIVE:
Add double word to accumulator
ALGORITHM:
ADDX *
- causes-+ (ACC)
ADDX * -
- causes-+ (ACC) + (@AR -1 :@AR) -+ ACe
(AR) - 2-+AR
+
ADDX *
ADDX A
CALLING
SEQUENCE:
-
+
(@AR:@AR + 1) -+ ACC
causes-+ (ACC) + (@AR:@AR + 1) -+ Ace
(AR) + 2 -+ AR
- causes-+ (ACC) + (A:A + 1) -+ ACC
ADDX {A,*,* -,* +}
ENTRY
CONDITIONS: 0 ~ A
~
127
EXIT
CONDITIONS: Accumulator contains updated value after addition; auxiliary register is
updated if necessary
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
2 words
DATA
MEMORY
REQUIRED:
None
None
EXECUTION
TIME:
2 cycles
7-11
ADDX
ADDX
FLOWCHART: ADDX
ADD @AR
AND @AR+ 1
ADD @AR
AND @AR+1
ADD @AR
AND @AR-1
ADD A AND A+ 1
SOURCE:
*ADD DOUBLE PRECISION
*
ADDX
7-12
$MACRO A
ADD
$VAR ST,SP,SM
$ASG '*+1 TO SP.S
$ASG '*_1 TO SM.S
$ASG '*1 TO ST.S
$IF A.SV=ST.SV
ADDH *+
ADD
ADDS *ADD
$ELSE
$IF A.SV=SP.SV
ADDH *+
ADD
ADDS *+
ADD
$ELSE
$IF A.SV=SM.SV
ADDS *ADD
ADD
ADDH *$ELSE
ADDH :A:
ADD
ADDS :A:+l
ADD
$ENDIF
$ENDIF
$ENDIF
$END
DOUBLE PRECISION
HIGH
LOW 1*1
HIGH
LOW 1*+1
LOW
HIGH 1*_1
:A: HIGH
:A: LOW
AR
=
AR-2
ADDX
ADDX
EXAMPLE 1:
0011
0001 0006 6007
0002 0007 6108
ADDX A
ADDH A
ADDS A+l
ADD A HIGH
ADD A LOW
ADDX *
ADDH *+
ADDS *-
ADD HIGH
ADD LOW 1*1
ADDX *ADDS *ADDH *-
ADD LOW
ADD HIGH 1*_1
ADDX *+
ADDH *+
ADDS *+
ADD HIGH
ADD LOW 1*+1
EXAMPLE 2:
0013
0001 0008 60A8
0002 0009 6198
EXAMPLE 3:
0015
0001 OOOA 6198
0002 0008 6098
EXAMPLE 4:
0017
0001 00 DC 60A8
0002 0000 61A8
I
7-13
ARTAC
Move Auxiliary Register to Accumulator -
TITLE:
Move Auxiliary Register to Accumulator
NAME:
ARTAC
OBJECTIVE:
Load data from auxiliary register into accumulator
ALGORITHM:
(AR) -+ temp
(temp) -+ ACC
CALLING
SEQUENCE:
Macro
ARTAC AR [,TEMP]
ENTRY
CONDITIONS: AR
= 0,1; 0 ~ TEMP ~ 127
EXIT
CONDITIONS: Accumulator contains same value as auxiliary register
I
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
2 words
DATA
MEMORY
REQUIRED:
1 word
None
EXECUTION
TIME:
2 cycles
FLOWCHART: ARTAC
NO
STORE AUXILIARY
REGISTER IN
TEMPORARY
LOAD TEMPORARY
INTO ACC
7-14
ASSIGN XRO AS
TEMP LOCATION
ARTAC
ARTAC
ARTAC
SOURCE:
*COpy AR TO AC
*
ARTAC
$MACRO A,T
$IF T.L=O
USE XRO AS TEMP
$ASG 'XRO' TO T.S
$ENDIF
SAR : A: , : T :
SAVE : A:
LAC :T:,O
LOAD INTO AC
$END
EXAMPLE 1:
0013
0001 0008 3004"
0002 0009 2004"
ARTAC ARO
SAR ARO,XRO
LAC XRO,O
SAVE ARO
LOAD INTO AC
ARTAC O,C
SAR O,C
LAC C,O
SAVE 0
LOAD INTO AC
EXAMPLE 2:
0014
***
0015
0001 OOOA 3000"
0002 OOOB 2000"
I
7-15
BIC
Clear Bits in Data Word -
TITLE:
Clear Bits in Data Word
NAME:
BIC
OBJECTIVE:
Clear bits in data word specified by one bit in mask
ALGORITHM:
(data) .AND .. NOT. (mask)
CALLING
SEQUENCE:
BIC mask,data
ENTRY
CONDITIONS: 0
~
BIC
Macro
data
-+
mask ~ 127; 0 ~ data ~ 127
EXIT
CONDITIONS: Data word contains initial value with specified bits cleared
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
4 words
DATA
MEMORY
REQUIRED:
1 word
None
EXECUTION
TIME:
4 cycles
FLOWCHART: BIC
(
,
BEGIN
J
,
LOAD MASK INTO
ACC
INVERT
MASK
•
,
,
AND ACC WITH
DATA
RESTORE DATA
WORD
(
END
)
SOURCE:
*BIT CLEAR - CLEAR BITS IN B WHERE A HAS ZEROS
*
BIC
7-16
$MACRO A,B
LAC :A: ,0
BIT CLEAR
LOAD :A:
BIC
BIC
XOR MINUS
AND :B:
SACL :B: ,0.
$END
INVERT MASK
AND :B:
SAVE RESULT IN :B:
EXAMPLE 1:
0.0.14
00.01
00.02
00.03
0.004
ODOA 20.08
ODOB 780.3 11
ODOC 790.1
0000 50.01
BIC
LAC
XOR
AND
SACL
B,A
B,O
MINUS
A
A,D
LOAD B
INVERT MASK
AND A
SAVE RESULT IN A
BIC
LAC
XOR
AND
SACL
D,C
D,D
MINUS
C
C'D
LOAD 0
INVERT MASK
AND C
SAVE RESULT IN C
BIC
LAC
XOR
AND
SACL
D,A
0,0
MINUS
A
A,O
LOAD 0
INVERT MASK
AND A
SAVE RESULT IN A
EXAMPLE 2:
0.0.16
0.0.01
0.00.2
000.3
0.0.0.4
DODE 20.0.1"
DDDF 780.3"
0.0.10. 7900."
0.0.11 50.0.0."
EXAMPLE 3:
00.18
000.1
0.0.0.2
0.0.0.3
0.0.0.4
0.0.12
0.013
00.14
0.0.15
20.01"
780.3"
790.1
50.01
7-17
BIS
Set Bits in Data Word -
TITLE:
Set Bits in Data Word
NAME:
BIS
OBJECTIVE:
Set bits in data word specified by one bit in mask
ALGORITHM:
(data) .OR. (mask) --. data
CALLING
SEQUENCE:
BIS mask, data
ENTRY
CONDITIONS: 0 ~ mask ~ 127; 0
~
BIS
Macro
data ~ 127
EXIT
CONDITIONS: Data word contains initial value with specified bits set
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
3 words
DATA
MEMORY
REQUIRED:
None
None
EXECUTION
TIME:
3 cycles
FLOWCHART: BIS
(
BEGIN )
~
,
,
,
LOAD ACC WITH
MASK
OR MASK WITH
DATA
RESTORE DATA WORD
TO MEMORY
(
END
J
SOURCE:
*SET BITS IN B CORRESPONDING TO ONES IN A
*
BIS
$MACRO
A,B
:A:,O
OR
:B:
LOAD :A:
SACL :B:, 0
OR WITH :B:
SAVE BACK TO :A:
$END
7-18
BIT SET
LAC
BIS
BIS
EXAMPLE 1:
0014
0001 DOOA 2008
0002 OOOB 7A01
0003 OOOC 5001
BIS
LAC
OR
SACL
B,A
B,O
A
A,O
LOAD B
OR WITH A
SAVE BACK TO B
BIS
LAC
OR
SACL
D,C
0,0
C
C,O
LOAD 0
OR WITH C
SAVE BACK TO 0
EXAMPLE 2:
0016
0001 0000 2001 11
0002 DOOE 7AOO II
0003 OOOF 5000 11
7-19
BIT
Test Bits in Data Word -
TITLE:
Test Bits in Data Word
NAME:
BIT
OBJECTIVE:
Test bits in data word specified by one bit in mask
ALGORITHM:
(data) .AND. (mask)
CALLING
SEQUENCE:
BIT mask,data
ENTRY
CONDITIONS: 0 ~
mask~
127; 0
-+
BIT
Macro
ACC
~ data~
127
EXIT
CONDITIONS: ACC contains zero if no bits of mask are set in data word: any bits masked
that are set in data word will be set in ACC
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
2 words
DATA
MEMORY
REQUIRED:
None
None
EXECUTION
TIME:
2 cycles
FLOWCHART: BIT
LOAD MASK INTO
ACC
AND ACC WITH
DATA WORD
SOURCE:
*BIT TEST - BITS IN B TESTED BY MASK IN A
*
BIT
7-20
$MACRO A,B
LAC :A: ,0
AND :B:
$END
BIT TEST
LOAD :A:, MASK
AND WITH :B:
BIT
BIT
EXAMPLE:
0014
0001 OOOA 2008
0002 OOOB 7901
BIT
LAC
AND
B,A
B,O
A
LOAD B, MASK
AND WITH A
I
7-21
CMP
Compare Two Words -
CMP
Macro
TITLE:
Compare Two Words
NAME:
CMP
OBJECTIVE:
Load word into accumulator; then subtract the other word, allowing
comparison
ALGORITHM:
CMPX A,B - causes'" (A) - (B)'" ACC
CALLING
SEQUENCE:
CMP {A,*,* - ,* + },{B,*,* - ,* +
ENTRY
CONDITIONS: 0 ~ A
~
}
127; 0 ~ B ~ 127
EXIT
CONDITIONS: Accumulator contains value of second word subtracted from the first
word; auxiliary register is updated if necessary
I
PROGRAM
MEMORY
REQUIRED:
2 words
DATA
MEMORY
REQUIRED:
None
STACK
REQUIRED:
None
EXECUTION
TIME:
2 cycles
FLOWCHART:
CMP
LOAD ACC WITH 1ST
WORD
SUBTRACT 2ND
WORD
SOURCE:
*COMPARE A TO B
*CMP
7-22
$MACRO
A,B
LAC :A: ,0
SUB :B: ,0
$END
COMPaRE
LOAD :A:
SUBTRACT :B:
CMP
CMP
EXAMPLE 1:
0007
0001 0006 2001
0002 0007 1008
CMP
LAC
SUB
A,B
A,O
B,O
LOAD A
SUBTRACT B
CMP
LAC
SUB
*,B
*,0
B,O
LOAD *
SUBTRACT B
CMP
LAC
SUB
C,*+
C,O
*+,0
LOAD C
SUBTRACT *+
CMP
LAC
SUB
* *
*,0
*,0
LOAD *
SUBTRACT *
EXAMPLE 2:
0009
0001 0008 2088
0002 0009 1008
EXAMPLE 3:
0011
0001 DaDA 2004 11
0002 00 DB 10A8
EXAMPLE 4:
0013
0001 OOOC 2088
0002 0000 1088
I
I
7-23
CMPX
Compare Two Double Words -
Macro
TITLE:
Compare Two Double Words
NAME:
CMPX
OBJECTIVE:
Load double word into accumulator; then subtract the other double word,
allowing comparison
ALGORITHM:
CMPX A,B - causes-
CALLING
SEQUENCE:
CM PX {A, * ,* - , *
ENTRY
CONDITIONS: 0 ~ A
~
(A:A + 1) -
(B:B
+ 1)
- ACC
+ }, { B, * , * - , * + }
127; 0 ~ B ~ 127
EXIT
CONDITIONS: Accumulator contains value of second double word subtracted from the
first double word; auxiliary register is updated if necessary.
I
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
4 words
DATA
MEMORY
REQUIRED:
None
None
EXECUTION
TIME:
4 cycles
FLOWCHART: CMPX
(
BEGIN
J
~
LOAD 1 ST DOUBLE
WORD INTO Ace
~
SUBTRACT 2ND
DOUBLE WORD
FROM ACC
(
,
END
)
SOURCE:
*COMPARE A TO B, DOUBLE
*CMPX
7-24
$MACRO A,B
LDAX :A:
SUBX :B:
$END
COMPARE DOUBLE
LOAD DOUBLE :A:
SUBTRACT DOUBLE :B:
CMPX
.CMPX
CMPX
EXAMPLE 1:
0011
0001
0001
0002
0002
0001
0002
0006 6507
0007 6108
0008 6209
0009 630A
CMPX A,B
LDAX A
ZALH A
ADDS A+1
SUBX B
SUBH B
SUBS B+1
LOAD DOUBLE A
LOAD HIGH A
LOAD LOW A
SUBTRACT DOUBLE B
SUBTRACT HIGH
SUBTRACT LOW
CMPX C,*
LDAX C
ZALH C
ADDS C+1
SUBX *
SUBH *+
SUBS *-
LOAD DOUBLE C
LOAD HIGH C
LOAD LOW C
SUBTRACT DOUBLE *
SUBTRACT HIGH
SUBTRACT LOW
CMPX *-,D
LDAX *ZALS *ADDH *SUBX D
SUBH D
SUBS D+1
LOAD DOUBLE *LOAD LOW
LOAD HIGH '*-'
SUBTRACT DOUBLE D
SUBTRACT HIGH
SUBTRACT LOW
CMPX *+,*+
LDAX *+
ZALH *+
ADDS *+
SUBX *+
SUBH *+
SUBS *+
LOAD DOUBLE *+
LOAD HIGH
LOAD LOW ,*+,
SUBTRACT DOUBLE *+
SUBTRACT HIGH
SUBTRACT LOW
CMPX *-,*LDAX *ZALS *ADDH *SUBX *SUBS *SUBH *-
LOAD DOUBLE *LOAD LOW
LOAD HIGH '*-'
SUBTRACT DOUBLE *SUBTRACT LOW
SUBTRACT HIGH
EXAMPLE 2:
0013
0001
0001
0002
0002
0001
0002
OOOA 6500"
OOOB 6101"
OOOC 62A8
OOOD 6398
EXAMPLE 3:
0015
0001
0001
0002
0002
0001
0002
OOOE 6698
OOOF 6098
0010 6202"
0011 6303"
EXAMPLE 4:
0017
0001
0001
0002
0002
0001
0002
0012 65A8
0013 61A8
0014 62A8
0015 63A8
I
EXAMPLE 5:
0019
0001
0001
0002
0002
0001
0002
0016 6698
0017 6098
0018 6398
0019 6298
7-25
DEC
Decrement Word -
TITLE:
Decrement Word
NAME:
DEC
OBJECTIVE:
Decrement word or accumulator
ALGORITHM:
DEC
DEC
Macro
- causes-+ (ACC) - 1 -+ ACC
DEC A - causes-+ (A) - 1 -+ (A)
DEC ,AR - causes-+ (AR) - 1 -+ AR
CALLING
SEQUENCE:
DEC [A]LAR]
ENTRY
CONDITIONS: 0 ~ A ~ 127; AR
=0,1
EXIT
CONDITIONS: Specified word or auxiliary register is decremented; auxiliary register
pointer will point to specified auxiliary register
I
PROGRAM
MEMORY
REQUIRED:
1 - 3 words
DATA
MEMORY
REQUIRED:
1 word
STACK
REQUIRED:
None
EXECUTION
TIME:
1 - 3 cycles
FLOWCHART:
DEC
LOAD ACC WITH
VARIABLE
YES
YES
SUBTRACT ONE
FROM ACC
SAVE ACC IN
VARIABLE
7-26
SUBTRACT ONE
FROM ACC
POINT TO AUX.
REG. SPECIFIED
BY 2ND ARGUMENT
SUBTRACT ONE
FROM AUXILIARY
REGISTER
DEC
DEC
SOURCE:
*DECREMENT THE ACCUMULATOR, AN AUXILIARY
*REGISTER, OR MEMORY
*
DEC
$MACRO A,B
$IF 'A.L=O
$IF B.L=O
SUB ONE,O
$ELSE
LARP :B:
MAR
*-
$ENDIF
$ELSE
LAC :A: ,0
SUB ONE,O
SACL :A: ,0
$ENDIF
$ END
DECREMENT
DECREMENT AC
LOAD ARP WITH :B:
DECREMENT
LOAD :A:
DECREMENT
SAVE :A:
EXAMPLE 1:
0007
0001 0006 2001
0002 0007 1000"
0003 0008 5001
DEC
A
LAC A,O
SUB ONE,O
SACL A,O
LOAD A
DECREMENT
SAVE A
DEC
,A
LARP A
MAR *-
LOAD ARP WITH A
DECREMENT
EXAMPLE 2:
0009
0001 0009 6881
0002 OOOA 6898
I
EXAMPLE 3:
0011
0001 OOOB 1000"
DEC
SUB
ONE,O
DECREMENT THE ACCUMULATOR
EXAMPLE 4:
0015
0001 OOOF 6880
0002 0010 6898
DEC
,ARO
LARP ARO
MAR *-
LOAD ARP WITH ARO
DECREMENT
7-27
DECX
Double-Word Decrement -
TITLE:
Double-Word Decrement
NAME:
DECX
OBJECTIVE:
Decrement double word or accumulator
ALGORITHM:
OECX*
- causes-+
(@AR:@AR + 1) - 1 -+ @AR:@AR + 1
DECX *-
- causes-+
(@AR - 1 :@AR) - 1 -+ @AR - 1 :@AR
(AR) - 2 -+ AR
+
- causes-+
(@AR:AR:@AR + 1) - 1 -+ @AR:@AR + 1
(AR) + 2 -+ AR
DECXA
- causes-+
(A:A + 1) - 1 -+ A:A + 1
DECX
- causes-+
(ACC) - 1 -+ ACC
DECX *
CALLING
SEQUENCE:
DECX [A, *, * - , *
ENTRY
CONDITIONS: 0 ~ A
I
DECX
Macro
~
+]
127
EXIT
CONDITIONS: Specified double word is decremented;
auxiliary register is updated as necessary
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
7-28
1 - 5 words
DATA
MEMORY
REQUIRED:
1 word
None
EXECUTION
TIME:
1 - 5 cycles
DECX
DECX
FLOWCHART:
DECX
DECREMENT
ACC
DECREMENT
@AR AND
@AR-1
DECREMENT
@AR AND
@AR+1
DECREMENT
@AR AND
@AR+1
DECREMENT
A AND A+ 1
I
SOURCE:
*DECREMENT DOUBLE
*
DECX
$MACRO A
$VAR ST,SP,SM
$ASG 1*+1 TO SP.S
$ASG 1*_1 TO SM.S
$ASG 1*1 TO ST.S
$IF A.L=O
SUB ONE,O
$ELSE
$IF A.SV=SM.SV
ZALS *ADDH *+
SUB ONE,O
SACX *$ELSE
$IF A.SV=SP.SV
LDAX *
SUB ONE,O
SACX *+
DECREMENT DOUBLE
DECREMENT AC
LOAD '*-'
DECREMENT
SAVE '*-'
LOAD '*'
DECREMENT
SAVE ,*+,
7-29
DECX
UI:\,;X
$ELSE
$IF A.SV=ST.SV
LDAX *
SUB ONE,O
SACX *
$ELSE
LDAX :A:
SUB ONE,O
SACX :A:
$ENDIF
$END
LOAD 1*1
DECREMENT
SAVE 1*1
LOAD :A:
DECREMENT
SAVE :A:
EXAMPLE 1:
0011
0001
0001
0002
0002
0003
0001
0002
0006 6507
0007 6108
0008 1004"
0009 5807
OOOA 5008
DECX A
LDAX A
ZALH A
ADDS A+1
SUB ONE,O
SACX A
SACH A,O
SACL A+1,0
LOAD A
LOAD HIGH A
LOAD LOW A
DECREMENT
SAVE A
STORE HIGH
STORE LOW
DECX *
LDAX *
ZALH *+
ADDS *SUB ONE,O
SACX *
SACH *+,0
SACL *-,0
LOAD 1*1
LOAD HIGH
LOAD LOW 1*1
DECREMENT
SAVE 1*1
STORE HIGH
STORE LOW
DECX *ZALS *ADDH *+
SUB ONE,O
SACX *SACL *-,0
SACH *-,0
LOAD 1*_ 1
DECREMENT
SAVE 1*_1
STORE LOW
STORE HIGH
DECX *+
LDAX *
ZALH *+
ADDS *SUB ONE,O
SACX *+
SACH *+,0
SACL *+,0
LOAD 1*1
LOAD HIGH
LOAD LOW 1*1
DECREMENT
SAVE 1*+1
STORE HIGH
STORE LOW
DECX
SUB
DECREMENT AC
EXAMPLE 2:
0013
0001
0001
0002
0002
0003
0001
0002
I
OOOE 65A8
OOOC 6198
OOOD 1004"
OOOE 58A8
OOOF 5098
EXAMPLE 3:
0015
0001
0002
0003
0004
0001
0002
0010 6698
0011 60A8
0012 1004"
0013 5098
0014 5898
EXAMPLE 4:
0017
0001
0001
0002
0002
0003
0001
0002
0015 65A8
0016 6198
0017 1004"
0018 58A8
0019 50A8
EXAMPLE 5:
0019
0001 001A 1004"
7-30
ONE,O
INC
Increment Word -
TITLE:
Increment Word
NAME:
INC
OBJECTIVE:
Increment word or accumulator
ALGORITHM:
INC
- causes'" (ACC)
INC A - causes'" (A)
+
INC ,AR - causes'" (AR)
CALLING
SEQUENCE:
+
INC
Macro
1 ... ACC
1 ... (A)
+
1 ... AR
INC [A][,AR]
ENTRY
CONDITIONS: 0 ~
A~
127; AR =0,1
EXIT
CONDITIONS: Specified word or auxiliary register is incremented; auxiliary register
pointer specifies the named auxiliary register
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
1 - 3 words
DATA
MEMORY
REQUIRED:
None
EXECUTION
TIME:
1 word
I
1 - 3 cycle
FLOWCHART: INC
LOAD ACC WITH
VARIABLE
POINT TO AUX.
REG. SPECIFIED
BY 2ND ARGUMENT
ADD ONE TO
ACC
SAVE ACC IN
VARIABLE
ADD ONE TO
Ace
ADD ONE TO
AUX. REGISTER
7-31
II~\'"
II~ \."
SOURCE:
*INCREMENT AC, AR, OR MEM
*INC
$MACRO A,B
$IF A.L=O
$IF B.L=O
ADD ONE,O
$ELSE
LARP :B:
MAR
*+
$ENDIF
$ELSE
LAC :A: ,0
ADD ONE,O
SACL :A: ,0
$ENDIF
$END
INCREMENT
INCREMENT AC
LOAD ARP WITH :B:
INCREMENT
LOAD :A:
INCREMENT
SAVE :A:
EXAMPLE 1:
0007
0001 0006 2001
0002 0007 0000"
0003 0008 5001
INC
A
LAC A,O
ADD ONE,O
SACL A,O
LOAD A
INCREMENT
SAVE A
INC
,AR1
LARP AR1
MAR *+
LOAD ARP WITH AR1
INCREMENT
INC
ADD
INCREMENT
EXAMPLE 2:
0009
0001 0009 6881
0002 OOOA 68A8
I
EXAMPLE 3:
0011
0001 OOOB DODO"
ONE,O
EXAMPLE 4:
0015
0001 OOOF 6880
0002 0010 68A8
7-32
INC
fARO
LARP ARO
MAR *+
LOAD ARP WITH ARO
INCREMENT
INCX
Double-Word Increment -
INCX
Macro
TITLE:
Double-Word Increment
NAME:
INCX
OBJECTIVE:
Increment double word or accumulator
ALGORITHM:
INCX*
- causes-+
(@AR:@AR + 1) + 1 -+ @AR:@AR + 1
INCX *-
- causes-+
(@AR - 1 :@AR) + 1 -+ @AR - 1 : @A
(AR) - 2 -+AR
INCX*+
- causes-+
(@AR:@ AR + 1) + 1 -+ @AR:@AR + 1
(AR) + 2 -+ AR
INCXA
- causes-+
(A:A + 1) + 1 -+ A:A + 1
INCX
- causes-+
(ACC) + 1 -+ ACC
CALLING
SEQUENCE:
INCX [A, * 1* - 1* + ]
ENTRY
CON DITIONS: 0 ~ A
~
127
EXIT
CONDITIONS: Specified double word is incremented;
auxiliary register is updated as necessary
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
I
1 - 5 words
DATA
MEMORY
REQUIRED:
1 word
None
EXECUTION
TIME:
1 - 5 cycles
7-33
INCX
INCX
FLOWCHART: INCX
NO
INCREMENT
ACC
INCREMENT
@AR AND
@AR-1
YES
INCREMENT
@AR AND
@AR+1
YES
INCREMENT
@AR AND
@AR+1
INCREMENT
A AND A+1
I
SOURCE:
*INCREMENT DOUBLE
*INCX
7-34
$MACRO A
$VAR ST,SP,SM
$ASG '*+' TO SP.S
$ASG '*-' TO SM.S
$ASG ,*, TO ST.S
$IF A.L=O
ADD ONE,O
$ELSE
$IF A.SV=SM.SV
ZALS *ADDH *+
ADD ONE,O
SACX *$ELSE
$IF A.SV=SP.SV
LDAX *
ADD ONE,O
SACX *+
INCREMENT DOUBLE
INCREMENT AC
LOAD '*-'
INCREMENT
SAVE '*_1
LOAD 1*1
INCREMENT
SAVE 1*+1
AR = AR+2
INCX
INCX
$ELSE
$IF A.SV=ST.SV
LDAX *
ADD ONE,O
SACX *
$ELSE
LDAX :A:
ADD ONE,O
SACX :A:
$ENDIF
$END
LOAD '*'
INCREMENT
SAVE ,*,
LOAD :A:
INCREMENT
SAVE :A:
EXAMPLE 1:
0011
0001
0001
0002
0002
0003
0001
0002
0006 6507
0007 6108
0008 0004"
0009 5807
OOOA 5008
INCX A
LDAX A
ZALH A
ADDS A+1
ADD ONE,O
SACX A
SACH A,O
SACL A+1,0
LOAD A
LOAD HIGH A
LOAD LOW A
INCREMENT
SAVE A
STORE HIGH
STORE LOW
INCX *
LDAX *
ZALH *+
ADDS *ADD ONE,O
SACX *
SACH *+,0
SACL *-,0
LOAD ,*,
LOAD HIGH
LOAD LOW '*'
INCREMENT
SAVE ,*,
STORE HIGH
STORE LOW
INCX *ZALS *ADDH *+
ADD ONE,O
SACX *SACL *-,0
SACH *-,0
LOAD '*-'
INCREMENT
SAVE '*-'
STORE LOW
STORE HIGH
INCX *+
LDAX *
ZALH *+
ADDS *ADD ONE,O
SACX *+
SACH *+,0
SACL *+,0
LOAD ,*,
LOAD HIGH
LOAD LOW ,*,
INCREMENT
SAVE ,*+,
STORE HIGH
STORE LOW
INCX
ADD
INCREMENT AC
EXAMPLE 2:
0013
0001
0001
0002
0002
0003
0001
0002
0008 65A8
OOOC 6198
OOOD 0004"
OOOE 58A8
OOOF 5098
I
EXAMPLE 3:
0015
0001
0002
0003
0004
0001
0002
0010 6698
0011 60A8
0012 0004"
0013 5098
0014 5898
EXAMPLE 4:
0017
0001
0001
0002
0002
0003
0001
0002
0015 65A8
0016 6198
0017 0004"
0018 58A8
0019 50A8
EXAMPLE 5:
0019
0001 001A 0004"
ONE,O
7-35
LACARY
Load Accumulator
from Address in Accumulator -
Macro
TITLE:
Load Accumulator from Address in Accumulator
NAME:
LACARY
OBJECTIVE:
Load accumulator from array in data RAM; the address of the data RAM
location is in the accumulator; the data will be left-shifted in the
accumulator
ALGORITHM:
(ACC) -+ AR1
(@AR1) * 2shift-+ ACC
CALLING
SEQUENCE:
LACARY [shift]
ENTRY
CONDITIONS: 0 ~ shift < 16; 0 ~ (ACC)
~
143
EXIT
CONDITIONS: Data RAM location pointed to by accumulator is stored in the
accumulator; AR1 is overwritten
I
LACARY
PROGRAM
MEMORY
REQUIRED:
4 words
DATA
MEMORY
REQUIRED:
1 word
STACK
REQUIRED:
None
EXECUTION
TIME:
4 cycles
FLOWCHART:
LACARY
LOAD ARRAY
POINTER INTO AUX.
REGISTER
LOAD Ace
WITHOUT SHIFT
LOAD Ace
WITH SHIFT
7-36
LACARY
LACARY
SOURCE:
*LOAD AC FROM ADDRESS IN AC
*
LACARY $MACRO A
ACTAR AR1
$IF A.L=O
LAC *,0
$ELSE
LAC *, :A:
$ENDIF
$END
AC TO AR1
LOAD
LOAD AND SHIFT
EXAMPLE 1:
0011
0001
0001
0002
0003
0002
0006
0007
0008
0009
5006 11
3906 11
6881
2888
LACARY 8
ACTAR AR1
SACL XRO,O
LAR AR1,XRO
LARP AR1
LAC *,8
AC TO AR1
STORE AC TO XRO
RE-LOAD AR1
LOAD AR POINTER
LOAD AND SHIFT
5006 11
3906 11
6881
2088
LACARY
ACTAR AR1
SACL XRO,O
LAR AR1,XRO
LARP AR1
LAC *,0
AC TO AR1
STORE AC TO XRO
RE-LOAD AR1
LOAD AR POINTER
LOAD
EXAMPLE 2:
0013
0001
0001
0002
0003
0002
OOOA
OOOS
OOOC
DODD
I
7-37
LASH
Arithmetic Left Shift -
LASH
Macro
TITLE:
Arithmetic Left Shift
NAME:
LASH
OBJECTIVE:
Move word from one data location to another with an arithmetic left shift
ALGORITHM:
(A) * 2shift --+ B
CALLING
SEQUENCE:
LASH A,B,shift
ENTRY
CONDITIONS:
o~ A ~
127; 0
~
B ~ 127; 0
~
shift < 16
EXIT
CONDITIONS: B contains the shifted value of A
2 words
DATA
MEMORY
REQUIRED:
None
STACK
REQUIRED:
None
EXECUTION
TIME:
2 cycles
FLOWCHART:
LASH
PROGRAM
MEMORY
REQUIRED:
I
LOAD ACC WITH
A, SHIFTED N
SAVE ACC AT
LOCATION B
SOURCE:
*MOVE A TO B (SINGLE-VAR) WITH N (CONST) BIT
*LEFT ARITHMETIC SHIFT
*
LASH
$MACRO A,B,N
LAC :A: :N:
SACL :B: ,0
$END
I
7-38
MOVE WITH LEFT ARITH. SHIFT
LOAD :A: LEFT SHIFT
STORE TO :B:
LASH
LASH
EXAMPLE:
0013
0001 0008 2507
0002 0009 5008
LASH A,B,S
LAC A,S
SACL B,O
LOAD A LEFT SHIFT
STORE TO B
I
7-39
LASX
Double-Word Arithmetic Left Shift -
Macro
TITLE:
Double-Word Arithmetic Left Shift
NAME:
LASX
OBJECTIVE:
Move double word from one data location to another in data memory with
left shift
ALGORITHM:
(A:A
CALLING
SEQUENCE:
LASX A, B,shift
ENTRY
CONDITIONS: 0 ~ A
+
~
1) * 2shift-+ B:B
+
1
126; 0 ~ B ~ 126; 0
~
shift < 16
EXIT
CONDITIONS: B: B + 1 contains shifted value of A:A + 1
I
8 words
DATA
MEMORY
REQUIRED:
1 word
STACK
REQUIRED:
None
EXECUTION
TIME:
8 cycles
FLOWCHART:
LASX
PROGRAM
MEMORY
REQUIRED:
(
,
BEGIN )
,
,
LOAD ACC WITH
A+ 1, SHIFTED N
SAVE ACC LOW IN
B+ 1; SAVE ACC
HIGH IN B
CREATE MASK
(16-N) 0'5;
(N) 1'5
,
,
ZERO SIGN-EXTENDED BITS IN B
,
ADD A, SHIFTED N
TO B
(
7-40
END
J
LASX
LASX
LASX
SOURCE:
*MOVE A TO B (DOUBLE VAR) WITH N (CONST) BIT
*LEFT ARITHMETIC SHIFT
*
LASX
$MACRO A,B,N
LAC : A: +1 , : N:
SACL :B:+1,0
SACH :B:, 0
LAC MINUS,:N:
NOT
AND :B:
ADD :A:, :N:
SACL :B:, 0
$END
MOVE DOUBLE WITH ARITH. SHIFT
LOAD LOW, SHIFT LEFT
SAVE IN LOW
SAVE HIGH OVERFLOW
GET MASK
TAKE SIGNIFICANT BITS
ADD IN SHIFT HIGH PART
SAVE HIGH
EXAMPLE:
0011
0001
0002
0003
0004
0005
0001
0006
0007
0008
0006
0007
0008
0009
2308
SODA
5809
2305"
OOOA
OOOB
OOOC
OOOD
7805"
7909
0307
5009
LASX A,B,3
LAC A+1,3
SACL B+1,0
SACH B,O
LAC MINUS,3
NOT
XOR MINUS
AND B
ADD A,3
SACL B,O
LOAD LOW, SHIFT LEFT
SAVE IN LOW
SAVE HIGH OVERFLOW
GET MASK
INVERT
TAKE SIGNIFICANT BITS
ADD IN SHIFT HIGH PART
SAVE HIGH
I
7-41
Load Double-Word into Accumulator
from Address in Accumulator - Macro
LAXARV
LAXARV
TITLE:
Load Double Word into Accumulator from Address in Accumulator
NAME:
LAXARY
OBJECTIVE:
Load accumulator from double-word array in data RAM; the address of
the first RAM location is in the accumulator
ALGORITHM:
(ACC) -+ AR1
(@AR1) -+ ACC high
(@AR1 + 1) -+ ACC low
CALLING
SEQUENCE:
LAXARY
ENTRY
CONDITIONS: 0 ~ (ACC)
~
143
EXIT
CONDITIONS: Double word pointed to by accumulator is stored in the accumulator; AR1
is overwritten
I
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
5 words
DATA
MEMORY
REQUIRED:
1 word
None
EXECUTION
TIME:
5 cycles
FLOWCHART: LAXARY
LOAD ARRAY
POINTER INTO AUX.
REGISTER
LOAD DOUBLE
WORD INTO Ace
SOURCE:
*LOAD DOUBLE AC FROM ADDRESS IN AC
*
LAXARY $MACRO
ACTAR ARI
LDAX *+
$END
7-42
AC TO ARI
LOAD DOUBLE
LAXARY
LAXARY
EXAMPLE:
0011
0001
0001
0002
0003
0002
0001
0002
0006 5006"
0007 3906"
0008 6881
0009 65A8
OOOA 61A8
LAXARY
ACTAR AR1
SACL XRO,O
LAR AR1,XRO
LARP AR1
LDAX *+
ZALH *+
ADDS *+
AC TO AR1
STORE AC TO XRO
RE-LOAD AR1
LOAD AR POINTER
LOAD DOUBLE
LOAD HIGH
LOAD LOW '*+'
7-43
LCAC
Load Constant into Accumulator -
Macro
TITLE:
Load Constant into Accumulator
NAME:
LCAC
OBJECTIVE:
Move constant value into accumulator with possible left shift
ALGORITHM:
Constant -+ ACC
if shift -+ (ACC) -+
temp * 2shift-+ ACC
CALLING
SEQUENCE:
ENTRY
CONDITIONS:
LCAC constant,shift, temp
- 32768
~
constant ~ 32767; 0
o ~ temp ~ 127
~
shift < 16;
EXIT
CONDITIONS: Accumulator contains value of the constant
I
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
7-44
1 - 5 words + LDAC$ routine
DATA
MEMORY
REQUIRED:
0 - 2 words
2 levels with LDAC$
EXECUTION
TIME:
1 - 15 cycles
LCAC
LCAC
FLOWCHART:
LCAC
LCAC
YES
YES
BUILD EQU
STATEMENT
YES
LOAD ACC
IMMEDIATE
CALL LDAC$ TO
LOAD CONSTANT
INTO Ace
I
NO
NO
USE XRO AS
TEMPORARY
YES
SAVE ACC IN
TEMPORARY
RELOAD TEMPORARY
WITH SHIFT
7-45
LCAC
LCAC
SOURCE:
**LOAD
*
*
*
CONSTANT TO AC
LCAC A
LCAC A,B
LCAC A,B,T
LOAD CONSTANT A
LOAD CONSTANT A, SHIFTED B, USE TEMP XRO
LOAD CONSTANT A, SHIFTED B, USE TEMP T
*
LCAC
I
$MACRO A,B,T
$IF A.SA&$REL
CALL LDAC$
LOAD AC WITH:
REF LDAC$
DATA :A:
:A:
$ELSE
$IF A.SA&$UNDF
$VAR L,Q
$ASG '$$LAB' TO L.S
$ASG L.SV+1 TO L.SV
V$:L.SV: EQU :A:
$ASG IV$' TO Q.S
$ASG :Q.S::L.SV: TO A.S
$ENDIF
$IF (A.SV<256)&(A.SV>-1)
LACK :A:
LOAD AC WITH :A:
$ELSE
CALL LDAC$
LOAD AC WITH:
REF LDAC$
DATA :A:
:A:
$ENDIF
$ENDIF
$IF B.L#=O
$IF (B.V>O)
$IF T.L=O
XRO AS TEMP
$ASG 'XRO ' TO T.S
$ENDIF
SACL :T:,O
STORE UNSHIFTED CONSTANT
LAC :T:,:B:
LOAD SHIFTED
$ENDIF
$ENDIF
$END
EXAMPLE 1:
LCAC 1,5
0012
0001
0001 V$2 EQU 1
LACK V$2
0002 0007 7E01
SACL XRO,O
0003 0008 5003 11
LAC XRO,5
0004 0009 2503"
LOAD AC WITH V$2
STORE UNSHIFTED CONSTANT
LOAD SHIFTED
EXAMPLE 2:
0014
0080
0001
0002 OOOA 7E80
LCAC 128,0
V$3 EQU 128
LACK V$3
LOAD AC WITH V$3
LCAC -1000,5
V$5 EQU -1000
CALL LDAC$
LOAD AC WITH:
EXAMPLE 3:
0018
FC18
0001
0002 OOOE F800
OOOF 0000
7-46
LCAC
0003
0004 0010 FC18
0005 0011 5003"
0006 0012 2503"
LCAC
REF
DATA
SACL
LAC
LDAC$
V$5
XRO,O
XRO,5
V$5
STORE UNSHIFTED CONSTANT
LOAD SHIFTED
EXAMPLE 4:
0022
0001 0016 7E07
0002 0017 5008
0003 0018 2608
LCAC A,6,B
LACK A
SACL B,O
LAC B,6
LOAD AC WITH A
STORE UNSHIFTED CONSTANT
LOAD SHIFTED
I
7-47
LCACAR
Load Constant to Accumulator
from Address in Accumulator - Macro
TITLE:
Load Constant to Accumulator from Program Address in Accumulator
NAME:
LCACAR
OBJECTIVE:
Load accumulator from array in program RAM; the address of the
program ROM location is in the accumulator; the data will be left-shifted
in the accumulator
ALGORITHM:
(@ACC) -+ temp
(temp) * 2shift -+ ACC
CALLING
SEQUENCE:
LCACAR [CH,TEMP]
ENTRY
CONDITIONS: 0 ~ shift < 16; 0 ~ TEMP ~ 127; 0 ~ (ACC) ~ 4095
EXIT
CONDITIONS: Program ROM location pointed to by accumulator is stored in the
accumulator
I
LCACAR
PROGRAM
MEMORY
REQUIRED:
2 words
DATA
MEMORY
REQUIRED:
1 word
STACK
REQUIRED:
1 level
EXECUTION
TIME:
4 cycles
FLOWCHART:
LCACAR
USE XRO AS
TEMP STORAGE
LOAD TEMPORARY
TO ACC WITH
NO SHIFT
LOAD TEMPORARY
TO Ace WITH SHIFT
7-48
LCACAR
LCACAR
SOURCE:
*LOAD CONSTANT ADDRESS BY AC IN AC
*
(IN ROM)
*
LCACAR $MACRO A,T
$IF T.L=O
ASSIGN TEMP
$ASG 'XRO' TO T.S
$ENDIF
TBLR :T:
READ FROM ROM TO :T:
$IF A.L=O
LAC :T:,O
LOAD :T: UNSHIFTED
$ELSE
LAC :T:,:A:
LOAD :T: SHIFTED
$ENDIF
$END
EXAMPLE 1:
0011
0001 0006 6706"
0002 0007 2806"
LCACAR 8
TBLR XRO
LAC XRO,8
READ FROM ROM TO XRO
LOAD XRO SHIFTED
LCACAR 4,A
TBLR A
LAC A,4
READ FROM ROM TO A
LOAD A SHIFTED
LCACAR
TBLR XRO
LAC XRO,O
READ FROM ROM TO XRO
LOAD XRO UNSHIFTED
LCACAR ,C
TBLR C
LAC C,O
READ FROM ROM TO C
LOAD C UNSHIFTED
EXAMPLE 2:
0013
0001 0008 6707
0002 0009 2407
EXAMPLE 3:
0015
0001 OOOA 6706"
0002 OOOB 2006"
I
EXAMPLE 4:
0017
0001 OOOC 6700"
0002 OOOD 2000"
7-49
LCAR
Load Constant into Auxiliary Reqister -
TITLE:
Load Constant into Auxiliary Register
NAME:
LCAR
OBJECTIVE:
Move constant value into auxiliary register
ALGORITHM:
Constant --+ AR
CALLING
SEQUENCE:
LCAR AR,constant
ENTRY
CONDITIONS:
- 32768 ~ constant ~ 32767; AR = 0,1
Macro
EXIT
CONDITIONS: Auxiliary register contains value of the constant
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
I
7-50
1 - 3 words (+ LDAR$O and
LDAR$1 routines)
2 levels with LDAR$
DATA
MEMORY
REQUIRED:
0 - 2 words
EXECUTION
TIME:
1 - 13 cycles
LCAR
LCAR
FLOWCHART:
LCAR
LeAR
YES
YES
CREATE
VARIABLE
WITH VALUE
OF NUMBER
YES
LOAD AUX.
REGISTER
IMMEDIATE
CALL LDAR$O OR
LDAR$1 TO PUT
DATA IN AUX.
REGISTER
I
SOURCE:
*LOAD CONSTANT (TO AROjl)
*
LCAR AROjl,CONSTANT
*
LCAR
$MACRO A,B
$IF
B.SA&$REL
CALL LDAR$:A.V:
LOAD :A: WITH:
REF LDAR$:A.V:
DATA :B:
:B:
$ELSE
$IF B.SA&$UNDF
$VAR L,Q
$ASG '$$LAB' TO L.S
$ASG L.SV+l TO L.SV
V$:L.SV: EQU :B:
$ASG IV$I TO Q.S
$ASG :Q.S::L.SV: TO B.S
$ENDIF
$IF (B.SV<256)&(B.SV>-1)
LARK :A:,:B:
LOAD :A: WITH :B:
$ELSE
CALL LDAR$:A.V:
LOAD :A: WITH:
REF LDAR$:A.V:
DATA :B:
:B:
7-51
LeAR
LeAR
$ENDIF
$ENDIF
$END
EXAMPLE 1:
0010
0001 0006 7007
LCAR O,A
LARK O,A
LOAD 0 WITH A
LCAR 1 , C
CALL LDAR$l
LOAD 1 WITH:
EXAMPLE 2:
0012
0001 0007 F800
0008 0000
0002
0003 0009 0000"
REF LDAR$l
DATA C
C
EXAMPLE 3:
0014
0001
0002 OOOA
OOOB
0003
0004 OOOC
FC18
F800
0000
FC18
LCAR AR1,-1000
V$l EQU -1000
CALL LDAR$l
REF LDAR$l
DATA V$l
LOAD AR1 WITH:
V$l
EXAMPLE 4:
0016
ODDS
0001
0002 OOOD F800
OOOE 0000
0003
0004 OOOF ODDS
I
7-52
LCAR ARO,3333
V$2 EQU 3333
CALL LDAR$O
REF LDAR$O
DATA V$2
LOAD ARO WITH:
V$2
LCAX
Load Double-Word Constant into Accumulator -
TITLE:
Load Double-Word Constant into Accumulator
NAME:
LCAX
OBJECTIVE:
Move double-word constant value into accumulator
ALGORITHM:
Constant -+ ACC
CALLING
SEQUENCE:
LCAX (upper,lower)
ENTRY
CONDITIONS:
- 32768
~
upper ~ 32767; - 32768
~
LCAX
Macro
lower ~ 32767
EXIT
·CONDITIONS: Accumulator contains value of the constant
PROGRAM
MEMORY
REQUIRED:
2 words
STACK
REQUIRED:
2 levels
+
LDAX$ routine
DATA
MEMORY
REQUIRED:
3 words
EXECUTION
TIME:
18 cyctes
FLOWCHART: LCAX
I
(
,
,
,
BEGIN
)
CALL LDAX$ WITH
CONSTANTS IN
NEXT TWO WORDS
•
READ SECOND
(LOWER) CaNST ANT
~
INCREMENT RETURN
ADDRESS
READ FIRST
(UPPER) CONSTANT
j
LOAD TWO WORDS
INTO ACC
l
INCREMENT
ARGUMENT
POINTER
l
RETURN
(
~
END
)
7-53
LCAX
LCAX
SOURCE:
*LOAD DOUBLE CONSTANT (TO AC)
*
LCAX (HIGH VALUE,LOW VALUE)
*
LCAX
$MACRO A
CALL LDAX$
REF LDAX$
DATA :A:
$END
LOAD DOUBLE
DATA LIST
EXAMPLE 1:
0010
0001 0006
0007
0002
0003 0008
0009
F800
0000
0080
0003
LCAX (128,3)
CALL LDAX$
REF LDAX$
DATA 128,3
LOAD DOUBLE
DATA LIST
EXAMPLE 2:
0012
0001 OOOA
OOOB
0002
0003 DaDe
DODD
F800
0000
FC18
0005
LCAX (-1000,S)
CALL LDAX$
REF LDAX$
DATA -1000,S
LOAD DOUBLE
DATA LIST
EXAMPLE 3:
0014
0001 OOOE F800
OOOF 0000
0002
0003 0010 0007
0011 0009
I
7-54
LCAX (A,B)
CALL LDAX$
REF LDAX$
DATA A,B
LOAD DOUBLE
DATA LIST
LCAXAR
Load Double-Word Constant to Accumulator
from Program Memory - Macro
LCAXAR
TITLE:
Load Double-Word Constant to Accumulator from Program Memory
NAME:
LCAXAR
OBJECTIVE:
Load accumulator from double-word array in program RAM; the address
of the first program ROM location is in the accumulator
ALGORITHM:
(@ACC) ~ temp
(@ACC + 1 ) ~ temp + 1
(temp:temp + 1 ) ~ ACC
CALLING
SEQUENCE:
LCAXAR [TEM Pl
ENTRY
CONDITIONS: 0 ~ TEMP ~ 127; 0
~
(ACC)
~
4095
EXIT
CON DITIONS: Program ROM double-word location pointed to by
accumulator is stored in the accumulator
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
5 words
DATA
MEMORY
REQUIRED:
2 words
1 level
EXECUTION
TIME:
9 cycles
I
FLOWCHART: LCAXAR
ASSIGN XRO
AND XR1 AS
TEMP STORAGE
YES
READ DOUBLE WORD
FROM PROGRAM
MEMORY INTO TEMP
LOAD DOUBLE WORD
FROM TEMPORARY
INTO ACC
7-55
LGAXAR
L\.;AAAH
SOURCE:
*LOAD FROM ROW AT ADDRESS IN ACCUMULATOR,
*DOUBLE CONSTANT TO ACCUMULATOR
*
LCAXAR $MACRO T
$IF T.L=O
ASSIGN TEMP
$ASG 'XRO' TO T.S
$ENDIF
TBLR :T:
READ HIGH PART OF :T:
ADD ONE,O
INCREMENT AC
TBLR :T:+1
READ LOW PART OF :T:
LDAX :T:
LOAD TO AC
$END
EXAMPLE 1:
0011
0001
0002
0003
0004
0001
0002
0006 6706 11
0007 0004 11
0008 6707 11
0009 6506 11
OOOA 6107 11
LCAXAR
TBLR XRO
ADD ONE,O
TBLR XRO+1
LDAX XRO
ZALH XRO
ADDS XRO+1
READ HIGH PART OF XRO
INCREMENT AC
READ LOW PART OF XRO
LOAD TO AC
LOAD HIGH XRO
LOAD LOW XRO
LCAXAR C
TBLR C
ADD ONE,O
TBLR C+1
LDAX C
ZALH C
ADDS C+1
READ HIGH PART OF C
INCREMENT AC
READ LOW PART OF C
LOAD TO AC
LOAD HIGH C
LOAD LOW C
EXAMPLE 2:
0013
0001
0002
0003
0004
0001
0002
I
7-56
OOOB 6700 11
OOOC 0004 11
0000 6701 11
OOOE 6500 11
OOOF 6101 11
LCP
Load Constant into P Register -
TITLE:
Load Constant into P Register
NAME:
LCP
OBJ ECTIVE:
Move constant value into P register
ALGORITHM:
1 * constant -+ P
CALLING
SEQUENCE:
LCP constant
ENTRY
CONDITIONS:
- 4096
~
Macro
LCP
constant ~ 4095
EXIT
CONDITIONS: P register contains value of the constant;
T register contains value 1
PROGRAM
MEMORY
REQUIRED:
2 words
DATA
MEMORY
REQUIRED:
1 word
STACK
REQUIRED:
None
EXECUTION
TIME:
2 cycles
FLOWCHART:
LCP
I
LOAD T REGISTER
WITH ONE
LOAD P REGISTER
WITH CONSTANT
SOURCE:
*LCP
*
LCP
LOAD A CONSTANT TO THE P REGISTER
$MACRO A
LT
ONE
MPYK :A:
$END
LOAD A ONE
MAKE CONSTANT
7-57
LCP
LCP
EXAMPLE 1:
0013
0001 0008 6A01 11
0002 0009 8007
LCP A
ONE
LT
MPYK A
LOAD A ONE
MAKE CONSTANT
LCP -4096
ONE
LT
MPYK -4096
LOAD A ONE
MAKE CONSTANT
LCP 4095
LT
ONE
MPYK 4095
LOAD A ONE
MAKE CONSTANT
LCP -4000
ONE
LT
MPYK -4000
LOAD A ONE
MAKE CONSTANT
EXAMPLE 2:
0015
0001 OOOA 6A01 11
0002 OOOB 9000
EXAMPLE 3:
0017
0001 oooe 6A01 11
0002 0000 8FFF
EXAMPLE 4:
0019
0001 OOOE 6A01 11
0002 OOOF 9060
I
7-58
Load Constant into P Register
and Accumulator - Macro
LCPAC
TITLE:
Load Constant into P Register and Accumulator
NAME:
LCPAC
OBJECTIVE:
Move constant value into P register and accumulator
ALGORITHM:
1 * constant -+ P
(P) -+ ACe
CALLING
SEQUENCE:
LCPAC constant
ENTRY
CONDITIONS:
- 4096
~
constant
~
LCPAC
4095
EXIT
CONDITIONS: P register and accumulator contain value of the constant;
T register contains the value 1
PROGRAM
MEMORY
REQUIRED:
3 words
DATA
MEMORY
REQUIRED:
1 word
STACK
REQUIRED:
None
EXECUTION
TIME:
3 cycles
FLOWCHART:
LCPAC
I
(
,
,
BEGIN)
LOAD T REGISTER
WITH ONE
LOAD P REGISTER
(MULTIPLY
ARGUMENT)
•
•
LOAD P REGISTER
INTO Ace
(
END
)
SOURCE:
*LCPAC
*
LCPAC
LOAD A CONST TO P AND AC REGISTERS
$MACRO
A
7-59
LCPAC
LCPAC
ONE
LT
HPYK :A:
PAC
$END
LOAD A ONE
MAKE CONSTANT
TO THE AC
EXAMPLE 1:
0013
0001 0009 6A01"
0002 OOOA 8007
0003 OOOB 7F8E
LCPAC A
ONE
LT
HPYK A
PAC
LOAD A ONE
MAKE CONSTANT
TO THE AC
LCPAC -4096
ONE
LT
MPYK -4096
PAC
LOAD A ONE
MAKE CONSTANT
TO THE AC
LCPAC 4095
LT
ONE
MPYK 4095
PAC
LOAD A ONE
MAKE CONSTANT
TO THE AC
LCPAC -4000
LT
ONE
MPYK -4000
PAC
LOAD A ONE
MAKE CONSTANT
TO THE AC
EXAMPLE 2:
0015
0001 OOOC 6A01"
0002 OOOD 9000
0003 OOOE 7F8E
EXAMPLE 3:
0017
0001 OOOF 6A01"
0002 0010 8FFF
0003 0011 7F8E
EXAMPLE 4:
0019
0001 0012 6A01"
0002 0013 9060
0003 0014 7F8E
I
7-60
LDAX
Load Double Word -
TITLE:
Load Double Word
NAME:
LDAX
OBJECTIVE:
Load double word into accumulator
~LGORITHM:
LDAX *
- causes-+ (@AR:@AR + 1) -+ ACC
LDAX * -
- causes-+ (@AR - 1: @ AR) -+ ACC
(AR) - 2-+AR
LDAX *
+
causes-+ (@AR:@ AR + 1) -+ ACC
(AR) + 2-+AR
- causes-+ (A:A + 1) -+ ACC
LDAX A
CALLING
SEQUENCE:
-
LDAX {A,*,* -,*
ENTRY
CONDITIONS: 0 ~ A
~
LDAX
Macro
+}
127
EXIT
CONDITIONS: Accumulator contains value of double word;
auxiliary register is updated if necessary
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
I
2 words
DATA
MEMORY
REQUIRED:
None
None
EXECUTION
TIME:
2 cycles
7-61
LDAX
LDAX
FLOWCHART:
LDAX
LOAD @AR
AND @AR+ 1
LOAD @AR
AND @AR+ 1
LOAD @AR
AND @AR+1
LOAD
A AND A+1
END
I
SOURCE:
*LOAD DOUBLE PRECISION
*
LDAX
7-62
$MACRO A
$VAR ST,SP,SM
$ASG 1*1 TO ST.S
$ASG 1*+1 TO SP.S
$ASG 1*_1 TO SM.S
$IF A.SV=ST.SV
ZALH *+
ADDS *$ELSE
$IF A.SV=SP.SV
ZALH *+
ADDS *+
$ELSE
$IF A.SV=SM.SV
ZALS *ADDH *$ELSE
ZALH :A:
ADDS :A:+l
$ENDIF
$ENDIF
$ENDIF
$END
LOAD DOUBLE
LOAD HIGH
LOAD LOW 1*1
LOAD HIGH
LOAD LOW 1*+1
LOAD LOW
LOAD HIGH 1*_1
LOAD HIGH :A:
LOAD LOW :A:
LDAX
LDAX
EXAMPLE 1:
0011
0001 0006 6507
0002 0007 6108
LDAX A
ZALH A
ADDS A+l
LOAD HIGH A
LOAD LOW A
LDAX *
ZALH *+
ADDS *-
LOAD HIGH
LOAD LOW 1*1
LDAX *ZALS *ADDH *-
LOAD LOW
LOAD HIGH 1*_1
LDAX *+
ZALH *+
ADDS *+
LOAD HIGH
LOAD LOW 1*+1
EXAMPLE 2:
0013
0001 0008 65A8
0002 0009 6198
EXAMPLE 3:
0015
0001 OOOA 6698
0002 OOOB 6098
EXAMPLE 4:
0017
0001 oooe 65A8
0002 OOOD 61A8
I
7-63
LTK
Load Constant into T Register -
TITLE:
Load Constant into T Register
NAME:
LTK
OBJECTIVE:
Move constant value into T register
ALGORITHM:
Constant -+ T
CALLING
SEQUENCE:
LTK constant
ENTRY
CONDITIONS:
- 32768
~
Macro
constant ~ 32767
EXIT
CONDITIONS: T register contains value of the constant
I
PROGRAM
MEMORY
REQUIRED:
3 words (+ LTK$ routine)
DATA
MEMORY
REQUIRED:
2 words
STACK
REQUIRED:
2 levels
EXECUTION
TIME:
13 cycles
FLOWCHART:
LTK
MOVE CONSTANT
TO DATA MEMORY
LOAD T REGISTER
WITH VALUE IN
DATA MEMORY
SOURCE:
*LOAD CONSTANT TO T
*
LTK
7-64
$MACRO A
CALL LTK$
REF LTK$
DATA :A:
$END
LOAD :A: TO T
LTK
LTK
LTK
EXAMPLE 1:
0012
0001 0009 F800
OOOA 0000
0002
0003 OOOB 0007
LTK A
CALL LTK$
LOAD A TO T
REF LTK$
DATA A
EXAMPLE 2:
0014
0001 OOOC F800
DODD 0000
0002
0003 00 DE 7FFF
LTK >7FFF
CALL LTK$
LOAD >7FFF TO T
REF LTK$
DATA >7FFF
EXAMPLE 3:
0016
0001 OOOF F800
0010 0000
0002
0003 0011 8000
LTK >8000
CALL LTK$
LOAD >8000 TO T
REF LTK$
DATA >8000
I
7-65
MAX
Select Maximum of Two Words -
TITLE:
Select Maximum of Two Words
NAME:
MAX
OBJECTIVE:
Load maximum of two words into accumulator
ALGORITHM:
If (A)
CALLING
SEQUENCE:
MAX A,B
ENTRY
CONDITIONS: 0 ~ A
> (B)
~
Macro
then (A) -+ ACC
else (B) -+ ACe
127; 0 ~ B ~ 127
EXIT
CONDITIONS: Accumulator contains maximum value of two words
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
8 words
DATA
MEMORY
REQUIRED:
None
None
EXECUTION
TIME:
5 - 7 cycles
FLOWCHART: MAX
I
COMPARE 1ST
ARGUMENT AND 2ND
ARGUMENT
LOAD 1ST
ARGUMENT INTO
Ace
LOAD 2ND
ARGUMENT INTO ACC
7-66
MAX
MAX
MAX
SOURCE:
*SELECT MAXIMUM OF SINGLE A OR B
*A AND B ARE VARIABLES
*
MAX
$MACRO A,B
LAC :A:,O
LOAD :A:
SUB :B:,O
COMPARE :B:
$VAR L,L1,L2
$ASG I$$LABI TO L.S
$ASG L.SV+2 TO L.SV
UNIQUE LABEL
$ASG L.SV-1 TO L1.V
$ASG L.SV
TO L2.V
BGZ L$:L1.V:
BRANCH IS :A:>:B:
LAC :B:,O
LOAD :B:
L$:L2.V:
TO CONTINUE
B
L$:L1.V: LAC :A:,O
LOAD :A:
L$:L2.V: EQU $
CONTINUE
$END
EXAMPLE:
0011
MAX A,B
0001 0006 2007
LAC A,O
0002 0007 1008
SUB B,O
0003 0008 FCOO
BGZ L$l
0009 OOOD I
0004 OOOA 2008
LAC B,O
0005 OOOB F900
B
L$2
oooe OOOEI
0006 OOOD 2007 L$l
LAC A,O
OODEI L$2 EQU $
0007
LOAD A
COMPARE B
BRANCH IS A>B
LOAD B
TO CONTINUE
LOAD A
CONTINUE
I
7-67
MAXX
Select Maximum of Two Double Words -
TITLE:
Select Maximum of Two Double Words
NAME:
MAXX
OBJECTIVE:
Load maximum of two double words into accumulator
ALGORITHM:
If (A:A + 1) > (8:B + 1) then (A:A + 1) -+ ACC
else (B:B + 1) -+ ACC
CALLING
SEQUENCE:
Macro
MAXX A,8
ENTRY
CONDITIONS: 0 <
= A < ,PI6, 171126; 0 < = 8 < = 126
EXIT
CONDITIONS: Accumulator contains maximum value of two double words; saturation
mode is reset
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
I
14 words
DATA
MEMORY
REQUIRED:
None
None
EXECUTION
TIME:
10 - 12 cycles
FLOWCHART: MAXX
COMPARE 1ST
ARGUMENT AND 2ND
ARGUMENT
LOAD 1ST
ARGUMENT INTO
ACC
LOAD 2ND
ARGUMENT INTO ACC
7-68
MAXX
MAXX
MAXX
SOURCE:
*SELECT MAX OF DOUBLE A OR B (VARIABLES)
*
MAXX
$MACRO A,B
SOVM
SET OVERFLOW MODE
LDAX :A:
LOAD :A:
SUBX :B:
COMPARE TO :B:
$VAR L,L1,L2
$ASG '$$LAB' TO L.S
$ASG L.SV+2 TO L.SV
UNIQUE LABEL
$ASG L.SV-1 TO L1.V
$ASG L.SV
TO L2.V
BGZ L$:L1.V:
BRANCH IF :A:>:B:
LDAX :B:
LOAD :B:
B
L$:L2.V:
TO CONTINUE
L$ : L1 . V: LDAX : A:
LOAD : A:
L$:L2.V: ROVM
CONTINUE
$END
EXAMPLE:
0013
0001
0002
0001
0002
0003
0001
0002
0004
0013 7F8B
0014 6500"
0015 6101"
0016
0017
0018
0019
6202"
6303"
FCOO
OOIE '
0005
0001 001A 6502"
0002 OOIB 6103"
0006 001C F900
OOID 0020 1
0007
L$3
0001 OOIE 6500"
0002 OOIF 6101"
0008 0020 7F8A L$4
MAXX C,D
SOVM
LDAX C
ZALH C
ADDS C+1
SUBX D
SUBH D
SUBS D+1
BGZ L$3
SET OVERFLOW MODE
LOAD C
LOAD HIGH C
LOAD LOW C
COMPARE TO D
SUBTRACT HIGH
SUBTRACT LOW
BRANCH IF C>D
LDAX D
ZALH D
ADDS D+1
B
L$4
LOAD D
LOAD HIGH D
LOAD LOW D
TO CONTINUE
LDAX C
ZALH C
ADDS C+1
ROVM
LOAD C
LOAD HIGH C
LOAD LOW C
CONTINUE
I
7-69
MIN
Select Minimum of Two Words -
TITLE:
Select Minimum of Two Words
NAME:
MIN
OBJECTIVE:
Load minimum of two words into accumulator
ALGORITH M:
If (A) < (B)
CALLING
SEQUENCE:
MIN A,B
ENTRY
CONDITIONS: 0 ~ A
~
Macro
then (A) -+ ACC
else (B) -+ ACC
127; 0 ~ B ~ 127
EXIT
CONDITIONS: Accumulator contains minimum value of two words
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
I
8 words
DATA
MEMORY
REQUIRED:
None
None
EXECUTION
TIME:
5 - 7 cycle
FLOWCHART: MIN
COMPARE 1ST
ARGUMENT AND 2ND
ARGUMENT
LOAD 1ST
ARGUMENT INTO
ACC
LOAD 2ND
ARGUMENT INTO ACC
7-70
MIN
MIN
MIN
SOURCE:
*SELECT MINUMUM OF SINGLE A OR B (VARIABLES)
*
MIN
$MACRO
A,B
LAC :A:,O
LOAD :A:
SUB :B:,O
COMPARE TO :B:
$VAR L,L1,L2
$ASG I$$LABI TO L.S
$ASG L.SV+2 TO L.SV
$ASG L.SV-1 TO L1.V
$ASG L.SV
TO L2.V
BLZ L$:L1.V:
BRANCH IF :A:<:B:
LAC :B:,O
LOAD :B:
B
L$:L2.V:
TO CONTINUE
L$:L1.V: LAC :A:,O
LOAD :A:
L$:L2.V: EQU $
CONTINUE
$END
EXAMPLE:
MIN A,B
0011
0001 0006 2007
LAC A,O
SUB B,O
0002 0007 1008
0003 0008 FAOO
BLZ L$l
0009 0000 1
0004 DaDA 2008
LAC B,O
B
L$2
0005 OOOB F900
OOOC OOOE I
LAC A,O
0006 OOOD 2007 L$1
OOOE I L$2 EQU $
0007
LOAD A
COMPARE TO B
BRANCH IF A
-I
ACC CONTAINS
DESTINATION; MOVE
ACC TO AR1
s:
o
<
o
»
--I
NO
YES
ACC CONTAINS
DESTINATION; MOVE
ACC TO AR1
LOAD AUX.
REG. TO ACC
LOAD SOURCE
ADDRESS TO
ACC
MOVE FIRST
WORD
MOVE TO RAM;
CALL MOVE$A
MOVE TO RAM;
CALL MOVE$$
MOVE TO RAM;
CALL MOVE$B
MOVE TO RAM;
CALL MOVE$B
YES
MOVE SECOND
WORD
so
<
C
~
I
00
-
l>
-I
MOVDAT
MOVDAT
SOURCE:
*MOVE L(CONST) WORDS FROM A(ROM ITEM)
*TO B(RAM VAR)
*ROM ITEM IS:
*
MOVDAT $MACRO A,B,L
$VAR ST
$ASG 1*1 TO ST.S
$IF B.L=O
ACTAR ARI
$ASG 1*1 TO B.S
$ENDIF
$IF L.V<3
$IF A.SV=ST.SV
ARTAC ARO
$ELSE
$IF A.L#=O
LCAC :A:
$ENDIF
$ENDIF
$IF B.SV=ST.SV
LARP 1
TBLR *+
$ELSE
TBLR :8:
$ENDIF
$IF L.V=2
ADD ONE,O
$IF B.SV=ST.SV
TBLR *+
$ELSE
TBLR :8:+1
$ENDIF
$ENDIF
$ENDIF
$IF L.V>2
$IF A.L=O
ACTAR ARO
$ASG 1*1 TO A.S
$ENDIF
$IF B.SV=ST.SV
$IF A.SV#=ST.SV
CALL MOVC$A
REF MOVC$A
DATA :A:
$ELSE
CALL MOVC$$
REF MOVC$$
$ENDIF
$ELSE
$IF A.SV#=ST.SV
CALL MOVA$B
REF MOVA$B
DATA :A:
$ELSE
CALL MOVC$B
REF MOVC$B
$ENDIF
DATA :8:
$ENDIF
DATA :L:
$ENDIF
SEND
I
7-82
ONE OR TWO WORDS
A= *
A = PROGRAM ADDRESS
READ FIRST WORD
TWO WORDS
INCREMENT POINTER
READ NEXT WORD
MOVE
FROM :A:
MOVE
MOVE
FROM :A:
MOVE
TO :B:
FOR :L: WORDS
MOVDAT
MOVDAT
EXAMPLE 1:
0012
0001
0001 0006 7E01
0002 0007 6708
MOVDAT A,B
LCAC A
LACK A
TBLR B
LOAD AC WITH A
EXAMPLE 2:
0014
0001
0001
0002
0002
0003
0004
0008
0009
OOOA
OOOB
OOOC
3004"
2004 11
6708
0002 11
6709
MOVDAT *,B,2
ARTAC ARO
SAR ARO,XRO
LAC XRO,O
TBLR B
ADD ONE,O
TBLR B+1
3004 11
2004 11
6881
67A8
0002 11
67A8
MOVDAT *,*,2
ARTAC ARO
SAR ARO,XRO
LAC XRO,O
LARP 1
TBLR *+
ADD ONE,O
TBLR *+
SAVE ARO
LOAD INTO AC
INCREMENT POINTER
EXAMPLE 3:
0016
0001
0001
0002
0002
0003
0004
0005
OOOD
OOOE
00 OF
0010
0011
0012
SAVE ARO
LOAD INTO AC
READ FIRST WORD
INCREMENT POINTER
READ NEXT WORD
EXAMPLE 4:
0018
0001 0013
0014
0002
0003 0015
0004 0016
F800
0000
DODO"
0008
HOVDAT C,*,B
CALL MOVC$A
REF MOVC$A
DATA C
DATA B
MOVE
I
FROM C
FOR B WORDS
EXAMPLE 5:
0020
0001
0001
0002
0003
0002
0017
0018
0019
001A
001B
5004 11
3904 11
6881
F800
0000
0003
0004 ODIC 0005
MOVDAT *,,5
ACTAR AR1
SACL XRO,O
LAR AR1,XRO
LARP AR1
CALL MOVC$$
REF MOVC$$
DATA 5
STORE AC TO XRO
RE-LOAD AR1
LOAD AR POINTER
MOVE
FOR 5 WORDS
EXAMPLE 6:
0022
0001 0010 6708
MOVDAT ,B
TBLR B
EXAMPLE 7:
0024
0001
0001
0002
0003
0002
ODIE
00 IF
0020
0021
0022
5004"
3804 11
6880
F800
0000
MOVDAT ,*,5
ACTAR ARO
SACL XRO,O
LAR ARO,XRO
LARP ARO
CALL MOVC$$
STORE AC TO XRO
RE-LOAD ARO
LOAD AR POINTER
MOVE
7-83
MOVDAT
MOVDAT
0003
0004 0023 0005
REF MOVC$$
DATA 5
FOR 5 WORDS
EXAMPLE 8:
0026
0001
0001 0024
0025
0002
0003 0026
0002 0027
0003 0028
F800
0000
0001"
6881
67A8
MOVDAT D,*
LCAC D
CALL LDAC$
REF LDAC$
DATA D
LARP 1
TBLR *+
LOAD AC WITH:
D
READ FIRST WORD
EXAMPLE 9:
0028
0001
0001
0002
0003
0002
0029
002A
002B
002C
002D
5004"
3904"
6881
F800
0000
0003
0004 002E 0001"
0005 002F 0003
MOVDAT D,,3
ACTAR AR1
SACL XRO,O
LAR AR1,XRO
LARP AR1
CALL MOVC$A
STORE AC TO XRO
RE-LOAD AR1
LOAD AR POINTER
MOVE
REF MOVC$A
DATA D
DATA 3
FROM D
FOR 3 WORDS
MOVDAT *,*
ARTAC ARO
SAR ARO,XRO
LAC XRO,O
LARP 1
TBLR *+
SAVE ARO
LOAD INTO AC
EXAMPLE 10:
0030
0001
0001
0002
0002
0003
I
0030
0031
0032
0033
3004"
2004"
6881
67A8
READ FIRST WORD
EXAMPLE 11:
0032
0001 0034 F800
0035 0000
0002
0003 0036 0009
7-84
MOVDAT *,*,9
CALL MOVC$$
REF MOVC$$
DATA 9
MOVE
FOR 9 WORDS
MOVE
Move Data Array -
TITLE:
Move Data Array
NAME:
MOVE
OBJECTIVE:
Copy data from one array to another in data memory.
ALGORITHM:
For number of elements in array,
(A[i]) - 8m
CALLING
SEQUENCE:
MOVE
Macro
MOVE A,B,length
ENTRY
CON DITIONS: 0
~
A
+
length ~ 143;0 ~ B
+
length ~ 143
EXIT
CONDITIONS: Elements of B contain corresponding elements of A;
ARO or AR1 may be overwritten
PROGRAM
MEMORY
REQUIRED:
5 - 7 words (+ MOV$ routines)
DATA
MEMORY
REQUIRED:
STACK
REQUIRED:
2 levels
EXECUTION
TIME:
1 - 3 words
(max) 29 + (7 x
length) cycles
I
7-85
MOVE
MUVE
FLOWCHART:
MOVE
MOVE SINGLEWORD SOURCE
TO DESTINATION
MOVE DOUBLEWORD SOURCE
TO
DESTINATION
CALL MOVAB$
TO PERFORM
TRANSFER
CALL MOVA$
TO PERFORM
TRANSFER
I
CALL MOVB$
TO PERFORM
TRANSFER
CALL MOV$$ TO
PERFORM TRANSFER
END
SOURCE:
*MOVE L(CONST) WORDS FROM A(RAM VAR)
*TO B(RAM VAR)
*
MOVE
7-86
$MACRO
A,B,L
$IF (L.V<2)&(B.L#=O)
MOV :A:,:B:
MOVE ,SINGLE
$ENDIF
$IF (L.V=2)&(B.L#=O)
MOVX :A:,:B:
MOVE DOUBLE
$ENDIF
MUVE
IVIUVI:.
$IF (L.V>2)++(B.L=0)
$VAR ST
$ASG 1*1 TO ST.S
$IF (A.L#=O)&(B.L#=O)
$IF (A.SV#=ST.SV)&(B.SV#=ST.SV)
CALL MOVAB$
MOVE
REF MOVAB$
FROM :A:
DATA :A:
TO :B:
DATA :B:
FOR :L.V: WORDS
DATA :L.V:
$ENDIF
$ENDIF
$IF (A.SV#=ST.SV)&(A.L#=O)
$IF (B.L=O)++(B.SV=ST.SV)
$IF B.L=O
AC TO AR1
ACTAR AR1
$ENDIF
MOVE
CALL MOVA$
REF MOVA$
FROM :A:
DATA :A:
FOR :L.V: WORDS
DATA :L.V:
$ENDIF
$ENDIF
$IF (B.SV#=ST.SV)&(B.L#=O)
$IF (A.L=O)++(A.SV=ST.SV)
$IF A.L=O
MOVE AC TO ARO
ACTAR ARO
$ENDIF
MOVE
CALL MOVB$
REF MOVB$
TO :B:
DATA :B:
FOR :L.V: WORDS
DATA :L.V:
$ENDIF
$ENDIF
$IF (A.L=O)++(A.SV=ST.SV)
$IF (B.L=O)++(B.SV=ST.SV)
$IF A.L=O
ACTAR ARO
AC TO ARO .
$ENDIF
$IF B.L=O
ACTAR AR1
AC TO AR1
$ENDIF
MOVE
CALL MOV$$
REF MOV$$
FOR :L.V: WORDS
DATA :L.V:
$ENDIF
$ENDIF
$ENDIF
$END
I
EXAMPLE 1:
0012
0001
0001 0006 2001
0002 0007 5008
MOVE
A,B
MOV A,B
LAC A,O
SACL B,O
MOVE SINGLE
LOAD A
STORE B
MOVE
*,B,2
MOVX *,B
LDAX *
ZALH *+
ADDS *-
MOVE
LOAD
LOAD
LOAD
EXAMPLE 2:
0014
0001
0001
0001 0008 65A8
0002 0009 6198
DOUBLE
DOUBLE *
HIGH
LOW 1*1
7-87
MOVE
MUVI:
0002
0001 OOOA 5808
0002 OOOB 5009
SACX B
SACH B,O
SACL B+1,0
STORE DOUBLE
STORE HIGH
STORE LOW
*
EXAMPLE 3:
0016
0001 OOOC
DODD
0002
0003 OOOE
0004 OOOF
F800
0000
0000 11
0008
MOVE
C,*,B
CALL MOVA$
REF MOVA$
DATA C
DATA 8
MOVE
FROM C
FOR 8 WORDS
EXAMPLE 4:
0018
0001
0001
0002
0003
0002
0010
0011
0012
0013
0014
5004 11
3904 11
6881
F800
0000
0003
0004 0015 0005
MOVE
*,,5
ACTAR AR1
SACL XRO,O
LAR ARl,XRO
LARP ARI
CALL MOV$$
REF MOV$$
DATA 5
AC TO AR1
STORE AC TO XRO
RE-LOAD ARI
LOAD AR POINTER
MOVE
FOR 5 WORDS
EXAMPLE 5:
0020
0001
0001
0002
0003
0004
0005
I
0016
0017
0018
0019
OOIA
5004 11
3804"
6880
2088
5008
MOVE
,B
MOV ,B
SACL XRO,O
LAR ARO,XRO
LARP ARO
LAC *,0
SACL B,O
MOVE SINGLE
SAVE AC
LOAD TO ARO
SELECT ARO
LOAD *
STORE B
MOVE
,*,5
ACTAR ARO
SACL XRO,O
LAR ARO,XRO
LARP ARO
CALL MOV$$
AC TO ARO
STORE AC TO XRO
RE-LOAD ARO
LOAD AR POINTER
MOVE
EXAMPLE 6:
0022
0001
0001
0002
0003
0002
OOIB
OOIC
OOID
DOlE
OOIF
5004 11
3804"
6880
F800
0000
0003
0004 0020 0005
REF MOV$$
DATA 5
FOR 5 WORDS
EXAMPLE 7:
0024
0001
0001 0021 2001"
0002 0022 5088
MOVE
D,*
MOV D,*
LAC D,O
SACL *,0
MOVE SINGLE
LOAD D
STORE *
MOVE
D, ,3
ACTAR ARI
SACL XRO,O
LAR ARl,XRO
LARP ARI
CALL MOVA$
AC TO AR1
STORE AC TO XRO
RE-LOAD ARI
LOAD AR POINTER
MOVE
EXAMPLE 8:
0026
0001
0001
0002
0003
0002
7-88
0023
0024
0025
0026
5004"
3904 11
6881
F800
MOVE
MOVE
0027 0000
0003
0004 0028 0001 11
0005 0029 0003
REF MOVA$
DATA D
DATA 3
FROM D
FOR 3 WORDS
I
7-89
MOVROM
TITLE:
Move Words to Program Memory
NAME:
MOVROM
OBJECTIVE:
Copy data from data memory to program memory
ALGORITHM:
For number of elements in array,
CALLING
SEQUENCE:
Macro
MOVROM
MOVROM
MOVROM
A,B,C - causes- (A)-@B
A, * ,C - causes- (A) -@AR1
A, ,C - causes- (A)-@ACC
MOVROM
MOVROM
MOVROM
*,B,C - causes- (@ARO)-@B
*, * ,C - causes- (@ARO) - @AR1
*, ,C - causes- (@ARO) - @ACC
MOVROM
MOVROM
,B,C - causes- (@ACC)-@B
, *,C - causes- (@ACC) - @AR1
MOVROM
MOVROM [A, *1,[B, *][,Iengthl
ENTRY
CONDITIONS: 0
I
Move Words to Program Memory -
~
A
+
length ~ 143; 0
~
B ~ 4095
EXIT
CONDITIONS: Program memory starting at B contains data elements starting at A; ARO
and AR1 may be overwritten
PROGRAM
MEMORY
REQUIRED:
8 words (+ TBW$ routines)
DATA
MEMORY
REQUIRED:
STACK
REQUIRED:
2 levels
EXECUTION
TIME:
7-90
3 words
(max) 31 + (7 x
length) cycles
MOVROM
FLOWCHART:
MOVROM
MOVROM
LENGTH = 1
ACC POINTS TO
SOURCE; MOVE
ACC TO ARO
ACC POINTS TO
DESTINATION; MOVE
ACC TO AR1
MOVE DATA TO
PROGRAM MEMORY;
CALL TBW$O
YES
YES
MOVE DATA TO
PROGRAM MEMORY;
CALL TBW$$
MOVE DATA TO
PROGRAM MEMORY;
CALL TBW$01
MOVE DATA TO
PROGRAM MEMORY;
CALL TBW$1
SOURCE:
*MOVE L(CONST) WORDS FROM A(RAM VAR)
*TO B(ROM VAR)
*
MOVROM $MACRO A,B,L
$VAR 5T
$A5G 1*1 TO 5T.5
$IF L.V=O
$ASG 1 TO L.V
$ENDIF
$IF A.L=O
ACTAR ARO
$ENDIF
$IF B.L=O
DEFAULT 0 TO 1
AC TO ARO
7-91
I
MOVROM
MOVROM
ACTAR AR1
AC TO AR1
$ENDIF
$IF (B.SV=ST.SV)++(B.L=O)
$IF (A.SV=ST.SV)++(A.L=O)
CALL TBW$Ol
MOVE RAM->ROM
REF TBW$Ol
DATA :L.V:
FOR :L.V: WORDS
$ELSE
CALL TBW$l
MOVE RAM->ROM
REF TBW$l
DATA :A:
FROM :A:
DATA :L.V:
FOR :L.V: WORDS
$ENDIF
$ELSE
$IF (A.SV=ST.SV)++(A.L=O)
CALL TBWSO
MOVE RAM->ROM
REF TBW$O
DATA :B:
TO :B:
DATA :L.V:
FOR :L.V: WORDS
$ELSE
CALL TBW$$
MOVE RAM->ROM
REF TBW$$
DATA :A:
FROM :A:
DATA :B:
TO :B:
DATA :L.V:
FOR :L.V: WORDS
$ENDIF
$ENDIF
$END
EXAMPLE 1:
0012
0001 0006
0007
0002
0003 0008
0004 0009
0005 OOOA
I
F800
0000
0001
0008
0001
MOVROM A,B
CALL TBW$$
REF
DATA
DATA
DATA
TBW$$
A
B
1
MOVE RAl-t - >ROM
FROM A
TO B
FOR 1 WORDS
EXAMPLE 2:
0014
0001 OOOB
OOOC
0002
0003 0000
0004 OOOE
F800
0000
0008
0002
MOVROM *,B,2
CALL TBW$O
REF TBW$O
DATA B
DATA 2
MOVE RAM->ROM
TO 8
FOR 2 WORDS
EXAMPLE 3:
0016
0001 OOOF
0010
0002
0003 0011
0004 0012
F800
0000
0000"
0008
MOVROM C,*,B
CALL TBW$l
REF TBW$l
DATA C
DATA 8
MOVE RAM->ROM
FROM C
FOR 8 WORDS
EXAMPLE 4:
0018
0001
0001 0013 5004"
0002 0014 3904"
7-92
MOVROM
ACTAR
SACL
LAR
*,,5
AR1
XRO,O
AR1,XRO
AC TO AR1
STORE AC TO XRO
RE-LOAD AR1
MOVROM
MOVROM
0003 0015 6881
0002 0016 F800
0017 0000
0003
0004 0018 0005
LARP AR1
CALL TBW$Ol
LOAD AR POINTER
MOVE RAM->ROM
REF TBW$Ol
DATA 5
FOR 5 WORDS
EXAMPLE 5:
0020
0001
0001
0002
0003
0002
0019
001A
001B
001C
0010
5004 11
3804 11
6880
F800
0000
0003
0004 DOlE 0008
0005 001F 0001
MOVROM ,B
ACTAR ARO
SACL XRO,O
LAR ARO,XRO
LARP ARO
CALL TBW$O
REF TBW$O
DATA B
DATA 1
AC TO ARO
STORE AC TO XRO
RE-LOAD ARO
LOAD AR POINTER
MOVE RAM->ROM
TO B
FOR 1 WORDS
EXAMPLE 6:
0022
0001
0001
0002
0003
0002
0020
0021
0022
0023
0024
5004 11
3804"
6880
F800
0000
0003
0004 0025 0005
MOVROM ,*,5
ACTAR ARO
SACL XRO,O
LAR ARO,XRO
LARP ARO
CALL TBW$Ol
REF TBW$Ol
DATA 5
AC TO ARO
STORE AC TO XRO
RE-LOAD ARO
LOAD AR POINTER
MOVE RAM->ROM
FOR 5 WORDS
EXAMPLE 7:
0024
0001 0026
0027
0002
0003 0028
0004 0029
F800
0000
0001"
0001
MOVROM D,*
CALL TBW$l
REF TBW$l
DATA D
DATA 1
MOVE RAM->ROM
I
FROM D
FOR 1 WORDS
EXAMPLE 8:
0026
0001
0001
0002
0003
0002
002A
002B
002C
002D
002E
5004"
3904"
6881
F800
0000
0003
0004 002F 0001"
0005 0030 0003
MOVROM D,,3
ACTAR AR1
SACL XRO,O
LAR AR1,XRO
LARP AR1
CALL TBW$l
REF TBW$l
DATA D
DATA 3
AC TO AR1
STORE AC TO XRO
RE-LOAD AR1
LOAD AR POINTER
MOVE RAM->ROM
FROM D
FOR 3 WORDS
EXAMPLE 9:
0028
0001 0031 F800
0032 0000
0002
0003 0033 0001
MOVROM *,*
CALL TBW$Ol
REF TBW$Ol
DATA 1
MOVE RAM->ROM
FOR 1 WORDS
7-93
MOVROM
MOVROM
EXAMPLE 10:
0030
0001 0034 F800
0035 0000
0002
0003 0036 0001
I
7-94
MOVROM *,*,1
CALL TBW$01
MOVE RAM->ROM
REF
TBW$01
DATA 1
FOR 1 WORDS
MOVX
Move Double Word -
MOVX
Macro
TITLE:
Move Double Word
NAME:
MOVX
OBJECTIVE:
Copy double word from one location to another in data memory
ALGORITHM:
(A:A + 1) ~ B:B + 1 or
(@ACC:@ACC + 1 ) ~ B: B + B
CALLING
SEQUENCE:
MOVX [ALB
ENTRY
CONDITIONS: 0 ~ A
~
126;0
~
B ~ 126
EXIT
CONDITIONS: Double word at B contains value of double word located at A; ARO may
be overwritten
PROGRAM
MEMORY
REQUIRED:
4 - 8 words
DATA
MEMORY
REQUIRED:
0 - 2 words
STACK
REQUIRED:
None
EXECUTION
TIME:
4 - 8 cycles
FLOWCHART:
MOVX
NO
LOAD DOUBLEWORD SOURCE
INTO ACC
I
MOVE ACC TO
AUX. REGISTER
LOAD Ace WITH
DOUBLE WORD
POINTED TO BY
AUX. REGISTER
STORE DOUBLE WORD
OF ACC INTO
DESTINATION
7-95
MOVX
MOVX
SOURCE:
*MOVE DOUBLE FROM A TO B
*
MOVX
$MACRO
A,B
MOVE DOUBLE
$IF A.L=O
A IN AC
SACH XRO,O
SACL XR1,0
SAVE AC TO XRO
TO ARO
LAR ARO,XRO
LARP ARO
SELECT ARO
LOAD *
LDAX *
$ELSE
LOAD DOUBLE :A:
LDAX :A:
$ENDIF
SACX :B:
STORE DOUBLE :A:
$END
EXAMPLE 1:
0011
0001
0001
0002
0002
0001
0002
0006 6501
0007 6102
0008 5808
0009 5009
MOVX
A,B
LDAX A
ZALH A
ADDS A+1
SACX B
SACH B,O
SACL B+1,0
LOAD DOUBLE A
LOAD HIGH A
LOAD LOW A
STORE DOUBLE A
STORE HIGH
STORE LOW
MOVX
*,B
LDAX *
ZALH *+
ADDS *SACX B
SACH B,O
SACL B+1,0
LOAD DOUBLE *
LOAD HIGH
LOAD LOW ,*,
STORE DOUBLE *
STORE HIGH
STORE LOW
HOVX
C,*+
LDAX C
ZALH C
ADDS C+1
SACX *+
SACH *+,0
SACL *+,0
LOAD DOUBLE C
LOAD HIGH C
LOAD LOW C
STORE DOUBLE C
STORE HIGH
STORE LOW
MOVX
,D
SACH XRO,O
SACL XR1,0
LAR ARO,XRO
LARP ARO
LDAX *
ZALH *+
ADDS *SACX D
SACH D,O
SACL 0+1,0
SAVE AC TO XRO
TO ARO
SELECT ARO
LOAD *
LOAD HIGH
LOAD LOW '*'
STORE DOUBLE
STORE HIGH
STORE LOW
EXAMPLE 2:
0013
0001
0001
0002
0002
0001
0002
I
OOOA 65A8
OOOB 6198
OOOC 5808
0000 5009
EXAMPLE 3:
0015
0001
0001
0002
0002
0001
0002
OOOE 6500"
OOOF 6101"
0010 58A8
0011 50A8
EXAMPLE 4:
0017
0001
0002
0003
0004
0005
0001
0002
0006
0001
0002
7-96
0012
0013
0014
0015
5806"
5007 11
3806 11
6880
0016 65A8
0017 6198
0018 5802 11
0019 5003 11
MOVX
MOVX
EXAMPLE 5:
0019
0001
0001
0002
0002
0001
0002
001A 6698
001B 6098
001C 5808
001D 5009
MOVX
*-,B
LDAX *ZALS *ADDH *SACX B
SACH B,O
SACL B+1,O
LOAD DOUBLE *LOAD LOW
LOAD HIGH 1*_1
STORE DOUBLE *STORE HIGH
STORE LOW
MOVX
*+,A
LDAX *+
ZALH *+
ADDS *+
SACX A
SACH A,O
SACL A+1,O
LOAD DOUBLE *+
LOAD HIGH
LOAD LOW 1*+1
STORE DOUBLE *+
STORE HIGH
STORE LOW
MOVX
D,*LDAX D
ZALH D
ADDS D+1
SACX *SACL *-,0
SACH *-,0
LOAD DOUBLE D
LOAD HIGH D
LOAD LOW D
STORE DOUBLE D
STORE LOW
STORE HIGH
EXAMPLE 6:
0021
0001
0001
0002
0002
0001
0002
ODIE 65A8
001F 61A8
0020 5801
0021 5002
EXAMPLE 7:
0023
0001
0001
0002
0002
0001
0002
0022 6502"
0023 6103"
0024 5098
0025 5898
I
7-97
NEG
Arithmetic Negation -
TITLE:
Arithmetic Negation
NAME:
NEG
OBJECTIVE:
Find negative value of argument
ALGORITHM:
- (A)
CALLING
SEQUENCE:
NEG A
ENTRY
CONDITIONS: 0 ~ A
NEG
Macro
~A
~
127
EXIT
CONDITIONS: Data word A contains the negative of its previous value
PROGRAM
MEMORY
REQUIRED:
3 words
DATA
MEMORY
REQUIRED:
None
STACK
REQUIRED:
None
EXECUTION
TIME:
3 cycles
FLOWCHART:
NEG
I
ZERO ACC
SUBTRACT A
FROM ACC
SAVE A
SOURCE:
*NEGATE VAR A
*
NEG
7-98
$MACRO A
ZAC
SUB :A:, 0
SACL :A: ,a
$END
NEGATE
ZERO AC
SUBTRACT :A:
RESTORE
NEG
NEG
EXAMPLE:
0015
0001 OOOC 7F89
0002 OOOD 1001 11
0003 OOOE 5001 11
NEG D
ZAC
SUB D,O
SACL D,O
ZERO AC
SUBTRACT D
RESTORE
I
7-99
NEGX
Double-Word Arithmetic Negation -
TITLE:
Double-Word Arithmetic Negation
NAME:
NEGX
OBJECTIVE:
Find negative value of double-word argument
ALGORITHM:
NEGX *
- causes-+
NEGX * - - causes-+
NEGX *
NEGX A
CALLING
SEQUENCE:
+-
causes-+
- causes-+
NEGX {A,*,* -,*
ENTRY
CONDITIONS: 0 ~ A
~
Macro
- (@AR:@AR + 1) -+@AR + 1
- (@AR - 1 :@AR) -+ @AR - 1 :@AR
(AR) - 2 -+ AR
- (@AR:@AR + 1) -+ @AR:@AR + 1
(AR) + 2 -+ AR
- (A:A + 1) -+ A:A + 1
+}
127
EXIT
CONDITIONS: Specified data words contain negative of previous value; auxiliary register
is updated as necessary
I
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
7-100
5 words
DATA
MEMORY
REQUIRED:
None
None
EXECUTION
TIME:
5 cycles
NEGX
NEGX
NEGX
FLOWCHART: NEGX
YES
NEGATE (a)AR
AND @AR+1
"'EGA TE (a)AR
AND @AR+1
NEGATE (a)AR
AND @AR+ 1
YES
NEGATE
A AND A+1
I
SOURCE:
*NEGATE DOUBLE WORD
*
NEGX
$MACRO A
$VAR ST,SP,SM
$ASG 1*+1 TO SP.S
$ASG 1*_1 TO SM.S
$ASG 1*1 TO ST.S
ZAC
$IF A.SV=SM.SV
SUBS *SUBH *+
SACX *$ELSE
$IF A.SV=SP.SV
SUBX *
SACX *+
$ELSE
$IF A.SV=ST.SV
SUBX *
SACX *
$ELSE
SUBX :A:
SACX :A:
$ENDIF
$END
NEGATE DOUBLE
SUBTRACT 1*_1
SAVE 1*_1
SUBTRACT 1*1
SAVE 1*+1
SUBTRACT
SAVE 1*1
1*1
SUBTRACT
SAVE :A:
:A:
7-101
NEGX
NEGX
EXAMPLE 1:
0011
0001
0002
0001
0002
0003
0001
0002
0006 7F89
0007 6207
0008 6308
0009 5807
OOOA 5008
NEGX A
ZAC
SUBX A
SUBH A
SUBS A+1
SACX A
SACH A,O
SACL A+1,0
SUBTRACT A
SUBTRACT HIGH
SUBTRACT LOW
SAVE A
STORE HIGH
STORE LOW
NEGX *
ZAC
SUBX *
SUBH *+
SUBS *SACX *
SACH *+,0
SACL *-,0
SUBTRACT '*'
SUBTRACT HIGH
SUBTRACT LOW
SAVE '*'
STORE HIGH
STORE LOW
NEGX *ZAC
SUBS *SUBH *+
SACX *SACL *-,0
SACH *-,0
SUBTRACT '*-'
SAVE '*-'
STORE LOW
STORE HIGH
NEGX *+
ZAC
SUBX *
SUBH *+
SUBS *SACX *+
SACH *+,0
SACL *+,0
SUBTRACT ,*,
SUBTRACT HIGH
SUBTRACT LOW
SAVE ,*+,
STORE HIGH
STORE LOW
EXAMPLE 2:
0013
0001
0002
0001
0002
0003
0001
0002
OOOB 7F89
OOOC 62A8
0000 6398
OOOE 58A8
OOOF 5098
EXAMPLE 3:
0015
0001
0002
0003
0004
0001
0002
I
0010 7F89
0011 6398
0012 62A8
0013 5098
0014 5898
EXAMPLE 4:
0017
0001
0002
0001
0002
0003
0001
0002
7-102
0015 7F89
0016 62A8
0017 6398
0018 58A8
0019 SOA8
NOT
Boolean Not -
NOT
Macro
TITLE:
Boolean Not
NAME:
NOT
OBJECTIVE:
Calculate one's complement of accumulator or data word
ALGORITHM:
(A) .XOR. - 1 -+ A
CALLING
SEQUENCE:
NOT [AJ
ENTRY
CONDITIONS: 0 ~ A
~
127
EXIT
CONDITIONS: A (accumulator) contains one's complement of previous value
PROGRAM
MEMORY
REQUIRED:
3 words
DATA
MEMORY
REQUIRED:
1 word
STACK
REQUIRED:
None
EXECUTION
TIME:
1 - 3 cycles
FLOWCHART:
NOT
NO
INVERT ACC
LOAD ACC
WITH A
INVERT ACC
SAVE A
7-103
NOT
NOT
SOURCE:
*NOT AC OR WORD A
*
NOT
$MACRO A
$IF A.L#=O
LAC :A: ,0
XOR MINUS
SACL :A: ,0
$ELSE
XOR MINUS
$ENDIF
$END
INVERT
LOAD AC
INVERT
RESTORE
INVERT
EXAMPLE 1:
0011
0001 0006 7803"
NOT
XOR
MINUS
INVERT
EXAMPLE 2:
0017
0001 0000 2000"
0002 00 DE 7803"
0003 OOOF 5000"
I
7-104
NOT C
LAC C,O
XOR MINUS
SACL C,O
LOAD AC
INVERT
RESTORE
RASH
Arithmetic Right Shift -
RASH
Macro
TITLE:
Arithmetic Right Shift
NAME:
RASH
OBJECTIVE:
Move shifted data from one location to another in data memory
ALGORITHM:
(A) * 2 -shift-+ B
CALLING
SEQUENCE:
RASH A,B,shift
ENTRY
CONDITIONS: 0 ~ A
~
127; 0
~
B ~ 127; 0
~
shift < 16
EXIT
CONDITIONS: B contains shifted value of A
2 words
DATA
MEMORY
REQUIRED:
None
STACK
REQUIRED:
None
EXECUTION
TIME:
2 cycles
FLOWCHART:
RASH
PROGRAM
MEMORY
REQUIRED:
I
LOAD ACC WITH
A, SHIFTED 16-N
SAVE ACC HIGH
IN B
SOURCE:
*MOVE A TO B (SINGLE-VAR) WITH N (CONST) BIT
*RIGHT ARITHMETIC SHIFT
*
RASH
$MACRO A,B,N
LAC : A: , 16 - : N:
SACH :B: ,0
$END
MOVE WITH RIGHT ARITH. SHIFT
LOAD :A: RIGHT SHIFT
STORE HIGH TO :B:
7-105
RASH
RASH
EXAMPLE:
0011
0001 0006 2D07
0002 0007 5808
I
7-106
RASH A,B,3
LAC A,16-3
SACH B,O
LOAD A RIGHT SHIFT
STORE HIGH TO B
RASX
Double-Word Arithmetic Right Shift -
Macro
TITLE:
Double-Word Arithmetic Right Shift
NAME:
RASX
OBJECTIVE:
Move shifted double word from one location to another in data memory
ALGORITHM:
(A:A + 1) * 2s hift-. B:B
CALLING
SEQUENCE:
RASX A, B ,shift
ENTRY
CONDITIONS: 0 ~ A
~
126; 0
~
+
RASX
1
B ~ 126; 0 ~ shift < 16
EXIT
CONDITIONS: Double word at B contains shifted value of double word at A
PROGRAM
MEMORY
REQUIRED:
10 words
DATA
MEMORY
REQUIRED:
1 word
STACK
REQUIRED:
None
EXECUTION
TIME:
10 cycles
FLOWCHART:
RASX
(
I
,
BEGIN)
,
,
,
,
SHIFT RIGHT A + 1
TO B + 1, LOGICAL
LOAD ACC WITH A,
SHIFTED 16-N
SAVE ACC HIGH
IN B
ADD ACC LOW
TO B+1
(
END
)
SOURCE:
*MOVE A TO B (DOUBLE VAR) WITH N (CONST) BIT
*RIGHT ARITHMETIC SHIFT
*
RASX
$MACRO
A,B,N
MOVE DOUBLE WITH ARITH. SHIFT
7-107
RASX
RASX
RLSH
LAC
SACH
OR
SACL
$END
:A:+1, :B :+1,
:A:,16-:N:
:B:,O
:B:+1
:B:+1,0
:N:
LOAD HIGH, RIGHT SHIFT
SAVE IN :B: HIGH
COMBINE WITH :B: LOW
SAVE BACK
EXAMPLE:
0011
0001
0001
0002
0003
0004
0001
0005
0006
0002
0003
0004
0005
I
7-108
0006 2008
0007 580A
0008 2D03 11
0009
OOOA
OOOB
OOOC
0000
OOOE
OOOF
7803 11
790A
500A
2007
5809
7AOA
500A
RASX A,B,3
RLSH A+1,B+l,3
LAC A+1,16-3
SACH B+1,0
LAC MINUS,16-3
NOT
XOR MINUS
AND B+1
SACL B+1,O
LAC A,16-3
SACH B,O
OR
B+1
SACL B+1,O
LOAD, RIGHT SHIFT
SAVE HIGH PART
GET MASK
INVERT
APPLY MASK
STORE BACK TO B+1
LOAD HIGH, RIGHT SHIFT
SAVE IN B HIGH
COMBINE WITH BLOW
SAVE BACK
REPCON
Move One-Word Constant into Array -
TITLE:
Move One-Word Constant into Array
NAME:
REPCON
OBJECTIVE:
Initialize an array in data memory with a constant
ALGORITHM:
Constant ... ACC
For number of elements in array,
(ACC) ... data memory
CALLING
SEQUENCE:
REPCON constant,arraY,length
ENTRY
CONDITIONS:
- 32768
~
constant ~ 32767; 0
~
array
+
Macro
REPCON
length ~ 143
EXIT
CONDITIONS: Array contains constant in each location
PROGRAM
MEMORY
REQUIRED:
DATA
MEMORY
REQUIRED:
2 - 4 words (+ SETS$ and
LAC$ routines)
STACK
REQUIRED:
2 levels
FLOWCHART:
REPCON
EXECUTION
TIME:
YES
CALL SETS$ FOR
MULTIPLE WORDS
a-
3 words
(max) 27 + (4 x
length) cycles
I
LOAD CONSTANT
INTO ACC
PLACE VALUE
IN ACC INTO
DESTINATION
7-109
REPCON
REPCON
SOURCE:
*REPLICATE CONSTANTS
*A IS A CONSTANT
*B IS A MEM LOCATION
*L IS LENGTH TO REPLICATE
*
REP CON $MACRO A,B,L
$IF L.V<2
LCAC :A:
SACL :B: ,0
$ELSE
CALL SETS$
REF SETS$
DATA :A:
DATA :L:
DATA :B:
$ENDIF
$END
LOAD CONSTANT
SET IT
CALL FOR SET MEMORY
CONSTANT
LENGTH
DESTINATION
EXAMPLE 1:
0014
0001 00 DB
OOOC
0002
0003 DODD
0004 OOOE
0005 00 OF
F800
0000
FF04
OOOA
0001
REPCON -252,A,10
CALL SETS$
REF
DATA
DATA
DATA
SETS$
-252
10
A
CALL FOR SET MEMORY
CONSTANT
LENGTH
DESTINATION
EXAMPLE 2:
0016
0001
0001
0002
0002 0010 7E02
0002 0011 5008
I
7-110
REP CON 2,B,1
LCAC 2
V$l EQU 2
LACK V$l
SACL B,O
LOAD CONSTANT
LOAD AC WITH V$l
SET IT
RIPPLE
Ripple Data Array One Position -
Macro
TITLE:
Ripple Data Array One Position
NAME:
RIPPLE
OBJECTIVE:
Move each element of array in data memory to next higher location
ALGORITHM:
(array element N - 1) -- array element N
(array element N - 2) -- array element N-1
RIPPLE
(array element 2) -- array element 3
(array element 1 ) -- array element 2
CALLING
SEQUENCE:
RIPPLE array [,lengthLinline]]
ENTRY
CONDITIONS: 0 ~ array + length ~ 143; inline
= any string
EXIT
CONDITIONS: All array elements N contain value of previous location N - 1; ARO and
AR1 may be overwritten
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
Inline - length words;
looped - 4 + RIP$ function
(23 words)
2 levels (looped)
DATA
MEMORY
REQUIRED:
EXECUTION
TIME:
I
3 words
Inline - length
cycles; looped 30 + (4 * length)
7-111
RIPPLE
RIPPLE
FLOWCHART: RIPPLE
CALL RIP$ FOR
LOOPED VERSION OF
DATA SHIFT
DECREMENT
ARRAY LENGTH
SOURCE 1:
I
RIPPLE $MACRO A,L,C
$IF (L.V<4)++(C.L#=O)
INRIP :A:,:L:
$ELSE
CALL RIP$
CALL FOR RIPPLE LOOP
REF RIP$
DATA :L:
FaR :L: -1 WORDS
DATA :A:
FROM :A:+:L:-l
$ENDIF
$END
SOURCE 2:
*RIPPLE DOWN ARRAY
*A IS ARRAY LOCATION
*L IS LENGTH OF ARRAY
*INRIP
7-112
$MACRO A,L
$IF L.V>16
INRIP :A:+16, :L:-16
$ENDIF
$IF L.V>15
DMOV :A:+15
$ENDIF
$IF L.V>14
DMOV :A:+14
$ENDIF
$IF L.V>13
DMOV :A:+13
$ENDIF
$IF L.V>12
RIPPLE
RIPPLE
DMOV :A:+12
$ENDIF
$IF L.V>ll
DMOV :A:+ll
$ENDIF
$IF L.V>lO
DMOV :A:+lO
$ENDIF
$IF L.V>9
DMOV :A:+9
$ENDIF
$IF L.V>B
DMOV :A:+B
$ENDIF
$IF L.V>7
DMOV :A:+7
$ENDIF
$IF L.V>6
DMOV :A:+6
$ENDIF
$IF L.V>S
DMOV :A:+S
$ENDIF
$IF L.V>4
DMOV :A:+4
$ENDIF
$IF L.V>3
DMOV :A:+3
$ENDIF
$IF L.V>2
DMOV :A:+2
$ENDIF
$IF L.V>l
DMOV :A:+l
$ENDIF
$IF L.V>O
DMOV :A:
$ENDIF
$END
I
EXAMPLE 1:
0007
0001
0001 0006 6909
0002 0007 690B
0003 OOOB 6907
RIPPLE
INRIP
DMOV
DMOV
DMOV
A,3
A,3
A+2
A+1
A
EXAMPLE 2:
0009
0001 0009
OOOA
0002
0003 OOOB
0004 oooe
F800
0000
0004
0007
RIPPLE A,4
CALL RIP$
REF RIP$
DATA 4
DATA A
CALL FOR RIPPLE LOOP
FOR 4-1 WORDS
FROM A+4-1
EXAMPLE 3:
0011
0001
0001 DODD 690B
0002 OOOE 690A
RIPPLE
INRIP
DMOV
DMOV
A,S,L
A,S
A+4
A+3
7-113
RIPPLE
RIPPLE
0003 OOOF 6909
0004 0010 6908
0005 0011 6907
I
7-114
DMOV A+2
DMOV A+1
DMOV A
RLSH
Right Logical Shift -
RLSH
Macro
TITLE:
Right Logical Shift
NAME:
RLSH
OBJECTIVE:
Move right-shifted data from one location to another in data memory
ALGORITHM:
[(A) * 2 -shift] .and. [216-shift-1]
CALLING
SEQUENCE:
RLSH A,B,shift
ENTRY
CONDITIONS: 0 ~ A
~
-+
B
127; 0 ~ B ~ 127; 0 ~ shift < 16
EXIT
CONDITIONS: B contains shifted value of A
PROGRAM
MEMORY
REQUIRED:
6 words
DATA
MEMORY
REQUIRED:
1 word
STACK
REQUIRED:
None
EXECUTION
TIME:
6 cycles
FLOWCHART:
RLSH
I
(
BEGIN)
~
LOAD ACC WITH A,
SHIFTED 16-N
~
SAVE ACC HIGH
IN B
~
,
REMOVE SIGN
EXTENSION IN B
(
END
J
SOURCE:
*MOVE A TO B (SINGLE VAR) WITH N (CONST) BIT
*RIGHT LOGICAL SHIFT
*
RLSH
$MACRO A,B,N
LAC :A:,16-:N:
SACH :B:,O
MOVE WITH RIGHT LOGICAL SHIFT
LOAD, RIGHT SHIFT
SAVE HIGH PART
7-115
RLSH
RLSH
LAC MINUS,16-:N: GET MASK
NOT
ANO : B :
APPLY MASK
SACL :B:,O
STORE BACK TO :B:
$END
EXAMPLE:
0011
0001
0002
0003
0004
0001
0005
0006
I
7-116
0006 2007
0007 5808
0008 2003 11
0009 7803 11
OOOA 7908
OOOB 5008
RLSH A,B,3
LAC A,16-3
SACH B,O
LAC MINUS,16-3
NOT
XOR MINUS
AND
B
SACL B,O
LOAD, RIGHT SHIFT
SAVE HIGH PART
GET MASK
INVERT
APPLY MASK
STORE BACK TO B
RLSX
Double-Word Logical Right Shift -
Macro
TITLE:
Double-Word Logical Right Shift
NAME:
RLSX
OBJECTIVE:
Move right-shifted double word from one location to another in data
memory
ALGORITHM:
[(A:A
CALLING
SEQUENCE:
RLSX A,B,shift
ENTRY
CONDITIONS: 0 ~ A
+
~
1) * 2 - shift].and.[2 16 - shift -1]--' B:B
126; 0
~
B ~ 126; 0
+
RLSX
1
shift < 16
~
EXIT
CONDITIONS: Double word at B contains shifted value of double word at A
PROGRAM
MEMORY
REQUIRED:
14 words
DATA
MEMORY
REQUIRED:
1 word
STACK
REQUIRED:
None
EXECUTION
TIME:
14 cycles
FLOWCHART:
RLSX
(
,
BEGIN
I
J
SHIFT RIGHT A + 1
TO B + 1 LOGICAL
I
~
LOAD ACC WITH A,
SHIFTED 16-N
~
SAVE ACC HIGH
IN B
~
,
ADD ACC LOW
TO B+1
ZERO-EXTENDED
SIGN IN B
(
-'
END
)
7-117
RLSX
RLSX
SOURCE:
*MOVE A TO B (DOUBLE VAR) WITH N(CONST) BIT
*RIGHT LOGICAL SHIFT
*
RLSX
$MACRO A,B,N
RLSH :A:+1, :B:+1,
LAC :A:,16-:N:
SACH :B:,O
OR
:B:+1
SACL :B:+1,O
LAC MINUS,16-:N:
NOT
AND :B:
SACL :B:,O
$END
MOVE DOUBLE WITH LOGICAL SHIFT
:N: SHIFT RIGHT LOWER
GET UPPER (RIGHT SHIFT)
SAVE IN :B: HIGH
COMBINE LOW PARTS
SAVE IN :B: LOW
GET MASK
MASK HIGH :B:
SAVE BACK IN :B:
EXAMPLE:
0011
0001
0001
0002
0003
0004
0001
0005
0006
0002
0003
0004
0005
0006
0007
0001
0008
0009
I
7-118
0006 2008
0007 580A
0008 2005"
0009
OOOA
OOOB
OOOC
0000
OOOE
OOOF
0010
7805"
790A
500A
2007
5809
7AOA
500A
2005 11
0011 7805 11
0012 7909
0013 5009
RLSX A,B,3
RLSH A+1,B+1,3
LAC A+1,16-3
SACH B+1,0
LAC MINUS,16-3
NOT
XOR MINUS
AND B+1
SACL B+1,0
LAC A,16-3
SACH B,O
OR
B+1
SACL B+1,0
LAC MINUS,16-3
NOT
XOR MINUS
AND B
SACL B,O
SHIFT RIGHT LOWER
LOAD, RIGHT SHIFT
SAVE HIGH PART
GET MASK
INVERT
APPLY MASK
STORE BACK TO B+1
GET UPPER (RIGHT SHIFT)
SAVE IN B HIGH
COMBINE LOW PARTS
SAVE IN BLOW
GET MASK
INVERT
MASK HIGH B
SAVE BACK IN B
SACX
Store Double Word -
TITLE:
Store Double Word
NAME:
SACX
OBJECTIVE:
Store double word from accumulator
ALGORITHM:
SACX *
- causes-+ (ACC) -+ @AR:@AR + 1
SACX * -
- causes-+ (ACC) -+ @AR-1 :@AR
(AR) - 2 -+ AR
SACX *
+
causes-+ (ACC) -+ @AR:@AR + 1
(AR) + 2 -+ AR
- causes-+ (ACC) -+ A:A + 1
SACX A
CALLING
SEQUENCE:
-
SACX {A,*,* -,* +
ENTRY
CONDITIONS: 0 ~ A
~
SACX
Macro
}
127
EXIT
CONDITIONS: Specified double word contains value from accumulator;
auxiliary register is updated if necessary
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
I
2 words
DATA
MEMORY
REQUIRED:
None
None
EXECUTION
TIME:
2 cycles
7-119
SACX
SACX
FLOWCHART: SACX
STORE TO @AR
AND @AR+1
YES
STORE TO @AR
AND @AR+ 1
YES
YES
STORE TO A AND A+ 1
I
SOURCE:
*STORE DOUBLE
*
SACX
7-120
$MACRO A
$VAR ST,SP,SM
$ASG 1*1 TO ST.S
$ASG 1*_1 TO SM.S
$ASG 1*+1 TO SP~S
$IF A.SV=ST.SV
SACH *+,0
SACL *-,0
$ELSE
$IF A.SV=SP.SV
SACH *+,0
SACL *+,0
$ELSE
$IF A.SV=SM.SV
SACL *-,0
SACH *-,0
$ELSE
SACH :A:,O
SACL :A:+l,O
$ENDIF
$ENDIF
$ENDIF
$END
STORE DOUBLE
STORE HIGH
STORE LOW
STORE HIGH
STORE LOW
STORE LOW
STORE HIGH
STORE HIGH
STORE LOW
STORE TO @AR
AND @AR-1
SACX
SACX
EXAMPLE 1:
0011
0001 0006 5807
0002 0007 5008
SACX A
SACH A,O
SACL A+l,O
STORE HIGH
STORE LOW
SACX *
SACH *+,0
SACL *-,0
STORE HIGH
STORE LOW
SACX *SACL *-,0
SACH *-,0
STORE LOW
STORE HIGH
SACX *+
SACH *+,0
SACL *+,0
STORE HIGH
STORE LOW
EXAMPLE 2:
0013
0001 0008 58A8
0002 0009 5098
EXAMPLE 3:
0015
0001 OOOA 5098
0002 OOOB 5898
EXAMPLE 4:
0017
0001 OOOC 58A8
0002 0000 SOA8
I
7-121
SAT
Saturate Data Word between Upper and Lower Bounds -
TITLE:
Saturate Data Word between Upper and Lower Bounds
NAME:
SAT
OBJECTIVE:
Insure that a data word falls within boundary conditions
ALGORITHM:
Else
CALLING
SEQUENCE:
If (A) > upper,
if (A) < lower,
then
then
upper
lower
~
~
Macro
A
A
SAT data,lower,upper
ENTRY
CON DITIONS: 0 ~ data ~ 127; - 32768
~
lower ~ upper ~ 32767
EXIT
CON DITIONS: Data word contains value within bounds; statu ration mode is reset
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
I
7-122
16 - 24 words (+ LDAC$ routine)
DATA
MEMORY
REQUIRED:
2 words
2 levels
EXECUTION
TIME:
10 - 48 cycles
SAT
SAT
SAT
FLOWCHART: SAT
COMPARE UPPER
BOUND WITH
DATA WORD
LOAD UPPER
BOUND INTO
ACC
YES
COMPARE LOWER
BOUND WITH
DATA WORD
LOAD LOWER
BOUND INTO
ACC
SAVE
BOUNDARY
VALUE IN
DATA WORD
I
SOURCE:
*SATURATE VALUE IN A BETWEEN VALUES BAND C
*A IS A VARIABLE
*B AND C ARE VARIABLES OR CONSTANTS
*
SAT
$MACRO A,B,C
$VAR L,L1,L2,L3
$ASG '$$LAB' TO L.S
$ASG L.SV+3 TO L.SV
GET A LABEL
$ASG L.SV-2 TO L1.V
$ASG L.SV-1 TO L2.V
$ASG L.SV
TO L3.V
SOVM
SET OVERFLOW MODE
$IF C.SA&$UNDF
LCAC :C:
LOAD UPPER BOUND :C:
$ELSE
LAC :C:,O
LOAD UPPER BOUND :C:
$ENDIF
SUB :A:,O
COMPARE TO :A:
BGEZ L$:L1.V:
BRANCH IF :A:<=:C:
$IF C.SA&$UNDF
LCAC :C:
RELOAD :C: AS VALUE
$ELSE
7-123
SAT
SAT
LAC :C:,O
$ENDIF
B
L$:L2.V:
L$:L1.V: EQU $
$IF B.SA&$UNDF
LCAC :B:
$ELSE
LAC :B:,O
$ENDIF
SUB· :A:,O
BLEZ L$:L3.V:
$IF B.SA&$UNDF
LCAC :B:
$ELSE
LAC :B:,O
$ENDIF
L$:L2.V: SACL :A:,O
L$:L3.V: ROVM
$END
RELOAD :C: AS VALUE
BRANCH TO CONTINUE
CHECK LOWER
LOAD LOWER BOUND :B:
LOAD LOWER BOUND :B:
COMPARE TO :A:
BRANCH IF :A:>:B:
RELOAD :B: AS VALUE
RELOAD :B: AS VALUE
RESTORE :A:
CONTINUE
EXAMPLE 1:
0011
0001
0002
0001
0002
0003
0004
0005 7F8B
0006
0007
0008
0009
0005
0001
0002 OOOA
0006 OOOB
OOOC
0007
0008
0001
0002 OOOD
0009 OOOE
0010 OOOF
0010
0011
0001
0002 0011
0012 0012
0013 0013
I
0032
7E32
1007
FOOD
0000 1
0032
0032
7E32
F900
0012 1
OOOD I
0000 1
0019
7E19
1007
FBOO
0013 1
0019
0019
7E19
5007
7F8A
SAT A,25,50
SOVM
LCAC 50
V$4 EQU 50
LACK V$4
SUB A,O
BGEZ L$l
LCAC 50
V$5 EQU 50
LACK V$5
B
L$2
L$l EQU $
LCAC 25
V$6 EQU 25
LACK V$6
SUB A,O
BLEZ L$3
LCAC 25
V$7 EQU 25
LACK V$7
SACL A,O
L$2
L$3
ROVM
SET OVERFLOW MODE
LOAD UPPER BOUND 50
LOAD AC WITH V$4
COMPARE TO A
BRANCH IF A<=50
RELOAD 50 AS VALUE
LOAD AC WITH V$5
BRANCH TO CONTINUE
CHECK LOWER
LOAD LOWER BOUND 25
LOAD AC WITH V$6
COMPARE TO A
BRANCH IF A>25
RELOAD 25 AS VALUE
LOAD AC WITH V$7
RESTORE A
CONTINUE
EXAMPLE 2:
0013
0001
0002
0003
0004
0014
0015
0016
0017
0018
0005 0019
0006 001A
001B
0007
0008 001C
0009 001D
7-124
SAT A,C,D
SOVM
7F8B
LAC D,O
2002 11
SUB A,O
1007
FDOO
BGEZ L$8
001C I
2002 11
LAC D,O
F900
B
L$9
0021 1
001CI L$8 EQU $
2000 11
LAC C,O
SUB A,O
1007
SET OVERFLOW MODE
LOAD UPPER BOUND D
COMPARE TO A
BRANCH IF A<=D
RELOAD D AS VALUE
BRANCH TO CONTINUE
CHECK LOWER
LOAD LOWER BOUND C
COMPARE TO A
SAT
SAT
0010 001E
001F
0011 0020
0012 0021
0013 0022
FBOO
0022 1
2000"
5007 L$9
7F8A L$10
BLEZ L$10
BRANCH IF A>C
LAC C,O
SACL A,O
ROVM
RELOAD C AS VALUE
RESTORE A
CONTINUE
I
7-125
SBAR
Subtract Variable from Auxiliary Register -
TITLE:
Subtract Variable from Auxiliary Register
NAME:
SBAR
OBJECTIVE:
Subtract data word from named auxiliary register
ALGORITHM:
(ACAR) - (dma) - ACC
(ACC) -AR
CALLING
SEQUENCE:
Macro
SBAR AR, B [,TEMP]
ENTRY
CONDITIONS: AR
= 0,1; 0 ~ B ~ 127; 0 ~ TEMP ~ 127
EXIT
CONDITIONS: Difference between memory location and auxiliary regi ster is stored in
named auxiliary register
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
I
7-126
5 - 7 words (plus LDAC$ routine)
DATA
MEMORY
REQUIRED:
2 words
o-
EXECUTION
TIME:
5 - 17 cycles
2 levels
SBAR
SBAR
SBAR
FLOWCHART: SBAR
NO
LET XRO BE
TEMPORARY
STORE AUXILIARY
REGISTER IN
TEMPORARY
YES
LOAD ACC WITH
TEMPORARY
CALL LCAC
TO LOAD
CONSTANT
IN ACC
ADD TEMP TO
ACC
SUBTRACT VARIABLE
FROM ACC
I
SAVE ACC IN
TEMPORARY
RELOAD AUXILIARY
REGISTER
SOURCE:
*SUB FROM AR
*A IS ARI OR ARO
*B IS CONST OR VAR
*SBAR
$MACRO A,B,T
$IF T.L=O
SASG 'XRl' TO T.S
$ENDIF
SAR : A: , : T :
$IF B.SA&$UNDF
$ASG -B.V TO B.V
LCAC :B. V:
ADD :T:,O
$ELSE
LAC :T:,O
SUB :B:,O
ASSIGN TEMP
SAVE : A:
LOAD -:B: VALUE
ADD :T: VALUE
LOAD :T:
SUB :B: VALUE
7-127
SBAR
SBAR
$ENDIF
SACL :T:,O
LAR :A:, :T:
$END
RESTORE
RELOAD :A:
EXAMPLE 1:
0007
SBAR
AR1,3
SAR AR1,XR1
0001 0006 3103"
LCAC -3
0002
FFFD V$l EQU -3
0001
0002 0007 F800
CALL LDAC$
0008 0000
REF LDAC$
0003
DATA V$l
0004 0009 FFFD
0003 OOOA 0003"
ADD XR1,O
0004 OOOB 5003"
SACL XR1,O
0005 OOOC 3903 11
LAR AR1,XR1
SAVE AR1
LOAD -3 VALUE
LOAD AC WITH:
V$l
ADD XR1 VALUE
RESTORE
RELOAD AR1
EXAMPLE 2:
0009
0001
0002
0003
0004
0005
OOOD
OOOE
OOOF
0010
0011
3008
2008
1004"
5008
3808
SBAR
ARO,C,B
SAR ARO,B
LAC B,O
SUB C,O
SACL B,O
LAR ARO,B
SAVE ARO
LOAD B
SUB C VALUE
RESTORE
RELOAD ARO
3003"
2003"
1005"
5003"
3803"
O,D
SBAR
SAR O,XR1
LAC XR1,0
SUB D,O
SACL XR1,0
LAR O,XR1
SAVE 0
LOAD XR1
SUB D VALUE
RESTORE
RELOAD 0
EXAMPLE 3:
I
0011
0001
0002
0003
0004
0005
7-128
0012
0013
0014
0015
0016
SBIC
Clear Single Bit in Data Word -
Macro
TITLE:
Clear Single Bit in Data Word
NAME:
SBIC
OBJECTIVE:
Clear bit in data word specified by bit position argument
ALGORITHM:
(A) .AND .. NOT. 2 bit -+ (A)
CALLING
SEQUENCE:
SBIC bit,A
ENTRY
CONDITIONS: 0 ~ A
~
SBIC
127; 0 ~ bit ~ 15
EXIT
CONDITIONS: A contains initial value with specified bit cleared
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
4 words
DATA
MEMORY
REQUIRED:
2 words
None
EXECUTION
TIME:
4 cycles
FLOWCHART: SBIC
(
,
I
BEGIN)
,
,
,
SET SINGLE BIT
IN ACC
INVERT
ACC
CLEAR BIT OF
DATA WORD
IN ACC
,
RESTORE DATA TO
MEMORY
(
END
J
7-129
SBIC
SBIC
SOURCE:
*BIC A SELECTED BIT
*A IS BIT NUMBER
*B IS VAR
*SBIC
$MACRO A,B
LAC ONE, :A:
XOR MINUS
AND :B:
SACL :B: ,0
$ END
SINGLE BIT CLEAR
GET SELECT BIT
INVERT MASK
AND :B:
STORE TO :B:
EXAMPLE 1:
0012
0001
0002
0003
0004
2802"
7803'1
7900"
5000'1
SBIC
LAC
XOR
AND
SACL
B,C
ONE,B
MINUS
C
C,O
GET SELECT BIT
INVERT MASK
AND C
STORE TO C
2302'1
7803"
7901"
5001 11
SBIC
LAC
XOR
AND
SACL
3,D
ONE,3
MINUS
D
D,O
GET SELECT BIT
INVERT MASK
ANDD
STORE TO D
SBIC
LAC
XOR
AND
SACL
12,B
ONE,12
MINUS
B
B,O
GET SELECT BIT
INVERT MASK
AND B
STORE TO B
OOOA
OOOB
OOOC
OOOD
EXAMPLE 2:
0014
0001
0002
0003
0004
OOOE
OOOF
0010
0011
EXAMPLE 3:
I
0016
0001
0002
0003
0004
7-130
0012
0013
0014
0015
2C02'1
7803'1
7908
5008
SBIS
Set Single Bit in Data Word -
TITLE:
Set Single Bit in Data Word
NAME:
SBIS
OBJECTIVE:
Set bit in data word specified by bit position argument
ALGORITHM:
(data) .OR. 2 bit -+ data
CALLING
SEQUENCE:
SBIS bit,A
ENTRY
CONDITIONS: 0 ~ A
~
SBIS
Macro
127; 0 ~ bit ~ 15
EXIT
CONDITIONS: A contains initial value with specified bit set
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
3 words
DATA
MEMORY
REQUIRED:
1 word
None
EXECUTION
TIME:
3 cycles
FLOWCHART: SBIS
(
,
I
BEGIN)
SET SINGLE BIT
IN ACC
I
,
OR ACC WITH
DATA WORD
,
RESTORE DATA WORD
TO MEMORY
(
END
)
SOURCE:
*SET SELECTED BIT
*A IS BIT NUMBER
*B IS VAR
*
SBIS
$MACRO A,B
LAC ONE, :A:
OR
:B:
SACL :B:,O
$END
SINGLE BIT SET
GET SELECT BIT
SET TO :B:
RESTORE
7-131
5815
S81S
EXAMPLE 1:
0012
0001 0009 2802"
0002 OOOA 7AOO"
0003 OOOB 5000"
SBIS
LAC
OR
SACL
B,C
ONE,B
C
C,O
SBIS
LAC
OR
SACL
3,0
ONE,3
GET SELECT BIT
SET TO C
RESTORE
EXAMPLE 2:
0014
0001 OOOC 2302"
0002 0000 7A01 11
0003 OOOE 5001 11
D,O
GET SELECT BIT
SET TO D
RESTORE
12,B
ONE,12
B
B,O
GET SELECT BIT
SET TO B
RESTORE
0
EXAMPLE 3:
0016
0001 OOOF 2C02 11
0002 0010 7A08
0003 0011 5008
I
7-132
SBIS
LAC
OR
SACL
SBIT
Test Single Bit in Data Word -
Macro
TITLE:
Test Single Bit in Data Word
NAME:
SBIT
OBJECTIVE:
Test bit in data word specified by bit position argument
ALGORITHM:
data .AND. 2 bit -. ACC
CALLING
SEQUENCE:
SBIT bit,A
ENTRY
CONDITIONS: 0 ~ A
~
SBIT
127; 0 ~ bit ~ 15
EXIT
CON DITIONS: ACC contains zero if specified bit is cleared, non-zero else
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
2 words
DATA
MEMORY
REQUIRED:
1 word
None
EXECUTION
TIME:
2 cycles
FLOWCHART: SBIT
I
SET SINGLE BIT
IN Ace
AND ACC WITH
DATA WORD
SOURCE:
*TEST SELECTED BIT
*A IS BIT NUMBER
*B IS VAR TO TEST
*SBIT
$MACRO A,B
LAC ONE, :A:
AND :B:
$END
SINGLE BIT TEST
GET BIT :A:
TEST FOR IT
7-133
SBIT
SBIT
EXAMPLE:
0014
0001 OOOA 2302"
0002 OOOB 7901 11
I
7-134
SBIT
LAC
AND
3,D
ONE,3
D
GET BIT 3
TEST FOR IT
STOX
Convert Single Word to Double Word -
TITLE:
Convert Single Word to Double Word
NAME:
STOX
OBJECTIVE:
Convert single word to a double word and save
ALGORITHM:
(A)
CALLING
SEQUENCE:
STOX single, double
ENTRY
CONDITIONS: 0
~
-+
Macro
STOX
B:B + 1
single ~ 127 ; 0 ~ double ~ 127
EXIT
CONDITIONS: Double word contains value of single word
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
3 words
DATA
MEMORY
REQUIRED:
None
None
EXECUTION
TIME:
3 cycles
FLOWCHART: STOX
(
BEGIN
I
)
~
LOAD SINGLE WORD
INTO ACC
~
SAVE AS
DOUBLE WORD
(
~
END
J
SOURCE:
*SINGLE TO DOUBLE (A TO B)
*
STOX
$MACRO A,B
LAC :A:, 0
SACX :B:
$END
LOAD SINGLE
STORE DOUBLE
7-135
STOX
STOX
EXAMPLE:
0011
0001 0006 2007
0002
0001 0007 5802"
0002 0008 5003"
7-136
STOX A,O
LAC A,O
SACX 0
SACH 0,0
SACL 0+1,0
LOAD SINGLE
STORE DOUBLE
STORE HIGH
STORE LOW
SUBX
Double-Word Subtract -
SUBX
Macro
TITLE:
Double-Word Subtract
NAME:
SUBX
OBJ ECTIVE:
Subtract double word from accumulator
ALGORITHM:
SUBX *
- causes'" (ACC) - (@AR:@AR + 1) ... ACC
SUBX * -
- causes'" (ACC) - (@AR-1 :@AR)'" ACC
(AR) - 2 -+ AR
SUBX *
+
causes'" (ACC) - (@AR:@AR + 1) ... ACC
(AR) + 2 -+ AR
- causes'" (ACC) - (A:A + 1) -+ ACe
SUBX A
CALLING
SEQUENCE:
-
SUBX {A,*,* -,* +
ENTRY
CONDITIONS: 0 ~ A
~
}
127
EXIT
CONDITIONS: Accumulator contains updated value after subtraction;
auxiliary register is updated if necessary
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
I
2 words
DATA
MEMORY
REQUIRED:
None
None
EXECUTION
TIME:
2 cycles
7-137
SUBX
SUBX
FLOWCHART: SUBX
YES
SUBTRACT @AR
AND @AR+l
SUBTRACT @AR
AND @AR+l
YES
YES
SUBTRACT A AND A + 1
END
I
SOURCE:
*SUBTRACT DOUBLE
*
SUBX
7-138
$MACRO A
$VAR ST,SM,SP
$ASG 1*1 TO ST.S
$ASG 1*+1 TO SP.S
$ASG 1*_1 TO SM.S
$IF A.SV=ST.SV
SUBH *+
SUBS *$ELSE
$IF A.SV=SP.SV
SUBH *+
SUBS *+
$ELSE
$IF A.SV=SM.SV
SUBS *SUBH *$ELSE
SUBH :A:
SUBS :A:+l
$ENDIF
$ENDIF
$ENDIF
$END
SUBTRACT DOUBLE
SUBTRACT HIGH
SUBTRACT LOW
SUBTRACT HIGH
SUBTRACT LOW
SUBTRACT LOW
SUBTRACT HIGH
SUBTRACT HIGH
SUBTRACT LOW
SUBTRACT @AR
AND @AR-l
SUBX
SUBX
EXAMPLE 1:
0011
0001 0006 6207
0002 0007 6308
SUBX A
SUBH A
SUBS A+1
SUBTRACT HIGH
SUBTRACT LOW
SUBX *
SUBH *+
SUBS *-
SUBTRACT HIGH
SUBTRACT LOW
SUBX *SUBS *SUBH *-
SUBTRACT LOW
SUBTRACT HIGH
SUBX *+
SUBH *+
SUBS *+
SUBTRACT HIGH
SUBTRACT LOW
SUBX 3
SUBH 3
SUBS 3+1
SUBTRACT HIGH
SUBTRACT LOW
EXAMPLE 2:
0013
0001 0008 62A8
0002 0009 6398
EXAMPLE 3:
0015
0001 OOOA 6398
0002 OOOB 6298
EXAMPLE 4:
0017
0001 OOOC 62A8
0002 0000 63A8
EXAMPLE 5:
0019
0001 OOOE 6203
0002 OOOF 6304
I
7-139
TST
Test Word -
TST
Macro
TITLE:
Test Word
NAME:
TST
OBJECTIVE:
Load word into accumulator, allowing comparison with zero
ALGORITHM:
(A)-'ACC
CALLING
SEQUENCE:
TST {A, * , * - , * +
ENTRY
CONDITIONS:
O~A~
}
127
EXIT
CONDITIONS: Accumulator contains value of word
PROGRAMM
MEMORY
REQUIRED:
STACK
REQUIRED:
1 word
DATA
MEMORY
REQUIRED:
None
None
EXECUTION
TIME:
1 cycle
FLOWCHART: TST
I
LOAD ACC WITH
WORD
SOURCE:
*TEST SINGLE VAR
*
TST
$MACRO A
LAC :A: ,0
$END
COMPARE TO ZERO
LOAD IT
EXAMPLE 1:
0007
0001 0006 2001
7-140
TST
LAC
A
A,O
LOAD IT
TST
TST
EXAMPLE 2:
0009
0001 0007 2088
TST
LAC
*
*,0
LOAD IT
TST
LAC
C
C,O
LOAD IT
TST
LAC
*+
*+,0
LOAD IT
EXAMPLE 3:
0011
0001 0008 2004 11
EXAMPLE 4:
0013
0001 0009 20A8
7-141
TSTX
I
Test Double Word -
TSTX
Macro
TITLE:
Test Double Word
NAME:
TSTX
OBJECTIVE:
Load double word into accumulator, allowing comparison with zero
ALGORITHM:
TSTX*
- causes-+
(@AR:@AR + 1) -+ ACC
TSTX * - - causes-+
(@AR - 1:@AR) -+ ACC
(AR) - 2-+AR
TSTX * +
-
(@AR:@ AR + 1) -+ ACC
(AR) + 2 -+ AR
TSTXA
- causes-
causes-+
CALLING
SEQUENCE:
TSTX {A, * , * - , *
ENTRY
CONDITIONS:
O~A~
(A:A + 1) -+ ACC
+}
127
EXIT
CONDITIONS: Accumulator contains value of double word;
auxiliary register is updated if necessary
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
7-142
2 words
DATA
MEMORY
REQUIRED:
None
None
EXECUTION
TIME:
2 cycles
TSTX
TSTX
FLOWCHART: TSTX
LOAD {@AR
AND @AR+1
LOAD @AR
AND @AR+ 1
LOAD @AR
AND @AR+1
LOAD A AND A+ 1
AR = AR+2
SOURCE:
I
*TEST DOUBLE VAR
*
TSTX
$MACRO A
LDAX :A:
$END
COMPARE TO ZERO DOUBLE
LOAD IT DOUBLE
EXAMPLE 1:
0011
0001
0001 0006 6507
0002 0007 6108
TSTX A
LDAX A
ZALH A
ADDS A+1
LOAD IT DOUBLE
LOAD HIGH A
LOAD LOW A
TSTX *
LDAX *
ZALH *+
ADDS *-
LOAD IT DOUBLE
LOAD HIGH
LOAD LOW 1*1
TSTX *LDAX *ZALS *ADDH *-
LOAD IT DOUBLE
LOAD LOW
LOAD HIGH 1*_1
EXAMPLE 2:
0013
0001
0001 0008 65A8
0002 0009 6198
EXAMPLE 3:
0015
0001
0001 DaDA 6698
0002 OOOB 6098
7-143
TSTX
TSTX
EXAMPLE 4:
0017
0001
0001 oooe 65AB
0002 0000 61AB
I
7-144
TSTX *+
LOAX *+
ZALH *+
ADDS *+
LOAD IT DOUBLE
LOAD HIGH
LOAD LOW 1*+1
XTOS
Convert Double Word to Single Word -
TITLE:
Convert Double Word To Single Word
NAME:
XTOS
OBJECTIVE:
Convert double word to a single word and save
ALGORITHM:
If (A:A + 1)
Else if (A:A + 1)
CALLING
SEQUENCE:
>
<
32767
- 32768
then
32767
then
- 32768
Else (A+ 1)
Macro
-+
B
-+
B
-+
B
XTOS
XTOS double,single
ENTRY
CON DITIONS: 0 ~ single ~ 127 ; 0 ~ double ~ 127
EXIT
CONDITIONS: Single word contains value of double word or saturation value
PROGRAM
MEMORY
REQUIRED:
STACK
REQUIRED:
27 words (+ LDAC$ routine)
DATA
MEMORY
REQUIRED:
2 words
2 levels
EXECUTION
TIME:
33 - 50 cycles
I
7-145
XTOS
XTOS
FLOWCHART: XTOS
COMPARE DOUBLE
WORD WITH 32767
LOAD 32767
INTO Ace
COMPARE DOUBLE
WORD WITH -32768
LOAD -32768
INTO Ace
LOAD DOUBLE WORD
INTO ACC
SAVE Aee LOW IN
SINGLE WORD
I
SOURCE:
*DOUBLE TO SINGLE (A TO B)
*
XTOS
$MACRO A,B
$VAR L,L1,L2,L3
$ASG '$$LAB' TO L.S
$ASG L.SV+3 TO L.SV
GET LABEL
$ASG L.SV-2 TO L1.V
$ASG L.SV-1 TO L2.V
$ASG L.SV
TO L3.V
LCAC 32767
GET BIGGEST SINGLE
SUBX :A:
COMPARE :A:
BGEZ L$:L1.V:
IF :A: >= 32767 THEN
LCAC 32767
SATURATE AT 32767
B
L$:L3.V:
JUMP TO DONE
L$:Ll.V: LCAC -32768
GET MOST NEG SINGLE
SUBX :A:
COMPARE :A:
BLEZ L$:L2.V:
IF :A: <= -32768 THEN
LCAC -32768
SATURATE AT -32768
B
L$:L3.V:
JUMP TO DONE
L$:L2.V: LDAX :A:
LOAD :A:
L$:L3.V: SACL :B:,O
RESTORE TO :B:
$ END
7-146
XTOS
XTOS
EXAMPLE:
0013
0001
0001
0002 0021
0022
0003
0004 0023
0002 0024
0001 0024
0002 0025
0003 0026
0027
0004 0028
0001
0002 0028
0029
0003
0004 002A
0005 002B
002C
0006 002D
0001
0002 002D
002E
0003
0004 002F
0007 0030
0001 0030
0002 0031
0008 0032
0033
0009 0034
0001
0002 0034
0035
0003
0004 0036
0010 0037
0038
0011 0039
0001 0039
0002 003A
0012 003B
7FD7
F800
0000
XTOS C,B
LCAC 32727
V$ll EQU 32727
CALL LDAC$
REF LDAC$
DATA V$ll
SUBX C
SUBH C
SUBS C+1
BGEZ L$8
7FD7
6200 11
6301 11
FDOO
002D 1
7FD7
F800
0000
LCAC 32727
V$12 EQU 32727
CALL LDAC$
REF LDAC$
DATA V$12
B
L$10
7FD7
F900
003B 1
8000
F800
0000
LCAC -32768
L$8
V$13 EQU -32768
CALL LDAC$
REF LDAC$
DATA V$13
SUBX C
SUBH C
SUBS C+1
BLEZ L$9
8000
6200"
6301"
FBOO
0039 1
8000
F800
0000
LCAC -32768
V$14 EQU -32768
CALL LDAC$
8000
F900
003B 1
L$9
6500"
6101"
5009 L$10
REF LDAC$
DATA V$14
B
L$10
LDAX C
ZALH C
ADDS C+1
SACL B,O
GET BIGGEST SINGLE
LOAD AC WITH:
V$ll
COMPARE C
SUBTRACT HIGH
SUBTRACT LOW
IF C >= 32767 THEN
SATURATE AT 32767
LOAD AC WITH:
V$12
JuriP TO DONE
GET MOST NEGATIVE SINGLE
LOAD AC WITH:
V$13
COMPARE C
SUBTRACT HIGH
SUBTRACT LOW
IF C <= -32768 THEN
SATURATE AT -32768
LOAD AC WITH:
V$14
JUMP TO DONE
LOAD C
LOAD HIGH C
LOAD LOW C
RESTORE TO B
7-147
7.4
STRUCTURED PROGRAMMING MACROS
The program structure macros, PROG AND MAIN, need to be used with most of the other macros
described in Section 7.3 in order to set up internal symbols and utility variables used by those
macros.
PROG
Begin Program -
Macro
PROG
PROG - Begin Program
The program directive does two things. First, it defines the module I DT name (the name of the module
printed on the link editor memory map listing). More importantly, it initializes several internal symbols used
in many of the macros from Section 7.3. Syntax is as follows:
PROG < name>
Where < name> is a string of up to six characters. This name is used to generate:
IDT'< name>'
To end the module, use the assembly language END statement:
END
SOURCE:
I
**
Prog Routine Initializes Internal Variables, and
Outputs IDT Statement
*
*
PROG
$MACRO
$VAR Q
$ASG 1 1 liTO Q. S
IDT :Q::A::Q:
A
**
*
Initialize unique label counter
*
*
*
Assign unique values to indirect symbols
7-148
$ASG '$$LAB' TO Q.S
$ASG 0 TO Q.SV
$ASG
$ASG
$ASG
$ASG
$ASG
$ASG
$END
,*, TO Q.S
>FOFO TO Q.SV
'*+1 TO Q.S
>FOFI TO Q.SV
1*_1 TO Q.S
>FOF2 TO Q.SV
MAIN
Begin Main Procedure -
Macro
MAIN
MAIN- Begin Main Procedure
MAIN
The MAIN directive begins the main procedure. < name> is the label (created by the macro) of the first
instruction of the main routine (up to six characters). MAIN allocates the variables ONE, MINUS, XRO, and
XR1 in data RAM (in the DSEG), and initializes ONE to 1, and MINUS to - 1.
SOURCE:
** Main Procedure Definition Macro
** A is Main Program Name «6 CHAR)
*
A
MAIN
$MACRO
PSEG
DEF :A:
EQU $
:A:
**
*
*
*
*
PROG SEG
ENTRY POINT
Initialize Variables
LACK
SACL
ZAC
SUB
SACL
1
ONE,O
ONE,O
MINUS,O
MAKE
SAVE
ZERO
MAKE
SAVE
CONSTANT ONE
IT
ACCUMULATOR
-1
IT
Data Segment
ONE
MINUS
XRO
XR1
DSEG
BSS
BSS
BSS
BSS
DEF
DEF
DEND
$END
1
1
1
1
ONE,MINUS
XRO,XR1
I
CONSTANT ONE
CONSTANT -1
TEMP
TEMP 1
ALLOW EXTERNAL USE
OF VARIABLES
END OF DATA
°
EXAMPLES OF PROG AND MAIN USAGE:
MLIB
*
*
*
PROG
I
MACROS I
MACTST
Declare directory of macros,
including PROG and MAIN
Set up symbol table variables
7-149
VAR1
VAR2
DSEG
BSS 1
BSS 1
User1s program variables
*
*
*
*
*
*
*
*
*
*
*
:
*
DEND
I
Interrupt Routine (user defined)
I
MAIN
START
Start of main routine
I
Maln Program - Instructions and Macros
*
*
IEND
LISTING:
0001
0002
0003
0001
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0021
I
7-150
0000
MLIB
*
0000
0000
0001
0002
PROG
IDT
*
*
VAR1
VAR2
*
*
*
*
*
*
*
*'
*
*
I
MACROS I
MACTST
I MACTST I
DSEG
BSS 1
BSS 1
*
Userls program variables
DEND
I
Interrupt Routine (user defined)
I
MAIN START
PSEG
DEF START
0000 1 START
EQU $
0000 7E01
LACK 1
SACL ONE,O
0001 5002"
ZAC
0002 7F89
SUB ONE,O
0003 1002"
SACL MINUS,O
0004 5003 11
DSEG
0002
ONE
BSS 1
0002
MINUS BSS 1
0003
XRO
BSS 1
0004
BSS 1
0005
XR1
DEF ONE ,MINUS
DEF XRO,XR1
DEND
0006
0000
Declare directory of macros,
including PROG and MAIN
Set up symbol table variables
Start of main routine
PROG SEG
ENTRY POINT
MAKE
SAVE
ZERO
MAKE
- SAVE
CONSTANT ONE
IT
ACCUMULATOR
-1
IT
CONSTANT ONE
CONSTANT -1
TEMP 0
TEMP 1
ALLOW EXTERNAL USE
OF VARIABLES
END OF DATA
*
0022
0023
0024
0025
0026
0027
0028
7.5
: I
*
Ma~n
:
Program - Instructions and Macros
IEND
UTILITY SUBROUTINES
The subroutines in this section are called by many of the macros described in Section 7.3.
Subroutines are used to save program space. Instead of inserting the code into each macro, the
code occurs as a separate subroutine. Since the code is not expanded with each macro call,
program space is saved. These routines should be assembled separately from the calling program
and linked with the main program.
SOURCE FILE OF UTILITY SUBROUTINES:
IDT 'SUBR'
**
*
*
SUBROUTINES USED AS UTILITIES IN VARIOUS MACRO LANGUAGE EXTENSIONS
AND SIGNAL PROCESSING LANGUAGE MACROS.
**
*
*
LDAC$ - Load the accumulator with value found in program memory
at location pointed to by address on the top of the stack.
REF ONE,MINUS
REF XRO,XRl
DEF LDAC$
LDAC$ POP
TBLR XRO
ADD ONE
PUSH
LAC XRO
RET
*
**
I
RIP$ - SUBROUTINE USED FOR LOOPED VERSION OF RIPPLE MACRO
*
DEF RIP$
POP
TBLR XRO
LAR ARO,XRO
LARP ARO
MAR *SAR ARO,XRO
ADD ONE
TBLR XR1
LAR AR1,XR1
SACL XR1
LAC XRO
SAR AR1,XRO
ADD XRO
SACL XRO
LAR AR1,XRO
RIP$L LARP AR1
DMOV *-,ARO
BANZ RIP$L
LAC XRl
ADD ONE
RIP$
1st argument
RO = count
= length
Decrement count
Store L-1 in XRO
I~crement argument pointer
2nd argument = address
Save address in R1
Save argument pointer
ACC = L-1
Get address from R1
ACC = address + L-1
Save address
Rl = address pointer
Shift data
Restore argument pointer
Decrement argument pointer
7-151
Put return address on top ot stack
PUSH
RET
**
*
LDAX$ - Load accumulator with double word
DEF LDAX$
LDAX$ POP
TBLR XRl
ADD ONE
TBLR XRO
ADD ONE
PUSH
ZALH XRl
ADDS XRO
RET
**
*
I
DEF LTK$
POP
TBLR XRO
LT
XRO
ADD ONE
PUSH
RET
** Instructions for MOVE
* positions, but all of
* actual data transfer.
*
** MOVAB$ - MOVE A,B
*
MOVAB$ POP
TBLR
LAR
ADD
MOVB$$ TBLR
LAR
ADD
B
* MOVA$
7-152
Get address of word
Read word into data memory
Load into ARO
Restore return address
Get address of word
Read word into data memory
Load into ARI
Restore return address
- Load T Register with word from program memory
LTK$
LTK$
*
*
Load upper half
Load lower half
LDAR$l - Load Auxiliary Register 1 with word from program memory
DEF LDAR$l
LDAR$l POP
TBLR XRO
LAR ARl,XRO
ADD ONE
PUSH
RET
**
*
Read lower half
LDAR$O - Load Auxiliary Register 0 with word from program memory
DEF LDAR$O
LDAR$O POP
TBLR XRO
LAR ARO,XRO
ADD ONE
PUSH
RET
**
*
Get address of constants
Read upper half
XRO
ARO,XRO
ONE
XRO
ARl,XRO
ONE
MOV$M
- MOVE A,*
Get address of word
Read word into data memory
Load word into T register
Restore return address
macro. There are four different entry
them use code starting at MOV$M to do
Read A into ARO
Read B into ARI
Move data
MOVA$
POP
TBLR
LAR
ADD
B
*
* MOVB$
*
MOVB$
POP
B
*
*
MOV$L
Move A into ARO
- MOVE *,B
* MOV$$
MOV$$
MOV$M
XRO
ARO,XRO
ONE
MOV$M
MOVB$$
Move B into AR1
- MOVE *,*
POP
TBLR
SACL
LARP
LAC
SACL
LAC
SUB
SACL
BNZ
LAC
ADD
PUSH
RET
DEF
* SETS$
*
SETS$ POP
*
TBLR
ADD
TBLR
LAR
LARP
MAR
ADD
TBLR
LAR
SACL
LAC
SET$L LARP
SACL
BANZ
LAC
ADD
PUSH
RET
DEF
XRO
XR1
°*+,O,ARI
*+,O,ARO
XRO
ONE
XRO
MOV$L
XR1
ONE
Read number of elements to move
Save return address
Move @ARO to ACC
Move ACC to @AR1
Decrement loop counter
Loop back for another move
Restore return address
MOVAB$,MOVA$,MOVB$,MOV$$
- Move constant into L positions of data memory
XRO
ONE
XR1
ARO,XR1
°*-
ONE
XR1
AR1,XR1
XR1
XRO
1
*+,O,ARO
SET$L
XR1
ONE
TBLR
LAR
ADD
B
MOVC$l POP
MOVC$M TBLR
LAR
LARP
MAR
I
Get 2nd argument - count
Use ARO as counter
Get 3rd argument - destination
Use AR1 as pointer
Save return address
Load constant into accumulator
Move constant to data memory
Repeat L times
Restore return address
SETS$
* MOVC$ AND
*
MOVC$ POP
*
Get 1st argument - constant
MOVC$l - Move list of constants to data memory
XRO
AR1,XRO
ONE
MOVC$M
XRO
ARO,XRO
°*-
Get argument pointer
1st argument = destination
Use AR1 as pointer
Increment argument pointer
Read length of data
ARO is loop counter
Decrement counter
7-153
ADD ONE
MOVC$L LARP 1
TBLR *+,ARO
ADD ONE
BANZ MOVC$L
PUSH
RET
DEF MOVC$,MOVC$l
Increment argument pointer
Read constant
Loop for length of data
Restore return address
*
* Routines for MOVDAT macro
*
* MOVA$B -
*
MOVDAT A,B,L
MOVA$B POP
TBLR
LAR
ADD
MOVCB$ TBLR
LAR
ADD
B
*
* MOVC$A -
*
MOVC$A
*
*
MOVC$B
POP
TBLR
LAR
ADD
B
* MOVC$B -
I
POP
B
XRO
ARO,XRO
ONE
XRO
AR1,XRO
ONE
MOV$$M
1st Argument is source
Increment pointer
Next argument is destination
Increment pointer
MOVDAT A,*,L or MOVDAT A"L
XRO
ARO,XRO
ONE
MOV$$M
Read source argument
Increment pointer
MOVDAT *,B,L or MOVDAT ,B,L
MOVCB$
Get destination argument
*
*
MOVC$$
* MOVC$$ - MOVDAT ,*,L or MOVDAT *"L or MOVDAT *,*,L
POP
MOV$$M SAR ARO,XRO
Save source location
TBLR XR1
Read length
LAR ARO,XR1
LARP
Decrement count
MAR *SACL XR1
Save return address
Load start address
LAC XRO
MOV$$L LARP 1
TBLR *+,ARO
Move to data memory
Update source pointer
ADD ONE
Loop on array length
BANZ MOV$$L
LAC XR1
ADD ONE
PUSH
Restore return address
RET
DEF MOVA$B,MOVC$A,MOVC$B,MOVC$$
°
** MOVROM routines
** TBW$$ - MOVROM A,B,L
*
TBW$$ POP
TBWO$
7-154
TBLR
LAR
ADD
TBLR
XRO
ARO,XRO
ONE
XRO
Read source address
Update pointer
Read destination address
LAR
ADD
B
** TBW$l *
TBW$l POP
TBLR
LAR
ADD
B
* TBW$O *
TBW$O POP
*
B
* TBW$$ *
TBW$Ol POP
*
TBW$M
TBW$L
SAR
TBLR
LAR
LARP
MAR
SACL
LAC
LARP
TBLW
ADD
BANZ
LAC
ADD
PUSH
RET
DEF
END
ARl,XRO
ONE
TBW$M
Update pointer
MOVROM A,*,L or MOVROM A"L
XRO
ARO,XRO
ONE
TBW$M
Read source address
Update pointer
MOVROM *,B,L or MOVROM ,B,L
TBWO$
Read destination address
MOVROM *,*,L or MOVROM *"L or MOVROM ,*,L
ARl,XRO
XRl
ARl,XRl
1
*XRl
XRO
Save destination address
Read length of move
Decrement counter
Save return address
Load destination address
0
*+,ARl
ONE
TBW$L
XRl
ONE
Move data
Increment pointer
Loop on length
Restore return address
I
TBW$$,TBW$l,TBW$O,TBW$Ol
* End of subroutines
7-155
I
DIGITAL SIGNAL PROCESSING
I
I
8.
DIGITAL SIGNAL PROCESSING
All of the digital signal processing information presented in this Section 8 has been provided to
Texas Instruments by Ronald W. Schafer, Russell M. Mersereau, and Thomas P. Barnwell, III, of
Atlanta Signal Processors, Inc., and of Georgia Institute of Technology, School of Electrical
Engineering.
The purpose of this section is to review the fundamentals of digital signal processing in order to
highlight some of the important features of the digital approach and to illustrate how OSP
techniques can be applied. The important issues in sampling analog signals will be presented,
followed by a discussion of the basic theory of discrete signals and systems. A description of the
basic algorithms that are widely used in applications of OSP techniques is also provided, along with
some examples of how OS P can be used in the areas of speech and audio processing and in
communications. Referral to references listed in Section 8.7 is indicated by brackets surrounding a
reference number.
8.1
A-TO-D AND D-TO-A CONVERSION
In most applications, signals originate in analog form, i.e., as continuously varying patterns or
waveforms. Thus, the first step in applying OSP techniques to a signal is to convert from
continuous to discrete form, thereby obtaining a representation of the signal in terms of a sequence
or array of numbers. In practice, this is called analog-to-digital (A-to-O) conversion.
Once the signal has been represented in discrete form, it can be processed or transformed into
another sequence or set of numbers by a numerical computation procedure (see Figure 8-1 ). There
is also the possibility of converting from the discrete representation back to analog form using a
digital-to-analog (O-to-A) converter. This last stage is often not necessary, especially when the
purpose of digital processing is to automatically extract information from the signal. The study of
digital signal processing is concerned with both the A-to-O and O-to-A conversion processes as
well as with the analysis and design of numerical processing algorithms. Although it is important to
fully understand both aspects, they can be treated somewhat independently.
x a(t)
-
A-TO-O
CONVERTER
-
---
NUMERICAL
PROCESSOR
O-TO-A
CONVERTER
I
-
Ya(t)
FIGURE 8-1 - BLOCK DIAGRAM OF DIGITAL SIGNAL PROCESSING
A-to-O conversion is conveniently analyzed by representing it as in Figure 8-2. First, it involves a
sampling operation wherein a sequence x[n] is obtained by periodically sampling an analog signal.
The samples are:
x[n]
= xa(nT),
-00
2000, i.e., SAMPLING MUST OCCUR AT A RATE THAT IS GREATER THAN
lWlCE THE HIGHEST FREQUENCY IN THE SIGNAL. This is true in general for any signal whose
Fourier transform is bandlimited, as explained in the following paragraphs.
If the above condition is met, it is possible to recover xa(t) from x[n] by continuously interpolating
between the samples, using an interpolation formula of the form:
8-3
00
xa(t)
=
~
x[n]· Pa(t-nT)
(9)
n=-oo
If Pa(t) is a square pulse of duration T, the resulting interpolated waveform (reconstructed signal)
has a staircase appearance, as in Figure 8-5. This is a good model for the output of most practical
O-to-A converters. A better approximation to the original analog signal can be obtained by
smoothing the sharp pulses with a lowpass filter. [1-4] If the effective pulse shape in (9) is:
•
Sin
1T
Tt
Pa(t) = - ~t
T
(10)
then the original signal Xa(t) can be recovered from the samples x[n] if the Fourier transform of Xa(t)
is bandlimited (i.e., identically zero above some frequency which is less than nIT).
RECONSTRUCTED
SIGNAL
SIGNAL
I
o
T
2T
4T
3T
5T
6T
TIME
FIGURE 8-5 -
8-4
D-TO-A CONVERSION USING A ZERO-ORDER HOLD
7T
aT
8.1.2
Sample Quantization
The other aspect of A-to-O conversion is concerned with the quantization of the samples. Figure
8-6 shows an eight-level quantizer which illustrates the important aspects of the quantization
operation. Each quantization level is represented by a binary number (three bits in this case).
Although the assignment of binary codes to the quantization levels is arbitrary, it is obviously
advantageous to assign binary symbols in a scheme which permits convenient implementation of
arithmetic operations on the samples (e.g., two's complement, as in Figure 8-6).
Once the number of quantization levels has been fixed (usually between 28 and 216 for most signal
processing applications), the binary numerical representation of the samples is related to the
amplitude of the analog signal by the quantization stepsize 6.. The choice of 6. depends upon the
peak-to-peak amplitude range of the signal. If the B-bit code is used, then 6. should be chosen so
that:
(11 )
~ . 2 8 = Peak-to-peak signal ampl itude
With this constraint, the maximum error in a sample value would be + - 6./2, so that in general,
the average quantization error will be proportional to 6.. This points up a fundamental dilemma in
quantization, i.e., for a fixed stepsize, the relative error becomes large as the sample amplitude
decreases. Thus, if signal amplitude varies widely (i.e., the signal has a wide dynamic range), then it
may be necessary to use a large number of quantization levels to keep the relative quantization error
within acceptable limits. Alternative approaches, often used in speech processing, are the use of
either a nonuniform set of quantization levels or the adaptation of the stepsize to the amplitude of
the input signal. [2]
"x
011
- 36
010
2b.
-9A
2
I
..
-7A
-3A
-sA
-2-
-2-
2
-t!.
2
111
110
101
100
I
I
001
A
000
..
A
3A
"2"
2
.
SA
I
.
7A
2
-
x-
2
.• -A
-2A
-36
.. -46
PEAK-TO-PEAK RANGE
FIGURE 8-6 - AN EIGHT LEVEL (THREE-BIT) QUANTIZER
8-5
In the uniform stepsize non-adaptive case, it is often useful to represent the quantized signal as:
(12)
x[n] = x[n] + e[n]
where ern] is, by definition, the quantization error. This model for A-to-D conversion is depicted in
Figure 8-7. As seen above:
-6/2 < e[n] < +6/2
(13)
As a result, the root mean squared value of ern] is proportional to ~, which in turn is inversely
proportional to 2B where B is the number of bits in the binary coded samples. Thus, the signal-toquantization noise ratio defined as:
SNR = 10· 10
(si9~al power)
(14)
910 nOise power
increases by 6 dB for each doubling of the number of quantization levels (i.e., for each additional bit
in the word length).
Another important point is that from the viewpoint of statistical measurements, the sequence of
noise samples appears to be uniformly distributed in amplitude and uncorrelated from sample to
sample whenever the number of quantization levels (bits) is large. Thus, the model of the A-to-D
conversion operation in Figure 8-7 consists of an ideal sampler whose output samples are corrupted
by an additive white noise whose power increases exponentially as the number of bits/sample
decreases.
SAMPLER
-------_...
x[n]
=
A-
x(nT)
x(n)
A-TO-D CONVERTER
FIGURE 8-7 -
I
8.2
QUANTIZATION AS ADDITIVE NOISE
BASIC THEORY OF DISCRETE SIGNALS AND SYSTEMS
Since signals are represented in discrete form as sequences of samples, a discrete system or digital
signal processor is simply a computational algorithm for transforming an input sequence of samples
into an output sequence.
8.2.1
Linear Systems
As in analog systems, a linear system is one which obeys the principle of superposition, and a timeinvariant (or in general, shift-invariant) system is one for which the input-to-output transformation
algorithm does not change with time. linear time-invariant systems are exceedingly important
because they are relatively easy to design and because they can be used to perform a wide variety of
signal processing functions.
As a direct consequence of linearity and time invariance, the output sequence for any linear timeinvariant system is obtained from the input sequence by the repeated evaluation of the convolution
sum relation:
00
y [n] =
~
h [k] . x [n-k]
-oo wN. The frequency wN is often
called the Nyquist frequency. Figure 8-88 shows the Fourier transform of a sequence of samples
where the sampling frequency wS = 2nlT is such that wS > 2wN. Figure 8-8c shows the case when
wS > 2wN. No aliasing distortion occurs if Xa(w) is bandlimited and if the sampling frequency is
greater than twice the Nyquist frequency. Thus, it is essential that analog signals be bandlimited to
the proper frequency before sampling. Even if the signal is 'naturally' bandlimited, it is well to
remember that since additive noise may have a much broader spectrum than the signal, analog
lowpass filtering is almost always necessary prior to sampling. Since it is generally desirable to
minimize the sampling rate so as to minimize the computational intensity of the processor, sharp
cutoff analog filters may be required. In situations where the expense of such filters is prohibitive,
but sufficient numerical processing capability is available, it is possible to use low-order analog
filters and sample at a higher sampling rate to avoid aliasing. Then, the resulting sequence of
samples can be filtered digitally and the sampling rate reduced appropriately by decimating
(throwing away samples) the digitally filtered sequence. [2] Such techniques are also useful in
implementing low-noise A-to-O conversion systems, using delta modulation or other simple
digitizing systems. [5]
A
I
FIGURE 8-8A - FOURIER TRANSFORM OF ANALOG SIGNAL
AfT
FIGURE 8-88 - FOURIER TRANSFORM OF SAMPLES FOR 2n/T > 200N
8-8
AfT
-211"
T
211"
T
T
FIGURE 8-8C -
w
FOURIER TRANSFORM OF SAMPLES FOR 2nlT > 2coN
FIGURE 8-8 - FOURIER TRANSFORM SAMPLING
8.3
DESIGN AND IMPLEMENTATION OF DIGITAL FILTERS
Linear filtering is one of the most important digital signal processing operations. As in the analog
system, digital filters can be used for separating signals from noise, for compensating for previous
linear distortions, for separating signal components from an additive combination of signals, and in
modeling of many classes of signals. Some of the important techniques for implementation and
design of digital filters are presented in the following paragraphs.
8.3.1
Digital Filter Structures
There are two classes of linear shift-invariant systems. The first class contains all such systems for
which the unit sample response is of finite length, e.g., h[n] = 0 for n > 0 and for n > M. Such
systems are called finite duration impulse response (FIR) systems. For such systems, it is clear from
the convolution sum equation (15) that:
M
(21)
y[n] = ~ h[k]· x[n-k]
k=Q
so that the computation of each value of the output sequence requires M + 1 multiplications and M
additions, i.e., the accumulation of M + 1 products. Thus, the convolution sum expression can be
used to implement FIR systems.
Systems which have infinite duration impulse responses are called IIR systems. In general, it is not
feasible to use the convolution sum expression to compute the output of such systems. However,
an interesting and useful class of IIR systems does exist. These are systems whose input and output
satisfy a linear constant coefficient difference equation of the form:
N
M
(22)
y [n] = ~ akY [n-k] + ~ bkx [n-kl
k=1
k=Q
For such systems, this equation can be used recursively to compute the output from the input
sequence and N previously computed output samples. When all the ak's are zero, (22) reduces to
(21) so that (22) turns out to be a general description of all computationally feasible (Le., realizable)
linear time-invariant systems.
By finding the z-transform of both sides of (22), the transfer function of this class of systems is
easily found to be:
M
(23)
~ bk Z - k
H(z)
k=Q
8-9
I
Since bkx[n-k] has z-transform bkz-kX(z), there is a direct correspondence between terms in the
numerator and denominator of H(z) in (23) and terms in the difference equation (22).
Block diagrams may be used to depict the computational procedure for implementing a digital filter.
Figure 8-9 depicts two systems whose input and output satisfy the difference equation (22) and
thus have the same transfer function (23). The operation of addition and multiplication are
represented in standard block diagram notation while the delays are represented by systems with
transfer functins z _1. (M = N = 4 is used for convenience only.) Figure 8-9A shows the direct
representation of the difference equation (22). This is sometimes called the Direct Form I structure
for a system with transfer function (23). If N = 0 (i.e., all the ak's are zero), then the system is a FIR
system. Thus, the left half of Figure 8-9A is illustrative of the general Direct Form implementation of
a FIR system. Also note that in general the left half implements the numerator (or zeros) of H(z)
while the right half implements the denominator (or poles) of the transfer function.
y[n]
x[n]
I
z-1
z-1
FIGURE 8-9A - DIRECT FORM I
8-10
y[n]
x[n]
FIGURE 8-98 - DIRECT FORM II
FIGURE 8-9 - DIRECT FORMS I AND II
Figure 8-S8 is obtained from Figure 8-SA. For linear time-invariant systems in cascade, the overall
transfer function is the product of the individual transfer functions. Thus, the overall transfer
function is the same regardless of the order in which the systems are cascaded. If the two
subsystems of Figure 8-SA are interchanged, the delay chains of the two systems can be combined.
This structure is often called the Direct Form II. Both forms require the same number of arithmetic
operations, but the Direct Form II requires up to 50 percent fewer memory registers for storing the
past values of the input and output. It is important to understand that although both forms have the
same overall transfer function, they correspond to different difference equations. The difference
equation for Figure 8-SA is given in (22) while the set of difference equations represented by Figure
8-S8 is:
N
(24A)
w[n] = ~ akw[n-k] + x[n]
k=1
y[n]
=
M
~
bkw[n-k]
(248)
k=O
Other structures (sets of difference equations) can be found for implementing a given rational
transfer function such as (23). The cascade form is obtained by factoring the numerator and
denominator of H(z) into second-order factors and pairing numerator and denominator factors to
form:
(25)
For simplicity it is assumed that N is even. When N is odd or when M =I N, some of the coefficients
in (25) will be zero. The structure suggested by (25) can be implemented with a cascade of secondorder sections implemented in any desired form. Figure 8-10 shows an example for N = 4.
8-11
I
x[n]
z-1
z-1
a22
FIGURE 8-10 - CASCADE STRUCTURE FOR N = 4
The corresponding set of difference equations is:
(26A)
yo[n] = A ·x[n]
a1k w k[n-1] + a2k w k[n-2] + Yk-1 [n]
k = 1, 2, ... , N/2
k
Yk[n]
y[n]
=
= 1, 2, ...
, N/2
(268)
(26C)
YN [n]
(260)
2"
Still another form for the general transfer function of (25) is obtained from a partial fraction
expansion of H(z) in the form of:
I
N
H(z)
=
AO
+
2"
~
bOk + b 1k Z- 1
(27)
k=1 1 - a1 kZ-1 - a2k z- 2
The set of difference equations corresponding to this form of the transfer function is:
wk[n] = a1kw k[n-1] + a2k w k[n-2] + x[n]
k
= 1, 2, ... , N/2
(28A)
Yk [n] = bOkwk [n] + b1 kWk [n-1]
k
= 1, 2, ... , N/2
(288)
N
Y [ n]
=
2"
AOx [n]
+
~
Y k [ n]
(28C)
k=1
There is literally an infinite number of alternative structures for implementing a digital filter with a
given transfer function, but the ones discussed above are the most commonly used because of the
ease with which they can be obtained from the transfer function and, in the case of the cascade and
parallel forms, because they are relatively insensitive to coefficient quantization and round-off
errors. It is important to note that the basic arithmetic process in digital filtering is multiplication of a
delayed sequence value by a fixed coefficient, followed by the accumulation of the result. This is a
built-in operation of the TMS32010.
8-12
8.3.2
Digital Filter Design
A number of ways to implement a linear time-invariant system having a rational transfer function
have been presented. Designing the system to meet a set of prescribed specifications is equally
important. The specifications for a filter design are most frequently applied to the frequency
response of the filter, i.e., to the Fourier transform of the impulse response. For example, a
frequency selective filter, such as a lowpass, bandpass, highpass, or bandstop filter, may be
required; or an approximation of a differentiator frequency response (i.e., jw), or a 90-degree phase
shift, or in the case of compensators or equalizers, an approximation of the reciprocal of some given
frequency response may be desired. In all these cases, the designer is concerned with finding the
bk'S in the FIR case, or the ak's and bk's in the IIR case, so that the corresponding H{eiwT)
approximates a desired function according to some approximation error criterion. Many
approximation techniques exist, and it is possible to design very accurate approximations to a wide
variety of frequency responses.
A valuable collection of digital filter design programs is available from IEEE Press. [6] A reader who
wants to use these programs or to write design programs is encouraged to consult the texts and
reference books [1,3,7] on digital signal processing to obtain a complete understanding of each
method. The following paragraphs include a survey of the important techniques, along with the
advantages and limitations of each one.
The design of IIR filters has traditionally been based upon the transformation of an analog filter
approximation to a digital filter. The basic approaches are impulse invariance and bilinear
transformation. The former approach is based upon defining the unit sample response of the digital
filter to be the sequence obtained by sampling the impulse response of an analog filter. In this case,
the analog filter must be designed so that the resulting digital filter will meet its specifications.
Because of the aliasing inherent in sampling, the impulse invariance method is not effective for
highpass or bandstop filter types, and the detailed shape of the analog frequency response is
preserved only in highly bandlimited cases, such as lowpass filters with high stopband attenuation.
In the bilinear transformation method, the system function H(z) of the digital filter is obtained by an
algebraic (bilinear) transformation of the system function (Laplace transform of the impulse
response) of an analog filter, i.e., the Laplace variable s is replaced by 2(1 - z - 1 )/(1 + z - 1).
Because the bilinear transformation causes a warping of the jw-axis of the s-plane onto the unit
circle of the z-plane, the bilinear transformation method is useful primarily for the design of
frequency selective filters where the frequency response consists of flat passbands and stopbands.
The passband and stopband cutoff frequencies of the analog filter must be 'prewarped' so that the
resulting digital filter meets its specifications. Because the bilinear transformation maps the entire
jw-axis of the s-plane onto the unit circle, the equiripple amplitude response of an elliptic filter will
be preserved. Thus, optimal magnitude responses can be obtained for IIR filters using bilinear
transformation of analog elliptic filters.
8-13
A major reason that the above methods are widely used is the existence of a variety of
approximation methods for analog frequency selective filters. That is, one can use the Butterworth,
Bessel, Chebyshev, or elliptic filter approximation methods for the analog filter and then simply
transform the analog filter to a digital filter by either the impulse invariance or bilinear
transformation methods. As an illustration of this general method, Figure 8-11 A shows the
magnitude response and Figure 8-11 B shows the phase response of a fourth-order elliptic filter
obtained by the bilinear transformation method. The difference equations for implementation of this
filter as a cascade of two second-order Direct Form II sections are:
yo[n]
w1 [n]
=
(29A)
0.11928·x[n]
= 0.34863' w1 [n-1] - 0.17168 . w1 [n-2] + YO [n]
y 1 [n]
=
w 1 [n] + 1.8345 . w 1 [n -1] + w 1 [n - 2]
w2[n] = -0.12362' w2[n-1] - 0.71406 . w2[n-2]
Y2[n]
=
+ Y1 [n]
w2[n] + 1.26185 . w2[n-1] + w2[n-2]
y[n]
=
Y2[n]
(29B)
(29C)
(290)
(29E)
(29F)
The block diagram representation for the above set of difference equations is identical to Figure
8-10, with the appropriate identification of the coefficients.
o
I
iii
~
w
c
-30
:l
t-
2:
(!)
«
2
(!)
0
...I
-60
-90
o
NORMALIZED FREQUENCY (RADIANS/SAMPLE)
FIGURE 8-11A - LOG MAGNITUDE OF FREQUENCY RESPONSE
8-14
4
en
z
«
2i
«
!;
2
w
....
C!J
Z
«
0
w
CJ)
«
:I:
D..
-2
-4
----------~~----------r_----------r_----------r_--------~
o
NORMALIZED FREQUENCY (RADIANS/SAMPLE)
FIGURE 8-118 - PHASE ANGLE OF FREQUENCY RESPONSE
FIGURE 8-11 - FOURTH-ORDER ELLIPTIC DIGITAL FILTER
It is relatively simple to design IIR filters using tables of analog filter designs and a calculator.
Alternatively, a program for designing IIR digital filters by bilinear transformation of Butterworth,
Chebyshev, and elliptic filters has been given by Dehner in the IEEE Press Book. [6, Section 6.1]
The bilinear transformation method can be termed a Iclosed form' solution to the IIR digital filter
design problem in the sense that an analog filter can be found in a non-iterative manner to meet a
set of prescribed approximation error specifications, and then the digital filter can be obtained in a
straightforward way by applying the bilinear transformation.
Another approach is as follows:
1) Define an ideal frequency response function,
2) Set up an approximation error criterion,
3) Pick an implementation structure, i.e., order of numerator and denominator of H(z),
cascade, parallel, or direct form,
4) Vary the filter coefficients systematically to minimize the approximation error criterion,
5) If the approximation is not good enough, increase the order of the system and repeat the
design process.
8-15
iterative design techniques have been proposed for both IIR and FIR filters.
oped a design program which minimizes a pth-order error norm. It is capable of
and group delay (negative derivative of phase with respect to frequency)
[6, Section 6.2] Another optimization program for magnitude approximations only
n by Dolan and Kaiser. [6, Section 6.3] Both this program and the Deczky program
e transfer function H(z) is a product of second-order factors.
fferent approaches have been developed for the design of FIR filters, since there really
rpart of the FIR filter for the analog system. In addition, FIR discrete-time filters can
ctly linear phase response. Since a linear phase response corresponds to only a delay,
atterll.".
10 be focused on approximating the desired magnitude response without concern for the
phase. In most IIR design methods, the phase is ignored, and one is forced to accept whatever
phase distortion is imposed by the design procedure. The condition for linear phase of a casual FIR
system is the symmetry condition:
h[n]
±h [M-n]
o
(30)
otherwise
In the case of the + sign in (30), the frequency response will be:
H (e jw T) = R (w T) . e
. T (M)
--
-JW
(31 )
2
where R(wT) is a real function of frequency. Such frequency responses are appropriate for
approximating frequency selective filters. In the case of the minus sign in (30):
. T(M)
-2
.
-Jw
H(eJwT ) = jl(wT) . e
(32)
where I(wT) is also a real function of frequency. Such frequency responses are required for
approximating differentiators and Hilbert transformers (90-degree phase shifters).
The most straightforward approach to the design of FIR filters is a technique often called the
'window method.' In this approach, an ideal frequency response function is first defined. Then, the
corresponding ideal impulse response is determined by evaluating the inverse Fourier transform of
the ideal frequency response. (In picking the ideal frequency response, the linear phase condition
mayor may not be applied depending on what is most appropriate.) The ideal impulse response will
in general be of infinite length. An' approximate impulse response is computed by truncating the
ideal impuse response to a finite number of samples and tapering the remaining samples with a
window function. With appropriate choice of the window function, a smooth approximation to the
ideal frequency response is obtained even at points of discontinuity. Many window functions have
been proposed, but the most useful window for filter design is perhaps the one proposed by Kaiser
[8] since it has a parameter which, in conjunction with the window length, can be used
systematically to trade off between approximation error in slowly varying regions of the ideal
response (e.g., the stopband) and sharpness of transition at discontinuities of the ideal frequency
response. A program for window design of FIR frequency selective filters is given by Rabiner and
McGonegal [6, Section 5.2]
I
8-16
FIR filters designed by the window method are not optimal, but in many cases the flexibility and
simplicity of the method outweigh the relatively small cost of increased filter length. In cases where
optimal designs are required for computationally efficient implementations, the Parks-McClellan
algorithm can be used to obtain equiripple or Chebyshev-type approximations. Such designs are
optimal in the sense of having the sharpest transitions between passbands and stopbands for a
given filter length and approximation error. This iterative algorithm is based upon the principles of
the Remez exchange algorithm. A program written by McClellan, Parks, and Rabiner is capable of
designing frequency selective FIR filters as well as differentiators and gO-degree phase shifters. [6,
Section 5.1] An example of the type of filters obtainable by this method is shown in Figure 8-12.
Only the magnitude response is shown since the phase is linear. The impulse response of this
system is given in Figure 8-13. With the symmetry of h[k], the difference equation for computing
the filtered output is:
15
y[n] = h[16] . x[n-16] +
~
h[k] [x[n-k] + x [n+k-32] ]
(33)
k=O
where h[k] is as given in Figure 8-13. (Note that M = 32.)
30~------------------------------------------~
iii
0
~
w
0
::::)
~
Z -30
~
«
:?!
~
0
...I
-60
I
-90L---------------------------------------------~
o
NORMALIZED FREQUENCY (RADIANS/SAMPLE)
NOTE: This FIR lowpass filter was designed by the Parks-McClellan algorithm (M
=32). The phase is linear with slope corresponding to
a delay of 16 samples.
FIGURE 8-12 - FREQUENCY RESPONSE OF FIR LOWPASS FILTER
8-17
IMPULSE RESPONSE OF EQUIRIPPLE LOWPASS FILTER
H(O)
H(1 )
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(9)
H(10)
H(11 )
H(12)
H(13)
H(14)
H(15)
H(16)
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
58211200E-02
12569420E-01
11188270E-01
49952310E-02
14605940E-01
29798820E-02
22352550E-01
42574740E-02
30249490E-01
17506790E-01
37882950E-01
41403080E-01
44224020E-01
91748770E-01
48421950E-01
31334940E-OO
54989020E-OO
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
H(32)
H(31)
H(30)
H(29)
H(28)
H(27)
H(26)
H(25)
H(24)
H(23)
H(22)
H(21)
H(20)
H(19)
H(18)
H(17)
H(16)
FIGURE 8-13 - IMPULSE RESPONSE OF EQUIRIPPLE LOWPASS FILTER
8.4
QUANTIZATION EFFECTS
When digital filters are implemented on any computer, the finite precision of the machine can lead
to deviations from ideal performance. Problems which arise are due to quantization of the
coefficients of the difference equation and roundoff of products prior to accumulation or roundoff
of accumulated products.
When a discrete system is designed to meet a certain set of specifications, the design program
usually will compute the filter coefficients using floating-point arithmetic and the output of the
design program will be a set of coefficients specified to at least 32 -bit floating-point precision.
When these coefficients are used in a fixed-point implementation, it is generally necessary to
quantize the coefficients to fewer bits, e.g., 16 bits. The resulting frequency response will differ
from the original design. It may not meet the original specifications and may even be unstable. This
is analogous to the component tolerance problem in implementing analog active filters. Sensitivity
of the frequency response to errors in a given coefficient is dependent upon the nature of the
desired frequency response, and thus it is difficult to obtain theoretical results with wide generality.
However, it is well established both theoretically and experimentally that the direct-form
implementation structures for high-order filters are in general much more sensitive to coefficient
quantization errors than the equivalent cascade or parallel-form implementations using secondorder sections. Therefore, these structures are generally to be preferred in small word-length
implementations.
I
The design program of Dehner [6, Section 6.1] has an option for optimizing filter response with
constraints on word length. Steiglitz and Ladendorf have also given an iterative program for
designing finite word-length IIR filters. [6, Section 6.4] A program for finite word-length design of
FIR filters has been written by Heute. [6, Section 5.4]
Another source of imperfection in implementing digital filters is the 'roundoff noise' that results
from quantization of intermediate computations in the difference equation. This problem is
particularly acute in IIR filters, where the recursive nature of the implementation algorithm leads to a
required word-length that increases linearly with time or to errors which propagate to future
computations. For example, with 16-bit input samples and 16-bit coefficients, the first output value
will require up to 32-bits for its representation, and in a recursive filter, the next output value will
8-18
require 32 + 16, etc. Thus, the products continually must be reduced to fit the word length of the
processor. However, the TMS320 has a full 32-bit accumulator so that 16-bit by 16-bit products
need not be rounded before addition. Thus, in implementing digital filters, each output value can be
computed with 32-bit precision and then rounded to 16-bits for output or for storage of delayed
variables.
It can be seen from (21) and (22) that in implementing digital filters, the basic operation is a multiply
followed by an accumulate (addition of the product to the sum of previously computed products).
An obvious additional problem is the danger of overflow of the accumulator word length. Overflow
can be eliminated as a problem by using floating-point arithmetic. However, this leads to
quantization of both sums and products, and implementation for floating-point arithmetic leads to
much higher costs in processors like the TMS320.
Rounding in digital filter implementations leads to errors in the output of the filters. In many cases,
these errors can be modeled as additive noise which is generated by noise sources in the filter
structure. (This is analogous to thermal noise generated by resistors in analog active filters.) In other
cases, the nonlinear nature of the quantization of products or overflow can lead to a much different
effect, i.e., periodic patterns of error samples are generated in the output. These 'limit cycles' are
particularly troublesome in situations where the input becomes zero for lengthy intervals. Certain
structures have been found which are free of limit cycle behavior. However, these require
somewhat more computation than the standard forms. [9] An important point is that limit cycles
cannot exist in the output of FIR filters. Since there is no feedback, the output of a FIR system
obviously becomes zero if the input is zero over an interval equal to or greater than the length of the
unit sample response. [1,3,7]
8.5
SPECTRUM ANALYSIS
Spectrum analysis is another major area of digital signal processing. Spectrum analysis consists of a
collection of techniques which are directed either toward the computation of the Fourier transform
of a deterministic signal or toward estimation of the power spectral density of a random signal. In
the following paragraphs are presented the important concepts and algorithms in discrete-time
spectrum analysis.
8.5.1
I
Discrete Fourier Transform (OFT)
The discrete Fourier transform (OFT) of a finite length sequence is defined as:
X[k]
N-1
= ~
n=O
"
x[n] e-J27Tkn/N
Q~ k
~ N-1
The DFT is simply a sampled version of the discrete-time Fourier transform of x[n], Le.:
jw
X[k] = X(e k T)
(34)
(35)
where Wk = 2nkl (NT), k = 0, 1, ... , N - 1. Thus, the OFT is a set of samples of the discrete-time
Fourier transform at N equally spaced frequencies from zero frequency up to (but not including) the
sampling frequency wS = 2n1T.
The inverse discrete Fourier transform (10FT) is:
1 N-1
"2 k IN
x [n] = ~
X [k] eJ 7T n
0 ~ n ~ N-1
(36)
N k=Q
The OFT (34) and its inverse (36) provide an exact Fourier representation for finite length
sequences. However, an important property of the 10FT relation (36) is that if it is evaluated for
values of n outside the interval 0 ~ n ~ N - 1, the result is not zero but rather a periodic repetition
of x[n]. Thus, the OFT analysis and synthesis pair, (34) and (36), can also be thought of as a Fourier
series representation for periodic sequences. Whether (34) and (36) represent a finite-length
8-19
sequence or a periodic sequence is only a matter of what is assumed about the sequence outside
the interval 0 ~ n ~ N - 1. Nevertheless, (36) does repeat periodically outside the interval if it is
evaluated there, and it is this property that leads to a need to be careful in its use and also to
efficient computational algorithms for its evaluation. [1 ]
8.5.2
Fast Fourier Transform (FFT)
The fast Fourier transform (FFT) is a generic term for a collection of algorithms for efficiently
evaluating the DFT or 10FT. These algorithms are all based upon the general principle of breaking
down the computation of the N accumulations of N products (N2 multiplications and additions)
called for by either (34) or (36) into a number of smaller OFT-like computations. Because of the
periodicity and the symmetry of the quantities e-j2pkn/N, many of the multiplications and additions
can be eliminated. In fact, by increasing the control and indexing aspects of the algorithm, the
amount of numerical computation can be reduced to be proportional to N.log N rather than
proportional to N2. For large N, the savings in arithmetic computation can be several orders -of
magnitude.
The basic arithmetic operation in a FFT algorithm is a (complex) multiply-accumulate operation,
which can be easily and efficiently realized with the TMS320 10. The details of many FFT algorithms
can be found in references and textbooks on digital signal processing. [1,3,7]
A number of FORTRAN programs for FFT algorithms are contained in the IEEE Press Book. [6,
Section 1] They range in complexity from very simple programs where N must be a power of two, to
more complex (and thus more efficient) mixed radix algorithms. Although these programs cannot
be run directly on the TMS32010, they do serve as a convenient and readable description of the
algorithm which could be translated readily into a TMS32010 program.
8.5.3
Uses of the OFT and FFT
Since highly efficient computation of the OFT is possible, and since Fourier analysis is such a
fundamental concept in signal and system theory, it is natural that many uses have been found for
the OFT. One major class of applications is in the computation of convolutions or correlations. If
x[n] and h[n] are convolved to produce y[n] (i.e., linear filtering), then the Fourier transforms of
these sequences are related by:
(37)
Y(e jw T) = H (e jw T) . X(e jw T)
I
Since the OFT is just a sampled version of the discrete-time Fourier transform, it is also true that:
(38)
Y[k] = H[k] . X[k]
O~k~N-1
and if x[n], h[n], and the y[n] resulting from their convolution are all less than or equal to N in
length, then y[n] can be computed as the 10FT of Y[k] in (38), Due to the great efficiency of the
FFT, it may be more efficient in some cases to compute X[k] and H[k], mUltiply them together, and
then compute y[n] using the IFFT than to compute y[n] directly by discrete convolution. Such a
scheme is depicted in Figure 8-14. Since correlations can be computed by time-reversing one of the
sequences before convolution, Figure 8-14 also represents a technique for computing both autoand cross-correlation functions.
When the lengths of the sequences are larger than the available random access memory, or when
real-time operation with minimal delay is required, there are schemes whereby the output can be
computed in sections. [1,3,7]
8-20
x[n]
.....
-..
FFT
X[k]
..
X
Y[k] ...
IFFT
~~
..
--.
y[n]
H[k]
FFT
A.
h[n]
FIGURE 8-14 - A DISCRETE CONVOLUTION USING THE FFT
Another use of the OFT / FFT is in the computation of estimates of the Fourier transform or the
power spectrum of an analog signal. The three basic concerns in this application are depicted in
Figure 8-15. First, the analog signal > 0
2
2
1
1
1
1
1
o
0
0
0
+----- BRANCH
BIOZ
Branch on BIO
2
2
o
0 0 0
+----- BRANCH
1
1
1
1
101
0
0
0
+--
1
~
=0
1
1
100 1 0
0
+----- BRANCH
1 101
0
0
101
0
0
0
0
0
000 0
0
000 0
000 0
~ BRANCH ADDRESS
1 0
0
0
0
0
ADDRESS - .
0
0
0
---+
000 0
0
0
ADDRESS ~
1111011000000000
ADDRESS
---+
100 000 0
0
0
BLEZ
Branch if accumulator :5 0
2
2
o
BLZ
Branch if accumulator
< 0
2
2
1
1
1
101
o
0 0 0
~
BNZ
Branch if accumulator
*- 0
2
2
1
1
1
1
1
o
0
0
0
4 - - BRANCH ADDRESS - - - .
BV
Branch on overflow
2
2
o
0
0
0
~
1
1
1
1
1
o
o
0
0
0
~ BRANCH ADDRESS
1
1
1
1
1
1
1
1
1 0
o
0
0
0
+----- BRANCH
o
1
1
1
1
BZ
Branch if accumulator = 0
2
CALA
Call subroutine from accumulator
2
CALL
Call subroutine immediately
2
RET
Return from subroutine or interrupt routine
2
2
2
1
BRANCH ADDRESS ~
000 0
000 0
0
BRANCH ADDRESS----'
1 0
0
0
0
000 0
0
1111010100000000
1
1
1
1
1
BRANCH ADDRESS----+
1 0
1
0 0
1
1
0
0
000 0
1 000
0
0
0
---+
1 100
000 0
0
0
ADDRESS-'
1 000
1 101
T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS
MNEMONIC
I
DESCRIPTION
NO.
NO.
CYCLES
WORDS
OPCODE
INSTRUCTION REGISTER
151413121110 9 8 7 6 5 4 3 2
1 0
APAC
Add P register to accumulator
1
1
o
1
LT
Load T register
1
1
011010101
4
1
1
o
1
1 0
1
I
4--D----+
1
1
o
1
1 0
1 0
I
.4i---D---4.~
1
1
o
1
1 0
1
I
~4~-D----.~
1
1
1 0 0
44~------K-----~••
LTA
LTD
MPY
MPYK
LT A combines LT and APAC into one
instruction
LTD combines LT, APAC, and DMOV into
one instruction
Multiply with T register, store product in
P register
Multiply T register with immediate
operand; store product in P register
1
1
1
1
1
1
1
1 0 0
1 1
1 0
1
1 000
1
1
1
~
D
PAC
Load accumulator from P register
1
1
o
1
1
1
1
1
1
1
SPAC
Subtract P register from accumulator
1
1
o
1
1
1
1
1
1
1 100 1 000 0
~-10
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
1 000
1
1
1 0
TMS32010
DIGITAL SIGNAL PROCESSOR
TABLE 2. TMS32010 INSTRUCTION SET SUMMARY (CONCLUDED)
CONTROL INSTRUCTIONS
DESCRIPTION
MNEMONIC
NO.
NO.
CYCLES
WORDS
1
DINT
Disable interrupt
1
EINT
Enable interrupt
1
1
LST
Load status register
1
1
NOP
No operation
1
1
POP
POP stack to accumulator
PUSH stack from accumulator
2
2
1
PUSH
ROVM
Reset overflow mode
1
1
SOVM
Set overflow mode
1
1
SST
Store status register
1
1
1
OPCODE
INSTRUCTION REGISTER
1514131211109 8
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
7 6 5 4 3 2 1 0
1 o 0 0 0 0 0 1
1 1 o 0 0 0 0 1 0
1
1
1
1
1
1
1
1
1 0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 1
1 1
1
1
1
1
1
1
1
0
0 0 0 0 0 0
1 1 0 0 1 1 1 0 1
1 1 0 0 1 1 1 0 0
1 1 0 0 0 1 0 1 0
1 1 o 0 0 1 0 1 1
0 I 4
D---.
1
I
4
D
1 0
•
1/0 AND DATA MEMORY OPERATIONS
MNEMONIC
DMOV
DESCRIPTION
Copy contents of data memory location
into next location
IN
Input data from port
OUT
Output data to port
TBLR
TBLW
Table read from program memory to data
RAM
Table write from data RAM to program
OPCODE
NO.
NO.
CYCLES
WORDS
1
1
0
1
2
2
1
0
1 0
0 0
1
0
1 0
0
1
3
1
0
1
1 0
3
1
0
1
1
INSTRUCTION REGISTER
1514131211109 8
1 0
1
7 6 5 4 3 2
I
.-.-D
.PA"
I
.-.-D
.PA"
I
'-'-D
0
1
1
1
I
'--D
1
1
0
1
I
4
1 0
0
1
D
1 0
~
••
•
•
development systems and software support
Texas Instruments offers concentrated development support and complete documentation for designing
a TMS3201 O-based microprocessor system. When developing an application, tools are provided to evaluate
the performance of the processor, to develop the algorithm implementation, and to fully integrate the
design's software and hardware modules. When questions arise, additional support can be obtained by
calling the nearest Texas Instruments Regional Technology Center (RTe).
Sophisticated development operations are performed with the TMS3201 0 Evaluation Module (EVM), Macro •
Assembler/Linker, Simulator, and Emulator (XDS). In the initial phase of developing an application, the
evaluation module is used to characterize the performance of the TMS3201 O. Once this evaluation phase
is completed, the macro assembler and linker are used to translate program modules into object code and
link them together. This puts the program modules into a form which can be loaded into the TMS3201 0
Evaluation Module, Simulator, or Emulator. The simulator provides a quick means for initially debugging
TMS32010 software while the emulator provides real-time in-circuit emulation necessary to perform system
level debug efficiently.
A complete list of TMS3201 0 software and hardware development tools is given in Table 3.
TEXAS . "
INSTRUMENTS
A-1'
TMS32010
DIGITAL SIGNAL PROCESSOR
TABLE 3. TMS32010 SOFTWARE AND HARDWARE SUPPORT
HOST
OPERATING
PART
COMPUTER
SYSTEM
NUMBER
MACRO ASSEMBLERS/LINKERS
DEC VAX
VMS
TMDS3240210-08
DEC VAX
Berkeley UNIX 4.1
TM DS3240220-08
IBM
MVS
TMDS324031 0-08
IBM
CMS
TMDS3240320-08
TI/IBM PC
MS/PC-DOS
TMDS324081 0-02
SIMULATOR
DEC VAX
VMS
TMDS3240211-08
TI/IBM PC
MS/PC-DOS
TMDS3240811-02
DIGITAL FILTER DESIGN PACKAGE (DFDP)
TI PC
MS-DOS
DFDP-TI001
IBM PC
PC-DOS
DFDP-IBMOO 1
HARDWARE
Evaluation Module (EVM)
RTC/EVM320A-03
Analog Interface Board (AlB)
RTC/EVM320C-06
Emulator (XDS/22)
TMDS3262210
absolute maximum ratings over specified temperature range (unless otherwise noted) t
Supply voltage, Vec:t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 7 V
All input voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 1 5 V
Output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 1 5 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.5 W
Air temperature range above operating device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55°C to + 150°C
ooe
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect
device reliability.
:tAli voltage values are with respect to VSS.
I
recommended operating conditions
VCC
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
0
I
I
All inputs except ClKIN
V
2.8
ClKIN
Vil
low-level input voltage (all inputs)
0.8
V
10H
High-level output current (all outputs)
300
p.A
2
mA
70
°c
tOl
low-level output current (all outputs)
TA
Operating free-air temperature
0
NOTES: 1. Case temperature (TC) for the TMS32010-25 and TMS32010FDl must be maintained below 90°C.
2. For dual-in-line package:
ROJA = 51.6°C/Watt
ROJC = 16.6°C/Watt.
For plastic chip-carrier package:
ROJA = 70°C/Watt
ROJC = 20°C/Watt.
A-12
V
2
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
I M:i.:JlU·IU
DIGITAL SIGNAL PROCESSOR
electrical characteristics over specified temperature range (unless otherwise noted)
TEST CONDITIONS
PARAMETER
VOH
High-level output voltage
IOH
VOL
Low-level output voltage
IOL
IOZ
Off-state output current
VCC
II
Input current
VI
ICC t
Supply current
Ci
Input capacitance
Co
Output capacitance
MIN
= MAX
= MAX
=
=
VCC
2.4
I
MAX
I
2.4 V
20
0.4 V
-20
=
=
O°C
70 c C
VSS to VCC
=
I
MAX
TA
I
Data bus
All others
0.5
=
va =
Vo
TA
180
=
1 MHz,
J-tA
J-tA
275
mA
235§
mA
pF
15
25
All other pins 0 V
V
±50
25
f
UNIT
V
3
0.3
Data bus
All others
Typt MAX
pF
10
t All typical values except for ICC are at VCC = 5 V, T A = 25 cC.
tlCC characteristics are inversely proportional to temperature; i.e., ICC decreases approximately linearly with temperature.
§Value derived from characterization data and not tested.
CLOCK CHARACTERISTICS AND TIMING
The TMS3201 0 can use either its internal oscillator or an external frequency source for a clock.
internal clock option
The internal oscillator is enabled by connecting a crystal across X 1 and X2/CLKIN (see Figure 1). The
frequency of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental
mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW,
and be specified at a load capacitance of 20 pF.
PARAMETER
TMS32010
TEST CONDITIONS
MIN
Crystal frequency fx
Cl, C2
OcC - 70 c C
OcC - 70 c C
X1
NOM
6.7
10
TMS32010-25
MAX
MIN
20.5
6.7
NOM
25.0
10
UNIT
MAX
MHz
pF
X2/ClKIN
CRYSTAL
e__--t
0
t--___e
J
C2
FIGURE 1. INTERNAL CLOCK OPTION
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
A-1
DIGITAL SIGNAL PROCESSOR
external clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X 1 left
unconnected. The external frequency injected must conform to the specifications listed in the table below.
timing requirements over recommended operating conditions
TMS32010
MIN
NOM
TMS32010-25
MAX
MIN
150
40
48.78
NOM
MAX
UNIT
150
ns
10
ns
10
ns
0. 5251:c(C)
ns
tc(MC)
Master clock cycle time
tr(MC)
Rise time master clock input
tf(MC)
Fall time master clock input
tw(MCP)
Pulse duration master clock
tw(MCL)
Pulse duration master clock low, tc(MC) = 50 ns
20
18
ns
tw(MCH)
Pulse duration master clock high, tc(MC) = 50 ns
20
18
ns
5
5
O.4751:c(C)
10
5
10
5
O. 5251:c(C) O.475tc(C)
switching characteristics over recommended operating conditions
TEST
PARAMETER
tc(C)
ClKOUT cycle time t
tr(C)
CLKOUT rise time
tf(C)
ClKOUT fall time
tw(CL)
Pulse duration, CLKOUT low
tw(CH)
Pulse duration, CLKOUT high
td(MCC)
Delay time CLKINi to CLKOUT ~:j:
TMS32010-25
TMS32010
CONDITIONS
MIN
NOM
MAX
n
Cl = 100 pF,
See Figure 2
NOM
8
8
ns
92
74
ns
90
72
ns
I
~
INSTRUMENTS
POST OFFICE BOX 1443 •
ns
10
25
TEXAS
UNIT
10
60
25
ttc(C) is the cycle time of CLKOUT, i.e., 4 *tc(MC) (4 times ClKIN cycle time if an external oscillator is used).
:j:Values given were derived from characterization data and are not tested.
~-14
MAX
160
195.12
RL = 870
MIN
HOUSTON. TEXAS 77001
ns
60
ns
I M;jJlUIU
DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION
2.14 V
RL = 870 (}
FROM OUTPUT n--__e
UNDER TEST
TEST
__- - 0 POINT
FIGURE 2. TEST LOAD CIRCUIT
2.0 V_
VIH (MIN)
1.88 V ....
0.80 V-
VIL (MAX)
-------------------------o
(a) INPUT
I
2.4V_
2.0V0.5 V-±==~==-==-=::....:=.=-~===-VOL (MAX)
o
(b) OUTPUTS
FIGURE 3. VolTAGE REFERENCE LEVELS
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
A-1
DIGITAL SIGNAL PROCESSOR
clock timing
--t ,.
tr(MC)
..
t
14
I Icc
X2/ClKIN
1:
I
: tf(MC)
1_
CLKOUT
t.
~
-.I ~
~
..
tw(MCH)
I
~
~
I
I
tw(MCP) t
I \""'__.J/----, /
~
I
~
-I
----...
-I
c(MC)
\~/
tw(MCL)
~~~------------ tw(CH) ------------~~.
I
I
td(MCC)t
~~_ _ _ _ _ _ _ _ _ _ _ _ _ _~t1~----------------~~
-.t
II
t.-
-.I
tf(C)
I.
J
~
tw(CL)--------------~~·
~I.~----------------------------
!...
I
tr(C)
r....
tc(C)
"
--------------------------~~.
NOTE 3: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
ttd(MCC) and tw(MCP) are referenced to an intermediate level of 1.5 volts on the ClKIN waveform.
MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions
TEST
PARAMETER
MIN
CONDITIONS
Delay time CLKOUT! to
td1
MAX
UNIT
10t
50
ns
address bus valid (see Note 4)
td2
Delay time CLKOUT! to MEN!
1i4tc(C) -5 t
1i4tc(C) + 15
ns
td3
Delay time CLKOUT! to MENt
-10t
15
ns
td4
Delay time CLKOUT! to DEN!
1i4tc(C)-5t
1i4tc(C) + 15
ns
td5
Delay time CLKOUT! to DENt
-10t
15
ns
td6
Delay time CLKOUT! to WE!
RL = 870 fl,
1htc(C)-5t
1htc(C)+15
ns
td7
Delay time CLKOUT! to WEt
CL = 100 pF,
-10 t
15
ns
1i4tc(C) +65
ns
See Figure 2
Delay time CLKOUT! to
I
TYP
td8
data bus OUT valid
Time after CLKOUT! that data
td9
ns
1i4tc(C)-5t
bus starts to be driven
Time after CLKOUT! that data
td10
tv
1i4tc(C)+30t
bus stops being driven
Data bus OUT valid after CLKOUT!
ns
ns
1i4tc(C)-10
NOTE 4: Address bus will be valid upon WEt, DENt, or MENt.
tThese values were derived from characterization data and are not tested.
timing requirements over recommended operating conditions
TEST
MIN
CONDITIONS
tsu(D)
Setup time data bus valid prior to CLKOUT!
tsu(A-MD)
Address bus setup time prior to MEN! or DEN!
th(D)
Hold time data bus held valid after CLKOUT!
See Figure 2
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
UNIT
ns
1i4tc(C)-45
0
ns
NOTE 5: Data may be removed from the data bus upon MENt or DENt preceding CLKOUT!.
~-16
MAX
50
RL = 870 fl,
CL = 100 pF,
NOM
ns
3
CD
3
o
~
-<
~
CD
m
c..
~
"--t
~
tc(C)
~
o
(/l
ClKOUT
o"Tl
'{
::!!-
hlZ
tel3-;
~C/l
~~
~~~
.c:~
5~
fiit'l'1
~Z
~Uj.
MEN
/
~
1/
~
All-AD
~
td2
tell
~
I
IV
'i
=:1'-
AOORESSB~SVAUOt
~
l>
(/l
.....
.....
sufO)
~.
~
(
~
--~~_ _ _ __
o
015-00)
/
INSTRUCTION IN VAllO
))-0----------
g
C5
=i
:I=-
r-
en
-2
G)
:I=-
r-
",
....
~3I:
"en
"'w
en N
(1)=
»
I
NOTE 3: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts. unless otherwise noted.
Q~
::D
«=
I
-10
ex>
•
-I
to
r
::XJ
:r
en
C.....j
-:5:
~~
-ICotJ
2:-N
...
...
c
...0'
!:!!c
3'
-a
~
(')
...
~
S'
CQ
~c
C')
2
2:~
::a
=
en
en
=
::a
C"')
m
CLKOUT
."
o
(fl
--t
~
o
/
\
/ ---r
\ /
td3
"T1
::!)-
~Z
~(J)
~~
~~~
.c:~
6~
~(T1
clZ
A11-AO
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~u1.
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11
LEGEND:
1.
TBlR INSTRUCTION PREFETCH
7.
ADDRESS BUS VALID
2.
3.
4.
5.
6.
DUMMY PREFETCH
8.
ADDRESS BUS VALID
DATA FETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
ADDRESS BUS VALID
9.
10.
11.
12.
\
I
t d3
! r-\~
2
MEN
\
/
--..I f4-
INSTRUCTION IN VALID
INSTRUCTION IN VALID
DATA IN VALID
INSTRUCTION IN VALID
NOTE 3: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
4
a
*==
~
to
~
~
:i'
en
.......
C
....
(")
S'
:::l
....
3'
CLKOUT
\
I
\
I
\
I
\
I
\
r
:i'
CO
"o
Cf)
-I
MEN
;;
3
2
:!:'-
~z
~(JJ
=*
~~
E ;tl~
.c:~
A11-AO
I~
~fT1
clZ
~ Ci14r
4
)@(
)@(
5
)@(
6
-.f,.-td7
I.--td6~
,---------
------------~I--~~
WE
}>
'Jl
I+--- t d8
-..J
-..J
o
~
015-00
-t
j4-td91~J..
o
(
8 )
("--9~)
~
~ j4-
t
V
~td10--l
10
.~<
TBLW INSTRUCTION PREFETCH
2.
3.
4.
5.
6.
DUMMY PREFETCH
NEXT INSTRUCTION PREFETCH
11
)~-
-=
c -)
=i
:.:r-
LEGEND:
1.
*==
7
7.
8.
9.
ADDRESS BUS VALID
INSTRUCTION IN VALID
INSTRUCTION IN VALID
ADDRESS BUS VALID
10.
DATA OUT VALID
ADDRESS BUS VALID
11 .
INSTRUCTION IN VALID
ADDRESS BUS VALID
-
(I)
c -)
iii!!
:.:r-
-a .....
~s:
ncn
mw
We
(l)N
»
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-
NOTE 3: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
Q
...
::::a =
-
y
~
o
;2
:r
fA
,...
~
s::
,...
(')
0'
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,...
c .....
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r-=
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3'
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cc
."
5'
=
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n
m
\__ __ 1-
CLKOUT
\
en
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.:!!-
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MEN
~~
~;o~
.c::~
5~
A11-AO
l>
II
DEN
-.J
-.J
\
\
2
I
I
\"--_
_~3~
4a<5~_
-------------X
td5~
I--
~Z
en
\
I
I
I
I
~fT1
~~~
---,I
I
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I
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Q
I
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td4---f
o
o
~-------------
f4-ts~:!.I
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f4--
{7
L..
,..-th(D)
))---0----(
LEGEND:
1.
2.
IN INSTRUCTION PREFETCH
3.
ADDRESS BUS VALID
4.
PERIPHERAL ADDRESS VALID
NEXT INSTRUCTION PREFETCH
5.
6.
7.
8.
ADDRESS BUS VALID
INSTRUCTION IN VALID
DATA IN VALID
INSTRUCTION IN VALID
NOTE 3: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
en
en
0
::a
o
C
-I
:i"
en
...
c:::
...o·n
::J
...
3·
~
:i"
(Q
\
CLKOUT
I
"
0
I
JJ
~ _
MEN
~Z
-
~~
~ ;C~
.C~
~~
I
\
/
_ _
A11-AO
3
_
4
~ td6
~
~td91
WE
(f)
-.J
-.J
0
I
)
015-00
/
I
I
I
I
~f"'J
~Ui4',
\
\!;
bZ
::!
I
I
(f)
--i
/
_
2
5
I
\~
/
_~
--...I f4- td7
~
'{
~ti8
("--6~)
\
\
V~------
tj
8{
t
V
0i
}a--<
=t=;j
7
1d1
8 )
5!
=t
C)
:I=-
r-
en
c;
LEGEND:
1.
2.
3.
4.
OUT INSTRUCTION PREFETCH
NEXT INSTRUCTION PREFETCH
ADDRESS BUS VALID
PERIPHERAL ADDRESS VALID
5.
6.
7.
8.
ADDRESS BUS VALID
i2
:I=-
INSTRUCTION IN VALID
r-
DATA OUT VALID
."
INSTRUCTION IN VALID
=-
=s
n(l:
me...
en
N
enc
>
1
r...>
NOTE 3: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
-
=c
Q-
DIGITAL SIGNAL PROCESSOR
RESET (RS) TIMING
timing requirements over recommended operating conditions
MIN
tsu(R)
Reset (RS) setup time prior to ClKOUT. See Note 6.
twIRl
RS pulse duration
NOM
MAX
UNIT
50
ns
5te(C)
ns
switching characteristics over recommended operating conditions
TEST
PARAMETER
Delay time DENt, WEi, and MENt from RS
td11
MIN
CONDITIONS
TVP
Rl = 870 fl,
MAX
UNIT
1f2tc(C) + 50 t
ns
1f4tc(C) + 50 t
ns
Cl = 100 pF,
Data bus disable time after RS
tdis(R)
See Figure 2
NOTE 6: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.
tThese values were derived from characterization data and are not tested.
reset timing
CLKOUT
~tSU(R)
KtSU(R)
\~~
RS
I..
DEN
WE
MEN
~
tw(R)
I
SEE
NOTE 11
tdis(R)
015-00
sj
- - - -..........
I
~
J
I
~td11
---t ~
S'"cr-_______---c/DATA IN FROMVDATA IN FROM
- - { DOAUTTA \ .....- - - -_________
•
(
;J
DATA SHOWN RELATIVE TO WE
\
ss
PC ADDR 0 r - \ P C ADDR PC + 1
\ ____r\'----
AB = ADDRESS BUS
~~~~=~ X~-A-B-=-P-C-+-1-~_ _ _ _ _ _ _A_B_=_P_C_=_0_ _ _ _ _~*=~+1
NOTES:
3. Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise
noted.
7. RS forces DEN, WE, and MEN high and tristates data bus DO through D15. AS outputs (and program counter) are synchronously
cleared to zero after the next complete ClK cycle from
~RS.
8. RS must be maintained for a minimum of five clock cycles.
9. Resumption of normal program will commence after one complete ClK cycle from tRS.
10. Due to the synchronizing action on RS, time to execute the function can vary dependent upon when tRS or
the ClK cycle.
11. Diagram shown is for definition purpose only. DEN, WE, and MEN are mutually exclusive.
12. During a write cycle, RS may produce an invalid write address.
.-22
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
~RS
occur in
TMS3201D
DIGITAL SIGNAL PROCESSOR
INTERRUPT (lNT) TIMING
timing requirements over recommended operating conditions
MIN
NOM
MAX
15
tf(INT)
Fall time INT
tw(lNT)
Pulse duration INT
tsu(lNT)
Setup time INT! before CLKOUT!
UNIT
ns
tc(C)
ns
50
ns
interrupt timing
CLKOUT
_/
\_'-----'1
\""--'----'/
"r..---~. .
tSU(lNT)
~I'--------'li
J
tf(lNT)~ ~
,..---tW(INT)-----4I~~
NOTE 3: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
I/O (BIO) TIMING
timing requirements over recommended operating conditions
MIN
NOM
MAX
15
tf(lO)
Fall time BIO
tw(lO)
Pulse duration BIO
tsu(lOI
Setup time BIO! before CLKOUT!
UNIT
ns
tc(C)
ns
50
ns
BIO timing
CLKOUT
/
/
\
~
~
I
L
I
f4-
J4
/
tsu(lO)
~
tf(lO)~
\
I
tw(lO)
~
NOTE 3: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
TEXAS . "
INSTRUMENTS
A-2:
TMS32010
DIGITAL SIGNAL PROCESSOR
input synchronization requirements
For systems using asynchronous inputs to the INT and BIO pins on the TMS3201 0, the external hardware
shown in the diagrams below is recommended to ensure proper execution of interrupts and the 810Z
instruction. This hardware synchronizes the INT and BIO input signals with the rising edge of CLKOUT
on the TMS3201 O. The pulse width required for these input signals is tc(C), which is one TMS3201 0 clock
cycle, plus sufficient setup time for the flip-flop (dependent upon the flip-flop used).
I
P
INTERRUPT INPUT SIGNAL
(ACTIVE LOW)
0
a
INT
SN74ALS74
-
~
C
TMS32010
I
+5 V
CLKOUT
I
BIO INPUT SIGNAL
(ACTIVE LOW)
P
0
-
810
Q
SN74ALS74
~
TMS32010
C
I
+5 V
CLKOUT
TI standard symbolization for devices without on-chip ROM
MEANINGS OF SYMBOLS
SYMBOLIZATION
line 1:
~-24
(a)
line 2:
(c)
line 3:
(e)
~
(b)
©1983 TI
(d)
TMS32010NL
DCU8327
24655
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
(a)
Texas Instruments trademark
(b)
Standard device number
(c)
TI design copyright
(d)
Tracking mark and date code
(e)
Lot code
IIYI~"'~U
IU
DIGITAL SIGNAL PROCESSOR
THERMAL DATA
thermal resistance characteristics
PACKAGE
40-pin plastic dual-in-line package
44-lead plastic chip carrier package
ROJA
(OC/W)
ROJC
(CC/W)
51.6
16.6
70
20
MECHANICAL DATA
40-pin plastic dual-in-line package
1 4 - - - - - - - - 53,1 (2.090) MAX - - - - - - - - . . .
EITHER OR BOTH
INDEX MARKS
o
ct.
15,24±0,25
ct.
~.600±0'010~
0.51~?N020)
It= ~~n~~~
0,28±0,08-1r(0.011 ±0.003)
-@
0,457±0,076
--II+-
5.08 (0.200) MAX
~
~
MIN~ I..=:JJI~l.-
2,92 (0.115) MIN
(0.018±0.003)
PIN SPACING 2,54 (0.100) T.P.
(SEE NOTE A)
0,84 (0.033)
2.41 (0.095)
1,40 (0.055)
1,52 (0.060) NOM
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Each pin centerline is located within 0,254 (0.010) of its true longitudinal position.
'Ii1
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
A-2
I M:i..1lUIU
DIGITAL SIGNAL PROCESSOR
44-lead plastic chip carrier package
(0.695) _ _ _ _ _ _ _~
17 AO (0.685)
1 4 - - - - - - - - - 17.65
4- - - - - - - -
r
16.66 (0.656)
16.51 (D.65D)
28
27
26
25
24
23
22
-------+11
~. _ _ _ _ _ _ _-,-
21
20
19
18
~
17
30
31
32
33
17.65 (0.695)
17.40 (0.685)
34
16.66 (0.656)
16.51 (0.650)
36
38
39
4.57 (0.180) - 1 4 - - - - - - . 1
4.19 (0.165)
3.05 (0. 120) 4oe--~
2.29 (0.090)
0.51 (0.020)
MIN
I
0.533 (0.021)
0.330 (0.013)
16.00 (0.630)
14.99 (0.590)
...,.......,=,"",--r-oL
1.27 (0.050)
TYP
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
A-26
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
APPENDIX B
SMJ32010 DATA SHEET
I
I
B-2
SMJ32010
DIGITAL SIGNAL PROCESSOR
MAY 1983 -
REVISED OCTOBER 1985
JD PACKAGE
•
DeSC Approved
-SMJ32010JDS DeSC No. 8405301QC
-SMJ32010FDS DeSC No. 8405301ZC
•
MIL-STD-883C Class B Processing
•
Same Features and Specifications as
TMS32010 over O°C - 70°C Temperature
Range
•
Currently Microprocessor Mode Only (All
Program Memory Is Extended)
•
144-Word On-Chip Data RAM
•
External Memory Expansion to Total of 4K
Words at Full Speed
•
16-Bit Instruction/Data Word
•
32-Bit ALU/Accumulator
•
16 x 16-Bit Multiply in One Instruction Cycle
•
0 to 16-Bit Barrel Shifter
•
Eight Input and Eight Output Channels
•
16-Bit Bidirectional Data Bus with
40-Megabits-per-Second Transfer Rate
(TOP VIEW)
A 1/PA 1
AO/PAO
MC/MP
RS
INT
CLKOUT
X1
X2/CLKIN
BIO
VSS
08
09
010
011
012
013
014
015
07
06
A2/PA2
A3
A4
A5
A6
A7
A8
MEN
OEN
WE
VCC
A9
A10
A 11
00
01
02
03
04
05
44-PAD FD PACKAGE
LEAD LESS CERAMIC CHIP CARRIER
•
Interrupt with Full Context Save
•
Signed Two's-Complement Fixed-Point
Arithmetic
•
2.4-Micron NMOS Technology
•
Single 5-V Supply [± 10% for (- 55°C to
100 0 C) Temperature Range (S Suffix)]
(TOP VIEW)
description
<
e::
I~ I~ ~ ~ ~ ~ <~ ~ ~ ~
I~-e::e::
~~
CLKOUT
X1
X2/CLKIN
BIO
NC
VSS
08
09
010
011
012 17
A7
A8
MEN
The SMJ3201 0 is a member of the new
WE
TMS320 digital signal processing family,
VCC
designed to support a wide range of high-speed
A9
or numeric-intensive applications. This 16/32-bit
A10
single-chip microcomputer combines the
A 11
flexibility of a high-speed controller with the
00
numerical capability of an array processor,
29 01
thereby offering an inexpensive alternative to
18 19 20 21 22 23 24 25 26 27 28
multichip bit-slice processors. The TMS320
family contains the first MOS microcomputers
capable of executing five million instructions per
second. This high throughput is the result of the
comprehensive, efficient, and easily programmed instruction set and of the highly pipelined architecture.
Special instructions have been incorporated to speed the execution of digital signal processing (DSP)
algorithms.
I
The TMS320 family's unique versatility and power give the design engineer a new approach to a variety
of complex applications. In addition, these microcomputers are capable of providing the mUltiple functions
PRODUCTION DATA documents contain information
current as of publication date. Products conform
to specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1985, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
B-~
SMJ32010
DIGITAL SIGNAL PROCESSOR
often required for a single application. For example, the TMS320 family can enable an industrial robot to
synthesize and recognize speech, sense objects with radar or optical intelligence, and perform mechanical
operations through digital servo loop computations.
PIN NOMENCLATURE
NAME
DEFINITION
I/O
A 11-AO/PA2-PAO
a
External address bus. I/O port address multiplexed over PA2-PAO.
BIO
I
External polling input for bit test and jump operations.
ClKOUT
a
System clock output, V4 crystal/ClKIN frequency.
D15-00
I/O
16-bit data bus.
DEN
a
Data enable indicates the processor accepting input data on 015-00.
INT
I
Interrupt.
MC/MP
I
Memory mode select pin. High selects microcomputer mode. low selects microprocessor
MEN
a
Memory enable indicates that 015-00 will accept external memory instruction.
RS
I
Reset used to initialize the device.
mode.
VCC
I
Power.
VSS
WE
I
Ground.
a
Write enable indicates valid data on D 1 5-DO.
X1
I
Crystal input.
X2/ClKIN
I
Crystal input or external clock input.
SMJ32010 SIGNAL PROCESSOR NOMENCLATURE
EXAMPLE:
SMJ
1.
P R E F I X - - - - - - - - - - - . . . J1
Must contain three or four letters
MIL-STD-883C Class B, Method 5004
I
8-4
2.
CIRCUIT DESIGNATOR----------...J
Must contain five digits
32010
3.
PACKAGE TYPE
Must contain two letters
J D - Side Braze
FD - Lead less Chip Carrier
4.
TEMPERATURE RANGE
Must contain one letter only
OOC to 70°C
L
S - - 55°C to 100°C
32010
JD
/
TEXAS •
INSTRUMENlS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
L
SMJ32010
DIGITAL SIGNAL PROCESSOR
SMJ32010 SIGNAL PROCESSOR SCREENING AND LOT CONFORMANCE
METHOD
SCREEN
2010 Condition B
Internal Visual (Precap)
See Note.
1008 Test Condition C
Stabilization Bake
(24 hours)
1010 Condition C
Temperature Cycling
(50 cycles)
2001 Condition A
Constant Acceleration
(MIN) in Y1 Plane
1014
Seal Fine and Gross
TI Data Sheet
Interim Electrical
Electrical Specifications
1015
125 DC (160 hours MIN)
Burn-in
RQMT
100%
100%
100%
100%
100%
100%
100%
PDA = 5%
TI Data Sheet
Final Electrical Tests
100%
Electrical Specifications
(A)
Static tests:
(1 )
25 DC (Subgroup 1, Table 1, 5005)
(2)
MAX and MIN Rated Operating
Temperature (Subgroups 2 and 3,
Table 1, 5005)
(B)
Switching tests:
(1)
25 DC (Subgroup 9, Table 1, 5005)
(2)
MAX and MIN Rated Operating
Temperature (Subgroups 10 and 11,
Table 1, 5005)
(C)
Functional tests:
(1 )
25 DC (Subgroup 7, Table 1, 5005)
(2)
MAX and MIN Rated Operating
Temperature (Subgroup 8, Table 1,
5005)
Quality Conformance
5005 Class B
Inspection Group A
(A)
(B)
Static tests:
(1 )
25 DC (Subgroup 1)
2%
(2)
Temperature (Subgroup 2)
3%
Temperature (Subgroup 3)
5%
Switching tests
(1)
(2)
(C)
LTPD
25 DC (Subgroup 9)
2%
Temperature (Subgroup 10)
3%
Temperature (Subgroup 11)
5%
I
Functional tests:
(1)
25 DC (Subgroup 7)
2%
External Visual
2009
100%
NOTE: 40x precap stress test in lieu of 100x precap per MIL-STD-883 Method 5004, Paragraph 3.3.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
B-~
I
8-6
APPENDIX C
DEVELOPMENT SUPPORT/PART
ORDER INFORMATION
I
C-1
I
C-2
TMS32010 EVALUATION MODULE
• Target Connector for Full In-Circuit Emulation
• Up to Eight Instruction Breakpoints
• Debug Monitor Including Over 60 Commands
with Full Prompting
• Flexible Single Step with Software Trace
• Execution from EVM Program Memory or Target
Memory
• Reverse Assembler
• Transparency Mode for Host CPU
Download
Upload/
• Event Counter for One Breakpoint
The Evaluation Module (EVM) is a single board which enables a user to determine inexpensively if the
TMS32010 meets the speed and timing requirements of the application. The EVM is a stand-alone module
whch contains all the tools necessary to evaluate the TMS32010 as well as to provide full in-circuit
emulation via a target connector. A powerful firmware package contains a debug monitor, editor,
assembler, reverse assembler, EPROM programmer, communication software to talk to two EIA ports, and
an audio cassette interface. The resident assembler will convert incoming source text into executable code
in just one pass by automatically resolving labels after the first assembly pass is completed. The EVM can
be configured with a dumb terminal, power supplies, and either a host computer, or an audio cassette.
Either source or object code can be downloaded into the EVM via the EIA ports provided on the board.
PART NUMBER
RTC/EVM 320A-03
POWER SUPPLIES (TM990/518A)
OUTPUT A:
+5 VOC (+/- 3%)
B: +12 VOC (+/- 3%)
C: -12 VOC (+/- 3%)
UNITS
4.0A
0.6A
0.4 A
C-3
XDS/320 MACRO ASSEMBLER/LINKER
• Macro Capabilities
• Complete Error Diagnostics
• Library Functions
• Symbol Table and Cross Reference
• Conditional Assembly
• Available on Several Host Computers
• Relocatable Modules
• Written in PASCAL
The XOS/320 Macro Assembler translates TMS32010 assembly language into executable object code. The
assembler allows the programmer to work with mnemonics rather than hexadecimal machine instructions
and to reference memory locations with symbolic addresses. The macro assembler supports macro calls
and definitions along with conditional assembly.
The XOS/320 Linker permits a program to be designed and implemented in separate modules that will later
be linked together to form the complete program. The linker assigns values to relocatable code, creating
an object file that can be executed by the simulator or emulator.
The XOS/320 Macro Assembler and Linker are currently available on several host computers, including
VAX(VMS and UNIX), IBM (MVS and CMS), and TIIIBM(MS/PC-OOS) operating systems. Contact the nearest
TI field sales office for availability or further details.
HOST
OPERATING
SYSTEM
PART NUMBER
TIIIBM
DEC VAX
DEC VAX
IBM
IBM
MS/PC-OOS
VMS
UNIX 4.1
MVS
CMS
TM OS324081 0-08
TM OS324021 0-08
TM OS3240220-08
TM OS324031 0-08
T M OS3240320-08
MEDIUM
5
1600
1600
1600
1600
For additional host support, please contact your local TI Field Sales Office.
C-4
1/4"
BPI
BPI
BPI
BPI
FLOPPY
MAG TAPE
MAG TAPE
MAG TAPE
MAG TAPE
XDS/320 SIMULATOR
• Trace and Breakpoint Capabilities
• Runs Object Code Generated by XDS/320 Macro
Assembler / Linker
• Full Access to Simulated Registers and Memories
• Available on VAX(VMS),TIIIBM(MS/PC-DOS)
• I/O Device Simulation
• Written in FORTRAN
The XDS/320 Simulator is a software program that simulates operation of the TMS32010 to allow
program verification. The debug mode enables the user to monitor the state of the simulated TMS3201 0
while the program is executing. The simulator program uses the TMS3201 0 object code, produced by the
XDS/320 Macro Assembler/Linker. During program execution, the internal registers and memory of the
simulated TMS3201 0 are modified as each instruction is interpreted by the host computer. Once program
execution is suspended, the internal registers and both program and data memories can be inspected and/
or modified. The XDS/320 Simulator is currently available on the VAX(VMS) and TIIIBM(MS/PC-DOS) operating
systems.
HOST
OPERATING
SYSTEM
PART NUMBER
MEDIUM
TI/lBM
DEC VAX
MS/PC-DOS
VMS
T M DS3240811·02
TMDS3240211-08
5 1/4" FLOPPY
1600 BPI MAG TAPE
I
C-5
XDS/320 EMULATOR
• 20-MHz Operation (Full In-Circuit Emulation)
• 2K of Full-Speed Hardware Trace
• Up to Ten Software Breakpoints
• Single Step
• 4K Words of Program Memory for User Code
• Assembler / Reverse Assembler
• Full Emulation of Microcomputer or Microprocessor Modes
• Host-Independent Upload/Download Capabilities
to/from Program or Data Memory
• Use of Target System Crystal, Internal Crystal, or
External Clock Signal
• Ability to Inspect and Modify All
Registers, Program and Data Memory
• Hardware Breakpoint on Program, Data, or 11 0
Conditions
• Multi-Microprocessor Development
Internal
The XDS/320 Emulator is a self-contained system that has all the features necessary for real-time in-circuit
emulation. This allows integration of the hardware and software in the debug mode. By setting breakpoints
based on internal conditions or external events, execution of the program can be suspended and control
given to the debug mode. In the debug mode, all registers and memory locations can be inspected and
modified. Single-step execution is available. Full trace capabilities at full speed and a reverse assembler that
translates machine code back into assembly instructions are also included to increase debugging
productivity. The system provides three EIA ports so that the emulator can be interfaced with a host
computer, terminal, printer, or PROM programmer. Using a standard EIA port,the object file produced by
the macro assembler/linker can be downloaded into the emulator. The emulator then can be controlled
through a terminal.
PART NUMBER
TM DS326221 0
I
C-6
TMS320 NOMENCLATURE
TMS
320
10
PREFIX----------a,
TMS = standard prefix
FAMILY-----------...j
320 = signal processing family
'
L
JD
DEVICE-----------------'
10 = Microprocessor
L
TEMPERATURE RANGE
L
=0
0
C to 70 0 C
PACKAGE TYPE
JD
ceramic
side-brazed
plastic
N
dual-in-line
=
=
M10 = Microcomputer (masked ROM)
DEVELOPMENT FLOWCHART
TMXtXXXX
Engineering prototypes that are not representative of the final
device's electrical specifications
Final silicon die that conforms to device's electrical specifications
but has not completed quality and reliability verification
Fully qualified production devices
tTMX units shipped against the following disclaimer:
1) Experimental product and its reliability has not been characterized.
2) Product is sold "as is."
3) Not warranted to be exemplary of final production version if or when released by Texas Instruments.
+TMP units shipped against the following disclaimer:
1) Customer understands that the product purchased hereunder has not been fully characterized and the expectation of quality and
reliability cannot be defined; therefore, Texas Instruments standard warranty refers only to the device's specifications.
2) No warranty of merchantability or fitness is expressed or implied.
I
C-7
I
C-8
APPENDIX D
TMS32020 DATA SHEET
0-1
TM5;iZUZU
DIGITAL SIGNAL PROCESSOR
MARCH 1985 - REVISED OCTOBER 1985
•
200-ns Instruction Cycle Time
•
•
544 Words of Programmable On-Chip Data
RAM
Repeat Instructions for Efficient Use of
Program Space
•
Five Auxiliary Registers and Dedicated
Arithmetic Unit for Indirect Addressing
•
Serial Port for Direct Codec Interface
•
Synchronization Input for Synchronous
Multiprocessor Configurations
•
Wait States for Communication to Slow
Off-Chip Memories/Peripherals
•
On-Chip Timer for Control Operations
•
Three External Maskable User Interrupts
•
Input Pin Polled by Software Branch
Instruction
•
Programmable Output Pin for Signalling
External Devices
•
128K Words of Data/Program Space
•
Sixteen Input and Sixteen Output Channels
•
16-Bit Parallel Interface
•
Directly Accessible External Data Memory
Space
•
Global Data Memory Interface
•
16-Bit Instruction and Data Words
•
32-Bit AlU and Accumulator
•
Single-Cycle Multiply/Accumulate
Instructions
•
0 to 16-Bit Scaling Shifter
•
Bit Manipulation and logical Instructions
•
2.4-Micron NMOS Technology
•
Instruction Set Support for Floating-Point
Operations
•
Single 5-V Supply
•
On-Chip Clock Generator
•
Block Moves for Data/Program Management
PIN ASSIGNMENTS
PIN
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
C1
C2
C10
FUNCTION
08
010
012
014
VCC
HOLD
RS
CLKX
VCC
VSS
07
09
011
013
015
BIO
READY
CLKR
VCC
lACK
06
05
MSC
PIN
C11
01
02
010
011
E1
E2
E10
E11
F1
F2
F10
F11
G1
G2
G10
G11
H1
H2
H10
H11
J1
J2
FUNCTION
CLKOUT1
04
03
CLKOUT2
XF
02
01
HOLDA
OX
DO
SYNC
FSX
X2/CLKIN
INTO
INT1
X1
BR
INT2
VCC
STRB
R/W
DR
FSR
PRODUCTION DATA documents contain information
current as of publication date. Products conform
to specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily incluile testing of all parameters.
PIN
J10
J11
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
L2
L3
L4
L5
L6
L7
L8
L9
L10
FUNCTION
PS
68-PIN GB
PIN GRID ARRAY CERAMIC PACKAGE t
(TOP VIEW)
is
AO
A1
A3
A5
A7
A8
A10
A12
A14
OS
VSS
VSS
A2
A4
A6
VCC
A9
A11
A13
A15
2
A
B
c
0
E
F
G
H
J
K
L
•
•
•
•
•
•
•
•
•
3
4
• • •
C!J • •
•
•
•
•
•
•
•
'e' • •
'-'
• • •
5
6
7
8
9
10 11
• • • • • •
• • • • • (e) •
• •
• •
• •
• •
• •
• •
• •
'.J
•
• • • • •
• • • • • •
\
...
I
t See Pin Assignments Table (Page 1) and Pin Nomenclature Table
(Page 2) for location and description of all pins.
Copyright © 1985, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
0-3
Im~.;I~U~U
DIGITAL SIGNAL PROCESSOR
PIN NOMENCLATURE
NAME
DEFINITION
I/O/Zt
VCC
I
5-V supply pins
VSS
X1
I
Ground pins
0
Output from internal oscillator for crystal
X2/ClKIN
I
ClKOUT1
0
0
1/0Il
ClKOUT2
015-00
Input to internal oscillator from crystal or external clock
Master clock output (crystal or ClKIN frequency/4)
A second clock output signal
16-bit data bus 015 (MSB) through DO (LSB). Multiplexed between program, data, and 1/0
spaces.
A15-AO
Oil
16-bit address bus A 15 (MSB) through AO (lSB)
pS,os,iS
Oil
Program, data, and 1/0 space select signals
R/W
Oil
Readlwrite signal
STRB
Oil
Strobe signal
RS
I
Reset input
INT2-INTO
I
External user interrupt inputs
MSC
lACK
0
0
Interrupt acknowledge signal
READY
I
Microstate complete signal
Data ready input. Asserted by external logic when using slower devices to indicate that the
current bus transaction is complete.
0
BR
Bus request signal. Asserted when the TMS32020 requires access to an external global data
memory space.
XF
0
HOLD
I
External flag output (latched software-programmable signal).
Hold input. When asserted, TMS32020 goes into an idle mode and puts the data, address, and
control lines in the high-impedance state.
HOLDA
0
Hold acknowledge signal
SYNC
I
Clock synchronization input
Branch control input. Polled by BIOl instruction.
BIO
I
DR
I
Serial data receive input
ClKR
I
Clock for receive input for serial port
FSR
I
OX
Oil
ClKX
FSX
tl/Oll
I
1/0Il
Frame synchronization pulse for receive input
Serial data transmit output
Clock for transmit output for serial port
Frame synchronization pulse for transmit. Configurable as either an input or an output.
Input/Output/High-impedance state.
I
)-4
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS32020
DIGITAL SIGNAL PROCESSOR
functional block diagram
1~1~lse I~
~
'1"
x N...I
, x CJ
'1"
...I
CJ
/
1
16
."16 • "16
Riw+--
I--
REAOY---+BR+--
a:
XF+--
...I
...I
w
a:
~
z
HOLOA+--
16
I
0
MSC+--
16
,;r.
...
0
HOLO ---+-
T
~
CJ
IN T(2-01
1,.16
J
~
A 15-AO
01 5-00
,1--16
• OX
~
~
16
16. '
(4X161
161
ORR(161
6
IMR(61
GREG(81
16 ...
,
PROGRAM BUS
16
16
16
l
16 , 16
/
~
~
ARO(16)
AR1(16)
3
I ARP(3) J,"'-
AR2(16)
16
h
I ARB(31 I
¥.L'
~
16
32
~16
I
'\P!W
,
'MU~
ALU(32)
,~32
ir16
,
1-._._._._.-
J
~32
~
16
BLOCK B2
(32 x 16)
SHIFTER(-6.0.1.4)
')
"'·l
16"
16
OAT RAM
BLOCK Bl
(256 x 161
f16?
PR(32)
1,.32
~
16
ARAU(161
TR(161
MULTIPLIER
7 LSB
FROM IR
~9
AR4(16)
16
I SHIFTER(0-161
AR3(16)
3,
U
FSX
TIM(161
OATA BUS
,
r
PRO(161
8~
/16
~
3
ClKX
OXR(161
.
16
16. '
V
;:)
- ~~
,
OR
CLKR
FSR
STACK
~~
~
16"
IFR(6)
X-"-'
16 "
RPTC(8)
~6
,.p
RS~
31
,
ST1(16)
PC(161
BIO--+
lACK+--
IR(16)
STO(16)
·
··
~
*--
STRB+--
/
PROGRAM BUS
'(32
~
OATA/PROG
RAM (256 x 161
BLOCK BO
IACCH(16) ACCl(16)I
~
"-
32
~
)'16
~16
I
~
/MUX\
~
16
"-
SHIFTERS(0.1.41
I
I
16
,
--"'
16
/
OATA BUS
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
~
V
o-!
TMS32020
DIGITAL SIGNAL PROCESSOR
description
The TMS32020 Digital Signal Processor is the second member of the TMS320 family of VLSI digital signal
processors and peripherals. The TMS320 family supports a wide range of digital signal processing
applications, such as telecommunications, modems, image processing, speech processing, spectrum
analysis, audio processing, digital filtering, high-speed control, graphics, and other computation-intensive
applications.
With a 200-ns instruction cycle time and an innovative memory configuration, the TMS32020 performs
operations necessary for many real-time digital signal processing algorithms. Since most instructions require
only one cycle, the TMS32020 is capable of executing five million instructions per second. On-chip data
RAM of 544 16-bit words, direct addressing of up to 64K words of external data memory space and 64K
words of external program memory space, and multiprocessor interface features for sharing global memory
minimize unnecessary data transfers to take full advantage of the capabilities of the processor.
architecture
The TMS32020 architecture is based upon that of the TMS3201 0, the first member of the TMS320 family.
The TMS32020 increases performance of DSP algorithms through innovative additions to the TMS320
family architecture. TMS32010 source code is upward-compatible with TMS32020 source code and can
be assembled using the TMS32-020 Macro Assembler.
Increased throughput on the TMS32020 for many DSP applications is accomplished by means of singlecycle multiply/accumulate instructions with a data move option, five auxiliary registers with a dedicated
arithmetic unit, and faster I/O necessary for data-intensive signal processing.
The architectural design of the TMS32020 emphasizes overall speed, communication, and flexibility in
processor configuration. Control signals and instructions provide floating-point support, block-memory
transfers, communication to slower off-chip devices, and multiprocessing implementations.
Two large on-chip RAM blocks, configurable either as separate program and data spaces or as two
contiguous data blocks, provide increased flexibility in system design. Maintaining program memory offchip allows large address spaces from which large programs of up to 64K words can operate at full speed.
Programs can also be downloaded from slow external memory to high-speed on-chip RAM. A total of 64K
data memory address space is included to facilitate implementation of DSP algorithms. The VLSI
implementation of the TMS32020 incorporates all of these features as well as many others, such as a
hardware timer, serial port, and block data transfer capabilities.
32-bit ALU/accumulator
The TMS32020 32-bit Arithmetic Logic Unit (ALU) and accumulator perform a wide range of arithmetic
and logical instructions, the majority of which execute in a single clock cycle. The ALU executes a variety
of branch instructions dependent on the status of the ALU or a single bit in a word. These instructions
provide the following capabilities:
• Branch to an address specified by the accumulator
• Normalize fixed-point numbers contained in the accumulator
• Test a specified bit of a word in data memory.
I
One input to the ALU is always provided from the accumulator, and the other input may be provided from
the Product Register (PR) of the multiplier or the input scaling shifter which has fetched data from the
RAM on the data bus. After the ALU has performed the arithmetic or logical operations, the result is stored
in the accumulator.
The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters
at the output of the accumulator perform shifts while the data is being transferred to the data bus for
storage. The contents of the accumulator remain unchanged.
)-6
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS32020
DIGITAL SIGNAL PROCESSOR
scaling shifter
The TMS32020 scaling shifter has a 16-bit input connected to the data bus and a 32-bit output connected
to the ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed
in the instruction. The LSBs of the output are filled with zeroes, and the MSBs may be either filled with
zeroes or sign-extended, depending upon the status programmed into the SXM (sign-extension mode) bit
of status register STO.
16 x 16-bit parallel multiplier
The TMS32020 has a two's complement 16 x 16-bit hardware multiplier, which is capable of computing
a 32-bit product in a single machine cycle. The multiplier has the following two associated registers:
• A 16-bit Temporary Register (TR) that holds one of the operands for the multiplier, and
• A 32-bit Product Register (PR) that holds the product.
Incorporated into the TMS32020 instruction set are single-cycle multiply/accumulate instructions that allow
both operands to be processed simultaneously. The data for these operations resides in the on-chip RAM
blocks and can be transferred to the multiplier each cycle via the program and data buses.
Four product shift modes are available at the Product Register (PR) output that are useful when performing
multiply/accumulate operations, fractional arithmetic, or justifying fractional products.
timer
The TMS32020 provides a memory-mapped 16-bit timer for control operations. The on-chip timer (TIM)
register is a down counter that is continuously clocked by an internal clock. This clock is derived by dividing
the CLKOUT1 frequency by 4. A timer interrupt (TINT) is generated every time the timer decrements to
zero. The timer is reloaded with the value contained in the period (PRD) register within the same cycle
that it reaches zero so that interrupts may be programmed to occur at regular intervals of 4 x (PRO)
cycles of CLKOUT1.
memory control
The TMS32020 provides a total of 544 16-bit words of on-chip data RAM, divided into three separate
blocks (BO, B1, and 82). Of the 544 words, 288 words (blocks 81 and 82) are always data memory, and
256 words (block BO) are programmable as either data or program memory. A data memory size of 544
words allows the TMS32020 to handle a data array of 512 words (256 words if on-chip RAM is used
for program memory), while still leaving 32 locations for intermediate storage. When using block 80 as
program memory, instructions can be downloaded from external program memory into on-chip RAM and
then executed.
When using on-chip program RAM or high-speed external program memory, the TMS32020 runs at full
speed without wait states. However, the READY line can be used to interface the TMS32020 to slower,
less-expensive external memory~ Downloading programs from slow off-chip memory to on-chip program
RAM speeds processing while cutting system costs.
The TMS32020 provides three separate address spaces for program memory, data memory, and I/O. The
on-chip memory is mapped into either the 64K-word data memory or program memory space, depending
upon the memory configuration. The CNFD (configure block 80 as data memory) and CNFP (configure
block 80 as program memory) instructions allow dynamic configuration of the memory maps through
software. Regardless of the configuration, the user may still execute from external program memory.
The TMS32020 has six registers that are mapped into the data memory space: a serial port data receive
register, serial port data transmit register, timer register, period register, interrupt mask register, and global
memory allocation register.
TEXAS •
INSTRUMENTS
0-
TMS3Z0Z0
DIGITAL SIGNAL PROCESSOR
PROGRAM
0(>0000)
31(>001F)
32(>0020)
DATA
1/0
0r-::::l
0(>0000)
INTERRUPTS
AND RESERVED
(EXTERNAL)
5(>0005)
6(>0006)
ON-CHIP
MEMORY-MAPPED
REGISTERS
15L::J
::.- PAGE 0
RESERVED
95(>005F)
96(>0060)
ON-CHIP
BLOCK B2
127(>007F)
128(>0080)
RESERVED
EXTERNAL
511(>01FF)
512(>0200)
ON-CHIP
BLOCK BO
767(>02FF)
768(>0300)
1023(>03FF)
1024(>0400)
PAGES 1-3
PAGES 4-5
ON-CHIP
BLOCK B1
~ PAGES 6-7
EXTERNAL
>- PAGES 8-511
65,535( >FFFF)
65,535( > FFFF)
~
~
(a) ADDRESS MAPS AFTER A CNFD INSTRUCTION
DATA
PROGRAM
31(>001F)
32(>0020)
INTERRUPTS
AND RESERVED
(EXTERNAL)
5(>0005)
6(>0006)
ON-CHIP
MEMORY -MAPPED
REGISTERS
95(>005F)
96(>0060)
EXTERNAL
127(>007F)
128(>0080)
511(>01FF)
512(>0200)
767(>02FF)
768(>0300)
65,535( > FFFF)
ON-CHIP
BLOCK BO
1023( >03FF)
1024(>0400)
°1
15
RESERVED
65,279(>FEFF)
65,280( >FFOO)
1/0
0(>0000)
0(>0000)
>- PAGE'O
ON-CHIP
BLOCK B2
RESERVED
~ PAGES 1-3
DOES NOT
EXIST
>- PAGES 4-5
ON-CHIP
BLOCK B1
~
EXTERNAL
>- PAGES 8-511
65,535( > FFFF)
(b) ADDRESS MAPS AFTER A CNFP INSTRUCTION
FIGURE 1. MEMORY MAPS
I
)-8
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
PAGES 6-7
mERNAL
1
TMS32020
DIGITAL SIGNAL PROCESSOR
interrupts and subroutines
The TMS32020 has three external maskable user interrupts INT2-INTO, available for external devices that
interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer
(TINT), and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS) having
the highest priority and the serial port transmit interrupt (XINT) having the lowest priority. All interrupt
locations are on two-word boundaries so that branch instructions can be accommodated in those locations
if desired.
A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a
multicycle instruction, the interrupt is not processed until the instruction is completed. This mechanism
applies both to instructions that are repeated or become multicycle due to the READY signal.
external interface
The TMS32020 supports a wide range of system interfacing requirements. Program, data, and I/O address
spaces provide interface to memory and I/O, thus maximizing system throughput. I/O design is simplified
by having I/O treated the same way as memory. I/O devices are mapped into the 1/0 address space using
the processor's external address and data busses in the same manner as memory-mapped devices. Interface
to memory and I/O devices of varying speeds is accomplished by using the READY line. When transactions
are made with slower devices, the TMS32020 processor waits until the other device completes its function
and signals the processor via the READY line. Then, theTMS32020 continues execution.
A serial port provides communication with serial devices, such as codecs, serial A/D converters, and other
serial systems. The interface signals are compatible with codecs and many other serial devices with a
minimum of external hardware. The serial port may also be used for intercommunication between processors
in multiprocessing applications.
The serial port has two memory-mapped registers: the data transmit register (DXR) and the data receive
register (ORR). Both registers operate in either the byte mode or 16-bit word mode, and may be accessed
in the same manner as any other data memory location. Each register has an external clock, a framing
synchronization pulse, and associated shift registers. One method of multiprocessing may be implemented
by programming one device to transmit while the others are in the receive mode.
multiprocessing
The flexibility of the TMS32020 allows configurations to satisfy a wide range of system requirements.
·The TMS32020 can be used as follows:
•
•
•
•
A
A
A
A
standalone processor
multiprocessor with devices in parallel
slave/host multiprocessor with global memory space
peripheral processor interfaced via processor-controlled signals to another device.
For multiprocessing applications, the TMS32020 has the capability of allocating global data memory space
and communicating with that space via the BR (bus request) and READY control signals. Global memory
is data memory shared by more than one processor. Global data memory access must be arbitrated. The
8-bit memory-mapped GREG (global memory allocation register) specifies part of the TMS32020's data
memory as global external memory. The contents of the register determine the size of the global memory
space. If the current instruction addresses an operand within that space, BR is asserted to request control
of the bus. The length of the memory cycle is controlled by the READY line.
I
The TMS32020 supports DMA (direct memory access) to its external program/data memory using the HOLD
and HOLDA signals. Another processor can take complete control of the TMS32020's external memory
by asserting HODS low. This causes the TMS32020 to three-state its address, data, and control lines,
and assert HOLDA.
TEXAS •
INSTRUMENlS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
D-~
II.I"~'U'U
DIGITAL SIGNAL PROCESSOR
instruction set
The TMS32020 microprocessor implements a comprehensive instruction set that supports both numericintensive signal processing operations as well as general-purpose applications, such as multiprocessing
and high-speed control. The TMS3201 0 source code is upward-compatible with TMS32020 source code.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Since
the same data lines are used to communicate to external data/program or I/O space, the number of cycles
may vary depending upon whether the next data operand fetch is from internal or external program memory.
Highest throughput is achieved by maintaining data memory on-chip and using either internal or fast external
program memory.
addressing modes
The TMS32020 instruction set provides three memory addressing modes: direct, indirect, and immediate
addressing.
Both direct and indirect addressing can be used to access data memory. In direct addressing, seven bits
of the instruction word are concatenated with the nine bits of the data memory page pointer to form the
16-bit data memory address. Indirect addressing accesses data memory through the five auxiliary registers.
In immediate addressing, the data is based on a portion of the instruction word(s).
In direct memory addressing, the instruction word contains the lower seven bits of the data memory address.
This field is concatenated with the nine bits of the data memory page pointer to form the full 16-bit address.
Thus, memory is paged in the direct addressing mode with a total of 51 2 pages, each page containing
128 words.
Five auxiliary registers (ARO-AR4) provide flexible and powerful indirect addressing. To select a specific
auxiliary register, the Auxiliary Register Pointer (ARP) is loaded with either a 0, 1, 2, 3, or a 4 for ARO
through AR4, respectively.
There are five types of indirect addressing: auto-increment or auto-decrement, post-indexing by either adding
or subtracting the contents of ARO, or single indirect addressing with no increment or decrement. All
operations are performed on the current auxiliary register in the same cycle as the original instruction,
followed by a new ARP value being loaded.
repeat feature
A repeat feature, used with instructions such as multiply/accumulates, block moves, I/O transfers, and
table read/writes, allows a single instruction to be performed up to 256 times. The repeat counter (RPTC)
is loaded with either a data memory value (RPT instruction) or an immediate value (RPTK instruction). The
value of this operand is one less than the number of times that the next instruction is executed. Those
instructions that are normally multicycle are pipelined when using the repeat feature, and effectively become
single-cycle instructions.
instruction set summary
I
)-10
Table 1 lists the symbols and abbreviations used in Table 2, the instruction set summary. Table 2 consists
primarily of single-cycle, single-word instructions. Infrequently used branch, I/O, and CALL instructions
are multicycle. The instruction set summary is arranged according to function and alphabetized within each
functional grouping. The symbol (t) indicates those instructions that are not included in the TMS3201 0
instruction set.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS32020
DIGITAL SIGNAL PROCESSOR
TABLE 1. INSTRUCTION SYMBOLS
SYMBOL
MEANING
B
eM
D
FO
I
4- bit field specifying a bit code
2-bit field specifying compare mode
Data memory address field
Format statuS bit
Addressing mode bit
Immediate operand field
Port address (PAO through PA15 are predefined
assembler symbols equal to 0 through 1 5,
respectively.)
2-bit field specifying P register output shift
code
3-bit operand field specifying auxiliary register
4-bit left-shift code
3-bit accumulator left-shift field
K
PA
PM
R
S
X
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
D-1
DIGITAL SIGNAL PROCESSOR
TABLE 2. INSTRUCTION SET SUMMARY
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS
Mnemonic
No.
Words
Description
Instruction Bit Code
15 14 13 12 11 10
Absolute value of accumulator
Add to accumulator with shift
Add to high accumulator
Add to low accumulator with
sign extension suppressed
ADDTt Add to accumulator with shift
specified by T register
ADLKt
Add to accumulator
long immediate with shift
AND
AND with accumulator
ANDKt AND immediate with accumulator with
shift
CMPLt Complement accumulator
LAC
Load accumulator with shift
LACK
Load accumulator immediate short
LACTt
Load accumulator with shift
specified by T register
LALKt
Load accumulator long
immediate with shift
NEGt
Negate accumulator
NORMt Normalize contents of accumulator
OR with accumulator
OR
ORKt
OR immediate with accumulator with
shift
SACH
Store high accumulator with shift
SACL
Store low accumulator with shift
SBLKt
Subtract from accumulator
long immediate with shift
SFLt
Shift accumulator left
SFRt
Shift accumulator right
SUB
Subtract from accumulator with shift
SUBC
Conditional subtract
SUBH
Subtract from high accumulator
SUBS
Subtract from low accumulator
with sign extension suppressed
SUBTt
Subtract from accumulator with
shift specified by T register
XOR
Exclusive-OR with accumulator
XORKt
Exclusive-OR immediate with
accumulator with shift
ZAC
Zero accumulator
ZALH
Zero low accumulator and load high
accumulator
ZALS
Zero accumulator and load low
accumulator with sign extension
suppressed
ABS
ADD
ADDH
ADDS
9
8
1
0
7
6
5
4
3
2 1
0
0
1
1 0 1
D
D
D
1
0
0
0 0
• I •
I •
0
1
I -
1
0
1
1
1
1
1
0
a
0
1
0
1
1
a
a
a
a
a 1 1
a-s
a 1 0
a 1 0
1
0
1
0
a
1
2
1
1
0
1-S
1
2
0
1
1
1
a
0
a 1 1
1-S
1
1
1
1
1
1
0
1
a
1
0
1
1
0
1
0
a
0 1 1
a-s
a 1 0
a 0 0
1
2
1
1
0
1-S
1
1
1
2
1
1
0
1
1
1
1
1
0
0
0
0
0 1 1
0 1 1
0 1 1
1-S
1
1
2
a
0
1
1
1
1
1
1
a
a 1-X-Ia O-X-I'
.0 0
1-S
1
1
1
1
1
1
1
1
a
a
a
0
1
1
0
1
1
1
0
0
0
a
0
0
0 1 1
0 1 1
1-S
a 0 1
0 0 1
a 0 1
1
0
0
0 0
0 0
• I •
I f
1
I ..
0
1
I •
1
0
1
0
a
0
1
1
0
I •
1
2
a
1
1
1
a
0
0 1 1
1-S
0
0
I • 0 0
1
1
1
a
1
1
0
a
a
1
0
1
1
a
1
a
a a
0
0
0
I
0
a
0
a 1
0
0
0
0
D
0
1 0
0
0 0
I -
1
0
0 1 1
D
K
D
1
• 0
0
I
1
1
o•
0
I •
1
1
a a
a a
0
0
1
1
I
•
I
0
a
0
0 0
1
0 0
1 0
I • 0 0
1
1
a
0
1
0
0
0
0 0 1
0 0 1
D
0 1 0
0
0
D
D
0 0 1
0
0
1
1
0
0
0
0
•
0
• 0
1
1
a
I
0
I •
a
t
D
-
• 0
•
I
0
1 0 0
1 0 0
D
D
D
D
D
0
0
0
0
a
•
1
I
•
1
0
1
•
•
I
I
J
D
0 1 1
I •
0 0 0
D
I •
D
•
a
a
I
I
AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS
Mnemonic
No.
Words
Description
Instruction Bit Code
15 14 13 12 11
CMPRt
I
LAR
LARK
LARP
LDP
LDPK
LRLKt
MAR
SAR
Compare auxiliary register with
auxiliary register ARa
Load auxiliary register
Load auxiliary register immediate short
Load auxiliary register pointer
Load data memory page pointer
Load data memory page pointer
immediate
Load auxiliary register long immediate
Modify auxiliary register
Store auxiliary register
1
1a
9
8
7
6
5
4
3
2 1
1
1
a a
1
a
1
a
a
1
1
1
1
1
1
a a 1 1 a-R-I'
1 1 a a a -R-----+-I •
K
a 1 a 1 a 1 a 1 1 a a a
a 1 a 1 a 0 1 0 I •
K
1 1 a a 1 a a ,
1 1 a 1 a-R-a 0 0 a
a 1 a 1 a 1 a 1 I•
a 1 1 1 a-R-I·
2
1
1
1
a
1
0
tThese instructions not included in the TMS3201 0 instruction set.
1-12
TEXAS.
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
a
•
D
I
1
D
R
0
D
D
a a
•
•
a
•
•
TMS32020
DIGITAL SIGNAL PROCESSOR
TABLE 2. INSTRUCTION SET SUMMARY (CONTINUED)
T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS
Mnemonic
No.
Words
Description
Instruction Bit Code
15 14 13 112 11 10
APAC
LPHt
LT
LTA
LTD
LTPt
LTSt
MACt
MACDt
MPY
MPYK
PAC
SPAC
SPMt
SORAt
SORSt
Add P register to accumulator
Load high P register
Load T register
Load T register and accumulate
previous product
Load T register, accumulate previous
product, and move data
Load T register and store P
register in accumulator
Load T register and subtract
previous product
Multiply and accumulate
Multiply and accumulate
with data move
Multiply (with T register, store product
in P register)
Multiply immediate
Load accumulator with P register
Subtract P register from accumulator
Set P register output shift mode
Square and accumulate
Square and subtract previous product
0
0
0
1
1
1
1
1
1
0
1
1
0
1
1
0
0
1
1
0
1
2
2
0
0
1
1
1
1
9
1
1
8
7
6
5
4
3
2 1
0
0
1
0 1 0
D
D
D
1
1
0
0
1
1
1
1
I
•
D
I
1
1
1
1
0
I •
D
•
0
1
1
0
1
1
I
•
D
•
1
1
0
0
1
1
1
1
1
1
0
0
1
0
I
I
I
I
0
0
•
0
0
1
1
1
0
0
0
I
•
0
•
1
0
1
1
1
0
1
1 •
0 0
0 0
0 0
1 1
0 1
1
1
1
1
1
1 0 0
1 1 0
O
0
0
0
1
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
1
0
0
0
1
1
1
0
0
0 0
I •
I •
I •
K
0 0
0 0
0 0
0
0
0
1
1
0
II ••
1
0
0
•
•
•
•
•
•
•
BRANCH/CALL INSTRUCTIONS
Mnemonic
Description
No.
Words
Instruction Bit Code
15 14 13 12 11 10
B
BACCt
BANZ
BBNZt
BBZt
BGEZ
BGZ
BIOZ
BLEZ
BLZ
BNVt
BNZ
BV
BZ
CALA
CALL
RET
Branch unconditionally
Branch to address specified by
accumulator
Branch on auxiliary register not zero
Branch if TC bit :F 0
Branch if TC bit = 0
Branch if accumulator ~'O
Branch if accumulator> 0
Branch on I/O status = 0
Branch if accumulator S 0
Branch if accumulator < 0
Branch if no overflow
Branch if accumulator :F 0
Branch on overflow
Branch if accumulator = 0
Call subroutine indirect
Call subroutine
Return from subroutine
2
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
0
1
0
1
0
0
1
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
0
0
0
0
1
1
0
1
1
1
1
9
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
1
8
1
0
1
1
0
0
1
0
0
1
1
1
0
0
0
0
0
7
6
1
0
1
1
5
4
0
1
0
I
1 •
1 ,
1
1
1
1
1
1
0
1
0
2 1
0
0
1 0
1
•
•
•,
•
•
I
0
1
0
0
0
1
0
0
•
•
•
0
0
0
0
0
0
0
0
0
0
0
0
I
1 •
1
3
0
I
•
•
•
•
•
•
•
•
•
•
•
1 0
0
1 1
0
0
•
tThese instructions not included in the TMS3201 0 instruction set.
I
TEXAS.
INSTRUMENTS
D-1 ~
TMS32020
DIGITAL SIGNAL PROCESSOR
TABLE 2. INSTRUCTION SET SUMMARY (CONCLUDED)
CONTROL INSTRUCTIONS
Mnemonic
No.
Words
Description
Instruction Bit Code
15 14 13 12 11 10
BiTt
BIITt
CNFDt
CNFPt
DINT
EINT
IDLEt
LST
lST1t
NOP
POP
POPDt
PSHDt
PUSH
ROVM
RPTt
RPTKt
RSXMt
SOVM
SST
SST1t
SSXMt
TRAPt
Test bit
Test bit specified by T register
Configure block as data memory
Configure block as program memory
Disable interrupt
Enable interrupt
Idle until interrupt
Load status register STO
Load status reg ister ST1
No operation
Pop top of stack to low accumulator
Pop top of stack to data memory
Push data memory value onto stack
Push low accumulator onto stack
Reset overflow mode
Repeat instruction as specified
by data memory value
Repeat instruction as specified
by immediate value
Reset sign-extension mode
Set overflow mode
Store status reg ister STO
Store status reg ister ST1
Set sign-extension mode
Software interrupt
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
9
8
7
6
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1 •
1 0
0 1
0 1
0 1
0 1
0 1
1 0
1 0
1 0
0 1
1 1
1 0
0 1
0 1
0 1
1
1
1
0
B-1'
I I
1 1
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
0 0
I •
I I
0 1
0 1 0
1 0 0
I •
1 0
I I
0 0
1 0 0
1 0 0
I I
1 1
1
1
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
0
1
0
0
0
0
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
5
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
3
D
D
0
0
0
0
1
D
D
0
1
D
D
1
0
D
2 1
I
I
1
1
0
0
1
0
0
0
0
1
0
1
1
0
1
0 0
1 0
0
0
0
I
I
0
0
0
0
0
0
0
0
0
0
1
I
•
1 0
0 1
0
0
I
I
1 1
0 1
0
0
0
0
0
1
D
D
0 1 1
1 1 1
0
4
3
2 1
0
I
•
.
I
K
I
0
0
1
I
I
1
1/0 AND DATA MEMORY OPERATIONS
Mnemonic
No.
Words
Description
Instruction Bit Code
15 14 13 12 11 10
BLKDt
BLKPt
DMOV
FORTt
IN
OUT
RTXMt
RXFt
STXMt
SXFt
TBlR
TBlW
Block move from data memory to
data memory
Block move from program memory
to data memory
Data move in data memory
Format serial port registers
Input data from port
Output data to port
Reset serial port transmit mode
Reset external flag
Set serial port transmit mode
Set external flag
Table read
Table write
9
8
2
1
1
1
1
1
1
0
1
7
I
2
1
1
1
1
1
1
0
0
I
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
1
0
0
0
1 0 1 1 0
I I
0 1 1 1 0 0 0
O-PA-I I
O-PA-I I
0 1 1 1 0 0 0
0 1 1 1 0 0 0
0 1 1 1 0 0 0
0 1 1 1 0 0 0
1 1 0 0 0
I •
1 1 0 0 1
I •
1
0
0
0
0
0
0
tThese instructions not included in the TMS3201 0 instruction set.
I
)-14
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
6
5
I
D
I
I
D
I
0
1
0
1
0
0
0
0
0
0
D
1 1
D
D
0 0
1 1
0 0
1 1
D
D
I
1 FO
I
I
0
0
0
0
0
0
1
1
I
I
TMS32020
DIGITAL SIGNAL PROCESSOR
development systems and software support
Texas Instruments offers concentrated development support and complete documentation for designing
a TMS32020-based microprocessor system. When developing an application, tools are provided to evaluate
the performance of the processor, to develop the algorithm implementation, and to fully integrate the
design's software and hardware modules. When questions arise, additional support can be obtained by
calling the nearest Texas Instruments Regional Technology Center (RTC).
Sophisticated development operations are performed with the TMS32020 Macro Assembler/Linker,
Simulator, and Emulator (XDS). The macro assembler and linker are used to translate program modules
into object code and link them together. This puts the program modules into a form which can be loaded
into the TMS32020 Simulator or Emulator. The simulator provides a quick means for initially debugging
TMS32020 software while the emulator provides the real-time in-circuit emulation necessary to perform
system level debug efficiently.
Table 3 gives a complete list of TMS32020 software and hardware development tools.
TABLE 3. TMS32020 SOFTWARE AND HARDWARE SUPPORT
MACRO ASSEMBLERS/LINKERS
Host Computer
Operating System
Part Number
DEC VAX
VMS
TMDS3241210-08
TI/IBM PC
MS/PC-DOS
TMDS3241810-02
Host Computer
Operating System
Part Number
DEC VAX
VMS
TMDS3241211-08
TI/IBM PC
MS/PC-DOS
TMDS3241811-02
SIMULATORS
EMULATORS
Model
Power Supply
Part Number
XDS/11
5 V @ 5 A required
TMDS32611 20
XDS/22
Included
TMDS3262220
I
TEXAS.
0-1
INSTRUMENTS
pnC:;T
O~~tr~
ROll
144~
•
~OIIC:::TON
T~lIll.C:::
77()()1
~
I m~ ... .tu.tu
DIGITAL SIGNAL PROCESSOR
absolute maximum ratings over specified temperature range (unless otherwise noted) t
Supply voltage range, VCC+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 7 V
Input voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V
Continuous power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2.0 W
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O°C to 70°C
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 1 50°C
tStresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
+AII voltage values are with respect to VSS.
recommended operating conditions
VCC
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
Vil
low-level input voltage
IOH
High-level output current
MIN
NOM
MAX
4.75
5
5.25
V
V
0
All inputs except ClKIN
UNIT
2
VCC+ 0 .3
V
2.4
VCC+0.3
V
All inputs except ClKIN
-0.3
0.8
V
ClKIN
-0.3
0.8
V
300
p,A
2
mA
70
DC
ClKIN
IOl
low-level output current
TA
Operating free-air temperature (Notes 1 and 2)
0
NOTES: 1. Case temperature (TC) must be maintained below 90°C.
2. ROJA = 36°C/Watt; ROJC = 6°C/Watt.
electrical characteristics over specified free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
VOL
low-level output voltage
VCC = MIN, IOH = MAX
VCC = MIN, IOl = MAX
IZ
Three-state current
VCC = MAX
II
Input current
VI = VSS to VCC
TA = o°C,
ICC
Supply current
3
fx = MAX
UNIT
V
0.6
V
-20
20
p,A
-10
10
p,A
360
mA
VCC = MAX, fx = MAX
TA = 25°C, VCC = 5 V,
MAX
mA
250
285
mA
CI
Input capacitance
15
pF
Co
Output capacitance
15
pF
t All typical values are at VCC
25°C.
&~.....
I
Typt
2.4
0.3
TC = 90°C, VCC = MAX, fx = MAX
-
MIN
Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic
fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according
to Mll-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum
rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic voltage level, preferrably
either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication "Guidelines for Handling ElectrostaticDischarge Sensitive (ESDS) Devices and Assemblies" available from Texas Instruments.
-16
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
TMS32020
DIGITAL SIGNAL PROCESSOR
CLOCK CHARACTERISTICS AND TIMING
The TMS32020 can use either its internal oscillator or an external frequency source for a clock.
internal clock option
The internal oscillator is enabled by connecting a crystal across X 1 and X2/CLKIN (see Figure 2). The
frequency of CLKOUT1 is one-fourth the crystal fundamental frequency.
MAX
UNIT
Input clock frequency
TA = O°C to 70°C
TEST CONDITIONS
6.7
20.5
MHz
Serial port frequency
TA = O°C to 70°C
50
2563
kHz
PARAMETER
fx
f sx
MIN
TA = OOC to 70°C
Cl, C2
Xl
TYP
10
pF
X2/ClKIN
CRYSTAL
.---401-----e2
T
FIGURE 2. INTERNAL CLOCK OPTION
external clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X 1 left
. unconnected. The external frequency injected must conform to the specifications listed in the following table.
switching characteristics over recommended operating conditions (see Note 3)
PARAMETER
MIN
tc(C)
CLKOUT1 ICLKOUT2 cycle time
td(CIH-C)
CLKIN high to CLKOUT1/CLKOUT2/STRB high/low
tf(C)
TYP
MAX
UNIT
195
597
ns
25
50
ns
CLKOUT 1ICLKOUT2/STRB fall time
10
ns
tr(C)
CLKOUT 1ICLKOUT2/STRB rise time
10
ns
tw(CL)
CLKOUT1 /CLKOUT2 low pulse duration
20-15
20
20+ 15
ns
tw(CH)
CLKOUT1/CLKOUT2 high pulse duratiOn
20-15
20
20+15
ns
td(Cl-C2)
CLKOUT1 high to CLKOUT2 low, CLKOUT2 high to CLKOUT1 high, etc.
0-10
0
0+ 10
ns
NOTE 3: Q
=
1/4t c (C).
TEXAS.
INSTRUMENTS
D-
TMS32D2D
DIGITAL SIGNAL PROCESSOR
timing requirements over recommended operating conditions (see Note 3)
MIN
te(CI)
elKIN cycle time
tf(CI)
elKIN fall time
48.8
tr(CI)
elKIN rise time
tw(CIL)
elKIN low pulse duration, te(CI)
tw(CIH)
elKIN high pulse duration, te(CI)
tsu(S)
th(S)
= 50 ns (Note 4)
= 50 ns (Note 4)
MAX
UNIT
150
ns
10
ns
10
ns
10
40
ns
10
40
ns
SYNC setup time before ClKIN low
10
Q-10
ns
SYNC hold time from ClKIN low
15
NOTES: 3. Q = 1/4tc (C).
4. ClKIN duty cycle [tr(CI) + tw(CIH)l/tc(CI) must be within 40-60%.
2.15 V
FROM OUTPUT
UNDER TEST
0---.
...-~o TEST
POINT
J
CL ~ 100 pF
FIGURE 3. TEST LOAD CIRCUIT
2.0 V_
VIH (MIN)
1.88 V"
--_IIIIIK-
0.92 V_
0.80 V_ .......
V'L (MAX)
~---------------------------o
(a) INPUT
2.4V_
2.0V-
- _ - - - VOH (MIN)
0.8 V-
0.6 V --:1:==~~=-===-==-==-=~==-VOL (MAX)
o
(b) OUTPUTS
FIGURE 4. VOLTAGE REFERENCE LEVELS
·18
NOM
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
ns
TMS32020
DIGITAL SIGNAL PROCESSOR
clock timing
X2/CLKIN
, , ' -_ _ _-J
......-----tc(C)-----~
........-....
;~~~_t_W(_CL_)_..3I"'"
CLKOUT1
"'--
le--tw(CH)
--t I-- tr(C)
CLKOUT2
I
.......-
t-
I
-I
tw(CH)-,*
td(C1-C2)
tflC)
~-----!IIr
tr(C)
J
...- -...... td(C1-C2)
~-td(C1-C2)
.....
TEXAS.
INSTRUMENTS
0-1
TMS32020
DIGITAL SIGNAL PROCESSOR
MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions (see Note 3)
PARAMETER
td(C1-S)
STRB from CLKOUT1 (if STRB is present)
MIN
TYP
MAX
0-15
0
0+ 15
ns
-15
0
15
ns
td(C2-S)
CLKOUT2 to STRB (if STRB is present)
tsu(A)
Address setup time before STRB low (Note 5)
0-30
th(A)
Address hold time after STRB high (Note 5)
0-15
tw(SL)
STRB low pulse duration (no wait states, Note 6)
tw(SH)
STRB high pulse duration (between consecutive cycles, Note 6)
tsu(D)W
Data write setup time before STRB high (no wait states)
th(D)W
Data write hold time from STRB high
ten(D)
Data bus starts being driven after STRB low (write cycle)
ns
ns
Data bus three-state after STRB high (write cycle)
td(MSC)
MSC valid from CLKOUT1
20
ns
20
ns
20-45
ns
0-15
tdis(D)
UNIT
ns
0
0
ns
- 25
0
0+30
ns
0
25
ns
NOTES: 3. 0 = 1/4t.£.LC).
5. A 15-AO, PS, DS, is, R/W, and BR timings are all included in timings referenced as "address."
6. Delays between CLKOUT 1ICLKOUT2 edges and STRB edges track each other, resulting in tw(SL) and tw(SH) being 20 with no
wait states.
timing requirements over recommended operating conditions (see Note 3)
MIN
ta(A)
Read data access time from address time (read cycle, Notes 5 and 7)
tsu(D)R
Data read setup time before STRB high
th(D)R
Data read hold time from STRB high
MAX
30-70
UNIT
ns
40
ns
0
ns
td(SL-R)
READY valid after STRB low (no wait states)
Q-40
ns
td(C2H-R)
READY valid after CLKOUT2 high
Q-40
ns
th(SL-R)
READY hold time after STRB low (no wait states)
Q-5
ns
th(C2H-R)
READY hold after CLKOUT2 high
Q-5
ns
td(M-R)
READY valid after MSC valid
th(M-R)
READY hold time after MSC valid
2Q-50
0
NOTES: 3. Q = 1/4tc (C).
5. A 15-AO, ps, DS, is, R/W, and BR timings are all included in timings referenced as "address."
7. Read data access time is defined as talA) = tsu(A) + tw(SL) - tsu(D)R.
I
20
NOM
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
ns
ns
TMS32020
DIGITAL SIGNAL PROCESSOR
memory read timing
CLKOUT1
A15-A<1BR,PS,OS,
OR is
R/W
READY
L
II
r.....-----r......
~ ~ th(O)R
th(SL-R) .....
015-00
__________________~r--O-~N-T-A~)~--------
memory write timing
CLKOUT1
CLKOUT2
STRB
\"'--_--.-1/
/
\"-_---..
\'---\"------',
\
'{
tsu(A) r!l------th-(A-)
A15-AO,
BR,PS,OS,
OR IS
~--II
VALID
R/W
READY
015-00
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
o
11VI::i.1lUlU
DIGITAL SIGNAL PROCESSOR
one wait-state memory access timing
CLKOUT1
)
"
"
CLKOUT2
I
I
~I
STRB
I
A15-AO,SR,
PS,OS,R/W,
OR IS
t
\
\
I
I
I
I
I
I
I
I
I
~
:I th(C2H-R)
~
015-00
(FOR READ
OPERATION)
015-00
(FOR WRITE
OPERATION)
MSC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
~I
1+-+ th(M-R)
I I
-+I
I
I
I
I
-
I
I
I
HI th(M-R)
1
I(
I I
I
I
I
I
I
DATA OUT
I
I
~td(MSC)
~2
/
th(C2H-R)
VALID
READY
td(M-R) ~
'----
/
\
I
I
I
I
I
I
I
I
I
I
I
TEXAS.
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
*
DATA )
IN
I
I
~
TMS32020
DIGITAL SIGNAL PROCESSOR
RS, INT, BIO, and XF TIMING
switching characteristics over recommended operating conditions (see Note 3)
PARAMETER
td(RS)
CLKOUT1 low to reset state entered
td(lACK)
CLKOUT1 to lACK valid
td(XF)
XF valid before falling edge of STRB
MIN
-25
TYP
0
MAX
UNIT
45
ns
25
ns
0-30
ns
NOTE 3: 0 = 1/4tc (C)'
8. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup
time is met, the exact sequence shown in the timing diagrams will occur.
timing requirements over recommended operating conditions (see Note 3)
MIN
tsu(IN)
INTIBIOIRS setup before CLKOUT1 high
th(lN)
INTIBIOIRS hold after CLKOUT1 high
tf(lN)
INT IBIO fall time
tw(lN)
INT IBIO low pulse duration
tw(RS)
RS low pulse duration
NOM
MAX
50
UNIT
ns
0
ns
15
ns
tc(C)
ns
3t c (C)
ns
NOTE 3: 0 = 1/4t c (C)'
8. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time
is met, the exact sequence shown in the timing diagrams will occur.
reset timing
CLKOUT1
RS
A15-AO
015-00
PS
STRB
CONTROL
SIGNALSt
I
lACK
SERIAL PORT
CONTROLS:J:
t Control signals are OS, IS, R/W and XF.
:J: Serial port controls are OX and FSX.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
0-2:
I
m" ... £u~u
DIGITAL SIGNAL PROCESSOR
interrupt timing
CLKOUT1
STRB
\
I
I
I
I
X
" "
I
I
II
I
I
II
~
I-:J tsu(l~) \
-+t
I I
/
I
I
- INT2-INTO ~tW(lNI
A15-AO
~
---+t
I
\
i+- th(lN)
I
\
I
\
II
I
X
I
I
X
FETCH N+ 1
FETCH I
I
X
810 timing
CLKOUT1
=* Flrb1 *
FETCH
BRANCH ADDRESS
ti
t
PC=N
I
I
*1 x=
FETCH
NEXT INSTRUCTION
PC=N+1
J
!++t th(lN)
tsu(lN)
ft"-+i
I
I
I
I
I
I
PC = N + 2
OR BRANCH ADDRESS
I
D-24
I
FETCH 1+ 1
lACK
A15-AO
\.
If
I
I
~ tf-'IN)
FETCH N
i
i
I I
--+I
I
I
I
I
I
\
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
)(
TMS32020
DIGITAL SIGNAL PROCESSOR
external flag timing
CLKOUT1
\
/
\
/
/
\
\.
STRB
--.j
I
A15-AO
)«
FETCH
_SXF/RXF
PC=N
*
VALID
PC=N+1
~
I
I
I
I
I
14- td(XF)
I
VALID
PC=N+2
K
VALID
XF
I
TEXAS"
INSTRUMENTS
0-
TMS32020
DIGITAL SIGNAL PROCESSOR
HOLD TIMING
switching characteristics over recommended operating conditions (see Note 3)
PARAMETER
TYP
MIN
MAX
-25
td(C1L-AL)
HOLDA low after CLKOUTl low
tdis(AL-A)
HOLDA low to address three-state
25
15
UNIT
ns
ns
tdis(C 1L-A) Address three-state after CLKOUT1 low (HOLD mode, Note 5)
30
ns
td(HH-AH)
HOLD high to HOLDA high
50
ns
t en (A-C1 L)
Address driven before CLKOUTl low (HOLD mode, Note 5)
10
ns
NOTES: 3. 0 = 1 14t.£.LC)~ _
_
_
5. A 15-AO, PS, OS, IS, R/W, and BR timings are all included in timings referenced as "address."
timing requirements over recommended operating conditions (see Note 3)
MIN
td(C2H-H)
NOM
MAX
HOLD valid after CLKOUT2 high
0-35
NOTE: 3. 0 = 1/4tc (C).
HOLD timing (part A)
CLKOUT1
\
/
X
CLKOUT2
I
"'=
STRB
I
A15-AO
PS,DS,
OR IS
~
X-I
I
\
I
\
I
\
I
\
I
I
I
~
I
\
i+- td(C2H-H)
---+1
HOLD
\
/
\
N
VALID
»<
»<
»<
»<
N+1
VALID
N+2
VALID
R/W
e
015-00
FETCH
~
EXECUTE
4
I
N
N-1
0
.~
...
N+1
I
I
I
I
I
I
I
I
I
I
I
I
N/A
~
.
DUMMY
I
I
I
'--
I
I
•-+t~
.~!
I
I
I
... I
'GolelL-A)
I
I
I
I
I N/A
I
I
I
! DEAD
II
•
~
1-+11+- tdis(AL-A)
1\1.1
I I!
td(C1L-AL)
TEXAS . "
INSTRUMENTS
POST OFFIrF ROX 1441
\
'*'
I
I
I
HOLDA
-26
/
I
.~
N
,.
I
I
I
•
HOIISTON
TI=Xl\.C:: 77{){)1
---.l
~
UNIT
ns
TMS32020
DIGITAL SIGNAL PROCESSOR
HOLD timing (part B)
CLKOUT1
I
I
I
I
\
l
CLKOUT2
STRB
I
I
I
I
---.!
HOLD
I
\
I
-
I
\
I
I
\
'cIIC2H-HI
fa
N+2
III
VALID
I
I
•
R/W
I
I
I
I
I
I
I
FETCH
..
..
DEAD
EXECUTE
HOLDA
I
I
I
I
I
I I
I
I
PS,DS,
OR is
N/A
'---
I
I
015-00
I \
\
I I
I I
I I
~ If- t en(A-C1L)
I
I
I
I
A15-AO
X I
\ II
I:
LJ
r
I
...
...
N/A
DEAD
...
...
*
*
N+1
)
VALID
)
®--
G
N+2
N+3
...
.
..
N+3
•
N+2
•
~!r--- td(HH-AH)
! I
..
TEXAS.
INSTRUMENTS
D-:
TMS32020
DIGITAL SIGNAL PROCESSOR
SERIAL PORT TIMING
switching characteristics over recommended operating conditions (see Note 3)
PARAMETER
MIN
td(CH-DX)
DX valid after CLKX rising edge (Note 9)
td(FL-DX)
= 0, Note 9)
FSX valid after CLKX rising edge (TXM = 1)
td(CH-FS)
TYP
DX valid after FSX falling edge (TXM
MAX
UNIT
100
ns
50
ns
60
ns
NOTES: 3. Q = 1/4tc (C)'
9. The last occurrence of FSX falling and CLKX rising.
timing requirements over recommended operating conditions (see Note 3)
MIN
NOM
390
ns
tf(SCK)
Serial port clock (CLKX/CLKR) fall time
50
ns
50
ns
ns
tr(SCK)
Serial port clock (CLKX/CLKR) rise time
tw(SCK)
Serial port clock (CLKX/CLKR) low pulse duration (see Note 10)
150
12,000
tw(SCK)
Serial port clock (CLKX/CLKR) high pulse duration (see Note 10)
150
12,000
tsu(FS)
FSX/FSR setup time before (CLKX/CLKR) falling edge (TXM = 0)
20
ns
th(FS)
FSX/FSR hold time after (CLKX/CLKR) falling edge (TXM = 0)
20
ns
tsu(DR)
DR setup time before CLKR falling edge
20
ns
th(DR)
DR hold time after CLKR falling edge
20
ns
serial port receive timing
~ tc(SCK) -+t
I
I+----+r tw(SCK)
I
tr(SCKI
I ~ th(FS)
II \
I! I
FSR
I
I
1--I
CLKR
I
I
-.I I+-
I
I
I tf(SCKI -tt ~----I~
1+ th(ORI
I:!
\ \~-------------~ tsu(OR)
DR
serial port transmit timing
:4-- tc(SCK)
-+,
tw(SCK)
CLKX:
:
th(FS)
FSX
(\NPUT.TXM=O)
!
t
4:
:
:
'
!
:\ 'I
"":....~-.....!-ld-(C-H--O-X-)~I--.-~........
~,
i+-tsUIFS)!
-.! !--
-+:
tf:
'-+i '
: '
' :,
, tf(' SCK) ..: I+"
:4 i
1411.: ',;: tw(SCK)
\~
dIFL-OXI
::
J
:
t:
::
FSX
(OUTPUT.TXM = 1)
+!
I
"
ox
tdICH-FS)
---.!
~ po~
(
~~
N=1
~
td(CH-FS)
\.!;~
~------------~
)-28
UNIT
tc(SCK)
NOTES: 3. Q = 1/4tc (C)'
10. The duty cycle of the serial port clock must be within 40-60%.
I
MAX
20,000
Serial port clock (CLKX/CLKR) cycle time
TEXAS.
INSTRUMENTS
O(""\CT nct:"lrt: c.nv
1 All. "l
•
Ur'llICTru.. 1
TCV I\C 17()()'
N=8.16
)....-
ns
TMS32020
DIGITAL SIGNAL PROCESSOR
MECHANICAL DATA
68-pin GB pin grid array ceramic package
TOP VIEW
28,448 (1.120)
r - - - - 2 7 , 4 3 2 (1.080)~
r-
I
I
17,0~ci~670)1
I
I
1
THERMAL RESISTANCE CHARACTERISTICS
PARAMETER
Junction-to-free-air
ROJA
thermal resistance
Junction-to-case
ROJC
thermal resistance
MAX
UNIT
36
°C/W
6
°C/W
8,448 (1.120)
27,432 (1.080)
17,02 (0.670)
L----------.J_
4,953 (0.195)
2,032 (0.080)
~
;:::==r:================:::J.'
____-, 1,397MAX
(0.055)
~I~~~~~~~~~~~~~~I~
~-~ ll111J~ IT tmJ:
3,302 (0.130)
2,794 (0.110)
2,54 (0.100)t1
T.P.
(0.062) OIA
1,473 (0.058)
0,406 (0.016)
BOTTOM VIEW
~~----------------------~
I
l
cD00880808-
r
808-~2,54(0.100)
K
(f)08 0888 8
J
88
88
H88
88
G88
88
F88
88
E88
80
088
88
C
8
8
8
8
B
0
\0 8
0
8
8
0
0
8
0
0
8
0
8
8
8
0
8
8--L
A
8
2
3
4
5
6
7
8
9
T.P.
=£1,524 (0.060)
NOM
4 PLACES
10 11 -r_J,27 (0.050)
NOM
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS •
INSTRUMENlS
POST OFFIr.F ROX 144::1
•
HOIISTON TFXAS 770()1
0-
0-30
TI Sales Offices TI Distributors
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~
TEXAS
INSTRUMENTS
Creating useful products
and services for you.
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4
enz
2
c:(
C
c:(
!;
W
....I
t!'
Z
c:(
0
w
en
c:(
J:
a..
-2
-4
----------~~----------r_----------r_----------r_--------~
o
NORMALIZED FREQUENCY (RADIANS/SAMPLE)
FIGURE 8-118 - PHASE ANGLE OF FREQUENCY RESPONSE
FIGURE 8-11 - FOURTH-ORDER ELLIPTIC DIGITAL FILTER
It is relatively simple to design IIR filters using tables of analog filter designs and a calculator.
Alternatively, a program for designing ItR digital filters by bilinear transformation of Butterworth,
Chebyshev, and elliptic filters has been given by Dehner in the IEEE Press Book. [6, Section 6.1]
The bilinear transformation method can be termed a 'closed form' solution to the ItR digital filter
design problem in the sense that an analog filter can be found in a non-iterative manner to meet a
set of prescribed approximation error specifications, and then the digital filter can be obtained in a
straightforward way by applying the bilinear transformation.
Another approach is as follows:
1) Define an ideal frequency response function,
2) Set up an approximation error criterion,
3) Pick an implementation structure, i.e., order of numerator and denominator of H(z),
cascade, parallel, or direct form,
4) Vary the filter coefficients systematically to minimize the approximation error criterion,
5) If the approximation is not good enough, increase the order of the system and repeat the
design process.
8-15
A variety of such iterative design techniques have been proposed for both IIR and FIR filters.
Deczky has developed a design program which minimizes a pth-order error norm. It is capable of
both magnitude and group delay (negative derivative of phase with respect to frequency)
approximations. [6, Section 6.2] Another optimization program for magnitude approximations only
has been written by Dolan and Kaiser. [6, Section 6.3] Both this program and the Deczky program
assume that the transfer function H(z) is a product of second-order factors.
Somewhat different approaches have been developed for the design of FIR filters, since there really
is no counterpart of the FIR filter for the analog system. In addition, FIR discrete-time filters can
have an exactly linear phase response. Since a linear phase response corresponds to only a delay,
attention can be focused on approximating the desired magnitude response without concern for the
phase. In most IIR design methods, the phase is ignored, and one is forced to accept whatever
phase distortion is imposed by the design procedure. The condition for linear phase of a casual FIR
system is the symmetry condition:
h[n]
±h [M-n]
o
In the case of the
(30)
otherwise
+ sign in (30), the frequency response will be:
H(e jwT )
=
. T(M)
-jw
R(wT)' e
--
(31 )
2
where R(wT) is a real function of frequency. Such frequency responses are appropriate for
approximating frequency selective filters. In the case of the minus sign in (30):
.
. T(M)
2
-jw
H(ejwT ) = jl(wT) . e
--
(32)
where I(wT) is also a real function of frequency. Such frequency responses are required for
approximating differentiators and Hilbert transformers (gO-degree phase shifters).
The most straightforward approach to the design of FIR filters is a technique often called the
Iwindow method.' In this approach, an ideal frequency response function is first defined. Then, the
corresponding ideal impulse response is determined by evaluating the inverse Fourier transform of
the ideal frequency response. (In picking the ideal frequency response, the linear phase condition
mayor may not be applied depending on what is most appropriate.) The ideal impulse response will
in general be ·of infinite length. An" approximate impulse response is computed by truncating the
ideal impuse response to a finite number of samples and tapering the remaining samples with a
window function. With appropriate choice of the window function, a smooth approximation to the
ideal frequency response is obtained even at points of discontinuity. Many window functions have
been proposed, but the most useful window for filter design is perhaps the one proposed by Kaiser
[8] since it has a parameter which, in conjunction with the window length, can be used
systematically to trade off between approximation error in slowly varying regions of the ideal
response (e.g., the stopband) and sharpness of transition at discontinuities of the ideal frequency
response. A program for window design of FIR frequency selective filters is given by Rabiner and
McGonegal [6, Section 5.2]
I
8-16
."
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