Technical_Reference_Options_and_Adapters_Volume_2_Apr84 Technical Reference Options And Adapters Volume 2 Apr84
User Manual: Technical_Reference_Options_and_Adapters_Volume_2_Apr84
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----- --- ------_.-
- ---- - -----
Technical
Reference
Options and Adapters
Volume 2
Personal Computer
Hardware Reference
Library
Revised Edition (April 1984)
The following paragraph does not apply to the United Kingdom or any country where such
provisions are inconsistent with local law: International Business Machines Corporation
provides this manual "as is," without warranty of any kind, either expressed or implied,
including, but not limited to the particular purpose. IBM may make improvements and/or
changes in the product(s) and/or the program(s) described in this manual at any time.
This product could include technical inaccuracies or typographical errors. Changes are
made periodically to the information herein; these changes will be incorporated in new
editions of the publication.
It is possible that this material may contain reference to, or information about, IBM
products (machines or programs), programming, or services that are not announced in
your country. Such references or information must not be construed to mean that IBM
intends to announce such IBM products, programming, or services in your country.
Products are not stocked at the address below. Requests for copies of this product and for
technical information about the system should be made to your authorized IBM Personal
Computer dealer.
The following paragraph applies only to the United States and Puerto Rico: A Reader's
Comment Form is provided at the back of this publication. If the form has been removed,
address comments to: IBM Corp., Personal Computer, P.O. Box 1328-C, Boca Raton,
Florida 33432. IBM may use or distribute any of the information you supply in any way it
believes appropriate without incurring any obligations whatever.
© Copyright International Business Machines Corporation 1981, 1982, 1983, 1984
ii
Federal Communications Commission
Radio Frequency Interference Statement
Warning: The equipment described herein has been certified
to comply with the limits for a Class B computing device,
pursuant to Subpart J of Part 15 of the FCC rules. Only
peripherals (computer input/ output devices, terminals,
printers, etc.) certified to comply with the Class B limits may
be attached to the computer. Operation with non-certified
peripherals is likely to result in interference to radio and TV
reception. If peripherals not offered by IBM are used with the
equipment, it is suggested to use shielded grounded cables
with in-line filters if necessary.
CAUTION
The product described herein is equipped with a grounded
plug for the user's safety. It is to be used in conjunction with
a properly grounded receptacle to avoid electrical shock.
iii
iv
-- ----_.-
--- ------ -- - ----
Personal Computer
Hardware Reference
Library
mM Monochrome
Display and Printer
Adapter
6361511
ii
Contents
Introduction ................................... 1
Monochrome Display Adapter Function .............. 1
Description ................................ 1
Programming Considerations .................. 5
Specifications .............................. 9
Printer Adapter Function ........................ 11
Description ............................... 11
Programming Considerations ................. 13
Specifications ............................. 17
Logic Diagrams ................................ 19
ill
iv
Introduction
The IBM Monochrome Display and Printer Adapter has two
functions. The first is to provide an interface to the IBM
Monochrome Display. The second is to provide a parallel
interface for the IBM Printers. We will discuss this adapter by
function.
Monochrome Display Adapter Function
Description
The IBM Monochrome Display and Printer Adapter is designed
around the Motorola 6845 CRT Controller module. There are
4K bytes of RAM on the adapter that are used for the display
buffer. This buffer has two ports to which the system unit's
microprocessor has direct access. No parity is provided on the
display buffer.
Two bytes are fetched from the display buffer in 553 ns,
providing a data rate of 1.8M bytes/second.
The adapter supports 256 different character codes. An 8K-byte
character generator contains the fonts for the character codes.
The characters, values, and screen characteristics are given in "Of
Characters, Keystrokes, and Colors" in your Technical Reference
system manual.
This adapter, when used with a display containing P39 phosphor,
does not support a light pen.
Where possible, only one low-power Schottky (LS) load is
present on any I/O slot. Some of the address bus lines have two
LS loads. No signal has more than two LS loads.
Monochrome Adapter 1
Characteristics of the adapter are:
•
Supports 80-character by 25-line screen
•
Has direct-drive output
•
Supports 9-PEL by 14-PEL character box
•
Supports 7-PEL by 9-PEL character
•
Has 18-kHz monitor
•
Has character attributes
2 Monochrome Adapter
The following is a block diagram of the monochrome display
adapter portion of the IBM Monochrome Display and Printer
Adapter.
Processor
Address
(12)
(1~
Memory
Address
Multiplexer
(10)
(10)
2K Memory
Character
Code
2K Memory
Attribute
(8)
Data
Bus
Gating
Processor
Data
BDO-7
I
I~
(8)
I"""
Character
Clock
(8)
Octal
Latch
MA
f-RA ~
AO
Chip
Select
~
-.
~
(4)
-..
1
~
Attribute
Decode
MC6845
CRTC
DOTCLK
L...
Signals
Serial Dots
r
Octal
Latch
Character
Generator
Shift
Register
Timing
,Ir
...
Video
Process
Logic
HSYNC, VSYNC, CURSOR, DISPEN
Character
Clock
I
*
Monitor
Direct Drive
Outputs
IBM Monochrome Display Adapter Block Diagram
Monochrome Adapter 3
4 Monochrome Adapter
Programming Considerations
The following table summarizes the 6845 controller module's
internal data registers, their functions, and their parameters. For
the IBM Monochrome Display, the values must be programmed
into the 6845 to ensure proper initialization of the display.
Register
Number
Register
File
Program
Unit
RO
R1
R2
R3
R4
R5
R6
R7
R8
R9
Horizontal Total
Horizontal Displayed
Horizontal Sync Position
Horizontal Sync Width
Vertical Total
Vertical Total Adjust
Vertical Displayed
Vertical Sync Position
Interlace Mode
Maximum Scan Line
Address
Cursor Start
Cursor End
Start Address (H)
Start Address (Ll
Cursor (H)
Cursor (L)
Reserved
Reserved
Characters
Characters
Characters
Characters
Character Rows
Scan Line
Character Row
Character Row
R10
R11
R12
R13
R14
R15
R16
R17
---------
Scan Line
Scan Line
Scan Line
---------------------------------
IBM Monochrome
Display
(Address in hex)
61
50
52
F
19
6
19
19
02
D
B
C
00
00
00
00
---------
--
---------
--
To ensure proper initialization, the first command issued to the
IBM Monochrome Display and Printer Adapter must be sent to
the CRT control port 1 (hex 3B8), and must be a hex 01, to set
the high-resolution mode. If this bit is not set, the system unit's
microprocessor's access to the adapter must never occur. If the
high-resolution bit is not set, the system unit's microprocessor will
stop running.
System configurations that have both an IBM Monochrome
Display and Printer Adapter, and an IBM Color/Graphics
Monitor Adapter, must ensure that both adapters are properly
initialized after a power-on reset. Damage to either display may
occur if not properly initialized.
Monochrome Adapter 5
The IBM Monochrome Display and Printer Adapter supports 256
different character codes. In the character set are alphanumerics
and block graphics. Each character in the display buffer has a
corresponding character attribute. The character code must be an
even address, and the attribute code must be an odd address in
the display buffer.
7
5
6
4
3
2
0
Character Code
Even Address (M)
7
6
5
FI
R
G
4
I
B
2
3
I I
I
R
G
B
I
~
I I I
I
0
Attribute Code
Odd Address (M + 1)
Foreground
Intensity
Background
Blink
The adapter decodes the character attribute byte as defined
above. The blink and intensity bits may be combined with the
foreground and background bits to further enhance the character
attribute functions listed below:
Background
R G B
Foreground
R G B
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
Function
Non-Display
Underline
White Character/Black Background
Reverse Video
The 4K display buffer supports one screen of the 25 rows of 80
characters, plus a character attribute for each display character.
The starting address of the buffer is hex BOOOO. The display
buffer can be read using direct memory access (DMA); however,
at least one wait state will be inserted by the system unit's
microprocessor. The duration of the wait state will vary, because
the microprocessor/monitor access is synchronized with the
character clock on this adapter.
6 Monochrome Adapter
Interrupt level 7 is used on the parallel interface. Interrupts can
be enabled or disabled through the printer control port. The
interrupt is a high-level active signal.
The following table breaks down the functions of the I/O address
decode for the adapter. The i/O address decode is from hex 3BO
through hex 3BF. The bit assignment for each I/O address
follows:
1/0 Register
Address
3BO
3B1
3B2
3B3
3B4
3B5
3B6
3B7
3B8
3B9
3BA
3BB
3BC
3BD
3BE
3BF
Function
Not Used
Not Used
Not Used
Not Used
6845 Index Register
6845 Data Register
Not Used
Not Used
CRT Control Port 1
Reserved
CRT Status Port
Reserved
Parallel Data Port
Printer Status Port
Printer Control Port
Not Used
1/0 Address and Bit Map
Monochrome Adapter 7
Bit
Number
Function
0
+ High Resolution Mode
1
Not Used
Not Used
+ Video Enable
Not Used
+ Enable Blink
Not Used
2
3
4
5
6,7
6845 CRT Control Port 1 (Hex 388)
Bit
Number
0
1
2
3
Function
+ Horizontal Drive
Reserved
Reserved
+ Black/White Video
6845 CRT Status Port (Hex 38A)
8 Monochrome Adapter
Specifications
9-Pin
Monochrome
Display
connector
o
1~6
9
5U
o
At Standard TTL Levels
1
Ground
2
Ground
IBM
Monochrome
Display
Note:
+ Intensity
Not Used
3
Not Used
4
Not Used
5
6
+ Video
7
+ Horizontal
8
- Vertical
9
IBM
Monochrome
Display and
Printer Adapter
Signal voltages are 0.0 to 0.6 Vdc at down level and + 2.4 to 3.5
Vdc at high level.
Connector Specifications
Monochrome Adapter 9
10 Monochrome Adapter
Printer Adapter Function
Description
The printer adapter portion of the IBM Monochrome Display and
Printer Adapter is specifically designed to attach printers with a
parallel-port interface, but it can be used as a general
input/ output port for any device or application that matches its
input/output capabilities. It has 12 TTL-buffer output points,
which are latched and can be written and read under program
control using the microprocessor In or Out instruction. The
adapter also has five steady-state input points that may be read
using the microprocessor's In instructions.
In addition, one input can also be used to create a microprocessor
interrupt. This interrupt can be enabled and disabled under
program control. A reset from the power-on circuit is also ORed
with a program output point, allowing a device to receive a
'power-on reset' when the system unit's microprocessor is reset.
The input/output signals are made available at the back of the
adapter through a right-angle, printed-circuit-board-mounted,
25-pin, D-shell connector. This connector protrudes through the
rear panel of the system unit or expansion unit, where a cable may
be attached.
When this adapter is used to attach a printer, data or printer
commands are loaded into an 8-bit, latched, output port, and the
strobe line is activated, writing data to the printer. The program
then may read the input ports for printer status indicating when
the next character can be written, or it may use the interrupt line
to indicate "not busy" to the software.
The output ports may also be read at the card's interface for
diagnostic loop functions. This allows faults to be isolated to the
adapter or the attaching device.
Monochrome Adapter 11
The following is a block diagram of the printer adapter portion of
the Monochrome Display and Printer Adapter.
L
Bus
~
r
25-Pin D-Shell
Connector
8
BUffe~r8:::....>-l~Data
Latc...
h_.....,8"--~
.
-..
~
Enable
Clock
Trans- 14C8~___+-____~
ceiver
DIR
L...---..J
,DIR
O.C.
Drivers
Read
Data
A~
STROBE
I----r~
Write Data
Command ~::..:..:..:~:....:.-:_ _ _ _+---.J
Decoder
Write Control
AUTO
FDXT
Read Status
I
SLCTIN
INIT
Read
Control
Control
Latch
Bus
Buffers
~ Enable
.
Y
~
4
Clock f-
rl
Clear
5
Enable
r
Reset
Printer Adapter Block Diagram
12 Monochrome Adapter
r.
SLCT
PE
ACK
BUSY
Programming Considerations
The printer adapter portion of the IBM Monochrome Display and
Printer Adapter responds to five I/O instructions: two output
and three input. The output instructions transfer data into 2
latches whose outputs are presented on pins of a 25-pin D-shell
connector.
Two of the three input instructions allow the system unit's
microprocessor to read back the contents of the two latches. The
third allows the system unit's microprocessor to read the real-time
status from a group of pins on the connector.
A description of each instruction follows.
IBM Monochrome Display &
Printer Adapter
Output to address hex 3BC
Bit 7
Bit 6
Bit 5
Bit4
Pin 9
Pin 8
Pin 7
Pin 6
The instruction captures data from the data bus and is present on
the respective pins. Each of these pins is capable of sourcing 2.6
rnA and sinking 24 rnA.
It is essential that the external device does not try to pull these
lines to ground.
IBM Monochrome Display &
Printer Adpater
Output to address hex 3BE
Bit4
IRQ
Enable
This instruction causes the latch to capture the five least
significant bits of the data bus. The four least significant bits
present their outputs, or inverted versions of their outputs, to the
Monochrome Adapter 13
respective pins as shown in the previous figure. If bit 4 is written
as aI, the card will interrupt the system unit's microprocessor on
the condition that pin 10 changes from high to low.
These pins are driven by open-collector drivers pulled to +5 Vdc
through 4.7 kQ resistors. They can each sink approximately 7 mA
and maintain 0.8 volts down-level.
IBM Monochrome Display &
Printer Adapter
Input from address hex 3BC
This instruction presents the system unit's microprocessor with
data present on the pins associated with the output to hex 3BC.
This should normally reflect the exact value that was last written
to hex 3BC. If an external device should be driving data on these
pins at the time of an input (in violation of usage ground rules),
this data will be ORed with the latch contents.
IBM Monochrome Display &
Printer Adapter
Input from address hex 3BD
This instruction presents the real-time status to the system unit's
microprocessor from the pins as follows.
Bit 7
Bit 6
Bit 5
Pin 11
Pin 10
Pin 12
I Bit4
I Pin 13
IBM Monochrome Display &
Printer Adapter
Input from address hex 3BE
14 Monochrome Adapter
Bit 3
Pin 15
I Bit 2 I
I- I
Bit 1
-
I
r
Bit 0
-
I
1
This instruction causes the data present on pins 1, 14, 16, 17, and
the IRQ bit to be read by the system unit's microprocessor. In
the absence of external drive applied to these pins, data read by
the system unit's microprocessor will match data last written to
hex 3BE in the same bit positions. Notice that data bits 0-2 are
not included. If external drivers are dotted to these pins, that
data will be ORed with data applied to the pins by the hex 3BE
latch.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IRQ
Enable
Pin 17
Pin 16
Pin 14
Por= 0
Por = 1
Por=O
Por= 1
Bit 0
-
Pin 1
Por= 1
These pins assume the states shown after a reset from the system
unit's microprocessor.
Monochrome Adapter 15
16 Monochrome Adapter
Specifications
0
• •
•
•
•
•
•
•
• ••
• •
• ••
•
14
•
•
•
•
•
•
•
13
25
0
At Standard TTL Levels
Printer
Signal
Adapter
Name
Pin Number
- Strobe
1
+ D.ata Bit 0
+ Data Bit 1
+ Data Bit 2
+ Data Bit 3
+ Data Bit 4
+ Data Bit 5
+ Data Bit 6
+ Data Bit 7
2
3
4
5
6
7
IBM
8
Monochr orne
9
Display and
- Acknowledge
10
Printer
+ Busy
+ P. End (out of paper)
+ Select
11
Adapter
12
13
-Auto Feed
14
- Error
15
- Initialize Printer
16
- Select Input
Ground
17
18-25
Connector Specifications
Monochrome Adapter 17
18 Monochrome Adapter
110 SLOT
(8HT6)
DO
'09
Ol
18H161
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AD'
AD6
AD5
A04
A03
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(SNT9)
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~
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Monochrome Display Adapter (Sheet 1 of 10)
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34 Color/Graphics Monitor Adapter
Index
A
alphanumeric mode 6
B
basic operations 12
c
change modes 21
character generator 5
color-select register 18
composite color generator 6
controller 5
D
description 1
display buffer 5
Index-l
G
graphics modes 9
high-resolution black-and-white 11
low-resolution color 9
medium-resolution color 9
H
high-resolution black-and-white graphics mode 11
L
logic diagrams 27
low-resolution color/graphics mode 9
M
medium-resolution color/graphics mode 9
memory requirements 22
mode set register 5
mode types
alphanumeric 6
graphics 9
mode-control register 19
mode-control register summary 20
modes of operation 1
Index-2
p
programming considerations 15
programming the mode control and status register 15
programming the 6845 crt controller 15
R
registers
color-select 18
mode control and status 15
mode set 5
mode-control 19
status 21
s
sequence of events for changing modes 21
specifications 23
status register 21
T
timing generator 6
Index-3
Index-4
------ ------------ - ---
Personal Computer
IBM Enhanced Graphics
Adapter
Contents
Description .................................... 1
Major Components .......................... 3
Modes of Operation ......................... 5
Basic Operations ............................ 8
Registers ................................. 12
Programming Considerations ..................... 62
Programming the Registers ................... 62
RAM Loadable Character Generator ........... 69
Creating a 512 Character Set ................. 70
Creating an 80 by 43 Alphanumeric Mode ....... 71
Vertical Interrupt Feature .................... 72
Creating a Split Screen ...................... 73
Compatibility Issues ........................ 74
Interface ..................................... 76
Feature Connector ......................... 76
Specifications ................................. 79
System Board Switches ...................... 79
Configuration Switches ...................... 80
Direct Drive Connector ...................... 83
Light Pen Interface ......................... 84
Jumper Descriptions ........................ 85
Logic Diagrams ................................ 87
BIOS Listing ................................. 103
Vectors with Special Meanings ............... 103
Index ........................................ Index-1
v
vi
Description
The IBM Enhanced Graphics Adapter (EGA) is a graphics
controller that supports both color and monochrome direct drive
displays in a variety of modes. In addition to the direct drive port,
a light pen interface is provided. Advanced features on the
adapter include bit-mapped graphics in four planes and a RAM
(Random Access Memory) loadable character generator. Design
features in the hardware substantially reduce the software
overhead for many graphics functions.
The Enhanced Graphics Adapter provides Basic Input Output
System (BIOS) support for both alphanumeric (A/N) modes and
all-points-addressable (AP A) graphics modes, including all modes
supported by the Monochrome Display Adapter and the
Color/Graphics Monitor Adapter. Other modes provide APA
640x350 pel graphics support for the IBM Monochrome Display,
full 16 color support in both 320x200 pel and 640x200 pel
resolutions for the IBM Color Display, and both A/N and APA
support with resolution of 640x350 for the IBM Enhanced Color
Display. In alphanumeric modes, characters are formed from one
of two ROM (Read Only Memory) character generators on the
adapter. One character generator defines 7x9 characters in a
9x14 character box. For Enhanced Color Display support, the
9x14 character set is modified to provide an 8x14 character set.
The second character generator defines 7x7 characters in an 8x8
character box. These generators contain dot patterns for 256
different characters. The character sets are identical to those
provided by the IBM Monochrome Display Adapter and the IBM
Color/Graphics Monitor Adapter.
The adapter contains 64K bytes of storage configured as four
16K byte bit planes. Memory expansion options are available to
expand the adapter memory to 128K bytes or 256K bytes.
The adapter is packaged on a single 13-1/8 inch (333.50 mm)
card. The direct drive port is a right-angle mounted connector at
the rear of the adapter and extends through the rear panel of the
system unit. Also on the card are five large scale integration
(LSI) modules custom designed for this controller.
August 2, 1984
IBM Enhanced Graphics Adapter 1
Located on the adapter is a feature connector that provides access
to internal functions through a 32-pin berg connector. A separate
64-pin connector provides an interface for graphics memory
expansion.
The following is a block diagram of the Enhanced Graphics
Adapter:
.
CPU
Addr.
CPU
...
Data
...
CRTC
LSI
..J...
MUX L
:1
GRAPH L
LSI
....
~
•
~
H
~
..- -j GRAPH ...'"
4
I--
... LSI
'\
SEQ
lSI
I--
..
f-
..
1~
~
r
.. ATTRIB
LSI
-""
~
BIT 0 MAP ~~
3 ~~
.:J
BIT
MAP
2
r~~
...
... DIRECT
.. DRIVE
OUTPUT
i
Enhanced Graphics Adapter Block Diagram
2 IBM Enhanced Graphics Adapter
August 2, 1984
Major Components
CRT Controller
The CRT (Cathode Ray Tube) Controller (CRTC) generates
horizontal and vertical synchronous timings, addressing for the
regenerative buffer, cursor and underline timings, and refresh
addressing for the dynamic RAMs.
Sequencer
The Sequencer generates basic memory timings for the dynamic
RAMs and the character clock for controlling regenerative
memory fetches. It allows the processor to access memory during
active display intervals by inserting dedicated processor memory
cycles periodically between the display memory cycles. Map
mask registers are available to protect entire memory maps from
being changed.
Graphics Controller
The Graphics Controller directs the data from the memory to the
attribute controller and the processor. In graphics modes,
memory data is sent in serialized form to the attribute chip. In
alpha modes the memory data is sent in parallel form, bypassing
the graphics controller. The graphics controller formats the data
for compatible modes and provides color comparators for use in
color painting modes. Other hardware facilities allow the
processor to write 32 bits in a single memory cycle, (8 bits per
plane) for quick color presetting of the display areas, and
additional logic allows the processor to write data to the display
on non-byte boundaries.
Attribute Controller
The Attribute Controller provides a color palette of 16 colors,
each of which may be specified separately. Six color outputs are
August 2, 1984
IBM Enhanced Graphics Adapter 3
available for driving a display. Blinking and underlining are
controlled by this chip. This chip takes data from the display
memory and formats it for display on the CRT screen.
Display Buffer
The display buffer on the adapter consists of 64K bytes of
dynamic read/write memory configured as four 16K byte video
bit planes. Two options are available for expanding the graphics
memory. The Graphics Memory Expansion Card plugs into the
memory expansion connector on the adapter, and adds one bank
of 16K to each of the four bit planes, increasing the graphics
memory to 128K bytes. The expansion card also provides DIP
sockets for further memory expansion. Populating the DIP
sockets with the Graphics Memory Module Kit adds two
additional 16K banks to each bit plane, bringing the graphics
memory to its maximum of 256K bytes.
The address of the display buffer can be changed to remain
compatible with other video cards and application software. Four
locations are provided. The buffer can be configured at segment
address hex AOOOO for a length of 128K bytes, at hex AOOOO for
a length of 64K bytes, at hex BOOOO for a length of 32K bytes, or
at hex B8000 for a length of 32K bytes.
BIOS
A read-only memory (ROM) Basic Input Output System (BIOS)
module on the adapter is linked to the system BIOS. This ROM
BIOS contains character generators and control code and is
mapped into the processor address at hex COOOO for a length of
16K bytes.
Support Logic
The logic on the card surrounding the LSI modules supports the
modules and creates latch buses for the CRT controller, the
4 IBM Enhanced Graphics Adapter
August 2, 1984
processor, and character generator. Two clock sources (14 MHz
and 16 MHz) provide the dot rate. The clock is multiplexed
under processor I/O control. The four I/O registers on the card
are not part of the LSI devices.
Modes of Operation
IBM Color Display
The following table describes the modes supported by BIOS on
the IBM Color Display:
Mode #
Type
Colors
Alpha
Format
Buffer
Start
Box
Size
Max.
Pages
Resolution
0
1
2
A/N
A/N
A/N
A/N
APA
APA
APA
APA
APA
16
16
16
16
4
4
2
16
16
40x25
40x25
80x25
80x25
40x25
40x25
80x25
40x25
80x25
B8000
B8000
B8000
B8000
B8000
B8000
B8000
8x8
8x8
8x8
8x8
8x8
8x8
8x8
8x8
8x8
8
8
4/8/8
4/8/8
1
1
1
2/4/8
1/2/4
320x200
320x200
640x200
640x200
320x200
320x200
640x200
320x200
640x200
3
4
5
6
D
E
AOOOO
AOOOO
°
Modes through 6 emulate the support provided by the IBM
Color/Graphics monitor Adapter.
Modes 0, 2, and 5 are identical to modes 1, 3, and 4, respectively,
at the adapter's direct drive interface.
The "MAX. PAGES" fields for modes 2,3, D, and E indicate the
number of pages supported when 64K, 128K, or 256K bytes of
graphics memory is installed, respectively.
January 20, 1986
IBM Enhanced Graphics Adapter
5
IBM Monochrome Display
The following table describes the modes supported by BIOS on
the IBM Monochrome Display.
Mode #
Type
Colors
Alpha
Format
Buffer
Start
Box
Size
Max.
Pages
Resolution
7
A/N
4
80x25
BOOOO
9x14
4/8
720x350
F
APA
4
80x25
AOOOO
8x14
1/2
640x350
The "MAX. PAGES" fields for modes 7 and F indicate the
number of pages supported when either 64K or greater than 64K
of graphics memory is installed, respectively.
Mode 7 emulates the support provided by the IBM Monochrome
Display Adapter.
IBM Enhanced Color Display
The Enhanced Graphics Adapter supports attachment of the IBM
Enhanced Color Display. The IBM Enhanced Color Display is
capable of running at the standard television frequency of 15.75
KHz as well as running21.85 KHz. The tabl~ below summarizes
the characteristics of the IBM Enhanced Color Display:
Parameter
Horiz Scan Rate
Vertical Scan Rate
Video Bandwidth
Displayable Colors
Character Size
Character Box Size
Maximum Resolution
Alphanumeric Modes
Graphics Modes
TV Frequency
High Resolution
15.75 KHz.
60 Hz.
14.318 MHz.
16 Maximum
7 by 7 Pels
8 by8 Pels
640x200 Pels
0,1,2,3
4,5,6,D,E
21.85 KHz.
60 Hz.
16.257 MHz.
16 or 64
7 by 9 Pels
8 by 14 Pels
640 by 350 Pels
0,1,2,3
10
In the television frequency mode, the IBM Enhanced Color
Display displays information identical in color and resolution to
the IBM Color Display.
6
IBM Enhanced Graphics Adapter
January 20, 1986
In the high resolution mode, the adapter provides enhanced
alphanumeric character support. This enhanced alphanumeric
support consists of transforming the 8 by 8 character box into an
8 by 14 character box, and providing 16 colors out of a palette of
64 possible display colors. Display colors are changed by altering
the programming of the color palette registers in the Attribute
Controller. In alphanumeric modes, any 16 of 64 colors are
displayable. The screen resolution is 320x350 for modes 0 and 1,
and 640x350 for modes 2 and 3.
The resolution displayed on the IBM Enhanced Color Display is
selected by the switch settings on the Enhanced Graphics
Adapter.
The Enhanced Color Display is compatible with all modes listed
for the IBM Color Display. The following table describes
additional modes supported by BIOS for the IBM Enhanced
Color Display:
Mode #
Type
Colors
0*
1*
2*
3*
A/N
A/N
A/N
A/N
APA
16/64
16/64
16/64
16/64
4/16
16/64
10
Alpha
Format
Buffer
Start
Box
Size
Max.
Pages
Resolution
40x25
40x25
80x25
80x25
80x25
88000
88000
88000
88000
8x14
8x14
8x14
8x14
8x14
8
8
4/8
4/8
1/2
320x350
320x350
640x350
640x350
640x350
AOOOO
* Note that modes 0, 1,2, and 3 are also listed for IBM Color
Display support. BIOS provides enhanced support for these
modes when an Enhanced Color Display is attached.
The values in the "COLORS" field indicate 16 colors of a 64
color palette or 4 colors of a sixteen color palette.
In modes 2, 3, and 10, the dual values for the "COLORS" field
and the "MAX. PAGES" field indicate the support provided
when eit4er 64K or greater than 64K of graphics memory is
installed, respectively.
January 20, 1986
IBM Enhanced Graphics Adapter
7
Basic Operations
Alphanumeric Modes
The data format for alphanumeric modes on the Enhanced
Graphics Adapter is the same as the data format on the IBM
Color / Graphics Monitor Adapter and the IBM Monochrome
Display Adapter. As an added function, bit three of the attribute
byte may be redefined by the Character Map Select register to act
as a switch between character sets. This gives the programmer
access to 512 characters at one time. This function is valid only
when memory has been expanded to 128K bytes or more.
When an alphanumeric mode is selected, the BIOS transfers
character patterns from the ROM to bit plane 2. The processor
stores the character data in bit plane 0, and the attribute data in
bit plane 1. The programmer can view bit planes 0 and 1 as a
single buffer in alphanumeric modes. The CRTC generates
sequential addresses, and fetches one character code byte and one
attribute byte at a time. The character code and row scan count
address bit plane 2, which contains the character generators. The
appropriate dot patterns are then sent to the palette in the
attribute chip, where color is assigned according to the attribute
data.
Graphics Modes
320x200 Two and Four Color Graphics (Modes 4 and 5)
Addressing, mapping and data format are the same as the
320x200 pel mode of the Color/Graphics Monitor Adapter. The
display buffer is configured at hex B8000. Bit image data is
stored in bit planes 0 and 1.
640x200 Two Color Graphics (Mode 6)
Addressing, mapping and data format are the same as the
640x200 pel black and white mode of the Color/Graphics
8
IBM Enhanced Graphics Adapter
January 20, 1986
Monitor Adapter. The display buffer is configured at hex B8000.
Bit image data is stored in bit plane O.
640x350 Monochrome Graphics (Mode F )
This mode supports graphics on the IBM Monochrome Display
with the following attributes: black, video, blinking video, and
intensified video. Resolution of 640x350 requires 56K bytes to
support four attributes. By chaining maps 0 and 1, then maps 2
and 3 together, two 32K bit planes can be formed. This chaining
is done only when necessary (less than 128K of graphics
memory). The first map is the video bit plane, and the second
map is the intensity bit plane. Both planes reside at hex address
AOOOO.
Two bits, one from each bit plane, define one picture element
(pel) on the screen. The bit definitions for the pels are given in
the following table. The video bit plane is denoted by CO and the
Intensity Bit Plane is denoted by C2.
C2
co
Pixel Color
0
0
1
1
0
1
0
1
Black
Video
Blinking Video
Intensified Video
Valid Attributes
0
3
C
F
The byte organization in memory is sequential. The first eight
pels on the screen are defined by the contents of memory in
location AOOO:OH, the second eight pels by location AOOO:1H,
and so on. The first pel within anyone byte is defined by bit 7 in
the byte. The last pel within the byte is defined by bit 0 in the
byte.
Monochrome graphics works in odd/even mode, which means
that even CPU addresses go into even bit planes and odd CPU
addresses go into odd bit planes. Since both bit planes reside at
address AOOOO, the user must select which plane or planes he
desires to update. This is accomplished by the map mask register
of the sequencer. (See the table above for valid attributes).
August 2, 1984
IBM Enhanced Graphics Adapter 9
16/64 Color Graphics Modes (Mode 10)
These modes support graphics in 16 colors on either a medium or
high resolution monitor. The memory in these modes consists of
using all four bit planes. Each bit plane represents a color as
shown below. The bit planes are denoted as CO,Cl,C2 and C3
respectively.
co = Blue Pels
C 1 = Green Pels
C2 = Red Pels
C3 = Intensified Pels
Four bits (one from each plane) define one pelon the screen.
The color combinations are illustrated in the following table:
I
R
G
B
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
.1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Color
Black
Blue
Green
Cyan
Red
Magenta
Brown
White
Dark Gray
Light Blue
Light Green
Light Cyan
Light Red
Light Magenta
Yellow
Intensified White
The display buffer resides at address AOOOO. The map mask
register of the sequencer is used to select any or all of the bit
planes to be updated when a memory write to the display buffer is
executed by the CPU.
Color Mapping
The Enhanced Graphics Adapter supports 640x350 Graphics for
both the IBM Monochrome and the mM Enhanced Color
10 mM Enhanced Graphics Adapter
August 2, 1984
Displays. Four color capability is supported on the EGA without
the Graphics Memory Expansion Card (base 64 KB), and sixteen
colors are supported when the Graphics Memory Expansion Card
is installed on the adapter (128 KB or above). This section
describes the differences in the colors displayed depending upon
the graphics memory available. Note that colors OH, 1H, 4H, and
7H map directly regardless of the graphics memory available.
Character
Attribute
Monochrome
Mode 10H
Mode 10H
64KB
>64KB
OOH*
Black
Black
Black
01H*
Video
Blue
Blue
02H
Black
Black
Green
03H
Video
Blue
Cyan
04H*
Blinking
Red
Red
05H
Intensified
White
Magenta
06H
Blinking
Red
Brown
07H*
Intensified
White
White
08H
Black
Black
Dark Gray
09H
Video
Blue
Light Blue
OAH
Black
Black
Light Green
OBH
Video
Blue
Light Cyan
OCH
Blinking
Red
Light Red
ODH
Intensified
White
Light Magenta
OEH
Blinking
Red
Yellow
OFH
Intensified
White
Intensified White
* Graphics character attributes which map directly regardless of
the graphics memory available.
August 2, 1984
IBM Enhanced Graphics Adapter 11
Registers
External Registers
This section contains descriptions of the registers of the Enhanced
Graphics Adapter that are not contained in an LSI device.
Name
Port
Miscellaneous Output Register
Feature Control Register
Input Status Register 0
Input Status Register 1
3C2
3?A
3C2
3?2
? = B in Monochrome Modes
Index
-
? = D in Color Modes
Miscellaneous Output Register
This is a write-only register. The processor output port address is
hex 3C2. A hardware reset causes all bits to reset to zero.
Miscellaneous Output Register Format
Bit
7
6
5
4
3
2
1
0
I/O Address Select
Enable Ram
Clock Select 0
Clock Select 1
L--_ _ _ _ _~
Disable Internal Video Drivers
Page Bit For Odd/Even
Horizontal Retrace Polarity
L..-----------l~
Bit 0
Vertical Retrace Polarity
3BX/3DX CRTC I/O Address-This bit maps
the CRTC I/O addresses for IBM Monochrome
or Color/Graphics Monitor Adapter emulation.
A logical 0 sets CRTC addresses to 3BX and
Input Status Register 1 's address to 3BA for
Monochrome emulation. A logical 1 sets CRTC
12 IBM Enhanced Graphics Adapter
August 2, 1984
addresses to 3DX and Input Status Register l's
address to 3DA for Color/Graphics Monitor
Adapter emulation.
Bit 1
Enable RAM-A logical 0 disables RAM from
the processor; a logical 1 enables RAM to
respond at addresses designated by the Control
Data Select value programmed into the Graphics
Controllers.
Bit 2-Bit 3
Clock Select-These two bits select the clock
source according to the following table:
Bits
3 2
o 0o 1-
Selects 14 MHz clock from the processor
I/O channel
Selects 16 MHz clock on-board oscillator
1 0- Selects external clock source from the
feature connector.
1 1- Not used
Bit 4
Disable Internal Video Drivers-A logical 0
activates internal video drivers; a logical 1
disables internal video drivers. When the internal
video drivers are disabled, the source of the direct
drive color output becomes the feature connector
direct drive outputs.
Bit 5
Page Bit For Odd/Even-Selects between two
64K pages of memory when in the Odd/Even
modes (0,1,2,3,7). A logical 0 selects the low
page of memory; a logical 1 selects the high page
of memory.
Bit 6
Horizontal Retrace Polarity-A logical 0 selects
positive horizontal retrace; a logical 1 selects
negative horizontal retrace.
Bit 7
Vertical Retrace Polarity-A logical 0 selects
positive vertical retrace; a logical 1 selects
August 2, 1984
IBM Enhanced Graphics Adapter 13
negative vertical retrace. The IBM Monochrome
display requires a negative vertical retrace
polarity.
Feature Control Register
This is a write-only register. The processor output register is hex
3BA or 3DA.
Feature Control Register Format
Bit
7
6
5
4
3
2
1
0
Feature Control Bit 0
Feature Control Bit 1
Reserved
Not Used
Bits 0 and 1
Feature Control Bits-These bits are used to
convey information to the feature connector.
The output of these bits goes to the FEAT 0 (pin
19) and FEAT 1 (pin 17) of the feature
connector.
Input Status Register Zero
This is a read-only register. The processor input port address is
hex 3C2.
14
mM Enhanced Graphics Adapter
August 2, 1984
Input Status Register Zero Format
Bit
7
6
5
I
4
I
3
2
1
0
IIII
:
Not Used
Switch Sense
Reserved
Reserved
CRT Interrupt
Bit 4
Switch Sense-When set to 1, this bit allows the
processor to read the four configuration switches
on the board. The setting of the CLKSEL field
determines which switch is being read. The
switch configuration can be determined by
reading byte 40:88H in RAM.
Bit 3:
Bit 2:
Bit 1:
Bit 0:
Switch 4 ; Logical 0
Switch 3 ; Logical 0
Switch 2 ; Logical 0
Switch 1 ; Logical 0
=
=
=
=
switch closed
switch closed
switch closed
switch closed
Bits 5 and 6
Feature Code-These bits are input from the
Feat (0) and Feat (1) pins on the feature
connector.
Bit 7
CRT Interrupt-A logical 1 indicates video is
being displayed on the CRT screen; a logical 0
indicates that vertical retrace is occurring.
Input Status Register One
This is a read-only register. The processor port address is hex
3BA or hex 3DA.
August 2, 1984
IBM Enhanced Graphics Adapter 15
Input Status Register One Format
Bit
7
6
5
4
3
2
1
0
Display Enable
Light Pen Strobe
Light Pen Switch
Vertical Retrace
Diagnostic 1
Diagnostic 0
Not Used
Bit 0
Display Enable-Logical 0 indicates the CRT
raster is in a horizontal or vertical retrace
interval. This bit is the real time status of the
display enable signal. Some programs use this
status bit to restrict screen updates to inactive
display intervals. The Enhanced Graphics
Adapter does not require the CPU to update the
screen buffer during inactive display intervals to
avoid glitches in the display image.
Bit 1
Light Pen Strobe-A logical 0 indicates that the
light pen trigger has not been set; a logical 1
indicates that the light pen trigger has been set.
Bit 2
Light Pen Switch-A logical 0 indicates that the
light pen switch is closed; a logical 1 indicates
that the light pen switch is open.
Bit 3
Vertical Retrace-A logical 0 indicates that video
information is being displayed on the CRT
screen; a logical 1 indicates the CRT is in a
vertical retrace interval. This bit can be
programmed to interrupt the processor on
interrupt level 2 at the start of the vertical
retrace. This is done through bits 4 and 5 of the
Vertical Retrace End Register of the CRTC.
Bits 4 and S
Diagnostic Usage-These bits are selectively
connected to two of the six color outputs of the
16 IBM Enhanced Graphics Adapter
August 2, 1984
Attribute Controller. The Color Plane Enable
register controls the multiplexer for the video
wiring. The following table illustrates the
combinations available and the color output
wiring.
Input Status
Register One
Color Plane
Register
Bit S Bit4
0
0
0
1
1
0
1
1
August 2, 1984
BitS
Bit4
Red
Secondary Blue
Secondary Red
Not Used
Blue
Green
Secondary Green
Not Used
IBM Enhanced Graphics Adapter 17
Sequencer Registers
Name
Port
Address
Reset
Clocking Mode
Map Mask
Character Map Select
Memory Mode
3C4
3C5
3C5
3C5
3C5
3C5
Index
00
01
02
03
04
Sequencer Address Register
The Address Register is a pointer register located at address hex
3C4. This register is loaded with a binary value that points to the
sequencer data register where data is to be written. This value is
referred to as "Index" in the table above.
Sequencer Address Register Format
Bit
7
6
5
4
3
2
1
0
IIII II I I
::
----L.---'.--------I_~
L...
Bit O-Bit 3
Sequencer Address
Not Used
Sequencer Address Bits-A binary value pointing
to the register where data is to be written.
Reset Register
This is a write-only register pointed to when the value in the
address register is hex 00. The output port address for this
register is hex 3C5.
18 IBM Enhanced Graphics Adapter
August 2, 1984
Reset Register Format
Bit
7
6
5
4
3
2
1
0
IIIIIII~
Asynchronous Reset
Synchronous Reset
Not Used
Bit 0
Asynchronous Reset-A logical 0 commands the
sequencer to asynchronous clear and halt. All
outputs are placed in the high impedance state
when this bit is a O. A logical 1 commands the
sequencer to run unless bit 1 is set to zero.
Resetting the sequencer with this bit can cause
data loss in the dynamic RAMs.
Bit 1
Synchronous Reset-A logical 0 commands the
sequencer to synchronous clear and halt. Bits 1
and 0 must both be ones to allow the sequencer
to operate. Reset the sequencer with this bit
before changing the Clocking Mode Register, if
memory contents are to be preserved.
Clocking Mode Register
This is a write-only register pointed to when the value in the
address register is hex 01. The output port address for this
register is hex 3C5.
Clocking Mode Register Format
Bit
7
6
5
4
3
2
1
0
8/9 Dot Clocks
Bandwidth
Shift Load
Dot Clock
Not Used
August 2, 1984
IBM Enhanced Graphics Adapter 19
Bit 0
8/9 Dot Clocks-A logical 0 directs the
sequencer to generate character clocks 9 dots
wide; a logical 1 directs the sequencer to generate
character clocks 8 dots wide. Monochrome
alphanumeric mode (07H) is the only mode that
uses character clocks 9 dots wide. All other
modes must use 8 dots per character clock.
Bit 1
Bandwidth-A logical 0 makes CRT memory
cycles occur on 4 out of 5 available memory
cycles; a logical 1 makes CRT memory cycles
occur on 2 out of 5 available memory cycles.
Medium resolution modes require less data to be
fetched from the display buffer during the
horizontal scan time. This allows the CPU
greater access time to the display buffer. All high
resolution modes must provide the CRTC with 4
out of 5 memory cycles in order to refresh the
display image.
Bit 2
Shift Load-When set to 0, the video serializers
are reloaded every character clock; when set to 1,
the video serializers are loaded every other
character clock. This mode is useful when 16 bits
are fetched per cycle and chained together in the
shift registers.
Bit 3
Dot Clock-A logical 0 selects normal dot clocks
derived from the sequencer master clock input.
When this bit is set to 1, the master clock will be
divided by 2 to generate the dot clock. All the
other timings will be stretched since they are
derived from the dot clock. Dot clock divided by
two is used for 320x200 modes (0, 1,4,5) to
provide a pixel rate of 7 MHz, (9 MHz for mode
D).
Map Mask Register
This is a write-only register pointed to when the value in the
address register is hex 02. The output port address for this
register is hex 3C5.
20 IBM Enhanced Graphics Adapter
August 2, 1984
Map Mask Register Format
Bit
7
6
5
4
3
2
1
0
1 Enables Map 0
1 Enables Map 1
1 Enables Map 2
1 Enables Map 3
Not Used
Bit O-Bit 3
Map Mask-A logical 1 in bits 3 through 0
enables the processor to write to the
corresponding maps 3 through O. If this register
is programmed with a value of OFH, the CPU can
perform a 32-bit write operation with only one
memory cycle. This substantially reduces the
overhead on the CPU during display update
cycles in graphics modes. Data scrolling
operations are also enhanced by setting this
register to a value of OFH and writing the display
buffer address with the data stored in the CPU
data latches. This is a read-modify-write
operation. When odd! even modes are selected,
maps 0 and 1 and maps 2 and 3 should have the
same map mask value.
Character Map Select Register
This is a write-only register pointed to when the value in the
address register is hex 03. The output port address for this
register is 3C5.
August 2, 1984
IBM Enhanced Graphics Adapter 21
Character Map Select Register Format
Bit
7
6
5
4
3
2
1
0
I I ~I::
IIII ~I
-
-
'--""---'----'-------~
Bits
0
Not Used
Character Map Select B-Selects the map used
to generate alpha characters when attribute bit 3
is a 0, according to the following table:
Bit O-Bit 1
1
Character Map Select 8
Character Map Select A
Map
Selected
Table Location
Value
0
0
1
1
0
1
0
1
Character Map Select A-Selects the map used
to generate alpha characters when attribute bit 3
is aI, according to the following table:
Bit 2-Bit 3
Bits
3
1st 8K of Plane 2 Bank 0
2nd 8K of Plane 2 Bank 1
3rd 8K of Plane 2 Bank 2
4th 8K of Plane 2 Bank 3
0
1
2
3
2
Map
Selected
0
1
0
1
0
1
2
3
Table Location
Value
0
0
1
1
1st 8K of Plane 2 Bank 0
2nd 8K of Plane 2 Bank 1
3rd 8K of Plane 2 Bank 2
4th 8K of Plane 2 Bank 3
In alphanumeric modes, bit 3 of the attribute byte normally has
the function of turning the foreground intensity on or off. This
bit however may be redefined as a switch between character sets.
This function is enabled when there is a difference between the
value in Character Map Select A and the value in Character Map
Select B. Whenever these two values are the same, the character
select function is disabled. The memory mode register bit 1 must
be a 1 (indicates the memory extension card is installed in the
unit) to enable this function; otherwise, bank 0 is always selected.
22 IBM Enhanced Graphics Adapter
August 2, 1984
128K of graphics memory is required to support two character
sets. 256K supports four character sets. Asynchronous reset
clears this register to O. This should be done only when the
sequencer is reset.
Memory Mode Register
This is a write-only register pointed to when the value in the
address register is hex 04. The processor output port address for
this register is 3C5.
Memory Mode Register Format
Bit
7
6
5
4
3
2
1
0
E
Alpha
Extended Memory
Odd/Even
Not Used
Bit 0
Alpha-A logical 0 indicates that a non-alpha
mode is active. A logical 1 indicates that alpha
mode is active and enables the character
generator map select function.
Bit 1
Extended Memory-A logical 0 indicates that the
memory expansion card is not installed. A logical
1 indicates that the memory expansion card is
installed and enables access to the extended
memory through address bits 14 and 15.
Bit 2
Odd/Even-A logical 0 directs even processor
addresses to access maps 0 and 2, while odd
processor addresses access maps 1 and 3. A
logical 1 causes processor addresses to
sequentially access data within a bit map. The
maps are accessed according to the value in the
map mask register.
August 2, 1984
IBM Enhanced Graphics Adapter 23
CRT Controller Registers
Name
Port
Index
Address Register
Horizontal Total
Horizontal Display End
Start Horizontal Blank
End Horizontal Blank
Start Horizontal Retrace
End Horizontal Retrace
Vertical Total
Overflow
Preset Row Scan
Max Scan Line
Cursor Start
Cursor End
Start Address High
Start Address Low
Cursor Location High
Cursor Location Low
Vertical Retrace Start
Light Pen High
Vertical Retrace End
Light Pen Low
Vertical Display End
Offset
Underline Location
Start Vertical Blank
End Vertical Blank
Mode Control
Line Compare
3?4
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
3?5
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
10
11
11
12
13
14
15
16
17
18
? = B in Monochrome Modes and 0 in Color Modes
CRT Controller Address Register
The Address register is a pointer register located at hex 3B4 or
hex 3D4. If an IBM Monochrome Display is attached to the
adapter, address 3B4 is used. If a color display is attached to the
adapter, address 3D4 is used. This register is loaded with a binary
value that points to the CRT Controller data register where data
is to be written. This value is referred to as "Index" in the table
above.
24 IBM Enhanced Graphics Adapter
August 2, 1984
CRT Controller Address Register Format
Bit
7
6
5
Bit O-Bit 4
4
3
2
1
0
CRT Controller Address Bits-A binary value
pointing to the CRT Controller register where
data is to be written.
Horizontal Total Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 00. The processor output port
address for this register is hex 3B5 or hex 3D5.
Horizontal Total Register Format
Bit
7
6
5
4
3
2
1
0
&-.1-,-I---II-..L-I-L.I---II--L-I-,-I~..
Horizontal Total
This register defines the total number of characters in the
horizontal scan interval including the retrace time. The value
directly controls the period of the horizontal retrace output signal.
An internal horizontal character counter counts character clock
inputs to the CRT Controller, and all horizontal and vertical
timings are based upon the horizontal register. Comparators are
used to compare register values with horizontal character values
to provide horizontal timings.
Bit O-Bit 7
August 2, 1984
Horizontal Total-The total number of
characters less 2.
IBM Enhanced Graphics Adapter 25
Horizontal Display Enable End Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 01. The processor output port
address for this register is hex 3B5 or hex 3D5.
Horizontal Display Enable End Register Format
BH
7
6
5
4
3
2
1
0
L-I---LI--LI---II_.L..I--,-I---LI---LI_-t.~
Horizontal Display Enable End
This register defines the length of the horizontal display enable
signal. It determines the number of displayed character positions
per horizontal line.
Horizontal display enable end -A value one less
than the total number of displayed characters.
Bit O-Bit 7
Start Horizontal Blanking Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 02. The processor output port
address for this register is hex 3B5 or hex 3D5.
Start Horizontal Blanking Register Format
Bit
7
6
5
4
3
2
I I I I I I
1
0
I I
~
Start Vertical Blanking
This register determines when the horizontal blanking output
signal becomes active. The row scan address and underline scan
line decode outputs are multiplexed on the memory address
outputs and cursor outputs respectively during the blanking
interval. These outputs are latched external to the CRT
Controller with the falling edge of the BLANK output signal.
The row scan address and underline signals remain on the output
signals for one character count beyond the end of the blanking
signal.
26 IBM Enhanced Graphics Adapter
August 2, 1984
Start Horizontal Blanking-The horizontal
blanking signal becomes active when the
horizontal character counter reaches this value.
Bit O-Bit 7
End Horizontal Blanking Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 03. The processor output port
address for this register is hex 3B5 or hex 3D5.
End Horizontal Blanking Register Format
Bit
7
6
5
II I
4
3
2
I I I
1
0
End Blanking
Display Enable Skew Control
Not Used
This register determines when the horizontal blanking output
signal becomes inactive. The row scan address and underline scan
line decode outputs are multiplexed on the memory address
outputs and the cursor outputs respectively during the blanking
interval. These outputs are latched external to the CRT
Controller with the falling edge of the BLANK output signal.
The row scan address and underline signals remain on the output
signals for one character count beyond the end of the blanking
signal.
Bit O-Bit 4
August 2,1984
End Horizontal Blanking-A value equal to the
five least significant bits of the horizontal
character counter value at which time the
horizontal blanking signal becomes inactive
(logical 0). To obtain a blanking signal of width
W, the following algorithm is used: Value of
Start Blanking Register + Width of Blanking
signal in character clock units = 5-bit result to be
programmed into the End Horizontal Blanking
Register.
mM Enhanced Graphics Adapter 27
Display Enable Skew Control-These two bits
determine the amount of display enable skew.
Display enable skew control is required to
provide sufficient time for the CRT Controller to
access the display buffer to obtain a character
and attribute code, access the character generator
font, and then go through the Horizontal Pel
Panning Register in the Attribute Controller.
Each access requires the display enable signal to
be skewed one character clock unit so that the
video output is in synchronization with the
horizontal and vertical retrace signals. The bit
values and amount of skew are shown in the
following table:
Bit 5-Bit 6
Bits
6 5
o 0 Zero character clock skew
o lOne character clock skew
1 0
1 1
Two character clock skew
Three character clock skew
Start Horizontal Retrace Pulse Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 04. The processor output port
address for this register is hex 3B5 or hex 3D5.
Start Horizontal Retrace Pulse Register Format
Bit
7
6
5
4
3
2
1
0
IL.._.J..I........LI----'I~IL.._.L.I---LI___l~..~
Start Horizontal Retrace Pulse
This register is used to center the screen horizontally, and to
specify the character position at which the Horizontal Retrace
Pulse becomes active.
28 IBM Enhanced Graphics Adapter
August 2, 1984
Start Horizontal Retrace Pulse-The value
programmed is a binary count of the character
position number at which the signal becomes
active.
Bit O-Bit 7
End Horizontal Retrace Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 05. The processor output port
address for this register is hex 3B5 or hex 3D5.
End Horizontal Retrace Register Format
Bit
7
6
5
II I
4
3
2
III
1
0
End Horizontal Retrace
Horizontal Retrace Delay
Start Odd Memory Address
This register specifies the character position at which the
Horizontal Retrace Pulse becomes inactive (logical 0).
Bit O-Bit 4
End Horizontal Retrace-A value equal to the
five least significant bits of the horizontal
character counter value at which time the
horizontal retrace signal becomes inactive (logical
0). To obtain a retrace signal of width W, the
following algorithm is used: Value of Start
Retrace Register + width of horizontal retrace
signal in character clock units = 5-bit result to be
programmed into the End Horizontal Retrace
Register.
Bit S-Bit 6
Horizontal Retrace Delay-These bits control
the skew of the horizontal retrace signal. Binary
00 equals no Horizontal Retrace Delay. For
some modes, it is necessary to provide a
horizontal retrace signal that takes up the entire
blanking interval. Some internal timings are
generated by the falling edge of the horizontal
retrace signal. To guarantee the signals are
August 2,1984
mM Enhanced Graphics Adapter 29
latched properly, the retrace signal is started
before the end of the display enable signal, and
then skewed several character clock times to
provide the proper screen centering.
Start Odd/Even Memory Address-This bit
controls whether the first CRT memory address
output after a horizontal retrace begins with an
even or an odd address. A logical 0 selects even
addresses; a logical 1 selects odd addresses. This
bit is used for horizontal pel panning applications.
Generally, this bit should be set to a logical O.
Bit 7
Vertical Total Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 06. The processor output port
address for this register is hex 3B5 or 3D5.
Vertical Total Register Format
Bit
7
6
5
4
3
2
1
0
I I I I II I I•
Bit O-Bit 7
Vertical Total
Vertical Total-This is the low-order eight bits of
a nine-bit register. The binary value represents
the number of horizontal raster scans on the CRT
screen, including vertical retrace. The value in
this register determines the period of the vertical
retrace signal. Bit 8 of this register is contained
in the CRT Controller Overflow Register hex 07
bit O.
CRT Controller Overflow Register
This is a write-only register pointed to when the value in the CRT
Controller Address Register is hex 07. The processor output port
address for this register is hex 3B5 or hex 3D5.
30 IBM Enhanced Graphics Adapter
August 2, 1984
CRTC Overflow Register Format
Bit
7
6
5
4
3
2
1
0
Vertical Total Bit 8
Vertical Display Enable End Bit 8
Vertical Retrace Start Bit 8
Start Vertical Blank Bit 8
Line Compare Bit 8
Cursor Location Bit 8
Not Used
Bit 0
Vertical Total-Bit 8 of the Vertical Total
register (index hex 06).
Bit 1
Vertical Display Enable End-Bit 8 of the
Vertical Display Enable End register (index hex
12).
Bit 2
Vertical Retrace Start-Bit 8 of the Vertical
Retrace Start register (index hex 10).
Bit 3
Start Vertical Blank-Bit 8 of the Start Vertical
Blank register (index hex 15).
Bit 4
Line Compare-Bit 8 of the Line Compare
register (index hex 18).
Bit 5
Cursor Location-Bit 8 of the Cursor Location
register (index hex OA).
Preset Row Scan Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 08. The processor output port
address for this register is hex 3B5 or hex 305.
August 2, 1984
mM Enhanced Graphics Adapter 31
Preset Row Scan Register Format
Bit
7
6
5
4
3
2
1
0
Starting Row Scan Count after
a Vertical Retrace
Not Used
This register is used for pel scrolling.
Preset Row Scan (Pel Scrolling)-This register
specifies the starting row scan count after a
vertical retrace. The row scan counter
increments each horizontal retrace time until a
maximum row scan occurs. At maximum row
scan compare time the row scan is cleared (not
preset).
Bit O-Bit 4
Maximum Scan Line Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 09. The processor output port
address for this register is hex 3B5 or hex 3D5.
Maximum Scan Line Register Format
Bit
7
6
5
III
Bit O-Bit 4
4
3
2
1
0
I I I I:
Maximum Scan Line
Not Used
Maximum Scan Line-This register specifies the
number of scan lines per character row. The
number to be programmed is the maximum row
scan number minus one.
Cursor Start Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex OA. The processor output port
32 mM Enhanced Graphics Adapter
August 2, 1984
address for this register is hex 3B5 or hex 3D5.
Cursor Start Register Format
Bit
7
6
5
4
3
2
1
0
Row Scan Cursor Begins
Not Used
Bit O-Bit 4
Cursor Start-This register specifies the row scan
of a character line where the cursor is to begin.
The number programmed should be one less than
the starting cursor row scan.
Cursor End Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex OB. The processor output port
address for this register is hex 3B5 or hex 3D5.
Cursor End Register Format
Bit
7
6
5
4
I' ,
3
2
1
0
Row Scan Cursor Ends
Cursor Skew Control
Not Used
Bit O-Bit 4
Cursor End-These bits specify the row scan
where the cursor is to end.
Bit 5-Bit 6
Cursor Skew-These bits control the skew of the
cursor signal.
August 2, 1984
mM Enhanced Graphics Adapter 33
Bits
6 5
o 0 Zero character clock skew
o lOne character clock skew
1 0
1 1
Two character clock skew
Three character clock skew
Start Address High Register
This is a read/write register pointed to when the value in the CRT
Controller address register is hex OC. The processor
input/output port address for this register is hex 3B5 or hex 305.
Start Address High Register Format
Bit
7
6
5
4
3
2
1
0
I I I I I I I
Bit O-Bit 7
~
High Order Start Address
Start. Address High-These are the high-order
eight bits of the start address. The 16-bit value,
from the high-order and low-order start address
registers, is the first address after the vertical
retrace on each screen refresh.
Start Address Low Register
This is a read/write register pointed to when the value in the CRT
Controller address register is hex 00. The processor
input/output port address for this register is hex 3B5 or hex 305.
Start Address Low Register Format
Bit
7
6
5
4
I I I
3
2
1
0
I I I
~
34 mM Enhanced Graphics Adapter
Low Order Start Address
August 2, 1984
Bit O-Bit 7
Start Address Low-These are the low-order 8
bits of the start address.
Cursor Location High Register
This is a read/write register pointed to when the value in the CRT
Controller address register is hex OE. The processor input/output
port address for this register is hex 3B5 or hex 3D5.
Cursor Location High Register Format
B~
7
6
5
4
3
2
1
0
I I I I I I•
High Order Cursor Location
Cursor Location High-These are the high-order
8 bits of the cursor location.
Bit O-Bit 7
Cursor Location Low Register
This is a read/write register pointed to when the value in the CRT
Controller address register is hex OF. The processor input/output
port address for this register is hex 3B5 or Hex 3D5.
Cursor Location Low Register Format
B~
7
6
5
4
3
2
1 0
I I I I I I I•
Bit O-Bit 7
August 2, 1984
Low Order Cursor Location
Cursor Location Low- These are the low-order
8 bits of the cursor location.
IBM Enhanced Graphics Adapter 35
Vertical Retrace Start Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 10. The processor output port
address for this register is hex 3B5 or hex 3D5.
Vertical Retrace Start Register Format
Bit
7
6
5
4
3
2
1
0
I I I I I I
Bit O-Bit 7
Low Order Vertical Retrace Pulse
Vertical Retrace Start-This is the low-order 8
bits of the vertical retrace pulse start position
programmed in horizontal scan lines. Bit 8 is in
the overflow register location hex 07.
Light Pen High Register
This is a read-only register pointed to when the value in the CRT
Controller address register is hex 10. The processor input port
address for this register is hex 3B5 or hex 3D5.
Light Pen High Register Format
Bit
7
6
5
4
3
2
1
0
I I I I III I•
Bit O-Bit 7
High Order Memory Address
Counter
Light Pen High-This is the high order 8 bits of
the memory address counter at the time the light
pen was triggered.
Vertical Retrace End Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 11. The processor output port
36 IBM Enhanced Graphics Adapter
August 2, 1984
address for this register is hex 3B5 or hex 3D5.
Vertical Retrace End Register Format
Bit
7
6
II
5
I
432
I
1
0
I I I I
~
Vertical Retrace End
O=Clear Vertical Interrupt
O=Enable Vertical Interrupt
Not Used
Bit O-Bit 3
Vertical Retrace End-These bits determine the
horizontal scan count value when the vertical
retrace output signal becomes inactive. The
register is programmed in units of horizontal scan
lines. To obtain a vertical retrace signal of width
W, the following algorithm is used: Value of Start
Vertical Retrace Register + width of vertical
retrace signal in horizontal scan units = 4-bit
result to be programmed into the End Horizontal
Retrace Register.
Bit 4
Clear Vertical Interrupt-A logical 0 will clear a
vertical interrupt.
Bit 5
Enable Vertical Interrupt-A logical 0 will
enable vertical interrupt.
Light Pen Low Register
This is a read-only register pointed to when the value in the CRT
Controller address register is hex 11. The processor input port
address for this register is hex 3B5 or 3D5.
August 2, 1984
IBM Enhanced Graphics Adapter 37
Light Pen Low Register Format
Bit
7
6
5
4
3
2
1
0
I I I I I I I I
..
Low Order Memory Address
Counter
Light Pen Low-This is is the low-order 8 bits of
the memory address counter at the time the light
pen was triggered.
Bit O-Bit 7
Vertical Display Enable End Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 12. The processor output port
address for this register is hex 3B5 or hex 3D5.
Vertical Display Enable End Register Format
Bit
7
6
5
4
3
2
1
0
I I I I I I I I .
Bit O-Bit 7
Low Order Vertical Display
Enable End
Vertical Display Enable End-These are the
low-order 8 bits of the vertical display enable end
position. This address specifies which scan line
ends the active video area of the screen. Bit 8 is
in the overflow register location hex 07.
Offset Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 13. The processor output port
address for this register is hex 3B5 or hex 3D5.
38
mM Enhanced Graphics Adapter
August 2,1984
Offset Register Format
Bit
7
6
5
4
3
2
1
I I I I
a
I •
Logical line width of the screen
Offset-This register specifies the logical line
width of the screen. The starting memory
address for the next character row is larger than
the current character row by this amount. The
Offset Register is programmed with a word
address. Depending upon the method of clocking
the CRT Controller, this word address is either a
word or double word address.
Bit O-Bit 7
Underline Location Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 14. The processor output port
address for this register is hex 3B5 or hex 3D5.
Underline Location Register Format
Bit
7
6
5
III
Bit O-Bit 4
4
3
2
I I I
1
a
:
Horizontal row scan where
underline will occur
Not Used
Underline Location-This register specifies the
horizontal row scan on which underline will
occur. The value programmed is one less than
the scan line number desired.
Start Vertical Blanking Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 15. The processor output port
August 2, 1984
IBM Enhanced Graphics Adapter 39
address for this register is hex 3BS or hex 3DS.
Start Vertical Blanking Register Format
Bit
7
6
5
4
3
2
1
0
I I I I I I I•
Bit O-Bit 7
Start Vertical Blanking
Start Vertical Blank-These are the low 8 bits of
the horizontal scan line count, at which the
vertical blanking signal becomes active. Bit 8 bit
is in the overflow register hex 07.
End Vertical Blanking Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 16. The processor output port
address for this register is hex 3BS or hex 3DS.
End Vertical Blanking Register Format
BH
7
6
5
4
III
Bit O-Bit 4
3
2
1
0
I I I I
:
End Vertical Blanking
Not Used
End Vertical Blank-This register specifies the
horizontal scan count value when the vertical
blank output signal becomes inactive. The
register is programmed in units of horizontal scan
lines. To obtain a vertical blank signal of width
W, the following algorithm is used: Value of Start
Vertical Blank Register + width of vertical blank
signal in horizontal scan units = S-bit result to be
programmed into the End Vertical Blank
Register.
40 mM Enhanced Graphics Adapter
August 2, 1984
Mode Control Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 17. The processor output port
address for this register is hex 3B5 or hex 3D5.
Mode Control Register Format
Bit
7
6
5
4
3
2
1
0
II I : ~::c~
Row Sea" Co",le,
Horizontal Retrace Select
'-------I~
Count by Two
L.--------i~ Output Control
L--_ _ _ _ _--I~
Address Wrap
L.----------i~ Word/Byte Mode
' - - - - - - - - - -.... Hardware Reset
Bit 0
August 2, 1984
Compatibility Mode Support- When this bit is
a logical 0, the row scan address bit 0 is
substituted for memory address bit 13 during
active display time. A logical 1 enables memory
address bit 13 to appear on the memory address
output bit 13 signal of the CRT Controller. The
CRT Controller used on the IBM
Color/Graphics Monitor Adapter is the 6845.
The 6845 has 128 horizontal scan line address
capability. To obtain 640 by 200 graphics
resolution, the CRTC was programmed for 100
horizontal scan lines with 2 row scan addresses
per character row. Row scan address bit 0
became the most significant address bit to the
display buffer. Successive scan lines of the
display image were displaced in memory by 8K
bytes. This bit allows compatibility with the
6845 and Color Graphics APA modes of
operation.
IBM Enhanced Graphics Adapter 41
Bit 1
Select Row Scan Counter-A logical 0 selects
row scan counter bit 1 on MA 14 output pin. A
logical 1 selects MA 14 counter bit on MA 14
output pin.
Bit 2
Horizontal Retrace Select-This bit selects
Horizontal Retrace or Horizontal Retrace divided
by 2 as the clock that controls the vertical timing
counter. This bit can be used to effectively
double the vertical resolution capability of the
CRT Controller. The vertical counter has a
maximum resolution of 512 scan lines due to the
9-bit wide Vertical Total Register. If the vertical
counter is clocked with the horizontal retrace
divided by 2 clock, then the vertical resolution is
doubled to 1024 horizontal scan lines. A logical
o selects HRTC and a logical 1 selects HRTC
divided by 2.
Bit 3
Count By Two- When this bit is set to 0, the
memory address counter is clocked with the
character clock input. A logical 1 clocks the
memory address counter with the character clock
input divided by 2. This bit is used to create
either a byte or word refresh address for the
display buffer.
Bit 4
Output Control-A logical 0 enables the module
output drivers. A logical 1 forces all outputs into
high impedance state.
Bit 5
Address Wrap-This bit selects Memory Address
counter bit MA 13 or bit MA 15, and it appears
on the MA 0 output pin in the word address
mode. If you are not in the word address mode,
MA 0 counter output appears on the MA 0
output pin. A logical 1 selects MA 15. In
odd/ even mode, bit MA 13 should be selected
when the 64K memory is installed on the board.
Bit MA 15 should be selected when greater then
64K memory is installed. This function is used to
implement Color Graphics Monitor Adapter
compatibility.
42 IBM Enhanced Graphics Adapter
August 2, 1984
Word Mode or Byte Mode-When this bit is a
logical 0, the Word Mode shifts all memory
address counter bits down one bit, and the most
significant bit of the counter appears on the least
significant bit of the memory address outputs.
See table below for address output details. A
logical 1 selects the Byte Address mode.
Bit 6
Internal Memory Address Counter
Wiring to the Output Multiplexer
CRTC Out Pin
Byte Address
Mode
MA O/RFA 0
MA 1/RFA 1
MA 2/RFA 2
MA3/RFA 3
MAO
MA1
MA2
MA3
MA 15 or MA 13
MAO
MA1
MA2
*
*
*
*
*
*
MA14
MA15
MA13
MA14
*
*
*
MA 14/RS 3
MA 15/RS 4
Word Address
Mode
Hardware Reset-A logical 0 forces horizontal
and vertical retrace to clear. A logical 1 forces
horizontal and vertical retrace to be enabled.
Bit 7
Line Compare Register
This is a write-only register pointed to when the value in the CRT
Controller address register is hex 18. The processor output port
address for this register is hex 3B5 or hex 3D5.
Line Compare Register Format
Bit
7
6
5
4
3
2
1
0
I I I I I I I I
Bit O-Bit 7
August 2, 1984
Line Compare Target
Line Compare-This register is the low-order 8
bits of the compare target. When the vertical
IBM Enhanced Graphics Adapter 43
counter reaches this value, the internal start of
the line counter is cleared. This allows an area of
the screen to be immune to scrolling. Bit 8 of
this register is in the overflow register hex 07.
44 mM Enhanced Graphics Adapter
August 2, 1984
Graphics Controller Registers
Name
Port
Index
Graphics 1 Position
Graphics 2 Position
Graphics 1 & 2 Address
Set/Reset
Enable Set/Reset
Color Compare
Data Rotate
Read Map Select
Mode Register
Miscellaneous
Color Don't Care
Bit Mask
3CC
3CA
3CE
3CF
3CF
3CF
3CF
3CF
3CF
3CF
3CF
3CF
-
00
01
02
03
04
05
06
07
08
Graphics 1 Position Register
This is a write-only register. The processor output port address
for this register is hex 3CC.
Graphics I Position Register Format
Bit
7
6
5
4
3
2
1
0
IIIIIII~
Bit O-Bit 1
August 2, 1984
Position 0
Position 1
Not Used
Position-These 2 bits are binary encoded
hierarchy bits for the graphics chips. The
position register controls which 2 bits of the
processor data bus each chip responds to.
Graphics 1 must be programmed with a position
register value of 0 for this card.
mM Enhanced Graphics Adapter
45
Graphics 2 Position Register
This is a write-only register. The processor output port address
for this register is hex 3CA.
Graphics II Position Register Format
B~
7
6
5
4
3
2
1
0
Position 0
Position 1
Not Used
Bit O-Bit 1
Position-These 2 bits are binary encoded
hierarchy bits for the graphics chips. The
position register controls which 2 bits of the
processor data bus to which each chip responds.
Graphics 2 must be programmed with a position
register value of 1 for this card.
Graphics 1 and 2 Address Register
This is a write-only register and the processor output port address
for this register is hex 3CE.
Graphics 1 and 2 Address Register Formats
Bit
7
6
5
4
IIII
Bit 0-B1t 3
3
2
1
0
:
Graphics Address
Not Used
Graphics 1 and 2 Address Bits-This output loads
the address register in both graphics chips
simultaneously. This register points to the data
register of the graphics chips.
46 IBM Enhanced Graphics Adapter
August 2, 1984
Set/Reset Register
This is a write-only register pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 00
before writing can take place. The processor output port address
for this register is hex 3CF.
Set/Reset Register Format
Bit
7
6
5
4
E
3
2
1
0
I ~set/Reset
Bit 0
~set/Reset Bit 1
Set/Reset Bit 2
Set/Reset Bit 3
L-~~--L-----------~NotUsed
Bit O-Bit 3
Set/Reset--These bits represent the value
written to the respective memory planes when the
processor does a memory write with write mode 0
selected and set! reset mode is enabled.
Set/Reset can be enabled on a plane by plane
basis with separate OUT commands to the
Set/Reset register.
Enable Set/Reset Register
This is a write-only register and is pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 01
before writing can take place. The processor output port for this
register is hex 3CF.
January 20, 1986
IBM Enhanced Graphics Adapter
47
Enable Set/Reset Register Format
Bit
7
6
5
4
3
2
1
0
III~L~
"oabl.
Sot,R"., BII a
Enable Set/Reset Bit 1
Enable Set/Reset Bit 2
Enable Set/Reset Bit 3
~~~--~----------~NotUsed
Bit O-Bit 3
Enable Set/Reset--These bits enable the
set/ reset function. The respective memory plane
is written with the value of the Set/Reset register
provided the write mode is o. When write mode is
o and Set/Reset is not enabled on a plane, that
plane is written with the value of the processor
data.
Color Compare Register
This is a write-only register pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 02
before writing can take place. The processor output port address
for this register is hex 3CF.
Color Compare Register Format
Bit
7
6
5
4
3
2
1
0
I I L:
Colo' Comp'" a
Color Compare 1
Color Compare 2
L...-_ _ _~
Color Compare 3
~~~--~----------~NotUsed
Bit O-Bit 3
48
Color Compare--These bits represent a 4 bit
color value to be compared. If the processor sets
IBM Enhanced Graphics Adapter
January 20, 1986
read mode 1 on the graphics chips, and does a
memory read, the data returned from the memory
cycle will be a 1 in each bit position where the 4
bit planes equal the color compare register.
Data Rotate Register
This is a write-only register pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 03
before writing can take place. The processor output port address
for this register is hex 3CF.
Data Rotate Register Format
Bit
7
6
5
4
3
2
1
0
Rotate Count
Rotate Count 1
Rotate Count 2
Function Select
Not Used
Bit O-Bit 2
Rotate Count-These bits represent a binary
encoded value of the number of positions to
rotate the processor data bus during processor
memory writes. This operation is done when the
write mode is O. To write unrotated data the
processor must select a count of O.
Bit 3-Bit 4
Function Select-Data written to memory can
operate logically with data already in the
processor latches. The bit functions are defined
in the following table.
August 2, 1984
IBM Enhanced Graphics Adapter 49
Bits
4 3
o0
o1
Data unmodified.
Data AND'ed with latched data.
Data OR'ed with latched data.
Data XOR'ed with latched data.
1 0
1 1
Data may be any of the choices selected by the Write Mode
Register except processor latches. If rotated data is selected, the
rotate applies before the logical function.
Read Map Select Register
This is a write-only register pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 04
before writing can take place. The processor output port address
for this register is hex 3CF.
Read Map Select Register Format
Bit
7
6
5
4
3
2
1
0
Map Select 0
Map Select 1
Map Select 2
Not Used
Bit O-Bit 2
Map Select-These bits represent a binary
encoded value of the memory plane number from
which the processor reads data. This register has
no effect on the color compare read mode
described elsewhere in this section.
Mode Register
This is a write-only register pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 05
50 IBM Enhanced Graphics Adapter
August 2, 1984
before writing can take place. The processor output port address
for this register is 3CF.
Mode Register Format
Bit
7
6
5
4
3
2
1
0
II : : :
Wdt, Mod,
Test Condition
Read Mode
'-------~
Odd/Even
'--------~ Shift Register Mode
'--..L-_ _ _ _ _ _ _
Bit O-Bit 1
~
Not Used
Write Mode
Bits
1 0
o0
o1
1 0
1 1
Each memory plane is written with the
processor data rotated by the number of
counts in the rotate register, unless
Set/Reset is enabled for the plane. Planes
for which Set/Reset is enabled are written
with 8 bits of the value contained in the
Set/Reset register for that plane.
Each memory plane is written with the
contents of the processor latches. These
latches are loaded by a processor read
operation.
Memory plane n (0 through 3) is filled
with 8 bits of the value of data bit n.
Not Valid
The logic function specified by the function select
register also applies.
Bit 2
August 2, 1984
Test Condition-A logical 1 directs graphics
controller outputs to be placed in high impedance
state for testing.
IBM Enhanced Graphics Adapter 51
Bit 3
Read Mode-When this bit is a logical 0, the
processor reads data from the memory plane
selected by the read map select register. When
this bit is a logical 1, the processor reads the
results of the comparison of the 4 memory planes
and the color compare register.
Bit 4
Odd/Even-A logical 1 selects the odd/even
addressing mode, which is useful for emulation of
the Color Graphics Monitor Adapter compatible
modes. Normally the value here follows the value
of the Memory Mode Register bit 3 of the
Sequencer.
Bit S
Shift Register-A logical 1 directs the shift
registers on each graphics chip to format the
serial data stream with even numbered bits on the
even numbered maps and odd numbered bits on
the odd maps.
Miscellaneous Register
This is a write-only register pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 06
before writing can take place. The processor output port for this
register is hex 3CF.
Miscellaneous Register Format
Bit
7
6
5
4
3
2
1
0
Graphics Mode
Chain Odd Maps to Even
Memory MapO
Memory Map 1
Not Used
S2 IBM Enhanced Graphics Adapter
August 2, 1984
Bit 0
Graphics Mode-This bit controls alpha-mode
addressing. A logical 1 selects graphics mode.
When set to graphics mode, the character
generator address latches are disabled.
Bit 1
Chain Odd Maps To Even Maps-When set to 1,
this bit directs the processor address bit 0 to be
replaced by a higher order bit and odd/even
maps to be selected with odd/even values of the
processor AO bit, respectively.
Bit 2-Bit 3
Memory Map-These bits control the mapping of
the regenerative buffer into the processor address
space.
Bits
3 2
o0
o1
1 0
1 1
Hex AOOO for 128K bytes.
Hex AOOO for 64K bytes.
Hex BOOO for 32K bytes
Hex B800 for 32K bytes.
If the display adapter is mapped at address hex AOOO for 128K
bytes, no other adapter can be installed in the system.
Color Don't Care Register
This is a write-only register and is pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 07
before writing can take place. The processor output port for this
register is hex 3 CF.
August 2, 1984
mM Enhanced Graphics Adapter 53
Color Don't Care Register Format
Bit
7
6
5
4
3
2
1
a
Color Plane a=Oon't Care
Color Plane 1=Oon't Care
Color Plane 2=Oon't Care
Color Plane 3=Oon't Care
Not Used
Color Don't Care-Color plane O=don't care
when reading color compare when this bit is set to
Bit 0
1.
Color Don't Care-Color plane 1 =don't care
when reading color compare when this bit is set to
Bit 1
1.
Color Don't Care-Color plane 2=don't care
when reading color compare when this bit is set to
Bit 2
1.
Color Don't Care-Color plane 3=don't care
when reading color compare when this bit is set to
Bit 3
1.
Bit Mask Register
This is a write-only register and is pointed to by the value in the
Graphics 1 and 2 address register. This value must be hex 08
before writing can take place. The processor output port for this
register is hex 3 CF.
Bit Mask Register Format
Bit
7
6
5
4
3
2
1
a
II I I II II•
a-Immune to change
1-Unimpeded Writes
54 IBM Enhanced Graphics Adapter
August 2, 1984
Bit O-Bit 7
Bit Mask-Any bit programmed to n causes the
corresponding bit n in each bit plane to be
immune to change provided that the location
being written was the last location read by the
processor. Bits programmed to a 1 allow
unimpeded writes to the corresponding bits in the
pit planes.
The bit mask applies to any data written by the processor (rotate,
AND'ed, OR'ed, XOR'ed, DX and SIR). To preserve bits using
the bit mask, data must be latched internally by reading the
location. When data is written to preserve the bits, the most
current data in latches is written in those positions. The bit mask
applies to all bit planes simultaneously.
January 20, 1986
IBM Enhanced Graphics Adapter
55
Attribute Controller Registers
Name
Port
Index
Address Register
Palette Registers
Mode Control Register
Overscan Color Register
Color Plane Enable Register
Horizontal Pel Panning Register
3CO
3CO
3CO
3CO
3CO
3CO
OO-OF
10
11
12
13
-
Attribute Address Register
This is a write-only register. The processor output port is hex
3CO.
Attribute Address Register Format
Bit
71
6
1
,
i I I 1:
Attribute Address
L-.-------i~Palette
Address Source
~~--------~- Not Used
Bit O-Bit 4
56
Attribute Address Bits-The Address Register is
a pointer register located at hex 3CO. This
register is loaded with a binary value that points
to the attribute data register where data is to be
written. The Attribute Controller does not have
an address bit input to control selection of the
address and data registers. An internal address
flip-flop controls selection of either the address
or data registers. To initialize the flip-flop, an
lOR instruction is issued to the Attribute
Controller at address 3BA or 3DA. This clears
the flip-flop, and selects the Address Register.
After the Address Register has been loaded, the
next OUT instruction loads the data register.
IBM Enhanced Graphics Adapter
January 20, 1986
The flip-flop toggles each time an OUT is issued
to the Attribute Controller.
Bit 5
Palette Address Source-When loading the color
palette registers, bit 5 must be cleared to O. To
enable the memory data to access the color
palette, bit 5 must be set to 1.
Palette Register Hex 00 through Hex OF
This is a write-only register. The processor output port is hex
3CO.
'
llli
Palette Registers Hex 00 through Hex OF Format
Bit
7
6
5
4
3
2
1
0
~ Blue Video
~ Green Video
1..-_ _ _ _ _ _
L-_ _ _ _ _ _~
Red Video
Secondary Blue/Mono Video
Secondary Green/Intensity
Secondary Red Video
L-....L_ _ _ _ _ _ _ _ _ Not Used
Sit O-Bit 5
Palette-These 6-bit registers allow a dynamic
mapping between the text attribute or graphic
color input value and the display color in the
CRT screen. A logical 1 selects the appropriate
color. A logical 0 de-selects. The color palette
register should be modified only during the
vertical retrace interval to avoid glitches in the
displayed image. Note that some color monitors
do not have an intensity input and only a
maximum of eight colors are available. Monitors
with four color inputs display sixteen colors, and
monitors with six color inputs display 64 colors.
January 20, 1986
IBM Enhanced Graphics Adapter
57
Mode Control Register
This is a write-only register pointed to by the value in the
Attribute address register. This value must be hex 10 before
writing can take place. The processor output port address for this
register is hex 3CO.
Mode Control Register Format
Bit
7
6
5
4
3
2
1
II
I:
0
Grnph'"IAlphaoome", Mode
Display Type
Enable Line Graphics Character
Codes
L....-_ _ _~
I--....L...........I._.L.-_ _ _ _ _~
Bit 0
Not Used
Graphics/ Alphanumeric Mode-A logical 0
selects alphanumeric mode. A logical 1 selects
graphics mode.
Bit 1
Bit 2
Select Background Intensity Or
Enable Blink
Monochrome Display/Color Display-A logical
A
logical 1 selects color Display attributes.
o selects IBM monochrome display attributes.
Enable Line Graphics Character Codes-When
this bit is set to 0, the ninth dot will be the same
as the background. A logical 1 enables the
special line graphics character codes for the IBM
Monochrome Display adapter. When enabled,
this bit forces the ninth dot of a line graphic
character to be identical to the eighth dot of the
character. The line graphics character codes for
the Monochrome Display Adapter are Hex CO
through Hex DF.
For character fonts that do not utilize the line
graphics character codes in the range of Hex CO
58
IBM Enhanced Graphics Adapter
January 20, 1986
through Hex DF, bit 2 of this register should be a
logical O. Otherwise unwanted video information
will be displayed on the CRT screen.
Enable Blink/Select Background Intensity-A
logical 0 selects the background intensity of the
attribute input. This mode was available on the
Monochrome and Color Graphics adapters. A
logical 1 enables the blink attribute in
alphanumeric modes. This bit must also be set to
1 for blinking graphics modes.
Bit 3
Overscan Color Register
This is a write-only register pointed to by the value in the
Attribute address register. This value must be hex 11 before
writing can take place. The processor output port address for this
register is hex 3CO.
Overscan Color Register Format
Bit
7
6
5
4
3
2
1
0
I' I
: s.,.o"
B',. Bom.ceo'",
Selects Green Border Color
Selects Red Border Color
Selects Secondary Blue
Border Color
Selects Intensified or
Secondary Green
Selects Secondary Red
Border Color
Not Used
Bit O-Bit S
August 2, 1984
Overscan Color-This 6-bit register determines
the overscan (border) color displayed on the
CRT screen. For monochrome display this
register should be set to a value of O. A logical 1
selects the appropriate color.
IBM Enhanced Graphics Adapter S9
Color Plane Enable Register
This is a write-only register pointed to by the value in the
Attribute address register. This value must be hex 12 before
writing can take place. The processor output port address for this
register is 3CO.
Color Plane Enable Register Format
Bit
7
6
5
4
3
2
1
0
Enable Color Plane
Video Status MUX
Not Used
Bit O-Bit 3
Enable Color Plane-Writing a logical 1 in any
of bits 0 through 3 enables the respective display
memory color plane.
Bit 4-Bit 5
Video Status MUX-Selects two of the six color
outputs to be available on the status port. The
following table illustrates the combinations
available and the color output wiring.
COLOR PLANE
ENABLE REGISTER
INPUT STATUS
REGISTER ONE
BitS
Bit4
BitS
Bit4
0
0
1
1
0
1
0
1
Red
Secondary Blue
Secondary Red
Not Used
Blue
Green
Secondary Green
Not Used
Horizontal Pel Panning Register
This is a write-only register pointed to by the value in the
Attribute address register. This value must be hex 12 before
writing can take place. The processor output port address for this
register is hex 3CO.
60 IBM Enhanced Graphics Adapter
August 2, 1984
Horizontal Pel Panning Register Format
Bit
7
6
Bit O-Bit 3
5
4
3
2
1
0
Horizontal Pel Panning-This 4 bit register
selects the number of picture elements (pels) to
shift the video data horizontally to the left. Pel
panning is available in both A/N and AP A
modes. In Monochrome A/N mode, the image
can be shifted a maximum of 9 pels. In all other
A/N and AP A modes, the image can be shifted a
maximum of 8 pels. The sequence for shifting
the image is given below:
9 pels/character: 8,0, 1,2,3,4,5,6, 7
(Monochrome A/N mode only)
8 pels/character: 0, 1,2,3,4,5,6, 7 (All other
Modes)
August 2, 1984
IBM Enhanced Graphics Adapter 61
Programming Considerations
Programming the Registers
Each of the LSI devices has an address register and a number of
data registers. The address register serves as a pointer to the
other registers on the LSI device. It is a write-only register that is
loaded by the processor by executing an 'OUT' instruction to its
I/O address with the index of the selected data register.
The data registers on each LSI device are accessed through a
common I/O address. They are distinguished by the pointer
(index) in the address register. To write to a data register, the
address register is loaded with the index of the appropriate data
register, then the selected data register is loaded by executing an
'OUT' instruction to the common I/O address.
The external registers that are not part of an LSI device and the
Graphics I and II registers are not accessed through an address
register; they are written to directly.
The following tables define the values that are loaded into the
registers by BIOS to support the different modes of operation
supported by this adapter.
62 IBM Enhanced Graphics Adapter
August 2, 1984
Register
Made of Operation
Hlme
Part
Index
0
1
2
3
Miscellaneous
3C2
Feature Cntrl
3?A
-
Input Stat 0
3C2
-
-
-
-
-
-
3?2
-
-
-
-
-
-
Input Stat 1
5
4
6
7
E
0
F 10
F: 10: 0- I- 2- 3-
23 23 23 23 23 23 23 A6 23 23 A2 A7 A2 A7 A7 A7 A7 A7
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
? = B in monochrome modes
-
- - - - - - -
- - - - -
-
-
-
-
-
-
-
-
-
-
? = D in color modes
'Values for these modes when the IBM Enhanced Color Display is attached
:Values for these modes when greater than 64 K Graphics Memory is installed
External Registers
Register
Made of Operation
F: 10: 0- I- 2- 3-
Port
Index
0
I
2
3
4
5
6
7
0
E
F 10
Seq Address
3C4
-
-
-
-
-
-
-
-
-
-
-
-
Reset
3C5
00
03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03
Clock Mode
3C5
01
DB DB 01
Map Mask
3C5
02
03 03 03 03 03 03 01
Char Gen Sel
3C5
03
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Memory Mode
3C5
04
03 03 03 03 02 02 06 03 06 06 00 00 06 06 03 03 03 03
Nlme
01
DB DB 01
00 DB 01
- - -
05 05 01
-
-
-
01 DB DB 01
-
01
03 OF OF OF OF OF OF 03 03 03 03
'Values for these modes when the IBM Enhanced Color Display is attached
:Values for these modes when greater than 64K Graphics Memory is installed
Sequencer Registers
August 2, 1984
IBM Enhanced Graphics Adapter 63
HI,lltlr
Midi
3
5
6
7
I'
O,ll1llon
0
E
F 10
Ft 10: 0' I' 2' 3'
-
-
-
-
Ptrt
lodn
0
I
Address Reg
3?4
-
-
- -
Horiz Total
3?5
00
37 37 70 70 37 37 70 60 37 70 60 5B 60 5B 20 20 5B 5B
Hrz Oisp End
3?5
01
27 27 4F 4F 27 27 4F 4F 27 4F 4F 4F 4F 4F 27 27 4F 4F
Strt Hrz Blk
3?5
02
20 20 5C 5C 20 20 59 56 20 56 56 53 56 53 2B 2B 53 53
End Hrz Blk
3?5
03
37 37 2F 2F 37 37 20 3A 37 20 1A 17 3A 37 20 20 37 37
Strt Hrz Retr
3?5
04
31 31 5F 5F 30 30 5E 51 30 5E 50 50 50 52 28 28 51 51
NIIII
2
4
- -
- - -
-
-
-
- - -
End Hrz Relr
3?5
05
15 15 07 07 14 14 06 60 14 06 EO BA
Vert Total
3?5
06
04 04 04 04 04 04 04 70 04 04 70 6C 70 6C 6C 6C 6e 6C
Overflow
3?5
07
11 11 11 11 11 11 11 1F 11 11 1F 1F 1F 1F 1F 1F 1F 1F
Preset Row SC
3?5
08
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Max Scan line
3?5
09
07 07 07 07 01
Cursor Start
3?5
OA
06 06 06 06 00 00 00 DB 00 00 00 00 00 00 DB DB DB DB
Cursor End
3?5
DB
07 07 07 07 00 00 00 DC 00 00 00 00 00 00 DC DC DC DC
Strt Addr Hi
3?5
DC
Strt Addr Lo
3?5
00
-
? = B in monochrome modes
- - -
- - -
60 00 60 60 58 5B
01 01 00 00 00 00 00 00 00 00 00 00 00
- - - - -
- - -
-
-
- - - - - - - - - -
-
? = 0 in color modes
'Values for these modes when the IBM Enhanced Color Display is attached
:Values for these modes when greater than 64 K Graphics Memory is installed
CRT Controller Registers (1 of 2)
64 IBM Enhanced Graphics Adapter
August 2, 1984
Mode of Oplration
RIglsllr
0
E
F 10 F:
-
-
-
-
-
10:
Port
fndex
0
1
2
3
4
Cursor LC Hi
3?5
OE
-
-
-
Cursor LC Low
3?5
OF
-
-
-
-
- - - - - - -
Vrt Retr Strt
3?5
10
EI
EI
EI
EI
EI
EI
EO 5E EI EO 5E 5E 5E 5E 5E 5E 5E 5E
Light Pen Hi
3?5
10
-
- -
-
-
-
-
Vert Retr End
3?5
II
24 24 24 24 24 24 23 2E 24 23 2E 2B 2E 2B 2B 2B 2B 2B
Lig ht Pen Low
3?5
11
-
Vrt Oisp End
3?5
12
C7 C7 C7 C7 C7 C7 C7 50 C7 C7 50 50 50 50 50 50 50 50
Offsel
3?5
13
14 14 28 28 14 14 28 28 14 28 14 14 28 28 14 14 28 28
Underline Loc
3?5
14
08 08 08 08 00 00 00 00 00 00 00 OF 00 OF OF OF OF OF
Strt Vert Blk
3?5
15
EO EO EO EO EO EO OF 5E EO OF 5E 5F 5E 5F 5E 5E 5E 5E
End Vert Blk
3?5
16
FO FO FO FO FO FO EF 6E FO EF 6E OA 6E OA OA OA OA OA
Mode Control
3?5
17
A3 A3 A3 A3 A2 A2 C2 A3 E3 E3 8B 8B E3 E3 A3 A3 A3 A3
Line Compare
3?5
18
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
Nlml
? = B in monochrome modes
- -
5
6
7
-
-
-
- - - - - - -
-
0' I' 2' 3'
-
-
-
-
-
-
-
- -
-
-
-
- -
-
- -
-
- - - -
-
? = 0 in color modes
'Values for these modes when the IBM Enhanced Color Display is attached
;Values for these modes when greater than 64K Graphics Memory is installed
CRT Controller Registers (2 of 2)
August 2, 1984
IBM Enhanced Graphics Adapter 65
Register
Name
Mode of Operation
5
F 10 Ft 10i 0- 1- 2- 3-
Port
Index
Grphx I Pas
3CC
-
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Grphx II Pas
3CA
-
01
01
01
01
01
01
01
01
01
01
Grphx III AD
3CE
-
-
-
-
-
-
-
- - - -
-
- -
Set Reset
3CF
00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Enable SIR
3CF
01
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Color Compare
3CF
02
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Data Rotate
3CF
03
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Read Map Sel
3CF
04
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Mode Register
3CF
05
10 10 10 10 30 30 00 10 00 00 10 10 00 00 10 10 10 10
0
2
1
3
4
7
6
01
E
0
01
01
01
01
01
01
-
-
-
- -
01
Miscellaneous
3CF
06
OE DE OE DE OF OF 00 OA 05 05 07 07 05 05 DE DE DE DE
Color No Care
3CF
07
00 00 00 00 00 00 00 00 OF OF OF OF OF OF 00 00 00 00
Bit Mask
3CF
08
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
'Values for these modes when the IBM Enhanced Color Display is attached
:values for these modes when greater than 64 K Graphics Memory is installed
Graphics 51 Registers
66 IBM Enhanced Graphics Adapter
August 2, 1984
Rlglsllr
Modi 01 Oplrilian
0
1
5
6
- -
-
- -
3?A
-
- - -
Palette
3CO
Q()
00 Q() 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Palette
3CO
01
01
Palette
3CO
02
02 02 02 02 15 15 17 08 02 02 00 00 00 02 02 02 02 02
01
01
3
Ft 10: 0* 1* 2* 3*
Indl.
Address
2
4
Part
MIIII
01
7
0
E
F 10
-
-
-
13 13 17 08 01 01
-
08 01
-
-
08 01
01
-
01
- 01 01
Palette
3CO
03
03 03 03 03 17 17 17 08 03 03 00 00 00 03 03 03 03 03
Palette
3CO
04
04 04 04 04 02 02 17 08 04 04 18 04 18 04 04 04 04 04
Palette
3CO
05
05 05 05 05 04 04 17 08 05 05 18 07 18 05 05 05 05 05
Palette
3CO
06
06 06 06 06 06 06 17 08 06 06 00 00 00 06 14 14 14 14
Palette
3CO
07
07 07 07 07 07 07 17 08 07 07 00 00 00 07 07 07 07 07
Palette
3CO
08
10 10 10 10 10 10 17 10 10 10 00 00 00 38 38 38 38 38
Palette
3CO
09
11
Palette
3CO
OA
12 12 12 12 12 12 17 18 12 12 00 00 00 3A 3A 3A 3A 3A
Palette
3CO
OB
13 13 13 13 13 13 17 18 13 13 00 00 00 3B 3B 3B 3B 3B
? = B in monochrome modes
11
11
11
11
11
i7 18 11
11 08 01
08 39 39 39 39 39
? = D in color modes
'Values for these modes when the IBM Enhanced Color Display is attached
!Values for these modes when greater than 64 K Graphics Memory is installed
Attribute Registers (1 of 2)
August 2, 1984
IBM Enhanced Graphics Adapter 67
Modi of Opll1llon
Reglsler
Nlme
4
5
6
7
E
F 10 F! 10l 0" I" 2" 3"
Pori
Index
Palette
3CO
OC
14 14 14 14 14 14 17 18 14 14 00 04 00 3C 3C 3C 3C 3C
Palette
3CO
OD
15 15 15 15 15 15 17 18 15 15 18 07 18 3D 3D 3D 3D 3D
Palette
3CO
OE
16 16 16 16 16 16 17 18 16 16 00 00 00 3E 3E 3E 3E 3E
Palette
3CO
OF
17 17 17 17 17 17 18 17 17 00 00 00 3F 3F 3F 3F 3F 3F
Mode Conlrol
3CO
10
08 08 08 08 01
Overscan
3CO
11
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Color Plane
3CO
12
OF OF OF OF 03 03 01
Hrz Panning
3CO
13
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0
1
2
3
01
0
01 OE 01
01
DB DB OB 01
08 08 08 08
OF OF OF 05 05 05 OF OF OF OF OF
'Values for these modes when Ihe IBM Enhanced Color Display is attached
:Values for these modes when greater than 64 K Graphics Memory is installed
Attribute Registers (2 of 2)
68 IBM Enhanced Graphics Adapter
August 2, 1984
RAM Loadable Character Generator
The character generator on the adapter is RAM loadable and can
support characters up to 32 scan lines high. Two character
generators are stored within the BIOS and one is automatically
loaded into the RAM by the BIOS when an alphanumeric mode is
selected. The Character Map Select Register can be programmed
to define the function of bit 3 of the attribute byte to be a
character generator switch. This allows the user to select between
any two character sets residing in bit plane 2. This effectively
gives the user access to 512 characters instead of 256. character
tables may be loaded off line. The adapter must have 128K bytes
of storage to support this function. Up to four tables can be
loaded can be loaded with 256K of graphics memory installed.
The structure of the character tables is described in the following
figure. The character generator is in bit plane 2 and must be
protected using the map mask function.
Bit Plane 2
+OK
Character
Generator 0
+8K
Character
Generator 1
Character
I-++-+-++-+-+-HI-++-I-++-I-++-i-++-i-i Generator 2
Character
t-+-+-t-+-+-t-+-+-t-++-IH-+-IH-+-I-++-t-l Generator 3
+64K ~--------------------------~
The following figure illustrates the structure of each character
pattern. If the CRT controller is programmed to generate n row
August 2, 1984
IBM Enhanced Graphics Adapter 69
scans, then n bytes must be filled in for each character in the
character generator. The example assumes eight row scans per
character.
Byte Image
Address
CC * 32
+0
Data
18H
3EH
2
66H
3
66H
4
7EH
5
66H
6
66H
7
66H
CC = Value of the character code. For example, 41H in the case
of an ASCII "A".
Creating a 512 Character Set
This section describes how to create a 512 character set on the
IBM Color Display. Note that only 256 characters can be printed
on the printer. This is a special application which the Enhanced
Graphics Adapter will support. The 9 by 14 characters will be
displayed when attribute bit 3 is a logical 0, and the IBM
Color/Graphics Monitor Adapter 8 by 8 characters will be
displayed when the attribute bit 3 is a logical 1. This example is
for demonstrative purposes only. The assembly language routine
for creating 512 characters is given below. Debug 2.0 was used
for this example. The starting assembly address is 100 and the
character string is stored in location 200. This function requires
128K or more of graphics memory.
70 IBM Enhanced Graphics Adapter
August 2, 1984
alOO
movax,1102
mov bl,02
intlO
;load 8x8 character font in character
;generator number 2
movax,1103
mov bl,08
intlO
;select 512 character operation
;if attribute bit 3 = 1 use 8x8 font
;if attribute bit 3=0 use 9x14 font
movax,lOOO
mov bx,07l2
intlO
;set color plane enable to 7H to disable
;attribute bit 3 in the color palette
;lookup table
movax,130l
mov bx,OOOF
mov cx,003A
mov dx,1600
mov bp,0200
push cs
popes
intlO
mov ax ,1301
mov bx,0007
mov cx,003A
mov dx,1700
mov bp,0200
push cs
popes
intlO
int 3
a200 db
;write char. string with attribute bit 3 = 1
;cx = character string length
;write character on line 22 of display
;pointer to character string location
;write char. string with attribute bit 3 =0
;cx = character string length
;write character on line 23 of display
;pointer to character string location
"This character string is used to show 512
characters"
Creating an 80 by 43 Alphanumeric Mode
The following examples show how to create 80 column by 43
row, both alphanumeric and graphics, images on the IBM
Monochrome Display. The BIOS Interface supports an 80
column by n row display by using the character generator load
routine call. The print screen routine must be revectored to
August 2, 1984
IBM Enhanced Graphics Adapter 71
handle the additional character rows on the screen. The assembly
language required for both an alphanumeric and a graphics screen
is shown below.
moval,7
int10
movax,1112
mov bI,O
int10
movax,1200
move bI,20
int10
int3
;Monochrome alphanumeric mode
;video interrupt call
;character generator BIOS routine
;load 8 by 8 double dot character font
;video interrupt call
;alternate screen routine
;select alternate print screen routine
;video interrupt call
movax,f
int10
movax,1123
mov bl,O
mov di,28
int10
movax,1200
mov bl,20
int10
int3
;Monochrome graphic mode
;video interrupt call
;character generator BIOS routine
;load 8 by 8 double dot character font
;43 character rows
;video interrupt call
;alternate screen routine
;alternate print screen routine
;video interrupt call
Vertical Interrupt Feature
The Enhanced Graphics Adapter can be programmed to create an
interrupt each time the vertical display refresh time has ended.
An interrupt handler routine must be written by the application to
take advantage of this feature. The CRT Vertical interrupt is on
IRQ2. The CPU can poll the Enhanced Graphics Adapter Input
Status Register 0 (bit 7) to determine whether the CRTC caused
the interrupt to occur.
The Vertical Retrace End Register (11H) in the CRT controller
contains two bits which are used to control the interrupt circuitry.
The remaining bits must be output as per the value in the mode
table.
72 IBM Enhanced Graphics Adapter
August 2, 1984
Bit 5
Enable Vertical Interrupt-A logical 0 will
enable vertical interrupt.
Bit 4
Clear Vertical Interrupt-A logical 0 will clear a
vertical interrupt.
The sequence of events which occur in an interrupt handler are
outlined below.
1.
2.
3.
4.
5.
6.
7.
8.
Clear IRQ latch and enable driver
Enable IRQ latch
Wait for vertical interrupt
Poll Interrupt Status Register 0 to determine if CRTC has
caused the interrupt
If CRTC interrupt, then clear IRQ latch; if not, then branch
to next interrupt handler.
Enable IRQ latch
Update Enhanced Graphics Adapter during vertical blanking
interval
Wait for next vertical interrupt
Creating a Split Screen
The Enhanced Graphics Adapter hardware supports an
alphanumeric mode dual screen display. The top portion of the
screen is designated as screen A, and the bottom portion of the
screen is designated as screen B as per the following figure.
Screen A
Screen 8
Dual Screen Definition
The following figure shows the screen mapping for a system
containing a 32K byte alphanumeric storage buffer. Note that the
Enhanced Graphics Adapter has a 32K byte storage buffer in
alphanumeric mode. Information displayed on screen A is
August 2,1984
IBM Enhanced Graphics Adapter 73
defined by the start address high and low registers (OCH and
ODH) of the CRTC. Information displayed on screen B always
begins at address OOOOH.
OOOOH . - - - - - - - - ,
Screen B
Buffer Storage Area
OFFFH 1 - - - - - - - - ;
1000H
Screen A
Buffer Storage Area
7FFFH '--_ _ _ _ _--'
Screen Mapping Within the Display Buffer Address Space
The Line Compare Register (18H) of the CRT Controller is
utilized to perform the split screen function. The CRTC has an
internal horizontal scan counter, and logic which compares the
horizontal scan counter value to the Line Compare Register value
and clears the memory address generator when a compare occurs.
The linear address generator then sequentially addresses the
display buffer starting at location zero, and each subsequent row
address is is determined by the 16 bit addition of the start of line
latch and the offset register.
Screen B can be smoothly scrolled onto the CRT screen by
updating the Line compare in synchronization with the vertical
retrace signal. The information on screen B is immune from
scrolling operations which utilize the Start Address High and Low
registers to scroll through the Screen A address map.
Compatibility Issues
The CRT Controller on the IBM Enhanced Graphics Adapter is a
custom design, and is different than the 6845 controller used on
the IBM Monochrome Monitor Adapter and the IBM
Color/Graphics Monitor Adapter. It should be noted that several
CRTC register addresses differ between the adapters. The
following figure illustrates the registers which do not map directly
across the two controllers.
74 IBM Enhanced Graphics Adapter
August 2, 1984
Register
02H
6485 Function
Start Horiz. Retrace
EGA CRTC Function
Start Horiz. Blanking
03H
End Horiz. Retrace
End Horiz. Blanking
04H
Vertical Total
Start Horiz. Retrace
05H
Vertical Total Adjust
End Horiz. Retrace
06H
Vertical Displayed
Vertical Total
07H
Vertical Sync Position
Overflow
08H
Interlace Mode and Skew
Preset Row Scan
Existing applications which utilize the BIOS interface will
generally be compatible with the Enhanced Graphics Adapter.
Horizontal screen centering was required on the IBM
Color/Graphics Monitor Adapter in order to center the screen
when generating composite video. This was done through the
Horizontal Sync Position Register. Since the Enhanced Graphics
Adapter does not support a composite video monitor, programs
which do screen centering may cause loss of the screen image if
centering is attempted.
The Enhanced Graphics Adapter offers a wider variety of
displayable monochrome character attributes than the IBM
Monochrome Display Adapter. Some attribute values may
display differently between the two Adapters. The values listed in
the table below, in any combinations with the blink and intensity
attributes, will display identically.
Background
R G B
0
0
0
1
0 0
0 0
0 0
1
1
Foreground
R G B
0
0
1
0
0
0
1
0
0
1
1
0
Function
Non-Display
Underline
White Character/Black Background
Reverse Video
Software which explicitly addresses 3D8 (Mode Select Register)
or 3D9 (Color Select Register) on the Color Graphics Monitor
Adapter may produce different results on the Enhanced Graphics
Adapter. For example, blinking which is disabled by writing to
3D8 on the Color Graphics Adapter will not be disabled on the
Enhanced Graphics Adapter.
August 2, 1984
IBM Enhanced Graphics Adapter 7S
Interface
Feature Connector
The following is a description of the Enhanced Graphics Adapter
feature connector. Note that signals coming from the Enhanced
Graphics Adapter are labeled "inputs" and the signals coming to
the Enhanced Graphics Adapter through the feature connector
are labeled "outputs".
Signal
Description
J2
This pin is connected to auxiliary jack 2 on the rear
panel of the adapter.
R'OUT
Secondary red output
ATRS/L
Attribute shift load. This signal controls the
serialization of the video information. The shift
register parallel loads at the dot clock leading edge
when this signal is low.
G OUT
Primary green output
R'
Secondary red input
R
Primary red input
FC1
This signal is input from bit 1 (Feature Control Bit
1) of the Feature Control Register.
FCO
This signal is input from bit 0 (Feature Control Bit
0) of the Feature control Register.
FEAT 0
This signal is output to bit 5 (Feature Code 0) of
Input Status Register O.
B'/V
Secondary blue input/Monochrome video
YIN
Vertical retrace input
76 IBM Enhanced Graphics Adapter
August 2, 1984
Internal
This signal is output to bit 4 (Disable Internal Video
Drivers) of the Miscellaneous Output Register.
V OUT
Vertical retrace output
J1
This pin is connected to auxiliary jack 1 on the rear
panel of the adapter.
G'OUT
Secondary green output
B'OUT
Secondary blue output
BOUT
Blue output
G
Green input
B
Blue input
ROUT
Red output
BLANK
This is a composite horizontal and vertical blanking
signal from the CRTC.
FEAT 1
This signal is output to bit 6 (Feature Code 1) of
Input Status Register O.
G'/I
Secondary green/Intensity input
HIN
Horizontal retrace input from the CRTC
14MHZ
14 MHz signal from the system board
EXT OSC
External dot clock output
HOUT
Horizontal retrace output
August 2, 1984
IBM Enhanced Graphics Adapter 77
The following figure shows the layout and pin numbering of the
feature connector.
Signal Name
Signal Name
Gnd
1
2
...........
,
-12V
J1
+12V
J2
G'OUT
R'OUT
B'OUT
ATRS/L
BOUT
GOUT
G
R'
B
R
ROUT
FEAT 1
BLANK
FEAT 0
FC1
FCO
G'/I
B'!V
HIN
VIN
14MHz
Internal
EXTOSC
VOUT
GND
HOUT
31
'"
32
+SV
~
Feature Connector Diagram
78 IBM Enhanced Graphics Adapter
August 2, 1984
Specifications
System Board Switches
The following figure shows the proper system board DIP switch
settings for the IBM Enhanced Graphics Adapter when used with
the Personal Computer and the Personal Computer XT. The
switch block locations are illustrated in the Technical Reference
Manual "System Board Component Diagram". The Personal
Computer has two DIP switch blocks; the switch settings shown
pertain to DIP Switch Block 1. The Personal Computer XT has
one DIP switch block.
1
234
5
6
7
8
~DDDD~~DD
Switch Block (1)
Note: The DIP switches must be set as shown whenever the
IBM Enhanced Graphics Adapter is installed, regardless of
display type. This is true even when a second display adapter
is installed in the system.
August 2, 1984
IBM Enhanced Graphics Adapter 79
Configuration Switches
The following diagram shows the location and orientation of the
configuration switches on the Enhanced Graphics Adapter.
Optional
Graphics Memory
Expansion Card
Off
On
80 IBM Enhanced Graphics Adapter
August 2, 1984
Configuration Switch Settings
The configuration switches on the Enhanced Graphics Adapter
determine the type of display support the adapter provides, as
follows:
Switch Sellings lor Enhanced Graphics Adapter
as Primary Display Adapter
Configuration
SWI SW2 SW3 SW4
On
Off
Off
On
Enhanced
Adapter
Color Display
Monochrome
Adapter
Color/Graphics
Adapter
Secondary
-
Secondary
-
40x25
Off
Off
Off
On
Color Display
BOx25
On
On
On
Off
Enhanced Display
Emulation Mode
Secondary
-
Off
On
On
Off
Enhanced Display
Hi Res Mode
Secondary
-
On
Off
On
Off
Monochrome
-
Secondary
40x25
Off
Off
On
Off
Monochrome
-
Secondary
BOx25
August 2, 1984
IBM Enhanced Graphics Adapter 81
Switch Settings lor Enhanced Graphics Adapter
as Secondary Display Adapter
Conllguratlon
SWI SW2 SW3 SW4
On
On
On
On
Enhanced
Adapter
Color Display
Monochrome
Adapter
Color/Graphics
Adapter
Primary
-
Primary
-
40x25
Off
On
On
On
Color Display
BOx25
On
Off
On
On
Enhanced Display
Emulation Mode
Primary
-
Off
Off
On
On
Enhanced Display
Hi Res Mode
Primary
-
On
On
Off
On
Monochrome
-
Primary
40x25
Off
On
Off
On
Monochrome
-
Primary
BOx25
82 IBM Enhanced Graphics Adapter
August 2, 1984
Direct Drive Connector
o
9-Pin Direct
Drive Signal
Signal Name - Description
Direct
Drive
Display
August 2, 1984
Pin
Ground
1
Secondary Red
2
Primary Red
3
Primary Green
4
Primary Blue
5
Secondary Green/Intensity
6
Secondary Blue/Mono Video
7
Horizontal Retrace
8
Vertical Retrace
9
Enhanced
Graphics Adapter
IBM Enhanced Graphics Adapter 83
Light Pen Interface
P-2 Connector
P-2 Connector
Light Pen
Attachment
Pin
+Light Pen Input
1
Not used
2
+Light Pen Switch
3
Ground
4
+5 Volts
5
12 Volts
6
84 IBM Enhanced Graphics Adapter
Enhanced
Graphics Adapter
August 2, 1984
Jumper Descriptions
Located on the adapter are two jumpers designated PI and P3.
Jumper PI changes the function of pin 2 on the direct drive
interface. When placed on pins 2 and 3, jumper PI selects ground
as the function of direct drive interface, pin 2. This selection is
for displays that support five color outputs, such as the mM
Color Display. When PI is placed on pins I and 2, red prime
output is placed on pin 2 of the direct drive interface connector.
This supports the mM Enhanced Color Display, which utilizes six
color outputs on the direct drive interface.
Jumper P3 changes the I/O address port of the Enhanced
Graphics Adapter within the system. In its normal position, (pins
I and 2), all Enhanced Graphics Adapter addresses are in the
range 3XX. Moving jumper P3 to pins 2 and 3 changes the
addresses to 2XX. Operation of the adapter in the 2XX mode is
not supported in BIOS.
The following figure shows the location of the jumpers and
numbering of the connectors.
August 2, 1984
mM Enhanced Graphics Adapter 85
86 IBM Enhanced Graphics Adapter
August 2, 1984
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Graphics Memory Expansion Card Sheet 5 of 5
BIOS Listing
Vectors with Special Meanings
Interrupt Hex 42 - Reserved
When an IBM Enhanced Graphics Adapter is installed, the BIOS
routines use interrupt 42 to revector the video pointer.
Interrupt Hex 43 - IBM Enhanced Graphics Video
Parameters
When an IBM Enhanced Graphics Adapter is installed, the BIOS
routines use this vector to point to a data region containing the
parameters required for the initializing of the IBM Enhanced
Graphics Adapter. Note that the format of the table must adhere
to the BIOS conventions established in the listing. The power-on
routines initialize this vector to point to the parameters contained
in the IBM Enhanced Graphics Adapter ROM.
Interrupt Hex 44 - Graphics Character Table
When an IBM Enhanced Graphics Adapter is installed the BIOS
routines use this vector to point to a table of dot patterns that will
be used when graphics characters are to be displayed. This table
will be used for the first 128 code points in video modes 4,5, and
6. This table will be used for 256 characters in all additional
graphics modes. See the appropriate BIOS interface for
additional information on setting and using the graphics character
table pointer.
August 2, 1984
IBM Enhanced Graphics Adapter 103
1
2
3
PAGE, 120
TITLE
ENHANCED GRAPHICS ADAPTER BIOS
EXTRN
CGMN:NEAR, CGDDOT:NEAR.
4
5
6
EXTRN
END_ADDRESS: NEAR
7
THE BIOS ROUTINES ARE MEANT TO BE ACCESSED THROUGH
SOFTWARE INTERRUPTS ONLY,
ANY ADDRESSES PRESENT IN
THE LISTINGS ARE INCLUDED ONLY FOR COMPLETENESS,
NOT FOR REFERENCE.
APPLICATIONS WHICH
REFERENCE
ABSOLUTE
ADDRESSES
WITH I N
THE
CODE SEGMENT
VIOLATE THE STRUCTURE AND DESIGN OF BIOS.
6
9
10
11
12
13
14
15
INT_1F_':NEAR, CGMN_FOG:NEAR
• LIST
16
INCLUDE
VFRONT. I Ne
SUBTTL VfRONT. I Ne
PAGE
17
16
19
20
21
22
23
24
25
26
27
26
29
30
31
32
33
34
35
36
37
36
39
I NT 10 - --------- ------ ----------- - - -- -- --------------------- ------.
VIDEO 10
-THESE ROUTINES PROVIDE THE CRT INTERFACE
THE FOLLOW I NG FUNCT IONS ARE PROV IDEO:
(AH)"'O
AL AD
*
*
0 B8
1 S.
2 B8
3 S6
4 S6
5 S6
*
6 SS
7 BO
41
42
'"44
45
D AO
E AO
46
47
46
49
50
51
52
53
54
55
56
57
56
59
10 AO
FAD
(AH)=2
(AH)=3
(AH)=4
73
74
75
76
{AH)=5
77
(AH)=6
76
79
60
61
62
66
69
90
91
92
93
94
95
96
97
96
99
100
101
102
103
104
105
106
107
10.
109
110
111
112
113
114
115
116
117
11.
119
120
121
122
123
124
125
126
GRPHX
GRPHX
GRPHX
GRPHX
NOTES
OF-DIM
DISPLAY
40X25
40X25
80X25
80X25
40X25
40X25
80X25
80X25
COLOR - BW
COLOR
COLOR - BW
COLOR
COLOR
COLOR - BW
COLOR - BW
MONOCHROME
40X25
80X25
80X25
80X25
COLOR
COLOR
MONOCHROME
HI RES
MAX PGS
I NTERNAL USE
I NTERNAL USE
320X200
640X200
640X350
640X350
***
(AH):l
60
61
62
67
RES
64DX200
640X200
640X200
640X200
320X200
320X200
640X200
720X350
NOTE: HIGH BIT AL SET PREVENTS REGEN BUFFER CLEAR ON
MODES RUNNING ON THE COMBO VIDEO ADAPTER
63
64
65
66
67
66
69
70
71
72
66
TYPE
ALPHA
ALPHA
ALPHA
ALPHA
GRPHX
GRPHX
GRPHX
ALPHA
RESERVED
RESERVED
RESERVED
RESERVED RESERVED -
40
63
64
65
SET MODE (All CONTAINS MODE VALUE
(AH)=7
NOTE BW MODES OPERATE SAME AS COLOR MODES, BUT
COLOR BURST I S NOT ENABLED
SET CURSOR TYPE
(CH) '= BITS 4-0 = START LINE FOR CURSOR
** HARDWARE WILL ALWAYS CAUSE BLI NK
** SETTING BIT 5 OR 6 WILL CAUSE ERRATIC
BUNKING OR NO CURSOR AT All
(Cl) = BITS 4-0 = END LINE FOR CURSOR
SET CURSOR POSITION
(DH,Dl) = ROW,COlUMN
(0,0) IS UPPER lEFT
(BH) = PAGE NUMBER
READ CURSOR POSITION
(BH) = PAGE NUMBER
ON EXIT (DH,Dl) = ROW,COLUMN OF CURRENT CURSOR
(CH,CL) = CURSOR MODE CURRENTLY SET
READ LIGHT PEN POSITION
ON EXIT:
(AH) = 0 ~- LIGHT PEN SWITCH NOT DOWN/NOT TRIGGERED
(AH) '" 1 -- VALID liGHT PEN VALUE IN REGISTERS
(DH,DL) = ROW,COlUMN OF CHARACTER LP POSN
(CH) == RASTER LINE (0~199)
(CX) == RASTER LINE (O-NNN) NEW GRAPHICS MODES
(BX) = PIXEL COLUMN (0-319,639)
SELECT ACTIVE DISPLAY PAGE
(AL) = NEW PAGE VALUE, SEE AH==O FOR PAGE INFO
SCROLL ACTIVE PAGE UP
(Al) = NUMBER OF LINES, INPUT LINES BLANKED AT BOTTOM
OF WINDOW
AL '" 0 MEANS BLANK ENT I RE WI NDOW
(CH,Cl) = ROW,COLUMN OF UPPER LEFT CORNER OF SCROLL
(DH,Dl) = ROW,COLUMN OF lOWER RIGHT CORNER OF SCROLL
(BH) = ATTR IBUTE TO BE USED ON BLANK LINE
SCROLL ACTIVE PAGE DOWN
(Al) = NUMBER OF LINES, INPUT LINES BLANKED AT TOP
OF WINDOW
AL = 0 MEANS BLANK ENTIRE WINDOW
(CH,Cl) = ROW,COlUMN OF UPPER LEFT CORNER OF SCROLL
(DH,Dl) = ROW,COLUMN OF LOWER RIGHT CORNER OF SCROLL
(BH) = ATTR I BUTE TO BE USED ON BLANK LINE
CHARACTER HANDL I NG ROUT I NES
(AH) '" 8 READ ATTRIBUTE/CHARACTER AT CURRENT CURSOR POSITION
(BH) = DISPLAY PAGE
ON EXIT:
(ALI = CHAR READ
(AH) = ATTRIBUTE OF CHARACTER READ (ALPHA MODES ONLY)
(AH) = 9 WRITE ATTRIBUTE/CHARACTER AT CURRENT CURSOR POSITION
(BH) = DISPLAY PAGE
(CX) = COUNT OF CHARACTERS TO WRITE
(AL) = CHAR TO WRITE
(BL) == ATTRIBUTE OF CHARACTER (ALPHA)/COLOR Of CHAR
(GRAPHICS)
SEE NOTE ON WRITE DOT FOR BIT 7 Of 8l == 1.
(AH) '" A WRITE CHARACTER ONLY AT CURRENT CURSOR POSITION
(BH) = DISPLAY PAGE
(CX) = COUNT OF CHARACTERS TO WRITE
(Al) == CHAR TO WRITE
FOR READ/WRITE CHARACTER INTERFACE WHILE IN GRAPHICS MODE, THE
CHARACTERS ARE fORMED FROM A CHARACTER GENERATOR IMAGE
MAINTAINED IN THE SYSTEM ROM.
ONLY THE 1ST 128 CHARS
ARE CONTAINED THERE.
TO READ/WRITE THE SECOND 128
CHARS, THE USER MUST INITIALIZE THE POINTER AT
:
INTERRUPT lFH (lOCATION 0007CH) TO POINT TO THE 1K BYTE:
TABLE CONTAINING THE CODE POINTS fOR THE SECOND
:
128 CHARS (128~255).
FOR THE NEW GRAPH I CS MODES 256 GRAPH I CS CHARS ARE
SUPPL I ED I N THE SYSTEM ROM.
FOR WRITE CHARACTER INTERFACE IN GRAPHICS MODE, THE REPLICATION;
fACTOR CONTAINED IN (CX) ON ENTRY WILL PRODUCE VALID
:
RESULTS ONLY FOR CHARACTERS CONTAINED ON THE SAME ROW.
:
CONTINUATION TO SUCCEEDING LINES WILL NOT PRODUCE
:
CORRECTLY.
:
104 IBM Enhanced Graphics Adapter
August 2, 1984
127
C
C
C
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
, 77
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
August 2, 1984
C
126
129
130
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
GRAPHICS INTERFACE
(AH) = B SET COLOR PALETTE
FOR USE IN COMPATIBILITY MODES
(8H) = PALETTE COLOR ID BEING SET (0-127)
(Bll = COLOR VALUE TO BE USED WITH THAT COLOR 10
NOTE: FOR THE CURRENT COLOR CARD, THIS ENTRY POINT
HAS MEANING ONLY FOR 320X2DO GRAPHICS.
COLOR ID = 0 SELECTS THE BACKGROUND COLOR (0-15)
COLOR 10 = 1 SELECTS THE PALETTE TO BE USED:
O=GREEN(lj/RED(2)/BROWN(3)
1 = CYAN(1)/MAGENTA(2)/WHITE(3)
IN 40><25 OR 60X25 ALPHA MODES, THE VALUE SET
FOR PALETTE COLOR 0 INDICATES THE
BORDER COLOR TO BE USED (VALUES 0-31,
WHERE 16-31 SELECT THE HIGH INTENSITY
BACKGROUND SET).
(AH) = C WRITE DOT
(SH) = PAGE
(OX) '" ROW NUMBER
(ex) = COLUMN NUMBER
(AL) '" COLOR VALUE
If BIT 7 Of AL '" 1, THEN THE COLOR VALUE IS
EXCLUSIVE aR'D WITH THE CURRENT CONTENTS OF
THE DOT
(AH) '" 0 READ DOT
(BH) '" PAGE
(OX) = ROW NUMBER
ICX} = COLUMN NUMBER
(AL) RETURNS THE DOT READ
ASC I I TELETYPE ROUT I HE FOR OUTPUT
(AHI '" E
WRITE TELETYPE TO ACTIVE PAGE
(AL) = CHAR TO WRITE
(BL) '" FOREGROUND COLOR IN GRAPHICS MODE
NOTE -- SCREEN WIDTH IS CONTROLLED BY PREVIOUS MODE SET
(AHl '" F CURRENT VIDEO STATE
RETURNS THE CURRENT VIDEO STATE
(ALI = MODE CURRENTLY SET
(SEE AH=O FOR EXPLANATION)
(AH) = NUMBER OF CHARACTER COLUMNS ON SCREEN
(BH) = CURRENT ACTIVE DISPLAY PAGE
(AH) '" 10
SET PALETTE REGISTERS
(ALl = 0
SET INDIVIDUAL PALETTE REGISTER
BL = PALETTE REG I STER TO BE SET
BH = VALUE TO SET
AL = 1
SET OVERSCAN REG I STER
BH = VALUE TO SET
AL = 2
SET ALL PALETTE REGISTERS AND OVERSCAN
ES:DX POINTS TO A 17 BYTE TABLE
BYTES 0 ~ 15 ARE THE PALETTE VALUES, RESPECTIVELY
BYTE 16 L 5 THE OVERSCAN VALUE
C
C
AL = 3
TOGGLE INTENSIFY/BLINKING BIT
C
BL ~ 0
ENABLE INTENSI FY
C
BL - 1 ENABLE BLINKING
C
C
(AHl = 11 CHARACTER GENERATOR ROUTINE
C
NOTE: THIS CALL WILL INITIATE A MODE SET, COMPLETELY
C
RESETTING THE VIDEO ENVIRONMENT BUT MAINTAINING:
C
THE REGEN BUffER,
C
C
AL '" 00
USER ALPHA LOAD
C
ES:BP - POINTER TO USER TABLE
C
CX
- COUNT TO STORE
C
OX
- CHARACTER OFFSET INTO TABLE
C
BL
- BLOCK TO LOAD
C
BH
- NUMBER OF BYTES PER CHARACTER
C
AL = 01
ROM MONOCHROME SET
C
BL
- BLOCK TO LOAD
C
AL = 02
ROM 8X8 DOUBLE DOT
C
BL
- BLOCK TO LOAD
C
AL = 03
SET BLOCK SPEC I F I ER
C
BL
- CHAR GEN BLOCK SPECIFIER
C
03-02 ATTR BIT" 3 ONE,
CHAR GEN 0-3
C
01-00
ATTR BIT 3 ZERO, CHAR GEN 0-3
C
NOTE : WHEN US I NG AL = 03 A FUNCT I ON CALL
C
AX = 1000H
C
BX = 0712H
C I S RECOMMENDED TO SET THE COLOR PLANES
C
RESULTING IN 512 CHARACTERS AND EIGHT
C
CONS I STENT COLORS.
C
C
NOTE: THE FOLLOWING INTERFACE (AL=lXl IS SIMILAR IN FUNCTION
C
TO (AL=OX) EXCEPT THAT:
C
- PAGE ZERO MUST BE ACT I VE
C
- POINTS (BYTES/CHAR) WILL BE RECALCULATED
C
• ROWS WILL BE CALCULATED FROM THE FOLLOWING:
C
INT((200 OR 350) / POINTS] M 1
C
- CRT_LEN WILL BE CALCULATED FROM:
C
(ROWS + 1) * CRT COLS * 2
C
- THE CRTC WI LL BE REPROGRAMMED AS fOLLOWS:
C
R09H '" PO I NTS - 1
MAX SCAN LI NI::
C
R09H DONE ONLY IN MODE 7
C
ROAH '" POINTS - 2
CURSOR START
C
ROBH = 0
CURSOR END
C
R12H =
VERT DISP END
C
(ROWS + 1)
POINTS] - 1
C
R14H = POINTS
UNDERLINE LOC
C
C
THE ABOVE REGISTER CALCULATIONS MUST BE CLOSE TO THE
C
ORIGINAL TABLE VALUES OR UNDETERMINED RESULTS WILL
C
OCCUR.
C
C
NOTE: THE fOLLOWING INTERfACE IS DESIGNED TO BE
C
CALLED ONLY IMMEDIATELY AFTER A MODE SET HAS
:
C
BEEN ISSUED. FAILURE TO ADHERE TO THIS PRACTICE:
C
MAY CAUSE UNDETERMINED RESULTS,
C
C
AL = 10
USER ALPHA LOAD
C
ES: BP - PO I NTER TO USER TABLE
C
CX
- COUNT TO STORE
C
OX
- CHARACTER OffSET INTO TABLE
C
BL
- BLOCK TO LOAD
C
BH
- NUMBER OF BYTES PER CHARACTER
C
AL = 11
ROM MONOCHROME SET
C
BL
• BLOCK TO LOAD
C
AL = 12
ROM 8xe DOUBLE DOT
C
BL
- BLOCK TO LOAD
C
C
*
IBM Enhanced Graphics Adapter 105
0000
0014
0014
0040
0040
007C
007C
0108
0108
Oloe
Oloe
0410
0410
0410
0449
0449
044A
044C
044E
0450
?1
1711
????
11?7
08 I
7117
0460
0462
????
??
253
254
255
256
251
256
259
260
261
262
263
264
265
266
261
266
269
210
211
212
213
214
215
216
211
216
219
260
261
262
283
264
265
266
261
266
269
290
291
292
293
294
295
296
291
296
299
300
301
302
303
304
305
306
301
306
309
310
311
312
313
314
315
316
311
316
319
320
321
322
323
324
325
326
321
326
329
330
331
332
333
334
335
336
331
336
339
340
341
342
343
344
345
346
341
346
349
350
351
352
353
354
355
356
351
356
359
360
361
362
363
364
365
366
361
366
369
310
311
312
313
374
315
316
311
316
e
e
e
e
e
NOTE: THE FOLLOWING INTERfACE IS DESIGNED TO BE
CALLED ONLY IMMEDIATELY AfTER A MODE SET HAS
•
BEEN ISSUED. FAILURE TO ADHERE TO THIS PRACTICE:
MAY CAUSE UNDETERMI NED RESULTS.
:
e
e
AL = 20
e
e
e
e
e
e
e
e
AL = 21
e
e
e
e
e
e
AL=22
USER GRAPHICS CHARS
INT OlfH (8Xa)
E5:BP ~ POINTER TO USER TABLE
USER GRAPHICS CHARS
ES:BP - POINTER TO USER TABLE
ex
- PO I NTS (BYTES PER CHARACTER)
BL
- ROW SPECIFIER
e
e
e
AL = 30
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
43 (28H)
= 3
ex
BH
BH
BH
BH
BH
(AH) '" 12
OL
- 0
ES: BP
- 1
ES: BP
- 2
ES: BP
- 3
ES:BP
- 4
ES:BP
- 5
ES:BP
-
POINTS
ROWS
RETURN
PTR TO
RETURN
'PTR TO
RETURN
PTR TO
RETURN
PTR TO
RETURN
PTR TO
RETURN
PTR TO
CURRENT I NT 1 FH PTR
TABLE
CURRENT I NT 44H PTR
TABLE
ROM B X 14 PTR
TABLE
ROM DOUBLE DOT PTR
TABLE
ROM DOUBLE DOT PTR (TOP)
TABLE
ROM ALPHA ALTERNATE 9X14
TABLE
RETURN EGA INFORMATION
BH == 0 - COLOR MODE IN EffECT <3>
1 - MONDC MODE I N EffECT <3>
= MEMORY VALUE
0 - 064K
0 1 - 128K
10-192K
11-256K
CH = FEATURE BITS
CL == SWI TCH SETT I NG
BL
BL = 20
(AH) == 13
-
ALTERNATE SELECT
BL == 10
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
o
SELECT ALTERNATE PRINT SCREEN ROUTINE
WRITE STRING
ES;BP - POINTER TO STRING TO BE WRITTEN
CX
- CHARACTER ONLY COUNT
OX
- POSITION TO BEGIN STRING, IN CURSOR
TERMS
BH
- PAGE NUMBER
AL == 0
BL
- ATTRIBUTE
STRING - (CHAR, CHAR,
CURSOR NOT MOVED
CHAR,
.. )
BL
- ATTRIBUTE
STRING - (CHAR, CHAR,
CURSOR
I S MOVED
CHAR,
... )
AL == 1
AL = 2
STRING - (CHAR, ATTR, CHAR, ATTR,
CURSOR NOT MOVED
e
e
e
e
e
e
e
e
e
e
e
e
e
BL
INFORMATION
BH
e
e
e
e
e
e
e
e
e
e
e
e
e
e
USER
DL - ROWS
14 (OEH)
25 (19H)
ROM8X14SET
BL
- ROW SPECI FI ER
AL = 23
ROM 8 X 8 DOUBLE DOT
BL
-ROWSPECIFIER
e
e
e
C
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
BL '" 0
Bl = 1
Bl = 2
AL == 3
STRING - (CHAR, ATTR, CHAR, ATTR,
CURSOR
I S MOVED
.. )
.. )
NOTE: CHAR RET, LI NE FEED, BACKSPACE, AND BELL ARE
TREATED AS COMMANDS RATHER THAN PRINTABLE
CHARACTERS.
SRLOAD
MACRO
SEGREG, VALUE
I FNB
I fI ON , <0>
SUB
OX,OX
ELSE
MOV
OX, VALUE
ENOl F
ENOl F
MOV
SEGREG,OX
ENOM
; ----- LOW MEMORY SEGMENT
SEGMENT AT
ORe
005H*4
LABEL
ORe
D1DH*4
VIDEO
LABEL
ORe
01FH*4
EXT_PTR
LABEL
ABSO
I NTS_PTR
ORe
PLANAR_VIDEO
; PR I NT SCREEN VECTOR
OWORD
;
; GRAPHIC CHARS 128-255
DWORD
REVECTORED 10H*4
042H*4
LABEL
aWaRD
GRX_SET
043H*4
LABEL
aWaRD
ORG
EQU I P_LOW
EQUI P_FLAG
0410H
LABEL
OW
,
ORG
VIDEO I/O VECTOR
OWORD
GRAPHIC CHARS 0-255
BYTE
;----- REUSE RAM FROM PLANAR BIOS
ORG
CRT MODE
CRT-COLS
CRT:::\EN
CRT START
CURSOR_POSN
449H
DB
OW
OW
OW
aw
'7
'7
8 OUP( 1)
e
e
106 IBM Enhanced Graphics Adapter
August 2, 1984
0463
0465
0466
0472
0472
0484
0484
0485
0487
7117
77
71
1717
71
1117
11
37,
380
381
382
383
384
385
386
387
388
38.
390
3"392
0488
11
04A8
04A8
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
C
4"
C
412
413
414
4"
416
417
418
419
420
421
422
423
424
4"
426
427
428
429
430
431
432
4"
434
4"
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
4"
452
4"
.,4
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
0500
0500
0501
473
474
475
47.
477
478
17
== 0061
== 0040
'" 00C4
'" 00C5
== 0004
'" 00B4
== 0005
:= OOCC
'" OOCA
= OOCE
= OOCF
= OOC2
'" 00C2
'" OOBA
'" OODA
= OODA
= OOCO
C
C
C
C
C
C
C
C
C
C
C
C
C
503
504
0472H
0484H
1
INFO
OW
ROWS ON THE SCREEN
BYTES PER CHARACTER
?
08
INFO
07 06 05·04 03 02 01
00 -
HIGH BIT OF MODE SET, CLEAR/NOT CLEAR REGEN
MEMORY 06 05 == 0 0 - 064K
0 1
1281<
MEMORY
1 0 - '92K
1 1 - 256K
RESERVED
EGA ACTIVE MONITOR (0), EGA NOT ACTIVE (1)
WAIT FOR DISPLAY ENABLE (1)
EGA HAS A MONOCHROME ATTACHED (1)
SET C_TYPE EMULATE ACTIVE (O)
INFO_3
07-04
03-00
FEATURE BITS
SWITCHES
04A8H
LABEL
DWORD
SAVE_PTR IS A PO I NTER TO A TABLE AS DESCR I BED AS FOLLOWS :
C
C
C
C
C
C
C
C
C
C
C
C
C
DWORD 1
OWORD-2
OWORO-3
OWORD-4
OWORD-5
OWORO-6
DWORO=7
V IDEO PARAMETER TABLE PO INTER
OYNAM I C SAVE AREA PO INTER
ALPHA MODE AUXILIARY CHAR GEN POINTER
GRAPHICS MODE AUXILIARY CHAR GEN POINTER
RESERVED
RESERVED
RESERVED
DWORD_'
PARAMETER TABLE PO INTER
INITIALIZED TO BIOS EGA PARAMETER TABLE.
TH I S VALUE MUST EX I ST.
C
C
C
C
C
C
C
C
C
C
PARAMETER SAVE AREA PO INTER
INITIALIZED TO 0000:0000, THIS VALUE IS OPTIONAL.
WHEN NON-ZERO, THIS POINTER WILL BE USED AS POINTER
TO A RAM AREA WHERE CERTAIN DYNAMIC VALUES ARE TO
BE SAVED. WHEN IN EGA OPERATION THIS RAM AREA WILL
HOLD THE 16 EGA PALETTE REGISTER VALUES PLUS
THE OVERSCAN VALUE IN BYTES 0-160 RESPECTIVELY.
AT LEAST 256 BYTES MUST BE ALLOCATED FOR THIS AREA.
ALPHA MODE AUXILIARY POINTeR
INITIALIZED TO 0000:0000, THIS VALUE IS OPTIONAL.
WHEN NON-ZERO, THIS POINTER IS USED AS A POINTER
TO A TABLES DESCRIBED AS FOLLOWS:
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
BYTE
BYTE
WORD
WORD
DWORD
BYTE
BYTE
C
C
C
C
C
C
C
C
C
C
C
C
C
C
BYTES/CHARACTER
BLOCK TO LOAD, SHOULD BE ZERO FOR NORMAL
OPERATION
COUNT TO STORE, SHOULD BE 2560 FOR NORMAL
OPERATION
CHARACTER OFFSET, SHOULD BE ZERO FOR NORMAL
OPERATION
PO I NTER TO A FONT TABLE
DISPLAYABLE ROWS
IF 'FF' THE MAXIMUM CALCULATED VALUE WILL BE
USED, ELSE TH I S VALUE WILL BE USED
CONSECUTIVE BYTES OF MODE VALUES FOR WHICH
THIS FONT DESCRIPTION IS TO BE USED.
THE END OF THIS STREAM IS INDICATED BY A
BYTE CODE OF 'Ff'
NOTE: USE OF THIS POINTER MAY CAUSE UNEXPECTED
CURSOR TYPE OPERATION. FOR AN EXPLANATION
OF CURSOR TYPE SEE AH '" 01 I N THE INTERFACE
SECT I ON.
GRAPHICS MODE AUXILIARY POINTER
INITIALIZED TO 0000:0000, THIS VALUE IS OPTIONAL.
WHEN NON-ZERO, THIS POINTER IS USED AS A POINTER
TO A TABLES DESCRIBED AS FOLLOWS:
C
BYTE
WORO
DWORD
BYTE
C
C
C
C
C
C
C
DISPLAYABLE ROWS
BYTES PER CHARACTER
PO I NTER TO A FONT TABLE
CONSECUT I VE BYTES OF MODE VALUES FOR WH I CH
THIS FONT DESCRIPTION IS TO BE USED.
THE END OF THIS STREAM IS INDICATED BY A
BYTE CODE OF 'FF'
C
DWORD_5 THRU DWORD_7
RESERVED AND SET TO 0000:0000.
C
C
C
C
C
C
501
ORG
RESET FLAG
ORG
ROWS
DB
POI NTS OW
C
C
C
C
491
492
493
494
495
496
497
498
499
500
OW
OB
OB
C
479
490
AoDR_6845
CRT_MODE_SET
CRTJALETTE
C
480
481
482
483
484
485
486
487
488
489
502
August 2, 1984
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
0500H
ORG
STATUS BYTE
ABSO - ENDS
OB
PORT B
TIMER
EQU
EQU
C
C
8255 PORT B ADDR
61"
40"
; ----- EQUATES FOR CARD PORT ADDRESSES
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
SEQ ADDR
SEcLDATA
CRTC ADDR
CRTC::::ADDR_B
CRTC_DATA
GRAPH_'_POS
GRAPH_2_POS
GRAPH_ADDR
GRAPH DATA
MI SC OUT PUT
I N_STAT_O
I NPUT STATUS B
I NPU(=STATUSATTR READ
ATTR=WRITE
EQU
EQU
EQU
[QU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
OC4H
OCSH
OD4H
OB4H
OD5H
OCCH
OCAH
OCEH
OCFH
OC2H
OC2H
OBAH
ODAH
ODAH
OCOH
OR OB5H
;----- EQUATES FOR ADDRESS REGISTER VALUES
IBM Enhanced Graphics Adapter 107
0000
0001
0002
0003
0004
505
506
507
508
509
510
511
512
513
514
515
516
'" 0000
'" 0001
'" 0002
=: 0003
=: 0004
= 0005
= 0006
= 0007
'" 0008
=: 0009
= OOOA
= 0008
=: OOOC
= 0000
::: OOOE
= OOOF
'" 0010
::: 0010
= 0011
= 0011
= 0012
= 0013
=: 0014
=: 0015
=: 0016
= 0017
= 0018
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
= 0000
= 0001
= 0002
=: 0003
=: 0004
=: 0005
'" 0006
= 0007
= 0008
= 0010
0011
= 0012
0013
=:
=:
0000
561
0000
0000
0001
0002
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
55
AA
20
577
0003
0003
0005
0009
0026
E8
32
36
36
4F
48
20
39
28
34
32
20
50
54
31
2F
34
30
37
28
59
20
39
31
30
37
43
52
49
38
33
33
29
49
42
34
2F
35
43
47
40
38
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
0020
0020
002F
0031
0032
0034
0035
0037
0039
86
82
EC
B2
EC
82
80
EE
003A
003C
28 02
8E OA
03
OA
SA
CO
00
618
619
620
621
622
623
624
625
626
627
628
629
630
S_RESET
S_CLOCK
S_MAP
S_CGEN
S_MEM
EQU
EQU
EQU
EQU
EQO
00"
01"
02"
03"
04"
C_HRZ_TOT
C_HRZ_DSP
C_STRT_HRZ_BLK
C_END_HRZ_BLK
C_STRT_HRZ_SYN
C_END_HRZ_SYN
C_VRT_TOT
C_OVERFLOW
C_PRE_ROW
C_MAX_SCAN_lN
C_CRSR_START
C_CRSR_END
C_STRT_HGH
C_STRT_LOW
C_CRSR_LOC_HGH
C_CRSR_LOC_LOW
C_VRT_SYN_STRT
C_LGHT_PEN_HGH
C_YRT_SYN_END
C_lGHT_PEN_LOW
C_VRT_DSP_END
C_OffSET
C_UNDERUCLOC
C_STRT_VRT_BLK
C_END_VRT_BLK
C_MODE_CNTL
C_LN_COMP
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQO
EQU
EQU
EQU
EQU
EQU
EOU
EOU
EOU
EQU
EQU
EOU
EOU
EOU
EOU
EQU
EOU
EOU
EOU
00"
01"
02"
03"
04"
05"
06"
07"
08"
09"
OA"
08"
OC"
00"
G_SET_RESET
G_ENBL_SET
G_CLR_COMP
G DATA ROT
G-REAO-MAP
G=MOOC
G_MI SC
G_COLOR
G_BIT_MASK
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
00"
01"
02"
03"
04"
05"
06"
07"
06H
P_MODE
P_OVERSC
P CPLANE
P=HPEL
EOU
EOU
EOU
EOU
12"
13H
OE"
OF"
10"
10"
""
12"
""
13"
;
;
;
;
WRITE ONLY
READ ONLY
WRITE ONLY
READ ONLY
;
;
;
SIGNATURE
BYTES
LENGTH INDICATOR
14H
15"
16"
17"
18"
10H
""
SUBTTL
; ----- CODE SEGMENT
CODE
c
c
c
c
c
c
c
;
-----
c
c
c
c
c
c
c
c
c
c
c
c
c
ASSUME
ORC
OH
08
08
06
055H
OAAH
020H
CS: CODE, DS;ABSO
PLANAR VIDEO SWITCH SETTINGS
o 0 - UNUSED
01-4QX25COlOR
10-8QX25COLOR
1 1 - 80 X 25 MONOCHROME
NOTE : 0 0 MUST BE SET WHEN TH I S ADAPTER I S INSTALLED.
c
c
V IDEO ADAPTER SW ITCH SETT I NGS
o
a
c
c
0 0 0
Q 0 1
0010
0 1 1
o 1 0 0
o 1 0 1
c
c
c
c
c
c
c
c
c
c
c
c
-
MONOC
MONOC
MONOC
MONOC
COLOR
COLOR
PRIMARY, EGA COLOR, 40X25
PRIMARY, EGA COLOR, 80X25
PRIMARY, EGA HI RES EMULATE (SAME AS 0001)
PR I MARY, EGA H I RES ENHANCED
40 PRIMARY, EGA MONOCHROME
80 PRIMARY, EGA MONOCHROME
1
1
1
1
1 1 0 1 1 1 0
0 0
1 0 1 0 0 1 1 -
MONOC
MONOC
MoNOC
MONOC
COLOR
COLOR
SECONDARY, EGA COLOR, 40X25
SECONDARY, EGA COLOR, 80X25
SECONDARY, EGA HI RES EMULATE (SAME AS 0111)
SECONDARY, EGA H I RES ENHANCED
40 SECONDARY, EGA MONOCHROME
80 SECONDARY, EGA MONOCHROME
1
1
1
,
1
1
1
1
RESERVED
RESERVED
RESERVED
RESERVED
o
o
o
c
c
c
c
c
c
c
c
c
c
c
POST
;----- NOTE; 00 NOT USE THE SIGNATURE BYTES AS A PRESENCE TEST
c
c
SEGMENT PUBL! C
INCLUDE
VPOST. INC
SUBTTL VPOST. INC
PAGE
a
a
0
0
1
1
0
1
0
1
-
; ----- SETUP ROUT I NE fOR TH I S MODULE
VIDEO SETUP
JMP
c
c
08
OB
PROC
FAR
SHORT
Ll
'2400'
'6277356 (C)COPYRtGHT IBM 1984'
08
'9/13/84'
c
c
c
c
c
c
c
C
C
C
C
C
C
C
C
C
C
C
c+
c+
;----- SET UP VIDEO VECTORS
L1:
MOV
MOV
IN
MOV
MOV
MOV
OUT
DH,3
DL, INPUT_STATUS
AL,DX
OL, I NPUT_STATUS_B
AL,DX
DL,ATTR_WRITE
AL,O
DX,AL
SRLOAO
SUB
MOV
DS,O
OX, OX
OS, OX
IN
108 IBM Enhanced Graphics Adapter
August 2, 1984
003E
003f
0045
0049
004f
0055
005B
005f
0065
0069
006F
0073
FA
C7
8C
C7
C7
C7
8C
C7
8C
C7
8C
F.
06
DE
06
06
06
DE
06
DE
06
OE
0074
0079
007C
0080
0083
0087
008B
008E
0091
0091
0092
C6
E8
88
E8
08
8A
E8
E9
06 0487
009B R
lE 0488
OOCE R
06 0488
lE 0488
00F3 R
0244 R
0092
0092
0093
0094
0095
0096
0098
009A
009B
0040
0042
0108
OlOA
04A8
04AA
007C
007E
010C
010E
R
R
R
R
R
R
R
R
R
R
OC07 R
f065
fOOD
010C R
0000 E
0000 E
R 04
R
R
R
e6
EE
50
56
EC
24 10
DO E8
C'
009B
009B
0090
009F
OOAl
B6 03
B2 C2
BO 01
00A2
00A4
00A7
DOA9
OOAB
DOAD
BO
E8
00
DO
DO
8A
00
0092 R
E8
E8
E8
06
OOAF
OOBl
00B4
00B6
00B8
BO
E8
DO
DO
OA
09
0092 R
E6
E8
06
OOBA
OOBC
OOBf
OOCl
BO
E6
00
OA
05
0092 R
E8
08
00C3
00C5
00C8
BO 01
E8 0092 R
OA 08
DOCA
OOCO
OOCE
80 E3 OF
C'
OOCE
OOCE
0000
0002
0004
0005
0007
0008
DaDA
00 DB
0000
OOoF
OOEl
00E3
00E5
OOE6
00E8
00E9
OOEB
OOEC
OOEE
OOFO
00f2
OOf3
EE
B6 03
B2 SA
60 01
EE
B2 OA
EE
62
EC
24
DO
8A
B2
BO
C2
60
E8
08
BA
02
EE
82
EE
B2
EC
24
DO
OA
C'
DA
C2
60
EO
C3
00F3
OOFS
OOF5
00F8
Oaf A
OOfB
OOFD
DOFF
0100
0103
0105
0107
2A ff
80 E3 Of
D1 E3
52
B6 03
8A E6
5A
BO E4 01
FE c4
F6 04
2E: FF A7 0128 R
010C
010C
alOE
0110
0112
0114
0116
0118
0717 R
COOO
0000
0000
0000
0000
0000
August 2, 1984
631
6'2
633
6'4
635
6'6
6'7
6'.
6'9
640
641
642
64,
644
645
646
647
646
649
650
651
652
653
654
655
656
657
656
659
660
661
662
66'
664
665
666
667
666
669
670
671
672
673
674
675
676
677
676
679
660
661
662
66'
664
665
666
667
666
669
690
691
692
693
694
695
696
697
696
699
700
701
702
70,
704
705
706
707
706
709
710
711
712
713
714
715
716
717
716
719
720
721
722
72'
724
725
726
727
726
729
7'0
731
732
733
734
735
7'6
737
7'8
739
740
741
742
743
744
745
746
747
746
749
750
751
752
753
754
755
756
e
e
e
C
C
e
e
e
e
e
C
C
C
C
C
eLI
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
STI
c
e
e
e
e
C
C
C
C
C
C
e
C
C
C
C
C
e
C
e
c
e
e
e
e
C
e
e
e
e
e
e
e
e
e
e
e
C
C
C
C
C
e
C
e
e
e
e
C
C
C
e
C
C
C
C
e
e
e
e
C
C
C
C
C
C
C
C
C
C
MOV
CAll
MOV
CAll
OR
MOV
CAll
JMP
SKI P:
RET
VIDEO_SETUP
POR_l
VIDEO, OffSET COMBO_VIDEO
VIDEO+2, CS
PLANAR_V IDEO, Of065H
PLANAR_V I DEO+2, OfOOOH
SAVE_PTR,OffSET SAVE_TBl
SAVE_PTR+2, CS
EXT_PTR, OFfSET INT_1F_l
EXT_PTR+2, CS
GRX_SET, OFFSET CGODOT
GRX_SET+2, CS
POR_l
INFO, 000001 OOB
RD_SWS
INFO_3,Bl
F_BTS
I NfO_3,Al
Bl,INfO_3
MK_ENV
POST
ENDP
PROC
OUT
PUSH
POP
IN
AND
SHR
RET
ENDP
NEAR
DX,Al
AX
AX
Al,DX
Al, 01 OH
Al,l
; ----- READ THE SW ITCH SETT I NGS ON THE CARD
RO_SWS
PROC
ASSUME
MDV
MOV
MOV
OUT
NEAR
DS:ABSO
OH,3
Dl,MISC_OUTPUT
Al,'
DX,Al
;----- COULD BE O,4,8,C
RD_SWS
MDV
CAll
SHR
SHR
SHR
MDV
Al,ODH
POR_l
Al,l
Al,'
Al,'
Bl,Al
MDV
CAll
SHR
SHR
DR
Al,9
POR_l
Al,l
Al,l
Bl,Al
MOV
CAll
SHR
OR
Al,5
POR_'
Al,l
6l,Al
MOV
CAll
OR
Al,l
POR_l
Bl,AL
AND
RET
ENOP
Bl,OFH
;----- OBTAIN THE FEATURE BITS FROM DAUGHTER CARD
F_BTS
c
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
PTR
PTR
PTR
PTR
PTR
PTR
PTR
PTR
PTR
PTR
;----- POST FOR COMBO VIDEO CARD
c
C
C
C
e
e
e
e
e
e
C
e
e
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
F_BTS
PROC
MOV
MOV
MOV
OUT
MOV
OUT
MOV
IN
AND
SHR
MOV
MOV
MOV
OUT
MOV
OUT
MOV
IN
AND
SHL
OR
RET
ENDP
NEAR
DH,3
Dl,DBAH
Al,l
DX,Al
Dl,OoAH
DX,AL
Dl, I N_STAT_O
Al,DX
Al,060H
Al,l
Bl,Al
Ol,OBAH
Al,2
OX,Al
Dl,ODAH
OX,Al
Dl, IN_STAT_a
Al,DX
Al,060H
Al,l
Al,8l
;----- ESTABLISH THE VIDEO ENVIRONMENT,
MK_ENV
PROC
ASSUME
SU6
AND
SAL
PUSH
MOV
MOV
POP
AND
INC
NOT
JMP
SAVE_TBl
ow
OW
OW
ow
ow
ow
ow
READ FEATURE BITS
; READ FEATURE BITS
KEYED OFF Of THE SWITCHES
NEAR
DS:A8S0
BH,BH
Bl,OFH
BX,l
OX
OH,3
AH,DH
OX
AH,l
AH
AH
WORD PTR CS: I 8X + OffSET T5]
lABEL
OffSET
OCOOOH
0
0
0
0
0
DWORD
VIDEO_PARMS
PARMS
PARMS
PAL SAVE AREA
PAL SAVE AREA
, ALPHA TABLES
; ALPHA TABLES
; GRAPH I CS TABLES
IBM Enhanced Graphics Adapter 109
OllA
0000
011C
011E
0120
0122
0124
0126
0000
0000
0000
0000
0000
0000
0128
0128
012A
012C
012E
0130
0132
0134
0136
0171
017E
017E
0189
0194
01A8
OlBC
01C7
R
R
R
R
R
R
R
R
0138
013A
013C
013E
0140
0142
0144
0146
01C7
0102
0100
01 f1
0204
0204
0204
0204
R
R
R
R
R
R
R
R
0148
0148
0140
0152
0155
0157
0158
80
80
B8
CD
C3
26 0410 R CF
OE 0410 R 10
0001
10
0158
0158
0150
0162
0165
0167
0168
80
80
B8
CD
C3
26 0410 R cr
DE 0410 R 20
0003
10
0168
0168
0160
0170
0172
0173
80 DE 0410 R 30
B8 0007
CO 10
C3
0173
0173
0177
017A
0170
017E
017E
017E
0182
0185
0188
0189
0189
0180
0190
0193
0194
0194
0196
0198
019A
019B
0190
01Al
01A4
01A7
01A8
01A8
01AA
01AC
01AE
OlAF
OlBl
0185
01B8
0188
01BC
01SC
OlCO
01C1
01C6
01C7
01C7
01C7
01CB
01CE
0101
0102
0102
0106
0109
010C
0100
0100
010F
01E1
01E3
01E4
01 E6
OlEA
OlEO
OHO
01 f1
OlFl
OlF3
OH5
01f7
OH8
OHA
OlFE
0201
0204
0204
0205
20 26 0487 R
E8 0148 R
E8 0168 R
C3
20 26 0487 R
E8 0158 R
E8 0168 R
C3
20 26 0487 R
f8 0158 R
E8 0168 R
C3
86 03
B2 C2
SO 00
EE
f6
08
E8
E8
C3
04
26 0487 R
0168 R
0148 R
86 01
82 C2
BO 00
EE
F6
08
£8
£8
C3
04
26 0487 R
0168 R
0158 R
20 26 0487 R
£8 0168 R
£8 0148 R
C3
20 26 0487 R
f8 0168 R
£8 0158 R
C3
20 26 0487 R
£8 0168 R
E8 0158 R
c3
B6 01
B2 C2
BO 00
EE
F6
08
E8
£8
C3
04
26 0487 R
0148 R
0168 R
B6 03
B2 C2
80 00
EE
F6
08
E8
£8
C3
04
26 0487 R
0158 R
0168 R
151
158
159
160
161
162
163
164
165
166
161
168
169
110
111
112
113
114
115
116
111
118
119
180
181
162
183
184
185
166
161
188
169
190
191
192
193
194
195
196
191
196
799
600
601
802
603
604
605
606
601
606
609
610
611
612
613
614
615
616
617
616
619
620
621
622
823
824
825
826
627
628
629
830
831
632
833
834
835
836
837
838
839
840
641
842
843
644
645
846
847
848
849
850
851
852
853
854
855
856
851
858
859
860
661
862
863
864
665
866
867
666
869
870
871
872
873
814
815
876
811
878
819
880
881
882
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
DW
T5
c
LABEL
DW
DW
DW
DW
DW
DW
WORD
OffSET
OFFSET
OFfSET
OFFSET
OW
OW
OfFSET PST_6
OfFSET PST_7
OW
OFfSET
OffSET
OffSET
OffSET
OfFSET
OfFSET
OFFSET
OffSET
DW
DW
DW
DW
DW
DW
DW
ENV_X
ENV_X
ENV_O
[NV_O
ENV_1
ENV_3
PST_O
PST_l
PST_2
PSC1
gn~H ~~i=~
PST 8
PST-9
PST-A
PST-B
PST=OUT
PST OUT
PST-OUT
PST=OUT
;
SET 40X25 COLOR ALPHA
PROC
AND
OR
MOV
INT
RET
ENOP
NEAR
EQU I P_LOW, OCfH
EQUIP_LOW,010H
AX,lH
10M
PROC
AND
OR
MOV
INT
RET
ENDP
NEAR
EQUIP_LOW,OCfH
EQU I P_LOW,020H
AX,OlH
10M
SET 80X25 COLOR ALPHA
PROC
OR
MOV
INT
RET
ENOP
NEAR
EQUIP_LOW,030H
AX,07H
10M
SET MONOCHROME ALPHA
AND
CALL
CALL
RET
INFO,AH
ENV X
ENV=l
AND
CALL
CALL
RET
INFO,AH
ENV_O
ENV_1
AND
CALL
CALL
RET
INFO,AH
ENV_O
fNV_1
MOV
MOV
MOV
OUT
NOT
OR
CALL
CALL
RET
OH,3
oL,M1SC_OUTPUT
AL,O
DX,AL
AM
I NFO,AH
ENV_3
ENV_X
MOV
MOV
MOV
OUT
NOT
OR
CALL
CALL
RET
OH,3
Ol,MISC_OUTPUT
AL,O
OX,Al
AM
I NFO,AH
ENV_3
ENV_O
AND
CALL
CAll
RET
INFO,AH
ENV 3
ENV=X
AND
CALL
CALL
RET
INFO,AH
ENV_3
ENV_O
AND
CALL
CALL
RET
INFO,AH
ENV_3
ENV_O
MOV
MOV
MOV
OUT
NOT
OR
CALL
CALL
RET
OH,3
OL, M I SC_OUTPUT
AL,O
OX,AL
AM
I NFO,AH
ENV_X
ENV_1
MOV
MOV
MOV
OUT
NOT
OR
CALL
CALL
OH,3
OL, MI SC_OUTPUT
AL,O
OX,AL
AM
INfO,AH
ENV_O
ENV_1
PST_O:
PST_1:
PST_2:
PST_3:
PST_4:
PST_5:
c
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
GRAPH I CS TABLES
DW
DW
DW
DW
DW
DW
PST_6:
PST_7:
PST_8:
PST_9:
PST_A:
PST_B:
PST_OUT:
MK_ENV
RET
ENoP
110 IBM Enhanced Graphics Adapter
August 2, 1984
0205
0205
0206
0209
020B
020C
020F
0211
0212
0213
0216
0217
0218
021B
0210
021 E
0220
0223
0223
0225
0226
0227
0227
022A
0228
022C
022C
022C
0220
022F
0231
0232
0233
0234
0235
0236
53
B8
88
50
£8
88
58
50
£8
58
50
£8
38
58
75
EB
007F
FB
022C R
FO
0236 R
022C R
C7
03
05 90
33 CO
56
C3
B8 0001
56
C3
52
88 00
80 DE
H
42
EC
5A
C3
0236
0236
0237
0238
023A
023C
023E
0241
0242
0243
0244
50
52
86
B4
BO
E8
947
DO
OE
7F
0015 R
5A
5B
C3
0244
0244
0247
024C
024E
0251
0254
0257
0259
025C
02SC
025E
0260
0260
0263
0266
0269
026B
026E
026E
0270
0270
0271
0274
0277
027A
027C
027F
0281
0283
0285
0287
0289
0289
[8
F6
75
B8
E8
30
74
E9
DC FE R
06 0487 R 02
12
03B4
0205 R
0001
03
0317 R
028A
8B 2E 0472 R
028E
0292
81 FD 1234
BE C3
B4 30
EB 10
88
E8
3D
74
E9
88'
8.,
885
88.
887
888
889
890
891
892
89'
89'
895
89.
897
898
899
900
901
902
90'
90,
905
90.
907
908
909
910
911
912
913
914
915
91.
917
918
919
920
921
922
923
924
925
92.
927
928
929
930
931
932
933
934
9'5
93.
937
938
939
940
941
942
94'
944
945
94.
0304
0205 R
0001
03
0317 R
84 20
50
8S BODO
8A 0368
89 1000
BO 01
60 FC 30
74 08
87 B8
82 08
85 40
FE C8
EE
August 2, 1984
948
949
950
951
952
953
954
955
95.
957
958
959
9.0
9.'
9.2
963
9.4
9.5
9 ••
9.7
9.8
9.9
970
971
972
973
974
975
97.
977
978
979
980
981
982
98'
984
985
98.
987
988
989
990
991
992
99'
994
995
99.
997
99.
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
C
C
C
C
C
C
C
C
C
C
; ~T~is-ROUT i NE-jESTS -T~E-cRT-cARD-iNTERNAL-DATA -suS-AND -iN -A-LiMiTED ---; WAY TESTS THE eRTC VIDEO CHIP BY WRITiNG/READING FROM CURSOR REGISTER
; CARRY I S SET I F AN ERROR I S FOUND
;
;
REGISTERS BX,SI,ES,OS ARE PRESERVED,
REG I STERS AX, CX, OX ARE MODI FYED,
bD:pRESENcE:'fs'f-pRoc----NEAR--------------------------------------------
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
G
G
G
BX
BX,07FH
DI,BX
AX
RO_CURSOR
51 ,AX
AX
AX
WR_CURSOR
AX
AX
g~~L
~~;gyRSOR
POP
JNZ
JMP
NOT_PRESENT:
XOR
POP
SAVE BX
INITIAL WORD PATTERN BYTE
SAVE PORT ADDRESS
SAVE OR I G I NAL VALUE
RECOVER PORT ADDRESS
SAVE PORT ADDRESS
WR I TE CURSOR
RECOVER PORT ADDRESS
SAVE PORT ADDRESS
READ IT BACK
SAME?
AX
NOT_PRESENT
TST_EX
EXIT
AX,AX
SET NOT PRESENT
IF NOT EQUAL
BX
RET
C
C
C
C
C
C
PUSH
MOV
MOV
PUSH
CALL
MOV
POP
PUSH
CALL
POP
PUSH
AX,l
MOV
POP
SET PRESENT ON EXIT
RESTORE BX
8X
RET
CD_PRESENCE_ TST ENOP
; -MODULE- NAME--RO:CURSOR------ --------- -------- ------- -- --- ------ -------READ CURSOR POSITION [ADDRESS]
(FROM CRTC) TO
AX
C
G
: REGISTER AX IS MODIFIED.
G
~O-CURSOR---
C
-
G
G
G
G
C
G
G
G
C
C
C
C
C
C
C
C
C
C
G
C
C
C
OX
DX,AX
AL, C_CRSR_LOC_HGH
DX,AL
OX
AL,OX
; SAVE REGS USED
RETURN WITH CURSOR POS I N AX
RESTORE REGS USED
G
G
C
C
C
----;ROC-NEAR -- ---------- -------- ---- ------------------ ------
PUSH
MOV
MOV
OUT
ING
IN
POP
RET
RO_CURSOR
ENDP
; -MODULE-N~M~--~~=~U~SO~ ------ -- ------- ------- ----- -------- -------------WR I TE CURSOR pas I T I ON [ADDRESS] (TO CRTC) 101 I TH CONTENTS OF AX
;
ALL REGISTERS PRESERVED
~R=~U~S~R-------PR~C-NEAR-----------------------------------------------
SAVE REGS USED
PUSH
PUSH
MOV
MOV
MOV
CALL
AX
OX
DX,AX
AH, C CRSR LaC HGH
AL,07FH OUT_OX
CURSOR LOCATION HIGH
TEST VALUE
G
C
C
C
C
C
POP
POP
G
POST:
;
G
C
C
OX
AX
RET
WR_CURSOR
C
C
C
C
C
C
C
C
ENOP
-------------------------------------------------------INITIALIZE AND START CRT CONTROLLER (6845)
ON COLOR GRAPH I CS AND MONOCHROME CARDS
TEST V IDEO READ/WR I TE STORAGE.
OEseR I PT I ON
RESET THE V IDEO ENABLE SI GNAl.
SELECT ALPHANUMERIC MODE, 40
25, 8 & W.
READ/WRITE DATA PATTERNS TO STG. GHECK STG
ADDRESSABILJTY.
*
. --------------------- - ---------------------------------ASSUME
CALL
TEST
JNZ
MOV
CALL
CMP
JE
JMP
C
C
C
C
C
C
C
C
OS: ABSO, ES: ABSO
DOS
INFO,2
COLOR_PRESENCE_ TST
AX,03B4H
CO PRESENCE TST
AX;1
CONT1
P0014
C
CONTt:
C
C
MOV
AH,30H
JMP
SHORT
OVER
COLOR_PRESENCE_TST:
MOV
AX,03D4H
CALL
CD_PRESENCE_ TST
CMP
AX, 1
JE
CONT2
JMP
POD14
CONT2 :
MOV
AH,20H
OVER:
PUSH
AX
MOV
BX, OBOOOH
MOV
OX,3B8H
MOV
CX,4096
MOV
AL,l
CMP
AH,30H
JE
E9
MOV
BH,OB8H
MOV
DL,OD8H
MOV
CH,40H
DEC
AL
E9:
OUT
DX,AL
C
C
C
C
C
C
C
C
C
C
C
C
G
C
C
C
C
C
C
C
C
C
C
C
C
C
G
INDEX
RETURN WITH CURSOR pas I N AX
RESTORE REGS USED
;
MONOCHROME CARD INSTALLED
COLOR GRAPH I CS CARD INSTALLED
RESAVE VALUE
BEG V I OEO RAM ADDR B/W CO
MODE CONTROL B/W
RAM BYTE CNT FOR B/W CO
SET MODE FOR Bioi CARD
B/W VIDEO CARD ATTACHED?
YES - GO TEST V I DEO STG
BEG VIDEO RAM AODR COLOR CD
MODE CONTROL COLOR
RAM BYTE CNT FOR COLOR CO
SET MODE TO 0 FOR COLOR CO
TEST_V I DEO_STG:
o I SABLE V IDEO FOR COLOR CD
MOV
BP, OS: RESET_FLAG
POD INITIALIZED BY KBD RESET
CMP
MOV
BP,1234H
ES,BX
POD INITIATED BY KBD RESET?
POINT ES TO VIDEO RAM STC
IBM Enhanced Graphics Adapter 111
0294
0296
BE DB
029B
029B
74 07
E8 020f R
75 2E
1009
1010
lOll
0290
0290
029E
029f
02A2
02A4
02A7
02A9
02AA
02A8
02AE
0281
02B3
0285
0285
0287
02B7
02B9
02B9
02BA
02BC
02BE
02CO
02C2
02C2
02Cl,
02C4
02C5
02C7
02C9
02CS
02CB
02CE
0201
0203
0203
0205
0207
0209
0209
02DA
020C
020C
02DF
02DF
02EO
02E2
02E5
02E8
02EA
02EC
02EC
02EO
02E£
02££
02fO
02F2
02F2
02F3
02F5
02F7
02F9
02FA
02fC
02FE
0300
0302
0304
0306
0308
030A
030C
030C
0300
030E
0310
0311
58
50
B8 7020
2B FF
B9 0028
f3/ AB
58
50
80
BA
74
B2
FC 30
03BA
02
DA
B4 08
2B C9
EC
22
75
E2
EB
C4
04
F9
09
2B C9
EC
22 C4
74 OA
E2 F9
SA 0102
E8 06C8 R
EB 06
Bl 03
02 EC
75 DE
58
E8 3B
B9 4000
FC
88 09
B8 AAAA
BA FF55
2B FF
F3/ AA
4F
FD
BB F7
88 CB
AC
32 C4
75 1E
8A C2
AA
£2 f6
22
74
8A
86
22
75
8A
EB
E4
13
EO
F2
£4
04
04
EO
FC
47
74 DE
4F
E809
0313
0313
0315
0315
0316
0317
80 00
FC
C3
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
105B
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1"0
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
1129
POP
PUSH
MOV
SUB
MOV
REP
1133
C
1134
C
GET VIDEO SENSE SWS (AH)
SAVE IT
WRT BLANKS IN REVERSE VIDEO
SETUP STARTING LOC
NO. OF BLANKS TO DISPLAY
WR I TE V IDEO STORAGE
AX
AX
AX,7020H
01,01
CX.40
STOSW
; -------CRT-~NTERFACE-LiNES -TEST-------------------- ----;
;
;
;
OESCRI PTION
SENSE ON/OFF TRANSITION OF THE VIDEO ENABLE
AND HORIZONTAL SYNC LINES.
------------------------------------------------------GET VIDEO SENSE
POP
AX
PUSH
CMP
MOV
JE
MOV
AX
MOV
AH,8
SUB
CX,CX
IN
ANO
JNZ
LOOP
JMP
AL,OX
AL,AH
SW INFO
SAVE IT
B/W CARD ATTACHED?
SETUP ADOR OF BW STATUS PORT
YES - GO TEST LJ /liES
COLOR CARD I S ATTACHED
AH,30H
OX,03BAH
E11
DL,ODAH
LlNE~TST:
Ell:
;
E12:
OFLOOP~CNT:
£13:
Et.
E13
SHORT E17
READ CRT STATUS PORT
CHECK V I OEO/HORZ LI NE
ITS ON - CHECK I F IT GOES OFF
LOOP TILL ON OR TIMEOUT
GO PR I NT ERROR MSG
E14:
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
• GO TEST V IDEO R/W STG
; R/W STG FA I LURE - BEEP SPK
~~O~-------------------------------------------------------------
C
C
; YES - SKIP VIDEO RAM TEST
; POINT OS TO VIDEO RAM STG
DESCRIPTION
ENABLE VIDEO SIGNAL AND SET MODE.
DISPLAY A HORIZONTAL BAR ON SCREEN.
C
1126
1127
1130
1131
1132
;
;
C
C
C
El0
OS, BX
OS: NOTH lNG, ES: NOTH I NG
STGTST_CNT
E17
~-------SETU;-;7~EO-OATA-ON-SCREEN-FOR-;7~EO-L7NE-TEST~----------
C
C
C
1125
1128
JE
MOV
ASSUME
CALL
JNE
C
C
C
SUB
CX,CX
IN
ANO
JZ
LOOP
AL,DX
AL,AH
MOV
CALL
JMP
OX,102H
ERR BEEP
SHORT E18
MOV
SHR
JHZ
CL,3
£15:
READ CRT STATUS PORT
CHECK VIDEO/HORZ LI NE
I TS ON - CHECK NEXT LI NE
LOOP If OFF TILL IT GOES ON
CRT_ERR
E1.
Et5
E17:
AH,CL
GO CHECK HORIZONTAL LINE
o I SPLAY_CURSOR:
GET VIDEO SENSE SWS (AH)
E12
£18:
POP
JMP
;
; GO BEEP SPEAKER
NXT_LINE
GET NEXT BIT TO CHECK
E16:
AX
SHORT
P0014
----------------------------------------------------------------------THIS SUBROUTINE PERFORMS A READ/WRITE STORAGE TEST ON
A 16K BLOCK OF STORAGE.
ENTRY REQU I REMENTS:
ES == ADDRESS OF STORAGE SEGMENT BE I NG TESTED
OS == ADDRESS OF STORAGE SEGMENT BE I NG TESTED
WHEN ENTERING AT STGTST_CNT. CX MUST BE LOADED WITH
THE BYTE COUNT.
EXIT PARAMETERS:
ZERO FLAG = 0 I F STORAGE ERROR (DATA COMPARE OR PAR I TY CHECK.
AL == 0 DENOTES A PARITY CHECK. ELSE AL::XOR'ED BIT
PATTERN OF THE EXPECTED DATA PATTERN VS THE
ACTUAL DATA READ.
AX.BX.CX.DX,DI, AND SI ARE ALL DESTROYED.
~TGTST--PROC----NEAR-----------------------------------------------------
MOV
STGTST_CNT:
CLD
MOV
MOV
MOV
SUB
REP
CX,4000H
BX,CX
AX,OAAAAH
DX,OfF55H
01,01
STOSB
C3:
OEC
01
STO
SETUP CNT TO TEST A 16K BLK
SET DIR fLAG TO INCREMENT
SAVE CNT (4K fOR VIDEO OR 16K)
GET DATA PATTERN TO WRITE
SETUP OTHER DATA PATTERNS TO USE
01 = OFfSET 0 RELATIVE TO ES REG
WR I TE STORAGE LOCAT IONS
STGOl
PO I NT TO LAST BYTE JUST WR I TTEN
SET DIR FLAG TO GO BACKWARDS
C4:
MOV
MOV
SI,OI
CX,8X
C5:
LODS8
XOR
JNE
MOV
STOSB
LOOP
ANO
JZ
MOV
XCHG
AND
JHZ
MOV
JMP
AL,AH
C7
AL,OL
C5
AH,AH
C.X
AH,AL
DH,DL
AH,AH
C.
DL,AH
C3
SETUP BYTE CNT
I NNER TEST LOOP
READ OLD TEST BYTE [SI]+
DATA READ AS EXPECTED ?
NO - GO TO ERROR ROUTI NE
GET NEXT DATA PATTERN TO WRITE
WRITE INTO LOCATION JUST READ
OECREMENT COUNT AND LOOP CX
ENDING 0 PATTERN WRITTEN TO STG?
YES - RETURN TO CALLER WITH AL=O
SETUP NEW VALUE fOR COMPARE
MOVE NEXT DATA PATTERN TO OL
READING ZERO PATTERN THIS PASS?
CONTI NUE TEST SEQUENCE TILL 0
ELSE SET 0 FOR END READ PATTERN
AND MAKE fiNAL BACKWARDS PASS
C6:
CLD
INC
JZ
DEC
JMP
01
C3
SET D I R FLAG TO GO FORWARO
SET POINTER TO BEG LOCATION
READ/WRlTE FORWARD IN STG
ADJ UST PO INTER
READ/WR I TE BACKWARD IN STG
AL,OOOH
AL==O DATA COMPARE OK
C,
01
C6X:
MOV
C7:
SET DIRECTION FLAG BACK TO INC
CLO
RET
STGTST
ENDP
EGA CRT ATTACHMENT TEST
1. INIT CRT TO 40><25 - 8W ****SET TO MOOE****
2. CHECK FOR VERTICAL AND VIDEO ENABLES, AND CHECK
TIMING OF SAME
3. CHECK VERTICAL INTERRUPT
4. CHECK RED, BLUE, GREEN, AND INTENSIFY DOTS
112 IBM Enhanced Graphics Adapter
August 2, 1984
= AOAC
= C460
= OOCS
= S099
= 6862
= 015E
= 015E
= 0043
= 0040
0317
0317
031A
031C
03H
83 EC OA
8B EC
ES OCfE R
BO 30
0321
0323
0325
0327
032C
032E
0331
0336
0336
0340
0342
0344
0346
0349
0346
0340
0340
0350
0353
0355
0357
0359
035B
035E
0363
0366
E6
BO
E6
f6
74
E8
C7
C7
c7
B2
B4
BO
E8
62
EB
43
00
40
06 0487 R 02
1f
016S R
46 02 015E
46 04 S099
46 06 6862
B4
01
27
0015 R
6A
2A
E8
E8
73
B2
B4
BO
E8
C7
EB
014S R
OE9A R
11
04
01
14
0015 R
46 02 015E
06 90
0366
036B
036B
0370
0375
C7 46 02 00C8
C7 46 04 AOAC
C7 46 06 C460
B2 OA
0377
0377
037A
037C
B8 0500
CO 10
2B C9
037E
037E
037F
0381
0383
0385
0387
EC
A8
75
E2
B3
E9
038A
038A
03SC
80 00
[6 40
038E
2B DB
0390
0392
0392
0393
0395
0397
0399
0398
EC
A8
74
E2
83
E9
039E
039E
03AO
03AO
03Al
03A3
03A5
03A7
03A9
03AB
03AD
03BO
03BO
03B2
03B5
03B5
03B7
08
07
f9
00
0448 R
33 C9
08
07
F9
01
0448 R
2B C9
EC
A8
74
A8
75
E2
83
E9
01
15
08
23
F5
02
0448 R
B3 03
E9 0448 R
B3 04
E9 0448 R
03BA
03BA
03BC
A8 08
75 F2
03BE
03BE
03BF
03Cl
03C3
EC
A8 01
E1 FB
E3 FO
August 2, 1984
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
"65
1166
1167
1168
1169
1170
1171
1172
1173
1174
'175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
"90
1191
1192
"93
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
: 5.
:
I NIT TO 40X25 - COLOR/MONO ****5ET TO MODE****
-- ------------------------------------------------------
;----- NOMINAL TIME 15 B286H FOR ·60 HZ.
;----- NOMINAL TIME IS A2fEH fOR 50 HZ.
350
350
MAX T I ME fOR VERT/VERT
(NOMINAL + 10%)
MIN TIME fOR VERT/VERT
(NOMINAL - 10%)
NUM Of ENA8LES PER FRAME
MAX T I ME FOR VERT/VERT
(NOMINAL + 10%)
MIN TIME FOR VERT/VERT
(NOMINAL - 10%)
ENHANCED ENABLES PER fRAME
NUM Of ENABLES PER fRAME
043H
040H
8253 T I MER CONTROL PORT
8253 T I MER/CNTER 0 PORT
MAX_VERT_COLOR
EQU
OAOACH
M I N_VERT_COLOR
EQU
OC460H
CENAB_PER_FRAME EQU
MAX_VERT _MONO
EQU
08D99H
M I N_VERT_MONO
OB862H
200
EQU
EENAB_PER_FRAME EQU
MENA8_PER_FRAME EQU
EQU
EQU
POD14
PROC
SUB
MOV
NEAR
SP,OAH
BP,SP
RESERVE 5 WORDS ON STACK
I NIT SCRATCH PAO POI NTER
ASSUME
CALL
MOV
DS:ABSO, ES:ABSO
ODS
AL, 0011 00008
SET T I MER 0 TO MODE 0
OUT
TIM CTL.AL
AL,OOH
TlMERO,AL
INFO,2
MOV
OUT
TEST
JZ
CALL
MOV
MOV
MOV
MOV
MOV
MOV
CALL
MOV
JMP
COLOR EGA V:
CALL
CALL
JNC
MOV
MOV
MOV
CALL
MOV
JMP
COLOR_V:
MOV
BRST COLOR V:
MOV
MOV
MOV
SEND fiRST BYTE TO T I MER
~~~~~_EGA_V
SET UP I N MONOCHROME
NUM.OF FRAMES fOR MONO
MAX T I ME fOR VERT/VERT
MIN T I ME FOR VERT/VERT
MONO CRTC REG
HORIZ. TOTAL DIPLAY
TO 40 COL
WORO PTRIBP][2],MENAB_PER_fRAME
WORD PTRIBP][4J,MAX_VERT_MONO
WORD PTR[BP][6J,MIN_VERT_MONO
DL, CRTC_AOOR_B
AH,C HRZ DSP
AL,27H OUT OX
DL, INPUT STATUS B
SHORT
COMMON-
'BA
ENV X
SEl UP IN 40X25 COLOR
BRST_DET
ENHANCED MODE
COLOR V
NO,40X25
BRST MODE ONLY!
OL, CRTC_ADOR
AH, ,
HRZ DSP END
AL,20
MOD I FY FOR TEST ONLY
OUT OX
WORO PTR[BPJ[2J,EENAB_PERJRAME ; NUM. OF FRAMES FOR COLOR
BRST_COLOR_V
WORD PTRI BP] [2 J. CENAB_PER_FRAME ; NUM. OF fRAMES fOR COLOR
WORD PTR[BP][4J,MAX_VERT_COLOR
WORD PTR[BPJ[6].MIN_VERT_COLOR
DL, INPUT_STATUS
MAX TIME FOR VERT/VERT
MIN T I ME FOR VERT /VERT
SET ADDRESSING TO VIDEO
ATTR STATUS
COMMON:
MOV
AX,0500H
10"
INT
;
SET TO VIDEO PAGE 0
CX,CX
SUB
;----- LOOK FOR VERTICAL
POD14_1 :
IN
TEST
JNE
LOOP
MDV
JMP
AL,OX
AL, 0000 10008
POD14_2
POD14 1
BL,OOPOD14_ERR
;----- GOT VERTICAL -
GET STATUS
VERT I CAL THERE YET?
CONTINUE IF IT IS
KEEP LOOK I NG TILL COUNT
EXHAUSTED
NO VERTI CAL
START TIMER
POD14_2:
MOV
Al,O
TIMERO,AL
OUT
SUB
; ----- WA I T FOR
XOR
POD14_25:
IN
TEST
JZ
LOOP
MOV
JMP
SEND 2ND BYTE TO TIMER TO
START IT
I NIT. ENABLE COUNTER
6X, BX
VERT I CAL TO GO AWAY
CX,CX
AL,oX
AL,00001000B
POD14_3
POD14_25
BL,OlH
POD14_ERR
GET STATUS
VERT I CAL ST 1LL THERE
CONTINUE If IT'S GONE
KEEP LOOKING TILL COUNT
EXHAUSTED
VERT I CAL STUCK ON
;----- NOW START LOOKING FOR ENABLE TRANSITIONS
POD14_3:
POD14 4:
-
SUB
eX,ex
IN
AL,DX
AL, 0000000 1B
POD14 5
AL, 0000 1OOOB
POD14 75
POD14::::4
BL,02H
POD14_ERR
;
BL,03H
POD14_ERR
; VERT I CAL STUCK ON
BL,04H
POo14_ERR
;
TEST
JE
T[ST
JNE
LOOP
MOV
JMP
POD14_4A:
MOV
JMP
POD14_4B:
MOY
JMP
GET STATUS
ENABLE ON YET?
GOONIFITIS
VERT I CAL ON AGA I N?
CONTINUE IF IT IS
KEEP LOOK I NG I F NOT
ENABLE STUCK Off
ENABLE STUCK ON
;----- MAKE SURE VERTICAL WENT Off WITH ENABLE GOING ON
POD14_5:
TEST
AL, 00001 OOOB
VERTI CAL Off?
JNZ
P0014_4A
GO ON If IT IS
; ----- NOW WAI T fOR ENABLE TO GO Off
(ERROR I F NOT)
POD14_6:
IN
AL,DX
GET STATUS
TEST
AL,OOOOOOOlB
ENABLE OFf YET?
LOOPE
POD14_6
KEEP LOOKING If NOT
JCXZ
POD14_4B
,
YET LOW
;----- ENABLE HAS TOGGLED, BUMP COUNTER AND TEST FOR NEXT VERTICAL
IBM Enhanced Graphics Adapter 113
03C5
03C5
03C6
74 04
03C8
A8 08
03CA
74 02
03CC
03CC
03CE
0300
eo 00
E6 43
3B 5E 02
0303
0305
0307
0309
0309
030B
0300
030E
03EO
03E2
03E3
03E4
03£7
03E9
03EB
03EO
03Eo
03FO
03F2
03F4
03F6
03F6
03F9
4'
74 04
B3 OS,
EB 6F
E4
8A
90
E4
86
90
90
3B
70
B3
EB
40
EO
3B
7E
B3
EB
46 06
04
07
52
40
EO
46 04
04
06
5B
B8 090S
BS OOOF
03FC
03Ff
0401
0402
0403
0405
0407
0409
040C
040F
0410
0410
0411
0412
0414
0416
0419
041A
0418
B2
B4
E8
5A
58
2B
0410
01110
041E
0420
0422
0424
0426
0428
EC
A8
75
E2
B3
OA
EB
0428
042B
0420
0420
042E
0430
0432
EC
A8 30
74 08
E2 F9
0434
0436
0438
B3 20
OA DC
EB OE
043A
043A
043C
043F
0441
0444
0446
0448
0448
044B
044E
0451
0454
0456
0458
045A
045C
0450
045E
0460
0463
0466
0466
0469
046C
046E
0470
0472
0474
0476
0477
0478
047A
0470
0480
0480
0480
S9 0050
CD 10
EC
52
B2
B4
BO
E8
B8
5A
CO
OF
3f
0015 R
OOOF
50
52
CO
32
0015 R
C9
30
09
F9
10
DC
1E 90
2B C9
FE
80
74
80
8A
EB
C4
FC 30
25
CC OF
C4
C8
B9
BA
E8
83
SO
E6
2A
E6
90
90
£6
Bo
E9
0006
0103
06C8 R
C4 OA
36
43
CO
40
E8
88
CD
80
E6
2A
E6
90
90
E6
83
SO
OCFE R
0500
10
36
43
CO
40
1E
40
0001
0091 R
40
C4 OA
0000
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1212
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
C
C
C
C
C
C
C
C
C
C
C
C
C
C
c
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
POD14_7:
BUMP ENABLE COUNTER
I F COUNTER WRAPS,
SOMETH I NG I S WRONG
DID ENABLE GO LOW
BECAUSE OF VERT I CAL
JZ
POD14_3
IF NOT, LOOK FOR ANOTHER
ENABLE TOGGLE
; ----- HAVE HAD COMPLETE VERT I CAL-VERT I CAL CYCLE: NOW TEST RESULTS
P0014_15:
MOV
AL,OO
LATCH T I MERO
OUT
TIM_CTl,AL
CMP
ex, WORD PTR! BP] (2]
NUMBER Of ENABLES BETWEEN
VERTICALS O.K.?
JE
P0014 8
MOV
BL,05H
JMP
SHORT POO14_ERR
POO14_8:
; GET TI MEA VALUE LOW
IN
AL, TIMERO
; SAVE IT
MOV
AH,AL
NOP
; GET TIMER HIGH
IN
AL, TlMERO
AH,AL
XCHG
NOP
NOP
CMP
AX, WORD PTAI SP][ 4]
; MAXIMUM VERTICAL TIMING
POD14_9
JGE
MOV
BL,06H
JMP
SHORT POO14_ERR
POD14_9:
AX, WORD PTR{ SP] (6]
; MINIMUM VERTICAL TIMING
CMP
P0014 10
JLE
MOV
SL,oiFi
JMP
SHORT
POD14_ERR
INC
JZ
BX
POO14_75
TEST
AL, 0000 1OOOB
;----- SEE I F RED, GREEN, BLUE AHO I NT ENS I FY DOTS WORK
;----- fiRST,
POO14_10:
MOV
MOV
SET A LINE OF REVERSE VIDEO,
AX,090SH
BX,OOOFH
MOV
CX,80
INT
10H
AL,oX
IN
PUSH
OX
MOV
OL,ATTR_WRITE
MOV
AH,OFH
MOV
AL,03FH
CALL
OUT ox
MOV
AX,OFH
POP
OX
POO14_13:
PUSH
AX
PUSH
OX
MOV
OL, ATTR_WR I TE
MOV
AH,32H
OUT_OX
CALL
POP
OX
POP
AX
SUB
CX,CX
; ----- SEE I F DOT COMES ON
POO14_14:
IN
AL,OX
TEST
AL, 0011 00008
P0014_15
JNZ
lOOP
P0014 14
MOV
BL, lOti
OR
BL,AH
JMP
POo14_ERR
; ----- SEE I F DOT GOES OFF
P0014_15:
SUB
CX,CX
POO14_16:
IN
AL,oX
TEST
Al,00110000B
JE
P0014_17
POD14_16
LOOP
MOV
OR
JMP
BL,20H
Sl,AH
SHORT POO14_ERR
I NTENS I F I ED BLANKS INTO BUFFER
; WRITE CHARS, BLANKS
PAGE 0, REVERSE VIDEO,
;
HIGH INTENSITY
; 80 CHARACTERS
;
;
;
;
;
;
SAVE I NPUT STATUS
ATTRIBUTE AOoRESSS
PALETTE REG' F'
TEST VALUE
V IDEO STATUS MUX
START WITH BLUE DOTS
;
;
;
;
;
;
SAVE
SAVE I NPUT STATUS
ATTA I BUTE AOoRESSS
COLOR PLANE ENABLE
VIDEO STATUS MUX
RECOVER I NPUT STATUS
; GET STATUS
; DOT THERE?
LOOK FOR DOT TO TURN OFF
; CONT I NUE TEST FOR DOT ON
OR I N DOT BE I NG TESTED
DOT NOT COM 1NG ON
;
GET STATUS
IS DOT STILL ON?
; GO ON IF DOT OFF
; ELSE, KEEP WAITING FOR
DOT TO GO OFF
;
; OR I N DOT BE I NG TESTED
; ----- ADJUST TO PO I NT TO NEXT DOT
POO14_17:
INC
CMP
JE
OR
MOV
JMP
P0014_ERR:
MOV
MOV
CALL
ADD
MOV
OUT
SUB
OUT
NOP
NOP
OUT
MOV
JMP
ASSUME
POO14_18:
CALL
MOV
INT
MOV
OUT
SUB
OUT
NOP
NOP
OUT
ADD
MOV
POO14
;
-~~--
AH
AH,030H
P0014 18
AH,OFH
AL,AH
POO14_13
CX,6
DX,0103H
ERR_BEEP
SP,OAH
AL,00110110B
TIM_CTL,AL
AL,AL
TIMERO,AL
; ALL 3 DOTS DONE?
; GO END
; MAKE OF, If,2F
; GO LOOK FOR ANOTHER DOT
; ONE LONG AND THREE SHORT
;
;
BALANCE STACK
RE-INIT TIMER 0
TIMERO,AL
BP,l
SKI P
OS:ABSO
DDS
AX,0500H
10H
Al,00110110B
TIM_CTL,AL
AL,AL
TIMERO,AL
T1MERO,Al
SP,OAH
BP,O
ENOP
SET TO VIDEO PAGE 0
RE-INIT TIMER 0
; REMOVE SCRATCH PAD
; MAKE SP NON ZERO
TEST STORAGE
MEM_TEST:
PUSH
OS
114 IBM Enhanced Graphics Adapter
August 2, 1984
0481
E8 OCfE R
0484
0489
048B
0490
0493
0498
049B
0490
0490
04A2
04A7
04AA
04AA
04AC
04AF
04Bl
f6
74
80
88
80
88
fB
CO
83
88
BB
10
EC 06
EC
ACOO
04B4
04B6
04B8
04BO
04C2
04C4
04C6
04C9
04CC
04CE
0401
0404
0405
0407
0408
040A
0400
04EO
04E3
04E6
04E8
04EB
04EB
04EE
04Fl
04F3
04F6
04F6
OitF7
04F9
04fC
04ff
0501
0504
0507
OS08
050A
050B
0500
0510
0513
0518
051B
051£
0520
0523
0523
0526
0529
052B
052E
052E
052F
0531
0534
0537
0538
053A
0530
0540
0542
0543
0545
0548
054B
0550
0553
0556
0558
055B
0558
055E
0561
0563
0566
0566
0567
0569
056C
056f
0571
0574
0577
0578
057A
057B
0570
0580
0583
0588
058B
058E
0590
0593
0596
0598
0599
059C
059C
0590
059E
8E
8E
C7
C7
B6
B2
B8
E8
B2
B8
E8
52
B2
EC
82
B8
E8
E8
80
74
E9
08
CO
46 02 0000
46 04 0000
03
C4
0201
0015 R
CE
0400
0015 R
E8
80
74
E9
0509 R
FC 00
03
05CO R
05Al
05A5
05A7
05A9
05AA
06 0487 R 02
12
DE 0410 R 30
OOOf
DE 0487 R 60
OOOf
00
80 26 0410 R Cf
80 OE 0410 R 20
B8 OOOE
5A
B2
68
E8
62
B8
E8
52
B2
EC
B2
B8
E8
C7
E8
80
74
E9
EB
80
74
E9
5A
B2
B8
E8
52
B2
B8
E8
82
EC
82
B8
EB
C7
E8
80
74
EB
E8
80
74
EB
5A
82
68
E8
82
B8
E8
52
B2
EC
82
B8
E8
C7
E8
80
75
E8
80
75
OA
CO
3200
0015 R
068F R
FC 00
03
05CD R
C4
0202
0015 R
CE
0401
0015 R
DA
CO
3200
0015 R
46 04 0000
068F R
FC 00
03
OSCD R
0509 R
FC 00
03
05CD R
C4
0204
0015 R
CE
0402
0015 R
DA
CO
3200
0015 R
46 04 0000
068F R
FC 00
03
73 90
0509 R
FC 00
03
68 90
C4
0208
0015 R
CE
0403
0015 R
DA
CO
3200
0015 R
46 04 0000
068F R
Fe 00
3D
0509 R
FC 00
35
55
BO 0000
5E
5A
E8 OCFE R
36: 88 SC 02
B1 06
03 EB
4B
B1 05
August 2, 1984
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
140O
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
CAll
DDS
ASSUME OS: ABSO
TEST
INfO,2
JZ
O_COlOR_M
OR
EQUIP~LOW,030H
MOV
AX,OfH
OR
INfO,060H
MOV
AX,OfH
JMP
SHORT O~OUT~M
O~COlOR_M:
AND
OR
MOV
£QUIP_lOW,OCFH
EQUIP_lOW,020H
AX,OEH
INT
SUB
MOV
MOV
ASSUME
MOV
MOV
MOV
MOV
MOV
MOV
MOV
CAll
MOV
MOV
CAll
PUSH
MOV
IN
MOV
MOV
CALL
CAll
CMP
JZ
JMP
10M
SP,6
BP, SP
AX,OAOOOH
OS: NOTH lNG, £S: NOTH I NG
OS,AX
ES,AX
WORD PTR[BP][2],0
WORD PTR[BP][4],0
DH,3
Dl, SEQ_ADOR
AX,0201H
OUT_OX
Ol, GRAPH_AOOR
AX,0400H
OUT_OX
OX
Ol,ATTR_REAO
Al,OX
Ol,ATTR_WRlTE
AX, 3200H
OUT_OX
HOW BIG
AH,O
AA1
EGA_MEM_ERROR
I NTERNAL COLOR MODE
TEST I N COLOR
D_OUT_M:
RESERVE 3 WORDS ON STACK
SET BP
PUT BUFFER ADDRESS IN AX
SET UP SEG REGS TO POI NT
TO BUFFER AREA
INITIALIZE
INITIALIZE
ADDRESS READ MAP SELECT
SET UP ATTRIBUTE
ATTRIBUTE WRITE ADDRESS
GO fINO AMOUNT OF MEMORY
AAl:
CAll
• CMP
JZ
JMP
MEMORY_OK
AH,O
AA2
EGA_MEM_ERROR
GO TEST IT
AA2:
POP
MOV
MOV
CALL
MOV
MOV
CAll
PUSH
MOV
IN
MOV
MOV
CAll
MOV
CAll
CMP
JZ
JMP
OX
DL, SEQ_AOOR
AX,0202H
OUT OX
Ol, GRAPH_AOoR
AX,0401H
OUT_OX
OX
Ol,ATTR_READ
Al,OX
Dl, ATTR_WR I TE
AX, 3200H
OUT_OX
WORD PTR [BPj[4],0
HOW_BIG
AH,O
AA3
EGA_MEM_ERROR
CALL
CMP
JZ
JMP
MEMORY_OK
AH,O
AA"
EGA_MEM_ERROR
POP
MOV
MOV
CALL
PUSH
MOV
MOV
CALL
MOV
IN
MOV
MOV
CALL
MOV
CALL
CMP
JZ
JMP
OX
DL, SEQ....ADOR
AX,0204H
OUT_OX
OX
DL, GRAPH_ADoR
AX,0402H
OUT_OX
ol, ATTR_READ
Al,DX
ol, ATTR_WR I TE
AX, 3200H
OUT OX
WORD PTR[BP1I4],0
HOW_BIG
AH,O
AA5
EGA_MEM_ERROR
CAll
CMP
JZ
JMP
MEMORY_OK
AH,O
AA6
EGA_MEM_ERROR
ADDRESS OF READ MAP
SET UP ATTRIBUTE
ATTRIBUTE WRITE AOORESS
INITIALIZE
GO F I NO AMOUNT Of MEMORY
AA3:
; GO TEST IT
AA4:
ADDRESS OF READ MAP
SET UP ATTRIBUTE
ATTRIBUTE WRITE ADORESS
INITIALIZE
GO F I NO AMOUNT Of MEMORY
AA5:
GO TEST IT
AA6:
POP
MDV
MOV
CAll
MOV
MOV
CALL
PUSH
MOV
IN
MOV
MOV
CAll
MOV
CALL
CMP
JNZ
CAll
CMP
JNZ
PUSH
MOV
EGA_MEM_EX IT:
POP
POP
CALL
ASSUME
MOV
MOV
SHR
DEC
MOV
OX
Dl, SE'LADDR
AX,0208H
OUT_OX
Dl, GRAPH_AODR
AX,0403H
OUT_OX
OX
Ol,ATTR_READ
Al,oX
DL,ATTR~WRJTE
AX,3200H
OUT OX
WORD PTR[ SP][ 4], 0
HOW BIG
AH,O
;
ADDRESS Of READ MAP
SET UP ATTRIBUTE
ATTRIBUTE WRITE ADDRESS
INITIALIZE
GO f r NO AMOUNT Of MEMORY
EGA~MEM_ERROR
MEMORY_OK
AH,O
EGA_MEM_ERROR
BP
BP,O
GO TEST
51
OX
DDS
oS:ABSO
BX,WORD PTR SS:[SI][2)
Cl,06H
BX,Cl
BX
Cl,05H
RESTORE
IT
SAVE SCRATCH PAD POINTER
RESET BP FOR XT
SET DATA SEGMENT
GET EGA MEMORY SIZE
DIVIDE BY 64 TO GET
NUMBER OF 64KB BLOCKS
IBM Enhanced Graphics Adapter 115
05AC
05A£
D3 E3
80 £3 60
05Bl
80 26 04B7 R 9F
05B6
08 1 £ 0487 R
05BA
05BF
05C3
05C6
05C9
05CA
05CO
05CO
05DO
0503
0504
05D7
80
8A
£8
83
lF
£9
DE 0487 R 04
1 E 0488 R
00F3 R
C4 06
BA
£8
55
BO
£B
0103
06C8 R
BB
8E
8E
8B
8A
2A
01
E8
80
7S
AOOO
DB
C3
46 04
E8
C9
E1
05FB R
FC 00
09
0509
0509
050C
050E
05£0
05E3
05£5
05E7
05E9
OSEC
OSEF
OSFl
OSFl
OSF4
OSF7
05FA
OSFA
OSFB
0091 R
0001
C3
88 46 04
01 46 02
B8 0000
C3
OSFB
OSFB
05FC
OSFD
S5
FC
26 FF
05FF
26 CO
0601
E8 OCFE R
0604
0608
060C
060E
0610
86
81
8C
8E
74
0612
0616
0618
0618
061A
061C
061E
0620
0622
0624
81 FB 4321
74 5e
88 05
8A 05
32 C4
7540
FE C4
8A C4
7S F2
0626
0628
0626
0620
8B
B8
88
BA
0630
1 E 0472 R
F6 1234
C2
OA
62
E9
AA55
08
55AA
F31 AS
0632
0633
0634
0635
0637
0639
0639
063A
063C
063£
0640
0641
0643
0645
0646
0647
0648
064A
064A
0646
0640
064F
4F
4F
FD
86 F7
8B CD
0650
E2 F8
0652
0653
4E
0654
0655
0657
0657
0658
065A
065C
065E
0660
0660
0662
0664
AD
33
75
86
A6
E2
8B
FC
46
46
8B
C3
22
C2
F6
CD
F£
AD
33 C2
75 11
A6
FO
4E
8B CD
AD
06
75
E2
EB
CO
04
F9
11
8B C8
32 E4
OA ED
1513
1514
1S15
1516
1S17
1518
1S19
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1S63
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
c
c
c
c
c
c
c
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
BX,CL
BL,01'00000B
AND
INFO,100111'1B
SHL
OR
OR
MOV
CALL
ADD
POP
JMP
EGA_MEM_ERROR:
MOV
CALL
PUSH
MOV
JMP
ISOLATE BITS SAND 6
I NFO,BL
INFO,00000100B
BL,INFO_3
MK ENV
SP-:-6
OS
SKI P
DX,0103H
ERR BEEP
BP BP,l
EGA_MEM_EXIT
; 04H
;
SET 3XX ACT I VE
RESTORE STACK
; GO TO END
; ONE LONG AND THREE SHORT
; SAVE SCRATCH PAD POINTER
; I NO I CA TE ERROR FOR XT
;----- THIS ROUTINE FINDS AMOUNT OF MEMORY GOOD
MEMORY OK
- MOV
MOV
MOV
MOV
MOV
SUB
SHL
CALL
CMP
JNZ
MEMORY OK EX:
- MOV
ADO
C
C
AND
MOV
MEMORY OK ERR:
- RET
MEMORY_OK
;
PROC
NEAR
BX,OAOOOH
DS,BX
ES,BX
AX,WORD PTR[BP)[4J
CH,AL
CL,CL
CX,'
POOSTG
AH,O
MEMORY_OK_ERR
AX,WORD PTR[BP1I4)
WORD PTRIBP)[2I,AX
AX,O
SET PTR. TO BUFFER SEG
SET SEG. REG.
; SET COUNT FOR 32K WORDS
; SET AMOUNT OF 8UFFER
,
TO BE TESTED
; MULTIPLY BY TWO
; TEST FOR ERROR
; IF ERROR GO PRINT IT
; AMOUNT OF MEMORY FOUND
; AMOUNT OF MEMORY GOOD
ENoP
---------------------------------------------------------------TH I S ROUTI NE PERfORMS A READ/WR I TE TEST ON A BLOCK OF STORAGE :
C
C
C
(MAX. SIZE'" 32KW). IF "WARM START", fiLL BLOCI< WITH 0000 AND:
RETURN.
:
ON ENTRY:
ES = ADDRESS OF STORAGE TO BE TESTED
OS = ADDRESS OF STORAGE TO BE TESTED
CX = WORD COUNT Of STORAGE BLOCK TO BE TESTED
(MAX. '" BOOOH (32K WORDS))
ON EXIT:
,
ZERO FLAG'" OFF I f STORAGE ERROR
; AX,BX,CX,DX,OI,SI ARE ALL DESTROYED.
C
~ODS;:G--PROC----NEAR---------------------------------------------
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
PUSH
CLO
BP
SUB
01,01
SUB
AX,AX
CALL
ASSUME
MOV
CMP
MOV
MOV
JE
DOS
DS:ABSO
BX, OS: RESET_FLAG
BX,1234H
OX,ES
OS,OX
POOSTG_5
CMP
JE
PODSTG_' :
MOV
MOV
XOR
JNZ
INC
MOV
JNZ
MOV
MOV
MOV
MOV
SET 0 I R TO INCREMENT
SET 01=0000 REL TO START
OF SEGMENT
INITIAL DATA PATTERN FOR
OO-FF TEST
; WARM START?
RESTORE OS
GO 00 FILL WITH 0000
I f WARM START
OCP WARM START?
00 fiLL IF SO
BX,4321H
PODSTG_5
[01 J,AL
AL,IOI}
AL,AH
PODSTG ERRO
AH
AL,AH
POOSTG_1
REP
BP,CX
AX,OAA55H
ax,AX
DX,055AAH
STOSW
DEC
DEC
01
01
; WRITE TEST DATA
; GET IT BACK
COMPARE TO EXPECTED
ERROR EXIT If MISCOMPARE
FORM NEW DATA PATTERN
LOOP TILL
PATTERNS
SAVE WORD
LOAD DATA
LOAD OTHER DATA PATTERN
FILL WORDS FROM LOW TO
HIGH WITH AAAA
PO I NT TO LAST WORD
WRITTEN
SET 0 I R FLAG TO GO DOWN
SET INDEX REGS. EQUAL
RECOVER WORD COUNT
GO fROM HIGH TO LOW
GET WORD FROM MEMORY
EQUAL WHAT S/8 THERE?
GO ERROR EXIT I F NOT
GET 55 DATA PATTERN AND
STORE IN LOC JUST READ
LOOP TI LL ALL BYTES DONE
RECOVER WORD COUNT
BACK TO INCREMENT
ADJUST PTRS
STO
MOV
MOV
POOSTG_2:
LOOSW
XOR
JNZ
MOV
STOSW
LOOP
MOV
CLD
INC
INC
MOV
PODSTG 3:
- LODSW
XOR
JNZ
STOSW
SI,OI
CX,SP
AX,BX
PODSTG_ERRO
AX, OX
POOSTG_2
CX,BP
$I
$I
OI,SI
LOW TO HIGH DO I NG WORDS
GET A WORD
SHOULD COMPARE TO OX
GO ERROR I F NOT
WR I TE 0000 BACK TO LOC
JUST READ
LOOP TILL DONE
AX,OX
PODSTG_ERRO
LOOP
STD
DEC
DEC
MOV
PODSTG_4:
LODSW
OR
JNZ
LOOP
JMP
PODSTG_ERRO:
HOV
'OR
OR
ALL 256 DATA
DONE
COUNT
PATTERN
BACK TO DECREMENT
ADJUST POINTER DOWN TO
LAST WORD WR I TTEN
$I
$I
eX,BP
;
IV<,IV<
, GET WORD
; '" TO 0000
PODSTG ERRO
PODSTG-4
SHORT PODSTG_ERR2
ex, AX
AH,AH
CH,CH
116 IBM Enhanced Graphics Adapter
GET WORD COUNT
ERROR I F NOT
LOOP TILL DONE
SAVE BITS I N ERROR
HIGH BYTE ERROR?
August 2, 1984
0666
0666
066A
066A
066C
066£
0671
0671
0672
0673
0674
74 02
B4 01
0674
0675
0676
0678
067A
0670
0680
0681
0682
0684
50
52
86 03
82 C4
88 020F
£8 0015 R
5A
58
F3/ A8
£8 OCFE R
0687
068B
0680
068F
89 1 E 0472 R
8£ OA
EB E2
068F
068F
0691
0693
0693
0695
0697
069A
069C
069F
06A1
06A4
06A6
06A8
OMB
06A0
06Bl
06B4
06B7
06B9
06BC
06BC
06BF
06C1
06C1
06C4
06C7
06C7
06C8
06C8
06C6
06C9
06CA
06CB
06CE
0600
0602
0602
0604
0607
0607
0609
060B
0600
0600
060F
06E2
06E2
06E4
06E6
06E8
06E8
06EA
06EA
06EC
06ED
06E£
06EF
OA C9
74 03
60 C4 02
50
FC
C3
8C OA
2B DB
8E C2
2B FF
B8 AA55
8B C8
26: 89 05
BO OF
26: 8B 05
33 C1
75 14
B9 2000
F3/ AB
81 C2 0400
83 C3 10
80 FE BO
75 OA
EB 01 90
80 FE AO
74 06
01 5E 04
B8 0000
C3
9C
FA
1£
E8 OC FE R
OA F6
74 DB
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1656
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1676
1679
1660
1681
1682
1563
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1706
1709
1710
1711
1712
1713
1714
1715
1716
1717
B3 06
£8 0020 R
£2 FE
FE CE
75 F5
B3 01
£6 0020 R
£2 FE
F£ CA
75 F5
£2 FE
E2 F£
lF
90
C3
JZ
MOV
POOSTG_ERR1 :
JZ
ADD
POOSTG_ERR2:
POP
POOSTG_5:
PUSH
PUSH
MOV
MOV
MOV
CALL
POP
POP
REP
as: RESET_FLAG, BX
as, OX
JMP
POOSTG_ERR2
SET 0 I R FLAG BACK TO INC
RETURN TO CALLER
SIMPLE FILL WITH 0000 ON
WARM-START
SAVE
SAVE VALUE
SEQ_AOOR
REG I STER
DO IT
RESTORE
RESTORE
ODS
OS:ABSO
; RESTORE OS
; AND EXIT
ENOP
;----- DETERMINE SIZE OF BUffER
HOW_BIG
MOV
SUB
FILL_LOOP:
MOV
SET PNTR TO BUffER LOC
BAS I C COUNT Of OaK
ES,OX
SET SEG.
SUB
01,01
AX,OM55H
CX,AX
ES: [01 LAX
AL,OfH
AX,ES:[DI]
AX,ex
HOW_B I G_ENO
CX,2000H
XOR
REP
PROC NEAR
OX,OS
BX,BX
MOV
MOV
MOV
MOV
MOV
JHZ
MOV
STOSW
ADO
ADD
CMP
JNZ
JMP
OX,0400H
BX,16
OH,DBOH
fiLL_LOOP
HOW_BIG_END
REG
TEST PATTERN
SEND TO MEMORY
PUT SOMETH I NG IN AL
GET PATTERN FROM MEMORY
COMPARE PATTERNS
GO END t f NO COMPARE
SET COUNT fOR 8K WORDS
FILL 8K WORDS
POINT TO NEXT 16K BLOCK
BUMP COUNT BY 161 16K MODE VALUES
;~~F~-
DB
DW
800,240,14D
08000H
DB
001H, OOFH, OOOH, 006H
DB
OA2H
DB
DB
DB
DB
DB
060H, 04FH, 056H, 03AH, 050H, 060H
070H, 01 FH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, 05EH. 02EH
OSOH, 028H, OOOH, 05EH, 06EH, OE3H
OFFH
DB
DB
DB
DB
OOOH, 008H,000H, OOOH, 018H, 018H
OOOH, OOOH, OOOH, 008H, OOOH, OOOH
OOOH, 018H, OOOH, OOOH, OOBH, OOOH
005H,000H
DB
DB
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
005H,00FH,OFFH
DB
DW
800,240,140
08000H
DB
001 H, OOFH, OOOH, 006H
;~10-~
BASE_3
;~~~~-
DB
OA7H
DB
DB
DB
DB
DB
05BH, 04FH, 053H, 037H, 052H, OOOH
06CH, 01 FH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, 05EH, 02BH
050H, 028H, OOfH, 05 FH, OOAH, OE3H
OFFH
DB
DB
DB
DB
OOOH, 001H, 002H, 003H, 004H, OOSH
014H, 007H, 038H, 039H, 03AH, 03BH
03CH, 030H, 03EH, 03FH, 001 H, OOOH
OOFH, OOOH
DB
DB
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
005H,OOFH,OFfH
EQU
S
~
VIOEO_PARMS
HI RES ALTERNATE VALUES
; --0-DB
DW
400,240,140
00800H
DB
00BH,003H, OOOH, 003H
DB
OA7H
DB
DB
DB
DB
DB
020H, 027H, 02BH, 020H, 028H, 060H
06CH, 01 FH, OOOH, OOOH, 006H, 007H
OOOH, OOOH, OOOH, OOOH, 05EH, 02BH
050H, 014H, OOFH, 05EH, OOAH, OA3H
OFFH
DB
DB
DB
DB
OOOH, 001 H, 002H, 003H, 004H, 005H
014H, 007H, 038H, 039H, 03AH, 03BH
03CH, 03DH, 03EH, 03 FH, 008H, OOOH
OOFH,OOOH
DB
DB
OOOH, OOOH, OOOH, OOOH, OOOH, 010H
OOEH,OOOH,OFFH
DB
DW
40D,240, 140
00800H
DB
OOSH, 003H,OOOH, 003H
DB
OA7H
DB
DB
DB
DB
DB
02DH, 027H, 02BH, 020H, 028H, 060H
06CH, 01 fH,OOOH, OODH, 006H, 007H
OOOH, OOOH, OOOH, OOOH, 05£H, 02BH
050H, 014H, OOFH, 05£H, OOAH, OA3H
OFFH
DB
DB
DB
DB
OOOH, 001H, 002H, 003H, 004H, 005H
014H, 007H,038H, 039H, 03AH, 03BH
03CH, 030H,03£H, 03FH, 008H, OOOH
OOFH,OOOH
DB
DB
OOOH, OOOH,OOOH, OOOH, OOOH, 010H
OOEH,OOOH,OFFH
DB
800,240,140
;~-1-~
;
-~2~~
IBM Enhanced Graphics Adapter 121
OC5A
1000
OC5C
01 03 00 03
OC60
A7
OC61
OC67
OC60
OC73
OC79
5B
6C
00
50
FF
4F
1F
00
28
OC7A
OC80
OC86
OC8C
00
14
3C
OF
01 02 03 04 05
07 38 39 3A 3B
30 3E 3F 08 00
00
OC8E
OC94
00 00 00 00 00 10
DE 00 FF
53
00
00
OF
37 51
00 06
DOSE
5E OA
OC97
OC9A
50 18 OE
1000
OC9C
01 03 00 03
5B
07
2B
A3
OCAO
A7
OCAl
OCA7
OCAO
OCB3
OCB9
58
6C
00
50
OCBA
OCCO
OCC6
OCCC
00
14
3C
OF
aCCE
OC04
00 00 00 00 00 10
DE 00 FF
OC07
oe07
OG08
OCD9
OCOA
OCOB
QGoe
oeoo
OGOE
DGOF
OGEQ
OCEl
OCE2
OCE4
OCE6
OCE8
OCEA
OGED
OGEf
OCFO
OCF2
OCF5
OCF5
OCF8
OCF9
OCfE
OCfE
OCfF
0001
0003
0004
0005
4F
1F
00
28
53
00
00
OF
37 51
00 06
DOSE
5E OA
FF
01 02 03 04 05
07 38 39 3A 3B
3D 3E 3F 08 00
00
FB
FC
55
06
1E
52
51
53
56
57
50
8A C4
32 E4
01
EO
8B FO
3D 0028
72 06
58
CD 42
E9 219E R
E8 OCFE R
58
2E:
FF A4 06EF R
50
2B CO
8E 08
5B
c3
0005
0005
0006
0009
0000
0010
0013
0014
0015
0015
0015
0011
0018
0019
001B
001C
0010
001 E
OlllE
001 E
OOlF
0020
0020
0020
0021
0024
0026
0029
Q02C
0020
0030
0032
0035
58
07
2B
A3
1E
E8
8B
80
80
IF
OCFE R
16 0463 R
E2 FO
CA OA
C3
86 C4
EE
42
86 C4
EE
4A
C3
EE
C3
52
BA
BO
E8
88
0043
B6
DOlE R
0533
4A
E8
SA
[8
BA
OOlE R
C4
OOlE R
0061
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
OW
01000H
DB
DOl H, 003H, OOOH, 003H
DB
OA7H
DB
DB
DB
DB
DB
05BH, 04FH, 053H, 037H, 051 H, 05BH
06CH, 01 FH, OOOH, OOOH, 006H, 007H
OOOH, OOOH, OOOH, OOOH, 05EH, 02BH
050H, 028H, OOFH, 05EH, OOAH, OA3H
OFFH
DB
DB
DB
DB
OOOH, DOl H, 002H, 003H, 004H, 005H
014H, 007H, 038H, 039H, 03AH, 03BH
03CH, 030H, 03EH, 03 FH, 008H,000H
OOFH,OOOH
DB
DB
OOOH, OOOH, OOOH, OOOH, OOOH, 010H
OOEH,OOOH,OFFH
; --3--
OW
800,240,140
01000H
DB
DOl H, 003H, OOOH, 003H
DB
OA7H
DB
DB
DB
DB
DB
05BH,04FH, 053H, 037H, 051 H, 05BH
06CH, 01 FH, OOOH, OODH, 006H, 007H
OOOH, OOOH, OOOH, OOOH, 05EH, 02BH
050H, 028H, OOFH, 05EH, OOAH, OA3H
OFFH
DB
DB
DB
DB
OOOH, 001 H, 002H, 003H, 004H, 005H
014H, 007H, 038H, 039H, 03AH, 03BH
03CH, 030H, 03EH, 03FH, 008H, OOOH
OOFH,aOOH
DB
DB
OOOH, OOOH, OOOH, OOOH, 000H,010H
OOEH,OOOH,OFFH
DB
SUBTTL
; ----- VECTOR INTO SPEC I F I ED FUNCT I ON
COMBO_VIOEO
PROC
NEAR
I NTERRUPTS ON
SET D I REeT I ON FORWARD
SAVE THE REG I STER SET
STI
CLD
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
BP
ES
OS
OX
CX
BX
SI
01
PUSH
AX
MOY
XOR
SAL
MOY
CMP
JB
POP
INT
JMP
AL,AH
AH,AH
AX, 1
SI,AX
AX, T2L
; SAVE AX VALUE
; GET I NTO LOW BYTE
; ZERO TO HIGH BYTE
2 FOR TABLE LOOKUP
PUT INTO SI FOR BRANCH
TEST FOR WITHIN RANGE
BRANCH AROUND BRANCH
RECOVER REG I STER
PASS UNRECOGN IZEO CALL
RETURN TO GALLER
; *
M2
AX
42"
V_RET
M2:
ASSUME
CALL
PDP
JMP
OS:ABSO
DDS
AX
RECOVER
JMP TO AH,=O THRU AH=XX
WORD PTR CS:ISI + OFFSET T2]
; ----- UT I L I TY ROUT I NES
; ----- SET OS TO THE DATA SEGMENT
DDS
PROC
PUSH
SUB
MOY
POP
RET
DDS
NEAR
SAVE REG I STER
AX
AX,AX
OS,AX
AX
RESTORE REG I STER
ENOP
WHAT_BASE
ASSUME
PUSH
CALL
MOY
AND
OR
POP
RET
PROC
NEAR
OS:ABSO
OS
DDS
OX,AOOR_6845
OL,OFOH
OL,OAH
ENDP
OUT_OX
NEAR
AL,AH
DX,AL
OUT
INC
XCHG
OUT
DEC
RET
aU-I_DX
BP_'
BEEP
; AH"'INOEX,AL=OATA,DX"'PORT
; GET I NOEX VALUE
; SET I NOEX REG
SET OX TO DATA REG
GET DATA VALUE
SET DATA REG
SET OX BACK TO I NO[X
OX
AL,AH
OX,AL
DX
ENOP
;----- ROUTINE 10
BP_'
SAVE DATA SEGMENT
GET LOW MEMORY SEGMENT
GET CRTC ADDRESS
STRI P Off LOW NIBBLE
SET TO STATUS REGISTER
OS
WHAT_BASE
PROC
XCHG
;.
;
;
;
;
PROC
OUT
RET
~OlJNlJ
Bl[PlK
NEAR
aX,AL
[NOP
PROC
PUSH
NEAR
MOY
MOY
OX, TI MER+3
AL,101101108
DX
CALL
BP 1
MOY
DEC
AX-;-533H
; SEL TIM 2,LSB,MSB,BINARY
; WR I TE THE T I MER MODE REG
; QIVISOR FOR 1000 HZ
; WRITE TIMER 2 CNT -
CALL
DX
BP 1
MOY
Al-;-AH
CALL
BP 1
MOY
OX-;-PORT_B
122 IBM Enhanced Graphics Adapter
LSB
; WRITE TIMER 2 CNT - HS8
August 2, 1984
0036
0039
003B
0030
0040
0042
0042
0044
0046
0048
004_"
0040
004E
004F
EC
8A
OC
E8
2B
EO
03
DOlE R
C9
E2
FE
15
8A
E8
FE
CB
FA
C4
DOlE R
5A
C3
004F
004F
0052
0056
0059
OD5A
E8 OCFE R
C4 1E 04A8 R
26: C4 1F
C3
OD5A
OD5A
0056
005C
005F
0063
0068
51
52
E8
8A
F6
74
OD4F R
26 0449 R
06 0487 R 60
16
OD6A
0060
OD6F
0073
0076
0076
0079
0078
007F
0082
0082
0085
80
75
61
EB
FC OF
07
C3 0440
33 90
80
75
81
E8
FC 10
07
C3 0480
27 90
0087
OOSA
008C
008E
0090
0092
0094
0097
0097
0098
OD9B
009F
OOAl
00A3
ODA3
00A6
00A8
00A8
OOM
ODA9
OOAA
OOAB
80 FC 03
17 14
AD
24
3C
74
3C
74
EB
0488 R
OF
03
07
09
03
05 90
81 C3 04co
8A DE 0449 R
2A ED
E3 05
83 C3 40
E2 FB
5A
59
C3
OOAB
OOAB
OOAE
OOBl
00B3
00B5
00B8
00B9
DOBC
DoeF
00C1
00C4
00C4
00C6
OOC7
OOCA
OOCD
DODO
E8
83
B6
B2
B8
0002
0005
0006
0008
0009
OOOB
OODE
OOEl
26: 8A 07
ODE2
00E6
00E8
00E8
ODE8
OOEE
OOEF
OOfl
OD5A R
C3 05
03
C4
0001
FA
E8 0015 R
26: 8A 07
FE. C4
E8 0015 R
FE C4
43
26: 8A 07
E8 0015 R
80 FC 05
72 F2
43
B2 C2
EE
82 C4
B8 0003
E8 0015 R
FB
88 16 0463 R
2A E4
26: 6A 07
E8 0015 R
43
FE C4
80 FC 19
August 2, 1984
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
21115
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
242B
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
GET SETT I NG OF PORT
SAVE THAT SETTING
TURN SPEAKER ON
SUB
AL,OX
AH,Al
Al,03
BP_l
ex,cx
lOOP
07
DELAY BEFORE TURNING OFF
DELAY CNT EXP 1RED?
NO-CONT I NUE BEEP I NG SPK
RECOVER VALUE OF PORT
IN
MOV
OR
eAll
SET CNT TO WA 1T 500 MS
07:
DEC
JNZ
MDV
Bl
CALL
PDP
RET
BEEP
07
Al,AH
BP_'
OX
RETURN TO CAllER
ENDP
;----- FIND THE PARAMETER TABLE VECTOR I N THE SAVE TABLE
SET_BASE
ASSUME
CALL
PROC
NEAR
DS:ABSO
DDS
GET PTR TP PTR TABLE
GET PARAMETER PTR
BX, SAVE_PTR
BX,DWORO PTR ES:[BX)
lES
lES
RET
SET_BASE
ENDP
;----- ESTABLISH ADDRESSING TO THE CORRECT MODE TABLE ENTRY
MAKCBASE
ASSUME
PUSH
PUSH
CAll
MOV
TEST
JZ
PROC
NEAR
OS: ABSO
CX
OX
GET PARM TBl PTR
SET BASE
AH,CRT_MOOE
INFO,060H
B_M_1
TEST FOR BASE CARD
MIN MEMORY
;----- WE HAVE A MEMORY EXPANSION OPTION HERE
CMP
JNE
ADD
JMP
AH,OFH
B_M_2
BX, BASE_2 8_M_OUT
CMP
JNE
ADD
JMP
AH,OlOH
BX, BASE_2 + M_ TBL_lEN B_M_OUT
CMP
JA
AH,03H
B_M_3
BASE_l
8_M_2:
B M 1
BASe 1
B_M_1 :
SK I P ENHANCED PORT I ON
;----- CHECK THE SWITCH SETTING FOR ENHANCEMENT
AL,INFO_3
AL,OFH
AL,03H
MOV
AND
CMP
JE
CMP
JE
JMP
SECONDARY EMULATE SEll I NG
BRS
PRIMARY EMULATE SETTING
AL,09H
BRS
B_M_3
; ----- WE WI LL PERFORM ENHANCEMENT
BRS:
ADD
BX,8ASE_3 - BASE_ 1
MDV
SUB
JCXl
Cl, CRT_MODE
CH,CH
B_M_4
; VECTOR TO ENHANCEMENT TBL
B_M_3:
;----- THIS loOP Will MOVE THE PTR TO THE INDIVIDUAL MODE ENTRY
B_M_5:
ADD
LOOP
BX, M_ TBl_lEN
B_M_5
;
LENGTH OF ONE MODE ENTRY
B M 4:
8=M=OUT:
PDP
PDP
RET
OX
CX
ENDP
MAKE_BASE
;----- PROGRAM THE EGA REGISTERS FROM THE PARAMETER TABLE
SET_REGS
ASSUME
PROC
NEAR
os: ASSO, ES: NOTH I NG
; ----- PROGRAM THE SEQUENCER
CAll
ADD
MDV
MDV
MOV
Cli
MAKE_BASE
BX, TFS_LEN
OH,3
Ol, SEQ_AOOR
AX,OOOlH
GET TABLE PTR
MODE TO SEQUENCER PARMS
;
CALL
MOV
INC
OUT_OX
AL,ES:[BXj
AH
CALL
OUT_OX
RESET SEQUENCER
01 SABLE INTERRUPTS
; GET SEQUENCER VALUE
; NEXT INDEX
SET IT
01 :
INC
INC
MDV
NEXT I NOEX REG I sTm
NEXT TABLE ENTRY
AH
BX
CALL
CMP
JB
AL,ES:[BXj
OUT_OX
AH,M1+1
01
AL, ES: [BX)
MDV
INC
MDV
OUT
MDV
MDV
BX
CAll
Ol, MI SC_OUTPUT
OX,AL
Dl, SEQ_ADDR
AX,0003H
OUT_OX
START SEQUENCER
ENABLE INTERRUPTS
STI
; ----- PROGRAM THE CRT CONTROLLER
MDV
SUB
OX, AOOR_6845
AH,AH
; CRTC I NOEX REG' STER
; COUNTER
MDV
AL, ES: I BX)
OUT_OX
;
;
;
;
;
Xl:
CALL
INC
INC
CMP
BX
AH
AH,M4
GET VALUE FROM TABLE
SET CRTC REG I STER
NEXT TABLE ENTRY
NEXT I NOEX VALUE
TEST REG I STER COUNT
IBM Enhanced Graphics Adapter 123
OOF4
ODF6
OOFA
OoFC
OOFF
OEOl
OE04
OE05
OE07
O£O9
OE09
bEaC
tlE(lE
gw
",
7~
2~21
'2
2(i: 68 47 Fl
86 EO
A3 0460 R
8B F3
E8 0005 R
EC
B2 CO
2A E4
~~: E8A
07
Eo
OPA
OE1C
EE
gg~
OE2B
OE2D
OE2E
OE2F
0(32
004
ti~35
OE36
01::36
OE31
BO 00
IE
O.
C4 3E 04A8 R
26: C4 7[:\ 04
8C CO
OB C7
74 09
1F
IE
B9 0010
F3/ A4
4.
A4
07
1F
B2
one
EE
OEJP
OE3f
OE41
OE42
01::44
OE46
OE46
OE49
OE4C
OE40
OE4F
OE52
OE54
OE55
fij
26: 8A 07
E8 0015 R
43
FE C4
80 FC 09
72
e3
'2
DES5
OE55
OE58
OE5A
OE5C
OE5F
01::62
0[64
OE66
OE69
OE66
(iE6P
OE70
OE70
0E73
OE75
0[77
on9
OE7B
OE1D
onD
OE7F
OE83
OE85
OE88
OE~B
~m
0~8f
PE~j
O~9~
OF':95
OE95
~O 0487
AS 80
R
7$ 39
!;iA B800
~O 0449 R
3C 06
76 OA
BA BOOO
3C 07
74 O~
BA AOOO
IJB
3C
72
3C
74
2B
8E
8B
E3
89
80
,4
as
(H2O
04
06
07
02
DB
C2
DE 044C R
10
8000
FE AD
()2
40
~gn
F3/ AB
c,
OE96
PEQ6
OE96
d~99
OE9A
Ea
lbBl R
C3
~p::>,O
2621
2622
2623
2624
2625
26<;:6
2621
2628
262S!
2$30
2631,
~p32
g633
~~~~
OE9A
g~;;
()E~C
PE9f
OEA2
OEA3
OEAS
OEI\7
QE~9
OEAB
50
1E
E8 OCFE R
M 0488 R
1F
24 QF
3C 03
74 07
~e g~
~f=>3~
2637
2638
~~ij~
2641
2642
2643
~644
2645
2646
AL, ES: i BXJ
GET DATA VALUE
AH,AL
QX,AL
~H;P.oL
Ja
aX,AL
ax
AM
AH;M5
03
MPV
OUT
AL,O
OX,AL
NEXT OATA VALUE
NEXT INDEX VALUE
TEST REG I STER COUNT
DO THE REST
j ---,.;:.. CHECk I F PALETTE REG I STER VALUES AR~ TO BE SAVED
PUSH
PUSH
OS
ES
LES
LES
MOV
OR
JZ
OI,SAVE_PTR
OI,OWORO PTR ES:[01}(4)
AX,ES
AX,OI
SAVE_OUT
GET TABLE PTR
GET PALETTE PTR
;
I F ZERO, NO SAVE OCCURS
; ----- STORE AWAY THE PALETTE VALUES I N RAM SAVE AREA
pOp
pU.SH
MOV,_
MOVSB
INC,
MOVSB
SAVE_OUT:
OS
OS
CX,160
REP
PO~
'0'
;-~---
SAVE THE PALETTE REGS
$1
SAVE THE OVERSCAN REG
ES
OS
PROGRAM THE GRAPHICS CHIPS
MCN
MOV
OUT
Mdv
MPV
oUt
MOY
SUB
~t;gRAPH_l_POS
OX,AL
qL, GRAPH_2_P05
AL; 1
OX,AL
,
0'-=; GRAPH AOOR
AH,AH
-
04:
MOV
CALL
INC
IHe
CMP
JB
RET
BX
AH
AL, ES: I BX]
OUT_OX
PARAMETER BYTE
SET IT
NEXT BYTE
NEXT REG I STER
AH,M6
04
CONTINUE
[NDP
SET_REGS
; --;,.-;. MODE SEt REGEN CLEAR ROUTI NE
BtMK
PR()C,
ASSUME
MOY
TEST
JHZ
MOV
MOV
CM'
JBE
MOV
eM'
JE
MOV
NEAR
as: ABSO, ES: NOTH f NG
AL;,INFO
AL,080H
; FILL RECEN WITH BLANKS
SEE IF .BLANK IS TO OCCUR
MODE SET HIGH BIT
5K I P BLANK FOR, REGEN
COLOR ,MODE REGEN ADDRESS
CURRENT MODE SET
0-6 ARE COLOR MODES
g~;O~800H
AL,CRT_MOOE
AL,,6
ceo
OX,OBOOOH
AL,7
CGO
OX,OAOOOH
MONOCHROME REGEN ADDRESS
MONOCHROME MOOE
; REMA I N I NG MODES
CGO:
~608
2609
2610
26n
2612
2613
2614
2615
2f)16
2611
2618
2619
I NOEX COUNTER
!;tOY
6~~
259~
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
,SI,BX
WHAT_BASE
AL,OX
Pl, ATTR_WR I TE
:<\H,AH
INC
2512
EE
AX. ES; (BX) (-OFH J
CALL
IN
MOY
SUB
our
25~1
2573
2574
2575
257(j
2'377
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589.
2590
2591
2592
SET LOW RAM VALUE
XCHG
bUT
XCHG
2571
B2 cA
B0 01
~.~
03:
2:170
cc
BO 00
DO THE REST
GET CURSOR MODE
~~R~~R_MOOE, AX
MOV
~539
2542
2543
2544
2545
2546
2547
2541:1
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
Xl
X,CHG
PROGRAM THE ATTRIBUTE CHIP
2540
256~
OI::3~
OE3A
j-----
2537
2536
FE c~
80 Fe 14
72 EF
43
JB
MOV
MOV
2,3.
EE ,"
86
E[
~E12
OE13
01::15
OE18
OE10
tlE1E
OE1F
OE23
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
:;:532
2533
2534
25:}5
MOV
BX,onOH
eM'
JB
eM'
JE
SU8
4
ot1
Al; 7
BX,BX
; GRAPH I CS BLANK VALUE
SRLDAIl
MOV
MOV
JCXZ
ES
ES,OX
CX,CRT_LEN
QUT..:J, ,
g".paODDH
; SET THE REGEN SEGMENT
WWl:
MaY
REGULAR COLOR CARD SETUP
~OV
RQWS, 0240
POINTS,8
M9V
PpP
AX
OR
CMP
JBE
CMP
JAE
OR
I ~FO, 00001000B
AI,.; 1
SL7
AL;4
ST_7
INFO,00000100B
; WA I T fOR, RETRACE ON
; MODES 2,3 ONLY
INT
JMP
42H
V_RET
; OTHER ADMtER MODE CALL
; BACK TO CALLER
RECOVER
EGA NOT ACT I VE
; DO RETRACE
ST_7:
;-~--;.. AT THis POINT THERE IS NO MONOCHROME ATTACHED TO THE ADAPTER
ST_1 :
AX, EQU I P_FLAG
AL,030H
Al,030H
ST_3
MOY
AND
CMP
JHE
j TEST THE EQU I PMENT FLAo
;
TO SEE IF THIS IS A
;
MONOCHRQ~E SETUP CALL
; MUST BE COLOR TO CARD
; ----- fALL THROUGH "'> REGULAR MONOCHROME CARD SETUP
ftOWS,024D
POINTS,Ol"o
MOY
MOV
POP
AX
MO"
OR
JMP
42H
CURSOR_MOOE,OBOCH
I NFO,8
V...;RET
ittr
;
-~--~
RECOVER
OTHER ADAPTER MODE CALL
F I X PLANAR VALUE
THE EGA I S NOT ACTIVE
BACK TO CALLER
MONOCHROME SETUP TO THE ADAPTER
ST_2:
POP
pU~H
RECOVER
SAVE
AX
AX
OH,3
AL,080H
INfO,07fH
INFO,AL
MOY
AND
AND
OR
POP
AND
CMP
AL, q7FH
AL,OfH
ST 2A
AL-:-7
PICK Off niE CLEAR BIT
MASK Off THE OTHER BITS
SAVE REGEN GLEAR, BIT
~ECOVER TRUE CALL VALUE
ALREADY DEALT WITH 01
A MONOCHROME MODE
00 THIS MODE
REGULAR MONOCHROME
CRT_MODE,AL
OL, CRTC~ADDR_B
OX
QQl
sAVE MODE VALUE
I T IS 3~B~X
SAVE CRTC ADDRESS
CaNT I NUE THE MODE SET
AX
JE
MOV
ST_2A:
MOV
MOY
MOY
JMP
;
~~~~~
ADDR~6845,
COLOR SETUP TO THE ADAPTER
ST_3:
POP
AX
PUSH
AX
MOY
ANO
AND
OR
POP
AND
MOY
MOY
MOY
DH,3
,o;L,08qH
INFO,07fH
INFO,AL
RECOVER PARAMETER VALUE
SAVE IT
ISOLATE REGEN CLEAR BIT
PREPARE 1NFO BYTE
SET IT, o~ NOT
RECOVER TRUE MODE tALL
DONE WITH D7
SAVE TH I S MODE
AX
AL,07FH
CRT_MODE, AL
DL, CRTC_ADOR
AOOR_6845, OX
3~D-X
SAVE CRTC ADDRESS
QQ1:
MOY
MOY
ASSUME
SAVE START ADDRESS
RESET PAGE VALUE TO ZERO
CRT_START,O
ACTtVE_PAGE,O
ES: NOTH I NG
MOY
MOY
CX,~
PUSH
OS
POP
SUB
REP
ES
AX,AX
STOSW
o I, OffSET CURSOR.... POSN
: 8 pACES OF cLiRSOR VALUES
; OffSET
ESTABLI SH
ADORESSINO
THOSE CuRSQR LOCATIONS
CLEAR OUT SAVED VALUES
°
CALL
MAKE_BASE
MOY
SUB
MOY
AL, ES: [BX)
AH,AH
CRT_COLS,AX
MOY
MOY
~L.ES:[BX][11
ROWS,AL
,
MOY
SUB
MOY
AL,ES:(BXJ(21
AH,AH
POINTS,AX
; GET THE BYTES/CHAR
j ZERO HIGH BYTE
) STORE BYTES/CHAR
MOY
MOY
AX, ES: I BX) [3)
CRT_LEN,AX
;
;
SUB
MOY
MOY
CMP
JE
eX,BX
AL j 1
AH, C;RT_MODE
AH,7
ENTRY_2
; ZERO
: MONOCHROME ALJ:'HA CHAR GEN
j GET CURRENT MODE
; I SIT MONOCHROME
J 9X14 fONT
GET COLUMN COUNT
ZERO HI CH BYTE
STORE COLUMN VALUE
: GET ROW VALUE
STORE ROW VALUE
GET PAGE SIZE
STORE PAGE LENGTH
IBM Enhanced Graphics Adapter 125
OFAl
OFA5
60 Fe 03
72 02
DFAC
80 02
OfAE
OfAE
2773
77 35
OFA7
OFAA
E8 OE9A R
OFBl
E8 lEAE R
[8 OCFE R
OFB4
SA 26 0449 R
orBS
orBB
OFBD
80 Fe 07
74 03
2785
2786
2787
2788
EB 10 90
OFCO
OFCO
OfC3
OfC6
BD 0000 E
OFC6
OFC7
OE
07
OFCC
DB 02
OFca
OFCE
OFDO
om3
OF04
OFo7
OFDA
OFDC
OFDC
OFDF
OfE2
OFE5
OFE8
OFED
OfEF
OFf5
OFf5
OHA
OFFC
OffE
1003
1005
1005
1009
100C
100F
10'1
1013
1015
1018
1018
1016
1010
10lF
1023
1025
1026
1028
1028
1029
102C
102E
1031
1035
1038
103C
103F
1043
1046
1047
1047
1049
1049
1040
1050
1053
1055
1057
1059
105C
105C
105F
1061
1063
1061
1069
106A
106C
106C
106F
1013
1077
1076
101f
1083
1084
1086
1089
108B
108C
1090
1092
1094
1096
1099
1099
109C
10Al
lOA3
10A6
10A9
10AB
lOAD
lOBO
10B3
10B5
10BA
10BC
lOBE
lOBE
BB OEOO
2789
2790
74,oc
89 0001
45
E8 1EF6 R
83 C5 OE
EB EA
£8 ODAB R
E8 OE55 R
£8 OE96 R
80
77
74
80
76
OCFE R
3E 0449 R Of
06
06 OlOC R 0000 E
3E 0449 R 07
09
4B
3E 0449 R 03
44
C4 lE 04A8 R
83 C3 OC
26: C4 lF
8C CO
OB C3
74 32
BE 0007
26: 8A 00
3C FF
74 7A
3A 06 0449 R
74 03
46
EB FO
FA
26: 8A 07
fE C8
A2 0484 R
26: 86 47 01
A3 0485 R
26: 86 47 03
A3 OlOC R
26: 86 47 05
A3 OlOE R
FB
EB 50
C4 lE 04A8 R
83 C3 08
26: C4 I f
8C CO
06 C3
74 40
BE 0006
26: 8A 00
3c FF
74 36
3A 06 0449 R
14 03
46
E6 fO
26:
26:
26:
26:
26:
26:
CMP
JA
8A
8A
8B
8B
8B
8E
27
47
4f
57
6F
47
01
02
04
06
08
53
88 08
B8 1110
CD 10
5B
26: 8A 47 OA
3C FF
74 05
FE C8
A2 0484 R
E8 OCFE R
80 3E 0449 R 07
71 lE
BB 10ce R
AO 0449 R
2A E4
03 08
2E: 8A 07
A2 0465 R
BO 30
80 3E 0449 R 06
75 02
BO 3F
A2 0466 R
JC
~~~~y~~T
AL,2
; COLOR ALPHA CHAR GEN
CALL
CALL
CH_GEN
; LOAD ALPHA CHAR GEN
MOV
CMP
JE
JMP
AH,CRT_MOOE
ENTRY_2:
005
AH,7
FOG_IT
ENTRY_'
; GET CURRENT MODE
IS I T MONOCHROME
; 9X14 fONT
FOG IT:
-
MOV
MOV
SP, OffSET CGHN_FoG
PUSH
POP
MOV
OR
JZ
MOV
ING
CALL
ADO
JMP
CS
ES
CALL
CALL
CALL
SET_REGS
BLANK
PH_5
ASSUME
CALL
DS:ABSO
aX,OEOOH
; TABLE POINTER
; 14 BYTES PER CHAR
FOG:
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2812
2873
2814
2815
2876
2877
2818
2819
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
AH,03H
ENTRY_,
MOV
CALL
2791
26: 88 56 00
E8
80
72
C7
2774
2775
2776
2777
2778
2779
2780
2781
2182
2783
2784
DX,ES:[BPj
OX,OX
ENTRY_'
eX,l
BP
oO_MAP2
BP,014D
FOG
ENTRY_1 :
GET THE ROM SEGMENT
I NTD ES
GET THE CHAR HEX CODE
ZERO = NO MORE CHARS
NO MORE
DO ONE CHAR AT A TIME
MOVE TO FIRST CODE PO I NT
STORE THE CODE POINT
ADJUST BP TO NEXT CODE
DO ANOTHER
; CLEAR OUT THE BUFFER
ODS
CRT_MODE,OFH
CMP
JB
MOV
MS 1
CMP
JA
JE
GMP
JBE
CRT_MODE, 7
SAVE_GRPH
SAVE_ALPH
CRT_MODE,3
SAVE_ALPH
WORD PTR GRX_SET • OFFSET CGMN
MS_l:
SAVE_GRPH:
LES
AOO
LES
Mav
aR
JZ
Mav
ax, SAVE_PTR
BX,OCH
ax, aWORD 'fTR ES: [BX)
AX,ES
AX,BX
J4J
; JMP AHO_DONE
SI,07H
SG_l :
Mav
CMP
JE
CMP
JE
ING
JMP
AL,ES:[BX][SI}
AL,OFFH
AHO_DONE
AL, CRT_MODE
SG_2
51
SG_l
SO_2:
GLI
Mav
OEG
Mav
MOV
Mav
Mav
MOV
MaV
MOV
STI
AL,6YTE PTR ES: I 6X]
AL
ROWS,AL
AX,WORD PTR ES:[BXJ[l]
POINTS,AX
AX,WORD PTR ES:[BXJ[3]
WORD PTR GRX_SET ,AX
AX,WORD PTR ES:[BXJ[5[
WORD PTR GRX_SET + 2, AX
J4J:
JMP
SHORT AHO_DONE
SAVE_ALPH:
LES
Aao
LES
MOV
OR
JZ
MOV
BX, SAVE_PTR
6X,08H
BX,DWORD PTR ES: I BX]
AX,ES
AX,BX
AHO_DONE
SI,OBH
Mav
GMP
eMP
JE
INC
JMP
AL,ES:(BXllSI]
AL,OffH
AHO_DONE
AL,CRT_MODE
SA_2
51
SA_'
Mav
Mav
MOV
MOV
Mav
Mav
AH, ES: I ax]
AL,ES:IBXj(l]
CX,ES:[BX1!2j
DX,ES:(BXJ[4]
BP,ES:(BX1!6]
ES,ES:(BXJ[e]
SA_l:
Jf
SA_2:
;~-~-~
PUSH
BX
Mav
Mav
I NT
POP
MOV
CMP
JE
DEC
Mav
BX,AX
AX,1"OH
10M
BX
AL,ES:(BX](OAH]
AL,OFFH
AHO_DONE
AL
ROWS,AL
SET THE LOW RAM VALUES FOR COMPATIBILITY {JD8 AND 309 SAVE BYTES)
AHO_DONE:
CALL
ODS
eMP
JA
Mav
Mav
SUB
ADD
MOV
MOV
Mav
eMP
JNE
Mav
CRT_MOOE,7
DNDCS
BX,OfFSET COMPAT_MODE
AL,CRT_MODE
AH,AH
BX,AX
AL,CS:(BX]
CRT_MODE_SET ,AL
AL,030H
CRT_MODE,6
Mav
CRT_PALETTE, AL
DO_PAL:
~~~~~~H
126 IBM Enhanced Graphics Adapter
August 2, 1984
10Cl
10Cl
10C5
10C8
10ca
10CE
8B DE 0460 R
EB 28 90
2C 28 2D 29 2A 2E
IE 29
1000
1000
1003
1005
1007
1009
1009
100B
100F
10El
10E3
10E3
10E4
10E6
10E9
tOEA
10EC
10EE
10EE
10EF
80
75
FE
EB
FO 00
0'"
Cl
OA
FE
3A
72
2A
Cl
OE 0485 R
02
C9
51
2A
80
59
75
FE
CO
F9 10
02
Cl
C3
'" 0004
10EF
10EF
10F1
10F5
10FA
8'"
89
F6
75
OA
OE 0"'60 R
06 0"'87 R 08
33
10FC
10FE
1100
1102
1104
1107
8A
2'"
3C
75
89
EB
C5
60
20
05
lEOO
26
F6
75
80
77
E8
73
80
76
80
06 0487 R 01
1F
3E 0449 R 03
15
OE9A R
10
FO 04
03
C5 05
"09
1109
110E
1110
1115
1117
",A
l11C
111F
1121
1124
1124
1127
1129
112C
112C
112F
112F
1132
80 F9 04
7603
80 Cl 05
E8 1000 R
E8 1135 R
E9 219E R
1135
1135
1139
113B
113E
1140
1142
1145
88
8A
E8
FE
8A
E8
C3
1146
1146
1147
1149
114B
114F
1151
"53
1155
1156
1157
53
88
8A
F6
32
03
01
5B
C3
"57
1157
16 0463 R
C5
0015 R
C4
Cl
0015 R
OS
C4
26 044A R
fF
C3
EO
E8 1150 R
August 2, 1984
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2913
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
DNDCS:
MOY
CX1 CURSOR_MODE
AHI
JMP
LABEL
BYTE
02CH, 028H, 02DH, D29H, 02AH, 02EH
01EH,029H
COMPAT_Mg~E
DB
INCLUDE Vl-,. INC
SUBHl Vl-,.INC
PAGE
C
C
C
C
CAlC_CUR~~~UME
C
CMP
PROC
NEAR
DS:ABSO
CH,O
C
C
C
JNE
INC
JMP
SHORT
C
C
C
C
INC
eL
eMP
JB
g
C
C
C
C
C
C
g~_'
CL, BYTE PTR PO I NTS
g~~gIOUT
SUB
CAlC_OUT~USH
C
C
C
C
C
C
ex
CL,CH
CL,010H
SUB
CMP
PDP
JNE
cx
COMP_4
INC
eL
CHECK FOR FULL HEIGHT
NORMAL CHECK
ADJUST END VALUE
ADJUST FOR EGA REG I STERS
WI LL IT WRAP
NO, ITS OK
EGA METHOD FOR CURSOR END
SAVE CURSOR TYPE VALUE
ENO - START
LOW NIBBLE EQUAL
RESTORE
ADO 1 FOR CORRECT CURSOR
BACK TO CALLER
ENOP
C
~ -SET:CT;;~-----S~T-~~~;~~-T;;E----------------------------------
C
C
;
THIS ROUTINE SETS THE CURSOR VALUE
; INPUT
;
(CX) HAS CURSOR VALUE CH-START LINE, CL-STOP LINE
; OUTPUT
.;
NONE
C
;
e
e
e
e
C
---------------------------------------------------------------EOU
e AH1:
C
ASSUME DS:ABSO
AH,C_CRSR_START
e
MDV
CRTC REG FOR CURSOR SET
C
MOV
CURSOR_MOOE, ex
SAVE IN DATA AREA
e
TEST
INFO,8
EGA ACTIVE BIT
e
JHZ
DO_SET
0=EGA 1=OLD CARDS
e
e ;----- THIS SECTION WILL EMULATE CURSOR OFF ON THE EGA
e
e
MOV
AL,CH
GET START VALUE
e
AND
AL,060H
TURN OFF CURSOR?
e
AL,020H
eMP
TEST THE BITS
e
JNE
SK I P CURSOR Off
e
MOV
~~:O~EOOH
EMULATE CURSOR OFF
e
SHORT DO_SET
JM'
e
e ;----- THIS SECTION: ADJUST THE CURSOR AND TEST FOR ENHANCED OPERATION
C
e
e
TEST
INFO,l
CURSOR EMULATE BIT
e
JHZ
O=EMULATE, 1=VALUE AS-IS
e
CMP
g~'f~~DE,3
POSS I BlE EHULA T I ON
e
JA
NO, SET THE CURSOR TYPE
e
CALL
SEE I F EMULATE MODE
i~~~;DET
e
JHC
NOT EMULAT I NG
CMP
TEST START
e
CH,CUT_OFF
AH1_B
JBE
SKI P ADJUST
e
ADJUST
ADD
CH,5
e
e
e
CMP
CL,CUT_OFF
TEST END
e
AH1_S
JBE
SKI P ADJUST
e
ADD
CL,5
C
; ADJUST END REGISTER
e
CALL
CALC_CURSOR
e
e
CALL
MI.
OUTPUT CX REG
JMP
e
V_RET
RETURN TO CALLER
e
e ; ----- TH I S ROUT I HE OUTPUTS THE ex REG I STER TO THE CRTC REGS NAMED IN AH
e
C M16:
e
MOV
OX, AOOR_6845
ADDRESS REG I STER
e
MOV
DATA
AL,CH
CALL
OUTPUT THE VALUE
e
~~T_OX
INC
NEXT REGISTER
e
MOV
AL,CL
SECOND DATA VALUE
e
CALL
OUT_OX
OUTPUT THE VALUE
e
RET
ALL DONE
e
e
e ; ---------------------------------------------------------------POSITION
e
C
r~~~E~~R~~C~ ~~~~!~iE~A~~U~~E:L~~~ ~~g~N BUFFER
e ~
e ; INPUT
C ;
AX = ROW, COLUMN POSITION
e ; OUTPUT
AX = OFFSET OF CHAR POSITION IN REGEN BUFFER
e ;
e f,OSiTioN--------;~~~----NEA~----------------------------- .. ------e
e
PUSH
BX
; SAVE REG I STER
1
MOV
MeV
C
C
e
e
e
e
e
e
C
e
C
C
e
e
C
C
C
e
e
e
e
e
C
POSITION
;
BX,AX
AL,AH
~g~
:~;~H PTR CRT_COlS
ADD
SAL
POP
RET
AX, BX
AX, 1
BX
ROWS TO AL
DETERMINE BYTES TO ROW
ZERO OUT
ADD I N COLUMN VALUE
2 FOR AlTR I BUTE BYTES
RESTORE REG I STER
*
ENDP
-_ .. _--------------_ .. _------_ .. __ .. _----------_ .... _----_.-----------
SET_CPOS
SET CURSOR POSITION
THIS ROUTINE SETS THE CURRENT CURSOR POSITION TO THE
NEW X-Y VALUES PASSED
INPUT
OX .. ROW,COLUMN OF NEW CURSOR
: : OUTPUTBH - DISPLAY PAGE OF CURSOR
CURSOR IS SET AT CRTC IF DISPLAY PAGE IS CURRENT
DISPLAY
iH2;------------------------------------------------------------CALL
IBM Enhanced Graphics Adapter 127
'1SA
1150
1150
11SF
1161
1163
1165
1169
1160
116F
1111
1114
1174
E9 219E R
8A CF
32 ED
01 £1
8B Fl
89940450 R
38 3£ 0462 R
7505
8B C2
£8 1115 R
3037
C3
1175
1175
1178
i11A
£81146 R
88 (;8
03 OE 044E R
117E
01 F9
11M
1182
84
11 85
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
ot
E8 1135 R
C3
1166
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
1186
1186
1188
118A
118C
1190
1194
11~5
1196
1197
1198
1199
119A
119B
119C
8A DF
32 FF
01 t:I
8B 97 0450 R
OE 0460 R
SF
sa
5£
3063
3064
3065
3066
3067
3066
3069
3070
3071
S13
58
58
1F
3072
3073
01
3074
3075
50
3076
CF
3071
3078
3019
1190
1190
llAO
11A2
3080
AO 0449 R
3G 07
77 37
3081
3082
3083
3084
3085
11 A4
l1A9
F6 06 0487 R 02
74 07
3086
3087
3088
3089
llAB
llAO
llAF
3C 07
742C
EB as 90
l1B2
l1B:?
119&
3006
1625
l1B6
CO 42
3090
3091
3092
3093
3094
3095
1186
1188
11M
3096
3097
SF
5E
ilM
liat!
63 e4 06
1F
1113E
l1BF
07
50
llca
3098
3099
3100
3101
g102
3103
3104
3105
3106
]107
3108
ct
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
l1el
l1Cl
l1C7
'1eo
1103
1109
3125
3126
3127
06060707 05 05
040$ 00 00 00 00
0() 05 06 04 04 04
040606040704
07 04
3128
3129
3130
3131
3132
3133
3134
3135
3136
110B
3137
3138
110B
110r
11 E2
11E3
11E5
l1E7
11E9
sa
83
EC
A8
B4
14
E9
16 01163 R
C2 06
3139
3140
3141
04
00
03
1291 R
3142
3143
3144
3145
3146
3147
3148
3149
l1EC
11EC
A8 02
3150
c
e
e
e
e
e
e
e
e
e
e
e
e
e
c
e
c
C
e
e
e
e
e
e
e
e
C
e
JMP
SET_CPOS~OV
SAL
eMP
MOV
AX,DX
CALL
M18
SET CURSOR POSITION, AX HAS ROW/COLUMN FOR CURSOR
M18
PROC
CALL
NEAR
pas IT I ON
CX,AX
eX,CRT_START
MOV
ADD
CALL
RET
M18
;
:,',
; DETERMt NE LOC I N REGEN
; ADO I N THE START ADOR
fOR TH I S PAGE
/ 2 FOR CHAR ONLY COUNT
REG I STER NUMBER FOR CURSOF
SET VALUE TO CRTC
eX,l
AH, C_CRSR_LOC_HGH
H16
SAR
HOV
e
e
e
e
e
e
e
c
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
c
e
c
e
e
e
e
e
e
C
c
ESTABl I SH LOOP COUNT
WORD OFfSET
USE I NOEX REG I STER
SAVE THE PO INTER
SET_CPOS_RETURN
GET ROW/COLUMN TO AX
CURSOR_SET
SET_CPOS_RETURN
RET
;-~~.-
;
;
;
;
;
"17
JNZ
M17:
c
C
CL,BH
CH,CH
CX,l
SI,CX
[SI+OffSET CURSOR_POSNI,OX
ACTIVEJAGE,BH
XOR
MOV
MOV
ENOP
-_ ...... _-_ ............ ...... _.. _--_ ............ __ .. _-----_ ........ _.... --_ .... _--- ------~-
READ_C¥~~~R ROUT I NE
READS THE CURRENT CURSOR VALUE f=ROM
I NPUT MEMORY AND SENDS IT BACK TO THE CALLER
BH -
":, OUTPUT
PAGE OF CURSOR
: ~3~RE~~Lg~~sg~ ~~~ECURRENT CURSOR POS I T ION
iHi;-.. -.. -.... -............. -.. --.. .. -.. ------.. -.. -.. --.... ---..
.... -.... -.. g~
~-
MOV
xoR
------~---
; PAGE VALUE
; ZERO UPPER BYTE
; WORD OFFSET
; GET CURSOR FOR TH I S PAGE
; GET THE CURSOR MOOE
BL, BH
BH,BH
eX.1
DX,I ex + OFFSET CURSOR_POSN I
SAL
HOV
HOV
'OP
POP
'OP
POP
'OP
POP
POP
POP
cx. CURSOR~MODE
01
"ox
; DISCARD CX
; DISCARD OX
AX
AX
OS
ES
BP
IRET
; ........ - READ LIGHT PE:N POSITION
AH4:
MOV
JA
AL,CRT_MODE
AL,07H
REAO_LPEN
TEST
JZ
EGA~I
OMP
I NFO,2
S_COLOR
; ----- MONOCHROME HERE (MONoe BIT 1)
eMP
JE
AL,07H
REAO_.LPEN
OLD_LP
JHP
;---- .. EGA IS COLOR HERE (MONOC BIT 0)
EGA_I S_COLOR:
eMP
J.E
AL,06H
REAO_LPEN
INT
42"
POP
POP
AOD
PoP
POP
c
e
; CALL EX I ST I NG CODE
01
51
SP,6
; DISCARD SAVED BX,eX,DX
OS
"
-"
e
'OP
IRtT
e
e
.. -........ .................. .............. -.. .. .. .. _...................... _-e ; ...... " . ..... -....
LIGHT PEN
e
THIS ROUTINE TESTS THE LIGHT PEN SWITCH AND THE LIGHT
e
e
PEN TitIGOER. Ir ~orH ARE SET, THE LOCATION OF THE LIGHT
e ~,
r~~0~~A~T6~R7~N~fDE~rH£RwISE, A RETURN WITH NO
e
e
ON E:xn
o ,
(AHl '" 0 IF NO LICHT PEN INf'ORMATION IS AVAILABLE
BX, CX, oX ARE: otSTROYED
e ;
e
(AH) '" 1 nH~br~T,/~~W!~ot~~~L~~L~URRENr LIGHT PEN
e :,:
e
POSIT I ON
o
(CH) '" I\ASTE:R POS I T I ON (OLD MODES)
e
l~~l
~
:~~+E~u~~~lr+O~I~~[WH~~?i~~TAL
e ;
...... ...... ........ - ............ _.......... -...... _.... __ _.. _...... _..POSITION
_......
c
e
ASSUME CS: CODE, DS:ABSO
e ;-........ SUBTRACT_TABLE
LABEL
BytE
o V1
Os
OQ6H, 006H, D07H, OD7H, D05H, 005H
; 0-5
e
; 6 .. B
DB
004H, D05H, OOOH, OOOH, OOOH, OOOH
e
; e .. l1
c
DB
0001'1, 005H, 006H,004H, 001lH, 004H
e
DB
001lH, 006H, 006H, OD4H, 007H, 004H
; 12-11
DB
007H,004H
J 18-19
e
e
PROC
NEAR
e
e
e ; .. ~ .. - .. WAIT FOR LIGHT PEN TO BE DEPRESSED
e
e
HOV
OX, ADDR_6845
GET BASE ADDRESS OF 6845
e
ADD
DX 6
PO I NT TO STATUS REG I STER
GET STATUS REGISTER
e
IN
AL,OX
TEst
AL,4
; TEST LIGHT PEN SWITCH
e
e
MOV
AH,O
J SET NO LIGHT PEN RETURN
e
JZ
;
CODE
v.
e
JMP
v6
J NOT SET. RETURN
e
e ;-_ ...... NOW TEST fOR LIGHT PEN TRIGGER
e
C V9:
e
lEST
AL.2
J rEST L I CHi PEN TR I GGER
~
-~-
~~
{........ - --_ -
-- -_
-
- -~
....
-----
j
128 IBM Enhanced Graphics Adapter
August 2, 1984
llEE
75 03
lHO
E9 129B R
lH3
l1F3
84 10
lH5
l1F9
lHB
l1FC
lHD
1HE
llFF
1201
1202
1203
1205
1207
1208
1209
120A
120C
1210
1212
1217
1219
1210
121F
1221
1223
88 16 0463 R
8A 04
4.
,0
EE
EO
SA [8
5.
4A
FE C4
8A C4
EE
42
EC
8A E5
8A lE 0449 R
2A FF
2E: 8A 9F l1Cl R
28 C3
8B 1E 044E R
01 EB
2B C3
79 02
2B CO
1225
1225
1227
122C
122E
1233
Bl 03
80 3E 0449 R 04
72 40
80 3E 0449 R 07
7446
1235
123A
123C
123E
80
77
7S
01
1240
1240
1242
1244
1246
1248
124A
124C
1251
1253
1255
1257
1257
1259
125B
1250
125F
1261
1264
1264
1265
1269
126B
126D
126F
1270
1271
1275
1276
1278
3E 0449 R 06
28
02
f8
B2 28
F6 F2
8A
02
8A
2A
80
75
B1
DO
f8
ED
DC
ff
3E 0449 R 06
04
04
E4
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
316~
3163
3164
3165
3166
3167
3168
3169
3170
3171
3112
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3191
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
321~
52
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3231
3238
3239
3240
99
3241
D3 f3
8A
8A
DO
DO
EB
99
F7
fl8
03
88
04
FO
EE
EE
2C 90
36 044A R
DA
E3
c8
F7 36 0485 R
C
C
C
C
C
C
C
C
C
e
e
e
e
G
C
G
G
C
e
C
e
e
e
e
C
e
e
e
G
C
C
C
C
C
C
e
C
I AX HAS I NPUT VALUE:
BL, CRT_MODI::
BH,8H
BL,CS:V1IBXI
AX,BX
BX,CRT_START
BX,l
AX, ax
MODE VALUE TO ax
AMOUNT TO SUBTRACT
TAKE I T AWAY
SGREEN At:)D~ESs
DiviDE BV 2
ADJUST Tt) ZERO START
IF POSITIVE, GET MOOE
<0 PLAYS AS 0
V2
AX,AX
1-........ DETERMINE MODE OF OPERATION
V2:
CL,3
CRT_MODE,4
MOV
eMP
JB
CMP
JE
V4
CRT_MODE,7
V4
CRT~MODE;
CMP
JA
JNE
SH.
3266
3261
5F
5E
3269
C
"
3270
3271
3272
C
C
Of
3215
i
ALPHA_liEN
06H
VO
VO'
AX,1
VflX;
DL j 40
MOY
OIV
DIVISOR FOR GRAPHICS
ROW(Al) AND GiJLUMN(AH}
AL RANGE 0-99;
AH RANGE 0"'39
DL
,"---" DETERMINE GRAPHIC ROW POSiTION
MOY
CH,AL
CH,CH
BL,AH
BH,BH
CRT_MODE, 6
SAVE ROW VALUE iNCH
*2 FOR EVEN/ODD FIELD
COLUMN VALUE TO BX
*8 FOR MED I UM RES
MEDIUM OR HIGH RES
AOO
MOV
SUB
eMP
JNE
MOV
SAL
V3
NOT~HIGH_RES
CL,4
AH,1
SHL
BX,CL
SH I FT VALUE FOR HIGH RES
COLUMN VALUE *2 FOR HIGH RES
NOT _H I GH_RES
*16 FOR HIGH RES
V3:
; ----- OETERM I NE ALPHA CHAR POSIT ION
DL,AH
DH,AL
DH,1
DH,l
MOV
MOV
SH'
SH.
JMP
;
:
;
;
;
V5
CRT .COLS
AX "" ROW. ox "" COLUMN
BX,OX
SAVE REMA I NOEA.
p[L COLUMN
PEL ROW
SAVE FROM i1lVIDE
PREPARE: TO blVIDE
01YIDE BY BYTES/CHAR
aX,CL
eX,AX
PUSH
CWO
OIV
POP
MOV
JMP
C
G
COLUMN VALUE FOR RETURN
ROW YALUE
DIVJOE BY.4
FOR VALUE: iN 0-24 RANGE
LIGHT_PEtLRETURN_SET
PREPARE TO 0 I V I DE
CWO
DIV
MOV
SAL
MOV
e
e
e
C
e
5A
DETERM I NE MODE
SET *8 SHIFT COUNT
, GRAPH I cs OR ALpHA
i ALPHA_PEN
; - ....... OLD GRAPH I CS MODES
G
129A
129B
129B
129C
1290
12AO
12A1
12A2
12A3
12A4
August 2, 1984
SECOND OAtA REGI aIER
J POINT TO DATA REGISTER
J on THE 2ND DATA VALUE
OX
AL,DX
AH,CH
MOV
SUB
MOV
SUB
MOV
SH.
SUB
JNS
SUB
e
e
e
C
8B 16 0463 R
83 C2 07
EE
3276
,
AL,AH
DX,AL
;----- NEW GRAPHICS MODES
1292
1296
1299
50
; ADDRESS REG I STER
V8:
52
3273
3214
GET THE VALUE
SAVE IN CX
AX
OX
AH
G
8A
flA
32
03
F6
fiB
07
AL,DX
CH,AL
; --_ .... AX HAS THE VALUE READ I N FROM tHE 6845
G
1281
1283
1285
1287
1289
1280
128F
128F
1291
1291
113 C4 06
II OHT PEN REG I STERS
ADDRESS REG I STER
REG I STER TO READ
SET IT UP
DATA REGISTER
OX
AX
C
C
f6 36 044A R
3~68
PUSH
C
C
SA fO
B4 01
ox,
AODlC6845
AL,AH
DX,AL
IN
MOV
POP
OEC
INC
MOV
OUT
INC
IN
MOV
C
1278
127B
D4
DC
Ff
E3
26 0485 R
C8
,
AI-!, 16
MOV
C
C
C
C
C
C
C
C
C
C
C
e
127r
8A FO
EB 15 90
REf URN WITHOUT RESETTING
TRIGGER
EX 1T LI OHT PEN ROUT] NE
INPUT REGS pOiNTED TO BY AH, AND CONVERT Ttl ROW COLUMN IN OX
MOV
MOV
OUT
INC
0
G
V7
__ TRIGGER HAS BEEN SET .. READ THE VALUE 1N
,.. _.. _.
0
C
C
C
C
C
C
C
C
C
C
C
C
C
C
e
e
C
C
C
C
C
C
C
V7A
JMP
V1A:
C
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
5A
;_~M
JNZ
OX
Po I NTS
~~X~X~~ER
OX
DH,AL
V5
ROW
e
G
C
C
C
C
C
C
C
C
C
C
C
C
C
e
; --'--- ALPHA MODE ON LI GHT PEN
V4:
e
e
e
e
C
C
C
(j
C
BYTE PTR CRT_COLS
DH,AL
DL,AH
BL,AH
BH,BH
BX,CL
BYTE PTR PO I NTS
CX,AX
MOV
AH,l
PUSH
DX
MOV
ADO
OUT
DX.At)iJR 6845
POP
OX
V5:
V6:
G
G
G
OIV
MOV
MOV
MOV
XO.
SAL
MUL
MOV
(lX; 7
ox.Al
V11
ALPHA PEN
ROW,COLUMN VALUE
ROWS TO DH
COLS TO DL
COLUMN VALUE
10 BX
LJ GHT rEN iH:TUR~ _SET
INDICATE EYERt~ING SEt
§~e~TRt¥~ft~E~~~~E
IN CASE _
-
0;
POP
POP
ADD
POP
'0'
;
;
;
;
;
;
51
sl>,6
OiSCARD SAVED ex,cx,ox
OS
ES
S.
pOP
I RET
REAO.... lPEN
lSNDfi
IBM Enhanced Graphics Ad.apter 129
12A4
12A4
12A7
A2 0462 R
8B OE 044C R
12AB
lZAC
12AD
98
50
F7 E1
12AF
A3 044E R
1282
1284
1288
12BB
12BD
12BD
12Bf
12BF
12C1
12C4
12C5
12C7
12CB
12CE
8B
8A
80
17
1201
1201
1202
1204
1206
1208
120A
12DB
1200
120F
12DF
12ED
12EO
12ED
12Et
12E2
12E5
12E9
12EA
12EA
12E8
12ED
12EF
12FO
12F1
12F3
12F4
12F5
12F7
12f9
12FA
12FC
12FD
12fE
12FE
12FE
12FF
1300
1303
1307
1308
1308
1309
130B
1300
130E
'30F
1311
1312
1313
1315
1317
1318
131A
131B
131C
131C
13tC
1310
131F
1321
1324
1327
1328
132A
132C
132E
132F
1331
1332
1334
1335
1337
1339
133B
133E
133f
1341
1343
1344
C8
1E 0449 R
F8 07
02
01 F9
84 DC
E8 1135 R
58
01 E3
88 87 0450 R
E8' 175 R
E9 219E R
50
8A
2A
FE
3A
58
75
2A
E6
E5
C4
EO
02
CO
C3
53
lE
E8 OCFE R
8B tE 044A R
If
51
8A CA
2A ED
56
57
F3! A4
5F
5E
03 F3
03 FB
59
E2 EE
5B
C3
53
lE
E8 OCFE R
8B lE 044A R
1F
51
8A CA
2A ED
56
57
F3! A4
5F
5E
2B F3
2B FB
59
E2 EE
5B
C3
52
B6 03
B2 C4
B8 020F
E8 0015 R
5A
2B CO
8A CA
2A ED
57
F3! AA
5F
8A C6
52
86 03
B2 C4
84 02
E8 0015 R
5A
eo H
8A CA
57
F3! AA
3217
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
;-;m:O,sp:PAGE---------sELEcT-AcTlvE-OI5PLAY-PAGE--------------;
THIS ROUTINE SETS THE ACTIVE DISPLAY PAGE, ALLOWING
;
FOR MULTIPLE PAGES OF DISPLAYED VIDEO.
; INPUT
,
Al HAS THE NEW ACTIVE DISPLAY PAGE
; DUTPUT
;
THE CRTC IS RESET TO DISPLAY THAT PAGE
itt;:;------------------------------------------------------------;
;
;
;
;
;
;
;
;
;
SAVE ACT I VE PAGE VALUE
GET SAVED LENGTH OF
REGEN BUfFER
CONVERT AL TO WORD
SAVE PAGE VALUE
DISPLAY PAGE TIMES
REGEN LENGTH
SAVE START ADDRESS FOR
LATER REQU I REMENTS
START ADDRESS TO CX
MOY
MOY
ACT I VE_PAGE, Al
ex, CRT_lEN
CBW
PUSH
MUl
AX
MOV
CRT_START, AX
MOV
MOV
CMP
JA
AOP_'
SAR
CX,1
; ! 2 FOR CRTC HANDL I NG
MOV
CAll
AH, C_STRT_HGH
M16
; REG FOR START ADDRESS
SAL
MOV
CAll
JMP
BX,1
POP
CX
CX,AX
Bl, CRT_MODE
Bl,7
DO NOT DIVIDE BY TWO
8)(
AX,{BX + OFFSET
M18
V_RET
CURSO~POSN]
;
;
;
;
RECOVER PAGE VALUE
*2 FOR WORD OFFSET
GET CURSOR FOR TH I S PAGE
SET THE CURSOR POSITION
SUBHl
INCLUDE VSCROll.INC
SUBHl VSCROll. INC
PAGE
FlTA
PROC
PUSH
MOV
SUB
INC
CMP
POP
JNE
SUB
NEAR
CHECK FOR SCROll COUNT
AH,DH
AH,CH
AH
AH,Al
lOWER ROW
UPPER ROW
NUMBER TO SCROLL
SAME AS REQUESTED
AX
AX
LTA
Al,Al
; YES, SET TO 0 FOR BLANK
PROC
PUSH
ASSUME
PUSH
CAll
MOV
POP
NEAR
BX
oS:A8S0
OS
ODS
8X,CRT_COlS
OS
; MOVE ROWS OF PELS UP
PUSH
CX
SUB
Cl,OL
CH,CH
;
;
;
;
lTA:
FlTA
CRANK
RET
ENoP
; SAVE DATA SEGMENT
; SET DATA SEGMENT
CRANK_A:
MOV
PUSH
PUSH
REP
POP
POP
AOO
AOO
POP
LOOP
POP
CRANK
RET
MOVS8
SAVE MOVE COUNT
COLUMN COUNT
CLEAR HIGH BYTE
SAVE POINTERS
MOVE THAT ROW
RECOVER PO INTERS
01
SI
SI,BX
DI,BX
NEXT ROW
NEXT ROW
REGOVER ROW COUNT
DO MORE
CX
CRANK_A
ax
RETURN TO CAllER
ENOP
CRANK_4 ~~~
ASSUME
PUSH
CALL
MOV
POP
CRANILB:
81
01
NEAR
; MOVE ROWS OF PELS DOWN
DS:A8S0
OS
DDS
BX, CRT_COlS
OS
; SAVE DATA SEGMENT
; SET DATA SEGMENT
ax
PUSH
CX
SUB
Cl,DL
CH,CH
SI
MOV
PUSH
PUSH
REP
POP
POP
SUB
SUB
POP
lOOP
POP
RET
;
;
;
;
SAVE MOVE COUNT
COLUMN COUNT
CLEAR HIGH BYTE
SAVE POINTERS
01
MOVSB
01
SI
SI,BX
~,BX
CRANK_B
. ax
; MOVE THAT ROW
; RECOVER PO INTERS
;
;
;
;
NEXT ROW
NEXT ROW
RECOVER ROW COUNT
DO MORE
; RETURN TO CALLER
CRANK_4 ENDP
PART_'
PROC
PUSH
MOV
MOV
MOV
CALL
POP
SUB
MOV
SUB
PUSH
NEAR
OX
DH,3
Dl,SEQ..ADDR
AX,020FH
g~T_DX
;
AX,AX
; ZERO
; COLUMN COUNT
01
;
;
;
;
Cl,Dl
CH,CH
REP
STOSB
POP
MOV
PUSH
MOV
MOV
MOV
01
CALL
POP
MOV
MOV
PUSH
REP
Al,DH
OX
OH,3
DL,SEQ..AODR
AH,02H
g~T_DX
Al,OFFH
Cl,Ol
01
STOSB
130 mM Enhanced Graphics Adapter
FilL ROW AFTER SCROLL
; SEQUENCER
; MAP MASK
; All MAPS ON
SAVE POINTER
CLEAR ONE ROW OF PELS
RECOVER PO INTER
GET COLOR VALUE
; SEQUENCER
; MAP MASK
; SET TH E COLOR
;
;
;
;
ALL BITS ON
COLUMN COUNT
SAVE POINTER
TURN ON THOSE BITS IN
August 2, 1984
1346
1341
1348
,F
C3
1348
1348
134A
134C
134F
1352
1353
86
82
88
E8
C3
1353
1353
1E
1354
1351
1359
135B
135C
1350
135F
1363
1365
1366
E8
8A
2A
50
52
8B
f7
8B
5A
58
1367
1F
1368
1368
E8 131C R
136B
136C
136F
1373
1374
1375
1377
137A
137B
1E
E8
03
1F
4B
75
E8
C3
137B
1378
03
C4
020F
0015 R
ceFE R
F7
FF
C3
26 0485
R
D8
OCFE R
3E 044A R
Fl
1348 R
1E
137C
137F
1381
1383
1384
1385
1387
138B
1380
138E
C3
F7 26 0485 R
8B D8
5A
58
138F
1F
1390
1390
E8 131C R
1393
1394
1397
139B
139C
1390
139F
13A2
13A3
1E
E8
2B
1F
4B
75
E8
C3
13A3
13A3
13A5
13AB
13AB
13AD
13BO
13B2
13B5
13B5
13B6
13B8
138B
13BO
13BF
13Cl
13C3
13C3
13C6
13C8
13CA
13CC
13CE
13CE
13CF
1301
1301
1304
1306
1308
13DA
130A
'300
13E2
13E4
13E7
13EA
13EB
nEB
E8
8A
2A
50
52
8B
OCFE R
F7
FF
OCFE R
3£ 044A R
Fl
1348 R
DB
8A
E8
80
72
80
74
E9
16EB R
FC 04
06
Fe 07
03
1474 R
53
8B
E8
74
03
8A
2A
Cl
13F2
31
FO
E6
E3
E8
03
03
FE
75
1432 R
F5
FO
CC
F5
R
56
BO 20
£8
03
FE
75
143B R
FO
CB
F7
E8
80
74
AD
OCFf R
3E 0449
07
0465 R
SA 0308
R
07
EE
E9 219E R
August 2, 1984
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3462
3483
3484
3485
3486
3487
3486
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
ENABLED PLANES
RECOVER PO INTER
RETURN TO CALLER
C
POP
RET
ENDP
C
C
C
C
C
C
PROC
MOV
MOV
MOV
CALL
C
C
C
C
C
C
C
C
RET
PROC
PUSH
ASSUME
CALL
MOV
SUB
PUSH
PUSH
MOV
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
513:
DH,BH
BH,BH
AX
OX
MUL
AX,ex
POINTS
MOV
POP
POP
AX
POP
ASSUME
OS
OS: NOTH I NG
BX,AX
OX
,
;
;
;
RET
; RETURN TO CALLER
SUB
PUSH
PUSH
NEAR
OS
DS:A8S0
; BLANK FOR SCROLL DOWN
; SAVE DATA SEGMENT
DDS
DH,BH
BH,BH
;
;
;
;
;
;
;
;
;
AX
OX
AX,BX
POINTS
BX,AX
MOV
MUL
MOV
POP
POP
ox
OS
OS: NOTH I NG
CALL
ASSUME
PUSH
CALL
; BLANK OUT ROW WITH COLOR
;
;
;
;
;
;
SUB
POP
DEC
JNZ
CALL
RET
- -:-:::::-::-::::::~:::-::------
~ -SCROLL~~ r:-:::~ ~:: ::~::
ON THE SCREEN
: : :.
;
INPUT (AH) = CURRENT CRT MODE
(AL) = NUMBER OF ROWS TO SCROLL
(CX) = ROW/COLUMN OF UPPER LEFT CORNER
(OX) = ROW/COLUMN OF LOWER RIGHT CORNER
IBH) = ATTRIBUTE TO BE USED ON BLANKED LINE
; OUTPUT
;
W~._~.
I~~ ~ ~ ~~~~N S~~~~~~
SEGMENT
N014E -- THE REGEN BUFFER · _______
IS MODIFIED
_________________________
· _____ · _________ _
JB
CMP
JE
JMP
CS:CODE# DS:ABSO, ES: NOTHI NG
PROC
NEAR
BL,AL
MK_ES
AH,4
Nl
AH,7
Nl
GRAPHICS_UP
ASSUME
SCROL~UP
MOV
CALL
CMP
Nl:
PUSH
BX
C
C
JZ
ADD
~R~~POSITION
MeV
SUB
N2:
CALL
ADD
ADD
DEC
JNZ
N5:
C
C
C
AX
POP
MDV
C
C
C
Nl0
SI,BP
OI,BP
AH
N2
N3:
AL, •
N4:
C
C
C
C
C
N7
SI,AX
AH,DH
AH,BL
MOV
C
C
C
SAVE SEGMENT
LOW MEMORY SEGMENT
NEXT ROW
RECOVER
NEXT
DO MORE
; RETURN TO CALLER
ENoP
CALL
C
GET LOW MEMORY SEGMENT
ATTR I BUTE FOR BLANK LI NE
CLEAR HIGH BYTE
SAVE
SAVE BECAUSE OF MULTI PLY
ROW COUNT
CHARACTER HEIGHT
NET VALUE TO BX
RECOVER
AX
POP
ASSUME
C
C
C
C
C
C
C
C
C
SAVE SEGMENT
LOW MEMORY SEGMENT
NEXT ROW
RECOVER
NEXT
DO MORE
ENOP
BLNIC4 • PROC
PUSH
ASSUME
CALL
MOV
C
C
C
GET LOW MEMORY SEGMENT
ATTRIBUTE FOR BLANK LINE
CLEAR HIGH BYTE
SAVE
SAVE BECAUSE OF MULTI PLY
ROW COUNT
CHARACTER HEIGHT
NET VALUE TO BX
RECOVER
BLANK OUT ROW WITH COLOR
DEC
JNZ
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
;
;
;
;
;
;
;
;
;
DDS
CALL
C
C
C
BLANK FOR SCROLL UP
SAVE DATA SEGMENT
NEAR
OS
DS:ABSO
POP
C
C
C
C
C
C
C
C
C
C
C
C
; SEQUENCER
; MAP MASK, ALL MAPS
, ENABLE THE MAPS
; RETURN TO CALLER
ADD
C
C
C
OH,3
OUT_OX
CALL
ASSUME
PUSH
CALL
C
C
C
C
NEAR
DL, SEQ_ADoR
AX,020FH
EHOP
C
C
C
C
C
C
C
C
C
C
01
N6:
CALL
N11
ADD
DEC
JNZ
BL
N4
OI#BP
CALL
DDS
CMP
JE
CRT_MODE,7
N6
MOV
MOV
Al,CRT_MOoE..SET
OUT
OX,AL
JMP
V_RET
oX,D3DSH
SAVE LI NE COUNT IN BL
TEST fOR GRAPH I CS MODE
HANDLE SEPERATELY
TEST FOR BW CARD
;
;
;
;
;
,
UP_CONTINUE
SAVE fiLL ATTR IN BH
UPPER LEFT POSITION
DO SETUP FOR SCROLL
BLANK_F I ELD
FROM ADDRESS
; # ROWS I N BLOCK
; # ROWS TO BE MOVED
; ROW_LOOP
; MOVE ONE ROW
;
;
;
;
;
•
;
;
,
;
;
;
NEXT LINE IN BLOCK
COUNT OF LINES TO MOVE
ROW_LOOP
CLEAR_ENTRY
RECOVER ATTR I BUTE IN AH
FILL WITH BLANKS
CLEAR_LOOP
CLEAR THE ROW
POINT TO NEXT LINE
LI NES TO SCROLL
CLEAR_LOOP
SCROLL_END
, IS THIS THE B/W CARD
; SKI P THE MODE RESET
; GET THE MODE SET
; ALWAYS SET COLOR CARD
; VIDEO_RET_HERE
IBM Enhanced Graphics Adapter 131
BEE
13EE
13FO
13F2
13F2
13F2
13F7
13F9
13FA
13FC
13FE
13FF
13FF
1400
1402
1404
1406
1408
1409
140A
140B
140B
140E
1412
1414
1416
1418
141A
141C
141E
1422
1424
1426
142A
142C
1420
142E
1431
1432
1432
1432
1434
1435
1436
1438
1439
143A
143B
143B
143B
1430
143E
1440
1441
1442
1442
1442
1443
1445
1448
1449
1448
144E
1450
1452
1454
1456
1456
1459
1458
1450
145F
1461
1461
1462
1464
1464
1467
1469
146B
1460
1410
1470
1412
1474
SA DE
EB DC
F6 06 0481 R 04
14 12
52
B6 03
B2 DA
50
EC
A8
74
BO
B2
EE
58
5A
E8
03
8B
86
2B
FE
FE
32
86
03
8A
F6
03
06
1F
80
C3
08
FB
25
08
1146 R
06 044E R
F8
FO
01
C6
C2
ED
2E 044A R
EO
C3
26 044A R
CO
F8 00
8A CA
56
51
F3j A5
5F
5E
C3
8A CA
57
F3j AB
5F
C3
FD
8A
E8
53
8B
E8
14
28
8A
2A
E8
28
28
FE
15
08
16E8 R
C2
13F2 R
20
FO
E6
E3
1432 R
F5
FD
CC
F5
58
BO 20
E8
2B
FE
75
E9
1438 R
FO
CB
F7
13DA R
8A DE
E6 ED
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3541
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
C
C
BL,OH
C
C
~~N ~O~ t a~eNT
N3
GO CLEAR THAT AREA
ENDP
N7:
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
;.---- HANDLE COMMON SCROLL SET UP HERE
SCROLL_pas I T ION PROC
TEST
INFO,4
JZ
N9
; ----- 80X25 COLOR CARD SCROLL
N10
N1D
Nll
C
C
C
C
C
C
C
CH,CH
SP,CRT_COLS
SP, BP
Al,BL
BYTE PTR CRT COlS
AX,AX
ES
OS
SL,D
INCREMENT FOR 0 ORIGIN
ZERO HIGH BYTE OF COUNT
NUM OF COLS IN 0 I SPLAY
TIMES 2 FOR ATTR BYTE
GET LINE COUNT
OffSET TO FROM ADDRESS
*2 FOR ATTR I BUTE BYTE
ESTABl I SH ADDRESS I NG
FOR BOTH PO INTERS
a MEANS BLANK FIELD
RETURN WITH FLAGS SET
PROC
MOV
PUSH
PUSH
NEAR
Cl,DL
51
01
MOVSW
01
51
RET
Nl1
;
; GET # Of COLS TO MOVE
, SAVE START ADDRESS
; MOVE THAT LINE ON SCREEN
;
RECOVER ADDRESSES
ENDP
PROC
MOV
PUSH
NEAR
CL,DL
01
STOSW
01
POP
RET
; GET
;
H
COLUMNS TO CLEAR
STORE THE FILL CHARACTER
ENOP
------------------ ------------------.-----------------SCROLL_DOWN
1H I S ROUT I NE MOVES THE CHARACTERS WITH I N A
DEFINED BLOCK DOWN ON THE SCREEN, FILLING THE
TOP LINES WITH A DEFINED CHARACTER
INPUT
(AH)
(AL)
(CX)
(OX)
(BH l
(OS)
(ES)
= CURRENT CRT MODE
""
=
=
=
=
=
NUMBER OF LINES TO SCROLL
UPPER LEFT CORNER OF REGION
LOWER RIGHT CORNER Of REGION
fiLL CHARACTER
DATA SEGMENT
REGEN SEGMENT
OUTPUT
NONE -- SCREEN IS SCROLLED
~~ROLL=~O~;j-----;ROC----NEAR---------------H~~~~-~---~~R_
STD
MOV
CALL
PUSH
MOV
~~ll
BL,AL
MK ES
BXAX, OX
~~~OLLJOS JT I ON
SUB
MOV
SUB
SI,AX
AH,DH
AH, BL
CALL
SUB
SUB
OEC
JNZ
SI,BP
DI.BP
AH
SCROLL DOWN
II NE COUNT TO BL
SAVE ATTRIBUTE IN BH
lOWER RIGHT CORNER
; GET REGEN LOCATION
SI I S fROM ADDRESS
GET TOTAL # ROWS
COUNT TO MOVE I N SCROLL
N13:
N10
; MOVE ONE ROW
N13
N14:
POP
MOV
AX
CALL
SUB
DEC
JNZ
JMP
N11
DI,BP
BL
; RECOVER ATTRIBUTE
IN AH
AL, '
N15:
C
C
DL
XOR
MOV
ADD
MOV
MUL
AOD
PUSH
pOP
CMP
REP
C
C
C
C
C
C
C
CONVERT TO REGEN PO INTER
OFFSET OF ACT I VE PAGE
TO ADDRESS FOR SCROLL
FROM ADDRESS FOR SCROLL
OX = #ROWS, HGOLS
POP
POP
C
C
C
C
C
POSITION
AX, CRT_START
OI,AX
SI,AX
DX,CX
DH
REP
C
C
CALL
ADD
MOV
MOV
SUB
INC
INC
RET
C
C
C
C
OX'" 308
TURN OFF VIDEO
OUR I NG VERT I CAL RETRACE
OX
SCROLL_POS I T I ON ENDP
C
C
C
C
C
WAI T FOR VERT RETRACE
WAI T_O I SP_ENABLE
N9:
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
AL,DX
AL,8
NB
AL,25H
DL,OD8H
DX,AL
AX
TEST
JZ
MOV
MOV
OUT
POP
POP
C
C
C
C
C
C
C
C
C
C
; COLOR CARD HERE
; WAIT_DISP_ENABLE
IN
C
C
C
C
C
C
C
C
DH,3
OL,ODAH
AX
N8:
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
OX
PUSH
MOV
MOV
PUSH
C
C
C
C
C
C
NEAR
N16:
MOV
JMP
SCROLL_DOWN
;
CLEAR ONE ROW
GO TO NEXT ROW
N15
N'
BL,DH
N1'
ENOP
---------------SCROLL UP
--~---------------------------
------------------
THIS ROUTINE SCROLLS UP THE INFORMATION ON THE CRT
ENTRY
CH,CL"" UPPER LEFT CORNER OF REGION TO SCROLL
DH,DL'" LOWER RIGHT CORNER OF REGION TO SCROLL
BOTH Of THE ABOVE ARE IN CHARACTER POSITIONS
BH = fiLL VALUE fOR BLANKED LI NES
Al = # LINES TO SCROLL (AL=O MEANS SLANl( THE ENTIRE
FI ELO)
DS = DATA SEGMENT
132 IBM Enhanced Graphics Adapter
August 2, 1984
147l1.
1474
1476
8A 08
88 C1
1478
147B
E8 16A7 R
8B F8
1470
147F
1483
28 01
81 C2 0101
DO E6
1485
DO E6
1487
148C
60 3E 0449 R 06
73 04
148E
1490
1492
1492
1493
1494
1496
1498
149A
149C
149E
14AO
14A2
14A4
14A6
14A8
14AA
14AA
14AO
14B1
14B5
14B7
14B9
1489
1488
1488
148E
14C2
l4c4
14C6
14C9
14C9
14CB
14CO
DO E2
01 E7
;
£8
81
81
FE
75
ED
E3
[3
20
C3
50
E4
F7
FO
£6
E3
14CO R
EE 1 FBO
EF 1 FBO
CC
F1
8A C7
E8
81
FE
75
£9
14E6 R
EF 1 FBO
CB
F5
219E R
8A DE
EB EC
SA CA
56
57
F3/ A4
5F
5E
Sl C6 2000
81 C7 2000
56
51
8A CA
F3/ A4
5F
5E
C3
14E6
14E6
14E8
14E9
14EB
14EC
14FO
14F1
14F3
14F5
14F6
14F7
8A CA
57
f3/ AA
5F
S1 C7 2000
57
8A CA
F3/ AA
SF
C3
14F7
50
lE
E8
8A
80
1F
58
74
F9
C3
OCFE R
26 0487 R
E4 60
02
F8
C3
August 2, 1984
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
EXIT
NOTHING, THE SCREEN IS SCROLLEO
b~~;Hics=u;-----;~OC----NE~R---------------·---------------------
MOV
MOY
BL,AL
AX,CX
• SAVE LINE COUNT IN BL
; GET UPPER LEFT POSITION
;
INTO AX REG
; ----- USE CHARACTER SUBROUT I NE FOR POS I T I ON I NG
;----- ADDRESS RETURNED IS MULTIPLIED BY 2 FROM CORRECT VALUE
CALL
MOV
GRAPHJOSN
OI,AX
SAVE RESULT AS
DEST I NAT I ON ADDRESS
;----- DETERMINE SIZE OF WINDOW
SUB
ADO
SAL
OX,CX
OX,101H
OH,1
SAL
DH,1
ADJUST VALUES
MULTIPLY H ROWS BY 4
SINCE 8 VERT DOTS/CHAR
AND EVEN/ODD ROWS
;----- DETERMINE CRT MODE
TEST FOR MED IUM RES
F I NO_SOURCE
CMP
JNC
;----- MEDIUM RES UP
• 2,
OL,l
01,1
SAL
SAL
SINCE 2 BYTES/CHAR
;----- DETERMINE THE SOURCE ADDRESS IN THE BUFfER
R7:
3691
06
1F
2A
DO
DO
74
SA
84
f6
8B
03
8A
2A
14CO
14CO
14CF
1400
1401
1403
1404
1405
1409
1400
140E
140F
14E1
14£3
14E4
14£5
14E6
14F7
14F8
14F9
14FC
1500
1503
1504
1505
1507
1508
1509
1509
150A
ES = REGEN SEGMENT
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
PUSH
POP
SUB
SAL
SAL
JZ
MOV
MOV
MUL
MOV
ADD
MOV
SUB
ES
OS
CH,CH
BL,1
BL,1
Rl1
AL,BL
AH,80
AH
SI,OI
SI,AX
AH,OH
AH,BL
~t~Os~g~~~~s
BOTH
PO I NT I NG TO REGEN
o TO HIGH OF COUNT REG
NUMBER OF LI NES *4
IF 0, BLANK ENTIRE FIELD
NUMBER OF LINES IN AL
80 BYTES/ROW
OffSET TO SOURCE
SET UP SOURCE
ADD I N OFFSET TO IT
NUMBER OF ROWS IN FIELD
OETERM I NE NUMBER TO MOVE
;----- LOOP THROUGH, MOVING ONE ROW AT A TIME, BOTH EVEN AND ODD FIELDS
R8:
CALL
SUB
SUB
DEC
JNZ
;-~---
R17
S I, 2000H-80
01,2000H-80
AH
R8
CALL
SUB
C
C
C
C
C
C
; CLEAR_ENTRY
; ATTRIBUTE TO FILL WITH
BL,OH
R9
CLEAR THAT ROW
PO I NT TO NEXT LI NE
NUMBER OF LINES TO FILL
CLEAR.LOOP
BLANK FIELD
SET BLANK COUNT TO
EVERYTH I NG I NFl ELO
CLEAR THE FIELD
ENOP
;----- ROUTINE TO MOVE ONE ROW OF INFORMATION
R17
PROC
MOV
PUSH
PUSH
REP
C
C
POP
POP
ADO
C
C
C
C
ADD
PUSH
PUSH
MOV
REP
POP
POP
RET
R17
NEAR
CL,OL
51
01
MOYSB
01
51
SI,2000H
01,2000H
51
01
CL,OL
MOVS8
01
51
NUM OF BYTES I N THE ROW
SAVE PO INTERS
MOVE THE EVEN FIELD
POINT TO THE ODD FIELD
SAVE THE PO INTERS
COUNT BACK
MOYE THE ODD FIELD
PO I NTERS BACK
RETURN TO CALLER
ENOP
; ----- CLEAR A 51 NGLE ROW
R18
PROC
MOV
PUSH
REP
C
C
POP
ADO
PUSH
MOV
REP
POP
RET
R18
ENOP
~~~~ME
PUSH
PUSH
CALL
MOV
AND
POP
POP
JZ
5TC
C
C
C
C
MIN:
NEAR
CL,OL
01
STOSB
01
0l,2000H
01
CL,OL
STOSB
01
NUMBER OF BYTES IN FIELD
SAVE PO INTER
STORE THE NEW VALUE
POINTER BACK
POINT TO 000 FIELD
FILL THE ODD FIELD
RETURN TO CALLER
MEM_DEl
C
C
C
C
C
C
C
C
C
V_RET
RIO
JMP
GRAPHICS_UP
C
C
C
01,2000H-80
BL
MOV
C
C
C
C
C
C
C
C
C
Rl.
DEC
JNZ
JMP
Rll:
C
C
C
C
C
C
C
C
C
C
C
C
C
C
AL,BH
MOV
C
C
C
NUMBER OF ROWS TO MOVE
CONT I NUE TILL ALL MOVED
R10:
C
C
C
C
C
ROW
MOVE TO NEXT ROW
FILL IN THE VACATED LlNE(S)
R9:
C
C
~g~{g~;
NEAR
OS;ABSO
AX
OS
ODS
AH,INFO
AH,060H
OS
AX
MIN
RET
CLC
RET
IBM Enhanced Graphics Adapter 133
150B
150B
150B
E9 13A3 R
150E
150E
15"
1515
1518
151A
1510
151F
1522
1522
1525
1528
1528
1520
1530
1532
1535
1535
1536
E8 1201 R
8A 26 0449 R
80 FC 07
76 F1
80 FC OD
7317
E9 219E R
SA
BO
80
72
E8
73
BO
AOOO
051'
FC OF
08
14F1 R
03
0501
e,
1536
1536
1537
153A
153C
153D
153F
1541
1542
1546
1549
154A
154C
154E
1552
1554
1556
1557
155B
155F
1561
52
E8 1522 R
8E C2
SA
8A
8B
5'
8A
E8
5B
8B
2B
81
2A
8A
52
F7
F7
8B
03
1563
1564
1565
1566
1568
156A
156C
156E
00
1F
5A
OA
74
8A
2A
2A
1570
1571
1574
1575
1576
1578
157C
157E
157F
E8
50
52
8B
F7
8B
5A
5.
D8
Cl
3E 0462 R
16C6 R
F8
D1
C2 0101
E4
C3
26 0485 R
26 044A R
F7
FO
DB
3F
CE
CB
ED
1E
OCFE R
C1
26 0485 R
C8
1580
1F
1581
1582
1584
1586
1588
1588
1580
1590
1593
1594
52
8B
B6
B2
£8
B2
B8
E8
5A
E8
C5
03
CE
0015 R
C4
020F
OD15 R
1597
1598
1599
159B
1590
159F
15A2
lSA3
15A3
52
40
8B
86
82
E8
5A
C5
03
CE
0015 R
15A6
15A9
lSA9
15A8
15AD
12EO R
E8 1353 R
E9 219E R
8A DE
EB F6
15AD
l~AD
E9 1442 R
15BO
1"580
15B3
1587
15BA
158C
158F
E8
8A
80
76
80
74
1201 R
26 0449 R
FC 03
F1
FC 07
EC
15Cl
15C4
15C6
15C9
15CB
15CD
15CF
15CF
80
73
80
77
B4
CD
FC 00
DC
FC 06
04
07
42
15D2
1502
E9 219E R
Fo
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3198
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3858
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
C
e
HEM_OET ENDP
;----~
SCROLL ACTIVE PAGE UP
SC_2:
AH6:
JMP
SCROLL_UP
ASSUME
CALL
MOV
eMP
JBE
eMP
JAE
JMP
DS:ABSO
FLTA
AH. CRT_MODE
AH.07H
SC_2
AH.ODH
GRAPHICS_UP_2
V_RET
GR_ST_' PROC
MOV
MOV
eMP
JB
CALL
JNe
MOV
VV1:
RET
GR_ST_1 ENDP
GET CURRENT MODE
ANY OF THE OLD MODES
NEW GRAPHICS MODES
NOT A RECOGN I ZED MODE
NEAR
DX.OAOOOH
BP.0511H
AH.OFH
W1
MEM_OET
W1
BP,0501H
REGEN BUFFER
GRAPHICS WRITE MODE
GRAPH I CS WR I TE MODE
C
C GRAPH I CSA~~U~E PROC
NEAR
e
DS:ABSO
e
PUSH
OX
e
CALL
GR_ST_'
SRLOAD ES
e
e+
MOV
ES,DX
POP
e
OX
e
MOV
BL.AL
AX,CX
C
MOV
PUSH
BX
e
MOV
BH.ACTIVE]AGE
e
e
CALL
GR>CPSN
PDP
e
BX
C
MOV
DI,AX
e
SUB
DX,CX
ADD
C
DX,0101H
SUB
e
AH,AH
MOV
e
AL,BL
PUSH
e
OX
MUL
C
POINTS
MUL
CRT_COLS
e
e
MOV
51,01
ADD
e
SI.AX
e
ASSUME DS:NOTHING
e
PUSH
ES
POP
e
OS
POP
e
OX
C
OR
BL.BL
e
JZ
AR9
C
MOV
CL.DH
e
SUB
CL.BL
e
SUB
CH,CH
e
e
ASSUME DS:ABSO
e
PUSH
OS
e
CALL
DDS
c
PUSH
AX
C
PUSH
OX
C
MOV
AX.CX
c
MUL
POINTS
e
MOV
CX.AX
C
POP
DX
e
POP
AX
e
ASSUME OS:NOTHING
e
POP
OS
e
PUSH
e
OX
C
HOV
AX,BP
C
HOV
DH,3
C
HOV
DL.GRAPH_ADDR
C
CALL
OUT_OX
e
HOV
DL.SEQ....ADOR
C
HOV
AX.020FH
C
CALL
OUT_OX
C
POP
OX
C
CALL
CRANK
C
C
PUSH
OX
C
DEC
BP
HOV
AX,BP
e
C
HOV
DH,3
C
MOV
DL, GRAPH_ADDR
C
CALL
OUT_OX
C
POP
OX
C ARlO:
C
CALL
8LNK_3
C
JHP
V_RET
C AR9:
C
MOV
BL.DH
C
JHP
ARlO
C GRAPHICS_UP_2
ENDP
C
C ;----- SCROLL ACTIVE DISPLAY PAGE DOWN
C
C SC_3:
C
JHP
SCROLL_DOWN
C
C AH7:
C
ASSUME DS:ABSO
CALL
FLTA
e
e
HOV
AH,CRT_MOOE
e
CHP
AH,03H
C
JBE
SC_'
C
eMP
AH.07H
e
JE
SC_3
C
e
eHP
AH.ODH
e
JAE
GRAPH I CS_DN_2
e
eHP
AH.06H
C
JA
H_O
e
HOV
AH.07H
e
42H
'NT
C "_0:
e
JHP
V_RET
C
C GRAPH I CS_DN_2
PROC
NEAR
C
STo
134 IBM Enhanced Graphics Adapter
SET SEGMENT. WR I TE MOOf
SET REGEN
NUMBER OF LINES
UPPER LEFT CORNER
; ACT IVE PAGE FOR SCROLL
; ADDRESS I N REGEN
l
;
;
;
;
SET POINTER
DETERMINE WINDOW
ADJUST
ZERO HIGH BYTE
LI NE COUNT
BYTES PER CHARACTER
COLUMNS
SET UP SOURCE INDEX
ADJUST
LINE COUNT
LOW MEMORY SEGMENT
BYTES PER CHAR
SET THE COUNT
GRAPH ICS
SEQUENCER
ENABLE ALL MAPS
SCROLL THE SCREEN
BLANK ENTIRE WINDOW
OLD COLOR ALPHA
MONOCHROME ALPHA
NEW GRAPH I CS MODES
OLD GRAPH I CS MODES
DIRECTION TO DECREMENT
August 2, 1984
1503
1505
1506
1509
150B
150C
150E
15EO
15E1
15E5
15E8
15E9
15EO
8A D8
52
E8 1522 R
15Fl
15F5
15F7
15F9
15FA
15F'E
1602
1604
8E
5A
88
F'E
53
8A
E8
58
28
88
28
81
2A
8A
52
F7
F7
88
28
1606
1607
1608
1609
160B
1600
160F
1611
06
1F
5A
OA
74
8A
2A
2A
15EF
1613
1614
1617
1618
1619
161B
161F
1621
1622
lE
E8
50
52
88
F7
88
SA
58
1623
1F
1624
1625
1627
1629
162B
162E
1630
1633
1636
1637
52
88
B6
82
E8
82
88
E8
5A
E8
163A
163B
163C
163E
1640
1642
1645
16116
1646
16119
164A
1640
164D
16l1F
1651
52
40
8B
86
82
E8
5A
C2
C2
Clf
3E 0462 R
16C6 R
06 044A R
Fa
01
C2 0101
E4
C3
26 0485 R
26 044A R
f7
fO
DB
40
CE
CB
ED
OCFE R
C1
26 0485 R
C8
C5
03
CE
0015 R
e4
020F
0015 R
12FE R
C5
03
CE
0015 R
E8 137B R
FC
£9 219E R
8A DE
EB F5
1651
1651
1653
1655
1657
1659
1650
32 ED
8B fl
01 E6
88 811 0450 R
33 DB
165F
E3 06
1661
1661
1665
1667
1667
166A
166C
1660
1660
1660
1670
1672
1673
1676
1676
1678
167A
167C
167E
1680
1681
1682
8A CF
03 1E 044C R
E2 fA
E8 1146 R
03 08
C3
80 E3 03
8A C3
51
B9 0003
DO EO
DO EO
OA DB
E2 F8
8A Fe
59
C3
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3921
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3936
3939
3940
3941
3942
3943
3944
3945
3946
3941
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3915
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
MOV
C
C
C+
C
C
C
C
CAll
Bl,AL
PUSH
SRLOAD
MOV
POP
MOV
INC
PUSH
MOV
CAll
POP
SUB
MOV
SUB
AOD
SUB
C
C
C
C
C
C
C
C
C
C
MOV
SUB
ASSUME
PUSH
POP
POP
OR
JZ
C
C
MOV
C
C
C
C
C
C
C
C
C
C
C
ASSUME
PUSH
CALL
PUSH
PUSH
SUB
SUB
C
C
C
C
PUSH
C
C
C
C
C
C
C
C
C
C
C
C
C
C
DXR9:
C
C
C
; CALCULATE WI NDOW
; ADJUST COUNT
DX,ex
DX,010'H
AH,AH
DX
POINTS
BYTES PER CHAR
BYTES PER ROW
SI,AX
NOTH ING
os:
ES
DS
DX
SET OS TO
BL,BL
DXR9
CL.DH
CL,BL
SCROLL COUNT
BLANK ENT I RE WI "DOW
THE REGEN SEGMENT
DS:A8S0
OS
005
AX
ox
AX.CX
POINTS
BYTES PER CHAR
ex,AX
ox
AX
DS:NOTHING
OS
ox
MOV
CALL
MOV
DL, GRAPH_ADDR
OUT_OX
DL, SECLADDR
CALL
AX,020FH
g~T_DX
DH,3
POP
CALL
CRANIL4
PUSH
DX
DEC
MOV
BP
CALL
AX,BP
OH,3
DL, GRAPH_ADDR
OUT_OX
POP
DX
MOV
MOV
DXR10:
; ONE SCAN OVERSHOOT
01 ,AX.
AX,BP
MOV
C
C
C
C
BX
AX,CRT_COLS
"OV
MOV
C
C
C
C
C
; ADDRESS I N REGEN
ox
CH,CH
MOV
MUl
"OV
POP
POP
ASSUME
POP
C
; HOV CHAR ROW UP BY ONE
BH.ACTIVE_PAGE
GR>t.PSN
~~;j'jTOLS
MOV
C
C
SET REGEN SEGMENT
ES,DX
ox
AX,OX
AH
AL,BL
PUSH
MUl
MUl
C
C
C
C
C
C
C
LINE COUNT
SAVE LOWER RIGHT
ox
~~_ST_'
CAll
BLNK_4
ClO
JMP
V_RET
MOV
JMP
GRAPH I CS_ON_2
; GRAPHICS
SEQUENCER
E"ABLE ALL MAPS
SCROLL THE SCREEN
BL,OH
DXR10
ENDP
BLANK ENT I RE WINDOW
C
C
SUBTTL
C
C
INCLUDE
VGRW.INC
SUBTTL VGRW. INC
PAGE
C
C
C
C
C
C
C
ASSUME
f I ND_POS IT I 0"
MOV
XOR
MOV
SAL
C
MOV
C
C
C
C
C
C
C
C
C
C
C
XOR
JCXZ
P4:
AOO
lOOP
P5:
CALL
AOD
RET
fiND_POSITION
DS:ABSQ
PROC
NEAR
CL,BH
CH,CH
Sl,ex
SI .. '
AX. I S I + OffSET CURSOR_POSH]
BX,ax
P5
BX,CRT_LEN
P.
;
DISPLAY PAGE TO CX
; MOVE TO S I fOR INDEX
2 fOR WORD OFFSET
; ROW/COLUMN Of THAT PAGE
; SET START ADDRESS TO 0
; NO_PAGE
; PAGE_LOOP
; LENGTH Of BUFFER
; *
; NO_PAGE
; DETERMINE LOC IN REGEN
; ADD TO START OF REGEN
POSITION
ax, AX
ENOP
C'
C
:--------------------------------------------------------
~ ~:. :::::Dr~!~-~~ri~~ ~~P~~D~E~~~T~~
I
2 8 I TS IN BL TO
C
C
g
~
g
~,9-----PROc----NEAR-------------------------------------
C
C
C
C
C
C
BL '" COLOR TO BE USED ( LOW 2 BITS I
EXIT
520:
C
C
C
C
C
C
C
C
S19
~XCOL~L~~T~OIBE USED ( 6 REPLICATIONS Of THE
AND
NOV
PUSH
HOV
BL,3
AL, BL
CX
CX.. 3
SAL
SAL
AL,l
OR
BL,AL
LOOP
520
BH,BL
ISOLATE THE COLOR BITS
COPY TO AL
SAVE REG I STER
NUMBER OF TIMES
AL .. 1
MOV
POP
RET
ex
;
;
..
;
;
;
LEFT SHIFT BY 2
ANOTHER COLOR VERSION
INTO BL
FILL ALL OF BL
FILL UPPER PORTION
REG I STER BACK
; ALL DONE
ENDP
4030
g ~ -EXPAND;~nE:::~~::-~::::-~::-:~~:-~:-::-:::-:::::::----
4032
C;
4031
August 2, 1984
C
C
ALL OF THE BITS, TURNING THE 8 BITS INTO
IBM Enhanced Graphics Adapter 135
1682
1682
1683
1684
1685
1681
168A
168A
168C
168E
1690
1692
1694
1696
1698
169A
52
51
53
2B 02
B9 0001
8B
23
DB
01
01
8B
23
08
08
09
03
EO
E1
DB
09
03
01 E1
169C
73 EC
169E
16AO
16A1
16A2
16A3
16A4
88 C2
58
59
SA
C3
16A4
16A4
16A7
16A7
16A8
16M
16AC
16BO
16B2
16B4
16B6
16B8
16B9
16BA
At 0450 R
53
8B
8A
F6
01
01
2A
03
5B
C3
08
C4
26 044A R
ED
EO
fF
C3
16BA
16BA
16BB
16BO
16Bf
16C1
16c5
16C6
16C6
16C7
16c8
16C9
16CB
16CD
16CF
1601
16D5
16D9
1606
1600
16El
16E3
16E3
16E5
16E7
16E7
16E8
16E9
16EA
16EB
16EB
16EB
16EE
16F2
16F6
16F9
16FB
16fE
16FE
1700
gg~
53
8A
2A
01
8B
5B
OF
FF
(3
81 0450 R
53
51
52
2A ED
8A Cf
8B 08
SA C4
F6 26 044A R
F7 26 0485 R
2A Ff
03 C3
8B lE 044C R
E3 04
03 C3
E2 FC
5A
59
5B
C3
BE
88
81
83
75
B800
3E 0410 R
E7 0030
Ff 30
03
BE BODO
8E C6
C3
E~
1704
1707
16[8 R
E8 1.651 R
8B F3
1 709
1700
~B 1.6 0463 R
83 C2 d6
1710
F6
iJ6 0467
R 04
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4Q79
/.j080
4081
4082
4083
4084
4085
4086
4087
4068
4069
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4"1
4112
4113
4114
4115
4116
4117
4118
4119
412Q
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
e
~ ~ ~§
e ; -READ=A~; ?~R=~~~~:: -:::::-~:: -: ~~: ~ ::~: -:::-:::~~:~:: ---
4136
4137
413~
4139
41'tO
4141
4142
4143
4144
4145
4146
4141
4148
4,49
4150
4151
4152
4153
4154
4155
4156
4157
4158
e
e
e
e
e
e
e
e
e
e
e
e
16 BITS. THE RESULT IS LEFT IN AX
~2;-----PRO;;----~EAR-------------------------------------
e
e
C
S21
S26
e
e
e
e
e
e
e
e
e
e
e
e
e
S26
~
522
MOV
POP
POP
POP
AX,DX
BX
ex
ox
RET
RECOVER REG I STERS
; ALL DONE
ENOP
PROC
MOV
NEAR
AX, CURSOR_POSN
LABEL
NEAR
; GET CURRENT CURSOR
SAVE REG I STER
SAVE A COPY Of CURSOR
GET ROWS TO AL
MULTI PLY BY BYTES/COLUMN
*4 SINCE 4 ROWS/BYTE
BX
BX,AX
AL,AH
BYTE PTR CRT_eOLS
AX,1
AX,l
BH.6H
AX,BX
BX
, ISOLATE COLUMN VALUE
; DETERMINE OFFSET
; RECOVER POINTER
; ALL DONE
ENDP
6R=CUR;----------------------------------------------------------
;
ASSUME
PUSH
MOV
SUB
SAL
MOV
POP
-~~~;~s~-
OS: ABSO
BX
BL, BH
BH, BH
BX.1
AX, I BX + OFFSET CURSOR_POSN 1
8X
,
;
;
;
SAVE REG I STER
GET TO LOW BYTE
ZERO HIGH BYTE
*2 FOR WORD COUNT
; CURSOR, REQUESTED PAGE
; _RECOVER REG I STER
-------------------------------------------------------
AX '" CURSOR POS I T I ON I N DES I RED PAGE
BH == DES I RED PAGE
EXIT
AX '" BYTE OFFSET I NTO REGEN
6R~=PS~-PROC----NEAR--------------------------------------------PUSH
PUSH
PUSH
SUB
MOV
_
MOV
BX
CX
OX
CH, CH
CL, BH
~M
BX,AX
SAVE
SAVE
SAVE
ZERO
_PAGE NUMBER
ROW, COLUMN
MUL
MUL
SUB
ADD
MOV
JCXZ
BYTE PTR CRT_COlS
PO I NTS
BH, BH
AX, BX
BX,CRT_LEN
GP_2
ROW * COLUMNS/ROW
BYTES PER ROW
ZERO TO LEAVE COL VALUE
ADO I N COLUMN
PAGE LENGTH
NO PAGE OFFSET
ADO
LOOP
AX,BX
GP_3
POP
POP
POP
ox
ex
; ADO I N THE PAGE LENGTH
; 00 FOR NUMBER OF PAGES
RECOVER
RECOVER
RECOVER
BX
RET
GRX_PSN ENOP
MOV
SI,OB800H
OI,EQUiP_FLAG
01,030H
01,030H
P6_A
SI,OBOOOH
MOV
ES,SI
MOV
MOV
AND
eMP
e
e
JNE
e
e
e
e
e
e
RET
e
e
e
e
e
e
C
e
e
e
e
SH I FT BASE AND MASK BY 1
BASE TO TEMP
EXTRACT THE SAME BIT
PUT I NTO RESULT
SHI FT ONLV MASK NOW,
MOV I NG TO NEXT BASE
USE MASK BIT COMING OUT
TO TERMINATE
RESULT TO PARM REGISTER
ENTRY BH == DI SPLAY PAGE:
EXIT
AX == CURSOR POSITION FOR REQUESTED PAGE
;
;
e
e
c
BASE I NTO TEMP
USE MASK TO EXTRACT BIT
PUT I NTO RESULT REG I STER
-GR=CUR ------------ ------------ ---- ------- --- -- ------ -----------
e
e
e
e
e
e
e
e
e
RESULT REG I STER
MASK REG I STER
RET
e
e
e
JNe
ADD
POP
e
C
; SAVE REG I STERS
CX,l
BX,AX
BX,CX
DX,BX
CX,l
MUL
SHL
SHL
SUB
e
e
e
e
e
C
AX,'
MOV
MOV
e
e
e
e
e
e
e
e
e
e
e
e
e
SHL
SHL
GRAPH_PO~~SH
e
e
BX,AX
BX,CX
OX,BX
SHL
e
e
MOV
AND
OR
MOV
AND
OR
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
OX
CX
BX
OX,DX
CX,l
S22:
e
e
e
e
e
e
e
e
C
e
C
e
e
e
e
e
e
e
e
e
e
e
PUSH
PUSH
PUSH
SUB
MOV
,
: INPUT
AT THE CURRENT CURSOR POSITION AND RETURNS THEM
TO THE CALLER
(AH) '" CURRENT CRT MODE
(BH) :::: t11SPLAY PAGE ( ALPHA MODES ONLY)
)
(OS) ::: DATA SEGMENT
; OUTPUT (ES)
REGEN SEGMENT
=
~
;
!:~l ~ ~~~~1:5~~
READ
-------- ----------------------------------------------:;
CS: CODE, OS:ABSO, ES: NOTH i NG
ASSUME
REAO_AC_CURRENT
CALL
CALL
MOV
1II0V
Abo
F'~OC
NEAR
M~_ES
FIND_POSITION
SI,BX
Ox, ADOR_6S45
ox, 6
; ADDRESSING IN 51
; GET BASE ~DORESS
; POINT AT STATUS PORT
INfO.4
136 IBM Enhanced Graphics Adapter
August 2, 1984
1715
1716
06
lF
1717
74 OB
4159
4160
4161
4162
4163
4164
4165
1719
1719
171A
171C
ll1E
171F
171F
1720
1722
EC
A6 01
75 FB
FA
EC
A6 01
74 FB
1724
1724
1725
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
AO
E9 219E R
1726
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
1726
1728
172A
1720
4196
4197
4198
85 C1
F6
1735
74 01
1737
1736
1738
173A
173C
DO
F9
02
01 E9
01 E9
173E
73 F2
17tj.(i
88 56 00
45
1743
1744
1745
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
~~~~
4212
C3
4213
4214
4215
4216
4217
4218
1745
1745
1748
1748
1740
E8
E8
8B
83
1750
8B EC
1752
1757
1758
1759
16EB R
16A4 R
FO
EC 08
80:iE 0449 R 06
06
1J;
72 lA
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
H5B
175D
175D
175F
1762
1763
1767
176A
1768
176E
1770
1772
B6 04
8A 04
88 46 00
45
6A 84 2000
88 46 00
45
63 C6 50
FE CE
75 EB
EB 17 90
1177
01 E6
B6 04
1779
1779
E8 1728 R
177C
61 C6 2000
1780
1783
E8 1726 R
81 EE HBO
FE CE
75 EE
1787
1789
178B
118B
H6C
n8F
1193
1794
1797
1799
lt9A
88 F5
FC
BO 00
179C
179C
1790
4248
4249
179E
BA 0080
HAl
11~1
171\2
sCi
51
August 2, 1984
IN
AL,D~
TEST
JNZ
AL,1
CLI
IN
TEST
JZ
TH I S ROUT I NE WILL TAKE 2 BYTES FROM THE REGEN
BUFFER, COMPARE AGA I NST THE CURRENT FOREGROUND
COLOR, AND PLACE THE CORRESPONDING ON/OFF BIT
PATTERN INTO THE CURRENT POSITION IN THE SAVE
AREA
ENTRY
S I, as '" PO I NTER TO REGEN AREA Of INTEREST
BX '" EXPANDED FOREGROUND COLOR
BP '" POINTER TO SAVE AREA
EXIT
BP I S I NCREMENT AFTER SAVE
~23-----PROC----NEAR----~--------------------------------
MOV
MOV
MOV
AH,(SII
AL, (SI +1 I
CX, OCOOOH
NOV
DL,O
S24:
IS, THIS 8ACKGROUND?
CLEAR CARRY I N HOPES
THAT IT IS
~rs~~ T ~ T sb Ss~~C~~~~~ND
DL,1
eX,1
eX,l
MOVE THAT BIT INTO THE
RESULT
MOVE THE MASK TO THE
RIGHT BY 2 BITS
DO IT AGAIN IF MASK
DIDN'T FALL OUT
STORE RESULT I,N SAVE
ADJUST PO INTER
ALL DONE
STC
C
C
JNC
S2'
C
MOV
IHC
[BPJ,DL
BP
RET
S23
ENDP
C
C
C
C
C
C
C
C
C
C
GRAPHICS_READ
CALL
CALL
MOV
C
;~--~~
C
C
C
C
C
SUB
PROC
MK ES
S26
SI,AX
SP,8
MOV
BP,SP
NEAR
CONVERTED TO OFFSET
SAVE IN SI
ALLOCATE SPACE TO SAVE
THE READ CODE PO I NT
PO I NTER TO SAVE AREA
DETERMINE GRAPHICS MODES
CMP
PUSH
POP
JC
CRT_MODE,6
ES
OS
S13P
PO I NT TO REGEN SEGMENT
MEO I UM RESOLUT I ON
C
HIGH RESOLUTION READ
C
;----~
C
C
;~--~- GET VALUES FROM REGEN BUFFER AND CONVERT TO CODE POINT
C
C
C
C
C
C
C
C
C
C
C
C
C
C
MOV
DH,4
NUMBER OF PASSES
MOV
MOV
IHC
MOV
MOV
INC
ADO
DEC
JHZ
JMP
AL, [SI J
GET FIRST BYTE
SAVE I N STORAGE AREA
NEXT LOCATION
GET LOWER REG I ON BYTE
ADJUST AND STORE
SAL
MOV
Sl,l
DH,4
CALL
S23
ADD
CALL
SI,2000H
S23
4270
4211
4272
C
C
I,.t~
4273
C
SUB
4274
C
C
C
C
t
SUB
S I ,2000H-80
DEC
JHZ
S14P
DH
GET PA I R BYTES
INTO SINGLE SAVE
GO TO LOWER REG I ON.
c
GEl; THIS PAIR INTO SAVE
ADJUST PO I NTER BACK INTO
UPPER
,
kEEP GO I NG UNT I L 8 DONE
;----.:. SAVE AREA HAS CHARACTER IN IT, MATCH IT
PUSH
CALL
eo:p
OS
DDS
_ ,
DI,GRX_SET
BP,8
HOV
ClO
SI,BP
MOV
AL,O
PUSH
POP
NOV
SS
DS
PUSH
51
S17P:
PUSH
ESTABLISH ADDRESSINd
DS
S16P:
C
c
PO I NTER I NTO REGEN
LOOP CONTROL
00 I T SOME MORE
GO MATCH THE SAVED CODE
POINTS
S15P:
C
C
C
C
C
DH
S12P
S15P
S14P:
4265
4266
4267
4266
4269
4275
SI,60
;----- MEDIUM RESOLUTION READ
C
4276
4277
(BPj,AL
BP
AL,[SI+2000Hl
(BP],AL
BP
S13P:
C
C
C
C
C
C
C
C
C
C
C
C
C
C
4279
42$0
428,1
4282
42$3
4284
AX,CX
S25:
C
GET FIRST BYTE
GET SECOND BYTE
2 BIT MASK TO TEST
THE ENTR I ES
RESULT REG I STER
S2,
RCl
SHR
SHe
C
4262
GET THE CHAR/ATTR
i~MEO=REAO=~;TE~---~~~-----------------------------------
C
C
C
C
C
4263
4264
;
LODSW
JMP
V RET
READ_AC_CURRENT ENDP
JZ
4254
4255
4258
4259
4260
4261
AL,DX
AL,l
P3
P3A:
C
C
C
C
WA I T FOR RETRACE LOW
GET STATUS
IS HORZ RETRACE LOW
WAIT UNTIL IT IS
NO MORE INTERRUPTS
WAIT FOR RETRACE HIGH
GET STATUS
IS IT HIGH
WAIT UNTIL IT IS
P2
P3:
TEST
C
C
SEGMENT FOR QU I CK ACCESS
WAIT FOR HORIZONTAL RETRACE
Cle
4253
4256
4257
PlA
C
C
4246
4247
OS
C
4240
4241
4242
4243
4244
4245
4276
16
1F
C
C
C
C
C
C
C
C
C
4250
1775
C
C
C
C
C
C
4238
4239
4251
4252
1775
C
C
C
8A 44 01
89 COOO
;~~-~~
ES
PUSH
POP
JZ
P2:
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
4195
82 00
C
C
C
4188
4189
6A 24
1732
1732
1734
C
4187
4190
4191
4192
4193
4194
1730
C
C
C
C
DX,128
01
ADJUST. POI NfER TO
, ,
8EG I NN I NG OF SAVE AREA
~a~~~~T 0 ~~6~T ~g~ NT
BE I NG
MATCHED
,.,
AOpRESSING TO,.,STACK_
FOR THE STRING COMPA6E
NUMBER TO TEST AGA I NST
~~~ ~~~~ ;~~~f~~iihER
IBM Enhanced Graphics Adapter 13'1
17A3
17A6
17A8
17A9
17M
89 0008
f3/ A6
SF
5E
74 10
17AC
17AE
17Bl
17B2
FE CO
83 C7 08
4A
75 ED
17B4
3C 00
17B6
74 11
17B8
17BB
17BF
17Cl
l7C3
l7C5
17C7
E8
C4
8C
DB
74
BO
EB
17C9
17C9
83 C4 08
17CC
17CF
17Cf
17Cf
OCFE R
3E 007C R
CO
C7
04
80
03
E9 219E R
E9 1701 R
1702
1702
1706
1709
170B
170E
17EO
17E3
17E5
17E8
17E8
17EB
17ED
17fO
17F2
17F4
17F7
17F9
17FB
8A
80
74
80
76
80
26 0449 R
fC 07
F4
FC 03
EF
FC 06
77 03
E9 1745 R
80
72
E8
72
EB
80
73
BO
E9
FC OF
52
14F7 R
40
OA
FC 00
46
00
219E R
17FE
17FE
1801
1803
1806
1808
l80C
BA
8E
£8
8B
8B
2B
l80E
8B EC
1810
1811
1813
1815
1817
1819
1818
1810
181F
1822
1825
1828
1828
1828
1820
1830
1831
1835
1836
1838
1839
la3c
183F
53
24
8A
80
02
84
86
82
E8
88
E8
ADOO
C2
16BA R
FO
lE 0485 R
E3
01
C8
05
EO
07
03
CE
0015 R
0518
0015 R
26: 8A 04
F6 DO
88 46 00
45
03 36 044A R
48
75 fO
58
88 0510
E8 32 90
183F
183F
1842
1844
1847
1849
1840
BA
8E
E8
88
88
28
184F
88 EC
1851
1853
1855
1858
1858
l85C
l65C
185F
1861
1664
1865
1869
186A
ADOO
C2
168A R
FO
1E 0485 R
E3
B6 03
82 CE
88 0508
E8 0015 R
53
26: 8A 04
F6 00
86 46 00
45
03 36 044A R
4B
75 FO
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
431t2
4343
4344
4345
1t346
1t347
431t8
431t9
4350
1t351
4352
1t353
4354
4355
1t356
1t357
4358
4359
1t360
1t361
1t362
4363
4364
4365
4366
4367
11368
4369
4370
4371
4372
4373
1t371t
4375
4376
4377
4376
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410
G
G
G
G
G
G
G
G
G
G
G
C
G
G
MOV
REPE
POP
POP
JZ
ING
ADD
DEG
JNZ
SI
I f ZERO FLAG SET,
THEN MATCH OCCURRED
NO MATCH, MOVE TO NEXT
NEXT CODE PO I NT
LOOP CONTROL
DO ALL OF THEM
S18P
AL
01,8
OX
S17P
;----- CHAR NOT MATCHED, MIGHT BE IN USER SUPPLIED SECOND HALF
GMP
AL,O
JE
S18P
ASSUME
CALL
LES
MOV
DS:ABSO
DDS
DI,EXT_PTR
AX,ES
AX,D!
S16P
AL,128
S16P
C
G
G
G
G
G
G
G
G
G
G
G
G
G
NUMBER Of BYTES TO MATCH
COMPARE THE 8 BYTES
RECOVER THE POINTERS
g~P~B
01
OR
JZ
MDV
JMP
; AL <> 0 IF ONLY 1ST
HALF SCANNED
IF == 0, THEN ALL HAS
BEEN SCANNED
GET POINTER
SEE I F THE PNTR EXISTS
If ALL 0, DOESN'T EXIST
NO SENSE LOOKING
OR I GIN FOR SECOND HALF
GO 8ACK AND TRY FOR IT
; ----- CHARACTER I S FOUND ( AL=O I F NOT FOUND )
C
G
G
G
G
G
G
G
G
G
G
ADD
SP,8
JMP
GRAPH I CS_READ
; READJUST THE STACK,
THROW AWAY SAVE
;
; ALL DONE
; ----- READ CHARACTER/ATTR I BUTE AT CURRENT CURSOR POS I T I ON
AH8S:
JMP
G
G
G
AH8:
C
G
G
G
G
G
G
C
ASSUME
MOV
GMP
JE
GMP
JBE
GMP
JA
JMP
DS:ABSO
AH , CRT_MODE
AH,07H
AH8S
AH,03H
AH8S
AH,06H
GMP
JB
CALL
JG
JMP
GMP
JAE
MOV
JMP
AH,OFH
GRX_RD2
MEM_DET
GRX_R02
SI-fORT GRX_RD1
AH,OOH
GRX R02
AL,a
V_RET
;
GET THE CURRENT MODE
Z_'
GRAPH I CS_READ
G
C
G
G
G
G
G
G
G
G
G
G
G
G
GRX ROl PROC
ASSUME
SRLOAD
G+
MOV
G+
MOV
CALL
G
MOV
G
G
MOV
C
G
G
G
C
C
C
C
C
G
G
G
G
G
G+
c+
G
G
c
c
c
C
G
C
G
G
G
G
G
G
G
G
G
G
G
G
G
G
BP, SP
PUSH
AND
MOV
MOV
SHL
MOV
MOV
MOV
CALL
MOV
CALL
C
G
G
MOV
REGEN SEGEMNT
BYTE OFFSET INTO REGEN
SAVE IN SI
BYTES PER CHARACTER
ALLOCATE SPACE TO SAVE
THE READ CODE PO I NT
PO I NTER TO SAVE AREA
; ----- GET VALUES FROM REGEN BUffER AND CONVERT TO CODE PO I NT
G
G
G
G
G
G
G
G
G
G
G
G
G
G
C
C
SUB
NEAR
DS:ABSO
ES,OAOOOH
OX,OAOOOH
ES,DX
GR CUR
SI-;-AX
BX, POINTS
SP,BX
RANGE TEST
FOUR MAP READ
BX
AL,l
CL,AL
AL,5
AL,CL
AH,G_COLOR
DH,3
DL, GRAPH_ADOR
OUT_OX
AX,518H
OUT_OX
MOV
NOT
MOV
I NG
AOD
DEG
JNZ
POP
MOV
JMP
GRX_R01 ENOP
AL,ES:(Slj
AL
S5: [BPj,AL
BP
GRX_R02 PROC
ASSUME
SRLOAO
MOV
MOV
CALL
MOV
MOV
SUB
NEAR
DS:ABSO
ES,OAOOOH
OX,OAOOOH
ES,DX
GR CUR
SI-;-AX
BX, POI NTS
SP,BX
MOV
BP, SP
~~,CRT_COLS
512 1
BX -
AX,51OH
GRX_RECG
SAVE BYTES PER CHARACTER
ODD OR EVEN BYTE
USE FOR SH I FT
COLOR COMP VALUE (CO-C2)
(Cl-C3) I F ODD BYTE
COLOR COMPARE REG! STER
SET GRAPH I CS CH I P
READ MODE
SET GRAPH! CS CH I P
GET FIRST BYTE
SAVE I N STORAGE AREA
NEXT LOCATION
POI NTER I NTO REGEN
LOOP CONTROL
DO I T SOME MORE
RECOVER BYTES PER CHAR
UNDO READ MODE
CHAR REGONTION ROUTINE
REGEN SEGMENT
BYTE OffSET I NTO REGEN
SAVE IN SI
BYTES PER CHARACTER
ALLOCATE SPACE TO SAVE
THE READ CODE PO I NT
PO I NTER TO SAVE AREA
;----- GET VALUES FROM REGEN BUFFER AND CONVERT TO CODE POINT
MOV
MOV
MOV
CALL
PUSH
DH,3
DL, GRAPH_ADOR
AX,50BH
OUT OX
MOV
NOT
MOV
ING
ADD
DEG
JNZ
AL,E5:(Slj
AL
5S; [BPj,AL
BP
SI,CRT_COlS
BX -
GRAPHICS CHIP
COLOR COMPARE
SET THE REG I STER
SAVE BYTES PER CHARACTER
512:
BX
S'2
138 IBM Enhanced Graphics Adapter
GET COLOR COMPARED BYTE
ADJUST
SAVE I N STORAGE AREA
NEXT LOCAT I ON
PO I NTER I NTO REGEN
LOOP CONTROL
DO I T SOME MORE
August 2, 1984
186C
1860
1870
58
88 0500
1870
1870
1873
1877
E8 0015 R
C4 3E 010C R
28 EB
1879
1878
187C
187E
187F
1880
1883
1883
1884
1885
1887
1889
18BA
1888
8B F5
FC
BO 00
16
1F
6A 0100
1880
188F
1891
1892
1894
1894
1896
56
57
86 CB
F3/ A6
5F
5£
74 07
FE CO
03 FB
4A
75 EF
03 E3
£9 219£ R
1899
1899
189C
18AO
18A3
18A5
18AS
18AA
18AD
18AD
18BO
1882
1883
1884
1887
1889
18BA
l8BB
188F
18C2
18C2
l8C7
18C9
18C9
18CA
l8CC
l8CE
l8CF
18CF
1800
1802
1804
1804
1806
1807
1808
180A
£8 OCFE R
8A 26 0449 R
80 FC 04
72 08
80 FC 07
74 03
£8 74 90
E8
8A
50
51
£8
8B
59
58
88
83
16E8 R
E3
1651 R
FB
16 0463 R
C2 06
F6 06 0487 R 04
74 OB
EC
A8 01
75 FB
FA
EC
A8 01
74 FB
88 C3
A8
F8
E2 [6
E9 219E R
180D
1800
18£0
£8 OCFE R
8A 26 0449 R
18E4
18E7
18E9
18EC
80 FC 04
72 08
80 FC 07
74 03
18EE
18fl
18Fl
EB 30 90
E8 16EB R
August 2, 1984
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
C
C
C
C
C
C
C
C
C
C
j-----
CALL
OUT OX
DI,GRX_SET
BP,BX
LES
SUB
MOV
ClD
MOV
PUSH
POP
MOV
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
SET READ MODE BACK
GET FONT DEFINITIONS
ADJUST POINTER TO
BEG I NN I NG OF SAVE AREA
SI, BP
;
AL,O
SS
DS
OX, 2560
PUSH
PUSH
MOV
REPE
POP
POP
JZ
SI
DI
INC
ADD
DEC
JNZ
Al
DI,BX
ADD
JMP
SP,BX
V_RET
ENSURE 0 I RECT I ON
CODE POINT BEING MATCHED
ADDRESSING TO STACK
FOR THE STR I NG COMPARE
NUM8ER TO TEST AGA I NST
SAVE SAVE AREA PO INTER
SAVE CODE PO INTER
NUMBER OF BYTES TO MATCH
COMPARE THE 8 BYTES
RECOVER THE POINTERS
CX,BX
CMPSB
DI
SI
S18_5
IF ZFL SET, THEN MATCH
OCCURRED
NO MATCH, ON TO NEXT
NEXT CODE POINT
LOOP CONTROL
DO ALL OF THEM
AL"CHAR, 0 I F NOT FOUND
READJUST THE STACK
DX
S17_5
;----- WRITE CHARACTER/ATTRIBUTE AT CURRENT CURSOR POSITION
;-wRi TE~AC~CURRENT ------------------------------TH I 5 ROUT I NE WR I TES THE ATTR I BUTE
AND CHARACTER AT THE CURRENT CURSOR
POS I T I ON
INPUT·
(AH)
(SH)
(CX)
(AL)
(BLI
(OS)
( ES)
C
C
C
C
C
C
C
C
C
C
C
C
C
C
RECO¥ER BYTES PER CHAR
UNDO READ MODE
AX,500H
SAVE AREA HAS CHARACTER IN IT, MATCH IT
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
BX
POP
MO¥
GRX_R02 ENOP
=
"
"
"
"
=
=
CURRENT CRT MODE
DISPLAY PAGE
COUNT OF CHARACTERS TO WRITE
CHAR TO WRITE
ATTR I BUTE OF CHAR TO WR I TE
DATA SEGMENT
REGEN SEGMENT
OUTPUT
NONE
1;;9 ----------------------------------- ---------~
ASSUME
CALL
MDV
OS:ABSO
DDS
AH, CRT_MODE
C
C
C
C
C
C
C
C
C
C
CMP
JC
CMP
JE
JMP
C
MK ES
AH-:-BL
WR I TE~AC_CONT I NUE
GET ATTRIBUTE TO AH
SAVE ON STACK
SAVE WR I TE COUNT
AX
CX
F I NO_pas I T I ON
OI,BX
ADDRESS TO D I REG I STER
WR I TE COUNT
CHARACTER IN BX REG
GET BASE ADDRESS
POINT AT STATUS PORT
CX
BX
ox, ADOR_6845
OX,6
WAIT FOR HORIZONTAL RETRACE
TEST
JZ
INFO,4
P9A
IN
TEST
JNZ
Al,DX
AL,l
P8:
C
C
C
C
C
C
C
C
C
C
C
C
C
C
j
P7:
C
C
C
IS THIS BW CARO
P6
GRAPHICS_WRITE
CAll
MOV
PUSH
PUSH
CALL
MDV
PDP
PDP
MOV
ADD
j-----
IS THIS GRAPHICS
P6
AH,7
P6:
C
C
C
C
C
C
C
C
C
C
C
C
C
AH,4
GET STATUS
IS IT LOW
WAIT UNTIL IT IS
NO MORE INTERRUPTS
PB
ell
P9:
IN
TEST
JZ
AL,DX
AL,l
P9
MOV
STOSW
AX,BX
j
GET STATUS
IS IT HIGH
WAIT UNTIL IT IS
P9A:
STI
lOOP
JMP
j-----
RECOVER THE CHAR/ATTR
PUT THE CHAR(ATTR
I NTERRUPTS BACK ON
AS MANY TIMES
WRITE CHARACTER ONLY AT CURRENT CURSOR POSITION
C
C
C
C
C
C
C
C
C
C
C
C
C
C
WR I TE C CURRENT
~THIS ROUTINE WRITES THE CHARACTER AT
THE CURRENT CURSOR POSITION, ATTRIBUTE
UNCHANGED
INPUT
(AH) " CURRENT CRT MODE
(BH) " DISPLAY PAGE
(CX) " COUNT OF CHARACTERS TO WRITE
(AL) " CHAR TO WRITE
(OS) = DATA SEGMENT
( ES) " REGEN SEGMENT
OUTPUT
NONE
C
C
C
C
C
ASSUME
CALL
MDV
C
C
C
C
C
C
C
C
C
DS:ABSO
DDS
AH, CRT_MODE
CMP
Je
CMP
JE
AH,4
IS THIS GRAPHICS
AH.7
IS THIS BW CARD
JMP
GRAPH I CS_WR I TE
CALL
MK_ES
PlD
PlD
P10:
IBM Enhanced Graphics Adapter 139
18F4
18F5
18F6
18F9
18FB
18FC
18FD
1901
1904
1904
1909
190B
190B
190C
190E
1910
1911
1911
1912
1914
1916
1916
1918
1919
191A
191B
1910
1920
1920
1923
1925
1928
1928
192B
192D
192E
1931
50
51
f8 1651 R
8B FB
59
5B
8B 16 0463 R
83 C2 06
F6 06 0487 R 04
74 OB
fC
A8 01
75 FB
FA
EC
A8 01
74 FB
8A C3
AA
FB
47
E2 E7
[9 2l9E R
80 FC 07
72 03
E9 1901 R
E8 16EB R
B4 00
50
E8 16A4 R
8B F8
1933
1934
1936
58
3C 80
73 06
1938
193C
C5 36 OlOC R
E8 06
193E
193E
1940
1944
1944
1946
1948
194A
194C
1940
1950
1955
1956
1958
1958
1959
195A
195C
195C
1950
1960
1962
1963
1964
1964
1969
196C
196E
1970
2C 80
C5 36 007C R
Dl
01
D1
03
EO
EO
EO
Fa
1E
E8 OCFE R
80 3E 0449 R 06
IF
72 2C
57
56
B6 04
AC
F6 C3 80
75 16
AA
AC
26: 88 85 lFFF
83 C7 4F
FE CE
75 EC
5E
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4510
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
C
C
C
C
C
C
PUSH
PUSH
CALL
AX
CX
; SAVE ON STACK
l SAVE WR I TE COUNT
POP
POP
ex
; ADDRESS TO 0 I
; WR I TE COUNT
; Bl HAS CHAR TO WR I TE
MOV
C
C
C
C
P13:
P13A:
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
AL,DX
AL, ,
P12
IN
TEST
JZ
AL,DX
AL,1
P13
HOV
STOSB
AL,BL
; GET STATUS
; IS IT LOW
; WAIT UNTIL IT IS
i NO MORE INTERRUPTS
; GET STATUS
; IS IT HIGH
; WAIT UNTIL IT IS
RECOVER CHAR
PUT THE CHAR/ATTR
I NTERRU PTS BACK ON
BUMP PO I NTER PAST ATTR
AS REQUESTED
JHP
; -G~APHics-WRi;:E------------------------------------------------THIS ROUTINE WRITES THE ASCII CHARACTER TO THE
;
CURRENT POSITION ON THE SCREEN.
; ENTRV
AL = CHARACTER TO WR ITE
BL = COLOR ATTR I BUTE TO BE USED FOR FOREGROUND COLOR
I F BIT 7 IS SET, THE CHAR IS XOR'D INTO THE REGEN
BUffER (0 IS USED FOR THE BACKGROUND COLOR)
CX = NUMBER OF CHARS TO WRITE
OS = DATA SEGMENT
ES = REGEN SEGMENT
; EXIT
NOTH I NG I S RETURNED
GRAPH I CS READ
THIS ROUTINE READS THE ASCII CHARACTER AT THE CURRENT
CURSOR POSITION ON THE SCREEN BY MATCHING THE DOTS ON
THE SCREEN TO THE CHARACTER GENERATOR CODE PO I NTS
ENTRY
NONE (0 IS ASSUMED AS THE BACKGROUND COLOR)
EXIT
AL = CHARACTER READ AT THAT POSITION (0 RETURNED IF
NONE FOUND)
; FOR COMPATIBILITY ROUTINES, THE IMAGES USED TO FORM CHARS ARE;
CONTAINED IN ROM FOR THE 1ST 128 CHARS.
TO ACCESS CHARS
IN THE SECOND HALF, THE USER MUST INITIALIZE THE VECTOR AT
INTERRUPT lFH (LOCATION 0007CH) TO POINT TO THE USER
SUPPLlEO TABLE OF GRAPHIC IMAGES (8X8 BOXES).
FAILURE TO DO SO WILL CAUSE IN STRANGE RESULTS
;
ASSUME CS: CODE, DS:ABSO, ES: NOTH I NG
GRAPHICSc~~ITE :~?~
NEAR
---------------------------------------------------------------~=P
~~X~WRT
CALL
MOV
PUSH
; 0 TO HIGH OF CODE POINT
; SAVE CODE PO I NT VALUE
;----- DETERMINE POSITION IN REGEN BUFFER TO PUT CODE POINTS
C
CALL
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
IN
TEST
JNZ
CLI
GET BASE ADDRESS
PO I NT AT STATUS PORT
INC
LOOP
C
C
C
C
C
C
INFO,4
P13A
STI
C
C
C
C
C
C
C
ox, ADDR_6845
OX,6
TEST
JZ
P12:
C
C
C
C
C
HOV
ADO
Pl1:
C
C
C
C
C
C
C
C
C
C
C
BX
;----- WAIT FOR HORIZONTAL RETRACE
C
C
C
C
C
C
F I NO_pas IT I ON
OI,BX
MOV
.26
LOC I N REGEN BUFFER
REGEN POINTER IN 01
DI,AX
;----- DETERMINE REGION TO GET CODE POINTS FROM
POP
CMP
JAE
AX
AL,80H
RECOVER CODE PO I NT
, I S IT I N SECOND HALF
; YES
51
IMAGE IS IN FIRST HALF, CONTAINED IN ROM
LOS
JMP
;-----
SI,GRX_SET
SHORT S2
IMAGE IS IN SECOND HALF,
DETERM I NE_MODE
IN USER RAM
S1:
SUB
C
C
LOS
AL,80H
SI,EXT_PTR
C
;----- DETERMINE GRAPHICS MODE IN OPERATION
C
C
S2:
C
C
C
C
C
C
C
C
SAL
SAL
SAL
ADO
PUSH
CALL
AX,l
AX,l
AX,l
SI,AX
OS
CMP
CRT_MODE,6
OS
57
POP
JC
;----- HIGH RESOLUTION HaDE
C
C
53:
C
C
PUSH
PUSH
MOV
01
51
DH,4
54:
LODSB
TEST
JHZ
STOSB
LODSB
S I HAS OFFSET OF
DES I RES CODES
O~S
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
; DETERM I NE_MODE
; MULTIPLY CODE POINT
; VALUE BY 8
BL,80H
56
; TEST FOR MEDIUM RES MODE
~e~-~~~~N
PO INTER
SAVE CODE PO INTER
NUMBER OF TIMES THROUGH
LOOP
GET BYTE FROM CODE PO I NT
SHOULD WE USE THE
FUNCT I ON TO PUT CHAR IN
STORE I N REGEN 8UFFER
55:
MOV
ADO
DEC
JNZ
POP
ES: [0 1+2000H-1 J.AL
01,79
OM
54
STORE I N SECOND HALF
MOVE TO NEXT ROW I N REGEN
DONE WI TH LOOP
51
140 IBM Enhanced Graphics Adapter
August 2, 1984
1971
1972
1973
1975
1978
1978
1978
197C
1970
1982
1984
1984
1986
1988
1988
198B
198C
1980
198F
198F
1990
1993
1995
1998
199A
199D
19A1
19A1
19A4
19A8
19M
19AC
19AE
1981
19B3
19B8
19BO
19BD
19C2
19C7
19CA
19CC
19CE
19CF
1900
1901
1902
1904
1907
5F
47
E2 E3
E9 219E R
26: 32 05
AA
AC
26: 32 85 1 FFF
EB EO
8A 03
01 £7
E8 1660 R
57
56
B6 04
AC
E8 1682 R
23 C3
F6 C2 80
74 07
26: 32 25
26: 32 45 01
26: 88 25
26: 88 45 01
AC
E8 1682 R
23 C3
F6 C2 80
74 OA
26: 32 A5 2000
26: 32 85 2001
26: 88 A.5 2000
26: 88 85 2001
83 C7 50
FE CE
75 Cl
5E
5F
47
47
E2 87
E9 219E R
1907
1907
190A
190C
190F
19E1
19E4
19E6
19E8
19EA
19EA
19EC
19FO
19F1
19F4
19F6
19FA
19FD
19FF
lA03
lA04
1A06
lA08
lA08
lA08
lAOD
lAOF
1A12
1A15
lA18
1A18
1A19
1A18
lA1E
1A21
1A23
1A24
lA26
lA27
lA2A
1A2A
lA28
lA2F
1A30
1A32
lA33
lA34
lA35
lA35
lA37
lA39
lA38
lA3E
lA3F
1A40
lA41
lA43
lA44
lA47
lA48
80 FC OF
72 DE
E8 14F7 R
72 09
80 E3 65
8A E3
DO E4
OA DC
2A
F7
50
E8
8B
88
E4
26 0485 R
16BA R
F8
2E 0485 R
BA
8E
C5
58
03
86
AQOO
C2
36 010C R
F6
74
82
88
E8
E8
C3 80
08
CE
0318
0015 R
lE 90
57
82
88
E8
28
51
88
1E
E8
FO
03
C4
020F
0015 R
CO
CD
OCFE R
AA
03 3E 044A R
4f
E2 F8
lF
59
5f
82
84
8A
E8
57
53
51
88
1E
E8
CII02
C3
0015 R
DO
OCFE R
88 OE 044A R
lF
lA4C
August 2, 1984
4663
4664
4665
4666
4667
4668
4669
4670
4671
4612
4673
4674
4675
4616
4677
4678
11-679
4680
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4100
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4721
4728
4729
4730
4131
4732
4733
4734
4735
4736
4737
4738
4739
4740
"741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
C
POP
C
C
C
INC
01
01
lOOP
JMP
V_RET
C
S6:
XOR
STOSB
lODS8
XOR
JMP
C
C
C
C
C
C
C
C
C
C
C
C
C
C
DL,Bl
01,1
CALL
51'
PUSH
PUSH
MOV
DH,4
S8:
C
C
S11:
loose
CAll
521
AND
AX,BX
TEST
JZ
XOR
XOR
DL,80H
510
AH,ES:[DIJ
Al,ES:IDI+1J
MOV
HOV
Loose
CAll
AND
TEST
JZ
XOR
XOR
C
ADD
DEC
C
C
C
C
POP
C
C
C
INC
INC
C
I.
STORE FIRST BYTE
STORE SECOND BYTE
GET CODE PO I NT
~~;lg:ll~~Al
521
CONVERT TO COLOR
IS THIS XOR FUNCTION
NO, JUST STORE THE VALUE
FUNCT I ON WITH FIRST HALF
AND WITH SECOND HALF
AX,8X
Dl,80H
511
AH, ES; I D I +200DH J
Al, ES: I D 1+2001H J
STORE I N SECOND PORT I ON
POINT TO NEXT LOCATION
KEEP GOING
RECOVER CODE paNTER
RECOVER REGEN PO INTER
PO I NT TO NEXT CHAR
51
01
01
01
lOOP
JMP
GRAPH I CS_WR I TE
58
MED_RES_WRITE
SAVE HIGH COLOR BIT
OFFSET*2, 2 BYTES/CHAR
EXPAND Bl TO FUll WORD
OF COLOR
SAVE REGEN POINTER
SAVE THE CODE POINTER
NUMBER OF lOOPS
eET CODE POINT
DOUBLE UP All THE BITS
CONVERT THEM TO FOREGROUND COLOR (0 BACK)
IS THIS XOR FUNCTION
NO, STORE IT IN AS IT IS
00 FUNCT I ON WITH HALf
AND WITH OTHER HALF
5,
JNZ
POP
C
C
,;
;
;
;
;
;
;
;
ES: [01+2000HJ,AH
ES: [01 +2000H+l J,Al
01,80
DH
MOV
MOV
C
C
C
01
51
S10:
C
C
C
C
; BACK TO MAINSTREAM
S9:
C
C
5,
,; XOR WITH CURRENT
,; STORE THE CODE PO I NT
; AGAIN FOR 000 FIELD
Al, ES: I DI+2000H-l J
SAL
MOV
C
C
C
C
C
I Dt J
S7:
C
C
C
C
C
C
C
C
C
C
Al, ES:
;----- MEDIUM RESOLUTION WRITE
C
C
; RECOVER REGEN PO INTER
; POINT TO NEXT CHAR pas
,; MORE CHARS TO WRITE
53
; MORE TO WR ITE
V_RET
ENDP
-ENTRY-i~-~-~i~~~~:i~~!:::----------·--------------------------
C
C
C
C
C
CX '" COUNT OF CHARS TO WR ITE
bRX=WRj-:~~~::--~~~::::~-::~~:~::::-----------------------------CMP
J8
CAll
C
C
C
C
~~D
C
C
C
C
C
C
C
C
C
C
C+
C+
C
C
C
C
C
85H, XOR C2 CO MASK
AH,8l
AH,1
Bl,AH
SUB
MUL
AH,AH
POINTS
AX
MOV
GR_CUR
DI,AX
BP,POINTS
ES,OAOOOH
DX,OAOOOH
ES,DX
SI,GRX_SET
AX
SI,AX
DH,3
TEST
JZ
MOV
MOV
CAll
JMP
Bl,080H
NO_XOR
OL, GRAPH_ADOR
AX,0318H
OUT_OX
'.2
PUSH
MOV
MOV
CAll
01
Dl, SEILADDR
AX,020FH
OUT_OX
LOS
POP
ADD
EXPAND CO TO Cl, C2 TO C3
BUilD ?(80H) + (O,3,C,n
;
,;
;
;
,
;
;
ZERO
OFFSET FONT TABLE BASE
FONT TABLE DISPLACEMENT
GET OFFSET I NTO REGEN
INTO DESTI NATION
ByTES PER CHAR
REGEN SEGEMNT
; ADDRESS I NG TO FONTS
; RECOVER OF fSET
; CHARACTER I N TABLE
S20A:
NO_XOR:
SUB
PUSH
MOV
PUSH
CALL
AX,AX
ex
CX,BP
; TEST FOR XOR
; NO XOR
GRAPH I CS CH I P XOR
SET REG I STER
SKIP BLANK
BLANK BOX FOR CHAR
SAVE REGEN PO INTER
ENABLE ALL MAPS
; STORE ZERO
; SAVE CHARACTER COUNT
; GET ByTE COUNT
OS
DDS
S13A:
STOSB
ADD
DEC
lOOP
POP
POP
POP
C
C
C
C
C
C
C
HOV
MOV
HOV
CALL
PUSH
PUSH
PUSH
MOV
PUSH
CAll
ASSUME
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
:~~~g~~010'8
MOV
SHl
OR
PUSH
CAll
MOV
HOV
SRlOAO
MOV
MOV
C
C
C
C
BASE CARD
NO_ADJ1 :
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
640X350 GRAPH t cs
AH, OFH
NO_ADJl
MEM_DET
,;
;
;
;
ZERO REGEN 8YTE
NEXT BVTE OF BOX
ADJUST
NEXT BYTE
OS
ex
01
Dl,SEQ_ADOR
AH,02H
Al,8l
OUT_OX
01
BX
CX
8X,BP
OS
MOV
DDS
DS:ABSQ
CX,CRT_COlS
ASSUME
DS:NOTHING
POP
SlK:
OI,CRT_COlS
01
513A
OS
RECOVER CHARACTER COUNT
RECOVER REGEN POINTER
SET MAP MASK
FOR COLOR
SET THE CHIP
SAVE OFFSET I N REGEN
SAVE COLOR VALUE
SAVE CHACTER COUNT
LOOP CONTROL, BYTES/CHAR
SAVE FONT SEGMENT
SET LOW RAM SEGMENT
; GET COLUMN COUNT
; RESTORE FONT SEGMENT
; WRITE OUT THE CHARACTER
mM Enhanced Graphics Adapter 141
lA4C
lA4E
lASl
lAS4
lASS
lAS7
lAS8
8A 04
26: 8A 25
26: 88 05
46
03 F9
4B
75 F2
lASA
lA5B
lA5C
lA5E
lA5F
lA60
59
5B
2B FS
lA62
lA64
lA67
lA6A
lA6C
lA6F
lA72
lA7S
82
B8
E8
82
B8
E8
E9
5F
47
E2 A6
CE
0300
0015 R
C4
020F
0015 R
219E R
lA7S
lA75
lA7A
lA7C
lA81
lAS3
lA85
lA85
lAS8
lAS8
lA8A
lA8C
lA90
lA93
lA96
lA98
lA9A
lA9C
lA90
lA90
lAAO
1AA2
80
74
F6
74
CO
3E 0463 R B4
09
06 0487 R 02
05
42
E9 219E R
2B CO
8B E8
C4 3E 04A8 R
83 C7 04
26: C4 30
8C CO
DB C7
74 01
45
E8 lOCO R
OA FF
75 65
lAA4
lAM
lAA9
lAAB
lAAE
lABO
lAB3
lABS
lAB8
lABA
lABC
lABF
1AC1
lAC4
lAC6
lAC8
lACB
lACE
8A
AD
24
80
OA
A2
8A
80
DO
8A
80
OA
80
8A
DO
80
80
OA
lADO
lAD3
lAD5
AO 0449 R
3C 03
76 OE
lAD7
lAD9
lADB
B4 00
8A C3
E8 109F R
lADE
lAEO
lAE2
OB ED
74 03
26: 88 10
lAE5
lAE5
lAEA
lAEC
1AEF
lAF1
1AF1
1AF3
lAF5
lAF8
lAF8
lAFA
lAFC
lBOO
lBOO
1B02
lB05
1807
80
77
E8
72
FB
0466 R
EO
E3 1 F
C3
0466 R
OF
E7 08
E7
E8
E5 EF
ED
E3 OF
F8
£3
E3 10
E7 07
OF
3E 0449 R 03
05
OE9A R
07
64 11
8A C3
E8 lD9F R
OB ED
74 04
26: 88 50 10
8A
80
S1
02
DO
E3 20
05
EB
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
48'20
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
MOV
MOV
MOV
INC
ADO
DEC
JNZ
POP
POP
SUB
POP
INC
LOOP
MOV
MOV
CAll
MOV
MOV
CALL
JMP
GRX_WRT ENOP
AL,OS:ISlj
CODE POINT
LATCH DATA
WR ITE ONE BYTE OF FONT
NEXT FONT PO I NT
ONE ROW BELOW LAST PO I NT
BYTES PER CHAR COUNTER
DO NEXT ROW OF CHARACTER
~~:f~i\~U
51
OI,CX
BX
SlK
CX
BX
SI, BP
01
01
S20A
;
;
;
;
;
;
Dl, GRAPH_ADDR
AX,0300H
OUT_OX
DL, SEQ_AODR
AX,020FH
OUT_OX
V_RET
CHARACTER COUNT
COLOR VALUE
ADJUST PTR TO FONT TABLE
REGEN PO INTER
NEXT CHAR POSN I N REGEN
WR ITE ANOTHER CHARACTER
NORMAL WR I TE,
SET THE CHI P
NO ROTATE
ENABLE ALL MAPS
SET THE CHI P
SUBTTL
;----- SET COLOR PALETTE
AHB:
ASSUME
CMP
JE
TEST
JZ
INT
DS:ABSO
BYTE PTR AODR_684S,OB4H
M21_B
INFO,2
M21_A
42H
; CALL VAll 0 ONLY FOR COLOR
; SEE I FITS THE OLD COLOR CARD
I F NOT, HANDLE I THERE
; OLD CODE CALL
JMP
V_RET
;
SUB
MOV
LES
ADD
LES
MOV
OR
JZ
INC
AX,AX
CALL
OR
JNZ
PAL INIT
BH,SH
M20
M21_B:
M21_A:
BACK TO CALLER
BP,AX
DI,SAVE_PTR
01,4
DI,OWORD PTR ES:IDlj
AX,ES
AX,OI
NOT4AHB
BP
NOT4AHB:
; ----- HANDLE BH == 0 HERE
ALPHA MODES => BL == OVERSCAN COLOR
"'> BL == OVERSCAN AND BACKGROUND COLOR
GRAPHICS
;----- MOVE INTENSITY BIT FROM 03 TO 04 FOR COMPATIBILITY
MOV
MOV
AND
AND
OR
MOV
MOV
AND
SHL
MOV
AND
OR
AND
MOV
SHL
AND
AND
OR
BH, BL
AL, CRT_PALETTE
AL,OEOH
BL, 01 FH
AL,BL
CRT_PALETTE,AL
BL,BH
BH,08H
BH,1
CH,AL
CH,OEFH
CH, CH
BL.OFH
SH,BL
BL,l
Bl,010H
BH,07H
BL,BH
MOV
CMP
JBE
AL, CRT_MODE
AL,3
M21
; ----- GRAPH I CS MODE DONE HERE (SET PALETTE 0 AND OVERSCAN)
MOV
MOV
CALL
AH,O
AL,BL
PAL_SET
OR
JZ
MOV
BP, BP
M21
ES:(DI],BL
;----- ALPHA MODE DONE HERE (SET OVERSCAN REGISTER)
M21:
CMP
JA
CALL
JC
SET_OVRSC:
MOV
MOV
CALL
CRT_MODE,3
SET OVRSC
BRST DET
SKI P=OVRSC
; CHECK FOR AN ENHANCED MODE
; NO CHANCE
; SEE I F WE ARE ENHANCED
; THERE I S NO BORDER
AH,OllH
AL,BL
PAL_SET
; OVERSCAN REG I STER
;
SET THE BORDER
SKIP~OVRSC:
OR
JZ
MOY
BP, SP
M21Y
ES:(DI )(16Dj,BL
MOV
AND
MOV
SHR
BL,CH
BL,020H
CL,5
BL,CL
M21Y:
HANDLE BH = 1 HERE
ALPHA MODES ==> NO EFFECT
==> LOW 81 T OF BL == 0
GRAPH I CS
PALETl E 0 == BACKGROUND
PALETTE 1 == GREEN
PALETTE 2 '" RED
PALETTE 3 '" BROWN
=> LOW B IT OF BL == 1
PALETTE 0 == BACKGROUND
PALETTE 1 == CYAN
PALETTE 2 == MAGENTA
PALETTE '3 = WH I TE
142 IBM Enhanced Graphics Adapter
August 2, 1984
1809
1809
lBOE
80 3E 0449 R 03
76 4A
1810
1813
lB15
lB18
lB1A
lBle
lBle
lB1F
lB21
lB23
lB25
1B27
1B29
AO
24
80
74
oe
0466 R
OF
E3 01
02
20
A2
24
oe
OA
B4
SA
E8
0466 R
182e
lB2E
1830
lB34
OB ED
74 04
26: 88 50 01
1834
1B36
lB38
lB3A
lB3C
FE
FE
B4
8A
E8
lB3F
lB41
1 B43
1847
DB EO
74 04
26: 88 50 02
1847
lB49
lBilB
lB40
lB4F
10
02
08
01
C3
lD9F R
C3
C3
02
C3
109F R
FE C3
FE C3
84 03
SA C3
E8 lD9F R
lB52
lB54
1 B56
OB ED
74 04
26: 88 50 03
lB5A
1B5A
lB5D
E8 lDB7 R
E9 219E R
lB60
1 B60
1B64
lB65
lB67
1869
186B
lB60
lB6F
1871
lB73
lB77
lB79
lB79
1878
1870
1870
187E
lB80
lB83
lB85
1887
lB88
1888
lB88
lB89
F7
51
al
al
01
26 044A R
E9
E9
E9
03 Cl
8A OF
2A FF
88 CB
88 1E 044C R
E3 04
03 C3
E2 FC
59
8B
80
BO
02
C3
08
El 07
80
E8
53
50
lB8A
lB8C
lB8D
1890
BO 28
52
80 E2 FE
F6 E2
lB92
1893
1896
1898
lB98
1B98
5A
F6 C2 01
74 03
05 2000
1890
lB9E
88 FO
58
88 01
August 2, 1984
H2O:
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4919
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015
501~
5017
5018
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
CMP
JBE
CRT_MODE,3
MBO
MOV
AND
AND
JZ
OR
AL,CRT_PALETTE
AL,OOFH
BL,1
M22
AL,020H
MOV
~~~O~~~ETTE,AL
M22:
AND
OR
OR
MOV
MOV
AL,2
BL,AL
AH,l
Al,BL
PAL_SET
CALL
JZ
MOV
8P,BP
M22Y
ES:[DI][l],BL
INC
INC
MOV
MOV
CALL
BL
BL
AH,2
AL,BL
PAL_SET
OR
JZ
MOV
BP,8P
M27Y
ES: (01 J[2].BL
INC
INC
MOV
MOV
CALL
BL
BL
AH,3
AL, BL
PAL_SET
OR
JZ
MOV
BP, BP
M80
ES:[DIJ[3],BL
OR
M22Y:
M27Y:
M80:
CALL
JMP
e
INCLUDE
vaoT. INC
e
SUBTTL VDOT. I Ne
e
PAGE
e : ----------- ... -----------------------------------e
ENTRY
OX = ROW
e
e
CX = COLUMN
BH = PAGE
e
EXIT
e
BX = OFFSET I NTO REGEN
e
AL = BIT MASK FOR COLUMN BYTE
e
e b~;=;up=~-------PROC----NEAR--------------------e
e
e ; ----- OFFSET'" PAGE OFFSET + ROW * BYTES/ROW + COLUMN/8
e
MUL
e
ROW * BYTES/ROW
~~RD PTR CRT_COlS
PUSH
e
SAVE COLUMN VALUE
SHR
CX,l
e
DIVIDE BY EIGHT TO
SHR
e
CX.1
DETERM I NE THE BYTE THAT
SHR
CX,l
e
THIS DOT IS IN
e
(8 BITS/BYTE)
ADD
AX, ex
e
BYTE OFFSET I NTO PAGE
e
MOV
BL,BH
GET PAGE INTO BL
e
SUB
BH,BH
ZERO
e
MOV
cX,ax
COUNT VALUE
e
MOV
BX,CRT_LEN
LENGTH OF ONE PAGE
e
JeXl
DS_2
PAGE ZERO
e
e
ADD
AX,BX
BUMP TO NEXT PAGE
e
LOOP
DS_3
DO FOR THE REST
e
e
POP
ex
RECOVER COLUMN VALUE
e
MOV
BX,AX
REGEN OFFSET
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
C
e
e
e
e
e
e
e
e
e
ANO
CL,07H
AL,080H
AL,CL
MOV
SH'
RET
DOT_SUP_l
SH I FT COUNT FOR 8 I T MASK
MASK BIT
POSITION MASK BIT
ENOP
; -;iii;-;UBROUTi NE-DET ERM i HE; -TttE-~EGEN-B;TE- ~OCAT i ON ----; OF THE INDICATED ROW COLUMN VALUE IN GRAPHICS MODE.
; ENTRY -;
OX = ROW VALUE (0-1991
;
CX'" COLUMN VALUE (0-639)
; EXIT -;
SI '" OFFSET INTO REGEN BUFFER FOR BYTE OF INTEREST
;
AH = MASK TO STRI P OFF THE BITS OF INTEREST
;
CL'" BITS TO SHIFT TO RIGHT JUSTIFY THE MASK IN AH
;
DH = # 8ITS IN RESULT
k;------PROC----NEAR------------------------------------PUSH
PUSH
BX
AX
SAVE BX DURING OPERATION
WILL SAVE AL DURING OPERATION
;----- DETERMINE 1ST BYTE IN IDICATED ROW BY MULTIPLYING ROW VALUE BY 40
;----- ( LOW BIT OF ROW DETERMINES EVEN/aDO, 80 BYTES/ROW
MOV
PUSH
AND
MUL
AL,40
ox
DL,OFEH
DL
POP
TEST
JZ
ADD
ox
DL,l
R4
AX,20aOH
R4:
MOV
POP
MOV
SI,AX
AX
oX,ex
SAVE ROW VALUE
STR I P OFF ODD/ EVEN BIT
AX HAS ADDRESS OF 1 ST BYTE
OF INDICATED ROW
RECOVER IT
TEST FOR EVEN/ODD
JUMP I F EVEN ROW
OFFSET TO LOCATION OF ODD ROWS
EVEN_ROW
MOVE POINTER TO SI
RECOVER AL VALUE
COLUMN VALUE TO D?(
; ----- DETERM IHE GRAPH I CS MODE CURRENTLY I N EFFECT
; -SET-UP-;HE -REG i ;TERS-ACCORDING-TO -;HE-MODE--------------------CH ;; MASK FOR LOW OF COLUMN ADDRESS ( 7/3 FOR HI GH/MED RES)
IBM Enhanced Graphics Adapter 143
lBAO
lBA3
lBA6
lBAB
1BAD
1 BBO
BB
B9
SO
12
BB
B9
02CO
0302
3E 0449 R 06
06
0180
0103
lBB3
lBB3
lBB5
lBB1
lBB9
03 EA
03 F2
8A F1
lSBB
lBBD
lBBO
2A C9
00 C8
lBBF
lBCT
lBC3
02 CD
FE CF
75 F8
lBC5
lBC7
1 BC9
TBCA
lBCB
8A £3
02 EC
5B
C3
lBCB
lBCB
lBOO
80 3£ 0449 R 07
77 2A
lBD2
1B02
lBD3
1 BD6
lBD8
1 B09
lBOA
lBOB
lBOE
lBEO
lB£2
18£5
1BE6
lBE9
lBEB
lBEO
lBEf
lBFl
lBFl
lBF4
l8F5
lBF8
lBF8
lBFA
TBFC
lBFC
lSFC
lCOl
lC03
1C06
lC08
lCOA
lCOC
lCOE
lClO
lC10
lCll
lCB
lCl6
lC1S
lC1A
lC1C
lCl F
1C20
lC23
lC25
1C26
1C27
1C29
1C2C
lC2E
lC30
lC32
lC35
lC38
lC38
lC3A
lC3C
lC3E
52
SA B800
8E C2
SA
50
50
£8 lB88 R
02 E8
22 C4
26: 8A DC
58
f6 C3 80
75 00
f6 04
22 CC
OA C1
26: 88 04
58
E9 219E R
32 Cl
EB F5
80
72
E8
72
24
8A
DO
OA
50
8B
£8
B6
B2
B4
E8
52
3£ 0449 R Of
00
14F1 R
08
85
EO
E4
C4
C2
1B60 R
03
CE
08
0015 R
BA
8E
5A
58
8A
F6
74
B4
BO
E8
EB
AOOO
C2
E8
C5 80
OA
03
18
0015 R
12 90
B2
B4
BO
E8
C4
02
FF
0015 R
5041
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060
5061
5062
5063
5064
5065
5066
5067
5068
5069
5070
5071
5072
5013
5014
5075
5076
5077
5078
5079
5080
50S1
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105
5106
5101
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166
C
C
C
C
e
e
e
e
e
e
e
e
e
e
C
e
e
e
e
e
e
e
e
e
e
e
C
e
e
C
e
e
e
e
e
e
e
e
e
e
e
e
e
C
e
e
e
e
e
e
,
CL = # OF ADDRESS BITS I N COLUMN VALUE ( 3/2 FOR HIM)
;
BL = MASK TO SELECT BITS fROM POINTED BYTE (BOH/COH FOR HIM)
;
BH = NUMBER OF VALID BITS IN POINTED BYTE ( 1/2 FOR HIM)
• - ----------- - - - - - ----------------- ---------------------- - --- ---MOV
MOV
eMP
Je
MOV
MOV
e
e
e
C
c+
c+
C
C
C
e
C
e
e
e
e
e
e
e
e
C
e
e
e
C
AND
CH,OL
SHR
ADO
MOV
DX,CL
51 ,OX
OH,SH
;----- MULTIPLY BH (VALID BITS IN BYTE) BY CH (BIT OFfSET)
SUB
CL,CL
ROR
AL,l
ADO
DEC
JNZ
CL,CH
BH
MOV
SHR
POP
AH,BL
AH,CL
RET
BX
THESE ROUTINES WILL WRITE A DOT, OR READ THE DOT AT
THE INDICATED LOCATION
ENTRY -OX'" ROW {0-199)
{THE ACTUAL VALUE DEPENDS ON THE MODE)
CX == COLUMN ( 0-639) ( THE VALUES ARE NOT RANGE CHECKED)
AL = DOT VALUE TO WRITE (1,2 OR 4 BITS DEPENOING ON MODE,
REQ'D FOR WRITE DOT ONLY, RIGHT JUSTIFIED)
BIT 1 OF AL=l INDICATES XOR THE VALUE INTO THE LOCATION
OS = DATA SEGMENT
ES = RECEN SEGMENT
.------------------------------------------------------------ ----
;
EXIT
AL = DOT VALUE READ, RIGHT JUSTIFIED, READ ONLY
; ----- WR I TE DOT
AHC:
ASSUME
eMP
JA
WRITE_DOT
ASSUME
PUSH
SRLOAD
MOV
MOV
POP
PUSH
PUSH
CALL
SHR
AND
MOV
POP
TEST
JNZ
NOT
AND
OR
Rl:
MOV
POP
JMP
R2:
OS:ABSO
CRT_MODE,1
WR I TE_DOT_2
PROC
NEAR
OS: ABSO, ES: NOTH I NG
OX
ES,OB800H
DX,OB800H
ES,DX
OX
AX
AX
R3
AL,CL
AL,AH
CL,ES:(Sll
BX
BL,80H
R2
AH
CL,AH
AL,CL
ES: (SI ],AL
AX
C
WRITE DOT 2
~
CMP
PROC
NEAR
CRT _MOOE, 0 FH
NO_ADJ2
MEM_DET
NO_AOJ2
AL,10000101B
AH,AL
AH,l
AL,AH
e
e
C
e
C
C
e
e
e+
e+
C
C
C
C
C
C
e
C
e
e
e
e
e
e
JB
CALL
JC
AND
MOV
SHL
OR
NO ADJ2:
PUSH
MOV
CALL
MOV
MOV
MOV
CALL
PUSH
SRLOAD
MOV
MOV
POP
POP
MOV
TEST
JZ
MOV
MOV
CALL
JMP
MOV
MOV
MOV
CALL
SAVE DOT VALUE
TWICE
DETERMINE BYTE POSITION OF THE DOT
SHIFT TO SET UP THE BITS fOR OUTPUT
STR I P OFf THE OTHER BITS
GET THE CURRENT BYTE
RECOVER XOR FLAG
IS IT ON
YES, XOR THE DOT
SET THE MASK TO REMOVE THE
INDICATED BITS
OR I N THE NEW VALUE OF THOSE BITS
FIN ISH_DOT
RESTORE THE BYTE I N MEMORY
V_RET
R'ENDP
C
C
C
LEFT JUSTIFY THE VALUE
IN AL (FOR WRITE)
AOD I N THE BIT OFFSET VALUE
LOOP CONTROL
ON EXIT. CL HAS SHI FT COUNT
TO RESTORE BITS
GET MASK TO AH
MOVE THE MASK TO CORRECT LOCATION
RECOVER REC
RETURN WITH EVERYTHING SET UP
---------------------------------------------------------------READ DOT -- WRITE DOT
XOR
C
C
; ZERO INTO STORAGE LOCATION
ENOP
R3
;
R6
JMP
WRITE_DOT
C
C
C
C
SH I FT BY CORRECT AMOUNT
I NCREMENT THE PO INTER
GET THE # Of BITS IN RESULT TO DH
R6:
C
e
; ADDRESS OF PEL WITHIN BYTE TO CH
; ----- DETERM I NE BYTE OFFSET FOR TH I S LOCAT I ON I N COLUMN
C
e
e
SET PARMS FOR HIGH RES
R5:
e
e
SET PARMS fOR MED RES
HANDLE I F MED ARES
; ----- DETERM I HE BIT OfFSET I N BYTE FROM COLUMN MASK
e
e
e
e
e
e
e
e
e
e
e
BX.2COH
CX,302H
CRT_MODE, 6
R5
BX,180H
CX,703H
AL,CL
XOR_DOT
EXCLUSIVE OR THE DOTS
FINISH UP THE WRITING
;
BASE CARD
; 85H, XOR C2 CO MASK
EXPAND CO TO Cl, C2 TO C3
BUILD ?(80H) + (0,3,C,F)
AX
AX,OX
OOT_SUP_l
DH,3
OL, GRAPH_AODR
AH,G_BIT_MASK
OUT_OX
OX
ES,OAOOOH
OX,OAOOOH
ES,OX
OX
AX
CH,AL
CH,080H
WD_A
AH,G_OATA_ROT
AL,018H
OUT_OX
WD_B
DL,SECSCAN_LN
OUT_OX
AL
POINTS - 1
R09H
SET THE CHARACTER HE I GHT
POINTS - 2
MOV
MOV
INC
MOV
INT
CH,AL
CL,AL
CL
AH,l
10H
CURSOR START
CURSOR END
ADJUST END
SET C TYPE B t OS CALL
SET THE CURSOR
MOV
MOV
CMP
JA
CALL
JC
MOV
BL,CRT_MODE
AX, 3500
BL,3
H11
BRST_DET
H11
AX, 2000
GET THE CURRENT MODE
MAX SCANS ON SCREEN
640X200 ALPHA MODES
MUST BE 350
CWO
DIV
DEC
MOV
INC
SU8
MUL
DEC
MOV
MOV
CALL
MOV
INC
MUL
SHL
ADD
MOV
CALL
JMP
POINTS
AX
ROWS,AL
AL
AH,AH
POINTS
AX
DX,ADDR_6845
AH, C_VRT_DSP _END
OUT_OX
AL,ROWS
AL
BYTE PTR CRT_COLS
AX,l
AX,2560
CRT_LEN,AX
PH_S
V_RET
HllA:
Hll :
;
---~.
SET LOW MEMORY SEGMENT
GET BYTES/CHARACTER
CRTC REG I STER
SET FOR 200
PREPARE TO DIVIDE
MAX ROWS ON SCREEN
ADJUST
SAVE ROWS
READJUST
CLEAR
ROWS*BYTES/CHAR
ADJUST
CRTC ADDRESS
SCANS 0 I SPLAYED
SET IT
GET CHARACTER ROWS
ADJUST
ROWS*COLUMNS
*2 FOR ALPHA MODE
SPACE BETWEEN PAGES
BYTES PER PAGE
VIDEO ON
RETURN TO CALLER
LOADABLE CHARACTER GENERATOR ROUT I NES
AH11:
AL,010H
AHll_ALPHA1"
CM'
JAE
CHECK PARAMETER
NEXT STAGE
;----- ALPHA MODE ACTIVITY HERE
CM'
JAE
CALL
CALL
CALL
ASSUME
CALL
MOV
MOV
INT
JMP
AL,03H
H1
CH_GEN
SET_REGS
PH_5
DS:ABSO
DDS
CX, CURSOR_MODE
AH,l
10H
V_RET
RANGE CHECK
NEXT STAGE
SET THE CHAR GEN
VIDEO ON
SET THE DATA SEGMENT
GET THE MODE
SET C TYPE
EMULATE CORRECT CURSOR
RETURN TO CALLER
; ----- SET THE CHARACTER GENERATOR BLOCK SELECT REG I STER
H1:
JNE
MOV
MOV
H2
DH,3
DL, SEQ_AODR
NOT IN RANGE
MOV
CALL
AX,1
OUT_OX
AH:=S_RESET, AL"'l
HOV
HOV
CALL
AH,S_CGEN
AL,BL
OUT_OX
CHAR BLOCK REGI STER
GET THE VALUE
SET IT
SEQUENCER
IBM Enhanced Graphics Adapter 149
lFCA
HCO
HOD
HOD
68 0003
E8 0015 R
E9 219E R
H03
H03
H05
3C 20
73 26
1 F07
1 F09
1 FOB
1 FOO
HOE
lFOF
HE2
HE5
lFE6
lFE7
HE9
HEB
HED
lFEF
1Hl
lFF4
lFF6
IH8
lFF8
lFFA
2C
3C
77
50
53
E8
E8
5B
5B
8A
OA
8A
74
BO
80
75
80
10
02
F3
lEAE R
OOAB R
EO
E4
C7
09
08
FC 01
02
DE
2A E4
E9 lF29 R
lFFO
HFO
lFFF
2001
2003
3C
73
2C
75
30
6A
20
11
2005
2007
2009
200A
200E
2012
2013
2013
2016
2B
8E
FA
89
8e
FB
02
OA
2016
52
2017
2019
201B
201C
201E
2020
2022
2024
2025
2026
2028
202A
202U
2030
2032
2032
2035
2038
2038
2039
2030
2041
2B
8E
5A
3C
77
FE
74
OE
07
FE
75
B9
BU
EB
2042
2045
2049
204B
204E
2050
2052
2054
2057
2057
2059
2058
2050
2050
205F
205F
2061
2064
E8
89
8A
B8
OA
75
8A
EB
FE C8
A2 0484 R
E9 219E R
2067
2067
00 OE 19 2B
2E 007C R
06 007E R
E9 219E R
02
OA
03
F3
C8
14
C8
08
OOOE
UUOO E
06
89 0008
BO 0000 E
FA
89 2E 010C R
8C 06 alOE R
FB
OCfE R
DE 0485 R
C3
2067 R
CO
05
C2
09 90
3C 03
76 02
BO 02
2E:
07
206B
206B
2060
206F
206F
2072
2072
2076
207A
2070
207F
2082
3C 30
74 03
8B
8A
80
77
80
77
2084
52
2085
2087
2089
2B 02
8E OA
5A
E9 219E R
OE
16
fF
FO
FF
18
0485 R
0484 R
07
01
5797
5798
5799
5800
5801
5802
5803
5804
5805
5806
5807
5808
5809
5810
5811
5812
5813
5814
5815
5816
5817
5818
5819
5820
5821
5822
5823
5824
5825
5826
5827
5828
5829
5830
5831
5832
5833
5834
5835
5836
5837
5838
5839
5840
5841
5842
5843
5844
5845
5846
5847
5848
5849
5850
5851
5852
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866
5867
5868
5869
5870
5871
58n
5873
5874
5875
5876
5877
5878
5879
5880
5881
5882
5883
5884
5885
5886
5887
5888
5889
5890
5891
5892
5893
5894
5895
5896
5897
5898
5899
5900
5901
5902
5903
5904
5905
5906
5907
5908
5909
5910
5911
5912
5913
5914
5915
5916
5917
5918
5919
5920
592'
5922
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
MOY
CALL
AX,3
OUT_OX
; AH=S_RESET, AL=3
JMP
V_RET
;
H2:
AH11_ALPHA 1 :
ASSUME
eMP
JAE
RETURN TO CALLER
OS:ABSO
AL,020H
AH1'_GRAPHICS
;----- ALPHA MODE ACTIVITY HERE
SUB
eMP
JA
PUSH
PUSH
CALL
CALL
POP
POP
MOY
OR
MOY
JZ
MOY
eMP
JNE
MOY
AL,010H
AL,02H
H2
AX
BX
CH_GEN
SET_REGS
BX
AX
AH,Al
AH,AH
AL, BH
; ADJUST TO 0 - N
RANGE CHECK
1NVALI 0 CALL
SAVE
H13
AL,140
; DO NOT SET BYTES/CHAR
; 8 X 8 FONT
I S THE CALL FOR MONoe
; NO, LEAVE IT AT 8
; MONOC SET
SUB
JMP
AH,AH
BRK_1
; CLEAR UPPER BYTE
; CONTINUE
LOAD THE CHAR GEN
; RESTORE
; CALL I NG PARAMETER
; USER MODE
AL,8
AH,1
H13
H13:
;----- GRAPHICS MODE ACTIVITY HERE
AH11_GRAPHICS:
ASSUME
eMP
JAE
SUB
JNZ
OS:ABSO
AL,030H
AH11 _INFORM
AL,020H
f10
;----- COMPATIBILITY, UPPER HALF GRAPHICS CHARACTER SET
C
e
e
e+
e+
e
e
e
e
e
e
e
e
e
e
e+
e+
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
C
e
e
e
e
e
e
e
e
e
e
e+
e+
e
ASSUME
SRLOAO
SUB
MOY
ell
MOY
MOY
S71
OS:ABSO
OS,O
OX,OX
OS,OX
WORD PTR EXT_PTR , BP
WORD PTR EXT_PTR + 2 ,
ES
F11 :
JMP
V_RET
ASSUME
PUSH
SRLOAO
SUB
MOY
POP
eMP
JA
OEe
JZ
PUSH
POP
OEe
JNZ
MOY
MOY
JMP
OS:ABSO
OX
OS,O
OX,OX
OS,OX
OX
AL,03H
f11
Al
f19
es
ES
Al
f13
CX,140
BP,OFFSET CGMN
SHORT F19
MOY
MOY
CX,8
BP, OFFSET CGDOOT
FlO:
; RANGE CHECK
; ROM 8 X 14 CHARACTER SET
F13:
; ROM 8 X 8 DOUBLE DOT
F19:
ell
MOY
MOY
S71
ASSUME
CALL
MOY
MOY
MOY
OR
JNZ
MaY
JMP
OR_3:
eMP
JBE
MOY
WORD PTR GRX_SET , BP
WORD PTR GRX_SET + 2 ,
ES
OS:ABSO
OOS
pOINTS,CX
AL,BL
ex, OffSET RT
AL,AL
OR 3
AL-:-Ol
OR_'
AL,3
OR 2
AL-:-2
OR_2:
XLAT
CS:RT
OEe
MOY
JMP
Al
ROWS,AL
V_RET
LABEL
OB
BYTE
000,140,250,430
OR_' :
RT
;-----
INFORMATION RETURN DONE HERE
AH11 _INFORM:
ASSUME
eMP
JE
F5:
JMP
F6:
MOY
MOY
eMP
JA
eMP
J'
ASSUME
PUSH
SRLOAD
SUB
MOY
POP
OS:ABSO
AL,030H
F6
V,-RET
CX, POINTS
OL,ROWS
BH,7
F5
BH,l
F7
OS:ABSO
OX
OS,O
OX,DX
OS,DX
OX
150 IBM Enhanced Graphics Adapter
August 2, 1984
208A
208C
208E
2092
2095
2095
2099
OA
75
C4
EB
FF
07
2E 007C R
lA 90
C4 2E OlOC R
EB 13 90
209C
209C
209F
20Al
20A3
20A!)
20A9
20AC
20AD
20AE
20AE
20AF
20BO
20Bl
20B2
2063
20B4
2085
20B6
2087
20B7
20B9
20BB
20BD
80 EF 02
8A OF
2A FF
01 £3
81 C3 20B7 R
2E: 88 2F
OE
07
5F
5E
5B
58
58
1F
58
58
eF
0000
0000
0000
0000
E
E
E
E
20BF
20BF
20C2
20C4
20c6
20C9
20CB
20CE
80
72
74
80
74
E9
20CE
2000
2002
2003
2009
2000
20DE
20E'
20£1
20E5
20E8
2B 02
8A 3E 0487 R
80 E7 02
DO EF
20EA
20EO
20EF
20Ft
20F3
AO
24
B1
02
8A
0487 R
60
05
E8
08
20F5
20F9
20FB
20FE
2100
2102
2104
2106
8A
8A
80
DO
DE 0488 R
E9
E1 OF
ED
2109
210A
210B
210C
2100
210E
210F
2110
2111
2112
2112
2115
2115
2115
5F
5E
5A
5A
5A
2118
2118
211A
211C
211E
21lF
2121
2123
2125
2129
212A
2128
212C
212F
2131
2132
2132
2133
2134
2135
2137
213B
213C
213E
2140
2142
2144
FB 10
51
1B
FB 20
03
219E R
8E DA
FA
C7 06 0014 R 21"7 R
8C DE 0016 R
F8
E9 219E R
DO ED
DO ED
DO ED
80 E5 OF
1F
D7
50
eF
E9 219E R
E9 219E R
3C 04
73 F9
E3 F7
53
8A OF
2A FF
01 E3
8B 87 0450 R
58
5.
50
BB 0200
CD 10
58
51
53
50
86 EO
26: 8A 46 00
45
3C
74
3C
74
3C
OD
3D
OA
39
08
August 2, 1984
5923
5924
5925
5926
5927
5928
5929
5930
5931
5932
5933
5934
5935
5936
5937
5938
5939
5940
5941
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960
5961
5962
5963
5964
5965
5966
5967
5968
5969
5970
5971
5972
5973
5974
5975
5976
5977
5978
5979
5980
598'
5982
5983
5984
5985
5986
5987
5988
5989
5990
5991
5992
5993
5994
5995
5996
5997
5998
5999
6000
6001
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015
6016
6017
6018
6019
6020
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032
6033
6034
6035
6036
6031
6038
6039
6040
6041
6042
6043
60lf.4
6045
6046
6047
6048
OK
JNL
LES
JMP
BH,BH
LES
JMP
BP,GRX_SET
INFORM_OUT
F'
BP, EXT_PTR
INFORM_OUT
F9:
;
----~
F7:
HANDLE BH = 2
ASSUME
SUB
MOV
SUB
SAL
ADD
MDV
PUSH
POP
THRU
BH ;:: 5 HERE
RETURN ROM TABLE PO INTERS
DS:ABSO
BH,2
BL,BH
BH,BH
ex,1
BX,OFFSET TBL_5
8P,CS: I BX]
CS
ES
INfORM_OUT:
POP
POP
POP
POP
POP
POP
POP
pOP
01
SI
BX
AX
AX
OS
AX
AX
01 SCARO SAVED CX
01 SCARO SAVED OX
01 SCARO SAVED ES
DISCARD SAVED BP
fRET
;----- TABLE OF CHARACTER GENERATOR OFFSETS
TBL_5
LABEL
OW
ow
ow
OW
WORD
OFFSET
OFfSET
OffSET
OffSET
CGMN
CGDDOT
INT_lF_'
CGMN_FDG
SUSfTL
;~----
AL1£RNATE SELECT
AH12:
ASSUME
eMP
JB
JE
eMP
JE
JMP
ACe2:
SRLOAD
SU8
MOV
eLi
DS:ABSO
BL,010H
ACT_1
ACT_3
BL,020H
e:~E~
; RETURN ACT I VE CALL
; ALTERNATE PRINT SCREEN
INVALID CALL
; NEW PR I NT SCREEN
DS,O
DX,DX
DS,OX
MOV
MOV
STI
JMP
WORD PTR INT5_PTR, OffSET PRINT_SCREEN
WORD PTR I NT5_PTR+2, CS
MOV
AND
SH'
BH,INFO
BH,2
BH,l
LOOKING FOR MONOC BIT
; ISOLATE
; ADJUST
MOV
AND
MOV
SH.
MOV
AL,INFO
AL.01100000B
CL,5
AL,CL
BL,AL
;
;
;
;
MOV
MDV
AND
SH'
SH'
SHR
SHR
AND
CL.INFO_3
CH,CL
CL.OFH
CH,l
CH.l
CH,l
CH.l
CH.OfH
PDP
POP
POP
POP
POP
POP
POP
POP
01
SI
DX
V_RET
ACI"_3:
ox
ox
LOOK I NG FOR MEMORY
MEMORY BITS
SH I fT COUNT
ADJUST MEM VALUE
RETURN REGISTER
FEATURE/SWI TCH
DUPLICATE IN CH
MASK Off SWITCH VALUE
MOVE fEATURE VALUE
MASK IT
DISCARD BX
DISCARD ex
OS
ES
BP
IRET
AH12_X:
JMP
V_RET
RETURN TO CALLER
V_RET
RETURN TO CALLER
ACT_' :
STR_OUTZ:
JMP
;---~-
WRITE STRING
AH13:
eMP
JAE
JCXZ
AL.04
STR_OUTZ
STR_OUTZ
RANGE CHECK
I NVALI 0 PARAMETER
PUSH
BX
MOV
SUB
SAL
MOV
POP
BL.BH
BH,BH
SAVE REGISTER
GET PAGE TO LOW BYTE
BX,1
Sl,lBX + OffSET CURSOR_POSN]
PUSH
BX
SI
PUSH
AX
MOV
AX,0200H
INT
POP
STR_l :
PUSH
PUSH
PUSH
XCHG
MOV
INC
eMP
JE
CMP
JE
CHP
*2 FOR WORD OffSET
GET CURSOR POSITION
RESTORE
CURRENT VALUE ON STACK
SET THE CURSOR POSITION
10H
AX
ex
BX
AX
AH,AL
AL,ES:[BP]
GET THE CHAR TO WR ITE
8P
AL,ODH
STR_CR_lf
AL,OAH
STR_CR_lf
AL,D8H
CARR I AGE RETURN
LINE FEED
BACKSPACE
mM Enhanced Graphics Adapter 151
2146
2148
214A
214C
214F
2152
2154
2158
2159
2159
215B
2150
215F
2163
2165
2169
216B
216E
2170
2172
2172
2174
2176
2176
2179
217B
2170
2170
217F
2181
2183
2185
2187
2188
2188
218C
2180
218E
74 35
3C 07
74 31
B9 0001
80 FC 02
72 05
26: 8A 5E 00
45
84
CD
FE
3A
72
3A
75
B8
CD
FE
FE C6
2A 02
B8 0200
CD 10
EB OE
84
CO
SA
2A
01
88
5A
2191
2193
2195
2197
2199
219C
219E
3C
74
3C
74
B8
CD
21M
OE
10
OF
FF
E3
97 0450 R
58
58
59
E2 A2
2190
219E
219E
219F
21AO
21A1
21A2
21A3
21A4
21A5
09
10
C2
16 044A R
11
36 0484 R
07
OEOA
10
CE
01
09
03
05
0200
10
5F
5E
58
59
5A
lF
07
50
CF
21A7
21M
21A7
21A7
21A8
21A9
21M
21A8
21AC
21AD
21BO
2185
2187
21BC
218E
F8
1E
50
53
51
52
E8
80
74
C6
84
CD
OCFE R
3E 0500 R 01
63
06 0500 R 01
OF
10
21CO
21C2
21C6
21C8
21C8
21CC
21CE
2100
2101
2102
8A
8A
FE
E8
51
B4
CD
59
52
33
CC
2E 0484 R
C5
2220 R
2104
2104
2106
2108
21DA
210C
B4 02
CO 10
8408
CD 10
OA CO
03
10
02
6049
6050
6051
6052
6053
6054
6055
6056
6057
6058
6059
6060
6061
6062
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
6073
6074
6075
6076
6077
6078
6079
6080
6081
6082
6083
6084
6085
6086
6067
6068
6089
6090
6091
6092
6093
6094
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106
6107
6108
6109
6110
6111
6112
6113
6114
6115
6116
6117
6118
6119
6120
6121
6122
6123
6124
6125
6126
6127
6128
6129
6130
6131
6132
6133
6134
6135
6136
6137
6138
6139
6140
6141
6142
6143
6144
6145
6146
6147
6148
6149
6150
6151
6152
6153
6154
6155
6156
6157
6158
6159
6160
6161
6162
6163
6164
6165
6166
6167
6168
6169
6170
6171
6172
6173
6174
!r~o~:-LF
JE
eMP
JE
NOV
eMP
JB
MOV
INC
STR_CR_LF
CX,1
AH,2
OO_STR
BL, ES: I BPI
MOV
INT
INC
eMP
JB
eMP
JNE
MOV
INT
DEC
AH,09H
10H
DL
OL, BYTE PTR CRT_COLS
STR_2
OH, ROWS
STR_3
AX,OEOAH
lDH
DH
INC
SUB
MOV
INT
JMP
STR_CR_L~bv
INT
MOV
SUB
SAL
MOV
POP
POP
POP
LOOP
POP
eMP
JE
eMP
JE
MOV
INT
STR_OUT:
; BELL
COUNT OF CHARACTERS
CHECK WHERE ATTR IS
NOT IN THE STRING
GET THE ATTRIBUTE
NEXT ITEM IN STRING
BP
; WRITE THE CHAR/ATTR
NEXT CURSOR POSITION
COLUMN OVERFLOW
NOT YET
NEXT ROW
COLUMN ZERO
DH
OL,DL
; SET THE CURSOR
AX,0200H
10H
SHORT
STR_4
AH,OEH
10H
BL,BH
BH,BH
BX,1
OX,I BX + OFFSET CURSOR_POSN I
; GET PAGE TO LOW BYTE
*2 FOR WORD OFFSET
GET CURSOR pas I T I ON
AX
ax
CX
STR_'
ox
RECOVER CURSOR POSITION
FROM PUSH S I ABOVE
AL,1
STR_OUT
AL,3
~~Og~~H
;
lOH
SET CURSOR POSITION
; ALLOW FALL THROUGH
V_RET
V_RET
PROC
POP
POP
POP
POP
POP
POP
POP
POP
I RET
ENDP
COMBO_VIDEO
NEAR
; VIDEO BIOS RETURN
01
SI
BX
CX
OX
OS
ES
BP
ENOP
INCLUDE
VPRSC.INC
SUBTTL VPRSC.INC
PAGE
;
-----------------------------------------------------------------------INTERRUPT 5
THIS LOGIC WILL BE INVOKED BY INTERRUPT 05H TO PRINT THE
SCREEN. THE CURSOR POSITION AT THE TIME THIS ROUTINE IS INVOKED
WILL BE SAVED AND RESTORED UPON COMPLETION. THE ROUTINE IS
INTENDED TO RUN WITH INTERRUPTS ENABLED. IF A SUBSEQUENT
'PRINT SCREEN' KEY IS DEPRESSED DURING THE TIME THIS ROUTINE
IS PRINTING IT WILL BE IGNORED.
ADDRESS 50:0 CONTAINS THE STATUS OF THE PRINT SCREEN:
50:0
=0
=1
=255
EITHER PRINT SCREEN HAS NOT BEEN CALLED
OR UPON RETURN FROM A CALL THIS INDICATES
A SUCCESSFUL OPERATION.
PR I NT SCREEN I SIN PROGRESS
ERROR ENCOUNTERED OUR I NG PR I NT I NG
; ----------------------------------~-~---~------------------------------ASSUME
PRINT_SCREEN
STI
PUSH
PUSH
PUSH
PUSH
PUSH
CALL
eMP
JZ
MOV
MOV
INT
;
CS: CODE, OS: ABSO
PROC
FAR
05
AX
BX
ex
ox
MUST RUN WITH I NTS ENABLED
MUST USE 50:0 fOR DATA
AREA STORAGE
USE THIS LATER FOR CURSOR LlMITS
WILL HOLD CURRENT CURSOR POS
ODS
; SEE IF PR I NT ALREADY I N PROGRESS
; JUMP IF PR I NT I N PROGRESS
; I NO I CATE PR I NT NOW I N PROGRESS
; WI LL REQUEST THE CURRENT MODE
;
IAL}=MODE (NOT USED)
;
[AH]=NUMBER COLUMNS/LINE
_____________________________________ ~ __
_ ~_a_a _ _ _ _ _ _
___ _
; a_~ _ _ _ _ _IBHI=VISUAL
PAGE
STATUS_BYTE, 1
EXIT
STATUS_BYTE,1
AH,15
10H
AT THIS POINT WE KNOW THE COLUMNS/LlNE ARE IN
;
;
0
~:~ I D~~~~~~, ~~~~X I ~U~~~~~ Cf!t~ ~S I I b~~ JMOri~E
STACK
----------------~-----------------------------------------------
MOV
HOV
INC
CALL
PUSH
MOV
INT
POP
PUSH
XOR
CL,AH
CH,ROWS
CH
CRLf
CX
AH,3
10H
CX
OX
DX,oX
MOV
INT
MOV
INT
OR
AH,2
10H
AH,8
10H
AL,AL
152 IBM Enhanced Graphics Adapter
; WI LL MAKE USE OF ICX] REG TO
CONTROL ROW &: COLUMNS
ADJUST
CAR RETURN Ll NE fEED ROUTI NE
SAVE SCREEN BOUNDS
WILL NOW READ THE CURSOR.
AND PRESERVE THE POSITION
RECALL SCREEN BOUNDS
RECALL IBH]=VISUAL PAGE
SET CURSOR POS IT I ON TO 10,0 I
TO INDICATE CURSOR SET REQUEST
NEW CURSOR POS ESTABL I SHED
TO I NO I CATE READ CHARACTER
CHARACTER NOW IN IALI
SEE I F VAll 0 CHAR
August 2, 1984
210E
21EO
21E2
21E2
21E3
21E5
21£7
21E9
21EA
21EO
21£F
21 F1
21F3
21 F5
21F7
21 F9
21 FA
21 FO
21FE
2200
2202
75 02
80 20
2204
2205
2207
2209
220E
2210
2210
2211
2213
2215
221A
221A
22113
221C
2210
221E
221F
2220
5A
134
CO
C6
EB
2220
2220
2222
2224
2226
2228
222A
222C
222E
222F
52
33
32
CO
5A
F6
75
FE
3A
75
32
8A
52
E8
5A
FE
3A
75
02
E4
17
C4 29
21
C2
CA
OF
02
E2
2220 R
C6
EE
DO
02
10
06 0500 R 00
OA
5A
13402
CD 10
C6 06 0500 R FF
5A
59
513
58
1F
CF
33 02
32 E4
130
CD
32
80
CD
C3
00
17
E4
OA
17
222F
6175
6176
6177
6178
6179
6180
6181
6182
6183
6184
6185
6186
6187
6188
6189
6190
6191
6192
6193
6194
6195
6196
6197
6198
6199
6200
6201
6202
6203
6204
6205
6206
6207
6208
6209
6210
6211
6212
6213
6214
6215
6216
6217
6216
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228
6229
6230
6231
6232
6233
3
0000
0000
0008
OOOE
0016
OOlC
0024
002A
0032
0038
0040
0046
004E
0054
005C
0062
006A
0070
0078
007E
0086
008C
0094
009A
00A2
00A8
OOBO
OOB6
OOBE
OOC4
OOCC
0002
OODA
OOEO
00E8
OOEE
OOF6
OOFC
0104
OlOA
00
00
00
00
81
99
00
FF
E7
00
FE
7C
00
FE
38
00
E7
18
00
FF
18
00
3C
18
FF
C3
E7
00
42
66
FF
130
99
00
78
CC
00
3C
7E
00
30
70
00
63
67
00
E7
DB
00
FE
EO
00
FE
DE
00
18
7E
00
00
00
00
00
BO
81
00
C3
FF
00
FE
38
00
7C
10
00
E7
18
00
7E
18
00
3C
00
FF
C3
FF
00
42
3C
FF
00 00 00 00
00
F8
CO
00
3E
06
00
18
3C
00
PUSH
XOR
XOR
I NT
POP
TEST
JNZ
INC
CMP
JNZ
XOR
MOV
PUSH
CALL
POP
INC
CMP
JNZ
OX
OX,OX
AH,AH
17H
AH,029H
ERR10
OL
Cl,Ol
PRll0
OL,OL
AH,OL
OX
CRLF
OX
OH
CH,DH
PRI10
SAVE CURSOR POSITION
INDICATE PRINTER 1
TO INDICATE PRINT CHAR IN (All
PR I NT THE CHARACTER
RECAll CURSOR POS I T I ON
TEST FOR PR I NTER ERROR
JUMP I f ERROR DETECTED
ADVANCE TO NEXT COLUMN
SEE I F AT END OF LINE
I F NOT PROCEED
BACK TO COLUMN 0
(AHl=O
SAVE NEW CURSOR POS I T I ON
LI NE FEED CARR I AGE RETURN
RECALL CURSOR POS I T I ON
ADVANCE TO NEXT LINE
FINISHED?
I F NOT CONT I NUE
POP
MOV
INT
MOV
JMP
OX
AH,2
10H
STATUS_BYTE,O
SHORT EX I T
RECALL CURSOR POS I T I ON
TO INDICATE CURSOR SET REQUEST
CURSOR POS I T I ON RESTORED
INDICATE FINISHED
EXIT THE ROUTINE
OX
Gf.T CURSOR POS I T I ON
TO REqUEST CURSOR SET
CURSOR POS I T I ON RESTORED
INOICATE ERROR
ox
POP
AH,2
MOV
lOH
INT
STATUS_BYTE,OFFH
MOV
EXIT:
POP
POP
POP
POP
POP
I RET
PR I NT_SCREEN
OX
CX
BX
AX
OS
ENDP
; ------ CARR I AGE RETURN,
CRlF
PROC
XOR
XOR
NEAR
OX, OX
AH,AH
MOV
AL,OOH
17H
INT
XOR
AH,AH
AL,OAH
MOV
17H
INT
RET
CRLF
RESTORE ALL THE REG I STERS USED
LI NE FEED SUBROUT I NE
°
PRINTER
WILL NOW SENO INITIAL CR,
TO PR INTER
LF
eR
SEND THE LI NE fEED
NOW FOR THE CR
IF
SEND THE CARRIAGE RETURN
ENDP
SUBTTL
COOE
ENDS
COOE
PAGE,120
SUBTTL MONOCHROME CHARACTER GENERATOR
SEGMENT PUBL t C
PUBLi C CGMN
LABEL
BYTE
CGMN
ENO
08
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
BW 8*14 PATTTERN
TOP_HALF _00
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OOOH,OOOH, 07EH, 081 H, OASH, 081 H, 081H,OBOH
BOTTOM_HALF 00
TH_01
8
9
10
08
08
7E 00 00 00
7E FF DB FF
"
12
13
013
DB
099H,081H,07EH,000H,000H,OOOH
,
000H,000H,07EH,OHH,00BH,OFFH,OFFH,OC3H ;
BT 01
TH::::02
7E 00 00 00
00 6C FE FE
14
15
16
DB
DB
OE7H,OFFH,07EH,000H,000H,000H
,
000H,000H,000H,06CH,OFEH,OFEH,OFEH,OFEH ;
BT 02
TH::::03
DB
OB
07CH, 038H, 01 OH, OOOH, OOOH, OOOH
,
OOOH, OOOH, OOOH, 010H, 038H, 07CH, OFEH, 07CH ;
BT 03
TH::::04
DB
DB
038H,010H,000H,000H,000H,000H
,
OOOH,000H,018H,03CH,03CH,OE7H,0E7H,OE7H ;
BT 04
TH::::05
DB
DB
018H,018H,03CIl,000H,000H,000H
;
OOOH, OOOH, 01 8H, 03CH, 07EH, OF FH, OFFH, 07EH ;
BT_05
TH_06
DB
DB
018H,018H,03CH,000H,OOOH,000H
, BT_06
OOOH, OOOH, OOOH, OOOH, OOOH, 018H, 03CH,03CH ; TH_07
DB
DB
018H,OOOH,000H,000H,000H,OOOH
OfFH, OFFH, OFFH, OFFH, OFFH, OE7H,OC3H,OC3H
BT 07
TH::::08
DB
DB
OE7H,OFFH,OFFH,OFFH,OFFH,OFFH
OOOH, OOOH, OOOH, OOOH, 03GH, 066H, 042H, 042H
BT 08
TH::::09
DB
DB
066H, 03CH, OOOH, OOOH, OOOH, OOOH
OHH, OFFH, OFFH, OFFH, OC3H, 099H,OBOH,OBDH
BT 09
TH::::OA
00 00 00 00
7E 81 A5 81
10 00 00 00
00 10 38 7C
00 00 00 00
18 3C 3C E7
3C 00 00 00
18 3C 7E FF
3C 00 00 00
00 00 00 18
00 00 00 00
FF FF FF E7
FF FF FF FF
00 00 3C 66
00 00 00 00
FF FF C3 99
BO
C3
00
CC
CC
00
18
18
00
30
FO
00
63
E7
00
3C
18
4
5
6
7
PRI15
Al, '
ERRlO:
1
2
0000
JUMP IF VALID CHAR
; MAKE A BLANK
JNZ
MOV
PR115:
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
FF FF FF FF
1E OE 1A 32
39
40
41
DB
DB
099H,OG3H,OFFH,OFFH,OFFH,OFFH
, BT OA
000H,000H,01EH,00EH,01AH,032H,078H,OCCH ; TH::::OB
78 00 00 00
3C 66 66 66
42
DB
DB
OCCH, OCCH, 076H, OOOH, OOOH, OOOH
OOOH, OOOH, 03CH, 066H, 066H, 066H, 03CH, 018H
BT 013
TH::::OC
DB
DB
07EH,018H,018H,000H,00QH,OQOH
OOOH, OOOH, 03FH, 033H, 03FH, 030H, 030H, 030H
BT OC
TH::::OD
DB
DB
070H,OFOH,OEOH,OOOH,000H,OOOH
,
000H,000H,07FH,063H,07FH,063H,063H,063H ;
BT 00
TH::::OE
DB
DB
067H,OE7H,OE6H,OCOH,OOOH,000H
,
000H,000H,018H,018H,ODBH,03CH,0E7H,03CH ;
BT_OE
TH_OF
08
OOBH, 01 8H, 018H, OOOH, OOOH, OOOH
DB
000H,000H,080H,OCOH,OEOH,OF8H,OFEH,OF8H ;
TH_l0
DB
DB
OEOH, OCOH, 080H, OOOH, OOGH, OOOH
OOOH, OOOH, 002H, 006H, OOEH, 03EH, OFEH,03EH
BT 10
TH::::11
DB
DB
OOEH, 006H, 002H, OOOH, OOGH, OOOH
OOOH, OOOH, 018H,03CH, 07EH, 018H,018H,018H
BT 11
TH::::12
DB
DB
07EH, 03CH, 018H, OOOH, OOGH, OOOH
OOOH, OOOH, 066H, 066H, 066H, 066H,066H, 066H
BT 12
TH=-'3
18 00 00 00
3F 33 3F 30
EO 00 00 00
7F 63 7F 63
E6 CO 00 00
18 18 DB 3C
18 00 00 00
80 CO EO F8
80 00 00 00
02 06 OE 3E
02 00 00 00
18 3C 7E 18
18 00 00 00
66 66 66 66
August 2, 1984
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
IBM Enhanced Graphics Adapter 153
0112
0118
0120
0126
012E
0134
013C
0142
014A
0150
0158
015E
0166
016C
0174
017A
0182
0188
0190
0196
019E
01A4
01AC
01B2
01BA
01CO
01C8
01CE
0106
010C
01E4
OlEA
01 F2
01V8
0200
0206
020E
0214
021C
0222
022A
0230
0238
023E
0246
024C
0254
025A
0262
0268
0270
0276
027E
0284
028C
0292
029A
02AO
02A8
02AE
02B6
02BC
02c4
02CA
0202
0208
02EO
02E6
02££
02F4
02FC
0302
030A
0310
0318
031£
0326
032C
0334
OHA
0342
0348
66 66
006666000000
0000 7F DB DB DB
7B lB
18 1B 1B 00 00 00
00 7C C6 60 38 6C
C6 C6
6C 38 DC C6 7C 00
00 00 00 00 00 00
00 00
FE FE FE 00 00 00
00 00 18 3C 7E 18
18 18
7E 3C 18 7E 00 00
00 00 18 3C 7E 18
18 18
18 18 18 00 00 00
00 00 18 18 18 18
18 18
7E 3C 18 00 00 00
00 00 00 00 18 DC
FE DC
18 00 00 00 00 00
00 00 00 00 30 60
FE 60
30 00 00 00 00 00
00 00 00 00 00 CO
CO CO
FE 00 00 00 00 00
00 00 00 00 28 6C
FE 6C
28 00 00 00 00 00
00 00 00 10 38 38
7C 7C
FE FE 00 00 00 00
00 00 00 FE FE 7C
7C 38
38 10 00 00 00 00
00 00 00 00 00 00
00 00
00 00 00 00 00 00
00 00 18 3C lC 3C
18 18
00 18 18 00 00 00
00 66 66 66 24 00
00 00
000000000000
00 00 6C 6C FE 6C
6C 6C
FE 6c 6C 00 00 00
18 18 7C C6 C2 CO
7C 06
86 C6 7C 18 18 00
00 00 00 00 C2 C6
DC 18
30 66 C6 00 00 00
00 00 38 6C 6C 38
76 DC
CC CC 76 00 00 00
00 30 30 30 60 00
00 00
00 00 00 00 00 00
00 00 OC 18 30 30
30 30
30 180C 00 00 00
00 00 30 180C DC
OC oc
OC 18 30 00 00 00
00 00 00 00 66 3C
FF 3C
66 00 00 00 00 00
00 00 00 00 18 18
7E 18
18 00 00 00 00 00
00 00 00 00 00 00
00 00
18 18 18 30 00 00
00 00 00 00 00 00
FE 00
00 00 00 00 00 00
00 00 00 00 00 00
00 00
00 18 18 00 00 00
00 00 02 06 OC 18
30 60
co 80 00 00 00 00
00
F6
c6
00
18
18
00
18
60
00
3C
06
00
CC
OC
00
FC
06
00
FC
C6
00
18
30
00
7C
C6
00
7£
06
00
00
18
00
00
18
00
60
00
E6
C6
00
18
18
00
30
C6
00
06
C6
00
FE
OC
00
06
C6
00
C6
C6
00
30
30
00
C6
C6
00
06
OC
00
00
18
00
00
18
00
30
7C C6 CE OE
7C 00 00 00
18 38 78 18
7£ 00 00 00
7C c6 06 oc
FE 00 00 00
7C C6 06 06
66
67
68
69
70
71
08
OOOH,066H,066H,OOOH,OOOH,OOOH
,
OOOH,OOOH,07FH,00BH,ODBH,ODBH,07BH,01BH ;
8T_13
TH_14
01BH,01BH,01BH,000H,000H,000H
,
OOOH, 07CH, OC6H, 060H, 038H, 06CH, OC6H, OC6H ;
BT 14
TH=15
8T 15
TH=16
72
73
74
DB
06CH,038H,00CH,OC6H,07CH,OOOH
GOOH, OOOH, OOOH, OOOH, OOGH, OOOH, OOGH, OOOH
76
77
78
DB
DB
GFEH,OFEH,OF£H,OOOH,OOOH,OOOH
, BT 16
OOOH,000H,018H,03CH,07EH,018H,018H,018H ; TH=17
79
DB
DB
07EH,03CH,018H,07£H,000H,OOOH
,
OOOH,000H,018H,03CH,07EH,018H,018H,018H ;
BT 17
TH=,8
08
08
018H, 018H, 018H, OOOH, OOOH, OOOH
OOOH, OOOH, 018H, 018H, 018H, 018H, 018H, 018H
BT_ 18
TH_19
DB
DB
07EH,03CH,018H,000H,000H,000H
OOOH, OOOH, OOOH, OOOH, 018H, OOCH, OFEH, OOCH
BT 19
TH=,A
DB
DB
018H,000H,OOOH,OOOH,OOOH,000H
OOOH, OOOH, OOOH, OOOH, 030H, 060H, OF£H, 060H
BT lA
TH= 1B
DB
08
75
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
08
030H,OOOH,000H,OOOH,OOOH,OOOH
, BT 18
OOOH,OOOH,OOOH,OOOH,OOOH,OCOH,OCOH,OCOH ; TH=,C
DB
DB
OFEH,OOOH,OOOH,OOOH,OOOH,OOOH
OOOH,OOOH,OOOH,000H,028H,06CH,OFEH,06CH ;
8T lC
TH=,0
DB
DB
028H, OOOH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH,010H, 038H, 038H, 07CH, 07CH
BT_1D
TH_l £
100
101
102
DB
DB
OFEH,OFEH,OOOH,OOOH,OOOH,OOOH
,
OOOH,000H,000H,OFEH,OFEH,07CH,07CH,038H ;
BT_1E
TH_' F
103
DB
038H, 010H, OOOH, OOOH, OOOH, OOOH
104
105
106
DB
OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH ;
TH_20 SP
DB
DB
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, 018H, 03CH, 03CH, 03CH, 018H, 018H
BT 20 SP
TH=21!
DB
DB
OOOH,018H,018H,OOOH,000H,000H
,
000H,066H,066H,066H,024H,OOOH,000H,OOOH ;
BT 21 !
TH=22 "
DB
DB
OOOH,OOOH,OOOH,OOOH,OOOH,OOOH
,
OOOH,000H,06CH,06CH,OFEH,06CH,06CH,06CH ;
BT 22
TH=23
II
08
08
OF£H,06CH,06CH,OOOH,000H,000H
018H, 018H, 07CH, OC6H, OC2H, OCOH, 07CH, 006H
BT_23
TH_24
II
S
DB
086H,OC6H,07CH,018H,018H,000H
OOOH, OOOH,OOOH, OOOH, OC2H, OC6H, OOCH, 018H
BT 24
TH=25
S
08
030H,066H,OC6H,000H,000H,OOOH
,
OOOH,000H,038H,06CH,06CH,038H,076H,00CH ;
BT_25 '%'
TH_26 &:
08
08
OCCH,OCCH,076H,000H,000H,000H
OOOH, 030H, 030H, 030H, 060H, OOGH, OOOH, OOOH
BT_26 &:
TH_27 ,
DB
08
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOCH, 01 8H, 030H, 030H, 030H, 030H
BT 27
TH_28 (
08
08
030H,018H,00CH,000H,000H,000H
OOOH, OOOH, 030H, 018H, OOCH, OOCH, OOCH, OOCH
BT_28 (
TH_29)
08
08
OOCH,018H,030H,000H,000H,000H
OOOH, OOOH, OOOH, OOOH, 066H, 03CH, OFFH, 03CH
BT_29 )
TH_2A *
DB
DB
066H,000H,OOOH,000H,OOOH,000H
000H,OOOH,000H,OOOH,018H,018H,07EH,018H
BT 2A
TH::::2B
DB
DB
018H,000H,000H,000H,000H,000H
OOOH,OUOH,OOOH,OOOH,OOOH,OOOH,OOOH,OGOH
BT 2B +
TH=2C,
08
DB
018H,018H,018H,030H,OOOH,OOOH
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OFEH, OOOH
BT_2C ,
TH_2D-
DB
DB
OOOH,OOOH,OOOH,OOOH,OOOH,OOOH
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOGH
8T 20 TH=2E
DB
DB
OOOH,018H,018H,000H,000H,000H
OOOH,OOOH,002H,006H,OOCH,018H,030H,060H
BT 2E ,
TH::::2F I
08
OCOH, 080H, OOOH, OOOH, OOOH, OOOH
BT_2F I
DB
OGOH, OOOH, 07CH, OC6H. OCEH, ODEH, OF6H, OE6H ; TH_30
DB
DB
OC6H, OC6H, 07CH, OOOH, OOOH, OOOH
OOOH, OOOH, 018H, 038H, 078H, 018H, 018H, 018H
BT_30
TH_31 1
DB
DB
018H,018H,07EH,000H,OOOH,000H
OOOH,000H,07CH,OC6H,006H,OOCH,018H,030H
BT 31 1
TH=322
DB
DB
060H,OC6H,OFEH,000H,000H,000H
OOOH, OOOH, 07CH, OC6H, 006H, 006H, 03CH, 006H
8T 32 2
TH=33 3
DB
DB
006H,OC6H,07CH,000H,OOOH,000H
,
000H,OOOH,00CH,01CH,03CH,06CH,OCCH,OF£H ;
BT_33 3
TH_34 4
DB
OOCH, OOCH, 01 EH,OOOH, OOOH, OOOH
000H,000H,OFEH,OCOH,OCOH,OCOH,OFCH,006H
BT 34 4
TH=355
006H,OC6H,07CH,000H,000H,000H
OOOH,000H,038H,060H,OCOH,OCOH,OFCH,OC6H
8T 35 5
TH=366
08
OC6H, OC6H, 07CH, OOOH, OOOH, OOOH
OOOH, OOOH, OFEH, OC6H, 006H, OOCH, 018H, 030H
BT_36 6
TH_37 7
08
DB
030H,030H,030H,000H,OOOH,000H
,
OOOH, OOOH, 07CH, OC6H, OC6H, OC6H, 07CH, OC6H ;
BT_37 7
TH_38 8
DB
DB
OC6H,OC6H,07CH,000H,OOOH,OOOH
,
000H,000H,07CH,OC6H,OC6H,OC6H,07£H,006H ;
BT 38 8
TH=39 9
08
006H, OOCH, 078H, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, 018H, 018H, OOOH, OOOH, OOOH
8T_39 9
TH_3A:
08
018H, 018H, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, 018H, 018H, OOOH, OOOH, OOOH
BT 3A :
TH=3B;
08
08
018H,018H,030H,000H,OOOH,OOOH
• BT_3B ;
OOOH, OOOH, 006H, OOCH, 018H, 030H, 060H, 030H ; TH_3C <
97
98
99
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
1E 00 00 00
FE CO CO CO
164
165
166
167
168
169
7C 00 00 00
38 60 CO CO
170
171
172
7C 00 00 00
DC lC 3C 6C
OB
08
DB
08
DB
08
08
08
It
'%'
*
+
°
°
173
7C 00 00 00
FE C6 06 DC
30 00 00 00
7C C6 C6 C6
7C 00 00 00
7C C6 C6 C6
78 00 00 00
00 18 18 00
00 00 00 00
00 18 18 00
30 00 00 00
06 OC 18 30
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
08
08
08
154 IBM Enhanced Graphics Adapter
August 2, 1984
0350
0356
035E
0364
036C
0372
037A
0380
0388
038E
0396
039C
03A4
03M
03B2
03B8
03CO
03C6
03CE
0304
030C
03E2
03EA
03FO
03F8
03FE
0406
040C
0414
041A
0422
0428
0430
0436
043E
0444
044C
0452
045A
0460
0468
046E
0476
047C
0484
048A
0492
0498
04AO
04A6
04AE
04B4
04BC
04C2
04CA
0400
0408
04DE
04E6
04EC
04F4
04FA
0502
0508
0510
0516
051E
0524
052C
0532
053A
18
00
00
7E
00
06
18
00
18
00
OC
00
00
00
00
OC
30
00
18
18
06 00 00 00
00 00 00 7E
00
DE
DC
00
C6
C6
00
7C
66
00
CO
C2
00
66
66
00
78
62
00
78
60
00
CO
C6
00
FE
C6
00
18
18
00
DC
CC
00
78
6C
00
60
62
00
06
c6
00
DE
C6
00
C6
C6
00
DE
CO
00
FE
c6
00
66
66
00
CO
66
00
66
6C
00
68
66
00
68
60
00
DE
66
00
C6
C6
00
18
18
7C C6 C6 OE
00
7C
60
00
C6
DE
00
7C
66
00
38
C6
00
18
18
00
C6
C6
00
C6
6c
00
06
FE
00
38
6C
00
3C
18
00
30
C2
00
30
30
00
38
DE
00
DC
DC
10
00
00
00
00
00
00
60
60
00
06
7C
00
6C
66
00
DC
C6
00
18
18
00
C6
C6
00
C6
38
00
06
7C
00
38
C6
00
18
18
00
60
C6
00
30
30
00
1C
06
00
DC
DC
38
00
00
00
00
00
30
00
00
00
OC
CC
00
6C
66
00
C6
CO
00
6C
CC
00
C6
30 18 00
00
00 00 00
00 00 00
7C
CC 76 00
00 EO 60
66
66 7C 00
00 00 00
CO
C6 7C 00
00 1C DC
CC
CC 76 00
00 00 00
FE
00 00 00 00
60 30 18 DC
60 00 00 00
7C C6 C6 DC
18 00 00 00
7C 00 00 00
10 38 6C C6
C6 00 00 00
FC 66 66 66
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
FC 00 00 00
3C 66 C2 CO
3C 00 00 00
F8 6C 66 66
F8 00 00 00
FE 66 62 68
FE 00 00 00
FE 66 62 68
FO 00 00 00
3C 66 C2 CD
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
3A 00 00 00
C6 C6 C6 C6
C6 00 00 00
3C 18 18 18
226
227
228
229
230
231
3C 00
~OlE DC
DC
CC 78 00
00 E6 66
6C
66 E6 00
00 FO 60
60
66 FE 00
00 C6 EE
c6
C6 C6 00
00 C6 E6
CE
C6 C6 00
00 38 6C
C6
6C 38 00
00 00
DC DC
232
233
0548
054E
0556
055C
0564
056A
0572
0578
0580
0586
018H,OOCH,006H,000H,OOOH,OOOH
OOOH. OOOH, OOOH, OOOH. OOOH, 07EH, OOOH, OOOH
BT_3C <
TH_3D ==
o.
07EH, OOOH, OOOH, OOOH, OOOH, OOOH
; BT_3o ==
000H,000H,060H,030H,018H,00CH,006H,00CH ; TH_3E >
o.
O.
018H, 030H, 060H, OOOH, OOOH, OOOH
000H,OOOH,07CH,OC6H,OC6H,00CH,018H,018H
DB
000H,018H,018H,OOOH,000H,OOOH
BT_3F"
08
OOOH,000H,07CH,OC6H,OC6H,00EH,OOEH,ODEH ;
TH_40 @
O.
O.
ODCH,OCOH,07CH,000H,OOOH,000H
,
000H,OOOH,010H,038H,06CH,OC6H,OC6H,OFEH ;
BT 40 @
TH=41 A
08
08
OC6H,OC6H,OC6H,OOOH,000H,000H
OOOH,000H,OFCH,066H,066H,066H,07CH,066H
BT 41 A
TH=42 8
o.
O.
066H,066H,OFCH,OOOH,OOOH,OOOH
000H,000H,03cH,066H,OC2H,OCOH,OCOH,OCOH
BT 42 B
TH=43 C
08
08
OC2H,066H,03CH,OOOH,000H,000H
OOOH,OOOH,OF8H,06cH,066H,066H,066H,066H
BT_43 C
TH_44 0
08
08
066H,06CH,OF8H,OOOH,OOOH,000H
,
OODH,OOOH,OFEH,066H,062H,068H,078H,068H ;
BT 44 0
TH=45 E
08
06
062H,066H,OFEH,000H,OOOH,OOOH
OOOH, OOOH, OFE~!, 066H, 062H, 068H, 078H, 068H
BT_45 E
TH_46 F
O.
BT _3E >
TH_3F"
DB
060H,060H,OFOH,000H,000H,000H
OOOH,OOOH,03CH,066H,OC2H,OCOH,OCOH,ODEH
BT~46 F
TH_47 G
D.
D.
OC6H,066H,03AH,000H,OOOH,OOOH
,
OOOH, OOOH, OC6H, OC6H, OC6H, OC6H, OFEH, OC6H ;
BT 47 G
TH=48 H
08
OC6H,OC6H,OC6H,OOOH,000H,OOOH
,
OOOH,OOOH,03CH,018H,018H,018H,018H,018H ;
BT_48 H
TH_49 !
08
08
018H,018H,03CH,OOOH,OOOH,000H
, BT_49 I
OOOH,OOOH,OlEH,OOCH,OOCH,OOCH,OOCH,OOCH ; TH_4A J
08
08
OGCH,OCCH,078H,000H,OOQH,OOOH
;
OOOH,OOOH,OE6H,066H,06CH,06CH,078H,06CH
O'
DB
O.
06CH,066H,OE6H,000H,OOOH,000H
OOOH, OOOH, OFOH, 060H, 060H, 060H, 060H, 060H
8T 4B K
TH=4C L
06
062H,066H,OFEH,000H,OOOH,000H
,
OOOH,000H,OC6H,OEEH,OFEH,OFEH,OD6H,OC6H ;
BT_4C L
TH_40 M
08
08
OC6H,OC6H,OC6H,OOOH,000H,000H
,
OOOH,OOOH,OC6H,OE6H,OF6H,OFEH,OoEH,OCEH ;
BT_4D M
TH_4E N
08
OC6H,OC6H,OC6H,OOOH,OOOH,OOOH
, BT_4E N
OOOH, OOOH, 038H, 06CH, OC6H, OC6H, OC6H, OC6H ; TH_ 4F 0
O'
234
00 00
6C 6c
00 00
60 60
00 00
FE FE
00 00
F6 FE
00 00
C6 C6
00 00
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
FC 66 66 66
252
253
FO 00 00 00
7C C6 C6 C6
254
OC OE 00 00
FC 66 66 66
256
257
258
259
E6 00 00 00
7C C6 c6 60
7C 00 00 00
7E 7E 5A 18
3C 00 00 00
C6 C6 C6 C6
255
260
261
262
263
264
265
266
267
268
7C 00 00 00
C6 C6 C6 C6
10 00 00 00
C6 C6 C6 C6
269
270
271
272
273
274
6C 00 00 00
C6 C6 6C 38
275
C6 00 00 00
66 66 66 66
278
276
O'
D.
O'
O'
O.
O.
O.
08
O.
O.
O'
O.
O.
O.
O.
O'
O'
O.
08
BT 4A J
TH=4B K
OC6H, 06CH, 038H, OOOH, OOOH, OOOH
000H,OOOH,OFCH,066H,066H,066H,07CH,060H ; TH_50 P
060H,060H,OFOH,OOOH,OOOH,000H
000H,OOOH,07CH,OC6H,OC6H,OC6H,OC6H,OD6H
BT 50 P
TH=51 Q
ODEH,07CH,OOCH,OOEH,OOOH,000H
,
OOOH, OOOH, OFCH, 066H, 066H, 066H, 07CH, 06CH ;
BT_51 Q
TH_52 R
066H,066H,OE6H,OOOH,OOOH,OOOH
OOOH,OOOH,07CH,OC6H,OC6H,060H,038H,OOCH
BT_52 R
TH_53 S
OC6H,OC6H,07CH,000H,OOOH,000H
, BT_53 S
OOOH,OOOH,07EH,07EH,05AH,018H,018H,018H ; TH_54 T
018H,018H,03CH,OOOH,000H,000H
,
000H,OOOH,oc6H,OC6H,oc6H,oc6H,OC6H,OC6H ;
BT_54 T
TH_55 U
OC6H,OC6H,07CH,OOOH,OOOH,OOOH
OOOH, OOOH, OC6H, OC6H,OC6H, OC6H, OC6H, OC6H
BT_55 U
TH_56 V
06CH,038H,010H,OOOH,OOOH,000H
,
OOOH,000H,OC6H,OC6H,OC6H,OC6H,OD6H,OD6H ;
BT_56 V
TH_57 W
OFEH, 07CH, 06CH, OOOH, DOOH, OOOH
,
OOOH, OOOH, OC6H, OC6H, 06CH, 038H, 038H, 038H ;
BT 57 W
TH=58 X
277
3C 00 00 00
FE C6 8C 18
FE 00 00 00
3C 30 30 30
3C 00 00 00
80 CO EO 70
279
08
D.
O.
o.
o.
O'
O'
0'
o.
o.
O'
D.
O'
O.
o.
289
02 00 00 00
3C DC OC OC
290
291
292
3C 00 00 00
6C C6 00 00
293
00 00 00 00
00 00 00 00
294
295
296
297
00 00 FF 00
298
299
00 00
301
00 00
00 78
302
303
304
305
00 00
60 78
00 00
00 7C
306
307
308
309
310
311
00 00
DC 3C
312
313
314
00 00
00 7C
315
August 2, 1984
08
280
281
282
283
284
285
286
287
288
300
0540
O.
08
o.
316
317
08
OS
O.
08
O'
O'
O'
o.
o.
o.
06CH, OC6H, OC6H, OOOH, OOOH, OOOH
, BT _58 X
OOOH, OOOH, 066H, 066H, 066H, 066H, 03CH, 018H ; TH_59 y
018H,018H,03CH,000H,000H,000H
,
OOOH,000H,OFEH,OC6H,08CH,018H,030H,060H ;
BT_59 y
TH_5A Z
OC2H,OC6H,OFEH,000H,000H,000H
OOOH, OOOH, 03CH, 030H, 030H, 030H, 030H, 030H
BT 5A Z
TH=5B [
030H, 030H, 03CH, OOOH, OOOH, OOOH
OOOH, OOOH, 080H, OCOH, OEOH, 070H, 038H, OtCH
BT 58 [
TH=5C
00EH,006H, 002H, OOOH, OOOH, OOOH
000H,OOOH,03CH,OOCH,00CH,00CH,OOCH,OOCH
BT 5C
TH=5D
00cH,aocH,03CH,OOOH,000H,000H
010H, 038H, 06CH, OC6H, OOOH, OOOH, oaoH, OOOH
BT_50
TH_5E
1
1
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
, BT_5E
OOOH,OOOH, OOOH,OOOH, OOOH, OOOH, OOOH, OOOH ; TH_5F _
OOOH, OOOH, OOOH"OOOH,
°
FFH, OOOH
030H, 030H, 018H, OOOH, OOOH, OOOH, OOOH, OOOH ;
TH_60
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
,
OOOH,OOOH, OOOH, OOOH, OOOH, 078H,00CH,07CH ;
BT 60
nC61 LOWER_CASE A
OCCH,OCCH,076H,000H,OOOH,000H
,
000H,000H,OEOH,060H,060H,078H,06CH,066H ;
BT_61 LOWER_CASE A
TH_62 L.C, B
066H,066H,07CH,000H,OOOH,OOOH
,
OOOH, OOOH, OOOH, OOOH, OOOH, 07CH, OC6H, OCOH ;
BT_62 L,C. B
TH_63 L, C, C
OCOH,OC6H, 07CH, OOOH, OOOH, OOOH
,
000H,OOOH,01CH,OOCH,OQCH,03CH,06CH,OCCH ;
BT_63 L. C,
TH_64 L.C.
OCCH,OCCH,076H,000H,000H,000H
,
OOOH, OOOH, OOOH, OaOH, OOOH, 01CH, OC6H, OFEH ;
BT_64 L,C.
TH_65 L. c.
IBM Enhanced Graphics Adapter 155
058E
0594
059C
05A2
05AA
05BO
05B8
05BE
05c6
05CC
0504
05DA.
05E2
05E8
05FO
05F6
05FE
0604
060C
0612
061A
0620
0628
062E
0636
063C
0644
064A
0652
0658
0660
0666
066E
0674
067C
0682
068A
0690
0698
069E
06A6
06AC
06B4
06BA
06C2
06C8
0600
0606
06DE
06E4
06EC
06F2
06FA
0700
0708
070E
0716
071C
0724
072A
0732
0738
0740
0746
074E
0754
075C
0762
076A
0770
0778
077E
0786
078C
0794
079A
07A2
07Ae
07BO
07B6
07BE
07C4
07CC
co
00
FO
60
00
CC
CC
00
76
66
00
18
18
00
06
06
00
6C
6C
00
18
18
00
FE
06
00
66
66
00
C6
C6
c6
00
60
60
00
CC
7C
00
66
66
00
18
18
00
06
06
00
78
66
00
18
18
00
06
06
00
66
66
00
C6
C6
00
66
66
00
CC
CC
00
76
60
00
C6
1C
00
30
30
00
CC
CC
00
66
66
00
e6
06
00
6e
38
00
C6
C6
00
CC
30
00
70
18
00
00
18
00
DE
18
00
00
00
00
6C
C6
00
66
7C
00
CC
7C
00
66
60
00
70
C6
00
30
36
00
CC
CC
00
66
3C
00
06
FE
00
38
6C
00
e6
7E
00
18
66
00
18
18
00
18
18
00
18
18
00
00
00
00
C6
FE
00
CO
66
00
CC
CC
00
C6
CO
00
OC
CC
00
OC
CC
00
OC
00
C2
3C
00
CC
CC
DC
FE
C6
10
7C
CC
00
7C
CC
60
7C
CC
38
7C
CC
00
66
DC
10
FE
C6
00
FE
C6
60
CC
00
DC
CC
00
60
3C
00
C6
co
00
C6
co
00
co
CO
00
18
18
00
18
18
00
18
18
00
FO 00 00 00
00 00 00 76
DC CC 78 00
EO 60 60 6C
E6 00 00 00
18 18 00 38
3C 00 00 00
06 06 00 DE
66 66 3C 00
EO 60 60 66
E6 00 00 00
38 18 18 18
3C 00 00 00
00 00 00 EC
c6 00 00 00
00 00 00 DC
66 00 00 00
00 00 00 7C
7C 00 00 00
00 00 00 DC
60 60 FO 00
00 00 00 76
DC OC 1E 00
00 00 00 DC
Fa 00 00 00
00 00 00 7C
7C 00 00 00
10 30 30 FC
1C 00 00 00
00 00 00 CC
76 00 00 00
00 00 00 66
18 00 00 00
00 00 00 C6
6e 00 00 00
00 00 00 C6
C6 00 00 00
00 00 00 e6
06 DC F8 00
00 00 00 FE
FE 00 00 00
DE 18 18 18
DE 00 00 00
18 18 18 18
18 00 00 00
70 18 18 18
70 00 00 00
76 DC 00 00
00 00 00 00
00 00 10 38
00 00 00 00
3C 66 C2 co
DC 06 7C 00
CC CC 00 CC
76 00 00 00
18 30 00 7C
7C 00 00 00
38 6C 00 78
76 00 00 00
CC CC 00 78
76 00 00 00
30 18 00 78
76 00 00 00
6c 38 00 78
76 00 00 00
00 00 3C 66
06 3C 00 00
38 6C 00 7C
7C 00 00 00
CC CC 00 7C
7C 00 00 00
30 18 00 7C
FE
C6
00
18
18
18
18
18
60
18
18
C6
C6
FE C6
co
7C 00 00 00
38 6C 64 60
7C 00 00 00
66 66 00 38
3C 00 00 00
3C 66 00 38
3C 00 00 00
30 18 00 38
3C 00 00 00
C6 10 38 6C
C6 00 00 00
318
310
320
321
322
323
324
325
326
327
328
320
330
331
332
333
334
335
336
337
338
33.
340
341
342
343
344
345
346
347
348
340
350
351
352
353
354
355
356
357
358
350
360
3.'
3.2
3.3
3.'
3.5
3 ••
3.7
3.8
3 ••
370
371
372
373
374
375
37.
377
378
370
380
381
382
383
38'
385
386
387
388
380
300
301
3,2
393
39'
3.5
30.
307
308
300
400
401
'02
'03
40'
405
40.
407
408
400
410
'"
'"'15
".
'17
"2
413
"8
410
420
'21
'22
'23
'24
425
42.
427
428
42'
430
431
432
'33
'34
435
43.
'37
'38
430
440
441
442
443
08
OB
OCOH.OC6H,07CH,OOOH.000H.000H
; Bl_65 L.C o E
000H,OOOH,038H,06CH,064H,060H,OFOH.060H ; TH_66 L.C. F
DB
DB
060H.060H,OFOH,OOOH,OOOH,OOOH
, 81_66 L.C. F
000H.000H,OOOH,OOOH,OOOH,076H,OCCH,OCCH ; TH_67 L.C. G
DB
DB
OCCH,07CH,OOCH,OCCH,078H,OOOH
, BT_67 L.C. G
000H.000H.OEOH,060H,060H,06cH,076H,066H ; TH_68 L.C. H
DB
DB
066H.066H,OE6H,OOOH,OOOH,OOOH
, BT_68 L.C. H
000H.000H,018H,018H,OOOH.038H,018H,018H ; TH_69 L.C. I
DB
DB
018H.018H,03CH,OOOH,OOOH,OOOH
, BT_69 L.C. I
000H,OOOH,006H.006H,OOOH,OOEH,006H.006H ; TH_6A. L.C. J
DB
DB
006H,006H,066H,066H,03CH,OOOH
; 8T_6A L.C. J
000H.000H,OEOH,060H,060H,066H,06cH,078H ; TH_6B L.C. K
DB
DB
06CH,066H,OE6H.000H,OOOH,OOOH
, BC6B L.C. K
000H,OOOH,038H.018H.018H,018H,018H,018H ; TH_6c L.C. L
DB
DB
018H.018H,03CH.000H.000H .. 000H
; Bl_6c L.C. L
000H,OOOH,OOOH.000H.000H,OECH,OFEH,006H ; TH_60 L.C. M
DB
DB
006H.006H.OC6H.000H,000H,000H
• BT_6D L.C. M
000H.000H,OOOH,000H,OOOH,00CH,066H,066H ; TH_6E LoCo N
DB
DB
066H,066H,066H,OOOH,OOOH,OOOH
; BT_6E L.C o N
000H,OOOH,OOOH,000H.000H,07CH.OC6H,OC6H ; TH_6F L.C. 0
DB
OC6H, OC6H, 07CH, OOOH. OOOH, OOOH
DB
000H,OOOH,OOOH,000H,000H,OOCH,066H,066H ; IH_70 L.C.
DB
DB
066H.07CH,060H,060H,OFOH,OOOH
• BT_70 L.C.
OOOH, OOOH, OOOH,OOOH,OOOH, 076H,OCCH, OCCH ; TH_71 L. C.
DB
DB
OCCH, 07CH, OOCH,OOCH,Ol EH, OOOH
, BT_71 L. C.
000H,OOOH,OOOH,OOOH,OOOH,ODCH,076H,066H ; TH_72 L.C.
DB
DB
060H.060H,OFOH,000H,000H,OOOH
, BT_72 L.C. R
000H,OOOH,OOOH,000H,000H,07CH,OC6H,070H ; TH_73 L.C. S
DB
DB
01CH,OC6H,07CH,OOOH,OOOH,OOOH
; BT_73 L.C.
OOOH, OOOH, 010H,030H,030H, OFCH,030H, 030H ; IH_74 L. C.
P
DB
DB
030H, 036H,01CH, OOOH,OOOH, OOOH
; BT_74 L. C.
OOOH,OOOH,OOOH#OOOH,OOOH,OCCH,OCCH,OCCH ; IH_75 L.C.
DB
DB
OCCH,OCCH,076H,000H .. 000H,OOOH
; BT_75 L.C. U
000H,000H,OOOH,000H,OOOH,066H.066H,066H ; TH_76 L.C. V
DB
DB
066H,03CH,018H,OOOH,OOOH,OOOH
; BT_76 L.C. V
000H,OOOH,OOOH,OOOH,OOOH,OC6H,OC6H,006H ; IH_77 L.C o W
OB
DB
006H,OFEH,06CH,OOOH,OOOH,000H
; BT_77 L.C. W
000H,000H,OOOH,OOOH,OOOH,OC6H,06CH,038H ; TH_78 L.C. X
OB
DB
038H,06CH,OC6H,OOOH,OOOH,000H
; BT_78 L.C o x
000H,OOOH,OOOH,OOOH,OOOH,OC6H,OC6H,OC6H ; TH_79 LoCo Y
DB
DB
OC6H,07EH,006H,OOCH,OF8H,OOOH
; BT_79 L.C. Y
000H,000H#000H,OOOH,OOOH,OFEH,OCCH,018H ; IH_7A L.C. Z
DB
DB
, BT_7A L.C. Z
030H.066H,OFEH,OOOH .. 000H,OOOH
000H,000H.00EH,018H,018H,018H,070H,018H ; TH_7B L 8RAK
r
DB
DB
g~g~:g~g~:g~~~:g~g~:g~g~:g~g~.000H.018H ~ ~~=i~
DB
DB
018H,018H,018H,OOOH,OOOH.000H
• BT_7C I
000H,000H.070H,018H,018H,018H,OOEH,018H ; TH_7D R BRAK
DB
DB
018H,018H,070H,OOOH,OOOH,OOOH
; 8T_7D R BRAK
000H,OOOH,076H,ODCH,OOOH,OOOH,000H.000H ; TH_7E TILDE
BRAK
DB
DB
OOOH,OOOH,OOOH,OOOH,OOOH,OOOH
; 8T_7E TILDE
000H,OOOH,000H,OOOH,010H,038H,06CH,OC6H ; TH_7F DELTA
DB
OC6H, OFEH, OOOH, OOOH# OOOH, OOOH
DB
OOOH,000H,03CH,066H,OC2H,OCOH,OCOH.OC2H ; TH_80
DB
DB
066H,03CH,00CH,006H,07CH,OOOH
; BT_80
OOOH,OOOH,OCCH,OCCH,OOOH.OCCH.OCCH .. OCCH ; TH_81
DB
OB
OCCH,OCCH,076H,000H,OOOH,OOOH
; BT_81
000H,OOCH,018H,030H,OOOH,07CH,OC6H,OFEH ; TH_82
DB
DB
OCOH,OC6H,07CH,000H,000H,OOOH
; BT_82
000H,010H,038H,06CH,OOOH, 078H,OOCH, 07CH ; TH_83
DB
DB
OCCH,OCCH,076H,OOOH,OOOH,000H
; 8T_83
000H,000H,OCCH,OCCH,OOOH,078H,00CH,07CH ; IH_84
DB
DB
OCCH,OCCH,076H,OOOH,OOOH,OOOH
; BT_84
000H,060H,030H,018H,OOOH,078H,00CH,07CH ; TH_85
DB
DB
OCCH,OCCH,076H,OOOH,OOOH.000H
; BT_85
000H,038H,06CH,038H#000H, 078H,00CH, 07CH ; TH_86
DB
DB
ggg~:ggg~:g~g~:ggg~:g~g~:ggg~.060H,066H
DB
DB
ggg~:g~g~:g~g~:g~g~:ggg=:g~g~.OC6H,OFEH ~ ~~=g~
;
~~=g~
DB
DB
ggg~:ggg~:g~g~:ggg~:ggg~:g~g~,OC6H,OFEH ~ ~~=:;
DB
DB
OCOH,OC6H.07CH,000H,000H,OOOH
; BT_89
000H,060H,030H,018H,OOOH,07CH,OC6H,OFEH ; IH_SA
DB
DB
ggg~:ggg~:g~~~:ggg~:ggg=:g~g=,018H,018H ~ ~~=:~
DB
DB
g~g=:g~:=:g~g=:ggg=:ggg=:g~g=,018H,018H
DB
DB
g~g=:gJg=:g~g=:g~g=:ggg=:ggg=,018H,018H ~ ~~:gg
DB
DB
g~g=:g~=:g~=:g~g=:g~g=:ggg=,0C6H,OC6H
DB
OFEH, OO6H, OO6H, OOOH, OOOH, OOOH
156 mM Enhanced Graphics Adapter
;
;
~~:g~
~~:g~
August 2, 1984
0702
070A
07E0
07E8
07EE
07F6
07FC
0804
080A
0812
0818
0820
0826
082E
0834
083C
0842
084A
0850
0858
085E
0866
086C
0874
087A
0882
0888
0890
0896
089E
08A408AC
0882
08BA
08CO
08C8
OSCE
0806
080C
08E4
08EA
08F2
08F8
0900
0906
090E
0914
091C
0922
092A
0930
0938
093E
0946
094c
38 6c 38 00 38 6C
c6 c6
FE C6 C6 00 00 00
18
60
60
00
36
08
00
FE
CC
00
C6
C6
00
C6
C6
00
C6
C6
00
CC
CC
00
CC
CC
00
C6
C6
00
C6
C6
00
C6
C6
00
60
3C
00
60
60
00
7E
7E
00
CC
CC
00
7E
18
30
7c
66
00
7E
08
00
CC
CC
10
C6
C6
00
C6
C6
60
C6
C6
30
CC
CC
60
CC
CC
00
C6
7E
C6
C6
6C
C6
C6
C6
18
66
18
38
60
E6
00
18
18
F8
DE
CC
DE
18
18
00
DC
CC
00
18
18
00
C6
C6
00
CC
CC
00
66
66
76
FE
18
7C
CC
DC
18
18
18
C6
C6
18
CC
CC
00
66
66
DC
DE
00
7E
00
00
7C
00
00
30
C6
00
FE
CO
00
3C
00
00
38
00
00
00
60
C6
00
CO
CO
00
06
06
CO
60
86
CO
66
9E
00
3C
3C
00
6C
00
00
6c
00
0962
0968
0970
0976
097E
0984
098C
0992
099A
09AO
09A8
09AE
0986
098C
09C4
09CA
0902
0908
09EO
09E6
09EE
09F4
09rc
OA02
OADA
6E 00 00 00
3E 6C CC CC
CE 00 00 00
38 6c 00 7C
7C 00 00 00
C6 C6 00 7C
7C 00 00 00
30 18 00 7C
7C 00 00 00
78 CC 00 CC
76 00 00 00
30 18 00 CC
76 00 00 00
C6 C6 00 C6
06 DC 78 00
C6 38 6C C6
38 00 00 00
C6 00 C6 C6
7C 00 00 00
18 3C 66 60
18 00 00 00
6C 64 60 FO
FC 00 00 00
66 66 3C 18
18 00 00 00
CC CC F8 C4
C6 00 00 00
18 18 18 18
18 08 70 00
30 60 00 78
76 00 00 00
18 30 00 38
3C 00 00 00
30 60 00 7C
7C 00 00 00
30 60 00 CC
76 00 00 00
76 DC 00 DC
66 00 00 00
00 C6 E6 F6
OE C6 C6 00 00 00
FE
0954
095A
60 00 FE 66
FE 00 00 00
00 00 CC 76
06
00
30
DC
00
30
CE
00
18
3C
00
08
36
00
36
DB
"
"
"
55
55
55
DO
DO
DO
18
18
18
18
18
18
18
18
18
36
36
36
00
00
36
44
44
44
AA
AA
AA
77
77
77
18
18
18
18
F8
18
18
F8
18
36
F6
36
00
FE
36
6C 6C 3E 00
00 00 00 00
6C 6C 38 00
00 00 00 00
30 30 00 30
7C 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
CO C6 CC 08
DC 18 3E 00
CO C6 CC 08
3E 06 06 00
18 18 00 18
18 00 00 00
00 00 36 6c
00 00 00 00
00 00 DB 6C
00 00 00 00
11 44 11 44
11 44 11 44
55 AA 55 AA
55 AA 55 AA
DO 77 DO 77
DD 77 DO 77
18 18 18 18
18 18 18 18
18 18 18 18
18 18 18 18
18 18 18 F8
18 18 18 18
36 36 36 36
36 36 36 36
00 00 00 00
36 36 36 36
August 2, 1984
444
445
446
447
448
449
450
D8
038H.06CH.038H.000H.038H,06CH,OC6H,OC6H ; TH_8F
DB
OFEH, 006H, OC6H, OOOH, OOOH, OOOH
DB
018H, 030H, 060H,OOOH,OFEH, 066H, 060H, 07CH ; TH_90
D8
451
DB
ggg~: ggg~: g~5~:ggg~:ggg~: g~g~, 036H, 07EH
;
~~:g~
453
DB
DB
ggg~; ggg~:gg~~;ggg~:ggg~; ggg~, OFEH, OCCH
;
~~:~~
DB
DB
OCCH,OCCH,OCEH .. OOOH,OOOH.OOOH
; 8T_92
000H,010H, 038H,06CH,OOOH, 07CH, OC6H, OC6H ; TH_93
DB
D8
gg8~: gg8~:g~~~:gg~~:ggg~: g~g~, OC6H, OC6H
;
~~:~~
DB
DB
ggg~: g~g~: g~g~:g~g~:ggg~: g~g~, OC6H, OC6H
;
~~:~~
D8
D8
ggg~:g~8~:g~~~;ggg~:ggg~:ggg~,occH,ocCH
;
~~:g~
D8
DB
ggg~:g~g~:g~8~:g~g~:ggg~:ggg~.occH,occH
;
~~:~~
DB
DB
ggg~:ggg~:g~~~:gg~~:ggg~:ggg~,oc6H,0C6H
;
~~:~~
DB
D8
ggg~:g~~~:gg~~:g~~~:g~~~:ggg~,oc6H,0C6H
;
~~:~;
D8
D8
ggg~;g~~~:g~~~;ggg~:ggg~:ggg~,oc6H,0C6H
;
~~:~~
DB
D8
ggg~:g~g~: g1~~:g~g~: g~g~: ggg~, 060H, 066H
;
~~:~~
D8
D8
ggg~:g~g~: gJ~~:g~g~:g~g~:g~g~,060H, 060H
;
~~:~~
DB
D8
060H,OE6H,OFCH,000H,000H,000H
, BT_9C
000H,000H,066H,066H,03CH,018H,07EH,018H ; TH_90
D8
D8
; BT_90
07EH,018H,018H,OOOH,OOOH,000H
000H,OF8H, OCCH,OCCH, OF8H, OC4H,OCCH, ODEH ; TH_9E
452
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
D8
D8
ggg~:gg~~:g~~~:g~g~:g~g~:g~g~,07EH,018H
D8
018H, 01 8H, 01 8H, 008H, 070H, OOOH
DB
000H,018H,030H,060H, 000H,078H .. 00CH, 07CH ; TH_AO
D8
ggg~:ggg~:g1~~:g~g~:ggg~:g~g~,018H,018H j ~~:!~
DB
;
~~:~~
DB
DB
g~~~:g~g~:g~g~:ggg~:ggg~:g~g~,OC6H,OC6H
DB
D8
OC6H, OC6H,07CH, OOOH,OOOH, OOOH
; BT_A2
000H,018H,030H, 060H,OOOH, OCCH,OCCH,OCCH ; TH_A3
DB
DB
OCCH,OCCH,076H,OOOH,000H,OOOH
, BT_A3
OOOH, OOOH, 076H,00CH, OOOH,OOCH, 066H, 066H ; TH_A4
DB
DB
066H, 066H, 066H,OOOH, OOOH,OOOH
; BT_A4
076H,OOCH,OOOH,OC6H,OE6H,OF6H,OFEH,OOEH ; TH_A5
i
~~:~J
DB
DB
DB
DB
ggg~:g~~~:ggg~:ggg~:g~~~:ggg~,07CH,OOOH
i
~~:~~
520
521
522
523
524
525
526
527
DB
DB
ggg~;ggg~:g~g~:g~g~:ggg~:g~g~,030H,060H
;
~~:~~
DB
DB
ggg~:ggg~:g~g~:ggg~:ggg~:ggg~,OFEH,OCOH
;
~~:~;
DB
DB
OCOH,OCOH,OOOH,OOOH,OOOH,OOOH
, BT_A9
000H,000H,OOOH,000H,OOOH,000H,OFEH,006H ; TH_M
529
DB
DB
006H,006H,OOOH,OOOH~000H,OOOH
; BT.-AA
000H .. OCOH,OCOH,OC6H,OCCH,0D8H,030H,060H ; TH_AB
528
530
531
532
533
534
535
536
537
538
539
DB
DB
00CH,086H,00CH,018H~03EH,OOOH
; ST_AB
000H,OCOH,OCOH,OC6H,OCCH,0D8H,030H,066H ; TH_AC
D8
OCEH,09EH,03EH,006H .. 006H,00QH
DB
000H,OOOH,018H,018H~000H,018H,018H,03CH
DB
DB
03CH,03CH.018H,000H~000H,000H
; ST_AD
000H,OOOH .. 000H,000H .. 036H,06CH,008H,06CH ; TH_AE
DB
D8
036H,OOOH,OOOH,OOOH,OOOH,OooH
, BT_AE
OOOH,OOOH,OOOH, 000H,OD8H, 06CH, 036H,06CH ; TH_AF
D8
008H, OOOH, OOOH, OOOH .. OOOH, OOOH
546
D8
011H,044H,011H,044H,011H,044H,011H,044H ; TH_80
547
548
549
D8
D8
011H,044H,011H,044H,011H,044H
, BT_80
055H, OAAH, 055H, OMH, 055H, OAAH. 055H, OMH ; TH_81
D8
D8
055H,OAAH,055H,OMH,055H,OAAH
; 8T_81
000H,077H, OODH, 077H,00DH, 077H .. 000H,077H ; TH_B2
D8
D8
OOOH,077H,OOOH,077H,OODH,077H
, 8T_B2
018H,018H,018H,018H,018H,018H,018H,018H ; 1H_83
D8
D8
018H,018H,018H,018H,018H,018H
, BT_83
018H,018H,018H,018H,018H,018H,018H,OF8H ; TH_84
D8
D8
018H,018H,018H,018H,018H,018H
; BT_84
018H,018H,018H,018H,018H,OF8H,018H,OF8H ; TH_B5
D8
D8
018H,018H,018H,018H,018H,018H
; 8T_85
036H, 036H, 036H, 036H, 036H, 036H, 036H, OF6H ; TH_86
DB
DB
036H,036H,036H,036H,036H,036H
DB
036H!0l.6H, 036H, 036H,036H, 036H
540
541
542
543
544
545
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
OOOH,OOOH,OOOH,OOOH~OOOH,OOOH,OOOH.OFEH
; BT_AC
; TH_AD
; 8T_86
; TH_87
mM Enhanced Graphics Adapter 157
OA10
OA18
DAlE
OA26
OA2C
OA34
OA3A
OA42
OA48
OA50
0A56
OASE
0A64
OA6C
OA12
OA1A
OA80
OAB8
OA8E
OA96
OA9C
OAA4
DAM
OAB2
OAB8
OACO
OAC6
DACE
OA04
OAOC
OAE2
OAEA
OAf0
OAF8
OAFE
0806
OBOC
OB14
OB1A
OB22
OB28
OB30
OB36
OB3E
OB44
OB4C
OB52
OB5A
OB60
OB68
OB6E
OB76
OB7C
OB84
OB8A
OB92
OB98
OBAO
OBA6
OBAE
08B4
OBBC
OBC2
oeCA
0800
OBD8
OBOE
OBE6
OBEC
OBF4
OBFA
OC02
OC08
OC10
OC16
OC1E
OC24
OC2C
OC32
OC3A
OC40
OC48
00
18
18
36
06
36
36
36
36
00
06
36
36
06
00
36
36
00
18
18
00
00
00
18
00
F8
18
36
F6
36
36
36
36
00
F6
36
36
FE
00
36
FE
00
18
F8
00
00
F8
18
00 00 00 F8
18
18
00
18
18
00
00
00
18
18
18
18
00
00
00
18
18
18
18
18
18
36
36
36
36
30
00
00
30
36
36
00
00
00
00
36
36
30
36
00
00
00
36
00
36
18
00
00
18
1F
00
18
FF
00
00
FF
18
18
1F
18
00
FF
00
18
FF
18
18
18 18 18 18
18 18 18 18
36 36 36 F6
36 36 36 36
36 36 36 36
36 36 36 36
00 00 00 FE
36 36 36 36
36 36 36 F6
00 00 00 00
36 36 36 36
00 00 00 00
18 18 18 F8
00 00 00 00
00 00 00 00
18 18 18 18
00 00 00 00
18 18 18 18
00 00 00 00
00 00 00 00
18 18 18 18
18 18 18 18
18 18 18 18
00 00 00 00
F1
018H,018H,018H.018H,018H,018H
; BT_B8
036H, 036H, 036H,036H,036H, OF6H,006H,OF6H ; TH_B9
DB
036H, 036H, 036H,036H,036H, 036H
; BT_B9
036H. 036H. 036H,036H,036H, 036H,036H,036H ; TH_BA
D8
D8
036H,036H.036H,036H,036H,036H
; BT_BA
OOOH, OOOH, OOOH,OOOH,OOOH,OFEH, 006H,OF6H ; TH_BB
DB
DB
g~g~:g~g~:g~g~:g~g~:gig~:g~g~, 006H,OFEH
;
~~=:~
D8
08
g~g~: g~g~:g~g~:g~~~: g~~~:g~g~, 036H,OFEH
i
~~=:g
DB
DB
g~g~;g~g~;g~g~:g~g~:g~g~:g~g~,018H,OF8H
D8
DB
DB
; ~~::~
ggg~;ggg~:ggg~:ggg~:ggg~:ggg~,OOOH,Of8H ; ~~::~
DB
018H, 018H, 018H, 018H, 018H, 018H
DB
018H,018H,018H,018H,018H,018H,018H, 01 FH ; TH_CO
DB
DB
g~g~:g~g~:g~g~:g~g~:g~g~:g~g~,018H,OFFH
DB
DB
ggg~:ggg~:ggg~:ggg~:ggg~:ggg~,OOOH,OFFH
; ~~=g~
; ~~:g~
DB
DB
g~~~:g~~~:g~~~:g~~~:g~:~: g~~~,018H~01 FH
;
DB
DB
018H,018H,018H,018H,018H,018H
; BT_C3
OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OFFH ; TH_C4
~~:g~
;
DB
DB
OOOH,OOOH~OOOH,OOOH,OOOH~OOOH
BT_C4
018H,018H.018H,018H,018H,01BH,018H,OFFH ; TH_C5
DB
DB
018H,018H,018H,018H.018H.018H
; BT_C5
018H,O'8H~ 018H,018H, 018H.01 FH, 018H,01 FH ; TH_C6
18 18 18 18
36 36 36 36
615
DB
DB
036H,036H~ 036H,036H,036H~036H,
DB
DB
036H,036H,036H,036H,036H,036H
; BT_C7
036H, 036H, 036H,036H,036H~037H, 030H,03FH ; TH_C8
DB
DB
OOOH,OOOH~OOOH,OOOH,OOOH.OOOH
BT_C8
OOOH, OOOH, OOOH,OOOH, OOOH, 03FH, 030H,031H ; TH_C9
DB
DB
036H, 036H, 036H,036H, 036H,036H
, BT_C9
036H,036H,036H,036H,036H,0F7H,OOOH,OFFH ; TH_CA
36 36 36 36
36 36 36 31
00 00 00 00
00 00 00 3F
36 36 36 36
36 36 36 F7
00 00 00 00
00 00 00 FF
36 36 36 36
36 36 36 37
36 36 36 36
00 00 00 FF
00 00 00 00
36 36 36 F1
610
611
616
617
618
619
620
621
622
62'
624
625
626
627
628
62'
6'0
631
6'2
633
6"
635
018H,018H,018H,018H,018H.018H
; BT_C6
036H,037H ; TH_C7
;
DB
DB
ggg~:ggg~:ggg~:ggg~:ggg~;g~~~,OOOH,OF1H ~ ~~:g~
DB
D8
036H,036H,036H,036H.036H,036H
, BT_CB
036H, 036H,036H,036H, 036H,037H.030H. 031H ; TH_CC
DB
DB
gJg~: gJg~:g~g~:g~g~: gJg~;g~~~, OOOH, OFfH ~ ~~:gg
DB
DB
gg~~:gg~~:g~~~:gg~~:gg~~:g~~~,OOOH,OF7H ~ ~~:g~
DB
DB
gi:~:gi:~: gi~~:gi~~:gi:~;g~~~,OOOH,OFFH
DB
OOOH, OOOH, OOOH, OOOH. OOOH, OOOH
DB
036H, 036H. 036H,036H. 036H,036H.036H, OFFH ; TH_OO
DB
DB
ggg~:ggg~:ggg~:ggg~:ggg~:g~~~,OOOH, OFFH
;
~~=g~
DB
DB
gJg~: gJg~: gJg~:gJg~: gJg~:gJg~,OOOH, OFFH
;
~~:g~
DB
DB
gig~: gig~:g~g~:g~g~: g~g~:g~~~,036H. 03FH
;
OOOH,OOOH~OOOH,OOOH.OOOH.OOOH
;
~~:g~
DB
DB
DB
DB
ggg~:ggg~:ggg~:ggg~:ggg~:g~~~,018H,01FH
; ~~:g;
DB
DB
gJg~:gJg~:gJg~:gJg~: gJg~:gJg~,OOOH, 03FH
;
664
665
666
667
668
DB
DB
036H,036H,036H,036H,036H,036H
; BT_06
036H,036H.036H,036H.036H,036H,036H,OFfH ; TH_07
DB
DB
036H, 036H, 036H,036H, 036H,036H
; 8T_01
018H,018H,018H,018H,018H,OFFH,018H,OFFH ; TH_DB
18 18 18 18
18 18 18 18
670
671
672
DB
DB
018H,018H,018H,018H,018H,018H
; BT_DB
018H,018H,018H,018H,018H,018H,018H,OF8H ; TH_09
00 00 00 00
00 00 00 00
673
DB
DB
OOOH,OOOH~OOOH,OOOH~OOOH,OOOH
OOOH,OOOH~OOOH,OOOH.OOOH,OOOH,OOOH,OlFH·;
08
018H,018H,018H,018H.018H,018H
36 36 36 36 36
18 18 18 18 FF
FF
00 00 00 00 00
36 36
36 FF
00 00
00 00
00 FF
18 18
00 00
00 FF
36 36
36 36
36 3F
00 00
18 18
18 1F
00 00
00 00
18 1F
18 18
00 00
00 3F
36 36
36 36
36 FF
36 36
18 18
18 FF
18 18
16 18
18 f8
00 00
00 00
00 1F
18 18
FF fF
FFFF
FF FF
00 00
00 FF
FF FF
FO FO
FO FO
FO FO
OF OF
OF OF
OF OF
FF FF
FF 00
00 00
000H,OOOH,OOOH,OOOH,OOOH,OF8H,018H,OF8H ; TILB8
08
DB
612
613
614
F7
36
36
37
36
00
fF
00
36
DB
18 18 18 18
18 18 18 1F
00 00 00 00
18 18 18 18
1F
18
36
37
36
36
3F
00
00
37
36
36
FF
00
00
570
571
572
57'
574
575
576
577
578
57.
580
581
582
58'
58.
585
586
587
588
58.
590
591
592
59'
594
595
596
597
598
599
600
601
602
60'
604
605
606
607
608
609
36 36 36 36
00 00 00 00
00 00 00 FF
18 18 18 16
00 00 00 00
6'6
6'7
6'8
6"
6'0
6"
6'2
6.,
6 ••
6'5
646
6'7
6'8
6 ••
650
651
36 36 36 36
36 36 36 36
00 00 00 00
18 18 18 IF
00 00 00 00
00 00 00 1F
18 18 18 18
00 00 00 00
36 36 36 36
36 36 36 36
36 36 36 36
18 18 18 FF
18 18 18 18
FF FF FF FF
FF FF FF FF
00 00 00 00
FF FF FF FF
FO FO FO FO
FO FO fO FO
OF OF OF OF
OF OF OF OF
FF FF FF FF
00 00 00 00
00 00 00 00 00 16
DC D8
DB DC 16 00 00 00
652
653
65.
655
656
657
658
65.
660
661
662
66'
66.
674
675
676
677
678
67'
680
681
682
68'
68'
6B5
686
687
688
6B9
6'0
6"
6,2
6.,
6 ••
695
i
~~=g~
BT_03
018H,018H,018H,018H.018H,01FH,018H.OlFH ; TH_04
~~:g~
; 8T_09
TH_DA
BT_OA
;; TH_DB
DB
OFFH,OFfH,OFFH,OFFH~OFFH,OFFH,OFFH,OFFH
DB
DB
OFFH,OFFH,OFFH,OFFH,OFFH,OFFH
; BT_DB
OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OFFH ; TH_DC
DB
DB
OfFH,OFFH,OFFH,OFFH,OFFH,OffH
; BT_DC
OfOH,OfOH,OFOH,OfOH,OFOH,OfOH,OFOH,OfOH ; TH_DD
DB
DB
OFOH.OFOH.OFOH.OfOH,OFOH,OFOH
, BT_DD
OOFH,OOFH,OOFH,OOFH,OOFH,OOFH,OOFH,OOFH ; TH_OE
DB
DB
gn~:g~~~:g~~~:g~~~:g~~~:g~~~,oFFH,OOOH
DB
DOOH, OOOH, OOOH~ OOOH, OOOH~ OOOH
DB
OOOH~ OOOH, OOOH,
DB
OD8H. ODCH, 076H, OOOH, OOOH, OOOH
158 IBM Enhanced Grapbics Adapter
; ~~=g~
OOOH, OOOH, 076H, OOCH, ODeH ; TH_EO
August 2, 1984
OC4E
OC56
OC5C
OC64
OC6A
OC72
OC78
OC80
OC86
OC8E
OC94
OC9C
OCA2
OCM
aceD
OCB8
OCBE
OCC6
OCCC
OC04
OCOA
OCE2
OCE8
OCFO
OCF6
DC FE
0004
OOOC
0012
OOlA
0020
0028
002E
0036
003C
0044
OD4A
0052
0058
0060
0066
006E
0074
007C
0082
008A
0090
0098
009E
00A6
OOAC
0084
OOBA
00C2
OOC8
0000
0006
ODOE
00E4
OOEC
00F2
OOFA
OEOO
00
FC
C6
00
00 00 00 7C C6
c6
FC CO CO 40 00
00 FE C6 C6 CO
CO CO
CO
00
6C
6C
00
30
C6
00
08
06
00
66
60
00
18 18
18 16
00 00
66 66
3C 18
00 00
FE C6
C6 6C
00 00
c6 6c
6C 6C
00 00
3£ 66
66 66
00 00
DB 03
7E 00
00 00
DB F3
7E 60
00 00
7C 60
60 30
00 00
C6 C6
C6 C6
CO
00
6C
6C
00
18
60
00
08
08
00
66
7C
00
00
FE
00
00
18
00
00
DC
30
00
30
DC
00
18
18
18
18
08
00
7£
18
00
00
DC
00
00
00
00
18
00
00
00
00
00
DC
6C
00
6C
00
00
F8
00
00
7C
7C
00
00
00
00
00
FE
00
18
00
00
18
00
00
18
00
00
18
18
18
18
08
00
00
18
00
76
00
38
00
00
00
18
00
00
18
00
OF
EC
3C
08
00
00
70
00
00
00
7C
7C
00
00
00
CO 00 00 00
00 00 FE 6C
6C 00 00 00
FE C6 60 30
FE 00 00 00
00 00 00 7E
70 00 00 00
00 00 66 66
60 CO 00 00
00 00 76 DC
18 00 00 00
7E 18 3C 66
7E 00 00 00
38 6C C6 C6
38 00 00 00
38 6C C6 C6
EE 00 00 00
1E 30 18 DC
3C 00 00 00
00 00 00 7E
DB
000H,OOOH,OOOH,OOOH,07CH,OC6H,OFCH,OC6H ;
DB
DB
OC6H,OFCH,OCOH,OCOH,040H,OOOH
; BT_El
000H,OOOH,OFEH,OC6H,OC6H,OCOH,OCOH,OCOH ; TH_E2
DB
DB
OCOH, OCOH, OCOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, OFEH, 06CH, 06CH, 06CH
DB
DB
06CH, 06CH, 06CH, OOOH, OOOH, OOOH
OOOH, OOOH, OFEH, OC6H, 060H, 030H, 018H, 030H
8T_E3
TH_E4
DB
06
060H,OC6H,OFEH,000H,000H,000H
,
OOOH, OOOH, OOOH, OOOH, OOOH, 07EH, OD8H, 008H ;
BT E4
TH=E5
DB
DB
OD8H, 008H, 070H, OOOH, OOOH, OOOH
;
000H,000H,000H,000H,066H,066H,066H,066H ;
BT E5
TH=E6
DB
DB
07CH, 060H, 060H, OCOH, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, 076H,ODCH, 018H, 01 8H
BT_E6
TH_E7
DB
DB
018H, 018H, 018H, OOOH, OOOH,OOOH
OOOH, OOOH, 07EH, 018H, 03CH, 066H, 066H, 066H
BT_E7
TH_EB
DB
DB
03CH,018H,07£H,000H,000H,000H
,
000H,000H,038H,06CH,OC6H,OC6H,OFEH,OC6H ;
BT_E8
TH_E9
DB
DB
OC6H, 06CH, 038H, OOOH, OOOH, OOOH
OOOH, OOOH, 038H, 06CH, OC6H, OC6H, OC6H, 06CH
BT E9
TH=EA
DB
DB
06CH, 06CH, OEEH, OOOH, OOOH, OOOH
OOOH, OOOH, 01 EH, 030H, 018H, OOCH, 03EH, 066H
BT_EA
TH_EB
DB
DB
066H,066H,03CH,000H,000H,000H
, BT £B
000H,000H,OOOH,000H,000H,07EH,00BH,00BH ; nCEC
731
06
732
733
734
DB
07EH, OOOH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, 003H. 006H, 07EH, OOBH, OOBH, OF3H
DB
DB
07EH,060H,OCOH,OOOH,000H,000H
; BT ED
OOOH, OOOH, 01 CH, 030H, 060H, 060H, 07CH, 060H ; TH=EE
DB
DB
060H,030H,01CH,000H,OOOH,OOOH
,
OOOH, OOOH, OOOH, 07CH, OC6H,OC6H, OC6H, OC6H ;
DB
OC6H, OC6H, OC6H, OOOH, OOOH, OOOH
696
697
696
699
700
701
702
703
704
705
706
707
706
709
710
711
712
713
714
715
716
717
716
719
720
721
722
723
724
725
726
727
726
729
CO 00 00 00
1C 30 60 60
lC 00 00 00
00 7C C6 C6
C6 00 00 00
00 FE 00 00
00 00 00 00
00 16 16 7E
fF 00 00 00
30 18 DC 06
7E 00 00 00
DC 18 30 60
7E 00 00 00
DE 1B 1B 18
18 16 18 18
18 18 18 18
70 00 00 00
00 18 18 00
00 00 00 00
00 00 76 DC
00 00 00 00
6C 6C 38 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
OC DC DC DC
1C 00 00 00
6C 6C 6C 6C
00 00 00 00
08 30 60 C8
00 00 00 00
00 00 7C 7C
00 00 00 00
00 00 00 00
00 00 00 00
0000
735
736
737
736
739
740
741
742
743
744
745
746
747
746
749
750
751
752
753
754
755
756
757
756
759
760
0018
~OlE
001F
0027
0020
002E
DB
OOOH,OOOH,OOOH,OFEH,OOOH,OOOH,OFEH,OOOH ;
DB
DB
OOOH, OFEH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, 018H, 01 8H, 07EH, 018H, 01 8H
BT_FO
TH_Fl
DB
DB
OOOH, OOOH, OFFH, OOOH, OOOH, OOOH
OOOH, OOOH, 030H, 018H, 00CH,006H, OOCH, 018H
BT_Fl
TH_F2
TH_FO
DB
DB
030H, OOOH, 07EH, OOOH, OOOH, OOOH
OOOH, OOOH, OOCH, 018H, 030H, 060H, 030H, 01 8H
BT_F2
TH_F3
DB
DB
OOCH, OOOH, 07£H, OOOH, OOOH, OOOH
OOOH, OOOH, OOEH, 01 BH, 01 BH, 018H, 018H, 01 8H
BT_F3
TH_F4
DB
DB
018H,018H,018H,018H,018H,018H
018H, 018H, 018H, 018H, 018H, 018H, 018H, 018H
BT F4
TH=F5
06
BT_f5
TH_F6
DB
DB
DB
018H,018H,000H,000H,000H,000H
OOOH, OOOH, OOOH, OOOH, 076H, OOCH, OOOH, 076H
BT F6
TH=F7
771
06
761
DB
10
11
12
13
14
15
BT f7
TH=f8
BT_F8
TH_F9
DB
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH,OOOH, OOOH, OOOH, 01 8H
BT_F9
TH_FA
DB
DB
OOOH,OOOH,OOOH,OOOH,OOOH,OOOH
,
OOOH, OOFH, OOCH, OOCH, OOCH, OOCH, OOCH, OECH ;
BT_FA
TH_FB
DB
DB
06CH,03CH,OlCH,000H,000H,000H
,
OOOH, OD8H, 06CH, 06CH, 05CH, 06CH, 06CH, OOOH ;
BT_FB
TH_FC
DB
DB
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OOOH, 070H, 008H, 030H,060H, OC8H, OF8H, OOOH
BT FC
TH=FO
DB
DB
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
,
000H,000H,000H,000H,07CH,07CH,07CH,07CH ;
BT_FO
TH_FE
DB
DB
07CH, 07CH, OOOH, OOOH, OOOH, OOOH
,
OOOH, OOOH, OOOH, OOOH,OOOH, OOOH, OOOH, OOOH ;
BT_FE
TH_FF
DB
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
BT_FF
06
DB
772
773
774
775
776
777
776
779
760
761
762
763
764
765
766
767
766
769
790
791
ODCH,OOOH,OOOH,OOOH,OOOH,OOOH
,
OOOH, 038H, 06CH, 06CH. 038H, OOOH, OOOH, OOOH ;
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, 018H, 018H
06
770
7
6
00 24 66
BT_EE
TH_EF
762
763
764
765
766
767
766
769
9
10
00 00 00
FF 66
24 00 00
22
00 63 63
00 00
00 00 00
2B
000000
FF 18
18 18 00
20
00 00 00
FF 00
BT EC
TH=EO
008H, 008H, 070H, OOOH, OOOH, OOOH
OOOH, OOOH, OOOH, 018H, 018H, OOOH, 07EH, OOOH
3
4
5
6
0000
0009
OOOF
0010
BT E2
TH=E3
730
00 00 00 00
03 06 7£ DB
1
2
0000
0001
TH_E1
CODE
ENDS
END
PAGE,120
SUBTTL MONOCHROME CHARACTER GENERATOR
CODE
SEGMENT PUBL I C
PUBL I C CGMN_FOG
CGMNJOG
LABEL
BYTE
-
ALPHA SUPPLEMENT
STRUCTURE OF TH 1S FILE
DB
XXH
WHERE xx IS THE HEX CODE FOR THE FOLLOWING CHAR
DB
[BYTES 0 - 13 OF THAT CHARACTER J
DB
OOH
DB
DB
010H
OOOH, OOOH, OOOH, 000H,024H, 066H, OFFH, 066H
17
16
19
DB
DB
DB
024H, OOOH, OOOH, OOOH,OOOH, OOOH
, BT_l0
022H
;
000H,063H,063H,063H,022H,000H,000H,000H; TH_22 "
21
22
DB
DB
DB
OOOH,OOOH,OOOH,OOOH,OOOH,OOOH
02BH
,
000H,OOOH,OOOH,018H,018H,018H,OFFH,018H ;
DB
DB
DB
018H, 018H, OOOH, OOOH,OOOH, OOOH
020H
OOOH,OOOH,OOOH,OOOH,OOOH,OODH,OFFH,OOOH
INDICATES NO MORE REPLACEMENTS TO BE DONE
TH_' 0
16
00 00 00
63 22 00
00 00 00
20
18 18 18
23
00 00 00
24
25
00 00 00
August 2, 1984
26
27
26
BT_22 "
TH_2B +
BT~2B
+
TH_20-
IBM Enhanced Graphics Adapter 159
0036
003C
0030
0045
004B
004C
0054
005A
005B
0063
0069
006A
0072
0078
0079
0081
0087
0088
0090
0096
0097
009F
OOAs
00A6
OOAE
0084
0085
OOBO
00C3
00C4
OOCC
0002
0003
00 DB
OOEl
00£2
OOEA
OOFO
OOFl
00F9
DOFF
0100
0108
010E
OlaF
0117
0110
011E
0126
012C
0120
00
40
00
C3
C3
54
00
18
18
56
00
C3
66
57
00
DB
FF
58'
00
18
66
59
00
3C
18
5A
00
18
61
60
00
FF
DB
76
00
C3
66
00 00 00 00 00
29
30
00 C3 E7 FF DB
C3
C3 C3 00 00 00
31
00 FF DB 99 18
18
18 3C 00 00 00
00 C3 C3 C3 C3
C3
3C 18 00 00 00
00 C3 C3 C3 C3
DB
66 66 00 00 00
00 C3 C3 66 3C
3C
C3 C3 00 00 00
00 C3 C3 C3 66
18
18 3C 00 00 00
00 fF C3 86 DC
30
C3 FF 00 00 00
00 00 00 00 E6
DB
DB 08 00 00 00
00 00 00 00 C3
C3
3C 18 00 00 00
77
00
C3
DB
91
00
1B
08
9B
00
CO
7E
90
00
fF
FF
9'
00
66
66
f1
00
18
18
'6
00
fF
00
00
00 00 00 00 C3
DB
FF 66 00 00 00
00 00 00 6E 3B
7E
DC 77 00 00 00
18 18 7E C3 CO
C3
18 18 00 00 00
00 C3 66 3C 18
18
18 18 00 00 00
FC 66 66 7C 62
6F
66 F3 00 00 00
00 18 18 18 FF
18
00 fF 00 00 00
00 18 18 00 00
00
18 18 00 00 00
0000
0000
0008
0010
0018
0020
0028
0030
0038
0040
0048
0050
0058
0060
0068
0070
0078
0080
0088
0090
0098
OOAO
00A8
OOBO
00B8
OOCO
33
34
35
36
37
3B
39
40
41
42
43
44
45
46
47
4B
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
6B
69
70
71
72
73
74
75
76
77
7B
79
80
Bl
B2
B3
84
85
86
87
00
00
7E
81
7E
FF
6C
10
10
10
38
38
10
38
00
00
FF
FF
00
3c
fF
C3
OF
CC
3C
7E
3F
FO
7F
E6
99
SA
00
00
81
7E
FF
7E
FE
00
38
00
7C
7C
10
7C
00
00
FF
FF
3C
00
C3
FF
07
78
66
18
33
EO
63
CO
5A
99
80
80
02
02
18
3C
66
66
7F
lB
3E
CC
00
7E
18
18
18
EO
00
DE
00
3C
18
66
00
DB
00
63
78
00
00
3C
FF
3C
00 00 00 00
A5 81 BD 99
DB FF C3 £7
89
90
91
92
93
1
2
3
4
5
6
7
8
9
10
11
12
FE FE 7C 38
13
7C FE 7C 38
14
15
16
38 FE FE 7C
38 7C FE 7C
18 3C 3C 18
E7 C3 C3 E7
66 42 42 66
99 Bo BD 99
Of 70 CC CC
66 66 3C 18
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH
BT_20 040H
OOOH, OOOH, OC3H, OE7H, OFFH, OOBH, OC3H, OC3H ; TH_40 M
DB
DB
DB
OC3H, OC3H, OC3H, OOOH, OOOH, OOOH
BT_40 M
054H
000H,000H,OFFH,00BH,099H,018H,018H,018H ; TH_54 T
DB
DB
DB
018H, 018H, 03CH, OOOH, OOOH, OOOH
; BT_54 T
056H
OOOH, OOOH, OC3H, OC3H, OC3H, OC3H, OC3H, OC3H ; TH_56 V
DB
DB
DB
066H, 03CH, 018H, OOOH, OOOH, OOOH
BT_56 V
057H
OOOH,OOOH, OC3H, OC3H, OC3H, OC3H, ODBH, OOBH ; TH_57 W
DB
DB
DB
OFFH, 066H, 066H, OOOH, OOOH, OOOH
BT_57 W
Os8H
OOOH, OOOH, OC3H, OC3H, 066H, 03CH, 018H, 03CH ; TH_58 X
DB
DB
DB
066H,OC3H, OC3H, OOOH, OOOH, OOOH
BT_58 X
Os9H
OOOH, OOOH, OC3H, OC3H, OC3H, 066H, 03CH,018H ; TH_59 Y
DB
DB
DB
a 18H, 01 8H, 03CH, OOOH, OOOH, OOOH
BT_59 Y
OsAH
OOOH, OOOH, OFFH, OC3H,086H, OOCH, 018H, 030H ; TH_5A Z
DB
DB
DB
061 H, OC3H, OFFH, OOOH, OOOH, OOOH
BT_5A Z
060H
OOOH, OOOH, OOOH, OOOH, OOOH, OE6H, OFFH,OOBH ; TH_6D L.C. M
DB
DB
DB
ODBH, ODBH, OOBH, OOOH, OOOH, OOOH
BT_60 L.C. M
076H
OOOH, OOOH, OOOH, OOOH, OOOH, OC3H, OC3H, OC3H ; TH_76 l.C. V
DB
DB
DB
066H, 03CH, 018H, OOOH,OOOH, OOOH
8T_76 L.C. V
077H
OOOH, OOOH, OOOH, OOOH, OOOH, OC3H, OC3H,ODBH ; TH_77 L.C. W
DB
DB
DB
OOBH, a FFH, 066H, OOOH, OOOH, OOOH
BT_77 l.C. W
091H
OOOH, OOOH, OOOH, OOOH, 06EH, 03BH, 01 BH, 07EH ; TH_91
DB
DB
DB
008H, OOCH, 077H, OOOH, OOOH, OOOH
8T_91
09BH
OOOH, 018H, 018H, 07EH, OC3H, OCOH, OCOH, OC3H ; TH_9B
DB
DB
DB
07£H, 018H, 018H, OOOH, OOOH, OOOH
090H
OOOH, OOOH, OC3H, 066H, 03CH, 018H, OFFH, 018H ;
DB
DB
DB
OFFH, 01 8H, 018H, OOOH, OOOH, OOOH
BT_90
09£H
OOOH, OFCH, 066H, 066H, 07CH, 062H, 066H, 06FH ; TH_9E
08
08
08
066H, 066H, Of3H, OOOH, OOOH, OOOH
BT_9E
OF1H
OOOH,OOOH, 01 8H, 018H, 018H, OffH, 018H, 018H ; THJl
DB
08
DB
018H, OOOH, OFFH, OOOH, OOOH, OOOH
DB
08
ENDS
END
OOOH, 018H, 018H, OOOH, OOOH, OOOH
OOOH
88
94
95
96
0000
DB
DB
DB
32
CODE
CODE
CGODOT
7F 63 63 67
3C E7 E7 3C
F8 FE F8 EO
3E FE 3E OE
7E 18 18 7£
66 66 66 00
DB 7B 1B lB
38 6C 6C 38
00 00 7E 7E
7E 18 7E 3C
7E 18 18 18
BTJ1
O~H
;
OOOH, OOOH, 018H, 018H, OOOH, OOOH, OFFH, OOOH ; THJ6
; BT_F6
; NO MORE
PAGE,120
SUBTTl D,OUBlE DOT CHARACTER GENERATOR
SEGMENT PUBLIC
PUBLI C CGoOOT,INT_1F_l
LABEL
BYTE
DB
DOUBLE DOT
OOOH, OOOH, OOOH,OOOH, OOOH, OOOH, OOOH, OOOH ; 0_00
DB
07EH, 081H, DASH, 081 H, OBDH, 099H, 081 H, 07EH ; 0_01
08
07EH, OFFH, OOBH, OFFH, OC3H, OE7H, OFFH, 07EH ; 0_02
08
06CH, OFEH, OFEH, OFEH, 07CH, 038H, 010H, OOOH ; 0_o3
010H, 038H, 07CH, OFEH, 07CH, 036H, 010H, OOOH ; 0_o4
17
18
08
038H, 07CH, 038H, OFEH, OFEH, 07CH, 038H, 07CH ; o_05
19
20
21
22
23
24
25
26
27
2B
29
30
08
010H, 01 OH, 038H, 07CH, OFEH, 07CH, 038H, 07CH ; 0_06
08
OOOH, OOOH, 018H, 03CH, 03CH, 018H, OOOH, OOOH ; 0_07
31
08
OFFH, OFFH, 0£7H, OC3H, OC3H, OE7H, OFFH, OFFH ; 0_08
DB
OOOH, 03CH, 066H, 042H,042H,066H, 03CH, OOOH ; o_09
DB
OFFH, OC3H, 099H, OBOH,OBOH, 099H, OC3H, OFFH ;
08
OOFH, 007H, OOFH, 07oH, OCCH, DCCH, DCCH, 078H ; O_DB
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
O_OA
08
03CH, 066H, 066H, 066H, 03CH, 018H, 07EH, 018H ; O_OC
DB
03 FH, 033H, 03FH,030H, 030H, 070H, OFOH, OEOH ; 0_00
08
07FH, 063H, 07FH, 063H, 063H, 067H, OE6H, OCOH ;
08
099H, OsAH, 03CH, OE7H, OE7H, 03CH, OsAH, 099H ; O_OF
DB
080H, OEOH, OF8H,OFEH, OF8H, OEOH, 080H, OOOH ; 0_10
32
3F 30 30 70
BT_9B
TH_90
O_OE
DB
002H,OOEH, 03EH,OFEH, 03EH, OO£H, 002H, OOOH ; 0_11
DB
018H, 03CH, 07£H,018H, 018H, 07EH, 03CH, 018H ;
08
066H, 066H, 066H. 066H, 066H. OOOH, 066H, OOOH ; 0_13
08
07FH, OOBH, ODBH, 07BH, 01 BH, 01 BH, 01 BH, OOOH ; o_14
08
03£H,063H, 038H,06CH,06CH,038H, OCCH. 078H ; 0_15
DB
000H,OOOH,OOOH,OOOH,07EH,07EH,07EH,000H ; 0_16
0_12
DB
018H,03CH,07EH,018H,07£H,03CH,018H,OFFH ; 0_17
08
018H,03CH,07EH,018H,018H,018H,018H,OOOH ; 0_18
160 IBM Enhanced Graphics Adapter
August 2, 1984
00C8
0000
0008
ODED
00E8
OOFO
00F8
0100
0108
0110
0118
0120
0128
0130
0138
0140
0148
0150
0158
0160
0168
0170
0178
0180
0188
0190
0198
01AO
01A8
01BO
01B8
01CO
01C8
0100
0108
OlEO
01E8
OlFO
01 F8
0200
0208
0210
0218
0220
0228
0230
0238
0240
0248
0250
0258
0260
0268
0270
0278
0280
0288
0290
0298
02AO
02A8
18
18
18
00
00
00
00
00
00
00
00
00
00
00
00
00
18
00
18
00
30
00
00
00
24
00
18
00
FF
00
00
00
30
30
6C
00
6C
6C
30
30
00
C6
38
76
60
00
18
18
60
60
00
00
00
00
00
30
00
00
00
30
06
80
00
00
78
00
6C
00
6C
00
7C
00
C6
00
6C
00
60
00
30
00
30
00
66
00
30
00
00
60
00
00
00
00
DC
00
7C
7C
30
FC
78
FC
78
78
lC
lE
FC
78
38
78
FC
30
78
78
78
70
00
30
00
30
18
18
00
00
60
60
78
30
C6
00
70
00
CC
00
CC
00
3C
00
CO
00
60
00
CC
00
CC
00
CC
00
30
00
30
60
30
00
00
00
30
00
CC
00
7C
78
30
CC
FC
FC
3C
3C
F8
F8
FE
FE
FE
FO
3C
3E
CC
CC
78
78
lE
78
E6
E6
FO
FE
C6
C6
C6
C6
38
38
C6
00
78
00
66
00
66
00
6C
00
62
DO
62
00
66
00
CC
00
30
00
DC
00
66
00
60
00
EE
00
E6
00
6c
00
DE DE DE CO
FC
FO
78
lC
FC
E6
78
78
FC
78
CC
66
00
CC
00
66
00
CC
00
84
00
CC
66 7C 60 60
18 18 7E 3C
DC FE DC 18
60 FE 60 30
CO CO CO FE
66 FF 66 24
3C 7E FF FF
FF 7E 3C 18
00 00 00 00
78 30 30 00
6C 00 00 00
FE 6C FE 6C
CO 78 DC F8
CC 18 30 66
38 76 DC CC
CO 00 00 00
60 60 60 30
18 18 18 30
3C FF 3C 66
30 FC 30 30
00 00 00 30
00 FC 00 00
00 00 00 30
1830 60 CO
CE DE F6 E6
30 30 30 30
DC 38 60 CC
DC 38 DC CC
6C CC FE DC
F8 DC DC CC
CO F8 CC CC
DC 18 30 30
CC 78 CC CC
CC 7C DC 18
30 00 00 30
30 00 00 30
60 CO 60 30
FC 00 00 FC
180C1830
DC 18 30 00
CC CC FC CC
66 7C 66 66
CO CO CO 66
66 66 66 6C
68 78 68 62
68 78 68 60
CO CO CE 66
CC FC CC CC
30 30 30 30
OC DC CC CC
6C 78 6c 66
60 60 62 66
FE FE D6 c6
F6 DE CE C6
c6 C6 C6 6C
CC CC DC 78
66 7e 6C 66
EO 70 1C CC
30 30 30 30
CC CC CC CC
August 2, 1984
57
58
5'
60
61
62
63
64
65
66
67
68
6.
70
71
72
73
74
75
76
77
78
7.
80
81
82
83
84
85
86
87
88
8.
'0
"
'2
.3
.4
.5
96
.7
.8
••
TOO
101
102
103
104
105
106
107
108
10'
110
111
112
113
114
115
116
117
118
"'
120
121
122
123
124
125
126
127
128
12,
130
131
132
133
134
135
136
137
138
13'
140
141
142
143
144
145
146
147
148
14.
150
151
152
153
154
155
156
157
158
15.
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
17'
180
181
182
DB
018H, 01SH, 018H, 01SH, 07EH, 03CH, 018H, OOOH ; 0_19
DB
OOOH, 018H, OOCH, OFEH, OOCH, 018H, OOOH, OOOH ; 0_1A
DB
OOOH, 030H, 060H, OFEH, 060H, 030H, OOOH, OOOH ; 0_18
DB
OOOH, OOOH, OCOH, OCOH, OCOH, OFEH, OOOH, OOOH ; D_1C
DB
OOOH, 024H, 066H, OFFH, 066H, 024H, OOOH,OOOH : 0_10
DB
OOOH, 018H, 03CH, 07EH, OFFH, OFFH, OOOH, OOOH ; O_lE
DB
OOOH, OFFH, OFFH, 07EH, 03CH, 018H, OOOH, OOOH ; O_1F
DB
OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH ; SP 0_20
0_21
DB
030H, 078H, 078H, 030H, 030H, OOOH, 030H, OOOH ;
DB
06CH, 06CH, 06CH, OOOH, OOOH, OOOH, OOOH, OOOH ;
DB
06CH, 06CH, OFEH, 06CH,OfEH, 06CH, 06CH, OOOH ; # 0_23
OB
030H,07CH, OCOH, 078H, OOCH, OF8H, 030H, OOOH ;
S 0_24
DB
OOOH, OC6H, OCCH, 018H, 030H, 066H, OC6H, OOOH ;
PER CENT 0_25
DB
038H, 06CH, 038H, 076H, ODCH, OCCH, 076H, OOOH ; & 0_26
DB
060H, 060H, OCOH, OOOH, OOOH, OOOH, OOOH, OOOH ;
0_27
DB
018H, 030H, 060H, 060H, 060H,030H, 018H, OOOH :
( 0_28
I
0_22
DB
060H, 030H, 018H, 018H, 018H, 030H, 060H, OOOH ;
1
0_29
OB
000H,066H, 03CH, OFFH, 03CH, 066H, OOOH, OOOH ;
*
0_2A
OB
OOOH, 030H, 030H, OFCH, 030H, 030H, OOOH, OOOH : + 0_2B
DB
OOOH, OOOH, OOOH,OOOH, OOOH, 030H, 030H, 060H :
0_2C
DB
OOOH, OOOH, OOOH, OFCH, OOOH,OOOH,OOOH, OOOH ;
- 0_20
DB
OOOH, OOOH, OOOH, OOOH, OOOH, 030H, 030H, OOOH ;
0_2E
DB
006H, OOCH, 018H, 030H, 060H, OCOH, 080H, OOOH ; I 0_2F
DB
07CH,OC6H, OCEH, OOEH, OF6H, OE6H, 07CH, OOOH ; o 0_30
DB
030H, 070H, 030H, 030H, 030H, 030H, 0 FCH, OOOH ; 1 0_31
DB
078H, OCCH, OOCH, 038H, 060H, OCCH, OFCH, OOOH : 2 0_32
DB
078H, OCCH, OOCH, 038H, OOCH, OCCH, 078H, OOOH :
DB
01CH, 03CH, 06CH, OCCH, OFEH, OOCH, 01 EH, OOOH ; 4 0_34
DB
OFCH, OCOH, OF8H, OOCH, OOCH, OCCH, 078H, OOOH ; 5 0_35
DB
038H, 060H, OCOH, OF8H, OCCH, OCCH, 078H, OOOH ; 6 0_36
DB
OFCH,OCCH, OOCH, 018H, 030H,030H,030H, OOOH ; 7 0_37
DB
078H, OCCH, OCCH, 078H, OCCH, OCCH,078H, OOOH ; 8 0_38
DB
078H, OCCH, OCCH, 07CH, OOCH, 018H, 070H, OOOH ; 9 0_39
DB
OOOH, 030H, 030H, OOOH, OOOH, 030H, 030H, OOOH ;
DB
000H,030H, 030H, OOOH, OOOH, 030H,030H, 060H ;
; 0_38
DB
018H,030H, 060H, OCOH, 060H, 030H, 018H, OOOH ;
< 0_3C
DB
OOOH, OOOH, 0 FCH, OOOH, OOOH, OFCH, OOOH, OOOH ; '" 0_30
DB
060H,030H, 018H, OOCH, 018H, 030H, 060H, OOOH ;
DB
078H,OCCH, OOCH, 018H, 030H, 000H,030H, OOOH ; ? 0_3F
DB
07CH, OC6H, ODEH, OOEH, ODEH, OCOH, 078H, OOOH ;
3 0_33
, O_3A
> 0_3E
@
0_40
030H, 078H, OCCH, OCCH, OFCH, OCCH, OCCH, OOOH ; A 0_41
DB
°
DB
03CH, 066H, OCOH,OCOH, OCOH, 066H, 03CH, OOOH : C 0_43
°
FCH, 066H, 066H, 07CH, 066H, 066H, FCH, OOOH ; 8 0_42
DB
OF8H, 06CH,066H,066H, 066H, 06CH, OF8H, OOOH ; o 0_44
DB
OFEH,062H,068H, 078H, 068H, 062H, OFEH, OOOH :
E 0_45
DB
OFEH, 062H,068H, 078H, 068H, 060H, OFOH, OOOH :
F 0_46
DB
03CH, 066H,OCOH, OCOH, OCEH, 066H, 03EH, OOOH : G 0_47
OCCH, OCCH,OCCH, OFCH, OCCH, aCCH, OCCH, OOOH ; H 0_48
0_49
DB
078H, 030H,030H,030H, 030H, 030H, 078H, OOOH ;
DB
01 EH, OOCH, OOCH, OOCH, OCCH, OCCH, 078H, OOOH ; J 0_4A
DB
OE6H, 066H, 06CH, 078H, 06CH,066H, OE6H, OOOH ;
K 0_4B
DB
OFOH, 060H, 060H, 060H, 062H, 066H, OFEH, OOOH ;
L 0_4C
DB
OC6H, OEEH, OFEH, OFEH, 006H, OC6H, OC6H, OOOH ; H 0_40
08
OC6H, OE6H, 0 F6H, OOEH, OCEH, OC6H, OC6H, OOOH ; N 0_4E
08
038H, 06CH, OC6H, OC6H, OC6H, 06CH, 038H, OOOH ;
a 0_4F
DB
OFCH, 066H, 066H, 07CH, 060H, 060H, OFOH, OOOH ;
PO_50
DB
078H,OCCH,OCCH,OCCH, OOCH, 078H, 01 CH, OOOH ; Q 0_51
DB
OFCH, 066H,066H,07CH, 06CH, 066H,OE6H, OOOH ;
R 0_52
DB
078H,OCCH,OEOH,070H, 01CH, OCCH, 078H, OOOH ;
SO_53
DB
OFCH, OB4H,030H,030H, 030H, 030H,078H, OOOH ; TO_54
DB
OCCH,OCCH,OCCH,OCCH. OCCH, OCCH,OFCH, OOOH ;
I
U 0_55
IBM Enhanced Graphics Adapter 161
02BO
02B8
02CO
02C8
0200
0208
02EO
02E8
02fO
02f8
0300
0308
0310
0318
0320
0328
0330
0338
0340
0348
0350
0358
0360
0368
0370
0378
0380
0388
0390
0398
03AO
03A8
03BO
03B8
03CO
03C8
0300
0308
03EO
03E8
03FO
03F8
FC
CC
30
C6
C6
C6
C6
CC
78
FE
FE
78
78
CO
02
78
78
10
00
00
00
00
CC
00
C6
00
C6
00
CC
00
C6
00
60
00
60
00
18
00
38
00
00
Ff
30
00
00
76
EO
DC
00
78
lC
76
00
78
38
FO
00
DC
EO
E6
30
78
DC
CC
EO
E6
70
78
00
c6
00
CC
00
78
30
00
00
00
60
00
00
00
DC
00
00
00
6C
00
00
f8
60
00
00
00
00
78
60
00
30
00
00
00
00
00
00
00
00
60
00
OC
00
FO
00
F8
10
18
00
76
00
30
00
6C
00
C6
00
DC
00
FC
lC
lC
18
18
EO
EO
76
00
00
FE
00 DC 66 66 7C
FO
00 76 CC CC 7C
00
00
00
00
30
00
00
00
00
00
00
00
00
00
00
F8
00
00
30
00
18
00
30
00
DC
00
10
00
78
DC
00
7£
lC
78
7E
3F
CC
7E
EO
7E
30
7£
00
OC
7E
3C
CC
78
EO
78
CC
78
7C
3C
EO
78
C6
C6
30
CC
CC
78
CC
00
00
00
C3
00
00
00
00
00
30
00
00
38
C3
00
00
00
00
00
00
00
C6
00
00
00
38
00
30
00
CC CC CC 78
c6 06 FE EE
6C 38 38 6C
CC 78 30 30
8C 18 32 66
60 60 60 60
30 18 OC 06
18 18 18 18
6c c6 00 00
00 00 00 00
18 00 00 00
78 DC 7C CC
60 7C 66 66
0408
0410
0418
0420
0428
0430
0438
0440
0448
0450
0458
0460
0468
0470
0478
08
OCCH, OCCH, OCCH, OCCH, OCCH, 078H, 030H,OOOH ; V 0_56
DB
OC6H, OC6H,OC6H, 006H, OFEH, OEEH, OC6H,000H ; W 0_57
DB
OC6H, OC6H, 06CH, 038H, 038H, 06CH, OC6H, OOOH ; X 0_58
DB
OCCH,OCCH,OCCH,078H,030H,030H,078H,000H ; YO_59
DB
OFEH,oc6H,08CH,018H,032H,066H,OFEH,000H ; Z 0_5A
DB
078H, 060H, 060H, 060H, 060H, 060H,078H, OOOH ;
DB
OCOH, 060H, 030H, 01 8H,00CH, 006H, 002H, OOOH ; BACKSLASH 0_5C
OB
078H,018H,018H,018H,018H,018H,078H,000H ;
DB
010H,038H,06CH,OC6H,000H,000H,000H,000H ; CIRCUMfLEX o_5£
DB
OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OFFH ; _ 0_5F
OB
030H, 030H, 018H, OOOH, OOOH, OOOH, OOOH, OOOH ;
DB
OOOH, OOOH, 078H, OOCH, 07CH, OCCH, 076H, OOOH ; LOWER CASE A 0_61
( 0_5B
J D._50
• 0_60
OB
OEOH, 060H, 060H, 07CH, 066H, 066H, OOCH, OOOH ;
L. C. B 0_62
211
DB
OOOH,000H,078H,OCCH,OCOH,OCCH,078H,000H ;
L.C. C 0_63
OC 7C CC CC
213
DB
01CH,OOCH,00CH,07CH,OCCH,OCCH,076H,000H ;
L.C.
78 CC FC CO
21'
215
216
DB
000H,000H,078H,OCCH,OfCH,OCOH,078H,000H ;
L.C. E o_65
DB
038H, 06CH, 060H, OFOH, 060H, 060H,OFOH, OOOH ; L. C.
DB
000H,000H,076H,oecH,ocCH,07CH,00CH,OF8H ;
L.C. G 0_67
DB
OEOH, 060H, 06CH, 076H, 066H, 066H, OE6H, OOOH ;
L. C. H o_68
DB
030H, 000H,070H, 030H, 030H, 030H, 078H, OOOH ; L. C.
225
DB
00CH,000H,00CH,00CH,00CH,OCCH,OCCH,078H ;
L.C. J D_6A
66 6C 78 6C
226
227
DB
228
229
230
OEOH, 060H, 066H, 06CH, 078H, 06CH,OE6H, OOOH ;
L. C. K 0_68
30 30 30 30
DB
070H, 030H, 030H, 030H, 030H, 030H, 078H, OOOH ;
L. C. L 0_6C
000H,000H,OCCH,OFEH,OFEH,006H,OC6H,000H ;
L.C. M 0_60
78 CC CO CC
212
60 FO 60 60
76 CC CC 7C
217
218
219
220
6C 76 66 66
70 30 30 30
OC OC DC CC
CC FE FE 06
f8 CC CC CC
78 CC CC CC
1E
DC 76 66 60
7C CO 78 DC
7C 30 30 34
CC CC CC CC
CC CC CC 78
c6 06 FE FE
C6 6C 38 6C
CC CC CC 7C
Fe 98 30 64
30 EO 30 30
221
222
223
18 00 18 18
30 lC 30 30
00 00 00 00
231
232
233
CO CC 78 18
00 CC CC CC
78 CC FC CO
3C 06 3E 66
78 OC 7C CC
78 OC 7e CC
78 DC 7C CC
78 CO CO 78
3C 66 7£ 60
000H,OOOH,078H,OCCH,OCCH,OCCH,078H,000H ;
L.C. 0 0_6F
DB
000H,000H,00CH,066H,066H,07CH,060H,OFOH ;
L.C.
DB
000H,000H,076H,OCCH,OCCH,07CH,OOCH,01EH ; l.C. Q 0_71
OB
000H,000H,OOCH,076H,066H,060H,OfOH,000H ; L.C. R 0_72
OB
000H,000H,07CH,OCOH,078H,00CH,OF8H,000H ;
2.6
DB
247
2'8
2'9
010H, 030H, 07CH, 030H, 030H, 034H, 01 8H, OOOH ; L. C. T o_74
DB
000H,000H,OCCH,OCCH,OCCH,OCCH,076H,000H; L.C. U 0_75
DB
000H,000H,OCCH,OCCH,OCCH,078H,030H,000H ; L.C. V o_76
DB
000H,000H,OC6H,006H,OFEH,OFEH,06CH,OOOH ; L.C. W o_77
DB
OOOH, OOOH, OC6H, 06CH, 038H, 06CH, oe6H, OOOH ;
L. C. X o_78
DB
000H,000H,OCCH,OCCH,OCCH,07CH,00CH,OF8H ;
L.C. Y 0_79
DB
000H,000H,OFCH,098H,030H,064H,OFCH,000H ;
L.C. Z 0_7A
DB
01CH, 030H, 030H, OEOH, 030H, 030H, 01CH, OOOH ;
L BRAK 0_78
DB
018H,018H,018H,000H,018H,018H,018H,000H ;
I 0_7C
DB
OEOH,030H, 030H, 01CH, 030H, 030H, OEOH, OOOH ; R BRAK 0_70
2"2'5
250
251
252
253
25'
255
256
257
258
259
260
262
263
26.
265
266
DB
076H, OOCH, OOOH, OOOH, OOOH, OOOH, OOOH, OOOH ; TILDE D_7E
268
269
270
271
272
OB
OOOH, 010H, 038H, 06CH, OC6H, OC6H, OFEH, OOOH ; DELTA D_7F
273
OB
078H,OCCH, OCOH, OCCH, 078H, 018H, OOCH, 078H;
DB
OOOH,OCCH, OOOH, OCCH, OCCH, OCCH, 07EH, OOOH;
o_81
DB
01CH,000H,078H,OCCH,OFCH,OCOH,078H,000H;
0_82
DB
07EH, OC3H, 03CH, 006H, 03EH, 066H, 03 FH, OOOH;
0_83
DB
OCCH, OOOH, 078H, OOCH, 07CH, OCCH, 07EH, OOOH;
0_84
DB
OEOH,OOOH,078H,00CH,07CH,OCCH,07EH,OOOH;
0_85
OB
030H, 030H,078H,00CH, 07CH, OCCH, 07EH, OOOH;
o_86
DB
OOOH, OOOH, 078H, OCOH, OCOH, 078H, OOCH, 038H;
0_87
DB
07EH, OC3H, 03CH, 066H,07EH,060H, 03CH, OOOH;
0_88
274
275
276
277
278
279
280
281
282
283
28.
285
286
287
288
289
290
LABEL
BYTE
0_80
DB
OCCH, OOOH, 078H, OCCH, orCH,OCOH, 078H, OOOH;
o_89
78 CC FC CO
DB
OEOH,000H,078H,OCCH,OFCH,OCOH,078H,000H;
0_8A
DB
OCCH,000H,070H,030H,030H,030H,078H,OOOH;
0_8B
OB
07CH,OC6H,038H,018H,018H,018H,03CH,OOOH;
0~8C
DB
OEOH, OOOH, 070H, 030H, 030H, 030H, 078H, OOOH;
0_80
DB
OC6H, 038H, 06CH, OC6H, OFEH, OC6H, OC6H,000H;
0_8E
DB
030H,030H,000H,078H,OCCH,OFCH,OCCH,OOOH;
O_Sf
DB
01CH, OOOH, OFCH, 060H, 078H, 060H, OfCH, OOOH;
o_90
DB
OOOH,OOOH,07FH,00CH,07FH,OCCH,07FH,OOOH;
0_91
6C C6 FE C6
00 78 CC FC
P 0_70
L.C. S o_73
292
293
29'
70 30 30 30
I 0_69
000H,000H,OF8H,OCCH,OCCH,OCCH,OCCH,000H ; l.C. N 0_6E
291
38 18 18 18
F 0_66
OB
235
236
237
238
239
2'0
241
2'2
243
78 CC FC CO
70 30 30 30
0_64
OB
234
267
38 6C C6 C6
°
22'
261
0400
0400
183
18.
185
186
187
188
189
190
191
192
193
19.
195
196
197
198
199
200
201
202
203
20.
205
206
207
208
209
210
295
296
297
298
299
300
301
302
303
30.
305
0480
0488
1C 00 FC 60 78 60
FC 00
00 00 7F OC 7F CC
306
307
308
162 IBM Enhanced Graphics Adapter
August 2, 1984
0490
0498
D4AO
D4AS
D4BO
04B8
D4CO
04C8
0400
0408
04EO
04E8
04FO
04F8
0500
0508
0510
0518
0520
0528
0530
0538
0540
0548
0550
0558
0560
0568
0570
0578
0580
0588
0590
0598
05AO
05AS
05BO
05B8
05CO
05C8
0500
0508
05EO
05E8
05FO
05F8
0600
0608
0610
0618
0620
0628
0630
0638
0640
0648
0650
0658
0660
0668
0670
7F
3E
CE
78
78
00
78
00
78
78
7E
00
7E
00
DC
C3
18
CC
78
18
18
38
FC
CC
30
F8
C6
DE
08
00
6C
00
CC
00
ce
00
EO
00
CC
00
EO
00
cc
F8
18
00
00
00
18
18
6C
00
CC
30
CC
C7
lB
70
1C
7E
38
78
00
78
00
7E
00
CC
FC
CC
3C
00
38
00
30
78
00
00
00
00
C3
CC
C3
CF
18
18
00
00
00
00
00
00
00
00
lC
00
lC
00
F8
00
00
00
6C
00
6C
00
00
00
00
00
00
00
C6
OF
c6
03
18
00
33
00
CC
00
22
22
55
55
DB
DB
18
18
18
18
18
18
36
36
00
36
00
18
36
36
36
36
00
36
36
00
36
00
18
00
00
18
88
88
AA
AA
77
EE
18
18
18
18
18
18
36
36
00
36
00
18
36
36
36
36
00
36
36
00
36
00
18
00
00
18
18
00
18
00
00
18
18
18
00
00
18
18
18
18
36
36
36
00
00
36
36
00
00
36
36
36
00
00
36
36
18
00
18
00
00
18
18
18
00
00
18
18
18
18
36
36
36
00
00
36
36
00
00
36
36
36
00
00
36
36
CC FE CC CC
00 78 CC ce
00 78 CC CC
00 78 CC CC
00 CC CC CC
00 CC CC CC
00 CC CC 7C
3C 66 66 3C
CC CC CC CC
7E CO CO 7E
64 FO 60 E6
78 FC 30 FC
CC FA C6 CF
18 3C 18 18
78 DC 7C CC
70 30 30 30
00 78 CC CC
00 CC CC CC
00 f8 CC CC
CC EC FC DC
6C 3E 00 7E
6C 38 00 7C
30 60 CO CC
00 FC CO CO
00 FC DC DC
CC DE 33 66
CC DB 37 6F
00 18 18 18
66 cc 66 33
66 33 66 CC
22 88 22 88
55 AA 55 AA
DB EE DB 77
18 18 18 18
18 18 F8 18
F8 18 F8 18
36 36 F6 36
00 00 FE 36
F8 18 F8 18
F6 06 F6 36
36 36 36 36
FE 06 F6 36
F6 06 FE 00
36 36 FE 00
F8 18 F8 00
00 00 F8 18
18 18 1F 00
18 18 FF 00
00 00 FF 18
18 18 1F 18
00 00 FF 00
18 18 FF 18
lF 18 1F 18
36 36 37 36
37 30 3F 00
3F 30 37 36
F7 00 FF 00
FF 00 F1 36
37 30 37 36
FF 00 FF 00
F1 00 F7 36
August 2, 1984
30.
310
311
312
313
314
315
316
317
31B
31,
320
321
322
323
324
325
32.
327
32B
32,
330
331
332
333
334
335
336
337
33.
33,
340
341
342
343
344
345
346
347
34.
34.
350
351
352
353
354
355
356
357
35'
35.
360
361
362
363
364
365
3••
367
36B
36.
370
371
372
373
374
375
376
317
378
37.
380
381
382
383
384
385
386
387
388
38,
3,0
3"
3,2
3'3
3,4
3.5
3,6
3,7
3,8
3"
400
401
402
403
404
405
406
407
408
40.
410
411
412
413
414
415
416
417
418
41,
420
421
422
423
424
425
426
427
428
42'
430
431
432
433
434
DB
03EH, 06CH,OCCH,OFEH, oeCH,OCeH,OeEH,OOOH ;
DB
078H,OceH, 000H,078H, OCCH,OCCH,078H, OOOH ;
0_92
0_93
DB
OOOH, OceH, OOOH, 078H, OCCH, OCCH, 078H, OOOH ;
0_94
DB
OOOH,OEOH, 000H,078H, OCCH,OCCH,078H, OOOH ;
.0_95
DB
078H,OCCH, OOOH,OCCH, oeCH,OCCH,07EH, OOOH ;
0_96
DB
OOOH,OEOH, 000H,OCCH,OCCH,OCCH,07EH, OOOH ;
0_97
DB
OOOH,OCCH, 000H,OCCH,OCCH,07CH,OOCH, OF8H ;
0_98
DB
OC3H,018H, 03CH,066H,066H, 03CH,018H, OOOH ;
0_99
DB
OCCH,OOOH, OCCH,OCCH,OCCH, OCCH,078H, OOOH ;
0_9A
DB
018H,018H, 07EH,OCOH,OCOH, 07EH, 018H, 018H ;
0_9B
DB
038H,06CH, 064H,OFOH,060H,OE6H,OFCH, OOOH ;
0_9C
DB
OCCH, OCCH, 078H,OFCH,030H, OFCH,030H, 030H ;
0_90
DB
OF8H,OCCH, OCCH,OFAH,OC6H, OCFH, OC6H, OC7H ;
0_9E
DB
00EH,01 BH, 018H, 03CH,018H, 018H, 008H, 070H ;
0_9f
DB
01CH,000H, 078H,00CH,07CH, OCCH, 07EH,000H ;
O_AO
DB
038H, OOOH, 070H,030H,030H, 030H, 078H,OOOH ;
O_Al
DB
OOOH,OlCH, OOOH, 078H,OCCH, OCCH, 078H,000H ;
D_A2
DB
OOOH, 01CH, OOOH,OCCH,OCCH, OCCH, 07EH,OOOH ;
0_A3
DB
OOOH, Of8H,000H, OF8H,OCCH, OCCH, OCCH,OOOH ;
0_A4
DB
OfCH, OOOH, OCCH, OECH, OFCH, OOCH, OCCH,OOOH ;
0_A5
DB
03CH, 06CH, 06CH, 03EH, OOOH, 07EH, OOOH,OOOH ;
0_A6
DB
038H, 06CH,06CH,038H .. 000H, 07CH, OOOH,OOOH ;
0_A7
DB
030H, OOOH, 030H, 060H .. OCOH, OCCH, 078H,000H ;
D_AS
DB
OOOH, OOOH, OOOH .. OFCH,OCOH, OCOH, OOOH,OOOH ;
0_A9
DB
OOOH, OOOH, OOOH, OFCH, OOCH, OOCH, OOOH,OOOH ;
D_AA
DB
OC3H, OC6H, OCCH, 00EH .. 033H, 066H, OCCH,OOFH ;
D_AB
DB
OC3H, OC6H,OCCH, OOBH, 037H, 06FH, OCFH,003H ;
O_AC
DB
018H, 018H, 000H .. 018H, 018H, 018H, 018H,OOOH ;
D_AD
DB
OOOH, 033H, 066H,OCCH,066H, 033H, OOOH,OOOH ;
O_AE
DB
OOOH, OCCH, 066H .. 033H,066H, OCCH, OOOH, OOOH ;
O_Af
DB
022H, 088H, 022H,088H,022H .. 088H,022H, 088H ;
O_BO
DB
055H .. OAAH, 055H,OAAH,055H,OAAH,055H, OAAH ;
O_Bl
DB
ODBH, 077H, OOBH,OEEH,OOBH, 077H,00BH, OEEH ;
0_B2
DB
018H, 018H, 018H,018H, 018H,018H,018H, 018H ;
0_B3
DB
018H, 018H, 018H,018H,OF8H,018H,018H, 018H ;
0_B4
DB
018H, 018H, OF8H,018H,OF8H,018H,018H, 018H ;
0_B5
DB
036H, 036H, 036H,036H, OF6H,036H,036H, 036H ;
0_B6
D8
OOOH, OOOH, OOOH,OOOH,OFEH, 036H,036H, 036H ;
0_87
DB
000H,OOOH,OF8H,018H,OF8H,018H,018H,018H ;
0_88
D8
036H,036H, OF6H,006H, OF6H,036H, 036H,036H ;
0_B9
DB
036H,036H, 036H,036H, 036H, 036H, 036H,036H ;
D_BA
DB
OOOH,OOOH, OFEH,006H, OF6H, 036H, 036H,036H ;
0_B8
DB
036H,036H, OF6H,006H, OFEH, OOOH, OOOH,OOOH ;
O_BC
DB
036H,036H, 036H,036H, OFEH, OOOH, OOOH,OOOH ;
0_80
DB
018H,01 8H, OF8H,018H,OF8H, OOOH, OOOH,OOOH ;
O_BE
DB
OOOH,OOOH, OOOH,OOOH, OF8H, 018H, 018H,Ol8H ;
O_BF
DB
018H, 018H,018H, 018H,01 FH, OOOH,OOOH, OOOH ;
O_CO
DB
018H, 018H,018H, 018H,OFfH,OOOH,OOOH, OOOH ;
O_Cl
DB
OOOH, OOOH,OOOH,OOOH, OHH,018H,Ol8H, 018H ;
0_C2
DB
018H, 018H, 018H, 018H, 01 FH,018H, 018H,018H ;
0_C3
DB
OOOH, OOOH, OOOH,OOOH, OFF"H,OOOH, OOOH,OOOH ;
O_CIi-
DB
018H,018H, 018H,018H, OFFH,018H, 018H,018H ;
0_C5
DB
018H .. 018H, 01 FH,018H. 01 FH,018H, 018H,018H ;
0_C6
DB
036H,036H, 036H,036H, 037H, 036H,036H,036H ;
0_C7
DB
036H,036H, 037H,030H,03FH, OOOH,OOOH,OOOH ;
0_C8
D8
OOOH,OOOH, 03FH,030H,037H, 036H,036H,036H ;
0_C9
DB
036H,036H .. 0F1H, OOOH,OFfH,OOOH,OOOH, OOOH ;
D_C"
DB
OOOH,OOOH,OFFH, 000H,OF7H,036H,036H, 036H ;
O_CB
DB
036H, 036H,037H, 030H,037H,036H,036H .. 036H ;
O_CC
DB
OOOH, OOOH, OFFH, OOOH, OFFH, OOOH, OOOH, OOOH ;
D_CO
DB
036H,036H,0F1H,OOOH, OF7H, 036H,036H,036H ;
D_CE
mM Enhanced Graphics Adapter 163
0678
18 18 FF 00 FF 00
00 00
0680
36
00
00
18
00
36
36
00
18
00
00
18
00
36
36
36
18
18
18
00
00
18
FF
FF
00
Ff
FO
FO
OF
OF
FF
00
36
00
00
18
00
36
36
00
18
00
00
18
00
36
36
36
18
18
18
00
00
18
ff
FF
00
FF
FO
FO
OF
OF
FF
00
00
76
00
CO
00
CO
00
76 DC C8 DC
6C
FC
FC
00
70
00
60
00
18
FC
30
38
38
38
EE
1C
78
00
00
06
60
38
38
78
CC
00
00
78
CO
FC
00
FE
00
CC
00
00
00
66
CO
76
00
30
FC
6C
00
6C
00
30
00
00
00
DC
CO
60
00
CC
00
00
00
30
FC
60
FC
18
FC
OE
18
18
08
30
30
00
00
38
00
00
00
00
00
OF
3C
78
00
70
00
00
00
00
00
FC
00
30
00
30
00
30
00
18
18
18
10
30
00
76
00
6C
00
00
00
00
00
DC
1C
6C
00
18
00
00
00
00
00
00 FC 00 FC
0688
0690
0698
06AO
06A8
06BO
0688
06CO
06C8
0600
0608
06EO
06E8
06FO
06F8
0700
0708
0710
0718
0720
0728
0730
0738
0740
0748
0750
0758
0760
0768
0770
0778
0780
0788
0790
0798
07AD
07A8
0780
0788
07CO
07C8
0700
0708
07EO
07E8
07FO
07F8
0800
0000
0000
0000
36 36 FF 00
FF 00 FF 18
00 00 FF 36
36 36 3f 00
IF 18 1F 00
1F 18 1f 18
00 00 3f 36
36 36 FF 36
FF 18 FF 18
18 18 F8 00
00 00 1f 18
FF fF fF Ff
00 00 FF ff
FO FO FO FO
OF OF OF OF
FF FF 00 00
CC F8 CC F8
CC CO CO CO
6C 6C 6C 6C
60 30 60 CC
7E 08 08 08
66 66 66 7C
DC 18 18 18
78 CC CC 78
C6 FE C6 6C
C6 C6 6C 6C
18 1C CC CC
1E DB DB 1E
1E DB DB 1E
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
DB
018H,018H,OFFH,OOOH,OFFH,000H,000H,OOOH;
O_CF
DB
036H,036H,036H,036H,OfFH,000H,OOOH,OOOH;
0_00
08
000H,000H,OFFH,OOOH,OFFH,018H,018H,018H;
0_01
DB
OOOH,000H,000H,000H,OFFH,036H,036H,036H;
0_02
DB
036H, 036H, 036H, 036H,03FH, OOOH, OOOH, OOOH;
0_03
DB
018H, 018H, 01 FH, 018H, 01 FH, OOOH,OOOH, OOOH;
0_04
DB
000H,OOOH,OlfH,018H,OlfH,018H,018H,018H;
0_05
DB
OOOH, OOOH, OOOH,OOOH, 03 FH, 036H, 036H,036H;
0_06
DB
036H,036H,036H,036H,OFFH,036H,036H,036H;
0_07
DB
018H,018H,OFFH,018H,OFFH,018H,018H,018H;
0_08
DB
018H,018H,018H,018H,OF8H,000H,000H,OOOH;
0_09
DB
OOOH,OOOH,000H,000H,OlfH,018H,018H,018H;
o_oA
DB
OFFH,OFFH,OFFH,OFFH,OFFH,OFfH,OFfH,OFFH;
D_DB
DB
OOOH,OOOH,OOOH,OOOH,OFFH,OFFH,OFFH,OFFH;
D_DC
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
OFOH,OFOH,OFOH,OFOH,OFOH,OFOH,OFOH,OFOH;
0_00
DB
OOFH,OOFH,OOFH,OOFH,OOFH,OOfH,OOFH,OOFH;
D_DE
DB
OFFH,OffH,OfFH,OFFH,OOOH,OOOH,OOOH,OOOH;
O_OF
DB
OOOH, OOOH, 076H, OOCH, OC8H, OOCH, 076H, OOOH;
O_EO
DB
000H,078H,OCCH,OF8H,OCCH,OF8H,OCOH,OCOH;
O_El
DB
OOOH,OFCH,OCCH,OCOH,OCOH,OCOH,OCOH,OOOH;
0_E2
DB
000H,OFEH,06CH,06CH,06CH,06CH,06CH,000H:
0_E3
DB
OFCH,OCCH,060H,030H,060H,OCCH,OFCH,OOOH;
0_[4
DB
OOOH, OOOH, 07EH, 008H, 008H, 008H, 070H, OOOH;
D_E5
DB
OOOH, 066H, 066H,066H, 066H, 07CH, 060H,OCOH;
D_E6
DB
000H,076H,ODCH,018H,018H,018H,018H,OOOH;
0_£1
DB
OFCH, 030H, 078H, OCCH, OCCH, 018H, 030H, OFCH:
0_E8
DB
038H, 06CH, OC6H, OFEH, OC6H, 06CH, 038H, OOOH:
0_E9
DB
038H, 06CH, OC6H, OC6H, 06CH, 06CH, OEEH, OOOH;
O_EA
DB
01CH,030H,018H,07CH,OCCH,OCCH,078H,000H;
O_EB
DB
OOOH, OOOH, 07EH, ODBH, OOBH, 07EH, OOOH, OOOH;
o_EC
497
DB
006H, OOCH, 01EH, OOBH, OOBH, 07EH, 060H, OCOH:
O_EO
499
DB
038H, 060H, OCOH, OF8H, OCOH, 060H, 038H, OOOH;
O_EE
DB
078H, OCCH, OCCH,OCCH, OCCH, OCCH, OCCH, OOOH;
D_EF
DB
OOOH,OFCH,OOOH,OFCH,OOOH,OFCH,OOOH,OOOH;
D_FO
DB
030H,030H,OFCH,030H,030H,OOOH,OFCH,000H;
O_Fl
DB
060H, 030H, 018H,030H, 060H, OOOH, OFCH,OOOH;
0_F2
DB
018H,030H,060H,030H,018H,000H,OFCH,000H;
0_F3
DB
00EH,OlBH,OlBH,018H,018H,018H,018H,018H;
0_F4
DB
018H,018H,018H,018H,018H,OD8H,OD8H,070H;
D_F5
DB
030H, 030H, OOOH, OFCH, OOOH, 030H, 030H, OOOH:
D_F6
DB
OOOH, 076H, OOCH, OOOH, 076H, OOCH, OOOH, OOOH;
O_f7
DB
038H, 06CH, 06CH, 038H, OOOH, OOOH, OOOH, OOOH;
D_F8
DB
000H,OOOH,OOOH,018H,018H,OOOH,000H,000H;
OJ9
DB
000H,OOOH,OOOH,000H,018H,OOOH,000H,000H;
O_FA
DB
00FH,00CH,00CH,OOCH,OECH,06CH,03CH,01CH;
O_FB
DB
078H, 06CH, 06CH, 06CH,06CH, OOOH, OOOH, OOOH;
D_FC
DB
070H, 018H, 030H, 060H, 078H, OOOH, OOOH, OOOH;
D_FD
DB
OOOH, OOOH, 03CH, 03CH, 03CH, 03CH, OOOH, OOOH;
O_FE
DB
OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH,OOOH;
O_FF
498
CO F8 CO 60
CC CC CC CC
FC 30 30 00
18 30 60 00
60 30 18 00
lB 18 18 18
18 18 18 08
DO FC 00 30
DC 00 76 DC
6C 38 00 00
00 18 18 00
00 00 18 00
OC DC EC 6C
6C 6c 6C 00
30 60 78 00
3C 3C 3C 3C
00 00 00 00
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
CODE
ENDS
END
PAGE,120
SUBTTL END ADDRESS
SEGMENT PUBL I C
END_ADDRESS
6~gloOR~~~S
LABEL
BYTE
CODE
PUBU C
END
164 IBM Enhanced Graphics Adapter
August 2, 1984
Index
A
Attribute Address Register 56
Attribute Controller
description 3
registers 56
B
BIOS
description 4
vectors with special
meanings 103
BIOS listing 103
Bit Mask Register 54
c
character generator
ROM 1
Character Map Select
Register 21
Clocking Mode Register 19
Color Compare Register 48
Color Don't Care Register 53
color mapping 10
Color Plane Enable
Register 60
compatibility issues 74
configuration switches 80
CRT Controller
description 3
registers 24
CRT Controller Address
Register 24
CRT Controller Overflow
Register 30
Cursor End Register 33
Cursor Location High
Register 35
Cursor Location Low
Register 35
Cursor Start Register 32
D
Data Rotate Register 49
direct drive connector 83
display buffer 4
E
Enable Set/Reset Register 47
End Horizontal Blanking
Register 27
End Horizontal Retrace
Register 29
Index-l
End Vertical Blanking
Register 40
F
I
Input Status Register One 15
Input Status Register Zero 14
Interface 76
feature connector 76
feature connector 76
Feature Control Register 14
L
G
Graphics Controller
description 3
registers 45
Graphics 1 and 2 Address
Register 46
Graphics 1 Position
Register 45
Graphics 2 Position
Register 46
H
Horizontal Display Enable End
Register 26
Horizontal Pel Panning
Register 60
Horizontal Total Register 25
Index-2
Light Pen High Register 36
light pen interface 84
Light Pen Low Register 37
Line Compare Register 43
M
Map Mask Register 20
Maximum Scan Line
Register 32
Memory Mode Register 23
Miscellaneous Output
Register 12
Miscellaneous Register 52
Mode Control Register 41,58
Mode Register 50
modes
alphanumeric 8
graphics 8
IBM Color Display 5
IBM Enhanced Color
Display 6
IBM Monochrome
Display 6
o
Graphics Controller 45
Sequencer 18
Reset Register 18
Offset Register 38
Overscan Color Register 59
s
p
Palette Registers 57
Preset Row Scan Register 31
programming
considerations 62
compatibility issues 74
creating a split screen 73
creating a 512 character
set 70
creating an 80 by 43
alphanumeric mode 71
programming registers 62
RAM loadable character
generator 69
vertical interrupt feature 72
R
RAM loadable character
generator 69
Read Map Select Register 50
registers
Attribute Controller 56
CRT Controller 24
external 12
Sequencer
description 3
registers 18
Sequencer Address Register 18
Set/Reset Register 47
specifications 79
configuration switch
settings 81
configuration switches 80
direct drive connector 83
light pen interface 84
system board switches 79
Start Address High Register 34
Start Address Low Register 34
Start Horizontal Blanking
Register 26
Start Horizontal Retrace Pulse
Register 28
Start Vertical Blanking
Register 39
support logic 4
u
Underline Location
Register 39
Index-3
v
Vertical Display Enable End
Register 38
vertical interrupt feature 72
Index-4
Vertical Retrace End
Register 36
Vertical Retrace Start
Register 36
Vertical Total Register 30
Personal Computer
Hardware Reference
Library
mM Printer Adapter
6361507
ii
Contents
Description ....................................
Programming Considerations ......................
Specifications ..................................
Logic Diagrams .................................
1
3
7
9
iii
iv
Description
The IBM Printer Adapter is specifically designed to attach
printers with a parallel port-interface, but it can be used as a
general input/output port for any device or application that
matches its input/output capabilities. It has 12 TTL-buffer
output points, which are latched and can be written and read
under program control using the microprocessor In or Out
instruction. The adapter also has five steady-state input points
that may be read using the microprocessor's In instructions.
In addition, one input can also be used to create a microprocessor
interrupt. This interrupt can be enabled and disabled under
program control. A reset from the power-on circuit is also ORed
with a program output point, allowing a device to receive a
'power-on reset' when the system unit's microprocessor is reset.
The input/ output signals are made available at the back of the
adapter through a right-angle, printed-circuit-board-mounted,
25-pin, D-shell connector. This connector protrudes through the
rear panel of the system unit or expansion unit, where a cable may
be attached.
When this adapter is used to attach a printer, data or printer
commands are loaded into an 8-bit, latched, output port, and the
strobe line is activated, writing data to the printer. The program
then may read the input ports for printer status indicating when
the next character can be written, or it may use the interrupt line
to indicate "not busy" to the software.
The output ports may also be read at the card's interface for
diagnostic loop functions. This allows faults to be isolated to the
adapter or the attaching device.
This same function is also part of the IBM Monochrome Display
and Printer Adapter.
Printer Adapter 1
The following is a block diagram of the Printer Adapter.
25-Pin D-Shell
Connector
8
~U'BUff"8 .Data Latch
....
~
r
8
Trans- .....
...
ceiver
8
po
...
Enable
Clock
...
DIR
~
O.C.
Drivers
Read
Data
~
A
STROBE
Write Data
Command
Decoder
SLCTIN
po
AUTO
Write Control
FDXT
Read Status
-INIT
Read
Control
-
A
Control
Latch
Bus
Buffers
~ Enable
~ ..... Clock
rERROR
5
po
4
r
R eset
Printer Adapter Block Diagram
2 Printer Adapter
Enable
SLCT
r..
~ Clear
PE
ACK
BUSY
Programming Considerations
The Printer Adapter responds to five I/O instructions; two output
and three input. The output instructions transfer data into two
latches whose outputs are presented on pins of a 25-pin D-shell
connector.
Two of the three input instructions allow the system unit's
microprocessor to read back the contents of the two latches. The
third allows the system unit's microprocessor to read the real-time
status from a group of pins on the connector.
A description of each instruction follows.
Printer Adapter
Output to address hex 378
I
Bit 3
Pin 5
Bit 2
Pin 4
I
Bit 1
Pin 3
I
BitO
Pin 2
The instruction captures data from the data bus and is present on
the respective pins. Each of these pins is capable of sourcing 2.6
rnA and sinking 24 rnA.
It is essential that the external device does not try to pull these
lines to ground.
Printer Adapter
Output to address hex 37 A
Bit3
Bit 2
Bit 1
BitO
Pin 17
Pin 16
Pin 14
Pin 1
This instruction causes the latch to capture the five least
significant bits of the data bus. The four least significant bits
present their outputs, or inverted versions of their outputs, to the
Printer Adapter 3
respective pins as shown in the previous figure. If bit 4 is written
as aI, the card will interrupt the system unit's microprocessor on
the condition that pin 10 changes from high to low.
These pins are driven by open-collector drivers pulled to +5 Vdc
through 4.7 kQ resistors. They can each sink approximately 7 rnA
and maintain 0.8 volts down-level.
Printer Adapter
Input from address hex 378
This instruction presents the system unit's microprocessor with
data present on the pins associated with the output to hex 3BC.
This should normally reflect the exact value that was last written
to hex 3BC. If an external device should be driving data on these
pins at the time of an input (in violation of usage ground rules),
this data will be ORed with the latch contents.
Printer Adapter
Input from address hex 379
This instruction presents the real-time status to the system unit's
microprocessor from the pins, as follows.
BitO
Printer Adapter
Input from address hex 37 A
4 Printer Adapter
This instruction causes the data present on pins 1, 14, 16, 17, and
the IRQ bit to be read by the system unit's microprocessor. In
the absence of external drive applied to these pins, data read by
the system unit's microprocessor will match data last written to
hex 3BE in the same bit positions. Notice that data bits 0-2 are
not included. If external drivers are dotted to these pins, that
data will be ORed with data applied to the pins by the hex 3BE
latch.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BitO
IRQ
Enable
Pin 17
Pin 16
Pin 14
Pin 1
Por=O
Por= 1
Por=O
Por = 1
Por= 1
These pins assume the states shown after a reset from the system
unit's microprocessor.
Printer Adapter 5
6 Printer Adapter
Specifica tions
25-Pin D-Shell
Connector
o
•
•
•
•
•
•
•
••
••
•
•
13
•
•
•
•
•
•
•
•
•
••
•
14
25
o
At Standard TTL Levels
Printer
Signal
Adapter
Name
Pin Number
- Strobe
1
+
+
+
+
+
+
+
+
2
Data Bit 0
Data Bit 1
3
Data Bit 2
4
Data Bit 3
5
Data Bit 4
6
Data Bit 5
7
Data Bit 6
8
Data Bit 7
9
Printer
- Acknowledge
10
Adapter
+ Busy
+ P.End (out of paper)
+ Select
12
13
- Auto Feed
14
- Error
15
- Initialize Printer
16
- Select Input
Ground
11
17
18-25
Connector Specifications
Printer Adapter 7
8 Printer Adapter
Logic Diagrams
The following page contains the logic diagram for the IBM Printer
Adapter.
Printer Adapter 9
~""
,~ -"--NO ..
---..-
~
."
,
oM
!:, '"
~LFrE5~J'"
...
~
.. .-. "
- -~'
.: "'
..~
tf
ri'
~
fTTT~
,
,
~
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Personal Computer
Hardware Reference
Library
mM 5-114" Diskette
Drive Adapter
6361505
ii
Contents
Description .................................... 1
Programming Considerations ...................... 3
Digital-Output Register ...................... 3
Floppy Disk Controller ....................... 4
Command Summary ......................... 8
Programming Summary ...................... 17
Interface ..................................... 19
System 110 Channel Interface ................ 19
Drive A and B Interface ..................... 20
Specifications ................................. 23
Logic Diagrams ................................ 25
iii
iv
Description
The IBM 5-1/4" Diskette Drive Adapter fits into one of the
expansion slots in the system unit. It is connected to one or two
diskette drives through an internal, daisy-chained flat cable. The
adapter has a connector at the other end that extends through the
rear panel of the system unit. This connector has signals for two
additional external diskette drives; thus, the 5-1/4 inch diskette
drive adapter can attach four 5-1/4 inch drives - two internal
and two external.
The adapter is designed for double-density, MFM-coded, diskette
drives and uses write precompensation with an analog phase-lock
loop for clock and data recovery. The adapter is a
general-purpose device using the NEC fLPD765 or equivalent
controller. Therefore, the diskette drive parameters are
programmable. In addition, the attachment supports the diskette
drive's write-protect feature. The adapter is buffered on the I/O
bus and uses the system board's direct memory access (DMA) for
record data transfers. An interrupt level also is used to indicate
when an operation is complete and that a status condition requires
microprocessor attention.
In general, the 5-1/4 inch diskette drive adapter presents a
high-level command interface to software I/O drivers.
Diskette Adapter 1
.
Clock
and
Timing
Circuit
•
1
•
~
Buffer
I'r- r-v'
NEC
Floppy
Disk
Controller
Data
VCO SYNC· Separator
STD. DATA
Data Window
I
Write Data
t'--
.../
<}-
I-I-
f
Step
Direction
Write Enable
Head Select
Index
V
V
iRes~t
INTR.
Read Data
""
"'-.J
./1
Digital
Control
Port
~
Write
I Data
I""
~
Write
Precompensate
Circuit
"
, ,
~-
Write Protect
'-J
Track 0
Drive A Motor On
'1
f-- B
f--C
Decoder f--D
Drive A Select
I-- B
f-- C
I-- D
5-1/4 Inch Diskette Drive Adapter Block Diagram
Programming Considerations
This attachment consists of an 8-bit digital output register in
parallel with a NEe p.PD765 or equivalent floppy disk controller
(FDe).
In the following description, drive numbers 0, 1,2, and 3 are
equivalent to drives A, B, e, and D.
Digital-Output Register
The Digital-Output register (DOR) is an output-only register used
to control drive motors, drive selection, and feature enable. All
bits are cleared by the I/O interface 'reset' line. The bits have the
following functions:
Bits 0 and 1
These bits are decoded by the hardware to
select one drive if its motor is on:
Bit 1 0
00
Drive
0 (A)
10
2 (e)
11
3 (D)
o1
1 (B)
Bit 2
The FDe is held reset when this bit is clear.
It must be set by the program to enable the
FDe.
Bit 3
This bit allows the FDe interrupt and DMA
requests to be gated onto the 110 interface.
If this bit is cleared, the interrupt and DMA
request 110 interface drivers are disabled.
Bits 4,5,6,
and 7
These bits control, respectively, the motors of
drives 0, 1,2 (A, B, e), and 3 (D). If a bit is
clear, the associated motor is off, and the
drive cannot be selected.
Diskette Adapter 3
Floppy Disk Controller
The floppy disk controller (FDC) contains two registers that may
be accessed by the system unit's microprocessor: a status register
and a data register. The 8-bit main status register contains the
status information of the FDC and may be accessed at any time.
The 8-bit data register (actually consisting of several registers in a
stack with only one register presented to the data bus at a time)
stores data, commands, parameters, and provides floppy disk
drive (FDD) status information. Data bytes are read from or
written to the data register in order to program or obtain results
after a particular command. The main status register can only be
read and is used to facilitate the transfer of data between the
system unit's microprocessor and FDC.
The bits in the main status register (hex 34F) are defined as
follows:
Bit
Number
Name
Symbol
Description
DBO
FDD A Busy
DAB
FDD number 0 is in the Seek mode.
DB1
FDD B Busy
DBB
FDD number 1 is in the Seek mode.
DB2
FDD C Busy
DCB
FDD number 2 is in the Seek mode.
DB3
FDD 0 Busy
DDB
FDD number 3 is in the Seek mode.
DB4
FOC Busy
CB
A read or write command is in process.
DB5
Non-DMA
Mode
NDM
The FDC is in the non-DMA mode.
DB6
Data Inputl
Output
010
Indicates direction of data transfer
between FDC and processor. If DIO =" 1;'
then transfer is from FDC data register to
the processor. If 010 = "0;' then transfer
is from the processor to FDC data register.
DB7
Request for
Master
ROM
Indicates data register is ready to send or
receive data to or from the processor. Both
bits 010 and ROM should be used to
perform the handshaking functions of
"ready" and "direction" to the processor.
The FDC is capable of performing 15 different commands. Each
command is initiated by a multi-byte transfer from the system
unit's microprocessor, and the result after execution of the
command may also be a multi-byte transfer back to the system
4 Diskette Adapter
unit's microprocessor. Because of this multi-byte interchange of
information between the FDC and the system unit's
microprocessor, it is convenient to consider each command as
consisting of three phases:
Command Phase
The FDC receives all information required to perform a particular
operation from the system unit's microprocessor.
Execution Phase
The FDC performs the operation it was instructed to do.
Result Phase
After completion of the operation, status and other housekeeping
information are made available to the system unit's
microprocessor.
The following tables define the symbols used in the command
summary. The command summary immediately follows these
tables.
Diskette Adapter 5
Symbol
Description
Name
AO
Address Line 0
AO controls selection of main status
register (AO = 0) or data register (AO = 1).
C
Cylinder Number
C stands for the current/selected cylinder
(track) number of the medium.
D
Data
D stands for the data pattern that is going
to be written into a sector.
07-00
Data Bus
8-bit data bus, where 07 stands for a
most significant bit, and DO stands for a
least significant bit.
OTL
Data Length
When N is defined as 00, OTL stands for
the data length that users are going to
read from or write to the sector.
EOT
End of Track
EOT stands for the final sector number on
a cylinder.
GPL
Gap Length
GPL stands for the length of gap 3
(spacing between sectors excluding VCO
sync field).
H
Head Address
H stands for head number 0 or 1, as
specified in ID field.
HD
Head
HO stands for a selected head number 0
or 1. (H = HD in all command words).
HLT
Head Load Time
HLT stands for the head load time in the
FDD (4 to 512 ms in 4-ms increments).
HUT
Head Unload Time
HUT stands for the head unload time after
a read or write operation has occurred (0
to 480 ms in 32-ms increments).
MF
FM or MFM Mode
If MF is low, FM mode is selected; if it is
high, MFM mode is selected only if MFM
is implemented.
MT
Multi-Track
If MT is high, a multi-track operation is to
be performed. (A cylinder under both HOO
and HD 1 will be read or written.)
N
Number
N stands for the number of data bytes
written in a sector.
Symbol Descriptions (Part 1 of 2)
6 Diskette Adapter
.
Symbol
Name
Description
NCN
New Cylinder
Number
NCN stands for a new cylinder number,
which is going to be reached as a result
of the seek operation. (Desired position of
the head.)
ND
Non-DMA Mode
ND stands for operation in the non-DMA
mode.
PCN
Present Cylinder
Number
PCN stands for cylinder number at the
completion of sense-interrupt-status
command indicating the position of the
head at present time.
R
Record
R stands for the sector number, which
will be read or written.
R/W
Read/Write
R/W stands for either read (R) or write
(W) signal.
SC
Sector
SC indicates the number of sectors per
cylinder.
SK
Skip
SK stands for skip deleted-data address
mark.
SRT
Step Rate Time
SRT stands for the stepping rate for the
FDD (2 to 32 ms in 2-ms increments).
STO
ST 1
ST 2
ST 3
Status
Status
Status
Status
STO-3 stand for one of four registers that
store the status information after a
command has been executed. This
information is available during the result
phase after command execution. These
registers should not be confused with the
main status register (selected by AO = 0).
ST 0-3 may be read only after a command
has been executed and contain
information relevant to that particular
command.
STP
Scan Test
During a scan operation, if STP = 1, the
data in contiguous sectors is compared
byte-by-byte with data sent from the
processor (or DMA), and if STP = 2, then
alternate sectors are read and compared.
USO,
US1
Unit Select
US stands for a selected drive number
encoded the same as bits 0 and 1 of the
digital output register (DOR).
0
1
2
3
Symbol Descriptions (Part 2 of 2)
Diskette Adapter 7
Command Summary
In the following table, 0 indicates "logical 0" for that bit, 1 means
"logical 1," and X means "don't care."
Phase
R/W
Data Bus
D7 D6 D5 D4 D3 D2 D1
DO
Remarks
Read Data
Command
W
W
MT MF SK
X
X
X
w
0
0
X
X
1
1
HD US1
0
C
H
R
N
EOT
GPL
DTL
W
W
W
W
W
W
Execution
Result
R
R
R
R
R
R
R
STO
ST 1
ST 2
C
H
R
N
Command
W
W
W
W
W
W
W
W
W
Read Deleted Data
0
MT MF SK 0
1
1
0
X
X
X
X
X HDUS1USO
C
H
R
N
EOT
GPL
DTL
Execution
Result
R
R
R
R
R
R
R
8 Diskette Adapter
STO
ST 1
ST 2
C
H
R
N
Command Codes
usa
Sector ID information
prior to command
execution.
Data transfer
between the FDD
and main system.
Status information
after command
execution.
Sector ID information
after command
execution.
Command Codes
Sector ID information
prior to command
execution.
Data transfer
between the FDD
and main system.
Status information
after command
execution.
Sector ID information
after command
execution.
Data Bus
Phase
R/W
07 06 05 04 03 02 01 DO
Remarks
Write Data
Command
W
W
W
W
W
W
W
W
W
MT MF
X
X
0
X
a a
X
1
a
1
Sector 10 information
prior to command
execution.
C
H
R
N
EOT
GPL
OTL
Data transfer
between the main
system and FOO.
Status information
after command
execution.
Sector 10 information
after command
execution.
Execution
Result
R
R
R
R
R
R
R
Command
W
W
w
W
W
W
W
W
W
a
ST
ST 1
ST 2
C
H
R
N
Write Deleted Data
1
1
X X X X HO US1 usa
C
H
R
N
EOT
GPL
OTL
MT MF
X
a a
Execution
Result
R
R
R
R
R
R
R
Command Codes
X HO US1 usa
STa
ST 1
ST 2
C
H
R
N
a a
Command Codes
Sector 10 information
prior to command
execution.
Data transfer
between the FOD and
main system.
Status 10 information
after command
execution.
Sector 10 information
after command
execution.
Diskette Adapter 9
Oata Bus
Phase
Command
R/W
W
W
07 06 05 04 03 02 01 00
0
X
w
W
W
W
W
W
W
Read a Track
MF SK 0
0
0
1
X
X
X
X HO US1
C
H
R
N
EOT
GPL
DTL
0
R
R
R
R
R
R
R
Command
W
W
Sector ID information
prior to command
execution.
Data transfer
between the FDD
and main system.
FDC reads all of
cylinder's contents
from index hole to
EOT.
Status information
after command
execution.
Sector ID information
after command
execution.
STO
ST 1
ST 2
C
H
R
N
0
X
MF
X
0
X
Read 10
0
1
0
1
X
X HD US1
Execution
Result
R
R
R
R
R
R
R
10 Diskette Adapter
STO
ST 1
ST 2
C
H
R
N
Command Codes
usa
Execution
Result
Remarks
0
Command Codes
usa
The first correct ID
information on the
cylinder is stored in
data register.
Status information
after command
execution.
Sector ID information
during execution
phase.
Oata Bus
Phase
Command
R/W
W
W
W
W
W
W
07 06 05 04 03 02 01 00
0
X
MF
X
Format a Track
0
0
1
1
0
X
X
X HD US1
N
SC
GPL
D
0
R
R
R
R
R
R
R
Command
W
W
Bytes/Sector
Sector/Track
Gap 3
filler byte.
FDC formats an
entire cylinder.
Status information
after command
execution.
In this case, the ID
information has no
meaning.
w
W
W
W
W
W
W
STO
ST 1
ST 2
C
H
R
N
MT MF SK
X
X
X
Scan Equal
1
0
0
X
X
C
H
R
N
EOT
GPL
STP
Execution
Result
R
R
R
R
R
R
R
STO
ST 1
ST 2
C
H
R
N
0
HD US1
Command Codes
usa
Execution
Result
Remarks
1
Command Codes
usa
Sector ID information
prior to command
execution.
Data compared
between the FDD
and the main system.
Status information
after Command
execution.
Sector ID information
after command
execution.
Diskette Adapter 11
Oata Bus
Phase
Command
R/W
W
W
w
W
W
W
W
W
W
07 06 05 04 03 02 01 00
Scan Low or Equal
MT MF SK 1
1
0
0
X X X X X HD US1
C
H
R
1
Command
Sector 10 information
prior to command
execution.
N
EOT
GPL
STP
R
R
R
R
R
R
R
W
W
w
W
W
W
W
W
W
Data compared
between the FDD
and main system.
Status information
after command
execution.
Sector 10 information
after command
execution.
STO
ST 1
ST 2
C
H
R
N
Scan High or Equal
1
MT MF SK 1
1
0
X X X X X HD US1
C
H
R
R
R
R
R
R
R
R
12 Diskette Adapter
1
Command Codes
usa
Sector 10 information
prior to command
execution.
N
EOT
GPL
STP
Execution
Result
Command Codes
usa
Execution
Result
Remarks
STO
ST 1
ST 2
C
H
R
N
Data compared
between the FDD
and main system.
Status information
after command
execution.
Sector 10 information
after command
execution.
Data Bus
Phase
Command
R/W
W
W
07 06 05 04 03 02 01 DO
0
0
X
X
Recalibrate
0
1
1
1
0
X
X
0 US1USO
X
0
Execution
No Result
Phase
Remarks
Command Codes
Head retracted to
track 0
Command
Result
W
R
R
Command
W
W
W
0
Sense Interrupt Status
0
0
1
0
0
0
STO
PCN
Specify
0
0
0
0
0
t--SRT
HLT
0
0
1
1
HUTND
Command Codes
Status information at
the end of seek
operation about the
FOC
Command Codes
No Result
Phase
Command
Result
Command
Sense Drive Status
0
0
1
0
0
X
X
X
X HO US1
ST 3
W
W
R
0
W
W
0
0
0
Seek
0
1
X
X
X
X
w
X
0
X
1
1
HO US1
0
Command Codes
usa
Status information
about FDD.
1
Command Codes
usa
NCN
Execution
Head is positioned
over proper cylinder
on diskette.
No Result
Phase
Command
W
Invalid
Invalid Codes
Result
R
STO
Invalid command
codes (NoOp - FOC
goes into standby
state).
ST 0: 80.
Diskette Adapter 13
Bit
No.
Name
Symbol
D7
Description
D7 = 0 and D6 = 0
Normal termination of command (NT).
Command was completed and properly
executed.
D7 = 0 and D6 = 1
Abnormal termination of command (AT).
Execution of command was started, but
was not successfully completed.
D7 = 1 and D6 = 0
Invalid command issue (IC). Command
that was issued was never started.
D7 = 1 and D6 = 1
Abnormal termination because, during
command execution, the ready signal
from FDD changed state.
Interrupt
Code
IC
D5
Seek End
SE
When the FDC completes the seek
command, this flag is set to 1 (high).
D4
Equipment
Check
EC
If a fault signal is received from the
FDD, or if the track 0 signal fails to occur
after 77 step pulses (recalibrate
command), then this flag is set.
D3
Not Ready
NR
When the FDD is in the not-ready state
and a read or write command is issued,
this flag is set. If a read or write command
is issued to side 1 of a single-sided drive,
then this flag is set.
D2
Head Address
HD
This flag is used to indicate the state of
the head at interrupt.
D1
DO
Unit Select 1
Unit Select 0
US 1
usa
These flags are used to indicate a drive
unit number at interrupt.
D6
Command Status Register 0
14 Diskette Adapter
Bit
No.
D7
Name
End of
Cylinder
Symbol
EN
Description
When the FDC tries to access a sector
beyond the final sector of a cylinder, this
flag is set.
D6
-
-
Not used. This bit is always 0 (low).
D5
Data Error
DE
When the FDC detects a CRC error in
either the ID field or the data field, this
flag is set.
D4
Over Run
OR
If the FDC is not serviced by the main
system during data transfers within a
certain time interval, this flag is set.
D3
-
-
Not used. This bit is always 0 (low).
D2
No Data
ND
During execution of a read data, write
deleted data, or scan command, if the
FDC cannot find the sector specified in
the ID register, this flag is set. During
execution of the read ID command, if the
FDC cannot read the ID field without an
error, then this flag is set. During the
execution of the read a cylinder
command, if the starting sector cannot be
found, then this flag is set.
D1
Not Writable
NW
During execution of a write data, write
deleted data, or format-a-cylinder
command, if the FDC detects a
write-protect signal from the FDD, then
this flag is set.
DO
Missing
Address
Mark
MA
If the FDC cannot detect the ID address
mark, this flag is set. Also, at the same
time, the MD (missing address mark in
the data field) of status register 2 is set.
Command Status Register 1
Diskette Adapter 15
Bit
No.
Name
Symbol
Description
D7
-
-
Not used. This bit is always 0 (low).
D6
Control Mark
CM
During execution of the read data or scan
command, if the FDC encounters a sector
that contains a deleted data address
mark, this flag is set.
D5
Data Error in
Data Field
DD
If the FDC detects a CRC error in the data,
then this flag is set.
D4
Wrong
Cylinder
WC
This bit is related to the ND bit, and when
the contents of C on the medium are
different from that stored in the ID
register, this flag is set.
D3
Scan Equal
Hit
SH
During execution of the scan command, if
the condition of "equal" is satisfied, this
flag is set.
D2
Scan Not
Satisfied
SN
During execution of the scan command,
if the FDC cannot find a sector on the
cylinder that meets the condition, then
this flag is set.
D1
Bad Cylinder
BC
This bit is related to the N D bit, and when
the contents of C on the medium are
different from that stored in the ID
register, and the contents of C is FF, then
this flag is set.
DO
Missing
Address Mark
in Data Field
MD
Command Status Register 2
16 Diskette Adapter
When data is read from the medium, if
the FDC cannot find a data address mark
or deleted data address mark, then this
flag is set.
Bit
No.
Name
Symbol
Description
07
Fault
FT
This bit is the status of the fault signal
from the FDD.
06
Write
Protected
WP
This bit is the status of the
write-protected signal from the FDD.
05
Ready
RY
This bit is the status of the ready signal
from the FDD.
04
Track 0
TO
This bit is the status of the track 0 signal
from the FDD.
03
Two Side
TS
This bit is the status of the two-side
signal from the FDD.
02
Head Address
HD
This bit is the status of the side-select
signal from the FDD.
01
Unit Select 1
US 1
This bit is the status of the unit-select-1
signal from the FDD.
DO
Unit Select 0
USO
This bit is the status of the unit-select-O
signal from the FDD.
Command Status Register 3
Programming Summary
FDC Data Register
I/O Address Hex 3F5
FDC Main Status Register
I/O Address Hex 3F4
Digital Output Register
I/O Address Hex 3F2
BitO
1
2
3
4
5
6
7
Drive
00: DR #A 10: DR #C
Select
01:DR#B 11 : DR #0
Not FDC Reset
Enable INT & DMA Requests
Drive A Motor Enable
Drive B Motor Enable
Drive C Motor Enable
Drive 0 Motor Enable
All bits cleared with channel reset.
OPC Registers
Diskette Adapter 17
FDC Constants (in hex)
N:
SC:
HUT:
SRT:
02
08
F
C
GPL Format: 05
GPLR/W:
2A
HLT:
01
(6 ms track-to-track)
Drive Constants
Head Load
Head Settle
Motor Start
35 ms
15 ms
250 ms
Comments
•
Head loads with drive select, wait HD load time before R/W.
•
Following access, wait HD settle time before R/W.
•
Drive motors should be off when not in use. Only A or Band
Cor D may run simultaneously. Wait motor start time before
R/W.
•
Motor must be on for drive to be selected.
•
Data errors can occur while using a home television as the
system display. Placing the TV too close to the diskette area
can cause this to occur. To correct the problem, move the TV
away from, or to the opposite side of the system unit.
18 Diskette Adapter
Interface
System 1/0 Channel Interface
All signals are TTL-compatible:
Most Positive Up Level
Least Positive Up Level
Most Positive Down Level
Least Positive Down Level
+5.5 Vdc
+2.7Vdc
+0.5 Vdc
-0.5 Vdc
The following lines are used by this adapter.
+00-7
(Bidirectional, Load: 1 74LS, Driver: 74LS 3-state):
These eight lines form a bus through which all
commands, status, and data are transferred. Bit 0 is
the low-order bit.
+AO-9
(Adapter input, Load: 1 74LS): These 10 lines form an
address bus by which a register is selected to receive or
supply the byte transferred through lines DO-7. Bit 0
is the low-order bit.
+AEN
(Adapter input, load: 1 74LS): The content of lines
AO-9 is ignored if this line is active.
-lOW
(Adapter input, Load: 1 74LS): The content of lines
DO-7 is stored in the register addressed by lines AO-9
or DACK2 at the trailing edge of this signal.
-lOR
(Adapter input, Load: 1 7 4LS): The content of the
register addressed by lines AO-9 or DACK2 is gated
onto lines DO-7 when this line is active.
-DACK2 (Adapter input, load: 2 74LS): This line being active
degates output DRQ2, selects the FDC data register as
the source or destination of bus DO-7, and indirectly
gates T / C to IRQ6.
Diskette Adapter 19
+T/C
(Adapter input, load: 4 74LS): This line along with
DACK2 being active indicates that the byte of data for
which the DMA count was initialized is now being
transferred.
+RESET (Adapter input, load: I 74LS): An up level ends any
operation in process and clears the digital output
register (DOR).
+DRQ2 (Adapter output, driver: 74LS 3-state): This line is
made active when the attachment is ready to transfer a
byte of data to or from main storage. The line is made
inactive by DACK2 becoming active or an I/O read of
the FDC data register.
+IRQ6
(Adapter output, driver: 74LS 3-state): This line is
made active when the FDC has completed an
operation. It results in an interrupt to a routine that
should examine the FDC result bytes to reset the line
and determine the ending condition.
Drive A and B Interface
All signals are TTL-compatible:
Most Positive Up Level
Least Positive Up Level
Most Positive Down Level
Least Positive Down Level
+ 5.5 Vdc
+ 2.4 Vdc
+ 0.4 Vdc
- 0.5 Vdc
All adapter outputs are driven by open-collector gates. The
drives must provide termination networks to Vcc (except 'motor
enable', which has a 2,000-ohm resistor to Vcc).
Each adapter input is terminated with a I 50-ohm resistor to Vcc.
20 Diskette Adapter
Adapter Outputs
-Drive Select A and B
(Driver: 7438): These two lines are
used by drives A and B to degate all
drivers to the adapter and receivers
from the attachment (except 'motor
enable') when the line associated
with a drive is inactive.
- Motor Enable A and B
(Driver: 7438): The drive associated
with each of these lines must control
its spindle motor such that it starts
when the line becomes active and
stops when the line becomes
inactive.
-Step
(Driver: 7438): The selected drive
moves the read/write head one
cylinder in or out per the direction
line for each pulse present on this
line.
-Direction
(Driver: 7438): For each recognized
pulse of the 'step' line, the
read/write head moves one cylinder
toward the spindle if this line is
active, and away from the spindle if
inactive.
- Head Select
(Driver: 7438): Head 1 (upper
head) will be selected when this line
is active (low).
-Write Data
(Driver: 7438): For each
inactive-to-active transition of this
line while 'write enable' is active, the
selected drive causes a flux change
to be stored on the diskette.
-Write Enable
(Driver: 7348): The drive disables
write current in the head unless this
line is active.
Diskette Adapter 21
Adapter Inputs
-Index
The selected drive must supply one pulse per
diskette revolution on this line.
- Write Protect
The selected drive must make this line active
if a write-protected diskette is in the drive.
-Track 0
The selected drive must make this line active
if the read/write head is over track O.
-Read Data
The selected drive supplies a pulse on this
line for each flux change encountered on the
diskette.
22 Diskette Adapter
Specifications
34- Pin Keyed
Edge Connector
Component
Side
Note: Lands 1-33 (odd numbers) are on the back of the
board. Lands 2-34 (even numbers) are on the front. or
component side.
At Standard TTL Levels
Land Number
Ground-Odd Numbers
1-33
Unused
2.4.6
Index
8
Motor Enable A
10
Drive Select B
12
Drive Select A
14
Motor Enable B
16
Diskette
Direction (Stepper Motorl
18
Drive
Drives
Step Pulse
20
Adapter
Write Data
22
Write Enable
24
Track 0
26
Write Protect
28
Read Data
30
Select Head 1
32
Unused
34
Connector Specifications (Part 1 of 2)
Diskette Adapter 23
37-Pin D-Shell
Connector
o
1 • • 20
19
• 37
o
At Standard TTL levels
Pin Number
Unused
1-5
Index
6
Motor Enable C
7
Drive Select D
Drive Select C
8
9
Motor Enable D
10
Direction (Stepper Motor)
11
External
Step Pulse
12
Drive
Drives
Write Data
13
Adapter
Write Enable
14
Track 0
15
Write Protect
16
Read Data
17
Select Head 1
18
Ground
20-37
Connector Specifications (Part 2 of 2)
24 Diskette Adapter
(2)
+ El'A8LE DRtVE 314
!2)
- ENABl.E DAM 314
(2)
_ DRIVE SELECT 1
- DftM SELECT 2
_ MOTOR ENA8LE 1
_ MOTOR ENABlE 2
+",11> 2118
(21
(2)
(2)
~~~~~~~~~~~~~~~~~~~~~"~-g"~"~-'~~i:
~:I~~~~o~,~~~~~~~ ~~'i'§~~~+INDEX
II>
:;
+ IoORITEPI'IOTECT (3)
t31
+ 1R,"CII 0
:::
'"
'"
'"
(S)
+ WRITE DATA
lSI
+ WRITE ENABlE
(2)
_ DRIVE SELECT 3
!2)
_ DflIV£SELECT4
_ MOTOftENABl.E3
(2)
(2)
_ MOTOR ENABLE 4
~~~~g~,
10
+'"
I
11>2K 3
8'16-1
RP-2
1/4'"
~
PROCESSOR
"
SIGNALS ON DRIVE PINS 10 THRU II> ARE SWAPPED BV THE DRIVE (ABLE
:~
:~
TIO
:~
:~
14
12
I')
II
II> TO
10
DR[VES3&4
NOTES I &2
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ALL DRiVES ARE JUMPERED FOR MULTIPLO OPERAT[ON. HEAD LOAD
WITH DRIVE SELECT AND DRIVE SELECT ViA INPUT PIN 12. TERMINATlNG
:g~
.0'11 ",FO SHOULD BE ADJACENT TO MODU~ES MC ,'161. 1'+.8. 7451'1.lbMHZOSC.
RI'-I.I1C'I0'fI.11{'I02'I,74L5Ibl&74LSI'I1 B.2"Fl)CAPSSHOULD8ENEARAS'i)(lATED~ PltlS
'"
ALL SlGtlAL UNES H["HER THAN OR EQUAL TO IMHZ SHOULD BE IIEPT TO THE
SHORTEST 'POSSIBLE LENGTH. THIS IS A PRIMARV DESIGN GOAL
')
MAKE NO CONNEClIOt< TO UNUSED PINS ON 1HE VCO. CHARGE PUMP & DATA SEI'!!IRATOR MODULES
b
ALL VOLTAGE AND (,ROUtlD eONtiECTIONS TO THE veo. CHARGE PUMP AND ASSOCIATED DISCRETE
COMPONENTS SHOULD 6E SEPARATE FROM OTHER CIRCUITS AND THEN JOINED TO THE OTHER
CiRCUITS AT ONE POINT
5-1/4 Inch Diskette Drive Adapter (Sheet 1 of 4)
+AO
+A1
+A2
.. A3
+A4
+A5
+A6
+A7
.. A6
+A9
+AEN
-lOR
(ll
12)
:~~ET
l!:
_ +TC
_ _ +00
+01
+02
_ _ _ +03
.. 04
_ _ _ +05
_ _ +06
(2)
(2)
(2)
(2)
(2)
(2)
(2)
t2}
(2)
(2)
(3)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
_ _ _ +07
(2)
_ _ _ OACK2 (3)
~~...L---~~
GATE-
''""
'"
(1)
+A<;
11,
+Ab
(1)
(1)
(1)
+A7
+AB
+A9
7"LG~
+AZ
~
'~13
,"'mJ
----r---;======4::j"tl--'
II
10 7'+LS12 8
7LtlS01t
+RESET
K:~'
----1-1---------''-1
2
UI2
~
q
g;
6
:; 1:
~llq
I~Kt
~7
7'+:18,
I,
'"
,I
DRIVE SELECT 3
UZ9
Ag~ ~I;~~~lll
:~
~
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~ ===it g~
1
, 74~~ L
~'SO»'~'----l1~~:~~,'~"r,'~~~====jt=L~~~----------rV
L __ -.JuIS
u"
U 13
(1)
,I,
u,"
~
(11
+ENABLE DRIVE 3/4
ENABLE DRIVE 314
,,
,
&
tH2
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U 14
~
17~3a-"1
~Ir'''-'--++---~=--=--=":i:'t-=!L.fT''------------
!~I
~
:7'*'18-":
lr
2~
I
3
LJ-______-l-____________-W+t:j,,:tl:[)~~"'------------MOTORENA8LEl
J2
7'+38-4
J
Ll--______+-__________--+-lJ:::~,,~l:[).__t-'·'------------MOTOA
__ ..J
9
1"38-'1
'"
'"
(t)
ENABLE 2 (1)
U ..
91
L-l-____________________-W===::l,,4=:[)~.lL-----------MOTOR
7'1'18-'118
p,
-DA"
(3) Dl.CK<
.00
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'" 'D'
'"'"'" 'D'
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'"'" .D7
.02
12
~
14i8--I
L---t====================~==jt~==~~"=----------L_---1ulS
13
ENABLE 3 (1)
j'
MQTORENABLE4 (1)
.",
'''"""
(1)
'"
."
HO
-IOR
5-1/4 Inch Diskette Drive Adapter (Sheet 2 of 4)
''""
,
r
,
IK~~~
D I~(~
MR2
~
7
=
.".
NOTE
"
5J
+!NOEX
III + WR'lTE PROTECT
I CLF
7
74lS10'l
U2
c8J
2
.,
III
.2 8
-
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14
CPI
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PO
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~-~CLKI
n
10
~~
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Qi
= IS CLR
14LS10"
U2
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----3!
We<
wDA '>0
1<1 ClK
PSO 12
PSI 11
.-"
,
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1~ FLT/TRO
II
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IB
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E8
-'4 SO
2
51
74lSIS'>
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SEEK "3"
.. 74LSOB
8
UIO
,
,
10
+WRITE ENABLE III
+STEP
III
""
USI t2t;- N(
MF .... p-NC
+V FO SYNC
_____--------------------------------~,
+DACK & TC
lC~ ~~
74LSOB
HO 27
SfANDARDOATAiCLK
+OATA WINDOW
,
III
r-'!---
,
,
U4
(4)
(4)
+WRITE DATA III
+ DIRECTION
IrEA
USO~NC
I 74lS0B
~'
,
~~A
~OB
HDL~NC
,
--N(
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,-!-< CLR
Q1
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I
e'lB-1
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,
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TR
4 CLK!
OSC.
, t2 MHZ
GlI'l
+2TRQbNC
+lbMHZ
+"i00 KHZ WRiTE CLOCK 14}
4
,
~4
2~ ROO
22 ROW
(4)
+SELECT HEAD I III
j.iPD7f;f)
CONTlJUEO FROM SHEET 4
"'
'"
(1)- OA(K 2
1074LSOB
9
j==============~f5~====~==~==)!8~
74lS04
U"
(2)
+OMA GATE
I~ 7'il50B
~-------------~~~U'
14LSO'+
"
",OTE: U '+ t 7'+LS08J PINS 12 AND 13 ARE
CONNECTED ONLY ON CARDS
8UILT USING RAW CARD PIN'iOOIZ'n
5-1/4 Inch Diskette Drive Adapter (Sheet 3 of 4)
DACK
(2)
12j
W
co
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!"....
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...
13) +1 ...HZ CLOCK
,
. ,.
LS112
CK1/2
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f
....
"STANDARD DATA" GENI!RATOR
un
un
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PR
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INPUT SELECTOR
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pu
k
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2.15K C17
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R2 O.03IIJIF
LOOP FILTI!R
---
5-1/4 Inch Diskette Drive Adapter (Sheet 4 of 4)
'"
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7
~ r;;;:;-;; r!-
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• B
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GO '
r~
+ •
+
(PULLUPI
•
oct-!+DATA WINDOW (3)
-- ---
---- --- ------,-
mM Fixed Disk
Adapter
6361503
Personal Computer
Hardware Reference
Library
ii
Contents
Description .................................... 1
Fixed Disk Controller ........................ 1
Programming Considerations ...................... 3
Status Register ............................. 3
Sense Bytes ................................ 4
Data Register .............................. 7
Control Byte ............................... 8
Command Summary ........................ 10
Programming Summary ...................... 14
Interface ..................................... 15
Specifications ................................. 17
Logic Diagrams ................................ 19
BIOS Listing .................................. 25
iii
it>
Description
The Fixed Disk Adapter attaches to one or two fixed disk drive
units through an internal, daisy-chained, flat cable (datal control
cable). Each system supports a maximum of one Fixed Disk
Adapter and two fixed disk drives.
The adapter is buffered on the I/O bus and uses the system
board's direct memory access (DMA) for record data transfers.
An interrupt level also is used to indicate operation completion
and status conditions that require microprocessor attention.
The Fixed Disk Adapter provides automatic II-bit burst error
detection and correction in the form of 32-bit error checking and
correction (ECC).
The device level control for the Fixed Disk Adapter is contained
on a ROM module on the adapter. A listing of this device level
control can be found in "BIOS Listing" of this section.
Warning: The last cylinder on the fixed disk drive is reserved
for diagnostic use. The diagnostic write test will destroy any
data on this cylinder.
Fixed Disk Controller
The disk controller has two registers that may be accessed by the
system unit's microprocessor: a status register and a data register.
The 8-bit status register contains the status information of the
disk controller, and can be accessed at any time. The 8-bit data
register (actually consisting of several registers in a stack with
only one register presented to the data bus) stores data,
commands, and parameters, and provides the disk controller's
status information. Data bytes are read from, or written to the
data register in order to program or obtain the results after a
particular command. The status register is a read-only register
that is used to help the transfer of data between the system unit's
microprocessor and the disk controller. The controller-select
pulse is generated by writing to port address hex 322.
Fixed Disk Adapter 1
Serializer /
Deserializer
J2
SERDES
ECC
Data
Separator
Edge
Connector
Data Bus
OB7-DBO
Control
Sector
Buffer
a-Bit
Processor
.Fixed Disk Adapter Block Diagram
To
} Drives
Programming Considerations
Status Register
At the end of all commands from the system board, the disk
controller sends a completion status byte to the system board.
This byte informs the system unit's microprocessor if an error
occurred during the execution of the command. The following
shows the format of this byte.
6
5
4
3
2
o
d
o
o
o
e
~I
Bits 0, 1, 2, 3, 4, 6, 7
These bits are set to zero.
Bit 1
When set, this bit shows an error has
occurred during command execution.
Bit 5
This bit shows the logical unit number
of the drive.
If the interrupts are enabled, the controller sends an interrupt
when it is ready to transfer the status byte. Busy from the disk
controller is unasserted when the byte is transferred to complete
the command.
Fixed Disk Adapter 3
Sense Bytes
If the status register receives an error (bit 1 set), the disk
controller requests four bytes of sense data. The format for the
four bytes is as follows:
Bits
7
6
Byte 0
Address
Valid
I o I
Byte 1
0
0
Byte 2
Cylinder High
Byte 3
5
4
2
3
Error Type
1
0
Error Code
I
d
I
I
Head Number
Sector Number
Cylinder Low
Remarks
d = drive
Byte 0
Bits 0, 1, 2, 3
Error code.
Byte 0
Bits 4,5
Error type.
Byte 0
Bit 6
Set to 0 (spare)
Byte 0
Bit 7
The address-valid bit. Set only when
the previous command required a
disk address, in which case it is
returned as a 1; otherwise, it is O.
4 Fixed Disk Adapter
Disk Controller Error Tables
The following disk controller error tables list the error types and
error codes found in byte 0:
Error Type
Bits
Error Code
5 4
3
2
1
0
0
0
0
0
0
0
The controller did not detect any error
during the execution of the previous
operation.
0
0
0
0
0
1
The controller did not detect an index signal
from the drive.
0
0
0
0
1
0
The controller did not get a seek-complete
signal from the drive after a seek operation
(for all non-buffered step seeks).
0
0
0
0
1
1
The controller detected a write fault from
the drive during the last operation.
0
0
0
1
0
0
After the controller selected the drive, the
drive did not respond with a ready signal.
0
0
0
1
0
1
Not used.
0
0
0
1
1
0
After stepping the maximum number of
cylinders, the controller did not receive the
track 00 signal from the drive.
0
0
0
1
1
1
Not used.
0
0
1
0
0
0
The drive is still seeking. This status is
reported by the Test Drive Ready command
for an overlap seek condition when the
drive has not completed the seek. No
time-out is measured by the controller for
the seek to complete.
Description
Fixed Disk Adapter 5
Error Type
Bits
Error Code
5 4
3
2
1
0
0
1
0
0
0
0
ID Read Error: The controller detected an
ECC error in the target ID field on the disk.
0
1
0
0
0
1
Data Error: The controller detected an
uncorrectable ECC error in the target sector
during a read operation.
0
1
0
0
1
0
Address Mark: The controller did not detect
the target address mark (AM) on the disk.
0
1
0
0
1
1
Not used.
0
1
0
1
0
0
Sector Not Found: The controller found the
correct cylinder and head, but not the
target sector.
0
1
0
1
0
1
Seek Error: The cylinder or head address
(either or both) did not compare with the
expected target address as a result of a
seek.
0
1
0
1
1
0
Not used.
0
1
0
1
1
1
Not used.
0
1
1
0
0
0
Correctable Data Error: The controller
detected a correctable ECC error in the
target field.
0
1
1
0
0
1
Bad Track: The controller detected a bad
track flag during the last operation. No
retries are attempted on this error.
Error Type
Bits
Description
Error Code
5 4
3
2
1
0
1 0
0
0
0
0
Invalid Command: The controller has
received an invalid command from the
system unit.
1 0
0
0
0
1
Illegal Disk Address. The controller
detected an address that is beyond the
maximum range.
6 Fixed Disk Adapter
Description
Error Type
Bits
Error Code
5 4
3
2
1
0
1
1
0
0
0
0
RAM Error: The controller detected a data
error during the RAM sector-buffer
diagnostic test.
1
1
0
0
0
1
Program Memory Checksum Error: During
this internal diagnostic test, the controller
detected a program-memory cheCksum
error.
1
1
0
0
1
0
ECC Polynominal Error: During the
controller's internal diagnostic tests, the
Description
hardware ECC generator failed its test.
Data Register
The system unit's microprocessor specifies the operation by
sending the 6-byte device control block (DCB) to the controller.
The figure below shows the coniposition of the DCB, and defines
the bytes that make up the DCB.
Bit
7
Byte 0
Byte 1
Byte 2
6
5
4
Command
Class
0
0
Cylinder High
1
0
Opcode
d
I
2
3
Head Number
Sector Number
Byte 3
Cylinder Low
Byte 4
Interleave or Block Count
Byte 5
Control Field
Byte 0
Bits 7, 6, and 5 identify the class of the command.
Bits 4 through 0 contain the Opcode command.
Byte 1
Bit 5 identifies the drive number. Bits 4 through 0
contain the disk head number to be selected. Bits
6 and 7 are not used.
Fixed Disk Adapter 7
Byte 2
Bits 6 and 7 contain the two most significant bits
of the cylinder number. Bits 0 through 5 contain
the sector number.
Byte 3
Bits 0 through 7 are the eight least-significant bits
of the cylinder number.
Byte 4
Bits 0 through 7 specify the interleave or block
count.
Byte 5
Bits 0 through 7 contain the control field.
Control Byte
Byte 5 is the control field of the DeB and allows the user to
select options for several types of disk drives. The format of this
byte is as follows:
I I
Bits
7
6
5
4
3
2
r
a
0
0
0
s
s
~I
Remarks
r = retries
s = step option
a = retry option on data ECC
error
Bit 7
Disables the four retries by the controller on all
disk-access commands. Set this bit only during the
evaluation of the performance of a disk drive.
Bit 6
If set to 0 during read commands, a reread is
attempted when an Eee error occurs. If no error
occurs during reread, the command will finish
without an error status. If this bit is set to 1, no
reread is attempted.
Bits 5, 4, 3
Set to O.
8 Fixed Disk Adapter
Bits 2, 1, 0
These bits define the type of drive and select the
step option. See the following figure.
Bits 2. 1. 0
0
0
0
This drive is [lot specified and defaults to 3 milliseconqs per
steP
0
0
1
0
1 0
0
1
1
N/A
N/A
N/A
1 0
0
200 microseconds per step.
1 0
1
70 microseconds per step (specified by BIOS).
1
1 0
3 milliseconds per step.
1
1
1
3 milliseconds per step.
Fixed Dislt Adapter 9
Command Summary
Command
Data Control Block
Remarks
Test Drive
Bit
7
6
5 4 3 2 1 0
Ready
Byte 0
0
0
010
0
0
0
0
(Class 0,
Byte 1
0
0
d
Ix
x
x
x
x
Opcode 00)
= drive (0 or 1)
= don't care
Bytes 2, 3, 4, 5 = don't
d
x
care
= drive (0 or 1 )
= don't care
r = retries
s = Step Option
Bytes 2, 3, 4 = don't
4
3
2 1 0
d
01 0
0
0
0
1
x
Ix
x
x
x
x
0
0
s
s
s
Recalibrate
Bit
7 6
(Class 0,
Byte 0
0
0
Opcode 01)
Byte 1
0
0
d
Byte 5
r
0
0
5
care
ch
= cylinder high
Reserved
This Opcode is not
(Class 0,
used.
Opcode 02)
= drive (0 or 1 )
= don't care
Bytes 2, 3, 4, 5 = don't
Request Sense
Bit
7 6
5
4
3
2
1 0
d
Status
Byte 0
0
0
01 0
0
0
1
1
x
(Class 0,
Byte 1
0
0
d
x
x
x
x
Ix
Opcode 03)
care
Format Drive
Bit
7 6
5
(Class 0,
Byte 0
0
01 0 0
Opcode 04)
Byte 1
0
Byte 2
0
0
d
4
2
1 0
1 0
0
I Head Number
10 0
ch
3
0
0
0
0
= drive (0 or 1 )
= retries
s = step option
ch = cylinder high
d
r
Cylinder Low
Byte 3
Byte 4
0
0
Byte 5
r
0
Ready Verify
Bit
7 6
(Class 0,
Byte 0
0
Opcode 05)
Byte 1
0
Byte 2
0
Interleave
01
0 0 0 s s s
for 51 2-byte sectors.
5 4
1 0
d
01 0 0 1 0 1
d Head Number
r
2
I
0
I
ch
3
Sector Number
Interleave 1 to 16
= drive (0 or 1 )
= retries
s = step option
a = retry option on
Byte 3
Cylinder Low
data ECC
Byte 4
Block Count
ch
Byte 5
10 Fixed Disk Adapter
r
a
0
0
0
s
s
s
= cylinder high
Data Control Block
Command
Remarks
Format Track
Bit
7
6
5
4
3
2
1 0
(Class 0,
Byte 0
0
0
010
0
1
1 0
Opcode 06)
Byte 1
0
0
d
Byte 2
10
ch
I Head Number
0
0
0
0
0
r = retries
s = step option
ch = cylinder high
Cylinder Low
Byte 3
Byte 4
0
Byte 5
r
0
0
Interleave
01
0 0 0 s s s
for 512-byte sectors.
d = drive (0 or 1 )
Format Bad
Bit
7
6
5
4
3
2
1 0
Track
Byte 0
0
0
010
0
1
1
(Class 0,
Byte 1
0
0
d
Opcode 07)
Byte 2
1
I Head Number
10 0
ch
Byte 3
0
0
0
0
Interleave 1 to 16
r = retries
s = step option
ch = cylinder high
Cylinder Low
Byte 4
0
0
Byte 5
r
0
Interleave
01
0 0 0 s s s
for 512-byte sectors.
d = drive (0 or 1 )
Read
Bit
7
6
5
(Class 0,
Byte 0
0
0
0[0
Opcode 08)
Byte 1
0
0
d
Byte 2
I
ch
4
3
2
1 0
1 0
0
0
I Head Number
Sector Number
r
0
a
0
0
s
Interleave 1 to 16
r = retries
a = retry option on
data ECC error
Cylinder Low
Byte 3
Byte 5
d = drive (0 or 1 )
s "" step option
s
s
ch = cylinder high
Reserved
This Opcode is not
(Class 0,
used.
Opcode 09)
Write
Bit
7
6
5
(Class 0,
Byte 0
0
0
010
Opcode OA)
Byte 1
0
0
d
Byte 2
ch
3
2
1 0
1
0
1 0
I Head Number
Sector Number
d = drive (0 or 1 )
r = retries
s = step option
ch = cylinder high
Cylinder Low
Byte 3
Byte 4
Byte 5
I
4
Block Count
r
0
0
0
0
s
s
5
4
3
2
1 0
d = drive (0 or 1)
1
r = retries
Seek
Bit
7
6
(Class 0,
Byte 0
0
0
010
Opcode OB)
Byte 1
0
0
d
Byte 2
Byte 3
1
I Head Number
10 0
ch
1 0
s
0
0
0
0
Cylinder Low
s '" step option
x = don't care
ch = cylinder high
Byte 4
x
x
x
x
x
x
x
x
Byte 5
r
0
0
0
0
s
s
s
Fixed Disk Adapter 11
Data Control Block
Command
Remarks
Initialize
I Bit
17
5 4
3
2
Drive
I Byte 0
10 0
010
1
1 0
Read ECC Burst
I Bit
17
6
5 4
3
2
Error Length
I Byte 0
10
0
01 0
1
1 0
17 6
IByteO 10 0
5 4
3
2
OlO
1
1
I Bit
17 6 5 4
IByte 0 10 0 010
3
2
1 01
1
1
1
6
1 01
01
Bytes 1, 2, 3, 4, 5, =
don't care
Characteristics *
(Class 0,
OpcodeOC)
1 01
Bytes 1, 2, 3, 4, 5, =
1I
don't care
1 01
1 01
don't care
(Class 0,
Opcode OD)
Read Data from
Sector Buffer
LBit
Bytes 1, 2, 3, 4, 5, =
(Class 0,
Opcode OE)
Write Data to
Sector Buffer
1
I
Bytes 1, 2, 3, 4,5, =
don't care
(Class 0,
Opcode OF)
RAM
I Bit
Diagnostic
IByte 0
17 6 5 4
1 1 [0
11
3
2
1 01
Bytes 1, 2, 3,4,5, =
0
0
0
don't care
01
(Class 7,
Opcode 00)
Reserved
This Opcode is not
(Class 7,
used.
Opcode 01)
Reserved
This Opcode is not
(Class 7,
used.
Opcode 02)
*Initialize Drive Characteristics: The DBC must be followed by eight additional bytes.
Maximum number of cylinders
(2 bytes)
Maximum number of heads
(1 byte)
Start reduced write current cylinder
(2 bytes)
Start write precompensation cylinder
(2 bytes)
Maximum ECC data burst length
(1 byte)
12 Fixed Disk Adapter
Remarks
Data Control Block
Command
Drive
Bit
7
6
5 4
3
2
1 0
d = drive (0 or 1 )
Diagnostic
Byte 0
1
1
1 10 0
0
1
1
s = step option
(Class 7,
Byte 1
0
0
dlx
x
x
x
x
r = retries
Opcode 03)
Byte 2
x
x
x
x
x
x
x
x
x = don't care
Byte 3
x
x
x
x
x
x
x
x
Byte 4
x
x
x
x
x
x
x
x
Byte 5
r
0
0
0
0
s
s
s
7
6
5 4
3
2
1 0
1
1
1 10 0
1 0
2
Controller
Internal
I Bit
I Byte 0
Bytes 1, 2, 3, 4,5, =
0
don't care
Diagnostics
(Class 7,
Opcode 04)
Read Long*
Bit
7
6
5 4
(Class 7,
Byte 0
1
1
1 10 0
Opcode 05)
Byte 1
0
0
Byte 2
d
J
ch
3
1 0
1 0
s = step option
I Head Number
r = retries
ch = cylinder high
Sector Number
Cylinder Low
Byte 3
Byte 4
Block Count
Byte 5
r
0
0
0
0
s
Write Long * *
Bit
7
6
5
4
3
2
1 0
(Class 7,
Byte 0
1
1
1 10 0
1
1 0
Opcode 06)
Byte 1
0
0
d
Byte 2
ch
Byte 3
I
s
s
d = drive (0 or 1 )
s = step option
I Head Number
r = retries
Sector Number
ch = cylinder high
Cylinder Low
Byte 4
Byte 5
d = drive (0 or 1 )
1
Block Count
r
0
0
0
0
s
s
s
*Returns 512 bytes plus 4 bytes of ECC data per sector.
* *Requires 512 bytes plus 4 bytes of ECC data per sector.
Fixed Disk Adapter 13
Programming Summary
The two least-significant bits of the address bus are sent to the
system board's I/O port decoder, which has two sections. One
section is enabled by the I/O read signal ( -lOR) and the other by
the I/O write signal (-lOW). The result is a total of four
read/write ports assigned to the disk controller board.
The address enable signal (AEN) is asserted by the system board
when DMA is controlling data transfer. When AEN is asserted,
the I/O port decoder is disabled.
The following figure is a table of the read/write ports.
R/W
Port Address
Read
Write
320
320
Read data (from controller to system unitl.
Write data (from system unit to controllerl.
Read
Write
321
321
Read controller hardware status.
Controller reset.
Read
Write
322
322
Reserved.
Generate controller-select pulse.
Read
Write
323
323
Not used.
Write pattern to DMA and interrupt mask
register.
14 Fixed Disk Adapter
Function
Interface
The following lines are used by the disk controller:
AO-AI9
Positive true 20-bit address. The least-significant 10
bits contain the I/O address within the range of hex
320 to hex 323 when an I/O read or write is
executed by the system unit. The full 20 bits are
decoded to address the read-only memory (ROM)
between the addresses of hex C8000 and C9FFF.
DO-D7
Positive 8-bit data bus over which data and status
information is passed between the system board and
the controller.
-lOR
Negative true signal that is asserted when the system
board reads status or data from the controller under
either programmed I/O or DMA control.
-lOW
Negative true signal that is asserted when the system
board sends a command or data to the controller
under either programmed I/O or DMA control.
AEN
Positive true signal that is asserted when the DMA in
the system board is generating the I/O Read (-lOR)
or I/O Write (-lOW) signals and has control of the
address and data buses.
RESET
Positive true signal that forces the disk controller to
its initial power-up condition.
IRQ 5
Positive true interrupt-request signal that is asserted
by the controller when enabled to interrupt the
system board on the return ending status byte from
the controller.
DRQ3
Positive true DMA-request signal that is asserted by
the controller when data is available for transfer to
or from the controller under DMA control. This
signal remains active until the system board's DMA
channel activates the DMA-acknowledge signal
(-DACK 3) in response.
Fixed Disk Adapter 15
-DACK 3
This signal is true when negative, and is generated by
the system board DMA channel in response to a
DMA request (DRQ 3).
16 Fixed Disk Adapter
Specifications
The Fixed Disk Adapter connector and interface specifications
follow.
Fixed Disk Adapter 17
Pin 34
fil~l~
,::,
~~
Pin
20rru!ZlJ!
-...'
::::::
"
Pin
';~
Pin 1
2~2~
..........
:::~~
Pin 1
,
,-
Pin 1
Signal
Position 5 has No Pin
(for Cable Orientation)
Pin Number
Ground-Odd Numbers
1-33
Reserved
4.16.30.32
- Reduced Write Current
2
- Write Gate
6
- Seek Complete
8
Disk
- Track 00
10
Disk
Drive
- Write Fault
12
Adapter
Connector
- Head"Select 2°
14
Connector
J1
- Head Select 2'
18
J1
-Index
20
- Ready
22
-Step
24
- Drive Select 1
26
- Drive Select 2
28
- Direction In
34
Signal
Ground
Pin Number
2.4.6.8.12.16.20
Drive Select
1
Reserved
Spare
3,7
9.10.5 (No Pin)
Disk
Ground
11
Disk
Drive
MFM Wire Data
13
Adapter
Connector
- MTM Write Data
14
Connector
J2orJ3
Ground
15
J2 or J3
MFM Read Data
17
- MFM Read Data
18
Ground
19
Fixed Disk Adapter Interface Specifications
18 Fixed Disk Adapter
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11,12,15.16.19.20
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Fixed Disk Adapter (Sheet 4 of 6)
2.6
5.6
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33"
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Fixed Disk Adapter (Sheet 5 of 6)
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+12VOLTS
NOTES:
UNLESS OTHERWISE SPECIFIED:
1. All RESISTOIIS 1/4 W,5'\'1, CARBON FILTER.
2. ALL CAPS +10V DR BREATER+ID%.
3. NO MORE THAN 15 lOADS PER PULLUP NET.
Fixed Disk Adapter (Sheet 6 of 6)
TP10
BIOS Listing
The BIOS Listing for the IBM Fixed Disk Adapter follows.
Fixed Disk Adapter 25
LaC OBJ
SOURCE
LINE
$TITLE( FIXED DISK BIOS FOR IBM DISK CONTROLLER)
j
w_
IHT 13 -------------------- _________________________________ _
; FIXED DISK lID INTERFACE
THIS INTERFACE PROVIDES ACCESS TO 5 1/4" FIXED 0151(5
THROUGH THE IBM FIXED DISK CONTROLLER.
10
j -- - - -- ---------------------- - --- - - - - - - --- - - - - -- - -------- - -------
11
12
; - - - - - - - - - - - - ------ -- - --- - ----- -- - - - - ----- - --------- ----- --------
13
THE
14
SOFTWARE INTERRUPTS ONLY.
BIOS ROUTINES ARE MEANT TO BE ACCESSED THROUGH
15
THE LISTINGS
16
NOT FOR
17
ABSOLUTE
18
19
2.
21
22
ARE INCLUDED
REFERENCE.
ANY ADDRESSES PRESENT IN
ONLY FOR
COMPLETENESS.
APPLICATIONS WHICH
ADDRESSES
WITHIN
VIOLATE THE STRUCTURE AND
DESI~N
THE
CODE
REFERENCE
SEGMENT
OF BIOS.
; ------------------------~--------.-----------------------------i
INPUT
(AH
= HEX
VALUE)
IAH)=OO RESET DISK ~Dl. = 80H,61H) I PISKETTE
(AH 1=01 READ THE STAnJS OF THE LAST DISK OPERATION INTO tAli
NOTE: Dl < SOH - DISKETTE
Dl > 80H - DISK
IAHI=02 READ THE DESIREQ SECTORS INTO MEMORY
IAHI=03 WRITE THE DESIRED SECTORS FROM MEMORY
IAHI=04 VERIFY THE DESIRED SECTORS
IAHI=05 FPRMAT THE DESIRED TRACK
IAH)=06 FORMAT THE DESIRED TRACK AND SET BAD SECTOR FLAGS
(AH )=07 FORMAT THE DRIVE STARTING AT THE DESIRED TRACK
IAH )=OS RETURN THE CURRENT DRIVE PARAMETERS
23
2.
25
26
27
28
29
3D
31
32
33
34
35
I AH )=09 INITIAlIZE DRIVE PAIR CHARACTERISTICS
INTERRUPT 41 POINTS TO DATA BLOCK
I AH I=OA READ LONG
IAHI=OB WRITE LmlG
NOTE: READ AND WRITE LONG ENCOMPASS 512 + it BYTES ECC
(AH I=OC SEEK
IAHI=OD Al.TERNATE DISK RESET (SEE Dli
(AH I=O~ READ SECTOR BUFFER
IAHI=OF ~ITE SECTOR BUFFER,
IRECDt1f1ENDED PRACTICE BEFORE FORMATTING)
IAH)=10 TEST DRIVE READY
tAHI=l1 RECALIBRATE
(AHI=12 CONTROLLER RAM DIAGNOSTIC
(AHI=13 DRIVE I;)IAGNOSTIC
IAHI=14 CONTROLl~R INTERNAL DIAGNOSTIC
36
37
38
3.
4.
41
4'
43
44
45
46
47
48
4.
5.
51
REGISTERS USED FOR FIXED DISK OPERATIONS
52
(DLI
IDHI
(CH)
(CLI
53
54
55
56
-
57
58
5'
6.
(All
61
62
-
63
IES:BX) -
64
65
DRIVE NUt1BER
H~AD HUt1BER
CYlINDER HUt1BER
SECTOR NUMBER
ISOH-S7H FOR DISK, VALUE CHECKED)
[P-7 ALLOWED, NOT VALUE CHECKED)
(0-1023. NOT VALUE CHECKEDHSEE CU
11-17. NOT VALUE CHECKED)
NOTE: HIGH 2 BITS OF ~YlINDER HUt1BER ARE PLACED
IN THE HIGH 2 BITS OF THE CL REGISTER
(10 BITS TOTAL)
NUI1BER OF SECTORS (MAXItM'1 POSSIBLE RANGE 1-80H.
FOR READIWRITE LONG 1-79H,
(INTERLEAVE VALUE FOR FORMAT 1-160)
ADDRESS OF BUFFER FOR READS AND WRITES.
(NOT REQUIRED FOR VERIFY)
66
67
; OUTPUT
6!S
69
70
71
AH = STATUS OF CURRENT OPERATION
STATUS BITS ARE DEFINED IN THE EQUATES BElCH
CY = 0 SUCCESSFUL OPERATION (AH:O ON RETURN)
CY : 1 FAIlED OPERATION (AH HAS ERROR REASON)
72
73
74
75
76
17
26 Fixed Disk Adapter
NOTE:
ERROR I1H INDICATES THAT THE DATA READ HAD A RECOVERABLE
ERROR WHICH WAS CORRECTED BY THE ECC ALGORITHM. THE DATA
IS PROBABLY GOOD.
HOWEVER THE BIOS ROUTINE INDICATES AN
ERROR TO ALLOW THE CONTROL LIft(; PROGRAM A CHANCE TO DECIDE
Fnp ITSELF. THE ERROR HAY HOT RECUR IF THE OA.TA IS
LOC OBJ
LINE
SOURCE
70
REWRITTEN. (AU CONTAINS THE BURST LENGTH.
7'
00
IF DRIVE PARAMETERS WERE REQUESTED.
01
OZ
01
DL ; NUMBER OF CONSECUTIVE ACKNOWLEDGING DRIVES ATTACHED (0-21
(CONTROllER CARD ZERO TALLY ONLY)
84
DH :: MAXIMUM USEABLE VALUE FOR HEAD NUMBER
85
CH
= MAXIMUM
Bb
CL
=
USEABLE VALUE FOR CYLINDER HUMBER
MAXIMUM USEABLE VALUE FOR SECTOR NUMBER
87
AND CYLINDER NUMBER HIGH BITS
80
0'
REGISTERS WILL BE PRESERVED EXCEPT WHEN THEY ARE USED TO RETURH
90
INFORMATION.
91
92
NOTE: IF AN ERROR IS REPORTED BY THE DISK CODE. THE APPROPRIATE
AcnON IS TO RESET THE DISK. THEN RETRY THE OPERATION.
93
'495
; ----------------- -------------------------------------------------------
'6
OOFF
OOBe
0080
,.
'7
EDU
OFFH
I SENSE OPERATIOH FAILED
UNDEF _ERR
EDU
OBBH
I UNDEfINED ERROR OCCURRED
EDU
80H
SENSEJAIL
0040
"
TIME_OUT
100
BAD_SEEK
EQU
40H
; SEEK OPERATIOH FAILED
0020
101
BAD_CNTLR
EDU
ZOH
I CONTROLLER HAS FAILED
0011
lOZ
DATA_CORRECTED
EDU
11H
; ECC CORRECTED DATA ERROR
0010
0004
101
104
105
106
107
108
0002
109
0001
110
oooe
0009
0007
0005
; ATTACHMENT FAILED TO RESPOND
BAD_ECC
EDU
lOH
; BAD ECC ON DISK READ
BAD_TRACK
EDU
08H
; BAD TRACK FLAG DETECTED
DMA_BOlrnOARY
EQU
09H
; ATTEMPT TO DHA ACROSS 64K BOUNDARY
INITJAIL
EDU
07H
; DRIVE P....RAMETER ACTIVITY FAILED
BAD_RESET
EDU
05H
; RESET FAILED
RECORD_NOTJNO
04H
BAD_ADDR_MARK
EDU
EQU
OZH
I ADDRESS MARK NOT FOUND
BAD_CMD
EQU
OlH
I BAD COMMAND PASSED TO DISK I/O
; REQUESTED SECTOR NOT FOl.n'ro
111
112
; ----------------------------------------
113
INTERRUPT AND STATUS AREAS
114
; -------------- --------------------------
115
116
SEGMENT AT 0
DU!1I1Y
0034
117
0034
004C
004C
118
11'
1ZO
0064
1Zl
0064
lZZ
lZl
lZ4
lZ5
126
DISK_VECTOR
lZ7
ORG
0078
0078
0100
0100
0104
0104
lZO
7C00
129
7eOD
130
III
ORG
HOISK_INT
DRG
DRG_VECTOR
ORG
BOOT_VEC
LABEL
ORG
DRG
HF _TBL_VEC
ORG
BOOT_lOCN
DWOOD
I DISK INTERRUPT VECTOR
13H*4
LABEL
DWORD
I BOOTSTRAP INTERRUPT VECTOR
19H*4
LABEL
DISKETTE_PARM
; FIXED D 15K INTERRUPT VECTOR
ODH*4
DWORD
I DISKETTE PARAMETERS
lEH*4
LABEL
DWORD
040H*4
LABEL
I NEW DISKETTE INTERRUPT VECTOR
DWORD
; FIXED DISK PARAMETER VECTOR
041H*4
LABEL
DWORD
; BOOTSTRAP LOADER VECTOR
7COOH
LABEL
FAR
DUMI1Y
ENDS
DATA
SEGMENT AT 40H
006t n??
0072
III
!l4
!l5
136
!l7
138
139
0072 7111
140
RESETJLAG
0074
141
DRG
0074 11
14Z
DISK_STATUS
08
; FIXED DISK STATUS BYTE
0075 11
141
HF _HUM
08
; COUNT OF FIXED OISK DRIVES
0076 ??
144
CONTROL_BYTE
DB
; COUTROL BYTE DRIVE OPTIONS
0077 ??
145
PORT_OFF
08
; PORT OFFSET
146
DATA
ENOS
COOE
SEGMENT
m
0042
0042
0042 (7 1?)
DQbt
DRG
4ZH
CMD_BLOCK
LABEL
BYTE
HO_ERROR
08
7 DUP(?l
ORG
TIMER_lOW
ORG
; OVERLAYS DISKETTE STATUS
ObCH
OW
; TIMER LOW WORD
7ZH
OW
• lZ34H IF KEYBOARD RESET UNDERWAY
74H
147
148
14'
150
1--------------------------------------------------------
lSI
; HARDWARE SPECIFIC VALUES
'"
153
154
-
CONTROLLER I/O PORT
> WHEI'i READ FIWM,
Fixed Disk Adapter 27
LaC OSJ
LINE
SOURCE
155
HF _F'ORT+O - READ DATA (fROM CONTROLLER TO CPU)
156
HF _PORT+l ... READ CONTROLLER HARDWARE STATUS
151
(CONTROLLER TO CPU)
158
HF _PORT+2 ... READ CONFIGImATlON SWITCHES
159
HF_PORT+! - NOT USED
160
> WHEN WRITTEN TO:
161
HF_PORT+O - WRITE DATA (fROM CPU TO CONTROLLER) :
162
HF __ PORHI - CONTROLLER RESET
163
HF _PORT+2 - GENERATE CONTROLLER SELECT PUlsE
164
HF_PORT+3 - WRIl'E PATTERN TO OHA AND INTERRUPT
165
0320
OQ08
0004
0002
0001
166
167
168
16.
17.
171
172
173
MASK REGISTER
i ... -- ------- - - --- --------------- -- ------- ... --- -------------
HF _PORT
EQU
EQU
EQU
0320H
Rl_BUS
Rl_IOMOOE
EQU
000000108
Rl_REQ
EQU
000000018
DHA_READ
EQU
EQU
010001118
Rl_BUSY
I DISK PORT
000010008
J DISK PORT 1 BUSY BIT
00000100B
1
COMMAND/DATA BIT
MODE BIT
REQUEST BIT
170
0047
004B
0000
0082
DOGD
0001
0003
OOOct
ODDS
0006
0007
0008
OOOA.
DOOB
Dooe
DODD
DOOE
DOOF
oDeD
00E3
OOE4
00E5
00E6
0020
0020
000&
0002
17.
176
177
178
17.
180
181
18.
183
18_
18S
186
187
188
18.
1'0
1.1
1"
1.3
1'_
1.5
1.6
1.7
1.8
1••
.OO
DM.\.WRlTE
DHA
EQU
EQU
I PORT FOR HIGH ,. BITS OF OMA
000000008
I CNTLR READY (DOH)
RECAL_Cf'I)
EQU
EQU
000000018
RECAL 101HI
SENSE_CI'I)
EQU
000000118
SENSE 103H)
FMTDRV_CMD
EQU
00000100B
DRIVE 104H)
CH~TRK_Ct1D
EQU
EQU
00000101B
000001108
TRACK (06H)
000001118
BAD
(07H)
READ_CMD
EQU
EQU
000010008
READ
(08H)
WRITE_CtID
EQU
000010108
WRITE (OAH)
SEEK_CMD
EQU
EQU
000010118
SEEK
(OBH)
INIT_DRV_CtIJ
000011008
INIT
(OCH)
RD_ECC_CI1D
EQU
000011018
BURST (DOH)
RD_BUFF _CMD
EQU
EQU
00001110B
BUFFR 10EH)
EOU
EOU
EQU
111000008
RAM
(EOH)
111000118
DRV
(ElH)
11100100B
CNTLR (E4H)
EQU
EQU
111001018
RlONG (E5H)
WlONG (E6H)
TST_RDY_Cf'I)
FMTTRK_CMD
FMTBAD_CMD
WR_BUFF _CtIJ
RAM_DlAG_CND
CHK_DRV_CtI)
CNTLR_DIAG_CHD
HO_LONG_Cm
WR_LONG_CMD
INT_CTL_PORT
.01
.0.
Eot
."
.0_
...
HAX]IlE
S_HAX_FIlE
EOU
EQU
ASS\Jt1E
CS:COOE
207
0000 55
.0.
o.G
DB
055H
'08
DB
DB
."
."
00001111B
11100110B
T CHK (OSH)
BUFFR (OFH)
20"
I 8259 CONTROL PORT
'0"
I END OF INTERRUPT CONtlAHD
EQU
EQU
'06
0002 10
I CHANNEL 3 (048H)
I DHA ADDRESS
082H
DHA_HIGH
0000
0001 AA
010010118
0
J CHANNEL 3 (047H)
0"
I GENERIC BIOS HEADER
OUH
16D
212
1-----"" -.. -.. ---------------------------------------- ... ----------... -
213
1 FIXED DISK lID SETUP
21_
215
-
ESTABLISH TRANSFER VECTORS FOR THE FIXED DISK
216
-
PERFORM POWER ON DIAGNOSTICS
217
218
0003
0003 EBIE
0005 35303030303539
20284329434FSO
5952494748542.0
20494240203139
3632
0023
0023 tBCO
002:5 8E08
SHOULD AN ERROR OCCUR" "1701" MESSAGE IS DISPUYED
219
1_ -- ------- -- --------------- w
•• 0
.21
DISK_SETUP
...
•••
..-
_w _______ . ____________
PROC
FAR
JHP
SHORT
L3
DB
'5000059 (C)COPYRIGHT
IBM 19B2'
w - - -----------
I COPYRIGHT NOTICE
l3:
••S
ASSU1E
"6
SUB
,.7
28 Fixed Disk Adapter
MO.
DS:Dl.It1MY
AX,AX
DS,AX
I ZERO
LaC OBJ
LINE
SOURCE
0028 A14COO
22.
22.
MOV
AX,WORD PTR ORG_IIECTOR
; GET DISKETTE IIECTOR
0026 A3COOl
230
MOV
WORD PTR DISK_VECTOR,AX
I
002£ Al4EOO
231
MOV
AX,WORD PTR ORG_IIECTOR+2
0031 A30201
232
233
,,.
HOV
HOV
WORD PTR DISK_IIECTOR+2.AX
0034 C7064C005602
HOV
WORO PTR ORG_YECTOR+2:,CS
0027 FA
C03A 8COE4EOO
003E 886007
0041 A3340Q
0044 6COE3600
0048 C70664008601
004E 8CO£6600
0052 C7060401£703
0058 8eOE0601
Dose FB
eLI
235
23.
237
23.
23.
240
241
242
243
244
HOV
HOV
MaY
MaY
HOV
MaY
HOV
STI
ASSUME
WORD PTR ORG_ VECTOR, OFFSET DIsK_IO
AX. OFFSET HD_INT
WORD PTR BOOT_IIEe.OFFSET BOOT_STRAP
WORD PTR HF _TBl_IIEC.OFFSET Fa_TBl
05:0ATA
MOV
AX.OATA
HOV
05,AX
0062 C606740000
0067 C606750000
246
D06e C606430000
24.
250
251
0076 892500
oo?e
7305
252
253
254
0083 890100
0086 BA8000
255
25.
257
256
25.
2.0
0089 B60D12
007E E2F9
0080 E9BFDO
I ESTABLISH SEGMENT
OISK_STATU5.0
I RESET TliE STATUS INDICATOR
HF _HUH,O
I ZERO COUNT OF DRIVES
CMD_BlOCK+l,O
PORT_OFF.
HOV
CX.25H
JHe
L7
LOOP
L4
a
I DRIVE ZERO. SET VALUE IN BLOCK
; ZERO CARD OFFSET
; RETRY COUNT
L4:
; RESET CONTROLLER
JHP
ERROR_EX
HOV
MOV
CXol
2.2
HOV
AX,1200H
DOet CD 13
2.3
INT
13H
006E 7303
2.4
0090 E9AFOQ
265
0093
0093 880014
0096 con
2 ••
266
INT
13H
0098 7303
2 ••
JNe
P.
JMP
ERROR_EX
TIMER_LOW. a
0083
I PARAMETER TBL
WORD PTR HF _TBl_VEC+2 .CS
24.
247
0079 EBF200
I BOOTSTRAP
WORD PTR BOOT_IIEC+2.CS
,.5
0079
I HDISK INTERRUPT
WORD PTR HDIsK_INT, AX
0050 884000
0071 C606770000
I HDISK HANDLER
WORD PTR HDISK_lHT+2:.CS
0060 8ED8
HOV
HOV
HOV
HOV
INTO INT 40H
; TRY RESET AGAIN
L7:
2.,
OX.80H
JNe
P7
JHP
ERROR_EX
HOY
AX,1400H
I CONTROllER DIAGNOSTICS
P7:
2.7
I CONTROllER DIAGNOSTICS
009,A. E9.6.500
270
0090
0090 C7066COOOOOO
271
aDA] .6.17200
273
HOV
MOV
00A6 3D3412
274
eHP
OOA9 7506
275
JNE
P6
OOA8 C7066C009AOI
27.
MOV
TIMER_LOW.410D
I SKIP WAIT ON RESET
DaB 1
277
OOBI £421
276
27.
IN
AL.021H
; TIMER
0083 24FE
0065 E621
DOB7
P9:
272
260
261
AX.l234H
AND
AL,OFEH
j
OUT
021H ,AL
; START TIMER
J RESET CONTROLLER
262
263
264
Je
P10
MOV
AX,lOOOH
26'
26.
INT
JNe
13H
P2
MOY
AX, TlMER_ LOW
DOBF COl3
OOCI 7308
OOC]
00C3 A16eoo
aOC6 308EOI
00C9 72£t
'67
266
289
,.0
eMP
AX,4460
JB
P4
JMP
ERROR_EX
MOV
MOV
CX.l
29.
297
2.6
299
MOV
AX.llOOH
INT
13H
Je
ERROR_EX
0008 880009
300
MOV
AX,0900H
OODe COil
3"
3"
ODD 1 BA800Q
0004 880011
0007
con
0009 7267
OOEO 7260
OOH B800C8
291
,92
303
304
I READY
Pia:
2.3
294
29.
00C8 EB7S90
DaCE
DaCE MOIDa
ENABLE TIMER
P4l
oaBA 7207
8BOOI0
I KEYBOARD RESET
P8l
00B7 E88400
ooee
ZERO TIMER
j
AX.RESETJLAG
; 25 SECONDS
P2:
OX.80H
INT
13H
Je
ERROR_EX
HOV
AX,OC800H
; RECALlBRATE
; SET DRIVE PARAMETERS
I OMA TO BUFFER
Fixed Disk Adapter 29
LOC OBJ
ODES SEeD
00E7 2808
OOE9 a8000F
OOEt
con
DOEE 7252
OOFO FE067500
LINE
SOURCE
305
300
307
308
MOV
ES,AX
30.
310
3JJ
sue
BX.BX
MOV
AX,OFOOH
INT
J3H
JC
ERROR_EX
IHC
HF _tM1
OX,213H
; SET SEGMENT
J WRITE SECTOR 8UFFER
J DRIVE ZERO RESPONDED
31'
00F4 8.4.1302
313
MOV
OOF7 BODO
314
315
310
317
318
MOV
AL,O
OUT
OX,AL
i TURN BOX OFF
MOV
OX,321H
; TEST IF CONTROLLER
IH
AL,OX
J ••• IS IN THE SYSTEM
AND
AL.OFH
CMP
AL.OFH
JE
MOV
BOX_ON
TIMER_LOW.42:00
; CONTROLLER IS IN SYSTEM
OIDA.
31'
320
321
322
010A. 8.4.1302
323
MOV
OX,213H
I EXPANSION BOX
0100 BOFF
MOV
AL,OFFH
OUT
OX,At
• TURN BOX ON
0110 890100
324
325
320
327
MOV
eX,l
j
ATTEMPT NEXT DRIVES
MOV
Dx.oalH
sue
,NT
AX,AX
j
RESET
POD_DONE
AX,OllOOH
00F9 EE
OOFA. BA2103
OOFO EC
OOFE 240F
0100 3eOF
Cla2 7406
0104 C7066COOA40 1
010F EE
0113 BA8100
"8
0116
32.
J EXPANSION BOX
0116 ZBce
330
331
011A 7240
33'
JC
OIlC 880011
OllF COIl
333
334
MOV
IHT
J3H
0121 7308
JHC
P5
MOV
AX, TIMER_LOW
0126 30BEOI
335
330
337
CMP
AX.446D
0129 nEB
338
JB
P3
0128 E82F90
33'
340
341
JMP
POD_DONE
MOV
INT
AX,0900H
012E
012E 880009
0131 con
0133 7227
0135 FE067500
0139 81F.4.8100
0130 7310
013F 42
0140 EBD4
13H
J RECAL
I 25 SECONDS
P5:
J INITIALIZE CHARACTERISTICS
13H
34'
343
344
345
340
JAE
POD_DONE
347
.48
34.
IHC
JMP
OX
P3
350
!..tIIT
P3:
Olle COll
0123 A.16eOO
l~IT
JC
POD_DONE
lHe
HF _NUt1
CMP
OX, (SOH + 5_MAX]ILE -
1 TALLY ANOTltER DRIYE
1)
; ----- POD ERROR
351
0142
35'
0142 BOOFOO
sua
AX,AX
0147 85FO
353
354
355
MOV
SI.AX
0149 89060090
350
MOV
CX.FI7L
; MESSAGE CHARACTER COUNT
0140 8700
357
MOV
BH,O
I PAGE ZERO
014F
358
014F 2E8A.846Btn
35.
HOV
AL,CS:F17[SIJ
I GET BYTE
0154 840E
300
HOV
AH.14D
; VIDEO OUT
0156 COlO
301
INT
lOH
I DISPLAY CHARACTER
015846
30'
303
INC
51
; NEXT CHAR
LOOP
OUT_CH
I 00 MORE
ClI
IH
AL,021H
I 8E SURE TIMER IS DISABLED
OR
AL,OlH
OUT
STl
021H,AL
CALL
OSBL
014:5 28CO
0159 E2F4
0158 F9
DISC
DISC FA
0150 E421
364
305
307
308
0161 E621
30.
0163 F8
37.
371
0167 CB
016& 31373031
MOV
37'
373
374
BP,OFH
I POD ERROR FLAG
STC
POD_DONE:
300
015F OCOI
0164 EBASOD
ERROR_EX:
RET
FJ7
DB
375
F17L
EQU
370
377
HD_RESET_l
'1701',ODH.OAH
Clbt 00
0160 0.4.
0006
016E
S-F17
PROC
016E 51
378
PUSH
CX
016F 52
31.
PUSH
DX
30 Fixed Disk Adapter
NEAR
; SAVE REGISTER
LOC OBJ
LINE
0170 F8
0171 990001
0174
380
eLe
381
MOV
eX,OloaH
; RETRY COUNT
0174 e80706
383
CALL
PORT_I
DX,AL
; RESET CARD
0177 EE
382
SOURCE
; CLEAR CARPY
l6:
384
OUT
0178 E80306
385
CAll
PORT_l
0178 EC
386
IN
AL,Di<
; CHECK STATUS
; ERROR BIT
OI7e 2402
387
AND
AL.2
OI7E 7403
388
Jl
.3
0180 E2F2
389
lOOP
16
0182 F9
390
STe
0183
391
0183 SA
392
POP
OX
0184- 59
393
PDP
ex
0185 C3
R3:
394
395
RESTORE REGISTER
RET
HO_RESET_l
ENoP
DISK_SETUP
ENDP
396
397
398
399
;----- INT 19 ---------------------------------------------------
400
401
INTERRUPT 19 BOOT STRAP LOADER
402
403
THE FIXED DISK BIOS REPLACES THE INTERRUPT 19
404
BOOT STRAP VECTOR IHTH A POINTER TO THIS BOOT ROUTINE
405
RESET THE DEFAULT DISK AHe DISKETTE PARAMETER VECTORS
406
407
THE BOOT BLOCK 'to BE READ IN IolIlL BE ATTEMPTED FROM
CYLINDER a SECTOR 1 OF THE DEVICE.
408
THE BOOTSTRAP SEQUENCE IS:
409
> ATTEMPT TO LOAD FROM THE DISKETTE !HTO THE BOOT
410
LOCATION (0000:7COO) AND TRANSFER CONTROL THERE
> IF THE DISKETTE FAILS THE FIXED DISK IS TRIED FOR A
411
412
VALID BOOTSTRAP BLOCK. A VALID BOOT BLOCK ON THE
413
FIXED DISK CONSISTS OF THE BYTES
414
41.
417
055H OAAH
AS Tl-IE
LAST TWO BYTES OF THE BLOCK
> IF THE ABOVE FAILS CONTROL IS PASSED TO RESIDENT BASIC
415
;
---- ---- -- --- -------------- ----------------- ---- ----------------
418
0186
419
BOOT_STRAP:
420
ASSUNE
0186 2BCO
421
sua
OS :OUMHY, ES : DUMMY
AX,AX
0188 8E08
422
MOV
OS,AX
ESTABLISH SEGMENT
423
424
;----- RESET PARAMETER VECTORS
425
018A FA
013B C7060401E703
426
427
eLI
MoV
WORD PTR HF_TBL_VEC, OFFSET fD_reL
0191 8COE0601
42.
MoV
WORD PTR HF_TBL_VEC+Z. CS
0195 C70678000102
429
MoV
WORD PTR DISKETTE]ARH, OFFSET DISKETTE_TSl
019B 8COE7AOO
430
MoV
WORD PTR DISKETTE_PARM+2. CS
019F FB
431
sn
432
433
;----- ATTEMPT BOOTSTRAP FRON DISKETTE
434
DIAD 690300
435
MOV
CX.3
; SET RETRY COUNT
01A3
43.
01.4.3 51
437
PUSH
ex
1 SAVE RETRY COUNT
OIA4 2602
HI:
; IPL_SYSTEM
438
sua
OX.OX
01A6 2BCO
439
SUB
AX,AX
; RESET THE DISKETTE
01A8 CDll
440
INT
13H
; FILE 10 CAll
01AA nOF
441
Je
H2
; IF ERROR, TRY AGAIN
01AC 880102
442
MOV
AX,0201H
; READ IN THE SINGLE SECTOR
sua
DX,DX
;
DRIV~
ZERO
443
OlAF 2B02
444
01BI 8EC2
445
MOV
ES,DX
0163 BB007C
44.
MOV
ex .OFFSET BOOT_LOCN
I ESTABLISH SEGMENT
447
01B6 890100
448
MOV
CX.l
01B9 CDl3
449
INT
13H
; FILE 10 CAll
OlBB 59
450
POP
ex
; RECOVER RETRi COWl
OIBC 730A
451
JNC
H4
i CF
OlBE aOFC80
452
eMP
AH, BOH
j
01Cl 740A
453
Jl
H5
; TRY FIXED DISK
01C3 E20E
454
LOOP
HI
; DO IT FOR RETRY TIMES
OlCS EB0690
455
JMP
H5
; UNABLE TO IPL FROM THE DISKETTE
0lC8
45.
H2:
H4:
; SECTOR I, TRACK 0
SE~
BY UNSUCCESSFU!- READ
IF TIME OUT, NO RETRY
; IPL WAS SUCCESSFUL
Fixed Disk Adapter 31
LOC OBJ
OIC8 £A007COOOO
LINE
SOURCE
457
JMP
BOOT_LOCN
458
459
; ----- ATTEMPT BOOTSTRAP FROM FIXEO DISK
460
OICO
461
Oleo 2BCO
462
SUB
AX. AX.
OleF 2602
463
SUB
DX,DX
OlDl COB
464
INT
13H
0103 890300
0106
MOV
eX,3
466
0106 51
467
PUSH
ex
0107 BA800a
468
MOV
OX, ooaOH
; FIXED DISK ZERO
OIDA 28CO
469
SUB
AX,AX
; RESET THE FIXED DISK
H5:
465
H6:
; F1ESET DISKETTE
I SET RETRY COUNT
; IPl_SYSTEH
; SAVE RETRY COUNT
OlOe COl3
470
INT
13H
I FILE 10 CALL
alOE 7212.
DIED 880102
471
472
JC
H7
MOV
AX,0201H
I IF ERROR. TRY AGAIN
; READ IN THE SINGLE SEC'rOR
OlE3 2BDB
473
SUB
eX,ex
0lE5 SEC3
474
tlOY
ES,BX
0lE7 BB007e
475
MOV
BX,OFFSET BOOT_LoeN
OlEA BA8000
476
MOV
Dx,eOH
OlEO 690100
477
HOV
ex,}
; SECTOR 1, TRACK 0
DIFO C013
478
INT
13H
; FILE 10 CALL
CIF2 59
OlF3 7208
OIFS AIFE7D
ex
j
480
JC
HB
MOV
AX,WORD rTR BOOT_lOCN+510Q
DIF8 3D55AA
481
482
CMP
AX,QAA55H
OlFB 74CB
483
JZ
N4
OIFD
484
DIFO E207
485
486
LOOP
H6
OIFF COIB
479
487
488
489
H7:
POP
; TO THE BOOT LOCATION
; DRIVE NUMBER
j
RECOVER RETRY COUNT
TEST FOR GENERIC BOOT BLOCK
H8:
I DO IT FOR RETRY TIMES
j------ UNABLE TO IPl FROM THE OISKETTE OR FIXED DISK
INT
RESIOENT BASIC
18N
j
,
1 5RT=C. HO UNlQAD=OF -
1ST SPEC BYTE
; HO LOAD=l, MODE=OI1A -
2HD SPEC BYTE
490
0201
491
492
0201 CF
493
DB
0202 02
494
08
0203 25
495
08
0204 02
496
08
0205 08
497
08
0206 ZA
DISKETTE_ TBl:
llaOlUl8
25N
2
; WAIT AFTER OPN TIL MOTOR OFF
; 512 BYTES PER SECTOR
; EDT (LAST SECTOR ON TRACK)
498
08
02AH
0207 FF
499
08
OFFH
0208 50
500
08
050H
501
502
08
OF6H
; FILL BYTE FOR FORHAT
020A 19
08
25
1 HEAD SETTLE TIME (MILLISECONDS}
02.06 04
S03
08
02.09 F6
I
GAP LENGTH
DTl
; GAP LENGTH FOR FORHAT
; MOTOR START TIME (1/8 SECOND)
S04
505
;----- HAKE SURE THAT ALL HOUSEKEEPING IS DONE BEFORE EXIT
506
ozoc
S07
OSB L
PROC
NEAR
S08
ASSUME
DS:DATA
509
PUSH
OS
0200 B84000
510
MOV
AX,OATA
0210 8E08
5II
MOV
OS,AX
ozoc
1E
SAVE SEGMENT
51'
0212 8A267700
513
0216 50
514
HOV
PUSH
AX
; SAVE OFFSET
515
0217 C606770000
516
MOV
021e E86905
517
CALL
0211" 2ACO
518
sus
AL,AL
0221 EE
519
OUT
OX,AL
0222 C606770004
520
MOV
PORT_OFF ,4H
PORT_3
0227 E85E05
521
CALL
022A 2ACO
52'
523
SUB
AL.AL
D22C EE
OUT
OX.Al
0220 C606770008
524
MOV
PORT_OFf,8H
0232 E85305
525
CALL
PORT_3
PORT_3
0235 2ACO
526
SUB
Al,AL
0237 EE
527
OUT
OX.AL
0238 C60677000C
528
MOV
PORT_OFF. OCH
0230 E84805
529
CAll
PORT_3
D2tiO 2ACO
530
SUB
Al,AL
0242 EE
531
OUT
OX ,AL
'"
533
t10V
Al,07H
OUT
DMA+IO.AL
0243 B007
0245 E60A
32 Fixed Disk Adapter
; RESET !NT/DNA NASK
; RESET INT /DNA MASK
; RESET INT /DNA NASK
; RESET INT/ONA MASK
I SET DMA MODE TO DISABLE
LaC OBJ
LINE
SOURCE
0,47 FA.
02:48 E421
5,4
535
CLI
IH
Al,021H
024A oelD
536
DO
AL,OZIiIH
024C E621
537
OUT
024E FB
538
STI
024F 58
539
0250 88267700
540
0254 IF
541
02.55 C3
S42
543
; DISABLE INTERRUPTS
02lH,AL
; DISABLE INTERRUPT 5
; ENABLE INTERRUPTS
'0'
AX
MOV
PORT_OfF ,AH
PO,
OS
t RESTORE OFFSET
; RESTORE SEGMENT
RET
ENIlP
DSBl
544
545
I -- --- - - ---------- - -- --------------------
546
547
FIXED DISK BIOS ENTRY POINT
; - --
--------------- ----------------------
548
02:56
549
DISK_IO PROC
FAR
550
ASSUME
OS: NOTHING, ES: NOTHING
0256 80FAeo
551
CMP
Dl,80H
; TEST FOR FIXED DISK DRIVE
0259 7305
552
JAE
HARD_DISK
; YES, HAHOLE HERE
0258 C040
553
IHT
40H
0250
554
555
RET_2:
0260
556
557
HARD_DISK:
0260 FB
558
STI
0261 OAE4
559
OR
AH.AH
0263 7509
560
JHZ
A3
0250 CA02:00
RET
ASSUME
; DISKETTE HANDLER
I BACK TO CALLER
OS:O.1.T"
I ENABLE INTERRUPTS
0265 C040
0267 2AE4
561
INT
562
SUB
AH.AH
0269 80fA81
563
CMP
Dl.leOH + S_MAXJllE -
40H
026C 77Ef
564
JA
RET_2
I RESET NEt WHEN AH=O
1J
A3:
026E
565
026E 80FC08
566
CMP
0271 7503
567
JNZ
A2
0273 E91A01
568
JMP
GET_PARH_N
0276
569
0276 53
570
PUSH
ex
0277 51
571
PUSH
CX
AH,08
I GET PARAMETERS IS A SPECIAL CASE
A2;
0278 S2
572
PUSH
ox
0279 IE
573
574
PUSH
OS
027A 06
PUSH
ES
0276 56
575
PUSH
SI
027C 57
576
PUSH
or
CAll
DISK_Io_com
; SAVE REGISTERS DURING OPERATION
577
0270 E86AOO
578
PERFORM THE OPERATum
579
0280 50
sao
PUSH
AX
0281 E888FF
581
CALL
D56L
0284 684000
582
MOV
AX.DATA
0287 8ED8
583
MOV
DS,AX
0289 58
584
PO,
AX
02:8A 8A267400
585
MOV
AH ,DISK_STATUS
; GET STATUS FROM OPERATION
AH.l
,
OI
SI
; RESTORE REGISTERS
028E 80FCOl
586
CMP
0291 F5
587
CMC
0292 SF
588
POP
0293 5E
589
pop
0294 07
590
POP
0295 IF
591
POP
OS
0296 SA
592
0297 59
593
PO'
POP
ox
0298 56
594
POP
8X
0299 CA0200
595
RET
596
; BE SURE DISABLES OCCURRED
I ESTABLISH SEGMENT
I SET THE CARIi/)' HAG TO INDICATE
SUCCESS OR FAILURE
ES
CX
1 THROW MoIA)' SAvea
Fl.A~S
DISK_IO EtIDP
597
LABEL
worm
; FUNCTION TRANSFER TABLE
ow
DISK_RESET
; OOQH
D29E 4003
'99
600
OW
RETURN_STATUS
; OOIH
02AO 5603
601
OW
DISK_READ
I D02H
02A2 6003
6"
DISK_l>IRITE
02A4 6A03
6"
604
DISK_ VERF
I D04H
02A6 7203
ow
ow
ow
FHT_TFlK
; DOSH
02A8 7903
60S
OW
FMT_BAO
; 006H
02AA e003
606
I Q07H
607
60s
ow
ow
ow
ow
ow
FHT_DRV
02AC 3003
029C
02:9C 3803
OZAE 2704
0260 CF04
0262 0004
598
6"
610
M1
6AD_COHMAtro
INICORV
DOJH
ooaH
I 009H
RO_LONG
OOAH
WR_LONG
DosH
Fixed Disk Adapter 33
LaC OBJ
LINE
0284 F204
611
0286 ;3803
612
613
02SS F904
02BA. 0705
a2BC 1505
028E lCOS
02tO 2305
6,5
61,
617
618
02t4 3105
61.
620
ow
ow
DISK_SEEK
D~
RD_BUFF
ow
ow
ow
.w
ow
ow
61.
02e2 ZAOS
002A
SOURCE
MIL
EQU
; OOCH
,
OOOH
I OOEH
; OOFH
DISK_RESET
WR_BUFF
1ST_ROY
J 0101'1
HDISK_RECAL
I 011H
RAM_DIAG
I 012H
CHK_DRV
I 013H
CNTLR_DIAG
$-NI
; 014H
621
q2C6
622
623
02t6 C606740000
62.
625
02tB 51
6'6
627
SETUP_A PROt
NEAR
MbV
DISK_STATUS,O
J RESET THE STATUS INtl~CATOR
PUSH
CX
I SAVE
ex
1----- CALCULATE THE PORt QFFSET
6~8
02ec 8AEA
02eE 80CAOJ
0201 FEeA
629
630
MOV
CH,Ot
OR
CL,I
i SAVE DL
631
632
DEC
DL
SHL
pL'l
I GENERATE OFFSET
MOV
PORT_OFF ,OL
I STORE OFFSET
0209 8.1.05
633
634
"OV
OL.CH
• RESTORE Dl
~2DB
635
AND
OL,l
636
637
MOV
02EO 02E2
638
SHL
02E2 OA06
63.
64.
OR
Cl,S
Ct.eL
OltOH
0203 DOE2
0205 88167700
80E201
020E BI05
02E4 asi64300
I $HIFT COUNT
I DfHVE tM1BER I 0 ,I )
; HEAD I'U18ER
MOV
CMD_BlOCK+l,DL
OZE6 59
641
POP
ex
02E9 C3
642
RET
6ft3
SETUP_A EHDP
644
02EA
02EA 50
645
646
PUSH
AX
02EB 884000
647
MOV
AX ,DATA
02EE 8ED8
64'
64.
650
651
MOV
OS,AX
JHZ
A.
65'
653
JMP
RETURN_STATUS
~~
eMP
OL.80H
; CotNERT DRIVE HlII1BER TO 0 BASED RANGE
DL.MAXJILE
,
JAE
BAD_COMMAND
CALL
SETUP_A
02FO 58
02Fl 60FCOl
02F4 7503
02F6 E65590
02F9
OZf980EA60
654
~OFA08
02FF 732F
655
656
0301 E6C2FF
657
658
02FC
DISK_IO_CONT
"DC
POP
AX
CMP
AH.OIH
NEAR
; ESTABLISH SEGMENT
J
RET~N
STATUS
A4:
LEGAL DRIVE TEST
65~
660
661
; ----- SET UP CQt1t1AND BLOCK
0304 FEC9
662
DEC
CL
0306 C606420000
663
664
MeV
CHD_BLOCK+O.O
MeV
CHD_BLOCK+2,CL
03~B 880£4400
J SECTORS 0-16 FOR CotrrROLLER
; SECTOR AND HIGH 2 BITS CYLINDER
030F 862£4500
665
MOV
CMD_BLOCK+3.CH
0~13 1.24600
666
667
668
MOV
CI"IIJ_BLQCK+4.AL
J INTERLEAVE /
MOV
MOV
AL.CONTRQL_BYTE
; CONTROL BYTE (STEP OPTION)
0316 A07600
0319 A24700
J CYLINDER
BLOCK COUNT
CMD_BLOCK+5.Al
031t 59
~69
P\JSH
AX
J SAVE AX
031D 6At4
670
611
HOY
AL.AH
I GET INTO LOW BYTE
031F 32E4
0321 DIED
0323 8BFO
0325 302AOO
032656
0329 7305
0328 2EFFA49C02
0330
XOR
672
673
674
675
676
677
678
AH.AH
I ZERO HlliH BYTE
SAL
AX.l
I *2 FOR TABLE LOOKUP
MOV
SI.Ax
I PUT INTO SI FOR BRANCH
CMP
AX,HlL
; TEST WITHIN RANGE
POP
AX
; RESTORE AX
JN8
8~D_COHJ'1AND
JMP
WORD PTR CS:[SI + OFFSET Mll
BAD_COMMAND :
0330 C606740001
67.
MeV
DISK_STATUS. BAD_CtI)
0335 BODO
680
681
MOV
AL,O
RET
0337 Cl
; COMMAND ERROR
682
OISK_IO_C;ONT
68'
684
I - - - - - - - - - - - - - -- -- ----- --- ---------- -- - - ---------
61t~
686
681
ENDP.
RESET THE DISK SYSTEM
CAH = OOOH)
t ----------------------------,.------- - - - ----------
34 Fixed Disk Adapter
LaC OSJ
LINE
SOURCE
0338
688
0338 E84304
689
CAll
PORT_l
i
0336 EE
OUT
OX,AL
I ISSUE RESET
OBC E83F04
690
691
PORT_l
I CONTROLLER HARDWARE STATUS
033F EC
692
IN
AL.DX
; GET STATUS
0340 2402
0342 7406
69'
694
AND
AL.2
; ERROR BIT
JZ
ORI
0344 C606740005
695
HOV
DISK_STATUS ,BAD_RESET
O~49 C3
034A
696
697
034A E90AOO
698
699
DISK_RESET
CALL
PROt
NEAR
RESET PORT
RET
oRl:
JHP
OISK_RESET
INIT_DRY
SET THE DRIVE PARAMETERS
ENDP
700
701
702
0340
; - ---- - --- -- -- ----- --- -- ------------- -----------DISK STATUS ROUTINE
(AH
=
OOlH)
70 3
; -- ------ - -- - - --------- - -- - ---------- ------------
704
705
RETURN_STATUS
PROC
NEAR
0340 A07400
0350 C606740000
706
HOV
AL,DISK_STATUS
I
707
HOV
DISK_STATUS.O
i RESET STATUS
0355 C3
708
RET
OBTAIN PREVIOUS STATUS
709
710
711
71Z
713
i -----------------------------------------------DISK READ ROUTINE
(AH
= OOZH)
i ------------ - -- - --------- - -- ------------ --------
714
0356
0356 8047
715
716
HOV
0358 C606420008
717
718
719
HOV
0350 E9E501
DISK_READ
PROC
NEAR
MODE BYTE FOR OMA READ
AL.OMA_READ
JHP
DISK_READ
ENDP
720
721
722
7Z3
; -------------- ------ - ------ --- --- --------------DISK WRITE ROUTINE
(AH
=
003HI
; -------------------- - --------- --- ---------------
724
0360
725
0360 804B
726
727
728
0362 C60642000A
0367 E90801
PROC
HOV
NEAR
; HODE BYTE FOR DHA WRITE
AL.OHA_WRITE
HOV
729
730
731
732
036A
036A C606420005
036F E9C401
; --------- -- ---- ------- -------------------------DISK VERIFY
(AH
=
004H)
733
734
; ------------------------------------------------
735
736
737
OISK_VERF
738
739
DISK_VERF
740
; ------------------------ --- ---- -----------------
741
742
PROC
NEAR
HOV
JHP
FORHATTIHG
=
IAH
OOSH 006H 007H)
; ---------------------- -- ------------------------
743
0372
0372 C606420006
0377 EBOC
0379
0379 C606420007
037E EB05
744
745
746
FHT_TRK PROC
747
FHT_TRK ENDP
748
749
750
751
752
0380
753
754
0380 C606420004
755
0385
NEAR
; FORMAT TRACK
MOV
CHO_BLOCK. FMTTRK_CMO
JMP
SHORT
; FaRHAT BAD TRACK
(AH
; FORHAT DRIVE
=
= 006H)
FMT_BAD ENDP
HOV
756
FMT_DRV END?
757
758
FMT_CONT:
(AH
007H)
CMD_BLOCK. FHTORV_CI1O
759
HOV
AL.CMD_BlOCK+2
0388 24CO
760
761
AfID
AL,llOOOOOOB
HOV
CMD_BLOCK+2,AL
762
JNP
NDHA_OPN
038D E9A60 1
= OOSH)
JHe
0385 A04400
038A A24400
(AH
FHT_CONT
; ZERO OUT SECTOR FIELD
763
Fixed Disk Adapter 35
laC OBJ
LINE
SOURCE
764
; ------ .. ------ -----------------.. -------------- ---
765
766
767
GET PARAMETERS
(AH
0390
7.8
GET]ARH_N
LABEL
NEM~
0390
0390 1E
0391 06
769
GET_PARM
PROC
FAR
770
771
PUSH
OS
PUSH
ES
0392 53
PUSH
BX
ASSUME
DS:DUt1t1Y
0393 2BCO
77'
773
774
775
0395 6E08
776
Mav
OS,AX
0397 C41E0401
777
778
LES
BX,HF _TaL_VEe
ASSUME
OS:DATA
AX,DATA
SUB
AX,AX
ESTABLISH ADDRESSING
03'98 884000
77,
MOV
7.,
Mav
as,AX
C3Ae aOEABO
781
782
sull
DL,SOH
eMP
DL,MAX]IlE
JAE
G4
CALL
SETUP _A
03A) 80FAoe
783
784
i GET DRIVE PARAMETERS
o SAVE REGISTERS
039E 8E06
03A6 73ZF
= 8)
; -- .... ----- --- -- ------------------------------- ---
J eSTABLISH SEGMENT
I TEST WITHIN RANGE
785
03A8 E81BFF
786
787
03AE 7227
7M
789
03BO 0308
790
03A8 E80FOl
CALL
SW2_0FFS
JC
G4
ADD
BX,AX
Mav
AX,ES:[BXJ
SUB
AX,2
791
03B, 268B07
03B5 200200
792
793
03(:1
03BF DIES
Dell
794
795
796
797
798
799
03C3 8Ace
800
03es 266A7702
8"
8"
8"
03Ba 8AE6
03BA 250003
03BO 01E8
03C9 FEtE
03e8 6AI67500
03eF 2BCO
0301
0301 58
0302 07
0303 IF
0304 CAD20D
0307
0307 C606740007
ClOC 6407
030E 2Aca
804
8"
8"
.,7
MDV
CH,Al
I ADJUST FOR O-N
AND
AX,0300H
SHR
AX'}
SHR
AX.l
'R
MOV
CL,AL
I HIGH TWO BITS OF, cn
; SECTORS
AL,OllH
MOV
DH.ES:{BXJ!2J
; HEADS
DEC
MaV
OH
DLjHF _NUl1
; O-N RANGE
; DRIVE COUNT
SUB
AX,AX
pop
BX
POP
ES
POP
oS
G5 ~
.08
8"
8"
811
I MAX NUHBEF! OF CYLINDERS
I AND RESERve LAST TRACK
; RESTORE REGISTERS
RET
G4:
Mav
DISK_STATUS. INrCFAIL
8"
814
Mav
Sull
AH.INIT]AIL
AL,AL
812
03EO 2802
81S
SUB
DX,DX
03E2 2BC9
81.
SUB
CX,CX
03£4 F9
03ES EBEA
817
STO
JMP
818
8"
I OPERATION FAILED
I SET ERROR FLAG
GS
ENDP
GET_PARM
8"
621
822
8"
824
; ----- .. -- -----------------------------------------------I INITIALIZE DRIVE CHARACTERISTICS
FIXED DISK PARAMETER TABLE
825
826
THE TABLE IS COMPOSED OF A. BLOCK DEFINED A.S:
821
"8
...
(1 WORD) - MAXIMUM HUMBER Or CYLINDERS
8"
8"
(1 BYTE) - MAXIMUM ECC DATA BURST LENGTH
8"
8"
j
1 BYTE) - MAXIMUM tM1BER OF HEADS
(1
WORD' - STARTING REDUCED WRITE CURRENT
cn
(1 WORO I - STARTING WRITE PRECOMPENSATlON CYL
Il BYTEJ - CONTROL BYTE IDRIVE STEP OPTION)
BIT
7 DISABLE DISK-ACCESS RETRIES:
835
BIT
6 DISABLE ECC RETRIES
8"
BITS 5-3 ZERO
83'
BITS 2-0 DRIVE OPTION
837
838
(1 BYTE) - STANDARD TIME OUT VALUE (SEE BELCH)
8"
(1 BYTE J - TINE OUT VALUE FOR FORMAT DRIVE
8.,
(4 BYTES)
8.,
36 Fixed Disk Adapter
(1 eYTE) - TIME OUT VALUE FOR CHECK DRIVE
LOC OBJ
LINE
SOURCE
8.,
- RESERVED fOR FUTURE USE
8.3
8 ••
8.5
- TO DYNAMICALLY DEFINE A SET OF PARAMETERS
BUILD A TABLE OF VALUES AND PLACE THE
CORRESPONDING VECTOR INTO INTERRUPT 41.
84.
8.7
8.8
NOTE:
8.'
850
THE DEFAULT TABLE IS VECTORED IN FOR
AN INTERRUPT 19H (BOOTSTRAP J
851
8S>
853
; ON THE CARD SWITCH SETTINGS
85.
855
85.
DRIVE 0
857
858
8. .
DRIVE 1
ON
: -1-
-2- I -3-
-4-:
OFF
8.0
8.,
8.'
8.3
8 ••
8.5
TRANSLATION TABLE
1/3
8 ••
8.7
8.8
8.'
870
:
2/4
ON
ON
ON
OFF
OFF
ON
OFF
OFF
:
TABLE ENTRY
871
812
;
------------------------- -- - ------- - .------ .---- --------
a73
03E7
87.
875
87.
877
;----- DRIVE TYPE 00
03E7 3201
878
DW
03E9 02
87'
8ao
DO
02D
DW
03060
03EA 3201
03060
03EC 0000
881
DW
03EE DB
88'
883
DO
OOH
DO
OOH
OCH
03EF 00
00000
03FO DC
SS.
DO
03Fl 84
8"
88.
887
DO
OB4H
j
DB
028H
; CHECK DRIVE
DO
0,0,0,0
03F2 28
03F3 00000000
I STAHOARD
fORMAT DRIVE
888
03F7 7701
03F9 08
03FA 7701
88'
890
891
j-----
8"
8'3
DRIVE TYPE 01
DW
03750
DO
08D
DW
03750
03FC 0000
8'.
DW
00000
03FE DB
8"
8'.
897
DO
OOH
DO
05H
DO
OCH
03FF 05
0400 ac
0401 64
; STANDARD
8'8
DO
OB4H
j
0402 28
a"
00
026H
; CHECK DRIVE
0403 00000000
900
901
DB
0,0,0,0
'02
j-----
FORMAT DRIVE
DRIVE TYPE 02
903
0407 3201
90.
ow
03060
0409 06
040A BODO
905
DO
06D
90.
907
DW
01280
DW
02560
040C 0001
040E DB
Q40F
as
0410
ac
0411 84
0412 28
0413 00000000
908
DO
OOH
90'
910
D8
05H
DO
OCH
; STANDARD
'11
DO
D8
OB4H
j
028H
; CHECK DRIVE
DO
0,0,0,0
'"
913
FORHAT DRIVE
91.
0417 3201
915
91.
917
0419 04
918
;----- DRIVE TYPE 03
OW
03060
DB
040
Fixed Disk Adapter 37
LOC OSJ
LINE
041A 3201
919
OW
03060
041C 0000
920
OW
00000
041E DB
921
DB
OBH
SOURCE
041F 05
922
OB
05H
0420 DC
923
DB
OCH
I STANDARD
0421 B4
924
DB
DB4H
0422 28
925
DB
028H
; FORMAT DRIVE
; CHECK DRIVE
0423 00000000
926
DB
0,0,0.0
927
0427
928
IN IT_DRY
PROC
HEAR
929
930
; ----- DO DRIVE ZERO
931
0427 C606420QOC
932
MOV
CMD_BLDCKtO .INIT_DRV_tHO
04ZC C606430000
933
MOV
CMD_BLOCK+l.D
0431 E81000
934
CAll
INIT_DRV_R
0434 7200
935
JC
nUT_DRV_OUT
936
937
j-----
00 DRIVE ONE
938
0436 C6D64Z000C
939
MOV
CMD_BlOCK+D. INIT _DlN_Ct1D
0436 C606430020
0440 E80100
940
MDV
tHO_BLOCK+ 1. 001000006
941
CALL
INIT_ORV_R
0443
942
0443 C3
943
944
IN!T_DRV_OUT:
RET
WIT_DRV
EHOP
INIT_DRV_R
PROt
945
0444
946
947
0444 2ACO
948
ASSUME
ES:CODE
SUB
Al,Al
NEA.R
0446 E8190 I
949
CALL
tOMMAHO
0449 7301
0448 C3
950
JNt
Bl
951
RET
044C
952
044C IE
953
PUSH
OS
954
ASSUME
DS:Dl.It1HY
0440 2BCO
955
SUB
044F 8E08
956
MOV
; ESTABLISH SEGMENT
0451 C41E0401
957
LES
AX,AX
OS,AX
BX,HF _TBl_VEC
0455 IF
958
POP
OS
; RESTORE SEGMENT
0456 E83403
0459 7257
045B 0308
ISSUE THE COMMAND
Bl:
959
ASSUHE
OS:OATA
960
CAll
SW2:_0FF5
961
JC
B3
962
ADD
BX,AX
; SAVE SEGMENT
963
964
I~--~-
SEND DRIVE PARAMETERS MOST SIGNIFICANT BYTE FIRST
965
0450 BFOI00
966
MOV
0460 E85FOO
967
CALL
INIT_ORV_S
0463 7240
968
JC
B3
01.1
969
0465 BFOOOO
970
MOV
0468 E85700
971
CALL
lNlT_DRV_S
046B 7245
972
JC
B3
01.2
01.0
973
0460 BF0200
974
MDV
0470 E84FOO
975
CAll
INIT_ORV_S
0473 7230
976
JC
B3
977
0475 BF0400
978
MDV
0478 E84700
979
CAll
1NIT_DRV_S
0478 7235
980
JC
B3
0470 BF0300
982
MOV
01,3
0480 E83FOO
983
CAll
lNIT_ORV_S
0483 7220
984
JC
B3
01.4
981
985
0485 BF0600
986
MOV
0468 E83700
987
CAll
INIT_DRY_S
048B 7225
988
JC
B3
01.6
989
0480 BF0500
01,5
990
MDV
0490 E82FOO
991
CAll
nUT_ORV_S
0493 7210
992
JC
B3
993
0495 BF0700
994
MOV
01,7
0498 E82700
995
CAll
INlT_ORY_S
38 Fixed Disk Adapter
LaC OBJ
0498 7215
0490 BF0800
04AQ 26eAD 1
04A3 A27600
LINE
99.
997
99.
999
1000
1001
04A6 28C9
1002
04A8
1003
1004
04A8 E80302
04AB EC
SOURCE
JC
B'
MOY
DI,8
MOY
AL,ES:[BX + OIl
MOY
CONTROL_SHE.AL
; DRIVE STEP OPTION
SUB
eX,ex
CALL
PORT_l
85:
1005
IN
AL,DX
04AC ABOl
1006
TEST
AL ,R I_IOMODE
04AE 7509
1007
JNZ
86
0480 E2:f6
1008
lOOP
85
0482
1009
0482 C606740007
0487 f9
1010
MaY
DISK_STATUS.INITJAIL
1011
STC
0468 C3
; STATUS INPUT NODE
B1:
,OPERATION FAILED
RET
1012
1013
0489
1014
0489 E88502
1015
86:
CALL
PORT_O
04BC EC
1016
IN
AL.DX
0480 2402
ANO
AL,2
04BF 75Fl
1017
1018
JNZ
B1
04Cl C3
1019
RET
1020
ASSUME
; HASK ERROR BIT
ES: NOTHING
ENDP
1021
1022
1023
;----- SEND THE BHE OUT TO THE CONTROLLER
1024
04C2
1025
INIT_DRV_S
PROt
NEAR
04C2 E8e501
1026
CAll
HD_WAIT_REQ
04C5 7207
1027
JC
01
04C7 EBA70Z
1028
CALL
04CA 2MAOI
1029
NOV
AL,ES:tBX + OIl
04CO EE
1030
OUT
DX,AL
04CE
1031
04CE C3
1032
PORT_O
01:
RET
ENDP
1033
1034
1035
; ------------ ---------------- - ___ -- _____ _
1036
1037
1038
READ LONG
(AH
= OAH)
; ------------ - --------------- ---------- --
04CF
1039
04CF E81900
1040
CALL
CHK_LONG
0402 7268
1041
JC
G8
PRoe
NEAR
0404 C6064200E5
1042
MOV
0409 8047
1043
HOV
AL.DHA_READ
0406 EB68
1044
JMP
SHORT
1045
CMD_BLDCK+O,RD_LONG_CI1O
DHA_OPN
ENOP
1046
1047
; ------------------- - ----------------- __ _
WRITE LONG
1048
1049
1050
0400
1051
0400 EBOBOO
1052
04EO 7250
1053
(AH
OBH)
; ----------------------------- - ---------PROC
JC
NEAR
68
04E2 C60642:00E6
1054
04E7 8048
1055
HOV
Al,ONA_WRITE
04E9 EBSA
1056
JMP
SHORT
1057
WR_LOHG
DNA_OPN
ENOP
1058
04E8
1059
PROC
NEAR
04E6 A04600
1060
MOY
AL.CHD_BLOCK+4
04[E 3e80
1061
CMP
AL,080H
04FO FS
1062
04Fl C3
1063
1064
eMC
RET
CHK_LONG
ENilP
1065
1066
; ------------------ - -- --- ----- _____ --- __ _
1067
SEEK
I AH
OCH)
; -----------------------_ ----- ____ - _____ _
1068
=
1069
04F2
04F2 C606420008
1070
1071
MOY
CHO_BLoeK ,SEEK_eND
04F7 E630
1072
JMP
SHORT
PROC
HEAR
NOMA_OPN
Fixed Disk Adapter 39
LOC 06J
LINE
SOURCE
1073
1074
1075
ENDP
; --- .. -- - ... ------............... -- --- ...... --_ .. _______ "' __ .. ___ _
1076
1077
REAl) SECTOR BUFFER
UH
= DEH)
i -------- .. ----------------- .. ---------------------
1(178
04F9
1079
04F9 C606420DOE
Hl80
04FE C60b46DOOl
1081
11182
MOV
MOV
AL.OHA_READ
1083
1084
JMP
SHORT
0503 se47
050,5 E83E
, ONLY ONE BLOCK
CHD_BlOCK+4.1
DMA_OPH
!lUi/_BUFF ENDP
108S
1086
; .. -------------------------... -_ .. _________________ _
1187
lIJ88
WJfITE SECTOR BUFfER
I AH = IFH)
; ------------------------------------___________ _
OSI7 C"'428""
1089
1690
1691
osee C6U46DOOl
1092
MOV
CHll_BlDCK+4.1
0511 11948
109]
MOV
AL.DNA_WRITE
1094
JH"
SHaRT
0,87
osn Eel8
1096
1 0 97
DNA_OPH
; --------- -- --- .. - --------________________ .... ___ .. _ ..
1098
1 0 99
I ONLY ONE BLOCK
TEST DISK READY
(AH
= 01 OH)
; ----------------- --- _ - ---- --- --- - _____ .. ________ _
1110
0515
0$15 C:,,6£t20ote
05U EBlA
1101
TST_ROY PROC
NEAR
1102
MaV
CHO_BlOCKt-O, TST_ROY_C~
1103
JMP
SHORT
1104
NOHA_OPN
TST_RDY ENDP
1105
OSlt
D51C C606420001
0521 EBU
1106
; --.. -----.. ----------.. ---... ---------- _____ .. _______ _
1107
Il08
RECALIBRATE
(AH
011H)
; ------------- __ "._ .. __ ... ___ ... _______________ .... _____ _
1109
1110
HDISK_"ECAL
1111
MOV
tHO_BLOCK ,RECA~CHO
1112
JMP
SHORT
1113
HDISK_RECAL
=
PROC
NEAR
NDMA_OPN
ENOP
1114
1115
; -- .. -- .. ----------- .. ,.-- .. -------_________________ .. _____ .. __ _
1116
1117
CONTROLLER RAM DIAGNOSTICS
UH
012H)
; - .... ---------------------- ______________ .. ______ .. ________ _
=
1118
0523
0523 C60Mt200ED
1119
1120
MOV
0528 EBOC
1l/!:1
JMP
PAce
,NOP
1122
1123
1124
; - .. ---------- .. ------------------.. ----- .... --- ____ .. _
1125
1126
NEAR
DRIVE DIAGNOSTICS
(AH
= 013H)
; -----------.. ..,.----- .... --- .. ----------- .... -----------
1127
052A
1128
052A C6D6428eE3
aS2:F EB85
1129
CHK_DRV PROC
JMP
1130
1131
NEAR
CHK_DRV Et-I>P
1132
1133
J --... --- .......... ---- ....... ---- .. ------ .. - ......... ---.. ------------ .... -----
1134
1135
CONTROLLER INTERNAL DIAGNOSTICS
(AH
= 014HI
) ---------.--- ... ------.--- .... ---- .. -- .. ------ ... ---.......... -- .. ----
1136
0531
1137
0$31 C6f16421&E4
1138
PROC
MOV
NEAR
CMD_BLOCK+O .CNTLR....DIAG_CHD
ENDP
1139
11ItG
1536
1141
1142
i -------....... ----- .. ------------------.. --.. - .. ---------------SUPPORT ROUTINES
1143
ll44
1145
N&lMA_OP'N:
; - .. ------.------------------------ .. --------------------- ..
0536 eOll2
1538 E82:700
1146
HOV
1147
CALL
COMMAND
0538 7221
11-530 lun,
1148
JC
GIl
1149
JMP
SHORT
40 Fixed Disk Adapter
AL,02H
I IS$UE THE COtflAHD
Gl
LOC OBJ
LINE
SOURCE
053F
1150
053F C606740009
1151
NOV
0544 C3
1152
66:
RET
0545
1153
0545 E85701
1154
DISK_STATUS, DNA_BOUNDARY
; SET UP FOR DNA OPEPATION
0543 72F5
ll55
JC
G8
054A B003
US6
HOV
AL,03H
054C E81300
1157
CALL
COMMAND
054F nOD
1158
JC
G11
0551 B003
1159
NOV
Al,03H
0553 E60A
1160
OUT
DMA+! 0, Al
IN
AL,021H
Al,ODFH
0555
ll61
0555 E421
1162
0557 Z40F
1163
AtID
0559 HZ1
0558 EBAAOl
1164
OUT
021H,AL
CALL
WAIT_HIT
OSSE
1166
1167
CALL
EPPOR_CHK
1168
RET
OSSE E83800
0561 C3
; ISSUE THE COMMAND
; INITIALIZE THE DISK CHANNEL
G3:
1165
G11:
1169
1170
1171
; -------------------------------------------------------; COMNAND
1172
THIS ROUTINE OUTPUTS THE COMMAND BLOCK
1173
INPUT
1174
Al
=
CONTROLLER DNA/INTERRUPT REGISTER MASK
1175
1176
1177
; --------------------------------------------------------
1178
1179
COMNAHD PRot
0562 BE4200
0565 E81B02
Ilea
CALL
PORT_2
0568 EE
1181
OUT
DX,Al
0569 E81C02
1182
CALL
PORT_3
056C EE
1183
OUT
OX,Al
0560 2:8C9
1184
SUB
ex.cx
; WAIT COUNT
IN
AL,OX
; GET STATUS
0562
056F E80C02-
1185
0572
1186
0572 EC
1187
MOV
NEAR
SI,OFFSET CHD_BLOCK
CONTROLLER SELECT PULSE
0573 240F
1188
ANO
Al,OFH
0575 3COD
1189
CNP
Al.RI_BUSY OR RI_BUS 00 Rl_REQ
JE
Cl
0577 7409
1190
0579 ElF7
0578 C606740060
1191
lOOP
lIn
NOV
0580 F9
1193
0581 C3
1194
1195
0582-
0582 Fe
0583 B90600
STC
RET
1 ERROR RETURN
Cl:
CLD
1196
NOV
ll97
CX,6
; BYTE COUNT
CM3:
0586
1198
0586 E8E801
1199
0589 At
1200
lOOSB
058A EE
1201
OUT
OX.AL
; OUT IT GOES
0588 E2F9
1202
lOOP
CM3
; DO MORE
; STATUS
; GET THE NEXT COHNAN[) BYTE
1203
0580 E8EEOI
1204
CALL
PORT_l
0590 EC
1205
IN
AL,DX
0591 A80 1
1206
TEST
AL,RI_REQ
0593 7406
1207
JZ
CN7
0595 e606740020
1208
NOV
DISK_STATUS .BAD_CNTLR
059A F9
1209
STC
0598
1210
0598 C3
1211
1212
CM7:
RET
COMMAND ENDP
1213
1214
; ------ ------- --------- -- -- - - - - ------,. -------- ---
1215
SENSE STATUS BYTES
1216
1217
j
BYTE
a
1218
BIT
1219
BIT
SPARE, SET TO ZERO
1220
BITS 5-4
ERROR TYPE
BITS 3-0
ERROR CODE
1221
ADDRESS VALID, WHEN SET
1222
1223
BYTE 1
1224
BITS 7-6
ZERO
1225
BIT
5
DRIVE (0-11
1226
BITS 4-0
HEAD NUMBER
Fixed Disk Adapter 41
LaC OBJ
LINE
SOURCE
1227
1228
; BYTE 2:
1229
1230
BITS 7-5
CYlINDER HIGH
BITS 4-0
SECTOR HUMBER
BITS 7-0
CYLINDER LOW
1231
1232
1233
; BYTE 3
1234
1235
i ------- ------- - -------------- ------ -------------
1236
0590
1237
PROt
ERROR_CHK
NEAR
1238
ASSUME
ES:OATA
059C A07400
1239
MOY
AL,OISK_STATUS
059F OACO
1240
1241
OR
Al,Al
JNZ
G'I
1242
RET
05Al 7501
05A3 C3
1243
1244
j-----
I CHECK IF THERE WAS AN ERROR
PERFORM SENSE STATUS
1245
G21:
05A4
1246
05A4 884000
1247
MaY
05A 7 8EtO
1248
MaY
05A9 2BCO
1249
SUB
AX,AX
05A6 SSFe
1250
MOY
DI,AX
05AO C606420003
1251
MOY
CMD_BLOCK+O ,SENSE_tHO
0562 2ACO
1252
SUB
Al,Al
0564 E8ABFF
1253
1254
CALL
COMMAND
JC
SENSE_ABORT
0587 7223
0589 B90400
1255
osse
12:56
05BC E8CBOO
1257
AX,DATA
ES,AX
ESTABLISH SEGMENT
MOY
CX,4
CALL
HO_WAIT_REQ
G24
G22 :
05BF 7220
1258
JC
05Cl E8AOOI
1259
CALL
PORT_O
05C4 EC
1260
IN
Al.OX
1261
MaY
ES :HO_ERRORt OI] .Al
05C5 26884542
05C9 47
1262
INC
or
05CA E8BI01
1263
CAll
PORT_l
05CO E2ED
1264
LOOP
G22
05CF E88800
1265
CALL
HO_WAIT_REQ
0502 7200
1266
JC
G24
0504 E09AOl
1267
CALL
PORT_O
0507 EC
1268
IN
0508 A802
1269
TEST
AL.2
050A 740F
1270
JZ
STAT_ERR
050e
1271
05DC C6067400FF
1272
05El
1273
05El F9
1274
05E2 C3
; STORE AWAY SENSE BYTES
AL.oX
SENSE_ABORT:
MOY
DISK_STATUS .SENSE_FAIl
G24:
STC
1275
1276
i ISSUE SENSE STATUS COMMAND
; CAHNOT RECOVER
RET
ERROR_CHK
ENDP
1277
05E3 1A06
1278
T_O
OW
TYPE_a
05E5 2706
1279
T_I
OW
TYPE_I
05E7 6A06
1280
T_'
TYPE_2
1281
T_'
ow
ow
05E9 7706
TYPE_3
1282
05EB
1283
STAT_ERR:
; GET ERROR BYTE
05EB 268AIE4200
1284
MOV
Bl,ES:HD_ERROR
05FO 8AC3
1285
MaV
AliBl
05F2 240F
05F4 80E330
1286
1287
ANO
AND
Al.OFH
Bl. 00 1100008
05F7 2AFF
1288
SUB
BH.BH
05F9 BI03
1289
MOV
Cl.3
05FB 03EB
1290
SHR
BX,Cl
05FD 2EFFA7E305
1291
JMP
WORD PTR CS:[BX .. OFFSET T_O I
; ISOLATE TYPE
; ADJUST
ASSUME ES:NOTHING
1292
1293
TYPE a_TABLE
LABEl
BYTE
0602
1294
0602 00204020800020
1295
OB
O. BAD_CHTLR .BAO_SEEK • BAO_CHTLR • TIHE_OUT, 0, BAD_CN'lLR
0609 0040
1296
OB
o ,BAD_SEEK
1297
TYPEO_LEN
060B
1298
TYPE I_TABLE
060B 1010020004
1299
0610 400000110B
1300
0009
EOU
$- TYPEO_ TABLE
LABEl
BYTE
OB
BAD_ECC, BAD_ECC. BAD _AOOR_MARK. 0, RECORD_NOTJND
OB
BAD_SEEK.O. 0 ,DATA_CORRECTED .BAO_TRACK
1301
TYPEl LEN
EOU
$-TYPEl_TABlE
0615
1302
TYPE2_TABLE
LABEL
BYTE
0615 0102
1303
OOOA
42 Fixed Disk Adapter
OB
BAO_CND. BAD_AD OR_HARK
LOC OBJ
0002
0617
01)17 202010
0003
LINE
SOURCE
1304
TYPE2_LEN
1305
TYPD_TABLE
1306
1307
DB
TYPE3_lEH
EOU
$-TYPE2_ TABLE
LABEL
BYTE
BAD_CHTlR ,BAD_CHTLR ,BAD_ECC
EOU
$-TYPE3_ TABLE
1308
061A
1309
1310
;----- TYPE 0 ERROR
1311
TYPE_O :
061A 880206
1312
MOV
0610 3C09
CMP
Al. TYPED_LEN
OolF 7363
1313
1314
JAE
UNDEF _ERR_l
0621 2ED7
1315
XlAT
C5:TYPEO_TABLE
I TABLE LOOKUP
DISK_STATUS,AL
; SET ERROR CODE
0623 A27400
1316
MOV
0626 C3
1317
RET
BX.OFFSET TYPED_TABLE
; CHECK IF ERROR IS DEFINED
1318
1319
; ------ TYPE 1 ERROR
1320
0627
1321
TYPE_I:
0627 8BOB06
1322
MOV
BX,OFFSET TYPE I_TABLE
062A 86ca
1323
MOV
eX.AX
Obze 3COA
1324
CMP
AL,TYPEl_lEN
06ZE 7354
1325
1326
JAE
UNDEF _ERR_l
0630 ZED7
XlAT
CS:TYPEl_TABLE
0632 A27400
1327
MOV
DISK_STATUS,Al
; SET ERROR CODE
0635 80EI08
1328
AND
Cl , 08H
; CORRECTED Eec
0638 80F908
1329
CMP
Cl,08H
0638 7S2A
1330
JNZ
G30
; CHECK If ERROR IS DEFINED
i
TABLE LOOKUP
1331
1332
;----- OBTAIH ECC ERROR BURST lENGTH
1333
0630 t606420000
1334
0642 2ACO
1335
SUB
Al,Al
0644 E8lBFF
1336
CAll
COMMAND
0647 72lE
1337
JC
G30
0649 E83EOO
MOV
tNO_BlOtKtO IRO_Ett_tHO
1338
tAll
HD_WAIT_REQ
064C 7219
1339
JC
G30
064E E82001
0651 EC
1340
1341
tALL
IN
PORT 0
Al,OX
0652: 8At8
1342:
MOV
Cl,Al
0654 E83300
1343
tAll
HD_WAIT_REQ
0657 nOE
1344
JC
G30
0659 E81501
1345
CAll
PORT_O
06se Et
1346
IN
Al,DX
0650 A801
1347
TEST
Al,OlH
065F 7406
1348
JZ
G30
0661 t60674002:0
1349
MOV
OISK_ STATUS, BAO_ CNTLR
0666 F9
1350
STC
0667
1351
0667 8ACl
1352:
MOV
0669 C3
1353
RET
1354
1355
G30:
Al,Cl
; ----- TYPE 2 ERROR
1356
066A
1357
T'l'PE_2:
066A BBlS06
1358
MOV
0660 3C02
1359
CMP
Al, TYPE2_LEN
066F 7313
1360
JAE
UHDEF _ERR_L
0671 2E07
1361
XLAT
CS:TYPEl_TABlE
; TABLE LOOKUP
0673 A27400
1362
MOV
DISK_STATUS,AL
; SET ERROR CODE
0676 C3
1363
RET
BX,OFFSET TYPE2_TABlE
1 CHECK IF ERROR IS DEFINED
1364
1365
1----- TYPE '3 ERROR
1366
0677
1367
0677 BB1706
TYPE_3:
1368
MOV
067A 3t03
1369
CMP
Al, TYPE3_LEN
067t 7306
1370
JAE
UHOEF _ERR_l
067E 2E07
1371
BX,OFFSET TYPE3_ TABLE
XLAT
CS:TYPE3_TABlE
0680 A2:7400
1372
MOV
DISK_STATUS,AL
0683 t3
1373
RET
1374
0684
1375
0684 C6067400BB
1376
MOV
0689 C3
UNDEF _ERR_L:
1377
RET
DISK_STATUS,UHDEF _ERR
1378
068A
1379
068A 51
1380
HO_WAIT_REQ
PUSH
PROt
NEAR
cx
Fixed Disk Adapter 43
LOC OBJ
LINE
068& 28C9
068D E8[EOO
1381
0690
1383
1384
0690 EC
0691 A801
SOURCE
SU8
1382
eX,ex
CALL
PORT_l
IN
AL,OX
AL,Rl_REQ
U:
1385
TEST
0693 75118
1386
JNZ
0695 E2F9
1387
lOOP
LI
0691 C606740080
069C F9
1388
I10V
5TC
DISK_STATUS. TIME_OUT
069D
069D 59
1390
1391
1392
1393
pop
CX
069E CS
1389
I'
L2:
RET
HD_WAIT_REQ
EtIlP
1394
1395
1396
J -------------------------------- - .. - ...... ---------- .. --.,. .. -_ ..
; DMA_SETUP
1397
1198
ntIS ROUTINE SETS UP FOR DHA OPERATIONS.
i
INPUT
1399
(AU :: HODE BYTE FOR THE DHA
(ES:8Xl ;:; ADDRESS TO READ/WRITE THE DATA
1400
1401
1402
1403
069F
069F 50
1404
1405
0640 404600
1406
06A3 3(:81
1407
06.5 58
1408
06A6
n02
06A8 F9
I OUTPUT
I AX) OESTROYED
J .. -------------- .. ---------------------------------------DHA_SETUP
PROC
NEAR
PUSN
I10V
CMP
POP
JB
5TC
RET
1409
AX
AL.CI1D_BlOCK"4
.
AL,8tH
I BLOCK COUNT OUT OF RANGE
JI
06A9 C3
1'\10
1411
06AA
06AA 51
1412
1413
PUSH
CX
06A8 FA
06AC E60C
1414
1415
CLI
OUT
I SAVE THE REGISTER
j NO MORE INTERRUPTS
DI1A+12,AL
I SET THE FIRSTILAST FIF
MAE 50
1416
1417
PUSH
06AF 58
0680
0682
E~08
eceo
1418
1419
06B4 BI04
1420
06B6 DlGO
068& SAES
1421
1422
06BA 24FO
Obec 03C3
1423
1424
1425
06BE 7302
06CO FEC5
06C2
06C2 50
06C3 E606
06C5 8AC4
06C7 E606
06C9 8ACS
06CB 240F
06CD E682
1426
1427
0606 8AEO
0608 BOFF
060A 50
0608 Mft200
06DE 3Ce5
06EO 7407
06E2 3CE6
06E4 7403
06E6 58
06E7 EBll
06E9
06E9 58
06EA aa0402
06ED 53
POP
OUT
"OV
"OV
ROI
"OV
AND
ADD
mc
lNC
1431
1432
1435
1434
U.38
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1't55
1456
1457
AX
AX
DHA+ll.AL
AX,ES
Cl.4
AX,CL
CH,AL
J OUTPUT THE MODE BYTE
j GET THE ES VALUE
, SHlFT COUNT
Al.OFOH
I ROTATE LEFT
i GET HIGHEST NYBBLE OF ES TO CH
, ZERO THE LOW NYBBLE FROM SEGHENT
AX.BX
I TEST FOR CARRY FROM ADDITION
J33
eH
I CARRY HEANS HIGH 4 BITS MUST BE tNC
J33:
1428
1429
1430
1435
1436
1437
06CF A04600
0602 ODED
0604 FEC8
Jl:
PUSN
OUT
MOV
OUT
I10V
AX
, SAVE START ADDRESS
DI1A+6"U
AL.AH
OMA+6,Al
AL,CH
1 OUTPUT LOW ADDRESS
ANO
AL.OFH
OUT
DHA_HIGH.AL
j OUTPUT HIGH ADDRESS
I GET HIGH 4 BITS
i OUTPUT THE HIGH 4 BITS TO PAGE REG
1-----.. OETERHINE COUNT
I10V
SNI
DEC
I10V
I10V
Al,CtID_BLOCK+4
AL.l
Al
I RECOVER BLOCK COUNT
I HULTIPLY BY 512 BYTES PER SECTOR
ANO DECREMENT VALUE BY ONE
AH,Al
AL,OFFH
.
.
1----- HAtilLE READ AND WRITE LONG 15160 BYTE BLOCKS)
PUSH
,",V
C"P
JE
C"P
JE
POP
J"P
AL,ct1D_aLOCK+O
ALoRD_LONG_CHO
I SAVE REGISTER
I GET COMMAND
ADD_
AL.WR_lONG_CMD
A004
SHORT
1 RESTORE REGISTER
J20
ADD4;
44 Fixed Disk Adapter
POP
,",V
PUSN
AX
AX,516D
BX
I RESTORE REGIST~R
I ONE BLOCK (512) PLUS 4 BYTES ECC
LOC OBJ
06Ef 2AFF
LINE
SOURCE
1458
SUB
SH,SH
06FO 8AIE4600
1459
MOV
BL,CMD_BLOCK+4
06F4 52
1460
PUSH
OX
06F5 F7E3
1461
MUL
BX
06F7 SA
1462
1463
1464
PDP
OX
PDP
BX
AX
06F8 58
06F9 48
DEC
; BLOCK COUHT TIMES Sib
I ADJUST
J20:
06FA
1465
1466
06FA 50
1467
PUSH
AX
06FB E607
1468
1469
OUT
DMA+7.AL
MOV
AL,AH
OUT
OHA+7,AL
06FO 8AC4
D6FF f607
0702 S9
1470
1471
1472
0703 58
1473
0704 03el
1474
1475
1476
1477
1478
1479
0701 FB
0706 59
0707 C3
1480
SAVE COUHT VALUE
lOW BYTE OF COUNT
CX
1 HIGH BYTE OF COUHT
; INTERRUPTS BACK ON
; J;!ECOVER COUtU VALUE
AX
; RECOVER ADDRESS VALUE
sn
POP
POP
ADD
AX,ex
POP
CX
; ADD. TEST FOR 64K OVERflOW
; RECOVER REGISTER
; RE11..IRN TO cALLER. CFL SET BY ABOVE IF ERROR
.ET
DHA_SETUP
ENOP
,-----------------------------------------------; WAIT_lNT
1481
THIS ROUTINE WAITS FOR THE FIXED DISK
1482
CotHROLLER TO SIGNAL THAT AN ItHERRUPT
1483
HAS OCCURRED.
------------------ -- ----- --------------- --------
1484
;
0708
1485
WAIT_INT
0708 FB
1486
sn
0709 53
1487
PUSH
BX
PIWC
NEAR
TURN ON INTERRUPTS
PRESERVE REGISTERS
070A 51
1488
PUSH
070B 06
1489
PUSH
070C 56
1490
PUSH
CX
ES
51
0700 IE
1491
PUSH
OS
1492
ASSUME
070E 2BCO
1493
SUB
AX,AX
0710 8E08
1494
MOV
DS,AX
0712 C4360401
1495
LES
SI,HF_TBl_VEC
1496
ASSUME
OS:DATA
1497
POP
OS
0716 IF
OS:DUHMY
I ESTABLISH SEGMENT
1498
1499
;----- SET TIMEOUT VAlUES
1500
0717 2AFF
1501
SUB
BH,BH
0719 268A5C09
071D 8A264200
1502
1503
HOV
MOV
BL,BYTE PTR ES:tSIlt91
ani
1504
CMP
AH.FMTDRV_CMD
80FC04
0724 7506
1505
JHZ
W5
0726 268A5COA
1506
MOV
Bl.IHTE PTR ES:[SIHOAH]
JMP
SHORT
CMP
AH. CHK_DRV _CND
072A EB09
1507
onc
1508
80Fcn
onF 7504
1509
0731 268A5COB
1510
0735
1511
0735 28C9
1512
1015:
; STANDARD TIME OUT
AH,CMD_BLOCK
FORMAT DRIVE
W4
JHZ
W4
MOV
Bl.BHE PTR ES:[SIl!OBHl
SUB
CX.CX
; CHECK DRIVE
1014:
1513
1514
1----- WAIT FOR INTERRUPT
1515
0737
1516
loll:
0737 £84400
1517
073A EC
1518
IN
AL,DX
0738 2420
1519
AND
,A,L.020H
0730 3C20
CALL
PORT_l
1520
CMP
Al.020H
; DID INTERRUPT OCCUR
073F 740A
1521
JZ
0741 E2F4
1522
LOOP
W'
WI
; INNER LOOP
0743 4B
1523
DEC
JHZ
BX
WI
• OUTER LOOP
MOV
DISK_STATUS. TIME_OUT
0744 75Ft
1524
0746 C606740080
1525
0748
1526
074B E82300
1527
CALL
074E EC
1528
IN
AL.DX
074F 2402
1529
MID
AL.2
; ERROR BIT
1012:
PORT_O
0751 08067400
1530
OR
DISK_STATUS.AL
; SAVE
0755 E83000
1531
CALL
PORT_3
; INTERRUPT MASK REGISTER
0758 32CO
1532
XOR
AL,AL
; ZERO
075A EE
1533
OUT
OX.AL
; RESET MASK
0758 5E
1534
POP
51
; RESTORE REGISTERS
Fixed Disk Adapter 45
LOC OBJ
LINE
SOURCE
07se 07
1535
pop
0750 59
1536
1537
pop
CX
POP
BX
07SE 58
075F C3
0760
0760 50
0761 B020
0763 E620
0765 B007
0767 E60A
0769 E421
0766 DClD
1538
1539
1540
1541
1542
1543
ES
RET
WAIT_INT
HD_INT
ENOP
PROC
PUSH
AX
MOV
AL,EOI
INT_CTL_PORT,Al
J END OF INTERRUPT
AL,07H
DMA+IO,AL
AL,OZlH
; SET DHA HOOE TO DISABLE
1544
OUT
1545
1546
1547
MOV
OUT
IN
1548
NEAR
OR
AL.020H
0760 E621
1549
OUT
021H,AL
076f 58
1550
1551
POP
AX
0770 CF
1552
1553
IRET
HD_INT
ENOP
1554
;----------------------------------------
1555
, PORTS
1556
1557
1558
GENERATE PROPER PORT VALUE
8ASED ON THE PORT OfFSET
1----------------------------------------
1559
0771
1560
PROC
NEAR
0771 BA2003
1561
1562
MOV
DX.HF _PORT
PUSH
1563
SUB
0777 A07700
1564
MOV
077A 0300
077C 58
0770 C3
1565
ADO
AX
AH,AH
.U,PORT_OFF
OX.AX
1566
POP
AX
0774 50
0775 2AE4
PORT_O
1567
1568
j
BASE VALUE
I ADO IN THE OFFSET
RET
PDRT_O
ENOP
1569
077E
1570
PORT_l
PROC
NEAR
077E E8FOFF
1571
CALL
PORT_O
0781 42
1572
INC
OX
0782 C3
1573
RET
1574
PORT_l
ENOP
0783
1575
1576
PORT_2
PROC
0783 E8F8FF
1577
CALL
PORT_1
0786 42
1578
INC
OX
0787 C3
1579
RET
1580
PORT_2
ENOP
PORT_3
PROC
; INCREMENT TO PORT ONE
NEAR
I INCREMENT TO PORT TWO
1581
0788
1582
0788 E8F8FF
1583
CALL
PORT_2
0768 4Z
1564
INC
OX
076C C3
1585
RET
1566
PORT_3
NEAR
• INCREMENT TO PORT THREE
ENOP
1587
1566
1589
; -------~---------------------------------------I SW2_0FFS
1590
DETERHINE PARAMETER TABLE OFFSET
1591
USING CONTROllER PORT T1oIO AND
DRIVE NUNBER SPECIFIER (0-1)
1592
1593
1------------------------------------------------
0780
1594
1595
SW2.0FFS
0780 E8F3FF
1596
CALL
PORT_2
0790 EC
1597
IN
AL.OX
0791 50
1598
PUSH
AX
PROC
07901: E8E9FF
1599
CALL
PORT_I
0795 EC
1600
IN
AL,DX
0796 2402
1601
ANO
NEAR
AL.Z
0798 58
1602
POP
AX
0799 7516
1603
JNZ
SW2_0FFS_ERR
0798 8A264300
1604
MOY
079F 80E420
1605
1606
ANO
AH.00I00000B
07A2 7504
JNZ
SW2_AND
07A4 00E8
1607
SHR
Al.I
07A6 DOE8
1608
SHR
AL.I
07A8
1609
07A8 2403
07AA 8104
1610
ANO
MeV
AL.OllB
Cl.ft
I READ PORT 2
I CHECK FOR ERROR
AH .CMD_BLOCK+l
I DRIVE 0 OR 1
; ADJUST
SW2_AND:
1611
46 Fixed Disk Adapter
I ISOLATE
LOC OBJ
07Ae 02EO
07AE 2AE4
07BO C3
07Bl
LINE
SOURCE
1612
1613
SHL
AL,CL
SUB
AH,AH
1614
1615
RET
07Bl F9
1616
0782 C3
1617
1618
I ADJUST
SW2_0FFS_ERR:
STC
RET
SW2_0FfS
EHOP
1619
07B3 30382F31362F38
DB
1620
'08/16/82'
; RELEASE MARKER
32
1621
07B6
1622
END_ADDRESS
1623
CODE
1624
LABEl
BYTE
ENOS
ENO
Fixed Disk Adapter 47
Notes:
48 Fixed Disk Adapter
--------- -- -----_
.-
--
Personal Computer
Hardware Reference
Library
Fixed Disk and Diskette
Drive Adapter
Contents
Description .................................... 1
Fixed Disk Function ............................. 1
Task File .................................. 2
Task File Registers .......................... 2
Miscellaneous Information ................... 11
Diskette Function .............................. 11
Diskette Controller ......................... 14
Diskette Controller Commands ............... 16
Controller Commands ...................... 20
Command Status Registers ................... 32
Interfaces .................................... 36
Interface Lines ............................ 37
Logic Diagrams ................................ 41
iii
Notes:
iv
Description
The IBM Personal Computer AT Fixed Disk and Diskette Drive
Adapter connects to the system board using one of the system
expansion slots. The adapter controls the 5-1/4 inch diskette
drives and fixed disk drives. Connectors on the adapter supply all
the signals necessary to operate up to two fixed drives and one
diskette drive or one fixed drive and two diskette drives. The
adapter will allow concurrent data operations on one diskette and
one fixed disk drive.
The adapter operates when connected to a system board
expansion slot. This channel is described in the" System Board"
section of the IBM Personal Computer AT Technical Reference
Manual.
Fixed Disk Function
The fixed disk function features 512-byte sectors; high-speed,
programmed input/output (PIO) data transfers; error correction
code (ECC) correction of up to five bits on data fields; multiple
sector operations across track and cylinder boundaries; and
on-board diagnostic tests. The adapter will support two fixed
disks with up to 16 read/write heads and 1024 cylinders.
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 1
Task File
A task file, which contains eight registers, controls fixed-disk
operations. The following figure shows the addresses and
functions of these registers.
I/O Address
Primary
Secondary
1 FO
1 F1
1 F2
1 F3
1 F4
1F5
1 F6
1 F7
170
171
172
173
174
175
176
177
Read
Write
Data Register
Error Register
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
Status Register
Data Register
Write Precomp
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
Command Register
Task File
Task File Registers
Data Register
The data register provides access to the sector buffer for read and
write operations in the PIG mode. This register must not be
accessed unless a Read or Write command is being executed. The
register provides a 16-bit path into the sector buffer for normal
Read and Write commands. When a R/W Long is issued, the 4
ECC bytes are transferred by byte with at least 2 microseconds
between transfers. Data Request (DRQ) must be active before
the transferring of the ECC bytes.
I
I
Error Register
The error register is a read-only register that contains specific
information related to the previous command. The data is valid
only when the error bit in the status register is set, unless the
adapter is in diagnostic mode. Diagnostic mode is the state
immediately after power is switched on or after a Diagnose
command. In these cases, the register must be checked regardless
of the status register indicator. The following are bit values for
the diagnostic mode.
August 31, 1984
2 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Diagnostic Mode
01
No errors
02
Controller error
03
Sector buffer error
04
ECC device error
05
Control processor error
The following are bit definitions for the operational mode.
Operational Mode
Bit 0
Data Address Mark (DAM) Not Found-This bit
indicates that DAM could not be found within 16 bytes
of the ID field.
Bit 1
TR 000 Error-This bit will be set if, during a Restore
command, the track 000 line from the fixed disk is not
true within 1023 step pulses to the drive.
Bit 2
Aborted Command-A command is aborted based on
the drive status (Write Fault, Not Seek Complete, Drive
Not Ready, or an invalid command). The status and
error registers may be decoded to determine the cause.
Bit 3
Not used.
Bit 4
ID Not Found-The ID field with the specified cylinder,
head, and sector number could not be found. If retries
are enabled, the controller attempts to read the ID 16
times before indicating the error. If retries are disabled,
the track is scanned a maximum of two times before
setting this error bit.
Bit 5
Not used
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 3
Bit 6
Data Eee Error-This bit indicates that an
uncorrectable Eee error occurred in the target's data
field during a read command.
Bit 7
Bad Block Detect-This bit indicates that the bad block
mark was detected in the target's ID field. No Read or
Write commands will be executed in any data fields
marked bad.
Write Precompensation Register
The value in this register is the starting cylinder number divided
by 4. The I reduced write current I signal to the drive is activated
and the adapter's write precompensation logic is turned on when
this number is entered into the register.
Sector Count Register
The sector count register defines the number of sectors to be
transferred during a Verify, Read, Write, or Format command.
During a multi-sector operation, the sector count is decremented
and the sector number is incremented. When the disk is being
formatted, the number of sectors per track must be loaded into
the register prior to each Format command. The adapter supports
multi-sector transfers across track and cylinder boundaries. The
drive characteristics must be set up by the Set Parameters
command before initiating a multi-sector transfer. The sector
count register must be loaded with the number of sectors to be
transferred for any data-related command.
Note: A 0 in the sector count register specifies a 256-sector
transfer.
Sector Number Register
The target's logical sector number for Read, Write, and Verify
commands is loaded into this register. The starting sector number
is loaded into this register for multi-sector operations.
August 31, 1984
4 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Cylinder Number Registers
The target number for Read, Write, Seek, and Verify commands
is loaded into these registers as shown in the following figure. The
cylinder-number registers address up to 1024 cylinders.
Register Bits
Cvlinder Bits
Cylinder High
Cylinder Low
76543210
76543210
76543210
--98
Cylinder Number Registers
Drive/Head Register
Bit 7
Set to 1
Bit 6
Set to 0
Bit 5
Set to 1
Bit 4
Drive Select-This bit selects the drive. A 0
indicates the first fixed disk drive, and a 1
indicates the second.
Bit 3-Bit 0
Head Select Bits-Bits 3 through 0 specify the
desired read/write head. Bit 0 is the
least-significant (0101 selects head 5). The
adapter supports up to 16 read/write heads. For
access to heads 8 through 15, bit 3 of the fixed
disk register (address hex 3F6) must be set to 1.
Note: This register must be loaded with the maximum
number of heads for each drive before a Set Parameters
command is issued.
Status Register
The controller sets up the status register with the command status
after execution. The program must look at this register to
determine the result of any operation. If the busy bit is set, no
other bits are valid. A read of the status register clears interrupt
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 5
request 14. If -write fault or error is active, or if -seek
complete or -ready is inactive, a multi-sector operation is
aborted.
I
I
I
I
I
I
I
I
The following defines the bits of the status register:
Bit 7
Busy-This bit indicates the controller's status.
A 1 indicates the controller is executing a
command. If this bit is set, no other status
register bit is valid, and the other registers reflect
the status register's contents; therefore, the busy
bit must be examined before any fixed disk
register is read.
Bit 6
Drive Ready-A 1 on this bit together with a 1
on seek complete bit (bit 4) indicates that the
fixed disk drive is ready to read, write, or seek. A
o indicates that read, write, and seek are
inhibited.
Bit 5
Write Fault-A 1 on this bit indicates improper
operation of the drive; read, write, or seek is
inhibited.
Bit 4
Seek Complete-A 1 on this bit indicates that the
read/write heads have completed a seek
operation.
Bit 3
Data Request-This bit indicates that the sector
buffer requires servicing during a Read or Write
command. If either bit 7 (busy) or this bit is
active, a command is being executed. Upon
receipt of any command, this bit is reset.
Bit 2
Corrected Data-A 1 on this bit indicates that
the data read from the disk was successfully
corrected by the ECC algorithm. Soft errors will
not end multi-sector operations.
Bit 1
Index-This bit is set to 1 each revolution of the
disk.
August 31, 1984
6 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Error-A 1 on this bit indicates that the previous
command ended in an error, and that one or more
bits are set in the error register. The next
command from the controller resets the error bit.
This bit, when set, halts multi-sector operations.
Bit 0
Command Register
The command register accepts eight commands to perform fixed
disk operations. Commands are executed by loading the task file
and writing in the command register while the controller status is
not busy. If -write fault is active or if -drive ready or -seek
complete are inactive, the controller will not execute any
command. Any code not defined in the following figure causes an
Aborted Command error. Interrupt request 14 is reset when any
command is written. The following are acceptable commands to
the command register.
I
I
I
I
I
I
Command
Restore
Seek
Read Sector
Write Sector
Format Track
Read Verify
Diagnose
Set Parameters
Bits
7
0
0
0
0
0
0
1
1
6 5 4 3 2 1
0 0 1 R3 R2 Rl
1 1 1 R3 R2 Rl
0 1 0 0 0 L
0 1 1 0 0 L
1 0 1 0 0 0
1 0 0 0 0 0
0 0 1 0 0 0
0 0 1 0 0 0
0
RO
RO
T
T
0
T
0
1
Valid Command-Register Commands
Note: Stepping rate values and bit definitions for Land T
are shown in the following figures.
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 7
The following figure shows the stepping rate as defined by R3
through RO.
R3
R2
R1
RD
Stepping Rate
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
35 us
0.5 ms
1.0 ms
1.5 ms
2.0ms
2.5 ms
3.0ms
3.5 ms
4.0ms
4.5 ms
5.0 ms
5.5 ms
6.0 ms
6.5 ms
7.0 ms
7.5 ms
1
1
1
1
1
1
1
1
1
1
1
1
a
a
a
a
1
1
1
1
1
1
a
a
1
1
a
a
1
1
a
a
1
1
1
a
1
a
1
a
1
a
1
a
1
a
1
a
1
Stepping Rate
Note: After a Diagnose or Reset Command, the stepping
rate is set to 7.5 milliseconds.
The following figure shows the bit definitions for bits Land T.
Bit
L
T
Definition
Data Mode
Retry Mode
D
Data Only
Retries Enabled
1
Data Plus 4 Byte ECC
Retries Disabled
Land T Bit Definitions
Note: When retries are disabled, ECC and ID field retries
are limited to less than two complete revolutions.
Following are descriptions of the valid command-register
commands.
Restore: The controller issues step pulses to the drive until the
Track 000 indicator from the drive is active. If Track 000 is not
active within 1023 steps the error bit in the status register is set
and a Track 000 error is posted in the error register. The implied
seek step rate can be set up using the stepping rate figure on the
August 31, 1984
8 Personal Computer AT Fixed Disk and Diskette Drive Adapter
previous page. The restore step rate is established by the seek
complete signal from the drive (each step pulse is issued after
seek complete is asserted by the drive from the previous step).
Seek: The Seek command moves the R/W heads to the cylinder
specified in the task files. The adapter supports overlapped
seeking on two drives or setup of the buffered seek stepping rate
for the implied seek during a Read/Write command. An interrupt
is generated at the completion of the command.
Read Sector: A number of sectors (1-256) may be read from
the fixed disk with or without the ECC field appended in the
Programmed I/O (PIO) mode. If the heads are not over the
target track, the controller issues step pulses to the drive and
checks for the proper ID field before reading any data. The
stepping rate used during the implied seek is the value specified
during the previous Seek or Restore command. Data errors, up to
5 bits in length, are automatically corrected on Read Short
commands. If an uncorrectable error occurs, the data transfer
still takes place; however, a multi-sector read ends after the
system reads the sector in error. Interrupts occur as each sector is
ready to be read by the system. No interrupt is generated at the
end of the command, after the last sector is read by the system.
Write Sector: A number of sectors (1-256) may be written to
the fixed disk with or without the ECC field appended in the PIO
mode. The Write Sector command also supports implied seeks.
Interrupts for the Write command occur before each sector is
transferred to the buffer (except the first) and at the end of the
command. The first sector may be written to the buffer
immediately after the command has been sent, and I -data
request is active.
I
Format Track: The track specified by the task file is formatted
with ID and data fields according to the interleave table
transferred to the buffer. The interleave table is composed of two
bytes per sector as follows: 00, Physical Sector 1, 00, Physical
Sector 2, ... 00, Physical Sector 17. The table for 2-to-l
interleave is: 00,01,00, OA, 00, 02, 00, OB, 00, 03, 00, OC, 00,
04,00,OD,00,05,00,OE,00,06,00,OF,00,07,00,10,00,08,
00, 11, 00, 09. The data transfer must be 512 bytes even though
the table may be only 34 bytes. The sector count register must be
loaded with the number of sectors per track before each Format
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 9
Track command. An interrupt is generated at the completion of
the command; the Format Track command supports no error
reporting. A bad block may be specified by replacing a 00 table
entry with an 80.
When switching between drives, a restore command must be
executed prior to attempting a format.
Preform the following when formatting a drive with more than 8
read/write heads:
1.
Restore
2.
Format all cylinders, heads 0 - 7 only
3.
Restore
4.
Format all cylinders, heads 8 and above.
Read Verify: This command is similar to to a Read command
except that no data is sent to the host. This allows the system to
verify the integrity of the fixed disk drive. A single interrupt is
generated upon completion of the command or in the event of an
error.
Diagnose: This command causes the adapter to execute its
self-test code and return the results to the error register. An
interrupt is generated at the completion of this command.
Set Parameters: This command sets up the drive parameters
(maximum number of heads and sectors per track). The
drive/head register specifies the drive affected. The sector count
and drive/head registers must be set up before this command is
issued. The adapter uses the values specified for track and
cylinder crossing during multi-sector operations. An interrupt is
generated at the completion of this command. This command
must be issued before any multi-sector operations are attempted.
The adapter supports two fixed disk drives with different
characteristics, as defined by this command.
August 31, 1984
10 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Miscellaneous InCormation
The following is miscellaneous information about the fixed disk
drive function.
•
The adapter performs normal read/write operations on a
data field only after a successful match of that sector's ID
with the targeted ID.
•
ID fields are checked for errors when read from the disk.
•
The adapter supports only Eee on data fields and only eRe
on ID fields. The eRe polynomial is X16 + X12 + X5 + 1;
the Eee polynomial is X32 + X28 + X26 + X19 + X17 +
X10 + X6 + X2 + 1. All shift registers are preset to hex F
before calculating the checksums, which begin with the
respective address marks.
Diskette Function
The 5-1/4 inch diskette drive function is an integral part of the
Fixed Disk and Diskette Drive Adapter. One or two diskette
drives are attached to the adapter through an internal,
daisy-chained, flat cable. The attachment will support 160K.-,
320K.-, and 1.2M.-byte diskette drives.
The address assignments for diskette functions are shown in the
following figure.
I/O Address
Primary
Secondary
3F2
3F4
3F5
3F6
3F7
372
374
375
376
377
Read
Write
Main Status Register
Diskette Data Register
Digital Input Register
Digital Output Register
Main Status Register
Diskette Data Register
Fixed Disk Register
Diskette Control Register
Diskette Function
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 11
The adapter is designed for a double-density, MFM-coded,
diskette drive and uses write precompensation with an analog
circuit for clock and data recovery. The diskette-drive parameters
are programmable, and the diskette drive's write-protect feature is
supported. The adapter is buffered on the I/O bus and uses the
system board's direct memory access (DMA) for record data
transfers. An interrupt level also is used to indicate when an
operation is complete and that a status condition requires
microprocessor attention.
Digital Output Register (hex 3F2)
The digital output register (DOR) is an output-only register used
to control drive motors, drive selection, and feature enable. The
bit definitions follow:
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Drive B Motor Enable
Bit 4
Drive A Motor Enable
Bit 3
Enable Diskette Interrupts and DMA
Bit 2
Diskette Function Reset
Bit 1
Set to a logical 0
Bit 0
Drive Select-A 0 on this bit indicates that drive
A is selected.
Note: A channel reset clears all bits.
Digital Input Register (hex 3F7)
The digital input register is an 8-bit, read-only register used for
diagnostic purposes. The following are bit definitions for this
register:
August 31, 1984
12 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Bit 7
Diskette Change
Bit 6
Write Gate
Bit 5
Head Select 3/Reduced Write Current
Bit 4
Head Select 2
Bit 3
Head Select 1
Bit 2
Head Select 0
Bit 1
Drive Select 1
Bit 0
Drive Select 0
Note: Bits 0 through 6 apply to the currently
selected fixed disk drive. These bits are valid
for 50 microseconds after a write to the
Drive Head Register.
Data Rates
The diskette function will support three data rates: 250,000,
300,000 and 500,000 bits per second.
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 13
Diskette Controller
The diskette controller has two registers to which the system
unit's microprocessor has access: a status register and a data
register. The status register may only be read and is used to
facilitate the transfer of data between the processor and diskette
controller. The 8-bit status register has the status information
about the diskette and may be accessed at any time. The 8-bit
data register (hex 3F5), which actually consists of several
registers in a stack with only one register presented to the data
bus at a time, stores data, commands, and parameters, and
provides diskette-drive status information. Data bytes are read
from or written to the data register in order to program or obtain
results after a particular command.
The bits in the status register (hex 34F) are defined as follows:
Bit 7
Request for Master (RQM)- The data register
is ready to send or receive data to or from the
processor.
Bit 6
Data Input/Output (DIO)-The direction of
data transfer between the diskette controller and
the processor. If this bit is a 1, transfer is from
the diskette controller's data register to the
processor; if it is a 0, the opposite is true.
Bit 5
Non-DMA Mode (NDM)-The diskette
controller is in the non-DMA mode.
Bit 4
Diskette Controller Busy (CB)- A Read or
Write command is being executed.
Bit 3
Reserved
Bit 2
Reserved
Bit 1
Diskette Drive B Busy (DBB)- Diskette drive
B is in the seek mode.
Bit 0
Diskette Drive A Busy (DAB)- Diskette drive
A is in the seek mode.
August 31, 1984
14 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Diskette Control Register (hex 3F7)
This register is assigned two addresses, hex 3F7 (primary) and
hex 377 (secondary). This is a four bit write only register. The
bits are defined as follows:
Bits 7 - 2
Reserved
Bits 2 - 0
Diskette Data Rate- These bits select the
diskette data rate as shown in the following
figure:
Bit 0
Bit 1
0
0
1
1
0
1
0
1
Diskette
Data Rate
500,000 bps
300,000 bps
250.000 bps
Unused
Diskette Data Rate
Fixed Disk Register (hex 3F6)
This register is assigned two addresses, 3F6 (primary) and 376
(secondary). This is a four bit write only register. The bits are
defined as follows:
Bits 7 - 4
Reserved
Bit 3
A logical 0 enables reduced write current. A
logical 1 enables head select 3.
Bit 2
A logical 1 enables reset fixed disk function.
Bit 1
A logical 0 enables fixed disk interrupts.
Bit 0
Reserved
Note: Bit 3 defines the function of the fixed disk control
interface connector (pin 2).
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 15
Diskette Controller Commands
The diskette controller can perform 16 different commands.
Each command is initiated by a multibyte transfer from the
processor, and the result after execution of the command may
also be a multibyte transfer back to the processor. Because of
this multibyte interchange of information between the diskette
controller and the processor, each command can be considered to
consist of three phases:
Command Phase: The processor issues a sequence of Write
commands to the diskette controller that direct the controller to
perform a specific operation.
Execution Phase: The diskette controller performs the specified
operation.
Result Phase: After completion of the operation, status and
other housekeeping information is made available to the processor
through a sequence of Read commands to the processor.
The following is a list of commands that may be issued to the
diskette controller:
•
Read Data
•
Read Deleted Data
•
Write Data
•
Write Deleted Data
•
Read a Track
•
Read ID
•
Format a Track
•
Scan Equal
•
Scan Low or Equal
•
Scan High or Equal
August 31, 1984
16 Personal Computer AT Fixed Disk and Diskette Drive Adapter
•
Recalibrate
•
Sense Interrupt Status
•
Specify
•
Sense Drive Status
•
Seek
•
Invalid.
Symbol Descriptions
The following are descriptions of the symbols used in the
"Command Definitions" later in this section.
AO
Address Line O-A logical 0 selects the main status
register, and a 1 selects the data register.
C
Cylinder Number-Contains the current or selected
cylinder number in binary notation.
D
Data-Contains the data pattern to be written to a
sector.
D7 -DO Data Bus-An 8-bit data bus in which D7 is the
most-significant bit and DO is the least- significant.
DTL
Data Length-When N is 00, DTL is the data length to
be read from or written to a sector.
EOT
End of Track-The final sector number on a cylinder.
GPL
Gap Length-The length of gap 3 (spacing between
sectors excluding the VCO synchronous field).
H
Head Address-The head number, either 0 or 1, as
specified in the ID field.
HD
Head-The selected head number, 0 or 1. (H
all command words.)
= HD in
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 17
HLT
Head Load Time-The head load time in the selected
drive (2 to 256 milliseconds in 2- millisecond increments
for the 1.2M-byte drive and 4 to 512 milliseconds in 4
millisecond increments for the 320K-byte drive ).
HUT
Head Unload Time-The head unload time after a read
or write operation (0 to 240 milliseconds in
16-millisecond increments for the 1.2M-byte drive and 0
to 480 milliseconds in 32- millisecond increments for the
320K-byte drive.
MF
FM or MFM Mode-A 0 selects FM mode and a 1
selects MFM (MFM is selected only if it is
implemented. )
MT
Multitrack-A 1 selects multitrack operation. (Both
HDO and HDI will be read or written.)
N
Number-The number of data bytes written in a sector.
NCN
New Cylinder-The new cylinder number for a seek
operation
ND
Non-Data Mode- This indicates an operation in the
non-data mode.
PCN
Present Cylinder Number-The cylinder number at the
completion of a Sense interrupt status command
(present position of the head).
R
Record-The sector number to be read or written.
R/W
Read/Write-This stands for either a
signal.
SC
Sector-The number of sectors per cylinder.
SK
Skip-This stands for skip deleted-data address mark.
I
read or write
I
I
I
August 31, 1984
18 Personal Computer AT Fixed Disk and Diskette Drive Adapter
SRT
This 4 bit byte indicates the stepping rate for the
diskette drive as follows:
1.2M-Byte Diskette Drive
1111
1 millisecond
111 a 2 milliseconds
11 a 1 3 milliseconds
320K-Byte Diskette Drive
1111 2 milliseconds
111 a 4 milliseconds
11 a 1 6 milliseconds
ST O-ST 3 Status a-Status 3-0ne of the four registers that
stores status information after a command is executed.
STP
Scan Test-If STP is 1, the data in contiguous sectors is
compared with the data sent by the processor during a
scan operation. If STP is 2, then alternate sections are
read and compared.
USO-US1 Unit Select-The selected driver number encoded the
same as bits a and 1 of the digital output register
(DOR).
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 19
Controller Commands
The following are commands that may be issued to the controller.
Note: An X is used to indicate a don't-care condition.
Commands not shown in binary format are shown as bytes.
Read Data
Command Phase: The following bytes are issued by the
processor in the command phase:
07
MT MF SK
06
0
03 02
0 1
X
X
X HO
X
05
X
04
c
01
1
US1
DO
0
usa
H
R
N
EOT
GPL
OTL
Result Phase: The following bytes are issued by the controller in
the result phase:
STO
STl
ST2
C
H
R
N
August 31, 1984
20 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Read Deleted Data
Command Phase: The following bytes are issued by the
processor in the command phase:
07
06
05
04
MT MF SK
0
X
X
X
X
c
03 02
1 1
01
DO
0
0
X HO
US1
usa
H
R
N
EOT
GPL
OTL
Result Phase: The following bytes are issued by the controller in
the result phase:
STO
STl
C
H
R
N
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 21
Write Data
Command Phase: The following bytes are issued by the
processor in the command phase:
07
06
05
MT MF a
x X x
04
03 02
x
1
X HO
a a
c
01
DO
US1
usa
a
1
H
R
N
EaT
GPL
OTL
Result Phase: The following bytes are issued by the controller in
the result phase:
STO
STl
ST2
C
H
R
N
August 31, 1984
22 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Write Deleted Data
Command Phase: The following bytes are issued by the
processor in the command phase:
07 06 05 04
MT MF 0 0
X
X
X
03 02 01
1 0 0
X HO US1
X
00
1
USO
C
H
R
N
EOT
GPL
OTL
Result Phase: The following bytes are issued by the controller in
the result phase:
STO
STl
ST2
C
H
R
N
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 23
Read a Track
Command Phase: The following bytes are issued by the
processor in the command phase:
07
06
a
MF SK a
05
04
x x x x
03 02
c
01
a a 1
X HO US1
DO
a
usa
H
R
N
EaT
GPL
OTL
Result Phase: The following bytes are issued by the controller in
the result phase:
STO
STl
ST2
C
H
R
N
August 31, 1984
24 Personal Computer AT Fixed Disk and Diskette Drive Adapter
ReadID
Command Phase: The following bytes are issued by the
processor in the command phase:
07
06
05
04
a MF a a
x x x x
03 02
01
1
1
a
X HO
US1
DO
a
usa
Result Phase: The following bytes are issued by the processor in
the command phase:
STO
STl
ST2
C
H
R
N
Format a Track
Command Phase: The following bytes are issued by the
processor in the command phase:
07
06
05
04
03 02
1 1
X HO
a MF a a
x x x x
01
a
US1
DO
a
usa
N
SC
GPL
0
August 31, 1984
.
Personal Computer AT Fixed Disk and Diskette Drive Adapter 2S
Result Phase: The following bytes are issued by the controller in
the result phase:
STO
STl
ST2
C
H
R
N
Scan Equal
Command Phase: The following bytes are issued by the
processor in the command phase:
07
MT
06
MF
05 04
SK 1
X
X
X
X
c
03 02
01
0
0
0
X
HO
US1
DO
1
usa
H
R
N
EOT
GPL
STP
Result Phase: The following bytes are issued by the controller in
the result phase:
STO
STl
ST2
C
H
R
N
August 31, 1984
26 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Scan Low or Equal
Command Phase: The following bytes are issued by the
processor in the command phase:
07
MT
06 05 04
MF SK 1
X
X
X
X
c
03 02 01
1 0 0
X HO US1
DO
1
usa
H
R
N
EOT
GPL
STP
Result Phase: The following bytes are issued by the controller in
the result phase:
STO
STl
ST2
C
H
R
N
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 27
Scan High or Equal
Command Phase: The following bytes are issued by the
processor in the command phase:
07 06
MT MF
x
X
05 04
SK 1
x x
03 02
1 1
c
X
01
a
HO US1
00
1
usa
H
R
N
EDT
GPL
STP
Result Phase: The following bytes are issued by the controller in
the result phase:
STO
STl
ST2
C
H
R
N
Recalibrate
Command Phase: The following bytes are issued by the
processor in the command phase:
07
06
05
04
X
X
X
X
a a a a
03 02 01
00
0111
X a US1 usa
Result Phase: This command has no result phase.
August 31, 1984
28 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Sense Interrupt Status
Command Phase: The following bytes are issued by the
processor in the command phase:
07
o
06 05 04
000
03 02 01
100
00
0
Result Phase: The following bytes are issued by the controller in
the result phase:
STO
peN
Specify
Command Phase: The following bytes are issued by the
processor in the command phase:
07
o
(
(
06
0
05
0
SRT
04
0
)
HLT
03 02
0 0
(
01
00
1
HUT
1
) ( NO
Result Phase: This command has no result phase.
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 29
Sense Driver Status
Command Phase: The following bytes are issued by the
processor in the command phase:
07
06
05
04
03 02
a a a a a a
x x x x X HO
01
1
US1
DO
a
usa
Result Phase: The following bytes are issued by the controller in
the result phase:
sn
Seek
Command Phase: The following bytes are issued by the
processor in the command phase:
07
06
05
04
a a a a
x x x X
03 02
01
DO
1
1
1
1
X HO US1
usa
NCN
Result Phase: This command has no result phase.
August 31, 1984
30 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Invalid
Command Phase: The following bytes are issued by the
processor in the command phase:
07
X
06
05
X
Invalid Codes
X X X HO
04
03 02
01
00
US1
USO
Result Phase: The following byte is issued by the controller in
the result phase:
STO
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 31
Command Status Registers
The following is information about the command status registers
STO through ST3.
Command Status Register 0 (STO)
The following are bit definitions for command status register o.
Bit 7-Bit 6
Interrupt Code (IC)
00
Normal Termination of Command
(NT)-The command was completed and
properly executed.
01
Abrupt Termination of Command
(AT)-The execution of the command was
started but not successfully completed.
10
Invalid Command Issue (IC)-The issued
command was never started.
11
Abnormal termination because, during the
execution of a command, the ready signal
from the diskette drive changed state.
I
I
Bit 5
Seek End (SE)-Set to 1 when the controller
completes the Seek command.
Bit 4
Equipment Check (EC)-Set if a fault signal
is received from the diskette drive, or if the
track-O signal fails to occur after 77 step pulses
(Recalibrate Command).
I
I
I
I
Bit 3
Not Ready (NR)-This flag is set when the
diskette drive is in the not-ready state and a Read
or Write command is issued. It is also set if a
Read or Write command is issued to side 1 of a
single-sided diskette drive.
Bit 2
Head Address (HD)-Indicates the state of the
head at interrupt.
August 31, 1984
32 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Bit I-Bit 0
Unit select 0 and 1 (US 0 and 1 )-Indicate a
drive's unit number at interrupt. The following
figure shows the binary values to select each
drive:
Bit 1
Bit 0
Drive
Selected
0
0
0
1
0
1
A
B
Unused
Unused
1
1
Unit Selection
Command Status Register 1 (STl)
The following are bit definitions for command status register 1.
Bit 7
End of Cylinder (EC)-Set when the controller
tries to gain access to a sector beyond the final
sector of a cylinder.
Bit 6
Not Used-Always O.
Bit 5
Data Error (DE)-Set when the controller
detects a CRC error in either the ID field or the
data field.
Bit 4
Overrun (OR)-Set if the controller is not
serviced by the main system within a certain time
limit during data transfers.
Bit 3
Not Used-This bit is always set to O.
Bit 2
No Data (ND)-Set if the controller cannot find
the sector specified in the ID register during the
execution of a Read Data, Write Deleted Data, or
Scan Command. This flag is also set if the
controller cannot read the ID field without an
error during the execution of a Read ID
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 33
command or if the starting sector cannot be
found during the execution of a Read Cylinder
command.
Bit 1
Not Writable (NW)-Set if the controller detects
a I write-protect I signal from the diskette drive
during execution of a Write Data, Write Deleted
Data, or Format Cylinder command.
Bit 0
Missing Address Mark (MA)-Set if the
controller cannot detect the ID address mark. At
the same time, the MD of status register 2 is set.
Command Status Register 2 (ST2)
o.
Bit 7
Not Used-Always
Bit 6
Control Mark (CM)-This flag is set if the
controller encounters a sector that has a deleted
data-address mark during execution of a Read
Data or Scan command.
Bit 5
Data Error in Data Field (DD)-Set if the
controller detects an error in the data.
Bit 4
Wrong Cylinder (WC)-This flag is related to
ND (no data) and when the contents of C on the
medium are different from that stored in the ID
register, this flag is set.
Bit 3
Scan Equal Hit (SH)-Set if the contiguous
sector data equals the processor data during the
execution of a Scan command.
Bit 2
Scan Not Satisfied (SN)-Set if the controller
cannot find a sector on the cylinder that meets
the condition during a Scan command.
Bit 1
Bad Cylinder (BC)-Related to ND; when the
contents of C on the medium are different from
that stored in the ID register, and the contents of
C is FF, this flag is set.
August 31, 1984
34 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Bit 0
Missing Address Mark in Data Field (MD)- Set
if the controller cannot find a data address mark
or a deleted data address mark when data is read
from the medium.
Command Status Register 3 (ST3)
The following are bit definitions for command status register 3.
Bit 7
Fault (FT)-Status of the fault signal from the
diskette drive.
Bit 6
Write Protect (WP)-Status of the
write-protect signal from the diskette drive.
I
I
I
I
Bit 5
Ready (RY)-Status of the
the diskette drive.
Bit 4
Track 0 (TO)-Status of the
from the diskette drive.
Bit 3
Two Side (TS)-Status of the
from the diskette drive.
Bit 2
Head Address (HD)-Status of the side-select
signal from the diskette drive.
Bit 1
Unit Select 1 (US 1)-Status of the
unit-select-l signal from the diskette drive.
ready signal from
I
I
track 0 signal
I
I
two side signal
I
I
I
Bit 0
I
I
U nit Select 0 (US 0 )-Status of the
signal from the diskette drive.
o
I
I
unit select
I
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 35
Interfaces
The system interface is through the I/O channel. The address,
DMA, and interrupt assignments are shown in the following
figures.
I/O Address
Primary
Secondary
3F2
3F4
3F5
3F6
3F7
372
374
375
376
377
Read
Main Status Register
Diskette Data Register
DiQital Input ReQister
Write
Digital Output Register
Main Status Register
Diskette Data Register
Fixed Disk Register
Diskette Control ReQister
Diskette Function
Note: DMA request is level 2 and interrupt request is level 6.
I/O Address
Primary
Secondary
Read
Write
1FO
1 F1
1F2
1F3
1F4
1F5
1F6
1F7
Data Register
Error Register
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head Register
Status Register
Data Register
Write Precomp
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive / Head Register
Command Register
170
171
172
173
174
175
176
177
Fixed Disk Function
Note: Interrupt request is level 14.
The following operations are supported by this adapter:
•
16 bit programmed I/O (PIO), data transfers to the fixed
disk. All other transfers are 8 bits wide.
•
The I/O addresses, recognized by the adapter for either the
fixed disk.or the diskette function, are independently selected
by jumpers.
August 31, 1984
36 Personal Computer AT Fixed Disk and Diskette Drive Adapter
Interface Lines
The interface to the fixed disk drive consists of the Control cable
and the Data cable. The following figures show signals and pin
assignments for these cables.
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 37
2
1
··..
··..
··.
·.
34
-
r---
Ground - Odd Numbers
_ - Reduced Write Current/- Head Select 3
_ - Head Select 2
4
_ - Write Gate
6
- Seek Complete
-
8..
- Track 000
10 ..
- Write Fault
12.
-
-
_ - Head Select 0
14
Reserved
16
_ - Head Select 1
18
- -Index
-
22_
- Step
24
- Drive Select 1
26
-= - Drive Select 2
28
Reserved
30
Reserved
32
-
_ - Direction In
-
Fix ed Disk
And Diskette
Ada pter
20_
- Ready
-
2
-
-Fixed Dis k
Drive
1-33
34
'---
Note: Connection is through a 2-by-17 Berg connector. Pin
15 is reserved to polarize the connector.
August 31, 1984
38 Personal Computer AT Fixed Disk and Diskette Drive Adapter
1 2
..
-
-
Fixed Disk
Drive
+ MFM Write Data
13
- MFM Write Data
14
+ MFM Read Data
17
- MFM Read Data
18
Ground-Pins
2,4,6,11,12,15,16,19,20
Fixe d Disk
And Diskette
Ada pIer
All Other Pins Unused
-
'----
Note: Connection is through a 2-by-1O Berg connector. Pin 8
is reserved to polarize the connector.
August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 39
The interface to the diskette drives is a single cable that carries
both data and control signals. The signals and pin assignments are
as follows.
1 2
c:::::Jc:::::::::::J
c=J
C=:l
c::.::J
c:::::J;~c:::::::::::Jc::JCJ
c::::::J
C J== =
==
c:=::::J c:=::::J
~ c::::::J
c::==:J c::=::J [=::J c::::J c::J
c.::::::J c=J
c:::::::::::J c::l [===:J c::::::::J C=::J c:::::J c::J c:::::J c::::J
CJ~c_~=Jc=J~c:::J
c:::::J c:::::Jc::Jc:=::J
D~
···....
···...
··..
·
.
33 34
-
r---
Ground - Odd Numbers
--
Reduced Write
2
Reserved
4
-
Drive Select 3
6
Index
8_
---
Drive Select 0
10
Drive Select 1
12
Drive Select 2
14
Motor On
16
Direction Select
18
Step
20
Write Data
22
Write Gate
Track 00
24
26 _
Write Protect
28_
Read Data
30
Side 1 Select
32
Diskette Change
34 _
--
----
Diskette
Drive
--..
-
--
1-33
...
Fixe d Disk
And Diskette
Ada pter
..
..
..
L..-
Note: Connection is through a 2-by-17 Berg connector. Pin 5
is reserved to polarize the connector.
August 31, 1984
40 Personal Computer AT Fixed Disk and Diskette Drive Adapter
PUP IS {SNT 2,11
1)
PUP 51 {SHT 1.2.1.11
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August 31, 1984
Personal Computer AT Fixed Disk and Diskette Drive Adapter 47
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Fixed Disk and Diskette Drive Adapter (Sheet 9 of 9)
U48
veo
(SHT 1)
Notes:
August 31, 1984
50 Personal Computer AT Fixed Disk and Diskette Drive Adapter
----
--- ---------,-
Personal Computer
Hardware Reference
Library
IBM Personal Computer
20MB Fixed Disk
Drive Adapter
6139790
March 17, 1986
Notes:
Contents
Description ..................................... 1
Fixed Disk Controller .......................... 1
Programming Considerations ....................... 3
Types of Drives ............................... 3
Status Register ............................... 4
Sense Bytes .................................. 4
Data Register ................................ 7
Programming Summary ........................ 14
Interface ...................................... 15
Connectors ............... ;.................... 17
Logic Diagrams ................................. 19
BIOS Listing ................................... 23
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Index-l
March 17, 1986
v
Notes:
vi
March 17, 1986
Description
The 20MB Fixed Disk Drive Adapter attaches to one or two fixed
disk drive units through an internal, daisy-chained, flat cable
(datal control cable).
The adapter is buffered on the 110 bus and uses the system
board's direct memory access (DMA) for fixed-disk-drive data
transfers. When the adapter is enabled, an interrupt request
occurs on the IRQ-5 line to the 8259A Interrupt Controller. The
8259A then causes an interrupt hex OD.
The Fixed Disk Drive Adapter provides automatic 11-bit burst
error detection and correction in the form of 32-bit error
checking and correction (ECC).
The device level control for the Fixed Disk Adapter is contained
on a ROM module on the adapter. A listing of this device level
control can be found in "BIOS Listing" of this section.
Warning: The last cylinder on the fixed disk drive is reserved for
diagnostic use. The diagnostic write test will destroy any data on
this cylinder.
Fixed Disk Controller
The disk controller has three registers that may be accessed by the
system unit's microprocessor: a status register, a data register, and
a read-option-jumpers register. The 8-bit status register contains
the status information of the disk controller, and can be accessed
at any time. This register is read-only and is used to help the
transfer of data between the system unit's microprocessor and the
disk controller. The 8-bit data register (actually consisting of
several registers in a stack with only one register presented to the
data bus) stores data, commands, and parameters, and provides
the disk controller's status information. Data bytes are read from,
or written to the data register in order to program or obtain the
results after a particular command. The controller-select pulse is
generated by writing to port address hex 322.
March 17, 1986
20MB Fixed Disk Drive Adapter
1
The following is a block diagram of the IBM 20MB Fixed Disk
Drive Adapter.
Serial izerl
Deserializer
Control
Edge
liD
)
SERDES
ECC
liD
J2
Interface
J3
Interface
Connector
Data Bus
DB7-DBO
--
Sector Buffer
8-Bit
Processor
220MB Fixed Disk Drive Adapter
March 17,1986
Programming Considerations
Types of Drives
The fixed disk drive adapter will accommodate any two of four
different types of drives. The figure below shows the
configuration of the different type drives.
Cylinders
Heads
Start of
Write Pre-Camp
Landing
Zone
1
306
4
a
306
2
615
4
300
615
13
306
8
128
336
16
612
4
a
663
Type
Fixed Disk Types
The figure below shows the switch settings for the above
mentioned drive types. Switches 1 and 2 set the parameters of
Drive 0, and switches 3 and 4 set Drive 1.
Drive a
Drive 1
Switch
Switch
1
2
3
4
Type 1
On
On
On
On
Type 2
Off
On
Off
On
Type 13
Off
Off
on
Off
Type 16
On
Off
On
Off
March 17, 1986
20MB Fixed Disk Drive Adapter
3
Status Register
At the end of all commands from the system board, the disk
controller sends a completion status byte to the system board.
This byte informs the system unit's microprocessor if an error
occurred during the execution of the command. The following
shows the format of this byte.
I Bit I : I : I : I : I : I : I : I :
I
Bit 5
This bit shows the logical unit number
of the drive.
Bit 1
When set, this bit shows an error has
occurred during command execution.
Bits 7, 6, 4, 3, 2, 0
These bits are set to zero.
If the interrupts are enabled, the controller sends an interrupt
when it is ready to transfer the status byte. Busy from the disk
controller is unasserted when the byte is transferred to complete
the command.
Sense Bytes
If the status register receives an error (bit 1 set), the disk
controller requests four bytes of sense data. The format for the
four bytes is as follows:
Bits
7
Byte 0
Address
Va 1 i d
Byte 1
0
Byte 2
Cy 1 i nder High
Remarks:
5
0
Error Type
0
d
I I
Byte 3
4
6
2
3
I
1
0
Error Code
Head Number
Sector Number
Cylinder Low
d = drive
420MB Fixed Disk Drive Adapter
March 17, 1986
Disk Controller Error Tables
The following disk controller error tables list the error types and
error codes found in byte O.
The address-valid bit (bit 7) is only set when the previous
command required a disk address. Bit 6 is set to 0 (spare).
Error Error Code
Type
Bits
5 4
3 2
I
0
0
0
0
0
0
0 The controller did not detect any error
during the execution of the previous
operation.
0
0
0
0
0
I The controller did not detect an index signal
Description
from the drive.
0
0
0
0
I
0 The controller did not get a seek-complete
signal from the drive after a seek operation
(for all non-buffered step seeks).
0
0
0
0
I
I The controller detected a write fault from
the drive during the last operation.
0 After the contro 11 er selected the drive, the
drive did not respond with a ready signal.
I
0
0
I
0
I Not Used.
0
1
I
0 After stepping the maximum number of cylinders,
the contro 11 er did not receive the track 00
signal from the drive.
0
0
I
I
I Not Used.
0
I
0
0
0 The drive is st ill seeking. This status is
reported by the test Drive Ready command for
an overlap seek condition when the drive had
not completed the seek. No time-out is measured
by the contro 11 er for the seek to complete.
0
0
0
0
0
0
0
0
0
March 17, 1986
20MB Fixed Disk Drive Adapter
5
Error Error Code
Type
Bits
5 4 3
2
1
0
1 0
0
0
0 ID Read Error: The controller detected an
0
Description
ECC error in the target ID field on the disk.
0
1 0
0
0
1 Data Error:
The controller detected an
uncorrectable ECC error in the target sector
during a read operation.
0
1 0
0
1
0 Address Mark:
0
1 0
0
1
1 Not Used.
0
1 0
1
0
0 Sector Not Found:
0
1 0
1
0
1 Seek Error:
0
1 0
1
1
0 Not Used.
0
1 0
1
1
I Not Used.
0
1 1
0
0
0 Correctable Data Error:
0
1 I
0
0
1 Bad Track:
The controller did not detect
the target address mark (AM) on the disk.
The contro ller found the
correct cyl inder and head, but not the
target sector.
The cyl inder or head address
(either or both) did not compare with the
expected target address as a result
of a seek.
The controller
detected a correctable ECC error in the
target fie ld.
The controller detected a bad
track flag during the last operation. No
retries are attempted on this error.
Error Error Code
Type
Bits
6
5 4 3
2
I
0
1
o0
0
0
0 1nva lid Command:
I
o
0
0
1 Illega I Disk Address:
0
Description
The controller had
received an i nva lid command from the
system unit.
The controller detected
an address that is beyond the
maximum range.
20MB Fixed Disk Drive Adapter
March 17,1986
Error Error Code
Type
Bits
5 4 3
2
1
0
1
0
0
0 RAM Error:
1 0
Description
the controller detected a data
during the RAM sector-buffer
diagnostic test.
error
1
1 0
0
0
1 Program Memory Checksum Error:
1
1 0
0
1
0 ECC Polynomial Error:
During
this internal diagnostic test, the contro ller
detected a program-memory checksum error.
During the
contro ller' s i nterna 1 diagnostic tests, the
hardware ECC generator fa i led its test.
Data Register
The system unit's microprocessor specifies the operation by
sending the 6-byte device control block (DCB) to the controller.
The figure below shows the format of the DCB, and defines the
bytes that make up the DeB.
Bits
7
Byte 5
4
3
2
1
0
Interleave or Block Count
Byte 3
Byte 1
5
Control Field
Byte 4
Byte 2
6
Cy 1 i nder Low
Cy 1 i nder High
0
Byte 0
0
Command
Class
I
Sector Number
d
Head Number
Opcode
Byte 5
Bits 7 through 0 contain the control field.
Byte 4
Bits 7 through 0 specify the interleave or block
count.
Byte 3
Bits 7 through 0 are the eight least-significant bits
of the cylinder number.
March 17, 1986
20MB Fixed Disk Drive Adapter
7
Byte 2
Bits 7 and 6 are the two most significant bits of the
cylinder number. Bits 0 through 5 define the sector
number.
Byte 1
Bit 5 identifies the drive number. Bits 4 through 0
contain the disk head number to be selected. Bits 6
and 7 are not used.
Byte 0
Bits 7, 6, and 5 identify the class of the command.
Bits 4 through 0 contain the Opcode (see command
byte on page 10
Control Byte
Byte 5 is the control field of the DeB and allows the user to
select options for several types of disk drives. The format of this
byte is as follows:
I s;t I : I :
I :
I :
I :
I :
I :
I:
I
Bit 7
Disables the four retries by the controller on all
disk-access commands. Set this bit only during the
evaluation of the performance of a disk drive.
Bit 6
If set to 0 during read commands, a reread is
attempted when an Eee error occurs. If no error
occurs during reread, the command will finish
without an error status. If this bit is set to 1, no
reread is attempted.
Bits 5,4,3
Set to O.
820MB Fixed Disk Drive Adapter
March 17, 1986
Bits 2, 1,0
These bits define the type of drive and select the
step option. See the following figure.
Bits 2, 1, 0
0
0
0
This drive is not specified and defaults
to 3 mill i seconds per step.
0
0
1
N/A
0
1
0
N/A
0
1
1
N/A
1
0
0
200 microseconds per step.
1
0
1
70 microseconds per step (specified by BIOS).
1
1
0
3 mi 11 iseconds per step.
1
1
1
3 mi 11 iseconds per step.
March 17,1986
20MB Fixed Disk Drive Adapter
9
Command Byte
Command
Data Control Block
Remarks
Test Drive
Bit
76543210
d = drive (0 or 1)
Ready
Byte 0
000 0 0 0 0 0
x = don't care
(Class 0,
Opcode 00)
Byte 1
o0
Bytes 2, 3, 4,
5, = don't care.
Recalibrate
Bit
7 6 5 4 3 2 1 0
d = drive (0 or 1)
(Class 0,
Opcode 00)
Byte 0
x = don't care
Byte 1
o0
o0
Byte 5
rOO 0 0 s s s
d x x x x x
0 0 0 0 0 1
d
x x x x x
Reserved
(Class 0,
Opcode 02)
Request Sense
Status
(Class 0,
Opcode 03)
Format Drive
(Class 0,
Opcode 04)
Ready Verify
(Class 0,
Opcode 05)
r = retries
s = Step Option
Bytes 2, 3, 4, = don't care
ch = cyl inder high
This Opcode is not used.
Bit
7 6 5 4 3 2 1 0
Byte 0
o0 0 0 0 0 1 1
~----~------+---------~
Byte 1
o0 d x x x x x
d=drive(Oorl)
x = don't care
Bytes 2, 3, 4,
5, = don't care.
Bit
7 6 5 4 3 2 1 0
d = drive (0 or 1)
Byte 0
r = retries
Byte 1
o0
o0
Byte 2
ch 10 0 0 0 0 0
Byte 3
Cylinder Low
Byte 4
o0
Byte 5
rOO 0 0 s
Bit
76543210
d = drive (0 or 1)
Byte 0
o0
o0
0 0 0 101
r = retries
Byte 1
d Head No.
s = Step Option
Byte 2
ch ISector No.
Byte 3
Cy I i nder Low
000 1 0 0
~-----+----~--------~
d Head No.
0 Interleave
S 5
Byte 4
Block Count
Byte 5
r a 000 s s s
1020MB Fixed Disk Drive Adapter
s = Step Option
ch = cylinder high
Interleave 1 to 16
for 512-byte sectors.
a = retry option on
data ECC
ch = cylinder high
for 512-byte sectors.
March 17, 1986
Command
Data Control Block
Remarks
Format Track
Bit
7 6 5 4 3 2 1 0
d
~
dr i ve (0 or II
(Class 0,
Opcode 06)
Byte 0
r
~
retries
s
~
step option
Byte 2
o0 o0 1 10
0 o d Head No.
ch 10 o 0 0 0 0
Byte 3
Cylinder Low
Byte 1
Byte 4
Byte 5
Format Bad
Track
(Class 0,
Opcode 07)
o 0 01 Interleave
r 0 0 0 os s s
~
cylinder high
Interleave 1 to 16
for 512-byte sectors.
7 654 3 2 1 0
d
~
dr ive (0 or 1 )
Byte 0
0 0 0
o0
x
~
don't care
Byte 1
0 0 d Head No.
s
~
Step Option
Byte 2
ch 10
Byte 3
Cylinder Low
Byte 5
1 1 1
o 000
0
o 0 01 Interleave
r 0 0 0 o s s s
ch
~
cylinder high
Interleave 1 to 16
for 512-byte sectors.
Bit
7 6 5 4 3 2 1 0
d
~
dr i ve (0 or II
Byte 0
0 0 0 0 1 0 0 0
r
~
retries
Byte 1
0 0 d Head No.
a
~
Byte 2
ch Isector No.
Byte 3
Cyl inder Low
s
~
Byte 5
r a 000 s s s
ch
Reserved
(Class 0,
Opcode 09)
Write
(Class 0,
Opcode OA)
ch
Bit
Byte 4
Read
(Class 0,
Opcode 08)
0
retry option on
data ECC error
step option
~
cyl inder high
This Opcode is not used.
Bit
7 6 5' 4 3 2 1 0
d
~
Byte 0
0 0 0 0 1 0 1 0
r
~
Byte 1
0 0 d Head No.
s
~
Byte 2
chlsector No.
ch
Byte 3
Cy 1 i nder Low
Byte 4
Byte 5
March 17, 1986
dr ive (0 or II
retries
step option
~
cylinder high
Block Count
rOO 0 0 s s s
20MB Fixed Disk Drive Adapter
11
Command
Data Control Block
Remarks
Seek
Bit
7 654 3 2 1 0
(Class 0,
Opcode OB)
Byte 0
0 0
Byte 1
0 0 d Head No.
Byte 2
ch
o
d = drive (0 or 1)
r = retries
0 1 0 1 1
s = Step Option
10 000 0 0
x = don't care
Byte 3
Cy I i nder Low
Byte 4
x x x x x x x x
Byte 5
rOO 0 0 s s s
Bit
7 6 5 4 3 2 1 0
Bytes 1, 2, 3, 4, 5, =
Byte 0
0 000 1 1 0 0
don't care.
Read ECC
Burst Length
(Class 0,
Opcode 00)
Bit
76543 2 1 0
Bytes 1, 2, 3, 4, 5, =
Byte 0
o
don't care.
Read Data
from Sector
Buffer
(Class 0,
Opcode OE)
Bit
7 6 5 4 3 2 1 0
Bytes 1, 2, 3, 4, 5, =
Byte 0
o0
don't care.
Write Data to
Sector Buffer
(Class 0,
Opcode OF)
Bit
7 6 5 4 3 2 1 0
Bytes 1, 2, 3, 4, 5, =
Byte 0
o
don't care.
RAM
Diagnostic
(Class 7,
Opcode 00)
Bit
7 654 3 2 1 0
Byte 0
1 1 1
In i t i a Ii ze
Drive
Characteristics*
(Class 0,
Opcode OC)
0 0 0 1 1 0 1
0 0 1 1 1 0
000 1 1 1 1
o
0
Bytes 1, 2, 3, 4, 5, =
a a a
don't
care.
Reserved
(Class 7,
Opcode 01)
This Opcode is not used.
Reserved
(Class 7,
Opcode 02)
This Opcode is not used.
*Initial ize Drive Characteristics:
additional bytes.
The DBC must be fol lowed by eight
Maximum number of cylinders
Maximum number of heads
Start reduced write current cyl inder
Start write precompensation cylinder
Maximum ECC data burst length
(2
(1
(2
(2
(1
1220MB Fixed Disk Drive Adapter
bytes)
byte)
bytes)
bytes)
byte)
March 17, 1986
Command
Data Control Block
Remarks
drive (0 or 1)
Bit
7 6 5 4 3 2 1 0
d
=
Byte 0
1 1 1 0 0 0 1 1
r
=
retries
Byte 1
0 0 d x x x x x
s
=
step option
Byte 2
x x x x x x x x
x
=
don't care
Byte 3
x x x x x x x x
Byte 4
x x x x x x x x
Byte 5
r 0 0
Controller
Internal
Diagnostics
(Class 7.
Opcode 04)
Bit
7 6 5 4 3 2 1 0
Byte 0
1 1 1
Read Long *
Track
(Class 7.
Opcode 05)
Bit
7 6 5 4 3 2 1 0
d
=
dr i ve (0 or 1)
Byte 0
1 1 1
o0
r
=
retries
Byte 1
o0
s
=
step option
Byte 2
ch I Sector No.
Byte 3
Cy 1 i nder Low
Byte 4
Block Count
Dr i ve
Diagnostic
(Class 7.
Opcode 03)
Write Long **
(Class 7.
Opcode 06)
o0
o0
s s s
1 0 0
1 0 1
d Head No.
Bytes 1. 2. 3. 4. 5.
don't
ch
=
cyl inder high
Byte 5
rOO 0 0 s s s
Bit
7 6 543 2 1 0
d
=
drive (0 or 1)
Byte 0
1 1 1
o0
s
=
step option
Byte 1
0 0 d Head No.
s
=
step option
Byte 2
ch Isector No.
ch
Byte 3
Cyl inder Low
s
Byte 4
Block Count
Byte 5
=
=
cy 1 i nder high
step option
rOO 0 0 s s s
* Returns 512 bytes plus 4
** Requires 512 bytes plus
March 17, 1986
1 1 0
=
care.
bytes of ECC data per sector.
4 bytes of ECC data per sector.
20MB Fixed Disk Drive Adapter
13
Programming Summary
The two least-significant bits of the address bus are sent to the
system board's I/O port decoder, which has two sections. One
section is enabled by the I/O read signal (-lOR) and the other by
the I/O write signal (-lOW). The result is a total of four
read/ write ports assigned to the disk controller board.
The address enable signal (AEN) is asserted by the system board
when DMA is controlling data transfer. When AEN is active, the
I/ 0 port decoder is disabled.
The following figure is a table of the read/write ports.
R!W
Port Address
Function
Read
Wr i te
320
320
Read data (from controller to system unit)
Write data (from system unit to controller)
Read
Wr i te
321
321
Read controller hardware status.
Controller reset.
Read
Write
322
322
Read option jumpers
Generate controller-select-pulse
Read
Write
323
323
Not used.
Write pattern to DMA and interrupt
mask register.
1420MB Fixed Disk Drive Adapter
March 17,1986
Interface
The following lines are used by the disk controller:
AO-AI9
Positive true 20-bit address. The least-significant 10
bits contain the I/O address within the range of hex
320 to hex 323 when an I/O read or write is executed
by the system unit. The full 20 bits are decoded to
address the read-only memory (ROM) between the
addresses of hex C8000 and hex C9FFF.
DO-D7
Positive 8-bit data bus over which data and status
information is passed between the system board and
the controller.
-lOR
This signal is active when the system board reads
status or data from the controller under either
programmed I/O or DMA control.
-lOW
This signal is active when the system board sends a
command or data to the controller under either
programmed I/O or DMA control.
AEN
This signal is active when the DMA in the system
board is generating the I/O Read (-lOR) or I/O
Write (-lOW) signals and has control of the address
and data buses.
RESET
This signal forces the disk controller to its initial
power-up condition.
IRQ 5
This signal is active by the controller when enabled to
interrupt the system board on the return ending status
byte from the controller.
DRQ 3
This signal is activated by the controller when data is
available for transfer to or from the controller under
DMA control. This signal remains active until the
system board's DMA channel activates the
DMA-acknowledge signal (-DACK 3) in response.
March 17,1986
20MB Fixed Disk Drive Adapter
15
-DACK 3 This signal is active when negative, and is generated
by the system board DMA channel in response to a
DMA request (DRQ 3).
1620MB Fixed Disk Drive Adapter
March 17, 1986
Connectors
The 20MB Fixed Disk Drive Adapter connector and interface
specifications follow.
At Standard TTL Levels
Land
Number
Ground-Odd Numbers
1-33
-Reserved
-Head Select 2
Disk
Drive
J1
2, 16, 30, 32
4
-Write Gate
6
-Seek Complete
8
-Track 000
10
-Wr i te Fau It
12
-Head Select 0
14
-Head Select 1
18
-Index
20
-Ready
22
-Step
24
-D rive Select 1
26
-Drive Select 2
28
-Drive Select 3
30
-Drive Select 4
32
-D i rect ion In
34
March 17,1986
Disk
Adapter
J1
20MB Fixed Disk Drive Adapter
17
-Drive Selected
Reserved
Fixe d
Disk
Driv e
J2 0 r J3
I
3,5,7,9
Key
5
+MFM Wr i te Data
13
-MFM Wr i te Data
14
+MFM Read Data
17
-MFM Read Data
18
Ground Pins 2,4,6,8,10,11,12,15,
16,19,20
Fixed
Disk
Adapt er
J2 or J3
All Other Pins Unused
1820MB Fixed Disk Drive Adapter
March 17,1986
ISH.3A)
(SH.3)
(SH.3)
ISH.2.S)
ISH. 2. 3)
(SH.2.S)
.
.......
=
,-
IOHHZ
2
II
IRQ ~~
~i:
."iI''"
., ....,......
1&
PJOR
18
PlOW
'J6 PRST
82
A"
AI1
A"
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ISH. 2, 3)
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AA
A7
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00
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.,-06--
07
TA
au
20MB Fixed Disk Drive Adapter (Sheet 1 of 4)
DRQ~
IR.,
."
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, - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ItFH ROUTA
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1'1 D3
----------------------------i~-------~r_~~~-------C~,,-~.) ~
(SH.S)
(SH.4)
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(SH.l.S)
(SH.l,3)
(SH.l.3)
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(SH.3)
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(SH.3) L A T E - - - - - - - - - ' C > " - - -..C>"--t--'l::;:"'-t-:--....-----'
CD
I
IN HALF 1/2 OFLS2'+'+
20M B Fixed Disk Drive Adapter (Sheet 2 of 4)
ISH. 31
, "
'""
loJIZ( a
MIl
ISH_1,21
101f
(SH.l,21
EN HOST
ISH, 1)
ISH. 1)
BUSY
'""
I
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WR
22
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I
III " '"
~(SH,41
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AEN
20 BlJSACK
lDRQ
MIirQ
20
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IOREQ
16 MREGI
17
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I5l1J
OAI
DA2
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2
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,.,
B
LDI
~
ENRO
39~
24
14
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XENO
"
MFH'JTDTA ~b
WTGTE 37
CLAMP 28
---"
vco
NEG PlJI1P ~2
HIrn'IT 2~
I1FH IoIT DATA
WRITE GATE
(SH.ll
KO CLAMP
.".....,..
(SH.4)
(SH.4)
NEG PUMP
mmmTA 22
"""'"
EARLY
(SH.4)
(SH.4)
(SH.4)
LATE
(SH.2l
EARLY
(SH_l)
~~'~'_£j2 '!MHZ
ISH. 1,2)
ISH.l,2)
ISH. 1,2)
ISH.l,l)
(SH.l)
ISH 1)
ISH.l)
ISH 1)
-I . < 2 - - - - - - _ C I : )
NRZ
(lO(K----------'1'f>>"'-------~GL)
10 M'2 "OCK
PI
RIO
89D~·~I2~V_~~--~---~~~---~---_
81.810
-----------""J{),;''----------QD
~-------------------~
BEAD
IKTVP
~.'
(SH.3)
DISABLE AM _ _ _ _ _ _ _ _ _
'Ie
(8H.2)
"==r-
~~-~---~----LT~---~----
~l'L'__R"'I~4_ _ _ _ ____{OD
-------------------~ 2.8.17
TESTENABLE-------------------- SOH - 0 I SK
REAO THE DESIRED SECTORS INTO MEMORY
WRITE THE DESIRED SECTORS FROM MEMORY
VER I FY THE DES I RED SECTORS
FORMAT THE OES I RED TRACK
FORMAT THE DESIRED TRACK AND SET BAD SECTOR FLAGS
FORMAT THE DRIVE STARTING AT THE DESIRED TRACK
RETURN THE CURRENT DR [VE PARAMETERS
[N[TlALIZE DRIVE PAIR CHARACTERISTICS
INTERRUPT 41H POINTS TO DATA BLOCK
READ LONG
WR I TE LONG
NOTE: READ AND WRITE lONG ENCOMPASS
512 BYTES + 4 BYTES OF ECC
SEEK
AL TERN ATE DISK RESET (SEE DL I
READ SECTOR BUFFER
WR I TE SECTOR BUFFER,
(RECOMMENDED PRACT I CE BEFORE FORMATT [NG)
TEST OR I VE READY
RECAL I BRA TE
CONTROLLER RAM 0 [AGNOST I C
DRIVE DIAGNOSTIC
CONTROLLER INTERNAL 0 I AGNOST [C
REGISTERS USED FOR FIXED DISK OPERATIONS
(DLI
(DHI
(CHI
(CLI
56
57
58
59
60
DR[VE NUMBER
HEAD NUMBER
CYLINDER NUMBER
SECTOR NUMBER
(AU
64
65
(ES:BXI
66
67
69
70
71
72
73
HIGH 2 BI TS OF CYL [NDER NUMBER ARE PLACED
IN THE HIGH 2 BITS OF THE CL REGISTER
(10 BITS TOTAl)
NUMBER OF SECTORS (MAXIMUM POSSIBLE RANGE 1-80H,
FOR READ/WRITE LONG 1-79H)
( I NTERLEA VE VALI,IE FOR FORMAT I - I 60 I
ADDRESS OF BUFFER FOR READS AND WR [TES,
(NOT REQU I RED FOR VER I FY I
NOTE:
61
62
63
68
(80H-87H FOR DISK, VALUE CHECKED)
(0-70 ALLOWED, NOT VALUE CHECKED I
(0-10230, NOT VALUE CHECKED) (SEE CU
( 1-170, NOT VALUE CHECKED)
OUTPUT
AH " STATUS OF CURRENT OPERATION
STATUS BITS ARE DEFINEO IN THE EGlUATES BELOW
SUCCESSFUL OPERATION (AH" OOH ON RETURN)
CY = 0
CY " I
FA[LED OPERATION (AH HAS ERROR REASON)
74
75
NOTE:
76
77
78
79
80
81
82
83
84
85
ERROR IIH
[NDICATES THAT THE DATA READ HAD A RECOVERABLE
ERROR WHICH WAS CORRECTED BY THE ECC ALGORITHM.
THE DATA
IS PROBABLY GOOD,
HOWEVER THE BIOS ROUT I NE I NO [CA TES AN
ERROR TO ALLOW THE CON TROLL [NG PROGRAM A CHANCE TO DEC I DE
FOR
ITSELF,
THE
ERROR
MAY
NOT
RECUR
IF THE DATA IS
REWRITTEN. (ALI CONTAINS THE BURST LENGTH.
I F DR I VE PARAMETERS WERE REQUESTED,
DL "
DH "
CH "
CL "
86
87
88
89
NUMBER OF CONSECUTIVE ACKNOWLEDGING DRIVES
ATTACHED (0-21
ICONTROlLER CARD ZERO TALLY ONLYI
MAX I MUM USEABLE VALUE FOR HEAD NUMBER
MAXIMUM USEABLE VALUE FOR CYLINDER NUMBER
MAX I MUM USEABLE VALUE FOR SECTOR NUMBER
AND CYL I NDER NUMBER H [GH BITS
90
91
92
IF AN ERROR OCCURS ON READ DRIVE PARAMETERS,
AH " ERROR CODE (INIT FAILI
AL :: CX '" OX " 0
-
93
94
95
96
97
REGISTERS WILL BE PRESERVED EXCEPT WHEN THEY ARE USED TO RETURN
INFORMATION.
98
99
NOTE:
100
101
102
24
IF AN ERROR [S REPORTED BY THE D[SK CODE, THE APPROPRIATE
ACT I ON I S TO RESET THE 0 [SK, THEN RETRY THE OPERAT I ON.
20MB Fixed Disk Drive Adapter BIOS
March 17, 1986
[BM Person .. 1 Computer MACRO Assemb I er
DISK2 ---- 10/28/85
F[XED DISK BIOS
103
104
105
1-2
10-28-B5
Vers I on 2.00
PAGE
;
;
----- - - -- ------- - ------- ------- - - ---- - -- - -------- - -----ERROR RETURN STATUS
(AH)::
PH
WHEN
CY=
I
106
107
108
109
110
I I 1
112
1 13
114
115
I 16
I 17
I 18
I 19
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
DOFF
:: OOCC
OOBB
0080
:: 0040
0020
0011
00 I 0
OOOB
0009
0007
0005
0004
0002
0001
SENSE FAIL
WR I TE-F AUL T
UNDEF-ERR
TIME OUT
BAD SEEK
BAD-CNTLR
DA TA CORRECTED
BAD ECC
BAD-TRACK
DMA -BOUNDARY
[NIT FAIL
BAD RESET
RECaRD NOT FNo
BAD ADDR MARK
BAo::::CMo -
0000
0034
0034
004C
004C
0064
0064
0078
0078
0 I 00
0100
0104
0 I 04
7COO
7COO
7COO
ABSO
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
OFFH
OCCH
OBSH
080H
040H
020H
o 11H
O\OH
OOBH
009H
007H
005H
004H
002H
00 I H
SENSE OPERAT I ON FA [LED
WRITE FAULT ON SELECTED DRIVE
UNDEF I NED ERROR OCCURRED
A TT ACHMENT FA I LED TO RESPOND
SEEK OPERATION FAILED
CONTROLLER HAS FA [LEO
ECC CORRECTED DATA ERROR
BAD ECC ON 0 [SK READ
BAD TRACK FLAG DETECTED
ATTEMPT TO OMA ACROSS 64K BOUNDARY
DRIVE PARAMETER ACTIVITY FAILED
RESET FAILED
REQUESTED SECTOR NOT FOUND
ADDRESS MARK NOT FOUND
BAD COMMAND PASSED TO 0 I SK I {a
I NTERRUPT AND STATUS AREAS
;- - - --------- - -
- --
-
- --
SEGMENT AT OH
DISKETTE_PARM
LABEL
01 SK_VECTOR
LABEL
HF _ TBL_ VEC
LABEL
ORG
000H·4
DWORO
o 13H·4
DWORD
o 19H·4
oWORD
01 EH·4
DWORD
040H-4
oWORD
041H·4
DWORD
7COOH
BOOT LOCN
ABSOENOS
LABEL
FAR
ORG
Ho [SK
I NT
LABEL
ORG
ORG_ VECTOR
LABEL
BOOT _ VEC
LABEL
ORG
ORG
ORG
ORG
F [XED 0 I SK
DISK
I NTERRUPT VECTOR
I NTERRUPT VECTOR
BOOTSTRAP
INTERRUPT VECTOR
DISKETTE PARAMETERS
NEW 0 I SKETTE
[NTERRUPT VECTOR
F I XED 0 [SK PARAMETER VECTOR
BOOTSTRAP LOADER VECTOR
144
145
146
147
148
149
150
151
152
153
154
155
0000
006C
006C 1777
0072
0072
0074
0074
0075
0076
0077
0078
DATA
0000
CODE
SEGMENT AT 40H
RESET_FLAG
DISK STATUS
HF NOM
CONTROL BYTE
PORT OFF
oATAENOS
ORG
OW
ORG
OW
ORG
,
,
T I MER LOW WORD
072H
1234H
[F KEYBOARD RESET UNDERWAY
074H
FIXED DISK STATUS BYTE
COUNT OF FIXED DISK DRIVES
CONTROL BYTE DR I VE OPT IONS
PORT OFFSET
DB
DB
DB
DB
156
157
158
159
160
161
162
163
164
165
166
167
168
;
HARDWARE SPECIFIC VALUES
1
I {O PORT
HF PORT+O
READ DATA (FROM CONTROLLER TO CPUI
HF-PORT + 1
READ CONTROLLER HARDWARE STATUS
(CONTROLLER TO CPU I
HF _PORT+2
READ CONFIGURATION SWITCHES
HF PORT + 3 - NOT USED
> WHEN WR I TTEN TO:
HF PORT+ 0
WR I TE OAT A I FROM CPU TO CONTROLLER I
HF-PORT+ I
CONTROLLER RESET
HF-PORT+2
GENERATE CONTROLLER SELECT PULSE
HF-PORT+3
WR I TE PATTERN TO DMA AND INTERRUPT
MASK REG! STER
170
171
172
173
174
175
176
177
178
CMD BLOCK
HF PORT
INTAOO
INTAO I
EOI
R I 8USY
R I-BUS
Rl-IOMOoE
R1::::REQ
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
8YTE PTR [BP1-B
0320H
020H
021 H
020H
00001000B
OOOOOIOOB
000000 1 DB
0000000 I B
CMO BLOCK HEAD
01 SK PORT
8259 PORT
8259 PORT
END OF I NTERRUPT COMMAND
DISK PORT 1 BUSY BIT
COMMAND/DATA BIT
MODE BIT
REQUEST B[T
0047
004B
0000
0082
DMA READ
DMA-WR [TE
DMA_H I GH
EOU
EQU
EQU
EOU
01000111B
01001011B
OOOH
OB2H
1047HI
CHANNEL 3 (04BH)
OMA ADDRESS
PORT FOR HIGH 4 BITS OF OMA
0000
0001
0003
0004
0005
0006
0007
0008
OOOA
OOOB
OOOC
0000
OOOE
OOOF
OOEO
00E3
00E4
00E5
00E6
TST ROY CMD
RECAL CMD
SENSE-CMD
FMToRV CMD
CHK TRK CMD
FMTTRK CMD
FMTBAO-CMD
READ CMD
WRITE CMo
SEEK CMD
I N I T-ORV CMD
RD ECC CMO
RD-BUFF CMD
WR-BUFF-CMO
RAM O[AG CMD
CHK-DRV CMD
CNTLR DIAG CMO
RD LONG CMD
WR:::LONG:::CMD
EQU
EQU
EQU
EOU
EOU
EQU
EQU
EQU
EQU
EQU
EOU
EOU
EQU
EQU
EOU
EQU
EQU
EOU
EQU
000000008
0000000IB
00000011 B
00000 I OOB
000001018
000001108
OOOOOIIIB
0000 I 0008
000010108
OOOOIOIIB
OOOOIIOOB
000011018
00001110B
000011118
1 I 100000B
11100011 B
I I 1001 OOB
I I 100101 B
I I 10011 OB
CNTLR READY { OOHI
RECAL (OIHI
SENSE 103H)
DRIVE (04Hl
T CHK ( 05H)
TRACK 106H)
107H)
BAD
READ
108H)
WRITE (OAHI
(08H)
SEEK
INIT
(OCHI
8URST (DOH)
BUFFR (OEHI
BUFFR (OFH)
RAM
IEOHI
ORV
IE3HI
CNTLR {E4HI
RLONG {E5HI
WLONG (E6HI
OOOB
0002
MAX FILE
S_MAX FILE
EQU
EQU
179
0320
180
0020
181
0021
182
0020
183
0008
184
0004
185
0002
1860001
213
214
CONTROLLER
> WHEN READ FROM:
169
187
188
189
190
191
192
193
194
195
196
197
198
199
200
20 I
202
203
204
205
206
207
208
209
210
211
212
SEGMENT
- --- ---- --- - - - - - -------- - - - - -----
March 17, 1986
OMA
20MB Fixed Disk Drive Adapter BIOS
25
IBM Personal Computer MACRO Assembler
0lSK2 ---- 10/Z8/85
FIXED O[SK 8[OS
215
216
217
218
219
220
221
222
223
224
225
225
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
240
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
252
263
254
265
266
267
268
269
270
271
272
273
274
275
216
277
278
279
280
281
282
283
284
285
285
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
1-3
Version 2.00
10-28-85
PAGE
ASSUME
CS:CODE,OS:ABSO
0000
ORG
OH
0000 55
0001 AA
DB
DB
DB
055H
OAAH
I
GENER [C B I
080
;
4K MODULE
OOOZ 08
;
;
;
;
as
HEADER
--- - -------- - - - ----- - - - - --- - - - ----- ---- ----- -- - --FIXED DISK
;
I/O SETUP
ESTABl [SH TRANSFER VECTORS FOR THE F I XED 0 I SK
PERFORM POWER ON 0 I AGNOSTI CS
SHOULD AN ERROR OCCUR A "170 I" MESSAGE IS D I SPLA YEO
;
;
0003
01 SK SETUP
JMP
0003 E8 35
0005 35 39 58 37 32 39
DB
31 20 Z8 43 29 20
43 4F 50 59 52 49
47 48 54 20 49 42
40 20 20 43 4F 52
50 2E
0025 2C 31 39 38 32 ZO
DB
2C 31 39 38 35 2E
0031 20 31 30 ZF 32 38
DB
2F 38 35
D03A
L3 :
003A 28 CO
SUB
003C 8E 08
MOV
003E FA
CLI
003F A I 004C R
MOV
MOV
0042 A3 0100 R
0045 A I 004E R
MOV
MOV
0048 A3 0102 R
MOV
0048 C7 06 004C R 0251 R
MDV
0051 8C DE 004E R
MDV
0055 B8 0755 R
MOV
0058 A3 0034 R
0058 8C OE 0036 R
MOV
005F C7 06 0064 R 0192 R
MOV
0065 8C DE 0066 R
MOV
0069 C7 06 0104 R 03FF R
MOV
006F 8C DE 0106 R
MDV
0073 F8
STI
FROC
FAR
SHORT
L3
'59X7291 IC)
COPYRIGHT
IBM
CORP.'
COPYR I GHT NOT I CE
',1982,1985,'
,
10/28/85'
RELEASE MARKER
AX ,AX
OS,AX
ADDRESS LOW RAM
AX, WORD PTR ORG VECTOR
WORD PTR 01 SK VECTOR,AX
AX,WORD PTR ORG VECTOR+2
WORD PTR DISK VECTOR+2,AX
WORD PTR ORG VECTOR, OFFSET 0 I SK 10
WORD PTR ORG-VECTOR+2,CS
AX, OFFSET Hi) I NT
WORD PTR HOI SI< INT ,AX
WORD FTR HDISK-INT+2,CS
WORD FTR SOOT VEC,OFFSET BOOT STRAP
WORD PTR BOOT-VEC+2,CS
WORD PTR HF TeL VEC, OFFSET FO TBL
WORD PTR HF=:TBL=:VEC+2,CS
-
LOAD 0 I SKETTE [P
STORE AT I NT 40H
LOAD D [SKETTE CS
STORE AT INT 40H
F I XED 0 [SK HANDLER
AT [NT 13H
F I XED 0 I SK INTERRUPT
HANDLER AT I NT ODH
BOOTSTRAP ROUT[NE AT
[NT 19H
PARAMETER TABLE AT
[NT 41H
ASSUME
0074
0077
0079
007E
0083
0088
008B
0088
008E
0090
0092
0095
0095
0098
0098
009E
OOAO
00A2
00A5
00A5
00A8
OOAA
OOAC
OOAF
OOAF
00B5
00B8
OOBO
00C3
00C3
00C4
ODC6
00C8
OOCA
00C8
00C8
OOCE
0000
00D3
0005
0007
0007
OODA
0000
OOOF
OOEI
OOEI
00E4
OOE6
88
8E
C6
C6
C6
B9
---- R
08
06 0074 R 00
06 0075 R 00
06 0077 R 00
0025
E8
73
E2
E9
0177 R
05
F9
0154 R
89
8A
B8
CO
73
E9
000 I
MOV
MOV
MOV
MOV
MOV
MOV
AX,oATA
OS,AX
DISK STATUS,O
HF NUM,O
PORT OFF, 0
CX,25H
ESTA8L I SH SEGMENT
RESET THE STATUS INDICATOR
ZERO COUNT OF DR I YES
ZERO CARD OFFSET
RETRY COUNT
L4:
CALL
JNC
LOOP
HO RESET 1
L 7-
RESET CONTROLLER
L4
ERROR_EX
TRY RESET AGA I N
JMP
MOV
MOV
MOV
CX,l
DX,80H
AX,I200H
L 7:
0080
1200
13
03
0154 R
INT
JNC
JMP
CONTROLLER D I AGNOST I CS
CHECK THE I NTERNAL RAM
BUFFERS
I3H
P7
ERROR_EX
P7 :
88 1400
CO 13
73 03
E9 0154 R
MOV
AX,I400H
CONTROLLER D I AGNOST I CS
I NTERNAL CHECKSUM AND
ECC CIRCUITRY TEST.
INT
JNC
I3H
P9
JMP
ERROR_EX
MOV
CMP
TIMER LOW,O
RESET-FLAG, 1234H
JNE
P8
TIMER_LOW,410D
P9:
C7
81
75
C7
06 006C R 0000
3E 0072 R 1234
06
06 006C R 019A
MDV
ZERO TIMER
KEYBOARD RESET
SKIP WAIT ON RESET
P8:
CLI
FA
E4 21
24 FE
E6 21
FB
IN
ANO
OUT
ST I
AL,INTAOI
AL,OFEH
INTA01,AL
CALL
JC
HD RESET
MOV
AX,IOOOH
INT
JNC
I3H
P2
D I SABLE INTERRUPTS
TIMER
ENABLE T [MER
START TIMER
I NTERRUPTS ON
P4:
E8 0177 R·
72 07
88 1000
CD 13
73 OA
p(5
-
1
RESET CONTROLLER
TEST TO SEE
[S READY
IF THE DRIVE
PIO:
AI
30
72
E8
006C R
OIBE
EC
73
MDV
CMP
JB
JMP
AX, Tl MER LOW
AX,446D -
25
SECONDS
P4
SHORT ERROR_EX
P2:
88 1100
CO 13
72 6C
MDV
AX,IIOOH
INT
JC
ERROR_EX
00E8 88 0900
O{)EB CD 13
ODED 72 65
MOV
AX,0900H
INT
JC
ERROR_EX
OOEF
00F2
00F4
00F6
00F9
00,F8
MOV
MDV
AX ,OC800H
ES,AX
88
8E
2B
88
CD
72
C800
CO
08
OFOO
13
57
RECAL 18RATE THE OR I YE 0
I3H
I3H
SUB
BX,ex
MDV
AX,OFOOH
INT
JC
ERROR_EX
SET DR I VE PARAMETERS
FOR DRIVE 0
DNA TO BUFFER
SET SEGMENT
WR [TE SECTOR BUFFER
I3H
323
324
325
326
327
328
26
OOFO FE 06 0075 R
0101 BA 0213
0104 80 00
0106 EE
Ol078A0321
INC
MDV
MOV
OUT
MDV
HF NUM
OX-;213H
Al,O
OX,AL
DX,321H
20MB Fixed Disk Drive Adapter BIOS
DR I VE ZERO RESPONDED
EXPANS [ON BOX
TURN BOX OFF
TEST IF CONTROLLER
March 17,1986
IBM Persona I Computer MACRO Assemb I er
DISK2 ---- 10/28/85
FIXED DISK BIOS
329
OIOA EC
330
OIOB 24 OF
331
0100 3C OF
332
OIOF 74 06
333
0111 C7 06 006C R 0lA4
334
0I I7
335
0117 BA 0213
336011ABOFF
337
Olle EE
338
OlIO 69 0001
339
0120 BA 0081
340
0123
341
0123 2B CO
342
0125 CD 13
343
0127 72 42
344
0129 B8 I 100
345
012C CD 13
346
012E 73 OA
347
0130 AI 006C R
348
013330 OIBE
349
0136 72 EB
350
0138 EB 31
351
013A
352
013A B8 0900
353
0130 CO 13
354
013F 72 2A
355
0141 FE 06 0075 R
356
0145 81 FA 0081
357
0149 73 20
358
014B 42
359
014C EB 05
ion
1-'
2.00
10-28-85
IN
AND
CMP
JE
MOV
AL,DX
AL, OFH
AL, OFH
BOX ON
TlMER_LOW,420D
MOV
MOV
OUT
MOV
MOV
DX,213H
AL, QFFH
aX,AL
CX, I
DX,08IH
EXPANS [ON BOX
SUB
INT
JC
MOV
tNT
JNC
MOV
CMP
JB
JMP
AX,AX
13H
POD DONE
AX,OIIOOH
13H
P5
AX,TIMER LOW
AX,446D P3
SHORT POD_DONE
RESET THE CONTROLLER
MOV
INT
JC
INC
CMP
JAE
INC
JMP
AX,0900H
13H
POD DONE
HF NUM
DX-;-180H + S_MAX_FtLE
POD DONE
OX P3
INITIALIZE DRIVE CHARACTERISTICS
FOR DRIVE I
FI1
DB
FI7L
EOU
'1701' ,ODH,OAH
I-FI7
IS
IN THE SYSTEM UNIT
CONTROLLER
I SIN SYSTEM UN I T
TURN BOX ON
ATTEMPT NEXT DR I VES
P3:
RECALlBRATE THE DRIVE
I
25 SECONDS
P5:
I:
TALLY ANOTHER DRIVE
360
361
362
014E 31
0006
37
30 31
ODOA
363
36'
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
0154
0154
0157
0159
015C
015E
015E
0163
0165
0167
0168
016A
016B
016B
016C
0 I 6E
0170
0172
0173
0176
BO
2B
B9
B7
OOOF
F6
0006
00
ERROR EX:
MOV
403
404
405
406
407
408
BP,OFH
POD ERROR FLAG
SUB
S I, S I
MDV
MDV
CX,FI7L
BH,O
MESSAGE CHARACTER COUNT
PAGE ZERO
AL,CS:FI7(SI]
AH,I40
IOH
GET BYTE
VIDEO OUT
D I SPLA Y CHARACTER
NEXT CHAR
DO MORE
OUT_CH:
2E: 8A 84 014E R
B4 OE
CD 10
46
E2 F4
F9
FA
E4
OC
E6
FB
E8
CB
21
0I
21
MDV
MDV
INT
INC
LOOP
STC
POD DONE:
CLl
IN
OR
OUT
0177
0 I 77 51
0178 52
0179 B9
017C
017C E8
017F 42
0180 EE
0181 EB
0183 EB
0185 EB
0187 EC
018824
OIBA 74
DI8C E2
018E F9
018F
018F 5A
0190 59
0191 C3
0192
0 I 92
SI
OUT_CH
AL,INTAOI
AL,O IH
INTAOI,AL
STI
0232 R
CALL
NO INTERRUPTS
READ THE I NTERRUPT MASK
o I SABLE THE T I MER
ENABLE INTERRUPTS
o I SABLE THE CARD MASKS
OSBL
RET
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
POST MESSAGE
POD ERROR
0100
0760 R
00
00
00
3F
03
EE
March 17,1986
HD RESET I
PUSH
PUSH
MDV
L6:
CALL
INC
OUT
JMP
JMP
JMP
IN
AND
JZ
LOOP
C,
PROC
NEAR
OX
CX, 0 I OOH
PORT 0
OXDX,AL
1+2
1+2
$+2
AL,DX
AL,OOIIIIIIB
R3
L6
STC
SAVE REG I STER
RETRY COUNT
ADDRESS PORT I
RESET CARD
I/O DELAY AT LEAST +5us
ALLOW T I ME TO CLEAR THE
HARDWARE STATUS REGISTER
READ THE HARDWARE STATUS
MASK OFF UPPER 2 BITS AND CLEAR CY
EXIT IF REGISTER IS CLEARED WITH CY=O
TRY AGAIN
SET ERROR CONDITION CY=I
R3:
POP
POP
OX
CX
RESTORE REG 1 STER
RET
HD RESET I
DISK_SETUP
ENDP
ENDP
20MB Fixed Disk Drive Adapter BIOS
27
IBM PersonOiI Computer MACRO Assembler
DISK2 ---- 10/28/85
FIXED DISK 810S
409
410
411
412
413
414
415
416
411
418
419
420
421
422
423
424
42S
426
427
428
429
430
431
432
433
434
43S
436
437
438
439
440
441
442
443
444
44S
446
447
448
449
4S0
4S1
4S2
4S3
4S4
4SS
4S6
4S7
4S8
4S9
460
461
462
463
464
46S
466
467
468
469
470
471
472
473
474
47S
476
477
478
479
480
481
482
483
484
48S
486
487
488
489
490
491
492
493
494
49S
496
497
498
499
SOO
SOl
S02
S03
S04
SOS
S06
S07
S08
S09
SIO
SII
SI2
SI3
SI4
SIS
SI6
SI1
SI8
5>9
S20
S21
S22
28
PAGE
; ---
Version 2.00
I NT
I-S
10-28-85
19 H --- ------- --- ------- ------ -- ----------- ---------
INTERRUPT
19 800T STRAP LOADER
THE F I XED 0 I SK B I OS REPLACES THE INTERRUPT 19H BOOT
STRAP VECTOR WITH A PO I NTER TO TH I S BOOT ROUT I NE AND
RESETS THE DEFAULT DISK AND DISKETTE PARAMETER VECTORS
THE BOOT BLOCK TO BE READ IN WILL 8E ATTEMPTED FROM
CYL I NDER 0 SECTOR 1 OF THE DEV I CE.
THE BOOTSTRAP SEQUENCE IS:
ATTEMPT TO LOAD FROM THE DISKETTE INTO THE BOOT
LoCAT I ON (0000: 7COOH) WHERE CONTROL I S TRANSFERRED.
IF THE DISKETTE FAILS THE FIXED DISK IS TRIED FOR A
VALID BOOTSTRAP 8LOCK. A VALID 800T 8LoCK ON THE
055H OAAH
AS THE
F I XED 0 I SK CONS I STS OF THE 8YTES
LAST TWO 8YTES OF THE 8LOCK.
IF THE A80VE FAILS CONTROL IS PASSED TO RESIDENT BASIC
0192
0192
0194
0196
0198
2B CO
8E 08
B4 CO
CD 15
BOOT STRAP:
ASSUME
SUB
NOV
NOV
IN7
OS: ABSO, ES: ABSO
AX,AX
DS,AX
AH,OCOH
ISH
EST A8L I SH SEGMENT
READ CONF I GURAT I ON PARAMETERS
IF XT OR PC, I NTERRUPTS ARE 0 I SABLEO
AT THIS POINT.
RESET PARAMETER VECTORS
o 19A
CLI
FA
0198 CT 06 0104 R 03FF R
MoV
MOV
JNC
WORD PTR HF TBL VEC, OFFSET FD TBL
WORD PTR HF-TBL -VEC+2, CS
HO
; JMP I F I NT
0lA7 C7 06 0078 R 0227 R
OIAD 8C OE 001A R
OIBI
HO:
0181 FB
MOV
MOV
WORD PTR 0 I SKETTE PARM, OFFSET 0 I SKETTE TBL
WORD PTR DISKETTE:::PARM+2,CS
-
01 B2 2B 02
SUB
01AI 8C OE 0106 R
0lA5 73 OA
15 FUNCT I ON
IMPLEMENTED
STI
ATTEMPT BOOTSTRAP FROM 01 SKETTE
OX,DX
OR I VE ZERO
ESTABLISH ES:BX POINTER
0lB4 8E C2
0186 BB 7COO R
NOV
NOV
CLEAR
0189
o IBA
018C
018F
OICI
FC
33 CO
89 0100
88 FB
F3/ A8
0lC3
o IC6
o IC6
0lC7
0lC9
OICB
89 0004
51
2B CO
CD 13
72 08
OICD
0100
0103
0105
0106
B8 0201
B9 000 I
CO 13
59
73 09
NOV
NOV
INT
POP
JNC
ESTABLISH SEGMENT
SET BX TO 1COOH
ES ,OX
BX,OFFSET BooT_LOCN
BOOT_LOCN
CLO
XOR
NOV
NOV
REP
AX, AX
CX,256
DI,8X
STOSW
DIRECT I ON FORWARD
NOV
CX,4
PUSH
SUB
INT
JC
CX
AX,AX
13H
H2
SET RETRY COUNT
IPL SYSTEM
SAVE RETRY COUNT
RESET THE 0 I SKETTE
FILE 10 CALL
IF ERROR, TRY AGAIN
AX,020!H
CX,I
13H
CX
H3
READ I N THE SINGLE SECTOR
SECTOR I, TRACK 0
FILE 10 CALL
•
RECOVER RETRY COUNT
CARRY FLAG SET 8'1' UNSUCCESSFUL READ
CLEAR 256 WORDS
POINT TO BOOT LOCATION 8UFFER
ZERO THE BOOT LOCAT I ON BUFFER
HI:
H2:
0108 80 FC 80
OIOB 74 22
CNP
JZ
AH,80H
H6
IF TIME OUT, NO RETRY
TRY FIXED DISK
0100 E2 E7
OIOF EB IE
LOOP
JNP
HI
SHORT H6
DO I T FOR RETRY TIMES
UNABLE TO I PL FROM THE 0 I SKETTE
CMP
JB
BYTE PTR BOOT_LOCN,06H
HIO
CHECK FOR FIRST INSTRUCTION INVALID
IF 800T NOT VAllO, GO TO BASIC
OIEI 80 3E 7COO R 06
0lE6 72 30
H3:
INSURE DATA PATTERN FIRST 8 WORDS NOT ALL EQUAL
0lE8 8F 7COO R
0lE8 89 0008
OIEE AI 7COO R
OIFI
0lF4
01F6
0lF8
o IFA
OIFA
83
38
EI
74
C7 02
05
F9
28
H4:
NOV
NOV
NOV
01 ,OFFSET BOOT LoCN
CX,8
AX,WORD PTR BOOT_LOCN
; CHECK DATA PATTERN
; CHECK THE NEXT 8 WORDS
; LOAD THE FIRST WORD
AOO
CNP
LoOPZ
JZ
01,2
AX, (01
H4
HIO
; PO I NT TO NEXT WORD
; CHECK DATA PATTERN FOR A FILL PATTERN
JMP
800T _LOCN
J
;
BOOT NOT VALID,
GO TO BASIC
H5:
EA 7COO ---- R
ATTEMPT BOOTSTRAP FROM FIXED DISK
01 FF
01 FF
0201
0203
0206
0209
0209
020A
020C
020E
H6:
28 CO
CD 13
89 0003
8A 0080
SUB
INT
MOV
NOV
AX, AX
13H
CX,3
DX,ooaOH
PUSH
SUB
INT
JC
AX, AX
13H
H8
H7 :
51
2B CO
CD 13
72 08
RESET D (SKETTE
SET RETRY COUNT
FIXED DISK ZERO
IPL SYSTEM
SAVE RETRY COUNT
RESET THE F I XED 0 I SK
FILE 10 CALL
IF ERROR, TRY AGAIN
ES AND BX ALREADY ESTABLISHED
0210
0213
0216
0218
0219
B8
89
CD
59
12
0201
0001
13
H8:
08
NOV
NOV
INT
POP
JC
AX, 020 1H
ex,
I
13H
CX
H9
20MB Fixed Disk Drive Adapter BIOS
READ I N THE SINGLE SECTOR
SECTOR I, TRACK 0
FILE 10 CALL
RECOVER RETRY COUNT
March 17,1986
IBM Personal Comput.l!lr MACRO Assl!lmbll!lr
OlSK2 ---- 10/28/85 FIXED DISK BIOS
523
524
525
526
521
.2.
0218
021 E
0221
0223
0223
AI 70FE R
30 AA55
74 01
1-6
Vl!lrslon 2.00
10-28-85
MOV
CMP
.JZ
AX, WORD PTR BOOT LOCN+510D
AX, OAA5SH
; TEST FOR GENER I C BOOT BLOCK
H5
J GO TO 800T LOCATION
LOOP
H1
H9:
E2 E4
;
DO IT FOR RETRY TIMES
.28
;-----
UNABLE TO IPL FROM THE DISKETTE OR FIXED DISK
53.
531
532
0225
0225 CO 18
533
534
0227
INT
18H
RESIDENT BASIC
110011 I IB
2
25H
2
SRT=O, HD UNLOAD=OF - 1 ST SPEC BYTE
HD LOAD= I, MODE=DMA - 2ND SPEC BYTE
MOTOR TIMEOUT AFTER OPERATION
51 2 8YTES PER SECTOR
EOT (LAST SECTOR ON TRACK)
GAP LENGTH
DTL
GAP LENGTH FOR FORMAT
FILL BYTE FOR FORMAT
HEAD SETTLE T I ME (M I LL I SECONDS)
MOTOR START TIME (118 SECOND)
01 SKETTE_ TBL I
.35
536
537
538
539
540
541
542
543
544
545
546
0227
0228
0229
022A
0228
022C
0220
022E
022F
0230
0231
CF
02
25
02
08
2A
FF
50
F6
19
04
550
551
552
553
554
555
556
557
558
559
560
0232
0232
0234
0231
0238
0239
023C
0230
0240
0241
0244
2A
BA
FA
EE
83
EE
83
EE
83
EE
'61
562
563
564
565
566
567
568
569
0245
0247
0249
0248
0240
024F
0250
0251
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
.41
548
'4'
80
E6
E4
OC
E6
FB
C3
8
02AH
OFFH
050H
OF6H
2.
4
;-----
MAKE SURE THAT ALL HOUSEKEEPING IS DONE BEFORE EXIT
D58L
PROC
SUB
MDV
CO
0323
NEAR
AL,AL
DX,HF _PORT+3
eLi
C2 04
C2 04
C2 04
07
OA
21
20
21
DUT
ADD
DUT
ADD
DUT
ADD
DUT
DX,AL
DX,4
DX,AL
DX,4
aX,AL
OX,4
DX,AL
MDV
DUT
IN
AL,07H
DMA+IO,AL
AL,INTAOI
AL,020H
INTAOI,AL
DR
OUT
511
RET
OSBL
; RESET I NT IDMA MASK
LOAD FOR PORT ADDRESS :3
01 SA8LE INTERRUPTS
RESET I NT/DMA MASK CARD
a
RESET
INT/DMA MASK CARD
RESET
(NT/DMA MASK CARD 2
1
J RESET
INT /DMA MASK CARD :3
SET DMA MODE TO 0 I SA8LE
o
I SABLE I REQ 5
ENABLE INTERRUPTS
ENDP
51 •
• 11
512
.13
FIXED DISK BIOS ENTRY POINT
.14
51.
516
577
;
0251
- --- -- - - -- - ---- - - - - - ------- -- - --------------------------
DISK
-
518
579
580
581
582
583
0251
0254
0256
0258
0258
80 FA 80
73 05
CO 40
10 PROC
ASSUME
eMP
"AE
INT
CA 0002
FAR
OS :DATA,ES:NOTHING
DL,080H
HARD 01 SK
40H -
TEST FOR FIXED DISK DRIVE
YES, HANDLE HERE
DISKETTE HANDLER
J BACK TO CALLER
RET
.84
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
0258
0258
025C
025E
0260
0262
0264
0267
0269
0269
026C
026E
0271
0271
0272
0274
602
603
604
605
606
607
608
609
610
0277
0278
0279
027A
0278
02IC
0270
027E
0281
6.,
6"
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
FB
OA
75
CO
2A
80
77
HARD DISK:
STI
E4
09
40
E4
FA 81
EF
OR
"NZ
INT
SUB
e"p
A3:
80 FC 08
75 03
E9 0380 R
"A
e"p
J ENABLE
AH,AH
A3
40H
AH,AH
DL, (80H+S MAX FILE-I)
RET_2
-
INTERRUPTS
RESET NEC WHEN AH=O
DL IN LIMITS?
AH,8
A2
GET_PARM_N
GET PARAMETERS
"NZ
55
8B EC
83 EC 08
PUSH
NOV
SUB
BP
8P,SP
SP,8
53
51
52
IE
06
56
57
8E ---- R
8E DE
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
NOV
NOV
SAVE THE BASE POINTER
LOAD THE CMD BLOCK PO INTER
ALLOCATE SPACE FOR THE COMMAND BLOCK
ON THE STACK.
SAVE REGISTERS DURING OPERATION
51 ,DATA
DS,SI
0283 E8 0200 R
CALL
DISK_IO_CONT
0286
0287
028A
0280
028F
0290
0294
0295
0296
0297
PUSH
CALL
MOV
MOV
POP
MOV
POP
POP
POP
POP
POP
POP
POP
AX
A21
SO
E8
88
8E
58
8A
SF
5E
07
IF
029B SA
0299 59
029A 5B
0232 R
---- R
08
26 0074 R
""P
BX
I S A SPEC I AL CASE
ex
ox
DS
ES
51
DI
DSBL
AX,DATA
DS,AX
AX
AH,DISK STATUS
DI
-
J ESTABLISH DATA SEGMENT
PERFORM THE OPERATION
BE SURE 0 I SABLES OCCURRED
ESTA8L I SH SEGMENT
RESTORE THE REGI STERS
GET STATUS FROM OPERATION
51
ES
OS
OX
ex
BX
621
628
629
630
631
632
633
0298
029E
029F
02A2
02A3
02A6
83 C4 08
50
BO FC 01
FS
CA 0002
March 17, 1986
ADD
POP
eMP
eMe
RET
SP,8
BP
AH, I
ADJUST FOR THE COMMAND BLOCK.
RESTORE 8ASE POINTER
SET THE CARRY FLAG TO INDICATE
SUCCESS OR FAILURE
THROW AWAY SAVED FLAGS
DISK_IO ENDP
20MB Fixed Disk Drive Adapter BIOS
29
IBM Personal Computer MACRO Assembler
O[SK2 ---- 10/28/85
FIXED DISK 8[OS
.34
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
02A6
02A6 032E
02A8 0347
02AA 0350
02AC 0359
02AE 0362
0280 0369
0282 036F
0284 0375
0286 0326
0288 043F
028A 04F4
028C 0501
028E 0515
02CO 032E
02C2 0518
02C4 0527
02C6 0533
02C8 0539
02CA 053F
02CC 0545
02CE 0548
'" 002A
PAGE
MI
10-28-85
LA8EL
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
OW
EQU
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
MIL
1-7
Version 2.00
FUNCT [ON TRANSFER TA8LE
OOOH
001 H
002H
003H
004H
DOSH
D06H
D07H
OOSH
009H
OOAH
008H
DOCH
OODH
OOEH
OOFH
OIOH
OIIH
QI2H
o 13H
014H
WORD
DISK RESET
RETURN STATUS
DISK READ
DISK-WR[TE
01 SK-VERF
FMT TRK
FMT-BAD
FMT-DRV
8AD-COMMAND
[NIT DRV
RD LONG
WR-LONG
D 15K SEEK
DISK-RESET
RD 8UFF
WR-8UFF
TST ROY
HOISK RECAL
RAM OTAG
CHK-DRV
CNTLR DIAG
$-M1 -
.58
01 SK
10 CONT
-CMP
JE
659
660
661
•• 2
663
664
665
0200
0200 80 FC 01
0203 74 72
0205 80 EA 80
0208 80 FA 08
0208 73 49
e"p
667
0200 C6 06 0074 R 00
"OV
02E2
02E4
02E8
02E8
02EE
02FI
02F4
FE
C6
88
88
88
AO
88
C9
46 F8 00
4E FA
6E F8
46 FC
0076 R
46 FD
DEC
"OV
"OV
"OV
"OV
"OV
"OV
02F7
02F9
02FC
02FE
0300
0304
0306
0309
0308
0300
030F
8A
80
FE
DO
88
8A
80
81
02
OA
88
EA
CA
CA
E2
16
05
E2
05
E2
06
56
"OV
OR
DEC
5HL
"OV
"OV
...
-
5UB
JAE
•• 8
•• 9
.70
671
672
673
674
675
676
677
PROC
NEAR
AH,OIH
RETURN_STATUS
RETURN STATUS
CONVERT DR I VE NUM8ER TO 0 8ASED RANGE
LEGAL DR I VE TEST
DL ,080H
DL,MAX FILE
8AO_COMMAND
SET UP COMMAND 8LOCK
.78
.79
SECTORS 0-16 FOR CONTROLLER
SET TO ZERO THE OP CODE
SECTOR AND HIGH 2 6 [TS CYL I NOER
CYL I NDER LOW
[NTERLEAVE / 8LOCK COUNT
CONTROL 8YTE (STEP OPT [ON)
SET THE CONTROL F [ELD
CL
CMD 8LOCK+0, 0
CMD-BLOCK+2,CL
CMD-8LOCK+3,CH
CMD-BLOCK+4, AL
AL, CONTROL BYTE
CMD_8LOCK+5,AL
CALCULATE THE PORT OFFSET
.80
681
682
683
684
685
686
687
688
689
690
691
0I
0077 R
01
AND
F9
"OV
5HL
OR
"OV
SAVE DL
CH,DL
DL,1
OL
OL,I
PORT OFF ,Dl
OL,eH
DL,I
CL,5
OL,Cl
DL,DH
CMD_BLOCK+ I ,DL
GENERATE OFFSET
STORE OFFSET
RESTORE Dl
MAKE DR I VE 0 OR I
SHI FT COUNT
DRIVE NUMBER (0,1)
HEAD NUMBER
SET THE DR [VE AND HEAD
.92
693
694
695
696
697
b98
699
700
70 I
702
703
704
705
0312 66 C8
0314 8A CO
031632 ED
031801 EI
031A 88 FI
031C 83 F9 2A
031F 73 05
0321 2E: FF A4 02A6 R
0326
0326 C6 06 0074 R 01
0328 80 00
0320 C3
032E
70.
707
725
72b
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
e"p
JNB
J"P
8AD COMMAND:
MOV
"OV
RET
D[SK_IO_CONT
CALCULATE JUMP ADDRESS
CX,AX
CL,CH
GET I NTO LOW BYTE
CH,CH
ZERO HIGH BYTE
-2 FOR TA8lE LOOKUP
CX, I
PUT INTO S I FOR BRANCH
S I, CX
CX,MIL
TEST WITHIN RANGE
8AD COMMAND
; GO DO THE COMMAND
WORD PTR CS:[SI+OFFSET MIl
DISK STATUS,8AD CMD
AL,O-
SET 8AD COMMAND ERROR
;
EXIT
ENDP
; ---------- - ----------- - -- ----- ------ - -------
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
"OV
"OV
XOR
5AL
"OV
;
032E
032E
0331
0332
0333
0335
0337
0339
033A
033C
033E
0343
0344
0344
E8 0760 R
42
D[SK RESET
CALL
EE
E8
E8
E8
EC
24
74
C6
C3
RESET THE DISK SYSTEM
00
00
00
INC
ox
OUT
DX,AL
J"P
J"P
J"P
IN
3F
06
06 0074 R 05
PROC
PORT 0
AND
JZ
"OV
RET
(AH '" OOOH)
:
NEAR
RESET PORT
PORT I ADDRESS
RESET CARD
I/O DELAY AT LEAST +5us
ALLOW T I ME TO CLEAR THE
HARDWARE STATUS REG (STER
READ THE HARDWARE STATUS
MASK OFF UPPER 2 BITS AND CLEAR CY
EXIT IF REGISTER IS CLEARED WITH CY",O
SET THE ERROR COND I T I ON
EX[T
-
"2
'.2
'.2
AL,DX
AL,OOIIIIIIB
ORI
01 SK_ST ATUS, 8AD _RESET
DRI:
E9 043F R
SET THE DRIVE PARAMETERS
J"P
0347
DISK_RESET
0347
0347 AO 0074 R
034A C6 06 0074 R 00
034F C3
0350
RETURN STATUS
- MOV
ENDP
DISK STATUS ROUTINE
(AH '" OOIH)
; -------- -------------- ----------------- -- - ------- - ------
"OV
RET
RETURN_STATUS
PROC
NEAR
AL,DISK STATUS
01 SK_STATUS, 0
OBTA[N PREVIOUS STATUS
RESET STATUS
ENDP
; -- ---- ------------ - --------;
0350
0350 80 47
0352 C6 46 F8 OS
0356 E9 055E R
0359
OISK READ ROUTINE
DISK READ
MDV
"OV
J"P
DISK_READ
PROC
~~D D~~5~;~~. READ
DMA-OPN
ENDP
(AH
= 002H)
:
NEAR
I MODE 8YTE FOR DMA READ
CMD
-
747
30
20MB Fixed Disk Drive Adapter BIOS
March 17, 1986
IBM Personal Computer MACRO Assembler
0lSK2 ---- 10/28/85
FIXED DISK BIOS
746
749
750
751
752
753
754
755
756
757
756
759
760
761
762
763
764
765
766
767
766
769
770
771
772
773
774
775
776
777
776
779
760
761
782
763
764
765
766
767
786
769
790
791
792
793
794
795
796
797
796
799
600
60 I
602
603
604
605
606
607
606
609
610
61!
612
613
614
615
616
617
616
619
620
621
622
623
624
625
626
627
626
629
630
631
632
633
634
635
636
637
636
639
640
641
642
643
644
645
646
647
646
649
65D
651
652
653
654
655
656
657
656
659
;
;
0359
0359 80 48
035B C6 46 F8 OA
035F E9 055E R
0362
DISK WRITE ROUT[NE
MOV
JMP
DISK_WRITE
-
PROC
NEAR
AL,DMA WR I TE
CMD 8LOCK+O,WRITE CMD
DMA-OPN
ENOP
IAH
;
DISK VER[FY
DISK VERF
MOV
JMP
DISK_VERF
--- - - --- - - - - --
FMT TRK PROC
MOV
D36F
036F C6 46 F6 07
0373 E8 04
0375
FMT 8AD PROC
MOV
0375
0375 C6 46 F6 04
0379
FMT ORV PROC
MOV
FMT _DR V ENDP
0379
0379 60 66 FA CO
0370 E9 054F R
FMT CONTI
AND
0380
0380
0380 IE
0381 06
0382 53
GET PARM N
GET-PARMPUSH
PUSH
PUSH
JMP
:
IAH
=
004H)
PROC
NEAR
CMD 8LOCK+O,CHK TRK CMO
NOMA OPN
-ENDP- -
FORMATTING
0369
0369 C6 46 F6 06
0360 EB OA
D36F
= 003H)
MODE BYTE FOR DMA WR I TE
- ----- ---- - --- - - --------- - - --------- --
;
;
;
1-6
10-28-85
--- - - --- - - -- --- - - - - - - - - ---
DISK WR[TE
MOV
.
0362
0362 C6 46 F6 as
0366 E9 054F R
0369
VersIon 2.00
-- -- ----- - --- - - - - --- - - - -- -- - - - - - -- - - - -IAH = 005H 006H OOTHI :
NEAR
CMO 8LOCK+O,FMTTRK CMO
SHORT
FMT _CONT
-
;
FORMAT TRACK
= 005H I
(AH
FMT _ TRK ENOP
JMP
= 006Hl
NEAR
CMO 8LOCK+O,FMTBAD CMD
SHORT
FMT_CONT
-
FORMAT BAD TRACK
(AH
NEAR
CMD_BLOCK +0, FMTDRV _ CMD
FORMAT DR[VE
= 007H)
FMT _8AD ENDP
JMP
CMD 8LOCK+2,IIOOOOOOB
NDMA_OPN
i
ZERO OUT SECTOR FJELD
GET PARAMETERS
ASSUME
5U8
0383 2B CO
0385 8E 08
0387 C4 IE 0104 R
MOV
LES
ASSUME
----
0388
038E
0390
0393
0396
0398
0390
039F
03A2
03A4
03A6
03AA
03AC
03AF
03B I
03B4
03B5
03B6
0387
03BA
03BC
038E
03CO
03CO
03C2
03C4
03C6
03C8
03CA
03CO
88
8E
60
80
73
C6
8A
60
FE
DO
66
6A
60
6A
E6
42
42
EC
6D
75
DO
DO
0300
0302
0305
0301
0309
030B
0300
03EI
03E3
03E7
03E9
03E9
03EA
03E8
03EC
03EF
03EF
03F4
03F6
03F8
03FA
03FC
03FO
03FF
8A E8
25 0300
DI E6
DI E6
DC I!
8A C6
26: 6A 77 02
FE CE
6A 16 0015 R
28 CO
MOV
58
07
IF
CA 0002
POP
POP
POP
R
08
EA 60
FA 06
57
06 0074 R 00
EA
CA 01
CA
E2
16 0077 R
D5
E2 01
E2
0760 R
MOV
MOV
SU8
CMP
JAE
MOV
MOV
OR
DEC
SHL
MOV
MOV
AND
MOV
CALL
INC
INC
IN
FC 00
04
E6
E6
CMP
JNZ
SHR
SHR
LABEL
PROC
DS
ES
8X
AH
NEAR
FAR
OS:ABSO
AX,AX
OS, AX
8X,HF _TBL_VEC
OSIDATA
AX,DATA
OS,AX
DL,80H
DL,MAX FILE
G4
DISK STATUS,O
CH,Oe
OL, I
OL
DL,I
PORT OFF tOl
DL,cR
OL, 0000000 I B
AH,Dl
PORT 0
OX
OX
AL,DX
AH,D
GO
AL, I
AL,I
IAH
=
8)
:
GET DR I VE PARAMETERS
SAVE REGI STERS
ESTABLISH ADDRESSING
EST ABL I SH SEGMENT
TEST WITH I N RANGE
RESET THE STATUS
SAVE THE DRIVE
GENERATE OFFSET
STORE OFFSET
RESTORE OL
DRIVE 0 OR DRIVE
[NDICATOR
I
PORT_2 ADDRESS
READ SW I TCH SEll [NGS
DRIVE 0 OR 1
R [GHT JUST I FY THE SW ITCH BITS
GO:
24 03
81 04
02 EO
2A E4
03 08
26: 68 07
2D 0002
AND
MOV
SHL
SU8
ADO
MOV
SU8
AND
SHR
SHR
OR
MOV
MOV
DEC
MOV
SU8
RET
AL,OOOOOOl18
CL,4
Al,Cl
AH,AH
8X,AX
AX,ES: (BX]
AX ,2
CH,Al
AX,0300H
AX,I
AX,I
AL,OIIH
Cl-,AL
DH,ES: [8X] [2]
DH
DL,HF NUM
AX, AX-
ISOLATE THE TABLE BITS
T ABLE LENGTH IS 16 BYTES
ADJUST
MAX NUMBER OF CYLINDERS
ADJUST FOR O-N
AND RESERVE lAST TRACK
HIGH TWO 8[TS OF CYLINDER
SECTORS
HEADS
O-N RANGE
DR I VE COUNT
8X
ES
OS
2
RESTORE REGISTERS
DISK STATUS, (N[T FA(L
AH,INIT FAIL
AL,Al
OX,OX
CX,CX
OPERATION FAILED
EXIT
G4:
C6
84
2A
28
28
F9
E8
06 0014 R 07
07
CO
02
C9
MOV
MOV
EA
JMP
March 17, 1986
SU8
SUB
SU8
STC
G5
ENOP
SET ERROR FLAG
EXIT
20MB Fixed Disk Drive Adapter BIOS
31
IBM P.rsonal Computer MACRO Assembler
DISK2 ---- 10/28/85
FIXED DISK BIOS
..•••,
•• 0
1-'
Version 2.00
10-28-85
PAGE
•• 2
I NIT I AL I ZE DR I VE CHARACTER I ST I CS
•••
•••
•••
FIXED DISK PARAMETER TABLE
...•••
THE TABLE IS COMPOSED OF A BLOCK DEFINED AS:
•• 7
(I
(I
.70
(I
(I
II
II
.71
."
.,.
.7.
.72
.7..77
.7.
.7'
..,
•••
II
(1
(I
(I
(I
•• 0
•• 2
(I
•••
•••
•••
-
•• 7
..•••••••••,
WORD)
BYTE)
WORD)
WORD)
BYTE}
BYTE)
-
BYTE)
BYTE)
BYTE)
WORD)
BYTEl
BYTE)
-
TO DYNAMICALLY DEFINE A SET OF PARAMETERS
BUILD A TABLE OF VALUES AND PLACE THE
CORRESPONDING VECTOR INTO INTERRUPT 41 •
NOTE:
•• 0
...••••••
•• 2
MAXIMUM NUMBER OF CYLINDERS
MAXIMUM NUMBER OF HEADS
STARTING REDUCED WRITE CURRENT CYL
STARTING WRITE PRECOMPENSATION CYL
MAXIMUM ECC DATA BURST LENGTH
CONTROL BYTE IDRIVE STEP OPTION)
BIT
1 DISABLE DISK-ACCESS RETRIES
BIT
6 DISABLE ECC RETRIES
BITS 5-3 ZERO
BITS 2-0 DRIVE OPTION
STANDARD TIME OUT VALUE (SEE BELOW)
TIME OUT VALUE FOR FORMAT DRIVE
T I ME OUT VALUE FOR CHECK OR I VE
LAND I NG ZONE
SECTORS/TRACK
RESERVED FOR FUTURE USE
THE DEFAULT TABLE IS VECTORED
AN INTERRUPT 19H (BOOTSTRAP)
IN FOR
ON THE CARD SW ITCH SETT I NGS
DRP/E 0
•••
•••
DRIVE I
I
ON:
I
OFF
.'7
-1-
-2- I
I
-3-
I
-4-:
:
• 00
.0..0.
'0'
'0.
'0.
.0..,0
TRANSLATION TABLE
'01
'02
DRIVE 0
:
DRIVE I
1/2
'07
..
03FF
917
918
919
920
921
922
923
924
925
926
921
928
03FF
0401
0402
0404
0406
0401
0408
0409
0401.
040B
0400
040E
:
TABLE ENTRY
3/4
ON ON
ON OFF
OFF ON
OFF OFF
:
:
:
:
ON ON
ON OFF
OFF ON
OFF OFF
:
:
:
.11
912
.,,.
913
FD_TBL:
,-----
DRIVE TABLE 0
91.
.2.'.0
.31
932
933
934
935
936
931
938
939
940
941
942
943
•••
•••
•••
947
948
949
950
951
952
953
954
955
956
957
958
..•••,
0132
04
0132
0000
OB
05
10
CO
28
0132
II
00
;----040F
0411
0412
0414
0416
0411
0418
0419
041A
041B
0410
041E
0264
04
0264
0000
OB
05
28
EO
42
0297
11
00
041F
0421
0422
0424
0426
0427
0428
0429
042A
042B
0420
042E
0267
04
0267
01 2C
OB
05
28
EO
42
0267
It
00
32
042F 0132
0431 08
0432 0132
0434 0080
0436 OB
0431 05
0438 28
0439 EO
0431. 42
04380150
0430 II
043E 00
OBH
OOOOOlOIB
OIOH
OCOH
028H
03060
0170
0
MAX CYLINDERS
MAX HEADS
START REDUCED WRITE CURRENT CYL
START WRITE PRECOMPENSATION CYL
MAX ECC BURST DATA LENGTH
CONTROL BYTE
STANDARD TIME OUT
T I ME OUT FOR FORMAT DR I VE
TIME FOR CHECK DRIVE
LANDING ZONE
SECTORS/TRACK
RESERVED
06120
0.0
06120
0
OBH
0000010lB
028H
OEOH
042H
06630
0110
0
MAX CYL I NDERS
MAX HEADS
START REDUCED WRITE CURRENT CYL
START WRITE PRECOMPENSATION CYL
MAX ECC BURST DATA LENGTH
CONTROL BYTE
STANDARD TIME OUT
T I ME OUT FOR FORMAT DR I VE
T I ME FOR CHECK DR I VE
LAND I NG ZONE
SECTORS/TRACK
RESERVED
DRIVE TABLE 2
OW
DB
OW
OW
DB
DB
DB
DB
DB
OW
DB
DB
;-----
03060
0.0
03060
0
OR I VE TABLE I
OW
DB
OW
OW
DB
DB
DB
DB
DB
OW
DB
DB
;-----
•• 0
962
963
964
965
966
961
968
969
910
911
912
913
OW
DB
OW
OW
DB
DB
DB
DB
DB
OW
DB
DB
06150
0.0
06150
03000
OBH
OOOOOIOIB
028H
OEOH
042H
06150
0170
0
MAX CYLI NOERS
MAX HEADS
START REDUCED WRITE CURRENT CYL
START WRITE PRECOMPENSATION CYL
MAX ECC BURST DATA LENGTH
CONTROL BYTE
STANDARD TIME OUT
TIME OUT FOR FORMAT DRIVE
TIME FOR CHECK DRIVE
LAND I NG ZONE
SECTORS/TRACK
RESERVED
DRIVE TABLE 3
OW
DB
OW
OW
DB
DB
DB
DB
DB
OW
DB
DB
03060
080
03060
01280
OBH
OOOOOIOIB
028H
OEOH
042H
03360
0110
0
20MB Fixed Disk Drive Adapter BIOS
MAX CYLINDERS
MAX HEADS
START REDUCED WR I TE CURRENT CYL
START WRITE PRECOMPENSATION CYL
MAX ECC BURST DATA LENGTH
CONTROL BYTE
STANDARD TIME OUT
T I ME OUT FOR FORMAT DR I VE
T I ME FOR CHECK DR I VE
LAND I NG ZONE
SECTORS I TRACK
RESERVED
March 17, 1986
IBM Persona! Computer MACRO Assembler
0lSK2 ---- 10/28/85
FIXED DISK 810S
97.
;
;
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
99 I
992
993
994
995
(-10
10-28-85
Version 2.00
----- - -- ------ ----
- - --------- -------- ----------- -----
INITIALIZE DRIVE
043F
PROC
(AH
= 09H)
:
NEAR
DO OR I VE ZERO
043F
0443
0447
044A
C6
C6
E8
72
46 F8 OC
46 F9 00
0458 R
08
044C
0450
0454
0457
0457
0458
C6 46 F8 OC
C6 46 F9 20
E8 0458 R
"OV
"OV
CALL
JC
CMD BLOCK+O, INIT ORV CMD
CMD-BLDCK+I,O
INIT DRV R
INIT::::DRV::::OUT
SET FOR DR I VE 0
SEND THE PARAMETERS
ERROR?
DO DRIVE ONE
"OV
"OV
CALL
INIT DRV OUT;
-
C3
996
997
0458
998
0458 2A CO
999
045A E8 057C R
10000450 73 01
1001 045F C3
\ 002 0460
1003 0460 8C 09
1004
1005
1006 0462 28 CO
1007 0464 8E 08
10080466 C4 IE 0104 R
1009 046A 8E 09
1010
101 I
1012
1013
1014
1015
1016
1017 046C 42
1018 0460 42
1019 046E EC
1020 046F 8A 66 F9
1021 047280 E4 20
1022 0475 75 04
1023 0477 DO E8
1024 0479 00 E8
1025 0478
1026 0478 24 03
1027 0470 81 04
1028 047F 02 EO
10290481 2A E4
1030 0483 03 08
1031 04858409
1032
1033
1034
10350487 SF 0001
1036 048A E8 04E9 R
1037 0480 72 4C
1038
1039 048F 8F 0000
1040 0492 E8 04E9 R
1041 0495 72 44
1042
1043 0497 8F 0002
1044 049A E8 04E9 R
1045 0490 72 3C
1046
1047 049F 8F 0004
1048 04A2 E8 04E9 R
1049 04A5 72 34
t 050
1051 04A7 8F 0003
1052 04AA E8 04E9 R
1053 04AD 72 2C
1054
1055 04AF BF 0006
1056 04B2 E8 04E9 R
1057 0485 72 24
\ 058
1059 04B7 SF 0005
1060 048A E8 04E9 R
1061 048072 IC
1062
1063 04BF 6F 0007
1064 04C2 E8 04E9 R
1065 04C5 72 14
1066
1067 04C7 BF 0008
1068 04CA 26: 8A 01
1069 04CD A2 0076 R
1070
1071 040026 C9
1072 0402 B4 OF
10730404
1074 0404 E8 0680 R
1075 0407 73 09
1076 0409 E2 F9
1077 0408
1078 0408 C6 06 0074 R 07
1079 04EO F9
1080 04E I C3
1081 04E2
1082 04E2 4A
1083 04E3 EC
1084 04E4 24 02
1085 04E6 75 F3
1086 04E8 C3
1087 04E9
March 17, 1986
CMD 8LOCK+O,INIT DRV CMD
CMD-BLOCK+l,OOtOOOOOB
INIT_DRV_R
RET
SET TO DRIVE I
SEND THE PARAMETERS
EXIT
lNIT_ORV
INIT DRV R
SUB
CALL
JNC
PROC
NEAR
AL,AL
COMMAND
BI
I SSUE THE COMMAND
OX = PORT 0 AFTER CALL
"OV
CX,DS
SAVE SEGMENT
ASSUME
SUB
"OV
LES
"OV
DS:ABSO
AX ,AX
DS,AX
8X ,HF TBL VEC
DS,CX-
ESTA8L I SH SEGMENT
LOAD THE TABLE VECTOR
RESTORE SEGMENT
ASSUME
DS:DATA
RET
61 :
. - - - - ------ - -- - - ---- - - - - ---- ----;
DETERMINE PARAMETER TABLE OFFSET
US I NG CONTROLLER PORT TWO AND
DRIVE NUMBER SPECIFIER (0-1)
INC
INC
IN
"OV
ANO
JNZ
SHR
SHR
OX
AL,DX
AH ,CMD_BLOCK+ I
AH,OOIOOOOOB
B2
AL, I
AL, I
ANO
"OV
SHL
SUB
AOO
"OV
AL,Ol18
CL,4
AL,CL
AH,AH
8X ,AX
AH,OOOOl0018
ox
ADDRESS PORT 2
READ THE SW ITCH SETT I NGS
DRIVE 0 OR
I
ADJUST
B2:
ISOLATE
ADJUST
SET MASK FOR DATA MODE CPU TO CARD
SEND DRIVE PARAMETERS MOST SIGNIFICANT BYTE FIRST
"OV
CALL
JC
DI, I
INIT DRV S
83
-
SEND MS8 OF MAX CYLINDER
"DV
PI,O
INIT DRV S
83
-
SEND LS8 OF MAX CYL I NDER
01,2
INIT DRV S
83
-
SEND THE MAX I MUM HEADS
CALL
JC
"OV
CALL
JC
DI,4
INIT DRV S
83
-
SEND MS8 OF REDUCE WR I TE CURRENT
CYL I NDER
"OV
CALL
JC
o [,3
SEND LSB OF REDUCE WRITE CURRENT
CYLINDER
CALL
JC
"DV
INIT DRV S
83
-
o [,6
SEND MSB OF WR I TE PRECOMP CYL I NDER
"OV
CALL
JC
INIT DRV S
83
-
"OV
CALL
JC
DI,5
INIT DRV S
B3
-
"OV
CALL
JC
01,7
[NIT DRV S
83
-
SEND ECC BURST LENGTH
"OV
"OV
"OV
01,8
AL, ES: [8X+D I]
CONTROL_ 8YTE, AL
LOAD THE CONTROL BYTE AND PLACE
MEMORY AT 40:76H
SUB
"DV
IN
CX,CX
AH,OOOOl1118
85:
CALL
JNC
LOOP
HD WA IT
B6-
B5
GO WA I T FOR THE STATE TO HAPPEN
JMP TO READ THE STATUS 8YTE
TRY AGAIN
83:
"OV
STC
DISK STATUS,INIT_FAIL
OPERATION FAILED
SET THE ERROR eOND I T I ON
DX
ADDRESS PORT 0
READ STATUS BYTE OF THE OPERATION
MASK ERROR 81T
ERROR 81T SET?
RET
B6:
OEC
IN
ANO
JNZ
AL,DX
AL,2
83
RET
INIT_DRV_R
ENDP
20MB Fixed Disk Drive Adapter BIOS
33
IBM Personal Computer MACRO Assembler
DISK2 ---- 10/28/85 FIXED DISK BIOS
1088
1089
\ 090
\09\ 04E9
1092 04E9
1093 04EC
1094 04EE
1095 04EF
10<;16 04F2
1097 04F3
1098 04F3
1099 04F4
1100
1101
I 102
1 103
I 104
1I0504F4
1106 04F4
1101 04F7
1108 04F9
I 109 04FO
I I \ 0 04FF
I I I I 050 I
II \2
1113
1114
1115
1116
1111 050 I
1118 0501
1 I 19 0504
1120 0506
1 121 05011.
I 122 050C
1123 050E
1124
1125 050E
1126 050E
11210511
1128 0513
1129 0514
11300515
34
\-11
10-28-85
SEND THE BYTE OUT TO THE CONTROLLER
E8 0680 R
12 05
411.
26:
EE
INIT DRV S
CALL
JC
DEC
MOV
OUT
PROC
NEAR
HD WA I T
DX
GO WA I T FOR REQUEST
AFTER CALL OX = PORT 1
ADDRESS PORT 0
AL,ES: [BX+Ol ]
aX,AL
WRITE THE OATil. TO THE CARD
D'-
01 :
RET
lNIT_DRV_S
C3
ENDP
READ LONG
RD_LONG
E8
12
C6
BO
EB
050E R
SF
46 F8 E5
47
50
CALL
JC
MDV
MDV
JMP
,----
PROC
NEAR
CHK LONG
(AH
;
E8
12
C6
80
E8
050E R
52
46 F8 E6
4B
50
CALL
JC
MOV
MDV
JMP
WR_LONG
811. 46 FC
3C 80
F5
C3
CHK LONG
MOV
CMP
CMC
CHECK LIM I TS
PROC
NEAR
CHK LONG
(AH
;
:
CHECK LIM I TS
GS -
PROC
NEAR
AL,CMD BLOCK+4
AL,080H
LOAD THE NUMBER OF SECTORS
COMPARE WITH LIMITS
SET THE COND I T I ON
ENDP
DISK SEEK
MOV
JMP
01 SK_SEEK
RD BUFF PROC
MOV
MDV
MDV
JMP
IAH
= OCH)
:
(AH
= OEHI
:
PROC
NEAR
CMD BLOCK+O, SEEK CMD
SHORT
NOMA OPNENDP
-
READ SECTOR BUFFER
46 F8 OE
46 FC 01
41
31
OBHI
CMD BLOCK + 0, WR LONG CMD
AL,DMA WRITE
SHORT - OMA OPN
ENOP
-
SEEK
C6
C6
BO
EB
=
RET
CHK_LONG
C6 46 F8 OB
E8 34
:
CMD BLOCK+O,RD LONG CMD
AL,DMA READ
SHORT - DMA OPN
ENDP
-
WR ITE LONG
WR_LONG
= OAHI
GS -
;
::.~~
1133
1134
1135
1136 0515
1131 0515
11380519
11390518
1140
1141
1142
1143
1144
1145 051B
1146 0518
1141 051F
1148 0523
1149 0525
I 150 0527
1151
1152
1153
1154
1155
1156 0521
11510521
1158 052B
1159 052F
1160 0531
11610533
1162
1163
1164
1165
1166
1 167 0533
1168 0533
1169 0537
1110 0539
1111
1112
1113
1114
1175
11760539
1111 0539
11180530
1119053F
Vers,on 2.00
NEAR
CMO BLOCK+O,RD BUFF CMD
CMD-BLOCK+4,1 AL,OMA READ
SHORT - DMA_OPN
ONLY ONE BLOCK
RD_BUFF ENDP
,-----
WR I TE SECTOR 8UFFER
(AH
;
C6
C6
BO
EB
46 F8 OF
46 Fe 01
4B
28
WR BUFF PROC
MOV
MDV
MOV
JMP
NEAR
CMO BLOCK + 0 • WR BUFF CMD
CMD-BLOCK+4, 1 AL,OMA WRITE
SHORT - OMA _ OPN
= OFHI
ONLY ONE BLOCK
WR _BUFF ENDP
._------------------------------------------------------;
C6 46 F8 00
EB 16
TEST DISK READY
TST ROY PROC
MOV
JMP
(AH
=
OIOHI
:
(AH
= 011HI
:
NEAR
CMD 8LOCK+O, TST ROY CMD
SHORT
NDMA_OPN
-
TST_ROY ENDP
;
;
C6 46 F8 01
EB 10
--- ------ - ---------- ------------- ---RECAL I BRATE
HD I SK RECAL
MOV
JMP
HDISK_RECAL
PROC
NEAR
CMD BLOCK+O,RECAL CMD
SHORT
NOMA OPN ENDP
-
20MB Fixed Disk Drive Adapter BIOS
March 17, 1986
IBM Personal Computer MACRO Assembler
0lSK2 ---- 10/28/85
FIXED DISK 810S
180
181
182
183
184
185 053F
186 053F
181 0543
188 0545
189
190
1191
1192
1193
1194 0545
11950545
1196 0549
1191 0546
1198
1199
1200
1201
1202
1203 0548
1204 0548
1205 054F
1206
1201
1208
1209
1210
1211054F
1212 054F
1213 0551
1214 0554
1215 0556
1216 0558
12110558
1218 0550
1219 055E
1220 055E
1221 0561
1222 0563
1223 0565
1224 0568
1225 056A
1226 056C
1227 056E
1228 056E
1229 056F
1230 0511
1231 0513
1232 0515
1233 0518
1234 0518
1235 051B
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245 051C
1246 051C
1241 051F
1248 0580
12490581
1250 0582
1251 0583
1252 0585
1253 0586
1254 0581
1255 0588
1256 0588
1251 0589
1258 0586
1259 0580
1260 058F
1261 0591
1262 0596
1263 0597
1264 0598
1265 0598
1266 0598
1261 059C
1268 059E
1269 05AI
1210 05A2
1271 05A2
1212 05A5
1213 05A6
1274 05A1
1215 05A9
1216 05A8
1211 05AC
1218 05AD
[-12
10-28-85
VersIon 2.00
PAGE
;
- - ---------------- ----------- - ------- - --- - - --- ----------
;
C6 46 F8 EO
E8 OA
CONTROLLER RAM DIAGNOSTICS
RAM DIAG
MOV
IAH
= 012HI
:
(AH
= 013HI
:
PROC
NEAR
CMD BLOCK+O,RAM DIAG CMD
SHORT
NOMA OPN
ENOP
-
J"P
RAM_D I Ar::.
DR I VE 0 I AGNOSTI CS
; ------ -- ---- ------ - ---------------- --------- ------ - ----C6 46 F8 E3
E8 04
CHK DRV PROC
MOV
J"P
CHK_DRV ENOP
; --- - -------;
C6 46 F8 E4
BO 02
E8 057C R
72 22
EB 16
INTERNAL DIAGNOSTICS
{AH
= 014Hl
:
PROC
NEAR
CMD BLOCK + 0 ,CNTLR 0 I AG CMO
ENDP
--
CNTLR DI AG
MOV
CNTLR_D I AG
;
;
------ --------------------------- ----------
CONTROLLER
------- -- ----- ------- ------ - --------- --------- ----- - ---SUPPORT ROUT! NES
NOMA OPN:
MOV
CALL
AL,02H
COMMAND
JC
Gil
J"P
SHORT
I S SUE THE COMMAND
G3
G8:
C6 06 0074 R 09
C3
E8
72
BO
E8
12
BO
E6
06A5 R
F5
03
051C R
OE
03
OA
FA
E4
24
E6
E8
21
OF
21
0700 R
"OY
RET
OMA OPN:
CALL
JC
"OY
CALL
OMA SETUP
G8 AL,03H
COMMAND
SET UP FOR OMA OPERAT I ON
I SSUE THE COMMAND
Gil
JC
"OY
OUT
AL,03H
DMA+l0,AL
INITIALIZE THE DISK CHANNEL
AL,INTAOI
AL,ODFH
INTA01,AL
WAIT_INT
NO INTERRUPTS
READ THE MASK
ENABLE IRQ-5
WR I TE THE MASK OUT
PROCEDURE DOES ST I
G3:
CLI
IN
AND
OUT
CALL
Gil:
CALL
RET
E8 05AD R
C3
;
;
;
EC
24
3C
14
E2
C6
F9
C3
SEE I F THERE
EXIT
I S AN ERROR
--------- --------- ----------------- - ------------------COMMAND
INPUT TH I S ROUT I NE OUTPUTS THE COMMAND BLOCK
AL
E8 0160 R
42
42
EE
42
2B C9
EE
4A
4A
ERROR_CHK
= CONTROLLER
COMMAND PROC
CALL
INC
INC
OUT
INC
SUB
OUT
DEC
DEC
WAIT BUSY:
-
OF
00
09
F1
06 0014 R 80
IN
NEAR
PORT 0
OX
OX
DMA/INTERRUPT REGISTER MASK
GET THE BASE ADDRESS
-
CX,CX
DX,AL
ADDRESS PORT 2
I SSUE CONTROLLER SELECT PULSE
ADDRESS PORT 3
WA IT COUNT
WRITE DMA MASK REGISTER
OX
OX
ADDRESS PORT
DX,AL
OX
1
RET
READ THE HARDWARE STATUS
AL,DX
AL,OFH
AL,Rl BUSY OR RI BUS OR Rl REQ
; CHECK FOR BUSY,COMMAND
CI
-;
AND REQUEST BITS
WA I T BUSY
KEEP TRY I NG
01 SK::::STATUS, T I ME_OUT
SET THE ERROR CONo I T I ON
ERROR RETURN
"OY
DEC
"OY
SUB
SI,BP
BP,8
AND
C"P
JE
LOOP
"OY
STC
CI:
B9 0006
4A
88 F5
83 ED 08
FA
CX,6
OX
CLI
SET FOR 6 BYTES OF COMMAND
ADDRESS PORT 0
SAVE THE BASE POINTER
SET FIRST BYTE OF COMMAND BLOCK
NO I NTERRUPTS I N COMMAND SEQUENCE
CM3:
8A 46 00
EE
45
E2 F9
88 EE
F8
C3
March 17, 1986
"OY
OUT
INC
LOOP
"OY
STI
AL, {BP]
DX,AL
BP
C"3
BP,SI
GET A COMMAND BYTE
ALLOW AT LEAST 2us BETWEEN EACH BYTE
ON SEND I NG THE COMMAND SEQUENCE.
DO MORE
RESTORE THE BASE POINTER
I NTERRUPTS BACK ON
RET
COMMAND ENDP
20MB Fixed Disk Drive Adapter BIOS
35
IBM Person"l Computer MACRO Assembler
DISK2 ---- 10/28/85 FIXED DISK 8105
1219
1280
1281
1282
1283
1284
1285
1286
1281
1288
1289
1290
1291
1292
1293
1294
1295
1296
1291
1298
1299
1300
1301
1302
1303 05AD
1304 05AD AO 0074 R
1305 0580 OA CO
13060582 15 01
1301 0584 C3
1308
1309
t 31 0
1311
1312
1313
13140585
13150585 C6 46 F8 03
13160569 2A CO
13110568 E8 051C R
1318 058E 1226
1319
1320 05CO 28 FF
1321 05C2 89 0004
1322 05C5 84 DB
1323 05C7
1324 05C1 E8 0680 R
1325 05CA 72 lA
1326 05CC 4A
1327 05CD EC
1328 05CE 88 43 F8
1329 0501 47
t 330 0502 E2 F3
1331 0504 B4 OF
1332 0506 E8 0680 R
1333 0509 12 DB
1334 05DB 4A
1335 05DC EC
1336 0500 A8 02
1331 05DF 14 OF
1338
1339 05E 1 C6 06 0074 R FF
1340 05E6
1341 05E6 F9
1342 05E7 C3
1343 05E8
1344
1345 05E8 061E R
1346 05EA 062B R
1341 05EC 0660 R
1348 OSEE 061A R
1349
1350 05FO
1351 05FO 8A 5E F8
1352 05F3 8A C3
1353 05F5 24 OF
1354 05F7 80 E3 30
1355 05FA 2A FF
1356 05FC BI 03
1351 05FE 03 EB
13580600 2E: FF A1 05E8 R
1359
1360 0605
1361 0605 00 20 40 CC 80 00
1362
20
1363 060C 00 40
1364
0009
1365
1366 060E
1361 060E 04 10 02 00 04
1368061340 00 00 II DB
1369 = OOOA
1310
1371 0618
1372 0618 01 02 01
1313
0003
1374
1315 061B
1316 061B 20 20
1371
0003
PAGE
:
;
;
-- - -- -- -- - -- - -- -- -- ----- - - -- --- --- - -- -- - - -- - --- - ---- ---
;
;
;
;
;
;
;
SENSE STATUS BYTES
BYTE 0
BIT
1
B[T
6
BITS 5-4
BITS 3-0
BYTE 1
;
;
;
;
BITS 7-6
81T
5
B[TS 4-0
ZERO
DRIVE (0-1)
HEAD NUMBER
81TS 1-5
BITS 4-0
CYL! NDER HIGH
SECTOR NUMBER
B[TS 1-0
CYLI NOER LOW
BYTE 2
;
;
;
;
;
ADDRESS VALID, WHEN SET
SPARE, SET TO ZERO
ERROR TYPE
ERROR CODE
BYTE 3
;
i - ---- - - ---------- ----- ----------- ----------------------
OR
PROC
NEAR
AL,DISK STATUS
AL,AL
-
JNZ
021
ERROR CHK
MOV
; CHECK IF THERE WAS AN ERROR
; ANYTHING IN AL?
RET
.-------------- ---- -------------;
PERFORM SENSE STATUS
SENSE STATUS CAN BE ISSUED MULTIPLE
TIMES
G21 :
MDV
SUB
CALL
CMD BLOCK+O, SENSE CMO
AL,AL
COMMAND
JC
024
SUB
MDV
MDV
DI,OI
CX,4
AH,OOOOIOIIB
CALL
JC
DEC
HO WA I T
G24
OX
AL,DX
[OI+CMD BLDCK],AL
WRITE ZERO IN INT/OMA MASK
[SSUE SENSE STATUS COMMAND
CANNOT RECOVER-EX I T WITH COMMAND
ERROR
SET [NDEX PO I NTER TO ZERO
READ FOUR BYTES
SET MASK FOR DATA MODE CARD TO CPU
G22:
IN
MDV
INC
LOOP
MDV
CALL
JC
DEC
01
022
AH,OOOO! II IB
HD WAIT
G24
GO WAIT FOR DATA INPUT STATE
ADDRESS PORT 0
READ THE DATA BYTE
STORE AWAY SENSE BYTES
NEXT DATA LOCAT[ON
LOOP TILL ALL FOUR READ.
SET THE MASK FOR STATUS MODE
GO WAIT FOR STATUS STATE
TEST
JZ
OX
AL,OX
AL,2
STAT_ERR
ADDRESS PORT 0
READ THE STATUS BYTE
SENSE OPERATION FAIL?
GO GET THE ERROR.
MDV
DISK_STATUS. SENSE_FA I L
SET SENSE OPERAT[ON FAIL
IN
G24:
STC
RET
ERROR_CHK
T_O
OW
OW
OW
ow
STAT ERR:
MOV
MDV
AND
AND
SUB
MDV
SHR
JMP
ENDP
TYPE 0
TYPE-I
TYPE-2
TYPE::)
ERROR TYPE .JUMP T A8LE
BL,CMD BLOCK+O
AL,BL AL,OFH
BL,00110000B
BH,BH
GET ERROR BYTE
ISOLATE THE TYPE OF ERROR
Cl,3
BX, CL
; AD.JUST
WORD PTR CS:{8X + OFFSET T_O)
TYPEO TABLE
DB
LABEL
BYTE
0, BAD _ CNTLR ,BAD_SEEK, WR I TE_F AUL T , T [ME_OUT. 0 ,BAD_CNTLR
DB
TYPEO_LEN
o ,BAD SEEK
EQU S-TYPEO_TABLE
TYPE 1 TABLE
DB
DB
TYPE I_LEN
LABEL
BYTE
RECORD NOT FND. BAD ECC, BAD ADDR MARK. 0, RECORD NOT FNO
BAD SEEK ,0-;-0 ,DATA C:ORRECTED,BAO-TRACK
-EQUS-TYPEI_TABLE
-
=
TYPE2 TABLE
DB
TYPE2_LEN
LABEL
BYTE
BAD CMO ,BAD ADDR MARK ,BAD CMD
EQUS-TYPE2_TABLE
-
TYPE3 TABLE
DB
TYPE3_LEN
LABEL
=
=
36
1-13
10-28-85
Version 2.00
BYTE
~~~_CNTL~~ ~~~E~~~~~L~AD _ ECC
20MB Fixed Disk Drive Adapter BIOS
March 17,1986
IBM Personal Computer MACRO Assernbler
DISK2 ---- 10/28/85
FIXED DISK BIOS
1318
1319
1380
1381 ablE
1382 ablE
1383 Ob21
1384 0623
1385 0625
! 386 Ob21
1381 062A
1388
1389
t 390
1391 062B
1392 Ob2B
1393 Ob2E
1394 0630
1395 0632
139b Ob34
1391 Ob36
1398 0639
1399 063C
1400 Ob3F
140 I
1402
1403
1404 0641
1405 Ob45
1406 0641
1401 064A
1408 064C
1409 Ob4E
1410 0651
1411 0653
1412 Ob54
1413 0655
1414 0657
14150659
1416 065C
1417 Ob5£
1418 065F
14190660
1420 0662
1421 0664
1422 Ob69
1423 066A
1424 066A
1425 066C
1426
1427
1428
1429 0660
1430 0660
1431 Ob70
1432 0672
1433 0674
1434 0676
1435 0679
1436
1437
143B
1439 061A
1440 067A
1441 0670
1442 067F
1443 0681
1444 0683
1445 0686
1446
1447 0687
1448 Ob87
1449 068C
1450
1451
1452
1453
1454
1455 Ob80
1456 0680
1451 068E
1458 0690
1459 0690
1460 0693
1461 0694
1462 0695
1463 0697
1464 0699
\ 465 069B
1466 0690
1467 06A2
1468 06A3
1469 06A3
1470 06A4
1471 06A5
1-14
10-28-85
Version 2.00
PAGE
TYPE 0 ERROR
BB 0605 R
3C 09
13 62
2E: 01
A2 0014 R
C3
MOV
eMp
"AE
XLAT
MOV
eX,OFFSET TYPED TABLE
AL,TYPEO LEN
UNDEF ERR L
CS:TYPEO TABLE
01 SK_STATUS,AL
CHECK
I F ERROR
I S OEF I NED
T ABLE LOOKUP
SET ERROR CODE
RET
:------ TYPE
I ERROR
TYPE_l :
BB ObOE R
8B CB
3C OA
13 53
2E: 01
A2 0014 R
80 E 1 08
80 F9 OB
15 29
MOV
MOV
eMP
"AE
XLAT
MOV
AND
eMP
"NZ
BX,OFFSET TYPE I_TABLE
CX,AX
AL, TYPE 1 LEN
UNOEF ERR L
CS:TYPEI TABLE
DISK STATUS,AL
CL,OSH
CL ,08H
G30
CHECK
I F ERROR
IS OEF I NED
T ABLE LOOKUP
SET ERROR CODE
CORRECTED ECC
OBTAIN ECC ERROR BURST LENGTH
C6
2A
E8
12
B4
E8
12
4A
EC
8A
B4
E8
72
4A
£C
A8
14
C6
F9
46 F8 00
CO
051C R
IE
OB
06BO R
17
MOV
C8
OF
0680 R
OC
MOV
MOV
CALL
SUB
CALL
X
MOV
CALL
"e
DEC
IN
"e
DEC
IN
02
Ob
06 0074 R 20
TEST
"Z
MOV
~~~ A~LOCK + 0 ,RD _ ECC _ CMO
COMMAND
G30
AH,OOOOI01IB
HD WAI T
I SSUE THE COMMAND
SET MASK FOR DATA INPUT CARD TO CPU
GO WAIT FOR THE INPUT STATE
GiO
OX
AL,OX
CL,AL
AH,OOOOIIIIB
HD WAI T
ADDRESS PORT 0
READ THE LENGTH OF THE ERROR
CORRECTED AND SAVE IN CL
SET MASK FOR STATUS STATE
GO WAIT FOR STATUS STATE
G30
OX
AL.DX
AL,2
G30
01 SK_ST ATUS, BAD_CNTLR
ADDRESS PORT 0
READ THE STATUS BYTE
ERROR BIT SEn
STG
G30 :
8A Cl
C3
MOV
RET
AL,CL
TYPE 2 ERROR
BB 0618 R
3C 03
13 13
2£: 07
A2 0074 R
C3
MOV
eMp
"AE
XLAT
"OV
BX, OFFSET TYPE2 TABLE
AL. TYPE2 LEN
UNDEF ERR L
CS :TYPE2 TABLE
DISK_STATUS,AL
CHECK
I F ERROR
I S DEF I NED
TABLE LOOKUP
SET ERROR CODE
RET
TYPE 3 ERROR
BB 061B R
3C 03
13 06
2E: 07
A2 0074 R
C3
C6 Ob 0074 R BB
C3
MOV
eMp
"AE
XLAT
"OV
BX, OFFSET TYPE3 TABLE
AL, TYPE3 LEN
UNDEF ERR L
CS: TYPE3 TABLE
01 SK_STATUS,AL
CHECK
I F ERROR
I S OEF I NED
T ABLE LOOKUP
SET ERROR CODE
RET
UNDEF ERR L:
MOV
DISK_STATUS, UNDEF _ERR
RET
.- - - - - -- - - - - - - -- - - - - -- - - - - -- - - - - - - -; ON ENTRY AH CONTA I NS THE CONTROLLER BUS STATUS DECODE :
USED TO CHECK THE HARDWARE STATUS.
:
.; - MASK
- - - - - - - -- - - - - - - - -- - - - -- - - - -- - - - - -- - - - - - - - - -- -- - - - - - ---
-
-
-
HD_WAIT
51
2B C9
PUSH
SUB
E8
42
£C
24
3A
74
E2
C6
F9
CALL
0760 R
INC
IN
OF
C4
08
F3
06 0074 R 80
AND
eMp
"Z
LOOP
"OV
STe
L2:
59
C3
March 17, 1986
PROC
CX
CX, CX
NEAR
SAVE CX
SET THE LOOP COUNT
PORT 0
OX
AL,DX
AL,OOOOIIIIB
AL,AH
L2
LI
o t SK_ST ATUS. T I ME_OUT
PORT 1 ADDRESS
READ-THE HARDWARE STATUS
CLEAR UPPER NIBBLE OF HARDWARE STATUS
CHECK THE STATE WITH THE MASK
.)MP t F o. K Wt TH CARRY CLEARED
TRY AGAIN
ex
RESTORE CX
SET ERROR CONO I T I ON
20MB Fixed Disk Drive Adapter BIOS
37
IBM Personal Computer MACRO Assembler
DISK2 ---- 10128185
FIXED DISK BIDS
1472
1413
1474
1475
1476
1477
1478
1479
1480
148 I
1482
1483 06A5
1484 06A5 80
1485 06A9 72
1486
1487 06AB F9
1488 06AC C3
1489
1490 D6AD
1491 06AD FA
1492 D6AE E6
1493 06BO BI
1494 0682 E6
1495 0684 8C
1496 D6B6 D3
1497 06B8 8A
1498 068A 24
1499 D6BC 03
1500 D6BE 80
1501
1502 06CI 88
1503 06C3 E6
1504 06C5 8A
1505 06C7 E6
1506 06C9 8A
1507 06CS 24
1508 06CO E6
1509
1510
1511
1512 06CF 8A
t 513 0602 DO
1514 0604 32
1515060648
t 516
1517
1518
15190607 80
1520 06DB 74
Version 2.00
PAGE
; --------------
1-15
10-28-85
-----------------------------
DMA SETUP
THIS ROUTfNE SETS UP FOR DMA OPERATIONS.
INPUT
(ALl
MODE BYTE FOR THE DMA
(ES:BX)
ADDRESS TO READ/WRITE THE DATA
OUTPUT
;
(AX' DESTROYED
; ----------- - ------------------------------------------;
=
7E FC 81
02
DMA SETUP
CMP
JB
=
PROC
NEAR
CMO BLOCK +4,81 H
JI -
BLOCK COUNT OUT OF RANGE
SET THE ERROR COND I T I ON
STC
RET
,)1:
CLI
DC
04
08
CO
CO
E8
FO
C3
05 00
OUT
MOY
OUT
MOY
AOC
DMA+12,AL
CL,4
OMA+ I I,AL
AX,ES
AX,CL
CH,AL
AL,OFOH
AX,BX
CH,O
FO
06
C4
06
C5
OF
82
MDY
OUT
MOY
OUT
MOY
AND
OUT
S[ ,AX
DMA+6,AL
AL,AH
DMA+6,AL
AL,CH
AL,OFH
DMA_HIGH,AL
ROL
MOY
AND
ADD
NO MORE INTERRUPTS
SET THE FIRSTfLAST FIF
SH 1FT COUNT
OUTPUT THE MODE 8YTE
GET THE ES VALUE
ROTATE LEFT
GET HIGHEST NIBBLE OF ES TO CH
ZERO THE LOW NIBBLE FROM SEGMENT
TEST FOR CARRY FROM ADD I T I ON
CARRY MEANS HIGH 4 B[TS MUST BE [NC
SAVE START ADDRESS
OUTPUT LOW ADDRESS
OUTPUT HIGH ADDRESS
GET HIGH 4 BITS
OUTPUT THE HIGH 4 BITS TO PAGE REG
;------ DETERMINE COUNT
MOY
66 FC
E4
CO
SHL
XOR
DEC
AH,CMD BLOCK+4
AH, I
AL,AL
AX
HANDLE READ AND WRITE LONG
7E F8 E5
06
CMP
JE
RECOVER BLOCK COUNT
, MULTIPLY BY 512 BYTES PER SECTOR
; CLEAR LOW BYTE
AND DECREMENT VALUE BY ONE
(5160 BYTE BLOCKS)
CMD BLDCK+O,RD LONG CMD
ADD4
--
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
38
0600
06El
06E3
06E3
06E6
06E7
06E9
D6EC
D6ED
06EF
06FO
D6FI
06F2
06F2
06F4
OoF6
06F8
06FA
06FB
06FD
06FF
0700
80 7E F8 E6
75 OF
CMP
JNE
ADD4:
(512)
PLUS 4 BYTES ECC
AX,516D
BX
BH,8H
BL,CMD BLOCK+4
ONE BLOCK
PUSH
OX
MUL
POP
POP
BX
BLOCK COUNT TIMES 516
DEC
AX
ADJUST
C8
07
C4
07
MOY
OUT
MOY
OUT
CX,AX
OMA+7,AL
AL,AH
DMA+7,AL
SAVE COUNT VALUE
LOW BYTE OF COUNT
C6
Cl
MOY
88 0204
53
2A FF
8A 5E FC
52
F7 E3
5A
58
48
MOY
PUSH
SUB
MOY
-
OX
BX
,)20:
86
E6
8A
E6
F8
88
03
C3
ST I
ADO
RET
DMA_SETUP
AX,51
AX,CX
HIGH BYTE OF COUNT
INTERRUPT 5 BACK ON
RECOVER ADDRESS VALUE
ADD, TEST FOR 64K OVERFLOW
RETURN TO CALLER,
CY SET BY ABOVE I F ERROR
ENDP
20MB Fixed Disk Drive Adapter BIOS
March 17,1986
IBM Personal Computer MACRO Assembler
DISK2 ---- 10{28{85 FIXED DISK BIOS
1545
1546
1541
1548
1549
1550
155 I
1552
1553 0700
1554
1555 0700 FB
1556 0101 8C DB
1551 0103 2B CO
1558 0705 8E 08
1559 0701 C4 36 0104 R
1560
1561
1562 070B 8E DB
1563
1564
1565
1566 0700 2A FF
1561 010F 26: 8A 5C 09
1568 0113 8A 66 F8
1569 0716 80 FC 04
1510 0719 15 06
1511
1512 071B 26: 8A 5C OA
1513 071F EB 09
15740721 80 FC E3
1575 0724 75 04
1576
1577 0726 26: 8A 5C OB
1578 07211.
1579 072A F8
1580 072B B8 9000
1581 072E CO 15
1582 0730 FB
1583
1584 0131 2B C9
1585
1586
1587
1588 0733
1589 0733 E8 0160 R
1590 0736 42
1591 0131 EC
1592 0138 11.8 20
1593 07311. 15 Oil.
1594
1595 013C E2 F5
1596 013E 4B
1591 073F 75 F2
1598
1599 0741 C6 06 0074 R 80
1600 0746
1601 0746 411.
1602 0747 EC
1603 0748 24 02
1604 074A 08 06 0074 R
1605 074E 83 C2 03
1606 0151 32 CO
1607 0753 EE
1608 0754 C3
1609
1610 0755
1611
1612
1613
1614
1615
1616
1617
1618 0155
16190755 50
1620 0156 BO 01
1621 0158 E6 OA
1622 01511. FA
1623 075B E4 21
1624 0150 OC 20
1625 015F E6 21
1626 0761 BO 20
1627 0763 E6 20
1628 0165 FB
1629076688 9100
1630 0169 CO 15
1631 016B 58
1632 016C CF
16330160
1634
1635
1636
1631
1638
1639
1640
1641 0160
1642 0760 BA 0320
1643 0170 02 16 0011 R
1644 0174 C3
1645 0175
1646
1647 0775
1648 0175
1649
March 17, 1986
Vers'on 2.00
:
PAGE
-;~ ~ ~-~~~---
;
;
;
-
WAIT
- - - -- --
; --
---- -----------
THIS ROUTINE WAITS FOR THE FIXED DISK
CONTROLLER TO SIGNAL THAT AN INTERRUPT
HA S OCCURRED.
INT
-
1-16
10-28-85
PROC
NEAR
DS:ABSO
ASSUME
STI
MO'
SUB
MO'
LES
BX,DS
AX,AX
OS,AX
SI,HF_TBL_VEC
EST ABL I SH SEGMENT
LOAD THE TABLE VECTOR
ASSUME
MO'
OS: DATA, ES: NOTH I NG
DS,BX
RESTORE OS
TURN ON
SAVE OS
INTERRUPTS
SET TIMEOUT VALUES
W5:
W4:
SUB
MO'
MO'
eMP
JNZ
SH,BH
BL ,BYTE PTR ES: [S[] (9)
AH,CMD BLOCK+O
AH,FMTDRV_CMD
05
MO'
JMP
CMP
JNZ
BL,BYTE PTR ES:[S[)[OAH]
SHORT
AH,CHK_DRV_CMD
MO'
LOAD THE STANDARD T I ME OUT
LOAD THE FORMAT DR I VE
T[ME OUT VALUE
O.
O.
BL,BYTE PTR ES:[SI)[OBH)
eLC
MO'
INT
ST I
; LOAD THE CHECK DR I VE
CLEAR ~Y Tl ME OUT VALUE
AX,9000H
15H
DEV I CE WA I T
SUB
CX,CX
WA [T FOR
INTERRUPT
ENABLE [NTERRUPTS FOR PC AND
XT MACH I NES.
SET THE LOOP COUNT
1NTERRUPT
WI:
CALL
INC
IN
TEST
JNZ
PORT 0
AL,OX
AL,020H
02
PORT I ADDRESS
READ-THE HARDWARE STATUS
0[0 I NTERRUPT OCCUR
.JUMP [F YES
LOOP
DEC
JNZ
01
BX
01
OUTER LOOP
MOV
DISK STATUS,TIME_OUT
DEC
IN
AND
OR
ADO
XOR
OUT
RET
ox
ox
-
INNER LOOP
W2:
ADDRESS PORT 0
READ THE STATUS BYTE
ISOLATE THE ERROR B[T
SAVE I N THE STATUS
PORT 3 ADDRESS
AL,DX
AL,2
DISK STATUS,AL
DX,3AL,AL
OX,AL
ZERORESET
I NTERRUPT MASK
ENDP
;---
HD
INT
FIXED DISK
:
PRoe
PUSH
MOV
OUT
eLi
IN
OR
OUT
MOV
OUT
STI
MOV
INT
POP
IRET
ENDP
INTERRUPT ODH ROUTINE
IRQ-5
NEAR
AX
AL,07H
DMA+IO,AL
AL,INTAOI
AL,020H
INTAOI,AL
AL,EOI
[NTAOO,AL
AX,9100H
15H
AX
-~~~~~----------------
SAVE WORK REGISTER
SET OMA MODE TO 0 I SABLE
NO INTERRUPTS
LOAD THE I NTERRUPT ENABLE MASK
TURN OFF FIXED DISK IRQ-5
REPLACE THE MA SK
LOAD THE END OF INTERRUPT MASK
CLEAR THE ACT [VE I NTERRUPT LEVEL
I NTERRUPTS BACK ON
DEV ICE POST
INTERRUPT
RESTORE AX
- -------- ---------
GENERATE PROPER PORT VALUE
BASED ON THE PORT OFFSET
PORT_O
PORT_O
PROe
MOV
ADO
RET
ENOP
END ADDRESS
CODE
ENDS
END
NEAR
OX,HF PORT
OL,PORT_OFF
LABEL
BASE VALUE
ADD [N OFFSET VALUE
(00,04,08,OC)
BYTE
20MB Fixed Disk Drive Adapter BIOS
39
Notes:
4020MB Fixed Disk Drive Adapter BIOS
March 17, 1986
Index
~
addresses, port
fixed disk controller 1
fixed disk drive types 3
14
[!J
BIOS listings 23
block diagram 2
command summary 10
connectors 17
control byte 8
controller, fixed disk 1
interface 15
interface signals
AEN 15
AO-AI9 15
-DACK 3 16
DO-D7 15
DRQ 3 15
-lOR 15
-lOW 15
IRQ 5 15
RESET 15
[EJ
data register 7
description 1
logic diagrams
19
[!]
error tables
5
March 17, 1986
20MB Fixed Disk Drive Adapter
Index-l
port addresses 14
programming
considerations 3
programming summary
registers
1
14
sense bytes 4
specifications 17
status register 4
switch settings 3
TTL levels
Index-220MB Fixed Disk Drive Adapter
17
March 17, 1986
----- - -----
--- --- ------
--_.-
Personal Computer
Hardware Reference
Library
mM Asynchronous
Communications
Adapter
6361501
ii
Contents
Description .................................... 1
Programming Considerations ...................... 3
Modes Of Operation ......................... 3
Line-Control Register ........................ 5
Programmable Baud-Rate Generator ............ 7
Line Status Register (LSR) ................... 10
Interrupt Identification Register (IIR) .......... 12
Interrupt Enable Register .................... 14
Modem Control Register .................... 15
Modem Status Register ...................... 16
Receiver Buffer Register ..................... 18
Transmitter Holding Register ................. 19
Selecting the Interface Format and Adapter Address 20
Interrupts ................................ 21
Interface ..................................... 23
Voltage Interchange Information .............. 24
INS8250 Functional Pin Description ........... 25
Specifications ................................. 31
Logic Diagrams ................................ 33
Index ........................................ Index-l
iii
jv
Description
The Asynchronous Communications Adapter's system control
signals and voltage requirements are provided through a 2- by
31-position card-edge connector. Two jumper modules are
provided on the adapter. One jumper module selects either
RS-232C or current-loop operation. The other jumper module
selects one of two addresses for the adapter, so two adapters may
be used in one system. An additional jumper is required on
connector J13 if the adapter is to be installed in expansion slot 8
of an IBM Personal Computer XT or IBM Portable Personal
Computer (see "Selecting the Interface Format and Adapter
Address" in this section).
The adapter is fully programmable and supports asynchronous
communications only. It will add and remove start bits, stop bits,
and parity bits. A programmable baud-rate generator allows
operation from 50 baud to 9600 baud. Five-, six-, seven-, or
eight-bit characters with 1, 1-1/2, or 2 stop bits are supported. A
fully prioritized interrupt system controls transmit, receive, error,
line status, and data set interrupts. Diagnostic capabilities provide
loop back functions of transmit! receive and input/output signals.
The major component of the adapter is an INS8250 LSI chip or
functional equivalent. Features in addition to those listed above
are:
•
Full double buffering eliminating the need for precise
synchronization
•
Independent receiver clock input
•
False-start bit detection
•
Line-break generation and detection
Asynchronous Adapter 1
•
Modern control functions:
Clear to send (CTS)
Request to send (RTS)
Data set ready (DSR)
Data terminal ready (DTR)
Ring indicator (RI)
Carrier detect (CD)
All communication protocol is a function of the system microcode
and must be loaded before the adapter is operational. All pacing
of the interface and control signal status must be handled by the
system software. The following figure is a block diagram of the
IBM Asynchronous Communications Adapter.
Address Bus
Address
Decode
Chip
r.S::""e-+le-c-:"t~~
Data Bus
----------~ln~te~r~ru~p~t--------~8250
4------------------------1
Oscillator
1.8432 MHz
I------.t
Asynchronous
Communications
Element
EIA
Receivers
Current Loop
A
25-Pin D-Sheli
Connector
Asynchronous Communications Adapter Block Diagram
2 Asynchronous Adapter
Programming Considerations
Modes Of Operation
The different modes of operation are selected by programming
the 8250 Asynchronous Communications Element. This is done
by selecting the I/O address (hex 3F8 to 3FF primary, and hex
2F8 to 2FF secondary) and writing data out to the adapter.
Address bits AO, Al, and A2, select the different registers that
define the modes of operation. Also, bit 7-the divisor latch
access bit (DLAB)-of the line-control register is used to select
certain registers.
I/O Decode (in Hex)
Primary
Adapter
Alternate
Adapter
3F8
2F8
TX Buffer
DLAB
3F8
3F8
3F9
3F9
2F8
2F8
2F9
RX Buffer
Divisor Latch LSB
Divisor Latch MSB
DLAB
3FA
2F9
2FA
Interrupt Enable Register
Interrupt Identification Registers
3FB
3FC
3FD
2FB
2FC
2FD
3FE
2FE
Register Selected
DLAB State
DLAB
DLAB
= 0 (Write)
= 0 (Read)
=1
=1
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
110 Decodes
Asynchronous Adapter 3
Hex Addresses 3F8 to 3FF AND 2F8 TO iFF
A9
A8
A7
A6
A5
1
1/0
1
1
1
Note:
A4 A3
1
1
A2
A1
AO
DLAB
Register
x
x
x
0
0
0
0
Receive Buffer (read).
Transmit
Holding Reg. (write)
0
0
1
0
Interrupt Enable
0
1
0
x
Interrupt Identification
0
1
1
x
Line Control
1
0
0
x
Modem Control
1
0
1
x
Line Status
1
1
0
x
Modem Status
1
1
1
x
None
0
0
0
1
Divisor Latch (LSB)
0
0
1
1
Divisor Latch (MSB)
Bit 8 will be logical 1 for the adapter designated as primary or a logical 0
for the adapter designated as alternate (as defined by the address jumper
module on the adapter).
A2, A 1 and AO bits are "don't cares" and are used to select the different
register of the communications chip.
Address Bits
INS8250
The INS8250 has a number of accessible registers. The system
programmer may access or control any of the INS8250 registers
through the system unit's microprocessor. These registers are
used to control INS8250 operations and to transmit and receive
data. The following figure provides a listing and description of
the accessible registers.
4 Asynchronous Adapter
Register/Signal
Reset Control
Reset State
Interrupt Enable Register
Master Reset
All bits Low (0-3 Forced and
4-7 Permanent).
Interrupt Identification
Register
Master Reset
Bit 0 is High, Bits 1 and 2 Low
Bits 3-7 are Permanently Low
Line Control Register
Master Reset
All Bits Low
Modem Control Register
Master Reset
All Bits Low
Line Status Register
Master Reset
Except Bits 5 and 6 are High
Modem Status Register
Master Reset
Bits 0-3 Low
Bits 4-7 - Input Signal
SOUT
Master Reset
High
INTRPT (RCVR Errors)
Read LSR/MR
Low
INTRPT (RCVR Data Ready)
Read RBR/MR
Low
INTRPT (RCVR Data Ready)
Read IIRI
Write THR/MR
Low
INTRPT (Modem Status
Changes)
Read MSR/MR
Low
OUT2
Master Reset
High
RTS
Master Reset
High
DTR
Master Reset
High
OUT 1
Master Reset
High
Asynchronous Communications Reset Functions
Line-Control Register
The system programmer specifies the format of the asynchronous
data communications exchange through the line-control register.
In addition to controlling the format, the programmer may
retrieve the contents of the line-control register for inspection.
This feature simplifies system programming and eliminates the
need for separate storage in system memory of the line
characteristics.
Asynchronous Adapter 5
The contents of the line-control register are as follows:
Hex Address 3FB
Bit
7
6
5
4
3
2
1
a
~
Word Length Select Bit
a (WLSO)
Word Length Select Bit 1 (WLS1)
Number of Stop Bits (STB)
Parity Enable (PEN)
Even Parity Select (EPS)
Stick Parity
Set Break
Divisor Latch Access Bit (DLAB)
Bits 0 and 1: These two bits specify the number of bits in each
transmitted or received serial character. The encoding of bits 0
and 1 is as follows:
Bit 1
BitO
Word Length
0
0
a
1
1
1
0
5 Bits
6 Bits
7 Bits
8 Bits
1
Bit 2: This bit specifies the number of stop bits in each
transmitted or received serial character. If bit 2 is a logical 0, one
stop bit is generated or checked in the transmitted or received
data, respectively. If bit 2 is logical 1 when a 5-bit word length is
selected through bits 0 and 1, 1-1/2 stop bits are generated or
checked. If bit 2 is logical 1 when either a 6-, 7-, or 8-bit word
length is selected, two stop bits are generated or checked.
Bit 3: This bit is the parity enable bit. When bit 3 is a logical 1, a
parity bit is generated (transmit data) or checked (receive data)
between the last data word bit and stop bit of the serial data.
(The parity bit is used to produce an even or odd number of l's
when the data word bits and the parity bit are summed.)
6 Asynchronous Adapter
Bit 4: This bit is the even parity select bit. When bit 3 is a logical
1 and bit 4 is a logical 0, an odd number of logical 1's is
transmitted or checked in the data word bits and parity bit. When
bit 3 is a logical 1 and bit 4 is a logical 1, an even number of bits
is transmitted or checked.
Bit 5: This bit is the stick parity bit. When bit 3 is a logical 1 and
bit 5 is a logical 1, the parity bit is transmitted and then detected
by the receiver as a logical 0 if bit 4 is a logical 1, or as a logical 1
if bit 4 is a logical O.
Bit 6: This bit is the set break control bit. When bit 6 is a logical
1, the serial output (SOUT) is forced to the spacing (logical 0)
state and remains there regardless of other transmitter activity.
The set break is disabled by setting bit 6 to a logical O. This
feature enables the system unit's microprocessor to alert a
terminal in a computer communications system.
Bit 7: This bit is the divisor latch access bit (DLAB). It must be
set high (logical 1) to access the divisor latches of the baud-rate
generator during a read or write operation. It must be set low
(logical 0) to access the receiver buffer, the transmitter holding
register, or the interrupt enable register.
Programmable Baud-Rate Generator
The INS8250 contains a programmable baud-rate generator that
is capable of taking the clock input (1.8432 MHz) and dividing it
by any divisor from 1 to (2 16 _1). The output frequency of the
baud generator is 16 x the baud rate (divisor # =(frequency
input)/(baud rate x 16)). Two 8-bit latches store the divisor in a
16-bit binary format. These divisor latches must be loaded during
initialization in order to ensure desired operation of the baud-rate
generator. Upon loading either of the divisor latches, a 16-bit
baud counter is immediately loaded. This prevents long counts on
initial load.
Asynchronous Adapter 7
Hex Address 3F8 DLAB = 1
Bit
7
5
6
4
3
2
o
BitO
Bit 1
Bit 2
Bit 3
Bit4
Bit 5
Bit 6
Bit 7
Divisor Latch Least Significant Bit (DLL)
Hex Address 3F9
Bit
7
DLAB = 1
6
5
4
3
2
o
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Divisor Latch Most Significant Bit (DLM)
8 Asynchronous Adapter
The following figure illustrates the use of the baud-rate generator
with a frequency of 1.8432 MHz. For baud rates of 9600 and
below, the error obtained is minimal.
Note: The maximum operating frequency of the baud-rate
generator is 3.1 MHz. In no case should the data speed be
greater than 9600 baud.
Desired
Baud
Rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
Divisor Used
to Generate
16x Clock
(Hex)
(Decimal)
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
Percent Error
Difference Between
Desired and Actual
-
900
600
417
359
300
180
0.026
0.058
oeo
-
060
040
03A
030
020
018
010
ooe
-
-
0.69
-
Baud Rate at 1.843 MHz
Asynchronous Adapter 9
Line Status Register (LSR)
This 8-bit register provides status information to the system unit's
microprocessor concerning the data transfer. The contents of the
line status register are indicated and described in the following
figure.
Hex Address 3FD
Bit
7
6
5
4
3
2
I I
L:
o
L -_ _ _ _ _ _~
'------------1~
L...-_ _ _ _ _ _ _ _ _ _
L...-_ _ _ _ _ _ _ _ _ _ _ _ _
~
L...-_ _ _ _ _ _ _ _ _ _ _~
D." R"dy [DR[
Overrun Error (OR)
Parity Error (PE)
Framing Error (FE)
Break Interrupt (BI)
Transmitter Holding
Register Empty
(THRE)
Tx Shift Register
Empty (TSRE)
=0
Line Status Register (lSR)
Bit 0: This bit is the receiver data ready (DR) indicator. Bit 0 is
set to logical 1 whenever a complete incoming character has been
received and transferred into the receiver buffer register. Bit 0
may be reset to a logical 0 either by the system unit's
microprocessor reading the data in the receiver buffer register or
by writing logical 0 into it from the system unit's microprocessor.
Bit 1: This bit is the overrun error (OE) indicator. Bit 1 indicates
that data in the receiver buffer register was not read by the
system unit's microprocessor before the next character was
transferred into the receiver buffer register, thereby destroying
the previous character. The DE indicator is reset whenever the
system unit's microprocessor reads the contents of the line status
register.
Bit 2: This bit is the parity error (PE) indicator. Bit 2 indicates
that the received data character does not have the correct even or
odd parity, as selected by the even-parity select bit. The PE bit is
10 Asynchronous Adapter
set to logical 1 upon detection of a parity error and is reset to
logical 0 whenever the system unit's microprocessor reads the
contents of the line status register.
Bit 3: This bit is the framing error (FE) indicator. Bit 3 indicates
that the received character did not have a valid stop bit. Bit 3 is
set to logical 1 whenever the stop bit following the last data bit or
parity is detected as a zero bit (spacing level).
Bit 4: This bit is the break interrupt (BI) indicator. Bit 4 is set to
logical 1 whenever the received data input is held in the spacing
(logical 0) state for longer than a full-word transmission time
(that is, the total time of start bit + data bits + parity + stop
bits).
Note: Bits 1 through 4 are the error conditions that produce a
receiver line status interrupt whenever any of the
corresponding conditions are detected.
Bit 5: This bit is the transmitter-holding-register-empty (THRE)
indicator. Bit 5 indicates that the INS8250 is ready to accept a
new character for transmission. In addition, this bit causes the
INS8250 to issue an interrupt to the system unit's microprocessor
when the transmit-holding-register-empty interrupt enable is set
high. The THRE bit is set to logical 1 when a character is
transferred from the transmitter holding register into the
transmitter shift register. The bit is reset to logical 0 concurrently
with the loading of the transmitter holding register by the system
unit's microprocessor.
Bit 6: This bit is the transmitter-shift-register-empty (TSRE)
indicator. Bit 6 is set to logical 1 whenever the transmitter shift
register is idle. It is reset to logical 0 upon a data transfer from
the transmitter holding register to the transmitter shift register.
Bit 6 is a read-only bit.
Bit 7: This bit is permanently set to logical O.
Asynchronous Adapter 11
Interrupt Identification Register (IIR)
The INS8250 has an on-chip interrupt capability that allows for
complete flexibility in interfacing to all the popular
microprocessors presently available. In order to provide minimum
software overhead during data character transfers, the INS8250
prioritizes interrupts into four levels: receiver line status (priority
1), received data ready (priority 2), transmitter holding register
empty (priority 3), and modem status (priority 4).
Information indicating that a prioritized interrupt is pending, and
the type of prioritized interrupt, is stored in the interrupt
identification register. Refer to the "Interrupt Control
Functions" table. The interrupt identification register (IIR) ,
when addressed during chip-select time, freezes the highest
priority interrupt pending, and no other interrupts are
acknowledged until that particular interrupt is serviced by the
system unit's microprocessor. The contents of the IIR are
indicated and described in the following figure.
Hex Address 3FA
Bit
7
6
543
o
2
II
I~
~0
If 'O-
=
....'"=
I'ICI
(SHT2l
PARA 8
(SHT3)
....tH
....
r---
.....
All
~
..
00
I
.,.A9
.g=
>0-3
7
g UI'!
~:~
i
~
,IS
... B
'I lit
.,.. A7
=
(SHT3)
--{MtB2')
~82lf
(SHT21
~B21
(SHT21
~821
~I7
01
01
8 Net
N"'~N/(
.00
.
ll
'01
'02
~t"{
AOIj~
AO' '
L!A
,,
,
(SHT2,3)
(SHT2,3)
(SHT2.3)
(SHT2.3)
(SHT2,3)
'0'
(SHT2.3)
B07
(SHT2,3)
(SHT2.3)
,"
('~
~
'---
2
I UI'i
Al' A8
:3.
!.
.........
Bllt
loR
BI'J
row
0;
I
LSOLt
~
-
BOl RESET
~
..
BOI GNO
~
810 6ND
1107 -12
=
>
i"
....
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RECEIVE DATA
Serial/Printer Adapter (Sheet 3 of 3)
J
Notes:
August 31, 1984
30 Personal Computer AT Serial/Parallel Adapter
......
----=_--- ---:S~5:
Personal Computer
Hardware Reference
Library
mMBinary
Synchronous
Communications
Adapter
6361499
ii
Contents
Description .................................... 1
Programming Considerations ...................... 3
Typical Programming Sequence ................ 3
USART Programming ........................ 5
Interface ...................................... 9
Specifications ................................. 11
Logic Diagrams ................................ 13
iii
iv
Description
The IBM Binary Synchronous Communications (BSC) Adapter
provides an RS-232C-compatible communications interface for
the IBM Personal Computer family of products. All system
control, voltage, and data signals are provided through a 2- by
31-position card-edge connector. External interface is in the
form of Electronic Industries Association (EIA) drivers and
receivers connected to an RS-232C, standard 25-pin, D-shell
connector.
The adapter is programmed to operate in a binary synchronous
mode. Maximum transmission rate is 9600 bits per second (bps).
The main feature of the adapter is an Intel 8251A Universal
Synchronous/ Asynchronous Receiver/Transmitter (USART).
An Intel 8255A-5 Programmable Peripheral Interface (PPI) also
is used for expanded modem operation, and an Intel 8253-5
Programmable Interval Timer provides time-outs and generates
interrupts.
The following is a block diagram of the BSC adapter.
~
~
Timer
EIA
Drivers/
Receivers
8253
,--
Syste m
Bus
'I
I
I
I
I
I
I
I
Data
Bus
~
:;:; USART
v:
Control
~
v:f--
I
I I
I I
I
L.J
,-'I
Z~
I
Address
E=
t-:
v:;
~n
~
=
Data
Comm unications
Equipm ent
~
[;j
[;j
I
14--
I
I
I
I
8251A_
I
I
I
I
I
I
I
I
Programmable
I
I
''';ph",'
L.J
Interface
I
I
r----14---
L-
'////////;) 8255A5
Bse Adapter Block Diagram
BSC Adapter 1
2 BSe Adapter
Programming Considerations
Before starting data transmission or reception, the system unit
programs the BSC adapter to define control and gating ports,
timer functions and counts, and the communications environment.
Typical Programming Sequence
The 8255A-5 Programmable Peripheral Interface (PPI) is set for
the proper mode by selecting address hex 3A3 and writing the
control word. This defines port A as an input, port B as an output
for modem control and gating, and port C for 4-bit input and
4-bit output. An output to port C sets the adapter to the wrap
mode, disallows interrupts, and gates external clocks (address =
hex 3A2, data = hex OD). The adapter is now isolated from the
communication interface, and setup continues.
Bit 4 of the PPI's port B brings the USART reset pin high, holds
it, then drops it. This resets the internal registers of the USART.
Bse Adapter 3
The PPI's port assignments are as follows:
8255 Port A Assignments
Address:
Input Port
Bit
7
6
5
4
hex 380 for Alternate BSe
3
2
1
0
II~
8255 Port B Assignments
Address:
Output Port
Bit
7
6
5
4
hex 3AO for BSe
o = Ring Indicate is on from Interface
o = Data Carrier Defect is on from Interface
Oscillating
= Transmit Clock Active
o = Clear-to-Send is on from Interface
Oscillating = Receive Clock Active
1 = TxRDY Active
1 = Timer 2 Output Active
1 = Timer 1 Output Active
hex 3A 1 for BSe
hex 381 for Alternate BSe
3
2
1
0
II~~
Address:
8255 Port e Assignments
o = Turn on Data Signal Rate Selector
o = Turn on Select Standby
o = Turn on Test
1 = Not Used
1 = Reset 8251A
1 = Gate Timer 2
1 = Gate Timer 1
1 = Gate Timers 1 and 2 to Interrupt Level 4
hex 3A2 for BSe
hex 382 for Alternate BSe
Bit 7
6
5
4
3
2
1
0
II~~
1 = Gate Internal Clock (Output Bit)
1 = Gate External Clock (Output Bit)
1 = Electronic Wrap (Output Bit)
o = Enable Timer 1 and 2, Interrupt 6 and
Receive Interrupt 3
Oscillating = Receive Data (Input Bit)
Oscillating = Timer 0 Output (Input Bit)
o = Test Indicate Active (Input Bit)
o = BSC Adapter
The USART uses the 8253-5 Programmable Interval Timer (PIT)
in the synchronous mode for inactivity time-outs to interrupt the
system unit after a preselected amount of time has elapsed from
the start of a communication operation. Counter 0 is not used for
synchronous operation. Counters 1 and 2 connect to
4 BSe Adapter
interrupt-level 4 and, being programmed to terminal-count values,
provide the desired time delay before generating a level-4
interrupt. These interrupts signal the system that a predetermined
amount of time has elapsed without a TxRDY (level 4) or an
RxRDY (level 3) interrupt being sent to the system unit.
USART Programming
After the support devices on the BSC adapter are programmed,
the USAR T is loaded with a set of control words that defines the
communication environment. The control words consist of mode
instructions and command instructions.
Both the mode and command instructions must conform to a
specified sequence for proper device operation. The mode
instruction must be inserted immediately after a reset operation
before using the USART for data communications. The required
synchronization characters for the defined communication
technique are then loaded into the USART (usually hex 32 for
BSC). All control words written to the USART after the mode
instruction wi11load the command instruction. Command
instructions can be written to the USART in the data block any
time during its operation.
To return to the mode instruction, the master reset bit in the
command instruction word is set to start an internal reset
operation, which places the USART back into the mode
instruction. Command instructions must follow the mode
instructions or synchronization characters.
BSC Adapter 5
The following represents a typical data block and shows the mode
instruction and command instruction.
3A9C/D = 1
Mode Instruction 1
3A9 c/o = 1
SYNC Character 1
3A9Cio = 1
SYNC Character 2
3A9Cio = 1
Command Instruction
3A8C/D = 0
I
3A9
Data
I
c/o = 1
3A8Cio
3A9
~
c/o
Command Instruction
= 1 ~~
= 1
~
Data
~
Command Instruction
Typical Data Block
The following are the communications interrupt levels.
• Interrupt level 4
Transmit
Timer 1
Timer 2
• Interrupt level 3
- Receive
6 BSC Adapter
The following are device addresses.
Hex Address
Device
Register Name
Function
Primary
Alternate
3AO
3A1
3A2
3A3
380
381
382
383
8255
8255
8255
8255
Port A Data
Port B Data
Port C Data
Mode Set
Internal/External Sensing
External Modem Interface
Internal Control
8255 Mode Initialization
3A4
3A4
3A5
3A5
3A6
3A6
3A7
384
384
385
385
386
385
387
8253
8253
8253
8253
8253
8253
8253
Counter 0 LSB
Counter 0 MSB
Counter 1 LSB
Counter 1 MSB
Counter 2 LSB
Counter 2 MSB
Mode Register
Not Used in Sync. Mode
Not Used in Sync. Mode
Inactivity Time Outs
Inactivity Time Outs
Inactivity Time Outs
Inactivity Time Outs
8253 Mode Set
3A8
3A9
388
389
8251
8251
Data Select
Command/Status
Data
USART Status
Device Address Summary
Bse Adapter 7
8 BSC Adapter
Interface
The IBM Binary Synchronous Communications Adapter
conforms to interface signal levels standardized by the Electronic
Industries Association (EIA) RS-232C Standard. The following
figure shows these levels.
Driver
EIA RS232C/CCITT V24·V28 Signal Levels
+15 Vdc - - - - - - - - - - - ,
~
Active/Data
0
+5 Vdc
+5 Vdc
I nval id Level
-5 Vdc
-5 Vdc
Inactive/Data = 1
-15 Vdc
Receiver
EIA RS232C/CCITT V24-V28 Signal Levels
+25Vdc .----------~
Active/Data
~
0
+3 Vdc
+3 Vdc
I nvalid Level
-3 Vdc
-3 Vdc
I nactive/Data
~
1
-25 Vdc
Interface Voltage Levels
BSC Adapter 9
Pins 11, 18, and 25 on the interface connector are not
standardized by the EIA. These lines are designated as 'select
standby,' 'test,' and 'test indicate.' 'Select standby' is used to
support the switched network backup facility of a modem that
provides this option. 'Test' and 'test indicate' support a modem
wrap function on modems designated for business-machine,
controlled-modem wraps.
10 BSe Adapter
Specific a tions
25-Pin D-Shell
Connector
o
13
••
••
•
••
•
•
•
•
•
25
•
••
•
•
•
•
14
o
Signal Name - Description
No Connection
Transmitted Data
Received Data
Request to Send
Clear to Send
Data Set Ready
Signal Ground
Received Line Signal Detector
No Connection
No Connection
External
Device
Select Standby*
No Connection
No Connection
No Connection
Transmitter Signal Element Timing
No Connection
Receiver Signal Element Timing
Test (IBM Modems Only)*
No Connection
Data Terminal Ready
No Connection
Ring Indicator
Data Signal Rate Selector
No Connection
Test Indicate (IBM Modems Only)*
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Binary
Synchro nous
Commun ications
Adapter
*Not standardized by EIA (Electronic Industries Association).
Connector Specifications
Bse Adapter 11
12 BSC Adapter
Logic Diagrams
lID BUS
8255 PCO IIIITERIiIAl CLOCK
••
,..
+AO
31
31
+A1
OSC
+12
+5 VOLTS
8255 PCI 10DEI CLOCI
lOR
3D
30
k-+t<~---1
""
Ell IODEI
REG RECEIIE GLOCI
28
+A3
"21
+A4
+A5
21
" ""
""
"
""
+ ..
-IB03
+A1
+IR04
24
+..
DATA SET
READY
AO-Al
23
+A9
21
CLEAR TO SEND
21
20
20
"
.
18
11
11
"
15
-lOR
"
-lOW
13
RECEIVE DATA
18
IRO 4
CARRIER DETECT
18
RillS lID.
15
14
+ RESET
13
12
12
+1£111
10
'.0
+00
10
+12 VOLTS
+01
+D2
-12 VOLTS
+03
J'
+04
13
+D5
+08
+5V
24 SELECT STAY
23 RATE SElECT
+5 JOLTS
+01
10
+flESET
GND
25 TEST liD
12
22 RIIIG Ilia
+--~--~----~--~--"3
T
1
1C1
BOARD TO CARD
CDIINECTOR
T
T
2C1=T
i-T
1&2
1••• =T
B2a
1BC2
f--+---~----~--~-BO'
+--+----+----+--+--13'
1L _,
rrn-_
,,
,,
+'"----11:r-,,-,---,..
L'
,.,,----"I>'-=,,"-,---801/831
14
Ell CARD TO
CABLE CO••ECTOR
" ----<..->----101
-'"
l ~-1--
J
_1""'1.
Binary Synchronous Communications Adapter (Sheet 1 of 2)
Bse Adapter 13
Binary Synchronous Communications Adapter (Sheet 2 of 2)
14 BSe Adapter
II~UL&ROIIIID
1
BSC Adapter 15
16 BSe Adapter
----- ---- -- -------_.-
Personal Computer
Hardware Reference
Library
mM Synchronous Data
Link Control (SDLC)
Communications
Adapter
6361497
ii
Contents
Description .................................... 1
8273 SDLC Protocol Controller ................ 2
8255A-5 Programmable Peripheral Interface ...... 2
8253-5 Programmable Interval Timer ............ 4
Programming Considerations ...................... 5
Initializing the Adapter (Typical Sequence) ....... 5
8253-5 Programmable Interval Timer ............ 5
Address and Interrupt Information .............. 6
Interface ...................................... 7
Specifications .................................. 9
Logic Diagrams ................................ 11
iii
iv
Description
The IBM Synchronous Data Link Control (SDLC)
Communications Adapter provides communications support to
the system in a half-duplex synchronous mode. The adapter
receives address, data, and control signals from the system board
through the internal bus. Electronic Industries Association (EIA)
drivers and receivers connect to an RS232-C standard 25-pin,
D-shell, male connector.
The adapter is programmed by communications software to
operate in a half -duplex mode. Maximum transmission rate is
9600 bits per second, as generated by the attached modem or
other data communications equipment.
The SDLC adapter uses an Intel 8273 SDLC Protocol Controller
and an Intel 8255A-5 Programmable Peripheral Interface (PPI)
for an expanded external modem interface. An Intel 8253
Programmable Interval Timer (PIT) generates timing and
interrupt signals. Internal test-loop capability is provided for
diagnostic purposes.
The following figure is a block diagram of the IBM SDLC
Communications Adapter.
Data
Bus
Buffer
EIA
Drivers
Receivers
System
Bus
Address
Address
Decode
Logic
' - - - - - - + I Controller
DCE
Modem
Status
Change
Logic
SDLC Communications Adapter Block Diagram
SDLC Communications Adapter 1
8273 SDLC Protocol Controller
The 8273 SDLC Protocol Controller has three operationstransmission, reception, and port read-with each operation
consisting of three phases:
Command: Commands and/or requirements for the operation
are issued by the system unit's microprocessor.
Execution: Executes the command, manages the data link, and
may transfer data to or from memory using direct memory access
(DMA), and thus freeing the system unit's microprocessor except
for minimal interruptions.
Result: Shows the effect of the command by returning the
interrupt results.
Support of these phases is through the internal registers and
control blocks of the controller.
8255A-5 Programmable Peripheral Interface
The 8255A-5 PPI has three 8-bit ports-A, B, and C.
Descriptions of each bit of these ports follow.
8255A-5 Port A Assignments*
Bit
7 6
5 4
3
2
Hex Address 380
1 0
~
0= Ring Indicator is on from Interface
0= Data Carrier Detect is on from Interface
Oscillating = Transmit Clock Active
0= Clear to Send is on from Interface
Oscillating = Receive Clock Active
1 = Modem Status Changed
1 = Timer 2 Output Active
1 = Timer 1 Output Active
* Port A is defined as an input port
2 SDLC Communications Adapter
8255A-5 Port B Assignments*
Bit
7
6
5 4 3 2
1
Hex Address 381
0
~
0= Turn On Data Signal Rate Select at
Modem Interface
0= Turn On Select Standby at Modem
Interface
0= Turn On Test
1 = Reset Modem Status Changed Logic
1 = Reset 8273
1 = Gate Timer 2
1 = Gate Timer 1
1 = Enable Level 4 Interrupt
* Port B is defineq as an output port
Hex Address 382
8255A-5 Port C Assignments*
Bit
7 6
5 4
3
2 1 0
III ~ =
1 Go<, '""",'
C'ooklO",,", 6'"
1 = Gate External Clock (Output Bit)
1 = Electronic Wrap (Output Bit)
0= Gate Interrupts 3 and 4 (Output Bit)
Oscillating = Receive Data (Input Bit)
Oscillating = Timer 0 Output (Input Bit)
0= Test Indicate Active (Input Bit)
Not Used
*Port C is defined for internal control and gating functions. It has three input
and four output bits. The four output bits are defined during initialization, but
only three are used.
SDLC Communications Adapter 3
8253-5 Programmable Interval Timer
The 8253-5 PIT is driven by a microprocessor clock signal that is
divided by 2. The PIT's three counters provide the following
output:
Counter 0
Programmed to generate a square-wave signal that is
used as an input to timer 2. Also connected to port
C, bit 5 of the PIT.
Counter 1
Connected to PPI port A, bit 7, and interrupt-level 4.
Counter 2
Connected to PPI port A, bit 6, and interrupt-level 4.
4 SDLC Communications Adapter
Programming Considerations
Initializing the Adapter (Typical Sequence)
Before the 8273 SDLC Protocol Controller is started, the support
devices on the adapter must be set to the correct modes of
operation.
Setup of the 8255A-5 Programmable Peripheral Interface is
accomplished by selecting the mode set address for the PPI and
by writing the appropriate control word to hex 98 to set ports A,
B, and C to the modes described previously in this section.
Next, a bit pattern sent to port C disallows interrupts, sets wrap
mode on, and gates the external clock pins (address is hex 382,
data is hex OD). The adapter is now isolated from the
communications interface.
The controller reset line is brought high through bit 4 of port B,
held, then dropped. This action resets the internal registers of the
controller.
8253-5 Programmable Interval Timer
The PIT's counters 1 and 2 terminal-count values are set to values
that will provide the desired time delay before a level-4 interrupt
is generated. These interrupts may be used to indicate to the
communication programs that a predetermined amount of time
has elapsed without a result interrupt (interrupt-level 3). The
terminal-count values for these counters are set for any time delay
the programmer requires. Counter 0 also is set to mode 3
(generates square-wave signal used to drive counter 2 input).
The counter modes are set up by selecting the address for the
PIT's counter-mode register and by writing the control word for
each individual counter to the device separately.
SDLC Communications Adapter 5
When the support devices are set to the correct modes and the
8273 SDLC Protocol Controller is reset, it is ready to be set up
for the operating mode that defines the communications
environment in which it will be used.
Address and Interrupt Information
The following tables provide address and interrupt information
for the SDLC adapter.
Hex Code
Device
Register Name
Function
380
381
382
383
384
384
385
385
386
386
387
388
389
38A
38B
38C
8255
8255
8255
8255
8253
8253
8253
8253
8253
8253
8253
8273
8273
8273
8273
8273
Port A Data
Port B Data
Port C Data
Mode Set
Counter 0 LSB
Counter 0 MSB
Counter 1 LSB
Counter 1 MSB
Counter 2 LSB
Counter 2 MSB
Mode Register
Command/Status
Parameter/Result
Transmit INT Status
Receive INT Status
Data
Internal/External Sensing
External Modem Interface
Internal Control
8255 Mode Initialization
Square Wave Generator
Square Wave Generator
Inactivity Time-Outs
Inactivity Time-Outs
Inactivity Time-Outs
Inactivity Time-Outs
8253 Mode Set
Out = Command In = Status
Out = Parameter In = Status
DMA/INT
DMA/INT
DPC (Direct Program Control)
SDLC Communications Adapter Device Addresses
Interrupt Level 3
Transmit/Receive Interrupt
Interrupt Level 4
Timer 1 Interrupt
Timer 2 Interrupt
Clear to Send Changed
Data Set Ready Changed
DMA Level 1 is used for Transmit and Receive
Interrupt Information
6 SDLC Communications Adapter
Interface
The SDLC Communications Adapter conforms to interface signal
levels standardized by the Electronic Industries Association
(EIA) RS232-C Standard. These levels are shown in the
following figure.
Drivers
Receivers
+15VdC~
+5Vdc
+ 25 Vdc
~
+ 3 Vdc
Invalid Level
- 5 Vdc
~
-15VdC~
- 3 Vdc
Inactive Level: Data
=1
L-25VdO
Additional lines used but not standardized by the ErA are pins 11,
18, and 25. These lines are designated as 'select standby,' 'test,'
and 'test indicate,' respectively. 'Select standby' supports the
switched network backup facility of a modem that has this option.
'Test' and 'test indicate' support a modem-wrap function for
modems that are designed for business-machine controlled
modem-wraps. Two jumpers on the adapter (PI and P2) connect
'test' and 'test indicate' to the interface.
SDLC Communications Adapter 7
8 SDLC Communications Adapter
Specifications
25-Pin D-Shell
Connector
o
•
•
•
•
•
•
•
•
••
•
•
•
13
•
•
•
•
•
•
•
•
•
•
•
•
25
14
0
Signal Name - Description
Pin
1
2
3
4
5
6
No Connection
Transmitted Data
Received Data
Request to Send
Clear to Send
Data Set Ready
7
Signal Ground
Received Line Signal Detector
No Connection
No Connection
External
Device
Select Standby*
No Connection
No Connection
No Connection
Transmitter Signal Element Timing
No Connection
8
9
10
11
12
13
14
15
16
Receiver Signal Element Timing
17
Test (IBM Modems Only)*
18
19
20
21
22
23
24
25
No Connection
Data Terminal Ready
No Connection
Ring Indicator
Data Signal Rate Selector
No Connection
Test Indicate (IBM Modems Only)*
Synchronous
Data Lin k
Control
Commu nications
Adapter
*Not standardized by EIA (Electronic Industries Association),
Connector Specifications
SDLC Communications Adapter 9
10 SOLC Communications Adapter
Logic Diagrams
The following pages contain the logic diagrams for the IBM
Synchronous Data Link Control (SDLC) Adapter.
SDLC Communications Adapter 11
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12 SDLC Communications Adapter
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Personal Computer
Hardware Reference
Library
mM Cluster Adapter
6361495
ii
Contents
Description. ................................... 1
8031 Microcomputer ........................ 5
Cluster Adapter I/O Register Definitions ....... 12
Programming Considerations ..................... 18
Interface ..................................... 83
System Processor I/O Interface ............... 83
Cluster Adapter Switch Settings ............... 84
System Processor Memory Interface ............ 90
System Processor Interrupt Interface ........... 90
8255 Programmable Peripheral Interface (PPI) ... 91
Cluster Bus Interface ....................... 94
Specifications ................................. 96
Logic Diagrams ................................ 97
Index ........................................ Index ... 1
iii
iv
Description
The Cluster Adapter is a 10.16 cm (4 inch) high by 25.4 cm (10
inch) wide communication adapter used for linking up to 64 IBM
Personal Computers (PCs). The transmission rate is 375,000 bits
per second (bps). A multi-drop bus architecture passively links
(cluster operation is unaffected if the power to any station is off)
the PCs to a coaxial cable. The coaxial cable bus can be a
maximum length of 1 kilometer (3280 feet) and requires a
75-ohm (n) terminating resistor at both ends to minimize signal
reflection. The coaxial cable drop can be a maximum length of 5
meters (16.4 feet) and a minimum length of 1 meter (3.3 feet).
The following is an example of a cluster:
75D
Resistor
75D
Resistor
CLUSTER EXAMPLE
The PCs share the bus through a distributed-access protocol
called carrier sense multiple access with collision avoidance
(CSMA/CA). With this protocol, each PC (station) that wants
to transmit, calculates its own access-window wait time after no
signal is sensed on the bus. The wait time differs for each station
and changes with each transmission to prevent collisions (two
stations transmitting at the same time). If cluster traffic is light
(no signal is on the coaxial cable for approximately 2.8
milliseconds), a station that wants to transmit establishes cluster
synchronization by transmitting all l's (111 ... 1) for 150
Cluster Adapter 1
microseconds (p,s), thereby forcing a carrier sense transition
(On-to-Off). The station can then calculate its access-window
wait time.
Because the PCs are passively connected and operate under a
distributed-access protocol, the operation of the cluster is
unaffected if the power to any single station is off.
The Cluster Adapter sends and receives frames consisting of
link-control and information fields to and from other Cluster
Adapters in the cluster.
The Cluster Adapter consists of the following components:
•
•
•
•
•
•
•
8031 8-bit Microcomputer
8031 Accessible ROM
8031 Accessible RAM
System Processor (8088) Interface
Adapter Status Register
8088 Accessible ROM
8255 Programmable Peripheral Interface (PPI)
Cyclic Redundancy Checking (CRC) Hardware
Cluster Interface
2 Cluster Adapter
The following is a block diagram of the Cluster Adapter:
Cluster Coaxial Cable
~
T
Cluster
Serial
Interface
I
Data
BK ROM/4K RAM
Address
CRC
H/W
~
-
Data Buffer
8255
PB
PA
PC
J
PO
P2
8031
P1
P3
8088 ROM
8K
I
I Switches
Addr I
I Register
Status I
I
Processor
Interface
System Processor Bus
Cluster Adapter Block Diagram
Cluster Adapter 3
DANGER
TO HELP PROTECT FROM LIGHTNING AND
OTHER SOURCES OF ELECTRICAL SHOCK, IBM
REQUIRES THAT THE COAXIAL CABLE
SHIELDING BE GROUNDED, AND NEITHER THE
FRAME NOR COVERS OF THE IBM PERSONAL
COMPUTER CAN BE USED AS THE GROUNDING
POINT.
•
To ensure proper operation of the cluster, the shielding of the
coaxial cable cannot be grounded at more than one point.
•
If compliance to electrical codes require multiple ground
points, then triaxial cable (double shielded) must be used. In
using the triaxial cable, only the outer shielding can be
grounded and under no circumstances should the outer shield
be connected to the inner shield.
•
This installation should be performed by a licensed electrician.
4 Cluster Adapter
8031 Microcomputer
The 8031 Microcomputer is the controlling processor for the
Cluster Adapter. The 8031 has an 8K x 8-bit ROM, and a 4K x
8-bit static RAM.
The 8031 consists of the following:
•
A processor
•
A dynamic 128 x 8-bit read/write data memory
•
32 I/O lines
•
2 16-bit timer/event counters
•
A five-source, two-priority-Ievel, nested interrupt structure
•
A serial I/O port for mUltiprocessor communications
•
I/O expansion or a full duplex Universal
Synchronous/ Asynchronous Receiver/Transmitter (USART)
•
An on-chip oscillator and clock circuits.
The 8031 also provides addressing for up to 64K bytes of
program memory and 64K bytes of data memory.
The 8031 is operated at 12 Megahertz (MHz), yielding a
single-cycle time of 1 p,s.
Program and data address spaces on the adapter are combined
into a 64K-byte address space by ORing -Program Store Enable
( -PSEN) and -Read (-RD). The memory address space includes
not only the 8K x 8-bit ROM and 4K x 8-bit static RAM, but also
the 8255 port and control registers and the 2653 registers
necessary for CRC calculation.
Cluster Adapter 5
8031 Ports
The 8031 on the Cluster Adapter provides external memory
addresses through ports 0 and 2.
•
Port 0 is an 8-bit, open-drain, bidirectional, I/O port used as
the multiplexed low-order address and data bus.
•
Port 2 is a bidirectional I/O port and provides the high-order
address byte for the external memory.
Port 1 of the 8031 is an 8-bit, bidirectional, I/O port used on the
adapter for status conditions.
Port 3 is an 8-bit, bidirectional, I/O port used as a serial port and
as a source for external memory and serial-transmission control
lines.
6 Cluster Adapter
The following is a summary of the 8031 port signals:
Port 0
Port 2
Port 3
Port 1
Transmission
and Control
Lines
Status
External Memory
Address
Bits
Low Order
Byte and
Data Bus
High Order
Address
Byte Only
7
A7/D7
A15
-RD
Direction to 8031
6
A6/D6
A14
-WR
Error
5
A5/D5
A13
-CRC INT
Communication
Port Busy
4
A4/D4
A12
-RTS
RX Virtual 1/0
Frame Available
3
A3/D3
A11
+Internal Loop
RX Frame in (FIFO)
2
A2ID2
A10
-Carrier Sense
Data Available for
8088 (0 = Active)
1
A1/D1
A9
+TXD
Command or Data
Available for 8031
0
AO/DO
A8
+RXD
Command in
Progress
Summary of 8031 Port Signals
Cluster Adapter 7
Serial Transmission and Control Lines
The serial transmission lines are:
+Receive Data (+RXD)
The + RXD line provides the
serial port's receiver data input.
+ Transmit Data (+ TXD)
The + TXD line provides the serial
port's transmitter data output.
The serial transmission control lines are:
-Request to Send (-RTS)
The -RTS signal enables the
adapter's transmitter to send data
on the cluster cable bus.
+ Internal Loop
The + Internal Loop line is used in
the diagnostic mode. When high,
it activates the internal loop back
feature so the Cluster Adapter can
receive the data it is transmitting
without interference or being
attached to the bus.
-Carrier Sense
-Carrier Sense is an input signal to
port 3 that indicates the current
state of the cluster; it is low (0)
when the cluster is busy.
8 Cluster Adapter
The memory control lines are:
-Write (-WR)
The -WR line latches the data
byte from port 0 into the external
data memory.
-Read (-RD)
The -RD line enables external
data memory to port o.
The interrupt line is:
-CRC Interrupt (-CRC INT)
The -CRC INT line is used to
indicate a successful or
unsuccessful comparison in CRC
values. The signal source is -INT
from the 2653 Polynomial
Checker Generator.
8K X 8-Bit ROM
The 8K x 8-bit ROM contains the 8031 code necessary for
hardware initialization and the data link control program
(DLCP). The DLCP is the lowest level of software for the
Cluster Adapter. The DLCP resides in the 8K by 8-bit ROM on
the Cluster Adapter, which is accessible by the 8031
Microcomputer.
4K X 8-Bit Static RAM
The 4K x 8-bit static RAM is available to the 8031 for read/write
storage necessary to implement the DLCP. The available space is
used to buffer frames and to store control and cluster
information. The 4K x 8-bit static RAM is implemented using
two 2K x 8-bit static RAM modules.
Cluster Adapter 9
The following is the 8031 memory map:
Start Address (Hex)
Function
0000
DlCP ROM
2000
RAM
3000
8255 Port A
3001
8255 Port 8
3002
8255 Port C
3003
8255 Control
3004
2653 Character Register
3005
2653 Status Register
3006
2653 Mode Register
3007
2653 CRC Upper flower Registers
8031 Memory Map
8088 Accessible ROM
The 8088 (System Processor) accessible ROM is an 8K x 8-bit
ROM and contains the 8088 code necessary to perform the
remote initial program load (IPL) and power-on diagnostic
functions.
2653 Polynomial Generator Checker
The 2653 Polynomial Generator Checker is used by the 8031
Microcomputer to compute the Cyclic Redundancy Check (CRC)
value for transmitted or received data blocks for error checking.
10 Cluster Adapter
The 2653 is programmed by the 8031 in the automatic mode to
generate the American National Standards Institute (ANSI)
CRC-16 values. Two 8-bit characters are read from the 2653
character register into the Block Check Character (BCC)
generation unit to calculate the 16-bit check character.
Programming is achieved as follows:
•
The Clear CRC command, hex 02, is issued to the 2653
command register at address hex 3005.
•
The Automatic Accumulation Mode command, hex 49, is
issued to the 2653 mode register at address hex 3006.
•
The Start Accumulation command, hex 01, is issued to the
2653 command register at address hex 3005.
•
Characters to be accumulated are written to the character
register at address hex 3004.
The accumulated CRC value may be read by the 8031 from
address hex 3007 (the 2653 CRC upper and lower registers) in
two read operations. The 2653 alternately provides the upper and
lower values.
The 2653 is activated upon proper decoding of addresses in the
range of hex 3004 through hex 3007 and the occurrence of -Read
Strobe (-RS) or -Write (-WR). This allows the input to the
. -Read/Write (-R/W) pin of the 2653 to become stable prior to
the fall of -Clear Entry 1 (-CEl), as required.
Cluster Adapter 11
Cluster Adapter 110 Register Definitions
The following defines the Cluster Adapter I/O registers:
Adapter
Adapter 1
I/O Address
(Hex)
Device
0790
Adapter Status Reg ister
0791
Adapter Command/Data (Output)
Adapter Result/Data (Input)
Adapter 2
0792
Adapter Interrupt Register
0793
Adapter Reset Control
0890
Adapter Status Register
0891
Adapter Command/Data (Output)
Adapter Result/Data (Input)
Adapter 3
0892
Adapter Interrupt Register
0893
Adapter Reset Control
1390
Adapter Status Register
1391
Adapter Command/Data (Output)
Adapter Result/Data (Input)
Adapter 4
1392
Adapter Interrupt Register
1393
Adapter Reset Control
2390
Adapter Status Register
2391
Adapter Command/Data (Output)
Adapter Result/Data (Input)
2392
Adapter Interrupt Register
2393
Adapter Reset Control
Cluster Adapter I/O Registers
12 Cluster Adapter
Adapter Status Register
The adapter status is provided to the system data bus by a
74LS373 transparent latch.
The following are the bit assignments:
Bit
Definition (1 = Active Unless Noted)
7
Direction (1 = data expected from 8088 to 8031)
6
Error
5
Communication Port Busy
4
RX Virtual I/O Frame Available
3
RX Frame in First in First Out (FIFO)
2
Data Available for 8088 (0 = active)
1
Command/Data Available for 8031
0
Command in Progress
Status Register Bit Definitions
The outputs of the transparent latch, though not enabled on the
bus, continuously follow the inputs provided by the 8031 and
8255. Upon decoding of the read-status I/O address, the
latch-enable input to the transparent latch goes low, latching the
inputs of the current state and enabling the data onto the bus.
The status bits are latched during the active read time to preserve
the integrity of the data. When the outputs are disabled and the
latch-enable input to the latch goes high at the end of the read
cycle, the outputs of the transparent latch again monitor the
inputs in real time.
Cluster Adapter 13
Definition of Bits at Port 0791
(for Adapter 1)
(Command or Parameters for 8031)
Bit
Definition
7
Command or Data Bit 7
6
Command or Data Bit 6
5
Command or Data Bit 5
4
Command or Data Bit 4
3
Command or Data Bit 3
2
Command or Data Bit 2
1
Command or Data Bit 1
0
Command or Data Bit 0
Cluster Adapter Command/Data Register (Output)
Definition of Bits at Port 0791
(for Adapter 1)
(Result or Data from 8031)
Bit
Definition
7
Result or Data Bit 7
6
Result or Data Bit 6
5
Result or Data Bit 5
4
Result or Data Bit 4
3
Result or Data Bit 3
2
Result or Data Bit 2
1
Result or Data Bit 1
0
Result or Data Bit 0
Cluster Adapter Result/Data Register (Input)
14 Cluster Adapter
Definition of Bits at Port 0792 (for Adapter 1)
Bit
Definitions
7-2
Not used.
1
Received Frame(s) Available. One or more information frames have
been received and may be read using either the BIOS Receive
Frame or Receive Virtual 1/0 Frame command (1 = active).
0
Cluster BIOS Command Complete. The Cluster BIOS command
intiated with the Initiate Transmit bit set is complete. The result
must be obtained by issuing the same Cluster BIOS command with
the Finish Transmit bit set (1 = active).
Cluster Interrupt Status Bits
Note: Both bits 1 and 0 are set to indicate interrupt due to
Cluster Status command complete.
Definition of Bits at Port 0793 (for Adapter 1 )
Bit
Definitions
7 -1
Not used.
0
Reset Cluster Adapter. The adapter microprocessor as well as all
other logic on the adapter will be held in a reset condition until
there is an output with this Reset Adapter bit set to zero (1 = active).
Note: Any output to the reset register will also disable the adapter from
generating interrupts.
Cluster Adapter Reset Register Bit Definitions
Cluster Adapter 15
Cluster Adapter Interrupts
The Cluster Adapter may be set (one jumper selectable) to allow
interrupts on either interrupt-level 3 or interrupt-level 7. An
adapter error detected by diagnostic tests is reported if the
interrupt jumper is missing. The received frames must be
available or the Transmit operation complete (if initiated by a
Transmit command with the Initiate Transmit bit set).
Up to four Cluster Adapters can be installed at a station. Each
adapter can be enabled/disabled and all are similar in operation.
If enabled, the adapter generates interrupts on levels 3 or 7
provided one of the following conditions is met:
•
•
•
A received frame is available.
The Transmit Frame command is complete.
The Cluster Status command is complete.
The following description is for adapter 1:
1. Interrupts are enabled by executing an output instruction to
the adapter's interrupt enable register.
2. Interrupts are disabled by writing the hex 00 instruction to the
adapter's reset register. Also, additional interrupts are
disabled by generating the interrupt request. The adapter
must be re-enabled after each interrupt if additional interrupts
are desired.
16 Cluster Adapter
3. To avoid resetting the adapter, data bit 0 must be set to a 0
when an output is sent to the adapter's reset register.
No interrupt handler is provided for the cluster, and must be
provided by the user who requires interrupt capability.
The interrupt condition is provided in the adapter's interrupt
register, as described in the Cluster Adapter Interrupt Status
Bits table.
Cluster Adapter 17
Programming Considerations
The data link control program (DLCP) is the lowest level of
software for the Cluster Adapter. The DLCP resides in the 8K
by 8-bit ROM, which is accessible by the 8031 Microcomputer.
The Cluster Adapter basic input! output system (BIOS) code
resides in an 8K-byte 8088 accessible ROM on the Cluster
Adapter at address hex DOOOO.
Note: The Cluster Adapter decodes a 32K-byte range starting
at hex DOOOO. High-level cluster BIOS commands are
processed by the cluster BIOS into the appropriate low-level
. commands and parameters. The low-level commands and
parameters are then passed to the 8031 Microcomputer, which
performs the requested command. After the command is
complete, the 8031 Microcomputer transfers the results back
to the DLCP BIOS routine, which fills in the requester's link
control block (LCB) with the results and then return through
an interrupt return (IRET) to the requester that issued the
INT hex 5A.
The cluster BIOS level interface allows the higher layer
communication program to transmit to and receive data from the
specified destination through the bus. The basic unit of
information transmitted using DLCP is a frame. A frame consists
of a control field and an optional data field.
18 Cluster Adapter
The following functions are implemented in the DLCP to
interface with the higher layer communication program and to
ensure reliable data transfer between stations on the bus:
•
•
•
•
•
•
•
Higher layer communication program BIOS interface to the
communication software
Frame assembly, reception and transmission
CRC generation and checking
Carrier sense multiple access with collision avoidance
(CSMA/CA)
Error detection and recovery
Cluster status monitoring
Remote IPL
Cluster Adapter 19
Higher Layer Communication Program BIOS
Interface
When the Power switch is set to On, the hex 5A software
interrupt vector is set to the address of the Cluster Adapter BIOS
by the adapter's self-test diagnostic code.
Notes:
1. The DLCP must be initialized before it can process most of its
commands.
2. Interrupt hex 5A is reserved for the Cluster Adapter BIOS and
should not be changed.
The higher layer communication program must access the Cluster
Adapter BIOS through an interrupt hex 5A instruction. The
program must set the Extra Segment (ES) Register output to the
segment and the Base Index (BX) Register output to the offset of
the Link Control Block (LCB) before invoking the cluster DLCP
BIOS. All parameters, the return code, and the cluster status are
passed through the LeB.
20 Cluster Adapter
The format of the LCB is shown below:
Link Control Block (LCB)
Number of Bytes
Destination Station Physical Address
1
Source Station Physical Address
1
Command
1
Buffer 1 Length
2
Buffer 1 Address
2 (Offset)
2 (Segment)
Buffer 2 Length
2
Buffer 2 Address
2 (Offset)
2 (Segment)
Return Code
1
Cluster Status
1
Select Adapter
1
Structure of Link Control Block (LCB)
Notes:
1. The internal variables and buffers of the DLCP are in the
RAM resident on the adapter and are not directly accessible
from the higher layer communication program.
2. Select Adapter is used to select the adapter for which the
command is intended (0 for adapter 1, 1 for adapter 2, 2 for
adapter 3, and 3 for adapter 4).
3. For the length and address fields, the word values are ordered
least-significant byte first.
Cluster Adapter 21
The contents of buffer 1 and buffer 2 together form the
information field of the frame. For example, buffer 1 can be used
to store header bytes while buffer 2 can be used to store the
actual data to be transferred.
The return code indicates the success or failure of the function
requested, and the error code if the function fails. The LCB
status indicates the current status of the cluster. This field is valid
as a result of the DLCP Status command. The LCB status field is
also used by some commands to store an extended return code.
Frame Transmission
Transmit or Transmit Virtual Information frames are sent by the
DLCP to complete the corresponding DLCP BIOS commands. The
DLCP on its own initiative transmits various frames. The
following response frames are issued in response to a received
frame:
Ack
Frame Reject
Not Connected
Bad Error
Duplicate Address
22 Cluster Adapter
Reception OK with no problems
All receive buffers full
Not connected to sending station
Frame out of sequence (rejected)
Duplicate station address exists on the
cluster
The following control frame is transmitted by the DLCP when the
Power switch is set to On or at initialization:
Initializing
Broadcast to all stations to indicate that the
source station is in the process of initializing and
all connections to that station should be set to
the disconnected state. Also, if any station has
the same station address, it sends a
duplicate-address response back to the
initializing station.
In addition, the DLCP determines if it is necessary to send a
connect frame to establish connection with the destination
station. If this station's Cluster Status table indicates that it is not
connected to the destination station, the DLCP transmits a
connect frame to establish connection and then transmits the
information frame. If a not-connected control frame is received
in response to the transmission of a frame, the DLCP transmits a
connect frame to establish connection, then transmits the
information frame.
Cluster Adapter 23
Frame Format
The basic unit of information transmitted is a frame. The
On-to-Off transition of the 'carrier sense' signal identifies the
beginning of a frame, and the Off-to-On transition identifies the
end. A frame consists of fixed control fields and an optional
variable length information field. The following shows the format
of a frame:
Field
Number of Bytes
Note
Desti nation Address
1
Control
Source Address
1
Field
Transmit Window Token
1
Control
1
Sequence
1
Byte Count
2
Control CRC
2
Information
1 to 578
Information
Data CRC
2
Field
Frame Format
Note: The minimum and maximum total number of bytes
transmitted for a frame is 9 and 587, respectively. The
transmission time for a frame ranges from approximately 1
millisecond (ms) for a minimum length frame up to
approximately 16.5 ms for the maximum length frame.
However, additional time may be required to gain access to
the cluster before a frame can be sent.
24 Cluster Adapter
Control Field Format
The control field consists of the following:
Destination Address - The destination address can be any
number from hex 00 through hex 3F; that is, 64 station addresses
are supported. Address hex FF is reserved as the broadcast
address that all stations respond to. Addresses hex FE through
hex FO are reserved for use as multicast addresses.
Source Address - The source address is used to tell the DLCP
the senders station address. The DLCP uses the source address
as an index into a Cluster Status Table, which is used to maintain
the status of connected stations and sequence numbers for each
possible sender. Station addresses hex 00 through hex 3F are the
only supported source addresses.
Transmit Window Token - This value is updated for every
transmission and is used in an algorithm to determine how long
each station must wait after Carrier Sense Off before
transmitting.
Control Byte - The control byte is used to identify the function
of a frame. There are two basic types of frames used in the
cluster, information frames and control frames. Information
frames are used to transfer information from one station to
another, and control frames are used to assure reliable transfer of
information across the cluster bus.
Cluster Adapter 25
The following types of frames are used by the DLCP:
Acknowledge (hex 10) Confirm receipt of a frame.
Initializing (hex 21) Indicates that the source station is
re-initializing. Existing connections to this station
should be cleared.
Virtual Disk (hex 82) Identifies that this frame contains a data
block and was transmitted as a result of the source
station issuing a Transmit Virtual Frame DLCP
command. One buffer is reserved for this frame.
Information (hex 83) Signifies the frame contains a data block and
was transmitted as a result of the source station
issuing a Transmit Frame DLCP command. There is a
first-in-first-out (FIFO) buffer set aside for this
frame.
Connect (hex 04) Establishes the virtual point-to-point
connection between a pair of stations.
Broadcast (hex 45) Signifies that the frame is a broadcast or
multicast frame.
Not Connected (hex 16) Indicates that the receiving station is not
connected to the sending station.
Frame Reject (hex 17) Sent by the receiving station when it has
received an information frame or a virtual disk frame
and the DLCP does not have buffer space available to
store the frame.
Bad Error (hex 18) Sent by the receiving station to indicate that a
frame is out of sequence.
Duplicate Address (hex 19) Sent by the receiving station in
response to an initializing control frame to indicate
that more than one station has the same address.
26 Cluster Adapter
Are You There? (hex lA) Sent to each station to poll for status in
the cluster. Each station that is on sends a response
to this query. An Acknowledge response frame is sent
by stations that are initialized. A Frame Reject
response is sent by stations that are not initialized.
Note: The most-significant four bits of the frame-control byte
have the following meaning:
Sequenced Information
Broadcast Information
Broadcast Control
Response
Bit
Bit
Bit
Bit
7
6
5
4
Frame Sequence Byte - If one of the acknowledge frames did
not reach the transmitting station, the frame sequence byte is used
to make sure that no duplicate information frames are received.
The least-significant four bits in the Cluster Status Entry are used
for maintaining a sequence number for transmitted and received
frames. The first two bits are used for the sequence number for
received frames. The two least-significant bits are used for the
sequence number for transmitted frames. The sequence numbers
are incremented each time a transmitting station sends an
information frame and each time the receiving station accepts an
information frame. If a mismatch occurs between the two
stations, the sender marks the destination station in the
disconnected state and sends a connect frame to try to reconnect
with the destination station. If the connection attempt is
successful, the frame is transmitted again.
Cluster Adapter 27
Byte Count - The byte count is the number of information bytes
to be transmitted. If the frame is a control frame, the byte count
is zero. There are two bytes allocated for the byte count.
Control CRC - A 16-bit cyclic redundancy check (eRe) is
calculated and appended to the end of the control block. A
hardware eRe generator is used. The receiving station compares
the control eRe received with the eRe calculated from the
received data and makes sure they are the same. If they are not
the same, the receiving station ignores the rest of the frame.
Data CRC - A 16-bit eRe is calculated and appended to the
end of the data block. The receiving station compares the data
eRe received with the eRe calculated from the received
information bytes and makes sure they are the same. If they are
not the same, the receiving station ignores the received frame.
Information Field
This field is for an information frame only. The information field
is absent in the control frames. The maximum number of
information bytes that can be transmitted in a frame is 578.
28 Cluster Adapter
Cluster Access Protocol
Collision avoidance is used with the Cluster Adapter. To avoid
collisions, each station waits a different amount of time after
'carrier sense' goes inactive before transmitting.
Stations get access to the cluster by timing from the end of the
current transmission (-Carrier Sense On-to-Off transition) until
its transmit time is reached, and then it may transmit. See also
"Collision Avoidance (Medium or High Activity)" on page 30.
Each station maintains two flags to determine that it is permitted
to transmit.
1. Synchronized Transmit Period.
2. Transmit Window.
The Synchronized Transmit Period is set and the Transmit
Window is cleared when the Carrier Sense Interrupt routine is
entered. Also, timer 0 is reloaded with the count corresponding
to this station's calculated Transmit Access Window. Timer 0
counts while 'carrier sense' is off and overflows when this
station's Transmit Access Window is reached. Timer O's overflow
causes an interrupt that sets the Transmit Window flag and then
reloads timer 0 with the count corresponding to the end of the
synchronized transmit period. When timer 0 interrupts again on
overflow, the Synchronized Transmit Period flag is reset to
indicate that the synchronized transmit period is finished.
Cluster Adapter 29
Collision Avoidance (Medium or High Activity)
The following shows the timing during medium or high activity in
the cluster:
Carrier
Sense
On
Off
l
1..._ _ _ _ _ _ _ _ __
I- TR --I
I-
1
I 2 I ...
163 I 64
I
--I
r- T2 ----i
r- T64 -------1
Synchronized
Transmit
Period
Transmit
Window
Slot 2
T1
On----------~L_
Off
On -------I
Off
30 Cluster Adapter
Collision Avoidance (Medium or High Activity)
TR=
T1 =
T2 =
Time allocated for a receiver to start transmitting a
response.
Time delay for 1st Transmit Access Window.
Time delay for 2nd Transmit Access Window.
Time delay for 64th Transmit Access Window.
T64 =
Station N's address with the bits in reverse order.
SN=
Token = Transmit Window Token which is decremented by 2
for each transmitted frame.
Delay time for Station N =
TR + «Token + SN) mod 128) x
transmit window12.
Notes:
1. TR is approximately 200
f.LS.
2. Transmit Access Window is approximately 40
f.LS.
A station must see its Transmit Window flag change from Off to
On before it is permitted to transmit. The case where it does not
see the change is covered in the next section.
Collision Avoidance (Light Activity)
If cluster activity is light (1480 f.LS average access time since the
previous transmission on the cluster) enough that the
Synchronized Transmit Period (STP) flag is reset, then
synchronization needs to be re-established to avoid collisions.
Cluster Adapter 31
The method used to re-establish synchronization is to transmit all
l's in the cluster for approximately 150 p,s and then to time the
carrier sense On-to-Off condition to this station's transmit slot
time. (See also "Collision Avoidance (Light Activity)" on page
33).
~ ---lI---------rulf··lJlJ
Transmit
Data
Transmit Frame
AlIl's
Carrier
Sense
~~f~
~ TR -11
I
I 2 I ... I 641
\-T1 -1
t- T2 -----I
r- T64
Synchronized
Transmit
Period
Transmit
Window
Slot 2
32 Cluster Adapter
On
Off
On
Off
--------I
L
Collision Avoidance (Light Activity)
TR=
T1 =
T2 =
Time allocated for a receiver to start transmitting a
response.
Time delay for 1st Transmit Access Window.
Time delay for 2nd Transmit Access Window.
T64 = Time delay for 64th Transmit Access Window.
Note: Average cluster access time is 1480 /LS if the cluster is
lightly loaded.
A station that is initializing waits the time of two complete
synchronization periods before sending its broadcast initializing
frame to allow it to become synchronized with the cluster. If no
frames are received in that time, it uses the procedure above to
establish a synchronized transmit period.
Frame Reception
The leading edge of the 'carrier sense' signal is used to interrupt
the 8031 Microcomputer. The 8031 interrupt service routine
updates its Transmit Window Token to the value transmitted with
the frame, and also sets the timer 0 counter to the calculated
Transmit Access Window based on the new token value. If the
frame is not addressed to this station, the DLCP ignores the rest
of the frame and leaves the interrupt routine.
If the frame is addressed to the station, the DLCP checks the
Cluster Adapter status to see if it can accept the frame. If this
station is not connected to the source station then a
not-connected control frame is transmitted to the source station.
If the frame is out of sequence, an bad error control frame is
transmitted to the source station.
If the DLCP can accept the frame, a check is made that a receive
buffer is available. If a buffer cannot be obtained, a frame- reject
control frame is sent back to the transmitting station. This
indicates that the frame cannot be accepted at this time and
another attempt should be made. If the frame is received
Cluster Adapter 33
correctly, DLCP transmits an Acknowledge frame to the
transmitting station and return the control to the interrupted 8031
program.
Error Detection and Recovery
The DLCP can detect various cluster errors and tries to recover
from them. If it is not able to recover after a specified number of
retries, it notifies the calling program with the returned error
code. The list of errors that can be detected is in the figure
below:
Type of Error
Cluster Busy Timeout
Action Taken
Report Error
Retry Count
N/A
(Seconds)
1.0
Cluster Access Timeout
Report Error
N/A
13.0
No Response
Retransmit Frame
8
0.20
Frame Reject
Retransmit Frame
after Delay
1
2
3
4
5
6
7
0.24
0.09
0.16
0.25
0.36
0.49
0.64
Not Connected or Bad
Error
Transmit Connect
Control Frame and
If Successful
Retransmit Frame
N/A
N/A
Command Timeout
Reset Adapter and
Report Error
N/A
120.0
Detectable Errors and Recovery
34 Cluster Adapter
After correctly receiving a control frame or an information frame,
the receiving station sends a response frame. If all receive buffers
are in use, a Frame Reject response frame is transmitted. If the
frame is out of sequence, a Bad Error response frame is
transmitted.
If the transmitting station did not get a confirmation of receipt
after a certain time period, it assumes that the receiving station
never got the frame and it transmits the same frame again. If the
transmitting station still does not get a reply after eight retries, it
assumes that the receiving station is not available and resets the
Connected bit in the corresponding Cluster Adapter status entry.
Cluster Status Table
The DLCP keeps track of the status and sequence numbers for
connection with stations through 63 in the Cluster Table in the
Cluster Adapter's RAM space. Offset in the Cluster Table
corresponds to the status for connection to station 0, offset 1 for
station 1, and so on. The offset corresponding to a station's own
address is used to store a duplicate-station address indicator.
°
°
Cluster Adapter 35
The bits for each Cluster Status Table byte are designated in the
following chart:
Cluster Status Entry (1 Byte)
= Connected
C
7
1
RBl
6
Response 10
RBO
5
Response 10
F'
4
1
RS1
3
Received Frame Sequence
RSO
2
Received Frame Sequence
TS1
1
Transmitted Frame Sequence
TSO
0
Transmitted Frame Sequence
= Response Pending
Cluster Status Table Entry
Bit 7-
Connected (C) is set to 1 when your station has
sent a connect frame and an acknowledge frame
has been received, or when a connect frame has
been received and an acknowledge has been sent.
Connected is reset when a not-connected, bad
error, or initializing control frame is received.
Bit 6, 5 -
Response ID
The following table defines the meaning of these
two bits:
Bit 6
RB1
Bit 5
RBO
0
0
Acknowledge
0
1
Frame Reject
1
0
Not Connected
Type of Response
Response 10 in Cluster Table Status Entry
36 Cluster Adapter
Bit 4 -
Pending (P) is set to 1 by the transmitting station to
indicate that it is waiting for an acknowledge frame
from the destination station, and is reset by the
interrupt handler when a response is received or upon
a time-out.
Bit 3, 2 -
Received Frames Sequence Number is incremented
every time a new data-sequenced information frame is
successfully received. This sequence number and the
transmitted frame sequence number are reset to 0
when a connection is established between two
stations.
Bit 1, 0 -
Transmitted Frames Sequence Number is incremented
every time a sequenced information frame is
successfully transmitted; that is, an acknowledge is
received from the destination station.
Remote IPL
A vector is established at bootstrap vector INT hex 19 to the
Remote System Reset Program Loader for the cluster, which is
located in adapter 1's ROM. The original contents of the
bootstrap vector are stored at vector INT hex SB. The disk server
station address is stored at the least-significant byte of vector INT
hex El. The number of the adapter from which to IPL is stored
at the word corresponding to the segment at vector INT hex El.
Cluster Adapter 37
The following actions are performed by the Remote System Reset
Program Loader:
1. The Remote System Reset Program Loader (in the Cluster
Adapter's 8088 accessible ROM) uses a portion of the top lK
bytes of memory for variable and buffer space.
2. The bootstrap vector is restored with its original vector (which
was temporarily saved at INT hex SB). The INT hex SB
vector is set to point to the adapter's diagnostic routines.
3. The variables of DLCP are initialized by executing a DLCP
BIOS Cluster Initialization command (hex 00) with
parameters provided by a table of constants in the adapter's
8088 ROM.
4. The user timer-interrupt vector at vector hex 1C is saved at
interrupt vector hex E2 and replaced with the address of a
routine to update a timer count variable used for time-outs by
the Remote System Reset Program Loader. It is restored
before this routine is left.
S. A broadcast frame requesting IPL is sent using the DLCP
BIOS command's Transmit Broadcast Frame (hex 08) to all
stations in the cluster. The format of the data portion of the
frame is:
Command =
Session ID =
38 Cluster Adapter
hex 91
hex 0000
(Request for IPL)
(2 bytes)
6. An acknowledge information frame is expected with the
following data:
Command =
Session ID =
Status =
hex 92
hex xxxx
hex 00
(Response to IPL request)
(2 bytes)
(non-zero is irrecoverable error)
xxxx = any hexidecimal number
The server station's address is saved at the least-significant
byte of vector INT hex E 1.
Up to eight retries are made unless a response from the disk
server station is received. Approximately 4 seconds are
allowed between retries. After the eight retries have been
used, the user timer-interrupt vector is restored and then
control is passed to the bootstrap routine.
Note: If a Keep-Alive command is received from the disk
server station, an additional 30 seconds is allowed.
7. Next, the Remote IPL program requests a data block
containing program code from the disk server station. The
request has the following form:
Command =
Session ID =
Status =
hex 93
hex xxxx
hex 00
Request IPL data block
(2 bytes)
(Non-zero is a irrecoverable
error)
xxxx = any hexidecimal number
The request is sent using the DLCP BIOS command's
Transmit Frame (hex 03). Retries are made for up to 20
seconds if the return code indicates a Frame Reject or a No
Response error.
Cluster Adapter 39
8. The disk server sends a response containing the next data
block. The response has the following form:
Command =
hex 94
Session ID =
Status =
hex xxxx
hex 00
Sector # =
Data Block =
hex xxxx
[0-512 bytes]
Response with IPL data
block
(2 bytes)
(N on-zero is a irrecoverable
error)
Relative sector number
Data Block containing
program code.
xxxx = any hexidecimal number
The DLCP BIOS Receive Frame command (hex 02) is issued
to read the response frame containing the block of program
code. Approximately 20 seconds are allowed to receive a
valid response from the disk server station. If a Keep-Alive
command is received from the disk server station, an
additional 30 seconds are allowed. There is no limit to the
number of Keep-Alive commands that are accepted. On
time-out, the user timer-interrupt vector is restored and
control is passed to the Bootstrap Loader by INT hex 19.
The received sector number must start at zero and increment
for each block of program code received. If the received
sector number is incorrect or if the status is non-zero, then the
user timer-interrupt vector is restored and control is passed to
the bootstrap vector by INT hex 19. The sector number is
two bytes long with the least-significant byte first in the
received data.
40 Cluster Adapter
The received program code is inserted in memory starting at
location hex 07CO:0000 and continuing upward. The end of
the program code is determined when a frame is received that
does not contain 512 bytes of program code.
9. The above two steps are repeated until the end of the program
code is received. The user timer-interrupt vector is restored
and control passes to the loaded program by a jump to hex
07CO:0000.
Notes:
1. The Remote IPL function is performed, even if local drives are
attached, if the Remote IPL switch on Cluster Adapter 1 is
On. Remote IPL is supported only for Cluster Adapter 1.
The Remote IPL function can be stopped by pressing Control
Break, and normal loading from local diskette drives occurs.
2. For every block of data received, an arrow rotates in a
clockwise direction on the screen.
3. After power on or system reset, the cursor is moved to the
right three columns for about 1 second. Special ROM
diagnostic tests for the adapter can be executed by
immediately pressing" Ctrl D" on the keyboard. Also, a
request to load a general diagnostic program over the cluster
can be selected by pressing "Ctrl L" at which time a blinking
L is displayed. The adapter sends out a broadcast frame
requesting a diagnostic program load. (The first data byte of
the request frame is set to hex 90.)
Cluster Adapter 41
DLCP BIOS Commands
The DLCP BIOS commands are issued by the higher layer
communication program to send and receive information through
the cluster. The following are the DLCP BIOS commands:
Command Number (Hex)
Command Name
00
Cluster Initialization
01
Receive Virtual Frame
02
Receive Frame
03
Transmit Frame
04
Reserved
05
Display CI uster Status
06
Cluster Status
07
Status
08
Broadcast Frame
09
Transmit Virtual Frame
OA
Stop DLCP
OB
Read Station Address
OC
Set Multicast Address
OD
Check Command In Progress
OE
Read IPL Switch
OF
Start DLCP
10
Dump Statistics
11
Diagnostic Function 1
12
Diagnostic Function 2
13
Diagnostic Function 3
14
Diagnostic Function 4
15
Diagnostic Function 5
16
Diagnostic Function 6
17
Diagnostic Function 7
DLCP BIOS Commands
42 Cluster Adapter
DLCP Return Codes
The following table indicates the Return Codes that are defined
for the cluster DLCP:
DLCP Return Codes
Return Code
Hex 00
Hex 30
Meaning
Successful Completion
Initialization failed
Hex 31
Cluster busy timeout (carrier sense
active for 2 seconds)
Hex 32
Duplicate station address on cluster
Hex 33
Hex 34
Hex 35
No response from destination
Frame rejected at destination
Hex 36
Cluster access timeout (could not gain
access to cluster within a 13 second timeout)
Information field too long (more than
578 bytes)
Hex 37
Hex 38
Reserved
Hex 39
Information field empty
DLCP command in progress
Hex 3A
Initialization required
Hex 3B
Received frame not available
Hex 3C
Error detected with 8031 (due to command
timeout or other processor interface error
Extended return code in cluster status field
Invalid initialization parameters (too many
or too large buffers specified)
Hex 3D
Hex 3E
Hex 3F
Previous DLCP BIOS command initiated
with Initiate Transmit bit set is not complete
Cluster DLCP Return Codes
Note: A return code of hex 00 indicates successful completion
of the DLCP BIOS command. Most of the other return codes
indicate error conditions.
Cluster Adapter 43
Cluster Initialization (DLCP) = Hex 00
Function:
This command initializes the DLCP and also transmits
an initializing frame to inform others in the cluster. If
another station in the cluster has the same address as
this station, it sends a response frame indicating
duplicate station address, and the return code is hex
32. The Initialization Control Block (ICB) must be
built by the calling program with the initialization
values indicated by the following:
Return Code
Definition
hex 00
hex 30
hex 32
hex 39
hex 3C
hex 3E
Successful completion
Initialization failed
Duplicate station address in the cluster
Command in progress
Error with 8031
Invalid initialization parameters
Link Control Block (LCB)
Field
Value at Entry
Value at Exit
Destination
Don't Care
Unchanged
Source
Don't Care
Unchanged
Command
=00 (Hex)
=OF (Hex)
Unchanged
Buffer 1 Address
Address of Initialization
Control Block (ICB)
Unchanged
Buffer 2 Length
Don't Care
Unchanged
Buffer 2 Address
Don't Care
Unchanged
Buffer 1 Length
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
Unchanged
Select Adapter
=0 for Adapter 1
= 1 for Adapter 2
=2 for Adapter 3
=3 for Adapter 4
Unchanged
Cluster Initialization (DlCP) = Hex 00
44 Cluster Adapter
Initialization Control Block (lCB)
The calling program must set the buffer 1 address field in the
LCB to the address of an initialization control block (ICB). The
figure below shows the composition and bytes that make up the
ICB:
Byte
Byte Definition
o
(Bits)
7
6
5 4
3
2
1
0
NVB
MM1
MM2
(Value) 0
0
0
0
0
Number of Large Buffers
Number of Small Buffers
Large Buffer Size
Small Buffer Size
Maximum Number of Retries for No Response
Maximum Number of Retries for Rejected Frame
Transmit Access Window (TAW)
Time Period Reserved for Response
Time from Frame Start to First Byte
Time Between Control Field and Data Field
Timeout Waiting for Response to be Received
Timeout Waiting for Next Byte to be Received
Timeout Waiting for Command to Complete
Timeout Waiting to Access Cluster
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Value
o
4
10
584 -0- 8
40
8
2
40 -0- 2
200
150
100
300
300
7
200
-0-0-0-0-0-
20
2
2
6
6
Initialization Control Block (ICB)
Cluster Adapter 45
Byte 0 -
Bits 7,6,5,4, and 3 are reserved and must be set to O.
Bit 2 - No Virtual Buffer (NVB), when set to zero,
allocates a receive buffer for Virtual Frames.
Bit 1 and 0 - These bits are set to enable the first
portion of all frames to be received (even if they are
not addressed to this station).
The following figure shows the Monitor Mode (MM)
bit definitions:
MM1
MMO
Monitor Mode Condition
0
0
Normal Mode
0
1
Receives All Frames on Cluster
1
0
Invalid Setting
1
1
Receives Only Frames from or to Multicast
Address or This Station Address
Monitor Mode Bit Definitions
Note: In Monitor Mode, only the first portion of a frame (up
to the size of the small buffer minus 7 bytes) is received. The
first byte is set to the value of Transmit Window Token, and
the second byte corresponds to the first data byte of the
information field of the frame.
46 Cluster Adapter
Byte 1 -
This byte indicates the number of large buffers
allocated in the 8031 RAM for incoming frames.
Byte 2-
This byte indicates the number of small buffers
allocated in the 8031 RAM for incoming frames.
Byte 3 -
This byte indicates the large buffer size (each unit
represents 8 bytes). Six bytes of the large buffer are
reserved for control information.
Byte 4-
This byte indicates the small buffer size (each unit
represents 1 byte). Six bytes of the small buffer are
reserved for control information.
Byte 5 -
This byte indicates the maximum number of times a
frame is transmitted with no response from the
destination station.
Byte 7 -
This byte is used to specify the Transmit Access
Window (TAW) time period in f.LS. For a 40 f.LS
TAW, set this byte to 20. After every transmitted
frame, an Access Time Period is allocated, which is
64 times the TAW time period.
Byte 8-
The value of this byte times TAW divided by 2
equals the amount of time (f.Ls.) reserved after each
frame for a response frame to be transmitted.
Cluster Adapter 47
Byte 9 -
The value of this byte times 2 equals the delay in p,s
after the start of a transmit frame before the first
byte (destination) is transmitted.
Byte 10 -
The value of this byte times 2 equals the delay in p,s
between the control field and data field of a frame.
Byte 11 -
The value of this byte times 6 equals the time
allowed in p,s for a response frame to be received.
Byte 12 -
The value of this byte times 6 equals the time
allowed in p,s for the next byte of a frame to be
received.
Byte 13 -
The value of this byte times 16.7 equals the number
of seconds allowed for any command in progress to
finish before the 8031 indicates error hex 3C to the
Cluster Adapter BIOS code.
Byte 14 -
The value of this byte times 67 milliseconds equals
the amount of time allowed waiting to access the
cluster before error hex 36 is returned.
48 Cluster Adapter
Receive Virtual Frame
Function:
=
Hex 01
This command is used to retrieve a data frame sent by
the disk server (using Transmit Virtual Frame).
Notes:
1. There is only one virtual frame buffer for this type of data
frame.
2. The destination, command, and cluster status fields in the
LCB are modified.
Return Code
Destination
hex
hex
hex
hex
hex
hex
hex
hex
Successful completion
Duplicate station address in the cluster
Information field too long
No information field present
Command in progress
Initialization required
No receive frame exists
Error detected with 8031
00
32
37
38
39
3A
3B
3C
Cluster Adapter 49
Link Control Block (LCB)
Field
Value at Entry
Value at Exit
Destination
Don't Care
Destination
Source
Don't Care
Source
Command
= 01 (Hex)
Frame Control
Buffer 1 Length
Length of Calling
Program's Buffer 1
Length of Received Data if
Less Tha n Buffer 1 Le ngth
Buffer 1 Address
Points to Calling
Program's Buffer 1
Unchanged
Buffer 2 Length
Length of Ca II i ng
Program's Buffer 2
Length of Received Data
Placed in This Buffer
Buffer 2 Address
Points to Calling
Program's Buffer 2
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
Frame Sequence
Select Adapter
= 0 for Adapter 1
Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4
Receive Virtual I/O Frame
50 Cluster Adapter
Hex 01
Receive Frame (from FIFO queue) = Hex 02
Function:
This command is used to retrieve a data frame sent
from another station (using Transmit Frame) from the
First-In-First-Out (FIFO) queue.
The FIFO queue can contain four full size frames and
10 small frames.
Note: The field's destination, command, and cluster status in
the LCB are modified.
Note: If the adapter is in Monitor mode, the first byte
returned is the Transmit Window Token. The second byte is
the first data byte of the information field of the received
frame.
Return Code
Definition
hex 00
hex 32
hex 37
hex 38
hex 39
hex 3A
hex 3B
hex 3C
Successful completion
Duplicate station address in the cluster
Information field too long
No information field present
Command in progress
Initialization required
No receive frame exists
Error detected with 8031
Cluster Adapter 51
Link Control Block (LCB)
Field
Value at Exit
Value at Entry
Desti nation
Don't Care
Destination
Source
Don't Care
Source
Command
= 02
Frame Control
Buffer 1 Length
Length of Calling
Program's Buffer 1
Length of Received Data if
Less Than Buffer 1 Length
Buffer 1 Address
Points to Calling
Program's Buffer 1
Unchanged
Buffer 2 Length
Length of Calling
Program's Buffer 2
Length of Received Data
Placed in This Buffer
Buffer 2 Address
Points to Calling
Program's Buffer 2
Unchanged
Return Code
Don't Care
Set to Return Code
CI uster Status
Don't Care
Frame Sequence
Select Adapter
= 0 for Adapter 1
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4
Unchanged
(Hex)
Receive Frame (from FIFO Queue)
52 Cluster Adapter
Hex 02
Transmit Frame
Function:
= Hex 03
This command is used to transmit a data frame to
another station where it can be retrieved by using the
Receive Frame command.
Note: See also "Special Transmit Mode Command Bits" on
page 81
Return Code
Definition
hex
hex
hex
hex
hex
00
31
32
33
34
Successful completion
Cluster always busy
Duplicate station address in the cluster
No response from destination
Exceed allowed number of rejected frames
hex 36
hex 37
Cluster access time-out
Information field too long (frame is not
sent)
No information field present (frame is not
sent)
Command in progress
Initialization required
Error detected with 8031
hex 38
hex 39
hex 3A
hex 3C
Cluster Adapter 53
Link Control Block (LCB)
Field
Destination
Value at Entry
Value at Exit
Destination
Unchanged
Source
Don't Care
Unchanged
Command
=03 (Hex)
Unchanged
Buffer 1 Length
Length of Calling
Program's Buffer 1
Unchanged
Buffer 1 Address
Points to Calling
Program's Buffer 1
Unchanged
Buffer 2 Length
Length of Calling
Program's Buffer 2
Unchanged
Buffer 2 Address
Points to Calling
Program's Buffer 2
Unchanged
Return Code
Don't Care
Set to Return Code
CI uster Status
Don't Care
Unchanged
Select Adapter
=
=
=
=
0 for
1 for
2 for
3 for
Transmit Frame = Hex 03
54 Cluster Adapter
Adapter
Adapter
Adapter
Adapter
1
2
3
4
Unchanged
Display Cluster Status = Hex 05
Function:
This command is used to determine and then display
the cluster status. The On/Off status of 64 stations is
displayed. Stations that have the Power switch set to
On are displayed in reverse video. Your station is
displayed in reverse video and blinking. If another
station in the cluster has the same address as your
station, a long beep sounds. Only those stations that
are initialized can be displayed.
Note: The screen should be cleared before issuing this
command.
Note: Type of status (destination field):
hex 00 =
report stations that are On
hex FF =
report stations that are initialized
Return Code
Definition
hex
hex
hex
hex
hex
Successful completion
Cluster always busy
Cluster access time-out
Command in progress
Error detected with 8031
00
31
36
39
3C
Cluster Adapter 55
Link Control Block (LCB)
Field
Value at Entry
Value at Exit
Destination
Type of Status
Unchanged
Source
Don't Care
Unchanged
Command
= 05 (Hex)
Unchanged
Buffer 1 Length
Number of Stations
to Display
Unchanged
Buffer 1 Address
Don't Care
Unchanged
Buffer 2 Length
Don't Care
Unchanged
Buffer 2 Address
Don't Care
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
Extended Return Code on
Error
Select Adapter
=
=
=
=
0
1
2
3
for
for
for
for
Adapter
Adapter
Adapter
Adapter
Display Cluster Status = Hex 05
56 Cluster Adapter
1
2
3
4
Unchanged
This page explains the cluster status that may appear on your
screen.
NN is any station address from 0 to 63.
The station you are using is indicated on the screen
in blinking reverse video, and the box is marked by
two asterisks.
Stations that have their Power switches set to On
are displayed in reverse video, and their boxes are
marked by two Xs.
Another station has the same address as your
station; a long beep sounds every 3 seconds, the
box is displayed in blinking reverse video, and is
marked by an X and an asterisk.
A station address not in the cluster is indicated by a
box displayed in normal video and not marked with
XS or asterisks.
Cluster Adapter 57
Cluster Status = Hex 06
Function:
This command determines the stations' OnlOff
status. The status bytes are stored in buffer 1 (as
determined by the buffer 1 pointer in the LCB). The
first byte's least-significant bit is the status of station
O. Bit 1 represents station 1. The least-significant bit
of the second byte is the status of station 8, and so on.
The number of stations checked is a parameter of this
command. Only those stations that are initialized are
reported.
Notes:
1. Type of status (destination field):
hex 00 = report stations that are On
hex FF = report stations initialized
2. See also "Special Transmit Mode Command Bits" on page 81
3. The size of the buffer required to store the cluster status bytes
is (number of stations to check + 7)-;.-8.
Return Code
Definition
hex
hex
hex
hex
hex
Successful completion
Cluster always busy
Cluster access time-out
Command in progress
Error detected with 8031
00
31
36
39
3C
58 Cluster Adapter
Link Control Block (LCB)
Field
Value at Entry
Value at Exit
Destination
Type of Status
Unchanged
Source
Don't Care
Unchanged
Command
= 06 (Hex)
Unchanged
Buffer 1 Length
N umber of Stations
to Check
Unchanged
Buffer 1 Address
Points to Calling
Program's Buffer 1
Unchanged
Buffer 2 Length
Don't Care
Unchanged
Buffer 2 Address
Don't Care
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
Extended Return Code
on Error
Select Adapter
= 0 for Adapter 1
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4
Unchanged
Cluster Status
Hex06
Cluster Adapter 59
Status - Hex 07
This command is used to return the status of the
connection with a particular station,
Function:
Return Code
Definition
hex 00
hex 39
hex 3C
Successful completion
Command in progress
Error detected with 8031
Link Control Block (LCB)
Field
Value at Entry
Value at Exit
Desti nation
Stations for Wh ich
Status is Desired
Unchanged
Source
Don't Care
Unchanged
Command
= 07
(Hex)
Unchanged
Buffer 1 Length
Don't Care
Unchanged
Buffer 1 Address
Don't Care
Unchanged
Buffer 2 Length
Don't Care
Unchanged
Buffer 2 Address
Don't Care
Unchanged
Return Code
Don't Care
Set to Return Code
CI uster Status
Don't Care
Cluster Status
Select Adapter
= 0 for Adapter 1
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4
Unchanged
Status
=
Hex 07
60 Cluster Adapter
Transmit Broadcast Frame = Hex 08
Function:
This command is used to transmit a data frame to
another station where it can be retrieved by using the
Receive Frame command. No acknowledgment to the
frame is sent by the receiving stations.
Note: Transmit Frame and Transmit Virtual Frames are
converted to Broadcast Frames if the destination station
number is greater than 127.
Note: See also "Special Transmit Mode Command Bits" on
page 81..
Return Code
Definition
hex
hex
hex
hex
hex
Successful completion
Cluster always busy
Duplicate station address in cluster
Cluster access time-out
Information field too long (frame is not
sent)
No information field present (frame is not
sent)
Command in progress
Initialization required
Error detected with 8031
00
31
32
36
37
hex 38
hex 39
hex 3A
hex 3C
Cluster Adapter 61
Link Control Block (LCB)
Field
Destination
Value at Entry
Destination
Value at Exit
Unchanged
Source
Don't Care
Unchanged
Command
= 08 (Hex)
Unchanged
Buffer 1 Length
Length of Calling
Program's Buffer 1
Unchanged
Buffer 1 Address
Points to Calling
Program's Buffer 1
Unchanged
Buffer 2 Length
Length of Calling
Program's Buffer 2
Unchanged
Buffer 2 Address
Points to Calling
Program's Buffer 2
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
Unchanged
Select Adapter
= 0 for Adapter 1
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4
Unchanged
Transmit Broadcast Frame
62 Cluster Adapter
Hex 08
Transmit Virtual Frame
Function:
= Hex 09
This command is used to transmit a data frame
containing sector information from the disk server
station. The information can be retrieved only by
using the Receive Virtual Frame command.
Note: See "Special Transmit Mode Command Bits" on page
81
Return Code
Definition
hex
hex
hex
hex
hex
Successful completion
Cluster always busy
Duplicate station address in cluster
No response from destination
Frame rejected at destination
00
31
32
33
34
hex 36
hex 37
hex 38
hex 39
hex3A
hex 3C
Cluster access time-out
Information field too long (frame is not
sent)
No information field present (frame is not
sent)
Command in progress
Initialization required
Error detected with 8031
Cluster Adapter 63
link Control Block (LCB)
Field
Destination
Value at Entry
Value at Exit
Desti nation
Unchanged
Source
Don't Care
Unchanged
Command
= 09 (Hex)
Unchanged
Buffer 1 Length
Length of Calling
Program's Buffer 1
Unchanged
Buffer 1 Address
Points to Calling
Program's Buffer 1
Unchanged
Buffer 2 Length
Length of Calling
Program's Buffer 2
Unchanged
B uffe r 2 Add ress
Points to Calling
Program's Buffer 2
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
Select Adapter
=
=
=
=
0
1
2
3
for
for
for
for
Transmit Virtual Disk Frame
64 Cluster Adapter
Unchanged
Adapter
Adapter
Adapter
Adapter
1
2
3
4
Hex 09
Unchanged
Stop DLCP = Hex OA
Function:
This command is used to temporarily inhibit the
DLCP from receiving or transmitting frames. Issue a
Start DLCP command to leave the stopped state.
Return Code
Definition
hex
hex
hex
hex
Successful completion
Command in progress
Initialization required
Error detected with 8031
00
39
3A
3C
Link Control Block (LCB)
Field
Value at Entry
Destination
Don't Care
Value at Exit
Unchanged
Source
Don't Care
UnChanged
Command
= OA (Hex)
Unchanged
Buffer 1 Length
Don't Care
Unchanged
Buffer 1 Address
Don't Care
Unchanged
Buffer 2 Length
Don't Care
Unchanged
Buffer 2 Address
Dont' Care
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
Unchanged
Select Adapter
= 0 for Adapter 1
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4
Unchanged
Stop DlCP
=
Hex OA
Cluster Adapter 65
Read Station Address = Hex OB
Function:
This command is used to return the address and state
of the remote IPL switch of this station.
Return Code
Definition
hex 00
hex 39
hex3C
Successful completion
Command in progress
Error detected with 8031
Link Control Block (LCB)
Field
Destination
Value at Exit
Value at Entry
Don't Care
Unchanged
Source
Don't Care
This station's address
Command
=OB (Hex)
Unchanged
Buffer 1 Length
Don't Care
Unchanged
Buffer 1 Address
Don't Care
Unchanged
Buffer 2 Length
Don't Care
Unchanged
Buffer 2 Address
Don't Care
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
00 = No IPL FF = IPL
Select Adapter
=
=
=
=
0
1
2
3
Read Address = Hex 08
66 Cluster Adapter
for Adapter
for Adapter
for Adapter
for Adapter
1
2
3
4
Unchanged
Set Multicast Address
Function:
= Hex OC
This command is used to set the desired multicast
address. The multicast address is a variation of the
broadcast address (hex FF). More than one station
may be assigned the same multicast address. A
default value of hex FF is set when a cluster
Initialization command is issued to the DLCP. A
frame sent, using the Transmit Broadcast Frame
command (8), to the group multicast address is
received by all stations that share the multicast
address.
Return Code
Definition
hex 00
hex 39
hex 3C
Successful completion
Command in progress
Error detected with 8031
Link Control Block (lCB)
Field
Destination
Value at Entry
Desired Multicast
Address
Value at Exit
Unchanged
Source
Don't Care
Unchanged
Command
= OC (Hex)
Unchanged
Buffer 1 length
Don't Care
Unchanged
Buffer 1 Address
Don't Care
Unchanged
Buffer 2 length
Don't Care
Unchanged
Buffer 2 Address
Don't Care
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
Unchanged
Select Adapter
= 0 for Adapter 1
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4
Unchanged
Set Multicast Address = Hex DC
Cluster Adapter 67
Check Inside DLCP Flag = Hex on
Function:
This command is used to return an indication that a
DLCP command is already in progress. This
command is necessary orily for programs that call
DLCP from inside an interrupt routine. If a DLCP
command is already in progress, the interrupt routine
should return to the interrupted program to allow the
current DLCP command to finish.
Return Code
Definition
hex 00
hex 39
hex 3C
Command not in progress
Command in progress
Error detected with 8031
Link Control Block (LeB)
Field
Oes~ination
Value at Exit
Value at Entry
Don't Care
Unchanged
Source
Don't Care
Unchanged
Command
= 00 (Hex)
Unchanged
Buffer 1 Length
Don't Care
Unchanged
Buffer 1 Address
Don't Care
Unchanged
Buffer 2 Length
Don't Care
Unchanged
Buffer 2 Address
Don't Care
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
Unchanged
Select Adapter
=
=
=
=
0 for Adapter
1 for Adapter
2 for Adapter
3 for Adapter
Check Inside DLCP Flag = Hex 00
68 Cluster Adapter
1
2
3
4
Unchanged
Read IPL Switch = Hex OE
Function:
This command is used to read the state of the Remote
IPL switch on the requesting station.
Return Code
Definition
hex 00
hex 39
hex 3C
Successful completion
Command in progress
Error detected with 8031
Link Control Block (LCB)
Field
Value at Entry
Value at Exit
Desti nation
Don't Care
Unchanged
Source
Don't Care
This station's address
Command
= OE (Hex)
Unchanged
Buffer 1 Le ngth
Don't Care
Unchanged
Buffer 1 Address
Don't Care
Unchanged
Buffer 2 Length
Don't Care
Unchanged
Buffer 2 Address
Don't Care
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
IPL Switch (00
FF = IPL)
Select Adapter
= 0 for Adapter 1
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4
Unchanged
= No
IPL
Read IPL Switch = Hex OE
Cluster Adapter 69
Start DLCP = Hex OF
Function:
This command is used to release the DLCP from the
stopped state. It enables the DLCP to receive and
transmit frames.
Return Code
Definition
hex 00
hex 39
hex 3A
hex 3C
Successful completion
Command in progress
Initialization required
Error detected with 8031
Link Control Block (LCB)
Field
Value at Entry
Destination
Value at Exit
Don't Care
Unchanged
Source
Don't Care
Unchanged
Command
= OF (Hex)
Unchanged
Buffer 1 Length
Don't Care
Unchanged
Buffer 1 Address
Don't Care
Unchanged
Buffer 2 Length
Don't Care
Unchanged
Buffer 2 Add ress
Don't Care
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
Unchanged
Select Adapter
= 0 for Adapter 1
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4
Unchanged
Start DLCP
= Hex OF
70 Cluster Adapter
Dump Statistics
Function:
= Hex 10
This command is used to transfer the current
communication statistics block from the adapter.
Link Control Block (LCB)
Field
Destination
Value at Entry
Value at Exit
Don't Care
Unchanged
Source
Don't Care
Unchanged
Command
= 10 (Hex)
Unchanged
Buffer 1 Length
12 bytes
Unchanged
Buffer 1 Address
Points to Calling
Program's Buffer 1
Unchanged
Buffer 2 Length
Don't Care
Unchanged
Buffer 2 Address
Don't Care
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
Unchanged
Select Adapter
= 0 for Adapter 1
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4
Unchanged
Dump Statistics
= Hex 10
Cluster Adapter 71
Communication Statistics Block (CSB)
The Cluster Adapter returns information regarding previous
activity in the CSB.
Return Code
Definition
hex 00
Successful completion
Command in progress
Error detected with 8031
hex 39
hex 3C
The figure below shows the composition and definition of the
CSB bytes:
Byte
Definition
0
Number of Times No Response Received (LSB)
1
Number of Times No Response Received (MSB)
2
Number of Times Frame Rejects Received
3
Number of Control Frames Correctly Received (LSB)
4
Number of Control Frames Correctly Received (MSB)
5
Number of Data Frames Correctly Received (LSB)
6
Number of Data Frames Correctly Received (MSB)
7
Number of Control Frames with CRC Error
8
Number of Data Frames with CRC Error
9
Number of Duplicate Frames Received
10
Number of Received Frames That Were Rejected
11
Number of Transmit Collisions
Communication Statistic Block
72 Cluster Adapter
Diagnostic Function 1 = Hex 11
Function:
This command is used to run an internal diagnostic
test.
(Reserved for diagnostic use only.)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Test adapter processor-to-processor interface
Reserved
Test driver and receiver logic (terminating plug required
for diagnostic use)
Test interrupt logic (set transmit interrupt status bit)
Test interrupt logic (set receive interrupt status bit)
Clear transmit and receive interrupt status bits (no
interrupt)
Set transmit and receive interrupt status bits (no
interrupt)
Return Code
Definition
hex 00
hex 39
hex 3C
hex 3D
Successful completion
Command in progress
Error detected with 8031
Error detected by 8031 diagnostic test
(reason for error in Cluster Status field)
Cluster Adapter 73
Link Control Block (LCB)
Field
Destination
Value at Exit
Value at Entry
Test Number **
Unchanged
Source
Don't Care
Unchanged
Command
= 11
(Hex)
Unchanged
Buffer 1 Length
Don't Care
Unchanged
Buffer 1 Address
Don't Care
Unchanged
Buffer 2 Length
Don't Care
Unchanged
Buffer 2 Address
Don't Care
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
Extended Return Code
Select Adapter
= 0 for Adapter 1
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4
Unchanged
Diagnostic Function 1 = Hex 11
Note:
** Test number (Destination field)
74 Cluster Adapter
Diagnostic Function 2
Function:
= Hex 12
This command is used to transfer data to the adapter's
RAM from a buffer in system memory. The data in
buffer 1 is transferred to the address specified by
buffer 2 in the 8031 address space.
(Reserved for diagnostic use only.)
Return Code
Definition
hex 00
hex 39
hex 3C
Successful completion
Command in progress
Error detected with 8031
Link Control Block (LCB)
Field
Destination
Value at Entry
Value at Exit
Don't Care
Unchanged
Source
Don't Care
Unchanged
Command
= 12 (Hex)
Unchanged
Buffer 1 Length
Length of Calling
Program's Buffer 1
Unchanged
Buffer 1 Address
Poi nts to Buffer 1
Unchanged
Buffer 2 Length
Don't Care
Unchanged
Buffer 2 Address
Set Offset to Address
in 8031 RAM Space
to Place Data
Unchanged
Return Code
Don't Care
Set to Ret u rn Code
Cluster Status
Don't Care
Unchanged
Select Adapter
= 0 for Adapter 1
Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4
Diagnostic Function 2
= Hex 12
Cluster Adapter 75
Diagnostic Function 3
Function:
= Hex 13
This command is used to transfer data from the
adapter's RAM to a buffer in system memory. The
data is transferred starting at the address specified by
the buffer 2 address (offset) in 8031 memory to
buffer 1 in the main system's memory.
(Reserved for diagnostic use only.)
Return Code
Definition
hex 00
hex 39
hex 3C
Successful completion
Command in progress
Error detected with 8031
Link Control Block (LCB)
Field
Value at Entry
Value at Exit
Destination
Don't Care
Unchanged
Source
Don't Care
Unchanged
Command
= 13 (Hex)
Unchanged
Buffer 1 Length
Length of Calling
Program's Buffer 1
Unchanged
Buffer 1 Address
Poi nts to Buffer 1
Unchanged
Buffer 2 Lerigth
Don't Care
Unchanged
Buffer 2 Address
Set Offset to Address
in 8031 RAM Space
from Which to get
Data
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
Unchanged
Select Adapter
= 0 for Adapter 1
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4
Unchanged
Diagnostic Function 3 = Hex 13
76 Cluster Adapter
Diagnostic Function 4 = Hex 14
Function:
This command is used to transfer data to the 8031 's
internal RAM from a buffer in system memory. The
data in buffer 1 is transferred to the address specified
by buffer 2 address in 8031 memory.
(Reserved for diagnostic use only.)
Note: Extreme care must be used to prevent destroying data
in the 8031 's stack and registers in this internal chip RAM.
Also, there are only 128 bytes of RAM.
Return Code
Definition
hex 00
hex 39
hex 3C
Successful completion
Command in progress
Error detected with 8031
Link Control Block (lCB)
Field
Value at Entry
Value at Exit
Desti nat ion
Don't Care
Unchanged
Source
Don't Care
Unchanged
Unchanged
Command
=
Buffer 1 Length
Length of Calling
Program's Buffer 1
Unchanged
Buffer 1 Address
Po i nts to Buffer 1
Unchanged
Buffer 2 Length
Don't Care
Unchanged
Buffer 2 Address
Set Offset to Address
in 8031 on Chip
Space to Place Data
Unchanged
14 (Hex)
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
Unchanged
Select Adapter
= 0 for Adapter 1
= 1 for Ada pter 2
= 2 for Adapter 3
= 3 for Adapter 4
Unchanged
Diagnostic Function 4
= Hex 14
Cluster Adapter 77
Diagnostic Function 5
Function:
= Hex 15
This command is used to transfer data from the
8031 's internal RAM to a buffer in system memory.
The data is transferred starting at the address
specified by buffer 2 address (offset) in 8031 memory
to buffer 1 in the main system's memory.
(Reserved for diagnostic use only.)
Return Code
Definition
hex 00
hex 39
hex 3C
Successful completion
Command in progress
Error detected with 8031
link Control Block (LCB)
Field
Value at Entry
Value at Exit
Desti nation
Don't Care
Unchanged
Source
Don't Care
Unchanged
Command
= 15 (Hex)
Unchanged
Buffer 1 Length
Length of Calling
Program's Buffer 1
Unchanged
Buffer 1 Address
Points to Buffer 1
Unchanged
Buffer 2 Length
Don't Care
Unchanged
Buffer 2 Address
Set Offset to Address
in 8031 RAM from
Which to Get Data
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
Unchanged
Select Adapter
= 0 for Adapter 1
Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4
Diagnostic Function 5 = Hex 15
78 Cluster Adapter
Diagnostic Function 6 = Hex 16
Function:
This command is used to execute an 8031 program at
the address specified by the buffer 2 address field. A
"Call" is made to that address and it is expected that
the called program sets the 8031 accumulator to a
return code value before returning. This return code
is placed in the Cluster Status field if non-zero.
(Reserved for diagnostic use only.)
Return Code
hex
hex
hex
hex
00
39
3C
3D
Definition
Successful completion
Command in progress
Error detected with 8031
Extended return code in cluster status
Link Control Block (LCB)
Field
Value at Entry
Value at Exit
Destination
Don't Care
Unchanged
Source
Don't Care
Unchanged
Command
= 16 (Hex)
Unchanged
Buffer 1 Length
Don't Care
Unchanged
Buffer 1 Address
Don't Care
Unchanged
Buffer 2 Length
Don't Care
Unchanged
Buffer 2 Address
Set Offset to Address
in 8031 RAM Space
where a Callable
Program Exists
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
Extended Return Code
Select Adapter
= 0 for Adapter 1
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4
Unchanged
Diagnostic Function 6
= Hex 16
Cluster Adapter 79
Diagnostic Function 7 = Hex 17
Function:
This command is used to transmit any type of frame
to another station. For example, a control frame may
be sent to another station.
(Reserved for diagnostic use only.)
Return Code
Definition
hex 00
hex 31
hex 32
hex 33
hex 34
hex 36
hex 37
hex 39
hex 3A
hex 3C
Successful completion
Cluster always busy
Duplicate station address in cluster
No response from destination
Exceeded allowed rejected frames
Cluster access time-out
Information field too long
Command in progress
Initialization required
Error detected with 8031
Link Control Block (LCB)
Field
Value at Entry
Value at Exit
Destination
Destination
Unchanged
Source
Frame Type
Unchanged
Command
= 17 (Hex)
Unchanged
Buffer 1 Length
Length of Calling
Program's Buffer 1
Unchanged
Buffer 1 Address
Points to Calling
Program's Buffer 1
Unchanged
Buffer 2 Length
Length of Calling
Program's Buffer 2
Unchanged
Buffer 2 Address
Points to Calling
Program's Buffer 2
Unchanged
Return Code
Don't Care
Set to Return Code
Cluster Status
Don't Care
Unchanged
Select Adapter
= 0 for Adapter 1
Unchanged
= 1 for Adapter 2
= 2 for Adapter 3
= 3 for Adapter 4
Diagnostic Function 7 = Hex 17
80 Cluster Adapter
Special Transmit Mode Command Bits
The three most-significant bits in the command field of the LCB
have the following meanings for transmit commands:
Name
Bit
Meaning
Initiate Transmit
7
Initiate transmit operation but return before
complete with return code set to immediate
result.
Finish Transmit
6
Wait for previously started transmit operation
to complete. Return with return code in LCB
set to result of transmit operation.
Return Status
5
If the transmit operation is complete, the
return code is set to hex 00 (transmit.operation
complete result available). Otherwise the
return code is set to hex 3F (transmit operation
not complete).
Special Transmit Command Bits
Notes:
1. These special transmit command bits are valid only for the
following DLCP BIOS commands:
Transmit Frame
Cluster Status
Transmit Broadcast
Transmit Virtual Frame
(hex 03)
(hex 06)
(hex 08)
(hex 09)
2, A transmit operation started with the Initiate Transmit bit set
to 1 must be finished by issuing the same transmit command,
with a different LCB and the Finish Transmit bit set to 1. If
the immediate return code was not zero, the transmit
operation is already complete.
3. If an interrupt handler is being used for receive frames, an
interrupt is also generated when the transmit operation is
complete for transmit operations initiated with the Initiate
Transmit bit set. The Transmit Interrupt status bit is set to 1
to indicate that the transmit operation is complete. This bit is
bit 0 of adapter port hex 0792 (for adapter 1).
Cluster Adapter 81
82 Cluster Adapter
Interface
System Processor 1/0 Interface
Four Cluster Adapters can be installed at each station. The
Cluster Adapter number is selected by switch positions 1 through
4 of switch block 2. These positions correspond to 1/ 0 address
bits 10, 11, 12, and 13. An adapter is selected when a select
switch is On, and the adapter receives a high level (1) on the
corresponding 110 address bit.
Note: High level is 1 and low level is 0.
If mUltiple Cluster Adapters are installed at a station, each
adapter can have only one address select switch set to On. A
station cannot have two Cluster Adapters with the same address.
Notes:
1. When more than one address select switch is On, the Cluster
Adapter decodes and responds to all I/O addresses selected.
2. Cluster Adapter 1 is the only adapter that decodes and
responds to all memory addresses; therefore, if more than one
Cluster Adapter is set as number 1 (Cl), undesirable results
occur.
3. If a Cluster Adapter does not have a select switch set to On, it
does not respond.
Cluster Adapter 83
Cluster Adapter Switch Settings
Cluster Adapter addresses and functions can be selected by two
eight-switch dual in-line package (DIP) switch blocks. The
following shows the switch assignments:
Notes:
1. Switch 8 of switch block 1 selects remote initial program load
(IPL) when in the On position.
2. Switch 7 of switch block 1 is reserved. It must be in the Off
position.
Switch
Legend
SW-8
IPL
Function
Remote IPL
SW-7
N/A
Reserved (Must be Off)
SW-6
A5
Station Address Bit 5
SW-5
A4
Station Address Bit 4
SW-4
A3
Station Address Bit 3
SW-3
A2
Station Address Bit 2
SW-2
A1
Station Address Bit 1
SW-1
AO
Station Address Bit 0
Switch Block 1 Bit Assignments
Switch
Legend
Function
SW-8
N/A
Reserved
SW-7
ROY
1/0 Channel Ready
SW-6
N/A
Reserved
SW-5
N/A
Reserved
SW-4
C4
Select Adapter 4
SW-3
C3
Select Adapter 3
SW-2
C2
Select Adapter 2
SW-1
C1
Select Adapter 1
Switch Block 2 Bit Assignments
84 Cluster Adapter
The following shows the station-address switch settings on switch
block 1.
Switch Block 1 Switch Settings
Station
SW 1
SW2
SW3
SW4
SW5
SW6
0
Off
Off
Off
Off
Off
Off
1
On
Off
Off
Off
Off
Off
2
Off
On
Off
Off
Off
Off
3
On
On
Off
Off
Off
Off
4
Off
Off
On
Off
Off
Off
5
On
Off
On
Off
Off
Off
6
Off
On
On
Off
Off
Off
7
On
On
On
Off
Off
Off
8
Off
Off
Off
On
Off
Off
9
On
Off
Off
On
Off
Off
10
Off
On
Off
On
Off
Off
11
On
On
Off
On
Off
Off
12
Off
Off
On
On
Off
Off
13
On
Off
On
On
Off
Off
14
Off
On
On
On
Off
Off
Notes:
1. Bit switches 7 and 8 are not appl icable to the station address.
2. "On" represents the closed/on position.
3. "Off" represents the open/off position.
Station Address Switch Settings
Cluster Adapter 85
Switch Block 1 Switch Settings
Station
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SW 1
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
SW2
On
Off
Off
On
On
Off
Off
On
On
Off
Off
On
On
Off
Off
On
On
Off
SW3
On
Off
Off
Off
Off
On
On
On
On
Off
Off
Off
Off
On
On
On
On
Off
Station Address Switch Settings
86 Cluster Adapter
SW4
On
Off
Off
Off
Off
Off
Off
Off
Off
On
On
On
On
On
On
On
On
Off
SW5
Off
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
Off
SW6
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
On
Switch Block 1 Switch Settings
Station
SW1
SW2
SW3
SW4
SW5
SW6
33
On
Off
On
Off
On
Off
On
Off
On
On
Off
Off
On
On
Off
Off
Off
On
On
On
Off
Off
Off
Off
Off
Off
Off
Off
On
On
On
On
Off
Off
Off
On
Off
Off
On
Off
Off
On
On
On
On
On
Off
On
Off
On
On
Off
Off
Off
On
Off
Off
Off
On
On
On
On
On
On
Off
On
Off
On
On
Off
On
On
On
Off
Off
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Off
On
Off
Off
On
Off
On
On
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
On
On
On
On
On
On
On
On
On
On
On
On
Station Address Switch Settings
Cluster Adapter 87
Switch Block 1 Switch Settings
Station
SW 1
SW2
SW3
SW4
SW5
SW6
51
On
On
52
Off
On
Off
Off
Off
On
On
On
Off
Off
On
Off
On
On
On
On
Off
Off
Off
Off
Off
On
On
On
On
On
On
On
On
On
Off
Off
On
On
Off
Off
On
On
On
On
On
On
On
On
On
On
53
54
55
56
57
58
59
60
61
62
63
Off
On
Off
On
Off
On
Off
On
On
Off
Off
On
On
Station Address Switch Settings
88 Cluster Adapter
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
The following I/O addresses are assigned to the Cluster
Adapters:
Adapter
Adapter 1
I/O Address
(Hex)
Device
0790
Adapter Status Register
0791
Adapter Command/Data (Output)
Adapter Result/Data (Input)
Adapter 2
0792
Adapter Interrupt Register
0793
Adapter Reset Control
0890
Adapter Status Register
0891
Adapter Command/Data (Output)
Adapter Result/Data (Input)
Adapter 3
0892
Adapter Interrupt Register
0893
Adapter Reset Control
1390
Adapter Status Register
1391
Adapter Command/Data (Output)
Adapter Result/Data (Input)
Adapter 4
1392
Adapter Interrupt Register
1393
Adapter Reset Control
2390
Adapter Status Register
2391
Adapter Command/Data (Output)
Adapter Result/Data (Input)
2392
Adapter Interrupt Register
2393
Adapter Reset Control
Cluster Adapter I/O Summary
The Adapter Reset command resets the 8031 and 8255 on a
Cluster Adapter by writing a 1 to that adapter's Adapter
Reset/Interrupt Disable port address. This sets a 74LS74 latch,
which remains set until a 0 is written to the same port. The latch
must remain set for a minimum of 2 MS, which is the minimum
reset time of the 8031 operating at 12 MHz.
The interrupts on a Cluster Adapter can be disabled by writing a
o to the Adapter Reset/Interrupt Disable port, when -lOW is
active (0).
Cluster Adapter 89
The Cluster Adapter can drive the I/O Channel Ready line low in
synchronization with the system clock when the processor reads
from the adapter card. This enables a longer read cycle from the
expansion slots. The option is selected by setting the I/O
Channel Ready switch (switch 7 of switch block 2) to On.
System Processor Memory Interface
The memory addresses assigned to the Cluster Adapter are hex
DOOOO through hex D7FFF. These addresses are fully decoded
only on adapter 1, and are selected by setting the C 1 select switch
(SW2-1) to On. Each station must have one Cluster Adapter
selected as number 1.
System Processor Interrupt Interface
The Cluster Adapter provides an interrupt interface to the system
processor with Interrupt Request 3 (IRQ3) or Interrupt Request 7
(lRQ7). The desired interrupt is selected using the interrupt
select jumper on the Cluster Adapter. The selection of the
interrupt is dependent on the programming requirements.
90 Cluster Adapter
The following is a sequence of the interrupt process for adapter 1:
1. The system processor enables interrupts by writing to the
adapter interrupt enable register at address hex 0792.
2. Upon receipt of an interrupt condition, the 8031 sends a
negative active (0) pulse of 10 IJ-S on the port C bit 0 (PCO)
line of the 8255 which is connected to IRQ3 or IRQ7. The
low-to-high transition of this line prevents this adapter and
other Cluster Adapters in the system from generating further
interrupt requests. The 8031 processor also sets either Port
C1 (PCl) or Port C2 (PC2) of the 8255 to indicate the
source of the interrupt. PC 1 corresponds to a transmit
interrupt, and PC2 corresponds to a receive interrupt. If both
PC 1 and PC2 are set, the source of the interrupt is the
completion of a Cluster Status command.
3. The system processor reads I/O addresses hex 0792, OB92,
1392, and 2392 on each Cluster Adapter to determine the
cause of the interrupt. After all pending requests are handled,
the system processor re-enables interrupts on all desired
adapters.
8255 Programmable Peripheral Interface
(PPI)
The 8255 is used to provide an asynchronous interface between
the system processor and the 8031 Microcomputer without the
use of interrupts or direct memory access (DMA).
Cluster Adapter 91
PortA
Port A is operated in mode 2 as a strobed, bidirectional, I/O bus.
In this mode, all eight bits of Port A (PAO through PA7) are
dedicated to data transfer between the microcomputer (8031) and
the system processor (8088).
PortH
Port B is operated in mode o. The low-order six bits (PBO
through PB5) provide the station address, and the high-order bit
(PB7) provides the Remote IPL (On/Off) status. Bit 7 (PB6 is
reserved). The source of information for Port B is switch block 1.
When a bit switch is On, the bit is active (low). The
microprocessor code in the 8031 complements the Port B
information to produce logical 1 active bits.
Port C
When port C is operated in mode 2, five lines are dedicated as
handshaking signals. The following four handshaking signals are
used by the Cluster Adapter:
•
-Output Buffer Full (-OBF)
A low signal on the -OBF (PC7) line indicates that the
microcomputer (8031) has written data to Port A. -OBF
provides status to the adapter status register.
•
-Acknowledge (-ACK)
A low signal on the -ACK (PC6) line enables the tri-state
output buffer of Port A to send out data to the system
processor (8088); otherwise the output is in a high
impedance state.
92 Cluster Adapter
•
Input Buffer Full (IBF)
A high signal on the IBF (PC5) output indicates that data
from the 8088 has been loaded into Port A. IBF provides
input to the adapter status register and to the 8031.
•
-Strobe Input (-STB)
A low signal on the -STB (PC4) loads data from the 8088
into Port A.
The following is a summary of the 8255 port signals:
8255 Port Signals
Bit
PortA
Mode 2
7
Data Bit 7
Port B
Mode 0
Port C
Mode 2
Remote IPL
-OBF
6
Data Bit 6
Reserved
-ACK
5
Data Bit 5
Station Address Bit 5
+IBF
4
Data Bit 4
Station Address Bit 4
-STB
3
Data Bit 3
Station Address Bit 3
Reserved
2
Data Bit 2
Station Address Bit 2
Receive Frame Interrupt
1
Data Bit 1
Station Address Bit 1
TX Complete Interrupt
0
Data Bit 0
Station Address Bit 0
Interrupt Request
Summary of 8255 Port Signals
Cluster Adapter 93
Cluster Bus Interface
The bus interface consists of a transmitter, receiver, carrier sense
circuitry, and internalloopback-mode logic. They are the
interface between the 8031 serial port and the 75Q coaxial cable.
Cluster Adapter Transmitter
The Cluster Adapter transmitter consists of an Am26LS29
tri-state, single-ended, line driver. This driver features a high
capacitive-load drive capability with buffered outputs, individual
rise-time control, and output short-circuit protection.
To transmit data to the bus, the microprocessor code in the 8031
must first enable the -RTS signal on the port 3 interface. Data
can then be sent to the bus bit-by-bit from + TXD on port 3.
The transmitter is electrically isolated from the logic circuits on
the Cluster Adapter by an HCPL-2531 high-speed optocoupler,
which uses a light-emitting diode and an integrated light detector
to obtain electrical insulation.
Cluster Adapter Receiver
The Cluster Adapter receiver consists of an Am26LS34
high-performance, differential line receiver.
The received signal is amplified by a 5535 Operational Amplifier
and is provided to the Am26LS34. To receive the digital data, the
microprocessor code in the 8031 must ensure that the + Internal
Loop signal on port 3 is inactive. Data can then be received
bit-by-bit at port 3 from +RXD.
The receiver is also electrically isolated from the logic circuits on
the Cluster Adapter by an HCPL-2531 high-speed optocoupler.
94 Cluster Adapter
Carrier Sense Circuitry
The carrier sense circuitry provides information about the state of
the Cluster Adapter. This information is needed to implement
the collision avoidance protocol. The amplified signal received
from the bus is passed through a comparator to detect the
negative voltage state (less than approximately -150 millivolts).
This negative portion of the signal is inverted into + NRXD and
then ORed with the positive portion (greater than approximately
+ 150 millivolts) of the +RXD signal. The result is then sent to
the clear input of a 74LS161 counter. As long as this ORed
signal (CLR) is active (0), the counter is held reset. When the
signal goes inactive (1), the counter begins counting on the rising
edges of the 8031 +ALE signal. On the fourth +ALE pulse, the
counter is disabled and the -Carrier Sense signal goes inactive (1).
The time delay between the bus going inactive and -Carrier Sense
going inactive is 1.5 fJ,S.
Internal Loopback Mode
The Cluster Adapter provides logic to allow the 8031 to receive
the data it is transmitting without interference from the bus by
wrapping the transmitter to the receiver on the Cluster Adapter.
The adapter is placed into internal loop back mode when the 8031
microprocessor code sets the + Internal Loop signal active (1).
This mode returns any data transmitted on + TXD to +RXD.
Notice that -RTS mayor may not be active. If -RTS is active, the
data not only returns to +RXD, but also is transmitted to the bus.
Cluster Adapter 95
Specifications
Ballpoint
Pen
Rocker
Switch
Shield
96 Cluster Adapter
Logic Diagrams
The following pages contain logic diagrams.
Cluster Adapter 97
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98 Cluster Adapter
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102 Cluster Adapter
Index
A
adapter reset 89
address switch settings 85
B
BIOS interface 20
block diagram 3
c
check inside DLCP flag 68
cluster access protocol 29
Cluster Adapter 1
adapter reset 89
address switch settings 85
BIOS interface 20
block diagram 3
bus interface 94
check inside DLCP flag 68
cluster access protocol 29
cluster initialization (DLCP initialization) 44
cluster status 58
cluster status table 35
collision avoidance 30
control field format 25
diagnostic function 1 73
Index-l
diagnostic function 2 75
diagnostic function 3 76
diagnostic function 4 77
diagnostic function 5 78
diagnostic function 6 79
diagnostic function 7 80
display cluster status 55
DLCP BIOS commands 42
dump statistics 71
error detection and recovery 34
frame format 24
frame reception 33
frame transmission 22
I/O addresses 83
I/O register definitions 12
Intel 8031 memory map 10
Intel 8031 port signals 5
Intel 8255 port signals 91
interrupt interface 90
interrupts 16
Link Control Block (LCB) 21
memory interface 90
polynomial generator checker 10
programming considerations 18
read IPL switch 69
read station address 66
receive frame 51
receive virtual frame 49
remote IPL 37
set Multicast address 67
special transmit mode command bits 81
start DLCP 70
status 60
status register bit definitions 13
stop DLCP 65
switch blocks bit assignments 84
switch settings 84
transmit broadcast frame 61
transmit frame 53
transmit virtual frame 63
Cluster Adapter switch settings 84
cluster bus interface 94
cluster initialization (DLCP initialization) 44
Index-2
cluster status 58
cluster status table 35
collision avoidance 30
control field format 25
D
data link control program (DLCP) 18
diagnostic function 1 73
diagnostic function 2 75
diagnostic function 3 76
diagnostic function 4 77
diagnostic function 5 78
diagnostic function 6 79
diagnostic function 7 80
display cluster status 55
DLCP BIOS commands 42
dump statistics 71
E
error detection and recovery 34
F
frame format 24
frame reception 33
frame transmission 22
Index-3
I
I/O addresses 83
I/O register definitions 12
Intel 8031 memory map 10
Intel 8031 port signals 5
Intel 8255 port signals 91
interrupt interface 90
interrupts 16
L
link control block (LCB) 21
M
memory interface 90
p
polynomial generator checker 10
programming considerations 18
R
read IPL switch 69
read station address 66
Index-4
receive frame 51
receive virtual frame 49
remote IPL 37
s
set multicast address 67
special transmit mode command bits 81
start DLCP 70
status 60
status register bit definitions 13
stop DLCP 65
switch blocks bit assignments 84
T
transmit broadcast frame 61
transmit frame 53
transmit virtual frame 63
Index-5
Index-6
-- - ------_.-
--- ---------
Personal Computer
Hardware Reference
Library
mM Game Control
Adapter
6361493
ii
Contents
Description ....................................
Programming Considerations ......................
Address Decode ............................
Data Bus Buffer/Driver ......................
Trigger Buttons .............................
Joystick Positions ...........................
II 0 Channel Description .....................
Interface ......................................
Specifications ..................................
Logic Diagram .................................
1
3
3
3
3
3
4
5
7
9
iii
iv
Description
The IBM Game Control Adapter allows up to four paddles or two
joysticks to be attached to the system. This adapter fits into one
of the system board's or expansion board's expansion slots. The
game control interface cable attaches to the rear of the adapter.
In addition, four inputs for switches are provided. Paddle and
joystick positions are determined by changing resistive values sent
to the adapter. The adapter, when used with system software,
converts the present resistive value to a relative paddle or joystick
position. On receipt of an output signal, four timing circuits are
started. By determining the time required for the circuit to
timeout (a function of the resistance), the paddle position can be
determined. This adapter could be used as a general purpose 1/0
card with four analog (resistive) inputs plus four digital input
points.
A9-AO ....
L 10
AEN
lOW
lOR
...
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~
"
...
...
...
Convert
Resistance
Digital
Pulse
Instruction
Decode
r---
f4-8
"
Data Bus
Buffer /
Driver
.A
K...
K
"
4
I
r--
07-00
.A
A Resistive Input
Typical Frequency
833 Hz
4
~
~
Digital Inputs
4
I
Game Control Adapter Block Diagram
Game Control Adapter 1
2 Game Control Adapter
Programming Considerations
Address Decode
The select on the Game Control Adapter is generated by two
74LS138s as an address decoder. AEN must be inactive while
the address is hex 201 in order to generate the select. The select
allows a write to fire the one-shots, or a read to give the values of
the trigger buttons and one-shot outputs.
Data Bus Buffer/Driver
The data bus is buffered by a 74LS244 buffer/driver. For an In
from address hex 201, the Game Control Adapter will drive the
data bus; at all other times, the buffer is left in the high
impedance state.
Trigger Buttons
The trigger button inputs are read by an In from address hex 201.
A trigger button is on each joystick or paddle. These values are
seen on data bits 7 through 4. These buttons default to an open
state and are read as 1. When a button is pressed, it is read as O.
Software should be aware that these buttons are not debounced in
hardware.
Joystick Positions
The joystick position is indicated by a potentiometer for each
coordinate. Each potentiometer has a range of 0 to 100 kilohms
that varies the time constant for each of the four one-shots. As
this time constant is set at different values, the output of the
one-shot will be of varying durations.
Game Control Adapter 3
All four one-shots are fired at once by an Out to address hex 201.
All four one-shot outputs will go true after the fire pulse and will
remain high for varying times depending on where each
potentiometer is set.
These four one-shot outputs are read by an In from address hex
201 and are seen on data bits 3 through O.
110 Channel Description
A9-AO:
Address lines 9 through 0 are used to address the
Game Control Adapter.
07-00:
Data lines 7 through 0 are the data bus.
lOR, lOW:
I/O Read and I/O Write are used when reading
from or writing to an adapter (In, Out).
AEN:
When active, the adapter must be inactive and the
data bus driver inactive.
+5 Vdc:
Power for the Game Control Adapter.
GND:
Common ground.
The following I/O channel lines are not used:
MEMR,MEMW
ALE,T/C
DACKO-DACK3
CLK,OSC
IRQ7-IRQ2
-5 Vdc
DRQ3-DRQl
+12 Vdc
I/O CURDY
-12 Vdc
I/O CUCK
RESETORV
A19-A10
4 Game Control Adapter
Interface
The Game Control Adapter has eight input lines; four digital
inputs and four resistive inputs. The inputs are read with one In
from address hex 201.
The four digital inputs each have a I-kilohm pullup resistor to +5
Vdc. With no drives on these inputs, a 1 is read. For a 0 reading,
the inputs must be pulled to ground.
The four resistive pullups, measured to +5 Vdc, will be converted
to a digital pulse with a duration proportional to the resistive load,
according to the following equation:
Time
= 24.2 f.LS + 0.011
(r) f.LS
The user must first begin the conversion by an Out to address hex
201. An In from address hex 201 will force the digital pulse to go
high and remain high for the duration according to the resistance
value. All four bits (bit 3-bit 0) function in the same manner;
their digital pulse will all go high simultaneously and will reset
independently according to the input resistance value.
Bit 7
Bit 6
I
Bit 5
Digital Inputs
Bit4
Bit 3
Bit 2
I
Bit 1
BitO
Resistive Inputs
The typical input to the Game Control Adapter is a set of
joysticks or game paddles.
The joysticks will typically be a set of two (A and B). These will
have one or two buttons each with two variable resistances each,
with a range of 0 to 100 kilohms. One variable resistance will
indicate the X coordinate and the other variable resistance will
indicate the Y coordinate.
Game Control Adapter S
The joystick should be attached to give the following input data:
Bit 7
Bit 6
Bit 5
Bit4
Bit 3
B-#2
B-#1
A-#2
A-#1
B-Y
Button Button Button Button Coordinate
Bit 2
Bit 1
BitO
B-X
Coordinate
A-Y
Coordinate
A-X
Coordinate
The game paddles will consist of two (A and B) or four (A, B, C,
and D) paddles. These will have one button each and one
variable resistance each, with a range of 0 to 100 kilohms. The
game paddles should be attached to give the following input data:
Bit 7
Bit 6
Bit 5
Bit4
Bit 3
Bit 2
Bit 1
BitO
0
C
B
A
0
C
B
A
Coordinate
Coordinate
Coordinate
Button Button Button Button Coordinate
The following "Joystick Schematic Diagram" may be used for
attaching game controllers.
15-Pin Male D-Shell
Connector
Joystick B
,.....-------------,
:
1
I
I
1
1
I
1
X-Coordinate
I
I
I
I
,•
.,.
I
1
1
I 9
Butto~;r--..------r!
1
1
1
,.-
Joystick A
r--------------...
I
2 1
X-Coordinate
••..;.1_ _-1--.
'
J Button
---"'-",
--
V-Coordinate
~
0
~r-
__
!~
:~! ~!~J
5• ,,
6 '
.
1'3
IL _____________ .JI
!,
" '2
?4-------r----I1_.
1
i
,1'4
,
:',__
'·5
--
.~I
,1
__ 1_ _V-Coordinate
____
"
•7,,
~I
-.~
I'
:,
: L: ____________ _
-_
-_ ,
....I
Note: Potentiometer for X- and V-Coordinates has a range of 0
to 100 k-ohms. Button is normally open; closed when
pressed.
Joystick Schematic Diagram
6 Game Control Adapter
Specifications
15-Pin D-Shell
Connector
0
B
• •
• •
• •
•
• ••
• •
•
• •
9
15
0
At Standard TTL Levels
Voltage
External
Devices
Adapter
Pin No.
+5Vdc
1
Button 4
2
Position 0
3
Ground
4
Ground
5
Position 1
6
Button 5
7
+5Vdc
8
9
+5Vdc
Button 6
10
Position 2
11
Ground
12
Position 3
13
Button 7
14
+5Vdc
15
GameC ontrol
Adapter
Connector Specifications
Game Control Adapter 7
8 Game Control Adapter
I/O CHANNEL
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74LS138
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A8
A7
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A24
A25
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74LS244
06
05
04
03
II
1
8
FIRE
--------:=:=11
10
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8
U3
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1
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L'--
74LS138
All
I
Game Control Adapter (Sheet 1 of 1)
Notes:
10 Game Control Adapter
Source Exif Data:
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