Technical_Reference_Options_and_Adapters_Volume_3 Technical Reference Options And Adapters Volume 3
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-------- ----_
.-
--
Personal Computer
Hardware Reference
Library
IBM Personal Computer
Professional Graphics
Controller Technical
Reference
6138161
August 15, 1984
© Copyright IBM Corporation 1984
Contents
Description .................................... 1
Major Components .......................... 3
System-Bus Interface ..................... 4
Microprocessor Section . . . . . . . . . . . . . . . . . . .. 6
Video Control Generator Section ............ 8
Emulator Address Control ................ 11
Graphics Emulator ...................... 13
Display Memory ........................ 15
Look-Up Table and Video Output Section .... 18
Timing and Control Section ............... 19
Emulator Modes ........................... 20
Alphanumeric Mode ..................... 20
Graphics Mode ......................... 24
Description of Basic Operations ............ 28
High-Function Graphics Mode ................ 29
Alphanumeric Operation ................. 29
Graphics Operation ..................... 30
Description of Basic Operations ............ 32
Programming Considerations ..................... 33
Emulator Programming Considerations ......... 33
Programming the 6845 CRT Controller ...... 33
Programming the Mode Control and Status
Registers ............................. 35
Color-Select Register .................... 36
Mode-Select Register .................... 38
Status Register ......................... 41
Sequence of Events for Changing Modes ..... 42
Memory Requirements ................... 42
High-Function Graphics Programming
Considerations ........................... 43
Coordinate Space ....................... 45
Video Generation ....................... 56
Display Control ........................ 58
Drawing Primitives ...................... 63
Text ................................. 69
Command Lists ......................... 71
Look-Up Table ......................... 73
August 15,1984
© Copyright IBM Corporation 1984
iii
Image Processing ....................... 74
Read-Back Commands ................... 75
System Reset .......................... 77
Communications ........................ 78
Communication Protocol ................. 80
High-Function Graphics Commands ........... 83
Interface .................................... 179
Connector Specifications ................... 180
Specifications ................................ 181
Logic Diagrams ............................... 183
Glossary
................................... Glossary-l
Index ........................................ Index-l
iv
August 15,1984
© Copyright IBM Corporation 1984
Description
The IBM Personal Computer Professional Graphics Controller is
an adapter that: (1) provides a high-function graphics capability
and (2) acts as an IBM Color/Graphics Monitor Adapter, with
the exception of the 160-by-100 color/graphics mode.
The operations of the Professional Graphics Controller are
controlled by an 8088 Microprocessor. It carries out all
communications through its data bus and address bus. The
system-bus interface recognizes its own commands and passes
only these commands to the controller. The interface allows the
microprocessor to read or write to memory locations, using the
IBM Professional Graphics Controller microprocessor's data and
address busses.
The microprocessor controls and initializes several sections of the
controller. It defines the requirements of the controller's
hardware so the controller can imitate the actions of the IBM
Color/Graphics Monitor Adapter. The microprocessor also
regulates the emulator address control, which translates the
system's I/O address information and stores the associated data
in the graphics emulator memory for screen display. Finally, it
initializes the video control generator, which generates timing
pulses and the horizontal- and vertical-synchronization (sync)
pulses.
During operation, the microprocessor intercepts commands sent
to the emulator and interprets them. The microprocessor can also
accept and interpret the high-function graphics commands,
writing the results in the display memory for screen display. Both
the emulator and high-function graphics functions have access to
the look-up table (LUT) and output section.
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 1
The following is a block diagram of the Professional Graphics
Controller.
Sync
Data Bus
~f=='--">,I
~ R/W Control
!
SystemBu,
Look-Up
,----,vl
Interface
Address Bus
Timing
and
Control
Section
Emulator
Control
Table &
Video
Output
Section
Video
f---....!..!"'-'=----'
Character ROM
Row Address
Emulator RAM Address Bus
2 Professional Graphics Controller
August 15,1984
© Copyright IBM Corporation 1984
Major Components
•
•
•
•
•
System-Bus Interface
Bidirectional Buffer
Control Decode Logic
Address Decoder
Microprocessor Section
8088 Microprocessor
Clock Generator Control
Address Latch
Data Latch
Decoders
2K by 8-bit RAM
64K by 8-bit ROM
Video Control Generator Section
Video Controller
Control Decoder
16- by 8-bit State Length Memory
Synchronization Pulse Generator
State Multiplexer
Vertical and Horizontal State Counters
Vertical and Horizontal State Length Counters
Buffer
Emulator Address Control
Controller
Cursor Generator
Parameter Registers
Character ROM Address Generator
Row Address Generator
Column Address Generator
Microprocessor Address Buffers
Graphics Emulator
16K by 16-bit Emulator RAM
Shift Registers
Character ROM
Attribute Latch
Emulator PEL Processing
Buffer
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 3
•
Display Memory
High-Function Graphics Display Memory
Latch
Tri-State Bidirectional Driver
Tri-State Latch
320K by 8-bit RAM
Display RAM Address Control
High-Function Graphics Scanner
ROM
Buffers
Look-Up Table (LUT) and Video Output Section
Latches
Look-Up Table Memory
Buffer
Triple Digital-to-Analog Converter
Timing and Control Section
50-MHz Oscillator
High-Function Graphics Display Timing Generator
Control Decoder and Latches
•
•
System-Bus Interface
Following is a block diagram of the system-bus interface.
r--
-
("
8/.
Data Bus
/
Bidirectional
./ Buffer
A
K
8/
--"
liP Bus
/
VI
'"
In
.
E
~
VI
4/•
Decoded Control Lines
R/W Control )
I
-~~f
Control
Decode
Logic
20/
/
4 Professional Graphics Controller
v
U
5/
:>
/ ~
~
./"
Address
Decoder
20/,
liP Address Bus
/
v
August 15,1984
© Copyright IBM Corporation 1984
The system-bus interface allows the system microprocessor to
gain access to the display memory and emulated registers through
the 'data,' 'address,' and 'control' lines. The system-bus interface
can detect the attempt by the system microprocessor to execute a
Memory Write command or an I/O Write command to either the
emulator memory addresses or the communications memory for
the high-function graphics mode.
When the interface logic detects an assigned address, a 'hold'
signal is sent to the system microprocessor, which suspends the
operation of the controller microprocessor until the proper time.
Although the system microprocessor can gain access to the
memory of the controller microprocessor (through a series of
commands on the bus interface), it cannot directly access the
display RAM, nor can it issue interrupts to the controller
microprocessor. Likewise, the controller microprocessor cannot
gain control of the system bus.
If the system microprocessor writes to a register of the emulated
6845 CRT Controller, the data is stored in the controller's local
RAM.
The controller operates by mapping both the I/O addresses and
the addressed memory into its own memory. It then reads these
locations, interprets the data, and programs the hardware to
imitate the IBM Color/Graphics Monitor Adapter. If
high-function graphics commands are written to the
communication area, the controller microprocessor interprets
those commands and writes to the display memory for screen
display.
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 5
,
Microprocessor Section
Following is a block diagram of the microprocessor section
8088
IlP
Horizontal Test
Vertical Interrupt
6 Professional Graphics Controller
August 15,1984
© Copyright IBM Corporation 1984
The microprocessor section is a standard 8088 Microprocessor
arrangement. A 'timing control' line's input leads into a clock
generator control. The control signal emitted from the clock
generator provides the clock frequency that drives the 8088
Microprocessor. Address and data latches store the signals sent
over the address and data busses. Both the address and data lines
use two 32K by 8-bit ROMs and a single 2K by 8-bit static RAM.
The decoders control chip-select and latch registers.
A single, maskable interrupt occurs from the 'vertical interrupt'
line. The test pin of the microprocessor samples the horizontalsynchronization pulse.
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 7
Video Control Generator Section
Following is a block diagram of the video control generator
section.
Control Signals
Video
Controller
Timin
8 Professional Graphics Controller
August 15,1984
© Copyright IBM Corporation 1984
The video controller monitors and sequences the video control
generator section. The main loop of the control generator
controls the format of the display screen. A display screen is
divided into four states, as shown in the following.
14
-I
820 PELs
Vertical Sync
640 PELs
Horizontal
Sync
States-J
B
B
L
A
N
L
A
N
Active
Display
K
I
480
Lines
K
I
N
N
G
G
2
1
3
508
Lines
4
The state length memory is a part of the video control generator
section. The contents of the state length memory provide the
data to the state length counters, which then determine how long
each state remains active. For each scan line, the state length
memory loads this data, one at a time, into the horizontal state
length counter. At the end of the count, the counter signals
'done' to the video controller, which then sets the control lines or_
particular stages of each state and sends the control information
into the horizontal state counter. The video controller determines
whether to start again at zero for some state, or to increment the
state counter and begin on the next state. The horizontal state
counter counts the number of states across the screen. From the
state counter, the synchronization pulse generator determines the
vertical- or horizontal-synchronization pulse and activates the
appropriate line.
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 9
This same loop occurs for vertical states. The video controller
monitors the current vertical and horizontal states through the
state counters and synchronization pulse generator.
The controller microprocessor can write directly to the state
length memory to vary the size of each state on the screen. State
lengths remain under program control.
10 Professional Graphics Controller
August 15,1984
© Copyright IBM Corporation 1984
Emulator Address Control
Following is a block diagram of the emulator address control.
Timin Contro
I na s
Mode
IJP Data Bus
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 11
For the emulator mode, the address control consists of two
generators-a row address generator and a column address
generator. Both are driven by a controller and produce the
addresses needed for the emulator RAM.
The controller microprocessor can access the address bus to
program the address generators using an address buffer, and can
program the four parameter registers. The cursor generator
compares the addresses saved in the address generator with those
saved in the parameter registers. If a match is found, the cursor
generator activates the 'cursor' line.
The character ROM address generator produces a character ROM
row address that defines which line to write using a font with 8 by
16 character cells.
12 Professional Graphics Controller
August 15,1984
© Copyright IBM Corporation 1984
Graphics Emulator
Following is a block diagram of the graphics emulator.
Control
Shift Register
IBM Alpha Video Data
Emulator
RAM
Address
Bu,
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 13
The emulator RAM address bus sends signals to the 16K by
16-bit emulator RAM. The 16-bit-wide RAM allows the
character and its attributes to be read simultaneously. The RAM
shifts this information into a register that also acts as a latch.
During the alphanumeric mode, this information travels through
an attribute latch and the character ROM. The character ROM
checks the shift in the look-up table (LUT) before passing the
information through another shift register.
The attributes determine the foreground and background colors
of the character. The picture element (PEL) processor then shifts
this information out onto the PEL bus.
During the 320-by-200 and 640-by-200 modes, the emulator
RAM shifts out the information 16 bits at a time. The shift
register then shifts out its signals two bits at a time into the PEL
processor. The 640-by-200 mode uses these two bits alternately
as either black or white values. The 320-by-200 mode uses the
same two bits to determine the color placed on the screen.
The system microprocessor can read and write directly into the
emulator RAM space using the CPU address bus.
14 Professional Graphics Controller
August 15,1984
© Copyright IBM Corporation 1984
Display Memory
The display memory block consists of the high-function graphics
display memory and the display RAM address control.
High-Function Graphics Display Memory
Following is a block diagram of the high-function graphics display
memory
J.1p
Data
Bus
Latch
Control
Shift Re ister Bus
The high-function graphics display memory is logically arranged
as an array of 640-by-480 PELs. Each PEL represents one byte
of data. The Professional Graphics Controller provides a variety
of PEL write modes to improve the transfer of data to display
memory.
The high-function graphics display memory consists of five,
32-bit-wide banks (32 bits equal 4 PELs). The controller
microprocessor can write through the latch into the PEL memory.
All information is read from each memory and displayed each
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 15
time the picture is scanned. This process begins when the tri-state
drivers latch four PELs. Each tri-state driver is enabled
individually as the beam crosses the screen. After the fourth PEL
appears on the screen, four new PELs become latched.
In the high-function graphics mode, the high-function graphics
scanner generates addresses for a display access cycle on one of
the five banks every 160 nanoseconds (ns). These cycles are
staggered over an 800-ns period. Of the 32 bits of data latched
from the memory, one PEL is released onto the shift register
every 40 ns. The address selection generator, a field
programmable logic sequencer (FPLS), interleaves
microprocessor access cycles between display cycles, thus
providing the possibility of access every 160 ns. This process
achieves a display-memory access capacity of 32 bits every 80 ns.
During a microprocessor write operation, even in multi-PEL write
modes, all data from the microprocessor is latched, so the
microprocessor receives a 'ready' instantly. The FPLS cycles to
the correct locations, or to all locations, depending on the mode,
while the microprocessor prepares for the next access.
Another important aspect of the display memory is low power
consumption. The staggered access technique reduces the RAM
cycle time to as low as 400 ns, even with both the microprocessor
and display at full capacity. When the display operates alone, the
cycle time increases to 800 ns, minimizing RAM power
consumption.
16 Professional Graphics Controller
August 15,1984
© Copyright IBM Corporation 1984
Display RAM Address Control
Following is a block diagram of the display RAM address control.
Display Address Bus
Control
3
High-Function
Graphics
Scanner
Buffers
r;::===~> Control
ROM
16
liP Address Bus
In the high-function graphics mode, the high-function graphics
scanner operates as an address generator. The scanner output
selects data from each of the five 32-bit-wide banks (for a total of
20 PELs written). The controller microprocessor expects
memory to appear in a continuous manner; that is, 640 PELs
across. The address-translator ROM is an address map of 640
adjacent memory locations. This provides the display format,
thus leaving the controller microprocessor out of the conversion
process.
Because this address system operates on 20-PEL boundaries, the
memory for each line maps into an adjacent space of 640
locations for microprocessor access. Otherwise, if the
microprocessor did the work, the very high writing speeds would
be reduced.
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 17
Look-Up Table and Video Output Section
Following is a block diagram of the look-up table and video
output section.
Latch
Look·Up
Table
256 x 12
12
Memory
8
Pixel Bus
Red
Latch
Triple
DAC
12
8
P Data Bus
Buffer
Shift registers from the display memory latch onto the PEL bus
leading from the emulator. Both the emulator and high-function
graphics modes use the same PEL bus. The latches provide an
address for data in the look-up table (LUT). The eight lines of
the PEL bus provide up to 256 colors, while the 256- by 12-bit
LUT in memory provides a selection from a palette of 4096
colors. The LUT generates the color sent as output. The 12 LUT
output lines (4 bits each for red, green, and blue) are the inputs to
a triple digital-to-analog converter (DAC), which converts the
signal to red, green, and blue (RGB) intensities. The controller
microprocessor can write to and read from the LUT.
18 Professional Graphics Controller
August 15,1984
© Copyright IBM Corporation 1984
Timing and Control Section
Following is a block diagram of the timing and control section.
System Control Signals
50 MHz
Osc
-
....
I
High-Function
Graphics
Display
Timing
Generator
8/
Control
I
r
8L
J>..
>
I
IJP Control
3/.
I
j.lP Address Bus
Control
....
Control
Decoder
and
Latches
8/"
)
/
....
IJP Data Bus
...)
The high-function graphics-display timing generator, which is
driven by a 50-MHz oscillator, sends control signals for memory
and for the latch control from the display memory. It signals the
controller microprocessor when it is ready to receive or send data
from display memory. Except for system control signals, the
signals from the timing generator are latched and decoded. The
controller microprocessor maintains some control of the latches
and decoder. The timing generator also generates clock signals to
synchronize the board functions.
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 19
Emulator Modes
To provide compatibility with the Color/Graphics Monitor
Adapter protocols, the Professional Graphics Controller emulates
the Color/Graphics Monitor Adapter in the alphanumeric and
graphics modes.
Note: If a Color/Graphics Adapter is already present in the
system unit, the emulator section of the Professional
Graphics Controller is disabled with the enable/disable
jumper.
Alphanumeric Mode
Every display-character position in the alphanumeric mode is
defined by two bytes in the regen buffer, not the system memory.
Both the Professional Graphics Controller and the
Color/Graphics Monitor Adapter use the following 2-byte
character or attribute format.
The attribute byte definitions are:
7
6
[ B1 R
543
G B
2
[I [ R
1
0
J
G B
II~
Foreground Color
Foreground Intensity
Background Color
Foreground Blinking
20 Professional Graphics Controller
August 15,1984
© Copyright IBM Corporation 1984
The following table provides a summary of available colors.
I
0
0
0
0
0
0
0
0
R
1
0
0
0
0
G
0
0
B
1
Blue
1
0
Green
~an
0
Color
Black
1
1
0
0
0
Red
1
Magenta
1
1
0
Brown
1
White
0
0
0
0
0
0
0
Gray
1
Light Blue
1
1
0
Light Green
1
Light Cyan
1
1
1
0
Light Red
1
0
0
1
Light Magenta
1
1
1
1
0
Yellow
1
1
1
White (HiQh Intensity)
1
1
1
1
1
1
1
In the alphanumeric mode, the display mode can be operated in
either a 40-by-25 mode or a 80-by-25 mode.
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 21
40-by-25 Alphanumeric Mode
The 40-by-25 alphanumeric mode:
•
Displays up to 25 rows of 40 characters each
•
Has a ROM character generator that contains dot patterns
for a maximum of 256 different characters
•
Requires 2000 bytes of read/write memory (on the
controller)
•
Has a 16-high by 8-wide character box
•
Has one character attribute for each character
22 Professional Graphics Controller
August 15,1984
© Copyright IBM Corporation 1984
80-by-2S Alphanumeric Mode
The 80-by-25 alphanumeric mode:
•
Supports the IBM Professional Graphics Display
•
Displays up to 25 rows of 80 characters each
•
Has a ROM character generator that contains dot patterns
for a maximum of 256 different characters
•
Requires 4000 bytes of read/write memory (on the
controller)
•
Has a 16-high by 8-wide character box
•
Has one character attribute for each character
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 23
Graphics Mode
The Professional Graphics Controller has two modes available
with the graphics mode-the 320-by-200 color/graphics mode
and 640-by-200 black-and-white graphics mode. Both are
supported in ROM. The following table summarizes the two
modes.
Modes
Number of Colors Available
(Includes Background Color)
320 x 200
4 Colors Total
1 of 16 for Background and
1 of Green, Red, or Brown or
1 of Cyan, Magenta, or White
640 x 200
Black-and-white only
320-by-200 Color/Graphics Mode
The 320-by-200 color/graphics mode supports the Color Display.
It has the following features:
•
Contains a maximum of 200 rows of 320 picture elements
(PELs), with each PEL being 2.4-high by I-wide
•
Preselects one of four colors for each PEL
•
Requires 16,000 bytes of read/write memory (on the
controller)
•
Uses memory-mapped graphics
24 Professional Graphics Controller
August 15,1984
© Copyright IBM Corporation 19R4
•
Formats four PELs for each byte as follows:
7
6
C1 CO
•
5
4
C1 CO
3
2
C1 CO
1 0
C1 CO
First
Second
Third
Fourth
Display
Display
Display
Display
PEL
PEL
PEL
PEL
Organizes graphics storage in two banks of 8000 bytes, using
the following format:
Memory
Address
(in hex)
Function
B9F3F
Even Scans (0,1,4,5,8,9 ... 198)
8,000 bytes
B8000
Not Used
BAOOO
Odd Scans (2,3,6,7,10,11 ... 199)
8,000 bytes
BBF3F
Not Used
BBFFF
Address hex B8000 contains PEL information for the
upper-left corner of the display.
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 25
•
Determines color selection by the following logic:
C1
co
0
0
Dot takes on the color of 1 of 16 preselected
background colors
0
1
Selects first color of preselected Color Set 1 or
Color Set 2
1
0
1
1
Selects second color of preslelcted Color Set 1
or Color Set 2
Selects third color of preselected Color Set 1 or
Color Set 2
Function
C 1 and CO select 4 to 16 preselected colors. This color selection
(palette) is preloaded in an 110 port.
The two color sets are:
Color Set 2
Color Set 1
Color 1 is green
Color 1 is cyan
Color 2 is red
Color 3 is brown
Color 3 is white
Color 2 is magenta
26 Professional Graphics Controller
August 15,1984
© Copyright IBM Corporation 1984
640-by-200 Black-and-White Graphics Mode
The 640-by-200 black-and-white graphics mode supports color
monitors. This mode:
•
Contains a maximum of 200 rows of 640 PELs, with each
PEL being I-high by I-wide.
•
Supports black-and-white mode only.
•
Requires 16,000 bytes of read/write memory (on the
controller) .
•
Uses the same addressing and mapping procedures as the
320-by-200 color/graphics mode, but the data format is
different. In this mode, each bit in memory is mapped to a
PEL on the screen.
•
Formats eight PELs per byte as follows:
1716151413121'101
First Display PEL
Second Display PE L
JJ
Third Display PEL
Fourth Display PEL
Fifth Display PEL
Sixth Display PEL
Seventh Display PEL
Eighth Display PEL
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics ControUer 27
Description of Basic Operations
In the alphanumeric mode, the controller fetches character and
attribute information from its display buffer. The starting address
of the display buffer is programmable through the 8088
Microprocessor, but it must be an even address. The character
codes and attributes are then displayed according to their relative
positions in the buffer as shown in the following.
Memory
Address
(in hex)
Display 8uffer
88000
(Even)
Starting
Address
Character Code A
88001
Attribute A
(Example of a 40 by 25 Screen)
88002
Character Code 8
AB
88003
Attribute 8
X
887CE
Character Code X
Last
Address
Video Screen
887CF
Attribute X
The processor and display control unit have equal access to the
display buffer during all operating modes except the 640-by-200
alphanumeric mode. During this mode, the processor should have
access to the display buffer during the vertical retrace time. If it
does not, the display will be affected with random patterns as the
processor is using the display buffer. In the alphanumeric mode,
the characters are displayed from a prestored ROM character
generator that contains the dot patterns of all the displayable
characters.
In the graphics mode, the displayed dots and colors (up to 16K
bytes) are also fetched from the display buffer.
28 Professional Graphics Controller
August 15,1984
© Copyright IBM Corporation 19R4
High-Function Graphics Mode
The Professional Graphics Controller provides high function
graphics capability for the PC by processing simple .command
strings into bit-mapped images in the controller. The Professional
Graphics Controller provides both alphanumeric and graphic
capabilities.
Alphanumeric Operation
The alphanumeric operation:
•
Contains a built-in character font with character enlargement
capabilities.
•
Uses a smoothing function for enlarged characters.
•
Permits characters to be drawn in a foreground color with a
transparent background; therefore, whatever is behind the
character remains there.
•
Contains programmable character fonts accessible through
the high-function graphics command set.
Note: The programmable character sets cannot be
enlarged.
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics ControUer 29
Graphics Operation
The high-function graphics mode supports the Professional
Graphics Display. It has the following features:
•
Contains 480 rows of 640 PELs; the PELs are spaced the
same distance vertically and horizontally providing the
standard 4:3 screen aspect ratio.
•
The color of each PEL is selected from a set of 256 colors,
which are selected from a palette of 4096 colors.
•
Requires 307,200 bytes of read/write memory (on the
controller) .
Note: This memory is addressable only through the
high-function graphics commands and does not occupy
system address space.
•
Uses memory-mapped graphics.
•
Formats one PEL for each byte.
•
Organizes a communications area consisting of a bank of
1000 bytes.
30 Professional Graphics Controller
August 15,1984
ID Copyright IBM Corporation 1984
•
Color selection is determined by the following logic:
The display RAM supplies an 8-bit byte that is used as an
address to the LUT. This 8-bit address selects one of 256
12-bit words from the LUT. This data provides the color
information for each PEL to be sent to the screen. The
12-bit word is divided into three groups of 4-bits: 4 red, 4
green, and 4 blue, as shown in the following table.
4 Bits
Red
I
I
4 Bits
Green
I
I
4 Bits
Blue
1 PEL
1 Byte
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 31
Description of Basic Operations
The controller microprocessor interprets high-function graphics
commands and translates them into data that is stored in the
display memory. The display memory is then scanned 60 times
each second. Each byte is then sent to the LUT. Whatever data
is in memory is used as an address to the LUT data to determine
what is sent to the screen.
32 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
Programming Considerations
The Professional Graphics Controller provides the operation of
two individual adapters: (1) the Color/Graphics Monitor
Adapter and (2) the High-Function Graphics Adapter. The
emulation operation and the high-function graphics operation may
be individually programmed. High-function graphics commands
determine which of the two operations appears on the screen.
Emulator Programming Considerations
The Professional Graphics Controller emulates the 6845 CRT
Controller of the Color/Graphics Monitor Adapter.
Programming the 6845 CRT Controller
The CRT Controller has 19 accessible internal registers, which
are used to define and control a raster-scan CRT display. One of
these registers, the index register, is actually used as a pointer to
the other 18 registers. It is a write-only register, and is loaded
from the processor by executing an Out instruction to I/O
address hex 3D4. The five least-significant bits of the I/O bus
are loaded into the index register.
To load any of the other 18 registers, the index register is first
loaded with the necessary pointer; then the data register is loaded
with the information to be placed in the selected register. The
data register is loaded from the processor by an Out instruction to
I/O address hex 3D5.
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 33
The following table defines the values that must be loaded into
the 6845 CRT Controller registers to control the different modes
of operation supported by the controller.
Address Register
Register Number
Register
Type
Units
I/O
40 by 25 80 by 25
AlphaAlphanumeric numeric
Graphic
Modes
4
R4
Vertical Total Character
Row
Write
Only
1F
1F
1F
5
R5
Vertical Total Scan Line
Adjust
Write
Only
06
06
06
6
R6
Character
Row
Write
Only
19
19
19
7
R7
Vertical Sync Character
Position
Row
Write
Only
1C
1C
1C
A
R10
Cursor Start Scan Line
Write
Only
06
06
06
B
R11
Cursor End
Scan Line
Write
Only
07
07
07
C
R12
Start
Address(H)
-
Write
Only
00
00
00
D
R13
Start
Address(L)
-
Write
Only
00
00
00
E
R14
Cursor
Address(H)
-
Read/
Write
XX
XX
XX
F
R15
Cursor
Address(L)
-
Read/
Write
XX
XX
XX
Vertical
Displayed
Note: All register values are in hexadecimal
34 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
Programming the Mode Control and Status Registers
The following shows the 110 registers of the Professional
Graphics Controller.
Function of Register
Hex
Address
A9 AS A7 A6 AS A4 A3 A2 A 1 AO
Mode Control Register
(DO)
3D8
1
1
1
1
0
1
1
0
0
0
Color Select Register
(DO)
3D9
1
1
1
1
0
1
1
0
0
1
Status Register (D 1)
3DA
1
1
1
1
0
1
1
0
1
0
6845 Index Register
3D4
1
1
1
1
0
1
0
1
0
0
6845 Data Register
3D5
1
1
1
1
0
1
0
1
0
1
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 35
Color-Select Register
This is a 6-bit, output-only register (cannot be read). Its I/O
address is hex 3D9, and it can be written to by using the 8088
Microprocessor's I/O Out command. Following is a description
of the bits of the color-select register.
Bit 0
Selects B (blue) background color in 320 x 200 graphics mode
Selects B (blue) foreground color in 640 x 200 graphics mode
Bit 1
Selects G (green) background color in 320 x 200 graphics mode
Selects G (green) foreground color in 640 x 200 graphics mode
Bit 2
Selects R (red) background color in 320 x 200 graphics mode
Selects R (red) foreground color in 640 x 200 graphics mode
Bit 3
Selects I (intensified) background color in 320 x 200 graphics mode
Selects I (intensified) foreground color in 640 x 200 graphics mode
Bit 4
Selects alternate, intensified set of colors in graphics mode
Bit 5
Bit 6
Selects active color set in graphics mode
Not used
Bit 7
Not used
Bits 0, 1, 2, 3
Select the foreground color in the 640-by-200
color / graphics mode, and the background color
(CO or Cl) in the 320 by 200 color/graphics
mode.
Bit 4
When set, selects an alternate, intensified set of
colors.
Bit 5
Used in the 320 by 200 color/graphics mode to
select the active set of screen colors for the
display.
36 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
When bit 5 is set to 0, colors are determined as follows:
Cl
co
0
0
Background (Defined by
bits 0-3 of port hex 309)
0
1
Green
1
1
0
Red
1
Brown
Colors Selected
When bit 5 is set to 1, colors are determined as follows:
Cl
co
0
0
Background (Defined by
bits 0-3 of port hex 309)
0
1
Cyan
1
1
0
Magenta
1
White
Colors Selected
°
When bit 5 is set to and bit 2 of the mode-select register is set
to 1, colors are determined as follows:
Cl
co
0
0
Background
0
1
Cyan
1
1
0
Red
1
White
August 15,1984
© Copyright IBM Corporation 1984
Colors Selected
Professional Graphics Controller 37
Mode-Select Register
This is a 6-bit, output-only register (cannot be read). Its I/O
address is hex 3D8, and it can be written to using the 8088
Microprocessor's I/O Out command.
The following table is a description of the register's functions
when the bit values are set to 1"
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
80 x 25 alphanumeric mode
Graphics select
Black/white select
Enable video signal
640 x 200 black/white mode
Change background intensity to blink bit
Not used
Not used
Bit 0
A 1 selects 8o-by-25 alphanumeric mode.
A a selects 4o-by-25 alphanumeric mode.
Bit 1
A 1 selects graphics mode.
A a selects alphanumeric mode.
38 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
Bit 2
A 1 selects black-and-white mode.
A 0 selects color mode.
Bit 3
A 1 enables the video signal at certain times when
modes are being changed. The video signal should be
disabled when changing modes.
Bit 4
A 1 selects the 640-by-200 mode black-and-white
graphics mode. One of 8 colors can be selected on
direct-drive sets in this mode by using register hex 3D9.
Bit 5
When on (set to 1), this bit changes the character
background intensity to the blinking attribute function
for alphanumeric modes. When the high-order attribute
bit is not selected, 16 background colors (or intensified
colors) are available. For normal operation, this bit
should be set to 1 to allow the blinking function.
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics ControUer 39
Mode-Select Register Summary
The following table shows the mode-select registers.
Bits
0
1
2
3
4
5
0
0
1
1
0
1
0
0
0
1
0
1
40 x 25 Alphanumeric Color
1
0
1
1
0
1
80 x 25 Alphanumeric Black-and-White
40 x 25 Alphanumeric Black-and-White
1
0
0
1
0
1
80 x 25 Alphanumeric Color
0
1
1
1
0
z
320 x 200 Black-and-White Graphics
0
1
0
1
0
z
320 x 200 Color Graphics
0
1
1
1
1
z
640 x 200 Black-and-White Graphics
II
I
:
'"bl, 81;,k AU,ib""
640 x 200 Black-and-White
Enable Video Signal
~------~
L--------__--~--------....
Select Black-and-White Mode
Select 320 x 200 Graphics
80 x 25 Alphanumeric Select
z = Don't care condition
40 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
Status Register
The status register is a 4-bit, read-only register. Its I/O address is
hex 3DA, and it can be read using the 8088 Microprocessor's I/O
In command. The following table is a description of the register
functions.
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
0
1
2
3
4
5
6
7
Display Enable
Reserved
Reserved
Vertical Sync
Not Used
Not Used
Not Used
Not Used
Bit 0
When set to 1, indicates that access to the regen buffer
memory can be made without interfering with the display.
Bit 3
When set to 1, indicates that the raster is in a vertical
retrace mode. This is a good time to update the screen
buffer.
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics ControUer 41
Sequence of Events for Changing Modes
1.
Determine the mode of operation.
2.
Reset the video enable bit in the mode-select register.
3.
Program the CRT Controller to select the mode.
4.
Program the mode- and color-select registers, including
re-enabling video.
Memory Requirements
The memory used by this controller is provided entirely on-board.
It consists of 16K bytes without parity. This memory is used as
both a display buffer for alphanumeric data and as a bit map for
graphics data. The regen buffer's address starts at hex B8000.
The following table shows the memory requirements.
Read/Write Memory Address
Space (in hex)
01000
System
Read/Write
Memory
AOOOO
B8000
Display Buffer
(16K Bytes)
BBFFF
coooo
42 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
High-Function Graphics Programming
Considerations
The high-function graphics command set uses a wide range of
two-dimensional and three-dimensional programs that include:
•
Drawing primitives with points, vectors, and polygons in two
and three dimensions
•
Coordinate transformations with modeling (scaling, rotation,
translation) and viewing transformations
•
Drawing primitives with rectangles, circles, ellipses, arcs, and
sectors in two dimensions
•
Stored segments that define and execute command lists
•
Color control functions
•
Text generation
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics ControUer 43
Following is a flowchart of the two- and three-dimensional
commands.
3D
Commands
Modeling
Transformation
(4·by·4 Matrix)
Viewing
Transformation
(4·by-4 Matrix)
Hither/Yon
Clipping
3D to 20
Transformation
20
Commands
Window Clipping
and Viewport
Transformation
Standard 20
Draw Routines
44 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
Objects may be defined in three dimensions using the
three-dimensional drawing commands. A modeling matrix allows
the object to be moved (translated), changed in size (scaled), and
rotated. A viewing matrix allows the object to be viewed from
different directions and distances.
Two clipping planes are defined at right angles to the
line-of-sight. Any part of an object beyond the yon clipping plane
and any part of an object in front of the hither clipping plane are
not seen.
Three-dimensional objects are projected onto a two-dimensional
viewplane, which is the plane of the monitor's screen.
Two-dimensional objects are defined directly on the viewplane.
Coordinates on the viewplane are referred to as virtual
coordinates. A window defines that area of the viewplane that is
visible. Any part of an object outside the defined window is not
seen. A viewport specifies a rectangular area on the monitor's
screen that completely contains the defined window.
Coordinate Space
Two-dimensional commands operate on a virtual coordinate space
whose x and y boundaries range from -32768.00000 bits to
+32767.99999 bits, with 16 bits of precision to the right of the
decimal point. The display screen, however, is 640 PELs wide by
480 high. Therefore, commands are available to specify how
coordinates are converted from virtual values to screen values. In
addition, portions of the physical screen may be declared "off
limits" to drawing. This is accomplished through the command
VWPORT, which defines a rectangular clipping viewport.
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 45
The following figure shows the relationship of two-dimensional
virtual coordinate space to real coordinate space.
Virtual Coordinate Space (20)
+32767.99999 Bits
Transformation
Process
y
~
x
-32768.00000 Bits
Real Coordinate Space
J-- 640 Bits--l
+32767.99999
Bits
(0,0)
0
1
IS
480
(D,O)
-32768.00000 Bits
Three-dimensional drawing commands operate in a virtual
coordinate space whose x and y boundaries range from
-32768.00000 bits to +32767.99999 bits, but a z coordinate is
added, which may have any value in the same range as x and y.
All three-dimensional drawing may be divided into a series of
points and lines; these points and lines are what are mapped onto
the two-dimensional plane for actual writing to the display.
The following figure shows the relationship of three-dimensional
virtual coordinate space to real coordinate space.
Virtual Coordinate Space (3D)
-32768.00000 Bits
,
""
-32768.00000
Real Coordinate Space
1--640 Bits--l
+32767.99999 Bits
y
Bits.-------"~-'---...
;;~:::~rmationD T
+32767.99999
Bits
(0,0,0)
-32768.00000 Bits
46 Professional Graphics Controller
1
4 80 Bits
..
+32767.99999 Bits
August 15,1984
© Copyright IBM Corporation 1984
Coordinate Transformations
The high-function graphics mode refers to four coordinate
systems when converting three-dimensional virtual coordinates to
a screen image. The two-dimensional commands MOVE and
DRAW undergo a single transformation.
Two-Dimensional Transformation
The lowest level of transformation occurs following the
two-dimensional command MOVE or DRAW. These commands
use parameters given in two-dimensional virtual coordinates. The
high-function graphics mode converts these points to screen
coordinates. To understand this conversion, keep in mind that the
window in two-dimensional virtual space maps onto the viewport
of the screen.
The WINDOW command defines an area (window) in
two-dimensional virtual space to be mapped into a defined
viewport with x and y virtual coordinate values, as follows:
y
Window
~
Yw2
x
x w l.Ywl
August 15,1984
© Copyright IBM Corporation 1984
xw2
Professional Graphics Controller 47
The x and y values may range from -32768.00000 to
+32767.99999. The VWPORT command defines an area
(viewport) within the display screen with x and y screen
coordinate values, as shown in the following.
,
Viewport
. . t. . .
Yv2
x v l,Yvl
xv2
x
0,0
The x values range from 0 to 639, and the y values from 0 to 479.
The two-dimensional command uses virtual coordinates; that is,
X2dvir and Y2dvir. The high-function graphics mode converts
these to screen coordinates, Xscrn and Yscrn, using the following
equations.
Xscrn
(Xv2 - XvI)
(X2dvir - XwI) x ----------------- + XvI
(Xw2 - XwI)
Yscrn
(Yv2 - YvI)
(Y2dvir - Ywl) x ----------------- + Yvl
(Yw2 - YwI)
The X2dvir, Y2dvir are two-dimensional virtual coordinates. The
variables Xwl, Xw2, Ywl, and Yw2 are window coordinates, and
XvI, Xv2, Yvl, and Yv2 are viewport coordinates.
48 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
Three-Dimensional Transformation
Three-dimensional transformations involve converting
three-dimensional points to two dimensions. This process uses
the following matrix operation for the conversion; that is
three-dimensional world coordinates to three-dimensional viewing
coordinates:
[Xview, Yview, Zview, 1 J =
[Xvirtual, Yvirtual, Zvirtual, 1J x [MJ x [VRPJ x [VJ
[M] represents the modeling matrix, [VRP] represents the view
reference point matrix, and [V] denotes the viewing matrix. The
three-dimensional viewing coordinates can be read back using the
command FLAGRD 24. The last value of the viewing matrix
remains 1 only if the last columns of all matrixes entered in this
formula have the following form.
x x x
x x x
x x x
0
x x
1
X
0
0
Otherwise, the result will have the form:
[Xview, Yview, Zview, QJ
To reduce this result to the form required, simply divide the X, Y,
and Z values by the value Q. This operation gives a 1 as the final
column value of the matrix, and proper values for the other three
parameters.
The Modeling Matrix
The modeling matrix, [M], rotates, translates, and scales the
coordinate values of an object defined in three-dimensional
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 49
virtual coordinates. Rotation about any axis uses the right-hand
rule. To understand this principle, refer to the coordinate space
depicted below (the positive z direction comes out of the page).
y
x
z
To rotate in a positive direction around the y axis, the positive z
axis rotates toward the positive x axis. To rotate in a positive
direction around the x axis, the positive y axis rotates toward the
positive z axis. To rotate in a positive direction around the z axis,
the positive x axis rotates toward the positive y axis.
Keep in mind that the order of rotation changes the viewing faces
of the object. That is, an object rotated along the x axis, then the
y axis, gives a different perspective than if the same object is
rotated first along the y axis, then the x axis.
SO Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
The following illustration depicts various viewing perspectives.
Original
MDROTX 90 ... then ... MDROTY 90
MDROTY 90 ... then ... MDROTX 90
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 51
Rotation involves the matrix operation,
[M(new)]
[M(old)] x [M(rst)]
[M(rst)] represents the rotation, scaling, or translation matrix.
For rotation, this matrix differs with each axis chosen as the axis
of rotation. For each direction of rotation, the algorithm refers to
the appropriate matrix as follows:
0
cose
1
Rx(e) =
Ry(e)
0
0
0
0
case
0
case
0
0
-sine
sine
0
0
-sine
0
Rz(e) =
0
sine
case
-sine
0
case
0
0
0
0
sine
case
0
0
0
0
0
0
0
0
0
0
0
0
0
The scaling operation uses the following matrix.
0
0
Ys 0
0
Zs
000
Xs
s
o
o
52 Professional Graphics Controller
0
0
0
August 15, 1984
© Copyright IBM Corporation 1984
The translation operation uses the following matrix.
T
o
o
Xt
000
0
0
0
Yt
0
Zt
Viewer Reference-Point Matrix
The viewer reference-point matrix, [VRP], translates the point
viewed by the user to the center of the currently defined window.
Because the window coordinates map onto the viewport
coordinates, this matrix also places the user-viewed point at the
center of the viewport.
The viewing matrix, [V], affects the degree of rotation of the
object by moving the eye about the object, while keeping the
object stationary. Like the modeling matrix, the viewing matrix
uses the right-hand rule for rotation of the eye about the viewing
reference point.
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 53
Three-Dimensional Hither and Yon Clipping
Besides two-dimensional viewport clipping, the high-function
graphics mode also clips in the third dimension. The hither and
yon clipping designate two x-y planes along the z axis beyond
which no drawing takes place.
..........
+y
• _ Y o n Plane
-z
-x
_--------,~-----
__ +x
+z
_
Hither Plane
-y
54 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
Three-Dimensional Viewing to Two-Dimensional Virtual
Projection
Using the DISTAN command, the user specifies the distance from
the eye to the viewplane. The command PROJCT provides a
viewing angle with a value ranging from 1 to 179 degrees. The
high-function graphics mode projects the viewing coordinate into
a two-dimensional coordinate value using the following formulas.
WINDOW DIAGONAL
DISTAN
X2dvir
------------ x Xview x -------------------------
DISTAN - Z
2 x DISTAN x tan(PROJCT)
2
DISTAN
Y2dvir
WINDOW DIAGONAL
------------ x Yview x -------------------------
DISTAN - Z
2 x DISTAN x tan(PROJCT)
2
Placing the object closer magnifies the X and Y values.
Increasing the viewing angle increases the amount of picture
visible in the viewing field.
If the PROJCT angle is 0, the projection is orthographic parallel
(non-oblique), The high-function graphics mode projects the
viewing coordinate into a two-dimensional coordinate value using
the following formulas:
X2dvir
Xview
Y2dvir
Yview
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 55
Video Generation
A total of 256 colors may be displayed on the screen at one time.
A total of 4096 possible color selections is available to the LUTs.
The video generation process begins when the video scanner reads
the value of the PEL about to be displayed. The PEL value
consists of eight bits and is used as an address to the LUT. The
PEL value selects one of 256 12-bit entries in the table. The
three 4-bit output values from the LUT represent the red, green,
and blue intensities required to compose the target PEL. Because
the table outputs are 4 bits each for the three colors, the 256
simultaneous colors may be chosen from a 4096-color palette.
The LUTINT command sets the entire look-up table from one of
several predefined LUT selections. The LUT command loads
individual LUT entries, and LUTRD reads them back.
Each bit of each PEL resides in one of eight bit planes in the
display memory. The bit planes are masked for reading and
writing. These bit planes are shown in the following.
Bit Plane 7
Bit Plane 0
I
1
480
Bits
-L.-
-L..L.-
-L..-
~
________ 640 ________~
Bits
56 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
Current Point
The current point is the x-y-z coordinate point at which the last
command finished. Many high-function graphics commands use a
current point in carrying out their functions. Two current points
are maintained; one is used by two-dimensional commands, the
other by three-dimensional commands. For example, the
two-dimensional command CIRCLE draws a circle centered on
the two-dimensional current point; the three-dimensional
command DRAW3 draws a vector that starts at the
three-dimensional current point. The current points are moved
whenever move and draw commands are executed. When
referred to in the command descriptions, the applicable current
point will be identified, unless it is clear from the context of the
command.
The command CONVRT will change a three-dimensional current
point to a two-dimensional virtual coordinate. This conversion
allows the user to overdraw a three-dimensional drawing with
two-dimensional commands, such as text.
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 57
Current Color
The current color is the last color a COLOR command defines for
general drawing. Drawing is possible in two modes-the
complement drawing mode and the replace drawing mode. In the
complement drawing mode, the PEL bit value in display RAM is
complemented from its current value. In the replace drawing
mode, the PEL bit value in display RAM is changed to a specified
value. The value comes from the current color, which is set by
using the COLOR command.
Note: In both cases, the actual value written into a PEL may
be affected by a mask.
Display Control
Display control commands set or reset flags or define commonly
used parameters. All these commands affect the way that later
commands draw to the screen.
Drawing Modes
The high-function graphics mode provides several drawing modes.
It has its own language. The Professional Graphics Controller
also imitates two current graphics modes resident in the existing
PC graphics systems. The Professional Graphics Controller will
accept and execute all commands sent to either mode. To view
the current status of commands sent to a particular mode, use the
DISPLA command, indicating the appropriate mode as the
parameter. This command simply switches between the
high-function graphics screen and the emulator screen. All
previous drawing sent to either screen remains intact during these
switches, because Draw commands are independent of the
viewing status; that is, high-function graphics commands affect
the high-function graphics screen even while the emulator screen
is displayed.
58 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
Primitive Fills and Drawing Patterns
The command PRMFIL sets an onloff flag to fill the commands
that draw defined geometric shapes and create an enclosed area.
Each command description will note the effects of any flags.
The user can change the drawing pattern by using Pattern
commands. The command LINP AT governs any vector or other
command drawing a geometric shape (with PRMFIL off). The
parameter, a 16-bit number, acts as a mask during drawing. Each
bit sets an onloff pattern for a corresponding PEL on the screen.
This pattern repeats every 16 PELs. A 1 in any bit position
draws a PEL, while a 0 changes nothing. The value 65535
produces a solid line.
Similarly, the command AREAPT establishes a drawing pattern
for an area using a 16-bit by 16-bit format. This command
repeats in blocks of 16-by-16 PELs, duplicating the pattern in
both a horizontal and vertical direction. To define a pattern,
enter sixteen 16-bit words, visualizing their orientation on a grid.
For example:
Word
Order
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Pattern
Bit
Number
XXXX
XXXX
XXXX
XXXX
XXXX
XXX
XX
XXXX
XXX X
XXXX
XXXX
X
X
XX
XXXX
XXXX
XXXX
XXXX
XXX
XXXX
XXXX
XXXX
XXX
XXX X
XXXX
XXX X
XXXX
XX
XXXX
X
X
XXXX
XXXX
XXXX
XX
XXX
XXX X
XXX X
XXXX
XXXX
XXXX
XXX
XXXX
XXX X
XXX X
XXXX
XX
XXXX
X
X
XXXX
62415
31207
15603
40569
53057
59294
62415
31207
15603
40569
53057
59294
62415
31207
15603
40569
FEDCBA9876543210
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 59
Each word, then, would equal the decimal equivalent of the 16-bit
number. For this example, use 40569 for word 0, 15603 for word
1, and so on. In hexadecimal mode, these same words should read
9E79 for word 0, 3CF3 for word 1, and so on.
Masks
Masks act as an overlay to either reveal or overwrite the bits of a
PEL. In reference to bit planes, the mask can effectively separate
planes and protect certain ones. Masks affect only read and write
operations but do not affect the displayed PELs.
Bit Planes
The number of bits used to define the colors of a graphics system
also defines the number of bit planes. Masks control the CPU
reads and writes. By using LUT entries, the user can designate
which bits will actually draw to the screen. This capability
effectively produces backgrounds. For example, if a mask hides
the first four bits of all color values, the system draws colors using
only the last four bits. Colors defined using the first four bits can
be protected by suitably setting the LUTs. Switching among
more than one LUT can produce animation.
The following mask writes only PELs whose color-values
(indexes) are given as xOH, where x can equal 0 to F.
11 1 1 110
I
0
0
I
0
~
8·Bit Mask Value
-
Masked Bits
.....- - - - - -.. Written Bit
Color values such as 19H and B4H will write as lxH and BxH
respectively, where x leaves any previous draw untouched.
60 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
Area Pattern Mask
The command FILMSK affects the two Area Fill commands. The
8-bit value of FILMSK is ANDed with the value of MASK and
with each PEL value read in an Area Fill command. The
high-function graphics mode then compares the ANDed value to
the boundary color.
Clipping
The high-function graphics mode describes a clipping window and
a set of clipping planes. Both the VWPORT and WINDOW
command define a clipping border, for the screen and
two-dimensional virtual space, respectively. The clipping window
can change to include more or less of the image in
two-dimensional virtual space. The viewport clipping window
defines the area on the screen that is to contain the image.
Redefining the coordinates of the viewport allows several clipped
images to appear on the screen simultaneously.
In three-dimension, the high-function graphics mode adds hither
and yon clipping capabilities. The previously defined clipping
window projects forward and backward to define a clipping space.
The high-function graphics mode calculates all intersecting
clipping planes.
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© Copyright IBM Corporation 1984
Professional Graphics Controller 61
Viewing
Viewing involves selecting a viewing distance with the command
DIS TAN and a viewing angle with the command PROJCT.
WAIT
The command WAIT causes the system to pause for a specified
number of frame scan cycles. An imbedded Wait command will
hold the drawn image on the screen for a specified amount of time
before continuing with the program. The Wait command bases its
timing on frame time, which equals 1/60 of a second. Use this
value to calculate the actual wait period. For example, specifying
300 frame times would give a wait period of 5 seconds.
62 Professional Graphics Controller
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© Copyright IBM Corporation 1984
Drawing Primitives
The term drawing primitives defines a group of commands that
draw defined geometric shapes. The user specifies size and
position with the parameters associated with each command.
Two-Dimensional and Three-Dimensional Command Format
Two-dimensional commands use no numbers within the 6-letter
command. All three-dimensional commands end in the numeral
3. Coordinates for two-dimensional commands require one
variable each for the x and y values; the three-dimensional
commands require three coordinate values (one each for the x, y,
and z direction). Not all two-dimensional Draw commands have
a three-dimensional counterpart.
Move Commands
The Move commands change the current point in either the
two-dimensional or three-dimensional coordinate space, one
current point for each space. The commands MOVE and
MOVE3 specify a change using absolute coordinate values.
These commands use the virtual coordinate systems. MOVER
and MOVER3 change the current point by a relative amount,
adding the parameter values to the current point to produce a new
coordinate value as the current point.
Point
The Point command changes the PEL at the current point to the
current color.
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics ControUer 63
Vectors
Draw commands produce vectors (directed line segments)
between two specified points. The current-point value supplies
the first coordinate. The high-function graphics mode then draws
a vector ending at the absolute coordinate values given in a
DRAW or DRAW3 command or at the relative distance specified
by the parameters of a DRAWR or a DRAWR3 commands.
After a vector command, the current point shifts to the location
of the last PEL drawn. The following examples show vectors.
Parameter Point
Parameter Point
(x,y)
(xO+dx,yO+dy)
(xO,yO)
(xO,yO)
Current Point
Current Point
64 Professional Graphics Controller
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© Copyright IBM Corporation 1984
Linear Forms
The high-function graphics mode produces two closed linear
forms: rectangles and polygons. Two points define a rectangle.
The current point is one corner of the shape. The parameters,
given in absolute values (RECT) or in a relative, offset distance
(RECTR), specify the opposite corner. The current point does
not change for any rectangle command. Rectangles are specified
only in two dimensions. The following example shows rectangles:
(xO,yO)
Current Point
Parameter Point
Parameter Point
(x,y)
(xO+dx,yO+dy)
\
\
Rectangle
(xO,yO)
Current Point
\
Rectangle Relative
Each pair of coordinates in a Polygon command declares a vertex
of any multisided figure. Two pairs of coordinate values, adjacent
within a command's variable string, produce a side between them.
The command effectively draws multiple vectors, changing the
current point to the location of the last PEL drawn. This pattern
continues until a vector has been drawn to the last coordinate.
The final draw of the command connects the final coordinates
given to the beginning point of the polygon. The current point
returns to its original value. Again this command uses either
absolute or relative coordinates-POLY or POLYR for
two-dimensional, and POLY3 or POLYR3 for three-dimensional.
All relative coordinates are expressed relative to the original
point. Keep in mind that nonplanar values in three-dimensional
polygons may produce undesired effects.
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 65
The following is an example of a polygon.
(x4,y4)
Final Point
in Parameter List
Final
Draw
(xO,yO)
(xl,y1)
Note: The primitive fill flag in PRMFIL 1 directs the
high-function graphics mode to draw any of the above
rectangles or polygons as a solid (that is, all enclosed PELs
are set to the current color). Undesirable effects may occur
if the filled polygon intersects itself.
Nonlinear Forms
The high-function graphics mode also produces some nonlinear
geometric shapes. The commands CIRCLE and ELIPSE require
only radius values (both an x and y radius value for ELIPSE).
The current point specifies the center of both of these figures.
The parameters for the command ARC list a radius, a beginning
angle value, and an ending angle value. The current point also
serves as the center point of rotation for this command. The
command SECTOR has the same parameter requirements as an
ARC command, but produces a pie-shaped figure. That is, the
end-points of the arc connect with vectors to the center point of
rotation.
Except when used with the ARC command, a PRMFIL command
with the fill flag set on, will instruct the commands to produce
solid shapes filled with PELs of the current color. All nonlinear
commands draw only in two dimensions.
66 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
The following illustrations show examples of nonlinear forms.
Current Point
Current Point
ARC deg 0 deg 1 example
CI RCLE radius example
>Current Point
ELI PSE x radius y radius example
SECTOR deg 0 deg 1 example
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics ControUer 67
Area Fills
The Area Fill commands employ a seed point. Before sending an
Area Fill command, place the current point within the area to be
filled. The current color must differ from the color being
changed. The command AREA changes PELs outward in all
directions from the current (seed) point until is encountered a
color different from either the one being changed or the current
color. The command AREABC allows the user to specify a color
to act as a boundary. This command converts PELs from the
seed point outward until PELs of the same color as the specified
boundary color are encountered. The current color must differ
from the boundary color. The following is an Area Fill example.
Seed Point
Color 4
Color 1
Color 2
Boundary
Color 3
In the Area Fill example, set the current color to color 4. The
Area Fill will fill only the area covered by color 1. The Area
Boundary Fill specified with the boundary color set to color 3 will
fill the area covered by color 1 and color 2.
68 Professional Graphics Controller
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© Copyright IBM Corporation 1984
Text
Various Text commands help in placing and moving text. The
two-dimensional current point acts as a placement marker. For
justifying text, this point defines the horizontal and vertical
placement of the text string, using the command TJUST (see the
following). The default is H = 1, V = 1.
=~:~
I
'----------------------------'. v
Text String
=1
Altering the angle adjusts the slope of the centering point for each
letter but not the rotation of the letter itself. The command
TANGLE uses standard Cartesian coordinates to measure the
angle, as shown in the following.
deg 0
To adjust the text size, use the command TSIZE. The parameter
of this command specifies a two-dimensional virtual x-distance.
Keep in mind that the high-function graphics mode sizes letters
using the mapping of the window onto the viewport. For
example, a window of 320 PELs by 240 PELs mapped to a
viewport of 640 PELs by 480 PELs would draw size 8 letters in a
16-PEL horizontal space. All text that exceeds the viewport
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 69
boundary undergoes clipping. The default, size 8, writes a
character of 7 by 9 PELs in a cell of 8 by 12 PELs using one
column for horizontal spacing between letters (see the following).
~I~~------x--------~~~I
Use the commands TEXT or TEXTD to write text to the screen.
TEXT uses a default text font; TEXTD uses any text defined in
the command TDEFIN. This command requires a size
specification followed by a bit value to describe each line of
blocks. The first step is to outline an area that encompasses the
character (see the following).
Line
Line
Line
Line
Line
Number
Number
Number
Number
Number
5
4
3
2
1
_
_
_
_
_
x
X
X
7
X
X X
X
X
X
X
X X
X
6
5
X
X
X
X
4
3
2
1
0
~
Bit Number
Then list each bit; start with the bottom, leftmost block and work
to the right and up. The command for this character becomes:
TDEFIN 'x' 85
001 0 0 0 0 1
1 1 1 0 000 1
0010000 1
1 1 1 0 0 001
00111 1 1 0
70 Professional Graphics ControUer
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© Copyright IBM Corporation 1984
Command Lists
Command lists consist of a series of valid high-function graphics
commands executed by a single command. The commands
CLBEG and CLEND mark the beginning and end of command
lists. Two commands begin execution of command lists. CLRUN
executes a single command list once; CLOOP executes a single
command list a specified number of times. The commands
CLDEL and CLBEG delete a command list previously defined by
the specified parameter value. Space permitting, the user can
define up to 256 command lists. Any command, except CLBEG,
may appear within a command list definition. However, during
the execution of a command list, the high-function graphics mode
will not execute an imbedded CLDEL.
The following examples show valid formats for command lists.
CLBEG 8
CLEARS a
MOVE a a
PRMFIL 1
COLOR 2
SECTOR 100 60 359
MOVE 10 10
COLOR 3
SECTOR 90 0 59
CLEND
CLRUN 8
CLBEG 17
CLEARS a
PRMFIL 1
MOVER 10
COLOR 2
CIRCLE 5
CLEND
CLOOP 17 5
a
Command list 8 will draw two sectors of different colors.
Command list 17 will draw a small circle of radius 5. The
command CLOOP repeats command list 17 five times, thus
drawing five, small, tangential circles.
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 71
The following example shows an invalid format for a command
list.
CLBEG 23
CLEARS 0
CLBEG 1
CIRCLE 25
CLEND 2
CLDEL 14
CLEND
Command list 23 is invalid because:
•
CLBEG cannot appear within a stream of command list
commands.
•
If the high-function graphics mode receives CLRUN 23, the
execution of CLDEL command would produce an error.
72 Professional Graphics ControUer
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© Copyright IBM Corporation 1984
Look-Up Table
The look-up table (LUT) contains the red, green, and blue
intensity information associated with each color. A value, or
index, identifies each color. The high-function graphics mode
provides several default LUT selections, which are accessible with
the command LUTINT. The user can change values by using the
command LUT or by initializing a new table. The command
LUTSAV stores the current LUT values. LUTSAV overwrites
any previously saved LUT values. The saved values may be
selected by the command LUTINT 255. The following block
diagram illustrates LUT generation.
States
1
r
I
r
I
0
r
LUTINT 0
1
I
LUTINT 1
•
•
•
5
255
r
r
LUT Command
1
~
:>
"
~
l
I
I
LUTINT 5
LUTINT 255
I
I
-:;;
I
,,/
LUT
"-...
I
LUTSAV Command
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 73
Image Processing
The high-function graphics mode uses limited image-processing
techniques. The user can read or write a line of PEL data with
variable endpoints. The user specifies a line number and a
beginning and ending point within that line. The Image Read
command (IMAGER) returns the line data formatted as an Image
Write command (IMAGEW). This format makes it easier to use
stored image information. The following illustrates image
processing.
r----------------,~ Line 479
PELs
~
I
..................•. .....+--I
x1
t
PEL D
7 4 Professional Graphics ControUer
Monitor Screen
Specified Line
I
x2
t~ lineD
PEL 63°
August 15, 1984
© Copyright IBM Corporation 1984
Read-Back Commands
The high-function graphics mode allows the user to read various
parameters from the color board back to the program. Items
readable in this way include LUT entries, both three-dimensional
transformation matrixes, and the line pattern and line function
flags. The read-back protocol is straightforward. When the
high-function graphics mode executes one of the read-back
commands (for example, FLAGRD), it puts the value of the
requested item in the output buffer. In ASCII mode, the value is
written as a decimal number followed by a carriage-return
character. A high-level language, such as BASIC, need only
execute an Input statement to get the data from the color board.
Some data read-back commands return more than one value. The
individual commands describe the format of the return in both
ASCII and hexadecimal communication modes.
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 75
The following table lists the flags readable by FLAGRD, and the
size and type of the value returned.
Flag
Name
Type of Value
Returned
16 integers
1 integer (byte)
1
AREAPT
2
CLiPH
3
4
CLiPY
COLOR
DISPLA
1 integer (byte)
1 integer (byte)
6
7
DISTAN
DISTH
1 real number
1 real number
8
9
10
DISTY
FILMSK
1 real number
1 integer (byte)
LlNFUN
1 integer (byte)
11
12
LlNPAT
1 integer
MASK
1 integer (byte)
13
14
MDORG
2D current point
3 real numbers
2 real numbers
15
3D current point
16
17
PRMFIL
3 real numbers
1 integer (byte)
5
1 integer (byte)
PROJCT
TANGLE
TJUST
1 integer (byte)
20
TSIZE
1 real number
21
VWPORT
4 integers
22
23
VWRPT
WINDOW
3 real numbers
4 real numbers
24
Transformed 3D
current point
3 real numbers
25
Free memory
available
1 integer
18
19
1 word
2 integers
(bytes)
The command LUTRD reads back the red, green, and blue
intensity levels for a particular LUT index. To read back either
the viewing matrix [V] specified in the command VWMATX, or
the modeling matrix [M] specified in the command MDMATX,
use the command MATXRD. This command returns a string of
16 values. These values of the 4-by-4 matrix begin at the
upper-left corner and read across the rows.
76 Professional Graphics Controller
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© Copyright IBM Corporation 1984
System Reset
The command RESETF resets all flags. The following table lists
the default values of all flags that can be reset.
Flag
Name
Default Value
1
AREAPT
65535 16 times
Solid area
2
CLiPH
FlaQ = 0
Disabled
3
CLiPY
FlaQ = 0
Disabled
4
COLOR
Value = 255
No change after a RESETF
5
DISPLA
6
DISTAN
Distance = 500
7
DISTH
Distance = -30000
8
DISTY
Distance = 30000
9
FILMSK
Mask = 255
No PEL draw
effect
10
LlNFUN
Function = 0
Replacement
mode
11
LIN PAT
Pattern = 65535
Solid line
12
MASK
Mask = 255
All planes
enabled
OX = OY = OZ = 0
13
MDORG
14
2D current point
X=Y=O
15
3D current point
X=Y=Z=O
16
PRMFIL
Flag = 0
17
PROJCT
Angle = 60
18
TANGLE
Angle = 0
Horizontal,
left-right text
19
TJUST
H=V=1
Left, bottom
justification
20
TSIZE
Size = 8
12 by 8 cell
characters
21
VWPORT
0,639,0,479
22
VWRPT
X=Y=Z=O
23
WINDOW
-320,319, -240, 239
24
Transformed 3D
current point
X=Y=Z=O
August 15, 1984
© Copyright IBM Corporation 1984
Primitive fill off
Entire screen
Professional Graphics Controller 77
Communications
The Professional Graphics Controller accepts high-function
graphics commands in either ASCII or hexadecimal format. In
ASCII mode, English-like commands and their parameters are
sent to the board as ASCII character strings. This allows easy
transmission of instructions from such high-level languages as
BASIC. For example, to draw a circle of radius 55.05 centered at
the screen center, execute a BASIC statement to transmit the
following character string:
MOVE 0,0 CIRCLE 55.05
In hexadecimal communication mode, the commands are sent as a
stream of bytes for greatest throughput. The statement above
could be sent in hexadecimal mode as
10 00 00 00 00 00 00 00 00 38 37 00 CD OC
to realize substantial time savings.
ASCII Communications
ASCII mode commands are sent in a format designed to
accommodate the restriction of a high-level language. The ASCII
command consists of a command word (no more than six letters
in length) and parameters, if applicable. Every command word
has a short form, which is always three characters or less in
length. Parameters may be either decimal numbers or text strings
enclosed in quotes.
Commands and parameters in a command line are separated by
delimiters. A delimiter is one or more of the following, except
when enclosed by quotation marks:
•
•
•
•
•
•
Space
Tab
Comma
Semicolon
Hyphen
Plus sign
78 Professional Graphics Controller
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© Copyright IBM Corporation 1984
Commands and parameters consist of letters, numbers, and
decimal points. Any other character, except when enclosed in
quotes, is illegal and will be ignored.
When a hyphen immediately precedes a numeric parameter, that
number is interpreted as negative.
Examples of Legal Commands:
"CI 5"
"RECT 67-88"
"COLOR 2 FLOOD 3"
"LUTRD 3"
Draw a circle of radius 5.
Draw a rectangle.
Change the current color to 2,
and flood the screen to the color 3.
Read LUT entry 3.
Examples of Illegal Commands:
"CIR 5"
"RECT%67,-68"
"COLOR 2 4 FLOOD 3"
"LUTRD 3.4"
August 15,1984
© Copyright IBM Corporation 1984
CIR is not a valid abbreviation.
"%" is not a legal character.
COLOR takes only one parameter.
The parameter to the LUTRD command
is an integer.
Professional Graphics Controller 79
Communication Protocol
The high-function graphics data is sent and received as a
sequential stream of bytes. To realize maximum throughput
between the system and the Professional Graphics Controller, a
first-in-first-out (FIFO) buffer protocol has been set up. This
protocol must be adhered to for proper transmission and
reception. These buffers, and their associated pointers and flags,
are directly addressable when the system uses addresses in the
hexadecimal range C6000 to C63FF.
There are three channels through which data may pass to and
from the controller. From the system's point of view, these
channels are 'output' (for sending commands and parameters),
'input' (for receiving data read-back commands), and 'error' (for
receiving high-function graphics-generated error and warning
codes). Each channel has a FIFO buffer associated with it and
each buffer has 256 bytes reserved in the lK-byte communication
area. A portion of the remaining 256 bytes is reserved for three
sets of buffer pointers-one pair for each channel-as well as the
warm and cold restart and diagnostic flags. The following
memory map shows the addresses as seen by the system.
Memory
Address
(in hex)
Function
C6000
Output FIFO (256 bytes)
C6100
Input FIFO (256 bytes)
C6200
Error FIFO (256 bytes)
C6300
Output FIFO Write Pointer
C6301
Output FIFO Read Pointer
C6302
Input FIFO Write Pointer
C6303
Input FIFO Read Pointer
C6304
Error FIFO Write Pointer
C6305
Error FIFO Read Pointer
C6306
Cold Restart Flag
C6307
Warm Restart Flag
C6308
Error Enable Flag
80 Professional Graphics Controller
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© Copyright IBM Corporation 1984
Each buffer has a one-byte read pointer and a one-byte write
pointer, which refer to buffer locations relative to the base of the
buffer in question. The read pointer always points to the next
byte to be read; the write pointer always points to the next byte
to be written. The buffer is empty when the read pointer is equal
to the write pointer, because the byte that would be read has not
yet been written. Alternately, the buffer is full when the write
pointer is one less than the read pointer.
A FIFO write must be done as follows:
1.
Ensure the buffer has room by comparing the write
pointer to the read pointer. If the read pointer is only
one greater than the write pointer, there is no room, and
no writing may take place until there is room.
2.
Write one byte to the address specified by that buffer's
base address plus the value in its write pointer.
3.
Increment the write pointer, modulo-255.
More than one byte may be written if the buffer's write pointer is
increased by the same number as the number of bytes written.
A FIFO read must be done as follows:
1.
Ensure the buffer has data by comparing the write
pointer to the read pointer. If the read pointer is equal
to the write pointer, the buffer is empty, and no reading
may take place until there is data to be read.
2.
Read one byte from the address specified by that
buffer's base address plus the value in its read pointer.
3.
Increment the read pointer, modulo-255.
More than one byte may be read if the buffer's read pointer is
increased by the same number as the number of bytes read.
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 81
Error Handling
The high-function graphics mode provides an error-reporting
capability. If the host sets the error-enable flag in the
communication area, the high-function graphics mode returns
errors in the error buffer. In ASCII mode, the error is returned as
a message, such as "Arithmetic Overflow." In hexadecimal mode,
the error is returned as a single byte code.
82 Professional Graphics Controller
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© Copyright IBM Corporation 1984
High-Function Graphics Commands
The high-function graphics commands can be logically grouped
into the following categories:
•
•
•
•
Two-Dimensional Drawing
ARC (AR) Arc
CIRCLE (CI) Circle
DRAW (D) Draw
DRAWR (DR) Draw Relative
ELIPSE (EL) Ellipse
MOVE (M) Move
MOVER (MR) Move Relative
POINT (PT) Point
POLY (P) Polygon
POLYR (PR) Polygon Relative
RECT (R) Rectangle
RECTR (RR) Rectangle Relative
SECTOR (S) Sector
Three-Dimensional Drawing
DRAW3 (D3) Draw in 3D
DRAWR3 (DR3) Draw Relative in 3D
MOVE3 (M3) Move in 3D
MOVER3 (MR3) Move Relative in 3D
POINT3 (PT3) Point in 3D
POLY3 (P3) Polygon in 3D
POLYR3 (PR3) Polygon Relative in 3D
Modeling Transformations
MATXRD (MRD) Matrix Read
MDIDEN (MDI) Modeling Identity
MDMATX (MDM) Modeling Matrix
MDORG (MDO) Modeling Origin
MDROTX (MDX) Modeling Rotate X Axis
MDROTY (MDY) Modeling Rotate Y Axis
MDROTZ (MDZ) Modeling Rotate Z Axis
MDSCAL (MDS) Modeling Scale
MDTRAN (MDT) Modeling Translation
Viewport/Window /Projection
CLIPH (CH) Clip Hither
CLIPY (CY) Clip Yon
CONVRT (CV) Convert
DISTAN (DS) Distance
DISTH (DH) Distance Hither
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 83
•
•
•
•
DISTY (DY) Distance Yon
PROJCT (PRO) Projection
VWIDEN (VWI) Viewing Identity
VWMATX (VWM) Viewing Matrix
VWPORT (VWP) Viewport
VWROTX (VWX) Viewing Rotate X Axis
VWROTY (VWY) Viewing Rotate Y Axis
VWROTZ (VWZ) Viewing Rotate Z Axis
VWRPT (VWR) Viewing Reference Point
WINDOW (WI) Window
Command List
CLBEG (CB) Command List Begin
CLDEL (CD) Command List Delete
CLEND (CE) Command List End
CLOOP (CL) Command List Loop
CLRD (CRD) Command List Read
CLRUN (CR) Command List Run
Mode Set/Read
CA (CA) Communications ASCII
CX (CX) Communications Hexadecimal
DISPLA (DI) Display
FLAGRD (FRD) Flag Read
RESETF (RF) Reset Flags
WAIT (W) Wait
Color/Fills/Patterns
AREA (A) Area Fill
AREABC (AB) Area Fill to Boundary Color
AREAPT (AP) Area Pattern
CLEARS (CLS) Clear Screen
COLOR (C) Color
FLOOD (F) Flood
FILMSK (FM) Fill Mask
LINFUN (LF) Line Function
LINP A T (LP) Line Pattern
MASK (MK) Mask
PRMFIL (PF) Primitive Fill
Image Transmission
IMAGER (IR) Image Read
IMAGEW (IW) Image Write
84 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
•
•
Look-Up Table Operations
LUT (L) Look-Up Table
LUTINT (LI) Look-Up Table Initialize
LUTRD (LRD) Look-Up Table Read
LUTSA V (LS) Look-Up Table Save
Text
TANGLE (T A) Text Angle
TDEFIN (TD) Text Define
TEXT (T) Text
TEXTP (TP) Text Programmed
TJUST (TJ) Text Justify
TSIZE (TS) Text Size
The high-function graphics commands appear on the following
pages in alphabetic order.
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 85
ARC
(Arc)
Purpose:
Draw an arc in two dimensions.
Command:
ARC radius degO degl
Description:
ARC draws the arc of a circle in the current color.
The center is at the current point. The radius is
specified in the attribute radius, starting at the
angle given in degO and ending at the angle given
in deg 1. The angles are expressed in degrees and
are measured counterclockwise from a ray that is
parallel to the X axis, starting at the origin and
going toward increasing X values. Radius values
are real numbers and may range from -8191 to
8191. Start and end angles are treated as
modulo-360. If radius is negative, 180 degrees are
added to both angles.
Short Form:
AR radius de gO degl
Hex Format:
3C
lowradius
lowfracradius
10wdegO
lowdegl
highradius
highfracradius
highdegO
highdegl
Example:
ASCII: AR 50.25 45 135
HEX:
Errors:
3C 32 00 00 40 20 00 87 00
Radius too large
86 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
AREA
(Area Fill)
Purpose:
Random area fill.
Command:
AREA
Description:
AREA sets all PELs in a given closed region to the
current color. The region extends from the
two-dimensional current point outward in all
directions until reaching a boundary of PELs
whose colors differ from the original color of the
PEL at the current point and the current color.
The region to be filled must be continuous. All
data read is ANDed against the fill mask and the
mask to compare colors. The original color should
not be equal to the current color.
Short Form:
A
Hex Format:
CO
Example:
ASCII: A
HEX:
Errors:
CO
None
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 87
AREABC
(Area Fill to Boundary Color)
Purpose:
Random area fill to the boundary color.
Command:
AREABC bcolor
Description:
AREABC sets all PELs in a given closed region to
the current color under mask. The region extends
from the two-dimensional current point outward
until reaching a boundary of PELs with the color
specified by bcolor. Bcolor must be different from
the current color. All data read is ANDed against
the fill mask and the mask for boundary
comparison.
Short form:
AB bcolor
Hex Format:
Cl bcolor
Example:
ASCII: AB 4
HEX;
Errors:
C1 04
Boundary = current color
88 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
AREAPT
(Area Pattern)
Purpose:
Define an area pattern mask.
Command:
AREAPT pattern
Description:
AREAPT defines the area pattern mask. The 16
pattern mask words define a 16-by-16 PEL array
to be repeated horizontally and vertically when
drawing filled figures. Setting all bits in the mask
(sending 16 words of 65535) causes areas to be
filled solidly; this is the default after a reset.
Short Form:
AP pattern
Hex Format:
E7
10wpO
lowp2
lowp4
lowp6
lowp8
lowp 10
highpO
highp2
highp4
highp6
highp8
highp 10
lowpl
lowp3
lowp5
lowp7
lowp9
lowp 11
highpl
highp3
highp5
highp7
highp9
highp 11
lowp 12 highp 12 lowp 13 highp 13
lowp 14 highp 14 lowp 15 highp 15
Example:
Errors:
ASCII: AP 52428
52428
52428
52428
52428
52428
52428
52428
13107
13107
13107
13107
13107
13107
13107
13107
HEX:
CC
CC
CC
CC
33
33
33
33
33
33
33
33
E7 CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
33
33
33
33
33
33
33
33
None
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 89
CA
(Communications ASCII)
Purpose:
Set the communication mode to ASCII.
Command:
CA
Description:
This command may be given in either ASCII or
hexadecimal mode.
Short Form:
CA
Hex Format:
43 41 20
Note: This is the hexadecimal equivalent of the three ASCII
characters "CA ".
Example:
ASCII: CA
HEX:
Errors:
43 41 20
None
90 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
CIRCLE
(Circle)
Purpose:
Draw a circle in two dimensions.
Command:
CIRCLE radius
Description:
CIRCLE draws a circle of a given radius, with its
center at the current point. The circle is drawn in
the current color and is filled if the PRMFIL flag
is set (see "PRMFIL"). Nothing is drawn if the
radius value is outside the range of -8191 to 8191.
Short Form:
CI radius
Hex Format:
38
lowradius
lowfracradius
highradius
highfracradius
Example:
ASCII: CI 25.5 5 135
HEX:
Errors:
38 19 00 00 80
Radius too large
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 91
CLBEG
(Command List Begin)
Purpose:
Begin command-list definition.
Command:
CLBEG c1ist
Description:
CLBEG begins the definition of the command list
specified by clist. Commands sent later to the
controller are saved in the command-list definition
area for execution (see "CLRUN" and
"CLOOP"). CLEND ends the command-list
definition. clist may be from 0 to 255. Any
previous definition of the command-list is erased.
Short Form:
CB clist
Hex Format:
70 c1ist
Example:
ASCII: CLBEG 1
HEX:
Errors:
70 01 07 02 06 01 30 00 C8 00 00 71
Not enough memory; command list running
92 Professional Graphics Controller
August 15,1984
© Copyright IBM Corporation 1984
CLDEL
(Command List Delete)
Purpose:
Delete the definition of a command list.
Command:
CLDEL clist
Description:
CLDEL deletes the definition of the command list
specified by clist. It also reclaims command-list
memory for other definitions. clist may be from 0
to 255.
Short Form:
CD clist
Hex Format:
74 clist
Example:
ASCII: CD 3
HEX:
Error:
74 03
Command list running
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics ControUer 93
CLEARS
(Clear Screen)
Purpose:
Clear the screen to a given color.
Command:
CLEARS color
Description:
Sets every PEL in the high-function graphics
display buffer to the color specified by color
regardless of the mask. This command does not
change the current color. It is similar, but not
identical, to the command FLOOD.
Short Form:
CLS color
Hex Format:
OF color
Example:
ASCII: CLS 23
HEX:
Errors:
OF 17
None
94 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
CLEND
(Command List End)
Purpose:
End the definition of a command-list.
Command:
CLEND
Description:
CLEND ends the definition of a command-list.
When the controller receives a CLEND, it resumes
executing commands as they are received.
Short Form:
CE
Hex Format:
71
Example:
ASCII: CE
HEX:
Errors:
71
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 95
CLIPH
(Clip Hither)
Purpose:
Set the hither clip flag.
Command:
CLIPH flag
Description:
CLIPH enables or disables hither clipping. Hither
clipping is enabled when flag is 1 or any odd
number, and disabled when flag is 0 or any even
number (default). Three-dimensional drawing
commands draw faster when hither clipping is
disabled.
Short Form:
CH flag
Hex Format:
AA flag
Example:
ASCII: CH
HEX:
Errors:
a
AA 01
None
96 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
CLIPY
(Clip Yon)
Purpose:
Set the yon clip flag.
Command:
CLIPY flag
Description:
CLIPY enables or disables yon clipping. Yon
clipping is enabled when flag is 1 or any odd
number, and disabled when flag is 0 or any even
number (default). Three-dimensional drawing
commands draw faster when yon clipping is
disabled.
Short Form:
CY flag
Hex Format:
AB flag
Example:
ASCII: CY 0
HEX:
Errors:
AB 01
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 97
CLOOP
(Command List Loop)
Purpose:
Repeat execution of a command list.
Command:
CLOOP c1ist count
Description:
CLOOP executes the command list specified by
clist, for the number of times specified by count.
clist may be between 0 and 255; count can be from
o to 65535.
Short Form:
CL c1ist count
Hex Format:
73 c1ist lowcount highcount
Example:
ASCII: CL 1 1000
HEX:
Errors:
73 01 E8 03
Command list running; stack full.
98 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
CLRD
(Command List Read)
Purpose:
Read back command list.
Command:
CLRD clist
Description:
In hexadecimal mode, a word representing the
number of bytes in the command list is read back
(zero if the list is undefined), followed by the
bytes as they are stored.
Short Form:
CRD clist
Hex Format:
75 clist
Example:
ASCII: CRD 1
HEX:
Errors:
75 01
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 99
CLRUN
(Command List Run)
Purpose:
Execute command list.
Command:
CLRUN dist
Description:
CLRUN executes commands in the command list
specified by clist. clist must be from 0 to 15.
Short Form:
CR clist
Hex Format:
72 clist
Example:
ASCII: CR 14
HEX:
Errors:
72 01
Command list running; stack full; nested
command list
100 Professional Graphics Controller ©
August 15, 1984
Copyright IBM Corporation 1984
COLOR
(Color)
Purpose:
Set the current color.
Command:
COLOR value
Description:
COLOR sets the current color to that specified by
value. All noncomplement mode drawing is done
in the current color. All drawing, including
complement mode, is subject to MASK and
FILMSK. value is treated as modulo-256.
Short Form:
C value
Hex Format:
06 value
Example:
ASCII: C 2
HEX:
Errors:
06 02
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 101
CONVRT
(Convert)
Purpose:
Convert three dimension to two dimension.
Command:
CONVRT
Description:
CONVRT converts the three-dimensional current
point to two-dimensional virtual coordinates, using
the current transformation matrixes. The result is
left in the two-dimensional current point.
Short Form:
CV
Hex format:
AF
Example:
ASCII: CV
HEX:
Errors:
AF
Arithmetic overflow
102 Professional Graphics Controller ©
August 15, 1984
Copyright IBM Corporation 1984
CX
(Communications Hexadecimal)
Purpose:
Set the communication mode to hexadecimal.
Command:
ex
Description:
This command may be given in either ASCII or
hexadecimal mode.
Short Form:
ex
Hex Format:
43 58 20 •
Note: This is the hexadecimal equivalent of the three ASCII
characters "CA ".
Example:
ASCII: CX
HEX:
Errors:
43 58 20
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics ControUer 103
DISPLA
(Display)
Purpose:
Select the display mode.
Command:
DISPLA flag
Description:
DISPLA selects a screen for display. If flag is 0,
the color high-function graphics screen is
displayed. If flag is 1, the emulator screen is
shown. Color graphics commands are accepted
and executed, no matter which screen is displayed.
Short Form:
DI flag
Hex Format:
DO flag
Example:
ASCII: DI 0
HEX:
Errors:
DO 01
None
104 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
DISTAN
(Distance)
Purpose:
Define the distance to the viewing reference point.
Command:
DISTAN dist
Description:
DISTAN defines the distance (dist) from the eye
to the viewing reference point.
Short Form:
DS dist
Hex Format:
B1
lowdist
lowfracdist
highdist
highfracdist
Example:
ASCII: OS 1200
HEX:
Errors:
B1 BO 04 9A 59
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics
Controll~r
lOS
DISTH
(Distance Hither)
Purpose:
Define the hither clip plane.
Command:
DISTH dist
Description:
DISTH defines the distance to the hither clip plane
from the viewing reference point. The hither clip
plane is parallel to the view plane, and the distance
(dist) is relative. When hither clipping is enabled,
no points before the hither clip plane are
displayed. Hither clipping affects only
three-dimensional drawing commands.
Short Form:
DH dist
Hex Format:
A8
lowdist
lowfracdist
highdist
highfracdist
Examples:
ASCII: DH 15.01
HEX:
Errors:
A8 OF 00 8F 02
None
106 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
DISTY
(Distance Yon)
Purpose:
Define the yon clip plane.
Command:
DISTY dist
Description:
DISTY defines the distance to the yon clip plane
from the viewing reference point. The yon clip
plane is parallel to the view plane, and the distance
(dist) is relative. When yon clipping is enabled, no
points beyond the yon clip plane are displayed.
Yon clipping affects only three-dimensional
drawing commands.
Short Form:
DY dist
Hex Format:
A9
lowdist
lowfracdist
highdist
highfracdist
Example:
ASCII: DY 15.999
HEX:
Errors:
A9 OF 00 BE FF
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 107
DRAW
(Draw)
Purpose:
Absolute draw in two dimensions.
Command:
DRAW x y
Description:
DRAW draws a line from the current point to the
point specified by x,y. The current point moves to
the x and y value.
Short Form:
D xy
Hex Format:
28
lowx
lowfracx
lowy
lowfracy
highx
highfracx
highy
highfracy
Example:
ASCII: D 23.5 -90.71
HEX:
Errors:
20 17 00 00 80 A5 FF C3 85
Arithmetic overflow
108 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
DRAWR
(Draw Relative)
Purpose:
Relative draw in two dimensions.
Command:
DRAWR dx dy
Description:
DRAWR draws a line from the current point to a
point dx,dy from the current point. The current
point moves to the end point of the line.
Short Form:
DR dx dy
Hex Format:
29
lowdx
lowfracdx
lowdy
lowfracdy
highdx
highfracdx
highdy
highfracdy
Example:
ASCII: DR 65.8 12.2
HEX:
Errors:
21 41 00 CD CC OC 00 34 33
Arithmetic overflow
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 109
DRAW3
(Draw in 3D)
Purpose:
Draw absolute in three dimensions.
Command:
DRAW3 x y z
Description:
DRAW3 draws a line from the current point to the
point in the three-dimensional space given. After
the draw, the current point moves to x,y,z.
Short Form:
D3 x y z
Hex Format:
2A
lowx
lowfracx
lowy
lowfracy
lowz
lowfracz
highx
highfracx
highy
highfracy
highz
highfracz
Example:
ASCII: 03 943, -266, 100
HEX:
Errors:
22 AF 03 00 00 F6 FE 00 00 64 00 00 00
Arithmetic overflow
110 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
DRAWR3
(Draw Relative in 3D)
Purpose:
Draw relative in three dimensions.
Command:
DRAWR3 dx dy dz
Description:
DRAWR3 draws a line to the point offset from the
current point by dX,dy,dz and moves the current
point to this new point.
Short Form:
DR3 dx dy dz
Hex Format:
2B
lowdx
lowfracdx
lowdy
lowfracdy
lowdz
lowfracdz
highdx
highfracdx
highdy
highfracdy
highdz
highfracdz
Example:
ASCII: DR3 835.02 44.62 98
HEX:
Errors:
23 43 03 IF 05 2C 00 B8 9E 62 00 00 00
Arithmetic overflow
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 111
ELIPSE
(Ellipse)
Purpose:
Draw an ellipse in two dimensions.
Command:
ELIPSE xradius yradius
Description:
ELIPSE draws an ellipse centered on the
two-dimensional current point whose x and y axis
lengths are given in xradius and yradius. The
ellipse is filled if the PRMFIL flag is set.
Short Form:
EL xradius yradius
Hex Format:
39
lowxradius
lowfracxradius
lowyradius
lowfracyradius
highxradius
highfracxradius
highyradius
highfracyradius
Example:
ASCII: EL 50 100
HEX:
Errors:
39 25 00 00 80 19 00 00 00
Radius too large
112 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
FILMSK
(Fill Mask)
Purpose:
Set area fill mask.
Command:
FILMSK mask
Description:
FILMSK sets the 8-bit area fill mask to mask. All
PELs read by the Area Fill commands are ANDed
against this mask, and also MASK, before
comparison with the boundary color.
Short Form:
FM mask
Hex Format:
EF mask
Example:
ASCII : FM 254
HEX:
Errors:
EF FE
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 113
FLAGRD
(Flag Read)
Purpose:
Read flag value.
Command:
FLAGRD flag
Description:
FLAGRD loads the current value of the flag
specified by flag into the output buffer for later
reading by the host. The flag numbers assigned
are as follows.
Flag
Name
Type of Value
Returned
1
2
AREAPT
CLiPH
16 inteRers
1 integer (byte)
3
CLiPY
1 integer (byte)
4
5
COLOR
DISPLA
1 integer (byte)
1 integer (byte)
6
7
DISTAN
1 real number
DISTH
8
9
10
DISTY
FILMSK
LlNFUN
1 real number
1 real number
11
LlNPAT
12
13
MASK
MDORG
14
15
2D current point
3D current point
16
17
PRMFIL
PROJCT
18
TANGLE
19
TJUST
20
TSIZE
21
VWPORT
22
VWRPT
WINDOW
23
24
25
Transformed 3D
current point
Free memory
available
114 Professional Graphics Controller
1 integer (byte)
1 integer (byte)
1 integer
1 integer (byte)
3 real numbers
2 real numbers
3 real numbers
1 integer (byte)
1 integer (byte)
1 word
2 integers
(bytes)
1 real number
4 integers
3 real numbers
4 real numbers
3 real numbers
1 integer
August 15, 1984
© Copyright IBM Corporation 1984
Each value is read in the same order as provided to
the command that sets it. For example, the
three-dimensional current point is read as one real
number each for x, y, and z. In ASCII mode,
commas separate multiple return values, with a
carriage return at the end.
Short Form:
FRD flag
Hex Format:
51 flag
Example:
ASCII: FRO 3
HEX:
Error:
51 03
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 115
FLOOD
(Flood)
Purpose:
Flood the screen to the color given.
Command:
FLOOD color
Description:
FLOOD sets every PEL in the defined viewport,
to the color specified by color subject to MASK.
This command does not change the current color.
Short Form:
F color
Hex Format:
07 color
Example:
ASCII: F 4
HEX:
Errors:
07 04
None
116 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
IMAGER
(Image Read)
Purpose:
Read image from the display.
Command:
IMAGER line xl x2
Description:
IMAGER reads a line from the image being
displayed. If the communication mode is ASCII
(CA) the image is placed in the output buffer as
one ASCII number for each PEL, separated by
carriage returns. If communication is in
hexadecimal mode (CX) the image output is in a
run-length encoded format. line, xl, and x2 are
expressed in PELs measured from the lower-left
corner of the screen.
Short Form:
IR line xl x2
Hex Format:
D8
lowline highline
lowxl
highxl
lowx2 highx2
Example:
ASCI I: IR 100
a 127
HEX: 08 64 00 00 00 7F 00
Errors:
Value out of range
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 117
IMAGEW
(Image Write)
Purpose:
Write image to the display.
Command:
IMAGEW line xl x2
Description:
IMAGEW writes a line of PELs to the display. If
communication is in ASCII (CA) each parameter
represents one PEL. If communication is in
hexadecimal (CX) the image is sent in run-length
encoded format. line, xl, and x2 are expressed in
PELs measured from the lower-left corner of the
screen.
Short Form:
IW line xl x2
Hex Format:
D9
lowline highline
lowxl
highxl
lowx2 highx2
data
Example:
ASCII: IW 100 50 60
HEX:
Errors:
09 64 00 32 00 3C 00 82 2C
18 42 03 OC 01 OE 81 18 2C
Value out of range
118 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
LINFUN
(Line Function)
Purpose:
Select drawing function.
Command:
LINFUN function
Description:
LINFUN sets the drawing function to that
specified by function. Available functions are:
o
Draw by writing PELs of the current color
(default).
1
Draw by complementing PEL. The current
color will be ignored.
Note: With both functions, drawing is subject
to MASK and FILMSK where appropriate.
Short Form:
LF function
Hex Format:
EB function
Example:
ASCII: LF 0
HEX:
Errors:
EB 00
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics ControUer 119
LINPAT
(Line Pattern)
Purpose:
Set line pattern.
Command:
LINP AT pattern
Description:
LINP AT sets the line-drawing pattern from a
16-bit number. The line pattern is used to
implement dotted or dashed lines. As each PEL is
generated, the line-pattern mask is rotated right.
If there is a 1 in the least-significant bit (LSB), a
PEL is drawn. If that bit is a 0 then no PEL is
drawn and the background remains visible. A
line-pattern mask of alII's (65535) produces solid
lines, and is the default following a RESETF. The
line pattern affects the following commands except
when drawing a filled primitive:
ARC, CIRCLE, DRAW, DRAW3, DRAWR,
DRAWR3, ELIPSE, POLY, POLY3, POLYR,
POLYR3, RECT, RECTR, SECTOR
Short Form:
LP pattern
Hex Format:
EA lowpattern highpattern
Example:
ASCII: LP 65280
HEX:
Errors:
EA 00 FF
None
120 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
LUT
(Look-Up Table)
Purpose:
Set an entry in the look-up table.
Command:
LUT index r g b
Description:
LUT loads red, green, and blue intensity levels
into the LUT entry specified by index. Intensity
values are treated as modulo-16 numbers.
Short Form:
L index r g b
Hex Format:
EE index r g b
Example:
ASCII: L 3 0 15 0
HEX:
Errors:
EE 04 00 00 OF
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 121
LUTINT
(Look-Up Table Initialize)
Purpose:
Initialize the look-up table.
Command:
LUTINT state
Description:
LUTINT sets the LUT to one of the following
states specified by state:
State
a
Color-cone distribution
1
Foreground/background colors in the low
4-bits of a value code will be visible only if
the hiah 4-bits is a (or "invisible")
Value codes interpreted as: R R G G G B B B
2
3
4
5
255
Value codes interpreted as: R R R G G B B B
Value codes interpreted as: R R R G G G B B
6-level RGB
Load LUT from LUT storage area (opposite
of LUTSAV)
Short Form:
LI state
Hex Format:
Ee state
Example:
ASCII: LI 4
HEX:
Errors:
EC 04
Value out of range
122 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
LUTRD
(Look-Up Table Read)
Purpose:
Read the look-up table entry.
Command:
LUTRD index
Description:
LUTRD loads the red, green, and blue entries at
the LUT entry specified by index into the output
buffer for reading by the host.
In ASCII mode, the LUT entries are read as red,
green, and blue intensities, separated by commas,
and ended by a carriage return.
In hexadecimal mode, the LUT entries are read
one byte for each entry for a total of three bytes.
Short Form:
LRD index
Hex Format:
50 index
Example:
ASCII: LRD 2
HEX:
Errors:
50 02
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 123
LUTSAV
(Look-Up Table Save)
Purpose:
Save the look-up table in the look-up table storage
area.
Command:
LUTSA V
Description:
LUTSA V saves all 256 LUT entries in the LUT
storage area. These values may be reloaded with a
"LUTINT 255" command. Each LUTSA V
overwrites any previous LUTSA V.
Short Form:
LS
Hex Format:
ED
Example:
ASCII: LS
HEX:
Errors:
ED
None
124 Professional Graphics Controller
August 15,1984
© Copyright IBM Corporation 1984
MASK
(Mask)
Purpose:
Set bit-plane mask.
Command:
MASK planemask
Description:
MASK sets the 8-bit, read/write, bit-plane mask
to the value specified by planemask. A zero in any
position in the mask means that no bits in that
plane are written to; when read, bits in that plane
return zero. Because of the organization of
display memory, the fastest drawing speed occurs
whenplanemask is FF, OF, or FO.
Short Form:
MK planemask
Hex Format:
E8 plane mask
Example:
ASCII: MK 15
HEX:
Errors:
E8 OF
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 125
MATXRD
(Matrix Read)
Purpose:
Read the matrix contents.
Command:
MATXRD matrix
Description:
MATXRD reads the contents of the 4-by-4 matrix
specified by matrix into the output buffer for later
reading by the host. The matrix number
assignments are:
1
Three-dimensional modeling transformation
matrix
2
Three-dimensional viewing transformation
matrix
In ASCII mode, the matrix entries are read in four
lines. Each line has four entries separated by
commas.
In hexadecimal mode, four bytes for each matrix
entry are read, for a total of 64 bytes. The reading
order is:
123
567
9 10 11
13 14 15
Short Form:
MRD matrix
Hex Format:
52 matrix
4
8
12
16
Example:
ASCII: MRD 1
HEX:
Errors:
52 01
Value out of range
126 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
MDIDEN
(Modeling Identity)
Purpose:
Reset the modeling transformation matrix.
Command:
MDIDEN
Description:
MDIDEN sets the modeling transformation matrix
to the identity matrix.
Short Form:
MDI
Hex Format:
90
Example:
ASCII: MOl
HEX:
Errors:
90
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 127
MDMATX
(Modeling Matrix)
Purpose:
Define the modeling matrix.
Command:
MDMATX array
Description:
MDMATX loads the modeling matrix directly
from the 4-by-4 real-number array.
Short Form:
MDM array
Hex Format:
97 lowmll
lowm12
lowm13
lowm14
lowm21
lowm22
lowm23
lowm24
lowm31
lowm32
lowm33
lowm34
lowm41
lowm42
lowm43
lowm44
highmll
highm12
highm13
highm14
highm21
highm22
highm23
highm24
highm31
highm32
highm33
highm34
highm41
highm42
highm43
highm44
lowfracmll
lowfracm12
lowfracm13
lowfracm14
lowfracm21
lowfracm22
lowfracm23
lowfracm24
lowfracm31
lowfracm32
lowfracm33
lowfracm34
lowfracm41
lowfracm42
lowfracm43
lowfracm44
highfracm 11
highfracm 12
highfracm 13
highfracm 14
highfracm21
highfracm22
highfracm23
highfracm24
highfracm31
highfracm32
highfracm33
highfracm34
highfracm41
highfracm42
highfracm43
highfracm44
Example:
ASCII: MOM 68.25 12.5
253
17
65503 0.25
306.75 34.5
0
8418 324.75 1.25
313.5 50
1. 25
1
HEX:
Errors:
97 44
11
32
44
39
01
00
00
01
01
01
00
00
00
00
00
00
00
40
00
CO
CO
80
00
OC
OF
22
01
32
00
FF
00
00
00
00
00
00
00
00
80
00
80
40
00
FO
00
E2
00
01
00
00
20
00
00
00
00
00
00
00
00
40
00
00
40
Arithmetic overflow
128 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
MDORG
(Modeling Origin)
Purpose:
Define the modeling origin.
Command:
MDORG ox oy oz
Description:
MDORG defines the origin for
modeling-transformation scaling and rotating
specified by oX,oy,oz.
Short Form:
MDO ox oy oz
Hex Format:
91 lowox highox lowfracox highfracox
lowoy highoy lowfracoy highfracoy
lowoz highoz lowfracoz highfracoz
Example:
ASCII: MOO 1.7 0.2 1.5
HEX:
Errors:
91 01 00 33 B3 00 00 33 33 01 00 00 80
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 129
MDROTX
(Modeling Rotate X Axis)
Purpose:
Rotate about the X axis.
Command:
MDROTX deg
Description:
MDROTX defines the rotation about the x axis
component of the modeling matrix.
Short Form:
MDX deg
Hex Format:
93 lowdeg highdeg
Examples:
ASCII: MOX 30
HEX:
Errors:
93 20 00
Arithmetic overflow
130 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
MDROTY
(Modeling Rotate Y Axis)
Purpose:
Rotate about the Y axis.
Command:
MDROTY deg
Description:
MDROTY defines the rotation about the y axis
component of the modeling matrix.
Short Form:
MDY deg
Hex Format:
94 lowdeg highdeg
Example:
ASCII: MDY 15
HEX:
Errors:
94 OF 00
Arithmetic overflow
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 131
MDROTZ
(Modeling Rotate Z Axis)
Purpose:
Rotate about the Z axis.
Command:
MDROTZ deg
Description:
MDROTZ defines the rotation about the z axis
component of the modeling matrix.
Short Form:
MDZ deg
Hex Format:
95 lowdeg highdeg
Example:
ASCII: MOZ 33
HEX:
Errors:
95 21 00
Arithmetic overflow
132 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
MDSCAL
(Modeling Scale)
Purpose:
Set modeling scaling.
Command:
MDSCAL sx sy sf
Description:
MDSCAL defines the scaling components for the
image transformation.
Short Form:
MDS sx sy sz
Hex Format
92 lowsx highsx lowfracsx highfracsx
lowsy highsy lowfracsy highfracsy
lowsz highsz lowfracsz highfracsz
Example:
ASCII: MDS 2 2 2
HEX:
Errors:
92 02 00 00 80 01 00 00 00 01 00 00 80
Arithmetic overflow
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 133
MDTRAN
(Modeling Translation)
Purpose:
Define the modeling translation.
Command:
MDTRAN tx ty tz
Description:
MDTRAN defines the translation components for
the image transformation specified by tx,ty,tz.
Short Form:
MDT tx ty tz
Hex Format:
96 lowtx hightx lowfractx highfractx
lowty highty lowfracty highfracty
lowtz hightz lowfractz highfractz
Example:
ASCII: MDT 50 0 0
HEX:
Errors:
96 32 00 00 00 00 00 00 00 00 00 00 00
Arithmetic overflow
134 Professional Graphics ControUer
August 15, 1984
© Copyright IBM Corporation 1984
MOVE
(Move)
Purpose:
Absolute move in two dimensions.
Command:
MOVE x y
Description:
MOVE moves the two-dimensional current point
to the x and y coordinates given.
Short Form:
M xy
Hex Format:
10
lowx highx lowfracx highfracx
lowy highy lowfracy highfracy
Example:
ASCII: M 300 -400
HEX:
Errors:
10 2C 01 00 00 70 FE 00 00
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 135
MOVER
(Move Relative)
Purpose:
Relative move in two dimensions.
Command:
MOVER dx dy
Description:
MOVER moves the two-dimensional current point
a relative amount specified by dx,dy.
Short Form:
MR dx dy
Hex Format:
11
lowdx highdx lowfracdx highfracdx
lowdy highdy lowfracdy highfracdy
Example:
ASCII: MR 20.44 59
HEX:
Errors:
11 14 00 A2 71 3B 00 00 00
Arithmetic overflow
136 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
MOVE3
(Move in 3D)
Purpose:
Absolute move in three dimensions.
Command:
MOVE3 x y z
Description:
MOVE3 moves the three-dimensional current
point to the coordinates specified by x,y,z.
Short Form:
M3 x y z
Hex Format:
12
lowx highx lowfracx highfracx
lowy highy lowfracy highfracy
lowz highz lowfracz highfracz
Example:
ASCII: M3 -1300 -233 519
HEX: 12 EC FA 00 00 17 FF 00 00 07 02 00 00
Errors:
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 137
MOVER3
(Move Relative in 3D)
Purpose:
Relative move in three dimensions.
Command:
MOVER3 dx dy dz
Description:
MOVER3 moves the three-dimensional current
point a relative amount specified by dx,dy,dz.
Short Form:
MR3 dx dy dz
Hex Format:
13
lowdx highdx lowfracdx highfracdx
lowdy highdy lowfracdy highfracdy
lowdz highdz lowfracdz highfracdz
Example:
ASCII: MR3 722 0 0
HEX: 13 D2 02 00 00 00 00 00 00 00 00 00 00
Errors:
Arithmetic overflow
138 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
POINT
(Point)
Purpose:
Set the PEL to the current color in two
dimensions.
Command:
POINT
Description:
POINT writes the current color to the PEL at the
two-dimensional current point.
Short Form:
PT
Hex Format:
08
Example:
ASCII: PT
HEX:
Errors:
08
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics ControUer 139
POINT3
(Point in 3D)
Purpose:
Set the PEL to the current color in three
dimensions.
Command:
POINT3
Description:
POINT3 writes the current color to the PEL at the
current three-dimensional point.
Short Form:
PT3
Hex Format:
09
Example:
ASCII: PT3
HEX:
Errors:
09
None
140 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
POLY
(Polygon)
Purpose:
Draw a polygon.
Command:
POLY npts xl yl x2 y2 ..... xn yn
Description:
POLY draws an absolute polygon in two
dimensions, where npts is the number of points,
and x and yare the coordinates of the points. The
polygon is filled if the PRMFIL flag is set. The
current point is not changed.
Short Form:
P npts xl yl x2 y2 ..... xn yn
Hex Format:
30 npts lowxl
lowyl
lowx2
lowy2
highxl
highyl
highx2
highy2
lowfracxl
lowfracyl
lowfracx2
lowfracy2
highfracxl
highfracyl
highfracx2
highfracy2
lowxN highxN lowfracxN highfracxN
lowyN highyN lowfracyN highfracyN
Example:
ASCII: P 300
HEX:
Errors:
10 10
-10 30
30 03 00 00 00 00 00 00 00 00
OA 00 00 00 F6 FF 00 00
F6 FF 00 00 E2 FF 00 00
Not enough memory; arithmetic overflow
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 141
POLYR
(Polygon Relative)
Purpose:
Draw a relative polygon.
Command:
POLYR npts dxl dyl dx2 dy2 ..... dxn dyn
Description:
POLYR draws a relative polygon in two
dimensions, where npts is the number of points,
and dx and dy are the offsets from the current
point. The polygon is filled if the PRMFIL flag is
set. The current point is not changed.
Short Form:
PR npts dxl dyl dx2 dy2 ..... dxn dyn
Hex Format:
31 npts lowdxl
lowdyl
lowdx2
lowdy2
highdxl
highdyl
highdx2
highdy2
lowfracdxl
lowfracdyl
lowfracdx2
lowfracdy2
highfracdxl
highfracdyl
highfracdx2
highfracdy2
lowdxN highdxN lowfracdxN highfracdxN
lowdyN highdyN lowfracdyN highfracdyN
Example:
ASCII: PR 3 0 0 20 20 -20 40
HEX:
Errors:
31 03 00 00 00 00 00 00 00 00
OA 00 00 00 OA 00 00 00
F6 FF 00 00 E2 FF 00 00
Not enough memory; arithmetic overflow
142 Professional Graphics Controller
August 15,1984
© Copyright IBM Corporation 1984
POLY3
(Polygon in 3D)
Purpose:
Draw a polygon in three dimensions.
Command:
POLY3 npts xl yl zl ..... xn yn zn
Description: POLY3 draws an absolute polygon in three
dimensions, where npts is the number of points,
and x, y, and z are the coordinates of the points.
The polygon is filled if the PRMFIL flag is set.
The current point does not change.
Short Form: P3 npts xl yl zl ..... xn yn zn
Hex Format: 32 npts lowxl
lowyl
lowzl
lowx2
lowy2
lowz2
highxl
highyl
highzl
highx2
highy2
highz2
lowfracxl
lowfracyl
lowfraczl
lowfracx2
lowfracy2
lowfracz2
highfracxl
highfracyl
highfraczl
highfracx2
highfracy2
highfracz2
lowxN highxN lowfracxN highfracxN
lowyN highyN lowfracyN highfracyN
lowzN highzN lowfraczN highfraczN
Example:
ASCII :
P3 3 0 0 0 10 10 10 -10 30 -10
HEX:
32 03 00 00 00 00 00 00 00 00 00 00 00 00
OA 00 00 00 OA 00 00 00 OA 00 00 00
F6 FF 00 00 E2 FF 00 00 F6 FF 00 00
Errors:
Not enough memory; arithmetic overflow
Professional Graphics Controller 143
POLYR3
(Polygon Relative in 3D)
Purpose:
Draw a relative polygon in three dimensions.
Command:
POLYR3 npts dxl dyl dzl ..... dxn dyn dzn
Description:
POLYR3 draws a relative polygon in three
dimensions, where npts is the number of points,
and dx, dy, and dz are the offsets from the current
point. The polygon is filled if the PRMFIL flag is
set. The current point is not affected.
Short Form:
PR3 npts dxl dyl dzl ..... dxn dyn dzn
Hex Format:
33 npts lowdxl
lowdyl
lowdzl
lowdx2
lowdy2
lowdz2
highdxl
highdyl
highdz1
highdx2
highdy2
highdz2
lowfracdxl
lowfracdyl
lowfracdz1
lowfracdx2
lowfracdy2
lowfracdz2
highfracdxl
highfracdyl
highfracdzl
highfracdx2
highfracdy2
highfracdz2
lowdxN highdxN lowfracdxN highfracdxN
lowdyN highdyN lowfracdyN highfracdyN
lowdzN highdzN lowfracdzN highfracdzN
Example:
ASCII:
PR3 3 0 0 0 10 10 10 -10 30 -10
HEX:
33 03 00 00 00 00 00 00 00 00 00 00 00 00
OA 00 00 00 OA 00 00 00 OA 00 00 00
F6 FF 00 00 E2 FF 00 00 F6 FF 00 00
Errors:
Not enough memory; arithmetic overflow
144 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
PRMFIL
(Primitive Fill)
Purpose:
Set primitive fill flag.
Command:
PRMFIL flag
Description:
PRMFIL sets the primitive fill flag to the value
specified by flag. If flag is 0, closed figures are
drawn in outline only. If flag is 1, closed figures
are drawn filled with the current color. If flag is 2,
there is a performance improvement but
degenerate polygons will fill unpredictably.
PRMFIL affects the following commands:
CIRCLE, ELIPSE, POLY, POLYR, POLY3,
POLYR3, RECT, RECTR, SECTOR
Short Form:
PF flag
Hex Format:
E9 flag
Example:
ASCII: PF 1
HEX:
Errors:
E9 01
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 145
PROJCT
(Projection)
Purpose:
Set the type of projection.
Command:
PROJCT angle
Description:
PROJCT defines the type of projection used in the
three-dimensional to two-dimensional
transformation. If angle is 0, the projection is
orthographic parallel (non-oblique). Otherwise,
the projection is perspective, with angle being the
view angle (default is 60). The range of angle is 0
to 179 degrees.
Short Form:
PRO angle
Hex Format:
BO angle
Example:
ASCII: PR 0
HEX:
Errors:
BO 3C
Value out of range; arithmetic overflow
146 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
RECT
(Rectangle)
Purpose:
Draw an absolute rectangle in two dimensions.
Command:
RECT x y
Description:
RECT draws a rectangle with one corner at the
current point and its diagonally opposite corner at
the point given. The current point does not move.
If the PRMFIL flag is set, the rectangle is drawn
filled.
Short Form:
Rxy
Hex Format:
34
lowx highx lowfracx highfracx
lowy highy lowfracy highfracy
Example:
ASCII: R 70.50 90.75
HEX:
Errors:
34 46 00 00 80 5A 00 00 CO
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics ControUer 147
RECTR
(Rectangle Relative)
Purpose:
Draw a relative rectangle in two dimensions.
Command:
RECTR dx dy
Description:
RECTR draws a rectangle. One corner is at the
current point, and its diagonally opposite corner is
offset by dx,dy. The current point does not move.
If the PRMFIL flag is set, the rectangle is drawn
filled.
Short Form:
RR dx dy
Hex Format:
35
lowdx highdx lowfracdx highfracdx
lowdy highdy lowfracdy highfracdy
Example:
ASCII: RR -12.5 60
HEX:
Errors:
35 F3 FF 00 80 3C 00 00 00
Arithmetic overflow
148 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
RESETF
(Reset Flags)
Purpose:
Reset program parameters.
Command:
RESETF
Description:
Reset all settable flags to their default values.
Flag
Name
Default Value
1
2
AREAPT
65535 16 times
Flag = 0
Solid area
Flag = 0
Disabled
3
CLiPH
CLiPY
4
5
COLOR
DISPLA
6
7
DISTAN
Distance = 500
DISTH
DISTY
Distance = -30000
Disabled
Value = 255
No change after a RESETF
8
9
FILMSK
Distance = 30000
Mask = 255
10
LlNFUN
Function = 0
11
LIN PAT
Pattern = 65535
12
MASK
Mask = 255
13
MDORG
14
15
2D current point
3D current point
OX= OY = OZ =0
X=Y=O
X=Y=Z=O
16
17
PRMFIL
PROJCT
18
TANGLE
AnQle = 60
Angle = 0
19
TJUST
H=V=1
20
TSIZE
Size = 8
21
22
VWPORT
0,639,0,479
X=Y=Z=O
23
24
WINDOW
Transformed 3D
current point
VWRPT
August 15, 1984
© Copyright IBM Corporation 1984
FlaQ = 0
No PEL draw
effect
Replacement
mode
Solid line
All planes
enabled
Primitive fill off
Horizontal,
left- riQht text
Left, bottom
justification
12 by 8 cell
characters
Entire screen
-320,319, -240, 239
X=Y=Z=O
Professional Graphics Controller 149
Short Form:
RF
Hex Format:
04
Example:
Errors:
ASCII :
RF
HEX:
04
None
150 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
SECTOR
(Sector)
Purpose:
Draw a sector in two dimensions.
Command:
SECTOR radius de gO deg1
Description:
SECTOR draws a pie-shaped sector that consists
of an arc with a given radius, with the arc spanning
two given angles, and a vector from the center of
the arc to each of the arc's endpoints. If the
PRMFIL flag is set, the sector is drawn filled.
radius is a real number. Angles are integers and
treated modulo-360. If radius is negative, 180
degrees are added to each angle.
Short Form:
S radius de gO deg1
Hex Format:
3D
lowradius
lowfracradius
lowdegO
lowdeg1
highradius
highfracradius
highdegO
highdeg1
Example:
ASCII: S 50 -90 30
HEX:
Errors:
3D 32 00 00 00 A6 FF IE 00
Arithmetic overflow
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 151
TANGLE
(Text Angle)
Purpose:
Set text angle.
Command:
TANGLE deg
Description:
TANGLE specifies the angle for drawing text. An
angle of 0 (default) causes the text to be drawn
normally from left to right.
Short Form:
TA deg
Hex Format:
82 lowdeg highdeg
Example:
ASCII: TA 90
HEX:
Errors:
82 5A 00
None
152 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
TDEFIN
(Text Define)
Purpose:
Define programmable text character.
Command:
TDEFIN N x y array
Description:
TDEFIN stores the character image given by x, y,
and array for a character with the ASCII value of
N. If communication is in ASCII, the character
image is to be sent as a series of O's and 1'so If
communication is in hexadecimal, the character is
sent as a series of bytes, as many for each line as
required, for as many lines as specified.
Short Form:
TD N x y array
Hex Format:
84 N x y linelbytel
line2bytel
linelbyte2
line2byte2
linelbyteX
line2byteX
line Ybyte 1 line Ybyte2 . .. line YbyteX
Example:
ASCII: T 65 70 12 14
HEX:
Errors:
84 62 05 07 IE 11 11 IE 10 10 10
Not enough memory
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 153
TEXT
(Text)
Purpose:
Draw hardware font text.
Command:
TEXT 'string'
TEXT "string"
Description:
TEXT writes a text string to the screen, justified
about the current point as specified by the last
TJUST command. The string may be delimited by
either single or double quotes.
Short Form:
T 'string'
T "string"
Hex Format:
80 22 c1 c2 c3
cN22
or
80 27 cl c2 c3
..... cN27
Example:
ASCII: T 'This is a test'
HEX:
Errors:
80 27 58 20 65 71 75 61
6C 73 20 31 2E 34 27
N at enough memory
154 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
TEXTP
(Text Programmed)
Purpose:
Draw text using a programmed font.
Command:
TEXTP 'string'
TEXTP "string"
Description:
TEXTP draws text with the user-programmed
font. The size is that specified by the latest TSIZE
command, and the angle is that specified by
TANGLE. The text is justified about the current
point.
Short Form:
TP 'string'
TP "string"
Hex Format:
83 22 cl c2 c3
cN22
or
83 27 c1 c2 c3
..... cN27
Example:
ASC II: TP
HEX:
Errors:
I
He 11 0
I
83 27 48 65 6C 6F 27
Not enough memory
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 155
TJUST
(Text Justify)
Purpose:
Set text justification
Command:
TJUST horiz vert
Description:
The TJUST command specifies the text
justification, where horiz is one of the following:
1 Left justify text at current point.
2 Center the text string about the current
point.
3 Right justify text at current point.
vert is one of the following:
1 Bottom of text at Y coordinate of current
point.
2 Center text string vertically about the
current point.
3 Top of text at Y coordinate of current
point.
The default is H = 1, V = 1.
Short Form:
TJ horiz vert
Hex Format:
85
Example:
ASCII: TJ 2 1
HEX:
Errors:
85 02 01
Value out of range
156 Professional Graphics ControUer
August 15, 1984
© Copyright IBM Corporation 1984
TSIZE
(Text Size)
Purpose:
Set the text size.
Command:
TSIZE size
Description:
TSIZE sets text size by specifying the virtual x
distance from one character to the next when
displayed.
Short Form:
TS size
Hex Format:
81 lowsize
lowfracsize
highsize
highfracsize
Example:
ASCII: TS 10
HEX:
Errors:
81 OA 00 00 00
Arithmetic overflow
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 157
VWIDEN
(Viewing Identity)
Purpose:
Reset the viewing matrix.
Command:
VWIDEN
Description:
VWIDEN sets the viewing transformation matrix
to the identity matrix.
Short Form:
VWI
Hex Format: AO
Example:
ASCII: VWI
HEX:
Errors:
AD
None
158 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
VWMATX
(Viewing Matrix)
Purpose:
Define the viewing matrix.
Command:
VWMATX array
Description:
VWMATX loads the viewing matrix directly from
the 4-by-4 array.
Short Form:
VWM array
Hex Format:
A7lowmll
lowm12
lowm13
lowm14
lowm21
lowm22
lowm23
lowm24
lowm31
lowm32
lowm33
lowm34
lowm41
lowm42
lowm43
lowm44
highmll
highm12
highm13
highm14
highm21
highm22
highm23
highm24
highm31
highm32
highm33
highm34
highm41
highm42
highm43
highm44
lowfracmll
lowfracm12
lowfracm13
lowfracm14
lowfracm21
lowfracm22
lowfracm23
lowfracm24
lowfracm31
lowfracm32
lowfracm33
lowfracm34
lowfracm41
lowfracm42
lowfracm43
lowfracm44
highfracmll
highfracm12
highfracm13
highfracm14
highfracm21
highfracm22
highfracm23
highfracm24
highfracm31
highfracm32
highfracm33
highfracm34
highfracm41
highfracm42
highfracm43
highfracm44
Example:
Errors:
ASCII: VWM 68
65503.5
8418
313.75
12.5
0
2628.25
50.25
HEX:
00
00
00
20
CO
00
80
A7 44
00
00
00
01
00
01
00
00
00
00
00
CO
00
00
11
00
E2
00
32
00
OC
00
32
00
00
00
00
40
01
00
00
40
253
306.25
1.75
1
00
OF
00
44
00
01
80
FF
40
OA
80
00
17.25
34
0.5
1.5
FO
00
22
00
39
00
00
80
00
40
01
00
Arithmetic overflow
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 159
VWPORT
(Viewport)
Purpose:
Define a viewport.
Command:
VWPORT xl x2 yl y2
Description:
VWPORT defines a viewport within the viewplane
and is measured in PELs from the lower-left
corner of the screen. Clipping is always enabled.
The default is the entire screen (0,639 and 0,479).
xl must be less than x2; otherwise, a warning is
generated and the coordinates are swapped. The
same is true for yl andy2. A warning is generated
if any of the coordinates fall outside the screen
boundary.
Short Form:
VWP xl x2 yl y2
Hex Format:
B2
lowxl highxl lowx2 highx2
lowyl highyl lowy2 highy2
Example:
ASCII: VWP 50 450 30 250
HEX:
Errors:
B2 32 00 C4 01 IE 00 FA 00
Arithmetic overflow
160 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
VWROTX
(Viewing Rotate X Axis)
Purpose:
Rotate viewing about the x axis.
Command:
VWROTX deg
Description:
VWROTX defines the rotation about the x axis
component of the viewing matrix.
Short Form:
VWX deg
Hex Format:
A3 lowdeg highdeg
Example:
ASCII: VWX 30
HEX:
Errors:
A3 2D 00
Arithmetic overflow
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 161
VWROTY
(Viewing Rotate Y Axis)
Purpose:
Rotate viewing about the y axis.
Command:
VWROTY deg
Description:
VWROTY defines the rotation about the y axis
component of the viewing matrix.
Short Form:
VWY deg
Hex Format:
A4 lowdeg highdeg
Example:
ASCII: VWY 45
HEX:
Errors:
A4 lE 00
Arithmetic overflow
162 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
VWROTZ
(Viewing Rotate Z Axis)
Purpose:
Rotate viewing about the z axis.
Command:
VWROTZ deg
Description:
VWROTZ defines the rotation about the z axis
component of the viewing matrix.
Short Form:
VWZ deg
Hex Format:
A5 lowdeg highdeg
Example:
ASCII: VWZ 30
HEX:
Errors:
AS 44 00
Arithmetic overflow
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 163
VWRPT
(Viewing Reference Point)
Purpose:
Define the viewing reference point.
Command:
VWRPT x y z
Description:
VWRPT defines the viewing reference point (the
point the user is looking at); specified by x,y,z.
Short Form:
VWR x y z
Hex Format:
Allowx highx lowfracx highfracx
lowy highy lowfracy highfracy
lowz highz lowfracz highfracz
Example:
ASCII: VWR 50 75 -25
HEX:
Errors:
Al 32 00 00 00 4B 00 00 00 E7 FF 00 00
Arithmetic overflow
164 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
WAIT
(Wait)
Purpose:
Insert a delay in execution.
Command:
WAIT frames
Description:
WAIT inserts a delay in the execution of
commands by waiting the number of frames
specified by frames. A frame is 1/60 second.
With the maximum of 65535 frames, a delay of up
to 20 minutes may be inserted.
Short form:
W frames
Hex Format:
05 lowframes highframes
Example:
ASCII: W 60
HEX:
Errors:
05 3C 00
None
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 165
WINDOW
(Window)
Purpose:
Define the viewport coordinates.
Command:
WINDOW xl x2 y1 y2
Description:
WINDOW defines the corner coordinates of the
viewport. These two-dimensional real coordinates
will map to the screen's PEL locations specified by
the most recent VWPORT command.
Short Form:
WI xl x2 y1 y2
Hex Format:
B3
lowxleft
lowfracxleft
lowxright
lowfracxright
lowybottom
lowfracybottom
lowytop
lowfracytop
highxleft
highfracxleft
highxright
highfracxright
highybottom
highfracybottom
highytop
highfracytop
Example:
ASCII: WI -100 100 100 100
HEX:
Errors:
B3 96 FF 00 00 64 00 00 00
64 00 00 00 64 00 00 00
Arithmetic overflow
t 66 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
Run-Length Encoding
In hexadecimal mode, the commands IMAGER and IMAGEW
send and receive data in run-length encoded format. This format
allows for extremely high data rates. The format is described as
follows:
Command (1 byte) IMAGER or IMAGEW
Line # (1 word)
Start x
End x
One or more PEL packets
A PEL packet is either of the following:
•
A solid block of one color:
Count (1 byte: N - 1)
Color (1 byte)
The count may range from 0 to 127 (N = 1 to 128),
with the most-significant bit set to O. This packet
defines multiple occurrences of the same color and
requires only two bytes to specify up to 128 PELs.
•
PELs of different colors:
Count (1 byte: N - 1 + 128)
PEL 0
PEL 1
PEL 2
PEL N - 1 (N bytes)
The count may range from 128 to 255 (N = 1 to 128),
with the most-significant bit set to 1. This packet
defines strings of color codes that are different from one
another.
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 167
Default LUT Selections for LUTINT
Each state provides a distinct way for initializing the look-up
table (LUT). Following are descriptions for each currently
defined state. The descriptions include a list of the default values
for that LUT.
State 0
State 0 reproduces a color-cone distribution. The 8-bit LUT
value divides into two 4-bit hexadecimal digits. The
least-significant digit supplies the luminance value, and the
most-significant digit supplies the color scale, each of the 16
values corresponding to a color. The color scale shades from
black through the given color to white.
168 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
The following table shows the default values of state 0 for the
various colors.
Color
Black to Grey to White
Black to Red to White
Black to Red-magenta to White
Black to Magenta to White
Black to Magenta-blue to White
Black to Blue to White
Black to Blue-cyan to White
Black to Cyan to White
Black to Cyan-green to White
Black to Green to White
Black to Green-yellow to White
Black to Yellow to White
Black to Yellow-red to White
Black to Unsaturated Red to White
Black to Unsaturated Green to White
Black to Unsaturated Blue to White
August 15, 1984
© Copyright IBM Corporation 1984
Default Values (in Hex) for State
000 111
222 333 444
888 999 AAA BBB CCC
000 200 400 600 800
FDa F22 F44 F66 F88
000 201 402 603 904
F08 F29 F4A F6B F8C
000 202 404 606 808
FOF F2F F4F F6F F8F
000 102 204 306 408
80F 92F A4F B6F C8F
000 002 004 006 008
OOF 22F 44F 66F 88F
000 012 042 036 048
08F 29F 4AF 6BF 8CF
000 022 044 066 088
OFF 2FF 4FF 6FF 8FF
000 021 042 063 084
OF8 2F9 4FA 6FB 8FC
000 020 040 060 080
OFO 2F2 4F4 6F6 8F8
000 120 240 360 480
8FO 9F2 AF4 BF6 CF8
000 220 440 660 880
FFO FF2 FF4 FF6 FF8
000 210 420 630 840
F80 F92 FA4 FB6 FC8
000 211 422 633 844
F88 F99 FAA FBB FCC
000 121
242 363 484
8F8 9F9 AFA BFB CFC
000 112 224 336 448
88F 99F AAF BBF CCF
0
555
DOD
ADO
FAA
A05
FAD
ADA
FAF
50A
OAF
OOA
AAF
05A
ADF
OAA
AFF
OA5
AFD
DAD
AFA
5AO
DFA
AAO
FFA
A50
FDA
A55
FDD
5A5
DFD
55A
DDF
666
EEE
COO
FCC
C06
FCE
CDC
FCF
60C
ECF
DOC
CCF
06C
CEF
OCC
CFF
OC6
DFE
OCO
CFC
6CO
EFC
CCO
FFC
C60
FEC
C66
FEE
6C6
EFE
66C
EEF
777
FFF
EOO
FEE
E07
FEF
EOE
FEF
70E
FEF
DOE
EEF
07E
EFF
DEE
EFF
OE7
EFF
OED
EFE
7EO
EFF
EEO
FFE
E70
FFE
E77
FFF
7E7
FFF
77E
FFF
Professional Graphics Controller 169
State 1
State 1 divides the 8-bit LUT value into two 4-bit hexadecimal
digits. The least-significant digit provides the background color,
and the most-significant digit defines the foreground color. The
high-function graphics mode interprets a value of 0000 for the
most-significant digit as a transparent foreground, allowing the
background color to be displayed. Otherwise, the high-function
graphics mode ignores the background color.
The following table lists the colors represented by each 4-bit
value for State 1.
Value
a
1
2
3
4
5
6
Color
Sky Blue (backaround only)
RGB
Black
Dark Brown
000
742
A74
700
Faa
F70
FFO
AFO
OFO
070
077
007
Liqht Brown
Dark Red
Liqht Red
7
Oranae
Yellow
8
9
Yellow-Green
Liaht Green
A
Dark Green
Green-Blue
B
C
D
E
Dark Blue
Liaht Burnt-Sienna
Grey
F
White
170 Professional Graphics Controller
68D
E96
777
FFF
August 15, 1984
© Copyright IBM Corporation 1984
States 2 through 4
For states 2 through 4, red, green, and blue LUT values employ
either two or three bits of information. For each state, one color
receives two bits while the other two colors each receive three.
Each bit value then translates to an RGB intensity of that color.
The following tables give the corresponding intensity values for
each bit value.
2-Bit Intensity Values
Decimal
Value
Bit
Value
Intensity
Level
0
1
2
3
o0
o1
0
5
10
15
Decimal
Value
1 0
1 1
3-Bit Intensity Values
Intensity
Bit
Value
Level
0
1
2
3
4
5
6
7
jlO 0
001
010
o1 1
100
1 o 1
1 1 0
1 1 1
0
3
5
7
9
11
13
15
State 2 uses two bits for red (R), three bits for green (G), and
three bits for blue (B). Thus, R R G G G B B B means:
I R R IG
I
I
'
G G B B B
~
L..-_ _ _ _ _ _
~
L..-_ _ _ _ _ _ _~
August 15, 1984
© Copyright IBM Corporation 1984
8-Bit code
Three bits for blue Intensity value
Three bits for green intensity value
Two bits for red intensity value
Professional Graphics ControUer 171
Similarly, state 3 uses two bits for green and three bits each for
red and blue (R R R G G B B B). State 4 allows two bits for blue
and three bits each for red and green (R R R G G G B B).
172 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
The following table shows the default values for state 2.
Default Values (in Hex) for State 2
000
030
050
070
090
OBO
000
OFO
050
530
550
570
590
5BO
500
5FO
AOO
A30
A50
A70
A90
ABO
ADO
AFO
FOO
F30
F50
F70
F90
FBO
FOO
FFO
003
033
053
073
093
OB3
003
OF3
503
533
553
573
593
5B3
503
5F3
A03
A33
A53
A73
A93
AB3
A03
AF3
F03
F33
F53
F73
F93
FB3
F03
FF3
August 15, 1984
005
035
055
075
095
OB5
005
OF5
505
535
555
575
595
5B5
505
5F5
A05
A35
A55
A75
A95
AB5
A05
AF5
F05
F35
F55
F75
F95
FB5
F05
FF5
007
037
057
077
097
OB7
007
OF7
507
537
557
577
597
5B7
507
5F7
A07
A37
A57
A77
A97
AB7
A07
AF7
F07
F37
F57
F77
F97
FB7
F07
FF7
© Copyright IBM Corporation 1984
009
039
059
079
099
OB9
009
OF9
509
539
559
579
599
5B9
509
5F9
A09
A39
A59
A79
A99
AB9
A09
AF9
F09
F39
F59
F79
F99
FB9
F09
FF9
OOB
03B
05B
07B
09B
OBB
OOB
OFB
50B
53B
55B
57B
59B
5BB
50B
5FB
AOB
A3B
A5B
A7B
A9B
ABB
AOB
AFB
FOB
F3B
F5B
F7B
F9B
FBB
FOB
FFB
000
030
050
070
090
OBO
000
OFO
500
530
550
570
590
5BO
500
5FO
AOO
A30
A50
A70
A90
ABO
ADD
AFO
FOO
F30
F50
F70
F90
FBO
FOO
FFO
OOF
03F
05F
07E
09F
OBF
OOF
OFF
50F
53F
55F
57F
59F
5BF
50F
5FF
AOF
A3F
A5F
A7F
A9F
ABF
AOF
AFF
FOF
F3F
F5F
F7F
F9F
FBF
FOF
FFF
Professional Graphics Controller 173
The following table shows the default values for state 3.
Default Values (in Hex) for State 3
000
050
OAO
OFO
300
350
3AO
3FO
500
550
5AO
5FO
700
750
7AO
7FO
900
950
9AO
9FO
BOO
B50
BAO
BFO
DOO
D50
DAO
DFO
FOO
F50
FAO
FFO
003
053
OA3
OF3
303
353
3A3
3F3
503
553
5A3
5F3
703
753
7A3
7F3
903
953
9A3
9F3
B03
B53
BA3
BF3
D03
D53
DA3
DF3
F03
F53
FA3
FF3
005
055
OA5
OF5
305
355
3A5
3F5
505
555
5A5
5F5
705
755
7A5
7F5
905
955
9A5
9F5
B05
B55
BA5
BF5
D05
D55
DA5
DF5
F05
F55
FA5
FF5
007
057
OA7
OF7
307
357
3A7
3F7
507
557
5A7
5F7
707
757
7A7
7F7
907
957
9A7
9F7
B07
B57
BA7
BF7
D07
D57
DA7
DF7
F07
F57
FA7
FF7
009
059
OA9
OF9
309
359
3A9
3F9
509
559
5A9
5F9
709
759
7A9
7F9
909
959
9A9
9F9
B09
B59
BA9
BF9
D09
D59
DA9
DF9
F09
F59
FA9
FF9
174 Professional Graphics Controller
OOB
05B
OAB
OFB
30B
35B
3AB
3FB
50B
55B
5AB
5FB
70B
75B
7AB
7FB
90B
95B
9AB
9FB
BOB
B5B
BAB
BFB
DOB
D5B
DAB
DFB
FOB
F5B
FAB
FFB
OOD
05D
OAD
OFD
30D
35D
3AD
3FD
50D
55D
5AD
5FD
70D
75D
7AD
7FD
90D
95D
9AD
9FD
BOD
B5D
BAD
BFD
DOD
D5D
DAD
DFD
FOD
F5D
FAD
FFD
OOF
05F
OAF
OFF
30F
35F
3AF
3FF
50F
55F
5AF
5FF
70F
75F
7AF
7FF
90F
95F
9AF
9FF
BOF
B5F
BAF
BFF
DOF
D5F
DAF
DFF
FOF
F5F
FAF
FFF
August 15,1984
© Copyright IBM Corporation 1984
The following table shows the default values for state 4.
Default Values (in Hex) for State 4
000
050
090
000
300
350
390
300
500
550
590
500
700
750
790
700
900
950
990
900
BOO
B50
B90
BOO
000
050
090
000
FOO
F50
F90
FOO
005
055
095
005
305
355
395
305
505
555
595
505
705
755
795
705
905
955
995
905
B05
B55
B95
B05
005
055
095
005
F05
F55
F05
F05
OOA
05A
09A
OOA
30A
35A
39A
30A
50A
55A
59A
50A
70A
75A
79A
70A
90A
95A
99A
90A
BOA
B5A
B9A
BOA
OOA
05A
09A
OOA
FOA
F5A
F9A
FDA
August 15,1984
© Copyright IBM Corporation 1984
OOF
05F
09F
OOF
30F
35F
39F
30F
50F
55F
59F
50F
70F
75F
79F
70F
90F
95F
99F
90F
BOF
B5F
B9F
BOF
OOF
05F
09F
OOF
FOF
F5F
F9F
FDF
030
070
OBO
OFO
330
370
3BO
3FO
530
570
5BO
5FO
730
770
7BO
7FO
930
970
9BO
9FO
B30
B70
BBO
BFO
030
070
OBO
OFO
F30
F70
FBO
FFO
035
075
OB5
OF5
335
375
3B5
3F5
535
575
5B5
5F5
735
775
7B5
7F5
935
975
9B5
9F5
B35
B75
BB5
BF5
035
075
OB5
OF5
F35
F75
FB5
FF5
03A
07A
OBA
OFA
33A
37A
3BA
3FA
53A
57A
5BA
5FA
73A
77A
7BA
7FA
93A
97A
9BA
9FA
B3A
B7A
BBA
BFA
03A
07A
OBA
OFA
F3A
F7A
FBA
FFA
03F
07F
OBF
OFF
33F
37F
3BF
3FF
53F
57F
5BF
5FF
73F
77F
7BF
7FF
93F
97F
9BF
9FF
B3F
B7F
BBF
BFF
03F
07F
OBF
OFF
F3F
F7F
FBF
FFF
Professional Graphics Controller 175
State 5
In state 5, the 8-bit value becomes the arithmetic result of the
formula (R x 36) + (G x 6) + B, where R, G, and B represent
coded values of intensity levels ranging from 0 to 5. The
following table defines which coded values correspond to which
intensity levels.
Coded
RGB
Values
Actual Intensity
Levels
0
0
3
6
9
1
2
3
4
12
5
15
176 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
The following table shows the default values for state 5:
Default Values (in Hex) for State 5
000
036
06C
OCO
OF6
30C
360
396
3CC
600
636
66C
6CO
6F6
90C
960
996
9CC
COO
C36
C6C
CCO
CF6
FOC
F60
f96
FCC
000
000
000
000
000
003
039
06F
OC3
OF9
30F
363
399
3Cf
603
639
66F
6C3
6F9
90F
999
999
9CF
C03
C39
C6F
CC3
CF9
FOF
F99
F99
FCF
000
000
000
000
000
006
03C
090
OC6
OFC
330
366
39C
3FO
606
63C
690
6C6
6FC
930
99C
99C
9FO
C06
C3C
C90
CC6
CFC
F30
F9C
F9C
FFO
000
000
000
000
000
August 15, 1984
© Copyright IBM Corporation 1984
009
03F
093
OC9
OFF
333
369
39F
3F3
609
63F
693
6C9
6FF
933
99F
99F
9F3
C09
C3F
C93
CC9
CFF
F33
F9F
F9F
FF3
000
000
000
000
000
DOC
060
096
OCC
300
336
36C
3CO
3F6
60C
660
696
6CC
900
936
9CO
9CO
9F6
CDc
C60
C96
CCC
FOO
F36
FCO
FCO
FF6
000
000
000
000
000
OOF
063
099
OcF
303
339
36F
3C3
3F9
60F
663
699
6CF
903
939
9C3
9C3
9F9
COF
C63
C99
CCF
F03
F39
Fc3
FC3
FF9
000
000
000
000
000
030
066
09C
OFO
306
33C
390
3C6
3FC
630
666
69C
6FO
906
93C
9C6
9C6
9FC
C30
C66
C9C
CFO
F06
F3C
FC6
FC6
FFC
000
000
000
000
000
033
069
09F
OF3
309
33F
393
3C9
3FF
633
669
69F
6F3
909
93F
9C9
9C9
9FF
C33
C69
C9F
CF3
F09
F3F
FC9
FC9
FFF
000
000
000
000
000
Professional Graphics Controller 177
State 255
State 255 restores the LUT values that were previously saved
with the command LUTSAV. These tables can include
user-defined values.
178 Professional Graphics Controller
August 15,1984
© Copyright IBM Corporation 1984
Interface
The following illustration shows the location of the connectors
and jumper on the Professional Graphics Controller.
Emulator
Enable/Disable
Connector
Enabled
Disabled
9-Pin D-Shell
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 179
Connector Specifications
The following table shows the pin numbers and their respective
signals.
S·19na IN arne /0 escnptlon
Red Video
Green Video
Professional
p.In
1
2
Blue Video
3
Horizontal and Vertical Sync
4
Professional
Graphics
Mode Control
5
Graphics
Display
Ground for Pin 1
6
7
Controller
Ground for Pin 2
Ground for Pin 3
Ground for Pins 4 and 5
180 Professional Graphics Controller
8
9
August 15, 1984
© Copyright IBM Corporation 1984
Specifications
The following is a description of the Professional Graphics
Controller specifications.
Size:
Length: 668 mm (4.2 in.)
Depth: 32 mm (1.26 in.)
Height: 210 mm (3.36 in.)
Weight: 90.72 kg (2Ib)
Power Requirements:
Voltage: 5 VDC (+/-5%)
Current: 5 A Maximum
Power Dissipation: 25 W Maximum
August 15, 1984
© Copyright IBM Corporation 1984
Professional Graphics Controller 181
Notes:
182 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
Logic Diagrams
This section shows the logic diagrams for:
•
Professional Graphics Controller's processor card
•
Professional Graphics Controller's emulator card
•
Professional Graphics Controller's memory card
August 15,1984
© Copyright IBM Corporation 1984
Professional Graphics ControUer 183
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12
11
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14
13
14
15
16
15
16
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6
+5
17
18
ERDL(5)
17
18
(5)EMOH
19
20
EWRL(3,5)
19
20
(5)EM1H
21
22
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21
22
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23
24
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23
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24
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DISPLlCPU(3)
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25
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26
CPUDAT4(3,5,6)
25
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27
CPUDAT1 (3,5,6)
28
CPUDAT5(3,5,6)
27
28
29
CPUDAT2(3,5,6)
30
CPUDAT6(3,5,6)
29
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31
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32
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31
30
32
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36
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38
CPUAD10(3)
37
39
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40
CPUAD11(3)
39
41
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42
CPUAD12(3)
41
43
CPUAD5(3)
44
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45
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88
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CPUDAT2(10)
CPUDAT3(10)
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CPUAD1(SI
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CPUAD6(NCJ
CPUAD7(NC)
CPUADS(NC)
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11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
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11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
AD2(10)
LPENINPUT
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AD4(1O)
AD5(10)
AD6(10)
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24
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Sheet 1 of 8
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a.A7ISHTU.4.51
SheetS of S
204 Professional Graphics Controller
August 15, 1984
© Copyright IBM Corporation 1984
Glossary
algorithm. A finite set of well-defined rules for the solution of a
problem in a finite number of steps.
alphanumeric (A/N). Pertaining to a character set that contains
letters, digits, and usually other characters, such as punctuation
marks.
American National Standard Code for Information Exchange
(ASCII). The standard code, using a coded character set
consisting of 7-bit coded characters (8 bits including parity
check) used for information exchange between data processing
systems, data communication systems, and associated equipment.
The ASCII set consists of control characters and graphic
characters.
A/N. Alphanumeric
ASCII. American National Standard Code for Information
Exchange.
Cartesian coordinates. A system of coordinates for locating a
point on a plane by its distance from each of two intersecting
lines, or in space by its distance from each of three mutually
perpendicular planes.
cathode ray tube (CRT). A vacuum tube in which a stream of
electrons is projected onto a fluorescent screen producing a
luminous spot. The location of the spot can be controlled.
cathode ray tube display (CRT display). (1) A CRT used for
displaying data. For example, the electron beam can be
controlled to form alphanumeric data by use of a dot matrix. (2)
Synonymous with monitor.
August 15,1984
© Copyright IBM Corporation 1984
Glossary-l
clipping. In computer graphics, removing parts of a display image
that lie outside a window.
color cone. An arrangement of the visible colors on the surface of
a double-ended cone where lightness varies along the axis of the
cone, and hue varies around the circumference. Lightness
includes both the intensity and saturation of color.
complement. A number that can be derived from a specified
number by subtracting it from a second specified number.
coordinate space. In computer graphics, a system of Cartesian
coordinates in which an object is defined.
cursor. (1) In computer graphics, a movable marker that is used
to indicate a position on a display. (2) A displayed symbol that
acts as a marker to help the user locate a point in text, in a system
command, or in storage. (3) A movable spot of light on the
screen of a display device, usually indicating where the next
character is to be entered, replaced, or deleted.
debounce. (1) An electronic means of overcoming the
make/break bounce of switches to obtain one smooth change of
signal level. (2) The elimination of undesired signal variations
caused by mechanically generated signals from contacts.
display. (1) A visual presentation of data. (2) A device for visual
presentation of information on any temporary character imaging
device. (3) To present data visually. (4) See cathode ray tube
display.
display attribute. In computer graphics, a particular property that
is assigned to all or part of a display; for example, low intensity,
green color, blinking status.
display element. In computer graphics, a basic graphic element
that can be used to construct a display image; for example, a dot,
a line segment, a character.
display group. In computer graphics, a collection of display
elements that can be manipulated as a unit and that can be further
combined to form larger groups.
Glossary-2
August 15, 1984
© Copyright IBM Corporation 1984
display image. In computer graphics, a collection of display
elements or display groups that are represented together at any
one time in a display space.
display space. In computer graphics, that portion of a display
surface available for a display image. The display space may be
all or part of a display surface.
display surface. In computer graphics, that medium on which
display images may appear; for example, the entire screen of a
cathode ray tube.
drawing primitive. A group of commands that draw defined
geometric shapes.
field-programmable-Iogic-sequencer (FPLS). An integrated circuit
containing a programmable, read-only memory that responds to
external inputs and feedback of its own outputs.
FIFO (first-in-first-out). A queuing technique in which the next
item to be retrieved is the item that has been in the queue for the
longest time.
FPLS. Field-programmable-Iogic-sequencer.
hither plane. In computer graphics, a plane that is perpendicular
to the line joining the viewing reference point and the view point
and which lies between these two points. Any part of an object
between the hither plane and the view point is not seen. See also
yon plane.
intensity. In computer graphics, the amount of light emitted at a
display point.
interleave. To arrange parts of one sequence of things or events
so that they alternate with parts of one or more other sequences
of the same nature and so that each sequence retains its identity.
August 15,1984
© Copyright IBM Corporation 1984
Glossary-3
least-significant digit. The rightmost digit.
look-up table (LUT). (1) A technique for mapping one set of
values into a larger set of values. (2) In computer graphics, a
table that assigns a color value (red, green, blue intensities) to a
color index.
luminance. The luminous intensity per unit projected area of a
given surface viewed from a given direction.
LUT. Look-up table.
mask. (1) A pattern of characters that is used to control the
retention or elimination of portions of another pattern of
characters. (2) To use a pattern of characters to control the
retention or elimination of portions of another pattern of
characters.
matrix. (1) A rectangular array of elements, arranged in rows and
columns, that may be manipulated according to the rules of matrix
algebra. (2) In computers, a logic network in the form of an array
of input leads and output leads with logic elements connected at
some of their intersections.
mode. (1) A method of operation; for example, the binary mode,
the interpretive mode, the alphanumeric mode. (2) The most
frequent value in the statistical sense.
modeling transformation. Operations on the coordinates of an
object (usually matrix multiplications) which cause the object to
be rotated about any axis, translated (moved without rotating),
and/ or scaled (changed in size along any or all dimensions). See
also viewing transformation.
modulo-N check. A check in which an operand is divided by a
number N (the modulus) to generate a remainder (check digit)
that is retained with the operand. For example, in a modulo-7
check, the remainder will be 0, 1,2,3,4,5, or 6. The operand is
later checked by again dividing it by the modulus; if the
remainder is not equal to the check digit, an error is indicated.
Glossary-4
August 15, 1984
© Copyright IBM Corporation 1984
modulus. In a modulo-N check, the number by which the operand
is divided.
monitor. Synonym for cathode ray tube display (CRT display).
most-significant digit. The leftmost (non-zero) digit.
nanosecond (ns). 0.000 000 001 second.
ns. Nanosecond; 0.000 000 001 second.
PEL. Picture element.
picture element (PEL). The smallest displayable unit on a display.
raster. A predetermined pattern of lines that provides uniform
coverage of a display space.
saturation. In computer graphics, the purity of a particular hue. A
color is said to be saturated when at least one primary color (red,
green, or blue) is completely absent.
scaling. In computer graphics, enlarging or reducing all or part of
a display image by multiplying the coordinates of the image by a
constant value.
vector. In computer graphics, a directed line segment.
view point. In computer graphics, the origin from which angles
and scales are used to map virtual space into display space.
viewing reference point. In computer graphics, a point in the
modeling coordinate space that is a defined distance from the
view point.
viewing transformation. Operations on the coordinates of an
object (usually matrix multiplications) which cause the view of
August 15, 1984
© Copyright IBM Corporation 1984
Glossary-5
the object to be rotated about any axis, translated (moved without
rotating), and/or scaled (changed in size along any or all
dimensions). Viewing transformations differ from modeling
transformations in that perspective is taken into account. See also
modeling transformation.
viewplane. In computer graphics, a two-dimensional coordinate
system onto which images are projected and which contains the
display space.
viewport. In computer graphics, a predefined part of the display
space.
virtual space. In computer graphics, a space in which the
coordinates of the display elements are expressed in terms of user
coordinates.
window. (1) In computer graphics, a predefined part of the virtual
space. (2) In computer graphics, the visible area of a viewplane
mapped into a viewport.
yon plane. In computer graphics, a plane that is perpendicular to
the line joining the viewing reference point and the view point and
which lies beyond the viewing reference point. Any part of an
object beyond the yon plane is not seen. See also hither plane.
Glossary-6
August 15, 1984
© Copyright IBM Corporation 1984
Index
A
absolute draw
DRAW (2D) 108
absolute move
MOVE (2D) 135
MOVE3 (3D) 137
alphanumeric mode 20,21,22,23
alphanumeric operation 29
ARC 86
AREA 87
area fill 87
area fill command description 68
area fill to boundary color 88
area pattern 89
area pattern mask 61
AREABC 88
ARE APT 89
ASCII commands
ARC 86
AREA 87
AREABC 88
AREAPT 89
CA 90
CIRCLE 91
CLBEG 92
CLDEL 93
CLEARS 94
CLEND 95
CLIPH 96
CLIPY 97
CLOOP 98
CLRD 99
CLRUN 100
COLOR 101
August 15, 1984
© Copyright IBM Corporation 1984
Index-l
CONVRT 102
CX 103
DISPLA 104
DISTAN 105
DISTH 106
DISTY 107
DRAW 108
DRAWR 109
DRAWR3 111
DRAW3 110
ELIPSE 112
FILMSK 113
FLAGRD 114
FLOOD 116
IMAGER 117
IMAGEW 118
LINFUN 119
LINPAT 120
list of commands 83, 84, 85
LUT 121
LUTINT 122
LUTRD 123
LUTSAV 124
MASK 125
MATXRD 126
MDIDEN 127
MDMATX 128
MDORG 129
MDROTX 130
MDROTY 131
MDROTZ 132
MDSCAL 133
MDTRAN 134
MOVE 135
MOVER 136
MOVER3 138
MOVE3 137
POINT 139
POINT3 140
POLY 141
POLYR 142
POLYR3 144
POLY3 143
Index-2
August 15, 1984
© Copyright IBM Corporation 1984
PRMFIL 145
PROJCT 146
RECT 147
RECTR 148
RESETF 149
SECTOR 151
TANGLE 152
TDEFIN 153
TEXT 154
TEXTP 155
TJUST 156
TSIZE 157
VWIDEN 158
VWMATX 159
VWPORT 160
VWROTX 161
VWROTY 162
VWROTZ 163
VWRPT 164
WAIT 165
WINDOW 166
ASCII communications 78, 79
B
basic operations
emulator 28
high-function graphics 32
bit planes 60
block diagrams
display RAM address control 17
emulator address control 11
graphics emulator 13
high-function graphics display memory 15
look-up table and video output section 18
microprocessor section 6
Professional Graphics Controller 2
system-bus interface 4
timing and control section 19
video control generator section 8
August 15, 1984
© Copyright IBM Corporation 1984
Index-3
c
CA 90
CIRCLE 91
CLBEG 92
CLDEL 93
clear screen 94
CLEARS 94
CLEND 95
clip hither 96
clip yon 97
CLIPH 96
clipping 61
CLIPY 97
CLOOP 98
CLRD 99
CLRUN 100
COLOR 101
color-select register 36,37
color/fills/patterns
AREA 87
AREABC 88
AREAPT 89
CLEARS 94
COLOR 101
FILMSK 113
FLOOD 116
LINFUN 119
LINPAT 120
list of commands 83, 84, 85
MASK 125
PRMFIL 145
command list begin 92
command list delete 93
command list description 71, 72
command list end 95
command list loop 98
command list read 99
command list run 100
command lists
CLBEG 92
CLDEL 93
Index-4
August 15, 1984
© Copyright IBM Corporation 1984
CLEND 95
CLOOP 98
CLRD 99
CLRUN 100
list of commands 83, 84, 85
communication protocol 80
Communications 78, 79
communications ASCII (command) 90
communications hexadecimal (command) 103
components
display memory 15, 16, 17
display RAM address control 17
emulator address control 11, 12
graphics emulator 13, 14
high-function graphics display memory 15, 16
list of major components 3,4,81
look-up table and video output section 18
microprocessor section 6, 7
system-bus interface 4, 5
timing and control section 19
video control generator section 8, 9, 10
connector specifications 180
convert 102
CONVRT 102
coordinate space 45,46,47,48,49,50,51,52,53,54,55
coordinate transformations 47
current color 58
current point 57
CX 103
D
default LUT selections for LUTINT 168
defining commands
AREAPT 89
DIS TAN 105
DISTH 106
DISTY 107
list of commands 83, 84, 85
MDMATX 128
August 15, 1984
© Copyright IBM Corporation 1984
Index-5
MDORG 129
MDTRAN 134
TDEFIN 153
VWMATX 159
VWPORT 160
VWRPT 164
WINDOW 166
DISPLA 104
display 104
display control 58, 59, 60, 62
drawing modes 58
drawing patterns 59
masks 60
primitive fills 59
viewing 62
display memory 15, 16, 17
display RAM address control 17
DISTAN 105
distance 105
distance hither 106
distance yon 107
DISTH 106
DISTY 107
DRAW 108
draw in 3D 110
draw relative 109
draw relative in 3D 111
drawing commands
ARC (2D) 86
CIRCLE (2D) 91
DRAWR3 (3D) 111
DRAW3 (3D) 110
ELIPSE (2D) 112
list of commands 83, 84, 85
POLY (2D) 141
POLYR 142
POLYR3 (3D) 144
POLY3 (3D) 143
RECT (2D) 147
RECTR (2D) 148
SECTOR 151
TEXT 154
TEXTP 155
Index-6
August 15, 1984
© Copyright IBM Corporation 1984
drawing modes 58
drawing patterns 59,60
drawing primitives 63,64,65,66,67,68
area fill command description 68
linear forms 65
move command description 63
nonlinear forms 66
point command description 63
two-dimensional and three-dimensional command format 63
vectors 64
DRAWR 109
DRAWR3 111
DRAW3 110
E
ELIPSE 112
ellipse 112
emulator
alphanumeric mode 20,21,22,23
color-select register 36, 37
description of basic operations 28
graphics mode 24, 25, 26, 27
memory requirements 42
mode register summary 40
mode-select register 38
programming the mode control and status register 35
programming the 6845 CRT controller 33, 34
sequence of events for changing modes 42
status register 41
320-by-200 color/graphics mode 24
40-by-25 alphanumeric mode 22
640-by-200 black-and-white graphics mode 27
80-by-25 alphanumeric mode 23
emulator address control 11, 12
emulator card logic diagrams 191
error handling 82
August 15, 1984
© Copyright IBM Corporation 1984
Index-7
F
fill mask 113
FILMSK 113
flag read 114
FLAGRD 114
FLOOD 116
G
graphics emulator 13, 14
graphics mode 24,25,26,27
graphics operation 30, 31
H
hexadecimal commands
hex AA (CLIPH) 96
hex AB (CLIPY) 97
hex AF (CONVRT) 102
hex AO (VWIDEN) 158
hex Al (VWRPT) 164
hex A3 (VWROTX) 161
hex A4 (VWROTY) 162
hex AS (VWROTZ) 163
hex A7 (VWMATX) 159
hex A8 (DISTH) 106
hex A9 (DISTY) 107
hex BO (PROJCT) 146
hex B1 (DISTAN) 105
hex B2 (VWPORT) 160
hex B3 (WINDOW) 166
hex CO (AREA) 87
hex Cl (AREABC) 88
Index-8
August 15, 1984
© Copyright IBM Corporation 1984
hex DO (DISPLA) 104
hex D8 (IMAGER) 117
hex D9 (IMAGEW) 118
hex EA (LINP AT) 120
hex EB (LINFUN) 119
hex EB (MASK) 125
hex EC (LUTINT) 122
hex ED (LUTSAV) 124
hex EE (LUT) 121
hex EF (FILMSK) 113
hex E7 (AREAPT) 89
hex E9 (PRMFIL) 145
hex OF (CLEARS) 94
hex 04 (RESETF) 149
hex 05 (WAIT) 165
hex 06 (COLOR) 101
hex 07 (FLOOD) 116
hex 08 (POINT) 139
hex 09 (POINT3) 140
hex 10 (MOVE) 135
hex 11 (MOVER) 136
hex 12 (MOVE3) 137
hex 13 (MOVER3) 138
hex 20 (DRAW) 108
hex 21 (DRAWR) 109
hex 22 (DRAW3) 110
hex 23 (DRAWR3) 111
hex 3C (ARC) 86
hex 3D (SECTOR) 151
hex 30 (POLY) 141
hex 31 (POLYR) 142
hex 32 (POLY3) 143
hex 33 (POLYR3) 144
hex 34 (RECT) 147
hex 35 (RECTR) 148
hex 38 (CIRCLE) 91
hex 39 (ELIPSE) 112
hex 43 (CA) 90
hex 43 (CX) 103
hex 50 (LUTRD) 123
hex 51 (FLAGRD) 114
hex 52 (MATXRD) 126
hex 70 (CLBEG) 92
August 15, 1984
© Copyright IBM Corporation 1984
Index-9
hex 71 (CLEND) 95
hex 72 (CLRUN) 100
hex 73 (CLOOP) 98
hex 74 (CLDEL) 93
hex 75 (CLRD) 99
hex 80 (TEXT) 154
hex 81 (TSIZE) 157
hex 82 (TANGLE) 152
hex 83 (TEXTP) 155
hex 84 (TDEFIN) 153
hex 85 (TJUST) 156
hex 90 (MDIDEN) 127
hex 91 (MDORG) 129
hex 92 (MDSCAL) 133
hex 93 (MDROTX) 130
hex 94 (MDROTY) 131
hex 95 (MDROTZ) 132
hex 96 (MDTRAN) 134
hex 97 (MDMATX) 128
high-function graphics
alphanumeric operation 29
ASCII communications 78, 79
communication protocol 80, 81
communications 78, 79
coordinate space 45,46,47,48,49,50,51,52,53,54,55
coordinate transformations 47
current color 58
current point 57
default LUT selections for LUTINT 168
description of basic operations 32
error handling 82
graphics operation 30, 31
list of commands 83, 84, 85
modeling matrix 49,50,51,52,53
programming considerations 43,44,45
run-length encoding 167
state 0 168, 169
state 1 170
state 255 178
state 5 176, 177
states 2-4 171,173,174,175
three-dimensional hither/yon clipping 54
three-dimensional transformation 49
Index-tO
August 15, 1984
© Copyright IBM Corporation 1984
three-dimensional viewing to two-dimensional virtual
projection 55
two-dimensional transformation 47, 48
video generation 56,57, 58
viewer reference-point matrix 53
viewing matrix 53
high-function graphics display memory 15, 16
I
image processing 74
image read 117
image transmission
IMAGER 117
IMAGEW 118
list of commands 83, 84, 85
image write 118
IMAGER 117
IMAGEW 118
interface information
connector specifications 180
monitor interface 180
L
line function 119
line pattern 120
linear forms 65, 66
LINFUN 119
LINPAT 120
logic diagrams
emulator card 183, 191
memory card 183, 196
processor card 183, 184
look-up table 121
list of commands 83, 84, 85
August 15, 1984
(c) Copyright IBM Corporation 1984
Index-ll
LUT 121
LUTINT 122
LUTRD 123
LUTSAV 124
look-up table and video output section 18
look-up table description 73
look-up table initialize 122
look-up table read 123
look-up table save 124
LUT 121
LUTINT 122
LUTRD 123
LUTSAV 124
M
MASK 125
masks 60,61,62
bit planes 60
clipping 61
matrix read 126
MATXRD 126
MDIDEN 127
MDMATX 128
MDORG 129
MDROTX 130
MDROTY 131
MDROTZ 132
MDSCAL 133
MDTRAN 134
memory card logic diagrams 196
memory requirements 42
microprocessor section 6, 7
mode register summary 40
mode set/read
CA 90
CX 103
DISPLA 104
FLAGRD 114
list of commands 83, 84, 85
Index-12
August 15, 1984
© Copyright IBM Corporation 1984
RESETF 149
WAIT 165
mode-select register 38
modeling identity 127
modeling matrix 49,50,51,52,53, 128
modeling origin 129
modeling rotate x axis 130
modeling rotate y axis 131
modeling rotate z axis 132
modeling scale 133
modeling transformations
list of commands 83, 84, 85
MATXRD 126
MDIDEN 127
MDMATX 128
MDORG 129
MDROTX 130
MDROTY 131
MDROTZ 132
MDSCAL 133
MDTRAN 134
modeling translation 134
monitor interface 180
MOVE 135
move command description 63
move in three dimensions 137
move relative 136
move relative in three dimensions 138
MOVER 136
MOVER3 138
MOVE3 137
N
nonlinear forms 66, 67
August 15, 1984
© Copyright IBM Corporation 1984
Index-13
p
POINT 139
point command description 63
point in three dimensions 140
POINT3 140
POLY 141
polygon 141
polygon in three dimensions 143
polygon relative 142
polygon relative in 3D 144
POLYR 142
POLYR3 144
POLY3 143
primitive fill 145
primitive fills 59, 60
PRMFIL 145
processor card logic diagrams 184
programming considerations
ASCII communications 78, 79
color-select register 36,37
communication protocol 80, 81
communications 78,79
coordinate space 45,46,47,48,49,50,51,52,53,54,55
coordinate transformations 47
current color 58
current point 57
default LUT selections for LUTINT 168
error handling 82
list of commands 83, 84, 85
memory requirements 42
mode register summary 40
mode-select register 38
modeling matrix 49,50,51,52,53
programming considerations for the high-function graphics
mode 43, 44, 45
programming the mode control and status register 35
programming the 6845 CRT controller 33,34
run-length encoding 167
sequence of events for changing modes 42
state 0 168, 169
state 1 170
Index-14
August 15, 1984
© Copyright IBM Corporation 1984
state 255 178
state 5 176, 177
states 2-4 171, 173, 174, 175
status register 41
three-dimensional hither/yon clipping 54
three-dimensional transformation 49
three-dimensional viewing to two-dimensional virtual
projection 55
two-dimensional transformation 47, 48
video generation 56, 57, 58
viewer reference-point matrix 53
viewing matrix 53
programming the mode control and status register 35
programming the 6845 CRT controller 33,34
PROJCT 146
projection 146
R
read-back commands 75,76
reading commands
IMAGER 117
list of commands 83, 84, 85
LUTRD 123
MATXRD 126
RECT 147
rectangle 147
rectangle relative 148
RECTR 148
relative draw
DRAWR (2D) 109
relative move
MOVER 136
MOVER3 (3D) 138
reset commands
list of commands 83, 84, 85
MDIDEN 127
VWIDEN 158
reset flags 149
RESETF 149
August 15, 1984
© Copyright IBM Corporation 1984
Index-15
rotate commands
list of commands 83, 84, 85
MDROTX 130
MDROTY 131
MDROTZ 132
VWROTX 161
VWROTY 162
VWROTZ 163
run-length encoding 167
s
save commands
list of commands 83, 84, 85
SECTOR 151
select commands
DISPLA 104
LINFUN 119
list of commands 83, 84, 85
sequence of events for changing modes 42
set commands
CA 90
CLIPH 96
CLIPY 97
COLOR 101
CX 103
FILMSK 113
FLAGRD 114
LINPAT 120
list of commands 83, 84, 85
LUT 121
LUTSAV 124
MASK 125
MDSCAL 133
POINT (2D) 139
POINT3 (3D) 140
PRMFIL 145
PROJCT 146
TANGLE 152
TJUST 156
Index-16
August 15, 1984
© Copyright IBM Corporation 1984
TSIZE 157
specifications
power requirements 181
size 181
weight 181
state 0 168, 169
state 1 170
state 255 178
state 5 176, 177
states 2-4 171, 173, 174, 175
status register 41
system reset 77
system-bus interface 4, 5
T
TANGLE 152
TDEFIN 153
text 154
list of commands 83, 84, 85
TANGLE 152
TDEFIN 153
TEXT 154
TEXTP 155
TJUST 156
TSIZE 157
text angle 152
text define 153
text description 69, 70
text justify 156
text programmed 155
text size 157
TEXTP 155
three-dimensional drawing
DRAWR3 111
DRAW3 110
MOVER3 138
MOVE3 137
POINT3 140
POLYR3 144
August 15, 1984
© Copyright IBM Corporation 1984
Index-17
POLY3 143
three-dimensional hither/yon clipping 54
three-dimensional transformation 49
three-dimensional viewing to two-dimensional virtual
projection 55
timing and control section 19
TJUST 156
TISZE 157
two-dimensional and three-dimensional command format 63
two-dimensional drawing
ARC 86
CIRCLE 91
DRAW 108
DRAWR 109
ELIPSE 112
MOVE 135
MOVER 136
POINT 139
POLY 141
POLYR 142
RECT 147
RECTR 148
SECTOR 151
two-dimensional transformation 47,48
v
vectors 64
video control generator section 8,9, 10
video generation 56, 57, 58
viewer reference-point matrix 53
viewing 62
viewing identity 158
viewing matrix 53, 159
viewing reference point 164
viewing rotate x axis 161
viewing rotate y axis 162
viewing rotate z axis 163
viewport 160
viewport/ window / projection
Index-IS
August 15, 1984
@
Copyright IBM Corporation 1984
CLIPH 96
CLIPY 97
CONVRT 102
DISTAN 105
DISTH 106
DISTY 107
PROJCT 146
VWIDEN 158
VWMATX 159
VWPORT 160
VWROTX 161
VWROTY 162
VWROTZ 163
VWRPT 164
WINDOW 166
VWIDEN 158
VWMATX 159
VWPORT 160
VWROTX 161
VWROTY 162
VWROTZ 163
VWPRT 164
w
WAIT 62,165
WINDOW 166
write commands
IMAGEW 118
list of commands 83, 84, 85
Numerals
320-by-200 color I graphics mode 24
40-by-25 alphanumeric mode 22
640-by-200 black-and-white graphics mode 27
80-by-25 alphanumeric mode 23
August 15, 1984
@
Copyright IBM Corporation 1984
Index-19
Index-20
August 15, 1984
co Copyright IBM Corporation 1984
---
-------- -----_.-
-
Personal Computer
Hardware Reference
Library
IBM Personal Computer
Data Acquisition and
Control Adapter
T echnical Reference
6138163
August 15,1984
© Copyright IBM Corporation 1984
Contents
Description .................................... 1
Major Components .......................... 3
Address Decode and Control Circuitry ........ 4
Data Bus Conversion Circuitry ............. 15
Analog I/O Device ...................... 21
Binary II 0 Device ...................... 40
Timer / Counter Device ................... 46
Interrupt Circuitry ...................... 54
Distribution Panel Connector .............. 60
Expansion Bus ......................... 64
Programming Considerations ..................... 69
Address Decoding .......................... 69
Registers ................................. 70
Device Registers ........................ 71
Timer/Counter Device Registers ........... 83
Device Number Register .................. 90
Interrupt Registers ...................... 91
Interface .......... ;.......................... 93
Distribution Panel Connector .............. ;.. 93
Expansion Bus Connectors ................... 96
Switch Settings ............................... 101
Analog Output Range ...................... 102
Analog Input Range ....................... 106
Adapter Number .......................... 108
Interrupt Level ........................... 109
Specifications ................................ 111
Data Acquisition Adapter ................... 111
Dimensions ........................... 111
Power Requirements .................... 112
System Reference Voltage ............... 112
Environment .......................... 113
Data Acquisition Adapter Devices ............ 114
Analog Output Device .................. 114
Analog Input Device .................... 116
Binary Device ......................... 119
32-Bit Timer Device .................... 121
August 15,1984
© Copyright IBM Corporation 1984
iii
16-Bit Timer/Counter Device ............ 122
Logic Diagrams ............................... 123
Index ........................................ Index-l
iv
August 15, 1984
© Copyright IBM Corporation 1984
Description
The IBM Personal Computer Data Acquisition and Control
Adapter (Data Acquisition Adapter) provides both analog and
digital I/O capabilities. It is installed in any full-length expansion
slot, and up to four may be installed in a system.
The adapter provides:
•
Four analog input channels multiplexed into an
analog-to-digital converter (ADC), with 12-bit resolution
•
Two analog output channels, each having its own
digital-to-analog converter (DAC), with 12-bit resolution
•
A 16-bit digital input port
•
A 16-bit digital output port
•
A 32-bit timer
•
A 16-bit, externally-clocked, timer/counter
•
An expansion bus.
August 15,1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
1
The Data Acquisition Adapter has a 16-bit data bus and a
buffered 8-bit data bus.
The adapter's 16-bit data bus provides access to:
•
An analog I/O device:
Analog input subsystem with four multiplexed channels
Analog output subsystem with two DACs
•
A binary I/O device:
16-bit digital input port
16-bit digital output port
Handshaking
•
An expansion bus.
The buffered 8-bit data bus provides access to:
•
Interrupt circuitry
•
A timer/counter device:
32-bit timer (Counters 0 and 1)
16-bit timer/counter (Counter 2).
Low and high bytes are transferred between the adapter's
buffered 8-bit data bus and 16-bit data bus.
A 60-pin, distribution-panel connector is provided for external
access to the analog I/O device, the binary I/O device, and the
timer/counter device.
2
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Major Components
Following is a block diagram of the Data Acquisition Adapter.
-
~
MDataBus~
Buffer
I~
R
~
OJ
14
en
~~
'f' \r-Y'
~..., g;'1-3
0
OJ
;>:
Ei
Control
Circuitry
Data Bus
Conversion
Circuitry
~
~
CARDSEL
Address
Decode
INTCLR
~
ro
-<
~
TI
'"~.
0
:::J
OJ
1>0
r-
2.
:t>
(3
'"
~[
TI
~
m
Co
~
I nterru pt
Circuitry
¢:::::;:
Ei
C>-
,[f-
-V xm
B10-B115
Binary
I/O
Device
BOO-B015
~
Handshaking
0
'"0:
OJ
~ EiH
'"OJ
c
D/AO
Jf
~
Analog
I/O
I'r.~ Device
AID INT
DIAl
AID
0-3
0
~
~
'--
0-
~.
j-
0
:::J
-0
TIMER INT
'":::J~
'---
COUNT
()
~
0
:::J
:::J
ro
;?
'~
by 14
OSC 14
MH1~,
Jl
'----v 8253-5
h
©
Copyright IBM Corporation 1984
RATE
Timer/ DELAY
Counter COUNT
IN
Device
COUNT
OUT
L---
August 15,1984
~
-
Data Acquisition Adapter
3
The following are descriptions of the major components shown in
the figure on the previous page.
Address Decode and Control Circuitry
The following are descriptions of address decode and control
circuitry.
Address Decode
Following is a block diagram of address decode.
AEN
Address
Preselection
A3, A5-A9
S5
en
~
3
L--_ _ _-'A--'-''--A_'_'_ _ _ _ _ _- J
~r------------~
BAD
BUFFRES
4
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
The signals used by the address decode circuitry are:
AEN
Address enable: De-gates the processor and
other devices from the II 0 channel to allow
direct-memory access (DMA) transfers to take
place. When active (high), the DMA
controller has control of the address bus, data
bus, read command lines (memory and I/O),
and the write command lines (memory and
I/O).
PRESEL
Preselect: Indicates preliminary address
decoding of the 'address enable' signal (AEN),
and the address bits that are common to the
adapter's base address and to the
shared-interrupt address.
CARDSEL
Card select: Indicates communication is in
process between the Data Acquisition Adapter
and the system. The shared-interrupt
re-activation function is not included.
INTCLR
Shared-interrupt reactivation control signal.
August 15,1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
5
The address preselection circuitry decodes the six address lines,
which are common in the adapter address and the
shared-interrupt address. AEN is used to prevent false decodes
during DMA cycles. Because the adapter has a base address of
hex 2E2 through 2E3, and the shared-interrupt address is hex
02Fx (where x is shared-interrupt level 3, 4, 5, 6, or 7), the
common address bits are: A9, A7, A6, and A5 equal to 1, and
A8 and A3 equal to O. The resulting signal (PRESEL) indicates
that either an adapter access or a shared-interrupt access may be
occurring.
The address decode circuitry uses the signals PRESEL, AlO, A11,
A4, and the signals from the switches S4-1 and S4-2 to decode an
adapter's base address. The control decode circuitry uses the
resulting signal (CARDSEL) as a master enable and then
generates the individual control signals.
When the address decoded is hex 2Fx (where x is the shared
interrupt level), INTCLR is generated. INTCLR reactivates the
adapter's interrupt circuitry. The address decode circuitry also
generates an INTCLR signal at power-on-reset time.
Power-on-reset occurs when the 'buffer reset' signal
(BUFFRES), which is created by the system bus signal
(RESET DRV), goes low.
6
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
System Bus Address and Control Signals
The following is a block diagram of the address and control
signals from the system bus.
,-
'roo--RESET DRV 1
I
AO
I
I
Receiver
BUFFRES
I
Receiver
I
Receivers
I
I
BAO
WDO - WD2t-,
A12-A14J...
)
v
co
........
...,
c
CD
CD
Q.
en
lOR
-<
....
'"CD
Receiver
3
co
c
'"
lOW
I
~
Receiver
Delay
Trailing
Edge
by 0.1ps
BIOR
0
....
:J
Q.
J
I
(")
-BlOW
I
BUFFREAD
BUFFREAD
L---
7
August 15,1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
7
The address and control signals from the system bus are as
follows:
RESETDRV
Resets system logic upon power-on or
during a low line-voltage outage.
RESET DRY is synchronized to the falling
edge of 'clock' and is active high.
BUFFRES
Buffer reset: Inverse of RESET DRY.
Provides power-on-reset of the adapter's
control logic. BUFFRES is active low.
WDO - WD2
Word number bits 0 through 2 (system bus
address lines A12 through A14 are buffered
and renamed WDO through WD2). Selects
word registers 0 through 7 when system bus
address line A15 is low. Selects word
registers 8 through 15 when A15 is high.
BAO
Buffered system-bus address line AO:
Selects high or low bytes.
Buffered I/O read (lOR): BIOR is active
low and is used for I/O read operations on
the buffered 8-bit data bus.
BlOW
8
Buffered I/O write(IOW): BlOW is active
low and is used for I/O write operations on
the buffered 8-bit data bus.
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
BUFFREAD
Buffer read: Indicates whether a read or a
write operation on the adapter's 16-bit data
bus is to be performed. When high, this
signal indicates a read operation, and when
it is low, a write operation is indicated.
BUFFREAD
Inverse of BUFFREAD.
August 15,1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
9
Control Decode
Following is a block diagram of the control decode circuitry.
OJ
c.....
.....
CD
....
CD
0..
(j
CARDSEL
\
Pal2
and
Additional
Logic
A15
J
WDO - WD2
0
...
BAO
-BIOR
WHRLSTB
WDEVICE
(j
DBUFFSTB
RINTSTATUS
"\
WINTCONT
v
::l
Q.
r-
"1-
Control
Decode
WCNT
0
...
Q.
...;;
::l
U'l
0CD
(J)
RCNT
--
WLBO
-BlOW
RLBI
--WHBO
BUFF READ
10
Data Acquisition Adapter
RHBI
August 15, 1984
© Copyright IBM Corporation 1984
The control decode circuitry inputs CARDSEL, A15, WDO
through WD2, BAO, BlOR, BlOW, and BUFFREAD generate
the following control strobes:
WHRLSTB
Write-high read-low strobe: Strobe for
reading or writing the data word from the
adapter's 16-bit data bus to an on-board or
expansion device.
WDEVICE
Write device: Write strobe for the
on-board or expansion device number
register.
DBUFFSTB
Data buffer strobe: Enable strobe for data
communications between the system bus
and the Data Acquisition Adapter.
RINTSTATUS
Read interrupt status: Read strobe for the
interrupt status register.
WINTCONT
Write interrupt control: Write strobe for
the interrupt status register.
WCNT
Write counter: Write strobe for the
timer / counter.
RCNT
Read counter: Read strobe for the
timer / counter.
August 15,1984
CD Copyright IRM Corporation 1984
Data Acquisition Adapter
11
WLBO
Write low byte out: Latch control strobe for
latching the low data byte for later
transmission to an on-board or expansion
device.
Read low byte in: Enable strobe for reading a
data word from an on-board or expansion
device to the adapter's 16-bit data bus. The
low byte is transmitted to the system bus
during this strobe. The high byte is latched
during RLBI for later transmission to the
system bus.
WHBO
Write high byte out: Enable strobe for writing
a data word from the adapter's 16-bit data bus
to an on-board or expansion device. The low
byte is the one previously latched in WLBO.
The high byte is the current data from the
system bus.
Read high byte in: Enable strobe for reading
the high byte (previously latched by RLBI)
from the adapter's 16-bit data bus to the
system bus.
12
Data Acquisition Adapter
August 15,1984
© Copyright IBM Corporation 1984
Device Selection
The following figure shows the device selection circuitry.
Device
Select
Strobes
Circuitry
1;>
::J
[
WHRLSTB
~
ae-
m
x
ASO-AS15
V
~
o·
::J
Delay
Leading
Edge
by
cc
5i
WRITEREAOGATE
0.11.15
ll:
it
~
OVO-DVl "
Device
I------,V
Number
Register
-
~
BOO-BOl ~
~
"'-
VL--.----J
Cl
~
'"
~
WOEVICE
August 15,1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
13
The device number register stores the device number. Device
strobes are generated for on-board and expansion devices.
The following are used for device selection:
DVO - DV7
Device number register bits 0
through 7
WRITEREADGATE
Strobe for all devices
ASO through AS15
Strobes for devices 0 through 15:
AS8 selects the binary I/O device,
and AS9 selects the analog I/O
device.
14
Data Acquisition Adapter
August 15,1984
© Copyright IBM Corporation 1984
Data Bus Conversion Circuitry
Following is a block diagram of the data bus conversion circuitry_
-,-'
,
OBUFFSTB
e
(JJ~
~
t
GATE
Data Bus
Buffer
WlBO
~
BOO-B07
"
C1)
3
OJ
OIR
ClK
low Byte
Write
Register
S;
lOO-l07
"
v
~~
OJ
s..
BUFFREAO
~
--
C1)
'l'
WHBO-
0-
~
(Xl
~
~
t
~
0
»
0-
'"
"S
GATE
~
BOO-BD7
S;
v
'"OJ
0
~
1G
2G
HOO-H07
'"OJ
~ S;
Line
Driver
RlBI
BOO",B07
K.
t
t
1G
2G
lOO-l07
/I
Line
Receiver
BOO-BO';-f
ClK
High Byte
~
Read
Register
V
HOO-H07
I~
'I
GATE
RHBI
August 15,1984
© Copyright IBM Corporation 1984
t
Data Acquisition Adapter
15
Data Bus Buffer
The system's data bus (DO through D7) is buffered by the data
bus buffer to create the adapter's buffered data bus (BDO through
BD7). The data bus buffer is activated by DBUFFSTB during all
communications between the system bus and the Data
Acquisition Adapter. The data direction is determined by
BUFFREAD.
The buffered 8-bit data bus is used for direct 8-bit data
communication with the interrupt circuitry, the timer/counter
device, and the device number register.
The buffered 8-bit data bus also communicates with the low byte
write register, a line driver, a line receiver, and the high byte read
register to implement the conversion of the buffered 8-bit data
bus into the adapter's 16-bit data bus.
16
Data Acquisition Adapter
August 15,1984
© Copyright IBM Corporation 1984
Writing Data
Data is written sequentially from the system data bus to the
adapter's 16-bit data bus. The low byte is first written to an even
address, then the high byte is written to an odd address. The
entire 16-bit word is transmitted to an on-board or expansion
device at the same time that the high byte is written.
When data is written from the system data bus to an even address
(AO is 0), the WLBO (write low byte out) strobe occurs. The
low-byte write register latches the data.
When data is written from the system data bus to an odd address
(AO is 1), the WHBO (write high byte out) strobe occurs. The
low-byte write register transmits the previously latched low byte
to the adapter's 16-bit data bus LD lines, 0 through 7. At the
same time, the line driver transmits the current data on the
buffered 8-bit data bus BD lines, 0 through 7, to the adapter's
16-bit data bus HD lines, 0 through 7.
August 15,1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
17
Following is a write timing diagram of the adapter's 16-bit data
bus.
-
0.5).15
BlOW - - -.. I
_0.5).15
0.1).15
BUFFREAO - -....... 1
OBUFFSTB - - - -.. I
WLBO - - - -...1
low byte
latched 1....
-------4---+----write of 16-bit
WHBO
BOO-B07
LOO-L07
Strobes:
WRITEREAOGATE
ASO-AS15
18
---------------1-..
Data Acquisition Adapter
1
August 15,1984
© Copyright IBM Corporation 1984
Reading Data
Data is read sequentially from the adapter's 16-bit data bus to the
system data bus. The low data byte is first read at an even
address, then the high data byte is read at an odd address. The
entire 16-bit word is transmitted from an on-board or expansion
device at the same time that the low byte is read.
When data is read to the system data bus at an even address
(AO is 0), the RLBI (read low byte in) strobe occurs. The line
receiver transmits the low byte from the adapter's 16-bit data bus
LD lines, 0 through 7, to the system data bus. At the same time,
the high-byte read register latches the data from the adapter's
16-bit data bus HD lines, 0 through 7.
When data is read from the system data bus at an odd address
(AO is 1), the RHBI strobe occurs. The high-byte read register
transmits the previously latched high byte to the system data bus.
August 15,1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
19
Following is a read timing diagram of the adapter's 16-bit data
bus.
o.5I1s_
-
~
-
.-0.5
f---O.ll1s
BUFFREAO
OBUFFSTB
low byte read
high byte latched
latched high byte
read
RHBI
BOO·BD7
LOO·L07
j/~
HOO·H07
Strobes:
o.111s
-
Valid
~////////h
l-
WRITEREAOGATE
ASo·ASi5
I'----'
20
Data Acquisition Adapter
August 15,1984
© Copyright IBM Corporation 1984
Analog 110 Device
The Data Acquisition Adapter's analog I/O device consists of two
subsystems:
•
Analog input: An analog-to-digital conversion subsystem.
•
Analog output: A digital-to-analog conversion subsystem.
Analog Input Subsystem
On the following page is a block diagram of the analog input
subsystem.
August 15,1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
21
WDO
WDI
WD2
AS9
BUFF READ
Analog
Device
Control
Decode
A/DO±r-----------~
AD574AK
12-Bit
ADC
to
AID 3±
0>
'"
;:;-
~
~
OJ
5i
o
~- AIDCE
AID CO
AID BUSY State
INT
Control
AI
Status
Register
AID INT State
Circuitry
RD AID STATUS!
.--------'
AID Channel Select
AI
Co n trol 1--------'
Register CONVERT START
EOCINT ENABLE
WR AID CaNT
22
Data Acquisition Adapter
August 15,1984
© Copyright IBM Corporation 19S4
Analog-to-digital conversion is the process of converting analog
signals (voltages) over a given range to digital values.
Unlike digital (binary) signals, which have only two voltage
states, analog signals have infinite voltage levels over a particular
range.
Analog-to-digital converters (ADCs) are categorized by the
number of bits of resolution they allow. The greater the number
of bits, the greater the number of discrete voltage levels that can
be represented.
The Data Acquisition Adapter has an analog input device with the
following features:
•
Four, multiplexed, differential channels
•
An ADC with 12-bit resolution
•
Switch-selectable ranges
•
Optional data-conversion control with 'AID convert out' and
'AID convert enable in' lines.
August 15,1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
23
The Data Acquisition Adapter's analog input device (device
number 9) has four channels, which are multiplexed into a single
ADC. This device converts analog signals in one of three ranges
to digital values in the range of 0 to 4095.
The three switch-selectable ranges are:
+ 5 volts
•
- 5 to
•
-10 to + 10 volts
•
0 to + 10 volts
The relationship of the analog input voltage to the returned digital
value depends on the range for which the hardware is configured.
The selected range setting for analog input is in effect for all
analog input channels. For example, in the -5 to +5 volt
configuration, an input of +4.997 volts generates a full-scale
value of 4095; an input of 0 volts generates a value of 2048; and
an input of -5 volts generates a value of O.
24
Data Acquisition Adapter
August 15,1984
© Copyright IBM Corporation 1984
Analog Input Device Control
The use of the AS9 strobe causes the analog input device to be
accessed as device number 9.
The control decode circuitry of the analog device decodes WDO
through WD2, AS9, and BUFFREAD to generate the following
control signals:
WRA/DCONT
Write analog-to-digital control.
Allows the AI control register to be
written to.
RD AID STATUS
Read analog-to-digital status. Allows
reading of the AI status register.
RDA/DVALUE
Read analog-to-digital value. Allows
reading of the AI data register.
Analog Input Device Registers
AI Control Register
The AI control register contains the
analog-to-digital channel selection,
analog-to-digital interrupt-enable
information, and convert start bit
information. The AI control register is
cleared by BUFFRES during
power-on- reset.
AI Status Register
The AI status register contains
information about 'AID busy,' the
'AID interrupt status,' and the
readback of the 'AID interrupt enable.'
AI Data Register
The 16-bit AI data register contains
the data from the ADC. Because the
output of the ADC is a 12-bit digital
value, the four highest bits of the
register are grounded.
August 15,1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
25
Following is a timing diagram of analog-to-digital conversion.
'" '"
,.5-,.5-
Ii]
C")
II
II
c
x
'E E'"
~~
...E~
OJ
/
,......-'
..........
/
/'
/
'"
N
1
W
..J
cc
f-
a:
-
(Jl
::J
ff-
a:
w
>
z
a
u
26
(Jl
cc
z
0
'
z
0
u
0
::c
Data Acquisition Adapter
I
......
'"
OJ
(Jl
..J
I
cc
......
'"
OJ
>-
(Jl
::J
z
(Jl
cc
f-
OJ
;:.:
LDO-LD7
HDO-HD3
0
...
~
vi
Ql
Ql
OJ
c
VI
AD7545
12-Bit
Buffered
DAC
D/A 0 OUT
~
"r--
0
u;.
...
~.
c:r
c
!7.
0
:l
-0
Ql
:l
~
(")
LDO-LD7
HDO-HD3
0
~
-0
AD7545
12-Bit
Buffered
DAC
:l
:l
...n..,
ell
D/A 1 OUT
0
-
34
Data Acquisition Adapter
August 15;1984
© Copyright IBM Corporation 1984
The Data Acquisition Adapter includes an on-board
digital-to-analog output device with the following features:
•
Two analog output channels, with each channel using
separate DACs with 12-bit resolution
•
Switch-selectable ranges for each converter
Each DAC converts digital values in the range of 0 to 4095 to
voltages in one of three ranges. The switches on the adapter
control voltage polarity and range.
The three switch-selectable ranges are:
•
-5 to +5 volts
•
-10 to + 10 volts
•
0 to + 10 volts
The settings of these switches determine the relationship between
analog output values and the voltages from the analog output
device. The relationship of the digital value to the analog output
voltage depends on the range for which the hardware is
configured. Because each analog output channel has its own
DAC, the analog output range can be set for each channel. For
example, in the 0 to + 10 volt configuration, a digital value of 0
generates an output of 0 volts; a digital value of 2048 generates
an output of +5 volts; and a digital value of 4095 generates an
output of +9.997 volts.
August 15,1984
© Copyright IBM Corporation 19R4
Data Acquisition Adapter
35
Analog Output Device Control
The control decode circuitry of the analog device decodes WDO
through WD2, AS9, and BUFFREAD to generate the following
control signals:
WRD/ACONT
Write digital-to-analog control:
Controls the writing of the
channel-select bit to the AO control
register. The channel-select bit is used
to determine which digital-to-analog
write strobe to generate.
WR D/A VALUE
Write digital-to-analog value:
Controls the generation of the
digital-to-analog write strobes.
WR D/ A VALUE occurs when the
AO data register is addressed.
Analog Output Device Registers
AO Control Register
When the 'write D/ A value' signal
occurs, the digital-to-analog write
value control circuitry either strobes
D/ A 0 or D/ A 1, on the basis of the
channel-select bit in the AO control
register.
AO Data Register
When either AD7545 DAC receives a
digital-to-analog write strobe, it latches
a 12-bit digital value from the
adapter's 16-bit data bus. Each DAC
has data latches that are loaded when
the AO data register address is written
to. The AD7545 DAC then performs
the digital-to-analog conversion, and
an analog value is sent to the
distribution panel connector by
'D/ A 0 out' or 'D/ A lout.'
36
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Analog Output Potentiometers
Four potentiometers (RI8, R19, R20, and R21) on the Data
Acquisition Adapter control bipolar offset and gain for the analog
output device. The following diagram shows the location of these
potentiometers.
m,mO
R19
August 15,1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
37
Bipolar Offset:
R18 controls bipolar offset for channel 0, and R20 controls it for
channel 1. The value of the potentiometer is set so a negative
full-scale voltage is provided on the analog output channel when
the digital code 0000 0000 0000 is sent to the DAC for that
channel. The potentiometer takes effect when a bipolar range is
selected. When the unipolar range is selected, the DAC output is
o volts.
The following table lists the output voltages for the digital code
000000000000 (000 hex).
Range
Output Voltage for 000 Hex
Code
o to +10 volts
-5 to +5 volts
0.00000 volts
-5.00000 volts
-10 to +10 volts
-10.00000 volts
The following shows the first few analog output voltages for the
-5 to + 5 volt range.
Analog Output
~/
-4.99268V
~/
-4.99512V
/
/
/
/
/
//
.//
-4.99756V
/
-5.00000V
/
/
1 lSB = 2.44 mV
,//
000
001
002
003
Input Code (Hex)
38
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Gain:
R19 controls gain for channel 0, and R21 controls it for channel
1. The value of the potentiomenter is set so a positive full-scale
-1 LSB voltage is provided on the analog output channel when
the digital code 1111 1111 1111 is sent to the DAC for that
channel.
The following table lists the output voltages for the digital code
1111 1111 1111 (FFF hex).
Range
Output Voltage for FFF Hex
Code
o to +10 volts
+9.99756 volts
-5 to +5 volts
+4.99756 volts
-10 to +10 volts
+9.99512 volts
The following shows the last few analog output voltages for the
-10 to + 10 volt range.
Analog Output
/
//
9.99512V
/
/
/
1 LSB
= 4.88 m v
,//
9.99024V
.
9. 98536V
/
/
/
/
/
/
/
/
FFD
FFE
FFF
Input Code (Hex)
August 15,1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
39
Binary I/O Device
Following is a block diagram of the binary I/O device.
-
WOO
WD1
WD2
ASS
BUFFREAD' -
Binary
Device
Control
Decode
r--BIHOLD
r-
~
L
}>
"-
LDO-LD7
HDO-HD7
"
'"
"E
r--
'!;
Binary
In
Register
B10-B115
'"
0
~:
~-
m
0-
ro;::;"
0
RD BI VALUE
~
t
'"o:J
-u
'"
V
r--
WR BO VALUE
~
LDO
f----'
LD2
WR BIN CONT
LDO
~
()
0
~
LDO-LD7
HDO-HD7
Binary
Out
Register
::J
::J
CD
;:.
BOO-B015
~
>
t
Binary
Control
Register
BO STROBE
BI CTS
t
BI STROBE
Binary
Status
Register
BO CTS
LD2
1---1
7
RD BIN STATUS
........
40
::J
::J
~
BO GATE
5:
'\
2.
0
Data Acquisition Adapter
+
'--
August 15, 1984
© Copyright IBM Corporation 1984
The Data Acquisition Adapter's binary I/O device has the
following features:
•
A 16-bit binary output port (BOO through B01S)
•
A 16-bit binary input port (BIO through BI15)
•
Input and output handshaking over the 'strobe' and
'c1ear-to-send' lines
•
Direct control using BO GATE ('binary out gate') and
BI HOLD ('binary in hold').
Digital signals have only two voltage states: On (high, +3 volts)
and Off (low, +0.2 volts). Digital signals in this range are called
TTL signals, because they are the proper levels to be interpreted
by the transistor-to-transistor logic circuitry. These signals have
many uses in data acquisition and control applications. Among
these are sensing the state of two-state devices and controlling
devices that require two-state control signals.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
41
Binary II 0 Device Control
The use of the AS8 strobe causes the binary I/O device to be
accessed as device number 8.
The AS8 strobe as an enable, the WDO through WD2 word bits,
and the BUFFREAD signal are used to decode which binary
decode operation is to occur.
Following are the four decode operations:
WRBINCONT
Write binary control: Controls the
latching of the binary output strobe
(BO STROBE) and the binary input
clear-to-send (BI CTS) bits by the binary
control register.
RD BIN STATUS
Read binary status: Controls the reading
of the binary input strobe (BI STROBE)
and the binary output clear to send
(BO CTS) bits by the binary status
register.
WR BO VALUE
Write binary value: Controls the writing
of the binary output word (BOO through
B01S) to the binary output register.
RD BI VALUE
Read binary value: Controls the reading
of the binary input word (BIO through
BI1S) from the binary input data register.
42
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Binary I/O Device Registers
Following is a description of the binary I/O device registers.
Binary Control Register
Contains the BO STROBE bit and
the BI CTS bit. These bits do not
physically cause or prevent binary
II 0 events from occurring. They are
programming control bits.
Binary Status Register
Allows the status of BO CTS and
BI STROBE bits to be monitored.
These bits do not physically cause or
prevent binary II 0 events from
occurring. They are programming
status bits.
Binary Input Register
When BI HOLD is brought high (or if
no connection is made), the binary
input register is not latched and
allows the current state of the binary
input lines to be monitored by reading
the binary input register.
Grounding BI HOLD causes the
binary input register to latch the
current state of all binary input lines.
If the grounding of the BI HOLD line
is maintained, any later read will
obtain the value that was present
when the line was initially grounded.
Binary Output Register
Contains the binary output word
(BOO through BOIS). Grounding the
BO GATE signal places the binary
output port in the tri-state condition
(all points floating). The binary
outputs are gated out when the
BO GATE signal is brought high
(or if no connection is made).
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
43
The Data Acquisition Adapter's binary I/O device consists of two
subsystems that use low-power Schottky logic:
•
Binary input
•
Binary output
Binary Input Subsystem
Following is a description of the binary input subsystem.
Binary Input Port (BIO through BIl5)
All bits of the binary input port (BIO through BI15) are pulled to
their high state internally. This means that if nothing is connected
to the binary input port, execution of a binary input function
returns a value of 65535 (all bits set to 1).
The input port of the Data Acquisition Adapter's binary 1/ 0
device can be used to sense the state of up to 16 individual binary
signals.
The binary input port also can be used for input of binary data
words (16-bit) from another device.
Binary Input Hold
The entire binary input port may be latched at any time by pulling
the BI HOLD signal low. These and all other data and
communication lines are pulled high through internal resistors to
+5 volts. No connections to them are necessary unless their
features are to be used.
Binary Input Handshaking
Binary input samples can be synchronized with binary words
generated by an external device. The external device must be
able to send parallel binary data when it receives a signal from the
Data Acquisition Adapter's binary I/O device. It also must be
able to generate a TTL signal that indicates the data word is valid
and should be sent by the Data Acquisition Adapter.
44
Data
Acqui~ition
Adapter
August 15,1984
© Copyright IBM Corporation 1984
Binary Output Subsystem
Following is a description of the binary output subsystem.
Binary Output Port (BOO through BOIS)
This subsystem uses high-power, tri-state, bus-driving devices.
Changes in the binary output word are carried out on a per-bit
basis. Only those bits affected by a change in the output word are
actually changed. All others remain the same.
The output port of the binary I/O device supplies 16 high/low
signals under program control. As with the input port, these
signals can be used individually or considered as a 16-bit data
word.
Binary Out Gate
You may place the output port in tri-state by pulling the binary
out gate (BO GATE) lines low. These and all other data,
handshaking, and control lines are pulled high by internal resistors
to +5 volts. No connections to them are necessary unless your
application requires handshaking or control.
Binary Output Handshaking
Because all communication lines are internally pulled up to their
logical true state, you can use or not use binary output
handshaking, depending on the requirements of your
communication setup.
Binary output can be synchronized with the data input capabilities
of the external device. The external device must be able to send a
TTL signal to indicate it is ready for new data. It also must be
able to accept parallel binary data when it recieves a signal from
the Data Acquisition Adapter's binary I/O device indicating the
data is available.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
45
Timer / Counter Device
The timer/counter device is an 8253-5 Programmable Interval
Timer. The timer/counter device provides three independent,
down-counting, 16-bit counters. Each counter can be
programmed to operate in one of four modes. In this
implementation, Counters 0 and 1 are cascaded to provide a
32-bit timer. Counter 2 is not cascaded and provides an
independent 16-bit timer/counter. These counters can be used to
generate interrupts, provide pulses (or pulse trains) to the
distribution panel connector (RATE OUT, DELAY OUT, and
COUNT OUT), and count events (COUNT IN).
Following is a diagram of the timer/counter device.
C/)
-<
~
3
OJ
"
14 MHz OSC
Divide
by
14
8253-5
g
RATE OUT
DELAY OUT
~
~
;::'"
~
COUNT OUT
COUNT 2 OUT
(Counter
Int.1
46
Data Acquisition Adapter
COUNT lOUT
Interrupt
(Timer Int_1
Circuitry
August 15, 1984
© Copyright IBM Corporation 1984
Timer/Counter System Interface
Following is a description of how the Data Acquisition Adapter
controls its timer/counter device.
BDO - BD7
The Data Acquisition Adapter's buffered
data bus lines are connected to data lines
(DO through D7) of the timer/counter
device's internal data-bus buffer.
RDCNT
Read counter: Connected to the RD pin
of the timer/counter device. Used as a
control signal when reading the values of
the counters.
WRCNT
Write counter: Connected to the WR pin
of the timer/counter device. Used as a
control signal when writing mode
information and loading the counters.
WDOandWDl
Connected to the AO and Al pins of the
timer / counter device. They select which
of the three counters to be operated on,
and address the control register.
The following lists the resulting timer/counter device operations
performed based on the values of the timer/counter device's
address and control signals.
Note:
The CS pin of the timer/counter device is tied low.
CS
RD
WR
Al
AO
Description
0
0
1
0
0
0
0
0
1
Load Counter 0
1
1
0
0
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
Load Counter 2
Write Mode Word
Read Counter 0
0
0
0
1
1
1
0
1
X
X
1
X
X
0
0
1
0
0
X
1
X
1
August 15,1984
© Copyright IBM Corporation 1984
Load Counter 1
Read Counter 1
Read Counter 2
No-Operation 3-State
Disable 3-State
No-Operation 3-State
Data Acquisition Adapter
47
32-Bit Timer
Following is a description of the output of the 32-bit timer
(Counters 0 and 1), and how it is clocked.
First Stage (Counter 0)
CLKO
A 1.023-MHz signal (50% duty cycle)
from the system bus' 14-MHz OSC and
divide-by-14 circuitry.
OUT 0
Output of Counter O.
RATE OUT
Inverted state of OUT 0 that is brought to
the distribution panel connector.
Second Stage (Counter 1)
CLK 1
The Counter-l clock. The output of
Counter 0 (OUT 0) is cascaded into the
counter of clock 1.
OUTl
Output of Counter 1. Provides the
'count 1 out' signal that is used by the
interrupt circuitry.
DELAY OUT
Inverted state of OUT 1 that is brought to
the distribution panel connector.
48
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
16-Bit Timer/Counter
Following is a description of the output of the 16-bit
timer/counter (Counter 2), and how it is clocked.
CLK2
The Counter-2 clock.
COUNT IN
Clocks Counter 2.
OUT 2
Output of Counter 2. Provides the
'count 2 out' signal used by the interrupt
circuitry.
COUNT OUT
Inverted state of OUT 2 that is brought to the
distribution panel connector.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
49
Counter Modes
The following counter modes apply to Counters 0 through 2.
Note: "Output" in the following timing diagrams refers to
the OUT 0, OUT 1, and OUT 2 pins of the timer/counter
device. Counter outputs, RATE OUT, DELAY OUT, and
COUNT OUT, on the distribution panel connector are the
inverted state of OUT 0, OUT 1, and OUT 2.
Mode 0: Interrupt on Terminal Count
Initially, the output is low after the mode-set operation. After the
count is loaded into the selected count register, the output
remains low, and the counter counts. When terminal count is
reached, the output goes high and remains high until the selected
count register is reloaded with the mode or a new count is loaded.
The counter continues to decrease after terminal count is reached.
Rewriting a counter register during counting results in the
following:
•
A Write to the first byte stops the current counting.
•
A Write to the second byte starts the new count.
Following is the timing diagram for mode
o.
Mode 0: Interrupt on Terminal Count
CLOCK
WRn
1 . . . __---'
432
OUTPUT
o
1---
(I NTE R RU~P;:;:T;)-!n(n:;;;~4iT)-~I.;:=:=~n:;-==::::;·~I
SO
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Mode 1: Programmable One-Shot
This mode is not used because the timer/counter device's gate
pins (GATE 0 through GATE 2) are tied high.
Mode 2: Rate Generator
Divide-by-N counter. The output is low for one period of the
input clock. The period from one output pulse to the next equals
the number of input counts in the count register. If the count
register is reloaded between output pulses, the present period is
not affected, but the next period reflects the new value.
When the mode is set, the output remains high until the count
register is loaded. The output can then also be synchronized by
programming.
Following is the timing diagram for mode 2.
Mode 2: Rate Generator
CLOCK
4
3
2
0(4)
3
2
OUTPUT--------------------~~
0(3)
OUTPUT~
3
2
0(3)
U
1
0(3)
U
2
o
2
LS
0(3)
2
U
(n~3)
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
51
Mode 3: Square-Wave Rate Generator
This mode is similar to mode 2, except the output remains high
until half the count is complete (for even numbers), then goes low
for the other half. This is accomplished by decrementing the
counter by 2 on the falling edge of each clock pulse. When the
counter reaches terminal count, the state of the output changes,
and the counter is reloaded with the full count; the complete
process then repeats.
If the count is odd and the output high, the first clock pulse after
the count is loaded, decreases the count by 1. Subsequent clock
pulses decrease the clock by 2. After time-out, the output goes
low and the full count is reloaded. The first clock pulse after the
reload, decreases the counter by 3. Subsequent clock pulses
decrease the count by 2 until time-out. Then the complete
process repeats. In this way, if the count is odd, the output will
be high for (N + 1)/2 counts and low for (N - 1)/2 counts.
Following is the timing diagram for mode 3.
Mode 3: Square Wave Generator
~
CLOCK
4
2
4
2
4
2
4
2
4
2
4
2
4
4
2
5
2
5
4
2
5
2
5
4
2
OUTPUT~
(n~4)
5
I
OUTPUT~
(n~5)
52
Data Acquisition Adapter
August 15,1984
© Copyright IBM Corporation 1984
Mode 4: Software-Triggered Strobe
After the mode is set, the output is high. When the count is
loaded, the counter begins counting. When the counter reaches
terminal count, the output goes low for one input clock period,
then goes high again.
If the count register is reloaded during counting, the new count is
loaded on the next eLK pulse.
Following is the timing diagram for mode 4.
Mode 4: Software Triggered Strobe
CLOCK
WRI
n=4
4
3
2
OUTPUT
a
u
Mode 5: Hardware-Triggered Strobe
This mode is not used because the pins for gates 0 through 2 are
tied high.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
53
;-J
:::r
(l)
......
0
TIMER INT ENABLE
~.
OJ
COUNTER
INT ENABLE
::j;
~
CD
"-
Generation of
Interrupt Request
(I)
~
00
~
"'W"'R"I"'N"T"""'C"'O"N;;-;-TT
~
BUFF RES
~ BOO-.-_ _,
5i B07 Interrupt
Status
(Active low for
2 System-ClK
Cycles)
IRQ ENABLE
::::s
(JQ
.....
CD
00
3
!Il
OJ
0'"
5i
-
0
(")
~
+5V
0..
~.
IRQ4
(JQ
'"1
iRQ5
!Il
IRQ6
IR07
0
......
3
.....
:::r
(l)
.....
::::s
.....
(l)
'"1
COUNT lOUT
HH
COUNT 2 OUT-.....~I--il
2
"r:l
AID INT
.....
'"1
;::::
.....
.....
.....
(")
IRQ
'from expansion bus
and distrubution panel
connector
('tl
- 'aa
0
BOO-B07
c
~
=
""""
INTClR
(")
'"1
~
n
...
'"'l
n
e.
~
The Data Acquisition Adapter can generate an interrupt from the
following individually maskable sources:
•
32-bit timer (cascaded 16-bit Counters 0 and 1 of the
timer/counter device)
•
16-bit externally-clocked timer/counter (Counter 2 of the
timer/counter device)
•
ADC 'end of conversion' signal
•
IRQ external interrupt (on the distribution panel connector
and the expansion bus).
Interrupts generated by the Data Acquisition Adapter can be set
to an interrupt level in the range of IRQ3 through IRQ7. The
interrupt level is set with the switches of S5 on the adapter and
must be set before adapter installation. IRQ7 is recommended.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
55
Interrupt Control Register
Following is a description of the bits of the interrupt control
register.
Bit 0
TINT ENABLE: Enables 32-bit timer interrupts
(Counters 0 and O.
Bit 1
CINT ENABLE: Enables 16-bit timer/counter
interrupts (Counter 2).
Bit 2
IRQ ENABLE: Enables the IRQ (external
interrupt) line and analog-to-digital
end-of-conversion interrupts as sources of
interrupts.
Bit 3
Reserved for reading status.
Bit 4 - 6
Not used.
Bit 7
LINT RESET: Performs the local-reset function.
Note: Power-on-reset (BUFFRES) resets the interrupt
control register (clearing all bits and disabling interrupts).
56
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Interrupt Status Register
Following is a description of the bits of the interrupt status
register.
Bits 0 - 3
Provided for reading the status of the
corresponding interrupt-enable bits listed under
"Interrupt Control Register". Bit 3 is not
currently used.
Bit 4
TINT STAT: The timer interrupt status (COUNT
1 OUT), which is the state of the output of the
second chained timer stage (Counter 1 of the
timer / counter device).
Bit 5
CINT STAT: The counter interrupt status
(COUNT 2 OUT), which is the state of the output
of the 16-bit timer/counter (Counter 2).
Bit 6
IRQ STAT: The IRQ (external-interrupt) status.
The on-board 'A/D interrupt' signal is logically
ORed into the IRQ (external-interrupt) function.
Bit 7
Read back as a O.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
57
Interrupt Request Pulse
The corresponding three interrupt-enable and three
interrupt-status lines are logically ANDed. Any combination of
the three interrupt sources may be enabled. The enabled
interrupts are logically ORed to generate the adapter-interrupt
trigger signal. This signal causes the generation of an 'interrupt
request out' pulse by enabling a tri-state driver to be active low
for two cycles of the system clock. The output of this driver is
connected to the desired system interrupt level (IRQ3 through
IRQ7) by switch S5. When not active low, the tri-state driver is
floating and allows other adapters to share the interrupt line.
Interrupt Reactivation
When the shared-interrupt line pulses low, regardless of whether
the Data Acquisition Adapter or another interrupt-sharing
adapter was the source, the interrupt-reactivation circuitry
prevents the Data Acquisition Adapter from generating interrupts.
Thus, a single interrupt causes deactivation of additional
interrupts. Additional interrupts are reactivated by either the
'local reset' signal (only one Data Acquisition Adapter
reactivated) or the INTCLR signal (all interrupt-sharing adapters
reactivated). A logical OR of the 'local reset' or INTCLR
shared-interrupt reactivation signals starts the
interrupt-reactivation circuitry.
58
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Following is a description of the two shared-interrupt reactivation
signals.
Local Interrupt Reset
The local-interrupt-reset bit in the interrupt control register
controls the reactivation of only one Data Acquisition Adapter.
The particular adapter is singled out by the adapter-number bits
(AlO and All) in the adapter's I/O address space.
Global Interrupt Reset
A global-interrupt reset also can be performed. This resets the
interrupt circuitry of all adapters sharing a particular interrupt
level. The only requirement is that the adapters support interrupt
sharing. The Data Acquisition Adapter does support interrupt
sharing.
To perform a shared-interrupt global reset, an I/O Write to an
address hex 02Fx (02F3 through 02F7) is performed for a
particular interrupt level (IRQ3 through IRQ7). Thus, to reset all
adapters sharing interrupt IRQ7, an 1/ a Write to hex 02F7 is
performed. The output value is not important.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
59
Distribution Panel Connector
Following is a block diagram of the signals of the distribution
panel connector, 14.
r---
D/AD
Analog
I/O
Device
D/A1
A
AID 0-3+
'l
A
A/D 0-3-
'l
A/D CE
A/D CO
+10V REF
AGND
CJ
BOO-B015
.1'..
V
BO GATE
Binary
I/O
Device
~:
or
~
o·
~
-c
0>
~
BO CTS
~
()
0
BO STROBE
~
::J
CD
~
A
BIO-BI15
Q
....
BIHOLD
BI CTS
BI STROBE
DGND
~
RATE OUT
Timer/Counter
Device
DELAY OUT
COUNT IN
COUNT OUT
Interrupt
Circuitry
60
Data Acquisition Adapter
IRQ
L----
August 15, 1984
© Copyright IBM Corporation 1984
Distribution Panel Connector Signals
The following is a description of how the distribution panel
connector, J4, provides access to the interrupt circuitry, and the
analog I/O, binary I/O, and timer/counter devices.
D/A 0, D/A 1
DAC outputs.
EXT +10VREF
10-volt reference output.
AGND
Analog ground: The system ground
reference for the analog devices in the
system.
A/D 0- to A/D 3-
Channels 0 through 3 ADC inputs
(low).
A/D 0+ to A/D 3+
Channels 0 through 3 ADC inputs
(high).
DGND
Digital ground: The system ground
reference for the digital devices in the
system.
A/DCE
'Convert enable' input for the ADC.
When high, enables conversion.
A/DCO
'Convert out' indicator for the ADC.
When high, indicates a conversion was
requested. Returns to low when the
conversion is complete.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
61
BIHOLD
Binary-input hold: Latch control for the
binary input port. When low, the binary
input device latches the state of all input
lines.
BISTROBE
(Input) Binary input strobe: When high,
indicates the binary input data is
available.
BIO - BIlS
Binary input port, bits 0 through 15.
BOO - BOIS
Binary output port, bits 0 through 15.
BO GATE
(Input) Binary output gate: Tri-state
enable for the binary output port. When
low, the binary outputs (BOO through
BOIS) are floating.
BO STROBE
(Output) Binary output strobe: When
high, indicates that new data was sent.
BOCTS
(Input) Binary output clear-to-send:
When high, permits new binary-output
port data to be sent.
BICTS
(Output) Binary input clear-to-send:
When high, indicates the binary input
data is being requested.
62
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
(Input) External-device,
interrupt-request: Active low.
RATE OUT
Output from the first stage of the 32-bit
timer (Counter 0). The 'rate out' signal
is the inverse of the timer/counter device
output.
DELAY OUT
Output from the second stage of the
32-bit timer (Counter O. The 'delay out'
signal is the inverse of the timer/counter
device output.
COUNT OUT
Output from the 16-bit counter device
(Counter 2). The 'count out' signal is the
inverse of the timer/counter device
output.
COUNT IN
Input to the 16-bit counter device
(Counter 2).
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
63
Expansion Bus
Following is a block diagram showing device selection signals,
control signals, and data bus lines which make up the expansion
bus.
-
l>
~'-r-
a.
To
Interrupt
Circuitry
~
LDO-LD7"'-r-
V1-
~
: N°W
t..
Data )
~
;::'.
V
HDO-HD7
0.11
AS8
"-
K
;~~1
V
~
AS9
;:'.
~
IRQ
m
x
.-J'. Device
Select
Strobes
Circuitry
()
0
High Data)
"C
Q)
ASO-AS15
ao·
:>
v IiiCl
2-
...
ac:r
Delay
Leading
CD
Edge
'" WHRLSTB
by
O.lJ.ls
t..
Ul
WRITEREADGATE
H
'ij
.
~
"
CD
a.
Device
Number
Register
~
DVO-DV7
-v
WD3
Cl)
OJ
;::'.
...0
WDEVICE
Q)
Q)
Cl
Iii
•
+5V
lr
WD3
~
WDO-WD2
"
BUFFREAD
BUFFREAD
Buffered Control
BUFF 00
64
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
The expansion bus is an expansion interface for data acquisition
and control adapters. The bus consists of two 34-pin transition
connectors, 11 and 12, on the Data Acquisition Adapter.
All drivers on the bus are intended to be low-power Schottky
(LS) TTL bus drivers or equivalent devices. Such devices can
drive below 0.4 volts at 12 milliamperes load current, and above
2.4 volts at 2.6 milliamperes.
All receivers on the bus are intended to be no more than two LS
TTL loads for each external device on any bus line. Such devices
will present a load current of no more than 0.8 milliamperes
sourcing at 0.4 volts, and no more than 40 microamperes sinking
at 2.4 volts. A single LS TTL load for each external device on
any bus line is preferred.
Drivers on the bidirectional data lines must be tri-state devices
enabled only during the appropriate strobes.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
65
Expansion Bus Signals
Following is a description of the signals on the expansion bus.
BUFF 0 0
(Output) OSC signal divided by 14
(1.023 MHz).
WRITEREADGATE
(Output) Active low strobe for all
devices. AS16 through AS255
strobes can be created by decoding
DVO through DV7 and using the
signal, WRITEREADGATE.
BUFFREAD
(Output) When high, indicates a
read is occurring. When low,
indicates a write is occurring.
BUFFREAD
(Output) Inverse of BUFFREAD.
BUFFRES
(Output) inverse of RESET DRV.
Performs system reset and
initialization.
(Input) External, interrupt request.
Active low.
ASO to AS15
66
(Outputs) Active low strobes for
devices 0 through 15. Must be low
for 0.4 microseconds.
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Word number bit 3, fixed high.
WD3
Word number bit 3, grounded.
HA4 - HA7
Reserved expansion signals; grounded.
DVO - DV7
(Output) Device-number bits. Select one
of 256 possible devices.
LDO - LD7
(Inputs/Outputs) Low byte of the
adapter's 16-bit data bus.
HDO - HD7
(Inputs/Outputs) High byte of the
adapter's 16-bit data bus.
WDO - WD2
Word number bits 0 through 2 (system-bus
address lines A12 through A14 are buffered
and renamed WDO through WD2).
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
67
Following is a diagram of the expansion bus read timing.
Word Register
Selection
(WDO-WD3)
-
O.llls
Strobes:
(WR ITE R EADGATE)
(ASO-AS15)
Adapter's 16-Bit
Data Bus
(LDO-LD7)
(HDO-HD7)
Valid
BUFFREAD
BUFFREAD
Following is a diagram of the expansion bus write timing.
0.5 J.lS
Word Register
Selection
(WDO-WD3)
Strobes:
(WRITEREADGATE)
(ASO-AS15)
-
Adapter's 16-Bit
Data Bus
(LDO-LD7)
(HDO-HD7)
•
0.1 IlS
Valid
BUFFREAD
BUFFREAD
68
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Programming Considerations
This section describes the programming considerations for the
Data Acquisition Adapter.
Address Decoding
The following table shows address decoding.
A9 AS A7 A6 A5 A4 A3 A2 A1
101
1
1
a a a
1
•
Register Select selects one of 16 word registers (0 through
15). Only registers 0 through 13 are used.
•
Card Select selects the adapter number (0 through 3).
•
Al through A9 are a fixed pattern to select Data Acquisition
Adapters.
•
AO selects the high or low byte of a 16-bit word register.
The base addresses of the Data Acquisition adapters are:
AdaDter Number
Base Address (Hex)
0
02E2
1
06E2
2
OAE2
3
OEE2
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
69
Registers
Each Data Acquisition Adapter has 16 (two-byte) word registers
through which all access to the Data Acquisition Adapter is made.
The registers allow access to the Data Acquisition Adapter's
on-board and expansion data-acquisition and control devices, the
adapter's interrupt registers and device number register, and the
timer / counter device registers.
The following table shows the Data Acquisition Adapter's
registers.
Register
0
1
2
3
4
5
6
7
8
9
10
11
70
Name
Device
Device
Device
Device
Device
Device
Device
Device
Register
Register
Register
Register
Register
Register
Register
Register
Function
0
1
2
3
4
5
6
7
Timer/Counter 0
Register
Timer / Counter 1
Register
Timer / Counter 2
Register
Timer / counter
Control
Register
Write values to, and read
values from, the on-board
and external devices
Read/load Counter 0
Read/load Counter 1
Read/load Counter 2
Controls the operation
of Counters 0 through 2.
12
Device Number
Selects device
13
Interrupt Reqisters
Interrupt control and status
14
Not used
15
Not used
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Device Registers
Eight register addresses have been reserved for reading and
writing the registers on the on-board and external devices. The
device is selected using the device-number register. These
registers may then be used for access to the registers of that
device. These registers are both read and write registers, and
often two different functions will be decoded for the read and
write.
Analog Input Device Registers
The on-board analog input (AI) device, accessed as device
number 9, has four channels. External AI devices can be added
to the expansion interface. These external AI devices have up to
256 channels, use ADCs with up to 16 bits of resolution, and are
accessed with a different device number, but with the same
register format as the on-board AI device.
The AI device has the following registers.
Register
Read/Write
Name
Function
0
Write
AI Control
Sets up and
controls the
register.
0
Read
AI Status
Returns status of
the hardware.
2
Read
AI Data
Returns current
analog value.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
71
Following is a description of the bits of the AI control register.
Name
Convert Start
1
Short Cycle
Reserved for enabling a
short cycle conversion.
2
EOCINT Enable
End-of-conversion
interrupt enable. When
set, an end-of-conversion
(conversion complete) will
generate an interrupt.
3-7
8-15
72
Function
0
Bit
Setting this bit starts an
analog-to-digital
conversion.
Not used
Channel
Data Acquisition Adapter
Channels 0 through 255.
On-board AI device uses
only channels 0 through 3.
August 15, 1984
© Copyright IBM Corporation 1984
Following is a description of the bits of the AI status register.
Bit
Name
Function
0
Busy State
When set, indicates that
the ADC is in the process
of doing a conversion and
data is not yet valid.
1
Int State
When set, indicates that a
conversion has ended (not
busy and interrupting
state). If the EOCINT
enable bit is set (enabled),
an interrupt is generated.
2
EOCINT Enable
Read back of state of
EOCINT enable bit in AI
control register.
3 - 15
Not used
Following is a description of the bits of the AI data register.
Bit
Name
Function
0-15
Data
Contains the data value from
the last conversion. Valid
only if the busy bit in the AI
status register is cleared. Bits
o through 11 will contain data
from the 12-bit ADC. Bits 12
through 15 will all be zeros.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
73
AI Device Access Strategy
The following outlines the access strategy for the AI device. Note
that because channel selection takes a while, routines that
repeatedly access a single channel would want to select the
channel only once before data acquisition.
Polling Method
To use the polling method, do the following:
1.
Set the device number in the device-number register to 9.
2.
Set the channel and simultaneously disable conversion by
setting the convert start bit to O.
3.
Wait for the channel multiplexer to settle (approximately 20
microseconds) .
4.
Request a conversion by setting the convert start bit to 1 and
set the same channel.
5.
Wait for the busy stat bit to equal O.
6.
Enable reading of the ADC's data by setting the convert start
bit to 0, and set the same channel.
7.
Read the data value.
74
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Interruption Method
To use the interruption method, do the following:
1.
Set the device number in the device-number register to 9.
2.
Set the channel and simultaneously disable conversion by
setting the convert start bit to O.
3.
Wait for the channel multiplexer to settle (approximately 20
microseconds) .
4.
Request a conversion by setting the convert start bit to 1,
and set the same channel.
5.
Set the EOCINT enable bit to 1 to enable an
end-of -conversion interrupt.
6.
After servicing the interrupt, set the EOCINT enable bit to 0
to disable AI interrupts.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
75
Analog Output Device
The analog output (AO) device has two channels, uses 12-bit
DACs, and is accessed as device number 9.
External AO devices can be added to the expansion interface.
These devices have up to 256 channels, use DACs with up to
16-bit resolution, and are accessed with a different device
number, but use the same register format as the analog output
device.
The AO device has the following registers.
Register
1
Read/Write
Write
3
Write
Name
AO Control
AO Data
Function
Sets up and
controls the
register.
Output value.
Following is a description of the bits of the AO control register.
Bit
0-7
8-15
Name
Function
Not used
Selects channel 0 through
255. On-board AO device
uses channels 0 and 1.
Channel
Following is a description of the bits of the AO data register.
Bit
0-15
76
Name
Function
Data
The value to be
provided to the
selected channel.
Sets bits 0 through 11
with data for the
12-bit DACs, and bits
12 through 15 with
zeros.
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
AO Device Access Strategy
To use the AO device access strategy, do the following:
1.
Set the device number to 9 in the device-number register.
2.
Set the channel in the AO control register.
3.
Write the data value to the AO data register.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
77
Binary Input/Output Device
This on-board device, which is accessed as device number 8, is a
parallel binary (TTL) I/O device. It has one 16-bit output port,
one 16-bit input port, and support for handshaking lines.
Binary I/O expansion devices can be attached to the expansion
interface. These devices are accessed with a different device
number, but use the same register format as the binary I/O
device.
The binary I/O device has the following registers.
Reg.
Read/Write
0
Read
Binary Status
The current state of the
handshaking input lines.
0
Write
Binary Control
Controls the state of the
handshakinQ output lines.
2
Read
Binary Input
Data register for binary input
port.
2
Write
Binary Output
Data register for binary output
port.
78
Name
Data Acquisition Adapter
Function
August 15, 1984
© Copyright IBM Corporation 1984
Following is a description of the bits of the binary status register.
Bit
0
Name
BI Strobe
1
2
BO CTS
3
4-15
Function
I ndicates the state of the
binary input port's 'BI strobe'
input handshaking line.
Reserved
Indicates the state of the
binary output port's 'clear to
send' (BO CTS) input
handshaking line.
Reserved
Not used
Following is a description of the bits of the binary control
register.
Bit
0
Name
BO Strobe
1
2
BICTS
3-4
5-15
August 15, 1984
© Copyright IBM Corporation 1984
Function
This bit sets and clears the
binary output port's 'BO
strobe' output handshaking
line.
Reserved
This bit sets and clears the
binary input port's 'clear to
send' (BI CTS) output
handshaking line.
Reserved
Not used
Data Acquisition Adapter
79
Following is a description of the bits of the binary input register.
Bit
0-15
Function
Name
Data
The current value at the
binary input port can be read
from this register. The value
contained is not latched
(unless 'BI hold' was used).
Following is a description of the bits of the binary output register.
Bit
0-15
80
Name
Function
Data
The value to be placed on the
binary output port is written
here. Data lines of the port
are affected as soon as the
register is written.
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Binary Input Access Strategies
To use binary input with handshaking, do the following:
1.
Set the device number to 8 in the device-number register.
2.
Set HI CTS high in the binary control register.
The external device puts new data on the binary input lines
(BIO through BI15) at the distribution panel connector.
The data on the input lines must remain valid until HI CTS is
lowered.
The external device sets 'HI strobe' high.
3.
Read data from the binary input register.
4.
Reset BI CTS in the binary control register.
The external device lowers 'BI strobe.'
Following is a diagram showing binary input with handshaking.
BI CTS
Output
CLEAR TO SEND
,<---________
STROBE
BI
STROBE _In_p_u_t_ _ _ _ _ _ _---'
To use binary input without handshaking, do the following:
1.
Set the device number to 8 in the device-number register.
2.
Read the data value from the binary input register.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
81
Binary Output Access Strategies
To use binary output with handshaking, do the following:
1.
Set the device number to 8 in the device-number register.
The external device lets BO CTS go high on the distribution
panel connector. This is detected by reading the binary
status register's BO CTS bit.
2.
Write the new data value to the binary output register.
3.
Set the binary control register's 'BO strobe' bit.
4.
Reset the 'BO strobe' bit in the binary control register.
The external device releases BO CTS.
The following diagram shows binary output with handshaking.
BO CTS
_In_pu_t_ _...J
Outputs
CLEAR TO SEND
Old data
New data
BOO-B015~
~"""""":0~~~/,,~r-r-~~--r-T~--"---'~~:0r-r-;///~
STROBE
~~ROBEO__ut_p_u_t_ _ _ _ _ _----'1
L I_ _ _ _ _ _ _ _ _
To use binary output without handshaking, do the following:
1.
Set the device number to 8 in the device-number register.
2.
Write the data value to the binary output register.
82
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Timer / Counter Device Registers
This section describes the timer/counter's control register,
loading of the counters, its write operations, programming format,
and read operations.
The timer/counter device has the following registers.
Reg.
Read/Write
Name
8
Read/Write
Timer / Counter 0
Register
Read/load Counter 0
9
Read/Write
Timer / Counter 1
Register
Read/load Counter 1
10
Read/Write
Timer / Counter 2
Register
Read/load Counter 2
11
Write
Timer / counter
Control Register
Controls the operation
of Counters 0 through
2.
Function
Control Register
The timer/counter's control register controls the operating mode
of each counter, selection of binary or binary coded decimal
(BCD) counting, and how each counter register is loaded. The
control register can only be written to; no read operation of its
contents is available.
The table on the following page shows control-word information
for the timer/counter's control register.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
83
Control Word Format
Definitions of Control
SC - Select Counter:
SC1
SCO
DescriDtion
0
0
1
Select Counter 0
Select Counter 1
0
1
Select Counter 2
0
1
1
lIIeQal
RL - Read/Load:
RL1
RLO
0
1
0
Counter latchinQ operation
0
Read/load most significant byte (MSB)
onlv.
0
1
1
1
Read/load least significant byte (LSB)
onlv.
Read/load LSB first, then the MSB.
Description
M - MODE:
M2
M1
MO
Description
0
0
X
0
0
1
0
1
ModeO
Mode 1
1
0
1
Mode 2
X
1
0
0
Mode 3
Mode 4
1
0
1
Mode 5
BCD - Binary Coded Decimal:
84
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Counter Loading
A count register is not loaded until the count value is written (one
or two bytes, depending on the mode selected by the RL bits) and
followed by a rising edge and a falling edge of the clock. Any
reading of the counter before that falling clock edge may yield
invalid data.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
85
Timer/Counter Write Operations
Each counter of the timer/counter must be programmed with the
mode and quantity desired. The programmer must write to the
timer/counter's control register, a control word containing mode
information and the programmed number of count register bytes
(1 or 2) before actually using the selected counter.
Writing the control word can be in any sequence of counter
selection (Counter 0 does not have to be first or Counter 2 last).
Each counter's control word has a separate address so that its
loading is completely independent of sequence. However, the
loading of the count register with the actual count value must be
done in the exact sequence programmed in the control word (RLO
and RLl). This loading, like that of the control word, is still
sequence-independent, but when a selected count register is
loaded, it must be done with the number of bytes programmed in
the control word. The one or two bytes, loaded in the count
register, do not have to immediately follow the associated control
word, they can be programmed at any time after the control word
is loaded, as long as the correct number of bytes is loaded in
order.
All counters are down counters. Thus, the value loaded into the
count register will actually be decreased. Loading all zeroes into
a count register results in the maximum count (2 to the 16th for
binary, or 10 to the 4th for BCD). In mode 0, the new count
does not restart until loading is complete. The count register will
accept one or two bytes, depending on how the mode control
words (RLO and RL 1) are programmed. Then the restart
operation proceeds.
86
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Timer/Counter Programming Format
The programming format shown below is a simple example of
timer / counter loading and does not imply that it is the only
format that can be used.
Programming Format:
MODE
Control Word Counter n
LSB
Count Register Byte Counter n
MSB
Count Register Byte Counter n
Alternate Programming Format:
Number
Byte
Description
Reg.
1
MODE
Control Word
Counter 0
8
2
MODE
Control Word
Counter 1
8
3
MODE
Control Word
Counter 2
8
4
LSB
Count Register Byte
Counter 1
9
5
MSB
Count Register Byte
Counter 1
9
6
LSB
Count Register Byte
Counter 2
10
7
MSB
Count Register Byte
Counter 2
10
8
LSB
Count Register Byte
Counter 0
11
9
MSB
Count Register Byte
Counter 0
11
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
87
Timer/Counter Read Operations
In most counter applications, it becomes necessary to read the
value of the count in progress and make a computational decision
based on this quantity. Event counters are probably the most
common applications that use this function. The timer/counter
has logic that allows the programmer to easily read the contents
of any of the three counters without disturbing the actual count in
progress.
The programmer can use two methods to read the value of the
counters. The first method involves the use of simple I/O read
operations of the selected counter. The only requirement of this
method is that the actual operation of the selected counter must
be inhibited by external logic that inhibits the clock input (only
valid for Counter 2, because its 'clock in' signal is brought to the
distribution panel connector). This requirement ensures a stable
count reading.
The contents of the selected counter are as follows:
•
The first I/O Read contains the least-significant byte.
•
The second I/O Read contains the most-significant byte.
Because of the timer/counter's internal logic, the entire reading
procedure must be finished. If two bytes are programmed to be
read, then the two bytes must be read before any loading-write
(WR) commands can be sent to the same counter.
The following chart has information about the read operation.
88
Reg.
DescriPtion
8
9
Read Counter 0
10
Read Counter 2
Data Acquisition Adapter
Read Counter 1
August 15, 1984
© Copyright IBM Corporation 1984
The second method of reading the value of the counters involves
reading while counting.
To allow the programmer to read the contents of any counter
without affecting the counting operation, special internal logic of
the timer/counter can be accessed with simple write commands to
the mode register. When the programmer wishes to read the
contents of a selected counter, he loads the mode register with a
special code that latches the present count value into a storage
register so that its contents have an accurate, stable quantity. The
programmer then issues a normal Read command to the selected
counter, and the contents of the latched register are available.
The second method of reading the counters has the same
limitation as the first method described. That is, the entire read
operation must be finished as programmed. The Read command
has no effect on the counter's mode.
The following table shows the control word used for latching
count. This control word is written to the timer/counter's control
register.
07
SC1
I 06 I 05 I 04 I 03 I 02 I 01
I sco I a I a I x I x I x
I 00
I x
Note:
SC1, SCO - specify counter to be latched
05, 04 - 00 designates counter latching operation
X - don't care
August 15,1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
89
Device Number Register
The device-number register selects the device to be accessed.
Only the low-order byte should be written.
The on-board devices are:
•
Analog I/O device (device number 9)
•
Binary I/O device (device number 8)
The following table describes the bits of the device-number
register.
Bit
0-7
Name
Device Number
8-15
90
Data Acquisition Adapter
Function
Selects which device to
address (0-255)
Not used
August 15, 1984
© Copyright IBM Corporation 1984
Interrupt Registers
Two registers are decoded for register 13, the interrupt control
register and the interrupt status register. The interrupt control
register may be written to for setting up the Data Acquisition
Adapter for various interrupts. The interrupt status register may
be read for information about the Data Acquisition Adapter's
current interrupt status.
The following is a description of the bits of the interrupt control
register.
Bit
Name
Function
0
TINT Enable
Enables the timer-generated
interrupts.
1
CINT Enable
Enables counter-generated
interrupts.
2
IRQ Enable
Enables the external I RQ line to
generate an interrupt. It also
enables AI end-of-conversion
interrupts. To enable EOC
interrupt, both this bit and the
EOCINT enable bit in the AI
control register must be set.
3
Reserved. Must be cleared.
4-6
7
Not used. Must be cleared.
LINT Reset
August 15,1984
© Copyright IBM Corporation 1984
Local Interrupt Reset; re-enables
the interrupt circuitry of the
addressed Data Acquisition
Adapter.
Data Acquisition Adapter
91
The following is a description of the bits of the interrupt status
register.
Note: The bits of the interrupt status register contain the
current state of the devices that generate an interrupt. They
are not latched, and they are not reset by reading them.
Bit
0-3
Read back of the current state of
bits 0 through 3 in the interrupt
control register.
4
TINT STAT
Timer Interrupt Status; if this bit
is set, a timer-generated
interrupt has occurred.
5
CINT STAT
Counter Interrupt Status; if this
bit is set, a counter- generated
interrupt has occurred.
6
IRQ STAT
IRQ Status; if this bit is set, the
IRQ line generated an interrupt.
7
92
Function
Name
TINT Enable
CINT Enable
IRQ Enable
Data Acquisition Adapter
Reserved
August 15, 1984
© Copyright IBM Corporation 1984
Interface
Following is information about the Data Acquisition Adapter's
connectors, J4 (distribution panel), and J1 and J2 (expansion
bus),
Distribution Panel Connector
The following shows the location of the distribution panel
connector (J 4 ),
59
August 15, 1984
© Copyright IBM Corporation 1984
60
Data Acquisition Adapter
93
The following shows the pins of the distribution panel connector
and their respective signals.
Sianal Name/Descriotion
Pin
DIA 1
DIAO
+10VREF
1
3
AGND
4
2
AID 0-
5
A/DO+
AID 1-
6
7
A/D1+
8
AID 2-
9
10
11
Data
External
AID 2+
AID 3AID 3+
12
Acquisition
Device
AGND
13
Adapter
AID CE
D GND
14
AID CO
SI8
16
SO 8
18
94
15
17
SI9
19
SO 9
SI 10
20
SO 10
22
SI 11
23
SO 11
24
SI12
25
21
SO 12
26
SI 13
27
SO 13
28
SI14
29
S014
30
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
S·Igna IN ame /0 eSCriptlon
BI15
B015
BI HOLD
BO GATE
BIO
BOO
BI 1
BO 1
BI2
BO 2
BI3
External
Device
BO 3
BI4
BO 4
BI5
p.In
31
32
33
34
35
36
37
38
39
40
Acquisition
43
Adapter
44
45
BO 5
46
BI6
47
BO 6
BI 7
BO 7
48
49
50
RATE OUT
51
DELAY OUT
BI STROBE
BO STROBE
52
53
54
BO CTS
55
BICTS
IRQ
56
57
COUNT OUT
COUNT IN
58
59
D GND
60
August 15, 1984
© Copyright IBM Corporation 1984
Data
41
42
Data Acquisition Adapter
95
Expansion Bus Connectors
Following is information about the expansion bus connectors (J1
and 12).
Expansion Bus Connector Jl
The following shows the location of the expansion bus connector,
J1.
96
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
The following shows the pins of the expansion bus connector, J1,
and their respective signals.
S·Igna IN arne /0 escr~tlon
p.In
BUFF 00
Reserved
1
2
WRITEREADGATE
3
4
BUFFREAD
BUFFRES
5
BUFFREAD
6
7
IRQ
8
Reserved
Reserved
DGND
9
10
11
External
D GND
Device
Reserved
12
13
Reserved
D GND
DGND
Reserved
Reserved
AS7
AS6
AS5
AS4
AS3
15
16
17
18
19
20
21
22
23
24
AS1
ASO
25
26
AS15
AS14
27
AS13
29
30
31
AS9
AS8
August 15,1984
© Copyright IBM Corporation 1984
Adapter
14
AS2
AS12
AS11
AS10
Data
Acquisition
28
32
33
34 ,
Data Acquisition Adapter
97
Expansion Bus Connector J2
The following shows the location of the expansion bus connector,
J2.
98
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
The following shows the pins of the expansion bus connector, 12,
and their respective signals.
S·Igna IN arne /D escnptlon
External
Device
p.In
WD3
1
D GND
2
HA 7 D GND
3
HA 6 D GND
4
HA 5 D GND
5
HA4 D GND
DV 7
6
7
DV6
8
DV 5
9
DV4
10
LD 7
11
Data
LD 6
12
Acquisition
Adapter
LD 5
13
LD 4
14
LD 3
15
16
LD 2
LD 1
17
LD 0
18
HD 7
19
HD 6
20
HD 5
21
HD4
22
HD 3
23
HD 2
24
HD 1
25
HD 0
26
DV 3
27
DV 2
28
DV 1
29
DVO
30
WD 3 D GND
31
WD2
32
WD 1
33
WDO
34
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
99
Notes:
100
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Switch Settings
The Data Acquisition Adapter has five groups of slide-type DIP
switches that control analog output range, analog input range,
adapter number, and interrupt level. Each group of switches is
labeled on the adapter, and each switch is numbered on the
housing. The switch positions (On and Off) also are labeled on
the housing.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
101
Analog Output Range
Following is a description of the switch blocks that control the
Data Acquisition Adapter's analog output range for channels 0
and 1.
Channel 0
Switch block Sl has two switches: Sl-l and Sl-2. These
switches determine the relationship between analog output values
and the voltage output of the analog output device.
S 1-1 controls voltage range:
•
•
On: 10-volt range
Off: 20-volt range
Sl-2 controls voltage polarity:
•
•
102
On: Bipolar (±) voltage
Off: Unipolar (+) voltage
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
The following diagram shows the location and switch settings for
switch block S 1.
Input Range
Switch Settings
-5 to +5 volts
-10 to +10 volts
o to +10 volts
Note: Only the settings shown may be used for this switch
block.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
103
Channell
Switch block S2 has two switches: S2-1 and S2-2. These
switches determine the relationship between analog output values
and the voltage output of the analog output device.
S2-1 controls voltage range:
•
•
On: la-volt range
Off: 20-volt range
S2-2 controls voltage polarity:
•
•
104
On: Bipolar (±) voltage
Off: Unipolar (+) voltage
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
The following diagram shows the location and switch settings for
switch block S2.
Output Range
Switch Settings
-5 to +5 volts
-10 to +10 volts
o to +10 volts
Note: Only the settings shown may be used for this switch
block.
August 15,1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
105
Analog Input Range
Switch block S3 has four switches: S3-1, S3-2, S3-3, and S3-4.
The settings of these switches determine the relationship of
analog input voltage to the values returned by the analog input
device.
S3-1 is not used and is placed in the Off position.
S3-2 controls the 20-volt input range:
•
•
On: 20-volt range active
Off: 20-volt range inactive
S3-3 controls the lO-volt input range.
•
•
On: lO-volt range active
Off: 10-volt range inactive
S3-4 controls voltage polarity.
•
•
106
On: Bipolar (±) voltage
Off: Unipolar (+) voltage
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
The following diagram shows the location and switch settings for
switch block S3.
Output Range
Switch Settings
-5 to +5 volts
-10 to +10 volts
o to +10 volts
Note: Only the settings shown may be used for this switch
block.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
107
Adapter Number
Switch block S4 has two switches: S4-1 and S4-2. These
switches specify the adapter number (0 through 3). Assign a
number to each Data Acquisition Adapter before installation.
Note: Up to four Data Acquisition Adapters may be
installed in your unit. Each adapter must be given a different
adapter number.
Adapter Number
Switch Positions
o
2
3
108
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Interrupt Level
Switch block S5 has two 5-switch switch blocks rather than one
lO-switch switch block. The switches of the right-hand, 5-switch,
switch block, although numbered 1 through 5, are functionally
identical to switches 6 through 10.
These 10 switches determine the interrupt level of each Data
Acquisition Adapter. Set the interrupt level for each adapter
before installation. Data Acquisition Adapters installed in the
same unit must be set to the same interrupt level. The setting for
interrupt request level 7 (IRQ7) is recommended.
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
109
The following diagram shows the location and switch settings for
switch block S5.
IRQ Level
7
(Recommended)
6
5
4
3
Note: Only the settings shown may be used for this switch
block.
110
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Specifications
The following is a description of the Data Acquisition Adapter
specifications and device characteristics.
Data Acquisition Adapter
Following is a description of the Data Acquisition Adapter
specifications.
Dimensions
Height
99.1 mm (3.9 in.)
Height at Tab Pins
106.7 mm (4.2 in.)
Length
335.3 mm (13.2 in.)
Thickness
14.2 mm (0.56 in.)
Weight
270 g (9.5 oz)
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
111
Power Requirements
+ 5 volts ± 5 % at approximately 1 ampere typical (1. 5 ampere
maximum)
System Reference Voltage
Output Voltage
+ 10 volts
Accuracy
±1.2%
Output Load Current
±2 milliamperes maximum
Output Load Capacitance
0.5 microfarads maximum for
stability
Output Protection
Protected for short to common
Output Impedance
2-ohms maximum at
distribution panel connector
112
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Environment
The Data Acquisition Adapter complies with the limits for a Class
B computing device according to Subpart J of Part 13 of FCC
rules and meets German VED requirements when installed in the
host system.
Operating Environment
Temperature Range
Humidity Range
8 % to 80% non-condensing
Altitude
2187 m (7000 ft) maximum
Non-Operating· Environment
Temperature Range
Humidity Range
August 15,1984
© Copyright IBM Corporation 1984
5% to 100% non-condensing
Data Acquisition Adapter
113
Data Acquisition Adapter Devices
Following is a description of the characteristics of the devices on
the Data Acquisition Adapter.
Analog Output Device
The analog output device has the following characteristics:
Resolution
12 bits
Output Channels
2
Output Ranges
Switch-selectable ranges:
o to + 10 volts (unipolar),
-5 to +5 volts (bipolar), and
-10 to + 10 volts (bipolar).
Output Load Current
±5 milliamperes minimum
Output Load Capacitance
for Stability
0.5 microfarads maximum
Digital Coding
Unipolar: binary.
Bipolar: offset binary.
Integral Linearity Error
± 1 least significant bit (LSB)
maximum
Impedance
2-ohms maximum at the
distribution panel connector
Protection
Protected for short to common
114
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Differential Linearity Error
± 1/2 LSB maximum;
guaranteed monotonic
Gain Error
± 0.1 % maximum between
ranges. Any range adjustable
to zero.
Gain Stability
± 35 ppm;o C of full scale
range (FSR) maximum
Unipolar Offset Error
± 3.25 millivolts maximum
Unipolar Offset Stability
±8ppm;oC of FSR
maximum
Bipolar Offset Error
Adjustable to zero
Bipolar Offset Stability
±24 ppm/oC of FSR
maximum
Power Supply Rejection
± 1/2 LSB maximum change
in full scale calibration
Throughput from Memory
25,000 conversions per
second, minimum
Dynamic characteristics for a -10 volt to + 10 volt step with less
than ± 5 milliamperes and less than 1000 picofarads load are:
Overshoot
± 1 % of FSR maximum
Settling Time
10 microseconds maximum to
within ±0.1 % FSR
August 15,1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
115
Analog Input Device
The analog input device has the following characteristics:
Resolution
12 bits
Input Channels
4 differential
Input Ranges
Switch-selectable ranges:
o to + 10 volts (unipolar),
-5 to +5 volts (bipolar), and
-10 to + 10 volts (bipolar).
Input Resistance
100 megohms minimum
Input Capacitance
200 picofarads maximum; measured
at the distribution panel connector
Input Leakage Current
±300 nanoamperes maximum
Input Current
± 4 milliamperes at maximum input
voltage
Digital Coding
Unipolar: binary.
Bipolar: offset binary.
Safe Input Voltage
± 30 volts maximum (power On or
Off)
Power Supply Rejection
± 1/2 LSB maximum change full
scale calibration
Integral Linearity Error
± 1 LSB maximum
116
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Differential Linearity Error
± 1/2 LSB maximum
Differential Linearity Stability
±5 ppm;o C maximum;
guaranteed monotonic
Gain Error
±O.l % maximum between
ranges. Any range adjustable
to zero.
Gain Stability
±32 ppm/oC of FSR
maximum
Common-Mode Input Range
± 11 volts maximum
Common-Mode Rejection
72 dB minimum ratio (signal
within common-mode range)
Unipolar Offset Error
Adjustable to zero
Unipolar Offset Stability
±24 ppm/oC of FSR
maximum
Bipolar Offset Error
Adjustable to zero
Bipolar Offset Stability
±24 ppm/oC of FSR
maximum
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
117
Settling Time
For channel acquisition: 20
microseconds maximum to ±0.1 %
of the input value
Conversion Time
35 microseconds maximum
Throughput to Memory
15,000 conversions per second,
minimum
'AID convert enable'
Input Impedance
One LS TTL load plus lO-kilohm
pull-up resistor
'AID convert out'
Fanout
118
10 LS TTL loads or 2 standard
TTL loads
Data Acquisition Adapter
August 15,1984
© Copyright IBM Corporation 1984
Binary Device
The binary device has the following characteristics:
Binary Input (BIO through BIl5)
Input Impedance
One LS TTL load plus 10-kilohm
pull-up resistor
Throughput to memory
25,000 operations per second,
minimum
BIHOLD
Input Impedance
Two LS TTL loads plus one
10-kilohm pull-up resistor
'BI Strobe'
Input Impedance
One LS TTL load plus one
lO-kilohm pull-up resistor
BIeTS
Fanout
August 15, 1984
© Copyright IBM Corporation 1984
10 LS TTL loads or 2 standard
TTL loads
Data Acquisition Adapter
119
Binary Output (BOO through B015)
Fanout
28 LS TTL loads or 7 standard
TTL loads
Throughput from Memory
25,000 operations per second,
minimum
'BO Gate'
Input Impedance
Two LS TTL loads plus one
lO-kilohm pull-up resistor
BoeTS
Input Impedance
One LS TTL load plus
10-kilohm pull-up resistor
'BO Strobe'
Fanout
120
Data Acquisition Adapter
10 LS TTL loads or 2 standard
TTL loads
August 15, 1984
© Copyright IBM Corporation 1984
32-Bit Timer Device
The 32-bit timer device has the following characteristics:
Counter 0
CLK 0 Frequency
1.023 MHz
'Rate Out'
Fanout
10 LS TTL loads or 2 standard TTL loads
Counter 1
'Delay Out'
Fanout
10 LS TTL loads or 2 standard TTL loads
August 15, 1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter
121
16-Bit Timer/Counter Device
The 16-bit timer/counter device has the following characteristics:
'Count In'
Input Impedance
One LS TTL load plus la-kilohm pull-up
resistor
Input Frequency
DC - 2 MHz (50% duty cycle)
'Count Out'
Fanout
122
10 LS TTL loads or 2 standard TTL loads
Data Acquisition Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Logic Diagrams
SHT 7
I
I
l
l
I
I
A9
DO
D1
I
1/0
A30
SLOT
D2
D3
D4
D5
~
SHT 7
A31
J3
A8
D7
A7
A29
A6
A28
A5
A27
A4
A26
A3
A25
A2
A24
A23
A22
SHT16
I
I
I
I
1I
SHT16
IRQ3
IRQ4
IRQ 5
IRQ 6
IRQ 7
825
A21
824
A20
823
A19
822
A18
821
A17
A11
813
B14
NOTES:
820
1. Resisto rs are 5%, 1/4W carbon
film un less otherwise noted
830
I
A1
A2
A3
A4
A5
I
I
A8
I
A9
I
A10
A11
A12
A14
A15
signals
~
B1
Other
signals
ru
89
SHT 4
J
I
I
I
SHT 4
I
I
SHT 3
SHT 3
SHT 3
SHT 5
AEN
J
SHT 4
lOW
I
SHT 3
lOR
I
SHT 3
CLOCK
J
I
SHT 8
+5V
I
SHT 2
GND
I
SHT 2
-12
I
SHT 2
+12
I
SHT 2
82
RESET DRV
I/O SIotJ3
August 15, 1984
© Copyright IBM Corporation 1984
SHT16
OSC
831
87
SHT 3
J
I
I
I
A7
83
Connector
I
I
A6
A13
A16
2. Symbo Is used:
AO
J
SHT 3
Sheet 1
Data Acquisition Adapter
123
NOTE, R3, R5, R6 ARE NOT INSTALLED,
SHT 1
SHT 1
:: :
SHT 1 + 12
J3-B3
p----s,~'.--
1 J3-B9
~---"~'~"'-"o"n
R5
SHT 1 - 12 1
J3-87
~---V./.r"0"\2
L1
L1
+5
15
SHT 1
+5
SHT 1
+5
RESERVED
SHT18A
RESERVED
SHT 18A
"O"[l
J3-B29
U1
POWER
GEN
408
J1-13
J1-14
R8
3,3[l
13
J1-9
J1-10
¢
+15
SHT 13A, 138
-15
SHT 13A, 138
C4
15!-,F
R9
DC to DC
SHT 17
Converter
SHT 18A
SHT 18A
SHT 18A
SHT18A
SHT 17
.....- - - D G N D
SHT 17
SHT 17
A GND
Power Supplies and Grounds
124
Data Acquisition Adapter
SHT 13A, 138, 14, 15, 17
Sheet 2
August 15, 1984
© Copyright IBM Corporation 1984
SHT 1
iOR
SHT1
lOW
SHT5
74LS244
SHT 5
SHT 3
SHT 18A
SHT 5, 7, 9, 12,18A
SHT 1 AO
SHT 4, 5
74 LS240
SHT 1 RESET ORV
8UFFRES SHT 4, 16, l8A
19
SHT 1 A12
WD 0 SHT 9,12, 18B
SHT 1 A13
WD 1 SHT 9, 12, 18B
7
~
70LS2';
U18
~_
~WD3
SHT188
19
SHT 1 A14
WD2 SHT9, 12,188
System Bus Control and Address Lines
August 15, 1984
© Copyright IBM Corporation 1984
Sheet 3
Data Acquisition Adapter
12S
+5V
O
~
rl11~6____-(=:~~
A9
) SHT 1
13
~
U50
74LS688
p
Q
Address
~;:--G:~:~ll
A5
Preselection
r9~----C=~A~3~~SHT1
r~~,-~ ~ ~_~·~_- ~1_2~7:~~1~1----~P=r.~~9~~
______ ___ ___-_____
SHT 1 AEN
I
J3-A11
r. +5V
n'
10K
RN11
PRESEL
I ---IL~------'~+5V
~
7
6
5~ 2~
J
20
9
SHT3~------~~-+-r-r1-+---~
SHT1 (
A11
SHT1(
A10
14
U22
PAL1
16H2
19
ADSW1
ADSW2
15
INSW1
Address
Decode
INTCLR) SHT 16
INSW3
OUT
INSW5
INSW7
SHT 1 (
A4
SHT 1 (
A2
SHT 1 (
A1
SHT 3 (
BAO
18
17
12
16
11
SHT 3 (BUFFRES
Address Decode
126
Data Acquisition Adapter
CARDSEL SHT 5
Sheet 4
August 15,1984
© Copyright IBM Corporation 1984
@>
o~
o(JQ
'"O~
«00
':!. t"""t"
DBUFFSTIl) SHT 7
'l}-VI
WHBD
ii3~
:::'\D
) SHT7
WDEVICE) SHT6
SHT3 (
BIDW
SHT3 (
BIOR
000
5;.j::;.
'"0
0
..,
"'g.
-...
:;
'.0
00
0
~
.....
SHT 4
(cARDsEL
6
SHTl
(
3
.c
5.
~.
.....
S·
=
:>
A15
SHT 3
(
WD2
SHT 3
(
WDl
SHT 3 (
SHT 3
~
:>
rl
13 .----12 JU20'
SHT 3
(
(
SHT3 (
WDO
BlOW
BAD
'::
SHT 3 (BUFFREAD
'C
.....
...
....
9
14
5
12
1
16
iNfSTli
17
CNTSTB
19
ISSTB
2
BIOR
10
13
r--
4
Control
8
Decode
IN
OUT
11
15
7
r--!!-
~
~
.----! U2
8
-V
JU20
1
1
74lS32
3
74lS32
5
.--
4
JUlY.
~
9
10
J U17
6
WlNTCONf) SHT 16
RINTSTATIlS) SHT 16
WCNT ) SHT8
RCNT ) SHT8
74lS32
8
WlBO ) SHT,7
74lS32
12
110
13
J U17
11
74lS32
--
~
-.J
2
1
74lS32
~
Q.
~
U21
PAl2
1018
11
-
RlBI
J SHT7
RHBI
)
SHT7
WHRlSTB) SHT6
Control Decode
Sheet 5
DVO
J2·30
SHT 18B
J2-29
SHT 188
J2-28
SHT 188
J2-27
SHT 18B
Jl-26
SHT 18A
DV1
DV2
SHT 5
DV3
1
ASO
2
AS1
C
3
AS2
D
4
AS3
19
5
AS4
15
6
AS5
23 A
K
SHT7
SHT 7
SHT 7
SHT 7
Q
16
22 B
21
12
20
U40
74LS374
Device
Number
Register
U39
74154
Jl-25
Jl-24
Jl-23
Jl-22
Jl-21
SHT 7
SHT 7
SHT 7
7
AS6
Device
Select
8
AS7
Strobe
Decoder
9
AS8
10
AS9
11
AS10
Jl-20
13 AS11
14 Ai,,12
15~
74LS02
SHT 18B
16 AS14
Gi
SHT 18B
17 AS15
G2
SHT 188
Jl-19
SHT 18A
J'-34
SHT 9, l8A
Jl-33
SHT 12, l8A
Jl-32
SHT 18A
Jl-31
Jl-30
J1-29
Jl-28
Jl-27
I
SHT 18A
SHT 5
Device Selection
128
Data Acquisition Adapter
Sheet 6
August 15, 1984
© Copyright IBM Corporation 1984
~
SHT5
SHT5
RlBI
1
1
SHT 10,l1,13B,14.15
SHT 1
DO
BOO
01
9
2G
1G
UJJ
74lS244
02
OJ
D4
line
ReceIVer
OS
OS
SHT1
07
SHT5
SHTJ
UJ2
74lS374
SHT 10,11,138,14,15
SHT 10,11,138
low Bvte
Write
Register
1B
J
K
G
I
SHT 10,11,138
11
SHT6.8,16
SHT5
SHT 5
~
~
J
I
SHT 6,8,16
Data Bus Conversion
Sheet 7
BUFF 0 0 SHT 18A
1,19
RATE
OUT
SHT 17
74LS04
.,
"
24
GATE 0
14
13
16
10
U46
74LS74
U49
Qf"---------------,
D 74LS163
SHT 1
15
os
21
GATE 1
GATE 2
QUTO
elK 1
11
14MHZ
elK 0
OSC
U26
8253-5
18
eLK 2
TtMER
COUNTER
17
SHT 17
COUNT
IN
OUT 2
J4·59
AO
13
OUT 1
RD
WR
SHT 16
J4·52
DELAY
OUT
SHT 17
SHT 16
COUNT
J4·58
Timer/Counter Device
OUT
SHT 17
Sheet 8
SHT 3
c
WDO
)----2-
SHT 3
(
WD1
~B
SHT 3
~UFFREA~
SHT 6
(
ASS
~
+5~
SHT 3
(
WD2
)---2-
A
C
V6 9
RD BI VALUE) SHT 10
Y2 13
WR 80 VALUE) SHT 11
U24
74lS138
G2A
VO
\9
1,
elK
ClR
15 WR BIN CONT
G1
G2B
Y4
~BINSTATUS
4
-D
o~
J4-54
I BO STROBE
o~
J4-56
I BI CTS
SHT 17
U25
74lS175
~D
""" '"' t
SH T17
+5
SHT17
BI STROBE
I
l1
G1
10 4
J4-53
+5
5
lDO
) SHT 7
lD2
SHT 7
U11
74lS367
RN9 10K
SHT 17
BO
CTsl
J4-55
10 6
7
Binary I/O Device Control Decode
August 15,1984
© Copyright IBM Corporation 1984
Sheet 9
Data Acquisition Adapter
131
RN10 10K
+5 ~ 1
~
SHT17
I
Bll
I
BI2 I
BIO
I
J4-45
BI6
SHT 17
BI7
7
6
4
5
2
J4-37
J4-41
BI5
8
33
2
18
19
4
J4-39
I
BI4
I
BI3
9
J4-35
(
5
U38
74lS373
17
7
J4-43
lDO
16
Q
D
6
)
lDl
)
lD2
)
lD3
)
SHT7
lD4
Binary
14
I
L J4-49
J4-47
15
Input
Register
8
9
K
+5
)
lD6
12
13
lD5
G
)
SHT7
HDO
)
SHT 7
HDl
)
HD2
)
HD3
)
lD7
1
11
RN7
10K
SHT 17
BI HO
lOl
10
J4-33
SHT 9 ~RD BI VALUE
+5 ~1
RN7
10K
SHT17 BI8
J4-17
I
J4-19
Bll0
I
J4-21
BI12~
I
I
I
BI14
I
BI15
I
BI13
8
6
7
5
4
2
K
3 3
G
2
19
U36
74lS373
4
5
16
17
J4-23
7
J4-25
D
Q
Binary
Input
14
J4-27
Register
J4-29
J4-31
Data Acquisition Adapter
6
HD4
15
HD5
8
9
13
12
Binary Input Device
132
1
11
9
18
BI9
Bill
SHT 17
I
<
HD6
)
HD7
)
SHT7
Sheet 10
August 15,1984
© Copyright IBM Corporation 1984
RN9 10K
RNa 10K
+5
SHT 7
1- +5
1
8 9 7 6 4 5 3 2 3
LOO
LOl
U37
74LS374
0
7
L04
Q
L07
15
8
9
12
I B02
I B03
J4·44
I B04
I B05
J4-48
I B06
I 807
SHT 17
SHT17
1
BO VALU
10
74LS04
J4-34
9
U27
8
'()
RN6 10K
AN5 10K
1
1
HOO
B 9 7 6 4 5 3 23
K
G
U35
4
~
~
~
2
2 3
L
~
~
8
13
7~
© Copyright IBM Corporation 1984
I 808
J4-20
I
J4-2~~
J4-24
a
0
Binary
Output
Register
6
15
9
12
Binary Output Device
August 15,1984
J4-18
16
17
14
7 9 B
5
74LS374
7
5 4 6
19
18
~
+5
1
11
SHT
J4-40
J4-50
+5 ,-.,
SHT 7
I BOO
I BOl
J4·42
J4-46
G
K
+:1 RN5
10K
~~TE I
6
13
11
SHT 17
J4-36
J4·38
5
Output
Register
14
L06
~R
7 9 8
Binary
L05
SHT 9
5 4 6
16
17
L03
2 3
19
4
L02
SHT 7
2
18
8010
I BOll
~
J4-28
SHT 17
B09
8012
I 8013
~ 8014
J4-32
I 8015
SHT 17
Sheet 11
Data Acquisition Adapter
133
AID CHAN SEL 0
SHT13B0IDBUSY}-~~~~~~-r-+----------~~-------------------------------'
SHT 13A
AID CHAN SEL 1
74LS175
A/DCE
READ/CONV
AID CO
SHT3
SHT 3
SHT 136
74LS138
U"
Y,fC-'-------,
SHT 3
Y3
G2B
J4-16
SHT 17
A!D INT
SHT 16
74LSOO
12
4
U28
Y6
SHT7
74LS367
3
LDO
SHT 7
SHT 7
LDJ
WR D/A CONT
SHT 14
WR D/A VALU
RD A/D VALUE
Analog 1/0 Device Control
Sheet 12
-15 O-+'-~-'~-+++-'---'r--,
RN4
SHT17
A/DOVIN
SHT 138
A/DO+
A!D2A/D2+
A!D3-
SHT17 A/D3+
R16
820K
SHT 12
SHT 12
SHT
(AID
CHAN SEL 0
)}-----~--------------"
2
A/DCOMM
MODE REJ.
AID CHAN SEL 1
13BG~}-------
Analog Input Device Channel Multiplexer
and Sample and Hold
Sheet 13A
r-----------------------------------------------------~A/DBUSY
136
Data Acquisition Adapter
SHT13A
August 15, 1984
© Copyright IBM Corporation 1984
SHT7
SHT7
~~~~£r----~==================+--1______________________________________________________,
~50 ().--_-4IIf-_~
SHT 7
INT +10 REF
17
WR
D
lVOO
18
+5
U6
74LS74
Ul.
74LSl38
DGND 3
CS
D/A 0 WR STROBE
0
16
U'
Gl
AD7545K
VREF
"
1 14 RN1,
G2.
50Of2
D/AOGAIN
R18
lK
2OK"
Rl0
820K
20K"
3 RN112
D/A 0 OUT
SHT 17
20K"
12 Bit
Buffered
20
DAC
SHT 7
R13
R,.
220il
1
OUT1
SHT7
RNl
20K"
Cll
R7
47H
11
47pf
5 RN110
20K·
A GND
WR D/AVALUE
Analog Output Device
DAC for Channel 0
Sheet 14
SHT 13B INT +10 REF
R21
15
"
13
12
D/A10FFSET
RN2
S2-1
2 RN2 13
19
D/A1 OUT
VREF
SHT17
20K*
U5
AD7545K
12
11
10
R'B
20
RN2
220n
12 Bit
Buffered
DAC
RN2
20K*
R12
C8
47 pf
aUll
10
SHT7
I
SHT7
R11
47n
4 2OK *11
Voo
18
20K*
RN2
+5
AD644K
DGND
CS
16
D/A1 WRSTROBE
SHT 14
Analog Output Device
DAC for Channel 1
Sheet 15
SHT 1 CLOCK
SHT 12
SHT7
'5V
U45
74LS74
Q 6
3 K
SHT7
13
SHTS
U45
SHT3
U45
74LS74
3 K
SHT7
74LS74
fi6
LOCAL
RESET
IRQ5!
IR06
SHT7
tR07
SHT5
SHT8
COUNT lOUT
SHT8
COUNT 2 OUT
SHT4
INTCLR
SHT 18A IRQ
SHT 17
SHTl
IRQ
~
J4-S7
1
Interrupt Status and Control
Sheet 16
INPUTS
OUTPUTS
SHT 14
SHT 15
SHT 13B
I
I
I
2
O/AO
1
D/A 1
+10V REF
8
A/D 1+
A/D 1
10
I
A/DCO
SHT 2
I
A GND
4
BOO
I
BO 1
I
BO 2
I
B03
I
I
B04
I
I
~
36
9
A/D3
11
14
42
44
SHT12
35
BIO
I
SHT 10
37
Bll
I
~----l
BI2
I
I
50
43
BI4
I
18
45
BI5
20
47
22
49
BI7
I
I
I
I
BO 11
24
17
BI8
I
I
I
I
BO 12
26
19
BI9
BO 13
28
21
Bll0
I
I
I
30
23
Bill
32
25
BI12
54
27
BI13
I
56
29
BI14
I
31
BI15
I
15
34
I
BO 15
SHT 9
I
BO STROBE
SHT 9
I
BI CTS
SHT 2
I
D GND
~
33
55
I
BI6
BO 14
SHT 11
RATE OUT
51
53
59
57
SHT8
I
DELAY OUT
52
SHT8
I
COUNT OUT
58
Distribution Panel Connector J4
Data Acquisition Adapter
SHT 13A
I
BI3
L
I BO 9
I BO 10
140
I
A/DCE
41
BO 7
SHT 13A
I
I
48
BO 6
BO 8
SHT8
A/D 2+
AID 3+
38
I
I
I
I
I
A/D 2
12
40
46
BO 5
A/DO
7
SHT 12
I
A/OO+
5
3
16
SHT 11
J4
6
I
SHT10
I SHT 11
I SHT10
BOCTS
I SHT9
BI STROBE I SHT9
BO GATE
BI HOLD
COUNTIN
IRO
I
I SHT8
SHT16
Sheet 17
August 15, 1984
© Copyright IBM Corporation 1984
SHT 8
SHT 6
I
I
1
BUFF 0 0
8
3
WRITEREADGATE
SHT 3
I
BUFFREAD
SHT 3
I
BUFFREAD
SHT 3
I
BUFFRES
SHT 2
I
RESERVED
JI
IRQ
I
SHT 16
4
6
5
2
!=it
18
SHT .2
I
RESERVED
SHT 2
I
RESERVED
SHT 2
I
D GND
9
~
13
~
11
8t
15
16
SHT6
I
ASO
I
AS1
I
I
SHT 6
26
25
24
AS2
23
AS3
I
AS4
I
I
I
I
ASS
22
21
20
AS6
19
AS7
34
ASS
I
AS9
I
I
AS10
33
32
31
AS11
~
30
I
AS13
29
I
AS14
I
28
27
AS15
Expansion Bus Connector J1
August 15, 1984
© Copyright IBM Corporation 1984
Sheet 18A
Data Acquisition Adapter
141
SHT 3
SHT 3
SHT 3
DGND
SHT 3
SHT 6
SHT 6
D GND
DGND
DGND
D GND
SHT 2
I
I
l
I
I
I
I
I
l
I
LDO
I
17
I
LD1
j
I
32
16
I
LD2
I
15
J
WD3
31
J
LD3
WD3
1
14
J
I
J
LD4
DVO
I
30
13
I
LD5
I
29
12
I
LD6
I
28
11
I
LD7
27
26
10
25
9
24
8
23
7
22
6
21
I
5
20
I
HD6
L
4
19
I
HD7
HA7
I
3
DGND
I
2
WD2
DV1
DV2
DV3
DV4
I
I
DV6
I
DV7
I
I
I
WD1
~
HA4
HA5
HA6
J2
18
33
DV5
I
I
I
I
34
WDO
Expansion Bus Connector J2
142
Data Acquisition Adapter
J
I
I
I
I
HDO
I
HD1
J
I-ID2
I
HD3
J
HD4
I
I
I
I
HD5
SHT 7
SHT 7
Sheet 18B
August 15,1984
© Copyright IBM Corporation 1984
Index
A
A/D busy and interrupt states 27
A/D convert enable 28
A/D convert out 28
A/D interrupt signal 28
adapter number 108
adapter's 16-bit data bus read timing 20
adapter's 16-bit data bus write timing 18
address and control circuitry 4
address decode 4
control decode 10
device selection 13
system bus address and control signals 8
address decode 4
address decode signals 5
address decoding 69
AI control register 25, 72
AI control signals 25
AI data register 25, 73
AI device access strategy 74
interruption 75
polling 74
AI status register 25, 73
analog I/O device 21
A/D busy and interrupt states 27
A/D convert enable 28
A/D convert out 28
A/D interrupt signal 28
analog input device registers 25
analog input subsystem 21
analog output subsystem 34
analog-to-digital conversion timing diagram 26
channel selection 27
reading an analog-to-digital value 27
August 15, 1984
© Copyright IBM Corporation 1984
Index-l
sample and hold 27
starting an analog-to-digital conversion 27
analog input device 23
analog input device control 25
analog input device registers 25, 71
AI control register 25, 72
AI data register 25, 73
AI status register 25, 73
analog input potentiometers 29
bipolar offset 30
common mode rejection 33
gain 32
unipolar offset 33
analog input range 106
analog input subsystem 21
analog input device control 25
analog input device registers 25, 71
potentiometers 29
analog output device 34
analog output device control 36
analog output device registers 36, 76
AO control register 36, 76
AO data register 36, 76
analog output potentiometers 37
bipolar offset 38
gain 39
analog output range 102
switch block S 1 102
switch block S2 104
analog output subsystem 34
analog output device control 36
analog output device registers 36, 76
potentiometers 37
analog-to-digital conversion timing 26
AO control register 36, 76
AO data register 36, 76
AO device access strategy 77
Index-2
August 15, 1984
© Copyright IBM Corporation 1984
B
binary control register 43, 79
binary decode operations 42
binary I/O device 40, 78
binary I/O device control 42
binary I/O device registers 43, 78
binary input subsystem 44
binary output subsystem 45
binary I/O device control 42
binary I/O device registers 43, 78
binary control register 43, 79
binary input register 43, 80
binary output register 43, 80
binary status register 43, 79
binary input access strategies 81
binary input handshaking 44, 81
binary input hold 44
binary input port 44
binary input register 43, 80
binary input subsystem 44
binary input handshaking 44
binary input hold 44
binary input port 44
binary out gate 45
binary output access strategies 82
binary output handshaking 45, 82
binary output port 45
binary output register 43, 80
binary output subsystem 45
binary out gate 45
binary output handshaking 45
binary output port 45
binary status register 43, 79
block diagrams
address decode 4
analog input subsystem 22
analog output subsystem 34
binary I/O device 40
control decode 10
Data Acquisition adapter 3
data bus conversion circuitry 15
August 15, 1984
© Copyright IBM Corporation 1984
Index-3
device selection 13
distribution panel connector 60
expansion bus 64
interrupt circuitry 54
system bus address and control signals 7
timer / counter 46
c
channel selection 27
components
address decode 4
address decode and control circuitry 4
analog I/O device 21
analog input subsystem 21
analog output subsystem 34
binary I/O device 40
binary input subsystem 44
binary output subsystem 45
control decode 10
data bus buffer 16
data bus conversion circuitry 15
device selection 13
expansion bus 64
interrupt circuitry 54
timer / counter device 46
timer/counter system interface 47
16 bit timer/counter 49
32 bit timer 48
control decode 10
control strobes 11
counter loading 85
counter mode 0 50
counter mode 1 51
counter mode 2 51
counter mode 3 52
counter mode 4 53
counter mode 5 53
counter modes 50,51,52,53
Index-4
August 15, 1984
© Copyright IBM Corporation 1984
D
data bus buffer 16
read timing diagram 20
reading data 19
write timing diagram 18
writing data 17
data bus conversion circuitry 15
device characteristics 114
device number register 90
device registers 71
analog input device 71
analog output device 76
binary 110 device 78
device selection 13, 90
dimensions (adapter) 111
distribution panel connector 60, 93, 94
distribution panel connector signals 61
E
expansion bus 64
connector J 1 96
connector 12 98
read timing diagram 68
signals 66
write timing diagram 68
expansion bus read timing 68
expansion bus signals 66
expansion bus write timing 68
G
global interrupt reset 59
August 15, 1984
© Copyright IBM Corporation 1984
Index-5
H
handshaking 44,45,81,82
binary input 44, 81
binary output 45,82
I
interface information
distribution panel connector J4 93
expansion bus connectors 96
11 96
J2 98
interrupt circuitry 54
interrupt control register 56,91
interrupt reactivation 58
interrupt request pulse 58
interrupt status register 57, 92
interrupt control register 56, 91
interrupt level 109
interrupt reactivation 58
global interrupt reset 59
local interrupt reset 59
interrupt registers 56,91, 92
interrupt request pulse 58
interrupt status register 57, 92
interruption method 75
L
local interrupt reset 59
logic diagrams
address decode 126
analog I/O device control 134
Index-6
August 15, 1984
© Copyright IBM Corporation 1984
analog input device 135, 136
ADC 136
AI data register 136
channel multiplexer 135
sample and hold 135
analog output device 137, 138
DAC for channel 0 137
DAC for channell 138
binary II0 device control decode 131
binary input device 132
binary output device 133
control decode 127
data bus conversion 129
device selection 128
distribution panel connector 140
expansion interface connectors 141, 142
connector 11 141
connector 12 142
I/O slot 13 123
interrupt status and control circuitry 139
power supplies and grounds 124
system bus control and address lines 125
timer/counter device 130
p
polling method 74
power requirements 112
programming considerations
address decoding 69
AI device access strategy 74
analog input device registers 71
analog output device 76
analog output device registers 76
AO device access strategy 77
binary I/O device registers 78
binary input access strategies 81
binary input/output device 78
binary output access strategies 82
counter loading 85
August 15, 1984
© Copyright IBM Corporation 1984
Index-7
device number 90
device number register 90
device registers 71
interrupt registers 91
registers 70
timer/ counter device 83
timer/counter read operations 88
timer/ counter registers 83
timer/ counter write operations 86
R
reading an analog-to-digital value 27
registers 70
AI control 25, 72
AI data 25, 73
AI status 25, 73
analog input device 71
analog output device 36
AO control 36, 76
AO data 36,76
binary control 43, 79
binary II 0 device 78
binary input 43, 80
binary output 43, 80
binary status 43, 79
device number 90
device registers 71
interrupt control 56,91
interrupt status 57, 92
timer/counter device 83
s
sample and hold 27
specifications
Index-8
August 15,1984
© Copyright IBM Corporation 1984
Data Acquisition Adapter 111
dimensions 111
environment 113
power requirements 112
system reference voltage 112
device characteristics 114
analog input device 116
analog output device 114
binary device 119
16-bit timer/counter device 122
32-bit timer device 121
starting an analog-to-digital conversion 27
switch blocks
Sl 102, 103
S2 104,105
S3 106, 107
S4 108
S5 109,110
switch settings
adapter number 108
analog input range 106
analog output range channel 0 102
analog output range channel 1 104
general description 101
interrupt level 109
switch blocks 102
Sl 102,103
S2 104,105
S3 106,107
S4 108
S5 109,110
system bus address signals 8
system bus control signals 8
system reference voltage 112
T
timer/counter control register 83
timer/counter control word information 84
timer/counter device 46,83
August 15, 1984
© Copyright IBM Corporation 1984
Index-9
counter loading 85
counter modes 50,51,52,53
read operations 88
registers 83
system interface 47
write operations 86
16 bit timer/counter 49
32 bit timer 48
timer/counter device registers 83
timer/counter programming format 87
timer/counter read operations 88
timer / counter system interface 47
timer / counter write operations 86
timing diagrams
analog-to-digital conversion 26
counter mode 0 50
counter mode 2 51
counter mode 3 52
counter mode 4 53
expansion bus read/write 68
read timing 20
write timing 18
Numerals
16 bit timer/counter 49
32 bit timer 48
Index-tO
August 15, 1984
© Copyright IBM Corporation 1984
-------
-
-- --- ---_
.-
Personal Computer
Hardware Reference
Library
IBM Personal Computer
General Purpose
Interface Bus Technical
Reference
6138155
August 15, 1984
© Copyright IBM Corporation 1984
Contents
Description .................................... 1
Major Components .......................... 4
Data-Bus Buffer ......................... 5
Control-Signal Buffer ..................... 5
DMA Circuitry .......................... 6
Interrupt Circuitry ....................... 7
Address Decode Logic ................... 12
J-LPD72l0 Talker/Listener/Controller (TLC)
13
GPIB Transceivers ...................... 30
Interface Control Logic .................. 31
Programming Considerations ..................... 33
The GPIB Adapter as a Controller ............. 35
The GPIB Adapter as a Talker or Listener ....... 39
Programmed Implementation .............. 39
Addressed Implementation ................ 39
Sending and Receiving Commands ............. 43
Programmed I/O Data Transfer ............ 43
DMA Data Transfer ..................... 43
Sending END or EOS .................... 44
Stopping on an END or EOS .............. 44
Serial Polls ............................... 45
Conducting Serial Polls ................... 45
Responding to a Serial Poll ................ 46
Parallel Polls .............................. 47
Configuring for a Parallel Poll ............. 48
Conducting a Parallel Poll ................. 50
Disabling Parallel Polling ................. 50
Responding to a Parallel Poll .............. 51
Interrupts ................................ 52
Programming the Interrupt Controller ....... 54
DMA Transfers ............................ 55
Programming the DMA Controller .......... 56
Interface ..................................... 57
Connector Specifications .................... 58
Jumper Positions ............................... 59
Adapter Selection .......................... 60
August 15, 1984
© Copyright IBM Corporation 1984
iii
DMA Channel Selection .....................
Interrupt-Request Selection ..................
Interrupt-Acknowledge Selection ..............
Specifications .................................
Logic Diagram ................................
61
62
63
65
67
Index ........................................ Index-1
iv
August 15,1984
© Copyright IBM Corporation 1984
Description
The IBM General Purpose Interface Bus (GPIB) Adapter
connects IBM Personal Computer products (PC) to a
general-purpose interface bus (bus) and is designed according to
the specifications of the following industry standards as
understood and interpreted by IBM as of September 1983:
ANSI/IEEE Std. 488-1978 (includes supplement IEEE Std.
488A-1980).
The GPIB Adapter makes it possible to use the PC as a controller
for a GPIB test and measurement system. The GPIB Adapter
implements bus interface functions for communication with GPIB
devices, and implements device functions for communication with
the PC central processor and memory.
The following lists interface function codes supported by the IBM
GPIB Adapter.
Code
Description
SHI
Complete source-handshake capability
AHI
Complete acceptor-handshake capability:
data-accepted and ready-for-data (RFD)
hold off on certain events
T5
Complete talker capability:
Basic talker
Serial poll
Talk-only mode
Unaddressed on my-listen-address (MLA)
Send end message (END)
Send end-of-string message (EOS)
Dual primary addressing
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
1
TE5
Complete extended-talker capability:
Basic extended talker
Serial poll
Talk-only mode
Unaddressed on my-secondary-address
(MSA) or
listener-primary-addressed-state
(LPAS)
Send END or EOS
Dual extended addressing with software
assist
Complete listener capability:
L3
Basic listener
Listen-only mode
Unaddressed on my-talk-address (MTA)
Detect END or EOS
Dual primary addressing
LE3
Complete extended-listener capability:
Basic listener
Listen-only mode
Unaddressed on MSA or
talker-primary-addressed-state (TPAS)
Detect END or EOS
Dual extended addressing with software
assist
SRl
Complete service request capability
RLl
Complete remote and local capability with
software interpretation
PPl
Remote parallel poll configuration
PP2
Local parallel poll configuration with software
assist
2
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
DCI
Complete device-clear capability with software
interpretation
DTI
Complete device-trigger capability with
software interpretation
CI-5
Complete controller capability:
System controller
Send interface-clear (IFC) and take
control
Send remote-enable (REN)
Respond to service-request (SRQ)
Send interface messages
Receive control
Pass control
Parallel poll
Take control synchronously or
asynchronously
EI/2
Three-state bus drivers with automatic switch
to open-collector drivers during parallel poll
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
3
.a;..
0""
'"d::T
_G
~
tJ:l ......
"tI
~
>@:
0. 0
"0 ......
==
~ ~
>
=-
~I='
~
....
~Otl
0"
0
~
"PD72lO
n
Ii';'
0.
......
CONTROL
~
Otl
INT
'"1
~
8
DMAREQ, DMAACK
DMA EN
GPIB
OMAACK
TRANSCEIVERS
(/.I
::T
0
~
Ul
~
75160A
75162A
@
n
8
~
'<
'"1
:1.
sc
g-
S3>
::::~
OCl
n
o ~
..,(/.1
"0
::T
G
......
0
0
"0
(JQ
~
s;_
~Ul
o'~
:1_
-\.0
'Doc
~.j:>.
FLIP FLOPS
~
n
0
- -=a
DATA
...
~
~
;...
n
o
8
"0
0
I='
G
I='
~
(/.I
0
......
~
::T
G
0
=
B
~
!;I.l
Data-Bus Buffer
The data-bus buffer transfers the data between the system's
input/output (I/O) channel and the GPIB Adapter. The
channel's data-bus signals, DO through D7, are buffered by a
Transceiver and become the internal data-bus signals, GDO
through GD7.
Control-Signal Buffer
The control-signal buffer acts as a line receiver to minimize
loading on the system's I/O channel and to increase noise
immunity. The I/O channel's control signals, the DMA
Controller's acknowledge signals, and the address lines all are
received by a Line Receiver before being used on the GPIB
Adapter. The channel signals, when received by the Line
Receiver, are given different names to avoid confusion. The
following table shows the channel signal names.
PC I/O Signal
Name
GPIB Adapter
Name
Address Lines
Al0
All
A12
RSO
RSl
RS2
Control Signals
lOR
lOW
RESET DRV
Read (RD)
Write (WR)
RESET
TIC
GT/C
DACK 1
DACK 2
DACK3
DACK
DACK
DACK
DMA Control
Acknowledge
Sianals
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
5
DMA Circuitry
The DMA circuitry recognizes when direct-memory access
(DMA) operations are enabled or disabled, and routes the DMA
request and acknowledge signals between the adapter and the
selected DMA channels.
The DMA acknowledge and request signals at the channel
connector are brought to jumper pin arrays on the board. These
pin arrays are arranged so that two small pin-to-pin shunt
connectors, which are supplied with the adapter, can be used to
select the proper pair of DMA signals for the adapter's use. Side
B of the pin array is connected to the channel connector, and side
A is connected to 'DMA acknowledge' (DACK) and'DMA
request' (DRQ DLY).
DACK is ANDed with 'DMA enable' (DMA EN) and becomes
'DMA acknowledge' (DMAACK). When DMAACK goes low,
both halves of U5 (a dual 74LS74A flip-flop) are cleared, and the
DMAACK pin on the Talker/Listener/Controller (TLC) goes
low. When DMAACK returns to high, the DMAACK pin on the
TLC goes high. The flip-flops delay the low-to-high transition of
the DMAACK signal for a minimum of 200 nanoseconds to
prevent any spurious TLC DMAREQ pulses from being sent to
the DMA Controller.
August 15, 1984
6
GPIB Adapter
© Copyright IBM Corporation 1984
Interrupt Circuitry
The interrupt circuitry recognizes when interrupts have been
enabled or disabled and passes or inhibits them accordingly.
The interrupt circuitry consists of logic and an array of jumper
pins to allow user selection of the channel 'interrupt request'
signal. The interrupt logic consists of one gate of a 74LS125A
three-state buffer, which drives the A side of an array of jumper
pins. The input of the buffer is tied to ground, and the enable for
the gate is driven by the 'interrupt request' signal (INT REQ),
which is generated by the shared interrupt logic. The B side of
the jumper pin array is connected to the channel 'interrupt
request' signals, IRQ2 through IRQ7. The pin array is arranged
so that a small pin-to-pin shunt connector, which is supplied with
the adapter, can be used to select the desired interrupt-request
level.
Because the input of the three-state buffer is tied to ground, an
active interrupt request (INT REQ is low) corresponds to a low
level being sent onto the selected interrupt-request bus line.
When INT REQ is high, no i1}terrupt is being requested, and the
output of the buffer's gate is in a high-impedance state. The 8.2
kilo-ohm pull-up resistor attached to the output of the gate
ensures that the IRQX signal (X is 2, 3, 4, 5, 6, or 7) is pulled to
a high level when the board is not requesting an interrupt.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
7
Shared Interrupt Logic
The shared interrupt logic, when used with the appropriate
interrupt-handling programs, allows multiple adapters to use or
share the same system I/O channel's interrupt-request line.
This interrupt-sharing scheme works properly only when adapters
using the same interrupt level are installed in the same unit.
The IRQX line is treated as an open-collector type of line, even
though it is connected to the output of a three-state gate. This
gate pulls the line to a low level when the adapter is requesting an
interrupt. Adapters using the IRQX line also can pull the line to
ground at the same time. Other adapters using the same IRQX
line, but not requesting an interrupt, are not driving the line,
because their gates are in a high-impedance state.
The shared interrupt logic generates a low-going pulse that is two
system clock periods long to request an interrupt from the
processor.
When the 'interrupt enable' signal (INT EN) from the interface
control logic is high, the GPIB Adapter can request interrupts.
Interrupt requests to the shared interrupt logic originate from the
interrupt signal (INT) of the TLC (TLC INT) and the DMA
terminal-count interrupt (DMA TIC INT) logic.
8
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
The TLC INT signal goes high, when the corresponding TLC
mask bit is unmasked and any of the following GPIB events
occur:
•
Command pass through (unrecognized command) received
•
Address pass through (unrecognized or secondary address)
received
•
Device trigger received
•
End message received
•
Device clear received
•
Error (no listeners)
•
Data out (ready to originate data byte)
•
Data in (data byte accepted)
•
Service request interrupt
•
Command out (ready to originate command byte)
•
Lockout-mode status change
•
Remote-mode status change
•
Address status change
The DMA TIC INT signal goes high whenever the DMA
Controller channel being used by the adapter during a DMA
transfer reaches terminal count.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
9
If the interrupt handler chooses not to clear the source of the
interrupt, the IRQX high-to-Iow-to-high pulse is regenerated after
the handler writes to port hex 02FX. The shared interrupt logic
will generate a continuous series of IRQX pulses, thereby causing
a series of interrupts, until the handler services it.
The following is a timing diagram showing how the shared
interrupt logic functions.
+
1--
Q
...J
U
E'" .Y.
..u
~
0
>(/)u
z~
Uu
...J~
1-1-
-<{
d:2'
~o
Ic:J
d
a: UJ
a:
UJ Ia:
z
0..
I
x
d
a:
~
I-
z
I~
dl~
I-LL
~g
u
'c,
o
..-Q.
E
en
~
c
~
"0
c
~
co
o
'~
.r:
~
~
cco
~
..-
'"
:0
;;;: "0
co
~
o '" C
d-~~
z~w~~
o
u"
I-
2',;;0:0.
1
I- 'v; I-
::J
<{co
a;x
+-'
C
0::::
0:::::::
Z
I-.
I-.
+-'
Cl}
I-.
N
II
C
o ;;;:.r:
X
o~~o~
0,+-0)0
1Z
";' > ~
....c C ::J
C)CQ
U
:.c
-.J
(l)
V)
]
X
OJ
o....c
en
+-'
-0'" 0
I-E:.c~Q.
E..-ooO
00.1->:J a. c
0
+-'
t
I-.
+-'
.!:
N
~
Q)
s
0
Q.l
5- .~ ;: -g
Q.)
.~
~ Uo.. iii ~ ;;;:
~
Q.""OIc.°
2I - ~u Z ::Jt IIW
-
..-
Q.)
rC/)
(/) __
C a:
w
Cl}
~ tV Z
a.l
...-NM""'tn
10
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
DMA TIC Interrupt
The DMA TIC interrupt logic determines when the DMA
Controller has reached terminal count and generates an interrupt
request.
The 'DMA acknowledge' signal (DACK) and the DMA TIC
signals from the DMA Controller are received by the DMA
circuitry and the control-signal buffer and become DMAACK
and GT IC, respectively. These signals and INT EN generate an
interrupt request (DMA TIC INT) when the DMA Controller
reaches terminal count (GT IC makes a low-to-high transition).
DMA TIC INT goes high on a terminal-count condition only if
interrupts were previously enabled by setting anyone of the
enable-interrupt bits in interrupt mask register 1 or 2 (IMRI or
IMR2).
The DMA TIC INT signal is cleared to a low state when 'reset'
goes high or when interrupt status register 2 (ISR2) is read. An
interrupt handler routine should read ISR2.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
11
Address Decode Logic
The address decode logic monitors the 16 address lines (AO
through A15) of the system's I/O channel to determine when the
GPIB Adapter's I/O address is present on the channel, and
enables read and write access to the adapter. A 13-input NAND
gate is used, along with some inverters and jumpers, to decode the
base address, 'TLC select' (TLC SEL). The 'address enable'
signal (AEN) from the processor ensures that the adapter is not
inadvertently selected when the system processor does not have
control of the bus.
The binary base address decoded by the NAND gate is as follows.
PC Address
Select
TLC Register
Select
GPI B Adapter Base Address
15 114 113 12111110 9 18 17 16 15 14 13 12 11 10
x Ix Ix
y
I y I y 1 10 I 1 I 1 I 1 10 10 10 10 11
x
PC Address Select (Jumpers)
y
TLC Register Select (Programmed)
A second NAND gate decodes the 'interrupt enable' signal,
02FX. The binary decode process is as follows.
Interrupt Enable Base Address
Interrupt
Level
15 114 113 112 111 110 19 18 17 16 15 14 13 2 11 I 0
0101010101011 LOll 11 I 1 I 1 10 z I z I z
z
Interrupt Request Level. Must correspond to the IRQ
level selected by jumpers.
The WR and AEN signals ensure that the 02FX signal is
generated only when the system processor is writing to the
decoded address.
12
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation
1984
MPD7210 Talker/Listener/Controller (TLC)
The TLC implements almost all interface functions to interact
with other devices on the bus. Within the TLC are 21 program
registers, which are used to set up, control, and monitor the
interface functions and to pass commands and data to and from
the bus. Access to these functions is through 8 read-only
registers and 8 write-only registers, of which 5 are indirectly
addressed.
The TLC is enabled when the TLC SEL signal is low and the
'register select' signals, RSO through RS2, are decoded internally
to gain access to the appropriate register. Data on the internal
data bus (GDO through GD7) is loaded into write-only registers
at the trailing edge of WR. Data in the read-only registers is
placed on the internal data bus for a minimum access time after
both TLC SEL and RD become low.
Most of the interface functions can be implemented or initiated
from either side of the TLC. The distinction between the two is
generally that between local and remote interface messages.
Read Interface Registers
The following table lists the read-only interface registers and their
corresponding bits.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Name
Num.
Name
Name
Name
Name
Name
Name
Name
Name
DIR
ISRl
ISR2
SPSR
ADSR
CPTR
ADRO
ADRl
+0
+1
+2
+3
+4
+5
+6
+7
DI7
CPT
INT
S8
CIC
CPTl
X
EOI
DI6
APT
SROI
PEND
ATN
CPT5
DTO
DTl
DI5
DET
LOK
S6
SPMS
CPT4
DLO
DLl
DI4
ENDRX
REM
S5
LPAS
CPT4
AD5-0
AD5-1
DI3
DEC
CO
S4
TPAS
CPT3
AD4-0
AD4-1
DI2
ERR
LOKC
S3
LA
CPT2
AD3-0
AD3-1
Dll
DO
REMC
S2
TA
CPTl
AD2-0
AD2-1
DID
DI
ADSC
Sl
MJMN
CPTO
AD1-0
AD1-l
Register
Bit 0
X indicates bit is not used. Read bits that are not used may be read as 1 or O.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
13
DIR (Data-In Register)
The data-in register receives data and commands from the bus.
ISR1 (Interrupt Status Register 1)
The ISRI records the occurrence of 8 conditions or events. This
register is not a true status register because the bits are cleared
whenever they are read.
The following table describes the bits of the ISRI register.
Bit
Name
Value
7
CPT
1
Command Pass Through. An undefined
command has been received over the bus.
6
APT
1
Address Pass Through. The secondary
address (Address Mode 3) has been received.
5
DET
1
Device Execute Trigger. The Device Execute
Trigger (DET) command has been received.
4
END
RX
1
End Received. EOI or EOS command has
been received.
3
DEC
1
Device Clear. The Device Clear (DCL)
command has been received.
2
ERR
1
Error. The contents of the Command/Data
Out Register (CDOR) have been lost.
1
DO
1
Data Out. A data write request issued to the
CDOR.
a
DI
1
Data In. A byte has been written to the DIR,
and the DIR should be read.
14
GPIB Adapter
Function
August 15, 1984
© Copyright IBM Corporation 1984
ISR2 (Interrupt Status Register 2)
The ISR2 records the occurrence of 8 conditions or events. This
register is not a true status register because the bits are cleared
whenever they are read.
The following table describes the bits of the ISR2 register.
Bit
Name
Value
7
INT
1
Logical OR of the enabled interrupt status
bits.
Function
6
SRQI
1
Service Request In. A respond to service
request (SRQ) message has been received
while the controller is active.
5
LOK
1
Lockout (non-interrupt bit). The device is in
local with lockout state (LWLS) or remote
with lockout state (RWLS).
4
REM
1
Remote (non-interrupt bit). The device is in
remote state (REMS) or RWLS.
3
CO
1
Command Output. A request for a
command to be written to the CDOR.
2
LOKC
1
Lockout Change. The value of the LOK bit
(bit 5) has changed.
1
REMC
1
Remote Change. The value of the REM bit
(bit 4) has changed.
0
ADSC
1
Address Status Change. One of the four bits
(TA, LA, CIC, MJMN) of the address status
register has changed.
SPSR (Serial Poll Status Register)
The serial poll status register echoes the contents of the serial poll
mode register (SPMR). This status can be read to confirm that a
request for a serial poll was accepted.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
1S
ADSR (Address Status Register)
The address status register contains information about the current
addressed state of the GPIB Adapter.
The following table describes the bits of the ADSR register.
Bit
Name
Value
7
CIC
1
The device is controller in charge.
6
ATN
1
Attention. The device is in data transfer
mode; the ATN line is high.
5
SPMS
1
Serial poll mode state: The serial poll
enable (SPE) message has been received.
4
LPAS
1
The device is in listener primary addressed
state.
3
TPAS
1
The device is in talker primary addressed
state.
2
LA
1
Listener Addressed: The device is in
listener addressed state.
1
TA
1
Talker Addressed: The device is in talker
addressed state.
0
MJMN
1
A major-talk or major-listen address has
been received.
0
A minor-talk or minor-listen address has
been received.
16
GPIB Adapter
Function
August 15, 1984
© Copyright IBM Corporation 1984
CPTR (Command Pass Through Register)
The command pass through register reads the data on the data
input/output (DIO) lines for the following situations:
If ISRI bit 7 (CPT) is equal to 1 and auxiliary register B
(AUXRB) bit 0 (CPT ENABLE) is equal to 1 then CPTR has an
undefined command or has received a secondary command after
an undefined primary command.
If ISRI bit 6 (APT) is equal to 1 and Address Mode 3 is selected
then CPTR contains a secondary address.
After a parallel poll the CPTR contains the parallel-poll response
message.
August 15,1984
© Copyright IBM Corporation 1984
GPIB Adapter
17
ADRO (Address Register 0)
Address register 0 contains the major address set by the address
register (ADR), as well as the functions enabled for that address.
The following table describes the bits of the ADRO register.
Bit
Name
Function
Not used
7
6
DTO
Disable Talker O. Set or cleared by a write to ADR.
5
4-0
DLO
Disable Listener
AD5-0
to
AD1-0
o.
Set or cleared by a write to ADR.
Major Address. Set by a write to ADR.
ADR1 (Address Register 1)
Address register 1 contains the minor address set by the address
register (ADR), as well as the functions enabled for that address.
The following table describes the bits of the ADRI register.
Bit
Name
7
EOI
End or Identify. Indicates that EOI message was sent
on the last data byte received.
6
DT1
Disable Talker 1. Set or cleared by a write to ADR.
5
DL 1
Disable Listener 1. Set or cleared by a write to ADR.
4-0
AD5-1
to
AD1-1
18
Function
Minor Address. Set by a write to ADR.
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Write Interface Registers
The following table lists the write-only interface registers.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Name
Num.
Name
Name
Name
Name
Name
Name
Name
Name
COOR
IMRl
IMR2
SPMR
AOMR
AUXMR
AOR
EOSR
+0
+1
+2
+3
+4
+5
+6
+7
C007
CPTIE
C006
APTIE
SROIIE
rsv
Ion
CNTl
OT
EC6
C005
OETIE
OMAO
S6
TRMl
CNTO
OL
EC5
C004
ENOIE
OMAI
S5
TRMO
COM4
A05
EC4
C003
OECIE
COlE
S4
C002
ERRIE
LOKCIE
S3
COOl
DOlE
REMCIE
S2
AOMl
COM'I
COOO
OIIE
AOSCIE
Sl
AOMO
COMO
AOl
ECO
Register
X
S8
ton
CNT2
ARS
EC7
X
X
COM3
A04
EC3
COM2
A03
EC2
A02
ECl
Bit 0
X indicates bit is not used.
CD OR (Command/Data Out Register)
The command/data out register is an output-only register used to
send commands or data to the bus.
IMRI (Interrupt Mask Register 1)
The interrupt mask registers are used to enable or disable the
generation of the INT signal on the occurrence of key events.
The following table describes the bits of the IMRI register.
Bit
Name
Function
7
CPTIE
Command Pass Throuqh, Interrupt Enable
6
5
APTIE
Address Pass Through, Interrupt Enable
DETIE
Device Trigger, Interrupt Enable
4
ENDIE
END message (EOI) or EOS message
received, Interrupt Enable
3
2
DECIE
Device Clear, Interrupt Enable
ERRIE
Error, Interrupt Enable
1
DOlE
Data Out, Interrupt Enable
0
DIIE
Data In, Interrupt Enable
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
19
IMR2 (Interrupt Mask Register 2)
The following table describes the bits of the IMR2 register.
Bit
Name
Function
Write a 0 to this bit.
7
6
5
SRQIIE
Service Request In, Interrupt Enable
DMAO
DMA Output (non-interrupt). Enables or
disables a DMA transfer to the data registers
4
DMAI
DMA Input (non-interrupt). Enables or
disables a DMA transfer to the data
registers.
3
COlE
LOKCIE
REMCIE
Command Output, Interrupt Enable
Lockout Chanqe, Interrupt Enable
Remote Chanqe, Interrupt Enable
ADSCIE
Address Status Change, Interrupt Enable
2
1
0
SPMR (Serial PoD Mode Register)
The serial poll mode register holds the status byte and the local
request service (rsv) message (bit 6). When rsv is 1, the adapter
enters the service request state (SRQS). When a serial poll is
requested, the adapter sends the contents of the SPMR over the
bus and clears the rsv bit upon completion of the poll.
20
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
ADMR (Address Mode Register)
The address mode register selects the functions of the Transmit
and Receive pins (T /R2 and T /R3) and selects the address mode.
The following table shows the functions of pins T /R2 and T /R3
for the various settings of bits 4 and 5.
Bit 5
TRM1
Bit4
TRMO
T/R2
T/R3
0
0
0
EOIOE
TRIG
1
CIC
TRIG
1
0
CIC
EOIOE
1
1
CIC
PE
The following table shows the various address modes as selected
by bits 0, 1,6, and 7.
Bit 7
ton
Bit 6
Ion
Bit 1
ADM1
BitO Address
ADMO
Mode
Contents of
Adr. Reg. 0
Contents of
Adr. Reg. 1
1
0
0
0
Talk
Only
Not Used
Not Used
0
1
0
0
Listen
Only
Not Used
Not Used
0
0
0
1
Address
Mode 1
Major Talk or
Major Listen
Address
Minor Talk or
Minor Listen
Address
0
0
1
0
Address
Mode2
Primary
Address
Talk or Listen
Secondary
Address
Talk or Listen
0
0
1
1
Address
Mode 3
Primary
Address
Major Talk or
Major Listen
Primary
Address
Minor Talk or
Minor Listen
August 15,1984
© Copyright IBM Corporation 1984
GPIB Adapter
21
AUXMR (Auxiliary Mode Register)
A write to the auxiliary mode register causes one of the following
to occur:
•
An auxiliary command is issued.
•
The state-change-prohibit-time is set using the internal
counter register.
•
The parallel poll register is written to.
•
Auxiliary register A, B, or E is written to.
The following table shows the 5 internal registers and their
corresponding functions.
Control Code
CNT2
CNT1
Command Code
CNTO
COM4
COM3
When CNT2-CNTO is:
0
0
1
COM2
COM1
COMO
ICR is loaded with:
0
ClK3
ClK2
ClK1
ClKO
PPR is loaded with:
0
1
1
U
1
0
0
BIN
P3
P2
S
AUXRA is loaded with:
XEDS
REDS
HlDE
Pl
HlDA
AUXRB is loaded with:
1
0
1
ISS
1
1
0
0
INV
TRI
SPEOI
CPT
ENABLE
AUXRE is loaded with:
22
GPIB Adapter
0
0
DHDC
DHDT
August 15,1984
© Copyright IBM Corporation 1984
To issue the auxiliary commands shown in the following table,
write a binary OOOCOM4COM3COM2COM1COMo to the
auxiliary mode register.
The following table lists the auxiliary command summary.
Function Code*
Auxiliary Command
COM4
COM3
COM2
Hex
Code**
COM1
COMO
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
00
1
02
1
1
03
1
a
04
1
a
a
1
05
1
1
a
06
1
1
1
07
a
1
1
1
1
OF
a
a
a
01
1
09
a
a
a
a
1
1
a
a
a
1
11
Take Control Synchronously
1
a
1
1
a
a
1
Take Control Synchronously
on End
1
a
a
1A
Go to Standby
1
10
1
1
13
Listen in Continuous Mode
1
1
a
a
a
a
1
a
a
a
Listen
1
1
1B
a
a
a
1C
1
10
Immediate Execute pon
Chip Reset
Finish Handshake
Trigger
Return to Local
Send EOI
Non-Valid Secondary
Command or Address
Valid Secondary Command
Address
0
Clear Parallel Poll Flag
Set Parallel Poll Flag
Take Control Asynchronously
(pulsed)
1
Local Unlisten
1
1
1
Execute Parallel Poll
1
1
1
12
Set IFC
1
1
1
1
1
a
1
1
a
a
1E
Clear IFC
Set REN
1
1
1
1
1
1F
Disable System Control
1
a
1
a
a
14
16
*CNT2-CNTO set to 000 binary
**Represents all eight bits of the auxilliary mode register
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
23
AUXMR Internal Registers
The following information describes the AUXMR internal
registers.
Internal Counter Register (ICR):
A write to this register (binary OOlOclk3clk2clk 1clko) sets the
state-change-prohibit-times T 1, T 6 , T 7 , and T9 as referenced in the
ANSI/IEEE std.488-1978.
The ICR should be set to equal the system clock frequency. The
following table shows the internal counter register.
ICR
24
7
6
5
4
0
0
1
0
GPIB Adapter
3
elk 3
2
1
0
elk2
elk,
elko
August 15, 1984
© Copyright IBM Corporation 1984
Parallel Poll Register (PPR):
You can write to the parallel poll register by writing a binary
011 USP 3P2 P 1 to the AUXMR.
You should not write to this register if you are using subset PP1
(remote parallel poll configuration) as the parallel poll (PP)
interface function.
The following table shows the functions of the bits of the parallel
poll register.
Bit
Bit Name
Value
4
U
1
3
S
2-0
Function
Disables participation in parallel poll
0
Enables participation in parallel poll
1
Sense of status is the same as the ist
message (If S=ist=1, PPR is logical 1).
0
Sense of status is reversed from the ist (If
S=O and ist=O, PPR is a loqical 1).
P(3)- P(1)
Binary value of which data line (0108-0101)
to assert durinq a parallel poll.
=
U Parallel Poll Unconfigure;
S = Status Bit Polarity
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
25
Auxiliary Register A (AUXRA):
You can write to this register by writing a binary lOOA4A3A2A1Ao
to the AUXMR.
The data-receiving modes are set by bits 1 (A1) and 0 (Ao) as
follows.
A,HLDE
AoHLDA
0
0
0
Normal Handshake Mode
1
Ready for Data (RFD) Hold Off
on All (HLDA) Data Mode
1
0
RFD Hold Off on End (HLDE)
Mode
1
1
Continuous Mode
Data Receiving Mode
The transmission and receiving modes of the EOI or EOS
message are set by bits 4 (A 4), 3 (A3), and 2 (A2) as follows.
Bit
Name
Value
Function
Description
A4BIN
0
7-bit EOS
8-bit EOS
Selects seven or eight bits as the valid
lenQth of the EOS messaQe
Prohibit
Permit
Transmit EOS. Permits or prohibits
the automatic transmission of the EOI
message at the same time as the EOS
message in talker-active-state
(TACS).
Prohibit
Permit
Receive EOS. Permits or prohibits
setting the EOI bit at reception of the
EOS message
1
A 3 XEOS
0
1
A 2 REOS
0
1
26
GPIB Adapter
August 15, 1984
1984
© Copyright IBM Corporation
Auxiliary Register B (AUXRB):
You can write to this register by writing a binary lOlB4B3B2BIBo
to the AUXMR.
Following is a description of the bits of the AUXRB register.
Bit Name
B4 1SS
Value
Function
0
Individual
status
(ist)=Paraliel
Poll flag
The value of the Parallel Poll
flag is taken as the ist local
message
1
ist=SRQS
SRQS indicates the value of
the ist local message (the
Parallel Poll flag is ignored)
SRQS=ist=l; SRQS=ist=O
liNT
OINT
Specifies the active level of
the INT pin
0
T(l) (low
speed)
Sets low speed as T( 1) in all
cases
1
T(l) (high
speed)
Sets high speed as T(l) of
handshake after
transmission of second byte
following data transmission
1
Permit
Prohibit
Permits or prohibits the
transmission of the END
message in serial poll
address state.
Permit
Prohibit
Permits or prohibits the
setti ng of the CPT bit on
receipt of an undefined
command
B3 1NV
B2 TRI
B1 SPEOI
0
BoCPT
ENABLE
Description
1
0
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
27
Auxiliary Register E (AUXRE):
You can write to auxiliary register E by writing a binary
110000E 1E o to the AUXMR.
Following is a description of the bits of the AUXRE register.
Bit Name
E,DHDC
EoDHDT
28
Value
Function
1 enables
Enables or disables DAC hold-off by
initiating device clear active state
(DCAS)
1 enables
Enables or disables DAC hold-off by
initiating device trigger active state
(DTAS)
a disables
a disables
GPIB Adapter
August 15,1984
© Copyright IBM Corporation 1984
ADR (Address Register)
A write to the address register sets the addresses and functions
for ADRO (major) and ADRI (minor).
Following is a description of the bits of the ADR register.
Bit
Bit Value
Name
Function
Description
7
ARS
0
1
Address register 0
Address register 1
6
DT
0
1
Permitted
Prohibited
Permits or prohibits the set address
(AD1 to AD5) detected as a talk
address. This bit corresponds to OT1 or
OTO of the address registers.
5
DL
0
1
Permitted
Prohibited
Permits or prohibits the set address
(AD1 to AD5) detected as a listen
address. This bit corresponds to OL 1 or
OLO of the address registers.
4-0 AD1
to
AD5
Selects the address register (ADRO or
ADR1) to which the low-order bits are
written (AD1 to AD5)
These bits indicate device addresses
and correspond to AD5-0 to A01-0 and
A05-1 toAD1-1.
EOSR (End-of-String Register)
The end-of-string register contains the 7- or 8-bit EOS message
byte used by the GPIB Adapter to detect the end of a data block
transfer.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
29
GPIB Transceivers
Special-purpose, multi-function, GPIB transceivers serve as the
interface between the adapter and the bus.
The TLC communicates with the bus through two special-purpose
transceivers, a DS7 5160A for the data signals, and a DS75162A
for the handshake and interface management signals. The
direction of signals through these transceivers is controlled by
three signals from the TLC (TE, DC, and PE) and the 'system
control' (SC) signal from the interface control logic.
'Talk enable' (TE) is high when the TLC is a talker or active
controller, and low when it is a listener. It controls the direction
of the data, handshake, and EOI signals.
'Direction control' (DC) is inverted so that it is high when the
TLC is controller-in-charge (CIC), and low at other times. It
controls the direction of the A TN and SRQ signals.
'Pull-up enable' (PE) is high when the three-state driver mode is
active, and low when the open collector mode is active. When a
parallel poll is requested, the transceiver switches to open
collector mode.
SC controls the direction of the 'interface clear' OFC) and
'remote enable' (REN) signals, driving the bus when SC is high
and receiving from the bus when it is low.
30
GPIB Adapter
August 15,1984
© Copyright IBM Corporation 1984
Interface Control Logic
The interface control logic monitors the GPIB Adapter's data and
control busses and generates signals that control interrupt
requests, DMA requests, and system-controller capability.
The PAL12L6 is the main component in this group. The PAL
monitors the internal data bus (GDO through GD7), the 'TLC
select' signal (TLC SEL), and the 'TLC register select' signals
(RSO through RS3). These inputs allow the internal logic of the
PAL to generate the following outputs:
•
SC OFF, or 'system controller off', which is true (low) when
the TLC AUXMR is being selected and the Chip Reset or
Disable System Control auxiliary commands are being sent.
•
SC ON, or 'system controller on,' which is true (low) when
the command being written to the AUXMR involves setting
or clearing the GPIB IFC or REN signals.
•
IR2, or 'TLC interrupt register 2,' which is true (low) when
either ISR2 or IMR2 is being selected by the 'register select'
lines.
•
DMA ON, which is true (low) when the internal data bus
indicates that the DMA out (DMAO) or DMA in (DMAI)
bits of IMR2 are being set.
•
IR 1, or 'TLC interrupt register 1,' which is true (low) when
either ISRI or IMRI is being selected by the 'register select'
lines.
•
INT ON, or 'interrupt on,' which is true (high) when the
internal data bus signifies that any of the interrupt-enable
bits in IMRI or IMR2 are being set.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
31
The SC signal is latched high, signifying that the GPIB Adapter is
the system controller, whenever the TLC receives an auxiliary
command to set or clear the REN or IFC signals. SC is returned
to a low level when a Disable System Control or a Chip Reset
auxiliary command is sent to the TLC, or when RESET is low.
The DMA EN signal is latched at a low level when either of the
DMA enable bits in the TLC IMR2 is set. DMA EN is returned
to a high level if both bits are cleared or if RESET is low.
The INT EN signal is latched at a high level if any of the
interrupt-enable bits in IMR1 or IMR2 are set. INT EN is
returned to a low level if RESET is low or if all interrupt-enable
bits are cleared.
32
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Programming Considerations
When power is switched on, the system issues a bus reset causing
the following:
•
The system-controller bit is cleared.
•
The 'interrupt request' line is tri-stated.
•
'DMA request' is tri-stated.
•
RESET is sent to the TLC, causing the following:
The local command, power on (pon), is set, and the
interface functions are placed into their idle states.
The serial poll mode register (SPMR) is cleared.
The end-or-identify (EOI) bit is cleared.
AUXRA, AUXRB, and AUXRE are cleared.
The Parallel Poll flag and the request system control
(rsc) locate message are cleared.
The transmit- and receive-mode bits (TRMO and
TRMl) in the address mode register are cleared.
All auxiliary mode commands are cleared and prevented
from executing.
All other register contents should be considered as undefined
after a bus reset has been issued.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
33
The GPIB Adapter's other registers can be initialized while pon is
set. A typical programmed initialization sequence for the adapter
may include the following steps:
1.
Write the Chip Reset auxiliary command (hex 02) to
AUXMR.
2.
Set or clear the desired interrupt-enable bits in IMRI and
IMR2.
3.
Write to ADR to set the desired address for both ADRO and
ADR1.
4.
Set the TRMO and TRMI bits and select the desired
addressing mode in the ADMR.
5.
Write the serial poll response to the SPMR.
6.
If using a remote setup, clear the parallel poll register (PPR).
If using a local setup, load the parallel poll response into the
PPR.
7.
Clear pon by issuing the Immediate Execute pon auxiliary
command.
The auxiliary commands can now be executed.
34
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
The GPIB Adapter as a Controller
The GPIB Adapter can become controller-in-charge (CIC) either
by being the system controller and taking control or by having
control of the bus passed from the current active controller.
The active controller has the ability to make A TN active and send
multi-line commands and conduct parallel polls.
If the GPIB Adapter is the system controller, it can take control
by executing the following command sequence:
1.
Issue the Set IFC (hex IF) auxiliary command. (This
command should never be executed if the adapter is not
system controller.)
2.
Wait a minimum of 100 microseconds
3.
Issue the Clear IFC (hex IE) auxiliary command.
If the bus has an active controller, the GPIB Adapter waits until
the controller becomes idle before making ATN active.
If the adapter is not the system controller, it can be passed control
by the active controller using the following sequence:
1.
Receive the My-Talk-Address (MTA) command.
2.
Receive the Take Control (TCT) command.
3.
The active controller sees the completed handshake and
makes A TN inactive.
4.
The adapter automatically becomes CIC and makes ATN
active.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
35
When the adapter becomes the active controller, the following
bits are set:
•
System controller bit
•
CIC bit in the ADSR
•
CO bit in ISR2.
The GPIB Adapter sends commands as an active controller by
writing to the CDOR in response to the setting of the CO bit in
ISR2. The TLC responds to and recognizes the interface
commands it sends as well as receives.
To perform data transfers, the GPIB Adapter enters the controller
standby state (CSBS). When the data transfer is complete, the
adapter resumes active control of the bus. The way this is done
depends on the role the adapter is to play in the data transfer.
The following three cases describe the ways the adapter
completes a data transfer and then resumes control.
Case 1: GPIB Adapter as the Talker
1.
If the CO bit is set, send the GPIB Adapter's MT A.
2.
With CO set, issue the Go to Standby auxiliary command
(hex 10).
3.
Complete the data transfer.
4.
If DO is set, issue the Take Control Asynchronously auxiliary
command (hex 11).
36
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Case 2: GPIB Adapter as the Listener
1.
With CO set, issue the Listen auxiliary command (hex 13).
2.
With CO set, issue the Go to Standby auxiliary command
(hex 10).
3.
Begin data transfer.
4.
After the DI bit is set and before reading the last byte from
the DIR, issue the Take Control Synchronously auxiliary
command (hex 12).
5.
Read the DIR. The GPIB Adapter then becomes the active
controller automatically.
Note: The last byte of the data transfer can be detected by
checking the END RX bit in ISR 1.
Case 3: GPIB Adapter as neither the Talker nor Listener
Note: The talker must finish the data transfer with the
END or EOS message.
1.
With CO set, issue the Listen auxiliary command (hex 13).
2.
Set the hold-off-on-end (HLDE) bit in AUXRA.
3.
Issue the Go to Standby auxiliary command (hex 10).
4.
Begin data transfer.
5.
When DI is set, read the DIR so that the handshake cycle can
be completed by other devices on the GPIB.
6.
When HLDE occurs, issue the Take Control Synchronously
auxiliary command. Hold-off also can be detected by
reading the END RX bit in ISR1.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
37
In Cases 2 and 3, the Take Control Asynchronously auxiliary
command can be issued when the possibility of disrupting an
in-progress handshake is acceptable.
In all cases, a CO status indicates the GPIB Adapter is now the
active controller.
The GPIB Adapter can relinquish control of the bus and become
an idle controller in two ways:
1.
By issuing the Chip Reset or Disable System Control
auxiliary command.
2.
By passing control to another device. This is done by
sending the MT A of the other device followed by the TCT
interface command. The GPIB Adapter makes ATN inactive
as soon as the TCT command is accepted.
38
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
The GPIB Adapter as a Talker or Listener
The GPIB Adapter may be either the GPIB talker or listener, but
not both simultaneously. Either function is deactivated
automatically if the other is activated. The talker-addressed
(TA), listener-addressed (LA), and ATN bits in the ADSR
indicate the specific state of the adapter as follows:
ATN
TA
LA
0
1
0
Addressed Talker-cannot send data
1
1
0
Active Talker-can send data
0
0
1
Addressed Listener-cannot receive data
1
0
1
Active Listener-can receive data
Programmed Implementation
When the GPIB has no controller, the talk only (ton) and listen
only (lon) local commands are used to set the talker and listener
interface functions. These commands are set in the ADMR and
should be programmed during initialization.
Addressed Implementation
The GPIB Adapter responds to the address command that the
active controller sends over the bus, regardless of which device is
in control. This enables the adapter to respond to it's own
addressing commands which the adapter sends over the bus. The
adapter has three address modes, which are selected by writing to
the ADMR. Descriptions of the address modes follow.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
39
Address Mode 1
In this mode, the GPIB Adapter responds to two primary
addresses, ADRO (major) and ADRI (minor).
The receipt of the GPIB Adapter's primary My Listen Address
(MLA) command has the following effects:
•
LA bit in ADSR is set.
•
ADSC bit in ISR2 is set.
•
MJMN bit in ADSR is set if MLA corresponds to ADRl.
•
DI bit is set in ISRI upon receipt of a data byte in the DIR.
The receipt of the GPIB Adapter's primary My Talk Address
(MTA) command has the following effects:
•
T A bit in ADSR is set.
•
ADSC bit in ISR2 is set.
•
MJMN bit in ADSR is set if MTA corresponds to ADRl.
•
DO bit in ISRI is set when the CDOR is ready to send
another data byte.
40
GPIB Adapter
August 15,1984
© Copyright IBM Corporation 1984
Address Mode 2
Address mode 2 is used for primary and secondary addressing as
specified by the talker-extended (TE) and listener-extended (LE)
interface functions. ADRO contains the primary address, and
ADRI the secondary address.
The sequence for programming the TE interface function is
shown in the following.
Step
Results
1. MTA received
(Hex 40 + ADRO address)
TPAS bit (in ADSR) = 1
2. MSA received
(Hex 60 + ADR1 address)
TA in ADSR = 1
ADSC in ISR2 = 1
DO in ISR1 = 1
Now in TADS (Talker Addressed State)
The following shows the sequence for programming the LE
interface function.
Step
Results
1. M LA received
(Hex 20 + ADRO address)
LPAS bit (ADSR) = 1
2. MSA received
(Hex 60 + ADR1 address)
TA bit in ADSR = 1
ADSC bit in ISR2 = 1
DI in ISR1 = 1 (when data byte is available in
DIR)
Now in LADS (Listener Addressed State)
In both listener and talker addressing sequences, the
My-Secondary-Address (MSA) command must be received
before the receipt of another primary-command-group (peG)
command. The MJMN bit indicates which register is referred to
by the address status.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
41
Address Mode 3
This mode is used to implement the TE and LE interface
functions with the addition of two possible primary addresses,
major and minor. The proper operation of address mode 3 is as
follows:
Step
Results
1.Primary Address (MLA or
MT A) received.
TPAS in ADSR = 1 if MTA received
LPAS in ADSR = 1 if MLA received
MJMN in ADSR = 1 if address is ADR1
2.Secondary Address received
APT in ISR1 = 1 Data Accepted handshake
hold-off is activated
3. In program, determine if
primary address is talk, listen,
major, or minor (use TPAS,
LPAS, and MJMN bits)
4. Read the secondary address
command from the CPTR,
determine if it is the address of
the GPIB Adapter
5. If not the adapter's address,
issue the non-valid (hex 07)
auxilliary command.
Command was other secondary address
(OSA), GPIB adapter enters Listen and Talk
idle state. Handshake is completed.
6. If the secondary address is
the adapter's address, issue the
valid (hex OF) auxilliary
command.
LA = 1 and TA = 0 if LPAS = 1
TA = 1 and LA = 0 if TPAS = 1
Data-accepted message sent true and
handshake is completed.
Now in TADS (TA=1) or LADS (LA=1).
In both listen- and talk-mode sequences, the secondary address
command will continue to generate a 'data accepted' holdoff with
APT set until another peG command is received. In this way, the
controller can address several devices having the same primary
address without repeating the primary address command.
42
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Sending and Receiving Commands
When the GPIB Adapter is a talker or listener, data or
device-dependent commands can be sent or received using DMA
or programmed I/O.
Programmed 1/0 Data Transfer
When the GPIB Adapter is operating as a talker, the DO bit in
ISRI is set when all addressed listeners are ready to receive a data
byte on the bus. The GPIB Adapter responds by writing the next
byte to the CDOR.
When the GPIB Adapter is a listener, the DI bit in ISRI is set
when a data byte is available in the DIR. The DIR is then read to
complete the handshake.
In both cases, remember that the DO and DI bits are cleared
when ISRI is read.
DMA Data Transfer
When the GPIB Adapter is properly set up for a DMA transfer,
the sending and receiving of data is controlled by the TLC and
the DMA Controller. During the sending of data (DMAO bit is
set), DRQ is driven high under the same conditions that set the
DO bit. During the receipt of data (DMAI is set), DRQ is driven
high under the same conditions that set the DI bit.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
43
Sending END or EOS
The END command is sent by issuing the Send EOI auxiliary
command just before writing the last data byte to the CDOR.
The EOS command is sent simply by making the last byte the
EOS code.
Stopping on an END or EOS
The END status bit in ISRI is used to inform the program of the
receipt of an END command or EOS command.
44
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Serial Polls
Serial polls allow the controller-in-charge to obtain detailed status
information about each device set up for responding.
Conducting Serial Polls
To conduct a serial poll, the adapter must:
1.
Become active controller and send the Unlisten (UNL)
command.
2.
Send the My-Talk-Address (MTA) command of the device
to be polled.
3.
Send the Serial Poll Enable (SPE) command.
4.
Issue the Listen auxiliary command.
5.
Issue the Go to Standby auxiliary command.
6.
Issue the Take Control Synchronously auxiliary command.
7.
Read the device's status byte from the Data Input Register
(DIR).
8.
Send the Serial Poll Disable (SPD) command.
9.
Repeat Steps 1 through 8 for all devices on the bus that must
be polled.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
45
Responding to a Serial Poll
The following are recommended steps for requesting service:
1.
Check the PEND bit of the SPMR. If the bit is set, the
GPIB Adapter is currently in the serial poll active state
(SPAS).
2.
If PEND is 0, write to the SPMR the desired status byte
_(STB) with rsv (bit 6).
3.
When the active controller polls the GPIB Adapter serially,
the adapter automatically transfers the STB message to the
bus with DI07 made active, and then makes the SRQ line
inactive.
Note: If a serial poll is in progress, the GPIB Adapter waits
for its completion before making the SRQ line active.
If the serial poll end-of-information (SPEOI) bit of AUXRB is
set, the EOI line is made active with the STB.
46
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Parallel Polls
The active controller uses parallel polls to check the status of
several devices simultaneously. The meaning of the status
returned by the polled devices is device-dependent, but two
general uses for parallel polls follow:
•
When the controller sees an active SRQ in a system with
several devices, it can quickly determine which one requested
a serial poll using, usually, only one parallel poll.
•
In systems for which the response time required for the
controller to service a device is short, and the number of
devices is few, parallel polls can replace serial polls entirely,
if the controller polls frequently.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
47
Configuring for a Parallel Poll
Before conducting a parallel poll, the controller must establish the
desired parallel poll response for each device. This can be done in
two ways:
•
Local configuration (parallel poll function, subset PP2): This
involves assigning the sense of the line and the 'response' line
from the device side. This setup does not change once the
device is installed.
•
Remote configuration (parallel poll function, subset PPl):
The active controller dynamically assigns the sense of the line
and the 'response' line using interface commands. The GPIB
Adapter, when operating as the system controller, should
execute the following sequence:
48
1.
Become an active controller.
2.
Send the Unlisten (UNL) command.
3.
Send the My-Listen-Address (MLA) of the first device
to be configured.
4.
Send the Parallel Poll Configure (PPC) command.
5.
Send the Parallel Poll Enable (PPE) command for that
device.
6.
Repeat Steps 2 through 5 for each additional device.
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Because there are 8 data lines, each with two possible responses
(true or false), 16 responses are possible. The data lines are
driven open collector during parallel polls, so more than one
device can respond on a certain data line. A device sending the
line true overrides any device sending the line false.
For each data line, the sense for a parallel poll can be set as
follows:
010
Line
Value
Sense (5)
Individual
Status (ist)
True
(1 )
0
0
False
(0)
0
1
False
(0)
1
0
True
(1 )
1
1
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
49
Conducting a Parallel Poll
To conduct a parallel poll, the GPIB Adapter does the following:
1.
Becomes active controller.
2.
Issues the Execute Parallel Poll auxiliary command (hex ID).
3.
Waits for the DO bit to be set, signaling the completion of
the parallel poll.
4.
Reads parallel poll response through the CPTR, and responds
as necessary.
Note: If more than one device is driving a certain data line,
Steps 2 through 4 may have to be repeated.
Disabling Parallel Polling
To disable a device from participating in parallel polls, the GPIB
Adapter:
1.
Becomes active controller.
2.
Sends the Unlisten (UNL) command.
3.
Sends the My-Listen-Address (MLA) command for the
device to be disabled.
4.
Sends the Parallel Poll Disable (PPD) command.
5.
Sends the Parallel Poll Unconfigure (PPU) command.
6.
Repeats Steps 2 through 5 for each device to be disabled.
50
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Responding to a Parallel Poll
Before the GPIB Adapter can be polled by the CIC, the following
must occur:
•
For a remote setup, the parallel poll commands are
interpreted without program assistance.
•
For a local setup, the controller sets the desired parallel poll
response by writing to the parallel poll register.
•
The GPIB Adapter then selects the source and value of the
local individual status (ist) message (see the following
figure).
Parallel Poll Function
Individual Status Select
(ISS in AUXRB)
ist set and cleared by the Set and Clear
Parallel Poll Flag auxilliary commands.
0
ist and SRQ set when rsv set. ist, rsv,
and SRQ cleared by completion of a
parallel poll.
1
After proper setup, programming is required for setting and
clearing the local ist command as desired.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
51
Interrupts
Interrupts are enabled through a hardware jumper to one of the
six available IRQ lines on the system's I/O channel.
Interrupt requests from the TLC are enabled using the IE bits in
IMRI and IMR2.
The DMA TIC interrupt is implemented external to the TLC and
is enabled whenever the DMAO or DMAI bit, and at least one of
the IE bits, is set. The DMA TIC interrupt is discussed further in
the next section.
The GPIB Adapter drives the selected IRQ line when at least one
of the IE bits is set in IMRI or IMR2; otherwise, the selected
IRQ line is tri-stated.
Once made active, the interrupt request line remains active until
the corresponding status register is read (ISRI or ISR2).
The DMA TIC interrupt has no corresponding status register or
bit, but is cleared when ISR2 is read.
Interrupts are selected by the Interrupt Controller on the system
board. When none of the IE bits in the TLC is set, the GPIB
Adapter's IRQ line is pulled to a high state. The IRQ line must be
pulled high because a tri-state may look like an interrupt request
to the Interrupt Controller.
52
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
An interrupt handler routine for the GPIB Adapter must do the
following:
1.
Read ISR2 to see if the INT bit is set, thus confirming that
the GPIB Adapter has issued an interrupt. If the DMA T /C
interrupt has been enabled, the INT bit will not be set when
it occurs; however, the DMA Controller will indicate
whether it has reached terminal count for the GPIB
Adapter's DMA channel.
2.
Read ISRI. Reading both ISR2 and ISRI will clear an
interrupt caused by any of the 13 possible conditions.
3.
Write the End of Interrupt command to the Interrupt
Controller.
4.
Write to I/O address hex 2FX, where X is the interrupt level
being used by the GPIB Adapter. Writing to 2FX reenables
interrupts on the adapter.
In a system where several GPIB Adapters share the same
interrupt level, Steps 1 through 4 should be used in each adapter's
interrupt handler routine. Each of the adapters is polled until the
one that caused the interrupt is found. When hex 2FX is written
to, any pending interrupt from another GPIB Adapter is allowed
to occur, and that adapter may then be serviced.
Note: Remember that the status bits in ISRI and ISR2
automatically clear when the register is read. A software
copy of these registers should be maintained.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
53
Programming the Interrupt Controller
Programming information for the Interrupt Controller chip may
be found in Intel's Intel Component Data Catalog. Additional
information may also be found in technical references for your
system.
Note: At power-up time, the Interrupt Controller is
initialized by the IBM PC BIOS program, which is in ROM
on the system board. Programs written for processing GPIB
Adapter interrupts must in no way change the overall
configuration of the controller. Commands written to the
controller should affect only the selected IRQ line.
The setup of the Interrupt Controller and the way it is used by the
BIOS may be found in the BIOS program listing in your system's
technical reference.
54
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
DMA Transfers
DMA transfers must be enabled through two hardware jumpers to
one of the three available pairs of DMA transfer lines on the
system's I/O channel.
DMA requests from the TLC are enabled using the DMAO and
DMAI bits in IMR2. The TLC generates a DMA request under
the same conditions that set the DO and DI bits in ISRl. A DMA
request indicates that the TLC requires either a byte to be written
to the CDOR or a byte to be read from the DIR. The 'DMA
request' signal (DRQ) is cleared by a low on the DACK.
The GPIB Adapter drives the selected DRQ line and enables the
DACK line whenever the DMAO or DMAI bit is set in IMR2.
Otherwise, the selected DRQ line is tri-stated, and the DACK
lines are disabled.
DMA transfers are selected by the DMA Controller on the
system board. The DMA Controller should never be enabled to
respond to a DMA request from the GPIB Adapter when neither
the DMAO nor DMAI bit is set in the TLC. This tri-states the
adapter's DRQ line, which may look like a DMA request from the
adapter.
Once made active, the DMA request line remains active until a
DMA transfer occurs, or until a read from the DIR or a write to
the CD OR occurs, depending on the direction of the DMA
transfer.
The DMA terminal count (T / C) interrupt is enabled whenever
the DMAO or DMAI bit is set and at least one of the interrupts
internal to the TLC is enabled.
The DMA T /C interrupt is asserted when the DMAO or DMAI
bit is set, and the system's I/O channel T /C line sends a high
pulse during a DMA transfer to the adapter. A high pulse on the
T / C line means the DMA Controller chip has reached terminal
count (that is, the DMA Controller's byte count has gone from 0
to FFFF for the corresponding DMA channel). The DMA T/C
interrupt is cleared when ISR2 is read.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
55
The DMA TIC interrupt can be detected by reading the status
register or channel byte-count register of the DMA Controller.
The terminal-count bit corresponding to the GPIB Adapter's
selected DMA channel is set in the DMA Controller's status
register when the controller reaches terminal count for that DMA
channel. All terminal-count bits are cleared when the controller's
status register is read. The channel byte count should be FFFF
unless the DMA Controller has been programmed to start that
channel automatically.
Programming the D MA Controller
Programming information for the DMA Controller chip may be
found in Intel's Intel Component Data Catalog. Additional
information may also be found in the technical references for
your system.
Note: At power-up time, the DMA Controller is initialized
by the IBM PC BIOS program, which is in ROM on the
system board. Programs written for processing GPIB
Adapter DMA transfers must in no way change the overall
configuration of the controller. Commands written to the
controller should affect only the selected DMA channel.
The setup of the DMA Controller and the way it is used by the
BIOS may be found in the BIOS program listing in your system's
technical reference.
56
GPIB Adapter
August 15,1984
© Copyright IBM Corporation 1984
Interface
The following illustration shows the GPIB Adapter with its
connectors.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
57
Connector Specifications
The following table provides the pin numbers and their signals:
13
12;;
Signal Name / Description
1
2
010 3
0104
EOI (24)
4
5
3
6
7
NDAC
IFC
SRQ
9
10
ATN
11
IBM
SHIELD
0105
12
13
14
GPIB
0106
010 7
8
16
Gnd, (6)
Gnd, (7)
18
19
Gnd, (8)
Gnd, (9)
20
21
17
Gnd, (10)
22
Gnd, (11)
23
24
GPIB Adapter
Adapter
15
0108
REN (24)
Gnd, LOGIC
58
p'In
010 2
DAV
Device
24
0101
NRFD
GPIB
~
August 15,1984
© Copyright IBM Corporation 1984
Jumper Positions
This section describes the jumper positions that may be selected
when installing the adapter.
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
59
Adapter Selection
The following figure shows the jumper positions required for the
adapter number of each adapter.
DDDDDDn~
DDDDDDU
-c:::>-
-c:::>-
-cr
.<:J.
~D
Adapter Number
Jumper Positions
0
[I
2
3
4
5
6
7
60
GPIB Adapter
~
~
~
~
=
~
E]
August 15, 1984
© Copyright IBM Corporation 1984
DMA Channel Selection
The following shows the jumper positions for selecting DMA
channels.
Direct-Memory
Access Channel
Jumper Positions
[II: :[ [;J
••
2
••••
~
3
[: :II[ ~
••
August 15, 1984
© Copyright IBM Corporation 1984
U
GPIB Adapter
61
Interrupt-Request Selection
The following shows the jumper positions for selecting the
interrupt-request line.
Interrupt-Request
Level
Jumper Positions
7
6
5
4
3
2
62
GPIB Adapter
August 15,1984
© Copyright IBM Corporation 1984
Interrupt-Acknowledge Selection
The following shows the jumper positions for each
interrupt-acknowledge level.
InterruptAcknowledge Level
Jumper Positions
7
6
5
4
3
2
August 15,1984
© Copyright IBM Corporation 1984
GPIB Adapter
63
Notes:
64
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Specifications
Size:
Length: 11.43 em (4.5 in)
Height: 10.67 em (4.2 in)
Thickness: 1.57 em (0.62 in)
Weight: 114.3 g (4.0 oz)
Power Requirements:
Voltage: 5 Vdc (+/-5%)
Current: 750 rnA Max, 400 rnA Typical
Power Dissipation: 3.75 Watts Max
August 15, 1984
© Copyright IBM Corporation 1984
GPIB Adapter
65
Notes:
66
GPIB Adapter
August 15, 1984
© Copyright IBM Corporation 1984
Logic Diagram
The following is the logic diagram of the GPIB Adapter.
~~
ci;~
.-~~;;~~~~: b-~
:;-
-~
,.
Ii
I~.
August 15,1984
© Copyright IBM Corporation 1984
GPIB Adapter
67
Notes:
68
GPIB Adapter
August 15,1984
© Copyright IBM Corporation 1984
Index
Special Characters
MPD72l0 (TLC) 13
read interface registers 13
write interface registers 19
A
address decode logic 12
address mode register (ADMR) 21
address mode 1 40
address mode 2 41
programming the LE interface function 41
programming the TE interface function 41
address mode 3 42
address register (ADR) 29
address register 0 (ADRO) 18
address register 1 (ADRl) 18
address selection 60
address status register (ADSR) 16
addressed implementation of talker and listener 39
address mode 1 40
address mode 2 41
address mode 3 42
ADMR (address mode register) 21
ADR (address register) 29
ADRO (address register 0) 18
ADRI (address register 1) 18
ADSR (address status register) 16
auxiliary mode register (AUXMR) 22
AUXRA (auxiliary register A) 26
August 15, 1984
© Copyright IBM Corporation 1984
Index-l
AUXRB (auxiliary register B) 27
AUXRE (auxiliary register E) 28
ICR (internal counter register) 24
PPR (parallel poll register) 25
auxiliary register A (AUXRA) 26, 27
auxiliary register E (AUXRE) 28
AUXMR (auxiliary mode register) 22
AUXRA (auxiliary register A) 26
AUXRB (auxiliary register B) 27
AUXRE (auxiliary register E) 28
ICR (internal counter register) 24
PPR (parallel poll register) 25
AUXRA (auxiliary register A) 26, 27
AUXRE (auxiliary register E) 28
B
block diagram GPIB adapter 4
c
CDOR (command/data out register) 19
codes (interface codes supported) 1, 2, 3
command pass through register (CPTR) 17
command/data out register (CDOR) 19
components
jlPD72lO TLC l3
address decode logic 12
control-signal buffer 5
data-bus buffer 5
DMA circuitry 6
GPIB transceivers 30
interface control logic 31
interrupt circuitry 7
conducting a parallel poll 50
conducting serial polls A5
Index-2
August 15, 1984
© Copyright IBM Corporation 1984
configuring for a parallel poll 48
control-signal buffer 5
controller application 35
CPTR (command pass through register) 17
D
data transfer cases 36, 37
data-bus buffer 5
data-in register (DIR) 14
DIR (data-in register) 14
disabling parallel polling 50
DMA channel selection 61
DMA circuitry 6
DMA controller 56
DMA data transfer 43
DMA T / C interrupt 11
DMA transfers 55
E
END or EOS (sending) 44
END or EOS (stopping) 44
end-of-string register (EOSR) 29
EOSR (end-of-string register) 29
G
GPIB transceivers 30
August 15, 1984
© Copyright IBM Corporation 1984
Index-3
I
ICR (internal counter register) 24
IEEE-488 interface function codes 1
IMRI (interrupt mask register 1) 19
IMR2 (interrupt mask register 2) 20
interface control logic 31
interface information 57, 58
interface registers 13
read only 13
ADRO (address register 0) 18
ADRI (address register 1) 18
ADSR (address status register) 16
CPTR (command pass through register) 17
DIR (data-in register) 14
ISRI (interrupt status register 1) 14
ISR2 (interrupt status register 2) 15
SPSR (serial poll status register) 15
write only 19
ADMR (address mode register) 21
ADR (address register) 29
AUXMR (auxiliary mode register) 22
CD OR (command/data out register) 19
EOSR (end-of-string register) 29
IMRI (interrupt mask register 1) 19
IMR2 (interrupt mask register 2) 20
SPMR (serial poll mode register) 20
internal counter register (ICR) 24
interrupt circuitry 7
DMA T/C interrupt 11
shared interrupt logic 8
interrupt controller 54
interrupt handler routine 53
interrupt mask register 1 (IMRl) 19
interrupt mask register 2 (IMR2) 20
interrupt status register 1 (ISRl) 14
interrupt status register 2 (ISR2) 15
interrupt-acknowledge selection 63
interrupt-request selection 62
interrupts 52
ISR 1 (interrupt status register 1) 14
ISR2 (interrupt status register 2) 15
Index-4
August 15,1984
© Copyright IBM Corporation 1984
J
jumper positions
address selection 60
DMA channel selection 61
interrupt-acknowledge selection 63
interrupt-request selection 62
L
logic diagram 67
p
parallel poll register (PPR) 25
parallel poUs 47
conducting 50
configuring 48
disabling 50
responding 51
physical characteristics 65
polling
parallel polls 47
serial polls 45
PPR (parallel poll register) 25
programmed I/O data transfer 43
programmed implementation of talker and listener 39
programmed initialization sequence 34
August 15, 1984
© Copyright IBM Corporation 1984
Index-S
R
read registers 13
ADRO (address register 0) 18
ADRI (address register 1) 18
ADSR (address status register) 16
CPTR (command pass through register) 17
DIR (data-in register) 14
ISRI (interrupt status register 1) 14
ISR2 (interrupt status register 2) 15
SPSR (serial poll status register) 15
registers
read only 13
write only 19
responding to a parallel poll 51
responding to a serial poll 46
s
sending and receiving commands 43
DMA data transfer 43
programmed I/O data transfer 43
sending END or EOS 44
stopping on an END or EOS 44
serial poll mode register (SPMR) 20
serial poll status register (SPSR) 15
serial polls 45
conducting serial polls 45
responding to serial polls 46
shared interrupt logic 8
shared interrupt logic timing diagram 10
specifications 65
SPMR (serial poll mode register) 20
SPSR (serial poll status register) 15
Index-6
August 15,1984
© Copyright IBM Corporation 1984
T
talker or listener application 39
addressed implementation 39
programmed implementation 39
talker /listener / controller [,uPD72lO (TLC)] 13
read interface registers 13
write interface registers 19
w
write registers 19
ADMR (address mode register) 21
ADR (address register) 29
AUXMR (auxiliary mode register) 22
AUXRA (auxiliary register A) 26
AUXRB (auxiliary register B) 27
AUXRE (auxiliary register E) 28
ICR (internal counter register) 24
PPR (parallel poll register) 25
CDOR (command/data out register) 19
EOSR (end-of-string register) 29
IMR 1 (interrupt mask register 1) 19
IMR2 (interrupt mask register 2) 20
SPMR (serial poll mode register) 20
August 15, 1984
© Copyright IBM Corporation 1984
Index-7
Notes:
-------
--- ---- ------_
-. -
Personal Computer
Hardware Reference
Library
mMVoice
Communications
Adapter
55X8866
October 11, 1985
© Copyright IBM Corporation 1985
Notes:
ii
Contents
Description ........................................
Hardware Circuit Description ......................
Functional Description ...........................
System Memory Interface .........................
Overview .................................
Host Memory ..............................
1
3
4
6
6
6
Programming Considerations ........................... 7
Interrupt Operation ............................. 7
Adapter InternalInterrupts .................... 7
Interrupt Assignment, Adapter to PC ............ 8
Interrupt Assignment, PC to Adapter ............ 9
The TMS32010 ................................ 10
Interfaces ........................................
Bus Connections ...............................
Input Output Control Register ....................
Analog DMA Control .......................
Analog Interface Description .................
Input Output Lines .............................
Input Output Address Map .......................
PSP Programming Interfaces .....................
PSP I/O Addressing Map ....................
PSP Instruction Paging ......................
PSP Address Register (TADDR) ..............
PSP Control Register (SC1) ..................
PSP Control Register (SC2) ..................
PSP Status Register (SS 1) ...................
13
13
15
17
19
21
21
23
23
23
24
25
27
31
Specifications .....................................
Electrical ......... . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Analog Specifications ...........................
Operating Conditions ...........................
FCC Requirements and Telephone Line Protection ....
35
35
35
37
38
October 11, 1985
iii
Logic Diagrams ...•.••.........•.•........•......•. 39
Index ....••••••....•..........•.....•....•... Index-1
iv
October 11, 1985
Description
The Voice Communications Adapter (henceforth called the
Adapter), part number 6294771, serves as a versatile interface
between the PC and analog signal sources. The Adapter can be
configured for a wide variety of signal processing tasks. The
Adapter uses a TMS32010 Programmable Signal Processor (PSP)
with memory, interface logic, analog connections, and other
support circuitry. A hardware interface is provided to synchronize
the processor with the PC. This allows memory access of a
common block of memory by both the Adapter and the host PC.
The Adapter plugs into the IBM Personal Computer PC, PC XT,
or PC AT from which it derives all system signals and power. The
Adapter can perform complex signal processing on signals within
the audio frequency range. The adapter has connections for two
telephone lines, a standard telephone, a microphone, and a
speaker.
October 11, 1985
Voice Communications Adapter 1
The following figure is a block diagram of the Adapter:
Interrupt
Page
PC Clock _ _ _ _-,
Registe.
Memory
PSP Instruction Bus
Gate Array
Priority Handler
D/A add. 121
AID add. 121
TADDR count
Memory Controller
Clock Generator
Analog Control
AID Register
Spkr/Mic
L.._ _ _ _
TeicoLine1
Functional Block Diagram
2 Voice Communications Adapter
October 11, 1985
Hardware Circuit Description
The Adapter consists of the analog subsystem and the digital
subsystem.
The analog section of the Adapter performs all of the interfacing
between the Programmable Signal Processor (PSP) and the
telephone lines, the telephone, the microphone, and the speaker.
The analog subsystem contains the sample/hold circuits, the
multiplexer / demultiplexer, operational amplifiers, analog line
filters, and the analog to digital and digital to analog converters.
The analog subsystem also drives the phone line, the handset, and
the two auxiliary ports used for microphone and speaker
connections.
The digital subsystem contains the PSP, the PSP instruction
RAM, interface registers, bus controllers, and associated logic. It
also contains memory and the circuitry that interfaces the PSP,
the analog subsystem, and the host PC together, thus providing a
common area accessible to all. All software resides in the PSP
instruction RAM.
October 11, 1985
Voice Communications Adapter 3
Functional Description
The Adapter Card is a programmable coprocessor with an analog
back end connected to the host processor by shared memory. This
coprocessor is a general purpose processor with special
instructions used for signal processing. It has an instruction
execution time of 200 nanoseconds, including 16 x 16 bit
multiplies.
The Adapter contains two memories that are used by the PSP.
The first memory is for program instructions, while the second
memory is for sample data storage and for communication with
the host PC. Both of these memories are accessible by the host
PC processor although not at the same time. Each processor
(either the PSP or the host PC) may interrupt the other with
maskable interrupts. The PSP is controlled by the host processor.
The PSP must have its instructions loaded before the Adapter will
function properly.
The Adapter draws power ( + / - 12 V dc and + 5 V dc) from the
motherboard connector. Three ground lines are provided. Four
connections to the maskable interrupt lines (2, 3, 4, and 7) are
provided, the level of which is selectable by a jumper.
The analog subsystem on the Adapter consists of two full duplex
audio channels. The rate the analog signal can be sampled
(production rate) is selectable at 8000 Hz or 9600 Hz.
4 Voice Communications Adapter
October 11, 1985
Both analog channels may be switched independently between the
telephone, telephone line, speaker or microphone. The telephone
and one telephone line can be connected together by the bypass
relay, allowing normal telephone use. The second analog channel
is normally connected to the second telephone line and is used for
data communications, although it may be connected to the
speaker or microphone.
The following diagrams show how the five analog connections
(telephone lines 1 and 2, the telephone, the microphone, and the
speaker) are connected:
Analog Functional Block Diagram
October 11, 1985
Voice Communications Adapter 5
System Memory Interface
Overview
This section describes the software interface as seen by the host
processor programmer.
The host interface consists of the I/O Control register (IOCR)
located in I/O memory space and an 8K address range of host PC
memory. The IOCR is used to enable the Adapter interrupts,
reset the on-board processor, select memory mapping, and load
Programmable Signal Processor instructions.
The IOCR controls the setup of the Adapter. The 8K of PC
memory is used to pass programs and data back and forth
between the host PC and the PSP.
Host Memory
The Adapter has 20K bytes of memory that are mapped into the
host PC in two 8K groups and one 4K group. The mapping
address (PC) is jumper selectable to start at DAOOO, D8000,
DCOOO or DEOOO.
The Adapter memory that may be mapped into the host PC is the
PSP Data memory image, the PSP instruction memory (low 4K)
or the PSP instruction memory (high 4K).
Note: PSP data memory is 16 bit words, while PC data is in
bytes. Thus, only one-half of the instruction memory (4K) may
be mapped (at one time) into 8K (bytes) of PC memory.
6 Voice Communications Adapter
October 11, 1985
Programming Considera tions
Interrupt Operation
Adapter Internal Interrupts
A single level of maskable interrupt is available on the PSP.
When a maskable interrupt is generated the INTF (interrupt flag)
is set. This informs the processor that an interrupt needs to be
serviced. At the start of the next available clock cycle, the
processor clears the INTF flag and sets the INTM bit to prevent
another interrupt service condition. The program counter is saved
on the stack and then the program counter is loaded with address
0002. The program branches to whatever instruction is located at
address 0002.
Note the distinction between the way interrupts are handled
internal to the Adapter and the way interrupts are handled by the
PC. The PC allows eight interrupts to be handled in priority
sequence; the PSP allows one mask able interrupt.
The jumper block located on the Adapter maps the PSP buffered
processor interrupt request (IRQ) into one of the host system
interrupt lines. The level of interrupt passed from the card to the
host is set by this jumper. A low to high transition on a host PC
IRQ line tells the host PC that an interrupt exists on that line.
When not active, the selected interrupt lines are held high by an
8.2KQ pull-up resistor. Moving a jumper to a selected position
connects the +IRQ line of the host to the +IRQ line of the PSP.
October 11, 1985
Voice Communications Adapter 7
Interrupt Assignment, Adapter to PC
Interrupts are passed from the Adapter to the PC along a line to
the interrupt handler chip on the PC. This level is jumper
selectable on the Adapter to one of four levels: 2,3,4, or 7. A
setting of 4 is recommended as it is used for communications
Adapters on the PC.
The level of this interrupt is assigned as in the following diagram:
Jumper-~-'
Installed
On
JP4
Jumper Positions
8 Voice Communications Adapter
October 11, 1985
Interrupt Assignment, PC to Adapter
The host PC interrupts the PSP by setting bit 3 of the 1/0
Control Register (IOCR). This sets an interrupt pending to the
PSP in status register SSI (SSI bit 6). Once the host PC has set
bit 3 of the IOCR, this bit cannot be reset by the PC. When the
PSP reads SS 1, this bit is cleared, showing the host that the signal
processor has acknowledged its interrupt.
The PC may reset the PSP by clearing bit 0 in the IOCR,
immediately stopping the PSP.
Note: A system reset via CTRL-ALT-DEL will not reset the
PSP.
October 11, 1985
Voice Communications Adapter 9
The TMS32010
The TMS32010 Microprocessor is the Programmable Signal
Processor (PSP) for the Adapter. This is a separate processor that
works independently of the host PC, and consists of the
following:
• A 12 bit address bus
• 4 I/O control lines
• 2 Auxiliary Registers
• Status Register
• Structured Interrupt handling
• 16 bit data bus
•
Volatile 144 word x 16 bit read/write on-chip data memory
•
Auto-incrementing/ decrementing registers for data
addressing and loop counting.
•
On-chip oscillator
•
20 MHz clock, 200ns instruction cycle time
The processor can execute one instruction while fetching the next
instruction and the data that it is to operate on. Because of both
data prefetch and address pre-calculation, fast access and
processing times are possible (up to five million instructions per
second).
10 Voice Communications Adapter
October 11, 1985
The TMS32010 can directly address up to 4K x 16 bit words.
However, an I/O register has been provided (external to the PSP)
so that 8K instructions may be addressed, logically divided as four
2K pages. Writing to I/O address 0 loads an extrenal register
called the page register.
Writing to I/O address 1 loads an external register called the
TADDR. Once this register has been loaded it can be used as a
pointer into the shared memory area (using I/O address 2). An
I/O write to address 2 will store data at the location pointed to by
the TADDR. An I/O read from ADDR2 will read data stored at
the location pointed to by the address 2.
The T ADDR has an auto-increment or auto-decrement feature
that allows it to read or write successive memory locations
without reloading the TADDR with an I/O 1 instruction. This
auto increment/decrement feature is controlled by bits 6 and 7 in
the system control register 1 (SC1, or writing to I/O location 4).
October 11, 1985
Voice Communications Adapter 11
Notes:
12 Voice Communications Adapter
October 11, 1985
Interfaces
The I/O lines on the PSP Adapter consist of PC bus lines and
Adapter edge external II0 lines. The edge connectors are used
for analog interfacing and the bus connector is used for digital
communications.
Bus Connections
The PC bus lines that are supported are:
•
Data lines 0 - 7
•
Data Address lines 0-15
•
(I/O Read) lOR
•
(I/O Write) lOW
• Static Memory Read (MEMR)
•
Static Memory Write (MEMW)
•
Clock
• Address Enable (AEN)
•
Reset Drv
• 1/0 Channel Ready
•
IRQ 2, 4, 6, 7
•
+/- 12 Vdc
October 11, 1985
Voice Communications Adapter 13
•
Ground
•
+5 Vdc
The Adapter uses the I/O Channel Ready line to cause the host
processor to wait while the PSP is reading or writing data in
Adapter memory. If the PSP is reset, or if the I/O register space
is being accessed, the I/O Channel Ready line is not pulled low.
14 Voice Communications Adapter
October 11, 1985
Input Output Control Register
The I/O Control Register (IOCR) is defined as follows:
IOCR Bit
Name
0
1
2
Enable PSP
Select instruction memory high/low
Select instruction memory
Interrupt PSP
Reserved
Enable interrupts
Interrupt status to host
3
4-5
6
7
The power-on state of the IOCR is hex 06.
The meaning of each of these bits is as follows:
Enable PSP
When clear, this bit holds the PSP in the reset state. It is cleared
on power up of the Adapter. When set, the PSP begins execution
at location 0 in instruction memory.
Select Instruction Memory High/Low
This bit selects which 4K x 16 block of PSP instruction memory is
mapped to the PC bus. When clear, this bit selects the first 4K.
When set, this bit maps the second 4K.
Note: This bit is used only when the select instruction memory
bit (bit 2) is also set.
October 11, 1985
Voice Communications Adapter 15
Select Instruction Memory
When clear, this bit maps the shared data memory to the PC Bus.
When set, this bit maps the PSP instruction memory to the PC
Bus.
Note: The PSP must be in the reset state to read or write
instruction memory (Bit 0 is clear). This prevents the PC from
changing a program while the PSP is running. When bit 0 is set,
the memory control is automatically set to the shared memory.
Interrupt PSP
When set, this bit generates both an interrupt status bit in the PSP
status register SS 1 and an interrupt pending signal to the PSP.
When the PSP reads the SSl register, the interrupt condition is
cleared and this bit is reset.
Note: Once set, this bit cannot be cleared by the host PC.
Enable Interrupts
When clear, this bit degates the PSP to host interrupt from the
system interface. When set, this bit allows the PSP to interrupt
the host processor.
Interrupt Status (to host)
When set, this bit indicates that the PSP is trying to interrupt the
host processor. It is set by the PSP but must be reset by the host.
This bit is reset when the host PC reads the IOCR. The PSP can
read this bit to detect when the host resets it, providing an
interrupt acknowledge function.
16 Voice Communications Adapter
October 11, 1985
Analog DMA Control
The analog subsystem contains four separate DMA address
registers that control where the analog channels access data
memory, and when it interrupts the PSP so that the acquired
samples may be processed (or digital samples output). Each
address counter is 12 bits wide, of which 8 bits are fixed in value
and 4 bits are used as an upcounting value.
When enabled, the address counter increments after each data
memory access (that is, after collection of each sample point).
When the 4 LSBs of an analog channel's counter wrap (from F to
0), that channel raises an interrupt request to the PSP. Thus, the
PSP is interrupted every 16 samples per channel.
There is no carry from bit 3 to bit 4, allowing register reuse
without zeroing. The 8 bits of the fixed value address need to be
adjusted through software for longer sample buffering ..
Note: Analog channels always run after reset. The enable bits in
SC2 control the DMA channels send or fetch data to the data
memory only; they do not turn the AID or D I A converters on or
off.
Each analog channel has its own outboard multiplexer under
program control. An inactive D I A section may be set to the wrap
position, preventing undesired analog output.
October 11, 1985
Voice Communications Adapter 17
The format of this data is shown in the following diagram:
Bit Range
Usage
0-3
4-B
CoD
B-F
4-bit incrementing address
8-bit fixed address
Channel Selection
Reserved
The power on state of this register is indeterminate.
DMA channels are loaded with data memory addresses. The
channel is enabled by setting the corresponding enable bit in
control register 2 (one bit is set for each channel). An I/O write
to PSP I/O address 3 loads the proper DMA address counter with
this address. Bits 12 through 14 specify which DMA channel is
loaded.
Once 16 DMA cycles are completed for a channel (that is, after
16 samples are processed) an interrupt status bit is set in SSI and
an interrupt is generated to the PSP. DMA cycles continue for the
interrupting channel(s) until the channel is disabled (by clearing
its enable bit in SC2). Reading the SSI register resets both the
interrupt pending and the interrupt status bits.
Channel selection works as shown in the following diagram:
BitsC D
Usage
00
01
10
11
D/ A converter 1
D/ A converter 2
A/D converter 1
A/D converter 2
18 Voice Communications Adapter
October 11, 1985
Analog Interface Description
Analog data is stored in Adapter external data memory until it can
be processed by a converter.
AID Channel Data
Data stored by the analog subsystem in data memory is formatted
as shown in the following diagram:
Bit range
Meaning
O-A
B
Data value
Sign bit
Sign bit extended
C-F
Data values have a range as shown in the following diagram:
Word Value
Decimal Equivalent
Meaning
FFFF
07FF
F800
0000
- 1
- Millivolts
+ full scale ( + 5 volts)
- full scale ( - 5 volts)
o volts
+ 2047
- 2048
0
October 11, 1985
Voice Communications Adapter 19
D / A Channel Data
The data read by the analog subsystem from data memory is
formatted as shown in the following diagram:
Bit Range
Meaning
O-A
B
Data value
Sign bit
ignored
C-F
Data values are as shown in the following diagram:
Word Value
FFFF
7FF
F800
0000
Decimal Equivalent
Meaning
- 1
- Millivolts
+ full scale ( + 5 volts)
- full scale ( - 5 volts)
o volts
+ 2047
- 2048
0
The hardware ignores the upper 4 bits of data when loading the
D/ A converter. Bit 11 is loaded into the DAC and is interpreted
as a sign bit.
20 Voice Communications Adapter
October 11, 1985
Inpu t Ou tpu t Lines
The IOCR address is selectable (by jumpers Sl and S2) to any of
4 addresses as shown in the following diagram:
PC I/O Address
Meaning
02lF
22lF
42lF
62lF
PSP I/O Control Register
Alternate address for IOCR
Alternate address for IOCR
Alternate address for IOCR
D8000
DAOOO
DCOOO
DEOOO
22lF
02lF
42lF
62lF
Input Output Address Map
The following diagram shows the I/O addresses selected by the
interrupt jumper block.
PC Memory Address
PSP 110 Address
02F2
02F3
02F4
02F7
IRQ
IRQ
IRQ
IRQ
2 lockout Reset
3 lockout Reset
4 lockout Reset
7 lockout Reset
After an interrupt has occurred from the Adapter to the PC,
interrupts must be enabled. The IOCR must be read by the PC,
October 11, 1985
Voice Communications Adapter 21
and then an I/O write must be performed to the address listed
above (the data written is not important).
22 Voice Communications Adapter
October 11, 1985
PSP Programming Interfaces
The following describes the programming interface from the PSP.
PSP 110 Addressing Map
PSP I/O Address
Meaning
0
Instruction Page Register
T ADDR Counter
Data Memory (at TADDR)
Analog DMA load
System Control Register 1 (SC1)
System Control Register 2 (SC2)
(SS1)
System Status Register
Reserved
1
2
3
4
5, on write
5, on read
6-7
PSP Instruction Paging
A paging scheme allows 8K of instructions to be addressed in
external PSP instruction storage. Page selection is controlled by a
two bit register, the Instruction Page Register (IPR).
The IPR is used only when address bit lIon the PSP is set. If bit
11 is clear, then this register is ignored and only the first 2 bit
page is addressed. Thus, page 0 is always addressable for interrupt
servicing.
October 11, 1985
Voice Communications Adapter 23
Pagination works as shown in the following diagram:
IPR Setting
Range Selected
00
01
1st 2K
2nd2K
3rd 2K
4th 2K
10
11
PSP Address Register (TADDR)
The PSP has 144 words of data memory internal to the chip. The
2K x 16 words of shared memory is external to the chip, not
directly accessible to the processor.
Access to this external data memory is via an external address
register known as the TADDR (TMS32010 address register). It is
loaded by writing to PSP I/O address 1. Once loaded, it is used as
a pointer to data in the external data memory using PSP I/O
address 2. Subsequent reads of address 2 fetch the data in
external data memory pointed to by TADDR. Similarly,
subsequent I/O writes to address 2 store data in external data
memory at the location specified by the TADDR address register.
The TADDR automatically increments/decrements after each
read or write, depending on the control bit settings in SC 1.
24 Voice Communications Adapter
October 11, 1985
PSP Control Register (SC 1)
This register is as shown in the following diagram:
Bit
Use
0
1-4
Raise host interrupt line
Reserved
Analog sample rate high/low
T ADDR control A
T ADDR control B
Reserved
5
6
7
8-F
The power-up value of this register is O.
The meaning of each of these bits is as follows:
Raise Host Interrupt Line
If this bit is set, the adapter raises the host interrupt line. This bit
is set by the PSP and cleared by the PC host processor, indicating
that the PC has acknowledged this interrupt. The PSP can read
this bit to see if it has been reset by the host PC processor.
Once set by the PSP, it cannot be reset by the PSP. This bit can
only be reset by the host PC reading the IOCR.
Analog Sample Rate High fLow
When this bit is clear, the analog sample rate is 8000 Hz. When
this bit is set, the rate is 9600 Hz.
October 11, 1985
Voice Communications Adapter 25
TADDR Control A and B
TADDR has an auto-increment/decrement feature, enabling
successive reads or writes to the data memory without reloading
TADDR with an I/O I instruction. This is controlled by bits 6
and 7 in system control register I (SCI, I/O address 4).
Combinations of auto-increment/decrement possibilities are as
shown in the following diagram:
Bit Value
Meaning
00
01
10
11
No change
Decrement
Increment
No change
26 Voice Communications Adapter
October 11, 1985
PSP Control Register (SC2)
Bit
Use
0
1
2
3
Enable AID channel 2
Enable AID channel 1
Enable DI A channel 2
Enable D I A channel 1
Channel 1 receive gain
Channel 2 receive gain
Bypass relay select
Telephone line 1 off-hook
Telephone line 2 off-hook
DC Wrap
Channel 1 multiplexer control
Channel 1 multiplexer control
Channel 2 mUltiplexer control
Channel 2 multiplexer control
4-5
6-7
8
9
A
B
C
D
E
F
1
2
1
2
The power on state of this register is O. The meaning of each of
these bits is as follows:
Enable AID Channel 1
When set, this bit stores analog samples at the location set in the
AID channell address register. For each sample, the address is
incremented. When incremented from F to 0 an interrupt bit for
channell is set in status register SSl.
Enable AID Channel 2
When set, this bit stores analog samples at the location set in the
AID channel 2 address register. For each sample, the address is
incremented. When incremented from F to 0 an interrupt bit for
channel 2 is set in status register SS 1.
October 11, 1985
Voice Communications Adapter 27
Enable D / A Channel 1
When this bit is set, the hardware for channell fetches digital
words from data at the location set in the D / A channel 1 address
register. After each fetch, the sample address is incremented.
When this bit is incremented from F to 0 an interrupt bit for
channel 1 is set in status register SS 1.
Enable D / A Channel 2
When this bit is set, the hardware for channel 2 fetches digital
words from data at the location set in the D / A channel 2 address
register. After each fetch, the sample address is incremented.
When incremented from F to 0 an interrupt bit for channel 2 is
set in status register SS 1.
Channel 1 Receive Gain
This bit sets the receive amplifier gain for the telephone line 1
interface to increase the level of the input signal. This is
implemented completely in analog hardware. There are four
possibilities:
Bits 54
Gain (approximate)
00
01
10
3 (this is the default setting)
11
12
18
24
Channel 2 Receive Gain
Sets the receive amplifier gain for the telephone line 2 interface to
increase the level of the input signal. This is implemented
completely in analog hardware. There are four possibilities:
28 Voice Communications Adapter
October 11, 1985
Bits 7 6
Gain (approximate)
00
01
10
11
3 (this is the default setting)
12
18
24
Bypass Relay Select
When this bit is set, the bypass relay disconnects the telephone
line 1 from the telephone and connects the telephone to the
Adapter. The telephone line 1 remains connected to the Adapter.
When this bit is reset, the line is reconnected to the phone.
When the Adapter is powered off, this relay closes and connects
the telephone to telephone line 1. This allows telephone use when
the PC is off.
Telephone Line 1 Off-Hook
When this bit is set, the PLI for line 1 goes off-hook.
Telephone Line 2 Off-Hook
When this bit is set, the PLI for line 2 goes off-hook.
DC Wrap
This connects the output of the D I A converter into the AID
converter. Values sent to the DI A convertor appear on the
receive side after conversion by the AID convertor. This feature
provides a DC path between the D I A and AID converters for
diagnostic routines.
October 11, 1985
Voice Communications Adapter 29
Channel 1 Multiplex Control 1 and 2
Controls connections to analog channel 1 for both the A/D
(receive) and the D/ A (transmit) functions. There are four
possibilities:
BitsD C
Meaning
00
01
10
11
Phone line interface 1 (transmit, receive)
Telephone (transmit, receive)
Microphone (receive), speaker (transmit)
AC Wrap (transmit, receive)
Channel 2 Multiplex Control 1 and 2
Controls connections to analog channel 1 for both the A/D
(receive) and the D/ A (transmit) functions. There are four
possibilities:
BitsFE
Meaning
00
01
10
11
Phone line interface 2 (transmit, receive)
Telephone (transmit, receive)
Microphone (receive), speaker (transmit)
AC Wrap (transmit, receive)
When both channels are set to the AC wrap mode the two
channels are connected together at a point after the bandpass
filters. This function is used by the diagnostics. When a channel is
not being used it should be set to AC wrap to prevent undesired
analog output.
30 Voice Communications Adapter
October 11, 1985
PSP Status Register (SSI)
Bit
Use
0
I
2
3
4-5
6
7
8-A
B-C
D
E
F
A/D interrupt channel 2
A/D interrupt channel I
D/ A interrupt channel 2
D/ A interrupt channell
Reserved
Host interrupt pending
Reserved
Host interrupt jumper level
Reserved
Telephone line I ring indicate
Telephone line 2 ring indicate
Cradle on-hook
The power on state of this register equals the value of the inputs.
The bits have the following meaning:
AID Interrupt Channel 2
When this bit is set, the DMA control for channel 2 has wrapped
from F-O, indicating the collection of 16 analog samples,
interrupting the PSP. Reading this register resets both this bit and
the interrupt condition. DMA is not suspended.
AID Interrupt Channel 1
When this bit is set, the DMA control for channell has wrapped
from F-O, indicating the collection of 16 analog samples,
interrupting the PSP. Reading this register resets both this bit and
the interrupt condition. DMA is not suspended.
October 11, 1985
Voice Communications Adapter 31
D / A Interrupt Channel 2
When this bit is set, the DMA control for channel 2 has wrapped
from F-O, indicating the conversion of 16 digital samples,
interrupting the PSP. Reading this register resets both this bit and
the interrupt condition. DMA is not suspended.
D / A Interrupt Channel 1
When this bit is set, the DMA control for channel 1 has wrapped
from F-O, indicating the conversion of 16 digital samples,
interrupting the PSP. Reading this register resets both this bit and
the interrupt condition. DMA is not suspended.
Host Interrupt Pending
When this bit is set, the host PC has set the bit in the IOCR,
requesting an interrupt of the PSP. Reading this register clears the
PSP interrupt and this bit in both the SS 1 and in the IOCR. The
host PC can then detect that the PSP has responded to its
interrupt.
Host Interrupt Jumper Level
These bits indicate how host interrupts are jumpered on the
Adapter. Only the PSP can read these bits in the Status register.
This allows host PC software to chose an interrupt vector for the
Adapter. Possible values are as follows:
32 Voice Communications Adapter
October 11, 1985
BitsA98
Meaning
000
010
011
100
111
Jumper not installed
Interrupt level 2
Interrupt level 3
Interrupt level 4
Interrupt level 7
Telephone Line 1 Ring Indicate (bit D)
This bit is cleared when a ringing voltage appears on line 1.
Telephone Line 2 Ring Indicate (bit E)
This bit is cleared when a ringing voltage appears on line 2.
Cradle On-Hook (bit F)
If this bit is set, the cradle is on-hook. If this bit is clear, the
telephone cradle is off-hook.
October 11, 1985
Voice Communications Adapter 33
Notes:
34 Voice Communications Adapter
October 11, 1985
Specifications
Electrical
The Adapter has the following specifications:
Power Type
-12 Vdc
+ 12 Vdc
+ SVdc
Tolerance
Ripple
Current Maximum
Current Typical
+/- 10
+/- 5
+/- 5
%
100
0.090
0.080
100
0.110
0.100
100
1.50
1.20
mv*P-P
Amps
Amps
Units.
Analog Specifications
The Adapter has five edge external lines that are used as an
analog interface. These lines consists of:
1. Telephone Line 1
Connected to the public telephone switching network Tip
and Ring signals.
•
600 ohm audio lines.
•
Output level 0 dbm maximum 300 - 3600 Hz.
October 11, 1985
Voice Communications Adapter 35
•
Ringer type B supported (15.3 - 68 Hz @ 40 - 150 Volts
Root Mean Squared)
•
Ringer Equivalent <0.2
2. Telephone Line 2 Tip and Ring
•
600 ohm audio lines.
•
Output level 0 dbm maximum
•
Ringer type B supported (15.3 - 68 Hz @ 40 - 150 V
RMS)
•
Ringer Equivalent <0.2
3. Telephone Instrument Tip and Ring
•
150 ohm audio lines.
•
Supports Bell Telephone Set type 2500, or 500.
•
Supports Bell compatible speaker phone.
4. External Speaker (female sub-miniature phono jack)
8 ohm audio pair.
•
Output power 0.5 watt maximum
5. External Microphone (female sub-miniature phono jack)
•
Audio pair
10K ohm impedance
•
Peak Input Voltage
= 16.7 mV
Note: When a telephone is connected to the telephone jack and
the Adapter is in bypass mode, the line 1 ringer equivalent is the
sum of both the telephone and the Adapter line 1 ringer
equivalent.
36 Voice Communications Adapter
October 11, 1985
Operating Conditions
The Adapter must be used under the following environmental
conditions:
Operating temperature:
15.6 C to 32.2 C
Shipment temperature
-40 C to 60 C
Storage temperature:
0.6 C to 60 C
Operating humidity:
8% to 80%
Shipment humididy
5% to 100%
Storage humidity:
5% to 80%
Maximum wet-bulb temperature: 22.8 C
FCC Class:
October 11, 1985
B
Voice Communications Adapter 37
FCC Requirements and Telephone Line
Protection
The Adapter software must monitor all outbound data to the
telephone line. If the outbound data exceeds the maximum energy
allowed by the FCC for a 3-second averaged period, the data
should be attenuated.
The Adapter must perform a 2-second billing delay. Outbound
data should be forced to silence for 2 seconds after the phone line
has gone off-hook on all incoming calls.
38 Voice Communications Adapter
October 11, 1985
Logic Diagrams
The following pages contain the logic diagrams of the Adapter.
© Copyright IBM Corporation 1985
55X8868
October 11,1985
Voice Communications Adapter 39
+CH DATA BF
+CH DATA BF (7: 0)
101
J01
013
SYS DATA \01
111
J02
012
111
121
H01
E13
121
131
H02
'"
151
H03
161
F02
FOl
171
+ ARR ADDR BIT 0
U32
........
+ ARR ADDR BIT 2
.+ ARR ADDR BIT 6
+ CH ADDR
181
'03
Fll
171
B06
H13
181
"12
181
A04
CMOS
Jl3
1101
B04
GATE ARRAY
J12
(111
IU)
C04
K13
A03
K12
III
B03
L13
n4)
171
A02
,n
(15)
181
A01
N"
191
B02
N13
no)
B01
N08
111)
003
M08
e02
N09
BOO
MOO
A06
L09
eoo
L"
e01
N07
J03
M"
- PSP 1/0 SELECT
- PSP REG SELECT
+ PSPADDR11
+ PSPADOR2
BOO
N12
Bll
Mll
B"
Kll
A"
L12
A09
N01
BOO
N02
A13
MOl
~
All
K03
COl
e12
L02
A12
K01
'03
K02
A08
Hll
~
~
~
001
~
- DEN
~
~
ell
B07
vee
vee
vee
vee
vee
vee
~
~
~
GND
~
GND
~
ICSOHIGH
ICSl HIGH
-ICS2HIGH
ICS3HIGH
ICSOLOW
ICS1LOW
- ICS2LOW
tCS3LOW
SYSCSOHIGH
SYSCSOLOW
- SYS CS 1 HIGH
~
- SYSCSl LOW
+ BUS DIRECTION
+ BUS ENABLE
+ ANALOG CH SEL
ANALOG CONVERT
+ CONVER CLOCK
+ FILTER CLOCK
+ SAMPLE/HOLD 1
+ SAMPLE HOLD 2
LO DAC BUFFER
RD ADC BUFFER
CH DATADIR
002
CH DATA ENABLE
e13
vee
~
r-;;;o;
+ INSTR R/W
Nll
A07
- PSP CARD SELCT
n3)
LDS
AOI
+IOCHRDY
+5V
161
141
- GATE ARRAY lOW
R15
3.3K
141
161
(12)
+ CH ADDR (19 0)
131
Fl2
G13
e06
+ ARR ADDR BIT 1
E12
Fl3
SYS DATA [16: 0)
GND
GND
GND
GND
'02
LEGEND:
'01
L06
M06
111
N06
121
L05
III
M05
141
N05
161
L04
161
M04
171
N04
181
GND
~
SYS ADDR 101
M03
191
N03
(10)
~
INTER-SHEET CONNECTION
'"
INTER-SHEET CONNECTION
'18
3.3K
~
~
•
HOST PC-BUS CONNECTION
HOST PC-BUS CONNECTION
NO CONNECTION
+5V
SYS ADDR \10: 0)
.".
11
U24
10
STATUS
AS04
October 11, 1985
Voice Communications Adapter 41
,
.
+ CH ADDR (19)
2
+ CH ADDR (181
+ CH ADDR 1171
+ CH ADDR (16)
"
5
,
,
+ CH ADDR (15)
+ CH ADDR (14)
-
U"
PA120R4A
3
+ CH ADDR (131
8
+ CHADDRl7I
9
..;::::;
..;::::;
22
21
- GATE ARRAY lOW
- PSP 110 SELECT
- PSP CARD SELCT
10
11
+5V~
23
-
+ CH ADDR 119: 0)
SI PINS
+'
r
2
J
9
,
.w
+ CH ADDR (6)
,
RP9
RP9
3_3K
3_3K
10
U52
PAl2{lL8A
+ CH AD DR (3)
2
+ CH ADDR (2)
3
22
+ CHADDR(I)
4
"
"
+ CH ADDR (0)
5
6
S2 PINS
8
ARR ADDR BIT 6
+ ARR ADDR BIT 1
+
ARR ADDR BITO
+ SYS DATA (10)
+ SYS DATA (91
..;::::;
"
9
+
+ ARR ADDR BIT2
"n
7
2
~
20
+ SYS DATA (81
"
10
11
"
"
23
+ CH DATA (7: 01
.5V
.sV
RP17
2
RP17
3
.
RP17
RP17
•
5
:
+ IRQ4
+ CH DATA (0)
I"
121
131
141
4
5
6
7
8
I
U55
."
TI2
.
5
JP~
02-1
151
JP~
161
8
'"
9
1
,
0-'-1
JP~
02-<
~
AO
3
1
4
October 11, 1985
LS'l'
4
4
+ IRQ7
JP~
RP17
8.2K
RP16
'OK
A2
A3
A.
7
A5
,
A'
A2
mR
ALS245
., "
so
n
"
"
"
"
"
" "
B2
.3
B4
"
11
+ CH DATA Bf (0)
I"
121
131
141
151
161
'"
+ CH DATA Bf 17: 0)
I'
Voice Communications Adapter 43
r----+----------------------------------------------------------------------------~--------------------------------<-==:J+PSPADDRO
r--+-----------------------------------------------------------------------------+--~----------------------------<:J+PSPAODR1
TMS32{)10
PROC
U23
INST DATA
INST DATA 115: 01
"'
'"
25
13'
23
14'
22
15'
21
rI,-T'T'"------------+--IH---------T"----<:::J
r'N:rS::;T'rA,D;.::D,.';;;110:r0:;.1
U9
F244
'01
INSTR ADOR 101
INSTR ADDR
m
I
lV2 ~---"C!NS"'T"-'",AD",D:::'.;:""-'__--....J
"
12
38
lVO
'61
'1
'91
12
un
5260
INSTR AOOR (l)
I-:----'::!::"'~::-:"':~",~"::-':=::"-:-----H
38
'81
INSTR ADDR (61
U12
ASao
INSTR ADDR (71
~------------+-------~~2A3
~OEl
001
A10
1111
U10
~OE2
"
INSTR ADDR 110:01
ALS138
un
5260
112)
CLKOUT
(lll
04)
0
1151
e60t
19.968
C59
J
D13
17 014
18 015
9
3
.£-
BID
veew< ~
MC/MP
DND
,.--!- 's
r-;-
'NT
INSTR AODR 181
2
~
L..-.-
r---;r--
lAO
~__+.....::6-11A2
~____+-"":''-I1A3
~12
INSTR ADDR 191
lA 1
IN5TR AD DR (10)
1Y3 f-'"'-__-";;;NS"T;.:.'...;AD:..:D;;;'...;I1.::.lI____+-________--'
~OEl
L-_--'
+ GA RESET
C>------'--j
L~
r··v:::-
L . . . - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - r - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - , r - - - - - - - < : J IN5TDATA(15:01
U.
I":-__.::'N:::S.:.TD",A"T::.A"':::"91'--1
101
111
INST DATA 115: 81
INSTR ADDA (10: 01
D2~--------"':::''--I
'21
INST DATA {7: 01
'"'21
'31
14'
1121
'41
'51
1111
'51
'"
114)
'61
'61
(15)
171
171
171
'41
'81
'81
ASO<
(NST DATA (0)
'21
'31
1111
C>-+-f--'-lU24»<>-'-..---------------------------,
20180-55
I-----'==='-'::~;-:---':-I
'91
(10)
110)
'
~
II
U12
A500
11
20180-55
"'
AU
'81
INSTR AOOR 00: 01
1101
1111
'41
151
101
'91
1131
'81
'21
'31
20180-55
AO
(NST DATA
0'
(0)
INST DATA (7: 01
'"'21
'31
141
141
15'
161
'51
'61
'81
'91
1101
INSTR ADOR {10 ,01
-ICS1LOW
October 11, 1985
rC>---__________________________________________________________________________________________________________--....J
Voice Communications Adapter 45
-ICS3LOW
.
- ICS2 LOW
INSTR ADDR
IOf
U'
AD 20180.55
111
12(
•
(31
04
141
05
A7
(81
23
19(
22
"
110/
18
- ICS2HIGH
20
21
18(
10(
19(
(11
u'
INSTDATA
AD 20180-55 01'0
A'
0'
18(
191
11
{10)
12(
11
(101
13
(111
(31
13
1111
14
(12)
14
(12)
"
(13)
141
16(
1141
(61
(15}
171
18(
23
19(
22
O'
16
07
17
O'
(61
171
INSTDATA
01 '0
0'
A'
A'
113)
114)
A'
A7
"
(10)
A10
18
CS
20
OE
21
WE
U51
17
A8
A9
A10
CS
OE
WE
INSTR ADDR (10; 01
101
INSTR ADOR
.
US
AD
III
12(
20180.56 01
13i
141
06
(61
07
171
..
A7
lSI
23
19(
22
(10)
19
INST DATA
(8)
101
III
12(
191
10
0'
11
03
13
04
05
IS(
INST DATA (16: OJ
(10)
7
A'
1111
14
(12)
141
16
1131
16(
16
1141
16(
17
(15)
O'
A'
21
'"
23
19(
22
A7
(10)
19
18
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21
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ADOR
INSTRADDR(10:O!C>-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....INSTR
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INST DATA (15: 0)
INST DATA 1 1 5 : 0 I C > - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - T ' " - - - - - - - - JL..._ _ _ _ _...:::;;.;.:;;;.;;;.:;;;;.::.
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20810·46
III
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IN
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-----
1-",,-'-+---'1
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SYS DATA (8)
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+
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21
c.
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WE
~------------+-----~~----~~
SYS DATA (15: 0)
October 11, 1985
Voice Communications Adapter
47
SYS DATA
I
101
3
111
4
121
6
131
11
141
13
151
14
9
10
U25
ALS114
20
1
2
30
3a
40
4a
50
5
60
6
------, ~CP
4
7
6
10
11
12
13
"
14
ecR
161
3
171
4
181
6
191
11
1101
13
1111
14
..--!.1
- ANALOG CONVERT
1
- RD STAT
2
- CRAOLE OFF
4
5
- PLl2 RING IND
10
9
- PUI RING IND
*
*
----*
---=
.. ,. ,
." .
,
3
SVS DATA
SYS DATA (151
U42
A
SYS DATA (141
LS125
EC
SYS DATA (131
'C
C
U22
ALS174
1
2
3
5
4
7
6
2a
30
3
40
4a
50
5a
60
6a
-;-
10
11
12
13
"
14
CP
~1
CLR
10
3
191
4
141
6
1101
11
151
13
161
14
10
U41
ALS114
30
3
40
4a
50
5a
60
60
lAO
10
1Y0
ALS244
lY2
AO
2YO
191
15 2AI
'"
181
17
13
1
18
4a~
50
sa
60
6a
SYS DATA
6
'"131
121
13
111
101
+ ADC DATA 111: 0 I
4
8
2A3
1AO
1A1
"
17
U31
lA2 ALS244
A3
11
AO
2A1
2A2
2A3
~ 0E1
151
2
161
5
30
3a
171
40
4a
50
5a
181
7
10
191
12
1101
6a~
60
CP
CLR
~
+ DAC DA TAll11
ASO<
+ CHI REC GAIN 0
~
U53
(151
U53
1131
12
1121
9
1111
==
+ CH2 REC GAIN 0
8
'"
'"
m
"
"
'"
"
"
12
11
7
1101
5
191
181
18
171
16
161
14
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12
9
10
U53
7406
(151
3
(141
4
(131
9
1121
11
1111
13
171
14
9
161
141
+ CH1 REC GAIN 1
CLR
'----;161
1a
20
15
>-----;- ~CP
~ 0"
2
131
15
7
40
9
14
'" 3
'"
2A2
0E1
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10
12
+ DACDATAll1:01
1406
WI
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C>-
U21
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20
5
U33
1Al
(101
121
CLR
2
3a
30
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111
7
1406
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+ DAC DATA
5
CP
1a
2a
20
ED
g
2
2
1a
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13
+ ADC DATA (Ill
U26
ALS174
20
U24
181
VD~*
D
10
20
3
5
2a
10
U40
ALS174
2
10
20
2a
3D
3a
40
40
50
5a
60
6a
5
7
+ CH2MUXCTL2
+ CH2 MUX CTL 1
+ CHI MUX CTL2
10
12
"
+ CHI MUX CTL 1
+ WRAP DAC ADC
+ CH2 REC GAIN 1
CP
CLR
'"
131
7
121
5
111
3
101
--'<: 0"
October 11, 1985
Voice Communications Adapter 49
;]V
,
C>--------..2'-,-";:--12-----,
,
C>----------'-l
, U" ,
C>---------'-i"
14.----. +5V
n
+ CHl RECGAIN 0
+ CHl REC GAIN 1
+ CH2RECGAINO
+
CH2REC GAIN 1
- OFF HOOK PU 1
,
MC4016
p
~
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*
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r-_-++--HI----------------<~-::.J6
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J ~L
c>-----------------'
- OFFHODKPlI2 c~::>----,
1
8
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14
13
1
9
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3.3K
+ CH2 MUX CTL2
+ CH2 MUX eTl 1
I -';,
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,
October 11, 1985
1
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+ CHl MUX elL 2
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CRADLE OFF
C>--~=============-----::::::============================:!
Voice Communications Adapter
53
Index
A
A/D Channel Data 19
A/D Interrupt Channel
1 31
A/D Interrupt Channel
2 31
Analog DMA Control 17
Analog Interface
Description 19
Analog Sample Rate
High/Low 25
Analog Specifications 35
B
Bus Connections 13
Bypass Relay Select 29
c
Channel 1 Multiplex Control
1 and 2 30
Channel 1 Receive Gain 28
Channel 2 Multiplex Control
1 and 2 30
Channel 2 Receive Gain 28
October 11, 1985
33
Cradle On-Hook (bit F)
D
D / A Channel Data 20
D / A Interrupt Channel
1 32
D / A Interrupt Channel
2 32
DC Wrap 29
Description 1
E
Electrical 35
Enable A/D Channell
Enable A/D Channel 2
Enable D / A Channel 1
Enable D / A Channel 2
Enable Interrupts 16
Enable PSP 15
27
27
28
28
F
Functional Description
4
Index-l
H
Hardware Circuit
Description 3
Host Interrupt Jumper
Level 32
Host Interrupt Pending
Host Memory 6
32
I
II0 Address Map 21
II0 Control Register 15
Input - Output Lines 21
Interfaces 13
Interrupt PSP 16
Interrupt Status (to host) 16
Interrupt Assignment,
Adapter to PC 8
Interrupt Assignment,
PC to Adapter 9
The TMS32010 10
PSP Address Register
(TADDR) 24
PSP Control Register
(SCl) 25
PSP Control Register
(SC2) 27
PSP II0 Addressing
Map 23
PSP Instruction Paging 23
PSP Programming
Interfaces 23
PSP Status Register
(SSl) 31
R
L
logic diagrams
Raise Host Interrupt
Line 25
39
s
o
Operating Conditions
37
p
Select Instruction
Memory 16
Select Instruction Memory
High/Low 15
Specifications 35
System Memory Interface 6
Programming
Considerations 7
Interrupt Operation 7
Adapter Internal
Interrupts 7
Index-2
October 11, 1985
T
TADDR Control A and
B 26
Telephone Line 1
Off-Hook 29
Telephone Line 1 Ring
Indicate (bit D) 33
October 11, 1985
Telephone Line 2
Off-Hook 29
Telephone Line 2 Ring
Indicate (bit E) 33
Index-3
Notes:
Index-4
October 11, 1985
----- --_.-
---------------
Personal Computer
Hardware Reference
Library
mM Prototype Card
6361513
ii
Contents
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110 Channel Interface . . . . . . . . . . . . . . . . . . .
Prototype Card Layout . . . . . . . . . . . . . . . . . ..
System Loading and Power Limitations . . . . . . ..
External Interface . . . . . . . . . . . . . . . . . . . . ..
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
3
3
4
6
6
9
iii
iv
Description
The IBM Prototype Card is 106.7 millimeters (4.2 inches) high by
335.3 millimeters (13.2 inches) long and plugs into an expansion
unit or system unit expansion slot. All system control signals and
voltage requirements are provided through a 2- by 31-position
card-edge tab.
The card contains a voltage bus (+5 Vdc) and ground bus (0
Vdc). Each bus borders the card, with the voltage bus on the
back (pin side) and the ground bus on the front (component
side). A system interface design is provided on the Prototype
Card.
The Prototype Card can also accommodate a D-shell connector if
it is needed. The connector size can range from a 9- to a
37-position connector.
Warning: Install all components on the component side of the
Prototype Card. The total width of the card, including
components, should not exceed 12.7 millimeters (0.500 inch).
If these specifications are not met, components on the
Prototype Card may touch other cards plugged into adjacent
slots.
Prototype Card 1
The following is a block diagram of the IBM Prototype Card.
Bit O· 7 Data Bus
8
E1
E3
E4
E6
Data Bus
Buffer
Transceiver
Bus Direction
Data
Bus
DIR G
t
1/0 ReadlWrite
Memory ReadlWrite
Spare-E18
Address Bit 0
Buffered
Address
Lines
Addrets Bit 2
Address Bit 3
t .
Address BIt 9
E2
Address
Buffer
E5
1--16_ _ _-11/0 Address
Address Enable
I - f - - - - t Decode
logic
H..--'-'. E11
-1/0 Decode
(Hex 300 . 31 F Inclusive)
Prototype Card Block Diagram
2 Prototype Card
Interface
1/0 Channel Interface
The Prototype Card has two layers screened onto it (one on the
front and one on the back). It also has 3,909 plated
through-holes that are 10.1 millimeters (0.040 inch) in size and
have a 1.52-millimeter (0.060-inch) pad, which is on a
2.54-millimeter (O.lO-inch) grid. There are 37 plated
through-holes that are 1.22 millimeter (0.048 inch) in size. These
holes are at the rear of the card (viewed as if installed in the
machine). These 37 holes are used for a 9- to 37-position D-shell
connector. The card also has 5 holes that are 3.18 millimeters
(0.125 inch) in size. One hole is located just above the two rows
of D-shell connector holes, and the other four are located in the
corners of the board (one in each corner).
Prototype Card 3
Prototype Card Layout
The component side has the ground bus, 1.27 millimeters (0.05
inch) wide, screened onto it, and card-edge tabs that are labeled
Al through A31.
Ground Bus
D-Shell Connector
Card-Edge Tabs
Hole for Option
Retaining Bracket
Component Side
The component side also has a silk screen printed on it that is
used as a component guide for the I/O interface.
C4
E10 :
=
E5 .:
E2 .:
E1
+
Component Side
4 Prototype Card
The pin side has a +5-Vdc bus, 1.27 millimeters (0.05 inch) wide,
screened onto it, and card-edge tabs that are labeled Bl through
B31.
Hole for Option
Retaining Bracket
+5 Vdc Bus
-
........
~~~~
19
37
20
1~~~~,~~m~~~;~m~~m~~'~~~~:~~~~~
D-Shell Connector
Pin Positions
Hole for Option
Retaining Bracket
Card-Edge Tabs
Pin Side
Each card-edge tab is connected to a plated through-hole by a
0.3-millimeter (0.012-inch) land. There are three ground tabs
connected to the ground bus by three 0.3-millimeter (0.012-inch)
lands. Also, there are two +5-Vdc tabs connected to the voltage
bus by two 0.3-millimeter (0.012-inch) lands.
For additional interfacing information, refer to "I/O Channel
Description" and "I/O Channel Diagram" in your Technical
Reference system manual. If the recommended interface logic is
used, the following list of TTL-type numbers will help you select
the necessary components.
Prototype Card 5
Component
TTL Number
Description
U1
74LS245
Octal Bus Transceiver
U2, U5
74LS244
Octal Buffers Line Driver/Line Receivers
U4
74LS04
Hex Inverters
U3
74LS08
Quadruple 2 - Input
Positive - AND Gate
U6
74LS02
Quadruple 2 - Input
Positive - NOR Gate
U7
74LS21
Dual 4 - Input
Positive - AND Gate
C1
10.0 IlF Tantalum Capacitor
C2,C3,C4
0.0471lF Ceramic Capacitor
System Loading and Power Limitations
Because of the number of options that may be installed in the
system, the II 0 bus loading should be limited to one Schottky
TTL load. If the interface circuity on the card is used, then this
requirement is met.
Refer to the power supply information in your Technical
Reference system manual for the power limitations to be observed.
External Interface
If a connector is required for the card function, you should
purchase one of the recommended Amp connectors listed in the
following table, or its equivalent.
Connector Size
9-pin
9-pin
15-pin
15-pin
25-pin
25-pin
37-pin
37-pin
D-shell
D-shell
D-shell
D-shell
D-shell
D-shell
D-shell
D-shell
(Male)
(Female)
(Male)
(Female)
(Male)
(Female)
(Male)
(Female)
6 Prototype Card
Part Number (Amp)
205865-1
205866-1
205867-1
205868-1
205857-1
205858-1
205859-1
205860-1
The following example shows how a I5-pin, D-shell, female
connector is attached to a prototype card.
Option Retaining
Bracket
---
8
---
0
•
•
•
•
•
•
•
••
•
•
•
•
• •
9
15
0
15-Pin D-Shell
Female Connector
Component Side
Prototype Card 7
8 Prototype Card
"====il
IMI + DATA BIT 0
IA8)·DATA8ITI>
IAlI+DATABIT2
[A6)+DAT-ABIT3
[A5)+OATABIT4
IA41"
OATA BIT 5
\A3)+DATABIT6
[A2) + DATA BIT 7
74lS245
18
17
18
15
U1
E===~~
~====~
"
13
12
11
74lS244
IBI4)-IOR
IBI31-IOW
\BI2)-MEMR
IBlll·MEMW
ISPARE)
E18
\A311+ADDR. BITO
rA3DI+AOOR.BITI
\A2!I) +AOOR. BIT 2
"
E3
E4
E6
E7
'8
'9
"0
18
1
U5
110 DECODE FOR PROTOTYPE CARD
A9 A8 A1 A6 A5 A4 A3 A2 Al AD
[MUI30D I I 000 0 0000
IMUI31f 1 1 000 1 1 I I 1
1 000 X X X X X
1
12
14lS0B
U3
11
E15
E17
E16
>------"'l
>-_ _ _-'".l
".
>-___JLJ
"3
'"
IA28)+ADDR.BIT3
IA26) +ADDR. BIT 5
jA25)+ADDR.,BtT
6
\A27) +AODR. BIT 4
>-___-1.rw'l
>----~
,,====='[lj'
>-___-"J
8
>-___-"J
\A24) +ADOR. BIT 7
IA23)"ADDR.BITB>
13
5
(A221"ADDR. BIT 9 >-___-"l'1
tAm"AEN
17
GROUND
+RESETDR
+5VOC
+IR02
-5VOC
+DRQ2
-12VDC
RESERVED
+12VOC
GROUND
-MEM W
-MEMR
-lOW
-lOR
-OACK3
+OR03
-OACK I
-ORQI
-OACKO
CLK
+IRQ1
+IRQ6
.IRQ5
+IRQ4
+IRQ3
-OACK2
+T/C
+AlE
+5VIIC
OSC
GROUND
,
B1
82
B3
84
85
"87
'8
89
810
811
812
813
91.
'15
'16
817
818
."
."
AZ
A3
A.
A5
A6
A7
A8
AQ
AIO
.11
A12
A13
A14
A15
A16
A17
Al8
Al9
820
AZO
All
822
823
'24
825
A22
A23
A24
A25
Al8
."
."
828
829
830
831
~
"
I~~~~~~~~~~
Al
A27
Al8
A26
'30
431
~E
EO
1;»~
Prototype Card {Sheet 1 of 1)
__--oEI1
-liD DECODE
[300 "EX-3-lf MEXINCLUSIVEI
-IJO CHANNEl CHECK
+OATABIT7
+DATA BIT 6
·DATABIT5
'OATABIT4
+OATA BIT 3
+OATA BIT 2
+OATABITI
+DATA BIT 0
+1/0 CHANNEL READY
·AEN
+ADDRESSBIT 19
+ADDRESSBITI8
+ADDRESSBITI1
+ADDRESSBIT 16
+AODRESSBIT15
+AOORESSBITI4
+ADDRESSBIT 13
+AODRESSBIT 12
+ADDRESS BIT 11
+ADORESSBIT10
+ADDRESS BIT 9
+ADDRESSBIT B
+ADDRESSBIT 7
ADDRESS BIT 6
ADDRESS BIT 5
ADDRESS BIT 4
ADDRESS BIT 3
ADDRESS BIT 2
ADDRESS BIT 1
ADDRESS BIT 0
10 Prototype Card
-------------
- --- -- -- --
Personal Computer
Hardware Reference
Library
IBM Personal Computer
Data Acquisition and
Control Adapter
Distribution Panel
Technical Reference
6138157
August 15, 1984
© Copyright IBM Corporation 1984
IBM Personal Computer Data
Acquisition and Control Adapter
Distribution Panel
The IBM Personal Computer Data Acquisition and Control (Data
Acquisition) Adapter Distribution Panel, with attached ribbon
cable and 60-pin connector, is provided for external access to the
Data Acquisition Adapter's analog I/O device, binary I/O device,
and timer/counter device.
Four 22-screw terminal strips on the Distribution Panel allow the
user to connect external devices to the Data Acquisition Adapter.
/
///
August 15,1984
© Copyright IBM Corporation 1984
1
Following is a diagram of the distribution panel.
®
@
0
0
DGND
D GND
BI CTS
BOO
BID
D GND
BO 1
Bll
D GND
B02
BI2
BOCTS
B03
BI3
D GND
D GND
DGND
BO
STROBE
BO'
BI'
D GND
B05
BI5
D GND
BI
STROBE
B06
BI6
B07
BI7
DGND
D GND
D GND
DELAY
OUT
B08
BI8
D GND
B09
BI9
DGND
BO 10
Bll0
RATE
OUT
BO 11
Bill
D GND
D GND
D GND
8012
BI12
D GND
BO 13
BI13
D GND
BO 1.
Bll'
COUNT
OUT
B015
8115
DGND
D GND
D GND
DGND
iRQ
@
2
0
®
August 15, 1984
© Copyright IBM Corporation 1984
The following shows the signals at the distribution panel and the
connector pins on which they appear.
2
00
§B
gg
~g
00
g§
00
00
00
00
00
00
00
00
Ii
gB
60
DO
DO
59
S·19na IN arne /D escnptlon
Distribution
Panel
In
DIA 1
1
DIA 0
+10V REF
2
AGND
AID 0AID 0+
AID 1AID 1+
AID 2AID 2+
AID 3AID 3+
AGND
AID CE
D GND
AID CO
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BI8
17
808
BI9
18
BO 9
BI 10
BO 10
B I 11
BO 11
BI 12
BO 12
Distribution
Panel
Connector
19
20
21
22
23
24
25
26
BI 13
27
B013
28
BI 14
B014
29
30
Part 1 of 2
August 15, 1984
© Copyright IBM Corporation 1984
3
2
DC
DO
CO
~~
CD
DO
DO
CD
DO
DO
00
DO
DO
DO
CC
DO
§g
i~
DO
DO
60 gg 59
Distribution
Panel
S·Igna IN arne /D escrrptlon
BI 15
B015
BI HOLD
BO GATE
BIO
BO 0
BI 1
BO 1
BI2
BO 2
BI3
BO 3
BI4
B04
BI5
BO 5
BI6
BO 6
BI 7
BO 7
RATE OUT
DELAY OUT
BISTROBE
BO STROBE
BO CTS
BICTS
IRQ
COUNT OUT
COUNT IN
D GND
p.In
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Distribution
Panel
Connector
Part 2 of 2
4
August 15, 1984
© Copyright IBM Corporation 1984
---- --------------
--
Personal Computer
Hardware Reference
Library
Prototype Adapter
Contents
Description .................................... 1
Adapter Design ............................. 3
IBM Personal Computer AT Prototype Adapter
Layout .................................. 7
Interfaces .................................... 13
Logic Diagrams ................................ 14
iii
Notes:
iv
Description
The IBM Personal Computer AT Prototype Adapter is 121.9
millimeters (4.8 inches) high by 333.25 millimeters (13.12 inches)
long and plugs into any system-unit expansion slot except number
1 or 7. Two card-edge tabs, one 2- by 31-position and one 2- by
18-position, provide all system control signals and voltages.
The adapter has a voltage bus (+5 Vdc) and a ground bus (0
Vdc). Each bus borders the adapter, with the ground bus on the
component side and the voltage bus on the pin side. A system
interface is also provided on the adapter with a jumper to specify
whether the device has an 8- or a 16-bit data bus.
This adapter also accommodates a D-shell connector from 9 to 37
positions.
Note: All components must be installed on the component
side of the adapter. The total width of the adapter, including
components, may not exceed 12.7 millimeters (0.5 inch). If
these specifications are not met, components on the IBM
Personal Computer AT Prototype Adapter may touch other
adapters plugged into adjacent expansion slots.
August 31, 1984
Personal Computer AT Prototype Adapter 1
>...,
...,::r'
('b
Bit 0-7 Data Bus
liD ReadlWrite
Spare
Address Bit 0
Address Bit 2
Address Bit 3
Address Bit 9
-/
~
-
-r
t!-
8
Bus Direclion
Command
and
Address
BuHer
-
'"0.....,
Data Bus
BuHered
Data Bus
Blls 0-7
>of
0
o .....
o..... :;;
0
'< .....
'0 ::l
Bus Transceiver
('b(JQ
>tii·
o..~
~c:T
'0_
.... 0
Address Bit 0
$!l (")
~
Address
BuHer
liD Address
Decode
Logic
6
Z
~
liD Decode
(Hex 300-31F Inclusive)
Data Bus
Enable Logic
0..
.....
~
(JQ
>of
Low Bus Enable
~
S
High Bus Enable
0
.....,
.....
Address Enable -
::r'
('b
Spare
Memory ReadlWrite
~
Bus Direction
System High Byte Enable
Buller
Bus
Transceiver
~
Bit 8-15 Data Bus
Data Bus
i
1
BuHered
Data Bus
Bits 8-15
t:C
~
'"0
('b
>of
til
0
::l
+S
~
8
IOKn
+8 Bit/-16 Bit Data Bus
e:-
n
0
S
Jumper Jl
'0
~
....
('b
>of
Prototype Adapter Block Diagram
Adapter Design
The following information is provided to assist in designing an
adapter using the IBM Personal Computer AT Prototype
Adapter.
Designing an Input/Output Adapter
The following information may be used to design an input/output
type of adapter.
Programming
Insert a Jump instruction after all I/O read (lOR) or I/O write
(lOW) assembler language instructions to avoid a potential timing
problem caused by slow I/O devices. The following figure shows
a typical programming sequence.
Before
After
Your Code
lOR
Your Code
NEXT:
Your Code
lOR
JMP NEXT
Your Code
Program Sequence
Jumper Wire (J1)
Your design can use either 8 bits of the data bus (jumper off) or
the full 16 bits of the data bus (jumper on). Most devices have
8-bit data buses.
Wait-State Generator Circuits
If your device runs too slow, you must add a wait-state generator
to make the II 0 read and write signals longer. First, determine
the time needed by your device from the start of an lOR signal
until it can put data on the system's data bus. Next, compare that
August 31, 1984
Personal Computer AT Prototype Adapter 3
time with the time given by the system's microprocessor. The
system microprocessor gives 750 nanoseconds for 8-bit devices
and 250 nanoseconds for 16-bit devices.
A similar problem may exist for an lOW signal. Determine the
write data setup time, which is the time required by your design
from the time it is given valid data until it is told to take this data
by the lOW signal. The time given by the system microprocessor
from when data is first valid to the device until the lOW signal
goes active and then inactive is shown in the following figure.
Your design can take the data when lOW goes active (less setup
time) or when lOW goes inactive (more setup time).
a-Bit Device
16-Bit Device
Description
100 ns
850 ns
100 ns
350 ns
Data Valid Until lOW is Active.
Data Valid Until lOW is Inactive.
lOW Timing
If the time given by the system microprocessor is not enough, you
must add a wait-state generator circuit that will provide longer
lOR and lOW signals. A recommended wait-state generator
circuit is shown in the following figure.
Note: Pulse Engineering Inc. PE21214 is the delay module
used.
4 Personal Computer AT Prototype Adapter
August 31, 1984
c>
ctI>
(JCl
-........
W
~
+ liD Cycle
Time Oala, (lote)
Time Delay (Note)
Time Oalay (lote)
PE21214
PE21214
PE21214
.1.
r - - ...L
r - - .1.
12 4
6
10
8
12
I
I.e
~
,I
g
iii'
oc
.:
•
12
8
4
10
6
8
I
g
z
ClIO
CI
6
...
w
ClIO
CI
10
I
QC
8z
4
z
ClIO
CI
•
!!.
iii'
oc
2
4
3
;1\
f
i Jum3Per
74 S74
tcLK
74ALS244
Of=5'--_ _ _ _ _ _ _--"15::.;
L------------~~~Reset
+ 51 o-~---...:..4a Set
L---.i:
D
Wait-State Generator Circuit
08
~5_ _ _
+ 110 Channal Raady
Note: To add wait states and increase the time given by the
microprocessor for I/O Read and Write commands, install
one of the following jumpers.
•
•
16-Bit Design
1 wait state
250 nanoseconds--No jumper
2 wait states
417 nanoseconds--Jumper 1 to 5
3 wait states
583 nanoseconds--Jumper 2 to 5
4 wait states
750 nanoseconds--Jumper 3 to 5
5 wait states
917 nanoseconds--Jumper 4 to 5
8-Bit Design
4 wait states
750 nanoseconds--No Jumper
5 wait states
917 nanoseconds--Jumper 4 to 5
Designing a Memory Adapter
The following information may be used to design a memory
adapter.
Control Lines
There are two sets of memory control lines.
-SMEMR for
system-memory read, and -SMEMW for system-memory write.
They are active when accessing memory in the first megabyte
(address bits 20 through 23 are all off). If you use these lines,
you can avoid an address decode circuit that checks for address
bits 20 through 23 being off.
I
I
I
I
The other set of control lines is MEMR and MEMW
These are active when addressing all memory locations. If you
wish to design memory that will answer to addresses above the
I -
I
6 Personal Computer AT Prototype Adapter
I -
I •
August 31, 1984
first megabyte, you must use these lines and decode address bits
20 through 23 to select the particular address range your memory
occupies.
System Address Lines (SA)
The 20 lowest-order address lines are 'SAO' through' SA19'.
SA address bits are active a minimum of 30 nanoseconds before a
control line goes active, and they stay active a minimum of 66
nanoseconds after the control line goes inactive. Timings are at
the adapter socket.
Local Address Lines (LA)
There are seven high-order address lines called 'LA17' through
'LA23'. LA address bits are active a minimum of 159
nanoseconds before a control line goes active, and they typically
stay active 83 nanoseconds before the control line goes inactive.
LA bits should be decoded to select the particular address range
your memory occupies. Because this decode will go inactive 83
nanoseconds before the control line goes inactive, it may be
necessary to latch the decode. The output of this decoder circuit
should be connected to the input of a transparent latch, such as a
74ALS573 (+BALE should be connected to the clock pin on the
latch). If this is done, the output of the 74LS573 will be active
approximately 30 nanoseconds before a control line goes active,
and will stay active approximately 66 nanoseconds after the
control line goes inactive. Timings are at the adapter socket.
IBM Personal Computer AT Prototype
Adapter Layout
The IBM Personal Computer AT Prototype Adapter has two
layers screened onto it: one on the front and one on the back. It
also has 4,311 plated through-holes that are 10.1 millimeters
(0.04 inch) wide and have a 1.52-millimeter (0.06-inch) pad.
These holes are arranged in a 2.54-millimeter (O.l-inch) grid.
There are 37 plated through-holes, 1.22 millimeters(0.048 inch)
wide, on the rear of the adapter that are used for a 9- to
37-position D-shell connector. The adapter also has 5 holes that
August 31, 1984
Personal Computer AT Prototype Adapter 7
are 3.18 millimeters (0.125 inch) wide. One of these is just above
the two rows of D-shell connector holes, and each of the other
four is in a corner of the adapter.
8 Personal Computer AT Prototype Adapter
August 31, 1984
Component Side
The component side of the adapter has a ground bus, 1.27
millimeters (0.05 inch) wide screened onto it and two card-edge
tabs labeled Al through A31 and C 1 through C31. The following
figure shows the ground bus and card edge-tabs.
August 31, 1984
Personal Computer AT Prototype Adapter 9
The component side of the adapter also has a silk screen printed
on it that may be used as a component guide for the I/O
interface. The following figure shows this silk screen.
:;
M
::::J
N
::::J
~
::::J
08
Lt"l
CD
::::J
sl
Du
5D~
c::::JC:::::=:S
::::J
5I
sOc::;
r-
::::J
5D~
co
::::J
DiS
5
0>
::::J
00
5
DB
10 Personal Computer AT Prototype Adapter
August 31, 1984
Pin Side
The pin side of the adapter has a 5-Vdc bus, 1.27 millimeters
(0.05 inch) wide, screened onto it, and two card-edge tabs:
labeled B 1 through B31 and D 1 through D 18. The following
figure shows the 5-Vdc bus and card edge-tabs.
o
August 31, 1984
Personal Computer AT Prototype Adapter 11
Card-Edge Tabs
Each card-edge tab is connected to a plated through-hole by a
0.3-millimeter (0.012-inch) land. Four ground tabs are
connected to the ground bus by four 0.3-millimeter (0.012-inch)
lands, and three 5 V dc tabs are connected to the 5-Vdc bus by
three O.3-millimeter (0.012 inch) lands.
Additional InCormation
Additional information regarding the I/O interface may be found
under I I/O Channell in Section 1 of IBM Personal Computer AT
Technical Reference manual. Logic diagrams of the IBM Personal
Computer AT Prototype Adapter may be found later in this
section. If the recommended interface logic is to be used, the
following figure shows the recommended components and their
TTL numbers.
Component
U1
U2
U3, U9
U4
U5
U6, U7, U8
Cl, C6
TTL #
74500
74510
74L5245
745139
745138
74AL5244
C2, C3, C4, C5,
C7,C8
R1
J1
Description
Quad 2 Input NAND
Triple 3 Input NAND
Octal Bus Transceiver
Dual 1 of 4 Decoder
1 of 8 Decoder
Octal Buffers
10-Microfarad Tantalum
Capacitor
0.047-Microfarad Ceramic
Capacitor
10 Kohm, .25-Watt, 10%
Resistor
(Axial Leads)
Jumper Wire
Recommended Components
Note: n, U8, and U9 are not required for a design using
only the low-order 8 bits of the data bus. Designs using all
16 bits of the data bus require these components.
12 Personal Computer AT Prototype Adapter
August 31, 1984
Interfaces
Internal Interface
Because of the number of adapters that may be installed in the
system, I/O bus loading should be limited to 1 Schottky TTL
load. If the recommended interface logic is used, this requirement
is met. Power limitations may be found under I Power Supply I in
the IBM Personal Computer AT Technical Reference Manual.
External Interface
The following figure lists the recommended connectors for the
rear of the adapter.
Connector
Part no. (Amp) or
Equivalent
9-Pin D-Shell (Male)
9-Pin D-Shell (Female)
15-Pin D-Shell (Male)
15-Pin D-Shell (Female)
25-Pin D-Shell (Male)
25- Pin D-Shell (Female)
37-Pin D-Shell (Male)
37-Pin D-Shell (Female)
205865-1
205866-1
205867-1
205868-1
205857-1
205858-1
205859-1
205860-1
Recommended Connectors
August 31, 1984
Personal Computer AT Prototype Adapter 13
I.
I.
I."
74LS24"
(SHT 3)
(SHT 3)
(SHT3)
(SHT3)
(SHT 3)
(SHT3)
(SHT3)
(SHT3)
(A9) + DATA BIT 0
(AS) + DATA BIT I
(A7) + DATA BIT 2
(Ab) + DATA BIT ,
(A'» + DATA BIT 4
(A4) + DATA BIT '5
(A,) +DATA BIT 6
(A2)
+ DATA
BIT 7
A
A
17
A "'
A
A
A
q A
A
"
•
12
(HEX) ,00
(HEX)'31 F
D[COPf RANGE
BUFFERED
DATA BUS
BITS 0-7
110 DECODE FOR PROTOTYPE CARD
A9A A7Af>Ar; 4A
AI
I I 0 0 0 a 0 0 0 0
I I 0 0 0 I I I I I
I I 0 0 0 x x x x x
"
L~=:~~===========r=-=E=N~==LE==W=W=B=V=TE~==============================~=======3============: +-8JOR
liD CYCLE
(SHT
(SHT
(SHT
(SHT
3)
3)
3)
3)
(SHT 3)
(SHT 3)
(SHT 3)
(SHT3)
(SHT 3)
(SHT 3)
(SHT3)
(SHT 3)
(SHT 3)
(SHT3)
(SHT 3)
(8m -lOW
(BI2) -SMEMR
(811) -SMEMW
(814)
-lOR
(SPARE)
(A'I)+ADDR.BITO
!;~~~~~~~
(A ,0) + ADDR. BIT I
(A29) + ADDR. BIT 2
(A27) + ADDR. BIT 4
+ ADDR. BIT '5
(A2,)
ADDR. BIT b,
(A28) +
+ADDR.
(A24) + ADDft BIT 7
(Alb)
~:~~;:=~:
(AII)+AEN
' - - - - - - - - - - - - - - - - - - - - - - > + 8 BIT I/O DEVICE (SHT2)
7451,S
I~~~~~~~!
u,
1Jt:====tl!?
~====::::j:==:",~ ENl
ENz
A2
:i
'----'1""
p..u___
~----------------
=
=
'11
7
W
.....
10
20
+'5V
(4
NOTES:
1
____________>
-I/O DECOOE
(SHT 2)
(100 HEX-3IF HEX INCLUSIVE)
>
IJQ
(SHT 2)
(SHT 2)
IF THE I/O DEVICE REQUIRES A 16 BIT WIDE
DATA BUS. THEN INSTAll JUMPER JI. FOR
8 BIT WIDE I/O DEVICES NO JUMPERING
IS REQUIRED.
Prototype Adapter (Sheet 1 of 4)
>
=
=
-
(JQ
rIJ
W
~
74L5Z4~
(SHT4)
(SHT4)
(SHT4)
(SHT4)
(SHT4)
(SHT4)
(SHT4)
(SHT4)
(C II) +DATA BIT B
(CIZ) +OATA BIT q
(CI3) +OATA BIT 10
(CI4) +OATA BIT II
(CI5) +OATA BIT IZ
(Clb) +OATA BIT 13
(CI7) +OATABIT 14
(CIB)+OATA BIT I~ ,
~
I.C
QCl
(SHT1)
-BIOR
q
B : U9
7
A
b A
~
4 A
A
3
A
A
)."""
DATA BUS
BITS B-I~
I
OIR
I'l
G
"'"
- ENABLE HIGH BYTE
(SHT 1)
IZ
13
+ I/O CYCLE
(SHT 1) + B BIT I/O DEVICE
>-__~______________________________2+~8~BI~T~OE=V~I~CE~~
r=-c;,S.!!BH!1!E'----.1.
14SJ~q
Z'
U4
74ALSZ44
(SHT 4)
(SHE.~)
(SHT4)
(C I) - SBHE
(C q) SPARE
(CIO) SP~~~
4
6
I
14
IB
12
U8
Z
8
Ie;
ZO
+~V
10
C7
74ALSZ~~
L ____________________________________---=\-__________________c:.+.\!.B..JB>!I-LT-'O"'ELVI"'C"-E---------'-13'-1
-1/0 DECODE
(SHT 1)
- I/O DECOIlE
Prototype Adapter (Sheet 2 of 4)
19
U8
G
f-7'----___________ -I/O CS Ib (OOZ) (SHT 4)
GROUND
+RESET DRV
+SVDC
+IRQ 9
BI
B2
B,
-SVDC
BS
A4
AS
+DRQ 2
-12VDC
+ 0 WAIT STATE
+12 VDC
(SHT1)
GROUND
Bb
B7
88
B9
Ab
A7
A8
A9
BIO
AIO
(SHT 1) -SMEM W
-SMEMR
-lOW
BII
BI2
BI,
All
.tIZ
814
AI4
.lIS
+ ADDRESS
BIT 17
BIS
+ ADDRESS
BIT 16
Bib
Alb
+ADDRESS BIT IS
+ ADDRESS
+ ADDRESS
+ADDRESS
+ADDRESS
BIT 14
BIT
BIT 12
BIT II
+ ADDRESS
BIT
(SHT1)
(SHT1)
t
(SHT 1)
B4
-lOR
-DACK
+DRQ
~
~
AI
-I/O CHANNEL CHECK
A2
+DATA BIT 7
+DATA BIT b
+DATA BIT I)
A,
+DATA BIT 4
+DATA Bin
+DATA BIT 2
+ DATA BIT I
.11
817
AI7
AI8
ClK
+IRQ 7
8Z0
811
AZO
All
+IRQ b
821
+IRQ S
Bl~
AZZ
AZ,
+ ADDRESS BIT
+ ADDRESS BIT
AI'I
(SHT 1)
"
+IRQ 4
BZ4
81S
AZ4
AZS
+ADDRESS Bn
+ IRQ,
+ ADDRESS
BIT
-DACK 2
Alb
AZ7
+ ADDRESS
BIT
+ TIC
81b
817
+BAlE
811
AZB
+AqDRESS BIT
+ ADDRESS BIT
(SHT 1)
+SV DC
82q
AZ9
+ ADDRESS BIT
(SHT 1)
OSC
GROUND
810
8,1
"0
A1I
+ ADDRESS BIT
+ ADDRESS BIT
PIN SIDE
(SHT 1)
+DATA BIT 0
+1/0 CHANNEL READY
+AEN
+ADDRESS BIT 19
+ ADDRESS BIT 18
818
81q
- DACK I
-DRQ I
-REFllESH
(SHT 1)
10
q
(SHT 1)
8
,
4
(SHT 1)
COMPONENT SIDE
Prototype Adapter (Sheet 3 of 4)
16 Personal Computer AT Prototype Adapter
August 31, 1984
~
-
'3b PIN
TAB CONNECTOR
rJ'Q
=
fIJ
....
....
W
~
~
OC
.&;..
~
...
§
fIJ
!..
(""}
Q
:g
(SHT2)
DI
D2
D'3
D4
DI)
-MEM CSlb
-I/O CSlb
+ IRQ 10
+IRQ II
+ IRQ 12
+ IRQ 1'3
+ IRQ 14
-DACK 4
+DRQ 4
-DACK I)
+DRQ I)
-DACK b
+DRQ b
-DACK 7
+DRQ 7
+I)VDC
-MASTER
GND
Db
D7
D8
D9
DIO
DII
DI2
DI'3
DI4
DII)
Ib
DI7
DI8
CI
C2
+
+
+
+
+
C'3
C4
CI)
Cb
C7
C8
C9
CIO
CII
CI2
CI'3
CI4
CII)
Ib
CI7
CI8
+
+
+
+
+
+
+
+
+
+
=
it
...
>
0-3
i
-....
~
E
PIN SIDE
COMPONENT SIDE,.
Q
~
>
~
...
~
......
Prototype Adapter (Sheet 4 of 4)
SBHE
LA ADDRESS
LA ADDRESS
LA ADDRESS
LA ADDRESS
LA ADDRESS
LA ADDRESS
LA ADDRESS
MEMR
MEMW
DATA BIT 8
DATA BIT 9
DATA BIT 10
DATA BIT II
DATA BIT 12
DATA BIT 1'3
DATA BIT 14
DATA BIT II)
(SHT2)
BIT 2'3
BIT 22
BIT 21
BIT 20
BIT 19
BIT 18
BIT 17
(SHT2)
(SHT2)
(SHT2)
(SHT2)
(SHT2)
(SHT2)
(SHT2)
(SHT2)
(SHT2)
(SHT2)
Notes:
18 Personal Computer AT Prototype Adapter
August 31, 1984
---- --- -- --------_.- - ----
Personal Computer
Hardware Reference
Library
mM PC Compact
Printer Connector
Adapter
6361517
ii
Contents
Description .................................... 1
Specifications .................................. 3
ill
iv
Description
The IBM PC Compact Printer Connector Adapter is required to
connect the 16-lead cable of the IBM PC Compact Printer to the
2S-pin D-shell connector of an Asynchronous Communications
Adapter or Alternate Asynchronous Communications Adapter.
Connector Adapter 1
2 Connector Adapter
Specifications
14
BOl
o
AOl
o ~
~
@]@]
@]@]
@]@]
@]@]
@]@]
@]@]
o
o
o
o
o
o
B08~A08
r
)
..
Compact
Printer
Cable
Receive Data
Request To Send
4
Not Used
A04
A08
A03
A07
A06
B02
B03
Transmitted Data
rB06
rB07
rB08
A05
r---
Pin
1
2
3
-
Clear To Send
Data Set Ready
Signal Ground
Received Line Signal Detector
+ Transmit Current Loop Data
B05
IBM PC
System End of
Connector Adapter
Description
~
r
-
Not Used
- Transmit Current Loop Data
Not Used
IBM PC
Compact
Printer
Connector
Adapter
Not Used
Not Used
Not Used
Not Used
ADl
Not Used
5
6
7
8
9
10
11
12
13
14
15
16
Not Used
17
+ Receive Current Loop Data
18
19
20
21
22
23
24
25
Not Used
AD2
0
0
0
0
0
0
13~25
Printer Cable End
of Connector Adapter
Pin
g
Data Terminal Ready
Not Used
Ring Indicator
Not Used
801
Not Used
Not Used
Receive Current Loop Return
Asynchronous
Communication
Adapter
(RS·232C)
Connector Adapter 3
Notes:
4 Connector Adapter
-----E : ::E~:'
Personal Computer
Hardware Reference
Library
mM Communications
Adapter Cable
6361515
ii
Contents
Description .................................... 1
Specifications .................................. 3
iii
iv
Description
The IBM Communications Adapter Cable is a 3.05 m (lO-ft)
cable designed to connect an IBM communications adapter to a
modem or other RS232-C data communications equipment
(DCE). It is fully shielded and provides a high quality, low noise
channel for interface between the communications adapter and
DCE.
The connector ends are 25-pin D-shell connectors. All pIn
connections conform with the EIA RS232-C standard. In
addition, connection is provided on pins 11, 18, and 25. These
pins are designated as 'select standby,' 'test,' and 'test indicate,'
respectively, on some modems. 'Select standby' is used to support
the switched network backup facility, if applicable. 'Test' and
'test indicate' support a modem wrap function on modems
designed for business-machine controlled modem wraps.
Communications Cable 1
2 Communications Cable
Specifications
The following page shows the pin locations and specifications for
the IBM Communications Adapter Cable.
Communications Cable 3
The IBM Communications Adapter Cable connects the following
pins on the 25-pin D-shell connectors.
14
14
Modem
Connector
Communications
Adapter
Connector
13
Communications
Adapter Connector
Pin #
Name
5
Outer Cable Shield
Transmitted Data
Received Data
Request to Send
Clear to Send
6
7
8
Data Set Ready
Signal Ground (Inner Lead Shields)
Received Line Signal Detector
NC
2
3
4
Select Standby
Transmitter Signal Element Timing
Receiver Signal Element Timing
Test
Data Terminal Ready
Ring Indicator
Data Signal Rate Selector
15
17
18
20
22
23
NC
NC
25
11
NC
NC
22
23
5
6
7
8
NC
NC
20
4
NC
NC
17
18
1
2
3
NC
NC
NC
NC
NC
NC
15
Modem
Connector
Pin #
NC
NC
NC
NC
11
13
25
25
Test Indicate
Connector Specifications
4 Communications Cable
25
---------- ----_
.-
--
Personal Computer
Hardware Reference
Library
IBM Personal Computer
AT Communications
Cable
Contents
Description .................................... 1
Specifications .................................. 2
iii
Notes:
iv
Description
The IBM Personal Computer AT Communications Cable cable is
for connection of an IBM communications adapter with a 9-pin
D-shell connector to a modern or other RS-232C DCE (data
communications equipment). It is fully shielded and provides a
high quality, low noise channel for interface between the
communications adapter and DCE.
August 31, 1984
Personal Computer AT Communications Cable 1
Specific a tions
One connector is a 9-pin D-shell connector and the other is a
25-pin D-shell connector. The pin numbering and connector
specifications follow.
14
COco
COco
co en
6
Modem
Connector
Or Other RS-232
Data Communications
Equipment
~§~ ~
com
mm
Communications
Adapter
Connector
t=-
CllQ)
Cll
13
25
25-Pin
D-Shell
Connector
9-Pin
D-Shell
Connector
-
r--
8
Carrier Detect
1 __
3
Received Data
2 ..
_2
Transmitted Data
3
-
Data Terminal Ready
4
Signal Ground
5
Data Set Ready
6 ..
Request To Send
7 -
5
Clear To Send
8 ..
22
Ring Indicator
9_
-
. . 20
DCE
25-Pin
Connect or
9
5
6
__ 4
-
-
-
A DAPTER
9- Pin
C onnector
-
'---
Note: All other pins on the 25-pin connector are not used.
August 31, 1984
2 Personal Computer AT Communications Cable
--- -- ----- -- -----.-
----
The Personal Computer
Hardware Library
Reader's Comment Form
Technical Reference
Options and Adapters
6137806
Your comments assist us in improving the usefulness of our
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IBM Personal Computer family of products or programs for the
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Comments:
IIIIII
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aJa~
adeJ.
aldelS
IOU
PIO:J
op aseald
~rlPI
UPDATE NUMBER 5
for the
IBM Technical Reference
Options and Adapters
(Part Number 6322509)
Note: All updates received prior to Update Number 5 must
be inserted before continuing.
If you have an IBM Personal Computer AT Technical Reference
manual, replace the following modules in your manual. If you
do not have an IBM Personal Computer AT Technical Reference
manual, insert the following modules in your manual.
1.
"Adapters" section:
•
IBM Personal Computer AT Serial/Parallel Adapter
•
IBM Personal Computer AT Fixed Disk and Diskette
Adapter.
2.
In the "Cables and Connectors" section, insert or replace the
IBM Personal Computer AT Communications Cable module.
3.
"Memory Expansion" section:
•
IBM Personal Computer AT 128KB Memory Expansion
Option
•
IBM Personal Computer AT 512KB Memory Expansion
Option.
August 31, 1984
4. In the "Miscellaneous" section, insert or replace the IBM
Personal Computer AT Prototype Adapter module.
5.
"Storage Devices" section:
•
IBM Personal Computer AT High Capacity Diskette
Drive
•
IBM Personal Computer AT Double Sided Diskette
Drive
•
IBM Personal Computer AT 20MB Fixed Disk Drive.
August 31, 1984
----- ---
---- ----==-=~=®
International Business Machines Corporation
P.O. Box 1328-W
Boca Raton, Florida 33432
6137806
Printed in United States of America
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