The_Designers_Guide_to_Programmed_Logic_for_PLS_400_Systems_Aug73 The Designers Guide To Programmed Logic For PLS 400 Systems Aug73
The_Designers_Guide_to_Programmed_Logic_for_PLS_400_Systems_Aug73 The_Designers_Guide_to_Programmed_Logic_for_PLS_400_Systems_Aug73
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TO PROGRAMMED LOGIC
For PLS 400 Systems
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THE DESIGNERS GUIDE
°""4""""1:;0
PRO-LOG CORPORATION
852 Airport Road
Monterey, California
-
-~-
THE
DESIGNERS GUIDE
TO PROGRAMMED LOGIC
For PLS 400 Systems
Written by
Matt Biewer
PRO-LOG CORPORATION
852 Airport Road
Monterey, California
Price: $10.00
15 August 1973
TABLE OF CONTENTS
SUMMARY
1-1
ROM Program Memory
RAM Register Storage
Input/Output
1-3
1-3
1-3
PLS 400 HARDWARE
2-1
PLS 401 Data Sheet
PLS 402 Data Sheet
PLS 403 Data Sheet
2-2
2-4
2-6
TIMING AND DEVICE DATA SHEETS
3-1
Timing
Device Data Sheets
3-1
3-3
PLS 400 SYSTEM ORGANIZATION
4-1
Central Processing Unit
PLS 400 Systems
Instruction Register
Program Address Counter
Subroutine Address Stack
Index Registers
Arithmetic Logic Unit
Program Memory
ROM Program Memory
RWM Program Memory
RAM Register Storage
Inputs and Outputs
Hexadecimal Notation
4-1
4-1
4-1
4-3
4-3
4-4
4-4
4-5
4-5
4-5
4-7
4-7
4-9
5.
INSTRUCTION TABLE
5-1
6.
INSTRUCTION DESCRIPTIONS
6-1
No Operation
Jump On Condition
Fetch Immediate
Send Register Control
Fetch Indirect
Jump Indirect
Jump Unconditional
6-1
6-1
6-2
6-2
6-4
6-4
6-5
1.
2.
3.
4.
i
TABLE OF CONTENTS
7•
ii
(Cont)
Jump to Subroutine
Increment Register
Increment Register Skip if Zero
Add Register to Accumulator
Subtract Register from Accumulator
Load Register to Accumulator
Exchange Register with Accumulator
Branch Back and Load Accumulator
Load Data to Accumulator
write Accumulator into RAM Character
write Memory Port
write ROM Port
Write to Program Memory
write into RAM Status Character 0
Write into RAM Status Character 1
Hrite into RAM Status Character 2
write into RAM Status Character 3
Subtract from Memory with Borrow
Read RAM Character
Read ROM Port
Add from Memory with Carry
Read RAM Status Character 0
Read RAM Status Character 1
Read RAM Status Character 2
Read RAM Status Character 3
Clear Both
Clear Carry
Increment Accumulator
Complement Carry
Complement Accumulator
Rotate Left
Rotate Right
Transmit Carry and Clear
Decrement Accumulator
Transfer Carry Subtract
Set Carry
Decimal Adjust Accumulator
Keyboard Process
Designate Command Line
6-5
6-6
6-6
6-6
6-7
6-8
6-8
6-8
6-9
6-9
6-10
6-10
6-10
6-11
6-11
6-11
6-11
6-12
6-12
6-12
6-12
6-12
6-13
6-13
6-13
6-13
6-13
6-13
6-13
6-14
6-14
6-15
6-15
6-15
6-15
6-16
6-16
6-16
6-17
IMPLEMENTING PROGRAMMED LOGIC
7-1
System Block Diagram
Flow Charts
Register Maps
Hex Coding Form
PLS Design Example
7-J.
7-3
7-4
7-6
7-8
TABLE OF CONTENTS
8.
(Concluded)
PROGRAMMING APPLICATIONS
8-1
Subroutines
Counting
Time Delays
Compare Subroutines
Logical Operations
Addition
Multiplication
Square Root
Teletype
8-7
8-12
8-18
8-20
8-23
8-24
8-27
8-31
8-1
APPENDIX A
Symbols and Definitions
A-I
APPENDIX B
Table of Powers of Two
B-1
APPENDIX C
Hexadecimal/Decimal Integers
C-l
APPENDIX D
Hexadecimal/Decimal Fractions
D-l
APPENDIX E
Table of Powers of Sixteen
E-l
APPENDIX F
Conversion Tables
F-l
LIST OF TABLES
4-1
RAM Addressing
4-7
4-2
Hexadecimal Notation for Sixteen Combinations
4-9
6-1
I/O Port and RAM Selection for One Bank by Even
Register Contents, as Used with SRC Instruction
6-3
8-1
Number of Steps Gained or Lost When a Routine
is Executed as a Subroutine
8-3
8-2
ISZ Register Settings for "N" Operations
8-10
8-3
Delay Time Using Cascaded ISZ Instructions
8-13
8-4
Boolean Laws of Operation for 0 and 1
8-20
iii
LIST OF ILLUSTRATIONS
1-1
3-1
3-2
3-3
4-1
4-2
4-3
4-4
4-S
7-1
7-2
7-3
7-4
7-S
7-6
7-7
7-8
7-9
8-1
8-2
8-3
8-4
8-S
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-lS
8-16
8-17
8-18
8-19
8-20
8-21
8-22
8-23
8-24
iv
PLS-400 Programmed Logic System Application
CPU Instruction Timing for Most Instructions
CPU Timing for SRC Instruction
CPU Timing for I/O and RAM Register Instructions
PLS-400 System Data Flow
Instruction Register, Program Address Counter,
and Subroutine Address Stack
Index Registers
Organization of Program Memory as Defined by
the CPU Instructions
RAM Index Register
System Block Diagram
Flow Chart
Register Maps
Hex Coding Form
Instruction and Operand Examples
Electronic Calculator Block Diagram
First Level Flow Chart
Flow Chart for Keyboard Scan
Flow Chart for Key Process
Example Showing how a Subroutine can be Used Many
Times From Various Places in a Routine
Example Showing Nesting of Subroutines
Example of a Subroutine with Multiple Endings
Example of Subroutines Sharing a Cornmon
Ending Sequence (Stacking)
Flow chart of Execute and Count
Flow Chart of Count and Execute
Subroutine to Count Three Decimal Decades
Flow Chart of Short Delay
Flow Chart of Longer Delay
Flow Chart of Control Timeout
Flow Chart of Holdover
(Compare) Four Bits
(Compare) Eight Bits
Logical Operations
Multiple Precision Addition
Brute-Force Method of Multiplication
Long-Hand Method of Multiplication
Example of Decimal Long-Hand Square Root
Example of Binary Long-Hand Square Root
Flowchart for Long-Hand Square Root
Teletype Interface
TTY Data Line Format
TTY Character Set
Flow Chart for TTY Read Without Echo
1-2
3-1
3-2
3-3
4-2
4-3
4-4
4-6
4-8
7-2
7-3
7-S
7-7
7-8
7-9
7-10
7-11
7-13
8-2
8-4
8-S
8-6
8-8
8-8
8-11
8-14
8-lS
8-16
8-17
8-18
8-19
8-22
8-23
8-24
8-26
8-27
8-27
8-28
8-32
8-34
8-3S
8-36
1.
SUMMARY
PLS 400 systems are micro-programmable processing systems suitable
for implementing random logic, and numeric and small alpha numeric
data handling applications. As shown in Figure 1-1, the PIJS-400
system consists of a CPU, RAM register storage, ROM program memory,
and input/output ports. The CPU is an Intel 4004 CPU chip, P~M
registers are the Intel 4002 circuits, ROM program memory is
implemented using Intel 1702 or NSC 5202 erasable reprogrammable
ROM's or equivalents, and I/O ports are TTL latches and selectors.
CPU CAPABILITIES
•
Twelve bit program address
•
Three level address stack for subroutines
•
Sixteen, four bit index registers
• A four bit accumulator plus carry
•
One, eight bit instruction word per cycle
•
Forty one single word instructions
•
Five double word instructions
•
Arithmetic and accumulator instructions
Add and subtract with carry
Complement, rotate, increment, decrement, clear,
and load the accumulator
Complement, clear, and set carry
•
Decimal arithmetic instructions
•
Decision making (address control instructions)
Test accumulator for zero or nonzero
Test carry for logic one or zero
Test external input for. high or low
Increment any index register and test for zero
•
Input/output instructions
•
RAM register instructions
•
Register instructions
1-1
~
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PLS 400 PROGRAMMED LOGIC SYSTEM
CPU
,
CPU BUS
~
,
\
\
~
OUTPUT
NTEPFACE
DRIVERS
I/O DEVICE
INPUT
INTERFACE
BUFFERS
OUTPUT
INTERFACE
DRIVERS
I/O DEVICE
INPUT
I rnER.FACE
BUFFERS
I/O DEVICES
KEYBOARDS
DISPLAY
TELETYPE
PAPER TAPE
MAGNET IC TAPE
CONTROL PANELS
D/A CONVERTERS
AID CONVERTERS
MEMORY
MODEMS
CRT
APPLICATIONS
DATil. TERMINALS
MEDICAL ELECTRONICS
CONTROL SYSTEMS
TEST SYSTEMS
BUSINESS MACHINES
FIGURE 1-1
PLS-400 Programmed Logic System Application
------
ROM PROGRAM MEMORY
• Programmable erasable ROM's MSC 5202, Intel 1702
•
256 eight bit instructions words per page
• Si.xteen pages maximum (ROM's) 4096 words of instruction
RAM REGISTER STORAGE
•
Intel 4002 RAM
• Organized as four registers of 16 four bit words
plus four status words for each register
• Requires CPU instruction addressing
• Includes four output lines used with CPU output
instruction
INPUT/OUTPUT
• TTL output latches and input selectors
• Requires CPU selection by
inst~uction
• 128 lines directly selectable
• Input instruction, gates data into the CPU accumulator
• Output instruction, latches accumulator data at output
1-3
2.
PLS 400 HARDWARE
The PLS 400 series provides a choice of micro-processor card sets
with varying expandability. Each set provides the CPU, ROM program memory, RAM register storage and I/O. All sets are implemented with CPU clock and external reset and power-on reset
circuits.
ROM program memory on each card set is implemented
with programmable erasable ROM.
The use of erasable, reprogrammabIe ROMs provides a speedy tool for implementing programmed
logic.
The PLS 401 one card set is complete on a single card
providing the lowest cost for limited system size. The system
expansion is limited to 1024 words of ROM program memory, 320
characters of RAM register storage, four output ports, four
input ports, and one RAM output port.
The PLS 402 two card set provides for reasonable program memory
and extensive I/O.
The system expansion is limited to 1536 words
os program memory, 320 characters of RAM register storage, 4 RAM
output ports, and up to 128 I/O lines.
The PLS 403 three card set provides maximum expansion capability
on ROM, RAM and I/O.
The system expansion is unlimited to the
full CPU capability of 4096 words of program memory, 1280 characters of RAM register storage, 48 lines of RAM output, and 128
lines of I/O.
The PLS 403 CPU Card 4111 will accept either eight
4002 RAM register devices or eight 4001 masked ROM devices.
This
card in itself can become a one card system with masked ROMs.
2-1
PLS. 401
SINGLE CARD SYSTEM
A programmable logic system which implements the Intel MCSTM_4 Micro Computer Set into a working
system with CPU, ROM program memory, RAM register storage and I/o on a single card. The PLS-401
organization provides for reasonable program and I/O capacity to give the lowest cost approach to investigating PLS technology.
FEATURES
• Single card programmed logic system for protypes Or production
• 1024 words of ROM program memory capacity (4 ROMs)
• 320 characters of RAM register storage capacity (4 RAMs)
COMPUTER
• Four output ports (16 lines)
• Four input ports (16 lines)
• One RAM output port (4 lines)
INPUT IOUTPUT
ROM PROGRAM MEMORY
OUTPUT
TEST
--==..._--l
CPU BUS
1--_""';'I_O_B_US_ _
EXT
RESET
PORT
b----'=---6
INPUT
POR T D----'''----Q
DATA
ADDRESS
BUS
BUS
OUTPUT
PORT
n----==---e
INPUT
PORT b----=---'~
UP TO 4 RAMS
UP TO 4 ROMS
PLS . 401 ONE CARD PROGRAMMED LOGIC
32 I/O LINES TOTAL
16 OUTPUT LINE S
16 INPUT LINES
PLS-401 SPECIFICATIONS
Card Dimensions
4. 5 inches high
6. 5 inches long
o. 48 inch maximum profile thickness
o. 062 inch printed circuit board thickness
Includes:
Card ejector
One 4004 CPU soldered to board
One 4002 RAM soldered to board plus three RAM sockets
One 1702A ROM and four ROM sockets
Master power-on and external reset circuit
Two phase CPU clock circuit
Four TTL output ports (16 lines)
Four TTL input ports (16 lines)
One MaS output port (4 lines)
CPU test input (MaS)
Maximum System Capabilities
Four 4002 RAMs (320 four bit characters)
Four 1302, 1602 or 1702 ROMs (1024 words of program memory)
20 output lines
16 TTL port lines
4 MaS RAM port lines
16 TTL input lines
Instruction Execution Capability
Capable of executing all 46 of the 4004 CPU Instruction except for DCL and WPM
10.8 microseconds instruction execution time
Logic Levels of External Connections:
Low level active
TTL Port:
MaS Input:
MOS Output:
Standard TTL compatibility and loading
Standard TTL compatibility
Drive capability, one LPTTL or one standard TTL load with 12K
pull-down to - VDD
Power Requirement
+VCC
::
GND
::
-VDD
+5 vol ts 5% @ 550 rnA maximum fully loaded (30 rnA per RAM, 35 mA per ROM)
o volts
-10 volts 5% @ 350 mA maximum fully loaded (30 rnA per RAM, 35 rnA per ROM)
Connector Requirem ents
56 pin, 28 position dual-readout on O. 125 centers
MCS™ is a registered trademark
of the Intel Corporation
PLS·402 TWO CARD SYSTEM
A programmable logic system which implements the Intel MCS™-4 Micro Computer Set into a working
system with CPU, ROM program memory, RAM register storage and I/O on two cards. The PLS-402
organization provides for reasonalbe program capacity and unlimited I/O capacity within the MCS-4
capability. The CPU card can be applied individually or used with one or more I/O cards depending on
system requirements.
FEATURES
•
•
•
•
•
Two card programmed logic system with expandable I/o
1536 words of ROM program memory capacity (6 ROMs)
320 characters of RAM register storage capacity (4 RAMs)
Eight I/o ports (32 lines) expandable to 128 lines
Four RAM output ports (16 lines)
COMPUTER
ROM PROGRAM MEMORY
INPUT /OUTPUT
CPU
CPU BUS
I/O
PORT
I/O BUS
TEST
EXT
~----o
I/O
PORT ~----o
RESET
DATA
BUS
ADDRESS
BUS
I/O
PORT ~----o
UP TO 32
I NPUT OR OUTPUT
LINES
41 13
I/O
UP TO 4 RAMS
UP TO
6
UP TO 64
ROMS TOTAL
4115
I/O LINES TOTAL
4113
I/O
,', 128 LINES WI TH FOUR I/O CARDS
CPU
ROM
PLS-402 TWO CARD PROGRAMMED LOGIC
I/O
PLS·402 SPECIFICA nONS
Card Dimensions
4. 5 inches high
6.5 inches long
0.48 inch maximum profile thickness
0.062 inch printed circuit board thickness
Includes:
One 4115 CPU card
One 4113 rio card
CPU Card Includes:
Card ejector
One 4004 CPU soldered to board
One 4002 RAM soldered to board plus three RAM sockets
One 1702A ROM and six ROM sockets
Master power-on and external reset
Two phase CPU clock circuit
Four MOS output ports (16 lines) when four RAMs are used
One MOS CPU Test input
110 Card Includes:
Card ejector
Eight TTL ports (32 lines)
Each port selectable as either an input port or output port
Output port lines can be wired for either high level or low level active
Common and individual reset inputs for each port
Maximum System Capabilities
Four 4002 RAMs (320 four bit characters)
Six 1302. 1602, or 1702 ROMs (1536 words of program memory)
16 MOS RAM port lines
128 TTL I/O port lines (requires four 4113 I/O cards)
64 output lines
64 input lines
Instruction Execution Capability
Executes all 46 of the 4004 CPU instructions except for DCL and WPM;
10.8 microseconds instruction execution time
Logic Levels of External Connections:
Low lever active
TTL Port:
MOS Input:
MOS Output:
Standard TTL compatibility and loading
Standard TTL compatibility
Drive capability, one LPTTL or one standard TTL load with 12K
pull-down to - VDD
Power Requirement: One CPU card and one
+VCC
GND
-VDD
+5 volts 5% @
I/o card both fully loaded
950 rnA maximum
(30 rnA per HAM, 35 rnA per ROM)
-10 volts 5% @ 450 rnA maximum
(30 rnA per RAM, 35 rnA per ROM)
o volts
Connector Requirements for each card
56 pin, 28 position dual-readout on O. 125 centers
MCS™ is a registered trademark
of the Intel Co;poration
PlS·403
THREE CARD SYSTEM
A programmable logic system which implements the Intel MCSTM-4 Micro Computer Set into a working
system with CPU, ROM program memory, RAM register storage and I/O on three cards. The PLS-403
organization provides for unlimited program and I/O capacity within the MCS-4 capability. This modular
arrangement allows the designer to tailor system size to suit his needs.
FEATURES
•
•
•
•
•
•
•
Three card programmed logic system with expandable RAM, ROM and I/O
2560 words of ROM program memory capacity expandable to 4096 words
640 characters of RAM register storage capacity expandable to 1280 characters
Eight I/o ports (32 lines) expandable to 128 lines
Six RAM output port capacity (24 lines) expandable to 48 lines
CPU card can be used as a single card system with masked ROMs
Allows use of RAM program memory
COMPUTER
ROM PROGRAM MEMORY
INPUT /OUTPUT
-
-
---
CPU
TEST
~--<
CPO
RESET
r--<
EXT
RESET
CPU BUS
r-'
"\
CPU
INTERFACE
~
~
~
E}
I/O BUS
---
I/O
PORT
0
'----
r--ROM
r-;;;-~(
~
I
~
~~
80
CHAR ~(
'---
~
ADDRESS
BUS
'---
DATA
BUS
0
PORT
I
'----
r-ROM
r-;;:;-P-I
80
CHAR
1~
~~
~ 256 x 8~
f:>-<
I
'-----
--
UP TO 8 RAM REG I STERS
t
UP TO 32 I NPUT OR OUTPUT LINES
UP TO 10 ROMS - -
~
4
•
4111
CPU
I/O
x 8~
256
-
r---
4112
ROM
1/0
4113
4
UP TO 16 ROMS TOTAL
UP TO 16 RAM REG I STERS TOTAL
CPU EXPANDER
4111-2
UP TO 64 I/O LINES TOTAL
4112- 2
ROM EXPANDER
4113
I/O
,', 128 LINES WITH FOUR I/O CARDS
CPU
ROM
PlS·403 THREE CARD PROGRAMMED lOGIC
I/O
PlS 403 SPECIFICATIONS
Card Dimensions
4.5 inches high
6.5 inches long
0.48 inch maximum profile thickness
0.062 inch printed circuit board thickness
Includes:
One 4111 CPU card
One 4112 ROM card
One 4113 I/o card
CPU Card Includes:
Card ejector
One 4004 CPU soldered to board
One 4002 RAM with eight RAM sockets
Master power-on and external system reset
Separate external CPU reset
Two phase CPU clock circuit
Six MOS port (24 lines) available when used with RAMs or masked ROMs
One MOS CPU TEST input
RAM sockets will accommodate 4001 masked ROMs
ROM Card Incl udes
Card ejector
One 1702A with 10 ROM sockets
Signal lines for controlling RAM program memory
1/ 0
Card Includes
Card Ejector
Eight TTL ports (32 lines)
Each port is selectable as either an input port or output port
Output port lines can be wired for either high level or low level active
Common and individual reset inputs for each port
Maximum System Capabilities
16 4002 RAMs (1280 four bit characters) or 16 masked ROMs (4096 words of program memory)
16 1302, 1602, or 1702 ROMs (4096 words of program memory) with ROM expander 4112-2
12 MOS ports (RAM or 4001 masked ROM) with CPU expander 4111-2
64 output lines
64 input lines
Instruction Execution Capability
Capable of executing all 46 of the 4004 CPU instructions
10.8 microseconds instruction execution time
Logic Levels of External Connections
Low Level active'
TTL Port:
MOS Input:
MOS Output:
Standard TTL compatibility and loading
Standard TTL compatibility
Drive capability, one LPTTL or one standard TTL load with 12K
pull- down to - VDD
Power Requirement: One CPU card, one ROM card, one
+VCC
GND
- VDD
=
=
I/o card
all fully loaded
+5 volts 5% @ 1. 3 amp maximum (30 rnA per RAM, 35 rnA per ROM)
0 volts
-10 volts 5% @ 0.7 amp maximum (30 rnA per RAM, 35 rnA per ROM)
Connector Requirements for each card
56 pin, 28 position dual-readout on '0. 125 centers
MCS™ is a registered trademark
of the Intel Corporation
3.
TIMING AND DEVICE DATA SHEETS
TIMING
The PLS 400 systems use a 4 bit micro-processor thus all data is
communicated between the system elements in groups of 4 bits.
The instruction cycle for the CPU requires eight, 4 bit time
intervals as shown in Figure 3-1. The eight time intervals
accomplish program memory addressing, instruction retrieval, and
instruction execution. The 12 bit address, required to address
up to 4096 words of program memory, is sent from the CPU to the
program memory in three time intervals defined as AI, A2, and A3.
The eight bits of instruction for each word are sent from the
addressed program memory to the CPU in two time intervals defined
as MI and M2. During the last three time intervals defined as Xl,
X2, and X3 the CPU executes the instruction.
Each time interval is generated by the operation of the two phase
CPU clock circuit. The two phase clock accomplishes the operations
within the MOS CPU, RAM, and CPU interface devices.
0l--u
02
SYNC
CM
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INSTRUCTION CYCLE
la.8 jlS
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\U \U \U \U \U \U IU IU
U
U
LJ
I
U
U
U
I
I
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Al
I
A2
I
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I
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,
II
Ml
A3
I
I
M2
ADDRESS
INSTRUCTION
FROM CPU TO
PROGRAM MEMORY
FROM PROGRAM
MEMORY TO CPU
Xl
X2
X3
EXECUTION
I
LOW ORDER HiGH ORDER
WORD
WORD
ADDRESS
ADDRESS
PAGE
ADDRESS
OPR
INCREMENT OR CHANGE
PROGRAM ADDRESS COUNTER
OPA
FIGURE 3-1
CPU Instruction Timing for Most Instructions
3-1
The sync pulse sent from the CPU keeps the RAM register and CPU
interface devices in step with the CPU. The CM line signals the
RAM registers and the CPU interface device to accept and decode
chip select information on the CPU bus. CM always occurs at A3
time as this is the ROM program memory chip select (page) address.
CM also occurs at X2 time as shown in Figure 3-2 during the SRC
instructions for addressing RAM register devices and I/O ports,
and at M2 time shown in Figure 3-3 during I/O and RAM register
instructions for sending operand information to the RAM registers
and the CPU interface circuits.
CM-RAM lines available from the CPU are used for bank switching of
RAM register devices.
If four or less RAM register devices are
used on a system they may be tied to the CM line. When the CM-RAM
lines are used and selected using the DCL instruction the timing
is identical to the CM timing shown in Figures 3-1, 3-2, and 3-3.
~I~
~2 -.J
SYNC
I
I:
.1
I
I
U
INSTRUCTION. CYCLE
10.8 I1S
1 35
"'
•
U
U
U
I
I
,
Al
U \U
I
U
U
U
I
I
I
A3
M2
ADDRESS
INSTRUCTION
FROM CPU TO
PROGRAM MEMORY
FROM PROGRAM
MEMORY TO CPU
LOW ORDER HIGH ORDER
WORD
WORD
ADDRESS
ADDRESS
U
I
U
OPR
XI
OPA
FIGURE 3-2
CPU Timing for SRC Instruction
3-2
I
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U
I
U
I
U
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PAGE
ADDRESS
I
I
I
I
MI
I
I
I
II
I
A2
I
I
I
U
I
CM
I
'1 U
I
U
I
I
I
I
X2
X3
EXECUTION
INCREMENT PROGRAM
ADDRESS COUNrR
SRC
.
SRC
ADDRESS
ADr.RESS
EVEN REG ODD REG
~ILJ
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SYNC I
02
CM
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U
35
I
1
IQ.8
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\U
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II
I
1
Al
A2
A3
ADDRESS
I
ILI IU
U
U
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Ml
MZ
I
INSTRUCTION
I
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\U
I
U
I
I
I
I
I
X2
IU
U
U
I
Xl
U
I
I
X3
EXECUTION
I
FROM CPU TO
PROGRAM MEMORY
LOW ORDER HIGH ORDER
WORD
WORD
ADDRESS
ADDRESS
)JS
I
I
U,
U,
I
.I
INSTRUCTION CYCLE
FROM PROGRAM
MEMORY TO CPU
PAGE
ADDRESS
OPR
OPA
TO RAM
AND CPU
INTERFACE
INCREMENT PROGRAM
.l\DDRESS COUNTER
RAM OR
I/O DATA
IN OR OUT
FIGURE 3-3
CPU Timing for I/O and RAM Register Instructions
DEVICE DATA SHEETS
The PLS 400 series uses 4000 series MOS devices. For exact specifications on the electrical and timing requirements of these
devices refer to the Intel data sheets. As an aid to the user
the 4001, 2, 3, 4 electrical specifications are shown with power
supply reference of +5 and -10 volts as used in the PLS 400 system.
3-3
ABSOLUTE MAXIMUM RATINGS
DC AND OPERATING CHARACTERISTICS
Ambient Temperature Under Bias
TA
Input Voltages and Supply Voltage
With Respect to VSS
O°C to +70°Ci VDD
=
-10 V ±5%, VSS
=
+5 +5%
Logic "0" is defined as the more positive voltage
(VIH' VOH) ,--Logic -"i" is defined as the more
+0.5 to -20 V
Power Dissipation
=
LOW
negative voltage (VIL, VOL)
SUPPLY CURRENT
Limit
Product
Symbol
Parameter
Hin
Typ
r1ax
Unit
Test Conditions
IDDI
Average Supply Current
15
20
rnA
Average Supply Current
17
33
rnA
4003
IDD2
IDD3
Average Supply Current
5.0
8.5
rnA
4004
IDD4
Average Supply Current
30
40
rnA
= 25°C
= 25°C
tWL = tttm =
TA = 25°C
VIL
4001
4002
TA
TA
8
llSi
TA
=
2Soc
INPUT CHARACTERISTICS
4001/2/3/4
Input Leakage Current
=
10
rnA
Input High Voltage
(all inputs except
clock)
+3.5
+5.3
V
VIL
Input Low Voltage
(all inputs except
clock)
VDD
VDD
-0.5
-1. 5
V
V
4001/2/4
VILC
Clock Il?-put Low Voltage
V
VIHC
Clock Input High
Voltage
VDD
+3.5
-8.4
4001/2/4
+5.3
V
4001
RI
I/O Pins Input
Resistance
35
Kn
Internal input resistor is
optional
10
rnA
VOUT
4.5
V
Driving 4000 series loads
only
4001/2/3/4
ILl
VIH
4001/2/3/4
10
18
VDD
Inverting Input
Noninverting Input
OUTPUT CHARACTERISTICS
ILO
Data Bus Output
Leakage Current
4001/2/3/4
VOH
Output High Voltage
4001/2/4
lOLl
Data Lines Sinking
Current "I" Level
10
18
rnA
VOUT
=
5 V
4001/2
IOL2
L/O Output Lines
Sinking Current,
"I" Level
2.5
5
rnA
VOUT
=
5 V
4003
IO L 3
Parallel Out Pins
Sinking Current,
·"1" Level
0.6
1.0
rnA
VOUT
=
5 V
4003
IOL4
Serial Out Sinking
Current, "1" Level
1.0
2.0
rnA
VOUT
=
5 V
4004
IOL5
CM-ROM Sinking Current
"I" Level
6.S
12
rnA
VOUT
=
5 V
4004
IOL6
CM-RAM Lines Sinking
Current "I" Level
2.5
4
rnA
VOUT = 5 V
4001/2/4
VOLI
Data Lines, CM Lines,
Sync Output Low Voltage
-7
-5
-1. 5
5.0
·V
-7 V, chip disabled
lOLl = 500 \1 A
4003
VO L 3
Output Low Voltage
-6
-2.5
-1. S
V
IOL3
VOL2
I/O Output Lines
Output Low Voltage
-7
-2.5
-1. 5
V
IOL2
=
=
10 \11\
4001/2
4001/2/4
ROHI
Output Resistance Data
Lines "0" Level
150
250
n
VOUT
=
4.5 V
4001/2
ROH2
Output Resistance
I/O Line "0" Level
1.2
1.8
Kn
VOUT
=
4.5 V
4003
ROH2
Parallel-Out Pins Output Resistance "0"
Level
400
750
n
VOUT
=
4 .. 5 V
4003
RoH4
Serial Out Output
Resistance "0" Level
6S0
1200
n
VOUT
=
4.5 V
4004
ROHS
CM-ROM Output
Resistance n·O" Level
320
600
n
VOUT
=
4.5 V
4004
RoH6
CM-RAM Lines Output
Resistance "0" Level
1.1
1.8
Kn
VOUT
=
4.5 V
Typical values are for TA
3-4
=
4001/2/4
2SoC and Nominal Supply Voltages
50 \1A
4.
PLS 400 SYSTEM ORGANIZATION
CENTRAL PROCESSING UNIT
Central processing unit consist of a central processing unit (CPU)
and a memory that has a stored sequence of instructions for the
CPu.
The CPU is operated by a clock circuit to alternately fetch
and execute the memory instructions. The CPU fetches an instruction by sending an address from a program address counting register
to the program memory. The program memory decodes the address and
sends the selected instruction to the CPU. The CPU stores the
instruction in an instruction register where it is decoded and
executed.
PLS 400 SYSTEMS
The PLS 400 systems are controlled by the Intel 4004 CPU chip.
The CPU performs control and data transfer functions with the
logic elements shown in the system data flow diagram Figure 4-1.
The CPU communicates with program memory, RAM registers and I/O
ports by connecting appropriate elements of the system to the
4 bit CPU BUS. Conceptually the information paths exist as
shown in Figure 4-1.
In addition to an instruction register and program address counter,
the CPU contains a program address counter stack, an arithmetic
logic unit (ALU) with a four bit accumulator register, and 16
four bit registers for intermediate data storage.
INSTRUCTION REGISTER
The instruction register shown in Figure 4-2 consists of eight
bits of storage 'and decoding for single word and the first word
of double word instructions as they are received from the program
memory.
The 4 bits associated with Ml time are always instruction
information. The 4 bits at M2 time can be additional instruction
information, data constants, or page address in£ormation.
The second word of a double word instruction does not go to the
instruction register but goes as either data to the index registers
or as a word address to Al and A2 of the program address counter.
4-1
~~
f
N
TO OTHER RAM PROGRAM MEMORY
~
, ,
WRI
A3
~
I' ,
READ
, r- .
RAM
PROGRAM
MEMORY
256 X 8
~
,
T£
""
_
WPM
A3
,
I'
8 4 2 I
E
C
flM PX
FIN PX
"P7
p6
i'S
p4
"P3
P2
PI
PO
A
8
6
4
1
0
I
(,N PO
/
,
,
TO OTHER ROM PROGRAM MEMORY
4~
I
I
0
9
1"""""'\
3
I
'1
~
I
I
RAR
J
-
"-
1
"
, ,
CARRYBlT
8
CPR
2
HI
4
,1.~
DPA
2 -112
I
JUN
JMS
JCN
ISl
STC
CLC
CMC
2
2
2
2
LDM X
BBL X
"JlJN
JHS
-,
I
PROGRAM ADDRESS •
COUNTER
[
A2
I
A3
Y. -
JIN PX
-
J
AI
•
I
I
-.1
/
8
JMS ,
..
.4
2 I
I
- I
FIN PO
SRC PX
, BBL
SUBROUTINE
ADDRESS STACK
./
LEVEL I
LEVEL 2
LEVEL 3
g
4
2 I
8
4
2 I
FIGURE 4-1
PLS-400 System Data Flow
I
I
o
STATUS
CHAR
1 2 3
l
I-
~
REG
2
I
U
~-
REG
2
1
I
~
REG
2
I
2
~
REG
2
3
I
ROM
WRM
-
SRC
SRC
EVEN
SRC ODD
)'
-
SRC
'\
./
~
I t
1
tHAR
V--
I
I
REG
OI234St>789ABCDEf
r-
I
,
RAM REGISTER
V--
I
1
---.. 8 4 2 1 J---
~
1
"
BUS'
LD
XCH,
RAL I
f
,
F
0
B
7 5
ACCUMULATOR
, .1
'", 1 \ 1
~
AI
'"
.
.
~
I v--
C>
~d,
t
~
CHIP SHECT
ROM
PROGRAM
MEMORY
256 X 8
A2
•
I
~
REG
PAIR 8 4 -2 I
INSTRUCTION
REGISTER
V
,
I
z
I
I
I
V
'\
TO OTHER RAM REGISTERS
I
- I
j-SRC PX WRITE
A2 Al READ
,
-
I
CPU
",
"
f
,
SRC
,, -
TO OTHER I/O PORTS
,
--- ..... --
WMP
WRR
"
t
SRC
RDR
"8
4
OUTPUT
j"\
0()
2
.n
I
.J"\
...
,
r-'8
4
2
I
.......
---
INPUT
.n
~
.;;
...
j"\
,
INSTRUCTION
REGISTER
FIRST WORD FROM
PROGRAM MEMORY
8 BITS
SECOND WORD FROM
PROGRAM MEMORY
8 BITS
-
-
8 OPR
4
2
MI
~~
8
4
OPA
2
I
M2
JUN
JMS
JCN
ISZ
2
2
2
2
JUN
JMS
- ,
I
I
PROGRAM ADDRESS
COUNTER
I
ADDRESS TO
PROGRAM MEMORY
12 BITS
),
A2
I
I
A3
I
J
/1\
I
J
-
/
JMS ,
A BBL
.
.
SUBROUTINE
ADDRESS ST/\CI<
~
8
4
-'-
.
LEVEL 1
LEVEL 2
LEVEL 3
I
2 \
S
4
2 \
8
4
2 \
FIGURE 4-2
Instruction Register, Program Address Counter,
and Subroutine Address Stack
PROGRAM ADDRESS COUNTER
The program address counter shown in Figure 4-2 is a 12 bit
sequential counter which keeps track of the location of the next
instruction to be executed from program memory.
The four most
significant bits (A3) are called the page address and the eight
least significant bits (A2 and AI) are the word address of the
instruction on a page. The program address counter is normally
incremented by I for each instruction word unless the instruction
is the type which modifies the count by loading a new address.
SUBROUTINE ADDRESS STACK
The subroutine address stack shown in Figure 4-2 consists of
three 12 bit registers used to save the program return address for
each of three allowable subroutine levels. The subroutine address
stack is controlled by two CPU instructions, an entry instruction
JMS and a return instruction BBL. Each entry to a subroutine
causes the program address counter to be transferred to the top
most level of the subroutine address stack. The three levels in
turn are pushed-down to accommodate the new entry. The lowest
level is lost off the bottom of the stack. Each return from a
subroutine causes the stack to be pulled-up one level with the top
most address going to the program address counter.
4-3
INDEX REGISTERS
The index registers consist of sixteen 4 bit registers which can
be directly operated on by various instructions, either individually
or in pairs. Figure 4-3 shows the registers organized as the even
numbered and the odd numbered registers, or as seven pairs, each
pair consisting of one even and one odd numbered register.
When the registers are being used with the 4 bit accumulator by
various instructions they are used individually. When data is
loaded direct from program memory or the registers are used for
address control they are used in pairs because of the 8 bit requirement for these functions.
ARITHMETIC LOGIC UNIT
The arithmetic logic unit consists of a 4 bit accumulator register
and a carry flip-flop as shown in Figure 4-3.
In addition to providing the arithmetic functions of ADD and SUBtract the accumulator
is the central control and distribution point for data flow in the
system. All data transfers to and from I/O. ~M registers and
the index register occurs with the accumulator register.
INDEX REGISTER
z
w
>
W
E
DATA FROM
PROGRAM MEMORY
8 BITS
FIM PX
FIN PX
c
A
8
6
4
2
0
REG
0
C)
842 I PAIR 842 I 0
P7
F
p6
0
B
P5
p4
9
P3
7
P2
5
PI
3
I
•
PO
I
..
I
_~
I
I
•
--'-
I
I
I
.
I
~~:
ACCUMULATOR
RAL
f
LD
XCH
842 I
t
CARRY BIT
STC
CLC
CMC
FIGURE 4-3
Index Registers
4-4
SR CPX
FIN PX
ADDRESS TO
I/O AND RAM
8 BITS
ADDRESS TO
PROGRAM MEMORY
8 BITS
'A,
RAR
;
DA TA FROM OR TO
I /0 AND RAM
REGISTERS
4 BITS
In addition to the instructions which control data transfer to or
from the accumulator there are instructions which directly control
the accumulator or its associated carry bit. The accumulator can
be tested, incremented, dec+emented, set to any value, cleared,
complemented, rotated right or left through the carry besides
being manipulated for" decimal arithmetic.
The carry bit can be
set, cleared, complemented, or tested.
PROGRAM MEMORY
Program memory stores the instruction to be executed by the CPU
and is defined by the CPU instruction set as a page oriented
memory of 256 words per page as shown in Figure 4-4. The CPU
addresses the page and word and the program memory sends the
8 bit word at that address to the CPU.
00
01
02
I
0 1 0
1 1 0 0
----
--I
I
256 WORDS
PER PAGE
A2, Al
Fe
FD
FE
FF
I I
I I
--- --- 1 0 0
o
1
I I 0
•
8 BITS/WORD
FIGURE 4-4
Organization of Program Memory as Defined
by the CPU Instructions
4-5
The 12 bit addressing capability of the CPU allows direct access
to 16 pages with the four A3 bits used as page address. The
eight bits at Al and A2 are used for the word address within a
page.
It is important to understand the page organization in
terms of the address control instructions (jumping and branching).
Certain address instructions use the full twelve bits of address
and may be used to change control within a page or from page to
page. Other address control instructions use only eight bits of
address and are limited to changing control only within a page.
The PLS 400 systems are implemented with ROM (read only memory)
program memory only.
In addition the PLS 403 has all the control
lines available for implementing RWM (read write memory) program
memory.
ROM program memory is used for systems in fixed applications.
RWM memory is used where it is desired to change the system application by the operator. RWM is a considerable step in
system complexity in hardware and programs, and is therefore not
recommended unless absolutely necessary.
ROM PROGRAM MEMORY
ROM program memory on the PLS 400 system is accomplished as
shown in Figure 4-4 using programmable erasable ROMs organized
as 256 location of 8 bits. This organization is equivalent to
the page size of the CPU therefore each ROM chip equals one page.
Other ROM sizes and organizations can be used if the appropriate
hardware addressing is provided.
.
ROM program memory addressing ~s an automatic function of the PLS
hardware.
The only control the program designer has over ROM
memory is use of the program control instructions to change the
instruction sequence.
RWM PROGRAM MEMORY
RWM program memory can be accomplished on the PLS 403 system only.
The Intel 4008 and 4009 interface devices provide the address lines
and control lines necessary for writing into the desired memory
type.
The WPM instrQction allows writing 4 bits at a time from
the accumulator to the RWM. For applications and suggested implementation, refer to the Intel 4008 and 4009 data sheet.
4-6
RAM REGISTER STORAGE
The PLS 400 systems use the Intel 4002 RAM register devices for
program controlled data storage. Each 4002 is organized as four
registers of 20 characters as shown in Figure 4-5. Each 20 character register consists of 16 individually addressable characters
of main storage plus 4 instruction selectable status characters.
The instruction capability of the CPU allows addressing of up to
32 of the 4002 RAM devices.
This is accomplished through an
organization of 8 banks of 4 RAM chips per bank. RAM banks are
selected by the DCL instruction that specifies which of the four
CM-RAM lines out of the CPU will be active. The active CM-RAM
line designates which RAM bank will respond to the SRC instruction.
The SRC instruction selects the RAM chip, register and character.
A summary of RAM addressing is given in Table 4-1 and further
definition of RAM addressing is given in Section 6 under the SRC
and DCL instructions.
TABLE 4-1
RAM Addressing
Level
Instruction
RAM Bank
DCL
RAM Chip
SRC, Even Register high order bits
RAM Register
SRC, Even Register low order bits
RAM Character
SRC, Odd Register 4 bits
;
INPUTS AND OUTPUTS
The flow of data into and out of the PLS systems is accomplished
through the I/O ports of four lines each. To accomplish an input
or output function a port must first be addressed by the CPU
instruction SRC. The even register of the SRC pair contains the
addres~ of the port to be selected.
Once a port has been addressed
it remains selected for as many input or output operations as desired until another port is addressed.
There are two types of output ports and one type of input port.
Each RAM register device has an output port packaged physically
within the device. This port shares chip select addressing with
the RAM but has its own instruction WMP for the transfer of data
from the accumulator to the port. The port latches any data sent
to it and retains it as a stable out~ut until a subsequent WMP
instruction changes the data. The ~1 port lines are MaS low
level active outputs ca~able of driving one low power TTL load.
4-7
STATUS
CHAR
REG
CHAR
0 1 2 3 4 5 6 7 8 9 A B C
.... . . .. I- • . .. . . .
... . .· - .. . . . . . .. . . . .. ..
... . i-' • · .. .. . .. .. . .. i-' • .. .. i-' • •
~
. .
.. I- ..
~
~
.
~
.~
~
I-
-
-r- •
~
~
~
..
~
-~
.. - ....
-
-
-I-
-- ..
-
· ..
I-
"
....
..
. .. . -
.
- - -.. -
..
.
- I-
-
-
I-
~
•
..
"
•
OIl" .. I-
~
RDM
WRM
-..
•
~
" I-
~
~
..
- ....
I-
I- • I-
"
.. .
~
.. ..
.
I-
•~
. I-
~
.. I-
• i-' .. ~
~
~
~
..
~
~
~
~
.. i-'
l-
.. l-
i-' •
I-
•
'1-
.. . ..
.. i-' •
SRC
!OlIo
•
~
~
~
....
I--
~
~
~
•
~
"II- .. I-
•
~
I-
~
I- ..
--
~
•
I-
~
. .. -.. -
. .I- - I- . I-- - - .. --I-
..
.. .. . . .. ..
..
. .
~
~
~
-. - - .. - .... . . ......
-I- ..
-I-
~
'1- • I- .. i-' ..
-~
.
•
~
... .. ... .
... . . - .. -. - -r- - ~
I-
~
3
D E F D 1 2
..
- .. .. - -
.. ~2
-..
...
--
po
•
... - ..
~I-
I-
~
•
I"
0
4
2
1
1
8 REG
4
..
.. ......
1
.8 REG
- --
~
.
8 REG
4
2
~
.. 1
4 REGISTERS
SELECTED BY
SRC EVEN
REGISTER
2
.8 REG
.. . . . I-- .. I-- .- ... 4
.. . .. .. " i-' - 1-SRC
.- - - .. I- - - .. - .. 21 3 EVEN
• po
"
•
~
...
~
ODD
..
~~------------ ----~¥~----------------~, ,~~¥~--,
16 MAIN CHARACTERS SELECTED
4 STATUS
ONE CHAR AT A TIME
BY SRC ODD REGISTER.
READ OR WRITE INTO
SELECTED CHARACTER BY
INSTRUCTIONS RDM, WRM
CHARACTERS
READ OR WRITE
DIRECTLY BY
INSTRUCTION
RDX, WRX
FIGURE 4,-5
RAM Index Register
The other type of output port is implemented in the PLS 400 systems
using TTL logic.
The CPU instruction WRR is used to send data to
a TTL quad D type flip-flop from the accumulator.
The TTL flipflops latch the data as a stable output until a subsequent WRR
instruction changes the data.
The PLS 400 input ports are also implemented with TTL logic. The
CPU instruction RDR reads data from the selected input port into
the accumulator.
4-8
HEXADECIMAL NOTATION
The basic 4 bit structure of the CPU makes it convenient to use
hexadecimal notation to express with a single character, one-ofsixteen possible combinations.
The single hexadecimal character notation 0 --+ 9, A --+F is used to
refer to the:
16 Basic Instructions
16 I/O and RAM Instructions
16 Accumulator Instructions
16 Index Registers
16 Pages of Program Memory Capacity
16 RAM Register Chip Capacity
16 Characters in a RAM Register
16 Output Ports
16 Input Ports
A double hexadecimal character notation is applied to the 8 bit
instruction word address for program memory, where the decimal
addresses 000 through 255 are given as 00 through FF in
hexadecimal.
Table 4-2 shows the hexadecimal notation for sixteen combinations.
Additional hexadecimal tables are given in the appendix.
TABLE 4-2
Hexadecimal Notation for Sixteen Combinations
Hexadecimal
Binary
Decimal
0
1
2
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
3
4
5
6
7
8
9
10
11
12
13
14
15
4-9
5.
INSTRUCTION TABLE
This section presents the 4004 CPU instructions in a short table
form.
Section 6 contains detailed descriptions of the instructions.
HEX
CODING
MNEMONIC
OPA
OPR
DESCRIPTION OF OPERATION
0
0
NOP
1
Cx
A1
JCN
Cx
LABEL
Jump on condition Cx to the program memory address A1,
A2, otherwise continue in sequence.
D2
Pxe
D1
FIM
D2
PO
x
D1
Fetch immediate from program memory data D1, D2 to
index register pair P x
2
Pxo
SRC
P 1
x
Send register control. Send the contents of index register
pair P x to I/o ports and RAM register as chip select and
RAM character address.
3
Pxe
FIN
PO
x
Fetch indirect. Send contents of register pair 0 out as a
program memory address. Data fetched is placed into register
pair P x
3
Pxo
JIN
P 1
x
Jump indirect. Jump to the program memory address designated
by contents of register pair P x
4
A3
A1
JUN
A3
A1
JMS
Rx
A2
2
A2
5
A2
6
7
A2
No operation.
LABEL
Jump unconditional to program memory address A1. A2 · A3'
LABEL
Jump to subroutine located at program memory address A1,
A2, A3' Save previous address (push down in stack).
INC
Rx
Increment contents of registerRx '
Rx
A1
ISZ
Rx
LABEL
Increment and skip on zero. Increment contents of register
Rx , if result is not 0 go to program memory address A1, A2,
otherwise skip to the next instruction in sequence.
Rx
ADD
Rx
Add contents of register Rx to accumulator.
Rx
SUB
Rx
Subtract contents of register Rx to accumulator with borrow.
8
9
A
B
Rx
LD
Rx
Load contents of register Rx to accumulator.
Rx
XCH
Rx
Exchange contents of index register Rx and accumulator.
C
D1
BBL
D1
Branch back one level in stack to the program memory address
stored by a prior JMS instruction. Load data D1 to accumulator.
0
D1
LDM
D1
Load data D1 to accumulator.
E
X
I/O and RAM register instructions
F
X
Accumulator instructions
Low order address bits
High order address bits
Chip select
P 1
x
Register Po through P d.esignated by odd characters
7
1, 3, 5, 7, 9, B, D, F
Register Po through P designated by even characters
7
0,2,4,6,8, A, C, E
Rx
Register 0 - - F
Data character #1
Data character #2
Jump conditions
5-1
Llo AND RAM REGISTER INSTRUCTIONS
MNEMONIC
HEX
CODING
OPR
E
0
WRM
Write the contents of the accumulator into the previously selected
RAM register character.
E
1
WMP
Write the contents of the accumulator into the previously selected
RAM output port. (Output lines. )
E
2
WRR
Write the contents of the accumulator into the previously selected
output port. (I/o lines. )
E
3
WPM
Write the contents of the accumulator into the previously selected
RAM program memory.
E
4
WRO
E 5
WRl
Write the contents of the accumulator into the previously selected
RAM status character 1-
E 6
WR2
Write the contents of the accumulator into the previously selected
RAM status character 2.
E 7
WR3
Write the contents of the accumulator into the previously selected
RAM status character 3.
E 8
SBM
Subtract the previously selected RAM register character from
accumulator with borrow.
E 9
RDM
Read the previously selected RAM register character into the
accumulator.
E A
RDR
Read the contents of the previously selected input port into the
accumulator. (lio lines.)
E B
ADM
Add the previously selected RAM register character to accumulator
with carry.
E C
ROO
Read the previously selected RAM status character 9 into
accum ulator.
E 0
RDl
Read tJ:te previously selected RAM status character 1 into
accumulator.
E E
RD2
Read the previously selected RAM status character 2 into
accumulator.
E E
RD3
Read the previously selected RAM status character 3 into
accumulator.
OPA
DESCRIPTION 'OF OPERATION
"
Write the contents of the accumulator into the previously selected
RAM status character O.
ACCUMULATOR INSTRUCTIONS
HEX.
CODING
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
5-2
MNEMONIC
OPR
OPA
DEf:CRIPTION OF OPERATION
0
1
CLB
CLC
CI ear carry.
2
lAC
Increml~n(
Complement carry.
Clear both.
(Accumulator and carry.)
accumulator.
3
CMC
4
CMA
Complement accumulator.
5
6
RAL
Rotate left.
RAR
Rotate ri!!:ht. (Accumulator and rarry. )
7
8
9
A
B
C
Tec
Transmit carry to accumulator and clear carry.
DAA
Decimal adjust accumulator.
KBP
Keyboard process. Converts the contents of the accumulator
from a one out of four code to a binary code.
0
DCL
Desi!!:nate command line.
E
F
(Accumulator and carry. )
DAC
Decrement accumulator.
TCS
Transfer carry subtract and clear carry.
STC
Set carry.
Condition Table for ICN Ins! ruction
Invert Jump Condition
CH
Jump if Accumulator -= 0
C4
.TeN
HEX
(r
Cx
:\:lNEMONIC
10
.Jump if Carry Bit
)1-
,Jump if Test Input
0
0
0
0
NO OPERATION
11
TO
0
0
0
1
.lump if test -= 0
12
Cl
0
0
1
0
Jump if CY
13
'TOICI
0
0
I
I
,lump if test
14
AO
0
1
0
0
Jump if AC
Hi
TO+AO
0
1
0
1
Jump if test
15
CIIAO
0
1
1
0
Jump if CY
17
TO+ChAO
0
1
1
1
Jump if test
1
0
0
0
Jump Unconditionally
18
=0
=0
=I
= 0 or CY = I
=0
= 0 Or AC
0
= 1 or AC = 0
= 0 Or CY = 1 or AC = 0
19
Tl
I
0
0
1
Jump if test
IA
CO
1
0
I
0
,Jump if CY
IB
TICO
1
0
I
I
Jump if test'" I and CY
IC
Al
I
1
0
0
Jump if ACi- 0
ID
TIAI
I
I
0
1
Jump if test
IE
COAl
1
I
1
0
,Jump if CY
IF
TICOAI
1
1
1
1
Jump if test
==
==
1
0
=0
= 1 and AC i- 0
:=
0 and AC i 0
= 1 and CY = 0 and AC i: 0
5-3
6.
llJSTRUCTION DESCRIPrIONS
NO OPERATION
NOP
M1
M2
00
00000000
2
8'4
1
8 1 4'2'1
'
'
No operation is performed by this instruction except that the
program address counter counts to the next instruction address in
sequence. This instruction can be used as a one cycle time delay.
To avoid problems with power-on reset, the first instruction at
program address 000 should always be an NOP.
JUMP ON CONDITION
M1
0
8 I 4
8
M2
0
0
I
JCN
2 1
A2
4 I 2 I
11
1
8
Cx
14 I 2 I
8
Al
I 4 I 2 I
First Word
1
Second Word
If the designated condition (C x ) is true, program control is transferred to the instruction located at the 8 bit address A2, Al of
the current page, otherwise program control continues in sequence.
If the JCN occupies the last two positions of a page or overlaps
the page boundary, program control is transferred to the 8 bit
address on the next page in sequence.
JCN is one of the two decision making instructions of the CPU, the
other being ISZ. JCN allows a decision on the following tests:
Test accumulator for zero or nonzero
Test carry bit for logic one or zero
Test external input lead for high or low
Table 5
provides detailed definitions of conditions Cx.
FETCH IMMBDIATE
FIM
First Word
Second Word
Load the 8 bits of data from the second word D2, Dl to the
designated pair of index registers PxO.
FIM uses the even register numbers to designate a pair. The only
valid operand codes for PxO are 0, 2, 4, 6, 8, A, C, and E.
FIM
provides the most efficient way to initialize a pair of index
registers.
RRR defines one of the eight register pairs PO through P7.
The
following RRR is part of the command decoding and distinguishes
the FIM from the SRC.
SEND REGISTER CONTROL
°
SRC
Send the contents of index register pair Pxl to the I/O ports and
RAM registers as chip select and/or RAM character select. SRC uses
the odd register numbers to designate a pair. The only valid
operand codes for Pxl are 1, 3, 5, 7, 9, B, D, and F.
RRR defines one of the eight register pairs PO through P7. The 1
following RRR is part of the command decoding and distinguishes
the SRC from the FIM.
It is necessary to address the I/O port or RAM register character
using an SRC instruction before an I/O operation or a RAM register
operation can be performed. The same SRC instruction can be used
t~ address both I/O ports and RAM registers, however, the meaning
of the address in the designated pair Pxl is different for each as
shown below.
The I/O port is addressed by the contents of the even register
designated by P x . The odd register does not serve any purpose
in selecting I/O ports.
6-2
REGISTER PAIR P x
ELEMENT
ADDRESSED
ODD REGISTER
EVEN REGISTER
I/O PORT
I
I
RAM
REGISTER
PORT SELECT
8
I
4
CHIP
SE~ECT
8
•
I
2
I
1
I I
J
REGISTERI
SEL,ECT
4 •
2 •
I
1
NOT USED
8
I
4
I
2
I
1
CHARACTER
8
I
4 I
2
I
1
I
I
The RAM chip select is addressed by the high order 2 bits of the
even register, the RAM register within the selected chip is addressed by the low order 2 bits of the even register and the
character within the RAH register is addressed by the 4 bits of
the odd register.
Addressing of the I/O port and RAH registers by the even register
is tabulated in Table 6-1. The table covers anyone bank of RAM
registers.
To select other RAH banks refer to the DeL instructions.
TABLE 6-1
I/O Port and
CONTENTS
OF
EVEN
REGISTER
RN~
Selection for One Bank by Even Register Contents,
as Used with SRC Instruction
RAM # AND RAM REGISTER SELECTED
I/O PORT
SELECTED
RAM #
REGISTER
0
0
0
0
1
1
0
1
2
2
0
2
3
3
0
3
4
4
1
0
5
5
i
1
6
6
1
2
7
7
1
3
8
8
2
0
9
9
2
1
A
A
2
2
B
B
2
3
C
C
3
0
D
D
3
1
E
E
3
2
F
F
3
3
RAM
DEVICE
TYPE
PIN 10
WIRED
4002-1
HIGH
4002-1
LOW
4002-2
HIGH
4002-2
LOW
RAM
6-3
FETCH INDIRECT
M1
FIN
M2
°
The 8 bit content of register pair
is sent out as an address to
the current page of program memory.
The 8 bit word at that location is loaded as data into the designated index register pair PxO.
If the FIN occupies the last position of a page, data will be
fetched from the next page in sequence. The program counter is not
affected.
After the FIN has been executed the next instruction in sequence
will be .addressed. However, the FIN is a one word instruction,
and it requires an additional instruction cycle to retrieve the
8 bits of data for the designated register pair. This extra cycle
must be considered when the FIN is used in routines with timing
considerations.
FIN uses the even register numbers to designate a pair. The only
valid operand codes for PxO are 0, 2, 4, 6, 8, A, C, and E. The
FIN instruction is useful for retrieving data from look-up or
translation tables.
RRR defines one of the eight register pairs PO through P7. The
following RRR is part of the command decoding and distinguishes
the FIN from the JIN.
JUMP INDIRECT
M1
001
°
JIN
M2
llR R R
11
8 1 4 1 2 1 1 8 1 4 1 2'1
The 8 bit content of the designated register pair Pxl is loaded
into the low order 8 positions of the program address counter.
Program control is transferred to the instruction at that address
on the same page.
If the JIN occupies the last position of the
current page program control transfers to the 8 bit address of the
next page in sequence.
The 8 bit content of the register pair is not affected.
JIN uses the odd register numbers to designate the pair P x . The
only valid operand codes for Pxl are 1, 3, 5, 7, 9, B, D, and F.
RRR defines one of the eight register pairs PO through P7. The 1
following RRR is part of the command decoding and distinguishes
the JIN from the FIN.
6-4
JUMP UNCONDITIONAL
M1
1
0
0
I 2 I
8 I 4
o
I
M2
I
4 1 2 I 1
First Word'
A3
8
I 4 I 2 11
A2
8
JUN
8 1
Al
4 I 2 I
Second Word
Program control is unconditionally transferred to the instruction
located at the address A3, A2' and AI. The CPU accomplishes this
internally by transferring A3 from the operand of the instruction
register and A2, Al from program memory to the program address
counter.
JUMP TO SUBROUTINE
M2
M1
0
1
0
8
I 4I
2
1
I
8
A2
8
,I
4
I
First Word
A3
I
4 I 2 1 1
Second Word
Al
2
I
1
8 1 4 1 2 I
The subroutine address stack is pushed down one level. The program address counter, containing the 12 bit address of the instruction following the second word of the JMS, is transferred to the
topmost stack level. Program control is transferred to the instruction located at A3, A2' and Al from program memory to the program
address counter.
First word.
Second word.
In Instruction Register
5
From Program Memory
Program Address Counter
Ph
Pm
PI
I
(Level 1)
Subroutine Address Stack
[Level 2]
{Level 3}
Stack shown fully loaded
6-5
INCREMENT REGISTER
INC
M2
The 4 bit content of the designated register Rx is incremented by
1.
If the count causes the register to overflow, the register is
set to zero.
The carry bit and accumulator are not affected.
INCREMENT REGISTER SKIP IF ZERO
Ml
0
1
18 I 4 I
M2
1
2
I
I
4
I
First Word
~
11
8
I
4
I
2
I
1
Al
A2
8
ISZ
2
I
1
8
I
4
I
Second Nord
2
I
The contents of the designated register Rx is incremented by 1.
If the result is zero, program control continues in sequence.
If
the result is not zero, program control is transferred to the
instruction located at the 8 bit address A2, Al on the same page.
If the ISZ occupies the last two positions of a page, or overlaps
the page boundary, program control is tran~ferred to the 8 bit
address on the next page in sequence.
The accumulator and carry are not affected.
ISZ is one of the two decision making in structions of the cpu.
The other is JCN.
ISZ allows a program control decision to be
made based on the count of a register.
Examples of ISZ use may
be found in Section 8 of this manual.
ADD REGISTER TO ACCUMULATOR
ADD
M2
The 4 bit content of the designated index register Rx is added to
the contents of the accumulator with carry. The result is stored
in the accumulator. The carry is set to 1 if a sum greater than
15 was generated, otherwise the carry is set to o.
6-6
The contents of the index register is not affected.
Accumulator in
Carry in
+)
Register
Accumulator out
Carry out
ag a4 a2 al
C·ill
Augend
Rg R4 R2 Rl
ag a4 a2 al
Cout
Addend
Carry in
Sum
Carry out
Addition of words longer than 4 bits (multiple precision addition)
may be accomplished by starting with the LSD, working on 4 bits at
a time until the desired word length has been operated on.
It is
important not to modify the carry bit between each 4 bits.
SUBTRACT REGISTER FROM ACCUMULATOR
11
M1
0
0
1I
8 1 4 1 211
SUB
M2
9 Rx
Rx
8 1 4'2 1
The 4 bit content of the designated register Rx is subtracted from
the accumulator with borrow.
The result is stored in the accumulator.
If a borrow is generated, (i.e., Rx > accumulator) the carry
bit is set to 0; is a borrow is not generated the carry is set to 1.
The content of the index register Rx is not affected.
The CPU performs the subtraction by adding the complement of the
index register plus the complement of the carry to the accumulator.
Accumulator in
Carry in
Register
Accumulator out
Carry out
+)
ag a4 a2 al
Minuend
Cin
Rg R4 R2 Rl
ag a4 a2 al
Borrow in
Cout
Subtrahend
Result
Borrow out
Subtraction of words longer than 4 bits (multiple precision subtraction) can be accomplished by starting with the LSD, working
on 4 bits at a time until the desired word length has been operated
on.
It is required that the carry bit be complemented between each
4 bits for the correct result.
.
The SUB instruction is useful for performing a compare function.
The compare is performed by initially clearing the carry bit and
subtracting the 4 bit word Rx to be compared from the accumulator.
6-7
The conditions to be tested for comparison results following subtraction are presented below:
COMPARISON
REG
>
CARRY
:f 0
0
CO
0
1
AO
:f 0
1
AI·Cl
X
1
CI
:f 0
X
Al
ACC
REG = ACC
REG
<
MNEMONIC
TEST CONDITION
ACCUMULATOR
ACC
REG =< ACC
-REG :f ACC
LOAD REGISTER TO ACCUMULATOR
M1
M2
110101
Rx
8
1
4'2'1
LD
8'4'2 1
The 4 bit content of the designated index register Rx is loaded
into the accumulator. The previous contents of the accumulator
are lost.
The content of the index register and the carry bit are not
affected.
EXCHANGE REGISTER WITH ACCUMULATOR
M1
M2
8 1 4'2'1
8 1 4 1 211
11011 1
Rx
XCH
I
The 4 bit content of the designated index register Rx is loaded
into the accumulator.
The prior content of the accumulator is
loaded into the designated register Rx.
The carry bit is not affected.
This is the only instruction which allows the accumulator to be
loaded into an index register.
BRANCH BACK AND LOAD ACCUMULATOR
M1
11 1 0 0I
8 1 4'2'1
BBL
M2
Dx
8 1 4'2'
BBL is used to return from subroutine to main program. The subroutine address stack is pulled up one level.
The top-most
address is placed in the program address counter causing program
control to be transferred to the sequential instruction following
the previous JMS.
6-8
Program Address Counter
Ph
Pm
PI
BBL
Program
(Level 1)
Address
[Level 2]
Stack
Level 3
Stack shown fully loaded
The 4 bits of data Dx in the operand portion of the instruction
are loaded into the accumulator.
The previous accumulator data
is lost.
The carry bit is not affected.
LOAD DATA TO ACCUMULATOR
M1
M2
8 1 4 1 211
8 1 4'2 1 1
11 1 0 1I
Dl
LDM
I
The 4 bits of data Dl stored in the operand field of the instruction word are loaded into the accumulator.
The previous contents
of the accumulator are lost.
The carry bit is not affected.
WRITE ACCUMULATOR INTO RAM CHARACTER
M1
M2
11110100001
8 1• 1 2 1 1
WRM
EO
8 1 .'2'1
The accumulator content is written into the RAM main memory
character location previously selected by an SRC instruction.
The accumulator and carry are not affected.
6-9
WRITE MEMORY PORT
Ml
M2
8 1 4 1 211
8 1 4 1 211
WMP
1111010 a all
E1
The content of the accumulator is transferred to the RAM output
port previously selected by an SRC instruction. The data is
available on the output pins until a new WMP is executed on the
same RAM chip.
The accumulator and carry are not affected.
WRITE ROM PORT
M1
WRR
M2
1111010 0101
8 1 4 1 211
8 14
1
E2
211
The content of the accumulator is transferred to the output port
previously selected by an SRC instruction. The data is available
on the output pins until a new WRR is executed on the same port.
The accumulator and carry are not affected.
WRITE TO PROGRAM MEMORY
M1
M2
1111010 a 111
8 14
1 211
WPM
E3
8 1 4 1 211
This instruction is used tq write data into RAM program memory 4
bits at a time. The WPM instruction must be executed twice for
each 8 bit RAM program memory location.
Program memory page select lines are
viousSRC address is sent out on the
and the accumulator contents becomes
the I/O bus. Two control lines from
control w~iting into the RAM.
forced to 1111. The preprogram memory address bus
available as 4 bits of data on
the CPU interface circuitry
The WPM instruction is not applicable to PLS 401 and PLS 402 systems since the program memory address bus is not available to the
user.
The PLS 403 configuration provides all necessary lines for
implementing RAM program memory.
6-10
WRITE INTO RAM STATUS CHARACTER 0
Ml
WRO
M2
11110101001
8 1 4 1 211
E4
8 1 4 1 2'1
The content of the accumulator is written into the RAM status
character 0 previously selected by an .SRC instruction.
The accumulator and carry are not affected.
WRITE INTO RAM STATUS CHARACTER 1
M1
M2
8 1 4 1 211
8 1 4 1 2'1
[11 10101011
WRl
E5
The content of the accumulator is written into the RAM status
character 1 previously selected by an SRC instruction.
The accumulator and carry are not affected.
WRITE INTO RAM STATUS CHARACTER 2
M1
WR2
M2
11110101101
8 1 4 1 211
E6
8 1 4 1 2'1
The content of the accumulator is written into the RAM status
character 2 previously selected by an SRC instruction.
The accumulator and carry are not affected.
WRITE INTO RAM STATUS CHARACTER 3
M1
M2
11110101111
1 1
1
8
4
WR3
21
8
E7
4 1 2'1
The content of the accumulator is written into the RAM status
character 3 previously selected by an SRC instruction.
The accumulator and carry are not affected.
6-11
SUBTRACT FROM MEMORY WITH BORROW
M1
SBM
M2
11110110001
8 14 1 2 I 1
E8
,8 1 4 1 2 1 1
The content of the RAM character previously selected by an SRC
instruction is subtracted from the accumulator with borrow.
The RAM character is unaffected.
READ RAM CHARACTER
M1
12
4 1
4 1
ROM
11110110011
1
1
8
211
8
E9
211
The content of the RAM character is transferred to the accumulator.
The carry is not affected.
The 4 bit data in memory is unaffected.
READ ROM PORT
RDR
12
M1
11110110101
1 1 2118 1
211
8
4 1
4
EA
The data present at the input lines of the port, previously selected
by an SRC instruction is transferred to the accumulator.
The carry is not affected.
ADD FROM MEMORY WITH CARRY
12
M1
11110110111
1 1
1
8
211
4
ADM
8
4 1
EB
211
The content of the RAM character previously selected by an SRC
instruction is added to the accumulator with carry.
The RAM character is not affected.
READ RAM STATUS CHARACTER 0
M1
12
III 10111001
8 14 1 2 1 1
RDO
8 1 4 I '2
I
EC
1
The 4 bits of status character 0 of the RAM register previously
selected by an SRC instruction are transferred to the accumulator.
The carry and the status character are not affected.
6-12 '
READ RAM STATUS CHARACTER 1
Ml
RDl
M2
11110111011
8 1 4 1 211
ED
8 1 4 1 211
The 4 bits of status character 1 of the RAM register previously
selected by an SRC instruction are transferred to the accumulator.
The carry and the status character are not affected.
READ RAM STATUS CHARACTER 2
Ml
M2
8 14 1
8 1 4 1
11110111101
211
RD2
EE
211
The 4 bits of status character 2 of the RAM register previously
selected by an SRC instruction are transferred to the accumulator
0
The carry and the status character are not affected.
READ RAM STATUS CHARACTER 3
Ml
M2
8 1 4 1 211
8 1 4 1 211
RD3
11110111111
The 4 bits of status character 3 of the RAM register previously
selected by an SRC instruction are transferred to the accumulator.
The carry and the status character are not affected.
CLEAR BOTH
CLB
Ml
M2
11111100001
8 1 4'2'1
8 14 1
FO
211
Set accumulator and carry to O.
CLC
CLEAR CARRY
Ml
M2
11111100011
8
1 4 1 211
8 1 4 1
Fl
211
Set carry to O.
The accumulator is not affected.
6-13
INCREMENT ACCUMULATOR
Ml
M2
I
lAC
I
F2
11 1 1 1 0 0 1 0
8 4'2'1 8'4'2'1
'
The content of the accumulator is incremented by 1. No overflow
sets the carry to O~ overflow sets the carry to a 1.
COMPLEMENT CARRY
Ml
11
1
8
1
1
I
4'2'1
CMC
M2
0
o· 1 1
I
F3
8'.1 2 '1
'
The carry content is complemented.
The accumulator is not affected.
COMPLEMENT ACCUMULATOR
Ml
CMA
M2
F4
11111101001
8 ' 4'2'1
8'4 1 2
1
1
The content of the accumulator is complemented.
The carry is not affected.
ROTATE LEFT
III
8
RAL
Ml
M2
111 0
.'2'1
1
F5
011
8'4 1 2 1 1
'
The content of the accumulator and carry are rotated left one
bit position.
A8
A2
A4
Cy
6-14
Al
ROTATE RIGHT
RAR
M1
M2
III 111 0110
8 1 4'2 1 1
F6
1
8 1 4'2 1 1
The content of the accumulator and carry are rotated right 1 bit
position.
A8
A2
A4
Al
Cy
TRANSMIT CARRY AND CLEAR
M1
M2
11111101111
8 1 4'2 1 1
TCC
F7
8 1 4 1 211
The accumulator is cleared.
The least significant position of the
accumulator is set to the value of the carry.
The carry is set to
O.
This instruction is used for decimal arithmetic.
DECREMENT ACCUMULATOR
M1
M2
11111110001
8 1 4'2 1 1
DAC
Fa
8 1 4 1 211
Decrementing when the accumulator equals zero sets the carry to O.
Decrementing when the accumulator is not zero sets the carry to 1 ..
The initial value of the carry bit does not affect the content of
the accumulator.
TRANSFER CARRY SUBTRACT
III 1 III
M1
8 1 4 1 211
TCS
M2
0 011
8 1 4 1 211
F9
The accumulator is set to 9 if the carry is o.
The accumulator is
set to 10 if the carry is a 1. The carry is set to O.
This
instruction is used for decimal arithmetic.
6-15 .
SET CARRY
STC
M1
M2
1111111010
8 1 4 1 2'1
FA
8'4 1 2'
Set carry to a 1.
The accumulator is not affected.
DECIMAL ADJUST ACCUMULATOR
M1
DAA
M2
11111111011
8 1 4 1 2'1
1
8
4
FB
1 2'1
The accumulator is incremented by 6 if either the carry is 1 or
if the accumulator content is greater than 9.
The carry is set
to a 1 if the result generates a carry, otherwise it is unaffected.
This instruction is used for decimal arithmetic.
KBP
KEYBOARD PROCESS
Ml
M2
11111111001
8
1
4 1 2'1
Fe
8'4 1 2'
A code conversion is performed on the accumulator content, from 1
out of n to binary code.
If the accumulator content has more than
1 bit on, the accumulator will be set to 15 (to indicate error).
The carry is not affected.
The conversion table is shown below:
(ACC)
Hex
8
1 0 0 0
3
7
o
o
o
o
9
1 0
2
5
6
0
0
o
o
0
•
o
1
~
0 0
0 1 0
1 0 0
0 1 1
1 o 1
1 1 0
1 1 1
o
1
.
0 0 0
0
o
1
1
0 0 1 0
2
o
0 1 1
3
•
•
0 1 0 0
4
1 1 1 1
1 1 1 1
F
.
.
1 1 1 1
F
1 1 1 1
1 III
F
1 1 1 1
F
•
1 1 1 1
F
~
..
~
1 0 1 0
B
C
1 0 1 1
1 1 0 0
D
1 1
E
III 0
..
F
1 1 1 1
•
1
Hex
..
A
o
after KBP
Binary
4
1
(ACC)
Binary
o
o
o
o
0
6-16
before KBP
.
F
F
1 1 1 1
F
1 1 1 1
F
1 1 1 1
F
1 1 1 1
F
DESIGNATE COMMAND LINE
Ml
DCL
M2
11111111011
8 1 4 1 211
FD
8 1 4'2 1 1
The content of the three least significant accumulator bits is
transferred to the CM-RAM output lines on the cpu.
This instruction provides RAM bank selection when multiple RAM
banks are used. When the CPU is reset, RAM Bank zero is automatically selected.
DCL remains latched until it is changed or
reset.
The selection is made according to the following truth table:
(ACC)
8421
CM-RAMi Enabled
Bank No.
XOOO
CM-RAM
Bank 0
XOOI
eM-RAMI
Bank 1
XOIO
CM- RAM 2
Bank 2
XIOO
CM- RAM 4
Bank 3
XOll
CM-RAMl' CM- RAM 2
CM-RAMl' CM- RAM 4
Bank 4
XIOI
XIIO
Bank 5
CM- RAM 2' CM- RAM 4
CM-RAMI' CM- RAM 2' CM- RAM 4
XIII
Bank 6
Bank 7
A low power TTL one-of-eight decoder may be tied to the CM-RAMI,
CM-RAM2, and CM-RAM4 lines to expand the number of RAM banks to
8. The command lines must be buffered for MOS compatibility.
RAM BANKO
RAM BANKl
16
4004
CPU
ONE
2
2
OF
3
4
EIGHT
4
15
14
13
DECODER 5
6
7
RAM BANK7
The DCL instructions does not apply to PLS 401 and PLS 402 systems
since they have capacity for only 4 RAM devices wired to RAM Bank O.
6-17
7.
IMPLE~1ENTING
PROGRAMMED LOGIC
Logic diagrams using graphic symbology are the key to visualization and implementation of hardwired logic designs.
The sequential
nature of programmed logic does not lend itself to logic diagrams.
The visual and verbal aids available to the program logic designer
are block diagrams, flow charts, register maps, and coding forms.
The designer begins with a block diagram to make input and output,
ROM, and RAM register assignments.
The problem is f,low charted
and detailed assignments made of registers on register maps.
The
flow charts are progressively partitioned into more and more detail until each flow symbol can be converted to program instructions on the coding forms.
The instructions are first written in mnemonic form for easily
verbalizing the solution to the problem. When the complete problem or a workable partition has been solved, the mnemonic instructions are converted to code for the ROM.
The code is programmed
into the ROI·1 and tested with the hard't'Jare on the breadboard system.
SYSTEH BLOCK DIAGRAM
One of the first steps in implementing programmed logic is construction of a system block diagram showing assignment of the
external input and output connections. Figure 7-1 represents a
block diagram work sheet available for PLS-401 systems.
Similar
worksheets for other PLS-400 systems are available.
The worksheet block diagrams show the elements of the PLS systems, and
the lines in and out of the sY$tem that are available to the
designer. Fig-ure 7-1 shows the number of inputs and outputs,
RAM memory capacity, ROM program memory 'capacity, and the CPU
microprocessor, interconnected via the CPU bus. The program
sequenGe stored in ROM program memory controls the interaction
between the elements connected on the CPU bus.
7-1
...J
I
tv
8
&
1
3
5
2
••v••••• ,
-
RAM REG1 STER STORAGE
D
RAr1 0
30 CHAR
~AM 0
OUTPUT
PORT
ROM PROGRAM MEMORY
RAft I
RAM ~
80 CHAR
S(. CHAR
RAM 3
80 CHAR
256 \JO~1)S
OUTPUT
P.oRT
OUTPUT
PORT
OUTPUT
PORT
OUTPUT
PORT
I
2
3
o
1-1-
ROM 0
II
~OM I
256 WORDS
INPUT
PORT
o
).J 256ROMWORDS·
2 II
ROM.3
256 WORDS
INPUT
PORT
I
INPUT
PORT
2
D
INPUT
PORT
3
c
c
Z
~·
EXTERNAl
flOS RAM
. OUTPUT
PORT
. BIT WEIGHT RElATIONSHI.p TO
CPU ACCUMULATOR
ACTIVE lOW STATE INDICATOR
•
t
A
r=~~=-~~~==~~IA
8
6
5
4
FIGURE 7-1
System Block Diagram
2
FLOW CHARTS
The sequential nature of programmed logic fits directly into the
graphic representation provided by flow charts. Programmed logic
being sequential with only yes or no decisions allows for very
simple flow charting procedure5 The graphic symbols used in
examples in this manual are shown in Figure 7-2. The main symbols
being the rectangle for operations and the diamond for decisions.
The rectangle contains an abbreviated statement of the operation
or operations. The diamond contains an abbreviated question concerning the decision.
The PLS 400 systems have only two decision instructions, JCN and
ISZ. Any time a diamond symbol appears in the flow chart one of
these two instructions must be involved. All other instructions
perform operations, either alone or in groups, and are thus
represented by the rectangle. The use of flow charts correlates
to the use of logic block diagrams in hardware design.
The hardware designer progressively partitions his problem into more and
more detailed logic diagrams until each block represents a logic
device.
The program logic designer uses progressively more
detailed flow diagrams to the point where individual instructions
or groups of instructions can be written for each flow symbol.
For
examples of flow charts refer to Section 8 of this manual.
OFF PAGE CONNECTION
SYMBOL (ENTRY)
LABEL
STATEMENT
~
___ OPERATION SYMBOL
PAGE AND WORD
ADDRESS
DECISION SYMBOL
YES
OFF PAGE
CONNECTOR (EXIT)
FIGURE 7-2
Flow Chart
7-3
REGISTER MAPS
In addition to the block diagram and flow charts, register maps
are valuable for visuali~ing register storage allocation. Figure
7-3 illustrates maps for both the index registers and the RAM
registers ..
The index register map shows the 16 four bit registers organized
such that they can be referred to either individually or in pairs
as used by the CPU instructions. The RAM register map shows all
the bits available in one 4002 device.
The organization is four
registers of 20 four bit characters addressable by SRC. Each
register contains 16 characters addressable by SRC and 4 characters addressable by individual instructions.
When using register maps it is helpful to write an abbreviated
mnemonic on the map to verbalize its assignment.
A mnemonic is written for each register used in a routine to show
which registers have been used and what they are used for. When
a register is used for individual flag bits it is helpful to
expand these in a table showing the individual bit assignment.
A convenient place for recording register maps is on the document
containing the flaw chart. Examples of register mapping are
given in Section 8 of this manual.
7-4
INDEX REGISTER MAP
z
REG
w
8 4 2 1 PAIR 8 4 2 1
E
P7
· • •
, I
p6
C
• •
1·
• ·
A •
P5
•
·
·
I
p4
8 ·
•
0
w
C~
>
I
I
··
·
6
4
I
·
I
I
· ·
I
· ·
•
•
·
· ·
2
0
i
1
I
I
I
•,
·
·
I
I
P2
Pl
I
I
I
T
P3
·· ·
I
I
I
"T
j
I
9
7
5
·• ·•
I
•
· ·•
· ·
T
PO
I
F
D
B
· ·
I
·
0
3
I
1
I
RAM REGISTER MAP
REG
STATUS
CHAR
F D 1 2
CHAR
0 1 2 3 4 5 6 7 8 9 A B C D E
-10
.. 10
·10 • ~
.. .
~
~
..
.
~
.
~
..
• I"
..
~
.. ..
.. .. ..
~
.. I- •
• I-- ..
.. .. ..
..
..
.. .
.. ..
~
~
.. .. 10
~
I- ..
lit
I-
•
~
~
~
I-
-
~
--
..
..
~
. . ,. .
-i-- ..
.
-
.. ..
-
I-
• II-
.....
..
..
.~
. .
-I.. I- •
-
~
~
,. .1-
- I-
-
•
~
-~
. " .. ~
.. ..
..
-.
~
to
.. I-
..
. .... ..
. ..... .. " ..
." ..
...... .. . .. .. .... - .. . .. - .. ..
- .... - - -r - . -- .. -
.. I- .. I-
..
·
..
..
~
.. .
..... ~ -
-.. .. .. -
~
~
• to
~
..
~
.. ... . i--
.- ..
~
. . .. ...
~
10
.. I- ....
Ia
..
.. .. ..
I- ....
...
- ..
.. "'"
.. i-
..
.~
.. .I- .. I- .. ..
~
- . . .....
. .. • I- ..
~
..
~
~
I-
8 REG
4
.~
-.. .
I- •
I- •
-- - -- ... . ... . ..
.. ", . .I-
-
..
. .- . .. .
- - --
..
.~
..
..... .. .
· .....
-'"
..
~
•
..
3
I-- ..
2
1
.8 REG
.. - .. .... 4
-.~
-
.. ""
.
2
8 REG
4
..
• to -
-
.. ~ . "'" .. 1
I- ..
... - . .. .. ..
~
.
t- ..
~
1
1
.
• i-- • ~-
0
i-.~
... -'"
2
2
~8
~4
REG
2
3
"" 1
SRC
EVEN
FIGURE 7-3
Register Maps
7-5
HEX CODING FORM
The Hex Coding form, or some variation of the form, is an absolute
necessity for keeping track of the bookeeping details inherrent in
programming.
In addition, when properly implemented, the coding
form becomes the program listing defining how the program accomplishes its task.
The program listing in programmed logic is
equivalent to a combined logic schematic, wire.list and assembly
drawing of a hard-wired logic system.
The hex coding form is divided into two major sections each serving a distinct requirement.
The major portion of the form is used
for mnemonic listing of the program as it is generated. The two
left most columns constitute the second section which provides the
hexadecimal coding of addresses and instructions used by the CPU
and Program memory.
The mnemonic section of the form is completed first as the designer
sequentially lists the program steps in easy to remember mnemonic
form.
When the designer has solidified the mnemonic listing the
hex address and instruction dodes are assigned.
The coding operation of programmed logic is similar to assigning device location,
pin numbers, and wire listing in hardware logic.
The mnemonic listing of instructions in programmed logic is equivalent to the hardware logic operation of creating a logic schematic
diagram where the program designer assembles instructions and subroutines in a mnemonic list and the hardware designer selects gates
MSI and LSI.
Hexadecimal program memory page address.
Single
character for 16 pages of program memory.
Hexadecimal program memory word address.
Twa hex~~
decimal character for 256 words per page of memory
with the least significant hex digit preprinted on
the form.·
o
Hexadecimal instruction word, as cross referenc~d
between mnemonic and hex code from Section 5.
Mnemonic address label used to verbalized the destination of the address control instructions. Addr~ss
labels in this column must appear only once with e~ch
label having unique spelling. This column is left
blank if the line does not require a label.
o
7-6
Mnemonic instructions, usually an abbreviation that
verbalizes the operation. The second word of double
word instructions does not have a mnemonic and is
left blank. The exception is the FIM where the even
register data character is inserted.
See Figure 7-5.
Mnemonic operand which can be blank, data constants,
instruction modifiers, register designation, register
pair designation, or a source address label.
Instructions 0 through 9 and A through D always require
operand information.
I/O, RAM and accumulator instructions never have operand information. See Figure 7-5.
for examples of operands.
o
,
Written comments defining the purpose of an instruction
or a group of instructions.
HEX CODING
MNEMONIC LISTING
, ,
"
~
~~
9.~
~
®
®
MNEMONIC
OPERAND
¢
~
~
~
Q)
COMMENTS
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
_.
F
FIGURE 7-4
Hex Coding Form
7-7
ADR
INSTR
LABEL
MNEMONIC
OPERAND
COMMENTS
0
1
2
INSTRUCTION
EXAMPLES
OPERAND
EXAMPLES
3
4
5
6
7
r-
/
If r-
A
LD
B
FIM~
•
DATA
0
E
.-
BLANK --........
........
F
REG ISTER PAl R
JI
INSTRUCTIONS
/ If r- DATA
/1 /
8
9
c
REGISTER
~
3
RAl ~
JCN ___
r-....
A
PO
D
TJ
STOP
'I)
~
NO OPERAND, BLANK
f/ V
f/ ~ ADD IT IONAl
,'/';"
~
I NSTRUCT ION INFORMATION
ADDRESS LABEL
~
FIGURE 7-5
Instruction and Operand Examples
PLS DESIGN EXAMPLE
An example for implementing an electronic calculator is given to
illustrate the techniques of using the block diagram, flow charts,
register maps, and coding forms.
The problem is defined as being
a four function eight digit calculator where two separate entries
of up to eight digits are operated upon.
Each entry is displayed
as it is keyed into the unit. The result of the operation is displayed following entry of the second operation.
The block diagram is generated as shown in Figure 7-6, consisting
of a PLS 401 system, eight digits of latching display, and a 16
key keyboard.
The keyboard is assigned as a four-by-four matrix,
with four key columns driven by four output lines and the key
closures sensed as four input row lines.
The latching displays are connected for separate strobe inputs and
common BCD data lines plus decimal point. The display data lines
are shared with the keyboard matrix column selection lines. An
additional key is used on the external reset input for a clear
function.
7-8
8
1
&
5
3
2
IIVII'O.,
ROH PROGRAH HEHORY
RAH REG I STER STORAGE
o
RAH 0
RAM I
RAM 2
RAM 0
OUTPUT
PORT
PO
OUTPUT
PORT
PI
OUTPUT
PORT
RAH
3
OUTPUT
PORT
P2
ROH I
ROH 2
ROH
OUTPUT
PORT
INPUT
PORT
INPUT
PORT
INPUT
PORT
2
P3
o
I
o
3
ROH 0
INPUT
PORT
3
c
c
B
~-
A
r-k--=~-=-~=-i--:::t-::~:-=i:'-~,"=C-=-OR=-P=-O=-=R:-':A=T"'"'IO"""N,.,---fl
8
&
5
4
FIGURE 7-6
....J
I
~
,-,-
Electronic Calculator Block Diagram
2
A
A very basic flow diagram, Figure 7-7, is generated which shows
the two major operations of scanning the keys and processing the
data.
In addition, a RAM register map is generated showing assignment of the entries to be processed.
POWER ON
OR CLEAR
INITIALIZE
REG 0 FIRST ENTRY OR RESULT
REG 1 SECOND ENTRY
REG 2
REG 3 ~------------~~~~
~------------~~~~
RAM REGISTER MAP
FIGURE 7-7
First Level Flow Chart
The operation of scanning the keys is expanded upon as shown in
Figure 7-8. The main purpose of this routine is to scan the keyboard matrix for a closure and to debounce the asynchronous key
closures and openings. At this time, three registers are assigned
on the index register map, KEY ROW, KEY COL and COL COUNT. KEYROW
and KEY COL are ,used to'store the row and column bits of a detected
key.
COL COUNT is used to keep track of which column 'is being
scanned.
7-10
EVEN
PAl R
KEYROW
ODD
7
KEYCOL
6
COL COUNT
5
4
3
2
1
a
INDEX REGISTER
MAP
FIGURE 7-8
Flow Chart for Keyboard Scan
7-11
The four key columns are scanned one at a time by rotating a bit
through the columns. As each column is scanned the rows are read
as inputs and tested for a key closure.
If a key closure is
detected a debouncing delay is generated and the same column is
read again.
If the key is still closed, it is checked to determine if the same key had previously been closed.
If the closure
was the same key detected in a previous scan, the routine ignores
the key and returns to scanning the key columns.
If the key was
not previously closed, the row and column of the new key are stored
and the routine exits to process the key.
If no key closure is detected on a column, the column register is
tested to see if a key in that column was previously closed.
If
'it is the same column where a key was previously closed, the
column register is reset indicating that a key was just released.
The routine returns to column scanning.
If the key that was just
released bounces and is detected on the next scan, the debounce
delay and second read should find the key open.
The operation of processing keys from the keyboard is expanded in
the flow chart of Figure 7-9. The purpose of this routine is to
decide the key matrix so the indicated function may be performed.
The KEY COL register is examined to determine if the key closure
occurred in Column 1.
If the closure was in Column 1 the individual bits of KEY ROW are examined to determine which of the
function keys (+, -, X, or ~) was closed.
If the closure was
not in Column 1, ROW 1 is examined to determine if either of the
other functions CE or CP are closed.
If the closure is determined to be a data key, the row and column
data is converted to a single hex character and used as an address
for a lookup table. The table translates the key matrix address
to the appropriate decimal key data.
7-12
KEY
PROCESS
YES
ADD
A+ B
YES
SUBTRACT
A -
YES
CLEAR
ENTRY
B
MULTIPLY
A XB
NO
DIVIDE
A, B
CONVERT ROW
AND COL TO
DA TAD I SPLA Y
CHAR
STORE CHAR
SET DP FLAG
STORE RESULT
DISPLAY RESULT
DISPLAY DP
STORE DP
SCAN
FIGURE 7-9
Flow Chart for Key Process
7-13
Mnemonic Listing for Keyboard Scan
ADR
LABEL
INSTR
MNEMONIC
SCAAi
0
LD
RAL
1
JUJ
2
3
STA~T
4
5
6
7
8
SOiA}
1/07 LAsT
LDM
j.J
1
D
FIM
PO
0
SRc..
0
LD
9
A
WRR
B
RDR
c
JC/J
Ao
No KEY
1= 1M
Po
F
0
F
C
2
1-1.
4
..6L_._
-.- -
IS~
- - - - - ' - - - f-.----
- - - - - - r--L~-~-
r-
RD~
JCfJ
5
6
7
8
9
SET
COL
cotJAJr Fot{ COL 1.
KEY CoL
S E'LEC.T
I. READ KE'/BoAfl..D
I'V
DE BovAlCE
KEy
t
c.i
Ao
1'\1/
17
KEY BOARD
~EAD
I't'
I..,...
CHECK
For<.
T
SAVE
AJEw
Dov8L£t(EY
Ao
SCAAI
A
eLc.
CMA
B
c
XCJ.l
SUg
JcAl
D
E
F
E
E.
At
SAVE COL
0
1
eLc.
2
LD
0
3
SvB
JCAJ
Ao
4
5
6
7
8
'T
'41
1-,-
0
No Key
JCAJ
LAsr COL
~1
1(CH
3
4
JUA/
r-
LJIECK
)F SAMC' CoL
D
F
AI
SCAAI
;=
SCAAI
R.ES ET
KEy
COL
Mnemonic Listing for Keyboard Process
ADR
INSTR
LABEL
KEY'
0
(il{oct=s<;
MNEMONIC
OPERAND
LD
5
6
T
\
RAt{
9
JOJ
B
RAR.
C
JC AJ
0
-
I-- f-E
F
0
f-----
1
---
C HEC/( 11= SuB
RA~
JUJ
r--I-I ME$
LD
9
frL
0
JCA)
E
NoTRow 1
MULT kEV
A I>v B
DIVIDE
LD
Row 1.
- Co
F
'V
T'"
C/-IECK IF
C.LE"~~ EIJTfl.Y
KEY
cl
EAJTAY
l-r CHE.ck. IF
cl
DP
E
IV
1
2
xcH-
/
3
LD
4
f{BP
F
/lE><
5
OAC
6
f<.A t-
7
8
CLC
9
ADD
/
A
J
F
0
Ii USE
c
)(ef!
LOM
>(clf
0
F/A/
Po
It
DECIMAL
Row;' COL
COIJVERT
r
KBF'
DAC
0
1/=
CHECK IF KEY 1$ IAl
T
CLE~I\
B
F
CH Eck,
't'
I-r
AJO! P..OvJ:1.
6
7
8
KEV
'V
T
I
C
J1~L.C~~_ ~:- /-__
4
I - - 1---- 1---- 1-------5
ADD KEV
IF
-
-_
2
CHECK
c./
----------- 1 - - - - - -1 - - - - - - - .. --- - - ------ --
I-- I--}
1
V
I
MIA/vS
A
CoL
+)
C/
FLUS
7
8
15 IAl
)(
i
E
1.0
fi..AR..
JuJ
4
IF KEIJ
CO
!JoT COL.
3
CHECK
f+ -
P-AL
J.UJ
1
2
COMMENTS
or _
F
OJ&IT
Fo~
PO/lilT KEY
ro
LCJoJ(I.)P
.4
TABi..E
P..AL
B
--
E
F
LocA
.-
HEX' 0/&1,
rlOIJ
DISPLAV
AS
APol1E'55
/N
FX
[}EC/MAL Cf/At<
F
5 TO~.£
-
0
1
Coding for Keyboard Lookup Table
Fo
Fl
F2
r=
3
F4
F5
03
"3
F6
0(,
b
F7 01
t=8
F9
FA
FB
F=c
0'2.
BOAR D
M"'TRlk'
TR~/JS/...ATloA..)
9
e
os
~
0$3
Of)
a
Fo 01
FE 04FF 07
-,- KEY
55
I
"'1-
7
\
7-15
When the complete problem has been charted and listed in mnemonic
form the hexadecimal address and instr~ction codes are assigned
on the coding form.
The address and instruction data is then
transferred to the program memory for system and program debugging.
7-16
8.
PROGRAMMING APPLICATIONS
SUBROUTINES
A group of instructions written to perform a function with common
usage is referred to as a subroutine.
The PLS 400 systems have
two instructions, JMS and BBL, which allow subroutines to be used
conveniently and efficiently. The JMS instruction allows the program to exit and perform a common routine and the BBL instruction
at the end of a subroutine causes the sequence to return to the
main program.
As shown in Figure 8-1 the JMS instruction can be used as many
times as needed to execute the same subroutine and automatically
return to the proper place ln sequence in the main program.
Using
subroutines is very efficient in terms of program storage space if
the subroutine is long enough and used often enough.
If a sub'routine is too short or is not used enough it is possible to waste
program storage space. This results because it requires two program locations to enter a subroutine plus one to return in addition to the routine itself. Table 8-1 presents the program
locations that can be gained or lost by using subroutines based
on how many steps in the routine and how many times the routine
occurs. As an example a subroutine of two steps will always
result in a loss of three locations no matter how many times it
is used. A subroutine of three steps must be used four times to
break even.
Subroutines are implemented so that the CPU hardware keeps track
of the return address by storing the program address counter in
the subroutine address stack when a JMS is executed and by
retrieving it back to the program address counter when a BBL is
executed.
Nesting
The subroutine address stack in the 4004 CPU can store up to
three subroutine return addresses. This feature allows nesting
of subroutines as shown in Figure 8-2.
Nesting means that a subroutine may have other subroutines within itself. A one-level
subroutine may have other subroutines within itself. A one-level
subroutine is one which does not contain any other subroutine. A
two level-subroutine contains at least one, one-level subroutine
8-1
MAIN
PROGRAM
JMS
(XXX)
SUBROUTINE
ENTER 1
(XXX)
JMS
(XXX)
BBl
JMS
(XXX)
FIGURE 8-1
Example Showing how a Subroutine can be
Used Many Times From Various Places in a Routine
8-2
TABLE 8-1
Number of Steps Gained or Lost When a Routine
is Executed as a Subroutine
Number of Times Routine Occurs (X)
z
---
1
2
1
-3
-4
-5
2
-3
-3
3
-3
4
3
5
6
7
-6
-7
-8
-9
-x -2
-3
-3
-3
-3
-3
-3
-2
-1
0
1
2
3
x -4
-3
-1
1
3
5
7
9
2 X -5
5
-3
0
3
6
9
12
15
3 X -6
6
-3
1
5
9
13
17
21
4 X -7
7
-3
2
7
12
17
11
27
5 X -8
8
-3
3
9
15
21
27
33
6 X -9
9
-3
4
11
18
25
32
39
7 X -10
10
-3
5
13
21
29
37
45
8 X-II
N
-3
N-5
2N-7
3N-9
4
4N-ll 5N-13
X
6N-15
(N-2) X- (N+l)
8-3
MAIN
PROGRAM
THREE-LEVEL
SUBROUTINE
JMS
{XXX ~
t XXX l
•
TWO-LEVEL
SUBROUTINE
JMS
I.
[YVV]
---r_
[YYV]
BBL
ONE-LEVEL
SUBROUTINE
JMS
(zzz)
•
(zzz)
FIGURE 8-2
Example Showing Nesting of Subroutines
and a three-level subroutine contains at least one, two-level subroutine. The subroutine address stack is referred to as a "pushdown" stack where each time a new subroutine is entered, the stack
is pushed-down with the old return addresses going to the bottom
of the stack and the most current being on top. When a BBL return
is executed the most current or the address at the top of the
stack is used first and the stack is pulled-up one level. The
subroutine stack only has three levels and it is possible to push
the stack down too far by executing more than three JMS instructions without an intervening return.
In order to keep track of
the three subroutine levels, parenthesis (), brackets [], and
braces {} are used as shown below:
Parentheses,
Brackets,
(LABEL X) denotes a one level subroutine.
[LABEL Y] denotes a two level subroutine.
Braces, {LABEL Z} denotes a three level subroutine.
The rules for nesting of mathematical factors apply to the nesting
of subroutines where any lower level subroutine may be nested within a higher level subroutine. A subroutine like a mathematical
factor may not have nested within itself one of its own level or a
higher level.
8-4
Examples of nesting
1.
~ [ (----) ] }
2•
~ [---]
Multiple Ending
[ --- ]
[( --- )
( ---) ] }
Subroutines
The BBL instruction has the feature of forcing a constant value
into the accumulator. This feature can be put to use as shown
in Figure 8-3 where a subroutine can make decisions and terminate
with multiple endings. Each ending can be executed with a BBL
with its own constant value forced into the accumulator. Therefore
the main program could test the accumulator in order to determine
which ending occurred.
SUBROUTINE
ENTRY
(xxx)
~
-
~
ZZZ
JCN
YYY
---...-----1_-
YY Y
JCN
ZZZ
BBL 3
RETURN #3
BBL 2
RETURN #2
l3BL 1
RETURN #1
FIGURE 8-3
Example of a Subroutine With Multiple Endings
8-5
Common Ending Subroutines
In a complex program it is relatively easy to reach three levels
of subroutines. A technique which helps conserve levels.is the
use of subroutine stacking in specialized situations. Figure 8-4
shows an example where subroutines are stacked to share a common
ending. Basically this technique uses a jump unconditional to an
existing subroutine rather than pushing the stack down another
level. This technique is useful only when a JMS occurs at the
very end of a subroutine. When this occurs a JUN is used in place
of the JMS.
This keeps the stack at the same level.
E.NTRY #1
ONE-LEVEL
ENTRY #2
ONE-lEVEL
ENTRY #3
TWO-lEVEL
(XXX)
(yyy)
[ZZZ]
AAA
JMS
~__J~U_N__~
I·
AAA
V
~
I
(WWW)
CCC
•
(WWW)
JUN
CCC
BBl
BBl
COMMON RETURN
FIGURE 8-4
Example of Subroutines Sharing a Common
Ending Sequence (Stacking)
8-6
COUNTING
Counting is one of the logical functions PLS systems can easily do
with the INC, lAC, DAC, and ISZ instructions. The simplest count
is use of INC to perform a binary hex count from 0 through F on
any of the index 'registers. When it is desirable to count greater
than 15, the ISZ instructions may be cascaded to reach any practical value.
The examplerbelow shows cascading ISZ instructions
where the first register overflows, the second register is then
counted, and when the second register overflows the third register
is counted.
This technique can be extended to any number of
registers for large counts.
ADR
o
INSTR
LABEL
=
MNEMONIC
OPERAND
____
_______________________________ _
COMMENTS
-~-- -·-C-O-V-N-T--+-;--l~/-s-~-+---O---+---I-I.J-C-«-EM-e;·/l---7ill.sr--I<,-'-E-6-IS-TE--~-·----------
3
f.--
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T
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I
-.l NC "EMENT
SEcoND -.£GIS iiI?
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LJ
INc:.-
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2.
A
Counters may be used simply to tally up the number of times a
function occurs or in other situations they may be used to control the number of times a function occurs.
In the control
situation, the count is compared to some preset limit and the
routine terminated when the limit is reached. The ISZ instruction provides an efficient means for performing this control
function by counting preset registers and terminating when the
registers overflow.
Two options exist in counting; one is to execute the functions to
be counted before counting and the other is to count first and
then execute. This distinction is important when presetting
registers to be counted.
In the execute and count technique the
function will always be executed at least once, since the decision
to terminate is a function of the count.
In the count and execute
technique it is possible for the count to terminate the routine
without performing any execution. Figures 8-5 and 8-6 show two
ways to implement these techniques.
8-7
IN IT IALIZE
COUNT
INITIALIZE
COUNT
EXECUTE
FUNCTION
TO BE COUNTED
COUNT
COUNT
EXIT
NO
EXECUTE
FIGURE 8-5
FIGURE 8-6
Flowchart of Execute
and Count
Flowchart of Count
and Execute
Coding for execute and count
ADR
INSTR
LABEL
~EKONIC
40
-
41
I--
4~
20
FI"1
Po
~}
00
0
0
44
22
45
£)0
F/~
~
PI
c'
46
-1
7
48
49
4A
4B
4c
4D
4
E
-
$"0
5 1
r. 2
1,""3
S4
~5
5"6
t;7
E"8
1!"«~TIt
M
-
---
70
4""71
4,
73
1<; ?
1+115 '2
1+-1-
72
4"
--
I, INIT/ttLI ze
~-
15
---
~
THE
COUNTEr:
I~
E)(eCUTE
0
r
SoME' PU/V( T-/O/J
CovNTHow
_MAf...IV
E=)(Fcurlo/Us
F. )( r: c u1 Ir
I
E Jc
152
~-.
COMMENTS
--
--
4 F 46
8-8
OPSRAND
f C I)T
C
2
F .1(1:'- (,,,ret.
:3
E)( t:.c: LITe:
i
IV
,-,..
OV~ ~
FLOtA)
0"-
fEA.)(}JI-J&
f(o IJ TJAJ~
Coding for count and execute
ADR
INSTR
LABEL
MNEMONIC
f--1---
0
3
l4
20
FIt}
Po
D.I),
/)0
DI
I=" If.'
Pi
Dz.
£)3
\
0
-r COUIJT
..
(, 6
[) [)~
C. 7
'?O
~ 8
b9
74
71
b A
'14
bB
72
74
t,
73
74
J ~?
CO.JI.}'T
~
.,...
~
F
73
C')(fC-IJH ~
75
76
7
78
79 /
7A b7
7B
Ie
ID
t
THE
CO.JIJ1F~
HQwMAIJ~
E=)(eCUTIOIJS
/
E' J(
(:'
c." T t:
2
F=)r FCUTE
?
'2
-
rJ(rcurr
IT
I
-
72
74
/S,.
1-'- 1~f7IAI./ ~
c: )( t: Cl)T f"
152
I!~-"
70
71
7
COMMENTS
-
bS 22
be
t. D
t. E
OPERAND
-
0
1
2
-'-Jc..AJ
-
01/ F-- k
~LOVJ
~O\J
r UjE
I'V
.... EXECvTE
--
SOME
FU1J~
1 /011./
-r
AI
W
C outJ T
., EN D/Nrr
f<.ovTINE
V
Binary Count
The nature of the ISZ instruction requires that the preset count
provide a binary complement limit of the desired count. For the
execute/count situation the preset value is the complement plus
one and for the count/execute technique the preset value is the
straight complement.
Table 8-2 is presented as a convenience for
determining register settings for counting with cascaded ISZ
instructions.
Register 0 must be set according to whether the
technique is count/execute or execute/count. The total desired
count is determined by adding all the individual register counts.
Example for count of 2387 using execute/count:
Setting
Nx
Reg 2
6
2304
Reg I
A
80
Reg 0
D
3
2387
8-9
TABLE 8-2
ISZ Register Settings for "N" Operations
REG 0
EXEC
COUNT
REG 0
COUNT
EXEC
REG 1
N1
REG 2
N2
REG 3
N3
F
1
F
0
F
0
F
0
F
0
F
0
E
2
E
1
E
16
E
256
E
4096
E
65536
D
3
D
2
D
32
D
512
D
8192
D
131072
C
4
C
3
C
48
C
768
C
12288
C
196608
B
5
B
4
B
64
B
1024
B
16384
B
262144
A
6
A
5
A
80
A
1280
A
20480
A
327680
9
7
9
'6
9
96
9
1536
9
24576
9
393216
8
8
8
7
8
112
8
1792
8
28672
8
458752
7
9
7
8
7
128
7
2048
7
32768
7
524288
6
10
6
9
6
144
6
2304
6
36864
6
589824
5
11
5
10
5
160
5
2560
5
40960
5
655360
4
12
4
11
4
176
4
2816
4
45056
4
720896
3
13
3
12
3
192
3
3072
3
49152
4
786432
2
14
2
13
2
208
2
3328
2
53248
2
851968
1
15
1
14
1
224
1
3584
1
57344
1
917504
0
16
0
15
0
240
0
3840
0
61440
0
983040
EXECUTE
EXECUTE
8-10
REG 4
N4
Decimal Count
All CPU instructions count directly in binary. When it is
necessary to do a decimal count such as for displays, the DAA
instruction becomes useful.
An example of a subroutine to count three decimal decades is given
in Figure 8-7.
The carry is initially cleared. The units decade
is loaded to the accumulator and incremented. The accumulator is
decimal adjusted and the result saved as the new units decade.
The TCC instruction moves the carry, if any, to the accumulator
and the tens decade is added. The accumulator is again decimal
adjusted and saved with the Tce moving any decimal overflow to
the accumulator for adding the hundreds decade.
(COUNT DEC)
CLEAR CARRY
COUNT UNITS
DECIMAL
ADJUST
EVEN
PAIR
E
7
6
5
A
COUNT TENS
DECIMAL
ADJUST
4
3
8
6
4
2
TE~IS
ODD
9
HUNDREDS
UNITS
1
0
COUNT HUNDREDS
DECIMAL
ADJUST
INDEX REGISTER MAP
EX IT
FIGURE 8-7
Subroutine to Count
Three Decimal Decades
ADR
INSTR
0
LABEL
(COUNT DEc)
MNEMONIC
CL~
OPERAND
2
LD
IAC--
-
-
3
DAA
--
-- 4
XCH
S
6
7
ADD
4-
-
r-!- I - - -
5
Tee
°
'>(ClI
Tee
A
ADD
Hi E? AI r
Co U A/
LT
r
DAA
c
'J(Cf./
7
D
8BL
0
TEA/S'
APJUST
'I
/IVCA£MEA/T
7
B
ADJlIST
/IVCR,E/vIEAlT
D£CIMAL
4
UNITS
-r -- - - - - - - - - - 0 - - 0
DECIMAL
SAVE
DAA.
8
9
COMMENTS
- S - - - - +=----i!J a
f)EC/MAL
IfU~/)f(EDS
ADJuST
~
RE
TU~N
E
F
8-11
TIME DELAYS
Time delay circuits can be simulated with programmed logic using
simple counting techniques.
Since each instruction word requires
10.8 microseconds to execute, the simplest time delay can be
achieved by executing a number of nonoperative instructions such
as the NOP.
Using this method, any signi_ficant time delay would
soon use up considerable program memory space.
A more efficient time delay can be implemented using the ISZ
instruction executed so that it loops on itself.
X
ADR
INSTR
LABEL
MNEMONIC
OPERAND
COMMENTS
2 _0
21
22
2
70
5f'lr
I
~
2/
s~
I.-
0
SELF
T
v
TIMF
DE/.
AY
3
For a 10.8 microsecond instruction cycle each executlon of the two
word ISZ instruction uses 21.6 microseconds.
Therefore, if an ISZ
instruction initially starts from 0 and loops through 16 passes
before it leaves the loop, a total of 345.6 microseconds is required.
By cascading two ISZ instructions one after another with the loops
of both returning to the first ISZ, the time delay will be doubled
for each pass through the second ISZ.
)(
ADR
INSTR
LABEL
20
21
22
23
24
MNEMONIC
r-
1 s,?-
21
1--1-
7/
I
I
70
21
I="IRST
~-+
OPERAND
0
COMMENTS
r-
CASC,""VED
TIME
OELAY
J: IR.$T
s-r
2
FIt
D.t
4
s~
JMs
5
00
6
7
-
-
COMMENTS
OPERAND
"T
l)~LA
'I
T
44
!.~.8
TO
.MSE' C
MI//'st!t:..
I
(SJloRre:.J
'V
-
Register pair zero is fetched to the data constants from Table 8-3
to give the delay time required.
(SHORT lI)
COUNT REG 0
EVEN
PAIR
ODD
E
7
6
5
F
4
3
9
A
8
6
4
2
1
2
o
o
COUNT DO
0
COUNT OJ
INDEX REGISTER MAP
COUNT REG I
FIGURE 8-8
Flow Chart of Short Delay
INSTR
70
(SHoR'rA) r' 15'r
01
00
71
/f.IS?
00
4--,
0
2
03
04
05
D6
7
8-14
LABEL
ADR
00
Co
MNEMONIC
BeL
OPE RAN 0
COMMENTS
0
(SHeRT ~)
(OUAJT
I
CovNT
{SHoR..r~J
0
TilE
FI/(ST
RFG/S
THE SEco/.JO
ReT()f(
JMS
7
12.
(
,..-
FErct/
Po
/fIJi)
1"1
BEFoJ(c
GOUJ("
10
( IIAtlo)
V'l~ ~)
(LONG 1I)
SET PAIR 0
FOR 5.8 MS
(VAR 1I)
REGISTER
PAIR 0
EVEN
PAIR
ODD
E
7
6
o
A
5
8
4
9
6
3
7
4
o
2
5
COUNT 02
1
COUNT 03
COUNT DO
0
COUNT 01
INDEX REGISTER MAP
REG I STER
PAIR 1
FIGURE 8-9
Flow Chart of Longer Delay
8-15
ADR
LABEL
INSTR
/1
~
I
I
3
14
I 5
00
'10
16
I
7
12
/8
73
FIN!
0
(VAICA) r-I' IS?
/2-
7/
12
72
1 9
MNEMONIC
(t.olJ(,. .&0)
10 20
0
0
l'f
ser
(VA~ ~)
P~I~
REG-/5TEt
C.OUAJT
I+r.-
Rec.. PA'~ 0
0
(5'.'I/IA,JJ,SEc)
/
2
I~
1--
*1-
(VAf<.A)
Ioe-fBEL
(VA~ .oj
J S'?:
12.
IT
(VA~A)
JS"!
COMMENTS
PO
I+r-
/5%
/A IC~
OPERAND
COIJIJT REG. PAIl< I
F1.oM 5'. g Mill,SE'G
ro
/,~ SEC.
3
o_
~I
RE/liRA!
Control Timeout
By interjecting a test condition within a delay loop, a timeout
can be affected.
In the example given the simplest test condition is used.
If the
test condition occurs with~n the selected time interval the
routine will terminate with the TEST EXIT.
If the test condition
does not occur within the selected time count the routine will
terminate with a TIMEOUT EXIT.
(TIME OUT)
SET COUNT
EVEN
PAl R
ODD
E
F
5
TEST
8
EX IT
6
7
6
5
4
3
4
2
A
B
9
7
3
1
2
COUNT DO
o
a
COUNT 01
INDEX REGISTER MAP
FIGURE 8-10
TIME OUT
Flow Chart of Control Timeout
EX IT
ADR
INSTR
12.0 CO
21
22
c--
19
. I(T/ME
MNEMONIC
au r J
TEST
,~
24
26
Po
Do
JCN
D,
TJ
EXIT
70
ZZ
71
27 22
28
OPERAND
FIN!.
'23
1---
25
8-16
LABEL
CO
IS-r
...... -
0
TEST
IS~
:..-BBL
J
TEST
0
COMMENTS
iT
I~
';;,ET
TIMEOUT
IT
E>(lr 1;=
I~'
IT
COIJIJT
CPU
HI E
C.oUIJT
INpuT
TEST
TIMEotJ
T
I
I
Il'
RETuluv'
0/./
TIMEouT
occuf(S
Holdover
A variation of the timeout subroutine is the holdover, where the
timeout count is reset if the test condition occurs.
(HOLDOVER)
SET COUNT
EVEN
PAIR
ODD
7
F
6
D
A
5
8
4
3
5
3
2
1
COUNT DO
0
COUNT DI
INDEX REGISTER MAP
FIGURE 8-11
Flow Chart of Holdover
ADR
0
INSTR
LABEL
I( HOL
MNEMONIC
DOVER)
TEST
I
Do
DJ
-.v
T
3
is?
4
5
~ I-
6
7
8
~
TJ
JCA)
~
-
COMMENTS
Po
1
2
OPERAND
FIM
(HoLD OVE~) .'40
T
TEST
I
/5 ?
I
I
BeL
ES T
0
SET
HOLD 0 Vcr<
RESt="T
COUNT
CovNT
COUNT
IF
CPU
r F5 T
INPVI
Occ ACC
~O
0
CO
REG = ACC
0
1
AO
REG <' ACC
REG < ACC
REG > ACC
~O
1
X
1
Al • Cl
Cl
~O
0
CO or AO
0
1
~O
X
REG ~ ACC
Al
(Compare) Four Bits
A subroutine which indicates only equal or.not-equal conditions
is sufficient in many applications.
In this example the carry
bit is cleared, register 7 is loaded to the accumulator and
register 5 is then subtracted from the accumulator.
The JCN
instruction tests the accumulator and goes to a BBL 1 return if
zero, or clears the carry and .does a BBLO return if nonzero.
Some features of this routine are that the registers are unaffected
and the compare condition is available in either the carry bit or
the accumulator.
CLEAR CARRY
LOAD CHAR B
SUBTRACT
CHAR A
EVEN
PAiR
ODD
7
F
6
6
5
4
3
DATA B
4
2
DATA A
A
RETURN WITH
ACC = 1 AND CARRY
(A
= B)
8
=1
1
o
0
INDEX REGISTER MAP
CLEAR CARRY
RETURN WITH
Ace
(A
~
=0
A~D
G=0
B)
FIGURE 8-12
(Compare) Four Bits
8-18
9
7
ADR
I--
1--
LABEL
INSTR
80
f:/
'8
8
1
2
8
A3
95
3
8
MNEMONIC
CC.OA-1PARET
OPERAND
eLf,,- ---7
COMMENTS
COMPA~E
r
LD
Ie.
.suB
~
JCN
AI
8(,
r
CI
I 88L
96
87
FI
3i/S-
._- ...-
I
CI
OR
AI
EQUAL $
0
CO
oR
AO
EQVAL$
COMPA~E
CLC
BBL
CO
__
No COMPARE:
4
? 5
No COMPARE~
REGISTER.S
--_ ..
NO
coMPARE:
8
(Compare) Eight Bits
A variation of the preceeding routine is presented which provides
equal or not-equal comparing of 8 bits. This routine provides the
same features as the 4 bit routine and can be extended in increments of 4 bits to any practical length.
CLEAR CARRY
LOAD CHAR B]
SUB CHAR A]
NO
EVEN
PAIR
ODD
7
F
6
CLEAR CARRY
LOAD CHAR B2
SUB CHAR A2
A
5
8
DATA B1
DATA A1
6
DATA B2
4
3
4
DATA A2
2
9
1
RETURN WITH
ACC = ] AND CARRY
o
=
(A = B)
0
INDEX REGISTER MAP
CLEAR CARRY
RETURN WITH
ACC = 0 AND CARRY
=0
(A" B)
FIGURE 8-13
(Compare) Eight Bits
ADR
INSTR
80 PI
81 A3
82 95'"
83
Ie
I-- ~4
88
85
LABEL
8B FI
s:(0.1-
ADD
t;'
XCII
HBJ..
AOD
IT ADD REG 8
~
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8-23
MULTIPLICATION
The two methods of multiplication are the brute-force method and
long-hand method.
Brute-Force Method
Multiply is accomplished with repeated addition.
Beginning with
a number to be multiplied (Multiplicand) and a number to multiply
by (Multiplier) the brute-force method adds the multiplicand
repeatedly into the product, doing the addition as many times as
designated by the multiplier.
This method is sufficient and sometimes appropriate for small numbers but can take considerable time
for large numbers.
One example of the brute-force method of multiply is given where
the multiplicand is multiplied by a constant K.
The routine clears
the product registers, sets the multiplier to K and then adds the
multiplicand to the product, K times.
Since the ISZ instruction
is used to count K, the complement plus one must be used for the
constant.
Table 8-2 is useful for determining these constant.
It
should be noted that this routine performs the execute/count
sequence as defined in the section on counting.
16 BITS
IA I
8 BITS
X
16 BITS
4
I
B
5
I
I
8
9
Multiplicand
6
7
Multiplier
2
3
Product
Registers used in multiply examples
CLEAR PRODUCT
LOAD
MULTIPLIER
CONSTANT K
EVEN
PAIR
ODD
7
F
D
6
A
ADD
MULTIPLICAND
to PRODUCT
8
6
4
2
MPL ICAND
MPLICAND
MULT K
PROD
PROD
o
2
1
MPLICAND
MPL ICAND
MULT K
PROD
PROD
0
INDEX REGISTER MAP
NO
FIGURE 8-16
Brute-Force Method of Multiplication
8-24
5
4
3
9
ADR
IA
IA
LABEL
INSTR
22
lMULT brK/
MNEMONIC
F/A.4
00
0
2.4-
PIttA
00
0
4
2f,
A5
[)I.P'7
Filii
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2
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A 7
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T/{E/A.O{)UCr
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MULTIf'L.IFI(
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( ADD)
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A B A6
Ac CO
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K
f>l{oDc.Jcr
ADD I( TtIV//?.5
BBL
6
ADD KTIMFS
0
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Long-Hand Method
Consider an example of multiplying six by seven.
The brute-force method suggests adding the number 6 to the product,
7 times for the result. Now consider the example again as shown
done in the long-hand method.
Multiplicand
Multiplier
0110
x) 0111
0110
01100
011000
+) 0000000
Product
101010
=
=
=
=
=
=
=
6
7
1 x 6
2 x 6
4 x 6
8 x 0
=
=
=
=
6
12
24
0
42
When done by the long-hand method only three additions are needed.
Each bit position of the multiplier containing a 1, adds the multiplicand times the multiplier bit position weight. Multiplying the
multiplicand by the bit position weight is accomplished by a left
shift operation.
An example of the long-hand method of multiply is given where the
multiplier can be variable. The routine shifts the multiplier
right and tests the LSB in the carry bit.
If the LSB is 1, the
multiplicand is added to the product.
If the LSB is 0 the addition is skipped.
The multiplier is tested for all zeroes to
determine completion.
If the operation is not complete the multiplicand is shifted left one place to multiply it by the current bit
position weight.
The routine then proceeds as above testing the LSB
and adding until the multiplier becomes all zeros.
This routine assumes the product area is initially cleared.
In
addition, overflow is stored in the carry bit and can be tested
by the main program. The multiplier and multiplicand are not
saved. Note that the entry point [MULT] is not at the beginning.
The (ADD) subroutine is given in the section on addition.
8-25
SHIFT
MULTI PLI CAND
LEFT
SHI FT
MULTI PLI ER
PAIR
EVEN
RIGHT
ODD
7
6
NO
MPLICAND
MPLI ER
5
4
3
PROD
2
PROD
PROD
1
PROD
A
MPLI CAND
8
MPLICAND
6
4
o
ADD
MULTI PLI CAND
MPLI CAND
MPLI ER
0
INDEX REGISTER MAP
TO PRODUCT
NO
FIGURE 8-17
Long-Hand r1ethod
of Multiplication
ADR
INSTR
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MNEMONIC
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8-26
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OA.JIE. PosJ"rto/li
SQUARE ROOT
There are various formulas for approximating the square root of a
number. There is also the long-hand division technique learned in
grade school. As shown in the example using a decimal number the
technique is to first separate the number into pairs of digits. A
trial divisor is then selected for the most significant pair. When
one is found that gives zero or the smallest positive remainder it
is saved as a partial result. This partial result is doubled and
multiplied by ten to become the basis for a new trail divisor. A
new trial divisor digit is added to the doubled partial result.
The new trail divisor operates on a new partial remainder, again
looking for zero or the smallest positive remainder. The new partial remainder consists of the division remainder plus the next two
digits of the dividend.
Doubled
Partial
Result
}
Trial Divisor #1
1
2
2
24
8
Trial Divisor #2
Trial Divisor #3
I
~
Partial Result #1
Partial Result #2
Ll
Trial
Digit
8 - Pinal "Result
Dividend
VOl 63 84
1
Partial Remainder #1
00 63
44
Partial Remainder #2
19 84
19 84
Final Remainder
00 00
1
2
FIGURE 8-18
Example of Decimal Long-Hand Square Root
The long-hand square root technique also works for binary numbers
and in fact is simpler because of the binary operations.
In binary
there are only two trial choices, 1 or 0 and to double the partial
result is simply a shift left, as is multiplying the partial result
by the number base. Also, the final result can be derived from the
trial division by shifting right one place at the end of the operation. This allows the quotient and divisor to use the same register.
Trial Divisor Digit
1
0
0
10
0
100
0
1000
1
10010
1
Trial Divisor
1
VOl
01
00
00
0 0 1 1
01 10 10 01
Partial remainder #1
01
00
(f06T 10
·00
01
1
0
Dividend
00
10
00
10
10
00
Partial remainder #2
10
01
01 01
01 01
00 00
Partial remainder #3
Partial remainder #4
Final remainder
FIGURE 8-19
Example of Binary Long-Hand Square Root
8-27
A programming example for the square root of a 16 bit integer is
given.
The routine initializes the remainder and quotient and
sets a pass counter for the 8 pairs of the 16 bit integer.
Two
bits of the integer are shifted into the partial remainder area
where the trial divisor is subtracted.
Before the subtractions,
the trial divisor is doubled and set to "I".
If the subtraction
gave a positive result the new partial remainder is saved and the
trial "I" is inserted into the combined quotient-divisor as a
result.
If the subtraction gave a negative result, the trial "1"
bit is removed from the divisor.
The process of shifting two bits into the remainder and subtracting the trial divisor is repeated for 8 passes. When the operation
is complete, the trial divisor is shifted right one place to obtain
the quotient.
This subroutine requires approximately 8.3 milliseconds to execute
when the CPU clock is 10.8 microseconds.
DIVISOR & QUOTIENT
DIVIDEND
5
4
7
REMAINDER
CLEAR
REMAINDER
CLEAR QUOT lENT
SET 8 PASSES
SH I FT TWO BITS
TO REMAINDER
TRY A "1"
DOUBLE RESULT
SUB RESULT
FROM REMA I NDER
SAVE REMAINDER
A
8
REMAINDER
DIVIDEND
CIVIDEND
6
YES
4
DIVISOR
7
6
5
4
3
2
NEW REMA I NDER 1
o
USE NEW
REMAINDER
INSERT "1"
IN RESULT
0
REMOVE THE
TRIAL "1"
RECOV~R
FIGURE 8-20
, Flowchart for Long-Hand
Square Root
8-28
REMAINDER
REMAINDER
DIVIDEND
DIVIDEND
DIVISOR
DIVISOR
NEW REMA INDER
COUNT
INDEX REGISTER MAP
NO
RESULT
FROM DIVISOR
ODD
PAIR
EVEN
9
Program for square root subroutine
ADR
0
1
2
I-'--- -
INSTR
LABEL
L SQ
RooT}
MNEMONIC
P7
FIN!
p(,
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5
6
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8-29
Subroutines used in [square root]
INSTR
ADR
I-1-.
-.-
LABEL
MNEMONIC
(FC[)AE'?"f.~ )
0
OPERAND
CLC
/IJ ~ ____J__
1
2
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F
6
7
BBL
0
3
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0
INSTR
LABEL
F
MNEMONIC
(74S(CH
S
4
LD
4-
r-- f-3
5
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6
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LD
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TO CPU
r
INPUT
1
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L
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DISTRIBUTOR
TTY
(NORMALLY CLOSED, LOGIC 1)
20 rnA
r
I
+5
20 V (-)
~
4.7 K
TELETYPE
FROM CPU
OIJTPUT----1VttA
4.7
•
K
I
r
....-----. +5
I
L ___ _
TTY SELECTOR
-RrrAY(~ ~
---';'-'-&.--
MDW)-I
470[1
o. J
llF
-10 V
100[1
L
_ _ _ _ _ _ _ -1
I
P.ELAY
COIL CONTACTS
12 V
6000.
TELETYPE INTERFACE
FIGURE 8-21
Teletype Interface
TELETYPE
15 VA
Full-Duplex mode allows the TTY to be used as an input and output
device in LINE operation. The separate send and receive allows the
~ata terminal to edit the input data before printing and/or punching the output data.
TTY PRINTER
OR PUNCH
~
-
DATA TO TTY
TTY
INTERFACE
TTY KEYBOARD
OR READER
DATA
TERMINAL
DATA FROM TTY.
r
Remote Reader mode allows the TTY paper tape reader to be activated
by a remote device in LINE operation. This mode would be used in
conjunction with Simplex Send or Full-Duplex operation.
In FullDuplex, the remote reader control allows paper tape editing.
TTY REQUIREMENTS
The full PRO-LOG TTY interface requires specific teletype configurations. The general configuration. requires a TTY modified for FullDuplex and Remote Reader Control. Specifically there are three
circuit connection requirements for the TTY:
(1)
(2)
(3)
20 rnA neutral loop send
20 rnA neutral loop receive
15 volt neutral loop reader control
TTY FORMAT
The programming examples given here assume a serial by character,
serial by bit TTY data format as shown in Figure 8-22.
The character structure consists of a minimum of ten equal time intervals;
one start bit, 8 data bits and at least one stop bit. When the
TTY is in a stopped state the line is held in the logical 1 state.
The first transition on the line is always a start bit (logical 0).
8-33
9
MILLISECONDS
-i
STOP
BIT
START
BIT
t-r-r-r-r-r-r-r-r-j1W"
bl
b2
b3
b4
b5
b6
b7
b8
_.J _ .J _ .J _ .J _ ..J _ .J _ .J _
STOP
BIT
FIGURE 8-22
TTY Data Line Format
The character set assumed is 7 level ASC II plus parity with the
codes de£ined as in Figure 8-23. The bit sequence is least significant bit first, to most significant in ascending consecutive order.
A character parity bit follows the most significant bit of the data
character. The character parity is assumed to be even over the
eight bits i.e., an even number of I bits per character including
the parity bit.
With a full duplex TTY interface various methods can be used when
reading. The most common method is to simply echo each bit back
to the TTY as it is detected and print the incoming character
immediately. Another method is to completely read the entire TTY
character and then issue a separate print response to the TTY only
if desired. This allows the incoming data to be edited before
printing.
TTY Read without Echo
In this example the program is written to receive from the TTY
without echoing a print response. The program reads the TTY input
line searching for a start bit. When the start bit occurs, the
program clocks off 4.5 milliseconds of delay and then makes eight
periodic samples, one every 9 milliseconds. At each 9 milliseconds
sample the TTY input is read as either a I or 0 bit. The eight
serial bits are assembled into the ASC II character by shifting the
bitsinot a data storage area. When the eight bits have been read, .
an additional 9 milliseconds interval is generated to prevent the
proqram from returning to a subsequent read too early.
8-34
~
b6
B.
~
. . ..
bS
~
0
0
0
00
0
1
1
0
0
11
b4
t
b3
t
b2
t
bl
t
0
0
0
0
0
NUL
DLE
SP
0
0
0
0
1
1
SOH
DCl
!
1
~-
Row
-I-
0
2
1
10
3
0
4
10
1
11
0
11
5
6
7
@
P
\
P
A
Q
a
q
1
0
0
1
0
2
STX
DC2
"
2
B
R
b
r
0
0
1
1
3
ETX
DC3
#
3
C
S
c
s
0
1
0
0
4
EaT
DC4
$
4
D
T
d
t
0
1
0
1
5
ENQ
NAK
'is
5
E
U
e
u
0
1
1
0
6
ACK
SYN
a
6
F
V
f
v
7
G
\':1
g
w
8
II
X
h
x
Y
i
y
0
1
1
1
7
BEL
ETB
I
1
0
0
0
8
BS
CAN
(
1
0
0
1
9
HT
EM
)
9
I
1
0
1
0
10
LF
SUB
*
:
J
Z
j
z
1
0
1
1
11
VT
ESC
+
;
K
[
k
j
1
1
0
0
12
FF
FS
,
L
l
I
-
\
1
1
1
0
1
13
CR
GS
1
1
1
0
14
SO
RS
1
1
1
1
15
SI
US
/
=
M
I
I
m
}
'.
N
A
n
~
?
a
-
0
DEL
Control Characters
NUL
Null
DLF.
Data Link Escape
SOH
Start of Heading
DCl
Device Control 1
STX
Start of Text
[)C2
Device Control 2
ETX
End of Text
DC3
Device Control 3
EaT
End of Transmission
DC4
Device Control 4 (Stop)
ENQ
Enquiry
NAK
Negative Acknowledge
ACK
Acknowledge
SYN
Synchronous Idle
BEL
Bell (audible or attention signal
ETB
End of Transmission Block
BS
Backspace
CAN
Cancel
HT
Horizontal Tabulation (punched
card skip)
LF
Line Feed
VT
vertical Tabulation
FF
Form Feed
CR
Carriage Return
SO
Shift Out
SI
Shift In
EM
End of Medium
SUB
Substitute
ESC
Escape
FS
File Separator
GS
Group Separator
RS
Record Separator
US
Unit Separator
DEL
Delete
FIGURE 8-23
TTY Character Set
8-35
EVEN
PAIR
ODD
E
7
6
F
C
A
8
6
4
TTY MSD
2
DELAY
DELAY
o
5
4
3
o
B
9
TTY LSD
2
1
0
DELAY
DELAY
INDEX REGISTER MAP
FIGURE 8-24
Flow Chart for TTY Read without Echo
8-36
7
5
Mnemonic Listing for TTY Read
ADR
INSTR
LABEL
lRD Try 7
0
1
2
MNEMONIC
Jc.AJ
OPERAND
COMMENTS
TO
'T
'lI
LRD TTY-}
FII'oI1
7
JA45
3
4
(SHORT" A)
5
6
7
Fltvf
0
8
JMS
NeXT BIT
FZg
A
CLB
B
JGA,)
;
NO BIT
T/
BIT
IS?
sNE}(T BIT
1
.JM<'"
2
IT
I'f'
BBL
TIIL1E
OJJE
8' /3ITS
BIT TIM£:-
CLE~f{
BIT
~EAO
OAJE
TTY
BIT
BIT
PitTA
ROTA rE
BITS It.JTO
PA/~
3
t
f
REAl)
'if
BIT<:'
it
T
(9 Ms)
3
4
5
BIT
I~
I,
(RoT P3""';')
0
SET COvAlT 1=' ()~
SET
JMS
F
OAJE -HALF
~
IT
$TC
0
DcLA'/
IT DELAY
No
c
"T"'
I'f'
(9 MS)
9
E
Po
3
5r"'~T 7flT
FIN!)
SToP
BIT
[)ELAY
\Y
0
6
7
8
E
LO
P..M,
XCJ.#
LO
KAR
XCH
F
BBL
9
A
B
c
0
(RbT P3-:;:.)
6
Si/IFT
REG
~
! 7 RIGHT
OAJE
ILACE
<0
7
7
(')
8-37
APPENDIX A
SYMBOLS AND DEFINITIONS
The symbols and definitions presented in this appendix are used
throughout PRO-LOG documentation.
BACKGROUND INFORMATION
Physical and Active States in Binary Logic (0 and 1)
Binary logic implies a two-state system. In physical applications
of binary logic, the two states can be any meaningful pair of
physical states such as high/low, positive/negative, in/out, up/
down, etc that will either cause a function to happen or to not
happen.
Binary Operations
Binary logic application is governed by the rules of Boolean
Algebra. There exist only three operations in Boolean Algebra;
AND, OR, NOT (invert).
AND
AND implies a combination of two or more active conditions
to achieve a result.
OR
OR implies a choice between two or more active conditions to
achieve a result.
NOT
NOT implies the negative or inverse. Since there are only
two states in binary logic, the inverse of a function must
always assume the opposite state, thus 0 = 1, I = o.
Duality of Operations
The inherent property of the NOT operation establishes a dual
relationship between the AND and OR operations. The dual relationship is such that the AND and OR functions can be interchanged if
the active conditions (0 and 1 states) are inverted. This property is stated as De Morgan's theorem in Boolean Algebra.
A-I
The importance of this property in physical systems is that the
active state can and will assume either physical state if the
logic operations have been assembled to achieve a result.
DEFINITIONS
Logic Block Diagram
A logic diagram is one which depicts logic functions with no
reference to physical implementations.
It consists primarily of
logic symbols and is used to depict all logic relationships as
simply and understandably as possible. Nonlogic functions are
not normally shown. This basic logic diagram is used for educa~
tional purposes. The purpose of the logic block diagram is to
communicate the overall system concept.
Detailed Logic Diagram
A diagram that depicts all logic functions and also shows nonlogic functions, locations, pin numbers, test points, and other
physical elements necessary to describe the physical and functional aspects of the logic is a detailed logic diagram. The
detailed logic diagram is used primarily to facilitate the rapid
diagnosis and localization of equipment malfunctions.
It also is
used to verify the physical consistency of the logic and to prepare fabrication instructions. The symbols can be connected by
lines that represent signal paths or can be cross-referenced
through the use of mnemonic identifiers.
Logic Function
A logic function is a combinational, storage, delay, or sequential
function expressing a relationship between signal input(s) to a
system or device and the resultant output(s). Logic functions are
expressed graphically with the use of logic symbols.
Logic Symbol
A logic symbol is the graphic representation of a logic function.
Symbol Orientation
The orientation of a symbol on a diagram does not alter the meaning of the symbol. However, logic diagrams indicate direction of
signal flow by symbol orientation and should, therefore, be logically oriented, consistent with the overall information flow.
Symbol Line Thickness
The weight of a line does not affect the meaning of a symbol.
specific cases, a heavier line may be used for emphasis.
A-2
In
Symbol Size
A symbol.may be drawn to any proportional size that suits a drawing, depending on the reduction or enlargement anticipated. Relative sizes of the symbols should be equivalent for related functions.
Table of C~mbinations
For purposes of this standard, tables of combinations describe the
active input/output conditions of the basic logic functions; i.e.,
HIGH (H) more positive, and LOW (L) relatively less positive or
negative.
Identifiers
Identification information is required on and adjacent to logic
symbols to specify unique location of logic function on the drawing,
within the equipment and its circuit diagram.
Identification is
required for clarity as follows:
a.
Notations shall be placed about the periphery of
symbols to identify input and output pin numbers
and test points.
b.
Line conditions, signal routing, etc may also be
labeled for clarity.
c.
Details such as stylized waveforms and timing durations may be included when required for clarity.
Mnemonic Identifiers
A mnemonic identifier is a name given to a logic function output
for the purpose of cross-reference identification.
It is usual
practice to assign a meaningful name for the purpose of implying
what function is being accomplished.
These identifiers can be
words, abbreviations, word-number combinations, numbers or symbols.
In all cases when mnemonic identifiers are used, they must always
appear identically written.
Signal Flow Direction
Logic Diagrams indicate direction of signal flow by symbol orientation, preferred. signal flow direction is from left to right. For
increased clarity, arrows superimposed on lines may be used. However, arrowheads shall not be placed immediately adjacent to any
graphic symbol input or output.
Stylized Waveforms
Stylized waveforms may be placed adjacent to signal lines (where
required) to indicate the nature and timing of the signals.
A-3
SYMBOLS
Line Symbols
Single Channel Path
Multiple Channel Paths
nl
;
n = Number of Channels
Example:
Multiple Channel Paths With Junction
Signal Paths Crossing With no Connection (not necessarily
perpendicular)
Junction of Signal Paths
Single Paths:
1
Signal Flow
A-4
Multiple Paths:
1
Inputs and Outputs
Preferred (left to right signal flow, no arrows required)
I
Inputs
I
I
Outputs
I
Undesirable But Acceptable (right to left signal flow,
arrows required for clarity)
Outputs
Inputs
A-5
Logic Symbols for Binary Operations
Low Level State Indicators
A small circle symbol at any input or output of a function is
used to represent the active low state. A small circle at
the input indicates that the relatively low (L) input signal
activates the input. Conversely, the absence of a small
circle indicates that the relatively high (H) input signal
activates the input. A small circle at a symbol output
indicates that when the function is activated the output
terminal is relatively low (L).
NOT ( Invert)
The NOT function is implied when a high input activates a
low output or a low input activates a high output. This is
represented in its simplest form using the appropriate symbol
below.
The invert function using low level state indicators
applies to AND, OR, and other more complex symbols.
-{>-[>AND
The symbol shown below represents the AND function.
The AND
symbol can be used with active low state indicators as shown
in Table A-I.
The AND output is active only if all inputs are
active.
OR
o
The symbol shown below represents the OR function.
The OR
symbol can be used with active low state indicators as shown
in Table A-I. The OR output is active only is anyone or
more inputs is active.
D
A-6
TABLE A-I
Table of Combinations
The following table of combinations.illustrates the applications
and functions of two variables illustrating duality and use of
low level state indicators.
AND
=D-'x
A
B
A
B
A
B
A.
B
B
A
B,
A
B
A
B·
B
~X
'~x
A
=:[)-
A
=D~
B
X
X
H
H
L
L
H
L
H
L
H
L
L
L
=D--x
H
H
L
L
H
L
H
L
L
H
L
=:[>-x
H
H
L
L
H
L
H
L
L
H
L
L
H
H
L
H
L
H
L
L
L
L
H
L
H
L
H
L
H
H
H
L
X
H
H
L
L
H
L
H
L
H
L
H
H
X
H
H
L
L
H
L
H
L
H
H
L
H
H
H
L
H
H
L
H
~
A
A
=[J--
A
A
OR
X
B
B
B
X
A
B
A
X
B
A
X
B
~x
A
B
..l
=D-
=D~
=:D-~
X
L
X
X
H
H
L
H
L
L
L
L
H
A-7
APPENDIX B
TABLE OF POWERS OF TWO
n
1
2
4
8
16
32
64
128
o
1
2
3
1.0
0.5
0.25
0.125
0.062
0.031
0.015
0.007
5
25
625
812 5
11
0.003
0.001
0.000
0.000
906
953
976
488
25
125
562 5
281 25
096
192'
384
768
12
13
14
15
0.000
0.000
0.000
0.000
244
122
061
030
140
070
035
517
625
312 5
156 25
578 125
65
131
262
524
536
072
144
288
16
17
18
19
0.000
0.000
0.000
0.000
015
007
003
001
258
629
814
907
789
394
697
348
062
531
265
632
5
25
625
812 5
1
2
4
8
048
097
194
388
576
152
304
608
20
21
22
23
0.000
0.000
0.000
0.000
000
000
000
000
953
476
238
119
674
837
418
209
316
158
579
289
406
203
101
550
25
125
562 5
781 25
16
33
67
134
777
554
108
217
216
432
864
728
24
25
26
27
0.000
0.000
0.000
0.000
000
000
000
000
059
029
014
007
604
802
901
450
644
322
161
580
775
387
193
596
390
695
847
923
625
312 5
656 25
828 125
268
536
1 073
2 147
435
870
741
483
456
912
824
648
28
29
30
31
0.000
0.000
0.000
0.000
000
000
000
000
003
001
000
000
725
862
931
465
290
645
322
661
298
149
574
287
461
230
615
307
914
957
478
739
062
031
515
257
5
45
625
812 5
256
512
1 024
2 048
4
8
16
32
4
5
6
7
8
9
10
4
8
17
34
294
589
179
359
967
934
869
738
296
592
184
368
32
33
34
35
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
232
116
058
029
830
415
207
103
643
321
660
830
653
826
913
456
869
934
467
733
628
814
407
703
906
453
226
613
25
125
562 5
281 25
68
137
274
549
719
438
877
755
476
953
906
813
736
472
944
888
36
37
38
39
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
014
007
003
001
551
275
637
818
915
957
978
989
228
614
807
403
366
183
091
545
851
425
712
856
806
903
951
475
640
320
660
830
40'
0.000 000 000 000 909 494 701 772 928 237 915 039 062 5
1 099 511 627 776
625
312 5
156 25
078 125
B-1
APPENDIX C
HEXADECIMAL/DECIMAL INTEGERS
Hex
Decimal
Hex
Decimal
Hex
0
1
0
268,435,456
536,870,912
0
1
0
0
1
4,294,967,296
8,589,934,592
12,884,901,888
17 , 179 , 869 , 184
2
3
4
2
3
4
5
21,474,836,480
5
6
7
25,769,803,776
6
30,064,771,072 7
8 34,359,738,368 8
9 38,654,705,664 9
A 42,949,672,960 A
B 47,244,640,256 B
805,306,368
1,073,741,824
1,342,177,280
1,610,612,736
64,424,509,440
9
F
5
6
7
1,879,048,192
2,147,483,648 8
2,415,919,104 9
2,684,354,560 A
2,952,790,016 B
C 51,539,607,552 C 3,221,225,472
D 55,834,574,848 D 3,489,660,928
E 60,129,542,144 E 3,758,096,384
F
2
3
4
4,026,531,840
8
Decimal
Hex
Decimal
0
1
0
1,048,576
2,097,152
0
16,777,216
33,554,432
F
8,192
12,288
16,384
20,480
2
3
4
5
6 24,576
7 28,672
C 12,582,912
8 524,288
9 589,824
A 655,360
B 720,896
C 786,432
D 13,631,488
E 14,680,064
F 15,728,640
D 851,968
E 917,504
F 983,040
8 32,768
9 36,864
A 40,960
B 45,056
C 49,152
D 53,248
E 57,344
F 61,440
4
5
5,242,880
6
6,291,456
3,145,728
4,194,304
177,440,512 7
7,340,032
134,217,728 8 8,388.608
150,994,944 9 9,437,184
167,772,160 A 10,485,760
184,549,376 B 11 ,534,336
of up to nine characters in length to their decimal
0
1
5 327,680
6 393,216
7 458,752
83,886,080
100,663,296
HEXADECIMAL TO DECI~lAL
This table allows for conversion of hexadecimal numbers
0
4,096
1
2
3
4
50,331,648
67,108,864
251,658,240
7
0 0
0
1 65,536
2 131,072
3 196,608
4 262,144
2
3
4
C 201,326,592
D 218,103,808
E 234,881,024
Hex Decimal Hex Decimal Hex Decimal Hex Decimal Hex Decimal
6
5
0
0
256
1
2
3
4
5
512
768
1,024
1,280
6
7
1,536
1,792
6
7
8
2,048
2,304
9
9
A
B
C
D
E
F
0
16
32
48
64
80
96
112
5
128
144
8
2,560
2,816
3,072
3,328
3,584
3,840
3
A
B
160
176
C
192
D
208
224
240
E
F
0
0
1
2
2
3
4
3
4
1
5
5
6
7
8
6
7
8
9
A
9
10
B
11
C
D
E
12
13
14
15
F
2
I
DECIMAL TO HEXADECHlAL
To convert decimal to hexadecimal using the table:
equi valents.
Select the largest decimal number that is equal to
or less than the number to be converted. Record
Locate the columns in the table corresponding to the
position of each character of the hexadecimal number.
Record the decim~l equivalents of the characters. The
sum of these numbers is the converted number. Hexa-
the hexadecimal equivalent as the most-significant
character of the hexadecimal number.
Subtract the selected number from the number to
be converted.
decimal number F4D is used as an example.
Hex. Char.
F
4
~
3
2
(2)
(3)
-(4)
= F4D
added.
Hexadecimal number F4D is again used as the example.
4
D
Units Dec. Eguiv.
15
4
13
Continue the process until there is no remainder.
Decimal number 3,917 is used as the example.
decimal equivalent of the next most-significant
character to the result and again multiply by 16.
Repeat this process until the last character is
F
Select the decimal number that is equal to or less
the hexadecimal equivalent as the second mostsignificant digit.
Assign the units decimal equivalent to each
hexadecimal character.
Starting with the decimal equivalent of the mostsignificant character, multiply by 16, add the
Hex. Char.
(3)
than the result obtained from step 2 and record
To convert a number without using the table:
(1)
(2)
Decimal EQuiv.
3,840
64
13
3,917
D
(1)
Decimal Number
from Table
3,840
~0D
64
13/
13
.:Q
Conversion without using the table is accomplished by
successively dividing by 16 and collecting the remainders
in reverse order as shown below.
244
16 13917
32
71
15
X16
64
240
77
+4
IT
64
m
Xl6
3,904
+13
3,917
3,917
15
161244
16
= F4D
84
80
4'
16~~
F4D
C-l
APPENDIX D
HEXADECIMAL/DECIMAL FRACTIONS
Hex
Decimal
Decimal
Hex
.00
.0000
Hex
0000
Decimal
Hex
Decimal
0000
.000
2
Hex
0000
0000
4
3
Decimal
5
FRACTIONAL HEXADECIMAL TO DECH1AL
FRACTIONAL DECIMAL TO UEXADECPIAL
When using the table, fractional hexadecimal to decimal
Fractional·decimal to hexadecimal conversion is accomplished
conversion is accomplished in the same manner as for
in the same manner as for integer conversion when using the
integer conversion.
table.
Hexadecimal .F4D is converted as
shown below:
Hex. Char.
~
.F
---:-orss
Decimal Eguiv.
.9375
.04
2
.0156
2500
.OOD
3
.0031
.9562
7382
9882
8125
8125
Decimal .9563 is converted as shown below.
.9563
-.9375
. F4D
-.0156
.0031
-.0031
.0000
0000
2500
7500
7382
0117
"
0000
8125
1875
..
or
•F
.04
.000
:F'4I)
Conversion without using the table is accomplished by multiConversion without using the table is accomplished as
follows:
. F4D
= .956298828125
• F4D
l6
=~
" -- =
F4D
3917
16
4096
plying successively by 16 and collecting the integers from
the products .
.9563
Xl6
.956298828125
.j
p3. ."
I5'3~~~
4:8T2s
X16
D-1
APPENDIX E
TABLE OF POWERS OF SIXTEEN
n
16
1
17
281
4 503
72 057
1 152 921
4
68
099
592
474
599
594
504
n
1
16
268
294
719
511
186
976
627
037
606
4
65
048
777
435
967
476
627
044
710
370
927
846
1
16
256
096
536
576
216
456
296
736
776
416
656
496
936
976
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
E-l
APPENDIX F
CONVERSION TABLES
This appendix contains the following reference tables:
Title
Hexadecimal Arithmetic
Addition Table
Multiplication Table
Powers of 16
Powers of 10
10
16
Hexadecimal-Decimal Integer Conversion
Hexadecimal-Decimal Fraction Conversion
Powers of Two
Mathematical Constants
F-l
HEXADECIMAL ARITHMETIC
ADDITION TABLE
0
1
2
3
4
5
6
7
8
9
A
8
C
D
E
F
1
02
03
04
05
06
07
08
09
OA
OB
DC
OD
OE
OF
10
2
03
04
05
06
07
08
09
OA
OB
DC
OD
OE
OF
10
11
3
04
05
06
07
08
09
OA
OB
DC
OD
OE
OF
10
11
12
4
05
06
07
08
09
OA
OB
DC
OD
OE
OF
10
11
12
13
5
06
07
08
09
OA
OB
DC
OD
OE
OF
10
11
12
13
14
6
07
08
09
OA
OB
DC
OD
OE
OF
10
11
12
13
14
15
7
08
09
OA
OB
DC
OD
OE
OF
10
11
12
13
14
15
16
8
09
OA
OB
DC
OD
OE
OF
10
11
12
13
14
15
16
17
9
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
A
OB
DC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
B
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
C
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
D
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
E
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
MULTIPLICATION TABLE
F-2
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
2
04
06
08
OA
DC
OE
10
12
14
16
18
1A
1C
1E
3
06
09
DC
OF
12
15
18
1B
1E
21
24
27
2A
2D
4
08
DC
14
18
1C
20
24
28
2C
30
34
38
3C
5
OA
OF
10
14
1E
23
28
2D
32
37
3C
41
46
4B
6
OC
12
18
19
1E ;
24
2A
30
36
3C
42
48
4E
54
5A
7
OE
15
1C
23
2A
31
38
3F
46
4D
54
5B
62
69
8
10
18
20
28
30
38
40
48
50
58
60
68
70
78
9
12
1B
24
2D
36
3F
48
51
5A
63
6C
75
7E
87
A
14
1E
28
32
46
50
5A
64
6E
78
82
8C
96
B
16
21
2C
37
3C
42
4D
58
63
6E
79
84
8F
9A
A5
C
18
24
30
3C
48
54
60
6C
78
84
90
9C
A8
B4
D
1A
27
34
41
4E
5B
68
75
82
9C
A9
B6
C3
E
1C
2A
38
46
54
62
70
7E
8C
8F
9A
A8
B6
C4
D2
F
1E
2B
3C
4B
5A
69
78
87
96
A5
B4
C3
D2
E1
TABLE OF POWERS OF SIXTEEN
10
16- n
n
o
16
0.10000 00000 00000 00000 x
10
0.62500 00000 00000 00000 x
10-
256
2
0.39062
x
10-
4
096
3
0.24414 06250 00000 00000 x
10-
65
536
4
0.15258 78906 25000 00000 x
10-
048 576
5
0.95367 43164 06250 00000 x
10-
50000 00000 00000
16 777
216
6
0.59604 64477
268 435
456
7
4 294 967
296
68 719
1 099 511
53906
25000
x
10-
0.37252
90298 46191
40625
x
10-
8
0.23283
06436 53869
62891
x
10-
476 736
9
0.14551
91522
83668 51807 x
10-
627 776
10
0.90949
47017 72928 23792
186
044 416
11
0.56843 41886 08080
474 976
710 656
12
0.35527
4 503 599 627
370 496
13
0.22204 46049 25031
927 936
846 976
17 592
281
72
057 594 037
152 921
504 606
x
10-
14870 x
10-
13678 80050 09294
x
10-
30808
x
10-
14
0.13877 78780 78144 56755
x
10-
15
0.86736
x
10-
17379 88403 54721
1
2
3
4
6
7
8
9
10
12
13
14
15
16
18
TABLE OF POWERS OF 1016
n
o
A
1.0000
0000
0000
0000
0.1999
9999
9999
999A
64
2
0.28 F5
C28F
5C28
F 5C3
x
3E8
3
0.4 1 89
374B
C6A7
EF9E
x
16- 1
16- 2
2710
4
0.68DB
8BAC
710C
B296
x
16- 3
86AO
5
0.A7C5
AC47
lB47
8423
x
16- 4
F
4240
6
0.10C6
F7 AO
B5E D
8D37
x
16- 4
98
9680
7
0.lAD7
F29A
BCAF
4858
x
5F5
E 100
8
0.2 AF 3
1 DC4
6118
73BF
x
16- 5
16- 6
3 B9 A
CAOO
9
0.44B 8
2FAO
9B5A
52CC
x
16- 7
2
540B
E400
10
0.6 DF 3
7F67
5EF6
EADF
x
16- 8
17
4876
E800
11
O.AF E B
FFOB
CB24
AAFF
x
16- 9
E8
D4A5
1000
12
0.1 197
9981
2DEA
1119
x
16- 9
918
4E72
AOOO
13
0.1 C25
C268
4976
81C2
x
5AF3
107A
4000
14
0.2 D09
370D
4257
3604
x
3
8D7E
A4C6
8000
15
0.480E
BE7B
9D58
566D
x
23
8652
6FCl
0000
16
0.734A
CA5F
6226
FOAE
x
163
4578
5 D8A
0000
17
O.B 877
AA32
3~A4
B449
x
DEO
86B3
A764
0000
18
0.1272
5DD1
D243
ABA1
x
8AC7
2304
89E8
0000
19
0.1 D83
C94F
B6D2
AC35
x
16- 10
16 -11
16- 12
16- 13
16- 14
16- 14
16- 15
F-3
HEXADECIMAL·DECIMAL INTEGER CONVERSION
The table below provides fordirect conversions between hexadecimal integers in the range O-FFF and decimal integers in
the range 0-4095. For conversion of larger integers, the
table values may be added to the following figures:
Hexadecimal
Decimal
Hexadecimal
Decimal
01000
02 000
03 000
04 000
05 000
06 000
07 000
08000
09 000
OA 000
OB 000
OC 000
OD 000
OE 000
OF 000
10000
11 000
12 000
13 000
14 000
15 000
16 000
17 000
18 000
19 000
lA 000
IB 000
lC 000
olD 000
lE 000
IF 000
4 096
8 192
12 288
16384
20 480
24576
28672
32768
36864
40 960
45 056
49 152
53248
57344
61440
65536
69632
73728
77824
81920
86 016
90 112
94208
98304
102400
106496
110 592
114688
118784
122 880
126 976
20
30
40
50
60
70
80
90
AO
BO
CO
DO
EO
Fa
100
200
300
400
500
600
700
800
900
AOO
BOO
COO
DOO
EOO
FOO
1 000
2 000
131 072
196608
262 144
327680
393 216
458752
524 288
589824
655 360
720 896
786 432
851 968
917 504
983 040
1 048576
2 097 152
3 145728
4 194304
5 242 880
6 291 456
7 340 032
8388608
9437 184
10 485 760
11 534336
12582 912
13631 488
14680 064
15728640
16 777 216
33554432
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
1.
Express the hexadecimal fraction as an integer times
16 -n, where n is the number of significant hexadecimal
places to the right of the hexadecimal point.
O. CA9BF3 16
2.
CA9 BF3 16 x 16-6
Find the decimal equivalent of the hexadecimal integer
CA9 BF3
3.
=
16
= 13 278 195
10
Multiply the decimal equivalent by 16-n
13 278 195
x 596 046 448 x 10- 16
0.791 442 096
10
Decimal fractions may be converted to hexadecimal fractions
by successively multiplying the decimal fraction by 16 ,
10
After each multiplication, the integer portion is removed to
form a hexadecimal fraction by building to the right of the
hexadecimal point. However, since decimal arithmetic is
used in this conversion, the integer portion of each product
must be converted to hexadec ima I numbers.
Example: Convert 0.89510 to its hexadecimal equivalent
0.895
16
jr----- ~ .~!~
g
\2j.ILU
~],g"
I
0.E51 E
16 •
@.720
7
8
9
A
B
C
D
E
F
0006
0022
0038
0054
0007
0023
0039
0055
0008
0024
0040
0056
0009
0025
0041
0057
0010
0026
0042
0058
0011
0027
0043
0059
0012
0028
0044
0060
0013
0029
0045
0061
0014
0030
0046
0062
0015
0031
0047
0063
0069
0085
0101
0117
0070
0086
0102
0118
0071
0087
0103
0119
0072
0088
0104
0120
0073
0089
0105
0121
0074
0090
0106
0122
0075
0091
0107
0123
0076
0092
0108
0124
0077
0093
0109
0125
0078
0094
0110
0126
0079
0095
0111
0127
0132
0148
0164
0180
0133
0149
0165
0181
0134
0150
0166
0182
0135
0151
0167
0183
0136
0152
0168
0184
0137
0153
0169
0185
0138
0154
0170
0186
0139
0155
0171
0187
0140
0156
0172
0188
0141
0157
0173
0189
0142
0158
0174
0190
0143
0159
0175
0191
0196
0212
0228
0244
0197
0213
0229
0245
0198
0214
0230
0246
0199
0215
0231
0247
0200
0216
0232
0248
0201
0217
0233
0249
0202
0218
0234
0250
0203
0219
0235
0251
0204
0220
0236
0252
0205
0221
0237
0253
0206
0222
0238
0254
0207
0223
0239
0255
0
1
2
3
4
5
000
010
020
030
0000
0016
0032
0048
0001
0017
0033
0049
0002
0018
0034
0050
0003
0019
0035
0051
0004
0020
0036
0052
0005
0021
0037
0053
040
050
060
070
0064
0080
0096
0112
0065
0081
0097
0113
0066
0082
0098
0114
0067
0083
0099
0115
0068
0084
0100
0116
080
090
OAO
aBO
0128
0144
0160
0176
0129
0145
0161
0177
0130
0146
0162
0178
0131
0147
0163
0179
OCO
aDO
OEO
OFO
0192
0208
0224
0240
0193
0209
0225
0241
0194
0210
0226
0242
0195
0211
0227
0243
F-4
Hexadecimal fractions may be converted to decimal fractions
as follows:
°6
HEXADECIMAL-DECIMAL INTEGER CONVERSION (cont.)
0
1
2
3
4
5
6
7
8
100
110
120
130
0256
0272
0288
0304
0257
0273
0289
0305
0258
0274
0290
0306
0259
0275
0291
0307
0260
0276
0292
0308
0261
0277
0293
0309
0262
0278
0294
0310
0263
0279
0295
0311
0264
0280
0296
0312
140
150
160
170
0320
0336
0352
0368
0321
0337
0353
0369
0322
0338
0354
0370
0323
0339
0355
0371
0324
0340
0356
0372
0325 0326 0327
0341 0342 0343
0357 0358 0359
0373 0374 0375
180
190
lAO
lBO
0384
0400
0416
0432
0385
0401
0417
0433
0386
0402
0418
0434
0387
0403
0419
0435
0388
0404
0420
0436
0389
0405
0421
0437
0390
0406
0422
0438
1(0
lDO
lEO
lFO
0448
0464
0480
0496
0449
0465
0481
0497
0450
0466
0482
0498
0451
0467
0483
0499
0452
0468
0484
0500
0453
0469
0485
0501
200
210
220
230
0512
0528
0544
0560
0513
0529
0545
0561
0514
0530
0546
0562
0515
0531
0547
0563
0516
0532
0548
0564
240
250
260
270
0576
0592
0608
0624
0577
0593
0609
0625
0578
0594
0610
0626
0579
0595
0611
0627
280
290
2AO
2BO
0640
0656
0672
0688
0641
0657
0673
0689
0642
0658
0674
0690
2(0
2DO
2EO
2FO
0704
0720
0736
0752
0705
0721
0737
0753
300
310
320
330
0768
0784
0800
0816
340
350
360
370
9
A
B
(
D
E
F
0265 0266 0267
0281 0282 0283
0297 0298 0299
0313 0314 0315
0268
0284
0300
0316
0269
0285
0301
0317
0270
0286
0302
0318
0271
0287
0303
0319
0328
0344
0360
0376
0329
0345
0361
0377
0330
0346
0362
0378
0331
0347
0363
0379
0332
0348
0364
0380
0333
0349
0365
0381
0334
0350
0366
0382
0335
0351
0367
0383
0391
0407
0423
0439
0392
0408
0424
0440
0393
0409
0425
0441
0394
0410
0426
0442
0395
0411
0427
0443
0396
0412
0428
0444
0397
0413
0429
0445
0398
0414
0430
0446
0399
0415
0431
0447
0454
0470
0486
0502
0455
0471
0487
0503
0456
0472
0488
0504
0457
0473
0489
0505
0458
0474
0490
0506
0459
0475
0491
0507
0460
0476
0492
0508
0461
0477
0493
0509
0462
0478
0494
0510
0463
0479
0495
0511
0517
0533
0549
0565
0518
0534
0550
0566
0519
0535
0551
0567
0520
0536
0552
0568
0521
0537
0553
0569
0522
0538
0554
0570
0523
0539
0555
0571
0524
0540
0556
0572
0525
0541
0557
0573
0526
0542
0558
0574
0527
0543
0559
0575
0580
0596
0612
0628
0581
0597
0613
0629
0582
0598
0614
0630
0583
0599
0615
0631
0584
0600
0616
0632
0585
0601
0617
0633
0586
0602
0618
0634
0587
0603
0619
0635
0588
0604
0620
0636
0589
0605
0621
0637
0590
0606
0622
0638
0591
0607
0623
0639
0643
0659
0675
0691
0644
0660
0676
0692
0645
0661
0677
0693
0646
0662
0678
0694
0647
0663
0679
0695
0648
0664
0680
0696
0649
0665
0681
0697
0650
0666
0682
0698
0651
0667
0683
0699
0652
0668
0684
0700
0653
0669
0685
0701
0654
0670
0686
0702
0655
0671
0687
0703
0706
0722
0738
0754
0707
. 0723
0739
0755
0708
0724
0740
0756
0709
0725
0741
0757
0710
0726
0742
0758
0711
0727
0743
0759
0712
0728
0744
0760
0713
0729
0745
0761
0714
0730
0746
0762
0715
0731
0747
0763
0716
0732
0748
0764
0717
0733
0749
0765
0718
0734
0750
0766
0719
0735
0751
0767
0769
0785
0801
0817
0770
0786
0802
0818
0771
0787
0803
0819
0772
0788
0804
0820
0773
0789
0805
0821
0774
0790
0806
0822
0775
0791
0807
0823
0776
0792
0808
0824
0777
0793
0809
0825
0778
0794
0810
0826
0779
0795
0811
0827
0780
0796
0812
0828
0781
0797
0813
0829
0782
0798
0814
0830
0783
0799
0815
0831
0832
0848
0864
0880
0833
0849
0865
0881
0834
0850
0866
0882
0835
0851
0867
0883
0836
0852
0868
0884
0837
0853
0869
0885
0838
0854
0870
0886
0839
0855
0871
0887
0840
0856
0872
0888
0841
0857
0873
0889
0842
0858
0874
0890
0843
0859
0875
0891
0844
0860
0876
0892
0845
0861
0877
0893
0846
0862
0878
0894
0847
0863
0879
0895
380
390
3AO
3BO
0896
0912
0928
0944
0897
0913
0929
0945
0898
0914
0930
0946
0899
0915
0931
0947
0900
0916
0932
0948
0901
0917
0933
0949
0902
0918
0934
0950
0903
0919
0935
0951
0904
0920
0936
0952
0905
0921
0937
0953
0906
0922
0938
0954
0907
0923
0939
0955
0908
0924
0940
0956
0909
0925
0941
0957
0910
0926
0942
0958
0911
0927
0943
0959
3(0
3DO
3EO
3FO
0960 0961 0962 0963
0976 0977 0978 0979
0992 0993 0994 0995
1008 1009 1010 1011
0964 0965 0966 0967
0980 0981 0982 0983
0996 0997 0998 0999
1012 1013 1014 1015
0968 0969 0970 0971
0984 0985 0986 0987
1000 1001 1002 1003
1016 1017 1018 1019
0972 0973 0974 0975
0988 0989 0990 0991
1004 1005 1006 1007
1020 1021 1022 1023
F-5
HEXADECIMAL-DECIMAL INTEGER CONVERSION (cont.)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
400
410
420
430
1024
1040
1056
1072
1025 1026 1027
1041 1042 1043
1057 1058 1059
1073 1074 1075
1028 1029 1030
1044 1045 1046
1060 1061 1062
1076 1077 1078
1031
1047
1063
1079
1032
1048
1064
1080
1033 1034
1049 1050
1065 1066
1081 1082
1035
1051
1067
1083
1036 1037
1052 1053
1068 1069
1084 1085
1038 1039
1054 1055
1070 1071
1086 1087
440
450
460
470
1088
1104
1120
1136
1089
1105
1121
1137
1090 1091
1106 1107
1122 1123
1138 1139
1092
1108
1124
1140
1095
1111
1127
1143
1096
1112
1128
1144
1097 1098 1099
1113 1114 1115
1129 1130 1131
1145 1146 1147
1100 1101
1116 1117
1132 1133
1148 1149
1102 1103
1118 1119
1134 1135
1150 1151
480
490
4AO
4BO
1152
1168
1184
1200
1153
1169
1185
1201
1154 1155
1170 1171
1186 1187
1202 1203
1156 1157
1172 1173
1188 1189
1204 1205
1158 1159
1174 1175
1190 1191
1206 1207
1160 1161
1176 1177
1192 1193
1208 1209
1162 1163
1178 1179
1194 1195
1210 1211
1164
1180
1196
1212
1165 1166 1167
1181 1182 1183
1197 1198 1199
1213 1214 1215
4CO
400
4EO
4FO
1216 1217
1232 1233
1248 1249
1264 1265
1218
1234
1250
1266
1220 1221
1236 1237
1252 1253
1268 1269
1222 1223
1238 1239
1254 1255
1270 1271
1224 1225 1226 1227
1240 1241 1242 1243
1256 1257 1258 1259
1272 1273 1274 1275
1228
1244
1260
1276
1229 1230
1245 1246
1261 1262
1277 1278
500
510
520
530
1280 1281
1296 1297
1312 1313
1328 1329
1282 1283
1298 1299
1314 1315
1330 1331
1284
1300
1316
1332
1285 1286
1301 1302
1317 1318
1333 1334
1288 1289 1290
1304 1305 1306
1320 1321 1322
1336 1337 1338
1291
1307
1323
1339
1292
1308
1324
1340
1293 1294 1295
1309 1310 1311
1325 1326 1327
1341 1342 1343
540
550
560
570
1344 1345
1360 1361
1376 1377
1392 1393
1346 1347
1362 1363
1378 1379
1394 1395
1348
1364
1380
1396
1349 1350 1351
1365 1366 1367
1381 1382 1383
1397 1398 1399
1352
1368
1384
1400
1353
1369
1385
1401
1354
1370
1386
1402
1355
1371
1387
1403
1356
1372
1388
1404
1357
1373
1389
1405
580
590
SAO
5BO
1408
1424
1440
1456
1412 1413 1414 1415
1428 1429 1430 1431
1444 1445 1446 1447
1460 1461 1462 1463
1416
1432
1448
1464
1417
1433
1449
1465
1418 1419
1434 1435
1450 1451
1466 1467
1420
1436
1452
1468
1421 1422 1423
1437 1438 1439
1453 1454 1455
1469 1470 1471
1219
1235
1251
1267
1409 1410 1411
1425 1426 1427
1441 1442 1443
1457 1458 1459
1093
1109
1125
1141
1094
1110
1126
1142
1287
1303
1319
1335
1231
1247
1263
1279
1358 1359
1374 1375
1390 1391
1406 1407
5CO
500
'5EO
5FO
1472 1473 1474
1488 1489 1490
1504 1505 1506
1520 1521 1522
1475
1491
1507
1523
1476
1492
1508
1524
1477
1493
1509
1525
1478 1479
1494 1495
1510 1511
1526 1527
1480
1496
1512
1528
1481
1497
1513
1529
1482 1483
1498 1499
1514 1515
1530 1531
1484
1500
1516
1532
1485
1501
1517
1533
1486 1487
1502 1503
1518 1519
1534 1535
600
610
620
630
1536 1537 1538
1552 1553 1554
1568 1569 1570
1584 1585 1586
1539
1555
1571
1587
1540
1556
1572
1588
1541
1557
1573
1589
1542 1543
1558 1559
1574 1575
1590 1591
1544
1560
1576
1592
1545
1561
1577
1593
1546 1547
1562 1563
1578 1579
1594 1595
1548
1564
1580
1596
1549
1565
1581
1597
1550
1566
1582
1598
1551
1567
1583
1599
640
650
660
670
1600
1616
1632
1648
1601
1617
1633
1649
1602 1603
1618 1619
1634 1635
1650 1651
1604 1605 1606
1620 1621 1622
1636 1637 1638
1652 1653 1654
1608 1609
1624 1625
1640 1641
1656 1657
1610 1611
1626 1627
1642 1643
1658 1659
1612
1628
1644
1660
1613
1629
1645
1661
1614
1630
1646
1662
1615
1631
1647
1663
680
690
6AO
6BO
1664
1680
1696
1712
1665
1681
1697
1713
1666
1682
1698
1714
1667
1683
1699
1715
1668 1669 1670 1671
1684 1685 1686 1687
1700 1701 1702 1703
1716 ·1717 1718 1719
1672
1688
1704
1720
1673 1674
1689 1690
1705 1706
1721 1722
1675
1691
1707
1723
1676
1692
1708
1724
/677 1678
1693 1694
1709 1710
1725 1726
1679
1695
1711
1727
6CO
600
6EO
6FO
1728
1744
1760
1776
1729 1730
1745 1746
1761 1762
1777 1778
1731
1747
1763
1779
1732 1733
1748 1749
1764 1765
1780 1781
1736
1752
1768
1784
1737 1738
1753 1754
1769 1770
1785 1786
1739
1755
1771
1787
1740
1756
1772
1788
1741
1757
1773
1789
1742
1758
1774
1790
1743
1759
1775
1791
F-6
1734
1750
1766
1782
1607
1623
1639
1655
1735
1751
1767
1783
HEXADECIMAL-DECIMAL INTEGER CONVERSION (cont.)
0
1
700
710
720
730
1792
1808
1824
1840
740
750
760
770
1856 1857
1872 1873
1888 1889
1904 1905
780
790
7AO
7BO
1920
1936
1952
1968
7CO
700
7EO
7FO
2
1793 1794
1809 1810
1826
18~5
1841 1842
3
1795
1811
1827
1843
1858 1859
1874 1875
1890 1891
1906 1907
1921 1922
1937 1938
1953 1954
1969 1970
4
5
1796 1797
1812 1813
1828 1829
1844 1845
6
7
8
9
1798
1814
1830
1846
1799
1815
1831
1847
1800
1816
1832
1848
1801
1817
1833
1849
A
B
1802 1803
1818 1819
1834 1835
1850 1851
C
1804
1820
1836
1852
D
E
1805 1806
1821 1822
1837 1838
1853 1854
1860 1861 1862 1863
1876 1877 1878 1879
1892 1893 1894 1895
1908 1909 1910 1911
1864 1865 1866 1867
1880 1881 1882 1883
1896 1897 1898 1899
1912 1913 1914 1915
1868 1869
1884 1885
1900 1901
1916 1917
1924
1940
1956
1972
F
1807
1823
1839
1855
1870 1871
1886 1887
1902 1903
1918 1919
1925
1941
1957
1973
1926 1927
1942 1943
1958 1959
1974 1975
1928 1929 1930 1931
1944 1945 1946 1947
1960 1961 1962 1963
1976 1977 1978 1979
1932
1948
1964
1980
1984 1985 1986 1987
2000 2001 2002 2003
2016 2017 2018 2019
2032 2033 2034 2035
1988 1989
2004 2005
2020 2021
2036 2037
1990 1991
2006 2007
2022 2023
2038 2039
1992 1993 1994 1995
2008 2009 2010 2011
2024 2025 2026 2027
2040 2041 2042 2043
1996 1997 1998 1999
2012 2013 2014 2015
2028 2029 2030 2031
2044 2045 2046 2047
800
810
820
830
2048
2064
2080
2096
2049
2065
2081
2097
2050
2066
2082
2098
2051
2067
2083
2099
2052
2068
2084
2100
2053
2069
2085
2101
2054
2070
2086
2102
2055
2071
2087
2103
2056
2072
2088
2104
2057
2073
2089
2105
2058
2074
2090
2106
2059
2075
2091
2107
2060
2076
2092
2108
2061
2077
2093
2109
2062
2078
2094
2110
2063
2079
2095
2111
840
850
860
870
2112
2128
2144
2160
2113
2129
2145
2161
2114
2130
2146
2162
2115
2131
2147
2163
2116
2132
2148
2164
2117
2133
2149
2165
2118
2134
2150
2166
2119
2135
2151
2167
2120
2136
2152
2168
2121
2137
2153
2169
2122
2138
2154
2170
2123
2139
2155
2171
2124
2140
2156
2172
2125
2141
2157
2173
2126
2142
2158
2174
2127
2143
2159
2175
880
890
8AO
8BO
2176
2192
2208
2224
2177
2193
2209
2225
2178
2194
2210
2226
2179
2195
2211
2227
2180
2196
2212
2228
2181
2197
2213
2229
2182
2198
2214
2230
2183
2199
2215
2231
2184
2200
2216
2232
2185
2201
2217
2233
2186
2202
2218
2234
2187
2203
2219
2235
2188
2204
2220
2236
2189
2205
2221
2237
2190
8CO
800
8EO
8FO
2240
2256
2272
2288
2241
2257
2273
2289
2242 2243
2258 2259
2274 2275
2290 2291
2244
2260
2276
2292
2245
2261
2277
2293
2246
2262
2278
2294
2247
2263
2279
2295
2248
2264
2280
2296
2249
2265
2281
2297
2250
2266
2282
2298
2251
2267
2283
2299
2252
2268
2284
2300
2253
2269
2285
2301
2254
2270
2286
2302
2255
2271
2287
2303
900
910
920
930
2304
2320
2336
2352
2305
2321
2337
2353
2306
2322
2338
2354
2307
2323
2339
2355
2308
2324
2340
2356
2309
2325
2341
2357
2310
2326
2342
2358
2311
2327
2343
2359
2312
2328
2344
2360
2313
2329
2345
2361
2314 2315
2330 2331
2346 2347
2362 2363
2316
2332
2348
2364
2317
2333
2349
2365
2318
2334
2350
2366
2319
2335
2351
2367
940
950
960
970
2368
2384
2400
2416
2369
2385
2401
2417
2370
2386
2402
2418
2371
2387
2403
2419
2372
2388
2404
2420
2373
2389
2405
2421
2374
2390
2406
2422
2375
2391
2407
2423
2376
2392
2408
2424
2377
2393
2409
2425
2378
2394
2410
2426
2379
2395
2411
2427
2380
2396
2412
2428
2381
2397
2413
2429
2382
2398
2414
2430
2383
2399
2415
2431
980
990
9AO
9BO
2432
2448
2464
2480
2433
2449
2465
2481
2434
2450
2466
2482
2435
2451
2467
2483
2436
2452
2468
2484
2437
2453
2469
2485
2438
2454
2470
2486
2439
2455
2471
2487
2440
2456
2472
2488
2441
2457
2473
2489
2442
2458
2474
2490
2443
2459
2475
2491
2444
2460
2476
2492
2445
2461
2477
2493
2446
2462
2478
2494
2447
2463
2479
2495
9C0
900
9EO
9FO
2496
2512
2528
2544
2497
2513
2529
2545
2498
2514
2530
2546
2499
2515
2531
2547
2500 2501
2516 2517
2532 2533
2548 2549
2502
2518
2534
2550
2503
2519
2535
2551
2504
2520
2536
2552
2505
2521
2537
2553
2506
2522
2538
2554
2507
2523
2539
2555
2508
2524
2540
2556
2509
2525
2541
2557
2510
2526
2542
2558
2511
2527
2543
2559
1923
1939
1955
1971
1933 1934 1935
1949 1950 1951
1965 1966 1967
1981 1982 1983
2191
2206 2207
2222 2223
2238 2239
F-7
HEXADECIMAL-DECIMAL INTEGER CONVERSION (cont.)
0
1
AOO
AlO
A20
A30
2560
2576
2592
2608
2561
2577
2593
2609
A40
A50
A60
A70
2624
2640
2656
2672
2625
2641
2657
2673
A80
A90
AAO
ABO
2688
2704
2720
2736
ACO
ADO
AEO
AFO
2752 2753
2768 2769
2784 2785
2800 2801
BOO
B10
B20
B30
A
4
5
6
7
8
2562 2563
2578 2579
2594 2595
2610 2611
2564
2580
2596
2612
2565
2581
2597
2613
2566
2582
2598
2614
2567
2583
2599
2615
2568
2584
2600
2616
2626
2642
2658
2674
2627
2643
2659
2675
2628
2644
2660
2676
2629 2630 2631
2645 2646 2647
2661 2662 2663
2677 2678 2679
2632 2633
2648 2649
2664 2665
2680 2681
2689 2690 2691
2705 2706 2707
2721 2722 2723
2737 2738 2739
2692
2708
2724
2740
2693
2709
2725
2741
2694 2695
2710 2711
2726 2727
2742 2743
2696
2712
2728
2744
2697 2698
2713 2714
2729 2730
2745 2746
2754 2755
2770 2771
2786 2787
2802 2803
2756
2772
2788
2804
2757 2758 2759
2773 2774 2775
2789 2790 2791
2805 2806 2807
2760
2776
2792
2808
2816 2817
2832 2833
2848 2849
2864 2865
2818 2819
2834 2835
2850 2851
2866 2867
2820
2836
2852
2868
2821
2837
2853
2869
2822 2823
2838 2839
2854 2855
2870 2871
B40
B50
B60
B70
2880
2896
2912
2928
2881
2897
2913
2929
2882
2898
2914
2930
2883
2899
2915
2931
2884
2900
2916
2932
2885
2901
2917
2933
B80
B90
BAO
BBO
2944
2960
2976
2992
2945
2961
2977
2993
2946 2947
2962 2963
2978 2979
2994 2995
BCO
BOO
'BEO
BFO
3008
3024
3040
3056
3009
3025
3041
3057
3010
3026
3042
3058
COO
C10
C20
C30
3072
3088
3104
3120
3073
3089
3105
3121
C40
C50
C60
C70
3136
3152
3168
3184
C80
C90
CAO
CBO
CCO
CDO
CEO
CFO
F-8
2
3
9
B
2569 2570 2571
2585 2586 2587
2601 2602 2603
2617 2618 2619
2634 2635
2650 2651
2666 2667
2682 2683
C
D
E
F
2572
2588
2604
2620
2573
2589
2605
2621
2574
2590
2606
2622
2575
2591
2607
2623
2636 2637
2652 2653
2668 2669
2684 2685
2638 2639
2654 2655
2670 2671
2686 2687
2699
2715
2731
2747
2700
2716
2732
2748
2701
2717
2733
2749
2702
2718
2734
2750
2703
2719
2735
2751
2761
2777
2793
2809
2762 2763
2778 2779
2794 2795
2810 2811
2764
2780
2796
·2812
2765 2766
2781 2782
2797 2798
2813 2814
2767
2783
2799
2815
2824
2840
2856
2872
2825
2841
2857
2873
2826 2827
2842 2843
2858 2859
2874 2875
2828
2844
2860
2876
2829 2830 2831
2845 2846 2847
2861 2862 2863
2877 2878 2879
2886 2887
2902 2903
2918 2919
2934 2935
2888
2904
2920
2936
2889
2905
2921
2937
2890
2906
2922
2938
2892
2908
2924
2940
2893
2909
2925
2941
2948
2964
2980
2996
2949 2950 2951
2965 2966 2967
2981 2982 2983
2997 2998 2999
2952
2968
2984
3000
2953
2969
2985
3001
2954 2955
2970 2971
2986 2987
3002 3003
2956 2957
2972 2973
2988 2989
3004 3005
3011
3027
3043
3059
3012
3028
3044
3060
3013
3029
3045
3061
3015
3031
3047
3063
3016
3032
3048
3064
3017
3033
3049
3065
3018
3034
3050
3066
3019
3035
3051
3067
3020
3036
3052
3068
3021
3037
3053
3069
3022
3038
3054
3070
3023
3039
3055
3071
3074
3090
3106
3122
3075
3091
3107
3123
3076 3077 3078 3079
3092 3093 3094 3095
3108 3109 3110 3111
3124 3125 3126 3127
3080
3096
3112
3128
3081
3097
3113
3129
3082
3098
3114
3130
3083
3099
3115
3131
3084 3085
3100 3101
3116 3117
3132 3133
3086
3102
3118
3134
3087
3103
3119
3135
3137
3153
3169
3185
3138
3154
3170
3186
3139
3155
3171
3187
3140
3156
3172
3188
3141
3157
3173
3189
3142
3158
3174
3190
3143
3159
3175
3191
3144
3160
3176
3192
3145
3161
3177
3193
3146
3162
3178
3194
3147
3163
3179
3195
3148
3164
3180
3196
3149 3150 3151
3165 3166 3167
3181 3182 3183
3197 3198 3199
3200
3216
3232
3248
3201
3217
3233
3249
3202
3218
3234
3250
3203·
3219
3235
3251
3204
3220
3236
3252
3205 3206
3221 3222
3237 3238
3253 3254
3207
3223
3239
3255
3208
3224
3240
3256
3209
3225
3241
3257
3210
3226
3242
3258
3211
3227
3243
3259
3212
3228
3244
3260
3213
3229
3245
3261
3214
3230
3246
3262
3215
3231
3247
3263
3264
3280
3296
3312
3265 3266
3281 3282
3297 3298
3313 3314
3267
3283
3299
3315
3268
3284
3300
3316
3269
3285
3301
3317
3271
3287
3303
3319
3272
3288
3304
3320
3273
3289
3305
3321
3274
3290
3306
3322
3275
3291
3307
3323
3276
3292
3308
3324
3277
3293
3309
3325
3278
3294
3310
3326
3279
3295
3311
3327
3014
3030
3046
3062
3270
3286
3302
3318
2891
2907
2923
2939
2894
2910
2926
2942
2895
2911
2927
2943
2958 2959
2974 2975
2990 2991
3006 3007
HEXADECIMAL-DECIMAL INTEGER CONVERSION (cont.)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DOO
D10
D20
D30
3328
3344
3360
3376
3329
3345
3361
3377
3330
3346
3362
3378
3331
3347
3363
3379
3332
3348
3364
3380
3333
3349
3365
3381
3334
3350
3366
3382
3335
3351
3367
3383
3336
3352
3368
3384
3337
3353
3369
3385
3338
3354
3370
3386
3339
3355
3371
3387
3340
3356
3372
3388
3341
3357
3373
3389
3342
3358
3374
3390
3343
3359
3375
3391
D40
D50
D60
D70
3392
3408
3424
3440
3393
3409
3425
3441
3394
3410
3426
3442
3395
3411
3427
3443
3396
3412
3428
3444
3397
3413
3429
3445
3398
3414
3430
3446
3399
3415
3431
3447
3400
3416
3432
3448
3401
3417
3433
3449
3402
3418
3434
3450
3403
3419
3435
3451
3404
3420
3436
3452
3405
3421
3437
3453
3406
3422
3438
3454
3407
3423
3439
3455
D80
D90
DAO
DBO
3456
3472
3488
3504
3457
3473
3489
3505
3458
3474
3490
3506
3459
3475
3491
3507
3460
3476
3492
3508
3461
3477
3493
3509
3462
3478
3494
3510
3463
3479
3495
3511
3464
3480
3496
3512
3465
3481
3497
3513
3466
3482
3498
3514
3467
3483
3499
3515
3468
3484
3500
3516
3469
3485
3501
3517
3470
3486
3502
3518
3471
3487
3503
3519
DCO
ODD
DEO
DFO
3520
3536
3552
3568
3521
3537
3553
3569
3522
3538
3554
3570
3523
3539
3555
3571
3524
3540
3556
3572
3525
3541
3557
3573
3526
3542
3558
3574
3527
3543
3559
3575
3528
3544
3560
3576
3529
3545
3561
3577
3530
3546
3562
3578
3531
3547
3563
3579
3532
3548
3564
3580
3533
3549
3565
3581
3534
3550
3566
3582
3535
3551
3567
3583
EOO
E10
E20
E30
3584
3600
3616
3632
3585
3601
3617
3633
3586
3602
3618
3634
3587
3603
3619
3635
3588
3604
3620
3636
3589
3605
3621
3637
3590
3606
3622
3638
3591
3607
3623
3639
3592
3608
3624
3640
3593
3609
3625
3641
3594
3610
3626
3642
3595
3611
3627
3643
3596
3612
3628
3644
3597
3613
3629
3645
3598
3614
3630
3646
3599
3615
3631
3647
E40
E50
E60
E70
3648
3664
3680
3696
3649
3665
3681
3697
3650
3666
3682
3698
3651
3667
3683
3699
3652
3668
3684
3700
3653
3669
3685
3701
3654
3670
3686
3702
3655
3671
3687
3703
3656
3672
3688
3704
3657
3673
3689
3705
3658
3674
3690
3706
3659
3675
3691
3707
3660
3676
3692
3708
3661
3677
3693
3709
3662
3678
3694
3710
3663
3679
3695
3711
E80
E90
EAO
EBO
3712
3728
3744
3760
3713
3729
3745
376)
3714
3730
3746
3762
3715
3731
3747
3763
3716
3732
3748
3764
3717
3733
3749
3765
3718
3734
3750
3766
3719
3735
3751
3767
3720
3736
3752
3768
3721
3737
3753
3769
3722
3738
3754
3770
3723
3739
3755
3771
3724
3740
3756
3772
3725
3741
3757
3773
3726
3742
3758
3774
3727
3743
3759
3775
ECO
EDO
EEO
EFO
3776
3792
3808
3824
3777
3793
3809
3825
3778
3794
3810
3826
3779
3795
3811
3827
3780
3796
3812
3828
3781
3797
3813
3829
3782
3798
3814
3830
3783
3799
3815
3831
3784
3800
3816
3832
3785
3801
3817
3833
3786
3802
3818
3834
3787
3803
3819
3835
3788
3804
3820
3836
3789
3805
3821
3837
3790
3806
3822
3838
3791
3807
3823
3839
FOO
FlO
F20
F30
3840
3856
3872
3888
3841
3857
3873
3889
3842
3858
3874
3890
3843
3859
3875
3891
3844
3860
3876
3892
3845
3861
3877
3893
3846
3862
3878
3894
3847
3863
3879
3895
3848
3864
3880
3896
3849
3865
3881
3897
3850
3866
3882
3898
3851
3867
3883
3899
3852
3868
3884
3900
3853
3869
3885
3901
3854
3870
3886
3902
3855
3871
3887
3903
F40
F50
F60
F70
3904
3920
3936
3952
3905
3921
3937
3953
3906
3922
3938
3954
3907
3923
3939
3955
3908
3924
3940
3956
3909
3925
3941
3957
3910
3926
3942
3958
3911
3927
3943
3959
3912
3928
3944
3960
3913
3929
3945
3961
3914
3930
3946
3962
3915
3931
3947
3963
3916
3932
3948
3964
3917
3933
3949
3965
3918
3934
3950
3966
3919
3935
3951
3967
F80
F90
FAO
FBO
3968
3984
4000
4016
3969
3985
4001
4017
3970
3986
4002
4018
3971
3987
4003
4019
3972
3988
4004
4020
3973
3989
4005
4021
3974
3990
4006
4022
3975
3991
4007
4023
3976
3992
4008
4024
3977
3993
4009
4025
3978
3994
4010
4026
3979
3995
4011
4027
3980
3996
4012
4028
3981
3997
4013
4029
3982
3998
4014
4030
3983
3999
4015
4031
FCO
FDO
FEO
FFO
4032
4048
4064
4080
4033
4049
4065
4081
4034
4050
4066
4082
4035
4051
4067
4083
4036
4052
4068
4084
4037
4053
4069
4085
4038
4054
4070
4086
4039
4055
4071
4087
4040
4056
4072
4088
4041
4057
4073
4089
4042
4058
4074
4090
4043
4059
4075
4091
4044
4060
4076
4092
4045
4061
4077
4093
4046
4062
4078
4094
4047
4063
4079
4095
F-9
HEXADECIMAL-DECIMAL FRACTION CONVERSION
Hexadecimal
Decimal
Hexadecimal
.00
.01
.02
.03
.04
.05
.06
.07
.08
.09
.OA
.OB
.OC
.00
.OE
.OF
000000
000000
000000
000000
000000
000000
000000
0000 00
000000
000000
000000
000000
000000
000000
000000
000000
.00000 00000
.00390 62500
.00781 25000
.0117187500
.0156250000
.01953 12500
.02343 75000
.02734 37500
.0312500000
.03515 62500
.03906 25000
.04296 87500
.04687 50000
.05078 12500
.05468 75000
.05859 37500
.40
.41
.42
.43
.44
.45
.46
.47
.48
.49
.4A
.4B
.4C
.40
.4E
.4F
.10
.11
.12
.13
.14
.15
.16
.17
.18
.19
.1A
.1 B
.IC
.10
.1 E
.1 F
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
.06~50 00000
.0664062500
.07031 25000
.07421 87500
.07812 50000
.08203 12500
.08593 75000
.08984 37500
.09375 00000
.09765 62500
.10156 25000
.10546 87500
.10937 50000
.11328 12500
.1171875000
.12109 37500
.20
.21
.22
.23
.24
.25
.26
.27
.28
.29
.2A
.2B
.2C
.20
.2E
.2F
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
00 00 00
000000
000000
.30
.31
.32
.33
.34
.35
.36
.37
.38
.39
.3A
.3B
.3C
.30
.3E
.3F
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
00 0000
000000
00 0000
F-IO
Decimal
Hexadecimal
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
.25000 00000
.25390 62500
.25781 25000
.2617187500
.2656250000
.26953 12500
.27343 75000
.27734 37500
.281 25 00000
.28515 62500'
.28906 25000
.29296 87500
.29687 50000
.30078 12500
.30468 75000
.30859 37500
.80
.81
.82
.83
.84
.85
.86
.87
.88
.89
.8A
.8B
.8C
.80
.8E
.8F
.50
.51
.52
.53
.54
.55
.56
.57
.58
.59
.5A
.5B
.5C
.50
.5E
.5F
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
.3125000000
.31640 62500
.32031 25000
.32421 87500
.3281250000
.33203 12500
.33593 75000
.33984 37500
.34375 00000
.34765 62500
.35156 25000
.35546 87500
.35937 50000
.36328 12500
.3671875000
.3710937500
.12500 00000
.12890 62500
.13281 25000
.13671 87500
· 14062 50000
· 14453 12500
.14843 75000
.15234 37500
· 15625 00000
.16015 62500
.16406 25000
· 16796 87500
.17187 50000
.17578 12500
.1796875000
.1835937500
.60
.61
.62
.63
.64
.65
.66
.67
.68
.69
.6A
.6B
.6C
.60
.6E
.6F
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
.1875000000
.1914062500
.19531 25000
.19921 87500
.2031 2 50000
.20703 12500
.2109375000
.2148437500
.2187500000
.22265 62500
.22656 25000
.23046 87500
.23437 50000
.23828 12500
.24218 75000
.2460937500
.70
.71
.72
.73
.74
.75
.76
.77
.78
.79
.7A
.7B
.7C
.70
.7E
.7F
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
Decimal
Hexadecimal
Decimal
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
.50000 00000
.50390 62500
.50781 25000
.51171 87500
.51562 50000
.51 953 12500
.5234375000
.52734 37500
.53125 00000
.53515 62500
.53906 25000
.54296 87500
.54687 50000
.55078 12500
.55468 75000
.55859 37500
.CO 000000
.Cl 000000
.C2 000000
.C3 000000
.C4 000000
.C5 000000
.C6 000000
.C7 000000
.C8 000000
.C9 000000
.CA 00 00 00
.CB 000000
.CC 000000
.CD 00 00 00
.CE 000000
.CF 000000
.75000 00000
.75390 62500
.75781 25000
.76171 87500
.76562 50000
.76953 12500
.77343 75000
.77734 37500
.781 25 00000
.78515 62500
.78906 25000
.79296 87500
.79687 50000
.80078 12500
.8046875000
.80859 37500
.90
.91
.92
.93
.94
.95
.96
.97
.98
.99
.9A
.9B
.9C
.90
.9E
.9F
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
.5625000000
.56640 62500
.57031 25000
.57421 87500
.57812 50000
.58203 12500
.58593 75000
.58984 37500
.59375 00000
.59765 62500
.60156 25000
.60546 87500
.60937 50000
.61328 12500
.6171875000
.62109 37500
.00 000000
.01 000000
.02 000000
.03 000000
.04 000000
.05 000000
.06 000000
.07 000000
.08 000000
.09 000000
.DA 00 00 00
.DB 000000
.DC 000000
.00000000
.DE 000000
.DF 000000
.81250 00000
.8164062500
.82031 25000
.82421 87500
.8281250000
.83203 12500
.83593 75000
.83984 37500
.84375 00000
.84765 62500
.85156 25000
.85546 87500
.85937 50000
.86328 12500
.8671875000
.8710937500
.37500 00000
.37890 62500
.38281 25000
.38671 87500
.39062 50000
.39453 12500
.39843 75000
.40234 37500
.40625 00000
.4101562500
.4 1406 25000
.4179687500
.42187 50000
.42578 12500
.42968 75000
.43359 37500
.AO
.Al
.A2
.A3
.A4
.A5
.A6
.A7
.A8
.A9
.AA
.AB
.AC
.AD
.AE
.AF
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
00 00 00
000000
000000
00 00 00
000000
000000
.6250000000
.62890 62500
.63281 25000
.63671 87500
.64062 50000
.64453 12500
.64843 75000
.65234 37500
.65625 00000
.66015 62500
.66406 25000
.66796 87500
.67187 50000
.67578 12500
.67968 75000
.68359 37500
.EO
.El
.E2
.E3
.E4
.E5
.E6
.E7
.E8
.E9
.EA
.EB
.EC
.ED
.EE
.EF
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
.87500 00000
.87890 62500
.88281 25000
.88671 87500
.89062 50000
.89453 12500
.8984375000
.90234 37500
.90625 00000
.9101562500
.91406 25000
.9179687500
.92187 50000
.92578 12500
.92968 75000
.93359 37500
.43750 00000
.44140 62500
.44531 25000
.44921 87500
.4531250000
.45703 12500
.46093 75000
.46484 37500
.46875 00000
.47265 62500
.47656 25000
.48046 87500
.48437 50000
.48828 12500
.4921875000
.49609 37500
.BO
.Bl
.B2
.B3
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
.68750 00000
.69140 62500
.69531 25000
.69921 87500
.7031 2 50000
.70703 12500
.7109375000
.7148437500
.71875 00000
.72265 62500
.72656 25000
.73046 87500
.73437 50000
.73828 12500
.7421875000
.74609 37500
.FO
.F 1
.F2
.F3
.F4
.F5
.F6
.F7
.F8
.F9
.FA
.FB
.FC
.FD
.FE
.FF
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
.93750 00000
.94140 62500
.94531 25000
.94921 87500
.9531250000
.95703 12500
.96093 75000
.96484 37500
.96875 00000
.97265 62500
.97656 25000
.98046 87500
.98437 50000
.98828 12500
.99218 75000
.99609 37500
.B4
.B5
.B6
.B7
.B8
.B9
.BA
.BB
.BC
.BD
.BE
.BF
HEXADECIMAL-DECIMAL FRACTION CONVERSION (cont.)
Hexadecimal
Decimal
Hexadecimal
Decimal
Hexadecimal
Decimal
Hexadecimal
Decimal
.0000
.0001
.0002
.0003
.0004
.0005
.0006
.0007
.00 08
.0009
.OOOA
.OOOB
.OOOC
.OOOD
.OOOE
.00 OF
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
.00000 00000
.00001 52587
.00003 05175
.00004 57763
.00006 10351
.00007 62939
.00009 15527
.0001068115
.00012 20703
.0001373291
.00015 25878
.00016 78466
.00018 31054
.0001983642
.00021 36230
.00022 88818
.0040
.0041
.0042
.0043
.0044
.0045
.0046
.0047
.0048
.0049
.004A
.004B
.004C
.004D
.004E
.004F
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
.00097 65625
.00099 18212
.00100 70800
.00102 23388
.00103 75976
.001 05 28564
.0010681152
.001 08 33740
.00109 86328
.00111 38916
.00112 91503
.0011444091
.00115 96679
.0011749267
.0011901855
.00120 54443
.0080
.0081
.0082
.0083
.0084
.0085
.0086
.0087
.0088
.0089
.008A
.008B
.008C
.008D
.008E
.008F
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
.00195 31250
.00196 83837
.00198 36425
.00199 89013
.0020141601
.00202 94189
.00204 46777
.00205 99365
.00207 51953
.00209 04541
.00210 57128
.00212 09716
.00213 62304
.00215 14892
.0021667480
.00218 20068
.00 CO 0000
.00C10000
.00 C2 0000
.00C3 0000
.00 C4 0000
.00 C5 0000
.00 C6 0000
.00 C7 0000
.00 C8 0000
.00 C9 0000
.00 CA 00 00
.00 CB 0000
.00 CC 0000
.00 CD 00 00
.00 CE 0000
.00 CF 0000
.00292 96875
.00294 49462
.00296 02050
.00297 54638
.00299 07226
.0030059814
.00302 12402
.00303 64990
.00305 17578
.00306 70166
.00308 22753
.00309 75341
.00311 27929
.0031280517
.00314 33105
.00315 85693
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
10
11
12
13
14
15
16
17
18
19
1A
1B
lC
1D
1E
1F
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
.0002441406
.00025 93994
.00027 46582
.00028 99169
.00030 51757
.00032 04345
.00033 56933
.00035 09521
.00036 62109
.00038 14697
.0003967285
.00041 19873
.00042 72460
.00044 25048
.00045 77636
.00047 30224
.0050
.0051
.0052
.0053
.0054
.0055
.0056
.0057
.0058
.0059
.005A
.005B
.005C
.005D
.005E
.005f
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
.0012207031
.00123 59619
.00125 12207
.00126 64794
.00128 17382
.0012969970
.00131 22558
.00132 75146
.00134 27734
.00135 80322
.00137 32910
.00138 85498
.0014038085
.00141 90673
.00143 43261
.00144 95849
.0090
.0091
.0092
.0093
.0094
.00 95
.0096
.00 97
.00 98
.00 99
.009A
.009B
.009C
.00 9D
.009E
.009F
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
.0021972656
.00221 25244
.00222 77832
.00224 30419
.00225 83007
.00227 35595
.0022888183
.0023040771
.00231 93359
.00233 45947
.00234 98535
.00236 51123
.00238 03710
.0023956298
.00241 08886
.00242 61474
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
DO 0000
D1 0000
D2 0000
D3 0000
D4 0000
D5 0000
D6 0000
D7 0000
D8 0000
D9 0000
DA 00 00
DB 0000
DC 0000
DD 0000
DE 0000
DF 0000
.00317 38281
.00318 90869
.00320 43457
.00321 96044
.00323 48632
.00325 01220
.00326 53808
.00328 06396
.00329 58984
.00331 11572
.0033264160
.00334 16748
.00335 69335
.00337 21923
.00338 74511
.00340 27099
.00 20
.00 21
.0022
.0023
.0024
.0025
.0026
.0027
.00 28
.00 29
.002A
.002B
.00 2C
.00 2D
.002E
.002F
0000
00 00
00 00
0000
00 00
00 00
00 00
00 00
00 00
0000
00 00
0000
0000
00 00
0000
0000
.0004882812
.00050 35400
.00051 87988
.00053 40576
. 00054 93164
.0005645751
.00057 98339
.0005950927
.00061 03515
.00062 56103
.00064 08691
.00065 61279
.00067 13867
.00068 66455
.00070 19042
.00071 71630
.0060
.00 61
.0062
.0063
.0064
.0065
.0066
.0067
.0068
.0069
.006A
.006B
.006C
.006D
.006E
.006F
00 00
00 00
00 00
0000
0000
00 00
0000
0000
00 00
0000
00 00
00 00
00 00
0000
0000
0000
.00146 48437
.00148 01025
.0014953613
.00151 06201
.0015258789
.00154 11376
.0015563964
.00157 16552
.0015869140
.00160 21728
.00161 74316
.00163 269()4
.00164 79492
.00166 32080
.00167 84667
.0016937255
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
0000
0000
00 00
0000
0000
00 00
0000
0000
00 00
0000
00 00
0000
0000
0000
0000
0000
.00244 14062
.00245 66650
.00247 19238
.00248 71826
.00250 24414
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.00253 29589
.0025482177
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.00257 87353
.00259 39941
.00260 92529
.00262 45117
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.00265 50292
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.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
0000
0000
0000
0000
0000
0000
00 00
00 00
0000
0000
0000
0000
0000
0000
0000
0000
.00341 79687
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.00355 52978
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.00358 58154
.00360 10742
.00361 63330
.00363 15917
.00364 68505
.0030
.0031
.0032
.0033
.0034
.0035
.00 36
.00 37
.00 38
.0039
.00 3A
.00 3B
.003C
.00 3D
.00 3E
.003F
0000
00 00
00 00
00 00
0000
00 00
00 00
00 00
00 00
00 00
00 00
0000
00 00
0000
0000
0000
.00073 24218
.00074 76806
.00076 29394
.00077 81982
.00079 34570
.00080 871~8
.00082 39746
.00083 92333
.00085 44921
.00086 97509
.0008850097
.00090 02685
.00091 55273
.0009307861
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.0070
.00 71
.0072
.00 73
.0074
.0075
.00 76
.00 77
.0078
.0079
.007A
.007B
.007C
.007D
.007E
.007F
0000
00 00
0000
00 00
0000
0000
00 00
00 00
0000
0000
0000
0000
0000
00 00
0000
0000
.0017089843
.00172 42431
.0017395019
.0017547607
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.0018005371
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~OO 183 10546
.0018463134
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.0018768310
.00189 20898
.00190 73486
.00192 26074
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.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
BO
Bl
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
0000
00 00
00 00
0000
0000
00 00
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
.00268 55468
.00270 08056
.00271 60644
.00273 13232
.00274 65820
.00276 18408
.00277 70996
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.0028076171
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.0028381347
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.00286 86523
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.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
00 00
0000
0000
0000
0000
00 00
0000
0000
00 00
0000
0000
0000
0000
0000
0000
0000
.00366 21093
.0036773681
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.00370 78857
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.00373 84033
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F-ll
HEXADECIMAL-DECIMAL FRACTION CONVERSION (cont.)
Hexadecimal
Decimal
Hexadecimal
Decimal
Hexadecimal
Decimal
Hexadecimal
Decimal
.000000
.000001
.000002
.000003
.000004
.000005
.000006
.000007
.000008
.000009
.OOOOOA
.0000 DB
.0000 DC
.0000 OD
.OOOOOE
.0000 OF
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.0000000000
.0000000596
.0000001192
.00000 01788
.00000 02384
.00000 02980
.0000003576
.00000 04172
.00000 04768
.00000 05364
.00000 05960
.00000 06556
.0000007152
.0000007748
.0000008344
.00000 08940
.000040
.000041
.000042
.000043
.000044
.000045
.000046
.000047
.000048
.000049
.00 00 4A
.00004B
.00004C
.00 0040
.00004E
.00004F
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00000 38146
.00000 38743
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.00000 39935
.0000040531
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.0000041723
.0000042319
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.00000 43511
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.0000044703
.00000 45299
.00000 45895
.0000046491
.00000 47087
.000080
.000081
.000082
.000083
.0000 84
.000085
.000086
.000087
.000088
.000089
.00008A
.00008B
.00 00 8C
.0000 8D
.00008E
.00008F
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00000 76293
.00000 76889
.00000 77486
.00000 78082
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.0000079870
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.0000081062
.0000081658
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.00000 83446
.00000 84042
.00000 84638
.00000 85234
.0000
.0000
.0000
.0000
.0000
.0000
.0000
.0000
.0000
.0000
.0000
.0000
.0000
.0000
.0000
.0000
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001
14440
15036
15633
16229
16825
17421
18017
18613
19209
19805
20401
20997
21593
22189
22785
23381
.00 00 10
.0000 11
.0000 12
.0000 13
.0000 14
.0000 15
.000016
.0000 17
.0000 18
.0000 19
.0000 1A
.00 00 1B
.00 00 1C
.00 00 1 D
.0000 1E
.0000 1F
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
09536
10132
10728
11324
11920
12516
13113
13709
14305
14901
15497
16093
16689
17285
17881
18477
.000050
.00 00 51
.00 00 52
.000053
.00 00 54
.000055
.000056
.000057
.000058
.00 00 59
.00005A
.00 00 5B
.00 00 5C
.00 00 50
.00005E
.00005F
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00000 47683
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.00 00 92
.00 00 93
.00 0094
.00 00 95
.00 00 96
.00 0097
.00 0098
.00 00 99
.00 00 9A
.00 00 9B
.00 00 9C
.00 00 9D
.00009E
.0000 9F
00
00
00
00
00
00
00
00
00
00
00
00
00,
00
00
00
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
85830
86426
87022
87618
88214
8881 0
89406
90003
90599
91195
91791
92387
92983
93579
94175
94771
.0000
.0000
.00 00
.00 00
.00 00
.0000
.0000
.0000
.0000
.0000
.00 00
.00 00
.00 00
.0000
.0000
.00 00
DO
Dl
D?
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00001
;00001
·0000 1
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001
23977
24573
25 169
25765
26361
26957
27553
28149
28746
29342
29938
30534
311 30
31726
32322
32918
.0000 20
.0000 21
.00 00 22
.000023
.00 00 24
.0000 25
.0000 26
'.0000 27
.0000 28
.00 00 29
.00002A
.00 00 2B
.00 00 2C
.00 00 2D
.00 00 2E
.00002F
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00000 19073
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.00000 2086 1
.00000 21457
.00000 22053
.00000 22649
.00000 23245
.00000 23841
.00000 24437
.00000 25033
.00000 25629
.00000 26226
.00000 26822
.00000 27418
.00000'28014
.000060
.000061
.000062
.000063
.000064
.00 00 65
.000066
.000067
.00 00 68
.00 00 69
.0000 6A
.00 00 6B
.00 00 6C
.0000 6D
.00 00 6E
.00 00 6F
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00000 57220
.00000 57816
.00000 58412
.00000 59008
.00000 59604
.0000060200
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.00000 61392
.00000 61 988
.0000062584
.00000 63180
.00000 63776
.00000 64373
.00000 64969
.00000 65565
.00000 66161
.0000
.0000
.0000
.0000
.00 00
.00 00
.0000
.0000
.00 00
.00 00
.'00 00
.0000
.00 00
.00 00
.0000
.00 00
AD
Al
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001
95367
95963
96559
97155
9775 1
98347
98943
99539
001 35
00731
01327
01923
02519
03116
03712
04308
.0000
.00 00
.0000
.00 00
.00 00
.0000
.00 00
.00 00
.00 00
.0000
.0000
.0000
.0000
.00 00
.0000
.0000
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00001 33514
.00001 3411 0
.00001 34706
.00001 35302
.00001 35898
.00001 36494
.00001 37090
· 0000 1 37686
.00001 38282
.00001 38878
.00001 39474
.00001 40070
·0000 1 40666
.00001 41263
.00001 41859
.00001 42455
.0000 30
.00 00 31
.0000 32
.000033
.00 0034
.00 00 35
.0000 36
.00 00 37
.0000 38
.0000 39
.00 00 3A
.00 00 3B
.00 00 3C
.00 00 3D
.00003E
.00003F
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00000 2861 a
.00000 29206
.00000 29802
.00000 30398
.00000 30994
.0000031590
.00000 32186
.00000 32782
.00000 33378
.00000 33974
.00000 34570
.00000 35 166
.00000 35762
.00000 36358
.00000 36954
.00000 37550
.000070
.000071
.00 00 72
.000073
.000074
.00 00 75
.00 00 76
.00 00 77
.00 00 78
.0000 79
.00007A
.00 00 7B
.00007C
.00 00 7D
.00007E
.00007F
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00000 66757
.00000 67353
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.00000 69737
.00000 70333
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.00000 7'2121
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.00000 73313
.00000 73909
.0000074505
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.00000 75697
.0000
.0000
.0000
.0000
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.0000
.00 00
.00 00
.0000
.00 00
.00 00
BO
Bl
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00001 04904
.00001 05500
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.00 00
.00 00
.0000
.0000
.00 00
.00 00
.00 00
.0000
.00 00
.0000
.00 00
.0000
.0000
.0000
.0000
.00,00
Fa
Fl
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00001 43051
.00001 43647
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.0000 1 46031
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.00001 47223
.00001 47819
.00001 48415
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.00001 50203
.00001 50799
.00001 51395
.00001 51991
CO 00
ClO~
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