Type_33_Digital_Symbol_Generator_1964 Type 33 Digital Symbol Generator 1964
Type_33_Digital_Symbol_Generator_1964 Type_33_Digital_Symbol_Generator_1964
User Manual: Type_33_Digital_Symbol_Generator_1964
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DIGIT.A.L SY-Jv.[EOL
GE~EIR.ATO:R
:3:3
COpy NO. 0013
Thismanual contains proprietary information. It is provided to the customers of Di gi ta I Equ ipment Corporation to he Ip them properly use and
maintain DEC equipment. Reveal ing the contents to any person or
organ i za tion for any other purpose is proh ibi ted.
Copyright 1964 by Digital Equipment Corporation
II
PREFACE
This manual is intended for use with the Type 30G and Type 30H
Precision CRT Displays.
These displays are identical in operation
and circuitry and only differ in slight degree with respect to their
use.
The Type 30H contains six emitter followers and BNC connec-
tors which allow on external oscilloscope to be used for monitoring
purposes.
Engineering drawings and schematics may become outdated over a
period of time.
If the particular equipment does not completely
resemble the printed drawing or schematic, please request a correct
print for your particular equipment listing all model and/or serial
numbers.
III
CONTENTS
SECTION 1
DESCRIPTION
, ,
Generai
Physical
I-I
1-1
SECTION 2
INTERFACE SIGNALS
2-1
2-1
Signal Description •••••••••••••• o • • •
Input Signals •••
Output Signals
0
••••••••••••••••••
2-3
SECTION 3
LOGICAL OPERATION
Genera I .••••••••.•..•••...•...•.•.•••.••••..••...
Numerica I Conventions •••••••••••••••••••••••••
Symbol ic Conventions
Basic Operation ......................................... .
Symbol Generating Mode
Starting Location
Coordinate Circuit Operation •••••••••••••••••••••
Intensity Level and Status Control Circuit •••••••••
Sta tu 5 Si 9 na Is. . . . . . . . . . . .
Format Determination ••••••••
Symbol Matrix Generation
0
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
•
•
•
0
•••••
0
••••••
•
•
•
•
•
•
•
3-1
3-1
3-1
3-1
3-5
3-5
3-7
3-10
3-13
3-14
3-19
SECTION 4
MAINTENANCE
Elec trica I Adjustments ••••••••••••••••
De lays •••
Character Size
Subscript Drop
Troubleshooting ••••
IV
4-1
4-1
4-1
4-2
4-2
SECTION 5
DIAGRAMS
Cable Schedule .•••.•.......•.•.•.....•....••..........•..
Wiring Schedule..........................................
5-2
5-12
ILLUSTRATIONS
1-1
1-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
Type 30 Precision CRT Display .••••.••..••.•.•••••....•.•..••
Logic Panel and Power Supply Locations ••.•.••.•.•.••••....
DEC Logic Symbols •••••••••.••••••••.•••.•••••••••.•••••..
Type 33 Digital Symbol Generator Block Diagram ..•••.•••.••.
Symbo I Ma tr ix Forma t •••••..•.•.•••..•.•.••.•.•••...•...•.
X Counter and Y Buffer Logic Block Diagram ••••.•.•••.•.••••.
Intensity Level and Status Control Logic Block Diagram •..••....
Subscript Logic Block Diagram •.••••••••••••••••.•••••.•••••
Character Size Logic Block Diagram ••••••.••••.••.•••...•.••
Increment and Space Control Logic Block Diagram .••••....•...
Timing Control Logic Block Diagram ••..•.•.•.....••••.••...•.
Matrix Sequencer Logic Block Diagram ••.•..••...•••••••..•..
Sequencer Control Logic Block Diagram •..•.•.•.•.••....••.•.
Deflection Modifier Logic Block Diagram •••••.•••••••...••••
18-Bit Shift Register Logic Block Diagram .•••••••.••••••••..•
0
•
VI
1-4
3-3
3-4
3-5
3-9
3-11
3-15
3-17
3-18
3-20
3-23
3-27
3-28
3-29
TAB LES
Table
1-1
1-2
2-1
2-2
2-3
2-4
3-1
3-2
3-3
3-4
3-5
3-6
3-7
5-1
Operating Specifications •••••••.•••.•••..••••••.••••••.••..
Physical Specifications ••••.•...••••••..•••.•.••••..•...•...
Interface Signals from PDP-1 •.•...•...•••••.••.••.••......••
Interface Signals from PDP-4 •••.••.•....••..................
Interface Signals to PDP-1 .••.........••...•......••.•...•..
Interface Signals to PDP-4 .•.....•..••.••....••...••••••.•.•
Starting Coordinate Loading Program for PDP-1 ..•••.••.••••..
Starting Coordinate Loading Program for PDP-4 ••..••.•.•...•..
Intensity Loading Program for PDP-4 ...••.•••.•.•••••....•...•
Intensity Correlations .•.•.•...•...........•••.•....•••.•..•
Format Loading Program for PDP-1 .••••..•....••.•.•••..•....
Format Loading Program for PDP-4 .......••.....••....•......
Symbol Generating Cycle Steps •....•••.•....•••••.•.••.•..•.
List of Diagrams ....••..•....•.••••...•.•••••..•••.••.••...
0
v
1-2
1-5
2-1
2-2
2-3
2-4
3-6
3-7
3-12
3-13
3-16
3-16
3-26
5-1
Figure 1-1
Type 30 Precision CRT Display
vi
SECTION 1
o ESC RI PTI 0 N
GENERAL
The Type 33 Digital Symbol Generator is an ancillary item designed and manufactured by
Digital Equipment Corporation for use with their PDP-l and PDP-4 computers.
It is used in
conjunction with either a Type 30G or a Type 30H Precision CRT Display to present alphanumeric symbols on the CRT with a minimum of computer time and programm ing.
The operation
of the display is unaffected in its normal point plotting mode.
The Type 33 controls the operation of the display in the symbol generating mode.
It enables
the display to show any symbol that can be made with a 5 by 7 dot matrix, at any selected
location on the raster.
Once a location has been selected, symbols are automatically posi-
tioned on a horizontal Iine, and each succeeding symbol is automatically moved one position
to the right. Any symbol can be dropped to a subscript position at any location with no extra
commands. A separate format command is used to select one of four matrix sizes and to space
one position to the right.
The display itself uses two 10-bit binary words and a display command to show a single dot at
some location within a 1024 by 1024 dot square raster. Successive dots may be displayed at
any random position at a 20 kilocycle rate.
Eight different levels of intensity can be selected
by the computer in both the point plotting and symbol generating modes.
The Type 30G may be used with either the PDP-lor PDP-4 computers, while the 30H may be
used only with the PDP-l. Aside from a few minor circuit changes to accomodate the different interface, the Type 30H has the ability to duplicate its presentation on an auxiliary highspeed oscilloscope such as the Tektronix RM 503.
Both displays can use a Light Pen, either
Type 32 or Type 370, to identify specific displays, and operate with either centered or offset
rasters.
Table 1-1 lists the operating characteristics of the Type 33 with either display.
PHYSICAL
The Type 33 Symbol Generator is an integral part of either a Type 30G or Type 30H Precision
CRT Display. It occupies slightlymorethanonerackof logic circuits in the display and normally
is not visible.
1-1
TABLE 1-1
OPERATING SPECIFICATIONS
Input Power
115 ± 10 volts, 60 cycles, single phase, at 8 amps.
Power Control
Input power manually turned on and off by a toggle switch or a circuit breaker, and remotely by a -15 volt 5 milliampere signal.
Ambient Temperature
50 F (10 C) to 11 0 F (43
Cathode Ray Tube
16ADP7A .
Focus
Magneti c •
Spot Size
Approximately 0.030 inch, 0.015 inch at the half-light output
points.
Deflection
Magnetic. The electron beam is deflected by the earth IS magnetic
field, therefore the CRT housing should not be moved while spot
positions are being made.
Deflection Sensitivity
0.009 inch change for change of least-significant bit in address,
using 9-3/8 inch raster.
Stability of (0,0) Point
± 0.5% of raster size.
Stability of Deflection
System
± 0.5% of raster size.
Overall Accuracy
± 3 % of raster size overall, ± 1 % of raster size not including dis-
0
0
0
0
C).
tortion due to geometry of the tube and deflecting system.
Repeatability
± 0.05 inch regardless of the location of the preceding point.
Addressing Scheme
lis complement, with 2 1s complement possible. Horizonta I zero
may be at the center or on the left edge. Vertical zero may be at
the center or on the bottom edge.
Raster Size
9 3/8 inches per side, with 1024 points per side.
Pincushion Distortion
Less than 3/16 inch per side.
Symbol Matrix
7 dots high by 5 dots wide.
Matrix Sizes
Dots may be spaced 2, 3, 4, or 5 points apart.
either:
(1) 0.13 by 0.09 inch
(2) 0.19 by 0.14 inch
(3) 0.26 by 0.18 inch
(4) 0.32 by 0.23 inch
Subscript Drop
Adjustable from 0
Intensity Levels
8 distinct levels selected by the octal number of a 3-bit word.
Single Display Time
3 microseconds from application of coordinate address words to display command, 35 microseconds for deflection setup delay, and 3
microseconds for intensification
Overall matrix is
to 100% of matrix size.
1-2
TABLE 1-1 OPERATING SPECIFICATIONS (continued)
Symboi Dispiay Time
IApproximately
96 microseconds from start of first memory cycle
to end of display cycle, plus 3 microseconds for each dot intens ified.
Format Loading Time
10 microseconds for 2 memory cycles.
Indicators
10 X-AXIS and 10 Y-AXIS indicators show the coordinate address
of the spot from either the center or the lower left-hand corner of
the symbol matrix. Three INTENSITY indicators give the octal
number of the intensity level. An LPS indicator glows if the
Iight pen saw a spot. The NAC indi cator Iights when the computer requests a compl etion pu Ise.
Controls
The only operator controls are the main power switch inside the
power suppl y bay and Iight pen ga in control underneath the front
corner of the CRT housing.
The two items consist of a table with a 16-inch cathode ray tube (CRT) in a movable housing
above the table top and two mounting bays underneath the table top. When viewed from the
front, the CRT housing is on the left side of the table above 25 indicator lights visible through
a cutout in the trim panel (see Figure 1-2).
The two mounting bays contain the dc power supplies and most of the electrical circuitry.
Some circuitry is contained in the CRT housing.
For location purposes the left-hand mounting
bay is bay 1, and the right-hand mounting bay is bay 2.
Bay 1 contains an indicator panel in
the front and the majority of the logic circuits in the rear.
Bay 2 contains the power control
panel in the front and the three dc power supplies in the rear.
These are divided into three
horizontal rows; A at the top, B in the center, and Catthe bottom (the logical circuits in the
CRT housing are considered row D).
The lower rows contain 25 vertical sockets, numbered from
left to right. A socket in row A has the same number as the socket directly below it in row
B.
Each socket has 22 terminals designated from top to bottom by the letters of the alphabet
(G, I, 0, and Q are not used).
Therefore, any terminal is specified by the module (socket)
location and socket terminal. As an example, C10H is in bay 1 (understood because all
modules are in bay 1), row C, tenth socket from left (tenth module from right if viewed from
inside the bay), and is the seventh terminal down.
Some of the sockets have component mounting boards over their terminals; these are identified
by the prefix CB- followed by the socket location. A few sockets have insu lated stand-off
1-3
FRONT VIEW
LIGHT PEN GAIN
OPEN
TYPE 811
POWER CONTROL
PANEL
INDICATOR PANEL
OPEN
BAY I
OPEN
BAY 2
115 VOLT AC LINE CABLE ~
')
REAR VIEW
TYPE 770
POWER SUPPLY
DEFLECTION
AMPLIFIER
TYPE 722
POWER SUPPLY
BUFFER AND CONTROL
LOGIC CIRCUITS
EQR
POWER SUPPLY
SYMBOL GENERATOR
LOGIC CIRCUITS
BAY 2
BAY I
INPUT CABLE F=========~
Figure 1-2 Logic Panel and Power Suppiy Locations
terminals above them; these are identified by the prefix ST- followed by the socket location.
Two switches are mounted on brackets for centering or offsetting the zero point.
The switch
on the left is Sl for the horizontal axis, and the switch on the right is S2 for the vertical axis.
Rows A, B, and C are fastened to a sl iding rack.
The rack may be pulled out for access to the
modules and cables. Rows Band C have a panel with three switches on its left-hand edge.
These switches are used for testing the operation of the equipment under marginal power conditions.
Under normal conditions they are down; throwing them up connects that bus to the
marginal power supply (if connected). The upper switch controls the + lOA bus to the A terminals, the center switch controls the + lOB bus to the B terminals, and the lower switch controls the -15 bus to the C terminals. All the D terminals are ground.
TABLE 1-2 PHYSICAL SPECIFICATIONS
Dimensions
50 inches wide, 34 inches deep, 24 inch table height, 49 inches overall
height.
Weight
Approximately 400 pounds.
Mounting
CRT assembly mounted to table, all logical circuits and power suppl ies
mounted under the table. The table legs have adjustable feet for leveling,
and normally support 100 pounds each when properly adjusted.
Clearance
CRT Housing
Access room for maintenance reauires 3 feet in front and rear and 2 feet
above.
·
Tilts approximately 50 forward and 20 0 backward, and rotates 60 0 sideways.
Full 360 0 rotation possible by removing stop bolts. A liB-inch thick sheet
of form-fitted plexiglass protects the face of the CRT.
Color
Blue and grey tweed unless otherwise specified.
The deflection output ampl ifiers and precision resistor stacks in row A are mounted on heat
sinks which are cooled by muffin fans.
The center fan also operates an airflow-actuated sail
switch. This switch controls the application of ac power to the dc power suppl ies and must be
closed before the equipment will operate.
The CRT housing rotates and tilts to allow a good optical presentation of the display.
The
housing contains the CRT; the mount for the CRT, deflection yoke, and focus coil; a fourmodule mounting box {row D}; the CRT component mounting plate; and the light pen gain
control potentiometer. The cables for the CRT go through the mounting pipe.
I
WARNING
Lethal voltages are present in this equipment. Never touch the
black ring around the CRT near the front bezel {exposed on early
models}. Turn off all power before removing any modules.
1-5
CAUTION
An airflow-actuated sail switch controls the application of the
115-volt power to the equipment. Loss of cooling air will shut off
the main power. Never operal'e the equipment without cool ing air I
as the deflection amplifier transistors will overheat. Replacement
cost is approximately $600.
1-6
SIGNAL DESCRIPTION
All logic signals between the computer and the display are either Standard DEC Logic Levels
or Standard DEC Pulses. A Standard DEC Logic Level is either a ground (0 to -0&3 volts),
indicated by an open diamond (~) I or -3 volts (-205 to -3.5 volts) I indicated by a sol:cJ
diamond (....). Dual-polarity level logic is used; therefore the particular voltage=logk state
relationships are defined by individual usage. All logic levels that are appl ied to the con=
ditioning level inputs of capacitor-diode gates must be present either 1 or 3 microseconds
before an input triggering signal is appl ied to the gate e The Standard DEC Negative Pulse IS
indicated by a sol id triangle (-.) and goes from ground to -2.5 or -3 volts (-2.3 to =3.5
volt tolerances). The Standard DEC Positive Pulse, indicated by an open triangle (--I>)' goes
either from -3 volts to ground or from ground to +2.5 volts (+2.3 to +3.0 volts)
e
The w!dth of
the standard pulses used in this equipment is either 100,004, or 0.07 microseconds", depend~ng
on the module and appl ication. All interface pulses are 400 nanoseconds wide
0
Ar~y
s!gncl IS non-standard and 15 indicated by an arrowhead pointing in the direcHon of
other
How(~)
0
iNPUT SIGNALS
The required input signals for the Type 33 are the same for either the Type 30G or 30H displays
when used with a PDP-l, but are different when used with a PDP-4. Tables 2= 1 and 2=2 ~ is~
these signals by their mnemonic names and include a functional description
The term ""leve~~~'
0
means that DEC Standard Levels are required. The definition of logical states for these signais
must be obtained from Section 30 The term "Pulse" means a DEC Standard 004=microsecond
Negative Pulse is required
0
Two other inputs require a constant -15 volt level if used
0
Not
Iisted is a variable dc voltage input used with the marginal voltage checks.
TABLE 2-1 INTERFACE SIGNALS FROM PDP= 1
Mnemonic
Name/Description
.~. ~.- I_T==~~J
I
10 bits comprising the horizontal coordinate word,
SRO_ = vertical coordinate word
9
I
SR 15_ 17 = format word
0
Levels
i levels
I
I
I
,
I
i
~_ _ _ _...J-:,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~_~_ _~~~~~_~=~_ .. _.~_~\
2-1
TABLE 2-1 I NTERFACE SIGNALS FROM PDP-1 {continued}
Mnemonic
Name/Description
SR _
O 16
= first
Type
half of character word,
SR
= subscript control signal.
17
SRO_ i 7 = second half of character word ~
DPY
DisPlaY. Enabling and control signal.
Level
INT-1
INT-2
INT-3
3-bit I NTensity level word.
Levels
CDP
Clear Display Pulse. Clears flip-flops.
Pulse
LDP
Load Display Pulse. Loads coordinate and intensity words.
Pulse
RESET
Resets I ight pen status fl ip- flop.
Pulse
LDF
LoaD Format. Loads format word.
Pulse
PLT
PLoT. Starts symbol generation.
Pulse
RTO
Remote Turn On. Power control level.
-15 v
NAC
Need a Completion. Indication signal.
-15 v
TABLE 2-2 INTERFACE SIGNALS FROM PDP-4
Mnemonic
SRO_17
Name/Description
= horizontal coordinate word.
SR8-17 = vertical coordinate word.
SR _ 17 = intensity level word.
15
SR _ 17 = format word.
15
SRS_17
Type
Levels
SR _ = first half of character word,
O 16
SR = subscript control signal.
17
SR _ = second half of character word.
O 17
DPY
DisPlaY. Enabling and control signal.
Level
CXB
Clear X Buffer. CI ears horizonta I counter.
Pulse
LXB
Load X Buffer. Loads horizontal coordinate word.
Pulse
2-2
TABLE 2-2 INTERFACE
, Mnemonic
S~ >~ALS
FPO,' :
~
:-,.!; (c.vntinued)
Name/Description
Type
CYB
Clear Y Buffer. Clears vertical buffer.
Pulse
LYB
Load Y Buffer. Loads vertical coordinate word.
Pulse
CDI
Clear Display Intensityo Clears intensity buffer.
Pulse
LDI
Load Display Intensity.
Pulse
LDF
Load Display Format. Loads format word.
Pulse
PLT
PLoT. Starts symbol generation.
Pulse
RTO
Remote Turn On.
-15 v
RESET
Resets i ight pen status fl ip- flop.
Loads intensity word.
Power control level.
Pulse
OUTPUT SIGNALS
The output signals produced are different for each computer and display combination. These
signals are either DEC Standard Levels or 0.4 microsecond pulses, or are non-standard intensity level and timing signals and analog deflection signals from emitter followers that are used
to control a remote slave display. These signals are listed in Tables 2-3 and 2-4.
TABLE 2-3 INTERFACE SIGNALS TO PDP-1
I
Type 33 with Type 30G Display
Name/Description
Mnemonic
DDP
Display Done Pulse. Occurs at end of point plotting mode
Type
Pulse
and after each half of a symbol generating operation.
LPF
Light Pen Flag. Occurs when the I ight pen sees a dis-
Pulse
played spot.
LPS
Light Pen Status. Goes to -3 volts when the I ight pen sees
a spot unti I reset from the computer.
2-3
Level
TABLE 2-3 INTERFACE SIGNALS TO PDP-l (continued)
Type 33 with Type 30H Display
Name/Description
Mnemonic
Type
DDP
Display Done Pulse.
Pulse
LPF
Light Pen Flag.
Pulse
LPS
Light Pen Status.
Level
INT _
l 3
Intensity buffer word.
Levels
INT-A
Intensify command. Three microsecond negative
Pulse
pulse when the CRT is to be unblanked.
Horizontal deflection analog voltage.
Analog
Vx
Horizontal reference analog vol tage.
Analog
Vv
Vertical deflection analog voltage.
Analog
Vs
Vertical reference analog voltage.
Analog
V
H
TABLE 2-4 INTERFACE SIGNALS TO PDP-4
Mnemonic
Name/Description
Type
DDP
Display Done Pulse.
Pulse
DDL
Display Done Level. Goes to -3 volts when DDP
Level
occurs until next CD P or PL T pu Ise occurs.
LPS
Level
Light Pen Status.
2-4
SECTION
~
LOGICAL OPERATION
GENERAL
The basic operation of the Type 33 Digital Symbol Generator is the same, whether a Type 30G
or a Type 30H Precision CRT Display is used with it, or whether it is controlled by a PDP-lor
a PDP-4. The Type 33 has two modes of operation:
a single, random-position, point plotting
mode; and a symbol generating mode. The point plotting mode of operation is very s im i lar to
the operation of the Type 30E; therefore it is not described in detail in this manual. The minor
differences, however, are completely covered.
Numerical Conventions
In describing the operation of this equipment, three numerical systems are used: the binary
(radix of 2), the octal (radix of 8), and the decimal (radix of 10). When using the decimal
system, arabic numerials are used and the radix omitted, a 10 being understood. Similarly,
the radix 2 is not shown on binary numbers as they consist entirely of zeros and ones and generally cannot be misunderstood.
However, all octal numbers will be designated as such with
a subscript 8 following the number.
Symbolic Conventions
Digital Equipment Corporation uses a drawing system in which the logical function, circuit
location, trouble shooting, and wiring information are contained on a single drawing. Most
general types of logical circuits are specified by a unique combination of shape, input and
output connections, and internal nomenclature. The module type and location information are
contained within the logical circuit symbol, if possible, or else within a dotted line around the
circuit symbol.
Input and output terminal designations appear next to the circuit symbol, and
all external components are shown with their values. The assertive signal condition that produces the desired output is designated by a signal symbol. These symbols may be either logic
1 or logic 0 as dual-polarity level logic is used. The various symbols used in the Type 33 are
depicted in Figure 3-1.
Names of signals that go through the interface are given in capital
letters, while internal signal names are given in lower case letters.
BASIC OPERATION
The basic operation of the Type 33 can most easily be understood by referring to the logical
3-1
block diagram, Figure 3-2. This diagram shows the configuration of the Type 33 and Type 30G
with both the PDP-l and PDP-4 options. The only difference when using the Type 30H is the
addition of some emitter followers that make the analog voltage inputs to the deflection amplifiers and the intensification signal from the timing control available for external use.
Three
intens ity buffer inverters for use with the PDP-l are not shown.
the CRT for 3 microseconds somewhere within a 9-3/8 inch square raster in each display cycle.
The location of the spot is controlled by four currents flowing through a deflection yoke, and
is directly related to the numerical value of two la-bit binary words. The computer loads one
of these binary words into the Y buffer, and the other into the X counter (wh ich acts as a
buffer). The vo Itage of each bit in both of these words is ampl ified and standardized, and
then each word is converted into an equivalent analog voltage by a digital-to-analog converter.
Each analog voltage controls the current through two opposing deflection coils in the deflection yoke, whose resultant magnetic field deflects the electron beam to its preselected point.
The spot is not produced unti I 35 microseconds after the binary words are loaded into the buffers
to el iminate any movement of the spot. The lOT command in the PDP-l that transfers the two
words to the buffers and initiates the display cycle also selects the level of intensity of the displayed spot. With the PDP-4, each loading of the coordinate words and the intens ity word
requires a separate lOT command.
Symbol Generating Mode - Operation in the symbol generating mode is more compl icated.
The computer determines the location of the left end of a horizontal I ine along which symbols
are to be plotted and loads this location into the X counter and Y buffer as in the point plotting mode, but does not initiate the 35-microsecond setup delay or permit a display.
It next
determines the intensity level, whether incrementing for additional symbols is needed, and the
character size format for the line; and loads this information into the intensity and format
buffers. Then it selects the first half of the particular symbol word to be generated and determines if it is to be a subscript, and loads this into a shift register with a command that inititates the symbol matrix plotting sequence. The computer must now select the last half of the
symbol word and wait for the Type 33 to give a completion signal when the first half of the
symbol word has been displayed, then transfer the last half of the symbol word to the shift register with a command that starts the symbol matrix plotting sequence again from the place where
it left off. The Type 33 will again return a completion signal to the computer when it has
finished displaying the character and has incremented the X counter to the beginning location
of the next symbol.
3-2
Miscellaneous signal. Indicates direction only. No voltage levels or
timing considerations impl ied.
I
!NPUT
_ _ _ _-I "'ANn
'. I U
DEC negative-going 3 volt pulse, usually from ground to -2.5 volts.
Pulse widths of 70,400, and 1000 nanoseconds.
OUTPUT
NAND or NOR Logic Gate. Same as an AND or OR Logic
Gate with an inverter which may be gated. Output polarity opposite to input polarities.
OUTPUT
Pulse Ampl ifier. Ampl ifies and standardizes DEC pu Ises .
Output is from a pulse transformer, giving either positive
or negative pulses depending on which side is grounded.
or
INPUT 2
NOR
INPUT 3
DEC positive-going 3 volt pu Ise, usually from -3 volts to ground. Pulse
widths of 70,400, and 1000 nanoseconds.
---[>
•
----<>
••
Negative level, -3 volts. Greater than one microsecond.
INPUT
+or -
PA
Il.
Positive level, ground. Greater than one microsecond.
-
Negative-going level which triggers on its leading edge, or differentiates. Open diamond and arrow for positive-going levels.
OUTPUT
+ or-
CLOCK
Time
r-::L
Negative-going ievei which triggers on its traiiing edge. Open diamond
and solid arrow for positive-going levels. Also applicable to pulses.
Clock. An astable multivibrator that generates a continuous series of DEC pulses. May be of either polarity.
Frequently crystal controlled.
-
LEVEL OUTPUT
Clamped load resistor. Normally goes to -15 volts, with the output
clamped to -3 volts. Gives ground and -3 volts output pulses or levels.
r
PULSE OUTPUT
DELAY
INPUT
Time
+or -
D-
PROPAGATE
OUTPUT{S)
Inverter. A transistor in common-emitter configuration,
with biased input on its base. Emitter must be at ground to
conduct. Ground input cuts it off and -3 volt input saturates it. Delay =20 nanoseconds.
BASE
{?
_IN_P.....;U.....;T_____
OUTPUT
OUTPUT
TRIGGER
INPUT
CONDITION ING
LEVEL INPUT
ONE
INPUT
Pulse Inverter. Similar to standard inverter but with lower
driving power. Used only with Capacitor-Diode Gates.
Capac itor-Diode Gate. Differentiates the input if the
conditioning level has had the proper voltage on it for
approximately 3 microseconds. No delay between input and output pulses.
ONE
OUTPUTS
INPUT 2
AND
INPUT 3
OR
or
OUTPUT
Flip-Flop. A bistable multivibrator with numerous inputs
and two outputs, which may be buffered. Outputs shown
twice, with diamonds indicating voltage levels in each
state. Positive pulses from ground to +2.5 volts are required on inputs to set or clear the fl ip-flop. A complement input changes the state regardless of the previous
state, and may generate a propagate pulse output.
COMPLEMENT
INPUT (S)
--Ie>
_INPU_T
I
OUTPUT
Analog Ampl ifier. Any ampl ifier that operates over a continuous voltage range. May have single or multiple inputs
and/or outputs. Generally requires different voltages.
OUTPUT (S)
INPUT I
Logic Gate. May be either AND or inclusive OR, depending on polarity of inputs and output. Number of inputs unlimited.
Delay. A monostable multivibrator which produces one or
two level outputs while it is timing out, and then may
trigger a Pulse Ampl ifier. Operating time adjustable.
IDENTIFICATION
Other types of circuits, such as Digital-to-Analog Converters, Electronic Switches, Switch Filters, Level Amplifiers, etc. Shown in any shape or orientation.
1---INPUT{Sl--1
Figure 3-1
DEC Logic Symbols
3-3
I
right ______________________________________r~ig~ht
~~
I
HORIZONTAL
DEFLECTION AMPLIFIER
t V~
rup~
___________________________________________________________
u~p;1
VERTICAL
Fdo~w~n________________________________________________________~do~w~nl
~~
left ____________________________________~Ieft
1
I
DEFLECTION AMPLIFIER
VY
Vx
cathode
;COMPENSATrj
NETWORK
grid
grid
-
Ij 5-10
21
r---"---11-.-....I....-----..j
+VH
FOCUS
COIL
DEFLECTION
YOKE
I......_----_
PEr~
~
....
CRT
liGHT
fO~- _ _ _ _~
I
-I
DIGI TAL-TO-ANALO
CONVERTER
lDIGITAL-TO-ANALOG
CONVERTER
10
I
~TS
.
4
XBo
I
tnt I .......
int ~ ..::
LPS
Vr
X-AXIS
int ~ :::
HORIZONTAL
LEVEL
AMPLIFIERS
4J
Vy
Vx
....
INDICATORS
NAC
MODIFIER
<> <) 0
<) <:>
51
0
XBI-XBg
51
2
count
I
...J..~nt_-A-t-t-I________-t-+---,
T'
LEVEL
INVERTERS
SAIL
SWITCH
~
)
DC POWER
FANS SUPPLIES ~
nn
AC POWER
CONTROL
I
0-
,---+-___S;;.1;.p~1
>
~
.---I______
st-=.op~
c:
:J
o
<>
- ~-;!'
.5 .: .!:
TIMING
H
CONTROL
INTENSITY LEVEL
AND STATUS CONTROL
H. ~.
~.
'7~~il~~~
~~~o7iioo'tJ
o
I-
a::
-
~
....... spl
-N_IO
~~~~~~~~~~~
9 BITS
MATRIX
SEQUENCER
inc-X
<> <> <>
-
a::
cs:
shift ..
BIAS
; ~;:
-+-+-_~:::.:;S~:;..:.:~t'-!>l
dpy:"1
...
I~
0
3: g
SEQUENCER
~ CONTROL
-
<> H 0
~
~~o~
.. ~
..~~~
0
I
o
.,
:J
-0
en
(J
0
(.J
FORMAT
I
J~ J~
J
~~It~~
U-10Q. u
CONTROL
<> < <> (>
<> <>
!~~~~J~
o.-Jc~CJ)U)
J
tgp-Y
I<~t-=C-'!.!Xb=-----..
f
... ___ l ___ . .
10 BITS
... _--,--_ ...
ICOUNTER INVERTERS
1
cyb
o
sro
x COUNTER I
CONTROL
m m
X
9 BITS
~-+-r~+--t-r~~r+----~~-t-r~+-~------t-I-+-r+-~--------~
shift
DDP ...
~~a.
xo
(.).-1 (.)
10 BITS _.... •
I
sr 0
~
cpp
I
0
.-I
Y BUFFER
: ~~~----~~----~
;Ixb
t-- -
j
~~~~
ffioa..o
inc-X
X COUNTER
Precision CRT Display is the same with the
addition of emitter followers and BNC connectors for VHf V X' Vyl VVSI INT-A,
and INT -B.
SUBSCR IPT
1"""'z~C""l0_N"l!'T..,RO~L~~
Precision CRT Display. When used with
the PD P- 1, the verti ca I address word is
appl ied to the X counter directly and the
counter inverters and three intensity inverters {not shown} are used. When used
with the PDP-4, both address words are
from the same AC register as the symbol
words.
2 _ The configuration for using the Type 30H
Il
00 0 en
'"
(,,)
u
J '-space!
~
...
-.1 MATRIX
":'1
SIZE
.... I'--_~_......
L . . . - -_ _-'r'""i_ _~
.
~
~
es
o
cs
~g
~ ~ ~ ~~t~
>
~
,... DDP
.......
.::
Krtg~p~_~y-t----~~~---------i
....
NOTES:
1. Configuration shown using the Type 30G
VERTICAL
LEVEL
AMPLIFIERS
- - . ; . -~--
YBO
10 BITS
10 BITS
INTENSITY
~TS
......
<>
7 01 7 1
7 21
I
51
I
Vr
Y-AXIS
MODIFIER
10
I
y BUFFER
IS-BIT
SHIFT REGISTER
CONTROL
start ~
-too .~ _. .~ - - .. - • - -
po. p.. ____ • - - _
;10
I-'-'~'I------ ~
- - - - - - .• - - - - - - - - . 10 BITS
--~_-IO
BITS---'--'-"'---+-+-H---IOBITS-
I
I
>
g
_ NI '"
1
I
I- I-
I
t;j
Cf)
I- UJ
g;~g;a:
a.
>a.
o
I-lL
:...J 0
a. .-I
o
o
IB BITS
m tIl
>- >.-I U
Figure 3-2 Type 33 Digital Symbol
Generator Block Diagram
3-4
SYMBOL
GENER,I\,TI~}G
:l.ODE
The Type 33 automatically generates a 5 by 7 matrix of some predeterm ined size with the
lower left corner at a predetermined starting location.
beam in sequential increments frum
a to 34 as shown
It moves the position of the electron
in Figure 3-3, with 2 microseconds required
for each move. A symbol is generated by intensifying the electron beam for 3 microseconds
when it is located at the desired position. This requires two l8-bit words per symbol from the
computer, with a 1 in each bit for an intensified location and a 0 in each bit for a blanked
location. The extra bit i 17 in the first half of the symbol word, is not displayed but is used as
a control level to select normal or subscript locations for the matrix.
First Hal f of Symbol Word
10 \1 \2\31415161718191 10 1111 12 1131141151161171
1
,
subscript
Second Hal f of Symbol Word
SYMBOL MATRIX
SEQUENCE
SYMBOL MATRIX
BIT LOCATION
Figure 3-3
Symbol Matrix Format
Starting Location
Before a symbol or line of symbols can be displayed, it is necessary to specify the location of
the lower left corner of the first symbol on the line. This is accomplished by having the computer load the X coordinate of the location into the X counter and the Y coordinate of the
location into the Y buffer.
Because two different computers are used, the coordinates are
loaded in two different manners.
PDP-l Coordinate Loading - The PDP-l has two registers available for in-out transfer of digital
information, as well as a register that makes some of the bits of the in-out transfer (lOT) command available as control levels. This makes it possible for both coordinate address words and
all necessary control pulses and levels to be transferred to the Type 33 during the two memory
3-5
cycles of the lOT operation.
However, each of the two registers - the accumulator (AC) and
the input-output (1-0) - must be loaded from memory separately before the lOT command. Each
loadi ng operation takes two memory cyc les; so a total of 30 microseconds is necessary for the
computer to retrieve the coordinate address words and loading command from memory and effect
the ir transfer to the Type 33.
iABLE 3-1
!
I
I
I
The three program steps necessary are I isted in Table 3-1 .
SiARiihiG COORDiNATE
LOADlt~G
PROGRA,V\ FOR PDP-l
Mnemonic
Name
Code Number
(octal)
Time
(,",sec)
lac X
20xxxx
10
C(xxxx)
=> C(AC)
X coordinate word in
xxxx loaded into AC
lio Y
22yyyy
10
C(yyyy)
=> C(I-O)
Y coordinate word in
yyyy loaded into 1-0
sdb
722007
10
C(AC) => C(XC)
C(AC) => C(VB)
no display
Operation
I
I
I
Explanation
All display buffers
cleared, X coordinate
word transferred into X
counter, Y coordinate
word transferred into Y
buffer, deflection setup
delay and intens ification
inhibited, intensity buffer
loaded for norma I i ntens ity
level
Only the first ten bits of the AC register, AC _ ' are used for the X coordinate word. The
O9
AC _ bits are ground for logic
and - 3 volts for logic 1; therefore each of these bits must
l 9
be inverted before application to the X counter. The first ten bits of the 1-0 register, 1-0 - ,
0 9
are used for both the Y coordinate word and as part of the character word. The 1-0 register
a
bits are - 3 vo Its for logic
a
and ground for logic 1. The lOT command produces a c lear display
pu Ise (C DP) at TP 7 and a load display pulse (L DP) at TP 10' and makes bit 7 and bits 9, 10, and
11 of the command available from the memory buffer (MB).
level, permitting a display when it is a logic
a (MB~)
Bit 7 (MB ) is the display (DPY)
7
and inhibiting a display when it is a
logic 1 (MBi). The other three bits control the intensity level, which is normal when their
octal number is O.
Increasing the number to 3
48 drops it to the minimum value.
progressively increases the intensity, while
8
Further increases slowly raise the intensity towards normal
again. These bits form the third digit from the right in the instruction word.
PDP-4 Coordinate Loading - The PDP-4 on Iy has one l8-bit register, the accumulator (AC),
for transfer of information between an external device and the computer, as well as the memory buffer which makes some of the bits of the lOT command available as control levels. Each
3-6
coordinate address word must therefore be loaded into a buffer in the Type 33 individually.
In addition, the intensity buffer is loaded with the same bits as the format buffer; so each of
these requires separate loading operations. This makes three separate pairs of c Iear and load
pu Ises necessary, whereas the PDP-1 only requires one pair.
All 18 bits from the AC register are applied to the inputs of the shift register.
The ten less-
significant bits (AC _ ) are used for both the X and Y coordinate address words, while the
8 17
three less-significant bits (AC - ) are used for both the intensity and format words. The
15 17
counter inverters shown in Figure 3-2 are not used, nor are the three inverters of the intensity
buffer (not shown).
The PDP-4 has an 8-microsecond memory cycle, during which it can produce various output
pulses at TP , TP , and TP . Like the PDP-1 it requires two memory cycles to retrieve a word
1
7
5
from memory and load it into the AC register, but only one memory cyc Ie is needed to effect
an lOT command. Since the two coordinate words are loaded seooratelv. a toto I of 48 m icroI
,
,
seconds is requ ired for retri eva I and transfer of the start ing coordi nate. The four program
steps necessary are I isted in Tabl e 3-2.
TABLE 3-2
STARTING COORDINATE LOADING PROGRAM FOR PDP-4
Mnemonic
Name
Code Number
(octal)
Time
(/Jsec)
lac X
20xxxx
16
dxl
700506
8
Operation
C(xxxx)
C(AC)
=> C(AC)
=> C(AC)
Explanation
I
X coordinate word in
xxxx loaded into AC
X counter cleared at
TP 5' X coord inate word
transferred into X counter
at TP
7
Y coordinate word in yyyy
loaded into AC
>
lac Y
20yyyy
16
dyl
700606
8
C(yyyy)
C(AC)
=> C(AC)
=> C(YB)
Y buffer cleared at TP 5'
Y coordinate word transferred into Y buffer at
TP
7
Coordinate Circuit Operation
The log ic block diagrams for the X counter and X counter contro I, and the Y buffer and Y buffer
control used by the Type 30G are shown in Figure 3-4. The Type 30H does not use the counter
inverters and uses a Type 4218 Quadruple Flip-Flop module in the more-significant part of the
Y counter instead of a Type 4213. The Type 4218 allows a jam transfer of the four mores ignificant bits of the vertical address to be effected without clearing the Y buffer, thereby
3-7
shortening the time required for large vertical spot movements.
Four inverters are also needed
to produce the dual logic levels per bit necessary for jam transfer.
The input connections for the X counter and Y buffer differ depending on whether a PDP-lor
a PDP-4 is being used.
These connections are listed in the wiring tables in Section 5. The
PDP-l applies a negative clear display pulse (CDP) at TP
7
to pulse amplifiers in both the X
counter and Y buffer control circuits. The X counter control circuit produces a negative 0.4microsecond clear X (cis) Dulse which vaenerates a Dositive 1.O-microsecond clear X buffer
\
I
I
I
(cxb) pulse and is used by the sequence control circuit to clear the matrix sequencer, timing
control, and shift register circuits. The cxb pulse is applied to the direct clear input of all the
X counter fl ip-flops and to the subs,cript fl ip-flop, setting them to their logic 0 states.
The
l-microsecond pulse width is necessary to allow the carry propagate pulses to die out, insuring
that the counter holds all zeros after the clear pulse.
The Y buffer control circuit produces a positive 0.4-microsecond clear Y buffer (cyb) pulse
which is applied to all the direct clear inputs of the Y buffer flip-flops and is ORed with the
c Ix pulse in the sequencer control circuit.
In the Type 30H the cyb pu Ise is on Iy appl ied to
the six less-significant bit flip-flops as the jam transfer module does not require a separate
c Iea r pu Is e .
When the PDP-4 is used, it generates negCltive clear pu Ises at TP 5 on different lOT commands.
Two clear pulses (CXB and CYB) are applied to the trigger inputs of capacitor-diode gates in
the Type 4606 Pulse Amplifier modules. These gates are three-input OR gates with two direct
pulse inputs and one capacitor-diode gate (permanently enabled by negative potentials on their
conditioning level inputs).
Operation after the particular lOT clear pulse occurs is identical
to the PDP-l operation previously described.
The PDP-l norma IIy produces a load display pu Ise (L DP) at TP 10' 2.2 microseconds after the
CDP pulse.
This pulse is applied to a Type 4606 Pulse Amplifier, producing the load X buffer
(LXB) pulse. The Ixb pulse loads the X coordinate word into the X counter, and triggers the
point plotting mode in the timing control circuit (if specified by the display command, DPY).
The Ixb pulse is also produced by the LXB load pulse from the PDP-4 at TP .
7
The negai"ive Ixb pulse is applied to a pulse inverter in each X counter module, producing
positive trigger gate pulses (tgp-x). These pulses are applied to the trigger inputs of positive
capacitor-diode gates, each of which will differentiate the pulse if a ground potential has
been on its conditioning level input for at least 3 microseconds.
Since the PDP-l has applied
the bits of the address word to the capacitor-diode gates at least 10 microseconds earl ier and
f
the PDP~4 ot least 8 r1icroseconds earlier, this condition is satisfied.
Each positive differentiated pulse is applied to the one input of its associated flip-flop (when
the capacitor-diode gate is eqabled), settif"lg the flip-flop to its ONE stote.
Bit ACr; in t~e
r.~~l-~~---j~---l----L r--j~----1----1---j~~ ~----l-----i~
4<1~n
H J
H J
IS22
I
10
COP
!
~L
KI L
W
x
I
10
Yo
W X
yz
0
'(I
,I
'4213~
IS23 H J
H J
tOil
I
' I 'h.;
vi' z
10.+
0
'(3
I
tgp-V
I
L-f--~-----~-----~-----~J
I
5
I~~'-'--
~
WX
W x
10
10
'(4
I
eYB
~
K L
K L
~
vz
v z
10
Ye
I
1110
I
----'---. --'-----Ye
'4214~
IBI2 V T
V T
I
I
Y?
IR
10
Vs
f4i'2S-- -
l
s---- -
WI
I
I
I
I
IR
I
PI
I
VI
YI
o
Vi
I
5
'{.J
I
I
yl
7
Vi
6
Vi
2
tgp-V
I
L _____ I.._
Lve
II
YS
1815
Iyb
LOP
~.
ZX
Z x
I
yl
Vi
S
e
VERTICAL (Y) BUFFER AND CONTROL CIRCUIT FOR THE 30G
82
~-----!...-----!:!.
[4606 - - - - - "I
[4,28 - - - - - - - - - - - J
IBI5
I
IB07
I
___________
I
I
~L~oP~~~_+I~--f:~--~~~~1---------~-----~-----_4------+_--L----_-4______+_-----~-----~~--~IR~PI
I
:
IL _____ I... _ _ _ _ _ y.JI
82
LVB
L..---"J,oA~-_15V
yl
I
Vi
o
Y I
yl
YI
YI
2
3
4
5
VERTICAL (V) BUFFER AND CONTROL CIRCUIT FOR THE
yl
6
y I
yl
7
8
tgp-y
yl
9
30 H
COP
CXB
LOP
I.b
B2
X,
o
X,
I
XI
2
X,
3
X I
4
X'5
X,
6
X,
XI
7
8
* NOT
LXB
I
X 9
USED WITH THE PDP-4
82
in(!-X
HORIZONTAL (X) COUNTER AND CONTROL
LOGIC BLOCK DIAGRAM
Figure 3-4
X Counter and Y Buffer Logic
Block Diagram
3-9
PDP-1 and all AC bits from the PDP-4 are ground for the logic 1 state; so they are appl ied
directly to the conditioning level inputs of the capacitor-diode gates.
However, bits AC _
l 9
from the PDP-1 are - 3 volts for the logic 1 state; so they are appl ied through inverters to the
capac itor-diode gates.
In this manner every bit of the X coordinate address word wh ich is a
logic 1 enables a gate, causing the associated flip-flop to be set to ONE, while every bit
which is a logic 0 disables a gate, preventing the associated flip-flop from being changed
from the ZERO state it al ready is in.
In order to avo id loading down the counter fl ip-flops, the output which is not connected to
the complement input of the next more-significant flip-flop is used to control a level amplifier.
Since these outputs are ground when the flip-flop holds a ONE and the level amplifier
must receive a -3 volt input, inverters are used to effect the voltage change. The mostsignificant bit flip-flop does not require an inverter, and both of its outputs are applied to a
double-throw switch. This enables the most-significant bit to be used either as a sign bit
(center zero,
X~ = positive
deflection,
X6 = negative deflection) or as part of the address
word (offset zero, located on the left-hand edge).
The Y coordinate address word is loaded into the Y buffer in the same manner as the X coordinate was.
The computer appl ies the bits of the Y coordinate address word directly to the
conditioning level inputs of the capacitor-diode gates in the buffer in one memory cycle, and
generates clear and load pulses during the next memory cycle{s). The PDP-4 uses separate
clear and load pulses, CYB and LYB.
Inverters are only necessary on the four more-significant
inputs of the Type 30H because jam transferring is used.
No inverters are necessary on the out-
puts. The outputs of the most-significant bit flip-flop are switched for offset zero (bottom edge)
or center zero modes of operat ion.
The two less-significant bits of the Y coordinate word are applied to capacitor-diode gates
In
a separate Type 4128 module, which controls half of a Type 4214 Quadruple Flip-Flop module.
The trigger pulse (tgp-y) from the pulse inverter in this module is ORed with the load x pulse
(Ixb) in the sequencer control circuit to initiate the point plotting cycle when enabled by the
display command, DPY.
Intens ity Leve I and Status Contro I C irc u it
The intensity level and status control circuit is shown in Figure 3-5 for the Type 30G. The
Type 30H is very similar, with only minor differences.
This circuit contains the intensity
buffer that selects and holds the intensity level of the displayed spot, and most of the circuits
which supply signals to the computer indicating the status of the display.
3-10
I
I
BI8
start
I
dpy
I
!
cpp
..
M
......
N .....
NAND
~
-
DDL .....
pi
,..---
~---- --- ---,
-
I:~t
J
F
J
II~'
I
P
COONE'
':...-
~
F I
III
:
________ ...J
W·
r4606 - - - - - - - - ,
~H~I____________________________~LP~F~
IB09
I E
I F
I
I
I
IL _________
L
--_JI
I
K
LPS
int9
DDP
int
sos
int ~
i
int ~
int ~
int ~
DPY
CDP
CDl
82
LDP
LDl
82
82
-
'----0. A A ,,,- -
15 V
lNT-1
lNT-2
..J*
:::..:IN.:....:T~-3~________________________________________________________
Figure 3-5
NOT
USED WITH PDP-4
Intensity Level and Status Control Logic Block Diagram
Intensity Buffer - Eight different levels of intensity are possible with the Type 30G or the
Type 30H. These levels correspond with the numerical value of a 3-bit l's complement binary
word suppl ied by the computer. The intensity buffer stores this word and generates appropriate
control signals for the intensity bias circuit until the computer next clears the buffer.
When the PDP-l is used, the 3-bit binary word which specified the intensity level is obtained
from bits 9,10, and 11 of the lOT instruction (MB _ ). These are the INT-l, INT-2, and
9 11
INT-3 signals, respectively. The lOT command which generates these signals also produces a
3-11
clear pulsf' (CDP) 1.1 microsecond later, and a load pulse (LDP) 3.3 microseconds later.
The
negative CDP pulse triggers a Type 4606 Pulse Amplifier, which produces a positive pulse that
is applied to the direct clear inputs of the intensity buffer flip-flops and the light pen status
flip-flop, setting them to their ZERO states.
The negative load pulse (LDP) is also applied to
a Type 4606 Pulse Amplifier, which produces a negative pulse that is applied to a pulse inverter
in the buffer module. The pulse inverter produces a positive trigger gate pulse (tgp-I) that is
appl i ed to four capac itor-diode gates connected to the i inputs of the fi ip-fiops.
The bits of the intensity word, which are -3 volts for logic 1, are inverted and applied to the
conditioning level inputs of the intensity buffer's positive capacitor-diode gates,
When these
capacitor-diode gates are enabled by a ground potential on their conditioning level inputs for
at least 3 microseconds, they differentiate the trigger pulse and set the associated flip-flop to
its ONE state.
In this manner the octal number specified by the three intensity bits is loaded
into the buffer.
Note that the capac itor-diode gate for the I ight pen status (LPS) fl ip-flop is
permanent Iy disabled by a negative potential on its condition ing I evel input.
The 3-bit intensity word from the PDP-4 is composed of AC bits 15, 16, and 17; therefore they
must first be retrieved from memory and loaded into the AC before they can be transferred to
the intensity buffer. The lOT command must also generate separate c lear display intens ity
(CDI) and load display intensity (LDI) pulses at TP and TP , respectively. The CDI and LDI
7
5
pu Ises are appl ied to OR c ircu its in the same Type 4606 modu Ies as the c Iear and load pu Ises
from the PDP-1, so the operation is similar. However, the three inverters are not used because
the AC bits are ground for logic 1 .
TABLE 3-3
INTENSITY LOADING PROGRAM FOR PDP-4
Mnemonic
Name
Code Number
(octal)
Time
(I-lsec)
lac I
20ii ii
16
C(iiii)
=)
dlb
700706
8
C(AC)
=-> C(IB)
Operation
C(AC)
Explanation
Intensity word in iiii
loaded into AC
Intensity buffer cleared at
TP5' intensity word transferred into buffer at TP 7'
The intensity buffer supplies a -3 volt signal for each bit to the indicators and to the computer
-+ int~, -+ int1, and ~ int1 signals,
. b'las circuit,
.
'-o't°-o'
th
e 'intensity
In l'
tnt 1, an d-<>,l
tnt3'
when the bit is a logic 1.
h
.
Is to
supp I ·les tree
signa
These are the
It also
N ote
2
that the two latter signals are the opposite outputs of the INT 2 and 1NT3 flip-flops, while the
former is the same as the INT 1 indicator signal.
3-12
This reversal causes the output intensity level
to be offset from the octal number of the 3-bit intensity word; producing a normal intensity
level that is slightly above the average level when the intensity buffer holds zero. The correlations between the intensity word, flip-flop states and outputs, and relative intensity levels
are shown in Table 3-4.
TABLE 3-4
Octal
Number
Relative
Intensity
4
0
5
6
7
0
1
1
2
3
2
3
4
5
6
7
0= dim
7 = bright
INTENSITY CORRELAT IONS
Input Signal
FI ip-Flop States
Output Signals
bit 1
bit 2
bit 3
bit 1
bit 2
bit 3
bit 1
bit 2
bit 3
+
+
+
+
0
0
0
0
0
0
+
+
0
0
+
+
0
+
0
+
0
+
0
+
1
1
1
1
0
0
0
0
0
0
1
0
-
-
0
0
0
0
0= ground
+ = + 2 . 5 vo Its
1
0
1
0
1
0
1
1
0
0
1
1
0= logic 0
1 = logic 1
-
0
0
0
0
-
0
0
-
-
0
-
0
0= ground
- = - 3 volts
Status Signals
Operating Status - The computer must know when any single point has been displayed, when
the first half of the symbol word has been processed, and when the second half of the symbol
word has been processed and the starting location of the next symbo I incremented to the proper
place. All this information is given by the display done pulse (DDP), a negative O.4-microsecond pulse produced by the tim ing control circuit. The DDP pulse is also used to generate a
display done level (DDL) that is used by the PDP-4.
The display done level (DDL) is produced by the done flip-flop in B12. This flip-flop is cleared
to the ZERO state by the c lear plot pulse (cpp) at the first c lear or plot command from the computer, and by the start pulse at the beginning of the second half of the symbol generating process. The cpp pulse is produced by the sequencer control circuit and is appl ied to the direct
c lear input of the done flip-flop.
The start pulse is ANDed with the negative display (DPY)
enabling level by a NAND gate to produce a ground signal that is applied to the 1 output of
the unbuffered done fl ip-flop.
Both the start and dpy signa Is are generated by the tim ing
control circuit.
Light Pen Status - When a light pen is being used to identify a particular display, the computer
must know if and when the light pen sees the particular spot.
3-13
If the light pen is looking at the
location of a spot when it is intensified, a negative saw a spot (sas) level will be produced by
the I ight pen ampl ifier. The sas level wi II last longer than the 3 microsecond intensification
period due to the persistency of the CRTls phosphor screen.
The sas level is ANDed with the DDP pulse to produce both I ight pen flag (LPF) and Iight pen
status (LPS) signals for the computer. The LPF signal is a negative 0.4-microsecond pulse that
is produced by a 4606 pulse amplifier in B09. This pulse amplifier is triggered by two methods.
Normally the DDP pulse will trigger it if the sas level has been present at the conditioning
level input of a capacitor-diode gate for approximately 1 microsecond.
For the cases where
this may not trigger the LPF pulse amplifier, the negative-going transition of the LPS signal
is used.
The LPS signal is obtained from the LPS flip-flop. This flip-flop is initially cleared to the
ZERO state by either the CDP or CDI (clear display intensity) pulse from the computer.
In this
state the LPS signal is grounded through 220 ohms. The sas signal and DDP pulse are applied
to a negative NAND gate, temporarily grounding the output of the gate. This ground signal
is applied to the 0 output of the unbuffered LPS flip-flop, setting it to the ONE state.
In this
state the LPS signal is clamped to -3 volts.
The LPS fl ip-flop can be reset to the ZERO state by a negative RESET pulse which is ANDed
with the negative no display level (DPY). These two signals are applied to a NAND gate
which will temporarily ground the 1 output of the flip-flop, setting it to the ZERO state.
Format Determination
Most of the display format information must be loaded into the appropriate control fl ip-flops
before the first half of the character word con be retrieved from memory. This information
consists of the intensity, character size, normal or subscript location, automatic incrementing
control, and automatic spacing control. The intensity has been described previously.
Subscript Control Circuit - The vertical location of the symbol matrix on a horizontal Iine can
be one of two places as determined by the subscript control circuit. This consists of the subscript (sub) flip-flop in B11 and control circuits shown in Figure 3-6. The sub flip-flop is in
the same module as the two less-significant bit flip-flops of the horizontal counter and is cleared
by the cxb pu Ise. The capac itor-diode gate on its 1 input is permanently disabl ed by a negative voltage to prevent the tgp-x pulse from setting the flip-flop. The flip-flop is set and
cleared instead by applying temporary ground signals on its outputs.
3-14
sub
PLT
DPY
SRI7
oxb
Figure 3-6
Subscript Logic Block Diagram
Bit SR
of the first half of the character word determines the subscript location. This bit is
17
applied directly to the conditioning level input of one capacitor-diode gate in C15 and is complemented by an inverter in C21 before being applied to the conditioning level input of another
capacitor-diode gate in C15. The result is that only one of these capacitor-diode gates will
be enabled at a time.
When the plot (PLT) pulse occurs, it triggers the pulse amplifier in Cll because the DPY signal
had previously enabled a capacitor-diode gate there.
(The PLT pulse must occur at least 1
microsecond after the DPY and SR
levels.) The pulse amplifier produces a negative pulse
17
that is applied to the trigger inputs of both capacitor-diode gates in C15. One of these is
enabled, causing a ground pulse to be produced by its pulse inverter which sets flip-flop sub.
The output of the fl ip-flop is the subscript (sub) signal, a ground level for the subscript position
(SR~ 7) and a
- 3 volt level for the normal position
(SR~ 7).
The symbol matrix is dropped into its subscript position by adding a subscript voltage, V ' in
S
superposition with the compensated vertical deflection voltage, Vv (see Figure 3-2). The Vs
voltage is a function of the reference voltage, V , that determines the size of the symbol
r
matrix.
Both Vr and V S are generated by the matrix size circuit, which is shown in Figure
3-7 a long with part of the format contro I circuit. The symbo I matrix therefore drops by some
percentage of the matrix size as determ ined by the potentiometer on CB-C23.
Character Size - Four different matrix sizes are selected by bits SR
and SR . Since these
17
16
bits are used in both the vertical coordinate word and the two halves of the character word, they
must be loaded into the format control buffer by a separate operation. These programs are
shown in Tables 3-4 and 3-5.
Note that the incrementing control bit, SR
same time.
3-15
15
, is loaded at the
TABLE 3-5
1
I
I
FORMAT LOADING PROGRAM FOR PDP-1
Mnemonic
Name
Code Number
(octa I)
(~ec)
lio F
22ffff
10
C (ffff)
glf
722026
10
C(I-O)
I
TABLE 3-6
Time
Operation
=> C (1-0)
=> C(FB)
Explanation
Format word in
ffff loaded into 1-0
Format word transferred
..
. , c __
r
I nro Tormar Duffer
FORMAT LOADING PROGRAM FOR PDP-4
Mnemonic
Name
Code Number
(octal)
Time
(~ec)
lac F
20ffff
16
C(ffff)
=> C(AC)
Format word in ffff
loaded into AC
glf
701004
8
C(AC)
=> C(FB)
Format word transferred
into format buffer
Operation
Explanation
The format buffer consists of four unbuffered fl ip-flops in C20, each with positive capac itordiode gates on their 0 and 1 inputs. A pulse inverter applies a positive trigger gate pulse
(tgp-F) to each capacitor-diode gate when it receives a negative input pulse, setting the increment (incmt) and character size (C5
and C5 ) flip-flop to whichever state has been selected
1
0
by the enabled capacitor-diode gate. (This method of transferring a word is called "jam transfer. II
It requ ires that one gate rece ive a b it and the other rece ive the comp Iement of the bit.)
The 1 outputs of the C5 flip-flops are applied to the base inputs of two level amplifier inverters
in C24. When these inverters receive a ground input, they are cut off and the ir co II ectors are
clamped at -10 volts. A - 3 volt input saturates the inverters and their collectors go to ground.
Each collector is connected to one input of a dc power ampl ifier in C25 through a weighed
resistor. The other input of the dc power amplifier goes to a voltage divider on CB-C25 and
is normally set for -6.25 volts. The difference of the fixed input and the selectable input,
V., produces the reference voltage, V. The values of these voltages and the relationships
r
I
between 5R
16
and 5R
17
and the matrix sizes are I isted in Figure 3-7.
When a symbol matrix is in the normal position, sub is - 3 volts and V 5 is returned to ground
through the potentiometer on CB-C23. When a symbol matrix is to be dropped to the subscript
position, sub is ground and
Vs
is returned ta the voltage Vr by the clamping diode.
3-·16
SRI6 SR'7
0
0
0
I
CS a
0
0
CS i
0
I
Vi
Vr
SIZE
INCREMENTS
I
2
2
-10 -4
-6.6 -6
3
4
iCB~
r4667 ~-
5
cr-r
rr-------------------------,
Vi
- -- - - - - -
I
- - - - - - - -
IC24
1.5K
-15V
...-..J'v'V'''''-4.........F',/'V'_
Vs
LDF = hood Qisplay f:ormat
DPY = Qiselay' command
SRI7 =§hift~egisfer input bit
- - -T-i
I
1.5K
I
I
I
= subscript voltoge
I
sub = subscript command
SRI6 = §hift ~egister input bit
Vs
!&
IT
P
V r = matrix size
reference voltage
N
sub
1820
17.----------..,
1706
1
I
I
I
C25
:
E
I
zi
:>--=-:--1..........----I~V r
LDF
I
Opy
~-----------I
I CB-C25
i
I
I
I
I
I
I
SR
-IOV REF
Figure 3-7
I
-6.25V
I
I
I
I
I
I
:
4.7K
IK
:
L _ _ _ _ _ _ _ _ _ _J
-=
Character Size Logic Block Diagram
Incrementing and Spacing - When successive symbols are to be displayed on the same horizontal line, the Type 33 automatically moves the starting location of the next symbol matrix to
the right. The next symbol can then be initiated by loading and displaying the first half of
the character word, or the starting location can be moved one more position to the right without a display by a spacing command. This avoids the time required to retrieve words from memory and set up the deflection currents.
The starting position is moved by incrementing the X counter (see Figure 3-4). A number of
increment X counter (inc-X) pulses are applied to a pulse amplifier in B09, which produces
positive pulses that are applied to the complement input of the X
flip-flop. Each inc-X
7
pulse adds four to the number held by the counter, moving the spot four places to the right.
The inc-X pulses are produced by the matrix sequencer circuit after the old symbol has been
displayed and before the DDP pulse occurs. The matrix sequencer circuit also determines the
number of inc-X pulses, based on the character size.
The format control circuit contains both the incrementing (incmt) and spacing (space) flip-flops
of the format buffer and the c ircu its that control these fl ip-flops. This portion of the format
3-17
control circuit is shown in Figure 3-8.
The format loading command produces the disabling
DPY level and a load format pulse (LDF).
These are applied to a capacitor-diode gate in B07
which will trigger a pulse amplifier that produces a negative load pulse for the format buffer.
inc
space~
f42ia- - - -- - - -- - - - - - - - - ---,
f4606 - - - -
- ---'1
1807
I
I C20
I
I
w I
U
X
1
:
L ___
~
___
DPY
W
Y
Z
Y
I
Z
I
I
I
I
I
- I
-=J
T
1P
I
1
T W
X
I
V
82~1~ ____ ~--- ;;~~3-- -T- - - - -- - J
-=-
IC2 I
I
II C 23
I N
I
I
J
H
P
I -=
10K
I
-=
-15 V
I
L _______ -.l ____ -.J
f4i27 --
DDP
Ie 15
LDF
M
I
p -,
I
1
I
I
I
N
I
L
____
.J
dpy
Figure 3-8
Increment and Space Control Logic Block Diagram
Th is load pu Ise is inverted and used to jam transfer SR
space flip-flop.
If SR
into the incmt fl ip-flop and c lear the
15
is a 1, incmt will be set to the ONE state and enable the inc-X cir-
15
cuit of the matrix sequencer with a ground inc signal.
If the next display is not going to be adjacent to the previous symbol, SR
is a O. This sets
15
incmt to the ZERO state and makes inc -3 volts, disabling the inc-X circuit and enabling a
gate which will stop the matrix plotting sequence after the last point is plotted.
In order to space the symbol matrix one character to the right, the incmt flip-flop must be set
to ONE and then a separate space command must be issued.
PDP-1, 701044 for PDP-4).
This is called gsp (720026 for
A counting sequence is then in itiated wh ic h increments the X
counter 4, 5,6, or 7 times, depending on the size specified by the CS flip-flops.
is produced by the last incrementing pu Ise.
3-18
A DDP pulse
NOTE: The space command will transfer the :ontents of the 1-0
register (AC in the PDP-4) to the shi ft registE: and any ones in
the seven more-significant bits will cause the spot to be intensified. The comouter's reaister shou Id be cleared before the soace
command occu~s to avo id extra displays.
I
The space flip-flop is set by the LDF pulse when it triggers a capacitor-diode gate in C15 that
has been enabled by the dpy level. The - 3 volt space level turns on two inverters in the matrix sequencer circuit that enables the inc-X circuit and disables a count gate. The fl ip-flop
is reset to the ZERO state by the DDP pulse, which produces a ground that is appl ied to the 1
output of the unbuffered fl ip-flop.
Symbol Matrix Generation
The symbol matrix is generated by the timing control circuit, sequencer control circuit, matrix
sequencer, and the X- and Y-axis modifier circuits.
It operates from a timing cycle that every
2 or 5 microseconds produces pulses which increment counters that control the X- and Y-axis
modifier circuits in the order described by Figure 3-3. Additional control circuits select the
proper number of incrementing pu Ises when incrementing or spac ing, and produce the DDP pu Ise
at the end of each operation.
Timing Control Circuit - The timing control circuit, Figure 3-9, controls the timing cycle,
produces the start, shift, count, and done (DDP) pulses, and generates the intensify (int-A)
and enable (dpy) levels. The selection of the point plotting or symbol generating modes is also
made in this circuit.
A single point is displayed when the display enable level, DPY, enables the two point plotting
capac itor-diode gates in B15 during the iot command that transfers a coordinate address word
to the display. The load pulse produces a negative set X pulse and/or a positive tgp-Y pulse
that triggers the enabled gate{s) and applies a positive signal to the deflection setup delay in
B24. This initiates a 35-microsecond delay, producing a ground output from terminal U that
is applied to a negative capacitor-diode gate in C15.
(This gate is permanently enabled by a
negative voltage on its conditioning level input.) The trailing edge of this signal triggers the
gate when it goes back to -3 volts, producing a positive pulse from the pulse inverter. This
signal is applied to the direct input of the intensify delay in B25, initiating a 3-microsecond
intensify command (int-A) from terminal J that unblanks the CRT.
NOTE: When using the Type 370 Light Pen, the intens ification
delay can be reduced to 1 .0 microsecond.
3-19
·mt··~.
rijo4 - - - - - iNTENSiFYl
I
1825
J
1
1
I
shift
82
r4303 -DEFLECTiON!
1824
------1
r:-- - - - 14128
POINT PLOTTING
1815
I
SETUP
I
r--~-_<~I-+-_i
I
1
tgp-Y
set
I
I
X I P
I
IL _ _ _ _ _ _
F_ _
dpy
start
DPY
LDF
r,-------..,
sto
/C12
4127
H
I
* NOT USED IN THE 30 H
IE:
cpp
ICOUNT
_ _ _ _ _F
_ _ _ oJ:
1
r4-S06 - - - - D,SpL.Ay-j
ell
iU
DONE
W
I
I
count
1
I
~
1500
DDP
I V
:
I y
X I
I
1
IL ____________
Z
-::- JI
spl
Figure 3-9
Timing Control Logic Block Diagram
At the end of the intensification delay a negative pulse is produced on terminal E that is applied to the direct input of the shift pulse amplifier in C10, producing a negative shift pulse
that is appl ied to the capac itor-diode gate input of the display done pulse ampl ifier in Cll .
This gate is enabled by a -3 volt level from the plot flip-flop when in the point plotting mode;
so the pulse ampl ifier is activated and produces the negative display done pu Ise (DDP). The
plot flip-flop was initially set to the ZERO state by the clear plot pulse (cpp) from the sequencer
contro I circuit.
The DPY level is also applied to an inverter in C21, producing the dpy signal. This is the
complement of the DPY potential, and is used both for greater driving ability and for a - 3
volt enabl ing level.
When a symbol is going to be displayed, the DPY level is -3 volts, disabling the point plotting
gates in B15 and producing a ground dpy signal. The latter signal is appl ied to the conditioning
3-20
level input of a capacitor-diode gate in the start plot pulse amplifier in C10. This disables
the gate and prevents the load format (LDF) pulse from activating the pulse ampl ifier. Therefore, when the format information is loaded into the buffer, the symbol plotting sequence is
not started.
The symbol generating mode is initiated by the plot (PL T) command from the computer, a negin the PDP-l and at TP in the PDP-4. In the 30H the PLT pulse
l
7
is applied directly to the start plot pulse amplifier, while in the 30G it is delayed 2.1 micro-
ative pulse occurring at TP
seconds by the 1304 delay module in C03. This delay is necessary in order to let the levels of
the character word set up the read in capacitor-diode gates.
When the start plot pulse amplifier is activated, it produces a negative start pulse. This pulse
reads the character word into the shift register, sets the plot flip-flop to ONE, and initiates
the timing cycle by triggering a 1.0-microsecond delay.
The timing cycie starts with a i .O-microsecond deiay in C04. At the end of this time a negative pulse is produced that initiates a second 1.0-microsecond delay. This module, in turn,
produces another negative pu Ise that is appl ied to two gates. One of these is a capac itordiode gate in Cl 0 that is enabled by the srO flip-flop when it holds a ZERO. When this is
the case, the gate triggers the shift pulse amplifier, producing a negative shift pulse. This
in turn is applied to the trigger input of the repeat capacitor-diode gate in C15 which is enab led by the plot fl ip-flop (previous Iy set to the ONE state). The repeat gate then produces
a positive pulse that is appl ied to the direct input of the first delay to start the tim ing cycle all
over again. The cycle stops when the plot flip-flop goes to ZERO and disables the repeat gate.
When the srO flip-flop holds a ONE, the capacitor-diode gate in C10 is disabled and an inverter gate in B25 is enabled. The second 1.0-microsecond delay then triggers the 3.0microsecond intensify delay. When the intensification time is over, the shift pulse amp I ifier
is activated and the cyc Ie continues as before.
The shift pulse is applied to the shift register, causing the register to shift the character word
up one bit. Therefore each timing cycle examines the bit in sr ' produces a 3-microsecond
O
display if the bit is a 1, and shifts the word so that the next less-significant bit is moved into
srO for the next cycle to examine.
After the fifteenth bit of the first half of the character word is examined, the matrix sequencer
circuit produces a -3 volt stop plot level (spl). This is applied to the conditioning level input
of the stop plot capacitor-diode gate in C12, enabl ing the gate and causing the sixteenth
shift pulse to set the plot flip-flop to ZERO. This disables the repeat capacitor-diode gate
(after about 1 microsecond) and prevents the seventeenth shift pulse from continuing the
3-21
timing cycle. The plot flip-flop also enables the capacitor-diode gate in the display done
module; so the seventeenth shift pulse produces a DDP pulse.
Each shift pulse also produces a CO'Jnt pulse from the permanently enabled count capacitordiode gate in C12. The count pu Ise is appl ied to a 2-part counter in the matrix sequencer
circuit where it causes the dot position of the symbol matrix to be moved according to the
number held by the counter.
See Figure 3-3 for the dot positions.
After the computer receives the DDP pulse, it transfers the second half of the character word
to the display with a different iot command. This command produces the load format pulse
(LDF) at TP
in the PDP-l and at TP in the PDP-4, as well as the plot (PLT) pulse. Since
7
10
the PL T pulse would clear the matrix sequencer counters, the display enable level (DPY) is
used to prevent this. The DPY level produces an enabling dpy level for the start plot pulse
ampl ifier, allowing the LDP pulse to bypass the PLT pulse in the 30G and start the second half
of the symbol generating process.
Operation in this half is the same as in the first half.
When
the last bit of the character word has been exam ined, the matrix sequence produces increment
pulses to move the symbol matrix to the next starting location and then produces the spl signal
to end the cycle.
Matrix Sequencer Circuit - This circuit keeps count of the number of timing cycles, generates
appropriate control levels to change the deflection according to the count, and produces the
stop, count of six, and stop plotting (spl) levels to properly end the two parts of the symbol
generating mode.
It also produces the correct number of incrementing (inc-X) pulses to move
the starting location of the next symbol matrix to the right, based on the size of the matrix.
Figure 3-10 shows the logic block diagram of the matrix sequencer circuit.
The basic component of the matrix sequencer circuit is a 2-part counter. This counter is divided
into a section that counts to seven (for incrementing the spot up each vertical column of the matrix) and a section that counts to five (for spacing each column to the right).
The seven counter consists of three fl ip-flops in C16. The count pulses from the matrix sequencer
circuit are applied to the complement input of the least significant bit flip-flop, 7 , causing it
2
to change its state each time. Every time a fl ip-flop changes from the ONE to the ZERO state,
the transition of its 1 output from -3 volts to ground acts as a carry signa!, which is applied to
the complement input of the next more-significant bit flip-flop and causes it to change its state.
When the seven counter ho Ids 6
the 70 and 71 fl ip-flops enab Ie a trans istor NAN D gate,
8
producing a - 3 volt count-of-six level. The six signal in turn enables a capacitor-diode gate
I
in the sequencer contro I c ircu it, caus ing the next sh ift pu Ise to produce the shift counter pu lse
(scp), and is also applied to one input of the incrementing size decoder in C19. Tne scp signal
3~22
cs?
p .......
4141
R":
CI9
u.:: a
T":
1/3
~
csg
~~
N': _
_cS~:__________________________________________________________________r ;__-+~~K~~~ ~4
NOR
M:::
F stop""
'"
csJ
z~ a
)(.:: 3/5
v.:.
J'::'t-H ...... 4~6~i-
r
4J1
l
L L¥ i
"
L
Jb'
s
70
L
I
6t
7,
',(
r-LI>&..,r--":'~r-"""a-l:
1<>0' 72
1
'I :
FE:
IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ..1.
I _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .JI
cpp
scp
count
Figure 3-10
Matrix Sequencer Logic Block Diagram
is a positive l-microsecond pulse that is applied to the seven counter as a clear pulse and to
the five counter as a count-of-seven pulse. The seventh count pulse would set the seven counter
to 78
I
but the scp pulse overrides it because of the 1.0 microsecond pulse width and resets
the counter to 0 .
8
3-23
The five counter consists of three flip-flops in C17. This counter is cleared, along with the
plot two completed (P2C) and enable stop (ES) flip-flops by the clear plot pulse (cpp) from the
sequencer contro I c ircu it. The cpp pu Ise occurs every time a coordinate address buffer is loaded at the start of each symbol generating cyc Ie.
Each scp pu Ise adds one to the counter on
every seventh shift pulse until the counterholds4 . The next scp pulse (thirty-fifth shift pulse)
8
resets the counter to 0 and sets the P2C fl ip-flop to the ON Estate, ind icating that the second
8
half of the character word has been processed.
The 52 flip-flop has a single complement input that switches the flip-flop from either state to
the opposite state when a positive pulse is applied as long as the AND gate is enabled by a
ground level. This is supplied from the 1 output of the 52 flip-flop.
However, when the AND
gate has a -3 volt disabling level input, the complement input only switches the flip-flop from
the ONE to the ZERO state. When the counter holds 48 (100), the 52 flip-flop disables the
AND gate and the next scp pulse resets the counter.
After the fifteenth shift and count pulses have occurred, the seven counter holds 28 (010) and
the five counter holds 18 (001). This number is detected by the 15 decoder in C13, a 5-input
positive NAND gate, and its output inverter is cut off. The collector of this inverter shares a
clamped load resistor with the collector of another inverter in C21.
If this latter inverter is
also cut off by a no space level (space), then the output of the two ANDed circuits is the - 3
volt stop plot level (spl). This signal enables the stop plot gate in the timing control circuit
so that the sixteenth shift pulse will set the plot flip-flop to ZERO and halt the timing cycle
(producing a DDP pulse) with the seventeenth shift pulse.
(See Figure 3-9.)
When the computer starts the second half of the symbol generating cycle again, the first shift
pulse that occurs is the eighteenth.
Operation continues until the thirty-fifth shift and count pulse occur and the P2C flip-flop is
set to the ONE state. When this occurs, the 1 output of P2C applies an enabling -3 volt level
to an inverter gate in C23 and the 0 output of P2C appl ies a ground input to a NAN D gate in
C13.
If the increment (incmt) flip-flop has been set to the non-incrementing ZERO state, the
inc signal is - 3 volts. This turns on an enabled inverter in C23 which produces a ground stop
Ieve I. The stop signa I resets the plot fl ip-flop to the ZERO state and stops the symbo I generating cycle when the thirty-sixth shift pube occurs.
When the incmt fl ip-flop is set to the incrementing ONE state, inc is ground. This activates
the NAND gate in C13 which produces an enabling -3 volt level for two capacitor-diode
go 'res , one inC 1? and one in C15.
Eac h of these gates is then tri ggered by the th irty-s ixth
(and a 11 sue ceed ing) sh ift pu Ise and produces ground pu Ise outputs. The capac i tor-diode gate
;,1 C12 produces the inc-X puises that increment the X counter by four to move the starting
3-24
location
0':
the next symbol matrix to the right. The capacitor-diode gate in C15 sets the
enable stop (ES) flip-flop to the ONE state, producing a -3 volt enabling level that turns on
the incrementing size decoder in C19. The ES fiip-fiop is reset to the ZERO state by the DDP
pulse, as well as the cpp pulse.
The incrementing size decoder consists of four negative AND gates whose outputs are applied
to a NOR gate that produces the ground stop level. Each AND gate receives a control level
from the ES flip-flop and some other signal(s) that enables the gate when a predetermined number of inc-X pulses have occurred, based on the symbol matrix size. For example, if the character size buffers are set for size 1 (smallest), both
cs~
and
cs~
are -3 volts. The shift pulse
that sets the ES flip-flop and produces the first incrementing pulse, inc-Xl' also produces a
count pu Ise that adds one to the seven counter. After two more inc -X and count pu Ises occur,
the counter holds 3 , and the 71 and 72 flip-flops both apply - 3 volt levels to the 1/3 AND
8
gate. This enables the gate and produces the stop signal. However; one more inc-X and count
pu Ise wi II be produced as well as the DDP pu Ise.
Both the 2/4 and 3/5 AND gates operate in a similar fashion. The 4/6 AND gate only receives
the count-of-six signal because a smaller matrix size will decode some lesser count before six
occurs.
Table 3-6 I ists the steps and operations in a symbol generating cycle. The symbol word bit is
that bit of each half of the character word that is examined before the shift and count pulse
occurs.
Note that the seven counter continues to count while incrementing after the character
word has been displayed. STOP indicates that the incrementing size decoder is activated and
produces the stop signal: one more inc-X and the DDP signals are produced by the next step.
When the symbol matrix location is to be spaced one character to the right without a display,
a separate space command sets the space fl ip-flop to ONE and starts the symbol generating
cycle with the equivalent of shift pulse thirty-six (see Table 3-6).
NOTE: The seven most-significant bits in the computer's 1-0
(or AC) register must be zeros if no display is to occur.
The space signal is - 3 volts when the space fl ip-flop is in the ONE state, saturating the transistor in C23 which sets the P2C flip-flop to the ONE state and enables the NAN D gate in
C13 (see Figure 3-10). Since the incmt flip-flop had previously been set to the ONE state,
the inc signal is ground and the incrementing part of the cycle proceeds in the normal fashion.
The cycle stops the same way as before, depending on the matrix size.
Sequencer Control Circuit - This circuit, shown in Figure 3-11, controls the symbol generating
cycle. Whenever a coordinate address word is loaded into a buffer, a clx and/or a cyb pulse
3-25
TABLE 3-7
Symbol
VYord
Bit
Shift and
Count Pu Ise
SYMBOL GENERATING CYCLE STEPS
Matrix Counter States
j
50 51 52
NL''11ber
I
70
.\~?_
o
o
1
2
36
37
38
39
0 0
0 0 1
0 0
0 1 0
000011
o 0 0
1 0 0
o 0 0
1 a 1
000110
001
000
o 0 1 0 0 1
001010
o 0 1 0 1 1
o 0 1 1 0 0
o 0 1 1 0 1
o 0 1 1 1 0
o 1 0 0 0 0
010001
010010
o 1 0 0 1 1
010
100
o 1 0 1 0 1
o 1 0 1 1 0
o 1 1 0 0 0
o 1 1 0 0 1
o 1 1 0 1 0
o 1 1 0 1 1
o 1 1 1 0 0
o 1 1 1 0 1
o 1 1 1 1 0
100000
1 0 0
0 0 1
100010
1 0 0
0 1 1
1 0 0
1 0 0
1 0 0
1 0 1
1 0 0
1 1 0
000
000
000
001
o 0 0 0 1 0
o 0 0 0 1 1
000
100
40
000
41
000
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
o
o
i
i
42
~~~_
I
I 0 0 0 I 1 1 1
"......... -~-- •. "",_,"~ ........ _"_ ... j_~_ ................... _________ ---J-_~ _ _ ~ _ _ _ _ _ ...
Other Actions and Operations
PLT starts cycle
six enabled
scp generated
six enabled
scp generated
spl enabled
/O~ PLOT
DDP generated, cycle halts
PLT restarts eye Ie
six enabled
scp generated
six enabled
scp generated
six enabled
scp generated,
P2C
inc Xl'
ENABLE STOP
inc X
2
inc X , STO P: size 1
3
inc X , DDP generated, cycle
4
inc X , STO P: size 2
4
inc X , DDP generated, cycle
5
inc X , STO P: size 3
5
inc X , DDP generated, cyc Ie
6
6
inc
X , STOP: size 4
inC X , DDP generated, cycle
7
L4
4..
ends: size 1
ends: size 2
!
ends: size 3
I
.'__'___
', ___
e~~~_:
si~~_4_
II',
is generated and appl ied to an OR gate in Cll.
Either one of these pulses (or the PL T pu Ise
when accompanied by a -3 volt no-display level, DPY) will activate the associated pulse amp-
!ifier, producing a negative clear shift register (csr) pulse. The csr pulse is applied to three
puise amplifiers, one in the shift register and two in the sequencer control circuit. The latter
two produce the clear plot pulse (cpp) and space count pulse (scp) signals.
Both of these are
applied to the matrix sequencer circuit and are discussed under that heading. The cpp pulse
is also applied to the timing
(~LHltrol c~rcuit,
shift
repi~;fer.
tro I c ircu it, see Figure 3-2.
f4113 - -- ----1
I BI8
~LD~F________~I~X~~
I
dpy
1 y
...:...;...-------------;1--'-......
I
1
I
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I
I
I- - - - - - - -,
14!27
I CI2
_
L ____ -~--i
scp
,
.------1-----001
R
82
:
shift
I
I
L ___s____ J
cpp
six
82
r:---------,
1~~~6
______ ..J
I
~H-I~----------------------------------------=cs~r
~
~cIX~_________________I~E~
c b
PLT
F
K
IL ___L
Figure 3-11
i
PA
J
I
_____
..JI
82
-=
Sequencer Control Logic Block Diagram
The scp pulse is produced by two other pairs of signals. Whenever the seven counter holds 6
8
the six signal enables a capacitor-diode gate in C12, allowing the next shift pulse to trigger
f
the gate, activating the pulse amplifier which produces the scp pulse. The scp pulse is also
produced by the iot command that starts the second ha If of the symbo I generati ng cyc Ie.
The
display enable level, dpy, is ANDed with the LDF pulse by a NAND gate in B18 to activate
the pulse amplifier that produces the scp pulse.
Deflection Modifier Circuits - These circuits consist of the X- and Y-axis modifiers, two identical 3-bit digital-to-analog converters with variable level amplifier gates shown in Figure 3-12.
Each D-A converter changes the octal number held by the seven counter and five counter into
the equivalent fraction of the common reference voltage, V.
r
3-27
{Refer to the subscript control
circuit description and Figure 3-6 for an explanation of V .) When any flip-flop is in the ONE
r
state the assoc iated inverter is cut off and its co lIector goes to the V clamping level. The rer
sistors of the D-A converters are weighed so that the resulting contributions to the output voltage are inversely proportional to their magnitude. The table in Figure 3-12 gives the relationships between the octal inputs (0 is -3 volts, 1 is ground) and the fractional values of V .
r
:cB:c; - - - - - - - -- - ---------;
:
51.IK
I02K
205K
VX
:
r; 667.J - - - H"--- - - - L - - - - - -
:C;-~I;:
--- - - - -- -- ------; Vy
51.IK
f - __ .l. -
I02K
--
205K
z- - - - -- Vi -
:
- - - - - ;:L,
I
I CIS
:
I
I
-
L - .: - ~ - ~ - Vr
I - I
-.: _ ~ __-__ ~ _ ~ _ -=- ____ ~ _ ~ _ -= __ ~ _ ~ __ ~ __ ~ _ ~ _ -= __ .J
-
51
0
51
I
Figure 3-12
-
-
7 1
51
2
0
-
7 1
I
7 1
2
Deflection Modifier Logic Block Diagram
The two output voltages, Vx and Vy , are applied to the reference inputs of the horizontal and
vertical deflection amplifiers, respectively (see Figure 3-2). A change in the reference voltage is equivalent to a corresponding change in the opposite direction of the deflection voltage.
The result is that as the counters increase their value, the V X and Vy voltages go more negative
and the spot is deflected in a positive (up and right) direction.
Shift Register - This circuit consists of a pulse amplifier and five 4216 quadruple flip-flop
modules.
These flip-flops are manufactured with shifting connections between the input gates
and the outputs, and with separate read-in gates.
Figure 3-13 shows the logic block diagram
of the shift register.
The reg ister is c Ieared to zero by two pu Ises, the c Iear plot pu Ise (c pp) from the sequencer
control circuit and a pulse produced by the pulse amplifier when the clear shift register (csr)
pulse or the DDP pulse occurs.
only clear sixteen flip-flops.
The two clear pulses are used because one pulse ampl ifier can
The csr and cpp pulses both occur whenever a coordinate loading
command or the first plot command iot instruction occurs. The DDP pulse occurs after a single
po i nt is d: sp layed or after eae h part of the symbo r generat i ng eyc Ie is over, i nsur i ng
•
I
d;be f,ore'" Ine secona'!.:0,.
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srg
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82
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i
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NOTE:
UNLESS OTHERWISE SPECIFIED
I. ALL TERMINATING RESISTORS ON
PULSE LINES ARE S2f1. 1/4W
2 BIO (4102R) IS USED WITH PDP-I
REMOVE WHEN USING PDP-4
3 DPY (--0) IS MB~ OR MBB I12 :
MBB I2 COMES FROM PDP-4
MB7 COMES FROM PDP-I
Figure 5-1
Type 30G Display Logic Diagram
5-14
XB,YB,X9,Y9 ARE NCT
ADclUSTABLE
- - - -...,
r,~;::;-4-
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IX
1-1:--'
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Control Logic Diagram
5-15
.
xb I
•
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f~
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x b 21
0
xb
5
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NOT USED WITH THE PDP-4
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1
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doy
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Figure 5-3
5::,)
J
Type 30G Symbol Generator Logic Diagram
17
5-16
l
I
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I
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RESET
82
INT-I
MB~
MBio
INT-2
MB"I
INT-3
ODP
sos
NOTE:
UNLESS OTHERWISE SPECIFIED:
I. ALL TERMINATING RESISTORS ON
PULSE LINES ARE S2!l 1/4W
2. BIO (4102R) IS USED WITH PDP-I
REMOVE WHEN USING PDP-4
3 DPY (-<» IS MB~ OR MBB I12:
MBBI2COMES FROM PDP-4
MB7 COMES FROM PDP-I
Figure 5-5
Type 30H Display Logic Diagram
5-18
XS,YS,X9,Y9 ARE NOT
ADJUSTABLE
1!304------,
I 825 100 'I- - - + 1 - - - - - - - - - - - - - - - - - - - - - - - - 4•..--.... INT-A
r-----,
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Figure 5-6 Type 30H Symbol
Generator Control Logic Diagram
5-19
x b '5
xb '
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Figure 5-7
Type 30H Symbo I Generator Logic Diagram
5-20
ALL 10 RESISTORS
82
ARE 3K
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r+: I I;~ I I~~ I I~~
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Figure 5-8 Type 30H Logic Panel
Wiring Diagram
5-21
GRV/W
WHTI VIO
GRN
04
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BOTTOM VIEW
OF SPU CONTAI NE R
~
E
··
~t0
.'
W .
·
M
F
N
CW
p :3 70-1
7 PIN AMP
LIGHT PEN
GAIN
MICRODOT
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CONNECT
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TO GROUND LUG
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r - - --
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S-308-FH
NOTES:
I.
RUN P-5 CAbLE BETWEEN
4688 SUCKET AND SPARE
SOCKE T.
2 .. RUN P-8 CAblE 8ETWEEN
4688 SOCKET AND 1705
SOCKET.
3.
RUN SHIELDEO CABLES TO
DUAL POT. BETWEEN 1559
SOCKET AND SIDE OF
CONTA.INER.
4.
RU"l CRT SOCKET CABLE
FkOM BACK EDGE OF
CONTAINER eETWEEN
4(;88 SOCKE'7' ANO 15s,=,
SOCKE T.
5.
DO NOT CLAMP P-4 AND
P-5 CABLES TOGETHER.
SCHEDULES
P_i}
P-5
F-B
®
CRT SOCKET
YOKE
CABLE
P-302-CCT
COMPONENTS IN CRT HOUSING 30G DISPLAY
01-04
0-666
05,DE:,
RI,R2
R3-RE:.
R7
50M 100 SZIO OR
EQUIVALENT
33K,2W,CAHBON COMf-'OSITION ±IO%.
',OK POTENTIOMETERS OHMITE 2 WATT TYPE Ab.
27Il,2W ':'vIRE WOUND OR CAhE:ON
COMPOSITION ± 109'0 OR ± 50/0.
TI
2N4S7A)5 ELECTRICALLY INSULATED FRCM
GROUND E::Y ANODIZED ALU'v1INUM V,ASHER
(1,(2
1.0 MFD 150V TANTALEX
B-PIN ~)OCKET IS S -308- FP.
2-PIN SOCKET 15 S-302-AB.
(3
IOOMFO)SO VDC)SPRAGUE.
R8
looon 1/4W±10%
C4
O.OOIMF D.
c5
3.9MFO J :OVOC TANTALUM.
HI,H2,H:\ARE ELECTRICALLY INSULATE D 5 TANDo~rs.
R9-R12 IOOf1.I/2WCAP.B'JN C'Y>'1PJSITIJN 10%
FOCUS cal L
ARE:
CS-A-22109 TO 22112
Figure 5-9
Type 30 Display Hous ing Diagram
5-22
,-----r------1----0
f' : ,
I
3,000
5%
')'1'"
I
T
P
L
n'"
I
04
1:
I
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05
1500
r,
5%
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C8
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r
T~'"
I
!
~------------~------------~~-------------~--------------+-------------~~------------~~l~~0~-15v
CHART
UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; 10%
CAPACITORS ARE M"MFD
D lODES ARE 0 ·001
TRANSISTORS ARE MA90
Figure 5-10
Type 1103 Inverter Schematic
A + 10VIA)
~
~ B+IOV (8)
~
RI
SIS,OOO
,....
02
~
,...
03
~
M
r'>
04
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R
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<>
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< 18,000
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H
.
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.
.
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01
MA90
R4
2,200 5%
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MFO
,
017
D-662
018
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07"
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o
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>- R9
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()
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r-.
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UNLESS 0 THERW ISE INDICATED:
RESISTOR S ~RE If4W; 10%
CAPAC I TO RS ARE MMFD
DIODES ARE 0-00 I
S
R8
2,200
C~
C2
120
Figure 5-11
02
MA90
5°"-
T
F
,
I
1
08
>. RIO
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Type 1110 Diode Schematic
5-23
TRANSISTOR 8: DIODE CONVERSI ON CHART
DEC
DEC
MA9()
D-OOI
D-662
orr---T---E-IA---:
~. 2N24~\A
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Figure 5-12
Type 1304 Delay Schematic
....- - - - - - - - - - - - o A + -:.
~-----------~..-----------+-----------
GNC
05
all
2"11308
2NI308
RI2
10POO
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270
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I
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Figure 5-17
f 2~149qA
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i
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Type 4127 Capacitor-Diode-Inverter Schematic
5-26
C -I~\I
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~---TII3-~---+l-~~o-·----'l1----c-8--1'--1c--i'~~~---ll
RIO
T
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0!3
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2,200
L-__________________l-______________________________
W_-'_T_____
iN_-______________________________
U NL ESS OTH ERWISE INDICATED:
RESISTORS ARE 114W; 5%
CAPACITORS ARE MMFO
DIODES ARE 0-001
~
--------------~1~--~--oc
I_WIDe-J-
o0-862
-OO!
Figure 5-18
~ 0- 001
_._---
IN218
----
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[~'11
i
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1
i
------
Type 4128 Inverter-Capacitor-Diode Schematic
~---------~If---------O
017
H 0 01
CONVERSIO~ ..~,.,
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--NC:-- 2NI499A
1I01!4
616 _4 -,
0- _ -;P>--__--+__.....______°-i1410111
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cf " "
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y
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015
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UNLESS
OTHERWISE INDICATED
ARE
il4W; 10%
RES.STORS
Figure 5-19
I
Type 4141 Diode Unit Schematic
5-27
S
L
--TfC2
,OOIMFD
l
RI4
3,000:;
5"10
•
~ DIO
f
?
•
C3
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_ _ _ _ _ _ _+--'C
1:
6w
y
Z
R
T
SET ZERO
UNLESS OTHERWISE
ONE SET ADD ZERO
ONE OUT
INDICATED:
OUT ZERO FFB OUT
FFA FFA
FFA fFA
FFB
RESISTORS ARE 1/4 W; 10%
llilS JUMPER IS NOT INSTALLED
CAPACITORS ARE MMFD
WRING MFG. IT IS USED WHEN INHIBIT
DIODES ARE D-OOI
FEATURE IS NOT NEEDED AND
-THIS JUMPER IS INSTALLED DURING MFG STANDARD LOADING OF FFC
IT IS NEEDED WHEN INHIBIT FEATURE
IS DESIRED,
IS DESIRED.
K
*"
N
P
ADO ZERO
HC OUT
Figure 5-20
E
ONE
OIJT
FFC
FFC
ADD ZERO
FFO OUT
FFD
Type 4215 4-Bit Counter Schematic
CS
2200
~I~------~~------------------t------------------.------------------~--,
CLEAR
. "016
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A
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::::OJ> IC\
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ONE
ONE
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LEVEL
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v
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W
ZERO
OUT
FF A
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t,::'''' \101 4
1
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0-001
o-en
0-114
1010114
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20'41"
Figure 5-21
Type 4216 Quadruple FI ip-Flop Schematic
5-28
B
C~EAR8>-----H--------1~----------"""-----------"""------------<,..,
oz.
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+ 10, IAI
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CI
330
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5%
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P
READ IN
L
ZERO
OUT
D
T
Z
ZERO
IN
ONE
OUT
ZERO
B
B
A
OUT
I
UNLESS OTHERWISE INDICATED
RESISTORS ARt:: 112w; 10%
CAPACITORS ARE M MFD
TRANSISTORS ARE MDI14
DIODES ARE D-ool
Figure 5-22
b----i~........-JI
LEAR
C23
2200
r1~
330
CHART
DEC
:
Type 4217 4-Bit Counter Schematic
A
r-~--------~--.-------------}--~----------+--~--------t---ov.'c
:> :>
.----+---4------..----+----1>f-------_----+--)~-----""1?....--+--o8. 0
DI~~~~O> >68RO~0 68~600>
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01
02
03
04
05
06
08
07
..............HH
I
~
R (0
3000
5"10
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3,000
5"10
5%
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3,oOC
5"10
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3.000
5%
J
RI7
DIO"~ l,oj C I'
0664
D664
C6
C7'
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OUTPUT
1500 V 5
cia
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330
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C 1:..1
330
1500
5%
D- 22
3,J00
5"10
150 r'
...... ~
~
rv- 664
UNLESS ';THfRwISE 'NDICATfD
RES.STORS ARE 1/4 W,IO%
CAPACITORS ARE M..,FO
DIODES A'lE c)-OOI
TRANSiSTORS ARE MD-I:4
,-
nUT
.
:
b_D6~
0-652
0"664
Figure 5-23
Type 4218 Quadruple Flip-Flop Schematic
5-29
:::
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:
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. 2NI499A
-.
N276
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>
I
I
6 ..
I
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D7
D8
D-003
0-003
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DII
00
D9
R28
390
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~~-----4~~t_---t__r---;------+_-----t_---~----+_--_+---4----+_--~--~~~~C-15V
UNLESS OTHERWISE
RESISTORS ARE 1/4 W; 10 %
CAPACITORS ARE MMFD
DIODES ARE D-662
M
Figure 5-24
'.... 1;
o---l f--_-.....---,
U
CI 330
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310
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