U60_Hitachi_HD68450_DMAC_Application_Notes U60 Hitachi HD68450 DMAC Application Notes

User Manual: U60_Hitachi_HD68450_DMAC_Application_Notes

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(213}~7596

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H068450 OMAC
(Direct Memory Access Controller)
APPLICATION NOTE

#U60

.HITACHI

H680DMAC-EAN

When using this manual, the reader should keep the following in mind:
1. This manual may, wholly or partially, be subject to change without notice.
2. All rights reserved: No one is permitted to reproduce or duplicate, in any
form, the whole or part of this manual without Hitachi's permission.
3. Hitachi will not be responsible for any damage to the user that may result
from accidents or any other reasons during operation of his unit according
to this manual.
4. This manual neither ensures the enforcement of any industrial properties
or other rights, nor sanctions the enforcement right thereof.

HD68450 DMAC
The HD68450 DMAC is a 16-bit microprocessor that is bus-compatible with
HMCS68000 systems, and has the following features:
• 4 independent DMA channels (programmable priority order)
• Maximum Transfer Rate is 4M Bytes/sec (8MHz)
• Various Multi-Data-Block Transfer Modes: Continue Mode, Array Chaining
Mode, and Linked Array Chaining Mode
• High Reliability of Data Transfer facilitated by Error Detect, Error Interrupt
Vector, and Exception features.
• 16M-Byte Address Space (same as the HD68000)
• Memory-to-I/O Device Transfer, Memory-to-Memory Transfer
• Programmable Operation Mode and Transfer Mode
• External Transfer Request, Internal Transfer Request (Auto-Request)
• Programmable System Bus Bandwidth Utilization
The HD68450 is also applicable in other processor systems (the 8086 system).

CONTENTS
page
1.1
1.2
1.3
1.4
1.5

HD68450 DMAC Operation ................................................ .
HD68450 Operating State .. " .. , .................. , .................. , .......
Transfer Types ....... " . " ........... '" .. , ... , ... , ...................... , ...
Internal Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

2.

System Example ............................................................. 10

3.
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12

HD68450 Transfer Operation and Circuit Examples .......................... ,
FIFO Register Operation ....................................................
FC Application Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DMAC Interrupt Request Examples ..........................................
Peripheral Control Line (PCL) Operations ....................................
Demultiplex Examples for Address/ Data Multiplexed Bus ................... ,
HIBYTE Application Example ...................... ~ . . . . . . . . . . . . . . . . . . . . . . ..
Low Speed I/O Device Circuit Example ......................................
High Speed I/O Device Circuit Example .....................................
6800 Family Application Examples ...........................................
Encode Example for Exceptions ............................................. ,
Priority Circuit Example (Daisy Chaining) ....................................
8086 System Application Examples ...........................................

13
13
13
13
16
17
17
18
18
18
18
18
18

4.
4.1
4.2
4.3
4.4
4.5

HD68450 DMAC Control Program ..........................................
Basic Control Routine .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Transfer Termination Routine ............................................... ,
Continue Mode Program Example .......................................... ,
A Program Example in Array Chaining Mode ............................... ,
A Program Example in Linked Array Chaining Mode ........................

39
39
39
39
39
45

5.

Data Sheets ................................................................. 49

I.

I
1
5
7
8

HD68450, HD68450Y DMAC ............................................... 51
HD68000 Series ............................................................. 99

I. HD684S0 DMAC Operation

Auto-Request when a certain internal condition is satisfied. The

R'EQ signal outputted can then inform an external device of the
I.I HD684S0 Operating State

start of transfer. The 2nd and succeeding operands can be transferred with External Request.

The H D68450 has internal control registers and performs
required operations through control w"rds written into the registers by the MPU. The DMAC state is divided into three modes:
I) MPU Mode: A bus master (MPU, DMAC) chip-selects the
DMAC, or the MPU acknowledges the DMAC's interrupt
request, reading or writing the contents of the DMAC's
internal registers.
2) DMA Mode: The DMAC owns bus mastership, and is
transferring data or preparing for data transfer.
3) IDLE Mode: The DMAC is waiting for a transfer request or
MPU access, and most of the bus control signals are
three-stated.
In normal operation, the DMAC transfers operands in the
lowing sequence:

1.2.2 Block Transfer Classification
The DMAC supports data block transfers by request generation methods shown in Table 1.1.
In Continue Mode, the DMAC transfers a pair of blocks
without software intervention. It can transfer multi blocks by
giving the next block information (address and word count) to
the DMAC internal registers, and setting CNT bit again during
the transfer of the second block.
In Array Chaining Mode, the MPU prepares for the array table
(transfer address and word count listed in main memory). The
DMAC transfers multi data blocks up to "2'· =64K" according to
the order in the array.
Linked Array Chaining Mode is almost the same as Array
Chaining Mode, except the block information in the array need
not be listed in the transfer order sequentially. Instead, linked
address (block information which is going to be transferred next)
is given as a part of the block information.
Examples of array tables are shown in Figure 1.2. The Linked
Array Chaining Mode is more flexible in composing an array
table, to change the order of transfer, or to skip blocks in the
transfer order. For example, when block #2 is skipped in Array
Chaining Mode, block #2 address and word counts must be
replaced by block #3 information in an Array Table, and the
former block #3 must be replaced by block #4, etc.
Linked Array Chaining Mode provides an easy method of
changing only "block #2 information address" in block #1 information to "block #3 information address." When one block
transfer has been completed, the DMAC automatically reads the
next transfer block information to the internal registers. Array
Chaining has 3 word read cycles, whereas Linked Array Chaining
has 5 word read cycles (larger overhead).
In Continue Mode, fewer clock cycles are required to transfer
information between the DMAC internal registers. The MPU,
however, must write the next block information in those DMAC
internal registers when 3 or more blocks are transferred.
Selection of a suitable mode for multi block transfers should
consider such factors as time, I/O device speed, and program
developing effort. Table 1.3 shows overhead clock cycles for each
mode:

fol~

(I) The initiation phase, in which the MPU sets up control registers, transfer address, and transfer counts. The DMAC is
enabled to accept transfer request.
(2) The transfer phase; the DMAC receives requests, transfers
data, and writes the transfer status into the error register and
internal status register after completion of the transfer.
(3) The termination phase; the M PU checks the post-transfer
status.
The M PU determines the operation types and checks the
transfer state by writing and reading the contents of the internal
registers.
In addition to normal operations, bus exceptions are also
prepared (see Chapter 1.5 Exceptions).
1.2 Transfer Types
1.2.1 Classification of the transfer modes in terms of request
generation methods.
Transfer modes which the DMAC supports are shown in Table
1.1.
The External Request is generated by asserting the R'E'

~

/L

CS
AS

-

f.DS

VDS
H/\V
DTACK

I/O device
control

Bit

Bus arbitration{
Interrupt reques t / {
Recognition

BG
BGACK

HD68450

DMAC
IRQ

lACK
OWN

AddreSS/Data!
demultiplex

VAS
IIJIlYTE
DilEN

DOli!

Exception {
Function cOde{

DOSE] Transfer end

BEC o
BEC,
BEC,

signal
llTC

FC o
FC,

Fe,

II

Vss 121

FIGURE 1.8 HD68450 Signal Lines
simultaneously, or before ~ assertion, and the BEC values
remain in the same level for two or more clock cycles. The HALT
exception is not implemented until DTACK input. If BEC's are
asserted after DTACK, the bus cycle occurs normally.

outputted at the end of each block transfer in Continue Mode,
and when al\ blocks are completely transferred in Chain Modes.
This signal is asserted at the same time as the last ACK signal of
the transfer. DONE, therefore, is not outputted in the transfer
cycle to the memory in the very last bus cycle when the transfer is
from device to memory Dual Addressing.
DONE is also used as an input signal in order that the I/O
device informs the DMAC of the transfer completion. The
DMAC monitors the signal during asserting ACK signal. After
the DONE assertion, the DMAC stops data transfer when the
operand transfer is completed, and the channel operation terminates. When the DMAC and I/O device simultaneously assert
DONE, the DONE inputted from the device is ignored. The
DMAC outputs DTC whenever it recognizes DTACK. In the
case of a 6800 compatible device, the DMAC detects the trailing
edge of E clock to output DTC. I/O devices can latch the data by
using the falling edge of the DTC assertion (DTACK is also
useful). The DTC negation indicates the bus cycle completion.
This signal is not outputted when i5'i'ACiC. is not inputted, or if
exceptions are entered, in order that the I/O device can detect
transfer abnormality.

Halt
When Halt is asserted during DMA transfer, the DMAC relinquishes the bus after receiving DTACK, and after normal bus cycle
completion. The D MAC does not arbitrate the bus until HALT is
negated.
Halt is useful in the following cases:
(I) When DMAC turns over the mastership to another bus
master without changing the number of the DMAC's bus
cycles. Even when the DMAC is using the bus continuously
and does not relinquish it, another bus master can get the
mastership by halting the DMAC. In this case the DMAC
resumes the bus cycle after the bus arbitration (total number
of the DMAC's bus cycles does not change).
(2) When transfer "trace" is performed by executing single step
bus cycle.
Bus error
When an error occurs during transfer. and the DMAC can not
continue the operation or can not get the correct results. Bus error
is asserted to stop the transfer abnormality.
The DMAC Bus error sequence is as follows.
(!)stops the transfer and sets COC bit and ERR bit in CS~
checks INT bit in CCR. If INT = I. the DMAC asserts IRQ
signal to interrupt the MPU.
CD Keeps the address where the bus error took place and the
transfer count left over in the Address Register and Transfer
Counter respectively in the channel.
CD relinquishes the bus without other channels' transfer requests.

1.5 Exceptions
To be sure of data transfer, the DMAC can stop the bus cycle
and retry it, or leave the recovery to the other bus master if an
abnormal transfer occurs. The Exceptions are requested by the
external devices and are encoded into 3 signals. BECO-BEC2, and
inputted into the DMAC. BEC exception conditions are shown
in Table 1.6.
The DMAC samples BEC signals with the rising edge of the
clock and recognizes an exception condition if the ~ signals
remain in the same level for two or more clock cycles. The DMAC
carries out 1rnC" exceptions only when BEC assertion starts

o

8

1...S1.JLs1J"L

CLK
min" 2

eD

clocks

I

BR
2~:l.5

cI ocks

l.'~:1.5

clocks

,.

J®

I

.-

BG
(3)

I

r

b)

BGACK

BUS cycle

®

o C)ock---MPIJ"CyC le

(4)

MPU cycle

co

4.5

ACK

•. 5

clocks

,

DTC

DMAC

\

(b)

MAX. 12.5 clocks+MPU cycle

I\.

"

(a)

cycle

®

7

MPU cycle

"

'--V'-

CLK

MPU cycle

.,

Cycle Steal Mode
(sensed by
rising edge of REQ)
FIGURE 1.9 Bus Arbitration Timing

BUS Idle

DMAC cycle --+- Idle +MPU
cycle

TABLE 1.6 (BEC) Exception Condition Types

BEC2 BECI BECo

Applications

Exception
Conditions

1

1

1

No exceptions

Usual operation

1

1

0

Halt

Used when DMA trnsfer is stopped
temporarily by external circuits.

1

0

1

Bus error

Used when a serious system error
occurs. For example, the DMAC bus
cycle does not terminate.

1

0

0

Retry

Used when the DMAC bus cycle has not been
carried out correctly, and needs retry.

0

1

1

Relinquish
and Retry

Used when the MPU uses the bus before the
termination of the DMAC bus cycle ,and
when the DMAC cycle must be continued
from the following cycle.

0

1

0

Not used

--

0

0

1

Not used

--

0

0

0

Reset

Power on reset.

System reset.

Relinquish and Retry can be used when the MPU service is
necessary to correctly transfer the operand after the bus cycle
starts. If the I/O device asserts Relinquish and Retry while
requesting an interrupt to the MPU, the DMAC releases the bus
so that the M PU may service the interrupt routine, and negates
Relinquish and Retry-recovering the fault with minimum overhead. The DMAC obtains the bus again and resumes the transfer.

Bus error is useful in the following cases:
(I) When preventing system dead lock (not receiving DTACK
signal), "a watch dog timer" is used, and the Bus error is
asserted when the time is out.
.
(2) When page fault is recognized in virtual memory environment, Bus error is asserted.
Retry
When Retry is recognized during the DMAC bus cycle, the
DMAC stops the bus cycle and repeats the same bus cycle right
after the negation of the Retry signal. During the whole sequence,
the DMAC holds the bus (OWN and BGACK are kept asserting).
When the DMAC accesses memory or device, and an error is
detected in the transferred operand, external circuitry asserts
Retry to transfer the operand again. For example, when an error
is found through parity information during a bus cycle, or when
DTACK does not return in spite of correct address, Retry can be
performed.

Reset
When the DMAC recognizes Reset, it relinquishes the bus,
clears GCR, and resets DCR, OCR, SCR, CCR, CSR, CPR, and
CER of all channels. The interrupt vector registers are set to $
OF(HEX), un initialized interrupt vector number.
2. System Example
HD68450 DMAC in HMCS68000 is shown in Figure 2.1.
Since only basic signals are shown, users are required to add
necessary circuitry to an actual system (See Chapter 3). If whole
address space is managed with a memory management unit
(MMU), the MPU physical address space is the system address
bus. The Circuit example is shown in Figure 2.2. The MMU's
page fault is encoded to be the DMAC's Bus error input signal.
Refer to Chapter 3 for further examples of each circuit.

Relinquish and Retry
When the DMAC recognizes Relinquish and Retry, it sets all
control lines, data bus, and address bus to three state, and
releases the bus temporarily. If the BEC exceptions are negated,
the DMAC outputs BR again to get the bus mastership and
retries the bus cycle in which Relinquish and Retry are asserted.

10

,........

Do~ D"

~==;=~~====1Data

Do ~D,.

r-

-

r-

& Address Bus Iv----YI

Interface
FDC,
etc.

:=-

I----

HDC,
etc.

- REQo}
~ ACK Channe 1

AI---A71¢==~

-RE(.!,} ~~anne 1

ASI-----l
LDSI-----l
lJDSI-----l
R/WI-------j
DTACKI-----l

o
'------- PC Lo

+0

'-----lACK,
' - - - - - l p c I.,

HD6845U
OMAC

REQ2} channel

CS~

~ --

P
r=

J.,

-y

-"
-------v

rf--

rr-

/---------;ACK

'--

-

1------llPi'iC"'IC,: + 2

r---

-

A,~A23

Mem &

MMU

-AS
---

f--

Do ""'-'D 15

AS
LDS
lJDS

IVW
DTACK
FCo-FC,
ERROR

P;lrall ed
I/O

Device,
~,tc

.

H0680UO

MPU

lJi)S

,...-

IVW

-

DTACK
VPA
VMA
E
3

-

r-§=rr--

Ene,

....

FIGURE 2.1 Basic System Configuration

11

r--

Periphr.

It--

'-

-

III-

1-----+---1E

t-t--

1 - - - - - - 1 1 RQ

-

'-

r5V +5V
R!W

1

AS
A I-A 23

23

HD68000

+5V

MPU

FC o-FC 2

PA I -PA7

t

7

MMU
~

IPL o-IPL 2 0--3

As-A23

16

e

MAS
AI-A,

5

FC o-FC 2

Circuit

R/W
AS
FC o-FC 2
AI-A 23
IRQ

r-r-

PA s-PA 23

T

3
23
~~+5V

!+!iV

1

OWN
H068+50

~
7b

OMAC

R/W
AS

BEC 2 :>--<: O2

60

BEe. D--{; 0\
BEC o
0

50

r
1

IRQ

HV~

2

~

FAULT

.c

""

~)



C
0

U

assigned in a 68000 system (e.g., the supervisor data area or the
user data area) becomes possible in Dual Addressing Mode. (See
Table 3.1)

3. "D68450 Transfer Operation and Circuit Examples
3.1 FIFO Register Operation (Data Pack and Unpack)
As shown in Figure 3.1, the DMAC possesses a 3-byte FIFO
(First In First Out) register, which reads and writes an operand in
byte or word unit. The FIFO register makes it possible to operate
on various operand sizes (abbreviated as OP), and to operate on
I/O devices with various port sizes (data bus bit length, abbreviated as P) for memory to I/O transfer. In these operations, the
transfer mode is Dual Addressing.
In Figure 3.1, I/O is an I/O device with P=8, and even address.
When the DMAC transfers operands from 1/0-1 to memory I to
6, it reads two byte-operands in the first and second bus cycles
from 1/0-1 into the FIFO, and writes a word operand in the third
bus cycle from FIFO to memory. Thus, the bus efficiency of
DMA transfer is increased with PACK operation (to transfertwo
byte-operands as one word). When the transfer is from memory
to I/O-I, a word operand is read from memory I and 2 into the
FIFO, and is written as two byte-operands into 1/0-1 by
UNPACK operation (one word into two bytes).

TABLE 3.1 68000 Function Code Table

Function Code
Classification

3.2 FC Application Examples
The DMAC possesses the following three registers in each
channel:
• MFC (Memory Function Code register)
• DFC JJ)evice Function Code register)
• BFC (Base Function Code register)
In memory access bus cycles in both Single Addressing Mode
and Dual Addressing Mode, the MFC contents are outputted
through FCO-FC2 pins at the same time as address output. In
device access bus cycles in Dual Addressing Mode, the DFC
contents are outputted. In Array Chain and Linked Array Chain
Modes, the BFC contents are outputted in the bus cycles which
load the block information from the Array Table in memory.
Because arbitrary values can be written in those function code
registers, the data transfer between different memory spaces

FC2

FCl

FCO

0
0
0
0
1
1
1

0
0

0

1
1

0

0
0
1

0

1

1

1

1
1
1
0

(Unassigned)
User Data
User Program
(Unassigned)
(Unassigned)
Supe~visor Data
Supervisor Program
Interrupt Acknowledge

FCO-FC2= III indicates the interrupt acknowledge cycle. The
DMAC should not output this code. When lACK input is
asserted during DMA transfer, address error occurs.
3.3 DMAC Interrupt Request Examples
The DMAC can output ~ to request an interrupt to the
MPU under the conditions shown in Table 3.2. "L~ means IRQ
assertion. I RQ is asserted as long as those conditions are satisfied.
To negate I RQ (make "H~ level), INT bit in CCR must be reset, or
"FF(HEX)" must be written in CSR to reset CSR.

/'

•

1/0-1
(OP=8, P=8,A=EVEN)

G) (3) (2) (i)

•

~

1/0-2
(OP=B, P=B, A~ ODD)

:'\

I':

•

t:::)

¢

,,

,,
,,
,

,I
I
I
I
I

FIFO

~

,

,,
,L ___________________

~

<=:> ® 0

I--

I
I
I

¢: ~ CD

I

~

D. - D" data bus
Do- D7

"(i)

(2)

(3)

(I)

(5)

(6)

• Mem. (OP=B

data bus

or 16, P=lti)

FIGURE 3.1 Data Bus Connection Example
in Dual Addressing Mode

13

®

-

(2)

(t)

(I) (3l @ (1)

• 1/0-3
(OP=8 or 16,P=16)

DMAC

r- - - - --- -- - -- - -- ----,

-I

® ®

HV

JID68000

JID68450

MPU

DMAC

IPLo p---~Ao
IPk
AI
IPL,
A.

b-----~-qIRQ

EI
FIGURE 3.2 Connection Example of IRQ and lACK

Various transfer examples using FIFO are given in the followings.
Example 1)

I/O (OP=8, P=8, A=EVEN,
DMAC bus cycle
R-B
1 byte
W-B
1 byte
R-B
1 byte
W-B
1 byte
R-B
1 byte
W-B
1 byte

*
Example 2)

CD to @ )--...Memory

---- I/O

(OP=16 or 32, P=16,

CD

to

®)

read from memory (CD (6) or I/O ( CD ® )
write to I/O (CD ®) or memory (CD @)
read from memory ( ® ®) or I/O ( Q) ®)
write to I/O (Q) ®) or memory ( @ ®)

15

Figure 3.4 shows BIT mask example. Because an interrupt has a
higher priority than a data transfer, BG should be masked in
lACK cycle.

Figure 3.2 shows IRQ/lACK examples in the DMAC and the
MPU system, where the interrupt level of the DMAC is four.
However, this level is arbitrary.
When the multi block transfer is in Continue Mode or in
Chaining Modes, the transfer status needs to be checked between
block transfers in some applications. In Continue Mode, since the
BTC bit is set after the first block transfer completes, the
DMAC can request interrupt according to Table 3.2.
In Chaining Modes the DMAC cannot request interrupt at the
end of each block transfer. Instead, when the last block transfer
completes, interrupt request is possible because the COC bit is
set. In Chaining Modes, if the DMAC needs to request interrupt
at the end of each block transfer, circuits shown in Figure 3.3. are
required. Appropriate values have been written in BFC, MFC,
and DFC, and the PCL signal is formed by decoding thefunction
codes, to enable the DMAC to request interrupt. (It should be
determined whether the FC's are used by the Memory Management Unit (MMU).

3.4 Peripheral Control Line (PCL) Operations
pin of each channel can be used for four different functions realized by setting PCL bits and DTYP bits in DCR as
shown in Table 3.3. However, Mode 3 becomes invalid when the
device type is 6800, or ACK type with IrnAUY, or 68000-type in
AutO-Request Mode. Similarly, Mode 4 becomes invalid when
the device type is 6800, or ACK type with READY.
In Mode I, PCT bit in CSR is set when PCL line is asserted
("H" to "L"). Mode I is usefulto record a status change of an 1(0
device. The timing chart for setting the PCT bit is shown in Figure
3.5.
Mode 2 is the function to interrupt the MPU via the DMAC
from the I/O device, using the PCL signal change from "H" to
"L". In this case, the INT bit of CCR should be set. The timing

rn.

TABLE 3.2 IRQ Output Condition

CCR

CS R
IRQ Output

INT

cac

BTC

a

x

x

x

x

x

x

X

H

1

0

0

0

0

x

0

X

H

1

1

X

X

X

a

x

x

L

1

0

1

0

0

1

X

X

L

1

0

0

0

0

X

1

X

L

NDT ERR ACT

PCT'" PCS

*: When the PCL function is set on interrupt input.
X: don't care.

FC.
FC,
FC.

AS
00684050

0068000
MPU

DMAC

LSl408

t.:>--+-d IRQ

EI
FIGURE 3.3 Circuit Example to Generate Interrupt at the
end of each block transfer in Chaining Modes

16

.
~

HV

L

o

BR

"'p---c

I3G

LS 161
HD6R450

S

Q

D

t=

LS74-

C\

Q

r--

CLEAH
E.p
ET

>CK

DMAC
~ImY

~

RESET

CLK

1

CLK
FIGURE 3.4 BG input Mask example

3.5 Demultiplex Examples for Address/Data Multiplexed Bus
As described in Chapter 1.4, (JWliI, UAS, 1'5lffiN, and DDIR
are used for bus demultiplexing. OWN is used for bi-directional
buffer control. Signal application examples are shown in Figure
3.6.

chart from PCl signal change to I RQ output is shown in Figure
3.5.
Mode 3 is used to ascertain the internal process time interval to
activate channels, since the STR bit of CCR is set. Table 3.4
shows the necessary ClK cycles in Mode 3 from the MPU write
cycle to set STR bit until start pulse output.
Mode 4 aborts the current transfer. This signal is inputted
through Pet,and EXTERNAL ABORT ERROR is recorded in
CER, and ERR bit is set in CSR. Timing is shown in Figure 3.5.

3.6 HIBYTE Application Example (Bus Matching)
Data transfer between devices with different port sizes in Dual
Addressing Mode is described in Chapter 3.1. In Single

TABLE 3.3 Conditions to set PCl functions
DCR
Mode

PCL

1

Status

Status Input with Interrupt

3

Start Pu I se ,Nega t ive 1/8 CLK

Abort

DTYP,H DTYP,L

REQG,H

PCL,H

PCL,L

0

0

x

x

X

0

1

X

X

x

1

0

x

x

0

1

x

0

x

Input

2

4

OCR

Fune t i on Mode

In pu t

1

0

1

1

x : don't care

CLK
pCL Input
(Mode 1)
PCT Bi t Set

(Mode 2)
PCT Bit Set

----4-~.J

_____

~..J

IRQ UJtput

(Mode 4)
PCT Bit Set _ _ _ _ _ _- J

I

ERR Bit Set ________________________________________~/

FIGURE 3.5 Timings for Mode 1,2, and 4

17

Figure 3.14 shows an application of HD68A43 (FDC) and
HD68B21 (PIA). The FDC makes a request by setting TxRQ
High. The negated TxRQ is inputted to PCL as READY.

TABLE 3.4 Clock Cycles from the MPU Write Cycle
to set STR bit to output Start Pulse (Mode 3)
Trans fe r Mode
No Chain
A r ray Chain
Link Array Chain

CLK Numbers*

3.10 Encode Example for Exceptions
An Exception request is made by external circuits and is
inputted into the DMAC's BEC" ~ BEC 2• Figure 3. I 5 indicates an
encode example.
Exception Examples: Figure 3.16 shows the bus cycle time out
error example. The transfer stop example is given in Figure 3.17.
If the DMAC does not have the bus, do not input the bus
Exceptions. Exceptions should be inputted after the AS output
(or UAS negation), as shown in Figure 3.15.

39
59
61

*MPU write cycle: 14 clock cycles
DMAC memory read cycle: 4 clock cycles
Addressing Mode, HrnY'fE is used for bus matching.
Figure 3.7 gives an example of bus matching between an 8-bit
I I 0 device and a 32-bit memory system. As shown, the I I 0 device
must be in the lowest byte of the data bus. HIBYTE is outputted
only when even address is accessed, and when the DMAC operates byte operand in the Single Addressing Mode. See Figure 3.5.
The example shown in Figure 3.8 is between a 16-bit II 0 device
and a 32-bit memory system.

3.1 I Priority Circuit Example (Daisy Chaining)
When multi DMAC's are used, priority circuits like Daisy
Chain are required. In the following example, the D MAC nearer
the MPU has higher priority.
3.12 8086 System Application Examples
Applied in an 8086 system, the H D68450 .is superior to other
DMAC alternatives because of the following features:
I) High speed data transfer operation by Single Addressing
Mode
2) Ease of operation for multi block transfer
3) Maximum bus exception utilization
Basic differences between the 8086 system and the H D68450
are as follows:
I) Address bus, data bus
2) Memory Structure
The H D68450 and the 8086 are different in arrangement of
address and data bus. Address bus is connected to the system bus
through LS373 latch. Data bus is connected to the system bus
through LS245, bi-directional transceiver.

3.7 Low Speed I/O Device Circuit Example
Figure 3.9 shows a circuit for a low speed 110 device; e.g.,
floppy disc controller. Figure 3.10 gives the timing chart. Since a
DMA transfer request signal (DRQ) from a low speed 110 device
is generated in every D MA transfer cycle, the channel is programmed to be External Request and Cycle Steal Mode. The data
latch timing in write cycle (memory-device) is the timing when
the write enable signal (WE) changes from "L"-"H". Data on the
data bus is valid only while the data strobe signal (UDS or LDS)
is "L"; therefore, the data latch timing must be made from DTC
assertion timing ("H"-"L"). This assertion occurs at least 30ns
earlier than the UDS or LDS negation ("L"-"H").

BIlE

.. 3.8 High Speed I/O Device Circuit Example
FIFO is used as external data buffer in the example shown.
Figure 3.11 shows the application of the DMAC and FIFO.
Figure 3.12 gives the control timing chart in read and write cycles
to FI FO. Since data of several words is continuously transferred
in DMA transfer between FIFO and memory, the external
request mode should be set to Burst Mode. The data write timing
to FIFO is derived from DTC output, and the timing to negate
the Burst request from "L" to "H" is made with up I down counter.
In write cycles to FIFO, the Burst request is negated synchronously with DTC assertion, when the counter number reaches
"the operand number transferred in a burst"(" I6" in Figure 3.11).
In read cycles from FIFO, the Burst request is negated synchronously with DTC when the counter number becomes two. In
Burst Mode, the Burst request in both read and write cycles
should be negated before the last transfer starts. In the last DMA
transfer when TC=O (transfer words counter = 0), DONE is outputted at the same timing as ACK. This signal is used to reset the
Burst request.

ADo - AD I ~---",I

Do -D '5

8086
LDS
UDS
A, - A7

3.9 6800 Family Application Examples
Since 6800 family devices are given their addresses on 68000
memory, and are used by memory mapping, the transfer mode is
Dual Addressing. The block diagram is shown in Figure 3.13.
Please note:
I) E clock is inputted from the PCL pin, and is used to synchronize 6800 devices and the DMAC.
2) 6800 devices close the data bus at the falling edge of E clock in
read cycle from the 6800 device. The D MAC, however, latches
the data when DTC is asserted. Therefore, the data outputted
from the 6800 device needs to be latched by the external latch.
3) For 6800 device chip select, the address decoder and the
address strobe are used.

LDS

<===============>

UDS
A, - A7

Do -D '5

HD68450
The H D68450 and the 8086 have different ways to address
memory. When HD68450 is used in the 8086 system, UI)S'
(Upper Data Strobe) should be connected to AOand LDS (Lower
Data Strobe) to BHE. For data bus, the upper byte bus and the
lower byte bus must be switched. In this configuration, the 8086
can access the internal registers of the H D68450 by the same
method as memory.

18

r  OE DIR

ro-ny

'8

Do/AI8 D,./A ..

R/W

~~
OE

HV

f

rLS24.5
~idiroctional
Buffer

HIBYTE
BGACK ~

L
UAS

1='

OWN

LS24.5
~idiroctional
Buffer

~ ~

ps-Dt;,
'll

-

R/W
HIBYTE

*

BGACK

'---

LS373
D-type
Latch

f--

~

r--

~

A.-AI'
8

jG~
OE

V

~

LS373
D-type
Latch

~

A IS -A23
8

'"

~

i:1l

!!

'"'"
'-'

al

-.,

'"
al

LDS
UDS

LS24.5
idiroctional
Buffer

/

7

t

jDIR
IDIR

AI -A7
7

OE
OE

---

•

LS245 IS used as a buffer for HIBYTE signal.
FIGURE 3.6 Demultiplex Examples for Time Multiplexed Bus

''""

19

'0...

!!.,

""
~

§

u

0

LDS
IUDS

------'

r--

"'-

:I

al

al
"'"

~

LS24.5
Bidiroctional
Buffer

'"

'-'

:I

A.-A,

------'

------'

"'-

'"'-

II-BUS

32 bit memory
31

LH IMH iMLi

lJIIlh----<
,-,n--+-<

0

AI

LI

AI UDS LDS
II
H ···0
L
MH ···0
H
L
ML ···1
L
H

L ... 1

H

L

8o-S3; select input

(II. MH . ML. L)

8 Bit

I/O

FIGURE 3.7 Bus Matching (8 bit 1/0-32 bit memory)

H-BUS
32

bit memory

31

0

IH!MH!ML!LI

H
MH
ML
L

AI DDS LDS
···0
L
II
···0
H
L
···1
L
H
... 1
H. L

So-§; ; select

R!W
HIBYTE

input

(H, MH, ML, L)
16 Bit

I/O

FIGURE 3.8 Bus Matching (16 bit 1/0-32 bit memory)

20

P-----------------------------~DRQ

ACK

p---lr--------~--------------__qCS

+5V

Low Speed
I/O Device

AO}

Address Bus { 1\0

At

AI

register
select "11"
data registe

Data Bus

*

to negate WE when DTe is not outputted
FIGURE 3.9 Low Speed I/O Device Application

I

/1
I

\i

I
I

I

\

I

\

I

I

DTC

I

LJ

I

I
I

:::-.

J"-

I

I

I

I

I

I
I

I

1

-;\

I

I

\1

~

I
JL

\

~J

I

I

I

I

1
I
I
1

1

1

I

o...----READ

1"'1

eYeLE.----~o-J1

JJ

,

I

I
I

I

1

~

~

\

I

I

1
I

1

I

·--WRITE

1-1

FIGURE 3.10 Timing chart of Fig. 3.9

21

ttT-

1
,~

y

"

.

'J

1
'U

I

I

I

11
J

"
~ ",

1

1

j

1

1
[\ I

j

I

I

I

data bus

I

Jf-'-\

I

eyeLE~

r--

rA

MPU

"

.

FIFO

y

Qo
I

Do
I

A

Q15 DIS

r:-AD cycle
A

MEM

,

L

FIFO

Do
I

"

I

"

.......

........

System Bus

*

Qo

DIs QIS

..

DMAC

,

WRITE cycle

Local Bus

Hard Disc Controller

(a) System Example of FIFO used as HOC Buffers
FIGURE 3. I I FIFO Application Examples

22

HDC

•

.

H/W

FIFO
Data In

CLKA

Do
\
D.

I

{write eye Ie)

CLKB
S 225

Qo

(x4)
UNLOAn.
eLK

Data Ou t

\

OE

(read eye Ie)

Q.

"-

:-l~ ------< LOAD

;~
5V

A
B

r

'.:l

UP

QD

OONE

(l.C

~INfIDL
REQ SET
<~~

HD6St50

DMAC

~
'"1
-....

latch

S

}

LS740

CK
R

~

~r

-Lr
RESEr

ACK
AS

REQ

-voo.

<1::::=

mUNT
DOM'I

C LS193
D
QA
Qa
Qc

R!W

f5V

.

LDS
UDS
ADDRESS
FCo-Fe 2

(b) Circuit Example Between the DMAC and FIFO

23

A

<,.

~+5V

IYI'ACK

~HV

AS

tV

LOS
UDS
AI-A.
Aa/Do-Au ID I5
Feo-Fe!

~__________~I~---------4~--~I~h£e~L~au'ut. ILra~n~'Ur.e.r
.
______~~

r:--=--=~f-----J..--_---"~_,.__------,J:=~=~=====:E
------~II~I--~----~~I~I------~/:

AS
Memory

LDS

Access

UDS

\

R/W

---~H~------~~~:====~r------~======j~
{~t
DTACK
,.
~l-I______---'I
'r-

Memory
Out

r ---'""'\

{

FIFO
Control

~I

ACK

r---\~

;~

DIC

REQ {cgWlER ------;;-f:llf---.:..:--------C-O-O)-H-I:;#"
Generator
REQ
CI~JHEQ:,
I
,

__________~!~,-

,"".

~
~

(a) Write (MEM-FIFO)

I~-------------,I :

AS
Memory
Access

LDS
UDS

---i~
Memory

Out
FIFO
Out
FIFO

co_::_:,

R/W

,

!

!

fData ---iJ.....:--_ _•
tOut

{~
--

:

--I~__________---'

~

(b) Read (FIFO-MEM)

FIGURE 3.12 Control Timing Chart of Figure 3.11 (b)

24

Do-D 7
' \ Do-D 7
'\.r--------------------------./ 6800

H

E

device

.----- CS

f-------

f--------------------..,/ dec
~--~

AS

RS

~--~

00-07 E

0 0 -0 7

6800

/

~-------------.---------.-v

C/l

;:3

~ ~ef---------------.----,/H ~ ~
AS ----..

m

I:Q

0

C/l
C/l

0

,...

QJ

0
0
00

'"0

""

~

device

'-----'

*+5V
L--*-------!--l---I--l AS

:m

~:=±:±--H ACK
~
+5~f
PCL~
,----+-----,1
~e-

PCL,

.----+-~=_<

o
o
o

00

""
Do-D,

r

M

~,

\

\

8D

81.;

~---~lD

r--

Do-D~
.,..

BUS

74LS373
CNT!.

Do-D"

D~~C
Do-D
Is o;,le!'t

V-"

~/5\

Do-D15/
A.-A'3

f--

DDIR

/ CKT

f------------------~
A.-A 23

DB EN

~

FIGURE 3.\3 6800 Device Application Example

25

LS 74

D~ type

LS 161

Synchronous 4-bi t Binary Counter

Posi tive Edge-Trigger F-F

~

~:~:eS8

,-----.,1-_'-----------'1
0----'
R

R

HD68A4S

T x RQ

i

-

LDS

nl

CS~~--------~--~)~------------~~----!-P!~
1_--+-,1...,-1':>0-.
~

H~;50

I--"

t--

I---"

HV

mID, ENABLE

V

-------....

r-

ti
t

FDC TxAKAr---

E

~

r6

~P'frJ--'VVY-+5V
HR~S74

l~CLR
L~16~~

~V

I

AC Ko ~ ~
PC Lo p..>--__--+____--l

'--------------

REQo~~-_===~,_-~------~

~~====tf-ri=~==V~~~~---------_r-------------l
UAS 1>----~k¢l>---I

PCL,

A,-A"

f-c AalDo-~~~~ 1-*lo~'----=~=-,ocl CO=~;Ol
c 'kt

"r

I-------,f:loc,--'-+-~----=-"'-----------

~
H
~

DDIR
ACK,

1------+.
10" -+--:-0-"0---=0-=,,'-------1 ~

'--_....

REQ,

I

Do-D,

0 -D

.-p-~-__l~,-<:1-'-a---..Fp_(R.f.r
to Fig 3. 6.) 0; ~

s --=--''---''--'-----1
DI--I--cc6-

p-t-

OE

REQ,
ACK,,..

R/wl--~~~--~

lv

E

r---

H~~~OO~LKI-~~+---LDS
__ ~
VPAb-~_+~-------+-+_---_+------V~P~A__I __ ~
VMA b-+-l-l--l------___+-___-+_______VL~"'IEA__t __ ~
~

~--+----------+---------A~2--t I--"
E

'--

CS ~~------4---~

Ro- R,I-+-f-______________---j---,rf-_ _-'A-:,c..-_A...:''--j I--"
I RQA [)-+-I----__I X ) - - - - - - -

-.6.

V

I RQ B

+5 V

2

11lAi'i, tNABLE

,..-;,~".......,

b-__l------I

C
LRj3LSlol
'lIL~

FIGURE 3.14 Circuit Example of HD68450,
HD68A43 (FDC) and HD68B21 (PIA)

26

2
c
o

()

VAS

+r

.........
,....

HD68450
7

DMAC

LSIH

60
50

BEC,

D,

4

BEC,

D,

3

BECo

Do

2

R&R
RETRY
BERR
HALT

1

Priority

00

Encoder
EI

C

FIGURE 3.15 Exception Encode Example

27

RESET

HD68000

MPU

CLR
4MHz ClK

CLR

A

A

LS393

lJA

Binary Counter

NC

LS393 QB
Qc 1---0-

QD

L..._ _....

QDI---0-

1

T6

OWN D------""""l
HD684:;O

DMAC
BEC,O----aD 2
BEC,

D1

BEC o

Do

FIGURE 3.16 Bus Cycle Time Out Error Example

28

+5V
Priori ty
Encoder

~

o LS148

I HQI

1

I

IlQ2

2

Do

IPL o

I HQ3

3

01

IPL I

I HQ 4

O2

IPL 2

I HQ.

4
5

I HQ6

6

I HQ7

7

HD68000
MPU

RES
INTERHUPT1
INTEHHUPT2

=vP-

~

Do

'~

P-->J

~riori

----k

,~ -

ty
Encoder
Il\:TEHHUPT3 -*

C

to---BEHH to-- '"
R&H

Do
01

4

O2

BEC o

I'"

BEC I
BEC 2
+5V

C 5

+5V

I

C 6

L---c

L----c CS
I - A7

C 3

Lo--- ,.,

LDS

OL8148
1
2

HALT

-

f

7

04
·Whe n INTERRUPT3 becomes "H"_ "L",
DMA transfer is stopped.
And the MPU is interrupted.

OWN
UAS

T

FIGURE 3.17 Transfer Stop Example

29

HD68450
DMAC

IHQ

+.v

G

AS
B
B

--a.J

..
I.

H068000
MPU

r--

~O

-~

t.

(PRIlIUTY our)

oom<:
(PRiORITY IN)

Q

~
~ PIUORrlY our

r--

'''LS3'18

--<0

'-I--- 0

Q

70183'18

'---

~

BR
BO

..

PRiiliii'i'\'1N •

AS

-0

'---

I~

Igj

~

lfil

H068 . . 0
OMAC

I~

I:
HOU . . O
OMAC

*This PRIORITY IN must be grounded.
**Open collector buffer.
FIGURE 3.18 Daisy Chain Example

1

~
SEL A,,-A 1
UPPER (ODD)

SEL Ao-A 1
LOWER (EVEN)

512kX8bi t

512kxHbi t

It

lr

Ds - DI5
Do -D7

upper byte. When an operand is transferred from the I/O device
to the lower byte of memory, HIBYTE signal must be used. See
Chapters 3.5 and 3.6 for circuit examples of HIBYTE.
Figure 3.19 shows an application example of the H D68450 in
the 8086 system, which requires the following circuits:
(I) CS, lACK GENERATOR .•. Read/Write control for
HD68450 internal
registers
(2) BUS ARBITER ............ 8086 bus arbitration
control
(3) STATUS GENERATOR ..... Control for form status
input to 8288 from
FCO-FC2
(4) RDY GENERATOR ........ Synchronizing 8086 and
HD68450 in internal register read / write cycles

8086

1

~
SEL A o-A2
UPPER (EVEN)

8MX8bi t

Ds- D I5

(I) CS, lACK GENERATOR
Figures 3.20 and 3.21 show a circuit example and timing chart
ofCSand l'i\'CK GENERATOR. CSand lACK are formed from
the 10RC, ATOWC, and INTA outputted from 8288. The
read/write cycle of the 8086 MPU to the HD68450 starts when
CS, LDS, UDS, and R/W become valid, and ends when both
LDS and UDS become inactive.
Since the H D68450 must output data to the lower byte of the
data bus, both lower bytes of 8086 and HD68450 need to be
directly connected, and the output from 8286 must be masked to
avoid bus conflict.

U

SEL Ao-A 22
LOWER (ODD)

8MX8bi t

IT

Do-D7

(2) BUS ARBITER
Figures 3.22 and 3.23 show the bus arbiter circuit and its timing
chart. As long as the HD68450 outputs BR or BGACK, bus
mastership is requested to the MPU, and bus conflict does not
take place. BR becomes inactive one clock after BGACK output,
and the bus request does not become inactive before the
HD68450 becomes bus master.

HD68450
The 8086 system allows one word operand whose upper and
lower bytes are located at both contiguous and diagonal position
in memory, as in the figure at the top of page 31. HD68450 does
not allow one word operand (see (2) in the figure). However, if the
operand size is programmed as a byte, and memory count is
programmed as increase in Dual Addressing Mode, the "diagonal" position can be supported by the HD68450.

(3) STATUS GENERATOR
Figures 3.24, 3.25 and 3.26 show the Status Generator circuit
and the DMA read/write cycle timing charts. This circuit generates status signals to inform the DMAC's bus ownership to 8288.
The H D68450 outputs VCO-FC2 in every bus cycle. These values
can be varied by writing different values into MFC, DFC, and

In addition to the Dual Addressing Mode (Chapter 3.1), the
HD68450 supports Single Addressing Mode, in which OP=P
must be satisfied. For one word operand in diagonal position (2),
OP=P=8 is required, and the I/O device must be connected to the

30

III

(2)

3

l~O

Z

3

2

5

4

5

4

l~O

The following examples show various data transfer between memory and I/O
device in Dual Addressing Mode.
Example 1

R-W
W-W
R-W
W-W
Example 2

® )
CIl )
CIl )

~I/O

( CD I]) )
(
CD )
(® CIl )
(I]) ® )
(

CIl

)

(P=16, OP=16, MTC=2)
1 word read from memory (I/O)
word write to I/O (memory)
word read from memory (I/O)
word write to I/O (memory)
(P=16, OP=8, MTC=4)
1 word read from I/O
1 byte write to memory
1 word read from I/O
1 word write to memory
1 byte wirte to memory

Mem
I I]) I

CD

CIl ®

Mem

I/O
1_ _ 1 ® I

CD

CIl ®

I

I/O

[§j~
® ~-CIl ®

~

Memory

R-B
R-B
W-W
R-B
W-B
R-B
W-B

I]) )

(CD
(CD
(®
( ®

Memory

R-W
W-B
Rr-W
W-W
W-B
Example 3

~I/O

Memory

I/O (P=8, OP=8, MTC=4)
)
1 byte read from I/O
)
1 byte read from I/O
)
1 word write to memory
)
1 byte read from I/O
)
1 byte write to memory
)
1 byte read from I/O
CIl
)
1 byte write to memory
CIl

( CD
( I])
( CD I])
(
®
(
®
(
(

31

Mem

I/O

II])ICDI
7
CIl ® - I CD

'V

0
CIlI

"..

HV

;~~~ ::

~

l'

RESET

ROY

S.

(j)

1
nK:o

-m
Ii
51

)

AMWTC

DT/Ii
AI.E

""

RDY

GEN.

~:

8US
~

~

~

II I
1111
~~===n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~5~
[,.Lll.d~±;;j·

-

""fNfi

MPU

A ,-A,

SYsTEMI

ROV

A,-Au

~=+====~t=~t====+~=+~==================:~

I-

LOCK

1¢~~~~~::;;:=ri=~~~~==~~~~==~~~==:::=:~~====~=======>D.-D"

+w

n: ,s

I\)

Ni

1i'i'AfK

fAi'"K

~r

RAVI
i'i'DS
Ws

IRQ

GRF.C.
ii"fT;fU:C,
HDB

~. ~

0

DMAC

~

__==------,II

ROO"
ACK.
REQ,
AC'K,

R:EQ;
ACk.

lffi'

FIGURE 3.19 Application Example of HD68450
in the 8086 System

+5V

~

DMAC SELECT

OWN

IORC

CS

R/W

AIOWC
INTA

(,)
(,)

BHE

Ao

lACK

+5[

LOCK

)

l:=k

~I'f
<

)

IRQ
,

Jj

LOS

HD684t50
DMAC
UDS

+5V
AS

FIGURE 3.20 CS and lACK Generator

Ti

~

CLK
lORC

T2

~

~

T3

TW

r~

TW

r

~

~

CS, lACK

,

.,

\

NOTE 1)

DTACK
RDY
ASYNC
ALE

I
I

I
I

I

I
I

I

I
I

I

i '.
Ii\

"

I

I
I
I

I
I

I

If

.,

I

"L"
I
I

-~

I

I

I
I
I
I

I
1
I

B
fl
'1 I

I

READ DATA

NOTE 2)1

I

FROM DMAC
I
I

WRITE tiATA TO DMAC

I

I

1
I

I
I
I
I
I

I

READY

I

1
35

1

1
I
I

NOTE I) Read and INTA cycles, consist of 13 clocks and write cycle consists of to clocks.
NOTE 2) DMAC Latches the data at a falling edge of this clock.
FIGURE 3.21 Timing Chart of Fig. 3.20

I
~~

T4

Ti

r "- r
I
I

I

60

TW

I

J'

LDS , ODS

.j>.

I

I

INTA

'"

~

I

AlOWC

R/W

TW

1:
-I

I

~j

\t:

k:~
I
I

\:
1

I

1
I

1
I

1
1

1

1

1

I

CLK

----------------------------------~

}---------- BG

'I4.S02

B
74.LS78

x)-~-I-IJ

Q

CJ1(

KCLRQ

R

74.LS04.

FIGURE 3.22 Bus Arbitration Circuit

CLK
BR

A
B

FIGURE 3.23 Bus Arbitration Timing

35

BFC (Memory Function Code register, Oevice Function Code
register and Base Function Code register). When the values in the
table are written in the registers, 8288 outputs bus commands
synchronizing with the OMAC's bus cycle, and the OMAC can
address devices on the 8086 system bus.
Figure 3.24 shows the shortest bus cycle, consisting of 5 clock
cycles. OSO-OS2 turn idle when the outputs from LS 191 are "3."
When access to memory or I/O device is not in time for the bus

0

0

0

0

interrupt acknowledge -------------- lNTA output
read I/O port ---------------------- 10RC output

0

0

0

1

(4) ROY GENERATOR
Figure 3.27 shows the ROY Generator circuit. See Figure 3.21
for the OMAC's ROY timing. In Figure 3.27, the STEM ROY
signal is used when the 8086 accesses devices other than the
H068450.

8086 STATUS

"IT Sf SO
0

cycle, it is possible to prolong the H068450 bus cycle by changing
the outputs of LS 191 to "4."

write I/O port --------------------- IOWC, AlOWC output
halt ------------------------------- None

0

0

code access ------------------------ MRDC output

0

1

read memory ------------------------ MRDC output

0

write memory ----------------------- MWTC, AMWTC output
idle ------------------------------- None

eLK

I

EJ
CK:

eLK
+5V

~

~

LSl91
LOAD

UfACK IN
(to Fig. 3 .27)

I

Q

~

--

UAS

I

l-

QA
Q8

t-

Qc

I-

Qo

tn

+5V

Q

6;,;

HD68450
D\lAC
Dt--

LS 74
Q

CK:
R

~

~
0

,
,

+5V
FC.
+5V
Fe,
+5V
Fe,

+5V ~
+5V ~
+5V~

FIGURE 3.24 Status Generator

36

'1'1

'1'1

CI.K(8Mllz)
UAS

~

r -

67

I";l
i

I

1.00

I

ALE

~NOTE

1.\

I

I

Olt

NOtE 2)

I

I
I
DT/R

DEN

I

d

I
I

i!!f

It

It.
I

~

I

I
I
I

I

I

I

~

I

I

I

I

I

I

I

I

HIlI'-

"

I

I

f1IIio1

I

I

I

I

~I

I

\.
I

~
I
I

tttti

-~I

a~cess.

Ifiq4

I

(DATA
memory

r--....

I

~\

I~

\1

J)

I

r'-DMAC
latches.

i'/

~

:

I
I

I

-.l

t

I
I

I
I
I

IN N0TJ94) I

mlll. 92 ns

I

I

~

I

'1

I

I

I'

I

'\ i!l,INOTE
I
I

I

f-it-ll

I

I

\

I
I

II

I

I

I

I

I

I
I

I

I

~

t

NOTE 4)

I/O latch

I

/

f\-

I
I
I

:'I
I

I

I
I

I

J.

I
I
I

I
I

t-

X

I

I

J

II

I

I
I

I
I

I

I

!

\

I

I
I

)'

r

"I

I

I

I
I
I

I
I

I

T2

1'1

T'

I

I
I

I

I

II

I

'1'1

I
XI

i

II

I

~

I

I

\

I

~NOTEJ)
I

I

I

'1'4-

~

I

'~
I \

'rw

I

I

I)

I
I
I
I

'1':1

JU
I

I
I
I

I

.;\

FC.-FC z
DSz,DS"DS.

J

r ~:-----r}; -r
'1'2

'1'1

I
I
I

I
I
I
I

I
I

timing

NOTE I) OS2, OSI and OSOcorrespond to Si, Si, and SOin the 8086 system, and are from FCO-FC20fthe DMAC. When the OMACis
used, each bus cycle needs one idle state (T1), and the basic bus cycle consists of five clock cycles.
NOTE 2) OWN and UAS of the OMAC are used, and ALE of the 8288 is not used to latch address AI-A23.
__
NOTE 3) 15S2, IJS1, and DSli are used to terminate the 8288 cycle, and OTACK is used to terminate the DMAC.
NOTE 4) Oata latch in Dual Addressing Mode, and from I/O device in Single Addressing Mode is with the falling edge of OTC.
FIGURE 3.25 H068450 READ Cycle Timing Chart

37

Tl
CLK(8MHz)

-T'
I

UAS

FC o - FC 2
,

DS, , DS o

LDS, UDS

I

I

I

L

I

I

L
I

I
I

I
I
I

L

\



device address
table top address

transfer
counts C

block C

-

memor y
addre ss

}

transfer
counts A

block A

A

BAR
MTC
*
BTC number of blocks

being transferred

memor y
addre ss

transfer
counts B

B

*

block B

loaded from the array table

--

devic e
addre ss

--

I/O device
or
memory

-FIGURE 4.4 Transfer Example in Array Chaining Mode

46

-

memory

Bit 1.5.
linked address

linked array table_

X....

linked address Y

memory address B(H)
memory address B(L)
transfer counts B
linked address Y(H)
linked address Y(L)

....

table top address;

~ o

memory address C(H)
memory address C(L)
trans er counts (;
"All 0" (terminator)

....

memory address A(H)
memory address A(~).
transfer counts A
linked address X(H)
linked address Y(L)
I.--

HD68450
DMAC
memory
address C

HD68000

MAR

MPU

DAR device address

:::!>

*

BAR table top address
MTC
BTC

*

t ransfer
c ounts C

block C

~

~

~
memory
address A

(not used)

memory
address B

*

-- ---

loaded from
array table

--

-

block A

transfer
counts A

block B

transfer
counts B

i.-'

devi ce
,.,.address -__.}-------------------4
I/O device
or memory

-

FIGURE 4.5 Linked Array Chaining Mode Transfer Examples

47

---

Example 4: Program Example in Linked Array Chaining Mode
(corresponding to Fig. 4.5)

line number
1
LINKA EQU
2
MOVE. W
3
MOVE. B
4
MOVE. B
5
MOVE. B
6
MOVE. B
7
MOVE. B
8
CLR, B
MOVE. B
9
10
MOVE. L
MOVE. B
11
RTS
12

(NOTE).
•
•
•

comment

*II$A89E,

setting OCR, nCR
setting SCR
setting NIV
II $80, $1025
setting EIV
11$81, $1027
setting MEC
11$01, $1029
setting BFC
11$01, $1039
$10lD
setting CPR
T'esetting CSR
II $FF, $1000
IItable top address, $101C setting BAR
setting STR bit
11$80, $1007
returning to
main routine
$1004

11$04, $1006

Setting Transfer
Mode

The DMAC is mapped onto address from $1000 through $IOFF.
Channel 0 is used.
The same modes are set as those in example I except Linked Array Chaining Mode
In Dual Addressing Mode, DAR and DFC should be set.

48

DATA
SHEETS

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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I

HD68450,HD68450Y
DMAC (Direct Memory Access Controller)
APRIL 1984
Microprocessor implemented systems are becoming increasingly complex, particularly with the advent of high-performance
l6-bit MPU devices with large memory addressing capability. In
order to maintain high throughput, large blocks of data must be
moved within these systems in a quick, efficient manner with
minimum intervention by the MPU itself.
The HD684S0 Direct Memory Access Controller (DMAC)
is designed specifically to complement the performance and
architectural capabilities of the HD68000 MPU by providing the
following features:
•
•
•
•
•
•
•
•
•
•
•
•

-The specifications for HD68450-10 and HD68450V10 are
preliminary.-

HD68450-4, HD68450-6,
HD68450-8, HD68450-10,

HMCS68000 Bus Compatible
4 independent DMA Channels
Memory-to-Memory, Memory-to-Device, Device·to-Memory
Transfers
MMU Compatible
Array-Chained and Linked-Array-Chained Operations
On·Chip Registers that allow Complete Software Control by
the System MPU
Interface Lines for Requesting, Acknowledging, and
Incidental Control of the Peripheral Devices
Variable System Bus Bandwidth Utilization
Programmable Channel Prioritization
2 Vectored interrupts for each Channel
Auto-Request and External-Request Transfer Modes
+5 Volt Operation

(DC-64)
HD68450Y4, HD68450Y6,
HD68450Y8,
HD68450Yl0,

"y" stands for Pin Grid
Arrav Package.

(PGA-68)

The DMAC functions by transferring a series of operands
(data) between memory and peripheral device; operand sizes can
be byte, word, or long word. A block is a sequence of operations; the number of operands in a block is determined by a
transfer count. A single-channel operation may involve the
transfer of several blocks of data bctween memory and devicc.

• PROGRAMMING MODEL

Status Regl5ler
Error Reglsle.
ConlfolReglS\e,
Operallon
Control RegIster

• TYPE OF PRODUCTS

Sequence
Control Regl&ter

Type No.

Bus Timing

HD68450-4

4MHz

HD68450-6

6MHz

HD68450-8

8M Hz

HD68450-10

10MHz

HD68450Y4

4MHz

HD68450Y6

6MHz

HD68450Y8

8MHz

HD68450Yl0

10MHz

Channel

Packaging
ConlrOIReglsrer

Control RegIster

I} One Per DMAC

Normal

Interrupt Vector
Error

Interrupt Vector
4 Sets
\--..:.:.:.::.:,c:::.,,:.:.,....==---H (One Set Per

Priority Register

DC·64

Memory

Function Codes
functIon Codes

I"

I

PGA·68

Memory

Memory Address Rag,ster
DtlVlCI! Address RegISter

Base Address flaglster

51

Tr~nsfer

Counter

Base Transler Counler

Channel)

HD68450,HD68450Y--------------------------------------------------------------------•
•

PACKAGING INFORMATION (Dimensions in mm)
DC-64 (SiDE-BRAZED CERAMIC DIP)

•

PGA-68 (PIN GRID ARRAY PACKAGE)

f-o--------,@

211.2-----_____..0

..

"1-_ _ _+""'-.1.
2256-

020-03B

•
•

PIN ARRANGEMENT
HD68450

•

HD68450Y

oolR
oBEN
HIBYTE
, UAS

OWN
BR

lfG
A,

5

A,
A,
A.
As

5

, A.
51

Vee
A,

Vss

A.ID.
A,ID,
A,.ID,

(Bottom View)

AIIID,

A"/o.
A"/D,

A,.ID.

1 AI"s/D7

A.. /O.
A"/O,
3
37

Au/DIO
Au/Oll

A,./o"
A" 10"

Fe, 31

,

A" 10,.

FC._'......_ _ _ _ _ _.....r- A"/0 15
(Top View)

52

---------------------------------------------------------------------HD68450,HD68450Y
•

ABSOLUTE MAXIMUM RATINGS
Item

.
.

Symbol

Value

Unit

Supply Voltage

Vee

-0.3-+7.0

V

I nput Voltage

V in

-0.3 - +7.0

Operating Temperature Range

Topr

0-+70

V
DC

Storage Temperature

T stg

-55 - +150

DC

• With respect to Vss (SYSTEM GNO)
(NOTE)

Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions.

If these conditions are exceeded, it could affect reliability of LSI.
•

RECOMMENDED OPERATING CONDITIONS
Item
Supply Voltage
I nput Voltage

Symbol

min

typ

max

Vee
V IH

4.75

5.0

5.25

V

2.0

Vee
0.8

V

-0.3

-

0

25

70

V IL

Operating Temperature

Topr

··
·

Unit

V
DC

• With respect to Vss (SYSTEM GNO)

•
•

ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee = 5V ±5%, Vss = OV, Ta = O-+70DC, unless otherwise noted.)
min

typ

max

Unit

Input "High" Voltage

V IH

2.0

V IL

Vss-0.3

Vee
0.8

V

Input "low" Voltage

-

Item

Symbol

Test Condition

V

~

Input leakage Current

lACK, BG, ClK,
BECo - BEC 2
REQo- REQ 3

lin

-

-

10

Il A

Three-5tate (Off State)
I nput Current

AI -A 7 , Do -Dis/As -A 23 ,
AS, UDS, lDS, R!W, UAS,
DTACK, BGACK, OWN, DTC,
HIBYTE, DDIR, DBEN,
FCo -FC 2

I TSI

-

-

10

IlA

Open Drain (Off State)
I nput Current

IREQ, DONE

1001

-

-

20

IlA

AI - A 7 , Do - Dis/As - A 23 ,
lDS, R!W. UAS,
DTACK, BGACK, BR, OWN,
DTC, HIBYTE, DDIR, DBEN,
ACKo - ACK 3 , PClo - PCl 3 ,
FC o -FC 2

V OH

10H = -4001lA

2.4

-

-

V

AI - A 7 , FCo - FC 2

VOL

10L = 3.2mA

-

-

0.5

Do - Dis/As - A 23 , AS, UDS,
lOS, R/W,DTACK, B~
OWN, DTC, HIBYTE, DDIR,
DBEN, ACKo - ACK 3 , UAS,
PClo - PCl 3 , BGACK

VOL

10L =5.3mA

-

-

0.5

IRQ, DONE

VOL

10L =8.9mA

-

-

0.5

-

1.4

2.0

W

-

-

15

pF

AS, (J[)S",
Output "High" Voltage

Output "low" Voltage

Power Dissipation

Po

Capacitance

Cin

53

f = 8 MHz,Vee =5.0 V
Ta = 25°C
Vin=OV,
Ta = 25DC, f = 1 MHz

V

HD68450.HD68450Y----------------------------------------------------~-------------

Test

LOAD A

LOAD B

LOAD C

+5V

+5V

+5V

15000

~

r

1.11kQ

Test
Point

7100

130pF
152074

---<

)

AI .... A 7

XDo - XDI5

GAS

AS

'---J
\
-..I

x::
>-

(

'---l
I
\

'L

r-

UDS
lDS
R/W

OWN

low

HIBYTE
DTACK
(lOry

/Joz)

PCL(READY)
DTC

®

ACKo
ACK,
ClK
1

2

3

4

5

6

7

8

9

10

1

2

3

4

5

6

7

8

9

Figure 7 AC Electrical Waveforms - OMA Read/Write (Single Cycle with PCl)

59

10

11

12 13

14

HD68450,HD68450Y------------------------------------------------------------------

ClK
AI -A 7
XD. - XDI5
UAS

As
UDS
lOS
R!W
OWN
HIBYTE

low
High

(0)

DTACK
DONE IN
ACK.
ACK I

DTC
ClK

3

4

5

6

2

8

3

4

5

6

7

8

9

10

• If #6 is satisfied for both DTACK and DONE, #103 may be Ons.

Figure 8 AC Electrical Waveforms - DONE Input
(NOTES for Figure 3 through 8)
1) Setup time for the asynchronous inputs BG, BGACK, CS, lACK, AS, UDS, lOS, and RNi guarantees their recognition at the next
falling edge of the clock. Setup time for BEC. - BEC" REO. - REO" PCl. - PCL." lITACK, and IX5l\IE guarantees their
recognition at the next rising edge of the clock.
2) Timing measurements are referenced to and from a low voltage of O.B volts and a high voltage of 2.0 volts.
3) These waveforms should only be referenced in regard to the edge-to-edge measurement of the timing specifications. They are not
intended as a functional description of the input and output signals. Refer to other functional descriptions and their related diagrams
for device operation.

60

------------------------------------------------------------------HD68450,HD68450Y

•

• SIGNAL DESCRIPTION

The following section identifies the signals used in the
DMAC. In the definitions, "MPU mode" refers to the state
when the DMAC is chip selected by MPU. The term "DMA
mode" refers to the state when the DMACassumes ownership of
the bus. The DMAC is in the "IDLE mode" at all other times.
Moreover, the DMA bus cycle refers to the bus cycle that is
executed by the DMAC in the "DMA mode".
NOTE) In this data sheet, the state of the signals is
described with these words: active or assert, inactive
or negate.
This is done to avoid confusion when dealing with a mixture
of "active-low" and "active-high" signals. The term assert or
assertion is used to indicate that a signal is active or true independent of whether that voltage is low or high. The term negate
or negation is used to indicate that a signal is inactive or false.

Input/Output
Active-high

<:;=:::::::>1

A,-A7

'-r---.""

•

Three-statable

These output signals provide the function codes during
DMA bus cycles. They are three-stated except in the DMA bus
cycles. They are used to control the HMCS68000 memories.
Clock (ClK)

Input
This is the input clock to the HD68450, and should never be
terminated at any time. This clock can be different from the
MPU clock since HD68450 operates completely asynchronously.
•

DTACK---~

BR-----I

irn-----I

Function Code (FC o through FC 2 )

Output
Active-high

cs---~
AS-----i
Ii5S-----i
UDS-----i
RIW-----i

BGACK-----i

Three-statable

In the MPU mode, the DMAC internal registers are accessed
with these lines and LDS, UDS. The address map for these
registers is shown in Table I. During a DMA bus cycle, Al -A7
are outputs containing the low order address bits of the location
being accessed.

•
As-A23!
00-0,.

Address Bus (AI through A7)

Input
Active low

RE02

HD68450
DMAC

TRQ------1

ACi<2
PCL2

This input signal is used to chip select the DMAC in "MPU"
mode. If the CS input is asserted during a bus cycle which is
generated by the DMAC, the DMAC internally terminates the
bus cycle and signals an address error. This function protects
the DMAC from accessing its own register.

RE03
ACK3
PCL3

~-----I

Chip Select (CS)

OWNi-----I

"liAS------1
HI BYTE------1
Dmf

•

DDIR:-----I

Address Strobe (AS)

Input/Output
Active low

BECo-----i
BEG,-----!
BEC2'-----!

Three-statable

In the "MPU mode," this line is an input indicating valid
address input, and during the DMA bus cycle it is an output
indicating a valid address output from the DMAC on the address
bus.
The DMAC monitors these input lines during bus arbitration
to determine the completion of the bus cycle by the MPU or
other bus masters.

FCo------1
FC,-----I
FC2-----I

Vss(2)

Figure 9 I nput and Output Signals
•
•

Output
Active low

Address/Data Bus (As/Do through An/DIs)

Input/Output
Active-high

Upper Address Strobe (UAS)

Three-statable

Three-statable
This line is an output to latch the upper address lines on the
multiplexed data/address lines. It is three-stated except in the
"DMAmode".

These lines are time multiplexed for the address and data
bus. The lines DDIR, DBEN, VAS and OWN are used to control the demultiplexing of the data and address lines externally.
Demultiplexing is explained in a later section. The bi-directional
data bus is used to transfer data between DMAC, MPU,
memory and I/O devices.
Address lines are outputs to address memory and I/O devices.

•

Own (OWN)

Output
Active low

61

Three-statable

HD68450,HD68450Y------------------------------------------------------------------This line is asserted by the DMAC during DMA mode, and is
used to control the output of the address line latch. This line
may also be used to control the direction of bi-directional
buffers when loads on AS, LDS, UDS, R/W and other signals
exceed the drive capability. It is three-stated in the "MPU
mode" and the "IDLE mode"
•

Data Direction (DDfR)
Outputs
Three-statable
Active low (when data direction is input to
theDMAC)
Active high (when the data direction is output
from the DMAC)

In the "MPU mode", this line is an output indicating the
completion of Read/Write bus cycle by the MPU.
In the "DMA mode", the DMAC monitors this line to determine when a data transfer has completed. In the event that a
bus exception is requested, except for HALT, prior to or concurrent with DTACK, the DTACK response is ignored and the
bus exception is honored. In the "IDLE mode", this signal is
three-stated.
• Bus Exception Controls

(BECo through BEC;')

Input
Active low
These lines provide an encoded signal input.indicating an
exceptional condition in the DMA bus cycle. See bus exception
section for details.

This line controls the direction of data through the bidirectional buffer which used to demultiplex the data/address lines.
It is three-stated during the "IDLE mode"

• Bus Request (SR)
• Data Bus Enable (DBEiii)
Output
Active low

Output
Active low

Three-statable

This line controls the output enable line of bidirectional
buffers on the multiplexed data/address lines. It is a three-stated
during the "IDLE mode".

This output line is used to request ownership of the bus by
the DMAC.
• Bus Grant (00)
Input
Active low

• High Byte (HlBY'fE)
Output
Active low

Three-statable

This line is used when the operand size is a byte in the single
addressing mode. It is asserted when data is present on the upper
eight bits of the data bus. It is used to control the output of the
bidirectional buffers which connect the upper eight bits of the
data bus with the lower eight bits. It is three-stated during the
"MPU mode" and the "IDLE mode."
•

This line is used to indicate to the DMAC that it is to be the
next bus master. The DMAC cannot assume bus ownership until
both AS and BGACK becomes inactive. Once the DMAC acquires the bus, it does not continue to monitor the BG input.
• Bus Grant Acknowledge (BGACi<)
Input/Output
Active low

Three-statable

Read/Write (R/W)

This line is an input in the "MPU mode" and an output
during the "DMA mode". It is three-stated during the "IDLE
mode". It is used to control the direction of data flow.

Bus Grant Acknowledge (BGACK) is a bidirectional control
line. As an output, it is generated by the DMAC to indicate that
it is the bus master.
As an input, BGACK is monitored by the DMAC, in limited
rate auto-request mode, to determine whether or not the
current bus master is a DMA device or not. BGACK is also
monitored during bus arbitration in order to assume bus ownership.

• Upper Data Strobe (UDS). Lower Data Strobe (LOS)

• Interrupt Request (iRa)

Input/Output
Active low (write)
Active high (read)

Input/Output
Active low

Three-statable

Three-statable

Output
Active low

This line is used to request an interrupt to the MPU.

These lines are extensions of the address lines indicating
which byte or bytes of data of the addressed word are being
addressed. These lines combined corresponds to address line
Ao in table 1.
•

• Interrupt Acknowledge (lACK)
Input
Active low

Data Transfer Acknowledge (Dl'ACi<)
In pu t/ Ou tpu t
Active low

Open drain

Three-statable

This line is an input to the DMAC indicating that the current
bus cycle is an interrupt acknowledge cycle by the MPU. The

62

---------------------------------------------------------------------HD68450,HD68450Y
DMAC responds the interrupt vector of the channel with the
highest priority requesting an interrupt. There are two kinds of
the interrupt vectors for each channel: normal (NIV) or error
(EIV). lACK is not serviced if the DMAC has not generated
IRQ.
• Channel Request

St8~a=_

(CSR)
(CER)
(OCR)
Control RlIgislfl
co~:r=':st.r (OCR)
con=-~~r (SCR)
con~::r~_r (CCR)
Interru~~vector (NIV)
Channel
Error RegIIII1'
Device

(RE"Clo through FfE})

------«(

»)

DTACK

\\\

or

Figure 11 MPU Read from DMAC - Word

66

,,.--

------------------------------------------------------------------H068450,H068450Y

Al-A23
FCo-FC2
AS

m

CS
R/W

m

HI
/Il

~

\X\
~

~

UOS

m

LOS

\S~

OOIR

,-u_,

OBEN

,.-----

XOO-X015
(External System Data Bus)

\n

,1/

,~~

r-

III'

-----«(
C---

As/Oo-A23/015

01

i5'fACj(

»)

«C

>>>
\"

fl{'

Figure 12 MPU Write to OMAC - Word
•

Bus Arbitration

(AS is negated), the MPU relinquishes the bus to the DMAC.
The DMAC asserts the bus grant acknowledge (BGACK) to
indicate that it has the bus ownership. A half clock before
BGACK is asserted, the DMAC asserts OWN. OWN is kept
asserted for a half clock after BGACK is negated at the end of the
DMA cycle. BR is negated one clock after BUACK is asserted.

The DMAC must obtain ownership of the bus in order to transfer
data. Figure 13 indicates the DMAC bus arbitration timing. It is
completely compatible with that of HD68000 MPU. The DMAC
asserts the Bus Request (BR) to request the bus mastership. The
MPU recognizes the request and asserts BG, then it grants the
ownership in the next bus cycle. After the end of the current cycle
ClK

----.

¥

1.5 - 3.5 clocks
10---

.,

I

2-3.5 clocks'
I

Sci
(68000 output)
\

OWN

1rnm
BUS Cycle

ACK

o clock -

I~

1MPU Cycle

MPU Cycle

4.5 - 5.5 clocks

max. 12.5 clocks + lMPU Cycle

ClK

• This case assumes that no exception condition exists and DMAC isn't accessed by MPU.
Figure 13 OMAC Bus Arbitration Timing

67

~ycIe
U

\ DMA Cycl.

HD68450,HD68450Y------------------------------------------------------------------device of the last data block. In the continue mode, DONE is
asserted for each data block. It is asserted and negated in coincident with the ACK line for the last data transfer to the
peripheral device. It is also outputted in coincident with the
ACK line of the last bus cycle, in which the address is outputted
from the DAR, in the memory-to-memory transfer (dual
addressing mode) that uses the ACK line.
The DMAC also monitors the state of the DONE line during
the DMA bus cycle. If the device asserts DONE during ACK
active, the DMAC will terminate the operation after the transfer
of the current operand. If DONE is asserted on the first byte of
2 byte operation or the first word of long word operation. the
DMAC does not terminate the operation until the whole operand transfer is completed. If DONE is inserted. then the DMAC
terminates the operation by clearing the ACT bit of the CSR,
and setting the COC and NDT bits of the CSR. If both the
DMAC and the device assert DONE, the device termination is
not recognized, but the channel operation does terminate.
DONE is outputted again for the retry exceptions bus cycles.
(5) Data Transfer Complete (DTC)
DTC is an active low signal which is asserted when the actual
data transfer is accomplished. It is also asserted in the bus cycle
when a chain information is read from memory in the Chaining
mode. However, if exceptions are generated and the DMA bus
cycle terminates, DTC is not asserted. DTC is asserted one half
clock before LDS and UDS are negated, and negated one half
clock after LDS and UDS are negated.

• Device/DMAC Communication
Communication between peripheral devices and the DMAC is
accomodatedby five signal lines. Each channel has REQ, ACK
and PCL, and the last two lines the DONE and DTC lines, are
shared among the four channels.
(1) Request (REQ)
The peripheral devices assert REQ to request data transfers.
See the "Requests" section for details.
(2) Acknowledge (ACK)
This line is used to implicitly address the device which is
transferring the data (This device is not selected by address
lines.) It is also asserted when the content of DAR is outputted during memory-to-memory transfer except for the autorequest mode at a limited rate or at the maximum rate.
(3) Peripheral Control Line (PCl)
The function of this line is quite flexible and is determined
by the OCR (Device Control Register).
The DlYP bits of the OCR define what type of device
is on the channel. If the DTYP bits are programmed to be a
HMCS6800 device, the PCL definition is ignored and the PCL
line is an Enable clock (E clock) input. If the DlYP bits are programmed to be a device with READY, the PCL definition as
ignored and the PCL line is a ready input.
PCl As a Status Input
The PCL line may be programmed as a status input. The
status level of this line can be determined by the PCS bit in the
CSR, regardless of the PCL function determined by the OCR.
If a negative transition occurs and remains stable for a minimum of two clocks, the PCT bit of the CSR is set. This PCT
bit is cleared by resetting the DMAC or the writing" I" to the
PCTbit.
PCl As an InterNpt
The PeL line may be programmed to generate an interrupt
on a negative transition. This enables an interrupt which is requested if the PeT bit of the" CSR is set. When using this function, it is necessary to reset the PCT bit in the CSR before the
PCL bit in the DCR is set to interrupt, in order to avoid
assertion ofIRQ line at this time.
PCl As a Starting Pulse
The PCL line may be progranuned to output a starting pulse.
This active low starting pulse is outputted when a channel is
activated. and is "Low" for a period of four clock cycles.
PCl As an Abort Input
The PeL line may be programmed to be a negative transition
above input which terminates an operation by setting the external abort error in CER. It is necessary to reset the PeT bit in
the CSR before activating the channel (Setting the ACT bit of
CCR) so that the channel operation is not immediately aborted.
PCl As an Enable Clock (E Clock) Input
If the DTYP bits are programmed to be a HMCS6800 device,
the PeL definition is ignored and the PCL line is an Enable
Clock input. The Enable clock downtime must be as long as five
clock cycles, and must be high for a minimum of three DMAC
clock cycles, but need not be synchronous with the DMAC's
clock.
PCl As a READY Input
If the DTYP bits are programmed to be a device with
READY, the PeL defmition is ignored and the PeL line is a
READY input. The READY is an active low input.

• Requests
Requests may be externally generated by circuitry in the
peripheral device, or internally generated by the auto-request
mechanism. The REQG bits of the OCR determine these modes.
The DMAC also supports an operation in which the DMAC
auto-requests the first transfer and then waits for the peripheral
device to request the following transfers.
(1) Auto-request Transfers
The auto-request mechanism provides generation of requests
within the DMAC. These requests can be generated at either of
two rates: maximum-rate and limited-rate. In the former case,
the channel always has a request pending.
The limited rate auto-request functions by monitoring the
bus utilization.
limited-rate Auto-request
TIME-+
Previous

Sample Interval

Next
Sample Interval

Figure 14 DMAC Sample Intervals
In the Iimited-rate auto-request the DMAC devides time into
equal length sample intervals by counting clock cycles. The end
of one sample interval makes the beginning of the next. DUring
a sample interval, the DMAC monitors by means of BGACK pin
the system bus activity of the DMAC and other bus master
devices. At the end of the sample interval, decision is made
whether or not to perform the channel's data transfer during
the next sample interval. Namely, based on the activity of
the DMAC or other bus master devices during the current
sample interval, the DMAC allows limited-rate auto-requests for
some initial portion of the next sample interval.
The length of the sample interval, and the portion of the
sample interval during which limited·rate auto·requests can be

(4) DONE (DONE)

This line is an active low Input/Output signal with an open
drain. It is asserted when the memo~y transfer couilt is exhausted in a single block transfer. In the chaining operation,
DONE" is asserted only at the last transfer to the peripheral

68

---------------------------------------------------------------------HD68450.HD68450Y
clock cycles.
The DMAC uses the BGACK to differentiate between the
MPU bus cycle and DMAC or other bus master devices. If
BGACK is active, then the DMAC assumes that the bus is used
by a DMAC or other bus master devices. If it is inactive, then
the DMAC assumes that it is used by the MPU.
Maximum-rate Auto-request
If the REQG bits in the OCR indicate auto-request at the
maximum rate, the DMAC acquires the bus after the start bit is
set and keeps it until the data transfer is completed.
If a request is made by another channel of higher priority,
the DMAC services that channel and then resumes the autorequest sequence. If two or more channels are set to equal
priority level and maximum rate auto-request, then the channels
will rotate in a "round robbin" fashion.
If the HMCS68000 compatible device is connected to a
channel, the ACK line is held inactive during an auto-request
operation. Consequently, any channel may be used for the
memory-to-memory transfer with the auto-request function in
addition to the operation of data transfer between memory and
peripheral device with using the REQ pin. Refer to Figure 15
for the timing of the memory-to-memory transfer. In this mode,
the ACK, HIBYTE and DONE outputs are always inactive.

made (the limited-rate auto-request interval) are controlled by
the BT and BR bits in the GCR. The length in clock cycles of
the limited-rate auto-request interval is 2(BT+4) (2 raised to the
BT+4 power). For example, if BT equals 2 and the DMA utilization of the bus was low' during the previous sample interval,
then the DMAC generates the auto-request transfers during the
first 64 clock cycles.
The ratio of the length of the sample interval to the length
of the limited-rate auto-request interval is controlled by the BR
bits. The ratio of the system bus utilization of the MPU to
other bus master devices including he DMAC is 2(BR+ I) (2
raised to the BR+ I power). If the fraction of DMA clock cycles
during the sample interval exceeds the programmed utilization
level, the DMAC will not allow limited-rate auto-requests during
the next sample interval.
For example, if BR equals 3, then at most one out of 16
clock cycles during a sample interval can be used by the DMAC
and other bus master devices, and still the DMAC would allow
limited rate auto-request during the next sample interval.
Therefore, from the viewpoint of long period, the ratio of the
system bus utilization of the MPU to I/O devices including the
DMAC is about 16: I. The sample interval length is not a direct
parameter, but it is equal to 2(BT+BR+5) clock cycles. Thus,
the sample interval can be programmed between 32 and 2048

ClK
1 2 3

9 1011121314151617181920212223242526272829

XIII

FCo-FC2-=:JJ//

A'-A7::u~"__________~u~n~
A8/DO_~d:ess Out

Data In

VII

A23/D,s..J//

XDo- XD,slIllIID--<1O

______________

Address Out

Data Out

ill

\\\

__________

ill-.llI

m

\\\

\\\

01

\\\
\\\
\\\

OJ

..111

\\\

ULJJJ
ACK
ClK
8 9 10
Read One Word
From Memory

I

Write One Word
to Memory

Figure 15 Memory-to-Memory Transfer
Read-Write-Read Cycles

69

~
~~

/mrr-

AdDress Out rrn _;;;.D;;.;at.;;.a,;.;ln;""'/T7

XIII
wI
'lJt1
YIIl
Oml';------~

m

"HD68450,HD68450Y----------------------------------------------------_______________
(2) External Requests

following is the description of the burst and the cycle steal
modes.
Bu rst Request Recognition
In the burst request mode, the REO line is an active low
input. The level sampled at the rising edge of the clock. Once
the burst request is asserted, it needs to be hel,d low until the
first DMA bus cycle starts in order to insure at least one data
transfer operation. In order to stop the burst mode transfer
after the current bu~le, the REQ line has to be negated
one clock before the DTC output clock of this cycle. Refer to
Figure 16 or the burst mode timing.

If the REOG bits of the OCR indicate that the REO line
generates requests, the transfer requests are generated externally. The request line associated with each channel allows the
device to externally generate requests for DMA transfers. When
the device wants an operand transferred, it makes a request by
asserting the request line. The external request mode is determined by the XRM bits of the OCR, which allows both burst
and cycle steal request modes. The burst request mode allows a
channel to request the transfer of mUltiple operands using
consecutive bus cycles. The cycle steal request mode allows
a channel to request the transfer of a single operand. The

MPU cycle

-+--

Idle

--t-

DMA cycle

-+

MPU cycle
or Idle

--r- DMA cycle -r- Idle

Figure 16 Burst Mode Request Timing
(Only one channel is active)
Cycle Steal Request Recognition
In the cycle steal request mode, the peripheral device requests the DMA transfer by generating an falling edge at the
REO line. 111e REO line needs to be held "low" for at least 2
clock cycles. In the cycle steal mode, if the REO line changes
from "Higll" to "Low" between ACK output and one clock before the clock that outputs DTC, then the next DMA transfer
is performed without relinquishing the bus. If the bus is not
relinquished, then maximum of 5 idle clocks is inserted between
bus cycles. Refer to Figure 17 for the request timing of the
cycle steal mode. If the XRM bits specify cycle steal without hold, the DMAC will relinquish the bus. If the XRM bits
specify cycle steal with hold, the DMAC will retain ownership.
The bus is not given up for arbitration until the channel opera-

ClK

:

tion terminates or until the device pauses. The device is determined to have paused if it does not make any requests during
the next full sample interval. The sample interval counter is free
running and is not reset or modified by this mode of operation.
The sample interval counter is the same counter that is uSed for
Limited Rate Auto Request and is programmed via the GCR.
Figure 18 shows the request timing in the cycle steal bus
hold. If the REO is inputted during the hold tinle, the ACK
is outputted after a maximum of 7.5 clock cycles from the
picked-up clock. On the cycle steal with hold mode, the DMAC
will hold the bus even when the transfer count is exhausted and
the last data has been transferred. If DMA transfer is requested
from other channels during this period, they are executed
normally.

JUlfl.fLJ1JUlfLJUU1JlIltlJUUUlJ

REQ~:
BR
\
BG
BGACK

\

:
: :

~~~lES

:

ACK

0

>"

LC:

I ~bUS

I

~

'--=F

,,_;:~-_~====~

rna:. 5 clocks

~s-(
""41
\
~J

DrC

f1..Il..IlJ1JlJ
r\R9IinqUishth9bU:. ___ ----1 LJ
j"\
,,--uu

>--C:)-"---<---!:=n-~}-0-----

Idle

DMAcycle

MPU cycle
or Idle

Figure 17 Cycle Steal Mode Request Timing

70

,,---

U-

I11lIlI1IUUlI

micro cleanup

-+-

\\

U

ClK
MPU cycle

__

.~

--r----

DMA cycle

------------------------------------------------------------------HD68450,HD68450Y

CLKJ1IL
REO'----I
BR--,
BG---

___

_'-,----I-----J
----"

BGACK

',-.

---------11-----\

BUS
CYCLES

-_---J

max. 5 clocks

( } - - !f~

ij"
II

ACK

}--

~I~~==~~-~--~~~U-­
\L1J
'U....IJ

DTC-------~f~J

Figure 18 Cycle Steal Bus Hold Mode Request Timing
Request Recognition in Dual-address Transfers

(1) Dual Addressing

In the following section dual-address transfers is defined.
Dual address transfer is an exception to the request recognition
rules in the previous paragraphs. In the cycle steal request mode,
when there are two or more than transfers between the DMAC
and the peripheral device during one operand transfer, the request is not recognized until the last transfer between the
DMAC and the I/O device starts.

HMCS68000 and HMCS6800 compatible devices may be
explicitly addressed. This means that before the peripheral
transfers data, a data register within the device must be addressed. Because the address bus is used to address the peripheral,
the data cannot be directly transferred to/from the memory
because the memory also requires addlessing. Instead, the data
is transferred from the source to the DMAC and held in an
internal DMAC holding register. A second bus transfer between
the DMAC and the destination is then required to complete
the operation. Because both the source and destination of the
transfer are explicitly addressed, this protocol is called dualaddressed.

(3) Mixed Request Generation

A single channel can mix the two request generation
methods. By programming the REQG bits of the OCR to "II ",
when the channel is started, the DMAC auto-requests the first
transfer. Subsequent requests are then generated externally by
the device. The ACK and PCL lines perform their normal functions in this operation.
•

HMCS68000 Compatible Device Transfers

In this operation, when a request is received, the bus 'is
obtained and the transfer is completed using the protocol as
shown in Figures 19 and 20. Figures 21 through 24 show the
transfer timings. Figure 21 and 24 show the operation when
the memory is the source and the peripheral device is the destination. Figures 22 and 23 show the transfer in the opposite
direction. The peripheral device is a l6-bit device in Figures 21
and 22, and a 8-bit device in Figures 23 and 24.

Data Transfers

All DMAC data transfers are assumed to be between memory
and the peripheral device. The word "memory" means a 16-bit
HMCS68000 bus compatible device. By programming the OCR,
the characteristics of the peripheral device may be assigned.
Each channel can communicate using any of the following
protocols.
DTYP

Device Type

01
10
II

HMCS6800 compatible device
Device with ACK
}
Device with ACK and READY

ao- HMCS68000 compatible deViCe}

Dual Addressing
Single Addressing

71

H D 6 8 4 5 0 , H D 6 8 4 5 0 Y - - - - - - - - - - - - - - - - - - - - - - - - - - -_ _ _ __
HMCS68000 Device

DMAC
Address Device
1) Set R/W to Read
2) PIIoC8 Address on A. - A..
3) Place Function Codes on
FC. -FC.
4) Assert Address Strobe (AS)
5) Assert Upper Dale Strobe
(UDS) and Lower Data
Strobe (LOS)
6) Assert Acknowledge (ACK)

,

I

Present Data
1) Decode Address
2) Place Data on D. - 0 II
3) Assert Data Transfer
Acknowledge (DTACK)

I

f
Acquire Data
1) Load Data into Holding
Register
2) Assert Device Transfer
Complete (DTC)
3) Negate UDS and LOS
4) Negate AS, ACR andl5'fC
Terminate Cycle
1) Remove Data from D. -' 0"
2) Negate"OTACK
I

f

Slert Next Cycle

Figure 19 Word Read Cycle Flowchart HMCS68000 Type Device
DMAC

HMCS68000 Device

Address Device
1) Place Address on A. - A..
2) Place Function Codel on
FC. -FC.
3) Assert Address Strobe (A!)
4) Set RMto Write
5) Place Data on D. - 015
6) Assert Acknowledge (ACK)
7) Assert Upper Data Strobe
(TIi5S) and Lower Data
Strobe ('[Os)

~.------------------------------------"

Accept Dale
1) Decode Address
2) Store Data on D. - 0"
3) Assert Data Transfer
AcknO~edge(DTACK)

I

. f

1)
2)
3)
4)
5)

Term.nate Output Transfer
Assert Device Transfer
Complete (DTC)
Negate UDS and LOS
Negate AS", AC K and D"i'C
Remove Data from D. - 0 15
Set RiW to Read
Terminate JCle
1) Negate DTACK

,

I

Start Next Cycle

Figure 20 Word Write Cycle Flowchart HMCS68000 Type Device

72

-------------------------------------------------------------------HD68450,HD68450Y

CLK
FCo-FC,
A,-A,
Data In

AB/Do
-A23/D,s
XDo-XD,s
(External System Data Bus)

Address Out

Data Out

~Ul

mOl/)

UAS
AS

m

UDS
LOS

U\

RW

il7
£0

~X~
~~

UJ
LU

\\\

OWN

~i\

DDIR
DBEN

~

llJ

HIBYTE

~~

{]j

m

~

DTACK

OJ

\\\

\\\..JJ

~

ACK
i50NE
CLK
1 2

3 4

5 6

7 8

9 10 11 12 13 14 15 16 17 18 19 20 2122 23
Write One Word
From Memory
To Device
The Last Transfer

---r-

----r-- Read One Word -----j---

Figure 21 Dual Addressing Mode, ReadlWrite Cycle,
Destination = 16·bit Device, Word Operand

ClK

~========~V~I~/============~
w-________
~vull~ ____________~
Data Out

AB/Do
-A23/D,s
XDo-XD'5
(External System Data Bus)

UAS
AS
UDS
LOS

'IIIC.

UJ

RW

rrr-rrr-rrr--

ill

10

ill
\\\

m

\\\

II1

OWN
DDIR

\\\

0/

10

\\\

DBEN

HiiiYi'E
DTACK

nr

'Xl
~\

~

i5'fC
ACK

\\\

DONE

CLK
--t--Read One Word ----t-From Device
The Last Transfer

Write One Word
To Memorv

Figure 22 Dual Addressing Mode, ReadlWrite Cycle,
Source = 16·bit Device, Word Operand

73

II1

~

HD68450,HD68450Y-------------------------------------------------------------------

ClK

ABloo
-A23/O,.
XoO-Xo15
(External System Data Bus)
UAS

Address Out

~l

Address Out

rur:::::::JHJ

Address Out .....--!o~a~ta:.;O:;:;u:.!t_ _,....--

Data In

~

'IlIl::::::J//I

~~U~====~lmm~U~ml~,~====~n~m~~~l~n=========/~"~
~

-11l
Ui5S -11l
rns -11l
AS

Data In

\\\

III

\\\

III

'LJlJ

\LJlJ
\\\

m

\\\

III

\\\

\\\

\\\

III

'M-JlJ
ill

III

\\\

III

-War---\\\

\w\\__________

RW

OWN

01

m>iR
l5BEN
HiB'fTE"
oTACK
oTC

11/

III

\\\

or

\\\

~

ClK

--+-- Read One Byte ---'+---Read One Byte --+-From Device

From Device

Write One Word
To Memory

Figure 23 Dual Addressing Mode, Read/Write Cycle
Source =8-bit Device, Word Operand

ClK

ABloo

-A23/O,.
Xoo-Xo,.
(External System Data Bus)

DAS
AS
Dos
lOS

A;;:ddiTr::,:es::..s,:;:O.;ut......:D;::a:.::ta:.,:'.:.:.n......:.;Address Out

""""LJJJ

o
o
o

ill
ill

III
0/
III

\\\

'LJ11

\\\

Data Out

Addre.. Out

\\\

10

I/lL
IW>\\L

'LJ11
ill

III
\w\\,--_~

fl'T"""""W.

\S~

orornr

0/
ill

\\\

III

III

From Memory

\\\

Write One Byte
To Device

Figure 24 Dual Addressing Mode, Read/Write Cycle,
Destination = 8-bit Device, Word Operand

74

Iff

ur--'\\\

\\\

-+- Read One Word ----t-.

III

ill

RW

OWN
Dlmi
oBEN
HiBY'i'E
DTACK
"D'i'C
ACK
ClK

Data Out

--QJL:JIO
YDJ::::::]Jl1
1JlL...JIl1
=nJJ----u~I;;;m;:::::=======:n~l>----TC
~
~E~)
r
DTACK

ClK

Figure 26 Dual Addressing Mode, HMCS6800 Compatible
Device, Read Cycle

75

HD68450,HD68450Y-------------------------------------------------------------------

ClK

A./Do

Jm'7mrrnr--..;,A,;;;d;:jidress Ou;:.;t:..-_ _ _ _ _ _..:D:.::a~ta:.;O:::;u:::t'___ _ _ _ _ _ __

-A23/D,.

1177JmmJ

(External System Data Bus)
XDo-XD'5
UAS

-4JIOO

AS

1I'fLJJ~================~ii
n
I>-------

It

~~

DBEN

36 37 38

fl.l

(ft

DDIR

I

fS

s~llll

As/Do-A15/D7

)

lD

~~m7

XDo-XD15
(External System Data Bus)

DTACK
ClK

32

Si

R;W
UDS

31

::



peripheral device address

BAR

top address of the table

MTC
8TC

block C

*

DAR

*

(not used)

-

<==>

memor~

}

block A

f"~",, ~M

block B

}

address A

memor~

• to be loaded from the linked array table

address B

...-

-

peripheral

device address --

peripheral device
or memory

Figure 38 Transfer Example of the Linked Array Chaining Mode

87

~"""Oo""

,.~"

A

oooM •

HD68450,HD68450Y------------------------------------------------------------------

mode, the BTC is not used. When the DMAC refers to the linked
array table, the value of the BFC is outputted as the function
code. The values of the function code registers are unchanged
by the linked array chaining operation.
This type of chaining allows entries to be easily removed or
inserted without having to reorganize data within the chain.
Since the end of the chain is indicated by a terminal link, the
number of entries in the array need not be specified to the
DMAC.
The linked array table must start at an even address in the
linked array chaining mode. Starting the table at an odd address
results in an address error. If "0" is initially loaded to the
MTC, the count error is signaled. Because the MPU can read
all of the DMAC registers, all necessary error recovery information is available to the operating system.
The comparision of both chaining modes is shown in Table 8.

In order to guarantee, reliable decoding, the DMAC verifies that
the incoming code has been statable for twoDMACclock,cycles
before acting on it. The DMAC picks up BEC o-BEC 2 at the
rising edge of the clock. If BEC o-BEC 2 is asserted to the undefined code, the operation of the DMAC does not proceed.
For example, when the DMAC is waiting for DTACK, inputting
DTACK does not result in the termination of the cycle if BEC oBEC 2 is asserted to the undefmed code. In addition, when the
transfer request is received, BR is not asserted if the BEC oBEC 2 is not set to no exception condition.
If exception condition, except for HALT, is inputted during
the DMA bus cycle prior to, or in coincidence with DTACK,
the DMAC terminates the current channel operation immediately. Here coincident means meeting the same set up requirements for the same sampling edge of the clock. If a bus exception condition exists, the DMAC does not generate any bus
cycles until it is removed. However, the DMAC still recognizes
requests.

Table 8 Chaining Mode Address/Count Information
Chaining Mode

Base Address
Register

Array Chaining

address of the
array table

Linked Array
Chaining

address of the
linked array
table

Base Transfer
Counter
number of data
blocks being
transferred
(unused)

Completed
When

Halt

The timing diagram of halt is shown in Figure 39. This
diagram shows halt being generated during a read cycle from the
68000 compatible device in the dual addressing mode. If the
halt exception is asserted during a DMA bus cycle, the DMAC
does not terminate the bus cycle immediately. The DMAC
waits for the assertion of DTACK before terminating the
bus cycle so that the bus cycle is completed normally. In
the halted state, the DMAC puts all the control signals to high
impedance and relinquishes the bus to the MPU. The DMAC
does not output the BR until halt exception is negated. When
halt exception is negated, the DMAC acquires the bus again and
proceeds the DMA operation. In order to insure a halt exception operation, the BEC lines must be set to halt at least until
the assertion of DTC.
If the DMAC has the bus, but is not executing any bus
cycle, the DMAC relinqUishes the bus as soon as halt exception
is asserted.

Base Transfer
Count = 0
Linked
Address = 0

(4) Bus Exception Conditions

The DMAC has three lines for inputting bus exception conditions called BEC o , BEC 1> and BEC 2 • The priority encoder can
be used to generate these signals externally. These lines are
encoded as shown in Table 9.
Table 9
BEC 2

BEC t

BEC o

1
1
1
1
0
0
0
0

1
1
0
0
1
1
0
0

1
0
1
0
1
0
1
0

Exception Condition
No exception condition
Halt
Bus error
Retry
Relinquish bus and retry
(undefined, reserved)
(undefined, reserved)
Reset

88

-------------------------------------------------------------------HD68450,HD68450Y
ClK
AID BUS
UAS
AS
UDS
LOS

R!W
OWN

---------------------------\L__~"------,--,n

\\IL\\ _ _ _m
\a.
~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __W~~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

iJIDR

~~~________________w~

DEiEfiI

~~"________~~w~___ J

HIBYTE
DTACK

----------------------~~~~------------------

-wmr--

~__________~~

~~~____

'LlII'-,-----'"--~

HALT
(BECo-BEC2)*
BGACK
BR
BG

~~~

Ilf

\\\

un

\\\

____IIIur_

f(

------------------~~--------------------___
HJ
'\~

----------------~I'~~

_____________m

ClK
67891011121314151617119221222324252627282930313233

Read
from Device
Halt Asserted
• BEe. - BEC,

Other Bus Master

I Rear~rgation I

---~I'-DMA Halted

Write
to Memory

.,If---

DMA cycle

= (011)
Figure 39 Halt Operation

Bus Error

The bus error exception is generated by external circuitry
to indicate the current transfer cannot be successfully completed and is to be aborted. The recognition of this exception
during a DMAC bus cycle signals the internal bus error condition for the channel for which the curren t bus cycle is being
run. As soon as the DMAC recognizes the bus error exception,
the DMAC immediately terminates the bus cycle and proceeds
to the error recovery cycle. In this cycle, the DMAC adjusts the

values of the MAR, the DAR, the MTC and the BTC to the
values when the bus error exception occurred. 25 clocks are
required for the error recovery cycle in the single addressing
mode and in the read cycle of the dual addressing mode. 29
clocks are required in the write cycle of the dual addressing
mode. If the DMAC does not have any transfer request in the
other channels after the error recovery cycle, the DMAC relin·
quishes the bus.
The diagram of the bus error timing is shown in Figure 40.

89

HP68450,HD68450Y------------------------------------------------------------------

ClK
AID BUS
UAS
AS

~_____________
,

UDS

-'II

lOS

-'
tllL~

R!W

\\\

\\\

/U""---i'~

\\\

/U

I~

_________
or-'"

OWN

DDIR

'~

~

'---

tw"____________~or-"I

DBEN

HIBYTE
DTACK

\m \m \\\\ \\ \\\\\YII/

~

DTC

r-

t...
,,_______

ACK

ll

\\\

Bus Error
(BE'Co-BEC2)'

ClK

--+--

Berr on Write to Device

I-

r-

Error
•
Recovery Cycle*·

Other Channels'"

=

• BEC.-BEC, (101)
•• In the single addressing mode and in the read cycle of the dual addressing mode: 25 clocks
In the write cycle of the dual addressing mode: 29 clocks
••• The DMAC keeps the bus because the other channels have requests pending. If other channels
do not have requests, the DMAC relinquishes the bus after the error recovery cycle.

Figure 40 Bus Error Operation

moved, and thus will not honor any requests until it is removed.
However, the DMAC still recognizes requests. The retry timing
is shown in Figure 41.

Retry

The retry exception causes the DMAC to terminate the
present operation and retry that operation when retry is re-

90

----------------------------------------------------------------HD68450,HD68450Y

C

l

K

.

AID BUS

OAS
AS
01'5S

---m...JJ
J
\\\
J

m

ill

~

m

0/

\\\

0/

'\SL-DI
ill

m

~ ~~~------~----------~----------~----~---iT]
m
\n
al
R/W
\\\
m
\\\
",--

~
DDIR ~LO=W==========================================================
High
--;;;;"---mm
01
\\\

OBEN
HIBYTE

9 1 11 12131415161718192021 22232425262728293031

1

- - ! - - - - Write to Device Retry Asserted

Write Cycle Retry

--1-1- - -

• 8EC,-BEC. = (001)

Figure 41 Retry Operation

the previous operation_
The diagram of the relinquish and retry timing is shown in
Figure 42_

Relinquish and Retry (R&R)

The relinquish and retry exception causes the DMAC to
relinquish the bus and three-state all bus master controls and
when the exception is removed, rearbitrate for the bus to retry

91

HD68450,HD68450Y------------------------------------------------------------------

ClK
AID BUS
UAS
AS
UDS
lOS
R!W --------------------~~~~-------------OWN
DDIR
DBEN

------------------~~~-------------a___________

~~

---"

~~

HIBYTE --------------------~~I
DTACK
DTC

-.JJ

"
_a__________ rf
\\\\\\\\\\\\\\\\\\\\\\1'

1",,~\

___
'---

-------~~~I-_'r--~~
.III

ACK
R&R
(i:lECo- BEC2)'
BGACK

\\\

\\.....____T'-.

IUlUumllm

m

BR

I

BG
ClK

----+-

Read Retry -1----Rearbitration

* BECo·BEC, = (110)

Figure 42 Relinquish and Retry Operation

(iii) DTYP specifies a dual addressing mode. DPS is 16
bits, SIZE is 8 bits and REQG is "10" or "II" .
(iv) an undefined configuration is set in the registers.
The undefmed configurations are: XRM ~ 01, MAC
~ II, DAC ~ 11, CHAIN ~ 01, and SIZE ~ II.
(b) Operation Timing Error - An operation timing error
occurs in the following cases:
(i) when the CNT bit is set after the ACT bit has been
set by the DMAC in the chaining mode, or when
the STR and the ACT bits are not set.
(ii) the STR bit is set when ACT, COC, BTC, NDT or
ERR is set.
(iii) an attempt to write to the OCR, OCR, SCR, MAR,
DAR, MTC, MFC, or DFC is made when the STR
bit or the ACT bit is set.
(iv) an attempt to set the CNT bit is made when the
BTC and the ACT bits are set.
(c) Address Error - An address error occurs in the following
cases:
(i) an odd address is set for word or long word
operands.
(ii) CS or lACK is asserted during the DMA bus cycle.
(d) Bus Error - Bus error occurs when a bus error excep-

Reset

The reset provides a means of resetting and initializing the
DMAC If the DMAC is bus master when the reset is asserted,
the DMAC relinquishes the bus. Reset clears GeR, OCR, OCR,
SCR, CCR, CSR, CPR, and CER for all channels. The NIV and
the EIV are all set to (OF)16, which is the uninitialized interrupt
vector number for the HD68000 MPU. MTC, MAR, DAR, BTC,
BAR, MFC, DFC, and BFC are not affected. In order to insure a
reset, BEC o - BEC 2 must be kept at "Low" level for at least
ten clocks.
(5) Error Conditions

When an error is signaled on a channel, all activity on that
channel is stopped. The ACT bit of the CSR is cleared, and the
COC bit is set. The ERR bit of the CSR is set, and the error
code is indicated in the CER. All pending operations are cleared,
so that both the STR and CNT bits ofCCR are cleared.
Enumerated below are the error signals and their sources.
(a) Configuration Error - This error occurs if the STR bit is
set in the following cases.
(i) the CNT bit is set at the same time STR bit in the
chaining mode.
(ii) DTYP specifies a single addressing mode, and the
device port size is not the same as the operand size.

92

---------------------------------------------------------------------HD68450,HD68450Y
and the channel control register. After the successful completion of any transfer, the memory and device address registers
points to the location of the next operand to be transferred and
the memory transfer counter contains the number of operands
yet to be transferred. If an error occurs during a transfer, that
transfer has not completed and the registers contain the values
they had before the transfer was attempted. If the channel
operation uses chaining, the Base Address Register points to the
next chain entry to be serviced, unless the termination occurred
while attempting to fetch an entry in the chain. In that case,
the Base Address Register points to the entry being fetched.
However, in the case of external abort, there are cases in which
the previous values are not recovered.

tion is signaled during a DMA bus cycle.
(e) Count Error - A count error occurs in the following
cases:
(i) The STR bit is set when zero is set in the MTC
and the MTC and the chaining mode is not used.
(ii) the STR bit is set when zero is set in STC for the
array chaining mode.
(iii) zero is loaded from memory to the STC or the MTC
in the chaining modes or the continue mode.
(f) External Abort - External abort occurs if an abort is
asserted by the external circuitry when the PCL line is
configured as an abort input and the STR or the ACT
bit is set.
(g) Software abort - Software abort occurs if the SAS bit
is set when the STR or the ACT bit is set.

Bus Exception Operating Flow
The bus exception operating flow in the case of multiple
exception conditions occurring continuously in sequence is
shown in Figure 43. Note that the DMAC can receive and execute the next exception condition. For example, if the retry
exception occurs, and next the relinquish and retry exception
occurs while the DMAC is waiting for the retry condition to be
cleared, the DMAC relinquishes the bus and waits for the
exception condition to be cleared. If a bus error occurs during
this period, the DMAC executes the bus error exception
operation.
The flow diagram of the normal operation without exception
operation or errors is shown in Figure 44.

Error Recovery Procedures
If an error occurs during a DMA transfer, appropriate information is available to the operating system (OS) to allow a
software failure recovery operation. The operating system must
be able to determine how much data was transferred, where the
data was transferred to, an what type of error occurred.
The information available to the operating system consists of
the present value of the Memory Address, Device Address and
Base Address Registers, the Memory Transfer and Base Transfer
Counters, the channel status register, the channel error register,

I ANYSTATE~

,I

RESETTING
,--jALL CHANNELS
NON
HLT. BER. RTY. RRT

Y

IDLE MODE

I

~

()'fACl( & HLT (DTC)

y

IDLE MODE
WAITING FOR
BE"CCLEAR

NON

I

BER

IDLE MODE
WAITING FOR
BEC CLEAR ~T
TO RETRY

~

1
DMAC YIELDS BUS

- --------- 1-------- ----- - -- i-DMAC OWNS BUS

REO

"0' ~ "" eo,
~TlNGFOR:

RRT. HLT

RRT. HLT

1

DMA MODE
NO ACTIVE
CYCLE

I

DMA MODE

DMA MODE
WAITING FOR
BEC CLEAR
TO RETRY

BER

NON

BEC CLEAR

BER. RTY

I

RST

NON
NON

BER

START
RTY
OTACK & NON
(OTC)

DMA MODE
BUS CYCLE ACTIV

HLT

BER

NON

OTACK & HLT (OTC)

Figure 43 Bus Exception Flow Diagram

93

RTY
RRT

REO
REON

: reset
: no exception
: halt
: bus error
: retry
: relinquish and retry

external request
no external request

START bus cycle start
DTACK DTACK signal asserted
DTC
DTC signal asserted

HD68450,HD68450Y------------------------------------------------------------------

oMA Mode Waiting for

Idle Mode

':Ieset All Channels

Bus Cycle to Start

Bus Cycle Start

No Transfer
r---------------~

oMA Mode Bus

oMA Mode Waiting for

Cycle Active

Bus Cycle to Start

r--------~

Idle Mode

Figure 44 Flow of Normal Operation Without Exception
or Error Condition
• Channel Priorities

• APPLICATIONS INFORMATION

Each channel has a priority level, which is determined by the
contents of the Channel Priority Register (CPR). The priority
of a channel is a number from 0 to 3, with 0 being the highest
pri~rity level. When mUltiple requests are pending at the DMAC,
the channel with the highest priority receives first service. The
priority of a channel is independent of the device protocol or
the request mechanism for that channel. If there are several
requesting channels at the highest priority level, a round-robin
resolution is used, that is, as long as these channels continue to
have requests, the DMAC does operand transfers in rotation.
Resetting the DMAC puts the priority level of all channels
to "0", the highest priority level.

Examples of how to interface HD684S0 to a HD68000 based
system are shown in Figure 4S and Figure 46.
Figure 45 shows an example of how to demultiplex the
address/data bus. OWN and VAS are used to control 74LS373
for latching the address. DBEN and DDIR are used to control
the bi-directional buffer 74 LS245.
Figure 46 shows an example of inter-device connection in
the HMCS68000 system.

+5V9

D

:>

'"
74LS04

.....
.....

OWN

~
G
G

I

UAS

OE
OE
16

16

16
As/Do-A23/D15

QQ ~ As - A23

0

74LS373
x2
HD68450
DMAC

+5V9
t-

!

(Address Bus)

-

8

~A

DBEN
DDIR

74LS245

G

B~

DIR
(Data Bus)

~
L--......,

A
74LS245

G

B~

DIR
Figure 45 An Example of the Demultiplexed Address Data Bus

94

-------------------------------------------HD68450,HD68450Y

t""

Do- D15

Do D15

r-

r-

r-

Data & Address

~

FDC,
etc.

Bus Interface

--

~

I~ I~
L.

t-------

~

HOC,
etc.

~

'--~

Ii Ii

0

18

<=

0'-

o

~

'-«
:(1

REOO}
ACKo Channel #0
PClo

REO,}
'-----lACK, Channel #1
L-----~PCl,
HD68450

::~ ==
---

AS
L DSI------I
UDSI-------I

c

0
~
"
~
~~ 'E""" g
~

ID

E

S

>.

.~

E c
0
0
u u

U)

e

~

1------1 REO,

1+-----lACK,} Channel #2
1-------IPCl,

0

R/WI-------I
DTACK 1-------1
3
FCo-FC,I--f-----1ri
I-

~

c-J
p I r--- PTI3

_

IRO
lACK

_

CPG

~~:

I~

Ig

iG«
g

lsystem
Interrupt

~

~

I--I--I---

r---

I---

-

~

LDS
UDS
R/W
DTACK

~ ~

~ - - till--- ~

FCo-FC,
-L.E_R_R_O_R_ _ _ _......l

0

1 - - - - - ' " Do- D15
E 'v-- E r- E 1------,V1_

~

liII~rl~l

'--

"-~

3

-+--

£-

I---

--

~

~

DS

R/W

I--~-----I~
CS
AS Dec.

RS

~~~~~r.

IY-:'RES
IL.:~~:O~S===~

r-

LDS

¢: rI--- 1===~~Do-D7
'-~
-I----- 1----" ~

U5S

--

Do~D15

A, A23

~

AS

--

--

VPA
VMA
E
3

I----

-- I-----

R/W
DTACK

T

r------ AS

1-----0

.e.s.el

FCo-FC,

HD68000
MPU

MEM & MMU

I----

nD:rT7"C'Tn:--]nn-="'lr~
I~A='~_-;:A-3....j.-I-I--I~ -- ~
DONE

A,-A23

n
_8e ~
~ I--- ~
IJ-/"'";j! I--- 8

BECo-BEC2

rv;:r;

o -D15

AS

-----

--

'--

ID

RE03 }
,-----jACK3 Channel #3

~'" .~-"
0.

DMAC

I) D

~

Al-A7k::==:::::j ~

L----o

I--I---

f--

6800
I--+-+-+--IR/W Periphr.

-

-- -- -- -- 1-----l--lE

-§:=
Ene.

---

---

I-------/IRO

--

The address bus and the system control bus in each device
are omitted in this Figure.

Figure 46 An Example of I nter-device Connection in
the HMCS68000 System

95

~~~~

H068450,H068450Y---------------------------------------------------------------------

orr

OMAC latches the data when
is asserted and not at the
falling edge of E clock. The 74LS373 need to be provided externally as shown in Figure 47 so that the data from the 6800
device can be held on the bus for a large period of time until
the OMAC can latch the correct data.

• ATTENTION ON USAGE
(I) How to interface various 6800 type peripheral devices to
the OMAC based system.
When the OMAC is reading data from the 6800 device, the

/'-------::0-0---::0:""7-----........ 00- 07

E

6800 Type

~-8

in=
:g8 f-RS

r-- cs Device

~-------;::;r~<~o~~
AS

L ______~

/'------0-0---:0:-1-7- - - - - - '........ 00- 07

E

6800 Type
Device

."
..
a

AS

~+5V
'----'-----+++1 AS

!D

l!l

8
00

L-

'"

~

PCl2

+5~f ~

~g:

~-~~
I~

V
OE

~_----I1D

00-D7

I
8D

H068450

G
r--OMAC
1Q ~
I Do'--D}1.~
0 0 -0,

8Q ---v

74lS373
00-D15

.3

g

8+
~

As-A23

~t
I
"' As/Do

~~

-A23/D15

V

DBEN
OOIR

Figure 47 An Example of Connection with 6800 type Peripheral Devices
(channel 2 and 3 are used)

(2) When"external abort"is inputted during the DONE input cycle
When the transfer direction is from the peripheral device to
memory and PCL signal is set to the external abort input mode
in the dual addressing mode, the external abort will be ignored
during the subsequent write cycle from the OMAC's internal
holding register to memory ifJ"5ONE is inputted during the read
cycle from the peripheral device to the OMAC's internal holding
register.
In this case, the channel status register (CSR) and the
channel error register (CER) show the normal termination
caused by DONE Input. The user is able to examine the PCT
bit and the ERR bit in order to detect the external abort

inputted at the timing described above. If PCT = I, ERR = 0,
and NOT = I, then an external abort has occurred.
(3) Multiple Errors
The OMAC will log the first error encountered in the channel
error resister. If an error is pending in the error register and
another error is encountered the second error will not be logged.
Even though the second error is not logged in the CER, it will
still be recognized internally and the channel will not start.
(4) The use of thick wiring is recommended between Vss of the
H068450 and the ground of the circuit board. When a socket is
used to install the OMAC on the board, please make sure that
the contact of the Vss pins are made well.

96

------------------------------------------------------------------HD68450,HD68450Y
PRECAUTIONS:
1. Extra Data Transfer In the Burst Mode
In certain conditions when two or more channels are active
and the REQ signal for the channel which is transferring in burst
mode has negated, the transfer operation will terminate one data
transfer later than specified in the data sheet. The condition on
which this occurs is shown in Figure 2. Problems may occur in
applications that need to control exact data transfer count using
the REQ line in the burst mode.
(Countermeasure)
When switching the channel of operation using the burst
request signals, negate the RE:Q signal within the period
bounded by (3) and (4) in Figure 48. (DTC falling edge may be
used for obtaining the timing for the negation of REQ.)
Caution must be taken when this countermeasure is used since
this external circuit will not be compatible with the next mask
version which will have this anomaly fixed.
NOTE I: If transfer request is asserted in channell, before (I)
which is I clock before DTC assertion of channel 0, the next bus
cycle should be the bus cycle for channell according to the data
sheet. However, the current DMAC transfers one more data for
channel 0 from 13th clock as shown above, before it changes to
channel I.
NOTE 2: If channel I has higher priority than channel 0, then
NO extra data is transferred even if request for channel I is
asserted before (2). In this case, data transfer for channell starts
from the 13th clock as specified in the data sheet.

2. One Byte of Transfer Data Is Left In the DMAC
When the DMAC is set to dual addressing mode, port size 8
bits, external request mode, and data transfer from peripheral
device to memory, the last byte of the transfer may be left inside
the DMACs internal register without being transferred to
memory if the transfer is stopped before the transfer count is
exhausted. The last byte that is left inside the DMAC becomes
inaccessible by the MPU.
In this mode, the DMAC transfers data repeating the following bus cycles:
(I) READ BYTE
(Byte is read from the peripheral device to DMAC)
(2) READ BYTE
(Byte is read from the peripheral device to DMAC)
(3) WRITE WORD
(Word is written to memory from DMAC)
If the transfer is terminated after (I) READ BYTE (see
NOTE·), then the byte data that was ready by (I) READ BYTE
bus cycle is not written to memory and is left inside the DMACs
internal holding register. The 0 MACs internal holding register
cannot be accessed by the MPU, so that it becomes "lost."
This will not occur when single addressing mode is used. So,
please use the single addressing mode when the transfer needs to
be terminated before the transfer is exhausted.
Note:"'The methods to terminate the transfer operation before
the transfer counter becomes zero are (I) assert external
abort using the PCL, (2) set the SAB bit to cause software
abort.

"'The timing in which one extra data is transferred in the burst
mode (the case for changing from channel 0 to channel I).

I 2 3 4 5

6 7 8 9 10 II 12 13 14

BUS----------~r-------~--------~

CYCL~E~__#_O____~~------~--------~

i5'fC _ _____

""fiE"O"O
(Burst) __L-._ _ _--<-+______....J

CD

CD

NOTE 2

NOTE I

Figure 48. Extra Data Transfer In the Burst Mode"

97

98

HD68000 [H068000-4, H068000-6, H068000-a H068D00-10, H068000-l2)
HD68000lr [H068000Y4, H068000Y6, H068000ya H068000Yln H068000Y12)
MPU (Micro Processing Unit)
- The specification for HD68000-10/-12 and HD68000
Y4/Y6/Y8/Yl0/Y12 are preliminary. -

Advances in semiconductor technology have provided the
capability to place on a single silicon chip a microprocessor at
least an order of magnitude higher in performance and circuit
complexity than has been previously available. The HD68000
is one of such VLSI microprocessors. It combines rate-of-the-art
technology and advanced circuit design techniques with cemputer sciences to achieve an architecturally advanced l6-bit
microprocessot.
The resources available to the HD68000 user consist of the
following.
As shown in the programming model, the HD68000 offers
seventeen 32-bit registers in addition to the 32-bit program
counter and a l6-bit status register. The first eight registers
(00-D7) are used as data registers for byte (8-bit), word
(i 6-bit), and long word (32-bit) data operations. The second set
of seven registers (AO-A6) and the system stack pointer may be
used as software stack pointers and base address registers. In
addition, these registers may be used for word and long word
address operations. All 17 registers may be used as index
registers.

•

FEATURES

•
•
•
•
•
•
•

32-Bit Data and Address Registers
16 Megabyte Direct Addressing Range
56 Powerful Instruction Types
Operations of Five Main Data Types
Memory Mapped I/O
14 Addressing Modes
Compatible with MC68000L4, MC68000L6, MC68000L8,
MC68000L 10 and MC68000L 12

•

PROGRAMMING MODEL
31

1 15

HD68000-4, HD68000-6. HD68000-8.
HD68000-10, HD68000-12

(DC·64)
HD68000Y4, HD68000Y6.
HD68000Y8, HD68000Yl0.
HD68000Y12

"Y" stands for Pin Grid
Array Package.
(PGA-68)

o

87

_ DO
01

-

-_

- 02
- 03 Eight
_ 04 Data

_

_ 05

~

_ 06

-

Registers

L-____________~----~----~07

~

~~
3. ,~~

"iii:"

EL______________

Regine"

L . . ._ _ _ _ _ _ _ _ _ _ _ _ _

16

87

ISystem Byte:

0

Use, Byte

I

Status

Register

99

HD68000,HD68000Y----------------------------------------------------• PACKAGE DIMENSIONS (Unit: mm)
• DC-64 (Side-brazacl Ceramic DIP)

,"... - - -.......... r

==.~Y-----r-------~~

i

32 'I-_ _ _-f~33

0

• PGA-68 (Pin Grid Arrav)

I

22.58

6.4 • 0.3

0.20-0.38

- 22"- .

• PIN ARRANGEMENT
O.

0,

0,

0,

0,
0,

0,

0,

0,

AS
IJ15S

0 ..
On

°u
°u
0 ..
°u

v"
A ..

Vee
A..
A ..

(Bottom View)

Au
Au

A!,.
Pin No.

A ..
A ..

1
2
3

Au
Au

Fe,

Function
N/C
OTACK
8GACK

FC,

An
A ..

4

iR

Fe"

A,

5

AI

A.

8

CLK
HALT

AI

A1

7
8
9
10
11
12
13
14
15
18
17

A)
A.
A• ....._ _ _ _ _ _ _ _J"" A,

(Top View)

100

liMA
E
8ERR

N/C
FC,
FCo

Pin No.

18
19
20
21
22
23
24
25
26
27
28
29

Function
A,
N/C
A,.
A,.

PinNa.
36
36
:f1
36

A"
A"
A..
All
An

39
40
41
42
43

0"
0"
0 ,•

44
46

48

A.
A,

30

D.

47

31

0,

Ao
Ao

32

D.
D.
D,

48
49

A,

33
34

50
.61

Function
D,

AS
LDS
BG
Vee
Vss
RES
VPA
IPL,
IP4

FC.
N/C
A,
A.

Ao
A,.
Au

Pin No.
52
53
54
65
58

67
58
59
50

61
B2
63
64

65
65
67
68

Function

A"
A"
All
Vee
Vss
Au
D,.
Du

0,
D.
D,
D.
UDS
RM
IPL.
A"

0"

-----------------------------------------------------------------HD68000,HD68000Y
• ABSOLUTE MAXIMUM RATINGS
Value

Symbol
Vee *
V in *

Item
Supply Voltage
Input Voltage
Operating Temperature Range
Storage Temperature

Topr

Unit

-0.3 - +7.0
-0.3 -+7.0
0-+70

V
V
°c

-55 - +150

°c

Tstg

• With respect to Vss (SYSTEM GNDI
(NOTE)

•

Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions.
If these conditions are exceeded. it cauld affect reliability of lSI.

RECOMMENDED OPERATING CONDITIONS
Item
Supply Voltage

Symbol
Vee *

Input Voltage

V IH *
V IL *

Operating Temperature

Topr

min
4.75
2.0
-0.3

typ

0

25

max
5.25

5.0

-

Unit
V
V
V
°c

Vee
O.B
70

• With respect to Vss (SYSTEM GNDI

•

ELECTRICAL CHARACTERISTICS

• DC CHARACTERISTICS (Vee

= 5V ±5%, Vss = OV, Ta = 0 -

Symbol

Item
Input "High" Voltage
Input "low" Voltage
Input leakage Current
Three-State (Off State)
Input Current

+70°C, Fig. 1,2,3, unless otherwise noted.)
Test Condition

V IH
V IL
BERR, BGACK, BR, DTACK,
IPlo-TiiI., VPA, ClK
HALT, RES
AS, A, -A.3 , Do - D,s,
FC o -FC., lOS, RIW, UDS,
VMA

lin

min

typ

2.0

-

Vss-0.3

-

@5.25V

ITSI

@2.4V/0.4V

VOH

IOH = -4001lA

-

AS,A,-A~G,~~

Output "High" Voltage

Output "low" Voltage

FCo-FC., lOS, R
VMA
E*

,UDS,

HALT
A, -An, BG, FC. -FC.
RES
AS, Do -0 15 , lOS, RIW, E,
UDS, VMA

VOL

20

-

-

-

IOL =5.3mA

-

IOL =5.3mA

-

Power Dissipation

Po

f = BMHz

Capacitance (Package Type Dependent)

Cln

V ln = OV, Ta = 25°C,
f = 1 MHz

-

2.5

-

-

V
V

20

IOL = 1.6mA
IOL = 3.2mA

V ee -O·75

Unit

-

-

2.4

max
Vee
O.B

IlA

JJ.A

V

0.5
0.5
0.5

V

0.5

-

1.5

W

10.0

20.0

pF

* With external pull up register of 470 n

+5 V
+5V

+5V

910!l

~130PF

Figure 1 RES Test Load

Test
POint

2.9k!l

lS2074-

HAlT/m

sa

S5

~

AI -Au

lDS/UDS

S3

S2
~

-----------------~

-

~

..",

l
:---@~

(NOTES) 1. Setup time for tha asynchronous inputs BGACK, IPLo - IPLo and VilA guarantees thair recognition at tha naxt falling edge of the clock.
2. BR need fall at this time onlv in order to insure being recognized at the end of this bus cycla.
3. Timing maasurements are refarenced to and from a low voltage of O.B volts and a high voltaga of 2.0 volts, unless otherwise noted.

Figure 5 Read Cycle Timing

104

-----------------------------------------------------------------HD68000,HD68000Y

50

elK

--::::

-

52

51

~

~

~ f-®
~

f-®

-

~

V\-I
'U'

@-.

...

~

---

4-

f-®

@)

®>

-.

Fe. -Fe.
Asynchronous
Inputs

~

~

"
/

--@

..

i-@

!-

---®

r-- @

r.;.,

I.

-

~

@

>-

~
®---- I =

so

"""
=

='

~

-

""

...

--@-

Data Out

57

-®

~®-

CD-

56

55

~1

~

-

J'-

54
,....---...

'------'

J ~ f-@ ®

RtW

53

~

f-®

"'"

-

@

I--@-

\.
--to

I--@

\

f4-®I
"'='"
..

~

I

@

(NOTE) Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts. unless otherwise noted.

Figure 6 Write Cycle Timing

105

HD68000,HD68000Y--------------------------------------------------------------

Strobes
and RIW

---------'
14---@--+I

~----~,®------~
BGACK---t--------------------\~~----+__,@,----~--~r---------------------r--

BG ---------~

ClK

(NOTES) 1. Setup time for the asynchronous inputs BERR, BGACK, BR, DTACK, IPL. -IPl., and VPA guarantees their recognition at the
.
next falling edge of the clock.
2. Waveform measurements for all inputs and outputs are specified at: logic high = 2.0 volts, logic low = O.B volts .
.3. These waveforms should only be referenced in regard to the edge·to-edge measurement of the timing specifications. They are
not intended as a functional description of the input an output signals. Refer to other functional descriptions and their related
diagrams for device operation.

Figure 7 AC Electrical Waveforms - Bus Arbitration

• SIGNAL DESCRIPTION
The following paragraphs contain a brief description of the
input and output signals. A discussion of bus operation during
the various machine cycles and operations is also given.
• SIGNAL DESCRIPTION
The input and output signals can be functionally organized
into the groups shown in Figure 8. The following paragraphs
provide a brief description of the signals and also a reference
(if applicable) to other paragraphs that contain more detail
about the function being performed.
Vcc(2)

2

A,-A"

ClK
0.-0"

FC.
Processor {
Status

FC
E

HMCS6BOO{
Peripheral
'iiJ5A
Control
System {
Control

Asynchronous
Bus
Control

HD6BOOO

R
ES

ADDRESS BUS (AI through A 23 )
This 23-bit, unidirectional, three-state bus is capable of
addressing 8 megawords of data. It provides the address for bus
operation during all cycles except interrupt cycles. During
interrupt cycles, address lines AI, A2 , and A3 Provide information about what level interrupt is being serviced while address
lines A4 through A23 are all set to a logic high.
DATA BUS (Do through DIS)
This 16-bit, bidirectional, three-state bus is the general
purpose data path. It can transfer and accept data in either
word or byte length. During an interrupt acknowledge cycle,
an external device supplies the vector number on data lines
Do -07 •
ASYNCHRONOUS BUS CONTROL
Asynchronous data transfer' are handled using the following
control signals: address strobe, read/write, upper and lower
data strobes, and data transfer acknowledge. These signals
are explained in the following paragraphs.
Address Strobe (AS)

BR

1m
IPl.
IPL
IPL

~

Bus
Arbitration
Control

}

Interrupt
Control

This signal indicates that there is· a valid address on the
address bus.
Read/Write (R/W)

This signal defines the data bus transfer as a read or write
cycle. The R/W signal also works in conjunction with the upper
and lower data strobes as explained in the following paragraph.

Figure 8 Input and Output Signals

106

------------------------------------------------------------------H068000,H068000Y
Upper and Lower Data Strobes (UDS, LOS)
These signals control the data on the data bus, as shown
in Table I. When the R/W line is high, the processor will read
from the data bus as indicated. When the R/W line is low, the
processor will write to the data bus as shown.
Table 1 Data Strobe Control of Data Bus
UOS
High

LOS
High

R/W
-

Low

Low

High

High

Low

High

No valid data

Low

High

High

Low

Low

Low

High

Low

Low

Low

High

Low

Valid data bits
B -15
Valid data bits
B-15
Valid data bits
0-7*
Valid data bits
8-15

0 8 - DIS
No valid data
Valid data bits
8-15

0 0 -0 7
No valid data
Valid data bits
0-7
Valid data bits
0-7
No valid data
Valid data bits
0-7
Valid data bits
0-7
Valid data bits
8 -15*

• These conditions are a result of current implementation and may not
appear on future devices.

Data Transfer Acknowledge (DTACK)
This input indicates that the data transfer is completed.
When the processor recognizes DTACK during a read cycle,
data is latched and the bus cycle terminated. When DTACK
is recognized during a write cycle, the bus cycle is terminated.
An active transition of data transfer acknowledge, DTACK,
indicates the termination of a data transfer on the bus.
If the system must run at a maximum rate determined by
RAM access times, the rel!ltionship between the times at which
DTACK and DATA are sampled are important.
All control and data lines are sampled during the H068oo0's
clock high time. The clock is internally buffered, which results
in some slight differences in the sampling and recognition of
various signals. 8068000 allow BERR or ~ to be recognized in S4, S6, etc., which terminates the cycle·. The DTACK
signal, like other control signals, is internally synchronized to
allow for valid operation in an asynchronous system. If the
required setup time (#47) is met during S4, 0'l'ACi{ will be
recognized during S5 and S6, and data will be captured during
S6. The data must meet the required setup time (#27).
If an asynchronous control Signal does not meet the required
setup time, it is possible that it may not be recognized during
that cycle. Because of this, asynchronous systems must not
allow DTACK to precede data by) more than parameter #31.
Asserting DTACK (or BERR on the rising edge of a clock
(such as S4) after the assertion of address strobe will allow
a HD68000 system to run at its maximum bus rate. If setup
times #27 and #47 are guaranteed, #31 may be ingnored.
• The mask version 68000 allowed DTACK to be recognized as early
as S2 (bus state 2).

BUS ARBITRATION CONTROL
These three signals form a bus arbitration circuit to determine which device will be the bus master device.

Bus Request (BR)
This input is wire ORed with all other devices that could
be bus masters. This input indicates to the processor that
some other device desires to become the bus master.
Bus Grant (BG)
This output indicates to all other potential bus master
devices that the processor will release bus control at the end
of the current bus cycle.
Bus Grant Acknowledge (BGACKI
This input indicates that some other device has become the
bus master. This signal cannot be asserted until the following
four conditions are met:
(1) A Bus Grant has been received
(2) Address Strobe is inactive which indicates that the
microprocessor is not using the bus
(3) Data Transfer Acknowledge is inactive which indicates
that neither memory nor peripherals are using the bus
(4) Bus Grant Acknowledge is inactive which indicates that
no other device is still claiming bus mastership.
INTERRUPT CONTROL ffii[o, IPL I • IPL2 )
These input pins indicate the encoded priority level of the
device requesting an interrupt. Level seven is the highest priority
while level zero indicates that no interrupts are requested.
The least significant bit is given in IPLo and the most significant
bit is contained in IPL2 •
SYSTEM CONTROL
The system control inputs are used to either reset or halt
the processor and to indicate to the processor that bus errors
have occurred. The three system control inputs are explained
in the following paragraphs.
Bus Error (BERR)
This input informs the processor that there is a problem
with the cycle currently being executed. Problems may be a
result of:
(1) Nonresponding devices
(2) Interrupt vector number acquisition failure
(3) Illegal access request as determined by a memory management unit
(4) Other application dependent errors.
The bus error signal interacts with the halt signal to determine if exception processing should be performed or the current
bus cycle should be retried.
I
Refer to BUS ERROR AND HALT OPERATION paragraph
for additional information about the interaction of the bus
error and halt signals.
Reset (RES)
This bidirectional signal line acts to reset (initiate a system
initialization sequence) the processor in response to an external
reset signal. An internally generated reset (result of a RESET
instruction) causes all external devices to be reset and the
internal state of the processor is not affected. A total system
reset (processor and external devices) is the result of external
HALT and RESET signals applied at the same time. Refer to
RESET OPERATION paragraph for additional information
about reset operation.
Halt (HALT)
When this bidirectional line is driven by an external device,
107

HD68000,HD68000Y----------------------------------------------------------------it will cause the processor to stop at the completion of the
current bus cycle. When the processor has been halted using
this input, all control signals are inactive and all three~tate lines
are put in their high-impedance state. Refer to BUS ERROR
AND HALT OPERATION paragraph for additional information
about the interaction between the halt and bus error signals.
When the processor has stopped executing instructions, such
as in a double bus fault condition, the halt line is driven by the
processor to indicate to external devices that the processor has
stopped.

devices that there is a valid address on the address bus and the
processor is synchronized to enable. This signal only responds
to a valid peripheral address (vpA) input which indicates that
the peripheral is a HMCS6800 family device.

HMCS6800 PERIPHERAL CONTROL
These control signals are used to allow the interfacing of
synchronous HMCS6800 peripheral devices with the asynchronous HD68000. These signals are explained in the following
paragraphs.

Table 2 Function Code Outputs

PROCESSOR STATUS (FC o• FC!. FC 2 )
These function code outputs indicate the state (user or
supervisor) and the cycle type currently being executed, as
shown in Table 2. The information indicated.,Ey the function
code outputs is valid whenever address strobe (AS) is active.

FC2
Low
Low
Low
Low
High
High
High
High

Enable (E)
This signal is the standard enable signal common to all
HMCS6800 type peripheral devices. The period for this output is ten HD68000 clock periods (six clocks low; four clocks
high).
Valid Peripheral Address (VPA)
This input indicates that the device or region addressed is
a HMCS6800 family device and that data transfer should. be
synchronized with the enable (E) signal. This input also indicates that the processor should use automatic vectoring for an
interrupt. Refer to INTERFACE WITH HMCS6800 PERIPHERALS.
Valid Memory Address (VMA)
This output is used to indicate to HMCS6800 peripheral

FC!
Low
Low
High
High
Low.
Low
High
High

FCo
Low
High
Low
High
Low
High
Low
High

Cycle Type
(Undefined, Reserved)
User Data
User·Program
(Undefined. Reserved)
(Undefined, Reserved)
Superviser Data
Supervisor Program
Interrupt Acknowledge

CLOCK (CLK)
The clock input is a TTL-compatible signal that is internally
buffered for development of the internal clocks needed by the
processor. The clock input sha1l be a constant frequency.
SIGNAL SUMMARY
Table 3 is a summary of all the signals discussed in the
previous paragraphs.

Table 3 Signal Summary
Signal Name
Address Bus
Data Bus
Address Strobe
ReadlWrite
Upper and lower Data Strobes
Data Transfer .i\cknowledge
Bus Request
Bus Grant
Bus Grant Acknowledge
Interrupt Priority level
Bus Error
Reset
Halt
Enable
Valid Memory Address
Valid Peripheral Address
Function Code Output
Clock
Power Input
Ground

Mnemonic
AI -A23
Do - 015
AS

Input/Output
output
input/output
output

RiW

output

UDS, TI5S
DTACK
BR
BG
BGACK
IPlo, WL" IPl,
BERR
RES
HALT
E

output
input
input
output
input
input
input
input/output
input/output
output
output
input
output
input
input
input

VMA
VPA
FC o ,FC I ,FC 2
ClK
Vcc
Vss

* Open drain

108

Active State
high
high
low
read-high
write-low
low
low
low
low
low
low
low
low
low
high
low
low
high

Three State
yes
yes
yes
yes
yes
no
no
no
no
no
no
no'
no'
no
yes
no
yes

hjgh

no

-

-

---------------------------------------------------------------HD68000.HD68000Y
•

REGISTER DESCRIPTION AND DATA ORGANIZATION
The following paragraphs describe the registers and data
organization of the HD68000.

• OPERAND SIZE
Operand sizes are defmed as follows: a byte equals 8 bits,
a word equals 16 bits, and a long word equals 32 bits. The
operand size for each instruction is either explicitly encoded
in the instruction or implicitly defmed by the instruction
operation. All explicit instructions support byte, word or long
word operands. Implicit instructions support some subset of
all three sizes.

•

DATA ORGANIZATION IN MEMORY
Bytes are individually addressable with the high order byte
having an even address the same as the word, as shown in
Figure 9. The low order byte has an odd address that is one
count higher than the word address. Instructions and multibyte
data are accessed only on word (even byte) boundaries. If a
long word datum is located at address n (n even), then the
second word of that datum is located at address n + 2.
The data types supported by the HD68000 are: bit data,
integer data of 8, 16, or 32 bits, 32-bit addresses and binary
coded decimal data. Each of these data types is put in memory ,
as shown in Figure 10.

•

DATA ORGANIZATION IN REGISTERS
The eight data registers support data operands of 1, 8, 16,
or 32 bits. The seven address registers together with the active
stack pointer support address operands of 32 bits.

• BUS OPERATION
The following paragraphs explain control signal and bus
operation during data transfer operations, bus arbitration, bus
error and halt conditions, and reset operation.

DATA REGISTERS
Each data register is 32 bits wide. Byte operands occupy
the low order 8 bits, word operands the low order 16 bits, and
long word operands the entire 32 bits. The least significant bit
is addressed as bit zero; the most significant bit is addressed
as bit 31.
When a data register is used as either a source or destination
operand, only the appropriate low-orderportion is changed;
the remaining high-order portion is neither used nor changed.

• DATA TRANSFER OPERATIONS
Transfer of data between devices involve the following leads:
(I) Address Bus Al through A23
(2) Data Bus Do through 015
(3) Control Signals
The address and data buses are separate parallel buses used
to transfer data using an asynchronous bus structure. In all
cycles, the bus master assumes responsibility for deskewing
all signals it issues at both the start and end of a cycle. In
addition, the bus master is responsible for deskewing the acknowledge and data signals from the slave device.
The following paragraphs explain the read, write, and readmodify-write cycles. The indivisible read-modify-write cycle
is the method used by the HD68000 for interlocked multiprocessor communications.

ADDRESS REGISTERS
Each address register and the stack pointer is 32 bits wide
and holds a full 32 bit address. Address registers do not support
byte sized operands. Therefore, when an address register is used
as a source operand, either the low order word or the entire
long word operand is used depending upon the operation size.
When an -address register is used as the destination operand, the
entire register is affected regardless of the operation size. If the
operation size is word, any other operands are sign extended
to 32 bits before the operation is performed.
• STATUS REGISTER
The status register contains the interrupt mask (eitht levels
available) as well as the condition codes; extend (X), negative
(N), zero (Z), overflow (V), and carry (C). Additional status
bits indicate that the processor is in a trace (T) mode and/or
in a supervisor (S) state.

Status Register

Interrupt
Mask

Overflow

(NOTE) The terms _rtion and negation will be used extensively.
This Is done to avoid confusion when dealing with a mixture
of "active-low" and "active-high" signals. :Ibe term assert or
assertion Is used to indicate that a signal Is active or true independent of whether that voltage Is low or high. The term
negate or negation is used to indicate that a signal is inactive or
false.

Read Cvcle
During a read cycle, the processor receives data from memory or a peripheral device. The processor reads bytes of data
in all cases. If the instruction specifies a word (or double word)
operation, the processor reads both bytes. When the instruction
specifies byte operation, the processor uses an internal Ao bit to
determine which byte to read and then issues the data strobe
required for that byte. For bytes operations, when the Ao bit
equals zero, the upper data strobe is issued. When the Ao bit
equals one, the lower data strobe is issued. When the data is
received, the processor correctly positions it internally.
A word read cycle flow chart is given in Figure 11. A byte
read cycle flow chart is given in Figure 12. Read cycle timing is
given in Figure 13. Figure 14 details word and byte read cycle
operations. Refer to these illustrations during the following
detailed.

Carry

Unused. read as zero.

109

HD68000,HD68000Y----------------------------------------------------------------At state zero (SO) in the read cycle, the address bus (AI
through A23 ) is in the high impedance state. A function code
is asserted on the function code output line (FC o through FC 2 ).
The read/write (R/W) signal is switched high to indicate a read
cycle. One half clock cycle later, at state 1, the address bus is
released from the high impedance state. The function code
outputs indicate which address space that this cycle will operate
on.
In state 2, the address strobe (AS) is asserted to indicate that
there is a valid address on the address bus and the upper and
lower data strobe (UDS, LDS) is asserted as required. The memory or peripheral device uses the address bus and the address
strobe to determine if it has been selected. The selected device
uses the read/write signal and the data strobe to place its information on the data bus. Concurrent with placing data on the
data bus, the selected device asserts data transfer acknowledge

(DTACK).
Data transfer acknowledge must be present at the processor
at the start of state S or the processor will substitute wait states
for states Sand 6. State 5 starts the synchronization of the

returning data transfer acknowledge. At the end of state 6
(beginning of state 7) incoming data is latched into an internal
data bus holding register.
During state 7, address strobe and the upper and/or lower
data strobes are negated. The address bus is held valid through
state 7 to allow for static memory operation and signal skew.
The read/write signal and the function code outputs also remain
valid through state 7 to ensure a correct transfer operation. The
slave device keeps its data asserted until it detects the negation
of either the address strobe or the upper and/or.1ower data
strobe. The.slave device must remove its data and data transfer
acknowledge within one clock period of recognizing the negation of the address or data strobes. Note that the data bus might
not become free and data transfer acknowledge might not be
removed until state 0 or 1.
When address strobe· is negated, the slave device is released.
Note that a slave device must remain selected as long as address
strobe is asserted to ensure the correct functioning of the readmodify-write cycle.

110

- HD68000,HD68000Y
15

14

13

12

11

9

10

Syte 000000

S
7
6
WOrd.OOooOO

5

Word,OOOO02

Byte 000002

3

2

0

Byte 000003

<'

WOrdtFFFFE

Byte FFFFFE

4

SyteOOOOOl

Byte FFFFFF

Figure 9 Word Organization in Memory

7

15

14

13

::I~'
n
n+2

10

I nteger Data
1 Byte ~ S Bits
9
S
7
6

0

5

4

3

0

2

n+l

Byte 1
LSBI

Syte2

14

13

12

11

Byte 3

10

9

1 Word = 16 Bits
S
7
6

5

4

3

I

~'I

Word 1
Word 2

13

12

11

10

1 Long Word = 32 Bits
7
5
6
9
8

4

3

n+3

0

2

Word 0

15 14
MSS

1---

11

5

SyteO

n IMSB
n+2

15

12

Bit Data
1 Byte ~ S Bits
4
3
2

6

n+l
n+3
n+5

0

2

High Order
Long Word 0 - - - - - - - - - - - - - - - - - : . . . . - - - - - - - - - - Low Order
LSB

n+l
n+3
n+5

n+4
---Long Word 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

n+7

n+6

n+9

n+S
n+l0

- - -Long Word 2-- - - - - - - - - - - - - - - - - - - - - - - - - - - -

15

14

13

12

11

10

Addresses
1 Address = 32 Bits
9
8
7
6

5

4

3

2

n+11

0

n MSB
High Order
- - Address 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - n+2
low Order
LSB

n+3

n+4

n+5
- - Address 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

n+6

n+8

__ .Address2. __________________________ - - - -

n+l

n+7
n+9
n+l1

n+l0
MSB = Most Significant Bit
LSB = Least Significant Bit

n

n+2

15 14 13
MSD
BCDO

12

Decimal Data
2 Binary Coded Decimal Digits
11 10
9 'S
7
6
BCDI

BCD4

LSD

BCD5

= 1 Byte
5

4

2

1

0

BCD3

n+l

SCD6

BCD7

n+3

..

MSD = Most S,gnificant DIgIt
LSD = Least Significant Digit

Figure 10 Data Organization in Memory

111

3

BCD2

HD68000,HD68000Y------------------------------BUS MASTER

1)
2)
3)
4)
5)

SLAVE

BUS MASTER

11
2)
3)
4)
5)

Address Device
Set R!W to Reed
Place Function Code on FC. - FC.
Place Address on AI - An
Assert Address Strobe (AS)
Assert Upper Data Strobe (iJi5S) or Lower
Data Strobe (lOS)

SLAVE

Address Device
Set R/Wto Read
Place Function Code on FC. - FC2
Place Address on AI - A..
Assert Addre•• Strobe (AS)
Assert Upper Data Strobe (iJDS) and Lower Data Strobe (lOS) (besed on A.)

I

I
Input Data
1) Decode Address
2) Place Data on D. - 0, or D. - DIS (based
on UDS or lOS)
3) Assert Data Transfer Acknowledge

Input Data
1) Decode Address
21 Place Data on D. - DIS
3) Assert Data Transfer Acknowledge
(DTACKI

(i5fACi()

l

Acquire Data
Acquire Data
1) Latch Data
2) Negate ~ and IDS
3) Negate~

1) latch Data
2) Negate ~ or IDS
3) Negate AS

1

~

Terminate Cycle
1) Remove Data from D. - 0, or D. - DIS
2) Negate DTACK

Terminate Cycle
11 Remove Data from D. - DIS
2) Negate DTACK

r

r

Start Next Cycle

Start Next Cycle

Figure 11 Word Read Cycle Flow Chart

so

Figure 12 Byte Read Cycle Flow Chart

S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 w w w

w S5 S6 S7

ClK

ASI~~~----~~~------~~~------------~~
\
~------------~~
~______-JI
UDS /
\
LOS /
\
I

Figure 13 Read and Write Cycle Timing Diagram

112

-----------------------------------------------------------------HD68000,HD68000Y

ClK
AI

H

...... A t3

AS

I
lOS I
R/W

\
\

DTACK

J

0 8 -DIS

:J

D. -0,
FC. -FC,

I
I
I

;---\

UDS

=>

\

I

\

I

\

;---\

<

>
)

(

::::x
f- -- -- Word Read -

-

+---

I

rr-

\
\

I

I

\

r-

<

(

>

X

• Internal Signal Only

>-

H

A.'

x::=

X
-Odd Byte Read- -

+ --

Even Byte Read

---1

Figure 14 Word and Byte Read Cycle Timing Diagram

Write Cycle

During a write cycle, the processor sends data to memory
or a peripheral device_ The processor writes bytes of data in
all cases_ If the instruction specifies a word operation, the processor writes both bytes. When the instruction specifies a byte
operation, the processor uses an internal Ao bit to determine
which byte to write and then issues the data strobe required
for that byte. For byte operations, when the Ao bit equals zero,
the upper data strobe is issued. When the Ao bit equals one,
the lower data strobe is issued. A word write cycle flow chart is
given in Figure 15. A byte write cycle flow chart is given in
Figure 16. Write cycle timing is given in Figure 13. Figure 17
details word and byte write cycle operation. Refer to these
illustrations during the following detailed discussion.
At state zero (SO) in the write cycle, the address bus (AI
through A23 ) is in the high impedance state. A function code is
asserted on the function code output line (FC o through FC 2 ).
(NOTE) The read/write (R/W) signal remains high until state 2 to prevent bus conflicts with preceding read cycles. The data bus is
not driven until state 3.

One half clock later, at state 1, the address bus is released
from the high impedance state. The function code outputs
indicate which address space that this cycle will operate on.
In state 2, the address strobe (AS) is asserted to indicate
that there is a valid address on the address bus. The memory
or peripheral device uses the address bus and the address strobe
to determine if it has been selected. During state 2, the read/
write signal is switched low to indicate a write cycle. When
external processor data bus buffers are required, the read/write
line provides sufficient directional control. Data is not asserted
during this state to allow sufficient turn around time for external data buffers (if used). Data is asserted onto the data bus
during state 3.
In state 4, the data strobes are asserted as required to indicate that the data bus is stable. The selected device uses the

read/write signal and the data strobes to take its information
from the data bus. The selected device asserts data transfer
acknowledge (DTACK) when it has successfully stored the data.
Data transfer acknowledge must be present at the processor
at the start of state 5 or the processor will substitute wait states
for states 5 and 6. State 5 starts the synchronization of the
returning data transfer acknowledge.
During state 7, address strobe and the upper and/or lower
data strobes are negated. The address and data buses are held
valid through state 7 to allow for static memory operation and
signal skew. The read/write signal and the function code outputs
also remain valid through state 7 to ensure a correct transfer
operation. The slave device keeps its data transfer acknowledge
asserted until it detects the negation of either the address strobe
or the upper and/or lower data strobe. The slave device must
remove its data transfer acknowledge within one clock period
after recognizing the negation of the address or data strobes.
Note that the processor releases the data bus at the end of state
7 but that data transfer acknowledge might not be removed
until state 0 or I. When address strobe is negated, the slave
device is released.

Read-Modify-Write Cycle

The read-modify-write cycle performs a read, modifies the
data in the arithmetic-logic unit, and writes the data back to the
same address. In the HD68000 this cycle is indivisible in that
the address strobe is asserted throughout the entire cycle. The
test and set (TAS) instruction uses this cycle to provide meaningful communication between processors in a multiple processor environment. This instruction is the only instruction that
uses the read-modify-write cycle and since the test and set instruction only operates on bytes, all read-modify-write cycles
are byte operations. A read-modify-write cycle flow chart is
given in Figure 18 and a timing diagram is given in Figure 19.
Refer to these illustrations during the following detailed discus113

HD68000.HD68000Y--------------------------------------------~~--------------

sions.
At state zero (SO) in the read-modify-write cycle, the address
bus (AI through Al3 ) is in the high impedance state. A function
code is asserted on the function code output line (FC o through
FC l ). The read/write (R/'ii) signal is switched high to indicate
a read cycle. One half clock cycle later, at state 1, the address
bus is released from the high impedance state. The function
code outputs indicate which address space that this cycle will
operate on.
In state 2, the address strobe (AS) is asserted to indicate that
there is a valid address on the address bus and the upper or
lower data strobe (UDS, LOS) is asserted as required. The memory or peripheral device uses the address bus and the address
strobe to determine if it has been selected. The selected device
uses the read/write signal and the data strobe to place its infor·
mation on the data bus. Concurrent with placing data on the
data bus, the selected device asserts data transfer acknowledge
(DTACK).
Data transfer acknowledge must be present at the processor
at the start of state 5 or the processor will substitute wait stat!ls
for states 5 and 6. State 5 starts the synchronization of the
returning data transfer acknowledge. At the end of state 6
(beginning of state 7) incoming data is latched into an internal
data bus holding register.
During state 7, the upper or lower data strobe is negated.
The address bus, address strobe, read/write signal, and function
code outputs remain as they were in preparation for the write'
portion of the cycle. The slave device keeps its data asserted
until it detects the negation of the upper or lower data strobe.
The slave device must remove its data and data transfer acknowledge within one clock period of recognizing the negation
of the data strobes. Internal modification of data may occur
from state 8 to state 11.
(NOTE) The read/write signal remains high until state 14 to prevent bus
conflicts with the preceding read portion of the cycle and the
data bus is not asserted by the processor until state 15.

In state 14, the read/write signal is switched low to indicate
a write cycle. When external processor data bus buffers are
required, the read/write line provides sufficient directional
control. Data is not asserted during this state to allow sufficient
turn around time for external data buffers (if used). Data is
asserted onto the data bus during state 15.
In state 16, the data strobe is asserted as required to indicate
that the data bus is stable. The selected device uses the read/
write signal and the data strobe to take its information from the
data bus. The selected device asserts data transfer acknowledge
(DTACK) when it has successfully stored its data.
Data transfer acknowledge must be present at the processor
at the start of state 17 or the processor will substitute wait
states for states 17 and 18. State 17 starts the synchronization

of the returning data transfer acknowledge for the write portion
of the cycle. The bus interface circuitry issues requests for
subsequent internal cycles during state 18.
During state 19, address strobe and the upper or lower data
strobe is negated. The address and data buses are held valid
through state 19 to allow for static memory operation and
signal skew. The read/write signal and the function code outputs
also remain valid through state 19 to ensure a correct transfer
operation. The slave device keeps its data transfer acknowledge
asserted until it detects the negation of either the address strobe
or the upper or lower data strobe. The slave device must remove
its data transfer acknowledge within once clock period after
recognizing the negation of the address or data strobes. Note
that the processor releases the data bus at the end of state 19
but that data transfer acknowledge might not be removed until
state 0 or 1. When address strobe is negated the slave device is
released.

• BUS ARBITRATION
Bus arbitration is a technique used by master-type devices
to request, be granted, and acknowledge bus mastership. In its
simples form, it consists of:
(I) Asserting a bus mastership request.
(2) Receiving a grant that the bus is available at the end of
the current cycle.
(3) Acknowledging that mastership has been assumed.
F:igure 20 is a flow chart showing the detail involved in a
request from a single device. Figure 21 is a timing diagram
for the same operations. This technique allows processing of
bus requests during data transfer cycles.
The timing diagram shows that the bus request is negated
at the time that an acknowledge is asserted. This type of operation would be true for a system consisting of the processor
and one device capable of bus mastership. In systems having
a number of devices capable of bus mastership, the bus request
line from each device is wire ORed to the processor. In this
system, it is easy to see that there could be more that one bus
request being made. The timing diagram shows that the bus
grant signal is negated a few clock cycles after the transition
of the acknowledge (BGACK) signal.
However, if the bus requests are still pending, the processor
will assert another bus grant within a few clock cycles after
it was negated. This additional assertion of bus grant allows
external arbitration circuitry to select the next bus master
before the current bus master has completed its requirements.
The following paragraphs provide additional information about
the three steps in the arbitration process.

114

-------------------------------HD68000,HD68000Y
BUS MASTER

SLAVE

BUS MASTER

SLAVE

Address Device
1)

2)
3)
4)

5)
6)

1) Place Function Code on FC. - FC,

Address Device
Place Function Code on FC. - FC,
Place Address on A, - Au
Assert Address strobe (AS)
Set R/W to Write
Place Data on D. - 0"
Assert Upper Data Strobe (iJEiS) and
Lower Data Strobe ([OS)

2) Place Address on AI"'" Au
3) Assert Add ress Strobe (AS)
4) Set R/iN to Write
5) Place Data on Do ..... 0, or Os .....

DIS (according
to Au)
6) Assert Upper Data Strobe ('liDS) or lower
Data Strobe ([OS) (based on A.)

1

1

Input Data
1) Decode Address
2) Store Data on D. - 0, if [[is is asserted
Store Data on D. - 0" if ODS is asserted
3) Assert Data Transfer Acknowledge
IDTACK)

Input Data
1) Decode Address
2) Store Data on D. - 0"
3) Assert Data Transfer Acknowledge
(DTACJ<)

1)
2)
3)
4)

~

Terminate Output Transfer
Negate UDS and lOS
Negate AS
Remove Data from D. - 0"
Set R/W to Read

1)
2)
3)
4)

I

Terminate Output Transfer
Negate iJDS and lOS
Negate AS
Remove Data from D. - 0, or D. - DIS
Set RIW to Read

1

Terminate Cycle
1)

Terminate Cycle
1) Negate D'fACK

Negate~

I
Start Next Cycle

Start Next Cycle

Figure 15 Word Write Cycle Flow Chart

Figure 16 Byte Write Cycle Flow Chart

SO SI S2 S3 54 55 56 57 SO SI 52 53 54 55 S6 S7 50 SI S2 53 54 55 S6 57
ClK

A."

A5~

\
\

UDS
lD5

I
I
I

RIWJ\

\

DTACK
D. -0 15

0.-0,
FC. -FC,

)
)

<

:x

"Internal Signal Only

I- - - - Word Write -

--

\

\
\

1\
I
>
>
X

(

I

\

\
<
(

+ --

Odd Byte Write - - -

I

1\
I
>
>
X

<

<

r

r

~
~

>

+ --

Even Byte Write - -

Figure 17 Word and Byte Write Cycle Timing Diagram

115

\

r-

r-

--I

HD68000,HD68000Y------------------------------BUS MASTER
11

21
31
41
51

SLAVE

Add.... Device
Set R/W to Read
Place Function Code on FC. - FC2
Place Address on AI - Au
Assert Add .... Strobe (ASI
Assert Upper Data Strobe (UDSI or
Lower Data Strobe (~l

Input Data
11 Decode Add ....
21 Place Data on O. -0, or O. -0 ..
31 Assert Data Transfer Acknowledge
(oTACKI

i

Acquire Data
11 Latch Data
21 Negate tm'S" or ~
31 Start Data Modification

Terminata Cycle
1) Remove Data from O. - 0, or o. - 0 ..

21

Negate~

i

Start Output Transfer
11 Set R/W to Writa
21 Place oeta on O. - 0, or O. - 0 ..
31 Assert Upper Data Strobe (UoSl or Lower
Data Strobe (rDJ)

11 Strobe Data on O. - 0, or O. - 0 ..

21 Assert Data Transfer Acknowledge
(oTACKI

Termlnata Output Transfer
Nagata OM or 1:DI
21 NegateAS
31 Remove Data from O. -0, or O. -0 ..
41 Set R/W to Reed
1')

Termlnata Cycle
11 Negate~

I
Start Next Cycle

Figure 18 Read·Modify-Write Cycle Flow Chart

CLK

Uos or res

'~______~============~
__JI
----"'\
I
'\.. __

..J,r---

R/W-----=======~-,....~~~~------~\==~--~r--

~ ---~,

o. - 0, orO. -0..
FC.- FC2

'r__

I

::x______________________________________x:::
(

)

r-- ----------

(

Indivisible Cycle - - - - - - - - - -

Figure 19 Read-Modify·Write Cycle Timing Diagram

116

}---

~

-----------------------------------------------------------------HD68000,HD68000Y
PROCESSOR

REQUESTING OEVICE

Requesting the Bus

Request the Bus
1) Assert Bus Request (BR)

I
Grant Bus Arbitration
1) Assert Bus Grant (BGI
~I--------------,

~

1)
2)
3)
4)

Acknowledge Bus Mastersh ip
External arbitration determines next bus
master
Next bus master waits for current cvcle to
complete
Next bus master asserts Bus Grant
Acknowledge (BGACK) to become new
master
Bus master negates BR

I
Terminate Arbitration
1) Negate BG (and wait for BGACK to be
negated)

Operate as Bus Master
11 Perform Data Transfers (Read and Write
cycles) according to the same rules the processor uses.

External devices capable of becoming bus masters request
the bus by asserting the bus request (BR) signal_ This is a wire
ORed signal (although it need not be constructed from open
collector devices) that indicates to the processor that some
external device requires control of the external bus_ The processor is effectively at a lower bus priority level that the external device and will relinquish the bus after it has completed
the last bus cycle it has started_
When no acknowledge is received before the bus request
signal goes inactive, the processor will continue processing
when it detects that the bus request is inactive _ This allows
ordinary processing to continue if the arbitration circuitry
responded to noise inadvertently.
Receiving the Bus Grant

The processor asserts bus grant (BG) as soon as possible_
Normally this is immediately after internal synchronization.
The only exception to this occurs when the processor has made
an internal decision to execute the next bus cycle but has not
progressed far enough into the cycle to have asserted the address
strobe (AS) signal. In this case, bus grant will not be asserted
until one clock after address strobe is asserted to indicate to
external devices that a bus cycle is being executed.
The bus grant signal may be routed through a daisy-(;hained
network or through a specific priority-encoded network. The
processor is not affected by the external method of arbitration
as long as the protocol is obeyed.
Acknowledgement of Mastership

Release Bus Mastership
11 Negate BGACK

Re-Arbitrate or Resume Processor
Operation

Figure 20 Bus Arbitration Cycle Flow Chart

Upon receiving a bus grant, the requesting device waits
until address strobe, data transfer acknowledge, and bus grant
acknowledge are negated before issuing its own BGACK. The
negation of the address strobe indicates that the previous
master has completed its cycle, the negation of bus grant
acknowledge indicates that the previous master has released
the bus. (While address strobe is asserted no device is allowed
to "break into" a cycle.) The negation of data transfer acknowledge indicates the previous slave has terminated its connection
to the previous master. Note that in some applications data

CLK

AS
LDS/UDS
R/W

DTACK
Do -015
FC. -FC,
BR
~

I ~--------~\~==~-----~I
I r---------~\====~~I
I
,"----+--+- - - --+---

\

BGAcK
Processor - -

,

DMA Device

Figure 21

Processor - - -

Bus Arbitration Cycle Timing Diagram

117

DMA Device - - - -

HD68000,HD68000Y----------------------------------------~--------------------

transfer acknowledge might not enter into this function. General purpose devices would then be connected such that they
were only dependent on address strobe. When bus grant acknowledge is issued the device is bus master until it negates
bus grant acknowledge. Bus grant acknowledge should not be
negated until after the bus cycle{s) is (are) completed. Bus
mastership is terminated at the negation of bus grant acknowledge.
The bus request from the granted device should be dropped after bus grant acknowledge is asserted. If a bus request
is still pending, another bus grant will be asserted within a few
clocks of the negation of bus grant. Refer to Bus Arbitration
Control section. Note that the processor does not perform
any external bus cycles before it re-asserts bus grant.
•

BUS ARBITRATION CONTROL
The bus arbitration control unit in· the HD68000 is implemented with a fmite state machine. A state diagram of this
machine is shown in Figure 22. All asynchronous signals to the
HD68000 are synchronized before being used internally. This
synchronization is accomplished in a maximum of one cycle
of the system clock, assuming that the asynchronous input
setup time (#47) has been met (see Figure 23). The input
signal is sampled on the falling edge of the clock and is valid
internally after the next falling edge.
As shown in Figure 22, input signals labeled R and A are
internally synchronized on the bus request and bus grant

acknowledge pins respectively. The bus grant output is lebeled
G and the internal three-state control signal T. If T is true, the
address, data, function code line, and control buses are placed
in a high-impedance state when AS is negated. All signals are
shown in positive logic (active high) regardless of their true
active voltage level.
State changes (valid outputs) occur on the next rising edge
after the internal signal is valid.
A timing diagram of the bus arbitration sequence during a
processor bus cycle is shown in Figure 24. The bus arbitration
sequence while the bus is inactive (i.e., executing internal
operations such as a multiply instruction) is shown in Figure 25.
If a bus request is made at a time when the MPU has already
~un a bus cycle but AS has not been asserted (bus state SO),
BG will not be asserted on the next rising edge. Instead, BG will
be delayed until the second rising edge following it's internal
assertion. This sequence is shown in Figure 26.
• BUS ERROR AND HALT OPERATION
In a bus architecture that requires a handshake from an external device, the possibility exists that the handshake might not
occur. Since different systems will require a different maximum
response time, a bus error input is provided. External circuitry
must be used to determine the duration between address strobe
and data transfer acknowledge before issuing a bus e~ror sign;d.
When a bus error signal is received, the processor has two
options initiate a bus error exception sequence or try running
the bus cycle again.

RA

1

Internal Signal v a l i d - - - - - - - - .
External Signal samPled.

+

ClK

BR (Externall-----"

@
BR U n t e r n a l l - - - - - - - - - - - - t - ,

Asychronous

Input Delay'

• This delay time is equal to parameter #33, tCHGL'
RAGT•
X•

Bus Request Internal
Bus Grant Acknowledge Internal
Bus Grant
Three-State Control to Bus Control logic
Don't Care

Figure 23 Timing Relationship of External Asynchronous
I nputs to I nternlll Signals

• State machine will not changa state if bus is in SO. Refer to
BUS ARBITRATION CONTROL for additional information.

Figure 22 State Diagram of HD68000 Bus
Arbitration Unit

118

-----------------------------------------------------------------HD68000,HD68000Y

CYClefl

Bus released from three state and
Processor starts next bus

BGACK negated internalll
BGACK sampled
BGACK negated

ClK
50 51 52 53 54 55 56 57 50 51

50 51 52 53 54 55 56 57

BR - - - - - - - ,

/

\

A. -Au

~

BG=========~~~~~S\:::~=~--~I

BGACK

_ _ _...J/

( )

(

\~ _ _ __JI'--------------~~

A5

U05

\

I'

~

l05

\

f"'\

~

___~I

r---r----

-=:::::x~~~~~~~)======~(
RtW =
,
, ~~~~~C~
~\<======/~------------------------__~\~:c====:J;---o. r---

FC.-FC,

OTACK
0.. _____________

..

( )

_I"

Processor

Alternate Bus Master

(

_I..

Processor

..

Figure 24 Bus Arbitration During Processor Bus Cycle

I

.~ ....... ,~ ~'" -~, ,-.~ ow ,~",'.
BGACK negated

BR valid internal

BR sampled

BR asserted
ClK
W~~~S4~~D

W~~~54

I

\

BR

BG-------------~=======\------J

\

I

\

BGACK

I

,
--<[~====;t:====~=========~(~~=
I
~

A5~

A.-A,.

__________________
U05~~=====~fl---------~~----------------~~
l05~

FC. -FC,

Ir----------~

:x

)

~~

(

RtW-------------~'----------~----OTACK
0.-0 ..

\

I

'---

-------:----~::::==}_--~~~~------------::
__~:_~_._------------~~~::
Processor
Bus Inactive
Alternate Bus Master
Processor

-

-I"

"I-

Figure 25 Bus Arbitration with Bus Inactive

119

"I"

HD68000.HD68000Y--------------------------------------------------------------

SA,

so

I

BG

I

\

\

BGACK
A,-A..

<

A8
U08

iJ5S
FC. -Fe.

SO 81 82 S3 S4 85 56 87 SO 81

81 82 83 S4 S5 56 87

=:J<

I

>

<

I'
I'

\
\
\

~

I'
>

RiW

(

(

..

Processor

I

\
)

-I-

>-C

x::

I

I

\

0.-0"

I
I

r---""\

\

i5'i'ACK

I

r--"\

(
Altarnate Bus Master

-I-

Proceaor

>--•

Figure 26 Bus Arbitration During Processor Bus Cycle Special Case

Exception Sequence
When the bus error signal is asserted, the current bus cycle
is tenninated. If BERR is asserted before the falling edge of
S4, AS will be negated in S7 in either a read or write cycle.
As long as BERR remains asserted, the data and address buses
will be in the high-impedance state. When BERR is negated,
the processor will begin stacking for exception processing.
Figure 27 is a timing diagram for the exception sequence.
The sequence is composed of the following elements.
(1) Stacking,the program counter and status register
(2) Stacking the error information

(3) Reading the bus error vector table entry
(4) Executing the bus error handler routine
The stacking of the program counter and the status register
is the same as if an interrupt had occurred. Several additional
items are stacked when a bus error occurs. These items are used
to determine the nature of the error and correct it, if possible.
The bus error vector is vector number two located at address
5000008. The processor loads the new program counter from
this location. A software bus error handler routine is then
executed by the processor. Refer to EXCEPTION PROCESS·
ING for additional information.

120

-----------------------------------------------------------------HD6S000,HD6S000Y

Re-Running the Bus Cycle
When, during a bus cycle, the processor receives a bus error
signal and the halt pin is being driven by an external device,
the processor enters the re-run sequence. Figure 28 is a timing
diagram for re-running the bus cycle.
The processor terminates the bus cycle, then puts the address
and data output lines in the high-impedance state. The processor
remains "halted," and will not run another bus cycle until the
halt signal is removed by external logic. Then the processor
will re-run the previous bus cycle using the same address, the

same function codes, the same data (for a write operation), and
the same controls. The bus error signal should be removed at
least one clock cycle before the halt signal is removed.
(NOTE) The processor will not re-run a read-modify-write cycle. This
restriction is made to guarantee that the entire cycle runs correctly and that the write operation of a Test-and-Set operation
is performed without ever releasing AS. If BERR and HALT
are asserted during a read-modify-write bus cycle, a bus error
operation results.

ClK
AS ______\~----------------------------JI

loS/UoS

\

\

'--

/"'---

Rm

\

oTACK--------------------------------------------------~

::~::::~(~~~~~~~~~~~~~~~~~~2:::::j
::::::x:
BERR==~====================~\-------------~~==

(

0.-0"
FC. - FC,

HAlT-------------~==============~--L--Initiat~

r- Read

.
- - Response Fallure- -

-+-

.

- - - Bus Error oetectlon- - -

_1_

~

Initiate Bus
- - - - - - --Error Stacking

Figure 27 Sus Error Timing Diagram

\'-_ _ _~I
r-------------------------~\

~- - - - - Reed -

-

-

~- - - - - - - Halt- - - - - -

+- -- -

Figure 28 Re-Run Bus Cycle Timing Information

121

/~---

Rerun- -

--.\

HD68000,HD68000Y-------------------------------

The processor terminates the bus cycle, then puts the address, data and function code output lines in the high-impedance
state. The processor remains "halted," and will not run another
bus cycle until the halt signal is removed by external logic. Then
the processor will re-run the previous bus cycle using the same
address, the same function codes, the same data (for a write
operation), and the same controls. The bus error signal should
be removed before the halt signal is removed.
Halt Operation with No Bus Error

The halt input signal to the HD68000 perform a Halt/Run/
Single-Step function in a similar fashion to the HMCS6800
halt function. The halt and run modes are somewhat self explanatory in that when the halt signal is constantly active the
processor "halts" (does nothing) and when the halt signal is
constantly inactive the processor "runs" (does something).
The single-step mode is derived from correctly timed transitions on the halt signal input. It forces the processor to execute
a single bus cycle by entering the "run" mode until the processor starts a bus cycle then changing to the "halt" mode.
Thus, the single-step mode allows the user to proceed through
(and therefore debug) processor operations one bus cycle at a
time.
Figure 29 details the timing required for correct single-step
operations. Some care must be exercised to avoid harmful
interactions between the bus error signal and the halt pin
when using the single cycle mode as a debugging tool. This
is also true of interactions between the halt and reset lines
since these can reset the machine.
When the processor completes a bus cycle after recognizing
that the halt signal is active, most three-state signals are put
in the high-impedance state. These include:
(J) Address lines
(2) Data lines

This is required for correct performance of the re-run bus
cycle operation.
While the processor is honoring the halt request, bus arbitration performs as usual. That is, halting has no effect on bus
arbitration. It is the bus arbitration function that removes the
control signals from the bus.
The halt function and the hardware trace capability allow
the hardware debugger to trace single bus cycles or single instructions at a time. These processor capabilities, along with
a software debugging package, give total debugging flexibility.
Doubla Bus Faults

When a bus error exception occurs, the processor will attempt to stack several words containing information about
the state of the machine. If a bus error exception occurs during
the stacking operation, there have been two bus errors in a row.
This is commonly referred to as a double bus fault. When a
double bus fault occurs, the processor will halt. Once a bus
error exception has occurred, any bus error exception occurring
before the execution of the next instruction constitutes a double bus fault.
Note that a bus cycle which is re-run does not constitute a
bus error exception, and does not contribute to a double bus
fault. Note also that this means that as long as the external
hardware requests it, the processor will continue to re-run
the same bus cycle.
The bus error pin also has an effect on processor operation
after the processor receives an external reset input. The processor reads the vector table after a reset to determine the address to start program execution. If a bus error occurs while
reading the vector table (or at any time before the flfSt instruction is executed), the processor react,s as if a double bus fault
has occurred and it halts. Only an external reset will start a
halted processor.

ClK

AI-Au

lDS/UOS

RIW

\

OTACK
0.-0 ..
FC. -FC.
HALT

\1.-_ _ _--11
1
~-----------------~\
I~---1

\
\

AS

::x
I-- -

1

(

)

X

\
--Read- -

-

+- - - -

1
-Halt'- -

-

-+-- -

Figure 29 Halt Signal Timing Characteristics

122

-Read- - - . ,

----------------------------------------------------------------HD68000,HD68000Y

+5V
RUN/SINGLE STEP
HALT
(To Processor).

* OPEN COLLECTOR
DEVICE
SINGLE
STEP

a

STEP

K

~I----""

AS" (From Processor)
RESET

Figure 30 Simplified Single-Step Circuit

• THE RELATIONSHIP OF DTACK, BERR, AND HALT
In order to properly control termination of a bus cycle for a
re-run or a bus error condition, DTACK, BERR, and HALT
should be asserted and negated on the rising edge of the
H068000 clock. This will assure that when two signals are
asserted simultaneously, the required setup time (#47) for
both of them will be met during the same bus state.
This, or some equivalent precaution, should be designed
external to the HD68000. Parameter #48 is intended to ensure
this operation in a totally asynchronous system, and may be
ignored if the above conditions are met.
The preferred bus cycle terminations may be summarized
as follows (case numbers refer to Table 4):
Normal Termination: DTACK occurs first (case 1).
Halt Termination: HALT is asserted at same time, or
precedes DTACK (no BERR) cases 2 and 3.
Bus Error Termination: BERR is asserted in lieu of, at same
time, or preceding DTACK (case 4); BERR negated at same
time,orafterDTACK.
Re-Run Termination: HALT and BERR asserted at the
same time, or before DTACK (cases 6 and 7); HALT must be
negated at least I cycle after BERR. (Case 5 indicates BERR

may precede HALT which allows fully asynchronous assertion)"
Table 4 details the resulting bus cycle termination under
various combinations of control signal sequences. The negation of these same control signals under several conditions is
shown in Table 5 (DTACK is assumed to be negated normally in all cases; for best results, both DTACK and BERR should
be negated when address strobe is negated.)
Example A: A system uses a watch-dog timer to terminate
~ to un-populated address space. The timer asserts
DTACK and BERR simultaneously after timeo{)ut. (case 4)
Example B: A system uses error detection on RAM contents. Designer may (a) delay DTACK until data verified, and
return BERR and HALT simultaneously to re-run error cycle
(case 6), or if valid, return DTACK; (b) delay DTACK until
data verified. and return BERR at same time as DTACK if
data in error(case 4); (c) return D'fACK prior to data verification, as described in previous section. If data invalid, BERR is
asserted (case 1) in next cycle. Error.nandling software must
know how to recover error cycle.

* For the mask version 68000, HALT and BERR must be asserted at
tile same time.

123

HD68000,HD68000Y----------------------------------------------------------------Table 4 DTACK, BERR, HALT Assertion Results

Case No.

Control Signal

1

2

3
4

5
6
7

DTACK
BERR
HALT
DTACK
BERR
HALT
DTACK
BERR
HALT
DTACK
BERR
HALT
DTACK
BERR
HALT
DTACK
BERR
HALT
DTACK

BEAR
HALT

Asserted on Risi ng
Edge of State
N+2
N
S
A
NA
X
NA
X
S
A
NA
X
A
S
NA
A
NA
NA
A
S
X
X
A
S
NA
NA
NA
X
A
S
NA
A
X
X
A
S
A
S
NA
X
NA
A
S
A

Result

Normal cycle terminate and continue.

Normal cycle terminate and halt. Continue when HALT removed.
Normal cycle terminate and halt. Continue when HALT removed.

Terminate and take bus error trap.
Terminate and re-run*.

Terminate and re-run.

Terminate and re-run when HALT removed.

Legend:
•
N - The number of the current even bus state (e.g., 54, 56, etc.)
A - Signal is asserted in this bus state
N A - Signal is not asserted in this state
X - Don't care
S - Signal was asserted in previous state and remains asserted in this state

For the mask version 68000, unpredictable results, no re-run, no error
trap; usuallv traps to vector number O.

Table 5 BERR and HALT Negation Results
Conditions of
Termination in
Table A

Control Signal

Bus Error
Re-run
Re-run

RA[j

Normal

B'Elm'

Normal

•

BERR
HALT
BERR
HALT
BERR

HALT
BERR
HALT

Negated on Rising
Edge of State
N+2
N
or
or
or

•
•
••
•
•
•

•

Results - Next Cycle

••

Takes bus error trap.

•

or
or

Illegal sequence; usually traps to vector number O.
Re,runs the bus cycle.

•
•

May lengthen next cycle.

•

If next cycle is started it will be terminated as a bus error.

none

RESET OPERATION

The reset signal is a bidirectional signal that allows either the
processor or an external signal to reset the system. Figure 31
is a timing diagram for reset operations. Both the halt and reset
lines must be applied to ensure total reset of the processor.
When the reset and halt lines are driven by an external
device, it is recognized as an entire, system reset, including
the processor. The processor responds by reading the reset
vector table entry (vector unumber zero, address $000000)
and loads it into the supervisor stack pointer (SSP). Vector
table entry number one at address $000004 is read next and
loaded into the program counter. The processor initializes
the status register to an interrupt level of seven. No other

registers are affected by the reset sequence.
When a RESET sequence is executed, the processor drives
the reset pin for 124 clock pulses. In this case, the processor
is trying to reset the rest of the system. Therefore, there is
no effect on the internal state of the processor. All of the
processor's internal registers and the status register are unaffected by the execution of a RESET instruction. All external
devices connected to the reset line should be reset at the completion of the RESET instruction.
Asserting the Reset and Halt pins for 10 clock cycles will
cause a processor reset, except when Vee is initially applied
to the processor. In this case, an external reset must be applied
for 100 milliseconds.

124

------------------------------·-----------------------------------HD68000,HD68000Y

CLK
Plus 5' Volts

Vee

t

> 100 Millis.conds--!,...._ _ _ _ _ _ _ _ _ _ _ _ __

RES1~-------------------II~-----------------______________________

HALT

,~

~

1----1

t <4

Bus Cycl.s

(61

(21
(NOTESI
11 Internal start-up tim. 41 PC High r.ad in here
21 SSP High read in here 51 PC Low read in here
31 SSP Low read in here 61 First instruction fetched here.

Figure 31

Bus State Unknown:

~

All Control Signals Inactive.
Data Bus In Read Mode:

>--<

Reset Operation Timing Diagram

• PROCESSING STATES

• PRIVILEGE STATES

This section describes the HD68000 which are outside the'
normal processing associated with the execution of instructions.
The functions of the bits in the supervisor portion of the status
register are covered: the supervisor/user bit, the trace enable bit,
and the processor interrupt priority mask. Finally, the sequence
of memory references and actions taken by the processor on
exception conditions is detailed.
The HD68oo0 is always in one of three processing states:
normal, exception, or halted. The normal processing state is
that associated with instruction execution; the memory references are to fetch instructions and operands, and to store
results. A special case of the normal state is the stopped state
which the processor enters when a STOP instruction is executed. In this state, no further memory references are made.
The exception processing state is associated with interrupts,
trap instructions, tracing and other exceptional conditions.
The exception may be internally generated by an instruction
or by an unusual condition arising during the execution of
an instruction. Externally, exception processing can be forced
by an interrupt, by a bus error, or by a reset. Exception processing is designed to provide an efficient context switch so that
the processor may handle unusual conditions.
The halted processing state is an indication of catastrophic
hardware failure. For example, if during the exception processing of a bus error another bus error occurs, the processor
assumes that the system is unusable and halts. Only an external
reset can restart a halted processor. Note that a processor in the
stopped state is not in the halted state, nor vice versa.

The processor operates in one of two states of privilege:
the "user" state or the "supervisor" state. The privilege state
determines which operations are legal, is used by the external
memory management device to control and translate accesses,
and is used to choose between the supervisor stack pointer
and the user stack pointer in instruction references.
The privileges state is a mechanism for providing security
in a computer system. Programs should access only their own
code and data areas, and ought to be restricted from accessing
information which they do not need and must not modify.
The privilege mechanism provides security by allowing
most programs to execute in user state. In this state, the accesses are controlled, and the effects on other parts of the
system are limited. The operating system executes in the supervisor state, has access to all resources, and performs the overhead tasks for the user state programs.

PROCESSING STATES

NORMAL

INSTRUCTION
EXECUTION
(INCLUDING STOP)

EXCEPTION

INTERRUPTS
TRAPS
TRACING ETC.

HALTED

HARDWARE HALT
DOUBLE BUS FAULT

SUPERVISOR STATE

The supervisor state is the higher state of privilege. For
instruction execution, the supervisor state is determined by
the S-bit of the status register; if the S-bit is asserted (high),
the processor is in the supervisor state. All instructions can be
executed in the supervisor state. The bus cycles generated by
instructions executed in the supervisor state are classified as
supervisor references. While the processor is in the supervisor
privilege state, those instructions which use either the system
stack pointer implicitly or address register seven explicitly
access the supervisor stack pointer.
All exception processing is done in the supervisor state,
regardless of the setting of the S-bit. The bus cycles generated
during exception processing are classified as supervisor references. All stacking operations during exception processing use
the supervisor stack pointer.
USER STATE

The user state is the lower state of privilege. For instruction
execution, the user state is determined by the S-bit of the status
register; if the S-bit is negated (low), the processor is executing
instructions in the user state.
Most instructions execute the same in user state as in the
supervisor state. However, some instructions which have important system effects are made privileged. User programs
are not permitted to execute the STOP instruction, or the

125

HD68000,HD68000Y----------------------------------------------------------------RESET instruction. To ensure that a user program cannot
enter the supervisor state except in a controlled manner, the
instructions which modify the whole status register are privileged. To aid in debugging programs which are to be used as
operating systems, the move to user stack pointer (MOVE
USP) and move from user stack pointer (MOVE from USP)
instructions are also privileged.
The bus cycles generated by an instruction executed in
user state are classifred as user state references. This allows
an external memory management device to translate the address and to control access to protected portions of the address
space. While the processor is in the user privilege state, those
instructions which use either the system stack pointer implicitly, or address register seven explicitly, access the use stack
pointer.
PRIVILEGE STATE CHANGES

Once the processor is in the user state and executing instructions, only exception processing can change the privilege state.
During exception processing, the current setting of the S-bit
of the status register is saved and the S-bit is asserted, putting
the processing in the supervisor state. Therefore, when instruction execution resumes at the address specified to process the
exception, the processor is in the supervisor privilege state.
USER/SUPERVISOR MODES
TRANSITION ONLY MAY OCCUR
DURING EXCEPTION PROCESSING

•

EXCEPTION PROCESSING

Before discussing the details of interrupts, traps, and tracing,
a general description of exception processing is in order. The
processing of an exception occurs in four steps, with variations
for different exception causes. During the flIst step, a temporary copy of the status register is made, and the status register
is set for exception processing. In the second step the exception
vector is determined, and the third step is the saving of the
current processor context. In the fourth step a new context is
obtained, and the processor switches to instruction processing.
EXCEPTION VECTORS

Exception vectors are memory locations from which the
processor fetches the address of a routine which will handle
that exception. All exception vectors are two words in length
(Figure 32), except for the reset vector, which is four words.
All exception vectors lie in the supervisor data space, except
for the reset vector which is in the supervisor program space.
A vector number is an eight-bit number which, when multiplied
by four, gives the address of an exception vector. Vector numbers are generated internally or externally depending on the
cause of the exception. In the· case of interrupts, during the
interrupt acknowledge bus cycle, a peripheral provides an 8-bit
vector number (Figure 33) to the processor on data bus lines Do
through D7 • The processor translates the vector number into
a full 24-bit address, as shown in Figure 34. The memory
layout for exception vectors is given in Table 7.
As shown in Table 7, the memory layout is 512 words
long (1024 bytes). It starts at address 0 and proceeds through
address 1023. This provides 255 unique vectors; some of these
are reserved for TRAPS and other system functions. Of the
255, there are 192 reserved for user interrupt vectors. However,
there is no protection on the flISt 64 entries, so user interrupt
vectors may overlap at the discretion of the systems designer.
KINDS OF EXCEPTIONS

TRANSITION MAYBE MADE BY:
RTE; MOVE, ANDI, EORI TO STATUS WORD

REFERENCE CLASSIFICATION

When the processor makes a reference, it classifies the kind
of reference being made, using the encoding on the three function code output lines. This allows external translation of addresses, control of access, and differentiation of special processor states, such as interrupt acknowledge. Table 6 lists the
classification of references.

Exceptions can be generated by either internal or external
causes. The externally generated exceptions are the interrupts
and the bus error and reset requests. The interrupts are requests
from peripheral devices for processor action while the bus
error and reset inputs are used for access control and processor
restart. The internally generated exceptions come from instructions, or from address error or tracing. The trap (TRAP), trap
on overflow (TRAPV), check register against bounds (CHK)
and divide (DIY) instructions all can generate exceptions as
part of their instruction execution. In addition, illegal instructions, word fetches from odd addresses and privilege violations
cause exceptions. Tracing behaves like a very high priority,
internally generated interrupt after each instruction execution.

Table 6 Reference Classification
EXCEPTION PROCESSING SEQUENCE

Function Code Output
FC 1
FC o
FC z
0
0
0
1
0
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
0
1
1
1

Reference Class
(Unassigned)
User Data
User Program
(Unassigned)
(Unassigned)
Supervisor Data
Supervisor Program
Interrupt Acknowledge

Exception processing occurs in four identiftable steps. In
the flIst step, an internal copy is made of the status register.
After the copy is made, the S-bit is asserted, putting the processor into the supervisor privilege state. Also, the T-bit is
negated which will allow the exception handler to execute
unhindered by tracing. For the reset and interrupt exceptions,
the interrupt priority mask is also updated.
In the second step, the vector number of the exception is
determined. For interrupts, the vector number is obtained by
a processor fetch, classified as an interrupt acknowledge. For
all other exceptions, internal logic provides the vector number.
This vector number is then used to generate the address of
the exception vector.
126

-----------------------------------------------------------------HD68000,HD68000Y

Word 0

New Program Counter (High)

AO=O,Al=O

Word 1

New Program Counter (Low)

AO=O,Al=1

Figure 32 Exception Vector Format
015

0807

DO

Ignored
Where:
v7 is the MSB of the Vector Number
vO is the LSB of the Vector Number
Figure 33 Peripheral Vector Number Format
A23

Al0 A9 A8 A7 A6 A5 A4 A3 A2 Al AO
All Zeroes
Figure 34 Address Translated From 8-Bit Vector Number
Table 7

Vector
Number(s)
0

2
3
4
5
6
7
8
9
10
11
12"
13"
14"
15
16 - 23"
24
25
26
27
28
29
30
31
32-47
48-63"
64-255

Dec
0
4
8
12
16
20
24
28
32

36
40
44
48
52
56
60
64
95
96
100
104
108
112
116
120
124
128
191
192
255
256
1023

Exception Vector Assignment

Address
Hex
000
004
008
OOC
010
014
018
01C
020
024
028
02C
030
034
038
03C
04C
05F
060
064
068

06C
070
074
078
07C
080
OBF

oeo
OFF
100
3FF

Space
SP
SP
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO

Assignment
Reset: Initial SSP
Reset: Initial PC
Bus Error
Address Error
Illegal Instruction
Zero Divide
CH K Instruction
TRAPV Instruction
Privilege Violation
Trace
Line 1010 Emulator
Line 1111 Emulator
(UnaSSigned, reserved)
(UnaSSigned, reserved)
(Unassigned, reserved)
Uninitialized Interrupt Vector

SO

(Unassigned, reserved)

SO
SO
SO
SO
SO
SO
SO
SO

Spurious Interrupt
Level 1 Interrupt Autovector
Level 2 Interrupt Autovector
Level 3 Interrupt Autovector
Level 4 Interrupt Autovector
Level 5 Interrupt Autovector
Level 6 Interrupt Autovector
Level 7 Interrupt Autovector

SO

TRAP Instruction Vectors

SO

(Unassigned, reserved)

SO

User Interrupt Vectors

SP: Supervisor program, SO: Supervisor data
• Vector numbers 12, 13, 14, 16 through 23 and 48 through 63 are reserved for future enhancements by Hitachi.

No user peripheral devices should be assigned these numbers.

127

HD68000,HD68000Y

The third step is to save the current processor status, except for the reset exception. The current program counter
value and the saved copy of the status register are stacked
using the supervisor stack pointer. The program counter value
stacked usually points to the next unexecuted instruction,
however for bus error and address error, the value stacked
for the program counter is unpredictable, and may be incremented from the address of the instruction which caused the

error. Additional information defining the current context is
stacked for the bus error and address error exceptions.
The last step is the same for all exceptions. The new program
counter value is fetched from the exception vector. The processor then resumes instruction execution. Then instruction
at the address given in the exception vector is fetched, and
normal instruction decoding and execution is started.

Figure 35 Exception Processing Sequence (Not Reset)
128

--- -----------------------------------------------------------------HD68000.HD68000Y
MULTIPLE EXCEPTIONS
These paragraphs descnbe the processing which occurs
when multiple exceptions arise simultaneously. Exceptions
can be grouped according to their occurrence and priority. The
Group 0 exceptions are reset, bus error, and address error.
These exceptions cause the instruction currently being executed
to be aborted, and the exeception processing to commence
within two clock cycles. The Group I exceptions are trace and
interrupt, as well as the privilege violations and illegal instructions. These exceptions allow the current instruction to execute
to completion, but preempt the execution of the next instruction by forcing exception processing to occur (privilege violations and illegal instructions are detected when they are the
next instruction to be executed). The Group 2 exceptions
occur as part of the normal processing of instructions. The
TRAP, TRAPV, CIIK, and zero divide exceptions are in this
group. For these exceptions, the normal execution of an instruction may lead to exception processing.
Group 0 exceptions have highest priority, while Group 2
exceptions have lowest priority. Within Group 0, reset has
highest priority, followed by address error and then bus error.
Within .Group I, trace has priority over external interrupts,
which in tum takes priority over illegal instruction and privilege violation. Since only one instruction can be executed at
a time, there is no priority relation within Group 2.
The priority relation between two exceptions determines
which is taken, or taken fust, if the conditions for both arise
simultaneously. Therefore, if a bus error occurs during a TRAP
instruction, the bus error takes precedence, and the TRAP
instruction processing is aborted. In another example, if an
interrupt request occurs during the execution of an instruction
while the T-bit is asserted, the trace exception has priority,
and is processed fust. Before instruction processing resumes,
however, the interrupt exception is also processed, and instruction processing commences fmally in the interrupt handler
routine. A summary of exception grouping and priority is given
in Table 8.
Table 8 Exception Grouping and Priority
Group

0

1

2

Exception
Reset
Address Error
Bus Error
Trace
Interrupt
Illegal
Privilege
TRAP. TRAPV
CHK.
Zero Divide

Processing
Exception processing begins
within two clock cycles.
Exception processing begins
before the next instruction

RECOGNITION TIMES OF EXCEPTIONS.
HALT. AND BUS ARBITRATION
END OF A CLOCK CYCLE
RESET
END OF A BUS CYCLE
ADDRESS ERROR
BUS ERROR
HALT
BUS ARBITRATION
END OF AN INSTRUCTION CYCLE
TRACE EXCEPTION
INTERRUPT EXCEPTIONS
ILLEGAL INSTRUCTION
UNIMPLEMENTED INSTRUCTION
PRIVILEGE VIOLATION
WITHIN AN INSTRUCTION CYCLE
TRAP. TRAPV
CHK
ZERO DIVIDE

• EXCEPTION PROCESSING DETAILED DISCUSSION
Exceptions have a number of sources, and each exception
has processing which is peculiar to it. The following paragraphs
detail the sources of exceptions, how each arises, and how each
is processed.
RESET
The reset input provides the highest exception level. The
processing of the reset signal is designed for system initiation,
and recovery from catastrophic failure. Any processing in progress at the time of the reset is aborted and cannot be recovered.
The processor is forced into the supervisor state, and the trace
state is forced off. The processor interrupt priority mask is set
at level seven. The vector number is intema11y generated to
reference the reset exception vector at location 0 in the supervisor program space. Because no assumptions can be made about
the validity of register contents, in particular the supervisor
stack pointer, neither the program counter nor the status
register is saved. The address contained in the rust two words
of the reset exception vector is fetched as the initial supervisor
stack pointer, and the address in the last two words of the
reset exception vector is fetched as the initial program counter.
Finally, instruction execution is started at the address in the
program counter. The power-up/restart code should be pointed
to by the initial program counter.
The RESET instruction does not cause loading of the reset
vector, but does assert the reset line to reset external devices.
This allows the software to reset the system to a known state
and then continue processing with the next instruction.

Exception processing is started by
normal instruction execution

129

---HD68000.HD68000Y------------------------------------~---------------------------

Yes
>------to Address Error or Bus Error Exception Processing

Figure 36 Reset Exception Processing

INTERRUPTS

Seven levels of interrupt priorities are provided. Devices
may be chained externally within interrupt priority levels,
allowing an unlimited number of peripheral devices to interrupt the processor. Interrupt priority levels are numbered
from one to seven, level seven being the highest priority. The
status register contains a three-bit mask: which indicates the
current processor priority, and interrupts are inhibited for
all priority levels less than or equal to the current processor
priority.
An interrupt request is made to the processor by encoding
the interrupt request level on the interrupt request lines; a
zero indicates no interrupt request. Interrupt requests arriving
at the processor do not force immediate exception processing,

but are made pending. Pending interrupts are detected between
instruction executions. If the priority of the pending interrupt
is lower than or equal to the current processor priority, execution continues with the next instruction and the interrupt
exception processing is postponed. (The recognition of level
seven is slightly different, as explained in a following paragraph.)
If the priority of the pending interrupt is greater than the
current processor priority, the exception processing sequence
is started. First a copy of the status register is saved, and the
privilege state is set to supervisor, tracing is suppressed, and
the processor priority level is set to the level of the interrupt
being acknowledged. The processor fetches the vector number
from the interrupting device, classifying the reference as an
interrupt acknowledge and displaying the level number of
130

-----------------------------------------------------------------HD68000,HD68000Y

the interrupt being'acknowledged on the address bus. If external
logic requests an automatic vectoring, the processor internally
generates a vector number which is determined by the interrupt
level number. If external logic indicates a bus error, the interrupt is taken to be spurious, and the generated vector number
references the spurious interrupt vector. The processor then
proceeds with the usual exception processing, saving the program counter and status register on the supervisor stack. The
saved value of the program counter is the address of the instruction which would have been executed had the interrupt not
been present. The content of the interrupt vector whose vector
number was previously obtained is fetched and loaded into the
program counter, and normal instruction execution commences
in the interrupt handling routine. A flow chart for the interrupt
acknowledge sequence is given in Figure 37, a timing diagram
is given in Figure 38, and the interrupt exception timing se·
quence is shown in Figure 39.

PROCESSOR

INTERRUPTING DEVICE

Request Interrupt

Grant Interrupt
1) Compare interrupt level in status register
and wait for current instruction to complete

2)
3)
4)
5)
6)

Place interrupt level on A, , A" A.
Set R/W to read
Set function code to interrupt acknowledge
Assert address strobe (AS)
Assert lower data strobe (LOS)

I

1

Provide Vector Number
1) Place vector number of Do - 0,
2) Assert data transfer acknowledge (OTACK)

I
Table 9 Internal Interrupt Level
Level

12
1
1
1
1
0
0
0
0

7
6
5
4
3
2
1
0

11
1
1
0
0
1
1
0
0

10
1
0
1
0
1
0
1
0

Interrupt

Acquire Vector Number
1) latch vector number
2) Negate lOS
3) Negate AS'

Non·Maskable Interrupt

Maskable Interrupt

!!!!!!!!
1) Negat.~

r

No I nterru pt

Start Interrupt ProceSSing

(NOTE) The internal interrupt mask level U2,.!,1.IO) are inverted to the
logic level applied to the pins (TPL., II'L, , J15'(0).

Figure 37 Interrupt Acknowledge Sequence
FlowChart

ClK

~

\

\

I
I

'\j

~,..,.

\
\
\

~
~
~

\

'I

\

'---.r
'---.r

~

/

~

~

\

}----/\

~§
last Bus Cycle of Instruction
(Read or Write)

r

<

""
7~

~

lACK Cycle
(Vector Number Acquisition

Figure 38 Interrupt Acknowledge Sequence Timing Diagram

131

\
\

<
<
Stack and,
Vector Fetch

HD68000,HD68000Y----------------------------------------------------------------last Bus Cycle
of Instruction
(During Which
I nterrupt Was
Recognized)

f---

Stack
PCl
(SSPI

-

lACK
Cycle
(Vector Number
Acquisition)

~

Read
Vector
High
(A .. -A.. I

-

Read
Vector
low
(A. - AI5I

f---

-

Stack
Status
(SSP)

f---

Stack
PCH
(SSP)

-+

Fetch First Word
of Instruction
of Interrupt
Routine

Figure 39 Interrupt Exception Timing Sequence
Priority level seven is a special case. Level seven interrupts
cannot be inhibited by the interrupt priority mask, thus providing a "non-maskable interrupt" capability. An interrupt is
generated each time the interrupt request level changes from
some lower level to level seven. Note that a level seven interrupt
may still be caused by the level comparison if the request level
is a seven and the processor priority is set to a lower level by an
instruction.

Word patterns with bits 15 through 12 equaling 1010 or
1111 are distinguished as unimplemented instructions and
separate exception vectors are given to these patterns to permit efficient emulation. This facility allows the operating
system to detect program errors, or to emlllate unimplemented
instructions in software.
ILLEGAL INSTRUCTION EXAMPLE

UNINITIALIZED INTERRUPT

MOVE DO, #$1000

An interrupting device asserts VPA or provides an interrupt
vector during an interrupt acknowledge cycle to the HD68000.
If the vector register has not been initialized, the responding
HMCS68000 Family peripheral will provide vector IS, the
unitialized interrupt vector. This provides a uniform way to
recover from a programming error.

+

MOVE OPWORD

0011

100111

tMOVE

t
IMMEDIATE

WORD

SPURIOUS INTERRUPT

If during the interrupt acknowledge cycle no device responds
by asserting DTACK or VPA, the bus error line should be asserted to terminate the vector acquisition. The processor separates
,the processing of this error from bus error by fetching the
spurious interrupt vector instead of the bus error vector. The
processor then proceeds with the usual exception processing.
INSTRUCTION TRAPS

Traps are exceptions caused by instructions. They arise
either from processor recognition of abnormal conditions
during instruction execution, or from use of instructions whose
normal behavior is trapping.
Some instructions are used specifically to generate traps.
The TRAP instruction always forces an exception, and is useful
for implementing system calls for user programs. The TRAPV
and CHK instructions force an exception if the user program
detects a runtime error, which may be an arithmetic overflow
or a subscript out of bounds.
The signed divide (DIVS) and unsigned divide (DNU) instructions will force an exception if a division operation is
attempted with a divisor of zero.
ILLEGAL AND UNIMPLEMENTED INSTRUCTIONS
Illegal instruction is the term used to refer to any of the
word bit patterns which are not the bit pattern of the first
word of a legal instruction. During instruction execution, if
such an instruction is fetched, an illegal instruction exception

occurs.

+

000

t
DATA
REGISTER
DIRECT

000

t

REGISTER
NUMBER

"0"

PRIVILEGE VIOLATIONS

In' order to provide system security, various instructions
are privileged. An attempt to execute one of the privileged
instructions while in the user state will cause an exception.
The privileged instruction are:
STOP
AND (word) Immediate to SR
RESET
EOR (word) Immediate to SR
RTE
OR (word) Immediate to SR
MOVE to SR
MOVE USP
TRACING

To aid in program development,. the HD68000 includes
a facility to allow instruction by instruction tracing. In the
trace state, after each instruction is executed an exceptions
is forced, allowing a debugging program to monitor the execution of the program under test.
The trace facility uses the T-bit in the supervisor portion
of the status register. If the T-bit is negated (off), tracing is
disabled, and instruction execution proceeds from instruction
to instruction as normal. If the T-bit is asserted (on) at the
beginning of the execution of an instruction, a trace exception
will be generated after the execution of that instruction is
completed. If the instruction is not executed. either because
an interrupt is taken, or the instruction is illegal or privileged,
the trace exception does not occur. The trace exception also
does not occur if the instruction is aborted by a reset, bus
132

-----------------------------------------------------------------HD68000,HD68000Y
error, or address error exception. If the instruction is·indeed executed and an interrupt is pending on completion, the trace
exception is processed before the interrupt exception. If, during
the execution of the instruction, an exception is forced by that
instruction, the forced exception is processed before the trace
exception.
As an extreme illustration of the above rules, consider the
arrival of an interrupt during the execution of a TRAP instruction while tracing is enabled. First the trap exception is processed, then the trace exception, and fInally the interrupt ex·
ception. Instruction execution resumes in the interrupt handler
routine.

TRACE MODE

IFT= 1

STATUS REGISTER

the bus error occurred. The processor is processing an instruction if it is in the normal state or processing a Group 2 exception; the processor is not processing an instruction if it is processing a Group 0 or a Group.l exception. Figure 40 illustrates
how this information is organized on the supervisor stack.
Although this information is not sufficient in general to effect
full recovery from the bus error, it does allow software diagnosis. Finally, the processor commences instruction processing
at the address contained in the vector. It is the responsibility
of the error handler routine to clean up the stack and determine
where to continue execution.
If a bus error occurs during the exception processing for a
bus error, address error, or reset, the processor is halted, and
all processing cases. This simplifIes the detection of catastrophic
system failure, since the processor removes itself from the
system rather than destroy all memory contents. Only the
RESET pin can restart a halted processor.
ADDRESS ERROR

AFTER EACH
INSTRUCTION

MAIN
PROGRAM
RETURN TO
EXECUTE
NEXT
INSTRUCTION

ADDRESS OBTAINED
FROM VECTOR TABLE

1. If, upon completion of an instruction, T = 1,
go to trace exception processing.
2. Execute trace exception sequence.
3. Execute trace service routine.
4. At the end of the service routine, execute
return from exception (RTE).

Address error exceptions occur when the processor attempts
to access a word or a long word operand or an instruction at
an odd address. The effect is much like an internally generated
bus error, so that the bus cycle is aborted, and the processor
ceases whatever processing it is currently doing and begins
exception processing. After exception processing commences,
the sequence is the same as that for bus error including the
information that is stacked, except that the vector number
refers to the address error vector instead. Likewise, if an address
error occurs during the exception processing for a bus error,
address error, or reset, the processor is halted. As shown in
Figure 42, an address error will execute a short bus cycle follow·
ed by exception processing.
•

BUS ERROR

Bus error exceptions occur when the external logic requests
that a bus error be processed by an exception. The current bus
cycle which the processor is making is then aborted. Whether
the processor was doing instruction or exception processing,
that processing is terminated, and the processor immediately
begins exception processing.
Exception processing for bus error follows the usual sequence of steps. The status register is copied, the supervisor
state is entered, and the trace state is turned off. The vector
number is generated to refer to the bus error vector. Since the
processor was not between instructions when the bus error
exception request was made, the context of the processor is
more detailed. To save more of this context, additional information is saved on the supervisor stack. The program counter
and the copy of the status register are of course saved. The value
saved for the program counter is advanced by some amount,
two to ten bytes beyond the address of the f11"St word of the
instruction which made the reference causing the bus error. If
the bus error occurred during the fetch of the next instruction,
the saved program counter has a value in the vicinity of the
current instruction, even if the current instruction is a branch,
a jump, or a return instruction. Besides the usual information,
the processor saves its internal copy of the fust word of the
instruction being processed, and the address which was being
accessed by the aborted bus, cycle. Specific information about
the access is also saved: whether it was a read or a write, whether the processor was processing an instruction or not, and the
classification displayed on the function code outputs when

INTERFACE WITH HMCS6800 PERIPHERALS

Hitachi's extensive line of HMCS6800 peripherals are directly compatible with the HD68000. Some of these devices
that are particularly useful are:
Peripheral Interface Adapter
HD6821
HD6843
Floppy Disk Controller
HD684SS CRT Controller
HD46508 Data Acquisition Unit
HD6850
Asynchronous Communication Interface
Adapter
HD6852
Synchronous Serial Data Adapter
To interface the synchronous HMCS6800 peripherals with
the asynchronous HD68000, the processor modifieS its bus
cycle to meet the HMCS6800 cycle requirements whenever an
HMCS6800 device address is detected. This is possible since
both processors use memory mapped JjO. Figure 44 is a flow
chart of the interface operation between the processor and
HMCS6800 devices.

• DATA

TRANSFER OPERATION

Three signal on the processor provide the HMCS6800 interface. They are: enable (E), valid memory address (VMA), and
valid peripheral address (vpA). Enable corresponds to the
E or tP2 signal in existing HMCS6800 systems. The bus frequency is one tenth of the incoming HD68000 clock frequency.
The timing of E allows 1 MHz peripherals to be used with
an 8 MHz HD68000. Enable has a 60/40 duty cycle; that
is, it is low for six input clocks and high for four input clocks.
This duty cycle allows the processor to do successive VPA accesses on successive E pulses.
HMCS6800 cycle timing is given in Figure 45 and 46. At

133

HD68000,HD68000Y-------------------------------------------------------------15

14

13

12

11

10

9

7

8

4

5

6

3

2

o

IRtWl I/N I Function Code

Lower Address
High

~-·AccessAddre.. - - - - - - - - - - - - - low
------------------\ ---·
Instruction Register
Status Register
High
- - -Program Counter----- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - low
R/W (reed/write): write ~ 0, read = 1. I/N (Instruction/not!: instruction = 0, not a 1

Figure 40 Supervisor Stack Order (Group 0)

15

14

13

12

11

10

9

lower AddreSS

Higher Address

8

7

6

4

5

3

2

o

Status Register

r----

High

Program Counter ---- ------------------------------

::v: -------

Figure 41 Supervisor Stack Order (Group 1, 2)

ClK

A,-A u

AS
UDS
"

iJ5!

\
\

/
/

I-

,

I

\

<
Read

)

-I-

\

'\4

"

(

}----I\

Aerr
Write

II

I

Approx. 8 Clocks
..
Idle

\

,

~

I

\

D. - 0 ..

I
/

\

,

I

\

RtW
DTACK

\

\

'---

+

(

Write Stack

..

Figure 42 Address Error Timing

state zero (SO) in the cycle, the address bus is in the highimpedance state. A function code is asserted on the function
code output lines. One-half clock later, in state 1 the address
bus is released from the high-impedance state.

During state 2, the address strobe (AS) is asserted to indicate that there is a valid address on the address bus. If the
bus cycle is a read cycle, the upper and/or lower data strobes
are also asserted in state 2. If the bus cycle is a write cycle,

134

-----------------------------------------------------------------HD68000,HD68000Y

-0,

D. - 0, (or 0, - DIS)

~=============~D.

Address
&
CS's

Address
Bus
AS

CS

HD68000
Block of
HMCS6800
Devices

VPA

CS

VMA

E

E

Figure 43 Connection of HMCS6800 Peripherals

the read/write (R/W) signal is switched to low (write) during
state 2. One half clock later, in state 3, the write data is placed
on the data bus, and in state 4 the data strobes are issued to
indicate valid data on the data bus. The processor now inserts
wait states until it recognizes the assertion of VPA.
The VPA input signals the processor that the address on the
bus is the address of an HMCS6800 device (or an area reserved
for HMCS6800 devices) and that the bus should conform to
the tP2 transfer characteristics of the HMCS6800 bus. -Valid
peripheral address is derived by decoding the address bus,
conditioned by address strobe.
After the recognition of VPA, the processor assures that
the Enable (E) is low, by waiting if necessary, and subsequently
asserts VMA. Valid memory address is then used as part of the
chip select equation of the peripheral. This ensures that the
HMCS6800 peripherals are selected and deselected at the
correct time. The peripheral now runs its cycle during the
high portion of the E signal. Figures 4S and 46 depict the best
and worst case HMCS6800 cycle timing. This cycle length is
dependent strictly upon when VPA is asserted in relationship
to the E clock.
During a read cycle, the processor latches the peripheral
data in state 6. For all cycles, the processor negates the address
and data strobes one half clock cycle later in state 7, and the
Enable signal goes low at this time. Another half clock later,
the address bus is put in the high-impedance state. During a
write cycle, the data bus is put in the high-impedance state
and the read/write signal is switched high. The peripheral logic
must remove VPA within one clock after address strobe is
negated.
Figure 47 shows the timing required by HMCS6800 peripherals, the timing specified for HDCS6800, and the corresponding timing for the HD68000. Two example systems with
HMCS6800 peripherals are showin in Figures 48 and 49. The
system in Figure 48 reserves the upper eight megabytes of
memory for HMCS6800 peripherals. The system in Figure 49
is more efficient with memory and easily expandable, but more
complex.
DTACK should not be asserted while VPA is asserted.
Notice that the HD68000 VMA is active low, contrasted with
the active high HMCS6800 VMA. This allows the processor
to put its buses in the high-impedance state on DMA requests
without inadvertently selecting peripherals.

PROCESSOR

SLAVE

Initiate Cycle
1) The processor starts a normal Read or
Write cycle

Define HMCS6800 Cycle
1) External hardware asserts Valid Peripheral
Address (i7PA)

!

Synchronize With Enable
1) The processor monitors Enable (E) until it is
low (Phase 1)
2l The processor asserts Valid Memory Address
(VMA)

Transfer Data
1) The peripheral waits until E is active and
then transfers the data

Terminate Cycle
1) The processor waits until E goes low. (On a
Read cycle the data is latchad as E goes
low internally)
2l The processor negates VMA
3) The processor negates AS, UDS, and LOS

1

Start Next Cycle

Figure 44 HMCS6800 Interface Flow Chart

135

HD68000,HD68000Y----------------------------------------------------------------50

51

52

53

S4

w

w

w

w

w

w

w

w

w

w

w

w

55

56

57

50

ClK
AI - An
A5
51

E
VPA
VMA

Data Out
Data In - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - FC.-F~

____

_J~

__________________________________________________________________

_Jr_-----

(NOTE) This figure represents the best case HMC56800 timing where VPA falls before the third system clock cycle after the falling edge of E.

Figure 45 HMCS6800 Timing - Best Case

W~~~S4wwwwwwwwwwwwwwwwwwwwwwwwwwww~~~W

ClK

.rv-: ~JL.Cf~~FIJ'LJ

A.-An J-{

~

\
---<

"1'

J

E

\

VPA

-

~

--

VMA

~/~

Write

®

~

~

-

:I-®

~@

®

Data In

Data Out

-@

-@J

RtW

R/WWrite

r-®

-@---

(Read)

UDS/lDS
Read

@

--- f-@

\
\

@....

@-

-

--<

r--@

\

K

FC. - FC.

Figure 46 HMCS6800 Timing - Worst Case

136

-----------------------------------------------------------------HD68000,HD68000Y

t=

HMCS6800·

Peripheral'""

150 n.~ Type
ns
~ 270n.

B
Type A
~S.;;'d;-.___

180

HMCS6800 VMA, RIW
HMCS6BOOAddress

I

70

n.~

140 ns

Type B
Tvpe A

140n.

S.d

~ 10 ns Peripheral·

B

1.5MHz

A

1.0 MHz

S.d

Peripheral il

Type B ~ 180 n s = = = s
Type A

~
~

220 ns

=m
----------------'W&#dIff/l#$

~
r--

Type B

~pe,,~e~:3"

Type A

80 ns
)~-----

HD68000 (8 MHz!

l--200n.~
VMA----------------------~~~~

~---~~=====-------------~

HD68000CLK
.. Times are expressed for different device clock frequencies.

Figure 47 HD6BOOO to HMCS6BOO Peripheral Timing Diagram
33k
+5V

I

AS

Do

~

I

I

VMA

-ou

~

AI-Au

I
J

?

C

C

I

I::i

~

.;

.. .. .. ,.
0

I';

CS; eS I es o RS. AS o

HD6BOOO

HD6821 PIA

L.-

VPA

Fe,
Fe,
Fe,

}e

IPL
IJiL,

tiV
IT

~a: li'l I'~"
It

E

I

~ .i

Ii

CS1 CS 1 AS

eso

H06850 ACtA

RIW

3.3k

J

11't",
RES
E
RIW

Figure 48 HMCS6800 Interface - Example 1

137

0
ci

iR1l E AtW

10 ns Peripheral

I

~'"""fj'"'_________________________.J)

Write Data

10 ns HMCS6800·

I ))------

~

Std
195 ns
HMCS6800WriteData _ _ _ _ _ _ _ _ _ _ _ _ _ _--<~

HD68000 Address

Type

==~~~----~==~------

~
--l 1--1~0~n..s":H':':M~C~S::68=OO:::'·:---------------......j

HMCS6800 Read 00'0

HMCS6800 E Clock Freq.
2.0 MHz

>

::t

C

0)

+5

§

3.3k

~~

J

%
c0)

6800 Addr_

(XI

~

Al
VQA

2

Do-DIS
AI-An

.c

~

L

.c

I~

.c
L
.c

)'

.-.&
~

8
~ C

133

cf

VPA

HD68000

~ A

.....

74LS y,
138

~B

Co>

y.
y,
y,

A,

(XI

~C

G1Gu.

~

Fe.
FC.

~

1>-

~

----

~

33~f ~
-

G,.

y.
y,
y,
y,

+5

~

~

!

.

0

«

~ ~ c .c

J
... 7'

-.l'"

cs. CS. CSo RS.

w

0

J

8CD :I'"

'" >

cs. CS•. CSO RS

RSo

HD6821 PIA

I~ I~ ~

"
~

~

HD6850ACIA

I~

~

w

I~

+s
3.3k

~
,/..

-rlr:.

IPL.
IPL
IPL

l

y•
74LS y.
A 138 ~'

,,~
74LS
348
r4LS

AoI48
A.
A,

l

:.

"
I,
h

I.
I

r--

1.1""--I
NMI

RES
1:

RIW___

---

--_._-

Figure 49 HMCS6800 Interface - Example 2

-

--------------------------------------------------------------HD68000,HD68000Y
• INTERRUPT OPERATION
During an interrupt acknowledge cycle while the processor
is fetching the vector, if VPA is asserted, the HD68000 wi1l
assert VMA and complete a normal HMCS6800 read cycle as
shown in Figure 50. The processor wi1l then use an internally
generated vector that is a function of the interrupt being serviced. This process is known as autovectoring. The seven autovectors are vector numbers 25 through 31 (decimal).
This operates in the same fashion (but is not restricted to)
the HMCS6800 interrupt sequence. The basic difference is that

there are six normal interrupt vectors and one NMI type vector.
As with both the HMCS6800 and the HD68000's normal
vectored interrupt, the interrupt service routine can be located
anywhere in the address space. This is due to the fact that
while the vector numbers are fixed, the contents of the vector
table entries are assigned by the user.
Since VMA is asserted during autovectoring, the HMCS6800
peripheral address decoding should prevent unintended accesses.

ClK
A, -A.

\
\

UOS
lOS

R/W

\

DTACK

I
'---1

c::::::J

o. -0"

(

D. - 0,

e,

,,,-

r--\
r--\
r--\

\

AS

FC. -FC,

\..-

)-J

A. - Au

X

)

y

Jlf[. - l"P"L;

\~

VPA

L___________________________J,___

VMA ----------------------------------------~\

,-••

Interna! ~PC low Stacking--oI-l••------Autovector Operation _ _ _ _ _ _ _ _ _
~I lnternal
Process,ng--rProcessing

Figure 50 Autovector Operation Timing Diagram

• DATA TYPES AND ADDRESSING MODES
Five basic data types are supported. These data types are:
• Bits
• BCD Digits (4-bits)
• Bytes (8-bits)
• Word (16-bits)
• long Words (32-bits)
In addition, operations on other data types such as memory
addresses, status word data, etc., are provided for in the instruction set.
The 14 addressing modes, shown in Table 10, includs six

basic types:
• Register Direct
• Register Indirect
• Absolute
• Immediate
• Program Counter Relative
• Implied
Included in the register indirect addressing modes is the capability to do postincrementing, pred.,crementing, offsetting and
indexing. Program counter relative mode can also be modified
via indexing and offsetting.

139

HD68000,HD68000Y----------------------------------------------------------------Table 10 Addressing Modes
Mode
Register Direct Addressing
Data Register Diredt
Address Register Direct
Absolute Data Addressing
Absolute Short
Absolute Long
Program Counter Relative Addressing
Relative with Offset
Relative with Index and Offset
Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset
I mmediata Data Addressing
Immediate
Quick Immediate
Implied Addressing
Implied Register
(NOTES)
EA = Effective Address
An = Address Register
Dn = Data Register
Xn = Address or Data Register used
as Index Regi.ter
SR = Status Register
PC = Program Counter
( ) = Contents of

•

Generation

EA=Dn
EA=An
EA = (Next Word)
EA = (Next Two Words)
EA = (PC) + d ..
EA = PC) + (Xn) + d.
EA= (An)
EA = (AN), An <-An + N
An <-An - N, EA = (An)
EA = (An) + d,.
EA = (An) + (Xn) + d.
DATA = Next Word(.)
Inherent Data
EA = SR, USP, SP, PC
d. = Eight-bit Offset
(displacement!
d ,. = Sixteen-bit Offset
(displacement)
N = 1 for Byte, 2 for
Words and 4 for Long
Words
..... = Replaces

INSTRUCTION SET OVERVIEW

The HD68000 instruction set is shown in Table 11. Some
additional instructions are variations, or subsets, of these and
they appear in Table 12. Special emphasis has been given to
the instruction set's support of structured high-level languages
to facilitate ease of programming. Each instruction, with few
exceptions, operates on bytes, words, and long words and most
instructions can use any of the 14 addressing modes. Combining
instruction types, data types, and addressing modes, over 1000
useful instructions are provided. These instructions include
signed and unsigned multiply and divide, "quick" arithmetic
operations, BCD arithmetic and expanded operations (through
traps).
The following paragraphs contain an overview of the form
and structure of the HD68000 instruction set. The instructions form a set of tools that include all the machine functions
to perform the following operations:
Data Movement
Integer Arithmetic
Logical
Shift and Rotate
Bit Manipulation
Binary Coded Decimal
Program Control
System Control
The complete range of instruction capabilities combined
with the flexible addressing modes described previously provide a very flexible base for program development.

Table 11 Instruction Set
Mnemonic

ABCD
ADD
AND
ASL
ASR
Bee
BCHG
BCLR
BRA
BSET
BSR
BTST
CHK
CLR
CMP
DBee
DIVS
DIVU

Description
Add Decimal with Extend
Add
Logical And
Arithmetic Shift Left
Arithmetic Shift Right
Branch Conditionally
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and Set
Branch to Subroutine
Bit Test
Check Register Against Bounds
Clear Operand
Compare
Test Condition, Decrement and
Branch
Signed Divide
UnSigned Divide

Mnemonic

EOR
EXG
EXT
JMP
JSP
LEA
LINK
LSL
LSR
MOVE
MOVEM
MOVEP
MULS
MULU
NBCD
NEG
NOP
NOT
OR

Description
Exclusive Or
Exchange Registers
Sign Extend
Jump
Jump to Subroutine
Load Effective Address
Link Stack
Logical Shift Left
Logical Shift Right
Move
Move Multiple Registers
Move Peripheral Data
Signed Multiply
Unsigned Multiply
Negate Decimal with Extend
Negate
No Operation
One's Complement
Logical Or

140

Mnemonic

PEA
RESET
ROL
ROR
ROXL
ROXR
RTE
RTR
RTS
SBCD
Sec
STOP
SUB
SWAP
TAS
TRAP
TRAPV
TST
UNLK

Description

Push Effective Address
Reset External Devices
Rotate Left without Extend
Rotate Right without Extend
Rotate Left with Extend
Rotate Right with Extend
Return from Exception

Return and Restore
Return from Subroutine

Subtract Decimal with Extend
Set Conditional
Stop
Subtract
Swap Data Register Halves
Test and Set Operand
Trap
Trap on Overflow
Test
Unlink

--------------------------------------------------------------HD68000.HD68000Y
Table 12 Variations of Instruction Types
Instruction
Type
ADD

Variation

ADD
ADDA
ADOQ
ADDI
ADDX

Add
Add
Add
Add
Add

AND

AND
ANDI

Logical And
And Immediate

CMP

CMP
CMPA
CMPM
CMPI
EOR
EORI

EOR

Instruction
Type

Description

Move
Move Address
Move Quick
Move from Status Register
Move to Status Register
Move to Condition Codes
Move User Stack Pointer

Compare
Compare Address
Compare Memory
Compare Immediate

NEG

NEG
NEGX

Negate
Negate with Extend

OR

OR
ORI

Logical Or
Or Immediate

Exclusive Or
Exclusive Or Immediate

SUB

SUB
SUBA
SUBI
SUBQ
SUBX

Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend

Address
Quick
Immediate
with Extend

and negate instructions may be used on all sizes of data operands.
The multiply and divide operations are available for signed
and unsigned operands using word multiply to produce a long
word product. and a long word dividend with word divisor to
produce a word quotien with a word remainder.
Multiprecision and mixed size arithmetic can be accomplished using a set of extended instructions. These instructions are:
add extended (ADDX). subtract extended (SUBX). sign extend
(EXT). and negate binary with extend (NEGX).
A test operand (TST) instruction that will set the condition
codes as a result of a compare of the operand with zero is also
available. Test and set (TAS) is a synchronization instruction
useful in multiprocessor systems. Table 14 is a summary of
the integer arithmetic operations.

Instructions for the HD68000 contain two kinds of information: the type of function to be performed. and the location
of the operand(s) on which to perform that function. The
methods used to locate (address) the operand(s) are explained
in the following paragraphs.
Instructions specify an operand location in one of three
ways:
Register Specification - the number of the register is given
in the register field of the instruction.
Effective Address - use of the different effective address
modes.
Implicit Reference - the defmition of certain instructions
implies the use of specific registers.
DATA MOVEMENT OPERATIONS

The basic method of data acquisition (transfer and storage)
is provided by the move (MOVE) instruction. The move instruction and the effective addressing modes allow both address
and data manipulation. Data move instructions allow byte.
word. and long word operands to be transferred from memory
to memory. memory to register. register to memory. and register to memory. and register to register. Address move instruc·
tions allow word and long word operand transfers and ensure
that only legal address manipulations are executed. In addition
to the general move instruction there are several special data
movement instructions: move multiple registers (MOVEM).
move peripheral data (MOVEP). exchange registers (EXG).
load effective address (LEA). push effective address (PEA).
link stack (LINK). unlink stack (UNLK). and move quick
(MOVEQ). Table 13 is a summary of the data movement
operations.
•

Description

MOVE
MOVEA
MOVEQ
MOVE fromSR
MOVE to.5R
MOVE to CCR
MOVE USP

• ADDRESSING

•

Variation

MOVE

Table 13 Data Movement Operations
Instruction

INTEGER ARITHMETIC OPERATIONS

The arithmetic operations include the four basic operations
of add (ADD). subtract (SUB). multiply (MUL). and divide
(DIY) as well as arithmetic compare (CMP). clear (CLR). and
negate (NEG). The add and subtract instructions are available
for both address and data operations. with data operations
accepting all operand sizes. Address operations are limited
to legal address size operands (16 or 32 bits). Data. address.
and memory compare operations are also available. The clear

Operand Size

EXG

32

LEA

32

LINK

-

MOVE

8.16.32

MOVEM

16.32

MOVEP

16.32

MOVEa
PEA

8
32

SWAP

32

UNLK

-

(NOTES)
s = source
d =: destination
[ I = bit numbers

141

Operation
Rx <+ Ry
EA .... An
(An .... SP@-;
SP .... An;
SP+d .... SP
(EA)s .... EAd
(EA) .... An. On
An. On .... EA
(EA) .... on
Dn .... EA
#Xxx .... On
EA .... SP@on[31:16) ... on[15:0)
(An .... SP;
SP@+ .... An

@ - = indirect with predecren'lent
@+ = indirect with postdecrement

H068000,H068000Y------------------------------------------------------------------Table 14 Integer Arithmetic Operations
Instruction

Operand Size

Operation

8,16,32

On + (EA) ..... On
(EA+ On ..... EA
(EA) + #Xxx ..... EA
AN + (EA) ..... An

AOD

16,32
8,16,32
16,32
8,16,32
8,16,32

ADDX
CLR

Dx+ Dy+ x ..... Ox
Ax@-+Ay@-+X ..... Ax@

OIVU
EXT
MULS
MULU
NEG
NEGX

Dn/(EA) ..... On

The HD68000 separates memory references into two classes: program references, and data references. Program references, as the name implies, are references to that section of
memory that contains the program being executed. Data references refer to that section of memory that contains data.
Generally, operand reads are froin the data space. All operand
writes are to the data space.

(On)s ..... Onl6
(On) 16 ..... On32

•

On - (EA)
(EA) - #Xxx
Ax@+-Ay@+
An - (EA)

16,32
32+ 16
32+ 16
8 ..... 16
16 ..... 32
16·16 ..... 32
16·16 ..... 32
8,16,32
8,16,32
8,16,32

Dn/(EA) ..... On

On*(EA) ..... On

0- (EA) ..... EA
0- (EA) - X - EA
On (EA)
(EA)
An -

16,32

•

(EA) ..... On
- On ..... EA
- #Xxx ..... EA
(EA) ..... An

SUBX

8,16,32

Ox - Oy - X ..... Ox
Ax@--Ay@--X4Ax@

TAS

8
8,16,32

(EA) - 0,1 ..... EA[7]

TST
(NOTE)

[

I

(EA) -0

= bit number

15

14

13

12

11

REGISTER SPECIFICATION

The register field within an instruction specifies the register
to be used. Other fields within the instruction specify whether
the register selected is an address or data register and how the
register is to be used.

Dn.(EA)"'" On

SUB

INSTRUCTION FORMAT

Instructions are from one to five words in length, as shown
in Figure 51. The length of the instruction and the operation
to be performed is specified by the first word of the instruction
which is called the operation word. The remaining words
further specify the operands. These words are either immediate
operands or extensions to the effective address mode specified
in the operation word.
• PROGRAM/DATA REFERENCES

0 ..... EA

CMP
DIVS

•

EFFECTIVE ADDRESS

Most instructions specify the location of an operand by using
the effective address field in the operation word. For example,
Figure 52 shows the general format of the single effective address is composed of two 3-bit fields: the mode field, and the
register field. The value in the mode field selects the different
address modes. The register field contains the number of a
register.
The effective address field may require additional information to fully specify the operand. This additional information,
called the effective address extension, is contained in the
following word or words and is considered part of the instruction, as shown in Figure 51. The effective address modes are
grouped into three categories: register direct, memory addressing, and special.

4
7
6
5
8
Operation Word
(F irst Word Specifies Operation and Modes)

10

9

3

2

3

2

1

0

Immediate Operand
(If Any, One or Two Words)
Source Effective Address Extension
(If Any, One or Two Words)
Destination Effective Address Extension
(If Any, One or Two Words)

Figure 51

Instruction Format

5

4

Effective Address
Mode
Register

Figure 52 Single-Effective-Address Instruction Operation Word General Format

142

o

-----------------------------------------------------------------HD68000,HD68000Y
REGISTER DIRECT MODES

Data Register Direct

These effective addressing modes specify that the operand
is in one of the 16 multifunction registers.

The operand is in the data register specified by the effective
address register field.

EXAMPLE

COMMENTS

MPU

MEMORY

• EA = On

$OOlFOO
• Machine Level Coding
MOVE DO, $1 FOO
iOOOOASCDi DO
0011

.I"

Move

Word

0001

1100

0000

IIJ.;-.,
Absolute
Short

MOVE DO, $1 FOO

OWL

31CO

OWL+2

lFOO

Data
Register
Direct

Address Register Direct

The operand is in the address register specified by the effective address register field.

EXAMPLE
MPU

COMMENTS
MEMORY

1000012341 A4

• EA

= An

• Machine Level Coding
MOVE A4, $201000

ITIl00~
Word Absol ute
Long
Address
OWL
MOVE A4,$201000

33CC

I---------~

OWL + 2 ~_....;00:..:..::2.:.0_ ___1
OWL+4
1000

1------1

143

Register

Direct

HD68000,HD68000Y
EXAMPLE
MPU

COMMENTS
MEMORY

.EA =An
• Address Register Sign Extended
• Machine Level Coding
MOVE $201000,A4

1000012341 A4

0011
Move
IWord

1[1000

0111

1001

~

Absolute
Long

Reg#4

Address
Register
Direct

MOVE $201000, A4

OWL

3879

OWL+2

0020

OWL+4

1000

MEMORY ADDRESS MODES

These effective addressing modes specify that the operand
is in memory and provide the specific address of the operand.

Address Register Indirect
The address of the operand is in the address register specified
by the register field. The reference is classified as a data reference with the exception of the jump and jump to subroutine
instructions.

EXAMPLE
MPU

MEMORY

COMMENTS
.EA~ (An)

• Machine Level Coding
MOVE (AO), DO

~

1000010001 AO

~

jiOOO¥OQ.1:'

~

Word

Register
Direct

OWL 1-_..;;.30,;;.1;.,;0_--1
MOVE (AO), DO

144

Reg

#0

ARI
(Address
Register
Indirect)

-------------------------------HD68000,HD68000Y

Address Register Indirect With Postinerement
The address of the operand is in the address register specified
by the register field. After the operand address is used, it is
incremented by one, two, or four depending upon whether
the size of the operand is byte, word, or long word. If the

MPU

address register is the stack pointer and the operand size is
byte, the address is incremented by two rather than one to
keep the stack pointer on a word boundary. The reference is
classified as a data reference.

MEMORY

00000100 A4
00000102

COMMENTS
• EA = (An); An + M-An
Where An-.Address Register
M -1,2,or4
(Depending Whether
Byte, Word, or
Long Word)
• Machine Level Coding
MOVE (A4) +, $2000

I
OWL
MOVE (A4) +,$2000

~

31DC

I-----~

OWL + 2 1-_...;;2;.;00.;;..;.0_-1

Address Register Indirect With Predecrement
The address of the operand is in the address register specified
by the register field. Before the operand address is used, it is
decremented by one, two, or four depending upon whether
the operand size is byte, word, or long word. If the address

register is the stack pointer and the operand size· is byte, the
address is decremented by two rather than one to keep the
stack pointer on a word boundary. The reference is classified
as a data reference.

EXAMPLE
MPU

r

0001
101
1r:
Move
Word Absolute
Short
ARI with
Increment

MEMORY

00000100 A3

OOOOOOFE

COMMENTS
• An - M_An; EA = (An)
Where An_Address Register
M -1,2,or4
(Depending Whether
Byte, Word, or
Long Word)
• Machine Level Coding
MOVE - (A3), $4000

:tI11~10011
0001

Move
Word

OWL
31E3
OWL + 2 ~--4-000----i
MOVE - (A3),$4000

145

Absolute
Short

with
Pred ie·
rament

Reg #3

HD68000,HD68000Y------------------------------·----------------------------------register and the sign-extended 16-bit displacement integer in
the extension word. The reference is classified as a data reference wlth the exception of the jump to subroutine instructions.

Address Register Indirect With Displacement
This address mode requires one word of extension. The address of the operand is the sum of the address in the address

MPU

MEMORY

$1100 I--";~=-__~

1000010001 AD

$3000

MOVE $100(AOI,$30oo
AQDRESS
CALCULATION:
AO - 00001000
d,. - 00000100
00001100·

I-__~=-__-I

COMMENTS
• EA = An +d,.
Where An -Pointer Register
d,. -16·Bit Displacement
• d,. Displacement is Sign Extended
• Machine Level Coding
MOVE $100(AOI,$3000

:r

0001

1110

.::::c-

Absolute
Short

1000

t IReg #0

ARI
with
Displacement

Move
Word

OWL 1-_.::3~1E:::8::"""_-I
OWL+21-_~0~lOO~_--I
OWL+41-_~3~000~_--1

Address Register Indirect With Index
This address mode requires one word .of extension. The
address of the operand is the sum of the address in the address
register, the sign-extended displacement integer in the low order

eight bits of the extension word, and the contents of the index
register. The reference is classified as a data reference with the
exception of the jump and jump to subroutine instructions.

EXAMPLE
MEMORY

MPU

100002BDCI DO
1000020001 AO

COMMENTS
• EA - An + Rx + d.
Where
An _
Pointer Register
Designated Index Regilter,
Rx (Either Address Register or
Data Registed
d. _
8·Bit Displacement
• Rx & d. are Sign Extended
• Rx mey be Word or Long Word
Long Word may be Designated with Rx.L
• Machine Level Coding
MOVE $04(AO, 001, $1000
0011

0001

1111

0000

---=r
~I:.::r::.Move
Absolute
Reg #0

Word
MOVE $04(AO, 001,
$1000
ADDRESS
CALCULATION:
AO - 00002000
DO • 00002BDC
d -00000004
ooo04BEO

OWL

Short

ARI
with
Index

.31FO

OWL+2r--~0~004~--~
OWL+41-__1~00~0::"""__-I

0000

olIwfra1
Reg #0

146

0000

0000

0100

Jr.ii

onstant Zeros

-----------------------------------------------------------------HD68000,HD68000Y
SPECIAL ADDRESS MODE

Absolute Short Address

The special address modes use the effective address register
field to specify the special addressing mode instead of a register
number.

This address mode requires one word of extension. The ad·
dress of the operand is the extension word. The 16-bit address
is sign extended before it is used. The reference is classified
as a data reference with the exception of the jump and jump
to subroutine instructions.

EXAMPLE
MPU

MEMORY

~
$2000

FFFF .... 0000

$2002

OOOO .... FFFF

COMMENTS
• EA = (Next Word)
• 16-Bit Word is Sign Extended

• Machine Level Coding
NOT.L$2000
0100

0110

t

1011

Not Instruction

NOT.L$2000

OWL

46B8

OWL+2

2000

EXAMPLE
MEMORY

MPU

$1000

1000

t.w~
Absolute
Short

COMMENTS
• EA = (Next Word)
• 16-Bit Word is Sign Extended

• Machine Level Coing
MOVE $1000, $2000
0011

-.rMove

$2000

Word

0001

1111

I~
Short

Absolute
Short

MOVE $1000, $2000

OWL

31F8

OWL+2

1000

OWL+4

2000

147

1000

HD68000.HD68000Y-------------------------------------------------------------Absolute Long Addnss

fust extension word; the low-order part of the address is the
second extension word. The reference is classified as a data
reference with the exception of the jump and jump to subroutine instructions.

This address mode requires two words of extension. The
address of the operand is developed by the concatenation of
the extension words. The high-<>rder part of the address is the

EXAMPLE
MPU

MEMORY

COMMENTS
• EA - (Next Two Words)

• Machine Lavel Coding
NEG $014000

0100

0100

01~

=roo:.. k. ---.L..
NEG
Instruction

OWL
NEG $014000

Absolute
Long

4479

OWL + 2

1-__..:.°00;;.;;.,;1__-1
OWL + 4 1-__...;.400;;.;;.,;0__-1

Program Counter With Displacemant
This address mode requires one word of extension. The
address of the operand is the sum of the address in the program
counter and the sign-extended 16-bit displacement integer in

the extension word. The value in the program counter is the address of the extension word. The reference is classified as a program reference.

EXAMPLE
MPU

MEMORY

COMMENTS
• EA (PC) + dl6
• d .. is Sign Extended
• Machine Laval Coding

=

MOVE (LABEL). 00

I

Move
Word

MOVE (LABEL), 00
ADDRESS
CALCULATION:
PC = 0000B002
d = 00001000 < LABEL> $9002
00009002

1----------1

148

-----------------------------------------------------------------HD68000,HD68000Y
Program Counter With Index

This address mode requires one word of extension. This
address is the sum of the address in the program counter, the
sign-extended displacement integer in the lower eight bits of
the extension word, and the contents of the index register.
The value in the program counter is the address of the extension
word. This reference is classified as a program reference.

EA = (PC)

+ (Rx) + d •.
(NOTE)

Extension Word
7654320
Displacement Integer
Beginning }
Addr... of
PC + d.
Data Table
Desir<:d D!,ta
LocatIon In Table

D/A
: Data Register = 0, Address Register = 1
Register: Index Register Number
W/L
: Sign-extented, low order Word integer
in Index Register = 0
Long Word in I ndex Register = 1

I PC + d• + Rx

EXAMPLE
MPU

MEMORY

IXXXX3456IDO

$8000

~

$8002~

;;;:;)
+ Om • (Om_' + ... + Om_,)
C

0

= Dm~r+1

0

C = Dm _r+1

0

?

0

0

0

?

C=X

0

?

C = Dm _r+1

0

0

0

?

0

0

0

?

C=X

0

?

C -0,_1

0

0

• General Case:
X=C
N = Rm
Z = Riii· ...

om .

• i'Ili

C =0,_1

Sm - Source operand molt lignificant bit
Om - DeBtinatlon operand most significant bit
Rm - Result bit mOlt lignificant bit
n - bit number
r

156

- shift amount

-----------------------------------------------------------------HD68000,HD68000Y
•

CONDITIONAL TESTS

Table 23 lists the condition names, encodings, and tests
for the conditional branch and set instructions. The test associated with each condition is a logical formula based on the
current state of the condition codes. If this formula evaluates to

1, the condition succeeds, or is true. If the formula evaluates to
0, the condition is unsuccessful, or false. For example, the T
condition always succeeds, while the EQ condition succeeds
only if the Z bit is currently set in the condition codes.

Table 23 Conditional Tests
Mnemonic
T
F

HI
LS
CC
CS
NE
EQ
VC
VS
PL
MI
GE
LT
GT
LE

•

Condition

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

not equal
equal
overflow clear
overflow set
plus
minus
greater or equal
less than
greater than
less or equal

INSTRUCTION SET

The following paragraphs provide information about the
addressing categories and instruction set of the HD68000.
•

Encoding

true
false
high
low or same
carry clear
carry set

Test

1
0
C·Z
C+Z
C
C

'Z
Z

V
V
N
N
N·V+N·V
N·V+N·v
N·V·Z+N·V·Z
Z+N·V+N·V

memory or data alterable. The former refers to those addressing modes which are both alterable and memory addresses, and
the latter refers to addressing modes which are both data and
alterable.

ADDRESSING CATEGORIES

Effective address modes may be categorized by the ways
in which they may used. The following classifications will
be used in the instruction definitions.
If an effective address mode may be used to refer
Data
to data operands, it is considered a data addressing effective address mode.
If an effective address mode may be used to refer
Memory
to memory operands, it is considered a memory
addressing effective address mode.
If an effective address mode may be used to refer
Alterable
to alterable (writeable) operands, it is considered
an alterable addressing effective address mode.
Control
If an effective address mode may be used to refer
to memory operands without an associated size, it
is considered a control addressing effective address
mode.
Table 24 shows the various categories to which each of the
effective address modes belong. Table 25 is the instruction set
summary.
The status register addressing mode is not permitted unless
it is explicitly mentioned as a legal addressing mode.
These categories may be combined so that additional, more
restrictive, classifications may be dermed. For example, the
instruction descriptions use such classifications as alterable

•

INSTRUCTION PRE-FETCH

The HD68000 uses a 2-word tightly-coupled instruction
prefetch mechanism to enhance performance. This mechanism
is described in terms of the microcode operations involved.
If the execution of an instruction is dermed to begin when the
microroutine for that instruction is entered, some features of
the prefetch mechanism can be descnbed.
1) When execution of an instruction begins, the operation
word and the word following have already been fetched.
The operation word is in the instruction decoder.
2) In the case of multi-word instructions, as each additional word of the instruction is used internally, a fetch
is made to the instruction stream to replace it.
3) The last fetch from the instruction stream is made when
the operation word is discarded and decoding is started
on the next instruction.
4) If the instruction is a single-word instruction causing a
branch, the second word is not used. But because this
word is fetched by the preceding instruction, it is impossible to avoid this superfluous fetch. In the case of
an interrupt or trace exception, both words are not used.
5) The program counter usually points to the last word
fetched from the instruction stream.

157

HD68000,HD68000Y----------------------------------------------------------------Table 24 Effective Addressing Mode Categories
Effective
Address
Modes
On
An
An@
An@+
An@An@(d)
An@(d,ix)
xxx.W
xxx.L
PC@(d)
PC@(d,ix)
#xxx

Mode

Register

Data

000
001
010
011
100
101
110
111
111
111
111
111

register number
register number
register number

-

X
X
X
X
X
X
X
X
X
X
X

register number
register number
register number
register number

000
001
010
011
100

Addressing Categories
Memory

Control

Alterable

-

X
X
X
X
X
X
X
X
X

-

X
X
X
X
X
X
X
X
X
X

-X
-

X
X
X
X
X
X

-

--

The following example illustrates many of the features of
,instruction prefetch. The contents of memory are assumed to
be as illustrated in Figure 53.
ORG

o

DEFINE RESTART VECTOR

DC.L
DC.L

INiSSP
RESTART

INITIAL SYSTEM STACK POINTER
RESTART SYSTEM ENTRY POINT

ORG
DC.L

INTVECTOR
INTHANDLER

DEFINE AN INTERRUPT VECTOR
HANDLER ADDRESS FOR THIS VECTOR

ORG

SYSTEM RESTART CODE

RESTART:
NOP
BRA.S
ADD.W

NO OPERATION EXAMPLE
SHORT BRANCH
ADD REGISTER TO REGISTER

LABEL
00,01

LABEL:
SUB.W
CMP.W
SGE.B

INTHANDLER:
MOVE.W
NOP
SWAP.W

DISP(AO), A1
02,03

SUBTRACT REGISTER INDIRECT WITH OFFSET
COMPARE REGISTER TO REGISTER
See TO REGISTER

07

LONGADR1, LONGADR2

MOVE WORD FROM AND TO LONG ADDRESS
NO OPERATION
REGISTER SWAP

Figure 53 Instruction Prefetch Example, Memory Contents

The sequence we shall illustrate consists of the power-up
reset, the execution of NOP, BRA, SUB, the taking of an
interrupt, and the execution of the MOVE.W xxx. L to yyy.L.

The order of operations described within each microroutine is
not exact, but is intended for illustrative purpose only.

158

HD68000,HD68000Y
Microroutine

Operation
Read
Read
Read
Read
Read
Read

Read

PC=PC+d
Read
Read

Read
Read
Read

Write
Read
Write

Reset

NOP
BRA

SUB

INTERRUPT

Write
Read
Read
Read
Read

Read
Read
Read
Read
Write
Read
Read


MOVE

Location

Operand

2
4
6
(PC)
+(PC)

SSP High
SSP Low
PC High
PC Low
NOP
BRA

+(PC)

ADD

(PC)
+(PC)

SUB
DISP

+(PC)
DISP(AO)
+(PC)

-(SSP)

-(SSP)
-(SSP)
(VR)
+(VR)
(PC)
+(PC)

CMP

SGE

+(PC)
+(PC)
xxx
+(PC)
yyy
+(PC)
+(PC)

xxx Low
yyy High

yyy Low

NOP
SWAP

0

PC Low
Vector #
SR
PC High
PC High
PC Low
MOVE
xxx High

Figure 54 Instruction Prefetch Example

order to optimize performance. As a result, the processor reads
one extra word beyond the higher end of the source area. For
example, the instruction sequence in Figure S5 will operate as
shown in Figure 56.

• DATA PREFETCH

Normally the HD68000 prefetches only instructions and not
data. However, when the MOVEM instruction is used to move
data from memory to registers, the data stream is prefetched in

A
B
C
D
E
F

MOVEM.L

A, DO/D1

MOVE TWO
LONGWORDS
INTO REGISTERS

DC.W
DC.W
DC.W
DC.W
DC.W
DC.W

1
2
3
4
5
6

WORD 1
WORD 2
WORD3
WORD4
WORD 5
WORD6

Assume Effective Address Evaluation is Already Done

MOVEM

Microroutine

Figure 55 MOVEM Example, Memory Contents

Operation

Location

Read

A

Read
Read

B
C

Read
Read

D
E

Other Operations

Prepare to Fill DO
A-+DOH
B -+DOL
Prepare to Fill D1
C-+D1H
D -+D1L
Detect Register List Complete

Figure 56 MOVEM Example, Operation Sequence

159

HD68000,HD68000Y-----------------------------------------------------------------

-.
Operation

Mea

Idd()glls

Table 25 Instruction Set

B'.

BInary

1

-

Add Address

AIIDI

Add Immed

•
1

B'W

1
B'W

Add QUick

1

AIIDX
Md Multi

BfW

preClston

1

AIID

B!W

Loglcal.o'lld

1

NIDI

B"

.\ld Immed

1

ASL, ASR

B'.

Arithmetic

911ft

l

Memory

W

10K

B

Test and
Cllange

1

10111

B

Test and
Oear

1

ISET
Test and

B

Set

1

ITST

B

&1 Test

1

CH.
ClleckReg·

Isler Agamst
&unds
CIII

aear {\Ierand

a...

Compare
Binary

a... A

•

s:(}1

u••

,

~

# 1-

L,

2'1

IOOA

~I

8
8
8

IOOA
IOOA

•

2'
2

8

1
2
2
2
2
1
4
6
2
2

2
2
2
2

,

•

6

11
8

20
14
12
14
16

28
12
20

#

1
2
2
2
2
2
4
6
2
2

11
8

20
14
12
14
16
18
12
20

-(An)

12
8
10
14
16
2B

2
2
2
2
4
6

11

8
20
14
16
28

diAn)

#

-

#

2
2
2
2
2
2
2
4
6
2
2

lB
14
10
22
16
14
16
18
30
14
22

,,
,,
,

18

6
8
4
4

20
32
16
2.

2
2
2
2
2

,
6

4

16

12
24
18
16

2'
2
4

,
2

,

,
2

2

•

,

30
I'
10
12
16
18
30

,

4

16
12
14

,•

18

6
8

20
32

4

,

14
14
18

,

4'
6

16
16
2il

6
8

20
2'

8
12

,2

8
12

2

10
I'

4
6

12
t6

4
6

14
t8

4

6

f2
16

6
8

16
2il

•

<44
2

1.

<46

16
20

'16

•

12
f6

d,
d, 6
d
d'

8
14

6

12
20

6
2
2

12
20
11
20

,

l

Hf'

dlsp-lmm

4

12

4
4
4

18
16
18

#

,
,
4
4

-

•

12

4

18

4

-

14

4

20
18
10

•

,

14
10

1100
1100
110 I
110 I
110 I
110 I
110 I
110 I
0000

8

6

12
"
I.

6

4

,
6

8
14
20

17
20

,,

6

,

4

6

,

6
6
6
6

20

12
18

<48

,
6

,

18

22

18

12
16

14
f8
<50

<44
4

20

,.

*u*u*

d+{)l'~d

•••••

liIt-s-Dl
d...-[)J ..... d
liIt"s-i>l
o'\1...-s .... /Ji!
d -t- :If.--d

** •••

0101 QQQO

SSEE EEEE

d .... 'tl:--d

"''''''''''II'

101 RRRI
10 I RRRI
101 RRRI
101 RRRI
100 0001
100 DODO
1000001
100 DODO
00000010

55000rrr
S500lrff

d-l-s+X ·d

.* •••

dD1 ........d

-**00

.. _6.

1000 Urn

1000
SSEE
55ee
1OEE

I rrf
EEEE
eeee
EEEE

D'ls....... [)]
dliI........ d

IDee uee

Dls ....... 1))

SSEE EEEE

d1t:--od

~~o

~i

-(MI# of d-l.
-(b"I# 01 d-

-**00

*****
- - *--

(bit):!:*: of d
-(bit)#: of d--Z,

~ ~

O-(b;t)# of d
-(bit)#ofd-Z,
l-(btl)# old

* -

..
~

-- -

-(blt)# ofd-Z

- ~ * --

If [))(bound),

-*UUU

then trap

d--+MPU

()-od

- 0100

I»-s

6

•

10
14

1011 AAAO
1011 MAl

II ee e e e~
II ~ e e ~ ee

M-S

-****
-••• *

00001100

SSEE EEEE

d-#

-

1011RRRI

5500 I rrr

d-s

- ••• *

2 <162 2 <162 2 <164 4 <166 4 <168 4 <166 6 <170 4 <166 4 <168 4 <162

1000 0001

11ee eeee

2 <144 2 <144 2 <146 4 <148 4 <150 ,

1000 DODO

1l132fsl6-"
1»(",1
Ilee eeee 1l132!slr
1»(",1

10 II r rr I

SSEE EEEE

d.lJn-d

-**00

00001010

SSEE EEEE

d. #--d

- •• 00

0100
0100
1000
1000
1100
Ilee

,-d

-----

,

,

8
16

4
6

16
28

4

16
28

6

,
6

2
2

6

,

I'
22

14

22

,•
•

16
24
12
18

6
8

16

4

4

1.
18

24

4

18
26
I'
2il

,•

16
2il

,,•
,
4

12
18

6
6

18
22

6
8

18
26

6
8

16
24

8
10

20
28

4

4

22

,

16
24

,,

18
30

6
8

20
32

6
8

14

16
24

28
f6
21

•
,,
4

12
18
14
18

•
,
4

14
20

4

16
20

,
6

<148 6 <1524 <148 4 1
IIUUI
.Multlply
titSlgned
IICO
B
Nelale 011111
B'.
IIC
M!rate.lJinary l
1111
B'W
M!rale Multi· L
pretlSlon

B/.
l

•

•
•
4
4

•
2
2
2
2
2
4

••
••

2
8
12 2
8 ,'"

d

s:[h

•
•

MOV£A

••

12
8
8
12
12

S:Xn

l

lolltal

#

12 2'
8 2
8 2
12 2
12 2
14 2
16
18 4
16 4
20 6
16 4
18
12 4
12 1
12 2
20 2
20 2
22 2
24 4
26 4
24 4
28 6
24 4
26
6
20
16 2

2'
2
2
2
2
2

d:Xn

•

10'

-

•
•

_VIP
Move
Peripheral

IIUIS

MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEI
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOV£A
MOVEA
MMI
MMI
MOVEA

"

Move 10 'from

MOn

#

-

B/. s;!)!

Inclusive(JI
lolleal

#

-

#

12"'411

•

•
•

•

8
12

1
1

14 4'
8 4
8 4
12 4
12 4
14 4
16 6
18 6
16 6
20 8
16 6
18 6
12 6
12
12 4
20
20
22
24 6
26 6
24 6
28 8
24 6
26 6
20 8
18

16 4'
12 4
12 4
16 4
16 4
18
20 6
22 6
20 6
24 8
20 6
22 6
16 6
16 4
16 4
24
24 4
26
28 6
30 6
28 6
8
32
28 6
30 6
24 8
10

18
14

10
16

•
••
•

-

-

#

Abs.L

#

-

-

-

-

1110 rrrf
1110 QQQf
1110 rrrf
1110 QQQf
1110001 f
DOSS RRRM

5510
5500
1010
1000
IIEE
MMee

16

0100 0100

•
•

2 <70

2 <74 2 <74 1 <76

2
2
2
2

d- 2
d, 2

16

14

Olt
8"
(l'lmmediate l
l
PIA
PIlshEffect·

d,

,-

•

<8Il

16

4

18

16
24
16
24

••
•

18
26
18
26

12

2

14

12

6
4
6

20

2
1
1
2

14
22
14
12

4
4
4

•6

2
2

12
20

2
2

12

2
2

14
22

4
4

16
14

4
4

2
2
1
1
4
6
2

12
8
20
1\
16

2
2
2
2

12
8
20
I'
16

14
10
22
16
18

•
•

16
12
24
18

4

6

JO

2
2
2
2
4
6

2
d' 4
d, 6

8
8
16

"

•
•

•

<78

2
2
2
2

~1>1

Solmm
s:lmm

•

<8Il

2

•

"

JO

•

<78

12
20
12
20

2

10
16

6
6

16

11
20
20

•

14

32

•

4
4
6
8
4

20

34
18

4

••

4
6
8
4

•
•
•

Ilee teee

, 'CCR

••• **

01000110
0[00 0000

Ilee tete
IIEE EEEE

, 'SR

*••••

0100 1110
0100 1110

0110 IAAA
0110 OAAA

iJSI'-o'"
'" .usp

0011 AMO
0010 MAO
01001000
a7-.0
0100 1100
17- aD
0100 1000
a7- aO
0100 1100
a7- .0
00000001
00000001
00000001
0000 DOD I
01110000

Olee eeee
Olee eeee
10EE EEEE
d7- dOt
IDee eeee
d7-dO
IIEE EEEE
d7-dOt
Ilee eeee
d7- dO
1000 lAM
0000 I AAA
1100 IAAA
0100 IAAA
QQQQ QQQQ

<8Il 4 <74

1100 0001

Ilee eeee

!lOP1

----- •• 00

·d

.u.u.

6

20

0100 1000

OOEE EEEE

O~dlO-X

20

0100 0100

S5EE EEEE

O-d ·d

•

28
20
28

0100 0000

5SEE EEEE

O-d- X "d

4

6
6
6
6

18
26

4
4

16
24

6
6

20
28

01000110

S5EE EEEE

-d ·d

- •• 00

18
I'
26
10
22
36
22

4
4
4

16
12
24
18

6
6
6
6
8
10
6

20
16
28
22
24
38
22

10000001
1000 DODO
10000001
1000 DODO
0000 0000

55EE
SSu
IDEE
IDee
S5EE

d{)I---d
i}\s--Bl
dD'l ......d
OI1s-"'Q,
d:Ii ......d

- •• 00

0100 1000

01 ee eeee

,'·-(SP)

-----

1110 rrrf

5511 1000

1110 QQQf
1I10ud
1110 QQQf
1110 011 f

SSOI
lOll
1001
II EE

•

6
8
4

20

34
18

•
•
•

12

•

14

18

4

10

18

4

•
6
4

8

14

20

22

EEEE
!tee
EEEE
eeee
EEEE

18 4'

16 6'

20

IDDD
I DOD
IDDD
EEEE

~c

•••••
•••••

- •• 00

- •• 00

c'19i:;J

Opcode Bit PaHem Key

Nat.: Ref., to"Condition Code Computilloos"
*;WonI

16 4'

-----

16

6+10
6+10
8+10
8+10
2'

-----

d-MPU
SR-"d

16
24
16
24

4
4

IveAddreSS

"I, III

O~i

••• 0*

20

16

12

d,

4
4

~:J5=l-0

e_

XNZVC

-.* 0 0

24

2
2
2
2

•

.1>1

~1>1

l

••

2

6

22
18

IDDD
IDDD
IDDD
IDDD
EEEE

C.....I .

, 'd

6 16"'8/1 6 18 ... 1J1 6 16+& 8 10,& 6 16"'811 6 18+&

12<& 412tBn

2 <74 2 <74 1 <76

d,
d,
d,
d,

••

••
•

20
16
16
20
20
22
24
26
24
28
24
26

4 8"'&1 6 12·8n 614"8n 6 12"'Sn 8 1'"80

2 <70

d, 2

•

•

16 6'
12 6
12 6
16 6
16 6
18 6
20 8
22 8
20 8
24 10
20 8
22 8
16 8
16 6
16 6
24 6
24 6
26 6
28 8
30 8
28 8
32 10
28 8
30 8
24 10
10 6

....-

.,n

0,..... all ' ...
d(PC) d(PC.XI) s billed
d=SR/CC 111111
#
#
#
5432 1098 76543210

6 16 .." 6 18 .. 40 6 16+40 8 10,. 6 16.o-.fn 6 18+4n

12·411

•
• •
,
"

•
•

••

d-

ddd_
d, 2

•
••

•

18 4'
,14 4
14 4
18 4
18 4
20
22 6
24 6
22 6
26 8
22 6
24 6
18 6
18
18
26 4
26
28 4
30 6
32 6
30 6
3' 8
30 6
32 6
26 8
22 4

10
11
14 4 12
16
18
16
I'
4 8l--4n 6 IZ+4n 6 14 .. 4n 6 12"4

2
2

Qlmplement

II

deAn) d(A.,Xi) Abs.W

count:Ol

•

MOVI

-

-(An)

d, 2 6+211

d, 2 8+211
counMtl-8d= 2 8+211
d,
count-l
BfW s=DI
d' 2 4
2 4
~'"
,,("')
d' 2 8
,,( .. ) + d' 2 8
,,-("')
d' 2 10
"d("')
d' 4 12
"d("'_X) d, 4 14
d, 4 12
s:Mls .•
d, 6 16
s=M!s.l
d, 4 12
"d(PC)
"d(Pl:X) d, 4 I'
s=lmm
8
d' 4
d- 2
l s=D!
d, 2 4
s="
d, 2 12
,,("')
,,( .. ) + ~ 2 12
d, 2 14
("')
d, 4 16
"d("')
18
"d("'_X) dd, 4 16
s=AbsW
d, 6 20
s=.lbs.l
d,
16
"d(PC)
ds=d(PC,X)
18
d- 6 12
s=Imm
d:CCR
2 12
l

Move 10 Con·

#

(An) +

countdU-8d= 2 6+211

lolical9llft
Memory
IIOVI
Move Data

count::Ol

#

(An)

An

On

Mol••

Operation II.

f: Direction: O-Rithl. I-Left
M: Destination fA Mode
P: Displacement
Q: QUICk Immediate Data

r:Source Rellstet"

EA+2~.

R: Destination Rells.ter
5: Size: OO-Byle
OI-Word
IO-LolII" WlII"d
ll-AlIOther OperatIon
V: Vector #

I" tile MOVE ln5tRlcllOn)
( 01-Byte

IO-Lone
ll-Word

Ward

(to be continued)

161

HD68000,HD68000Y----------------------------------------------------------------IIn_Dnic
II..
QJ)eration

RDXR.RDn 8. count,[)l
~tale

IhrnughX

L

Memory
SICD

•
8

Subtract

Binary

SUIA
Subtract

•
L

8.
L

Subtract
Multiprecisiotl

count'!
S"())

(In)

cc

do!l1
.!l1
"'!l1

SWAP

~,.,

s~lmm

1 64

1

•

1
1
1

8
8
8

"'0
"'0

s,lmm

8. $=01
(In)
So!))
s: (hi)

S'

W

Test

,,"
,
"

,
,

8

Test and Set
Qlerand

TST

-(An)
#

-

d(An)

#

-

d(An,Xi) Abs.W

#

-

-

#

Abs.L

d(PC)

#

#

-

d(PC.Xi)

#

-

s Immed

d=SRfC
#

8W

'0

l

U...

12

4

11

l'

l'

14

1

18

4'

16

4'

18 4'

16 6'

6

8
16

1
1

4
8

1

4

1

8

1

4

1

4

1
1

SlJlA

•

1'1
SJiA
8
8
8

II

SUiA
SUiA
4

l'
1

8

1

11

1

12

1

I'

1
1
1
1
1
1

11
8
20
I.
11

11
8
10
I.
11

1
1

14
10
11
16

14

1
1
1
1
1
1

4

6

16
28

4
6

16
18

6

1
1

11
16

1
1

11
16

1
1
1

18

1

30

1

4

14

1
1

4

1

8
11

14

14

1
1
1

8
11

1

1
1
1
4

1
2

1

•
4

16

4

••

18

4

16
11
14
18
16
18

18
30

6
8

10
31

6
8

11
34

14
11

4

16
2'

4
4

18
16

14
16

16
10
14

•
4
4
4

•

4
4
4

18
I.
16
10
18
10

4

•
4

•
4
4
4

•
6
8

,
•

1000 RRRI

4
4

18
11
16

4

•
4

20

4

14

,

18

4

Branch
Conditionally

III
Branch
Always

ISR
Bran ell
to Subroutine

alcc
Decrement
Counter. &
Branchlkltll
Condition
True or

Count= 1

'"'

Jump to

,SR

Jump to
Subroutme

.OP

dlOslOX ·d

*U*U*

1 lEE EEEE

- --

16
11
14
18
16
18

6
6
6
6
6
6

10
16
18
11
10

0001
DODO
0001
DODO
AAAO

SSEE EEEE
SSee uee
I DEE EEEE
IOee uee

d-MPU
Ilcctrue,l's ·d
Else,Q's ·d
d·r:n ·d
iii s-+1l1
d!l1·d
Il1 s"{),

llee eeee

10
31

8
10

16

6
6

24

18

4

8

6

14

4

11
14

1001 AAA!

Ilee teet

'" s ~kl

.....

6

14
36

0000 0[00

SSEE EEEE d:::r: ·d

*****

10
18

0101 QQQI

SSEE EEEE d:t 'd

*****

100 I RRRI

5500 Orrr d s X ~d
5500 1r rr
1000 Orrr
1000lrrr
0100 0000 !l1(3116)-~
!l1(150)

*****

II EE EEEE testd ·cc

- •• 00

•
4
4

11
18
16
18

•
4
4

•

11

6
6

RRRI
RRRI
RRRI
1000

01001010

16
10

12

8

dISP'
dlsp

B

dlsp
dlsp,

•
B

••

bra
bra not
bra
bra not

taken
taken
taken
taken

1
1

,

10
8
10

SSEE EEEE lestd· ... cc

- .*0 0

0100 1110

0101 IAAA "'-'SP.

-----

0110

ecee

14
10
10

0110 0000

pppp pppp PC+dlsP .. pc

4

~ISpo

1

10

0110 0001

pppp pppp

dlsp

4

10

pc, (SP)

~

~

-- -

- -- ~

-

--

~

-

PC.J-dlsP"'PC
dlspclmm

cc

counter,

10

• I1 i~

false
true
false

'0
'0

Clunt.r
1
, 1

,

expired

Branch

010 I

,es

ecce

1100 1000 II cc false
1-+1)) & If
1.PC+d!sp---PC
Else.r«P

/)!

no
no

-----

[)P<

1

8

4

10

4

14

1

16

•

18

•

21

,
•

10

6

12

4

10

4

14

0100 1110

IIEE EEEE ,-pc

18

6

·'0

4

18

4

22

0100 1110

10EE EEEE pc, (SP) , .pc

- -----~

~

1

4

0100 1110

01110001

none

1

131

01001110

01110000

assert RESET pm

-- .
- ---

1

10

0100 1110

01110011

(SP)

+

'50

(SP)

+

*.**.
.****

~

,pc

1

10

0100 1110

0111 0111

(51') + 'IX:.

1

16

01001110

0111 0101

(SP) + ,pc

0100 1110

0111 0010

#: "'SR.Walt for
Interrupt

1

34

01001110

0100 VVVV PC-(SSP).

•

Trap

1

34 Trap taken
4 Trap not
I.kj

Noh: Refer to-CoMitlon Code Computations'
as lor conCitlon Code
Word only
<: Ma~imum value
#;Number of Program Bytes
-:Numbef of Clock Penod$

*

I!cctrue
PC+dlsP ... pc

4

ITO'

Trap If
OmfiowSet

pppp pppp

~An

1

LoadSRlStop

nary

-**00

0100 1010

(SP) +

•

•• ***

14

4

l ... blt7ofd

12
16

~

10
18
10

12

6

~

100 I
100 I
100 I
1001
100 I

Return from
Subroutine

TRAP

0000 Orr r

0000 Irrr

Return from
SIIbroutme l
Restore OC

RTt

***0.

eeee

Return from
ucephon

In

r~,;
~x"J9n1

010 I

Reset Exter·
nalDevlces

IITI

DODD
DODD
DODD
DODD
EEEE

20

rt~eratlon

RIIIT

SSII
SSO I
1011
1001
I lEE

e....

XNZVC

6

Lklhnk

I ••

C...,,,..

16

100!
1001
100 I
0100
4

.......

Opoodo 1ft ' ..tern
111111
54321098 ~654 3210

1110 QQQI
1110 0101
1000 RRRI

20

6

So

So

Swap Regis·
terHalves

TlS

-

#

tllO rn f

l'

1

So
So

"'In

B W s,lmmJ
L s"lmm3

l

(An)+

1110 rr rf

~Ick

SUIl

-

#

1110 QQQI

Mdress
SUll
Subtract
Immediate
SUI'
Subtract

-

#

1 8+2n
CQulll'#1-8d= 1 8+1n

B'W s=[),
L

'0
'0
''00
'0
'0
'0
'0

(An)

An

-

1 6+1n

counl~D'I

S'

8

#

counl,#\-8(1o 1 6+1n

digits

Scc
Sol
Conditionally
SUI
Subtract

On

Add••
I.....

4

0100 1110

0111 0110

(SP) + ,pc

SIH (SSP)
(Vector) ~PC
IfHIIIeIIPC"

,(SSP) SR - iSSpl
(TIlAPVYftIor}'PC

ehe.NOP
Opcode Bit Pattern Key
A: Address Register #
C:TestCondltlon
0: Data Register #
e;SourceEllectlveAddtess
E:DestlnatlonEffe<:tlveAddress

f,Dlrectlon.O-Rlght.l-left
M:Oestlllatlon EA Mode
P:Dlsplacement
Q. QUICk Immediate Data
r.Source RegIster

162

R. Destination Register
S. Slze.OO-Byte
D)-Word
IO-Long Word
ll-Another OPt'ratlon
V.Vectorlt

III the MOVE IlistructlOIl]
( Ol-Byte
lO-lonS Word
ll-Word

~

~

~

.. ~

*.***
- --~

-----

----------------------------------------------------------------HD68000,HD68000Y
•

INSTRUCTION FORMAT SUMMARY
This provides a summary of the first word in each instruction
of the instruction set. Table 26 is an operation code (op-code)
map which illustrates how bits 15 through 12 are used to
specify the operations. The remaining paragraph groups the

instructions according to the op-code map.
where, Size; Byte = 00
Sz; Word = 0
Word = 01
Long Word = 1
Long Word =10

Table 26 Operation Code Map
Bits
15 thru 12
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Operation
Bit Manipulation/MOVEP/lmmediate
Move Byte
Move Long
Move Word
Miscellaneous
ADDOISUBOISee/DB ee
Bee
MOVEa
OR/DIV/SBCD
SUB/SUBX
(Unassigned)
CMP/EOR
AND/MULIABCD/EXG
ADD/ADDX
Sh itt/Rotate
(Unassigned)

(1) BIT MANIPULATION, MOVE PERIPHERAL, IMMEDIATE INSTRUCTIONS
Dynamic Bit
15

14

13

12

0

0

0

0

15

14

13

12

0

0

0

0

11

8

9

10

I

Register

7

1

6

5

4

Type

3

2

0

Effective Address

Static Bit

I

I

11

I I
1

10

9

0

0

7

8

I

0

6

5

4

Type

3

0

2

Effective Address

Bit Type Codes: TST = 00, CHG = 01, CLR = 10, SET = 11
MOVEP
15
0

I

14

13

12

0

0

0

Op-Mode; Word to Reg

11

10

9

8

Register

= 100, Long to

6

7
Op-Mode

Reg

5
0

4

3

I I
0

2

1

0
Register

= 101, Word to Mem = 110, Long to Mem = 111

OR Immediate
15

14

13

12

0

0

0

15

14

13

0

0

0

I I I
0

I

11

10

0

0

11

10

I

9

8

0

0

9

8

1

0

7

6

5

4

3

2

0

Effective Address

Size

AND Immediate

I

12

I I I I
0

0

0

163

'"I

7

6
Size

5

4

3

2

Effective Address

0

HD68000,HD68000Y
SUB Immediate
15

14

13

12

11

0

0

0

0

15

14

13

12

11

I I

0

0

0

0

14

13

12

11

0

0

13

12

0

0

I I
0

10

9

8

0

0

9

8

7

6

5

4

Size

3

2

0

Effective Address

ADD Immediate

0

10

7

0

6

5

4

Size

3

0

2

Effective Address

EOR Immediate
15

I I0
0

10

9

0

8

7

0

6

5

4

Size

3

2

0

Effective Address

CMP Immediate
15

14

I0 I0

11

10

9

8

0

0

9

8

7

6

5

4

Size

3

0

2

Effective Address

(2) MOVE BYTE INSTRUCTION

MOVE Bvte
15

14

13

12

11

10

6

7

5

4

3

Destination

Register

2

0

Source

Mode

Mode

Register

(3) MOVE LONG INSTRUCTION
MOVE Long
15

14

13

12

11

10

9

8

7

6

5

4

3

Destination
Register

2

0

Source
Mode

Mode

Register

(4) MOVE WORD INSTRUCTION
MOVE Word
15

14

13

12

11

10

9

8

7

6

5

4

3

Register

0

2

'Source

Destination
Mode

Mode

Register

(5) MISCELLANEOUS INSTRUCTIONS
NEGX
15

14

I

0

13

12

11

10

9

8

0

0

0

0

0

0

13

12

11

10

9

8

0

0

0

0

0

0

13

12

11

10

9

8

0

0

0

0

7

6

5

4

Size

3

2

0

Effective Address

MOVE fromSR
15

14

0

6

7

5

4

3

2

0

Effective Address

CLR
15
0

14

0

164

7

6
Size

5

4

3

2

Effective Address

0

~------------------------------------------------------------H068000.H068000Y

NEG
15

o

14

13

I1

o

12

I0

11

o

10

9

8

I1 I0 I0

7

6

5

o

432

Size

Effective Address

MOVE loCCR
15

o

14

13

12

11

10

9

8

7

6

I1 I0 I0 I0 I1 I0 I0 I1 I1

5

4

3

2

1

0

Effective Address

NOT
15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

Effective Address

Size

MOVE toSR
15

o

14

13

I1 I0

12

11

10

9

8

7

6

5

o

432
Effective Address

NBCO
15

14

13

12

11

10

9

8

7

6

5

4

I0 I1 I0 I0 I1 I0 I0 I0 I0 I0

3

2

0

Effective Address

PEA
15

o

14

13

I1 I0

12

11

10

9

8

7

6

5

o

432
Effective Address

SWAP
15

14

13

12

11

10

9

8

7

6

5

4

3

2

10111010111010101011101010

0
Register

MOVEM Registers to EA
15

14

13

12

11

10

9

8

7

6

5

4

I 0 I 1 I 0 I 0 I 1 I 0 I 0 I 0 I 1 I Sz

3

2

0

Effective Address

EXTW
15

o

14
11

13

12

11

10

9

8

7

6

5

4

3

10

10

11

10

10

10

11

10

10

10

10

13

12

11.

10

9

8

7

6

2

0
Register

EXTL
15

14

543

o

2
Register

TST
15

o

14

13

12

11

10

9

8

I1 I0 I0 I1 I0 I1 I0

7

6
Size

5

4

3

2

0

Effective Address

TAS
15

14

13

12

11

10

9

8

7

6

543

2

Effective Address

165

o

HD68000,HD68000Y-------------------------------------------------------------MOVEM EA to Registers
15

14

13

12

11

10

9

8

7

6

I 0 I 1 I 0 I 0 I 1 I 1 I 0 I 0 I 1 I Sz

5

4

3

2

0

Effective Address

TRAP
15

14

13

12

11

10

9

8

7

6

5

4

I0 I1 I0 I0 I1 I1 I1 I0 I0 I1 I0 I0

3

2

0

Vector

LINK
15

14

13

12

11

10

9

8

7

6

5

4

3

2

I 0 I 1 I 0 I0 I 1 I 1 I 1 I 0 I 0 I 1 I 0 I 1 I 0

0
Register

UNLK
15

14

13

12

11

10

9

8

7

6

543

2

0

Register

MOVE to USP
15

14

13

12

11

10

9

8

7

6

5

4

3

I 0 I 1 I 0 I 0 I 1 I 1 I 1 I O· I 0 I 1 I 1 I 0 I 0

2

0
Register

MOVE from USP
15

14

13

12

11

10

9

8

7

6

5

4

3

2

10111010111111101011111011

0
Register

RESET
15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

10111010111111101011111110101010

NOP
15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

10111010111111101011111110101011

STOP
15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

10111010111111101011111110101110

RTE
15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

1011101011111110011111110101111

RTS
15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

10111010111111101011111110111011

TRAPV
15

14

13

12

11

10

9

8

7

6

5

10111010111111010111 1

166

4

3

2

1110111 1

0
10

-----------------------------------------------------------------HD68000,HD68000Y
RTR
15

14

13

12

11

10

9

8

7

6

5

4

15

14

13

12

11

10

9

8

7

6

5

4

3

2

o

3

2

o

JSR
Effective Address

JMP
15

14

13

12

11

10

9

8

7

6

4

5

3

o

2

Effective Address

CHK
15

14

13

12

11

10

9

8

7

6

5

3

4

o

2

Effective Address

Register

LEA
15

14

13

12

11

10

9

8

7

6

4

5

Register

3

o

2

Effective Address

(6) ADD QUICK, SUBTRACT QUICK, SET CONDITIONALLY, DECREMENT INSTRUCTIONS
ADDQ
15

14

13

12

11

10

9

8

7

I0

Data

6

4

5

3

o

2

Effective Address

Size

SUBQ
15

14

13

12

11

10

9

8

6

7

I1

Data

5

4

3

o

2

Effective Address

Size

Sec
15

14

13

12

11

10

9

8

7

6

5

3

4

I1 I1

Condition

o

2

Effective Address

DBee
15

14

13

12

11

10

9

8

7

6

5

4

3

2

0
Register

Condition

(7) BRANCH CONDITIONALLY, BRANCH TO SUBROUTINE INSTRUCTION
Bee
15

14

13

12

11

10

9

8

7

6

5

Condition

4

3

2

o

2

o

2

o

8 bit Displacement

BSR
15

14

13

12

I0 I1 I1 I0

11

o

10

I0

9

o

8

I1

7

6

5

4

3

8 bit Displacement

(8) MOVE QUICK INSTRUCTION
MOVEQ
15

14

13

12

11

10

Register

9

8

I0
167

7

6

5

4

3
Data

HD68000,HD68000Y
(9) OR, DIVIDE, SUBTRACT DECIMAL INSTRUCTIONS
OR

15

B

14

13

12

0

0

0

11

10

9

8

Register

7

6

5

4

Op-Mode

3

0

2

Effective Address

Op-Mode
L

'w

000 001 010
100 101 110

On V EA-+Dn
EA V On -+EA

DIVU
15

14

13

12

0

0

0

14

13

12

0

0

0

14

13

12

11

10

9

8

0

Register

7

6

I I
1

5

4

1

3

2

0

Effective Address

DIVS
15

11

10

9

8

6

7

I1

Register

5

4

I1

3

0

2

Effective Address

SBCD
15

10

11

9

8

7

6

5

4

3

Destination
Register

2

0

Source Register

RIM (register/memory): register - register = 0, memory - memory = 1
(10) SUBTRACT, SUBTRACT EXTENDED INSTRUCTIONS
SUB

15

14

1

0

I

13

12

I I

1

13

12

0

11

10

9

8

Register

7

6

5

4

Op-Mode

3

2

0

Effective Address

Op-Mode
L
Dn-EA-+Dn
010
100 101 110
EA-Dn-+EA
011 111
An-EA-+An

B
W
000 001

-

SUBX

15

14

11

10

9

8

6

7

5

4

3

Destination
Register

2

0

Source Register

(11) COMPARE, EXCLUSIVE OR INSTRUCTIONS
CMP

I

15

14

1

0

B

W

000 001
011

-

CMPM

I

15

14

1

0

15

14

13

12

I I

1

13

12

1

11

10

9

8

Register

6

7

5

4

Op-Mode

3

0

2

Effective Address

Op-Mode
L
Dn-EA
010
111
An-EA

I

11

1

10

9

B

I

Register

7

1

6
Size

5

4

0

0

5

4

3

I

0

2

1

Register

EOR
0

13

I I
1

12

11

1

10

9

8

6

7

Register

Size

3

2

0

Effective Address

(12) AND, MULTIPLY, ADD DECIMAL, EXCHANGE INSTRUCTIONS
AND

15

I

14

1

13

12

0

0

11

10

9

8

Register

Op-Mode
L
On A EA-+Dn
000 001 010
EA A On -+EA
100 101 110
B

7
Op-Mode

W

168

6

5

4

3

2

Effective Address

0

HD68000,HD68000Y
MULU
15

14

13

12

0

0

13

12

0

0

13

12

11

10

9

8

7

6

5

4

0

Register

3

2

0

Effective Address

MULS
15

14

11

10

9

8

7

6

5

4

Register

3

2

0

Effective Address

ABCD
14

15

11

10

9

8

7

6

5

4

3

2

0

Source Register

EXGD
15

14

13

12

11

10

9

8

7

6

5

4

3

2

Data Register

0

Data Register

EXGA
15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

Address Register

Address Register

EXGM
14

15

13

12

11

10

9

8

7

6

5

4

3

Data Register

2

0

Address Register

(13) ADD, ADD EXTENDED INSTRUCTIONS

ADD
14

15

13

12

11

0

10

9

8

Register

7

6

5

4

Op-Mode

3

2

0

Effective Address

Op-Mode
B

W

L

000 001 010
100 101 110
011 111

On + EA~Dn
EA+ On ~EA
An + EA~An

ADDX
15

14

13

12

11

10

9

8

7

6

5

4

3

Destination

0

2

Source Register

(14) SHIFT/ROTATE INSTRUCTIONS
Data Register Shifts
15

14

13

12

11

10

9

8

7

6

5

4

3

2

Count/Register

0
Register

Memory Shifts
15

I

1

14

13

12

11

0

0

10
Tvpe

9

8

7

6

d

Shift Type Codes: AS =00, LS = 01, ROX = 10, RO = 11
d (direction): Right =0, Left = 1
i/r (count source): Immediate Count = 0, Register Count = 1

169

5

4

3

2

Effective Address

0

HD68000,HD68000Y----------------------------------------------------------------

the time required to perform the operations, store the results,
and read the next instruction. The number of bus read and
write cycles is shown in parenthesis as: (r/w). The number
of clock periods and the number of read and write cycles must
be added respectively to those of the effective address calculation where indicated.
In Table 30 the headings have the following meanings: An =
address register operand, Dn = data register operand, ea = an
operand specified by an effective address, and M = memory
effective address oper~d.

.' INSTRUCTION EXECUTION TIMES

The following paragraphs contain listings of the instruction
execution times in terms of external clock (CLK) periods.
In this timing data, it is assumed that both me~ory read and
write cycle times are four clock periods. Any wait states caused
by a longer memory cycle must be added to the total fustruction time. The number of bus read and write cycles for each
instruction is also included with the timing data. This data is
enclosed in parenthesis following the execution periods and
is shown as: (r/w) where r is the number of read cycles and
w is the number of write cycles.

•

•

IMMEDIATE INSTRUCTION CLOCK PERIODS

The number of clock periods shown in Table 31 includes
the time to fetch immediate operands, perform the operations,
store the results, and read the next operation. The number of
bus read and write cycles is shown in parenthesis as: (r/w).
The number of clock periods and the number of read and write
cycles must be added respectively to those of the effective
address calculation where indicated.
In Table 31, the headings have the following meanings:
# = immediate operand, Dn = data register operand, An = address register operand, M =memory operand, CCR =condition
code register, and SR =status register.

(NOTE) The number of periods includes instruction fetch and all applicable operand fetches and stores.

EFFECTIVE ADDRESS OPERAND CALCULATION
TIMING
Table 27 lists the number of clock periods required to com-

pute an instruction's effective address. It includes fetching
of any extension words, the address computation, and fetching of the memory operand. The number of bus read and
write cycles is shown in parenthesis as (r/w). Note there are
no write cycles involved in processing the effective address.

• SINGLE OPERAND INSTRUCTION CLOCK PERIODS
Table 32 indicates the number of clock periods fOi the

• MOVE INSTRUCTION CLOCK PERIODS

Table 28 and 29 indicate the number of clock periods for
the move instruction. This data includes instruction fetch,
operand reads, and operand writes. The number of bus read
and write cycles is shown in parenthesis as: (r/w).

single operand instructions. The number of bus read and write
cycles is shown in parenthesis as: (r/w). The number of clock
periods and the number of read and write cycles must be added
respectively to those of the effective address calculation where
indicated.

• STANDARD INSTRUCTION CLOCK PERIODS
The number of clock periods shown in Table 30 indicates

Table 27 Effective Address Calculation Timing
Addressing Mode

Byte, Word

Long

Data Register Direct
Address Register 0 irect

0(0/0)
0(0/0)

0(0/0)
0(0/0)

Memory
Address Register Indirect
Address Register Indirect with Postincrement

4(1/0)
4(1/0)

Address Register Indirect with Predecrement
Address Register Indirect with Displacement

6(1/0)
8(2/0)

8(2/0)
8(2/0)
10(2/0)
12(3/0)

Register
On
An
An@
An@+
An@An@(d)
An@(d,ix)*
xxx.W

Address Register Indirect with Index
Absolute Short

10(2/0)
8(2/0)

xxx.L
PC@(d)

Absolute Long
Program Counter with Displacement

PC@(d, ix)*
#xxx

Program Counter with Index
Immediate

12(3/0)
8{2/0)
10(2/0)
4(1/0)

• The size of the index register Ox) does not affect execution time.

170

14(3/0)
12(3/0)
16(4/0) .
12(3/0)
14(3/0)
8(2/0)

-------------------------------------------------------------------HD68000.HD68000Y
Table 28 Move Byte and Word Instruction Clock Periods

Dn

An

An@

An@+

Destination
An@-

An@(d)

An@(d.ix)*

4(1/0)
4(1/0)
8(2/0)

4(1/0)
4(1/0)
8(2/0)

8(1/1)
8(1/1)
12(211 )

8(1/1 )
8(1/1)
12(2/1)

8(1/1)
8(1/1)
12(2/1)

12(2/1 )
12(2/1 )
16(3/1)

14(2/1)
14(2/1)
18(3/1)

xxx.W
12(2/1)
12(2/1)
16(3/1)

16(3/1 )
16(3/1 )
20(4/1)

An@+
An@An@(d)

8(2/0)
10(2/0)
12(3/0)

8(2/0)
10(2/0)
12(3/0)

12(2/1)
14(2/1)
16(3/1)

12(2/1 )
14(2/1)
16(3/1)

12(2/1)
14(2/1)
16(311)

16(3/1 )
18(3/1)
20(4/1)

18(3/1)
20(3/1)
22(4/1)

16(3/1)
18(3/1)
20(4/1)

20(4/1)
22(4/1 )
24(5/1)

An@(d, ix)*
xxx.W
xxx.L

14(3/0)
12(3/0)
16(4/0)

14(3/0)
12(3/0)
16(4/0)

18(3/1)
16(3/1)
20(4/1)

18(3/1)
16(3/1)
20(4/1)

18(3/1)
16(3/1 )
20(4/1)

22(4/1)
20(4/1)
24(5/1 )

24(4/1)
22(4/1)
26(5/1)

22(4/1 )
20(4/1)
24(5/1 )

26(5/1)
24(5/1)
28(6/1)

PC@(d)
PC@(d,ix)*
#xxx

12(3/0)
14(3/0)
8(2/0)

12(3/0)
14(3/0)
8(2/0)

16(3/1)
18(3/1)
12(2/1)

16(3/1)
18(3/1 )
12(2/1)

16(3/1 )
18(3/1)
12(2/1)

20(4/1)
22(411 )
16(3/1)

22(4/1)
24(4/1)
18(3/1)

20(4/1)
22(4/1 )
16(3/1)

24(5/1 )
26(5/1)
20(4/1)

Source
Dn
An
An@

xxx.L

* The size of the index register Ox) does not affect execution time.

Table 29 Move Long Instruction Clock Periods
Destination

Source

Dn

An

An@

An@+

An@-

An@(d)

An@(d,ix)*

xxx.W

xxx.L

Dn
An
An@

4(1/0)
4(1/0)
12(3/0)

4(1/0)
4(1/0)
12(3/0)

12(1/2)
12(1/2)
20(3/2)

12(1/2)
12(1/2)
20(3/2)

12(1/2)
12(1/2)
20(3/2)

16(2/2)
16(2/2)
24(4/2)

18(2/2)
18(2/2)
26(4/2)

16(2/2)
16(2/2)
24(4/2)

20(3/2)
20(3/2)
28(5/2)

An@+
An@An@(d)

12(3/0)
14(3/0)
16(4/0)

12(3/0)
14(3/0)
16(4/0)

20(3/2)
22(3/2)
24(4/2)

20(3/2)
22(3/2)
24(4/2)

20(3/2)
22(312)
24(4/2)

24(4/2)
26(4/2)
28(5/2)

26(412)
28(4/2)
30(5/2)

24(4/2)
26(4/2)
28(5/2)

28(5/2)
30(5/2)
32(6/2)

An@(d, ix)*
xxx.W
xxx.L
PC@(d)
PC@(d,ix)*
#xxx

18(4/0)
16(4/0)
20(5/0)

18(4/0)
16(4/0)
20(5/0)

26(4/2)
24(4/2)
28(512)

26(4/2)
24(4/2)
28(5/2)

26(4/2)
24(4/2)
28(5/2)

30(5/2)
28(5/2)
32(6/2)

32(5/2)
30(5/2)
34(6/2)

30(5/2)
28(5/2)
32(6/2)

34(6/2)
32(6/2)
36(7/2)

16(4/0)
18(4/0)
12(3/0)

16(4/0)
18(4/0)
12(3/0)

24(4/2)
26(4/2)
20(3/2)

24(4/2)
26(4/2)
20(3/2)

24(4/2)
26(4/2)
20(3/2)

28(5/2)
30(5/2)
24(4/2)

30(5/2)
32(5/2)
26(4/2)

28(5/2)
30(5/2)
24(4/2)

32(6/2)
34(6/2)
28(5/2)

* The size of the index register Ox) does not affect execution time.

Table 30 Standard I nstruction Clock Periods
Instruction
ADD
AND
CMP
DIVS
DIVU

EOR

Size
Byte, Word
Long

op,An
8(1/0) +
6(1/0)+**

op.Dn
4(1/0)+
6(1/0) + **

Byte, Word

-

4(1/0) +

Long

-

6(1/0) + *'

6(1/0) +

4(1/0) +

-

6(1/0) +

6(1/0)+

-

-

158(1/0) + *

-

-

140(1/0) + *
4(1/0) ,,*

8(1/1) +

8(1/0) '**

12(1/2) +

Byte, Word
Long

-

70(1/0) + •

MULU

-

-

70(1/0)+*

Byte, Word
Long

4(1/0) +
6(1/0) + **

-

Byte, Word

8(1/0) +

4(1/0) +

Long

6(1/0) + **

6(1/0)+'*

+ add effective address calculation time
* indicates maximum value

8(1/1) +
12(1/2) +

Long

-

SUB

8(1/1) +
12(1/2) +

Byte, Word

MULS

OR

opDn,

-

-

8(1/1) +
12(1/2) +
8(1/1) +
12(1/2) +

* * total of 8 clock periods for instruction if the effective address is register direct
*** only available effective address mode is data register direct

171

HD68000,HD68000Y---------------------------------------------------------------Table 31
Instruction
ADDI

Immediation Instruction Clock Periods

Size

op#, Dn

op #, An

op#,M

op #, CCR/SR

Byte, Word

8(2/0)

-

12(2/1) +

16(3/0)

-

20(3/2) +

-

Long

ADDO
ANDI

Byte, Word

4(1/0)

8(1/0)*

8(1/1) +

Long

8(1/0)

8(1/0)

12(1/2) +

-

Byte, Word

8(2/0)

-

12(2/1) +

20(3/0)

-

CMPI

Long

MOVEO
ORI

-

14(3/0)

14(3/0)

12(3/0) +

-

8(2/0)

12(2/1) +

20(3/0)

-

-

20(3/2) +

Long

4(1/0)

-

-

-

Byte, Word

8(2/0)

-

12(2/1) +

20(3/0)

16(3/0)

-

20(3/2) +
12(2/1) +

-

-

20(312)

+

-

8(111) +

-

Byte, Word

8(2/0)
16(3/0)

Long

SUBO

8(2/0) +

16(3/0)

Long

SUB I

-

8(2/0)

Long

Byte, Word

EORI

20(3/1) +

8(2/0)

16(3/0)

Long
Byte, Word

Byte, Word

4(1/0)

8(1/0)*

Long

8(1/0)

8(1/0)

12(112)

+

+ add effective address calculation time
* word only

Table 32 Single Operand Instruction Clock Periods
Size

Instruction
CLR
NBCD
NEG
NEGX
NOT
See
TAS
TST

Register

Memory

Byte, Word

4(1/0)

8(1/1) +

Long

6(1/0)

12(1/2) +

Byte

6(1/0)

8(1/1) +

Byte, Word

4(1/0)

8(1/1) +

Long

6(1/0)

12(1/2) +

Byte, Word

4(1/0)

8(1/1) +

Long

6(1/0)

12(1/2) +

Byte, Word

4(1/0)

8(1/1) +

Long

6(1/0)

12(1/2) +

Byte, False

4(1/0)

8(1/1) +

Byte, True

6(1/0)

8(1/1) +

Byte

4(1/0)

10(1/1) +

Byte, Word

4(1/0)

4(1/0) +

Long

4(1/0)

4(1/0) +

+ add effective address calculation time

• SHIFT/ROTATE INSTRUCTION CLOCK PERIODS
Table 33 indicates the number of clock periods for the shift

• BIT MANIPULATION INSTRUCTION CLOCK PERIODS
Table 34 indicates the number of clock periods required for

and rotate instructions. The number of bus read and write
cycles is shown in parenthesis as: (r/w). The number of clock
periods and the number of read and write cycles must be added
respectively to those of the effective address calculation where
indicated.

the bit manipulation instructions. The number of bus read and
write cycles is shown in parenthesis as: (r/w). The number of
clock periods and the number of read and write cycles must be
added respectively to those of the effective address calculation
where indicated.
172

-------------------------------------------------------------------HD68000,HD68000Y
• CONDITIONAL INSTRUCTION CLOCK PERIODS
Table 35 indicates the number of clock periods required for
the conditional instructions. The number of bus read and write
cycles is indicated in parenthesis as: (r/w). The number of clock
periods and the number of read and write cycles must be added
respectively to those of the effective address calculation where
indicated.

• JMP, JSR, LEA, PEA, MOVEM INSTRUCTION CLOCK
PERIODS
Table 36 indicates the number of clock periods required for
the jump, jump to subroutine, load effective address, push effective address, and move multiple registers instructions. The number of bus read and ~rite cycles is shown in parenthesis as: (r/w).

Table 33 Shift/Rotate Instruction Clock Periods
Instruction
ASR,ASL
LSR, LSL
ROR, ROL
ROXR,ROXL

Size
Byte, Word
Long
Byte, Word
Long
Byte,Word
Long

Register
6 + 2n(1/0)
8 + 2n(1/0)
6 + 2n(1/0)
8 + 2n(1/0)
6+2n(1/0)
8 + 2n(1/0)

Memory
8(1/1) +

Byte, Word
Long

6 + 2n(1/0)
8 + 2n(1/0)

8(1/1) +
-

8(1/1) +
8(1/1) +

-

Table 34 Bit Manipulation Instruction Clock Periods
Instruction
BCHG
BCLR
BSET
BTST

Dynamic
Register
Memory
8(1/1) +
8(1/0)*
8(1/1) +
10(1/0)*
8(1/1) +
8(1/0)*
4(1/0) +
6(1/0)
-

Size
Byte
Long
Byte
Long
Byte
Long
Byte
Long

Static
Register
Memory
12(2/1) +
12(2/0)*
12(2/1) +
14(2/0)*
12(211) +
12(2/0)*
8(2/0) +
10(2/0)
-

+ add effective address calculation time
* indicates maximum value

Table 35 Conditional Instruction Clock Periods
Instruction

Displacement

Bee
BRA
BSR
DBee
CHK
TRAP
TRAPV

Byte
Word
Byte
Word
Byte
Word
CClru.
CCtalo.
-

-

Trap or Branch
Taken
10(2/0)
10(2/0)
10(2/0)
10(2/0)
18(2/2)
18(2/2)

Trap of Branch
Not Taken
8(1/0)
12(2/0)
-

-

12(2/0)
14(3/0)
10(1/0) +

10(2/0)
40(5/3) + *
34(4/3)
34(5/3)

+ add effective address calculation time
* indicates maximum value

173

-

4(1/0)

HD68000,HD68000Y----------------------------------------------------------------Table 36 JMP, JSR, LEA, PEA, MOMEM Instruction Clock Periods
Instr
JMP

Size

-

An@

An@(d)

An@+

An@-

-

-

10(2/0)

14(3/0)

xxx.W
10(2/0)

xxx.L
12(3/0)

PC@(d)

8(2/0)

10(2/0)

14(3/0)

-

-

18(2/2)

22(2/2)

18(2/2)

20(3/2)

18(2/2)

22(2/2)

JSR
LEA

-

16(2/2)
4(1/0)

PEA

-

12(1/2)

MOVEM

Word

12+4n
(3+n/0)

M-+R

Long

MOVEM

Word

R-+M

Long

12+8n
(3+2n/0)
8+4n
(2/n)

12+4n
(3+n/0)
12+8n
(3+2n/0)
-

8+8n
(2/2n)

An@(d,ix)*

PC@(d,ix)*

8(2/0)

12(2/0)

8(2/0)

12(3/0)

8(2/0)

12(2/0)

16(2/2)

20(2/2)

16(2/2)

20(3/2)

16(2/2)

20(2/2)

16+4n
(4+n/0)

18+4n
(4+n/0)

16+4n
(4+n/0)

20+4n
(5+n/0)

16+4n
(4+n/0)

18+4n
(4+n/0)

16+8n
(4+2n/0)
12+4n
(3/n)

18+8n
(4+2n/0)

16+8n
(4+2n/0)

20+8n
(5+2n/0)

16+8n
(4+2n/0)

18+8n
(4+2n/0)

-

8+4n
(2/n)

14+4n
(3/n)

12+4n
(3/n)

16+4n
(4/n)

-

-

8+8n
(2/2n)

12+8n
(3/2n)

14+8n
(3/2n)

12+8n
(3/2n)

16+8n
(4/2n)

-

-

-

-

n is the number of registers to move
* is the size of the index register (ix) does not affect the instruction's execution time

•

MULTI-PRECISION INSTRUCTION CLOCK PERIODS

Table 37 indicates the number of clock periods for the multiprecision instructions. The number of clock periods includes
the time to fetch both operands, perform the operations, store

the results, and read the next instructions. The number of read
and write cycles is shown in parenthesis as: (r/w).
In Table 37, the headings have the following meanings: Dn =
data register operand and M = memory operand.

Table 37 Multi-Precision Instruction Clock Periods
Instruction
ADDX
CMPM

Size

op On, On

Byte, Word

4(1/0)

Long

8(1/0)

Byte, Word

4(1/0)
8(1/0)
6(1/0)
6(1/0)

Long

SUBX

Byte, Word
Long

ABCD

Byte

SBCD

Byte

opM,M
18(3/1)
30(5/2)
12(3/0)
20(5/0)
18(3/1)
30(5/2)
18(3/1)
18(3/1)

• MISCELLANEOUS INSTRUCTION CLOCK PERIODS

•

Table 38 indicates the number of clock periods for the following miscellaneous instructions. The number of bus read and
write cycles is shown in parenthesis as: (r/w). The number of
clock periods plus the number of read and write cycles must be
added to those of the effective address calculation where indicated.

Table 39 indicates the number of clock periods for exception
processing. The number of clock periods includes the time for
all stacking, the vector fetch, and the fetch of the first instruction of the handler routine. The number of bus read and write
cycles is shown in parenthesis as: (r/w).

174

EXCEPTION PROCESSING CLOCK PERIODS

-------------------------------------------------------------------HD68000,HD68000Y
Table 38 Miscellaneous Instruction Clock Periods
Instruction
MOVE from SR
MOVE toCCR
MOVE to SR
MOVEP

Size
-

Memory
8(1/1) +
12(2/0) +
12(2/0) +

Register -+ Memory

Memory -+ Register

-

-

-

16(2/2)
24(2/4)

16(4/0)
24(6/0)

-

-

-

-

-

-

-

Word
Long

EXG

-

EXT

Word
Long

LINK
MOVE from USP
MOVE to USP
NOP
RESET
RTE
RTR
RTS
STOP
SWAP
UNLK

Register
6(1/0)
12(2/0)
12(2/0)

-

6(1/0)
4(1/0)
4(1/0)
16(2/2)
4(1/0)
4(1/0)
4(1/0)
132(1/0)
20(5/0)
20(5/0
16(4/0)
4(0/0)
4(1/0)
12(3/0)

-

-

-

-

-

-

-

-

-

+ add effective address calculation time

Table 39 Exception Processing Clock Periods

Reset

Exception

Periods
34(6/0)

Address Error
Bus Error
Interrupt
Illegal Instruction
Privileged Instruction
Trace

50(417)
50(417)
44(5/3)*
34(4/3)
34(4/3)
34(4/3)

* The interrupt acknowledge bus cycle is assumed to take
four external clock periods.

175

-

-

-

-

-

HD68000,HD68000Y------------------------------------------------------------------

turn, may cause external DMA logic to run a bus cycle at the
same time as the processor cycle, only when those paticuiar
timings are all satisfied. If the DMAC HD68450 is used, this
problem can be avoided. Because the HD68450 negates BR
by one clock after the assertion of BGACK.
For the 68000S mask: set, an internal hardware change is
implemented and a timing specification (tBGKBR) is added.
If BR and BGACK meet the asynchronous set·up time
tASI #47, then tBGKBR can be ignored. If BR and BGACK
are asserted asynchronously with respect to the clock, then
BGACK has to be asserted before BR is negated.

• APPENDIX
• THE 680008 MASK SET

We implement the specification for HD68000·1O/·12 and
two corrections on the 68000S mask: set. One of these correc·
tions is the bus arbitration logic, and the other is a change to
correct a RTE/RTR microcode problem.
(1) Bus Arbitration Logic
_ __
The problem occurs when bus grant acknowledge (BGACK)
is asserted for only one clock cycle while bus request (BR) is
negated. IF BR is asserted one clock cycle....!!fter BGACK is
negated, the processor asserts bus grant (BG) and address
strobe (AS) at the same time (Refer to Figure 58). This, in

Table 40 tBGKBR Specification

Number

Symbol

Item

Test
Condition

4MHz

6MHz

8MHz

10MHz

12.5MHz

Version

Version

Version

Version

Version

HD68000-4
HD68000Y4

HD68000-6
HD68000Y6

min

C@

BGACK "Low" to BR "High" tBGKBR

Fig. 57

30

I max
I -

min
25

1 max
I -

HD68000-8 HD68000·10 HD68000·12
HD68000Y8 HD68000Yl0 HD68000Y12
min

I

max

min

20

I

-

20

I max

1 -

min

20

I

and

RtW--------.J

BGACK--+----------~~~----+_

BG-----------------1

CLK

Figure 57 AC Electrical Waveforms - 8us Arbitration

CLK
I

I

8R

- - -......

/

BG

\~--------________~i________~-------­
I

~--------,.\

/

--------------------~

:\

:I

BGACK

:!\
I

I

AS------------------------------------J/~-----,~L------T_------I
i
Bus Grant Error --.t

t

Fix moves Bus Grant to here - - - -......

Figure 58 8us Arbitration Timing Diagram Error Sequence
176

max

1 -

Strobes

Unit

ns

----------------------------HD68000,HD68000Y
68000S Mask Set

68000R and 68000 Mask Set

RA

Ri>.:

= Bus Request Internal
= Bus Grant Acknowledge

R
A
G

=

T

= Three State Control

X

=

R == Bus Request Internal
A = Bus Grant Acknowledge Internal
G = Bus Grant

Internal

Bus Grant

T :::: Three State Control to Bus Control Logic

to Bus Control Logic

X = Don't Care

Don't Care

* State machine will not change state if bus is in SO. Refer to

* State machine will not change state if bus is in SO. Refer to
BUS ARBITRATION CONTROL for additional information.

BUS ARBITRATION CONTROL for additional information.

Figure 59 State Diagram of HD68000 Bus Arbitration Unit
RTE instructions. These two instructions execute correctly
provided there is no bus error.
If there is a bus error on the 2nd, 3rd, or 4th bus cycle of
RTR or RTE, the program counter is lost. The program counter
loads the stack pointer +2 which is the same address as the
access. The results is the program counter containing the stack
pointer. This problem can occur on all HD68000 mask sets
previous to 68000S.
The fix inhibits the loading of the program counter during
this instruction until the 4th bus cycle.

To Avoid this problem on 68000R mask set, users are rec·
ommended to choose one of the followings.
1) Negate BR more than one clock after the assertion of
BGACK.
2) Avoid the assertion of BGACK for one clock cycle.
3) Reassert BR more than two clocks later than the nega·
tion of BGACK.
4) Use HD684S0 as DMA controllers.
(2) RTE/RTR Microcode Problem
The error in the microcode only affects the RTR and the

Memory

Bus Cycle

I.~
~

I

Access Address

Contento!

\

SP

I

:

SP+2
(M+2)-

Progrilm Counter

I

i

SP+4

!

SP+2

:
SP+2
I ,

(M+2)-

I

,

PCH'PCL

i

: PCH'PCL+2
'

S P t 2 : PCH'PCL+2
(Mt2)"

, 680005 milsk set

Figure 60 RTE Instruction Bus Cycle

177

SP+2
SP
SPt4

~R
PCH

pel

M~
Mt28

...
•

••



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