U70_8_16_Bit_Multi Chip_Microcomputer_Data_Book U70 8 16 Bit Multi Chip Microcomputer Data Book

User Manual: U70_8_16_Bit_Multi-Chip_Microcomputer_Data_Book

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8/16-BIT MULTI-CHIP
MICROCOMPUTER DATABOOK

_HITACHI

When using this manual, the reader should keep the following in mind:
1. This manual may, wholly or partially, be subject to change without notice.
2. All rights reserved: No one is permitted to reproduce or duplicate, in any
form, the whole or part of this manual without Hitachi's permission.
3. Hitachi will not be responsible for any damage to the user that may result
from accidents or any other reasons during operation of his unit according
to this manual.
4. This manual neither ensures the enforcement of any industrial properties
or other rights, nor sanctions the enforcement right thereof.

INDEX
•

GENERAL INFORMATION
• QUick Reference Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

7

• Introduction of Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

9

• Quality Assurance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 18
• Reliability Test Data ....................................................................................... 24
• DATA SHEETS
•

8-bit Multi-chip Microcomputer.

HD6803
HD6803-1
HD6303R
HD63A03R
HD63803R
HD6303X
HD63A03X
HD63803X
HD6303Y
HD63A03Y
HD63803Y
HD6305X2
HD63A05X2
HD63805X2
HD6305Y2
HD63A05Y2
HD63805Y2
HD6800
HD68AOO
HD68BOO
HD6802
HD6802W
HD6809
HD68A09
HD68B09
HD6309
HD6809E
HD68A09E
HD68B09E
HD6309E
HD682 I
HD68A21
HD68B21
HD6321
HD63A21
HD63821
HD6840
HD68A40
HD68840
HD6340
HD63A40
HD63840
HD6843
HD68A43
HD6844
HD68A44
HD68844

Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 33
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Micro ProcessIng Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Micro Processing Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Micro Processing Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Micro Processing Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Micro Processing Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Micro Processing Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Micro Processing Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Micro Processing Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ' . . . . . . . . . . . . 126
Micro Processing Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Micro Processing Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Micro Processing Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Micro Processing Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Micro Processing Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Micro Processing Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Micro Processing Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Micro Proces~ing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Micro Processing Unit (NMOS) " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Microprocessor with Clock and RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Microprocessor with Clock and RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Micro Processing Unit (NMOS) .. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Micro Processing Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . 285
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Micro Processing Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Peripheral Interface Adapter (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 19
Peripheral Interface Adapter (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Peripheral Interface Adapter (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Peripheral Interface Adapter (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Peripheral Interface Adapter (CMOS) .... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Peripheral Interface Adapter (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Programmable Timer Module (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Programmable Timer Module (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Programmable Timer Module (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..... 355
Programmable Timer Module (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Programmable Timer Module (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Programmable Timer Module (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Floppy Disk Controller (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Floppy Disk Controller (NMOS) . . . . . . . . . . . . . . '.' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Direct Memory Access Controller (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Direct Memory Access Controller (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Direct Memory Access Controller (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

$

HITACHI

HD6845S
CRT Controller (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
H068A45S
CRT Controller (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
H068B45S
CRT Controller (NMOS) . ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
H06846
Combination ROM I/O Timer (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
H06850
Asynchronous Communications Interface Adapter (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . 506
Asynchronous Communications Interface Adapter (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . 506
H068A50
H06350
Asynchronous Communications Interface Adapter (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . 517
H063A50
Asynchronous Communications Interface Adapter (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . 517
H063B50
Asynchronous Communications Interface Adapter (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . 517
HD6852
Synchronous Serial Data Adapter (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
HD68A52
Synchronous Serial Data Adapter (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
H046508
Analog Data Acquisition Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
HD46508-1
Analog Data Acquisition Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
HD46508A
Analog Data Acquisition Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
H046508A·l
Analog Data Acquisition Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
H0146818
Real Time Clock Plus RAM (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
H06318
Real Time Clock Plus RAM (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
HD63A18
Real Time Clock Plus RAM (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
• 16-blt Multi-chip Microcomputers
H068000-4
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
H068000·6
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
HD68000·8
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
H068000·10
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
HD68000-12
Micro Processing Unit (NMOS) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
H068000Y4
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
HD68000Y6
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
HD68000Y8
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
HD68000YI0
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
HD68000Y 12
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
HD68000Z4
Micro 'Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
H068000Z6
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
H068000Z8
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
HD68000Z10
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . . . . . . 585
HD68000Z 12
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
HD68450·4
Direct Memory Access Controller (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
HD68450·6
Direct Memory Access Controller (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
HD68450·8
Direct Memory Access Controller (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
H068450·10
Direct Memory Access Controller (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
HD68450Y4
Direct Memory Access Controller (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
H068450Y6
Direct Memory Access Controller (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
H068450Y8
Direct Memory Access Controller (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
HD68450YI0
Direct Memory Access Controller (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
HD634634
Hard Disk Controller (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . .. 711
H063463·6
Hard Disk Controller (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 711
H063463·8
Hard Disk Controller (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......... , 711
H063484-4
Advanced CRT Controller (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 712
H063484·6
Advanced CRT Controller (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 712
HD63484·8
Advanced CRT Controller (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 712
•

INTRODUCTION OF RELATED DEVICES
• 8-bit Single-chip Microcomputers . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• 4·bit Single·chip Microcomputer HMCS40 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . .
• 4·bit Single-chip Microcomputer HMCS400 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .
• Ie Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .
• Gate Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• LCD Driver Series ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... '.' . . . . . . . . . . . . . . . . . .
• LSI for Speech Synthesizer System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• CODEC/Filter Combo LSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

•

717
726
728
729
732
734
736
739

HITACHI SALES OFFICE LOCATIONS ........•..•........•....•............•...........................•...742

~HITACHI

GENERAL
INFORMATION
• au ick Reference Gu ide
•

I ntroduction of Packages

• Qual ity Assu rance
• Reliability Test Data

QUICK REFERENCE GUIDE
•

a·BIT MULTI·CHIP MIC'ROCOMPUTERS
LSI Characteristics
Division

Type No.
Process

Old Type No.

MPU

~

1
a

:

HD6803
HD6803-1
HD6303R
HD63A03R
HD63B03R
HD6303X*
HD63A03X*
HD63B03X*
HD6303Y**
HD63A03Y"
HD63B03Y**
HD6305X2*
HD63A05X2*
HD63B05X2*
HD6305Y2*
HD63AOSY2*
HD63B05Y2*
HD6800
HD68AOO
HD68BOO
HD6802
HD6802W
HD6809
HD68A09
HD68B09

~
1.25

Supply
Voltage
(V)
5.0

Operating···
Temp'eratu ra
(OC)
0-+70

DP40

Microprocessor +128 Bytes of RAM
Microprocessor +128 8ytes of RAM

CMOS

~

5.0

0- +70

DP40
FP-54
CG40

CMOS

~

5.0

0-+70

DP-64S
FP-80

Microprocessor +192 Bytes of RAM

~
~

5.0

0-+70

DP-64S
FP-64

Microprocessor +256 Bytes of RAM

CMOS

~
~
2.0

5.0

0- +70

DP-64S
FP-64

Microprocessor +128 Bytes of RAM

CMOS

....14-~

5.0

0- +70

DP-64S
FP-64

Microprocessor +256 Bytes of RAM

5.0

·20 - +75

DP40

5.0
5.0

-20 - +75
-20- +75

DP-40
DP40

4
- 5.0
2.0

~

-20-+75

DP40

CMOS

~
2.0
~
2.0
2.0

2.0
HD46800D
HD468AOO
HD468BOO
HD46802

Function

NMOS
NMOS
NMOS
NMOS

~
~
2.0
1.0
1.0

MC6800
MC68AOO
MC68BOO
Microprocessor+Clock+128 Bytes of RAM MC6802
MicrQP!ocessor+Clock+256 Bvtes of RAM
MC6809
High-End 8-Bit Microprocessor
MC68A09
MC68B09

# - 5.0

-20-+75

DP40

High-End 8-Bit Microprocessor

HD6809E
HD68A09E
HD68B09E

NMOS

~

5.0

-20 - +75

DP40

High-End 8-Bit Microprocessor
(External Clock Type)

HD6309E**

CMOS

-#--

5.0

-20- +75

DP40

High-End 8-Bit Microprocessor
(External Clock Type)

HD46821
HD468A21
HD468B21

NMOS

~
3.0

....14-~

5.0

-20 - +75

DP-40

Peripheral Interface Adapter

5.0

-20-+75

DP40
FP-54

Peripheral I nterface Adapter

4
- 5.0
2.0

..:20 - +75

DP-28

Programmable Timer Module

2.0
CMOS

NMOS

HD46603S
HD46503S-1
HD46504
HD46504-1
HD46504-2
HD46506R
HD46505R-l
HD46505R-2
HD46505S
HD46505S-1
HD46505S-2
HD46846
HD46850
HD468A50

~
2_0

~
~
2.0

~

CMOS

~
~
2.0

5.0

-20 - +75

DP-28

Programmable Timer Module

NMOS

.14-1.5

5.0

0- +75

DP40

Floppy Disk Controller

NMOS

~
~
2.0

5.0

-20 - +75

DP40

Direct Memory Access Controller

5.0
-M-2.0

-20 - +75

DP40

NMOS

NMOS
NMOS
NMOS

~
~
~
2_0
1.0

.14-1.5

CRT Controller

5.0

-20 - +75

OP40

5.0

-20 - +75

DP40

HD46852
H0468A52

NMOS

~
2.0

....14-1.5

(3.0MHz High-speed Display)

MC6809E
MC68A09E
MC68B09E

(3.7MHz High-speed Display)
Combination ROM 110 Timer
Asynchronous Communications

-20- +75

DP-24

5.0

-20 - +75

DP-24

5.0

-20 - +75

DP-24

Synchronous Serial Data Adapter

5.0

-20 - +75

DP40

Analog Data Acquisition Unit

Interface Ada~ter

MC6821
MC68A21
MC68B21

MC6840
MC68A40
MC68B40

MC6843
MC6844
MC68A44
MC68B44
MC6845
MC68A45
MC68B45
I------~

MC6846
MC6850
MC68A50

Asynchronous Communications

Interface Adapter
MC6852
MC68A52

~

CMOS

~

HD631S**
H063A1S**

CMOS

1.0

~
1.5

5.0

0- +70

~::i:

Real Time Clock Plus RAM

5.0

-20 - +75

DP-24

Real Time Clock Plus RAM

33
33
87
87
87
117
117
117
152
152
152
155
155
155
188
188
188
221
221
221
253
266
279
279
279
310
310
310
311
311
311
344
344
345
345
345
362
362
362
381
381
381
395
395
395
410
410
437
437
437
509
509
509
470
470
--~.rn-

511
532
532
543
543
543
554
554

568
568

1.5

HD146818

Page

568
588

~
NMOS

Reference

344

CRT Controller

5.0

~

CMOS

MC6803
MC6803-1

Microprocessor

CMOS

#
-3.0

Compatibility

Packaget

HD6309**

HD6821
HD68A21
HD68B21
PIA
HD6321*
HD63A21*
HD63B21 *
HD6840
HD68A40
HD68B40
PTM
HD6340*
HD63A40*
HD63B40*
HD6843
'FDC
HD68A43
HD6844
DMAC
HD68A44
HD68844
HD6846
HD68A46
HD68B46
CRTC
HD6845S
HD68A45S
HD68B45S
COMBO HD6846
HD6B50
HD68A50
ACIA
HD6350
HD63A50
HD63B50
HD6852
SSDA
HD68A52
HD4850S
HD46508-1
ADU
HD46508A
HD46508A-l
RTC

NMOS

Clock
Frequency
(MHz)

MCl46818

588
607
607

* Preliminary *. Under development ••• Wide Temperature Range (-40 - +85°C) version i. available.
tOP; Plastic DIP, FP; Plastic Flat Package, CG: Glass-sealed Ceramic Leedles. Chip Carrier

~HITACHI

7

QUICK REFERENCE G U I D E - - - - - - - - - - - - - - - - - - - - - - - - - -

•

16-BIT MULTI-CHIP MICROCOMPUTERS
LSI Characteristics
Type No.

Division

MPU

Process

Clock
Frequency
(MHz)

Supply
Voltage
(V)

Operating
Temllerature
(oC)

t
Package

Function

Compatibility

Reference
Page

HD68000-4

4

MC68000L4

611

HD68000-6

6

MC68000L6

611

HD68000-8

8

MC68000L8

611

H 068000-1 0

10

HD68000-12

12.5

HD68000Y4

4

HD68000Y6

6

HD68000Y8

NMOS

8

DC-64

r-5.0

0- +70

PGA-68

Microprocessor

MC68000Ll0

611

MC68000L 12

611

MC68000R4

611

MC68000R6

611

MC68000R8

611

HD68000Yl0

10

MC68000Rl0

611

;

HD68000Y12

12.5

MC68000R12

!

HD68000Z4

611
611

I

r----

4

HD68000Z6

6

HD68000Z8

8

MC68000Z4

CG-68*

MC68000Z6

611

MC68000Z8

611

i

HD68000Z10

10

MC68000Z10

I

HD68000Z12

12.5

MC68000Z12

---611
611

I HD68450-4

4

~ MC68450L4

690

HD68450-6

6

MC68450L6

690

MC68450L8

690

MC68450Ll0

690
690

I

DMAC

HD68450-8

10

HD68450-12**

12.5

HD68450Y4

iii

HD68450Y6

~

..J

8

--

H 068450-1 0*

NMOS

4

DC-64

5.0

0-+70

Direct Memory

-

Access Controller

6

-

690
690

HD68450Y8

8

.c

HD68450Yl0*

10

-

CI>
0..

HD68450Y12**
..

12.5

-

690
690

-

737

-

737

.g-

H 063463-4 * *
HOC

H 063463-6 * *

4
CMOS

H 063463-8 * *
H 063484-6 * *

8

5.0

-20 - +75

DC-48

Hard Disk Controller

4
CMOS

HD63484-8**
* Preliminary

6
8

H 063484-4 * *
ACRTC

PGA-68*

* * Under development

6

5.0

-20 - +75

DC-64

Advanced CRT Controller

8
DC; Ceramic DIP, PGA; Pin Grid Array,
CG; Glass-sealed Ceramic Leadless Chip Carrier

$

HITACHI

-

---

-.----

690

737
738
738
738

INTRODUCTION OF PACKAGES
Hitachi microcomputer devices are offered in a variety of
packages. to meet various user requirements.

1. Package Classification

When selecting suitable packaging, please refer to the
Package Classifications given in Fig. I for pin insertion. surface
mount, and multi-function types, in plastic and ceramic.

Standard Outline

Plastic DIP
Ceramic DIP

Pin Insertion Type
Shrink Outline

Shrink Type Plastic DIP
Shrink Type Ceramic DIP

Package Classification

Flat Package

SOP (Plastic)
FPP (Plastic)

Surface Mounting Type
Chip Carrier

EPROM on the
Package Type

Multi·function Type

PLCC (Plastic)
LCC
(Glass Sealed Ceramic)

DIP; DUAL IN LINE PACKAGE
S-DIP; SHRINK DUAL IN LINE PACKAGE
PGA: PIN GRID ARRAY
FLAT-DIP; FLAT DUAL IN LINE PACKAGE
FLAT-QUIP; FLAT QUAD IN LINE PACKAGE
CC: CHIP CARRIER
SOP;SMALL OUTLINE PACKAGE
FPP; FLAT PLASTIC PACKAGE
PLCC; PLASTIC LEADED CHIP CARRIER
LCC ; LEADLESS CHIP CARRIER

Fig. 1

Package Classification according to Material and Printed Circuit Board Mounting Type

$

HITACHI

9

INTRODUCTION OF PACKAGES-------------------------------------------------2. Type No. and Package Code Indication
The Hitachi Type No. for multi-chip microcomputer devices is
followed by package material and outline specifications, as
shown below. The package type used for each device is identified

by code as follows, and illustrated in the data sheet for each
device.
When ordering, please write the package code next to the type
number.

Type No. Indication

HDx X

X

xP
Package Classification
No Indication : Ceramic DIP
P
; Plastic DIP
F (FP)
SOP,FPP
LCC (8-bit microcomputer device)
CG
y
PGA (16-bit microcomputer device)
LCC (16-bit microcomputer device)
Z

Package Code Indication

DP-64S
Outline

Materials

D ;DIP
C;CC
F ; FLAT

P
G
C

(Note)

PGA packages of 16-bit microcomputer devices have a different indication.

Package Code Indication;

10

; Plastic
; Glass Sealed
ceramic
;Ceramic

PGA-68

~HITACHI

- - - - - - - - - - - - - - - - - - - - - - - I N T R O D U C T I O N OF PACKAGES
3,

Package Dimensional Outline

shown in Table I according to PCB mounting method,

Hitachi multi-chip microcomputer devices employ the packages
Table 1 Package List

Method of Mounting

Package Classification

Package Material

Plastic

Package Code
DP·24
DP·28
DP·40

Standard Outline (DIP)
Pin I nsertion Type

Ceramic

Shrink Outline

S·DIP

Plastic

DP-64S

PGA

Glass Sealed Ceramic

PGA·68
FP·24

FLAT·DIP (SOP)
Flat Package

DC·48
DC·64

FLAT·QUIP (FPP)

Plastic

Surface Mounting Type
Chip Carrier (LCC)

Glass Sealed Ceramic

Fp·54
FP·64
FP·80
CG-40
CG·68

Plastic DIP
• DP·24

'"

~

~

O.51mi"~l ~~

'S .24

A

5.8,.,.XLt.;4min

!

.L

0'-15'

'_

0.20-0.38

(Unit: mm)

• DP·28

'4"1_==;'~3.4';"'.=-'~~
15.24

r--l

0.51~n...jr

!

5.8mex~

2.54min

0' -IS' t = = \ . . 0 . 2 0 _ 0 . 3 8

(Unit: mm)

$

HITACHI

11

INTRODUCTION OF PACKAGES----------------------------------------------• OP-40

(Unit: mm)

I Ceramic 01 P I
• OC-48

o
'1----,•.-.---F'------'-

J

~

~
• OC-64

1

(Unit: mm)

@

~O.:ZO-O.38

L22.81-J

12

(Unit: mm)

~HITACHI

--------------------------------------------------INTRODUCTION OF PACKAGES
Shrink Type Plastic DIP
•

DP·64S
64

I

CD
I

I

o

I

:8

I

32

l!==.j===9'=--=
17.0

; I,

19.05

'I

5.1max 2.54min

~Ad-'<

(Unit:mm)

Pin Grid Array
•

PGA·68

~~'~I~------~-------~"

I

I
'--______+-______-L-t.

(Unit: mm)

$

HITACHI

13

INTRODUCTION OF PACKAGES-------------------------------------------------Flat Package

• FP·24

-

-..

1

.!!

"'-

r.;:

I
.5

!.oJ

l

11

~

.r

:J
.5
13

12

d

;t:
~

~

~

2.50..,

d

l.~ ~*t )-fi
11.80

(Unit: mm)

< FPP>
•

FP·54

20

E:

~.::

:l,

J-mn~n,~±oN,nsrn~~of~~;
I
~

2S"8±04

--

dl ( UOoihhiiiiiUIu

: ~

eli

1 0.t"

)~w+
""

(Unit: mm)

< FPP>
•

FP·64

2.9 max.

(Unit: mm)

14

$

HITACHI

--------------------------------------------------INTRODUCTION OF PACKAGES


• FP-80

(Unit:mm)

Leadless Chip Carrier
•

I

CG-40

-D,~
E

~ 11'1

000000000

o4fils
~

"' E
CO.64

~

(Unit: mm)

•

CG-68
~~3..04m••.

--TT

203

52_--t--I

(Unit: mm)

~HITACHI

15

INTRODUCTION OF PACKAGES------------------------------------------------4. Mounting Method

Package lead pins are surface treated with solder coating or
plating to facilitate PCB mounting. The lead pins are connected
to the package by eutectic solder. Common connecting method
of leads and precautions are explained as follows:
4.1 Mounting Methods of Pin Insertion Type Package

Insert lead pins into the PCG through-holes (usually about
't.O.8mm). Soak leads in a wave solder tub.
Lead pins held by the through-holes enable handling of the
package through the soldering process, and facilitate automated
soldering. When soldering leads in the wave solder tub, do not
get solder on the package.
4.2 Mounting Method of Surface Mount Type Package

Apply the specified quantity of solder paste to the pattern on
any printed board by the screen printing method, to temporarily
fix the package to the board. The solder paste melts when heated
in a reflowing furnace, and package leads and the pattern of the
printed board are fixed by the surface tension of the melted
solder and self alignment.
The size of the pattern where leads are attached should be 1.1
to 1.3 times the leads' width, depending on paste material or
furnace adjustment.
The temperature of the reflowing furnace is dependent on
packaging material and type. Fig. 2 lists the adjustment of the
reflowing furnace for FPP. Pre-heat the furnace to 150" C. Surface temperature of the resin should be kept at 2350 C maximum
for 10 minutes or less.

Employ adequate heating or temperature control equipment
to prevent damage to the plastic package epoxy-resin material.
When using an infrared heater, avoid long exposure at temperatures higher than the glass transition point of epoxy-resin (about
150" C), which may cause package damage and loss of reliability
characteristics. Equalize the temperature inside and outside of
packages by reducing the heat of the upper surface of the
packages.
FPP leads may easily bend in shipment or during handling,
and impact soldering onto the printed board. Heat the bent leads
again with a sold~ring iron to reshape them.
Use a rosin flux when soldering. Do not use chloric flux
because the chlorine in the flux has a tendency to remain on the
leads and reduce reliability. Use alcohol, chlorothene or freon to
wash away rosin flux from packages. These solvents should not
remain on the packages for an excessive length of time, because
the package markings may disappear.
5.

Marking

The Hitachi trademark, product type No., and other markings
are printed on packages as shown in the following examples.
Case I and Case II are examples of markings and Nos. Case I
applies to products which have only a standard type No., while
Case II applies to products which have an old type No. and a
standard type No.

Time-

Fig. 2

Reflowing Furnace Adjustment

for FPP

16

~HITACHI

~~~~~~~~~~~~~~~~~~~~INTRODUCTION

OF PACKAGES

1.lmOB

Case I; Includes a standard type No.

(elBDB8D9B
(d)

(]~ B~

lSI

Case II; I ncludes an old type No. and a standard type No.

I. mDB
(a)

(b)

(e) B D~BBDBSB
(d)

[]~ B~

lSI

(e) BDB8~BSB

~HITACHI

Meaning of Each Mark
(a)
(b)
(e)

Hitachi Trademark
Lot Code

(d)

Standard Type No.
Japan Mark

(e)

Old Type No.

17

QUALITY ASSURANCE
1. VIEWS ON QUALITY AND RELIABILITY
Basic views on quality at Hitachi are to meet the
individual uers' required quality level and maintain a
general quality level equal to or above that of the
general market. The quality required by the user may
be specified by contract. or may be indefinite. In either
case, efforts are made to assure reliable performance
in actual operating circumstances. Quality control
during the manufacturing process, and quality awareness from design through production lead to product
quality and customer satisfaction. Our quality assurance technique consists basically of the following
steps:
(1) Build in reliability at the design stage of new
product development.
(2) Build in quality at all steps in the manufacturing
process.
(3) Execute stringent inspection and reliability confirmation of final products.
(4) Enhance quality levels through field data feed
back.
(5) Cooperate with research laboratories for higher
quality and reliability.
With the views and methods mentioned above,
utmost efforts are made to meet users' requirements.

design, device design. layout design, etc. Therefore. as long as standardized processing and
materials are used the reliability risk is extremely
small even in the case of new development
devices. with the exception of special requirements imposed by functional needs.
(2) Device DeSign
It is important for the device design to consider
total balance of process, structure. circuit. and
layout design. especially in the case where new
processes and/or new materials are employed.
Rigorous technical studies are conducted prior to
device development.
(3) Reliability Evaluation by Functional Test
Functional Testing is a useful method for design
and prOCess reliability evaluation of IC's and LSI
devices which have complicated functions.
The objectives of Functional Test are:
• Determining the fundamental failure mode.
• Analysis of relation between failure mode and
manufacturing process.
• Analysis of failure mechanism.
• Establishment of QC points in manufacturing
process.

2. RELIABILITY DESIGN OF
SEMICONDUCTOR DEVICES
2.1 Reliability Targets
The reliability target is an important factor in sales,
manufacturing. performance. and price. It is not adequate to set a reliability target based on a single set of
common test conditions. The reliability target is set
based on many factors:
(1) End use of semiconductor device.
(2) End use of equipment in which device is used.
(3) Device manufacturing process.
(4) End user manufacturing techniques.
(5) Quality control and screening test methods.
(6) Reliability target of system.
2.2 Reliability Design
The following steps are taken to meet the reliability
targets:
(1) Design Standardization
As for design rules. critical items pertaining to
quality and reliability are always studied at circuit

18

$

2.3 Design Review
Design Review is an organized method to confirm that
a design satisfies the performance required and
meets design specifications. In addition. design review
helps to insure quality and reliability of the finished
products. At Hitachi, design review is performed from
the planning stage to production for new products.
and also for design changes on existing products.
Items discussed and considered at design review are:
(1) Description of the products based on design
documents.
(2) From the standpoint of each participant. design
documents are studied. and for points needing
clarification, further investigation will be carried
out.
(3) Specify quality control and test methods based on
design documents and drawings.
(4) Check process and ability of manufacturing line to
achieve design goal.
(5) Preparation for production.
(6) Planning and execution of sub-programs for
design changes proposed by individual specialists.

HITACHI

- - - - - - - - - - - - - - - - - - - - - , QUALITY ASSURANCE

for test, experiments, and calculations to confirm
the design changes.
(7) Analysis of past failures with similar devices, discussion of methods to prevent them, and planning
and execution of test programs to confirm success.

3. QUALITY ASSURANCE SYSTEM
3.1 Activity of Quality Assurance
General views of overall quality assurance in Hitachi
are as follows:
(1) Problems in each individual process should be
solved in the process. Therefore, at the finished
product stage the potential failure factors have
been removed.
(2) Feedback of information is used to insure a satisfactory level of ability process.

3.2 Quality Approval
To insure quality and reliability, quality approval is
carried out at the preproduction stage of device

I

(1) A third party executes approval objectively from
the standpoint of the customer.
(2) Full consideration is given to past failures and
information from the field.
(3) No design change or process change without QA
approval.
(4) Parts, materials, and processes are closely
monitored.
(5) Control points are established in mass production
after studying the process abilities and variables.

3.3 Quality and Reliability Control at Mass
Production
Quality control is accomplished through division of
functions in manufacturing, quality assurance, and
other related departments. The total function flow is
shown in Fig.2. The main points are described below.

Contents

Step

Target
Specification

design, as described in section 2. Our views on quality
approval are:

I

I •

Design
Trial
Production

Purpose

I Design Review

Materials, Parts"
Approval
II

Confirmation of
Characteristics and
Reliability of Materials
and Parts

Characteristics of Material and
Parts
Appearance
Dimension
Heat Resistance
Mechanical
Electrical
Others
Electrical
Characteristics
Function
Voltage
Current
Temperature
Others
Appearance, Dimension

I Confirmation of Target

llQuality Approval (1)

Reliability Test
Life Test
Thermal Stress
Moisture Resistance
Mechanical Stress
Others

I

"QualitY. Approval (2)

Reliability Test
Process Check same as
Quality Approval (1)

IlCharacteristics Approval

t

~

Mass
Production

J

II

Spec. Mainly about
Electrical Characteristics

Confirmation of Quality
and Reliability in Design

Confirmation of Quality
and Reliability in Mass
Production

Figure 1 Flow Chart of Quality Approval

$

19

HITACHI

QUALITY A S S U R A N C E - - - - - - - - - - - - - - - - - - - -

Quality Control

Proceu

Products
I
I

Method

Inspection on Material and
Parts for Semiconductor
Devices

Lot Sampling,
Confirmation of
Quality Level

Manufacturing Equipment,
Environment, Sub-material,
Worker Control

Confirmation of
Quality Level

I nner Process
Quality Control

Lot Sampling,
Confirmation of
Quality Level

100% Inspection on
Appearance and Electrical
Characteristics

Testing,
Inspection

Sampling Inspection on
Appearance and Electrical
Characteristics

Lot Sampling

Reliability Test

Confirmation of
Quality Level, Lot
Sampling

I
I
I
I

'-----

r- - - - - - - - - - - - - - - - ,
Qual ity I nformation
I
I
Claim
:
Field Experience
:
I
General Quality
'- _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ oJI
Information

l

Feedback of
Information

Figure 2 Flow Chart of Quality Control in Manufacturing Process

20

eHITACHI

QUALITY ASSURANCE

3.3.1 Quality Control of Parts and Materials

3.3.2 Inner Process Quality Control

As semiconductor devices tend towards higher performance and higher reliability, the importance of
quality control of parts and materials becomes paramount. Items such as crystals, lead frames, fine wire
for wire bonding, packages, and materials needed in
manufacturing processes such as masks and chemicals, are all subject to rigorous inspection and control.
Incoming inspection is performed based on the purchase specification'and drawing. The sampling is executed based mainly on MIL-STD-105D.

Inner Process Quality Control performs very important
functions in quality assurance of semiconductor
devices. The manufacturing Inner Process Quality
Control is shown in Fig. 3.

The other activities of quality assurance are as
follows:
(1) Outside vendor technical information meeting.
(2) Approval and guidance of outside vendors.
(3) Chemical analysis and test.
The typical check points of parts and materials are
shown in Table 1 .
Table 1 Quality Control Check Points of Material and Parts
(Examplel
Material,
Parts

Wafer

Mask

Fine
Wire for
Wire
Bonding

Frame

Ceramic
Package

Plastic

Important
Control Items
Appearance
Dimension
Sheet Resistance
Defect Density
Crystal Axis
Appearance
Dimension
Resistoration
Gradation
Appearance
Dimension
Purity
Elongation Ratio
Appearance
Dimension
Processing
Accuracy
Plating
Mounting
Characteristics
Appearance
Dimension
Leak Resistance
Plating
Mounting
Characteristics
Electrical
Characteristics
Mechanical
Strength
Composition
Electrical
Characteristics
Thermal
Characteristics
Molding
Performance
Mounting
Characteristics

Point for Check
Damage and Contamina·
tion on Surface
Flatness
Resistance
Defect Numbers
Defect Numbers, Scratch
Dimension Level

(1) Quality Control of Semi-final Products and Final
Products
Potential failure factors of semiconductor devices
are removed in the manufacturing process. To
achieve thiS, check points are set-up in each process and products which have potential failure
factors are not moved to the next process step.
Manufacturing lines are rigidly selected and tight
inner process quality controls are executed-rigid
checks in each process and each lot. 100% inspection to remove failure factors caused by manufacturing variables and high temperature aging and
temperature cycling. Elements of inner process
quality control are as follows:
• Condition control of equipment and workers
environment and random sampling of semifinal products.
• Suggestion system for improvement of work.
• Education of workers.
• Maintenance and improvement of yield.
• Determining quality problems, and implementing countermeasures.
• Transfer of quality information.

Uniformity of Gradation

(2) Quality Control of Manufacturing Facilities and
Measuring Equipment
Manufacturing equipment is improving as higher
performance devices are needed. At Hitachi, the
automation of manufacturing equipment is encouraged. Maintenance Systems maintain operation of high performance equipment. There are
daily inspections which are performed based on
related specifications. Inspection points are listed
in the specification and are checked one by one to
prevent any omission. As for adjustment and
maintenance of measuring equipment, specifications are checked one by one to maintain and
improve quality.

Contamination, Scratch,
Bend, Twist
Purity Level
Mechanical Strength
Contamination, Scratch
Dimension Level
Bondability, Solderability
Heat Resistance
Contamination, Scratch
Dimension Level
Airtightness
Bondability, Solderability
Heat Resistance

Mechanical Strength
Characteristics of
Plastic Material

(3) Quality Control of Manufacturing Circumstances
and Sub-Materials
The quality and reliability of semiconductor devices
are highly affected by the manufacturing process.
Therefore, controls of manufacturing circum-

Molding Performance
Mounting Characteristics

$

HITACHI

21

QUALITY A S S U R A N C E - - - - - - - - - - - - - - - - - - - stances such as temperature, humidity and dust,
and the control of submaterials, like gas, and pure
water used in a manufacturing process, are intensively executed.

attention to buildings, facilities, air conditioning
systems, delivered materials, clOthes, work environment, and periodic inspection of floating dust
concentration.

Dust control is essential to realize higher integration and higher reliability of devices. At Hitachi,
maintenance and improvement of cleanliness at
manufacturing sites is accomplished through

3.3.3 Final Product Inspection and Reliability
Assurance
(1) Final Product Inspection
Lot inspection is done by the quality assurance

Process

Control Point

Purpose of Control

Purchase of Material
Wafer

Wafer,

~ Surface Oxidation

Characteristics, Appearance

Oxidation

Inspection on Surface
Oxidation
Photo Resist
Inspection on Photo Resist
<> PQC L.evel Check
Diffusion

Appearance, Thickness of
Oxide Film
Photo
Resist
Dimension, Appearance
Diffusion

Inspection on Diffusion
<> PQC L.evel Check
Evaporation
Inspection on Evaporation
<> PQC L.evel Check
Wafer Inspection

Diffusion Depth, Sheet
Resistance
Gate Width
Characteristics of Oxide Film
Break~own Voltage

Evaporation

Thickness of Vapor Film,
Scratch, Contamination

Wafer

Thickness, VTH Character istics
Electrical Characteristics

Dimension Level
Check of Photo Resist
Diffusion Status
Control of Basic Parameters
(VTH. etc.) Cleanness of surface.
Prior Check of VIH
Breakdown Voltage Check
Assurance of Standard
Thickness

Prevention of Crack,
Quality Assurance of Scribe

Inspection on Chip
Electrical Characteristics
Chip Scribe
Inspection on Chip
Appearance
<> PQC Lot Judgement

Chip

Assembling

Assembling

Appearance after Chip
Bonding
Appearance after Wire
Bonding
Pull Strength, CompreSSion
Width, Shear Strength
Appearance after Assembling

Quality Check of Chip
Bonding
Quality Check of Wire
Bonding
Prevention of Open and
Short

Sealing

Sealing

Guarantee of Appearance
and Dimension

<> PQC Leval Check
Final Electrical Inspection
<> Failure Analysis

Marking

Appearance after Sealing
Outline, Dimension
Marking Strength
AnalysiS of Failures, Failure
Mode. Mechanism

Feedback of Analysis Information

Appearance of Chip

<> PQC Level Check

Inspection after
Assembling
<> PQC Lot Judgement

Appearance Inspection
Sampling Inspection on
Products
Receiving
Shipment

Figure 3 Example of Inner Process Quality Control

22

Scratch, Removal of Crystal
Defect Wafer
Assurance of Resistance
Pinhole. Scratch

eHITACHI

- - . . . - - - - - - - - - - - - - - - - - - - - QUALITY ASSURANCE
department for products which were judged good
in 100% test ... the final process in manufacturing. Though 100% yield is expected, sampling
inspection is executed to prevent mixture of bad
product by mistake. The inspection is executed not
only to confirm that the products have met the
users' requirements but also to consider potential

Customer

I

quality factors. Lot inspection is executed based
on MIL-STD-l05D.
(2) Reliability Assurance Tests
To assure the reliability of semiconductor devices,
reliability tests and tests on individual manufacturing lots that are required by the user, are periodically performed.

Claim
(Failures, Information)
Sales Dept.
Sales Engineering Dept.
r------------~---------------------l
Failure Analysis

Quality Assurance Dept.

L

Countermeasure
Execution of
Countermeasure

Design Dept.

Manufacturing Dept.

Report

Quality Assurance Dept.

L ____________ _

I---

Follow-up and Confirmation
of Countermeasure Execution

Report

--------------------~

Sales Engineering Dept.
Reply

Customer
Figure 4 Process Flow Chart of Field Failure

~HITACHI

23

RELIABILITY TEST DATA
1.

INTRODUCTION

2. PACKAGE AND CHIP STRUCTURE
2.1 Packaging

Microcomputers provide high reliability and quality to meet
the demands of increased function, enlarging scale, and widening
application. Hitachi has improved the quality level of microcomputer products by evaluating reliability, building quality
into the manufacturing process, strengthening inspection techniques, and analyzing field data.
The following reliability and quality assurance data for
Hitachi 8-bit and 16-bit multi-chip microcomputers indicates
results from test and failure analysis.

Production output and application of plastic packaging continues to increase, expanding to automobile measuring and control systems, and computer terminal equipment operating under
severe conditions. To meet this demand, Hitachi has significantly
improved moisture resistance and operational stability in the
plastic manufacturing process.
Plastic and side-brazed ceramic package structures are shown
in Figure 1 and Table I.

(2) Plastic DIP

(1) Ceramic DIP

(3) Plastic Flat Package

Bonding wire

Figure 1 Package Structure

Table 1 Package Material and Properties

Item

24

Plastic DIP

Ceramic DIP

Plastic Flat Packag,e

Package

Alumina

Epoxy

Epoxy
Solder plating Alloy 42

Lead

Tin plating Brazed Alloy 42

Solder dipping Alloy 42

Seal

Au-Sn Alloy

N.A

N.A

Die bond

Au-Si

Au-Si or Ag paste

Au-Si or Ag paste

Wire bond

Ultrasonic

Thermo compression

Thermo compression

Wire

AI

Au

Au

~HITACHI

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ RELIABILITY TEST DATA

2.2

Chip Structure

Hitachi microcomputers are produced in NMOS E D technology or low power CMOS technology. Si-gate process is used

in both types to achieve high reliability and density.
Chip structure and basic circuit are shown in Figure 2.

Si-Gate N-channel E/D

Drain

Source

FET1

Drain

Si-Gate CMOS

SiO,

Source

Drain

Source
FET2

FET2

P-channel
EMOS

N-channel
DMOS

N-channel
EMOS

N-channel
EMOS

Figure 2 Chip Structure and Basic Circuit

3. QUALITY QUALIFICATION AND EVALUATION
3.1 Reliability Test Methods

Reliability test methods shown in Table 2 are used to qualify and evaluate new products and processes.
Table 2 Reliability Test Methods
Test Items

Test Condition

MIL-STO-883B Method No.

Operating Life Test

12SoC,1000hr

100S,2

High Temp, Storage
Low Temp, Storage
Steady State Humidity
Steady State Humidity Biased

Tstg max, 1000hr
Tstg min, 1000hr
6SoC 9S%RH, 1000hr
c
8S C 8S%RH, 1000hr

1008,1

Temperature Cycling
Temperature Cycling
Thermal Shock
Soldering Heat
Mechanical Shock
Vibration Fatigue
Variable Frequency
Constant Acceleration
Lead Integrity

-SSoC""" 1S0°C, 10 cycles
-20°C"" 12S0C," 200 cycles
O°C -- 100°C, 100 cycles
260° C, 10 sec
1S00G 0.5 msec, 3 times/X, V, Z
60Hz 20G, 32hrs/X, V, Z
2D-2000Hz 20G, 4 min/X, V, Z
20000G,1 min/X, V, Z
225gr, 90° 3 times

1010,4

_HITACHI

1011,3
2002,2
200S,1
2007,1
2001,2
2004,3

25

RELIABILITY TEST DATA - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3.2

Reliability Test Result

Reliability Test Results of 8-bit multi-chip microcomputer

devices is shown in Table 3 to Table 7, and of 16-bit microprocessor HD68000 in Table 8, Table 9 ..

Table 3 Dinamic Life Test (8-bit multi-chip microcomputer)
Sample Size

Device

Failure

Component Hour

HD6800
HD6802
HD6809

248
452
85

248000
153712
85000

0
1*
0

HD6821
HD6850
HD6852
HD6846
HD6843
HD6844
HD6845S
HD6840
HD46508
HD146818

399
158
170
69
66
80
88
64
140
44

266368
158000
125816
69000
66000
69000
55000
64000
140000
44000

1*
0
0
0
0
0
0
0
0
0

2063

1543896

.---------------------------------_ .. ------- --------------------- .. --------- . ------------- . ------------------- .. ---- .. --------- .. -------------- -------------------------------------

Total

2
* Current leakage

Table 4 High Temperature, High Humidity Test (8-bit multi-chip microcomputer) (Moisture Resistance Test)
(1) 85°C 85%RH Bias Test
Device
HD6800P
HD6802P
HD6809P
HD6850P
HD6852P
HD6843P
HD6844P
HD6845SP
HD6840P
HD46508P
HD146818P

Vcc Bias

168 hrs

500 hrs

1000 hrs

5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V

0/45
0/38
0/22
0/45
0/22
0/22
0/22
0/137
0/22
0/22
0/22

0/45
0/38
0/22
0/45
0/22
0/22
0/22
0/137
0/22
0/22
0/22

0/45

0/419

Total

0/22
0/45

0/137

0/22
0/271

0/419

(2) High Temperature, High Humidity Storage Life Test
Device
HD6800P
HD6802P
HD6802P
HD6809P
HD6850P
HD6850P
HD6852P
HD6843P
HD6844P
HD6845SP
HD6840P
HD46508P
HD146818P

26

Condition
65°C
80°C
65°C
65°C
65°C
80°C
85°C
80°C
80°C
80°C
65°C
65°C
65°C

95%RH
90%RH
95%RH
95%RH
95%RH
90%RH
95%RH
95%RH
90%RH
90%RH
95%RH
95%RH
95%RH

168 hrs

500 hrs

1000 hrs

0/22
0/22
0/38
0/45
0/135
0/22
0/22
0/22
0/22
0/22
0/22
0/70
0/45

0/22
0/22
0/38
0/45
0/135
0/22
0/22
0/22
0/22
0/22
0/22
0/70
0/45

0/22
0/22

~HITACHI

0/45
0/135
0/22

0/22

0/22
0/22
0/70
0/45

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RELIABILITY TEST DATA
(3) Pressure Cooker Test (121°C, 2 atm)
Device
HD6800P
HD6802P
HD6821P
HD6850P
HD6843P
HD6845SP
HD6846P
HD46508P
HD146818P

40 hrs

60 hrs

100 hrs

200 hrs

0/42
0/22
0/44
0/220/22
0/43
0/13
0/45
0/22

0/42
0/22
0/44
0/22
0/22
0/43
0/13
0/45
0/22

0/42
0/22
0/44
0/22
0/22
0/43
0/13
0/45
0/22

-

1 */43

* Aluminum corrosion

(4) MIL-STD-883B Moisture Resistance Test (65°C'" -lOoC, 90%RH or more, Vcc=5.5V)
Device
HD6800P
HD6802P
HD6821P
HD6846P

10 cycles

20 cycles

40 cycles

0/25
0/25
0/25
0/25

0/25
0/25
0/25
0/25

0/25
0/25
0/25
0/25

Table 5 Temperature Cycling Test (S-bit multi-chip microcomputer) (-55°C'" 25°C'" 150°C)
Device
HD6800P
HD6802P
HD6809P
HD6821P
HD6850P
HD6852P
HD6843P
HD6844P
HD6845SP
HD6846P
HD6840P
HD46508P
HD146818P

10 cycles

100 cycles

200 cycles

0/453
0/502
0/202
0/420
0/151
0/149
0/247
0/150
0/358
0/150
0/148
0/207
0/103

0/44
0/77
0/45
0/44
0/38
0/38
0/44
0/44
0/76
0/22
0/22
0/44
0/22

0/44
0/77
0/45
1 */44
0/38
0/38
0/44
0/44
0/76
0/22
0/22
0/44
0/22
* Large current leakage

Table 6 High Temperature, Low Temperature Storage Life Test (8-bit multi-chip microcomputer)
Device
MPU total
Peripheral total

Temperature

168 hrs

500 hrs

1000 hrs

150°C
-55°C
150°C
-55°C

0/88
0/76
0/110
0/88

0/88
0/76
0/110
0/88

0/88
0/76
0/110
0/88

~HITACHI

27

RELIABILITY TEST DATA

-----~-------------------------

Table 7 Mechanical and Environmental Test (8-bit multi-chip microcomputer)

24,28,40 pin
Ceramic DIP

Plastic DIP
Test Item

Condition

Flat Plastic Package

Sample Size

Failure

Sample Size

Failure

Sample Size

Failure

O°C - 100°C
10 cycles

110

0

175

100

Soldering Heat

260° C, 10 sec.

164

Salt Water Spray

110

a
a

177

35°C, NaCI 5%
24 hrs

176

a
a
a

20

a
a
a

Solderabil ity

230° C, 5 sec.
Rosin flux

159

a

137

a

34

a

Drop Test

75cm, maple board
3 times

110

a

-

-

20

a

Mechanical Shock

1500G, 0.5 ms
3 times/X, Y, Z

110

a

189

a

20

a

Vibration Fatigue

60 Hz, 20G
32 hrs/X, Y, Z

110

a

167

a

20

a

Vibration Variable Freq.

100 - 2000 Hz
20G, 4 times/X, Y, Z

110

a

167

a

20

a

Lead Integrity

225 g, 90°
Bonding 3 times

110

a

102

a

20

a

Thermal Shock

20

--

Table 8 Oinamic Life Test (H068000)

Condition
Temperature

Vee

125°C
150°C

5.5V
5.5V

168 hrs

500 hrs

1000 hrs

0/62
0/52

0/62
0/52

0/62
0/52

Table 9 Mechanical and Environmental Test (H068000)

Test Item

Condition

Sample Size

Failure

High Temp. Storage

Ta = 295°C
1000 hrs

42

0

Low Temp. Storage

Ta = -55°C
1000 hrs

42

0

Temperature Cycling I

-55°C - 25°C -150°C
10 cycles

189

0

Temperature Cycling II

-20°C - 25°C- 125°C
500 cycles

44

0

Thermal Shock

-55°C - 125°C
15 cycles

44

a

Soldering Heat

260°C, 10 sec.

44

0

Solderabil ity

230°C, 5 sec.

44

0

Mechanical Shock

1500G, 0.5 ms
3 times/X, Y, Z

44

0

Vibration Variable Freq.

20- 2000 Hz
20 G, 3 times/X, Y, Z

44

0

Constant Acceleration

20000G
1 m,in/X, Y, Z

44

0

28

$

HITACHI

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RELIABILITY TEST DATA
4.

PRECAUTIONS

4.3 Handling for Measurement

4.1 Storage

To prevent deterioration of electrical characteristics, solderability, appearance or structure, Hitachi recommends semiconductor devices be stored as follows:
(I) Store in ambient temperatures of 5 to 300 C, with a relative
humidity of 40 to 60%.
(2) Store in a clean, dust- and active gas-free environment.
(3) Store in conductive containers to prevent static electricity.
(4) Store without any physical load.
(5) When storing devices for an extended period, store in an
un fabricated form, to minimize corrosion of pre-formed
lead wires.
(6) Unsealed chips should be stored in a cool, dry, dark and
dust-free environment. Assembly should be performed
within 5 days of unpacking. Devices can be stored for up to
20 days in dry nitrogen gas with a dew point at -300 C or less.
(7) Prevent condensation during storage due to rapid temperature changes.

Avoid static electricity, noise and voltage surge when measuring or mounting devices. Precaution should be taken against
current leakage through terminals and housings of curve tracers,
synchroscopes, pulse generators, and DC power sources.
When testing devices, prevent voltage surges from the tester,
attached clamping circuit, and any excessive voltage possible
through accidental contact.
In inspecting a printed circuit board, power should not be
applied if any solder bridges or foreign matter is present.
4.4 Soldering

Semiconductor devices should not be exposed to high
temperatures for excessive periods. Soldering must be performed
consistent with temperature conditions of 2600 C for 10 seconds,
3500 C for 3 seconds, and at a distance of I to 1.5mm from the end
of the device package.
A soldering iron with secondary voltage supplied through a
grounded transformer is recommended to protect against
leakage current. Use of alkali or acid flux, which may corrode the
leads, is not recommended.

4.2 Transportation

General precautions for electronic components are applicable in transporting semiconductors, units incorporating semiconductors, and other similar systems. In addition, Hitachi
recommends the following:
(I) When transporting semiconductor devices or printed circuit
boards, minimize mechanical vibration and shock. Use containers or jigs which will not induce static electricity as a
result of vibration. Use of an electrically conductive container or aluminum foil is recommended.
(2) To prevent device deterioration from clothing-induced static
electricity, workers should be properly grounded while handling devices. Use of a I M ohm resistor is recommended to
prevent electric shock.
(3) When transporting printed curcuit boards containing semiconductor devices, suitable preventive measures against
static electricity must be taken. Voltage build-up can be
avoided by shorting the card-edge terminals. When a belt
conveyor is used, apply some surface treatment to prevent
build-up of electrical charge.
(4) Minimize mechanical vibration and shock when transporting semiconductor devices or printed circuit boards.

4.5 Removing Residual Flux

Detergent or ultrasonic removal of residual flux from circuit
boards is necessary to ensure system reliability. Selection of
detergent type and cleaning conditions are important factors.
When chloric detergent is used for plastic packaged devices,
care must be taken against package corrosion. Extended
cleaning periods and excessive temperature conditions can cause
the chip coating to swell due to solvent permeation. Hitachi
recommends use of Lotus and Dyfron solvents. Trichloroethylene solvent is not suitable.
The following conditions are advisable for ultrasonic
cleaning:
•
Frequency: 28 to 29 k Hz (to avoid device resonation)
•
Ultrasonic outP1Jt: 15W / I
•
Keep devices from making direct contact with power
generator
•
Cleaning time: Less than 30 seconds.

~HITACHI

29

DATA
SHEETS

8-BIT MULTI-CHIP
MICROCOMPUTERS

Preliminary data sheets herein contain information on new products. Specifications and information are subject to change without notice.
Advance Information data sheets herein contain information on products

under development. Hitachi reserves the right to change or discontinue these
products without notice.

HD6803, HD6803-1----

M PU

(Micro Processing Unit)

The HD6803 MPU is an 8·bit microcomputer system which
is compatible with the HMCS6800 family of parts. The H06803
MPU is object code compatible with the H06800 with improved
execution times of key instructions plus several new 16·bit and
8 bit instruction including an 8 x 8 unsigned multiply with
16·bit result. The H06803 MPU can be expanded to 65k words.
The H06803 MPU is TTL compatible and requires one +0.5
volt power supply. The H06803 MPU has 128 bytes of RAM,
Serial Communications Interface (S.C.I.), and parallel I/O as
well as a three function 16·bit timer. Features and Block
Diagram of the H06803 include the following:
•
•

FEATURES
Expanded HMCS6800 Instruction Set

•
•
•

8 x 8 Multiply
On·Chip Serial Communications Interface (S.C.I.)
Object Code Compatible with The HD6800 MPU

•
•
•
•

f6-Bit Timer
Expandable to 65k Words
Multiplexed Address and Data
128 Bytes of RAM (64 Bytes Retainable On Power
Down)

•
•
•
•
•

•

HD6803P
HD6803p-1

(DP-40)
• PIN ARRANGEMENT

o
AS

AM
D·o/Ao
D)/A)

IRQ,
RES

D2/A2

D3/ A 3

13 Parallel I/O Lines
Internal Clock/Divided·By·Four
TTL Compatible Inputs and Outputs
Interrupt Capability
Compatible with MC6803 and MC6803·1

P,n

D4 /A 4

PH
P"
P"

Do/A;

HD6803

p ..

BLOCK DIAGRAM

,

D6/ A ti
D7/ A 7
A.

P,o

A~

PII
P12

A,o
All

P"

A"

p,.
P,s

A,.
AIS

Standby

(Top View)

.....~+--P'o
I-t-~-+--P"

t+h......-P"
I-t-+-+......- P,.
t++-++-,,... P..

Address/
Data
Buffers

A.
A.

Address

A,o

A"

Au
Au

Address
Buffers

A14

A..

t-----P'o
t----P"
t-----P'2
t-----P13

E=====:~::
t----~::

•

TYPE OF PRODUCTS
Type No.

Bus Timing

HD6803

1.0MHz

HD6803-1

1.25MHz

Vee Standby

~HITACHI

33

H 0 6 8 0 3 , H 0 6 8 0 3 - 1 - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ __
•

ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Value
-0.3-+7.0

V

Input Voltage

Vee *
V in *

-0.3-+7.0

Operating Temperature

Topr

-+70

V
°c

- 55 - +150

°c

Supply Voltage

Storage

Temperatur~

0

TSIR

Unit

* With respect to VSS (SYSTEM GND)
[NOTE] Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded, it could affect reliability of LSI.

•

ELECTRICAL CHARACTERISTICS

•

DC CHARACTERISTICS (Vee =5.0V±5%, Vss = OV, Ta = Q-i\10°C, unless otherwise noted.)
Item
Input "High" Voltage

Symbol
RES

Other Inputs*

V 1H

Input "Low" Voltage

Allinputs*

V 1L

Input Load Current

EXTAL

Ilinl

Input Leakage Current

NMI,IRQI, RES

Ilinl

Three State (Offset)

PIO - PI'
P20 - P24

Leakage Current

IITsd

Do/Ao - D,/A,
Output "High" Voltage
Output "Low" Voltage

As - ~15, E, RIW, AS
Other Outputs

V OH

All Outputs

VOL

Darlington Drive Current PIO
Power Dissipation
Input Capacitance
Vee Standby
Standby Current

-

PI'

Ao/Do '" A,/D,
Other Inputs

Test Condition

-loH

= 0- Vee
V in = 0'" 5.25V
V in

V in

= 0.5 -

= -205 IJ.A
= -1451J.A
I LOAD = -1001J.A
I LOAD = 1.6 mA
V out = 1.5V
I LOAD
I LOAD

Cin

typ

max

4.0

-

Vee

2.0

-

-0.3

-

2.4
2.4
2.4

1.0

-

Po
V in
f

= OV, Ta = 25°C,

= 1.0 MHz

-

Powerdown

V SBB

4.0

Operating

V SB

4.75

Powerdown

ISBB

VSBB

= 4.0V

* Except Mode Programming Levels.

34

2.4V

min

~HITACHI

-

Unit
V

Vee
0.8

V

0.8

mA

-- -

2.5
10
100

---IJ.A

IJ.A

-

V

0.5

V

10.0

mA

-

1200

mW

-

5.25

12.5
10.0
5.25
8.0

pF
V
mA

----------------------------H06803,H06803-1
• AC CHARACTERISTICS

=5.0V ± 5%,

BUS TIMING (Vee

Vss - OV, Ta '"' 0"" +70°C, unless otherwise noted.)

Item

Test
Condition

Symbol

Cycle Time

HD6803
min

typ

0.8

-

150

-

5

-

50

5

-

50

5

-

30

-

-

ns

50

ns

50

ns

tAsr

Address Strobe Fall Time

tASf

Address Strobe Delay Time

tAso
t Er

60

Enable Pulse Width "High" Time

tEf
PWEH

450

-

Enable Pulse Width "Low" Time

PW EL

450

-

60

-

5
5

Address Strobe to Enable Delay Time

t ASEo

Address Delay Time
Address Delay Time for Latch

tAD
t AoL

Data Set-up Write Time

tosw

225

Data Set-up Read Time

-

10

50

5

50

-

5
340
350
30

260

-

270

-

-

tOSR

80

-

Read

tHR

10

-

-

Write

tHW
t ASL

20

-

-

20

Address Set-up Time for Latch

60

50

tAHL

20

-

-

Address Hold Time for Latch

20

Address Hold Time

tAH

20

-

-

Peripheral Read Access Time (Multiplexed Bus)

(tACCM)

(600)

I
I

115
70
10

20

-

-

Oscillator stabilization Time

tRc

Fig. 7

100

-

-

100

Processor Control Set-up Time

tpcs

Fig.8

200

-

-

200

PERIPHERAL PORT TIMING (Vee

=5.0V ± 5%,

Item

Vss

=OV,

Ta

Unit

5

Address Strobe Rise Time

Data Hold Time

max

-

200

Fig. 1

typ

-

tCYC
PW ASH

Enable Fall Time

min

-

1

Address Strobe Pulse Width "High"

Enable Rise Time

HD6803-1
max

-

-

10

IlS
ns

50

ns

50

ns

-

ns

260

ns

260

-

ns
ns

-

ns

-

ns

(420)

-

ns

-

ns
ns
ns
ns
ns
ms
ns

= 0 -- +70°C, unless otherwise noted,)

Symbol

Test Condition

min

typ

max

Unit

Peripheral Data Setup Time

Port 1,2

t posu

Fig. 2

200

-

ns

Peripheral Data Hold Time

Port 1,2

tpoH

Fig. 2

200

-

-

Delay Time, Enable Negative
Transition to Peripheral Data
Valid

Port 1,2*

t pwo

Fig. 3

-

-

400

ns

ns

* Except P21

$

HITACHI

35

HD6803,HD6803-1--------------------------------------------------------TIMER, SCI TIMING (Vee

=5.0V ±5%, Vss =OV, Ta =0 -

+70°C, unless otherwise noted.)

Symbol

Item
Timer Input Pulse Width

tPWT

Delay Time, Enable Positive Transition to
Timer Out

tTOD

SCI Input Clock Cycle

tScyC

SCI Input Clock Pulse Width

tpwsCK

MODE PROGRAMMING (Vee

=5.0V ±5%, Vss =OV, Ta = 0 -

Test Condition

typ

max

-

-

ns

-

-

600

ns

1

-

0.4

-

0.6

tScyc

min
2tcyc +200

Fig.4

Unit

tCYC

+70°C, unless otherwise noted.)
min

typ

max

Unit

Mode Programming Input "Low" Voltage

V MPL

-

-

1.7

V

Mode Programming Input "High" Voltage

V MPH

4.0

-

-

V

3.0

-

-

tcyc

-

tcyc

-

ns

Symbol

Item

PW RSTL

RES "low" Pulse Width
~ode

Programming Set-up Time

Mode Programming
Hold Time

I

RES Rise Time ~ l#lS

Im

Rise Time

< l#lS

Test Condition

Fig.8

tMPs

2.0

tMPH

0
100

~---------------------t~----------------------~

Address Strobe

2.2V

(AS)

O.6V

tASO-

Enable
(E)

R/W.A,-A ..

MPUWrote
Do/A,,-D7/A,
(PorI 3)

MPU Read
Du/Ao-DdA7
(PorI 3)

Figure 1 Expanded Multiplexed Bus Timing

36

~HITACHI

-

-

-----------------------------------------------------------H06803,H06803-1

r-

r-MPU Read

MPUWrote

Enable (E)
Enable (E)

All Oata*----------------~
Port Outputs __________________

*Not applicable to P21

Figure 2

Data Set-up and Hold Times
(MPU Read)

Figure 3 Port Data Delay Timing
(MPU Write)

Enable (E)

RES

Timer
Counter _ _ _ _ _J

,,--t-----J _____
I~~~~ ,I ~:~:: ), _____________-<..1

1'-------....,

P"

Output

Figure 5 Mode Programming Timing
Figure 4

Timer Output Timing

Vee

Test POInt 0-_.......-+
lS2074

®

or Equiv

C

C = 90 pF for Du/A" - 0, /A,. A. - A,;. E. AS. R/IN
= 30pF for P,O -P'7,P,,-P14
R=12kflforD u/A,,_D;/A,. A.-A"" E. AS. R/W
= 24 kfl for P, 0 -P, 7 . P, 0 -P 14

TTL Load

Figure 6 Bus Timing Test Load

~HITACHI

37

H 0 6 8 0 3 , H 0 6 8 0 3 - 1 - - - - - - - - - - - - - - - - - - - - -_ _ _ _ _ __

La.. Instruction

~

Cycle
#1

I

#2

I

#J

I

Enable lEI

Internal

Address

BusJ\_'-'''-_~''-

_ _ '\'''''_'''''_ _ _ _ _''__....J''__...J'__

_''\'''''_",'_ _","_....J''__

_'\'''''_"''_ _'''"_ _

\~~------------------------------------------------------------

~ ~tpcs

Intern.I""',_-'""'--..,.-....,.r--'"""",...-'""'--"V'--v--....,.r--'""""_-""""~-'""'--"""~-'""'--...,.-......v _ -

Data B u s - " " - - " " - - - " - - . . . J ' - - . . . J ' - - - " ' , - - "....-

\~----------------------------_I

Internal R/W

*

Eriable IE)

_',_ _"''-_ _-'''--_"',_-''--...J'......_

.....''-_...J'-_-''''"-_

IRa~

; Internal Interrupt

~~~\\\\\\\\\\~ ~\\\\\\\\\\\\\\\\
-5.25V

Figure 7 Interrupt Sequence

L.JlJ4 ~ [1J1..fLr
~

llo-l-----------"""'iH

rn
A:;tern:1
ress us
Internal

~

It

V~ ~-4-.7-5V---------------------tRC-----------------~----~ ~t~

~ ~t~

--------tll-t--------------4~ ~4.6v

.1~'p;;;~o;::..8v:....-----

\\\\\\\\\\\\\\\\\\\\\~ }sss\\\\\\\\S\\\\\\\\\\W&~=
~
""F'm""J FFFE FFFE FFFE FFFF New PC
FFFE FFFE

'< ~

Rm \\,,\\\\\\\\\%\\~ ~\\\\\\\\\\\\\\\\\\\\\S\\\\Y

~;t':r;~: U\\\'\\\\\\$\\\\\\~ 0%\\\\\\\\\\\\\\\\\\\\\\\\~

~

~NotValid

Figure 8 Reset Timing

Nominal Crystal Parameter

• SIGNAL DESCRIPTIONS
• Vee and Vss
These tWQ pins are used to supply power and ground to the
chip. The voltage supplied will be +5 volts ±5%.
• XTAL and EXTAL
These connections are for a parallel resonant fundamental
crystal, AT cut. Devided by 4 circuitry is included with the
internal clock, so a 4 MHz crystal may be used to run the
system at I MHz. The devide by 4 circuitry allows for use of the
inexpensive 3.58 MHz Color TV crystal for non-time critical
applications. Two 22pF capacitors are needed from the two
crystal pins to ground to insure reliable operation. EXTAL may
be driven by an external TTL compatible source with a 50%
(±lo%) duty cycle. It will devided by 4 any frequency less than
or equal to 5 MHz. XT AL must be grounded if an external
clock is used. The following are the recommended crystal
parameters:

38

~rvstall

Item ----........... -'

4 MHz

~ __LJpF

RS

~HITACHI

5 MHz

max. 4.7pF max.

160n max.

30n typo

XTAlr---~------,

C L1 = C L2 = 22pF ± 20%

(3.2 - 5 MHz)
EXTAl r--_e--.

tL2

[NOTE) AT cut parallel
resonance parameters

~CL1

Figure 9 Crystal Interface

---------------------------------------------------------HD6803,HD6803-1
•

• vee Standby
This pin will supply +5 volts ±S% to the standby RAM on the
chip. The first 64 bytes of RAM will be maintained in the power
down mode with 8 mA current max. The circuit of figure 13
can be utilized to assure that Vee Standby does not go below
V SBB during power down.
To retain information in the RAM during power down the
following procedure is necessary:
1) Write "0" into the RAM enable bit, RAM E. RAM E is bit
6 of the RAM Control Register at location $0014. This
disables the standby RAM, thereby protecting it at power
down.
2) Keep Vee Standby greater than VSBB.

v cc $,,"db,

T

P".. U",

Figure 10 Battery Backup for Vee Standby

•

Reset (RES)

This input is used to reset and start the MPU from a power
down condition, resulting from a power failure or an initial
startup of the processor. On power up, the reset m~be held
"Low" for at least 100 ms. During operation, RES, when
brought "Low", must be held "Low" at least 3 clock cycles.
When a "High" level is detected, the CPU does the following;
I) All the higher order address lines will be forced "High".
2) I/O Port 2 bits, 2, I, and 0 are latched into programmed
control bits PC2, PC I and PCO.
3) The last two ($FFFE, $FFFF) locations in memory will
be used to load the program addressed by the program
counter.
4) The interrupt mask bit is set, must be cleared before the
CPU can recognize maskable interrupts.
•

Table 1 Interrupt Vector Location
Vector
Highest
Priority

Lowest

Priority

Interrupt

MSB

LSB

FFFE

FFFF

FFFC

FFFD

FFFA

FFFB

FFF8

FFF9

IRQ!

FFF6

FFF7

ICF (Input Capture)

FFF4

FFF5

OCF (Output Compare)

FFF2

FFF3

TOF (Timer Overflow)

FFFO

FFF1

SC I (RDRF + ORFE + TDRE)

RES
NMI
Software Interrupt (SWI)

Enable (E)

This supplies the external clock for the rest of the system
when the internal oscillator is used. It is a single phase, TTL
compatible clock, and will be the divide by 4 result of the
crystal frequency. It will drive one TTL load and 90 pF.
•

Interrupt Request (I RQ! )

This level sensitive input requests that an interrupt sequence
be generated within the machine. The processor will wait until it
completes the current instruction that it being executed before
it recognizes the request. At that time, if the interrupt mask bit
in the Condition Code Register is not set, the-ma.chine will begin
an interrupt sequence. The Index Register, Program Counter,
Accumulators, and Condition Code Register are stored on the
stack. Next the CPU will respond to the interrupt request by
setting the interrupt mask bit "High" so that no further maskable interrupts may occur. At the end of the cycle, a 16-bit
address will be loaded that points to a vectoring address which is
located in memory locations $FFF8 and $FFF9. An address
loaded at these locations causes the CPU to branch to an interrupt routine in memory.
The IRQ! requires a 3.3 kil external resister to Vee which
should be used for wire-OR and optimum control of interrupts.
Internal Interrupts will use an internal interrupt line (lRQ1)'
This interrupt will operate the same as IRQ! except that it will
use the vector address of $FFFO through $FFF7. IRQ! will
have priority over IRQ2 if both occur at the same time. The
Interrupt Mask Bit in the condition code register masks both
interrupts (See Table 1).

Non-Maskable Interrupt (NMI)

A low-going edge on this input requests that a non-maskableinterr1}pt sequence be generated within the processor. As with
interrupt Request signal, the processor will complete the current
instruction that is being executed before it recognizes the NMI
signal. The interrupt mask bit in the Condition Code Register
has no effect on NMI.
In response to an NMI interrupt, the Index Register, Program
Counter, Accumulators, and Condition Code Register are stored
on the stack. At the end of the sequence, a 16-bit address will
be loaded that points to a vectoring address located in memory
locations $FFFC and $FFFD. An address loaded at these locations causes the CPU to branch to a non-maskable interrupt
service routine in memory.
A 3.3 kil external resistor to Vee should be used for
wire-OR and optimum control of interrupts.
Inputs IRQ! and NMI are hardware interrupt lines that are
sampled during E and will start the interrupt routine on the
E following the completion of an instruction.

•

Read/Write (RiW)

This TTL compatible output signals the peripherals and
memory devices whether the CPU is in a Read ("High") or a
Write ("Low") state. The normal standby state of this signal is
Read ("High"). This output is capable of driving one TTL load
and 90 pF.
•

Address Strobe (AS)

In the expanded multiplexed mode of operation address
strobe is output on this pin. This signal is used to latch the 8
LSB's of address which are multiplexed with data on Port 3. An
8-bit latch is utilized in conjunction with Address Strobe, as
showl'\ in figure II. Expanded Multiplexed Mode. Address
Strobe signals the latch when it is time to latch the address lines
so the lines can become data bus lines during the E pulse. The
timing for this singal is shown in Figure 1 of Bus Timing. This
signal is also used to disable the address from the multiplexed
bus allowing a deselect time, tASD before the data is enabled to
the bus.
• PORTS

There are two I/O ports on the HD6803 MPU; one 8-bit
port and one S-bit port. Each port has an associated write

~HITACHI

39

H06803,H06803-1---------------------------only Data Direction Register which allows each I/O line to be
programmed to act as an input or an output*~ A "1" in the
corresponding Data Direction Register bit will cause that I/O
line to be an output. A "0" in the corresponding Data Direction
Register bit will cause that I/O line to be an input. There are
two ports: Port 1, Port 2. Their addresses and the addresses of
their Data Direction registers are given in Table 2.

* The only exception is bit 1 of Port 2, which can either be data
input or Timer output.

Table 2 Port and Data Direction Register Addresses
Ports

Port Address

1/0 Port 1
1/0 Port 2

$0002
$0003

Data Direction
Register Address

state when used as an input. In order to be read properly, the
voltage on the input lines must be greater than 2.0 V for a
logic "I" and less than 0.8 V for a logic "0". As outputs, this
port has no internal pullup resistors but will drive TTL inputs
directly. For driving CMOS inputs, external pullup resistors are
required. After Reset, the I/O lines are configured as inputs.
Three pins on Port 2 (pin 8, 9 and 10 of the chip) are requested
to set following values (Table 3) during reset. The values of
above three pins during reset are latched into the three MSBs
(Bit 5,6 and 7) of Port 2 which are read only.
Port 2 can be configured as I/O and provides access to the
Serial Communications Interface and the Timer. Bit 1 is the
only pin restricted to data input or Timer output.
Table 3 The Values of three pins

$0000
$0001

Pin Number

I/O Port 1
This is an 8-bit port whose individual bits may be defined as
inp~ts or outputs by the corresponding bit in its data direction
register. The 8 output buffers have three-state capability,
allowing them to enter a high impedance state when the
peripheral data lines are used as inputs. In order to be read
properly, the voltage on the input lines must be greater than 2.0
V for a logic "I" and less than 0.8 V for a logic "0". As outputs,
these lines are TTL compatible and may also be used as a source
of up to I rnA at 1.5 V to directly drive a Darlington base. After
Reset, the I/O lines are configured as inputs.
•

I/O Port 2
This port has five lines that may be defined as inputs or
outputs by its data direction register. The 5 output buffers have
three-state capability, allowing them to enter a high impedance

•

GND
AS

[NOTES)

Value

8

L

9

H

10

L

L; Logical "0"
H; Logical "1"

• BUS

•

Data/Address Lines (Do/Ao -- D7/A7)
Since the data bus is multiplexed with the lower order
address bus in Data/Address, latches are required to latch those
address bits. The 74LS373 Transparent Octal D-type latch can
be used with the HD6803 to latch the least significant address
byte. Figure 11 shows how to connect the latch to the HD6803 .
The output control to the 74LS373 may be connected to
ground.
• Address Lines (As -- Als)
Each line is TTL compatible and can drive one TTL load and
90 pF. After reset, these pins become output for upper order
address lines (As to Als ).
• INTERRUPT FLOWCHART
The Interrupt flowchart is depicted in Figure 16 and is common to every interrupt excluding reset.

I
G OC

0,

a,

74LS373

D.

~

1

a.

1D~'D.-D.
Figure 11 Latch Connection

40

Function Table

Add"" A. -A,

~HITACHI

Output
Control
L
L
L
H

Enable

Output

G

0

a

H
H
L

H
L

H
L

x
x

ao

x

Z

----------------------------------------------------------H06803.H06803-1
•

MEMORY MAP

• PROGRAMMABLE TIMER

The MPU can provide up to 65k byte address space. A
memory map is shown in Figure 12. The first 32 locations are
reserved for the MPU's internal register area, as shown in Table
4 with exceptions as indicated.
Table 4

Internal Register Area

Register

Address

1 Data Direction Register"

Port
Port
Port
Port

2 Data Direction Register"
1 Data Register
2 Data Register

Not
Not
Not
Not

Used
Used
Used
Used

00
01
02
03

•

04'
05'

06'
07'

Timer Control and Status Register
Counter (High Byte)
Counter (Low Byte)
Output Compare Register (High Byte)

08
09

OA
OB
OC

Output Compare Register (Low Byte)
Input Capture Register (High Byte)
Input Capture Register (Low Byte)
Not Used

RAM Control Register
Reserved

OE
OF'
10
11

12
13
14
1S-1F

• External Address
•• 1; OutPut, 0; Input

Multiplexed/RAM
$0000

Free Running Counter ($0009:000A)

The key element in the programmable timer is a 16-bit free
running counter which is driven to increasing values by E (Enable). The counter value may be read by the CPU software at
any time. The counter is cleared to zero on RES and may be
considered a read-only register with one exception. Any CPU
write to the counter's address ($09) will always result in preset
value of $FFF8 being loaded into the counter regardless of the
value involved in the write. This preset figure is intended for
testing operation of the part, but may be of value in some
applications.
• Output Compare Register ($OOOB:OOOC)

00

Rate and Mode Control Register
Transmit/Receive Control and Status Register
Receive Data Register
Transmit Data Register

The HD6803 contains an on-chip 16-bit programmable timer
which may be used to perfonn measurements on an input
waveform while independently generating an output waveform.
Pulse widths for both input and output signals may vary from a
few microseconds to many seconds. The timer hardware consists
of
• an 8-bit control and status register,
• a 16-bit free running counter,
• a 16-bit output compare register, and
• a 16-bit input capture register
A block diagram of the timer registers is shown in Figure 13.

Internal Registers

The Output Compare Register is a l6-bit read/write register
which is used to control an output wavefonn. The contents of
this register are constantly compared with the current value of
the free running counter. When a match is found, a flag is set
(OCF) in the Timer Control and Status Register (TCSR) and the
current value of the Output Level bit (OLVL) in the TCSR is
clocked to the Output Level Register. Providing the Data
Direction Register for Port 2, Bit I contains a "I" (Output),
the output level register value will appear on the pin for Port 2
Bit 1. The values in the Output Compare Register and Output
Level bit may then be changed to control the output level on
the next compare value. The Output Compare Register is set to
$FFFF during RES. The Compare function is inhibited for
one cycle following a write to the high byte of the Output
Compare Register to insure a valid 16-bit value is in the register
before a compare is made.
•

$OOlF

Input Capture Register ($OOOD:OOOE)

The Input Capture Register is a 16-bit read-only register used
to store the current value of the free running counter when the
proper transition of an external input signal occurs. The input
transition change required to trigger the counter transfer is
controlled by the input Edge bit (IEDG) in the TCSR. The Data
Direction Register bit for Port 2 Bit 0, should * be clear (zero)
in order to gate in the external input signal to the edge detect
unit in the timer.

External Memory Space

$0080
Internal RAM

$ooFF

* With Port 2 Bit 0 configured as an output and set to "1 ", the
external input will still be seen by the edge detect unit.

External Memory Space

$FFFOt-----4
$FFFF _ _ _ _001 } External Interrupt Vectors
[NOTE]
Excludes the following addresses which may
be used externally: $04, $05, $06, $07, and
$OF.

Figure 12 HD6803 Memory Map

$

HITACHI

41

H06803,H06803-1----------------------------

HD6803 Internal Bus

IRa,

IRa,
Output Input
Level
Edge
BIt 1 BIIO
port 2 Port 2

Figure 13 Block Diagram of Programmable Timer
Timer Control and Status Register

76543210

lieF

I I I I I
OCF

TOF

EICI

• Timer Control and Status Register (TCSR) ($0008)
The Timer Control and Status Register consists of an 8·bit
register of which all 8 bits are readable but only the low order 5
bits may be written. The upper three bits contain read·only
timer status information and indicate that:
• a proper transition has taken place on the input pin with a
subsequent transfer of the current counter value t.o the
input capture register.
• a match has been found between the value in the free
running counter and the output compare register, and
when $0000 is in the free running counter.
Each of the flags may be enabled onto the HD6803 internal
bus (IRQ2) with an individual Enable bit in the TCSR. If the
I·bit in the H06803 Condition Code register has been cleared, a
priority vectored interrupt will occur corresponding to the flag
bit(s) set. A description for each bit follows:
Bit 0 Ol VL Output Level - This value is clocked to the output
level register on a successful output comp.are. If
the OOR for Port 2 bit I is set. the value will
appear on the output pin.
Bit I IEDG Input Edge - This bit controls which transition of
an input will trigger a transfer of the counter to
the input capture register. The OOR for Port 2 Bit
o must be dear for this function to operate. IEOG
= 0 Transfer takes place on a negative edge
("High"·to···Low" transition).
IfOG = I Transfer takes place on a positive edge

42

EOCI

ETOIIIEDG

I

OLVLI $0008

("Low".to·"High" transition).
Bit 2 ETOI Enable Timer Overflow Interrupt - When set, this
bit enables IRQ2 to occur on the internal bus for a
TOF interrupt; when clear the interrupt is in·
hibited .
Bit 3 EOCI Enable Output Compare Interrupt - When set,
this bit enables IRQ 2 to appear on the internal 'bus
for an output compare interrupt; when clear the
interrupt is inhibited.
Bit 4 EICI Enable input Capture Interrupt - When set, this
bit enables IRQ2 to occur on the internal bus for
an input capture interrupt: when clear the inter·
rupt is inhibited.
Bit 5 TOF Timer Overflow Flag - This read-only bit is set
when the counter contains $FFFF. It is cleared by
a read of the TCSR (with TOE set) followed by an
CPU read of the Counter ($09).
Bit 6 OCF Output Compare Flag - This read·only bit is set
when a match is found between the output
compare register and the free running counter. It is
cleared by a read of the TCSR (with OCF set)
followed by an CPU write to the output compare
register (SOB or SOC).
Bit 7 ICF
Input Capture Flag - This read·only status bit is
set by a proper transition on the input; it is cleared
by a read of the TCSR (with ICF set) followed by
an CPU read of the Input Capture Register ($OD).

~HITACHI

-----------------------------H06803,H06803-1
•

SERIAL COMMUNICATIONS INTERFACE

Bit 7

The HD6803 contains a full-duplex asynchronous serial
communications interface (SCI) on chip. The controller
comprises a transmitter and a receiver which operate independently or each other but in the same data format and at the same
data rate. Both transmitter and receiver communicate with the
CPU via the data bus and with the outside world via pins 2, 3,
and 4 of Port 2. The hardware, software, and registers are explained in the following paragraphs.

Rate and Mode Control Register

Transmit/Receive Control and Status Register

$12

Port 2

•

Receive Shift Register

Clock
Bit
2

10

14-........;..:......------~

Tx
BIt
4

....---E

12

Programmable Options

The following features of the HD6803 serial I/O section are
programmable:
• format - standard mark/space (NRZ)
• Clock - external or internal
• baud rate - one of 4 per given CPU 1/J2 clock frequency or
external clock :.:8 input
• wake-up feature - enabled or disabled
• Interrupt requests - enabled or masked individually for
transmitter and receiver data registers
• clock output - internal clock enabled or disabled to Port
2 (Bit 2)
• Port 2 (bits 3 and 4) - dedicated or not dedicated to serial
I/O individually for transmitter and receiver.
•

(Not Addressablel

Wake-Up Feature

In a typical multi-processor application, the software
protocol will usually contain a destination address in the initial
byte(s) of the message. In order to permit non-selected MPU's
to ignore the remainder of the message, a wake-up feature is
included whereby all further interrupt processing may be
optionally inhibited until the beginning of the next message.
When the next message appears, the hardware re-enables (or
"wakes-up") for the next message. The "wake-up" is automatically triggered by a string of ten consecutive I's which
indicates an idle transmit line. The software protocol must
provide for the short idle period between any two consecutive
messages.
•

Bit 0

1CCl -I CCO 15511550 IS10

I

Figure 14 Serial I/O Registers
Bit 0 WU

Bit 1 TE

Serial Communications Hardware

The serial conununications hardware is controlled by 4
registers as shown in Figure 14. The registers include:
• an 8-bit control and status register
• a 4-bit rate and mode control register (write only)
• an 8-bit read only receive data register and
• an 8-bit write only transmit data register.
In addition to the four registers, the serial I/O section utilizes
bit 3 (serial input) and bit 4 (serial output) of Port 2. Bit 2 of
Port 2 is utilized if the internal-clock-out or external-clock-in
options are selected.

Bit 2 TIE

Bit 3 RE

Transmit/Receive Control and Status (TRCS) Register

TIle TRCS register consists of an 8-bit register of which all 8
bits may be read while only bits 0-4 may be written. The
register is initialized to $20 on RES. The bits in the TRCS
register are defined as follows:

Bit 4 RIE

"Wake-up" on Next Message - set by HD6803
software and cleared by hardware on receipt of
ten consecutive 1's or reset of RE flag. It should
be noted that RE flag should be set in advance of
CPU set of WU flag.
Transmit Enable - set by HD6803 to produce
pream ble of nine consecutive I's and to enable
gating of transmitter output to Port 2, bit 4
regardless of the DDR value corresponding to this
bit; when clear, serial I/O has no effect on Port 2
bit 4.
TE set should be after at least one bit time of data
transmit rate from the set-up of transmit data
rate and mode.
Transmit Interrupt Enable - when set, will pennit
an IR0 2 interrupt to occur when bit 5 (TDRE) is
set; when clear, the TDRE value is masked from
the bus.
Receiver Enable - when set, gates Port 2 bit 3 to
input of receiver regardless of DDR value for this
bit; when clear, serial I/O has no effect on Port 2
bit 3.
Receiver Interrupt Enable - when set, wiU permit
an IR0 2 interrupt to· occur when bit 7 (RDRF) or
bit 6 (ORFE) is set; when clear, the interrupt is
masked.

Transmit/Receive Control and Status Register
76543210

IRDR~ORFEITDREI

RIE I

RE

I

TIE I

~HITACHI

TE

I WU

IADDR:SO011

43

HD6803,HD6803.1---------------------------Bit 5 TORE Transmit Data Register Empty - set by hardware
when a transfer is made from the transmit data
register to the output shift register. The TDRE bit
is cleared by reading the status register. then

writing a new byte into the transmit data register,
TDRE is initialized to I by RES.
Bit 6 ORFE Over·Run·Framing Error - set by hardware when
an overrun or framing error occurs (receive only).

Rate and Mode Control Register

X

I

6

5

X

X

4

3

2

0

X

CC,

CCO

SSO

I I I I ss,
ADDR : $0010

An overrun is defined as a new byte received with
last byte still in Dat Register/Buffer. A framing
error has occured when the byte boundaries in bit
stream are not synchronized to bit counter. If
WU.fiag is set, the ORFE bit will not be set. The
ORFE bit is cleard by reading the status register,
then reading the Receive Data Register. or by
RES.
Bit 7 RORF Receiver Data Register Full·set by hardware when
a transfer from the input shift register to the
receiver data register is made. If WU·fiag is set, the
RDRF bit will not be set. The RDRF bit is cleared
by reading the status register, then reading the
Receive Data Register, or by RES.
Rate and Mode Control Register (RMCR)
The Rate and Mode Control register controls the following
serial I/O variables:
• Baud rate

• format
• clocking source. and
• Port 2 bit 2 configuration
The register consists of 4 bits all of which are write·only and
cleared on RES. The 4 bits in the register may be considered as
a pair of 2-bit fields. The two low order bits control the bit rate
for internal clocking and the remaining tWQ bits control the
format and clock select logic. The register definition is as
follows:
Bit 0 SSO Speed Select - These bits select the Baud rate for
Bit I SS1 the internal clock. The four rates which may be
selected are a function of the CPU tP2 clock
frequency. Table 5 lists the available Baud rates.
Bit 2 CCO Clock Control and Format Select - this 2-bit field
Bit 3 CC1 controls the format and clock select logic. Table 6
defines the bit field.

Table 5 SCI Bit Times and Rates
XTAL

2.4576 MHz

4.0 MHz

E

614.4 kHz

1.0 MHz

SS1 : SSO
0
0
1
1

0
1
0
1

E + 16
E'" 128
E + 1024
E'" 4096

26 ~s/38,400 Baud
208 ~s/4,800 Baud
1.67 ms/600 Baud
6.67 ms/150 Baud

4.9152 MHz*
1.2288 MHz
13.0 ~s/76,800 Baud
104.2 ~s/9,600 Baud
833.3 ~s/1 ,200 Baud
3.33 ms/300 Baud

16 ~s/62,500 Baud
128 ~s/7812.5 Baud
1.024 ms/976.6 Baud
4.096 ms/244.1 Baud

• HD6803·' Only

Table 6 SCI Format and Clock Source Control
CC1:CCO

•

Clock Source

Port 2 Bit 2

Port 2 Bit 3

Port 2 Bit 4

o0

-

-

-

0 1
1 0
1 1

NRZ
NRZ
NRZ

Internal
Internal
External

Not Used
Output*
Input

**
**
**
**

**
**
**
**

Format

Clock output is available regardless of values for bits RE and TE.
Bit 3 is used for serial input if R E • "'" in TRCS; bit 4 is used for serial output if TE • "'" in TRCS.

I nternally Generated Clock

If the user wishes for the serial I/O to furnish a clock, the
following requirements are applicable:
• the values of RE and TE areiJ1lt1laterial.
•ce I. ceo must be set to 10
• the maximum clock rate will be E + 16.
• the clock will be at Ix the bit rate and will have a rising
edge at mid·bit.

44

Externally Generated Clock
If the user wishes to provide an external clock for the serial
I/O, the following requirements are applicable:
• the CC I, ceo, field in the Rate and Mode Control Register
must be set to II,
• the external clock must be set to 8 times (x 8) the desired
baud rate and
• the maximum external clock frequency is 1.0 MHz.

~HITACHI

----------------------------H06803,H06803-1
•

Serial Operations

The serial I/O hardware should be initialized by the HD6803
software prior to operation. This sequence will nonnally consist
of;
• writing the desired operation control bits to the Rate and
Mode Control Register and
• writing the desired operational control bits in the Transmit/
Receive Control and Status Register.
The Transmitter Enable (TE) and Receiver Enable (RE) bits
may be left set for dedicated operations.
Transmit Operations

The transmit operation is enabled by the TE bit in the
Transmit/Receive Control and Status Register. This bit when
se.t, gates the output of the serial transmit shift register to Port 2
BIt 4 and takes unconditional control over the Data Direction
Register value for Port 2, Bit 4.
Following a RES the user should configure both the Rate
and Mode Control Register and the Transmit/Receive Control
and Status Register for desired operation. Setting the TE bit
during this procedure initiates the serial output by first
~ransmitting a nine-bit preamble of 1 'so Following the preamble,
Internal synchronization is established and the transmitter
section is ready for operation.
At this point one of two situation exist:
1) if th.e Transmit Data Register is empty (TORE = I), a
contInUOUS string of ones will be sent indicating an idle
line. or.
2) if data has been loaded into the Transmit Data Register
(T~RE = 0). the word is transferred to the output shift
regIster and transmission of the data word will begin.
During the transfer itself. the 0 start bit is first transmitted.
Then the 8 data bits (beginning with bit 0) followed by the stop
bit, are transmitted. When the Transmitter Data Register has
been emptied, the hardware sets the TORE flag bit.
If the HD6803 fails to respond to the flag within the proper
time, (TORE is still set when the next nomlal transfer from the
parallel data register to the serial output register should occur)
then a I will be sent (instead. of a 0) at "Start" bit time.
followed by more I's until more data is supplied to the data
register. No D's will be sent while TORE remains a I.
Receive Operation

The receive operation is enabled by the RE bit which gates in
the serial input through Port 2, Bit 3. The receiver section
operation is conditioned by the contents of the Transmit/
Receive Control and Status Register and the Rate and Mode
Control Register.
The receiver bit interval is divided into 8 sub-intervals for
internal synchronization. In the NRZ Mode. the received bit
stream is synchronized by the first 0 (space) encountered.
The appro~imate center of each bit time is strobed during
the n~xt IO bIts. If the tenth bit is not a I (stop bit) a framing
error IS assumed, and bit ORFE is set. If the tenth bit as a I, the
data is transferred to the Receive Data Register, and interrupt
flag RDRF is set. If RDRF is still set at the next tenth bit time,
ORFE will be set, indicating an overrun has occurred. When the
HD6803 resp?nds to either flag (RDRF or ORFE) by reading
the status regIster followed by reading the Data Register, RDRF
(or ORFE) will be cleared.
•

it at power d?wn if V~c Standby is held greater than VSBB
volts, as explaIned prevIously in the signal description for V C'c
Standby.

$0014

~1 ~_~_B_~ ~,~R_A_M_:~i~M_x_C_O~j_tr_Ox_'R_e~i_is_t:_r-l
__

__

x~1

__X__l-_X__JI__

Bit 0 Not used.
Bit 1 Not used.
Bit 2 Not used.
Bit 3 Not used.
Bit 4 Not used.
Bit 5 Not used.
Bit 6 RAME The RAM Enable control bit allows the user the
ability to disable the standby RAM. This bit is set
to a logic "I" by RES whicil enables the standby
RAM and can be written to one or zero under program contra!' When the RAM is disabled. data is
read from external memory.
Bit 7 STBY The Standby Power bit is cleared when the standPWR by voltage is removed. This bit is a read/write status flag that the user can read which indicates that
the standby RAM voltage has been applied. and
the data in the standby RAM is valid.
•

GENERAL DESCRIPTION OF INSTRUCTION SET

The HD6803 is upward object code compatible with the
HD6800 as it implements the full HMCS6800 instruction set.
The execution times of key instructions have been reduced to
increase throughout. In addition. new instructions have been
added; these include 16-bit operations and a hardware multiply.
Included in the instruction set section are the following:
• CPU Programming Model (Figure 15)
• Addressing modes
• Accumulator and memory instructions - Table 7
• New instructions
• Index register and stack manipulations instructions .- Table
8
• Jump and branch instructions - Table 9
• Condition code register manipulation instructions .- Table 10
• Instructions Execution times in machine cycles -- Table
II
• Summary of cycle by cycle operation - Table 12
· Summary of undefined instructions - Table 13
•

CPU Programming Model

The programming model for the HD6803 is shown in Figure
15. The double (D) accumulator is physically the same as the
Accumulator A concatenated with the Accumulator B so that
any oper.ation using accumulator D will destroy information in
A and B.

RAM CONTROL REGISTER

· ,This register. which is addressed at SOOI4. gives status
mtormation about the standby RAM. A 0 in the RAM enable
bit (RAM E) will disable the standby RAM. thereby protecting

~HITACHI

45

HD6803,HD6803-1---------------------------8·8il Accumuillors A and 8
0, 16·Bil Double Accumuillor 0

115

X

01

Index Regiller (XI

115

SP

01

Slack Poinler (SPI

115

PC

01

Program Counler (PCI

Condition Code Regiller (CCRI
Carry/Borrow from MSB
Overflow
Zero
Negalive
Interrupt
HIlI Carry (From Bil 31

Figure 15 CPU Programming Model

46

• CPU Addressing Modes
The H06803 8-bit microcomputer unit has seven address
modes that can be used by a programmer, with the addressing
mode a function of both the type of instruction and the coding
within the instruction. A summary of the addressing modes for
a particular instruction can be found in Table II along with the
associated instruction execution time that is given in machine
cycles. With a clock frequency of 4 MHz, these times would be
microseconds.
Accumulator (ACCX) Addressing
In accumulator only addressing, either accumulator A or
accumulator B is specified. These are one-byte instructions.
Immediate Addressing
In immediate addressing, the operand is contained in the
second byte of the instruction except LOS and LOX which have
the operand in the second and third bytes of the instruction.
The CPU addresses this location when it fetches the immediate
instruction for execution. These are two or three-byte instructions.

_HITACHI

--------------~------------------------------------------HD6803.HD6803-1

Table 7 Accumulator & Memory Instructions

I
Operations

I

Condition Code
Addressing Modes
Mnemonic

IMMED.

INDEX

DIRECT

Register

EXTEND

-

#

OP

-

#

OP

-

#

OP

-

ADDA

88

2

2

9B

3

2

AB

4

2

BB

4

3

A+M-A

ADDB

CB

2

2

DB

3

2

EB

4

2

FB

4

3

B+M-B

Add Double

ADDD

C3

4

3

03

5

2

E3

6

2

F3

6

3

A: B + M: M + 1 -~ A: B

Add Accumulators

ABA

Add With Carry

ADCA

89

2

2 99

3

2

A9

4

2

B9

4

3

A+M+C-A

ADCB

C9
84

2 2
212

'B+M+C-B

ANDA
ANDB

C4

Bit Test

BIT A
BIT B

Clear

CLR

AND

#

3

2

E9

4

2

F9

4

3

2

A4

4

2

B4

4

3

A·M-A

2

2 '04

3

2

E4

4

2

F4

4

3

B·M- B

85

2

2

95

3

2

A5

4

2 iB5

4

3

A·M

C5

2 12

05

3

2

E5

4

2

F5

4

3

B'M

6F

6

2

7F

6

3

00- M

2

2

91

3

2

Al

4

2

Bl

4

3

CMPB

Cl

2

2

01

3

2

El

4

2

Fl

4

3

63

6

2

73

6

3

CBA
COM

A + B- A

3

81

Complement,l's

1

09

CMPA

Compare
Accumulators

2

#

94

CLRB
Compare

OP

lB

I

CLRA

4F

2

5F

2

--

COMB
70

1

A -A

43

2

1

53

2

1 B -B
OO-M-M

50

2

1 OO-B-B

Decimal Adjust, A

DAA

19

2

1

Decrement

DEC

4A

2

1

5A

2

1 B-l-B

2

7A

6

DECB
Exclusive OR

-

Increment

4

EORA

BB

2

2

9B

3

2

A8

EORB

C8

2

2

08

3

2

E8

4

2

6C

6

2

INC
t--INCA

2

4

3

F8

4

3

7C

6

3

B8

INCB
~.oAA __

Load
Accumulator

--

Load Double
Accumulator

_ Mult~~~~ned
OR, Inclusive
.Push Data
Pull Data
Rotate Left

Rotate Right

~.2

2

96

3

2

A6

4

Converts binary add of BCD
characters into BCD format
M-l-M

3

A -l-A
A(j)M-A
B

0

M- B

4C

2

,

5C

2

1 B + 1- B

M+l-M
A +1- A

2

B6

4

3

M-A

C6

2

2

06

3

2

E6

4

2

F6

4

3

M -B

LDD

CC

3

3

DC 4

2

EC

5

2

FC

5

3

M + 1 - B, M

--8A

2

2

9A

3

2

AA 4

2

BA 4

3

ORAB

CA

2

2

DA 3

2

EA

2

FA

4

3

----

-~

A

3D 10 1 Ax B- A :B

ORAA

4

A + M- A
B + M- B
36

3

1 A - Msp, SP - 1 ~ SP

.PSHB

37

3

1 B - Msp, SP - 1 - SP

PULA

32

4

1 SP + 1 - SP, Msp - A

PULB

33

4

1 SP + 1 - SP, Msp - B

PSHA

ROL

f----.

69

6

2

79

6

3

ROLA

49

~

1

ROLB

59

2

1

46

2

1

56

2

1

ROR

66

6

RORA
RORB

I

2

76

6

3

~}l.o1ll1lll
B
C b7
~} co:; I I

B

t

t

t

t

t

t

t

t+.t t
t I
t t

I

t
t
t
t

I

I 'R

t

I

I
I

t R!.
I 'R I.

t
t

·• ··•
•
··· ·•
·· ·•
• ·
• ·
·· ·•
·• ·••
·· •
·•
·· ··
·• ·•
·• ··
·· ·•
• ·
• •
·• •
·
• ·• •

R

··

t t t
t t t

C

I

R S

t I
t t

R S

b7

R S

I
I
I

I

1

2

t
t

1

2

1

2

I

t

I

3

•

t

t

4

I
t

t

4

t

4

t

t

R

I

I

R

t
t

t

5

I

5

t

I
I

R

I

I

R

I

I

R

I

LDAB

MUL

til

I

t

1 OO-A-A

6

··
· ··
t

t t t t

A-B

2

6A

vic

I

40

DECA

z

t

NEGA
NEGB

!

1 0

N

I

M-M

3

2

I

R S R R

(Negate)

2

3

H

R S RIR
R S ~R R

NEG

6

4

t '.

1 00 - A
1 00 - B
A-M

Complement,2's

60

6

2

5

t

B-M
11

COMA

-

-

OP

Add

--

Booleanl
Arithmetic Operation

IMPLIED

5

·•

·•
··•
·•
·

• 111

• • I t R •
• • I t R •
• • • • •
• • • • •
• • • • •
• • • •
• • t I 6 t
• • t I' 6 I
• • t t 6L

·

liJ
bo

I I I I I~
bO

·
·
· ·
·• ·•
•
·

t

t

6 '

I

t

6

I

I

t

I
6 I

(Continued)

The Condition Code Register notes are listed after Table 10.

~HITACHI

47

H06803,H06803-1---------------------------Table 7 Accumulator & Memory Instructions (Continued)
Condition Code
Register

Addressing Modes
Operations

Mnemonic

IMMED.
OP

Shift l.eft
Arithmp.tic

Douhlp. Shift
Left, ArithfTIp.tic
Shift Right
Arithmp.tic

-

INDEX

DIRECr

~Iop

-

#

ASL

OP

68

EXTEND

-

.: OP

-.

6

2 7B

6 3

Double Shift
Right l.ogical
Store
Accumulator

M}

_
b7

05

3

1 ~

47

2

1

ASR

67

6

2

71

6

3

ASRA

57

2

1

LSRA

44

2

1

LSRB

54

2

1

LSRD

04

3

1

64

LSR

6

2

74

6 3

~] r:rl

B

b7

~}o~
B
0-001
A7

97

3

2

A7

4

2

B7

4

3

A- M

STAB

07

3

2

E7

4

2

F7

4 3

B-M

2

2 90

SUBS

CO

2

2

SUBD

83

4

3 93

SBA

BQ

IIIII ~r.g

ACC AI ACC B
AD

B7

A- M
B_M+1

2

ED 5

2

FD 5

AO

4

2

BO

4 3

A-M-A

DO 3

2

EO

4

2

FO

4

3

5 2

A3

6

2

B3

6

3

B-M-B
A:B-M:M+1-A:B

I

10
3

2

A2

02 3

2

E2

Subtract
With Carry

SBCA

82

2 2 92

SBC8

C2

2 2

Transfer
Accu'rTlI'; lators

TAB

Test Zero or
Minus

TST

4 2
4 2

B2
F2

4

3

4

3

2

1 A-B-A
A-M-C-A
8-M-C-8

16
17

2
2

1 A-B
1 B_A

TSTA

40

2

1 A -00

TST8

50

2

1 B - 00

TBA
60

M -00

6 2 70 6 3

·• •
• •
• •
• •

··

r9 • •

2

3

•
•
•
•
•

3

l

•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•

C

l @l

t t ([I t
l (§)t

l

l

t

®

t

t t @ t
l t ® t
t t 6 l
t t §) l
t
t

l
l

R t

BO

3

DO 4

I N Z V

•
•
•
1_0 •

I IIIIIIJV

b7

STAA

80

-AO 87

1 0

4

bD

Ai:!i:!"A7 "Ai:!i:! II

A7

2

5
H

'?111111111-0

A
B

ASLD

SUBA

..

1
1

HD

A~cumulators

2
2

Subtract
Double Subtract

- ..

58

Store Double
Accumulator

Subtract

OP

ASLB

ASRI3
Shift Right
Logical

IMPLIED

48

ASLA

Booleanl
Arithmetic Operation

®

t

@ t
@ t

t l R
t R

t

t t R

•
•
•

t l t t
t t t t
t

t

t

t t

t

t

t

t t t t
t t t t
t· t R

•
•

t
t

~ R

t
t

t R R
t R R

t

R R

The Condition Code Re!llster notes lire listed after Table 10 .

Direct Artdressing

In direct addressing. the address of the operand is contained
in the second bvte' of the instruction. Direct addressing allows
the user to directly address the lowest 256 bytes in the machine
i.e .• locations zero through 255. Enhanced execution times are
achieved by storing data in these locations. In most configura·
tions, it should be a random access memory. These are two·byte
instructions.
E)l.tltnded Addressing

In extended addressing. the address contained in the second
hyte of the instruction is used as the higher 8·bits of the address
of the operand. The third byte of the instruction is used as the
lower g·hits of the address for the operand. This is an absolute
~ddress in memory. These are three·byte instructions:
Indexed Addressing

In indexed addressing. the address contained in the second
hyte of the instruction is added to the index register's lowest

48

8·bits. in the CPU. The carry is then added to the higher
order 8·bits of the index register. This result is then used to
address memory. The modified address is held in a temporary
address register so there is no change to the index register. These
are two-byte instructions.
Implied Addressing

In the implied addressing mode the instruction gives the
address (i.e., stack pointer, index register, etc.). These are
one·byte instructions.
Relative Addressing

In relative addressing, the address contained in the second
byte of the instruction is added to the program counter's lowest
g·bits plus two. The carry or borrow is then added to the high
g·bits. This allows the user to address data within a range of
-126 to +129 bytes of the present instruction. These are two·
byte instructions,

_HITACHI

-----------------------------H06803,H06803-1
•

New Instructions
In addition to the existing 6800 Instruction Set, the following new instructions are
incorporated in the HD6803 Microcomputer.

ABX

Adds the 8-bit unsigned accumulator B to the 16-bit X-Register taking into account
the possible carry out of the low order byte of the X-Register.
ADDD Adds the double precision ACCD * to the double precision value M: M+ I and places
the results in ACCD.
ASLD Shifts all bits of ACCD one place to the left. Bit 0 is loaded with zero. The C bit is
loaded from the most significant bit of ACCD.
LDD
Loads the contents of double precision memory locatIOn mto the double
accumulator A:B. The condition codes are set according to the data.
LSRD Shifts all bits of ACCD one place to the right. Bit 15 is loaded with zero. The C bit
is loaded from the least Significant bit to ACCD.
MUL
Multiplies the 8 bits in accumulator A with the 8 bits in accumulator H to obtain a
16-bit unsigned number in A:B, ACCA contains MSB of result.
PSHX The contents of the index register is pushed onto the stack at the address contained
in the stack pointer. The stack pointer is decremented by 2.
PULX The index register is pulled from the stack beginning at the current address
contained in the stack pointer + I. The stack pointer is incremented by 2 in total.
STD
Stores the contents of double accumulator A:B in memory. The contents of ACCD
remain unchanged.
SUBD Subtracts the contents of M:M + I from the contents of double accumulator AB
and places the result in ACCD.
BRN
Never branches. If effect, this instruction can be considered a two byte NOP (No
operation) requiring three cycles for execution.
CPX
Internal processing modified to permit its use with any conditional branch instruction.
*ACCD'is the 16 bit register (A:B) formed by concatenating the A and B accumulators. The A-accumulator is the most significant byte.

Table 8 Index Register and Stack Manipulation Instructions

Pointer Operations

Mnemonic

Compare Index Reg

CPX

Decrement Index Reg

DEX

IMMED.

AddreSSing Modes
--,-EXTND
DIRECT
INDEX

-

OP

-

::

OP

-

::

OP

-

::

8C

4

3

9C

5

2

AC

6

2 BC 6

OP

IMPLI ED
::

OP

-

Boolean/
Arithmetic Operation

::

X-M:M+1

3
09

3

1

X -1- X

Decrement Stack Pntr

DES

34

3

1

SP - 1 -+ SP

Increment Index Reg

INX

08

3

1

X + 1- X

Increment Stack Pntr

INS

31

3

1

Load Index Reg

LOX

CE

3

3

DE

4

2

EE

5

2

FE

5

8E

3

3

AE

5

2 BE
2 FF
2 BF

5

Load Stack Pntr

LOS

9E

4

2

Store Index Reg

STX

OF

4

Store Stack Pntr

STS

9F

4

2 EF 5
2 AF 5

Index Reg - Stack Pntr

TXS
- - _._-_.-

--

.-

-

SP + 1 -+ SP

3

M - X H • 1M + 1) - XL

5

3

M- SP H . (M+1)-SP L

5

3

X H -M.X L -(M+1)

3
1

SP H - 'VI. SP L - (M + 1)
X-1-SP

35

3

Stack Pntr'-+ Index Reg

TSX

30

3

1

SP+1-+X

Add

ABX

3A

3

1

B + X- X

Push Data

PSHX

3C

4

1

XL - M sp • SP - 1 - SP

Pull Data

PULX

38

5

1

SP + 1 - SP. Msp - X H

----------

--------

XH- Msp. SP -1-+ SP
SP + 1 - SP. Msp - XL

Condition Code
Register

2

5

4

3

1

0

H

I

N Z;V

C

• I I
• • I
•
•
• • I
• • •
• • J) I
• IJ) I
• (j)t
• ?) t
• • •
• • •
• • •

I

I

· ··· ·
·
·· ·•
·· · ·• ·••
•
· · · ·· · ··
·• • • • •
•

I

•
• •
• •
• •
R •
R
R
R

The Condition Code Register notes are listed after Table 10.

~HITACHI

49

H06803,H06803-1------------------------------------_____________________
Table 9 Jump and Branch Instructions
Condition Code
Register

Addressing Modes
Operations

Mnemonic

RELATIVE
OP

Branch Always

BRA

20

Branch Never

BRN

Branch If Carry Clear

BCC

Branch If Carry Set

BCS

-

#

DIRECT
OP

-

#

INDEX
OP

-

#

OP

-

Branch Test

IMPLIED

EXTND
#

OP

-

#

None

3

2

21

3

2

None

24

3

2

C=O

25

3

2

C=l

Branch If = Zero

BEQ

27

3

2

Z=l

Branch If ;;. Zero

BGE

2C

3

2

N

> Zero

BGT

2E

3

2

Z + IN

Branch If Higher

BHI

22

3

2

C+Z=O

Branch If .;; Zero

BlE

2F

3

2

Z + IN

Branch If lower Or
Same

BlS

23

3

2

C+Z=l

Branch If

------_.

Branch If

< Zero

<±l

<±l

BlT

20

3

2

N

Branch If Minus

BMI

2B

3

2

N= 1

Branch If Not Equal
Zero

BNE

26

3

2

Z=O

Branch If Overflow
Clear

BVC

28

3

2

V=O

Branch If Overflow Set

BVS

29

3

2

V =1

Branch If Plus

BPl

2A

3

2

N=O

Branch To Subroutine

BSR

80

6

2

Jump

JMP

Jump To Subroutine

JSR

No Operation

NOP

01

Return From InterruptI

RTI

3B 10 1

Return From
Subroutine

RTS

39

Software Interrupt

SWI

3F 12 1

Wait for Interrupt

WAI

3E

3

2

7E

3

3

AD 6

2

BO 6

3

6E
90

Table10

5

2

2

5

9

1

<±l

V) = 0
V) = 1

V= 1

Mnemonic

IMPLIED

ClC

OC

Clear Interrupt Mask

CLI

Clear Overflow

ClV

Set Carry
Set Interrupt Mask
Set Overflow

Advances Prog. Cntr.
Only

1 0
V

-

· ··
·
·• • •• ·• • ·•
· ·• •
• fID •

Condition Code Register

#

2

1

OE

2

1

O-C
0 ..... 1

OA

2

1

O-V

SEC

oq

2

1

1-C

SEI

OF

2

1

1-1

SEV

OB

2

1

1-V

Accumulator A - CCR

TAP

06

2

1

A- CCR

TPA

07

2

1

CCR-A

5

4

3

2

1

0

H

I

N

Z

V

C

··
·

• •
• R
• • •
•
•
S
•
•
•

• • R
• • •
R
•
• S
• • •
• S •

· ·· ·

--@l---

• • • • • •

Test: Result = 10000000?
Test: Result .. OOOOOOOO?
Test: Decimal value of most significant BCD Character greater than nine? (Not cleared if previously set)
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
Test: Set equal to result of N <±l C after shift has occurred.
Test: Result less than zero? (Bit 15 = 1)
load Condition Code Register from Stack. (See Special Operations)
Set when interrupt occurs. If previously set, a Non·Maskable Interrupt is required to exit the wait state.
Set according to the contents of Accumulator A.
Set equal to result of Bit 7 (AccB)

~HITACHI

C

• • •
• •
• •
•
• •
• •
• •
• •
• •
•
•
• •
• •
• •
• • •
• •
• • •
• •
• •
• • •

S

1

Condition Code Register Notes: (Bit set it test is true and cleared otherwise)

50

• • •
• • •
• •
• •
• • •
• •
• • •
•
•
• • •
• •
• • •
• •
• •
• •
• •
• • •
• •
• • •
• •

2

-@-

1

Boolean Operation

CCR ..... Accumulator A

1 (Bit V)
(Bit C)
(Bit C)
(Bit V)
(Bit V)
(Bit V)
(Bit N)
(All)
(Bit I)
(All)
(Bit C)

N Z

Condition Code Register Manipulation Instructions

OP
Clear Carry

3

I

· ·
· ·
· ··

~ddressingModes

Operations

4

H

·· · ·· ·
· · ··
·· ·· ··
· ·
· ·· ·

V =0

<±l

5

------------------------------H06803,H06803-1
Table 11
Direct

ABA
ABX
ADC
ADD

•

Extended

Indexed

•

4

•

4

2

4

4

4

6

AND

2

3

4

6
4

6

6

•

•

•

•

ASL
ASLD

2

ASR

2

6

6

BCC
BCS
BEQ
BGE
BGT
BHI
BIT
BLE

•

•

•

BLT
BMI
BNE
BPL
BRA
BRN
BSR

Bve

Implied

3

•
3

•

•
4

•

•
•
•
•
•

•
•

•

4

•

•
•

•

•

•
•

•

•

•

•

•
•
•

•
•
•

2

4

DAA
DEC

•

DES

•
•

2

EOR
INC
INS

•

2

2

•

5

•

•

•
6

4

4

6
6

6
6

6

6

•

•

2

3

4

4

•

•

6

6

•
•

•
•

4

3

4
4

LSRD

MUL
NEG

PSH
PSHX
PUL
PULX
ROL

RTS

•

6

•

RTI

3

•

LOX

3
3

3

•
6

•
•
•

•
•

LSR

3

3

CPX

DEX

3

6

CMP

COM

LOS

ROR

ClI

CLR
CLV

LOA
LDD

2

SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI

•

~HITACHI

3
6

•

4

4

•

5
5
5
6

5
5
5
6

•
•

•
•

•

10

6

6

•

2

2

ORA

3
3

•
•
•

•

JSR

•
•
•

Relative

3

INX

NOP

•

Implied

ACCX
JMP

3

BVS

CBA
CLC

Relative

2

•

ADDD

BLS

Instruction Execution Times in Machine Cycle

•

•

4

•
2
2

•
•

•

3

4

•

•

•
•

•
•

•

•

6
6

6

•

•
•

4

•
•
•
•

•
•
•

•
•
•
•
•

•

2
4

5

4

5

5

4

5

5

3
5

4

4

•

•
•

•
•

•

4

5

•

10
5

4

•

•

6

•
•
4

•

•

•

4

•

4

•
•
•

4

•

•

6

6

•
•

•

•
•

•
•
•

6

6

•
•
•

•

•
•

•
•
•
•
•
•
•
•

12

2

•
•
•
•

9

•

51

H06803,H06803-1--------------------------------------------------------• Summary of Cycle by Cycle Operation
Table 12 provides a detailed description of the information
present on the Address Bus. Data Bus, and the Read/Write line
(R/W) during each cycle for each instruction.
This information is useful in comparing actual with expected
results during debug of both software and hardware as the

control program is executed. The information is categorized in
groups according to addressing mode and number of cycles per
instruction. (In general. instructions with the same addressing
mode and number of cycles execute in the same manner: exceptions are indicated in the table).

Table 12 Cycle by Cycle Operation
Address Mode &
Instructions

Address Bus

Data Bus

IMMEDIATE
ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SBC
SUB

2

I

LDS
LDX
LDD

3

CPX
SUBD
ADDD

4

1
2

Op Code Address
Op Code Address + 1

1
1

Op Code
Operand Data

1
2

Op Code Address
Op Code Address + 1
Op Code Address + 2

1
1
1

Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address Bus F F F F

1
1
1
1

Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Address of Operand

1
1
1

Op Code
Address of Operand
Operand Data

Op Code Address
Op Code Address + 1
Destination Address

1
1

0

Op Code
Destination Address
Data from Accumulator

Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1

1
1
1
1

Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand + 1

1
1

0
0

Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)

Op Code Address
Op Code Address + 1
Operand Address
Operand Address + 1
Address Bus F F F F

1
1
1
1
1

Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Subroutine Address
Stack Pointer
Stack Pointer + 1

1
1
1

Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)

3
1
2

3
4

DIRECT
ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SBC
SUB

3

1
2

3

STA

3

1

2

3
LDS
LOX
LDD
STS
STX
STD

4

1

2

3
4

4

I

1
2

3
4

CPX
SUBD
ADDD

5

JSR

5

1

2

3
4
5
1
2

3
4
5

I

0
0

(Continued)

52

~HITACHI

----------------------------------------------------------H06803,H06803-1
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions

Address Bus

Data Bus

INDEXED
JMP

3

Op Code Address
Op Code Address + 1
Address Bus F F F F

1
1
1

Op Code
Offset
Low Byte of Restart Vector

3
4

Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset

1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data

4

1
2
3
4

Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset

1
1
1

0

Op Code
Offset
Low Byte of Restart Vector
Operand Data

LDS
LDX
LDD
LDD

5

1
2

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1

1
1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

STS
STX
STD

5

1
2

3
ADC
ADD
AND
BIT
CMP
--.STA

ASL
ASR
CLR
COM
DEC
INC

4

EOR
LDA
ORA
SBC
SUB

3
4
5
1
2

3
4
5
LSR
NEG
ROL
ROR
TST*

6

1
2

--- ---- - - - -

CPX
SUBD
ADDD

----

3
4
5
6

Op Code Add ress
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1

--1--.----- -.------- ---

Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
Address Bus FFFF
Index Register Plus Offset

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
0
Operand Data (Low Order Byte)
0
- - - - - - - - - - - - - - - - - - --_._-----Op Code
1
Offset
1
Low Byte of. Restart Vector
1
Current Operand Data
1
Low Byte of Restart Vector
1
New Operand Data
0
1
1
1

-----~-

6

1
2
3
4
5
6

6

1

-JSR

1
2

2

3
4
5
6

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register + Offset
Index Register + Offset + 1
Address Bus F F F F

1
1
1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

1
1
1

Op Code
Offset
Low Byte of Restart Vector
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)

------

' Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register + Offset
Stack Pointer
Stack Pointer - 1

• In the TST instruction, R/W line of the sixth cycle is "1" level, and AB

1

0
0

=FFFF, DB =Low Byte of Reset Vector.

~HITACHI

(Continued)

S3

HD6803,HD6803-1--------------------------------------------------------Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions

Address Bus

Data Bus

EXTENDED
JMP

3

1
2

3
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

4

3
4
4

STA

1
2

1
2

3
4
LOS
LOX
LOD

5

STS
STX
STD

5

ASL
ASR
CLR
COM
DEC
INC

1
2

3
4
5
1
2

3
4
5
LSR
NEG
ROL
ROR
TST*

6

1
2

3
4
5
6

CPX
SUBD
ADDD

6

JSR

6

1
2

3
4
5
6
1
2

3
4
5
6

Op Code Address
Op Code Address + 1
Op Code Address + 2

1
1
1

Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand

1
1
1
1

Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data

Op Code
Op Code
Op Code
Operand

1
1
1
0

Op Code
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1

1
1
1
1
1

Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low

(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1

1
1
1
0
0

Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low

(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address Bus F F F F
Address of Operand

1
1
1
1
1
0

Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data

Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1
1

Op Code
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1

1
1
1
1
0
0

Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

Address
Address + 1
Address + 2
Destination Address

• In the TST instruction, RIW line of the sixth cvcle is "1" level, and AB = F FFF, DB = Low Bvte of Reset Vector.

54

_HITACHI

(Continued)

----------------------------H06803,H06803-1
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions

Data Bus

Address Bus

IMPLIED
2

1
2

Op Code Address
Op Code Address + 1

1
1

Op Code
Op Code of Next Instruction

ABX

3

1
2

Op Code Address
Op Code Address + 1
Address Bus F F F F

1
1
1

Op Code
Irrelevant Data
Low Byte of Restart Vector

ASLD
LSRD

3

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Irrelevant Data
Low Byte of Restart Vector

DES
INS

3

Op Code Address
Op Code Address + 1
Previous Register Contents

1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data

INX
DEX

3

Op Code Address
Op Code Address + 1
Address Bus F F F F

1
1
1

Op Code
Op Code of Next Instruction
Low Byte of Restart Vector

PSHA
PSHB

3

Op Code Address
Op Code Address + 1
Stack Pointer

1
1

0

Op Code
Op Code of Next Instruction
Accumulator Data

TSX

3

Op Code Address
Op Code Address + 1
Stack Pointer

1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data

TXS

3

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Op Code of Next Instruction
Low Byte of Resturt Vector

PULA
PULB

4

3
4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1 .

1
1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data

1
2
3
4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1

1
1

0
0

Op Code
Irrelevant Data
Index Register (Low Order Byte)
Index Register (High Order Byte;

1
2

3
4
5
1
2
3
4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer +2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1

1
1
1
1
1
1
1
1
1

5

Stack Pointer + 2

1

1
2

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1

1
1

ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM

DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA

SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST

3
1
2

3
1
2

3
1
2

3
1
2

3
1
2

3
1
2

3

PSHX

PULX

RTS

WAI**

4

5

5

9

1
2

3
4

0
0

Op Code
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)
Op Code
Irrelevant Data
Irrelevant Data
Address of Next Instruction
(High Order Byte)
Address of Next Instruction
(Low Order Byte)
Op Code
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
(Continued)

$

HITACHI

55

H06803,H06803-1---------------------------------------------------------Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions

Cycles

Cycle
;::

5
6
7

WAI""

10

SWI

10

12

Pointer
Pointer
Pointer
Pointer
Pointer

-

2
3
4
5
6

Data Bus
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register

10

Op Code Address
Op Code Address + 1
Address Bus FFFF
Address Bus F F F F
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus F F F F
Address Bus FFFF
Address Bus FFFF

1
1
1
1
1
1
1
1
1
1

Op Code
Irrelevant
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte

1
2
3
4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1

1
1
1
1

5

Stack Pointer + 2

1

6

Stack Pointer + 3

1

7

Stack Pointer + 4

1

8

Stack Pointer + 5

1

9

Stack Pointer + 6

1

10

Stack Pointer + 7

1

Op Code
Irrelevant Data
Irrelevant Data
Contents of Condo Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from
Stack (High Order Byte)
Next Instruction Address from
Stack (Low Order Byte)

10
11

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Stack Pointer - 7
Vector Address FFFA (Hex)

1
1
0
0
0
0
0
0
0
1
1

12

Vector Address FFFB (Hex)

1

1
2
3
4
5
6
7

8
9
RTI

Stack
Stack
Stack
Stack
Stack

R/W
line
0
0
0
0
0

8
9
MUL

Address Bus

1
2
3
4
5
6
7

8
9

Data
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart

Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector

Op Code
Irrelevant Data
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)
(Continued)

•• While the MPU is in the "Wait" state, its bus state will appear as a series of MPU reads of an address which is seven locations less than the
original contents of the Stack Pointer. Contrary to the HD6800, none of the ports are driven to the high impedance state by a WAI
instruction.

56

~HITACHI

----------------------------------------------------------H06803,H06803-1
Table

12 Cycle by Cycle Operation (Continued)

RELATIVE
Address Mode &
Instructions

R/W
Line

Cycles

Cycle

3

1

Op Code Address

1

Op Code

2
3

Op Code Address + 1
Address Bus FFFF

1
1

Branch Offset
Low Byte of Restart Vector

BCC BHT BNE
BCS BLE BPL
BEQ BLS BRA

Address Bus

#

Data Bus

BGE BL T BVC
BGT BMT BVS
BRN

6

BSR

•

1

Op Code Address

1

Op Code

2

Op Code Address + 1

1

Branch Offset

3

4

Address Bus FFFF
Subroutine Starting Address

1
1

Low Byte of Restart Vector
Op Cl)de of Next Instruction

5
6

Stack Pointer

0

Return Address (Low Order Byte)

Stack Pointer - 1

0

Return Address (High Order Byte)

Summary of Undefined Instruction Operations

When the op codes (4E. SE) are used to execute. the MPU
continues to increase the program counter and it will not stop
until the Reset signal enters. These op codes are used to test the

The HD6803 has 36 underfined instructions. When these are
carried out, the contents of Register and Memory in MPU
change at random.

Table 13

LSI.

Op codes Map

HD6803 MICROPROCESSOR INSTRUCTIONS

OP
CODE

i ACC
I

~
La

0000

0

0001

1

0010

2

0011

3

0100

4

0000

0001

0010

0011

0

1

2

3

SBA

BRA

TSX

CBA

BRN

INS

~---

BHI

PULA (+1)

~
~

BLS

PULB (+1)'

LSRD (+1)

BCC

DES

ASLD(+1)

~

BCS

TXS

TAP

TAB

BNE

PSHA

NOP
----------------

-----------------------

A

~CCIIND

ACCA or SP
EXT

0100 0101 10110 0111
4

:

5

7

\ 6
NEG

------

ACCB or X

IMM \ DIR \IND \ EXT

IMM \ DIR \IND \ EX~

1000 \1001 \1010 \1011

1100 \1101 \1110\1111

S

1 9

1 A

1 B

C

1 DIE

I

F
0

SUB

:=========- .

CMP

1

SBC

2

--

-------------

SUBD (+2)

COM

·

ADDD (+2)

--- 3

'---

0111

7

TPA

TBA

BEQ

PSHB

--------

1000

S

INX (+1)

~

Bve

PULX (+2)

ASL

EOR

8

1001

9

DEX (+1)

DAA

BVS

RTS (+2)

ROL

ADC

9

DEC

ORA

A

0101

5

0110

6

LSR

AND
BIT

5

ROR

LDA

6

ASR

1010

A

CLV

~

BPL

ABX

1011

B

SEV

ABA

BMI

RTI (+7)

1100

C

CLC

~

BGE

PSHX (+1)

1101

D

SEC

BLT

MUL (+71

TST

1110

E

Cli

BGT

WAI (+61

___ •• -- I JMP (-3)

1111

F

SEI

~.

BLE

SWI (+91

CLR

1/2

1/2

2/3

1/3

BYTE/CYCLE
[NOTES)

/
/

--------====

.

INC

1/2

1/2

I

2/6

~

BSR
1+4)

.

2/2

/\

STA

STA

i 7

ADD

I

CPX (+2)
JSR (+21
LDS (+1)
STS (+11

; (+1)1

3/6

14

i

2/3

1 2/4

13/4

B

·
·

LDD(+1)

; (+111

LDX (+1)

• (+1-1\

2/2

STD (+1)

STX (+11

C

10
!E

!F

I 2/3 I 2/4 I 3/4 I

11 Undefined Op codes are marked with ~ .
21 (

1 indicate that the number in parenthesis must be added to the cycle count for that instruction.

31 The instructions shown below are all 3 bytes and are marked with ......
Immediate addressing mode of SUBD, CPX, LDS, ADDD, LDD and LDX instructions, and undefined op codes
(SF, CD, CFI.
41 The Op codes (4E, 5EI are 1 by tel"" cycles instructions, and are marked with ......

$

HITACHI

57

J:

U1
00

o

0)

CO

o

5N

J:

o

0)

CO

o


(NC>
O./A.

[~~

A'2

~~

A13

~~

A,.

[2:2 A,s

03/A3

[~1 Vee

O./A.
O./A.

[~O A7/P17

[lj

As/P,s

D~8 As/P,s

Oz A.jP,.
[(6 A3/P13
A,.
A,.
"-'\_ _ _ _ _ _ _~ Vee

(Top View)

(Top View)

•

(Top View)

BLOCK DIAGRAM

.........--1-~- P20

...-,-.....+-- P2'

tM--+---- and Mode ContrOl Regis1t'

Bit 7

I

1 CC1! CCo

l

Bit 0

55115501$10

Transmit/Receive Control and Status Register

$12

Port

'2

8.~
~

ReceivJ Shift Register

L -____________-,~----____- -__~

Clock
10
Bit ~--------.......

....- - - - - E

2

~---.------Transmit Data Register

Figure 19 Serial I/O Register

o

6

x

x

CCl

CCO

SSl

SSO

AD DR

$0010

Transfer Rate / Mode Control Register

Table 5

74

SCI Bit Times and Transfer Rates

XTAL

2.4576 MHz

I

4.0 MHz

E

614.4 kHz

!

1.0MHz

4.91S2MHz

SSl

SSO

0

0

E.;. 16

26 ~s/38.400 Baud

16

0

1

E.;. 128

208iJs/4,800 Baud

128 ~s/7B12.5 Baud

104.2/,/s/ 9.600BaOO

1

0

E.;. 1024

1.024ms/976.6 Baud

833.3/,/s/ 1.200BaOO

1

1

E.;. 4096

4.096ms/244.1 Baud

3.333ms/

1

1.67ms/600 Baud
6.67ms/150 Baud

I

~HITACHI

~s/62,500 Baud

12288MHz
13

/,/ s/76.800Baud

300Baud

------------------------------------------------HD6303R,HD63A03R,HD63B03R
Table
CC1:CCO

Format

0
0

0

-

1

NRZ

1

0

1

1

NRZ
NRZ

6 SCI Format and Clock Source Control
Clock Source

Port 2 Bit 2

Port 2 Bit 3

Port 2 Bit 4

-

-

-

......

!

Internal
Internal

Not Used ***
Output·

External

Input

··..
·.

• Clock output is available regardless of values for bits RE and TE .
•• Bit 3 is used for serial input if RE = "1" in TRCS.
Bit 4 is used for serial output if TE = "1" in TRCS .
••• This pin can be used as I/O port.
•

Transfer Rate/Mode Control Register (RMCR)

The register controls the following serial I/O functions:
• Bauds rate
'data format
• clock source
• Port 2 bit 2 feature
It is 4·bit write-only register, cleared by RES. The 4 bits are
considered as a pair of 2·bit fields. The lower 2 bits control the
bit rate of internal clock while the upper 2 bits control the
format and the clock select logic.
Bit 0 SSO}
Bit 1 SS 1
Speed Select
These bits select the Baud rate for the internal clock. The
rates selectable are function of E clock frequency of the CPU.
Table 5 lists the available Baud Rates.
Bit2 CCO }
Bit 3 CCI
Clock Control/Format Select
They control the data format and the clock select logic.
Table 6 defines the bit field.
•

I nternally Generated Clock

If the user wish to use externally an internal clock of the
serial I/O, the following requirements should be noted.
• CCl, CCO must be set to "10".
• The maximum clock rate must be E/I6.
• The clock rate is equal to the bit rate.
• The values of RE and TE have no effect.
•

•

Externally Generated Clock

If the user wish to supply an external clock to the Serial
I/O, the following requirements should be noted.
• The CC 1, CCO must be set to "11" (See Table 6).
• The external clock must be set to 8 times of the desired
baud rate.
• The maximum external clock frequency is E/2 clock.
•

Serial Operations

The serial I/O hardware must be initialized by the software
before operation. The sequence will be normally as follows.
'Writing the desired operation control bits of the Rate and
Mode Control Register.
• Writing the desired operation control bits of the TRCS
register.
If Port 2 bit 3, 4 are used for serial I/O, TE, RE bits may be
kept set. When TE, RE bit are cleared during SCI operation,
and subsequently set again, it should be noted that TE, RE
must be kept "0" for at least one bit time of the current baud
rate. If TE, RE are set again within one bit time, there may be
the case where the initializing of internal function for transmitter and receiver does not take place correctly.
•

register. When set, the output of the transmit shift register
is connected with Port 2 bit 4 which is unconditionally con·
figured as an output.
After RES, the user should initialize both the RMC register
and the TRCS register for desired operation. Setting the TE bit
causes a transmission of ten·bit preamble of" I "s. Following the
preamble, internal synchronization is established and the trans·
mitter is ready to operate. Then either of the following states
exists.
(1) If the transmit data register is empty (TDRE = \), the
consecutive "\ "s are transmitted indicating an idle
states.
(2) If the data has been loaded into the Transmit Data
Register (TDRE = 0), it is transferred to the output
shift register and data transmission begins.
During the data transfer, the start bit ("0") is first trans·
ferred. Next the 8·bit data (beginning at bit 0) and finally the
stop bit ("I "). When the contents of the Transmit Data Register
is transferred to the output shift register, the hardware sets the
TDRE flag bit: If the CPU fails to respond to the flag within
the proper time, TDRE is kept set and then a continuous string
of I's is sent until the data is supplied to the data register.

Transmit Operation

Data transmission is enabled by the TE bit in the TRCS

Receive Operation

The receive operation is enabled by the RE bit. The serial
input is connected with Port 2 bit 3. The receiver operation
is determined by the contents of the TRCS and RMC register.
The received bit stream is synchronized by the first "0" (start
bit). During 10·bit time, the data is strobed approximately at
the center of each bit. If the tenth bit is not "I" (stop bit),
the system assumes a framing error and the ORFE is set.
If the tenth bit is "I", the data is transferred to the receive
data register, and the RDRF flag is set. If the tenth bit of the
next data is received and still RDRF is preserved set, then
ORFE is set indicating that an overrun error has occurred.
After the CPU read of the status register as a response to
RDRF flag or ORFE flag, followed by the CPU read of the
receive data register, RDRF or ORFE will be cleared.
•

RAM CONTROL REGISTER

The register assigned to the address $0014 gives a status
information about standby RAM.
RAM Control Register

a ..

1 s:.:.r 1':"'1 1: 1 : 1' 1' 1: I
5

Bit 0 Not used.
Bit 1 Not used.
Bit 2 Not used.

~HITACHI

75

HD6303R,HD63A03R,HD63B03R-----------------------------------------------Bit 3 Not used.
Bit 4 Not used.
Bit 5 Not used.
Bit 6 RAM Enable.
Using this control bit, the user can disable the RAM. RAM
Enable bit is set on the positive edge of RES and RAM is
enabled. The program can write "1'\ or "0". If RAME is
cleared, the RAM address becomes external address and the
CPU may read the data from the outside memory.
Bit 7 Standby Bit
This bit can be read or written by the user program. It is
cleared when the Vee voltage is removed. Normally this bit
is set by the program before going into stand-by mode. When
the CPU recovers from stand-by mode, this bit should be
checked. If it is "I ", the data of the RAM is retained during
stand-by and it is valid.
•

GENERAL DESCRIPTION OF INSTRUCTION SET
The HD6303R has an upward object code compatible with
the HD6801 to utilize all instruction sets of the HMCS6800.
The execution time of the key instruction is reduced to increase
the system through-put. In addition. the bit operation instruction. the exchange instruction between the index and the
accumulator. the sleep instruction are added. 111is section
describes:
• CPU programming model (See Fig. 20)
• Addressing modes
• Accumulator and memory manipulation instructions (See
Table 7)
• New instructions
• Index register and stack manipulation instructions (See
Table 8)
• Jump and branch instructions (See Table 9)
• Condition code register manipulation instructions (See
Table 10)
·Op-code map (See Table II)
• Cycle-by-cycle operation (See Table 12)

• CPU Programming Model
The programming model for the HD6303R is shown in Figure 20. The double accumulator is physically the same as the
accumulator A concatenated with the accumulator B, so that
the contents of A and B is changed with executing operation of
an accumulator D.

f .
tS- -

1,5
1,5
1,5

-

- -

- -

-

°U

7

B

0 - - -

- -

- -

X

-

~

7

8-Bit Accumulators A and B

~ Or 16·Bit Double Accumulator 0

01

Index Register (X)

01

Stack Pointer (SP)

01

Program Counter (PC)

,
11

PC

every instruction is shown along with execution time given in
terms of machine cycles (Table 7 to 11). When the clock
frequency is 4 MHz, the machine cycle will be microseconds.
Accumulator (ACCX) Addressing
Only the accumulator (A or B) is addressed. Either accumulator A or B is specified by one-byte instructions.
Immediate Addressing
In this mode, the operand is stored in the second byte of the
instruction except that the operand in LDS and LDX, etc are
stored in the second and the third byte. These are two or
three-byte instructions.
Direct Addressing
In this mode, the second byte of instruction indicates the
address where the operand is stored. Direct addressing allows
the user to directly address the lowest 256 bytes in the machine;
locations zero through 255. Improved execution times are
achieved by storing data in these locations. For system
configuration, it is recommended that these locations should be
RAM and be utilized preferably for user's data realm_ These are
two-byte instructions except the AIM, OIM, ElM and TIM
which have three-byte.
Extended Addressing
In this mode, the second byte indicates the upper 8 bit
addresses where the operand is stored, while the third byte
indicates the lower 8 bits. This is an absolute address in
memory. These are three-byte instructions.
Indexed Addressing
In this mode, the contents of the second byte is added to the
lower 8 bits in the Index Register. For each of AIM, OIM, ElM
and TIM instructions, the contents of the third byte are added
to the lower 8 bits in the Index Register. In addition, the resulting "carry" is added to the upper 8 bits in the Index Register.
The result is used for addressing memory. Because the modified
address is held in the Temporary Address Register, there is no
change to the Index Register. These are two-byte instructions
but AIM, OIM, ElM, TIM have three-byte.
Implied Addressing
In this mode, the instruction itself gives the address; stack
pointer, index register, etc. These are I-byte instructions.
Relative Addressing
In this mode, the contents of the second byte is added to the
lower 8 bits in the program counter. The resulting carry or
borrow is added to the upper 8 bits. This helps the user to
address the data within a range of -126 to + 129 bytes of the
current execution instruction. These are two-byte instructions_

0

H

I

N

Z V C

condit_ion Code Reg.iSter (eeRI
Carry IBorrow from MSB
Overflow

Zero
Negative
Interrupt
Half Carry (From Bit 3)

Figure 20 CPU Programming Model

• CPU Addressing Modes
The HD6303R has seven address modes which depend on
both of the instruction type and the code. The address mode for

76

~HITACHI

~~~~~~~~~~~~~~~~~~~~~~~-HD6303R,HD63A03R,HD63B03R

Table 7 Accumulator, Memory Manipulation Instructions
Condition Code
Addressing Modes
Operations

Add
Add Doable

Mnemonic

IMMEO

DIRECT

Register

EXTEND

INDEX

Boolean/
Arithmetic Operation

IMPLIED

-

OP

-

#

OP

-

#

OP

-

#

OP

-

#

ADDA

BB

2

2 9B

3

2

AB 4

2

BB

4

3

A+M- A

ADDB

CB

B+M-B

ADOD

C3

2 2 DB 3 2 EB 4 2 FB 4 3
3 3 03 4 2 E3 5 2 F3 5 3

OP

#

A:B+M:M+l-A:B
lB

A + B- A

ABA
ADCA

B9

2 2 99

3 2

A9

4

2

B9

4

3

A+M+C-A

ADCB

2

2

3

2

E9

4

2

F9

4

3

B+M+C-B

2

2 94

3 2

A4

4

2

B4

4

3

A'M-A

2

3 2

09

1

1

Add Accumulators
Add With c.rry
AND

ANDA

C9
B4

ANOB

C4

2

2

E4

4

2

F4

4

3

B'M-B

Bit Test

BITA

85

2

2 95

A5

4

2

B5

4

3

A·M

BIT B

C5

2

2 05 3 2 E5

4

2

F5

4

3

Clear

CLR

Compare

6F

5 2 7F

B'M
OO-M

5 3
4F

1

1 00- A

CLRB

5F

1

1 00 - B
A-M

CMPA

81

2

2 91

3 2

Al

4

2

Bl

4

3

CMPB

Cl

2 2 01

3 ,2

El

4

2

Fl

4

3

63

6

2

73

6

3

Compere
Accumulators

CBA
COM

B-M
11

1

1

A-B
M-M

COMA

43

1

1

A -A

COMB

53

1

1

B -B

Complement, 2's

NEG

(Negata'

NEGA
NEGB

Decimal Adjust. A

OAA

Decrement

DEC

Increment

3

CLRA

Complement, l's

exclUSive OR

04

60

6

2

70

6

OO-M-M

3
40

SA

6

2

7A

6

1

1 OO-A-A

1 1 00-B-8

19

2 1 characters mto BCD format

C8

6C

6

2 7C

6

B@M- B

INCA

4C

1 1

A+ l - A

INCB

5C

1 1

B + 1- B

4

3

M-A

LDAB

2 2 96 3 2 A6 4 2 B6
C6 2 2 06 3 2 E6 4 2 F6

4

3

M-B

Load Double
Accumulator

LDD

CC

FC

5

3

Multiply Unsigned

MUL

OR, Inclusive

ORAA

8A

ORAB

CA 2

Load
Accumulator

Push Data

LOAA

86

3

3

DC 4

2

EC

5

2

3

2

AA 4

2

BA 4

3

OA 3

2

EA 4

2

FA 4

3

2 2 9A
2

PSHA

Rotata Laft

1

A + M- A
8 + M- B
36

4

1 A - MsP, SP - 1 - SP
1

37

.4

32

3

PULB

3 1 SP + 1 - SP, MsP - B

49

1

59

1 1

ROL

69

6

2 79

6

ROLB
ROR

66

6

2 76

6

B - MsP, SP - 1 - SP
1 SP+l-SP,MsP- A

3
1

:\ C¢=1' ! ! ! ! , !
B

b7

bO

3

RORA

46

1

1

RORB

56

1

1

Note) Condition Code Register will be explained in Note of Table 10.

~HITACHI

I

I

I

I

I

I

I

I

I

I

I

I

I

I

:

I

I

I

I

I

I

I

I

I
R

I

I

R

I

I

R

···
·

:jl{}1! , ! ! ! ! !
B

b7

I

I I R
R S R R
R S R R
R S R R

I

I

I

I

I

I

I

I

I

I

I

I

I

I

R S

I

I

R S

I

I

R S

t
t
t

t

(1)

'2'1

I

' ~1~

2,

t

(1) ;2,

t

(3)

(~

CO{)

•

(~,

I

I
I
I

I
I

I
I

® •

I

I

@ •

I

I

I
I

R

I

I

R

I
I

t R

I
I
I
I
I
I

I @ I
I @ I
I @ I
I @ I
I @ I
I (i) I

R

R

@ •

R

@

AxB-A:B

33

ROLA
Rotat, Right

7

PULA

PSHB
Pull Data

M + 1- B, M- A
30

I

I

M + 1 -M

3

I

I

A@M-A

I

I

I

1 B-l-B

C

I

I

1 A -1- A

1

1 0

I

I

1

INC

2

t I

5A

EORB

··
· ··
·
·
·· ··
·· ··
·· ··
··· ···
·· ··
·· ··
·· ··

3

I

4A

2 2 98 3 2 AS 4 2 B8 4 3
2 2 08 3 2 E8 4 2 F8 4 3

I N Z V

M-l -M

DECB

88

H

Converts binary add of BCD

DECA
EORA

4

·· ··
·· ·· ..
·· ·· ·
··· ··· ·
·· ·· ·
·· ·· ··
·· ·· · · · ·
··· ··· ·· ·· ·· ···
· ·· ·· ·· ·· ··
·
iJ · ·
·· ··
~ ··
·· ··

50

3

5

bO

I

R

(to be continued)

77

Table 7 Accumulator, Memory Manipulation Instructions
Condition Code
Register

Addressing Modes
Operations

Mnemonic

IMMED
OP

Shift Left
Arithmetic

Double Shift
Left. Arithmetic
Shift Right
Arithmetic

Shift Right
Logical

Double Shift
Right logical

-

DIRECT
#

OP

-

EXTEND

INDEX

#

ASL

OP -

#

OP

-

#

68

2 78

6

3

6

Booleanl
Arithmetic Operation

IMPLIED
OP

-

#

M}

_

A ~lIlllllt-o

1

ASLB

48
58

ASLD

05

1 1 ~

ASLA

1

1 1

8

b7

"7

ASR

67

6

2

77

6

3

ASRA

47

1

ASRB

57

1 1

LSRA

44

1

LSRB

54

1 1

lSRD

04

1 1

LSR

64

6

2

74

6

1

"0

=1 CCI
8

bO

A~ ~

b7

1

_

8

b7

0-01
"7

--

3

2

A7

4

2

B7

4

3

A-M

STAB

07

3

2

E7

4

2

F7

4

3

Store Double
Accumulator

STD

DO 4

2

ED 5

2

FD 5

3

B-M
A_M
B _ M+ 1

Subtract

SUBA

80

2

2

90

3

2

AO

4

2

BO

4

3

A-M -A

SUBB

CO

2

2

DO

3

2

EO

4

2

FO

4

3

B -M-B

3 3

B3

Subtract
With CarrV

SBCA

82

2

2 92

3

2

A2

4

2

B2

4

3

SBCB

C2

2

2

02

3

2

E2

4

2

F2

4

3

Transfer
Accumulators

TAB

Test Zero or
Minus

TST

5

A:B-M:M+l-A:B

5 3

SBA

4

2

2

Subtract
Accumulators

83

93

A3

SUBD

10

4

2

70

4

A-B-A

B-M-C-B

17
60

1 1

A-M-C-A
16

TBA

1 1
1 1

A-B
B-A
M-OO

3

TSTA

40

1

1 A -00

T5TB

50

1

1 B - 00

And Immediate

AIM

OR Immediate

OIM

EOR Immediate
Test Immediate

71

6

72

6

3
3

ElM

3 61 7
3 62 7
75 6 3 65 7

TIM

7B

4

3
3 6B 5 3

bO

"CC"oAl 8~CC 8 80~

97

Double Subtract

iii

AO--lIIIIIIII~

STAA

Store
Accumulator

\,-0

IITIi IbOrQ

M}

3

m: I
87

M·IMM-M
M+IMM-M
M®IMM-M
M·IMM

5

4

H

I N Z

·· ··
·· ··
··· ··
·· ··

3

2 1 0
V

C

®

~

~

~

~

~ ~ l

~

l ~ ~

~

l @l

l 6 l
6 l
~ l
l 6 l
.' l
R l 6 ~
R l @l
R ~ @l

··
··
·· ··
·· ··
·· ··
·· ··
·· ··
·· ··
·· ··
••
••
••
••

l

@l

R

~

~

~

R

l

l

R

l

l R

l
f

l
l
l

f
f
f

~

f

f

l

f

f
f

f

~

f
f

f

~

R

~

~

R

~

f

R R

f

~

R R

~

l R R

t
t
t
t

t
t
t
t

~

R
R
R
R

··
·
f

l
f

l

··
•
•
•

•

Note) Condition Code Register will be explained in Note of Table 10.

• New Instructions
In addition to the HD6801 Instruction Set, the HD6303R
has the following new instructions:
AIM----(M)· (IMM)~(M)
Evaluates the AND of the immediate data and the
memory, places the result in the memory.
OIM---- (M) + (IMM) ~ (M)
Evaluates the OR of the immediate data and the
memory, places the result in the memory.
EIM----(M)(!) (IMM)~ {M)
Evaluates the EOR of the immediate data and the
contents of memory, places the result in memory.

78

TIM----(M) • (lMM)
Evaluates the AND of the immediate data and the
memory, changes the flag of associated condition code
register
Each instruction has three bytes; the fust is op-code, the
second is immediate data, the third is address modifier.
XGDX--(ACCD) ~ (IX)
Exchanges the contents of accumulator and the index
register.
'SLP- - --The MPU is brought to the sleep mode. For sleep
mode, see the "sleep mode" section.

eHITACHI

Table 8 Index Register, Stack Manipulation Instructions
Addressing Modes
POinter Operations

Mnemonic

IMMED.
OP
#

-

EXTEND

#

OP

-

IMPLIED

OP

-4

#

OP

-

#

2

AC 5

BC

5

3

09

I

I

X-M:M+I
X -I-X
SP-I-SP

-

Compare Indu Reg

CPX

Decrement Index Reg

DEX

Decrement Stack Pntr

DES

34

I

I

Increment Index Reg

INX

08

I

I

X + 1- X

Increment Stack Pntr

INS

31

I

I

sP+I-SP

load Ind4ix Reg

lOX

CE

3

load Stack Pntr

lOS

BE

3 3 9E

Store Index Reg

STX

Stack Pntr
-Store
-_

STS

8C

~-f-

...

3

2

2

EE

5

2

FE

5

3

4

2

AE 5

2

BE

5

3

OF

4

2

EF

5

2

FF

5

3

9F

4

2

AF 5

2

BF

5

3

DE 4

I

XH-M,X L -1M + II
SP H - M, SP L - IM+ II
X-I-SP

I

SP+I-X

35

1

TSX

30

Add

ABX

3A

I
I

Push Dlla

PSHX

3C

5

Pull Data

PUlX

38

4

1

Exchange

XGDX

18

2

1 ACCD-IX

Index Reg - Stack Pntr

f-------

-

•

------~--

I

Condition Code
Register
5 4 3 2 I 0
H I N Z V C

·· ·· · • · ·
·· ·· ·· · ·· ··
·• ·· · ·• ···
·· · • ··
·· · · ·• ··•
··• ···· ···· ··
··· ··
t

t

t

t

t

M - XH, 1M + 1) - XL
M- SPH, (M+ll-SPL

Stack Pntr - Index Reg

-------~~-

TXS

3 3 9C

8o0leanl
Arithmetic Operation

INDEX
OP
#

DIRECT

B +X- X
XL - M.. , SP - I - SP
XH- MIP , SP - 1 - SP
SP + 1- SP,MIP - XH
SP + 1- SP, M.. - XL

(i)

• ®
®
.®

R

t

R

R

R

·• ·• ·• · · ·
•••

Note) Condition Code Register will be explained in Note of Table 10.

Table 9 Jump, Branch Instruction
Addressing Modes
Operations

Mnemonic

RELATIVE
OP

Branch Always

BRA

20

Branch Never

BRN

Branch If Carry Clear

BCC

21
24

Branch If Carry Sat
Branch If • Zero

BCS
BEQ

Branch If

Zero

BGE

Branch If > Zero
Branch If Higher

BGT
BHI

Branch If " Zero
8ranch If lower Or
Same

~

-3

#

DIRECT
OP

-

#

INDEX
OP

-

EXTEND
#
OP

-

#

Branch Test

IMPLIED

-

OP

#

2

None

3 2

None

3

2

C=O

25
27

3

2

C=1

2C
2E

3

Z·1
N0 V-O

3 2
I

2

BlE

22
2F

3 2
3 2
3 2

BlS

23

3 2

8ranch If < Zero
Branch If Minus

8lT
BMI

20

N 0 V-I

2B

3 2
3 2

Branch If Not Equal
Zero

BNE

26

3

Z-O

Branch If Overflow
Clear

BVC

28

3 2

V-O

Branch If Overflow Set

BVS

29

3 2

V -,

Branch If Plus

BPl

2A

3 2

N-O

Branch To Subroutine

80 5

Jump

BSR
JMP

Jump To Subroutine

JSR

No Operation

NOP

01

Raturn From Interrupti

RTI

3B 10 1

Return From
Subroutine
Software Intarrupt
Wait for InterruptSleep

RTS

39

SWI
WAI
SLP

3F 12 1
3E 9 1
lA 4 1

I

Z + IN 0 VI - 0
C+Z=O

i
I

Z + IN 0

VI-I

C+Z-l

i

N -I

2

2
3

2

7E

AD 5

2

BD 6

6E
90

5

2

3 3
3
1 1

Advances Prog. Cntr.
Only

5 1

Nt) ·WAf puts R/W hIgh; Address Bus goes to FFFF; Data Bus goes to the three state.
o e Condition Code Register will be explained in Note of Table 10.

eHITACHI

Condition Code
Register
5 4 3 2 1 0
H I N Z V C

·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
··· ··· ··· ··· ··· ···
··· ··· ··· ··· ··· ···
··· ··· ··· ··· ··· ···
· · ·· ··
·•· ·• ··• ··•· ··· ···
••
--@-

S

• @ •

79

HD6303R,HD63A03R,HD63B03R-----------------------------------------------Table 10 Condition Code Register Manipulation Instructions
Condition Code Register

AddressingModes

[NOTE']

Condition Code
(1)
(Bit V)
(ji
(Bit C)
(3)
(Bit C)
.:~)
(Bit V)
':!D (Bit V)
'6; (Bit V)
(7)
(Bit N)
'8;
(All Bit)
9:
(Bit I)

!1Qj
(11)

(All Bit)
(Bit C)

OC
OE
OA

ClC
Cli
ClV
SEC
SEI
SEV
TAP
TPA

CI.ar Carry
CI.ar Interrupt Mask
CI.arOverfiow
Set Carry
Set Interrupt Mask
SetOwrflow
Accumulator A - CCR
CCR - Accumulator A

Boolean Operation

IMPLIED
OP

Mnemonic

Operations

- "

3

2

1

0

I

N

Z

V

C
R

R

1

1

0-1

1

1

00

1

1

O-V
l-C

OF
OB
06

1

1

1-1

I
I
I

I
I
I

I-V
A- CCR
CCR - A

07

4

H

·· · ·· ·· ·· ·
·· ·· ·· ·· · ·
·· · ·· ·· · ··
······

O-C

1

1

5

--

R

S

S

S

---

10

---

Register Notes: (Bit set if test is true and cleared otherwise)
Test: Result = 1000oo00?
Test: Result,\ 00000000?
Test: BCD Character of high-order byte greater than 9? (Not cleared if previously set)
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
Test: Set equal to NeC=1 after the execution of instructions
Test: Result less than zero? (Bit 15=1)
Load Condition Code Register from Stack.
Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exit the wait
state.
Set according to the contents of Accumulator A.
Result of Multiplication Bit 7= 1 of ACCB?

[NOTE 2] Cli instruction and interrupt.
If interrupt mask-bit is set (1="''') and interrupt is requested (iAO;" = "0" or i'R'Q'; = "0"),
and then CLI instruction is executed, the CPU responds as follows.
The next instruction of CLI is one-machine cycle instruction.
Subsequent two instructions are executed before the interrupt is responded.
That is, the next and the next of the next instruction are executed.
@ The next instruction of CLI is two-machine cycle (or more) instruction.
Only the next instruction is executed and then the CPU jump to the interrupt routine.
Even if TAP instruction is used, instead of CLI, the same thing occurs.

CD

Table 11
OP
CODE

~o ___
0000
0

lO

0000
0001
0010

0011
0100
0101

OliO
0111
1000
1001

1

NOP

2 ~
3 ~
4 lSRD
5 ASLO
6 TAP
7 TPA

0001
1
SBA
CBA

...-/
...-/
...-/

---

TAB
TBA

0010

0011

2

3
TSX

BRA
BRN
BHI
BlS
BCC
BCS
BNE
BEQ

8

INX

9

DEX
CLV

XGDX BVC
DAA
BVS
BPl
SlP

SEV
ClC

~

SEC

...-/

1010 A
lOll B
1100 C
1101 0
1110

E Cli

""

F ·SEI

0

ABA

BMI
BGE

BlT
~ BGT
~ BlE
1

2

INS
PULA
PUlB
DES
TXS
PSHA
PSHB
PUlX
RTS
ABX
RTI
PSHX
MUl
WAI
SWI

3

ACC i ACC
IND
A i B
0110
0100
0101
4
6
1 5
NEG

I

----

OP-Code Map

1%
OIR

I

Oil 1

1

7

AIM

~

I

OIM

SBC
SUBD
AND
BIT

--

6

---'I

STA

STA

7

ASl
ROl

EOR
ADC

8

DEC

9RA
ADD

A

TIM
INC

9
B

CPX

TST

JSR

BSR 1

~---

JMP

~I

CLR
6

1

......-------'1

___ l

lOS
7

8

UNDEFINED OP CODE ~
* Only for instructions of AIM, OIM, ElM, TIM

80

4
5

lOA

"""-------'1

0
1

2
3

ADDD

ElM
ROR
ASR

1 5

ACCA or SP
ACCB or X
IMM 1 OIR liND 1 EXT
IMM 1 DIR liND 1 EXT
1000 1 1001 1 1010 1 lOll
1100 I 1101 1 1110 1 1111
C
8 1 9 1 A 1 B
o I E I F
SUB
CMP

COM
lSR

~

4

•

~HITACHI

1 9

STS

1 A

LDD

C

STD
lOX

E

0

STX

1 B

C

1

o

I

E

F

I

F

------------------------HD6303R.HD63A03R.HD63B03R
• Instruction Execution Cycles
In the HMCS6800 series, the execution cycle of each instruction is the number of cycles between the start of the current
instruction fetch and just before the s~art of the subsequent
instruction fetch.
The HD6303R uses a mechanism of the pipeline control
for the instruction fetch and the subsequent instruction fetch
is performed during the current instruction being executed.

Therefore, the method to count instruction cycles used in
the HMCS6800 series cannot be applied to the instruction
cycles such as MULT, PULL, DAA and XGDX in the HD6303R.
Table 12 provides the information about the relationship
among each data on the Address Bus, Data Bus, and R/W status
in cycle-by-cycle basis during the execution of each instruction.

Table 12 Cycle-by-Cycle Operation
Address Mode &
Instructions

IMMEDIATE
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
ADDD CPX
LDD
LDS
LDX
SUBD
DIRECT
ADC
AND
CMP
LDA
SBC
STA

ADD
BIT
EOR
ORA
SUB

Address Bus

1
2

3

CPX
LDS
SUBD

STD
STX

STS

1

I
1
2
3

Op Code Address+ 1
Op Code Address+2
Op Code Address+3

1
2
3

Op Code Address + 1
Address of Operand
Op Code Address+2

I

i

I

Operand Data
Next Op Code

I

1
1

1

I
I

i

i

1

1
1
I

4

1
2
3
1
2
3

4
4

1
2
3

4
JSR

5

1
2
3

4
5
TIM

4

1
2
3

4
AIM
OIM

1

I

I

Operand Data (MSB)
Operand Data (LSB)
Next Op Code

--

---

Address of Operand (LSB)
Operand Data
Next Op Code

I

3
ADDD
LDD
LDX

Op Code Address+ 1
Op Code Address+2

2

3

Data Sus

ElM

6

1
2
3

4
5
6

Op Code Address+ 1
Destination Address
Op Code Address+2
Op Code Address+ 1
Address of Operand
Address of Operand + 1
Op Code Address+2
Op Code Address+ 1
Destination Address
Destination Address+ 1
Op Code Address+2
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer-l
Jump Address
Op Code Address+ 1
Op Code Address+2
Address of Operand
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
Address of Operand
·FFFF
Address of Operand
Op Code Address+3

-----L----_ _ _ _ _ _ _ _ _ _ I

1

a
1
1
1
1
1
1

a
a
1
1
1

a
a
1
1
1
1
1
1
1
1
1

a
1

~_

Destination Address
Accumulator Data
Next Op Code
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Next Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
- Continued -

~HITACHI

81

Table 12 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions

INDEXED
JMP

1

2

3
ADC
AND
CMP
LDA
SBC
TST
STA

ADD
BIT
EOR
ORA
SUB

3
1
2
3

4

4

I

4

1
2
3

4
ADDD
CPX
LDS
SUBD
STD
STX

LDD
LDX

5

1
2
3

4
5
STS
I
I

5

1
2
3

4
5

I

JSR

i

5

1
2
3

4
5
ASL
COM
INC
NEG
ROR

ASR
DEC
LSR
ROL

i

6

I

TIM

1
2
3

4
5
6
1

2
5

3

4
5
CLR

5

1
2
3

4
5
AIM
OIM

Data Bus

Address Bus

ElM

1
2
3

7

4
5
6
7

Op Code Address+ 1
FFFF
Jump Address
Op Code Address+ 1
FFFF
IX + Offset
Op Code Address+2

1
1
1
1
1
1
1

Offset
Restart Address (LSB)
First Op Code of Jump Routine
Offset
Restart Address (LSB)
Operand Data
Next Op Code

Op Code Address+ 1
FFFF
IX + Offset
Op Code Address+2
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address+2
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address+2
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer-1
IX + Offset
Op Code Address+ 1
FFFF
IX+Offset
FFFF
IX + Offset
Op Code Address+ 1
Op Code Address+ 1
Op Code Address+2
FFFF
IX + Offset
Op Code Address+3
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset
Op Code Address+2
Op Code Address+ 1
Op Code Address+2
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address+3

1
1

Offset
Restart Address (LSB)
Accumulator Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data

a
1
1
1
1
1
1

1
1

a
a
1
1
1

a
a
1
1
1
1
1

a
1
1
1
1
1
1
1
1
1

I

a

00

1
1
1
1
1
1

Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code

a
1

- Continued-

82

$

HITACHI

-------------------------------------------------HD6303R,HD63A03R,HD63B03R
Table 12 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions

Address Bus

EXTEND
JMP

1

2

3
ADC
AND
CMP
LDA
SBC
STA

ADD
BIT
EOR
ORA
SUB

3
1

TST

2

4

3

4

l

2

STD
STX

3

I
LDD
LDX

I

4
1

2
5

3

4
5
STS

1
I

5

2
3

I

4
5
1
2

JSR

6

ASL
COM
INC
NEG
ROR

ASR
DEC
LSR
ROL

Op Code Address+ 1
Op Code Address+2
Jump Address
Op Code Address+ 1
Op Code Address + 2
Address of Operand
Op Code Address+3

[

1

i

1
1

3
4
5
6
1
2

6

CLR

5

3
4
5
6
1
2
3

4
5

Jump Address
Op Code Address+ 1
Op Code Address+2
Address of Operand
FFFF
Address of Operand
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
Address of Operand
Address of Operand
Op Code Address+3

Next Op Code

!

i

1

ill

Op Code Address+ 1
Op Code Address+2
Destination Address
Op Code Address+3
Op Code Address+ 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
Destination Address
Destination Address+ 1
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
FFFF
Stack Pointer

Stack Po;n..,-1

I Jump
Jump Add,ess IMSBI
Address (LSB)

1- iTdd,ess
of Ope,.nd IMSBI
1
Address of Operand (LSB)
'

1

4
ADDD
CPX
LDS
SUBD

Data Bus

I

I

1
1

I Destination Address (MSB)
I

0
i
!
I

i

I

i
I
I

I
I

--JI

I

I

I
I

Operand Data
Next Op Code

1
1
1
1
1
1
1
1

I

I

I
I

I

I

0
0

I
I

1
1
1
1

I

I

0

I

0

I

1
1
1
1
1

0
1
1
1
1

I

I

Destination Address (LSB)
Accumulator Data
Next Op Code
Address of Operand-(MSS)
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address-(MSS)
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (MSBj
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data

0

00

1

Next Op Code
- Continued -

$

HITACHI

83

Table 12 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions

Address Bus

IMPLIED
ABA
ABX
ASL
ASLD
ASR
CBA
CLC
CLI
CLR
CLV
COM
DEC
DES
DEX
INC
INS
INX
LSR
LSRD
ROL
ROR
NOP
SBA
SEC
SEI
SEV
TAB
TAP
TPA
TBA
TST
TSX
TXS
-- .. -DAA
XGDX

!

Data Bus

Next Op Code

Op Code Address+ 1

I

'[

I
I
i

I

-----

- --

PULA

2

PULB·

I

3
--

-----~--.-.-

PSHA

I,

PSHB

I

I

3

I

1
2

r

4

I
I
i

- --------_._-_ ..

PULX

I

I

4

I

PSHX

i

I
I

I

i

I

I

5

1
2
1
2

3
4
1
2

3
4
1
2

3
4
5
1
2

I

RTS
5

3
4
5
1
2

MUL

3
7

4
5

6
7

84

i
I

Op Code Address+ 1
FFFF
Op Code Address+ 1
FFFF
Stack Pointer+ 1
Op Code Address+ 1
FFFF
Stack Pointer
Op Code Address+ 1
Op Code Address+ 1
FFFF
Stack Pointer+ 1
Stack Pointer + 2
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer-l
Op Code Address+ 1
Op Code Address+ 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Return Address
Op Code Address+ 1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF

$

HITACHI

I
i
I

1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0

0
1
1
1

1
1
1
1
1
1

1
1
1
1

I Next Op Code
Restart Address (LSB)
Next Op Code
Restart Address (LSB)
Data from Stack
Next Op Code
Restart Address (LSB)
Accumulator Data
Next Op Code
Next Op Code
Restart Address (LSB)
Data from Stack (MSB)
Data from Stack (LSB)
Next Op Code
Restart Address (LSB)
Index Register (LSB)
Index Register (MSB)
Next Op Code
Next Op Code
Restart Address (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
- Continued -

Table 12 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions

Address Bus

IMPLIED
WAI

9

1
2
3
4
5
6

7
8
9
RTI

10

1
2
3
4
5
6

7
8
9
SWI

12

10
1
2
3
4
5
6

7
8
9
10
11
12
1
2

SLP

4

I

I

I

Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer-1
Stack Pointer-2
Stack Pointer-3
Stack Pointer-4
Stack Pointer-5
Stack Pointer-6
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer + 1
Stack Pointer+2
Stack Pointer + 3
Stack Pointer+4
Stack Pointer+5
Stack Pointer+6
Return Address
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Vector Address FFFA
Vector Address FFFB
Address of SWI Routine
Op Code Address+ 1
FFFF
FFFF

Sleep

1
3
4

FFFF
Op Code Address+ 1

Data Bus

1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1

Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator. A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address (LSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index Register (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)
Address of SWIRoutine (LSB)
First Op Code of SWI Routine
Next Op Code
Restart Address (LSB)
High Impedance-Non MPX Mode
Address Bus -MPX Mode

1

Restart Address (LSB)
Next Op Code
- Continued -

$

HITACHI

85

HD6303R,HD63A03R,HD63B03R-----------------------Table 12 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions

Address Bus

Data Bus

RELATIVE
BCC
BEQ
BGT
BLE
BLT
BNE
BRA
BVC
BSR

BCS
BGE
BHI
BLS
BMT
BPL
BRN
BVS

1

3

2
3

1
2

5

3
4
5

Op Code Address+ 1
FFFF
J Branch Address······Test= .. 1..
\ Op Code Address + 1.. ·Test="O"

Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer-1
Branch Address

• LOW POWER CONSUMPTION MODE
The HD6303R has two low power consumption modes; sleep
and standby mode .

• SleepMode
On execution of SLP instruction, the MPU is brought to the
sleep mode. In the sleep mode, the CPU sleeps (the CPU clock
becomes inactive), but the contents of the registers in the CPU
are retained. In this mode, the peripherals of CPU will remain
active. So the operations such as transmit and receive of the
SCI data and counter may keep in operation. In this mode,
the power consumption is reduced to about 1/6 the value of a
normal operation.
The escape from this mode can be done by interrupt, RES,
STBY. The RES resets the MPU and the STBY brings it into the
standby mode (This will be mentioned later). When interrupt is
requested to the CPU and accepted, the sleep mode is released,
then the CPU is brought in the operation mode and jumps to
the interrupt routine. When the CPU has masked the interrupt,
after recovering from the sleep mode, the next instruction of
SLP starts to execute. However, in such a case that the timer
interrupt is inhibited on the timer side, the sleep mode cannot
be released due to the absence of the interrupt request to the
CPU.

HD6303R

lSTBY~~
I
) Stack registers
,~)

RAM control

register set

I

I

~

~~i"'~~~~ I
r---;.

time

restart

Figure 21 Standby Mode Timing

86

$

1

1
1

0
0
1

Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Op Code of Subroutine

• Standby Mode
Bringing "STBY "Low", the CPU becomes reset and all
clocks of the HD6303R become inactive. It goes into the
standby mode. This mode remarkably reduces the power consumptions of the HD6303R.
In the standby mode, if the HD6303R is continuously supplied with power, the contents of RAM is retained. The standby
mode should escape by the reset start. The following is the
typical application of this mode.
First, NMI routine stacks the CPU's internal information and
the contents of SP in RAM, disables RAME bit of RAM control
register, sets the standby bit, and then goes into the standby
mode. If the standby bit keeps set on reset start, it means that
the power has been kept during stand-by mode and the contents
of RAM is normally guaranteed. The system recovery may be
possible by returning SP and bringing into the condition before
the standby mode has started. The timing relation for each line
in this application is shown in Figure 21.

~-------iJ\I----~rI-->t

I

Branch Offset
Restart Address (LSB)
First Op Code of Branch Routine
Next Op Code

This sleep mode is available to reduce an average power
consumption in the applications of the HD6303R which may
not be always running.

NMI

my

1
1

HITACHI

• ERROR PROCESSING

When the HD6303R fetches an undefined instruction or
fetches an instruction from unusable memory area, it generates
the highest priority internal interrupt, that may protect from
system upset due to noise or a program error.
• Op-Code Error
Fetching an undefmed op-code, the HD6303R will stack the
CPU register as in the case of a normal interrupt and vector to
the TRAP ($FFEE, $FFEF), that has a second highest priority
(RES is the highest).
• Address Error
When an instruction is fetched from other than a resident
RAM, or an external memory area, the CPU starts the same
interrupt as op-code error. In the case which the instruction is
fetched from external memory area and that area is not usable,
the address error can not be detected.
The address which cause address error are shown in Table

13.
This feature is applicable only to the instruction fetch, not to
normal read/write of data accessing.
Transitions among the active mode, sleep mode, sta.ndby
mode and reset are shown in Figure 22.
Figures 23, 24 show a system configuration.
The system flow chart of HD6303R is shown in Figure 25.

Figure 22

Transitions among Active Mode, Standby Mode,
Sleep Mode, and Reset

Table 13 Address Error
Address Error

$0000 - $001 F

HD6303R MPU

16

Address Bus

Data Bl"

Address Bus

Figure 23 HD6303R MPU Multiplexed Mode

8

Data Bus

Figure 24 HD6303R MPU Non-Multiplexed Mode

~HITACHI

87

STACK
PCL~MSP

PCH -MSP-1
IXL - MSP-2
IXH -MSP-3
ACCA-MSP-4
ACCB-MSP-5
CCR~MSP-6

Figure 25 HD6303R System Flow Chart

88

eHITACHI

• PRECAUTION TO THE BOARD DESIGN OF OSCILLATION CIRCUIT
As shown in Fig. 26, there is a case that the cross talk disturbs the normal oscillation if signal lines are put near the
oscillation circuit. When designing a board, pay attention to
this. Crystal and CL must be put as near the HD6303R as
possible.

• PIN CONDITIONS AT SLEEP AND STANDBY STATE
• Sleep State
The conditions of power supply pins, clock pins, input pins
and E clock pin are the same as those of operation. Refer to
Table 14 for the other pin conditions.
• Standby State
Only power supply pins and "SiB'V are active. As for the
clock pin EXTAL, its input is fixed internally so the MPU is
not influenced by the pin conditions. XT AL is in "1" au tpu t.
All the other pins are in high impedance.

HD6303R

Do not use this kind of print board design.

Figure 26

Precaution to the boad design
of oscillation circuit
Table 14 Pin Condition in Sleep State

~

Non Multiplexed Mode

Multiplexed Mode

I/O Port
Keep the condition just before sleep

I/O Port

Condition

Address Bus (Ao - A,)
Output "1"

I/O Port
Keep the condition just before sleep

Pin

P20 - P24
Ao/Plo A,/PI'
As - AlS
DolAo D7/A,

RIW

Function
Condition
Function

-

---

-------

---

---

Function

Address Bus (As -A Is )

Condition

Output"1 "

Address Bus (As -A 1S )

Function

E: Address Bus (Ao-A,). E: Data Bus

Condition

Data Bus (Do -0,)
High Impedance

Function

R/W Signal

R/W Signal

Condition

Output "1"

E: Output "1", E: High Impedance

-

-

AS

-

Output AS

Table 15 Pin Condition during RESET

~

Non-Multiplexed Mode

Multiplexed Mode

Pin

P20 - P24

High Impedance

.

AO/PIO - A,/PI7

High Impedance

.

As - Ais

High Impedance

..

Do/Ao - D7/A,

High Impedance

R/W

"1" Output

..

E: "1" Output

..

AS

E : "0" Output

$

HITACHI

E : "1" Output
E : High Impedance

89

HD6303R,HD63A03R,HD63B03R-----------------------------------------------•

DIFFERENCE BETWEEN HD6303 AND HD6303R
The HD6303R is an upgraded version of the HD6303. The
difference between HD6303 and HD6303R is shown in Table
16.

Table 16 Difference between HD6303 and HD6303R
Item
Operating
Mode

HD6303
Mode 2: Not defined

The electrical character·
Electrical
istics of 2MHz version
Character·
(B version) are not spec·
istics
ified.
Timer

90

~HITACHI

Has problem in output
compare function.
(Can be avoided by software.)

HD6303R
Mode 2: Multiplexed
Mode
(Equivalent to Mode 4)
Some characteristics
are improved.
The 2MHz version is
guaranteed.
The problem is solved.

HD6303X,HD63A03X,---HD63B03X
CMOS MPU (Micro Processing Unit)
-PRELIMINARYThe HD6303X is a CMOS 8-bit microprocessing unit (MPU)
which includes a CPU compatible with the HD6301 VI, 192
bytes of RAM, 24 parallel I/O pins, a Serial Communication
Interface (SCI) and two timers on chip.

HD6303XP, HD63A03XP,
HD63B03XP

•
•
•

FEATURES
Instruction Set Compatible with the HD6301V1
Abundant On-chip Functions
192 Bytes of RAM
24 Parallel I/O Ports
16-Bit Programmable Timer
8-Bit Reloadable Timer
Serial Communication Interface
Memory Ready
Halt
Error-Detection (Address Trap, Op Code Trap)
• Interrupts ... 3 External, 7 Internal
• Up to 65k Words Address Space
• Low Power Dissipation Mode
Sleep
Standby
• Wide Range of Operation
Vee = 3 - 6V (f =0.1 - 0,5MHz).

Vee'" 5V±10%

(

XTAL ~
EXTAL 3

MP.

0

D.
10,
0,
0,
D.
0,
2 D.

P u ;;
P2l 12

S

Pu 1
Pu 1

51 D1

A.
A,
A,
A,

P26 1

PSI

1

'

A.
A,
A,
A,

P"
P,.. 21

P"
PSt 2

2 VII

1 A,

4

P"

p,.

s

A,
3

P'I 2

A ..

P" 1
P"
P"
P"
p.. 31

~ An

i!l

~ Vee

P"

0

OR

*

Pn

-'

~ ~ wl~I~I~ ~I~;a

BA

P" ~
P" ~

1

HD6303XF, HD63A03XF, HD63B03XF

1 R/W

STBY
NMI ~

Pso

•

1m
WR

~:~ ~

1

(FP-80)

E

4

P21

HD6303XF, HD63A03XF,
HD63B03XF

f = 0.5 -1.0MHz; HD6303X )
f = 0.5 -1.5MHz; HD63A03X
f =0.5 - 2.0MHz; HD63B03X

• PIN ARRANGEMENT
• HD6303XP, HD63A03XP, HD63B03XP
VIS 1

(DP-64S)

~ Au

¥. A"
3

Au

~

A"

NC

24

(Top View)

(Top View)

~HITACHI

91

• BLOCK DIAGRAM

vc c - - - -

w

Vss
Vss

oa:

NO

P2o(Tin)

Il.

0

I ~ a:

P2,(Tout1)

.... 0
00

P22(SCLK)

~

N

P23(Rx)

r01III II 11 Ia:

. .J . .J

~
X

X

w

alolaa:l~

CPU

L.- AD

!;a:a:~:I:

~

;:..

0
Il.

P24(Tx)
P2s(Tout2)

V
t\

P2s(Tout3)
P27(TcLK)

II

JOa:~i?...J1Il
'~I!; «

~

R/W
LlA

I!

SA

\J

...-L--

f----

....

£

~

"~

'---

Qj

'\

"

V

I

U
CJ)

::::J

'"::::J

f----

CO

f---

::l

£ ff -- -- --

III
."

::::J

iii

~

CO

0

I!

'"::::J

V

E

I\.

t=

CO

"
(J)

::l

r---

III

Pso(i'R'Q,,)

'"J

y

(J)
(J)

'"'"
-0
"0
Q)

\\\\\\\\\\I\\\\\\\\\\\.\\\'~-----""'O--O-O-;"'~r)-f- - - - PCB PC 15

PCO PC7

Forst

Instruction

Figure 11 Reset Timing
• FUNCTIONAL PIN DESCRIPTION
• Vee, Vss
Vcc and Vss provide power to the MPU with 5V± I 0% supply. In the case of low speed operation (fmax = 500kHz), the
MPU can operate with three through six volts. Two Vss pins
should be tied to ground.
• XTAl,EXTAl
These two pins interface with an AT-cut parallel resonant
crystal. Divide-by-four circuit is on chip, so if 4MHz crystal
oscillator is used, the system clock is 1MHz for example.
AT Cut Parallel Resonant Crystal Oscillator
Co=7pF max
Rs=60Q max
XTAL~--~----~

CJ

Cll =CL2
=

EXTALI---.........,

• STBY
This pin makes the MPU standby mode. In "Low" level, the
oscillation stops and the internal clock is stabilized to make
reset condition. To retain the contents of RAM at standby,
"0" should be written into RAM enable bit (RAME). RAME
is the bit 6 of the RAM/port 5 control register at $0014. RAM
is disabled by this operation and its contents is sustained.
Refer to "LOW POWER DISSIPATION MODE" for the
standby mode.
•

Reset (RES)
This pin is used to reset the MPU from power OFF state
and to provide a startup procedure. During power-on, RES
pin must be held "Low" level for at least 20ms.
The CPU registers (accumulator, index register, stack pointer,
condition code register except for interrupt mask bit), RAM
and the data register of a port are not initialized during reset,
so their contents are unknown in this procedure.
To reset the MPU during operation, RES should be held
"Low" for at least 3 system-clock cycles. At the 3rd cycle
during "Low" level, all the address buses become "High". When
RES remains "Low", the address buses keep "High". If RES
becomes "High", the MPU starts the next operation.
(I) Latch the value of the mode program pins;MPo and MP,.

10pF - 22pF±20%
(3.2 - SI\,:Hz)

-ICL2J-CLI

(a) Crystal Interface

XTAL~ N.C.
EXTAL

EXT AL pin is drivable with the external clock of 45 to
50% duty. and one fourth frequency of the external clock
is produced in the LSI. The external clock frequency should
be less than four times of the maximum operable frequency.
When using the external clock, XT AL pin should be open.
Fig. 12 shows examples of connection circuit. The crystal and
CL I. CL2 should be mounted as close as possible to XT AL
and EXT AL pins. Any line must not cross the line between the
crystal oscillator and XTAL, EXTAL.

External Clock

(b) External Clock
Figure 12 Connection Circuit

$

HITACHI

99

HD6303X,HD63A03X,HD63B03X--------------------------------------------_____
(2) Initialize each internal register (Refer to Table 3).
(3) Set the interrupt mask bit. For the CPU to recognize the
maskable interrupts IRQ. , IRQ2 and IRQ3, this bit should
be cleared in advance.
(4) Put the contents (= start address) of the last two addresses
($FFFE, $FFFF) into the program counter and start the
program from this address. (Refer to Table 1).
*The MPU is usable to accept a reset input until the clock
becomes normal oscillation after power on (max. 20ms). During
this transient time, the MPU and I/O pins are undefined. Please
be aware of this for system designing.
•

Enable (E)

This pin provides a TTL-compatible system clock to external
circuits. Its frequency is one fourth that of the crystal oscillator
or external clock. This pin can drive one TTL load and 90pF
capacitance.
•

Non·Maskable Interrupt (NMJ)

When the falling edge of the input signal is detected at this
pin, the CPU begins non-maskable interrupt sequence internally.
As well as the IRQ mentioned below, the instruction being
executed at NMI signal detection will proceed to its completion.
The interrupt mask bit of the condition code register doesn't
affect non-maskable interrupt at all.
When starting the acknowledge to the NMI, the contents of
the program counter, index register, accumulators and condition
code register will be saved onto the stack. Upon completion

of this sequence, a vector is fetched from $FFFC and $FFFD
to transfer their contents into the program counter and branch
to the non·maskable interrupt service routine. After re;et start.
the stack pointer should be initialized on an appropreate memory area and then the falling edge be input to NMT pin.
•

Interrupt Request (IRQ •• IRQ2)

These are level-sensitive pins which request an internal
interrupt sequence to the CPU. At interrupt request, the CPU
will complete the current instruction before its request acknowledgement. Unless the interrupt mask in the condition code
register is set, the CPU starts an interrupt sequence; if set, the
interrupt request will be ignored. When the sequence starts, the
contents of the program counter, index register, accumulators
and condition code register will be saved onto the stack, then
the CPU sets the interrupt mask bit and will not acknowledge
the maskable request. During the last cycle, the CPU fetches
vectors depicted in Table I and transfers their contents to the
program counter and branches to the service routine.
The CPU uses the external interrupt pins, IRQ. and IRQ2
also as port pins P so and p s ., so it provides an enable bit to
Bit 0 and I of the RAM port 5 control register at $0014. Refer
to "RAM/PORT 5 CONTROL REGISTER" for the details.
When one of the internal interrupts, ICI, OCI, TOI, CMI or
SIO is generated, the CPU produces internal interrupt Signal
(IRQ3)' IRQ3 functions just the same as IRQ. or IRQ2 except
for its vector address. Fig. 13 shows the block diagram of the
interrupt circuit.

Table 1 Interrupt Vector Memory Map
Priority
Highest

Lowest

100

Vector

Interrupt

MSB

LSB

FFFE
FFEE
FFFC

FFFF

RES

FFEF
FFFD

FFFA
FFF8
FFF6
FFF4

FFFB
FFF9
FFF7
FFF5
FFF3
FFED
FFEB
FFFl

TRAP
NMI
SWI (Software Interrupt)

FFF2
FFEC
FFEA
FFFO

$

IRQ.
ICI (Timer 1 Input Capture)
OCI (Timer 1 Output Compare 1 • 2)
TO I (Timer 1 Overflow)
CMI (Timer 2 Counter Match)
IRQ 2
SIO (RDRF+ORFE+TDRE)

HITACHI

------------------------HD6303X,HD63A03X,HD63B03X
Each Register's Interrupt
Enable Flag
"1"; Enable, "0"; Disable

--

IRQ,
IRQ2

....

ICF

--

ICI

--

OCF1

Condition
Code
Register
I-MASK
"O";Enable
"1";Disable

V"

~

- 0 - t-'

----

OCF2
TOF
IRQJ
CMF
RDRF

-0-

ORFE

TOI

~

CMI

~

Interrupt
Request
Signal

~

- 0 - t-'

TORE

-J

Edge
Detective
Circuit

Sleep
Cancel
Signal

I

TRAP
Address Error
Op Code Error
Detective Circuit

SWI

Figure 13 Interrupt Circuit Block Diagram

•

Mode Program (MP o , MP I)
To op~rate MPLI. MP o pin should he wnnected to "High"
level and MP , should h~ cOllllect~d to "Low" level (refer to
rj~. 15).

•

Read/Write (R/W)
This signal. usually be in read state ("High"), shows whether
the MPU is in read ("High") or write ("Low") state to the
peripheral or memory devices. This can drive one TTL load
and 30pF capacitance.

•

RD, WR
These signals show active low outputs when the CPU is
reading/writing to the peripherals or memories. This enables
the CPU easy to access the peripheral LSI with RD and WR
input pins. These pins can drive one TTL load and 30pF capacitance.

•

Load Instruction Register (UR)
This signal shows the instruction opecode being on data
bus (active low). This pin can drive one TTL load and 30pF
capacitance.

•

Memory Ready (MR; P S2 )
This is the input control signal which stretches the system
clock's "High" period to access low-speed memories. During
this signal being in "High", the system clock operates in normal
sequence. But this signal in "Low", the "High" period of the
system clock will be stretched depending on its "Low" level
duration in integral multiples of the cycle time. This allows the
CPU to interface with low-speed memories (see Fig. 2). Up to

9 Jis can be stretched.
During internal address space access or nonvalid memory
access, MR is prohibited internally to prevent decrease of operation speed. Even in the halt state, MR can also stretch "High"
period of system clock to allow peripheral devices to access
low-speed memories. As this signal is used also as P S2 , an enable
bit is provided at bit 2 of the RAM/port 5 control register at
$0014. Refer to "RAM/PORT 5 CONTROL REGISTER" for
more details.

• Halt (HALT; PS3)
This is an input control Signal to stop instruction execution
and to release buses free, When this signal switches to "Low",
the CPU stops to enter into the halt state after having executed
the present instruction. When entering into the halt state, it
makes BA (P 74 ) "High" and also an address bus, data bus, RD,
WR, R/W in high impedance. When an interrupt is generated
in the halt state, the CPU uses the interrupt handler after the
halt is cancelled. When halted during the sleep state, the CPU
keeps the sleep state, while BA is "High" and releases the buses.
Then the CPU returns to the previous sleep state when the
HALT signal becomes "High". The same thing can be said when
the CPU is in the interrupt wait state after having executed the
WAI instruction.
• Bus Available (BA)
This is an output control signal which is normally "Low"
but "High" when the CPU accepts HALT and releases the buses.
The HD6800 and HD6802 make BA "High" and release the
buses at WAI execution, while the HD6303X doesn't make

~HITACHI

101

HD6303X,HD63A03X,HD63B03X------------------------------------------------BA "High" under the same condition. But if the HALT becomes
"Low" when the CPU is in the interrupt wait state after having
executed the WAI, the CPU makes BA "High" and releases the
buses. And when the HALT becomes "High", the CPU returns
to the interrupt wait state.
•

PORT

The HD6303X provides three I/O ports. Table 2 gives the
address of ports and the data direction register and Fig. 14
the block diagrams of each port.

(DDR) of port 2 is responsible for I/O state. It provides two
bits; bit 0 decides the I/O direction of P 20 and bit I the I/O
direction of P 21 to P 27 ("0" for input, "I" for output).
Port 2 is also used as an I/O pin for the timers and the
SCI. When used as an I/O pin for the timers and the SCI, port
2 except P 20 automatically becomes an input or an output
depending on their functions regardless of the data direction
register's value.
Port 2 Data Direction Register

Table 2 Port and Data Direction Register Address

6543210

Port

Port Address

Data Direction Register

Port 2

$0003
$0015
$0017

$0001
$0016

Port 5
Port 6

• Port 2
An 8-bit input/output port. The data direction register

A reset clears the DDR of port 2 and configures port 2 as an
input port. This port can drive one TTL and 30pF. In addition,
it can produce ImA current when Vout = 1.5V to drive directly
the base of Darlington transistors.

Port Write Signal

Data Bus

Timer 1, 2,:--t-_ _ _..J
SCI Output

Tri-state
Control

Timer 1,2,_--------<
SCI Input

Port 2
Port Read Signal

...L

Data Bus ---~~-<

Port 5
Figure 14 Port Block Diagram

• Port 5
An 8-bit port for input only. The lower four bits are also
usable as input pins for interrupt, MR and HALT.

•

• Port 6
An 8-bit I/O port. This port provides an 8-bit DDR corresponding to each bit and can specify input or output by the
bit (''0'' for input, "1" for output). This port can drive one
TTL load and 30pF. A reset clears the DDR of port 6. In
addition, it can produce ImA current when Vout = I.SV to
drive directly the base of Darlington transistors.

•

Ao"'Als

These pins are address bus and can drive one TTL load and
90pF capacitance respectively.
RAM/PORT 5 CONTROL REGISTER

The control register located at $0014 controls on-chip
RAM and port S.
RAM/Port 5 Control Register
7

6

543

2

1

0

• BUS
•

0 0 "'0 7
These pins are data bus and can drive one TTL load and
90pF capacitance respectively.

BitO, Bit 1 IRO I , IR0 2 Enable Bit (IRO I E, IR0 2 E)
When using Pso and PSI as interrupt pins, write "I" in

these bits. When "0", the CPU doesn't accept an external

102

~HITACHI

interrupt or a sleep cancellation by the external interrupt.
These bits become "0" during reset.
Bit 2 Memory Ready Enable Bit (MRE)
When uSoing P S2 as an input for Memory Ready signal, write
"1" in this bit. When "0", the memory ready function is prohihited. This hit hecomes "1" during reset.

AD
WR

CJ

R/iii
CiA
BA

Bit 3 Halt Enable bit (HL TE)
When using P53 as an input for Halt signal, write "1" in this
hi t. When "0", the hal t function is prohibi ted. This bit becomes
"1" during reset.

Port 2

8 liD Lines

Timer 1.2
SCI

8 Data Bus

Port 5

Bit 4, Bit 5 Not Used.

8~~~

Bit 7 Standby Power Bit (STBY PWR)
When Vee is not provided in standby mode, this bit is
cleared. This is a flag for both read/write by software. If this bit
is set before standby mode, and remains set even after returning
from standby mode, Vee voltage is provided during standby
moue and the on·chip RAM data is valid.

16 Address
Bus

MR. HALT
Port 6

Bit 6 RAM Enable (RAME)
On-chip RAM can be disabled by this control bit. The
M:>IJ Reset sets "I" at this bit and enables on-chip RAM
available. This bit can be written "1" or "0" by software.
When RAM is in disable condition (= logic "0"), on-chip RAM
is ihvalid and the CPU can read data from external memory.
This bit should be "0" at the beginning of standby mode to
protect on·chip RAM data.

8 liD Lines

Figure 15 Operation Mode

•

MEMORY MAP
The MPU can address up to 65k bytes. Fig. 16 gives memory
map of HD6303X. 32 internal registers use addresses from "00"
as shown in Table 3.

Table 3 Internal Register
Registers
-

Address
00
02*

Port 2 Data Direction Register
-

03

Port 2

01

Initialize at RESET

W

$FC

RIW

04*

-

05

-

06*

-

-

-

07*

R/W***
-

-

Undefined

$00

08

Timer Control/Status Register 1

R/W

09

Free Running Counter ("High")

R/W

$00

OA

Free Running Counter ("Low")

R/W

$00

OB

Output Compare Register 1 ("High")

RIW

$FF

OC

Output Compare Register 1 ("Low")

R/W

$FF

OD

Input Capture Register ("High")

R

$00

OE

Input Capture Register ("Low")

R

$00

OF

Timer Control/Status Register 2

R/W

$10

10

Rate, Mode Control Register

R/W

$00

11

Tx/Rx Control Status Register

RIW

$20

12

Receive Data Register

R

$00

13

Transmit Data Register

W

$00

14

RAM/Port 5 Control Register

15

Port 5

R/W
R

16

Port 6 Data Direction Register

W

$7C or $FC

$00
(continued)

~HITACHI

103

HD6303X,HD63A03X,HD63B03X------------------------------------------------Table 3 Internal Register
Registers

Address
17

Port 6

-

18*

R/W***

Initialize at RESET

R/W

-

Undefined
-

19

Output Compare Register 2 ("High")

R/W

$FF

1A

Output Compare Register 2 ("Low")

R/W

$FF

18

Timer Control/Status Register 3

R/W

$20

1C

Time Constant Register

W

$FF

1D

Timer 2 Up Counter

R/W

$00

-

1E
1F**

-

Test Register

-

* External Address.
** Test Register. Do not access to this· register.

*** R

: Read Only Register
W : Write Only Register
R/W: Read/Write Register

and incremented by system clock. The counter value is readable
by software without affecting the counter. The counter is
cleared by reset.
When writing to the MSB byte (509). the CPU writes the
preset value ($FFF8) into the counter (address S09. SOA)
regardless of the write data value. But when writing to the
LSB byte (SOA) after MSB byte writing. the CPU write not
only LSB byte data into lower 8 bit. but also MSB byte data
into higher 8 bit of the FRC.
The counter will be as follows when the CPU writes to it
by double store instructions (STD. STX etc.).

HD6303X
Expanded Mode

$001F~~::-..:;.,,::~

Internal*
Registers
External

m.,.,.."..,..,..,.~ ~ ~;:~ry
Internal
RAM

$OOFF F"~"""~h'

$09 Write
External
Memory
Space

Counter value

$OA Write

$FFF8

$5AF3

In the case of the CPU write ($5AF3) to the FRC

Figure 17 Counter Write Timing
$FFFF 1..-_ _ _..1,

•
• Excludes the following addresses
which may be used externally:

$02, $04, $06, $07, $18.

Figure 16 HD6303X Memory Map
•

TIMER 1

The HD6303X provides a 16-bit programmable timer which
can measure an input waveform and generate two independent
output waveforms. The pulse widths of both input/output
waveforms vary from microseconds to seconds.
Timer 1 is configurated as follows (refer to Fig. 18).
• Control/Status Register 1 (8 bit)
• Control/Status Register 2 (7 bit)
• Free Running Counter ( 16 bit)
Output Compare Register 1 (16 bit)
• Output Compare Register 2 (16 bit)
• Input Capture Register (16 bit)

The output compare register is a 16·bit read/write register
which can control an output waveform. It is always compared
with the FRC.
When data matches, output compare flag (OCF) in the timer
control/status register (TCSR) is set. If an output enable bit
(OE) in the TCSR2 is "I", an output level bit (OLVL) in the
TCSR will be output to bit I (Tout 1) and bit 5 (Tout 2) of
port 2. To control the output level again by the next compare, a
change is necessary for the OCR and OLVL. The OCR is set to
$FFFF at reset. The compare function is inhibited for a cycle
just after a write to the OCR or to the upper byte of the
FRC. This is tQ set the 16·bit value valid in the register for
compare. In addition, it is because $FFF8 is set at the next
cycle of the CPU's MSB byte write to the FRC.
* For data write to the FRC or the OCR, 2·byte transfer
instruction (such as STX etc.) should be used.
•

•

Free-Running Counter (FRC) ($0009 : OOOA)

The key timer element is a 16·bit free·running counter driven

104

$

Out;lut Compare Register (OCR)
($0008, $OOOC; OCR1) ($0019, $001A; OCR2)

Input Capture Register (fCR) ($0000: OOOE)

The input capture register is a 16·bit read only register which
stores the FRC's value when external input Signal transition

HITACHI

~~~~~~~~~~~~~~~~~~~~~~~~HD6303X,HD63A03X,HD63B03X

generates an input capture pulse. Such transition is defined by
input edge bit (IEDG) in the TCSRI.
In order to input the external input signal to the edge
detecter. a bit of the DDR corresponding to bit 0 of port 2
should be cleared ("0"). When an input capture pulse occures
by input transition at the next cycle of CPU's high-byte read of
the ICR. the input capture pulse will be delayed by one cycle.
In order to ensure the input capture operation, a CPU read of
the ICR needs 2-byte transfer instruction. The input pulse width
should be at least 2 system cycles. This register is cleared
(SOOOO) during reset.

• Timer Control/Status Register 1 (TCSR1) ($0008)
The timer control/status register 1 is an 8-bit register. All bits
are readable and the lower 5 bits are also writable. The upper 3
hits are read only which indicate the following timer status.
Bit 5 The counter value reached to $0000 as a result of
counting-up (TOF).
Bit 6 A match has occured between the FCR and the OCR 1
(OCFI).
Bit 7 Defined transition of the timer input signal causes the
counter to transfer its data to the ICR (ICF).
The followings are each bit descriptions.

the OCRI ($OOOB or $OOOC) following the TCSRI or
TCSR2 read.
Bit 7

ICF

Input Capture Flag

This read only bit is set when an input signal of
port 2, bit 0 makes a transition as defined by IEDG and
the FRC is transferred to the ICR. Cleared when reading
the MSB byte ($OOOOD) of the ICR following the
TCSRI or TCSR2 read.

• Timer Control/Status Register 2 (TCSR2) ($OOOF)
The timer control/status register 2 is a 7 -bit register. All bits
are readable and the lower 4 bits are also writable. But the
upper 3 bits are read-only which indicate the following timer
status.
Bit 5 A match has occured between the FRC and the OCR2
(OCF2).
Bit 6 The same status flag as the OCFI flag of the TCSRI,
bit 6.
Bit 7 The same status flag as the ICF flag of the TCSRI , bit 7.
The followings are each bit descriptions.
Timer Control/Status Register 2
76543210

Timer Control/Status Register 1
ICF IOCF11 OCF21 -

Bit 0
Bit 0

OLVL 1

Bit 1

Bit 2

IEDG

Bit 1

This bit determines which rising edge or falling of
input signal of port 2, bit 0 will trigger data transfer
from the counter to the ICR. For this function, the
DDR corresponding to port 2, bit 0 should be cleared
beforehand.
IEDG=O. triggered on a falling edge
("High" to "Low")
IEDG= I. triggered on a rising edge
("Low" to "High")

Bit 2

ETOI

Bit 3

EOCll

Enable Output Compare Interrupt 1

When this bit is set. an internal interrupt (IRQ3) by
oCt I interrupt is enabled. When cleared, the interrupt
is inhihited.
Bit 4

EICI

Bit 5

TOF

Timer Overflow Flag

This read only bit is set when the counter increments from $FFFF by 1. Cleared when the counter's
MSB byte ($0009) is ready by the CPU following the
TCSRI read.
Bit 6

OCF 1

Output Compare Flag 1

This read only bit is set when a match occurs between the OCRI and the FRC. Cleared by writing to

OL VL2

Output Level 2

EOCI2

transferred to port 2, bit 5 when a match
between the counter and the OCR2. If
bit 5 of the TCSR2, is set to "1", OLVL2
port 2, bit 5.

Enable Output Compare Interrupt 2

When this bit is set, an internal interrupt (lRQ3) by
OCI2 interrupt is enabled. When cleared, the interrupt
is inhibited.
Bit 4
Bit 5

Not Used
OCF2 Output Compare Flag 2

This read-only bit is set when a match has occurred
between the counter and the OCR2. Cleared when
writing to the OCR2 ($0019 or $OOIA) following the
TCSR2 read.

Enable Input Capture Interrupt

When this bit is set. an internal interrupt (IRQ3) by
ICt interrupt is enabled. When cleared. the interrupt is
inhibited.

Output Enable 2

OLVL2 is
has occurred
OE2, namely
will appear at

When this bit is set. an internal interrupt (IRQ3) by
Tal interrupt is enabled. When cleared, the interrupt is
inhibited.
Bit 3

OE2

This bit enables the OLVL2 to appear at port 2, bit
5 when a match has occurred between the counter and
the output compare register 2. When this bit cleared,
port 2, bit 5 will be I/O port. When set, it will be an
output of OLVL2 automatically.

Input Edge

Enable Timer Overflow Interrupt

Output Enable 1

This bit enables the OLVLl to appear at port 2, bit
1 when a match has occurred between the counter and
the output compare register 1. When this bit cleared, bit
1 of port 2 will be I/O port. When set, it will be an
output ofOLVLl automatically.

Output Levell

OLVLI is transferred to port 2, bit 1 when a match
occurs between the counter and the OCRI. If OEI,
name Iy. bit 0 of the TCSR2. is set to "1". OLVLl will
appear at hit I of port 2.

OEl

IEOCI2~LVL21 OE21 O~ $OOOF

Bit 6
Bit 7

OCFl Output Compare Flag 1
ICF Input Capture Flag

OCFI and ICF addresses are partially decoded.
CPU read of the TCSRI/TCSR2 makes it possible to
read OCFI and ICF into bit 6 and bit 7.
Both the TCSRI and TCSR2 will be cleared during reset.
(Note) If OEI or OE2 is set to "1" before the first output
compare match occurs after reset restart, bit I or bit 5
of port 2 will produce "0" respectively.

~HITACHI

105

Figure 18 Timer 1 Block Diagram

(Note) Because the set condition of ICF precedes its reset
condition, ICF is not cleared when the set condition
and the reset condition occur simultaneously. The
same phenomenon applies to OCF 1, OCF2 or TOF
respectively.
•

TIMER 2

In addition to the timer 1, the HD6303X provides an 8-bit
reloadable timer, which is capable of counting the external
event. This timer 2 contains a timer output, so the MPU can
generate three independent waveforms (refer to Fig. 19).
The timer 2 is configured as follows:
Control/Status Register 3 (7 bit)
8-bit Up Counter
Time Constant Register (8 bit)
•

•

Time Constant Register (TCONR) ($001C)

The time constant register is an 8-bit write only register. It
is always compared with the counter.
When a match has occurred, counter match flag (eMF) of
the timer control status register 3 (TCSR3) is set and the value
selected by TOSO and TOSl of the TCSR3 will appear at port 2,
bit 6. When CMF is set, the counter wi\l be cleared simultaneously and then start counting from $00. This enables regular
interrupts and waveform outputs without any software support.
The TCONR is set to "$FF" during reset.
•

Timer Control/Status Register 3 (TCSR3) ($001 B)

The timer control/status register 3 is a 7-bit register. All bits
are readable and 6 bits except for CMF can be written.
The followings are each pin descriptions.

Timer 2 Up Counter (T2CNT) ($0010)

Timer Control/Status Register 3

This is an 8-bit up counter which operates with the clock
decided by CKSO and CKSl of the TCSR3. The counter is
always readable without affecting itself. In addition, any value
can be written to the counter by software even during counting.
The counter is cleared when a match occurs between the
counter and the TCONR or during reset.
If a write operation is made by software to the counter at the
cycle of counter clear, it does not reset the counter but put the
write data to the counter.

106

7

654

3

2

1

0

/ CMF/ECMII - / T2E /TOSlITOsoICKS1/CKsol $0018

~HITACHI

------------------------HD6303X,HD63A03X,HD63B03X

. - - - - - Timer1 FRC

....----1-- Port 2
Bit 7

t-+--I-------- Port 2
Bit 6

Figure 19
Bit 0
Bit 1

CKSO
CKS1

Timer 2 Block Diagram
Table 5 Timer 2 Output Select

Input Clock Select 0
Input Clock Select 1

Input clock to the counter is selected as shown in
Table 4 depending on these two bits. When an external
clock is selected, bit 7 of port 2 will be a clock input
automatically. Timer 2 detects the rising edge of the
external clock and increments the counter. The external
clock is countable up to half the frequency of the
system clock.
Table 4 Input Clock Select
CKS1

CKSO

0
0

0

Input Clock to the Counter

1

E clock/8*

1

0

E clock/128*

1

1

External clock

E clock

• These clocks come from the FRC of the timer 1. If one of these clocks
is selected as an input clock to the up counter, the CPU should not
write to the F RC of the timer 1.

Bit 2
Bit 3

TOSO
TOSl

TOSl

TOSO

0

0

0

1

Toggle Output*

1

0

Output "0"

1

1

Output "1"

* When a match occurs between the counter and the TCONR, timer 2
output level is reversed. This leads to production of a square wave with
50% duty to the external without any software support.

Bit 4

When a match occurs between the counter and the
TCONR timer 2 outputs shown in Table 5 will appear at
port 2, bit 6 depending on these two bits. When both
TOSO and TOSI are "0", bit 6 of port 2 will be an I/O
port.

T2E

Timer 2 Enable Bit

When this bit is cleared, a clock input to the up
counter is prohibited and the up counter stops. When set
to "I", a clock selected by CKS 1 and CKSO (Table 4)
is input to the up counter.
(Note) P26 produces "0" when T2E bit cleared and timer 2 set
in ontput enable condition by TOS} or TOSO. It also
produces "0" when T2E bit set "1" and timer 2 set in
output enable condition before the first counter match
occurs.
Bit 5
Bit 6

Timer Output Select 0
Timer Output Select 1

Timer Output
Timer Output Inhibited

Not Used
ECMI Enable Counter Match Interrupt

When this bit is set, an internal interrupt (IRQ3) by
CMI is enabled. When cleared, the interrupt is inhibited.
Bit 7

CMF

Counter Match Flag

This read only bit is set when a match occurs between
the up counter and the TCONR. Cleared by a software
write (unable to write "1" by software).
Each bit of the TCSR3 is cleared during reset.

~HITACHI

107

HD6303X,HD63A03X,HD63B03X------------------------------------------------•

SERIAL COMMUNICATION INTERFACE (SCI)

The HD6303X SCI contains two operation modes; one is an
asynchronous mode by the NRZ format and the other is a
clocked synchronous mode which transfer data synchronizing
with the serial clock.
The serial interface is configured as follows:
• Control/Status Register (TRCSR)
• Rate/Mode Control Register (RMCR)
• Receive Data Register (RDR)
• Receive Data Shift Register (RDSR)
• Transmit Data Register (TDR)
• Transmit Data Shift Register (TDSR)
The serial I/O hardware requires an initialization by software
for operation. The procedure is usually as follows:
1) Write a desirable operation mode into each corresponding control bit of the RMCR.
2) Write a desirable operation mode into each corresponding control bit of the TRCSR.
When using bit 3 and 4 of port 2 for serial ]/0 only, there is
no problem even if TE and RE bit are set. But when setting the
baud rate and operation mode, TE and RE should be "0". When
clearing TE and RE bit and setting them again, more than 1 bit
cycle of the current baud rate is necessary. If set in less than 1
bit cycle, there may be a case that the internal transmit/receive
initialization fails.
•

Asynchronous Mode

An asynchronous mode contains the following two data
formats:
1 Start Bit + 8 Bit Data + 1 Stop Bit
1 Start Bit + 9 Bit Data + 1 Stop Bit
In addition, if the 9th bit is set to "1" when making 9
bit data format, the format of
1 Start bit + 8 Bit Data + 2 Stop Bit
is also transferred.
Data transmission is enabled by setting TE bit of the TRCSR,
then port 2, bit 4 will become a serial output independently of
the corresponding DDR.
For data transmit, both the RMCR and TRCSR should be
set under the desirable operating conditions. When TE bit is
set during this process, 10 bit preamble will be sent in 8-bit data
format and 11 bit in 9-bit data format. When the preamble is
produced, the internal synchronization will become stable and
the transmitter is ready to act.
The conditions at this stage are as follows.
1) If the TDR is empty (TDRE=I), consecutive l's are
produced to indicate the idle state.
2) If the TDR contains data (TDRE=O), data is sent to the
transmit data shift register and data transmit starts.
During data transmit, a start bit of "0" is transmitted first.
Then 8-bit or 9·bit data (starts from bit 0) and a stop bit of "1"

108

are transmitted .
When the TDR is "empty", hardware sets TDRE flag bit. If
the CPU doesn't respond to the flag in proper timing (the TDRE
is in set condition till the next normal data transfer starts from
the transmit data), "1" is transferred instead of the start bit "0"
and continues to be transferred till data is provided to the data
register. While the TDRE is "1", "0" is not transferred.
Data receive is possible by setting RE bit. This makes port 2,
bit 3 be a serial input. The operation mode of data receive is
decided by the contents of the TRCSR and RMCR. The first
"0" (space) synchronizes the receive bit flow. Each bit of the
following data will be strobed in the middle. If a stop bit is not
"I", a framing error assumed and ORFE is set
When a framing error occurs, receive data is transferred to
the receive data register and the CPU can read error-generating
data. This makes it possible to detect a line break.
]f the stop bit is "I", data is transferred to the receive data
register and an interrupt flag RDRF is set. If RDRF is still
set when receiving the stop bit of the next data, ORFE is set to
indicate overrun generation.
When the CPU read the receive data register as a response to
RDRF flag or ORFE flag after having read TRCS, RDRF or
ORFE is cleared.
(Note) Clock Source in Asynchronous Mode
When using an internal clock for serial ]/0, the followings should be kept in mind.
Set CC 1 and CCO to "I" and "0" respectively.
A clock is generated regardless of the value of TE,
RE.
Maximum clock rate is E.;-16.
Output clock rate is the same as bit rate.
When using an external clock for serial I/O, the follow·
ings should be kept in mind.
Set
and CCO in the RMCR to "I" and" 1" respectively.
The external clock frequency should be set 16 times
of the applied baud rate.
• Maximum clock frequency is that of the system
clock.

cn

•

Clocked Synchronous Mode

In the clocked synchronous mode, data transmit is
synchronized with the clock pulse. The HD6303X SCI
provides functionally independent transmitter and receiver
which makes full duplex operation possible in the asynchronous
mode. But in the clocked synchronous mode an SCI clock I/O
pin is only P22 , so the simultaneous receive and transmit
operation is not available. In this mode, TE and RE should
not be in set condition ("1 ") simultaneously. Fig. 21 gives a
synchronous clock and a data format in the clocked synchronous mode.

~HITACHI

------------------------HD6303X,HD63A03X,HD63B03X

HD6303X Internal Data Bus

Tlmerl FAC.
Tlmer2
Up Counter

Figure 20 Serial Communication Interface Block Diagram

Data transmit is realized by setting TE bit in the TRCSR.
Port 2, bit 4 becomes an output unconditionally independent
of the value of the corresponding DDR.
Both the RMCR and TRCSR should be set in the desirable
operating condition for data transmit.
When an external clock input is selected, data transmit is

 (IMM) -+ (M)
Executes "EOR" operation to immediate data and the
memory contents and stores its result in the memory.

116

0

Executes "AND" operation to immediate data and
changes the relative flag of the condition code register.

~HITACHI

Goes. to the sleep mode. Refer to "LOW POWER DISSIPATION MODE" for more details of the sleep mode.

Table 11

Index Register, Stack Manipulation Instructions
Condition Code
Regilter

Addressing Modes
Pointer Operations

Mnemonic

IMMED.

-

OP
Compare Index Reg

CPX

8C

DIRECT

#

OP

3 3

9C

-4

INDEX

#

OP

-

#

EXTEND

IMPLIED

OP

OP

-

#

2 AC 5 2 BC 5 3

Boolean/
Arithmetic Operation

-

#

1 X -1 .... X

X-M:M+l

Decrement I ndex Reg

DEX

09

1

Decrement Stack Pntr

DES

34

Increment Index Reg

INX

08

1
1

1 X + 1- X

Increment Stack Pntr

INS

31

1

1

load I nde x Reg

lOX

CE

3

3

DE

4

2

EE

5

2 FE

5

3

load Stack Pntr

lOS

8E

3

3

9E

4

2

AE

5

2

BE

5

3

M .... X H .(M+1)- X L..
M- SP H • (M+1)-SPL.

Store Index Reg

STX

OF

4

2

EF

5

2

FF

5

3

X H - M. XL. - (M + 11

Store Stack Pntr

STS

9F

4 12 'AF

5

2

BF

5

3

SP H - M.SPL - (M+ '1

Inriex Reg .... Stack Pntr

I

SP + 1 .... SP

X-I - SP

1

1

SP+l-X

1

1

B +X- X

3C

5

1

XL - MI!>' SP - 1 - SP
SP + 1 - SP. M,p - X H

35

1

St.:k Pntr .... Index Reg

TSX

30

Add

ABX

3A

Push Data

PSHX
I

i

SP - 1 - SP

1

TXS

I

1

X H - M,p. SP - 1 - SP

Pull Data

PUlX

38

4

1

Exchange

XGDX

18

2

1

SP + 1 - SP. MoP - XL
ACCD· ·IX

5

4

3 2 1 0

H

I

N Z

V

C

·· ·· · · ·
··· ··· ··· ····· ···
: : : :
:
:

·· ·· ··
·· ·· ··
··· ··· ··· ··· ··· ···
· · · · ··
······
't :

R

'f

:

R

7

I

R

7

:

R

• •• •••

(Note) Condition Code Register will be explained in Note of Table 13.

Table 12 Jump, Branch Instructions
Condition Code
Register

AddresSing Modes
Operations

Mnemonic

RELATIVE
OP

-

#

DIRECT
OP

-

#

INDEX
OP -

#

EXTEND

IMPLIED

OP

OP

-

#

-

Branch Test

H

#

Branch Always

BRA

Branch Never

BRN

21

None

Branch I f Carry Clear

BCC

24

C=O

Branch If Carry Set

BCS

25

C=1

Branch If = Zero

BEQ

27

Branch If ;;. Zero

BGE

2C

3

2

> Zero

Branch If

V

C

Z= 1

2E

3

2

Z+(NGVI=O

BHI

22

3

2

C+Z=O

Branch If.; Zero

BlE

2F

3

2

Z + (N G VI = 1

Branch If lower Or
Same

BlS

23

3

2

C+Z = 1
NG>V=1

BlT

20

3

2

Branch If Minus

BMI

2B

3

2

N = 1

Branch If Not Equal
Zero

BNE

26

3

2

Z=O

Branch If Overflow
Clear

BVC

28

3

2

v=o

Branch If Overflow Set

BVS

29

3

2

Branch If Plus

BPl

2A

3

80

5

V =1
N=O

Branch To Subroutine

BSR

Jump

JMP

Jump To Subroutine

JSR

No Operation

NOP

01

Return From Interrupt

RTI

3B 10 1

Return From
Subroutine

RTS

39

5

Software Interrupt

SWI

3F

12 1

Wait for Interrupt"
Sleep

WAI

3E

9

1

SLP

lA

4

1

(Note)

N Z

N G V =0

BGT

< Zero

I

None

20

Branch If Higher

Branch If

543210

3

2

7E

3

3

AD 5

2

BD

6

3

6E
90

5

2

1

1

Advances Prog. Cntr.
Only

--1 --

1

•

S ••

••••••

• WAI puts R/IN high; Address Bus goes to FFFF; Data Bus goes to the three state.
Condition Code Register will be explained in Note of Table 13.

~HITACHI

117

HD6303X,HD63A03X,HD63B03X-----------------------Table 13 Condition Code Register Manipulation Instructions
~ddrellin9Modes

Operations

Mnemonic

Condition Code Register
Boolean Operation

IMPLIED
OP

-

#

Cle.. Carry

ClC

OC

1

1

Clear Intarrupt Mask

Cli

OE

1

Clear Overflow

ClV

OA

1

O-V

Set Carry

SEC

00

1
1
1

O"'C
0-1

1

1 -C

Set Interrupt Mask

SEI

OF

1

1

1-1

Set Overflow

SEV

OB

1

1

I .... V

Accumulator A - CCR

TAP

06

1

1

A- CCR

CCR ... Accumulator A

TPA

07

1

1

CCR-A

LEGEND
OP Operation Code (Hexadecimal)
Number of MCU Cycles
Msp Contents of memory location pointed to by Stack Pointer
#
Number of Program Bytes
+
Arithmetic Plus
Arithmetic Minus
•
Boolean AND
+ Boolean Inclusive OR
e Boolean Exclusive OR
iii; Complement of M
~
Transfer into
OBit = Zero
00 Byte = Zero
(Note)

Condition Code
(Bit V)
(Bit C)
(Bit C)
(Bit V)
15; (Bit V)
(6)
(Bit V)
(i)
(Bit N)
® (All Bid
(§) (Bit I)
(1gl (All Bid
® (Bit C)

(i)
(2)
(3)

®

5

4

3

2

1

H

I

N

Z

V

0
C

·· · ·· ·· ·· ·
··· ·· ··· ·· ·· ··
···· ·
······
R

R

R

a

S

S

S

---

,Jit---

CONDITION CODE SYMBOLS
H
Half-carry from bit 3 to bit 4
I
Interrupt mask
N
Negative (sign bit)
Z
Zero (byte)
V
Overflow, 2's complement
C
Carry/Borrow from/to bit 7
R
Reset Always
S
Set Always
t Set if true after test or clear
•
Not Affected

Register Notes: (Bit set if test is true and cleared otherwise)
Test: Result = 100oo000?
Test: Result ~ OOOOOOOO?
Test: BCD Character of high-order byte greater than 10? (Not cleared if previously set)
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
Test: Set equal to Nel C = 1 after the execution of instructions
Test: Result less than zero? (Bit 15=1)
Load Condition Code Register from Stack.
Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exist the wait state.
Set according to the contents of Accumulator A.
Result of Multiplication Bit 7=1? (ACCB)

Table 14 OP-Code Map
OP

ACC

ACC

CODE

A

B

0100

0101

~
LO

0000

0001

0010

0011

0

I

2

3

0000

O~ SBA

0001

I

0010
0011

2
3

0100

4

0101

5

ASLO

0110

6

TAP

0111

7

TPA

TBA

1000

8

INX

NOP

BRA

TSX

BRN

INS

BHI

PULA

BLS

PULB

BCC

DES

BCS

TXS

------

BNE

PSHA

BEQ

PSHB

XGOX

BVC

PULX

CBA

~ ~
/' ~
LSRO ~
TAB

1001

9

OEX

OAA

BVS

RTS

1010

A

CLV

SLP

BPL

ABX

1011

B

SEV

ABA

BMI

RTI

1100

C

CLC

L'

BGE

PSHX

1101

0

SEC

1110

E

CLI

1111

F

SEI
0

---------

~
I

'UNOEFINEO OP CODE

BLT

MUL

BGT

WAI

BlE

SWI

2

3

5

%

OIR

liND

0111

1000

1

1001

1

7

8

1

9

!

6

EXT

IMM

1

OIR

liND

1

EXT

1010 i 1011

1100

1

1101

1

1110

1

1111

E

1

A

1

1

B

NEG

...-----

0
I

OIM

SBC

2
3

AOOO

SUBO
AND
ElM

ROR
_ _ _ ·1

ASR

4

BIT

5

LOA

6

~·I

STA

ASL

EOR

ROL

AOC.
TIM

7
8
A

-.-

ADO

TST

BSR

JSR

1

lOS

JMP

~I
7

8

~

~HITACHI

J

--

STS

9

1

A

._-

___ I

CPX

INC

6

STA

9

ORA

DEC

CLR

5

F

CMP

LSR

~ -----4

: 01

AIM

COM

---

C
SUB

• Only each instructions of AIM, OIM, ElM, TIM

118

ACCB or X

ACCA or SP
IMM i

OIR

0110

----4

INO

1

B

.

B

LOO

C

STO
----lOX
~~----sTX-

~

C

1

0 1

E

1

F

0

7

•
•

CPU OPERATION
CPU Instruction Flow

When operating, the CPU fetches an instruction from a
memory and executes the required function. This sequence
starts with RES cancel and repeats itself limitlessly if not
affected by a special instruction or a control Signal. SWI, RTI,
WAI and SLP instructions are to change this operation, while
NMI, IRQl, IRQ2 , IRQ3, HALT and STBYare to control it.
Fig. 24 gives the CPU mode transition and Fig. 25 the CPU
system flow chart. Table 15 shows CPU operating states and
port sta tes.
•

Operation at Each Instruction Cycle

Tahle 16 provides the operation at each instruction cycle.
By the pipeline control of the HD6303X, MULT, PUL, DAA
and XGDX instructions etc. pre fetch the next instruction. So
attention is necessary to the counting of the instruction cycles
because it is different from the existent one·····op code fetch
to the next instruction op code.
Table 15 CPU Operation State and Port State
Port

Reset

STBY ***

HALT

Ao - A7

H

T

T

H

Port 2

T

T

Keep

Keep
T

Sleep

Do - D7

T

T

T

AR - AI5

H

T

T

H

Port 5

T

T

T

T

T

T

Keep

Keep

*

T

**

*

Port 6

--

- - - - - - -1 - - - -

Control
Signal

Figure 24 CPU Operation Mode Transition

H ; High, L; Low, T; High Impedance
• RD, WR, R/IN, LTR = H, BA = L
RD, WR, R/IN = T, LTR, BA = H
E pin goes to high impedance state.

~HITACHI

119

~

:I:

I\)

o

o
0)

~

Co)

X

"z
o
0)
w

»
o

PC. IX

w
X

ACCA
ACCB

"z
o
0)
W

to

(Note)

1. The program sequence will come to the RES start from
any place of the flow during RES. When STBY=O. the
sequence will go into the standby mode regardless of the CPU
condition.
2. Refer to "FUNCTIONAL PIN DESCRIPTION" for more
details of interrupts.

~
J:

~

()

-J:

N

Figure 25 HD6303X System Flow Chart

o

W

X

~~~~~~~~~~~~~~~~~~~~~~~~HD6303X,HD63A03X,HD63B03X

Table 16 Cycle-by-Cycle Operation
Address Mode &
Instructions

Address Bus

Data Bus

IMMEDIATE
ADC
AND
CMP
lOA
SBC
ADDD
lDD
LOX

ADD
BIT
EOR
ORA
SUB
CPX
lOS
SUBD

1

2

Op Code Address+ 1
Op Code Address+2

1
1

0
0

1
1

1
2
3

Op Code Address+ 1
Op Code Address+ 2
Op Code Address + 3

1
1
1

0
0
0

1
1
1

1
2
3

Op Code Address + 1
Address of Operand
Op Code Address + 2

1
1
1

0
0
0

1
1
1

1
2
3
1
2
3
4
1
2
3
4
1
2
3
4

Op Code Address + 1
Destination Address
Op Code Address + 2
Op Code Address + 1
Address of Operand
Address of Operand + 1
Op Code Address + 2
Op Code Address+ 1
Destination Address
Destination Address+ 1
Op Code Address + 2
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Jump Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
Address of Operand
FFFF
Address of Operand
Op Code Address+3

1

1

0

Operand Data
Next Op Code

2

3

1
1

0

Operand Data (MSB)
Operand Data (LSB)
Next Op Code

DIRECT
ADC
AND
CMP
LOA
SBC
STA

ADD
BIT
EOR
ORA
SUB

3

3
ADDD
LDD
LOX

CPX
lOS
SUBD

STD
STX

STS

4

4

JSR

5

5
TIM

4
AIM
OIM

ElM
6

1
2

3
4
1
2
3
4

5
6

0

1

0

1

0

1
1
1
1
1
1

0
0
0
0
0
0

1
1
1
1
1
1

0
0
1
1

1
1

0
0
1
1
1
0
0

1

0
0
1
1
1
1
1
1
1
1
1

0
0
1
1
1

0
0
0
0
0
0
0
0

0

1
1

1

0

1
1
1
1
1
1
1
1
1

0
1

1
1

0

1
1

0
1
1
1

0
1
1
1

0
1
1
1
1

0
1
1
1

0
1
1
1
1
1

0

Address of Operand (lSB)
Operand Data
Next Op Code

Destination Address
Accumulator Data
Next Op Code
Address of Operand (lSB)
Operand Data (MSB)
Operand Data (lSB)
Next Op Code
Destination Address (lSB)
Register Data (MSB)
Register Data (lSB)
Next Op Code
Jump Address (lSB)
Restart Address (lSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Next Op Code
Immediate Data
Address of Operand (lSB)
Operand Data
Restart Address (lSB)
New Operand Data
Next Op Code

(Continued)

$

HITACHI

121

Address Mode &
Instructions

Address Bus

INDEXED
JMP

Data Bus

1
2
3

Op Code Address + 1
FFFF
Jump Address

1
1
1

0
1
0

1
1
1

1
1
0

Offset
Restart Address (LSB)
First Op Code of Jump Routine

2

FFFF
IX + Offset
Op Code Address+2

1
1
1

1
0
0

1
1
1

1
1
0

Restart Address (LSB)
Operand Data
Next Op Code

-~A~D~C~~A~D~D~---------+--~l--~O~p-C~o-d~e-A~d~d~r-es-s~+~1-----r~l--~O---+-~l~--~l--~O~ff~s-e~t~-----~--c~=~~

AND
BIT
CMP
EOR
4
LOA
ORA
SBC
SUB
TST
-- STA---------------

3
4

r--,-- -Op"code Address +T-- -

-1'--;---..,0------i---.1--t--·1:--+--O
""'"ff··s-e-t------ - - -- --FFFF
1
1
1
1
Restart Address (LSB)
3
IX + Offset
0
1
0
1
Accumulator Data
4
Op Code Address + 2
1
0
1
0
Next Op Code
'---OpCode-Address+T--- -l;--t-"O.---+-'lr-+-----.l.----+ -Offset -- --- - 2

4

--ADOO----- --CPX
LOS
SUBD

LDD
LOX

s'fo

STS

2

3
4

5

-- ; -2
3
4

STX

5

JSR --

1

FFFF
IX + Offset
IX + Offset + 1
Op Code Address+2
- cip Code- Address + 1 -FFFF
IX + Offset
IX+Offset+ 1
Op Code Address+2
Op Code Address + ,-

I
-

-~

1
1
1
1
1
1
0
0
1
1

1
0
0
0
0
1
1
1
0
0

1
1
1
1
1
1
0
0
1
1

1
1
1
0
1
1
1
1
0
1

Restart Address (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Offse-t
Restart Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code

- Offset

--

--- -- ---

2
3

ASL

ASR

COM
INC
NEG
ROR

DEC
LSR
ROL

- ClR-

I

--

-Ai1iif--EfM---OIM

FFFF
1
1
1
1
Restart Address (LSB)
Stack Pointer
0
1
0
1
Return Address (LSB)
4
Stack Pointer-l
0
1
0
1
Return Address (MSB)
5
IX + Offset
1
0
1
0
First Subroutine Op Code
1
Oil-Code Address+l
1
0
1
1
-Qffsi!t--------2
FFFF
1
1
1
1
Restart AddreS$ (LSB)
6
3
IX + Offset
1
0
1
1
Operand Data
4
FFFF
1
1
1
1
Restart Address (LSB)
5
IX + Offset
0
1
0
1
New Operand Data
6
Op Code Address+ 1
1
0
1
0
Next Op Code
- - ,- --- --Op Code Address+ 1
1
0
1
1
Immediate Data
2
Op Code Address+2
1
0
1
1
Offset
3
FFFF
1
1
1
1
Restart Address (LSB)
4
IX + Offset
1
0
1
1
Operand Data
5
Op Code Address+3
1
0
1
0
Next Op Code
--- t---'---oPcode Address+l
1
0
1
1
Offset
2
FFFF
1
1
1
1
Restart Address (LSB)
3
IX + Offset
1
0
1
1
Operand Data
4
IX + Offset
0
1
0
1
00
5
Op Code Address+2
1
0
1
0
Next Op Code
-- -t--OpCode AddresS+'- - - -1-+-"0.--;---1.-------i-~1-+-'I-m-m--e-dc-c-ia-;-te--D;;;-a--:t-a------ --- ----

-c
2
3
4
5
6
7

Op Code Address+2
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address+3

1
1
1
1
0
1

0
1
0
1
1
0

1
1
1
1
0
1

1
1
1
1
1
0

Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operal"\d'bata
Next Op Code

(Continued)

122

~HITACHI

Address Mode &
Instructions

Address Bus

EXTEND
JMP
3
ADC
AND
CMP
LOA
SBC
STA

ADD
BIT
EOR
ORA
SUB

TST

4

4
ADDD
CPX
LOS
SUBD

LDD
LOX

5

STS

5

Op Code Address + 1
Op Code Address + 2
Jump Address
Op Code Address + 1
Op Code Address+2
Address of Operand
Op Code Address+3

1
1
1
1
1
1
1

0
0
0
0
0
0
0

1
2
3
4
1
2
3
4

Op Code Address+ 1
Op Code Addless+2
Destination Address
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
Op Code Address+3
Op Code Address + 1
Op Code Address + 2
Destination Address
Destination Address+ 1
Op Code Address + 3
Op Code Address+ 1
Op Code Address + 2
FFFF
Stack Pointer
Stack Pointer - 1
Jump Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
FFFF
Address of Operand
Op Code Address+3
Op Code Address + 1
Op Code Address+2
Address of Operand
Address of Operand
Op Code Address + 3

1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
0
1

0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
1
1
0
0
0
0

1
2
3
4

5
JSR

6

1
2
3
4

5
6
ASL
COM
INC
NEG
ROR

ASR
DEC
LSR
ROL

6

1
2
3
4

5
6

,

CLR

5

Data Bus

1
2
3
1
2
3
4

5
STD
STX

RW

2
3
4

5

,
,
,
1

0

,

0

1
1
0
1
1
1
0

Jump Address (MSB)
Jump Address (LSB)
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Next Op Code

0
0
1
1
1
1
0
0
1
1
1
1
1
0
1

1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0

0
1

0

Destination Address (MSB)
Destination Address (LSB)
Accumulator Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (MSB)
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (MSB)
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
00
Next Op Code

1
1

,
1
1
1
1
1
1

0

:

1
1
1
1
1
1
1

,

I

I

I

i

,,,

,
,,,

I

(Continued)

~HITACHI

123

HD6303X,HD63A03X,HD63B03X~~~~~~~~~~~~~~~~~~~~~~~-

Address Mode &
Instructions

IMPLIED
ABA
ASL
ASR
CLC
CLR
COM
DES
INC
INX
LSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
DAA
PULA

ABX
ASLD
CBA
CLI
CLV
DEC
DEX
INS
LSR
R(J)L
NOP
SEC
SEV
TAP
TPA
TSX
XGDX

Address Bus

Op Code Address + 1

1
2
1
2

Op Code Address+ 1

3

Stack Pointer + 1
Op Code Address + 1

1

0

1

0

Next Op Code

1
1

0
1
0
1

1
1
1
1
1
1
1
0
1
1
1
1
1
1
1

0
1
0
1
1
1
1
1
0

Next Op Code
Restart Address (LSB)
Next Op Code
Restart Address (LSB)
Data from Stack
Next Op Code
Restart Address (LSB)
Accumulator Data
Next Op Code
Next Op Code
Restart Address (LSB)
Data from Stack (MSB)
Data from Stack (LSB)
Next Op Code
Restart Address (LSB)
Index Register (LSB)
Index Register (MSB)
Next Op Code
Next Op Code
Restart Address (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)

1

2

PULB

3
PSHA

1

Data Bus

PSHB

4

PULX--------t--4

1
2

3
4
1
2

3
4
1
2

PSHX
5

3
4
5
1
2

RTS
5

7

Op Code Address+ 1

FFFF

FFFF
Stack Pointer
Op Code Address+ 1
Op Code Address+ 1

FFFF
Stack Pointer + 1
Stack Pointer + 2
Op Code Address + 1

FFFF
Stack Pointer
Stack Pointer-l
Op Code Address+ 1
Op Code Address + 1

FFFF

5
1

Stack Pointer + 1
Stack Pointer + 2
Return Address
Op Code Address+ 1

2
3
4
5
6
7

FFFF
FFFF
FFFF
FFFF
FFFF
FFFF

3
4

MUL

FFFF

---,

1
1
---- 1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
1
1
0

0
1

0
0
0
1
1
1
0

0
1
0
0
0
0
1
1
1
1
1
1

0
1
1
1
1
1
1
1
0
1
1
1
1
0

0
0
1
1
1
1
1
1
1
1
1
1
1
1
1

0
1
I

1
1
1
1
1

(ContInued)

124

~HITACHI

------------------------HD6303X,HD63A03X,HD63B03X
Address Mode &
Instructions

i Cycles . CY~le

R/iN

Address Bus

Data Bus

IMPLIED
WAI

1
2
3
4
5
6
7

9

8
9
RTI

1
2
3
4
5
6
7

10

8
9
SWI

12

I
I

10
1
2
3
4
5
6
7

8
9
10
11
12
1
2

SLP

Op Code Address+ 1
FFFF
Stack Pointer
Star.k Pointer-1
Stack Pointer - 2
Stack Pointer-'3
Stack Pointer-4
Stack Pointer - 5
Stack Pointer-6
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer+2
Stack Pointer + 3
Stack Pointer+4
Stack Pointer + 5
Stack Pointer + 6
Stack Pointer + 7
Return Address
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer-1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer-4
Stack Pointer - 5
Stack Pointer-6
Vector Address FFFA
Vector Address FFFB
Address of SWI Routine
Op Code Address+ 1
FFFF

1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1

1
j

4

I

Sleep

I

3
4

FFFF
Op Code Address+ 1

1
2

Op Code Address+ 1
FFFF
I Branch Address' .... Test = " 1"
! Op Code Address +1.. ·Test="0"

0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0

0
0
1
1
1
1
1
1
1
1
0
0
0
0
1

I

1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
I

I

!

!

~

1
0

1
1

Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address (LSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index Register (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)
Address of SWI Routine (LSB)
First Op Code of SWI Routine
Next Op Code
Restart Address (LSB)

I

I

1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1

1

I

i

•1

1
1

0

0
1

1
1

1
1

1

0

1

0

1
1
0
0
1

0
1
1
1
0

1
1
0
0
1

1
1
1
1
0

Restart Address (LSB)
Next Op Code

RELATIVE
BCC
BEQ
BGT
BLE
BLT
BNE
BRA
BVC
BSR

BCS
BGE
BHI
BLS
BMT
BPL
BRN
BVS

3

i

3

I
I

Branch Offset
Restart Address (LSB)
First Op Code of Branch Routine
Next Op Code

I
1
2

5

3
4

5

Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
I Branch Address

I
I
!

I

~HITACHI

Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Op Code of Subroutine

125

H D6303Y, H D63A03Y ,
HD63B03Y
CMOS MPU (Micro Processing

Unit)

-ADVANCE INFORMATIONThe HD6303Y is a CMOS 8-bit micro processing unit which
contains a CPU compatible with the HD6301Vl, 256 bytes of
RAM, 24 parallel I/O Pins, Serial Communication Interface
(SCI) and two timers.
•
•
•

•
•

•
•

•

•

FEATURES
Instruction Set Compatible with the HD6301 Family
Abundant On-chip Resources
• 256 Bytes of RAM
• 24 Parallel 1/0 Pins
• Handshake Interface (Port 6)
• Darlington Transistor Direct Drive (Port 2, 6)
• l6-bit Programmable Timer
1 Input Capture Register
1 Free Running Counter
(
2 Output Compare Registers
• 8-Bit Reloadable Timer
1 8-bit Up Counter
( 1 Time Constant Register
• Serial Communication Interface
Asynchronous Mode
8 Transmit. Formats
( Hardware Parity
Clocked Synchronous Mode
Interrupt - 3 External, 7 Internal
CPU Functions
• Memory Ready, Auto Memory Ready
• Halt
• Error Detection
(Address Trap, Op-code Trap)
Up to 65k Bytes Address Space
Low Power Dissipation Mode
• Sleep
• Standby (Hardware Set, Software Set)
Wide Range of Operation
Vee=3t06V
(f=0.ltoO.5MHz)
f = 0.1 to 1.0 MHz; HD6303Y )
Vee = 5V ± 10%
f = 0.1 to 1.5 MHz; HD63A03Y
(
f = 0.1 to 2.0 MHz; HD63B03Y
Minimum Instruction Cycle Time: 0.51J.s (f = 2.0 MHz)

126

HD6303YP, HD63A03YP,
HD63B03YP

(DP-64S)
HD6303YF, HD63A03YF,
HD63B03YF

(FP-64)

H D6303Y, H o 63A03Y, H D63B03Y

•

PIN ARRANGEMENT

•

•

HD6303YP, HD63A03YP, HD63B03YP

H D6303Y F, H D63A03Y F, H D63B03Y F

.....

6

AD

6

WR

.....
I~Iii iU)~:ECL ~ ~.... ....X .;
e(

e(

w

I~ I~ I~

~ ::i

1 R/W

OR

NMi

BA

5

STBV

D.

P2I

·0.

0,

PH

D.

0,

P"

7 0,

NMI
5

0.

1

P,o

0.

D.

D.
5

D.

Os

D.

2 D.
51 0,

p"

0,

P27

A.

p.~

AI
A.

A,

A,

p.,

A.

p"

A.

p ••

As

p ••

A.

p ••

A,

PS7

'VSS

P60

A.

P6I

A.

A"
CL

CL

: CL::

CL

u

CL

CL

~

<{

c(

nnected to the terminal. Refer to "INTERNAL
OSCILLATOR" for using these input terminals.
• TIMER
This is an input terminal for event counter. Refer to
"TIMER" for details.
.RES
Used to reset the MPU. Refer to "RESET" for details.
.NUM
This terminal is not for user application. This terminal
should be connected to V ss.
• Enable (E)
This output terminal supplies E clock. Output is a singlephase, TTL compatible and 1/4 crystal oscillation frequency
or 1/4 external clock frequency. It can drive one TTL load and
a 90 pF condenser.

• Input Terminals (01 '" 07)
These seven input-only terminals are TTL or CMOS compatible. Of the port D's, D6 is also used as INT2. If D6 is
used as a port, the INT2 interrupt mask bit of the miscellaneous register must be set to "1" to prevent an INT2 interrupt
from being accidentally accepted .
• STBY
This terminal is used to place the MPU into the standby
mode. With STSY at "Low" level, the oscillation stops and
the internal condition is reset. For details, refer to "Standby Mode."
The terminals described in the following are I/O pins for
serial communication interface (SCI). They are also used as
ports Cs , C6 and C7 • For details, refer to "SERIAL COMMUNICA nON INTERFACE."

.CK (Cs)
Used to input or output clocks for serial operation .

.Rx (C6)
Used to receive serial data.

.Tx (C7)
Used to transmit serial data .

-MEMORY MAP
The memory map of the MPU is shown in Fig. 9. During
interrupt processing, the contents of the CPU registers are saved
into the stack in the sequence shown in Fig. 10. This saving
begins with the lower byte (PCL) of the program counter.
Then the value of the stack pointer is decremented and the
higher byte (pC H) of the program counter, index register (X),
accumulator (A) and condition code register (CC) are stacked
in that order. In a subroutine call, only the contents of the
program counter (pCH and peL) are stacked .

• Read/Write (R/W)
This TTL compatible output signal indicates to peripheral
and memory devices whether MPU is in Read ("High"), or
in Write ("Low"). The normal standby state is Read ("High").
Its output can drive one TTL load and a 90pF condenser.

$

HITACHI

135

HD6305X2,HD63A05X2,HD63B05X2---------------------------------------------

o
127
128

$0000

I/O Ports
Timer
SCI

0080
~P07F

RAM
(128Bytes)
Stack

255
256

0
1
2
3
4
5
6

PORT
PORT
PORT
PORT

A
B
C
0

PORT C DDR

8

Timer Data Reg

9

Timer CTRl Reg

PORT A DDR
PORT BOOR

SOO
$01
$02
S03"
S04'
S05'
$06'

Not Used

$QOFF
$0100

10
External
Memory Space

MISC

Reg

S08
$09
$OA

-REGISTERS
There are five registers which the programmer can operate.

o
1" -_ _ _ _A_ _ _ _.....11Accumulator
o
7
IIndex
1' -_ _ _ _X_ _ _ _...JReglster
o

7

13

Program

PC_ _ _ _ _ _ _-'.ICounter
1"'-_ _ _ _ _ _ _
13

6 5

0

Not Used
r--r---r-..-........., Condition

Code

'-T-'-""",,,,,,""""'-'-r"""' Register

16
17
18

r----------

i$lFF6
8182 Interrupt
8191 I-_Y§~ton __ SlFFF

SCI STS Reg
SCI Data Reg

$10
$11
$12

' - - - - - - Negative

Figure 11 Programming Model

• Accumulator (A)
This accumulator is an ordinary 8·bit register which holds
operands or the result of arithmetic operation or data process·
ing.

Figure 9 Memory Map of MPU'

I

76543210
n-4 1 1 1

'------Interrupt
Mask
' - - - - - - - Half
Carry

* Write only regi ster
** Read only regi ster

$3FFF

Condition
Code Register

Pull

n+l

n-3

Accumulator

n+2

n-2

Index Register

n+3

n- 1 1

'1

n+4

n

~g~~~~

Zero

Not Used
$lF
31
32 External
$20
12"'> Memory Space $7F

External
Memory Space

16383

SCI CTRl Reg

PCW
PCl'

n+5

• Index Register (X)
The index register is an 8·bit register, and is used for index
addressing mode. Each of the addresses contained in the
register consists of 8 bits which, combined with an offset
value, provides an effective address.
In the case of a read/modify/write instruction, the index
register can be used like an accumulator to hold operation
data or the result of operation.
If not used in the index addressing mode, the register can
be used to store data temporarily.

Push

* In a subroutine call, only PCl and PCH are stacked.

Figure 10 Sequence of Interrupt Stacking

• Program Counter (PC)
The program counter is a I4·bit register that contains the
address of the next instruction to be executed.
• Stack Pointer (SP)
The stack pointer is a I4·bit register that indicates the ad·
dress of the next stacking space. Just after reset, the stack
pointer is set at address $OOFF. It is decremented when data
is pushed, and incremented when pulled. The upper 8 bits
of the stack pointer are fixed to 00000011. During the MPU
being reset or during a reset stack pointer (RSP) instruction,
the pointer is set to address $OOFF. Since a subroutine or
interrupt can use space up to address $OOCI for stacking, the
subroutine can be used up to 31 levels and the interrupt up
to 12 levels.
• Condition Code Register (CC)
The condition code register is a 5·bit register, each bit
indicating the result of the instruction just executed. The
bits can be individually tested by conditional branch instruc·

136

_HITACHI

HD6305X2,HD63A05X2,HD63B05X2
tions. The CC bits are as follows:
Half Carry (H): Used to indicate that a carry occurred between bits 3 and 4 during an arithmetic operation (ADD, ADC).
Interrupt (I): Setting this bit causes all interrupts, except
a software interrupt, to be masked. If an
interrupt occurs with the bit I set, it is
latched. It will be processed the instant
the interrupt mask bit is reset. (More specifically, it will enter the interrupt processing
routine after the instruction following the
CLI has been executed.)
Negative (N): Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is negative (bit 7 is logic
"1 ").
Zero (Z):
Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is zero.
Carry/
Represents a carry or borrow that occurred
Borrow (C): in the most recent arithmetic operation. This
bit is also affected by the Bit Test and Branch
instruction and a Rotate instruction.
-INTERRUPT
There~e

six different types of interrupt: external interrupts (INT,. I~T2), internal timer interrupts (TIMER,
TIMER2), senal mterrupt (SCI) and interrupt by an instruction (SWI).

Of these six interrupts, the INT2 and TIMER or the SCI
and TIMER2 generate the same vector address, respectively.
When an interrupt occurs, the program in progress stops
and the then CPU status is saved onto the stack. And then,
the interrupt mask bit (I) of the condition code register is
set and the start address of the interrupt processing routine
is obtained from a particular interrupt vector address. Then
the interrupt routine starts from the start address. System
can exit from the interrupt routine by an RTI instruction.
When this instruction is executed, the CPU status before
the interrupt (saved onto the stack) is pulled and the CPU
restarts the sequence with the instruction next to the one at
which the interrupt occurred. Table 1 lists the priority of
interrupts and their vector addresses.
Table 1
Interrupt

Priority of Interrupts
Priority

Vector Address

RES

1

$lFFE,

$lFFF

SWI

2

$lFFC,

$lFFD

INT

3

$lFFA,

$lFFB

TIMER/INT2

4

$lFF8,

$lFF9

SCI/TIMER2

5

$lFF6,

$lFF7

I
I

A flowchart of the interrupt sequence is shown in Fig. 12.
A block diagram of the interrupt request source is shown in
Fig. 13.
,.---------,

y

TNT

y

iNl2

y

1---1
$FF---SP
O---DDR's
CLR INT Logic
$FF---TDR
$7F---Timer Prescaler
$50-+TCR
$3F-+SSR
$OO-+SCR
$7F-+MR

TIMER
Y

SCI

Figure 12 Interrupt Flow Chart

~HITACHI

137

HD6305X2,HD63A05X2,HD63B05X2--------------------------------------------Bit 7 of this register is the INT2 interrupt request flag.
When the falling edge is detected at the INT2 terminal, "I"
is set in bit 7. Then the software in the interrupt routine
(vector addresses: $IFF8, $IFF9) checks bit 7 to see if it
is INT2 interrupt. Bit 7 can be reset by software.

In the block diagram, both the external interrupts INT and
INT2 are edge trigger inputs. At the falling edge of each input,
an interrupt request is generated and latched. The INT interrupt request is automatically cleared if jumping is made to
the INT processing routine. Meanwhile, the INT2 request is
cleared if "0" is written in bit 7 of the miscellaneous register.
For the external interrupts (INT, INT2), internal timer
interrupts (TIMER, TIMER2) and serial interrupt (SCI), each
interrupt request is held, but not processed, if the I bit of the
condition code register is set. Immediately after the I bit is
cleared, the corresponding interrupt processing starts according to the priority.
The INT2 interrupt can be masked by setting bit 6 of the
miscellaneous register; the TIMER interrupt by setting bit 6
of the timer control register; the SCI interrupt by setting bit
5 of the serial status register; and the TIMER2 interrupt by
setting bit 4 of the serial status register.
The status of the INT terminal can be tested by a BIL or
BIH instruction. The INT falling edge detector circuit and
its latching circuit are independent of testing by these instructions. This is also true with the status of the INT2 terminal.

7

Miscellaneous Register (MR;$OOOA)
S
543210

IMR71MRsIZlZlZlZlZlZl
r

f

.

-INT2 Interrupt Mask
INT2 Interrupt Request Flag

Miscellaneous Register (MR; SOOOA)
Bit 6 is the INT2 interrupt mask bit. If this bit is set to "I",
then the INT2 interrupt is disabled. Both read and write are
possible with bit 7 but "I" cannot be written in this bit by
software. This means that an interrupt request by software
is impossible .
When reset, bit 7 is cleared to "0" and bit 6 is set to "I".

• Miscellaneous Register (MR; SOOOA)
The interrupt vector address for the external interrupt
INT2 is the same as that for the TIMER interrupt, as shown
in Table 1. For this reason, a special register called the miscellaneous register (MR; $OOOA) is available to control the
INT2 interrupts.

-TIMER

Figure 14 shows a MPU timer block diagram. The timer
data register is loaded by software and, upon receipt of a
clock input, begins to count down. When the timer data

Vectoring generated
$1 FFA, $1 FFB
BI H/BI L Test
Condition Code Register (CCR)
INT Interrupt Latch

INT
Falling Edge Detector

I

~~~~---

Vectoring generated
$1FFB.$1FF9

TIMER

Serial Status
Register (SSR)

SCI TIMER2

")---~---

Figure 13 Interrupt Request Generation Circuitry

138

eHITACHI

Vectoring generated
$1FF6.$1FF7

----------------------------------------------HD6305X2,HD63A05X2,HD63B05X2
register (TDR) becomes "0", the timer interrupt request
bit (bit 7) in the timer control register is set. In response to
the interrupt request, the CPU saves its status into the stack
and fetches timer interrupt routine address from addresses
$lFF8 and $lFF9 and execute the interrupt routine. The
timer interrupt can be masked by setting the timer interrupt
mask bit (bit 6) in the timer control register. The mask bit
(I) in the condition code register can also mask the timer
interrupt.
The source clock to the timer can be either an external
signal from the timer input terminal or the internal E signal
(the oscillator clock divided by 4). If the E signal is used as
the source, the clock input can be gated by the input to the
timer input terminal.
Once the timer count has reached "0", it starts counting
down with "$FF". The count can be monitored whenever
desired by reading the timer data register. This permits the
program to know the length of time haVing passed after the
occurrence of a timer interrupt, without disturbing the con·
tents of the counter.
When the MPU is reset, both the prescaler and counter are
initialized to logic "I". The timer interrupt request bit
(bit 7) then is cleared and the timer interrupt mask bit (bit
6) is set.
To clear the timer interrupt request bit (bit 7), it is necessary to write "0" in that bit.

• Timer Control Register (TCR; $0009)
Selection of a clock source, selection of a prescaler frequency division ratio, and a timer interrupt can be controlled
by the timer control register (TCR; $0009).
For the selection of a clock source, anyone of the four
modes (see Table 2) can be selected by bits 5 and 4 of the
timer control register (TCR).
Timer Control Register (TCR; $0009)

' - - - - - - - - - - - - - Timer interrupt mask
' - - - - - - - - - - - - - - - Timer interrupt request

After reset, the TCR is initialized to "E under timer terminal control" (bit 5 = 0, bit 4 = 1). If the timer terminal is
"1", the counter starts counting down with "$FF" immediately after reset.
When "I" is written in bit 3, the prescaler is initialized.
This bit always shows "0" when read.
Table 2

TCR7

Timer interrupt request

o

Absent

TCR

Clock Source Selection
Clock input source

Bit 5

Bit 4

0

0

Internal clock E

Present
TCR6

Timer interrupt mask

0

1

E under timer terminal control

o

Enabled

1

0

No clock input (counting stopped)

Disabled

1

1

Event input from timer terminal

Initialize

!Internal
Clock)

E --1---1

Timer Data
Register

L---~-------r----~

Write

Timer Interrupt

Read

Figure 14 Timer Block Diagram

~HITACHI

139

HD6305X2,HD63A05X2,HD63B05X2--------------------------------_____________
A prescaler division ratio is selected by the combination of
three bits (bits 0, 1 and 2) of the timer control register (see
Table 3). There are eight different division ratios: +1, +2, +4,
+8, +16, +32, +64 and +128. After reset, the TCR is set to the
+1 mode.

A timer interrupt is enabled when the timer interrupt mask
bit is "0", and disabled when the bit is "I". When a timer
interrupt occurs, "1" is set in the timer interrupt request bit.
This bit can be cleared by writing "0" in that bit.
-SERIAL COMMUNICATION INTERFACE (SCI)

Table 3

Prescaler Division Ratio Selection

Bit2

TCR
Bit 1

0

0

0

+1,

0

0

1

+2

0

1

0

+4

0

1

1

+8

1

0

0

+16

1

0

1

+32

1

1

0

+64

1

1

1

+128

BitO

Prescaler division ratio

This interface is used for serial transmission or reception
of 8·bit data. Sixteen transfer rates are available in the range
from 1 ,.,.S to approx. 32 ms (for oscillation at 4 MHz).
The SCI consists of three registers, one eighth counter and
one prescaler. (See Fig. 15.) SCI communicates with the CPU
via the data bus, and with the outside world through bits 5,
6 and 7 of port C. Described below are the operations of
each register and data transfer.
eSCI Control Register (SCR; $0010)

SCI Control Registers (SCR; 0010)

E
Transfer
Clock
....._ ......--.PO-I Generator

SCI Data Registers
(SOR: $0012)
Initialize

SCI StatuI Registers
(SSR :$0011 )

Not Used

SCI/TIMER2
Figure 15 SCI Block Diagram

140

_HITACHI

----------------------------------------------HD6305X2,HD63A05X2,HD63B05X2
Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set upon
completion of transmitting or receiving 8-bit data. It is
cleared when reset or data is written to or read from the
SCI data register with the SCRS="I". The bit can also be
cleared by writing "0" in it.

C7 terminal

SCR7

a

Used as I/O terminal (by DDR).
Serial data output (DDR output)

SCR6

Bit 6 (SSR6)
Bit 6 is the TIMER2 interrupt request bit. TIMER2 is used
commonly with the serial clock generator, and SSR6 is set
each time the internal transfer clock falls. When reset, the
bit is cleared. It also be cleared by writing "0" in it. (For
details, see TIMER2.)

C6 terminal

a

Used as I/O terminal (by DDR).
Serial data input (DDR input)

SCR5 SCR4

Clock source

C5 terminal

a
a

a

-

1

-

1

a

Internal

Clock output (DDR output)

1

1

External

Clock input (DDR input)

Bit 5 (SSRS)
Bit 5 is the SCI interrupt mask bit which can be set or
cleared by software. When it is "1", the SCI interrupt (SSR7)
is masked. When reset, it is set to "1".

Used as I/O terminal (by
DDR).

Bit 4 (SSR4)
Bit 4 is the TIMER2 interrupt mask bit which can be set
or cleared by software. When the bit is "I", the TIMER2
interrupt (SSR6) is masked. When reset, it is set to "I".

Bit 7 (SCR7)
When this bit is set, the DDR corresponding to the C7
becomes "1" and this terminal serves for output of SCI data.
After reset, the bit is cleared to "0".
Bit 6 (SCR6)
When this bit is set, the DDR corresponding to the C6
becomes "0" and this terminal serves for input of SCI data.
After reset, the bit is cleared to "0".

Bit 3 (SSR3)
When "1" is written in this bit, the prescaler of the transfer
clock generator is initialized. When read, the bit always is "0".
Bits 2,.., 0
Not used.
SSR7

a

Bits 5 and 4 (SCRS, SCR4)
These bits are used to select a clock source. After reset,
the bits are cleared to "0".

SCR2

SCR1

SCRO

Absent
Present

Bits 3,.., 0 (SCR3 ,.., SCRO)
These bits are used to select a transfer clock rate. Mter
reset, the bits are cleared to "0".

SCR3

SCI interrupt request

SSR6

TIMER2 interrupt request

a

Absent
Present

Transfer clock rate
4.00 MHz

4.194 MHz

SSR5

SCI interrupt mask

0.951lS

a

Enabled

a
a
a
a

a
a
a
a

a
a

a
1

21ls

1.91 1lS

1

a

41ls

3. 82 1ls

1

1

81lS

7.641ls

SSR4

1

1

1

l

1

1

a

1

1

1

1

32768 1ls

1/32 s

1 Ils

-SCI Data Register (SDR; $0012)
A serial-parallel conversion register that
of data.

IS

Disabled

76543210

ISSR7ISSR6ISSR5ISSR4ISSR3~
$

Enabled
Disabled

used for transfer

-SCI Status Register (SSR; $0011)

TIMER2 interrupt mask

• Data Transmission
By writing the desired control bits into the SCI control
registers, a transfer rate and a source of transfer clock are
determined and bits 7 and 5 of port C are set at the serial
data output terminal and the serial clock terminal, respectively. The transmit data should be stored from the accumulator or index register into the SCI data register. The data
written in the SCI data register is output from the C 7 /Tx
terminal, starting with the LSB, synchronously with the
falling edge of the serial clock. (See Fig. 16.) When 8 bit of

HITACHI

141

HD6305X2,HD63A05X2,HD63B05X2--------------------------------------------data have been transmitted, the interrupt request bit is set in
bit 7 of the SCI status register with the rising edge of the last
serial clock. This request can be masked by setting bit 5 of the
SCI status register. Once the data has been sent, the 8th bit
data (MSB) stays at the C7/Tx terminal. If an external clock
source has been selected, the transfer rate determined by bits
o '" 3 of the SCI control register is ignored, and the Cs /CK
terminal is set as input. If the internal clock has been selected,
the Cs/ CK terminal is set as output and clocks are output at
the transfer rate selected by bits 0 '" 3 of the SCI control
register.

Figure 16 SCI Timing Chart
• Data Reception
By writing the desired control bits into the SCI control
register, a transfer rate and a source of transfer clock are determined and bit 6 and 5 of port C are set at the serial data
input terminal and the serial clock terminal, respectively.
Then dummy-writing or -reading the SCI data register, the
system is ready for receiving data. (This procedure is not
needed after reading the subsequent received data. It must be
taken after reset and after not reading the subsequent received
data.)
The data from the C6 /Rx terminal is input to the SCI
data register synchronously with the rising edge of the
serial clock (see Fig. 16). When 8 bits of data have been received, the interrupt request bit is set in bit 7 of the SCI
status register. This request can be masked by setting bit 5
of the SCI status register. If an external clock source have been
selected, the transfer rate determined by bits 0,.., 3 of the SCI
control register is ignored and the data is received synchronously with the clock from the Cs /CK terminal. If the internal
clock has been selected, the Cs/CK terminal is set as output
and clocks are output at the transfer rate selected by bits 0 ,..,
3 of the SCI control register.
.TIMER2
The SCI transfer clock generator can be used as a timer.
The clock selected by bits 3 '" 0 of the SCI control register
(4~s"" approx. 32 ms (for oscillation at 4 MHz» is input to bit
6 of the SCI status register and the TIMER2 interrupt request
bit is set at each falling edge of the clock. Since interrupt
requests occur periodically, TIMER2 can be used as a reload
counter or clock.

CD
-----1
'---_---oJ

CD
®.@
®.@

142

@@

L

:Transfer

clock generator is reset and mask bit (bit 4
of SCI status register) is cleared.
:TIMER2 interrupt request
:TIMER2 interrupt request bit cleared

$

TIMER2 is commonly used with the SCI transfer clock
generator. If wanting to use TIMER2 independently of the
SCI, specify "External" (SCRS = 1, SCR4 = 1) as the SCI
clock source.
If "Internal" is selected as the clock source, reading or
writing the SDR causes the 'prescaler of the transfer clock
generator to be initialized.
-I/O PORTS
There are 24 input/output terminals (ports A, B, C). Each
I/O terminal can be selected for either input or output by the
data direction register. More specifically, an I/O port will
be input if "0" is written in the data direction register, and
output if "1" is written in the data direction register. Port A,
B or C reads latched data if it has been programmed as output,
even with the output level being fluctuated by the output
load. (See Fig. 17.)
When reset, the data direction register and data register go
to "0" and all the input/output terminals are used as input.

Bit of data
direction
register

Bit of
output
data

1

0

1

1

0

X

Figure 17

Status of
output

0
1

3-state

Input to
CPU

0
1

Pin

Input/Output Port Diagram

Seven input-only terminals are available (port D). Writing
to an input terminal is invalid.
All input/output terminals and input terminals are TTL
compatible and CMOS compatible in respect of both input and
output.
If I/O ports or input ports are not used, they should be
connected to Vss via resistors. With none connected to these
terminals, there is the possibility of power being consumed
despite that they are not used.
-RESET
The MPU can be reset either by external reset input (RES)
or power-on reset. (See Fig. 18:) On power up, the reset
input must be held "Low" for at least tose to assure that the
internal oscillator is stabilized. A sufficient time of delay can
be obtained by connecting a capacitance to the RES input as
shown in Fig. 19.

HITACHI

----------------------------------------------HD6305X2,HD63A05X2,HD63B05X2
requirement for minimum external configurations. It can be
driven by connecting a crystal (AT cut 2.0 "" 8.0MHz) or
ceramic oscillator between pins 5 and 6 depending on the required oscillation frequency stability.
Three different terminal connections are shown in Fig. 20.
Figs. 21 and 22 illustrate the specifications and typical arrangement of the crystal, respectively.

4.5/~

5V
Vee

OV
RES
Terminal

----------f"V
-

~:::;al

tRHL

~
VIH

--

RES

r--Cl

_ _ _ _ _ _ _ _ _ _--'

Figure 18

AT Cut
Parallel
Resonance
Co=7pF max.
EXTAL
f=2.0-S.0MHz
6
Rs=600 max.

C~

XTAL

Power On and Reset Timing

5

Co

Figure 21

s

Parameters of Crystal

100kr2 typ
Vee

(a)

HD6305X2
MPU

Figure 19

Input Reset Delay Circuit

-INTERNAL OSCILLATOR

The internal oscillator circuit is designed to meet the
[NOTE] Use as short wirings as possible for connection of the crystal
with the EXT AL and XTAL terminals. Do not allow these
wirings to cross others.

6 EXTAL

iO-~f-O-M-HZ-c:::::J.--5-t XTAL

Figure 22

HD6305X2
MPU

10-22pF±20%

Typical Crystal Arrangement

-LOW POWER DISSIPATION MODE

The HD6305X2 has three low power dissipation modes:
wait, stop and standby.
Crystal Oscillator

HD6305X2
MPU

External
Ceramic Oscillator
Clock
Input 6 EXTAL
NC 5 XTAL HD6305X2
MPU

External Clock Drive
Figure 20

Internal Oscillator Circuit

.Wait Mode

When WAIT instruction being executed, the MPU enters
into the wait mode. In this mode, the oscillator stays active
but the internal clock stops. The CPU stops but the peripheral
functions - the timer and the serial communication interface - stay active. (NOTE: Once the system has entered the
wait mode, the serial communication interface can no longer
be retriggered.) In the wait mode, the registers, RAM and I/O
terminals hold their condition just before entering into the
wait mode.
The escape from this mode can be done by interrupt (INT,
TIMER/INT:i or SCI/TIMER2), RES or STBY. The RES
resets the MPU and the STBY brings it into the standby
mode. (This will be mentioned later.)
When interrupt is requested to the CPU and accepted, the
wait mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt routine. If the interrupt is
masked by the I bit of the condition code register, after releasing from the wait mode the MPU executes the instruction
next to the WAIT. If an interrupt other than the INT (Le.,
TIMER/INT2 or SCI/TIMER2) is masked by the timer control

~HITACHI

143

HD6305X2,HD63A05X2,HD63B05X2---------------------register, miscellaneous register or serial status register, there
is no interrupt request to the CPU, so the wait mode cannot
be released.
Fig. 23 shows a flowchart for the wait function.
-Stop Mode

When STOP instruction being executed, MPU enters into
the stop mode. In this mode, the oscillator stops and the CPU
and peripheral functions become inactive but the RAM,
registers and I/O terminals hold their condition just before
entering into the stop mode.
The escape from this mode can be done by an external
interrupt (INT or INT2), RES or STBY. The RES resets the
MPU and the STBY brings into the standby mode.
When interrupt is requested to the CPU and accepted,
the stop mode escapes, then the CPU is brought to the operation mode and vectors to the interrupt routine. If the interrupt is masked by the I bit of the condition code register,
after releasing from the stop mode, the MPU executes the
instruction next to the STOP. If the INT2 interrupt is masked
by the miscellaneous register, there is no interrupt request to
the MPU, so the stop mode cannot be released.

144

Fig. 24 shows a flowchart for the stop function. Fig. 25
shows a timing chart of return to the operation mode from
the stop mode.
For releasing from the stop mode by an interrupt, oscillation starts upon input of the interrupt and, after the internal
delay time for stabilized oscillation, the CPU becomes active.
For restarting by RES, oscillation starts when the RES goes
"0" and the CPU restarts when the RES goes "1". The duration of RES="O" must exceed tosc to assure stabilized oscillation.
- Standby Mode

The MPU enters into the standby mode when the STBY
terminal goes "Low". In this mode, all operations stop and
the internal condition is reset but the contents of the RAM are
hold. The I/O terminals turn to high-impedance state. The
standby mode should escape by bringing STBY "High". The
CPU must be restarted by reset. The timing of input signals
at the RES and STBY terminals is shown in Fig. 26.
Table 4 lists the status of each parts of the MPU in each
low power disSipation modes. Transitions between each mode
are shown in Fig. 27.

_HITACHI

----------------------------------------------HD6305X2,HD63A05X2,HD63B05X2

Oscillator Active
Timer and Serial
Clock Active
All Other Clocks
Stop

Initialize
CPU, TIMER, SCI,
I/O and All
Other Functions

No

No

1=1

Load PC from
Interrupt Vector
Addresses

Fetch
Instruction
Figure 23 Wait Mode Flow Chart

$

HITACHI

145

HD6305X2,HD63A05X2,HD63B05X2---------------------------------------------

Stop Oscillator
and All Clocks

No

Turn on Oscillator
Wait for Time Delay
to Stabilize

Turn on Oscillator
Wait for Time Delay
to Stabilize

1=0
1=1

Load PC from
Interrupt Vector
Addresses

Fetch
Instruction

Figure 24 Stop Mode Flow Chart

146

~HITACHI

----------------------HD6305X2,HD63A05X2,HD63B05X2

Oscillator ""

11111"" 1111" 1/11" //I

a411111111111111111111111111111111111111111111111111111IIII

II

(
~Ir---+-~

E

Time required for oscillation to become

t

stabiljzed (built-in delay time)

Interrupt

STOP instruction
executed

restart
(a) Restart by Interrupt

Oscillator 11111111111111111111111111111

E

~~~~
Time required for oscillation to become
stabilized (tos c)

STOP instruction
executed

Reset
start

(b) Restart by Reset

Figure 25

Timing Chart of Releasing from Stop Mode

__________

~

~

________

~

~

~

I
I
I
I __I __ I
~

~

~

I

_

,
_ _ _ _ _ _- - J

tosc

Figure 26

Table 4

Restart

Timing Chart of Releasing from Standby Mode

Status of Each Part of MPU in Low Power Dissipation Modes
Condition

Mode

Start

WAIT
Software

STOP
Standby

Hardware

Oscillator

WAIT instruction

Register

RAM.

Active

Stop

Active

Keep

Keep

Keep

STBY, RES, INT, INT2 ,
each interrupt request of
TIMER, TIMER 2 , SCI

STOP instruction

Stop

Stop

Stop

Keep

Keep

Keep

STBY, RES, INT, INT2

STBY="Low"

Stop

Stop

Stop

Reset

Keep

High impedance

~HITACHI

I/O
terminal

Escape

CPU

Timer,
Serial

STBY="High"

147

HD6305X2,HD63A05X2,HD63B05X2----------------------------------------------

Figure 27

Transitions among Active Mode, Wait Mode,
Stop Mode, Standby Mode and Reset

-BIT MANIPULATION

The MPU can use a single instruction (BSET or BCLR) to
set or clear one bit of the RAM or an I/O port (except the
write-only registers such as the data direction register). Every
bit of memory or I/O within page 0 ($00 -- $FF) can be tested
by the BRSET or BRCLR instruction; depending on the result
of the test, the program can branch to required destinations.
Since bits in the RAM, or I/O can be manipulated, the user
may use a bit within the RAM as a flag or handle a single I/O
bit as an independent I/O terminal. Fig. 28 shows an example
of bit manipulation and the validity of test instructions. In
the example, the program is configured assuming that bit 0
of port A is connected to a zero cross detector circuit and
bit I of the same port to the trigger of a triac.
. The program shown can activate the triac within a time of
lOllS from zero-crossing through the use of only 7 bytes on
the memory. The on-chip timer provides a required time of
delay and pulse width modulation of power is also possible.
SE L F 1.

Figure 28

BRClR 0, PORT A, SELF 1
BSET 1, PORT A
BClR 1, PORT A

Example of Bit Manipulation

the byte that follows the operation code.
e Direct
See Fig. 30. In the direct addressing mode, the address of
the operand is contained in the 2nd byte of the instruction.
The user can gain direct access to memory up to the lower
255th address. All RAM and I/O registers are on page 0 of address space so that the direct addressing mode may be utilized.
e Extended
See Fig. 31. The extended addressing is used for referencing to all addresses of memory. The EA is the contents of
the 2 bytes that follow the operation code. An extended
addressing instruction requires a length of 3 bytes .
e Relative
See Fig. 32. The relative addressing mode is used with
branch instructions only. When a branch occurs, the program
counter is loaded with the contents of the byte following the
operation code. EA = (PC) + 2 + ReI., where ReI. indicates a
. signed 8-bit data following the operation code. If no branch
occurs, ReI. = O. When a branch occurs, the program jumps
to any byte in the range + 129 to -127. A branch instruction
requires a length of 2 bytes.

-ADDRESSING MODES

Ten different addressing modes are available to the MPU.
elmmediate
See Fig. 29. The immediate addressing mode provides
access to a constant which does not vary during execution of
the program.
This access requires an instruction length of 2 bytes. The
effective address (EA) is PC and the operand is fetched from

148

elndexed (No Offset)
See Fig. 33. The indexed addressing mode allows access
up to the lower 255th address of memory. In this mode, an
instruction requires a length of one byte. The EA is the
contents of the index register.

_HITACHI

----------------------HD6305X2,HD63A05X2,HD63B05X2
e Indexed (S-bit Offset)
See Fig. 34. The EA is the contents of the byte following the operation code, plus the contents of the index register.
This mode allows access up to the lower 511 th address of
memory. Each instruction when used in the index addressing
mode (8-bit offset) requires a length of 2 bytes.
elndexed (16-bit Offset)
See Fig. 35. The contents of the 2 bytes following the
operation code are added to content of the index register
to compute the value of EA. In this mode, the complete
memory can be accessed. When used in the indexed addressing mode (16-bit offset), an instruction must be 3 bytes long.
e Bit Set/Clear
See Fig. 36. This addressing mode is applied to the BSET
and BCLR instructions that can set or clear any bit on page
O. The lower 3 bits of the operation code specify the bit to
be set or cleared. The byte that follows the operation code
indicates an address within page O.

I

e Bit Test and Branch
See Fig. 37. This addressing mode is applied to the BRSET
and BRCLR instructions that can test any bit within page 0
and can be branched in the relative addressing mode. The
byte to be tested is addressed depending on the contents of
the byte following the operation code. Individual bits within
the byte to be tested are specified by the lower 3 bits of the
operation code. The 3rd byte represents a relative value which
will be added to the program counter when a branch condition
is established. Each of these instructions should be 3 bytes
long. The value of the test bit is written in the carry bit of the
condition code register.
elmplied
See Fig. 38. This mode involves no EA. All information
needed for execution of an instruction is contained in the
operation code. Direct manipulation on the accumulator
and index register is included in the implied addressing mode.
Other instructions such as SWI and RTI are also used in this
mode. All instructions used in the implied addressing mode
should have a length of one byte.

A

~
=

i

Memory

~_~A~
r-F8
I
Index Reg

I
Stack Point

I

PROG LOA ::$F8

058EI=I=4A~6=:J_------J
058FI

Prog Count

0750

F8

CC

I

~
I
I

I

,I

Figure 29

Example of Immediate Addressing

Memory

A

CATFC8320048~~c::j---+_---~~-----[~]2~O::J
lndex eg

Stack
PROG LOA CAT

0520t-:~t::::}_ _--.J
052E I-

Prog !ount

052F
CC

S
:
:

\lrbo~in~t_ _oJ

:

:

Figure 30

Example of Direct Addressing

_HITACHI

149

HD6305X2,HD63A05X2,HD63B05X2--------------------------------------------

Memory

0000
A

40
PROG LOA CAT ~:~!I-~~--L.

Index Reg

I

040B..,.......;;;;..._...

Stack Point

CATFCB6406E5t:~4~0C:~~______________~

Prog Count

040C
CC

Figure 31

Example of Extended Addressing

PROG BEO PROG2 04A 7
04ASI--=:";---I

Figure 32

Example of Relative Addressing

Memory

A

TABLFCC LI

OOBS~:J4~C::~~--~~~-------i----------~~~4C~;:J
~
49
n ex e
BS

,"OG COA X

Stack Point

O"'~

Prog Count

05F5
CC

~

,

Figure 33

150

Example of Indexed (No Offset) Addressing

~HITACHI

----------------------------------------------HD6305X2,HD63A05X2,HD63B05X2

Memory

TABL FCB
FCB
FCB
FCB

Bt
86
DB
CF

BF
86
DB
CF

00B9
008A
008B
OOBC

A

CF
Index Reg

L-----i

03
Stack Point

E6
89

PROG LOA TABL.X 075B
075C

Prog Count
0750
CC

~

t

,

Figure 34

Example of Index (8-bit Offset) Addressing

Memory
i

PROG LOA TABL.X 0692
0693
0694

TABL FCB
FC8
FCB
FCB

BF
86
DB
CF

OnE
OnF
0780
0781

~

DB
Index Reg
02
Stack Point

I
Prog Count
0695
CC

I

BF
86
DB
CF

Figure 35

PORT B EQU 1 0001

A

Example of Index (16-bit Offset) Addressing

r---::-:=--i---.
A

Index Reg
PROG BCLR 6 PORT B 058F
0590

t=::£l0t::j~
01

_ _ _---.J

Prog Count
0591
CC

~

i
,

Figure 36

I
Stack Point

•

«

Example of Bit Set/Clear Addressing

~HITACHI

151

HD6305X2,HD63A05X2,HD63B05X2-------------------·------'--

PORT C EOU 2.0002 t---;""---1 ~____,

A

Index Reg

I

Stack POint

PROG BRCLR 2.PORT C.PROG 2 0574

Prog bount
0594

0575t::~~::~i I

0576 r

t---';;""--1

Figure 37

Example of Bit Test and Branch Addressing

Memory

~

'''''G'AXO'''''~

~..

··

Figure 38

Example of Implied Addressing

-INSTRUCTION SET

• Branch Instructions

There are 62 basic instructions available to the HD6305X2
MPU. They can be classified into five categories: register/
memory, read/modify/write, branch, bit manipulation, and
control. The details of each instruction are described in
Tables 5 through 11.
• Register/Memory Instructions

Most of these instructions use two operands. One operand
is either an accumulator or index register. The other is derived
from memory using one of the addressing modes used on the
HD6305X2 MPU. There is no register operand in the unconditional jump instruction (JMP) and the subroutine jump
instruction (JSR). See Table 5.

A branch instruction branches from the program sequence
in progress if a particular condition is established. See Table 7.
• Bit Manipulation Instructions

These instructions can be used with any bit located up to
the lower 255th address of memory. Two groups are available;
one for setting or clearing and the other for bit testing and
branching. See Table 8.
• Control Instructions

The control instructions control the operation of the MPU
which is executing a program. See Table 9.
• List of Instructions in Alphabetical Order

• Read/Modify/Write Instructions

These instructions read a memory or register, then modify
or test its contents, and write the modified value into the
memory or register. Zero test instruction (TST) does not
write data, and is handled as an exception in the read/modify/
write group. See Table 6.

152

Table 10 lists all the instructions used on the' HD6305X2
MPU in the alphabetical order.
• Operation Code Map

Table 11 shows the operation code map for the instructions
used on the MPU.

~HITACHI

----------------------HD6305X2,HD63A05X2,HD63B05X2
Table 5 Register/Memory Instructions
Addressing Modes
Indexed

Indexed
Mnemonic

Operations

Immediate

Extended

Direct

OP II

-

OP

r

-

-

OP II

-

OP II

-

OP II

-

Load A from Memory

LOA

A6

2

2

B6

2

3 C6

3

4

F6

1

3

E6

2

4

06 3

5

Load X from Memory

LOX

AE

2

2

BE

2

3

cr

3

4

FE

1

3

EE

2

4

DE 3

5

M~X

Store A in Memory

STA

-

-

B7

2

3 C7

3

4

F7

1

4

E7

2

4

07 3

5

Store X in Memory

STX

-

-

-

A~M

BF

2

3

CF

3

4

FF

1

4

EF

2

4

OF

3

5

X~M

Add Memory to A

ADD

AS

2

2

BB

2

3 CB

3

4

FB

1

3

EB

2

4

DB 3

5

A+M-.A

toA

AoC

A9

2

2

B9

2

3 C9

3

4

F9

1

3

E9

2

4

09 3

5

A+M+C~A

Subtract Memory

SUB

AO

2

2

BO

2

3 CO 3

4

FO

1

3

EO

2

4

DO 3

5

A-M~A

A with Borrow

SBC

A2

2

2

B2

2

3 C2

3

4

F2

1

3

E2

2

4

02 3

5

A-M-C~A

AND Memory to A

AND

A4

2

2

B4

2

3 C4

3

4

F4

1

3

E4

2

4

04 3

5

A'M~A

OR Memory with A

ORA

AA

2

2

BA

2

3 CA 3

4

FA

1

3

EA

2

4 oA 3

5

A+M~A

EOR

A8

2

2

BB

2

3 C8

3

4

F8

1

3

E8

2

4

08 3

5

AtM~A

CMP

A1

2

2

Bl

2

3 CI

3

4

F1

1

3

EI

2

4

01

3

5

CPX

A3

2

2

B3

2

3 C3

3

4

F3

1

3

E3

2

4 03 3

BIT

A5

2

2

----

OP II

Condition
Code

Booleanl
Arithmetic
Operation

Indexed

(No Offset) (8-Bit Offset) (16-Bit Offset)

M~A

H

I

•
•
•
•

•
•
•
•
•

N

Z

A

A

A

/'

A

A

C

•
•
•
•

A

A

A

/

/

A

/

f\

/\

/,

/

/\

A

I,

A

/\

A

• •

f\

/

A-M

• •

f\

/

5

X-M

• •

A

I

A·M

• •
•
• • • • •
• • • • •

A

Add Memory and Carry

•
• •
A

Subtract Memory from

• •
• •
• •

f\

•
•

Exclusive OR Memory
with A

i

Arithmetic Compare A
with Memory
Arithmetic Compare X
with Memory

•

I

~

Bit Test Memory with

i

A (Logical Compare)

!

B5

2

3 C5

3

4

F5

1

3

E5

2

4

05 3

5

Jump Unconditional

!

JMP

BC

2

2 CC

3

3

FC

1

2

EC

2

3 DC 3

4

Jump to SubroutIne

I

JSR

Bo 2

5 CD 3

6

Fo

1

5 ED

2

5 DO 3

6

A

Symbols: Op = Operation
# = Number of bytes
- = Number of cycles

Table 6

!

A,

Read/Modify/Write Instructions
Addressing Modes

Operations

I

Indexed

I Mnemonic
I

Implied(A)

Implied(X)

Indexed

(No Offset) (8·Bit Offset)

Direct

OP II

- OP

II

-

OP II

-

OP II

- OP

II

-

Increment

INC

4C

1

2

5C

1

2

3C

2

5

7C

1

5

6C

2

6

A+I ~A or X+I~X or M+ '~M

Decrement

DEC

4A

1

2

5A

1

2

3A

2

5

7A

1

5

6A 2

6

A-I

Clear

CLR

4F

1

2

5F

1

2

3F

2

5

7F

1

5

6F

2

6

OO~A

Complement

COM

43

1

2

53

1

2

33

2

5

73

1

5

63

2

6

A~A or X~X or M~M

~A

or

or

OO-A~A

Negate
(2's Complement)

NEG

40

1

2

50

1

2

30

2

5

70

1

5

60

2

6

Rotate Left Thru Carry

ROL

49

1

2

59

1

2

39

2

5

79

1

5

69

2

6

Rotate Right Thru Carry

ROR

46

1

2

56

1

2

36

2

5

76

1

5

66

2

6

Condition
Code

Booleanl Arithmetic Operation

X-1~X

OO~X

or

or

or

M-l~M

OO~M

H

I

•
•
•
•

•
•
•
•

Z

A

/\

A

/\

0

1

A

A

C

•
•
•
1

OO-X~x

• •
bOlJ
Lb-t I I I I I I I • •
I !AH.,:M! Ibo~ • •
b,
c
[]-I ! ~,,:xr~ I I t--0 •
b,
0-1 I !AH"':M! ! HJ • •
bo e
[?b :1' !AH"':"'! I HJ • •
Equal to LSL
••
or

N

OO-M~M

Aor Xor"

L@:t

A

A

A

/\

A

A

A

A

A

A

A

A

0

A

A

C

bo

Logical Shift Left

LSL

48

1

2

58

1

2

38

2

5

78

1

5

68

2

6

bo

44

2

54

1

2

1

2

57

1

2 37 2

5

1

2 58 1

2

2

5

2 50 1

2 3D 2

4

70

1

Logical Shift Right

LSR

Arithmetic Shift Right

ASR

47

Arithmetic Shift Left

ASL

48

TST

40

1

34

38

2

5

74

1

5

64

2

6

77

1

5

67

2

6

78

1

5

68

2

6

1

4

60 2

5

Test for Negative
or Zero

Symbols: Op = Operation
# = Number of bytes
- = Number of cycles

_HITACHI

A-DO or X-OO or M-DO

C

·

• •

A

A

A

A

A

A

A

A

•

153

H D6305X2,H D63A05X2,H D63B05X2 - - - - - - - - - - - - - - - - - - - - : - - - - Table 7 Branch Instructions
Addressing Modes
Operations

Mnemonic

Relative
OP

:1*

-

Branch Always

BRA

20

2

3

None

Branch Never

BRN

21

2

3

None

Branch IF Higher

BHI

22

2

3

C+Z=O

Branch IF lower or Same

BlS

23

2

3

C+Z=1

Branch IF Carry Clear

BCC

24

2

3

C=O

(BHS)

24

2

3

C=O

BCS

25

2

3

C=1

(BlO)

25

2

3

C=1

BNE

26

2

3

z=o
Z=1

(Branch IF Higher or Same)
Branch IF Carry Set
(Branch IF lower)
Branch IF Not Equal
Branch IF Equal

Condition Code

Branch Test

BEQ

27

2

3

Branch IF Half Carry Clear

BHCC

28

2

3

H=O

Branch IF Half Carry Set

BHCS

29

2

3

H=1

Branch IF Plus

BPl

2A

2

3

N=O

Branch IF Minus

BMI

2B

2

3

N=1

BMC

2C

2

3

1=0

Z

·i-·-

I

BMS

2D

2

3

I

1=1

- - r---- 1----

Branch IF Interrupt line
is low

Bil

2E

2

3

INT=O

Branch IF Interrupt Line
is High

BIH

2F

2

3

INT=1

Branch to Subroutine

BSR

AD

2

5

--

C

• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • • •
• • •
• • •
• .~-- f--t
!. • • i~• • •

Branch IF Interrupt Mask
Bit is Set

N

•
•
•
•
•
•
•
•
•
•
•
•
•

Branch IF Interrupt Mask
Bit is Clear

I

H

_!t·-

.1.

:

Symbols: Op = Operation
# = Number of bytes
- = Number of cycles

Table 8 Bit Manipulation Instructions

Operations
Branch IF Bit n is set
Branch IF Bit n is clear
Set Bit n
Clear Bit n
Symbols: Op

#

Addressing Modes
Bit Test and
Bit Set/Clear
OP
OP
~
BRSET n(n =0··· 7)
2·n
BRCLR n(n=0···7)
01 +2·n
BSET n(n=0···7)
10+2·n 2 5
-BCLR n(n=0···7)
11+2'n 2 5
Mnemonic

-

= Operation

= Number of bytes

- = Number of cycles

154

eHITACHI

Boolean/
Branch Arithmetic
~l- Operation

3
3
-

5

-

5

-

1--+Mn
O--+Mn

Branch
Test

Condition Code
H

Mn=1
Mn=O
-

-

I

N

Z

• • • •

C
/\

• • • •
• • • • •
• • • • •
/\

- - - - - - - - - - - - - - - - - - - - - - HD6305X2,HD63A05X2,HD63B05X2

Table 9 Control Instructions

Mnemonic

Operations

Addressing Modes
Implied

#

-

1

2
2

Transfer A to X
Transfer X to A

TAX

OP
97

TXA

9F

1

Set Carry Bit
Clear Carry Bit
Set Interrupt Mask Bit

SEC

99

CLC
SEI

9B
9B
9A

1
1
1

Clear Interrupt Mask Bit

Decimal Adjust A
Stop
Wait
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles

0--1

2
10

80

1

8

1
1

2

NOP
DAA

9C
90
80

STOP
WAIT

8E
8F

1
1

2
4
4

RSP

Reset Stack Pointer
No-Operation

2

1
1

RTS
RTI

Return from Interrupt

1--C
O--C
1--1

1

• • •
? ? ?
• • •
• • •
• •
• • •
• • •

5

1

N

• • •
• • •
• • •
• •1 •
• •
• 01 •
• •

A--X
X--A

1

1

I

H

1

83
81

CLI
SWI

Software Interrupt
Return from Subroutine

Condition Code

Boolean Operation

$FF-+SP
Advance Prog. Cntr. Only
Converts binary add of BCD charcters Into
BCD format

1\

Z

C

• •
• •1
• 0

•
• •
• •
• •
• •
? ?
• •
• •
• •
• •

1\

1\*

* Are BCD characters of upper byte 10 or more? (They are not cleared if set in advance.)

Table 10 Instruction Set (in Alphabetical Order)
Condition Code

Addressing Modes
Bit
Mnemonic
Implied

Immediate

Direct

" ...ded

x
x
x

x
x
x
x
x

x
x
x

ADC
ADD
AND
ASl
ASR

x
x

IRe,,,'w

Indexed

Indexed

Indexed

Set!

Test lit

(No Offset)

(S-Bit)

(16-Bit)

Clear

Branch

x
x
x
x
x

x
x
x
x
x

X

1\

X

1\

x

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

x

BCC

x

BClR

x
x
x
x
x
x
x
x

BCS
BEQ
BHCC
BHCS
BHI
(BHS)
BIH
Bil
BIT

x

x

x
x
x
x
x
x
x
x

(BlO)
BlS
BMC
BMI
BMS
BNE
BPl
BRA
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero

x

x

Bit

x

x

H

I

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

N

Z

C

1\

1\

1\

1\

1\

1\

1\

1\

•

1\

1\

1\

1\

1\

1\

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

1\

•
•
•
•
•
•
•
•
•
1\

(to be continued)
C
1\

•?

Carry IBorrow
Test and Set if True, Cleared Otherwise
Not Affected
load CC Register From Stack

~HITACHI

155

HD6305X2,HD63A05X2,HD63B05X2---------------------------------------------Table 10 Instruction Set (in Alphabetical Order)
Condition Code

Addressing Modes
Bit
Indexed

Mnemonic
Implied

Immediate

Direct

Extended Aelative (No Offset)

BAN

Indexed

Indexed

Set!

Test &

(S-Bit)

(16-Bit)

Clear

Branch

X

x
x

BACLA
BASET
BSET

X

BSA
CLC

X
X

CLI

X

CLA

X

CMP
COM

X
X

X

X

CPX

x

DEC

X

EOA

X

X
X

DAA

INC

X

X

X
X

X

X

X

X

JMP

X

JSA

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

LOA

X

X

X

X

X

X

LOX

X

X

X

X

X

X

LSL

X

X

X

X

LSA

X

X

X

X

NEG

X

X

X

X

NOP

X

OAA

X

X

X

AOL

X

X

X

X

AOA

X

X

X

X

ASP

X

RTI

X

ATS

X

SBC

X

X

SEC

X

SEI

X

X

STA
STOP

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

STX
SUB

X

SWI

X

TAX

X

TST

X

TXA

X

WAIT

X

Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero

156

Bit

X

C
A

•

X

CarryIBorrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack

$

HITACHI

X

H

I

N

Z

C

•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
~
•
•
•
•0

•
•
•
•
•
•
•1

•

A

A

A

A

1

A

A

A

A

A

A

A

1\

A

A

,\

A

•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•
•
•
•
•

•
?
•
•
•1
•
•
•
•1
•
•
•
•

A
A

•
•
0
•
•
A

•
•
•

• • •
• • •
•
•
A

A

A

A

A

A

1\

0

1\

/\

1\

,\

/\

• • •
•
A

1\

1\

1\

/\

1\

1\

A

•
?
•
•
•
•

• •
? ?
• •

• 1
• •
•
• •

A

A

1\

1\

1\

1\

1\

A

•
•
•
•

•

A

1\

•
•
•
A

•
•
•
•
•
•
A

--------------------------------------------HD6305X2,HD63A05X2,HD63B05X2
Table 11
Bit Manipulation

0

Branch

Operation Code Map
Control

Read/ Modify/Write

Test &

Set/

Branch

Clear

Rei

DIR

A

X

,Xl

,XC

IMP

0

1

2

3

4

5

6

7

8

BRSETO

BSETO

BRA

RTI"

NEG

1

BRCLRO

BCLRO

BRN

-

2

BRSET1

BSET1

BHI

-

RTS"
-

3

BRCLR1

BCLR1

BLS

COM

4

BRSET2

BSET2

BCC

LSR

5

BRCLR2

BCLR2

BCS

SWI"

-

IMP IMM

9

-

CPX

3

-

-

AND

4

-

-

BIT

5

ROR

-

ASR

-

8
9

BRSET4

BSET4

BHCC

LSL/ASL

-

BRCLR4

BCLR4

BHCS

ROL

-

A

BRSET5

BSET5

BPL

DEC

-

B

BRCLR5

BCLR5

BMI

-

C

BRSET6

BSET6

BMC

-

RSP"

D

BRCLR6

BCLR6

BMS

E

BRSET7

BSET7

BIL

F

BRCLR7

BCLR7

3/5

2/5

BIH
2 13

(NOTES)

2 /6

6
STA(+l) 7

CLC

EOR

SEC

ADC

8
9

CLI*

ORA

A

SEI*

ADD

-

JSR(+2)

2/3

W

C

JSR(+1)

JSR(+2) D

LDX

WAIT" TXA" -1/5 1/" 1/1 2/2

L

o

B

JMP(-l)

--

DAA" NOP BSR"
STOP"

1/2

LDA
STA

-

TAX"

HIGH

0
1

BNE

112

<-

2

BEQ

25

F

SBC

BSET3

CLR

,XC

E

CMP

BCLR3

TST(-l)

,Xl

D

-

BRSET3

-

,X2

C

-

BRCLR3

TST

EXT

B

SUB

7

TST(-l)

DIR

A

-

6

INC

Register/Memory

E
STX(+l) F

STX
3/4 3/5

2/4

1/3

1. "-" is an undefined operation code.

2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles).
The number of cycles for the mnemonics asterisked (*) is as follows:
RTI
8
TAX
2
RTS
5
RSP
2
SWI
10
TXA
2
DAA
2
BSR
5
STOP
4
ell
2
WAIT
4
SEI
2
3. The parenthesized numbers must be added to the cycle count of the particular instruction .

• Additional Instructions
The following new instructions are used on the HD6305X2:
DAA Converts the contents of the accumulator into BCD
code.
WAIT Causes the MPU to enter the wait mode. For this mode,
see the topic, Wait Mode.
STOP Causes the MPU to enter the stop mode. For this mode,
see the topic, Stop Mode.

• OPERATION AT EACH INSTRUCTION CYCLE

The HD6305X2 employs a mechanism of the pipeline
control for the instruction fetch and the subsequent instruction
fetch is performed during the current instruction being ex·
ecuted.
Table 12 provides the information about the relationship
among each data on the Address Bus, Data Bus and R/W status
in cycle·by-cycle basis during the execution of each instruction.

Table 12 Cycle·by·Cycie Operation
AddTess Mode & Instructions I Cycles ICycle

# I

Address Bus

Data Bus

IMMEDIATE
ADC, ADD, AND,
BIT, CMP, CPX, EOR,
LDA, LOX, ORA,
SBC, SUB

2

1
2

Op Code Address +1
Op Code Address +2

1
1

Operand Data
Next Op Code

3

1
2

Op Code Address +1
Address of Operand
Op Code Address +2

1
1
1

Address of Operand
Operand Data
Next OpCode

DIRECT
ADC, ADD, AND,
BIT, CMP, CPX,
EOR, LOA, LDX,
ORA, SBC, SUB

3

$

(to be continued)

HITACHI

157

HD6305X2,HD63A05X2,HD63B05X2~~~~~~~~~~~~~~~~~~~~~~-

I

I

Address Mode & Instructions Cycles Cycle #
STA, STX

Op Code Address +1

1

2

Address of Operand

0

3
1
2
1
2
3
4
5
1
2
3
4
5
1
2
3
4

Op Code Address +1
Op Code Address +1
Jump Address
Op Code Address + 1
1FFF
Stack Pointer
Stack Pointer -1
Jump Address
Op Code Address +1
Address of Operand
1FFF
Address of Operand
Op Code Address +2
Op Code Address +1
Address of Operand
1FFF
Op Code Address +2

1

Address of Operand
( Data from Acc.
Data from Ix.
Next Op Code

1
1
1
1
0
0
1
1
1
1
0
1
1
1
"1
1

Jump Address
Next Op Code
Jump Address (LSB)
Irrelevant Data
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Address of Operand
Operand Data
Irrelevant Data
New Operand Data
Next OpCode
Address of Operand
Operand Data
Irrelevant Data
Next Op Code

1
2
3
4
1
2

Op Code Address +1
Op Code Address +2
Address of Operand
Op Code Address +3
Op Code Address +1
Op Code Address +2

1
1
1
1
1
1

3

Address of Operand

0

4
1
2
3
2
3
4
5
6

Op Code Address +3
Op Code Address +1
Op Code Address +2
Jump Address
Op Code Address +1
Op Code Address +2
1FFF
Stack Pointer
Stack Pointer -1
Jump Address

1
1
1
1
1
1
1
0
0
1

Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
( Data from Acc.
Data from I x.
Next OpCode
Jump Address (MSB)
Jump Address (LSB)
Next OpCode
Jump Address (MSB)
Jump Address (LSB)
Irrelevant Data
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code

3

1
2
3

Op Code Address +1
Ix
Op Code Adalress +1

1
1
1

NextOpCode
Operand Data
Next OpCode

4

1
2

Op Code Address +1
1FFF

1
1

3

Ix

0

4
1
2

Op Code Address +1
Op Code Address +1
Ix

1
1
1

Next Op Code
Irrelevant Data
( Data from Ace.
Data from Ix .
Next OpCode
NextOp Code
First Op Code of Jump Routine

2

JSR

5

ASR, CLR, COM,
DEC, INC, LSL,
LSR, NEG, ROL,
ROR

5

TST

4

4

4

JMP

3

JSR

6

INDEXED (No offset)
ADC, ADD, AND,
BIT, CMP, CPX,
EOR, LOA, LOX,
ORA, SBC, SUB
STA, STX

JMP

--

Data Bus

Address Bus

1

3

JMP

EXTENDED
ADC, ADD, AND,
BIT, CMP, CPX,
EOR, LOA, LOX,
ORA, SBC, SUB
STA, STX

I

2

1

(to be continued)

158

$

HITACHI

-----------------------------------------------HD6305X2,HD63A05X2,HD63B05X2
Address Bus

R/W

Data Bus

Op Code Address + 1
1FFF
Stack Pointer
Stack Pointer -1
Ix

1
1
0
0
1

Next Op Code
Irrelevant Data
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code

5

Op Code Address +1
Ix
1FFF
Ix
Op Code Address +1

1
1
1
0
1

Next Op Code
Operand Data
Irrelevant Data
New Operand Data
Next Op Code

1
2
3
4

Op Code Address +1
Ix
1FFF
Op Code Add ress + 1

1
1
1
1

Next Op Code
Operand Data
Irrelevant Data
Next OpCode

4

1
2
3
4

Op Code Address +1
1FFF
Ix + Offset
Op Code Address +2

1
1
1
1

Offset
Irrelevant Data
Operand Data
Next Op Code

4

1
2

Op Code Address +1
1FFF

1
1

Offset
Irrelevant Data
( Data from Ace.
Data from Ix .
Next Op Code

JSR

5

ASR, CLR, COM,
DEC, INC, LSL,
LSR, NEG, ROL,
ROR

5

TST

4

ADC, ADD, AND,
BIT, CMP, CPX,
EOR, LDA, LDX,
ORA, SBC, SUB
STA,STX

1
2
3
4

5
1
2
3
4

INDEXED (S-bit offset)

3

JMP
------

JSR

5

3

Ix + Offset

0

4

Op Code Address +2

1

1
2
3

Op Code Address +1
1FFF
Ix + Offset

1

1

Op Code Address +1
1FFF
Stack Pointer
Stack Pointer -1
Ix + Offset

2
3
4

5
ASR, CLR, COM,
DEC, INC, LSL,
LSR, NEG, ROL,
ROR

a

1
2
3
4

5
6
TST

5

1
2
3
4

5

1

1

Offset
Irrelevant Data
First Op Code of Jump Routine

1

Offset
Irrelevant Data
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code

Op Code Address +1
1FFF
Ix + Offset
1FFF
Ix + Offset
Op Code Address +1

1
1
1
1
0
1

Offset
Irrelevant Data
Operand Data
Irrelevant Data
New Operand Data
Next OpCode

Op Code Address +1
1FFF
Ix + Offset
1FFF
Op Code Address +2

1
1
1
1
1

Offset
Irrelevant Data
Operand Data
Irrelevant Data
Next Op Code

Op Code Address +1
Op Code Address +2
1FFF
Ix + Offset
Op Code Address +1

1
1
1
1
1

'Offset (MSB)
Offset (LSB)
Irrelevant Data
Operand Data
Next OpCode

1
1

0
0

INDE:XED (l6-blt offset)
ADC, ADD, AND,
BIT, CMP, CPX,
EOR, LDA, LDX,
ORA, SBC, SUB

5

1
2
3
4

5

(to be continued)

~HITACHI

159

HD6305X2,HD63A05X2,HD63B05X2---------------------------------------------

I

I

Address Mode & Instructions Cycles Cycle

#

I

Address Bus

Data Bus

5

Op Code Address +3

1

JMP

4

1
2
3
4

JSR

6

1
2
3
4
5

6

Op Code Address +1
Op Code Address +2
1FFF
Ix + Offset
Op Code Address + 1
Op Code Address +2
1FFF
Stack Pointer
Stack Pointer -1
Ix + Offset

1
1
1
1
1
1
1
0
0
1

Offset (MSB)
Offset (LSB)
Irrelevant Data
( Data from Acc.
Data from Ix.
Next OpCode
Offset (MSB)
Offset (LSB)
Irrelevant Data
First Op Code of Jump Routine
Offset (MSB)
Offset (LSB)
Irrel evant Data
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code

1
2

Op Code Address + 1
Op Code Address + 1

1
1

Next Op Code
Next Op Code

5

STA, STX

IMPLIED
ASR, CLR,
DEC, INC,
LSR, NEG,
ROR, TST
CLC, NOP,

COM,
LSL,
ROL,

2

1
2
3

Op Code Address + 1
Op Code Address +2
1FFF

1
1
1

4

Ix + Offset

0

SEC

1

1

Op Code Address +1

RSP, TAX, TXA

2

1
2

2

DAA

2

1
2
1
2

1
1
1
1
1
1
1

Next OpCode
Next OpCode
Next OpCode

CLI, SEI

Op Code Address +1
Op Code Address + 1
Op Code Address + 1
1FFF
Op Code Address +1
Op Code Address +1

STOP, WAIT

4

1
2
3
4

Op Code Address +1
1FFF
1FFF
Op Code Address +1

1
1
1
1

Next OpCode
Irrelevant Data
Irrelevant Data
Next Op Code

RTI

8

1
2
3
4

Op Code Address + 1
1FFF
Stack Pointer
Stack Pointer +1
Stack Pointer +2
Stack Pointer +3
Stack Pointer +4
Return Address

1
1
1
1
1
1
1
1

Next Op Code
Irrelevant Data
CC
Acc.
Ix.
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine

Op Code Address +1
1FFF
Stack Pointer
Stack Pointer +1
Return Address
Op Code Address + 1
1FFF
Stack Pointer
Stack Pointer-1
Stack Pointer-2
Stack Pointer-3
Stack Pointer-4
Vector Address 1 FFC
Vector Address 1 FFD
Address of SWI Routine

1
1
1
1
1
1
1
0
0

Next Op Code
Irrelevant Data
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine

5
6
7
8
RTS

5

SWI

10

1
2
3
4

5
1
2
3
4

5
6
7
8
9
10

160

~HITACHI

0
0

0
1
1
1

Next Op Code
Irrelevant Data
Next Op Code
Next OpCode

Next OpCode
Irrelevant Data
Return Address (LSB)
Return Address (MSB)
Ix.
Acc.
CC
Address of SWI Routine (MSB)
Address of SWI Routine (LSB)
First Op Code of SWI Routine
(to be continued)

~~~~~~~~~~~~~~~~~~~~~~-HD6305X2,HD63A05X2,HD63B05X2

R/W

Data Bus

1
1

3

Op Code Address +1
lFFF
Branch Address ............. Test = "1"
Op Code Address +1 .... Test = "0"

(

1

Next OpCode
Irrelevant Data
First Op Code of Branch Routine
Next Op Code

(

1
2
3
4

Op Code Address +1
lFFF
Stack Pointer
Stack Pointer-l
Branch Address

1
1
0
0
1

Offset
Irrelevant Data
Return Address (LSB)
Return Address (MSB)
First Op Code of Subroutine

Op Code ~ddress +1
Address of Operand
Op Code Address +2
lFFF
( Branch Address .............. Test ="1"
Op Code Address +3 ...... Test = "0"

1
1
1
1

Address of Operand
Operand Data
Offset
I rrelevant Data
First Op Code of Branch Address
NextOp Code

Address Bus

Address Mode & Instructions
RELATIVE
BCC, BCS, BEQ,
BHCC, BHCS, BHI,
BIH, BIL, BLS,
BMC, BMI, BMS,
BNE, BPL, BRA,
BRN

3

BSR

5

1
2

5
BIT TEST AND BRANCH
BRCLR, BRSET

5

1
2
3

4
5

1

(

BIT SET/CLEAR
BCLR,BSET

5

1
2
3

4
5

Op Code Address +1
Address of Operand
lFFF
Address of Operand
Op Code Address +1

~HITACHI

1

1
1
0
1

Address of Operand
Operand Data
Irrel evant Data
New Operand Data
Next OpCode

161

H D6305Y2, H D63A05Y2,
HD63B05Y2
CMOS M PU (Micro Processing

Unit)

-PRELIMINARYThe HD6305Y2 is a CMOS 8-bit micro processing unit. A
CPU, a clock generator, a 256 byte RAM, I/O terminals, two
timers and a serial communication interface (SCI) are built in
the HD6305Y2.
The HD6305Y2 has the same functions as the HD6305YO's
except for the number of I/O terminals. Its memory space is
expandable to 16k bytes externally

HD6305Y2P, HD63A05Y2P,
HD63B05Y2P

• HARDWARE FEATURES
• 8-bit based MPU
.256 bytes of RAM
• A total of 31 terminals, including 24 I/O's, 7 inputs
• Two timers
- 8·bit timer with a 7·bit prescaler (programmable prescaler;
event counter)
- 15-bit timer (commonly used with the SCI clock divider)
.On-chip serial interface circuit (synchronized with clock)
.Six interrupts (two external, two timer, one serial and one
software)
• Low power dissipation modes
- Wait .... In this mode, the clock oscillator is on and the
CPU halts but the timer/serial/interrupt function is operatable.
- Stop .... In this mode, the clock stops but the RAM
data, I/O status and registers are held.
- Standby .. In this mode, the clock stops, the RAM data
is held, and the other internal condition is
reset.
• Minimum instruction cycle time
- HD6305Y2 ..... 11ls (f = 1 MHz)
- HD63A05Y2 ..... 0.67 IlS (f = 1.5 MHz)
- HD63B05Y2 .... 0.51ls (f = 2 MHz)
• Wide operating range
VCC 3 to 6V (f =0.1 to 0.5 MHz)
- HD6305Y2 ..... f = 0.1 to 1 MHz (Vee = 5V ± 10%)
- HD63A05Y2 .... f = 0.1 to 1.5 MHz (Vee = 5 V ± 10%)
- HD63B05Y2 .... f = 0.1 to 2 MHz (Vee = 5 V ± 10%)
.System development fully supported by an evaluation kit

=

162

(DP-64S)
HD6305Y2F, HD63A05Y2F,
HD63B05Y2F

(FP-64)

• SOFTWARE FEATURES
.Similar to HD6800
• Byte efficient instruction set
• Powerful bit manipulation instructions (Bit Set, Bit Clear, and
Bit Test and Branch usable for 192 byte RAM bits within page
and all I/O terminals)
• A variety of interrupt operations
• Index addressing mode useful for table processing
• A variety of conditional branch instructions
• Ten powerful addressing modes
• All addressing modes adaptable to RAM, and I/O instructions
• Three new instructions, STOP, WAI T and DAA, added to the
H06805 family instruction set
• Instructions that are upward compatible with those of Motorola's MC6805P2 and MC146805G2

a

~HITACHI

----------------------------------------------HD6305Y2,HD63A05Y2,HD63B05Y2
• PIN ARRANGEMENT

•

•

HD6305Y2P, HD63A05Y2P, HD63B05Y2P
vss

0

HD6305Y2F, HD63A05Y2F. HD63B05Y2F

DATAo
DATA,
DATAa
DATA3
DATA.
DATA_
DATA.
DATA,
E
R/W
ADR"
ADR ..
ADR"
ADR,o
AOR.
ADR.
ADR,

RES

iNT
STBY
XTAL
EXTAL
NUM
TIMER
A,
A.
A_
A.
A3
Aa
A,
Ao
B,
B.
B_
B.
B3
B2
B,
Bo
C,/Tx
C./Rx

51

OATAs
DATA,
E
R/W
AOR'3
AOR 12
AOR"
AOR,o
AOR.
AOR s

ADR.
ADR.
ADR.
AD R 3
ADR2
ADR,
ADRo
0,

AOR,
AOR s
AOR s
AOR4
AOR 3
AOR,

0./i'N'f;

AOR,

C_/CK

o.

C.
C3
Ca
C,
Co

O.

AOR o

03
02
0,

0,

Vee

(Top View)
(Top View)

• BLOCK DIAGRAM
XTAl EXTAl

TIMER

Accumulator
A

Index
Register

Port A
I/O
Terminals

Condition Code
Register
t -_ _ _--.,;C;.;;C~
Stack
Pointer Sp
B,

B2
B3

"Low"

0,

ALU
CD

Program
Counter

B.
B_

0.!iNT2
D.
D.
Port 0
0 3 Input
O2
Terminals

CPU

Program
Counter
"High" PCH

So
Port B
I/O
Terminals

0,

CPU
Control

x

"5
PCl

B.
B,

a!

;;
a!

~

"0
"0
c{

Port C
I/O
Terminals

ADR'3
ADR"
ADR"
ADR,o
ADR.
ADR.
ADR,
ADR.
ADR.
ADR.
ADR3
ADR2
ADR,
ADRo

c_/CK - - , . . - - - 1
C./Rx
c,/Tx

--f-'*--t

-iH-rL-.1.-.J
Serial
Data
Register

Serial
Status
Register

DATA,
DATA.
DATA.
DATA.
DATA3
DATA2
DATA,
DATAo

~HITACHI

163

HD6305Y2.HD63A05Y2.HD63B05Y2~~~~~~~~~~~~~~~~~~~~~~

• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Value

Unit

Supply Voltage

Vee

-0.3-+7.0

V

Input Voltage

Vin

-0.3 - Vee + 0.3

V

Operating Temperature

Topr

0-+70

Storage Temperature

T ltg

-55 - +150

°c
°c

(NOTE]

Th ..e products hive I protection circuit in their input terminlls 19a1nst high Ilectrostltic voltlge or high Ilectric fields. Notwlthstlndlng.
be clreful not to epply Iny voltlge higher then the ebsolute mlxlmum rltlng to the.. high Input Impedence circuits. To I ..ure normel
operltlon. we recommended Vln. Vout ; Vss ~ (Vln or Vout ) ~ Vee.

•

ELECTRICAL CHARACTERISTICS

•

DC CHARACTERISTICS (Vee

=5.0V±10%, Vss" OV, Ta" 0 Symbol

Item

o

+70 C, unless otherwise noted.)

Input "High" Voltage

min

typ

max

V~c-0.5

Vr-r.+0.3

Test Condition

IOH = -200~A

2.4

IOH = -10~A

Vee- 0 .7

IOl = 1.6mA

-

-

-

Operating
Wait

RES, STBY
V IH

EXTAL

Vcc xO .7

Other Inputs
Input "Low" Voltage

2.0

All Inputs

-0.3

V il

Output "High" Voltage All Outputs

V OH

Output "Low" Voltage

VOL

Input Leakage Current
Three·state Current

Current Dissipation * *

All Outputs
TIMER,INT,
0 1 "" 0 7 , STBY
Ao ,.., A 7 , Bo ,.., B 7 •
Co"" C 7 • ADRo '" ADR13*,
E*, R!W*

Illd
II Ts "

f= 1MHz***

Standby
Input Capacitance

All Terminals

Vcc+0 .3

V

Vcc+ 0 .3

0.8

V

-

-

V

0.55

V

1.0

~A

-

1.0

~A

-

5

10

mA

-

2

5

mA

-

2

10

~A

2

10

~A

-

-

12

pF

Yin = 0.5"" Vce-0.5

Icc

Stop

Unit

f = 1MHz, Vin = OV

Cin

• Only at standby
•• VIH min = Vee-1.OV, Vil max = O.BV
••• The value at f = xMHz is given by using.
Icc (f=xMHz) = Icc (f= 1MHz) xx
•

AC CHARACTERISTICS (Vee = 5.0V±10%, Vss = OV, Ta = 0 '" +70°C, unless otherwise noted.)
Item

Symbol

Test
Condition

HD6305Y2

Unit

max

min

typ

max

min

-

10

0.666

0.5

-

10

-

20

-

20

ns

-

-

20

-

10

20

20

-

20

ns

-

300

-

220

-

ns

-

300

-

220

-

-

ns

250

-

-

-

-

190

-

-

TBD

ns

-

20

-

20

-

-

ns

t cvc

1

Enable Rise Time

tEr

-

Enable F,all Time

tEf

-

Enable Pulse Width("High" Level)
Enable Pulse Width("Low" Level)

PWEH
PW El

Address Delay Time

tAD

Address Hold Time

tAH

Data Delay Time

tow

-

Data Hold Time (Write)

tHW

20

Data Set-up Time (Read)

tOSR

80

Data Hold Time (Read)

tHR

0

164

HD63B05Y2

typ

Cycle Time

450
450
Fig. 1

HD63A05Y2

min

20

-

-

~HITACHI

250

-

-

20
60

-

-

0

-

160

-

-

20

-

-

typ

max

~s

TBD

ns

-

ns

TBD

-

-

ns

0

-

-

ns

---------------------------------------------HD6305Y2,HD63A05Y2,HD63B05Y2
•

PORT TIMING (Vee = 5.0V±10%, Vss = OV, Ta = 0 ,..., +70°C, unless otherwise noted.)
Item

•

Symbol

Port Data Set-up Time
(Port A, B, C, D)

tpDS

Port Data Hold Time
(Port A, B, C, D)

tpDH

Port Data Delay Time
(Port A, B, C)

tpDW

HD6305Y2

HD63A05Y2

HD63B05Y2

Unit

min

typ

max

min

typ

max

min

typ

max

200

-

-

200

-

-

200

-

-

ns

200

-

-

200

-

-

200

-

-

ns

-

-

300

-

-

300

-

-

300

ns

Fig. 2

Fig. 3

CONTROL SIGNAL TIMING (Vee = 5.0V±10%, Vss = OV, Ta = 0"'" +70°C, unless otherwise noted.)
Item

Symbol

Test
Condition

HD6305Y2

HD63A05Y2

HD63B05Y2

typ

max

min

typ

max

min

typ

max

-

tcyc
+200
tcyc
+200

-

-

-

-

ns

-

-

tcyc
+200
tcyc
+200

-

-

ns

5

-

5

-

250

-

-

250

-

-

tCYc
ns

t'WL

tcyC
+250

-

INT2 Pulse Width

t'WL2

tcyC
+250

-

-

RES Pulse Width

tRWL

5

Control Set-up Time

tcs

250

-

-

Timer Pulse Width

tTWL

tcyC
+250

-

-

tcyc
+200

-

-

Oscillation Start Time (Crystal)

tosc

Fig.5,Fig.20*

-

20

-

-

20

-

Reset Delay Time

tRHL

Fig. 19

-

-

80

--

-

80

typ

max

min

typ

max

21845

0.5

-

-

200

-

16384

250

Fig.5

Unit

min

INT Pulse Width

* CL = 22pF ±20%, Rs
•

Test
Condition

80

tcyc
+200

-

-

ns

-

20

ms

-

ms

= 60il max .

SCI TIMING (Vee = 5.0V±10%, Vss= OV, Ta = 0"'" +70°C, unless otherwise noted.)
Item

Symbol

Clock Cycle

tscyc

Data Output Delay Time

tTXD

Data Set-up Time

tSRX

Data Hold Time

tHRX

Test
Condition

Fig.6,
Fig. 7

HD6305Y2
min

typ

1

-

200
100

HD63B05Y2

HD63A05Y2

max

min

250

-

-

200

-

100

-

32768 0.67

~HITACHI

100

Unit

250

IlS
ns

-

ns

-

ns

165

HD6305Y2,HD63A05Y2,HD63B05Y2~~~~~~~~~~~~~~~~~~~~~~

~---------- tcvc----------~

E

PWEL
tEr

2.4V

Ao-A13
R/W

O.6V
tDW

MPU Write
00-07

MPU Read
00-07
Figure 1 Bus Timing

E

2.4V

E

tv

tpDw

Port
A,B,C,D

Port
A,B,C

I
2.4V
O.6V

Data
Valid

Figure 3 Port Data Delay Time (MPU Write)

Figure 2 Port Data Set-up and Hold Times
(MPU Read)
Interrupt
Test
E

Address
Bus

SP-1

~gd~~~" 2Nd~e~~~ 11 FFF

\\.-_......JI

SP-2 SP-3 SP-4 Vector Vector New PC
MSB

LSB

Address Address

PCoPC7

Address

Data Bus
Qp

Code

R/W

Vector Vector

Operand Irrelevant

op Code Data

PC13

\\...______.....1
Figure 4 Interrupt Sequence

166

~HITACHI

First Inst. of

~:d~ess~~~ress Interrupt Routine

~~~~~~~~~~~~~~~~~~~~~~~HD6305Y2.HD63A05Y2.HD63B05Y2

=:=u-t
--l--+-------I~

E

~.~

Vee

tosc

~JVee-O.5V

f

STBY

Vee-O.5V

RES
Address
Bus

R/W

-~

--

'-----:_,- - - -

Vee-O.5V

-~
1FFF

1FFF

's~--'l/llllIllllI

_ _ _I

Data Bus

:--------------~I~__W$$Rtj____
Figure5 Reset Timing
tSeyc

Clock Output

2.4V

C5/CK

O.6V

Data Output

C7/TX
tSRX

tHRX - - - - -

Data Input

2.0V

Cs/RX

O.8V
Figure6 SCI Timing (Internal Clock)

tscyC

2.0V

Clock Input

C5/CK

O.8V

Data Output

C7/ T X

tSRX

tHRX - . - - - - i

Data Input

2.0V

Ca/Rx

O.8V
Figure7 SCI Timing(External Clock)

~HITACHI

167

HD6305Y2,HD63A05Y2,HD63B05Y2----------------------------------------------Data Bus (DATA o '" DATA,)
This TTL compatible three-state buffer can drive one TTL
load and 90pF.

Vcc
TTL Load
2.4kQ
(Pord
IOL=1.6mA
Test point
terminal n - - -......- - - . . - - - , . . - - . . . ,

90pF

-Address Bus (ADR o '" ADR I3 )
Each terminal is TTL compatible and can drive one TTL
load and 90pF.

12kQ

-Input/Output Terminals (Ao '" A" Bo '" B" Co '" C 7 )
These 24 terminals consist offour 8-bit I/O ports (A, B, C).
Each of them can be used as an input or output terminal on
a bit through program control of the data direction register.
For details, refer to "I/O PORTS."
(NOTES 1 1. The load capacitance includes stary capacitance caused
by the probe, etc.
2. All diodes are 1S2074

®.

Figure 8 Test Load

- DESCRIPTION OF TERMINAL FUNCTIONS
The input and output signals of the MPU are described
here.

eVee,Vss

.

Voltage is applied to the MPU through these two tenrunals.
Vee is S.OV ± 10%, while Vss is grounded.
-INT,INT2
External interrupt request inputs to the MPU. For details,
refer to "INTERRUPT". The INT2 terminal is also used as
the port D6 terminal.
- XT AL, EXT AL
These terminals provide input to the on-chip clock circuit.
A crystal oscillator (AT cut, 2.0 to 8.0 MHz) or ceramic
mter is connected to the terminal. Refer to "INTERNAL
OSCILLATOR" for using these input terminals.
• TIMER
This is an input terminal for event counter. Refer to
"TIMER" for details.
-RES
Used to reset the MPU. Refer to "RESET" for details.
-NUM
This terminal is not for user application. This terminal
should be connected to VSS.
- Enable (E)
This output terminal supplies E clock. Output is a singlephase, TTL compatible and 1/4 crystal oscillation frequency
or 1/4 external clock frequency. It can drive one TTL load
and a 90 pF condenser.

-Input Terminals (DI '" D,)
These seven input-only terminals are TTL or CMOS compatible. Of the port D's, D6 is also used as INT2. If D6 is
used as a port, the INT2 interrupt mask bit of the miscellaneous register must be set to "1" to prevent an INT2 interrupt
from being accidentally accepted.
-STBY
This terminal is used to place the MPU into the standby
mode. With STBY at "Low" level, the oscillation stops and
the internal condition is reset. For details, refer to "Standby Mode."
The terminals described in the following are I/O pins for
serial communication interface (SCI). They are also used as
ports Cs , C6 and C,. For details, refer to "SERIAL COMMUNICATION INTERFACE."
-CK (Cs)
Used to input or output clocks for serial operation.

- Rx (C6)
Used to receive serial data.
-Tx (C,)
Used to transmit serial data .

-MEMORY MAP
The memory map of the MPU is shown in Fig. 9. During
interrupt processing,the contents of the CPU registers are saved
into the stack in the sequence shown in Fig. 10. This saving
begins with the lower byte (PCL) of the program counter. Then
the value of the stack pointer is decremented and the higher
byte (PCH) of the program counter, index register (X), accumulator (A) and condition code register (CC) are stacked in
that order. In a subroutine call, only the contents of the program counter (PCH and PCL) are stacked.

- Read/Write (R/W)
This TTL compatible output signal indicates to peripheral
and memory devices whether MPU is in Read ("High"), or
in Write ("Low"). The normal standby state is Read ("High").
Its output can drive one TTL load and a 90pF condenser.

168

~HITACHI

---------------------------------------------HD6305Y2,HD63A05Y2,HD63B05Y2
-REGISTERS

o
63
64

255
256
319
320

I/O Ports
Timer
SCI
RAM
(192Bytes)
Stack
RAM
(64Bytes)

$0000

0
1
2
3
4
5
6

r

$003F

40

A
B
C
D

PORT A DDR
PORT BOOR
PORT C DDR

$00
$01
$02
S03*"
$04*
S05"
S06"

Not Used

OFF
$8
$ 100

8
9
10

\
$013F

Timer Data Reg
Timer CTRL Reg

Mlsc Reg

,
,

o

7

....._ _ _ _
A_ _ _ _.....1 Accumulator

o

7

Index
X_ _ _ _~Reglster
'--_ _ _ _

,

I

o

13

Program
PC_ _ _ _ _ _ _~. Counter
'--_ _ _ _ _ _ _
13
6 5
0

$10
$11
$12

~gg~~

I

l~o. . . l~o.lo. .1.~o'i.-0.I.0-,-1_1
. .1......1 1i.--_ _sP_ _,...." ~~~~fer

Not Used

--------Interrupt
_y§~~n.

There are five registers which the programmer can operate.

$08
$09
SOA

$0140

External
Memory
Space
8182
8191

PORT
PORT
PORT
PORT

__

16
17
18

$1FF6
S1FFF

31
External

3\
633

Memory Space

16383

$3FFF

SCI CTRL Reg
SCI STS Reg
SCI Data Reg

Not Used

Zero
' - - - - - Negative
'------Interrupt
Mask
'-------Half
Carry

$1F

$20

External
Memory Space

$3F

Figure 11 Programming Model

* Write only regi ster
** Read only regi ster

• Accumulator (A)

This accumulator is an ordinary 8-bit register which holds
operands or the result of arithmetic operation or data processing.
Figure 9 Memory Map of MPU
• Index Register (X)

7

I

6

543 2 1 0
Condition
n-4 1 1 1
n+1
Code Register
n-3

Accumulator

n+2

n-2

Index Register

n+3

n-1 1 1
n

I

PCW

Pull

The index register is an 8-bit register,and is used for index
addressing mode. Each of the addresses contained in the
register consists of 8 bits which, combined with an offset
value, provides an effective address.
In the case of a read/modify/write instruction, the index
register can be used like an accumulator to hold operation
data or the result of operation.
If not used in the index addressing mode, the register can
be used to store data temporarily.

n+4
• Program Counter (PC)

PCl*

n+5

Push

* In a subroutine call, only PCL and PCH are stacked.

Figure 10 Sequence of Interrupt Stacking

The program counter is a 14-bit register that contains the
address of the next instruction to be executed.
• Stack Pointer (SP)

The stack pointer is a 14-bit register that indicates the address of the next stacking space. Just after reset, the stack
pointer is set at address $OOFF. It is decremented when data
is pushed, and incremented when pulled. The upper 8 bits
of the stack pointer are fixed to 00000011. During the MPU
being reset or during a reset stack pointer (RSP) instruction,
the pointer is set to addresS $OOFF. Since a subroutine or
interrupt can use space up to address $OOCI for stacking, the
subroutine can be used up to 31 levels and the interrupt up
to 12 levels.
• Condition Code Register (ee)

The condition code register is a S-bit register, each bit
indicating the result of the instruction just executed. The
bits can be indiVidually tested by conditional branch instruc-

~HITACHI

169

HD6305Y2,HD63A05Y2,HD63B05Y2~~~~~~~~~~~~~~~~~~~~~~

tions. The CC bits are as follows:
Half Carry (H): Used to indicate that a carry occurred between bits 3 and 4 during an arithmetic operation (ADD, ADC).
Interrupt (I): Setting this bit causes all interrupts, except
a software interrupt, to be masked. If an
interrupt occurs with the bit I set, it is
latched. It will be processed the instant
the interrupt mask bit is reset. (More specif'ically, it will enter the interrupt processing
routine after the instruction following the
CLI has been executed.)
Negative (N): Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is negative (bit 7 is logic
"I ").
Zero (Z):
Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is zero.
Carry/
Represents a carry or borrow that occurred
Borrow (C): in the most recent arithmetic operation. This
bit is also affected by the Bit Test and Branch
instruction and a Rotate instruction.

-INTERRUPT
There~e six different types of interrupt: external interrupts (INT,. I~T2), internal timer interrupts (TIMER,
TIMER2), senal mterrupt (SCI) and interrupt by an instruction (SWI).

Of these six interrupts, the INT2 and TIMER or the SCI
and TIMER2 generate the same vector address, respectively.
When an interrupt occurs, the program in progress stops
and the then CPU status is saved onto the stack. And then,
the interrupt mask bit (I) of the condition code register is
set and the start address of the interrupt processing routine
is obtained from a particular interrupt vector address. Then
the interrupt routine starts from the start address. System
can exit from the interrupt routine by an RTI instruction.
When this instruction is executed, the CPU status before
the interrupt (saved onto the stack) is pulled and the CPU
restarts the sequence with the instruction next to the one at
which the interrupt occurred. Table 1 lists the priority of
interrupts and their vector addresses.
Table 1
Interrupt

Priority of Interrupts
Priority

Vector Address

RES

1

$1FFE,

$1FFF

SWI

2

$1FFC,

$1FFD

INT

3

$1FFA,

$1FFB

TIMER/INT2

4

$1FF8,

$1FF9

SCI/TIMER2

5

$1FF6,

$1FF7

A flowchart of the interrupt sequence is shown in Fig. 12.
A block diagram of the interrupt request source is shown in
Fig. 13.
y

y

1---+1
$FF---+SP
O---+DDR's
CLR INT Logic
$FF---+TDR
$7F---+ Timer Prescaler
$50---+TCR
$3F---+SSR
$OO---+SCR
$7F---+MR

TIMER
Y

Figure 12 Interrupt Flow Chart

170

TNT

~HITACHI

SCI

~~~~~~~~~~~~~~~~~~~~~~HD6305Y2.HD63A05Y2.HD63B05Y2

In the block diagram, both the external interrupts INT and
INT:z are edge trigger inputs. At the falling edge of each input,
an interrupt request is generated and latched. The INT interrupt request is automatically cleared if jumping is made to
the INT processing routine. Meanwhile, the INT:z request is
cleared if "0" is written in bit 7 of the miscellaneous register.
For the external interrupts (INT, INT:z), internal timer
interrupts (TIMER, TIMER:z) and serial interrupt (SCI), each
interrupt request is held, but not processed, if the I bit of the
condition code register is set. Immediately after the I bit is
cleared, the corresponding interrupt processing starts according to th.:.£!!ority.
The INT:z interrupt can be masked by setting bit 6 of the
miscellaneous register; the TIMER interrupt by setting bit 6
of the timer control register; the SCI interrupt by setting bit
5 of the serial status register; and the TIMER:z interrupt by
setting bit 4 of the serial status register.
The status of the INT terminal can be tested by a BIL or
BIH instruction. The INT falling edge detector circuit and
its latching circuit are independent of testing by these instructions. This is also true with the status of the INT:z terminal.
• Miscellaneous Register (MR; $OOOA)

The interrupt vector address for the external interrupt
INT:z is the same as that for the TIMER interrupt, as shown
in Table 1. For this reason, a special register called the miscellaneous register (MR; $OOOA) is available to control the
INT:z interrupts.

Bit 7 of this register is the INT:z interrupt request flag.
When the falling edge is detected at the INT:z terminal, "1"
is set in bit 7. Then the software in the interrupt routine
(vector addresses: $IFF8, $IFF9) checks bit 7 to see if it
is INT:z interrupt. Bit 7 can be reset by software.
Miscellaneous Register (MR;$OOOA)
76543210

1M R71MR61Z1Z1Z1Z1Z1Z1

I

f

-IN-T-2 Interrupt Mask
' - - - - - - - - - - - - - - INT2 Interrupt Request Flag

Bit 6 is the INT2 interrupt mask bit. If this bit is set to "I",
then the INT2 interrupt is disabled. Both read and write are
possible with bit 7 but "1" cannot be written in this bit by
software. This means that an interrupt request by software
is impossible.
When reset, bit 7 is cleared to "0" and bit 6 is set to "1" .
-TIMER

Figure 14 shows a MPU timer block diagram. The timer
data register is loaded by software and, upon receipt of a
clock input, begins to count down. When the timer data

Vectoring generated
$1 FFA. $1 FFB
BIH/BIL Test
Condition Code Register (CCR)

fNf Interrupt Latch
INT
Falling Edge Detector

~

'\---4~I----- Vectoring generated

$1FFB.$1FF9
TIMER

SCI/TIMER2

" } - - -.......- - - Vectoring generated
$1FF6.$1FF7

Figure 13 Interrupt Request Generation Circuitry

~HITACHI

171

HD6305Y2.HD63A05Y2.HD63B05Y2~~~~~~~~~~~~~~~~~~~~~~

register (TDR) becomes "0", the timer interrupt request
bit (bit 7) in the timer control register is set. In response to
the interrupt request, the CPU saves its status into 'the stack
and fetches timer interrupt routine address from addresses
$1 FF8 and $1 FF9 and execute the interrupt routine. The
timer interrupt can be masked by setting the timer interrupt
mask bit (bit 6) in the timer control register. The mask bit
(I) in the condition code register can also mask the timer
interrupt.
The source clock to the timer can be either an external
signal from the timer input terminal or the internal E signal
(the oscillator clock divided by 4). If the E signal is used as
the source, the clock input can be gated by the input to the
timer input terminal.
Once the timer count has reached "0", it starts counting
down with "$FF". The count can be monitored whenever
desired by reading the timer data register. This permits the
program to know the length of time having passed after the
occurrence of a timer interrupt, without disturbing the con·
tents of the counter.
When the MPU is reset, both the prescaler and counter are
initialized to logic "I". The timer interrupt request bit
(bit 7) then is cleared and the timer interrupt mask bit (bit
6) is set.
To clear the timer interrupt request bit (bit 7), it is necessary to write "0" in that bit.

• Timer Control Register (TCR; $0009)

Selection of a clock source, selection of a prescaler frequency division ratio, and a timer interrupt can be controlled
by the timer control register (TCR; $0009).
For the selection of a clock source, anyone of the four
modes (see Table 2) can be selected by bits 5 and 4 of the
timer control register (TCR).
Timer Control Register (TCR; $0009)

' - - - - - - - - - - - - Timer interrupt mask
' - - - - - - - - - - - - - - - Timer interrupt request

After reset, the TCR is initialized to "E under timer terminal control" (bit 5 = 0, bit 4 = I). If the timer terminal is
"1", the counter starts counting down with "$FF" immediately after reset.
When "1" is written in bit 3, the prescaler is initialized.
This bit always shows "0" when read.
Table 2

TCR7

Timer interrupt request

o

Absent

TCR
Bit 5

Bit 4

0

0

Present

Clock input source
Internal clock E

TCR6

Timer interrupt mask

0

1

E under timer terminal control

o

Enabled

1

0

No clock input (counting stopped)

Disabled

1

1

Event input from timer terminal

Initialize

(Internal
Clock)

E --+---1

"-_ _....,..._ _ _ _,...-_ _.... Timer Interrupt

Write

Read

Figure 14 Timer Block Diagram

172

Clock Source Selection

~HITACHI

~~~~~~~~~~~~~~~~~~~~~~HD6305Y2,HD63A05Y2,HD63B05Y2

A prescaler division ratio is selected by the combination of
three bits (bits 0, 1 and 2) of the timer control register (see
Table 3). There are eight different division ratios: +1, +2, +4,
+8, -'-16, +32, +64 and +128. After reset, the TCR is set to the
+1 mode.
Table 3

Prescaler Division Ratio Selection

TCR
Bit 2

Bit 1

0

0

0
0
0

BitO

Prescaler division ratio

0

+1

0

1

+2

1

0

+4

1

1

+8

A timer interrupt is enabled when the timer interrupt mask
bit is "0", and disabled when the bit is "1". When a timer
interrupt occurs, "1" is set in the timer interrupt request bit.
This bit can be cleared by writing "0" in that bit.
-SERIAL COMMUNICATION INTERFACE (SCI)
This interface is used for serial transmission or reception
of 8·bit data. Sixteen transfer rates are available in the range
from 1 /.Is to approx. 32 ms (for oscillation at 4 MHz).
The SCI consists of three registers, one eighth counter and
one prescaier. (See Fig. 15.) SC I communicates with the CPU
via the data bus, and with the outside world through bits 5,
6 and 7 of port C. Described below are the operations of
each register and data transfer.
-SCI Control Register (SCR; $0010)

1

0

0

+16

1

0

1

+32

1

1

0

+64

1

1

1

+128

SCI Control Registers (SCR; $0010)
E

_ ,. __{Jf_-,

1..-.,...-'-_........

Transfer
Clock
Generator

C5tCK) :
I
I
I

I

SCI Data Registers
(SOR: $0012)

I
I
I

Initialize

I

----.:

C6(Rx)
C7(Tx)

I

:

I _____ _
L

SCI Status Registers
(SSR :$0011)

Not Used

SCI/TIMER2
Figure 15 SCI Block Diagram

~HITACHI

173

HD6305Y2,HD63A05Y2,HD63B05Y2---------------------------------------------SCR7

Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set upon
completion of transmitting or receiving 8-bit data. It is
cleared when reset or data is written to or read from the
SCI data register with the SCRS=" 1". The bit can also be
cleared by writing "0" in it.

C 7 terminal

o

Used as I/O terminal (by DDR).
Serial data output (DDR output)

SCR6

C6 terminal

o

Bit 6 (SSR6)
Bit 6 is the TIMER2 interrupt request bit. TIMER2 is used
commonly with the serial clock generator, and SSR6 is set
each time the internal transfer clock falls. When reset, the
bit is cleared. It also be cleared by writing "0" in it. (For
details, see TIMER2.)

Used as I/O terminal (by DDR).
Serial data input (DDR input)

SCR5 SCR4
0

Clock source

C s terminal

-

0

Used as I/O terminal (by
DDR).

0

1

-

1

0

Internal

Clock output (DDR output)

1

1

External

Clock input (DDR input)

Bit 7 (SCR7)
When this bit is set, the DDR corresponding to the C 7
becomes "1" and this tenninal serves for output of SCI data.
After reset, the bit is cleared to "0".
Bit 6 (SCR6)
When this bit is set, the DDR corresponding to the C6
becomes "0" and this tenninal serves for input of SCI data.
After reset, the bit is cleared to "0".

Bit S (SSRS)
Bit S is the SCI interrupt mask bit which can be set or
cleared by software. When it is "1", the SCI interrupt (SSR7)
is masked. When reset, it is set to "1".
Bit 4 (SSR4)
Bit 4 is the TIMER2 interrupt mask bit which can be set
or cleared by software. When the bit is "1", the TIMER2
interrupt (SSR6) is masked. When reset, it is set to "1".
Bit 3 (SSR3)
When "1" IS written in this bit, the prescaler of the transfer
clock generator is initialized. When read, the bit always is "0".
Bits 2 '" 0
Not used.

Bits Sand 4 (SCRS, SCR4)
These bits are used to select a clock source. After reset,
the bits are cleared to "0".

SCRl

SCRO

0

0

0

0

1 fJ.S

0.95

0

0

0

1

2 J,1s

1.91 J,1S

o

Absent

SSR6

TIMER2 interrupt request

o

Absent
Present

Transfer clock rate
4.00 MHz
4.194 MHz

SCR2

SCI interrupt request

Present

Bits 3 '" 0 (SCR3 '" SCRO)
These bits are used to select a transfer clock rate. After
reset, the bits are cleared to "0".

SCR3

SSR7

SSR5

o

fJ.S

0

0

1

0

4 J,1s

3.82J,1s

0

1

1

8J,1s

7.64J,1s

SSR4

I

I

l

l

l

I

1

1

1

o

1

32768 fJ.S

1/32 s

eSCI Status Register (SSR; $0011)

76543210

ISSR7ISSR6ISSR5ISSR4ISSR3~
174

Enabled
Disabled

0

eSCI Data Register (SDR; $0012)
A serial-parallel conversion register that is used for transfer
of data.

SCI interrupt mask

TIMER2 interrupt mask
Enabled
Disabled

• Data Transmission
By writing the desired control bits into the SCI control
registers, a transfer rate and a source of transfer clock are
detennined and bits 7 and S of port C are set at the serial
data output tenninal and the serial clock tenninal, respectively. The transmit data should be stored from the accumulator or index register into the SCI data register. The data
written in the SCI data register is output from the C 7 /Tx
terminal, starting with the LSB, synchronously with the
falling edge of the serial clock. (See Fig. 16.) When 8 bit of

~HITACHI

----------------------------------------------HD6305Y2,HD63A05Y2,HD63B05Y2
data have been transmitted, the interrupt request bit is set in
bit 7 of the SCI status register with the rising edge of the last
serial clock. This request can be masked by setting bit 5 of the
SCI status register. Once the data has been sent, the 8th bit
data (MSB) stays at the C7/Tx terminal. If an external clock
source has been selected, the transfer rate determined by bits
o ,. ., 3 of the SCI control register is ignored, and the Cs /CK
terminal is set as input. If the internal clock has been selected,
the Cs/ CK terminal is set as output and clocks are output at
the transfer rate selected by bits 0 ,..., 3 of the SCI control
register.

Figure 16 SCI Timing Chart

- Data Reception
By writing the desired control bits into the SCI control
register, a transfer rate and a source of transfer clock are determined and bit 6 and 5 of port C are set at the serial data
input terminal and the serial clock terminal, respectively.
Then dummy-writing or -reading the SCI data register, the
system is ready for receiving data. (This procedure is not
needed after reading the subsequent received data. It must be
taken after reset and after not reading the subsequent received.)
The data from the C6 /Rx terminal is input to the SCI
data register synchronously with the rising edge of the
serial clock (see Fig. 16). When 8 bits of data have been received, the interrupt request bit is set in bit 7 of the SCI
status register. This request can be masked by setting bit 5
of the SCI status register. If an external clock source have been
selected, the transfer rate determined by bits 0 ,..., 3 of the SCI
control register is ignored and the data is received synchronously with the clock from the Cs /CK terminal. If the internal
clock has been selected, the Cs /CK terminal is set as output
and clocks are output at the transfer rate selected by bits 0 ,...,
3 of the SCI control register.

TIMER2 is commonly used with the SCI transfer clock
generator. If wanting to use TIMER2 independently of the
SCI, specify "External" (SCRS = 1, SCR4 = 1) as the SCI
clock source.
If "Internal" is selected as the clock source, reading or
writing the SDR causes the' prescaler of the transfer clock
generator to be initialized.
-I/O PORTS

There are 24 input/output terminals (ports A, B, C). Each
I/O terminal can be selected for either input or output by the
data direction register. More specifically, an I/O port will
be input if "0" is written in the data direction register, and
output if "1" is written in the data direction register. Port A,
B or C reads latched data if it has been programmed as output,
even with the output level being fluctuated by the output
load. (See Fig. 17.)
When reset, the data direction register and data register go
to "0" and all the input/output terminals are used as input.

Bit of data
direction
register

Bit of
output
data

Status of
output

Input to
CPU

1

0

0

0

1

1

1

0

X

Figure 17

3-state

1

Pin

Input/Output Port Diagram

-TIMER2

The SCI transfer clock generator can be used as a timer.
The clock selected by bits 3 -- 0 of the SCI control register
(4Ils- approx. 32 ms (for oscillation at 4 MHz)) is input to bit
6 of the SCI status register and the TIMER2 interrupt request
bit is set at each falling edge of the clock. Since interrupt
requests occur periodically, TIMER2 can be used as a reload
counter or clock.

CD

@@

@@

-----'!. . ______r------'::.ytL..__

---I

CD

:Transfer

L

Seven input-only terminals are available (port D). Writing
to an input terminal is invalid.
All input/output terminals and input terminals are TTL
compatible and CMOS compatible in respect of both input and
output.
If I/O ports or input ports are not used, they should be
connected to Vss via resistors. With none connected to these
terminals, there is the possibility of power being consumed
despite that they are not used.
-RESET

clock generator is reset and mask bit (bit 4
of SCI status register) is clea red.
@. @ : TIMER2 interrupt request
@.@ : TIMER2 interrupt request bit cleared

The MPU can be reset either by external reset input (RES)
or power-on reset. (See Fig. 18.) On power up, the reset
input must be held "Low" for at least tose to assure that the
internal oscillator is stabilized. A sufficient time of delay can
be obtained by connecting a capacitance to the RES input as
shown in Fig. 19.

~HITACHI

175

HD6305Y2,HD63A05Y2,HD63B05Y2-----------------------------------------------

4.5;

5V
Vcc

requirement for minimum external configurations. It can be
driven by connecting a crystal (AT cut 2.0 ,..., 8.0MHz) or
ceramic oscillator between pins 5 and 6 depending on the required oscillation frequency stability.
Three different terminal connections are shown in Fig. 20.
Figs. 21 and 22 illustrate the specifications and typical arrangement of the crystal, respectively.

OV

t RHL t-------

~:::;al

/~-VIH RES

---------¥"1/
1

RES

Terminal

AT Cut
Parallel
Resonance
Co=7pF max.
f=2.0-S.0MHz
Rs=6OQ max.

_ _ _ _ _ _ _ _ _ _- . 1

Figure 18

Power On and Reset Timing

Figure 21

Parameters of Crystal

100kD typ 2
Vee

(a)

RES*2.2t.t F

HD6305Y2

MPU

Figure 19

Input Reset Delay Circuit

-INTERNAL OSCILLATOR

The internal oscillator circuit is designed to meet the
[NOTE] Use as short wirings as possible for connection of the crystal
with the EXTAL and XTAL terminals. Do not allow these
wirings to cross others.

11--~t--6-t EXTAl

iO-~;OM.u= 5 XTAL H~~~5Y2

Figure 22

Typical Crystal Arrangement

-LOW POWER DISSIPATION MODE

10-22pF±20%

The HD630SY2 has three low power dissipation modes:
wait, stop and standby.
Crystal Oscillator

HD6305Y2

MPU
External
Ceramic Oscillator
Clock
Input 6 EXTAl
NC 5 XTAl H D6305Y2

MPU

External Clock Drive
Figure 20

176

Internal Oscillator Circuit

.Wait Mode

When WAIT instruction being executed, the MPU enters
into the wait mode. In this mode, the oscillator stays active
but the internal clock stops. The CPU stops but the peripheral
functions - the timer and the serial communication interface - stay active. (NOTE: Once the system has entered the
wait mode, the serial communication interface can no longer
be retriggered.) In the wait mode, the registers, RAM and I/O
terminals hold their condition just before entering into the
wait mode.
The escape from this mode can be done by interrupt (INT,
TIMER/INTi or SCI/TIMER2), RES or STBY. The RES
resets the MPU and the STBY brings it into the standby
mode. (This will be mentioned later.)
When interrupt is requested to the CPU and accepted, the
wait mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt routine. If the interrupt is
masked by the I bit of the condition code register, after releasing from the wait mode the MPU executes the instruction
next to the WAIT. If an interrupt other than the INT (i.e.,
TIMER/INT2 or SCI/TIMER2) is masked by the timer control

~HITACHI

----------------------------------------------HD6305Y2,HD63A05Y2,HD63B05Y2
register, miscellaneous register or serial status register, there
is no interrupt request to the CPU, so the wait mode cannot
be released.
Fig. 23 shows a flowchart for the wait function.

• Stop Mode
When STOP instruction being executed, MPU enters into
the stop mode. In this mode, the oscillator stops and the CPU
and peripheral functions become inactive but the RAM,
registers and I/O terminals hold their condition just before
entering into the stop mode.
The escape from this mode can be done by an external
interrupt (INT or IN'f2), RES or STBY. The RES resets the
MPU and the STBY brings into the standby mode.
When interrupt is requested to the CPU and accepted,
the stop mode escapes, then the CPU is brought to the operation mode and vectors to the interrupt routine. If the interrupt is masked by the I bit of the condition code register,
after releasing from the stop mode, the MPU executes the
instruction next to the STOP. If the INT2 interrupt is masked
by the miscellaneous register, there is no interrupt request to
the MPU, so the stop mode cannot be released.

Fig. 24 shows a flowchart for the stop function. Fig. 25
shows a timing chart of return to the operation mode from
the stop mode.
For releasing from the stop mode by an interrupt, oscillation starts upon input of the interrupt and, after the internal
delay time for stabilized oscillation, the CPU becomes active .
For restarting by RES, oscillation starts when the RES goes
"0" and~ CPU restarts when the RES goes "I". The duration of RES="O" must exceed 30 ms to assure stabilized oscillation.
• Standby Mode

The MPU enters into the standby mode when the STBY
terminal goes "Low". In this mode, all operations stop and
the internal condition is reset but the contents of the RAM are
hold. The I/O terminals turn to high-impedance state. The
standby mode should escape by bringing STBY "High". The
CPU must be restarted by reset. The timing of input signals
at the RES and STBY terminals is shown in Fig. 26.
Table 4 lists the status of each parts of the MPU in each
low power dissipation modes. Transitions between each mode
are shown in Fig. 27.

~HITACHI

177

HD6305Y2,HD63A05Y2,HD63B05Y2----------------------------------------------

Oscillator Active
Timer and Serial
Clock Active
All Other Clocks
Stop

Initialize
CPU, TIMER, SCI,
I/O and All
Other Functions
No

No

1=1
Load PC from
Interrupt Vector
Addresses

Fetch
Instruction
Figure 23 Wait Mode Flow Chart

178

~HITACHI

----------------------------------------------HD6305Y2,HD63A05Y2,HD63B05Y2

Stop Oscillator
and All Clocks

No

Turn on Oscillator
Wait for Time Delay
to Stabilize

Turn on Oscillator
Wait for Time Delay
to Stabilize

1=0
1=1
Load PC from
Interrupt Vector
Addresses

Fetch
Instruction

Figure 24 Stop Mode Flow Chart

$

HITACHI

179

HD6305Y2,HD63A05Y2,HD63B05Y2------------------------------------------

O.":.'~:~~~\~~~~
I

Time required for oscillation to become
Interrupt

STOP instruction
executed

stabilized (built-in delay time)

Instructions
restart

(a) Restart by Interrupt

Oscillator 11111111111111111111111111111

E

Time required for oscillation to become
stabilized (toscl

STOP instruction
executed

Reset
start

(b) Restart by Reset
Figure 25

Timing Chart of Releasing from Stop Mode

\'--___~~\)--_--JI
,
I

I

I

I

I

I
I

~-~--~--~~~~~~~r~---~~----r---~-------J

tosc

Figure 26

Table 4

Restart

Timing Chart of Releasing from Standby Mode

Status of Each Part of MPU in Low Power Dissipation Modes
Condition

Mode

WAIT

-

Start

Software

STOP
Standby

180

Hardware

Oscillator

WAIT instruction

Escape

CPU

Timer,
Serial

Register

RAM

I/O
terminal

Active

Stop

Active

Keep

Keep

Keep

STBY, RES, INT, INT 2 ,
each interrupt request of
TIMER, TIMER 2 , SCI

STOP instruction

Stop

Stop

Stop

Keep

Keep

Keep

STBY, RES, INT, INT2

STBY="Low"

Stop

Stop

Stop

Reset

Keep

High impedance

~HITACHI

STBY="High"

-----------------------------------------------HD6305Y2,HD63A05Y2,HD63B05Y2

Figure 27

Transitions among Active Mode, Wait Mode,
Stop Mode, Standby Mode and Reset

-BIT MANIPULATION

The MPU can use a single instruction (BSET or BCLR) to
set or clear one bit of the RAM within page 0 or an I/O port
(except the write-only registers such as the data direction
register). Every bit of memory or I/O within page 0 ($00 $FF) can be tested by the BRSET or BRCLR instruction;
depending on the result of the test, the program can branch to
required destinations. Since bits in the RAM on page 0, or I/O
can be manipulated, the user may use a bit within the RAM on
page 0 as a flag or handle a single I/O bit as an independent
1/0 terminal. Fig. 28 shows an example of bit manipulation
and the validity of test instructions. In the example, the program is configured assuming that bit 0 of port A is connected
to a zero cross detector circuit and bit I of the same port to
the trigger of a triac.
The program shown can activate the triac within a time of
lOllS from zero-crossing through the use of only 7 bytes on
the memory. The on-chip timer provides a required time of
delay and pulse width modulation of power is also possible.
SE IF 1.

Figure 28

BRClR 0, PORT A, SELF 1
BSET 1 • PORT A
BClR 1. PORT A

Exa';'ple of Bit Manipulation

-ADDRESSING MODES

Ten different addressing modes are available to the MPU.
elmmediate
See Fig. 29. The immediate addressing mode provides
access to a constant which does not vary during execution of
the program.
This access requires an instruction length of 2 bytes. The

effective address (EA) is PC and the operand is fetched from
the byte that follows the operation code.
e Direct
See Fig. 30. In the direct addressing mode, the address of
the operand is contained in the 2nd byte of the instruction.
The user can gain direct access to memory up to the lower
255th address. 192 byte RAM and 1/0 registers are on page 0
of address space so that the direct addressing mode may be
utilized.
eExtended
See Fig_ 31. The extended addressing is used for referencing to all addresses of memory_The EA is the contents of
the 2 bytes that follow the operation code. An extended
addressing instruction requires a length of 3 bytes_
e Relative
See Fig. 32. The relative addressing mode is used with
branch instructions only. When a branch occurs, the program
counter is loaded with the contents of the byte following the
operation code. EA = (PC) + 2 + ReI., where ReI. indicates a
signed 8-bit data following the operation code. If no branch
occurs, ReI. = O. When a branch occurs, the program jumps
to any byte in the range + 129 to -127. A branch instruction
requires a length of 2 bytes.
elndexed (No Offset)
See Fig. 33. The indexed addressing mode allows access
up to the lower 255th address of memory. In this mode, an
instruction requires a length of one byte. The EA is the
contents of the index register.

~HITACHI

181

HD6305Y2,HD63A05Y2,HD63B05Y2~~~~~~~~~~~~~~~~~~~~~~-

-Indexed (8-bit Offset)
See Fig. 34. The EA is the contents of the byte following the operation code, plus the contents of the index register.
This mode allows access up to the lower 511 th address of
memory. Each instruction when used in the index addressing
mode (8·bit offset) requires a length of 2 bytes.
_Indexed U6-bit Offset)
See Fig. 35. The contents of the 2 bytes following the
operation code are added to content of the index register
to compute the value of EA. In this mode, the complete
memory can be accessed. When used in the indexed, addressing mode (16-bit offset), an instruction must be 3 bytes long.
- Bit Set/Clear
See Fig. 36. This addressing mode is applied to the BSET
and BCLR instructions that can set or clear any bit on page
O. The lower 3 bits of the operation code specify the bit to
be set or cleared. The byte that follows the operation code
indicates an address within page O.

I

Memory

,

~

e Bit Test and Branch
See Fig. 37. This addressing mode is applied to the BRSET
and BRCLR instructions that can test any bit within page 0
and can be branched in the relative addressing mode. The
byte to be tested is addressed depending on the contents of
the byte following the operation code. Individual bits within
the byte to be tested are specified by the lower 3 bits of the
operation code. The 3rd byte represents a relative value which
will be added to the program counter when a branch condition
is established. Each of these instructions should be 3 bytes
long. The value of the test bit is written in the carry bit of the
condition code register.
elmplied
See Fig. 38. This mode involves no EA. All information
needed for execution of an instruction is contained in the
operation code. Direct manipulation on the accumulator
and index register is included in the implied addressing mode.
Other instructions such as SWI and RTI are also used in this
mode. All instructions used in the implied addressing mode
should have a length of one byte.

A

::
~

I

~_-CA~
rF8
J
Index Reg

I

:

:

Stack Point

I

PROG LOA lt$F8

058EIl=~A~6=:}-----_.J
058FI

Prog Count
05CO
CC

F8

I

~

.
I
I

Figure 29

Example of Immediate Addressing

Memory

A

CATFCB32004B~:Ec:~---+----~~-----t~~2~0~J
Index eg

t-::!!t:::t-_....J

PROG LOA CAT 0520
052E I-

Stack

Prog !ount
052F
CC

~
I
I

I
I

I

:

:

I

Figure 30

182

Example of Direct Addressing

~HITACHI

~to~in~t- - - '

- - - - - - - - - - - - - - - - - - - - - - - H D6305Y2,HD63A05Y2,HD63B05Y2

Memory

0000
A

PROG LOA CAT

40

04091-....;~_-L

Index Reg

g:g:I-"";;;;"--I

I
Stack Point

CATFCB6406E5t:::~::~--------------~

Prog Count

040C
CC

Example of Extended Addressing

Figure 31

PROG BEQ PROG2 04A7
04ASI-""':;":"---I

Figure 32

Example of Relative Addressing

Memory

A

TABlFCC II

00B8t:::4~C::::~--~~~------~----------~~~~;;J
49

'"DO COA' O'''§

Prog Count

05F5
CC

§
.

Figure 33

;

Example of Indexed (No Offset) Addressing

~HITACHI

183

HD6305Y2,HD63A05Y2,HD63B05Y2----------------------------------------------

.

r

MeJory

I

TABL FCB
FCB
FCB
FCB

:: BF
::86
::OB
::CF

,

:
/'

BF
86
DB
CF

00B9
008A
008B
008C

lEA
008C

Adder

-,-

I

:

:
E6
89

PROG LOA TABL.X 075B
075C

.

§

"""

~

A
CF
Index Reg
03
Stack Point

l

I

I

Prog Count

I

0750
CC

,

Figure 34

Example of Index (S-bit Offset) Addressing

Memory

~

DB
Index Reg
02

'

,

PROG LOA TABL.X 0692
0693
0694

A

Stack

Oint

I

Prog (;ount
0695
CC

TABL FCB
FCB
FCB
FCB

BF
86
DB
CF

I

BF
86
DB
CF

077E
077F
0780
0781

Figure 35

Example of Index (16-bit Offset) Addressing

Memory

PORT B EQU 1 0001

BF
0000

A
Index Reg

I
PROG BCLR 6. PORT B 058F
0590

":::::J1~0t:::t_ _-_---.J

I-

01
Prog Count
0591
CC

~
I,

Figure 36

184

Stack Point

•,

Example of Bit Set/Clear Addressing

$

HITACHI

I
1

I
I

-----------------------------------------------HD6305Y2,HD63A05Y2,HD63B05Y2

PORT C EQU 2 0002 I--':"~---l

A

Index Reg

I

Stack POint

PROG BRCLR 2.PORT CPROG 20S74
OS 7 SI-""';;;;----l
OS 761-.......:;;--~ I

Figure 37

,

Example of Bit Test and Branch Addressing

Memory

§§

"OGW""~

§§
.··
·

..,.

Figure 38

Example of Implied Addressing

-INSTRUCTION SET
There are 62 basic instructions available to the HD6305Y2
MPU. They can be classified into five categories: register/
memory, read/modify/write, branch, bit manipulation, and
control. The details of each instruction are described in
Tables 5 through 11.
• Register/Memory Instructions
Most of these instructions use two operands. One operand
is either an accumulator or index register. The other is derived
from memory using one of the addressing modes used on the
HD6305Y2 MPU. There is no register operand in the unconditional jump instruction (JMP) and the subroutine jump
instruction (JSR). See Table 5.
• Read/Modify/Write Instructions
These instructions read a memory or register, then modify
or test its contents, and write the modified value into the
memory or register. Zero test instruction (TST) does not
write data, and is handled as an exception in the read/modify/
write group. See Table 6.

• Branch Instructions
A branch instruction branches from the program sequence
in progress if a particular condition is established. See Table 7.
• Bit Manipulation Instructions
These instructions can be used with any bit located up to
the lower 255th address of memory. Two groups are available;
one for setting or clearing and the other for bit testing and
branching. See Table 8.
• Control Instructions
The control instructions control the operation of the MPU
which is executing a program. See Table 9.
-list of Instructions in Alphabetical Order
Table 10 lists all the instructions used on the HD6305Y2
MPU in the alphabetical order.
• Operation Code Map
Table 11 shows the operation code map for the instructions
used on the MPU.

~HITACHI

185

HD6305Y2,HD63A05Y2,HD63B05Y2--------------------------------------------Table 5 Register/Memory Instructions
Addressing Mode.
Indexed
Mnemonit

Operations

Immediate

Indexed

OP #

-

OP #

-

OP #

-

OP #

-

Load A from Memory

LDA

A6 2

2 86

2

3 C6 3

4

F6

1

3 E6

2

4 D6 3

5

M-A

Load X from Memory

LDX

AE

2 BE 2

3 CE 3

4

FE

1

3

EE

2

4 DE 3

5

M-X

Store A in Memory

STA

B7 2

3 C7 3

4

F7

1

4

E7

2

4 D7 3

5

A-M

Store X in Memory

STX

BF 2

3 CF 3

4

FF

1

4

EF

2

4

DF 3

5

Add Memory to A

ADD

AB 2

2 BB 2

3 CB 3

4

FB

1

3 EB 2

4 DB 3

to A

ADC

A9

2

2 B9 2

3 C9 3

4

F9

1

3 E9

2

Subtract Memory

SUB

AO 2

2 BO 2

3 CO 3

4

FO

1

3 EO

2

A with Borrow

SBC

A2 2

2 B2 2

3 C2 3

4

F2

1

3 E2

AN D Memory to A

AND

A4 2

2 B4 2

3 C4 3

4

F4

1

3 E4

OR Memory with A

ORA

AA 2

2 BA 2

3 CA 3

4

FA

EOR

A6 2

2 B8 2

3 C8 3

4

CMP

A1

2

2 B1

3 C1

3

CPX

A3

2

2 B3 2

3 C3 3

A5

2

2

OP #

-

OP #

-

Condition
Code

Booleanl
Arithmetic
Operetion

Indexed

Extended (No Offset) (8·Bit Offset) (16·BitOffset)

Direct

H

I

X-M

a
a
a
a

5

A+M-.A

1\

4 D9 3

5

A+M+C-A

A

4 DO 3

5

A-M-A

a

•
•
•
•
•
•
•

2

4 D2 3

5

A-M-C-A

2

4 D4 3

5

A·M-A

•

1

3 EA 2

4 DA 3

5

A+M-A

a
a
a

F8

1

3 E8

2

4 D8 3

5

A+M-A

a

4

F1

1

3 E1

2

4 D1

3

5

A-M

4

F3

1

3

E3

2

4 D3 3

5

Add Memory and Carry

Subtract Memory from

2

A (Logical Compare)

BIT

2 B5 2

3 C5 3

4

F5

1

3

E5

2

4 D5 3

5

JMP

BC 2

2 CC 3

3 FC

1

2 EC

2

3 DC 3

4

Jump to Subroutine

JSR

BD 2

5 CD 3

6 FD

1

5 ED 2

5 DO 3

6

f,

1\

1\

1\

1\

a
a
a
a

1\

1\

1\

1\

1\

1\

1\

f,

1\

A

1\

1\

•

A

1\

a

a

•

I'

1\

1\

X-M

a

•

1\

1\

1\

A·M

a

Bit Test Memory with

Jump Unconditional

1\

1\

Arithmetic Compare X
with Memory

C

1\

1\

Arithmetic Compare A
with Memory

Z

1\

f,

Exclusive OR Memory
with A

N

•
•

f·

•
•

•
•
• • • • a
a • • • a
1\

f\

Symbols: Op = Operation
# = Number of bytes
- = Number of cycles

Table 6 Read/Modify/Write Instructions
Addressing Modes
Operations

) Mnemonic
I

Indexed
Implied(A)

Implied(X)

OP #

-

Increment

INC

4C

1

2 5C

OP #
1

-

Direct
OP #

2 3C 2

Indexed

(No Offset) (8·Bit Offset)

-

OP #

-

OP #

-

H

I

6

•
A-1-A or X-1-X or M-1-M
•
OO-A or OO-X or OO-M
•
A-A or x-X or M-M
•
OO-A-A or OO-X-X
or OO-M-M
•
orlI ~~
AOfi
•
I
I
I
II
I
Lb-t

•
•
•
•

5 7C

1

5 7A

1

5 6A 2

6

7F

1

5

6F

2

6

5 6C

2

Decrement

DEC

4A

1

2 5A

1

2 3A 2

Clear

CLR

4F

1

2

5F

1

2

Complement

COM

43

1

2

53

1

2 33 2

5 73

1

5 63

2

6

(2's Complement)

NEG

40

1

2

50

1

2 30 2

5 70

1

5 60

2

6

Rotate Left Thru Carry

ROL

49

1

2 59

1

2 39 2

5 79

1

5 69

2

6

Rotate Right Thru Carry

ROR

46

1

2 56

1

2 36

5 76

1

5 66

2

6

3F

2

5

Negate

2

A+1-A or X+1-X or M+1-M

L@:t I IAHor:MI I~~
C

Logical Shift Left

LSL

48

1

2 58

1

2 38 2

5 78

1

5 68

2

6

Logical Shift Right

LSR

44

1

2 54

1

2 34 2

5

74

1

5 64

2

6

Arithmetic Shift Right

ASR

47

1

2 57

1

2 37

2

5 77

1

5 67

2

6

Arithmetic Shift Left

ASL

48

1

2 58

1

~

38 2

5 78

1

5 68

2

6

TST

40

1

2 50 1

4 60 2

5

Test for Negative
orZaro

2 3D 2

4 70 1

186

~HITACHI

•

•
•
a

1~Of:Xr~ I I 1- 0• •
0, 1 IAH":MI I 1-0c • •
[?b'
:1 H.. ;":"I I ~ • •
Equal to LSL
• •
c

b,

[]-1

b,

Symbols: Op = Operation
# = Number of bytes
- - Number of cycles

Condition
Code

Booleanl Arithmetic Operation

N

Z

1\

1\

1\

f\

0

1

1\

1\

C

•
•
•
1

1\

1\

1\

1\

.~

.\

1\

1\

1\

1\

1\

1\

0

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

•

bo

bo

bo

A-OO ur X-OO or M-OO

C

• •

-----------------------------------------------HD6305Y2,HD63A05Y2,HD63B05Y2
Table 7 Branch Instructions
Addressing Modes
Operations

Mnemonic

Relative
OP

;;

-

Branch Always

BRA

20

2

3

None

Branch Never

BRN

21

2

3

None

Branch IF Higher

BHI

22

2

3

c+z=o

Branch IF Lower or Same

BlS

23

2

3

C+Z=1
C=O

(BlO)

25

2

Branch IF Not Equal

BNE

26

2

Branch IF Equal

BEQ

27

2

Branch IF Half Carry Clear

BHCC

28

2

Branch IF Half Carry Set

BHCS

29

2

Branch IF Plus

BPl

2A

2

Branch IF Minus

BMI

2B

2

3
3
3
3
3
3
3
3
3
3

BMC

2C

2

3

1=0

BMS

2D

2

3

1=1

Bil

2E

2

3

INT=O

Branch IF Carry Clear
(Branch IF Higher or Same)
Branch IF Carry Set
(Branch IF lower)

BCC

24

2

(BHS)

24

2

BCS

25

2

Condition Code

Branch Test

C=O
C=1
C=1
Z=O
Z=1
H=O
H=1
N=O
N=1

Branch IF Interrupt Mask
Bit is Clear
Branch IF Interrupt Mask
Bit is Set
Branch IF Interrupt Line
is Low
Branch IF Interrupt Line
is High

BIH

2F

2

3

INT=1

Branch to Subroutine

BSR

AD

2

5

--

H

I

N

Z

C

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •

•
•
•
•
•

•
•
•

•
•
•
•
•
•
• • • •
• • • •
• • • •
• • • •
• • • •

Symbols: Op = Operation
# = Number of bytes
- = Number of cycles

Table 8 Bit Manipulation Instructions

Operations
Branch IF Bit n is set
Branch IF Bit n is clear
Set Bit n
Clear Bit n

Addressing Modes
Bit Test and
Bit Set/Clear
OP
OP
:It BRSET n(n=0···7)
2·n
BRClR n(n=0···7)
01+2·n
-BSET n(n=0···7)
10+2·n 2 5
BClR n(n=0···7)
11+2·n 2 5
Mnemonic

Symbols: Op = Operation
# = Number of bytes
- = Number of cycles

~HITACHI

Booleanl
Branch Arithmetic
Operation
-

Branch
Test

:It
3
3

5
5

-

-

--

-

-

1--Mn
O--Mn

-

Mn=1
Mn=O
-

-

Condition Code
H

I

Z

C

•
•
•
•

• • •
• • • •

• • •

/\

N

/\

• • • •

187

HD6305Y2,HD63A05Y2,HD63B05Y2-------------_ _ _ _ _ _ _ __
Table 9

Control Instructions

Addressing Modes
Operations

Mnemonic

Implied

Condition Code

Boolean Operation

OP
97

#

-

1

X-A

Transfer A to X

TAX

Transfer X to A

TXA

9F

1

2
2

Set Carry Bit

SEC

99

1

1

1-C

Clear Carry Bit

CLC

98

1

1

O-C

Set Interrupt Mask Bit

SEI

9B

1

Clear Interrupt Mask Bit
Software Interrupt

CLI

9A

1

2
2

1-1
0-+1

SWI

83

1

10

Return from Subroutine

RTS

81

1

5

Return from Interrupt

RTI

80

1

8

Reset Stack Pointer

RSP

9C

1

2

$FF-SP

No-Operation

NOP

90

1

1

Advance Prog. Cntr. Only

Decimal Adjust A

OAA

80

1

2

Converts binary add of BCD charcters .nto
BCD format

STOP

8E

1

WAIT

8F

1

4
4

Stop
Wait
Symbols:

ap- Operation

A-X

H

I

•
•
•
•
•
•
•
•
?
•
•
•
•
•

•
•
•
•1

Z C

N

• • •
• • •1
• • 0
•
• • •
0 •
• •
1 •
• •
•? •? •? •?
• • • •
• • • •
•
• • • •
• • • •
.1

/\

/\

/\*

• Are BCD characters of upper byte 10 or more? (They are not cleared if sot in advance.!

# - Number of bytes
- Number of cycles

-

Table 10 Instruction Set (in Alphabetical Order)
Addressing Modes

Condition Code
Bit

Mnemonic
Implied

Immediate

Direct

x
x
x

x
x
x
x
x

ADC
ADD
AND
ASl
ASR

x
x

Extended Relative

x
x
x

Indexed

Indexed

Indexed

Set!

Test &

(No Offset)

(S·Bit)

(16·Bit)

Clear

Branch

x
x
x
x
x

x
x

X

/\

X

/\

x

x

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

x

x

x

BCC

x

BClR
BCS

x

BEQ

x
x

BHCC

BIH

x
x
x
x

Bil

x

BHCS
BHI
(BHS)

BIT

x

x

BL'S
BMC
BMS

x
x
x

BNE
BPl
BRA

188

x

x
x

BMI

Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero

x
x
x
x

(BlO)

Bit

x

x

H

•
•
•
•
•
•

I

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•

N

Z C

/\

/\

/\

/\

/\

/\

/\

•

/\

/\

/\

/\

/\

/\

/\

•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
/\

••

•
•
•
•
•
•
•
•
•
•
•
/\

•
•

•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

(to be continued)
C
/\

•?

Carry/Borrow
Test and Set if True. Cleared Otherwise
Not Affected
load CC Register From Stack

~HITACHI

~~~~~~~~~~~~~~~~~~~~~~-HD6305Y2.H~3A05Y2.HD63B05Y2

Table 10 Instruction Set (in Alphabetical Order)
Condition Code

Addressing Modes
Bit
Indexed

Mnemonic
Implied

Direct

Immediate

Extended Relative (No Offset)

Indexed

Indexed

Set!

Test &

(S-Bit)

(16-Bit)

Clear

Branch

H

I

N

Z

x
x

•
•
•
•

•
•
•
•
•
•0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•1
•
•
•
•1
•
•
•
•

•
•
•
•
•
•
•0

•
•
•
•
•
•
•1

x

BRN
BRCLR
BRSET

x

BSET

x
x
x

CLI
CLR

x
x
x

x

X

X

x

x
x

x

CMP

x

COM
CPX

I

x
x

DAA
DEC
EOR

i
i

!

x

I

I
i

JSR
LOX

!
•

,

x
x
x
x

LSL
LSR
NEG
NOP
ORA

I

RTI
i

RTS
SBC
SEC
SEI

x

x
x

ROR
RSP

x
x

i

I

ROL

!

I
I

X

x
x

TST
TXA
WAIT

X

X

X

X

X

x
x

x
x

X

X

x
x
x
x

x
x
x
x

X

X

x
x

x
x

x
x

x
x

X

X

X

x
x
x
x
x
x
x

x
x
x
x

x
x
x

X

x
x
x
x
x

x

I

I

x

i

x

x

x

x

x

x
x
x

x

x

x

x

x
x

x
x

x

x
x

x
x

x
x

SUB
TAX

x

I

STX
SWI

x
x
x

i

STA
STOP

x
x
x

I

JMP
LOA

•
•

x

BSR
CLC

INC

Bit

x
x
x
x
x

Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero

x

C
/\

•?

x

x

x

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•
•
•
•
•

C

•
/\
/\

•
•0
•
•

/\

/\

/\

/\

1

/\

/\

/\

/\

/\

/\

/\

•
•
•
• • •
• • •
•
•

/\

/\

/\

/\

1\

/\

/\

/\

/\

/\

/\

/\

0

/\

/\

/\

/\

/\

/\

• • •
•
/\

/\

/\

/\

/\

/\

/\

/\

•
?
•
•
•
•

•
?
•
•
•
•

•

/\

/\

?

•
/\

/\

1

/\

•
•
•
•

/\

/\-

/\

/\

/\

•
•
•
•

•
•
•
•

•
•
•
•

/\

/\

•

Carry IBorrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack

~HITACHI

189

HD6305Y2,HD63A05V2,HD63B05Y2---------------------------------------------Table 11 Operation Code Map
Bit Manipulation
Test &
Branch

Set/
Clear

0

1

Branch
Rei

DIR
3

BSETO

2
BRA

,

BRSETO
BRCLRO

BCLRO

SRN

2

BRSETl

BSET1

BHI

3
4

BRCLRl
BRSET2

BCLRl
BSET2

BLS
BCC

5

BRCLR2

BCLR2

BCS

6

BRSET3

BSET3

BNE
BEQ

0

Read/Modify/Write
A
4

X
5

.Xl
6

Control
.XO
7

IMP

8
RTI·

NEG

IMP IMM
9
A

SWI·

COM
LSR
ROR

-

CPX
AND

3
4

-

-

-

-

BIT

5

-

-

LOA

6
STA(+l) 7

BCLR4

ROL

-

BRSET5

BSET5

BPL

DEC

BRCLR5

BCLR5

BMI

C

BRSET6

BSET6

BMC

0

BRCLR6

BCLR6

BMS

E
F

BRSET7
BRCLR7

BSET7
BCLR7

BIL
BIH

3/5

2/5

2/3

(NOTES)

--

INC
TST(-l)

-

TST(-l)

TST
CLR

2/5

1/2

1/2

STA
EOR

-

SEC
cu*
SEI*
RSp·

ORA
ADD
JMP(-l)

--

DAA· NOP BSR·

JSR(+2)

2/6

1/5

1/"

1/1

2/3

L

o

W

A
B
C
JSR(+2) 0

JSR(+l)

LOX
2/2

HIGH

8
9

ADC

STOP' WAIT' TXA·

-

+--

0

SUB

1

CLC

-

.XO
F

2

TAX·

B

E

SBC

-

A

.Xl

0

CMP

-

BSET4

.X2

C

-

ASR

BCLR3

BRSET4
BRCLR4

EXT

B

RTS·
-

LSL/ASL

BRCLR3

DIR

-

BHCC
BHCS

7

8
9

Register /Memory

E
STX(+1) F
2/4 1/3

STX
3/4 I 3/5

1. "-" is an undefined operation code.

2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles).
The number of cycles for the mnemonics asterisked (0) is as follows:
ATI
8
TAX
2
ATS
5
ASP
2
SWI
10
TXA
2
DAA
2
BSA
5
STOP
4
ell
2
WAIT
4
SEI
2
3. The parenthesized numbers must be added to the cycle count of the particular instruction.

• Additional Instructions
The following new instructions are used on the HD630SY2:
DAA Converts the contents of the accumulator into BCD
code.
WAIT Causes the MPU to enter the wait mode. For this mode,
see the topic, Wait Mode.
STOP Causes the MPU to enter the stop mode. For this mode,
see the topic, Stop Mode.

•

OPERATION AT EACH INSTRUCTION CYCLE
The HD630SY2 employs a mechanism of the pipeline
control for the instruction fetch and the subsequent instruction
fetch is performed during the current instruction being executed.
Table 12 provides the information about the relationship
among each data on the Address Bus, Data Bus and R/W status
in cycle-by-cycle basis during the execution of each instruction.

Table 12 Cycle-by-Cycle Operation
Address Mode & Instructions

I Cycles ICycle # I

Address Bus

Data Bus

IMMEDIATE
ADC, ADD, AND,
BIT, CMP, CPX, EOR,
LOA, LOX, ORA,
SBC, SUB

2

1
2

Op Code Address +1
Op Code Address +2

1
1

Operand Data
Next Op Code

3

1
2
3

Op Code Address + 1
Address of Operand
Op Code Address +2

1
1
1

Address of Operand
Operand Data
Next OpCode

DIRECT
ADC, ADD, AND,
BIT, CMP, CPX,
EOR, LOA, LOX,
ORA, SBC, SUB

(to be continued)

190

~HITACHI

-----------------------------------------------HD6305Y2,HD63A05Y2,HD63B05Y2
Address Mode & Instructions I Cycles ICycle #
STA, STX

3

JMP

2

JSR

5

ASR, CLR, COM,
DEC, INC, LSL,
LSR, NEG, ROL,
ROR

5

TST

4

EXTENDED
ADC, ADD, AND,
BIT, CMP, CPX,
EOR, LOA, LDX,
ORA, SBC, SUB
STA, STX

4

4

JMP

3

JSR

6

Op Code Address +1

1

JMP
--

4

2

Address of Operand
( Data from Acc.
Data from Ix.
Next Op Code
Jump Address
Next Op Code
Jump Address (LSB)
Irrelevant Data
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Address of Operand
Operand Data
Irrelevant Data
New Operand Data
Next Op Code
Address of Operand
Operand Data
Irrelevant Data
Next Op Code

2

Address of Operand

0

3
1
2
1
2
3
4
5
1
2
3
4
5
1
2
3
4

Op Code Addre.ss +1
Op Code Address +1
Jump Address
Op Code Address +1
1FFF
Stack Pointer
Stack Pointer -1
Jump Address
Op Code Address +1
Address of Operand
1FFF
Address of Operand
Op Code Address +2
Op Code Address +1
Address of Operand
1FFF
Op Code Address +2

1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1

1
2
3
4
1
2

Op Code Address +1
Op Code Address +2
Address of Operand
Op Code Address +3
Op Code Address +1
Op Code Address +2

1
1
1
1
1
1

3

Address of Operand

0

4
1
2
3

Op Code Address +3
Op Code Address +1
Op Code Address +2
Jump Address
Op Code Address +1
Op Code Address +2
1FFF
Stack Pointer
Stack Pointer -1
Jump Address

1
1
1
1
1
1
1
0
0
1

Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
( Data from Acc.
Data from Ix.
Next Op Code
Jump Address (MSB)
Jump Address (LSB)
Next Op Code
Jump Address (MSB)
Jump Address (LSB)
Irrelevant Data
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code

3

Op Code Address +1
Ix
Op Code Address +1

1
1
1

Next OpCode
Operand Data
Next OpCode

1
2

Op Code Address +1
1FFF

1
1

3

Ix

0

4

Op Code Address +1
Op Code Address +1
Ix

1
1
1

Next OpCode
Irrelevant Data
( Data from Acc.
Data from Ix .
Next Op Code
Next Op Code
First Op Code of Jump Routine

1

6
3

Data Bus

Address Bus

1

2
3
4
5
INDEXED (No offset)
ADC, ADD, AND,
BIT, CMP, CPX,
EOR, LDA, LDX,
ORA, SBC, SUB
STA, STX

I

1
2

1
2

(to be continued)

~HITACHI

191

HD6305Y2,HD63A05Y2,HD63B05Y2~~~~~~~~~~~~~~~~~~~~~~

Address Bus

5

JSR

1
2

3
4
5
-ASR, CLR, COivi,
DEC, INC, LSL,
LSR, NEG, ROL,
ROR

S

TST

4

.

Op Code Address + 1
1FFF
Stack Pointer
Stack Pointer -1
Ix
,,_""_..J . . A-J..J ... _ ...... 11
\.I .... ,,",vue; ,",UUI'C';);) , I

R/W
1
1

0
0
1

1

Data Bus
Next Op Code
Irrelevant Data
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code

1

f\Jext Op Cede
Operand Data
I rrelevant Data
New Operand Data
Next Op Code

Op Code Address +1
Ix
1FFF
Op Code Address +1

1
1
1
1

Next Op Code
Operand Data
Irrelevant Data
Next Op Code

3
4

Op Code Address +1
1FFF
Ix + Offset
Op Code Address +2

1
1
1
1

Offset
I rrelevant Data
Operand Data
Next Op Code

1
2

Op Code Address +1
1FFF

1
1

I

2

3
4
5
1
2

3
4

Ix
1FFF
Ix
Op Code Address +1

1
1

0

INDEXED (8-bit offset)
ADC, ADD, AND,
BIT, CMP, CPX,
EOR, LOA, LDX,
ORA, SBC, SUB

4

STA,STX

4

3

JMP
---

JSR

.. -

1
2

3

Ix + Offset

0

4

Op Code Address +2

1

Offset
Irrelevant Data
( Data from Acc.
Data from I x .
Next Op Code

1
2

Op Code Address +1
1FFF
Ix + Offset

1
1
1

Offset
I rrelevant Data
First Op Code of Jump Routine

Op Code Address +1
1FFF
Stack Pointer
Stack Pointer-1
Ix + Offset

1
1

'Offset
Irrelevant Data
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code

3

..

5

1
2

3
4
5
ASR, CLR, COM,
DEC, INC, LSL,
LSR, NEG, ROL,
ROR

6

1
2

3
4
5
6

TST

5

1
2

3
4
5

0
0
1

1

Offset
Irrelevant Data
Operand Data
Irrelevant Data
New Operand Data
Next Op Code

Op Code Address +1
1FFF
Ix + Offset
1FFF
Op Code Address +2

1
1
1
1
1

Offset
I rrelevant Data
Operand Data
Irrelevant Data
Next Op Code

Op Code Address + 1
Op Code Address +2
1FFF
Ix + Offset
Op Code Address +1

1
1
1
1
1

Offset (MSB)
Offset (LSB)
Irrelevant Data
Operand Data
Next OpCode

Op Code Address + 1
1FFF
Ix + Offset
1FFF
Ix + Offset
Op Code Address + 1

1
1
1
1

0

IN DEXED (16-bit offset)
ADC, ADD, AND,
BIT, CMP, CPX,
EOR, LDA, LDX,
ORA, SBC, SUB

5

1
2

3
4
5

(to be continued)

192

~HITACHI

----------------------------------------------HD6305Y2,HD63A05Y2,HD63B05Y2
Address Bus

R/W

Data Bus

1

Offset (MSB)
Offset (lSB)
Irrelevant Data
( Data from Ace.
Data from Ix.
Next Op Code

JMP

4

1
2
3
4

Op Code Address +1
Op Code Address +2
1FFF
Ix + Offset

1
1
1
1

Offset (MSB)
Offset (lSB)
I rrelevant Data
First Op Code of Jump Routine

JSR

6

1
2
3
4

5
6

Op Code Address + 1
Op Code Address +2
1FFF
Stack Pointer
Stack Pointer -1
Ix + Offset

1
1
1
0
0
1

Offset (MSB)
Offset (lSB)
Irrelevant Data
Return Address (lSB)
Return Address (MSB)
First Subroutine Op Code

2

1
2

Op Code Address +1
Op Code Address +1

1
1

Next OpCode
Next Op Code

ClC, NOP, SEC

1

1

Op Code Address +1

1

Next Op Code

RSP, TAX, TXA

2

1
2

Op Code Address +1
Op Code Address + 1

1
1

Next Op Code
Next Op Code

ClI, SEI

2

1
2

1
1

Next Op Code
I rrelevant Data

DAA

2

1
2

Op Code Address +1
1FFF
Op Code Address +1
Op Code Address +1

1
1

Next Op Code
Next OpCode

STOP, WAIT

4

1
2
3
4

Op Code Address +1
1FFF
1FFF
Op Code Address +1

1
1
1
1

Next Op Code
Irrelevant Data
I rrelevant Data
Next Op Code

RTI

8

1
2
3
4
5
6
7

8

Op Code Address + 1
1FFF
Stack Pointer
Stack Pointer +1
Stack Pointer +2
Stack Pointer +3
Stack Pointer +4
Return Address

1
1
1
1
1
1
1
1

Next Op Code
Irrelevant Data
CC
Acc.
Ix.
Return Address (MSB)
Return Address (lSB)
First Op Code of Return Routine

RTS

5

1
2
3
4
5

Op Code Address +1
1FFF
Stack Pointer
Stack Pointer +1
Return Address

1
1
1
1
1

Next Op Code
Irrelevant Data
Return Address (MSB)
Return Address (lSB)
First Op Code of Return Routine

SWI

10

1
2
3
4

Op Code Address +1
1FfF
Stack Pointer
Stack Pointer-1
Stack Pointer-2
Stack Pointer-3
Stack Pointer-4
Vector Address 1 FFC
Vector Address 1 FFD
Address of SWI Routine

1
1
0
0
0
0
0
1
1
1

Next Op Code
Irrelevant Data
Return Address (lSB)
Return Address (MSB)
Ix.
Ace.
CC
Address of SWI Routine (MSB)
Address of SWI Routine (lSB)
First Op Code of SWI Routine
(to be continued)

STA, STX

5

Op Code Address +1
Op Code Address +2
1FFF

1
1
1

4

Ix + Offset

0

5

Op Code Address +3

1
2
3

IMPLIED
ASR,
DEC,
lSR,
ROR,

ClR, COM,
INC, lSl,
NEG, ROl,
TST

5
6
7

8
9
10

~HITACHI

193

HD6305Y2,HD63A05Y2,HD63B05Y2---------------------------------------------Address Bus

Address Mode & Instructions

----------------

R/W

Data Bus

1
1

Next OpCode
Irrelevant Data
First Op Code of Branch Routine
Next Op Code

--~~--~~--~--------------------------~----~------------------------

RELATIVE
BCC, BCS, BEQ,
BHCC, BHCS, BHI,
BIH, Bll, BlS,
BMC, BMI, BMS,
nr..lr8PL, BRA,
BRN

3

BSR

5

1
2
3

Op Code Address +1
lFFF
Branch Address ............. Test = "1"
Op Code Address +1 .... Test = "0"

(

I

(

1
I

Ol~c;.,

1
2
3

4
5

Op Code Address +1
lFFF
Stack Pointer
Stack Pointer-l
Branch Address

1
1

a
a
1

Offset
Irrel evant Data
Return Address (lSB)
Return Address (MSB)
First Op Code of Subroutine

BIT TEST AND BRANCH
BRClR, BRSET

5

1
2
3
4

5
BIT SET/CLEAR
BClR, BSET

5

1
2
3
4

5

194

Address of Operand
Operand Data
Offset
I rrelevant Data
First Op Code of Branch Address
Next OpCode

Op Code Address +1
Address of Operand
Op Code Address +2
lFFF
( Branch Address .............. Test ="1"
Op Code Address +3 ...... Test = "0"

1
1
1
1
1

(

Op Code Address +1
Address of Operand
lFFF
Address of Operand
Op Code Address +1

1
1
1
0
1

Address of Operand
Operand Data
Irrelevant Data
New Operand Data
Next Op Code

~HITACHI

H06800, H068AOO, H068BOO-

MPU

(Micro Processing Unit)

The HD6800 is a monolithic 8-bit' microprocessor forming
the central control function for Hitachi's HMCS6800 family.
Compatible with TTL, the HD6800 as with all HMCS6800
system parts, requires only one SV power supply. and no external TTL devices for bus interface. The HD68AOO and
HD68BOO are high speed versions.
The HD6800 is capable of addressing 6Sk bytes of memory with its 16-bit address lines. The 8-bit data bus is hi-directional as well as 3-state, making direct memory addressing and
multiprocessing applications realizable.
• FEATURES
• Versatile 72 Instruction - Variable Length (1~3 Byte)
• Seven Addressing Modes - Direct, Relative, Immediate,
Indexed, Extended, Implied and Accumulator
• Variable Length Stack
• Vectored Restart
• Maskable Interrupt
• Separate Non-Maskable Interrupt - Internal Registers Saved
in Stack
• Six Internal Registers - Two Accumulators, Index Register,
Program Counter, Stack Pointer and Condition Code Register
• Direct Memory Accessing (DMA) and Multiple Processor
Capability
• Clock Rates as High as 2.0 MHz
(HD6800'" 1 MHz,
HD68AOO ... 1.5 MHz, HD68BOO ... 2.0 MHz)
• Halt and Single Instruction Execution Capability
• Compatible with MC6800, MC68AOO and MC68BOO

HD6800P, HD68AOOP, HD68BOOP

(DP-40)
•

PIN ARRANGEMENT

NC
¢2
DBE

NC

RiW
Vee

Ao
A,

HD6800

A,

A,

•

A4

BLOCK DIAGRAM

A,
A,

A,s
25

1,1/>2
---------------Clock Input "Low" Voltage I 1/>1,1/>2
I

Output "High" Voltage

= OV, Ta = -20"'+75°C, unless otherwise noted.)

Symbol

VMA

V IH

i

V IL

I

I
I

0 0"'0 7

I Ao"'A 1S , R/W

I

Input Leakage Current

, 0 0"'0 7

~---.. -

-.!-0"'A 1S , R/W

Power Dissipation

0 0"'0 7
1/>1
Ao~AlS, R/W

VMA SA

Unit

Vee

V

-

0.8

V
V

-

V

-

V

2.4

-

-

V

2.4

-

-

V

-

-

0.4

V

-2.5

-

2.5

pA

-100

-

100

pA

-10

-

10

pA

-100

-

100

pA

PD

-

0.5

1.0

W

6.5

10

pF

Cin

-

pF

-

!

IOH = -205pA

:

' IOH = -145pA
IOH = -100pA

VOL

IOL = 1.6mA

lin

V in = 0"'5.25V,
All other pins are connected
to GNO

I TS1

I

Yin = 0.4 '" 2.4V

Yin = OV, Ta = 25°C,
f = 1 MHz

Cout

Yin = OV, Ta
f = 1 MHz

= 25

* Ta = 25°e, vee = 5V
** All. inputs except tP\ and tP,
*** All inputs except tP\ ,tP, and Do -0 7

196

max

-

-

I

~HITACHI

u

C,

V ee - 0.6!

typ*

2.4

i

I
I

1/>2

Output Capacitance

- 0.3

I

Logic***
Input Capacitance

I

!

Vee + 0.3
0.4

1/>1,1/>2

Three-State (Off-state)
Input Current

I

2.0

-

SA

Logic***

:
-+-

min

i

-0.3

V IHe
VILe

-; V
OH
I

Output"Low" Voltage

Test Condition
I

10

12.5

25

35

pF

45

70

pF

-

12

pF

---------------------------------------------------HD6800,HD68AOO,HD68BOO
•

AC CHARACTERISTICS

(Vee

= SV ± S%, Vss = OV, Ta = -20-+7SoC, unless otherwise noted.)

1. TIMING CHARACTERISTICS OF CLOCK PULSE CPl and CP2
Item

Symbol

Frequency of Operation

f

Cycle Time

tcyc
PW
I CPl , Lf----

Clock Pulse Width

CH1 ,

PWCH 2

HD68AOO

HD6800

Test
Condition

min
0.1

-

Fig. 10

1.000

-

Fig. 10

400

-

typ

max
1.0

0.1

-

4,500

Rise and Fall Tim:~. CP2

t r , tf

Fig. 10

-

-

100

td

Fig. 10

-

4,500

Clock "High" Level Time

tUT

Fig. 10

0
900

-

-

typ

10 0.666

Delay Time (Clock Internal)

--

min

230

0
600

-

HD68BOO
max
1.5

min
0.1

10 0.500
4,500
100
4,500
-

180

typ

Unit

max

--

2.0

-

10

ps

4,500

ns

--

MHz

-

-

100

ns

0
440

-

4,500

ns

-

-

-

ns

2 READIWRITE CHARACTERISTICS
Item

Symbol
C=90pF

Address Delay
Time

C=30pF

Data Setup Time (Read)

Test
Condition

max

min

typ

max

min

typ

Unit

max

tAOl

Fig.ll,
Fig. 12

-

-

270

-

-

180

-

-

150 : ns

t A02

Fig. 11,
Fig. 12

-

-

250

-

-

165

-

-

135

ns

tOSR

Fig. 11

100

-

-

60

-

-

40

-

-

ns

tacc

Fig. 11

-

-

530

-

-

360

-

-

250

ns

-

10

-

10

ns

-

20

-

-

20

-

-

ns

i

------ - -

Peripheral Read Access Time
tacc = tUT - (tAO + tOSR)

typ

HD68BOO

HD68AOO

HD6800
min

Input Data Hold Time

tH

Fig. 11

10

Output Data Hold Time

tH

Fig. 12

20

-

10

-

-

10

-

-

10

-

-

ns

450

-

-

280

-

-

220

-

-

ns

225

-

-

200

-

-

160

ns

-

ns

tAH

Fig. 11,
Fig. 12

Enable "High" Time for DBE
Input

tEH

Fig. 12

Data Delay Time (Write)

toow

Address Hold Time
(Address, R/IN, VMA)

---- -- -

- - - - - f-----

- - - - - - - -f---

Data Bus Enable Down Time
(During CPl Up Time)

~

tOBE

Fig. 12
-Fig. 12

-

-

150

-

-

120

-

-

75

-

300

-

-

250

-

-

180

-

-

ns

-

-

25

-

-

25

-

-

25

ns

140

-

-

110

-

-

ns

Data Bus Enable Delay Time

tOBEO

Fig. 12

Data Bus Enable
Rise and Fall Times

tOBEr
tOBEf

Fig. 12

Processor Control Setup Time

tpcs

200

-

-

Processor Control
Rise and Fall Times

tpcr
tpCf

-

-

100

-

-

100

-

-

100

ns

Bus Available Delay Time (BA)

tBA
t TSO

-

-

250

-

-

ns

270

-

135

270

-

165

-

220

ns

Three-State Delay Time

5.0V

Test Point

0--.............-

C

.....-

....

C = 130pF for 0 0 -0 7
= 90pF for Ao-A,s.R/W. and VMA
= 30pF for BA
R = 11k.!1 for 0 0 -0 7
= 16k.!1 for Ao-A". R/Wand VMA
= 24k.!1 for BA
C includes Stray Capacitance.
All diodes are 152074 (8) or equivalent.
Figure 1 Bus Timing Test Load

~HITACHI

197

HD6800,HD68AOO,HD68BOO-------------------------------------------------The Last Instruction Cycle

,--------\1

Halt Cycle

'"

SA

Figure 2 Timing of HALT and SA

Halt Cycle

-I-

Instruction Cycle

O.4V

SA

Figure 3 Timing of HALT and SA

MPU Reset

MPU Restart Sequence

-I-

\'--___1 06V\'---_---Jr
VCC

-

Vee - O.6V

RES

2.4V

VMA

Figure 4 RES and MPU Restart Sequence

198

~HITACHI

--------------------------------------------------HD6800,HD68AOO,HD68BOO
WAIT Cycle or
The Last Instruction Cycle

Interrupt Sequence

\~_-J/

\'--_----'r

Vcc - O.6V

(When WAIT Cycle)

BA

Figure 5 IRQ and NMI Interrupt Timing

.I.

.I

The last execution cycle of
WAI instruction (#9)

(/>'---.I----\~

WAIT Cycle

_____JI,....---\'_______r

\\.....--_5;::C-06VL
_tpc r

BA

Figure 6 WAI Instruction and BA Timing

PW CH , (4.5

J,lS

max)

TSC

A.-A,s
----+~""'"'.-.

R/W

VMA

v

BA

v

~ Indeterminate period

Figure 7 TSC Input and MPU Output

eHITACHI

199

HD6800,HD68AOO,HD68BOO--------------------------------------------------•

MPU REGISTERS

AddteuBus
tH)A.-A'1

The MPU provides several registers in Fig. 8, which is available for use by the programmer.
Each register is described below.
•

AddressBu5
IU Ao-A,

Program Counter (PC)

The program counter is a two byte (l6-bit) register that
points to the current program address.
•

Stack Pointer (SP)

The stack pointer is a two byte register that contains the
address of the next available location in an external push-down/
pop-up stack. This stack is normally a random access Read/
Write memory that may have any location (address) that is convenient. In those applications that require storage of information in the stack when power is lost, the stack must be nonvolatile.
•

Index Register (IX)

The index register is a two byte register that is used to store
data or a sixteen bit memory address for the Indexed mode of
memory addressing.
•

Accumulators (ACCA, ACCB)

The MPU contains two 8-bit accumulators that are used to
hold operands and results from an arithmetic logic unit (ALU).

7

I
I

0

7

15

I
I
I

Figure 9 Internal Block Diagram of MPU

Accumulator A

0
ACCB

•
Accumulator B

I
I
0

Index Register

•

0

15

,
11

PC

~

SP

7

0

H I N Z V C

-

I ~

~

MPU SIGNAt DESCRIPTION

Proper operations of the MPU requires that certain control
and timing signals (Fig. 9) be provided to accomplish specific
functions. The functions of pins are explained in this section.

0

IX

15

I
I

ACCA

Clock (1)2,1>2 )

Two pins are used to provide the clock signals. A two-phase
non-overlapping clock is provided as shown in Fig. 10.

Program Counter

I--------tcyc--------oi

Stack Pointer

~~~~~~~n Codes
Carry (From Bit 7)
Overflow
Zero
V IHC
VILC
VOv

Negative
Interrupt Mask

' - - - - - - Half Carry
(From Bit 3)

=
=
=

vcc - O.6V (min.)
VSS +O.4V (max.)
Vss + O.6V

Figure 10 Clock Timing Waveform

Figure 8 Programming Model of the Microprocessing
Unit
•
•

Condition Code Register (CCR)

The condition code register indicates the results of an Arithmetic Logic Unit operation: Negative (N), Zero (Z), Overflow
(V), Carry from bit 7 (C), and half carry from bit 3(H). These
bits of the Condition Code Register are used as testable conditions for the conditional branch instructions. Bit 4 is the
interrupt mask bit (I). The unused bits of the Condition Code
Register (b6 and b7) are" 1". The detail block diagram of the
microprossing unit is shown in Fig. 9.

200

$

Address Bus (A o "'A 1s )

Sixteen pins are used for the address bus. The outputs are
three-state bus drivers capable of driving one standard TTL load
and 90pF. When the output is turned off, it is essentially an
open circuit. This permits the MPU to be used in DMA applications. Putting TSC in its high state forces the Address bus to go
into the three-state mode.
•

Data Bus (0 0 "'0 7 )

Eight pins are used for the data bus. It is bidirectional,
transferring data to and from the memory and peripheral
devices. It also has three-state output buffers capable of driving
one standard TTL load and 130pF. Data Bus is placed in the
three-state mode when DBE is "Low."

HITACHI

----------------------------------------------------HD6800,HD68AOO,HD68BOO

~-----------------------tcyc----------------------~

1>,

Address~~~~~~~--~~-----------------------------------rt-~~

From
MPU

---+---------tacc----------~~

Data From
Memory or
Peripherals

2.0V --==-"J--~===j.~

------------------------------------~~
O.8V --=""".,t-=;;;:::::::~~

~'\01lndeterminate period
Figure 11 Read from Memory or Peripherals

Address

FromMPU~~~_F~~~--~t_--------_+--------------------------__+f~
VMA

~------------tEH------------~

Data
From MPU

Data Valid

Indeterminate period

Figure 12 Write to Memory or Peripherals

$

HITACHI

201

HD6800,HD68AOO,HD68BOO - - - - - - - - - - - - - - - - - - - - - - - - - •

Write ("Low") state. The normal standby state of this signal is
Read ("High"). Three-State Control going "High" will turn RjW
to the off (high impedance) state. Also, when the processor is
halted, it will be in the off state. This output is capable of
driving one standard TTL load and 90pF.

Data Bus Enable (DBE)

This input is the three-state control signal for the MPU data
bus and will enable the bus drivers when in the "High" state;will
make the bus driver off when in the "Low" state. This input is
TTL compatible; however in normal operation, it would be
driven by ct>2 clock. During an MPU read cycle, the data bus
drivers will be disabled internally. When it is desired that another device control the data bus such as in Direct Memory
Access (DMA) applications, DEE should be held "Low."
If additional data setup or hold time is required on an MPU
write, the DBE down time can be decreased as shown in Fig. 13
(DBE ~ rt>2)' The minimum down time for DBE is tDBE as
shown and must occur within ¢it up time. As for the characteristical values in Fig. 12, refer to the table of electrical characteristics.
•

•

Bus Available (BA)

The BA signal will normally be in the "Low" state. When
activated, it will go to the "High" state indicating that the
microprocessor has stopped and that the address bus is available. This will occur if the HALT line is in the "Low" state
or the processor is in the WAIT state as a result of the execution
of a WAIT instruction. At such time, all three-state output
drivers will go to their off state and other outputs to their
normally inactive level. The processor is removed from the
WAIT state by the occurrence of a maskable (mask bit I = 0) or
nonmaskable interrupt. This output is capable of driving one
standard TTL load and 30pF. If TSC is in the "High" state, Bus
Available will be "Low".
•

ReadlWrite (R/W)

This TTL compatible output signals the peripherals and
memory devices whether the MPU is in a Read ("High") or

5

1

6

I

7

I

Reset (RES)

The RES input is used to reset and start the MPU from a
power down condition resulting from a power failure or initial
stalt-up of the plocessol. Thls input can also be USed to ieinitialize the machine at any time after start-up.
If a "High" level is detected in this input, this will signal the
MPU to begin the reset sequence. During the reset sequence, the
contents of the last two locations (FFFE, FFFF) in memory
will be loaded into the Program Counter to point to the beginning of the reset routine. During the reset routine, the interrupt
mask bit is set and must be cleared under program control
before the MPU can be interrupted by IRQ. While RES is
"Low" (assuming a minimum of 8 clock cycles have occured)
the MPU output signals will be in the following states; VMA =
"Low", BA = "Low", Data Bus = high impedance, RjW= "High"
(read state), and the Address Bus will contain the reset address
FFFE. Fig. 13 illustrates a power up sequence using the Reset
control line. After the power supply reaches 4.75Y, a minimum
of eight clock cycles are required for the processor to stabilize
in preparation for restarting. During these eight cycles, YMA will
be in an indeterminate state so any devices that are enabled by
YMA which could accept a false write during this time (such as
a battery-backed RAM) must be disabled until VMA i~ forced
"Low" after eight cycles. RES can go "High" asynchronously
with the system clock any time after the eighth cycle.

8

9

1

1 n+ 1 1 n+2

I n+3 1 n~ 41

n-l 5

1SLJlJlSLJL
¢2
Power on
Switch
Power
Supply

II

j
---lJ 5 .25V
- - 4.75V

RES

----!)

Address
Bus

~;

R/W

=1

VMA
Data
Bus
BA

~;

~;
Restart Routine
Address Bits 8-15

~ = Indeterminate period

Figure 13 RES Timing

202

$

HITACHI

Restart Routi ne
Address Bits 0-7

Instruction of
Restart Routine

---------------------------------------------------HD6800,HD68AOO,HD68800
The Reset control line may also be used to reinitialize the
MPU system at any time during its operation. This is accomp·
lished by pulsing RES "Low" for the duration of a minimum of
three complete ,

Address

Bus
IROor
NMI

1M
Data

Bus

Inst (x)

R/W

PCO-PC7 PC8IXO-IX7 IX8PC15
IX15

ACCA

ACCB

New PCB-PC' 5 New PCO-PC7 First Inst of

CCR

Address

\~-----------------------------------'I

VMA

Address

Interrupt Routine

Figure 14 Interrupt Timing

I

I

I

I

I

I

I

I

Cycle Cycle CYCle, Cycle I Cycle Cycle ICYcle CYCle, Cycle I Wait C I CYcle, CYcle, Cycle Cycle Cycle Cycle
#2
#3
tt4
#5
,,6
tt7
tt8
#9
yce #n ttn+l ttn+2 #n+3 "n+4 "n+5

I #1

I

<1>,

,

Cycle

Address
Bus

Riw

Jl

it

1X

Instruction

I

I

X

I

I

I

(NOTE)
n ;n+l n+2

X

SPin! SPln-ll SPin 21 SPln-31 SPin 41 SPin 51 SPln-61

VMA

n+3

Cycle
n+4 #n+5

I
_FFF8-FFF9- New PC
Address

(NOTE) Midrange waveform indicates high impedance state.

Figure 15 WAI Instruction Timing

eHITACHI

203

HD6800,HD68AOO,HD68BOO------~------------------------------------------

the PC, IX, ACCX, and the CCR is already done.
While the MPU is waiting for the interrupt, Bus Available will
go "High" indicating the following states of the control lines:
VMA is "Low", and the Address Bus, R/W and Data Bus are all
in the high impedance state. After the interrupt occurs, it is
serviced as previously described.

•

Table 1 Memory Map for Interrupt Vectors
Vector
MS
FFFE

LS
FFFF

FFFC

FFFD

•

Description
Restart
Non·maskable Interrupt

FFFA

FFFB

Software Interrupt

FFF8

FFF9

Interrupt Request

Three State Control (TSC)

When the Three State ~ontrol (TSC) line is "High" level, the
Address Bus and the R/W line are placed in a high impedance
State. VMA and BA are forced "Low" when TSC = "High" to
prevent false reads or writes on any device enabled by VMA.
It is necessary to delay program execution while TSC is held
"High". This is done by insuring that no transitions of rPl (or
rP2) occur during this period. (Logic levels of the clocks are
irrelevant so long as they do not change.)
Since the MPU is a dynamic device, the rPl clock can be
stopped for a maximum time PW CH1 without destroying data
within the MPU. TSC then can be used in a short Direct Memory Access (DMA) application.
Fig. 16 shows the effect of TSC on the MPU. The Address
Bus and R/W line will reach the high impedance state at tTS D
(three-state delay), with VMA being forced "Low". In this
example, the Data Bus is also in the high impedance state while
rP2 is being held "Low" since DBE=rP2' At this point in time, a
DMA transfer could occur on cycles #3 and #4. When TSC is
returned "Low," the MPU address and R/W lines return to the
bus. Because it is too late in cycle #5 to access memory, this
cycle is dead and used for synchronization. Program execution
resumes in cycle #6.

Cycle
#1

#2

I

#3

I

#4

Halt (HALT)

\'lhcn this input is in the "Lo\v" state, all activity i...'1 the
machine will be halted. This input is level sensitive.
The HALT line provides an input to the MPU to allow control or program execution by an outside source. If HALT is
"High", the MPU will execute the instructions; if it is "Low",
the MPU will go to a halted or idle mode. A response signal,
Bus Available (BA) provides an indication of the current MPU
status. When BA is "Low", the MPU is in the process of executing the control program; if BA is "High", the MPU has halted
and all internal activity has stopped.
When BA is "High", the Address Bus, Data Bus, and R/W line
will be in a high impedance state, effectively removing the
MPU from the system bus. VMA is forced "Low" so that the
floating system bus will not activate any device on the bus that
is enabled by VMA.
While the MPU is halted, all program activity is stopped, and
if either an NMI or IRQ interrupt occurs, it will be latched into
the MPU and acted on as soon as the MPU is taken out of the
halted mode. If a RES command occurs while the MPU is
halted, the following states occur: VMA = "Low", BA = "Low",
Data Bus = high impedance, R/W = "High" (read state), and
the Address Bus will contain address FFFE as long as RES is
"Low". As soon as the RES" line goes "High", the MPU will
go to locations FFFE and FFFF for the address of the reset
routine.
Fig. 18 shows the' timing relationships involved when halting
the MPU. The instruction illustrated is a one byte, 2 cycle instruction such as CLRA. When HALT goes "Low", the MPU
will halt after completing execution of the current instruction.
The transition of HALT must occur tPCS before the trailing edge
of rPl of the last cycle of an instruction (point A of Fig. 18).
HALT must not go "Low" any time later than the minimum
tpcs specified.

Refer to Figure 18 for program flow for Interrupts.

•

Valid Memory Address (VMA)

This output indicates to peripheral devices that there is a
valid address on the address bus. In normal operation, this signal
should be utilized for enabling peripheral interfaces such as the
PIA and ACIA. This signal is not three-state. One standard TTL
load and 90pF may be directly driven by this active "High"
signal.

#5

I

#6

System
rP.
MPUrP.
Address
Bus
R/W
VMA

rPz

Data
Bus
DBE
TSC

Figure 16 TSC Control Timing

204

eHITACHI

#7

I

#8

---------------------------------------------------HD6800,HD68AOO,HD68BOO

y

IRQ
Ignored

,



",3 - 9

y
(FFFC) Fetch

IM=l
Reset

=<11

(~R~~

:;10

(FFF8) Fetch
",,11

IM=l
Reset

(~R~~

#12

#13

Figure 17 MPU Interrupt Flow Chart

$

HITACHI

205

H06800,H068AOO,H068BOO--------------------------------------------------

IP,

BA
VMA

R/W
Address
Bus

~~--~~~~--------~~S--------~I

WA>......(N.;.;;O;..;T-=E..:2~)"J.,-----
1///07>

nSf

V

M+1=1001, •• Y=CLRB(OP 5F)

Example: M=1 000, •• X=CLRA (OP 4F)

(NOTE)

1. Oblique lines indicate indeterminate range of data.
2. Midrange waveform indicates high impedance state.

Figure 18 HALT and Single Instruction Execution for System Dubug
Table 2 Operation States of MPU and Signal Outputs (Except the Execution of Instruction)
Halt and
Signals
Halt state
Reset state
WAI state
Reset state
"H"
"L"
BA
"L"
"H"
;'L"
VMA
"L"
"L"
"L"
"H"
"H"
RM
"T"
''T''
"T"
(FFFE) 16
"T"
(FFFElt6
Ao - Au
Do -D 7
"T"
"T"
"T"
"T"

TSC state
"L"
"L"

"T"
"T"

...

'T mdlcates high Impedance state •

The fetch of the OP code by the MPU is the first cycle of the
instruction. If HALT had not been "Low" at Point A but went
"Low" during cJ>z of the cycle, the MPU would have halted after
completion of the following instruciton. BA will go "High" by
time tBA (bus available delay time) after the last instruction
cycle. At this point in time, VMA is "Low" and R/W, Address
Bus, and the Data Bus are in the high impedance state.
To debug programs it is advantageous to step through programs instruction by instruction. To do this, HALT must be
brought "High" for one MPU cycle and then returned "Low" as
shown at point B of Fig. 18. Again, the transitions of HALT
must occur tPCS before the trailing edge of cJ>1' BA will go
"Low" at tBA after the leading edge of the next cJ>1 ,indicating
that the Address Bus, Data Bus, VMA and R/W lines are back
on the bus. A single byte, 2 cycle instruction such as LSR is
used for this example also. During the first cycle, the instruction
Y is fetched from address M+ 1. BA returns "High" at tBA on
the last cycle of the instruction indicating the MPU is off the
bus, if instruction Y had been three cycles, the width of the BA
"Low" time would have been increased by one cycle.
Table 2 shows the relation between the state of MPU and
signal outputs.

206

MPU INSTRUCTION SET
This Section will provide a brief introduction and discuss
their use in developing HD6800 MPU control programs. The
HD6800 MPU has a set of 72 different executable source
instructions. Included are binary and decimal arithmetic, logical,
shift, rotate, load, store, conditional or unconditional branch,
interrupt and stack manipulation instructions.
Each of the 72 executable instructions of the source language
assembles into 1 to 3 bytes of machine code. The number of
bytes depends on the particular instruction and on the addressing mode. (The addressing modes which are available for use
with the various executive instructions are discussed later.)
The coding of the first (or only) byte corresponding to an
executable instruction is sufficient to identify the instruction
and the addressing mode. The hexadecimal equivalents of the
binary codes, which result from the translation of the 72 instructions in all valid modes of addressing, are shown in Table 3.
There are 197 valid machine codes, 59 of the 256 possible codes
being unassigned.
When an instruction translates into two or tnree bytes of
code, the second byte, or second and third bytes contain(s) an
operand, an address, or information from which an address is
obtained during execution.
•

~HITACHI

- - - - - - - - - - - - - - - - - - - - - - - - - - HD6800,HD68AOO,HD68800
memory locations. In addition, the HD6800 MPU allow the
MPU to treat peripheral devices exactly like other memory
locations, hence, no I/O instructions as such are required. Because of these features, other classifications are more suitable
for introducing the HD6800's instruction set: (1) Accumulator and memory operations; (2) Program control operations;
(3) Condition Code Register operations.
For Accumulator and Memory Operations, refer to Table 4.

Microprocessor instructions are often devided into three
general classifications; (1) memory reference, so called because
they operate on specific memory locations; (2) operating instructions that function without needing a memory reference;
(3) I/O instructions for transferring data between the microprocessor and peripheral devices.
In many instances, the HD6800 MPU performs the same
operation on both its internal accumulators and the external

Table 3 Hexadecimal Values of Machine Codes

~
MSB

0

0
1

1
NOP
(IMP)

SBA
(A, B)

CBA
(A, B)
-~

2

3

·

·
·

4

5

6

7

.

TAP

[TPA

(~MP)
TAB

r---

BCS
(REL)

BNE
(REL)

,BEO
I (REL)

PUL
(A)

TXS
(IMP)

PSH
(A)

I

3

TSX
(IMP)

4

NEG
(A)

5

NEG
(B)

6

NEG
(lND)

·

7

NEG
(EXT)

·

8

~1~M)(A)i ~~~iA} ~1~CMiA)

9

~~I~)(A) f~~)(A) ~~I~)(A)

A

~I~~)(A) ~~~)(A)

SBC (A)
(lND)

·

AND (A)
(lND)

B

~~:T)(A)

~:~T)(A)

·

~E~~)(A) ~~:T)(A) ~~XAT)(A)

------

·

·
·

fEM:T)(A)
----- -

~1~BMiB) ~~~iB) ~I~CM)(B)

D

~~I~)(B} f~:)(B) ~~I~)(B)

E

~I~~)(B) ~~~)(B) ~I~~)(B)

F

~~:T)(B)

fEM:T)(B)

PUL
(B)

DES
(IMP)

COM
(A)

LSR
(A)

ROR
(A)

~:~T)(B)

1

~:)H

I (REL)

BVS
(REL)

I

RTS
(IMP)

! BVC

ASR
(A)

ASL
(A)

ROL
(A)

iASL
'(B)

ROL
I (B)

A
[CLV
(IMP)

.

ABA
(IMP)

·

·

i BPL
(REL)

DEC
(A)

ROR
(B)

ASR
(B)

ROR
(lND)

ASR
(lND)

ASL
(lND)

ROL
(lND)

DEC
(lND)

COM
(EXT)

LSR
(EXT)

ROR

ASR
(EXT)

ASL
(EXT)

ROL
(EXT)

DEC
(EXT)

~~~)(A) ~~~R) (A)I ~~~) (A)

~D~~)(B)

DEC
(B)

.

.

(A)
~1~~iA) ~~~)(A) ~:~iA) ADD
(lMM)
STA (A)
(DIR)

~~~)(A) ~~~)(A) 7D~~)(A)

~~D)(A) ~~~)(A) ~I:~)(A) ~I~~)(A) ~~~)(A) ~~~)(A)

·

BLT
(REU

·

INC
(A)

TST
(A)

INC
(B)

TST
-(B)

SEI
(IMP)
I

i
:BGT
I(REL)

i (REL)

WAI
(IMP)

'SWI
(IMP)

BLE

CLR
(A)

.

CLR
(B)

INC
(IND)

TST
(IND)

JMP
(lND)

CLR
(lND)

INC
, (EXT)

TST
(EXT)

JMP
(EXT)

CLR
(EXT)

CPX (A) BSR
(lMM)
(REL)

LDS
(lMM)

·

LDS
(DIR)

STS
I(DIR)

ADD (A) CPX (A) JSR
(lND)
(lND)
(IND)

LOS
(lND)

ISTS
I(lND)

~~~)(A)

LOS
(EXT)

STS
(EXT)

ADC (A)IORA (A)
(EXT)
(EXT)

EOR (B)
(lMM)

~~~)(B)' ~:~)(B) ~~~iB)

BIT
(B) LDA (B) STA (B) EOR (B)
(DIR)
(DIR)
(DIR)
(DIR)

~~~)(B) 7D~~)(B) ~~~)(B)

~~~)(B) ~I~D)(B) ~~~)(B) ~I:AD)(B) ~~~)(B) ~~~)(B) ~~~)(B) ~~~)(B)

DIR - D,rect Addressing Mode
EXT= Extended Addressing Mode
IMM= Immediate Addressing Mode

·

ADD (A) CPX (A)
(DIR)
(OIR)

~~:TiA)

STA (A)
(EXT)

BGE
(REL)

F

E
CLI
(IMP)

JSR
f::T)(A) (EXT)

~-

~~~iB) ~i~MiB) ~~~)(B)

·

, BMI
, (REL)
RTI
(IMP)

LSR
(lND)

~~~)(A) ~I~M)(A) ~~~)(A)

D
'SEC
(IMP)

LSR
(B)

·

C
CLC
(IMP)

COM
(B)

i (EXT)

B
SEV
(IMP)

COM
(lND)

- - -----------

C

.

DAA
(IMP)

(I~_MP)

BRA
(REL)

9
DEx
(IMP)

TBA

--- --BHI
BCC
BLS
(REL)
(REL)
(REU

2

INS
(IMP)

8
!INX
!(lMP)

~ENX~iB) ~~:T)(B) ~~xATiB) ~::TiB) ~~:T)(B) ~Dx~iB) 7ERX~)(B) ~E~~)(B)
IND - Index Addressing Mode
IMP = Implied Addressing Mode
REL= Relative Addressing Mode

LDX
(lMM)

·
·
·

!

~~~)(B) ~;I~)(B)

·

LDX
(IND)

STX
(lNO)

LDX
(EXT)

STX
(EXT)

A = Accumulator A
B = Accumulator B

~HITACHI

207

H06800,H068AOO,H068BOO-------------------------------------------------Table 4 Accumulator and Memory Operations
Cond. Code Reg.

Addressing Modes
Operation

Add
Add Acmltrs
Add with Carry
And
Bit Test
Clear

Compare
Compare Acmltrs
Complement, l's

Complement,2's
(Negate)
Decimal Adjust, A
Decrement

Exclusive OR
Increment

Load Acmltr
Or, Inclusive
Push Data
Pull Data
Rotate Left

Rotate Right

Shift Left, Arithmetic

Shift Right, Arithmetic

Sh itt Right, Logic

Store Acmltr
Subtract
Subtract Acmltrs
Subtr with Carry
Transfer Acmltrs
Test Zero or Minus

Mnemonic

ADDA
ADDB
ABA
ADCA
ADCB

ANDA
ANDB
BITA
BITB
CLR
CLRA
CLRB
CMPA
CMPB
CBA
COM
COMA
COMB
NEG
NEGA
NEGB
DAA
DEC
DECA
DECB
EORA
EORB
INC
INCA
INCB
LDAA
LDAB
ORAA
ORAB
PSHA
PSHB
PULA
PULB
ROL
ROLA
ROLB
ROR
RORA
RORB
ASL
AS LA
ASLB
ASR
ASRA
ASRB
LSR
LSRA
LSRB
STAA
STAB
SUBA
SUBB
SBA
SBCA
SBCB
TAB
TBA
TST
TSTA
TSTB

LEGEND:
OP Operation Code (Hexadecimal)
Number of MPU Cycles
#
Number of Program Bytes
Arithmetic Plus
+
Arithmetic Minus
Boolean AND
Msp Contents of memory location
pointed to be Stack Pointer

IMMED

DIRECT

'INDEx

EXTND

IMPLIED

OP - #

OP - #

OP - #

OP - #

OP - #

8B
CB

2
2

2
2

9B
DB

I" I' ;
89
C9

C4
85
C5

81
Cl

2
2

2
2
2

2
2

2
2

2
2

99
09

3
3

2
2

2191
2 01

5
5

3
3

2
2

2
2

86 2
C6 2
8A 2
CA 2

2
2

98
08

A+M~A

3
3

BB 14
FB 4

3 2
312
I
3
3

2
2

3
3

1
I
2 96 '3
2 06 3
2 9A 3
2 DA 3

2
2

21 B914
2 F9 4

3
3

A+M+C~A

5

,

3

/\, •

5
5
5
7

2
2
2
2

3
3
3
3

B· M~ B
A·M
B·M

E4
A5
E5
6F

Al
El

5
5

2
2

I

u-'

F4
B5
F5
7F

Bl
Fl

..

4
4
4
6

4
4

7

2

73

6

3

60

7

2

70

6

3

A8 5
E81,5
6C 7

2

2
2
2

7A

B8
F8
7C

6

A6
E6
AA
EA

5
5
5
5

7

2
2
2
2

2

B6
F6

79

4
4
4
4

6

2
2

1
1

11

2

1

43
53

2
2

1
1

40
50
19

2
2
2

4A
5A

2
2

3
3
3
4C
5C

!I"

7

2

76

6

3

68

7

2

78

6

3

67

7

2

77

6

3

64

7

2

74

6

3

80
CO
82
C2

2
2
2
2

2 92
2 02

3
3

2
2

A2
E2

60

+

Boolean Inclusive OR
Boolean Exclusive OR
1IiI Complement of M
Transfer Into
OBit = Zero
00
Byte = Zero

CB

6
6
5
5
5
5

7

2
2
2
2
2
2

2

B7
F7
BO
FO
B2
F2

70

5
5
4
4
4
4

6

2
2

li.~A
B"~B

M~B

4
4
4
4

1
1
1
1

49
59

2
2

1
1

46
56

2
2

1
1

3

66

A7
E7
AO
EO

B
A-M
B-M
A-B
M .... M

1 OO-A~A
1 OO-B .... B
1 Converts Binary Add of BCD
Characters into BCD Format
M-l ~M
1 A-l~A
1 B-1~B
A M, SP L -> (M + 1)
X -1 ..... SP
SP + 1 ..... X

(Bit N) Test: Sign bit of most significant (MS) byte of result = 1?
@ (Bit V) Test: 2's complement overflow from subtraction of ms bytes?
@ (Bit N) Test: Result less than zero? (Bit 15 = 1)

~HITACHI

5

4

3

2

1

0

H

I

N Z

V

C

··
·
·
·
·
·1·
··• ··• .'. ·· ..•
··· ·· • . • ··•
·• ·· · . · •

!.•

t @
• CD t

I·

•

t

@ t
@ t

•

@
@

t
t

T

R
R
R
R

•

209

H06800,H068AOO,H068BOO------------------------------____________________
MPU

MPU

ACCA

m-2

m-2

m-1

SP-m-1
New Data

SP-m
m+1

p~~~~~~~y
Data

7F

m+2
{

[ill

ACCA

63
1--------1
FD
m+3

Previously
Stacked
Data

m

F3

{ :::

7F

63

m+3

FD

PC----Next Instr.

PC-----

(a) Before PSHA

(b) After PSHA

Figure 19 Stack Operation (Push Instruction)
MPU

MPU

o

ACCA

ACCA

m-2

m-2

m-1

m-1
m

SP-m
1A
Previously {
Stacked
Data

m+1
m+2

3C

m+l

D5

1A

SP-m+1

P'~io","
Stacked
Data

EC

f

m+2

3C

m+3

05

l

~

PC-----

PULA
PC-

(b) After PULA

(a) Before PU LA

Figure 20 Stack Operation (Pull Instruction)

210

Next Instr.

_HITACHI

--------------------------------------------------HD6800,HD68AOO,HD68BOO

m-2

SP--m-2

m-1

m-1

SP---m

(n+2)H

m
7E

m+1

(n+2)L
7E

m+1

-7A

pc----- n

BSR

n+1

n+1

n+2

n+2

±K *

= Offset

Next Main I nstr.

*K = Signed 7-Bit Value
PC--(n+2) ± K

(a) Before Execution

(b) After Execution

Figure 21 Program Flow for BSR

.------

m-3

m-2

SP--m-2

m-1

m-1

SP---m

(n+3)H

m

(n+3)L

m+1

7E

m+1

7E

m+2

7A

m+2

7A

--

r--PC----n

-7D

. JSR

JSR = BD

n+1

SH

= Subr. Addr.

n+1

SH

n+2

SL

= Subr. Addr.

n+2

SL = Subr. Addr.

n+3

Next Main Instr.

n+3

Next Main Instr.

= Subr.

Addr.

-pc---S
(S formed from
SH and SL)
(b) After Execution

(al Before Execution

Figure 22 Program Flow for JSR (Extended)

$

HITACHI

211

m-2

SP-m-2

m-1

m-1

---

(n+2)H

m

SP---m
m+1

7E

(n+2)L
7E

m+1

-

7A

7A
~

PC-n
n+1

n+1

n+2

n+2

• K = 8-Bit Unsigned Value

PC--X"

+K

1st Subr. Instr .

• 'Contents of Index Register
(b) After Execution

(a) Before Execution

Figure 23 Program Flow for JSR (Indexed)

SP-m-2

m-2

---

m-1

(n+3)H

m-1

m

(n+3)L

SP---m

(n+3)L

m+1

----

7E

m+1

7A

7E

7A

~

JSR

(n+3)H

= BD

JSR = BD

n+1

SH

= Subr.

Addr.

n+1

SH

= Subr.

Addr.

n+2

SL

= Subr.

Addr.

n+2

SL

= Subr.

Addr.

n+3

Next Main Instr.

Pc-n+3

Next Main Instr.

P C - Sn

(b) After Execution

(a) Before Execution

Figure 24 Program Flow for RTS

212

$

HITACHI

--------------·-------------------------------------HD6800,HD68AOO,HD68BOO
Wait for
Interrupt
Main Program

Software Interrupt
Main Program

Hardware Interrupt or
Non-Maskable Interrupt (NMI)
Main Program

n+1

Yes

Stack
SP--. m-7

c::::>

m-6

Condition Code

m-5

Acmltr. B

m-4

Acmltr. A

m-3

Index Register (XH)

m-2

Index Register (XL!

m-1

PC(n+1 )H

m

PC(n+1 )L

HDWR
INT

SWI

No

FFF8
FFF9

Interrupt Memory Assignment
FFF8

Hardware Int.

MS

FFF9

Hardware Int.
Software

MS

Software

LS

FFFA
FFFB

LS

FFFC

Non-Maskable Int. MS

FFFD
FFFE

Non-Maskable Int.
Restart

MS

FFFF

Restart

LS

(NOTE)

c::::>

LS

First Instr.
Addr. Formed
By Fetching
2-Bytes From
Per. Mem.
Assign.

MS = Most Significant Address Byte
LS = Least Significant Address Byte

Figure 25 Program Flow for Interrupts

~HITACHI

213

HD6800,HD68AOO,HD68BOO - - - - - - - - - - - - - - - - - - - - - - - - -

SP-m-7

m-7

m-6

CCR

m-6

CCR

m-5

ACCB

m-5

ACCB

m-4

ACCA

m-4

ACCA

m-3

XH (Index Reg)

m-3

XH

m-2

XL (Index Reg)

m-2

XL

m-1

PC(n+1)H

m-1

PCH

m

PC(n+1)l

SP-m

PCl

L2:..---n+1

-

~

PC----n+1

Next Main Instr.

last Inter. Inst.

last Inter. Instr.

Pc-Sn

-

Sn

RTI

(a) Before Execution

RTI

...--------1
(b) After Execution

Figure 26 Program Flow for RTI

•

Jump and Branch Operation

The Jump and Branch instructions are summarized in Table
6. These instructions are used'to control the transfer of opera·
tion from one point to another in the control program.
The No Operation instruction, NOP, while included here,
is a jump operation in a very limited sense. Its only effect is to
increment the Program Counter by one. It is useful during
program development as a "stand-in" for some other instruction that is to be determined during debug. It is also used for
equalizing the execution time through alternate paths in a con·
trol program.
Execution of the Jump Instruction, JMP, and Branch Always,
BRA, affects program flow as shown in Fig. 27. When the MPU
encounters the Jump (Index) instruction, it adds the offset to
the value in the Index Register and uses the result as the address
of the next instruction to be executed. In the extended addressing mode, the address of the next instruction to be executed is
fetched from the two locations immediately following the JMP
instruction. The Branch Always (BRA) instruction is similar to
the JMP (extended) instruction except that the relative addressing mode applies and the branch is limited to the range within
-125 or +127 bytes of the branch instruction itself. The opcode
for the BRA instruction requires one less byte than JMP (extended) but takes one more cycle to execute.
The effect on program flow for the Jump to Subroutine
(JSR) and Branch to Subroutine (BSR) is shown in Figs. 21
through 23. Note that the Program Counter is properly in-

214

cremented to be pointing at the correct return address before
it is stacked. Operation of the Branch to Subroutine and Jump
to Subroutine (extended) instruction is similar except for the
range. The BSR instruction requires less opcode than JSR (2
bytes versus 3 bytes) and also executes one cycle faster than
JSR. The Return from Subroutine, RTS, is used at the end of
a subroutine to return to the main program as indicated in Fig.
24.
The effect of executing the Software Interrupt, SWI, and the
Wait for Interrupt, WAI, and their relationship to the hardware
interrupts is shown in Fig. 25. SWI causes the MPU contents to
be stacked and then fetches the starting address of the interrupt
routine from the memory locations that respond to the addresses FFF A and FFFB. Note that as in the case of the subroutine instructions, the Program Counter is incremented to
point at the correct return address before being stacked. The
Return from Interrupt instruction, RTI, (Fig. 26) is used at the
end of an interrupt routine to restore' controi to the main
program. The SWI instruction is useful for inserting break points
in the control program, that is, it can be used to stop operation
and put the MPU registers in memory where they can be examined. The WAI instruction is used to decrease the time
required to service a hardware interrupt; it stacks the MPU
contents and then waits for the interrupt to occur, effectively
removing the stacking time from a hardware interrupt sequence.

_HITACHI

--------------------------------------------------HD6800,HD68AOO,HD68BOO
Table 6 JUMP/BRANCH Instruction
Condo Code Reg.

Addressing Modes
-------r------j

Mnemonic

Operation

Branch Always
Branch If Carry Clear
Branch If Carry Set
Branch If = Zero
Branch If ~ Zero
Branch If> Zero
Branch If Higher
Branch If ~ Zero
Branch If lower Or Same
Branch If < Zero
Branch If Minus
Branch If Not Equal Zero
Branch If Overflow Clear
Branch If Overflow Set
Branch If Plus
Branch To Subroutine
Jump
Jump To Subroutine
No Operation
Return From Interrupt
Return From Subroutine
Software Interrupt
Wait for Interrupt

CD
@

BRA
BCC
BCS
BEQ
BGE
BGT
BHI
BlE
BlS
BlT
BMI
BNE
BVC
BVS
BPl
BSR
JMP
JSR
NOP
RTI
RTS
SWI
WAI

(All)
(Bit I)

OP

-

#

20
24
25
27
2C
2E
22
2F
23

4
4
4
4
4
4
4
4
4

2
2
2
2
2
2
2
2
2

20 4

2

2B
26
28

4
4
4

2
2
2

29

4

2

2A

4

2

80 8

2

OP

-

IMPLIED!

EXTND
#

lOp

-

it

OP

-

i

i

2
2

7E 3
BD 9

1
1

39

1

5

3F 12
3E 9

210

NZ

VC

··• ..• •• !.i. .\• .•
··· ... ... ... ..· ..
·· .. .. .. .. ..
• i_

.1 •

· ....
·· .. ··• ..•
·. .. ..
• i.

\.

•

•

•

• i· • •

•

3
3
01 2
3B 10

4!3

• .!.:. • •

None
C=O
C=1
Z = 1
N<±)V=O
Z + (N @ V) = 0
C+Z=O
Z + (N <±) V) = 1
C+Z=1
N eV= 1
N= 1
Z=O
V=O
V = 1
N=O

I

5

HII

#
I

i

Branch Test

Advances Prog Cntr Only

•

• •

i •

· · · .1+.
•

•

•

•

•

•

•

•

•

I •

1

•

i •

1

t---

CD

:

• •

• • • • I· •

:~::I:I:

1
1

load Condition Code Register from Stack. (See Special Operations)
Set when interrupt occurs. If previously set, a Non-Maskable interrupt is required to exit
the wait state.

PC

Main Program

PC

6E = JMP

{"

K = Offset

n+1

INDXD

INDEX

RELATIVE

EXTND
Next Instruction

X+K

{"

Main Program

n+1

KH ; Next Address

n+2

KL = Next Address

K

Main Program

7E = JMP

.

20 = BRA
n+1

(n+2) :t K

K* = Offset

I

Next Instruction

INext Inst;uction
*K = Signed 7-bit value
(b) Branch

(a) Jump

Figure 27 Program Flow for JUMP/BRANCH Instructions

BMI
BPl

N= 1;
N = 0;

BEQ
BNE

Z= 1 ;
Z=o;

BVC
BVS

V=0 ;
V= 1;

BCC
BCS

C=0 ;
C= 1 ;

BHI
BlS

C+Z= 0 ;
C+Z=1;

BL T
BGE

N ® V =1;
N(±)V=O;

BLE
BGT

0
0

:
:

Z + (N
Z + (N

V) = 1 ;
V) = 0 ;

Figure 28 Conditional Branch Instructions

The conditional branch instructions, Fig. 28, consists of
seven pairs of complementary instructions. They are used to
test the results of the preceding operation and either continue
with the next instruction in sequence (test fails) or cause a
branch to another point in the program (test succeeds).
Four of the pairs are used for simple tests of status bits N,
Z, V,and C:
1. Branch on Minus (BMI) and Branch On Plus (BPL) tests the
sign bit, N, to determine if the previous result was negative or
positive, respectively.
2. Branch On Equal (BEQ) and Branch On Not Equal (BNE)
are used to test the zero status bit, Z, to determine whether
or not the result of the previous operation was equal to "0".
These two instructions are useful following a Compare (CMP)
instruction to test for equality between an accumulator and
the operand. They are also used following the Bit Test (BIT)
to determine whether or not the same bit positions are set in
an accumulator and the operand_

~HITACHI

215

HD6800,HD68AOO,HD68BOO-------------------------------------------------3. Branch On Overflow Clear (BVC) and Branch On Overflow
Set (BVS) tests the state of the V bit to determine if the
previous operation caused an arithmetic overflow.
4. Branch On Carry Clear (BCC) and Branch On Carry Set
(BCS) tests the state of the C bit to determine if the previous
operation caused a carry to occur. BCC and BCS are useful
for testing relative magnitude when the values being tested
are regarded as unsigned binary numbers, that is, the values
are in t.he range "00" (lowest) of "FF" (!'>Jg.l-test). BCC
following a comparison (CMP) will cause a branch if the
(unsigned) value in the accumulator is higher than or the
same as the value of the operand. Conversely, BCS will cause
a branch if the accumulator value is lower than the operand.
The Fifth complementary pair, Branch On Higher (BHI)
and Branch On Lower or Same (BLS) are in a sense comple·
ments to BCC and BCS. BHI tests for both C and Z = "0", if
used following a CMP, it will cause a branch if the value in the
accumulator is higher than the operand. Conversely, BLS will
cause a branch if the unsigned binary value in the accumulator
is lower than or the same as the operand.
The remaining two pairs are useful in testing results of opera·
tions in which the values are regarded as signed two's comple·
ment numbers. This differs from the unsigned binary case in the
following sense: In unsigned, the orientation is higher or lower;
in signed two's complement, the comparison is between larger
or smaller where the range of values is between -128 and +127.
Branch On Less Than Zero (BLT) and Branch On Greater
Than Or Equal Zero (BGE) test the status bits for N (f)V = "1"
and N (f) V = "0", respectively. BLT will always cause a branch
following an operation in which two negative numbers were
added. In addition, it will cause a branch following a CMP in
which the value in the accumulator was negative and the oper·
and was positive. BLT will never cause a branch following a
CMP in which the accumulator value was positive and the
operand negative. BGE, the complement to BLT, will cause a
branch following operations in which two positive values
were added or in which the result was "0".
The last pair, Branch On Less Than Or Equal Zero (BLE) and
Branch On Greater Than Zero (BGT) test the status bits for
Z (f) (N + V) = "I" and Z (f)(N + V) = "0", respectively,
The action of BLE is identical to that for BLT except that a
branch will also occur if the result of the previous result was
"0". Conversely, BGT is similar to BGE except that no branch
will occur following a "0" result.

•

CONDITION CODE REGISTER OPERATIONS
The Condition Code Register (CCR) is a 6·bit register within
the MPU that is useful in controlling program flow during sys·
tern operation. The bits are defined in Fig. 29.
The instructions shown in Table 7 are available to the user
for direct manipulation of the CCR. In addition, the MPU auto·
matically sets or clears the appropriate status bits as many of
the other instructions on the condition code register was in·
dicated as they were introduced.
Systems which require an interrupt window to be opened
under program control should use a CLI·NOP·SEI sequence
rather than CLI·SEI.
b5

b4

H

b3

b2

bl

bO

N

z

v

C

H = Half·carry; set whenever a carry from b3 to b4 of the result is
generated by ADD, ABA, ADC; cleared if no b3 to b4
carry; not affected by other instructions.
Interrupt Mask; set by hardware of software interrupt or SEI
instruction; cleared by CLI instruction. (Normally not used
in arithmetic operations,) Restored to a "0" as a result of an
RTI instruction if 1M stored on the stacked is "0"
N

=

Negative; set if high order bit (b7) of result is set; cleared
otherwise.

Z = Zero; set if result = "0"; cleared otherwise.
V = Overflow; set if there was arithmetic overflow as a result of
the operation; cleared otherwise.
C = Carry; set if there was a carry from the most significant bit
(b7) of the result; cleared otherwise.

Figure 29 Condition Code Register Bit Definition

• ADDRESSING MODES
The MPlJ operates on 8·bit binary numbers presented to it
via the Data Bus. A given number (byte) may represent either
data or an instruction to be executed, depending on where it is
encountered in the control program. The HD6800 MPU has
72 unique instructions, however, it recognizes and takes action
on 197 of the 256 possibilities that can occur using an 8·bit
word length. This larger number of instructions results from the
fact that many of the executive instructions have more than
one addressing mode.

Table 7 Condition Code Register Instructions

Operations

Mnemonic

Addressing
Mode
IMPLIED
OP

Clear Carry
Clear Interrupt Mask
Clear Overflow
Set Carry
Set Interrupt Mask
Set Overflow
Acmltr A - CCR
CCR ..... Acmltr A

CLC
CLI
CLV
SEC
SEI
SEV
TAP
TPA

OC
OE
OA
00
OF
OB
06
07

2
2

2
2
2
2
2
2

Condo Code Reg.
Boolean Operation

R = Reset
S = Set
- = Not affected
CD (ALL) Set according to the contents of Accumulator A.

216

_HITACHI

r----H

#

1
1
1
1
1
1
1
1

5

0 ..... C
0 ..... I
0 ..... V
1 ..... C
1 ..... I
1 ..... V
A ..... CCR
CCR ..... A

4
I-~

I

32T~

-N-zi

V

C

-- - -- -- -- .
-- -- -- -- - -- - -- -- - -R

R

R

S

S

S

CD

-\-1-1-1-\-

These addressing modes refer to the manner in which the
program causes the MPU to obtain its instructions and data.
The programmer must have a method for addressing the MPU's
internal registers and all of the external memory locations.
Selection of the desired addressing mode is made by the user
as the source statements are written. Translation into appropriate opcode then depends on the method used. If manual translation is used, the addressing mode is implied in the opcode.
For example, the Immediate, Direct, Indexed, and Extended
modes may all be used with the ADD instruction. The proper
mode is determined by selecting (hexidecimal notation) 8B,
9B, AB, or BB, respectively.
The source statement fonnat includes adequate information
for the selection if an assembler program is used to generate the
opcode. For instance, the Immediate mode is selected by the

DO Instruction

Direct:
Example: SUBB Z
Addr. Range = 0~255

&

n+1

Z

=Operand Address

n+2

Assembler whenever it encounters the "#" symbol in the
operand field. Similarly, an "X" in the operand field causes the
Indexed mode to be selected. Only the Relative mode applies
to the branch instructions, therefore, 'the nmemonic instruction itself is enough for the Assembler to determine addressing
mode.
For the instructions that use both Direct and Extended
modes, the Assembler selects the Direct mode if the operand
value is in the range 0-255 and Extended otherwise. There are
a number of instructions for which the Extended mode is
valid but the Direct is not. For these instructions, the Assembler
automatically selects the Extended mode even if the operand is
in the 0-255 range. The addressing modes are summarized in
Fig. 30.

Immediate:

Instruction

Example: LDAA ttK
(K = One-Byte Operand)

n+1

K = Operand

n+2

Next Inst.

Next Instr.

OR

•
•
•
(K

= One-Byte Operand)

= Operand

K

Z

Instruction

(K = Two-Byte Operand)
(CPX. LDX and LDS)

= Two-Byte

Operand)

Z

KH

Z+1

KH = Operand
KL

= Operand

KL = Operand
Instruction

Relative:

&

= Operand

Next Instr.

n+3

OR
(K

n+1
n+2

If Z ~ 255, Assembler Select Direct Mode
If Z> 255, Extended Mode is selected

Example: BNE K
(K

= Signed

n+1

7-Bit Value)

n+2

±K

= Branch

Offset

Next Instr.,&

Addr. Range:
-125 to +129
Relative to n.

•

FO Instruction

Extended:

= Operand Address

Example: CMPA Z

n+1

ZH

Addr_ Range:

n+2

ZL = Operand Address

n+3

Next Instr.

&

256~65535

(n+2)±K

&

If Branch Test False,

&.

(K = One-Byte Operand)

Z

K

= Operand

Instruction

= Two-Byte

Operand)

Z
Z+1

KH

= Offset

Example: ADDA Z. X

n+1

Z

Addr. Range:
Relative to
Index Register, X

n+2

Next Instr.

0~255

•
•

OR
(K

&

If Branch Test True.

Indexed:

•
•

Next Instr.

= Operand

KL = Operand

(Z = 8-Bit Unsigned Value)

X+Z

IL.-__K_=_o_p_e_r_an_d_ _--'

Figure 30 Addressing Mode Summary

~HITACHI

217

Implied (Includes "Accumulator Addressing" Mode)
The successive fields in a statement are normally separated
by one or more spaces. An exception to this rule occurs for instructions that use dual addressing in the operand field and for
instructions that must distinguish between the two accumulators. In these cases, A and B are "operands" but the space
between them and the operator may be omitted. This is commonly done, resulting in apparent four character mnemonics
for those instructions.
The addition instruction, ADD, provides an example of dual
addressing in the operand fields;
Operator Operand
ADDA
or ADDS

MPU

MPU

•

~
Eif=
Program
Memory

RAM

R

I

Comment

MEM12
MEM12

ADD CONTENTS OF MEM12 TO ACCA
ADD CONTENTS OF MEM12 TO ACCS
PC

1'----1"

The example used earlier for the test instruction, TST, also
applies to the accumulators and uses the "accumulator addressing mode" to designate which of the two accumulators is being
tested:
Operator
TSTS
or TSTA

General Flow

Figure 32 Accumulator Addressing

Comment
TEST CONTENTS OF ACCS
TEST CONTENTS OF ACCA

•

A number of the instructions either alone or together with
an accumulator operand contain all of the address information
that is required, that is, "inherent" in the instruction, itself.
For instance, the instruction ABA causes the MPU to add the
contents of accumulators A and B together and place the result
in accumulator A. The instruction INCB, another example of
"accumulator addressing", causes the contents of accumulator
B to be increased by one. Similarly, INX, increment the Index
Register, causes the contents of the Index Register to be increased by one.
Program flow for instructions of this type is illustrated in
Figures 31 and 32. In these figures, the general case is shown
on the left and a specific example is shown on the right.
Numerical examples are in decimal notation. Instructions of this
type require only one byte of opcode. CycIe-by-cycIe operation
of the implied mode is shown in Table 8.
MPU

MPU

Example

Immediate Addressing Mode
In the Immediate addressing mode, the operand is the value
that is to be operated on. For instance, the instruction
Operator

Operand

LDAA

#25

Comment
LOAD 25 INTO ACCA

causes the MPU to "immediately load accumulator A with the
value 25"; no further address reference is required. The Immediate mode is selected by preceding the operand value with
the "#" symbol. Program flow for this addressing mode is
illustrated in Fig. 33.
The operand format allows either properly defined symbols
or numerical values. Except for the instructions ('PX, LDX, and
LDS, the operand may be any value in the range 0 ~ 255. Since
Compare Index Register (CPX), Load Index Register (LDX),
Load Stack Pointer (LDS), require 16-bit values, the immediate
mode for these three instructions requie two-byte operands.
Table 9 shows the cycIe-by-cycIe operation for the immediate addressing mode.

RAM
RAM

PC

J-. -:. .: :. :. :. :. .f'~r- 5~
..... PC -

General Flow

f

Program
Memory

I

PC

1-=-:-=-:---11/

General Flow

Example

PC = 5002 ......,:==..:..;...;~/

Example

Figure 33 Immediate Addressing Mode

Figure 31 Implied Addressing

218

Program
Memory

_HITACHI

- - - - - - - - - - - - - - - - - - - - - - - - HD6800,HD68AOO,HD68BOO
Table 8 Implied Mode Cycle by Cycle Operation
Address Mode
and Instructions
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM
DES
DEX
INS
INX

DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA

SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST

Cycle

Cycle
'+

VMA
Line

Address Bus

R/W

Data Bus

Line

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Op Code of Next Instruction

4

1
2
3
4

1
1
0
0

Op Code Address
Op Code Address + 1
Previous Register Contents
New Register Contents

1
1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)

4

1
2
3
4

1
1
1
0

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1

1
1
0
1

Op Code
Op Code of Next Instruction
Accumulator Data
Accumulator Data

4

1
2
3
4

1
1
0
1

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1

1
1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data (NOTE 1)
Operand Data from Stack

1

1
1
0
0

Op Code Address
Op Code Address + 1
Stack Pointer
New Index Register

1
1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)

3
4

1
1
0
0

Op Code Address
Op Code Address + 1
I ndex Register
New Stack Pointer

1
1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data
Irrelevant Data

1
2
3
4
5

1
1
0
1
1

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2

1
1
1
1
1

Op Code
Irrelevant Data (NOTE 2)
Irrelevant Data (NOTE 1)
Address of Next Instruction (High Order Byte)
Address of Next Instruction (Low Order Byte)

1
2
3
4
5
6
7

1
1
1
1
1
1
1
1
1

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6 (NOTE 3)

1
1
0
0
0
0
0
0
1

Op Code
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Cond. Code Register

8
9

1
1
0
1
1
1
1
1
1

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer + 4
Stack Pointer + 5
Stack Pointer + 6

1
1
1
1
1
1
1
1
1

10

1

Stack Pointer + 7

1

Op Code
Irrelevant Data (NOTE 2)
Irrelevant Data (NOTE 1)
Contents of Cond. Code Register from Stack
Contents of Accumulator B from Stack
Contents of Accumulator A from Stack
Index Register from Stack (High Order Byte)
Index Register from Stack (Low Order Byte)
Next Instruction Address from Stack
(High Order Byte)
Next Instruction Address from Stack
(Low Order Byte)

1
2
3
4
5
6
7

1
1
1
1
1
1
1
1
1
0
1
1

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Stack Pointer - 7
Vector Address FFFA (Hex)
Vector Address FFFB (Hex)

1
1
0
0
0
0
0
0
0
1
1
1

2

PSH

PUL

TSX
4

TXS

2
3
4
1

4

RTS
5

WAI

9

2

8
9
RTI

10

SWI

12

1
2
3
4
5
6
7

8
9
10
11
12

Op Code
Irrelevant Data (NOTE 1)
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data (NOTE 1)
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)

If deVice which IS addressed dUring thiS cycle uses VMA, then the Data Bus Will go to the high Impedance three·state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.
NOTE 2. Data is ignored by the MPU.
NOTE 3. While ~e MPU is waiting for the interrupt, Bus Available will go "High" indicating the following states of the control lines: VMA is "Low"; Address
Bus,R/W, and Data Bus are all in the high impedance state.

NOTE 1.

$

HITACHI

219

HD6800,HD68AOO,HD68BOO - - - - - - - - - - - - - - - - - - - - - - - Table 9 Immediate Mode Cycle by Cycle Operation
Address Mode
and Instructions

Cycle

EaR
LOA
ORA
SBC
SUB

2

ADC
ADD
AND
BIT
CMP
CPX
LOS
LOX

3

Cycle
#"

VMA
Line

1
2

1
1

OP Code Address
Op Code Address + 1

1
1

Op Code
Operand Data

1
2
3

1
1
1

OP Code Address
OP Code Address + 1
Op Code Address + 2

1
1
1

00 Code
OPerand Data (High Order Byte)
Operand Data (Low Order Byte)

Address Bus

• Direct and Extended Addressing Modes
In the Direct and Extended modes of addressing, the operand
field of the source statement is the address of the value that is
to be operated on. The Direct and Extended modes differ only
in the range of memory locations to which they can direct the
MPU. Direct addressing generates a single 8-bit operand and,
hence, can address only memory locations 0 ...., 255; a two byte
operand is generated for Extended addressing, enabling the MPU
to reach the remaining memory locations, 256 ...., 65535. An
example of Direct addressing and its effect on program flow is
illustrated in Fig. 34.
Table 10 shows the cycle-by~ycle operations of this mode.
The MPU, after encountering the opcode for the instrution
LDAA (Direct) at memory location 5004 (program Counter =
5004), looks in the next location, 5005, for the address of the
operand. It then sets the program counter equal to the value
found there (100 in the example) and fetches the operand, in

R/W
Line

Data Bus

this case a value to be loaded into accumulator A, from that
location. For instructions requiring a two-byte operand such as
LDX (Load the Index Register), the operand bytes would be
retrieved from locations 100 and 101.
Extended addressing, Fig. 35, is similar except that a twobyte address is obtained from locations 5007 and 5008 after the
LDAB (Extended) opcode shows up in location 5006. Extended
addressing can be thought of as the "standard" addressing
mode, that is, it is a method of reaching anyplace in memory.
Direct addressing, since only one address byte is required,
provides a faster method of processing data and generates fewer
bytes of control code. In most applications, the direct addressing range, memory locations 0 ...., 255, are reserved for RAM.
They are used for data buffering and temporary storage of
system variables, the area in which faster addressing is of most
value, Cycle-by~ycle operation is shown in Table 11 for Extended Addressing.

Table 10 Direct Mode Cycle by Cycle Operation
Address Mode
and Instructions
ADC
ADD
AND
BIT
CMP
CPX
LOS
LOX

EaR
LOA
ORA
SBC
SUB

Cycle
#

VMA
Line

1
2
3

1
1
1

Op Code Address
Op Code Address + 1
Address of Operand

1
1
1

Op Code
Address of Operand
Operand Data

1
2

3
4

1
1
1
1

OP Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1

1
1
1
1

Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

4

1
2
3
4

1
1
0
1

Op Code Address
Op Code Address + 1
Destination Address
Destination Address

1
1
1
0

OP Code
Destination Address
Irrelevant Data (NOTE 1)
Data from Accumulator

5

1
2
3
4
5

1
1
0
1
1

Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand
Address of Operand + 1

1
1
1
0
0

OP Code
Address of Operand
Irrelevant Data (NOTE 1)
Register Data (High Order Byte)
Register Data (Low Order Byte)

Cycle

3

4

STA

STS
STX

Address Bus

R/W
Line

Data Bus

NOTE 1. If device which is address during this cycle uses VM;A., then the Data Bus will go to the high impedance three-state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data BU5.

220

eHITACHI

--------------------------------------------------H06800,H068AOO,H068800
Table 11 Extended Mode Cycle by Cycle
Address Mode
and Instructions

Cycle

Cycle
#

VMA
Line

6

1
2
3
4
5
6

1
1
1
0
1
1

1
2
3
4
5
6

7
8
9

1
1
1
1
1
1
0
0
1

1
2
3

1
1
1

STS
STX

JSR

9

I

I

JMP

i

I

3

R/W
Line

Address Bus

I

I

i

I

----I-

I
I

Data Bus

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand
Address of Operand + 1

1
1
1
1
0
0

Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Irrelevant Data (NOTE 1)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Op Code Address + 2
Op Code Address + 2

1
1
1
1
0
0
1
1
1

Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
Irrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)
Address of Subroutine (Low Order Byte)

Op Code Address
Op Code Address + 1
Op Code Address + 2

:

I

1
1
1

I
I

I
!

I

Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)

ADC EOR
ADD LOA
AND ORA
BIT
SBC
CMP SUB

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand

Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data

CPX
LOS
LOX

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1

Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low

STA A
STA B
5
____________________
ASL
ASR
CLR
COM
DEC
INC

1
2
,3
45
i

01

Op Code
Op Code
,lOP Code
Operand

Address
Address + 1
Address + 2
1
Destination Address
1
__
A_d_dr_e_ss__-4___

~I---~~I---l--~i--o-p-e-ra-n-d-D-e-s-ti-n-at-io_n

LSR
NEG
ROL
ROR
TST

I
'I

6

i
11

1
2
3
4
56

I'

I

~1:i

1
0
I
1/0
(NOTE

i

(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)

Op Code
Destination Address (High Order Byte)
Destination Address (Low Order Byte;
Irrelevant Data (NOTE 1)
________________

o__~I---D-at-a-f-ro-m--A-c-c-um--u-la-to_r

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand
Address of Operand

I

1
1
1
1
1
0

Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Irrelevant Data (NOTE 1)
New Operand Data (NOTE 2)

2)

If device which is addressed during this cycle uses VMA, then the Data Bus will go to the high impedance three-state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.
NOTE 2. For TST, VMA = 0 and Operand data does not change.

NOTE 1.

MPU

MPU

MPU

MPU

RAM

RAM
ADDR = 100

ADDR

Program
Memory

ADDR=300~~__~,

Program
Memory

Program
Memory

PC = 5006 ~;;;;.;...;...;;.~
5007

PC = 5004
5005

PC
PC-l
ADDR = 0 ~255
General Flow

;~~~~----I
Example

AD DR ~ 256
General Flow

Example

Figure 35 Extended Addressing Mode

Figure 34 Direct Addressing Mode

~HITACHI

221

H06800,H068AOO,H068800-------------------------------------------------• Relative Address Mode
In both the Direct and Extended modes, the address obtained by the MPU is an absolute numerical address. The Relative addressing mode, implemented for the MPU's branch
instructions, specifies a memory location relative to the Program
Counter's current location. Branch instructions generate two
bytes of machine code, one for the instruction opcode and one
for the "relative" address (see Fig. 36). Since it is desirable to be
able to branch in either direction, the 8-bit address byte is interpreted as a signed 7 -bit value; the 8th bit of the operand is
treated as a sign bit, "0" =plus and "1" =minus. The remaining
seven bits represent the numerical value. This result in a relative
addressing range of ±I27 with respect to the location of the
branch instruction itself. However, the branch range is computed with respect to the next instruction that would be executed if the branch conditions are not satisfied. Since two
byte are generated, the next instruction is located at PC+2.
If, D is defined as the address of the branch destination, the
range is then;
or

(PC+2) -128;£ 0;£ (PC+2) + 127
PC-126;£ 0 ;£PC + 129

that is, the destination of the branch instruction must be
within -126 to +129 memory locations of the branch instruction itself. For transferring control beyond this range, the unconditional jump (JMP), jump to subroutine (JSR), and return
from subroutine (RTS) are used.
In Fig. 36, when the MPU encounters the opcode for BEQ
(Branch if result of last instruction was zero), it tests the Zero
bit in the Condition Code Register. If that bit is "0", indicating
a non-zero result, the MPU continues execution with the next
instruction (in location 5010 in Fig. 36). If the previous result
was zero, the branch condition is satisfied and the MPU adds the
offset, 15 in this case, to PC+2 and branches to location 5025
for the next instruction.
The branch instructions allow the programmer to efficiently
direct the MPU to one point or another in the control program
depending on the outcome of test results. Since the control
program is normally in read·c::_________x::::x::::x"--_______
PSH

Data

--------1-\t\_"""'--+-':.
I

I

••

r·i----ioo-~--+--"'!"'"--!

DataR:: J_
.._.-,..,--__""\.J__---v ___""\.J____""\.J____"'V'____.... /

'-

Branch
Inst.

PC ±
Offset

Next
Inst.
I

_ _ _.... ,,____""_

Next
Inst.

Figure 38 Example of Excution Timing in Each Addressing Mode

$

HITACHI

225

HD6800,HD68AOO,HD68BOO----------------------------------------------------• NOTE FOR THE RELATION BETWEEN WAI INSTRUCTION AND HALT OPERATION OF HD6800

When HALT input signal is asserted to "Low"
level, the MPU will be halted after the· execution of
the current instruction except WAI instruction.
The "Halt" signal is not accepted after the fetch
cycle of the WAI instruction (See CD in Fig. 39). In the
case of the "WAI" instruction, the MPU enters the
"WAIT" cycle after stacking the internal registers and

outputs the "High" level on the BA line.
When an interrupt request signal is input to the
MPU, the MPU accepts the interrupt regardless the
"Halt" signal and releases the "WAIT" state and outputs the interrupt's vector address. If the "Halt" signal
is "Low" level, the MPU halts after the fetch of new
PC contents. The sequense is shown below.

WAI
Instruction

I

Fetch

I

2
Address
Bus

RM

VMA

--1

IROor

NMT

BA

~

_ _ CD

HALT

When the interrupt occurs during the WAIT CYCLE, the MPU accepts the interrupt even if HALT is at "Low" level.

Figure 39 HD6800 WAIT CYCLE & HALT Request

226

~HITACHI

HD6802---------------MPU

(Microprocessor with Clock and RAM)

The HD6802 is a monolithic 8-bit microprocessor that contains all the registers and accumulators of the present HD6800
plus an internal clock oscillator and driver on the same chip.
In addition, the HD6802 has 128 bytes of RAM on the chip
located at hex addresses 0000 to 007F. The first 32 bytes of
RAM, at hex addresses 0000 to OOlF, may be retained in a low
power mode by utilizing V cc standby, thus facilitating memory
retention during a power-down situation.
The HD6802 is completely software compatible with the
HD6800 as well as the entire HMCS6800 family of parts.
Hence, the HD6802 is expandable to 65k words.
• FEATURES
• On-Chip Clock Circuit
• 128 x 8 Bit On-Chip RAM
• 32 Bytes of RAM are Retainable
• Software-Compatible with the HD6800

• PIN ARRANGEMENT
Vss

o

RES

HAlf

•
•

Expandable to 65k words
Standard TIL-Compatible Inputs and Outputs

•
•
•
•

8 Bit Word Size
16 Bit Memory Addressing
Interrupt Capability
Compatible with MC6802

XTAL

MR

VMA

RE

NMI

Vee Standby

Rffl
Do

HD6802
0,

•

0,

BLOCK DIAGRAM

Vee

Vee

Vee

Standby

2

Os

2

D.
0,

Vee

Vce

A,s

A"
2

A"

A"

---,._ _ _ _ _ _--Jr-'

VSS

(Top View)

XTAL~""""---'

CJ

Crystal

e';J; ie,

$

HITACHI

227

HD6802
• ABSOLUTE MAXIMUM RATINGS
Item

Symbol
Vee *
Vee Standby*
Vin *

Supply Voltage
Input Voltage

Value

Unit

~

V

-0.3

~

-0.3

~

+7.0
+7.0

Operating Temperature

Topr

-20

Storaoe Ternoerature

T·

-"'''' ~ +150

V

+75

°c

Or

• With respect to Vss (SYSTEM GND)
(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions are exceeded, it could affect reliability of LSI.

•

RECOMMENDED OPERATING CONDITIONS
Item

Symbol
Vee *
Vee Standby*
VIL *

Supply Voltage

Input Voltage

l

VIH *

typ

max

Unit

5.0

5.25

V

-0.3

0.8

V

Vee

V

Vee
75

°c

Except RES

2.0

-

RES

4.25

-

-20

25

I

Operation Temperature

min
4.75

Topr

V

* With respect to Vss (SYSTEM GND)

• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vee=5.0V±5%, Vee Standby=5.0V±5%, Vss=OV, Ta=-20~+75°C, unless otherwise noted.)
Item
Input "High" Voltage
Input "Low" Voltage

Symbol
Except RES

VOH

Output "Low" Voltage
Do~D7'

Input Leakage Current

Except Do ~D7 ****

Output Capacitance

10H = -145t.LA

Do~D7

Except

Do~D7

Ao~Als,

R/W, BA,

VMA,E

e, V

$

-

2.4

-

2.4

-

-

---

V

-

-

0.4

V

-

10

t.LA

~5.25V

-2.5

-

2.5

-

0.6

1.2

t.L A
W

10

12.5

6.5

10

-

-

12

Vin =
Vin =

~n

Vin=OV, Ta=25°C,
f=1.0MHz

Caut

Vin=OV, Ta =25°C,
f=1.0MHz

HITACHI

V

0.8
V
0.8
- -I----

2.4

... A~ RES inpuH

at 2.4V (Fig. 2, Fig. 3)

I "Low"

PWL

at 0.8V (Fig. 2, Fig. 3)

f2 Output(E)
The following is a summary of the HD6802 MPU signals:
•

Address Bus (Ao - A 15 )

Sixteen pins are used for the address bus. The outputs are
capable of driving one standard TTL load and 90pF.
•

Data Bus (Do - D 7 )

Eight pins are used for the data bus. It is bidirectional,
transferring data to and from the memory and peripheral
devices. It also has three-state output buffers capable of driving
one standard TTL load and 130pF.
Data Bus will be in the output mode when the internal RAM
is accessed. This prohibits external data entering the MPU. It
should be noted that the internal RAM is fully decoded from
$0000 to $007F. External RAM at $0000 to $007F must be
disabled when internal RAM is accessed.
•

HALT

When this input is in the "Low" state, all activity in the
machine will be halted: This input is level sensitive.
In the halt mode, the machine will stop at the end of an
instruction. Bus Available will be at a "H igh" state. Valid
Memory Address will be at a "Low" state. The address bus will
display the address of the next instruction.
To insure single instruction operation, transition of the
HALT line must not occur during the last 250ns of E and the
HALT line must go "High" for one Clock cycle.
HALT should be tied "High" if not used. This is good
engineering design practice in general and necessary to insure
proper operation of the part.
•

Read/Write (R,w)

This TTL compatible output signals the peripherals and
memory devices whether the MPU is in a Read ("High") or
Write ("Low") state. The normal standby state of this signal is
Read ("High"). When the processor is halted, it will be in the
logical one state ("High").
This output is capable of driving one standard TTL load and
90pF.
•

Valid Memory Address (VMA)

This output indicates to peripheral devices that there is a
valid address on the address bus. In normal operation, this signal
should be utilized for enabling peripheral interfaces such as the
PIA and ACIA. This signal is not three-state. One standard TTL
load and 90pF may be directly driven by this active high signal.
•

Bus Available (BA)

The Bus Available signal will normally be in the "Low" state.
When activated, it will go to the "High" state indicating that the
microprocessor has stopped and that the address bus is available
(but not in a three-state condition). This will occur if the HALT
line is in the "Low" state or the processor is in the wait state
as a result of the execution of a WAI instruction. At such time,
all three-state output drivers will go to their off state and other

234

outputs to their normally inactive level.
The processor is removed from the wait state by the
occurrence of a maskable (mask bit 1=0) or nonmaskable
interrupt. This output is capable of driving one standard TTL
load and 30pF.
•

Interrupt Request (IRQ)

This level sensitive input requests that an interrupt sequence
be generated within the machine. The processor will wait, until
it completes the current instruction that is being executed
before it recognizes the request. At that time, if the interrupt
mask bit in the Condition Code Register is not set, the machine
will begin an interrupt sequence. The index Register, Program
Counter, Accumulators, and Condition Code Register are stored
away on the stack. Next the MPU will respond to the interrupt
request by setting the interrupt mask bit high so that no further
interrupts may occur. At the end of the cycle, a 16-bit address
will be loaded that points to a vectoring address which is located
in memory locations FFF8 and FFF9. An address loaded at
these locations causes the MPU to branch to an interrupt
routine in memory.
The HALT line must be in the "High" state for interrupts to
be serviced. Interrupts will be latched internally while HALT is
"Low".
A 3kQ external register to Vee should be used for wire-OR
and optimum control of interrupts.
•

Reset (RES)

This input is used to reset and start the MPU from a
power-down condition, resulting from a power failure or an
initial start-up of the processor. When this line is "Low", the
MPU is inactive and the information in the registers will be lost.
If a "High" level is detected on the input, this will signal the
MPU to begin the restart sequence. This will start execution of a
routine to initialize the processor from its reset condition. All
the higher order address lines will be forced "High". For the
restart, the last two(FFFE, FFFF) locations in memory will be
used to load the program that is addressed by the program
counter. During the restart routine, the interrupt mask bit is set
and must be reset before the MPU can be interrupted by IRQ.
Power-up and reset timing and power-down sequences are
shown in Fig. 12 and Fig. 13 respectively.
•

Non-Maskable Interrupt (NMI)

A low-going edge on this input requests that a non-maskinterrupt sequence be generated within the processor. As with
the IRQ signal, the processor will complete the current
instruction that is being executed before it recognizes the NMI
signal. The interrupt mask bit in the Condition Code Register
has no effect on NMI.
The Index Register, Program Counter, Accumulators, and
Condition Code Register are stored away on the stack. At the
end of the cycle, a 16-bit address will be loaded that points to a
vectoring address which is located in memory locations FFFC
and FFFD. An address loaded at these locations causes the
MPU to branch to a non-maskable interrupt routLtle in memory.
A 3kQ external resistor to Vee should be used for wire-OR
and optimum control of interrupts.
Inputs IRQ and Nm are hardware interrupt lines that are
sampled when E is "High" and will start the interrupt routine
on a "Low" E following the completion of an instruction. IRQ
and NMI should be tied "High" if not used. This is good engineering design practice in general and necessary to insure
proper operation of the part. Fig. 14 is a flowchart describing the
major decision paths and interrupt vectors of the microprocessor. Table 1 gives the memory map for interrupt vectors.

~HITACHI

----------------------------------------------------------------HD6802

Vcc

E
!--tpcs

>4.25V

__----------{~---"""""'_+------------l---RES -------+--~ I

Option 1
(See Note below)

RES ----------~

Option 2
See Figure 8 for
Power Down condition

Jt

i.OV

RE

VMA

O.8V

O.8V

----------------

tpcr

(f~---------------__~~_____________

____....J/
(NOTE)

If option 1 is chosen. RES and RE pins can be tied together.

Figure 12 Power-up and Reset Timing

Vec

E

RE

Figure 13 Power-down Sequence

Figure 14 MPU Flow Chart

$

HITACHI

235

HD6802-----------------------------------------------------------------Conditions for Crystal (4 MHz)
• A: Cut Parallel resonant
• Co = 7 pF max.
• R J = 80n max.

Table 1 Memory Map for Interrupt Vectors
Vector

Description

MS

LS

FFFE

FFFF

Restart

FFFC

FFFD

Non-Maskable Interrupt (NMI)

FFFA

FFFB

Software Interrupt

(SWI)

FFFS

FFF9

Interrupt Request

(lRO)

(RES)

Co

Crystal Equivalent Circuit

• RAM Enable (RE)
A TTL-compatible RAM enable input controls the on-chip
RAM of the HD6802. When placed in the "High" state, the
on-chip memory is enabled to respond to the MPU controls. In
the "Low" state, RAM is disabled. This pin may also be utilized
to disable reading and writing the on-chip RAM during a
power-down situation. RAM enable must be "Low" three cycles
before Vee goes below 4.7SV during power-down.
RE should be tied to the correct "High" or "Low" state if
not used. This is good engineering design practice in general and
necessary to insure proper operation of the part.
•

Recommended Oscillator (4MHz)
39 pin

LJ--------.----,

HD6802

38 pin

EXTAL and XTAL

The HD6802 has an internal oscillator that may be crystal
controlled. These connections are for a parallel resonant
fundamental crystal (AT cut). A divide-by-four circuit has been
added to the HD6802 so that a 4MHz crystal may be used in
lieu of a 1MHz crystal for a more cost-effective system. Pin39 of
the HD6802 may be driven externally by a TTL input signal if
a separate clock is required. Pin38 is to be left open in this
mode.
An RC network is not directly usable as a frequency source
on pins 38 and 39. An RC network type TTL or CMOS
oscillator will work well as long as the TTL or CMOS output
drives the HD6802.
If an external clock is used, it may not be halted for more
than 4.5J.(s. The HD6802 is a dynamic part except for the
internal RAM, and requires the external clock to retain
information_

C,

± 20%

Figure 15 Crystal Oscillator

When using the crystal, see the note for Board Design of the
Oscillation Circuit in HD6802 .
•

Memory Ready (MR)

MR is a TTL compatible input control signal which allows
stretching of E. When MR is "High", E will be in normal
operation. When MR is "Low", E may be stretched integral
multiples of half periods, thus allowing interface to slow
memories. Memory Ready timing is shown in Fig. 16.
MR should be tied "High" if not used. This is good
engineering design practice in general and necessary to insure
proper operation of the part. A maximum stretch is 4.5J.(s.

~O.4V

2.4V
E

~tSMR

tpCf

tPCr

MR

Figure 16 Memory Ready Control Function

236

= C, = 22pF

_HITACHI

I

----------------------------------------------------------------HD6802
•

• MPU INSTRUCTION SET

Enable (E)

This pin supplies the clock for the MPU and the rest of the
system. This is a single phase, TTL compatible clock. This clock
may be conditioned by a Memory Ready Signal. This is
equivalent to lP2 on the HD6800 .

• Vee Standby
This pin supplies the dc voltage to the first 32 bytes of RAM
as well as the RAM Enable (RE) control logic. Thus retention of
data in this portion of the RAM on a power up, power-down, or
standby condition is guaranteed at the range of 4.0 V to 5.25 V.
Maximum current" drain at S.2SV is 8mA.

The HD6802 has a set of 72 different instructions. Included
are binary and decimal arithmetic, logical, shift, rotate, load,
store, conditional or unconditional branch, interrupt and stack
manipulation instructions.
This instruction set is the same as that for the
6800MPU(HD6800 etc.) and is not explained again in this
data sheet.
•

NOTE FOR BOARD DESIGN OF THE OSCILLATION
CIRCUIT IN HD6802

In designing the board, the following notes should be taken
when the crystal oscillator is used.

_____
Crystal oscillator and load capacity CL must be placed near
________
the LSI as much as possible.

o

CL

~

39

[Normal oscillation may be disturbed when external noise is]
induced to pin 38 and 39.

~~~----~~
HD6802

~

37

Pin 38 signal line should be wired apart from pin 37 signal
line as much as possible. Don't wire them in parallel, or normal
oscillation may be disturbed when E signal is feedbacked to
XTAL.

The following design must be avoided.
Must be avoided

«

o

'\

-+-----+--+-------

Signal C

A Signal line or a power source line must not cross or go near
the oscillation circuit line as shown in the left figure to prevent
the induction from these lines and perform the correct
oscillation. The resistance among XT AL, EXT AL and other pins
should be over 10MU.

HD6802

Figure 17

Note for Board Design of the Oscillation Circuit

_HITACHI

237

HD6802----------------------------------------------------------------

,......___Other signals are not wired in this area.

/

/"" E signal is wired apart from 38 pin
and 39 pin.

HD6802

Figure 18

238

Example of Board Design Using the Crystal Oscillator

~HITACHI

-------------------------------------------------------------------HD6802
• NOTE FOR THE RELATION BETWEEN WAI INSTRUCTION AND HALT OPERATION OF HD6802

When HALT input signal is asserted to "Low"
level, the MPU will be halted after the execution of
the current instruction except WAI instruction.
The "Halt" signal is not accepted after the fetch
cycle of the WAI instruction (See CD in Fig. 19). In the
case of the "WAI" instruction, the MPU enters the
"WAIT" cycle after stacking the internal registers and

outputs the "High" level on the BA line.
When an interrupt request signal is input to the
MPU, the MPU accepts the interrupt regardless the
"Halt" signal and releases the "WAIT" state and outputs the interrupt's vector address. If the "Halt" signal
is "Low" level, the MPU halts after the fetch of new
PC contents. The sequense is shown below.

WAI

E

Address
Bus
SP Inl

SP In-II SP In-21 SP In-31 SP In-41 SP In-51 SP In-61

Vector

Vector

Address

Address Address

New PC

R/iN

VMA

IROor

NMT

+------------I~
~~--

BA

__ CD

'HALT
When the interrupt occurs during the WAIT CYCLE. the MPU accepts the interrupt even if HALT is at ··Low·· level.

Figure 19 HD6802 WAIT CYCLE & HALT Request

~HITACHI

239

HD6802W

MPU

(Microprocessor with Clock and RAM)

H06802W is the enhanced version of H06802 which contains MPU, clock and 256 bytes RAM. Internal RAM has been
extended from 128 to 256 bytes to increase the capacity of
system read/write memory for handling temporary data and
manipulating the stack.
The internal RAM is located at hex addresses 0000 to OOFF.
The first 32 bytes of RAM, at hex addresses 0000 to 001 F, may
be retained in a low power mode by utilizing Vee standby,
thus facilitating memory retention during a power-down situation.
The HD6802W is completely software compatible with the
H06800 as well as the entire HMCS6800 family of parts. Hence,
the H06802W is expandable to 65k words.

•
•
•
•
•
•
•

FEATURES
On-Chip Clock Circuit
256 x 8 Bit On-Chip RAM
32 Bytes of RAM are Retainable
Software-Compatible with the HD6800, HD6802
Expandable to 65k words
Standard TTL-Compatible Inputs and Outputs

•
•
•

8 Bit Word Size
16 Bit Memory Addressing
Interrupt Capability

I

I

HD6802WP

(DP-40)

• PIN ARRANGEMENT

0

RES
EXTAL
XTAL
E
RE

NMI

Vee Standby
RiW

SA

D.

Vee

0,

0,

HD6802W

•

0,

BLOCK DIAGRAM

D.

2

0,
0,
Au

Vee

Vee

Vee

A,.

Vee

Standby Vee

A"

All

Counter/ {
Timer I/O

'Rn

~,,"" (
I/O

IRci

TIm
MR

CS.

VMA
Clock

R/W

E
RE
RtW
HD6802W NMI
(MPU)

SA
XTAL

Control {

(Top View)

REs

VMA

0.-0,

o

Crystal

C

.i .i c,

A.-A" EXTAL

I

I

nf *l

Vss

240

VSS

eHITACHI

----------------------------------------------------------------HD6802W
A expanded block diagram of the HD6802W is shown in Fig.
1. As shown, the number and configuration of the registers are

the same as the HD6802 except that the internal RAM has been
extended to 256 bytes.

A,
16

A. As
15 14

A. A) A2
13 12 11

AI
10

A.
9

MA 3
E 37
RES 40

NMi 6
HALT 2
~4

EXTAL 39
XTAL 38
BA 7
VMA 5
34

Am

Vee = Pins 8,35
Vss = Pins 1,21

26
0,

27
O.

28
Os

29 30
O. 0 3

31

32 33

O2

01

O.

Figure 1 Expanded Block Diagram

Address Map of RAM is shown is Fig. 2.
The HD6802W has 256 bytes of RAM on the chip located
at hex addresses 0000 to DOFF. The first 32 bytes of RAM, at
hex addresses 0000 to 001 F, may be retained in a low power

mode by utilizing Vee standby and setting RAM Enable Signal
"Low" level, thus facilitating memory retention during a
power-down situation.

: : _____________ } retention by Vee Standby
0020

OOFF t -_ _ _ _ _ _---..l

Figure 2 Address Map of HD6802W

~HITACHI

241

HD6802W-------------------------------------------------------------• ABSOLUTE MAXIMUM RATINGS
Item

Symbol
Vee *
Vee Standby*
Vin *

Supply Voltage
Input Voltage
Operating :remperature

V
V
°c

-20 - +75

Tst9

I

Unit

-0.3 - +7.0

Topr

Storage Temperature

Value
-0.3'" +7.0

°c

-55'" +150

I

I

• With respect to Vss (SYSTEM GND)
(NOTE)

•

Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.

RECOMMENDED OPERATING CONDITIONS
Item

Symbol

Supply Voltage

min

Vee*

4.75

Vee Standby *
V 1l *

4.0

Input Voltage
V 1H

I Except RES
I RES

*

Operation Temperature

typ

max

Unit

5.0

5.25

V
V

-0.3

-

0.8

2.0

-

Vee

Vee -0.75

-

-20

25

Vee
75

Topr

V
°c

• With respect to Vss (SYSTEM GND)

• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vee=5.0V±5%, Vee Standby=5.0V±5%, Vss=OV, Ta=-20-+75°C, unless otherwise noted.)
Symbol

Item
Input "High" Voltage
Input "Low" Voltage

Except RES

V1H

RES
Except RES

Ao-A lS , RIW, VMA

VOH

Output "Low" Voltage
Three State (Off State) Input Current

0 0-0.,.

Input Leakage Current

Except 0 0 -0 7

Vee

Vcc-O.75

Vee
0.8

-

IOH = -205J.LA

2.4

-

IOH = -145J.LA

2.4

-

IOH = -100J.LA

2.4

-0.3
-0.3

0 0 -0 7
Except 0 0 -0 7
Ao-A lS , R/W. SA,
VMA

V

-

V

-

0.4

V

-10

-

10

J.LA

lin ***

Vin = Q-5.25V

-2.5

-

2.5

J.LA

-

0.7

1.2

W

10

12.5

6.5

10

-

-

12

IOl = 1.6mA

~n

Vin=OV, Ta=25°C,
f=1.0MHz

Gout

Vin=OV, Ta= 2SoC,
f=1.0MHz

• T a=2ft e, Vcc =5V

$

V

V in = 0.4-2.4 V

•• As RES inpull1as histeresis character. applied voltage up to 2.4V is regarded as "Low" level when it goes up from OV.
... Does not include EXTAL and XTAL, which are crystal inputs .
•• ** In power-down mode, maximum power dissipation is less than 42mW.

242

0.8

Unit

VOL
ITS1
Po ****

Power Dissipation

Output Capacitance

max

-

-

SA

Input Capacitance

typ*

2.0

**
V1l

RES

00-0 7 , E
Output "High" Voltage

min

Test Condition

HITACHI

pF
pF

------------------------------------------------------------------HD6802VV
• AC CHARACTERISTICS (Vee=5.0V±5%, Vee Standby=5.0V±5%, Vss=OV, Ta=-20~+75°C, unless otherwise noted.)
1. CLOCK TIMING CHARACTERISTICS

I Input Clock -;- 4

Frequency of Operation

1Erystal Frequency

typ

max

0.1

-

1.0

fXTAL

1.0

-

4.0

1.0

-

10

450

-

4500

ns

-

-

25

ns

Test Condition

tcye

Fig. 4, Fig. 5

f "High" Level

PW¢H

at 2.4V(Fig. 4, Fig. 5)

"Low" Level

PWL

at 0.8V (Fig. 4, Fig. 5)

t.-p

0.8V

Cycle Time
Clock Pulse Width

min

f

Symbol

Item

Clock Fall Time

~

2.4V(Fig.4,Fig.5)

Unit
MHz
/1s

2. READ/WRITE TIMING
Item

Symbol

min

typ*

max

Address Delay

tAD

Fig. 4, Fig. 5, Fig. 8

-

270

ns

Peripheral Read Access Time

tace

Fig.4

-

-

530

ns
ns

Test Condition

Unit

Data Setup Time (Read)

tOSR

Fig.4

100

-

-

Input Data Hold Time

tH

Fig.4

10

-

-

ns

Output Data Hold Time

tH

Fig.5

20

-

-

ns

225

ns

250

ns

Address Hold Time (Address, R/W, VMA)

tAH

Fig. 4, Fig. 5

Data Delay Time (Write)

toow

Fig. 5

10
-

Bus Available Delay

teA

Fig. 6, Fig. 7, Fig. 9, Fig. 10

-

-

tpcs

Fig. 6

Fig. 9, Fig. 11

200

-

-

ns

tpcr,
tpCf

Fig. 6~ Fig. 9, Fig. 11, Fig.12,
Fig. 14

-

-

100

ns

max

Unit

Processor Controls
Processor Control Setup Time
Processor Control Rise and Fall Time
(Measured at O.BV and 2.0V)

~

ns

3. POWER DOWN SEQUENCE TIMING, POWER UP RESET TIMING AND MEMORY READY TIMING
min

typ

RAM Enable Reset Time (1)

tRE1

Fig. 12

150

-

-

RAM Enable Reset Time (2)

tRE2

Fig. 12

E-3 cycles

-

-

Item

Symbol

Test Condition

ns

Reset Release Time

tLRES

Fig. 11

20

tRE3

Fig. 11

0

-

-

ms

RAM Enable Reset Time (3)
Memory Ready Setup Time

tSMR

Fig. 14

300

-

-

ns

Memory Ready Hold Time

tHMR

Fig. 14

0

-

eHITACHI

200

ns
ns

243

HD6802VV------------------------------------------------------------------

5.0V

RL = 2.4kfl
c = nQpF for n c, -n,. E _
= 90pF for Ao -A",
and VMA
= 30pF for BA
R= 11kflfor 0 0 -0 7 , E
= 16kfl for Ao-A", R/IN, and VMA
= 24kfl for SA
.
C includes stray Capacitance.
All diodes are 1 S2074 (8) or equ ivalent.

R/W,

C

R

Figure 3 Bus Timing Test Load

2.4V

E

R/W
Address
From MPU

VMA

Data
From Memory
or Peripherals

2.0V -::;;;oo..,.i....",===!>ok
------------------------------~~
0.8V--="4---===~

~

Data Not Valid

Figure 4

Read Data from Memory or Peripherals

~--------------------tcyc----------------------~

~------PW~L------1~======~PW~~~H~======~1
E

0.4V

R/W

Address
From MPU
VMA

Data
From MPU

__________________

t oow [
~I~~.4-V~

0.4 V ----,-....::::00""1'
~==;;;::;;;;::;;:;:;::=~,.c:..
"

~

Data Not Valid

Figure 5 Write Data in Memory or Peripherals

244

$

HITACHI

----------------------------------------------------------------HD6802W

The Last Instruction Cycle

HALT Cycle

+

2.4V

~~~--L
BA

t

________________________
I_--J

_
2.4V

Figure 6 Timing of HALT and BA
HALT Cycle

Instruction Cycle

O.4V
2.0V

HALT

O.BV

tpc,

-*__tpcs

-'--.-j

BA
O.4V

Figure 7 Timing of HALT and BA
MPU Restart Sequence

MPU Reset

VCC-O.75V
O.BV

VMA

2.4V

Figure 8 RES and MPU Restart Sequence

eHITACHI

245

HD6802W--------------------------------------------------______________

WAIT Cycle or
The Last Instruction Cycle

Interrupt Sequence

2.4V

\

-------

IRQ, NMI

- - - - - - - - - - - - -- -- - - - - - -- - - - - - - (When WAIT Cycle)

--

-"\
\

BA
Figure 9

IRQ and NMI Interrupt Timing

The last execution cycle of

WAI instruction (,.#9_)_ _ _ _ _"'\..I~

WAIT Cycle

2.4V

BA

Figure 10 WAI Instruction and BA Timing

246

eHITACHI

------------------------------------------------------------HD6802W
•

HD6802W MPU SIGNAL DESCRIPTION

Address Bus (Ao ......, A 1s )
Sixteen pins are used for the address bus. The outputs are
capable of driving one standard TTL load and 90pF.
• Data Bus (Do ......, 0 7 )
Eight pins are used for the data bus. It is bidirectional,
transferring data to and from the memory and peripheral
devices. It also has three·state output buffers capable of driving
one standard TTL load and l30pF.
Data Bus will be in the output mode when the internal RAM
is accessed. This prohibits external data entering the MPU. It
should be noted that the internal RAM is fully decoded from
$0000 to $OOFF. External RAM at $0000 to $OOFF must be
disabled when internal RAM is accessed.
• HALT
When this input is in the "Low" state, all activity in the
machine will be halted: This input is level sensitive.
In the halt mode, the machine will stop at the end of an
instruction. Bus Available will be at a "High" state. Valid
Memory Address will be at a "Low" state. The address bus will
display the address of the next instruction.
•

To insure single instruction operation, transition of the
HALT line must not occur during the last tpcs of E and the
HALT line must go "High" for one Clock cycle.
HALT should be tied "High" if not used. This is good
engineering design practice in general and necessary to insure
proper operation of the part.
• Read/Write (RIW)
This TTL compatible output signals the peripherals and
memory devices whether the MPU is in a Read ("High") or
Write ("Low") state. The normal standby state of this signal is
Read ("High"). When the processor is halted, it will be in the
logical one state ("High").
This output is capable of driving one standard TTL load and
90pF.
•

Valid Memory Address (VMA)
This output indicates to peripheral devices that there is a
valid address on the address bus. In normal operation, this signal
should be utilized for enabling peripheral interfaces such as the
PIA and ACIA. This signal is not three-state. One standard TTL
load and 90pF may be directly driven by this active high signal.
• Bus Available (BA)
The Bus Available signal will normally be in the "Low" state.
When activated, it will go to the "High" state indicating that the
microprocessor has stopped and that the address bus is available
(but not in a three-state condition). This will occur if the HALT
line is in the "Low" state or the processor is in the wait state
as a result of the execution of a WAI instruction. At such time,
all three-state output drivers will go to their off state and other
outputs to their normally inactive level.
The processor is removed from the wait state by the
occurrence of a maskable (mask bit 1=0) or nonmaskable
interrupt. This output is capable of driving one standard TTL
load and 30pF.
• Interrupt Request (IRQ)
This level sensitive input requests that an interrupt sequence

$

be generated within the machine. The processor will wait, until
it completes the current instruction that is being executed
before it recognizes the request. At that time, if the interrupt
mask bit in the Condition Code Register is not set, the machine
will begin an interrupt sequence. The index Register, Program
Counter, Accumulators, and Condition Code Register are stored
away on the stack. Next the MPU will respond to the interrupt
request by setting the interrupt mask bit high so that no further
interrupts may occur. At the end of the cycle, a 16-bit address
will be loaded that points to a vectoring address which is located
in memory locations FFF8 and FFF9. An address loaded at
these locations causes the MPU to branch to an interrupt
routine in memory.
The HALT line must be in the "High" state for interrupts to
be serviced. Interrupts will be latched internally while HALT is
"Low".
A 3kll external register to Vee should be used for wire-OR
and optimum control of interrupts.
•

Reset (RES)
This input is used to reset and start the MPU from a
power-down condition, resulting from a power failure or an
initial start-up of the processor. When this line is "Low", the
MPU is inactive and the information in the registers will be lost.
If a "High" level is detected on the input, this will signal the
MPU to begin the restart sequence. This will start execution of a
routine to initialize the processor from its reset condition. All
the higher order address lines will be forced "High". For the
restart, the last two(FFFE, FFFF) locations in memory will be
used to load the program that is addressed by the program
counter. During the restart routine, the interrupt mask bit is set
and must be reset before the MPU can be interrupted by IRQ.
Power-up and reset timing and power-down sequences are
shown in Fig. II and -Fig. 12 respectively.
•

Non-Maskable Interrupt (NMI)
A low-going edge on this input requests that a non-maskinterrupt sequence be generated within the processor. As with
the IRQ signal, the processor will complete the current
instruction that is being executed before it recognizes the NMI
signal. The interrupt mask bit in the Condition Code Register
has no effect on NMI.
The Index Register, Program Counter, Accumulators, and
Condition Code Register are stored away on the stack. At the
end of the cycle, a 16-bit address will be loaded that points to a
vectoring address which is located in memory locations FFFC
and FFFD. An address loaded at these locations causes the
MPU to branch to a non-maskable interrupt routine in memory.
A 3kll external resistor to Vee should be used for wire-OR
and optimum control of interrupts.
Inputs IRQ and NMI are hardware interrupt lines that are
sampled when E is "High" and will start the interrupt routine
on a "Low" E following the completion of an instruction. IRQ
and NMI should be tied "High" if not used. This is good engineering design practice in general and necessary to insure
proper operation I)f the part. Fig. 13 is a flowchart describing
the major decision paths and interrupt vectors of the microprocessor. Table 1 gives the memory map for interrupt vectors.

HITACHI

247

HD6802W--------------------------------------_____________________

Vee

E

I--tpcs

>Vee-O.75V

r-------------~r-------~+------------l---Option 1
(See Note below)

Option 2
See Figure 12 for
Power Down condition

Jt

i.OV

RE

O.8V

---------------VMA

O.8V

tpcr

(.~'-----------------,,-------------------

____,-J/
(NOTE)

If oPtion 1 is chosen, RES and RE pins can be tied together.

Figure 11

Power-up and Reset Timing

Vee

E

RE

Figure 12 Power-down Sequence

Figure 13 MPU Flow Chart

248

eHITACHI

--------------------------------------------------------------HD6802W
Conditions for Crystal (4 MHz)
• AT Cut Parallel resonant
• Co = 7 pF max.
• Rl =80n max.

Table 1 Memory Map for Interrupt Vectors
Vector

Description

MS

LS

FFFE

FFFF

Restart

FFFC

FFFD

Non-Maskable Interrupt (NMI)

FFFA

FFFB

Software Interrupt

(SWI)

FFF8

FFF9

Interrupt Request

(IRQ)

(RES)

Co

•

Crystal Equivalent Circuit

RAM Enable (RE)

A TTL-compatible RAM enable input controls the on-chip
RAM of the HD6802W_ When placed in the "High" state, the
on-chip memory is enabled to respond to the MPU controls. In
the "Low" state, RAM is disabled. This pin may also be utilized
to disable reading and writing the on-chip RAM during a
power-down situation_ RAM enable must be "Low" three cycles
before Vee goes below 4.7SV during power-down.
RE should be tied to the correct "High" or "Low" state if
not used. This is good engineering design practice in general and
necessary to insure proper operation of the part.
•

Recommended Oscillator (4MHz)
39 pin L J - - - - - - - t - - - ,
HD6802W

38 pin

EXTAL and XTAL

The HD6802W has an internal oscillator that may be crystal
con trolled_ These connections are for a parallel resonant
fundamental crystal (AT cut). A divide-by-four circuit has been
added to the HD6802W so that a 4MHz crystal may be used in
lieu of a I MHz crystal for a more cost-effective system. Pin39 of
the HD6802W may be driven externally by a TTL input signal if
a separate clock is required. Pin38 is to be left open in this
mode.
An RC network is not directly usable as a frequency source
on pins 38 and 39. An RC network type TTL or CMOS
oscillator will work well as long as the TTL or CMOS output
drives the HD6802W.
If an external clock is used, it may not be halted for more
than 4.5J.Ls. The HD6802W is a dynamic part except for the
internal RAM, and requires the external clock to retain
information.

C, = C,

= 22pF ±.20%

When using the crystal, see the note for Board Design of the
Oscillation Circuit in HD6802W.
•

Memory Ready (MR)

MR is a TTL compatible input control signal which allows
stretching of E. When MR is "High", E will be in normal
operation. When MR is "Low", E may be stretched integral
multiples of half periods. thus allowing interface to slow
memories. Memory Ready timing is shown in Fig. 14.
MR should be tied "High" if not used. This is good
engineering design practice in general and necessary to insure
proper operation of the part. A maximum stretch is 4.5J.Ls.

~O.4V

E

I="=tSMR

r

tPCr

MR

Figure 14 Memory Ready Control Function

$

HITACHI

249

HD6802W------------------------------------------------------------•

• Enable IE)
This pin supplies the clock for the MPU and the rest of the
system. This is a single phase, TTL compatible clock. This clock
may be conditioned by a Memory Ready Signal. This is
equivalent to cfJ2 on the HD6800 .
• Vee Standby

This pin supplies the dc voltage to the first 32 bytes of RAM
as well as the RAM Enable (RE) control logic. Thus retention of
data in this portion of the RAM on a power-up, power-down, or
standby condition is guaranteed at the range of 4.0 V to 5.25 V.
Maximum current drain at 5.25V is 8mA.

MPU INSTRUCTION SET

The HD6802W has a set of 72 different instructions.
Included are binary and decimal arithmetic, logical, shift, rotate,
load, store, conditional or unconditional branch, interrupt and
stack manipulation instructions.
This instruction set is the same as that for the
6800MPU (HD6800 etc.) and is not explained again in this
data sheet.
•

NOTE FOR BOARD DESIGN OF THE OSCILLATION
CIRCUIT IN HD6802W

In designing the board, the following notes should be taken
when the crystal oscillator is used.

______
Crystal oscillator and load capacity CL must be placed near
_______
the LSI as much as possible.

o

cL

39

~

38

1-'-'-;"';";"~----4~

HD6802W

(Normal oscillation may be disturbed when external noise is]
induced to pin 38 and 39.

~

Pin 38 signal line should be wired apart from pin 37 signal
line as much as possible. Don't wire them in parallel, or normal
oscillation may be disturbed when E signal is feedbacked to
XTAL.

The following design must be avoided.
Must be avoided

«

o

co

~

-4---!-~------

Signal C

39

38

A signal line or a power source line must not cross or go near
the oscillation circuit line as shown in the left figure to prevent
the induction from these lines and perform the correct
oscillation. The resistance among XT AL, EXT AL and other pins
should be over IOMU.

HD6802W

Figure 15 Note for Board Design of the Oscillation Circuit

250

$

HITACHI

------------------------------------------------------------HD6802W

..,.....-----Other signals are not wired in this area.

IE
x

E
E

~
/

. / E signal is wired apart from 38 pin
and 39pin.

E

HD6802W

Figure 16 Example of Board Design Using the Crystal Oscillator

$

HITACHI

251

HD6802W--------~-------------------------------------------------------

•

NOTE FOR THE RELATION BETWEEN WAI INSTRUCTION AND HALT OPERATION OF HD6802W

When HALT input signal is asserted to "Low"
level, the MPU will be halted after the execution of
the current instruction except WAI instruction.
The "Halt" signal is not accepted after the fetch
cycle of the WAI instruction (See CD in Fig. 17). In the
case of the "WAr' instruction, the MPU enters the
"WAIT" cycle after stacking the internal registers and

outputs the "High" level on the BA line.
When an interrupt request signal is input to the
MPU, the MPU accepts the interrupt regardless the
"Halt" signal and releases the "WAIT" state and outputs the interrupt's vector address. If the "Halt" signal
is "Low" level, the MPU halts after the fetch of new
PC contents. The sequense is shown below.

WAI
Instruction
Fetch

I

I

Address
Bus
Vector
Address

A/iii

VMA

~

iRa or

NMi

~

BA

_ _ CD
HALT

When the interrupt occurs during the WAIT CYCLE, the MPU accepts the interrupt even if HALT is at "Low" level.

Figure 17 HD6802W WAIT CYCLE & HALT Request

252

$

HITACHI

Vector New PC
Address Address

H 06809, H 068A09, H 068809-

M PU

(Micro Processing Unit)

The H06809 is a revolutionary high perfonnance 8-bit
microprocessor which supports modem programming techniques such as position independence, reentrancy, and modular
programming.
This third-generation addition to the HMCS6800 family has
major architectural improvements which include additional
registers, instructions and addressing modes.
The basic instructions of any computer are greatly enhanced
by the presence of powerful addressing modes. The H06809 has
the most complete set of addressing modes available on any
8-bit microprocessor today.
The H06809 has hardware and software features which make
it an ideal processor for higher level language execution or
standard controller applications.
• PIN ARRANGEMENT
HD6800 COMPATIBLE
• Hardware - Interfaces with All HMCS6800 Peripherals
• Software - Upward Source Code Compatible Instruction Set and Addressing Modes

HAlT
XTAL
EXTAL

Rrs
MRDY

• ARCHITECTURAL FEATURES
• Two l6-bit Index Registers
• Two l6-bit Indexable Stack Pointers
• Two 8·bit Accumulators can be Concatenated to Form
One l6-Bit Accumulator
• Direct Page Register Allows Direct Addressing Thr~ugh­
out Memory
•
•
•
•

HARDWARE FEATURES
On Chip Oscillator
DMA/BREQ Allows DMA Operation or Memory Refresh
Fast Interrupt Request Input Stacks Only Condition
Code Register and Program Counter

•

MRDY Input Extends Data Access Times for Use With
Slow Memory

•

Interrupt Acknowledge Output Allows Vectoring By
Devices

•

SYNC Acknowledge Output Allows for Synchronization
to External Event

•
•
•

Single Bus-Cycle RESET
Single 5-Volt Supply Operation
NMI Blocked After RESET Until After First Load of
Stack Pointer

•
•

Early Address Valid Allows Use With Slower Memories
Early Write-Data for Dynamic Memories

•

Compatible with MC6809. MC68A09 and MC68B09

• SOFTWARE FEATURES
• 10 Addressing Modes
• HMCS6800 Upward Compatible Addressing Modes
• Direct Addressing Anywhere in Memory Map
• Long Relative Branches
• Program Gounter Relative
• True Indirect Addressing
• Expanded Indexed Addressing:

~HITACHI

Q

i5MA7Biml
R/W

HD6809

(Top View)

253

0, 5, 8, or 16·bit Constant Offsets
8, or 16·bit Accumulator Offsets
•
•

Auto-Increment/Decrement by 1 or 2
Improved Stack Manipulation
1464 Instructions with Unique Addressing Modes

•

8 x 8 Unsigned Multiply

•
•
•

16·bit Arithmetic
Transfer/Exchange All Registers
Push/PUll Any Registers or Any Set of Registers

•

Load Effective Address

• BLOCK DIAGRAM

4 - - Vcc

+--vss

PC

U

S

RES
NMI

Y
FIRQ

TRQ

X

o{

OMA/BREQ
R/W

A
B

HALT
BA
BS
XTAL
EXTAL
MROY
E
Q

254

~HITACHI

---------------------------------------------------HD6809,HD68A09,HD68B09
• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Value

Vee *
V in *

-0.3 ~ +7.0
-0.3 ~ +7.0
-20 ~ +75
-55 ~ +150

Supply Voltage
Input Voltage
Operating Temperature

Topr
Tstg

Storage Temperature

Unit
V
V

°c
°c

* With respect to Vss (SYSTEM GND)
(NOTE)

Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions are exceeded, it could affect reliability of LSI.

• RECOMMENDED OPERATING CONDITIONS
Item
Supply Voltage

Symbol

min

typ

max

Unit

Vee *
V 1L *

4.75
-0.3

5.0
-

5.25
0.8

V

2.0

-

Vee

2.2

-

Vee

4.0

-

Vee

-20

25

75

Logie

(Ta
Input Voltage

=0 -

+75°C)

Logie

V 1H *

(Ta

= -20 -

O°C)

RES
Operating Temperature

Topr

V

V

-

°c

* With respect to Vss (SYSTEM GND)

•

ELECTRICAL CHARACTERISTICS

•

DC CHARACTERISTICS (Vee =5V±5%, VSS = OV, Ta = -20~+75°C, unless otherwise noted.)
Item

Input "High" Voltage

Symbol
Except RES

V 1H

Test Condition
Ta = 0 - +75°C

min
2.0

Ta = -20 - O°C

2.2

RES
Input "Low" Voltage

V 1L

Input Leakage Current

Except EXTAL,
XTAL

lin

Three State (Off State)
Input Current

Do-D7
A o-A I5 ,R/W

ITs l

Output "High" Voltage

Vee

2.2

Vee

4.0

Vee

min
2.0

HD68B09
typ* max

Vee

2.2

Vee

4.0

-0.3

-

0.8

-0.3

-

0.8

V

-2.5

-

2.5

-2.5

-

2.5

IJ.A

-10
10
100 -100

-

10
100

-10

-

-100

-

100

4.0

-0.3

-

0.8

-2.5

-

2.5

-

-

Vee
Vee
Vee

-

-

Do-D7

I LOAO=-205IJ.A,
Vee=min

2.4

-

-

2.4

-

-

2.4

-

-

Ao-A", R/W,
a, E

I LOAO=-145IJ.A,
Vee=min

2.4

-

-

2.4

-

-

2.4

-

-

2.4

-

-

2.4

-

-

2.4

-

-

-

-

-

-

10

-

-

-

10

0.5
1.0

-

-

0.5
1.0

15

-

7

10

7

10

-

10
7

-

-

12

-

-

12

-

-

V OH

VOL
Po
Do-D7
Except Do-D7

Cin

Ao -A ls , R/W,
BA, BS

Cout

Vee=max

I LOAo--100IJ.A,
Vee=min
I LOAo =2mA

Vin=OV,
Ta=25°C,
f=1MHz

~HITACHI

Unit

-

-

!

HD68A09
tvp* max

-10

BA,BS

Output Capacitance

Vee

min
2.0

-100

Output "Low" Voltage
Power Dissipation
Input Capacitance

Vin-0-5.25V,
Vee=max
Vin=0.4-2.4 V,

HD6809
I tvp* max

15

10

V

IJ.A

V

0.5
1.0
15
10
12

V
W
pF
pF

255

• AC CHARACTERISTICS (Vcc=5V±5%, VSS
1. CLOCK TIMING

=OV, Ta = -20-+7SoC, unless otherwise noted.)
HD6809

Item
Frequency of Operation
(Crystal or External Input)

Symbol

HD68A09

HD68B09

Test Condition

Unit
min

typ

max

min

typ

4

0.4

-

10000 667

-

fXTAL

0.4

Cycle Time

tcyc

1000

Total Up Time

tUT

975

Processor Clock "High"

tpWEH

450

-

Processor Clock "Low"

tpwEL

430

E Rise and Fall Time

tEr. tEf

-

Fig. 2. Fig. 3

max

min

typ

6

0.4

-

max
8

MHz
ns

-

480

280

-

-

10000

15700

220

-

15700

5000

280

-

5000

210

-

5000

ns

25

-

-

25

-

-

20

ns

125

ns

-

640

15500

-

-

10000 500

-

E Low toOHigh Time

tAvS

200

-

250

130

80

tpWOH

450

-

5000

280

-

165

o Clock "High"
o Clock "Low"
o Rise and Fall Time

5000

220

tPWQL

450

-

15500

280

-

15700

220

-

-

25

-

-

tOE

200

-

-

133

-

25

0Low to E Falling

-

100

typ

max

min

typ

max

min

typ

max

-

140

-

tOr. tOf

ns
ns

5000

ns

15700

ns

20

ns

-

ns

2. BUS TIMING
Item

Symbol

HD6809

Test Condition
min

Address Delay
Address Valid to 0High
Peripheral Read Access Time
(tUT-tAo-toSR=tACC)
Data Set Up Time (Read)
Input Data Hold Time
Add,,§ Hold Tim.

I

A. -A". RJW

Data Delay Time (Write)
Output Hold Time

-

tAD
tAO
tACC

Fig. 2. Fig. 3

tAH
tDDW
toHW

Fig. 2. Fig. 3
Ta=0-+75°C
Fig. 2. Fig. 3
Ta=-20-0°C
Fig. 3
Fig.3
Ta=0-+75°C
Fig.3
Ta=-20-0°C

HD68B09

Unit

-

200

-

-

25

-

-

15

-

110

-

-

ns
ns

695

-

-

ns

40
10

-

-

-

ns
ns

20

-

-

-

-

-

330

-

-

440

80
10

20

-

-

ns

10

-

-

10

-

-

10

-

-

ns

-

-

200

-

-

140

-

110

ns

30

-

-

30

-

-

30

-

-

ns

20

-

-

20

-

-

20

-

-

ns

max

min
125
140
140
140
125

typ

max

-

-

min
110

50

toSR
toHR

HD68A09

60
10
20

3. PROCESSOR CONTROL TIMING
Item
MRDY Set Up Time
Interrupts Set Up Time
HALT Set Up Time
RES Set Up Time
DMA/BREO Set Up Time
Processor Control Rise and Fall Time
Crystal Oscillator Start Time

256

Symbol

Test Condition

tpCSM
tpr.!':
tpCSI-l
tpCSR
tpCSo
tPCr,
tpCf
tRC

Fig. 6-Fig. 10
Fig. 14, Fig. 15

HD6809
min
125
200
200
200
125

typ

-

-

~HITACHI

-

-

HD68A09

-

-

-

100
50

-

-

-

~

-

HD68B09

-

110
110
110
110

tvp

max

-

-

-

Unit
ns
ns
ns
ns
ns

100

-

-

100

ns

30

-

-

30

ms

----------------------------------------------------HD6809,HD68A09,HD68B09
5.0V

'C= 30pF (BA, BS)

RL = 1.8kn

Test Point

o--~~~t_-__fII......-

130pF (Do - D 7 , E, a)
90pF (Ao - Au, R/W)

• R = 11kn (Do - D 7 )

...

16kn (Ao - Au, E,
24kn (BA, BS)

R

_

a, R/W)

All diodes are 1S20749 or equivalent.
C includes Stray Capacitance.

Figure 1 Bus Timing Test Load

Rfii

---or

~NotValid
*Hold time for BA, BS not specified.

Figure 2 Read Data from Memory or Peripherals

~NotV'ljd
*Hold time for BA, BS not specified.

Figure 3 Write Data to Memory or Peripherals

• PROGRAMMING MODEL
As shown in Figure 4, the HD6809 adds three registers to the
set available in the HD6800. The added registers include a
Direct Page Register, the User Stack pointer and a second Index
Register.
•

Accumulators (A. B. D)

The A and B registers are general purpose accumulators
which are used for arithmetic calculations and manipulation of
data.
Certain instructions concatenate the A and B registers to
form a single 16-bit accumulator. This is referred to as the D

register, and is formed with the A register as the most significant
byte.
•

Direct Page Regi!lter (DP)

The Direct Page Register of the HD6809 serves to enhance
the Direct Addressing Mode. The content of this register appears
at the higher address outputs (As -AI s) during Direct Addressing Instruction execution. TQis allows the direct mode to be
used at any place in memory, under program control. To ensure
HD6800 compatibility, all bits of this register are cleared during
Processor Reset.

eHITACHI

257

offset. During some indexed modes, the contents of the index
register are incremented or decremented to point to the next
item of tabular type. data. All four pointer registers (X, Y, U, S)
may be used as index registers.

•

Index Registers (X. Y)
The Index Registers are used in indexed mode of addressing.
The 16-bit address in this register takes part in the calculation of
effective addresses. This address may be used to point to data
directly or may be modified by an optional constant or register

o

15

x-

Index Register

Y - Index Register

} Po;"" R.,;,.."

U - User Stack Pointer
S - Hardware Stack Pointer
PC

Program Counter

1

A
\.

B

Accumulators
I

~

D
7

0

--li

D_P_ _ _ _

L . . I_ _ _ _ _

7

Direct Page Register

0

I ElF I H II I N I z I V I C

I

cc -

Condition Code Register

Figure 4 Programming Model of The Microprocessing Unit

• Stack Pointer (U. S)
The Hardware Stack Pointer (S) is used automatically by the
processor during subroutine calls and interrupts. The stack
pointers of the HD6809 point to the top of the stack, in
contrast to the HD6800 stack pointer, which pointed to the
next free location on the stack. The User Stack Pointer (U) is
controlled exclusively by the programmer thus allowing arguments to be passed to and from subroutines with ease. Both
Stack Pointers have the same indexed mode addressing capabilities as the X and Y registers, but also support Push and Pull
instructions. This allows the HD6809 to be used efficiently as a
stack processor, greatly enhancing its ability to support higher
level languages and modular programming.
• Program Counter
The Program Counter is used by the processor to point to the
address of the next instruction to be executed by the processor.
Relative Addressing is provided allowing the Program Counter
to be used like an index register in some situations.

• CONDITION CODE REGISTER DESCRIPTION
•

Bit 0 (C)
Bit 0 is the carry flag, and is usually the carry from the
binary ALU. C is also used to represent a 'borrow' from subtract
like instructions (CMP, NEG, SUB, SBC) and is the complement
of the carry from the binary ALU.
•

Bit 1 (V)
Bit 1 is the overflow flag, and is set to a one by an operation
which causes a signed two's complement arithmetic overflow.
This overflow is detected in an operation in which the carry
from the MSB in the ALU does not match the carry from the
MSB-l.

• Bit 2 (Z)
Bit 2 is the zero flag, and is set to a one if the resul t of the
previous operation was identically zero.
•

• Condition Code Register
The Condition Code Register defines the State of the
Processor at any given time. See Fig. S.

Bit 3 (N)
Bit 3 is the negative flag, which contains exactly the value of
the MSB of the result of the preceding operation. Thus, a
negative two's-complement result will leave N set to a one.

•

Bit 4 (I)
Bit 4 is the IRQ mask bit. The processor will not recognize
interrupts from the 1RO line if this bit is set to a one. NMI,
FIRQ, iRO', RES, and SWI all are set I to a one; SWI2 and SWI3
do not affect I.

Carry
Overflow
'-----Zero
' - - - - - - Negative
' - - - - - - - IRQ Mask
' - - - - - - - - - Half Carry
L - -_ _ _ _ _ _ _ _ FIRQ Mask

• Bit 5 (H)
Bit 5 is the half-carry bit, and is used to indicate a carry' from
bit 3 in the ALU as a result of an 8-bit addition only (ADC or
ADD). This bit is used by the DAA instruction to perform a
BCD decimal add adjust operation. The state of this flag is

' - - - - - - - - - - - Entire Flag

Figure 5 Condition Code Register Format

258

$

HITACHI

Table 1 Memory Map for Interrupt Vectors

undefined in all subtract-like instructions.
•

Memory Map For
Vector Locations

Bit 6 (F)

Bit 6 is the FIRQ mask bit. The processor will not recognize
interrupts from the FIRQ line if this bit is a one. NMI, FIRQ,
SWI, and RES all set F to a one. IRQ; SWI2 and SWI3 do not
affect F.
• Bit 7 (E)
Bit 7 is the entire flag, and when set to a one indicates that
the complete machine state (all the registers) was stacked,--as
opposed to the subset state (pC and CC). The E bit of the
stacked CC is used on a return from interrupt (RT!) to
determine the extent of the un stacking. Therefore, the current
E left in the Condition Code Register represents past action.
• SIGNAL DESCRIPTION
Power (Vss , Veel
Two pins are used to supply power to the part: VSS is
ground or 0 volts, while VCC is +5.0V ±5%.

•

• Address Bus (Ao-A1s )
Sixteen pins are used to output address information from the
MPU onto the Address Bus. When the processor does not
require the bus for a data transfer, it will output address
FFFF 16 , R/W = "High", and BS = "Low"; this is a "dummy
access" or VMA cycle. Addresses are valid on the rising edge of
Q (see Figs. 2 and 3). All address bus drivers are made high
impedance when output Bus Availalbe (BA) is "High". Each pin
will drive one Schottky TTL load or four LS TTL loads, and
typicany 90 pF.

MS

LS

FFFE
FFFC
FFFA
FFF8
FFF6
FFF4
FFF2
FFFO

FFFF
FFFD
FFFB
FFF9
FFF7
FFF5
FFF3
FFF1

Interrupt Vector
Description
RES
NMI
SWI
IRQ
FIRQ
SWI2
SWI3
Reserved

• HALT
A "Low" level on this input pin will cause the MPU to stop
running at the end of the present instruction and remain halted
indefinitely without loss of data. When halted, the BA output is
driven "High" indicating the buses are high impedance. BS is
also "High" which indicates the processor is in the Halt or Bus
Grant state. While halted, the MPU will not respond to external
real-time requests (FIRQ, IRQ) although DMA/BREQ will
always be accepted, and NMI or RES will be latched for later
response. During the Halt state Q and E continue to run
normally. If the MPU is not running (RES, DMA/BREQ). a
halted state (BA· BS= 1) can be achieved by pulling HALT
"Low" while RES is still "Low". If DAM/BREQ and HALT arc
both pulled "Low", the processor will reach the last cydc of thc
instruction (by reverse cycle stealing) where the machinc will
then become halted. See Figs. 8 and 16.
•

• Data Bus (Do -0 7 )
These eight pins provide communication with the system
bi-directional data bus. Each pin will drive one Schottky TTL
load or four LS TTL loads, and typically 130 pF.
•

ReadJWrite (R/W)
This signal indicates the direction of data transfer on the data
bus. A "Low" indicates that the MPU is writing data onto the
data bus. R/W is made high impedance when BA is "High". R/W
is valid on the rising edge of Q. Refer to Figs. 2 and 3.
Reset (RES)
A "Low" level on this Schmitt-trigger input for greater than
one bus cycle will reset the MPU, as shown in Fig. 6. The Reset
vectors are fetched from locations FFFE16 and FFFF16 (Table
1) when Interrupt Acknowledge is true, (BA • BS=I). During
initial power-on, the Reset line should be held "Low" until the
clock oscillator is fully operational. See Fig. 7.
Because the HD6809 Reset pin has a Schmitt-trigger input
with a threshold voltage higher than that of standard peripherals,
a simple RIC network may be used to reset the entire system.
This higher threshold voltage ensures that all peripherals are out
of the reset state before the Processor.

Bus Available, Bus Status (BA, BS)
The BA output is an indication of an internal control signal
which makes the MOS buses of the MPU high impedance. This
signal does not imply that the bus will be available for more
than one cycle. When BA goes "Low", an additional dead cycle
will elapse before the MPU acquires the bus.
The BS output signal, when decoded with BA, represents the
MPU state (valid with leading edge of Q).

Table 2 MPU State Definition

•

°

$

BA

BS

a
a

a
1

a
1

MPU State
Normal (Running)
Interrupt or RESET Acknowledge
SYNC Acknowledge
HALT or Bus Gfant

Interrupt Acknowledge is indicated during both cycles of a
hardware-vector-fetch (RES, NMI, FIRQ, IRQ, SWI, SWI2,
SWI3). This signal, plus decoding of the lower four address lines,
can provide the user with an indication of which interrupt level
is being serviced and allow vectoring by device. See Table 1.
Sync Acknowledge is indicated while the MPU is waiting for
external synchronization on an interrupt line.
Halt/Bus Grant is true when the HD6809 is in a Halt or Bus
Grant condition.

HITACHI

259

I\)

:J:

C»

o

o

CD

CD

o

!D

:t:

o

CD

CO

o>

~

:J:

o

%'

",,::,.\\\\~\\

CD

Rr;;.\\Ss\S\\s{~
~~ Ss\\\SSS\\~

~"r'T,""~M~

SA

ViiA

\\SS\\\\S~
~~

I

~

~

In"::;~~",n

H

\

Sf

,-

Figure 6 RES Timing

e:J:
()

c

C!~

4.75V

Vcc
E

---+----f

RES

tRC

HD6809

VI
8MHz
6MHz
4 MHz

Cin

Cout

18pF±20% 18pF±20%
22pF±20% 22 pF ± 20%
22pF±20% 22 pF ± 20%

38

qnI

Figure 7 Crystal Connections and Oscillator Start Up

VJ

39

T
rrr

Coot

~'--_ _ __

CO
aJ

oCD

--------------------------------------------------HD6809,HD68A09,HD68B09
•

Non Maskable Interrupt (NMI)*

A negative edge on this input requests that a non-maskable
interrupt sequence be generated. A non-maskable interrupt
cannot be inhibited by the program, and also has a higher
priority than FIRQ, IRQ or software interrupts. During recognition of an NMI, the entire machine state is saved on the
2nd To Last
Cycle Of
Current
Ins!.

I

I

Las! Cycle
Of
Current
Dead
Ins!. \. Cycle

hardware stack. After reset, an NMI will not be recognized until
the first program load of the Hardware Stack Pointer (S). The
pulse width of NMI "Low" must be at least one E cycle. If the
NMI input does not meet the minimum set up with respect to
Q, the interrupt will not be recognized until the next cycle. Set'
Fig. 9.

H=--_ _ _ _....:.:Ha~lt:::ed:::__ _ _ _~~--'-'..:...._I___--I-~::.::.::c::.r_..:....-I-,.....:.H:::a:.::lte::.:::d~

\.

Q

~--~.~-----------------~~-----

Address
Bus

Fetch

Execute

r---)r--~------~J~----------------------~,r--------,'----------

R/W

11

BA ________________~/
BS _________________--J

\~____________~/

1----------

--------------------""""'1\

,-------i('~

~--~~------------------~~---Instruction

Data

Bus

Opcode

Figure 8 HALT and Single Instruction Execution for System Debug

Last Cycl.
of Current
Instruction
I""- - + I - - - - - - - - - - - - - I n t e r r u p t Stacking and Vector Fetch Sequence

Instruction
Fetch

------------_+-1___.1

a

UL

UH

YL

YH

XL

Figure 9 I RQ and NMI Interrupt Timing

eHITACHI

261

loItCycl.
ofCurr.nt

Instruction

Instruction

Fetch

fool--fool_______ Int.rrupt Stlckinglnd Vector FItch 5 e Q u e n c : e - - - - - - _ I - - _ - i

a
~~~,~~~~--~/----\~--~,--~'r---~r--~r---~--~.r---'r--~,r---~--~,r---~­

Bu.

~

tP~1r tpcs
VIH

~~O.~8V~

PC

PC

FFFF

5P-l

5P-2

5P-3

FFFF

FFF6

FFF7

FFFF

NlwPC NewPC+l

_________________________________________________________________

~. _ _~_ _ _ _,~_ _~_ _~,~_ _~~_ _~,~_ _~_ __J~_ _J~___J.~_ _J~___J.~_ _J~___J~_ __

PCl

VJ;UJ;

PCH

CC

VJ;UJ;

New PCH

New PCl

imA

\'-____--J!

Figure 10 FIRQ Interrupt Timing

•

Fast-Interrupt Request (FIRQ)*
A "Low" level on this input pin will initiate a fast interrupt
sequence provided its mask bit (F) in the CC is clear. This
se~nce has priority over the standard Interrupt Request
(IRQ), and is fast in the sense that it stacks only the contents of
the condition code register and the program counter. The
interrupt service routine should clear the source of the interrupt
before doing an RTI. See Fig. 10.

• Interrupt Request (lRQ)*
A "Low" level input on this pin will initiate an interrupt
Request sequence provided the mask bit (I) in the CC is clear.
Since IRQ stacks the entire machine state it provides a slower
response to interrupts than FIRQ. IRQ also has a lower priority
than FIRQ. Again, the interrupt service routine should clear the
source of the interrupt before doing an RTI. See Fig. 9.

*

near the LSI as much as possible.
Normal oscillation may be disturbed when external noise is
( induced to pin 38 and 39.

2) Pin 38 and 39 signal line should be wired apart from other
signal line as much as possible. Don't wire them in parallel.
Normal oscillation may be disturbed when E or Q signal is ..,
( feedbacked to pin 38 and 39.
J

o

J..:.:-:":':':="'---II

< NOTE FOR BOARD DESIGN OF THE OSCILLATION
CIRCUIT>
In designing the board, the following notes should be taken
when the crystal oscillator is used.

1) Crystal oscillator and load capacity Cin, Cout must be placed

262

$

cOl

ch

NMI, FIRQ, and IRQ requests are sampled on the falling
edge of Q. One cycle is required for synchronization before
these interrupts are recognized. The pending interrupt(s)
will not be serviced until completion of the current instruction unless a SYNC or CWAI condition is present. If IRQ and
FIRQ do not remain '~Low" until completion of the current
instruction they may not be recognized. However, NMI is
latched and need only remain "Low" for one cycle.

• XTAL, EXTAL
These inputs are used to connect the on-chip oscillator to an
external parallel-resonant crystal. Alternately, the pin EXTAL
may be used as a TTL level input for external timing by
grounding XTAL. The crystal or external frequency is four
times the bus frequency. See Fig. 7. Proper RF layout
techniques should be observed in the layout of printed circuit
boards.

J

HD6809

Figure 11 Board Design of the Oscillation Circuit.


A signal line or a power source line must not cross or go near
the oscillation circuit line as shown in Fig. 12 to prevent the
induction from these lines and perform the correct oscillation.
The resistance among XT AL, EXT AL and other pins should b(l
over lOMil.

HITACHI

--------------------------------------------------HD6809,HD68A09,HD68B09
• E,a
E is similar to the HD6800 bus timing signal tP2; Q is a
quadrature clock signal which leads E. Q has no parallel on the
HD6800. Addresses from the MPU will be valid with the leading edge of Q. Data is latched on the falling edge of E. Timing
for E and Q is shown in Fig. 13.

Must be avoided.

«aI
~(i

c:

CI

c:

CI

(i)(i)

o

1

:

f\

•

t---'-..L.....-----Signal C
Cout

MRDY

This input control signal allows stretching of E and Q to
extend data-access time. E and Q operate normally while MRDY
is "High". When MRDY is "Low", E and Q may be stretched in
integral multiples of quarter (1/4) bus cycles, thus allowing
interface to slow memories, as shown in Fig. 14. A maximum

~
Ci'::rir

HD6809

Figure 12 Example of Normal Oscillation may be Disturbed.

Start o~ Cycle

End of Cycle ~ Latch Datal

I

E

I

t

\_O_.5_V_____ 1
f--t
AVS

Q

I

I
I

1

:

...J

-2-.4-V------------~"

O.5V

I

~.----~I-------

Address Valid

I

Figure 13 E/Q Relationship

\_--11

2.4V=\ f~
r
!'------~
I
I

I

Q

MRDY

I

\'--_--JI

\----.,..:~f~f

________________________________~~~tP~c~'~
\\\\\~

I

_--J

-jJ;._tP_c_r___________

fr--110~~~

Figure 14 MRDY Timing

~HITACHI

263

stretch is 10 microseconds. During non valid memory access
(VMA cycles) MRDY has no effect on stretching E and Q; this,
inhibits slowing the processor during "don't care" bus accesses.
MRDY may also be used to stretch docks (for slow memory)
when bus control has been transferred to an external device
(through the use of HALT and DMA/BREQ).
Also MRDY has effect on stretching E and Q during Dead Cycle.
•

DMA/BREQ

The DMAfBREQ input provides a method of suspending
execution and acquiring the MPU bus for another use, as shown
in Fig. 15. Typical uses include DMA and dynamic memory
refresh.
Transition of DMA/BREQ should occur during Q. A "Low"
level on this pin will step instruction execution at the end of the
current cycle. The MPU will acknowledge DMA/BREQ by
setting BA and BS to "High" level. The requesting device will
now have up to 15 bus cycles before the MPU retrieves the bus
for self-refresh. Self-refresh requires one bus cycle with a leadMPU

DEAD

ing and trailing dead cycle. See Fig. 16.
Typically, the DMA controller will request to use the bus by
asserting DMA/BRE9 pin "Low" on the leading edge of E.
When the MPU replies by setting BA and BS to a one, that cycle
will be a dead cycle used to transfer bus mastership to the DMA
controller.
False memory accesses may be prevented during and dead
cycles by developing a system DMAVMA signal which is "Low"
in any cycle when BA has changed .
When BA goes "Low" (either as a result of DMA/BREQ =
"High" or MPU self-refresh), the DMA device should be taken
off the bus. Another dead cycle will elapse before the MPU
accesses memory, to allow transfer of bus mastership without
contention.
•

MPU OPERATION

During normal operation, the MPU fetches an instruction
from memory and then executes the requested function. This

DEAD

DMA

MPU

E

o
DMA/BREO

BA. BS

DMAVMA*

\

/

C

)

ADDR
(MPU)

ADDR
(OMAC)

(

*OMAVMA is a signal which is developed externally. but is a system requirement for OMA.
Figure 15 Typical DMA Timing «14 Cycles)

264

\.-

/

~HITACHI

>

!oEAoI""".---------14 OMA cycles-------------l.loEAO/ MPU

IDEA~OMA-

I

I

I

I

I

I

I

I

I
I

I

I

I

I

E
Q

DMA/BREQ

BA, BS
DMAVMA*

\,

I
I

I

!
~~~I~---------- - -Ir-~------------------------------------------------~~
/
I~
I

::,.--i~\____________

!~,I:~
1

I
,
~

I'

*DMAVMA is a signal which is developed externally, but is a system requirement for DMA.

Figure 16 Auto - Refresh DMA Timing
(Reverse Cycle Stealing)

sequence begins at RES and is repeated indefinitely unless
altered by a special instruction or hardware occurrence. Soft·
ware instructions that alter normal MPU operation are: SWI,
SWI2, SWI3, CWAI, RTI and SYNC. An interrupt, HALT or
DMA/BREQ can also alter the normal execution of instructions.
Fig. 17 illustrates the flow chart for the HD6809.

• ADDRESSING MODES
The basic instructions of any computer are greatly enhanced
by the presence of powerful addressing modes. The HD6809 has
the most complete set of addressing modes available on any
microcomputer today. For example, the HD6809 has 59 basic
instructions; however, it recognizes 1464 different variations of
instructions and addressing modes. The addressing modes
support modern programming techniques. The following ad·
dressing modes are available on the FlD6809:
(1) Implied (Includes Accumulator)
(2) Immediate
(3) Extended
(4) Extended Indirect
(5) Direct
(6) Register
(7) Indexed
Zero·Offset
Constant Offset
Accumulator Offset
Auto Increment/Decrement
(8) Indexed Indirect
(9) Relative
(10) Program Counter Relative
Implied (Includes Accumulator)
In this addressing mode, the opcode of the instruction
contains all the address information necessary. Examples of
Implied Addressing are: ABX, DAA, SWI, ASRA, and CLRB.

Immediate Addressing
In Immediate Addressing, the effective address of the data is
the location immediately following the opcode (i.e., the data to
be used in the instruction immediately follows the opcode of
the instruction). The HD6809 uses both 8 and 16·bit immedi,~e
values depending on the size of argument specified oy the
opcode. Examples of instructions with Immediate Addressing
are:
LDA #$20
LDX #$FOOO
LDY #CAT
(NOTE) # signifies Immediate addressing, $ signifies hexa·
decimal value.

•

•

Extended Addressing
In Extended Addressing, the contents of the two bytes
immediately following the opcode fully specify the 16·bit
effective address used by the instruction. Note that the address
generated by an extended instruction defines an absolute
address and is not position independent. Examples of Extended
Addressing include:
LDA
CAT
STX
MOUSE
LDD
$2000

•

Extended Indirect
As a special case of indexed addressing (discussed below),
"I" level of indirection may be added to Extended Addressing.
In Extended Indirect, the two bytes follOWing the postbyte of
an Indexed instruction contain the address of the data.
LDA
[CAT]
LDX
[$FFFE]
STU
[DOG]

•

$

•

Direct Addressing
Direct addressing is similar to extended addreSSing except
that only one byte of address follows the opcode. This byte
specifies the lower 8·bit of the address to be used. The upper
8·bit of the address are supplied by the direct page register. Since
only one byte of address is required in direct addressing, this
mode requires less memory and executes faster than extended
addressing. Of course, only 256 locations (one page) can be

HITACHI

265

I\:)
(J)
(J)

::I:

o

'FiRQ.1'

en

0)

o

~

:::I:

o

en

0)

»

()->DPR
l-->F, I
l-->Rfiii

o

~
::I:

ClrNMT
Logic

o

Disarm NMI
-r--

en

0)

CD

o(0

J:

~

(')

FFF4
FFF2

:§

HD6809 Interrupt Structure
Bus State

BA

BS

Running

o
o

o

I nterrupt or Reset Acknowledge
Sync
Halt/Bus Grant
(NOTE)

Asserting RES will result in entering the reset sequence from any point in the flow chart.

Figure 17 Flowchart for HD6809 Instruction

o

------------------------HD6809,HD68A09,HD68B09
accessed without redefining the contents of the DP register.
Since the DP register is set to $00 on Reset, direct addressing on
the HD6809 is compatible with direct addressing on the
HD6800. Indirection is not allowed in direct addressing. Some
examples of direct addressing are:
LDA
$30
SETDP
$10 (Assembler directive)
LDB
$1030
LDD
- X Adds 5-bit constant 10 to X
X + 500 ->- X Adds 16-bit constant 500 to X
Y + A ->- Y Adds 8-bit accumulator to Y
Y + D ->- Y Adds 16-bit 0 accumulator to Y
U - 10 ->- U Subtracts 10 from U
S -10 ->- S Used to reserve area on stack
S + 10 -'> S Used to 'clean up' stack
S+ 5
->- X
Transfers as well as adds

FFFF16 on the address bus, R/W="High" and BS="Low".
The following examples illustrate the use of the chart; see Fig.
20.
Example 1: LBSR (Branch Taken)
Before Execution SP = FOOO

LBSR

$8000

CAT

MUL

Multiplies the unsigned binary numbers in the A and B
accumulator and places the unsigned result into the 16-bit D
accumulator. This unsigned multiply also allows multipleprecision multiplications.

The HD6809 has the capability of program counter relative
branching throughout the entire memory map. In this mode, if
the branch is to be taken, the 8 or 16-bit signed offset is added
to the value of the program counter to be used as the effective
address. This allows the program to branch anywhere in the 64k
memory map. Position independent code can be easily generated through the use of relative branching. Both short (8-bit)
and long (16-bit) branches are available.

6

Address
8000
8001
8002
FFFF
FFFF
AOOO

7
8

FFFF
EFFF

03

*

1
0

9

EFFE

80

0

Data
17
IF
FD

*
*
*

R/W
1
1
1
1
1
1

Description
Opcode Fetch
Offset High Byte
Offset Low Byte
VMACycle
VMACycle
Computed Branch
Address
VMA Cycle
Stack Low Order
Byte of Return
Address
Stack High Order
Byte of Return
Address

Example 2: DEC (Extended)
$8000
$AOOO

$AOOO
$80

DEC
FCB

CYCLE-BY-CYCLE FLOW

Software Interrupts

A Software Interrupt is an instruction which will cause an
interrupt, and its associated vector fetch. These Software Interrupts are useful in operating system calls, software debugging, trace operations, memory mapping, and software development systems. Three levels of SWI are available on this
HD6809, and are prioritized in the following order: SWI, SWI2,
SWI3.

Cycle #
1
2
3
4

5

SYNC

After encountering a Sync instruction. the MPU enters a
Sync state, stops processing instructions and waits~ an
interrupt. If the pending interrupt is non-maskable (NMI) or
maskable (FIRQ, IRQ) with its mask bit (F or I) clear, the
processor will clear the Syne state and perform the ~mal
interrupt stacking and service routine. Since FIRQ and IRQ are
not edge-triggered, a "Low" level with a minimum quration of
three bus cycles is required to assure that the interrupt will be
taken. If the pending interrupt is maskable (FIRQ, IRQ) with its
mask bit (F or I) set, the processor will clear the Sync state and
continue processing by executing the next inline instruction.
Fig. 19 depicts Sync timing.

CAT
CYCLE-BY-CYCLE FLOW

Long And Short Relative Branches

•

$ AOOO

Cycle #
1
2

Address
8000
8001

Data
7A
AO

3

8002

00

4
5

FFFF
AOOO
FFFF
AOOO

6
7

*

80

*

7F

Description
Opcode Fetch
Operand Address,
High Byte
Operand Address,
Low Byte
1
VMACycle
1
Read the Data
VMACycle
1
Store the Decre0
mented Data
that particular address.
R/W
1
1

*

The data bus has the data at

•

HD6809 INSTRUCTION SET TABLES

16-Bit Operation

The HD6809 has the capability of processing 16-bit data.
These instructions include loads, stores, compares, adds, subtracts, transfers, exchanges, pushes and pulls.
•

CYCLE-BY-CYCLE OPERATION

The address bus cycle-by-cycle performance chart illustrates
the memory-access sequence corresponding to each possible
instruction and addressing mode in the HD6809. Each instruction begins with an opcode fetch. While that opcode is being
internally decoded, the next program byte is always fetched.
(Most instructions will use the next byte, so this technique
conSiderably speeds throughput.) Next, the operation of each
opcode will follow the flow chart. VMA is an indication of
270

$

The instructions of the HD6809 have been broken down into
five different categories. They are as follows:
8-Bit operation (Table 5)
16-Bit operation (Table 6)
Index register/stack pointer instructions (Table 7)
Relative branches (long or short) (Table 8)
Miscellaneous instructions (Table 9)
HD6809 instruction set tables and Hexadecimal Values of
instructions are shown in Table 10 and Table II.

HITACHI

--------------------------------------------------H06809,H068A09,H068809
Last Cycle
Sync
of Previous Opc:ode
,Instruction, Fetch , Execute ,

Last Cycle
of Sync
,Instruction,

Sync Acknowledge

'Ij

a
Add,asl
Data

----)(----l{~~~~~I)------------------~---------1--------------------<-~~J(
~

____

-'~~

__

_J.~

_ _ _ J . ' __ _ _ J

,

R/W~
BA:::A~

____~____~_____

________~I

~:::A~----------------------~~r------~-----------------------------

-l!-+t

~ ------------------------------------------~~~.----~V~;1lj
O.8~

Fi'F«:i

(NOTES)

*
**

PCf

**

f-- tpcs

If the associated mask bit is set when the interrupt is reques~his ~ will be an instruction fetch from address location PC + 1.
However, if the interrupt is accepted (NMI or an unmasked FIRO or IRO) interrupt processing continues with this cycle as (m) on Figure 9
and 10 (Interrupt Tim~
___
If mask bits are clear, IRO and FIRO must be held "Low" for three cycles to guarantee that interrupt will be taken, although only one
cycle is necessary to bring the processor out of SYNC.

Figure 19 Sync Timing

~

Opcode (Fetch)

Short
flranch

Immediate

Indexed

&

Inherent

Opcode +

ACCAOffset
ACCB Offset
R + 5 Bit
A + 8 Bit
PC + 8 Bit

Auto
InclDec
By 1

Auto
R + 16·Blt
Inc/Dec
By 2

RtD

PC + E.. end.d No Offset
16-81t tndirect

Opcode + Opcode + Opcode + Opcode +
Opcode + Opcode + Opcode + Opcode +

vk~wk:
vkwk~
vMA

ADDR
I

'\i1JA

I

Stack (Write)
Stack (Write)

(NOTE)

Write operation during store instruction.

Figure 20 Address Bus Cycle-by-Cycle Performance

_HITACHI

271

Implied Page

ASLA
ASLB
ASRA
ASRB
CLRA
CLRB
COMA
COMB
DAA
DECA
DECB
INCA
INCB
LSLA
LSLB
LSRA
LSRB
NEGA
NEGB
NOP
ROLA
ROLB
RORA
RORB
SEX
TSTA
TSTB

ABX

RTS

TFR

EXG

MUL

PSHU
PSHS

PULU
PULS

V A
VMA

VMA

RTI

liMA

I

STACK'

(wrr

12xSTACK

(Oum"1Y Read)

{~~~i7~)I~

STACK
STACK

CWAI

SWI
SWI2
SW13

VMA

VMA

VMA
VMA

I

STACK
{(Writel

I

VECTOR
VECTOR
VMA

12

)b

I

T~::: 1

1
(NOTE)

STACK':
STACK":

Address stored in stack pointer before execution.
Address set to stack pointer as the result of the execution.

Figure 20 Address Bus Cycle·by·Cycie Performance (Continued)

Non-Implied
~~---'----~----~----~----'-----~--~~----~END
ADCA
ADCB
ADDA
ADDB
ANDA
ANDB
BITA
BITB
CMPA
CMPB
EORA
EORB
LOA
LOB
ORA
ORB
SBCA
SBCB
STA
STB
SUBA
SUBB

LDD
LOS
LOU
LOX
LOY
ANDCC
ORCC

ASL
ASH
CLR
COM
DEC
INC
LSL
LSA
NEG
AOL
AOA

TST

ADDD
CMPD
CMPS
CMPU
CMPX
CMPY
SUBD

JSA

STD
STS
STU
STX
STY

VMA
STACK
VMA

VMA

ADDA +

~~~he~

ADDA +

1'1 rI r']"'

Figure 20 Address Bus Cycle-by-Cycle Performance (Continued)

272

_HITACHI

- - - - - - - - - - - - - - - - - - - -------HD6809,HD68A09,HD68B09
Table 58-Bit Accumulator and Memory Instructions
Mnemonic(s)

Operation

AOCA,AOCB

Add memory to accumulator with carry

AOOA,AOOB

Add memory to accumulator

ANOA,ANOB

And memory with accumulator

ASL, AS LA, ASLB

Arithmetic shift of accumulator or memory left

ASR, ASRA, ASRB

Arithmetic shift of accumulator or memory right

BITA, BITB

Bit test memory with accumulator

CLR,CLRA,CLRB

Clear accumulator or memory location

CMPA, CMPB

Compare memory from accumulator

COM, COMA, COMB

Complement accumultor or memory location

OAA

Decimal adjust A accumulator

DEC, OECA, OECB

Decrement accumulator or memory location

EORA, EORB

Exclusive or memory with accumulator

EXG Rl, R2

Exchange Rl with R2 (Rl, R2 =A, B, CC, OP)

INC, INCA, INCB

Increment accumulator or memory location

LOA, LOB

Load accumulator from memory

LSL, LSLA, LSLB

Logical shift left accumulator or memory location

LSR, LSRA, LSRB

Logical shift right accumulator or memory location

MUL

Unsigned multiply (A x B ~ D)

NEG,NEGA,NEGB

Negate accumulator or r;nemory

ORA, ORB

Or memory with accumulator

ROL, ROLA, ROLB

Rotate accumulator or memory left

ROR,RORA,RORB

Rotate accumulator or memory right

SBCA, SBCB

Subtract memory from accumulator with borrow

STA, STB

Store accumulator to memory

SUBA, SUBB

Subtract memory from accumulator

TST, TSTA, TSTB

Test accumulator or memory location

TFR Rl, R2

Transfer Rl to R2 (Rl, R2 = A, B, CC, OP)

-...

---_.-

(NOTE) A, B, CC or DP may be pushed to (pulled from) either stack with PSHS, PSHU
(PULS, PULU) instructions.

Table 6 l6-Bit Accumulator and Memory Instructions
Mnemonic(s)

Operation

AOOO

Add memory to 0 accumulator

CMPO

Compare memory from 0 accumulator

EXG 0, R

Exchange 0 with X, Y, S, U or PC

LOO

Load 0 accumulator from memory

SEX

Sign Extend B accumulator into A accumulator

STO

Store 0 accumulator to memory

SUBO

Subtract memory from 0 accumulator

TFR O,R

Transfer 0 to X, Y, S, U or PC

TFR R,O

Transfer X, Y, S, U or PC to 0

(NOTE)

0 may be pushed (pulled) to either stack with PSHS, PSHU (PULS, PULU)
instructions.

eHITACHI

273

Table 7 Index Register/Stack Pointer Instructions
Mnemonic(s)

Operation

CMPS, CMPU

Compare memory from stack pointer

CMPX, CMPY

Compare memory from index register

EXG Rl, R2

Exchange D, X, Y, S, U or PC with D, X, Y, S, U or PC

LEAS, LEAU

Load effective address into stack pointer

LEAX, LEAY

Load effective address into index register

LDS, LDU

Load stack pointer from memory

LDX, LDY

Load index register from memory

PSHS

Push A, B, CC, DP, D, X, Y, U, or PC onto hardware stack

PSHU

Push A, B, CC, DP, D, X, Y, S, or PC onto user stack

PULS

Pull A, B, CC, DP, D, X, Y, U or PC from hardware stack

PULU

Pull A, B, CC, DP, D, X, Y, S or PC from user stack

STS, STU

Store stack pointer to memory

STX, STY

Store index register to memory

TFRR1,R2

Transfer D, X, Y, S, U or PC to D, X, Y, S, U or PC

ABX

Add B accumulator to X (unsigned)

Table 8 Branch Instructions
Mnernonic(s)

Operation

BEQ, LBEQ

Branch if equal

SIMPLE BRANCHES
BNE, LBNE

Branch if not equal

BMI, LBMI

Branch if minus

BPL,LBPL

Branch if plus

BCS,LBCS

Branch if carry set

BCC,LBCC

Branch if carry clear

BVS, LBVS

Branch if overflow set

BVC, LBVC

Branch if overflow clear

BGT,LBGT

Branch if greater (signed)

SIGNED BRANCHES
BGE, LBGE

Branch if greater than or equal (signed)

BEQ, LBEQ

Branch if equal

BLE,LBLE

Branch if less than or equal (signed)

BLT,LBLT

Branch if less than (signed)

BHI, LBHI

Branch if higher (unsigned)

UNSIGNED BRANCHES
BHS,LBHS

Branch if higher or same (unsigned)

BEQ, LBEQ

Branch if equal

BLS, LBLS

Branch if lower or same (unsigned)

BLO,LBLO

Branch if lower (unsigned)

BSR,LBSR

Branch to subroutine

BRA,LBRA

Branch always

BRN,LBRN

Branch never

OTHER BRANCHES

274

$

HITACHI

--------------------------------------------------HD6809,HD68A09,HD68B09
Table 9 Miscellaneous Instructions
Mnemonic(s)

Operation

ANDCC

AND condition code register

CWAI

AND condition code register, then wait for interrupt

NOP

No operation

ORCC

OR condition code register

JMP

Jump

JSR

Jump to subroutine

RTI

Return from interrupt

RTS

Return from subroutine

SWI. SWI2. SWI3

Software interrupt (absolute indirect)

SYNC

Synchronize with interrupt line

~HITACHI

275

HD6809,HD68A09,HD68B09 - - - - - - - - - - - - - - - . - - - - - - - - - Table 10 HD6809 Instruction Set Table
HD6809 ADDRESSING MODES

INSTR UCTI ONI
FORMS

IMPLIED
OP

ABX

-

3A 3

#

-

EXTENDED

#

OP

-

IMMEDIATE

OP

DIRECT

#

OP

-

#

OP

1

INDEXEOQ;

-

#

RELATIVE
OP

_® #

ADCA
ADCB

99
09

4
4

2
2

89
F9

5
5

3
3

89
C9

2
2

2
2

A9 4+
E9 4+

2+
2+

?t+X-+X
UN~G"i:ED)
A+
+ -+A
B+M+C-+B

ADD

ADDA
ADDB
ADDD

9B
DB
03

4
4
6

2
2
2

BB
FB
F3

5
5
7

3
3
3

8B
CB
C3

2
2
4

2
2
3

AB 4+
EB 4+
E3 6+

2+
2+
2+

A+M-A
B+M-+B
0+ M:M + 1- 0

AND

ANDA
ANDB
ANDCC

94
04

4
4

2
2

B4
F4

5
5

3
3

84
C4
1C

2
2
3

2
2
2

A4 4+
E4 4+

2+
2+

AIIM-A
B IIM-+ B
CCII I MM -+ CC

ASR

ASlA
ASlB
ASl

48
58

ASRA
ASRB
ASR

47
57

2
2
2
2

08

6

2

78

7

3

68

6+

2+

07

6

2

77

7

3

67

6+

2+

t
t
t t
t t
t
t
t
(-I-

r:rnTIiIJJ-o

1
1

BCC

BCC
lBCC

24
10
24

2
3
5(6) 4

BCS

BCS
lBCS

25
10
25

2
3
5(6) 4

BEQ

BEQ
lBEQ

BGE

BGE
lBGE

27
3
2
10 5(6) 4
27
2
2C
3
10 5(6) 4
2C

BGT

BGT
lBGT

2E
10
2E

2
3
5(6) 4

BHI

BHI
lBHI

22
10
22

2
3
5(6) 4

BHS

BHS

24

lBHS

10
24

5(6) 4

2F
10
2F

2
3
5(6) 4
2
3
5(6) 4

3
3

BITA
BITB

BlE

BlE
lBlE

BlO

BlO
lBlO

25
10
25

BlS

BlS

23

lBlS

10
23

5(6) 4

BlT

BlT
lBlT

20
10
20

2
3
5(6) 4

BMI

BMI
lBMI

2B
10
2B

2
3
5(6) 4

BNE

BNE
lBNE

26
10
26

2
3
5(6) 4

BPl

BPl
lBPl

2
2A 3
10 5(6) 4
2A

BRA

BRA
lBRA

20
16

3
5

2
3

BRN

BRN
lBRN

21
10
21

3
5

2
4

4
4

2
2

B5
F5

5
5

85
C5

2
2

2
2

AS 4+
E5 4+

2

BIT

95
05

A1
Br
MI"
""
Branch C=O
long Branch
C=O

2+
2+

3

2

t
t

t
t

•
•
•

1

0

V C

t
t
t
t
t

t
t
t
t
t

t
t
t
t
t

0
0

•
•

(tJ I-H
t t t t

@
@ t

t

t

@

t

t t

t
t

@

t
t

t
t

•
•
•

t
t
t

(J'l.~

'j!;

•
•
•
•
•
•
•
•
•
•
•

t t

·• ·• ·· •·

•
•
Branch Z=1
•
long Branch
•
Z= 1
Branch N (+)V=Q
•
Long Branch
•
NEi-lV=O
Branch ZV(N(f)V)=O
•
long Branch
•
ZV(N V)=O
Branch CVZ=O
•
long Branch
• •
CVZ=O
Branch
• •
C=O
long Branch
•
C=O
Bit Test A (M II A) • t
Bit Test B (M liB) • t
Branch ZVIN(:Bv)=l
long Branch
• •
ZV(N (:t)V)=1
Branch C=1
• •
long Branch
• •
C=1
Branch
• •
CVZ=1
long Branch
• •
CVZ=1
Branch N !:BV=1
• •
long Branch
• •
N®V=1
Branch N=1
• •
long Branch
• •
N=1
Branch Z = 0
• •
long Branch
• •
Z=O
Branch N = 0
• •
long Branch
• •
N=O
Branch Always
• •
long Branchl
• •
Always
Branch Never
• •
long Branch Never • •
Branch C=1
long Branch
C=1

(+)

3

2

• • • • •

~) DiJ 11111 J}'

1
1

3

H N Z

ADC

ASl

5

DESCRIPTION

·

•
•
•
•
•
•
•
•
•
•

• •
• •
• •
•
• •
• •
• •
• •
• •
• •
• •
• • •
t 0 •
t 0 •
• ••

·

·

· · ·· ·
•
•
•
•
•
•
•

•
•
•
•

·•

·• •••
•
•
•
•
•
•
•

•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

·

(to be continued)

276

~HITACHI

--------------------------------------------------IHD6809,HD68A09,HD68B09
H06809 ADDRESSING MODES

INS~~~~~ON/ r-I-M-P-L-I-E-O-'--O--IR-E-C-T--"E-X-T-E-N--O-E-O'-I-M-M-E-O-I-A-T-E-r'-I-N-D-E-X-E-D-~-'r-R-E-L-A-T-IV--E4

#

#

#

#

#

#

2

1

0

H N Z

V

C

O->A
O->B
O->M

•
•
•

0
0
0

0
0
0

Compare M from A
Compare M from B
Compare M: M + 1
from D
Compare M: M + 1
from S
Compare M: M + 1
from U
Compare M: M + 1
from X
Compare M: M + 1
from Y

% I t I I
(II t t l !
• I Itt

-(§/

BSR

8D

7

2

LBSR

17

9

3

BVC

BVC
LBVC

28
10
28

3
2
5(6) 4

Branch V = 0
Long Branch
V=O

BVS

BVS
LBVS

29
10
29

3
2
5(6) 4

Branch V = 1
Long Branch
V =1

CLR

CLRA
CLRB
CLR

BSR

CMP

4F
5F

-

OP -

OF

CMPA
CMPB
CMPO

91
D1
10
93
11
9C

6

2

7F

7

3

4

2
2
3

B1
F1
10
B3
11
BC

5
5
8

3
4

4
7

3

7

3

CMPU

11

7

3

11

CMPX

93
9C

6

2

B3
BC

7

3

10
9C

7

3

10
BC

8

4

03

6

2

73

7

3

CMPY
COMA
COMB
COM

CWAI
OAA
DEC

DECA
DECB
DEC

EOR

EORA
EORB

43
53

OP

-

OP -

2
2

CMPS

COM

OP

2
2

3C

20

19

2

4A
5A

2
2

8

4

S-

4

81
C1
10
83
11
8C
11
83
8C
10
8C

2

2
5

2
2
4

5

4

5

4

4

3

5

4

6F

6+

2+

A1
E1
10
A3
11
AC
11
A3
AC

4+
4+
7+

2+
2+
3+

7+

3+

7+

3+

6+

2+

10 7+
AC

3+

63

2+

1
1

5

Branch to
Subroutine
Long Branch to
Subroutine

A-> A

B -> B,
6+

2

M->M
CC IIIMM->CC
(except l-->E) .
Wait for Interrupt
Decimal Adjust A

OA

6

2

7A

7

98
D8

4

2
2

B8
F8

5
5

4

3
3
3

88
C8

2
2

2
2

6A

6+

2+

A8
E8

4+
4+

2+
2+

A (t) M--> A
B (+)M--> B

2+

0
0
0

1
1
1

•

I

I

I

t

•

I

I

I

I

•

I

I

I

I

•

I

I

I

I

•

t

I

0

1

•

I

•

A -l-->A
B -1--> B
M-1-->M

3

·· .. .. .. ..
·· .. .. .. ..
·• .• .• .• .•

DESCRIPTION

OP

OP -

I 0 1
ItO 1

(--:7) -

•

I

I

)

l,I)

:~: 11
•

I

:

ItO •
I I 0 •
B
M+1--> M

•
•
•

I
I
I

I
I
I

I
I
!

•
•
•

Jump to Subroutine.

OC

JMP

OE

JSR

9D

LD

LDA
LOB
LDD
LDS

96
D6
DC
10
DE
DE
9E
10
9E

LDU
LDX
LDY
LEA

LSL

LSR

NOP

2

2
2
2
2

4
4
5

2

6

3

5
5
6

2
2
3

7C

7

7E

4

3
3

BD

8

3

B6
F6
FC
10
FE
FE
BE
10
BE

5
5
6

3

3
3

7

4

6
6

3
3

7

4

86
C6
CC
10
CE
CE
8E
10
8E

LEAS
LEAU
LEAX
LEAY
LSLA
LSLB
LSL

48
58

LSRA
LSRB
LSR

44
54

MUL
NEG

6
3
7

NEGA
NEGB
NEG

2
3
4

2
2

3
4
3

3
3

3

4

4

6+

6E

3+

2+

AD 7+

2+

A6
E6
EC
10
EE
EE
AE
10
AE

4+
4+
5+
6+

2+
2+
2+
3+

M->A
M->B
M: M+ 1--> D
M: M+ 1'" S

5+
5+
6+

2+
2+
3+

M: M+ 1--> U
M: M+ 1--> X
M: M+ 1--> Y

32
33
30
31

4+
4+
4+
4+

2+
2+
2+
2+

EA(;J; ...

68

6+

2+

2

2
08

6

2

78

2

2
04

3D

11

40
50

2
2

6

2

74

7

3

64

6+

2+

EA'"' -> PC

s

EA"- ... U
EA(;J; ... X
EA(;J; ... y

6

2

70

7

3

60

6+

2+

•

•

•

•

•

!

•
•
•

I
t
I

I 0
I 0

to.

•
•

•

t

I 0 •

•

A+1->A
B+ 1- B
M+1->M

I

0 •

t to.

to.

·· .. .. .. ..
•

t

•

•

t

•

•

t
t

!

~\'iJI""lJiJ: g
No Operation

2

· .. . .

~}01.J111"1.r' :
AxB ... D
(Unsigned)

00
12

2

6C

•
•
t
t
t

•
t
t

t •

t

t

t
t

t
t

t

t

•
•
•

•

t

~

··
(m t t t t
t t t t
Ij@.8tttt
(I!)

I •• • •
(to be continued)

$

HITACHI

277

HD6809,HD68A09,HD68B09 - - - - - - - - - - - - - - - - - - - - - - - HD6S09 ADDRESSING MODES
INSTRUCTION/
FORMS

IMPLIED

#

OP OR

PSH

PUL

ROL

ROR

ORA
ORB
ORCC
PSHS

34

5+@

2

PSHU

36

5+@)

2

PULS

35

5+@)

2

PULU

37

5+@;

2

ROLA
ROLB
ROL

49
59

RORA
RORB
ROR

46

2
2

56

1

39

1

5

SBCA
SBCB

SWI

10

2

SU8A
SUBB
SUBD

SWI36.,
SVNC

4
4

2
2

BA
FA

5
5

IMMEDIATE

INDEXED
(1) DMA/BREQ: "Low" for 6~13 cycles
(2) DMA/BREQ: "High" for 3 cycles

(#1)

HD6809 acknowledges the input signal level of
DMA/BREQ at the end of each cycle, then determines
whether the next sequence is MPU or DMA. When
"Low" level is detected, HD6809 executes DMA

MPU
cycle

I

I

I

DMA cycle
MPU cycle
Dead
Dead 1 - - - - - - - - - - - - - - - - - - - 1 Dead 1 - - cycle
- - ' - - - - - 1 cycle
cycle

I

DMA cycle

E

DMA/BREO

!~

~

BA.B~r~--------------------------------~-\L--1____________~~~~
Assertion of
SA delays
one clock
cycle

3 cycles

6-13 cycles

Figure 21 Exception of BA. BS Output

verce cycle steal. And it is only cleared ifDMA/BREQ is
inactive ("High") for 3 or more MPU cycles. So 1 or 2
inactive cycle(s) doesn't affect the self refresh counter.

(b) Exceptional Operations of DMA/BREQ, BA signals
(#2)

HD6809 includes a self refresh counter for the reE

---n-nY1SUl-IDL-fu--u-u-uu--L
I

I

I

::

I :

11 cycle "High",
DMA/BREO

BA. BS

I

I !

I

I

I

i

:

I

I

I

I

,

'
: ~'
i'
~' i
~
I I ~~A j I I DM~ j I
I

I

I

r

I

I

I

I

I
I

I
I

I
I

I

I

Dead

,

,-

:
I

Dead

I
I
I

i

I
I
J!
I

1
I

I
J
I
I ' ! !

Dead

Dead

.:

effective (15 cycles)

J: t'Y"~ "\
I '

y:..---..;.:-----

I

J

t

I

,

I

t

I

I

I

MPU , Dead

I

DMA

Rever~e cycle steal

I

r

\~-+-----'---il
'
, L .-l----~t~l-----l--_i_-__+---l---~:
t~:'
~
;\:1'
'\ +,__--',V
I

: :

MPU
Self Refresh
counter

I

J

~i:

I

BA. BS

!

::

~.~--~--~l~ : ~~l----~----7---~----~-----

Self Refresh
counter

DMA/BREO

r

I

,:'
MPU

12 cycles "Hi9h"l

I

::;

I Dead

I

: : ,

~~A

I I I
Dead

MPU

, L -_ _

Dead

1

D~A

I I I

II-----------e-:-ff::-e-ct-:iv-e-(,.,,1-::5-c-y-cl:-e-:s)-------..~i

Dead

MPU

Dead

DMA

Reverse cycle steal

Figure 22 Exception of DMA/BREQ

$

HITACHI

281

(c)

How to avoid these exceptional operations
It is necessary to provide 4 or more cycles for in·

active DMA/BREQ level as shown in Fig. 23.

DMA7BRE~~_____________________________

1

4 or more cycles

\

BA,BS--.l

tI

Figure 23 How to Avoid Exceptional Operations

(a) An Example of the System Configuration
This restriction is applied to the following system.
(I) DMA/BREQ is used for DMA request.
(2) "Halt Burst Mode" is used for DMA transfer

[2] Restriction for DMA Transfer
There is a restriction for the DMA transfer in the HD6809
(MPU), HD6844 (DMAC) system. Please take care of fol·
lowing.
r---

DMA/BREQ
DMA transfer
request
HD6809
(MPU)

BA

Q

DRQH

D

C f - - - E clock
"-7474

HD6844
(DMAC)

DGRNT

DMA acknowledge

Figure 24 An Example of HD6809, HD6844 System

,I The restriction is also applied to the system which doesn't \
\ use 7474 Flip·Flop. Fig. 24, Fig. 25 shows an example which )
\ uses 7474 for synchronizing DMA request with E.
/
(b) Restriction
"The number of transfer Byte per one DMA Burst
transfer must be less than or equal to 14."

reverse cycle steals once in 14 DMA cycles by taking
back the bus control. In this case, however, the action
taken by MPU is a little bit different from the DMAC.

Halt burst DMA transfer should be less than or
equal to 14 cycles. In another word, the number
stored into DMA Byte count register should be O~14.

As shown in Fig. 25, DMA controller can't stop
DMA transfer (@) by BA falling edge and excutes
an extra DMA cycle during HD6809 dead cycle. So
MPU cycle is excuted right after DMA cycle, the Bus
confliction occurs at the beginning of MPU cycle.

*

Please than care of the section [I ] (b) if 2 or more
DMA channels are used for the DMA transfer.

(d)

(c) Incorrect operation of HD6809, HD6844 system
"Incorrect Operation" will occur if the number of
DMA transfer Byte is more than 14 bytes. If DMA/
BREQ is kept in "Low" level HD6809 performs

282

_HITACHI

How to impliment Halt Bust DMA transfer
(> 14 cycles)
Please use HALT input of HD6809 for the DMA
request instead of DMA/BREQ.

1 - - - - - - - - 1 4 cycles - - - - -...

H D6809 reverse
cycle steal

DMA/BREQ

BA

HD6809~---L~L-~~~------------D-M-A-C-y-C-le-s----------~~~~---b??~~---D-M--A-C-y-Cl-es---cycle
MPU cycle is
excuted right
after DMA,
Bus confl iction
occurs.

DGRNT
(BA) - - - - f - - - - i

HD6844
cycles

DMA cycles

DMA cycles

@)
MPU sets BA to inactive "Low" )
for reverse cycle steal, But
DMAC couldn't acknowledge
the request and performs
extra DMA during Dead cycle.

)

Figure 25 Comparison of HD6809, HD6844 DMA cycles

[3] Note for ClR Instruction
Cycle-by-cycle flow of CLR instruction (Direct, Extended, Indexed Addressing Mode) is shown below. In this
sequence the content of the memory location specified by
the operand is read before writing "00" into it. Note that
status Flags, such as IRQ Flag, will be cleared by this extra
data read operation when accessing the control/status
register (sharing the same address between read and write)
of peripheral devices.

Example: CLR (Extended)
$8000
$AOOO

CLR
FCB

Cycle #
I
2

Address
8000
8001

3

8002

4

FFFF
AOOO
FFFF
AOoo

5
6
7

*

The data bus has the

~HITACHI

$AOOO
$80
Data
7F
AO

R!W

Description
Opcode Fetch
Operand Address,
High Byte
00
Operand Address,
Low Byte
I
VMACycie
*
80
1
Read the Data
I
VMACycle
*
00
o
Store Fixed "00"
into Specified
Location
data at that particular address.
1
1

283

HD6309---------------CMOS MPU (Micro

Processing Unit)
-ADVANCE INFORMATION-

The HD6309 is the highest 8-bit microprocessor of
HMCS6800 family. which is just compatible with the conventional HD6809.
The HD6309 has hardware and software features which make
it an ideal processor for higher level language execution or
standard controller applications.
The HD6309 is complete CMOS device and the power
dissipation is extremely low. Moreover the SYNC and CWAI
instruction makes lower power application possible.
•
•

FEATURES
Hardware Software -

Interfaces with All HMCS6800 Peripherals
DMA transfer with no auto-refresh cycle
Lin-Limited MRDY control
Fully Compatible with HD6809, HD6809E,
•
HD6309E MPU families
• Low Power Consumption Mode; SYNC and CWAI instruction
• Crystal Oscillation
• Wide Operation Range
f= 0.5 to 8 MHz
(Vee = 5V±10%)

(DP-40)

•

PIN ARRANGEMENT
vss

0

HALT

NMT

XTAL
EXTAL
RES
MRDY

SA

Q

Bus Timing

DMA/BREQ
R/W

2.0 MHz

HD6309

2.5 MHz
A.

3.0 MHz

D.
D,
D,

As

•

A.
A,

BLOCK DIAGRAM

Ds
D.

A.

AI4

+--Vcc
+--Vss

(Top View)

"CMA7BREQ
R'W"

HALT
SA
BS
XTAL

EXTAL

MRDY
E

a

284

@HITACHI

H D6809E, H D68A09E,
HD68B09E

M PU(Micro

Processing Unit)

The HD6809E is a revolutionary high performance 8-bit
microprocessor which supports modern programming techniques
such as position independence, reentrancy, and modular
programming.
This third-generation addition to the HMCS6800 family has
major architectural improvements which include additional
registers, instructions and addressing modes.
The basic instructions of any computer are greatly enhanced
by the presence of powerful addressing modes. The HD6809E
has the most complete set of addressing modes available on any
8-bit microprocessor today.
The HD6809E has hardware and software features which
make it an ideal processor for higher level language execution
or standard controller applications. External clock inputs are
provided to allow synchronization with peripherals, systems or
other MPUs.
HD6800 COMPATIBLE
• Hardware - Interfaces with A" HMCS6800 Peripherals
• Software - Upward Source Code Compatible Instruction Set
and Addressing Modes
• ARCHITECTURAL FEATURES
• Two 16-bit I ndex Registers
• Two 16-bit I ndexable Stack Pointers
• Two 8-bit Accumulators can be Concatenated to Form One
16-Bit Accumulator
• Direct Page Register Allows Direct Addressing Throughout
Memory
• HARDWARE FEATURES
• External Clock Inputs, E and Q, A"ow Synchronization
• TSC Input Controls Internal Bus Buffers
• L1C Indicates Opcode Fetch
• AVMA Allows Efficient Use of Common Resources in A
Multiprocessor System
• BUSY is a Status Line for Multiprocessing
• Fast Interrupt Request Input Stacks Only Condition Code
Register and Program Counter
• Interrupt Acknowledge Output A"ows Vectoring By Devices
• SYNC Acknowledge Output A"ows for Synchronization to
External Event
• Single Bus-Cycle RESET
• Single 5-Volt Supply Operation
• NMI Blocked After RESET Until After First Load of Stack
Pointer
• Early Address Valid A"ows Use With Slower Memories
• Early Write-Data for Dynamic Memories
• SOF~ARE FEATURES
• 10 Addressing Modes
• HMCS6800 Upward Compatible Addressing Modes
Direct Addressing Anywhere in Memory Map
Long Relative Branches
• Program Counter Relative
• True Indirect Addressing
• Expanded Indexed Addressing:
0, 5, 8, or 16-bit Constant Offsets
8, or 16-bit Accumulator Offsets

•
•
•
•
•
•
•

Auto-Increment/Decrement by 1 or 2
Improved Stack Manipulation
1464 Instruction with Unique Addressing Modes
8 x 8 Unsigned Multiply
16-bit Arithmetic
Transfer/Exchange A" Registers
Push/Pull Any Registers or Any Set of Registers
Load Effective Address

•

PIN ARRANGEMENT

@HITACHI

HALT
TSC

Lie
RES
AVMA

a
BUSY

R/W

HD6809E
0,
0,

Os

D.

0,
A"
A,.

(Top View)

285

HD6809E,HD68A09E,HD68B09E----------------------------------_____________
• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Value

Unit

Supply Voltage

Vcc*

-0.3 - +7.0

V

Input Voltage

Vin*

-0.3- +7.0

V

Operating Temperature Range

Topr

-20 -+75

Storage Temperature Range

Tstg

-55 - +150

°c
°c

• With respect to Vss (SYSTEM GND)
(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended
operating conditions. If these conditions are exceeded, it could affect reliability of LSI.
•

RECOMMENDED OPERATING CONDITIONS
Symbol

min

typ

max

unit

Vcc*

4.75

5.0

5.25

V

Logic, Q, RES

VIL *

-0.2

0.8

V

E

VILC·

-0.3

-

0.4

V

Item
Supply Voltage

Input Voltage

Logic

2.2

VIH·

RES

4.0
VIHC*

E
Operating Temperature

.
•

•

Vcc* -0.75

Topr

-20

Vcc*

V

Vcc*

V

Vcc* +0.3

25

V

°c

75

With respect to Vss (SYSTEM GND)

ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee = S.OV ±S%, Vss = OV, Ta = -20 - +7SoC, unless otherwise noted.)
Item

Input "High" Voltage

Symbol

Test Condition

Logic, Q

VIH

2.2

Vee

VIHR

4.0
Vee
-0.75 -

Vee 4.0
Vee Vee
+0.3 -0.75
0.8 -0.2
0.4 -0.3

Logic, Q, RES
Logic, Q, RES

lin

Do -07
Output "High" Voltage

Ao - Au, R/W

VOH

BA, BS, LIC,
AVMA, BUSY
Output "Low" Voltage

VOL

Power Dissipation

Po

Input Capacitance

Output Capacitance
Frequency of Operation
Three·State (Off Statel
Input Current

Do - 07, Logic
Input,Q,m
Ao - AIS, RIW,
BA, BS, LlC,
AVMA, BUSY
E,Q
Ao-Au,RIW

-

2.2

Vee

Vee 4.0
Vee Vee
+0.3 -0.75 -

Vee

V

Vee
+0.3
0.8
0.4

V

2.5
100

/JA
/JA

-0.2 -0.3 2.5 -2.5 100 -100 -

V

ILoad = -205/JA,
Vee = min

2.4

2.4

2.4

V

ILoad = -145/JA,
Vee = min
ILoad = -100/JA,
Vee = min

2.4

2.4

2.4

V

2.4

2.4

2.4

V

ILoad = 2mA,
Vee - min

Vin = OV,
Ta = 25°C,
f = 1MHz

Cout

Vin = OV,
Ta = 25°C,
f -lMHz

ITSI

Vin =0.4-2.4V,
Vee = max

-100

eHITACHI

2.5 -2.5
100 -100

0.8
0.4

V
V

0.5

0.5

0.5

V

1.0

1.0

1.0

W

10

15

10

15

10

15

pF

30

50

30

50

30

50

pF

10

15

10

15

10

15

pF

2.0
10

MHz

100

/JA

0.1
-10

• Ta c 25°C. Vee· 5V

286

Vee

Unit

Vin = 0 - 5.25V,
Vee = max

Cin

00- 07

2.2

H068B09E
typo

min

-0.2 -0.3 -2.5 -100 -

VIL
VILC

Input Leakage Current

H068A09E
typO

min

RES

VIHC

Input "Low" Voltage

H06809E
typO max

min

1.0
10

-

0.1
-10

100 -100

-

1.5
10

0.1
-10

100

-100

-

/JA

•

AC CHARACTERISTICS (Vee
READ/WRITE TIMING

= 5.0V ±5%, Vss = OV, Ta = -20 ~ +75°C, unless otherwise noted.)

Item

HD6809E
min

typ

HD68A09E
max

min

typ

HD68B09E

max

-

min

typ

Cycle Time

tcyC

1000

-

Peripheral Read Access Times
tcyc - tEf - tAD - tDSR = tACC

tACC

695

-

-

440

-

-

330

Data Setup Time (Read)

tDSR

80

-

-

60

-

-

40

Input Data Hold Time

tDHR

10

-

-

10

-

-

10

30

-

-

30

-

-

30

-

20

-

-

20

-

-

20

20

-

-

20

-

-

10

-

-

10

-

-

Output Data Hold Time

i

Ta =0 - +75°C

I

) Ta = -20 - O°C
I

Address Hold Time
(Address, R/W)

Ta =0 - +75°C
Ta = -20 - O°C

)

I
I

I

tDHW

I
I

tAH

:

Address Delay

tAD

Data Delay Time (Write)

tDDW

E Clock" Low"

tPWEL

Fig, 1,2,
7 -10,
14 and 17

!

10000 667

450

-

9500 1295

-

9500 i 280

-

-

I

-

-

I

-

E Clock "High" (Measured at VIH)

tPWEH

450

-

E Rise and Fall Time

tEr, tEf

-

-

o Clock "High"
o Rise and Fall Time

tPWOH

450

-

tOr, tOf

-

E "Low" to 0 Rising

tEOl

200

-

o "High" to E Rising

tE02

200

-

E "High" to 0 Falling

tE03

200

o "Low" to E Falling

tE04

200

Interrupts HALT, RES and TSC Setup Time

tpcs

200 '

-

-

200
200

25

I

-

280

25

-

-

130

-

-

~30

-

-

-

130

1-

-

-

10000

Unit
ns

-

ns

-

-

ns

-

-

ns

-

-

ns

20

-

-

ns

10

-

-

ns

120

ns

ns

i 140

-

-

' 140

1-

-

110

ns

-

9500

ns

-

9500

ns

20

ns

i9500 i,210
1

-

9500

10000 500

max

220

9500
25

-

I

I
-

220

.9500

i

9500

ns

25

-

-

20

ns

-

100

-

-

ns

(-

100

-

-

ns

-

-

100

-

-

ns

130

-

-

100

-

-

ns

140

-

-

110

-

-

ns

j

I

TSC Drive to Valid Logic Levels

tTSA

-

-

210

-

-

150

-

-

120

ns

TSC Release MOS Buffers to High Impedance

tTSR

-

I -

200

-

-

140

-

-

110

ns

TSC Three-State Delay

tTSD

-

I

-

120

-

85

1-

-

80

ns

Control Delay (BUSY, LlC)

tCD

-

300

-

I

-

-

200

ns

-

-

300

-

270

-

-

240

ns

tPCr' tpCf

-

-

100

-

-

100

-

-

100

ns

tPCT

10

-

-

10

-

-

10

-

-

ns

Control Delay (AVMA·)

TSC Input Delay

I

tCD

Processor Control Rise/Fall

•

Test
Condition

Symbol

I

I

250

AVMA drives a not-valid data before providing correct output, so spec teo max = 270nsec (HD68A09E) and 240 nsec (HD68B09E) are applied to
this signal. When this delay time causes a problem in user's application, please use D-type latch to get stable output.

AVMA--~~~N~o~t~V~a~l~id~~~----'ij~N~o~t~V~al~id~~~--100--

$

HITACHI

287

HD6809E,HD68A09E,HD68B09E----------------------------------------------~---------------------tcvc----------------------~

E

Q

R/W
Addr
BA,BS* __________~~

~

BUSY,
LlC, ________________________
AVMA

~

Data

~NotValid
* Hold time for BA, BS not specified
(NOTE)

Waveform measurements for all inputs and outputs are specified at logic "High" = V IHmin and logic "Low"

= V I Lmax unless otherwise specified.

Figure 1 Read Data from Memory or Peripherals

E

~------tpWQH----~~

Q

----------+-------~~

R/W
Addr
BA,BS* __________

~~

Data

BUSY,

LlC,
AVMA

~NotValid
* Hold time for BA, BS not specified
(NOTE)

Waveform measurements for all inputs and outputs are specified at logic "High" = V IHmin and logic "Low" = V I Lmax unless otherwise specified.

Figure 2 Write Data to Memory or Peripherals

288

$

HITACHI

-----HD6809E,HD68A09E,HD68B09E

+-Vcc
4 - - V ss

r---- RES
NMI

FIRQ

rna
'--AEi==!........... LlC
...----I~ AVMA
R/iN
TSC
HALT
BA
BS
'----·BUSY

'----- E
'------Q

Figure 3 HD6809E Expanded Block Diagram

5.0 V

RL

=

2.2 kn

Test Point CH---__-~~....
C

R

C = 30 pF for BA, BS, LIC, AVMA, BUSY
130 pF for Do - 0 7
90pF for Ao -Au, R/W
R = 11.7 kil for Do - 0 7
16.5 kil for Ao -A 15 , R/W
24 kil for BA, BS, LlC, AVMA, BUSY
All diodes are 1S2074@ or equivalent.
C includes stray capacitance.

Figure 4 Bus Timing Test Load

• PROGRAMMING MODEL
As shown in Figure 5. the HD6809E adds three registers to
the set available in the HD6800. The added registers include a
Direct Page Register, the User Stack pointer and a second
Index Register.
• Accumulators (A, B, D)
The A and B registers are general purpose accumulators
which are used for arithmetic calculations and manipulation
of data.
Certain instructions concatenate the A and B registers to
form a single 16·bit accumulator. This is referred to as the D
R~gistt'r. and is formed with the A Register as the most
signitil:ant byte.
• Direct Page Register (DP)
Tltt' Direct Page Register of the HD6809E serves to enhance
the Direct Addressing Mode. The content of this register
appears at the higher address outputs (As - Au) during direct
addressing instruction execution. This allows the direct mode
to be used at any place in memory, under program control.
To ensure HD6800 compatibility, all bits of this register are
cleared during Processor Reset.

eHITACHI

289

HD6809E,HD68A09E,HD68B09E~~~~~~~~~~~~~~~~~~~~~~

o

15

x-

Index Register

V - Index Register

Pointer Registers

U - User Stack Pointer
S - Hardware Steck Pointer
PC
A
\.

Program Counter

1

B

Accumulators
I

"

D

7

0

I_____
7
0
I
I Iz I I I
D_P_ _ _ _--',

I..

ElF I H II

N

V

C

Direct Page Register

cc -

Condition Code Register

Figure 5 Programming Model of The Microprocessing Unit

• Index Registers (X, Y)
The Index Registers are used in indexed mode of addressing.
The 16-bit address in this register takes part in the calculation
of effective addresses. This address may be used to point to
data directly or may be modified by an optional constant or
register offset. During some indexed modes, the contents of
the index register are incremented or decremented to point to
the next item of tabular type data. All four pOinter registers
(X, Y, U, S) may be used as index registers.
• Stack Pointer (U, S)
The Hardware Stack Pointer (S) is used automatically by
the processor during subroutine calls and interrupts. The User
Stack Pointer (U) is controlled exclusively by the programmer
thus allowing arguments to be passed to and from subroutines
with ease. The U-register is frequently used as a stack marker.
Both Stack Pointers have the same indexed mode addressing
capabilities as the X and Y registers, but also support Push and
Pull instructions. This allows the HD6809E to be used efficiently as a stack processor, greatly enhancing its ability to
support higher level languages and modular programming.
(NOTE) The stack pointers of the HD6809E point to the top
of the stack, in contrast to the HD6800 stack pointer,
which pointed to the next free location on stack.
• Program Counter (PC)
The Program Counter is used by the processor to point to
the address of the next instruction to be executed by the
processor. Relative Addressing is provided allowing the Program
Counter to be used like an index register in some situations.
• Condition Code Register (CC)
The Condition Code Register defines the state of the
processor at any given time. See Figure 6.

290

Carry
Overflow
'----Zero
~---- Negative
' - - - - - - IRQ Mask
' - - - - - - - - - Half Carry
~-------- FIRQ Mask
' - - - - - - - - - - - Entire Flag

Figure 6 Condition Code Register Format

• CONDITION CODE REGISTER DESCRIPTION
• Bit 0 (C)
Bit 0 is the carry flag, and is usually the carry from the
binary ALU. C is also used to represent a 'borrow' from
subtract like instructions (CMP, NEG, SUB, SBC) and is the
complement of the carry from the binary ALU.
• Bit 1 (V)
Bit 1 is the overflow flag, and is set to a one by an operation
which causes a signed two's complement arithmetic overflow.
This overflow is detected in an operation in which the carry
from the MSB in the ALU does not match the carry from the
MSB-1.
• Bit 2 (Z)
Bit 2 is the zero flag, and is set to a one if the result of the
previous operation was identically zero.
• Bit 3 (N)
Bit 3 is the negative flag, which contains exactly the value
of the MSB of the result of the preceding operation. Thus, a
negative two's-complement result will leave N set to a one.

eHITACHI

~~~~~~~~~~~~~~~~~~~~~~~-HD6809E.HD68A09E.HD68B09E

• Bit 4 (I)
Bit 4 is the IRQ mask bit. The processor will not recognize
interrupts from the IRQ line if this bit is set to a one. NMI,
FIRQ, IRQ, RES and SWI all set I to a one; SWI2 and SWI3
do not affect I.
• Bit 5 (H)
Bit 5 is the half-carry bit, and is used to indicate a carry
from bit 3 in the ALU as a result of an 8-bit addition only
(ADC or ADD). This bit is used by the DAA instruction to
perform a BCD decimal add adjust operation. The state of this
flag is undefined in all subtract-like instructions.
• Bit 6 (F)
Bit 6 is the FIRQ mask bit. The processor will not recognize
interrupts from the FIRQ line if this bit is a one. NMI, FIRQ,
SWI, and RES all set F to a one. IRQ, SWI2 and SWI3 do not
affect F.
•

This higher threshold voltage ensures that all peripherals are
out of the reset state before the Processor.
Table 1 Memory Map for Interrupt Vectors
Memory Map for Vector
Locations

Interrupt Vector
Description

MS

LS

FFFE

FFFF

RES

FFFC

FFFD

NMI

FFFA

FFFB

SWI

FFF8

FFF9

IRQ

FFF6

FFF7

FIRQ

FFF4

FFF5

SWI2

FFF2

FFF3

SWI3

FFFO

FFFl

Reserved

Bit 7 (E)

Bit 7 is the entire flag, and when set to a one indicates that
the complete machine state (all the registers) was stacked, as
opposed to the subset state (pC and CC). The E bit of the
stacked CC is used on a return from interrupt (RTI) to determine the extent of the unstacking. Therefore, the current E
left in the Condition Code Register represents past action.
• HD6809E MPU SIGNAL DESCRIPTION
• Power (VSS, Vee)
Two pins are used to supply power to the part: Vss is
ground or 0 volts, while Vee is +5.0 V ±5%.
• Address Bus (Ao - A 1S )
Sixteen pins are used to output address information from
the MPU onto the Address Bus. When the processor does not
require the bus for a data transfer, it will output address
FFFF 16, R/W = "High", and BS = "Low"; this is a "dummy
access" or VMA cycle. All address bus drivers are made highimpedance when output Bus Available (BA) is "High" or when
TSC is asserted. Each pin will drive one Schottky TTL load or
four LS TTL loads, and 90 pF. Refer to Figures I and 2.
• Data Bus (Do - 0 7 )
These eight pins provide communication with the system
bi-directional data bus. Each pin will drive one Schottky TTL
load or four LS TTL loads, and 130 pF.
• ReadlWrite (R/W)
This signal indicates the direction of data transfer on the
data bus. A "Low" indicates that the MPU is writing data-onto
the data bus. R/W is made high impedance when BA is "High"
or when TSC is asserted. Refer to Figures I and 2.
• RES
A "Low" level on this Schmitt-trigger input for greater tl).an
one bus cycle will reset the MPU, as shown in Figure 7. The
Reset vectors are fetched from locations FFFE 16 and FFFF 16
(Table I) when Interrupt Acknowledge is true, (BA • BS = 1).
DUring initial power-on, the Reset line should be held "Low"
until the clock input signals are fully operational.
Because the HD6809E Reset pin has a Schmitt-trigger input
with a threshold voltage higher than that of standard peripherals,
a simple R/C network may be used to reset the entire system.

• HALT
A "Low" level on this input pin will cause the MPU to stop
running at the end of the present instruction and remain halted
indefinitely without loss of data. When halted, the BA output
is driven "High" indicating the buses are high impedance. BS
is also "High" which indicates the processor is in the Halt state.
While halted, the MPU will not respond to external real-time
requests (FIRQ, IRQ) although NMI or RES will be latched
for later response. During the Halt state Q and E should
continue to run normally. A halted state (BA • BS = 1) can be
achieved by pulling HALT "Low" while RES is still "Low". See
Figure 8.
• Bus Available, Bus Status (BA, BS)
The Bus Available output is an indication of an internal
control signal which makes the MOS buses of the MPU high
impedance. When BA goes "Low", a dead cycle will elapse before
the MPU acquires the bus. BA will not be asserted when TSC
is active, thus allowing dead cycle consistency.

The Bus Status output signal, when decoded with BA,
represents the MPU state (valid with leading edge of Q).
MPU State
BA

BS

o
o

0

MPU State Definition
Normal (Running)

1

I nterrupt or RESET Acknowledge

o

SYNC Acknowledge
HALT Acknowledge

Interrupt Acknowledge is indicated during both cycles of a
hardware-vector-fetch (RES, NMI, FIRQ, IRQ, SWI, SWI2,
SWI3). This signal, plus decoding of the lower four address
lines, can provide the user with an indication of which interrupt
level is being serviced and allow vectoring by device. See Table
1.
Sync Acknowledge is indicated while the MPU is waiting
for external synchronization on an interrupt line.
Halt Acknowledge is indicated when the HD6809E is in a
Halt condition.

_HITACHI

291

I\)

:::I:

CD

o

I\)

0)

00

o

co

m

:::I:

o

0)

00

»o

CO

m
:::I:

o

0)

00

E

m

oco

Q

m

~

%

~

0

!

Address
Data

R/Vii
BA
BS

NewPCH NewPC L

~

mmm

VMA 1st Opcode

~

NewPCH NewPCL

~

~

AVMA
BUSY
L1C

(NOTE)

Waveform measurements for all inputs and outputs are specified at logic "High" ; VIHmin and logic "low"; VILmax unless otherwise specified.

Figure 7 RES Timing

VMA

Halted

Halted

Q

E

HALT

e%
~

Address
Bus
Fetch

()

!

Execute

A/W
BA
BS

1
----_-----11

_ _ _ _ _- - - - - J

Data
Bus _ _

~

\
\

\
\

/
j,----~i-----

....

Instruction
Opcode

AVMA

LIe

-----~

\

-------~/

\

J:

o

\~----

/

~

0>
(X)

o

<0

m
J:

o

0>
(X)

l>

(NOTE)

Waveform measurements for all inputs and outputs are specified at logic "High"

= V IHmin and

logic "Low"

= V ILmax

unless otherwise specified.

o

<0

!1'1.
Figure 8

HALT and Single Instruction Execution for System Debug

J:

o

0>
(X)
I\)

<0

CA)

III

o

<0

m

HD6809E,HD68A09E,HD68B09E~~~~~~~~~~~~~~~~~~~~~~~

•

Non Maskable Interrupt (NMI)*
A negative transition on this input requests that a nonmaskable interrupt sequence be generated. A non-maskable
interrupt cannot be inhibited by the program, and also has a
higher priority than FIRQ, IRQ or software interrupts. During
recognition of an NMI, the entire machine state is saved on
the hardware stack. After reset, an NMT will not be recognized
until the first program load of the Hardware Stack Pointer (S).
The pulse width of NMI low must be at least one E cycle. If
the NMI input does not meet the minimum set up with respect
to Q, the interrupt will not be recognized until the next cycle.
See Figure 9.

of a double-byte operation (e.g., LDX, STD, ADDD). Busy is
also "High" during the first byte of any indirect or other vector
fetch (e.g., jump extended, SWI indirect etc.).
In a multi-processor system, busy indicates the need to
defer the rearbitration of the next bus cycle to insure the
integrity of the above operations. This difference provides the
indivisible memory access required for a "test-and-set" primitive, using anyone of several read-modify-write instructions.
Busy does not become active during PSH or PUL operations.
A typical read-modify-write instruction (ASL) is shown in
Figure 12. Timing information is given in Figure 13. Busy is
valid tCD after the rising edge of Q.

•

• AVMA

Fast-Interrupt Request (FIRO)*
A "Low" level on this input pin will initiate a fast interrupt
sequence, provided its mask bit (F) in the CC is clear. This
sequence has priority over the standard Interrupt Request
<.IRQ), and is fast in the sense that it stacks only the contents
of the condition code register and the program counter. The
interrupt service routine should clear the source of the interrupt
before doing an RTI. See Figure 10.
Interrupt Request (lRO)*
A "Low" level input on this pin will initiate an Interrupt
Request sequence provided the mask bit (I) in the CC is clear.
Since IRQ stacks the entire machine state it provides a slower
response to interrupts than FIRQ. IRQ also has a lower priority
than FIRQ. Again, the interrupt service routine should clear
the source of the interrupt before doing an RTI. See Figure 9.

•

*

NMI, FIRQ, and IRQ requests are sampled on the fal1ing edge of Q.
One cycle is required for synchronization before these interrupts are
recognized. The pending interrupt(s) will not be serviced until
completion of the current instruction unless a SYNC or CWAI
condition is present. If IRQ and FIRQ do not remain "Low" until
completion of the current instruction they may not be recognized.
However, NMI is latched and need only remain "Low" for one cycle.

• Clock Inputs E, 0
E and Q are the clock signals required by the HD6809E.
Q must lead E; that is, a transition on Q must be followed by a
similar transition on E after a minimum delay. Addresses will
be valid from the MPU, tAD after the falling edge of E, and
data will be latched from the bus by the falling edge of E.
While the Q input is fully TTL compatible, the E input directly
drives internal MOS circuitry and, thus, requires levels above
normal TTL levels. This approach minimizes clock skew
inherent with an internal buffer. Timing and waveforms for E
and Q are shown in Figures 1 and 2 while Figure 11 shows a
simple clock generator for the HD6809E.
•

BUSY

Busy will be "High" for the read and modify cycles of a readmodify-write instruction and during the access of the first byte

294

AVMA is the Advanced VMA signal and indicates that the
MPU will use the bus in the following bus cycle. The predictive
nature of the AVMA signal allows efficient shared-bus multiprocessor systems. AVMA is "Low" when the MPU is in either a
HALT or SYNC state. AVMA is valid tCD after the rising edge
ofQ.
•

L1C
LIC (Last Instruction Cycle) is "High" during the last cycle
of every instruction, and its transition from "High" to "Low"
will indicate that the first byte of an opcode will be latched at
the end of the present bus cycle. LIC will be "High" when the
MPU is Halted at the end of an instruction, (Le., not in CWAI or
RESET) in SYNC state or while stacking during interrupts.
LIC is valid teo after the rising edge of Q.
• TSC
TSC (Three-State Control) will cause MOS address, data,
and R/W buffers to assume a high-impedance state. The control
signals (BA, BS, BUSY, AVMA and LIC) will not go to the
high-impedance state. TSC is intended to allow a single bus to
be shared with other bus masters (processors or DMA controllers).
While E is "Low", TSC controls the address buffers and R/W
directly. The data bus buffers during a write operation are in a
high-impedance state until Q rises at which time, if TSC is
true, they will remain in a high-impedance state. If TSC is held
beyond the rising edge of E, then it will be internally latched,
keeping the bus drivers in a high-impedance state for the
remainder of the bus cycle. See Figure 14.
• MPU Operation
During normal operation, the MPU fetches an instruction
from memory and then executes the requested function. This
sequence begins after RES and is repeated indefinitely unless
altered by a special instruction or hardware occurrence. Software instructions that alter normal MPU operation are: SWI,
SWI2, SWI3, CWAI, RTI and SYNC. An interrupt or HALT
input can also alter the normal execution of instructions.
Figure 15 illustrates the flow chart for the HD6809E.

eHITACHI

last Cycle
of Current
Instruction

I'

I'

m-2 m-1

I·

I

"

Instruction
Fetch
.\.. \

Interrupt Stacking and Vector Fetch Sequence
m

I m+1, m+2

m+3
1

m+4

"I'

m+5 m+6

I,

I

m+7

'I"

I

m+8

m+9 m+10 m+11,m+12 m+13 m+14 m+15 m+16m+17 m + 18

I'

I

"'1 '

,

,',

'I

I

I

n

I n+1 I

"'_."

E
Q

~
l:

~
:E

(')

Data ~'----J'----J'----J'----J'----J'----J'----J'----J'----J,"----,,'----J'----J
YH
A
Yl
B
UH
Xl
XH
DP
Ul
VMA PCl PCH

R/W

-:r::::::x:::::

BAJC:JC:)~

BS

\

CC

VMA

New
P~H

I

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

::x::::x::::>.

I

,'--________

AVMA ___ ~

BUSY
L1C

::J.

r--\

I

E

c=.
\----

::z:

o

0)


o
!"
::z:
o
(D

0)

.

lIC _~I

-

00

o

\

/

\

X,...-$B8

/----\\-______
I

AVMA

E

l:

(NOTE)

~
!

Waveform measurements for all inputs and outputs are specified at logic "High"

= V IHmin and logic "low" = V I Lmax

unless otherwise specified.

Figure 13 BUSY Timing (ASL Extended Indirect Instruction)

()

MPU Data

(NOTES) Data will be asserted by the MPU only during the interval while R/W is "low" and E or Q is "High".
Waveform measurements for all inputs and outputs are specified at logic "High" = V IHmin and logic "low"

Figure 14 TSC Timing

$0203

= V I Lmax unless otherwise specified.

,'---_

<0

!"
::t

o

0)

00
00

o

<0

m

mm.~

%

~

o

!

::L

a

0)

co
o
co

m

HD6809E Interrupt Structure
Bus State
Running
Interrupt or Reset Acknowledge
Sync Acknowledge
Halt Acknowledge
(NOTES) 1. Asserting RES will result in entering the reset
sequence from any point in the flow chart.
2. BUSY is "High" during first vector fetch cycle.

0
0
1
1

::I:
BS

0
1
0
1

a

0)

co

»
o

co

!"
::L

a0)

co
CD

I\)

~

SA

Figure 15 Flowchart for HD6809E Instruction

o
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m

HD6809E,HD68A09E,HD68B09E----------------------------------------------• ADDRESSING MODES
The basic instructions of any computer are greatly enhanced
by the presence of powerful addressing modes. The HD6809E
has the most complete set of addressing modes available on
any microcomputer today. For example, the HD6809E has 59
basic instructions; however, it recognizes 1464 different variations of instructions and addressing modes. The addressing
modes support modern programming techniques. The following
addressing modes are available on the HD6809E:
(1) Implied (Includes Accumulator)
(2) Immediate
(3) Extended
(4) Extended Indirect
(5) Direct
(6) Register
(7) Indexed
Zero-Offset
Constant Offset
Accumulator Offset
Auto Increment/Decrement
(8) Indexed Indirect
(9) Relative
(10) Program Counter Relative
•

Implied (Includes Accumulator)
In this addressing mode, the opcode of the instruction
contains all the address information necessary. Examples of
Implied Addressing are: ABX, DAA, SWI, ASRA, and CLRB.

Immediate Addressing
In Immediate Addressing, the effective address of the data
is the location immediately following the opcode (Le., the data
to be used in the instruction immediately follows the opcode
of the instruction). The HD6809E uses both 8 and 16-bit
immediate values depending on the size of argument specified
by the opcode. Examples of instructions with immediate
Addressing are:
LDA #$20
LDX #$FOOO
LDY #CAT

•

Direct Addressing
Direct addressing is similar to extended addressing except
that only one byte of address follows the opcode. This byte
specifies the lower 8 bits of the address to be used. The upper
8 bits of the addres~ are supplied by the direct page register.
Since only one byte of address is required in direct addressing,
this mode requires less memory and executes faster than
extended addressing. Of course, only 256 locations (one page)
can be accessed without redefining the contents of the DP
register. Since the DP register is set to $00 on Reset, direct
addressing on the HD6809E is compatible with direct addressing
on the HD6800. Indirection is not allowed in direct addressing.
Some examples of direct addressing are:
LDA
$30
SETDP $10
(Assembler directive)
LDB
$1030
LDD

CO

m

= S).

J:

o

0)

CO
OJ

oCO

m

Co)

:J:
C

0

Q)

0)

00

Non mplied

e%
~

ADCA
ADCB
ADDA
AD DB
ANDA
ANDB
BITA
BITB
CMPA
CMPB
FORA
FORB
LDA
LDB
ORA
ORB
SBCA
SBCB
STA
STB
SUBA
SUBB

o
<0
!"

LDD
LDS
LDU
LDX
LDY

ASL
ASR
CLR
COM
DEC
INC
LSL
LSR
NEG
ROL
ROR

ANDCC
ORCC

ADDD
CMPD
CMPS
CMPU
CMPX
CMPY
SUBD

:J:
C

STD
STS
STU
STX
STY

0)

00

»
o
<0

!"
:J:
C

00

OJ

VMA
STACK (W)
STACK (W)

o

<0

m

AD DR +

VMA
ADDR+

JSR

0)

VMA, BUSY +-1
ADDR+
BUSY +-0

0

=

TST

I

ADD R+ (W)

VMA

VMA

,

,

(NOTES)
1. Stack (WI refers to the following sequence: SP +- SP - 1, then ADDR +- SP with R/IN = "Low"
Stack (RI refers to the following sequence: ADDR +- SP with R/W = "High", then SP +- SP + 1.
PSHU, PULU instructions use the user stack pointer (i.e., SP = UI and PSHS, PULS use the hardware stack pointer (i.e., SP
2. Vector refers to the address of an interrupt or reset vector (see Table 1 I.
3. The number of stack accesses will vary according to the number of bytes saved.
4. VMA cycles will occur until an interrupt occurs.

Figure 18 Address Bus Cycle-by-Cycle Performance (Continued)

= SI.

HD6809E,HD68A09E,HD68B09E
Table 4 a-Bit Accumulator and Memory Instructions
Mnemonic(s)

Operation

AOCA,AOCB

Add memory to accumulator with carry

AOOA,AOOB

Add memory to accumulator

ANOA,ANOB

And memory with accumulator

ASL,ASLA,ASLB

Arithmetic shift of accumulator or memory left

ASR, ASRA, ASRB

Arithmetic shift of accumulator or memory right

BITA, BITB

Bit test memory with accumulator

CLR,CLRA,CLRB

Clear accumulator or memory location

CMPA, CMPB

Compare memory from accumulator

COM, COMA, COMB

Complement accumultor or memory location

DAA

Decimal adjust A accumulator

DEC,OECA,OECB

Decrement accumulator or memory location

EORA, EORB

Exclusive or memory with accumulator

EXG Rl, R2

Exchange Rl with R2 (Rl, R2 =A, 8, CC, OP)

INC, INCA, INCB

Increment accumulator or memory location

LOA, LOB

Load accumulator from memory

LSL, LSLA, LSLB

Logical shift left accumulator or memory location

LSR, LSRA, LSRB

Logical shift right accumulator or memory location

MUL

Unsigned multiply (A x B -+ D)

NEG,NEGA,NEGB

Negate accumulator or memory

ORA, ORB

Or memory with accumulator

ROL, ROLA, ROLB

Rotate accumulator or memory left

ROR, RORA, RORB

Rotate accumulator or memory right

SBCA, SBCB

Subtract memory from accumulator with borrow

STA, STB

Store accumulator to memory

SUBA, SUBB

Subtract memory from accumulator

TST,TSTA,TSTB

Test accumulator or memory location

TFR Rl, R2

Transfer Rl to R2 (Rl, R2 = A, B, CC, OP)

(NOTE) A, B, CC or DP may be pushed to (pulled from) either stack with PSHS, PSHU
(PULS, PULU) instructions.

Table 5 l6-Bit Accumulator and Memory Instructions
Operation

Mnemonic(s)
AOOO

Add memory to 0 accumulator

CMPO

Compare memory from 0 accumulator

EXG 0, R

Exchange 0 with X, V, S, U or PC

LOO

Load 0 accumulator from memory

SEX

Sign Extend B accumulator into A accumulator

STO

Store 0 accumulator to memory

SUBO

Subtract memory from 0 accumulator

TFR O,R

Transfer 0 to X, V, S, U or PC

TFR R,O

Transfer X, V, S, U or PC to 0

(NOTE)

0 may be pushed (pt.llled) to either stack with PSHS, PSHU (PULS, PULU)
instructions.

_HITACHI

309

HD6809E,HD68A09E,HD68B09E--------------------------------------_________
Table 6 Index Register Stack Pointer Instructions
Mnemonic(s)

Operation

CMPS,CMPU

Compare memory from stack pointer

CMPX,CMPY

Compare memory from index register

EXG Rl,R2

Exchangl:! 0, X, Y, S, U or PC with 0, X, Y, S, U or PC

LEAS, LEAU

Load effective address into stack pointer

LEAX,LEAY

Load effective address into index register

LOS, LOU

Load stack pointer from memory

LOX, LOY

Load index register from memory

PSHS

Push A, B, CC, DP, 0, X, Y, U, or PC onto hardware stack

PSHU

Push A, B, CC, DP, 0, X, Y, S, or PC onto user stack

PULS

Pull A, B, CC, DP, 0, X, Y, U or PC from hardware stack

PULU

Pull A, B, CC, DP, 0, X, Y, S or PC from user stack

STS, STU

Store stack pointer to memory

STX, STY

Store index register to memory

TFR Rl, R2

Transfer 0, X, Y, S, U or PC to 0, X, Y, S, U or PC

ABX

Add B accumulator to X (unsigned)

Table 7 Branch Instructions
Mnemonic(s)

Operation
SIMPLE BRANCHES

BEO,LBEO

Branch if equal

BNE,LBNE

Branch if not equal

BMI, LBMI

Branch if minus

BPL,LBPL

Branch if plus

BCS,LBCS

Branch if carry set

BCC,lBCC

Branch if carry clear

BVS, LBVS

Branch if overflow set

BVC, LBVC

Branch if overflow clear

BGT, LBGT

Branch if greater (signed)

SIGNED BRANCHES
BGE, LBGE

Branch if greater than or equal (signed)

BEQ, LBEQ

Branch if equal

BLE,LBLE

Branch if less than or equal (signed)

BLT,LBLT

Branch if less than (signed)

BHI, LBHI

Branch if higher (unsigned)

BHS,LBHS

Branch if higher or same (unSigned)

UNSIGNED BRANCHES

BEQ, LBEQ

Branch if equal

BLS, LBLS

Branch if lower or same (unsigned)

BLO,LBLO

Branch if lower (unsigned)

BSR,LBSR

Branch to subroutine

BRA, LBRA

Branch always

BRN, LBRN

Branch never

OTHER BRANCHES

310

$

HITACHI

HD6809E,HD68A09E,HD68B09E
Table 8 Miscellaneous Instructions
Operation

Mnemonic(s)
ANDCC

AND condition code register

CWAI

AND condition code register, then wait for interrupt

NOP

No operation

ORCC

OR condition code register

JMP

Jump

JSR

Jump to subroutine

RTI

Return from interrupt

RTS

Return from subroutine

SWI. SWI2. SWI3
SYNC

Software interrupt (absolute indirect)

---------

Synchronize with interrupt line

$

HITACHI

311

HD6809E,HD68A09E,HD68B09E-----------------------------------------------Table 9 HD6809E Instruction Set Table
INSTRUCTIONI
FORMS

HD6809E ADDRESSING MODES
IMPLIED
OP

ABX
ADC

-

3A 3

#
1

DIRECT
OP

-

EXTENDED IMMEDIATE

#

OP

-

OP

#

-

#

INDEXEDQ;
OP

-

#

RELATIVE
OP

-(~

UN~G~ED)

4
4

2
2

B9
F9

5
5

3
3

89
C9

2
2

2
2

A9 4+
E9 4+

2+
2+

A+
+ .... A
B+M+C .... B

ADDA
ADDB
ADDD

9B
DB
03

4
4
S

2
2
2

BB
FB
F3

5
5
7

3
3
3

8B
CB
C3

2
2
4

2
2
3

AB 4+
EB 4+
E3 S+

2+
2+
2+

A+M .... A
B+ M .... B
D+M:M + 1 .... 0

AND

ANDA
ANDB
ANDCC

94
04

4
4

2
2

B4
F4

5
5

3
3

84
C4
1C

2
2
3

2
2
2

A4 4+
E4 4+

2+
2+

A AM .... A
BAM .... B
CC/, IMM .... CC

ASL

ASLA
ASLB
ASL

48

08

S

2

78

7

3

S8

S+

2+

~ }DiJ 11111l[

ASAA
ASAB
ASA

47
57

07

S

2

77

7

3

S7

S+

2+

A}
B·
M.7

ASA

2
2
2
2

1
1

BCC

BCC
LBCC

24
10
24

3
2
5(S) 4

BCS

BCS
LBCS

25
10
25

2
3
5(S) 4

BEQ

BEQ
LBEQ

BGE

BGE
LBGE

27
3
2
10 5(S) 4
27
2
2C
3
10 5(S) 4
2C

BGT

BGT
LBGT

2E
10
2E

2
3
5(S) 4

BHI

BHI
LBHI

22
10
22

2
3
5(S) 4

BHS

BHS

24

LBHS

10
24

I

3
3

2
2

5(S) 4

C

•
•
•
•

Branch C=O
Long Branch
c=o
Branch C=1
Long Branch
C=l

••

Branch Z =1
Long Branch
2=1
Branch N GlV=O
Long Branch
N GlV=O
Branch ZVINGlV)=O •
Long Branch
ZV(N GlV)=O

•

•
•
•

Branch
C=O
Long Branch
C=O
Bit Test A (M A A)
Bit Test B (M AB)

2+
2+

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

2F
10
2F

2
3
5(S) 4

Branch Z\IlN GlV)=l
Long Branch
ZV(N GlV)=1

BLO

BlO
lBLO

25
10
25

2
3
5(S) 4

BLS

BlS

23

LBLS

10
23

BLT

BLT
LBLT

20 3
2
10 5(S) 4
20

Branch C=l
Long Branch
C=l
Branch
CVZ=l
Long Branch
CVZ=l
Branch N Gl V=l
Long Branch
N GlV=l

BMI

BMI
LBMI

2B
10
2B

2
3
5(S) 4

Branch N=l
Long Branch
N=l

BNE

BNE
LBNE

26
10
2S

3
2
5(S) 4

Branch 2 =0
Long Branch
Z=O

BPL

BPL
LBPL

2A 3
2
10 5(S) 4
2A

Branch N = 0
Long Branch
N =0

BAA

BAA
LBRA

20
lS

3
5

2
3

Branch Always
long Branchl
Always

BAN

BAN
LBAN

21
10
21

3
5

2
4

Branch Never
Long Branch Never •

85
C5

3

2

5(S) 4

•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•

!
!

!
!

0
0

••
•
•
•
•
• •
• •
• •
• •
•
• •
• •
• •
•• ••
• •
• •

••
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

·• ·•

Branch CVZ=O
Long Branch
CVZ=O

BlE
LBLE

5
5

t

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

t t
,8~
'1I' t t
\8~ t
t

BlE

B5
F5

AS 4+
E5 4+

0

BITA
BITB

4
4

2
2

2

t
t t
t

t

0
0
(-1- \7,1---)
\.8: t
t t t
t t t
~ t
\li't t t t

BIT

95
05

2
2

3

""

t t

t t

•

crrmrto--o

1
1

V C

t t t
t t t
t t t
t t t
• t t
t t
• t t

99
09

58

1 0

3

• • • • •

~ + X .... X

ADCA
ADCB

ADD

2

H N Z

5

DESCRIPTION

#

•
•
•
•

•

••
•
•
•

t
t
!

•
•
•
•
•
•
•
•
•
•
•
•

·•
•
•
••
•
•
•

· ·•

·

•
•
•
•
•
•
•
•
•
•
•

(to be continued)

312

$

HITACHI

HD6809E,HD68A09E,HD68B09E
HD6809E ADDRESSING MODES
INSTRUCTtON/
FORMS

IMPLIED

#

OP -

DIRECT
OP

-

EXTENDED

#

#

OP -

IMMEDIATE
OP

-

#

INDEXED Condition Codes set as a direct result of the instruction if CC is specified, and not affected otherwise.

@

LEGEND:
OP
Operation Code (Hexadecimal)
Number of MPU Cycles
Number of Program Bytes
#
Arithmetic Plus
+
Arithmetic Minus
Multiply
x
Complement of M
M
Transfer Into
Half-carry (from bit 3)
H
Negative (sign bid
N

314

Z
V

C

t

•CC
V
1\

(±)

$

Zero (byte)
Overflow, 2's complement
Carry from bit 7
Test and set if true, cleared otherwise
Not Affected
Condition Code Register
Concatenation
Logical or
Logical and
Logical Exclusive or

HITACHI

HD6809E,HD68A09E,HD68B09E
Table 10 Hexadecimal Values of Machine Codes
OP

00

Mnem

Mode

#

NEG

Direct

2

6

06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13

14
15
16
17
18
19
1A
1B
1C
1D
1E
1F

20
21

22
23
24
25
26
27
28
29

2A
2B

2C
2D
2E
2F

Mnem

Mode

30

LEAX
LEAY
LEAS
LEAU
PSHS
PULS
PSHU
PULU

Indexed

31
32

01

02
03
04
05

OP

COM
LSR

6
6

2
2

ROR
ASR
ASL,LSL
ROL
DEC

6
6
6
6
6

2

INC
TST
JMP
CLR

6
6
3
6

2
2
2
2

Direct

} See
Next Page
NOP
SYNC

Implied
Implied

2
2
2
2

2
2

33
34

35
36
37

38
39
3A
3B
3C

3D

SWI

Implied

19

40

NEGA

Implied

2

41
42
43
44
45
46
47
48

5
9

3
3

DAA
ORCC

Implied
Immed

2

1

49

3

2

4A
4B

ANDCC
SEX
EXG
TFR

Immed
Implied

3
2
8
6

2

4C

1
2
2

4D
4E
4F

BRA
BRN
BHI
BLS
BHS,BCC
BLO, BCS
BNE
BEQ
BVC
BVS
BPL
BMI
BGE
BLT
BGT
BLE

Relative

3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3

2
·2
2

50
51
52
53
54
55
56

Relative

2

2
2
2
2
2
2
2
2
2
2
2
2

5
3
6,15
20
11

3E

Relative
Relative

;

RTS
ABX
RTI
CWAI
MUL

3F

LBRA
LBSR

Implied

1

Indexed
Implied

4+
4+
4+
4+
5+
5+
5+
5+

57

58
59
5A
5B

5C
5D
5E
5F

#

OP

Mnem

M~de

2+
2+
2+
2+

60
61
62
63
64
65
66
67
68
69
6A

NEG

Indexed

2
2

2
2

2

6B
6C

6D
6E
6F

2+

6+
6+

2+
2+

ROR
ASR
ASL, LSL
ROL
DEC

6+
6+
6+
6+
6+

2+
2+
2+
2+
2+

INC
TST

6+
6+
3+
6+

2+
2+
2+
2+

COM
LSR

I

JMP

CLR

Indexed

70
71
72

NEG

Extended

COM
LSR

3

ROR
ASR
ASL, LSL
ROL
DEC

3
3

COMA
LSRA

2

73

2

RORA
ASRA
ASLA, LSLA
ROLA
DECA

2
2
2
2
2

74
75
76

INCA
TSTA

2
2

77
78

79

7A
7B
7C
7D

INC
TST

7E

JMP

3
3

~ .

Implied

2

7F

CLR

Extended

NEGB

Implied

2

80

SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LOA

Immed

81
82

2
2

RORB
ASRB
ASLB, LSLB
ROLB
DECB

83
84

2

85
86

2

87

2
2
2

88
89
8A
8B

2

INCB
TSTB
CLRB

2
Implied

2

8C
8D
8E
8F

4

2
2
2
4
2

2
2
2
2
2

EaR A

ADCA
ORA
ADDA
CMPX
BSR
LDX

3

3

CLRA

COMB
LSRB

#
6+

2

Immed
Relative
Immed

4
7

3

3
3
3
3
2
2
2
3
2
2

2
2
2

2
2
3
2
3

(to be continued)

LEGEND:
-

Number of MPU cycles (less possible push pull or indexed-mode cycles)

# Number of program bytes
•

Denotes unused opcode

~HITACHI

315

HD6809E,HD68A09E,HD68B09E~~~~~~~~~~~~~~~~~~~~~~~
OP

Mnem

Mode

90
91
92
93
94
95
96
97
98
99
9A
98
9C
90
9E
9F

SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LOA
STA
EORA
AOCA
ORA
AODA
CMPX
JSR
LOX
STX

Direct

AO
A1
A2
A3
A4

SUBA
CMPA
SBCA

Indexed

',5

r"IA

A7
A8
A9
AA
AB
AC
AD
AE
AF

LOA
STA
EORA
AOCA
ORA
AODA
CMPX
JSR
LOX
STX

BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF

SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LOA
STA
EORA
AOCA
ORA
AODA
CMPX
JSR
LOX
STX

CO
C1
C2
C3
C4
C5

OP

Mnem

Mode

C6
C7
C8
C9
CA
CB
CC
CD
CE
CF

LOB

Immed

5
5
4+
4+
4+
6+
4+
4+
4+
4+
4+
4+
4+
4+
6+
7+
5+
5+

2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+

5
5

3
3
3
3
3

4

6
4

4
4
4
4
4
4
4
6

Direct

~III>"'"

SUBB
CMPB
SBCB
AODD
ANDB
BITB

#
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

4
4

Indexed
Extended

Extended

'T

Immed

5
5
5
5
5
5
5.
7
8
6
6
2
2
2
4
2
2

3
3
3
3
3
3
3
3
3
3
2
2
2
3
2
2

DO
01
02
03
D4
D5
06
D7
08
D9
DA
DB
DC
DD
DE
DF

EORB
AOCB
ORB
AODB
LDD
LOU

SUBB
CMPB
SBCB
AOOD
ANDB
BITB
LOB
STB
EORB
ADCB
ORB
AODB
LDD
STD
LDU
STU

I

Immed

Direct

I
j
Direct

EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF

SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDB
STB
EORB
ADCB
ORB
ADDB
LDD
STD
LDU
STU

Indexed

FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB

SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LOB
STB
EORB
ADCB
ORB
ADDB

Extended

Indexed

I

Extended

(NOTE): All unused opcodes are both undefined and illegal

316

eHITACHI

#

OP

Mnem

Mode

2

2
2
2
2
2

LDD
STD
LOU
STU

Extinded

2

FC
FD
FE
FF

6
6
6

3
3
3

Extended

6

3

5

4
4
4
4

2
2
2
3

3

3

3

4
4
4
6
4
4
4
4
4

4
4
4

5
5
5
5

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

4+
4+
4+
6+
4+
4+
4+
4+
4+
4+
4+
4+
5+
5+
5+
5+

2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+

5
5
5
7
5
5
5
5
5
5
5
5

3
3
3
3
3
3
3
3
3
3
3
3

#

2 Bytes Opcode

I

1021

LBRN

1022
1023
1024
1025
1026
1027
1028
1029
102A
102B
102C
1020
102E
102F
103F
1083
108C
10SE
1093
109C
109E
109F
10A3
10AC
10AE
10AF
10B3
10BC
10BE
10BF
10CE
100E
10DF
10EE
10EF
10FE
10FF
113F
1183
118C
1193
119C
11A3
11AC
11 B3
11 BC

LBHI
LBLS
LBHS, LBCC
LBCS, LBLO
LBNE
LBEQ
LBVC
LBVS
LBPL
LBMI
LBGE
LBLT
LBGT
LBLE
Relative
Implied
SWI2
CMPD
Immed
CMPY
~
LDY
Immed
CMPD
Direct
CMPY
LDY
STY
Direct
CMPD
Indied
CMPY
LDY
STY
Indexed
CMPD
CMPY
LDY
STY
Extended
LDS
Immed
LOS
Direct
STS
Direct
LOS
Indexed
Indexed
STS
LOS
Extended
Extended
STS
SWI3
Implied
Immed
CMPU
CMPS
Immed
CMPU
Direct
CMPS
Direct
CMPU
Indexed
CMPS
Indexed
CMPU
Extended
CMPS
Extended

Relative

I

t

·"rod

5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
20

4
4
4
4
4
4
4
4

4
4
4
2

5
5

4
4

4

4

7
7

3
3

6
6

3
3

7+
7+
6+
6+

3+
3+
3+
3+

8

4

8

4

7
4

4
4
4

6

3

6
6+
6+

3
3+
3+

7

4

7

4
2
4
4

20
5

5
7

3

7
7+
7+

3'
3+
3+

8

4

8

4

HD6809E,HD68A09E,HD68B09E
• NOTE FOR USE
Execution Sequence of CLR Instruction
Cycle-by-cycle flow of CLR instruction (Direct, Extended,
Indexed Addressing Mode) is shown below. In this sequence
the content of the memory location specified by the operand
is read before writing "00" into it. Note that status Flags, such
as IRQ Flag, will be cleared by this extra data read operation
when accessing the control/status register (sharing the same
address between read and write) of peripheral devices.

Example: CLR (Extended)
$8000
$AOOO

CLR
FCB

$AOOO
$80

Cycle #
1
2

Address
8000
8001

Data
7F
AO

3

8002

00

4
5
6
7

FFFF
AOOO
FFFF
AOOO

•
•
00

80

• The data bus has the data at

R/W

Description
Opcode Fetch
Operand Address,
High Byte
Operand Address,
Low Byte
VMACycle
1
Read the Data
1
VMACycle
1
Store Fixed "00"
o
into Specified
Location
that particular address.
1
1

$

HITACHI

317

HD6309E---------------CMOS MPU

(Micro Processing Unit)
-ADVANCE INFORMATION-

The HD6309E is the highest 8-bit microprocessor of
HMCS6800 family, which is just compatible with the con·
ventional HD6809E.
The HD6309E has hardware and software features which
make it an ideal 'processor for higher level language execution
or standard controller applications. External clock inputs are
provided to allow synchronization with peripherals, systems
or other MPUs.
The HD6309E is complete CMOS device and the power
dissipation is extremely low. Moreover the SYNC and CWAI
instruction makes lower power application possible.
•
•
•

FEATURES
Hardware - Interfaces with All HMCS6800 Peripherals
Software - Fully Compatible with HD6809E, HD6809,
HD6309 MPU families
• Low Power Consumption Mode; SYNC and CWAI instruction
• External Clock Inputs, E and Q, Allow Synchronization with
other devices
• Wide Operation Range
f = 0.5 to 3 MHz (Vee = 5V±10%)

•

PIN ARRANGEMENT
TSC
LIC
RES

AVMA
Q

BUSY

Bus Timing

R/W'

2.0 MHz
2.5 MHz
3.0 MHz
•

HD6309E

BLOCK DIAGRAM

0,
D.
07

+--Vcc

AI.

4 - V ss

(Top View)

FIRQ
IRa

'--~;::::=::"':""-LIC

AVMA

R/iN
TSC
HALT
BA
BS
BUSY

E
L..----O

318

D.
01
0,
0,

@>HITACHI

HD6821, HD68A21, HD68B21PIA (Peripheral Interface Adapter)
The HD6821 Peripheral Interface Adapter provides the
universal means of interfacing peripheral equipment to the
HD6800 Microprocessing Unit (MPU). This device is capable
of interfacing the MPU to peripherals through two 8-bit
bi-directional peripheral data buses and four control lines. No
external logic is required for interfacing to most peripheral
devices.
The functional configuration of the PIA is programmed by
the MPU during system initialization. Each of the peripheral
data lines can be programmed to act as an input or output, and
each of the four control/interrupt lines may be programmed for
one of several control modes. This allows a high degree uf
flexibility in the over-all operation of the interface.

HD6821P, HD68A21P, HD68B21P

• FEATURES
• Two Bi-directional 8-Bit Peripheral Data Bus for interface to
Peripheral devices
•
•
•

Two Programmable Control Registers
Two Programmable Data Direction Registers
Four Individually-Controlled Interrupt Input Lines: Two
Usable as Peripheral Control Outputs
• Handshake Control Logic for Input and Output Peripheral Operation
•

High-Impedance 3·State and Direct Transistor Drive
Peripheral Lines

•

CMOS Drive Capability on Side A Peripheral Lines
Two TTL Drive Capability on All A and B Side Buffers

•

N Channel Silicon Gate MOS

•

Compatible with MC6821, MC68A21 and MC68B21

~

• PIN ARRANGEMENT
vssl"f 0

CA,

PA.

CA,

PA,
PA,

iRaA
iROi

PA,
PAl .§.

AS.

PA,g

ReS

PA.U

0,

AS,

PA,g
PBp 1
PB. ~

Program Controlled Interrupt and Interrupt Disable
capability

•
•

(DP-40)

L-__________________________________________

PB,
PS,

0,

HD6821

~
~

0,
0,
0,
0,

PS. ~

0,

PBI~

0,

PB.~

PB,

#.

CS.

CB'!1::!!
CB,!U

E,

cs,
vccli-,._ _ _ _ _ _--J- A/W

• BLOCK DIAGRAM
CA,
CA,

0,
0,
0,
0,
0,
0,
0,
0,

33
32
31
30
29
2B
27
2B

9

CS,
CS,
lji,
RS,
RS,
Rm

22
24
23
36
36
21

E

26

(Top View)

PA,
PA,
PA,
PA,
PA,
PA,
PA,
PA,

10 pa,
11 pa,
12 pa,
13 PB.
14 PB,
16 pa,
16 pa,
17

pa,

m34

lB CB,

~ 37.-------------------------1-~::~.j

19

ca,

~HITACHI

319

• ABSOLUTE MAXIMUM RATINGS
Symbol

Value

Supply Voltage

Vee *

-0.3 - +7.0

Input Voltage

Yin *

-0.3 - +7.0

Operating Temperature

Topr

-20- +75

Storage Temperature

T stg

-55 - +150

Item

Unit

------+-

V
V
°c

---- --------oC---

* With respect to Vss (SYSTEM GNO)
(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.

• RECOMMENDED OPERATING CONDITIONS
typ

Symbol

min

Supply Voltage

Vee *

4.75

Input Voltage

V'L *
V'H *

-0.3
2.0

-

Topr

-20

25

Item

Operating Temperature

I

max

5.25
5.0
-_._-~.---.0.8

ynit

;
V
---+-._---_._- .. _---I

~

V

--"--7S=--r--oc----

* With respect to Vss (SYSTEM GNO)

•

ELECTRICAL CHARACTERISTICS

•

DC CHARACTERISTICS (Vcc=S.OV±S%. Vss=OV. Ta=-20~+75°C, unless otherwise noted.)
min

typ*

max

Input "High" Voltage

All Inputs

VIH

2.0

-

VGC

Unit
_.l/

Input "Low" Voltage

All Inputs

VIL

-0.3

-

0.8

V

Input Leakage Current

R/W. RES~o. RS I •
CS o • CS I • CS 2 • CA 1 •
CB 1 • E

lin

-2.5

-

2.5

p.A

-

10

p.A

-

-

p.A

-2.4

mA

Item

Symbol

Test Condition

Yin =

~5.25V

0 0 ~07. PB o ~PB7. CB 2
PA o-PA 7 • CA 2

ITSI

Yin = 0.4-2.4V

-10

Input "High" Current

IIH

VIH = 2.4V

-200

Input "Low" Current

PA o-PA 7 • CA 2

IlL

VIL = 0.4V

-

IOH = -205p.A

2.4

Three-State (Off State) Input Current

2.4**

-

IOH = -10p.A

VCC-1.0

-

-

PB o -PB 7 • CB 2

IOH = -200p.A

2.4

0 0 -0 7 • IROA. IROB

IOL = 1.6mA

-

-

0.4

0 0 -0 7
Output "High" Voltage

PA o-PA 7.CA 2

Output "Low" Voltage

VOL

Other Outputs

IOH

PB o-PB 7 • CB 2
Output Leakage Current (Off State)

TR 2 Clock.
This signal must be continuous clock pulse.
• PIA ReadlWrite (R/W)
This signal is generated by the MPU to control the direction
of data transfers on the Data Bus. A "Low" state on the PIA
line enables the input buffers and data is transferred from the
MPU to the PIA on the E signal if the device has been selected.
A "High" on the R/W line sets up the PIA for a transfer of data
to the bus. The PIA output buffers are enabled when the proper
address and the enable pulse E are present.
• Reset (RES)
The active "Low" RES line is used to reset all register bits in
the PIA to a logical zero "Low". This line can be used as a
power-on reset and as a master reset during system operation.
• PIA Chip Select (CS o , CS I and CS 2 )
These three input signals are used to select the PIA. CS o and
CS I must be "High" and CS 2 must be "Low" for selection of
the device. Data transfers are then performed under the control
of the E and R/W signals. The chip select lines must be stable
for the duration of the E pulse. The device is deselected when
any of the chip selects are in the inactive state.
• PIA Register Select (RS o and RS I )
The two register select lines are used to select the various
registers inside the PIA. These two lines are used in conjunction
with internal Control Registers to select a particular register that
is to be written or read.
The register and chip select lines should be stable for the
duration of the E pulse while in the read or write cycle.
• Interrupt Request (lROA and IROB)
The active "Low" Interrupt Request lines (lRQA and IRQB)
act to interrupt the MPU either directly or through interrupt
priority circuitry. These lines are "open drain" (no load device
on the chip). This permits all interrupt request lines to be tied
together in a wire-OR configuration.
Each IBQ..line has two internal interrupt flag bits that can
cause the IRQ line to go "Low". Each flag bit is associated with
a particular peripheral interrupt line. Also four interrupt enable
bits are provided in the PIA which may be used to inhibit a
particular interrupt from a peripheral device.
Servicing an interrupt by the MPU may be accomplished by a
software routine that, on a prioritized basis, sequentially reads
and tests the two control registers in each PIA for interrupt flag
bits that are set.

324

$

The interrupt flags are cleared (zeroed) as a result of an MPU
Read Peripheral Data Operation of the corresponding data
register. After being cleared, the interrupt flag bit cannot be
enabled to be set until the PIA is deselected during an E pulse.
The E pulse is used to condition the interrupt control lines
(CAl, CA 2 , CB I , CB 2 ). When these lines are used as interrupt
inputs at least one E pulse must occur from the inactive edge to
the active edge of the interrupt input signal to condition the
edge sense network. If the interrupt flag has been enabled and
the edge sense circuit has be.en properly conditioned, the
interrupt flag will be set on the next active transition of the
interrupt input pin.
•

PIA PERIPHERAL INTERFACE LINES

The PIA provides two 8-bit bi-directional data buses and four
interrupt/control lines for interfacing to peripheral devices.
• Section A Peripheral Data (PA o-PA7 )
Each of the peripheral data lines can be programmed to act
as an input or output. This is accomplished by setting a "1" in
the corresponding Data Direction Register bit for those lines
which are to be outputs. A ''0'' in a bit of the Data Direction
Regist~r causes the corresponding peripheral data line to act as
an input. During an MPU Read Peripheral Data Operation, the
data on peripheral lines programmed to act as inputs appears
directly on the corresponding MPU Data Bus lines.
The data in Output Register A will appear on the data lines
that are programmed to be outputs. A logical" I" written into
the register will cause a "High" on the corresponding data line
while a "0" results in a "Low". Data in Output Register A may
be read by an MPV "Read Peripheral Data A" operation when
the corresponding lines are programmed as outputs. This data
will be read properly if the voltage on the peripheral data lines is
greater than 2.0 volts for a logic" 1" output and less than 0.8
volt for a logic "0" output. Loading the output lines such that
the voltage on these lines does not reach full voltage causes the
data transferred into the MPU on a Read operation to differ
from that contained in the respective bit of Output Register A.
• Section B Peripheral Data (PB o "'PB7 )
The peripheral data lines in the B Section of the PIA can be
programmed to act as either inputs or outputs in a similar
manner to PA o"'PA 7 • However, the output buffers driving
these lines differ from those driving lines PAo"'PA7 • They have
three-state capability, allowing them to enter a high impedance
state when the peripheral data line is used as a input. In
addition, data on the peripheral data lines PBo '" PB 7 will be
read properly from those lines programmed as outputs even if
the voltages are below 2.0 volts for a "High". As outputs, these
lines are compatible with standard TTL and may also be used as
a source of up to 2.5 milliampere (typ.) at 1.5 volts to directly
drive the base of a transistor switch.
• Interrupt Input (CAl and CB I )
Peripheral Input lines CAl and CB I are input only lines that
set the interrupt flags of the control registers. The active
transition for these signals is also programmed by the two
control registers.
• Peripheral Control (CA2 )
The peripheral control line CA2 can be programmed to act as
an interrupt input or as a peripheral control output. As an
output, this line is compatible with standard TTL. The function
of this signal line is programmed with Control Register A.
• Peripheral Control (CB 2 )
Peripheral Control line CB 2 may also be programmed to act
as an interrupt input or peripheral control output. As an input,

HITACHI

this line has "High" input impedance and is compatible with
standard TTL. As an output it is compatible with standard TTL
and may also be used as a source of up to 2.5 milliampere (typ)
at 1.5 volts to directly drive the base of a transistor switch. This
line is programmed by Control Register B.
(NOTE) 1. Interrupt inputs CAl, CAl, CB I and CBl shall be
used at normal "High" level. When interrupt inputs
are "Low" at reset (RES = "Low"), interrupt flags
CRA6, CRA7, CRB6 and CRB7 may be set.
2. Pulse width of interrupt inputs CAl', CAl, CB I and
CBl shall be greater than a E cycle time. In the case
that "High" time of E signal is not contained in
Interrupt pulse, an interrupt flag may not be set.

INTERNAL CONTROLS

There are six locations within the PIA accessible to the MPU
data bus: two Peripheral Registers, two Data Direction Registers, and two Control Registers. Selection of these locations is
controlled by the RS o and RS I inputs together with bit 2 in the
Control Register, as shown in Table 1.
Table 1 I nternal Addressing
Control
Register Bit

f

;~~~~rh~~:NormaIlYt
Input

•

~

_

More than a Cycle Time

CRA2

CRB2

0

0

1

x

Peripheral Register A *

0
0

0

0
x

x
x

Data Direction Register A

1

0

1

Peripheral Register B*

1

0

x
x

0

Data Direction Register B

1

1

x

x

Control Register B

1

Location Selected

Control Register A

• Initialization

A "Low" reset line has the effect of zeroing all PIA registers.
This will set PAo~PA7' PBo~PB7' CA 2 and CB 2 as inputs, and
all interrupts disabled. The PIA must be configured during the
restart program which follows the reset.
Details of possible configurations of the Data Direction and
Control Register are as follows.

+5V

~------+--<

RS o

x = Don't Care
* Peripheral interface register is a generic term containing peripheral
data bus and output register.

• The equivalent Circuit of the Lines on Peripheral side

The equivalent circuit of the lines on Peripheral side is shown
in Fig. 15. The output circuits of A port is different from
that of B port. When the port is used as input, the input is
pullup to Vee side through load MaS in A port and B port
becomes "Off' (high impedance).

RS,

~----------~~~-+PAx

From

•

Data Direction Registers (DDRA and DDRB)

The two Data Direction Registers allow the MPU to control
the direction of data through each corresponding peripheral
data line. A Data Direction Register bit set at "0" configur~s the
corresponding peripheral data line as an input; a "1" results in
an output.

ORA

(a) Section A

•

Control Registers (CRA and eRB)

The two Control Registers (CRA and CRB) allow the MPU to
control the operation of the four peripheral control lines CAl,
CA 2 , CB I and CB 2 • In addition they allow the MPU to enable
the interrupt lines and monitor the status of the interrupt flags.
Bits 0 through 5 of the two registers may be written or read by
the MPU when the proper chip select and register select signals
are applied. Bits 6 and 7 of the two registers are read only and
are modified by external interrupts occurring on control lines
CAl, CA 2 , CB I or CB 2 • The format of the control words is
shown in Table 2.

From DDR B

+5V

To Data Bus

Table 2 Control Word Format
~~--~-------r--~~~-'PBx

From ORB

>----'~--------------_I.,./

l

7

1

6

I

5

I

7

I

6

I

CRB llRQB1 IIRQB21

(b) Section B
Figure 15 Peripheral Data Bus

~HITACHI

I

4

I

3

CA, Control

CRA IIRQA1 IIRQA21

5

I

4

I

3

CB. Control

I

2

I

1Access
DORA I
I

2

I

1Access
DDRB I

1

I

0

CA, Control

1

I

0

CB, Control

325

Data Direction Access Control Bit (CRA2 and CRB2)

CRBO are used to enable the MPU interrupt signals IRQA and

Bit 2 in each Control register (CRA and CRB) allows
selection of either a Peripheral Interface Register or the Data
Direction Register when the proper register select signals are
applied to RS o and RS I ·

TRQIi, respectively. Bits CRAt and CRBI determine the active

Interrupt Flags (CRA6, CRA7, CRB6, and CRB7)

The four interrupt flag bits are set by active transitions of
signals on the four Interrupt and Peripheral Control lines when
those lines are programmed to be inputs. These bits cannot be
set directly from the MPU Data Bus and are reset indirectly by a
Read Peripheral Data Operation on the appropriate section.
Control of CAl and CB I Interrupt Lines (CRAO, CRBO, CRA1,
and CRB1)

The two lowest order bits of the control registers are used to
control the interrupt input lines CAl and CBI' Bits CRAO and

transition of the interrupt input signals CAl and CBI (Table 3)
Control of CA2 and CB2 Peripheral Control Lines (CRA3,
CRA4, CRAS, CRB3, CRB4, and CRBS)

Bits 3, 4 and 5 of the two control registers are used to
control the CA2 and CB2 Peripheral Control lines. These bits
determine if the control lines will be an interrupt input or an
output control signal. If bit CRAS (CRBS) is "0" CA 2 (CB 2 )
is an interrupt input line similar to CAl (CBl)(Table 4). When
CRAS (CRBS) is "1", CA2 (CB 2 ) becomes an output signal
that may be used to control peripheral data transfers. When in
the output mode, CA 2 and CB 2 have slightly different
characteristics (Table Sand 6).

Table 3 Control of Interrupt Inputs CAl and CB l
MPU Interrupt
Request
IROA (i'RCm)

CRAl
(CRB1)

CRAO
(CRBO)

Interrupt Input
CAl (CB l )

Interrupt Flag
CRA7 (CRB7)

0

0

.J,. Active

Disabled - i'R'Q remains
"High"

0

1

.J,. Active

Set "1" on.J,. of CAl
(CB l )
Set "1" on .J,. of CAl
(CB l )

1

0

t

Active

Set "'" on t of CAl
(CB I )

Disabled - I RO remains
"High"

1

1

t Active

Set "1" on t of CAl
(CBt!

Goes "Low" when the interrupt flag bit CRA7 (CRB7)
goes "1"

(Notes)

Goes " Low" when the interrupt flag bit CRA7 (CRB7)
goes "1"

,. t indicates positive transition ("Low" to "High")
2. l indicates negative transition ("HiQh" to "Low")
3. The Interrupt flag bit CRA 7 is cleared bv an MPU Read of the A Peripheral Register
and CRB7 is cleared by an MPU Read ot the B Peripheral Register.
4. If CRAOJ.C.B.BO) is "0" when an interrupt occurs (Interrupt disabled) and is later brought ",".
~ (llfilB) occurs after CRAO (CRBO) is written to a"'''.

Table 4 Control of CA2 and CB 2 as Interrupt Inputs - CRAS (CRBS) is "0"
CRAS
(CRBS)

CRA4
(CRB4)

CRA3
(CRB3)

Interrupt Input
CA2 (CB 2 )

Interrupt Flag
CRA6 (CRB6)

MPU Interrupt
Request
IROA (lROB)

0

0

0

.J,. Active

Set "1" on.J,. of CA 2
(CB 2 )

Disabled - IRO remains
"High"

·0

0

1

.J,. Active

Set "1" on.J,. of CA2
(CB 2 )

0

1

0

t Active

0

1

1

t Active

Set "1" on t of CA 2
(CB2)
Set "1" on t of CA2
(CB 2 )

Goes "Low" when the interrupt flag bit CRA6 (CRB6)
goes "1"
Disabled - IRO remains
"High"

(Notes)

326

Goes "Low" when the interrupt flag bit CRA6 (CRB6)
goes "1"

1. t indicates positive transition ("Low" to "High")
2_ l indicates negative transition ("High" to "Low")
3. The interrupt flag bit CRA6 is cleared by an MPU Read of the A Peripheral Register and CRB6 is
cleared by an MPU Read of the B Peripheral Register.
4. If CRA3 (CRJ!llis "0" when an interrupt occurs (Interrupt disabled) and is later brought
",", IROA (IROB) occurs after CRA3 (CRB3) is written to a"'''.

e

HITACHI

Table S Control of CB2 as an Output - CRBS is "1"
CB 2
CRB5
1

Cleared
"Low" on the positive transition of
the first E pulse after MPU
Write "B" Data Register operation.

Set
"High" when the interrupt flag bit
CRB7 is set by an active transition
of the CB I signal. (See Figure 16)

"Low" on the positive transition of
the first E pulse after an MPU Write
"B" Data Register operation.

"High" on the positive edge of the
first "E" pulse following an "E"
pulse which occurred while the
part was deselected. (See Figure 16)

CRB4

CRB3

0

0

1

0

1

1

1

0

" Low"
(The content of CR B3 is output on CB 2 )

1

1

1

"High"
(The content of CRB3 is output on CB 2 )

Table 6 Control of CA2 as an Output - CRAS is "1"
CA 2
CRA3
Cleared
"Low" on negative transition of E
0
after an MPU Read" A" Data Operation.

CRAS

CRA4

1

0

1

0

1

1

1

0

1

1

1

"Low" on negative transition of E
after an MPU Read "A" Data operatign.

Set
"High" when the interrupt flag bit
CRA7 is set by an active transition
of the CAl signal. (See Figure 16)
"High" on the negative edge of the
first "E" pulse which occurs during
a deselect. (See Figure 16)

"Low"
(The content of CRA3 is output on CA 2 )
"High"
(The content of CRA3 is output on CA 2 )

eHITACHI

327

HD6821,HD68A21,HD68B21------------------------------____________________
• PIA OPERATION
•

Initialization

When the external reset input RES goes "Low", all internal
registers are cleared to ''0''. Periperal data port (PAo -PA7.
PBo-PB,) is dermed to be input and control lines (CAl. CA 2 •
CB I and CB 2 ) are dermed to be the interrupt input lines. PIA is
also initialized by software sequence as follows.
• Program the data direction register access bit of the control
register to "0" to allow to access the dada direction register.

Clear the control register
Load input/output direction data into ACC

Store the contents of ACC into the
data direction register

Load the control data to be written into ACC

• The data of the control line function is set into the accumulator, of which Data Direction Register Access Bit shall be
programmed to "1".
• Transfer the control data from the accumulator into the
control register.

Store the contents of ACC into the control register

Input/output processing

•

Read/VVrite Operation Not Using Control Lines

Set the data direction register to "00"

Initialize the control register

Load the contents of the peripheral
interface register into the accumulator

CRA
•
DORA •

CLR
CLR
LDAA
STAA

#$04

•

CRA

LDAA

PIRA

CLR
LDAA
STAA

CRA

Clear the DDRA access bit of the control register to "0" .
Clear all bits of the dada direction register.
Set DDRA access bit of the control register to "1" to allow
to access the peripheral interface register.


Set the data direction register to "FF"

Initialize the control register

Store the data in the accumulator into
output register

328

•

#$FF }.
DDRB

#$O4}.

LDAA
STAA : CRB
LDAA
STAA

Set DDRB access bit of the control register to "0".
Set all bits of the data direction reaister
to "FF".
C"

Set DDRB access bit of the control register to "1" to allow to
access the peripheral interface register.

I

DATA} •
PIRB

Write the data into the peripheral interface register.

_HITACHI

• Read/Write Operating Using Control Lines

Read/write request from peripherals shall be put into the
control lines as an interrupt signal, and then MPU reads or
writes after detecting interrupt request.


The following case is that Port A is used and that the rising
edge of CAl indicates the request for read from peripherals.

Set the data direction register to "00"

CLR
CLR

LDAA #$06

Initialize the control register

Program the rising edge of CAl to be active. IRQA is masked
and OORA access bit is set to 1.

•

STAA CRA

LOOP

Load the contents of the control register
into the accumulator

Set the OORA access bit to "0".
Set all bits of the data direction register to "0".

CRA •
DORA.

LOAA eRA
BPL LOOP

I
j.

Check whether the read request comes from peripherals
or not.

No

Load the contents of the peripheral
interface register into the accumulator

LDAA PIRA

• Load the data from the peripheral interface register into the
accumulator. CRA flag is reset after this read operation.

To read the peripheral data, the data is directly transfered to
the data buses 0 0 -0, through PAo-PA, or PBo-PB, and
they are not latched in the PIA. If necessary, the data should be
held in the external latch until MPU completes reading it.
When initializing the control register, interrupt flag bit
(CRA7, CRA6, CRB7, CRB6) cannot be written from MPU. If
necessary the interrupt flag must be reset by dummy read of
Peripheral Register A and B.

Write operation using the interrupt signal is as follows. In
this casez..!.port is used and interrupt request is input to CB I .
And the IRQ flag is set at the rising edge of CB I .

~HITACHI

329

Set the data direction register to "FF"

Initialize the control register

Load the contents of the control
register into the accumulator

• Set DDRB access bit to "0"

CLR
LDAA
STAA

CRB
#$FF
DDRB

}•

Set all bits of DDRB to output" 1".

LDAA
STAA

#$06
CRB

}•

Program the rising edge of CB I to be active. IRQB is masked
and DDRB access bit is set to "I".

LOOP LDAA
BPL

CRB
LOOP

• Check whether the write request comes from peripherals
or not.

No

Load the contents of the output
register in the accumulator

LDAA

PIRB

• Reset the CRB7 flag by the dummy read of the
peripheral interface register.

Store the contents of the accumulator
into the output register

STAB

PIRB

• Store the data of the accumulator B to the peripheral
interface register.

Interrupt request flag bits (C'RA7, CRA6, CRB7 and CRB6)
cannot be written and they cannot be also reset by write
operation to the peripheral interface register. So dummy read of
peripheral interface register is needed to reset the flags.
To accept the next interrupt, it is essential to reset indirectly
the interrupt flag by dummy read of peripheral interface
register.
Software poling method mentioned above requires MPU to
continuously monitor the control register to detect the read/
write request from peripherals. So other programs cannot run at
the same time. To avoid this problem, hardware interrupt may
be used. The MPU is interrupted by mOA or 11U}B when the
read/write request is occurred from peripherals and then MPU
analyzes cause of the interrupt request during interrupt processing.
• Handshake Mode
The functions of CRA and CRB are similar but not identical
in the hand-shake modes. Port A is used for read hand-shake
operation and Port B is used for write hand-shake mode.
CAt and CB I are used for interrupt input requests and CAl
and CB z are control outputs (answer) in hand-shake mode.
Fig. 16, Fig. 17 and Fig. 18 show the timing of hand-shake
mode.

< Read Hand-shake Mode>
CRAS=" I ", CRA4="0" and CRA3="0"
r,; A peripheral device puts the 8-bit data on the peripheral
data lines after the control output CAl goes "Low".

m

330

!he peripheral requests MPU to read the data by using CAl
mput.

$

'3') CRA 7 flag is set and CAz becomes "High" (CA 2 auto-

'4)
is)

matically becomes "High" by the interrupt CAl)' This
indicates the peripheral to maintain the current data and
not to transfer the next data.
MPU accepts the read request by IRQA hardware interrupt
or CRA read. Then MPU reads the peripheral register A.
CA 2 goes "Low" on the following edge of read Enable
pulse. This informs that the peripheral can set the next data
to port A.


CRBS = "I", CRB4 = "0" and CRB3 = "0"
'1' A peripheral device requests MPU to write the data by using
CB t input. CB l output remains "High" until MPU write
data to the peripheral interface register.
'2) CRB7 flag is set and MPU accepts the write request.
(3) MPU reads the peripheral interface register to reset CRB7
(dununy read).
@ Then MPU write data to the peripheral interface register.
The data is output to port B through the output register.
(5) CB 2 automatically becomes "Low" to tell the peripheral
that new data is on port B.
® The peripheral read the data on Port B peripheral data lines
and set CB I to "Low" to tell MPU that the data on the
peripheral data lines has been taken and that next data can
be written to the peripheral interface register.

CRAS = "1", CRA4 = "0" and CRA3 = "1"
CRBS = "I", CRB4 = "0" and CRB3 = "I"
This mode is shown in Figure 16, Figure 19 and Figure 20.

HITACHI

Timing

CRAS CRA4 CRA3

:m~
CS·RS,

I

.~

0 0 -0,

I

:

~------~i----------------I
>-----~---------------

CAl

,;, ,r---

R EAO Request

5
a..
CRA7
CA,

o
o
CRBS

IL.--~~......;..J

of PA o -PA, i
is not allowed. I
PA o -PA,\ are
Busy
allowed to be set.
CA,
ReJdy ,.....~------l.;;
The

o

chan~e

Busy

Timing

CRB4 CRB3
E

R/W

CS· RS, • _R_So;;..._ _--'
0 0 -0,

PBo-PB, _ _ _ _ _ _ _ _ _-<

o

o

CB,

o

PS o -PB, data is old.

CB,

,.......~--""'!S~U-Sy----., PB o -PB, data is new.

Ready

Figure 16 Timing of Hand-shake Mode and Pulse Mode

~HITACHI

331

HD6821 ,HD68A21 ,HD68821
Goes "High" on
transition of CA I
(I RQA 1 Flag bit sad

r---=-==

\J~----------~/:

J

CAl

Goes "Low" when data on
"A" side has been read by
MPU after falling edge
of ....bIe >;gMI
(LOA A PIRA)

Enable signal IE)

Handshaking with peripheral on 'A' side
Data

PIRA

CA'I~

____________

CA2~

________~~~

~

Peripheral

PIA
CRA
0
7
Ixloll1ol01110111
....J
7

Peripheral Says:
Here's new data
(Sets CRA7)

Says: Data taken
(LOA A PIRA)

Figure 17 Bits 5,4,3 of CRA = 100 (Hand-shake Mode)

::'3'

Goes "Low" on first
positive edge of enable
signal aftar the MPU
stores data to the "B"
side. ISTA A PIRB)

Goes "High" or transition

fI~ ~t ~I

t_

',I----__

~na~le

signal
IE)

Handshaking with peripheral on 'B' side
Data

I
PIRB

CB11~--------------~

~

PIA

Peripheral

CB2~----------~~~1

(x 1Olll~rolll ° 11°,

r~

Peripheral
Request for data

Says: Here'. new data /
(STA A PIRB)

Figure 18 Bits 5, 4, 3 of CRB

=100 (Hand-shake Mode)

eHITACHI

~~~~~~~~~~~~~~~~~~~~~~~~HD6821,HD68A21,HD68B21

Enable
signal (E)

Goes "High" on
the negative
edge of the
next E pulse
after a
"Read a
side data"
Instruction
(LOA)

Goes "Low" after a "Read a side
data" Instruction (LOA)
(Negative transition of E)

CA2 Normally
'''High''

I""_____

....J

Pulse mode
Pulse output on 'A' side

l!.~

I

Data

111
I

PIRA

Peripheral

PIA
CA2

CRA

7

0

I _I l' I l' l' I _I _I
0

0

'",..of ;.;,"''''
§,side".."
reading 'A'
(LOA A PIRA)

X

0,
a a "R ead" b y M'U

Figure 19 Bits 5,4,3 of CRA = 101 (Pulse Mode)
CB 2 Normally
"High"

Goes "High" on the
next positive E
pulse after A
"write B
side data"
instruction

Goes "Low" on the positive
transition of the first
E pulse after a "write B
side data" instruction

(STA)

(STA)

Enable
signal
(E)

1 . . ___-'
Pulse mode
Pulse output on 'B' side

If I
I

PIRB

~!ll

Data

1
Peripheral

PIA
7

CRB

CB2
0

1_101'101'1'1_1_1

...

Pulse ',:,,~,at~d aS,a ,re~ult
of (~~~ng~n~~R~) SIde

X-_"""'''d
at port
for peripheral

Figure 20 Bits 5,4,3 of CRB=101 (Pulse Mode)

eHITACHI

333

• SUMMARY OF CONTROL REGISTERS CRA AND CRB
Control registers CRA and CRB have total control of CAl,
CA z , CB I , and CB z lines. The status of eight bits of the control
registers may be read into the MPU. However, the MPU can only
write into Bit 0 through Bit 5 (6 bits), since Bit 6 and Bit 7 are
set only by CAl, CAl, CB t , or CBl .
• Addressing PIAs
Before addressing PIAs, the data direction (DDR) must first
be loaded with the bit pattern that defines how each line is to
function, i.e., as an input or an output. A logic "I" in the data
direction register defines the corresponding line as an output
while a logic "0" defines the corresponding line as an input.
Since the DDR and the peripheral interface resister have the same
address, the control register bit 2 determines which register is
being addressed. If Bit 2 in the control register is a logic "0",
then the DDR is addressed. If Bit 2 in the control register is a
logic" I", the peripheral interface register is addressed. Therefore, it is essential that the DDR be loaded first before setting
Bit 2 of the control register.

Given a PIA with an address of 4004,4005,4006, and 4007.
4004 is the address of the A side peripheral interface register.
4005 is the address of the A side control register. 4006 is the
address of the B side peripheral interface register. 4007 is the
address of the B side control register. On the A side, Bits 0, I, 2,
and 3 will be defined as inputs, while Bits 4, 5, 6, and 7 will be
used as outputs. On the B side, al11ines will be used as outputs.

1.
2.
3.
4.
5.
6.
7.

PIA lAD = 4004
PIA 1AC =4005
PIA I BD =4006
PIA 1BC =4007

(DDRA, PIRA)
(CRA)
(DDRB, PIRB)
(CRB)

LDA A #%11110000
PIAIAD
STA A
LDA A #% 11111111
STA A
PIAIBD
LDA A #%00000 100
STA A
PIAIAC
STA A
PIAIBC

(4 outputs, 4 inputs)
(Loads A DDR)
(All outputs)
(Loads B DDR)
(Sets Bit 2)
(Bit 2 set in A control register)
(Bit 2 set in B control register)

•

Active Low Outputs

When all the outputs of given PIA port are to be active "Low"
(True ~ 0.4 volts), the following procedure should be used.
a)
b)
c)
d)
e)

Set Bit 2 in the control register.
Store all Is ($FF) in the peripheral interface register.
Clear Bit 2 in the control register.
Store all Is ($FF) in the data direction register.
Store control word (Bit 2 = I) in control register.


The B side of PIAl is set up to have all active low outputs.
CB I and CBl are set up to allow interrupts in the HANDSHAKE MODE and CB I will respond to positive edges
("Low"-to-"High" transitions). Assume reset conditions. Addresses are set up and equated to the same labels as previous
example.

1.
2.
3.
4.
5.
6.
7.
8.

LDA A #4
STA A PIAIBC
LDA B#$FF
STA B PIAIBD
CLR PIAIBC
STA B PIAIBD
LDA A #$27
STA A PIAIBC

The program shown in the previous section can be accomplished using the Index Register.
LDX
STX
LDX
STX'

#$ F004
PIA lAD
#$FF04
PIAIBD

$FO~PIA I AD .;$04~PIA I AC
$FF~PIAIBD;$04~PIAIBC

Using the index register in this example has saved six bytes of
program memory as compared to the program shown in the
previous section.

334

00100111- control register

•

Interchanging RSo And RS J
Some system applications may require movement of 16 bits
of data to or from the "outside world" via two PIA ports (A
side + B side). When this is the case it is an advantage to
interconnect RS I and RS o as follows.
RS o to Al (Address Line AI)
RS I to AO (Address Line AO)

This will place the peripheral interface registers and control
registers side by side in the memory map as follows.
Table
PIAIAD
PIAIBD
PIAIAC
PIAIBC

PIA Programming Via The Index Register

I.
2.
3.
4.

All I s in peripheral interface register
Clear Bit 2
All I s in data direction register

The above procedure is required in order to avoid outputs
going "Low", to the active "Low" TRUE STATE, when allis
are stored to the data direction register as would be the case if
the normal configuration procedure were followed.

Statement 2 addresses the DDR, since the control register
(Bit 2) has not been loaded. Statements 6 and 7 load the control
registers with Bit 2 set, so addressing PIA lAD or PIA lBD
accesses the peripheral interface register.
•

Set Bit 2 in PIAIBC (control register)

Example Addr('ss
$4004
$4005
$4006
$4007

(DDRA, PIRA)
(DDRB, PIRB)
(CRA)
(CRB)

The index register or stackpointer may be used to move the
16-bit data in two 8-bit bytes with one instruction. As an
example:
LDX PIAIAD
IXL
PIAIAD - IX»: PIAlBD • PIA - After Reset
When the RES (Reset Line) has been held "Low" for a
minimum of one microsecond, aU registers in the PIA will be
•
cleared.
Because of the reset conditions, the PIA has been defined as

eHITACHI

follows.
1. All I/O lines to the "outside world" have been defined as
inputs.
2." CAl, CA2 , CBl , and CB2 have been defmed as interrupt
input lines that are negative edge sensitive.
3. All the interrupts on the control lines are masked. Setting of
interrupt flag bits will not cause IROA or IRQB to go "Low".

• SUMMARY OF CA2 -CB2 PROGRAMMING
Bits 5, 4, and 3 of the control registers are used to program
the operation of CAz -CBz .

CA2 -CB 2
Input ~
Mode

• SUMMARY OF CAl ·CB I PROGRAMMING
Bits 1 and 0 of the respective control registers are used to
program the interrupt input control lines CAl and CB I •

bl

bO

o
o

o
1
o

1
1

bl
bO

W
b5

CA2 -CB z
Output ~
Mode

0
0

b4

0(-)
0(-)

o

1(+)
1(+)

1
1

0
0
1

1

1

m

b3

o

(Mask) CAz -CB 2 Input Mode
(Allow) b4 = Edge (0 = -, 1 = +)
(Mask) b3 =Mask (0 =Mask,
(Allow)
1 =Allow)

1

o
1

o-

Handshake Mode
1 - Pulse Mode

~

} b3 Following Mode

= Edge (0 = -, 1 = +)
= Mask (0 = Mask, 1 = Allow)

1

Note that this is the same logic as Bits 4 and 3 for CA 2 -CB 2
when CA 2 -CB 2 are progranuned as inputs.

...~f------CA,

1-----~.CA2

I/O As Follow:
Control Lines:
CAl - Positive Edge, Allow Interrupt
CA 2 - Pulse Mode
CBI - Negative Edge, Mask Interrupt
CB 2 - Hand Shake Mode

~------.~PA7

~~~----__ PA.

"A"

~--------.: PAs

1--------,...

PA.

~-----......j~. PA 3

~-----.~ PA 2
Assume Reset Condition
PIA1AD
PIA1AC
PIA1BD
PIA1BC
PIA Configuration Solytion
LOA A #$BC
10111100
STA A PIA1AD
I/O to DORA
LOA A #$FF
11111111
STA A PIA1BD
I/O to DDRB
LOA A #$2F
0010 1111
STA A PIA1AC
To "A" Control
LOA A #$24
00100100
STA A PIA1BC
To "B" Control

1oI~....- - - - - - - PA,

1oI;~....- - - - - - - - PAo
~------------

\oIII.~t------- CB,

1--------:..
1---------:.

CB 2
PB 7

"B"

1------.:.

PB o

Figure 21 PIA Configuration Problem

eHITACHI

335

HD6321 ,HD63A21 ,HD63B21CMOS PIA (Peripheral Interface Adapter)
-PRELIMINARYThe HD6321 is a CMOS Peripheral Interface Adapter provides the universal means of interfacing peripheral equipment
to the HD6800 Microprocessing Unit (MPU). This device is
capable of interfacing the MPU to peripherals through two
8-bit bi-directional peripheral data buses and four control
lines. No external logic is required for interfacing to most
peripheral devices.
The functional configuration of the PIA is programmed
by the MPU during system initialization. Each of the peripheral data lines can be programmed to act as an input or
output, and each of the four control/interrupt lines may be
programmed for one of several control mode. This allows
a high degree of flexibility in the over-all operation of the
interface. Exceeding Low power dissipation is realized due
to adopting CMOS process.
• FEATURES
• Low-Power, High-Speed, High-Density CMOS
• Compatible with NMOS PIA (HD6821) (Refer to Electrical Specification as to Minor difference.)
• Two Bi-directional 8-Bit Peripheral Data Bus for interface
to Peripheral devices
• High·lmpedance 3·State and Direct Transistor Drive Peri·
pheral Lines
• Two TTL Drive Capability on All A and B Side Buffers
• Handshake Control Logic for Input and Output Peripheral
Operation
CAt, CA 2 • • • • • •• Port A
(PAo "'" PA 7 )
(PBo ..... PB 7 )
CB t , CB 2 • • • • • • • Port B
• Two Programmable Control Registers
(CRA,CRB)
• Two Programmable Data Direction Registers
(DORA, DDRB)

HD6321 P,HD63A21 P,HD63B21 P

(DP-40)
HD6321 FP, HD63A~1 FP, HD63B21 FP

(FP-54)

•

BLOCK DIAGRAM

Do
0,

0,
0,
D.
D.
0,
0,

Vee
V..

CSo
CS.

cs.

RSo
RS.

PAD
PA,
PA,
PA,
PA.
PA,
PAl
PA,

PBo
PI.
PI,
PI,

PI.
Pie

PI.
PI,

R/W
E

m

IAOli ------------L~~!.J

336

~HITACHI

CI,
CI,

-----------------------------------------------------HD6321,HD63A21,HD63821
•
•

PIN ARRANGEMENT
H06321P, H063A21P, H063B21P

•

H06321 FP, H063A21 FP, H063B21 FP

J.
~ ci. J. ~ - "I~ I~
~~~~> ~~~~~

o

0





PA.
PAs
PA 6
PA,
PBo
PBI
PB ,
PB 3
PB.

03

04
05
06

- Preliminary -

PBs



33 

01" -

12
<:(/)(1)(1)

a:()UUW

(Top View)

(Top View)

•

ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage
Input Voltage

Symbol

Value

Unit

Vee *
V in *

-0.3 -- +7.0
-0.3 -- +7.0
10

V
mA

100

mA

-20 -- +75
-55 -- +150

°c
°c

Maximum Output Current

1101**

Maximum Total Output Current
Operating Temperature

ILlol***

Storage Temperature

Topr
Tstg

V

• With respect to Vss (SYSTEM GNO)
** Maximum output current is the maximum current which can flow in or flow out from one output terminal and I/O common
terminal. (PA o - PA 7 , CA" PS o - PB 7 , CB" Do - D7 )
* ** Maximum total output current is the total sum of output current which can flow in or flow out simultaneously from output
terminals and I/O common terminals.(PA o - PA 7 , CA" PS o - PB 7 , CB., Do - D7 )
(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended
operating conditions. If these conditions are exceeded, it could affect reliability of LSI.

~HITACHI

337

•

RECOMMENDED OPERATING CONDITIONS
Item

Symbol

min

typ

max

Unit

Supply Voltage

Vee *

4.5

5.0

5.5

V

Input "Low" Voltage

V IL *

0

-

0.8

-

Vee

25

75

Input "High"
Voltage

Do - 0 7 , PAo - PA 7 , CAl, CA 2 ,
PB o - PB 7 , CB I , CB 2

2.2
V IH

E, R/W, CS o , CS 2 ,CS I , RS o ,
RS I , RES

*

V

3.0**

Operating Temperature

-20

Topr

°c

* With respect to Vss (SYSTEM GNO)

** Characteristics will be improved.

•

ELECTRICAL CHARACTERISTICS

•

DC CHARACTERISTICS (Vcc=5.0V±10%, Vss:=OV, Ta=-20-+7SoC, unless otherwise noted.)
Item

Symbol
Do -0 7 , PA o -PA 7 •
CA •• CA 2 • PB o -PB 7 •
CB •• CB 2

Input "High" Voltage

Test Condition

VIH

E. Rm. CSo. CS2 • CS ••
RS o . RS •• RES"
All Inputs

Vil

Input Leakage Current

R/W. RES~o. RS •.
CS o . CS •. CS l • CA •.
CB •. E

lin

Do -0 7 • PB o -PB 7 • CBl

ITSI

0 0 -0 7
Output "High" Voltage

VOH

Output Leakage Current (Off State)

Output Capacitance

..

2.2

-

Vee

V

-'0.3

-

0.8

V

Vin = 0 '" Vcc

-2.S

-

2.S

/lA

Vin = 0.4 - Vcc
IOH = -400/lA

-10

-

10

/lA

IOH < -10/lA
IOH = -400/lA
IOH< -10/lA

Vee -0.1
4.1

-

4.1

-

= 1.6mA

-

IOl

= 3.2mA

-

-

0.6

ILOH

VOH

= Vee

-

10

-

12.5

R/W. RES. RS o • RS t •
CS o . CS •. CS 2 • CA •.
CBt. E

Cin

Vin = OV.
Ta = 2SoC.
f = 1.0MHz

-

-

-

10

IRQA.IRQB

Cout

Vin = OV.
Ta = 2SoC.
f = 1.0MHz

-

-

10

E = 1.0MHz

-

-

300

E = 1.SMHz

-

-

400

E = 2.0MHz

-

-

SOO

.PAo -PA 7 • CA 2 and
PB o"'PB 7 • CB 2 are
specified as input .
• Chip is not selected
• Input level (Except E)
VIH min = Vee-0.8V
Vil max = 0.8V

Supply Current*

Unit

IOl

Do -0 7 • I RQA. I ROB
PA o -PA 7 • CA 2
PB o-PB 7 • CB 2
IRQA.IROB

VOL

PA o -PA 7 • PB o -PB 7 •
CA 2 • CB 2 • 0 0 -0 7
Input Capacitance

max

-

PA o -PA 7 • CA 2
PB o -PB 7 • CBl
Output "Low" Voltage

typ

3.0·*

Input "Low" Voltage

Three-State (Off State) Input Current

min

.PA o-PA 7 • CA 2 and
PB o "'PB 7 • CB 2 are
specified as input.
• Under Data Bus R!W
operation

Icc

1-----

Vee -0.1

0.4
V
/lA

pF
i---

E = 1.0MHz

-

-

4

E = 1.SMHz

-

-

S

E = 2.0MHz

-

-

6

~HITACHI

V

-

pF

• Supply current IS defined on the condition that there IS no current flow from output terminals. Supply current will be Increased when
the current from output terminal exists. Also the current will be increased for charging and discharging the capacitive load. Please take
this case into consideration in estimating system power.
** Characteristics will be improved.

338

-

/lA

mA

----------------------------------------------------HD6321,HD63A21,HD63B21
• AC CHARACTERISTICS (VcC=5.0V±10%,vSS=O, Ta=-20-+75°C, unless otherwise noted.)
1. PERIPHERAL TIMING
Symbol

Item

Test Condition

HD63A21

HD6321
min

max

min

max

-

100

-

ns

Peripheral Data Setup Time

tposu

Fig. 1

100

-

100

tPOH

Fig. 1

0

-

0

Enable .... CA. Negative

tCA2

Delay Time. Enable negative
transition to CA. positive
transition

Enable .... CA, Positive

tRSl

Aise and Fall Times for CA,
and CA. input signals

CA,.CA.

Delay Time from CA, active
transition to CA. positive
transition

Unit

min

Peripheral Data Hold Time
Delay Time, Enable negative
transition to CA. negative
transition

HD63B21

max

0

ns

-

200

-

200

-

200

ns

Fig. 2

-

200

-

200

-

200

ns

tr,tf

Fig.3

-

100

-

100

-

100

ns

CAl ~CA.

tRS2

Fig. 3

-

300

-

300

-

300

ns

Delay Time, Enable negative
transition to Peripheral Data
Valid

Enable--Peripheral Data

tpow

Fig. 4, Fig. 5

-

300

-

300

-

300

ns

Delay Time, Enable positive
transition to CB. negative
transition

Enable .... CB,

tCB2

Fig. 6, Fig. 7

-

200

-

200

-

200

ns

Delay Time, Peripheral Data
Valid to CB. negative
transition

Peripheral Data .... CB,

toc

Fig.5

20

-

20

-

20

-

ns

Delay Time, Enable positive
transition to CB. positive
transition

Enable .... CB,

tRSl

Fig.6

-

200

-

200

-

200

ns

Peripheral Control Output
Pulse Width, CA,/CB.

CA"CB ,

PWCT

550

-

375

-

250

-

ns

Aise and Fall Time for CB I
end CB, input signals

CB,. CB,

tr,tf

Fig.7

-

100

-

100

-

100

ns

Delay Time, CB, active transi·
tion to CB. pos,tive transition

CB, .... CB ,

tRS2

Fig. 7

-

300

-

300

-

300

ns

-

800

ns

400

ns

~u:~d'~a;: Time,

iRaA, iROB

Interrupt Aesponse Time

lm:iA, TR2 Clock.
This signal must be continuous clock pulse.
•

Read/Write (RtW)

This signal is generated by the MPU to control the direction
of data transfers on the Data Bus. A "Low" state on the PIA
line enables the input buffers and data is transferred from the
MPU to the PIA on the E signal if the device has been selected.
A "High" on the R/W line sets up the PIA for a transfer of data
to the bus. The PIA output buffers are enabled when the proper
address and the enable pulse E are present.
• Reset (RES)

The active "Low" RES line is used to reset all register bits in
the PIA to a logical zero "Low". This line can be used as a
power-on reset and as a master reset during system operation.
•

Chip Select (CSo, CS 1 and ~)

These three input signals are used to select the PIA. CS o and
CS I must be "High" and CS 2 must be "Low" for selection of
the device. Data transfers are then performed under the control
of the E and R/W signals. The chip select lines must be stable
for the duration of the E pUlse. The device is deselected when
any of the chip selects are in the inactive state.
• Register Select (RS o and RS 1)

The two register select lines are used to select the various
registers inside the PIA. These two lines are used in conjunction
with internal Control Registers to select a particular register that
is to be written or read.
to
Data Bus

Internal data bus

Interrupt Request UReA and IROB)

The active "Low" Interrupt Request lines (IRQA and IRQB)
act to interrupt the MPU either directly or through interrupt
priority circuitry. These lines are "open drain" (no load device
on the chip). This permits aU interrupt request lines to be tied
together in a wire-OR configuration.
Each IBQ..line has two internal interrupt flag bits that can
cause the IRQ line to go "Low". Each flag bit is associated with
a particular peripheral interrupt line. Also four interrupt enable
bits are provided in the PIA which may be used to inhibit a
particular interrupt from a peripheral device.
Servicing an interrupt by the MPU may be accomplished by a
software routine that, on a prioritized basis, sequentially reads
and tests the two control registers in each PIA for interrupt flag
bits that are set.
.
The interrupt flags are cleared (zeroed) as a result of an MPU
Read Peripheral Data Operation of the corresponding data
register. After being cleared, the interrupt flag bit cannot be
enabled to be set until the PIA is deselected during an E pulse.
The E pulse is used to condition the interrupt contror lines
(CAl, CA 2 , CB I , CB2 ). When these lines are used as interrupt
inputs at least one E pulse must occur from the inactive edge to
the active edge of the interrupt input signal to condition the
edge sense network. If the interrupt flag has been enabled and
the edge sense circuit has been properly conditioned, the
interrupt flag will be set on the next actjve transition of the
interrupt input pin.
•

PIA PERIPHERAL INTERFACE LINES

Port A and Port B 'provide four interrupt control lines and
two sets of 8-bit Bi-directional peripheral data bus for interfacing to input/output divices. Fig. 15 shows the block diagram
of Port A and Port B. The output drivers of Port A and Port B
consist of three-state drivers, allowing them to enter a Highimpedance state when the peripheral data line is used as an
input. Port A and Port B have the same output buffer. But the
circuit configuration is slightly different and this makes the
difference on data flow when MPU reads Port A and Port B
in the case each Port is specified as output. As shown in Fig.
15, the output of the peripheral data A is transferred to internal
data bus when used as output. On the other hand, in the case
of Port B the contents of output register (ORB) is directly
transferred to internal data bus through the multiplexor.
to
Data Bus

Internal data bus

PBx

-0
Buffers

(a) Port A

(b) Port B

Figure 15 Block Diagram of Port A and Port B

342

$

HITACHI

- - - - - - - - - - - - - - - - - - - - - - - - - - H D 6 3 2 1 , H D 6 3 A 2 1 ,HD63B21
• Port A Peripheral Data (PA o - PA,)
Each of the peripheral data lines can be programmed to act
as an input or output. This is accomplished by setting a "1" in
the corresponding Data Direction Register bit for those lines
which are to be outputs. A ''0'' in a bit of the Data Direction
Regist!,r causes the corresponding peripheral data line to act as
an input. During an MPU Read Peripheral Data Operation, the
rlata on peripheral lines programmed to act as inputs appears
directly on the corresponding MPU Data Bus lines.
The data in Output Register A wili appear on the data lines
that are programmed to be outputs. A logical "1" written into
the register will cause a "High" on the corresponding data line
while a "0" results in a "Low". Data in Output Register A may
be read by an MPU "Read Peripheral Data A" operation when
the corresponding lines are programmed as outputs.
• Port B Peripheral Data (PB o -PB,)
Each of the Port B peripheral data bus can be programmed
to act as an input or output like PAo - PA, .
PBo - PB, are in High-impedance condition because they
are three-state outputs just like PAo ..... PBo when the peripheral
buses are used as inputs, when programmed as outputs, MPU
read of Port B make it possible to read the output register
regardless of PBo ..... PB, loads.
• Interrupt Input (CAl and CB I )
Peripheral Input lines CAl and CB I are input only lines that
set the interrupt flags of the control registers. The active
transition for these signals is also programmed by the two
control registers.
• Peripheral Control (CA 2 )
The peripheral control line CA 2 can be programmed to
act as an interrupt input or as a peripheral control output.
The function of this signal is programmed by the Control
Register A. When used as an input, this signal is in High-impedance state
• Peripheral Control (CB2 )
Peripheral Control line CB 2 may also be programmed to act
as an interrupt input or peripheral control output.
This line is programmed by Control Register B.
When used as an input, this signal is in High-impedance.
(NOTE) 1. Pulse width of interrupt inputs CAl, CA2 , CB I and
CB 2 shall be ~reater than a E cycle time. In the case
that "High" time of E signal is not contained in
Interrupt pulse, an interrupt flag may not be set.

Table 1 Intemal Addressing

RS 1

RS o

Control
Register Bit
CRB2
CRA2

0

0

1

0

0
1

0
x

0

x
x
x

0
1
1

0

1

1

x
x
x
1

Location Selected
Peripheral Register AData Direction Register A
Control Register A
Peripheral Register B-

0

Data Direction Register B

x

Control Register B

x = Don't Care
• Peripheral interface register is a generic term containing peripheral
data bus and output register.

• Initialization
A "Low" reset line has the effect of zeroing all PIA registers.
This will set PAo -PA, , PBo.....PB, ,CA2 and CB 2 as inputs, and
all interrupts disabled. The PIA must be configured during the
restart program which follows the reset.
Details of possible configurations of the Data Direction and
Control Register are as follows.
• Data Direction Registers (DORA and DDRB)
The two Data Direction Registers allow the MPU to control
the direction of data through each corresponding peripheral
data line. A Data Direction Register bit set at "0" configures the
corresponding peripheral data line as an input; a "1" results in
an output.
•

Control Registers (CRA and CRB)
The two Control Registers (CRA and CRB) allow the MPU to
control the operation of the four peripheral control lines CAl,
CA2 , CBI and CB 2 • In addition they allow the MPU to enable
the interrupt lines and monitor the status of the interrupt flags.
Bits 0 through 5 of the two registers may be written or read by
the MPU when the proper chip select and register select signals
are applied. Bits 6 and 7 of the two registers are read only and
are modified by external interrupts occurring on control lines
CAl, CA 2 , CBI or CB 2 • The format of the control words is
shown in Table 2.

Table 2 Control Word Format
CRA

CRB

• INTERNAL CONTROLS
There are six locations within the PIA accessible to the MPU
data bus: two Peripheral Registers, two Data Direction Registers, and two Control Registers. Selection of these locations is
controlled by the RS o and RS I inputs together with bit 2 in the
Control Register, as shown in Table 1.

~HITACHI

343

Data Direction Access Control Bit (CRA2 and CRB2)
Bit 2 in each Control register (CRA and CRB) allows
selection of either a Peripheral Interface Register or the Data
Direction Register when the proper register select signals are
applied to RS o and RS I .
Interrupt Flags (CRA6, CRA7, CRB6. and CRB7)
The four interrupt flag bits are set by active transitions of
signals on the four Interrupt and Peripheral Control lines when
those lines are programmed to be inputs. These bits cannot be
set directly from the MPU Data Bus and are reset indirectly by a
Read Peripheral Data Operation on the appropriate section.
Control of CAl and CB I Interrupt Lines (CRAO, CRBO, CRA1.
and CRBU
The two lowest order bits of the control registers are used to
control the interrupt input lines CAl and CB I . Bits CRAO and

CRBO are used to enable the MPU interrupt signals IRQA and
IRQB, respectively. Bits CRAl and CRBI determine the active
transition of the interrupt input signals CAl and CB I (Table 3).
Control of CA2 and CB 2 Peripheral Control Lines (CRA3,
CRA4, CRAS. CRB3, CRB4, and CRBS)
Bits 3, 4 and 5 of the two control registers are used to
control the CA 2 and CB 2 Peripheral Control lines. These bits
determine if the control lines will be an interrupt input or an
output control signal. If bit CRA5 (CRB5) is "0" CA 2 (CB l )
is an interrupt input line similar to CAl (CBl)(Table 4). When
CRA5 (CRBS) is "I", CAl (CB 2 ) becomes an output signal
that may be used to control peripheral data transfers. When in
the output mode, CA 2 and CB 2 have slightly different
characteristics (Table 5 and 6).

Table 3 Control of Interrupt Inputs CAl and CBl
I

MPU Interrupt
Request
I ROA (iFfCiB)

CRAl
(CRB1)

CRAO
(CRBO)

Interrupt Input
CAl (CB l )

I nterrupt Flag
CRA7 (CRB7)

0

0

-I- Active

Set "1" on -I- of CAl
(CB l )

Disabled "High"

0

1

-I- Active

Set "1" on -I- of CAl
(CB l )

Goes "Low" when the inter·
rupt flag bit CRA7 (CRB7)
goes "1"

1

0

t

Active

Set "1" on t of CAl
(C8 1 )

Disabled - I RQ remains
"High"

1

1

t

Active

Set "1" on t of CAl
(C8 1 )

Goes " Low" when the inter·
rupt flag bit CRA7 (CRB7)
goes "1"

(Notes)

I

TRCl remains

1. t indicates positive transition ("Low" to "High")
2. ~ indicates negative transition ("High" to "Low")
3. The Interrupt flag bit CRA 7 is cleared by an MPU Read of the A Peripheral Register
and CRB7 is cleared by an MPU Read of the B Peripheral Register.
4. If CRAOlCRBO) is "0" when an interrupt occurs (Interrupt disabled) and is later brought "1",
l'J!faA (lJiOB) occurs after CRAO (CRBO) is written to a "1".

Table 4 Control of CA 2 and CB 2 as Interrupt Inputs - CRAS (CRBS) is "0"
CRA5
(CRB5)

CRA4
(CRB4)

CRA3
(CRB3)

0

0

0

~

Active

0

0

1

~

Active

Interrupt Input
CA 2 (CB 2 )

"

~quest

IROA (lROB)

Set "1" on ~ of CA 2
(CB 2 )

Disabled - I RQ remains
"High"

Set "1" on -I- of CA2
(CB2)

Goes " low" when the inter·
rupt flag bit CRA6 (CRB6)
goes "1"

0

1

0

t

Active

Set "1" on t of CA 2
(CB 2 )

Disabled - IRO remains
"High"

0

1

1

t Active

Set "1" on t of CA 2
(CB 2 )

Goes "low" when the interrupt flag bit CRA6 (CRB6)
goes "1"

(Notesl

344

MPU Interrupt

Interrupt Flag
CRA6 (CRB6)

1. t indicates positive transition ("Low" to "High")
2. , indicates negative transition ("High" to "Low")
3. The interrupt flag bit CRAS is cleared by an MPU Read of the A Peripheral Register and CRB6 is
cleared by an MPU Read of the B Peripheral Register.
4. If CR~R.!llis "0" when an interrupt occurs (Interrupt disabled) and is later brought
"1", IROA (tROB) occurs after CRA3 (CRB3) is written to a "1".

~HITACHI

Table 5 Control of CB2 as an Output - CRB5 is "'"
CB 2
CRBS
1

CRB4
0

CRB3
0

Cleared
"Low" on the positive transition of
the first E pulse after MPU
Write "B" Data Register operation.

Set
"High" when the interrupt flag bit
CRB7 is set by an active transition
of the CB I signal. (See Figure 16)

1

0

1

"Low" on the positive transition of
the first E pulse after an MPU Write
"B" Data Register operation.

"High" on the positive edge of the
first "E" pulse following an "E"
pulse which occurred while the
part was deselected. (See Figure 16)

1

1

0

"Low"
(The content of CR B3 is output on CB2)

1

1

1

"High"
(The content of CRB3 is output on CB 2 )

Table 6 Control of CA 2 as an Output - CRA5 is "1"
CA 2
CRA3
Cleared
"Low" on negative transition of E
0
after an MPU Read" A" Data Operation.

CRA5
1

CRA4

1

0

1

1

1

0

1

1

1

0

"Low" on negative transition of E
after an MPU Read "A" Data operaticm.

Set
"High" when the interrupt flag bit
CRA7 is set by an active transition
of the CAl signal. (See Figure 16)
"High" on the negative edge of the
first "E" pulse which occurs during
a deselect. (See Figure 16)

"Low"
(The content of CRA3 is output on CA 2 )
"High"
(The content of CRA3 is output on CA 2 )

~HITACHI

345

• PIA OPERATION
•

Initialization
When the external reset input RES goes "Low", all internal
registers are cleared to ''0''. Periperal data port (PAo -PA7,
PBo-PB,) is dermed to be input and control lines (CAl, CA 2 ,
CBI and CB 2 ) are dermed to be the interrupt input lines. PIA is
also initialized by software sequence as follows.

• Program the data direction register access bit of the control
register to "0" to allow to access the dada direction register.

Clear the control register

Load input/output direction data into ACC

Store the contents of ACC into the
data direction register

Load the control data to be written into ACC

• The data of the control line function is set into the accumulator, of which Data Direction Register Access Bit shall be
programmed to "1".
• Transfer the control data from the accumulator into the
control register.

Store the contents of ACC into the control register

tnput/output processing

•

ReadM/rite Operation Not Using Control Lines

Set the data direction register to "00"

Initialize the control register

Load the contents of the peripheral
interface register into the accumulator

CLR
CLR
LDAA
STAA

Clear the DDRA access bit of the control register to "0".
Clear all bits of the dada direction register.
• Set DDRA access bit of the control register to "1" to allow
to access the peripheral interface register.

CRA
•
DORA •

#$04
CRA

LDAA

PIRA

CLR
LDAA
STAA

CRA


Set the data direction register to "FF"

Initialize the control register

Store the data in the accumulator into
output register

346

• Set DDRB access bit of the control register to "0".

~~:B}.

Set all bits of the data direction register to "FF".

STAA

#$04 }.
CRB

Set DDRB access bit of the control register to "1" to allow to
access the peripheral interface register.

LDAA
STAA

DATA} •
PIRB

Write the data into the peripheral interface register.

LDAA

eHITACHI

•

ReadlWr~

()per.ting Using Control Linet

Read/write request from peripherals shall be put into the
control linea as an interrupt signal, and then MPU reads or
writes after detecting interrupt request.


The following cue is that Port A is used and that the rising
ectae of CAl indicates the request for read from peripherals.

elR
elR

Set the date direction regllter to ''00''

eRA •
DORA.

lDAA _$06

Inl11111111 thl controll'lllilte,

ST AA eRA

load the ::~~~s :~~~~~~~I register

'--_ _ _ _ _ _......,._ _ _ _ _ _----'

•

Set the DDRA access bit to "0".
Set all bits of the data direction register to "0".
Program the rising edge of CAl to be active.1I'QA is muked
and DDRA aeeess bit is set to 1.

LOOP LDAA eRA }
BPL LOOP
•

Check whether the read request comes from peripherals
or not.

No

load thl contents of the peripherel
interface regilt.r into the accumulator

lDAA PIRA

• Load the data from the peripheral interface register into the
accumulator. CRA flag is reset after this read operation.

To read the peripheral data, the data is directly transfered to
the data buses Do-D, throuah PAo-PA, or PDo-PB, and
they are not latched in the PIA. If necessary, the data should be
held in the extemallatch until MPU completes reading it.
When initializing the control register, interrupt flag bit
(CRA7, CRA6, CRB7, CRB6) cannot be written from MPU. If
necessary the interrupt flaa must be reset by dummy read of
Periphenl Register A and B.


Write operation

uaina the

interrupt sipUll

IS

as follows. In

this calli. B port is used ud interrupt request is input to CD I
And the IRO flag is set It the rising edge of CD I •

•

~HITACHI

347

Set the data direction register to "FF"

Initialize the control register

Load the contents of the control
register into the accumulator

CLR
LDAA
STAA

CRB

LDAA
STAA

#$06

LOOP LDAA
BPL

#$FF

DDRB
CRB

CRB
LOOP

• Set DDRB access bit to "0"
} • Set all bits ofDDRB to output "I"
}

• Program the rising edge of CD I to be active. IRQB is masked
and DDRB access bit is set to "1".

• Check whether the write request comes from peripherals
or not.

No

Load the contents of the output
register in the accumulator

Store the contents of the accumulator
into the output register

LDAA

PIRB

• Reset the CRB7 flag by the dummy read of the
peripheral interface register.

STAB

PIRB

• Store the data of the accumulator B to the peripheral
interface register.

Interrupt request flag bits (CRA 7, CRA6, CRB7 and CRB6)
cannot be written and they cannot be also reset by write
operation to the peripheral interface register. So dummy read of
peripheral interface register is needed to reset the flags.
To accept the next interrupt, it is essential to reset indirectly
the interrupt flag by dummy read of peripheral interface
register.
Software poling method mentioned above requires MPU to,
continuously monitor the control register to detect the read/
write request from peripherals. So other programs cannot run at
the same time. To avoid this problem. hardware interrupt may
be used. The MPU is interrupted by IRQA or IRQB when the
read/write request is occurred from peripherals and then MPU
analyzes cause of the interrupt request during interrupt processing.
• Handshake Mode
The functions of CRA and CRB are similar but not identical
in the hand-shake modes. Port A is used for read hand-shake
operation and Port B is used for write hand-shake mode.
CAl and CB I are used for interrupt input requests and CA 2
and CB2 are control outputs (answer) in hand-shake mode.
Fig. 16, Fig. 17 and Fig. 18 show the timing of hand-shake
mode.

< Read Hand-shake Mode>
CRAS=" 1", CRA4="0" and CRA3="0"
A peripheral device puts the 8-bit data on the peripheral
data lines after the control output CA 2 goes "Low"
Q) The peripheral requests MPU to read the data by using CA
input.
I

CD

348

Q) CRA 7 flag is set and CA2 becomes "High" (CA2 automatically becomes "High" by the interrupt CAl). This
indicates the peripheral to maintain the current data and
not to transfer the next data.
@ MPU accepts the read request by IRQA hardware interrupt
or CRA read. Then MPU reads the peripheral register A.
~ CA 2 goes "Low" on the following edge of read Enable
pulse. This informs that the peripheral can set the next data
to port A.

CRBS = "1" CRB4 = "0" and CRB3 = "0"
CD A peripheral device requests MPU to write the data by using
CB I input. CB 2 output remains "High" until MPU write
data to the peripheral interface register.
Q) CRB7 flag is set and MPU accepts the write request.
® MPU reads the peripheral interface register to reset CRB7
(dummy read).
@ Then MPU write data to the peripheral interface register.
The data is output to port B through the output register.
~ CB 2 automatically becomes "Low" to tell the peripheral
that new data is on port B.
® The peripheral read the data on Port B peripheral data lines
and set CB I to "Low" to tell MPU that the data on the
peripheral data lines has been taken and that next data can
be written to the peripheral interface register.

CRAS = "I", CRA4 = "0" and CRA3 ="1"
CRBS ="I", CRB4 = "0" and CRB3 = "1"
This mode is shown in Figure 16, Figure 19 and Figure 20.

~HITACHI

Timing

CRAS CRA4 CRA3

:m~
I

CS·RS,·~

°0-°7

I

:

~------~i-----------------

>-______~I____________________

CA,

~"

,,..--

R EAO Request

CRA7
CA,

o

o

o

Ready

Busy

Timing

CRBS CRB4 CRB3
E

RM

CS· RS, • _R_S...
o ____..,j

.,

°0-°7

!

PBo-PB, __________________-<

ID

t:

o

a..

o
o

CB,

o

CB,

PB o -PB 7 data is old.

......-I~--~B~U-Sy----..,

PB o -PB, data is new.
Ready

Figure 16 Timing of Hand-shake Mode and Pulse Mode

$

HITACHI

349

HD6321,HD63A21,HD63B21-------------------------------------------------Goes "High" on
trensition of CAl

II.::F'.'{'

Goes "Low" when data On
"A" side h.. been read by
MPU after filling edgl
~ of enabll.ignal
"
(LOA A PIAA)

(f

Enable lignal (E)

Handshaking with peripheral on 'A' side
Data

PIAA

CA,I. .____________

~

Peripheral

PIA

CA2~--------~r-~

1.lolll~i:llloI1°1 f~
SIYs: Data takan /
(LOA A PIAA)

Peripheral Says:
Here's new data
(Sets CAA7)

Figure 17 Bits 5,4,3 of CRA" 100 (Hand-shake Mode)
Goes " Low" on first
positive edg. of .nabl.
signal aftar the MPU
stores data to the "B"
side. (STA A PIAB)
CB2---.::1~-----~:'}I------r
...._ __

. 10
Goes "High" or trlns.t
n
of CB, (lAOB' fl.g bit sed
\
•

~na~I'

Slgnel
(E)

Handshaking with peripheral on 'B' side
Data

PIAB

CB11~--------------~

PIA

P.riph.rll
CBt~----------~--~

Pariph.I'
Aequ..t for diU!

Figure 18 Bits 5,4,3 of CRB - 100 (Hand-shake Mode)

350

~HITACHI

--------------~------------------------------------HD6321,HD63A21,HD63B21
C~

Normally
"High"

Enable
signal (El

Goes "High" on
the negative
edge of the
next E pulse
after a
"Read a
side data"
Instruction
(LOAl

Goes "Low" after a "Read a side
data" Instruction (LOAl
(Negative transition of El

1 "'_____--'
Pulse mode
Pulse output on 'A' side
Data

111
I

ItI
I

PIRA

Peripheral

PIA
CA 2

7

I

x

CRA
0
1011 1011 11 1x 1x I
Pul" ;";,;"'" a,

.... "

of reading 'A' side
(LOA A PIRA)

~

0 t "R ad" b MPU

aa

e

y

Figure 19 Bits 5,4,3 of CRA = 101 (Pulse Mode)
CB 2 Normally
"High"

Goes "High" on the
next positive E
pulse after A
"writeB
side data"
instruction

Goes "Low" on the positive
transition of the first
E pulse after a "write B
side data" instruction

(STA)

(STA)

Enable
signal
(E)

, " ' -_ _- - '

Pulse mode
Pulse output on 'B' side

I

~ul

Data

Iff

I

PIRB

Peripheral

PIA
7

. . x-_. . " "
CRB

CB 2
0

I x lo111 0 111'l x lxl

Pulse '~'~'a~ as,8 ,ra~ult
of i~~~ng~n~~R~) s,de

at port
for peripheral

Figure 20 Bits 5, 4, 3 of CRB=101 (Pulse Mode)

$

HITACHI

351

• SUMMARY OF CONTROL REGISTERS CRA AND CRB
Control registers CRA and CRB have total control of CAl,
CA 2 , CB I , and CB 2 lines. The status of eight bits of the control
registers may be read into the MPU. However, the MPU can only
write into Bit 0 through Bit 5 (6 bits), since Bit 6 and Bit 7 are
set only by CAl, CA 2 , CBI , or CB 2 •
• Addressing PIAs
Before addressing PIAs, the data direction (DDR) must first
be loaded with the bit pattern that defines how each line is to
function, i.e., as an input or an output. A logic "I" in the data
direction register defines the corresponding line as an output
while a logic "0" defines the corresponding line as an input.
Since the DDR and the peripheral interface resister have the same
address, the control register bit 2 determines which register is
being addressed. If Bit 2 in the control register is a logic "0",
then the DDR is addressed. If Bit 2 in the control register is a
logic" I", the peripheral interface register is addressed. Therefore, it is essential that the DDR be loaded first before setting
Bit 2 of the control register.

Given a PIA with an address of 4004, 4005, 4006, and 4007.
4004 is the address of the A side peripheral interface register.
4005 is the address of the A side control register. 4006 is the
address of the B side peripheral interface register. 4007 is the
address of the B side control register. On the A side, Bits 0, I, 2,
and 3 will be defined as inputs, while Bits 4, 5, 6, and 7 will be
used as outputs. On the B side, all lines will be used as outputs.

1.
2.
3.
4.
5.
6.
7.

PIAIAD =4004
PIA lAC =4005
PIA I BD =4006
PIA I BC =4007

(DDRA, PlRA)
(CRA)
(DDRB, PIRB)
(CRB)

LDA A #%11110000
STA A
PIAIAD
LDA A #% 11111111
STA A
PIAIBD
LDA A #%00000100
STA A
PIAIAC
PIAIBC
STA A

(4 outputs, 4 inputs)
(Loads A DDR)
(All outputs)
(Loads B DDR)
(Sets Bit 2)
(Bit 2 set in A control register)
(Bit 2 set in B control register)

•

Active Low Outputs
When all the outputs of given PIA port are to be active "Low"

(True~ 0.4 volts), the following procedure should be used.

Set Bit 2 in the control register.
Store all Is ($FF) in the peripheral interface register.
Clear Bit 2 in'the control register.
Store all Is ($FF) in the data direction register.
Store control word (Bit 2 = I) in control register.

a)
b)
c)
d)
e)


The B side of PIA I is set up to have all active low outputs.
CBI and CB 2 are set up to allow interrupts in the HANDSHAKE MODE and CB I will respond to positive edges
("Low"-to-"High" transitions). Assume reset conditions. Addresses are set up and equated to the same labels as previous
example.
1.
2.
3.
4.
5.
6.
7.
8.

LDA A #4
STA A PIAIBC
LDA B #$FF
STA B PIAIBD
CLR PIAIBC
STA B PIAIBD
LDA A #$27
STA A PIAIBC

The program shown in the previous section can be accomplished using the Index Register.
1.

3.
4.

LDX
STX
LDX
S1'X

#$ F004
PIAIAD
#$FF04
PIA}BD

$FO~PIA lAD ;$04~PIA 1AC
$FF~PIAIBD;$04~PIAIBC

Using the index register in this example has saved six bytes of
program memory as compared to the program shown in the
previous section.

352

00100111-+-+ control register

•

Interchanging RS o And RS 1
Some system applications may require movement of 16 bits
of data to or from the "outside world" via two PIA ports (A
side + B side). When this is the case it is an advantage to
interconnect RS I and RS o as follows.

RS o to Al (Address Line AI)
RS I to AO (Address Line AO)
This will place the peripheral interface registers and control
registers side by side in the memory map as follows.
Table
PIAIAD
PIAIBD
PIAIAC
PIAIBC

PIA Programming Via The Index Register

2.

All Is in peripheral interface register
Clear Bit 2
All I s in' data direction register

The above procedure is required in order to avoid outputs
going "Low", to the active "Low" TRUE STATE, when all Is
are stored to the data direction register as would be the case if
the normal configuration procedure were followed.

Statement 2 addresses the DDR, since the control register
(Bit 2) has not been loaded. Statements 6 and 7 load the control
registers with Bit 2 set, so addressing PIA I AD or PIA I BD
accesses the peripheral interface register.
•

Set Bit 2 in PIAIBC (control register)

$

Example Address
$4004
$4005
$4006
$4007

(DDRA, PIRA)
(DDRB, PIR B)
(CRA)
(CRB)

The index register or stackpointer may be used to move the
16-bit data in two 8-bit bytes with one instruction. As an
example:
PIAIAD -+-+ IXJ{: PIAIBD -+-+ (XL
LDX PIAIAD
• PIA - After Reset
When the RES (Reset Line) has been held "Low" for a
minimum of one microsecond, all registers in the PIA will be
cleared.
Because of the reset conditions, the PIA has been defined as

HITACHI

follows.
1. All I/O lines to the "outside world" have been defined as
inputs.
2. CAl, CA2 , CBl , and CB2 have been defined as interrupt
input lines that are negative edge sensitive.
3. All the interrupts on the control lines are masked. Setting of
interrupt flag bits will not cause IRQA or IRQB to go "Low".

• SUMMARY OF CA2 ·CB2 PROGRAMMING
Bits 5, 4, and 3 of the control registers are used to program
the operation of CA 2 ·CB2 .

CA 2 -CB 2
Input ~
Mode

• SUMMARY OF CAl ·CB I PROGRAMMING
Bits I and 0 of the respective control registers are used to
program the interrupt input control lines CAl and CBI .

bl

bO

o
o

o

1
1

1

CA 2 -CB 2
Output ~
Mode

W
b5

b4

0
0

0(-)
0(-)
1 (+)
1(+)

o

b3

m
1
1
1

0
0
1

o

(Mask) CA 2 -CB2 Input Mode
(Allow) b4 = Edge (0 = -, 1 = +)
(Mask) b3 = Mask (0 = Mask,
(Allow)
1 = Allow)

1

o
1

o-

Handshake Mode
1 - Pulse Mode

~

} b3 Following Mode

bl = Edge (0= -,1 =+)
bO = Mask (0 = Mask, 1 = Allow)

o
1

Note that this is the same logic as Bits 4 and 3 for CA 2 -CB 2
when CA 2 -CB 2 are prograrruned as inputs.

...~t------ CA,

1------...
1/0 As Follow:
Control Lines:
CAl - Positive Edge, Allow Interrupt
CAl - Pulse Mode
CS I - Negative Edge, Mask Interrupt
CS 2 - Hand Shake Mode

Assume Reset Condition
PIAl AD
PIA1AC
PIA1SD
PIA1SC
PIA Configuration Solutjon
LDAA#$SC
10111100
STA A PIAl AD
1/0 to DDRA
LDA A #$FF
1111 1111
STA A PIA1SD
1/0 to DDRS
LDA A #$2F
0010 1111
STA A PIA1AC
To "A" Control
LDA A #$24
00100100
STA A PIA1SC
To "S" Control

CA 2

.....- - - - -..
:- PA?
...- - - - - - P A .

I-------!'.
..

"A"

PAs

.....- - - - _...
~ PA.
I-----_~ PA,

1------.. .

t.------..

PA 2
PA,

~t------ PAo

-------------

. ""t-----.

CB,

1-_ _ _ _ _-'110.. CB

1------.. .

2

PB?

"S"

.....- - - - -.... PB o

Figure 21 PIA Configuration Problem

~HITACHI

353

HD6321,HD63A21,HD63B21------------------------------------------________
NOTE FOR USE

•

Compatibility with NMOS PIA (HD6821)
Table 7 Comparison CMOS PIA (HD6321) with NMOS PIA (HD6821)
CMOS PIA (HD6321)

Item

NMOS PIA (HD6821)

Pull-up output

Three-state output

+5V

+5V

Port A

Output
Buffer

OORA~

PA o -PA,

t----It-I~CA2

ORA

OORA~

PA o -PA,
CA,

ORA
Internal
Data Bus

t

Read signal

Measure for Input floating

Three-state output

Three-state output

+5V

Port B

OORB~

Output

ORB

+5V

PMOS
. -_ _ _~~PBo-PB7
CB,

DDRB

ORB

Buffer
Internal
Data Bus

Internal
Data Bus

!

Read signal

Measure for Input floating

There is no difference between CMOS PIA and NMOS PIA in pin arrangement_

354

$

NMOS

PB o - PB,

.----_--t~ CB,

HITACHI

HD6840, HD68A40,
HD68B40

PTM (Programmable Timer
The HD6840 is a programmable subsystem component of the
HMCS6800 family designed to provide variable system time
intervals.
The HD6840 has three 16·bit binary counters, three corres·
ponding control registers and a status register. These counters
are under software control and may be used to cause system
interrupts and/or generate output signals. The HD6840 may be
utilized for such tasks as frequency measurements, event count·
ing, interval measuring and similar tasks. The device may be
used for square wave generation, gated delay signals, single
pulses of controlled duration, and pulse width modulation as
well as system interrupts.
•
•
•
•
•

•
•
•
•
•
•
•

FEATURES
Operates from a Single 5 Volts Power Supply
Fully TTL Compatible
Single System Clock Required (E)
Selectable Prescaler on Timer 3 Capable of 4 MHz for the
HD6840, 6 MHz for the HD68A40 and 8 MHz for the
HD68B40
Programmable Interrupts (I RO) Output to MPU
Readable Down Counter Indicates Counts to Go until Time·
Out
Selectable Gating for Frequency or Pulse-Width Comparison
RES Input
Three Asynchronous External Clock and Gate/Trigger
Inputs Internally Synchronized
Three Maskable Outputs
Compatible with MC6840, MC68A40 and MC68840

Module)

HD6840P, HD68A40P, HD68840P

•

PIN ARRANGEMENT

Vss

1

C.

G2

o.

02

eft

C2

Do

G3

D.

03

02

C;.
RES

1\

IRO

':)

HD6840

05

RSo
•

03
D.
06

BLOCK DIAGRAM

07
RS2

E

R/W

CS.

Vee

15 CSo

(Top View)

rt

v..

r

Vee

r

jiB

~HITACHI

355

H D 6 8 4 0 , H D 6 8 A 4 0 , H D 6 8 B 4 0 - - - - - - - - - - - - - - - - - - - - - -_ __
• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Value

,.

Unit

Supply Voltage

Vee

Input Voltage

V ,.
ln

-0.3-+7.0

V

Operating Temperature

Topr

- 20-+ 76

Storage Temperature

T.tII.

- 55-+160

°c
°c

-0.3-+7.0

V

* With respect to Vss (SYSTEM GND)
(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded, it could affect reliability of LSI.

• RECOMMENDED OPERATING CONDITIONS
Item

Symbol

min

typ

max

Vee *
V ,L *

4.75

5.0

5.25

V'H *
Topr

2.2

Supply Voltage
Input Voltage
Operating Temperature
•

-0.3
- 20

25

Unit
V

0.8

V

Vee
75

V

°c

With respect to Vss (SYSTEM GND)

• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vee· 6V ± 5%, Vss· OV, Ta· -20"" +75°C, unless othtnvise noted.)
Item

Svmbol

Test Condition

min

2.4

-

-

V

-

-

0.4

-

-

-

330

650

-

-

12.5

Input Leakage Current

1,1'1

Three-State Input Current
(off-state)

I TS1

Output "High" Voltage

V OH

Output "Low" Voltage

VOL

Output Leakage Current
(off-state)

I LOH

Power Dissipation

Po

I nput Capacitance

Output Capacitance

Cin

Caut

V OH

=2.4V (IRQ)

V ln =OV,
Ta = 2SoC,
f· 1 MHz
Vin =OV.
Ta "'25°C,
f 1 MHz

=

Do"" 0.,
Other Input
IRQ
0 1 .02, OJ

* Ta = 25°C. Vee" 5.0V

356

_HITACHI

f!.A
fJ.A

-0.3

=-200 fJ.A (Other Outputs)
= 1.6 mA (Do ,... 0,)
I LOAD = 3.2 mA (0 1 ,... 0 3 • I R2) line,
an Interrupt Request line, an external Reset line, and three
Register Select lines. These signals, in conjunction with the
HD6800 VMA output, permit the MPU to control the PTM.
VMA should be utilized in conjunction with an MPU address
line into a Chip Select of the PTM, when the HD6800, HD6802
are used.
Bidirectional Data (Do -- 0 7 )
The bidirectional data lines (Do""D7) allow the transfer of
data between the MPU and PTM. The data bus output drivers
are three·state devices which remain in the high.impedance (off)
state except when the MPU performs a PTM read operation
(Read/Write and Enable lines "High" and PTM Chip Selects
activated).
•

•

Chip Select (CS o , CSt)

These two signals are used to activate the Data Bus interface
and allow transfer of data from the PTM. With CS o = "Low"
and CSt = "High", the device is selected and data transfer will
occur.
•

Read/Write (R/W)

This signal is generated by the MPU to control the direction
of data transfer on the Data Bus. With the PTM selected, a
"Low" state on the PTM Rtw line enables the input buffers and

~HITACHI

359

HD6840,HD68A40,HD68B40--------------------------------------------------data is transferred from the MPU to the PTM on the trailing
edge of the Enable (System tP,,) signal. Alternately, (under the
same conditions) R/W ="High" and Enable "High" allows data
in the PTM to be read by the MPU.
• Enable (El
This signal synchronizes data transfer between the MPU and
the PTM. It also performs an equivalent synchronization function on the external clock, reset, and gate inputs of the PTM'
• Interrupt Request (iRQ)
The active "Low" Interrupt Request Signal is normally tied
directly (or through priority interrupt circuitry) to the IRQ
input of the MPU. This is an "open drain" output (no load
device on the chip) which permits other similar interrupt request lines to be tied together in a wire-OR configuration.
The IRQ line is activated if, and only if, the Composite Interrupt Flag (Bit 7 of the Internal Status Register) is asserted. The
conditions under which the IRQ line is activated are discussed in
conjunction with the Status Register.
• Reset (RES)
A "Low" level at this input is clocked into the PTM by the
Enable (System tP2) input. Two Enable pulses are required to
synchronize and process the signal. The PTM then recognizes the
active "Low" or inactive "High" on the third Enable pulse. If
the RES signal is asynchronous, an additional Enable period is
required if setup times are not met. The RES input must be
stable "High"/"Low" for the minimum time stated in the AC
Characteristics.
Recognition of a "Low" level at this input by the PTM
causes the following action to occur:
a. All counter latches are preset to their maximal count

values.
b. All Control Register bits are cleared with the exception of
CR10 (internal reset bit) which is set.
c. All counters are preset to the contents of the latches.
d. All counter outputs are reset and all counter clocks are
disabled.
e. All Status Register bits (interrupt flags) are cleared.
• Register Select Lines (RS o , RS 1 , RS 2 )
These inputs are used in conjunction with the R/W line to
select the internal registers, counters and latches as shown in
Table 1.
It has been previously stated that the PTM is accessed via
MPU Load and Store operations in much the same manner as a
memory device. The instructions available with the HMCS6800
family of MPUs which perform operations directly on memory
should not be used when the PTM is accessed. These instructions actually fetch a byte from memory, perform an operation,
then restore it to the same address location. Since the PTM used
the R/W line as an additional register select input, the modified
data may not be restored to the same register if these instructions are used.
• PTM ASYNCHRONOUS INPUT/OUTPUT SIGNALS
Each of the three timers within the PTM has external clock
and gate inputs as well as a counter output line. The inputs are
high impedance, TTL compatible lines and outputs are capable
of driving two standard TTL loads.
• Clock Inputs (C";, C;, C;)
Input pins ~, C;, and C; will accept asynchronous TTL
voltage level signals to decrement Timers I, 2, and 3, respectively. The "High" and "Low" levels of the external clocks must
each be stable for at least one system clock period plus the sum

Table 1 Register Selection
Register
*
Select Inputs
RS 2

RS 1

RS o

Operations
R/W • "Low"
CR20" "0" Write Control Register #3
CR20 - "1" Write Control Register #1
Write Control Register #2
Write MSB Buffer Register

L

L

L

L
L

L
H

H
L

L

H
L

H
L

L
H

H
L

Write
Write
Write
Write

H

H

Write Timer #3 Letches

H
H
H
H

Timer #1 Letches
MSB Buffer Register
Timer #2 Letches
MSB Buffer Register

R/W. "High"
No Operation
Read Status Register
Read Timer # 1 Counter
Read LSB Buffer Register
Read Timer #2 Counter
Read LSB Buffer Register
Read Timer #3 Counter
Read LSB Buffer Register

• L; "Low"level, H; "High" level

of the setup and hold times for the inputs. The asynchronous
clock rate can vary from dc to the limit imposed by Enable
(System 412) Setup, and Hold time.
The external clock inputs are clocked in by Enable (System
tP2) pulses. Three Enable periods are used to synchronize and
process the external clock. The fourth Enable pulse decrements
the internal counter. This does not affect the input frequency, it
merely creates a delay between a clock input transition and
internal ~cognition of that transition by the PTM. All references to C inputs in this document relate to internal recognition
of the input transition. Note that a clock "High" or "Low" level
which does not meet setup and hold time specifications may
require an additional Enable pulse for recognition. When observing recurring events, a lack of synchronization will result in
360

"jitter" being observed on the output of the PTM when using
asynchronous clocks and gate input signals. There are two types
of jitter. "System jitter" is the result of the input signals being
out of synchronization with the Enable (System tP2), permitting
signals with marginal setup and hold time to be recognized by
either the bit time nearest the input transition or the subsequent
bit time.
"Input jitter" can be as great as the time between input
signal negative going transitions plus the system jitter, if the
first transition is recognized during one system cycle, and not
recognized the next cycle, or vice versa.
External clock input C; represents a special case when Timer

~HITACHI

---------------------------------------------------HD6840,HD68A40,HD68B40
#3 is programmed to utilize its optional';-8 prescaler mode. The
maximum input frequency and allowable duty cycles for this
case are specified under the AC Characteristics. The output of
the .;-8 prescaler is treated in the same manner as the previously
discussed clock inputs. That is, it is clocked into the counter by
Enable pulses, is recognized on the fourth Enable pulse
(provided setup and hold time requirements are met), and must
produce an output pulse at least as wide as the sum of an Enable
period, setup, and hold times.
Enable~~
Input~t--

ReCOg~-- t--

Input

Output

Either
Here

or Here

--1

f--- System

r-T
------------I(f--l- __ J

Bit Time
Jitter

• Gate Inputs (~ ,6;, G;)
Input pins ~, G;, and IT; accept asynchronous TTLcompatible signals which are used as triggers or clock gating
functions to Timers I, 2, and 3, respectively. The gating inputs
are clocked into the PTM by the Enable (System 1/>2) signal in
the same manner as the previously discussed clock inputs. That
is, a Gate transition is recognized by the PTM on the fourth
Enable pulse (provided setup and hold time requirements are
met), and the "High" or "Low" levels of the Gate input must be
stable for at least one system clock period plus the sum of setup
and hold times. All references to G transition in this document
relate to internal recognition of the input transition.
The Gate inputs of all timers directly affected the internal
16-bit counter. The operation of IT; is therefore independent of
the .;-8 prescaler selection.
• Timer Outputs (0\, O2 ,0 3 )
Timer outputs 0 1 , O2 , and 0 3 are capable of driving up to
two TTL loads and produce a defined output waveform for
either Continuous or Single-Shot Timer modes. Output waveform definition is accomplished by selecting either Single 16-bit
or Dual g-bit operating modes. The single 16-bit mode will
produce a square-wave output in the continuous timer mode
and will produce a single pulse in the Single-Shot Timer mode.
The Dual 8-bit mode will produce a variable duty cycle pulse in
both the continuous and single shot Timer modes. "I" bit of
each Control Register (CRX7) is used to enable the corresponding output. If this bit is cleared, the output will remain
"Low" (V 0 d regardless of the operating mode.
If it is cleared while the output is high the output will go low
during the first enable cycle following a write to the Control
Register.
The Continuous and Single-Shot Timer Modes are the only
ones for which output response is defined in this data sheet.
Signals appear at the outputs (unless CRX7 = "0") during Frequency and Pulse Width comparison modes, but the actual
waveform is not predictable in typical applications.
• CONTROL REGISTER

Each timer in the HD6840 has a corresponding write-only
Control Register. Control Register #2 has a unique address
space (RSO="High", RSI ="Low", RS2="Low") and therefore
may be written into at any time. The remaining Control
Registers (#1 and#3) share the Address Space selected by a
"Low" level on all Register Select inputs.
• CR20

The least-significant bit of Control Register #2 (CR20) is
used as an additional addressing bit for Control Registers #1 and

#3. Thus, with all Register selects and R/W inputs at "Low"
level. Control Register #1 will be written into if CR20 is a logic
"I". Under the same conditions, control Register #3 can also be
written into after a RES "Low" condition has occurred, since
all control register bits (except C RlO) are cleared. Therefore,
one may write in the sequence CR3, CR2, CRI.
• CR10

The least-Significant bit of Control Register #1 is used as an
internal Reset bit. When this bit is a logic "0", all timers are
allowed to operate in the modes prescribed by the remaining
bits of the control registers. Writing a "I" into CRIO causes all
counters to be preset with the contents of the corresponding
counter latches, all counter clocks to be disabled, and the timer
outputs and interrupt flags (Status Register) to be reset.
Counter Latches and Control Registers are undisturbed by an
Internal Reset and may be written into regardless of the state
ofCRIO.
• CR30

The least-Significant bit of Control Register #3 is used as a
selector for a .;-8 prescaler which is available with Timer #3
only. The prescaler, if selected, is effectively placed between the
clock input circuitry and the input to Counter #3. It can therefore be used with either the internal clock (Enable) or an external clock source.
•

CRX1 - CRX7 (X=1-3)

The functions depicted in the foregOing discussions are
tabulated in Table 2 for ease of reference.
Control Register Bits CRIO, CR20, and CR30 are unique in
that each selects a different function. The remaining bits (l
through 7) of each Control Register select common functions,
with a particular Control Register affecting only its corresponding timer.
• CRX1

Bit 1 of Control Register #1 (CR!I) selects whether an internal or external clock source is to be used with Timer #1.
Similarly, CR21 selects the clock source for Timer #2, and
CR31 performs this function for Timer #3. The function of
each bit of Control Register "X" can therefore be defined as
shown in the remaining section of Table 2.
•

CRX2

•

CRX3- CRX7

Control Register Bit 2 selects whether the binary information
contained in the Counter Latches (and subsequently loaded into
the counter) is to be treated as a single 16-bit word or two 8-bit
bytes. In the single 16-bit Counter Mode (CRX2=0) the counter
will decrement to zero after N + I enabled (G="Low") clock
periods, where N is defined as the 16-bit number in the Counter
Latches. With CRX2 = I, a similar Time Out will occur after (L
+ l)-(M + 1) enabled clock periods, where Land M, respectively, refer to the LSB and MSB bytes in the Counter Latches.
Control Register Bits 3, 4, and 5 are explained in detail in the
Timer Operating Mode section. Bit 6 is an interrupt mask bit
which will be explained more fully in conjunction with the
Status Register, and bit 7 is used to enable the corresponding
Timer Output. A summary of the control register programming
modes is shown in Table 3..
• STATUS REGISTER/INTERRUPT FLAGS

The HD6840 has an internal Read-Only Status Register
which contains four Interrupt Flags. (The remaining four bits of
the register are not used, and default to "O"s when being read.)
Bits 0, I, and 2 are assigned to Timers 1,2, and 3, respectively,
as individual flag bits, while Bit 7 is a Composite Interrupt Flag.
This flag bit will be asserted if any of the individual flag bits is

~HITACHI

361

HD6840,HD68A40,HD68B40------------------------Table 2 Control Register Bits
CONTROL REGISTER #2

CONTROL REGISTER #1
CR10

I Internal R...t Bit

CR20

"0" All timers allowed to operate
"1" All timers held in preset state
CRX1·

J

Control Registar Address Bit

"0" CR #3 may be written
"1" CR #1 may be written

CONTROL REGISTER #3
CR30

ITimer #3 Clock Control

"0" T3 Clock is not prescaled
"1" T3 Clock is prescaled by .;. a

Timer #X Clock Source

"0"

TX uses external clock source on CX input

"'"

Timer #X Counting Mode Control

"0"

TX configured for normal (16-bit) counting mode

"'"

Timer #X Counter Mode and Interrupt Control (See Table 3)

CRX2

CRX3 CRX4 CRX5
CRX6

TX uses Enable clock

TX configured for dual a·bit counting mode
Timer #X Interrupt Enable

"0"

Interrupt Flag masked on TRQ

"'"

CRX7

Timer #X Counter Output Enable

"0"

TX Output masked on output OX

"'"

TX Output enabled on output OX

Interrupt Flag enabled to

TRQ

• Control Register for Timer 1, 2, or 3, Bit 1.

set while Bit 6 of the corresponding Control Register is at a
logic "I". The conditions for asserting the Composite Interrupt
Flag bit can therefore be expressed as:
INT = II'CRI6 + 12 'CR26 + 13 'CR36
where INT
II
12
13

=Composite Interrupt Flag (Bit 7)
=Timer #1 Interrupt Flag (Bit 0)
=Timer #2 Interrupt Flag (Bit I)
=Timer #3 Interrupt Flag (Bit 2)
STATUS REGISTER

An interrupt flag is cleared by a Timer Reset condition, i.e.,
External RES = "Low" or Internal Reset Bit (CR I 0) = "1". It
will also be cleared by a Read Timer Counter Command pro·
vided that the Status Register has previously been read while the
interrupt flag was set. This condition on the Read Status
Register - Read Timer Counter (RS-RT) sequence is designed
to prevent missing interrupts which might occur after the status
register is read, but prior to reading the Timer Counter.
An Individual Interrupt Flag is also cleared by a Write Timer
Latches (W) command or a Counter Initialization (CI) seq·
uence, provided that W or CI affects the Timer corresponding to
the individual Interrupt Flag.
• COUNTER LATCH INITIALIZATION

Each of the three independent timers consists of a I6-bit
addressable counter and 16 bits of addressable latches. The
counters are preset to the binary numbers stored in the latches.
Counter initialization results in the transfer of the latch con·
tents to the counter. See notes in Table 5 regarding the binary
number N, L, or M placed into the Latches and their relation·
ship to the output waveforms and counter Time·Outs.
Since the PTM data bus is 8-bits wide and the counters are
I6-bits wide, a temporary register (MSB Buffer Register) is
provided. This "write only" register is for the Most Significant

362

Byte of the desired latch data. Three addresses are provided for
the MSB Buffer Register (as indicated in Table I), but they all
lead to the same Buffer. Data from the MSB Buffer will auto·
matically be transferred into the Most Significant Byte of Timer
# X when a Write Timer #X Latches Command is performed. So
it can be seen that the HD6840 has been designed to allow trans·
fer of two bytes of data into the counter latches provided that
the MSB is transferred first.
In many applications, the source of the data will be as
HMCS6800 MPU. It should be noted that the 16-bit store opera·
tions of the HMCS6800 microprocessors (STS and STX etc.)
transfer data in the order required by the PTM. A Store Index
Register Instruction, for example, results in the MSB of the X
register being transferred to the selected address, then the LSB
of the X register being written into the next higher location.
Thus, either the index register or stack pointer may be trans·
fered directly into a selected counter latch with a single instruc·
tion.
A logic "Low" at the RES input also initializes the counter
latches. In this case, all latches will assume a maximum count of
(65,536)10. It is important to note that an Internal Reset (Bit 0
of Control Register I Set) has no effect on the counter latches.
• COUNTER INITIALIZATION

Counter Initialization is defined as the transfer of data from
the latches to the counter with subsequent clearing of the Indi·
vidual Interrupt Flag associated with the counter. Counter
Initialization always occurs when a reset condition (RES =
"Low" or CRIO = "1") is recognized. It can also occur -depending on Timer Mode - with a Write Timer Latches com·
mand or recognition of a negative transition of the Gate input.
Counter recycling or re·initialization occurs when a negative
transition oCthe clock input is recognized after the counter has
reached an all·zero state. In this case, data is transferred from
the Latches to the Counter.
• TIMER OPERATING MODES

The HD6840 has been designed to operate effectively in a
wide variety of applications. This is accomplished by using three
bits of each control register (CRX3, CRX4, and CRX5) to

~HITACHI

H 06840, H 068A40, H 068840
defined different operating modes of the Timers. These modes
are divided into Wave Synthesis and Wave Measurement modes,
and outlined in Table 4.
Table 4 Operating Modes
Control Register
CRX3

CRX4

CRX5

Timer Operating Mode

0

*

0

Continuous

0

*
0

1

Single·Shot

*

Frequency Comparison

1

Wave
Synthesis

Pulse Width Comparison
1
1
*
* Defines Additional Timer Functions.

Wave
Measurement

Either symmetrical or variable duty-cycle waves can be generated in this mode. The other wave synthesis mode, the SingleShot mode, is similar in use to the Continuous operating mode,
however, a single pulse is generated, with a programmable preset
width.
The WAVE MEASUREMENT modes include the Frequency
Comparison and Pulse Width Comparison modes which are used
to measure cyclic and singular pulse wid ths, respectively.
In addition to the four timer modes in Table 4, the remaining
control register bit is used to modify counter initialization and
enabling or interrupt conditions.
• WAVE SYNTHESIS MODES

One of the WAVE SYNTHESIS modes is the Continuous
Operating mode, which is useful for cyclic wave generation.

• Continuous Operating Mode (Table 5)
The continuous mode will synthesize a continuous wave with

Table 3 Control Register Programming
Register 1

Register 2

Register 3

All Timers Operate

Reg #3 May Be Written

T3 Clk.;. 1

All Timers Preset

Reg #1 May Be Written

T3 Clk.;. 8

External Clock

(CX

Input)

Internal Clock (Enable)
Normal (16·Bit) Count Mode
Dual 8·Bit Count Mode

Continuous Operating Mode: Gate 4, or Write to Latches or Reset Causes Counter Initialization

Frequency Comparison Mode: Interrupt if Gate

L...Jt is < Counter Time Out

Continuous Operating Mode: Gate 4, or Reset Causes Counter Initialization

Pulse Width Comparison Mode: Interrupt if Gate

t.---l is < Counter Time Out

Single Shot Mode: Gate 4, or Write to Latches or Reset Causes Counter Initialization

Frequency Comparison Mode: Interrupt If Gate L n i s > Counter Time Out

Single Shot Mode: Gate 4, or Reset Causes Counter Initialization

Pulse Width Comparison Mode: Interrupt If Gate

L--J is> Counter Time Out

Interrupt Flag Masked (fRO)
Interrupt Flag Enabled (fRO)
Timer Output Masked
Timer Output Enable
(NOTE) Reset is Hardware or Software Reset (RES = "Low" or CR10 = "1").

~HITACHI

363

HD6840,HD68A40,HD68B40'- - - - - - - - - - - - - - - - - - - - - - - - a period" proportional to the preset number in the particular
timer latches.
. Any of the timers in the PTM may be programmed to
operate in a continuous mode by writing "O"s into bits 3 and 5
of the corresponding control register. Assuming that the timer
output is enabled (CRX7 = "1 "), either a square wave or a variable duty cycle waveform will be generated at the Timer
Output, OX. The type of output is selected via Control Register
Bit 2.
Either a Timer Reset (CRlO = "1" or External RES =

"Low") condition or internal recognition of a negative transition of the Gate input results in Counter Initialization. A Write
Timer Latches command can be selected as a Counter Initialization signal by clearing CRX4.
The counter is enabled by an absence of a Timer Reset condition and a "Low" level at the Gate input. In the 16-bit mode,
the counter will decrement on the first clock cycle during or
after the counter initialization cr.cle. It continues to decrement
on each clock signal so long as G remains "Low" and no reset
condition exists. A Counter Time Out (the first clock after all

Table 5 Continuous Operating Model
CONTINUOUS MODE
(CRX3 ,. "0", CRX5" "0")
Initialization/Output Waveforms

Control Register
CRX2

CRX4

Counter Initialization

·Timer Output (OX) (CRX7 • "''')
r-(N + II(T)T~N + II(T)--j--(N +

0

0

G~+W+R

0

1

G~+R

1

0

G~+W+R

1

1

G~+R

II

I

I

to

TO

TO

1)(T)1

l-voH
I

n-r--

I-- (L + II(M + II(Tl-r--(L + II(M + II(Tl--l

I
I
to

n

--1

(LI(T)

t-TO

VOL

TO

V
OH
VOL

~ (LI(T)

TO

G~ ,. Negative transition of Gate input.
W = Write Timer Latches Command.
R = Timer Reset (CR10 = "1" or External RES = "Low")
N = 16·Bit Number in Counter Latch.
L = 8·Bit Number in LSB Counter Latch.
M = 8·Bit Number in MSB Counter Latch.
T

= Clock Input Negative Transitions to Counter.

to = Counter Initialization Cycle.
TO= Counter Time Out (All Zero Condition).
• All time intervals shown above assume the Gate (G) and Clock (e) signals are synchronized to Enable
(System 4>2) with the specified setup and hold time requirements.

364

~HITACHI

---------------------------------------------------HD6840,HD68A40,HD68B40
Control Register Bits

Timer #X Counter Output Enable
TX Output masked on output OX
TX Output enabled on output OX

CRX7
a
1

CRX6
a
1

Timer #X Interrupt Enable
Interrupt Flag masked on fFiQ
Interrupt Flag enabled to IRQ

~1;~~RX31
Control Register x 1.7

6 15141 3 1 211 1 a

/
CRX2
0
1

CRla Internal Reset Bit
All timers allowed to operate
All timers held in preset state
X = 1

I

= 1. 2 or 3

~

Timer #x Counting Mode Control
TX configured for normal (16-bit) counting mode
Tx configured for dual 8-bit counting mode

CRxl
a
1

a
1

Lx

Timer #X Counter Mode and Interrupt Control (See Table 3)

-

Timer #x Clock Source
TX uses external clock source on
TX uses Enable clock

ex input

CR20 Control Register Address Bit
a CR#3 may be written
1 CR#l may be written

X=2

~HITACHI

a
1

CR30 Timer #3 Clock Control
T3 Clock is not prescaled
T3 Clock is prescaled by + 8
X =3

365

HD6840,HD68A40,HD68B40-----------------------·Time
Out

Example: Contents of MSB '" 03'" M
Contents of LSB '" 04 '" L

t

....- - - - - - - - - - - M(L + 1) + 1
Algebraic Expression
03(04 + 1) + 1 '"
16 Enables

,,

-----it--- 2.4V

,

0.4V

E
(System!/>2 )
I
I

---1I.pI:...-- 1 + L

1 + L --"""It-- 1 + L
5 Enable
5 Enable
Pulses

I

I

~

5 Enable

I

Pulses

Pulses

I

I
I

I

--- L
:
4 Enable
Pulses

I

1 +L5 Enable
Pulses

p4----

:
I
I

I

-

I
I
I

I•

(M+!)(~~.1I
~

I •• I

I

,:

I

....-.J

.* I

I •• I

-+
.. I

Algebraic Expression
(04 + 1) (03 + 1) '" 20 Enable or
External Clock Pulses

(M + 1) (L + 1) '" Period
M(L + 1) + 1 .. "Low" portion of period
L .. Pulse width

• Preset LSB and MSB to Respective Latches on the negative transition of the E.
•• Preset LSB to LSB Latches and Decrement MSB by one on the negative transition of the E.

Figure 9 Timer Output Waveform Example
(Continuous Dual a·Bit Mode using Internal Enable)

counter bits ="0") results in the Individual Interrupt Flag being
set and re·initialization of the counter.
In the dual 8·bit mode (CRX2= "I") [Refer to the example
in Fig. 9] the MSD decrements once for every full countdown
of the LSD + 1. When the LSD ="0", the MSD is unchanged; on
the next clock pulse the LSD is reset to the count in the LSD
Latches and the MSD is decremented by 1 (one). The output, if
enabled, remains "Low" during and after initialization and will
remain "Low" until the counter MSD is all "O"s. The output
will go "High" at the beginning of the next clock pulse. The
output remains "High" until both the LSD and MSD of the
counter are all "O"s. At the beginning of the next clock pulse
the defmed Time Out (TO) will occur and the output will go
"Low". In the Dual 8-bit mode the period of the output of the
example in Fig. 9 would span 20 clock pulses as opposed to
the 1546 clock pulses using the NormalI6-bit mode.
A special time-out condition exists for the dual 8-bit mode
(CRX 2 = "1") if L = "0". In this case, the counter will revert to
a mode similar to the single 16-bit mode, except Time Out
occurs after M+I clock pulses. The output, if enabled, goes
"Low" during the Counter Initialization cycle and reverses state
at each Time Out. The counter remains cyclical (is re-initialized
at each Time Out) and the Individual Interrupt Flag is set when
Time Out occurs. If M = L = "0", the internal counters do not
change, but the output toggles at a rate of 1/2 the clock frequency.
The discussion of the Continuous Mode has assumed that the
366

application requires an output signal. It should be noted that
the Timer operates in the same manner with the output disabled
(CRX7 = "0"). A Read Timer Counter command is valid regardless of the state of CRX7.
• Single-Shot Timer Mode

This mode is identical to the Continuous Mode with three
exceptions. The first of these is obvious from the name - the
output returns to a "Low" level after the initial Time Out and
remains "Low" until another Counter Initialization cycle
occurs. The waveforms available are shown in Table 6.
As indicated in Table 6, the internal counting mechanism
remains cyclical in the Single-Shot Mode. Each Time Out of the
counter results in the setting of an Individual Interrupt Flag and
re-initialization of the counter.
The second major difference between the Single-Shot and
Continuous modes is that the internal counter enable is not
dependent on the Gate input level remaining in the "Low" state
for the Single-Shot mode.
Another special condition is introduced in the Single-Shot
mode. If L =M ="O"(Dual 8-bit) or N ="0" (Single 16-bit), the
output goes "Low" on the first clock received during or after
Counter Initialization. The output remains "Low" until the
Operating Mode is changed or nonzero data is written into the
Counter Latches. Time Outs continue to occur at the end of
each clock period.
The three differences between Single-Shot and Continuous
Timer Modes can be summarized as attributes of the Single-Shot

~HITACHI

--------------------------HD6840,HD68A40,HD68B40
mode:
1. Output is enabled for only one pulse until it is reinitialized.

2. Counter Enable is independent of Gate.
3. L =M ="0" or N ="0" disables output.
Aside from these differences, the two modes are identical.

Table 6 Single·Shot Operating Modes
Single·Shot Mode
(CRX3 = "0", CRX7 = ",", CRX5 = "'''1
Initialization/Output Waveforms

Control Register
CRX2

0

CRX4

0

Counter Initialization

Timer Output (OXI

I:(N+l)(T)~(N+l)(T)1

-

GI+W+R

r',.,

f--(N)(T)

~

0

1

GI+R

1

0

GI+W+R

1

1

GI+R

I

TO

to

to

11M., IITI~ '" liM.,

---1 (L)(T)
!1TO

TO

lITll
TO

Symbols are as defined in Table 5.

• Wave Measurement Modes
The Wave Measurement Modes are the Frequency (period)
Measurement and Pulse Width Comparison Modes, and are provided for those applications which require more flexibility of
interrupt generation and Counter Initialization. Individual Interrupt Flags are set in these modes as a function of both Counter
Time Out and transitions of the Gate input. Counter Initialization is also affected by Interrupt Flag status.
A timer's output is normally not used in a Wave Measurement mode, but it is defined. If the output is enabled, it will

operate as follows. During the period between reinitialization of
the timer and the first Time Out, the output will be a logical
zero. If the first Time Out is completed (regardless of its
method of generation), the output wi\l go "High". If further
TO's occur, the output will change state at each completion of a
Time-Out.
The counter does operate in either Single 16-bit or Dual 8-bit
modes as programmed by CRX2. Other features of the Wave
Measurement Modes are outlined in Table 7.

Table 7 Wave Measurement Modes
CRX3 = "'"
Condition for Setting Individual Interrupt Flag

CRX4

CRX5

Application

0

0

Frequency Comparison

Interrupt Generated if Gate Input Period (l/FI is less
than Counter Time Out (TO)

0

1

Frequency Comparison

Interrupt Generated if Gate Input Period (l/F) is greater
than Counter Time Out (TOI

1

0

Pulse Width Comparison

Interrupt Generated if Gate Input "Down Time" is less
than Counter Time Out (TOI

1

1

Pulse Width Comparison

Interrupt Generated if Gate Input "Down Time" is greater
than Counter Time Out (TO)

• Frequency Comparison or Period Measurement Mode (CRX3
= "1", CRX4 = "0")
The Frequency Comparison Mode with CRX5 = "1" is
straightforward. If Time Out occurs prior to the first negative
transition of the Gate input after a Counter Initialization cycle,
an Individual Interrupt Flag is set. The counter is disabled, and a
Counter Initialization cycle cannot begin until the interrupt flag
is cleared and a negative transition on G is detected.
If CRX 5 = "0", as shown in Table 7 and Table 8, an interrupt is generated if Gate input returns "Low" prior to a Time
Out. If Counter Time-Out occurs first, the counter is recycled
and continues to decrement. A bit is set within the timer on the
initial Time Out which precludes further individual interrupt
generation until a new Counter Initialization cycle has been
completed. When this internal bit is set, a negative transition of
the Gate input starts a new Counter Initialization cycle. (The

condition of G,j.·Y·TO is satisfied, since a Time Out has occurred and no individual Interrupt has been generated.)
Any of the timers within the PTM may be programmed to
compare the period of a pulse (giving the frequency after calculations) at the Gate input with the time period requested for
Counter Time-Out. A negative transition of the Gate input
enables the counter and starts a Counter Initialization cycle provided that other conditions as noted in Table 8 are satisfied.
The counter decrements on each clock signal recognized during
or after Counter Initialization until an Interrupt is generated, a
Write Timer Latches command is issued, or a Timer Reset condition occurs. It can be seen from Table·8 that an interrupt
condition will be generated if CRX 5 ="0" and the period of the
pulse (single pulse or measured separately repetitive pulses) at
the Gate input is less than the Counter Time Out period. If
CRX 5 ="I", an interrupt is generated if the reverse is true.

~HITACHI

367

HD6840,HD68A40,HD68B40--------------------------------------------------Assume now with CRX 5 ="1" that a Counter Initialization
has occurred and that the Gate input has returned "Low" prior
to Counter Time Out. Since there is no Individual Interrupt
Flag generated, this automatically starts a new Counter Initialization Cycle; The process will continue with frequency comparison being performed on each Gate input cycle until the
mode is changed, or a cycle is determined to be above the
predetermined limit.
• Pulse Width Comparison Mode (CRX3 ="1", CRX4 ="1")
This mode is similar to the Frequency Comparison Mode
except for a positive, rather than negative, transition of the Gate

input terminates the count. With CRXS = "0", an Individual
Interrupt Flag will be generated if the "Low" level pulse applied
to the Gate input is less than the time period required for
Counter Time Out. With CRXS ="1", the interrupt is generated
when the reverse condition is true.
As can be seen in Table 9, a positive transition of the Gate
input disables the counter. With CRX 5 = "0", it is therefore
possible to directly obtain the width of any pulse causing an
interrupt. Similar data for other Time Interval Modes and
conditions can be obtained, if two sections of the PTM are
dedicated to the purpose.

Table 8 Frequency Comparison Mode
CRX3 • ",", CRX4· "0"
Counter Enable
Flip-Flop Set (CEI

Counter Enable
Flip-Flop Reset (CEI

GH'(CE+TOI+R

G~,w·R·T

W+R+I

G~

G~:j"+R

G~;W·1FT

W+R+I

TO Before "IT I

Control Reg
Bit5 (CRX51

Counter
Initialization

0
1

Interrupt Flag
Set (I)
Before TO

I represents the interrupt for a given timer.

Table 9 Pulse Width Comparison Mode
CRX3 = ",", CRX4 = "'"
Counter
Initialization

Counter Enable
Flip-Flop Set (CEI

Counter Enable
Flip-Flop Reset (CE)

0

G~·I+R

GI,W'R'I

W+R+I+G

Gt Before TO

1

G~·T+R

G~·W·R·I

W+R+I+G

TO Before "ITt

G = Level sensitive recognition of Gate input.

368

Interrupt Flag
Set (I)

Control Rag
Bit 5 (CRX51

~HITACHI

HD6340,HD63A40,HD63B40CMOS PTM (Programmable Timer Module)
-PRELIMINARYThe HD6340 is a programmable subsystem component of the
HMCS6800 family designed to provide variable system time
intervals.
The HD6340 has three 16-bit binary counters, three corresponding control registers and a status register. These counters
are under software control and may be used to cause system
interrupts and/or generate output signals. The HD6340 may be
utilized for such tasks as frequency measurements, event counting, interval measuring and similar tasks. The device may be
used for square wave generation, gated delay signals, single
pulses of controlled duration, and pulse width modulation as
well as system interrupts.
Exceeding Low Power dissipation is realized due to adopting
CMOS process.

•

PIN ARRANGEMENT

C1
01
GI
Do
01
O2
03
D.
05
06
07
E
CSt
CSo

Vss
• FEATURES
• Operates from a Single 5 Volts Power Supply
• Fully TTL Compatible
• Single System Clock Required (E)
• Selectable Prescaler on Timer 3 Capable of 4 MHz for the
HD6340, 6 MHz for the HD63A40 and B MHz for the
HD63B40
• Programmable Interrupts (I Ra) Output to MPU
• Readable Down Counter Indicates Counts to Go until Time·
Out
• Selectable Gating for Frequency or Pulse-Width Comparison
• RESlnput
• Three Asynchronous External Clock and Gate/Trigger
Inputs Internally Synchronized
• Three Maskable Outputs
• Low-Power, High-Speed, High-Density CMOS
• Compatible with NMOS PTM (HD6840)

G2
02
C2
G3
03
C3
RES
IRQ
RSo
RSI
RS2
R/W
Vee
(Top View)

~HITACHI

369

·HD6340,HD63A40,HD63840------------------------• BLOCK DIAGRAM

E
R/W RSo

~

Vss

•

1 1

Vee

RES

(System 912)

RSI

03

ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Input Voltage

Vee *
V in *

Maximum Output Current

1101**

Operating Temperature

Topr

Storage Temperature

T stg

S!-Ipply Voltage

Value

Unit

-0.3""+7.0
-0.3""+7.0
10

V
mA

- 20""+75
- 55""+150

°c
°c

V

* With respect to Vss (SYSTEM GND)
* * Maximum output current is the maximum currents which can flow out from one output terminal or 1/0 common terminal. (Do - 0 7 , O. - 0
[NOTE]

•

Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded, it could affect reliability of LSI.

RECOMMENDED OPERATING CONDITIONS
Item
Supply Voltage
Input Voltage
Operating Temperature

Symbol

min

typ

max

Unit

Vee *
V 1L *

4.5
0
2.0
- 20

5.0
25

5.5

V

0.8

V

V 1H *
Topr

* With respect to Vss (SYSTEM GND)

370

~HITACHI

Vee

V

75

°c

3,

IRQ)

--------------------------------------------------HD6340,HD63A40,HD63B40
•

ELECTRICAL CHARACTERISTICS

•

DC CHARACTERISTICS (Vee

=5V ±10%, Vss =OV, Ta = -20 -

+75°C, unless otherwise noted.)
min

typ*

max

Unit

Input "High" Voltage

V 1H

2.0

-

V

Input "Low" Voltage

V 1L

-0.3

-

Vee
0.8

I nput Leakage Current

lin

V in = 0 - Vee (Except Do - 0 7 )

-2.5

-

2.5

/-LA

Three-State Input Current
(off-state)

I TS1

V in = 0.4 - Vee,
Vee =5.5V (Do - 0 7 )

-10

-

10

/-LA

-

Item

Output "High" Voltage

Test Condition

Symbol

V OH

I LOAD - -400/-LA (Do - 0 7 )

4.1

-

I LOAD ~ -10 /-LA (Do - 0 7 )

Vee-O. l
4.1

-

I LOAD

-

Vee- 0 . 1

-

-

0.4

V

Output Leakage Current
(off-state)

-

-

10

/-LA

E= 1.0 MHz

-

-

1.0

E= 1.5 MHz

-

-

1.5

E =2.0 MHz

-

-

2.0

-

-

3.0

-

-

4.0

-

-

6.0

-

-

5.0

-

8.0

-

-

10.0

I LOAD = 1.6 mA (Do - 0 7 )

VOL

I LOAD = 3.2 mA (0 1

I LOH

lee

0 3 , IRO)

V OH = Vee (TRTI)

I

Supply Current

-

• Chip is not selected.
• All counter latches
are preset.
· 0 1 - 0 3 outputs are
masked.
• Input level (Except E)
{V IH min = Vee-0.8V
V 1L max=0.8V

• Chip is not selected.
• Counters are operating. E = 1.0 MHz
• 0 1 - 0 3 operating
E=1.5MHz
with.load.
• Input level (Except E)
{V IH min = Vee-0.8V
E=2.0 MHz
V 1L max= 0.8V
• Data bus in R!W
E= 1.0 MHz
operation.
• Counters are operating. E= 1.5 MHz
· 0 1 - 0 3 operating
E=2.0 MHz
with load.

I nput Capacitance

Cin

V in = OV,
Ta = 25°C,
f = 1 MHz

Output Capacitance

Cout

V in = OV,
Ta = 25°C,
f = 1 MHz

V

-

= -400 /-LA (Other Outputs)

I LOAD ~ -10 /-LA (Other Outputs)
Output "Low" Voltage

V

-

mA

Do - 0 7

-

-

12.5

Other Input

-

7.5

IRO

-

-

0 1 , O2 , 0 3

-

-

10

pF
5.0
pF

* Ta = 25°C. vee" 5.0V

~HITACHI

371

HD6340,HD63A40,HD63B40-------------------------------------------------•

AC CHARACTERISTICS (Vee = 5V ±10%, Vss = OV, Ta = -20 -- +75°C, unless otherwise noted.)

1. MPU READ TIMING
Symbol

Item

HD6340

Test
Condition

typ

max

min

tcycE
PW EH

1000

10000

666

9500

280

Enable "Low" Pulse Width

PWEL

430

9500

280

Enable Rise and Fall Time

tEr, tEf

25

-

Address Set Up Time

tAS

-

-

60

Data Delay Time

tooR

-

Data Hold Time

tHR

20

-

290
100

Address Hold Time

tAH
t ACC

10

-

-

-

-

370

Enable Cycle Time
Enable "High" Pulse Width

Data Access Time

450

Fig. 1

80

HD63840

HD63A40
typ
max

min

-

20

-

10

-

min

10000
9500

500
220

9500

210

max

-

10000

-

ns

150

ns

-

100

ns

-

ns

190

ns

-

25

-

40

180

-

100

20

-

10

-

240

Unit

typ

9500

ns
ns

9500

ns

20

ns

2. MPU WRITE TIMING
Item

Symbol

min

typ

max

min

-

10000

500

-

9500

220

9500

210

25

-

tcycE
PW EH

1000
450

-

10000

Enable "High" Pulse Width

-

9500

666
280

Enable "Low" Pulse Width

PW EL

430

9500

280

Enable Rise and Fall Time

t Er , tEf

-

25

-

Enable Cycle Time

-

HD63A40

HD6340
max
min! typ

Test
Condition

----

Address Set Up Time

tAS

Data Set Up Time
Data Hold Time

tosw
tHW

Address Hold Time

tAH

-

Fig. 2

80

-~-

165
10
10

-

60
80
10
10

I

-

-

HD63840
typ
max

40
60
10
10

Unit

-

10000
9500

ns

9500

ns
ns

-

-

20

ns

ns
ns
ns
ns

3. TIMING OF PTM SIGNAL
Item
Input Rise and Fall Times
Input "Low" Pulse Width

C, G, RES

e,G.1m

Symbol

Test Condition

t"t,

Fig. 3. Fig. 4

PW L

Fig. 3

e,G

Input Pulse Width

C, G, RES
C) (-;.8 Prescaler Mode)
C, G, RES
C) (-;'8 Prescaler Mode)
C) (-;'8 Prescaler Mode)

Output Delay Time

O. - 0)

Input SetuJ1 Time

Input Hold Time

Interrupt Release Time

372

PWH
tsu

HD63A40
max

-

1000'

min

-

HD63840
max
666·

Unit

min

max

-

500'

ns

teveE +tsu +t HO

-

teveE+ tsU+tHO

-

teveE +tsu +tHO

-

ns

( ~~~:Chronous )

teveE +tsu +t HO

-

teveE+tSU+tHO

-

teveE+tsu+tHo

-

ns

Fig. 5
( ~o,::ronous )

200

-

120

-

75

-

200

-

170

-

170

-

( ~~dneChrono!Js )
Fig. 4

Input "High" Pulse Width

HD6340
min

ns

50

50

-

50

-

tHO

Fig. 5
( ~Ondcehronous )

-

50

-

50

-

50

-

ns

PW L •
PWH

( ~~d:chronous )

120

-

80

-

60

-

ns

teo

Fig. 6

-

200

-

200

ns

Fig. 7

-

1200

-

900

-

200

t'R

700

ns

$

HITACHI

--------------------------------------------------HD6340,HD63A40,HD63B40

E

CS.

RS.

R!W

Data Bus

Figure 1

Bus Read Timing
(Read Information from PTM)

Figure 2

Bus Write Timing
(Write Information into PTM)

c. - C;.
G; - G,.

Figure 3

Figure 4

Input Pulse Width "Low"

e-J20V

E

c;-~ .<3;-

Cr..

Input Pulse Width "High"

\---

O. -03

RES

Figure 5

Figure 6 Output Delay

Input Setup and Hold Times

e_

~-t-IR-J---V-C-C---2-.0-V

IRQ ________________- J

Figure 7

I RQ Release Time

_HITACHI

373

HD6340,HD63A40,HD63B40 - - - - - - - - - - - - - - - - - - - - - - - -

Load B

Load A

(0 •• 0 2 .0,)

(Do - D.)

5.0V

5.0V

Test Point

Test Pointo-_._---1.---!4I--.

O-......--tt---i4I---e

Adjust RL
130 pF

10 kn

40 pF

All diodes are
152074 ® or equiv.

so that IOL = 3.2 rnA
then test VOL
All diodes are
1520748 or equiv.

Load C
(IRQ Only)

d1
5.0V

T,n PO;"'

1.3 k<'

2) signal in
the same manner as the previously discussed clock inputs. That
is, a Gate transition is recognized by the PTM on the fourth
Enable pulse (provided setup and hold time requirements are
met), and the "High" or "Low" levels of the Gate input must be
stable for at least one system clock period plus the sum of setup
and hold times. All references to G transition in this document
relate to internal recognition of the input transition.
The Gate inputs of all timers directly affected the internal
16-bit counter. The operation of IT; is therefore independent of
the -;-8 prescaler selection.
• Timer Outputs (0 1 , O 2 ,0 3 )
Timer outputs 0 1 , O2 , and 0 3 are capable of driving up to
two TTL loads and produce a defined output waveform for
either Continuous or Single-Shot Timer modes. Output waveform definition is accomplished by selecting either Single 16-bit
or Dual 8-bit operating modes. The single 16-bit mode will
produce a square-wave output in the continuous timer mode
and will produce a single pulse in the Single-Shot Timer mode.
The Dual 8-bit mode will produce a variable duty cycle pulse in
both the continuous and single shot Timer modes. "I" bit of
each Control Register (CRX7) is used to enable the corresponding output. If this bit is cleared, the output will remain
"Low" (Vo d regardless of the operating mode.
If it is cleared while the output is high the output will go low
during the first enable cycle following a write to the Control
Register.
The Continuous and Single-Shot Timer Modes are the only
ones for which output response is defined in this data sheet.
Signals appear at the outputs (unless CRX7 = "0") during Frequency and Pulse Width comparison modes, but the actual
waveform is not predict~ble in typical applications.
• CONTROL REGISTER

Each timer in the HD6340 has a corresponding write-only
Control Register. Control Register #2 has a unique address
space (RSO="High", RSI="Low", RS2="Low") and therefore
may be written into at any time. The remaining Control
Registers (#1 and#3) share the Address Space selected by a
"Low" level on all Register Select inputs.
• CR20

The least-significant bit of Control Register #2 (CR20) is
used as an additional addressing bit for Control Registers #1 and

376

#3. Thus, with all Register selects and R/W inputs at "Low"
level. Control Register #1 will be written into if CR20 is a logic
"I". Under the same conditions, control Register #3 can also be
written into after a RES "Low" condition has occurred, since
all control register bits (except CRlO) are cleared. Therefore,
one may write in the sequence CR3, CR2, CRI.

The least-significant bit of Control Register #3 is used as a
selector for a -;-8 prescaler which is available with Timer #3
only. The prescaler, if selected, is effectively placed between the
clock input circuitry and the input to Counter #3. It can therefore be used with either the internal clock (Enable) or an external clock source.
• CRX1 - CRX7 (X=1-3)
The functions depicted in the foregoing discussions are
tabulated in Table 2 for ease of reference.
Control Register Bits CRlO, CR20, and CR30 are unique in
that each selects a different function. The remaining bits (I
through 7) of each Control Register select common functions,
with a particular Control Register affecting only its corresponding timer.
• CRX1

Bit I of Control Register #1 (CRII) selects whether an internal or external clock source is to be used with Timer #1.
Similarly, CR21 selects the clock source for Timer #2, and
CR31 performs this function for Timer #3. The function of
each bit of Control Register "X" can therefore be defined as
shown in the remaining section of Table 2.
• CRX2

Control Register Bit 2 selects whether the binary information
contained in the Counter Latches (and subsequently loaded into
the counter) is to be treated as a single 16-bit word or two 8-bit
bytes. In the single 16-bit Counter Mode (CRX2=0) the counter.
will decrement to zero after N + I enabled (G="Low") clock
periods, where N is defined as the 16-bit number in the Counter
Latches. With CRX2 = I, a similar Time Out will occur after (L
+ I)- (M + I) enabled clock periods, where Land M, respectively, refer to the LSB and MSB bytes in the Counter Latches.
• CRX3- CRX7
Control Register Bits 3,4, and 5 are explained ~ detail in the
Timer Operating Mode section. Bit 6 is an interrupt mask bit
which will be explained more fully in conjunction with the
Status Register, and bit 7 is used to enable the corresponding
Timer Output. A summary of the control register programming
modes is shown in Table 3..
• STATUS REGISTER/INTERRUPT FLAGS
The HD6340 has an internal Read-Only Status Register
which contains four Interrupt Flags. (The remaining four bits of
the register are not used, and default to "O"s when being read.)
Bits 0, I, and 2 are assigned to Timers 1,2, and 3, respectively,
as individual flag bits, while Bit 7 is a Composite Interrupt Flag.
This flag bit will be asserted if any of the individual flag bits is

~HITACHI

--------------------------HD6340,HD63A40,HD63B40

Table 2 Control Register Bits
CONTROL REGISTER #1
CR10

I Internal Reset Bit

CONTROL REGISTER #2
CR20

IControl Register Address Bit

CONTROL REGISTER #3
CR30

ITimer #3 Clock Control

"0" All timers allowed to operate

"0" CR #3 may be written

"0" T3 Clock is not prescaled

"1" All timers held in preset state

"1" CR #1 may be written

"1" T3 Clock is prescaled by -;- 8

CRX1*

Timer #X Clock Source

"0"

TX uses external clock source on CX input

"1"

TX uses Enable clock

CRX2

Timer #X Counting Mode Control

"0"

TX configured for normal (16-bitl counting mode

"1"

TX configured for dual 8-bit counting mode

CRX3 CRX4 CRX5
CRX6
"0"
"1"

Timer #X Counter Mode and Interrupt Control (See Table 3)
Timer #X Interrupt Enable
Interrupt Flag masked on IRQ
Interrupt Flag enabled to IRQ

CRX7

Timer #X Counter Output Enable

"0"

TX Output masked on output OX

"1"

TX Output enabled on output OX

* Control Register for Timer 1,2, or 3, Bit 1.

set while Bit 6 of the corresponding Control Register is at a
logic" 1". The conditions for asserting the Composite Interrupt
Flag bit can therefore be expressed as:
INT = 11 ·CRI6 + 12 ·CR26 + 13 ·CR36
where INT
11
12
13

= Composite Interrupt Flag (Bit 7)
= Timer #1 Interrupt Flag (Bit 0)
= Timer #2 Interrupt Flag (Bit 1)
= Timer #3 Interrupt Flag (Bit 2)
STATUS REGISTER

An interrupt flag is cleared by a Timer Reset condition, i.e.,
External RES = "Low" or Internal Reset Bit (CRIO) ="1". It
will also be cleared by a Read Timer Counter Command provided that the Status Register has previously been read while the
interrupt flag was set. This condition on the Read Status
Register - Read Timer Counte-r (RS-RT) sequence is designed
to prevent missing interrupts which might occur after the status
register is read, but prior to reading the Timer Counter.
An Individual Interrupt Flag is also cleared by a Write Timer
Latches (W) command or a Counter Initialization (CI) sequence, provided that W or CI affects the Timer corresponding to
the individual Interrupt Flag.
• COUNTER LATCH INITIALIZATION

Each of the three independent timers consists of a I6-bit
addressable counter and 16 bits of addressable latches. The
counters are preset to the binary numbers stored in the latches.
Counter initialization results in the transfer of the latch contents to the counter. See notes in Table 5 regarding the binary
number N, L, or M placed into the Latches and their relationship to the output waveforms and counter Time-Outs.
Since the PTM· data bus is 8-bits wide and the counters are
I6-bits wide, a temporary register (MSB Buffer Register) is
provided. This "write only" register is for the Most Significant

Byte of the desired latch data. Three addresses are provided for
the MSB Buffer Register (as indicated in Table 1), but they all
lead to the same Buffer. Data from the MSB Buffer will automatically be transferred into the Most Significant Byte of Timer
# X when a Write Timer #X Latches Command is performed. So
it can be seen that the .HD6340 has been designed to allow transfer of two bytes of data into the counter latches provided that
the MSB is transferred first.
In many applications, the source of the data will be as
HMCS6800 MPU. It should be noted that the 16-bit store operations of the HMCS6800 microprocessors (STS and STX etc.)
transfer data in the order required by the PTM. A Store Index
Register Instruction, for example, results in the MSB of the X
register being transferred to the selected address, then the LSB
of the X register being written into the next higher location.
Thus, either the index register or stack pointer may be transfered directly into a selected counter latch with a single instruction.
A logic "Low" at the RES input also initializes the counter
latches. In this case, all latches will assume a maximum count of
(65,536)10. It is important to note that an Internal Reset (Bit 0
of Control Register 1 Set) has no effect on the counter latches.
• COUNTER INITIALIZATION

Counter Initialization is defined as the transfer of data from
the latches to the counter with subsequent clearing of the Individual Interrupt Flag associated with the counter. Counter
Initialization always occurs when a reset condition (RES =
"Low" or CRlO = "1") is recognized. It can also occur depending on Timer Mode - with a Write Timer Latches command or recognition of a negative transition of the Gate input.
Counter recycling or re-initialization occurs when a negative
transition of the clock input is recognized after the counter has
reached an all-zero state. In this case, data is transferred from
the Latches to the Counter.
• TIMER OPERATING MODES

The HD6340 has been designed to operate effectively in a
wide variety of applications. This is accomplished by using three
bits of each control register (CRX3, CRX4, and CRX5) to

~HITACHI

377

HD6340,HD63A40,HD63B40--------------------------------------------------Either symmetrical or variable duty-cycle waves can be generated in this mode. The other wave synthesis mode, the SingleShot mode, is similar in use to the Continuous operating mode,
however, a single pulse is generated, with a programmable preset
width.
The WAVE MEASUREMENT modes include the Frequency
Comparison and Pulse Width Comparison modes which are used
to measure cyclic and singular pulse widths, respectively.
In addition to the four timer modes in Table 4, the remaining
control register bit is used to modify counter initialization and
enabling or interrupt conditions.

defined different operating modes of the Timers. These modes
are divided into Wave Synthesis and Wave Measurement modes,
and outlined in Table 4.
Table 4 Operating Modes
Control Register
CRX3

CRX4

CRX5

Timer Operating Mode

0

0

Continuous

0

*
*

1

Single-Shot

1

0

Frequency Comparison

1

1

*
*

Wave
Synthesis

Pulse Width Comparison

Wave
Measurement

• WAVE SYNTHESIS MODES

* Defines Additional Timer Functions.

•

One of the WAVE SYNTHESIS modes is the Continuous
Operating mode, which is useful for cyclic wave generation.

Continuous Operating Mode (Table 5)

The continuous mode will synthesize a continuous wave with

Table 3 Control Register Programming
Register 1

Register 2

Register 3

+1

All Timers Operate

Reg #3 May Be Written

T3 Clk

All Timers Preset

Reg #1 May Be Written

T3 Clk + 8

External Clock

(CX

Input)

Internal Clock (Enable)
Normal (16-Bit) Count Mode
Dual 8-Bit Count Mode

Continuous Operating Mode: Gate

~

or Write to Latches or Reset Causes Counter Initialization

Frequency Comparison Mode: Interrupt if Gate

Continuous Operating Mode: Gate

~

LJl is < Counter Time Out

or Reset Causes Counter Initialization

Pulse Width Comparison Mode: Interrupt if Gate

Single Shot Mode: Gate

~

L---.J is < Counter Time Out

or Write to Latches or Reset Causes Counter Initialization

Frequency Comparison Mode: Interrupt If Gate U t i s

Single Shot Mode: Gate

~

or Reset Causes Counter Initialization

Pulse Width Comparison Mode: Interrupt If Gate

Interrupt Flag Masked (JAn)
Interrupt Flag Enabled (IRQ)
"0" Timer Output Masked
"1" Timer Output Enable
(NOTE) Reset is Hardware or Software Reset (RES = "Low" or CR10 = "1"1.

378

> Counter Time Out

~HITACHI

L-J is > Counter Time Out

--------------------------------------------------HD6340,HD63A40,HD63840
a period proportional to the preset number in the particular
timer latches.
. Any of the timers in the PTM may be programmed to
operate in a continuous mode by writing "O"s into bits 3 and 5
of the corresponding control register. Assuming that the timer
output is enabled (CRX7 = "1 "), either a square wave or a vari·
able duty cycle waveform will be generated at the Timer
Output, OX. The type of output is selected via Control Register
Bit 2.
Either a Timer Reset (CRI0 = "1" or External RES =

"Low") condition or internal recognition of a negative transition of the Gate input results in Counter Initialization. A Write
Timer Latches command can be selected as a Counter Initialization signal by clearing CRX4.
The counter is enabled by an absence of a Timer Reset condition and a "Low" level at the Gate input. In the 16-bit mode,
the counter will decrement on the first clock cycle during or
after the counter initialization cycle. It continues to decrement
on each clock signal so long as G remains "Low" and no reset
condition exists. A Counter Time Out· (the first clock after all

Table 5 Continuous Operating Modes
CONTINUOUS MODE
(CRX3 = "0", CRX5 = "0")
Control Register
CRX2

CRX4

Initialization/Output Waveforms
Counter Initialization

0

G.j.+W+R

0

1

G.j.+R

1

0

G.j.+W+R

1

1

G.j.+R

0

r-

*Tirner Output (OX) (CRX7 = "1")
1N + 1IITIT!N + ll1TlTIN + 11 IT)

II

I

I

to

TO

TO

n

1

I-VOH

I

n-

I---IL + 111M + 1llTl -t--IL+ 111M + l11Tl--i

I

I
to

---l

ILlIT)

I-TO

VOL

TO

--I

ILlIT)

VOH
VOL

I--

TO

G.j. = Negative transition of Gate input.
W = Write Timer Latches Command.
R = Timer Reset (CR10 = "1" or External RES = "Low")
N = 16·Bit Number in Counter Latch.
L = a·Bit Number in LSB Counter Latch.
M = a·Bit Number in MSB Counter Latch.
T

= Clock Input Negative Transitions to Counter.

to = Counter Initialization Cycle.
TO= Counter Time Out (All Zero Condition).

* All time intervals shown above assume the Gate (3) and Clock
(System

q,2 ) with the specified setup and hold time

(e) signals are synchronized to Enable

requirements.

~HITACHI

379

HD6340,HD63A40,HD63840,-------------------------------------------------Control Register Bits

CRX7

o

Timer #X Counter Output Enable
TX Output masked on output OX
TX Output enabled on output OX

CRX6

o

Timer #X Interrupt Enable
Interrupt Flag masked on IRQ
Interrupt Flag enabled to IRQ

Timer #x Counter Mode and Interrupt Control (See Table 3)

CRX2

o

Timer #x Counting Mode Control
TX configured for normal (16-bit) counting mode
Tx configured for dual 8-bit counting mode

CRX 1

o

o

CR10 Internal Reset Bit
All timers allowed to operate
All timers held in preset state

x =1

380

Timer #x Clock Source
TX uses external clock source on
TX uses Enable clock

ex input

CR20 Control Register Address Bit
o CR#3 may be written
CR#1 may be written
X=2

~HITACHI

o

CR30 Timer #3 Clock Control
T3 Clock is not prescaled
T3 Clock is prescaled by + 8

x =3

--------------------------------------------------HD6340,HD63A40,HD63B40

Example: Contents of MSB
Contents of LSB

= 03 = M
= 04 = L
M(L+1) + 1
Algebraic Expression
03(04 + 1) + 1 =
16 Enables

,,
,,

~----------+-----------~------------~~

(System li>,)

;

~: --1+L~ LL~

I
I
I

1+L - -••-toI....
_ - 1 + L - -..... ....
5 Enable
I
5 Enable
Pulses
Pulses

5 Enable
':
Pulses:
:

4 Enable
Pulses

I

:---1+L-

,,

I

I

*

I

,

1
1

I

1

I

**

'M+J~

,~~

r

~

_

'**'

*1

Algebraic Expression
(04 + 1) (03 + 1 ) = 20 Enable or
External Clock Pulses

(M+1) (L+1)=Period
M(L + 1) + 1 = "Low" portion of period
L = Pulse width

* Preset LSB and MSB to Respective Latches on the negative transition of the E.
** Preset LSB to LSB Latches and Decrement MSB by one on the negative transition of the E.

Figure 9 Timer Output Waveform Example
(Continuous Dual 8-Bit Mode using Internal Enable)

counter bits = "0") results in the Individual Interrupt Flag being
set and re-initialization of the counter.
In the dual 8-bit mode (CRX2= "1") [Refer to the example
in Fig. 9] the MSB decrements once for every full countdown
of the LSB + 1. When the LSB ="0", the MSB is unchanged; on
the next clock pulse the LSB is reset to the count in the LSB
Latches and the MSB is decremented by 1 (one). The output, if
enabled, remains "Low" during and after initialization and will
remain "Low" until the counter MSB is all "O"s. The output
will go "High" at the beginning of the next clock pUlse. The
output remains "High" until both the LSB and MSB of the
counter are all "O"s. At the beginning of the next clock pulse
the defmed Time Out (TO) will occur and the output will go
"Low". In the Dual 8-bit mode the period of the output of the
example in Fig. 9 would span 20 clock pulses as opposed to
the 1546 clock pulses using the Normal 16-bit mode.
A special time-out condition exists for the dual 8-bit mode
(CRX2 = "1") if L ="0". In this case, the counter will revert to
a mode similar to the single 16-bit mode, except Time Out
occurs after M+ 1 clock pulses. The output, if enabled, goes
"Low" during the Counter Initialization cycle and reverses state
at each Time Out. The counter remains cyclical (is re-initialized
at each Time Out) and the Individual Interrupt Flag is set when
Time Out occurs. If M = L = "0", the internal counters do not
change, but the output toggles at a rate of 1/2 the clock frequency.
The discussion of the Continuous Mode has assumed that the

application requires an output signal. It should be noted that
the Timer operates in the same manner with the output disabled
(CRX7 = "0"). A Read Timer Counter command is valid regardless of the state of CRX7.
• Single-Shot Timer Mode
This mode is identical to the Continuous Mode with three
exceptions. The first of these is obvious from the name - the
output returns to a "Low" level after the initial Time Out and
remains "Low" until another Counter Initialization cycle
occurs. The waveforms available are shown in Table 6.
As indicated in Table 6, the internal counting mechanism
remains cyclical in the Single-Shot Mode. Each Time Out of the
counter results in the setting of an Individual Interrupt Flag and
re-initialization of the counter.
The second major difference between the Single-Shot and
Continuous modes is that the internal counter enable is not
dependent on the Gate input level remaining in the "Low" state
for the Single-Shot mode.
Another special condition is introduced in the Single-Shot
mode. If L =M ="O"(Dual 8-bit) or N ="0" (Single 16-bit), the
output goes "Low" on the first clock received during or after
Counter Initialization. The output remains "Low" until the
Operating Mode is changed or nonzero data is written into the
Counter Latches. Time Outs continue to occur at the end of
each clock period.
The three differences between Single-Shot and Continuous
Timer Modes can be summarized as attributes of the Single-Shot

eHITACHI

381

HD6340,HD63A40,HD63B40-------------------------------------------------2. Counter Enable is independent of Gate.
3. L = M = "0" or N = "0" disables output.
Aside from these differences, the two modes are identical.

mode:
1. Output is enabled for only one pulse until it is reinitialized.

Table 6 Single·Shot Operating Modes
Single-Shot Mode
(CRX3 = "0", CRX7 = "1", CRX5 '" "1")
Control Register

Initialization/Output Waveforms

CRX2

CRX4

Counter Initialization

0

0

GI+W+R

0

1

GI+R

1

0

GI+W+R

1

1

GI+R

Ii
r(L'"

Timer Output (OX)

(N+l)(T) ;=:r-(N+l )(T)
i--(N)(T)

~

I

TO

to

1
TO

}(T'~U' }(MH }(T'l

(M"
---j(L)(T)

! lTO

to

TO

Symbols are as defined in Table 5.

• WAVE MEASUREMENT MODES

The Wave Measurement Modes are the Frequency (period)
Measurement and Pulse Width Comparison Modes, and are provided for those applications which require more flexibility of
interrupt generation and Counter Initialization. Individual Interrupt Flags are set in these modes as a function of both Counter
Time Out and transitions of the Gate input. Counter Initialization is also affected by Interrupt Flag status.
A timer's output is normally not used in a Wave Measurement mode, but it is defined. If the output is enabled, it will

operate as follows. During the period between reinitialization of
the timer and the first Time Out, the output will be a logical
zero. If the first Time Out is completed (regardless of its
method of generation), the output will go "High". If further
TO's occur, the output will change state at each completion of a
Time-Out.
The counter does operate in either Single 16-bit or Dual 8-bit
modes as programmed by CRX2. Other features of the Wave
Measurement Modes are outlined in Table 7.

Table 7 Wave Measurement Modes
CRX3 = "1"
CRX4
0

CRX5
0

Application
Frequency Comparison

Condition for Setting Individual Interrupt Flag
Interrupt Generated if Gate Input Period (1/F) is less
than Counter Time Out (TO)

0

1

Frequency Comparison

Interrupt Generated if Gate Input Period (l/F) is greater
than Counter Time Out (TO)

1

0

Pulse Width Comparison

Interrupt Generated if Gate Input "Down Time" is less
than Counter Time Out (TO)

1

1

Pulse Width Comparison

Interrupt Generated if Gate Input "Down Time" is greater
than Counter Time Out (TO)

• Frequency Comparison or Period Measurement Mode (CRX3
= "1", CRX4 ="0")
The Frequency Comparison Mode with CRXS = "1" is
straightforward. If Time Out occurs prior to the first negative
transition of the Gate input after a Counter Initialization cycle,
an Individual Interrupt Flag is set. The counter is disabled, and a
Counter Initialization cycle cannot begin until the interrupt flag
is cleared and a negative transition on G is detected.
If CRXS = "0", as shown in Table 7 and Table 8, an interrupt is generated if Gate input returns "Low" prior to a Time
Out. If Counter Time-Out occurs first, the counter is recycled
and continues to decrement. A bit is set within the timer on the
initial Time Out which precludes further individual interrupt
generation until a new Counter Initialization cycle has been
completed. When this internal bit is set, a negative transition of
the Gate input starts a new Counter Initialization cycle. (The

382

$

condition of G-I--Y-TO is satisfied, since a Time Out has occurred and no individual Interrupt has been generated.)
Any of the timers within the PTM may be programmed to
compare the period of a pulse (giving the frequency after calculations) at the Gate input with the time period requested for
Counter Time-Out. A negative transition of the Gate input
enables the counter and starts a Counter Initialization cycle provided that other conditions as noted in Table 8 are satisfied.
The counter decrements on each clock signal recognized during
or after Counter Initialization until an Interrupt is generated, a
Write Timer Latches command is issued, or a Timer Reset con·
dition occurs. It can be seen from Table 8 that an interrupt
condition will be generated if CRX 5 = "0" and the period of the
pulse (single pulse or measured separately repetitive pulses) at
the Gate input is less than the Counter Time Out period. If
CRX 5 ="1", an interrupt is generated if the reverse is true.

HITACHI

--------------------------------------------------HD6340,HD63A40,HD63B40
Assume now with CRX5 = "1" that a Counter Initialization
has occurred and that the Gate input has returned "Low" prior
to Counter Time Out. Since there is no Individual Interrupt
Flag generated, this automatically starts a new Counter Initialization Cycle. The process will continue with frequency comparison being performed on each Gate input cycle until the
mode is changed, or a cycle is determined to be above the
predetermined limit.
• Pulse Width Comparison Mode (CRX3 = "1", CRX4 ="1")
This mode is similar to the Frequency Comparison Mode
except for a positive, rather than negative, transition of the Gate

input terminates the count. With CRX 5 = "0", an Individual
Interrupt Flag will be generated if the "Low" level pulse applied
to the Gate input is less than the time period required for
Counter Time Out. With CRX 5 = "1", the interrupt is generated
when the reverse condition is true.
As can be seen in Table 9, a positive transition of the Gate
input disables the counter. With CRX 5 = "0", it is therefore
possible to directly obtain the width of any pulse causing an
interrupt. Similar data for other Time Interval Modes and
conditions can be obtained, if two sections of the PTM are
dedicated to the purpose.

Table 8 Frequency Comparison Mode
CRX3
Control Reg
BitS (CRXS)
0
1

Counter
Initialization
G~-I-

= "1",

CRX4

= "0"

Counter Enable
Flip-Flop Set (CE)

Counter Enable
Flip-Flop Reset (CE)

G~,w·R·1

W+R+I

G~

G~:W·R·1

W+R+I

TO Before G~

(CE+TO)+R

G~:j"+R

Interrupt Flag
Set (I)
Before TO

I represents the interrupt for a given timer.

Table 9 Pulse Width Comparison Mode
CRX3

= "1",

CRX4

= "1"

Control Reg
BitS (CRXS)

Counter
Initialization

Counter Enable
Flip-Flop Set (CE)

Counter Enable
Flip-Flop Reset (CE)

0

m'I+R

G~'W'R'I

W+R+I+G

Gt Before TO

1

G~'I+R

G~'W'R'I

W+R+I+G

TO Before Gt

Interrupt Flag
Set (I)

G = Level sensitive recognition of Gate input.

• NOTE FOR USE

Input signal, which is not necessary for user's application,
should be used flxed to "High" or "Low" level. This is applicable to the following signal pins.
C2 , C3 , 'G;, G2 , G3

c.-:

$

HITACHI

383

H06843,H068A43

Foe

(Floppy Disk Controller)

The HD6843 Floppy Disk Controller performs the complex MPU/Floppy interface function. The FDC was designed to
optimize the balance between the "Hardware/Software" in
order to achieve integration of all key functions and maintain
flexibility.
The FOe can interface a wide range of drives with a
minimum of external hardware. Multiple drives can be controlled with the addition of external multiplexing rather than
additional FDC's.
•
•
•
•
•

FEATURES
Format compatible with IBM3740
User Programmable read/write format
Ten powerful macro-commands
Macro End Interrupt allows parallel processing of MPU
and FOC

•

Controls mUltiple Floppies with external multiplexing

•
•

Direct interface with HMCS6800
Programmable seek and settling times enable operation
with a wide range of Floppy drives
Offers both Programmed Controlled I/O (PCIO) and
DMA data transfer mode

•
•
•
•

HD6843P, HD68A43P

(DP-40)

• PIN ARRANGEMENT

Vss

o

TAZ
WDT

FIA

ADT
IAQ
TxAQ
NC
NC

D.
0,

Free-Format read or write
Single S-volt power supply
All registers directly accessible

HD6843

10,
OJ

0,

•

Compatible with MC6843

Os

D.

0,

• BLOCK DIAGRAM

BD

Cs

20
To HD6B44 {
for DMA

Operation

36
_ _ _...:.:...... TxAQ
21
T.AK

AD
elK

E

AiW

Read
Recovery

BD

Aead Data

D.

0,

AD
Data

0,
0,
WDT

HDA

D.
0,

STP

Write Data
Write Gate
Head Direction
15
16

HlD
leT
elK
AES

A,
A.

lB
17
24

AS,

FIA

File Inoperable Reset

WPT

Wrtte Protect

lOX

AS,
TAZ

RS,

CS

Head Load
Low Current Track

Fde Inoperable

E
19

Step

10

AiVi
A.
A,
A,

(Top View)

39

WGT

0,

ADY

40
13

Track Zero
Readv

VSS

As
A.
A,
A,
A,
A ..
A"
Au
A"
A"
A"

384

, TxAK
-,...-----~

~HITACHI

-----------------------------------------------------------HD6843,HD68A43
• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Value
-0.3 - +7.0

V

Input Voltage

Vee *
Vin *

Operating Temperature

Topr

-0.3 - +7.0
0-+75

V
°c

Storage Temperature

TstQ

-55 -

°c

Supply Voltage

Unit

+150

* With respect to Vss (SYSTEM GND)
(NOTE)

Permanent LSI damage may occur if maximum
ratings are exceeded. Normal operation should
be under recommended operating conditiOns. If
these conditions are exceeded, it could affect
reliability of LSI.

• RECOMMENDED OPERATING CONDITIONS
Symbol
Vee *

Item
Supply Voltage

typo

max.

5.0

5.25

V
V

Input "Low" Voltage

V 1H *
V 1L *

-0.3

-

Vee
0.8

Operating Temperature

Topr

0

25

75

Input "High" Voltage

Unit

min.
4.75
2.0

-

V
vC

* With respect to Vss (SYSTEM GND)

• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vcc=5V±5%, Vss=OV, Ta = 0 ~ +7SoC, unless otherwise noted.)
min.

typ.*

max.

Unit

Input "High" Voltage

V 1H

2.0

--

Input "Low" Voltage

V 1L

-0.3

-

Vee
0.8

V

Test Condition

Symbol

Item

V

I nput Leakage Current

lin

Vin=G-5.25V

-

1.0

2.5

J.l.A

Output "High" Voltage

VOH

IOH=-205J.1.A (0 0 -0 7 )
IOH=-100J.l.A (Others)

2.4

-

-

V

VOL

I OL =3.2mA (I RO)
IOL =1.6mA (Others)

-

-

0.4

V
J.l.A
J.l.A

Output "Low" Voltage
Three-state (off-state) Leakage Current

I TS1

V in =0.4-2.4V

-

2.0

10

Output Leakage (off-state)
Current (iRLi)

I LoH

Vo H=2.4V

-

1.0

10

-

600

1000

mW

-

12.5

pF

-

-

10

pF

-

-

10

pF

Power Dissipation
Input Capacitance

Output Capacitance

Po

I

0 0 -0 7

IOther inputs

Cin

V1n=OV, Ta =25°C,
f=l MHz

Cout

V1n=OV, Ta =25°C,
f=l MHz

$

HITACHI

385

HD6843,HD68A43----------------------------------------------------------• AC CHARACTERISTICS (Vee=5V±5%, Vss=OV, Ta = 0 - +75°C, unless otherwise noted.)
Item

Symbol

Test Condition

HD6843

HD68A43

min.

typo

max.

min.

typo

max.

Unit

ClK Cycle Time

tcycC

Figure 1

-

1.0

-

-

1.0

-

ClK Pulse Width, "High"

PWHc

Figure 1

0.4

PW LC

Figure 1

0.35

-

0.4

ClK Pulse Width, "low"

tCr, tCf

Figure 1

-

25

-

-

-

Rise and Fall Time of ClK

-

DCK Cycle Time

Figure 2

2.6

4.0

-

2.6

4.0

DCK Pulse Width, "High"

tcyco
PWHo

Figure 2

1.3

1.95

1.3

1.95

DCK Pulse Width, "low"

PWLo

Figure 2

1.3

1.95

-

1.3

1.95

-

25

-

-

1.0
1.0

-

1.70

0.15

~

-

1.70

-

-

JJ.s

Rise and Fall Time of DCK

tOr, tof

Figure 2

-

ROT Width, "High"

tRoH

Figure 2

1.0

ROT Width, "low"

tRoL

Figure 2

1.0

RDT-DCK Delay Time 1

tRool

Figure 2

0.15

RDT-DCK Delay Time 2

tRoo2
PWlDx

Figure 2
Figure 3

0.15
20.0

tFIRo
PWF1R

Figure 4

-

Figure 4

200

WDT Pulse Width, "High"

PWwo

Figure 7

WDT Cycle Time

Figure 7

STP Pulse Width, "High"

tcycW
PWSTP

Figure 5

-

STP Cycle Time

tCycS *

Figure 5

1

HlD Delay Time (HlD-STP)

tHLoo *

Figure 5

1

HDR Set Up Time

tHoRS

Figure 5

0

HDR Hold Time

tHoRH

Figure 5

32

TxAK Set Up Time

t As3

Figure 10, 11

140

TxAK Hold Time

Figure 10, 11

10

TxRQ Release Time

tAH3
tTR

Figure 10, 11

-

I RQ Release Ti me

tlR

Figure 6

-

lOX Pulse Width, "High"
FI R Delay Time
FI R Pulse Width, "High"

0.35

25

25

JJ.s
JJ.S
JJ.s
ns
JJ.s
JJ.S
JJ.s
ns

-

JJ.S

-

JJ.s

1.70

JJ.s

1.70

JJ.s

-

-

0.15
20.0

-

450

-

-

450

ns

-

200

-

ns

1.0

-

-

JJ.s

2.0

-

32

-

JJ.s

2.0
32

-

1.0

JJ.S

15

1

ms

1

-

15

15

15

ms

-

0

-

-

32

-

-

-

240

ns

-

1.2

JJ.s

450
1.2

140
10

-

ns
JJ.s

ns
ns

* Cycle Ti,me of STP and HLD Delay Time change according to the program .

• BUS TIMING CHARACTERISTICS (Vee =5V±5%, Vss =OV, Ta = 0 - +75°C, unless otherwise noted.)
1

READ OPERATION SEQUENCE
Item

Symbol

Test Condition

HD68A43

HD6843
min.

typo

max.

Unit

min.

typo

-

0.666

-

-

0.23

-

-

JJ.S

max.

tcycE
PW EH

Figure 8, 10

1.0

-

Enable Pulse Width, "High"

Figure 8,10

0.4

Enable Pulse Width, "low"

PWEL

Figure 8, 10

0.4

-

Rise and Fall Time of
Enable Input

tEr, tEf

Figure 8, 10

-

-

25

-

-

25

ns

140

-

-

140

-

ns

-

-

225

-

365

10

-

10

-

-

ns

-

-

400

ns

Enable Cycle Time

Address Set Up Time

tAS

Figure 8, 10

Data Delay Time

tooR

Figure 8, 10

Data Access Time

tACC

Figure 8, 10

Data Hold Time

tH

Figure 8,10

10

Address Hold Time

tAH

Figure 8, 10

10

Bus Direction Delay Time

toBo

Figure 8, 10

-

386

$

HITACHI

400

0.23

JJ.s
JJ.s

200

ns

340

ns

-

ns

------------------------------------------------------------HD6843,HD68A43
2

WRITE OPERATION SEQUENCE
Item

Symbol

Test Condition

HD6843

HD68A43

1-

min.

typo

max.

min.

typo

max.

Unit

Enable Cycle Time

tcy~_E

Figure 9, 11

1.0

0.666

-

-

PWEH

Figure 9, 11

0.4

-

-

Enable Pulse Width, "High"

-

0.23

-

-

ps
ps

Enable Pulse Width, "low"

0.4

-

-

0.23

-

-

ps

25

ns

-

ns

-

ns
ns

PWEL

Figure 9, 11

Rise and Fall Time of
Enable Input

tEr, tEf

Figure 9, 11

-

-

25

-

-

Address Set Up Time

tAS

Figure 9,11

140

-

-

140

-

Data Set Up Time

tDSW

Figure 9, 11

100

-

-

60

-

Data Hold Time

tH

Figure 9, 11

10

-

-

10

Address Hold Time

tAH

Figure 9,11

10

-

-

10

-

Bus Direction Delay Time

tOBO

Figure 9, 11

-

-

-

-

400

400

ns
ns

elK

PWLC--l
tcycC

-I

Figure 1 ClK Waveform

tOr
2.0V

~------PWHOI------~--------------------~---tcycO------------

ROT

Figure 2 DCK, RDT Timing

IDX_![PW'DX~~
Figure 3 IDX Waveform

~HITACHI

387

HD6843,HD68A43---------------------------------------------------------

O.8V

E

2.4V

FIR
......----PWFIR---~~I

Figure 4 FIR Timing

HDR

STP

~----tcycS----t--l

HLD

Figure 5 Seek Operation Sequence

hReading of STRB
E

"~A)

2.4V

Figure 6 IRQ Release Timing

PWWD

r--"JL

I

I
WDT

Figure 7 WDT Waveform

388

~HITACHI

\

\

---------------------------------------------------------HD6843,HD68A43

1------------tcycE - - - - - - - - - - 1

1 - - - - - PWE L - - - - - <..I i""~---PWEH---~

E

CS

RSo-RS,

R/W

0 0 -0 7
(Output)

tOBo-:k:

so

_ _ _ _ _ _ _ _ _ _ _J....J

2.4V

Figure 8 Read Timing

tcycE
PWEH

PWEL

'E

CS

\

-

if.-2.0V
-,

-k-O.8V

-

k- O.8V

O.8V
tEf_
tAH-

I-- tEr

v- -1

~~

tAS

-'vO.8V

-'k- O.8V

):
A/W

\r-

1 .....

0 0 -0 7

-~

O.8V

-

O.8V

V

t---tosw-

O.8V
-JL2.0V

(Input)

(2.0V

J

..,1- O.8V
__ tH

-

2.0V

...,F O.8V

r-tOBD

I

so
Figure 9 Write Timing

eHITACHI

389

HD6843,HD68A43----------------------------------------_________________

tcycE
PWEH

PWEL

E

~

'-

O.8V -k-

O.8V-,
ter-

-'f-2.0V
/'r---tTR-

TxAK
---tp,SJ-

-r

\l+--tAS-

R/W

O.8V

....J

-

-

--

- ' - tEf

r- 2.0V

\

- t.

---- tAH3

tAH_

r- tOOR'"

tACC-

8V

_tH

r-~

D,

2.4V

-\: O.4V

--tOBO-

utI

2.0V
r-O.8V

...J

2.4V

..., ~ O.4V

...,~2.4V

BD

TxRQ

\-r- O.4V
Figure 10 OMA Read Timing

.....- - - - - - - - t c y c e - - - - - - - - -.....

f 4 - - - - PW e L - - - - - I t-----PWEH----.~
2.0V

E

2.0V

O.8V

O.8V

O.8V

TxAK
2.0V

R/W

Do-D,
(Input)

BD

TxRQ
O.4V

Figure 11 DMA Write Timing

390

eHITACHI

---------------------------------------------------------HD6843,HD68A43
LOAD B (IRQ)

LOAD A (Except IRQ)

s.ov

s.ov

RL =2.4kn
Test
Point

o---__- -.....

I---~

Test
Point
R

R
R

= 12kn, C = 130pF

= 24kn, C = 30 pF

(Do -0 7

)

(Outputs except IRQ, 0 0 -0 7 )
All diodes are 152074 @or equivalent.

Figure 12 Load Circuit

vee
ClK

vss
AES

STP
IRQ
INSTRUCTION
DECODER
&
SEQUENCE
CONTROL

TxRQ

TxAK

Do
D,

lCT

D,
D,
D,
0,

FI

0,

IDX

0,

TRZ
WPT
ROY
FIR

HDR
AS.

HLO

RS,

WGT

RS,

A/Vii

VFOC
~----------+ WDT

BD

DCK
ROT

Figure 13 Block Diagram of the FDC

$

HITACHI

391

HD6843,HD68A43--------------------------------------------------------• GENERAL DESCRIPTION
The H06843 FOC consists of four primary sections; the
Register, Serializing, Bus Interface, and Control sections. The
following explanation of these sections can be followed in the
block diagram of Figure 13.
• Register Section
The register section consists of twelve user accessible registers
used for controlling a floppy disk drive. All twelve are
connected by the internal data bus to allow the processor access
to them.
Data Output Register (DOR)
The OOR is an 8-bit register which holds the data to be
written onto the disk. The information is stored here by the bus
interface.
Data Input Register (DIR)
The data words read from the disk are stored in the 8-bit
DIR until read by the bus interface.
Current Track Address Register (CTAR)
CT AR is a 8-bit register containing the address of the track
over which the R/W head is currently positioned.
Command Register (CMR)
The macro commands are written to the 8-bit CMR to begin
their execution.
Interrupt Status Register (lSR)
The four bits of the ISR represent the four conditions that
can cause an interrupt to occur.
Set-Up Register (SUR)
Variable Seek and Settling times are progranuned by the
SUR Four bits are used to program the track to track seek time
and four bits are used to program the head settling time for the
floppy disk drive used with the FDC.
Status Register A (STRA)
The eight bits of STRA are used to indicate the state of the
floppy disk interface.
Sector Address Register (SAR)
SAR contains the five bit sector address associated with the
current data transfer.
Status Register B (STRB)
The eight error flags of STRB are used to signify error
conditions detected by the FDC or generated by the floppy disk
drive.
General Count Register (GCR)
The seven bits of GCR contain the destination track address
when a SEK (seek) macro command is being executed. If a
multi-sector Read or Write macro command is being executed,
GCR contains the number of sectors to be read or written.
CRC Control Register (CCR)
The two bits of the CCR are used to enable the CRC and
shift the CRC for the Free Format Commands.
Logical Track Address Register (L TAR)
The seven bit track address used for read and write

392

operations is stored in the LTAR by the bus interface.
• Serializing Section
The serializing section handles the serial-to-parallel and
parallel-to-serial conversions for Read/Write operations as well
as CRC generation/checking and the generation/detection of the
clock pattern. The Data Output Shift Register (DOSR), Data
Input Shift Register (DISR) , CRC Generator/Checker, and
Clock Shift Register (CSR) comprise the serializing section of
the FOC.
• Bus Interface
The Bus Interface section provides the timing and control
logic that allows the FOC to operate with the 6800 bus, and is
comprised of the Data Buffers. Request ControL and the
Register Select circuitry.
• Control
The internal timing and control signals which sequence the
FOC are derived from the macro instructions by the control
section.
• HD6843 PIN DESCRIPTION
• Power Pins
Vee: +5 volt (±5'/r) power input.
Vss: Power Supply Ground.
• Bus Pins
Reset (RES) Input
The RES input is used to initialize the FOC. When RES
becomes "Low", the state of the outputs is defined by the table
below:

Output
FIR
WGT
HDR
STP

State of Output
"Low"
"Low"
"Low"
"Low"

Output
HLD
TxRQ
IRQ
WDT

State of Output
"Low"
"Low"
"High"
"Low"

Registers which are affected by RES are shown in Table 7.

Interrupt Request (I RQ) Output
The IRQ line is an open drain output that becomes a "Low"
level (logic "0") when the FOC requests an interrupt. Interrupt
requests are controlled by the interrupt enables in CMR
(Command Register) with the function causing the interrupt
shown in ISR (Interrupt Status Register).
Data Bus O~Data Bus 7 (Do ~D7) Bidirectional
The 8 bidirectional data lines allow the transfer of data
between the FDC and the controlling system. The output
buffers are three-state drivers that are enabled when the FOC is
transferring data to the data bus.
Enable (E) Input
The E input to the FOC causes data transfers to occur
between the FOC and the system controlling the FDC

~HITACHI

_________________________________________________________ HD6843,HD68A43
(HMCS6800 MPU, DMA Controller, etc.) E must be a logic "I"
("High" level) for any transfer to be enabled on Do~D7' The E
inpu t is normally connected to system ct>2 .
Chip Select (CS) Input
The CS input in conjunction with the E input, is used to
enable data transfers on Do~D7' E must be a "High" level and
CS must be a "Low" level (logic "0") to enable the transfer.
The TxAK input being a "High" level (logic "I ") performs a
similar function as CS being a "Low" level.
ReadlWrite (R/W) Input
The R/W input is issued by the system controlling the FDC
(HMCS6800 MPU, DMA Controller, etc.) to signify if a read or
write operation is to be performed on the FDC. When TxAK is a
"Low" level. R/W is used in conjunction with CS and RSo~RS2
to determine which register is accessed by the bus as shown in
Table I. When TxAK is a "High" level. R/W is used to select
either the DOR or DIR to the data bus (see description of
TxAK input).
Register Select O~Register Select 2 (RS o ~RS2 ) Input
RSo~RS2' in conjunction with the R/W input, are used
to select one of the user accessible registers in the FDC as
shown in Table I.

causes the FDC to neglect the state of RSo~RS2 causing the
FDC to select the DOR (Data Output Register) or DIR (Data
Input Register) to the data bus (D o-D 7 ) as shown in Table 2.
CS = "0" and TxAK = "I" cannot be permitted at the same
time.
Table 2 Register Selection for DMA Transfers
TxAK

RSo~RS2

CS

R/W

Register
Selected

1

x
x

1

1

DOR

1

0

DIR

1

"1" ..... "High", "0" ..... "Low"

This mode of operation is normally used for DMA (Direct
Memory Access) transfer with the FDC.
When TxAK is a "Low" level the registers are selected by CS,
R/W and RSo~RS2 as shown in Table 1.
•

Bus Direction (BD) Output
The BD output is prOvided to control external bidirectional
buffers on the data bus (Do~D7) as shown in Figure 14. Its
polarity is shown by Table 3.

Transfer Request (TxRQ) Output
TxRQ is used in the DMA mode to request a data transfer
from the DMAC. TxRQ is a "High" level if the FDC is in the
DMA mode (CMR bit 5 is set) when a data transfer request
occurs (STRA bit 0 is set). It is reset to a "Low" level (logic
"0"') when TxAK becomes a "High" level (logic "I "). Data
transfer errors will occur if TxAK does not reset TxRQ before
the next data transfer is required.
Transfer Acknowledge (TxAK) Input
TxAK is generated by the system controlling the FDC
(HMCS6800 MPU, DMA Controller, etc.) and is a response to a
TxRQ issued by the FDC. A "High" level (logic "I ") on TxAK

Table 3 Bus Direction (BD) States
TxAK

CS

BD

1

1

R!W

0
0

1

0

0
R/W

"1" ..... "High", "0" ..... "Low"
(Operation of SO as defined by this chart allows the FOC to function
with the OMA Controller H 06844.)

Table 1 Address Codes for User Accessible Registers
TxAK

CS

RSz

RS,

RS o

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

1

1

1

0

0

1

0

0

0
0
0

0
0

1

0

1

1

1

0

0

1

1

1

"1" ..... "High",

R/W
0
1/0

0

Registers
DOR (Data Output Register)
01 R (Data Input Register)

CTAR (Current Track Address Register)
CM R (Command Register)

1

ISR (I nterrupt Status Register)

0

SUR (Set Up Register)

1

STRA (Status Regiser A)

0

SAR (Sector Address Register)

1

STRB (Status Register B)

0
0
0

GCR (General Count Register)
CCR (CRC Control Register)
LTAR (Logical Track Address Register)

"a" ..... "Low"

~HITACHI

393

HD6843,HD68A43----------------------------------------------------------1-----------1
Din

MPU

I

_-.---_--I'--~

,

......

~~--....,..-J,.-

-~

FOe

Rout,

,
,
,
I
,,

ruE

~--~-----------------,~~

I

I __________ ....l
L
HD268T26
Enable

Figure 14

•

Bus Buffer Control

B is read.

I/O and Control Pins

Head Load (HLO) Output
HLD is used to notify the disk drive that the R/W head
should be loaded (placed in contact with the media). When the
FOC is ready for the head to load, HLO is a "High" level (logic
"I"). A "Low" level (logic "0") HLO indicates the head should
be unloaded.
Step (STP) Output
The STP output, in conjunction with HOR, is used to control
head movement. A 32 J.l.S wide positive (logic "1 ") pulse is
generated on STP, to move the R/W head one track in the
direction defined by the HOR output. The period of the STP
signal is programmable by the SUR (Set-Up Register). The
number of pulses generated on STP is the difference between
the contents of the CTAR (Current Track Address Register),
and the GCR (General Count Register) which contains the track
address to which the head is to be moved.
Head Direction (HOR) Output
The HOR signal controls the direction of head movement. A
"High" level (logic "1") signifies the head should step to the
inside (toward the hub) of the disk. A "Low" level (logic "0")
indicates the direction of head movement should be to the
outside of the disk.
Low Current Track (LCT) Output
The LCT signal is used to control the level of write current
used by the disk drive. LCT is a "Low" level (logic "0") when
the write head is pOSitioned over tracks 0-43. If it is over tracks
44-76, LCT is a "High" level (logic" 1"). LCT is determined
from the contents of the Current Track Address Register
(CTAR).
Write Gate (WGT) Output
When a write operation is being performed, WGT is a logic
"1" ("High" level). For a read operation, WGT is a "Low" level
(logic "0").
File Inoperable Reset (FIR) Output
FIR is an output from the FOC to the floppy disk drive to
reset it from an inoperable status. If the FI input is a "High"
level, a pulse, of which width ahnost equals to E pulse "Low"
width, is generated on the FIR output whenever Status Register

394

File Inoperable (FI) Input
FI is an input to the FOC from the drive. A "High" level
indicates the drive is in an inoperable state. Its current state can
be examined by reading bit 5 of Status Register B (STRB).
Track Zero (TRZ) Input
The TRZ input is ret1ected by bit 3 of STRA (Status Register
A). The TRZ input must be a "High" level (logic" I") when the
R/W head of the drive is positioned over track zero. A logic" I"
on this input inhibits step pulses during a Seek Track Zero
command.
Index (lOX) Input
The index input is received from the t10ppy disk drive and is
used to sense the index hole in the disk media. The lOX signal is
used to initialize the internal FOC tin1ing. The state of the lOX
input is reflected by bit 6 of Status Register A (STRA). A
"High" level (logic" 1") is to indicate the index hole is under the
index sensor. The index input is used to count the number of
disk revolutions while searching for the address ID field (see
description of STRB bit 3).
Ready (ROY) Input
The ready input is received from the disk drive and can be
read as bit 2 of STRA (Status Register A). A "High" level (logic
"1") indicates the drive is ready and allows the FDC to operate
the drive.
Write Protect (WPT) Input
WPT is an input indicating when the media is Write
Protected. A "High" level during an FDC write operation results
in a Write Error (STRB bit 6) but the FOC continues to perform
the write function. The st~te of the WPT input can be read by
examining bit 4 of the Status Register A (STRA).
Clock (CLK) Input
The CLK input is used to generate various timing sequences
internal to the FDC. The head settling, seek time, step pulse
width and write data pulse width, etc., are generated from the
CLK input signal. The CLK is 1 MHz frequency and the duty is

50%.

eHITACHI

-------------------------------------------------------HD6843,HD68A43
• Data Pins
Data Clock (DCK) Input
OCK is used to clock data from the drive into the FOC. It is
generated from the read data received from the drive.
Read Data (ROT) Input
RDT is the serial data input from the drive. The data stream
includes both the clock and data bits.

f = Frequency of the ClK Input. To insure IBM3740
compatibility the clock frequency must be 1 MHz.

Figure 15 WDT Output Timing

Write Data (WDT) Output
WDT is the double frequency modulated data output from
the FOC. The time between clock bits is 4/f where f is the
frequency of the clock input. The pulse width for both clock
and data is I/f (see Figure 15). For the normal clock frequency
of 1 MHz the clock period is 4 p.s, the clock pulse width is 1 p.s
and the data pulse width is 1 p.s. Figure IS shows the
relationship between the WDT output and the frequency of the
CLK inputs.

• FORMAT
The format used by the HD6843 , shown in Figure 18, is
compatible with the soft sector format of the IBM3740.
• MACRO COMMAND SET
The macro command set shown in Table 4 is discussed in the
following paragraphs.

Variable Frequency Oscillator Control (VFOC) Output
VFOC is used as a sync signal during system diagnostics.
Waveforms are shown in Figure 16.
SSR, RCR, MSR Command
lOX

Disk

~~I G~s
__
"High"

I~-I-D-...

_-II.....;;;G.:.,..fl1 G,
~~

G
~_'::'-...J
3

Data

10

G3

WGT

2 bits

SSW, SWD, MSW Command
lOX

D;'k~

G.

t. ~r---ID-'"

"--""";'--1-.:..1 M
1

I

G3

6 bytes--

,

Data

~

",'_ _G..;;,4_...J

~

10

G3

1 bytes

WGT

---+--------------------~~

In FFW Command, VFOC becomes "High" when WGT is at "High" level.
In FFR Command, VFOC remains "High".

Figure 16 Variable Frequency Oscillator Control Waveform
(Relation Between WGT and VFOC)

eHITACHI

395

HD6843,HD68A43------·---------------------------------------------------SSW, SWD and MSW commands (Single Sector Write, Single Sector Write with Delet Data Mark, and Multi-Sector Write)

WGT~

L

o

C

o

C

-l ~(2)
---~

C

WDT ----I---~

(1) 1.0 /.lS (typ)
0.7 ILS (min)
1.31Ls (max)

(2) 0 /.lS (min)
0.3/.ls (max)

Figure 17 Write Data versus Write Gate Timing

Index~_________________________~fJ~--------------------~~
Track
Format

Gap 1
Gap 2
Preamble
(Post-Index)
46 Bytes
32 Bytes
~~~

t------t:j

Index

I

Sector 1

Address Mark
Data = FC
Clock = 07
10
Address

Da~a~kFE
Sector
Format

Sector2

I

Clock = C7

I

I /J I

Sector3

Sector 25

I

I

I

I

Sector 26~

Sector 24

274 Bytes
(Pre-Index Gap)

Gap 3
(10 Gap)
17 Bytes

Gap 4
(Data Gap)
33 Bytes

~--J ''-----.,,--------- I~U
Address 10 Field
6 Bytes
1 - Track Address
2 - 00 Byte
3 - Sector Address
4 - 00 Byte
5- CRC
6-CRC

Data
Address Mark

Data
128 Bytes

Dag~~kB=O~~8

CRC
2 Bytes

Next 10
Address Mark

Figure 18 Soft Sector Format

Table 4 Macro Command Set
CMR Bits

Macro Command

1
2
3

4
5
6
7

8
9
10

396

STZ
SEK
SSR
SSN
RCR
SND
MSN
MSR
FFW
FFR

Seek Track Zero
Seek
Single Sector Read
Single Sector Write
Read CRC
Single Sector Write with Delete Data Mark
Multi Sector Write
Mu Iti Sector Read
Free Format Write
Free Format Read

_HITACHI

Bit 3

Bit 2

Bit 1

BitO

0
0
0
0
0

0
0
1

1
1
0

1

0

1
1
1
1

1
1

0
0

0
0

1
1

0
1
0
1
0
1
1
0
1
0

0
1
1
1
1

Hex
Code
2
3

4
5
6
7
0
C
B

A

---------------------------------------------------------HD6843,HD68A43
•

Seek Track Zero (STZ)

•

The STZ command causes the R/W head to be released from
the surface of the disk (HLD is reset) and positioned above
track 00. The FDC issues step pulses on the STP output until
the TRZ input becomes a "High" level or until 82 pulses have
been sent to the drive. When the TRZ input becomes "High",
the step pulses are inhibited on the STP output but the FDC
remains busy until all 82 have been generated internally.
If the TRZ input remains "Low" (logic "0") after all 82
pulses have been generated, the seek error flag (STRB bit 4) is
set.
After all 82 pulses have been generated, the head is loaded
(HLD becomes a "High"). After the settling time specified in
the SUR has expired, the Seek Command End flag is set (ISR
bit 1), Busy STRA 7 is reset, CT AR and GCR are cleared. The
head remains in contact with the disk. A command such as
RCR (Read CRC) may be issued following a STZ if the head
must be released.
•

Address Search Operation

The flow chart of Figure 20 shows the operation of the
address search operation.

This Operation is Conducted in Parallel
with all Other Operations.

Seek (SEK)

The SEK command is used to position the R/W head over the
track on which a Read/Write operation is to be performed. The
contents of the GCR are taken as the destination address and
the content of the CT AR is the source address; therefore, the
number of pulses (N) on the STP output are given by:
N = I(CTAR) - (GCR)I
HDR is a "High" for (GCR) > (CTAR) otherwise it is a "Low".
When a SEK command is issued, Busy is set, the head is
raised from the disk, HDR is set as described above, and N
number of pulses appear on the STP output. After the last step
pulse is used, the head is placed in contact with the disk. Once
the head settling time has expired, the Seek Command End flag
(lSR bit I) is set, Busy is reset, and the contents of the GCR are
transferred to the CT AR.
•

SINGLE SECTOR READ/WRITE COMMANDS

The single sector Read/Write commands (SSR, RCR, SSW,
and SWD) are used to Read/Write data from a single 128 byte
sector on the disk. As shown in Figure 19 these types of
instructions can be divided into two sections. The first section,
which is common to all instructions, is the address search
operation, while the second section is unique to the requirements of each instruction.

Figure 20 Operational Flow of the Address Search Sequence

•

Single Sector Read (SSR)

The single sector read command follows the address search
procedure as defined in the previous flowchart. If the search is
successful, status sense request is set and the operation
continues as described by the flowchart of Figure 21 .
•

Figure 19 Basic Single Sector Command Flow Chart

$

Read CRC (RCR)

The RCR command is used to verify that correct data was
written on a disk. The operation is the same as for the SSR

HITACHI

397

HD6843,HD68A43-------------------------------------------------------

Set Data Address
Mark Undetected
(STRB Bit 2)
Set RWCE
USR Bit 0)

Set CRC Error
(STRB Bit 1)
Set RWCE
(ISR Bit(l)

Figure 21 Operational Flow of the SSR Command

398

_HITACHI

-----------------------------------------------------------HD6843,HD68A43
command with the exception that the data transfer request
(STRA bit 0) is not set. The Status Sense Request interrupt can
be disabled by using the DMA flag of CMR.
•

•

Single Sector Write with Delete Data Mark (SWD)

The operation flow of SWD is exactly like that of SSW. For
SWD, the data pattern of the Data Address Mark becomes F8
instead of FB. The clock pattern remains C7.

Single Sector Write (SSW)

Single sector write is used to write 128 bytes of data on the
disk. After the command is issued, the address search is
performed. The remainder of the instruction's operation is
shown in Figure 22.

•

Multi-Sector Commands (MSR/MSW)

MSR is used for sequential reading of one or more sectors.
If S sectors are to be read, S - 1 must be written into the GCR
before the command is issued.

Figure 22 Operational Flow of the SSW Command

eHITACHI

399

HD6843,HD68A43--------------------------------------------------------The basic operation for the MSR and MSW is the same as
that for the SSR and SSW respectively. The basic operation
begins with an address search operation, which is followed by a
single sector read or write operation. This completes the
operation on the first sector. The SAR is incremented, the GCR
is decremented, and if no overflow is detected from the GCR
(i.e., GCR become negative) the sequence is repeated until S
number of sectors are read or written.
The completion of an MSR or MSW is like that of an SSR or
SSW command. First RWCE is set and Busy is reset, after the
settling time has expired, the head is released.
If a delete data mark is detected during an MSR command,
STRA bit 1 (Delete Data Mark Detected) remains set throughout the commands operation.
When a multi-sector instruction is issued, the sum of the SAR
and GCR must be less than 27. If SAR + GCR > 26, an address
error (STRB bit 3 set) will occur after the contents of SAR
becomes greater than 26.
• Free Format Write (FFW)
The FFW has two modes of operation which are selected by
FWF (Free Format Write Flag) which is dat,a bit 4 of the CMR.
When FWF = "0", the data bits of the DOR are written directly to the disk without first writing the preamble, address
mark, etc. The contents of the DOR are FM modulated with a
clock pattern of all ones.
If FWF ="1" the odd bits of the DOR are used as clock bits
and even bits are used for data bits. In this mode, the DOSR
clock is twice a normal write operation and one byte of DOR is
one nibble (four bits of data) on the disk.
The two modes of the FFW command allow formatting a
disk with either the IBM3470 format or a user defined format.
After the FFW command is loaded into the CMR, WGT
becomes a "High" level, the contents of DOR are transferred to
the DOSR, data transfer request (STRA bit 0) is set, and the
serial bit pattern is shifted out on the WDT line. Therefore, DOR
must be loaded before the FFW command is issued. Data from
the DOR is continually transferred to the DOSR and shifted out
on WDT until the CMR has been written with an all zero
pattern. When CMR becomes zero, WGT becomes a "Low"
level, but RWCE is not set and the R/W head is left in contact
with the disk.
•

Free Format Read (FFR)
FFR is used to hIput all data (including Address marks) from
a disk. Once the FFR command is set into the CMR, the head is
loaded and after the settli.ng time has expired the serial data
from the FDC is brought into the DISR. After 8 bits have
accumulated, it is transferred to the DIR and Data Transfer
Request (STRA bit 0) is set.
This operation continues until a zero pattern is stored in the
CMR, terminating the FFR command. As in the case of the
FFW command, RWCE is not set and the head remains in
contact with the disk.
The first data that enters the DISR is not necessarily the first
bit of a data word since the head may be lowered at any place
on the disk. To prevent the FDC from remaining unsynchronized to the data, the FFR command will synchronize
to an ID address mark (FE) or a Data Address mark (FB or F8)
or an Index Address Mark (FC).

400

• REGISTER DEFINITIONS

When one of the four write macro commands (SSW, SWD,
MSW, and FFW) is executed, the information contained in the
DOR is loaded into the DOSR, and is shifted out on the WDT
line using a double frequency (FM) format.
• Data Input Register (DIR); Hex address 0, read only

One of the three read macro commands (SSR, MSR, FFR)
executed, will cause the information on the ROT input to be
clocked into the DISR. When 8 clock pulses have occurred, the
8 bits of information in the DISR are transferred to the DIR
where it can be read by the bus interface.
• Current Track Address (CTAR); Hex address 1, read/write
Bit 7

I Bit 6 I Bit 5 I Bit 4 I Bit 31 Bit 2 TBit 11 Bit 0
Track Address of Current Head position

The address of the track over which the R/W head is
currently positioned is contained in the CT AR, At the end of a
SEK command, the contents of the GCR are transferred to the
CT AR. CT AR is cleared at the completion of a STZ command.
CTAR is a read/write register so that the head position can be
updated when several drives are connected to one FDC. Bit 7 is
read as a "0".
• Command Register (CMR); Hex address 2, write only
Bit7

Bit6

Function
Interrupt
Mask

ISR3
Interrupt
Mask

Bit 5

Bit 4

DMA
Flag

FWF

--+--

.''''1 .o. 2'1 ••" ·r..,0'1
Macro Command

*Bit 0 - 3 are cleared by RES.

The commands that control the FDC are loaded into the
lower four bits of the CMR. Information that controls the data
transfer 'mode and interrupt conditions are loaded into bits four
through seven.
Bit o-Bit 3: Macro Command
The Macro Command to be executed by the FDC is written
to bits 0~3,
Bit 4: Free Format Write Flag (FWF)
If a Free Format Write command is issued, the state of bit 4
of the CMR determines what clock source will be used. The
FWF is defined in the FFW (Free Format Write) command
explanation.
Bit 5: DMA Flag
If bit 5 is a "1" the FDC is in the DMA mode. Bit 5 being a
"1" inhibits setting of Status Sense Request (lSR bit 2) thereby
preventing its associated interrupt. A logic" 1" DMA flag also
enables the TxRQ output allowing it to request DMA transfers
when the Data Transfer Request flag (STRA bit 0) is set.
A logic "0" DMA flag indicates the program controlled I/O
(PC I/O) mode.

_HITACHI

------------------------------------------------------------HD6843,HD68A43

..

,
Command End

Command Set
____ ,

GCR. CTAR; clear

I

HLO

f-------'

----,

HOR

~-~~-time

LCT

g

-.11:-'

ee,k tIme

STP

-

r:

Inn

2'------1..J - 3 L - -

,

ri,.~
time I
~eeK

-----------t----

~---u':-,---""""'------n.L..~'--H--~8~2

H:in'2~'

mIn, On,

I

TRZ

"'"

ROY

STRA7
(Busy)

ISR'

(Seek Command End)

* STP output is masked when TRZ becomes "High", But if TRZ falls to "Low" again before 82 pulse outputs are all provided
STP output become available again from that time point.

** When ROY is "Low" with Command Set, the execution is postponed until ROY becomes "High".

Figure 23 Timing Sequence of STZ Command

.....

GCR Set
Command Set

..

CTAR Determined

\

HLO

HOR

I

-----------'x.r--------------!

I-------+-"-----------t------

::~~g>;~O:.a;~r~h~ ~~~ hub

,......-----------1 I - - - - - - - + - + - - - - - - - - - - t - - - - - - " H i g h " GCR> 44

LCT

'-~--:'--------___i I - - - - - - - + - + - - - - : - : - - - - - - - t - - - - - - " L o w " GCR<. 43

+~,Seek_1

~~·n

time

h

STP

J 'L---....J
--t----+---J

ROY

"'"

n

n

_

r

~mln32~s

' - - 13L - -!,}-----1 n' - - - - - - - - - - - t - - - - - -

2

(Difference between
GCR and CTAR)

:~~~Co;m~-~=;====:t-----------~I------------------~
mand End)

Time for calculation

of relative address
Max lms.

* When ROY is "Low" with Command Set, the execution is postponed until ROY becomes "High",

Figure 24 Timing Sequence of SEK Command

~HITACHI

401

HD6843,HD68A43----------------------___________________________________
LTARSAR
Sal SOl

..

Slarl Addross Search

W--

Next Command Set

Command Sel

HLO

::::J

comm!'nd End
(Address Errod
Unless a new command

-Settling_

~:tlme

is issued during the
settling time after
Command End, HLD
becomes .. Low".

~.----£~------------

lOX

,----I--------------------L

1'\.
I'\.

STRA7
(Busv)

Unless the address is detected

~~~;ea:~:r ~~~r~~~I~e~~~~~e

results in Command End with
Address Error.

ISRO=1
STAB3 =1

ISRO
(RIW Command End)

ROT V.-.,;;Iid:..-_ _ _ _....J

\

• If HLO has already been "High" when the command is set, the FOC starts the address search immediately.

When ROY is "Low" with Command Set, the FOC waits for the execution until ROY becomes "High".

Figure 25 Timing Sequence of SSR, SSW, RCR, 5WD, MSR, MSW Command
(Relation with HLD and lOX)

I--------IO-------!I
Oatafrom
Iho disketto

FF

00

00

00

00

00

00

lOAM

Track

00

Sector

00

CAC

CAC I FF

FF

Check Timing

-----+--+--+---+--+--+-_+---4--I--+--+--_-~--+--+--+----

of Data

1\

~~~ion (f) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....J

---------------------'~~/~

'~j;,- - -

Reset

- - - - - -

\~ ~ - -

Reset

~:~

@

Sector
Equal

@

!,~"CRC

@ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-=-'..J

- - - - - - - - - -

,

\ . _________,L _____________

Reset

" '",-I --,

-----------------------------------~

\,------------Reset

Sector

Track
Not Equal

Not Equal

I

I

IA/W Command Endl
ISAO
ISR2

...!.:(S~en~s:..eA::e:!!q!!!ue:!!sl!.)_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..J

ISA2 set by address
detection

@; In the case of Track Not Equal, ® is not set and -if CRC equals to the one calculated by FOC, STRA5 is set.
@; In the case of Sector Not Equal, @ is not set and CD & ® are reset to search the next I DAM.
@; In the case of CRC Error, @ is not set and CD,® & @are reset. OSRQ: Set, STRB1: Set, STRB3: Set)
When CD, ®, @, & @ are all set, ISR2 is Set. These four signals are reset with Command End.
When @ is "1 ", go to the data transfer routme.

Figure 26 Internal Timing Sequence of Address Search Routine

402

_HITACHI

Compare with

LTAR

Reset
Compare with

SAA

-----------------------------------------------------------HD6843,HD68A43
L

-I

Data from
the diskette

:j

FF

FF

FF

00

~-GAP--

--.,

10CRC
"0"

I

Data

~AM
or
DAM

3rd
Data

2nd
Data

lst
Data

127th 128th
Data Data

-----

,

--------------

~----------Command End with DAM' Undetected

U

FF

Roset with Command End

n,

m ~w~
~

STRAO
Read
DIR

~

~

Ii

~

01

It

In the coso ofRCR,
no signal rei ated to
STRAOis ge nerated

I----

I

(0ata Transfer Errod

32 bytes

Transfer Error

I

:r-----------

I

:

i

V-!--------- -------------,

STRB2

(0 AM

STRBI

(C RC Error)

i

undetected)

(RIW Command End)

- - - - - ------------~-Set with DA M Undetecte

,"'"---~-Set with CRC Error

Command End with DAM Undetected

i
STRAI

FF

\

STRAO (Oat a Transfer Request)
Set Pulse

ISRO

CR:I

~GAP-

Read Data
Valid

STRBO

CRC

' " Set if DAM is 'FB',
Remains 100"if DAM
is 'FB',

(DO AM detected)

il

'i-

ISR2
(Sense Request)

ISR Read

Unless DAM(FB) or DDAM(FS) is detected within 32 bytes after ID field has been detected,STRB2 is set to end the command.

Figure 27 Data Transfer Timing of SSR, RCR Command

I

10-CRC

Data from
the diskette

FF

FF

-;-;-b~tes
IDCRC
"0"

(Data Transfer

00

1st
Data

2nd
Data

127th
Data

-)

--- ------- ---

\

~)

DOR ~ DOSR
Transfer

~

Writing

onOOR

128th
Data

1

6 bytes

WGT

STRAO

00

I

Data
DAM'
or
DDAM

- --

---

-Write Data

rutl ~K m
~ ~

d

~

CRC

CRcJ

FF

FF

~
I

~

,...-Transfer Error

STRBO
(Data Transfer Error)

,..--ISRO
(R/wComman d End)

-

ISR2
(Sense Request!

Command End

If

..\

ISR Read

• As Data Address Mark, SSW command writes 'FB' and SWD command writes 'FS'.

Figure 28 Data Transfer Timing of SSW, SWD Command

_HITACHI

403

HD6843,HD68A43------------------------------------------------------Commend Set

~~-+-r--~-------+--~~--~------_+_4r~~~~------~~---------Addra••
Sear

FOC
Operation

Addres.
Search

Data Transf.r

Address
Data Transfer

GCR-l

Search

Data Transfer

GCR-l

GCR-l

~~~~::a~t----------------------~S~A~R~+l~--------------~S~A~R~+~l~~----------~S~A~R~+~l~(~G~C_R~)=~O___________
~--------------~-------------

-- - -------- r.--------

(RiW eo'!:..-:d":E..
nd:':')--------~------------------~---::::~-o;;;;;;:;;;::::::=:n::t-=-=:i
......- - - - - - - - - - - - - - ' Command End
Command End with Address Error

Address Search and Data Transfer in each sector is the same as those of SSR or SSW command.
When Add~ess Error occurs, it results in Command End. If an error relating to Data Transfer occurs,
Error flag IS sat. But the command continues to be executed to shift into the next sector.

Figure 29 Timing Sequence of MSR, MSW Command
Set "00" Command into CMR

CommlndSet

HLO

I
1,...-----------------------------11-----------------"\

Se.ttling
tIme
WGT

2nd
Data

1st Data

OOR

• The first one-byte data must be set into DOR before Command Set.
• If HLD has already been "High" when the command is set, WGT becomes "High" immediately.
• When '00' command is set into CMR, an interrupt of Command End is not generated.

Figure 30 Timing Sequence of FFW Command

Commend Set

Set "00" commlnd into CMR

Settling time
~::

Data _______________J
1st
Dati

OSR

~::~sf_;. OIR__________________..'+_. . II;__.........;-...n+.......

,+........ "'+........,~ I-''"+........ ~--, ....r__......I _.......- - - - - - - - - - - - -

OIR
~f·O:~

out_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _........____, .......n___, ...._

......__......- t .......__, ..._ .......__.... .....__.OJ

STRAO
10Itl 'trlnsfer Request)

If HLD has already been "High" when the command is set, Read operation starts immediately without waiting for the settling time.
When "00" command is set into CMR, an interrupt of Command End is not generated.

Figure 31 Timing Sequence of FFR Command

404

_HITACHI

-----------------------------------------------------------HD6843,HD68A43
Bit 6: ISR3 Interrupt Mask
CMR bit 6 (ISR3 Mask) is used to control the operation of
ISR bit 3. A logic "I" in CMR bit 6 inhibits output of STRBOR-Interrupt signal to IRQ. If CMR bit 6 (ISR3 Mask) and
CMR bit 7 are "0" STRB-OR-Interrupt signal will be output to
IRQ.

times. For MSR and MSW commands, it is set for each sector.
In the PC I/O mode, an interrupt occurs when Status Sense
Request becomes a logic "1". In the DMA mode, (DMA flag of
CMR is set) Status Sense Request is unchanged and does not
generate an interrupt when the address ID field has been
verified.

Bit 7: Function Interrupt Mask
When CMR bit 7 is a logic "I" all interrupts are inhibited.

Bit 3: STRB-OR
STRB·OR is an "OR" of all of the bits of Status Register B.

STRS-OR = STRBO + STRBI + STRB2 + STRB3 +
STRB4 + STRB5 + STRB6 + STRB7
STRB-OR-Interrupt = STRBI + STRB2 + STRB3 +
STRB4 + STRB5 + STRB6 + STRB7

Table 5

Causes
of
Interrupt

Command Register Masks
That Affect Interrupts
CMR7
CMR6
(Function
Interrupt (lSR3 Mask)
Mask)

CMR5
(DMA Flag)

STRS-OR-Interrupt signal cau~s IRQ. STRB-OR is read
by Read ISR. STRBO (Data Transfer Error) sets ISR Bit 3 but
does not cause Interrupt.

ISRO
(Read write
Command End)

M

X

X

ISRO, ISRl, and ISR2 are cleared when the Interrupt Status
Register is read, but ISR3 is cleared only after Status Register B
has been read except when FI input is "High".

ISRl
(Seek Command
End)

M

X

X

• Set-Up Register (SUR); Hex address 3, write only

ISR2
(Status Sense
Request)

M

X

M

ISR3
(STRB·OR·
Interrupt)

M

M

X

Bit 0 - Bit 3: Head Settling Time
The head settling time is used to generate a delay after the
head is placed in contact with the disk. This allows the head to
stop bouncing before any operations are performed. The delay
is programmed by bits 0-3 and is specified by the equation:

x = No effect
M = Bits that are used as masks

• Interrupt Status Register USR); Hex address 2, read only
Bit 71Bit 61Bit 51 Bit 4
Not Used
(Read as "0")

Bit 3
STRB
-OR

Bit 2*

Bit 1*

The SUR is not affected by a reset operation; therefore, once
it is initialized, the information remains until power is removed
from the FDC.

Bit 0*

Seek
Read Write
Status
Sense Command Command
End
Request
End

* Cleared by RES

Bit 0: Read Write Command End (RWCE)
When an SSR, RCR, SSW, SWD, MSR or MSW Macro
Command has completed executioil, bit a becomes set (logic
"1 "). If the function interrupts are enabled (bit 7 of CMR is a
logic "0"), the conclusion of a Macro Command's execution will
cause an interrupt.

Delay = 4096
f

•B

B = Number contained in bits 0'-3 of SUR
f = Frequency of ClK input

For IBM3740 compatibility f = 1 MHz and the timing range
is 4.096 ms for a "0001" to 61.44 ms for a "1111". A "0000"
code prevents Settling Time complete from being set and the
FDC must be Reset.
Bit 4 - Bit 7: Track to Track Seek Time
The frequency of STP is determined by bit 4- bit 7 of SUR
as shown below.

Bit 1: Seek Command End (SCE)
Seek Command End is set on SEK and STZ commands to
indicate the head has been loaded and the settling time specified
in SUR has expired. Since RWCE is not set for the SEK or STZ
command, SCE can be used as an interrupt to signify the SEK
or STZ command has finished. SCE is not set for any of the
R/W commands.

~~----------~~

Bit 2: Status Sense Request
For an SSR, SSW, SWD, MSR, or MSW Command, Status
Sense Request indicates that the specified address ID field has
been detected and verified by a CRC check. This is used as an
early indication that data transfers will occur after 18 more byte

For IBM compatible operation, f is 1 MHz. This results in an
STP pulse width of 32 J.LS and an STP interval of 1.024 ms for a
"000 1" to 15.36 ms for a "1111".

$

11------------ri;f-

A 1024

f

-------...jl

A = Number specified in bits 4-7 of SUR.
f = Frequency of ClK input.

HITACHI

405

HD6843,HD68A43------------------------------------------------------• Status Register A (STRA); Hex address 3, read only
Bit 7*

Busy

Bit 6

Index

Bit 5* Bit 4
Track
Not
Equal

Write
Protect

Bit 3
Track
Zero

Bit 2

Bit 1·

Drive
Ready

Delete
Data
Mark
Detected

of STRB bit 3) during the address search phase of a non-free
format read/write command.
Bit O·
Data
Transfer
Request

* Cleared by 'RES

Bit 7: Busy
When Busy is a logic" 1", the FDC is executing a command
and no new commands can be issued. Busy should be confirmed
to be "0" before reading ISR or STRB as well as issuing a
command.
• Sector Address Register (SAR); Hex address 4, write only

Bit 0: Data Transfer Request
For a write operation (SSW, SWD, MSW, FFW) the transfer
request bit indicates that the DOR is ready to accept the next
data word to be written on the disk. If data is not written into
the DOR before the last data bit in the DOSR is shifted out to
the WDT line; the data transfer error bit (bit 0 of STRB) will be
set. After a write command has been issued, the first transfer
request occurs simultaneously with the Status Sense Request.
For a write operation, transfer request is reset after the DOR
has been written from the data bus.
DUring a read operation (SSR, MSR, FFR) the transfer
request bit Signifies data from the DISR has been transferred to
the DIR. The DIR must be read before the DISR is full again or
the data transfer error bit (bit 0 of STRB) will be set. For read
operations, transfer request is reset by a read of the DIR.
Bit 1: Delete Data Mark Detected
A Single Sector Read operation that detects a delete data
code (F8) instead of a general data code (FB) as a Data Address
Mark will set the Delete Data Mark Detected bit. For the MSR
command, bit 1 is set the first time an "F8" code is found and
remains set throughout the execution of the command. Bit 1 is
reset whenever an SSR, SSW, SWD, MSR, MSW, or RCR
command is issued.
Bit 2: Drive Ready
The Drive Ready bit indicates the state of the Ready input
from the floppy disk drive. If a command is issued with Ready
at logic "0", its execution will be inhibited until Ready becomes
a logic "I". If ready becomes a "0" during the execution of a
command the Hard Error Flag (STRB bit 7) is set.
Bit 3: Track Zero
The state of the Track Zero input from the floppy disk drive
is reflected in this bit of STRA. A logic "1" on the Track Zero
input inhibits step pulses during an STZ command.
Bit 4: Write Protect
The Write Protect input from the floppy disk drive is
reflected by bit 4 of STRA. A "High" level (logic "1") on the
WPT input during the execution of any write command results
in a write error (bit 6 of STRB set).
Bit 5: Track Not Equal
If the track address read from the address ID field does not
coincide with the address in the LTAR inspite ofCRC matching
the one calculated by FDC, the Track Not Equal bit is set.
Track Not Equal applies to all non-free format read/write commands, and is· reset after a non-free format read/write command is issued.
Bit 6: Index
The state of the index input appears in bit 6 of STRA. The
index input is used to count the number of disk revolutions
while the FDC is looking for the address ID field (see operation
406

$

• Cleared by ~

Before a data transfer macro command (SSW, SWD, SSR,
RCR, MSW, MSR) is issued, the address of the sector on which
the operation is to be performed must be written into the SAR.
The address in the sector address byte of an Address ID field of
the disk is compared with the contents of the SAR. During an
MSW or MSR command, the SAR is incremented after each
sector is read or written. When execution is complete, the SAR
contains the address of the last sector on which an operation
was performed plus one.
•

Statu~

Register B(STRB); Hex address 4, read only

Bit 7·

Bit 6"

Hard
Error

File
Write InoperError
able

Bit 5

Bit 4·
Seek
Error

Bit 3"

Bit 2· Bit 1·

Sector
Data
Address Mark
Unde- Undetected tected

CRC
Error

Bit 0"
Data
Transfer
Error

• Cleared by 'RES

The bits of the STRB represent possible error conditions that
may occur during execution of macro commands. Whenever
STRB is reset, ISR bit 3 is also reset.
Bit 0: Data Transfer Error
Data Transfer Error indicates an underflow or overflow of
data. If a Write operation is being performed, it signifies that
data was not presented to the DOR before the DOSR became
empty. In this case, the current contents of the DOR are transferred to the DOSR and the write operation continues. The
data transfer error temains set until STRB is read, and the data
transfer request remains set until data is written into the DOR.
The operation of the CRC is unchanged.
For read commands, a data transfer error indicates that data
in the DIR was not read before the next data word from the
disk was transferred to the DIR. The read operation continues
until sufficient data has been read from the disk to satisfy the
requirements of the command (I28 bytes for SSR). The error
indication remains set until STRB is read, and the transfer
request remains set until data is read from the DIR.
Bit 1: CRC Error
A C&C error occurs when the CRC read from the disk does
not match that calculated by the FDC on the data it reads from
the disk. A CRC error can occur in two different situations;
checking the address ID field, checking the data field.
If the CRC error occurs during the check of an address ID
field, Sector Address Undetected (STRB bit 3) will also be
indicated (see Table 6). A CRC error of a data field is indicated
by a CRC Error and no Sector Address Undetected.

HITACHI

-----------------------------------------------------------HD6843,HD68A43
Bit 2: Data Mark Undetected
If a valid data mark is not detected in the data block of a
sector, it is indicated by a Data Mark Undetected error.
Bit 3: Sector Address Undetected
The Sector Address Undetected bit can be set on two conditions; not finding the sector address and a CRC error on an
address ID field.
If the disk makes three revolutions during an address search
operation and the sector address specified in the sector address
register is not found in any of the address ID fields, a Sector
Address Undetected condition is indicated.
A CRC error that occurs on an address ID field will set bit 3
also. Table 6 shows how bits I and 3 are related.
Table 6 Relationship of CRC Error and
Sector Address Undetected

CRC Error
(STRB1)

Sector
Address
Undetected
(STRB3)

Condition

0
0

0

No Error

1

Sector Address not Detected

1

0

CRC Error on a Data Field

1

1

CRC Error on Address ID Field

Bit 4: Seek Error
An STZ (Seek Track Zero) command that never receives a
track zero indication on the track zero input will result in a
Seek Error (see description of STZ command).
Bit 5: File Inoperable
The state of the File Inoperable input appears in bit 5. If the
File Inoperable input is a "High" level, a pulse of width equals
to Enable pulse width PWEL is issued on the FIR output when
STRB is read. FI is not latched but the input is gated to the bus
when STRB is read.
Bit 6: Write Error
If the WPT input becomes a "High" level (logic "I ") during
the execution of a write command the Write Error bit is set.
Bit 7: Hard Error
If the Ready input becomes a "Low" level during the operation of a command (Busy is set), a Hard Error indication will
result.
• General Count Register (GCR); Hex address 5, write only

61

Bit

51

Bit

41

Bit 3

The eCR contains the destination track address for the R/W
head on an SEK Macro Command. The contents of the eCR are
transferred to the CT AR at the end of the SEK Command. For
multi-sector read or write operations (MSR, MSW), the eCR
contains the number of sectors to be read minus one. During the
MSR or MSW execution the eCR is decremented after each
sector is read or written.
• CRC Control Register (CCR) ; Hex address 6, write only
Bit

71 Bit 61 Bit 51 Bit 4 I Bit 3 I Bit 2
Not Used

Bit 1

Bit 0

Shift CRC
CRC Enable

The CCR information is used only in the free format
commands; for all other commands this register is masked and
has no function.
Bit 0: CRC Enable
During an FFW command, CRC Enable is set by software
and CRC generation takes effect on the next transfer of data
from DOR to DOSR (see figure 32). The CRC generation
continues until Shift CRC (CCR bit 1) is set.
For an FFR command, CRC Enable is set by software and
CRC generation takes effect on the next data read from DIR.
The calculation continues for all data bytes read from DIR until
CRC Enable is reset. The bytes read previous to resetting CRC
Enable are considered the CRC information bytes and the CRC
check is made against them.
Bit 1: Shift CRC
Bit 1 is valid only for the FFW command. After setting, it
takes effect on the next transfer of data from DOR to DOSR
(see Figure 33). Setting Shift eRC terminates the CRC
calculation and causes the CRC calculated on all the data
written into DOR up to the setting of bit I, to be shifted out
the WDT output. The CRC calculation will not include any data
written to DOR after Shift CRC is set.
•

LTAR (Logical Track Address); Hex address 7, write only
Bit 7
Not
Used

Bit 6

I Bit 5 I Bit 4 i Bit 3 I Bit 2 I Bit 1 TBit 0
7 Bit Logical Track Address

When a read or write macro command (SSW, SWD, SSR,
RCR, MSW, MSR) is issued, the address of the track on which
the operation is to be performed must be written into the
LT AR. The address in the track address byte of an Address ID
field of the disk is compared with the contents of the LTAR.
The contents of LT AR are not affected by the execution of any
of the commands.

I Bit 2 I Bit 1 I Bit 0

Bit 7

Bit

Not
Used

7 Bit Count for Track Number on SEK Command
and Sector Count for MSR or MSW Command

$

HITACHI

407

HD6843,HD68A43------------------------------------------------------CRC
Enable
Reset
(CCRO=O)
Read Data
Byte n from
DIR
(Data n)
DCK (Data
Clock Input)
Load Signal
fromDISR
toDIR
DTR

~~~~)able_-+_ _ _~ \......._ _ _ _ _ _ _+ __-{~---+_-----_+----Io~~
~-+------

CRC
valid
DISR
DIR
CRC Calculation includes Data Byte 1 through Data Byte n.

Figure 32 CCR Control Register Timing for an FFR Command (READ)

Shift
CCA Set
(CCRO=1)
Write (CCR1 =1 )
Byte n
to DOR
(Data n)

CCR Enable Set
(CCRO=1)
(CCR1=O)

Shift
Clock
Load signal
from DOR
to DOSR
STRAO
(DTA)
CCRO
(CRC Enable)
CCR1
(Shift CRC)
CAC valid
DOR
DOSR

WDr
Output

Data 2
The CAC Calculation includes Data Byte 1 through Data Byte n-1.

Figure 33 CCR Control Register Timing for an FFW Command (WRITE)

408

$

HITACHI

Write Byte
n+2 to DOR
(Data n+2)
CCA Set
(CCAO=O)
(CCR1=O)

---------------------------------------------------------HD6843,HD68A43
Table 7 Programming Reference Data
Table 7 is a summary of the information in the data sheet and can be used as a reference when programming the HD6843.

Registers

CMR

Hex
Address

2

R/W
Mode

WO

Data Bits

Bit 7

Bit 6

Bit 5

Bit4

Function
Interrupt
Mask

ISR3
Interrupt
Mask

DMA
Flag

FWF

I

Bit 7
ISR

2

STRB

3

4

*

I

Bit 5

Bit 6

Bit 5

Busy

Index

Track
Not
Equal

Bit 7 *

Bit 6 *

RO

RO

I

Bit4

Not Used

RO

Bit 7

STRA

Bit 6

Hard
Error

Write
Error

*

Bit 4
Write
Protect

Bit 5
File
Inoperable

Seek
Error

*

I

Bit 2

*

I

Bit 1 *

I

Bit 0 *

Macro Command

Bit 3

Bit 2 *

STRB
-OR

Status
Sense
Request

Bit 3

Bit 2

Track
Zero

Bit 3 *

Drive
Ready

Bit 2 *

Sector
Data
Address
Mark
Undetected Undetected

Bit 1

*

Bit 0

*

Read Write
Seek
Command Command
End
End

Bit 1 *

Bit 0 *

Delete
Data Mark
Detected

Data
Transfer
Request

Bit 1 *

Bit 0 *

CRC
Error

Data
Transfer
Error

* Cleared by RES

RO - Read Only
WO - Write Only
RIW - ReadlWrite

$

Bit 4 *

Bit 3

HITACHI

409

HD6843,HD68A43---------------------------------------------------------MACRO COMMANDS
Hex Code

Instruction

Hex Code

Instruction

2
3
4
5

STZ
SEK
SSR
SSW
RCR
SWD

A

FFR
FFW
MSR
MSW

6

7

B

C
D

Table 8 Error Condition, Command Execution, Interrupt, and Head Control
Flag

Set Condition

Track Not
Equal

STRA5

Track information of 10 field
is not equal to the content of
LTAR.

Data
Transfer
Error

STRBO

Overrun or underflow during
the data transfer

Reading of STRB

SSR, MSR, SSW,
SWO, MSW, FFR
FFW

Read/Write command continues to be executed.

CRC
Error

STRBl

CRC Error on 10 field or Date
field

Reading of STRB

SSR, RCR, MSR,
SSW, SWO, MSW
(FFR)

The execution of a command Request
is interrupted and R/W
OSRO,
Command End OSRO) is set. ISR3)

Unchanged··

Data Mark
Undetected

STRB2

DAM or OOAM is undetected
within 32 bytes after 10 field
has been detected.

Reading of STRB

SSR, RCR, MSR

The execution of a command Request
is interrupted and R/W
OSRO,
Command End OSRO) is set. ISR3)

Unchanged" "

Sector
Address
Undetected

STRB3

(1 ) Sector Address of 10
field is not equal to the
content of SAR.
(2) CRC Error on 10 field

Reading of STRB
SSR, RCR, MSR
after Busy (STRA7)
SSW, SWO, MSW
is reset.

The execution of a command Request
is interrupted and R/W
OSRO,
Command End OSRO) is set. ISR3)

Unchanged
(Head remains
loaded after
settling time
has expired.)

Seek Error

STRB4

TRZ signalsemains "Low"level
though eighty-two STP pulse
outputs are provided in STZ
command.

Reading of STRB

STZ

The execution of a command
Request
is interrupted and Seek
Command End OSR1) is set. OSR1,
ISR3)

Unchanged

STRB5

A "High" level input of FI
terminal is reflected.

FI signal of the
FOO is reset when
"High" pulse output is provided by
reading of STRB
at FI="l".

All commands

The execution of a command
is interrupted. If it is a
Read/Write command, ISRO
is set. If it is a seek command,
ISRl is set.

Write operation (WGT="High")
is performed when the input of
WPT terminal is "High" level.

Reading of STRB

STRB6

SSW, SWO, MSW
FFW

The execution of a command Request
is interrupted and R/W
OSRO,
Command End OSRO) is set. ISR3)

All commands

The execution of a command
is interrupted. If it is a Read/
Write command, ISRO is set.
If it is a seek command, ISRl
is set.

Error

File
Inoperable

Write
Error

Hard Error

STRB7

Not Ready
during the
idling

STRA2

ROY input signal becomes
"Low" level during the execution of a command (Busy="l".)

-

Reset Condition

Command

Issuing of SSR, RCR,
MSR, SSW, SWO or SSR, RCR, MSR
SSW, SWO, MSW
MSW Command

Reading of STRB

-

Command Execution

-

" These errors except STRB5 and STRA2 are reset by "RES inputs.
". Head is unloaded if the new command is not issued during the settling time after Read/Write command ends.

410

$

HITACHI

Interrupt Head Control

The execution of a command
Request
is interrupted and R/W
Command End OSRO) is set. OSRO)

-

Unchanged""

No
Unchanged··
interrupt

Unload the
Request
head imediatel
OSROor (HLO="Low")
ISR1,
Set WGT to
ISR3)
"Low"
Unload the
head imediatel y
(HLO="Low"
Set WGT to
"Low"

Unload the
Request head imediatel y
IISRO or (HLO="Low")
ISR1,
Set WGT to
ISR3)
"Low"
Unload the
No
head imediatel y
interrupt
(HLO="Low")

HD6844, HD68A44,
HD68B44
DMAC (Direct Memory Access
The HD6844 Direct Memory Access Controller (DMAC)
performs the function of transferring data directly between
memory and peripheral device controllers. It controls the
address and data buses in place of the MPU in bus organized
systems such as the HMCS6800 Microprocessor System.
The bus interface of the HD6844 includes select, read/
write, interrupt, transfer request/grant, and bus interface logic
to allow the data transfer over an 8-bit bidirectional data bus.
The functional configuration of the DMAC is programmed via
the data bus. The internal structure provides for control and
handling of four individual channels, each of which is separately
configured. Programmable control registers provide control for
the transfer location and length, individual channel control and
transfer mode configuration, priority of servicing, data chaining,
and interrupt control. Status and control lines provide control
to the peripheral controllers.
The mode of transfer for each channel can be programmed as
cycle-stealing or a burst transfer mode.
Typical applications would be with the Floppy Disk Controller (FDC), etc ..

Controller)

HD6844P, HD68A44P, HD68B44P

(DP-40)

• PIN ARRANGEMENT

o

t/J,DMA

ReS
DGRNT

DRciT

•
•

FEATURES
Four DMA Channels, Each Having a 16-Bit Address
Register and a 16·Bit Byte Count Register
• 1 M Byte/Sec (HD6844), 1.5 M Byte/Sec (HD68A44),
2.0 M Byte/Sec (HD6BB44)
Maximum Data Transfer Rate

DROH
TxAKA

TxSTii
iRci/i5E"N'O
HD6844

•
•
•
•
•

Selection of Fixed or Rotating Priority Service Control
Separate Control Bits for Each Channel
Data Chain Function
Address Increment or Decrement Update
Programmable Interrupts and DMA End to Peripheral
Controllers
• Compatible with MCS844, MCS8A44, MCSBB44

TxRO.
TxRO,
TxRO,
TxRO,

• BLOCK DIAGRAM

(Top View)

Address/Control and Interrupt

Data
Bus

$

HITACHI

411

HD6844,HD68A44,HD68B44-------------------------------------------------• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Value
-0.3 - +7.0

V

Input Voltage

Vee *
Yin *

-0.3 - +7.0

V

Operating Temperature

Topr

-20 -+75

°c

Storage Temperature

Tstg.

-55-+150

°c

Supply Voltage

Unit

* With respect to Vss (SYSTEM GND)
(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be
under recommended operating conditions. If these conditions are exceeded, it could affect
reliability of LSI.

• RECOMMENDED OPERATING CONDITIONS
Item

Symbol

min

typ

max

Unit

Power Supply Voltage

Vee *
V 1L *

4.75

5.0

5.25

V

-0.3

0.8

V

VII; *

2.0

-

Topr

-20

25

Vee
75

°c

Input Voltage
Operati ng Temperature

V

* With respect to Vss (SYSTEM GND)

• ELECTRICAL CHARACTERISTICS (VCC=5V±S%, VSS=OV, Ta=-20-+7SoC, unless otherwise noted.)
• DC CHARACTERISTICS
min

typ*

max

Unit

Input "High" Voltage

V 1H

2.0

V 1L

-0.3

Vee
0.8

V

Input "Low" Voltage

-

V in =0-5.25V

-2.5

-

2.5

p.A

V in =0.4-2.4V

-10

-

10

p.A

IOH=-205p.A

2.4

-

-

IOH=-145p.A

2.4

IOH=-100p.A

2.4

-

Item

TxRO o - 3 • ¢2 OMA,
RES.OGRNT

Input Leakage Current
Three-State (off state)
Leakage Current

Symbol

i

'in

Ao"'A I5 • 0 0 "'0 7 , R/W

!

Test Condition

TS1
'

0 0 -0 7

-.----

Output "High" Voltage

A o-A I5 • R/W

VOL

IOL =1.6mA

-

-

0.4

V

less

Vin=OV, Fig. 10

-

10

16

mA

-

500

1000

mW

-

20

-

-

12.5

-

-

10

-

-

12

V OH
I

All Other Outputs
Output "Low" Voltage
Source Current

CS/TxAKB

Power Dissipation

Po
¢2

Input Capacitance

0MA

0 0 -0 7 , CS, A o -A 4 •
R/W
TxRO oOGRNT

Output Capacitance
*

3,

Cin

Vin=OV, T a=25°C
f=1.0MHz

Cout

Vin=OV, Ta= 2SoC, f=lMHz'

RES.

vec=s.ov, Ta=2SOC

412

V

$

HITACHI

V

pF

pF

--------------------------------------------------HD6844,HD68A44,HD68844
•

AC CHARACTERISTICS (Load Condition Fig. 9)
1. CLOCK TIMING
Item
C/l, DMA Cycle Time
C/l, DMA Pulse Width

Symbol

II

HD6844

Test
Condition

min

typ

HD68A44
max

min

typ

HD68B44
max

min

typ

Unit
max

tcycC/l

Fig.2

1000

-

-

666

-

-

500

-

-

"High" Level

PWC/lH

Fig. 2

450

-

-

280

-

-

235

-

ns

"Low" Level

PWC/lL

Fig. 2

400

-

230

210

-

ns

Fig. 2

-

25

-

-

-

tC/lr, tC/lf

-

25

-

-

25

ns

Test
Condition

min

typ

max

min

typ

max

min

typ

max

C/l, DMA Rising
tToS1
Edge

120

-

-

120

-

-

120

-

-

C/l, DMA Falling
tTOS2
Edge

210

-

-

210

-

-

155

-

-

tTOH1

20

-

-

10

-

-

10

-

-

C/l , DMA Falling
tTOH2
Edge

20

-

-

10

-

-

10

-

-

-

115

-

-

-

10

-

160

C/l, DMA Rise and Fall Time

ns

2. DMA TIMING (Load Condition Fig. 9)
Item

Symbol

HD6844

HD68A44

HD68B44
Unit

TxRO Setup Time

ns
I

Fig.3
C/l, DMA Rising
Edge
TxRO Hold Time

155

-

-

125

10

-

-

10

-

Fig.6

-

-

270

-

-

180

-

-

Fig.6

30

-

-

20

Fig.7

-

35

-

-

35

-

-

ns

35

-

20

tAHO

-

Ao-A 1s , Riw

tATSO

Fig. 7

-

-

270

-

-

270

-

-

270

ns

Ao-A 1s , R/W

tATSR

Fig. 7

-

-

270

-

-

270

-

-

270

ns

DROH,DROT tooo

Fig.5

-

-

375

-

-

250

-

-

210

ns

C/l,0MA Rising
Edge

tTK01

Fig.5

-

-

400

-

-

310

-

-

250

OGRNT Rising
tTK02
Edge

Fig.8

-

-

190

-

-

160

-

-

150

C/l, OMA Falling
tOE01
Edge

Fig.6

-

-

300

-

-

250

-

-

210

DGRNT Rising
tOE02
Edge

Fig.8

-

-

190

-

-

160

-

-

125

Test
Condition

min

typ

max

min

typ

max

min

typ

max

tAS

140

-

-

140

-

-

70

-

-

ns

tAHI

10

-

-

10

-

-

10

-

-

ns

DGRNT Setup Time

DGRNT

tOGS

DGRNT Hold Time

DGRNT

tOGH

Address Output
Delay Time

Ao-A", R/W,
TxSTB

tAD

Address Output
Hold Time

Ao-A 1s • R/W
TxSTB

Address Three-State
Delay Time
Address Three-State
Recovery Time
Delay Time

ns

Fig.4

TxAK Delay Time

IRO/DENO Delay
Time

ns

ns

ns

ns

3. BUS TIMING
1) READ TIMING
Item

Address Setup Time

Symbol
Ao-A.,R/W,

CS

H06844

H068A44

H068B44
Unit

Address Input Hold
Time

CS

Data Delay Time

0,-0,

tOOR

-

-

320

-

-

-

180

ns

0 0 -0,

tACC

-

-

460

-

-

220

Data Access Time

360

-

-

280

ns

Data Output Hold
Time

0 0 -0,

tOHR

10

-

-

10

-

-

10

-

-

ns

Ao-A.,R/W,

Fig. 2

~HITACHI

413

HD6844,HD68A44,HD68B44--------------------------------------------------2) WRITE TIMING
Item

Address Setup Time

Symbol
Ao-A •• R/W.

CS

Address Input Hold
Time

CS

Data Setup Time

0 0 -0 7

Data Input Hold
Time

0 0 -0 7

A o -A 4 • R/W.

H06844

Test
Condition

tAS

H068A44

min

typ

max

min

typ

140

-

-

140

-

H068B44
max

Unit

min

typ

max

-

70

-

-

ns

-

10

-

-

ns

10

-

-

10

-

tosw

195

-

-

80

-

-

60

-

-

ns

tOHW

10

-

-

10

-

-

10

-

-

ns

tAHI

Fig. 2

R/W

BUS

CS

T.AKB

_______
_
110 H J.I _______
L

DRQT~----r----;

_! ~ __H__ ~ ___ '= ___ _

~T------~--~

DRQH

112 H
L
-#3
-"H- -:--- -L-- -I

-----~--__1

CHANNEL

. . . - - - - - , CONTROL
#0
REGISTER
III

(6X4)

.....--------T.RQ,
T.~

#2
#3

/-f.AK
GENERAL

.......- - - - , CONTROL

CONTROL

BYTE COUNT REGISTER
(16X4)

REGISTER

.....--------T.RQ,

TxRQ,

t---------T.RQ.
TxSTB
T.AKA

RESVccVss_

Figure 1 Expanded Block Diagram

414

$

HITACHI

--------------------------HD6844,HD68A44,HD68B44

1-----------

tcycl/>··-----------I~

2.0V

Ao::::..A4 \Input!
R/W (Input)

CS (Input)

I
f~H~1

o-tOOR--j

1-----tACC--!

Do -0 7 (Output)
(Read Operation)

tosw

2.0V

Do -0 7 (Input)

2.0V

(Write Operation)

O.8V

Figure 2 Read/Write Sequence

Figure 3 Timing of TxRQ Input

_HITACHI

415

HD6844,HD68A44,HD68B44-------------------------------------------------Set Up Timing

~ __________ A20V
'0:'-1
--------

~2DMA

---------

2.0V

DGRNT
O.8V

Hold Timing

~2DMA

DGRNT

Figure 4 Timing of DGRNT Input

2.0V
~2DMA

toaD
2.4V

O.4V

2.4V
TxAKA
CS/TxAKB (Output)
O.4V

Figure 5 Timing of DROH, DROT, TxAK Outputs

416

$

HITACHI

--------------------------HD6844,HD68A44,HD68B44

¢,DMA

tAO"2AV
Ao.:::...A, s (Output)
R/W (Output)

TxSTB

O.4V

tDEOX1
2.4V

-------------------

OAV

------------------------

Figure 6 Timing of Addres£ and I RQ/OEND Outputs

"Recovery Time of Address Three-state

¢, DMA (or DGRNTl

2.4V

O.4V

Delay Time of Address Three-state

¢,DMA

tATSD2.4V

O.4V

tAHO

Figure 7 Timing of Address Three-state

_HITACHI

417

HD6844,HD68A44,HD68844---------------------------------------------------

DGRNT

CS/TxAKB (Output)

IRQ/DEND

Figure 8 Timing of Synchronous DGRNT Output

5.0V

2.4kU

Test terminal
00"'D7

Test terminal

0---.-.-_-...----+
0,

C

0,

C

R

130 pF

11 kil

Ao"'A15, R/W
CS/TxAKB

90pF

16kil

50 pF

24kil

All other outputs

30 pF

24 kil

0 1 - 04

:

1S2074 tED or equ ivalent.

Figure 9 Load Circuit

r----------------------------l

,

,
,
,

HD6844

Vee

ON

:i..-:,____

less

~-rl-~~

TxAKB output

OFF

I
I

D.C. Ammeter

I

Vss
TxAK ENABLE

I
I
I

I
I
I
I
I

CS input
,

Vss

I

L ___________________________ J
Figure 10 Source Current Measurement Circuit for CS/TxAKB Terminal

418

eHITACHI

---------------------------------------------------HD6844,HD68A44,HD68844
•

DEVICE OPERATION

The DMAC has fifteen addressable registers, eight of them
are sixteen bits in length. Each channel has a separate Address
Register and a Byte Count Register, each of which is sixteen
bits. There are also four Channel Control Registers. The three
General Control Registers common to all four channels are the
Priority Control Register, the Interrupt Control Register, and
the Data Chain Register.
To prepare a channel for DMA, the Address Registers must
be loaded with the starting memory address and the Byte Count
Register loaded with the number of bytes to be transferred. The
bits in the Channel Control Register establish the direction of
the transfer, the mode, and the address increment or decrement
after each cycle. Each channel can be set for one of three
transfer modes: Three-State Control (TSC) Steal, Halt Steal, or
Halt Burst. Two read-only status bits in the Channel Control
Register indicate when the channel is busy transferring data and
when the DMA transfer is completed.
The Priority Control Register enables the transfer requests
from the peripheral controllers and establishes either a fixed
priority or rotating priority scheme of servicing these requests.
When the DMA transfer for a channel is complete (the Byte
Count Register is zero), a DMA End signal is directed to the
peripheral controller and an IRQ goes to the MPU. Enabling of
these interrupts is done in the interrupt Control Register. The
IRQ flag bit is read from this register.
Chaining of data transfers is controlled by the Data Chain
Register. When enabled, the contents of the Address and Byte
Count Registers for channel #3 are put into the registers of the
channel selected for chaining when its Byte Count Register
becomes zero. This allows for repetitively reading or writing a
block of memory.
During the DMA mode, the DMAC controls the address bus
and data bus for the system as well as providing the R/W
line and a signal to be used as VMA. When a peripheral
device controller desires a DMA transfer, it is requested by a
Transfer Request. Assuming this request is enabled and meets
the test of highest priority, the DMAC will issue a DMA
Request. When the DMAC receives the DMA Grant, it gives a
Transfer Acknowledge to the peripheral device controller, at
which time the data is transferred. When the channel's Byte
Count Register equals zero, the transfer is complete and a DMA
Eid is given to the peripheral device controller, and an IRQ is
given to the MPU.

The DGRNT signal must cause the address control and data
lines to go to the high impedance state. The DMAC now
supplies the address from the Address Register of the channel
requesting. It also supplies the R/W signal as determined from
the Channel Control Register. After one byte is transferred,
control is returned to the MPU. This method stretches the 1/»
and 4>2 clocks while the DMAC uses the memory.
The second method of cycle-stealing is the Halt Steal mode.
This method actually halts the MPU imtead of stretching the 1/>\
clock for the transfer period. This mode is initiated by the
DMAC bringing the DRQH line "Low". This line connects to
the MPU HALT input. The MPU Bus Available (BA) line is the
DGRNT input to the DMAC. While the MPU is halted. its
Address Bus, Data Bus, and R/W are in the high impedance
state. The DMAC now supplies the address and R/W line. After
one byte is transferred, the HALT line is returned "High" and
the MPU regains control. In this mode. the MPU stops internal
activity and is removed from the system while the DMAC uses
the memory.
The third mode of transfer is the Halt Burst mode. This
mode is similar to the Halt Steal mode. except that the transfer
does not stop with one byte. The MPU is halted while an entire
block of data is transferred. When the channel's Byte Count
Register equals zero, the transfer is complete and control is
returned to the MPU. This mode gives the highest data transfer
rate, at the expense of the MPU being inactive during the
transfer period.
•

INPUT/OUTPUT FUNCTIONS

•

DMAC I nterface Signals for the MPU

The DMAC interfaces with the HMCS6800 MPU through the
eight-bit bidirectional data bus, therS line, five address lines,
an IRQ line, the Read/Write line, and the RES line. These signals, in conjunction with the HMCS6800 VMA output, permit
the MPU to have access to the DMAC. Four other lines associated with the MPU and the clock driver are the DRQT,
DRQH, DGRNT, and the 1/>2 DMA.
Bidirectional Data (Do ~D7)

The Bidirectional Data lines (Do~D7 ) allow for data transfer
between the DMAC and the MPU. The data bus output drivers
are three-state devices that remain in the high impedance state
except when the MPU performs DMAC read operations.
Chip Select/Transfer Acknowledge B (CS/T x AKB)

•

Initialization

During a power-on sequence, the DMAC is reset via the RES
input. All registers, with the exception of the Address and Byte
Count Registers, are- set to a logic "0" state. This disables all
requests and the Data Chain function while masking all
interrupts. The Address, Byte Count, and Channel Control
Registers must be programmed before the respective transfer
request bit is enabled in the Priority Control Register.
• Transfer Modes
There are three ways in which a DMA transfer may be done.
The one used is determined by the data transfer rate required,
the number of channels attached, and the hardware complexity
allowable. Refer to Figures 12, 16 and 17.
Two of the modes, TSt Steal and Halt Steal, are done by
cycle-stealing from the MPU. The Three-State Con~SC)
Steal mode is initiated by the DMAC bringing the DRQT line
"Low". This line goes to the system clock driver which returns a
"High" on DGRNT on the rising edge of the system 4>1 clock.

This line is multiplexed, serving both as an input and an
output. CS/TxAKB is an output in the four-channel mode
during the DMA transfer. At all other times, it is a high
impedance TTL compatible input used to address the DMAC.
The DMAC is selected when CS/TxAKB is "Low". VMA must
be used in generating this input to insure that false selects will
not occur. Transfers of data to and from the DMAC are then
performed under the control of the 1/>2 DMA, Read/Write, and
Ao-~ address lines. In the four-channel mode when TxAKB is
needed, the CS gate must have an open-collector output (a
pull-up resistor should not be used). In the two-channel mode,
CS/TxAKB is always an input.
Address Lines (Ao ~ A4 )

Address lines Ao~A4 are both input and output lines. In the
MPU mode, these are high impedance inputs used to address the
DMAC registers. In the DMA mode, these lines are outputs
which are set to the contents of the Address Register of the
channel being processed.

~HITACHI

419

HD6844,HD68A44,HD68B44--------------------------------------------------Interrupt Request/DMA End (lRO/DEND)

IRQ/DEND is a TTL compatible, active "Low" output that
is used to interrupt the MPU and to signal the peripheral
controller that the data block transfer has ended. If the
Interrupt has been enabled, the IRQ/DEND line will go "Low"
after the last DMA cycle of a transfer. An open collector gate
must be connected to DGRNT and IRQ/DEND to prevent false
interrupts from the DEND signal when interrupts are not
enabled. Refer to the section of "DMA End Control".
Read/Write (R/W)

Read/Write is a TTL compatible line that is a high impedance
input in the MPU mode and an output in the DMA mode. In the
MPU mode, it is used to control the direction of data flow
through the DMAC's input/output data bus interface. When
Read/Write is "High" (MPU read cycle) and the chip is selected,
DMAC data output buffers are turned on and a selected register
is read. When it is "Low", the DMAC output drivers are turned
off and the MPU writes into a selected register.
In the DMA mode, Read/Write is an output to drive the
memory and peripheral controllers. Its state is determined by
bit 0 of the Channel Control Register for the channel being
serviced. When Read/Write is "High", the memory is read and
the data from the memory is written into the peripheral
controller. When it is "Low", the peripheral controller is read
and its data stored in the memory. In the DMA mode, the
DMAC data buffers are off.

indicating that the MPU has halted and turned control of its
busses over to the DMAC. For a design involving TSC Steal and
Halt mode transfers, this input must be the OR of the clock
driven DMA Grant and the MPU BA.
1/>2DMA

Transferring in and out of the DMAC registers, sampling
of channel request lines and gating of other control signals to
the system is done internally in conjunction with the 1/>2 DMA
high impedance input. This input must be the system memory clock (non-stretched 1/>2 clock).
• Transfer Signals From the Peripheral Controller
Transfer Request (TxROo-TxR03 )

Each of the four channels has its own high impedance input
request for transfer line. The peripheral controller requests a
transfer by setting its TxRQ line "High" (a logic" 1"). The lines
are sampled according to the priority and enabling established in
the Priority Control Register. In the Steal mode and the first
byte of the Halt Burst mode, the TxRQ signals are tested on the
positive edge of 1/>2 DMA and the highest priority channel is
strobed. Once strobed, the TxRQs are not tested until that
channel's data transfer is finished. In the succeeding bytes of the
Halt Burst mode transfer, the TxRQ is tested on the negative
edge of 1/>2 DMA, and data is transferred on the next 1/>2 DMA
cycle if TxRQ is "High".
• Transfer Signals to the Peripheral Controller

Reset (RES)

The RES input provides a means of resetting the DMAC from
an external source. In the "Low" state, the RES input causes all
registers, with the exception of the Address and Byte Count
Registers, to be reset to the logic "0" state. This disables all
transfer requests, masks all interrupts, disables the data chain
function, and puts each Channel Control Register into the
condition of memory write, Halt Steal transfer mode, and
address increment.
• Transfer Signals to the MPU

Two DMA request output lines and a DMA Grant input line,
together with the system clock, synchronize the DMAC with the
MPU system.
DMA Request Three-State Control Steal (DROT)

This active "Low" output requests a DMA transfer for a
channel configured for the TSC Steal transfer mode. This line is
connected to the system clock driver, requesting a 1/>1 clock
stretch. It will remain in the "Low" state until the transfer has
begun.

Two encoded lines select the channel to be serviced. A strobe
line acknowledges the request and performs the transfer. The
DEND line signals to the peripheral controller that the DMA
transfer is completed.
Transfer Acknowledge A (T x AKA)

The Transfer Acknowledge A (TxAKA) is a TTL compatible
output used in conjunction with the CS/TxAKB line to select
the channel to be strobed for transfer and to give the DMA End
Signal. In the two-channel mode, only TxAKA is used to select
channel 0 or channel I, and CS/TxAKB is always an input.
Chip Select/Transfer Acknowledge B (CS/TxAKB)

In the DMA mode, this dual purpose line is encoded together
with TxAKA to select the channel being serviced. Table 1 shows
the encoding order.
Table 1 Encoding Order
CS/TxAKB

TxAKA

Channel #

0
0

0

0

1

1
1

0

1
2

1

3

DMA Request Halt (DROH)

This active "Low" output requests a DMA transfer for a
channel programmed for the Halt Steal or Halt Burst mode
transfer. This line is connected directly to the MPU HALT input
and remains "Low" until the last byte has begun to be
transferred.
DMA Grant (DGRNT)

This is a high impedance input to the DMAC, giving it
control of the system busses. For the TSC Steal mode, the signal
comes from the system clock drive circuit (DMA Grant),
indicating that the clock is being stretched. For either of the
Halt modes, this signal is the Bus Available from the MPU,

420

Transfer Strobe (TxSTB)

The TxSTB causes acknowledgement to be given to the
peripheral controller and transfers the data to or from the
memory. This line is also intended to be the VMA signal for the
system in the DMA mode. In a one-channel system, TiSTB may
be inverted and run to the peripheral controller's Acknowledge
input. In a two or four-channel system, TxSTB enables the
decode of TxAKA and CS/TxAKB to select the device
controller to be acknowledged.

eHITACHI

--------------------------HD6844,HD68A44,HD68B44
Interrupt Request/DMA End (IRQ/DEND)
In the DMA mode, this dual purpose line is "Low" for the
last byte of transfer, indicating a DMA End. This occurs when
the Byte Count register decrements to zero.
This line, through the decode of TxAKA and CS/TxAKB,
can be used to strobe a DMA End to each device controller.
•

nels, Interrupt Control Register (ICR) that controls interrupt
and Data Chain Control Register (OCR) that controls data chain
function. Refer to Table 2 and Figure 1.
These are Read/Write registers and MPU can exchange the
data with DMAC when CS is at "Low" level. Ao ...... A4 specifies
the address of the registers. How to specify the registers is
shown in Table 2.
2-byte ADR and BCR can be read or written by one instruction, using 2-byte instruction of the MPU.

Address Lines to the Memory

Address Lines (A o....... A 15 )
These output lines are in the high impedance state during the
MPU mode. In the DMA mode, these lines are outputs which are
set to the contents of the Address Register of the channel being
processed.

• Function of Internal Registers
ADR (Address Register)
Each channel has 16-bit Address Register. Initial address of
memory used for DMA transfer is programmed to this register.
The contents of ADR are output to address bus (Ao""" A 15 )
during DMA transfer operation. When I-byte transfer has completed, the 16-bit address is incremented or decremented by

• THE DMAC REGISTERS
The HD6844 (DMAC) has Address Register (ADR), Byte
Count Register (BCR), Channel Control Register (CHCR), and
General Control Register (GCR).
General Control Register (GCR) is composed of Priority
Control Register (PCR) that controls priority among the chan-

on The address which the MPU reads out is the renewed one,
that is, the memory address for the next transfer. When I-block
transfer has completed, final memory address + I is read out.

Table 2 Internal Registers of the DMAC
Address Bus Signal
Register Name

Symbol

A4

AJ

A2

AI

Ao

Address
(Hexadecimal)

Channel

Address Register

AORH
AORl

0
0

0
0

0
0

0
0

0
0

0
1

00
01

Byte Count Register

BCRH
BCRl

0
0

0
0

0
0

0
0

1
1

0
1

02
03

Address Register

AORH
AORl

1
1

0
0

0
0

1
1

0
0

0
1

04
05

Byte Count Register

BCRH
BCRl

1
1

0
0

0
0

1
1

1
1

0
1

06
07

Address Register

AORH
AORl

2
2

0
0

1
1

0
0

0
0

0
1

08
09

Byte Count Register

BCRH
BCRL

2
2

0
0

1
1

0
0

1
1

0
1

OA
OB

Address Register

AORH
AORl

3
3

0
0

1
1

1
1

0
0

0
1

OC
00

Byte Count Register

BCRH
BCRl

3
3

0
0

1
1

1
1

1
1

0
1

OE
OF

Channel Control Register

CHCR
CHCR
CHCR
CHCR

0
1
2
3

1
1
1
1

0
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

10
11
12
13

Priority Control Register

PCR

0

1

0

0

14

ICR

-

1

Interrupt Control Register

1

0

1

0

1

15

Data Chain Control Register

OCR

-

1

0

1

1

0

16

(NOTE)

1) All the registers can be accessed by R/W operation. Unused bit of the register is read out "0".
2) H/l of ADR and BCR means the higher (H) 8 bits/the lower (L) 8 bits of a 16-bit register.
3) 16-bit ADR and BCR can be read or written by one instruction, using MPU's 2-byte LOAD/STORE instruction.
Register Address
............ [(ADRH 3) -+ (Index Register H)]
e.g. LOX $ ~* Oc
Address of DMAC
(ADRl 3) -+ (Index Register Ll

_HITACHI

421

HD6844,HD68A44,HD68B44--------------------------------------------------BCR (Byte Count Register)
Each channel has a 16-bit Byte Count Register. Number of
DMA transfer words is programmed into this register. The content of the Byte Count Register is decremented by one every time
one-byte transfer has completed. When it becomes "0", DEND
output goes "Low" level and informs I/O controller of the end
of one-block DMA transfer. When IRQ is not masked, IRQ output goes "Low" level and MPU is interrupted to be informed of
the end of DMA transfer. Moreover, IRQ and DEND signals are
output, multiplexed with IRQ/DEND pin.

used to program the control information of its corresponding
channel. Structure ofCHCR is shown in Table 3.
(1) RjW Control (specifies the direction of transfer)
Bit - CHCR Bit 0
This bit controls the direction of DMA transfer. When it
is at "I", R/W signal of DMAC goes "High" level during
DMA transfer operation. This means to read out memory
and write into I/O controller, that is, data is transferred
from memory to I/O controller.
When it is at "0", R/W output goes "Low" level and
data is transferred from I/O controller to memory.

CHCR (Channel Control Register)
Each channel has Channel Control Register. This register is
Table 3 Bit Structure of CHCR (Channel Control Register)
Function

Bit
No.

0

Name

R/W

R/W

R/W

"0"

"1"
Transfer from memory
to I/O controller
(R/W output = "High")

Transfer from I/O
controller to memory
(R/W output = " Low")

1

Burst/Cycle Steal

R/W

Burst Mode

Cycle Steal Mode *

2
3
4
5

TSC/HALT

R/W

TSC Mode

HALT Mode*

Address down/up

R/W

Address: -1

Not used

-

6

Busy/Ready Flag

R

Busy
(DMA Transfer Operation)

Ready
(No DMA Transfer Operation)

7

DEND Flag

R

DMA End & Interrupt

No Interrupt

Not used

Address: +1

-

-

* Burst· TSC mode is prohibited.

Note that during DMA transfer operation, the function of
R/W signal is accommodated to the memory Read/Write
operation. Therefore, on the side of I/O device during DMA
transfer operation, R/W input should be interpreted in
inverse of the MPU Read/Write. That is, data should be output when R/W input is at "Low" level (In the case of
MPU's read operation, I/O device outputs the data when it
is at "High" level).
This arises from that during DMA transfer operation,
I/O side performs data transfer independently instead of
MPU. Moreover, such family LSI as HD6843 (FDC), etc.
has this function and R/W signal is automatically interpreted inversely.
(2) Burst/Cycle Steal Bit - CHCR Bit I
This bit is used to decide that DMA transfer should
be performed in burst mode or cycle steal mode. When it
is at "I ", it specifies burst mode. That is, once DMA transfer is performed, MPU remains stopped until one-block data
transfer is completed.
When this bit is "0", it specifies cycle steal mode. That
is, every time one-byte transfer has completed, MPU takes
back the bus control, and DMA transfer and MPU operation
are performed in time sharing.
(NOTE) Only in the case of HALT mode, burst mode can
be specified. When TSC mode is specified, burst
mode cannot be specified.
(3) TSC/HALT Mode Bit - CHCR Bit 2
This bit is used to decide that DMA transfer should be

422

$

performed by using MPU's TSC function or HALT function. When it is at "0", DRQH output of DMAC is connected to HALT input of MPU and DMA transfer is performed
by using MPU's HALT function.
When it is at "I ", DMA transfer is performed by using
MPU's TSC function. That is, DRQT output is connected to
HD26501 (CPG) and MPU's clock cJ>1 is extended. Then
MPU's TSC input becomes "High" level and the bus gets
into high impedance state to perform DMA transfer.
(4) Address down/up Bit - CHCR Bit 3
This bit is used to decide that the address of memory
region used for DMA transfer should be renewed up (increment of address) or down (decrement of address). When it
is at "I", the address is decremented by one after one-byte
transfer. When it is at "0", the address is incremented by
one.
(5) Busy/Ready Flag Bit - CHCR Bit 6
This bit is a status flag to indicate whether its corresponding channel is performing DMA transfer or not.
(READ only)
When it receives the first TxRQ of its corresponding
channel, it goes to "I". When one-block transfer is completed and BCR becomes "0", it is reset to "0".
Also this flag is cleared when corresponding TxRQ
Enable Bit in the PCR becomes "0".
(6) DEND Flag Bit - CHCR Bit 7
This bit is an interrupt flag to indicate that one-block
DMA transfer of its corresponding channel has completed.

HITACHI

--------------------------HD6844,HD68A44,HD68B44
(READ only).
When one-block transfer of its corresponding channel is
completed and BCR becomes "0", it goes to "I". As soon
as this flag is read out, i.e. CHCR of this channel is read
out, it is reset to "0".
Moreover, this bit is connected to IRQ output. When it
is at "I" and IRQ enable bit (within ICR register described

later) is at "I ", IRQ output goes "Low" level.
PCR (Priority Control Register)
Priority Control Register is a 5-bit register to decide the
operation mode of priority control circuit. Structure of peR is
shown in Table 4.

Table 4 Bit Structure of PCR (Priority Control Register)
Function

Bit
No.

Name

R/W

a

TxRO Enable #0 (TxENo)

R/W

TxRO of Channel

1

TxRO Enable #1 (TxEN 1 )

R/W

TxRO of Channel 1 is accepted.

Tx RO of Channel 1 is not accepted.

2

TxRO Enable #2 (TxEN 2 )

R/W

TxRO of Channel 2 is accepted.

TxRO of Channel 2 is not accepted.

3

TxRO Enable #3 (TxEN 3 )

R/W

TxRO of Channel 3 is accepted.

TxRO of Channel 3 is not accepted.

-

-

-

4

Not used

5
6
7

Rotate Control

"0"

"1"

-

a is accepted.

Rotate Mode

(1) TxRQEnable Bit (TxENo~TxEN3) - PCR Bit 0~3
Each channel has this TxRQ Enable bit. When it is at
"I", TxRQ input of its corresponding channel is accepted
to perform DMA transfer. When it goes to "0", TxRQ of its
corresponding channel is masked not to be received and
TxAK is not output. During DMA transfer operation, when
this bit goes to "0" before BCR becomes "0", following
TxRQ input is not accepted and DMA transfer is interrupted. Then contents of ADR and BCR remain unchanged.
When it rises to "I" again, DMA transfer is reopened.
Therefore, in the case of cycle steal DMA, it is possible for
the program to change the priority of the specific channel
temporarily by manipulating this bit.
(2) Rotate Control Bit - PCR Bit 7
When this bit is at "0", the order of priority among
DMA channels is fixed at numerical order. That is, Channel
o is given a first priority and then is followed by Channel
1-+2-+3.

When this bit is at "1", priority control is due to rotate
mode. That is, the channel that ended in the first time is
given a first priority and the channel ended in the last time
is controlled to be given a last priority.
ICR (Interrupt Control Register)
Interrupt Control Register is a 5-bit register to control IRQ
output. Its structure is shown in Table 5.
(1) IRQ Enable Bit - ICR Bit 0~3
Each channel has IRQ Enable Bit. When this bit is at "1"
and DEND Flag of its corresponding channel is set to "1",
IRQ output goes "Low" level. But when it is at "0", IRQ
output is masked not to be output even if DEND Flag is set
to "1".
These bits enable to control to output only a necessary
channel to IRQ.
(2) IRQ Flag - ICR Bit 7

$

a is not accepted.

-

-

R/W

TxRO of Channel

The order of priority is fixed at
numerical order.

This is a read-only bit and the statu~ IRQ output is
directly reflected on it. That is, when IRQ output goes to
"Low" level, it becomes" I".
IRQ output of DMAC is output as logical OR of 4channel DEND Flag according to the following equation.
IRQ = (DEN Do •IRQ Enableo) + (DEND 1 • IRQ
Enable 1 ) + (DEND2 -IRQ Enable 2) +
(DEND3 -IRQ Enable3)
OCR (Data Chain Control Register)
Data Chain Control Register is a 4-bit register and three of
those bits are used to control data chain function. Remaining
one bit is used to specify 2-channel/4-channel mode.
Structure of DCR is shown in Table 6.
(1) Data Chain Enable Bit - DCR Bit 0
When this bit is at "I", data chain function ofDMAC
is enabled. That is, when DMA transfer of a specified channel has completed and BCR goes to "0", the contents of
ADR and BCR of Channel #3 are automatically transferred
to ADR and BCR of the specified channel.
(2) Data Chain Channel Bit - DCR Bit I ~2
These bits are used to specify which channel should
be used for the data chain. How to specify the channel is
shown in Table 7. Data Chain Channel bit specifies the
channel to which data should be transfered from Channel
#3. Channel #3 contains the data for replacement. Channel
#3 is fixed and cannot be changed.
(3) 2/4-channel Mode Bit - DCR Bit 3
This bit has no relation to the data chain function.
It is used to specify whether CS/TxAKB is used for only
input pin or I/O pin. When this bit is "0", CS/TxAKB becomes CS input pin in 2-channel mode since TxAKB output
is not necessary for application up to 2-channel.
When this bit is "1", CSjTxAKB becomes I/O pin in
4-channel mode (See Fig. 11).

HITACHI

423

HD6844,HD68A44,HD68B44-------------------------------------------------Table 5 ICR (Interrupt Control Register)
Bit
No.

Function

R/W

Name

"0"

"1"

TRO output of Channel

0

I RO Enable #0

R/W

fRO of Channel

1

I RO Enable #1

R/W

I RO of Channel 1 is able to be output.

I RO output of Channel 1 is masked.

2

I RO Enable #2

R/W

IRO of Channel 2 is able to be output.

I RO output of Channel 2 is masked.

3

I RO Enable #3

R/W

IRO of Channel 3 is able to be output.

I RO output of Channel 3 is masked.

-

-

4

5
6
7

-

Not used

fRO output

R

IRO Flag

0 is able to be output.

0 is masked.

-

"Low"

I RO output "High" (off state)

Table 6 Bit Structure of DCR (Data Chain Control Register)
Bit
No.
0
1
2
3

Name
Data Chain Enable
Data Chain Channel
2/4-Channel Mode

4
5

6
7

}

Not used

Function

R/W

"0"

"1"

Data Chain is not performed.
Data Chain is performed.
The channel which performs Data Chain is specified.
(The channel where contents of ADR and BCR of Channel
#3 are loaded.)
2-Channel Mode (CS/TxAKB is
4-Channel Mode (CS/TxAKB is
designated to only input pin.)
I/O pin.)

R/W
R/W
R/W
R/W

-

-

-

-

Table 7 How to specify Data
Chain Channel
OCR
Bit 1

OCR
Bit 2

Specified
Channel

0

0

Channel #0

1

0

Channel #1

0

1

Channel #2

1

1

-

or

r-----r::-

!

I
I

- - - - CS Input

I
I
I

:

cs

(SA of MPU)
Input

~---CS

:
3-state buffer
,:L _____
_

----oc::

I

I

:

~----------------------------In CS input mode T1 turns ON and T2 turns OFF. T1 functions as pull-up resistance.

Figure 11 How to Use CS/TxAKB Pin

424

DGRNT

eHITACHI

•

OPERATION OF THE DMAC

@ When DRQH rises to "High" level, MPU gets into Instruction

•

Transfer Mode of the DMAC

® TxRQ falls to "Low" level.

Cycle again.
There are three DMA transfer modes such as HALT Cycle
Steal, HALT Burst and TSC Cycle Steal. Operation in each
mode is explained in the following.

@) Ao -A 1s and R/W get into high impedance state again.
® DGRNT falls to "Low" level.

HALT Cycle Steal Mode

[Note] TxRQo-TxRQ3 input is, in prinCiple as shown in Fig.
12, set to "High" on account of I/O request. When
TxSTB of the DMAC is driven, it is. reset to "Low".
Take care not to be against this principle, or the following states may happen.
(1) In the case where TxRQ becomes "High", but it
is reset to "Low" before DGRNT becomes "High".
In this case, the DMAC is in the wait state without
sending out TxSTB until TxRQ rises to "High"
again. As DRQH remains "Low" the MPU is forced
to be stopped, and the system is in dead lock state
until TxRQ rises to "High" again (Fig. 14).
(2) In the case where TxRQ is not reset to "Low"
though TxSTB has been driven.
In this case, unless TxRQ returns to "Low" by the
time 2DMA_ When it is at "High" level, it gets into the following
operation.
® DRQH="Low" is output and MPU is requested to stop its
operation.
@ TxAKA is driven (Level output).
@ MPU stops its operation and DMAC waits until DGRNT goes
to "High" level.
@ When DGRNT goes to "High" level, DMAC drives TxAKB,
Ao-A 1s and R/Wlines.
@ TxSTB is given to perform DMA transfer.
CD Address is incremented by one and number of transfer words
is decremented by one.

1------ M P U - - -

DRQH
DGRNT
(MPUBA)

TxAKA
: :

TxAKB
(output)
CS(input)

(input)
00-07 (output)

MPU

x

tTK02

I

I

tATSR~

"

Ao-A1S,R!W

~tTKoi

@

I

N,,'

tAS :-: tAHI
_
______~x~____~Xa_.!__~!~1
r

(output)

Ao-A., R/Vi

I

!:-f. ----I---!oi.......~
I:
'

"
:--l

,Ki

I

tAHO

x

\

® --! ~:®
0 MA

! 1>:

X

MPU

MPU

,MPU'.RE:AO

------------------~~~,~>-----~------. . . .~--------------~!-----'tOOR'

tOHR

I

00-07 (input)
:

~tOEOl

HtOEOl

,·~t
._--- -- - -- -- -- --- -- - - ------ -~~
' . - r - .J

*

-

,

H

t OE01

,..----**

.'

-'
\ ***
'tOE02 OMA END

* fRQ of another channel
or its own IRQ (remaining)

** Its own IRQ (output) or
its own IRQ (remaining)
or IRQ of another channel
This is the last cycle
of transfer

Figure 12 HALT Cycle Steal Mode

$

HITACHI

425

HD6844.HD68A44.HD68B44---------------------------------------------------

Initial State wait
for Programming

Wait for TxRO
Input
Checked
~-----:~--,------~!---,<<=,____-+___M~P~U~____~X~__
H
__________________ ~_h "
, C ____ .J

_____M_p~u__~x~

tOE02

t---:tDEO!

:---; tOED!

tOED!

_ _ _~~ When I RQ is
put out

Figure 17 TSC Cycle Steal Mode

• Priority Control
Basic priority Control
There are two kinds of the DMAC priority control function.
One is to mask TxRQ on each channel by TxRQ Enable bit.
The other is priority-order-determining-Circuit which the DMAC
has as a hardware.
Moreover, the priority-order-detennining-Circuit has two
operation modes (the rotate mode and the nonnal mode).
Structure of the priority control circuit is shown in Fig. 18.
As shown in Fig. 18, TxRQ of the channel whose TxRQ Enable
bit is at "1" level becomes an input of the priority-order-determining-Circuit. Then it is checked whether TxRQ is at "High"
level or not.

$

(Note) In this case, ZERO flag needs to be at "1" level. ZERO
flag will be described later.
If one of TxRQo-TxRQ3 is at "High" level, its channel is
selected, being given a first priority. Then it is latched by an
executing-channel-number-latch-circuit to perform DMA transfer. Once an executing channel is detennined and latched, it is
unchanged until its DMA transfer has been completed. That is,
the channel number strobe signal doesn't go to "I" and the
contents of the channel-number-latch-Circuit are unchanged. In
the cycle steal mode, the channel is fixed until I-byte transfer
has completed. In the burst mode, it is fixed until BCR becomes

"0".

HITACHI

429

HD6844,HD68A44,HD68B44-------------------------------------------------TxRQ Enable Bit of PCR

3

2

Rotate Mode Bit

o

Channel Number Strobe Signal (Synchronous with 1/1 2 )

o

TxRQ.

The channel which is
executing DMA transfer
now becomes "1".
All other lines are
at "O"level.

TxRQ,

2

3

3

2

L

0

(From ZERO Flag)

Executing-Channel-Nu mber
Latch-Circu it

Figure 18 Structure of Priority Control Circuit

Therefore. once a long-period DMA transfer of a channel is
performed in the burst mode, other channels need to wait until
it has completed even if they have higher priority than the channel. Take much care to this point in designing response time to
TxRQ of DMA channel.
(Note) As explained above, TxRQ input is latched internally. So

TxRO. -TxR0 3

once it is accepted and latched, the channel number cannot be
changed even though it returns to "Low". But as explained in
HALT Cycle Steal Mode, DMA transfer is not performed unless
TxRQ rises to "High" again.
Strobe timing of executing-channel-number-Iatch-circuit is
shown in Fig. 19.

______--J!

\_-----------------LJ

~~~~~l -----------------------+I-.------------------~~~~~-----------------------Strobe
possible

Strobe
prohibited
(Channel cannot
be changed.)

L

Strobe
possible
Strobe possible
(But channel under executing
DMA transfer is prohibited.)

Figure 19 Strobe Timing of Executing-Channel-Number-Latch-Circuit (the cycle steal mode)

But, as shown in Fig. 19, only the channel under executing
DMA transfer is prohibited to accept TxRQ during DMA transfer operation, in order that one more byte transfer may not be

430

performed when the reset timing of TxRQ
timing in the burst mode is shown in Fig. 20.

_HITACHI

i~

delayed. Strobe

--------------------------HD6844,HD68A44,HD68B44

- - MPU--j

I-

~

DMA

MPU - - - - -

tP2DMA

TxRO o ~TxR03

~

TxSTB

________~r-\~____~I

LJ

IRO/DEND

Strob.
Grant signal
of executing
channel

1

~I,

Strobe prohibited

Strobe
possible

Strobe possible
(But channel under
executing DMA transfer
is prohibited.)

Figure 20 Strobe Timing of Executing-Channel-Number-Latch-Circuit (the burst mode)

Rotate Mode

There are two operation modes in priority-order-determining
circuit. These are Normal Mode and Rotate Mode. In the normal
mode, the order of priority is fIxed at numerical order. (Channel
o is given a first priority and then is followed by Channel 1 ~ 2
~ 3.) In the rotate mode, the channel next to the channel with

Channel Number

#0

1. Order of Priority
in the reset state

which DMA was executed in the last sequence, is given a fIrst
priority and the channel in the last sequence is given a last
priority. But immediately after it gets into the reset state, the
order of priority is the following: Channel 0 ~ 1 ~ 2 ~ 3.
An example of the rotate mode is shown in Fig. 21.

#1

#2

#3

->2

->3

->4

->4

..... 1

-'>2J

..... 1

->2

->3J

DMA transfer

2. Order of Priority
immediately after
Channel #1 has
performed DMA
transfer

3. Order of Priority
immediately after
Channel #0 has
performed DMA
transfer

r

3

These numerals
show the
order of
priority.

DMA transfer

[

4

Figure 21 Example of Operation in the Rotate Mode

Next, Fig. 22 shows an example of the difference between
the operation in the rotate mode and that in the normal mode.
In this example, TxRQ of all channels is always at "High" level.

Moreover, BCR=2 and TxEN=l are assumed. As a transfer
mode, HALT cycle steal mode is used.

eHITACHI

431

HD6844,HD68A44,HD68B44-------------------------------------------------OMA Switching of Channel

 - - - in the normal mode is that during DMA transfer
operation. TxRQ of an executin'g channel is prohibited from
being accepted.

-+

DMA Operation Timing with priority control

When more than 2 channels perform DMA transfer in parallel, the abovementioned priority-order-determining-circuit is
used to determine the priority. The channel with lower priority
waits until the channel with higher priority completes the
transfer. Then it gets into DMA transfer operation. In this case,
The following combinations of transfer modes are conceivable.
(1) From HALT mode to HALT mode (Fig. 23)
(2) From TSC mode to TSC mode (Fig. 24)
(3) From HALT mode to TSC mOde} (Fi .25)
(4) From TSC mode to HALT mode
g
In changing from HALT mode to HALT mode, only one
dead cycle is intervened. That is, even in the cycle steal mode,
DMA transfer of the next channel is performed without returning the bus control to the MPU (DRQH remains "Low").
In changing from TSC mode to TSC mode, DMA transfer

432

$

of the next channel is performed, after returning the bus control
to MPU for one cycle.
In the case of HALT -+ HALT, it doesn't return the bus control to MPU in order not to increase the response time of DMA
transfer and dead cycles of the system.
On the other hand, in the case of TSC -+ TSC mode, same
mean cannot be applicable because MPU clock cannot remain
stopped for a long time as in the case of HALT mode.
Both in the case of HALT -+ TSC mode and in the case of
TSC -+ HALT mode, DMA operation timing is based on the
same idea as the above two kinds of mode change. (In detail,
see Fig. 25).
The timing in the case where the next byte is transfered without changing the channel is shown in Fig. 26. This is the case of
HALT -+ HALT mode. In this case, the bus control returns to
MPU, before the next byte is transfered. In the case of TSC -+
TSC mode, its timing is almost the same as than in Fig. 24, that
is, after I-byte transfer has completed, MPU executes the
Instruction Cycle for one clock and then DMAC executes I-byte
transfer again.

HITACHI

--------------------------------------------------HD6844,HD68A44,HD68B44
MPU

----II

Dead

rDMAT-DeadT DMA

I

Dead

r-MPU-

1>2DMA

'"

, " .. I

~
________________________

TxRQa
TxRQ/J

,

' I

--J/~----------~------------------~~

DGRNT
(MPU BA)

~

:--1

TxSTB

I

TxAKB

I~----------------

tTKDI

CH13====-,

.--.hKDI

TxAKB
(output)

CCHa

'

g

CH13=:==/

x

x

CS (input)

Ao-AI5. R

i~

CHa

_________

x

/v,

(output)

x

AI5. R / W

Ao(Input)

x

x

>
x

>

IRQ/DEND

Figure 23 Channel Change (HALT Mode --+- HALT Mode)

MPU

MPU

~

____________________

~r-I~

____________________

~

nDMA
TxRQa
,

TxRQP
DRQT

(DGR NT

•

I

,

•

,

,

,

\~

. . . I

•

__________

out~';t ~~ 6PG) ------------.r----------~,t_:

TxAKA
TxAKB
(output)

:~t~

I

I

I

i

CAD

:

CHa!

!
I

,

!7

!"
htATSD

I

(output)

__________--Jr,

I

:
I

CS (input)
Ao-AI5.R/W

_________________J/r-----------------

'-----.V:

TxSTB

Ao-A•• R/W

.\

~~~

-------------+,1,'---<====:;::,

I

CH8
CH8

I

;7

x

I

~~------~---<====:>_-------------

)1+.

__

======~::~>----------~c~::::::::::~!p>>------------«::::=:::::JXC:
~tDEOI C._.J
,~ ______tjtDEDI C._._.7
u

_________

Figure 24 Channel Change (TSC Mode ~ TSC Mode)

$

HITACHI

433

H D 6 8 4 4 , H D 6 8 A 4 4 , H D 6 8 B 4 4 - - - - - - - - - - - - - - - - - - - - - -_ __

D..d

r

TSC

HAL.T
OMA -1

Deed

I

MPU one instruction cycle

Deed j---DMA--i Deed

f----- MPU

-----j

Deed

HAL.T
r-OMA-j Deed

nOMA
nMPU
TxRQo

,.

TxRQP

________

~/r----------------~~

----------~\~

______

__________

~----------------J/~-------

~r---------~--------------------

~CPG~T)---L:..~~~~.~-CPG~.=DGRNT~.~~~~=;.=M~PU.:=BA~.=:~------____~------__--Jlr------------TxSTB
TxAKA

CHo

TxAKB

CHo

!

CHo

CS(input)

A.-AIS. R/W
(output)
A.-A •. R/W
(input)

!-:t"TSO

--<

I>,

. _.J

~ _.~;

IRQ/OEI'i5

C

\.... ________________ ___ J <_._.=-.Y

Figure 25 Channel Change (HALT Mode -)0 TSC Mode -)0 HALT Mode)

~2DMA

TxRQ
ORQH

.Jjj)

f\

/

\

TxSTB

TxAKB

/

/

DGRNT
(BA)

TxAKA

\\\\.,\

'\lEI
\

\

LJ
I

'---l
I

\
\

7

\

\

I

* Executing Period of One Instruction

Figure 26 Successive 2-byte Transfer of One Channel (HALT Cycle Steal Mode)
HALT -)0 HALT (by one channel)

434

~HITACHI

>--

-------------------------HD6844,HD68A44,HD68B44
•

Status Flag

DMAC has BUSY Flag, DEND Flag and ZERO Flag on each
channel. The former two of these flags can be read out by
MPU, but ZERO Flag cannot be read out. Set and reset timing
of each flag are shown in Fig. 27.
BUSY/READY Flag

This flag is set to "1" when it accepts the first-byte TxRQ
of its corresponding channel. After I-block transfer has completed and BCR becomes "0", it is reset to "0". Therefore,
while this flag is "1", that is, its corresponding channel is being
used, the next block transfer cannot be performed.

Also this flag is cleared when corresponding TxRQ Enable
Bit in the PCR becomes "0".
DEND Flag

This is the interrupt flag to indicate the end of DMA transfer of its corresponding channel. After I-block transfer has completed and BCR becomes "0", this flag is set to "1". This flag is
reset to "0" immediately after the Channel Control Register
having this flag is read out.
ZERO Flag

This is the internal flag to indicate whether the data stored in
the BCR is "0" or not (It cannot be read out).

MPU

MPU

ffiQ/~--------------~--------------------~

BUSY/READY - - - - - - - - - '
Flag
~ Flag

----------------------------------4----J

ZERO Flag

MPUWrit.
BCR

\
BCR

MPUR•• d ______________________________________________

CHCR

~rl)

CHCR tha'-t-ha-s-th-e-f-Ia-g
is read out.

Figure 27 Timing of Status Flag (Suppose that BeR is 2 in the initial state)

When BCR is "0", ZERO Flag is "0". When BCR is not "0",
it is "1".
In the reset state, this flag is "0". If data that is not "0" is
written into BCR, this· flag is set to "1". When BCR becomes
"0" after I-block data transfer has completed, or MPU writes
"0" into BCR, this flag is reset to "0" .
The function of ZERO Flag is to prohibit accepting TxRQ
of its corresponding channel while this flag is "0" (that is, BCR
is "0") (See Fig. 18). While ZERO Flag is "0", TxRQ is not
accepted even if TxEN is "1". This function avoids an false
operation even if "High" input is provided to TxRQ before the
initialization of the register.
When RES pin goes to "Low" , this flag becomes "0", but the
number in BCR is not reset to "0". Therefore, the state of this
flag and BCR are not the same. In this case new data should be
written into BCR (Then ZERO Flag becomes" 1").
• DMA End Control
Function of IRQ/DEND Pin

PMAC has IRQ output and DEND output to perform
DMA End Control. These are multiplexed outputs to IRQ/

DENDpin.
The function of DEND output is to inform I/O controller of
the end of I-block transfer. After I·block transfer has been
completed and BCR becomes "0", DEND output provides
"Low" pulse whose cycle is one clock, being synchronous with
the final I-byte data transfer. 4 channels have only one DEND
output in common, so each channel determines whether DEND
output is its own output or not, combining with TxAK signal.
When TxAK of the channel is "Low" and DEND is "Low",
it shows that the cycle is the last one of DMA (See Fig. 29 and
30).
The function of IRQ output is to inform MPU of the end of
I-block transfer by interrupting it. As shown in Fig. 28, IRQ
output is logical AND-OR of the interrupt flag (DEND Flag)
and IRQ Enable bit of each channel.
IRQ and DEND outputs are multiplexed. IRQ/DEND pin is
used as DEND output during DMAC cycle and IRQ output
during MPU cycle. Moreover, DGRNT signal separates DEND
and IRQ by its "High" or "Low". In detail, see Fig. 29 and
Fig. 30.

eHITACHI

435

H D 6 8 4 4 , H D 6 8 A 4 4 , H D 6 8 B 4 4 - - - - - - - - - - - - - - - - - - - - - -_ _

#0
# 1
DE NO Flag
(CHCR Bit 7)

1 0 - - - - IRQ Output

#2

#3#2#1#0

'---v---I
IRQ Enable Bit (PCR Bit 0-3)

Figure 28 Logic of I RQ Output

T.AK

l

#o----------~fiNIl
r::-:-1

=1 ____________________~I

M-II~

______+_----~

OGRNT
(BA)

DEND

J110

In the case where other
channel of DMAC requests IRQ.

llli ----------~--------------------------~
-------+--?-----------------------------------------~--------------

Figure 29 Timing of I ROIDEND Output

436

_HITACHI

-------------------------HD6844,HD68A44,HD68B44

Channel Number
#

'0)

DEND

# 1

# OJ TxAI<
;:0>---4---- # 1

Decoder

Figure 30 How to Use IRQ/DEND Output Signal

Unusual DMA End
Following section describes how to terminate or change
normal sequence of DMA transfer.
(1) When "0" is written into BCR
When "0" is written into BCR before it becomes "0",
subsequent TxRQ are not accepted and this causes the termination of the DMA transfer since the internal ZERO
Flag is reset to "0". In this case, note that DEND pulse is
not provided.
(2) When "I" is written into BCR
When "I", instead of "0", is written into BCR, only the
next TxRQ is accepted and I-byte DMA transfer is performed. In this case, DEND pulse is provided, being synchronous with the last transfer.
(3) When another value is written into ADR & BCR during the
transfer
When the data in ADR & BCR are changed during the transfer, the following transfer is performed according to the
change of the data.
(4) When "0" is written into TxRQ Enable bit
When TxEN is reset to "0" during the transfer, this causes
TxRQ comes not to be accepted and the transfer halts. But
the state is different from that in the case (1), the number
in BCR remains unchanged. Therefore, when TxEN is set to
"1" again, the transfer is performed again.
(5) When RES pin is set to "Low"
When RES is provided during the transfer, the transfer
stops.
Then all of the control registers and their internal flags are
reset to "0". But the data in ADR & BCR are not reset.
(Supplement)
It is only in the cycle steal mode that DMAC registers such as
BCR and ADR can be read or written during the transfer. In the
burst mode, it is usually impossible (But special external circuits
enable it).

• Data Chain Function
The data chain function of DMAC is to transfer the contents
of ADR & BCR of Channel #3 to ADR & BCR of a specified
channel automatically and renew the data of them after the
channel has completed I-block transfer.

ADA

&

(

\1

BCR

#0

#0

# 1

# 1

#2

#2

#3

#3

DCA specifies
the channel to
which the contents
of Channel #3 are
transfered.

~

Channel #3 has addresf
and number of transfer
words for the renewal.

Figure 31 Data Chain Operation

Its detailed timing is shown in Fig. 32 and Fig. 33. As shown
in these figures the contents of ADR & BCR of Channel #3
are transfered to the channel during the clock cycle next to the
last one of I-block transfer (which provides DEND pulse). Then
DRQH or DRQT provides "Low" output for one more clock
cycle than in the normal case_ TherefOl'e, MPU takes back the
bus control again I-clock later than in the normal case, that is,
after the data renewal of the specified channel by the data
chain from Channel #3.
In the TSC mode, the stretching period of clockrJ> 1 is longer
than in the normal case.
The contents of ADR & BCR of Channel #3 remain unchanged as long as new data are not written by MPU, even if
the data chain is executed.
As for DEND output, DEND Flag and BUSY Flag in the case
of data chain execution, they function in the same way as in the
normal case. They provide DEND pulse every time I-block transfer has completed, and then DEND Flag is set to "1". Therefore, in the case where more than 3-block data chain is needed,
DEND Flag is used for the execution. Its sequence is shown in
Fig. 34. First, DEND Flag="I" that shows the end of the firstblock data chain is read out. Next, the data of ADR & BCR for
the third-block data chain need to be written into Channel #3,
in parallel with the execution of the second-block data chain.
(This data chain is feasible only in the cycle steal mode.)

~HITACHI

437

HD6844,HD68A44,HD68B44-------------------------------------------------Cycle under the execution of
Data Chain

' - OM A _ _ _ _ _ _-0/

- - - - - - MPU - - - - - - - - 4

f-

MPU--

+z-OMA

TxRQa

It· • ·7

..

\

t,'

t:'

,~------------------------~----~1
I;

DGRNT
(MPU BA)

\

I

TxAKA
TxAKB

\

(output)

CS

X

(input)

at

,

~

7

\_____>C

I

A,,-A,·,. R W

<

(output)

A,,-A,. R W
(input)

X

>

X

tD£D2

IRQ DENO

1

\

TxSTB

>

i-:

1

____________________________________ u./

''''''_____

~-----,

The contents of ADA & BCA
of Channel #3 are transfered
to Channel Q.

Figure 32 Data Chain Operation (HALT Mode)

--

MPU

---l

I-

Cycle under the execution of
Data Chain
OMA

I"

I

MPU

---

+ZMPU

TxRQa

DRaT

\~

________________~ __- J

DGRNT
(CPG DGRNT)

TxSTB

TxAKA
TxAKB

CS(input)

______

-Jx~

____-'

Ao-A". R W
(output)

Au-A.. R W
(input)

____-Jxc====~---------~----~~========:J~------\\o.___~-,I

IRQ, DEND

The contents of ADR & BCA of
Channel #3 are transfered
to Channel Q.

Figure 33 Data Chain Operation (TSC Mode)

438

$

HITACHI

---------------------------HD6844,HD68A44,HD68B44

TxAK

u

u
DEND Flag

BUSY Flag

Channel #3

:g~)

Write Signal

Read Signal
of CHCR of the
Specified Channel

Figure 34 Sequence of More than 3-block Data Chain

•

DMAC PROGRAMMING

Preparation of a channel for a DMA transfer requires:
1) Load the'starting address into the Address Register.
2) Load the number of bytes into the Byte Count Register.
3) Program the Channel Control Register for the transfer
characteristics: direction (bit 0), mode (bits I and 2), and
the address update (bit 3).
The channel is now configured. To enable the transfer

request, set the appropriate enable bit (bits 0-3) of the Priority
Control Register, as well as the Rotate Control bit.
If an interrupt on DMA End is desired, the enable bit (bits
0-3) of the Interrupt Control Register must be set.
If data chaining for the channel is necessary, it is programmed into the Data Chain Register and the appropriate
data must be written into the Address and Byte Count Registers
for channel #3.

Table 8 DMAC Programming Model
Register

Address
(Hex)

Register Content
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

BitO

TSC/
Halt

Burst/
Steal

Read/Write
(R/W)

TxRQ
Enable #2
(TxEN2)

TxRQ
Enab:? #1
(TxEN1)

TxRQ
Enable #0
(TxENO)

IRQ
Enable #3
(tE3)

IRQ
Enable #2
(tE2)

IRQ
Enable #1
(tE1)

IRQ
Enable #0
(tEO)

Two/Four
Channel
Select (2/4)

Data Chain
Channel
Select B

Data Chain
Cbannel
Select A

Data Chain
Enable

Channel
Control

1x*

DMA End
Flag
(DEND)

Busy/Ready
Flag

Not Used

Not Used

Address
Up/Down

Priority
Control

14

Rotate
Control

Not Used

Not Used

Not Used

TxRQ
Enable #3
(TxEN3)

Interrupt
Control

15

IRQ
Flag

Not Used

Not Used

Not Used

Data Chain

16

Not Used

Not Used

Not Used

Not Used

* The x represents the binary equivalent of the channel desired.

A comparison of the response times and maximum transfer
rates is shown in Table 9. The data are shown for a system
clock rate of 1 MHz.
The two 8-bit bytes that form the registers in Table 10 are
placed in consecutive memory locations, making it very easy to
use the MPU index register in programming them.

Fig. 38 shows an example of its mmunum structure (1
channel, HALT mode, combination with FDC). Fig. 39 shows
an example of its maximum structure. (but only one DMAC is
used.)

eHITACHI

439

HD6844,HD68A44,HD68B44-----------------------_
Table 9 Maximum Transfer Speed & Response Time of the DMAC when tCycl/> equals 1 lisec.
Mode
HALT Cycle Steal
HALT
Burst

Response Time (lisec)

Maximum Transfer
Speed (lisec/byte)

maximum

minimum

(executing time of
one instruction) + 3

(executing time
of one instruction)

3.5+ tTOSl

first byte
since second
byte

+1.5 - tTOHl

1

4

TSC Cycle Steal

2 -tTOH2

1 + tTos2

3.5 - tTOHl

2.5 + tTOHl

rnn (Open Collector)

Table 10 Address and Byte Count Registers
Register

Channel

0
0
0
0

0
1
2

Address High
Address Low
Byte Count High
Byte Count Low

1
1
1
1

4
5

Address High
Address Low
Byte Count High
Byte Count Low

2
2
2
2

8

3
3
3

C

3

F

Address High
Address Low
Byte Count High
Byte Count Low

DENDo

:>0----'---- TxAKo
CS/TxAK
Figure 35 One Channel

i

I

I

Address High
Address Low
Byte Count High
Byte Count Low

IRQ (Open Collector)

Address
(Hex)

3

6

7
9
A
B

0

E

DENDo
DENDI
.----r--L~}-4--+---..

IRQ (Open Collector)

TxAKo
DGRNT

CS

IRQ/DEND

TxSTB

Figure 36 Two Channel

TxAKA~----~~

CS/TxAKBI---.---+--I
(Open
Collector)

1~)-+---+--I---f--TxAK
/o-----~--+---~TxAK

~_;~~------~----~TxAK

~---------~~TxAK

CS
Figure 37 Four-Channel

440

$

HITACHI

----------------------------------------------------HD6844,HD68A44,HD68844

Address Bus
(16)

Data Bus
(8)
1'2

ITII

A.-A"

f---->..

00-0,

HD6800
(MPU)

r-

~

r-- "'I

00-0, HM6810

f--

CS, Ao-A.

R/W

f--

R/W(RAM)

IRQ

f--

-

VMA

SA

f----o'

+5V
3.3kQ

'!.MAiRQ

;::::L>-

HM6810
(RAM)

f--

HALT

\1IzMPU
"'lMPU

t/lzTTL

f---

f--

HD26501
(CPG)

~

1ft

1ft
1ft

OGRNT

I

.l!I

~

bRQH.

~

IRQ

5

Decoder

-

A.-A.
As-A"

11

~

=D-

'---\

00-0,

R/W

CS

HD6843
(FOC)

E
00-0,

--"?"
8

HD6844
(OMAC)

TxSTii

~

TxRQ,

R/W

-

TxAK

-

TxRQ

I--

f---

I--

f---

"-

11 If

RES

CS/TxAKB

Vee
Floppy Disk Drive

Decoder

Vss
n.OMA

Figure 38 Example of DMA System Structure (1) (minimum)

~HITACHI

441

HD6844,HD68A44,HD68B44-----------_ _ _ _ _ _ _ _ _ _ _ __

DB

00-0.

..
,,,.-

I

I

III

,RQ

DB

TTT

"v

t-- I-- f -

;:D-

, ~
IRQ

SA

TSC

I

~

R/W

,..- ,

tlMEM

!V-

VMA

r - - ,

VMA

.~

~

A.-AlS

HD6800
(MPU)

AB

HALT

AB
tlMEM

I - - I-- f t--

HM6810

-

READY
REFRESH REQ
REF GRNT

en
'-- ¢lMPU

:>

I - - IDfo-en
t-- en~
:g
t--

MEM

' - - - QMPU

MRDY
RRQ

c

HD26501
(CPG)
RGRNT

DGANT

ORQ

I-~ .......

~H>

v

I

1·

I--

c

~

EX
r-v

".-

A,-A"

00-0.

r

~

iRCi,DEN6
HD6844
(OMAC)

TxSTB-

TxAKA
RES

Vee
CS/TxAKB
TxRQo-TxRQ3

CJ

~

Ao-A.
DRQT

D

~)

~~

f

Vss

1.1

~

OGRNT

L...-.

1

H>U

I--

TxAK
-

H>-;-p

TxAK

P #0-3

f1.~
-

OMAEND

CS

....

hOMA

t

"l-' ....

~

-- r:D-

~

I--

R/W

~ t-

I - - I--

DB
TxRQ

HITACHI

CONTROLLER HD6B43
(FCC)

E

8

Figure 39 Example of DMA System Structure (2) (maximum)

$

DEVICE

CS

• Open Collector

442

1/0

R/W

HD741!5!5

f-- A

p

I--

etc.

#2

----------------------------------------------------HD6844,HD68A44,HD68B44
• APPENDIX
Contents of the DMAC Registers

(I)ADRO '" ADR3 (Address Register)

(I ADR on each channel)

H

L

16 bit x 4

(2) BCRO '" BCR3 (Byte Count Register)

(I BCR on each channel)

H

I

L

~------~--------~------~~------~.

(3) CHCRO ,..., CHCR3 (Channel Control Register)

16 bit x 4

(I CHCR on each channel) (6 bit x 4)
"1"

"0"

Transfer
Direction

Read

Write

Transfer
Mode

Burst
TSC

Cycle steal
HALT

Address
up/down

-1

+1

B/R

Busy

Ready

DEND

DMA END / NOT END

(4) PCR (priority Control Register)

Control bit

J Status flag

(5 bit x 1)

7

"1"

A

"0"

#0
TxRQ #1
Enable #2

Enable/

Mask

#3
Specify Rotate

(5) ICR (Interrupt Control Register)

(5 bit x 1)

o

7

Rotate / Fixed

"1"

IRQ
#1
Enable #2

"0"

1

#0

Enable / Mask

#3
IAQ Flag

(6) OCR (Data Chain Control Register)

(4 bit xl)

o

7

[:=E

~4/21

IRQ output / NOT IRQ output
Status Flag

"1"
Specify
Data Chain

11

Specify Data
Chain Channel

-

Specify
4/2-Channel
mode

' - - - -]

"0"

Executed / NOT executed
00
1
1 0

o

#3
#3
#3

-+
-+

#0
#1
#2

4-Channel mode / 2-ehannel mode

_HITACHI

443

HD6845S, HD68A45S,--HD68B45S
CRTC

(CRT Controller)

The CRTC is a LSI controller which is designed to provide an
interface for microcomputers to raster scan type CRT displays.
The CRTC belongs to the HMCS6800 LSI Family and has full
compatibility with MPU in both data lines and control lines. Its
primary function is to generate timing signal which is necessaty
for raster scan type CRT display according to the specification
programmed by MPU. The CRTC is also designed as a
programmable controller, so applicable to wide-range CRT
display from small low-functioning character display up to
raster type full graphic display as well as large high-functioning
limited graphic display.
•
•

FEATURES
Number of Displayed Characters on the Screen, Vertical
Dot Format of One Character, Horizontal and Vertical
Sync Signal, Display Timing Signal are Programmable

HD6845SP, HD68A45SP, HD68845SP

(DP-40)

•

PIN ARRANGEMENT
Vss

•
•
•

3.7 MHz High Speed Display Operation
line Buffer·less Refreshing
14-bit Refresh Memory Address Output (16k Words
max. Access)
• Programmable Interlace/Non-interlace Scan Mode
• Built-in Cursor Control Function
• Programmable Cursor Height and its Blink
• Built-in light Pen Detection Function
• Paging and Scrolling Capability
•
•

ms

VSYNC

0

HSYNC

LPSTB

RA.
RA,

MA.
MA,
MA,

RA,
RA,

MA,

RA.

MA.

O.
0,

MA,

HD6845S

0,
0,

o.
0,

TTL Compatible
Single +5V Power Supply

D.
D,

cs
• SYSTEM BLOCK DIAGRAM

RS

E

I - - - r - - - - - - r - - - - - - :~~~:.BUS

RNi

1-----+-.------+---..----- Data Bu.,
0 0 -0

(Top View)

•

ORDERING INFORMATION
CRTC
HD6845S

444

Bus Timing
1.0 MHz

HD68A45S

1.5 MHz

HD68B45S

2.0 MHz

~HITACHI

CRT Display
Timing
3.7 MHz max.

-----------------------------------------------HD6845S,HD68A45S,HD68B45S
•

ABSOLUTE MAXIMUM RATINGS
Item

Symbol
Vee *

Supply Voltage

Vin *
Topr
Tstg

Input Voltage
Operating Temperature

Value

Unit

-0.3- +7.0

V

-0.3 - +7.0

V
°c

- 20 - + 75

·

Storage Temperature
°c
- 55- +150
With respect to Vss (SYSTEM GND)
[NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded, it could affect reliability of LSI.

•

RECOMMENDED OPERATING CONDITIONS
Item

min

typ

max

Unit

4.75

5.0

5.25

V

V 1L *
V 1H *

-0.3

-

0.8

V

Topr

- 20

Vee
75

V
°c

Symbol
Vee *

Supply Voltage
Input Voltage
Operating Temperature

2.0

25

• With respect to Vss (SYSTEM GND)

•

ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vee = 5V ± 5%, Vss = OV, Ta = -20-+75°C, unless otherwise noted.)
typ*

max

Unit

Input "High" Voltage

V 1H

2.0

-

V

Input "Low" Voltage

V 1L

-0.3

-

Vee
0.8

Input Leakage Current

I in

-2.5

-

2.5

p.A

Three·State Input Current
(off-state)

ITS1

- 10

-

10

p.A

Output "High" Voltage

V OH

2.4

-

V

Output "Low" Voltage

VOL

-

10.0

pF

10.0

pF

600

1000

mW

Item

Input Capacitance

Symbol

Cin

Output Capacitance

Cout

Power Dissipation

Po

Test Condition

min

Vin = 0 - 5.25V (Except 0 0 -0 7 )
V in = 0.4 - 2.4V
Vee = 5.25V (0 0 - 0 7 )
I LOAD = -205p.A (0 0 - 0 7 )
I LOAD = -100 p.A (Other Outputs)
ILOAD = 1.6 mA
V in = 0
Ta = 25°C
f = 1.0 MHz

I

I

Do -

D7

Other Inputs

Vln =OV, Ta = 25°C, f= 1.0 MHz

-

V

0.4

V

12.5

pF

* Ta = 25°C, Vee = 5.0V

$

HITACHI

445

HD6845S,HD68A45S,HD68B45S~----------------------------------------------

•

AC CHARACTERISTICS (Vee = 5V ±5%, Vss .. OV, Ta .. _20-+75°C, unless otherwise noted.)

1. TIMING OF CRTC SIGNAL
min

typ

max

Clock Cycle Time

tcvcC

270

-

-

ns

Clock "High" Pulse Width

PWCH

130

PWCL

130

-

ns

Clock "Low" Pulse Width

-

ns

Rise and Fall Time for Clock Input

tCr, tCf

ns

160

ns

Raster Address Delay Time

tMAO
t RAO

-

20

Memory Address Delay Time

-

160

ns

DISPTMG Delay Time

tOTO

-

-

250

ns

CUDISP Delay Time

tcoo

-

250

ns

Horizontal Sync Delay Time

tHSO

200

ns

Vertical Sync Delay Time

-

250

ns

Light Pen Strobe Pulse Width

tvso
PW LPH

-

-

60

-

-

ns

Light Pen Strobe

t LP01

-

-

70

ns

Uncertain Time of Acceptance

t LPo2

-

-

0

ns

Item

Symbol

Test Condition

Fig. 1

Fig. 2

Unit

2. MPU READ TIMING
Item

Symbol

Test
Condition

HD6845S
min

min

typ

max

-

0.666

-

-

0.5

0.28

-

0.22

0.28

-

-

0.21

25

-

25

t cVCE
PW EH

1.0

-

0.45

Enable "Low" Pulse Width

PWEL

0.40

Enable Rise and Fall Time

tEr, tEf

Address Set Up Time

tAs

-

Data Delay Time

tOOR

-

Data Hold Time

tH

10

Address Hold Time

tAH

10

Data Access Time

tAcc

-

Fig.3

140

HD68845S

max

Enable "High" Pulse Width

Enable Cycle Time

HD68A45S

typ

Unit

typ

max

-

-

-

-

25

IJS
ns

-

ns

180

ns
ns
ns

min

-

140

-

-

70

-

320

-

-

220

-

-

10

-

10

-

-

10

-

-

-

10

-

-

460

-

-

360

-

-

250

typ

max

min

typ

max

min

0.666

-

-

0.21

IJS

IJS

ns

3. MPU WRITE TIMING
Item

Symbol

Test
Condition

HD68A45S

HD6845S
min

Enable Cycle Time

tCYCE

Enable "High" Pulse Width

PW EH

0.45

-

Enable "Low" Pulse Width

PW EL

0.40

-

-

Enable Rise and Fall Time

tEr, tEf

Address Set Up Time

t AS

Data Set Up Time

tosw

Data Hold Time

tH

Address Hold Time

tAH

446

1.0

Fig. 4

0.28
0.28

-

-

25

-

140

-

140

195

-

-

10

-

-

10

10

-

-

10

_HITACHI

80

-

HD68845S
typ

max

0.5

-

0.22

-

-

25

-

-

70

-

60

-

10

10

-

25

Unit

IJS
IJS
IJS
ns

-

ns

-

ns
ns
ns

-----------------------------------------------HD6845S,HD68A45S,HD68B45S

2.0V

2.0V

o.sv
PW CH
tCr

tCf

2.4V

MAo-MAil ------------+--~

2.4V

RAo-RA.

------------~--~

2.4V

DISPTMG

tOTO
2.4V

CUDISP
tCDD

tCDD

2.4V

HSYNC
VSYNC

LPSTB _________

J~~;-.O-V-----------P-W-L-P-H--------~~------------------------

__

This Figure shows the relation in time between
CLK signal and each output signals. Output
sequence is shown in Figs. 10-15.

Figure 1 Time Chart of the CRTC

$

HITACHI

447

HD6845S,HD68A45S,HD68B45S-----------------------------------------------

elK

MAo-MAI3

M

lPSTB

M +2

M+1

\

O.8V

l·

2.0V
lPSTB

L

~(' When

lPSTB rises in this periOd,)'
Refresh Memory Address "M+2"
is set into the light pen registers. ,

tLPD1, tLPD2: lPSTB's uncertain time of acceptance.

Figure 2 LPSTB Input Timing & Refresh Memo.ry Address that is set into the light pen registers.

~-----------t~E ------------.~

E -------10----11

cs-----.
R/Vii, RS _ _ _ _oJ

t

2.4V
0 0 -0 7
O.4V

--ItE

----'

:V
_ _ _ _ _ _ _ _ _ _ _ __

O.4V

Figure 3 Read Sequence

448

$

HITACHI

~~~~~~~~~~~~~~~~~~~~~~~~HD6845S.HD68A45S.HD68B45S

f-o------tcycE - - - - - - - . . !

E------4--....J

cs----'""
R/iiii
RS (Address
Register)

RS _ _ _ _.J

tosw
2.0V

o.sv

(Control Registers)

Figure 4 Write Sequence

s.ov
RL =2.4kn

Test Point

cr---.>---..---~--.

C = 130pF (Do -0 , )
30pF (Output signals except Do - 0,)
R = llkn (Do -0,)
= 24kn (Output signals except Do - 0,)
0, -0. are lS2074~or equivalent.

O2
0,

D.

Figure 5 Test Loads

• SYSTEM DESCRIPTION

The CRTC is a LSI which is connected with MPU and CRT
display device to control CRT display. The CRTC consists of
internal register group, horizontal and vertical timing circuits,
linear address generator, cursor control circuit, and light pen
detection circuit. Horizontal and vertical timing circuit generate
RAo-~, DISPTMG, HSYNC, and VSYNC. RA o-RA 4 are
raster address signals and used as input signals for Character
Generator. DISPTMG, HSYNC, and VSYNC signals are received
by video control circuit. This horizontal and vertical timing
circuit consists of internal counter and comparator circuit.

Linear address generator generates refresh memory address MAo
-MA 13 to be used for refreshing the screen. By these address
signals, refresh memory is accessed periodically. As 14 refresh
memory address signals are prepared, 16k words max are
accessible. Moreover, the use of start address register enables
paging and scrolling. Light pen detection circuit detects light
pen position on the screen. When light pen strobe signal is
received, light pen register memorizes linear address generated
by linear address generator in order to memorize where light
pen is on the screen. Cursor control circuit controls the position
of cursor, its height, and its blink.

eHITACHI

449

HD6845S,HD68A45S,HD68B45S----------------------------------------------Vee Vss

E

RES

i--+-t-+-t--+-~

CS RS 0,,-0,

-- - -

Horizontal Displayed
Register

ClK -+__.-.;

Horizontal Total
Register

Horizontal Sync
Position Register
HSYNC
Sync
Width Register

Maximum Raster
Address Register

Vertical Displayed
Register

Vertical Total
Register

Vertical Total Adjust
Register
DISPTMG
Vertical Sync
Position Register

Start Address
Registers

Cursor Start
Raster Register
CUDISP
Cursor End
Raster Register

Cursor Registers
VSYNC
Interlace & Skew
Register

LPSTB--f---------; 1 - - - - - - - - - 1

-------

Figure 6 Internal Block Diagram of the CRTC

450

eHITACHI

-------------------------------------------------HD6845S,HD68A45S,HD68B45S
• FUNCTION OF SIGNAL LINE
The CRTC provides 13 interface signals to MPU and 25
interface signals to CRT display.
• Interface Signals to MPU
Bi-directional Data Bus (0 0 -0 7 )
Bi-directional data bus(Do -D 7 ) are used for data transfer
between the CRTC and MPU. The data bus outputs are 3-state
buffers and remain in the high-impedance state except when
MPU performs a CRTC read operation.
Read/Write (RtW)
Read/Write signal (R/W) controls the direction of data
transfer between the CRTC and MPU. When R/W is at "High"
level, data of CRTC is transfered to MPU. When R/W is at
"Low" level, data ofMPU is transfered to CRTC.
Chip Select (CS)
Chip Select signal (CS) is used to address the CRTC. When
CS is at "Low" level, it enables Read/Write operation to CRTC
internal registers. Normally this signal is derived from decoded
address signal of MPU under the condition that VMA of MPU
is at "High" level.
Register Select (RS)
Register Select signal (RS) is used to select the address
register and 18 control registers of the CRTC. When RS is at
"Low" level, the address register is selected and when RS is at
"High" level, control registers are selected. This signal is
normally a derivative of the lowest bit (AO) of MPU address bus.
Eni\ble(E)
Enable signal (E) is used as strobe signal in MPU Read/Write
operation witt. the CRTC internal registers. This signal is
normally a derivative of the HMCS6800 System 1/>2 clock.
Reset (RES)
Reset signal (RES) is an input signal used to reset the CRTC.
When RES is at "Low" level, it forces the CRTC into the
following status.
1) All the counters in the CRTC are cleared and the device
stops the display operation.
2) All the outputs go down to "Low" level.
3) Control registers in the CRTC are not affected and remain
unchanged.
This signal is different from other HMCS6800 family LSIs in the
following functions and has restrictions for usage.
I) RES has capability of reset function only when LPSTB
is at "Low" level.
2) The CRTC starts the display operation immediately after
RES goes "High" level.

• Interface Signals to CRT Display Device
Character Clock (ClK)
CLK is a standard clock input signal which defines character
timing for the CRTC display operation. CLK is normally derived
from the external high-speed dot timing logic .
Horizontal Sync (HSYNC)
HSYNC is an active "High" level signal which provides
horizontal synchronization for display device.
Vertical Sync (VSYNC)
VSYNC is an active "High" level signal which provides vertical synchronization for display device.
Display Timing (DISPTMG)
DISPTMG is an active "High" level signal which defines the
display period in horizontal and vertical raster scanning. It is
necessary to enable video signal only when DISPTMG is at
"High" level.
Refresh Memory Address (MAo -MA 13 )
MA o-MA I3 are refresh memory address signals which are
used to access to refresh memory in order to refresh the CRT
screen periodically. These outputs enables 16k words max.
refresh memory access. So, for instance, these are applicable up
to 2000 characters/screen and 8-page system.
Raster Address (RA o-RA 4 )
RA o-RA 4 are raster address signals which are used to select
the raster of the character generator or graphic pattern
generator etc.
Cursor Display (CUDISP)
CUDISP is an active "High" level video signal which is used
to display the cursor on the CRT screen. This output is inhibited while DISPfMG is at "Low" level. Normally this output
is mixed with video signal and provided to the CRT display
device.
Light Pen Strobe (lPSTB)
LPSTB is an active "High" level input signal which accepts
strobe pulse detected by the light pen and control circuit. When
this signal is activated, the refresh memory address (MAo"""
MA I3 ) which are shown in Fig. 2 are stored in the 14-bit light
pen ,register. The stored refresh memory address need to be
corrected in software, taking the delay time of the display
device, light pen, and light pen control circuits into account.

_HITACHI

451

HD6845S,H068A45S,HD68B45S

•

REGISTER DESCRIPTION

Table 1 Internal Registers Assignment
Register

CS

Register Name

Program Unit

READ

WRITE

#

X

0

Character

X

0

Horizontal Displayed

Character

X

0

R2

Horizontal Sync·
Position

Character

X

0

0

R3

Sync Width

Vertical-Raster,
HorizontalCharacter

X

0

0

R4

Vertical Total •

Line

X

0

0

R5

Vertical Total Adjust

Raster

X

0

0

R6

Vertical Displayed

Line

X

0

0

R7

Vertical Sync·
Position

Line

X

0

0

RS

Interlace & Skew

X

0

0

R9

Maximum Raster
Address

Raster

X

0

0

Rl0

Cursor Start Raster

Raster

X

0

0

Rll

Cursor End Raster

Raster

X

0

0

R12

Start Address( H)

0

0

0

R13

Start Address( L)

0

0

0

R14

CursodH)

0

0

0

R15

Cursor (L)

0

0

0

R16

Light Pen(H)

0

X

0

R17

Light Pen( L)

0

X

0

AR

Address Register

0

RO

Horizontal Total •

0

Rl

0

[NOTE]

1_ The Registers marked·: (Written Value) = (Specified Value) - 1

2. Written Value of R9 is mentioned below.

3.
4.

5.
6.
7.

452

1) Non-interlace Mode } (Written Value) = (Specified Value) - 1
I nterlace Sync Mode
2) Interlace Sync & Video Mode
(Written Value) = (Specified Value) -2
CO and C1 specify skew of CUDISP.
DO and 01 specify skew of DISPTMG.
When Sis "1", V specifies video mode. S specifies the Interlace Sync Mode.
B specifies the cursor blink. P specifies the cursor blink period.
wvO-wv3 specify the pulse width of Vertical Sync Signal.
whO-wh3 specify the pulse width of Horizontal Sync Signal.
RO is ordinally programmed to be odd number in interlace mode.
0; Yes, X; No

~HITACHI

wv3

wv2

wvl

wvO

wh3

wh2

wh1

whO

V

S

-------------------------------------------------HD6845S,HD68A45S,HD68B45S
•

Table 2 Pulse Width of Vertical Sync Signal

FUNCTION OF INTERNAL REGISTERS

• Address Register (AR)
This is a 5·bit register used to select 18 internal control
registers (RD-RI7). Its contents are the address of one of 18
internal control registers. Programming the data from 18 to 31
produces no results. Access to RO-R 17 requires, first of all, to
write the address of corresponding control register into this
register. When RS and CS are at "Low" level, this register is
selected.
•

Horizontal Total Register (RO)
This is a register used to program total number of horizontal
characters per line including the retrace period. The data is 8·bit
and its value should be programmed according to the specifl·
cation of the CRT. When M is total number of characters,M·I
shall be programmed to this register. When programming for
interlace mode, M must be even.

•

Horizontal Displayed Register (R 1)
This is a register used to program the number of horizontal
displayed characters per line. Data is 8·bit and any number that
is smaller than that of horizontal total characters can be
programmed.

• Horizontal Sync Position Register (R2)
This is a register used to program horizontal sync position as
multiples of the character clock period. Data is 8·bit and any
number that is lower than the horizontal total number can be
programmed. When H is character number of horizontal Sync
Position. H·I shall be programmed to this register. When pro·
grammed value of this register is increased, the display position
on the CRT screen is shifted to the left. When programmed
value is decreased, the position is shifted to the right. Therefore,
the optimum horizontal position can be determined by this
value.
• Sync Width Register (R3)
This is a register used to program the horizontal sync pulse
width and the vertical sync pulse width. The horizontal sync
pulse width is programmed in the lower 4-bit as multiples of the
character clock period. "0" can't be programmed. The vertical
sync pulse width is programmed in higher 4-bit as multiples
of the raster period. When "0" is programmed in higher 4-bit,
16 raster period (J 6H) is specified.
• Vertical Total Register (R4)
This is a register used to program total number of lines per
frame including vertical retrace period. The data is within 7·bit
and its value should be programmed according to the specification of the CRTC. When N is total number of lines, N·l shall
be programmed to this register.
• Vertical Total Adjust Register (R5)
This is a register used to program the optimum number to
adjust total number of rasters per field. This register enables to
decide the number of vertical deflection frequency more
strictly.

VSW

Pulse Width

2'

26

25

24

0

0

0

0

0

0

0

1

1

0

0

1

0

2

0

0

1

1

3

0

1

0

0

4

0

1

1

5

0

1

0
1
1
0
0
1
1
0
0
1
1

0

6

0

1

1

0

1

0

1

0

1

0

1

1

1

1

1

1

1

1

16H

1

7

0
1

8
9

0

10

1

11

0

12

1

13

0

14

1

15

H; Raster period

Table 3 Pulse Width of Horizontal Sync Signal
HSW
23

22

21

20

Pulse Width

0

0

0

0

0

0

0

1

1 CH

0

0

1

0

2

0

0

1

1

3

0

1

0

0

4

0

1

0

1

5

0

1

1

0

6

- (Note)

0

1

1

1

7

1

0

0

0

1

0

0

1

0

1

1

0

1

1

1

0

1
0
1
0
1
0
1

8
9

1

1

0

1

1

1

1

1

1

10
11
12
13
14
15

CH; Character clock period
(Notel HSW = "0" can't be used.

• Vertical Displayed Register (R6)
This is a register used to program the number of displayed
character rows on the CRT screen. Data is 7·bit and any number
that is smaller than that of vertical total characters can be
programmed.

$

HITACHI

453

HD6845S,HD68A45S,HD68845S----------------------------------------------• Vertical Sync Position Register (R7)
This is a register used to program the vertical sync position
on the screen as mUltiples of the horizontal character line peri·
od. Data is 7·bit and any number that is equal to or less than
vertical total characters can be programmed. When V is charac·
ter number of vertical sync position, V·I shall be programmed
to this register. When programmed value of this register is in·
creased, the display position is shifted up. When programmed
value is decreased, the position is shifted down. Therefore, the
optimum vertical position may be determined by this value.
•

Interlace and Skew Register (RS)
This is a register used to program raster scan mode and skew
(delay)ofCUDISP and DISPTMG.
Raster Scan Mode Program Bit (V, S)
Raster scan mode is programmed in the V, S bit.
'\

S

0

0
0

1

0

•

Maximum Raster Address Register (R9)
This is a register used to program maximum raster address
within 5·bit. This register defines total number of rasters per
character including line space. This register is programmed as
follows.
Non·interlace Mode, Interlace Sync Mode
When total number of rasters is RN, RN·l shall be pro·
grammed.
Interlace Sync & Video Mode
When total number of rasters is RN, RN·2 shall be pro·
grammed.
This manual defines total number of rasters in non·interlace
mode, interlace sync mode and interlace sync & video mode as
follows:

Table 4 Raster Scan Mode (2 1 , 2°)
V

Skew function is used to delay the output timing of
CUDISP and DISPTMG in LSI for the time to access refresh
memory, character generator or pattern generator, and to
make the same phase with serial video signal.

Raster Scan Mode

Non·interlace Mode
0-----Total Number of Rasters:5
Programmed Value: Nr =4
The same as displayed
(
total number of rasters
3------

} Non·interlace Mode
Interlace Sync Mode
Interlace Sync & Video Mode

l

4-----

Raster Address
In the non·interlace mode, the rasters of even number
field and odd number field are scanned duplicatedly. In the
interlace sync mode, the rasters of odd number field are
scanned in the middle of even number field. Then it is
controlled to display the same character pattern in two
fields. In the interlace sync & video mode, the raster scan
method is the same as the interlace sync mode, but it is
controlled to display different character pattern in two field.
Skew Program Bit (C1, CO, 01, DO)
These are used to program the skew (delay) of CUDISP
and DISPTMG.
Skew of these two kinds of signals are programmed
separately.

Interlace Sync Mode
Total Number of Rasters:5
0-----...•••••••••.. 0 Programmed Value: Nr = 4

1------

.............. I

In the interlace sync mode, )
total number of rasters in
both the even and odd fields
is ten. On programming,
( the half of it is defined as
total number of rasters.

2-----

•••••••••••••• 2
3-----•••••........• 3

4------

•••••••••••••• 4

Raster Address

Interlace Sync & Video Mode
Total Number of Rasters:5
Programmed Value: Nr =3
2----Total number of rasters )
4----( displayed in the even field
Raster Address
and the odd field.
0-----

-.-- . -------

Table 5 DISPTMG Skew Bit (2 5 , 24)
01

DO

o
o

o

Non·skew

1

One·character skew
Two·character skew
Non·output

o

Table 6 CUDISP Skew Bit (2
C1

CO

0
0

0

• Cursor Start Raster Register (R10)
This is a register used to program the cursor start raster
address by lower 5·bit (2° _24 ) and the cursor display mode by
higher 2-bit (2 5 , 2 6 ).

DISPTMG

7

Table 7 Cursor Display Mode (2 6 , 25 )

, 26 )

Non·blink

1

Cursor Non·display

0

Blink 16 Field Period

Cursor Display Mode

Blink 32 Field Period

Non·skew
Blink Period

light

Two·character skew

dark

~~-------v-------------~

Non·output

454

P

0

CUDISP

One·character skew

0

B

0
0

16 or 32 Field Period

$

HITACHI

•

-------------------------------------------------HD6845S,HD68A45S,HD68B45S
• Cursor End Raster Register (R11)
This is register used to program the cursor end raster address.

6) 2 ~ Nr ~ 30 (Interlace Sync &0 Video mode)
7) 3 ~ Nht (Except non-interlace mode)
5 ~ Nht (Non-interlace mode only)

• Start Address Register (R12, R 13)
These are used to program the first address of refresh
memory to read out.
Paging and scrolling is easily performed using this register.
7
This register can be read but the higher 2-bit (2 6 ,2 ) ofRI2 are
always "0".

'"

• Cursor Register (R14, R15)
These two read/write registers stores the cursor location. The
higher 2-bit (2 6 ,2 7) of RI4 are always "0".
•

light Pen Register (R16, R17)
These read only registers are used to catch the detection
address of the light pen. The higher 2-bit (2 6 , 27) of RI6 are
always "0". Its value needs to be corrected by software because
there is time delay from address output of the CRTC to signal
input LPSTB pin of the CRTC in the process that raster is lit
after address output and light pen detects it. Moreover, delay
time shown in Fig. 2 needs to be taken into account.

Restriction on Programming Internal Register
1) O

-0

"tl
~

~A~ ~B~ ~C

co
co

()

11

~

~
is

I

"l3
"t ~

0

~~

"l3

'0

I-

"-e

1l

'0

2

~

E
:>

Display Period

'"

~

.c

()

.c
'"
E
:>

2

r---

Vertical Retrace Period

VertIcal Total Adjust (NadJ}

Figure 7 CRT Screen Format

$

HITACHI

455

HD6845S,HD68A45S,HD68B45S;----------------------------------------------Table 8 Programmed Values into the Registers
Register

Register Name

Value

Register

RO

Horizontal Total

Nht

Rl

Horizontal Displayed

Nhd

R9
Rl0

Cursor Start Raster

Rll

Cursor End Raster

R2

Horizontal Sync Position

R3

Sync Width

R4

Vertical Total

Nvt

R5

Vertical Total Adjust

R6

Vertical Displayed

R7

Vertical Sync Position

R8

Interlace & Skew

[NOTE)

Nhsp
Nvsw, Nhsw

Register Name

Nr

R12

Start Address (H)

0

R13

Start Address (L)

0

Nadj

R14

Cursor (H)

Nvd

R15

Cursor (L)

Nvsp

R16

Light Pen (H)

R17

Light Pen (L)

I

Nhd
~

(J1

!!'
:J:
C

en

(X)

OJ
.j:>.

~

~

(J)

(J1

~
I\)

J:

o0)
CD
~

01

!"
J:
o
0)

CD

---'I
UM'_~ (

Raster address

Horizontal Display Period

tN.
0

[

Nhd

Nhd+l

r

Nhd

Nhd+l

C

2Nhd

2Nhd+l

.

>-

2Nhd

2Nhd+ 1

2

0

~
o

!

t

'f--

o

el:

I

I

"&

t

•
t

r

]
~

I

JI~ ~

1

I

:

:

:

r INvd-l)·Nhd Nvd-l)'Nhd+'

~ I {J
Nvd

I

Nvd·Nhd

Nvd·Nhd+ 1

r

Nvd·Nhd

Nvd·Nhd+'

:

t

~

I)~ !

II:

1i
u

't:

~

Nvt

{O';I

Nvt·Nhd

N,r

Nvt·Nhd

t

---

--

1
NY! ·Nhd+l

t

Nvt ·Nhd+l

'INvt+l).Nhd Nvt+lfhd+

t

---

1

I INvd-l)-Nhd NVd-llfhd+'
NVd-l{N

--

Nadj- I INvt+l)·Nhd Nvt+l).Nhd+

--

-

»
~

Horizontal Retrace Period

\I
Nhd-l

Nhd

Nhd-l
2Nhd-l

*

*
2Nhd

2Nhd-l

2Nhd

3Nhd-1

3Nhd

3Nhd-'

3Nhd

1

1

t

:

Nhd

:

t

Nvd-Nhd-l

Nvd-Nhd

Nvd·Nhd·l

Nvd·Nhd

t

:

INvd+')Nhd-' INvd+1)Nhd

t

:

!

!

INvd+' )Nhd-l INvd+l)Nhd

INvt+ ')Nhd-'

INvt+ !)Nhd

INvt+!)Nhd-!

INvt+l)Nhd

t

t

INvt+2)Nhd-l INvt+2)·Nhd

:

t

INvt+ 2)Nhd·l INvt+2)-Nhd

--

--

\

C1I

!"

Nht

J:

t

o

Nht
Nhd+Nht

0)

CD

:

aJ

2Nhd+Nht

en

~

Nhd+Nht

C1I

t

2Nhd+Nht

1
INvd·U·Nhd+Nh'
--+

:

(Nvd·1)·Nhd+Nht

--

Nvd-Nhd+Nht

t

Nvd·Nhd+Nht

1

---

Nvt·Nhd+Nht

t

Nvt·Nhd+Nht
(Nvt+l}Nhd+NhC

*

INvt+1JNhd+Nht

Figure 16 Refresh Memory Address (MA o -MA 13 )

Valid refresh memory address (O-NvdoNhd-ll
are shown within the thick-line square.
Refresh memory address are provided even
during horizontal and Vertical retrace period.
This is an example in the case where the
programmed value of start address register is O.

-------------------------------------------------HD6845S,H D68A45S, HD68B45S
•

How to Use the CRTC

•

Interface to MPU
As shown in Fig. 17, the CRTC is connected with the standard bus of MPU to control the data transfer between them. The
CRTC address is determined by CS and RS, and the Read/Write
operation is controlled by R/W and E. When CS is "Low"
and RS is also "Low", the CRTC address register is selected.
When ES is "Low" and RS is "High", one of 18 internal regis-

ters is selected.
RES is the system reset signal. When RES becomes "Low",
the CRTC internal control logic is reset. But internal registers
shown in Table 1 (RO- R17) are not affected by RES and remain unchanged.
The CRTC is designed so as to provide an interface to microcomputers, but adding some external circuits enables an interface to other data sources_

Ao -- A15

RS

OECQOER

VMA

cs
RtW

R/W

CRTC

HD6800
MPU

E

00 -- 07

0 0 -0 7

REs

RES

Sy stem rP, clock
RES

Figure 17 Interface to MPU

•

Dot Timing Generating Circuit
CRTC's CLK input (21 pin) is provided with CLK which
defines horizontal character time period from the outside.
This CLK is generated by dot counter shown in Fig. 18. Fig.
18 shows a example of circuit where horizontal dot number
of the character is "9". Fig. 19 shows the operation time chart

L.-_~""-'

of dot counter shown in Fig. 18. As this example shows explicitly, CLK is at "Low" level in the former half of horizontal
character time and at "High" level in the latter half. It is necessary to be careful so as not to mistake this polarity.

___ lOAD PIS REG-N
}

to PIS SHI FT
REGISTER

L----------+----------------DOTCP-P

L-_ _ _ _ _ _ _ _ CHCP-P to CRTC (ClK)

Figure 18 Example of Dot COj.H1ter

_HITACHI

463

HD68455,HD68A455,HD68B455------------------------

6780123456780

2

3

4

7

o

DOTCP-P

a.

0.,-----,

.....-+----_...1

lOAD PIS REG-N

CHCP-P (ClK)

I-----One Horizontal-----I
Character Time

Figure 19 Time Chart of Dot Counter

• INTERFACE TO DISPLAY CONTROL UNIT
Fig. 20 shows the interface between the CRTC and display
control unit. Display control unit is mainly composed of
Refresh Memory, Character Generator, and Video Control
circuit. For refresh memory, 14 Memory Address line
(0-16383) max are provided and for character generator,S
Raster Address line (0-31) max are provided. For video control
circuit, DISPTMG, CUDISP, HSYNC, and VSYNC are sent
out. DISPTMG is used to control the blank period of video
signal. CUDISP is used as video signal to display the cursor on
the CRT screen. Moreover, HSYNC and VSYNC are used as
drive signals respectively for CRT horizontal and vertical deflection circuits.
Outputs from video control circuit, (video signals and sync
signals) are provided to CRT display unit to control the
deflection and brightness of CRT, thus characters are displayed
on the screen.

464

Fig. 21 shows detailed block diagram of display control unit.
This shows how to use CUDISP and DISPTMG. CUDISP and
DISPTMG should be used being latched at least one time
at external flip-flop FI and F2. Flip-flop FI and F2 function
to make one-character delay time so as to synchronize them
with video signal from parallel-serial converter. High-speed
D type flip-flop as TTL is used for this purpose. After being
delayed at F I and F2 DISPTMG is AND-ed with character
video signal, and CUDISP is Or-ed with output from AND
gate. By using this circuitry, blanking of horizontal and vertical
retrace time is controlled. And cursor video is mixed with
character video signal.
Fig. 21 shows the example in the case that both refresh
memory and Character Generator can be accessed for horizontal
one character time. Time chart for this case is shown in Fig. 24.
This method is used when a few character needed to be displayed in horizontal direction on the screen.

_HITACHI

~~~~~~~~~~~~~~~~~~~~~~~~HD6845S.HD68A45S.HD68B45S

14 max

Refresh
Memory

5 max

Character
Generator

MA

RA

II

CRTe

II

DISPTMG

Video
Signals

CUDISP
HSYNC
CLK

Video Control

VSYNC

Sync
Signals

D
0

I

0

I
Figure 20 Interface to Display Control Unit

F1
CUDISP
CHCP-N

F2

DISPTMG

VIDEO

CRTC
MA

P
Refresh
Memory

Character
Generator

~

S

RA
CLK
CHCP-P

DOT COUNTER

Figure 21 Display Control Unit (1)

_HITACHI

465

HD6845S,HD68A45S,HD68B45S----------------------------------------------When many characters are displayed in horizontal direction
on the screen, and horizontal one-character time is so short
that both refresh memory and Character Generator cannot be
accessed, the circuitry shown in Fig. 22 should be used. In this
case refresh memory output shall be latched and Character
Generator shall be accessed at the next cycle. The time chart
in this case is shown in Fig. 25. CUDISP and DISPTMG should
be provided after being delayed by one-character time by using
skew bit of interlace & skew register (R8). Moreover, when

there are some troubles about delay time of MA during horizontal one-character time on high-speed display operation,
system shown in Fig. 23 is adopted. The time chart in this case
is shown in Fig. 26. Character video signal is delayed for twocharacter time because each MA outputs and refresh memory
outputs are latched, and they are made to be in phase with
CUDISP and DISPTMG by delaying for two-character time.
Table 10 shows the circuitry selection standard of display units.

Table 10 Circuitry Standard of Display Control Unit

Case

> RM Access + CG Access + tMAD

1

tCH

2

RM Access

3

RM

+ CG Access + tMAD L tCH > RM
Access + tMAD 2 tCH > RM Access

Interlace & Skew Register
Bit Programming

Block
Diagram

Relation among tCH Refresh Memory and Character Generator

C1

CO

01

DO

0
1

0
0

0

Fig. 22

0
0

Fig. 23

1

0

1

0

Fig. 21
Access

+ tMAD

tCH : CHCP Penod; tMAD: MA Delay
RM: Refresh Memory CG: Character Generator
F1

CUDISP
CHCP-N
F2

DISPTMG

CRTC

P

MA

Refresh
Memory
S

RA

ClK
CHCP-P

Figure 22 Display Control Unit (2)
F1

CUDISP
CHCP-N
DISPTMG

CRTC
MA

Refresh
Memory

RA

ClK
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--=C;.;,.H;.;:C:.;".P.,;.-P-iDOT

COUNTERI....---01----t OSC

Figure 23 Display Control Unit (For high-speed display operation) (3)

466

$

HITACHI

1

-------------------------------------------------HD6845S,HD68A45S,HD68B45S

CHCP-P
MA
DISPTMG

-.--,~-~

CUDISP

---~--~-~~-------_4-----J

F2-Q
F1-Q

RMOUT
CGOUT
VIDEO
CRT

\
Display

•••••••
Figure 24 Time Chart of Display Control Unit (1)

CHCP-P
MA

CUDISP
F2-Q

Fl-Q

LATCH(l~)_J~------~~----------~~----------~I'__- - - - -__'I'----------JI~--CGOUT
VIDEO
CRT

•••••••

Display

Figure 25 Time Chart of Display Control Unit (2)

$

HITACHI

467

HD6845S,HD68A45S,HD68845S - - - - - - - - - - - - - - - - - - - - - - -

CHCP·P

MA
DISPTMG

CUDISP

-----'"\\

-+------~~------4_----~~------~----~
2
3
4
o
-+______-J~------,~------J~-------JII~------~~------~\-------

lATCH (21

F2.Q

F1·Q

RMOUT ..

,1v.l'flll1L.1.

1~'~_-I.-I'""'~_~.J'¥.t.I./f'__~

CGOUT

VIDEO

CRT Display

Figure 26 Time Chart of Display Unit (3)
• HOW TO DECIDE PARAMETERS SET ON THE CRTC
•

How to Decide Parameters Based on Specification of CRT
Display Unit (Monitor)
Number of Horizontal Total Characters

Horizontal deflection frequency fh is given by specification
of CRT display unit. Number of horizontal total characters is
determined by the following equation.

fh

=

1

tc (Nht + 1)

where,

tc : Cycle Time of CLK (Character Clock)
Nht : Programmed Value of Horizontal Total Register
(RO)
Number of Vertical Total Characters

Vertical deflection frequency is given by specification of
CRT display unit. Number of vertical Total characters is
determined by the following equation.
1) Non-interlace Mode
Rt =(Nvt + I)(Nr + 1) + Nadj
2) Interlace Sync Mode
Rt =(Nvt + I)(Nr + 1) + Nadj + 0.5
3) Interlace Sync & Video Mode -

468

Rt Rt

(Nvt + I) (Nr + 2) + 2Nadj
2

. . . . . . . . . . . .. (a)

=(Nvt + I)(Nr + 2) + 2Nadj +I

(b)
2
(a) is applied when both total numbers of vertical characters
(Nvt + 1) and that of rasters in a line (Nr + 2) are odd.
(b) is applied when total number of rasters (Nr + 2) is even, or
when (Nr + 2) is odd and total number of vertical characters
(Nvt + I) is even.
where,
Rt
Number of Total Rasters per frame
(Including retrace period)
Nvt
Programmed Value of Vertical Total
Register (R4)
Nr
Programmed Value of Maximum Raster
Address Register (R9)
Nadj
Programmed Value of Vertical Total Adjust
Register (RS)
Horizontal Sync Pulse Width

. Horizontal sync pulse width is prbgrammed to low order
4-bit of horizontal sync width register (R3) in unit of horizontal
character time. Programmed value can be selected within from 1
to 15.

eHITACHI

Horizontal Sync Position

Vertical Sync Position

As shown in Fig. 27, horizontal sync position is nonnally
selected to be in the middle of horizontal retrace period. But
there are some cases where is optimum sync position is not
located in the middle of horizontal retrace period according to
specification of CRT. Therefore, horizontal sync position
should be determined by specification of CRT. Horizontal sync
pulse position is programmed in unit of horizontal character
time.

As shown in Fig. 28, vertical sync position is nonnally
selected to be in the middle of vertical retrace period. But there
are some cases where its optimum sync position is not located in
the middle of vertical retrace period according to specification
of CRT. Therefore, vertical sync position should be detennined
by specification of CRT. Vertical sync pulse position is programmed to vertical sync position register (R7) in unit of line
period.
• How to Decide Parameters Based on Screen Format
Dot Number of Characters (Horizontal)

HSYNC

Dot number of characters (horizontal) is detennined by
character font and character space. An example is shown in Fig.
29. More strictly, dot number of characters (horizontal) N is
determined by external N-counter_ Character space is set by
means shown in Fig. 30.

.J1'--_ _ _ _ _ _ _ _.Jn,L.-_ _ _ _ _ _ __
Figure 27 Time Chart of HSYNC

Oot Number of Characters (Vertical)
Vertical Sync Pulse Width

Vertical Sync Pulse Width is programmed to high order 4-bit
of vertical sync pulse width register (R3) in unit of raster
period. Programmed value can be selected within from 1 to 16.

f - - Vertical

I

Vertical
Retrace Period

Display Period

I I

DISPTMG---..J

jJ

Dot number of characters (vertical) is detennined by
characters font and line space. An example is shown in Fig. 29.
Dot number of characters (vertical) is programmed to mayb.m1
raster address (R9) of CRTC.

.1.

Vertical
.-----I
Display Period
I

~___~I--'--I---IJ~

I

- - 1 Frame------..j./

f--I

VSYNC------------------------~n~-------------------------Figure 28 Time Chart of VSYNC

Don Number of

Character Fo nt

"-...

rHO';'O"'" Ch'''"'~Ch aracter
l

•

• •

•
•
•
•
•
•
• • • •• • •
•
•
•
•
•
•

I

Space

•••
•
•
•
•
•
•
••••
•
•
•
•
•
•
•••••
••

Dot Number of
Vertical Characters
(Number of Rasters)

Line
Space

I

Dot Number of Horizontal Characters
Dot Number of Vertical Characters
7x9 Character generator is used.

10
13

J

Figure 29 Dot Number of Horizontal and Vertical Characters

eHITACHI

469

HD6845S,HD68A45S,HD68B45S-----------------------Character Font

\

•••••
•
•
•
•
•
•
••••
•
•
•
•
•
•
•••••

"0"

"0""0"

I

I I

Seria I Data

Shift Register

Figure 30 How to Make Character Space

Horizontal Deflection Period Ith) =

Horizontal Display Period

i-

Horizontal Retrace Period

Number of Horizontal Displayed Characters

~

Horizontal Display Period
Horizontal Character Time = - - - - - - - - - - - - - - , - , - - Number of Horizontal Displayed Characters

Figure 31 Number of Horizontal Displayed Characters

Number of Horizontal Displayed Characters

Number of horizontal displayed characters is programmed to
horizontal displayed register (Rl) of the CRTC. Programmed
value is based on screen format. Horizontal display period,
which is given by specification of horizontal deflection frequency and horizontal retrace period of CRT display unit,
determines horizontal character time, being divided by number
of horizontal displayed characters. Moreover, its cycle time and
access time which are necessary for CRT display system are
determined by horizontal character time.
Number of Vertical Displayed Characters

Number of vertical displayed characters is programmed to
vertical displayed register (R6). Programmed value is based on
screen format. As specification of vertical deflection frequency
of CRT determines number of total rasters (Rt) including verti-

470

cal retrace period and the relation between number of vertical
displayed character and total number of rasters on a screen is
as mentioned above, CRT which is suitable for desired screen
format should be selected.
For optimum screen format, it is necessary to adjust number
of rasters per line, number of vertical displayed characters, and
total adjust raster (Nadj) within specification of vertical
.
deflection frequency.
Scan Mode

The CRTC can program three-scan modes shown in Table 11
to interlace mode register (R8). An example of character display
in each scan mode is shown in Fig. 8.

~HITACHI

------------------------------------------------HD6845S.HD68A45S.HD68B45S
Table 11 Program of Scan Mode

v

S

0

0

1

0

0

1

1

1

Scan Mode

Main Usage
Normal Display of Characters

Non-interlace

& Figures
Fine Display of Characters

Interlace Sync

& Figures
Display of Many Characters

Interlace Sync

[NOTE]

& Figures Without Using

& Video

High-resolution CRT

In the interlace mode. the number of times per
sec. in raster scanning on one spot on the screen
is half as many as that in non-interlace mode.
Therefore. when persistence of luminescence is
short. flickering may happen. It is necessary to
select optimum scan mode for the system. taking
characteristics of CRT. raster scan speed, and
number of displayed characters and figures into
account.

Cursor Display Method
Cursor start. raster register and cursor end raster register

(R 10, R II) enable programming the display modes shown in
Table 7 and display patterns shown in Fig. 9. Therefore, it is
possible to change the method of cursor display dynamically
according to the system conditions as welI as to realize the
cursor display that meets the system requirements.
Start Address
Start address resisters (RI2, R13) give an offset to the
address of refresh memory to read ouL This enables paging and
scrolling easily.
Cursor Register
Cursor registers (R 14, R 15) enable programming the cursor
display position on the screen. As for cursor address, it is not X,
Y address but linear address that is programmed.
•

Applications of the CRTC

•

Monochrome Character Display
Fig. 32 shows a system of monochrome character display.
Character clock signal (CLK) is provided to the CRTC through
OSC and dot counter. It is used as basic clock which drives
internal control circuits. MPU is connected with the CRTC by
standard bus and controls the CRTC initialization and read/
write of internal registers.
Refresh memory is composed of RAM which has capacity of
one frame at least and the data to be displayed is coded and
stored. The data to refresh memory is changed through MPU

..--MPU

I

II

-

MA

,
OSC

DDT
COUNTER

lJ

I

ClK

;-

BUS DRIVER

MULTIPLEXER

lL
REFRESH
MEMORY
(RAM)

TI
CRTC

RA

CHARACTER
GENERATOR

JL

P

-

S

~

DISPTMG
CUDISP

VIDEO

HSYNC

CONTROL

VIDEO
SYNC
SIGNAL

0
0

0

VSYNC

Figure 32 Monochrome Character Display

_HITACHI

471

bus, while refresh memory is read out successively by the CRTC
to display a static pattern on the screen. Refresh memory is
accessed by both MPU and the CRTC, so it needs to change its
address selectively by multiplexer. The CRTC has 14 MA
(Memory Address output), but in fact some of them thai are
needed are used according to capacity of refresh memory .
Code output of refresh memory is provided to character
generator. Character generator generates a dot pattern of a
specified raster of a specified character in parallel according to
code output from refresh memory and RA (Raster Address
output) from the CRTC. Parallel-serial converter is normally
composed of shift register to convert output of character
generator into a serial dot pattern. Moreover, DISPTMG,

CUDISP, HSYNC, and VSYNC are provided to video control
circuit. It controls blanking for output of parallel-serial converter, mixes these signals with cursor video signal, and generates sync signals for an interface to monitor.
• Color Character Display
Fig. 33 shows a system of color character display. In this
example, a 3-bit color control bit (R, G, B) is added to refresh
memory in parallel with character code and provided to video
control circuit. Video control circuit controls coloring as well
as blanking and provides three primary color video signals (R,
G, B signals) to CRT display device to display characters in
seven kinds of color on the screen.

I=====::::;-;::::=======================iir=========~

Au -Ao

~=====*~~====================~~====~~=>D,-Do
MA

Configuration of the Refresh Memory

REFRESH
MEMORY
(RAMI

CRTC

Blink

RA

COLOR BIT (R, G, BI

DISPTMG

R. VIDEO

CUDISP

G. VIDEO
VIDEO CONTROL

HSYNC

B. VIDEO

0
0

0

VSYNC
SYNC SIGNAL

Figure 33 Color Character Display

• Color limited Graphic Display
Umited graphic display is to display simple figures as well as
character display by combination of picture element which
are dermed in unit of one character.
As shown in Fig. 34, graphic pattern generator is set up in
parallel with character generator and output of these generators are wire-ORed. Which generator is accessed depends on

472

$

coded output of refresh memory.
In this example, graphic . pattern generator adopts ROM, so
only the combination of picture elements which are program·
med to it is used for this graphic display system. Adopting RAM
instead of ROM enables dynamically writable symbols in any
combination on one display by changing the contents of them.

HITACHI

------------------------------------------------HD6845S,HD68A45S,HD68845S

~====~~======================~==============~A,s-Ao

~====~~~====================~===========;==~D7-Do

REFRESH
MEMORY
(RAM)

CRTC

COLOR BIT (R, G, B)

R. VIDEO
G. VIDEO

CUDISP
VIDEO CONTROL

HSYNC
VSYNC

L-______________________

B. VIDEO

o
o

0

~SYNCSIGNAL

Figure 34 Color Limited Graphic Display

$

HITACHI

473

HD6845S,HD68A45S,HD68B45S----------------------------------------------• Monochrome Full Graphic Display

Fig. 35 shows a system of monochrome full graphic display.
While simple graphic display is figure display by combination of
picture elements in unit of 1 picture elements, full graphic display is display of any figures in unit of I dot. In this case,

refresh memory is dot memory that stores all the dot patterns,
so its output is directly provided to parallel-serial converter to
be displayed. Dot memory address to refresh the screen is set
up by combination of MA and RA of CRTC.

~======~====================~~================~AI5-Ao
MPU

I¢:===~==;~========:::::;~========;~==!>

MA
RA

DOT MEMORY
(RAMI

CRTC

DISPTMG
HSYNC

VIDEO
SYNC

VIDEO
CONTROL

SIGNAL

VSYNC

Figure 35 Monochrome Full Graphic Display

474

~HITACHI

o
o

o

D7 -Dn

- - - - - - - - - - - - - - - - - - - - - - - - HD6845S,HD68A45S,HD68845S
Fig. 36 shows an example of access to refresh memory
by combination ofMA and RA. Fig. 36 shows a refresh memory
address method for full graphic display. Correspondence be-

tween dot on the CRT screen and refresh memory address is
shown in Fig. 37.

RA,
RA,
RAo

MA.
MA.
MA,
MA.
MA,

CRTC

~~tl1l1
MA'~

Refresh Memory
Address

Figure 36 Refresh Memory Address Method for Full Graphic Display

32 Characters x 8 dots = 256 dots
, / 1 b yte (8 -b"It )

11101111
8 rasters
(1 line)

32
64
96

1
33
65
97

31
63
95
127

224

225

255

24 lines
x 8 rastars
= 192 rasters

"

:

I

6112

6148

6113

'\

Value of ma

Figure 37 Memory Address and Dot Display Position on the Screen for Full Graphic Display

_HITACHI

475

• Color Full Graphic Display
Fig. 38 shows a system of color full graphic display by 7·
color display. Refresh memory is composed of three dot
memories which are respectively used for red, green, and blue.
These dot memories are read out in parallel at one time and

their output is provided to three parallel.serial converters. Then
video control circuit adds the blanking control to output of
these converters and provides it to CRT display device as red,
green, and blue video signals with sync signals.

r---

..
MPU

---DOT
OSC

COUN·
TER

"

F-

BUS
DRIVER

MA
RA

BUS
DRIVER

BUS
DRIVE

!dl

MULTIPLEXER

I

B

,

I

G
R

DOT
MEMORY (RAM)
CRTC

toto-

Ib 1==
;=

1

<7
P

-

S

iJJ
RED VIDEO

DISPTMG
HSYNC

VIDEO
CONTROL

GREEN
VIDEO
BLUE
VIDEO

0
0

VSYNC

,

0

SYNC SIGNAL

Figure 38 Color Full Graphic Display

• Cluster Control of CRT Display
The CRTC enables cluster control that is to control CRT
display of plural devices by one CRTC. Fig. 39 shows a system
of cluster control. Each display control unit has refresh memory,
character generator, parallel-serial converter, and video control

476

circuit separately, but these are controlled together by the
CRTC.
In this system, it is possible for plural CRT display devices to
have their own display separately.

~HITACHI

:t

~
!

()

DISPTMG
CUDISP
HSYNC

VIDEO
CONTROL

::L
C

VSYNC

0>

00
~

C1I

,en
~
~
o

o

~

L....::.:.-J
o

o

~
~
o

0

::L
C

0>

00

»
~

C1I

y>
::L
C
0>

00
OJ
~

~

......

......

Figure 39 Cluster Control by the CRTC

C1I

en

•

EXAMPLES OF APPLIED CIRCUIT OF THE CRTC

Fig. 41 shows an example of application of the CRTC to
monochrome character display. Its specification is shown in

Table 12. Moreover, specification of CRT display unit is shown
in Table 13 and initializing values for the CRTC are shown in
Table 14.

Table 12 Specification of Applied Circuit
Item

Specification
5 x 7 Dot

Character Format
Character Space

Horizontal : 3 Dot Vertical : 5 Dot

One Character Time
Number of Displayed Characters

1 tls
40 characters x 16 lines

Access Method to Refresh Memory

Snychronous Method (DISPTMG Read)

Refresh Memory

640B

Address Map

= 640 characters

2 15 214 :2 13 212 211 2 10 2 9

28

27

26

25

24

i'

22

21

20

*

*

*

*

"-

"-

x

0

"-

x

1

Refresh
Memory

0

0

0

0

0

0

*

*

*

*

*

*

CRTC
Address
Register

0

0

0

1

0

0

x

x

)<.

x

x

)<.

CRTC
Control
Register

0

0

0

1

0

0

"-

"-

"-

"

"-

x

x ... don't care, * ... 0 or 1
Synchronization Method

HVSYNC Method
Table 13 Specification of Character Display
Specification

Item
Scan Mode

478

Non·interlace

Horizontal Deflection Frequency

15.625 kHz

Vertical Deflection Frequency

60.1 Hz

Dot Frequency

8MHz

Character Dot (Horizontal x Vertical)

8 x 12 (Character Font 5 x 7)

Number of Displayed Characters (Row x Line)

40x 16

HSYNCWidth

4 tls

VSYNCWidth

3H

Cursor Display

Raster 9 - 10, Blink 16 Field Period

Paging, Scrolling

Not used

eHITACHI

Table 14 Initializing Values for Character Display
Register

Symbol

Name

Initializing Value
Hex (Decimal)

AO

Horizontal Total

Nht

3F

(63)

Al

Horizontal Displayed

Nhd

28

(40)

Nhsp

34

(52)

Nvsw. Nhsw

34

A2

Horizontal Sync Position

A3

Sync Width

A4

Vertical Total

Nvt

14

(20)

A5

Vertical Total Adjust

Nadj

08

( 8)

A6

Vertical Displayed

Nvd

10

(16)

A7

Vertical Sync Position

Nvsp

13

(19)

A8

Interlace & Skew

00
Nr

(11)

A9

Maximum Raster Address

Al0

Cursor Start Raster

B. p. NCSTART

49

All

Cursor End Raster

NCEND

OA

(10)

A12

Start Address (H)

00

( 0)

A13

Start Address (L)

00

( 0)

R14

Cursor (H)

00

( 0)

A15

Cursor (L)

00

( 0)

tc

OB

1IJS

i0123456710123456J01234567i

I mm:l

I I I1111
I11111111
II
\

Cursor

Figure 40 Non-interlace Display (Example)

eHITACHI

479

~

::I:
C

~

0)

00
~

U1

r-=::::=::]:=:::t±=~~"'T~TLT
II

ll' rrrAt" ~' rJrj' rrrr

'OOOIO~~~ 1

11

......... IOI

M

~~~~----~
HD74L.S3

07

6. 0 ..

at

01 02 01 O.

00

I----'

r

~

Y--'::L':::L9.:

>
~

LL.L

J! ;2:T: )

U1

Yl
::I:
C
0)

00

00
~

U1

en

CRTC MA,

~D'

;l

~: O:S~~~

$

::t

~
()
!

~t~~~~::i:=+==t===
REs

D,
D,

ri

~'~:III~.1

llJ

CLK

rL

ti

L

DISPTMG REG.

DISPR£AD-N

IL'=
56~'

2201.!

[

00_

o

~~

::I:
C
0)

~f,_~l, l:~:4LSO°:l~ii!iii~~~;;;;,
D.

Yl

=~:~r--i----, r-+------, r - - - - - - , r-------,

·N
HD

_

7402

CS

.

0 - - - -.....

CGA. CGA.

$'

CG OUTPUT' •
SROUT.P ,

_

~.

;
i

.

!

! i

C!

c:
!

;

!

;

S«,aIO.ta

HD7486

:=~~=============~D

Figure 41 Example of Applied Circuit of the CRTC (Monochrome Character Display)

R,'S'"

•

DISPLAY SEQUENCE AFTER

fiR RELEASE OF HD6845S (1)

HD6845S starts the display operation immediately after the
release of RES. The operation at the first field is different from
the normal subsequent display operation.
[Operation at the first field after the RES release]

DISPTMG and CUDISP are not output. (They remain at
"Low" level. The display is inhibited.)
The data programmed in the start address register is not
used. (MA and RA start at "0".)
The sequences are shown in the following figures.

(2)
(3)

Display Operation Starts (first field)

ClK

RES __________-+~
0- 50ns (RES should be released during this period.)

MAx

o

o
Figure 42

first field

1-----...;,;,;,;:..:...;=.:=-------1_- Normal

RES Release Sequence

Operation

RES _
Frame Period

RAX---CCX
L,ne::O::l

-x:x ~ y:::x ~ XJ:. ~ D
::Nvsp

n

VSYNC

::Nvt

:~~ .••

\

::1

: Nvsp

n

Adjust

Figure 43

:0:1

:Nvt

: Nvsp

n

::0::'

:Nvt

Even,

n.-

RES Release Sequence in The Non-interlace Mode

I -_ _ _ _ _f;.;.ir~s.:..t.:..:fi.::.;el~d_ _ _ _ _+ _ Normal Operation

!

::Nvsp

:t------

I - - - - - - - - - - - - - - F r l m e ' - - - - - - - - - - - - -....
Field - - - - - - i ! - - - - - - O d d Field

Field------<~----- Even

Even

RAX-S;;;::;;X ~~.
:1 ~ ~ ~ ~
VSYN~C~A

____________

~~L____··__:NVt
____~
__~A_d_JU_.S.t -~

______
- __

~-~~-------:N.rt
____'__
\~A_d_jU_S:t ~ ~ -~rhL-______
:__
__________

A:_d _~jU_.st

Nvt__" __

__"__
' __"___
2

VSYN~C~B__________~~~____________________~~~________________________~~L______________________
VSYNC A

VSYNCB

Interlace Sync
Interlace Sync
Jnterlace Sync
Jnterlace Sync

Control
& Video Control (Nr + 2 = Even)
& Video Control (Nr+2=Odd. Nvt=Odd, Nvsp=Even)
& Video Control (Nr+2=Odd, Nvt=Odd, Nvsp=Odd)

Figure 44

RES Release Sequence in The Interlace Mode (1)

1-_ _ _ _...:.f.:.:.ir::.,;st:.,;f.:.:ie;.:.ld::..-_ _ _ _-+_-NormaIOperation

I

I-------------Frame-------------+t:---------Even,Field-----+-----Even,Field
Odd F i e l d - - - - - . j . - - - - E v e n - - -

I

'AA~~~V~~~
:

VSYN~C~~~

_________

Adjust

~~

:

Adjust: :

I

::

Adjust

fl~----------------------rn~--------------------------

r,

VSYN~C~~~__________~~

~~

___________________________

VSYNCIC: : Interlace Sync & Video Control (Nr+2=Odd, Nvt=Even, Nvsp=Even)
VSYNC~ : Interlace Sync & Video Control (Nr+2=Odd, Nvt=Even, Nvsp=Odd)

Figure 45

RES Release Sequence in The Interlace Mode (2)

~HITACHI

481

HD6845S,HD68A45S,HD68B45S-----------------------------------------------• ANOMALOUS OPERATIONS IN HD6845S CAUSED BY REWRITING REGISTERS DURING THE DISPLAY OPERATION*

Register

Register Name

#

Anomalous operations caused by rewriting registers & Conditions to avoid
those operations

Rewriting"
OK or NG

X
0

RD

Horizontal Total

The horizontal scan period is disturbed.

R1

Horizontal Displayed

There are some cases where the width of DISPTMG becomes shorter than the
programmed value at the moment of a rewrite operation. An error operation
occurs only during one raster period.

R2

Horizontal
Sync Position

There are some cases where HSYNC is placed on the position different from
the programmed value or the noise is output.

X

R3

Sync Width

When a rewrite operation is performed at a "High" level on HSYNC pulse or VSYNC
pulse, there are some cases where the width pulse becomes shorter than the
programmed value at the moment of a rewrite operation.

6.

R4

Vertical Total

When a rewrite operation is performed during the last raster period in the line, there is
a possibility that the disturbance occurs during the vertical scan period. There is no
problem of a rewrite operation during raster period except this period.

R5

Vertical Total
Adjust

When a rewrite operation is performed in the last character time of the raster period,
there are some cases where the numbers of Adjust Raster, specified by program, are
not added. (Only during the adjust raster period)

6.

R6

Vertical Displayed

After the moment of a rewrite operation, there are some cases where the Display is
inhibited. However, the display according to the programmed value is performed
from the next field.

0

R7

Vertical Sync
Position

There are some cases where VSYNC is placed on the position different from the
programmed value or the noise is output.

X

RB

Interlace & Skew

Neither scan mode bit nor skew bit is rewritten dynamically.
Dynamic Rewrite into scan mode bit and skew bit is prohibited.

X

R9

Maximum Raster
Address

The internal operation will be disordered by a rewrite operation.

X

R10

Cursor Start Raster

When a rewrite operation is performed in the last character time of the raster
period, there are some cases where the jitter occurs on the cursor raster or the cursor
is not displayed correctly. There is also a possibility that the blink rate becomes
temporally shorter than usual.

6.

R11

Cursor End Raster

When a rewrite operation is performed in the last character time of the raster period,
there are some cases where the jitter occurs on the cursor raster or the cursor
is not displayed correctly. Moreover, there are also some cases where the bl ink rate
becomes temporally shorter than normal operation.

6.

R12

Start Address (H)

0

R13

Start Address (L)

R12 and R13 are used in the last raster period of the field. A rewrite operation can
be performed except during this period. However, when R12 and R13 are rewritten in
each field separately, the display operation, whose start address is determined
temporally by programming sequence, will be performed.
A rewrite operation should be performed during the horizontal/vertical display
period.

R14

Cursor (H)

0

R15

Cursor (L)

When a rewrite operation is performed during the display period, there are some
cases where the cursor is temporally displayed at the address different from the
programmed value. A rewrite operation should be performed during the horizontal/
vertical retrace period. Also, when R14 and R 15 are rewritten in each field separately,
the cursor is displayed temporally at the temporal address determined by programming
sequence .

-~-.--

--

0

0

. means temporary abnormal operations in rewriting the internal register during the display operation. Normally, after a rewrite operation,
the LSI performs the specified display operation from the next field.
(The operations in this table are outside our guarantee and are regarded as materials for reference.)

*. {

0
6.

.. A

rewrite operation is possible without affecting the screen in the display so much.

If conditions are satisfied, a rewrite operation is possible. If conditions are not satisfied, there are some cases where a flicker and
. . .•. so on occu r temporally.

X ..... When a rewrite

482

operation is performed, there are some cases where a flicker and so on occur temporally.

~HITACHI

•
•

COMPARISON BETWEEN HD6845S AND HD6845
Comparison of function between HD6845S and HD6845
No.

Functional Difference

HD6845S

HD6845

Character line address
Interlace Programming Character line address
Method
1,--_ _ _ _ _ _ _ _ _ _ _-"
Sync
&
Numo~er of 0 ~_!t~______________________________ J~~~f~~7~~~ber ~ ABC
1J~~~f~~~~~~gber
Video Mode
Vertical
of vertical
of vertical
Display
Characters 1 ---------------------------------- characters
2
characters
____________________
_________________

I

3,~

4~

2 ------------------------------

5~

____________________

~

6,~-----------~
7~---__. - - - - - - - - - - - -__
-__________________

3 ------ - - -- ---------- --- -----------

8,~

4 ------- - -------- - ------- ---- ----

9.L-_ _ _ _ _ _ _ _ _ _ _

In H 06845, number of characters is vertically programmed in unit of two lines, as illustrated above.
(Number of vertical total characters, Number of
vertical displayed characters, Vertical Sync Position)

Number of
Rasters Per
Character
Line

~

In HD6845S, number of characters is vertically programmed in unit of one line, as illustrated above.
(Number of vertical total characters, Number of
vertical displayed characters, Vertical Sync Position)

Example of above figure

Example of above figure

Programmed number into Vertical Displayed
Register = 5

Programmed number into Vertical Displayed
Register = 10

Only even number can be specified.

Both even number and odd number can be specified.
Character line address
Character line address

0------

~~=~} + 4~5
~=t~:=~~-~=t~=~}t

2~~}

: __ ~---mm-$:: 5
8

~==~_-_-_-=~=~~~ .~

o

... -- N umber of raster

!i~:}

Character line address

0

4:1-~~5
6~7

0

4 _________ --5

1

tm---~~~~-~~~=!}· ;~~}1

:==~_~~~~~~~~

68 --:3-+-0-0-----.7
_________________ 9

Number of raster = 10 scan line (specified)
However, number which is programmed into register is calculated at follows.
Programmed number (Nr)
= (Number specified) - 1

0

6=8:--------tt::7

5~6

7--------------8

When number of raster
per character line is
EVEN.
Number of raster
= 10 scan line
(specified)

When number of raster
per character line is
ODD.
Number of raster
= 9 scan line
(specified)

However, number which is programmed into register
is calculated as follows.
Programmed number (Nr)
= (Number specified) -2
Cursor
Display

Cursor is displayed in either EVEN field or ODD
field.

Cursor is displayed in both EVEN field and ODD
field.

01------

---------------1

!~3 -EVEN number

6:!~~_~~!_~_-_~~

-EVEN number

8

0-------------- 1

2-~~-Q__e__o--3 -ODD number

4--~_o-9-_E>__E>_--5
6 _____________ 7

-ODD number

~ --------------1
~~itit--3

4~66:g:--5

6:------

-ODD number
-ODD number

8--------------7

8--------

01------

2~1

-EVEN number

4~~
-ODD number
6 _____________
8,------

7

(to be continued)

~HITACHI

483

No.

HD6845

Functional Difference

2

HD6845S

Fixed at 16 raster scan cycle (16H)

Vertical Sync
Pulse Width

I

Programmable (1 - 16 raster scan cycle)

r-

I

Fixed at 16

~
scan cycle"!
VS~

(VSYNC output)

Specified bY-1
high order
4 bit of R3

V~
Attached bits

R3~JJJJ
Not used

SKEW Function

3

E±±E1\llL1

R3

Horizontal Sync Width

Vertical Sync
Width

Not included

Horizontal Sync
Width

SKEW function is newly included in DISPTMG,
CUDISP signals.
Attached byte

R8~vlsl

R8

@§@B~vl S I

CUDISP DISPTMG

Not used

Example of DISPTMG output
~Notskewed

-~ One character skew

-rif--:--J
L.:.'
4

Start Address Register

5

RESET Signal

Impossible to READ

(R"ES)

L-~

Possible to READ
MAo - MA13 outputl
RAo - RA. Output
Other Outputs

MAo - MAn output}
RAo _ RA. Output . . . . . Synchronous reset
Other Outputs

L--.. Two character skew
1 character time
2 character time

J' .... Asynchronous reset

. . . . . Asynchronous reset

Output signals of MAo - MA u , RAo - RA.,
synchronizing with DLK "Low" level, go to
"Low" level, after RES has gone to "Low".
Other outputs go to "Low" immediately after
________________L-__________________________________
~ has gone to "Low" level

Output signals of MAo - MA 13, RAo - RA. and
others go to "Low" level immediately after ~
has gone to "Low" level.
~

__________________________________ __

• Comparison of Timing Signal between HD6845S and HD6845
Item

No.

•

Symbol

max

min

-

270

-

-

ns

130

-

-

ns

130

-

-

ns

20

ns

-

200

ns

-

ns

70

ns

-

0

ns

1

Clock Cycle Time

tcycc

330

-

Clock "High" Pulse Width

PWCH

150

-

150

-

3

Clock "Low" Pulse Width

PWCL

4

Rise and Fall Time for Clock Input

tCr. tCf

5

Horizontal Sync Delay Time

tHSD

-

6

Light Pen Strobe Pulse Width

PWLPH

80

7

Light Pen Strobe
Uncertain Time of Acceptance

tLPD1

-

-

80

tLPD2

-

-

10

COMPATIBILITY OF HD6845S AND HD6845

; Fully compatible with HD6845'"
HD6845 can be directly replaced
by HD6845S in these modes.
Interlace sync & Video mode control:
Not compatible with HD6845 in
regard to programming and
Interlace sync mode control

15
250

-

60

-

typ

Unit

typ

2

Non-interlace mode control }

484

HD6845S

HD6845
min

max

data for vertical direction need
to be changed.
... The functions added to HD6845S utilize undefined bits of
the Control Register in HD6845. If "0" is programmed to
the undefined bits in the initial set, it is possible to replace
HD6845 with HD6845S without changing the parameters.
Note)
The restriction on programming of HD6845S and
HD6845 should be taken into consideration.

~HITACHI

HD6846

COMBO

(Combination ROM I/O Timer)

The H06846 combination chip provides the means, in con·
junction with the H06802, to develop a basic 2·chip microcomputer system. The HD6846 consists of 2048 bytes of mask·
programmable ROM, an 8·bit bidirectional data port with con·
trollines, and a 16·bit programmable timer·counter.
This device is capable of interfacing with the H06802 (basic
H06800, clock and 128 bytes of RAM) as well as the H06800
if desired. No external logic is required to interface with most
peripheral devices.
• FEATURES
• 2048 Bytes of Mask·Programmable ROM
• 8·Bit Bidirectional Data Port for Parallel Interface plus
Two Control Lines
• Programmable Interval Timer·Counter Functions
• Programmable I/O Peripheral Data, Control and Direc·
tion Registers
• Compatible with the Complete HMCS6800 Microcom·
puter Product Family
• TTL·Compatible Data and Peripheral Lines
• Single 5-Volt Power Supply
• Compatible with MC6846

• PIN ARRANGEMENT

Vss

o

A.
A,

A,

A ,u

iRQ
CP,
CP,
0"
0,

• TYPICAL MICROCOMPUTER
Vee

0,
Vee

A"
A,

HD6846
A,

Vee
Standby Vee

Vee

CTO
Counter/Timer 1/0 ( CTG
CTC

0,

VCC

0,

P,

0,
0,

P,
P,
P,

CS,

P,

P,
P,

P,

P,
PI,.II.II/O

::

P,
p.

Control

IC;:

{

(Top View)

CP,

40 pins

Vss

Vss

This is a block diagram of a typical cost effective microcomputer. The MPU is
the center of the microcomputer system and is shown in 8 minimum system interfacing with a ROM combination chip, It is not intended that this system be limited to
thil function but that it be expandable with other parts in the HMCS6800 Microcomputer family,

~HITACHI

485

HD6846----------------------------------------------------------______
• RECOMMENDED OPERATING CONDITIONS

• ABSOLUTE MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

Vee *

-0.3 - +7.0

V

Input Voltage

V in *

-0.3 - +7.0

V

Operating Temperature

Topr

-20 - +75

°c

Storage Temperature

Tstv

-55 -

°c

Item

+150

Item

Symbol

min

typ

Vee *

4.75

5.0

5.25

V

V 1L *

-0.3

-

0.8

V

V 1H *

2.0

-

Vee

Topr

-20

25

Supply Voltage
Input Voltage
Operating Temperature

* With respect to Vss (SYSTEM GND)
(NOTE) Permanent LSI damage may occur if maximum
ratings are exceeded. Normal operation should
be under recommended operating conditions. If
these conditions are exceeded, it could affect
reliability of LSI.

max Unit

* With respect to VSS (SYSTEM GND)

• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vcc=5.0V±5%, Vss=OV, Ta=-20-+75°C, unless otherwise noted.)
min

typ

max Unit

Input "High" Voltage

All Inputs

V 1H

2.0

Vee

V

Input "Low" Voltage

All Inputs

V 1L

-0.3

0.8

V

Vee
-0.5

-

Vee
+0.5

Vss
-0.5

-

Vss
+0.5

Test Condition

Symbol

Item

Input "High" Level
Clock Overshoot/Undershoot

Input "Low" Level

Vos

V

Input Leakage Current

R/W, RES, CSo ,
CS 1, CP I , CTG,
CTC, E, Ao-A 1o

lin

V in = 0 - 5.25V

-2.5

-

2.5

p.A

Three-State (Off State)
I nput Current

0 0 -0 7 , PO-P 7 ,
CP 2

ITS I

V in = 0.4 - 2.4V

-10

-

10

p.A

IOH = -205p.A

2.4

CP 2 , PO -P 7

IOH = -200p.A

2.4

CTO

IOH = -200p.A

2.4

-

-

V

Output "High" Voltage

0 0 -0 7

IOL = 1.6mA

-

0.4

V

IOL = 3.2mA

-

0.4

V

-

p.A

-

p.A

,

0 0 -0 7

Output "Low" Voltage
I

--"--

VOH

VOL

Other Outputs
0 0 -0 7

Output "High" Current
(Sourcing)

IOH

CTO, CP 2 , PO -P 7

Output "High" Current
(Sourcing)
(the current for driving other than
TTL, e.g., Darlington Basel

CP 2 , PO -P 7

IOH

0 0 -0 7

I

205

V OH = 2.4V

200

-

VOH = 1.5V

-1.0

-

1.6

-

-

3.2

-

-

mA

10

p.A

800

mW

IOL

VOL = O.4y

Output Leakage Current
(Off State)

IRO

I LOH

VOH = 2.4V

E

Cin

D O-0 7

Cin

Vee;: OV

Po
I

Capacitance

PO-P 7 , CP 2 , CTO

Gout

Ao-Alo, R!W

C;n

V in = OV
Ta = 25°C

RES,~,CSI'

C;n

f = lMHz

IRO

Gout

CP I ,

486

T

V

V OH = 2.4V

Other Outputs

Power Dissipation

V

-

Output "Low" Current
(Sinking)

eHITACHI

-

V
°c

75

-10 mA

20

pF

-

12.5

pF

-

10

pF

7.5

pF

-

10

pF

-

7.5

pF

------------------------------------------------------------------HD6846
• AC CHARACTERISTICS (VCC=S.OV±S%, VSS=OV, Ta=-2o-+7SoC, unless otherwise noted.)
1. BUS TIMING
min

typ

Enable Cycle Time

Item

tcycE

1.0

-

10

loIS

Enable Pulse Width, "Low"

PWEL

430

-

4500

ns

PWEH

430

4500

ns

Address Set Up Time

tAS

140

-

-

ns

Data Delay Time

tOOA

-

-

320

ns

10

-

-

ns

Enable Pulse Width, "High"

Symbol

I

Data Hold Time

tH

Address Hold Time

tAH

Enable Rise and Fall Time

tEf,tEr

Data Set Up Time

tosw

Reset "Low" Time

tAL

Interrupt Release Time

tlA

Test Condition

Fig. 1

10
-

max

-

Unit

ns
ns

25

--195

-

-

ns

2

-

-

loIS

-

1.6

loIS

-

Fig. 2

2. PARALLEL PERIPHERAL I/O LINE TIMING
Item

Symbol

Test Condition

tposu

Fig.3

Rise and Fall Times CP, ' CP,

tpr, tpf

Fig. 5

Delay Time E to CP, Fall

tCP2

Delay Time I/O Data CP, Fall

toc

Delay Time E to CP, Rise

tAS1

Peripheral Data Setup Time

I

min

-+- I

Fig.4

typ

-

I

-

1

!

1.0

I

I

-

I

20

ns
1.0 _ +--_'"'_s___

-

-

I

Delay Time CP, to CP, Rise

tAS2

Fig.5

Peripheral Data Delay

tpow

Fig.4

r-=--r----::-~ J
2.0
I
I I
1.0
-

Peripheral Data Setup Time for Latch

tpsu

Peripheral Data Hold Time for Latch

Fig.9

~O-+--

tpOH

I

r

l-S

Unit

---~---~,------

L-------r---

i

max

-i--=---

!
200
~

-

i

I
I

loIS

ns
loIS
loIS
loIS

ns

-

-

min

typ

max

-

-

100

tC:l!cE
+ 50

-

-

ns

:256

-

-

ns

200

-

-

50

-

-

ns

-

1.0

loIS

i

ns

3. TIMER/COUNTER LINE TIMING
Item

Symbol

CTC, CTG Rise and Fall Time

tCr' tCf

CTC, CTG Pulse Width, "High" (Asynchronous Mode)

tpWH

CTC, CTG Pulse Width, "Low" (Asychronous Mode)

tpWL

CTC, CTG Setup Time (Synchronous Mode)

tsu

CTC, CTG Hold Time (Synchronous Mode)

thd

CTO Delay Time

tCTO

eHITACHI

Test Condition

I
Fig. 6

Fig. 7
Fig. 8

I

r--'

-

I

I

Unit
ns

i

ns

487

HD6846-------------------------------------------------------E
E

'RS2)

R/W

A.-A,.

es., CS,

CP 2

2.4V

(Output)

Figure 5 CP 2 (Output) Delay Time
0.-0, (Read)

-------'

COMBO ..... MPU

D. -0, (Write)

------

MPU-->COMBO

Figure 1 Bus ReadlWrite Timing
Figure 6 CTG, CTC Pulse Width

C"R~------

E

f2.4V

Figure 2 I RQ Release Time
Figure 7 CTG, CTC Setup Time and Hold Time

~.OV
p.-p, -------

E

~~~:~:~s-u--l---/--------------

f2.0V

p.-p,

\"----

·l--tCTO~

L

....,2-.4~V~---

CTO

Figure 3 Peripheral Data Set Up Time

(Output) _ _ _ _ _

_~OV

..:;O:.;;.4:..:v~_ __

Figure 8 CTO Delay Time

1'-"...,.......tc-P-2L--tDC::l

CP 2
(Output)

\.;;O,;.;.4;.;;V_ _ _,.,

Figure 4 Peripheral Data and CP 2 (Output) Delay Time

488

$

HITACHI

Figure 9 Pedpheral Port Latch Setup and
Hold Time

------------------------------------------------------------------HD6846

(TIm I
LOA~B

LOAD A

10.-0,. CTO.
CP,.Po-P,1

5.0V

1.5 kO
Test Point

Test Point

C

r~'

The timer/counter control register allows control of the
interrupt enable, output enable, selection of an internal or
external clock source, a + 8 prescaler, and operating mode.
Input pin CTC (counter-timer clock) will accept an asynchronous clock pulse to decrement the internal register for the
counter-timer. If the divide-by-8 prescaler is used, the maximum
clock rate can be four times the master clock f~ency with an
absolute maximum of 4 MHz. Gate input (CTG) accepts an
asynchronous TTL-compatible signal which may be used as a
trigger or gating function to the counter-timer. A counter-timer
output (CTO) is also available and is under software control
being dependent on the timer control register, the gate input.
and the clock source.
•

Parallel I/O Port
The parallel bidirectional I/O port has functional operational
characteristics similar to the B port on the HD6821 PIA. This
includes 8 bidirectional data lines and two handshake control
Signals. The control and operation of these lines are completely
software programmable.
The interrupt input (CP I ) will set the interrupt flag CSRI of
the composite status register. The peripheral control (CP 2 ) may
be programmed to act as an .interrupt input (set CSR2) or as a
peripheral control output.

C· 13QpF for 00 -0,
3QpF forCTO.CP,.p.-p,
R • 11 kO for D. -0,
12 kO for CTO. CP,. p.-p,

R L • 2.4 kn for 0.-0,
1.2kn forCTO.CP"p.-p,
All diodes are 1S2074@or equivalent.

Figure 10 Bus Timing Test Loads

• GENERAL DESCRIPTION
The HD6846 combination chip may be partitioned into
three functional operating sections: programmed storage, timercounter functions, and a parallel I/O port.

0,
0,
0,

0,
0,
D.

0,
0,

•

Programmed Storage
The mask-programmable ROM section is similar to other
ROM products of the HMCS6800 family. The ROM is organized
in a 2048 by 8-bit array to provide read only storage for a
minimum microcomputer system. Two mask-programmable
chip selects are available for user definition.
Address inputs Ao '" AlO allow any of the 2048 bytes of
ROM to be uniquely addressed. Bidirectional data lines (Do '"
D,) allow the transfer of data between the MPU and the HD
6846.
Timer-Counter Functions
Under software control· this 16-bit binary counter may be
programmed to count events, measure frequencies, time intervals, or similar tasks. Internal registers associated with the I/O
functions may be selected with A o , Al and A2 • It may also be
used for square wave generation, single pulses of controlled
duration, and gated signals. Interrupts may be generated from a
number of conditions selectable by software programming.

CS,
CS,
A,
A,
A,
A,

A,
A.
A,
A,
A.

A.
A"

•

Figure 11 Combination ROM I/O Timer (COMBO)

_HITACHI

Basic Block Diagram

489

HD6846----------------------------------------------------------------

CP,
CP,

im:i Buffer

s,.,!

R.. ",.,

---~
P,
P,

P,
P,

p.
P,
p.
,---~-P,

Figure 12 Parallel I/O Port Block Diagram

Figure 13 Timer/Counter Block Diagram

•

• SIGNAL DESCRIPTION
•

Bus Interface

The HD6846 interfaces to the HMCS6800 Bus via an eight
bit bidirectional data bus, two Chip Select lines, a Read/Write
line, and eleven address lines. These signals, in conjunction with
the HMCS6800 VMA output, permit the MPU to control the
HD6846.
•

Bidirectional Data Bus (0 0 -0 7 )

The bidirectional data lines (Do'" D7 ) allow the transfer of
data between the MPU and the HD6846. The data bus output
drivers are three-state devices which remain in the highimpet41nce (Off) state except when the MPU performs an
HD6846 register or ROM read (R/W = 1 and I/O Registers or
ROM selected).
•

Chip Select (CS Or CS 1 )

The CS o and CS I inputs are used to select the ROM or I/O
timer of the HD6846. They are mask programmed to be active
"High" or active "Low" as chosen by the user.
•

Address Inputs (Ao - A I 0)

The Address Inputs allow any of the 2048 bytes of ROM to
be uniquely selected when the circuit is operating in the ROM
mode. In the I/O-Timer mode, address inputs Ao , AI, and A2
select the proper I/O Register, while A3 through A IO (together
with CS o and CS I) can be used as additional qualifiers in the
I/O Select circuitry. (See the section on I/O-Timer Select for
additional details.)

490

$

Reset (RES)

The active "Low" state of the RES input is used to initialize
all register bits in the I/O section of the device to their proper
values. (See the section on Initialization for Reset conditions for
timer and peripheral registers.)
• Enable (E)

This signal synchrOnizes data transfer between the MPU and
the HD6846. It also performs an equivalent synchronization
function on the external clock, reset, and gate inputs of the
HD6846 Timer section.
•

ReadlWrite (R/W)

This signal is generated by the MPU and is used to control
the direction of data tran.E"er on the bidirectional data pins. A
"Low" level on the R/W input enables the HD6846 input
buffers and data is transferred to the circuit during the E pulse
when the part has been selected. A "High" level on the R/W
input enables the output buffers and data is transferred to the
MPU during E when the part is selected.
•

Interrupt Request (I RQ)

The active "Low" IRQ output acts to interrupt the 'MPU
through logic included on the HD6846. This output utilizes an
open drain configuration and permits other interrupt request
outputs from other circuits to be connected in a wire-OR
configuration.
•

Peripheral Data (P O"'P7 )

The peripheral data lines can be individually programmed as
either inputs or outputs via the Data Direction Register. When
programmed as outputs, these lines will drive two standard TTL

HITACHI

------------------------------------------------------------------HD6846
external clock. The fourth Enable pulse decrements the internal
counter. This does not affect the input frequency; it merely
creates a delay between a clock input transition and internal
recognition of that transition by the HD6846. All references to
CTC inputs in this document relate to internal recognition of
the input transition. Note that a clock transition which does not
meet setup and hold time specifications may require an
additional Enable pulse for recognition.
When observing recurring events, a lack of synchronization
will result in either "System jitter" or "Input jitter" being
observed on the output of the HD6846 when using an
asynchronous clock and gate input signal. "System jitter" is the
result of the input signals being out of synchronization with
Enable, permitting signals with marginal set-up and hold time to
be recognized by either the bit time nearest the input transition
or subsequent bit time. "Input jitter" can be as great at the time
between the negative going transitions of the input signal plus
the system jitter if the first transition is recognized during one
system cycle, and not recognized the next cycle or vice-versa.

loads (3.2 rnA). They are also capable of sourcing up to 1.0 rnA
at 1.5 Volts (Logic "1" output.)
When programmed as inputs, the output drivers associated
with these lines enter a three-state (high impedance) mode.
Since there is no internal pull-up for these lines, they represent
a maximum lOJ.lA load to the circuitry driving them -regardless of logic state.
A logic zero at the RES input forces the peripheral data lines
to the input configuration by clearing the Data Direction
Register. This allows the system designer to preclude the
possibility of having a peripheral data output connected to an
external driver output during power-up sequence.
•

Interrupt Input (CPt)

Peripheral input line CP 1 is an input-only that sets the
Interrupt Flags of the Composite Status register. The active
transition for this Signal is programmed by the peripheral
control register for the parallel port. CP 1 may also act as a
strobe for the peripheral data register when it is used as an input
latch. Details for programming CP 1 are in the section on the
parallel peripheral port.
(Note)
Unexpected noise may occur on the peripheral data line
when the peripheral data register is loaded with .. 1". This
erroneous noise may occur only when peripheral data line is
specified as output and the peripheral data register has
already been loaded with "1". Note that peripheral data line
doesn't keep "High" level continuously in the case write
peripheral data register operation is executed.
•

•

Peripheral Control (CP 2 )

Peripheral Control line CP 2 may be programmed to act as an
Interrupt input or Peripheral Control output. As an input, this
line has high impedance and is compatible with standard TTL
voltage levels. As an output, it is also TTL compatible and may
be used as a source of 1 rnA at 1.5 V to directly drive the base
of a Darlington transistor switch. This line is programmed by
the Peripheral Control Register.
•

•

FUNCTIONAL SELECT CIRCUITRY

•

I/O-Timer Select Circuitry

CS o and CS I are user programmable. Any of the four binary
combinations of CSo and CS I can be used to select the ROM.
Likewise, any other combination can be used to select the
I/O-Timer. In addition, several address lines are used as
qualifiers for the I/O-Timer. Specifically, A3 = A4 = As =
logical "0". A6 can be programmed to a "1", "0", or don't care.
A7 = As = A9 = A IO = don't care or one line only may be
programmed to a logical .. 1". Figure 14 outlines in diagrammatic form the available chip select options.

Counter Timer Output (CTO)

The Counter Timer Output is software programmable by
selected bits in the timer/counter control register. The mode of
operation is dependent on the Timer control register, the gate
input, and the clock source. The output is TTL compatible.
•

Gate Inputs (CTG)

The input pin CTG accepts an asynchronous TTL-compatible
signal which is used as a trigger or a clock gating function to the
Timer. The gating input is clocked into the HD6846 by the
Enable Signal in the same manner as the previously discussed
clock inputs. That is, a CTG transition is recognized on the
fourth Enable pulse (provided setup and hold time requirements
are met), and the "High" or "Low" levels of the CTG input
must be stable for at least one system clock period plus the sum
of setup and hold times. All references to CTG transition in this
document relate to internal recognition of the input transition.
The CTG input of the timer directly affects the internal
16-bit counter. The operation of CTG is therefore independent
of the ..;- 8 prescaler selection.

External Clock Input (CTC)

Input pin CTC will accept asynchronous TTL voltage level
signals to be used as a clock to decrement the Timer. The "High"
and "Low" levels of the external clock must be stable for at
least one system clock period plus the sum of the setup and
hold times for the inputs. The asynchronous clock rate can vary
from de to the limit imposed by System E, setup, and hold
times.
The external clock input is clocked in by Enable pulses.
Three Enable periods are used to synchronize and process the

•

Internal Addressing

Seven I/O Register locations within the HD6846 are
accessible to the MPU data bus. Selection of these registers is
controlled by Ao, A I, and A2 (as shown in Table 1) provided
the I/O timer is selected. The combination status register is
Read-only; all other Registers are Read and Write.

Input

CTC Input
Recog.
Input

Output

~

E

,.....--------1Jr-- 1----1

' - - _ _..J

I----~

.

either
here

Ir-----JJ~ ___L

"H

I

or

$

___ J

1 System
Bit Time
Jitter

ere

HITACHI

491

HD6846------------------------------------------------------------------CS,

) - - - - + I/O-TIMER
SELECT

r
Figure 14 I/O·Timer Select Circuitry

combination of the chip select inputs.

Table 1 Internal Register Addresses
REGISTER SELECTED
Combination Status Register
Peripheral Control Register
Data Direction Register
Peripheral Data Register
Combination Status Register
Timer Control Register
Timer MSB Register
Timer LSB Register
ROM Address

A2

0
0
0
0
1
1
1
1
x

AI
0
0

Ao

ROM Select

0

The active levels of CS o and CS I for ROM and I/O select are
a user programmable option. Either CSo or CS I may be programmed active "High" or active "Low", but different codes
must be used for ROM or I/O select. CSo and CSt are mask
programmed simultaneously with the ROM pattern. The ROM
Select Circuitry is shown in Figure 15.

1

1
1

0

0
0

0

1
1
x

0

1
1
1
x

Initialization

When the RES input has accepted a "Low" signal, all
registers are initialized to the reset state. The data direction and
peripheral data registers are cleared. The Peripheral Control
Register is cleared except for bit 7 (the RES bit). This forces the
parallel port to the input mode with Interrupts disabled. To
remove the RES condition from the parallel port, a "0" must be
written into the Peripheral Control Register bit 7 (PCR7).
The counter latches are preset to their maximal count, the
Timer control register bits are reset to zero except for Bit 0
(TCRO is set), the counter output is cleared, and the counter
clock disabled. This state forces the timer counter to remain in
an inactive state. The combination status register is cleared of all
interrupt flags. During timer initialization, the reset bit (CCRO)
must be clear~d.
ROM

The Mask Programmable ROM section is similar in operation
to other ROM products of the HMCS6800 Microprocessor
family. The ROM is organized as 2048 words of 8·bits to
provide read-only storage for a minimum microcomputer
system. The ROM is active when selected by the unique

492

Figure 15 ROM Select Circuitry

• TIMER OPERATION

The Timer may be programmed to operate in modes which
fit a wide variety of applications. The device is fully bus
compatible with the HMCS6800 system, and is accessed by
Load and Store operations from the MPU.
In a typical application, the timer will be loaded by storing
two bytes of data into the counter latch. This data is then
transferred into the counter during a Counter Initialization
cycle. The counter decrements on each subsequent clock cycle
(which may be Enable or an external clock) until one of several
predetermined conditions causes it to halt or recycle. Thus the
timer is programmable, cyclic in nature, controllable by external
inputs or MPU program, and accessible to the MPU at any time.

_HITACHI

HD6846
•

Counter Latch Initialization

The Timer consists of a 16-bit addressable counter and two
8-bit addressable latches. The function of the latches is to store
a binary equivalent of the desired count value minus one.
Counter initialization results in the transfer of the latch
contents of the counter. It should be noted that data transfer to
the counters is always accomplished via the latches. Thus, the
counter latches may be accurately described as a I6-bit
"counter initialization data" storage register.
In some modes of operation, the initialization of the latches
will cause simultaneous counter initialization (Le. immediate
transfer of the new latch data into the counters). It is, therefore,
necessary to insure that all-16-bit of the latches are updated
simultaneously. Since the HD6846 data bus is 8·bit wide, a
temporary register (MSB Buffer Register) is provided for in the
Most Significant Byte of the desired latch data. This is a
"write-only" register selected via address lines Ao , A 1, and A z .
Data is transferred directly from the data bus to the MSB Buffer
when the chip is selected, R/W is "Low", and the timer MSB
register is selected (Ao ="0", A 1 =A z ="I ").
The lower 8-bit of the counter latch can also be referred to as
a "write-only" register. Data Bus information will be transferred
directly to the LSB of a counter latch when the chip is selected,
R/W is "Low" and the Timer LSB Register is selected (Ao =A1
= A z = "1 "). Data from the MSB Buffer will automatically be
transferred into the Most Significant Byte of the counter latches
Simultaneously with the transfer of the Data Bus information to
the Least Significant Byte of the Counter Latch. For brevity,
the conditions for this operation will be referred to henceforth
as a "Write Timer Latches Command."
The HD6846 has been designed to allow transfer of two
bytes of data into the counter latches from any source, provided
the MSB is transferred first. In many applications, the source of
data will be an HMCS6800 MPU. It should therefore be noted
that the 16-bit store operations of the HMCS6800 family
microprocessors (STS and STX) transfer data in the order
required by the HD6846. A Store Index Register instruction,
for example, results in the MSB of the index register being
transferred to the selected address, then the LSB of the index
register being written into the next higher location. Thus, either

the index register or stack pointer may be transferred directly
into a selected counter latch with a single instruction.
A logic zero at the RES input also initializes the counter
latches. All latches will assume maximum count (65,535)
values. It is important to note that an internal reset (Bit zero of
the Timer/Control Register Set) has no effect on the counter
latches.
•

Counter Initialization

Counter Initialization is defined as the transfer of data from
the latches to the counter with attendant clearing of the
Individual Interrupt Flag associated with the counter. Counter
Initialization always occurs when a reset condition (external
RES = "0" or TCRO = "1") is recognized. It can also occur
(dependent on The Timer Mode) with a Write Timer Latches
command or recognition of a negative transition of the CTG
input.
Counter recycling or reinitialization occurs when a clock
input is recognized after the counter has reached an all·zero
state. In this case, data is transferred from the Latches to the
Counter, but the Interrupt Flag is unaffected.
•

Timer Control Register

The Timer Control register (see Table 2) in the HD6846 is
used to modify timer operation to suit a variety of applications.
The Timer Control Register has a unique address space (Ao =
"I, A1 = "0", A z = "I") and therefore may be written intoat
any time. The least significant bit of the Control Register is used
as an Internal Reset bit. When this bit is a logic zero, all timers
are allowed to operate in the modes prescribed by the remaining
bits of the timer control register.
Writing "I" into Timer Control Register Bit 0 (TeRO) causes
the counter to be preset with the conents of the counter latches,
all counter clocks are disabled, and the timer output and
interrupt flag (Status Register) are reset. The Counter Latch and
Timer/Control Register are undisturbed by an Internal Reset
and may be written into regardless of the state of TCRO.
Timer Control Register Bit I (TCRI) is used to select the
clock source. When TCRI = "0", the external clock input CTC
is selected, and when TCRI ="I", the timer uses Enable.

Table 2 Format for Timer/Counter Control Register
CONTROL
REGISTER
BIT

STATE

TCRO

0

TCRl

0

BIT DEFINITION
I nternal Reset

Timer in Preset State

1
Clock Source

0
1

TCR3
TCR4
TCR5

x
x
x

TCR6

0
1

TCR7

0

Timer uses External Clock (CTC)
Timer uses - (2 frames· 1 byte'

~

Check
IUm

Byte
count

record

date

check IUm

HD6846
3) Example of load module format

1
2
3
4
5
6
7

8
9
10

frame
start of record
type of record
byte count
start address of
data in this
record
data
data
data

n

check
sum

CC=30
header
record
53
30
30
36
30
30
30
30
34
38
34
34
35
32
32
42

S
0

06

0000

48-H
44-D
52-R
2B
(check sum)

CC=31
data
record
53
31
31
36
31
31
30
30
39
38
30
32

5a
38

Check sum of header record above is complement of 1 of (06
+ 00 + 00 + 48 + 44 + 52)16 i.e., 2B.
The start address of data record is incremented for each one
byte data, then is compared to the next address in data record
and is checked to be sequential or not.
When it is not sequential, hexadecimal 00 is ftlled as data for
that address automatically.
A example of type out of paper tape in HMCS6800 load
module format is shown below.

header record ... SOO600004844522B
data record ...... Sl13F0007EF5587EF7897EFAA 77EF9C07EF9C47E24
data record ...... Sl12FOl OFA657EFA8B7EF AA07EF9OC7EFA24 7E06
end of me record .... S9030000FC

S

16

1100

98

CC=39
end of file
record
53
39
30
33
30
30
30
30
46
43

S
9

---03

0000

Fe (check sum)

02

AS
(check sum)

4) Four types of data of ROM code are able to be processed. In
any case, header record before data record is needed and so
as end of ftle record after data record.
(a) No vacancy in ROM
Data record is filled with full ROM record of one chip.
Therefore address is sequential. Initial ROM address in "Confirmation sheet of specification" is O.
(b) Vacancy in former part of ROM
Desired initial address shall be fIlled in initial ROM address
column in "Confirmation sheet of specification". Data of 00 are
filled automatically for vacant address.
(c) Vacancy in the middle of ROM
Data of 00 are filled in for vacant address. Initial ROM
address for data I is 0 and desired initial address for data II shall
be described in "Confirmation sheet of specification".
(d) Vacancy in later part of ROM
When end of file record is read out, data of 00 are filled in
thereafter.

ROM

vacancy
(filled with 00)

vacancy
(filled with 00)

(a)

(bl

(cl

~HITACHI

(dl

503

HD6846--------------------------------------------________________
(Example) Paper tape whose data record is S1141920B6FC .....

000

00

0

o
0 00000
0 0
ooooooooooooooooooogoooooggogg~~g~OOOOOOOOOOOOOOOOOOOO000
o
00000000
0000000

o

0000

0

1

S
1

4

0
0

B

2

9

0

0

00000
00000
000
00000 0
F

6

F
C

4
46

4
6

• BNPF format
1) Each word is expressed as BNPF slice which begins word
opening mark B, has 8 character bit contents shown by P or
N and finishes with end mark F.

(Example) OF in hexadecimal code is expressed as shown below (paper tape).

00000
0000

0
0

0000000000000000000000000000000000

0000
0000
0000000000

o

f11tU~~unn

BNNNN

PPPPF
bit weight

2) Any contents between F of the fust slice and B of next slice
are disregarded.
3) Bit pattern (BNPF) slice for all ROM address shall be
indicated. Initial ROM address in "Confirmation sheet of
specification" is, therefore always 0 for BNPF.
B
shows beginning of the word
N
shows 0 of one bit data
P ..... shows 1 of one bit data
F ..... shows end of the word
Note 1) X can be used expect for P and N for indication of
word contents of BNPF slice. This X means that bit
can be either P or N (don't care). X shall be
determined by HITACHI for testing and shall be

504

Note 2)

Note 3)

eHITACHI

informed to the customer in confumation table.
Expression of B*nF can be used for indicating that
the same contents of foregoing slice are applicable
from this word to following n words.
For example, when B*4F is indicated at 10th word
position, the contents of 9th word are repeated for
10,11,12 and 13th word.
(Content of X is not always repeated even in this
case.)
n is grater than 1 and less than final address of ROM.
When vacancy of ROM exists, combination of Note
1) and Note 2) is usefull.

------------------------------------------~--------------------HD6846

Customer

HITACHI

ROM code
Customers PIN
chip select &
other information
Choice
of Media

"Organizational Data"
"Specification Confirmation Sheet"
"ROM code"

or

same as
input
medium

information

Customer's
responsibility
Mask
making

-----+______

report ....

Figure 20 Flow chart of Mask ROM Development

_HITACHI

505

HD6850,HD68A50
ACIA (Asynchronous, Communications
Interface Adapter)
The HD6850 Asynchronous Communications Interface
Adapter provides the data fonnatting and control to interface
serial asynchronous data communications infonnation to bus
organized systems such as the HMCS6800 Microprocessing Unit.
The bus interface of the HD6850 includes select, enable,
read/write, interrupt and bus interface logic to allow data
transfer over an 8-bit bi-directional data bus. The parallel data
of the bus system is serially transmitted and received by the
asynchronous data interface, with proper fonnatting and error
checking.
The functional configuration of the ACIA is programmed via
the data bus during system initialization. A programmable
Control Register provides variable word lengths, clock division
ratios, transm'it control, receive control, and interrupt control.
For peripheral or modem operation three control lines are
provided.
•
•
•
•
•
•
•

FEATURES
Serial/Parallel Conversion of Data
Eight and Nine-bit Transmission
Insertion and Deleting of Start and Stop Bit
Optional Even and Odd Parity
Parity, Overrun and Framing Error Checking
Peripheral/Modem Control Functions (Clear to Send
CTS, Request to Send RTS, Data Carier Detect DCD)

•

Optional";' 1, ..;. 16, and";' 64 Clock Modes

HD6850P, HD68A50P

(DP-24)

•

~N ARRANGEMENT

• Up to 500kbp's Transmission
• Programmable Control Register
• N-channel Silicon Gate Process
• Compatible with MC6850 and MC68A50

•

BLOCK DIAGRAM

Tx CLK 4
E
14

(Top View)

13
8

6

~o

T. Data

11

24 CTS
22
21

20
19
18
17
16

7

IRQ

' - - - -.......~---- 23 DCD

5

RTS

2

Ax Data

15

R. CLK

506

$

HITACHI

---------------------------------------------------------H06850,H068A50
• ABSOLUTE MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

Vee *

-0.3 - +7.0

V

Input Voltage

Yin *

-0.3 - +7.0

V

Operating Temperature

Topr
Tstg

-20 - +75

°c

-55 - +150

°c

Item

Storage Temperature
* With respect to Vss (SYSTEM GNO)
(NOTE)

Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be
under recommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.

• RECOMMENDED OPERATING CONDITIONS
Item

Symbol

min

typ

max

Unit

Vee *
V 1L *

4.75

5.0

5.25

V

-0.3

-

0.8

V

V 1H *

2.0

-

Vee

V

Topr

-20

25

75

°c

Supply Voltage
Input Voltage
Operating Temperature
• With respect to Vss (SYSTEM GNO)

• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vcc=5V±5%, VSS=OV, Ta=-2Q-+75°C, unless otherwise noted.)
min

typ*

max

Unit

Input "High" Voltage

All Inputs

V 1H

2.0

-

Vee

V

Input "Low" Voltage

All Inputs

V 1L

-0.3

-

0.8

V

Input Leakage Current

RAN,CSo ,CS 1 ,CS2 ,E

lin

Vin=Q-5.25V

-2.5

-

2.5

I1A

0 0 -0 7

ITS1

V in =0.4-2.4V

-10

-

10

I1A

IOH=-205I1A, Enable
Pulse Width ~ 2511s

2.4

-

-

10 H--10()p.A, Enable
Pulse Width ~ 2511s

2.4

-

-

Item

Three-State (Off State)
Input Current

Symbol

0 0 -0 7

I

Output "High" Voltage

V OH
TxOata, RTS

Test Condition

V

Output "Low" Voltage

All outputs

VOL

10L =1.6mA,Enable
Pulse Width ~ 25i-ts

-

-

0.4

V

Output Leakage Current
(Off State)

IRO

I LOH

VOH=2.4V

-

-

10

I1A

300

525

mW

-

12.5

-

-

7.5

-

-

10

-

-

5.0

Power Dissipation

Po

0 0 -0 7
Input Capacitance

E,IxCLK, RxCLK,
RAN, RS, RxOata, CS o ,
CS 1 , CS;-,
OCO

Cin

Vin=OV, Ta=25°C,
f=1.0MHz

Cout

Vin=OV, Ta=25°C,
f=1.0MHz

crs,

Output Capacitance

RT-S, TxOata
IRO

$

HITACHI

pF

pF

507

HD6850,HD68A50------------------------------------------------------• AC CHARACTERISTICS
1. TIMING OF DATA TRANSMISSION

Minimum Clock Pulse Width
Clock Frequency

Test
Condition

Symbol

Item

min

typ

-

-

+16, +64 Modes

PWCL

Fig. 1

600

+16, +64 Modes

PWCH

Fig. 2

600

+1 Mode

fc

+16, +64 Modes

max

Unit

-

ns

-

ns

500

kHz

800

t Too

Fig.3

-

-

1.0

J1.s

Receive Data Setup Time

+ 1 Mode

t ROSU

Fig. 4

500

+ 1 Mode

tROH

Fig. 5

500

-

ns

Receive Data Hold Time

tlR

Fig. 6

-

1.2

J1.s

tRTS

Fig. 6

-

-

1.0

J1.s

1.0*

J1.S

Clock-to-Data Delay for Transmitter

I RQ Release Time

RTS Delay Time
Rise Time and Fall Time

* 1.0 IlS or

-

t r , tf

Except E

ns

10% of the pulse width, whichever is smaller.

2. BUS TIMING CHARACTERISTICS
1) READ
Item

Symbol

Test
Condition

min

HD6850'
typ
max

HD68A50
min

typ

max

Unit

-~_s_

0.666

-

25

0.28

-

25

0.43

-

-

0.28

-

-

J1.S

tAS

Fig.7

140

-

-

140

-

-

ns

Data Delay Time

tooR

Fig. 7

-

-

ns

Fig. 7-

10

10

tAH

Fig.7

10

10

-

-

ns

Address Hold Time

-

-

220

tH

-

320

Data Hold Time
Rise and Fall Time for Enable
Input

tEr, tEf

Fig. 7

-

-

25

-

-

25

ns

Symbol

Test
Condition

HD6850
typ
max

min

HD68A50
typ
max

Unit

Enable Cycle Time

tcycE
PW EH

Fig.7

1.0

Enable "High" Pulse Width

Fig.7

0.45

Enable "Low" Pulse Width

PW EL

Fig. 7

Setup Time, Address and RNI valid
to Enable positive transition

-

J1.s

--1----

ns

2) WRITE
Item
Enable Cycle Time

min

-

0.666

-

-

J1.S

25

0.28

J1.S

-

0.28

-

25

0.43

-

-

J1.S

Fig.8

140

-

-

140

-

-

ns

-

ns
ns

25

ns

tcycE
PW EH

Fig.8

1.0

Enable "High" Pulse Width

Fig. 8

0.45

Enable "Low" Pulse Width

PW EL

Fig. 8

Setup Time, Address and R/W
valid to Enable positive transition

tAS

Data Setup Time

tosw

Fig. 8

195

-

-

80

Data Hold Time

tH

Fig. 8

10

-

-

10

Address Hold Time

tAH

Fig. 8

10

-

-

10

-

Rise and Fall Time for Enable
Input

tEr, tEf

Fig. 8

-

-

25

-

-

508

eHITACHI

ns

-------------------------------------------------------HD6850,HD68A50

Tx ClK

Tx

or

or

Rx ClK

Rx

PWCH

Figure 2 Clock Pulse Width, "High" State

Figure 1 Clock Pu Ise Width, "Low" State

Rx Data

tTDD~
2.4V

Tx Data
___________

~O~.4~V~

_______

Figure 4 Receive Data Setup Time (71 Mode)

Figure 3 Transmit Data Output Delay

2.4V
Q.4V

IRQ ________________________

-J~

* (1) IRQ Release Time applied to Rx Data Register read operation.
(2) IRO Release Time applied to Tx Data Register write operation.
(3) IRO Release Time applied to control Register write TIE = 0,
RIE = 0 operation.

** IRQ Release Time applied to Rx Data Register read operation

Figure 5 Receive Data Hold Time (71 Mode)

right after read status register, when IRO is asserted by DCD
riSing edge.
Note that followings take place when IRO is asserted by the
detection of transmit data register empty status. IRO is
released to "High" asynchronously with E signal when
CTS goes "High". (Refer to Figure 14)

(Note)

Figure 6 RTS Delay and IRQ Release Time

Enable

RS, CS, R/W

Data Bus

Figure 7 Bus Read Timing Characteristics
(Read information from ACIA)

$

HITACHI

509

H06850,H068A50------------------------------___________________________

Enable

Data Bus

Figure 8 Bus Write Timing Characteristics
(Write information into ACIA)
load B

load A

5.0V (Vee)

(Do -0 7 , RTS, Tx Data)

(IRQ Only)

R L=2.4kn
Test Point

o-....-~---f

C

__--+

Test point

R

~I

5'OV

3kn

'OOP
'

C = 130pF for 0 0 -0 7
R = 11kn for 0 0 -0 7
= 30pF for RTS and Tx Data
= 24kn for RTS and Tx Data
All diodes are 1S2074 ® or Equivalent.

Figure 9 Bus Timing Test Loads

START
BIT

Do

O2

06

i"4--------CHARACTER TIME @ 10 CPS (11 BITS)
100 msec

Figure 10 110 Baud Serial ASCII Data Timing

510

eHITACHI

PARITY
BIT

STOP STOP
BIT
BIT

-----------1

-----------------------------------------------------------HD6850,HD68A50

START
BIT

Do

D.

D.

PARITY STOP
BIT
BIT

D.

t--------CHARACTER TIME @ 15 & 30 CPS (10 B I T S ) - - - - - - - i
(SEE TABLE BELOW)

BAUD RATE

150

300

CHARACTERS/SEC

15

30

BIT TIME (msec)

6.67

3.33

CHARACTER TIME (msec)

66.7

33.3

BIT TIME

= __S_E_C_ _
BAUD RATE

Figure 11 150 & 300 Baud Serial ASCII Data Timing

MARK

I

I
START

I

D.

D.

D.

PARITY

STOP

STOP

NEXT
CHAR.

SPACE

Figure 12 Send a 7 Bit ASCII Char. "H" Even Parity
- 2 Stop Bits H = 48 16 = 1001000 2

• DATA OF ACIA

• ACIA OPERATION

HD6850 is an interface adapter which controls transmission
and reception of Asynchronous serial data. Some exainples of
serial data are shown in Figs. 10 - 12.

• Master Reset

•

INTERNAL STRUCTURE OF ACIA

HD6850(ACIA) provides the following; 8-bit Bi-directional
Data Buses (Do-D 7 ), Receive Data Input (Rx Data), Transmit
Data Output (Tx Data), three Chip Selects (CS o , CS 1 , CS 2 ),
Register Select Input (RS), Two Control Input (Read/Write
(R/W), Enable(E) , Interrupt Request Output(IRQ), Clear-toSend (CTS) to control the modem, Request-to-Send (RTS),
Data Carrier Detect(DCD) and Clock Inputs(Tx CLK, Rx CLK)
used for synchronization of received and transmitted data. This
ACIA also provides four registers; Status Register, Control
Register, Receive Register and Transmit Register.
24-pin dual-in-line type package is used for the ACIA. Internal Structure of ACIA is illustrated in Fig. 13.

$

ACIA has an internal master reset function controlled
by software, since it has no hardware reset pin. Bit 0 and
bit I of control register should be set to "11" to execute
master reset, also b~ and bit 6 should be programmed to
get predetermined RTS output accordingly. To release the
master reset, the data other than "11" should be written into
bit 0, bit 1 of the control register. When the master reset is
released, the control register needs to be programmed to get
predetermined options such as clock divider ratios, word
length, one or two stop bits, parity (even, old, or none), etc.
.-.l! may happen that "Low" level output is provided in
IRQ pin during the time after power-on till master reset. In
the system using ACIA, interrupt mask bit of MPU should be
released after the master reset of ACIA. (MPU interrupt should
be prohibited until MPU program completes the master reset
of ACIA.) Transmit Data Register (TDR) and Receive Data
Register (RDR) can not be reset by master reset.

HITACHI

511

HD6850.HD68A50--------------------------------------_________________

r-------------------------------,
I~~l ---i
i
ACIA

TRANSMIT DATA REGISTER (TORI

~+';;~ ~

WRITE ONLY

i

I 0, I 0.1 0.1 0.1 0.1 0, I0, I 0.1

SERIAL DATA OUT

Tx Data;

t

~l_ }~.~JIJ/)
LINES IPARALLEL
TO SERIAL CONVERTERI

DATA
LINES
TO
OR
FROM
MPU

I
I

WAITE
ONLY

I

II

i

A.ClK

iiI

READ

I

ONLY

SERIAL DATA IN

00

T.ClK

I

~Eg~~VE

IRa

DI

O2

OJ

0..

0,

O.

0,

RECEIVE DATA REGISTER IRDRI
AM

E

AS

~?~~E

ENABLE

ffi

~-r----r---l---r--r
INT:f.?:UPT

TAANSMIT
CLaCK

MPU

R. Data

-r-rr-r -rCS.

cs,

CS,

DcD

i~;:L ~

IAOI
AEGISTER

~~~~M

~~~~T

~I~~~ESS

MPU
ADDAESS
liNE

I
I

J

~f~~EST

SE~ECT

CHIP
FADM MPU

RTs

I

MODEM
DATA

g~~~~~R
FROM
MODEM

Figure 13 Internal Structure of ACIA

• Transmit
A typical transmitting sequence consists of reading the ACIA
Status Register. either as a result of an interrupt or in the
ACIA's tum in a polling sequence. A character may be written
into the Transmit Data Register if the status read operation has
indicated that the Transmit Data Register is empty. This
character is transferred to a Shift Register where it is serialized
and transmitted from the Transmit Data output preceded by a
start bit and followed by one or two stop bits. Internal parity
(odd or even) can be opti2 Clock.
ReadlWrite (R/W)
The RjW line is a high impedance input that is TTL
compatible and is used to control the direction of data flow
through the ACIA's input/output data bus interface. When R/W
is "High" (MPU Read cycle), ACIA output drivers are turned on
and a selected register is read. When it is "Low", the ACIA
output drivers are turned off and the MPU writes into a selected
register. Therefore, the R/W signal is used to select read-only or
write-only registers within the ACIA.
Chip Select (CS o , CS 1 , CS 2 )
These three high impedance TTL compatible input lines are
used to address the ACIA. The ACIA is selected when CS o and
CSt are "High" and CS2 is "Low". Transfers of data to and
from the ACIA are then performed under the control of the
Enable signal, Read/Write, and Register Select.

Clock Inputs
Separate high impedance TTL compatible inputs are provided for clocking of transmitted and received data. Clock
frequencies of 1, 16 or 64 times the data rate may be selected.
Transmit Clock (Tx ClK)
The Tx CLK input is used for the clocking of transmitted
data. The transmitter initiates data on the negative transition of
the clock.
Receive Clock (Rx ClK)
The Rx CLK input is used for synchronization of received
data. (In the -;- 1 mode, the clock and data must be
synchronized externally.) The receiver samples the data on the
positive transition of the clock.
• Serial Input/Output Lines
Receive Data (Rx Data)
The Rx Data line is a high impedance TTL compatible input
through which data is received in a serial format. Synchronization with a clock for detection of data is accomplished internally when clock rates of 16 or 64 times the bit rate are used. Data
rates are in the range of 0 to 500 kbps when external
synchronization is utilized.
Transmit Data (Tx Data)
The Tx Data output line transfers serial data to a modem or
other peripheral. Data rates in the range of 0 to 500 kbps when
external synchronization is utilized.
Modem Control
The ACIA includes several functions that permit limited
control of a peripheral or modem. The functions included are
CTS, RTS and DCD.
Clear-to-Send (CTS)
This high impedance TTL compatible input provides automatic control of the transmitting end of a communications link
via the modem CTS active "Low" output by inhibiting the
Transmit Data Register Empty (TDRE) status bit. (Refer to
Figure IS.)
Request-to-Send (RTS)
The RTS output enables the MPU to control a peripheral or
modem via the data bus. The RTS output corresponds to the
state of the Control Register bits CRS and CR6. When CR6=O
or both CR5 and CR6=1, the RTS output is "Low" (the active
state). This output can also be used for Data Terminal Ready
(DTR). (Refer to Figure 15.)

Register Select (RS)
The RS line is a high impedance input that is TTL
compatible. A "High" level is used to select the Transmitj
Receive Data Registers and a "Low" level the Control/Status
Registers. The RjW signal line is used in conjunction with
Register Select to select the read-only or write-only register in
each register pair.
Interrupt Request (IRQ)
IRQ is a TTL compatible, open-drain (no internal· pullup),
active "Low" output that is used to interrupt the MPU. The
IRQ output remains "Low" as long as the cause of the interrupt
is present and the appropriate interrupt enable within the ACIA
is set.

$

HITACHI

515

HD6850,HD68A50--------------------------------------------------______
Tx Data

TORE flag
Control Register
Write
Status Register
Read
Tx Data Register
Write

Transmit operation is not disabled, even if CTS goes "High".

Figure 15 RTS and CTS Timing Chart (Example of 2 bytes transmission)

Data Carrier Detect (OCO)

DC'D

is the input signal corresponding to the "carrier
detect" signal which shows carrier detect of modem.
DCD signal is used to control the receiving operation. When
DCD input goes "High", ACIA stops all the receiving operation
and sets receiving part in reset status. It means that receive
shift register stops shifting, error detection circuit and synchronization circuit of receive clock are reset. When DCD is
in "High" level, the receiving part of ACIA is kept in initial

status and the operation in the receiving part is prohibited.
When DCD goes "Low", the receiving part is allowed to
receive data. In this case, the following process is needed to
reset DCD flag and restarts the receive operation. (Refer to
Figure 16.)
(I) Return DCD input from "High" to "Low" .
(2) Read status register. (DCD flag ="1 ")
(3) Read receive data register (Uncertain data will be read.)

DCD input
DCD flag
fR'O
(RIE

="''''

Status Register Read

Rx Data Register Read

~I
All the receiving operation are prohibited and ACIA is stopped
in this period.

Figure 16

516

OCD Flag Timing Chart

_HITACHI

H 06350,H 063A50,H 063 850CMOS ACIA (Asynchronous Communications I nterface Adapter)
The HD63S0 CMOS Asynchronous Communications Interface Adapter provides the data formatting and control to
interface serial asynchronous data communications information to bus organized systems such as the HMCS6800 Microprocessing Unit.
The bus interface of the HD63S0 includes select, enable,
read/write, interrupt and bus interface logic to allow data
transfer over an 8-bit bi-directional data bus. The parallel data
of the bus system is serially transmitted and received by the
asynchronous data interface, with proper formatting and
error checking.
The functional configuration of the ACIA is programmerl
via the data bus during system initialization. A programmable
Control Register provides variable word lengths, clock division
ratios, transmit control, receive control, and interrupt control.
F9r peripheral or modem operation three control lines are
provided. Exceeding Low Power disSipation is realized due
to adopting CMOS process.

HD6350P, HD63A50P, HD63850P

(DP-24)
•

PIN ARRANGEMENT

•
•
•
•
•
•
•
•

FEATURES
Low-Power, High-Speed, High-Density CMOS
Compatible with NMOS ACIA (HD6850)
Serial/Parallel Conversion of Data
Eight and Nine-bit Transmission
Optional Even and Odd Parity
Parity, Overrun and Framing Error Checking
Peripheral/Modem Control Functions (Clear to Send
CTS, Request to Send RTS, Data Carrier Detect DCD)
• Optional + 1, + 16, and + 64 Clock Modes
• Up to 500kbpsTransmission
•

BLOCK DIAGRAM

Tx ClK 4

E
(Top View)

R/W
CSo

~--- 6

~
RS

Tx Data

' - - - - - 24 CTS

22
21
20
19
18
17
18
15

.....::::::::::::::=--

L-_ _ _

Lr---"--~-+---

Vee.Pin 12
V... Pin 1

7 IRQ
23 Deli

___ 5 m

2

Ax Data

Ax elK 3 - - - - - - - - - -.....

~HITACHI

517

HD6350,HD63A50,HD63B50,-------------------------------------------------• ABSOLUTE MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

Item

Vee

V

Input Voltage

Vin -

-0.3 - +7.0
-0.3 - +7.0

Maximum Output Current-Operating Temperature

1101

-

V
mA

10
-20 - +75

°c
To~
Storage Temperature
Tstg
-55 - +150
°c
* With respect to Vss (SYSTEM GNO)
** Maximum output current is the maximum current which can flow out from one output terminal or

I/O common terminal (Do - 0,. R'i'S. Tx Data. IRO).
(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be
under recommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.

•

RECOMMENDED OPERATING CONDITIONS
Item

Symbol

min

typ

max

Unit

Vee
VIL

4.5

5.0

5.5

V

0

0.8

V .-

2.2

-

-20

25

Supply Voltage
Input "low" Voltage
Input "High"
Voltage

Do - 0 7 , RS, Tx ClK, DCD, CTS,
Rx Data

V IH

CSo , CS 2 , CS}, R/W, E, Rx ClK

Operating Temperature

-

2.0

Topr

Vee

V

Vee
75

°c

* With respect to Vss (SYSTEM GND)

• ELECTRICAL CHARACTERISTICS
•

DC CHARACTERISTICS (Vcc =5V±10%, Vss = OV, Ta= -20-+75°C, unless otherwise noted.)
Item

Input "High" Voltage
Input "low" Voltage

Symbol
Do - D,. RS. Tx ClK.
[)c[).
Rx Data

rn.

CSo • CS 2 • CS 1 • Rm, E,
RxClK
All Inputs

min

typ

max

!

-

Vee

I

-

Vee

-

O.B

V

-2.5

-

2.5

p.A

-10

-

10

p.A

4.1

-

-

Vee-0.1

-

-

4.1

-

-

Vee- 0 . 1

-

-

12.5

-

-

7.5

-

5.0

2.0
V 1H
2.2

Input leakage Current

RIW, CS o , CS 1 , CS 2 , E

Three·State (Off State)
Input Current

0 0 -0 7

ITS'

V in

=0 -

V in

= 0.4 -

IOH

Vee
Vee

= -400 p.A

IOH:5: -10p.A

V OH

IOH

Tx Data, RTS

= -400p.A

IOH:5: -10p.A

Output "Low" Voltage

All Outputs

VOL

IOH

= 1.6 mA

-

Output leakage Current
(Off State)

IRQ

I LOH

VOH

= Vee

-

Input Capacitance

Do - 0 7
E, Tx ClK, Rx ClK,
RIW, RS, Rx Data, CSo,
CS" CS 2 , CTS, DCD

Cin

f

Cout

V in

-

f

-

= OV, Ta = 25°C,
= 1.0 MHz
E = 1.0 MHz
E = 1.5 MHz
E = 2.0 MHz

• Under transmitting and
Receiving operation
.500 kbps
• Data bus in R/Woperation
Supply Current

518

• Chip is not
selected
.500 kbps
• Under non transmitting
and receiving operation
• Input level (Except E)
V'H min = Vee-O.BV
V'L max = O.BV

= OV, Ta = 25°C,
= 1.0 MHz

V in

RTS, Tx Data
IRQ

lee

!

!

~-

-.-_._-

---- ..

V

V

10

p.A

pF

10

-

3

.... - -

-

4

-

-

5

= 1.0 MHz

-

-

200

E = 1.5 MHz

-

-

250

E = 2.0 MHz

-

-

300

pF
I

mA

p.A

I

$

V

0.4

-

E

Unit

--

-0.3

Do - 0 7

Output Capacitance

!

_.-

V'L
lin

Output "High" Voltage

Test Condition

HITACHI

-------------------------------------------------HD6350,HD63A50,HD63B50
• AC CHARACTERISTICS (Vee = 5.0V ±10%, Vss = OV, Ta = -20 '" +75°C, unless otherwise noted.)
1. TIMING OF DATA TRANSMISSION
Item

Symbol

Test
Condition

PW CL

Fig. 1

+ 1 Mode
Minimum Clock Pulse
Width

+ 16, + 64 Modes
+ 1 Mode

PW CH

+ 16, + 64 Modes
+ 1 Mode

Clock Frequency

HD6350
max

min

max

900

-

650

-

600
900

Fig. 2

600

fc

+ 16,+64 Modes

-

500

~

BOO

Clock·to-Data Delay for Transmitter

tTDD

Fig.3

-

600

Receive Data Setup Time + 1 Mode

tRDSU

Fig. 4

250

-

Receive Data Hold Time

tRDH

Fig. 5

250

IRQ Release Time

tlR

Fig. 6

RTS Delay Time

tRTS
t r , tf

Fig. 6

-

Rise Time and Fall Time

+ 1 Mode

Except E

HD63A50

min

450
650
450

-

-

ns

-

1000

kHz

1500

kHz

460

30

-

ns
ns

500
2BO

540

-

-

1000·

500
2BO

750

100

Unit

max

1000

100

1200
560

HD63850
min

30
-

900
4BO

700
400

-

500

250

ns
ns
ns

ns
ns
ns
ns

• 1.0 liS or 10% of the pulse width, whichever is smaller.

2. BUS TIMING CHARACTERISTICS
1) READ
Item
Enable Cycle Time
Enable "High" Pulse Width
Enable "Low" Pulse Width
Setup Time, Address and R/W Valid
to Enable Positive Transition
Data Delay Time
Data Hold Time
Address Hold Time
Rise and Fall Time for Enable Input

Symbol

Test
Condition

tcycE
PWEH
PWEL

Fig.7
Fig.7
Fig. 7

tAS

Fig.7

tOOR
tH
tAH
tEr, tEf

Fig.7
Fig.7
Fig.7
Fig.7

Symbol

Test
Condition

HD6350
min
max
1000
450
430
BO

20
10

-

290
100

HD63A50
min
max
666
2BO
2BO
60

-

-

1BO
100

-

20
10

25

-

HD63850
min
max

Unit

500
220
210

-

ns
ns
ns

40

-

ns

-

150
100

ns
ns
ns
ns

-

20
10

25

-

-

20

2) WRITE
Item
Enable Cycle Time
Enable "High" Pulse Width
Enable "Low" Pulse Width
Setup Time, Address and R/W
Validto Enable Positive Transition
Data Setup Time
Data Hold Time
Address Hold Time
Rise and Fall Time for Enable Input

HD6350
min
max
1000
450
430

HD63A50
max
min
666
2BO
2BO

-

tcycE
PWEH
PWEL

Fig.B
Fig. B
Fig.B

tAS

Fig. B

BO

-

60

tosw
tH
tAH
tEr, tEf

Fig. B
Fig. B
Fig.B
Fig. B

165
10
10

-

-

BO
10
10

-

25

-

~HITACHI

HD63850
max
min
500
220
210

Unit

-

ns
ns
ns

40

-

ns

-

-

60
10
10

25

-

ns
ns
ns
ns

-

20

519

Tx ClK
or
Ax ClK

Tx
or
Ax

* Tx ClK is V IH

Figure 1 Clock Pulse Width, "Low" State

x

..

2.0V

Figure 2 Clock Pulse Width, "High" State

t TDO

Tx Data

__________-J.

Vcc -2.0V

~,-~O~.4~V~-------

Figure 3 Transmit Data Output Delay

Figure 4 Receive Data Setup Time (+1 Mode)

ATS

----~------~I~~~---

* (11 lAO Aelease Ti"me applied to Ax Data Aegister read operation.
(2) IRO Release Time applied to Tx Data Register write operation.
(3) IRO Release Time applied to control Register write TIE
0,
RIE = 0 operation.

=

Figure 5 Receive Data Hold Time (+1 Mode)

** IRQ Release Time applied to Rx Data Register read operation
right after read status register. when "iRCl is asserted by DCi)
rising edge.
(Note) Note that followings take place when IRQ is asserted by the
detection of transmit data register empty status. TRQ is
reieased to "High" asynchronously with E signal when
CTS goes "High". (Refer to Figure 14)

Figure 6 RTS Delay and IRQ Release Time

Enable

AS. CS, A/Iii

Data Bus

Figure 7 Bus Read Timing Characteristics
(Read information from ACIA)

520

eHITACHI

Enable

Data Bus

Figure 8 Bus Write Timing Characteristics
(Write information into ACIA)
Load B

Load A

5.0V (Vee)

(Do ~D7' RTS, Tx Data)

5'OV

(IRQ Only)

RL = 2.4k!l

~r

3k!l

Test Point 0 -_ _ _--1__---.

Test pOint

lOP
'

C = 130pF for Do ~D7
= 30pF for RTS and Tx Data
R = 10k!l for Do ~ D" Ri'S and Tx Data
All diodes are.1S20749 or Equivalent.

Figure 9 Bus Timing Test Loads

START
BIT

Do

D,

D.

D6

r---------CHARACTER TIME @ 10 CPS (11 BITS)
100 msec

PARITY
BIT

STOP STOP
BIT
BIT

-----------i

Figure 10 110 Baud Serial ASCII Data Timing

~HITACHI

521

HD6350,H063A50,HD63B50------------------------

START
BIT

0,

Do

!--------CHARACTER TIME

05
@

06

PARITY STOP
BIT
BIT

15 & 30 CPS (10 B I T S l - - - - - - I

(SEE TABLE BELOWl

BAUD RATE

150

300

CHARACTERS/SEC

15

30

BIT TIME (msec)

6.67

3.33

CHARACTER TIME (msecl

66.7

33.3

BIT TIME = --~
BAUD RATE

Figure 11 150 & 300 Baud Serial ASCII Data Timing

MARK

I

I
START

I

D.

D.

PARITY

STOP

STOP

NEXT
CHAR.

SPACE

Figure 12 Send a 7 Bit ASCII Char. "H" Even Parity
- 2 Stop Bits H = 48'6 = 10010002

• ACIA OPERATION
• Master Reset

• DATA OF ACIA

HD6350 is an interface adapter which controls transmission
and reception of Asynchronous serial data. Some examples of
serial data are shown in Figs. 10 - 12.
•

INTERNAL STRUCTURE OF ACIA

HD6350(ACIA) provides the following; 8-bit Bi-directional
Data Buses (00 -0,), Receive Data Input (Rx Data), Transmit
Data Output (Tx Data), three Chip Selects (CSo , CS" C8;),
Register Select Input (RS) , Two Control Input (Read/Write:
R/W, Enable: E), Interrupt Request Output(IRQ), Clear-toSend (CTS) to control the modem, Request-to-Send (RTS),
Data Carrier Detect(OCD) and Clock Inputs(Tx CLK, Rx CLK)
used for synchronization of received and transmitted data. This
ACIA also provides four registers; Status Register, Control
Register, Receive Register and Transmit Register.
24-pin dual-in-line type package is used for the ACIA. Internal Structure of ACIA is illustrated in Fig. 13.

522

$

ACIA has an internal master reset function controlled
by software, since it has no hardware reset pin. Bit 0 and
bit 1 of control register should be set to "11" to execute
master reset, also bit 5 and bit 6 should be programmed to
get predetermined RTS output accordingly. To release the
master reset, the data other than "11" should be written
into bit 0, bit 1 of the control register. When the master
reset is released, the control register needs to be programmed
to get predetermined options such as clock divider ratios,
word length, one or two stop bits, parity {even , old, or none),
etc.
It may happen that "Low" level output is provided in
IRQ ·pin during the time after power-on till master reset.
In the system using ACIA, interrupt mask bit of MPU should
be released after the master reset of ACIA. (MPU interrupt
should be prohibited until MPU program completes the master
reset of ACIA.) Transmit Data Register (TOR) and Receive
Data RegiSter (RDR) can not be reset by master reset.

HITACHI

ACIA

r-------------------------------,I

I

VSS

(GNDI - - - - ,

~+C51 ~

TRANSMIT DATA REGISTER ITDRI

WRITE ONLY

i :::'"

I

SERIAL DATA OUT

I 0·1 0.1 0, I 0.1 0, I 0, I0, I 0·1

Tx Oat.;

}:~~)/)/ )
LINES (PARALLEL
TO SERIAL CONVERTERI

P

I
I
I

I
I
I

.-~--r-~--~~~-r--T-~I

r--r--+-~r_-r--+-~r__+--~I

~~--~--~-RE-ALD-O-N~LY~~--~--~:

DATA
LINES
TO
OR
FROM
MPU

I
I

0,

I
0,
0,
4

TO MPU DATA LINES

D.

D"''

(SERIAL TO
PARALLEL
CONVERTER)

Illl'~f ----f':'~t~:~:r:e ~O~'f--

"""

INT::-:O:UPT

CLOCK
TRANSMIT

CLOCK

~~AO

3

tAO)

~~~AL
~~~~M

0

I!
I
I
I

om"

e. ,",.:

~f -j

-lCS'- .3'0

~~EAR

ENABLE

~~6~
MPU

I I 21'cL

WRITE
ONLY

'fSO - -crS'

RECEIVE

I

CONTROL REGISTER ICRI

1

~6aUEST

~---'
CHIP SE ... ECT

REGISTER

FROM MPU

SELECT

AnORESS

FROM

liNES

~~ND

M00EM

OATA

CARRIEk

DETECT

MPU

FROM

AOORESS
LINE

MODEM

Figure 13 Internal Structure of ACIA

• Transmit
A typical transmitting sequence consists of reading the ACIA
Status Register either as a result of an interrupt or in the
ACIA's turn in a polling sequence. A character may be written
into the Transmit Data Register if the status read operation has
indicated that the Transmit Data Register is empty. This
character is transferred to a Shift Register where it is serialized
and transmitted from the Transmit Data output preceded by a
start bit and followed by one or two stop bits. Internal parity
(odd or even) can be optionally added to the character and will
occur between the last data bit and the first stop bit. After the
first character is written in the Data Register, the Status
Register can be read again to check for a Transmit Data Register
Empty condition and current peripheral status. If the register is
empty, another character can be loaded for transmission even
though the first character is in the process of being transmitted
(because of double buffering). The second character will be
automatically transferred into the Shift Register when the first
character transmission is completed. This sequence continues
until all the characters have been transmitted .

the detectkn of the leading mark-space transition ot the start
bit. False start bit delection capability insures that a full half bit
of a start bit has been received before the internal clock is
synchronized to the bit time. As a character is being received,
parity (odd or even) will be checked and the error indication
will be available in the Status Register along with framing error,
overrun error, and Receive Data Register full. In a typical
receiving sequence, the Status Register is read to detennine if a
character has been received from a peripheral. If the Receiver
Data Register is full, the character is placed on the 8-bit ACIA
bus when a Read Data command is received from the MPU.
When parity has been selected for an 8-bit word (7 bits plus
parity), the receiver strip the parity bit (D 7 ="0") so that data
alone is transferred to the MPU. This feature redu.:es MPU
programming. The Status Register can continue to be read again
to determine when another character is available in the Receive
Data Register. The receiver is also double buffered so that a
character can be read from the data register as another character
is being received in the Shift register. The above sequence continues until all characters have been received.

•

• ACIA INTERNAL REGISTERS
The ACIA provides four registers; Transmit Data Register
(TDR), Receive Data Register(RDR), Control Register(CR) and
Status Register(SR). The content of each of the registers is
summarized in Table I.

Receive
Data is received from a peripheral by means of the Receive
Data input. A divide-by-one clock ratio is provided for an
externally synchronized clock (to its data) while the divide-by16 and 64 ratios are provided for internal synchronization. Bit
synchronization in the divide-by-16 and 64 modes is initiated by

~HITACHI

523

Table 1 Definition of ACIA Register Contents
Buffer
Address
Data Bus

•
••
•••
••••

****
RS=1· R/W=O

RS=1 • R/W=1

RS=O· R/W=O

RS=O· R/W=1

Transmit Data
Register

Receiver Data
Register

Control Register

Status Register

(Write Only)

(Read Only)

(Write Only)

(Read Only)

0

Data Bit 0*

Data Bit 0

Counter Divide
Select (CRCl)

Rx Data Reg. Full
(RDRF)

1

Data Bit 1

Data Bit 1

Counter Divide
Select (CR1)

Tx Data Reg. Empty
(TORE)

2

Data Bit 2

Data Bit 2

Data Carrier Detect
(DCD)

3

Data Bit 3

Data Bit 3

Word Select 1
(CR2)
Word Select 2
(CR3)

Clear to Send
(CTS)

4

Data Bit 4

Data Bit 4

Word Select 3
(CR4)

Framing Error
(FE)

5

Data Bit 5

Data Bit 5

Tx Control 1
(CR5)

Overrun
(OVRN)

6

Data Bit 6

Data Bit 6

Tx Control 2
(CA6)

Parity Error
(PE)

7

Data Bit 7***

Data Bit 7**

Rx Interrupt Enable
(CR7)

Interrupt Request
(IRQ)

Leiding bit· LSB = Bit 0
Dltl bit will be zero in 7·bit plus parity modes .
Dlta bit is "don't care" in 7·bit plus parity modes .
1 ... "High" level,O ... "Low" level

•

Transmit Data Register (TOR)
Data ill written in the Transmit Data Register during the
negative transition oCthe enable (E) when the ACIA has been
addressed and RS· R!W is selected. Writing data into the
register causes the Transmit Data Register Empty bit in the
Status Register to go "0". Data can then be transmitted. If the
transmitter is idling and no character is being transmitted, then
the transfer will take place within 2 bit time + several E cycles
of the trailing edge of the Write command. If a character is
being transmitted, the new data character will commence as
soon as the previous character is complete. The transfer of
data causes the Transmit Data Register Empty (TORE) bit to
indicate empty.
•

Receive Data Register (RDR)
Data is automatically transferred to the empty Receive Data
Register (RDR) from the receiver deserializer (a shift register)
upon receiving a complete character. This event causes the
Receive Data Register Full bit (RDRF) on the status buffer to
go "I" (full). Data may then be read through the bus by ad·
dressing the ACIA and R/W "High" when the ACIA is enabled.
The non-destructive read cycle causes the RDRF bit to be
cleared to empty although the data is retained in the RDR. The
status is maintained by RDRF as to whether or not the data
is current. When the Receive Data Register is full, the automatic
transfer of data from the Receiver Shift Register to the Data
Register is inhibited and the RDR contents remain valid with its
current status stored in the Status Register.
• Control Register
The ACIA Control Register consists of eight bits of writeonly buffer that are selected when RS and R/W are "Low". This

524

register controls the functit'n of the recei~ transmitter,
interrupt enables, and the Request-to-Send (RTS) peripheral/
modem control output.
Counter Divide Select Bits (CRO and CR1)
The Counter Divide Select Bits (CRO and CRI) determine
the divide ratios utilized in both the transmitter and receiver
section of the ACIA. Additionally, these bits are used to provide
a master reset for the ACIA which clears the Status Register
(except for external conditions on CTS and DCD) and initializes
both the receiver and transmitter. Master reset does not affect
other Control Register bits. Note that after power-on or a power
fail/restart, these bits must be set "I" to reset the ACIA. After
resetting, the clock divide ratio may be selected. These counter
select bits provide for the following clock divide ratios:
Table 2 Function of Counter Devide Select Bit
CR1

CRO

0

0

0

Function
+1
+16

0

+64
Master Reset

Word Select Bits (CR2, CR3, and CR4)
The Word Select bits are used to select word length, parity,
and the number of stop bits. The encoding format is as follows:

eHITACHI

---------------------------------------------------HD6350,HD63A50,HD63B50
Table 3 Function of Word Select Bit
CR4

CR3

CR2

0

0

0

7 Bits + Even Parity + 2 Stop Bits

0

0

1

0

0

7 Bits + Odd ParitY + 2 Stop Bits
7 Bits + Even Parity + 1 Stop Bit

0

1
1

1

7 Bits + Odd Parity + 1 Stop Bit

1

0

0

1
1
1

0
1

0

1

1

8 Bits + 2 Stop Bits
8 Bits + 1 Stop Bit
8 Bits + Even Parity + 1 Stop Bit
8 Bits + Odd Parity + 1 Stop Bit

1

Function

Word length, Parity Select, and Stop Bit changes are not
buffered and therefore become effective immediately.
Transmitter Control Bits (CR5 and CR6)
Two Transmitter Control bits provide for the control of
the interrupt from the Transmit Data Register Empty condition,
the Request-to-Send (RTS) output, and the transmission of a
Break level (space). The following encoding format is used:

Table 4 Function of Transmitter Control-Bit
CR6

CR5

o

o

RTS

1

RTS = "Low", Transmitting Interrupt Enabled.

o

RTS = "High", Transmitting Interrupt
Disabled.

o

Function

= "Low", Transmitting Interrupt Disabled.

RTS = "Low", Transmits a Break level on
the Transmit Data Output.
Transmitting Interrupt Disabled.
Receive Interrupt Enable Bit (CR7)
The following interrupts will be enabled by a "1" in bit
position 7 of the Control Register (CR7): Receive Data
Register Full, Overrun, or a "Low" to "High" transistion on the
Data Carrier Detect (DC D) signal line.
RORF Flag

R

.

ecelver

RIE

[--'""""~
['"'..

iRci

OVRN Fla.

OeD Flag

Transmitter

""""~
CTS Input

TORE Flag

Figure 14 IRQ Internal Circuit

• Status Register
Information on the status of the ACIA is available to the
MPU by reading the ACIA Status Register. This read-only
register is selected when RS is "Low" and R/W is "High".
Information stored in this register indicates the status of the
Transmit Data Register, the Receive Data Register and error
logic, and the peripheral/modem status inputs of the ACIA.
Receive Data Register Full (RDRF), Bit 0
RDRF indicates that received data has been transferred to
the Receive Data Register. RDRF is cleared after an MPU read
of the Receive Data Register or by a master reset. The cleared or
empty state indicates that the contents of the Receive Data
Register are not current. Data Carrier Detect (OCD) being
"High" also causes RDRF to indicate empty.
Transmit Data Register Empty (TORE), Bit 1
The Transmit Data Register Empty bit being set "1"
indicates that the Transmit Data Register contents have been
transferred and that new data may be entered. The "0" state
indicates that the register is full and that transmission of a new
character has not begun since the last write data command.
Data Carrier Detect (DCD), Bit 2
The OCD bit will be "1" when the DCD input from a modem
has gone "High" to indicate that a carrier is not present. This bit
going" I" causes an Interrupt Request to be generated when the
Receive Interrupt Enable is set. It remains "1" after the OCD
input is returned "Low" until cleared by first reading the Status
Register and then the Data Register or until a master reset
occurs. If the DCD input remains "High" after read status and
read data or master reset has occurred, the interrupt is cleared,
the DCD status bit remains" I" and will follow the DCD input.
Clear-to-Send (CTS), Bit 3
The CTS bit indicates th~ state of the CTS input from a
modem. A "Low" CTS input indicates that there is a CTS from
the modem. In the "High" state, the Transmit Data Register
Empty bit is inhibited and the CTS status bit will be "1".
Master reset does not affect the Clear-to-Send Status bit.
Framing Error (FE), Bit 4
FE flag indicates that the received character is improperly
framed by a start and a stop bit and is detected by the absence
of the 1st stop bit. This error indicates a synchronization error,
faulty transmission, or a break condition. The FE flag is set or
reset during the receive data transfer time. Therefore, this error
indicator is present throughout the time that the associated
character is available.
Receiver Overrun (OVRN), Bit 5
Overrun is an error flag that indicates that one or more
characters in the data stream were lost. That is, a character or a
number of characters were received but not read from the
Receive Data Register (RDR) prior to subsequent characters
being received. The overrun condition begins at the midpoint of
the last bit of the second character received in succession
without a read of the RDR having occurred. The overrun does
not occur in the Status Register until the valid character prior to
Overrun has been read. The RDRF bit remains set until the
Overrun is reset. Character synchronization is maintained during
the Overrun condition. The Overrun indication is reset after the
reading of data from the Receive Data Register or by a Master
Reset.

~HITACHI

525

HD6350,HD63A50,HD63B50-----------------------Parity Error (PE), Bit 6
The PE flag indicates that the number of "1"s (highs) in the
character does not agree with the preselected odd or even
parity. Odd parity is defined to be when the total number of
ones is odd. The parity error indication will be present as long as
the data character is in the RDR. If no parity is selected, then
both the transmitter parity generator output and the receiver
parity check results are inhibited.
Interrupt Request (lRO), Bit 7
The IRQ bit indicates the state of the IRQ output, Any
interrupt condition with its applicable enable will be indicated
in this status bit. Anytime the IRQ output is "low" the IRQ bit
will be "I" to indicate the interrupt or service request status.
IRQ is cleared by a read operation to the Receive Data Register
or a write operation to the Transmit Data Register. (Refer to
Figure 14.)

is present and the appropriate interrupt enable within the ACIA
is set.
Clock Inputs
Separate high impedance TTL compatible inputs are provided for clocking of transmitted and received data. Clock
frequencies of 1, 16 or 64 times the data rate may be selected.
Transmit Clock (Tx CLK)
The Tx ClK input is used for the clocking of transmitted
data. The transmitter initiates data on the negative transition of
the clock.
Receive Clock (Rx CLK)
The Rx ClK input is used for synchronization of received
data. (In the -:- 1 mode. the clock and data must be
synchronized externally.) The receiver samples the data on the
positive transition of the clock .

• SIGNAL FUNCTIONS
• Serial Input/Output Lines
•

Interface Signal for MPU

Bi-Directional Data Bus (0 0 -0 7 )
The bi-directional data bus (Do-D 7 ) allow for data transfer
between the ACIA and the MPU. The data bus output drivers
are three-state devices that remain in the high impedance (off)
state except when the MPU performs an ACIA read operation.

Receive Data (Rx Data)
The Rx Data line is a high impedance TTL compatible input
through which data is received in a serial format. Synchronization with a clock for detection of data is accomplished internally when clock rates of 16 or 64 times the bit rate are used. Data
rates are in the range of 0 to 500 kbps when external
synchronization is utilized.

Enable (E)
The Enable signal, E, is a high impedance TTL compatible
input that enables the bus input/output data buffers and clocks
data to and from the ACIA. This signal will normally be a
derivative of the HMCS6800 4>2 Clock. The ACIA accepts both
continuous pulse signal and strobe type signal as Enable input.

Transmit Data (Tx Data)
The Tx Data output line transfers serial data to a modem or
other peripheral. Data rates in the range of 0 to 500 kbps when
external synchronization is utilized.

Read/Write (RM)
The R/W line is a high impedance input that is TTL
compatible and is used to control the direction of data flow
through the ACIA's input/output data bus interface. When R/W
is "High" (MPU Read cycle), ACIA output drivers are turned on
and a selected register is read. When it is "low", the ACIA
output drivers are turned off and the MPU writes into a selected
register. Therefore, the R/W signal is used to select read-only or
write-only registers within the ACIA.
Chip Select (CS o , CS., CS 2 )
These three high impedance TTL compatible input lines are
used to address the ACIA. The ACIA is selected when CSo and
CS. are "High" and CS; is "low". Transfers of data to and
from the ACIA are then performed under the control of the
Enable signal, Read/Write, and Register Select.
Register Select (RS)
The RS line is a high impedance input that is TTL
compatible. A "High" level is used to select the Transmit!
Receive Data Registers and a "low" level the Control/Status
Registers. The R/W signal line is used in conjunction with
Register Select to select the read-only or write-only register in
each register pair.

Modem Control
The ACIA includes several functions that penn it limited
contr~ a p~eral or modem. The functions included are
CTS, RTS and OCD.
Clear-to-Send (eTS)
This high impedance TTL compatible input provides automatic control of the transmitting end of a communications link
via the modem CTS active "Low" output by inhibiting the
Transmit Data Register Empty (TDRE) status bit. (Refer to
Figure 15.)
Request-to-Send (RTS)
The RTS output enables the MPU to control a peripheral or
modem via the data bus. The RTS output corresponds to the
state of the Control Register bits CR5 and CR6. When CR6=O
or both CR5 and CR6=1, the RTS output is "Low" (the active
state). This output can also be used for Data Terminal Ready
(OTR). (Refer to Figure 15.)

Interrupt Request (lRO)
iR'Q is a TTL compatible, open-drain (no internal· pullup),
active "Low" output that is used to interrupt the MPU. The
IRQ output remains "Low" as long as the cause of the interrupt

526

$

HITACHI

H 06350, H063A50, H 063850
Tx Data

TORE flag
Control Register
Write
Status Register
Read
Tx Data Register
Write

Transmit operation is not disabled, even if CTS goes "High".

Figure 15 RTS and CTS Timing Chart (Example of 2 bytes transmission)

Data Carrier Detect (OCD)
DCD is the input signal corresponding to the "carrier
detect" signal which shows carrier detect of modem.
DeD signal is used to control the receiving operation. When
DCD input goes "High", ACIA stops all the receiving operation
and sets receiving part in reset status. It means that receive
shift register stops shifting, error detection circuit and synchronization circuit of receive clock are reset. When DCD is
in "High" level, the receiving part of ACIA is kept in initial

status and the operation in the receiving part is prohibited.
When DCD goes "Low", the receiving part is allowed to
receive data. In this case, the following process is needed to
reset DCD flag and restarts the receive operation. (Refer to
Figure 16.)
(1) Return DCD input from "High" to "Low".
(2) Read status register. (DCD flag = "1")
(3) Read receive data register (Uncertain data will be read.)

OCO input
OCO flag
IRO
(RIE= "1")

Status Register Read

Rx Data Register Read

All the receiving operation are prohibited and ACIA is stopped
in this period.

Figure 16 DCD Flag Timing Chart
•

Note for Use

Input Signal, which is not necessary for user's application,
should be used fIxed to "High" or "Low" level. This is

applicable to the following signal pins.
Rx Data, Rx CLK, Tx CLK, CTS, OCD

~HITACHI

527

HD6852, HD68A52
SSDA (Synchronous Serial
The HD6852 Synchronous Serial Data Adapter provides a
bi-directional serial interface for synchronous data infonnation
interchange. It contains interface logic for simultaneously
transmitting and receiving standard synchronous communications characters in bus organized systems such as the
HMCS6800 Microprocessor systems.
The bus interface of the HD6852 includes select, enable,
read/write, interrupt, and bus interface logic to allow data
transfer over an 8-bit bi-directional data bus. The parallel data
of the bus system is serially transmitted and received by the
synchronous data interface with synchronization, fill character
insertion/deletion, and. error checking. The functional confIguration of the SSDA is programmed via the data bus during
system initialization.
Programmable control registers provide control for variable
word length, transmit control, receive control, synchronization
control and interrupt co~trol. Status, timing and control lines
provide peripheral or modem control.
Ty-pical applications include data communications tenninals,
floppy·disk controllers, cassette or cartridge tape controllers and
numerical control systems.

Data Adapter)

HD6852P, HD68A52P

(DP-24)

• PIN ARRANGEMENT

• fEATURES
• Programmable Interrupts from Transmitter, Receiver,
and Error Detection Logic
• Character Synchronization on One or Two Sync Codes
• External Synchronization Available for Parallel-Serial
Operation
• Programmable Sync Code Register
• Up to 600kbps Transmitter
• Peripheral/Modem Control Functions
• Three Bytes of FIFO Buffering on Both Transmit and
Receive
• 6, 7, or 8 Bit Data Transmission
• Optional Even and Odd Parity
• Parity, Overrun, and Underflow Status

(Top View)

Compatible with MC6852 and MC68A52

•

E

"

RIVi

13
6

Tx Data

RS

11

8

TUF

22

23

O.

21

7

0C0
iRa

0)

D.

20

0)

19

0 ..

18

D,

17

0,

16

0,

15

FiEi

9

528

~HITACHI

2

Ax Data

3

All. eLK

5

SM/i5TR

-------------------------------------------------------HD6852,HD68A52
•

ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Value

Vee *
Yin *

-0.3 -- +7.0

V

-0.3 -- +7.0

Topr
T stg

- 20 -- + 75

V
°c

-55 -- +150

°c

Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature

Unit

* With respect to Vss (SYSTEM GND)
(NOTE)

•

Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded, it could affect reliability of LSI.

RECOMMENDED OPERATING CONDITIONS
Item

Symbol

min

typ

max

Unit

Supply Voltage

Vee *
V 1L *

4.75

5.0

5.25

V

-0.3

-

0.8

V

V 1H *

2.0

-

Vee
75

V

Input Voltage
Operating Temperature

25

- 20

Topr

°c

* With respect to Vss (SYSTEM GND)

•

ELECTRICAL CHARACTERISTICS

•

DC CHARACTERISTICS (Vee

= 5V ± 5%, Vss = OV, Ta = -20-+75°C, unless otherwise noted.)
min

typ*

Input "High" Voltage

All Input

VIH

2.0

-

-

V

Input "Low" Voltage

All Input

VIL

-0.3

-

0.8

V

0 0 -0 7

V OH

2.4

-

-

V

2.4

-

-

V

-

-

0.4

V

-2.5

-

2.5

J1.A

-10

-

10

J1.A

-

-

10

J1.A

-

300

525

-

-

12.5

-

-

7.5

Yin = OV, Ta = 25°C

-

f = 1 MHz

-

-

5.0

Item

Output "High" Voltage

Symbol

Tx Data

V OH

DTR, TUF
Output "Low" Voltage

All Output

VOL

Test Condition

= -205 J1.A,

IOH

PW EH , PWEL~ 25J1.s

= -100 t.tA,

IOH

PW EH , PWEL~25J1.s

= 1.6 mA,

IOL

PW EH , PWEL~25J1.s

max

Unit

TxCLK, RxCLK,
Input Leakage Current

Rx Data, E,
RES, RS, R/W

lin

Yin

=0 -

Yin

= 0.4 -- 2.4V,
= 5.25V

5.25V

I

CS, DCD, CTS
Three·State Input Current
(Off State)
Output Leakage Current
(Off State)

00- 0 7

ITS1

IRQ

I LOH

Power Dissipation

Vee

V OH

= 2.4V

Po

00- 07
RxData, RxCLK,
Input Capacitance

TxCLK, RES,
CS, RS, R/W, E,

Cin

Yin = OV,
Ta = 25°C,
f = 1 MHz

mW

pF

DCD,CTS
Output Capacitance
* Ta

TxData, DTR, TUF,
IRQ

Cout

10

pF

= 25°C, Vee = 5V

_HITACHI

529

HD6852,HD68A52------------------------------------------------------•

AC CHARACTERISTICS

(VcC=5V±5%, VSS=OV, Ta=-20-+75°C, unless otherwise noted.)

1. TIMING OF THE DATA TRANSFER
Item

Test
Condition

Symbol

HD6852

HD68A52

Clock "low" Pulse Width

PWCL

Fig. 1

min
700

Clock "High" Pulse Width

PWCH

Fig. 2

700

-

Clock Frequency

fc

-

600

1.0

typ

max

-

min
400

-

typ

max

-

400

-

-

Unit
ns
ns

-

-

0.666

/J.S
/J.s

Receive Data Setup Time

tROSU

Fig. 3,7

350

Receive Data Hold Time

tROH

Fig.3

350

Sync Match Delay Time

tSM

Fig.3

-

-

Clock-to-Data Delay for
Transmitter

tTOO

Fig. 4,6

-

-

1.0

-

-

0.666

Transmitter Underflow

tTUF

Fig.4

-

-

/J.s

Fig. 5

0.666

J,J.s

Fig. 5

-

0.666

tOTR

-

1.0

DTR Delay Time
I RQ Release Time

tlR

RES Pulse Width

tREs

CTS Setup Time

tCTS

Fig.6

200

DCD Setup Time

toco

Fig.7

500

Input Rise and Fall Times(Except E)

h, tf

0.8V to 2.0V

-

*

1.0/l or 10% of the pulse Width, whichever

IS

1.0

-

200

-

200

1.0

1,000

kHz

-

ns

-

ns

1.2

-

-

0.8

J,J.s

-

0.666

-

J,J.s

-

ns

1.0*

-

-

150
350

1.0*

ns
J,J.s

smaller.

2. BUS TIMING
1) READ
Symbol

Item
Enable Cycle Time

Test
Condition

Enable "low" Pulse Width
Setup Time, Address and R/W valid
to Enable positive transition

max

tAS

Fig. 8

HD68A52
min
max

Unit

-

0.666

-

J,J.s

0.45

25

0.28

25

J,J.s

0.43

-

0.28

-

J,J.s

140

-

140

-

ns

1.0

tcycE
PW EH
PW EL

Enable "High" Pulse Width

HD6852
min

Data Delay Time

tOOR

-

320

-

220

ns

Data Hold Time

tH

10

-

10

-

ns

Address Hold Time

tAH

10

80

10

80

ns

Rise and Fall Time for Enable input

tEr, tEf

-

25

-

25

ns

.-

2) WRITE
Symbol

Item

Test
Condition

HD6852
min

max

HD68A52
max

min

Unit

tcycE
PW EH

1.0

-

0.666

-

J,J.s

Enable Pulse Width, "High"

0.45

25

0.28

25

J,J.s

Enable Pulse Width, "low"

PW EL

0.43

0.28

-

J,J.s

25

ns

Enable Cycle Time

Data Setup Time

tosw

195

-

Data Hold Time

tH

10

-

10

Address Hold Time

tAH

10

-

10

Rise and Fall Time for Enable input

tEr, tEf

Setup Time, Address and R/W valid
to Enable positive transition

530

I

tAS

Fig.9

140

-

$

HITACHI

25

140
80

-

ns
ns
ns
ns

-------------------------------------------------------HD6852.HD68A52

TXClK~.OV

PWCL

or
Rx ClK

Tx ClK
or
Rx ClK

PWCH

Figure 2 Clock Pulse Width ("High" level)

Figure 1 Clock Pulse Width ("Low" level)

Rx ClK

Rx Data

n

= Number of

~=

bits in character

Don't care

Sync Match

--------------------------------'

O.4V
~

Rx elK
Period

Figure 3 Receive Data Setup and Hold Times and Sync Match Delay Time

Tx
Cl.K
Enable

Tx
Data

TUF _ _ _ _ _ _ _ _ _J
n

= Number

of bits
in character

* lAO Release Time applied to TxData FIFO write operation and
RxData FIFO read operation.

Figure 4 Transmit Data Output Delay and
Transmitter Underflow Delay Time

** I RO Release Time applied to write "1" operation to RxRS, TxRS,
CTUF, Clear CTS bits.

Figure 5 DTR and

fRO Release Time

Ax ClK

Ax Data
Tx Data
At least two Rx ClK pulse should be input after the last bit of the last data
before the next falling edge of DCD occurs.

Figure 7 DeD Setup Time

Figure 6 CTS Setup Time

~HITACHI

531

HD6852,HD68A52-------------------------------------------------------

Enable

Enable

RS.CS. R/W

__

-J.~~~~-+~'~

_____

RS. CS.R/W

Data Bus
Data Bus

Figure 9 Bus Write Timing Characteristics
(Write information into SSDA)

Figure 8 Bus Read Timing Characteristics
(Read information from SSDA)

Load A
(Do ~ 0 7 , OTR. Tx Data. TUF)

LoadB
(IRQ Only)

5.0V

RL = 2.4K
Test point

Test point
C

R

~I

5'OV

3k

100pF

C=13OpF for Do ~07
=3OpF for OTR. Tx Data, and TUF
A" diodes are lS2074 (8) or Equivalent.
R=llkSl for 0 0 -0 7
=24kSl for OTR. Tx Data, and TUF

Figure 10 Test Loads

•

DEVICE OPERATION

At the bus interface, the SSDA appears as two addressable
memory locations. Internally, there are seven registers: two
read-only and five write-only registers. The read-only registers
are Status and Receive Data; the write-only registers are Control
1, Control 2, Control 3, Sync Code and Transmit Data. The
serial interface consists of serial input and output lines with
independent clocks, and f~ur peripheral/modem control lines.
Data to be transmitted is transferred directly into the 3-byte
Transmit Data First-In First-Out (FIFO) Register from the data
bus. Availability of the input to the FIFO is indicated by a bit
in the Status Register; once data is entered, it moves through
the FIFO to the last empty location. Data at the output of the
FIFO is automatically transferred from the FIFO to the
Transmitter Shift Register as the shift register becomes available
to transmit the next character. If data is not available from the
FIFO (underflow condition), the Transmitter Shift Register is
automatically loaded with either a sync code or an all "1 "s
character. The transmit section may be programmed to append
even, odd, or no parity to the transmitted word. An external
control line (CTS) is provided to inhibit the transmitter without clearing the FIFO.
Serial data is accumulated in the receiver based on the
synchronization mode selected. In the external sync mode used
for parallel-serial operation, the receiver is synchronized by the

532

Data Carrier Detect (OCD) input and transfers successive bytes
of data to the input of the Receiver FIFO. The single-synccharacter mode .requires that a match occur between the Sync
Code Register and one incoming character before data transfer
to the FIFO begins. The two-sync-character mode requires that
two sync codes be received in sequence to establish synchronization. Subsequent to synchronization in any mode, data is
accumulated in the shift register, and parity is optionally
checked. An indication of parity error is carried through the
Receiver FIFO with each character to the last empty location.
Availability of a word at the FIFO output is indicated by a bit
in the Status Register, as is a parity error.
The SSDA and its internal registers are selected by the
address bus, Read/~rite (R/W) and Enable control lines. To
configure the SSDA, Control Registers are selected and the
appropriate bits set. The Status Register is addressable for
reading status.
Other I/O lines, in addition to Clear-to-Send (CTS) and Data
Carrier DeteE!.J.DCD), include Sync Match/Data Terminal
Ready (SM/DTR) and Transmitter Underflow (TUF). The
transmitter and receiver each have individual clock inputs
allowing simultaneous operation under separate clock control.
Signals to the microprocessor are the Data bus and Interrupt
Request (iRQ).

_HITACHI

---------------------------------------------------------HD6852,HD68A52
•

Initialization
During a power-on sequence, the SSDA is reset via the RES
input and internally . latched in a reset condition to prevent
erroneous output transmissions. The Sync Code Register,
Control Register 2, and Control Register 3 should be programmed prior to the programmed release of the Transmitter
and/or Receiver Reset bits; these bits in Control Register I
should be cleared after the RES line has gone "High".

In the external sync mode, TDRA is unaffected by CTS in
order to provide Transmit Data FIFO status for preloading and
operating the transmitter under the control of the CTS input.
When the Transmitter Reset bit (Tx Rs) is set, the Transmit
Data FIFO is cleared and the TDRA status bit is cleared. After
one E clock has occurred, the Transmit Data FIFO becomes
available for new data with TDRA inhibited.
•

•

Transmitter Operation
Data is transferred to the transmitter section in parallel fonn
by means of the data bus and Transmit Data FIFO. The
Transmit Data FIFO is a 3-byte register whose status is
indicated by the Transmitter Data Register Available status bit
(TDRA) and its associated interrupt enable bit. Data is
transferred through the FIFO on negative edges of Enable (E)
pulsts. Two data transfer modes are provided in the SSDA. The
I-byte transfer mode provides for writing data to the transmitter section (and reading from the receiver section)" one byte
at a time. The 2-byte transfer mode provides for writing two
data characters in succession.
Data will automatically transfer from the last register
location in the Transmit Data FIFO (when it contains data) to
the Transmitter Shift Register during the last half of the last bit
of the previous character. A character is transferred into the
Shift Register by the Transmitter Clock. Data is transmitted
LSB first, and odd or even parity can be optionally appended.
The unused bit positions in short word length characters from
the data bus are "don't cares". (Note: The data bus inputs may
be reversed for applications requiring the MSB to be transferred
taken, e.g., IBM format for floppy disks: however, care must be
taken to properly program the control registers - Table I will
have its bit positions reversed.)
When the Shift Register becomes empty, and data is not
available for transfer from the Transmit Data FIFO, an
"underflow" occurs, and a character is inserted into the
transmitter data stream to maintain character synchronization.
The character transmitted on underflow will be ~ither a "Mark"
(all" I "s) or the contents of the Sync Code Register, depending
upon the state of the Transmit Sync Code on Underflow control
bit. The underflow condition is indicated by a pulse (~ Tx CLK
"High" period) on the Underflow putput (when in Tx Sync on
underflow mode). The Underflow output occurs coincident
with the transfer of the last half of the last bit preceding the
underflow character. The Underflow status bit is set until
cleared by means of the Clear Underflow control bit. This
output may be used in floppy disk systems to synchronize write
operations and for appending CRCe.
Transmission is initiated by clearing the Transmitter Reset
bit in Control Register 1. When the Transmitter Reset bit is
cleared, the first full positive half-cycle of the Transmit Clock
will initiate the transmit cycle, with the transmission of data or
underflow characters beginning on the negative edge of the
Transmit Clock pulse which started the cycle. If the Transmit
Data FIFO was not loaded, an underflow character will
be transmitted.
The Clear-to-Send (CTS) input provides for automatic
control of the transmitter by means of external system
hardware; e.g., the modem CTS out~provides the control in a
data communications system. The CTS input resets and inhibits
the transmitter section when "High", but does not reset the
Transmit Data FIFO. The TDRA status bit is inhibited by CTS
being "High" in either the one-sync character or two-synccharacter mode of operation.

$

Receiver Operation
Data and a pre synchronized clock are provided to the SSDA
receiver section by means of the Receive Data (Rx Data) and
Receive Clock (Rx CLK) inputs. The data is a continuous
stream of binary data bits without means for identifying character boundaries within the stream. It is, therefore, necessary to
achieve character synchronization for the data at the beginning
of the data block. Once synchronization is achieved, it is
assumed to be retained for all successive characters within the
block.
Data communications systems utilize the detection of sync
codes during the initial portion of the preamble to establish
character synchronization. This requires the detection of a
single code or two successive sync codes. Floppy disk and
cartridge tape units require sixteen bits of defined preamble and
cassettes require eight bits of preamble to establish the reference
for the start of record. All three are functionally equivalent to
the detection of sync codes. Systems which do not utilize code
detection techniques require custom logic external to the SSDA
for character synchronization and use of the parallel-to-serial
(external sync) mode.
(Note: The Receiver Shift Register is set to ones when reset)
•

Synchronization
The SSDA provides three operating modes with respect to
character synchronization: one-sync-character mode, two-synccharacter mode, and external sync mode. The external sync
mode requires synchronization and control of the receiving
section through the Data Carrier Detect (OCD) input. This
external synchronization could consist of direct line control
from the transmitting end of the serial data link or from
external logic designed to detect the start of the message block.
The one-sync-character mode searches on a bit-by-bit basis until
a match is achieved between the data in the Shift Register and
the Sync Code Register. The match indicates character synchronization is complete and will be retained for the message block.
In the two-sync-character mode, the receiver searches for the
first sync code match on a bit-by-bit basis and then looks for a
second successive sync code character prior to establishing
character synchronization. If the second sync code character is
not received, the bit-by-bit search for the first sync code is
resumed.
Sync codes received prior to the completion of synchronization (one or two character) are not transferred to the
Receive Data FIFO. Redundant sync codes during the preamble
or sync codes which occure as "fill characters" can automatically be stripped from the data, when the Strip Sync control bit
is set, to minimize system loading. The character synchronization will be retained until cleared by means of the Clar Sync bit,
which also inhibits synchronization search when set.

•

Receiving Data
Once synchronization has been achieved, subsequent characters are automatically transferred into the Receive Data FIFO
and clocked through the FIFO to the last empty location by E
pulses (MPU System t/>2). The Receiver Data Available status bit

HITACHI

533

HD6852,HD68A52------------------------------------------------------(RDA) indicates when data is available to be read from the last
FIFO location (#3) when in the I-byte transfer mode. The
2-byte transfer mode causes the RDA status bit to indicate data
is available when the last two FIFO register locations are full.
Data being available in the Receive Data FIFO causes an
interrupt request if the Receiver Interrupt Enable (RIE) bit is
set. The MPU will then read the SSDA Status Register, which
will indicate that data is available for the MPU read from the
Receiver Data FIFO register. The IRQ and RDA status bits are
reset by a read from the FIFO. If more than one character has
been received and is resident in the Receive Data FIFO,
subsequent E clocks will cause the FIFO to update and the
RDA and IRQ status bits will again be set. The read data
operation for the 2-byte transfer mode requires an intervening E
clock between reads to allow the FIFO data to shift. Optional
parity is automatically checked as data is received, and the
parity status condition is maintained with each character until
the data is read from the Receive Data FIFO. Parity errors will
cause an interrupt request if the Error Interrupt Enable (EIE)
has been set. The parity bit is not transferred to the data bus
but must be checked in the Status Register. NOTE: In the
2-byte transfer mode, parity should be che~ked prior to reading
the second byte, since a FIFO read clears the error bit.
Other status bits which pertain to the receiver section are
Receiver Overrun and Data Carrier Detect (DCD). Tht: Overrun
status bit is automatically set when a transfer of a character to
the Receive Data FIFO occurs and the first register of the
Receive Data FIFO is full. Overrun causes an interrupt if Error
Interrupt Enable (EIE) has been set. The transfer of the
overrunning character into the FIFO causes the previous
character in the FIFO input register location to be lost. The
Overrun status bit is cleared by reading the Status Register
(when the overrun condition is present), followed by a Receive
Data FIFO Register read. Overrun cannot occur and be cleared
without providing an opportunity to detect its occurrence via
the Status Register.
A positive transition on the DCD input causes an interrupt if
the EIE control bit has been set. The interrupt caused by OCD
is cleared by reading the Status Register when the DCD status
bit is "I", followed by a Receive Data FIFO read. The DCD
status bit will subsequently follow the state of the DCD input
when it goes "Low".
• SSDA REGISTERS
Seven registers in the SSDA can be accessed by means of the
bus. The registers are defined as read-only or write-only
according to the direction of information flow. The Register
Select (RS) input selects two registers in each state, one being
read-only and the other write-only. The Read/Write (R/W) input
dermed which of the two selected registers will actually be
accessed. Four registers (two read-only and two write-only) can
be addressed via the bus at any particular time. These registers
and the required addressing are defined in Table 1.
•

Control Register 1 (C1)
Control Register I is an 8-bit wirte-only register that can be
directly addressed from the data bus. Control Register 1 is
addressed when RS ="Low" and R/W ="Low".

Receiver Reset (Rx Rs), C1 Bit 0
The Receiver Reset control bit provides both a reset and
inhibit function to the receiver section. When Rx Rs is set, it
clears the receiver control logiC, error logic, Rx Data FIFO

534

$

Control, Parity Error status bit, and DCD interrupt. The
Receiver Shift Register is set ones. The Rx Rs bit must be
cleared after the occurrence of a "Low" level on RES in order
to enable the receiver section of the SSDA.
Transmitter Reset (Tx Rs), C1 Bit 1
The Transmitter Reset control bit provides both a reset and
inhibit to the transmitter section. When Tx Rs is set, it clears
the transmitter control section, Transmitter Shift Register, Tx
Data FIFO Control (the Tx Data FIFO can be reloaded after
one E clock pulse), the Transmitter Underflow status bit, and
the CTS interrupt, and inhibits the TDRA status bit (in the
one-sync-character and two-sync-character modes). The Tx Rs
bit must be cleared after the occurrence of a "Low" level on
RES in order to enable the transmitter section of the SSDA. If
the Tx FIFO is not preloaded, it must be loaded immediately
after the Tx Rs release to prevent a transmitter underflow
condition.
Strip Synchronization Characters (Strip Sync), C1 Bit 2
If the Strip Sync bit is set, the SSDA will automatically strip
all received characters which match the contents of the Sync
Code Register. The characters used for synchronization (one or
two characters of sync) are always stripped from the received
data stream.
Clear Synchronization (Clear Sync), C1 Bit 3
The Clear Sync control bit provides the capability of
dropping receiver character synchroni:?ation and inhibiting
resynchronization. The Clear Sync bit is set to clear and inhibit
receiver synchronization in all modes and is reset to zero to
enable resynchronization.
Transmitter Interrupt Enable (TIE), C1 Bit 4
TIE enable both the Interrupt Request (IRQ) output and
Interrupt Request status bit to indicate a transmitter service
request. When TIE is set and the TDRA status bit is "1", the
IRQ output will go "Low" (the active state) and the IRQ status
bit will go "1".
Receiver Interrupt Enable (RIE), C1 Bit 5
RIE enable both the Interrupt Request output (IRQ) and the
Interrupt Request status bit to indicate a receiver service
request. When RIE is set and the RDA status bit is "1", the IRQ
output will go "Low" (the active state) and the IRQ status bit
will go "1".
Address Control 1 (AC1) and Address Control 2 (AC2), C1
Bits 6 and 7
ACI and AC2 select one of the write-only registers - Control
2, Control 3, Sync Code, or Tx Data FIFO - as shown in Table
I, when RS ="High" and R/W = "Low".
• Control Register 2 (C2)
Control Register 2 is an 8-bit write-only register which can be
programmed from the bus when the Address Control bits in
Co.!!.trol Register I (ACI and AC2) are reset, RS = "High" and
R/W ="Low".
Peripheral Control 1 (PC1) and Peripheral Control 2 (PC2),
C2 Bits 0 and 1
Two control bits, PCI and PC2, determine the operating
characteristics of the Sync Match/DTR output. PCI, when
"High", selects the Sync Match mode. PC2 provides the inhibit/

HITACHI

-----------------------------------------------------------HD6852,HD68A52
enable control for the SM/DRT output in the Sync Match mode.
A one-bit-wide pulse is generated at the output when PC2 is "0",
and a match occurs between the contents of the Sync Code
Register and the incoming data even if sync is inhibited (Clear
Sync bit = "1 "). The Sync Match pulse is referenced to the
negative edge of Rx CLK pulse causing the match.
The Data Terminal Ready (DTR) mode is selected when PCI
is "0". When PC2 = "1" the SM/DTR output ="Low" and vice
versa. The operation of PC2 and PCl is summarized in Table 4.
1-Byte/2-Byte Transfer (1-Byte/2-Byte), C2 Bit 2
When I-Byte/2-Byte is set, the TDRA and RDA status bits
will indicate the availability if their respective data FIFO
registers for a single byte data transfer. Alternately, if I-Byte/
2-Byte is reset, the TDRA and RDA status bits indicate when
two bytes of data can be moved without a second status read.
An intervening Enable pulse must occur between data transfers.
Word Length Selects (WS1, WS2, WS3), C2 Bits 3, 4, 5
Word length Select bits WS1, WS2, and WS3 select word
length of 7, 8, or 9 bits including parity as shown in Table 3.
Transmit Sync Code on Underflow (Tx Sync), C2 Bit 6
When Tx Sync is set, the transmitter will automatically send
a sync character when data is not available for transmission. If
Tx Sync is reset, the transmitter will transmit a Mark character
(including the parity bit position) on underflow. When the
underflow is detected, a pulse approximately a Tx CLK "High"
period wide will occur on the underflow output if the Tx Sync
bit is "1". Internal parity generation is inhibited during
underflow except for sync code fIll character transmission in 8
bit plus parity word lengths.
Error Interrupt Enable (EIE), C2 Bit 7
When EIE is set, the IRQ status bit will go "1" and the IRQ
output will go "Low" if:
1) A receiver overrun occurs. The interrupt is cleared by reading
the Status Register and reading the Rx Data FIFO.
2) DCD input has gone to a "High". The interrupt is cleared by
reading the Status Register and reading the Rx Data FIFO.
3) A parity error exists for the character in the last location
(#3) of the Rx Data FIFO. The interrupt is cleared by
reading the Rx Data FIFO. The interrupt is cleared by
reading the Rx Data FIFO.
4) The CTS input has gone to a "High". The interrupt is cleared
by writing a "1" in the Clear CTS bit, C3 bit 2, or by a Tx
Reset.
5) The transmitter has underflowed (in the Tx Sync on
Underflow mode). The interrupt is cleared by writing a "1"
into the Clear Underflow, C3 bit 3, or Tx Reset.
When EIE is a "0", the IRQ status bit and the IRQ output
are disabled for the above error conditions. A "Low" level on
the RES input resets EIE to "0".
• Control Register 3 (C3)
Control Register 3 is a 4-bit write-only register which can be
programmed from the bus when RS = "High" and R/W
«Low" and Address Control bit ACI ="1" and AC2 = "0".
External/Internal Sync Mode Control (Ell Sync), C3 Bit 0
When the E/I Sync Mode bit is "1", the SSDA is in the
external sync mode and the receiver synchronization logic is
disabled. Synchronization can be achieved by means of the DCD
input or by starting Rx CLK at the midpoint of data bit "0" of

a character with DCD "Low". Both the transmitter and receiver
sections operate as parallel - serial converters in the External
Sync mode. The Clear Sync bit in Control Register 1 acts as a
receiver sync inhibit when "High" to provide a bus controllable
inhibit. The Sync Code Register can serve as a transmitter fill
character register and a receiver match register in this mode. A
"Low" on the RES input resets the E/I Sync Mode bit placing
the SSDA In the internal sync mode.
One-Sync-Character/Two-Sync-Character Mode, Control (1
Sync/2 Sync), C3 Bit 1
When the 1 Sync/2 Sync bit is set, the SSDA will

synchronize on a single match between the received data and
the contents of the Sync Code Register. When the 1 Sync/2
Sync bit is reset, two successive sync characters must be
received prior to receiver synchronization. If the second sync
character is not detected, the bit by bit search resumes from the
fIrst bit in the second character. See the description of the Sync
Code Register for more details.
Clear CTS Status (Clear CTS), C3 Bit 2
When a "1" is written into the Clear CTS bit, the stored
status and interrupt are cleared. Subsequently, the CTS status
bit reflects the state of the CTS input. The Clear CTS control
bit does not affect the CTS· input nor its inhibit of the
transmitter secton. The Clear CTS command bit is self-clearing,
and writing a "0" into this bit is a nonfunctional operation.
Clear Transmit Underflow Status (CTUF), C3 Bit 3
When a "1" is written into the CTUF status bit, the CTUF
bit and its associated interrupt are reset. The CTUF command
bit is self-clearing and writing a "0" into this bit is a
nonfunctional operation.
• Sync Code Register
The Sync Code Register is an 8-bit register for storing the
programmable sync code required for received data character
synchronization in the one-sync-character and two-synccharacter modes. The Sync Code Register also provides for
stripping the sync/fill characters from the received data (a
programmable option) as well as automatic insertion of fill
characters in the transmitted data stream. The Sync Code
Register is not utilized for teceiver character synchronization in
the external sync mode; however, it provides storage of receiver
match and transmit fill characters.
The Sync Code Register can be loaded when AC2 and ACI
are a "1" and "0" respectively, and R/W = "Low" and RS =
"High".
The Sync Code Rr.gister may be changed after the detection
of a match with the received data (the fIrst sync code having
been detected) to synchronize with a double-word sync pattern.
(This sync code change must occur prior to the completion of
the second character.) The sync match (SM) output can be used
to interrupt the MPU system to indicate that the fIrst eight bits
have matched. The service routine would then change the sync
match register to the second half of the .pattern. Alternately, the
one-sync-character mode can be used for sync codes for 16 or
more bits by using software to check the second and subsequent
bytes after reading them from the FIFO.
The detection of the sync code can be programmed to appear
on the Sync Match/DTR output by writing a ."1" in PCl (C2 bit
0) and a "0" in PC2 (C2 bit 1). The Sync Match output will go
"High" for one bit time beginning at the character interface
between the sync code and the next character.

~HITACHI

535

HD6852,HD68A52--------------------------------------------------------• Parity for Sync Character
Transmitter
Transmitter does not generate parity for the sync character
except 9-bit mode.
9-bit (8-bit + parity) - 8-bit sync character + parity
8-bit (7-bit + parity) - 8-bit sync character (no parity)
7-bit (6-bit + parity) - 7-bit sync character (no parity)
Receiver
At Synchronization
,Receiver automatically strips the sync character(s) (two sync
characters if '2 sync' mode is selected) which is used to establish
synchronization. And parity is not checked for these sync
characters.
After Synchronization is Established
When 'strip sync' bit is selected, the sync characters (fill
characters) are stripped and parity is not checked for the
stripped sync (fill) characters. When 'strip sync' bit is not
selected (0), the sypc character is assumed to be nonnal data
and it is transferred into FIFO after parity checking. (When
non-parity format is selected, parity is not checked.)

Strip Sync
(C1 Bit 2)

Data Format
(C2 Bit 3-5)

Operation

1

x

No transfer of sync
code.
No par ity check of
sync code.

0

With Parity

.()

Without Parity

*Transfer data and
sync codes.
Parity check.
*Transfer data and
sync codes.
No parity check.

* Subsequent to synchronization
x ••••• don't care

It is necessary to pay attention to the selected sync character
in the following cases.
1) Data format is (6 + parity), (7 + parity),
2) Strip sync is not selected ("0").
3) After synchronization when sync code is used as a fill
character.
Transmitter sends sync character without parity, but receiver
checks the parity as if it is normal data. Therefore, the sync
character should be chosen to match the parity che~k selected
for the receiver in this special case.
•

Receive Data First-In Fint-Out Register
(Rx Data FIFO)
The Receive Data FIFO Register consists of three 8-bit
registers which are used for buffer storage of received data. Each
8-bit register has an internal status bit which monitors its full or
empty condition. Data is always transferred from a full register
to an adjacent empty register. The transfer from register to
register occurs on E pulses. Th~ RDA status bit will be "1"
when data is available in the last location of the Rx Data FIFO.
In an Overrun condition, the overrunning character will be
transferred into the full first stage of the FIFO register and will
cause the loss of that data character. Successive overruns
continue to overwite the fIrst register of the FIFO. This
destruction of data' is indicated by means of the Overrun status

536

bit. The Overrun bit will be set when the overrun occurs and
remains set until the Status Register is read, followed by a read
of the Rx Data FIFO.
Unused data bits for short word lengths (including the parity
bit) will appear as "O"s on the data bus when the Rx Data FIFO
is read.
•

Transmit Data First-In First-Out Register
(Tx Data FIFO)
The Transmit Data FIFO Register consists of three 8-bit
registers which are used for buffer storage of data to be
transmitted. Each 8-bit register has an internal status bit which
monitors its full or empty condition. Data is always transferred
from a full register to an adjacent empty register. The transfer is
clocked by E pulses.
The TDRA status bit will be "High" if the Tx Data FIFO is
available for data.
Unused data bits for short word lengths will be handled as
"don't cares". The parity bit is not transferred over the data
bus since the SSDA generates parity at transmission.
When an Underflow occurs, the Underflow character will be
either the contents of the Sync Code Register or an all "1 "s
character. The underflow will be stored in the Status Register
until cleared and will appear on the Underflow output as a pulse
approximately a Tx CLK "High" period wide.
• Status Register
The Status Register is an 8-bit read-only register which
provides the real-time status of the SSDA and the associated
serial data channel. Reading the Status Register is a non-destructive process. The method of clearing status bits depends upon
the function each bit represents and is discussed for each bit in
the register.
Receiver Data Available (RDA), S Bit 0
The Receiver Data Available status bit indicates when
receiver data can be read from the Rx Data FIFO. The receiver
data being present in the last register (#3) of the FIFO causes
RDA to be "I" for the I-byte transfer mode. The RDA bit
being "1" indicates that the last two registers (#2 and #3) are
full when in the 2-byte transfer mode. The second character can
be read without a second status rad (to determine that the
charac.ter is available). And E pulse must occur between reads of
the Rx Data FIFO to allow the FIFO to shift. Status must be
read on a word-by-word basis if receiver data error checking is
important. The RDA status bit is reset automatically when data
is not available.
Transmitter Data Register Available (TDRA). S Bit 1
The TDRA status bit indicates that data can be loaded into
the Tx Data FIFO Register. The fIrst register (#1) of the Tx
Data FIFO being empty will be indicated by a "1" in the TDRA
status bit in the I-byte transfer mode. The first two registers
(#1 and #2) must be empty for TDRA to be "1" when in the
2-byte transfer mode. The Tx Data FIFO can be loaded with
two bytes without an intervening status read; however, one E
pulse must occur between loads. TDRA is inhibited by the Tx
Reset or RES. When Tx Reset is set, the Tx Data FIFO is
cleared and then released on the next E clock pulse. The Tx
Data FIFO can then be loaded with up to three characters of
data, even though TDRA is inhibited. This feature allows
preloading data prior to the release of Tx Reset. A "High" level
on the CTS input inhibits the TDRA status bit in either sync
mode of operation (one-sync-character or two-sync-character).
CTS does not affect TDRA in the external sync mode. This

~HITACHI

-----------------------------------------------------------HD6852,HD68A52
enables the SSDA to operate under the control of the CTS input
with TDRA indicating the status of the Tx Data FIFO. The CTS
input does not clear the Tx Data FIFO in any operating mode.
Data Carrier Detect (DCD), S Bit 2
A positive transition on the DCD input is stored in the SSDA
until cleared by reading both Status and Rx Data FIFO. A "1"
written into Rx Rs also clears the stored DCD status. The DCD
status bit, when set, indicates that the DCD input has gone
"High", The reading of both Status and Receive Data FIFO
allows Bit 2 of subsequent Status reads to indicate the state of
the beD input until the next positive transition.
Clear-to-Send (CTS), S Bit 3
A positive transiton on the CTS input is stored in the SSDA
until cleared by writing a "I" into the Clear CTS control bit or
the Tx Rs bit. The CTS status bit, when set, indicates that the
CTS input has gone "High". The Clear CTS command (a "1"
into C3 Bit 2) allows Bit 3 of subsequent Status reads to
indicate the state of the CTS input until the next positive
transition.
Transmitter Underflow (TUF), S Bit 4
When data is not available for the transmitter, an underflow
occurs and is so indicated in the Status Register (in the Tx Sync
on underflow mode). The underflow status bit is cleared by
writing a "1" into the Clear Underflow (CTUF) control bit or

the Tx Rs bit. TUF indicates that a sync character will be
transmitted as the next character. A TUF is indicated on the
output only when the contents of the Sync Code Register is to
be transferred (transmit sync code on underflow ="1 ").
Receiver Overrun (Rx Ovrn), S Bit 5
Overrun indicates data has been received when the Rx Data
FIFO is full, resulting in data loss. The Rx Ovrn status bit is set
when Overrun occurs. The Rx Ovrn status bit is cleared by
reading Status followed by reading the Rx Data FIFO or by
setting the Rx Rs control bit.
Receiver Parity Error (PE), S Bit 6
The parity error status bit indicates that parity for the
character in the last register of the Rx Data FIFO did not agree
with selected parity. The parity error is cleared when the
character to which it pertains is read from the Rx Data FIFO or
when Rx Rs occurs. The DCD input does not clear the Parity
Error or Rx Data FIFO status bits.
Interrupt Request (IRQ), S Bit 7
The Interrupt Request status bit indicates when the IRQ
output is in the active state (IRQ output = "Low"). The IRQ
status bit is subject to the same interrupt enables (RIE, TIE, and
EIE) as the IRQ output. The IRQ status but simplifies status
inquiries for polling systems by providing single bit indication of
service requests.

Table 1 SSDA Programming Model
Control*
Address
Register Content
Register 1-_ln.:,..p_u_ts=-+-_C_o,n_t_ro_I-t-_ _ _ _--._ _ _--._ _ _..,--_ _ _-.-_ _ _ _,--_ _ _ _ _--._ _ _ _ _, -_ _ __
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
RS
R/W AC2 AC1
Status (S)

x

o

x

Interrupt
R~st

(IRQ)

Control 1
(C1)

o

o

Receive
Data FIFO

x

x

Address
Control 2
(AC2)

x

x

07

o

Control 2
(C2)

o

o

Control 3
(C3)

o

o

Transmit
Data FIFO

o
o

o

Receiver
Parity
Error
(PE)

Receiver Transmitter I
Overrun Underflow!
(Rx Ovrn)
(TUF)
I

Clear-toSend
(CTS)

Data Carrier
Detect
(DCD)

Transmitter
Data
Register
Available
(TDRA)

Receiver
Data
Available
(RDA)

Address
Control 1
(AC1)

Receiver Transmitter
I nterrupt Interrupt
Enable
Enable
(RIE)
(TIE)

Clear
Sync

Strip Sync
Characters
(Strip Sync)

Transmitter
Reset
(Tx Rs)

Receiver
Reset
(Rx Rs)

O2

0,

Error
Interrupt
Enable
(EIE)

Transmit
Sync Code
on
Underflow
(Tx Sync)

Word
Length
Select 3
(WS3)

Word
Length
Select 2
(WS2)

Word
Length
Select 1
(WS1)

1-Byte/2-Byte
Transfer
(1-Byte/2-Byte)

Peripheral
Control 2
(PC2)

Peripheral
Control 1
(PC1)

Not Used

Not Used

Not Used

Not Used

Clear
Transmitter
Underflow
Status
(CTUF)

Clear CTS
Status
(Clear CTS)

One-SyncCharacter/
Two-Sync
Character
Mode Control
(1 Sync/
2 Sync)

External/
Internal
Sync Mode
Control
(E/I Sync)

07

O2

0,

Do

07

O2

0,

* 0; "Low" level, 1; "High" level
** "FF" should not be used as Sync Code.
*** When the SSDA is used in applications requiring the MSB of data to be receive and transmitted first, the data bus inputs to the SSDA
may be reversed (Do to 0 7 , etc.). Caution must be used when this is done since the bit positions in this table will be reversed, and the
parity should not be selected.

eHITACHI

537

HD6852.HD68A52--------------------------------------------------------Table 2 Functions of SSDA Register
Bit
7

Register

Symbol
IRQ

~

PE

5

Rx Ovrn

4

TUF

Function
The iRQ flag is cleared when the source of the IRQ is cleared. The source is determined by
the enables in the Control Registers: TIE. RIE. EIE.
When parity error is detected in

Read Rx Data FIFO. or a "1" into

_~~~i~_~~~~

receive data.
r------------------When receive data FIFO overruns.
When under flow i. occurred in
the transmitter.
Wh;;rn-;ig.;lr~;s_:_-------

Status
Register
(SI

2

DCD

Conditions
for Set

f---------------

r----------------When DCD signal rises.

Conditions
for Reset

_! :~·..!~t~I~~~(~!..~~!.I ______ _
Read Status and then Rx Data FI FO
or a "1" into Rx Rs (C1 Bit 01

-------- ----- ----------

t-1ByteT;a-;:;sfe-;M;d~;';he;--­
the transmit data FIFO (#1 I
is empty.

-----------------2 Byte Transfer Mode; when the

TDRA

________ __ _

Read Status and then Rx Data FI FO.
or a "1" into Rx Rs (C1 Bit 01.
-A-;;:;-;;-i;;t~ CTUF(C3 Bit 3I-;rin't; --Tx Rs (C1 Bit 1 I.
-A-;;;;'i;;t;ci;a-;CTS-(C3Bit2l-0;---

Write into Tx Data FIFO.

transmit data FIFO (#1. #21 is
!~~t~/:

------------o

RDA

7

AC2

_____ ________ _

r--------------------

1 Byte Transfer Mode; when the
data is received in the receive
~a~~I~~!~~

________ _

Read Rx Data FI FO.

2 Byte Transfer Mode; when the
data is received in the receive
data FIFO (#2. #3).
Used to access other registers. as shown Table 1 .

... ~ .....~~~ .........................................................................................................................................................
5

Control
Register 1
(C11

RI E

When "1". enables interrupt on RDA (S Bit 01.

::: ~::: ::!(~:::::::: ::::::::: :::~~~~:~:~~.:.:~:~~:~~~~: ~~~~~~~~~ :~:~:i~~~:{~:~~~:~!~:::::::::::::::::::::::::::::::::::::::::::::::::::::.:::::::::::::::::::::

... ~ ..... ~I.~~~.~~!1.~ ........... '!!.~~.~.:·.~:·.'.~.I~~~~.~~~.~~~~~.~.~?~!~~~~.r.~x~.~~!.~~.i.~~!!?~: ..................................................................... .
2
Strip Sync
When "1". strips all sync codes from the received data stream.
- ------ ----_.. ---- ---_. ------- - ----_.. --_. --. --- -- -- -------- -- ---. -_. ---- --------. - ---. _. --_. -- --- ----- ----- - -- ---------- - - - - - -- ------- - - -- - . -- - -. - . ------- - --- . -_. _. -.......... ~~.~~................. '!'!.~~~.:·.~::..~~~~~~.~~~.!~.~!~i.t.s.~.~~.!~~.~~~.i~:.~~.~~~!~~: .................................................................... .
~

"

o
7

Rx Rs
EI E

... ~ ..........................
Control
Register 2
(C21

When "1". resets and inhibits the receiver section.
When "1". enables the PE, Rx Ovrn. TUF. CTS. and DCD interrupt flags (S· Bits 6 through 21 .
···i,.ihe;;·;·';;:iilio~~·sY~~·~;;d~·~o·~t~;;t;·to·be·t~~;;;f;;r·,:~~j;;~·~~de·rf·I~~:·~~d·~;.;~bl~~·th~·TU·F···········

Tx Sync

Status bit and output. When "0". an all mark character is transmitted on underflow.

5
4
3

WS3
WS2
WS1

Word Length Select

2

1-Byte/2-Byte

When "1". enables the TDRA and RDA bits to indicate when a 1·byte transfer can occur; when

o

PC1
CTUF

When "1". clears TUF (S Bit 41. and IRQ if enabled.

........... .

..................................
::?::~.~~~.~!?~.~.~~~.~.~~.~!!~.~~~~~~:~.~~~~.~.~. ~y.~~.~~~~~!~~.~~~.~~~.~~: ............................................. .
1
PC2
3

Control
Register 3
(C31

"':2""

··Cl~~~·rn········

SM/DTR Output Control

........................................................................

···~\ihe·~·;·';;:~·le-.;~;·rn·isBit·3y.·~;.;d·l"Rel·if·e;;~bi~d·

...., ... "l:Synci2:Sync'" ···Wh~~·;;i;;:~~I~~t~·th~·o;.;~:;y~~~h~;~~t~;·~~d~·;·~j,·~;;··;O·;:·~~i~~·t~·t·h~·t~~:~yh~~·h~~~~t~·r·~·~d~:···· ........... .
"'Cj"" ··Eii·Sync·········· ··"Wlie·n·;;i;;:sele~ts·tt;e·exte;:nai·sy;;~·mode;·vl;lien·;·O;··.·se·le·cts·th~·fnt;;,:n~i·s~;nc·mode:············ ................. .

Table 3 Word Length
Bit 5
WS3

Bit 4
WS2

Bit 3
WSl

0
0
0
0
1
1
1

0
0
1
1
0
0
1
1

0

1

538

1

0
1
0
1
0
1

Word Length
6 Bits + Even Parity
6 Bits + Odd Parity
7 Bits
8 Bits
7 Bits + Even Parity
7 Bits + Odd Parity
8 Bits + Even Parity
8 Bits + Odd Parity

_HITACHI

-----------------------------------------------------------HD6852,HD68A52
•
Table 4 SM/DTR Output Control
Bit 1
PC2

Bit 0
PCl

SM/DTR Output at Pin 5

0
0

0
1

"High" Level*

1
1

0
1

"Low" Level*
SM Inhibited, "Low"*

Pulse~l-Bit

Wide, on SM

Register Select (RS)

The Register Select line is a high impedance input that is
TTL compatible. A "High" level is used to select Control
Registers C2 and C3, the Sync Code Register, and the
Transmit/Receive Data Registers. A "Low" level selects the
Control 1 and Status Registers (see Table 1).
•

Interrupt Request (IRQ)

IRQ is a TTL compatible, open-drain (no internal pullup),
active "Low" output that is used to interrupt the MPU. The
IRQ remains "Low" until cleared by the MPU.

* OUTPUT level is fixed by the data written into PC2, PC1.
** When "10" or "11 ", output is fixed at "Low".

•

Reset (RES)

The SSDA interfaces to the HD6800 MPU with an 8-bit
bi-directional data bus, a chip select line, a register select line, an
interrupt request line, read/write line, an enable line, and a reset
line. These signals, in conjunction with the HD6800 VMA
output, permit the MPU to have complete control ever the
SSDA.

The RES input provides a means of resetting the SSDA from
an external source. In the "Low" state, the RES input causes
the following:
1) Receiver Reset (Rx Rs) and Transmitter Reset (Tx Rs) bits
are set causing both the receiver and transmitter sections to
be held in a reset condition.
2) Peripheral Control bits PC 1 and PC2 are reset to zero,
causing the SM/DTR output to be "High".
3) The Ertor Interrupt Enable (EIE) bit is reset.
4) An internal synchronization mode is selected.
5) The Transmitter Data Register Available (TDRA) status bit is
cleared and inhibited.
When RES returns "High" (the inactive state), the transmitter and receiver sections will remain in the reset state until the
Receiver Reset and Transmitter Reset bits are cleared via the
bus under software control. The control Register bits affected
by RES (Rx Rs, Tx Rs, PC I, PC2, EIE, and E/I Sync) cannot be
changed when RES is "Low".

•

• CLOCK INPUTS

RDA·PE
Rx Dvrn

CTS
DCD
TUF

TDRA

RDA

•

INTERFACE SIGNALS FOR MPU

Bi-Directional Data Bus (0 0 -0 7 )

The bi-directional data bus (Do -D 7 ) allow for data transfer
between the SSD4. and the MPU. The data bus output drivers
are three-state devices that remain in the high impedance (off)
state except when the MPU performs an SSDA read operation.
•

Enable (E)

The Enable signal, E, is a high impedance TTL compatible
input that enables the bus input/output data buffers, clocks
data to and from the SSDA, and moves data through the FIFO
Registers. This signal is normally the continuous HMCS6800
System 1>2 clock, so that incoming data characters are shifted
through the FIFO.
•

Read/Write (RtW)

The Read/Write line is a high impedance input that is TTL
compatible and is used to control the direction of data flow
through the SSDA's input/output data bus interface. When
Read/Write is "High" (MPU read cycle), SSDA output drivers
are turned on if the chip is selected and a selected register is
read. When it is "Low", the SSDA output drivers are turned off
and the MPU writes into a selected register. The Read/Write
signal is also used to select read-only or write-only registeres
within the SSDA.

Separate high impedance TTL compatible inputs are provided for clocking of transmitted and received data.
•

Transmit Clock (Tx CLK)

The Transmit Clock input is used for the clocking of
transmitted data. The transmitter shifts data on the negative
transition of the clock.
•

Receive Clock (Rx CLK)

The Receive Clock input is used for clocking in received data.
The clock and data must be synchronized externally. The
receiver samples the data on the positive transition of the clock.
• SERIAL INPUT/OUTPUT LINES
• Receive Data (Rx Data)

The Receive Data line is a high impedance TTL compatible
input through which data is received in a serial format. Data
rates are from 0 to 600 kbps.
•

Transmit Data (Tx Data)

The Transmit Data output line transfers serial data to a
modem or other peripheral. Data rates are from 0 to 600 kbps.
• PERIPHERAL/MODEM CONTROL

•

Chip Select (CS)

This high impedance TTL compatible input line is used to
address the SSDA. The SSDA is selected when CS is "Low".
VMA should be used in generating the CS input to insure that
false selects will not occur_ Transfers of data to and from the
SSDA are then performed under the control of the Enable
signal, Read/Write, and Register Select.

$

The SSDA includes several functions that permit limited
control of a peripheral or modem. The functions included are
ITS, SM/DTR, DCD, and TUF.
•

Clear-to-Send (eTS)

The CTS input provides a real-time inhibit to the transmitter

HITACHI

539

HD685.2,HD68A52----------------------------section (the Tx Data FIFO is not disturbed). A positive CTS
transition resets the Tx Shift Register and inhibits the TDRA
status' bit and its associated interrupt in both the one-synccharacter and two-sync.:character modes of operation. TDRA is
not affected by the
input in the external sync mode.
The positive transition of CTS is stored within the SSDA to
insure that its occurrence will be acknowledged by the system.
The stored CTS information and its associated IRQ (if enabled)
are cleared by writing a "1" in the Clear CTS bit. The CTS
status bit subsequently follows the CTS input when it goes
"Low".
The CTS input provides character timing for transmitter data
when in the external sync mode. Transmission is initiated on the
negative transition of the frrst full positive clock pulse of the
transmitter clock (Tx CLK) after the release of CTS (see Figure
6).

crs

•

Data Carrier Detect (OCD)

The DCD input provides a real-time inhibit to the receiver
section (the Rx FIFO is not disturbed). A positive DCD
transition resets and inhibits the receiver section except for the
Receive FIFO and the RDRA status bit and its associated IRQ.
The positive transition of DCD is stored within the SSDA to
insure that its occurrence will be acknowledged by the system.
The stored r:>cD information and its associated IRQ (if enabled)
are cleared by reading the Status Register and then the Receiver
FIFO, or by writing a "1" into the Receiver Reset bit. The DCD
status bit subsequently follows the DCD input when it goes
"Low". The r>cD input provides character synchronization
timing for the receiver during the external sync mode of
operation. The receiver will be initialized and data will be
sampled on the positive transition of the first full Receive Clock

cycle after release of OCD (see Figure 7).
•

Sync Mach/Data Terminal Ready (SM/DTR)

The SM/DTR output provides four functions (see Table 4)
depending on the state of the Pel and Pe2 control bits. When
the Sync Match mode is selected (PC 1 = "1", Pe2 = "0"), the
output provides a one-bit-wide pulse when a sync code is
detected. 'This pulse occurs for each sync code match even if the
receiver has already attained synchronization. The SM output is
inhibited when Pe2 = "1". The DTR mode (Pel = ''0'')
provides an output level corresponding to the complement of
Pe2 (D'fR = "0" when Pe2 = "1" ,) (see Table 4.)
•

Transmitter Underflow (TUF)

The Underflow output indicates the occurrence of a transfer
of a "fill character" to the Transmitter Shift Register when the
last location (#3) in the Transmit Data FIFO is empty. The
Underflow output pulse is approximately a Tx CLK "High"
period wide and occurs during the last half of the last bit of the
character preceding the "Underflow" (see Figure 4). The
Underflow output pulse does not occur when the Tx Sync bit is
in the reset state.
• NOTE FOR USAGE

If the hold time of ES signal and R/W signal is within 50230 ns, there is a case that Transmit Data FIFO is not cleared
and TDRA flag is not set when software reset using TxRS
(TxRS=l) is executed. Usual program for data transmission will
start to send the data as shown in Fig. 11 and Fig. 12.
In this case, the data of the first three bytes are not preset
and unexpected data which is remaining in Transmit Data FIFO
are sent in the first two bytes.

When address hold time is
within 50-230 ns, sometimes
TDRA flag is not set.

Figure 12 Transmission Start Sequence

Figure 11 Normal Flow of Starting
the Transmission and Reception

In case of SSDA, Address Hold Time should be from 20 to
50 ns or over 230 ns.

540

$

•

OeD Input in External Synchronization Mode

In case of receiving data in External Synchronization Mode,
Receive data is put off by one bit at times, when DCD is drived
like..fl..in RxCLK cycle in which RDA flag is set.

HITACHI

---------------------------------------------------------HD6852,HD68A52

RxCLK

RxData

O2

07

RDA fla;:.g_ _ _--I

0,

D.

D.

0

7

.~--~---+----------------------------------~~---------

t

Read operation of Receive
Data FIFO after read
operation of Status Register
DCD input

Read operation of Receive Data FIFO after
read operation of Status Register
(Data $FO)

Read data is put off by one bit
(Unusual Case)
RxCLK

RxData

Os

0

0,

O2

7

D.

D.

07

+--J,...,._______________________

....J ....._ __

RDA flag..;...._ _ _ _ _ _

!

Read operation of Receive Data FIFO after
read operation of Status Register

Read operation of Receive Data FIFO after read
operation of Status Register (Data $78)

DCD input

------------+--~
Figure 13 Exceptional External Sync Operation

To avoid this case, use SSDA in the following method.
(1) DCD Land RxCLK L should meet the relation shown
in Fig. 14.

RxCLK

,,

,,

:,' :,'

X

RxData _ _ _ _ _ _....
:_!-;""'; __..J

,,
,

''

'

,

! 12

I

Do

~
!t

J

t2

~

t,

>0

X,-_ _ _0.;..'__

500 nsec

Figure 14 DeD Input Timing in External Sync Mode

(2) RxData should be input regarding the second RxCLK rise
as Do bit, after DCD~.

~HITACHI

541

HD4650S, HD4650S-1,
HD4650SA, HD4650SA-1
ADU (Analog Data Acquisition Unit)
The HD46508 is a monolithic NMOS device with a 10-bit
analog-to-digital converter, a programmable voltage comparator,
a 16-channel analog multiplexer and HMCS6800 microprocessor
family compatible interface.
Each of 16 analog inputs is either converted to a digital data
by the analog-to-digital converter or compared with the specified value by the programmable comparator. The analog-todigital converter uses successive approximation method as the
conversion technique. It's intrinsic resolution is 10 bits but it
can be 8 bits if the programmer so desires. The programmable
voltage comparator compares the input voltage with the value
specified by the programmer. The result (greater than, or
smaller than) is reflected to the flag in the status register.
The device can expand its capability by controlling the
external circuits such as sample holder, pre-amplifier and
external multiplexer.
With these features, this device is ideally suited to applications such as process control, machine control and vehicle
control.
•
•
•

HD46508P, HD46508P-l, HD46508PA, HD46508PA-l

•

PIN ARRANGEMENT

o

AI,
Do

FEATURES
16-channel Analog multiplexer
Programmable AID Converter resolution (1 O-bit or 8-bit)

Single +5V Power Supply
Compatible with HMCS6800 Bus (The connection with
other Asynchronous Buses possible)

•

BLOCK DIAGRAM

AI,

0,

AI,

0,

AI,

0,

AI.
AI,
AI,

• Programmable Voltage comparison (PC)
• Conversion Time 100J,Ls (AID), 13J,Ls(PC)
• External Sample and Hold Circuit Control
• Auto Range-switching Control of External Amplifier
• Waiting Function for the Settling Time of External
Amplifier
• Interrupt Control (Only for AID conversion)
•
•

Alo
AI,

, AI.

HD46508

0,

AltO

AI'I
2

AI"

2

AI"

AI'4
Ails

REF(+}

2

COMMON
COMPIN

....r-'

'--1_ _ _ _ _ _ _

REF\-}

(Top View)

Comparator
r-"Inpul
-+--------~~
:
(COMPINI
L ___ Common

5V (Veel

GND IVssl

+-------,

__

ClK 11 MHzl

Output

(COMMON I
AI,
AI,

Do - D7

ANllog

Inputs

~S,

I

~---------+-- RS.
~,

AIlS

RS,
R/iN

Ext"nel
Control

~----------4~.

rna

S;gnol
IGAINSELI
5V

Analog GND

(NOTE]

PC Data

(REF(+}) (REF(-)I

542

~HITACHI

Data for programmable
voltage comparison

• ORDERING INFORMATION
ADU

Bus Timing

HD46508A

1 MHz

HD46508A·l

1.5 MHz

HD46508

1 MHz

HD46508·1

1.5 MHz

Non Linearity·

• Specification for 10 bit AID conversion

±1 lSB
±3lSB

0 0 -0 ,
E
CS"

IRQ
R!WCONTROL
C.START
SYNCHRONOUS
CIRCUIT

®
CLK

L--

CS,
RS o

RS,

CD
(Reg. 0)

R/W

~
::t

BASIC
TIMING
GENERATOR

-

::t

D/A
(1024 LADDER
RESISTANCE &
DECODER)

REGISTER

~

()

RES
SUCCESSIVE
APPROXIMATION

EXPAND
CONTROL

@
ST
(Reg. 0)

Alo

AI,
PC.GS.GO.G1@·@
(Reg.0.1)

:r:
c
~

(j)

CJ1

ANALOG
MPX

MODE SELECT
& GAINSEL
CONTROL

o
:r:
o

StJ
~

(j)

01

o

cp

......

AI,s

COMPARATOR

GAINSEL

REF(+) REFH

COMPIN

COMMON

:r:
o

®

~
(j)

DO-D3 (Reg. 1)
MI

o
ex>
J>
:r:
c

"206": Fixed Data for Auto Range·Switching x 4
"410": Fixed Data for Auto Range-Switching x 2

01

~

(j)

Figure 1 Internal Block Diagram
U1

-'="
CN

CJ1

o

ex>

~

H04650B,H 04650B-1 ,H04650BA,H04650BA-1---_ _ _ _ _ _ _ _ _ _ _ _ _ _ __
•

ABSOLUTE MAXIMUM RATINGS
Item

Value

Vee *
Vin *

-0.3 - +7.0

V

-0.3- +7.0

V

Input Voltage
Analog Input Voltage

VAin *

-0.3 - +7.0

V

Operating Temperature

TOJlr
T stg

- 20- + 75

°c
°c

Storage Temperature
•
[NOTE)

•

- 55- +150

With respect to Vss (SYSTEM GNO)
Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions.
If these conditions are exceeded. it could affect reliability of LSI.

RECOMMENDED OPERATING CONDITIONS
Item

Symbol

min

typ

max

Unit

4.75

5.0

5.25

V

Input "High" Voltage

Vee *
V 1H *

2.0

-

Input "Low" Voltage

V 1L *

-0.3

-

Vee
0.8

V

Analog Input Voltage

VAin *

V

Supply Voltage

Reference Voltage

0

-

V REF (+)

-

Vee

Vee+0.25

V REF (-) *

-0.1

0

-

Vee
-2-

Operating Temperature

- 20

Topr

*With respect to Vss (SYSTEM GND)
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS<1> (Vee 5V

=

Test Condition

max

Unit
V

-0.3

Vee
0.8

2.4

-

-

-

-

Input "low" Voltage

V 1L
Do -0 7

0 0 -0,. GAINSEL

IRQ

°c

75

-

2.0

Output "low" Voltage

V

typ

min

V 1H

GAINSEL

V~e+0.25

25

Input "High" Voltage

Output "High" Voltage

V

-

± 5%, Vss = OV, Ta = -20-+75°C, unless otherwise noted.)
Symbol

Item

V

~.REF(+) *

V REF (+) + V REF (-) *
2

Voltage Center of Ladder

•
•

Unit

Symbol

Supply Voltage

10H = -2051lA
V OH

10 H = -2001lA
10L = 1.6 mA

VOL

2.4

-

-

0.4

-

0.4

Vee- 1.O

10H = -101lA
10L = 3.2 mA

V
V

V

E, ClK, R/W

Input Leakage Current
Three-State (off state)
Input Current
Output Leakage
Current

--

RES, RSo, RS 1
CSo, CS 1

lin

Vin = 0- 5.25V

-2.5

-

2.5

IlA

Do -0 7

I TS1

Vin = 0.4 - 2.4V

-10

-

10

IlA

IRQ

I LOH

V OH = 2.4V

-

10

IlA

-

-

12.5

mW
pF

-

-

10.0

pF

-

-

10.0

pF

Power Dissipation

-

Po
Do -0 7

Input Capacitance

E,CLK,R/W

--

RES, RSo, RS 1

V in = OV, Ta
f = 1 MHz

Cin

500

= 25°C

CSo, CS 1
Output Capacitance

544

IRQ, GAINSEl

V in = OV, Ta = 25°C
f= 1 MHz

Cout

$

HITACHI

- - - - - - - - - - - - - - - - - - - - H 046508, H 046508-1, H 046508A, H 046508A-1
•

DC CHARACTERISTICS <2> (Vee

= 5V ± 5%, Vss = OV, Ta = -20-+75°C, unless otherwise noted.)

Item

= 5.0V,
= 4.75V, Ta = 25°C
VAin = 5.0V
Vee = 4.75V, Ta = 25°C
COMMON = OV
VAin = OV, Ta = 25°C
Vee = 4.75V, COMMON =
VAin
Vee

Analog Multiplexer ON Resistance

OFF Channel Leakage Current

Ladder Resistance

V REF

VREF (-)

• CONVERTER SECTION (Ta = 25°C, Vee
1. 10-BIT AID CONVERSION

= V REF (+)

(+)

= 5.0V
= OV, Ta =

= 5.0V, tcycC

25°C

kQ

100

nA

-10

-

nA

-

-

7.5

pF

10

-

40

kQ

-

-

10

HD4650S, HD4650S-1
typ

min

typ
10

-

±1/2

±1

Zero·Error

-

Full-Scali Error

-

±1/2
±1/4

±3/4
±1/2

-

Quantization Error

-

-

±1/2

-

-

±1

±3/2

-

±2

Resolution
Non-linearity Error

Absolute Accuracy

*

*

Unit

=lJ..Ls, unless otherwise noted.)

H D4650SA, H D4650SA-1

Item

max
1

-

-100

5V

Analog Multiplexer Input Capacitance
(from REF(+) to REF(-))

typ

min

Test Condition

min

max

I

max

-

10

Unit
bits

±1

±3

LSB

±1/2

±1

LSB

±1/2

±1

LSB

±1/2

LSB

±4

LSB

2. 8-BIT AID CONVERSION
HD4650S, HD46508-1

HD4650SA, HD4650SA-'

Item

min

typ

max

min

typ

max

Unit

-

8

-

-

8

-

bits

-

±l/S

±1/4

±1/4

±3/4

LSB

±1/4

±3/8

±3/8

±1/2

LSB

Full-Scali Error

-

±1/4

±3/8

-

±3/8

±1/2

LSB

Quantization Error

-

-

±1/2

-

-

±1/2

LSB

±5/S

±3/4

-

±3/4

±5/4

LSB

max

min

Resolution
Non-linearity Error

*

Zero-Error

Absolute Accuracy

*

-

3. PROGRAMMABLE VOLTAGE COMPARISON (PC)

Resolution
Non·linearity Error

*

Zero-Error
Full-Scali Error
Absolute Accuracy

H D4650S, H D46508-1

HD4650SA, HD4650SA-'

Item

*

typ

-

-

8

-

±l/S

±1/4

-

±1/4

±3/4

LSB

-

±1/4

±3/8

±3/8

±1/2

LSB

-

±1/4

±3/8

±3/8

±1/2

LSB

±3/8

±5/8

-

±1/2

±1

LSB

8

-

typ

Unit

min

max

bits

*Temperature Coefficient; 25 ppm of FSRf C (max)

~HITACHI

545

H 046508,H 046508-1 ,H 046508A, H 0 4 6 5 0 8 A - 1 - - - - - - - - - - - - - - - - - - • AC CHARACTERISTICS (Vee= 5.0V ± 5%, Vss = OV, Ta = -20-+75°C, unless otherwise noted,)
1. CLOCK WAVEFORM
Item

Test
Conditions

Symbol

CLK Cycle Time
ClK "High" Pulse Width
ClK "low" Pulse Width
Rise and Fall Time of
ClK
* CD: ClK Divider bit

tCYcC
PW CH
PW CL

Fig. 2

min

CD* = 0
typ

1.0
0.45
0.40

-

tCr, tCf

CD*

=1

max

min

typ

0.5
0.22

-

-

10
4.5
4.0

0.21

-

25

-

-

Unit

max
5

-

2.2
2.1

IlS
IlS
IlS

-

25

ns

2.0V

O.BV

ClK

~-----PWCH------~~tCf~------PWCL--------~

~----------------tcycC----------------~

Figure 2 ClK Waveform

2. IRQ, GAINSEL OUTPUT
Item
IRQ Release Time
GAINSEl Delay Time

Symbol
tlR
tGSD1
tGSD2

Test condition
Fig. 3
Fig.4

tGSD1: TTL load
tGSD2: CMOS load

_ E/

Figure 3 fRLi Release Time

546

~HITACHI

min

typ

-

-

max
750
750

-

-

750

-

-

Unit
ns
ns

ns

- - - - - - - - - - - - - - - - - - - H D46508,HD46508-1 ,HD46508A,HD46508A-1
(') Sample & Hold

ClK

"

.. ----- - -- -------

GAINSEL
*CMOS Load

(2) x2, x4 Auto Range-Switching, Programmable Gain

ClK

O.8V

-- - -- --*CMOS Load

Figure 4 GAINSEL Delay Time

3. BUS TIMING CHARACTERISTICS
READ OPERATION SEQUENCE

Item
Enable Cycle Time

Symbol

HD46508
HD46508A

Test
Condition

Unit

max

min

typ

-

-

0.666

-

-

-

0.28

-

-

ps

-

0.28

-

ps

-

-

25

-

-

25

ns

140

-

-

140

-

-

ns

320

-

220

ns

460

-

-

10

-

10

-

1.0

Enable "High" Pulse Width

tcycE
PWEH

0.45

Enable "Low" Pulse Width

PWEl

0.40

Rise and Fall Time of Enable

tEr,tEf

Address Set Up Time

tAS

Data Delay Time

tDDR

Data Access Time

tACC

-

Data Hold Time

tH

10

Address Hold Time

tAH

10

$

I

typ

min

Fig. 5

HD46508·'
HD46508A-1

HITACHI

max

ps

360

ns

-

ns
ns

547

HD4650S,HD4650S-1 ,HD4650SA,HD4650SA-1-----------------_
WRITE OPERATION SEQUENCE

Item
Enable Cycle Time
Enable "High" Pulse Width
Enable "Low" Pulse Width
Rise and Fall Time of Enable
Address Set Up Time
Data Set Up Time
Data Hold Time
Addms Hold Time

Symbol

HD4650S
HD4650SA
typ max
min
1.0
0.45
0.40
-

Test
Condition

tcycE
PWEH
PW EL
tEr, tEf
t AS

Fig. 6

tosw
tH
tAH

-

-

25

140
195
10
10

-

-

-

-

-

HD4650S·'
HD4650SA·'
typ max
min
0.666
0.2S0
0.2S0
25
140
SO
10
10

-

-

Unit
J1.s
J1.S

p.s
ns
ns
ns
ns
ns

~--------tcycE--------------,~

2.0V

o.sv

E
~----PWEL---~

R/W,CS o

Figure 5 Read Timing

548

$

HITACHI

- - - - - - - - - - - - - - - - - - - H 046508, H 046508-1 ,H 046508A, H046508A-1
~--------------------tcycE----------------------~

2.0V

2.0V

O.8V
~--------PWEL-----~

CS,. R/W-----,.
RS o • RS,

CS"

0,,-0,

Figure 6 Write Timing
5.0V

5.0V

R

....

Test Point 0----<___.----+__--..

Test Point o----.>---..-----~--

r

R

LOAD B (IRQ)

LOAD A (Do -D,. GAINSEL)

:L : 21·~:~
C

=

130pF

RL

=

R

= 3kS1

C

= 100pF

1

1Diode = 1S2074®

2.4kn

Diode = lS2074®
or Equivalent

or Equivalent

T'"'"'"'l

I~F

LOAD C (GAINSEL)

Figure 7 Test Load

$

HITACHI

549

H046508,H 046508-1,H 0 4 6 5 0 8 A , H 0 4 6 5 0 8 A - 1 - - - - - - - - - - - - - - - - - • SIGNAL DESCRIPTION
• Processor Interface
Data Bus (0 0 -0 7)
The Bi-directional data lines (Do -D 7 ) allow data transfer
between the ADU and MPU. Data bus output drivers are
three state buffers that remain in the high-impedance state
except when MPU performs a ADU read operation.
Enable (E)
The Enable signal (E) is used as strobe signal in MPU R/W
operation with the ADU internal registers. This signal is
normally derived from the HMCS6800 system clock (t/>2).
Chip Selact (CSo, CS 1 )
The Chip Select lines (CS o , CS 1 ) are used to address the
ADU. The ADU is selected when CS o is at "High" and CS 1 is
at "Low" level.
ReadlWrite (R/W)
The R/W line controls the direction of data transfer between the ADU and MPU. When R/W is at "High" level, data
of ADU is transferred to MPU. When R/W is at "Low" level,
data of MPU is transferred to ADU.
Register Select (RS o, RS 1 )
The Register Select line (RS o , RS 1 ) are used to select one
of the 4 ADU internal registers. Table 1 shows the relation
between (RS o , RS I) address and the selected register. The
lowest 2 address lines of MPU are usually used for these
signals.
Reset (RES)
This input is used to reset the ADU. An input "Low" level
on RES line forces the ADU into following status.
1) All the shift-registers in ADU are cleared and the conversion operation is stopped.
2) The GAINSEL output goes down to "Low" level. The
IRQ output is made "Off' state and the Do -D 7 are made
high impedance state.
Interrupt Request (IRQ) (Open Drain Output)
This output line is used to inform the A/D conversion end
signal to the MPU. This signal becomes active "Low" level
when IE bit in the control register 1 is "1" and IRQ bit in
the control register 2 goes "1" at the end of conversion. And
this signal returns to "High" right after The MPU reads the
A/D Data Register (R3). Programmable voltage comparison

does not affect this signal.
• Analog Data Interface
Analog Input (Alo-Al lS )
The Input Analog Data to be measured is applied to these
Analog Input (Alo-AI ls ). These are multiplexed by internal
16 channel multiplexer and output to COMMOM pin. A
particular input channel is selected when the multiplexer
channel address is programmed into the control Register 1
(Rl).
Multiplexer Common Output (COMMON)
This signal is the output of the 16 channel analog multiplexer, and may be connected to the input of pre-amplifier
or sample/hold circuit according to user's purposes. When no
external circuit needed, this output should be connected to
the COMPIN input.
Comparator Input (COMPIN)
This is a high impedance input line that is used to transmit
selected analog data to comparator. The COMMON line is
usually connected to this input. When external Pre-amplifier
or Sample/hold circuit is used, output of these circuits may
be connected to this input.
Reference Voltage (+) (REF (+))
This line is used to apply the standard voltage to the internalladder resistors.
Reference Voltage (-) (REF (-))
This line is connected to the analog ground.
• AOU Control
Conversion Clock (ClK)
The CLK is a standard clock input signals which defmes
internal timing for A/D conversion and PC operation.
Gain Select (GAINSEl) (CMOS Compatible Output)
This output is used to control the external circuit. The
function of this signal is programmable and it is specified
by (Gl, GO) bits in Control Register O. By using this output,
user can control the auto-range-switching of external preamplifier, also control external sample & hold circuit, etc. as
well.

[NOTE] This LSI is different from other HMCS6800 family
LSIs in following function
• RES doesn't affect IE bit of RO

• FUNCTION OF INTERNAL REGISTERS
• Structure
Table 1 Internal Registers of the ADU

(Note)

0 - - - YES

x ---NO

550

~HITACHI

- - - - - - - - - - - - - - - - - - - H 046508, H046508-1 ,H 046508A,H 046508A-1
Control Register 0 (RO)

1716151413

I IE I CD I ST

,

L-

"1 "
Not Used

"0"

See Table 2

Mode Select
I

Not Used
Not Used

!

Settling Time

Available

ClK Divider

ClK/2

Interrupt Enable *

Enable IRQ

Figure 8 Control Register

Not Available
ClK

-r---

Mask IRQ
'RES doesn't affect IE bit.

a

Control Register 1 (R1)

"1"
MPX Channel Address
MPX Inhibit
L-______________________~

"0"

See Table 3
Inhibited

Not Inhibited

Prog. Comparator mode

A/D Converter mode

GAINSEl Enable

GAINSEl Enable

GAINSEl Disable

Short-cycle Conversion

8-bit length

10-bit length

--

Prog. Comparator Select

Figure 9 Control Register 1
Status & AID Data Register (H)

"1"

"0"

Upper bit (10 bit data)
Data Weight

I

Data Over Scale flag

See Table 4.
Data is over scale

Within the scale

Programmable
Comparator Output

VAin> Vp

VAin

Busy flag

Under Conversion

Conversion Completed

IRQ flag

Requested

Not Requested

Not Used

< Vp

VAin: Unknown Input Voltage
Vp: Programmed Voltage by R4
Cg, C8 bits are cleared when 8 bit AID conversion is performed.

Figure 10 Status & A/D Data Register (H)

AID Data Register (L)

I~71

~6 I ~51 ~41 ~31 ~2 I~, I ~O I
L -_ _ _ _ _ _ _

• {lOWer order 8 .bit Data (Normal 1a ~it Conversion)
8 bit Data (8 bit Short-cycle Conversion)

----I~

Figure 11 A/D Data Register (L)

~HITACHI

551

H D46508,HD46508-1,H D4650SA,H D 4 6 5 0 8 A - 1 - - - - - - - - - - - - - - - - - PC Data Register

L - - - - - - - - - - 8 bit Data for Programmable Voltage Comparison
Figure 12 PC Data Register

SC ="1", Short-cycle conversion
(8 bit length)
SC ="0", Normal conversion
(10 bit length)

SCbit
(Short-cycle)
• Description for the Internal Registers
Control Register 0 (RO)
This Register is a 5-bit read/write register that is used to
specify Interrupt Enable (IE), CLK Divider (CD), Settling
Time (ST) and Mode Select (GO, GI). This Register should
be written before writing RI.

IE bit:
(Interrupt Enable)
CD bit:
(Clock Divider)

JIE

="I",

Interrupt is requested
tluough the IRQ output.
Interrupt is masked.

lIE ="0",
CD ="I", CLK + 2 is used as internal

GS bit
(GAINSEL Enable)

ST= "I", First comparison is executed
after I expanded cycle in
order to compensate external amplifiers settling delay.
Cycle is not delayed.

L= . o..,

= "1",

Internal MPX channel is
inhibited in order to use
external MPX channel.
MI ="0", Internal MPX channel is
used.

MI bit
(MPX Inhibit)

lMI

Do-D3
(MPX channel)

TIlese bits are used to specify the function of GAINSEL signal when GS bit
is "I".

GO, GI bit;
(Mode select)

r:: ~ : ~: :

GAINSEL signal is
enabled. The function of
GAINSEL is specified by
(GO, G 1) bits.
GAINSEL signal is disabled. ("Low" level)

PC bit
{PC = "I" Programmable voltage
(program comparator)
, comparator mode
PC= "0", AID conversion mode

clock.
{
CD="O", CLK is used directly.

STbit:
(Settling Time)

These bits are used to select the
particular MPX channel.

Table 3 MPX Channel Addressing
03

02

01

DO

0

0

0

0

0

Alo

1

0

0

0

1

All

Mode Select

2

0

0

1

0

AI2

Channel #1
Table 2 Function of GO, G1

Analog Input

G1

GO

0
0

0

Sample & Hold

3

0

0

1

1

AI3

1

Auto Range-Switching x 2

4

1

0

0

AI4

1

0

Auto Range-Switching x 4

5

1

0

1

Als

1

1

Programmable Gain Control

6
7

0
0
0
0

1

1

0

AI6

Control Register 1 (R1)
This register is an 8-bit read/write register that is used to
store the command for A/D conversion mode and programmable comparison mode. This register includes MPX channel
address (Do -D 3 ), MPX inhibit (MI), progranwable comparator select (PC), GAINSEL enable (GS) and short-cycle
conversion (SC) bits. When this register (Rl) is progranwed,
each conversion mode starts.

552

f

$

HITACHI

1

1

1

AI,

8
9

1

0

0

0

AI8

1

0

0

1

10

1

0

1

0

AI9
Al lo

1

1

AlII

0
0

0

1

1

0

AI12
AI 13
AI14

1

1

1

AilS

11

1

12

1

0
1

13

1

1

14

1

15

1

1

- - - - - - - - - - - - - - - - - - H 04650S,H 046508-1,H 04650SA,H 04650SA-1
Table 4 Function Select
PC

Function

SC
0

10 bit AD CONY.

0
1
1

x

8 bit AD CONY.
PROG. COMP (8 bit)

GS

(GO, G1)

0

DISABLE

1

ENABLE*

0

DISABLE

1

ENABLE*

x

DISABLE

OV bit
(Over scale)

This bit is set when analog data is
greater than or equal to reference Voltage (V REF (+»).

PCO bit
(programmable
comparator
Output)

This bit indicates the result of programmable voltage comparison.
"1"~PCO
VAin >Vp
"O"~PCO
VAin

410
1024 •

V REF (+)

VAin>

206
1024 •

V REF (+)

Analog Input Voltage to be measured
Voltage Applied to REF(+)

$

HITACHI

553

:I:

01
01

o

~

~

0)

01

o

WAITE WRITE
Reg.O Reg. 1

READ READ
Reg. 2 Reg. 3

I f .

I

I

I

I
I

I
I

I
I

I
I

I
I

f

I

I

I

~
:I:

o

~

0)

c.n

o
:

cs,

i

:

:

I

•

I

:

: :

~

R/W,CSo

R::~::'~:
c~nve==

Control

~e~)iSler 0
Register
Control
IR1)

~

~

~

~

Analog
MPX
Out

~

o

c.n

o(X)

2'

LSB 12")

~}WW@

-----------t----------=====::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::~~:::::::::::jt::::::::::::i:::t:j:::::

BSY _________.......

--------------------------------------------------------------------------------~~----------~~
,,& AID
IRQ

Status

DataRegisterIHI~~~~~~

IR2)

AID Data
Register III
IR3)

o(X)
~

~
MSB 12" I

01

0)

CLK

()

o

0)

:I:

I~~~~~~<;=====================================J

Cycle

:I:

1>

0

$ ~~
J:

cp
~

~

"""","""","""",,,,,,,:-:g,,::,",,~,,,,,,:-:g,,::~~~~~~~~~~~~~~~~~~~~~~~~.

I

I

~~

Figure 13 AID Conversion Timing Chart (Basic Sequence)

~

- - - - - - - - - - - - - - - - - - H 04650S, H04650S-1 ,H04650SA,H 04650SA-1
• AID Conversion and PC sequence

(tcyc=1ps)

10 bits AID Conversion
1) Basic Sequence
SC = "0"

Conversion Start

Conversion End

2°

( ST = "0")
GS= "0"

(LSB)

2) Basic Sequence

(When overscale
is detected)
Overscale check Cycle
(Analog Input is compared with VREF(+I-)
3) Expanded Sequence

"0")

SC =
( ST = "1"
GS = "0"

MSB cycle is expanded to compensate external amplifier's settling delay.
4) Auto Range-

Switching Control
Sequence
SC = "0"
ST = "0"

1

GS = "1" ~
GO = "0"
\ Gl = "1")
I
or
I
GO'" "1"
I Gl = "0")

' - + - - - - Auto Range- switching cycle

(Analog Input is compared with 1/2 V REF (+) or 1/4 V REF (+)
at this cycle)

J

5) Auto Range-

Switching & Expansion
Control
Sequence
SC = "0"

a) Analog Input

< 1/2 V REF (+) or 1/4 V REF (+)

r - - - -....

"GAINSEL" goes "High"

ST = "1"
GS = "1"
GO = "0"
iGl =

"1,,)

or
I

b) Analog Input> 1/2V REF (+) or 1/4VREF (+)

GO = "1"
Gl = "0")

6) Sample & Hold

Control Sequence

(

~~: ::~::)

GS = "1"
GO = "0"
G1 = "0"

$

HITACHI

555

H04650S,H 04650S-1 ,H04650SA,H 0 4 6 5 0 S A - 1 - - - - - - - - - - - - - - - - - - 7) Programmable
Gain Control
Sequence

(

"GAINSEL" always goes "High"

~~: ::g::)

. GS= "1"
GO= "1"
Gl = "1"

8) Programmable

Gain & Expansion
Control Sequence
SC="O")
ST = "1"
GS= "1"
( GO= "1"
Gl = "1"

8 Bit AID Conversion
1) Basic Sequence

~~: ::6::)
( GS=
"0"
Additional conversion cycle
for rounding the LSB - 1 Bit.
,/.

2) Expanded Sequence

"1")

SC =
( ST = "1"
GS= "0"

Programmable Voltage Comparison

~
~

1) Basic Sequence

(

"1")

PC =
ST = "0"

2) Expanded Sequence

(

PC
ST

= "1"\
= "1")

• HOW TO USE TH E ADU

•

Functions of GAINSEL
The ADU is equipped with programmable GAINSEL output signal. By using GAINSEL output and external circuit,
the ADU is able to implement following control.

1) Auto Range-Switching (Auto Gain) Control
2) Programmable Gain control
3) Sample & Hold control
GAINSEL output is controlled by Mode Select bit (GO,
G 1) when GAINSEL enable bit (GS) is "1".

Table 6 GAINSEL Control
GS

Gl

GO

0

x

x

"Low"

Normal Use (GAINSEL is not used)

1

0

"High"

Sample & Hold control

1

0
0

1

1

1

0

*
*

1

1

"High"

1
*

556

GAINSEL

Control Mode

Auto Range Switching x 2 control

OW

0
0

Auto Range Switching x 4 control

**
**

Programmable Gain control

1

GAINSEl goes "High" or "low" according to the condition shown in Table 5.
See, Table 5.

$

HITACHI

- - - - - - - - - - - - - - - - - - H 04650S,H 04650S-1,H 04650SA, H04650SA-1
+SV

How to Control External Circuit

(1) Sample & Hold Control (Gl=O, GO=O)
An example of Sample & Hold circuit is shown in Fig. 14.
When ADU is set in Sample & Hold Control Mode, GAINSEL
becomes "High" level on conversion and controls the data holding.
(2) Automatic Range Switching Control (Gl=O, GO=l or Gl=
1, GO=O)
The GAINSEL signal controls the external amplifier which can
change the ratio of voltage amplification. (GAIN: 1 ~ 2 times or
1 ~ 4 times). Fig. 15 shows Automatic Range Switching Control. In this case, when the input voltage is lower than 206/1024
V REF(+) , GAINSEL becomes "High" level. This makes the GAIN
of the amplifier change from 1 to 4 times, and 4 times value
of the input voltage is AID converted. Using this function even
if an input signal is small, it is possible to execute A/D conversion in nearly full scale. In this mode, when GAINSEL signal
becomes "High", DW bit becomes "1" to show the range
switching is in a progress.
(3) Programmable GAIN Control (G 1=1, GO=I)
The GAINSEL signal is used for controlling the external
amplifier of any GAIN which is fit to the system.
In this mode, GAINSEL always becomes "High" at the
beginning of A/D conversion, so the change of range is controlled by GS bit. Converted data need to be corrected in software in accordance with GAIN of the amplifier.
This mode is effective in the case of converting very small
input voltage.
(Note) Refer to "ADU Function Sequence" (A/D Conversion
and PC Sequence) for the timing in which GAINSEL signal becomes "High". GAINSEL signal becomes
"Low" in accordance with "1" ~ "0" change of BSY
bit. Refer to Fig. 13.

GAIN
SEL

Vss

REF (-I

CDMPIN

ADU

Figure 15 Pre·amplifier Circuit
(x1, x4 Auto-Range Switching)
•

Overscale Check

ADU is equipped with hardware overscale detection
function. The overscale detection is performed automatically when the result of AID conversion is 2n-l (all
bits = I). When analog input VAin is higher than V REF (+),
overscale bit (OV) is set to "1". The definition of the overscale is illustrated in Fig. 17. And the flow of overscale
check is shown in Fig. 16.

x1 Sample & Hold

HD14066
OR Eau

Figure 16 Overscale Check Flow

r-------------------

2"

I

2" -1

ffl
o

8
COMMON

Vss

GAINSEL

REF(-)

COMPIN

ideal transition

"':

I
1101
I overscale area
~ADU

I
101 I

I

I

I

I
1001
I
011 1

I

I

I
I
I
I
I

I

0101
I
I

ADU

0011

I
000

I

0: liS: 1/4: 3/S: 1/2 I 5/8 : 3/4 : 7/S

I

I

I

~

:

~:

S'/8overseale
refers voltage

~VReFI+)

Figure 14 Sample & Hold Circuit

R/2 R

R

3R/2

(F51

NORMALIZED ANALOG INPUT

Figure 17 Definition ADU's Overscale

eHITACHI

557

HD46508,HD46508-1,HD46508A,HD46508A-1-------_ _ _ _ _ _ _ _ _ _ __
•

Usage of the PC

output is stored into PCO bit at the end of comarison.
The programmable voltage comparison time is so short
that the interrupt is not requested at this mode. The end of
comparison needs to be confirmed by reading the 1-+0 transition of the BSY bit in R2.

The ADU has a programmable threshold voltage comparator (PC) function. The threshold voltage is pre-setable
from OV to 5V range with 8 bit resolution. The comparator's

to
"'"""'------ Reg. R2 ..... MPU

~

I

I

I

~------------------------Figure 18 Function Diagram of the PC

r--

0
Rq

SC

GS

PC

MI

I

address

I

D1

OV

DW

I

C9

C8

83

82

81

80

I

0

R211RQ

I I I
8SY

PCO

86

85

~

D2

D3

I

DO

I

PC=O
PC=1

peo :

8,,-8 7
R41

87

84

AID conversion mode
Programmable Voltage
Comparison Mode
Programmable compardtor
output (1 bit data)
V p setting byte (upper
byte of 10 bit D/A.
Lower byte IS set to 0)

Figure 19 Registers of the PC Mode

(

AD CONV.

(a) General PC
(c) Check and AID conv.
(b) Window comparator

Figure 20 PC Application Flow Chart Examples

558

~HITACHI

)

- - - - - - - - - - - - - - - - - - - H 046508,H 046508-1 ,H 046508A,H046508A-1
• How to use MI bit
MI bit (RI) functions as follows.
MI = I: Internal MPX channel is inhibited in order to use
attached external MPX channel.
{
MI = 0: Internal MPX channel is enabled.
(8 b,t A/O
conversion)

MI bit used to select either of External MPX and Internal
MPX. External MP~ is connected as follows.

External MPX
------~

r---~---.

(Addressed at MI=1)

COMMON

(Programmable
Voltage
Comparison)

COMPIN

AOU

[NOTE]

When external MPX is used as the way figure 20,
1 dammy AD conversion or PC at MI=1 should be
performed.

Figure 21 How to use External MPX

(d) Voltage Comparison between two channels.

Figure 20 PC Application Flow Chart Examples (continued)

• EXAMPLE OF APPLIED CIRCUIT OF THE ADU
R/IN
CSt

Alo

R/IN
A"

AI,
VMA

CS o
H046508
AOU

,

~

AIlS

Ao

H06S00

A,

MPU

0 0 -0 7
COMMON

IRQ

+5V

iRQ

Vee

Figure 22 Single ADU System

_HITACHI

559

HD46508,HD46508-1,HD46508A,HD46508A-1------------------r---

E

Alo

R/W

AI.

Signal

:

Source

H046508
AOU

I

RS o
RS.

I

AIlS

-

r==B=

CS. CS o

I

I
I

[

Ao

Ao
A.

T

A,.

Au-A.
H06800
MPU

0.-0 7
COMMON

i"im

COMPIN

CLK

f--+5V{
f-- f -

-

GAINSEL REF(+)

!RT'1
I
I
I

CLOCK

Alo

E
R/W

All

CS., CS o

I

Signal

I
I

Source

!

I
I
AI ..

LftT

H046508
AOU RS.
RS.

A.
AI

0.-0,

j-------..,

i
I
:

PA

•

:
I
I

l_______ J

iAn

COMMON
COMPIN
CLK
GAINSEL REF(+)

TRT'T

·SEE
GAIN SEL
USAGE

Figure 23 Multi ADU System

560

~HITACHI

n-

=[;]
REF

- - - - - - - - - - - - - - - - - - - H D4650S,HD4650S-1 ,HD4650SA,H D4650SA-1
•

DEFINITIONS OF ACCURACY
Definitions of accuracy applyed to HD46508 are as follows.
(I) Resolution ... The number of output binary digit.
(2) Offset Error ... The difference between actual input voltage and ideal input voltage for the first transition. (when
digital output code is changed from 000 ... 00 to 000 ...
01.)
(3) Full Scale Error ... The difference between actual input
voltage and ideal input voltage for the fmal transition.
(when digital output code is changed from 111 ... 10 to

111 ... 11.)
(4) Quantizing Error ... Error equipped in A/D converter
inherently. Always ±~ LSB is applied.
(5) Non-linearity Error ... The maximum deviation of the
actual transfer line from an ideal straight line. This error
doesn't include Quantizing Error, Offset, or Full Scale
Errors.
(6) Absolute Accuracy ... The deviation of the digital output
code from an analog input voltage. Absolute accuracy includes all of (2), (3), (4), (5).

Digital Output Code

Digital Output Code

111

.110
101

Lldeal Straight Line

100
011
010

Analog
Input
Voltage
Analog
Input
Voltage

~~~~~~~~~~~~+-~~~F~S~

~~--------------------------~-

Figure 24 Definition of Accuracy

~HITACHI

561

HD146818
RTC (Real Time

Clock Plus RAM)

The HOl46818 is a HMCS6800 peripheral CMOS device
which combines three unique features: a complete time-of-day
clock with alarm and one hundred calendar, a programmable
periodic interrupt and square-wave generator, and 50 bytes of
Low-power static RAM.
This device includes H06801, H06301 multiplexed bus
interface circuit and 8085's multiplexed bus interface as well,
so it can be directly connected to H0680 I , H0630 1 and 8085.
The Real-Time Clock plus RAM has two distinct uses. First.
it is designed as battery powered CMOS part including all the
common battery backed-up functions such as RAM, time, and
calender. Secondly, the HOl46818 may be used with a CMOS
microprocessor to relieve the software of timekeeping workload and to extend the available RAM of an MPU such as the
H06301.
• FEATURES
•

Time-of-Day Clock and Calendar
• Counts Seconds, Minutes, and Hours of the Day
• Counts Days of Week, Date, Month, and Year
Binary or BCD Representation of Time, Calendar, and Alarm
12- or 24 Hour Clock with AM and PM in 12-Hour Mode
Automatic End of Month Recognition
Automatic Leap Year Compensation
Interfaced with Software as 64 RAM Locations
14 Bytes of Clock and Control Register
• 50 Bytes of General Purpose RAM
Three Interrupt are Separately Software Maskable and Testable
• Time-of-Day Alarm, Once-per-Second to Once-per-Day
• Periodic Rates from 30.5J.[s to 500ms
• End-of-Clock Update Cycle
Programmable Square-Wave Output Signal
Three Time Base Input Options
• 4.194304 MHz
• 1.048576 MHz
• 32.768 kHz
Clock Output May be used as Microprocessor Clock Input
• At Time Base Frequency +4 or + 1
Multiplexed Bus Interface Circuit of HD6801, HD6301 and
8085
Low-Power, High-Speed, High-Density CMOS
Battery Backed-up Operation
Motorola MC146818 Compatible

•
•
•
•
•

•

•
•

•
•
•
•
•

(DP-24)
HD146818FP

(FP-24)
The Flat Package product is under development.

•

PIN ARRANGEMENT

NC

VCC

OSC,

SQw
PS

OSC2

CKOUT

ADo
AD,
AD2

CKFS

HD146818

iRQ

AD3

RES

AD4

OS

ADs

NC

ADs

R/Vi

AD7

AS

Vss

CE
(Top View)

,
• ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage
Input Voltage

•

Value

Vee *
V in *

-0.3 -- +7.0

V

-0.3 -- +7.0

V

Operating Temperature

T opr

o -+70

Storage Temperature

T stg

-55 -- +150

With respect to Vss (SYSTEM

(NOTE)

562

Symbol

GNDI

Permanent LSI damage may occur if maximum rating are exceeded. Normal operation should be under
recomended operating condition. If these conditions are exceeded. it could affect reliability of LSI.

~HITACHI

Unit

°c
°c

----------------------------------------------------------------HD146818
•

RECOMENDED OPERATING CONDITIONS
Item

Symbol

min

typ

max

Unit

Supply Voltage

Vee *
V 1L *

4.5

5.0

5.25

V

-0.3

-

0.7

V

Vee
70

°c

Input Voltage

V 1H *

Operating Temperature

Topr

Vee- 1 .O
0

25

V

* With respect to Vss (SYSTEM GND)
(NOTE) Refer to Battery Backed-up Electrical characteristics,

•

ELECTRICAL CHARACTERISTICS

•

DC CHARACTERISTICS (Vee = 4.5 - 5.25V, Vss = OV, Ta = 0 - +70°C, unless otherwise noted.)
Item

Symbol

Test Condition

AD o -AD 7 , CE, AS,
R/W, DS, CKFS, PS
Input "High" Voltage

V 1H

RES
OSCI
AD o -AD 7 , CE, AS,
R/W, DS, CKFS, PS

Input "Low" Voltage

V 1L

RES
OSCI

min

typ

max

V ee -2,O

-

Vee

V ee -1.0

-

Vee

V ee -l,O

-

Vee

-0,3

-

0.7

-0,3

-

0,8

-0.3

Unit

V

V

0,8

Input Leakage Current

OSC I , CE, AS, R/W,
DS, RES, CKFS, PS

Ilinl

-

-

2.5

p.A

Three-state (off state)
Input Current

ADo -AD 7

ilTsli

-

-

10

p.A

IRO

I LOH

-

-

10

p.A

IOH = -1,6 mA

4.1

-

-

V

IOH <-10IlA

Vee- 0 . 1

-

-

V

-

-

0.5

V

-

-

12.5

pF

-

-

12.5

pF

-

-

12.5

pF

-

10

-

-

2

-

300

500

-

-

10

-

-

7

-

-

5
4

60

100

Output Leakage Current

AD o -AD 7
Output "High" Voltage

Output "Low" Voltage

SOW,CKOUT
AD o -AD 7
SOW,CKOUT
AD o -AD 7
CKOUT

V OH

IOL = 1,6 mA
VOL

IRO, SOW
I nput Capacitance

AD o -AD 7
All inputs except
AD o -AD 7

Output Capacitance

SOW, CKOUT,IRO

Supply Current
(MPU Read/Write
operating)
Crystal
Oscillation
Supply Current*
(MPU not operating)

fose

Supply Current
(MPU Read/Write
operating)

fose

External
Clock
Supply Current**
(MPU not operating)

fose
fose
fose

= 4 MHz
= 1 MHz
= 32 kHz
= 4 MHz

IOL
Cin

fose
fose
fose

= 32 kHz
= 4 MHz
= 1 MHz
= 32 kHz
= 4 MHz

fose = 1 MHz
fosc = 32 kHz

= 1.6 mA

V· =OV

T~n = 250C
f

= 1 MHz

Cout

lee *

fose = 1 MHz
fose

IOL = 1.6 mA

lee *

Vee = 5.0V
SOW: disable
CKOUT = fose
(No Load)
tcyC = 11ls
Circuit: Fig. 11
Parameter:
Table 1
Vee = 5.0V
SOW: disable
CKOUT = fose
(No Load)
OSC 2 : open
tCYC = 11ls
Circuit: Fig. 17

7

mA

5
5

1

mA
IlA
mA

mA
IlA

* Supply current of HD146B1 B is defined as the value when the time-base frequency to be used is programmed into Register A.
When power is turned on, these bits are unfixed, so there is a case that current more than the above specification may flow,
Please never fail to set the time-base frequency after turning on power supply.
** V1H min = Vee- O.2V
VIL max= VSS +O·2V

~HITACHI

563

HD146818----------------------------------------------------____________
•

AC CHARACTERISTICS (Vee
BUS TIMING

= 4.5 -

5.25V, Vss

=OV, Ta =0 -

+70°C, unless otherwise noted.)

Item

Symbol

min

typ

max

Unit

tAsr

AS Fall Time

tASf

Delay Time DS/E to AS/ALE Rise

tASO

DS Rise Time

tosr

DS Fall Time
Pulse Width, DS/E Low or RD/WR "High"

tOSf
PW OSH

-

ns

AS Rise Time

Pulse Width, DS/E High or RD/WR "Low"

PWos L

Delay Time, AS/ALE to DS/E Rise

tAsos

Address Setup Time (R/W)

tAS1

Address Setup Time (CE)

tAS2

Address Hold Time (R/W, CE)

tAH

Muxed Address Valid Time to AS/ALE Fall

tAS L

Muxed Address Hold Time

tAHL

Peripheral Data Setup Time

tosw

Write Data Hold Time

tOHW

Peripheral Output Data Delay Time From DS/E or RD

tOOR

Read Ddta Hold Time

tOHR

953
100
40
325
300
90
15
55
10
50
20
195
0
10

-

Pulse Width, AS/ALE "High"

tcyc
PW ASH

Symbol

Cycle Time

-

-

ns

30
30
30
30
-

ns

-

ns

ns
ns
ns
ns
ns
ns
ns

-

ns

-

ns

-

ns
ns

-

220
-

min

typ

max

Unit

-

-

100
1000
2.0
2.0
2.0

-

-

ns
ns
ns
ns

CONTROL SIGNAL TIMING
fl<.

Item
Oscillator Startup

564

11 MHz,4 MHz
32 kHz
1

tRC

Power Sense Pulse Width

tPWL

Power Sense Delay Time

tpLH

5.0
5.0
5.0
5.0

I RQ Release from DS

tlRoS

-

I RQ Release from RES

tlRR

VRT Bit Delay

tVRTO

Reset Pulse Width

tRWL

Reset Delay Time

tRLH

~HITACHI

-

ms

I1S
I1S
I1S
I1S
I1S
I1S
I1S

----------------------------------------------------------------HD146818

t

~I\

~

V

AS

OS

\

-

-

t ASO
V 1L

-

eye

!---tASOSVIH

lr--

J

k- VIL

I--PW ASH -

-

f--tASr

-

f-tASf

~

tOSr

f---

I
~

f--

~\

~

VIH

It-

VIL
PW OSH

PWOSL

~C

X

VIH

..... VIL

-

-

tAS2

tASI

f--

-

~

~v

VI\~

AD7

(W rite)

tASL

tAHL

f---

I----

..31\

}

VIH

\k:VIL

7/

\

VIL

~
ADo- AD7
(Re ad)

tOHW

I------- t OSW-

Jf-VIH

Jf\ V 1L
V 1H

1---

tAH

1-1--

f------toOR -

~

V

~

V

-

tAHL

~

~

t OHR f - -

J~VOH

~II\

\k:-VOL

~

(NOTE)

VIH = V OH
VIL = O.7V
VOL = O.5V

=

Vcc-2.OV

Figure 1 Bus Read, Write Timing (6801 Family)

@HITACHI

565

HD14681S------------------------------------------------------------___
t eye

V,.
ALE

.J

(AS pin)

~

(OS pin )

-

'i;sr

,j~

R5

VIH

j

\rVIL

PWASH

t ASOS

t--

tASf

r

VIH
PW OSH

\ (- VIL

~

PWOSL

J~
in)

CE

--

tOOR

-

t AS2

~-

t--

tAH

V-

VIH.\
VIL

t ASL

tAHL

/

AO,,-A 0;

I---

"\~

___ VVIL

Figure 2

~VOH

/

,""V IH

~

(Addre ssData Bus)

tOHR

r--

t---

¥VOL

(NOTE)

Read Timing (8085 Family)

VIH = VOH = Vee-2.OV
VIL = O.7V, VOL = O.5V

teyc

,1/

ALE

~

(AS pin)

RO
(OS pin )

)"
-

If'-

VIH
PWASH
- t ASr

\

J

VIL
~tASf

-

tASOS

tASD

VIH

J
WR

~

~I\

PWOSH

VIL!

V

-'

t As2

(R/W P in)

t----

PW OSL

VI~/\

-

"'l

tASL

ADo-A 07

/

(Addre ss/Data Bus)

"\~

~

~tosw_

K.VIH
VVIL

"\

Figure 3 Write Timing (8085 Family)

$

HITACHI

tOHw

,,-VIH

/

"VVIL

(NOTE)

566

-V
tAH

V IL 1(.

VIH = Vee - 2.0V
VIL =O.7V

----------------------------------------------------------------HD146818

DS~

r--------t

RES

RWL-------I

--tIRRj_
V OH

(NOTE)

VIL = O.7V, VOH = VCC-2.OV
----------

Figure 4

(NOTE)

I RQ Release Delay (from DS)

V 1L = O.8V
VO H = VCC-2.0V

Figure 5 IRQ Release Delay (from RES)

4.SV
Vec

ov

PS

~)'r------,r-

VR_T_B_i_t____________·_·o_·_·_ _ _ _ _

~1

~I_··_o_·_·

··r· •
________

~

(NOTE)

VIH = V c c-2.0V
VIL=O.7V

* The VRT bit is set to a "1" by reading control register #0. There is no additional way to clear the VRT bit.

Figure 6 VRT Bit Clear Timing

vee_~V

~ ~t""

Figure 7 RES Release Delay

$

HITACHI

567

HD14681~8---------------------------------------------------------------5.0V

5.0V

3kn

Test Terminal
Test Terminal
Diode
1S2074 @ or equiv.

R

C = 130pF
RL = 2kn
R = 2.55kn

(b) IRQ Load Circuit

(a) ADo -AD 7 , SQW, CKOUT

•
•

Figure 8

Test Load

BATTERY BACKED-UP OPERATION
DEFINITION OF BATTERY BACKED-UP OPERATION

Active functions

(I) Clock function
•

(2) Retention of RAM data
(3) RES, IRQ, CKFS, CKOUT, PS, SQW functions
Inactive functions
(1) Data bus read/write operation

=OV, Ta =0 -

BATTERY BACKED-UP ELECTRICAL CHARACTERISTICS (Vss
Item

Symbol

Supply Voltage

Test Condition

Supply
Current

ICCL *
External
Clock

Battery Backed-up Transit
Setup Time

tCE

Operation Recovery Time

tR

Supply Voltage Fall Time

tpf

Supply Voltage Rise Time

tPr

typ

max

2.7

-

4.5

V

-

600

p.A

350

p.A

50

100

p.A

-

500

p.A

lMHz

-

150

p.A

32kHz

-

30

70

p.A

0

-

-

ns

t cvc

V CCL = 3.0V
saw : disable
CKOUT: fosc (No load)

4MHz

VC CL = 3.0V
saw: disable
CKOUT: fosc (No load)

4MHz

Input "Low" Voltage
Output "High" Voltage
Output "Low" Voltage

V 1HL

VOLL

CE, PS
CKFS

0.7XVCCL
2.5

-

V CCL

V

RES

0.8XVCCL

V CCL

V

OSCI

0.8XVCCL

-

V CCL

V

-

0.5

V

0.5

V

-

0.5

V

-

V

0.5

V

-

0.5

V

300

= 2.7V-3.5V
V CCL = 3.5V-4.5V

IOH

= -800p.A

IOL = 800p.A

CKFS, PS

-0.3

RES

-0.3

OSC I

-0.3

SaW,CKOUT

0.8XVCCL

SQW,CKOUT

-

IRQ

* The time-base frequency to be used needs to be chosen in Register A.

568

Unit

-

300

V 1LL
V OHL

lMHz
32kHz

Fig.9

V CCL

Input "High" Voltage

+70°C, unless otherwise noted.)
min

V CCL
Crystal
Oscillation

0------...

~HITACHI

-

ns

-

p.s

-

p.s

V CCL

V

----------------------------------------------------------------HD146818

Battery Backed-up Mode

v cc ----------____,

VIHl

Figure 9 Battery Backed-up Timing

CKaUT
CKFS

ascI
asc.

Bus
Interface

Clockl
Calendar
Update

Clock, Alarm,
Calendar RAM
(10 Bytes)

BCDI
Binary
Increment
User RAM
(50 Bytes)

Figure 10 Block Diagram

~HITACHI

569

HD146818~------------------------------------------------------------•

CRYSTAL OSCILLATION CIRCUIT

Table 1 Oscillator Circuit Parameters

The on-chip oscillator is designed for a parallel resonant
crystal at 4.194304 MHz or 1.048576 MHz or 32.768 kHz
frequencies. The crystal connections are shown in Figure 11.
HD146818
OSC,

o

~

Paramete

•

32.768 kHz

Rs

-

-

150 kil

Rf

150 kil

150 kil

5.6 Mil

Cin

22 pF

33 pF

15 pF

Cout

22 pF

33 pF

33 pF

CL

-

-

33 pF

CI

80 il (max)

700 il (max)

40 kil (max)

(NOTE)

,. Rs, CL are used for 32.768 kHz only.

2. Capacitance (Cin) should be adjusted to accurate frequency.
Parameters listed above are applied to the supply current
measurement (See table of DC CHARACTERISTICS).

3. CI: Crystal Impedance

Rf

Figure 11

4.194304 MHz 1.048576 MHz

Crystal Oscillator Connection

NOTE FOR BOARD DESIGN OF THE OSCILLATION
CIRCUIT

In designing the board, the following notes should be taken
when the crystal oscillator is used.
(l) Crystal oscillator, load capacity Cin, Cout> CL and Rf, Rs
must be placed near the LSI as much as possible.
Normal oscillation may be disturbed when external]
[ noise is induced to pin 2 and 3.

(2) Pin 3 signal line should be wired apart froin pin 4 signal
line as much as possible. Don't wire them in parallel, or
normal oscillation may be disturbed when this signal is
feedbacked to asc I .
(3) A signal line or a power source line must not cross or go
near the oscillation circuit line' as shown in the right figure
to prevent the induction from these lines and perform the
correct oscillation. The resistance among aSCI, asc 2 and
other pins should be over 10Mil.
The following design must be avoided.

~"IA 'i'MI
Signal C
2

2

3

3

HD146818

HD146818

Figure 12 Note for Board Design of the Oscillation Circuit

570

B

I

~HITACHI

---------------------------------------------------------------HD146818
•

INTERFACE CIRCUIT FOR HD6801, HD6301 AND
8085 PROCESSOR
HD146818 has a new interface circuit which permits the
HDl46818 to be directly interfaced with many type of multiplexed bus microprocessor such as HD6801, HD6301 and 8085
etc_
H06801,
H06301 Type 8085 Type
MPU Signals
MPU Signals
AS

H0146818
Pin Signals

ALE

Figure 13 shows the bus control circuit. This circuit automatically selects the processor type by using AS/ ASE to latch
the state of DS/RD pin_ Since DS is always "Low" and RD is
always "High during AS/ALE, the latch automatically indicates
which processor type is connected_

Q

0

C

AS

IT

OS, E, or 1/>2

RfW

8085

Internal
Signals

Bus

6801
Bus

OS

Read Enable

RfW

Write Enable

Figure 13 Functional Diagram of the Bus Control Circuit

•

ADDRESS MAP
Figure 14 shows the address map of the HD146818_ The
memory consists of 50 general purpose RAM bytes, 10 RAM
bytes which normally contain the time, calendar, and alarm
data, and four control and status bytes_ All 64 bytes are
directly readable and writable by the processor program except Registers C and D which are read only _ Bit 7 of Register
A and the seconds byte are also read only _ Bit 7, of the second
byte, always reads "0". The contents of the four control and
status registers are described in the Register section.

•

Time, Calendar, and Alarm Locations
The processor program obtains time and calendar information by reading the appropriate locations. The program
0

00

may initialize the time, calendar, and alarm by wntlOg to
these RAM locations_ The contents of the 10 time, calendar,
and alarm byte may be either binary or binary-coded decimal
(BCD)_
Before initializing the internal registers, the SET bit in
Register B should be set to a "I" to prevent time/calendar
updates from occurring_ The program initializes the 10 locations in the selected format (binary or BCD), then indicates
the format in the data mode (DM) bit of Register B. All 10
time, calendar, and alarm bytes must use the same data mode,
either binary or BCD_ The SET bit may now be cleared to
allow updates_ Once initialized the real-time clock makes
all updates in the selected data mode_ The data mode cannot
be changed without reinitializing the IO data bytes_
0

14
Bytes
13

00

14

50
Bytes
User
RAM

Seconds

0o

Sec Alarm

0

2

Minutes

0

3

Min Alarm

0

4

Hours

04

5

HrAlarm

05

6

Day of Wk

06
0

7

Date of Mo

8

Month

9

Year

09

Register A

0A

Register B

0B

Register C

0C

Register 0

0o

63

Binary
or BCD
Contents

08

~----------------~
Figure 14 Address Map

~HITACHI

571

HD146818-----------------------------------------------------------Table 2 shows the binary and BCD formats of the 10 time,
calendar, and alarm locations. The 24/12 bit in Register B
establishes whether the hour locations represent I-to-12 or
0-to-23. The 24/12 bit cannot be changed without reinitializing
the hour locations. When the 12-hour format is selected the
high-order bit of the hours byte represents PM when it is a "I ".
The time, calendar, and alarm bytes are not always accessable by the processor program. Once-per-second the 10
bytes are switched to the update logic to be advanced by one
second and to check for an alarm condition. If any of the 10
bytes are read at this time, the data outputs are undefined.
The update lockout time is 248 p,s at the 4.194304 MHz and
1.048567 MHz time bases and 1948 p,s for the 32.768 kHz time
base. The Update Cycle section shows how to accommodate

the update cycle in the processor program.
The three alarm bytes may be used in two ways. When
the program inserts an alarm time in the appropriate hours,
minutes, and seconds alarm locations, the alarm interrupt is
initiated at the specified time each day if the alarm enable bit
is "I". The alternate usage is to insert a "don't care" state in
one or more of three alarm bytes. The "don't care" code is
any hexadecimal byte from CO to FF. That is, the two mostsignificant bits of each byte, when set to "1", create a "don't
care" situation. An alarm interrupt each hour is created with
a "don't care" code in the hours alarm location. Similarly, an
alarm is generated every minute with "don't care" codes in
the hours and minutes alarm bytes. The "don't care" codes
in all three alarm bytes create an interrupt every second.

Table 2 Time, Calendar, and Alarm Data Modes
Address
Location

Function

Decimal
Range

Range

Example*

Binary Data Mode

BCD Data Mode

Binary

BCD

Data Mode

Data Mode
21

0
1

Seconds

0-59

$00-$3B

$00-$59

15

Seconds Alarm

0-59

$00-$3B

$00-$59

15

21

2

Minutes

$00-$3B

$00-$59

Minutes Alarm

$00-$3B
$Ol-$OC (AM) and
$81 -$8C (PM)

$00-$59
$01-$12 (AM) and
$81 -$92 (PM)

3A
3A

58

3

0-59
0-59

05

05

4

5

6

58

Hours
(12 Hour Mode)

1-12

Hours
(24 Hour Mode)

0-23

$00-$17

$00-$23

05

05

Hours Alarm
(12 Hour Mode)

1-12

$Ol-$OC (AM) and
$81 -$8C (PM)

$01 -$12 (AM) and
$81 -$92 (PM)

05

05

Hours Alarm
(24 Hour Mode)

0-23

$00-$17

$00-$23

05

05

Day of the Week
Sunday = 1

1-7

$01 -$07

$01 -$07

05

05

$01 -$1 F

$01 -$31

7

Day of the Month

15

Month

1-31
1-12

OF

8

$Ol-$OC

$01-$12

02

02

9

Year

0-99**

$00-$63

$00-$99

4F

79

* Example: 5:58:21 Thursday 15th February 1979
** Set the lower two digits of year in AD. If this number is multiple of 4, update applied to leap year is excuted .
•

•

Static CMOS RAM

The 50 general purpose RAM bytes are not dedicated within
the HD146818. They can be used by the processor program,
and are fully available during the update cycle.
When time and calendar information must use battery
back-up, very frequently there is other non-volatile data that
must be retained when main power is removed. The 50 user
RAM bytes serve the need for low-power CMOS batterybacked storage, and extend the RAM available to the program.
When further CMOS RAM is needed, additional HD146818s
may be included in the system. The time/calendar functions
may be disabled by holding the dividers, in Register A, in the
reset state by setting the SET bit in Register B or by removing
the oscillator. Holding the dividers in reset prevents interrupts
or SQW output from operating while setting the SET bit allows
these functions to occur. With the dividers clear, the available
user RAM is extended to 59 bytes. Bit 7 of Register A, Registers
C and D, and the high-order Bit of the seconds byte cannot
effectively be used as general purpose RAM.

572

INTERRUPTS

The RTC plus RAM includes three separate fully automatic
sources of interrupts to the processor. The alarm interrupt
may be programmed to occur at rates from once-per-second
to one-a-day. The periodic interrupt may be selected for rates
from half-a-second to 30.517 p,s. The update-ended interrupt
may be used to indicate to the program that an up-date cycle
is completed. Each of these independent interrupt conditions
are described in greater detail in other sections.
The processor program selects which interrupts, if any, it
wishe-s to receive. Three bits in Register 8 enable the three
interrupts. Writing a "1" to a interrupt-enable bit permits
that interrupt to be initiated when the event occurs. A "0" in
the: interrupt-enable bit prohibits the IRQ pin from being
asserted due to the interrupt cause.
If an interrupt flag is already set when the interrupt becomes
enabled, the IRQ pin is immediately activated, though the
interrupt initiating the event may have occurred much earlier.
Thus, there are cases where the pro&ram should clear such

~HITACHI

------·---------------------------------------------------------HD146818
earlier initiated interrupts before first enabling new interrupts.
When an interrupt event occurs a flag bit is set to a "1" in
Register C. Each of the three interrupt sources have separate
flag bits in Register C, which are set independent of the state
of the corresponding enable bits in Register B. The flag bit
may be used with or without enabling the corresponding enable
bits.
In the software scanned case, the program does not enable
the interrupt. The "interrupt" flag bit becomes a status bit,
which the software interrogates, when it wishes. When the
software detects that the flag is set, it is an indication to software that the "interrupt" event occurred since the bit was
last read.
However, there is one precaution. The flag bits in Register
C are cleared (record of the interrupt event is erased) when
Register C is read. Double latching is included with Register
C so the bits which are set are stable throughout the read
cycle. All bits which are high when read by the program are
cleared, and new interrupts (on any bits) are held until after
the read cycle. One, two, or three flag bits may be found to
be set when Register C is read. The program should inspect
all utilized flag bits every time Register C is read to insure that
no interrupts are lost.
The second flag bit usage method is with fully enabled
interrupts. When an interrupt-flag bit is set and the corresponding interrupt-enable bit is also set, the IRQ pin is asserted
"Low". IRQ is asserted as long as at least one of the three
interrupt sources has its flag and enable bits both set. The

IRQF bit in Register C is a "1" whenever the IRQ pin is being
driven "Low".
The processor program can determine that the RTC initiated
the interrupt by reading Register C. A "I" in bit 7 (IRQF bit)
indicates that one of more interrupts have been initiated by
the part. The act of reading Register C clears all the then-active
flag bits, plus the IRQF bit. When the program finds IRQF set,
it should look at each of the individual flag bits in the same
byte which have the corresponding interrupt-mask bits set
and service each interrupt which is set. Again, more than one
interrupt-flag bit may be set.
•

DIVIDER STAGES

The HD 146818 has 22 binary-divider stages following the
time base as shown in Figure 10. The output of the dividers is
a I Hz signal to the update-cycle logic. The dividers are controller by three divider bus (DV2, DVI, and DVO) in Register

A.
• Divider Control
The divider-control bits have three uses, as shown in Table
3. Three usable operating time bases may be selected (4.194304
MHz, 1.048576 MHz, or 32.768 kHz). The divider chain may
be held reset, which allows precision setting of the time. When
the divider is changed from reset to an operating time base,
the first update cycle is. one second later. The divider-control
bits are also used to facilitate testing the HD146818.

Table 3 Divider Configurations
Time-Base
Frequency

Divider Bits
Register A
DV2

DV1

Dva

Operation
Mode

Divider
Reset

Bypass First
N·Divider Bits

4.194304 MHz

a

a

0

Yes

-

N=a

1.048576 MHz

0

0

1

Yes

N=2

32.768 kHz

0

1

a

Yes

-

Any

1

1

a

No

Yes

Any

1

1

1

No

Yes

-

N=7

(NOTE) Other combinations of divider bits are used for test purposes only.

• Square-Wave Output Selection
Fifteen of the 22 divider taps are made available to a l-of-15
selector as shown in Figure 10. The first purpose of selecting
a divider tap is to generate a square-wave output signal in the
SQW pin. Four bits in Register A establish the square-wave
frequency as listed in Table 4. The SQW frequency selection
shares the 1-of-15 selector with periodic interrupts.
Once the frequency is selected, the output of the SQW pin
may be turned on and off under program control with the
square-wave enable (SQWE) bit in Register B. Altering the
divider, square-wave output selection bits, or the SQW outputenable bit may generate an asymetrical waveform at the time
of execution. The square-wave output pin has a number of
potential uses. For example, it can serve as a frequency standard
for external use, a frequency synthesizer, or could be used to
generate one or more audio tones under program control.

$

• Periodic Interrupt Selection
The periodic interrupt allows the IRQ pin to be triggered
from once every 500 ms to once every 30.517 J.l.S. The periodic
interrupt is separate from the alarm interrupt which may be
output from once-per-second to once-per-day.
Table 4 shows that the periodic interrupt rate is selected
with the same Register A bits which select the square-wave
frequency. Changing one also changes the other. But each
function may be separately enabled so that a program could
switch between the two features or use both. The SQW pin
is enabled by the SQWE bit. Similarly the periodic interrupt is
enabled by the PIE bit in Register B.
Periodic interrupt is usable by practically all real-time systems. It can be used to scan for all forms of input from contact
closures to serial receive bits or tyes. It can be used in multiplexing displays or with software counters to measure inputs,
create output intervals, or await the next needed software function.

HITACHI

573

HD146818:------------------------------------------_________________
Table 4 Periodic Interrupt Rate and Square Wave Output Frequency
4.194304 or 1.048576 MHz
Time Base

Rate Select
Control Register 1

•

32.768 kHz
Time Base

RS2

RS1

RSO

Periodic
Interrupt Rate
tpi

saw Output

RS3

Frequency

Periodic
I nterrupt Rate
tpi

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0

0

0

None

None

None

None

0

0

1

30.517 J,lS

32.768 kHz

3.90625 ms

256 Hz

0

1

0

61.035 J,lS

16.384 kHz

7.8125 ms

128 Hz

0

1

1

122.070 J,lS

8.192 kHz

122.070 J,lS

8.192 kHz

1

0

0

244.141 J,lS

4.096 kHz

244.141 J,lS

4.096 kHz

1

0

1

488.281 J,lS

2.048 kHz

488.281 J,lS

2.048 kHz

1

1

0

976.562 J,lS

1.024 kHz

976.562 J,lS

1.024 kHz

1

1

1

1.953125 ms

512 Hz

1.953125 ms

512 Hz

0

0

0

3.90625 ms

256 Hz

3.90625 ms

256 Hz

0

0

1

7.8125 ms

128 Hz

7.8125 ms

128 Hz

0

1

0

15.625 ms

64 Hz

15.625 ms

64 Hz

0

1

1

31.25 ms

32 Hz

31.25 ms

32 Hz

1

0

0

62.5 ms

16 Hz

62.5 ms

16 Hz

1

0

1

125 ms

8 Hz

125 ms

8 Hz

1

1

0

250 ms

4 Hz

250ms

4 Hz

1

1

1

500 ms

2 Hz

500 ms

2 Hz

Calendar, Time of day
& Status after Update

Examples

If 29th 23:59:59 in all the months is initialized, update to 1st in the next month is
executed. (Jan. - Dec. However except for
Feb. 29th in leap year)

Mar. 29th
.... Apr. 1st

If 30th 23: 59 :59 in Apr., June, Sept., and
Nov. is initialized, update to 31st in each
month is executed.

Apr. 30th
.... Apr.31st

Procedure of time initialization

(l) Set the SET bit of control register B. (SET = "1")
(2) Set "1" into all the DVO, 1, 2 bits of control register A.
(DVO = DVl = DV2 = "1")
(3) Set the time and calendar to each RAM.
(4) Set the frequency in use into DVO, 1 and DV2.
(5) Reset the SET bit. (SET ="0")

lsoom,-'s", r~~
I

T,m" ... ",;,.
[SET bIt 1 .... 0)

II

~

244"si-248J1s 14MHz. lMHz)
1244",s + 1984/01' 138kHz))

Figure 15 Time Initialization and the First Update
Restriction on Time-of-day and Calendar Initialization
There is a case in HD146818 (RTC) that update is not exe-

cuted correctly if time of day and calendar shown below are
initiaiized. Therefore, initialize the RTC without using time of

574

Frequency

day shown below.

I nitialization of the Time and the Start Sequence

The first update of the time occurs about 500ms later after
the SET bit of control register B is reset. So keep followings in
mind when initializing and adjusting the time.

U'P.B"
,,,
...,"A' .

saW Output

If Feb. 28th 23:59:59 (not in leap year) is
Feb. 28th, 1983
initialized, update to Feb. 29th is executed. .... Feb. 29th,1983
If Feb. 28th 23:59: 58 (in leap year) is initialized, update to Mar. lst is executed.

•

Feb. 28th, 1984
....Mar.1st,1984

UPDATE CYCLE

The HD146818 executes an update cycle once-per-second,
assuming one of the prope{ time bases is in place, the divider
is not clear, and the SET bit in Register B is clear. The SET bit
in the "1" state permits the program to initialize the time and
calendar bytes by stopping an existing update and preventing
a new one from occurring.
The primary function of the update cycle is to increment
the seconds byte, check for overflow, increment the minutes
byte when appropriate and so forth through to the year of
the century byte. The update cycle also compares each alarm
byte with the corresponding time byte and issues an alarm
if a match or if a "don't care" code (llXXXXXX) is present
in all three positions.
With a 4.194304 MHz or 1.048576 MHz time base the up-

~HITACHI

---------------------------------------------------------------HD146818
. date cycle takes 248 JlS while a 32.768 kHz time base update
'cycle takes 1984 JlS. During the update cycle, the time, calendaY, and alarm bytes are not accessable by the processor
program. The HD146818 protects the program from reading
transitional data. This protection is provided by switching
the time, calendar, and alarm portion of the RAM off the
microprocessor bus during the entire update cycle. If the
processor reads these RAM locations before the update is
complete the output will be undefined. The update in progress
(VIP) status bit is set during the interval.
A program which randomly accesses the time and date information finds data unavailable statistically once every 4032
attempts. Three methods of accommodating nonavailability
during update are usable by the program. In discussing the
three methods it is assumed that at random points user programs are able to call a subroutine to obtain the time of day.
The first method of avoiding the update cycle uses the
update-ended interrupt. If enabled, an interrupt occurs after
every update cycle which indicates that over 999 ms are available to read valid time and date information. During this time
a display could be updated or the information could be transfered to continuously available RAM. Before leaving the interrupt service routine, the IRQF bit in Register C should be
cleared.
The second method uses the update-in-progress bit (VIP)
in Register A to determine if the update cycle is in progress
or not. The VIP bit will pulse once-per-second. Statistically,
the UIP bit will indicate that time and date information is
unavailable once every 2032 attempts. After the VIP bit goes
"I", the update cycle begins 244 JlS later. Therefore, if a "0"
is read on the VIP bit, the user has at least 244 JlS before the
time/calendar data will be changed. If a "1" is read in the
VIP bit, the time/c~lendar data may not be valid. The user
should avoid interrupt service routines that would cause the

time needed to read valid time/calendar data to exceed 244 JlS .
The third method uses a periodic interrupt to determine if
an update cycle is in progress. The UIP bit in Register A is set
., I" between the setting of the PF bit in Register C (see Figure
16) Periodic interrupts that occur at a rate of greater than
tBUC + tuc allow valid time and date information to be read
at each occurrence of the periodic interrupt. The reads should
be completed within (tPI 7 2) + tBUC to insure that data is
not read during the update cycle.
•

POWER-DOWN CONSIDERATIONS

In most systems. the HD 146818 must continue to keep
time when system power is removed. In such systems. a conversion from system power to an alternate power supply,
usually a battery, must be made. During the transition from
system to battery power, the designer of a battery backed-up
RTC system must protect data integrity, minimize power
consumption, and ensure hardware reliability according to
the specification described in the section regarding Battery
Backed-up operation.
The chip enable (CE) pin controls all bus inputs (R/W, OS,
AS. ADo ~ AD7)' CEo when negated, disallows any unintended
modification of the RTC data by the bus. CE also reduces
power consumption by reducing the number of transitions
seen internally.
Power consumption may be further reduced by removing
resistive and capacitive loads from the clock out (CKOUT)
pin and the squarewave (SQW) pin.
During and after the power source conversion, the V IN
maximum specification must never be exceeded. Failure to
meet the V IN maximum specification can cause a virtual
SCR to appear which may result in excessive current drain
and destruction of the part.

~i-~-------------

UIP bit in
Register A

tBUC~· hrrm""",--:C_

UF bit in
Register C

f---t PI
---.Jnmm
Wlllll..-___________--'nrnm

I-

PF bit in C
Register

tpi
tuc
tsuc

7

tPI------lOolal

2---1
rtP172--j

nmm

WLW.IL-_ _ _ __

= Periodic Interrupt Time Interval (500 ms, 250 ms, 125 ms, 62.5 ms, etc.)
= Update Cycle Time (2481's or 19841'5)
= Delay Time Before Update Cycle (2441's)
Figure 16

Update-Ended and Periodic Interrupt Relationship

$

HITACHI

575

HD146818-----------------------------------------------------------• SIGNAL DESCRIPTIONS
The block diagram in Figure 10, shows the pin connection
with the major internal functions of the HD146818 Real-Time
Clock plus RAM. The following paragraphs describe the function of each pin.

The on-chip oscillator is designed for a parallel resonant
crystal at 4.194304 MHz or 1.048576 MHz or 32.768 kHz frequencies. The crystal connections are shown in Figure 11.

• Vee, Vss

DC power is provided to the part on these two pins, Vee
being the most positive voltage. The minimum and maximum
voltages are listed in the Electrical Characteristics tables.

• CKOUT - Clock Out (Output)
The CKOUT pin is an output at the time-base frequency
divided by 1 or 4. A major use for CKOUT is as the input clock
to the microprocessor; thereby saving the cost of a second
crystal. The frequency of CKOUT depends upon the time-base
frequency and the state of the CKFS pin as shown in Table 5.

• OSC I , OSC 2 - Time Base (I nputs)
The time base for the time functions may be an external
signal or the crystal oscillator. External square waves at
4.194304 MHz, 1.048576 MHz, or 32.768 kHz may be connected to OSC I as shown in Figure 17. The time-base frequency
to be used is chosen in Register A.

• CKFS - Clock Out Frequency Select (Input)
The CKOUT pin is an output at the time-base frequency
divided by 1 or 4. CKFS tied to Vee causes CKOUT to be the
same frequency as the time base at the OSC I pin. When CKFS
is at V ss' CKOUT is the OSC I .time-base frequency divided
by four. Table 5 summarizes the effect of CKFS.

Lv

~


HD146818P (X type ..... Marked as follows)

~XorRX

e

rl,
L_J

2B2

HD146818P
JAPAN

< Restriction on usage>
Please set "0" to DSE bit (Daylight Saving Enable bit) on initializing the control register B.
DSE = "1" is prohibited.

RESTRICTION ON HD146818 USAGE (2)
Access to HD146818 needs to be performed under following conditions.
(i) Chip-enable (CE) must be asserted to active "Low" level only when MPU performs read/write operation from/into
internal RAM (Time and Calendar RAM, Control register, User RAM).
(ii) User RAM and control register must be accessed in less than 1/4 frequency shown below.
(Example: After one access, non·access cycles more than three cycles are necessary to be inserted.)

[Example

11

Address

Non-Access

_

Access to HD146818

[Example 21

Access to HD146818 (Two Continuous Accesses)

As shown in the above {example 21. when HD146818 is accessed continuously, continuous access must
not be executed over fifty times.

(iii) The application that User RAM is used for program area should be avoided. (Inhibit continuous access.)
(iv) Minimize the noise by inserting noise bypass condenser between power supply and gro.und pin (Vcc-V ss).
(Insert noise bypass condenser as near HD146818 as possible.)

580

$

HITACHI

HD6318,HD63A18----RTC (Real Time Clock Plus RAM)
-ADVANCE INFORMATIONThe HD6318 is a HMCS6800 peripheral CMOS device which
combines three unique features: a complete time-of-day clock
with alarm and one hundred calendar, a programmable periodic
interrupt and square-wave generator, and 50 bytes of Lowpower static RAM.
This device includes HD6801, HD6301 multiplexed bus
interface circuit and 8085's multiplexed bus interface as well,
so it can be directly connected to HD6801 , HD6301 and 8085.
The Real-Time Clock plus RAM has two distinct uses. First,
it is designed as battery powered CMOS part including all the
common battery backed-up functions such as RAM, time, and
calendar. Secondly, the HD6318 may be used with a CMOS
microprocessor to relieve the software of timekeeping workload and to extend the available RAM of an MPU such as the
HD6301.
•
•
•
•

•
•
•
•
•

•

•
•

•
•
•
•

FEATURES
Revised product of HD146818 in both Function and Characteristics
Compatible with HD146818 and Motorola MC146818
Time-of-Day Clock and Calendar
• Counts Seconds, Minutes, and Hours of the Day
• Counts Days of Week, Date, Month, and Year
Binary or BCD Representation of Time, Calendar, and Alarm
12- or 24 Hour Clock with AM and PM in 12-Hour Mode
Automatic End of Month Recognition
Automatic Leap Year Compensation
Interfaced with Software as 64 RAM Locations
• 14 Bytes of Clock and Control Register
• 50 Bytes of General Purpose RAM
Three Interrupt are Separately Software Maskable and
Testable
• Time-of-Day Alarm, Once-par-Second to Once-per-Day
• Periodic Rates from 30.51ls to 500 ms
• End-of-Clock Update Cycle
Programmable Square-Wave Output Signal
Three Time Base Input Options
• 4.194304 MHz
• 1.048576 MHz
• 32.768 kHz
Clock Output May be used as Microprocessor Clock Input
• At Time Base Frequency";- 4 or ..;- 1
Multiplexed Bus Interface Circuit of HD6801, HD6301 and
8085
Low-Power, High-Speed, High-Density CMOS
Battery Backed-up Operation

HD6318P, HD63A18P

(DP-24)

•

PIN ARRANGEMENT

(Top View)
•

TYPE OF PRODUCTS

~HITACHI

Type No.
HD6318
HD63A18

Bus Timing
1.0MHz
1.5 MHz

581

HD6318,HD63A18-------------------------------------------------------•

BLOCK DIAGRAM

CKOUT
CKFS

OSC.
OSC l

saw

ps

Bus
Interface

Clock/
Calendar
Update

Clock, Alarm,
Calendar RAM
(10 Bytes)

BCD/
Binary
Increment
User RAM
(50 Bytes)

582

~HITACHI

16-BIT MULTI-CHIP
MICROCOMPUTERS

HD68000,HD68000Y
HD68000Z

M PU (Micro

Processing Unit)

Advances in semiconductor technology have provided the
capability to place on a single silicon chip a microprocessor at
least an order of magnitude higher in performance and circuit
complexity than has been previously available. The H068000
is one of such VLSI microprocessors. It combines rate-of-the-art
technology and advanced circuit design techniques with computer sciences to achieve an architecturally advanced 16-bit
microprocessor.
The resources available to the H068000 user consist of the
following.
As shown in the programming model, the HD68000 offers
seventeen 32-bit registers in addition to the 32-bit program
counter and a 16-bit status register. The first eight registers
(00-D7) are used as data registers for byte (8-bit), word
(16-bit), and long word (32-bit) data operations. The second set
of seven registers (AO-A6) and the system stack pointer may be
used as software stack pointers and base address registers. In
addition, these registers may be used for word and long word
address operations. All 17 registers may be used as index
registers.

•

FEATURES

•
•
•
•
•
•
•

32·Bit Data and Address Registers
16 Megabyte Direct Addressing Range
56 Powerful Instruction Types
Operations of Five Main Data Types
Memory Mapped I/O
14 Addressing Modes
Compatible with MC6S000l4/l6/lS/l 10/l 12, MC6S000R4/
R6/RS/Rl0/R12 and MC6S000Z4/Z6/ZS/Zl0/Zl2

• PROGRAMMING MODEL

HD6S000·4, HD68000·6, HD6S000·S,
HD6S000·l0, HD68000·12

(DC·64)
HD68000Y4, HD68000Y6,
HD68000Y8, HD68000Y10,
HD68000Y12

( PGA-6S)

"Y" stands for Pin Grid
Array Package.

HD68000Z4, HD68000Z6,
HD68000Z8, HD68000Z1 0,
HD68000Z12

,oo

r31~__________~1~6r15~__~8~7~____

01

02
03 Eight
Data
04 Registers
05
06

L-------------~------~----~o

~

~~3. .t=:·

"!:,::,"

EL__
' _________

07

-"

L..._ _ _ _ _ _ _ _ _

15

87

ISystem 8Yte:

0
User Byte

I

(CG·6S)

"Z" stands for leadless
Chip Carrier Package.

As for package used for HD6S000Z, Leadless Chip Carrier
Package is preliminary.

Status
Register

~HITACHI

585

H068000, Ho68000Y, Ho6 8 0 0 0 Z - - - - - - - - - - - - - - - - - - - - - - - • PIN ARRANGEMENT

D ••

0 ..
0"
0"
D ••
0 ..
VSS
A"
A2I

HD68000

Vee
A,.
A ••
A ..

(Bottom View)

AI?
A"

BERR

A ..

Pin No.

A ••

1
2

A"
FC,

3
4

A ..
A ••

FC.
Fe.

5
6

A,

7

A,
A,

8

A,

9
10

A.

"

11
12

(Top View)

13
14

Pin No.
18
19

Function

Pin No.

Function

Pin No.

Function

A.
N/C

35
36

D.

52
53

20
21

37

56
57

A"

58

25

A2I

42

26

Vee
Vss
RES
VPA
IPl,
IPl.
FC ,

A"
AIS
A ••
Vee
Vss

24

A ••
A,.
AI7
A,.
A,.

AS
lOS
BG

0 ,•
0 ..
D.

62

0,

N/C
A,
A,

63

66

50

A.
A,.

D.
UDS
RIW
IPl.

67

A.,

51

All

66

0"

22
23

43

0"

45

29

D ••

46

30

D.
0,
0,
D.
0,

47

31

32

17

A,

34

33

44

48
49

54
55

59
60
61

64
65

D.

TYPE OF PRODUCTS
Package

Clock Frequency (MHz)

HD68000-4

4.0

HD68000-6

6.0

HD68000-8

DC-64

B.O

HD68000-10

10.0

HD6BOOO-12

12.5

HD68000Y4

4.0
6.0

HD6BOOOY6
HD68000YB

PGA-68

B.O

HD68000Y10

10.0

HD68000Y12

12.5
4.0

HD68000Z4

6.0

HD68000Z6
HD68000Z8

586

41

A"
DIS

A.
Ao

Type No.

(Top View)

38
39
40

28

27

16

15

•

Function
N/C
OTACK
BGACK
BR
ClK
HALT
VMA
E
BERR
N/C
FC,
FC.
A,
A,

CG-68

8.0

HD68000Z10

10.0

HD68000Z12

12.5

~HITACHI

- - - - - - - - - - - - - - - - - - - - - - - - H D68000,HD68000Y,H o68000Z
•

ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Supply Voltage
Input Voltage

Vee
,
V in

Operating Temperature Range
Storage Temperature

Value

,

Unit

-0.3 -+7.0

V

-0.3 - +7.0

V

T opr

0-+70

Tstg

-55 - +150

°c
°c

• With respect to Vss (SYSTEM GND)
(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions.
If these conditions are exceeded. it could affect reliability of LSI.

•

RECOMMENDED OPERATING CONDITIONS
Item

Symbol

min

typ

max

Unit

Vee
,
V IH
V 1L *

4.75

5.0

5.25

V

2.0

-

-0.3

-

Vee
0.8

V

0

25

70

°c

,

Supply Voltage
Input Voltage
Operating Temperature

T opr

V

• With respect to Vss (SYSTEM GND)

•

ELECTRICAL CHARACTERISTICS

•

DC CHARACTERISTICS (Vee

=5V ±5%, Vss = OV, Ta = 0 '" +70°C, Fig. 1,2,3, unless otherwise noted.)
Item

Symbol

min

max

Unit

Input "High" Voltage

V 1H

2.0

V

Input "low" Voltage

V 1L

Vss-0.3

Vee
0.8

-

2.5

-

20

-

20

2.4

-

V ee -O·75

-

Input leakage Current

BERR, BGACK, BR, DTACK,
iPIo -IPLz , VPA, ClK

Test Condition

@5.25V

lin

HAL T, RES
Three·State (Off Statel
Input Current

Output "High" Voltage

AS, A,-A z3 , 0 0 -0'5,
FC o - FC z • lOS, R/W, UDS,
VMA
AS, A, -A 23 , BG, Do -0'5,
FC o -FC z , lOS, R/W, UDS,
VMA,E

ITS'

@2.4V/0.4V

V OH

IOH

= -400J.(A

E'
HALT
Output "low" Voltage

IOL

= 1.6mA
= 3.2mA
= 5.3mA

IOL

= 5.3mA

IOL

A, -A z3 , BG, FC o -FC z

VOL

RES
AS, Do -0'5, lOS, R/W, E,
UDS, VMA
Power Dissipation

PD

Capacitance (Package Type Dependentl

Cin

IOL

V in = OV, Ta
f = 1 MHz

= 25°C,

p.A

JJA

V

-

0.5

-

0.5

-

0.5

* With external pull up resistor of 1.1 kn.
** 1.75Wat f = 12.5 MHz

V

V

0.5

1.5*'

W

20.0

pF

+5 V

Test
POint

152074@
or
Equivalent

Figure 1 RES Test Load

Figure 2 HALT Test Load

C L = 130 pF (Includes all Parasiticsl
RL = 6.0 kn for AS, A, -A'3' fiG, D. -D,s, E,
FC.-FC"LDS,R/VV,ODS,~

*R = 1.22 kn for A, -A 23

,

BG,

FC. -FC,

Figu re 3 Test Loads

•

HITACHI

587

H068000,H068000Y,H068000Z----------------------• AC CHARACTERISTICS (Vee

=5.0V ±5%, Vss =OV, Ta =0 -

o

+70 C, unless otherwise noted.)
4MHz
Version

Number

Symbol

Item

Test
Condition

6MHz
Version

~~~~4

HD68000Z4

min

HD68000Z6

max min
4.0 2.0

8MHz

10MHz
Version

~~~8

~~~g~~o

HD68000Z,O

12.5MHz
Version
HD68000·12
HD68000V12
HD68000Z'2

min

max

min

max

2.0

10.0 4.0

Version

~~;~~6
max

HD68000Z8

min
2.0

max
8.0

Unit

Frequency of Operation

f

2.0

12.5

MHz

CD

Clock Period

tcyc

250 500

167 500

125 500

100 500

80

250

ns

@

Clock Width "Low"

tCL

115 250

75

250

55

250

45

250

35

125

ns

@
@

Clock Width "High"

tCH

115 250

75

250

55

250

45

250

35

125

ns

Clock Fall Time

tCf

-

10

ns

®
®

Clock Rise Time

tCr

-

10

Clock "Low" to Address

tCLAV

-

Clock "High" to FC Valid

tCHFCV

@

CD

®
@'
@)

@2
@2
@1

@2
@2
@2
@2

Clock "High" to Address!Data High
Impeda~ce

(Maximum)

Clock "High" to Address/FC Invalid (Minimum)

tCHAZx

--

tCHAZn

0

Clock "High" to AS. DS"Low"(Maximum) tCHSLx
Clock "High" to AS. OS" Low "(Minimum) tCHSLn

10

10

5

10

10

10

5

ns

90

80

70

60

55

ns

90

80

80

60

55

ns

--

120

100
0

80
0

70

70
0

60

60

ns
ns

0
55

55

ns

0

0

0

0

0

ns

0

ns

Address to AS. OS (Read) "Low" AS Write

tAVSL

55

35

30

20

FC Valid to AS. OS (Read)" Low" 'AS Write

tFCVSL

80

70

60

50 I

Clock "Low" to AS. OS "High"

tCLSH

-

AS. OS "High" to Address/FC Invalid

tSHAZ

60

40

30

20

10

ns

AS. OS Width "Low" (Read)/AS Write

tSL

535

337

240

195

160

ns

285

170

115

95

80

ns

285

180

150

105

65

OS Width "Low" (Write)

-

AS. OS Width "High"

tSH

@

Clock "High" to AS. OS High Impedance

tCHSZ

@2

AS. OS "High" to R/W "High"

tSHRH

@'. Clock "High" to R/W "High" (Maximum)
@
Clock "High" to R/W "High" (Minimum)

@'
@
@2

10

80

-

6.0

60

tCHRL

AS "Low" to R/W Valid

tASRV

Address Valid to R/W "Low"

tAVRL

100

0

0
90

Fig.4
-Fig. 7

-

20

20

-

10

0
20

0

20

-

ns
ns

60

ns
ns

60

-

ns

ns
60

60

70

80

-

20

0

50

70

70

80

ns

55

80
40

50
90

tCHRHn

70

80

120

tCHRHx

Clock "High" to R/W "Low"

@2 FC Valid to R/W "Low"

90

40

60

ns

I 20

ns

45

25

20

0

0

ns

tFCVRL

80

70

60

50

30

ns

140

80

50

30

@2

R/W "Low" to OS "Low" (Write)

tRLSL

200

@
@2

Clock "Low" to Data Out Valid

tCLDO

-

OS "High" to Data Out Invalid

tSHDO

60

@2

Data Out Valid to OS "Low" (Write)

tDOSL

55

@5

Data In to Clock "Low" (Setup Time)

tDICL

30

@2
<3

AS. OS "High" to DTACK "High"

tSHDAH

0

490

0

325

0

OS "High" to Data Invalid (Hold Time)

tSHDI

0

--

0

-

0

0

0

~

AS. OS "High" to BERR "High"

tSHBEH

0

-

0

0

0

0

@)2,5 DTACK "Low" to Data In (Setup Time)
@
HALT and RES Input Transition Time
@
Clock "High" to BG "Low"

tDALDI

--

180

-

120

tRHrf

0

200

0

200

0

200

tCHGL

-

90

-

80

-

70

<8

Clock "High" to BG "High"

tCHGH

--

90

-

80

-

70

@
@

BR "Low" to BG "Low"

tBRLGL

1.5

3.5

1.5

3.5

1.5

3.5

1.5

3.5

1.5

BR "High" to BG "High"

tBRHGH

1.5

3.5

1.5

3.5

1.5

3.5

1.5

3.5

1.5

3.5 Clk.Per.

®

BGACK "Low" to BG "High"

tGALGH

1.5

3.0

1.5

3.0

1.5

3.0

1.5

3.0

1.5

3.0 Clk.Per.

@

BG "Low" to Bus High Impedance
(With AS "High")

tGLZ

-

90
-

-

120

55

40

30

20

15

35

30

20

15

25

15

10

10

-

100

245

0

80

190

0

65

90

-

ns

55

70

80

0

-

-

200

0

ns
ns
ns
ns

I

150

ns
ns
ns

50

ns

200

ns

60

50

ns

60

50

ns

70

-

3.5 Clk.Per.

60

ns

tGH

1.5

._-

1.5

-

1.5

-

1.5

-

1.5

-

Clk.Per.

tBGL

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

Clk.Per.

tASI

30

-

25

-

20

-

20

-

20

-

ns

BERR "Low" to DTACK "Low" (Note 3)

tBELDAL

30

25

20

-

20

-

20

-

ns

Data Hold from Clock "High"

tCHDO

0

-

0

-

0

-

0

-

0

-

ns

R/W to Data Bus Impedance Change

tRLDO

55

-

35

-

30

-

20

-

10

-

ns

FiA[f /RES Pulse Width (Note 4)

tHRPW

10

-

10

-

10

-

10

-

10

-

Clk.Per.

~

BG Width "High"

@
@5

BGACK Width "Low"
Asynchronous Input Setup Time

@
~
@
~

(to be continued)

588

~HITACHI

HD68000,HD68000Y,HD68000Z-----------------------------------------------

I-->

--1-- - -

Even Byte Write - -

---I

Figure 17 Word and Byte Write Cycle Timing Diagram

~HITACHI

601

H068000,H068000Y,H068000Z----------------------BUS MASTER
1)
2)
3)
4)
5)

SLAVE

Address Device
Set R/W to Read
Place Function Code on FC o - FC,
Place Address on Al - A'3
Assert Address Strobe (AS)
Assert Upper Data Strobe (UDS) or
Lower Data Strobe (LOS)

Input Data
1) Decode Address
2) Place Data on Do -0 7 or D. - 015
3) Assert Data Transfer Acknowledge
(DTACK)

i

Acquire Data
1) Latch Data
2) Negate lJDS or LOS
3) Start Data Modification

Terminate Cycle
1) Remove Data from Do - 0 7 or D. - DIS
2) Negate r>TACl<

j
Start Output Transfer
1) Set R/Vii to Write
2) Place Data on Do - 0 7 or D. - 015
3) Assert Upper Data Strobe (UDS) or Lower
Data Strobe (LOS)

Input Data
1) Strobe Data on Do '-- 0 7 or D. - DIS
2) Assert Data Transfer Acknowledge
(DTACK)

Terminate Output Transfer
1)
2)
3)
4)

Negate ODS or LOS
Negate AS
Remove Data from Do -0 7 or D. -015
Set R/Vii to Read
Terminate Cycle
1) Negate DTACK

I
Start Next Cycle

Figure 18 Read-Modify-Write Cycle Flow Chart

SO

DDS or

S1 S2 S3 54 S5 S6 S7 58 S9 S10 S11S12S13514515S16517518519

I

\
\

LD5

I

R/W

FC o -FC,

I

\

DTACK
Oo - 0 7 or D. -DIS

=x

)

<

j+-- - - - - - - - - - -

Indivisible Cycle - -

\

•

HITACHI

>-x:::

<
- - -

- -

Figure 19 Read-Modify-Write Cycle Timing Diagram

602

r-rr-

\
\

-

-

--1

-----------------------H068000,H068000Y,H068000Z
PROCESSOR

REQUESTING DEVICE

Requesting the Bus

Request the Bus
1) Assert Bus Request (BR)

I
Grant Bus Arbitration
1) Assert Bus Grant (BG)

~I---------------,

+

Acknowledge Bus Mastership
1) External arbitration determines next bus
master
2) Next bus master waits for current cycle to
complete
3) Next bus master asserts Bus Grant
Acknowledge (BGACK) to become new
master
4) Bus master negates BR

I
Terminate Arbitration
1) Negate BG(and wait for BGACK to be
negated)

Operate as Bus Master
1) Perform Data Transfers (Read and Write
cycles) according to the same rules the processor uses.
Release Bus Mastership
1) Negate BGACK

Re-Arbitrate or Resume Processor
Operation

Figure 20 Bus Arbitration Cycle Flow Chart

External devices capable of becoming bus masters request
the bus by asserting the bus request (BR) signal. This is a wire
ORed signal (although it need not be constructed from open
collector devices) that indicates to the processor that some
external device requires control of the external bus. The processor is effectively at a lower bus priority level that the external device and will relinquish the bus after it has completed
the last bus cycle it has started.
When no acknowledge is received before the bus request
signal goes inactive, the processor will continue processing
when it detects that the bus request is inactive. This allows
ordinary processing to continue if the arbitration circuitry
responded to noise inadvertently.
Receiving the Bus Grant

The processor asserts bus grant (BG) as soon as possible.
Normally this is immediately after internal synchronization.
The only exception to this occurs when the processor has made
an internal decision to execute the next bus cycle but has not
progressed far enough into the cycle to have asserted the address
strobe (AS) signal. In this case, bus grant will not be asserted
until one clock after address strobe is asserted to indicate to
external devices that a bus cycle is being executed.
The bus grant signal may be routed through a daisy-chained
network or through a specific priority-encoded network. The
processor is not affected by the external method of arbitration
as long as the protocol is obeyed.
Acknowledgement of Mastership

Upon receiving a bus grant, the requesting device waits
until address strobe, data transfer acknowledge, and bus grant
acknowledge are negated before issuing its own BGACK. The
negation of the address strobe indicates that the previous
master has completed its cycle, the negation of bus grant
acknowledge indicates that the previous master has released
the bus. (While address strobe is asserted no device is allowed
to "break into" a cycle.) The negation of data transfer acknowledge indicates the previous slave has terminated its connection
to the previous master. Note that in some applications data

ClK

AS
lDS/UDS
R/IN
DTACK
Do -DIS
FC o -FC.
BR

\

BG

BG'AC'K
Processor - -

,
+ --

I -----------,~==~~----_I
I
------------_\====~--_I
I
,'-------

DMA Device

Figure 21

-+- - - --

Processor

- -

-

--t-- - -

DMA Device - - - -

Bus Arbitration Cycle Timing Diagram

~HITACHI

603

H068000,H068000Y,H068000Z----------------------transfer acknowledge might not enter into this function. General purpose devices would then be connected such that they
were only dependent on address strobe. When bus grant acknowledge is issued the device is bus master until it negates
bus grant acknowledge. Bus grant acknowledge should not be
negated until after the bus cycle(s) is (are) completed. Bus
mastership is terminated at the negation of bus grant acknowledge.
The bus request from the granted device should be dropped after bus grant acknowledge is asserted. If a bus request
is still pending, another bus grant will be asserted within a few
clocks of the negation of bus grant. Refer to Bus Arbitration
Control section. Note that the processor does not perform
any external bus cycles before it re-asserts bus grant.
•

BUS ARBITRATION CONTROL

The bus arbitration control unit in the HD68000 is implemented with a finite state machine. A state diagram of this
machine is shown in Figure 22. All asynchronous signals to the
HD68000 are synchronized before being used internally. This
synchronization is accomplished in a maximum of one cycle
of the system clock, assuming that the asynchronous input
setup time (#47) has been met (see Figure 23). The input
signal is sampled on the falling edge of the clock and is valid
internally after the next falling edge.
As shown in Figure 22, input signals labeled R and A are
internally synchronized on the bus request and bus grant

acknowledge pins respectively. The bus grant output is lebeled
G and the internal three-state control signal T. If T is true, the
address, data, function code line, and control buses are placed
in a high-impedance state when AS is negated. All signals are
shown in positive logic (active high) regardless of their true
active voltage level.
State changes (valid outputs) occur on the next rising edge
after the internal signal is valid.
A timing diagram of the bus arbitration sequence during a
processor bus cycle is shown in Figure 24. The bus arbitration
sequence while the bus is inactive (i.e., executing internal
operations such as a multiply instruction) is shown in Figure 25.
If a bus request is made at a time when the MPU has already
begun a bus cycle but AS has not been asserted {bus state SO),
BG will not be asserted on the next rising edge. Instead, BG will
be delayed until the second rising edge following it's internal
assertion. This sequence is shown in Figure 26.
•

BUS ERROR AND HALT OPERATION

In a bus architecture that requires a handshake from an external device, the possibility exists that the handshake might not
occur. Since different systems will require a different maximum
response time, a bus error input is provided. External circuitry
must be used to determine the duration between address strobe
and data transfer acknowledge before issuing a bus error signal.
When a bus error signal is received, the processor has two
options initiate a bus error exception sequence or try running
the bus cycle again.

RA
Internal Signal v a l i d - - - - - - - - .
External Signal samPled.

1
•

ClK

BR (External) - - - - - _ _ .

BR (Internal)--------------.~

R
A
G
T
X

= Bus Request Internal
= Bus Grant Acknowledge Internal
= Bus Grant
= Three-State Control to Bus Control
= Don't Care

Figure 23 Timing Relationship of External Asynchronous
Inputs to Internal Signals

logic* *

* State machine will not change state if bus is in SO. Refer to BUS
ARBITRATION CONTROL for additional information.
** The address bus will be placed in the high impedance state if T is
asserted and "AS is negated.

Figure 22

604

State Diagram of HD6aOOO Bus
Arbitration Unit

@HITACHI

-----------------------HD68000,HD68000Y,HD68000Z
Bus released from three state and
Processor starts next bus C Y C l e n
BGACK negated internal
BGACK sampled
BGACi< negated

Bus three stated - - - - - - - - ,
BG
BR
BR
BR

asserted~

valid internal ~
sampled
asserted

===:-l

+

ll

+

ClK
SO S1 S2 S3 S4 S5 S6 S7
BR----"""\

SO S1 S2 S3 S4 S5 S6 S7 SO S1
/

BG====~~~~~~~~~=_~~\;:::;~~-~/r----------------------------\~____________~/

BGACK
A, -A

l3

~

==~;:===:;r)====~---=~{;:===:;>-e
,~--------I'-------------------~~--------;-----

UDS - - - - - - - , . ,

I'

lOS

f'

r---"\.;----r-----'\;-----

==::x==~=============:)\

x::

o

FC - FC

l

Rm

\

~\c:=====/~-------------------__----___\~=<====:J;---.1"
_I
('--_ _~)___

Do
- DIS _______________ ( )
DTACK
Processor

..

Alternate Bus Master

Processor

II

Figure 24 Bus Arbitration During Processor Bus Cycle

Bus released from three state and processor starts next bus c Y c l e - - - - - - - - - - - - - - - - .
BGACK negated - - - - - - - - - - - - - - - - - - - - - - - - - - ,
BG asserted and bus three s t a t e d - - - - - - - - - - .

ClK
SO S 1 S2 S3 S4 S5 S6 S7
BR

SO S1 S2 S3 S4
\

/

BG--------------------~======\~------~

I~------------------

BGACK-------------------------------=====,\-------J

,
A -A l3

/

'------~

~~~==========~::::::::::::~--::::::::::=--------:~(;;;::::
_ _ _ _ _/

AS~

~

UDS~

Ir----------~

LDS~
FC o -FCl

_______________

~

~

I

J ________________y)-------------~_ _ __

R/W----------------------------~----------------------~
DTACK
Do-DIS

\

I

'----

------~~~(::==:J)~~~~~--------_:~~~~~---------:~~::
.1...
Processor

_,..

Bus Inactive

Alternate Bus Master

_,...

Processor

Figure 25 Bus Arbitration with Bus Inactive

~HITACHI

605

HD68000,HD68000Y,HD68000Z------------------------------------------------

ITl

BR asserted

Bus released from three state and
Processor starts next bus cycle
Bus three stated------...,~BGACK negated internal
BGACK sampled~
BGACK negated

BR sampled

I

t

50 51 52 53 54 55 56 57

BR

"\

I

\

BG

I

\

BGACK
A,-A 23

<

AS
UD5
LD5
FC o -FC,

50 51 52 53 S4 55 56 57 50 51

I
)

rf '

\
\
\

)

I

\

DTACK
Do -D,s
>II

Processor

<

>
,I"

C

<
I

\

R/Vi

r-r-r--

~
~

f'

==><

K

(
~

r--

\
Alternate Bus Master

<

"I"

Processor

>--..

Figure 26 Bus Arbitration During Processor Bus Cycle Special Case

Exception Sequence
When the bus error signal is asserted, the current bus cycle
is terminated. If BERR is asserted before the falling edge of
S4, AS will be negated in S7 in either a read or write cycle.
As long as BERR remains asserted, the data and address buses
will be in the high-impedance state. When BERR is negated,
the processor will begin stacking for exception processing.
Figure 27 is a timing diagram for the exception sequence.
The sequence is composed of the following elements.
(l) Stacking the program counter and status register
(2) Stacking the error information
(3) Reading the bus error vector table entry
(4) Executing the bus error handler routine
The stacking of the program counter and the status register
is the same as if an interrupt had occurred. Several additional
items are stacked when a bus error occurs. These items are used
to determine the nature of the error and correct it, if possible.
The bus error vector is vector number two located at address
$000008. The processor loads the new program counter from
this location. A software bus· error handler routine is then
executed by the processor. Refer to EXCEPTION PROCESSING for additional information.

606

Re-Running the Bus Cycle
When. during a bus cycle, the processor receives a bus error
Signal and the halt pin is being driven by an external device,
the processor enters the re-run sequence. Figure 28 is a timing
diagram for re-running the bus cycle.
The processor terminates the bus cycle, then puts the address
and data output lines in the high-impedance state. The processor
remains "halted," and will not run another bus cycle until the
halt signal is removed by external logic. Then the processor
will re-run the previous bus cycle using the same address, the
same function codes, the same data (for a write operation), and
the same controls. The bus error signal should be removed at
least one clock cycle before the halt signal is removed.
(NOTE) The processor will not re-run a read-modify-write cycle. This
restriction is made to guarantee that the entire cycle runs correctly and that the write operation of a Test-and-Set operation
is performed without ever releasing AS. If BERR and HALT
are asserted during a read-modify-write bus cycle, a bus error
operation results.

~HITACHI

-------------------------------------------------HD68000,HD68000Y,HD68000Z
ClK
AS

\~

_________________________________ _ J

lDS/UDS ---""'\\

R/W
DTACK
0

0 -0"

FC o - FC,

::~==::::~======================================~::::J
=::x:

BERR==~======================~\----------------r====

HAlT----------------------------==============~--~

1.- __Error
1~it~t!:..B~s __ _
Stacking

I+-I~iat.!!._J._.. __ Response Failure- _ --J..-.. _ _ _ Bus Error Detection- __ ....

Read -1-

--,--

Figure 27

Bus Error Timing Diagram

ClK
~

__________JI

\~

________I

~ __________~/~--------------------------~\

jr-----

\(~======.>-rx=:

:~~~~~~~~~~~~~~~~~_~::==:~:=l=C=IO=c=k=p=e=ri=o_d-_---~~;fj~-----------------------------------t-- - - - - -

Read -

-

-

--I- - - - - - - -

Figure 28

Halt - - -

- - -

+ - - - - Rerun- -

-.j

Re-Run Bus Cycle Timing Information

The processor terminates the bus cycle, then puts the address, data and function code output lines in the high-impedance
state. The processor remains "halted," and will not run another
bus cycle until the halt signal is removed by external logic. Then
the processor will re-run the previous bus cycle using the same
address, the same function codes, the same data (for a write
operation), and the same controls. The bus error signal should
be removed before the halt signal is removed.
Halt Operation with No Bus Error
The halt input signal to the HD68000 perform a Halt/Run/
Single-Step function in a similar fashion to the HMCS6800
halt function. The halt and run modes are somewhat self explanatory in that when the halt signal is constantly active the
processor "halts" (does nothing) and when the halt signal is
constantly inactive the processor "runs" (does something).
The single-step mode is derived from correctly timed transitions on the halt signal input. It forces the processor to execute
a single bus cycle by entering the "run" mode until the processor starts a bus cycle then changing to the "halt" mode.
Thus, the single-step mode allows the user to proceed through
(and therefore debug) processor operations one bus cycle at a
time.

Figure 29 details the timing required for correct single-step
operations. Some care must be exercised to avoid harmful
interactions between the bus error signal and the halt pin
when using the single cycle mode as a debugging tool. This
is also true of interactions between the halt and reset lines
since these can reset the machine.
When the processor completes a bus cycle after recognizing
that the halt signal is active, most three-state signals are put
in the high-impedance state. These include:
(1) Address lines
(2) Data lines
This is required for correct performance of the re-run bus
cycle operation.
While the processor is honoring the halt request, bus arbitration performs as usual. That is, halting has no effect on bus
arbitration. It is the bus arbitration function that removes the
control signals from the bus.
The halt function and the hardware trace capability allow
the hardware debugger to trace single bus cycles or single instructions at a time. These processor capabilities, along with
a software debugging package, give total debugging flexibility.

@HITACHI

607

H068000,H068000Y,H068000Z----------------------------------------------Double Bus Faults
When a bus error exception occurs, the processor will attempt to stack several words containing information about
the state of the machine. If a bus error exception occurs during
the stacking operation, there have been two bus errors in a row.
This is commonly referred to as a double bus fault. When a
double bus fault occurs, the processor will halt. Once a bus
error exception has occurred, any bus error exception occurring
before the execution of the next instruction constitutes a double bus fault.
Note that a bus cycle which is re-run does not constitute a
bus error exception, and does not contribute to a double bus

fault. Note also that this means that as long as the external
hardware requests it, the processor will continue to re-run
the same bus cycle.
The bus error pin also has an effect on processor operation
after the processor receives an external reset input. The processor reads the vector table after a reset to determine the address to start program execution. If a bus error occurs while
reading the vector table (or at any time before the first instruction is executed), the processor reacts as if a double bus fault
has occurred and it halts. Only an external reset will start a
halted processor.

ClK

\~__________~I

AS

lDS/UDS ----~\

R/W
DTACK
15

Do -D
o

FC HALT
-FC.

\~

__________-JI

/~------------------------~\

I~----

------~========~-------------------------=========~------

r-~:::=~(~~~~~)~============~(~~~~}-I

\

\

=::x~===~--_--'X~-----;::==========~x:::===
________________________-JI
I-- - --Read- - -Halt- - - -+-- - -Read- --~
\~

+

Figure 29 Halt Signal Timing Characteristics

+5V

RUN/SINGLE STEP

* OPEN COllECTOR
DEVICE
SINGLE
STEP
Q

K

STEP
(J '-'-"_ _...J

AS" (From Processor)
RESET

Figure 30 Simplified Single-Step Circuit

608

~HITACHI

_______________________________________________ H068000,H068000Y, H068000Z
THE RELATIONSHIP OF DTACK, BERR, AND HALT
In order to properly control termination of a bus cycle for a
-run or a bus error condition, DTACK, BERR, and HALT
lould be asserted and negated on the rising edge of the
D68000 clock. This will assure that when two signals are
serted simultaneously, the required setup time (#47) for
>th of them will be met during the same bus state.
This, or some equivalent precaution, should be designed
"ternal to the HD68000. Parameter #48 is intended to ensure
Lis operation in a totally asynchronous system, and may be
nored if the above conditions are met.
The preferred bus cycle terminations may be summarized
follows (case numbers refer to Table 4):
ormal Termination: DTACK occurs first (case I).
alt Termination:
HALT is asserted at the same time or
before DT ACK and BERR remains
negated (cases 2 and 3).
us Error Termination: HERR is asserted in lieu of, at the same
time, or before DT ACK (case 4); BERR
is negated at the same time or after
DTACK.
e-Run Termination: HALT and BERR are asserted in lieu
of, at the same time, or before DT ACK
(cases 6 and 7); HALT must be held at
least one cycle after BERR. Case 5 in-

dicates BERR may precede HALT
which allows fully asynchronous assertion.
Table 4 details the resulting bus cycle termination under
various combinations of control signal sequences. The negation of these same control signals under several conditions is
shown in Table 5 (DT ACK is assumed to be negated normally in all cases; for best results, both Dr ACK and BERR should
be negated when address strobe is negated.)
Example A: A system uses a watch-dog timer to terminate
accesses to un-populated address space. The timer asserts
DTACK and BERR simultaneously after time~ut. (case 4)
Example B: A system uses error detection on RAM contents. Designer may (a) delay DTACK until data verified, and
return BERR and HALT simultaneously to re-run error cycle
(case 6), or if valid, return DTACK; (b) delay DTACK until
data verified. and return BERR at same time as DTACK if
data in error (case 4); (c) return DTACK prior to data verification, as described in previous section. If data invalid, BERR is
asserted (case 1) in next cycle. Error-handling software must
know how to recover error cycle.

Table 4 DTACK, BERR, HALT Assertion Results

Case No.

Control Signal

Asserted on Rising
Edge of State
N

N+2

X
X

S

1

DTACK
BERR
HALT

A
NA
NA

2

DTACK
BERR
HALT

A
NA
A

X

3

DTACK
BERR
HALT

NA
NA
A

A
NA
S

DTACK
BERR
HALT

X

X

4

A
NA

S
NA

DTACK
BERR
HALT

NA
A
NA

X

5

DTACK
BERR
HALT

X

X

6

A
A

S
S

7

DTACK
BERR
HALT

NA
NA
A

A
S

gend:
N A NA X S -

Result

Normal cycle terminate and continue.

S
Normal cycle terminate and halt. Continue when HALT removed.

S
Normal cycle terminate and halt. Continue when HALT removed.

Terminate and take bus error trap.

Terminate and re-run.

S
A

Terminate and re-run when HALT removed.

X
Terminate and re-run when HALT removed.

The number of the current even bus state (e.g., S4, S6, etc.)
Signal is asserted in this bus state
Signal is not asserted in this state
Don't care
Signal was asserted in previous state and remains asserted in this state

$

HITACHI

609

H068000,H o 68000Y, Ho 68000Z-----------------------------------------------Table 5 BERR and HALT Negation Results
Conditions of
Termination in
Table A

Control Signal

Bus Error

BERR
HALT

Re-run

BERR
HALT

Re-run

BERR
HALT

Normal
Normal

•

Negated on Rising
Edge of State
N

i3tlffi
HALT
BERR
HALT

•
•
•
•
•
•
•
•

or
or
or

•
•
•

Takes bus error trap.
Illegal sequence; usually traps to vector number O.
Re-runs the bus cycle.

•
or
or

May lengthen next cycle.

•
•
none

ASYNCHRONOUS VERSUS SYNCHRONOUS OPERATION

ASYNCHRONOUS OPERATION

To achieve clock frequency independence at a system level,
the HD68000 can be used in an asynchronous manner. This
entails using only the bus handshake lines (AS, UDS, LDS,
-DTACK, BERR, HALT, and VPA) to control the data transfer.
Using this method, AS signals the start of a bus cycle and the
data strobes are used as a condition for valid data on a write
cycle. The slave device (memory or peripheral) then responds by
placing the requested data on the data bus for a read cycle
or latching data on a write cycle and asserting the data transfer
acknowledge signal (IJ1'ACK) to terminate the bus cycle. If
no slave responds or the access is invalid, external control logic
asserts the BERR, or BERR and HALT, signal to abort or
re-run the bus cycle.
The DTACK signal is allowed to be asserted before the data
from a slave device is valid on a read cycle. The length of
time that DTACK may precede data is given as parameter #31
and it must be met in any asynchronous system to insure that
valid data is latched into the processor. Notice that there is no
maximum time speCified from the assertion of AS to the assertion of DT ACK. This is because the MPU will insert wait cycles
of one clock period each until DT ACK is recognized.
The BERR signal is allowed to be asserted after the DT ACK
signal is asserted. BERR must be asserted within the time given
as parameter #48 after DT ACK is asserted in any asynchronous
system to insure proper operation. If this maximum delay time
is violated, the processor may exhibit erratic behavior.
SYNCHRONOUS OPERATION

To allow for those systems which use the system clock as a
signal to generate DTACK and other asynchronous inputs,
the asynchronous input setup time is given as parameter #47. If
this setup is met on an input, such as DTACK, the processor is
guaranteed to recognize that signal on the next falling edge of
the system clock. However, the converse is not true - if the
input signal does not meet the setup time it is not guaranteed
not to be recognized. In addition, if DT ACK is recognized
on a falling edge, valid data will be latched into the processor
(on a read cycle) on the next falling edge provided that the data
meets the setup time given as parameter #27. Given this, parameter #31 may be ignored. Note that if DT ACK is asserted,
with the required setup time, before the falling edge of S4, no
wait status will be incurred and the bus cycle will run at its
maximum speed of four clock periods.

610

Results - Next Cycle

N+2

$

If next cycle is started it will be terminated as a bus error.

In order to assure proper operation in a synchronous system
when BERR is asserted after DT ACK, BERR must meet the
setup time parameter #27 A prior to the falling edge of the clock
one clock cycle after DT ACK was recognized. This setup time
is critical to proper operation, and the HD68000 may exhibit
erratic behavior if it is violated.
(NOTE)

During an active bus cycle, VPA and BERR are sampled
on every falling edge of the clock starting with SO.
DT ACK is sampled on every falling edge of the clock
starting with S4 and data is latched on the falling edge of
S6 during a read. The bus cycle will then be terminated
in S7 except when BERR is asserted in the absence of
DTACK, in which case it will terminate one clock cycle
later in S9.
•

RESET OPERATION

The reset signal is a bidirectional signal that allows either the
processor or an external signal to reset the system. Figure 31
is a timing diagram for reset operations. Both the halt and reset
lines must be applied to ensure total reset of the processor.
When the reset and halt lines are driven by an external
device, it is recognized as an entire system reset, including
the processor. The processor responds by reading the reset
vector table entry (vector unumber zero, address $000000)
and load.s it into the supervisor stack pointer (SSP). Vector
table entry number one at address $000004 is read next and
loaded into the program counter. The processor initializes
the status register to an interrupt level of seven. No other
registers are affected by the reset sequence.
When a RESET instruction is executed, the processor drives
the reset pin for 124 clock pulses. In this case, the processor
is trying to reset the rest of the system. Therefore, there is
no effect on the internal state of the processor. All of the
processor's internal registers and the status register are unaffected by the execution of a RESET instruction. All external
devices connected to the reset line should be reset at the completion of the RESET instruction.
Asserting the Reset and Halt pins for 10 clock cycles will
cause a processor reset, except when Vee is initially applied
to the processor. In this case, an external reset must be applied
for 100 milliseconds.

HITACHI

------------------------H068000,H068000Y,H068000Z
ClK
Plus 5 Volts
Vee

t

RES

1

HALT

1

> 100 Milliseconds--.j,...._ _ _ _ _ _ _ _ _ _ _ _ __

I
f-----l

t

<4

Bus Cycles
(2)

(NOTES)
1) Internal start-up time 4) PC High read in here
2) SSP High read in here 5) PC low read in here
3) SSP low read in here 6) First instruction fetched here.

Figure 31

•

(3)

Bus State Unknown:

(4)

(5)

(6)

)O()O(:;O(

A~;~n~~~II~i~n:~~ I~~~!~e.

>--<

Reset Operation Timing Diagram

PROCESSING STATES

•

This section describes the HD68000 which are outside the
normal processing associated with the execution of instructions.
The functions of the bits in the supervisor portion of the status
register are covered: the supervisor/user bit, the trace enable bit,
and the processor interrupt priority mask. Finally, the sequence
of memory references and actions taken by the processor on
exception conditions is detailed.
The HD68000 is always in one of three processing states:
normal, exception, or halted. The normal processing state is
that associated with instruction execution; the memory references are to fetch instructions and operands, and to store
results. A special case of the normal state is the stopped state
which the processor enters when a STOP instruction is executed. In this ~tate, no further memory references are made.
The exception processing state is associated with interrupts,
trap instructions, tracing and other exceptional conditions.
The exception may be internally generated by an instruction
or by an unusual condition arising during the execution of
an instruction. Externally, exception processing can be forced
by an interrupt, by a bus error, or by a reset. Exception processing is designed to provide an efficient context switch so that
the processor may handle unusual conditions.
The halted processing state is an indication of catastrophic
hardware failure. For example, if during the exception processing of a bus error another bus error occurs, the processor
assumes that the system is unusable and halts. Only an external
reset can restart a halted processor. Note that a processor in the
stopped state is not in the halted state, nor vice versa.

PROCESSING STATES

NORMAL

INSTRUCTION
EXECUTION
(INCLUDING STOP)

EXCEPTION

INTERRUPTS
TRAPS
TRACING ETC.

HALTED

HARDWARE HALT
DOUBLE BUS FAULT

PRIVILEGE STATES

The processor operates in one of two states of privilege:
the "user" state or the "supervisor" state. The privilege state
determines which operations are legal, is used by the external
memory management device to control and translate accesses,
and is used to choose between the supervisor stack pointer
and the user stack pointer in instruction references.
The privileges state is a mechanism for providing security
in a computer system. Programs should access only their own
code and data areas, and ought to be restricted from accessing
information which they do not need and must not modify.
The privilege mechanism provides security by allowing
most programs to execute in user state. In this state, the accesses are controlled, and the effects on other parts of the
system are limited. The operating system executes in the supervisor state, has access to all resources, and performs the overhead tasks for the user state programs.
SUPERVISOR STATE

The supervisor state is the higher state of privilege. For
instruction execution, the supervisor state is determined by
the S-bit of the status register; if the S-bit is asserted (high),
the processor is in the supervisor state. All instructions can be
executed in the supervisor state. The bus cycles generated by
instructions executed in the supervisor state are classified as
supervisor references. While the processor is in the supervisor
privilege state, those instructions which use either the system
stack pointer implicitly or address register seven explicitly
access the supervisor stack pointer.
All exception processing is done in the supervisor state,
regardless of the setting of the S-bit. The bus cycles generated
during exception processing are classified as supervisor references. All stacking operations during exception processing use
the supervisor stack pointer.
USER STATE

The user state is the lower state of privilege. For instruction
execution, the user state is determined by the S-bit of the status
register; if the S-bit is negated (low), the processor is executing
instructions in the user state.
Most instructions execute the same in user state as in the
supervisor state. However, some instructions which have important system effects are made privileged._ User programs
are not permitted to execute the STOP instruction, or the

$

HITACHI

611

HD68000,HD68000Y,HD68000Z-----------------------------------------------RESET instruction. To ensure that a user program cannot
enter the supervisor state except in a controlled manner, the
instructions which modify the whole status register are privileged. To aid in debugging programs which are to be used as
operating systems, the move to user stack pointer (MOVE
USP) and move from user stack. pointer (MOVE from USP)
instructions are also privileged.
The bus cycles generated by an instruction executed in
user state are classified as user state references. This allows
an external memory management device to translate the address and to control access to protected portions of the address
space. While the processor is in the user privilege state, those
instructions which use either the system stack pointer implicitly, or address register seven explicitly, access the use stack
pointer.
PRIVILEGE STATE CHANGES
Once the processor is in the user state and executing instructions, only exception processing can change the privilege state.
During exception processing, the current setting of the S-bit
of the status register is saved and the S-bit is asserted, putting
the processing in the supervisor state. Therefore, when instruction execution resumes at the address specified to process the
exception, the proceSsor is in the supervisor privilege state.
USER/SUPERVISOR MODES
TRANSITION ONLY MAY OCCUR
DURING EXCEPTION PROCESSING

TRANSITION MAY BE MADE BY;
RTE; MOVE, ANDI. EORI TO STATUS WORD

REFERENCE CLASSIFICATION
When the processor makes a reference, it classifies the kind
of reference being made, using the encoding on the three function code output lines. This allows external translation of addresses, control of access, and differentiation of special processor states, such as. interrupt acknowledge. Table 6 lists the
classification of references.

•

EXCEPTION PROCESSING
Before discussing the details of interrupts, traps, and tracing,
a general description of exception processing is in order. The
processing of an exception occurs in four steps, with variations
for different exception causes. During the first step, a temporary copy of the status register is made, and the status register
is set for exception processing. In the second step the exception
vector is determined, and the third step is the saving of the
current processor context. In the fourth step a new context is
obtained, and the processor switches to instruction processing.
EXCEPTION VECTORS
Exception vectors are memory locations from which the
processor fetches the address of a routine which will handle
that exception. All exception vectors are two words in length
(Figure 32), except for the reset vector, which is four words.
All exception vectors lie in the supervisor data space, except
for the reset vector which is in the supervisor program space.
A vector number is an eight-bit number which, when multiplied
by four, gives the address of an exception vector. Vector numbers are generated internally or externally depending on the
cause of the exception. In the case of interrupts, during the
interrupt acknowledge bus cycle, a peripheral provides an 8-bit
vector number (Figure 33) to the processor on data bus lines Do
through D 7 • The processor translates the vector number into
a full 24-bit address, as shown in Figure 34. The memory
layout for exception vectors is given in Table 7.
As shown in Table 7, the memory layout is 512 words
long (1024 bytes). It starts at address 0 and proceeds through
address 1023. This provides 255 unique vectors; some of these
are reserved for TRAPS and other system functions. Of the
255, there are 192 reserved for user interrupt vectors. However,
there is no protection on the first 64 entries, so user interrupt
vectors may overlap at the discretion of the systems designer.
KINDS OF EXCEPTIONS
Exceptions can be generated by either internal or external
causes. The externally generated exceptions are the interrupts
and the bus error and reset requests. The interrupts are requests
from peripheral devices for processor action while the bus
error and reset inputs are used for access control and processor
restart. The internally generated exceptions come from instructions, or from address error or tracing. The trap (TRAP), trap
on overflow (TRAPV), check register against bounds (CHK)
and divide (DIV) instructions all can generate exceptions as
part of their instruction execution. In addition, illegal instructions, word fetches from odd addresses and privilege violations
cause exceptions. Tracing behaves like a very high priority,
internally generated interrupt after each instruction execution.

Table 6 Reference Classification
Function Code Output

Reference Class

FC 2

FC!

FC o

0

0
0
1
1

0
1

0

0

(Unassigned)

1

Supervisor Data

1

0
1

a

Supervisor Program

1

1

1

Interrupt Acknowledge

0
0
0
1
1

612

0
1

(Unassigned)
User Data
User Program
(Unassigned)

EXCEPTION PROCESSING SEQUENCE
Exception processing occurs in four identifiable steps. In
the first step, an internal copy is made of the status register.
After the copy is made, the S-bit is asserted, putting the processor into the supervisor privilege state. Also, the T-bit is
negated which will allow the exception handler to execute
unhindered by tracing. For the reset and interrupt exceptions,
the interrupt priority mask is also updated.
In the second step, the vector number of the exception is
determined. For interrupts, the vector number is obtained by
a processor fetch, classified as an interrupt acknowledge. For
all other exceptions, internal logic provides the vector number.
This vector number is then used to generate the address of
the exception vector.

~HITACHI

-----------------------------------------------HD68000,HD68000Y,HD68000Z
Word 0

New Program Counter (High)

AO=O, A1 =0

Word 1

New Program Counter (Low)

AO=O,A1=1

Figure 32

Exception Vector Format

015

0807

DO

!V7! V6! V5! V4! V3! V2! v1 !vO !

Ignored

Where:
v7 is the MSB of the Vector Number
vO is the LSB of the Vector Number
Figure 33

Peripheral Vector Number Format

A23
All Zeroes
Figure 34

Address Translated From 8-Bit Vector Number

Table 7

Exception Vector Assignment

Address

Vector
Numbeds)

Dec

Hex

Space

0

0

000

SP

-

4

004

SP

Reset: Initial PC

2

8

008

SO

Bus Error
Address Error

Assignment
Reset: Initial SSP

3

12

OOC

SO

4

16

010

SO

Illegal Instruction

5

20

014

SO

Zero Divide
CH K Instruction

6

24

018

SO

7

28

01C

SO

TRAPV Instruction

8

32

020

SO

Privilege Violation
Trace

9

36

024

SO

10

40

028

SO

Line 1010 Emulator

11

44

02C

SO

Line 1111 Emulator

12*

48

030

SO

(Unassigned, reserved)

13*

52

034

SO

(Unassigned, reserved)

14*

56

038

SO

(Unassigned, reserved)

15

60

03C

SO

Uninitialized Interrupt Vector

64

04C

95

05F

16 - 23*

SO

(Unassigned, reserved)

24

96

060

SO

Spurious Interrupt

25

100

064

SO

Level 1 Interrupt Autovector

26

104

068

SO

Level 2 Interrupt Autovector

27

108

06C

SO

Level 3 Interrupt Autovector

28

112

070

SO

Level 4 Interrupt Autovector

29

116

074

SO

Level 5 Interrupt Autovector

30

120

078

SO

Level 6 Interrupt Autovector

31

124

07C

SO

Level 7 Interrupt Autovector

128

080

SO

TRAP Instruction Vectors

SO

(Unassigned, reserved)

SO

User Interrupt Vectors

32 -47
48 - 63*
64 - 255

191

OBF

192

OCO

255

OFF

256

100

1023

3FF

SP: Supervisor program, SO: Supervisor data
* Vector numbers 12, 13, 14, 16 through 23 and 48 through 63 are reserved for future enhancements by Hitachi.
No user peripheral devices should be assigned these numbers.

@HITACHI

613

H068000,H068000Y,H068000Z----------------------The third step is to save the current processor status, except for the reset exception. The current program counter
value and the saved copy of the status register are stacked
using the supervisor stack pointer. The program counter value
stacked usually points to the next unexecuted instruction,
however for bus error and address error, the value stacked
for the program counter is unpredictable, and may be incremented from the address of the instruction which caused the

error. Additional information defining the current context is
stacked for the bus error and address error exceptions.
The last step is the same for all exceptions. The new program
counter value is fetched from the exception vector. The processor then resumes instruction execution. Then instruction
at the address given in the exception vector is fetched, and
normal instruction decoding and execution is started.

Figure 35 Exception Processing Sequence (Not Reset)

614

•

HITACHI

------------------------------------------------H068000,H068000Y,H068000Z
MULTIPLE EXCEPTIONS

These par(lgraphs describe the processing which occurs
when multiple exceptions arise simultaneously. Exceptions
can be grouped according to their occurrence and priority. The
Group 0 exceptions are reset, bus error, and address error.
These exceptions cause the instruction currently being executed
to be aborted, and the exeception processing to commence
within two clock cycles. The Group 1 exceptions are trace and
interrupt, as well as the privilege violations and illegal instructions. These exceptions allow the current instruction to execute
to completion, but preempt the execution of the next instruction by forCing exception processing to occur (privilege violations and illegal instructions are detected when they are the
next instruction to be executed). The Group 2 exceptions
occur as part of the normal processing of instructions. The
TRAP, TRAPV, CHK, and zero divide exceptions are in this
group. For these exceptions, the normal execution of an instruction may lead to exception processing.
Group 0 exceptions have highest priority, while Group 2
exceptions have lowest priority. Within Group 0, reset has
highest priority, followed by address error and then bus error.
Within Group 1, trace has priority over external interrupts,
which in turn takes priority over illegal instruction and privilege violation. Since only one 'instruction can be executed at
a time, there is no priority relation within Group 2.
The priority relation between two exceptions determines
which is taken, or taken first, if the conditions for both arise
simultaneously. Therefore, if a bus error occurs during a TRAP
instruction, the bus error takes precedence, and the TRAP
instruction processing is aborted. In another example, if an
interrupt request occurs during the execution of an instruction
while the T-bit is asserted, the trace exception has priority,
and is processed first. Before instruction processing resumes,
however, the interrupt exception is also processed, and instruction processing commences finally in the interrupt handler
routine. A summary of exception grouping and priority is given
in Table 8.
Table 8

Exception Grouping and Priority

Group

Exception

0

Reset
Address Error
Bus Error

Exception processing begins
within two clock cycles.

1

Trace
Interrupt
Illegal
Privilege

Exception processing begins
before the next instruction

2

TRAP, TRAPV
CHK,
Zero Divide

Exception processing is started by
normal instruction execution

Processing

RECOGNITION TIMES OF EXCEPTIONS,
HALT, AND BUS ARBITRATION
END OF A CLOCK CYCLE
RESET
END OF A BUS CYCLE
ADDRESS ERROR
BUS ERROR
HALT
BUS ARBITRATION
END OF AN INSTRUCTION CYCLE
TRACE EXCEPTION
INTERRUPT EXCEPTIONS
ILLEGAL INSTRUCTION
UNIMPLEMENTED INSTRUCTION
PRIVILEGE VIOLATION
WITHIN AN INSTRUCTION CYCLE
TRAP, TRAPV
CHK
ZERO DIVIDE

•

EXCEPTION PROCESSING DETAILED DISCUSSION

Exceptions have a number of sources, and each exception
has processing which is peculiar to it. The following paragraphs
detail the sources of exceptions, how each arises, and how each
is processed.
RESET

The reset input provides the highest exception level. The
processing of the reset signal is designed for system initiation,
and recovery from catastrophic failure. Any processing in progress at the time of the reset is aborted and cannot be recovered.
The processor is forced into the supervisor state, and the trace
state is forced off. The processor interrupt priority mask is set
at level seven. The vector number is internally generated to
reference the reset exception vector at location 0 in the supervisor program space. Because no assumptions can be made about
the validity of register contents, in particular the supervisor
stack pointer, neither the program counter nor the status
register is saved. The address contained in the first two words
of the reset exception vector is fetched as the initial supervisor
stack pointer, and the address in the last two words of the
reset exception vector is fetched as the initial program counter.
Finally, instruction execution is started at the address in the
program counter. The power-up/restart code should be pointed
to by the initial program counter.
The RESET instruction does not cause loading of the reset
vector, but does assert the reset line to reset external devices.
This allows the software to reset the system to a known state
and then continue processing with the next instruction.

@HITACHI

615

HD68000,HD68000Y,HD68000Z-----------------------

Yes

> - - - - - -.... Sus Error Exception Processing

Figure 36 Reset Exception Processing

INTERRUPTS

Seven levels of interrupt priorities are provided. Devices
may be chained externally within interrupt priority levels,
allowing an unlimited number of peripheral devices to interrupt the processor. Interrupt priority levels are numbered
from one to seven, with level seven being the highest priority.
The status register contains a three-bit mask which indicates the
current processor priority, and interrupts are inhibited for
all priority levels less than or equal to the current processor
priority.
An interrupt request is made to the processor by encoding
the interrupt request level on the interrupt request lines; a
zero indicates no interrupt request. Interrupt requests arriving
at the processor do not force immediate exception processing,

616

$

but are made pending. Pending interrupts are detected between
instruction executions. If the priority of the pending interrupt
is lower than or equal to the current processor priority, execution continues with the next instruction and the interrupt
exception processing is postponed. (The recognition of level
seven is slightly different, as explained in a following paragraph.)
If the priority of the pending interrupt is greater than the
current processor priority, the exception processing sequence
is started. First a copy of the status register is saved, and the
privilege state is set to supervisor, tracing is suppressed, and
the processor priority level is set to the level of the interrupt
being acknowledged. The processor fetches the vector number
from the interrupting device, classifying the reference as an
interrupt acknowledge and displaying the level number of

HITACHI

------------------------H068000,H068000Y,H068000Z
the interrupt being acknowledged on the address bus. If external
logic requests an automatic vectoring, the processor internally
generates a vector number which is determined by the interrupt
level number. If external logic indicates a bus error, the interrupt is taken to be spurious, and the generated vector number
references the spurious interrupt vector. The processor then
proceeds with the usual exception processing, saving the program counter and status register on the supervisor stack. The
saved value of the program counter is the address of the instruction which would have been executed had the interrupt not
been present. The content of the interrupt vector whose vector
number was previously obtained is fetched and loaded into the
program counter, and normal instruction execution commences
in the interrupt handling routine. A flow chart for the interrupt
acknowledge sequence is given in Figure 37, a timing diagram
is given in Figure 38, and the interrupt exception timing sequence is shown in Figure 39.

PROCESSOR

INTERRUPTING DEVICE
Request Interrupt

Grant Interrupt
1) Compare interrupt level in status register
and wait for current instruction to complete
2) Place interrupt level on A. , A" A3
3) Set R/W to read
4) Set function code to interrupt acknowledge
5) Assert address strobe (AS)
6) Assert lower data strobe ([[55)*

I
Provide Vector Number
1) Place vector number of Do - D7
2) Assert data transfer acknowledge (DTACK)

I
Table 9
Level

Internal Interrupt Level

12

11

10

1

1
0

7

1

6

1

1

5

1

0

1

4

1

0

0

3

0

1

1

2

0

1

0

1

0

0

1

0

0

0

0

(NOTE)

Acquire Vector Number

Interrupt
Non-Maskable Interrupt
I'

1) Latch vector number
2) Negate LDS*
3) Negate AS

~

Maskable Interrupt

Release
1) Negate DTACK

No Interrupt
Start Interrupt Processing

The internal interrupt mask level 112,11,10) are inverted to th,
logic level appl ied to the pins (WL, , fI5l. , fPCo ).

Figure 37

Interrupt Acknowledge Sequence
Flow Chart

CLK

A. - Al

J-<. . . ._______

~----------~)~--------------~~----------r----..\I-__---.J!
\I-__ r

.J

As~~_ ____J

--J

~~\

\

I~--------------~~

LJ

I

\_---\~----~/~----------~\~---

--~====r_A~----------------~(====
----~--~~~----r(~~-_-~})----------~(

------~~------~--\~------------____________________
~~~-------------------------~7
St k
PCacL

I

Last Bus Cycle of Instruction
(Read or Write)
_, .. Idle

I_

-

I

lACK Cycle
(Vector Number Acquisition)

7SSP) -

4 Clocks
Idle

Stack and
Vector Fetch.

... ,-

* Although a vector number is one byte, both data strobes are asserted due to the microcode used for exception processing. The
processor does not recognize anything on data lines Ds through D. s at this time.

Figure 38

Interrupt Acknowledge Sequence Timing Diagram

eHITACHI

617

HD68000,HD68000Y,HD68000Z-----------------------

last Bus Cycle
of Instruction
(During Which
Interrupt Was
Recognized)

~

-

Stack
PCl
(SSP)

Read
Vector
High
(A 16 -A 23 )

r-----

lACK
Cycle
(Vector Number
Acquisition)

Read
Vector
low
(Ao - A .. )

-

Stack
Status
(SSP)

r----

f---+

-

Stack
PCH
(SSP)

Fetch First Word
of Instruction
of Interrupt
Routine

Figure 39 Interrupt Exception Timing Sequence

Priority level seven is a special case. Level seven interrupts
cannot be inhibited by the interrupt priority mask, thus providing a "non-maskable interrupt" capability. An interrupt is
generated each time the interrupt request level changes from
some lower level to level seven. Note that a level seven interrupt
may still be caused by the level comparison if the request level
is a seven and the processor priority is set to a lower level by an
instruction.

Word patterns with bits 15 through 12 equaling 1010 or
1111 are distinguished as unimplemented instructions and
separate exception vectors are given to these patterns to permit efficient emulation. This facility allows the operating
system to detect program errors, or to emulate unimplemented
instructions in software.
ILLEGAL INSTRUCTION EXAMPLE

UNINITIALIZED INTERRUPT

An interrupting device asserts VPA or provides an interrupt
vector during an interrupt acknowledge cycle to the HD68000.
If the vector register has not been initialized, the responding
HMCS68000 Family peripheral will provide vector 15, the
unitialized interrupt vector. This provides a uniform way to
recover from a programming error.

MOVE DO, #$1000

+

MOVE OPWORD

0011

tMOVE

100111

t
IMMEDIATE

WORD

SPURIOUS INTERRUPT

If during the interrupt acknowledge cycle no device responds
by asserting DTACK or VPA, the bus error line should be asserted to terminate the vector acquisition. The processor separates
the processing of this error from bus error by fetching the
spurious interrupt vector instead of the bus error vector. The
processor then proceeds with the usual exception processing.
INSTRUCTION TRAPS

Traps are exceptions caused by instructions. They arise
either from processor recognition of abnormal conditions
during instruction execution, or from use of instructions whose
normal behavior is trapping.
Some instructions are used specifically to generate traps.
The TRAP instruction always forces an exception, and is useful
for implementing system calls for user programs. The TRAPV
and CHK instructions force an exception if the user program
detects a runtime error, which may be an arithmetic overflow
or a subscript out of bounds.
The signed divide (DNS) and unsigned divide (DIVU) instructions will force an exception' if a division operation is
attempted with a divisor of zero.
ILLEGAL AND UNIMPLEMENTED INSTRUCTIONS

Illegal instruction is the term used to refer to any of the
word bit patterns which are not the bit pattern of the first
word of a legal instruction. DUring instruction execution, if
such an instruction is fetched, an illegal instruction exception
occurs.
618

+

000

t
DATA
REGISTER
DIRECT

-,000

REGISTER
NUMBER

"0"

PRIVILEGE VIOLATIONS

In order to provide system security, various instructions
are privileged. An attempt to execute one of the privileged
instructions while in the user state will cause an exception.
The privileged instruction are:
STOP
AND (word) Immediate to SR
RESET
EOR (word) Immediate to SR
RTE
OR (word) Immediate to SR
MOVE to SR
MOVE USP
TRACING

To aid in program development, the HD68000 includes
a facility to allow instruction by instruction tracing. In the
trace state, after each instruction is executed an exceptions
is forced, allowing a debugging program to monitor the execution of the program under test.
The trace facility uses the T-bit in the supervisor portion
of the status register. If the T-bit is negated (off), tracing is
disabled, and instruction execution proceeds from instruction
to instruction as normal. If the T-bit is asserted (on) at the
beginning of the execution of an instruction, a trace exception
will be generated after the execution of that instruction is
completed. If the instruction is not executed. either because
an interrupt is taken, or the instruction is illegal or privileged,
the trace exception does not occur. The trace exception also
does not occur if the instruction is aborted by a reset, bus

eHITACHI

error, or address error exception. If the instruction is indeed executed and an interrupt is pending on completion, the trace
exception is processed before the interrupt exception. If, during
the execution of the instruction, an exception is forced by that
instruction, the forced exception is processed before the trace
exception.
As an extreme illustration of the above rules, consider the
arrival of an interrupt during the execution of a TRAP instruction while tracing is enabled. First the trap exception is processed, then the trace exception, and finally the interrupt exception. Instruction execution resumes in the interrupt handler
routine.
TRACE MODE

IF T = 1

STATUS REGISTER

the bus error occurred. The processor is processing an instruction if it is in the normal state or processing a Group 2 exception; the processor is not processing an instruction if it is processing a Group 0 or a Group 1 exception. Figure 40 illustrates
how this information is organized on the supervisor stack.
Although this information is not sufficient in general to effect
full recovery from the bus error, it does allow software diagnosis. Finally, the processor commences instruction processing
at the address contained in the vector. It is the responsibility
of the error handler routine to clean up the stack and determine
where to continue execution.
If a bus error occurs during the exception processing for a
bus error, address error, or reset, the processor is halted, and
all processing cases. This simplifies the detection of catastrophic
system failure, since the processor removes itself from the
system rather than destroy all memory contents. Only the
RESET pin can restart a halted processor.
ADDRESS ERROR

RETURN TO
EXECUTE
NEXT
INSTRUCTION
ADDRESS OBTAINED
FROM VECTOR TABLE

1. If, upon completion of an instruction, T = 1,
go to trace exception processing.
2. Execute trace exception sequence.
3. Execute trace service routine.
4. At the end of the service routine, execute
return from exception (RTE).

Address error exceptions occur when the processor attempts
to access a word or a long word operand or an instruction at
an odd address. The effect is much like an internally generated
bus error, so that the bus cycle is aborted, and the processor
ceases whatever processing it is currently doing and begins
exception processing. After exception processing commences,
the sequence is the same as that for bus error including the
information that is stacked, except that the vector number
refers to the address error vector instead. Likewise, if an address
error occurs during the exception processing for a bus error,
address error, or reset, the processor is halted. As shown in
Figure 42, an address error will execute a short bus cycle followed by exception processing.
•

BUS ERROR

Bus error exceptions occur when the external logic requests
that a bus error be processed by an exception. The current bus
cycle which the processor is making is then aborted. Whether
the processor was doing instruction or exception processing,
that processing is terminated, and the processor immediately
begins exception processing.
Exception processing for bus error follows the usual sequence of steps. The status register is copied, the supervisor
state is entered, and the trace state is turned off. The vector
number is generated to refer to the bus error vector. Since the
processor was not between instructions when the bus error
exception request was made, the context of the processor is
more detailed. To save more of this context, additional information is saved on the supervisor stack. The program counter
and the copy of the status register are of course saved. The value
saved for the program counter is advanced by some amount,
two to ten bytes beyond the address of the first word of the
instruction which made the reference causing the bus error. If
the bus error occurred during the fetch of the next instruction,'
the saved program counter has a value in the vicinity of the
current instruction, even if the current instruction is a branch,
a jump, or a return instruction. Besides the usual information,
the processor saves its internal copy of the first word of the
instruction being processed, and the address which was being
accessed by the aborted bus cycle. Specific information about
the access is also saved: whether it was a read or a write, whether the processor was processing an instruction or not, and the
classification displayed on the function code outputs when

INTERFACE WITH HMCS6800 PERIPHERALS

Hitachi's extensive line of HMCS6800 peripherals are directly compatible with the HD68000. Some of these devices
that are particularly useful are:
HD6821
Peripheral Interface Adapter
HD6840 Programmable Timer Module
HD6843
Floppy Disk Controller
HD6845S CRT Controller
HD46508 Analog Data Acquisition Unit
HD6850
Asynchronous Communication Interface
Adapter
HD6852
Synchronous Serial Data Adapter
To interface the synchronous HMCS6800 peripherals with
the asynchronous HD68000, the processor modifies its bus
cycle to meet the HMCS6800 cycle requirements whenever an
HMCS6800 device address is detected. This is possible since
both processors use memory mapped I/O. Figure 44 is a flow
chart of the interface operation between the processor and
HMCS6800 devices.
•

DATA TRANSFER OPERATION

Three signal on the processor provide the HMCS6800 interface. They are: enable (E), valid memory address (VMA), and
valid peripheral address (VPA). Enable corresponds to the
E or 1/>2 signal in existing HMCS6800 systems. The bus frequency is one tenth of the incoming HD68000 clock frequency.
The timing of E allows 1 MHz peripherals to be used with
an 8 MHz HD68000. Enable has a 60/40 duty cycle; that
is, it is low for six input clocks and high for four input clocks.
This duty cycle allows the processor to do successive VPA accesses on successive E pulses.
HMCS6800 cycle timing is given in Figure 45 and 46. At

~HITACHI

619

HD68000,HD68000Y,HD68000Z----------------------15

14

13

12

11

10

9

8

7

543

6

2

0

Function Code

Lower Address

- -

High
• Access Address----- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .
low
Instruction Register
Status Register
High

1-- -Program Counter----- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .
low
R/IN (read/write): write = O. read = 1. I/N (instruction/not): instruction = O. not = 1

Figure 40 Supervisor Stack Order (Group 0)

15

14

13

12

11

10

9

Lower Address

6

8

4

5

3

o

2

Status Register
High

- - - - - Program Counter - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Higher Address
low

Figure 41

Supervisor Stack Order (Group 1,2)

ClK
A.-Au

AS

\

UOS

\

lOS

\

I
I
I

\

\

/
I

\

/

\

R/W
OTACK

(

Do - 015

I-

Read

)

\

Aerr
Write

Approx.8 Clocks
• Idle
1

LL-

'--

}----l\

<

-I-

~

'...

I

\

,

\

~

(

·1-

Write Stack

Figure 42 Address Error Timing

state zero (SO) in the cycle, the address bus is in the highimpedance state. A function code is asserted on the function
code output lines. One-half clock later, in state 1 the address
bus is released from the high-impedance state.

620

During state 2, the address strobe (AS) is asserted to indicate that there is a valid address on the address bus. If the
bus cycle is a read cycle, the upper and/or lower data strobes
are also asserted in state 2. If the bus cycle is a write cycle,

eHITACHI

------------------------HD68000,HD68000Y,HD68000Z
Do - 0 7 (or D. - D,s)

!I'--"-"---'--'----.::-'-----'-''-'-------'''J Do - 0

7

Address
&
CS's

Address 1--_ _ _..,/
Bus
AS t - - - - - - - - '

CS

HD68000
Block of
HMCS6800
Devices

VPA ~-----------~

VMA t - - - - - - - - - - - - - - - - i CS

E

E

Figure 43 Connection of HMCS6800 Peripherals

the read/write (R/W) signal is switched to low (write) during
state 2. One half clock later, in state 3, the write data is placed
on the data bus, and in state 4 the data strobes are issued to
indicate valid data on the data bus. The processor now inserts
wait states until it recognizes the assertion of VP A.
The VPA input signals the processor that the address on the
bus is the address of an HMCS6800 device (or an area reserved
for HMCS6800 devices) and that the bus should conform to
the 1/>2 transfer characteristics of the HMCS6800 bus. 'Valid
peripheral address is derived by decoding the address bus,
conditioned by address strobe. Chip select for the HMCS6800
peripherals should be derived by decoding the address bus
conditioned by VMA.
After the recognition of VP A, the processor assures that
the Enable (E) is low, by waiting if necessary, and subsequently
asserts VMA. Valid memory address is then used as part of the
chip select equation of the peripheral. This ensures that the
HMCS6800 peripherals are selected and deselected at the
correct time. The peripheral now runs its cycle during the
high portion of the E signal. Figures 45 and 46 depict the best
and worst case HMCS6800 cycle timing. This cycle length is
dependent strictly upon when VP A is asserted in relationship
to the E clock.
If we assume that external circuitry asserts VPA as soon as
possible after the assertion of AS, then VPA will be recognized
as being asserted on the falling edge of S4. In this case, no
"extra" wait cycles will be inserted prior to the recognition of
VPA asserted and only the wait cycles inserted to synchronize
with the E clock will determine the total length of the cycle.
In any case, the synchronization delay will be some integral
number of clock cycles within the following two extremes:
1. Best Case - VPA is recognized as being asserted on the
falling edge three clock cycles before E rises for three
clock cycles after E falls).
2. Worst Case - VPA is recognized as being asserted on the
falling edge two clock cycles before E rises(or four clock
cycles after E falls).
During a read cycle, the processor latches the peripheral
data in state 6. For all cycles, the processor negates the address
and data strobes one half clock cycle later in state 7, and the
Enable signal goes low at this time. Another half clock later,
the address bus is put in the high-impedance state. During a
write cycle, the data bus is put in the high-impedance state

PROCESSOR

SLAVE

Initiate Cycle
1) The processor starts a normal Read or

Write cycle

Define HMCS6800 Cycle
1) External hardware asserts Valid Peripheral

Address (VPA)

Synchronize With Enable
1) The processor monitors Enable (E) until it is
low (Phase 1 )
2) The processor asserts Valid Memory Address

(VMA)

Transfer Data
1) The peripheral waits until E is active and
then transfers the data

Terminate Cycle
1) The processor waits until E goes low. (On a

Read cycle the data is latched as E goes
low internally)
2) The processor negates VMA
3) The processor negates AS, UDS, and LDS

~HITACHI

!

Start Next Cycle

Figure 44 HMCS6800 Interface Flow Chart

621

H068000,H068000Y,H068000Z----------------------50

51

52

53

54

w

w

w

w

w

w

w

w

w

w

w

w

55

56

57

50

ClK

A, - A23

AS

®
E

®

VPA
VMA
Data Out
Data In - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- -- -- -

FC -FC2 ______
o

(NOTE)

J~

- -- -- - -- - - --

________________________________________________________________________

This figure represents the best case HMC56800 timing where

VPA

~

falls before the third system clock cycle after the falling edge of E.

Figure 45 HMCS6800 Timing - Best Case

50 51 52 53 54 w w w w w w

ClK

w w w w w w w w

w w w w

w w w

w w

w

w w w

w 55 56 57 50

J\J"'~M~F- ~
\44;

A5 ~

,49.~
-------0

I

E

VPA

1

\

®

--

VMA

-

i@
I

i-@

-@--

®

(4l~

-.

-@

-

=!E
--~~

~®

R/W
(Read )

[

f

Data In

r
UD5/LDS
Read

\

R/WWrite

\

@-

®-

':!9/-

14--

~@

1.+14-

Data Out

UDS/LDS
Write

\

K

FC o - FC2

Figure 46 HMCS6800 Timing - Worst Case

622

eHITACHI

®

-----------------------HD68000,HD68000Y,HD68000Z

t=

HMCS6800'

~

Type A
Std

70ns~

140ns
140 ns

•

I

1.0 MHz

l -....l~O....n...
sH
...M
...C":"S~6~80~0~'-------------- Peripheral'
I - 10 ns Peripheral'
Type B ~ 180 ns~
Type A
Std

HD68000 Address

Std

--I f.- 10 ns HMCS6800'
--I
10 ns Peripheral

220 ns
320 ns

I

--------------~_;W$
Type 8
Type A
Std

HMCS6800Write Data

Type
B
A

==~~;;~--~==~---~
---l
---4

HMCS6800 Read Data

HMCS6800 E Clock Freq.
2.0 MHz
1.5 MHz

TypeB
Type A
Std

1

r-- - -

HMCS6800 VMA. R/Vii
HMCS6800 Address

Peripheral'

l50nS~TypeB

lBOns
270 ns

r--

)~-----

~pe"~~e~:13· I

--------------@'#$hl@~

80 ns
195 ns

)>-_ _ _ __

~
........
J;,",,;0
...Ij_________________________--I)>--------

1/1/1
HD68000 (8 MHzl
1---200 ns-..j
VMA

Write Data
HD68000 ClK
• Times are expressed for different device clock frequencies.

Figure 47 HD68000 to HMCS6800 Peripheral Timing Diagram

+5VTT I
1
33k

AS

.

VMA

r=?

Oil - DIS

)

AI -An

c5

"

I

I~
HD68000

.;

I~

1.£ .; .; .;

 «~ .; I'; , 7
es, CS, RS CS.

I

HD6850 ACIA

fl'fO E RIW

I

~:m

Il'"CO
RES
E
RIW

Figure 48 HMCS6800 Interface - Example 1

eHITACHI

623

0)

:L

N

o

~

C»
00

+} Ii

o
o

P
:L
o

6800 Address

C»

AS

00

o
o

VMA

r=?

r--~i

00-0"

ir-----li

A,-A"

v

31 •

~
AI
A,

A

74LS
138

:::

~

A B
5

•
::z:

AS

VPA

~

C

cs;
HD6821 PIA

~

' A 74LS
A2 B 138

~

I !!:~ I~!!:

A, C

(')

::z:

t

c(
:t

d
-.!

3.3k

HD68000

o

81 >

CXI
<0

Iffia:

w

HD6850 ACIA

I~a:

+5
3.3k

~I"~

~

CS, CSo RS

~ ~

74LS
348
or

74LS
A" 148

A,
A,

RES

R/W

Figure 49 HMCS6800 Interface - Example 2

I~

w

I~
a:

7

~

:L

o

C»
00

g
2

-----------------------HD68000,HD68000Y,HD68000Z
and the read/write signal is switched high. The peripheral logic
must remove VP A within one clock after address strobe is
negated.
Figure 47 shows the timing required by HMCS6800 peripherals, the timing specified for HMCS6800, and the corresponding timing for the HD68000. Two example systems with
HMCS6800 peripherals are shown in Figures 48 and 49. The
system in Figure 48 reserves the upper eight megabytes of
memory for HMCS6800 peripherals. The system in Figure 49
is more efficient with memory and easily expandable, but more
complex.

DTACK should not be asserted while VPA is asserted.
Notice that the HD68000 VMA is active low, contrasted with
the active high HMCS6800 VMA. This allows the processor
to put its buses in the high-impedance state on DMA requests
without inadvertently selecting peripherals.
-

INTERRUPT OPERATION

During an interrupt acknowledge cycle while the processor
is fetching the vector, if VPA is asserted, the HD68000 will
assert VMA and complete a normal HMCS6800 read cycle as
shown in Figure 50. The processor will then use an internally

ClK
A, -A 3

AS

\'----_-1r--\

UDS

r--\
r--\
\'-----~I
L-.J

,-,-,--

\
\

lOS
R/W

DTACK

c:::::::)
c:::::::)

D. -D,s
Do - 0 7

FC o - FC 2

'---

)-I

A. - A23

y

X

E,

IPl o - IPl 2

L-

VPA

\~------------------------------I,---

VMA

\'---------~,--

~~~~e~~:ng__+_PC

low Stacking--l·--tl...·-------Autovector O p e r a t i o n - - - - - - - -....·~If+·

~~~~:S::ng

* Although a vector number is one byte, both data strobes are asserted due to the microcode used for exception processing. The
processor does not recognize anything on data lines D. through D,s at this time.

Figure 50 Autovector Operation Timing Diagram

generated vector that is a function of the interrupt being serviced. This process is known as autovectoring. The seven autovectors are vector numbers 25 through 31 (decimal).
This operates in the same fashion (but is not restricted to)
the HMCS6800 interrupt sequence. The basic difference is that
there are six normal interrupt vectors and one NMI type vector.
As with both the HMCS6800 and the HD68000's normal
vectored interrupt, the interrupt service routine can be located
anywhere in the address space. This is due to the fact that
while the vector numbers are fixed, the contents of the vector
table entries are assigned by the user.
Since VMA is asserted during autovectoring, the HMCS6800
peripheral address decoding should prevent unintended accesses.

•

DATA TYPES AND ADDRESSING MODES

Five basic data types are supported. These data types are:
- Bits

- BCD Digits (4-bits)
- Bytes (8-bits)
- Word (16-bits)
_ Long Words (32-bits)
In addition, operations on other data types such as memory
addresses, status word data, etc., are provided for in the instruction set.
The 14 addressing modes, shown in Table 10, includs six
basic types:
_ Register Direct
_ Register Indirect
_ Absolute
_ Immediate
_ Program Counter Relative
- Implied
Included in the register indirect addressing modes is the capability to do postincrementing, predecrementing, offsetting and
indexing. Program counter relative mode can also be modified
via indexing and offsetting.

~HITACHI

625

H068000,H068000Y,H068000Z----------------------Table 10 Addressing Modes
Mode

•

Generation

Regilter Direct Addressing
Data Register Diredt
Address Register Direct

EA= On
EA = An

Absolute Data Addressing
Absolute Short
Absolute Long

EA = (Next Word)
EA = (Next Two Words)

Program Counter Relative Addressing
Relative with Offset
Relative with Index and Offset

EA = (PC) + d. 6
EA = PC) + (Xn) + do

Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset

EA = (An)
EA = (AN), An +-An + N
An +-An - N, EA = (An)
EA = (An) + d. 6
EA = (An) + (Xn) + d.

Immediate Data Addressing
Immediate
Quick Immediate

DATA = Next Word(s)
Inherent Data

Implied Addressing
Implied Register

EA = SR, USP, SP, PC

(NOTES)
EA = Effective Address
An = Address Register
On = Data Register
Xn = Address or Data Register used
as Index Register
SR = Status Register
PC = Program Counter
( ) = Contents of

do = Eight-bit Offset
(displacement)
d. 6 = Sixteen-bit Offset
(displacement)
N = 1 for Byte, 2 for
Words and 4 for Long
Words
= Replaces

Table 11
Mnemonic

Description

ABCD
ADD
AND
ASL
ASR

Add Decimal with Extend
Add
Logical And
Arithmetic Shift Left
Arithmetic Shift Right

Bee
BCHG
BCLR
BRA
BSET
BSR
BTST

Branch Conditionally
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and· Set
Branch to Subroutine
Bit Test

CHK
CLR
CMP

Check Register Against Bounds
Clear Operand
Compare

DBee

Test Condition, Decrement and
Branch
Signed Divide
Unsigned Divide

DIVS
DIVU

626

INSTRUCTION SET OVERVIEW
The HD68000 instruction set is shown in Table 11. Some
additional instructions are variations, or subsets, of these and
they appear in Table 12. Special emphasis has been given to
the instruction set's support of structured high-level languages
to facilitate ease of programming. Each instruction, with few
exceptions, operates on bytes, words, and long words and most
instructions can use any of the 14 addressing modes. Combining
instruction types, data types, and addressing modes, over 1000
useful instructions are provided. These instructions include
signed and unsigned multiply and divide, "quick" arithmetic
operations, BCD arithmetic and expanded operations (through
traps).
The following paragraphs contain an overview of the form
and structure of the HD68000 instruction set. The instructions form a set of tools that include all the machine functions
to perform the following operations:
Data Movement
Integer Arithmetic
Logical
Shift and Rotate
Bit Manipulation
Binary Coded Decimal
Program Control
System Control
The complete range of instruction capabilities combined
with the flexible addressing modes described previously provide a very flexible base for program development.

Mnemonic

Instruction Set
Description

EOR
EXG
EXT

Exclusive Or
Exchange Registers
Sign Extend

JMP
JSP

Jump
Jump to Subroutine

LEA
LINK
LSL
LSR

Mnemonic

Description

PEA

Push Effective Address

Load Effective Address
Link Stack
Logical Shift Left
Logical Shift Right

RESET
.ROL
ROR
ROXL
ROXR
RTE
RTR
RTS

Reset External Devices
Rotate Left without Extend
Rotate Right without Extend
Rotate Left with Extend
Rotate Right with Extend
Return from Exception
Return and Restore
Return from Subroutine

MOVE
MOVEM
MOVEP
MULS
MULU

Move
Move Multiple Registers
Move Peripheral Data
Signed Multiply
Unsigned Multiply

SBCD
Sec
STOP
SUB
SWAP

Subtract Decimal with Extend
Set Conditional
Stop
Subtract
Swap Data Register Halves

NBCD
NEG
NOP
NOT

Negate Decimal with Extend
Negate
No Operation
One's Complement

TAS
TRAP
TRAPV
TST

Test and Set Operand
Trap
Trap on Overflow
Test

OR

Logical Or

UNLK

Unlink

eHITACHI

------------------------------------------------H068000,H068000Y,H068000Z
Table 12 Variations of Instruction Types
Instruction
Type
ADD

Instruction
Type

Description

ADD
ADDA
ADDQ
ADDI
ADDX

Add
Add
Add
Add
Add

AND

AND
ANDI

Logical And
And Immediate

CMP

CMP
CMPA
CMPM
CMPI

Compare
Compare Address
Compare Memory
Compare Immediate

EOR
EORI

Exclusive Or
Exclusive Or Immediate

EOR

•

Variation

ADDRESSING

Move
Move
Move
Move
Move
Move
Move

NEG

NEG
NEGX

Negate
Negate with Extend

OR

OR
ORI

Logical Or
Or Immediate

SUB

SUB

Subtract
Subtract
Subtract
Subtract
Subtract

SUBA
SUBI
SUBQ
SUBX

Address
Quick
from Status Register
to Status Register
to Condition Codes
User Stack Pointer

Address
Immediate
Quick
with Extend

and negate instructions may be used on all sizes of data operands.
The multiply and divide operations are available for signed
and unsigned operands using word multiply to produce a long
word product, and a long word dividend with word divisor to
produce a word quotien with a word remainder.
Multiprecision and mixed size arithmetic can be accomplished using a set of extended instructions. These instructions are:
add extended (ADDX), subtract extended (SUBX), sign extend
(EXT), and negate binary with extend (NEGX).
A test operand (TST) instruction that will set the condition
codes as a result of a compare of the operand with zero is also
available. Test and set (T AS) is a synchronization instruction
useful in multiprocessor systems. Table 14 is a summary of
the integer arithmetic operations.

DATA MOVEMENT OPERATIONS

The basic method of data acquisition (transfer and storage)
is provided by the move (MOVE) instruction. The move instruction and the effective addressing modes allow both address
and data manipulation. Data move instructions allow byte,
word, and long word operands to be transferred from memory
to memory, memory to register, register to memory, and register to memory, and register to register. Address move instructions allow word and long word operand transfers and ensure
that only legal address manipulations are executed. In addition
to the general move instruction there are several special data
movement instructions: move multiple registers (MOVEM),
move peripheral data (MOVEP), exchange registers (EXG),
load effective address (LEA), push effective address (PEA),
link stack (LINK), unlink stack (UNLK), and move quick
(MOVEQ). Table 13 is a summary of the data movement
operations.
•

Description

MOVE
MOVEA
MOVEQ
MOVE from SR
MOVE to SR
MOVE to CCR
MOVE USP

Address
Quick
Immediate
with Extend

Instructions for the HD68000 contain two kinds of information: the type of function to be performed, and the location
of the operand(s) on which to perform that function. The
methods used to locate (address) the operand(s) are explained
in the following paragraphs.
Instructions specify an operand location in one of three
ways:
Register Specification - the number of the register is given
in the register field of the instruction.
Effective Address - use of the different effective address
modes.
Implicit Reference - the definition of certain instructions
implies the use of specific registers.
•

Variation

MOVE

INTEGER ARITHMETIC OPERATIONS

The arithmetic operations include the four basic operations
of add (ADD), subtract (SUB), multiply (MUL) , and divide
(DIV) as well as arithmetic compare (CMP) , clear (CLR), and
negate (NEG). The add and subtract instructions are available
for both address and data operations, with data operations
accepting all operand sizes. Address operations are limited
to legal address size operands (16 or 32 bits). Data, address,
and memory compare operations are also available. The clear

Table 13 Data Movement Operations
Instruction

Operand Size

EXG

32

LEA

32

EA~An

(An~SP@-;
SP~ An;
SP + d ~ SP

LINK

-

MOVE

8,16,32

MOVEM

16,32

MOVEP

16,32

Operation
Rx"'" Ry

(EA)s~

(EA)

~

(EA)

~

EAd

An, On
An,Dn~ EA
On

Dn~EA

#Xxx ~ On

MOVEQ

8

PEA

32

EA~

SWAP

32

Dn[31:16] ...,. Dn[15:0]

UNLK

-

(NOTES)
s = source
d = destination
[ I = bit numbers

eHITACHI

SP@-

( An~Sp;
SP@+ ~ An

@-

= indirect with

predecrement

@+ = indirect with postdecrement

627

H068000,H068000Y,H068000Z---------·-------------Table 14 Integer Arithmetic Operations
Instruction

Operand Size

•

Operation

16,32

On + (EA) ~ On
(EA+ Dn~ EA
(EA) + #Xxx ~ EA
AN + (EA)~An

ADDX

8,16,32
16,32

Dx+ Dy+ X~ Ox
Ax@-+Ay@-+ X

CLR

8,16,32

O~EA

8,16,32

On - (EA)
(EA) - #Xxx
Ax@+ - Ay@+
An - (EA)

8,16,32
ADD

CMP
16,32
32+ 16

Dn/(EA)

~

On

DIVU

32+ 16
8~ 16

Dn/(EA)

~

On

EXT

16~32

16*16 ~ 32

Dn*(EA)

~

On

MULU

16*16 ~ 32

Dn*(EA)

~

On

NEG

8,16,32

0- (EA)

NEGX

8,16,32

o - (EA) - X -

8,16,32

On (EA)
(EA)
An -

SUB
16,32

•

8,16,32

EA
EA

(EA) ~ On
- Dn~ EA
- #Xxx ~ EA
(EA) ~ An

•

(EA) -0

1 = bit number

15

14

13

12

11

REGISTER SPECIFICATION

The register field wi.thin an instruction specifies the register
to be used. Other fields within the instruction specify whether
the register selected is an address or data register and how the
register is to be used.

(EA) - 0, 1 ~ EA[7]

8

TST
[

~

PROGRAM/DATA REFERENCES

The HD68000 separates memory references into two classes: program references, and data references. Program references, as the name implies, are references to that section of
memory that contains the program being executed. Data references refer to that section of memory that contains data.
Operand reads are from the data space except in the case of the
program counter relative addressing mode. All operand writes are
to the data space.

Ox - Dy - X ~ Ox
Ax@- -Ay@- -X~Ax@

8,16,32

TAS

(NOTE)

Ax@

(Dn)s ~ Dn16
(On)16 ~ Dn32

MULS

SUBX

~

•

DIVS

INSTRUCTION FORMAT

Instructions are from one to five words in length, as shown
in Figure 51. The length of the instruction and the operation
to be performed is specified by the first word of the instruction
which is called the operation word. The remaining words
further specify the operands. These words are either immediate
operands or extensions to the effective address mode specified
in the operation word.

EFFECTIVE ADDRESS

Most instructions specify the location of an operand by using
the effective address field in the operation word. For example,
Figure 52 shows the general format of the single effective
address instruction operation word. The effective address is
composed of two 3-bit fields: the mode field. and the register
field. The value in the mode field selects the different address
modes. The register field contains the number of a register.
The effective address field may require additional information to fully specify the operand. This additional information,
called the effective address extension, is contained in the
following word or words and is considered part of the instruction, as shown in Figure 51. The effective address modes are
grouped into three categories: register direct, memory addressing, and special.

4
7
6
5
8
Operation Word
(First Word Specifies Operation and Modes)
10

9

3

2

1

0

Immediate Operand
(If Any, One or Two Words)
Source Effective Address Extension
(If Any, One or Two Words)
Destination Effective Address Extension
(If Any, One or Two Words)

Figure 51

Instruction Format

5

4

3
2
Effective Address
Mode
Register

Figure 52 Single-Effective-Address Instruction Operation Word General Format

628

eHITACHI

o

- - - - - - - - - - - - - - - - - - - - - - - H D68000,HD68000Y, H o68000Z
REGISTER DIRECT MODES

These effective addressing modes specify that the operand
is in one of the 16 multifunction registers.

Data Register Direct
The operand is in the data register specified by the effective
address register field.

EXAMPLE
MPU

COMMENTS
MEMORY

• EA

= On

• Machine Level Coding
MOVE DO, $1 FOO
10000ASCDI DO
0011

.
I
Move
Word

0001

1100

0000

Ilf,.,
Absolute
Short

MOVE DO, $1 FOO

OWL

31CO

OWL+2

1FOO

Data
Register
Direct

Address Register Direct
The operand is in the address register specified by the effective address register field.

EXAMPLE
MPU

1000012341 A4

COMMENTS
MEMORY

$201000 ~_....;,.=.~_~

• EA = An

• Machine Level Coding
MOVE A4, $201000
0011001111001100

~II~
OWL
OWL+ 2
MOVE A4,$201000

OWL +4

33CC

~--------j

0020

Word Absolute
Long
Address
Register
Direct

~--------j

1000

1---'------1

eHITACHI

629

H068000,H068000Y,H068000Z
EXAMPLE
MPU

COMMENTS
MEMORY

eEA = An
e Address Register Sign Extended
e Machine Level Coding
MOVE $201000,A4

IJ[-

1000012341 A4

0011

1000

0111

1001

~

Move
Word

Absolute
Long

Reg#4

Address
Register
Direct

MOVE $201000, A4

OWL

3879

OWL+2

0020

OWL+4

1000

MEMORY ADDRESS MODES
These effective addressing modes specify that the operand
is in memory and provide the specific address of the operand.

Address Register Indirect
The address of the operand is in the address register specified
by the register field. The reference is classified as a data reference with the exception of the jump and jump to subroutine
instructions.
COMMENTS

MPU

MEMORY

e EA = (An)

e Machine Level Coding
MOVE (AO). DO
0011

0001

0000

~lill~

1000010001 AO

Word

OWL

3010

1--------1

MOVE (AO), DO

630

0000

eHITACHI

Data
Register
Direct
Reg #0
ARI
(Address
Register
Indirect)

------------------------------------------------H D68000,H o 68000Y, HD68000Z
Address Register Indirect With Postincrement

The address of the operand is in the address register specified
by the register field. After the operand address is used, it is
incremented by one, two, or four depending upon whether
the size of the operand is byte, word, or long word. If the

address register is the stack pointer and the operand size is
byte, the address is incremented by two rather than one to
keep the stack pointer on a word boundary. The reference is
classified as a data reference.

EXAMPLE
MPU

1000001001 A4

MEMORY

$100

+

[000001021

COMMENTS
• EA = (An); An + M-An
Where An __ Address Register
M -1,2,or4
(Depending Whether
Byte, Word, or
Long Word)
• Machine Level Coding
MOVE (A4) +, $2000
0011

MOVE (A4) +,$2000

OWL

31DC

OWL+2

2000

Address Register Indirect With Predecrement

The address of the operand is in the address register specified
by the register field. Before the operand address is used, it is
decremented by one, two, or four depending upon whether
the operand size is byte, word, or long word. If the address

MPU

$OOFE
$0100

COMMENTS
• An - M-An; EA = (An)
Where An_Address Register
M -1,2,or4
(Depending Whether
Byte, Word, or
Long Word)
• Machine Level Coding
MOVE - (A3), $4000
0011

0001

1110

0011

IIa,=1

$4000

Move
Word

MOVE - (A3),$4000

1100

register is the stack pointer and the operand size is byte, the
address is decremented by two rather than one to keep the
stack pointer on a word boundary. The reference is classified
as a data reference.

MEMORY

t
1000000FEI

1101

Move
Word Absolute
Short
AR I with
Increment

EXAMPLE

1000001001 A3

0001

IIr

$2000

OWL

31E3

OWL+2

4000

$

HITACHI

Absolute
Short

with
Predicrement

Reg #3

631

H068000,H068000Y,H068000Z----------------------Address Register Indirect With Displacement
This address mode requires one word of extension. The ad·
dress of the operand is the sum of the address in the address

MPU

register and the sign-extended 16·bit displacement integer in
the extension word. The reference is classified as a data refer·
ence with the exception of the jump to subroutine instructions.

MEMORY

$1100~_---.,;_ _~

1000010001 AO

$3000 . . - - - - - - l

MOVE $100(AO),$3000
ADDRESS
CALCULATION:
AO = 00001000
d. 6 = 00000100
00001100

MOVE $100(AO),$3000

I

$1000~_ _ _ _-l"\

1000020001 AO
$4BEO I - - - - - - - - l

I
Reg #0

COMMENTS
• EA = An + Rx + d.
Where
An _
Pointer Register
Rx Designated Index Register,
(Either Address Register or
Data Register)
d. _
8-Bit Displacement
• Rx & d. are Sign Extended
• Rx may be Word or Long Word
Long Word may be Designated with Rx.L
• Machine Level Coding
MOVE $04(AO, DO), $1000
0011

---=r-

632

1000

ARI
with
Displacement

Move
Word

Move
Word

ADDRESS
CALCULATION:
AO = 00002000
DO = 00002BDC
d = 00000004
00004BEO

1110

eight bits of the extension word, and the contents of the index
register. The reference is classified as a data reference with the
exception of the jump and jump to subroutine instructions.

MEMORY

MPU

MOVE $04(AO. DO),
$1000

0001

-=r=- t

Absolute
Short

OWL t-_...;;3..;,1...;;E~8_--l
OWL + 2
0100
t-------l
OWL +4
3000
t-------l

Address Register Indirect With Index
This address mode requires one word of extension. The
address of the operand is the sum of the address in the address
register, the sign-extended displacement integer in the low order

100002BDCI DO

COMMENTS
• EA = An + d. 6
Where An -Pointer Register
dl6 -16-Bit Displacement
• dl6 Displacement is Sign Extended
• Machine Level Coding

OWL
OWL+2

.=r:::=-yI.0001

31FO
0004

t-----~

0000

HITACHI

0000

olTwlral
Reg #0

$

0000

Reg #0

ARI
with
Index

I-----~

OWL + 4 ~_ _
10.;.0;..;0~_-I

1111

Absolute
Short

0000

0100

~

Constant Zeros

------------------------H068000,H068000Y,H068000Z
SPECIAL ADDRESS MODE

Absolute Short Address

The special address modes use the effective address register
field to specify the special addressing mode instead of a register
number.

This address mode requires one word of extension. The address of the operand is the extension word. The 16-bit address
is sign extended before it is used. The reference is classified
as a data reference with the exception of the jump and jump
to subroutine instructions.

MPU

MEMORY

COMMENTS
• EA = (Next Word)
• 16·Bit Word is Sign Extended

• Machine Level Coding
NOT.L $2000
0100
$2002

0110

t

1--------1

Not Instruction

NOT.L $2000

OWL
OWL + 2

1000

Short

46B8

1---------1
2000

EXAMPLE
MPU

1011

t.w~
Absolute

MEMORY

$1000

COMMENTS
• EA = (Next Word)
• 16·Bit Word is Sign Extended

• Machine Level Coing
MOVE $1000, $2000
0011

--...r-

$2000

Move
Word

0001

1111

1000

I~
Short

Absolute
Short

MOVE $1000, $2000

OWL

31F8

OWL+2

1000

OWL+4

2000

~HITACHI

633

H068000,H068000Y,H068000Z----------------------Absolute Long Address

This address mode requires two words of extension. The
address of the operand is developed by the concatenation of
the extension words. The high-order part of the address is the

MPU

first extension word; the low-order part of the address is the
second extension word. The reference is classified as a data
reference with the exception of the jump and jump to subroutine instructions.

MEMORY

$14000

1--------1

COMMENTS
• EA = (Next Two Words)

• Machine Level Coding
NEG $014000
0100

0100

0111

1001

--=r.-be~
NEG
Absolute
Instruction

OWL
NEG $014000

OWL + 2
OWL +4

4479
0001

1--------1

4000

1--------1

Program Counter With Displacement

This address mode requires one word of extension. The
address of the operand is the sum of the address in the program
counter and the sign-extended 16-bit displacement integer in

MPU

Lbng

the extension word. The value in the program counter is the address of the extension word. The reference is classified as a program reference.

MEMORY

COMMENTS
• EA = (PC) + d , •
• d '6 is Sign Extended
• Machine Level Coding
MOVE (LABEL), DO
0011

0000

0011

1010

I Lbth
Move
Word

MOVE (LABEL), DO
ADDRESS
CALCULATION:
PC = 00008002
d = 00001000 $9002
00009002
1--------1

634

~HITACHI

Dat~
Register
Direct

Displacement

------------------------HD68000,HD68000Y,HD68000Z
Program Counter With Index
This address mode requires one word of extension. This
address is the sum of the address in the program counter, the
sign-extended displacement integer in the lower eight bits of
the extension word, and the contents of the index register.
The value in the program counter is the address of the extension
word. This reference is classified as a program reference.

EA = (PC)

+ (Rx) + d.
(NOTE)
PC Value ......._ _ _ _ _-/

Extension Word
654

3

o

Displacement Integer
Beginning }
PC + d. Address of
Data Table
Desir,,:d Data
} PC + d + R x _
Location In Table
•

D/A
: Data Register = 0, Address Register = 1
Register: Index Register Number
W/L
: Sign-extented, low order Word integer
in Index Register = 0
Long Word in Index Register = 1

Data
Table

MEMORY

MPU

COMMENTS
• EA = (PC) + (Rx) + dB
Where
PC-Current Program Counter
Rx_Designated Index Register
(Either Data or Address Register)
dB -8-Bit Displacement
• Rx and dB are Sign Extended
• Rx may be Word or Long Word
Long Word is Designated with Rx.L
• Machine Level Coding
MOVE (LABEL) (AO), DO

0011

-----.rMove
Word

0000

0011

1011

~- P~With
~Index

Data Register
Direct

oO

lIT 9OT ~

MOVE (LABEL) (AO), DO

Address
8-Bit Displacement
Register
.L._ _-..,.~_
Register
Constant Zeros
Number
0:1n=-=df-e":"x'L:-:e-=-ngC:::t:L'h

ADDRESS
CALCULATIONS:
PC = 00008002
AO=00001010
d = 00000010
00009022

$

HITACHI

635

H068000,H o68000Y, Ho6 8 0 0 0 Z - - - - - - - - - - - - - - - - - - - - - - - - Immediate Data
This address mode requires either one or two words of extension depending on the size of the operation.
Byte operation - operand is low order byte of extension
word
Word operation - operand is extension word
Long word operation - operand is in the two extension
words, high-order 16 bits are in the first extension word,
low-order 16 bits are in the second extension word.

MPU

MEMORY

Extension Word

o

8 7

15

10 0 o

0

0

0

0

0:I

Byte

o

or

15

Word

t----

or

15

0

Long Word ________ Iji!!.h_q,r
-(SSP)
< INT ACK>
-(SSP)
-(SSP)
(VR)
+(VR)
(PC)
+(PC)

CMP

SGE

+(PC)
+(PC)
xxx
+(PC)
yyy
+(PC)
+(PC)

xxx Low
yyy High

yyy Low

NOP
SWAP

0

PC Low
Vector #
SR
PC High
PC High
PC Low
MOVE
xxx High

Instruction Prefetch Example

• DATA PREFETCH

Normally the HD68000 prefetches only instructions and not
data. However, when the MOVEM instruction is used to move
data from memory to registers, the data stream is prefetched in

A
B
C
0
E
F

Location

Operation
Read
Read
Read
Read
Read
Read

Read

PC=PC+d
Read
Read

Read
Read
Read

Write
Read
Write
Write
Read
Read
Read
Read

Read
Read
Read
Read
Write
Read
Read


Reset

order to optimize performance. As a result, the processor reads
one extra word beyond the higher end of the source area. For
example, the instruction sequence in Figure 55 will operate as
shown in Figure 56.

A,DO/D1

MOVE TWO
LONGWORDS
INTO REGISTERS

Assume Effective Address Evaluation is Already Done

MOVEM.L
DC.W
DC.W
DC.W
DC.W
DC.W
DC.W

1
2
3
4
5
6

WORD 1
WORD 2
WORD3
WORD4
WORD5
WORD6

MOVEM

Microroutine

Figure 55 MOVEM Example, Memory Contents

Operation

Location

Read

A

Read
Read

B
C

Read
Read

0
E

Other Operations

Prepare to Fill DO
A-+DOH
B-+DOL
Prepare to Fill 01
C-+D1H
D -+D1L
Detect Register List Complete

Figure 56 MOVEM Example, Operation Sequence

~HITACHI

645

HD68000,HD68000Y,HD68000Z-----------------------Table 25

..........
Operation

AICO
AddDleits
ADO
Add
Sonary
ADOA
Add Address
ADOI
Add Immed
ADOG
Add Quick
ADDX
Add Multi'
preCISion

AIID
loelCal",d
AIIDI
"'d Immed
AIL. AlII
Arithmet"
Shilt
Memory
ICNG
Test and
Olanee
ICLII
Test and
Cear
lilT
Test and
Set

ITiT
Bit Test
CNII
OleckRee

AIIIIr.

II

-

B s,1),
d· 2
d·
s'("')
B'II s,1),
d.
d,1),
s 2
l s'DI
d
s 2
d'DI
II d''''
s 2
l d''''
s 2
B'II s,lmm
d 4
l s=lmm
d 6
Bill s'lmm3
d 2
l s'lmm3
d 2
Bill s.1),
d 2
d,
s' ("')
d. 2
l s'DI
d·
S' ("')
B'II s'DI
d
d'DI
s· 2
d
l s·DI
d,DI
s· 2
Bill s'lmm
d 4
l sdmm
d· 6
d, 2
8 /11 counl'l),
count,III-8d, 2
d. 2
L counteDI
count'III-8d' 2
d,
II counl'l
d,
B bitll'DI
bitll'lmm d.
d· 2
L bitll'DI
bitll'lmm d. 4
d.
B bitll'DI
bitll'lmm d.
d. 2
L bitll'DI
bitll'lmm d. 4
d.
8 bitll'DI
bitll'lmm d.
d. 2
L bitll'DI
blllI'lmm d. 4
d,
B bit 11,1),
blllI'lmm d.
d,2
L blllI'Dn
bltll'lmm d,4

6

II

deDI

IsterAgamst

Ibunds
CLII

An

On

......

II-

s· 2
(bound)

4
8
8
8
8
16
4
8
4

-

II

L

2'1 4
IOOA
8
8
8
AOOA
AOOA
2'
4
2 8

~I

(An)

(An) +

-(An)

deAn)

Instruction Set

d(An.Xi) Abs.W

Abs.L

II

-

II

-

II

-

II

-

II

-

II

-

II

-

2
2
2
2
2
2
4
6
2
2

12
8
20
14
12
14
16
28
12
20

2
2
2
2
2
2
4
6
2
2

12
8
20
14
12
14
16
28
12
20

2
2
2
2
2
2
2
4
6
2
2

18
14
10
22
16
14
16
18
30
14
22

4
4
4
4
4
4
6
8
4
4

16
12
24
18
16
18
20
32
16
24

4
4
4
4
4
4
6
8
4
4

18
14
26
20
18
20
22
34
18
26

4
4
4
4
4
4
6
8
4
4

16
12
24
18
16
18
20
32
16
24

6
6
6
6
6
6
8
10
6
6

20
16
28
22
20
22
24
36
20
28

2

18

2
2
2
2
2
4
6

30
14
10
22
16
18
30

d(PC)
II

-

d(PC.Xi)
II

-

2
2
2
2
4
6

8
8
16
6+20
6+20
8+20
8+20

12
8
20
14
16
28

2
2
2
2
4
6

12
8
20
14
16
28

4
4
4
4
6
8

16
12
24
18
20
32

4
4
4
4
6
8

18
14
26
20
22
24

4
4
4
4
6
8

16
12
24
18
20
32

6
6
6
6
8
10

20
16
28
22
24
36

2'
2
4

12
12
16

2'
2
4

12
12
16

2'
2
4

14
14
18

4'
4
6

16
16
20

4'
4
6

18
18
22

4'
4
6

16
16
20

6'
6
8

20
20
24

4

12

4

14

4

8

4
4
4

18
16
18

4
4
4

20
18
20

6
4
6

14
12
14

1100
1100
1101
1101
1101
1101
1101
1101
0000

2
4

12
16

2
4

12
16

2
4

14
18

4
6

16
20

4
6

18
22

4
6

17
20

6
8

20
24

4
6

16
20

4
6

18
22

4
6

16
20

6
8

20
24

4
6

12
16

4
6

14
18

4
6

12
16

6
8

16
20

2
4

12
16

2
4

12
16

2
4

14
18

2
4

8
12

2
4

B
12

2
4

10
14

10

.lo-

<44
2

<46

<44
2

14

<48
4

2
16

14

<50
4

<48
4

20

18

d.+-#-d

d- s +X 'd

SSIO
SSOO
1010
1000
IIEE
01EE
01EE
01EE
01 EE
10EE
IDEE
1OEE
10EE
11 EE
11EE
11EE
IIEE
OOEE
OOEE
OOEE
OOEE
IOee

~:::r£?-0

8

4

18

4

20

6
4

14
20

<44

1110 rr rI
1110 QQQI
II 10 rr rf
1110 QQQI
1110 0001
0000 r rr 1
0000 1000
0000 rr r 1
OOOG 1000
0000 rr r 1
0000 1000
0000 rr r 1
0000 1000
0000 rr r I
0000 1000
0000 rrr I
0000 1000
0000 rr r:
0000 1000
0000 rr r 1
0000 1000
01000001

<52

<50

<48
4

6

4
18

22

18

SSEE EEEE

4

14
18

4
20

0000
0000
0000
0000
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
eeee

Bill

d,2
d,2
s,2
s,2

4
6
4
6

2'
2

2
s' 2

6
6

2
2

-5=

d' 4
d, 6
d
d·

8
14

dDI-d
DIs'-DI
dDI-d
DIs-DI
dlI-d

~i
-(bitJlI old-Z,
-(bit)1I ot d(bit) II 01 d

C...tl.
C.....
XNZVC

.....
.....
.....
.....
.U.U*

-----

- "0 0

.....
-"00

--.--

-(bit)#ol d-Z.
1-(biI) II old

-.-- -.--

-(bit)# 01 d-Z

- --

111),<0. or
DI>(bound).

-.U U U

-(bitJ# old-Z.
O-(bit)1I 01 d

-

-.

then trap

14

trap

Cear~erand
L
Bill d,1),
ClIP
(l)mpare
L d,1),
Sonary
II d,'"
C..'A
(l)mpare
l d,'"
Address
Bill s,lmm
CIIPI
(l)mpare Imm L s:lmm
Bill s'("') +
C"'"
(l)mpare
L s'("') +

'" .s-",

Ilee tete

SSOOOrrr
SSOO I rr r
1000 Orr r
1000 I rr r
SSEE EEEE
SSte eeee
10EE EEEE
IOeeeeee
SSEE EEEE

14

4
6

I DEE EEEE
IOee teee
lite eeee

~d

d+1), ~d
Dlts-DI
d.DI-d
DI's-DI

0101 QQQO

4

12
16

SSet eeee

dIO+sIO+X

d·lI-d

12

4
6

0000 Orr r
0000 1 rr r
SSEE EEEE

SSEE EEEE

4

<8
<12
6
10
<40 -trap--

RRRI
RRRI
DD01
DODO
DODO
0001
AAAO
AAAI
0110

1101 RRR I
1101 RRR I
1101 RRRI
1101 RRR I
1100 0001
1100 DODO
11000001
1100 DODO
0000 00 10

<8
<12
<10
<14

....

-

8
4

-

s-Immed
Opo.... lit ,.uun
d=SR/CC
1111 11
II
5412 Itll 7114 1211

....
....
....
....

d-MPU
D-d
DI-s

-

Ilee eeee

"'-5

-

0000 1100

SSEE EEEE

d-#

-

10 II RRRI

SSOO 1 rrr

d-s

-

Dl32/s16DI(rq)
Dl32 / s16DI(r:q)

- ••• 0

2
2
2
2

12
20
8
14

2
2
2
2

12
20
8
14

2
2
2
2

14
22
10
16

4
4
4
4

16
24
12
18

4
4
4
4

18
26
14
20

4
4
4
4

16
24
12
18

6
6
6
6

20
28
16
22

0100 00 10

SSEE EEEE

4
6

4
4

12
18

4
4

14
20

4
6

8
14

1011 DODO

55et eeee

6
6

2
2

10
14

2
2

10
14

2
2

12
16

4
4

14
18

4
4

16
20

4
4

12
18

6
6

18
22

4
4

14
18

4
4

16
20

4
6

10
14

1011 AAAO
1011 AAAI

Ileeteee

()1PA
()1PA

4
6

12
20

4
6
2
2

12
20
12
20

4
6

14
22

6
8

16
24

6
8

18
26

6
8

16
24

8
10

20
28

- 0100

Memory
II
DIVI
DlVldeSiened
II
DIVU
DIVIde
l)1S1ened
Bill
1011
Exclusivem
L
Loe"al
8f W
0111
Exclusive OR L

d,DI

s. 2 <158

2 <162 2 <162 2 <164 4 <166 4 <168 4 <166 6 <170 4 <166 4 <168 4 <162

1000 0001

Ilee eeee

d,DI

s· 2 <140

2 <144 2 <144 2 <146 4 <148 4 <150 4 <148 6 <152 4 <148 4 <150 4 <144

1000 DODO

Ilee eeee

s,1),

d. 2
d. 2

4
8

2
2

12
20

2
2

12
20

2
2

14
22

4
4

16
24

4
4

18
26

4
4

16
24

6
6

20
28

10 II rr rl

SSEE EEEE

del),-d

-"00

4
6

16
28

4
6

16
28

4
6

18
30

6

20
32

6

8
10

24
36

SSEE EEEE

de#-d

-.'00

8

20
32

0000 1010

8

22
34

6

8

111000001
11100 AAAI
11000001
0100 1000
0100 1000
0100 AAAI

0100 0000
0100 1AAA
1000 1AAA
1000 0000
1100 DODD
Ileeeeee

s-d

-----

"I),

d. 4
d. 6

8
16

L s,DI
s,'"

d· 2
d· 2

6
6

II

d, 2
d, 2
s'

4
4

s:lmm
s:lmm

Immediate

IXG
Exchanee

2

4

20

6

Registers

IXT
SienExtend
LEA
Load Eflect

L
L d.'"

2

4

4

8

4

12

4

8

6

12

4

8

4

12

bit 7-biI8-15
bit1~bltI6-31

S-M

iveAddress

UIII
link and
llliocale

dispJmm

s'

Note: Refer to~Condilion Code Computations
as for COndition Code
• Word only
<;Maximum value
#; Number of Pr08ram Bytes
-: Number of Clock Periods

4

16

0100 1110

0101 OAAA

- "'0

"'--(SP)

-'.00

-----

___ e.

SP-'"

SP+disp~SP

Opcode Bit Pattern Key
A; Address Register #
C; Test Condition
D;Oata Resister #
e;Source Effective Address
E; Destination Effective Address

f : Direction; 0- Right. 1- Left
M; Destination EA Mode
P; Displacement

Q: Quick Immediate Data
r; Source Register

R. Destination ReBlster
S. Size: 00 - Byte
01 - Word
10-long Word
II-Another Operatton
V,Vector :If:

[

In the MOVE Instruction]
01 ~ Byle
1O~ lon3 Word
II"Word

(to be continued)

646

eHITACHI

------------------------HD68000,HD68000Y,HD680002

.........

.....

On

Milr.

()peration II.

-

d,
d,
d'
d,
d,
d,

2
2
2
2

6+20
6+20
8+20
8+20

2

"
d'

2
2

d'
d,
d
d'
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
5

2
2
4
4
4
6
4
4
4
2
2
2
2
2
4
4
4
6

?

4
4
8
8
10
12
14
12
16
12
14
8
4
4
12
12
14
16
18
16
20
16
18
12
12

W dSR
Move to from
sSR
Slalu,Rel
l ,USP
IIOVE

5
d

1
1

11
6

MovE' to from

5

B'II count,1)!
counl, 111-8
l counl,o,
counl, 111-8
W countt
B'W "I)!

LIl, " .
lOIIe.ISlllft
Memory

IIOVE
Mo,e Dal.

"lei
,,(lei)
,'(lei),
, (lei)

"d(IeI)
,d(IeI,X)
,'Ab,W
,Ab,l
,d(Ft)
,d(Ft,X)
s Imm

l

"I)!
,lei
,(lei)

,,(IeI)(lei)
,d(IeI)
,d(IeI,XI
, Ab,W
,Ab,l
,d(FtI
,d(Ft,XI
;) Imm
W da:R

IIIIVI

4

4
6

(An)

AIt

II

II

-

MMA
MMA
M"'EA
MMA
MMA
MOYEA
MOYEA
MOYEA
M"'EA
MOYEA
MOYEA
M"'EA
MOVEA
M"'EA
fOEA
M"'EA
MOYEA
M"'EA
M"'EA
M"'EA
MOYEA
MOYEA
M"'EA
MOVEA

II

-

-(AIt)

(AIt)+
II

-

II

-

d(AIt)
II

4
6
1

12 2'
2
8
2
8
12 2
12 2
14 2
16 4
18 4
16 4
20 4
16 4
18 4
12 4
12 2
12 2
20 2
20 2
22 2
24 4
26 4
24 4
28 4
24 4
26 4
20 6
16 1

12 2'
8
2
8
2
12 2
12 2
14 2
16 4
18 4
16 4
20 6
16 4
18 4
12 4
12 2
12 2
20 2
20 2
22 2
24 4
26 4
24 4
28 6
24 4
26 4
20 6
16 1

144'
8 4
8 4
12 4
12 4
14 4
16 6
18 6
16 6
20 8
16 6
18 6
12 6
12 4
12 4
20 4
20 4
22 4
24 6
26 6
24 6
28 8
24 6
26 6
20 8
18 4

1
1

16
12

16
12

18
14

2'
2
2
2
2
2

4
4
4
6
4
4
4
2
2

,
2
2
4
4
4
6
4

1

-

d(An.Xi) Abs.W
II

16 4'
12 4
12 4
16 4
16 4
18 4
20 6
22 6
20 6
24 8
20 6
22 6
16 6
16 4
16 4
24 4
24 4
26 4
28 6
30 6
28 6
32 8
28 6
30 6
24 8
4
20

-

II

18 4'
.14 4
14 4
18 4
18 4
20 4
22 6
24 6
22 6
26 8
22 6
24 6
18 6
18 4
18 4
26 4
26 4
28 4
30 6
32 6
30 6
34 8
30 6
32 6
26 8
12 4

-

Abs.L

-

II

16 6'
12 6
12 6
16 6
16 6
18 6
20 8
22 8
20 8
24 10
20 8
22 8
16 8
16 6
16 6
24 6
24 6
26 6
28 8
30 8
28 8
32 10
28 8
30 8
24 10
20
6

20
16
16
20
20
22
24
26
24
28
24
26
20
20
20
28
28
30
32
34
32
36
32
34
28
14

20
16

14
20

d(PC)
II

-

d(PC.Xi)
II

-

-

,att....

I-Immod
........ lit
d=SR/CC 111111
II
5432 1098 76543210

....

-

1II0rrrf
I I I 0 QQQI
I I 10 rr rf
I I 10 QQQI
11100011
OOSS RRRM

S510
S500
1010
1000
I lEE
MMu

1000
1000
1000
1000
EEEE
teet.

~:r£?-O
O~~

dUSP

U,erSP(A7l

.OVIA
Move .tddress

IIOVE.

W dlcl
l dlel
W ,Xn

Move Multiple
Registers

5
d

4
4

2
2

4
4

2
1

4
4

1
1
8
1 12 1
48·4n

4
4

s

4 11·4n 411·4n

d

48·Bn

d,Xn

5

4 12·Bn

W ,I)!

d
d
d
d
d

4
2

W dl)!

,

2 • ;0

2

·14

W dj),

,

1

10

1

<'

d

1

6

2

11

2

11

2

14

4

d
d
d
d

1
2
2
2

4
6
4
6

2
2
2
2

12
20
12
20

2
2
2
2

12
20
12
20

2
2
2
2

14
22
14
22

4
4
4
4

d
d

2
2

4
6

2
2

12
20

2
2

12
20

2
2

14
22

4
4

,d
d
,

4

2
2
2
2
4
6
2

12
8
20
14
16

1
2
2
2
4
6

12
8
20
14
16

1
2
2
2
4
6

14
10
21
16
18
32

4

2

,d(IeII
l

.OVEO

l

,()l

,d(IeII
s ImlTl8

4

20
16

4
4

11
18

4
4

6
6

4

20

4

22

4

16

01000100

lief eeH'

, -COl

4

20

4

12

4

16

01000110
01000000

lief f'f'eE'
II EE EEEE

, -SR

01001110
0100 II 10

0110 IAAA
0110 OAAA

0011 AAAO
0010 AAAO
01001000
.7 ,0
0100 I 100
.7-,0
01001000
,7-,0
01001100
.7-,0
0000 DDDI
OOOODDDI
OOOODDDI
0000 DDDI
oII I DDOO

Olu eeee , -lei
Olu eeee
10EE EEEE Xn-d
d7-dOr
10 ee eeee S "Xn **
d7-dO
II EE EEEE Xn -d
d7- dOt
lite teee S "Xn ••
d7-dO
1000 IAAA I)! -dby byle,
0000 IAAA s -I)! by byle,
1100 IAAA I)! ·d by byle,
0100 IAAA "{)lbybyle,
QQQQ QQQQ :: -()l

1100 DOD I

llt'e

1100 DDDO

2
10 4
12 4 14 4 11 6 16 4
4
14 4 16 4 18 4 16 6 20
2
418.4n 6 12-4n 6 14-4n 6 12·4n 8 16-4n

8
11

5Xn

Move
Peripheral

Move Cbck
MULS

,

1
1

1
1

dXn
l

IIOVE'

d

1
2

12
16

4
4

14
18

4
6

8
12

6 16·4n 6 18·4n 6 16·4n 8 20·4n 6 16-4n 6 18·4n
41 88n

611·8n 614·8n 611-8n 81!-8n
6 16·Bn 6 18·Bn 6 16·Bn 8 2O-Bn 6 16-Bn 618-8n

41i·Bn

4

16

4

24

16
14
4
2

·14

2 <'16

4 ' 18

4 <'SO

4 <'18 6

<82

4 <18

4 I)!··d
ll1s'-1lI

- •• 00

0100 1000

Olu

t't't't'

I II 0 rrrf

55 II 1000

1110
1110
I I 10
I I 10

5501
1011
1001
I lEE

('t'tt'

Muiliply

SlIned
IIIILU

<

14 2 <14

<18 6

Multiply
lk1slgned

8
I.CD
Nelale DlIII
BW
IIG
Nolaleanary l
BW
1111
Nolate Mull.
l
preCISion

lOT
LOllcal

BW
l

.....
.....
.U.U.

Complement

.1
Inch,slveCl'
logical

B W "I)!
dj),
l ,()l
d,{)l
.11
B W "Imm
(J! Immedoale
l s·lmm
l
'IA
l'IJ,hElfecl

d

,d

1
4
6

8
8
16

:.J

:.J

14

4

4
4
6
8
4

4

4
4
6
8
4

6

6
6
8
10
6

4

12

4

14

4

8

4

18

4

20

6
4

14
20

4

18

4

12

IveAddress

.... IIL
~1.le

Without X
Memory

B'W counl,1)!
counl, 111-8
l count:1lI
counl, 111-8
W count:)

d' 2 6+2n
d 2 6+20
d, 2 8+20
d~ 1 8+20
d,

2'

Note: Refer toWCOnditlon Code Computations
as for condition Code

*:Word only

< ;M•• imum

value

0:; Number of P'OIIram Bytes
-;Number of Clock Periods

11

l'

12

2'

14

4'

16 4'

18

4'

16 6'

20

QQQI
rrrf
QQQI
01 If

1000
JOOO
1000
EEEE

dl)!~d
l)!,~1)!

dlI~d

- •• 00

,~·(SP)

-----

GErc

- •• 00

c~

Opeode Bit PaHem Ke,
A;Address R'lister #
C; Test Condition

O;Oala Re"ster #
e;Source Effective Address
E;Oestination Effective Address

t; Direcllon; O-Rilht, I-lett
M:Oestination EA Mode
P. Displacement
Q: Quick Immediate Data
r:SOl.Irce R'lister

R: Destination Relister
S;Size:OO-Byte
Ol-WOt'd
IO-Lon, Word
ll-AnottMr ()peration
V:Vector #:

I" the MOVE Instruction)
Ol-Byte
( lO-lone Word
ll-Word

•• : The MPU goes through an extra
null read cycle aft4lt'. muttipkt reed is done IThe last EA+2).

(to be continued)

eHITACHI

647

H068000,H068000Y,H068000Z-----------------------

-

An

On

AMr.

..

II

IDU,IDIL B • count· ()I
d, 2
fbtat.
count.III-8d, 2
thrOUlh X
L count,()I
d, 2
count·2%1-8d, 2
Memory
count'l
d,
,,()I
d,2
S.CD
,. (Ifl)
d,
Subtract
dillt'
Sec
8 cc
d' 2
Set
Cllndltlonally
d,
BIIS'()I
SUI
Subtract
2
"'()I
d,
Binary
L .. ()I
2
"'()I
IU••
2
"'Ifl
2
Subtract
d'Ifl
Address
SU.I
d
B II "Imm
d·
Subtract
L "Imm
Immediate
SUM
d·
8 II "lmm3
Subtract
L "lmm3
d'

-

II

(An)

-

2%

-

- (An)

deAn)

d(An.Xi) Abs.W

Abs.L

d(PC)

d(PC.Xi): :~Rm/~

111't.I~ • •11

II

2%

II

II

II

2%

2%

S4321098

76S4 3210

1110
1110
1110
1110
1110
1000
1000

5SIIODOO
550 I 0000
1011 0000
100 I ODDD
IIEE EEEE
0000 Orr r
0000 I r rr dlO ,10 X 'd

-

-

-

-

II

-

-

-

-

2%

-

6 + 20
6+20
B+20
8+20
2'

2

64

12

12

......

(An) +

l'

2

12 l '

12

144'

1

18

2

14

4

164'

184'

166'

20

16

18

16

20

4

4

6

rrrl
QQQI
rrrl
QQQf
a I 01
RRR I
RRR I

a 10 I ecce

'.nl'"

C.... II..
C....
XNZVC

[~x~
~x~J

II EE EEEE

d -.MPU

It cctrue.l's "d

Else. 0', 'd

,.

4

8

12
8
20
14
12
14

12
8
20
14
11
14

14
10
22
16
14
16

16
12
24
18
16
18

18
14
26
20
18
20

16
12
24
18
16
18

SUBA
SUBA

16
28

16
28

18
30

20
32

22
34

20
32

\0

12
16

12
16

14
12

16
24

18
26

16
24

6
6

SU!A
2'1 4
SU!A
8

~I

,."

"

8

16

8

2'
2

20
16
28

OODI
0000
0001
DODO
HAO
AAA I

55EE EEEE d()l'd
SStt t t t t ()I, .()I
10EE EEEE d[)J 'd
10tt t t t t ()I, .()I
Iitt t t t t Ifl' -Ifl
lit. f t t t

24
36

00000100

55EE EEEE d :: -d

20
28

a 101 llQlll

55EE EEEE d :: -d

100 I
100 I
100 I
1001
0100

5500
5500
1000
1000
0100

4

n

4

20

14

8

4

14
11
14

20
18
20

18
16
18

n
8

12

100 I
100 I
1001
100 I
1001
100 I

*****

*****

()lICk

SU'.
Subtract
MultlpreCls~n

B II ,,()I
,. (Ifl)
L

s:{),

,. (Ifll
SWAP
Swap RegIS·
ter Halves
TAS
Test.ndSeI
(\Ierand
TIT
BII
Test
L

d·
d,
d·
d·
d·

d

2
2

2

18

2

30

8

2

14

2

8
12

Will
'--'hnk

2

14

2

8
12

16

4

18

4

20

4

14
18

\0

14

18

6

12
16

Orr
I rr
Orr
I rr

r d,X 'd
r
r
r
ooon [)J(j1161' [)J(1501

22

0100 1010

I lEE EEEE tesfd ·C(
I -blt7ofd

16
20

a100

SSEE EEF.E tesld 'cc

12

1010

a 100 1110

dlsP=

Branch
Cllndltlonally

bra
bra not
bra
bra not

dISP

10
8

taken
taken
taken
laken

dlSo,lmm
counter, 4

co

ICoUnter

I :~.

false
true

'I
~ 1

114

lalse

expired

ecce

- •• 00

PPPP PI'I'P

-Ifl

cc true
PC-dl'p 'PC

II

\0

14

.IA
Branch
oIIw.ys

.11

a II 0

- •• 00

0101 IAH Ifl .sp
(SP)·

.eo

Branch
to Subroutln,
D•••
Decrement
Counter. &
Branch '--'tit
CllndlllGn

RRR I
RRR I
RRR I
RRRI
1000

\0
\0

0110 0000

I'PPP I'PI'P PC-dISP 'PC

2

20

0110 0001

I'I'I'P I'PPI' PC' (sp)
PC-d',o -PC

4

20

'rlnch
ye'

a 10 I

ecce

1100 1000 If cc false
()I I .()I & If
[)J, I.PC-dlSo-PC
Else rtJ>

True or
Cllunt'l
IMP
limp to
lSI
limp to
SubroutIne
lOP
"'Iller.tion
liS IT
Reset Exler·
n.IDevices
III
Return lrom
Exception
ITII
Relurn lrom
Subroutine'
Reslore a:
I'll
Return Irom
Subroutine
STII'
Load SR'Stop
TIIA'
Tr.p

4
1

of Program Bytes
-; Number of Clock Periods

648

4

14

4

10

6

11

4

10

4

14

0100 1110

I lEE EEEE d 'PC

18

4

22

4

18

6

20

4

18

4

11

0100 1110

I OEE EEEE PC - (SPld'PC

0100 1110

all I 0001

132

0100 1110

all I 0000 assertRESEToon

2

10

a100

1110

0111 0011

(sp)(sp)-

·SR
'PC

1

20

0100 1110

01110111

(SP)+
(SP)-

-PC

2

1

Note: Refer toWCondition Code Computations
as tor condition Code
• Word only

#; Number

10

1

TIIAPY
Tr.pil
0..,110. Sel

<:M,.imum value

16

16

-(l;

0100 1110

0 III a t a I (SP)" .pc

0100 1110

aIII
a100

34

0100 1110

34 Tr.pt.ken
4 Tr.pnot
takf

0100 1110

0010

II ·SR.... t for
Interrupt

VVVV PC' (SSP)
SI!-~ (SSP)
(Vector) .pc
aIII 0110 IfHIIonPC·
(SSP)SR'(SSPl
(TRAPVwe<1ad -PC
IIOP

~ ...

Opcode Bit Pattern Key
A: Address ReSister

#:

C; Test Condition
0; Data Register #:
e;SOLtrce Effective Address
E;Oestination Effective Address

f : Oirection; 0- Right. ]- Left
M; Destination EA Mode
p; Oisplacement
Q: QuiCk Immediate Data
r:Source Register

•

HITACHI

R; DestinatIon Register
S. Size: OO-Byte
01 - Word

IO-Long Word
It-Another Operation
V;Vector :

In the MOVE InstructIon]
Ol-Byte

( IO-Long Word
11--Word

.....
.....

-----------------------H068000,HD68000Y,H068000Z
•

INSTRUCTION FORMAT SUMMARY

instructions according to the op-code map.
where, Size; Byte = 00
Sz; Word = 0
Word = 01
Long Word = 1
Long Word = 10

This provides a summary of the first word in each instruction
of the instruction set. Table 26 is an operation code (op-code)
map which illustrates how bits 15 through 12 are used to
specify the operations. The remaining paragraph groups the

Table 26 Operation Code Map
Bits
15 thru 12

Operation

0000

Bit Manipulation/MOVEP/lmmediate

0001

Move Byte

0010

Move Long

0011

Move Word

0100

Miscellaneous

0101

ADDO/SUBO/See/DB ee

0110
0111

Bee
MOVEO

1000

OR/DIV /SBCD

1001

SUB/SUBX

1010

(Unassigned)

1011

CMP/EOR

1100

AND/MUL!ABCD/EXG

1101

ADD/ADDX

1110

Shift/Rotate

1111

(Unassigned)

(1) BIT MANIPULATION, MOVE PERIPHERAL, IMMEDIATE INSTRUCTIONS
Dynamic Bit
15

14

13

11

12

9

10

8

6

0

4

5

Effective Address

Register

Static Bit

I

15

14

13

12

0

0

0

0

I

11

10

9

1

0

0

Bit Type Codes: TST = 00, CHG

6

8

I

0

4

5

Type

0

3
Effective Address

= 01, CLR = 10, SET = 11

MOVEP
15

14

0

0

I

13

12

0

0

Op-Mode; Word to Reg

11

9

10

8

Register

= 100, Long to

6
Op-Mode

Reg

= 101, Word

to Mem

4

5

I
=

0

I

0

0

3

I

1

110, Long to Mem

Register

= 111

OR Immediate
14

15

I

0

I

0

I

13

12

11

10

9

8

0

0

0

0

0

0

9

8

1

0

6

5

4

3

0

Effective Address

Size

AND Immediate
15

14

13

12

11

10

0

0

0

0

0

0

I
•

HITACHI

6
Size

5

4

3

0

Effective Address

649

·H 068000,H 068000Y,H o68000Z
SUB Immediate
15

14

13

12

I0 I0 I0

0

10

9

8

0

1

0

0

11

10

11

I I

7

6

5

4

Size

3

0

2

Effective Address

ADD Immediate
15

14

13

12

9

8

0

0

0

0

1

1

0

14

13

12

11

0

0

0

14

13

12

I I I I I I I
0

6

5

4

Size

3

2

0

Effective Address

EOR Immediate
15

I I
0

10

9

8

1

0

1

0

11

8

I I

I

6

5

4

Size

3

0

2

Effective Address

CMP Immediate
15

I I
0

0

10

9

1

1

0

11

10

I I I I
0

0

I

6

7

5

4

Size

0

3

2

0

Effective Address

I

(2) MOVE BYTE INSTRUCTION

MOVE Byte
15

14

0

0

13
0

12

I

9

8

6

5

4

3

Destination

1

Register

Mode

Mode

0

2

Source
~
~~egister

(3) MOVE LONG INSTRUCTION

MOVE Long
15

14

13

12

10

11

9

8

7

6

5

4

3

Destination
Register

~

2

Source
Mode

Mode

Register

(4) MOVE WORD INSTRUCTION
MOVE Word
15

14

13

12

11

10

9

8

7

6

5

4

3

Destination
Register

2

0

Source
Mode

Mode

Register

(5) MISCELLANEOUS INSTRUCTIONS
NEGX
15

14

13

12

11

10

9

I I I I I I I I
0

1

0

0

0

0

14

13

12

11

1

0

0

14

13

12

8

0

0

6

7

5

4

Size

3

2

0

Effective Address

MOVE from SR
15
0

I

10

9

8

0

0

0

0

11

10

9

8

1

0

I I

7

6

I I
1

5

4

3

2

0

Effective Address

1

CLR
15

I
650

0

I I I I I I
1

0

0

0

0

6

7

eHITACHI

Size

5

4

3

2

Effective Address

0

-----------------------HD68000,HD68000Y,HD68000Z
NEG
15

14

13

12

11

10

9

8

6

5

4

Size

3

o

2

Effective Address

MOVE to CCR
15

14

13

12

11

10

9

8

6

5

4

3

o

2

Effective Address

NOT
15

14

13

12

11

10

9

8

6

5

4

3

o

2

Effective Address

Size

MOVE to SR
15

14

13

12

11

10

9

8

7

6

5

4

3

o

2

Effective Address

NBCD
15

14

13

12

11

10

9

8

6

5

4

3

o

2

Effective Address

PEA
15

14

13

12

11

10

9

8

6

5

4

3

o

2

Effective Address

SWAP
15

14

13

12

11

10

9

8

6

5

4

3

o

2
Register

MOVEM Registers to EA
15

14

13

12

11

10

9

8

6

5

4

3

o

2

Effective Address

Sz

EXTW
15

14

13

12

11

10

9

8

6

5

4

3

o

2
Register

EXTL
15

14

13

12

11

10

9

8

6

5

4

3

o

2
Register

TST
15

14

13

12

11

10

9

8

6

5

4

3

2

o

Effective Address

Size

TAS
15

14

13

12

11

10

9

8

6

5

4

3

2

o

Effective Address

eHITACHI

651

H068000, Ho68000Y, Ho6 8 0 0 0 Z - - - - - - · - - - - - - - - - - - - - - - - MOVEM EA to Registers
15
o

14
1

1

13
1

0

12
1

0

11
1

1

10
1

1

9
1

0

8

1

°

7
1

1

5

6
1

4

Sz

3

2

0

Effective Address

TRAP
15

°

1

14
1

1

13
1

12

11

° °E

10
1 1

1

9
1

1

8

7

1

° °

1

° 1°

1

5

6

1 1

1

4

3

2

° °

0

Vector

1

LINK
15

14

°

1 1

13
1

12

°=r_ ~_ J

11

10

1

1 1

11

10

9
1

1

8

6

5

4

1 1

1 0

1 1

6

5
1 0

G

7

o

3
1

°

Register

UNLK
15
-0

14

13

12

9

8

7

---'-1-1--'-1-0--'--1-0---r1-1---r1-1---'1-1---r-~· I

r-I

1

4

3
1 1

I

2

0
Register

MOVE to USP
15

7

6

5

4

3

1 0

1 1

1 1

1 0

1 0

7

6

5

4

3

"---0---,1~1---'1_o---'-l_o--'-I_1----L1_1----L1_1--L1_0-L1_o-,---Q 1

1 0

1 1

4

3

1 0

14
1 1

13
1 0

12
1

°

11

10

9

1 1

1 1

1 1

12

11

10

8

1

°

2

0
Register

MOVE from USP
15

14

13

9

8

2

0
Register

RESET
15

14

13

12

11

10

9

8

7

6

5

2

0

10111010111111101011111110101010

NOP
15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

10111010111111101011111110101011

STOP
15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

10111010111111101011111110101110

RTE
15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

10111010111111101011111110101111

RTS
15

14

13

12

11

10

9

8

7

6

543

2

0

14

13

12

11

10

9

8

7

6

5

2

0

TRAPV
15

o

652

1 1

eHITACHI

4

3

------------------------H068000,H068000Y,H068000Z
RTR
15

14

13

12

11

10

9

8

15

14

13

12

11

10

9

8

7

6

5

4

6

5

4

3

o

3

o

JSR
Effective Address

JMP
15

14

13

12

11

10

9

8

6

5

o

3

4

Effective Address

CHK
15

14

13

12

11

10

9

8

6

5

o

3

4

Register

Effective Address

LEA
15

14

13

12

11

10

8

9

6

5

4

Register

o

3
Effective Address

(6) ADD QUICK, SUBTRACT QUICK, SET CONDITIONALLY, DECREMENT INSTRUCTIONS
ADDQ
15

14

13

12

11

10

9

8

I

Data

6

5

o

3

4

Effective Address

Size

0

SUBQ
15

14

13

12

11

10

8

9

I

Data

6

5

o

3

4

Size

1

Effective Address

See
15

14

13

12

11

10

9

8

6

4

5

I1 I1

Condition

o

3
Effective Address

DBee
15

14

13

12

11

10

8

9

Condition

6

5

I1 I1

o

7

4

o

3

I0 I1

Register

(7) BRANCH CONDITIONALLY, BRANCH TO SUBROUTINE INSTRUCTION

Bee
15

14

13

12

11

10

8

9

6

5

Condition

4

3

o

8 bit Displacement

BSR
15

14

13

12

11

10

9

o

I

8

7

6

5

4

3

o

8 bit Displacement

1

(8) MOVE QUICK INSTRUCTION
MOVEQ
15

14

13

12

11

10

Register

9

8

I0

eHITACHI

6

5

4

3

o

Data

653

H068000,H068000Y,H068000Z----------------------(9) OR, DIVIDE, SUBTRACT DECIMAL INSTRUCTIONS
OR

15

14

13

12

11

9

10

8

6

5

4

3

Op-Mode

Register

a

2

Effective Address

Op-Mode

B

W

L

000
100

001
101

010
110

On V EA ~ On
EA V Dn~EA

DIVU
15

14

13

12

a

o

o

14

13

12

o

o

o

14

13

12

11

9

10

8

6

5

3

4

o

Register

a

2

Effective Address

DIVS
15

11

8

9

10

6

5

3

4

Register

o

2

Effective Address

SBCD
15

10

11

8

9

6

5

3

4

Destination
Register

a

2

Source Register

R/M (register/memory): register - register

= 0, memory -

memory

=1

(10) SUBTRACT, SUBTRACT EXTENDED INSTRUCTIONS

SUB

15

14

13

12

11

9

10

8

6

5

4

Op-Mode

Register

3

o

2

Effective Address

Op-Mode

SUBX

B

W

L

000
100

001
101
011

010
110
111

15

14

Dn-EA~Dn
EA-Dn~EA
An-EA~ An

13

12

11

10

8

9

6

5

3

4

Destination
Register

o

2

Source Register

R/M (register/memory): register - register

=0, memory -

memory = 1

(11) COMPARE, EXCLUSIVE OR INSTRUCTIONS
CMP
15

13

14

12

11

10

9

8

6

5

3

4

Op-Mode

Register

o

2

Effective Address

Op-Mode

CMPM

B

W

L

000

001
011

010
111

15

14

Dn-EA
An-EA
12

13

11

o

10

9

8

6

Register

Size

5

4

o

o

5

4

3

I

o

2
Register

1

EOR
15

14

13

12

11

10

9

8

7

6

Register

3

2

a

Effective Address

(12) AND, MULTIPLY, ADD DECIMAL, EXCHANGE INSTRUCTIONS
AND

15

14

13

12

11

10
Register

9

8

7
Op-Mode

Op-Mode

654

B

W

L

000
100

001
101

010
110

On /\ EA~Dn
EA /\ On ~EA

~HITACHI

6

5

4

3

2

Effective Address

o

H068000,H068000Y,H068000Z
MULU
15

14

13

12

0

0

13

12

0

0

13

12

11

10

9

8

6

5

4

0

Register

3

2

0

Effective Address

MULS
15

14

11

9

10

8

6

5

4

Register

3

2

0

Effective Address

ABCD
14

15

11

9

10

8

6

5

4

3

Destination
Register

2

0

Source Register

R/M (register/memory): register - register

= 0, memory -

memory

=1

EXGD
15

14

13

12

11

10

9

6

8

5

4

3

2

Data Register

0

Data Register

EXGA
14

15

13

12

11

10

9

6

8

5

4

3

Address Register

2

0

Address Register

EXGM
15

14

13

12

11

10

9

6

8

5

4

3

Data Register

2

0

Address Register

(13) ADD, ADD EXTENDED INSTRUCTIONS
ADD
14

15

13

12

11

10

9

B
000
100

W
001
101
011

6

8

Register

5

4

Op-Mode

3

2

0

Effective Address

Op-Mode
L
010
On + EA -+Dn
110
EA + On -+ EA
111
An + EA -+An

ADDX
15

14

13

12

11

10

9

8

6

5

4

3

Destination
Register

2

0

Source Register

R/M (register/memory): register - register

=0, memory -

memory

=1

(14) SHIFT/ROTATE INSTRUCTIONS
Data Register Shifts
15

14

13

12

11

10

9

8

6

5

4

3

2

Count/Register

0
Register

Memory Shifts
15

I

1

14

13

12

11

0

0

10
Type

9

8

7

6

d

5

4

3

2

0

Effective Address

Shift Type Codes: AS = 00, LS = 01, ROX = 10, RO = 11
d (direction): Right = 0, Left = 1
i/r (count source): Immediate Count = 0, Register Count = 1

eHITACHI

655

H068000,H068000Y,H068000Z----------------------•

INSTRUCTION EXECUTION TIMES

The following paragraphs contain listings of the instruction
execution times in terms of external clock (CLK) periods.
In this timing data, it is assumed that both memory read and
write cycle times are four clock periods. Any wait states caused
by a longer memory cycle must be added to the total instruction time. The number of bus read and write cycles for each
instruction is also included with the timing data. This data is
enclosed in parenthesis following the execution periods and
is shown as: (r/w) where r is the number of read cycles and
w is the number of write cycles.

the time required to perform the operations, store the results,
and read the next instruction. The number of bus read and
write cycles is shown in parenthesis as: (r/w). The number
of clock periods and the number of read and write cycles must
be added respectively to those of the effective address calculation where indicated.
In Table 30 the headings have the following meanings: An =
address register operand, Dn = data register operand, ea = an
operand specified by an effective address, and M = memory
effective address operand.
•

IMMEDIATE INSTRUCTION CLOCK PERIODS

Table 27 lists the number of clock periods required to compute an instruction's effective address. It includes fetching
of any extension words, the address computation, and fetching of the memory operand. The number of bus read and
write cycles is shown in parenthesis as (r/w). Note there are
no write cycles involved in processing the effective address.

The number of clock periods shown in Table 31 includes
the time to fetch immediate operands, perform the operations,
store the results, and read the next operation. The number of
bus read and write cycles is shown in parenthesis as: (r/w).
The number of clock periods and the number of read and write
cycles must be added respectively to those of the effective
address calculation where indicated.
In Table 31, the headings have the following meanings:
# = immediate operand, Dn = data register operand, An = address register operand, M = memory operand, CCR = condition
code register, and SR =status register.

• MOVE INSTRUCTION CLOCK PERIODS

• SINGLE OPERAND INSTRUCTION CLOCK PERIODS

Table 28 and 29 indicate the number of clock periods for
the move instruction. This data includes instruction fetch,
operand reads, and operand writes. The number of bus read
and write cycles is shown in parenthesis as: (r/w).

Table 32 indicates the number of clock periods for the
single operand instructions. The number of bus read and write
cycles is shown in parenthesis as: (r/w). The number of clock
periods and the number of read and write cycles must be added
respectively to those of the effective address calculation where
indicated.

(NOTE) The number of periods includes instruction fetch and all applicable operand fetches and stores.

•

EFFECTIVE ADDRESS OPERAND CALCULATION
TIMING

• STANDARD INSTRUCTION CLOCK PERIODS

The number of clock periods shown in Table 30 indicates

Table 27 Effective Address Calculation Timing

On
An

Addressing Mode
Register
Data Register 0 irect
Address Register Direct

An@
An@+
An@An@(d)
An@(d,ix)*
xxx.W
xxx.L
PC@(d)
PC@(d, ix)*
#xxx

Memory
Address Register Indirect
Address Register Indirect with Postincrement
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
Address Register Indirect with Index
Absolute Short
Absolute Long
Program Counter with Displacement
Program Counter with Index
Immediate

• The size of the index register Ox) does not affect execution time.

656

eHITACHI

Byte, Word

Long

0(0/0)
0(0/0)

0(0/0)
0(0/0)

4(1/0)
4(1/0}

8(2/0}
8(2/0}

6(1/0)
8(2/0)

10(2/0}
12(3/0)

10(2/0)
8(2/0)

14(3/0)
12(3/0}

12(3/0)
8(2/0)

16(4/0)
12(3/0)
14(3/0)
8(2/0}

10(2/0)
4(110)

- - - - - - - , - - - - - - - - - - - - - - - - - - - H 068000, H068000Y, H068000Z
Table 28 Move Byte and Word Instruction Clock Periods
Destination

Source

On

An

An@

An@+

An@-

An@(d)

An@(d, ix)*

xxx.W

4(1/0)
4(1/0)
8(210)

4(1/0)
4(1/0)
8(2/0)

8(1/1 )
8(1/1 )
12(2/1)

8(1/1 )
8(1/1)
12(2/1 )

8(1/1)
8(1/1 )
12(2/1 )

12(2/1)
12(2/1 )
16(3/1 )

14(2/1 )
14(2/1)
18(3/1)

12(2/1)
12(2/1)
16(3/1)

xxx.L
16(3/1)
16(3/1)
20(4/1)

8(2/0)
10(2/0)
12(3/0)
14(3/0)
12(3/0)
16(4/0)

12(2/1)
14(2/1)
16(3/1)

12(2/1)
14(2/1)
16(3/1)
18(3/1)
16(3/1 )
20(4/1 )

18(3/1)
20(3/1)
22(4/1)

16(3/1)
18(3/1)
20(4/1)

20(4/1)
22(4/1)
24(5/1)

18(3/1)
16(3/1)
20(4/1)

12(2/1)
14(2/1)
16(3/1)
18(3/1 )
16(3/1)
20(4/1)

16(3/1)
18(3/1)
20(4/1)

An@(d, ix)*
xxx.W
xxx.L

8(210)
10(2/0)
12(3/0)
14(3/0)
12(3/0)
16(4/0)

22(4/1)
20(4/1 )
24(5/1 )

24(4/1)
22(4/1)
26(5/1)

22(4/1)
20(4/1)
24(5/1 )

26(5/1)
24(5/1 )
28(6/1)

PC@(d)
PC@(d,ix)*
#xxx

12(3/0)
14(3/0)
8(210)

12(3/0)
14(3/0)
8(2/0)

16(3/1)
18(3/1)
12(2/1)

16(3/1)
18(3/1 )
12(2/1 )

16(3/1 )
18(3/1 )
12(2/1)

20(4/1)
22(4/1 )
16(3/1 )

22(4/1)
24(4/1)
18(3/1)

20(4/1 )
22(4/1 )
16(3/1)

24(5/1 )
26(5/1)
20(4/1)

xxx.W
16(2/2)
16(2/2)
24(4/2)
24(4/2)
26(4/2)
28(5/2)
30(5/2)
28(5/2)
32(6/2)

xxx.L
20(3/2)
20(3/2)
28(5/2)

28(5/2)
30(5/2)
24(4/2)

32(6/2)
34(6/2)
28(5/2)

On
An
An@
An@+
An@An@(d)

* The size of the index register (ix) does not affect execution time.
Table 29 Move Long Instruction Clock Periods
Destination

Source

On

4(1/0)
4(110)
12(3/0)
12(3/0)
14(3/0)
16(4/0)
18(4/0)
16(4/0)
20(5/0)

On
An
An@
An@+
An@An@(d)
An@(d, ix)*
xxx.W
xxx.L
PC@(d)
PC@(d,ix)*
#xxx

16(4/0)
18(4/0)
12(3/0)

An
4(1/0)
4(1/0)
12(3/0)

An@

An@+

An@-

An@(d)

An@(d,ix)*

12(1/2)
12(1/2)
20(3/2)

12(1/2)
12(1/2)
20(3/2)

16(2/2)
16(2/2)
24(4/2)

18(2/2)
18(2/2)
26(4/2)

12(3/0)
14(3/0)
16(4/0)

20(3/2)
22(3/2)
24(4/2)

20(3/2)
22(3/2)
24(4/2)

12(1/2)
12(1/2)
20(3/2)
20(3/2)
22(3/2)
24(4/2)

26(4/2)
28(4/2)
30(5/2)

18(4/0)
16(4/0)
20(5/0)
16(4/0)
18(4/0)
12(3/0)

26(4/2)
24(4/2)
28(5/2)
24(4/2)
26(4/2)
20(3/2)

26(4/2)
24(4/2)
28(5/2)
24(4/2)
26(4/2)
20(3/2)

26(4/2)
24(4/2)
28(5/2)
24(4/2)
26(4/2)
20(3/2)

24(4/2)
26(4/2)
28(5/2)
30(5/2)
28(5/2)
32(6/2)
28(5/2)
30(5/2)
24(4/2)

32(5/2)
30(5/2)
34(6/2)
30(5/2)
32(5/2)
26(4/2)

28(5/2)
30(5/2)
32(6/2)
34(6/2)
32(6/2)
36(7/2)

* The size of the index register (ix) does not affect execution time.

Table 30 Standard Instruction Clock Periods
Instruction
ADD
AND
CMP

op, An

op,Dn

8(1/0) +
6(1/0) + **

4(1/0) +
6(1/0) + **

8(1/1) +
12(1/2) +

-

4(110) +
6(1/0) + **

8(1/1) +
12(1/2) +

Long
Byte, Word
Long
Byte, Word

6(110) +

Long

6(1/0) +

DIVS

-

-

DIVU

-

-

EOR
MULS
MULU

OR
SUB

Byte, Word
Long

Byte, Word
Long
Byte, Word
Long

+ add effective address calculation time
* indicates maximum value

op Dn,

Size
Byte, Word

-

4(1/0)
6(1/0)
158(1/0)
140(1/0)
4(1/0)
8(110)

+
+
+ *
+ *
***
***

70(1/0) + *
70(1/0) + *

8(1/1) +
12(1/2) +

-

-

4(110) +
6(1/0) + **

8(1/1) +
12(1/2) +

8(1/0) +
6(1/0) + **

4(1/0) +
6(110) + **

12(1/2) +

8(1/1)+

** total of 8 clock periods for instruction if the effective address is register direct
*** only available effective address mode is data register direct

eHITACHI

657

H068000,H068000Y,H068000Z----------------------------------------------Table 31
Instruction
ADDI

Immediation Instruction Clock Periods
op #, On

op #, An

op#,M

8(2/0)

-

12(2/1) +

-

16(3/0)

-

20(3/2) +

-

Long

AD DO

Byte. Word

4(1/0)

8(1/0)*

8(1/1)+

Long

8(1/0)

8(1/0)

12(1/2) +

-

12(2/1) +

20(3/0)

20(3/1) +

Long
Long

MOVEO

12(3/0) +
12(2/1) +

20(3/0)

20(3/2) +

-

20(3/0)

Long

4(1/0)

-

8(2/0)

-

12(2/1)+

16(3/0)

-

20(3/2) +

-

12(2/1) +

-

20(3/2) +

-

8(2/0)

Byte, Word

16(3/0)

Long

SUBO

14(3/0)

8(2/0)
16(3/0)

Long

SUBI

14(3/0)

-

8(2/0) +

Long
Byte. Word

ORI

8(2/0)

-

Byte, Word

EORI

8(2/0)

16(3/0)

Byte, Word

CMPI

-

8(2/0)

Byte. Word

ANDI

op #, CCR/SR

Size
Byte, Word

Byte, Word

4(1/0)

8(1/0)*

8(1/1) +

Long

8(1/0)

8(1/0)

12(1/2) +

+ add effective address calculation

time

* word only

Table 32 Single Operand Instruction Clock Periods
Instruction
CLR
NBCD
NEG
NEGX
NOT
See
TAS
TST

Register

Size

Memory

Byte, Word

4(1/0)

8(1/1)+

Long

6(1/0)

12(1/2) +

Byte

6(1/0)

8(1/1) +

Byte, Word

4(1/0)

8(111)+

Long

6(1/0)

12(1/2) +

Byte, Word

4(1/0)

8(1/1) +

Long

6(1/0)

12(1/2) +

Byte, Word

4(1/0)

8(1/1)+

Long

6(1/0)

12(1/2) +

Byte, False

4(110)

8(1/1)+

Byte, True

6(1/0)

8(1/1)+

Byte

4(1/0)

10(1/1)+

Byte, Word

4(1/0)

4(1/0) +

Long

4(1/0)

4(1/0) +

+ add effective address calculation time

•

•

SHIFT/ROTATE INSTRUCTION CLOCK PERIODS

Table 33 indicates the number of clock periods for the shift
and rotate instructions. The number of bus read and write
cycles is shown in parenthesis as: (r/w). The number of clock
periods and the number of read and write cycles must be added
respectively to those of the effective address calculation where
indicated.

658

BIT MANIPULATION INSTRUCTION CLOCK PERIODS

Table 34 indicates the number of clock periods required for
the bit manipulation instructions. The number of bus read and
write cycles is shown in parenthesis as: (r/w). The number of
clock periods and the number of read and write cycles must be
added respectively to those of the effective address calculation
where indicated.

~HITACHI

- - - - - - - - - - - - - - - - - - - - - - - - H D68000,H D68000Y, H o 68000Z
•

CONDITIONAL INSTRUCTION CLOCK PERIODS
Table 35 indicates the number of clock periods required for
the conditional instructions. The number of bus read and write
cycles is indicated in parenthesis as: (r/w). The number of clock
periods and the number of read and write cycles must be added
respectively to those of the effective address calculatiun where
indicated.

• JMP, JSR, LEA, PEA, MOVEM INSTRUCTION CLOCK
PERIODS
Table 36 indicates the number of clock periods required for
the jump, jump to subroutine, load effective address, push effective address, and move multiple registers instructions. The number of bus read and write cycles is shown in parenthesis as: (r/w).

Table 33 Shift/Rotate Instruction Clock Periods
Instruction
ASR,ASL

Size

Register

Memory

Byte, Word

6 + 2n(1/0)
8 + 2n(1/0)
6 + 2n(1/0)
8 + 2n(1/0)

8(111) +

6+2n(1/0)
8 + 2n(1/0)

8(1/1) +

6 + 2n(1/0)
8 + 2n(1/0)

8(111)+

Long
Byte, Word

LSR, LSL

Long
Byte, Word

ROR, ROL

Long
Byte, Word

ROXR, ROXL

Long

8(111) +

-

Table 34 Bit Manipulation Instruction Clock Periods

Instruction
BCHG
BCLR
BSET
BTST

Dynamic

Size

Memory

Register

-

8(1/1)+

-

Byte

8(1/0)*

Long

-

Byte

10(1/0)*

Long

-

Byte
Long

j

8(1/0)*

-

Byte

6(1/0)

Long

Static

Register

8(111)+

8(111) +

-

Memory
12(2/1)

+

-

12(2/0)*

-

12(2/1) +

-

14(2/0) *

-

12(2/1) +

-

12(2/0)*

4(110) +

-

-

10(2/0)

8(2/0) +

-

+ add effective address calculation time
* indicates maximum value

Table 35 Conditional Instruction Clock Periods
Instruction

Displacement

Bee
BRA
BSR
DBee

Trap or Branch
Taken

Trap of Branch
Not Taken

Byte

10(2/0)

8(1/0)

Word

10(2/0)

12(2/0)

-

Byte

10(2/0)

Word

10(2/0)

Byte

18(2/2)

Word

18(2/2)

-

CCtrue

-

12(2/0)

CCfalse

10(2/0)

14(3/0)
10(1/0) +

CHK

-

40(5/3) + *

TRAP

-

34(4/3)

-

34(5/3)

4(1/0)

TRAPV

+ add effective address calculation time
* indicates maximum value

eHITACHI

659

H068000,H068000Y,H068000Z----------------------------------------------Table 36 JMP, JSR, LEA, PEA, MOMEM Instruction Clock Periods
Instr
JMP
JSR
LEA
PEA

Size

-

An@
8(2/0)
16(2/2)
4(1/0)
12(1/2)

An@+

An@-

-

-

An@(d)
10(2/0)
18(2/2)

-

8(2/0)

12(2/0)

8(2/0)

12(3/0)

8(2/0)

12(2/0)

16(2/2)

20(2/2)

16(2/2)

20(3/2)

16(2/2)

20(2/2)

16+4n
(4+n/0)

18+4n
(4+n/0)

16+4n
(4+n/0)

20+4n
(5+n/0)

16+4n
(4+n/0)

16+8n
(4+2n/0)

18+8n
(4+2n/0)

16+8n
(4+2n/0)

20+8n
(5+2n/0)

16+8n
(4+2n/0)

18+4n
(4+n/0)
18+8n
(4+2n/0)

-

An@(d,ix)*
14(3/0)
22(2/2)

xxx.W
10(2/0)
18(2/2)

xxx.L

PC@(d)

12(3/0)
20(3/2)

10(2/0)
18(2/2)

MOVEM

Word

12+4n
(3+n/0)

12+4n
(3+n/0)

M~R

Long

12+8n
(3+2n/0)

12+8n
(3+2n/0)

MOVEM

Word

8+4n
(2/n)

-

8+4n
(2/n)

12+4n
(3/n)

14+4n
(3/n)

12+4n
(3/n)

16+4n
(4/n)

R~M

Long

8+8n
(2/2n)

-

-

8+8n
(2/2n)

12+8n
(3/2n)

14+8n
(3/2n)

12+8n
(3/2n)

16+8n
(4/2n)

-

-

PC@(d,ix)*

-

14(3/0)
22(2/2)

-

-

n is the number of registers to move
* is the size of the index register (ix) does not affect the instruction's execution time

• MULTI·PRECISION INSTRUCTION CLOCK PERIODS

Table 37 indicates the number of clock periods for the multi·
precision instructions. The number of clock periods includes
the time to fetch both operands, perform the operations, store

the results, and read the next instructions. The number of read
and write cycles is shown in parenthesis as: (r/w).
In Table 37, the headings have the following meanings: Dn =
data register operand and M = memory operand.

Table 37 Multi·Precision Instruction Clock Periods
Instruction
ADDX
CMPM

Size

op On, On

Byte, Word

4(1/0)

opM, M
18(3/1)

Long
Byte, Word

8(1/0)

30(5/2)

-

20(5/0)

12(3/0)

Long
Byte, Word
Long

4(110)

18(3/1)

8(1/0)

30(5/2)

ABCD

Byte

6(110)

18(3/1 )

SBCD

Byte

6(110)

18(3/1)

SUBX

• MISCELLANEOUS INSTRUCTION CLOCK PERIODS

•

Table 38 indicates the number of clock periods for the fol·
lowing miscellaneous instructions. The number of bus read and
write cycles is shown in parenthesis as: (r/w). The number of
clock periods plus the number of read and write cycles must be
added to those of the effective address calculation where indio
cated.

Table 39 indicates the number of clock periods for exception
processing. The number of clock periods includes the time for
all stacking, the vector fetch, and the fetch of the first instruc·
tion of the handler routine. The number of bus read and write
cycles is shown in parenthesis as: (r/w).

660

EXCEPTION PROCESSING CLOCK PERIODS

~HITACHI

- - - - - - - - - - - - - - - - - - - - - - - - H068000,HD68000Y,H068000Z
Table 38 Miscellaneous Instruction Clock Periods
Instruction

Size

Memory

Register

MOVE from SR

-

6(1/0)

8(1/1) +

MOVE to CCR

-

12(2/0)

12(2/0) +

-

12(2/0)

12(2/0) +

MOVE to SR

-

6(110)
4(1/0)

Long

4(1/0)
16(2/2)
4(110)

-

-

4(1/0)

-

-

-

-

RTR

-

20(5/0

RTS

16(4/0)

SWAP

-

UNLK

-

12(3/0)

-

-

RTE

-

LINK
MOVE from USP
MOVE to USP
NOP
RESET

STOP

-

Memory ~ Register

-

EXT

Long

Memory

-

Word

EXG

-

~

-

MOVEP

Word

Register

4(1/0)
132(1/0)
20(510)

4(010)
4(1/0)

16(2/2)

16(4/0)

24(2/4)

24(6/0)

-

-

-

-

-

-

-

-

-

-

+ add effective address calculation time

Table 39 Exception Processing Clock Periods
Exception

Periods

Reset

34(6/0)

Address Error

50(4/7)

Bus Error

50(4/7)

Interrupt

44(5/3)*

Illegal Instruction

34(4/3)

Privileged Violation

34(4/3)

Trace

34(4/3)

* The interrupt acknowledge bus cycle is assumed to take
four external clock periods .

• APPENDIX
• THE 68000S MASK SET

We implement the specification for HD68000-10/-12 and
two corrections on the 68000S mask set. One of these corrections is the bus arbitration logic, and the other is a change to
correct a RTE/RTR microcode problem.
(1) Bus Arbitration Logic
The problem occurs when bus grant acknowledge (BGACK)
is asserted for only one clock cycle while bus request (BR) is
negated. IF BR is asserted one clock cycle...!fter BGACK is
negated,..lhe processor asserts bus grant (BG) and address
strobe (AS) at the same time (Refer to Figure 58). This, in

turn, may cause external DMA logic to run a bus cycle at the
same time as the processor cycle, only when those paticular
timings are all satisfied. If the DMAC HD68450 is used, this
problem can be avoided. Because the HD68450 negates BR
by one clock after the assertion of BGACK.
For the 68000S mask set, an internal hardware change is
implemented and a timing specification (tBGKBR) is added.
If BR and BGACK meet the asynchronous set-up time
tAS! #47, then tBGKBR can be ignored. If BR and BGACK
are asserted asynchronously with respect to the clock, then
BGACK has to be asserted before BR is negated.

~HITACHI

661

H068000,H068000Y,H068000Z-----------------------------------------------Table

Number

Item

40

Test
Condition

Symbol

tBGKBR Specification
4MHz
Version

6MHz
Version

8MHz
Version

10MHz
Version

12.5MHz
Version

H068000-4
H068000Y4
H068000Z4

H068000-6
HD68QOOY6
H068000Z6

H068000.s
H068000Y8
H068OooZ8

::g::~y11~
H068000Z10

H068000·12
H068000Y12
H068000Z12

min

min

min

@

SGACK "Low" to SA "High" tBGKBR

Fig. 57

30

I max
I -

min
25

I max
I -

20

I max
I -

20

I max
I -

min
20

I max
I -

Strobes
and R / W - - - - - - - - - '

~-----+------~------------~

BGACK---t------------------~l~__--~~

BG----------------~

CLK

Figure 57

AC Electrical Waveforms - Bus Arbitration

L- -- - __ u."
:\

!'

I

I

:I

:I

:

I

------------------------~~(-~!----~!----__________________________________________J'
B", G,,", E,w,

--.J

Fix moves Bus Grant to here

Figure

662

58

I

I

~~-----~:~--------

;
--------1-

Bus Arbitration Timing Diagram Error Sequence

_HITACHI

Unit

ns

-------------------------------------------------H068000,H068000Y,H068000Z
68000R and 68000 Mask Set

680005 Mask Set

RA

RA

R = Bus Request Internal
A = Bus Grant Acknowledge Internal
G = Bus Grant
T = Three State Control to Bus Control Logic
X = Don't Care

R
A
G
T
X

= Bus Request Internal

• State machine will not change state if bus is in SO. Refer to
BUS ARBITRATION CONTROL for additional information.

• State machine will not change state if bus is in SO. Refer to
BUS ARBITRATION CONTROL for additional information.

= Bus

Grant Acknowledge Internal

= Bus Grant
= Three State Control to Bus Control Logic
= Don't Care

Figure 59 State Diagram of HD68000 Bus Arbitration Unit

To Avoid this problem on 68000R mask set, users are recommended to choose one of the followings.
I) Negate BR more than one clock after the assertion of
BGACK.
2) Avoid the assertion of BGACK for one clock cycle.
3) Reassert BR more than two clocks later than the negation of BGACK.
4) Use HD68450 as DMA controllers.
(2) RTE/RTR Microcode Problem
The error in the microcode only affects the RTR and the

RTE instructions. These two instructions execute correctly
provided there is no bus error.
If there is a bus error on the 2nd, 3rd, or 4th bus cycle of
RTR or RTE, the program counter is lost. The program counter
loads the stack pointer +2 which is the same address as the
access. The results is the program counter containing the stack
pointer. This problem can occur on all HD68000 mask sets
previous to 68000S.
The fix inhibits the loading of the program counter during
this instruction until the 4th bus cycle.
Memory

BusCvcle

Access Add,",

Content of

~

I

I

I

:

:

I

$P+2:

:

I

I

I

I

I

I

$P+2
(M+2'-

P'09,·mCount.,

:
:

$P+2
IM+21-

t

PCH,PCl

'

: PCH'PCL+2 :
I

I

I

I

$P+2: PCH,PCL+2
IM+21-,

!

SP~A

5P+2

PCH

$P+4

pel

M~
M+28

I

• ; 68000S m_k set

Figure 60 RTE Instruction Bus Cycle

~HITACHI

663

HD68450. HD68450 Y - - - DMAC (Direct Memory Access Controller)
Microprocessor implemented systems arc becoming increasingly complex, particularly with the advent of high-performance
16-bit MPU devices with large memory addressing capability. In
order to maintain high throughput, large blocks of data must be
moved within these systems in a quick, efficient manner with
minimum intervention by the MPU itself.
The HD68450 Direct Memory Access Controller (DMAC)
is designed specifically to complement the performance and
architectural capabilities of the HD68000 MPU by providing the
following features:
•
•
•
•
•
•
•
•
•
•
•
•

HMCS68000 Bus Compatible
4 independent DMA Channels
Memory-to-Memory, Memory-to-Device, Device-to-Memory
Transfers
MMU Compatible
Array-Chained and Linked-Array-Chained Operations
On-Chip Registers that allow Complete Software Control by
the System MPU
I nterface Lines for Requesting, Acknowledging, and
Incidental Control of the Peripheral Devices
Variable System Bus Bandwidth Utilization
Programmable Channel Prioritization
2 Vectored interrupts for each Channel
Auto-Request and External-Request Transfer Modes
+5 Volt Operation

The DMAC functions by transferring a series of operands
(data) between memory and peripheral device; operand sizes can
be byte, word, or long word. A block is a sequence of operations; the number of operands in a block is determined by a
transfer count. A single-channel operation may involve the
transfer of several blocks of data between memory and device.

-The specifications for HD68450-10/-12 and HD68450Yl0/Y12
are preliminary.HD68450-4, HD68450-6,
HD68450-8, HD68450-10,

(DC-64)
HD68450Y4, HD68450Y6,
HD68450Y8,
HD68450Yl0,

"y" stands for Pin Grid
Array Package.

(PGA-68)
• PROGRAMMING MODEL
a
Sl8lusRegls.ter
Error Register
ControtRegister

Operation
Conuol Register

• TYPE OF PRODUCTS

Sequence
Control Register

Type No.
HD68450-4

Bus Timing
6MHz

HD68450-8

8MHz

HD68450-10

10MHz

HD68450Y4

4MHz

HD68450Y6

6MHz

HD68450Y8

8MHz

HD68450Y10

Packaging

4MHz

HD68450-6

Channel

ContfolReglster

Control Register

I} One Per DMAC

Normal

I nterrupt Vector
Error

Interrupt Vector
Channel

Priority Register

DC-64

Memory

Function Codes

r

I

PGA-68

10MHz

Memory Transfer Counter
Base Transfer Counter

Memory Address Register
DeVice Address Register
Bast! Address Register

664

~HITACHI

4 Sets
(One Set Per
Channel)

----------------------------------------------------------HD68450,HD68450Y
• PACKAGING INFORMATION (Dimensions in mm)
• DC-64 (SIDE·BRAZED CERAMIC DIP)

•

PGA-68 (PIN GRID ARRAY PACKAGE)

•

HD68450Y

-

... --

U'03

~

020-0.38

---22.86 -

•
•

PIN ARRANGEMENT
HD68450

(Bottom View)

~~.I Function ~i~.
1

N/C

18

Function

~i~.

PC[;

35

-2·--A~3/D' ~

19 --OTACK ~
3-~A;;-/D;--~O --liDS
4-~A.~/D;--- ~:ii-

·~5-~-A-;;O~
-~e---A;·
~7~

-

~~~i\;

- '2223
-

·8--~- A;:-~--

25-

-

R/iii
N/C

- CS
eLK

-

54

38

A,-;;O~ ~

55

3-9 -A,/O;- 56
40
v~;~- 57
41
Vc~
_... 5842

:lS--IACK-·

43
44
45

i"2" .

28

29- 30

UAS - -

13 -·~DiIDi

4e
-Fe, -- 47
SEC;"

i4 ~. ·-REa-;-~-

34

FC,

48

15 -

3:133
34

A23/D"
An/D..

49
50

A,o/D"

51

16~

,i-r-

~HITACHI

--- REO, --REOo

PeL,

BGACK

A,~/D;

27

ACK;ACKo

Function

52

37

9--i.;~~

N/C--

~~.

A'9/D!1

A,-;;O,- 53- ---Los

10-"

11 ---~BR -~

(Top View)

~:i4

~-AS

Function

36

59

Vss
Vee
DONE

iRa
ACK,
BEC,

60
FCo
-HI8YTE COIR --

63
64

665

HD68450,HD68450Y--------------------------------------------------------•

ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Value

Unit

-0.3 - +7.0

V

I nput Voltage

Vee *
V in *

-0.3 - +7.0

Operating Temperature Range

Topr

0-+70

V
°c

Storage Temperature

T stg

-55 - +150

°c

Supply Voltage

• With respect to Vss (SYSTEM GNO)
(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions.
If these conditions are exceeded, it could affect reliability of LSI.
•

RECOMME-NDED OPERATING CONDITIONS
Symbol

min

typ

max

Unit

4.75

5.0

5.25

V

I nput Voltage

Vee *
V IH *

2.0

-

V

V IL *

-0.3

-

Vee
0.8

Operating Temperature

Topr

0

25

70

Item
Supply Voltage

V
°c

• With respect to Vss (SYSTEM GNO)

•
•

ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee = 5V ±5%, Vss = OV, Ta = O-+70°C, unless otherwise noted.)
min

typ

Input "High" Voltage

Item

Symbol
V IH

2.0

-

Input "Low" Voltage

V IL

Vss-0.3

lin

Test Condition

max

Unit

-

Vee
0.8

V

-

-

10

IJ.A

C]., lACK, BG, ClK,
Input leakage Current

BECo-~

REO o - RE0 3

V

Three·State (Off State)
Input Current

Al -A 7 , Do -Dis/As -A23 ,
AS, UDS, IDS, R/W, OAS,
DTACK, BGACK, OWN, DTC,
H IBYTE, 001 R, DBEN,
FC o -FC 2

ITSI

-

-

10

IJ.A

Open Drain (Off State)
Input Current

IREO, DONE

1001

-

-

20

IJ.A

Al - A 7 , Do - DIS/As - A 23 ,
R/W. UAS,
DTACK, BGACK, BR, OWN,
DTC, HIBYTE, DDIR, DBEN,
ACK o - ACK 3 , PClo - PCl 3 ,
FC o - FC 2

V OH

10H = -4001J.A

2.4

-

-

V

Al - A 7 , FC o - FC 2
Do - Dis/As - A 23 , AS, UDS,
lOS, RIW,DTACK. B~
OWN, DTC, HIBYTE, DDIR,
DBEN, ACKo - ACK 3 , UAS,
PCl o - PCL3. BGACK

VOL

10L = 3.2mA

-

-

0.5

VOL

10L =5.3mA

-

-

0.5

IRO, DONE

VOL

10L =8.9mA

-

-

0.5

-

1.4

2.0

W

-

15

pF

AS, lJDS, LOS,
Output "High" Voltage

Output" low" Voltage

Power Dissipation
Capacitance

666

Po
C in

f = 8 MHz,Vee =5.0 V
Ta = 25°C
Vin=OV,
Ta = 25°C, f= 1 MHz

~HITACHI

V

----------------------------------------------------------HD68450,HD68450Y
LOAD A

LOAD B

LOAD C

+5V

+5V

+5V

1.11k0

5000

r

7100

130pF
lS2074 If
or
Equivalent

Figure 1 Test Loads

• AC ELECTRICAL SPECIFICATIONS (Vee = 5V ±5%, VSS = OV, Ta = O-+70°C)
No.

Item

Unit

Symbol...

10

Frequency of Operation
Clock Period

250

500

167

500

126

500

100

500

Clock Width Low

115

250

75

250

55

250

45

250

Clock Width High

115

250

75

250

55

250

45

250

Clock Fall Time

10

10

10

Clock Rise Time

10

10

10

tCr
30

Asynchronous I"put Setup Time
Data in to DBEN Low

tOIDBL

DTACK Low to Data Invalid

tOTLOI

25

MHz

10
10
15

20

Address in to AS in Low
10

AS, OS in High to Address in Invalid

11

Clock High to OOIR Low

tCHDRL

12

Clock High to OOIR High

tCHORH

13

OS in High to DD1R High Impedance

tOSHORZ

14

Clock Low to OSEN Low

tCLOBL

15

Clock Low to OSEN High

tCLD8H

16

OS in High to OSEN High Impedance

17

Clock High to Data Out Valid (MPU read)

18

OS in High to Data Out Invalid

tDSH~2n

19

tSIHAIV

90

70

80

60

90

80

70

60

160

140

120

110

90

80

70

60

90

80

70

60

tOSHD8Z

160

140

120

110

tCHDVM

290

230

180

160

160

140

120

110

OS in High to Data High Impedance

tOSHOZ

20

Clock Low to OTACK Low

tCLOTL

21

-OS in High to OTACK High

tOSHDTH

22

OTACK Width High

tOTH

23

OS in High to OTACK High Impedance

tOSHOTZ

24

OTACK Low to OS in High

tOTLOSH

25

REO Width Low

26

REO Low to SR Low

27

Clock High to SR Low

tCHeRl

Clock High to SR High

tCHBRH

29

BG Low to SGACK Low

tBGLBL

30

BR Low to MPU Cycle End lAS in High)

tBRLASH

31

MPU Cycle End lAS in High) to SGACK I.OW

80

70

60

130

110

110

10

10

10
200

220

tRELBRL

28

90
160

10
180

160

2.0

2.0

2.0

2.0

500

334

250

200

Fig. 1Fig.8

90

80

90
4.5
4.5

5.5

70

80
4.5
4.5

5.5

60

70
4.5
4.5

clk. per.

60
4.5

5.5

4.5

elk. per.

5.5

32

REO Low to BGACK Low

tREQLBL

33

Clock High to BGACK High

tCHBL

34

Clock High to SGACK High

tCHBH

90

80

35

Clock Low to BGACK High Impedance

tCLBZ

120

100

80

70

36

Clock High to FC Valid

tCHFCV

140

120

100

90

37

Clock High to Address Valid

tCHAV

160

140

120

110
100

12.0

12.0
90

12.0
80

12.0
70
70

60

38

Clock High to Address/FC/Oata High Impedance

140

120

100

39

Clock High to Address/FC/Data Invalid

tCHAZn

40

Clock Low to Address High Impedance

tCLAZ

140

120

100

90

41

Clock High to UAS Low

tCHUL

90

80

70

60

42

Clock High to UAS High

tCHAZx

90

tCHUH

43

Clock Low to UAS High Impedance

tCLUZ

44

I:JAS High

tUHAI

45

Clock High to A:>, l:JS Low

tCHSL

80

46

Clock Low to OS Low Iwrite)

tCLOSL

47

Clock Low to AS, OS High

48

Clock Low to AS. OS High Impedance

49

to Address Invalid

80

120
50

70

100
40

60

80

70
20

30
70

60

80

70

60

55

tCLSH

90

80

70

60

tCLSZ

120

100

80

70

AS Width Low

55

545

350

255

195

420

265

190

145

285

180

150

105

tAVSL

50

40

30

20

tSHAZ

50

40

30

20

50

l:JS Width Low

51

AS, OS Width High

52

Address/FC Valid to

53

AS, OS High to Address/FC/Oata Invalid

54

Clock High to R/W Low

tCHRL

90

80

70

60

55

Clock High to R/W High

tCHRH

90

80

70

60

tOSL

AS,

OS Low

* Preliminary

elk. per.
elk. per.

60

(continued)

~HITACHI

667

HD68450,HD68450Y-------------------------------------------------------No.
56

Item

Clock Low to R/W High Impedance

Unit

Symbol
70

Address/FC Valid to R/W Low

100

40

20

10

R/W Low to OS Low (write)

285

170

120

90

60

40

50

20

59

OS High to R/W High

tSHAH

60

Clock Low to OWN Low

tCLOL

90

80

61

Clock Low to OWN High

tCLOH

90

80

70
70

62

Clock High to OWN High Impedance

tCHOZ

120

100

80

63

OWN Low to BGACK Low

tOLBL

50

64

30

40

30

40

tBHOH

50

OWN Low to UAS Low

tOLUL

50

Clock High to ACK Low

tCHACL

90

80

70

67

Clock Low to ACK Low

tCLACL

90

80

70

68

Clock High to ACK High

tCHACH

69

ACK Low to OS Low

70

OS High to

ACK High

90

60

70
20

BGACK High to OWN High

65

30

40

60

20

66

20
60
60

70

80

60

tACLOSL

230

140

100

80

tOSHACH

50

40

30

20

71

Clock High to HIBYTE Low

tCHHIL

90

80

Clock Low to HIBYTE Low

tCLHIL

90

80

70
70

60

72
73

Clock High to HIBYTE High

tCHHIH

90

80

70

60

74

Clock Low to HIBYTE High Impedance

tCLHIZ

120

100

80

70

75

Clock High to OTC""Low

tCHOTL

90

80

70

60

76

Clock High to

80

70

60

77

Clock Low 10 DTC High Impedance

tCLOTZ

78

DTC Width Low

tOTCL

79

DTC" High

tCHOTH

Fig.l Fig.8

90
120
230

80

100
105

147

95

70
80

30

50

60

20

DTC Low 10 OS High

tOTLOH

80

Clock High to DONE Low

tCHOOL

90

80

70

81

Clock Low 10 ~ Low

tCLOOL

90

80

70

60

82

Clock High to DONE High

tCHOOH

150

140

130

120

83

Clock Low to DDIR High Impedance

tCLDAZ

84

Clock Low to DBEN High Impedance

tCLOBZ

85

DOIR Low to OBEN Low

tORLOBL

50
50

86

100

120
120

80
30

70
20

30

40

70

80

100
40

60

20

bs....e-N High to OOIR High

tOBHORH

87

DBEN Low to Address/Data High Impedance

tOBLAZ

17

17

17

17

88

Clock Low to PCL Low (118 clock)

tCLPL

90

80

70

60

89

Clock Low to PCL High (118 clock)

tCLPH

90

80

70

60

90

PCL Width Low (1/8 clock)

tpCLL

91

OTACK Low to Data In (setup time)

tOALDI

92

OS High to Oat. Invalid (hold time)

tSHOI

93

OS High to DTACK High

tSHOAH

94

Data Out Valid to OS Low

tOOSL

95

4.0

4.0

4.0
200

150

115

240

160

120

90

30

15

15

Data I n to Clock Low (setup timel

tOICL

96

BEC Low to DTACK Low

tBECOAL

50

50

50

50

BEC Width Low

tBECL

2.0

2.0

2.0

2.0

98

Clock High to IRQ Low

tCHIRL

99

Clock High to

iRa High
DTC" Low

25

70

80

90
150

tCHIRH

lRead)

130

140

120

READY In to

tRALOTL

270

180

145

120

101

READ)' In to OS Low (Write)

tRALOSL

395

240

205

170

OS High to READY High

tOSHRAH

DONE In Low to DTACK Low

tOOLOAL

104

as High to DONE In High

tOSHOOH

105

Asynchronous Input Hold Time

240
50
15

• Preliminary

Figure 2

Input Clock Waveform

_HITACHI

120

160
50

50
240
15

90
50

120

160
15

elk. per.

60

100

103

elk. per.

4.0

320

97

102

668

BO

100

120

tCLRZ

57
58

90
15

----------------------------------------------------------HD68450,HD68450Y
28

29

30

31

32

33

34

35

36

1

23

24

25

26

27

28

29

30

CLK

A,

A,
AS
CS
R/IN
UDS
LDS

@

DDIR

,..--;

DBEN

~

As/Do
A23/D,.
Data In
DTACK

* Data are latched at the enq of clock 25,

Figure 3 AC Electrical Waveforms - MPU Read/Write
CLK

BGACK-------t-----------t--------~~W~·-_-__
~_i~
__
----~-------------------ri-----~,~----+J
f-oBUS

Cycle===1===~M~P~U~Cy~C~le=======::===j'-------II~r.;-I):-------~=:JD~M~A ~
Cycle
DTC· _ _ _-.-!.._______________-\I-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----'r---~

~

CLK
• REQ is sampled at the rising edge of ClK in cycle steal and Burst modes,
asserted while a BEC exception condition exists or DMAC is accessed by MPU,

.. S1f isn't

Figure 4 AC Electrical Waveforms - Bus Arbitration

$

HITACHI

669

HD68450,HD68450Y-------------------------------------------------------9

4

ClK

I

~
"
J..

Re d Cycle

FCo-FC2
:11

4r_

UAS

-

i

,I

4~

l.44

r-- r-.' I

AS

·1'1

\

~

I

- ..J

',ll

-!

lOS

1---'::. t---

!~
~

R/W

~

'~~"
1""-'-

ACKo
ACK 1
DONE

IRa'

,,~

r--

9
t=1

~

~-

I
I

-,';

t
-'"-1 I

.
"

!'--

7',

f-

1-1
l

-'

'\

"

L .JQ
.69)

4:7

'\
,,\
,.......,

'"1-

::?:l
'''I
I

"

Figure 5 AC Electrical Waveforms - DMA Read/Write (Single Cycle)

~HITACHI

I

\

r-K

-'" ~

--"~-

--..

::::,

. DTACK is sampled at the rising edge of CLK. This is different from HD68000 .
.. This timing is not related to DMA Read/Write (Single Cycle) sequence.

670

,',

,"

I

~
DTC

~
I

- -.-

-

~-

OBEN
HIBYTE

H

"~

\

~N

DOIR

F

~'" I' '

Write Cycle

)

~
AB/DoA23/D'5

OWN

10

J\J',J \jr\W ru"W""'uf\ J'J\J"'u

"'1

--------------------------------------------------------HD68450,HD68450Y
7" 8

ClK

10

4

F\J\J\jrLr\-r ~nf'~~W'tJL
t-n

'"

FCo-FC2

Write Cycle

Read Cycle

"
/

"A./DoA2l/D,.

""""II;.

/

'"

Data in

~

AS

-"

.J

~ """\

UDS

r---

lOS

r--

~

**** * ~

------<

...

~ f-

_-

~

~-

- "IlI

"""\

"

r\

r-- ~

r-- -""\
r-- h

J

In

\
~
r - -h

~

"i-_

~

14

-15)-

E

1"

_l'I!.

HI8YTE

/

~
I

'\.

~

\.

\

I

'----1
ACK

..
...
8EC

J

-'"t--

PCl

I

~
\

****

"

~

'"

~
~'

I

li

• Data is latched at the end of clock 7. This timing is the same as HD68000 .
.. This timing is not related to DMA Read/Write (Dual Cycle) sequence. This timing is only applicable when 1/8 clock pulse mode is selected .
••• This timing is applicable when a bus exception occurs .
.... If #6 is satisifed for both DTACK and BEG. #96 may be Ons
.... ·If the propagation delay of the external bidirectional buffer LS245 is less than 17nsec. a conflict may occur between the address output of the DMAC and
the system data bus. In this case. the output of DBrn must be delayed externally.

Figure 6 AC Electrical Waveforms - DMA ReadlWrite (Dual Cycle)

~HITACHI

671

HD68450,HD68450Y------------------------------------------------------2

3

4

5

6

8

9

10

1

2

4

3

5

6

8

9

10 11

12

13

14

ClK

X

X

>--<

)

A, - A,
XDo - XD,s
UAS

AS

)C

>-

<

'---J

'---J
\
--.I

"-

;--

\

/

UDS
lDS

R/IN

OWN

low

HIBYTE
DTACK
PCL(READY)
DTC
ACK o
ACK,
ClK
1

2

4

5

6

8

9

10

1

2

3

4

5

6

7

8

9

Figure 7 AC Electrical Waveforms - DMA Read/Write (Single Cycle with PCL)

672

~HITACHI

10

11

12

13

14

--------------------------------------------------------HD68450,HD68450Y
CLK
A, - A7

XDo - XD"
UAS

AS
'UDS
lDS

R/W
OWN
HIBYTE

low
High
'6.

DONE IN

CLK

3

4

5

6

8

• If #6 is satisfied for both DTACK and DONE, #103 may be Ons.

Figure 8 AC Electrical Waveforms - DONE Input
(NOTES for Figure 3 through 8)
1) Setup time for the asynchronous inputs BG, BGACK, CS, lACK, AS, UDS, lDS, and R/W guarantees their recognition at the next
falling edge of the clock. Setup time for BEC" - BEC" REOo - REO" PCl o - PCL" DTACK, and ~ guarantees their
recognition at the next rising edge of the clock.
2) Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts.
3) These waveforms should only be referenced in regard to the edge-to-edge measurement of the timing specifications. They are not
intended as a functional description of the input and output signals. Refer to other functional descriptions and their related diagrams
fOf' device operation.

~HITACHI

673

HD68450,HD68450Y---------------------------------------------------------• Address Bus (A I through A7)

• SIGNAL DESCRIPTION
The following section identifies the signals used in the
DMAC. In the definitions, "MPU mode" refers to the state
when the DMAC is chip selected by MPU. The term "DMA
mode" refers to the state when the DMAC assumes ownership of
the bus. The DMAC is in the "IDLE mode" at all other times.
Moreover, the DMA bus cycle refers to the bus cycle that is
executed by the DMAC in the "DMA mode".
NOTE) In this data sheet, the state of the signals is
described with these words: active or assert, inactive
or negate.
This is done to avoid confusion when dealing with a mixture
of "active-low" and "active-high" signals. The term assert or
assertion is used to indicate that a signal is active or true independent of whether that voltage is low or high. 111e term negate
or negation is used to indicate that a signal is inactive or false.
Vcc(2)

elK

Input/Output
Active-high

Three-statable

In the MPU mode, the DMAC internal registers arc accessed
with these lines and LOS, UDS. The address map for these
registers is shown in Table I. During a DMA bus cycle, Al -A7
are outputs containing the low order address bits of the location
being accessed.

•

Function Code (FC o through FC 2 )
Output
Active-high

Three-statable

These output signals provide the function codes during
DMA bus cycles. They are three-stated except in the DMA bus
cycles. They are used to control the HMCS68000 memories.

• Clock (ClK)
As-A23
00-015
Al-A7

Input

REOo
ACKo
PCLo

ES

This is the input clock to the HD68450, and should never be
terminated at any time. This clock can be different from the
MPU clock since HD68450 operates completely asynchronously.

~

REal
ACKl

Il5S

ODS
RW
OTACK

PEL,"

Em

RE02

~
~

H068450

OMAC

iRa

• Chip Select (CS)
Input
Active low

ACR2

1SCG

This input signal is used to chip select the DMAC in "MPlJ"
mode. If the CS input is asserted during a bus cycle which is
generated by the DMAC, the DMAC internally terminates the
bus cycle and signals an address error. This function protects
the DMAC from accessing its own register.

REa3

~

~

PCL3

•

Address Strobe (AS)
Input/Output
Active low

Three-statable

In the "M PU mode," this line is an input indicating valid
address input, and during the DMA bus cycle it is an output
indicating a valid address output from the DMAC on the address
bus.
The DMAC monitors these input lines during bus arbitration
to determine the completion of the bus cycle by the MPU or
other bus masters.

Vss (2)

Figure 9 Input and Output Signals

•
•

Upper Address Strobe (UAS)
Output
Active low

Address/Data Bus (Ag/Do through A 23 /D ls )
Input/Output
Active-high

Tlnee-statable

These lines are time multiplexed for the address and data
bus. The lines DDt R, DBEN. U AS and OWN are used to control the demultiplexing of the data and address lines externally.
Demultiplexing is explained in a later section. The bi-directional
data bus is used to transfer data between DMAC, MPU,
memory and I/O devices.
Address lines are outputs to address memory and I/O devices.

674

Three-statable

$

This line is an output to latch the upper address lines on the
multiplexed data/address lines. It is three-stated except in the
"DMA mode".

• Own (OWN)

HITACHI

Output
Active low

Three-statable

----------------------------------------------------------HD68450,HD68450Y
This line is asserted by the DMAC during DMA mode, and is
used to control the output of the address line latch. This line
may also be used to control the direction of bi-directional
buffers when loads on AS, LOS, UDS, R/W and other signals
exceed the drive capability. It is three-stated in the "MPU
mode" and the "IDLE mode"
•

In the "MPU mode", this line is an output indicating the
completion of Read/Write bus cycle by the MPU.
In the "DMA mode", the DMAC monitors this line to determine when a data transfer has completed. In the event that a
bus exception is requested, except for HALT, prior to or concurren t with DT ACK, the DT ACK response is ignored and the
bus exception is honored. In the "IDLE mode", this signal is
three-stated.

Data Direction (DDiR)
Outputs
Three-statable
Activc low (when data direction is input to
the DMAC)
Activc high (whcn the data direction is output
from the DMAC)

•

•

Output
Active low

•

Bus Grant (8(;)
Input
Active low

Three-statable

This line is used when the operand size is a byte in the single
addressing mode. It is asserted when data is present on the upper
eight bits of the data bus. It is used to control the output of the
bidirectional buffers which connect the upper eight bits of the
data bus with the lower eight bits. It is three-stated during the
"MPU mode" and the "IDLE mode."
•

This output line is used to request ownership of the bus by
the DMAC.

High Byte (HiBYTE)
Output
Active low

BEC;")

Bus Request (SR)

Three-statable

This line controls the output enable line of bidirectional
buffers on the multiplexed data/address lines. It is a three-stated
during the "IDLE mode".
•

through

These lines provide an encoded signal input indicating an
exceptional condition in the DMA bus cycle. See bus exception
section for details.

Data Bus Enable (DBEN)
Output
Active low

(BEe;;

Input
Active low

This line controls the direction of data through the bidirectional buffcr which used to demultiplex the data/address lines.
It is thrce-statcd during the "IDLE mode"
•

Bus Exception Controls

This line is used to indicate to the DMAC that it is to be the
next bus master. The DMAC cannot assume bus ownership until
both AS and BGACK becomes inactive. Once the DMAC acquires the bus, it does not continue to monitor the BG input.
•

Bus Grant Acknowledge (BGACI<)
Input/Output
Activc low

Three-statable

Read/Write (RIW)

This line is an input in the "MPU mode" and an output
during the "DMA mode". It is three-stated during the "IDLE
mode". It is used to control the direction of data flow.

Bus Grant Acknowledge (BGACK) is a bidircctional control
line. As an output, it is generated by the DMAC to indicatc that
it is the bus master.
As an input. BGACK is monitored by the DMAC. in limited
rate auto-request mode, to determine whether or not the
current bus master is a DMA device or not. BGACK is also
monitored during bus arbitration in order to assume bus ownership.

•

•

Input/Output
Active low (write)
Active high (read)

Three-statable

Upper Data Strobe (ODS), Lower Data Strobe (iJ5S)
Input/Output
Active low

Output
Active low

These lines are extensions of the address lines indicating
which byte or bytes of data of the addressed word are being
addressed. These lines combined corresponds to address line
Ao in table I.
•

Interrupt Request (iRQ)

Three-s ta ta ble

ll1is line is used to request an interrupt to the MPU.
•

I nterrupt Acknowledge (lACK)
Input
Active low

Data Transfer Acknowledge (DT ACK)
Input/Output
Active low

Three-statable

Open drain

This line is an input to the DMAC indicating that the current
bus cycle is an interrupt acknowledge cycle by the MPU. The

~HITACHI

675

HD68450,H.D68450Y---------------------------DMAC responds the interrupt vector of the channel with the
highest priority requesting an interrupt. There are two kinds of
the interrupt vectors for each channel: normal (NIV) or error
(EIV). lACK is not serviced if the DMAC has not generated
IRQ.
Channel Request (~ through

•

Sta~:~~~ster

(CSR)
(CER):
(OCR)
(OCR)i
c.n'::'~~:..., (SCR)
Con~:;r~,ster
(eCR)
Inter~'V.ctor (NIV)
e"., Reg",.,
Conl~v~:glster
co~:r~;:7stet

FfECl;)

In~er~~~~:~e.ctor

Input
Active low or falling edge

Channel Acknowledge

Peripheral Control Line

.... Add'H'

Funct,:seCOdes

Memory Tr.nsf., Counler

.... T"n,f.,Coun,.,

One set per
channel

i

(BTC) I
(MAR) I

(DAR)

Reo"'·'

(BAR)

J

(PCLo

through

PCi:; )
Table 1 Internal Register Addressing Assignments

Three-statable

Address Bits
Register
Channel Status Register
Channel Error Register
Device Control Register
Operation Control Register
Sequence Control Register
Channel Control Register
Memory Transfer Counter
Memory Address Register
Device Address Register
Base Transfer Counter
Base Address Register
Normal Interrupt Vector
Error Interrupt Vector
Channel Priority Register
Memory Function Codes
Device Function Codes
Base Function Codes
General Control Register

Open Drain

6

5 4
a
a

c
c
c
c
c
c
c
c
c
c

c
c
c
c
c
c
c
c
c
c

c
c
c

c
c
c

a
0
0

0
0 0
0 0
a

°

0 0
a 0
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1
1
1 1

1
1

3

2

1
0

a
0
a
a
a
1
1

a
1
1
1
1
a
1
1

0 1 R
0 0 R W
0 1 R W
1 0 R W
1 1 R W
1 b R W
s s R W
s R W
b R W
s
R W
0
R W
1
R W
0
R W
0
R W
R W
0
R W
0
1
R W

0 0

0
1
1

0
0
1
1

0

,
1

0
1
1
1
1

0
0
0
1

0

0

Mode
R w*

cc:OO·Channel :;O,Ol-Channel :; 1
1 a-Channel :; 2, 11·Channel :; 3,
ss :OO-high-order. 01·upper middle.
10-lower middle,ll-low-order
b: O-high-order.
1 -low-order
see Channel Status Register Section

*

Device Transfer Complete (DTC)

Output
Active low

Register Organization

The internal register addresses are represented in Table I.
Address space not used within the address map is reserved for
future expansion. A read from an unused location in the map
results in a normal bus cycle with all ones for data. A write
to one of these locations results in a normal bus cycle but no
write occurs.
Unused bits of the denned registers in Table 1 read as zeros.

As an output, this line is asserted concurrently with the
ACK x timing to indicate the last data transfer to the peripheral
device. As an input, it allows the peripheral device to request a
normal termination of the DMA transfer.

Three-statable

•

This line is asserted when the DMA bus cycle has terminated
normally with no exceptions. It may be used to supply the data
latch timing to the peripheral device. In this case, data is valid at
the falling edge of DTC.
INTERNAL ORGANIZATION

The DMAC has four independent DMA channels. Each channel has its own set of channel registers. These registers define
and control the activity of the DMAC in processing a channel
operation.

676

~

CUI1I~:ln~~~ISle, I(GCR) - g~e:;r

•

Input/Output
Active low

•

(DFC)
(BFC)
(MTC)

r-_ _ _ _ _oevlc. Address RegIster

Done (i5ONE)

•

Funce:~'~od.S

Memory Addresl Regllter

The four lines (pCL o - PCL 3 ) are mUlti-purpose lines which
may be individually programmed to be a START output, an
Enable Clock input, a READY input, an ABORT input, a
STATUS input, or an INTERRUPT input.
•

(CPR)

Figure 10 Internal Registers

These lines indicate to the I/O device requesting a transfer
that the request is acknowledged and the transfer is to be performed. These lines may be used as a part of the enable circuit
for bus interface to the peripheral.

Input/Output
Active low

I

I

(ACJ<;;" through ~)

Output
Active low

•

(EIV)

PMrltv Reg,s'.r

Func~i;:Codes (MFC)'

These lines are the DMA transfer request inputs from the
peripheral devices.
These lines are falling edge sensitive inputs when the request
mode is cycle steal. They are low-level sensitive when the
request mode is burst.
•

I

Device Control Register (OCR)

The OCR is a device oriented control register. The XRM bits
specifies whether the channel is in burst or cycle steal request
mode. The DTYP bits define what type of device is on the
channel. If the DTYP bits are programmed to buJ:IMCS6800
device, the PCL definition is ignored and the PCL line is an
Enable clock input. If the DTYP bits are programmed to be a
device with READY, the PCL definition is ignored and the PCL
line is a READY input. The DPS bit defines the port size (eight
or sixteen bits) of the peripheral device. (A port size is the largest
data which the peripheral device can transfer du~ DMA bus
cycle.) The PCL bits define the function of the PCL line. If the
DTYP bits are programmed to be HMCS6800 device, or Device
with ACK and READY, these definitions are ignored. The XRM

~HITACHI

----------------------------------------------------------HD68450,HD68450Y
bits are ignored if an auto-request mode (REQG
Operation Control Register) is selected.

= 00

or 01 in

o

4

6

XRM

DTYP

DPS

o

PCl

10
II

REQ line requests an operand transfer
Auto-request the first operand, external request for
subsequent operands
Bit 6 Not Used
•

Sequence Control Register (SCR)

The SCR is used to define the sequencing of memory and
device addresses.
XRM
00
aI
10
II
DTYP
00

aI
10
II
DPS

a
I
PCL
00
01
10
II
Bit 2
•

(EXTERNAL REQUEST MODE)
Burst Transfer Mode
(undefined, reserved)
Cycle Steal Mode without Hold
Cycle Steal Mode with Hold
(DEVICE TYPE)
HD68000 compatible device, explicitly addressed
(dual addressing mode)
HD6800 compatible device, explicitly addressed
(dual addressing mode)
Device with ACK, implicitly addressed
(single addressing mode)
Device with ACK and READY, implicitly addressed
(single addressing mode)
(DEVICE PORT SIZE)
8 bit port
16 bit port
(PERIPHERAL CONTROL LINE)
Status Input
Status Input with Interrupt
Start Pulse
Abort Input
Not Used

Operation Control Register (OCR)

The OCR is an operation control register. The DIR bit
defines the direction of the transfer. The SIZE bits define the
size of the operand. The CHAIN bits define the type of the
CHAIN mode. The REQG bits det1ne how requests for transfers
are generated.
6
DIR

DIR

o

SIZE

CHAIN

•

5

4

o

o

o

3

o

2
DAC

MAC

(MEMORY ADDRESS COUNT)
Memory address register does not count
Memory address register counts up
Memory address register counts down
(undefined, reserved)
(DEVICE ADDRESS COUNT)
Device address register does not count
Device address register counts up
Device address register counts down
(undefined, reserved)
6, 5, 4 Not Used

Channel Control Register (CCR)

TIle CCR is used to start or terminate the operation of a
channel. This register also determines if an interrupt request is
to be generated. Setting the STR bit causes immediate activation of the channel; the channel will be ready to accept request
immediately. The STR and CNT bits of the r.:gister cannot
be reset by a write to the register. The SAB bit is used to
terminate the operation forcedly. Setting the SAB bit will reset
STR and CNT. Setting the HLT bit will hal t the channel operation, and clearing the H LT bit wil resume the operation. Setting
the start bit must be done by a byte access. Otherwise, a timing
error occurs.
4

6

REQG

STR

(DIRECTION)
Transfer from memory to device
(transfer from MAR address to DAR address)
Transfer from device to memory
(transfer from DAR address to MAR address)
SIZE (OPERAND SIZE)
00
Byte (8 bits)
01
Word (\6 bits)
10
Long Word (32 bits)
II
(undefined, reserved)
CHAIN (CHAINING OPERATION)
00
Chain operation is disabled
aI (undefined, reserved)
10
Array Chaining
II
Linked Array Chaining
REQG (DMA REQUEST GENERATION METHOD)
00
Auto-request at transfer rate limited by General Control
Register (limited Rate Auto-Request)
aI Auto-request at maximum rate

a

MAC
00
aI
10
II
DAC
00
aI
10
II
Bits 7,

o

4

5

o

6

CNT

HlT

SAB

o

2
INT

o

o

o

(START OPERATION)
No operation is pending
I
Start operation
CNT (CONTINUE OPERATION)
No continuation is pending
a
Continue operation
I
HLT (HALT OPERATION)
a Operation not halted
I
Operation halted
SAB (SOFTWARE ABORT)
a Channel operation not aborted
I
Abort channel operation
(INTERRUPT ENABLE)
INT
a No interrupts enabled
Interrupts enabled
Bits 2, I, a Not Used
STR

a

•

Channel Status Register (CSR)

The CSR is a register containing the status of the channel.

~HITACHI

677

HD68450,HD68450Y-------------------------------------------------------7
CDC

654

I I I
eTC

NDT

ERR

3
ACT

I

o

2
0

PCT

PCS

COC

(CHANNEL OPERATION COMPLETE)
Channel operation incomplete
I
Channel operation complete
BTC (BLOCK TRANSFER COMPLETE)
o Block transfer incomplete
I
Block transfer complete
NDT (NORMAL DEVICE TERMINATION)
o No normal device termination by DONE input
I
Device ~erminated operation normally by DONE input
ERR (ERROR BIT)
o No errors
I
Error as coded in CER
ACT (CHANNEL ACTIVE)
o Channel not active
I
Channel active
PCT (PCLTRANSITION)
o No PCl transition occurred
I
PCl transition occurred
PCS (THE STATE OF THE PCl INPUT LINE)
o PCl "low"
I
PCl "High"
Bit 2 Not Used

o

• Channel Error Register (CER)
The CER is an error condition status register. The ERR bit of
CSR indicates if there is an error or not. Bits 0-4 indicate what
type of error occurred.

o

6

5

o

o

o

4
ERROR CODE

Error Code
00000 No error
0000 I Configuration error
000 I0 Operation timing error
0010 I Address error in MAR
00 II 0 Address error in DAR
00 II I Address error in BAR
0100 I Bus error in MAR
01010 Bus error in DAR
01011 Bus error in BAR
0110 I Count error in MTC
oI III Count error in BTC
10000 External abort
1000 I Software abort
Bits 7,6, 5 Not Used

CP (CHANNEL PRIORITY)
00 Priority level a
oI Priority level I
10 Priority level 2
II Priority level 3
Bit 7 through 2 Not Used
• General Control Register (GCR)
The GCR is used to define what portion of the bus cycles is
available to the DMAC for limited rate auto-request generation.
GCR is also used to specify the hold time for cycle steal mode
with hold.
6

5

4

o

o

o

3

o

2
BT

SR

BT (BURST TIME)
The number of DMA clock cycles per burst that the DMAC
allows in the auto-request at a limited rate of transfer is controlled by these two bits. The number is 2(BT+4) (two to the
BT+4 power).
BR (BANDWIDTH RATIO)
The amount of the bandwidth utilized by the auto-request at
a limited rate transfer is controlled by these two bits. The ratio
is 2(BR+ I) (two to the BR+ I powel').
The hold time for cycle steal mode with hold is defined to
be minimum of I sample interval and maximum of 2 sample
intervals. A sample intelval is defined to be 2(BT+BR+5) (two
to the BT+BR+5 power) clock cycles.
Bits 7 through 4 Not Used
• Address Registers (MAR, DAR, BAR)
Three 32-bit registers are utilized to implement the Memory
Address Register, Device Address Register, and the Base Address
Register. Only the least significant twenty-four bits are connected to the address output pins. The content of the MAR is
outputted when the memory is accessed in single or dual adressing mode. 111e content of the DAR is outputted when the
peripheral device is accessed. 111e contents of the BAR is outputted when reading chain information from memory in the
Array Chaining Mode or the Linked Array Chaining Mode. It is
also used to set the top address of the next block transfer in
Continue mode.
• Function Code Registers (MFC, oFC, BFC)
The DMAC has three function code registers per channel:
the Memory Function Code Register (MFC), Device Function
Code Register (DFC), and the Base Function Code Register
(BFC). The contents of these registers are outputted from FC o
through FC 2 lines when an address is outputted from MAR.
DAR, or BAR, respectively. The BFC is also used to set the
MFC for the transfer of the next data block in the Continue
mode.

• Channel Priority Register (CPR)
The CPR is used to define the priority level of the channel.
Priority level 0 is the highest and priority level 3 is the lowest
priority.

6

5

o

4

3

2

o

o

FC2

0

FC1

FCO

Bits 3 through 7 Not Used

o
678

6

5

4

3

2

o

o

o

o

o

o
CP

• Transfer Count Registers (MTC, BTC)
Each channel has two 16-bit counters: the Memory Transfer
Counter (MTC) and the Base Transfer Counter (BTC). The MTC

_HITACHI

--------------------------------------------------------HD68450,HD68450Y
counts the number of transfer words in one block, and is decreased by one for every operand transfer.
TIle BTC is used to count the number of data blocks in the
Array Chaining Mode. BTC is also used to set the number of
operands to transfer for the next data block in the Continue
Mode.

•

Read/Write of the DMAC Registers by MPU
The MPU reads and writes the DMAC internal registers and
controls the DMA transfer. Figure II indicates the timing diagram when the MPU reads the contents of the DMAC register.
The MPU outputs AI-An, FC o -FC 2 , AS, RjW, UDS, and LDS,
and accesses the DMAC internal register. The specific internal
register is selected by AI-A7, LDS and UDS. The CS and lACK
lines are generated by the external circuit with Ag-Au and
FC o-FC 2 . TIle DMAC outputs data on the data bus, together
with DDIR, DBEN and DTACK. The DDIR and DBEN control
the bidirectional buffer on the bus and the DTACK indicates
that the data has been sen t or received by the DMAC. Read
Cycle is eighteen CLKs. Figure 12 shows the MPU write cycle.
Write cycle is fifteen CLKs.
Note the following points.
( I) The clock reference shown in this figure is the DMAC input
clock.
(2) The DDIR and the DBEN arc three-stated at the beginning
which detects CS and the ending of the cycle.
(3) During the MPU read cycle, the DT ACK is asserted after
the data is valid on the system bus.
(4) During the MPU write cycle, the DDIR line will be driven
low to direct the data buffers toward to DMAC before the
buffers arc enabled.
(5) During the MPU write cycle, the DMAC will latch the data
before asserting DT ACK. Then it will negate DB EN and
DDIR in the proper order.
(6) After the MPU cycle and the LDS and the UDS arc negated
by the MPU, the DMAC will put DBEN, DDIR and the
address data lines to a high impedance state.
(7) DTACK will once go "High" and then to a high impedance
state after negating LDS and UDS.

•

Interrupt Vector Registers (NIV, EIV)
Each channel has a Normal Interrupt Vector register and an
Error Interrupt Vector register.
When an interrupt acknowledge cycle occurs. an interrupt
vector is outputted from one of these registers. If the error bit
(CSR) is set for the channel with interrupt pending, then content of EIV is outputted, otherwise content of NIV is outputted.
•

OPERATION DESCRIPTION

A DMAC channel operation proceeds in three principal
phases. During the initialization phase. the MPU sets the channel
control registers, supply the initial address and the number of
transfer words, and starts the channel. During the transfer
phase, the DMAC accepts requests for data operand transfers,
and provides addressing and bus controls for the transfers. The
termination phase occurs after the operation is completed.
This section describes DMAC operations. A description of
the MPUjDMAC communication is given first. Next, the transfer
phase is covered. including how the DMAC recognizes requests
and how the DMAC arranges for data transfer. Following this,
the initialization phase is described. The termination phase is
covered. introducing chaining, error signaling, and bus exceptions. A description of the channel priority scheme rounds out
the section.

ClK

AS

~ _ _ _ _ _ _ _ _ _ __

CS

~ ___________
~
....._ _

RW
UDS

~ ___________
~
....._ _

lOS

~____

DDIR

-.-r-----

DBEN

__________Jr------------~u:Q~
______~~---------~,--ill
1/1

As/Do - A23/D15

------- ~[«====)~»----

XDo-XD15
(External system data bus)

DTACK

~UoI.--_ _
~

___.J,___

--------~'llr(---~»;')...}- - - -

-----------

-------------\~U~__~nT'~
Figure 11 MPU Read from DMAC - Word

~HITACHI

679

HD68450,HD68450Y--------------------------------------------------------

Al -A23
FCo- FC2
AS

In

~

m

CS
RVV

,1\

m

ItJ
~

~

UDS

\\\

LDS

m

DDIR

,----,

DBEN

,-----

\\\

[J/

m

III'

-----<<<

As/Do- A23/D15

oj

»>

({C---

XDo-XD15
(External System Data Bus)

DTACK

,--

~S~

or

«C

»>

Figure 12 MPU Write to DMAC - Word

•

Bus Arbitration

The DMAC must obtain ownership ofthe bus in order to transfer
data. Figure 13 indicates the DMAC bus arbitration timing. It is
completely compatible with that of HD68000 MPU. The DMAC
asserts the Bus Request (BR) to request the bus mastership. The
MPU recognizes the request and asserts BG, then it grants the
ownership in the next bus cycle. After the end of the current cycle
CLK

(AS is negated), the MPU relinquishes the bus to the DMAC.
The DMAC asserts the bus grant acknowledge (BGACK) to
indicate that it has the bus ownership. A half clock before
BGACK is asserted, the DMAC asserts OWN. OWN is kept
asserted for a half clock after BGACK is negated at the end of the
DMA cycle. BR is negated one clock after BGACK is asserted.

f\.F\F\J\.J\JV\\f\..f\J\.JVV\.\J\J\f'J\...
min. 2 clocks
~

--¥
I

1.5 - 3.5 clocks

I

U

I------

2-3.5 clocks'

I

!
I

(68000 output)

~
BUS Cycle

,

I

OWN

o clock -

4.5 - 5.5 clocks

max. 12.5 clocks + 1MPU Cycle

U
~:==>---@
DMA Cycle
Cy cle

\

CLK

• This case assumes that no exception condition exists and DMAC isn't accessed by MPU.

Figure 13 DMAC Bus Arbitration Timing

680

$

I'--

Jf

i'----<..---f'---

1MPU Cycle .1

MPU Cycle

II

t'

BG

HITACHI

/

--------------------------------------------------------HD68450,HD68450Y
•

Device/DMAC Communication
Communication between peripheral devices and the DMAC is
accomodated by five signal lines. Each channel has REQ, ACK
and PCl, and the last two lines the DONE and DTC lines, arc
shared among the four channels.
(1) Request (REO)
The peripheral devices assert REQ to request data transfers.
Sec the "Requests" section for details.
(2) Acknowledge (ACK)
This line is used to implicitly address the device which is
transferring the data (This device is not selected by address
lines.) It is also asserted when the content of DAR is outputted during memory-to-memory transfer except for the autorequest mode at a limited rate or at the maximum rate.
(3) Peripheral Control Line (PCl)
The function of this line is quite flexible and is determined
by the OCR (Device Control Register).
The DTYP bits of the OCR define what type of device
is on the channel. If the DTYP bits are programmed to be a
HMCS6800 device, the PCl definition is ignored and the PCl
line is an Enable clock 0:: clock) input. If the DTYP bits arc programmed to be a device with READY, the PCl definition as
ignored and the PCl line is a ready input.
PCl As a Status Input
The PCl line may be programmed as a status input. The
status level of this line can be determined by the PCS bit in the
CSR, regardless of the PCl function determined by the DCR.
If a negative transition occurs and remains stable for a minimum of two clocks, the PCT bit of the CSR is set. This PCT
bit is cleared by resetting the DMAC or the writing "I" to the
PCTbit.
PCl As an Interrupt
The PCl line may be programmed to generate an interrupt
on a negative transition. This enables an interrupt which is requested if the PCT bit of the CSR is set. When using this function, it is necessary to reset the PCT bit in the CSR before the
PCL bit in the DCR is set to interrupt. in order to avoid
assertion of IRQ line at this time.
PCl As a Starting Pulse
The PCl line may be programmed to output a starting pulse.
This active low starting pulse is outputted when a channel is
activated, and is "low" for a period of four clock cycles.
PCl As an Abort Input
The PCl line may be programmed to be a negative transition
above input which terminates an operation by setting the external abort error in CER. It is necessary to reset the PCT bit in
the CSR before activating the channel (Setting the ACT bit of
CCR) so that the channel operation is not immediately aborted.
PCl As an Enable Clock (E Clock) Input
If the DTYP bits are programmed to be a HMCS6800 device,
the PCl definition is ignored and the PCl line is an Enable
Clock input. The Enable clock downtime must be as long as five
clock cycles, and must be high for a minimum of three DMAC
clock cycles, but need not be synchronous with the DMAC's
clock.
PCl As a READY Input
If the DTYP bits are programmed to be a~ice with
READY, the PCl definition is ignored and the PCl line is a
READY input. The READY is an active low input.
(4) DONE (DONE)
This line is an active low Input/Output signal with an open
drain. It is asserted when the memory transfer count is exhausted in a single block transfer. In the chaining operation,
DONE is asserted only at the last transfer to the peripheral

device of the last data block. In the continue mode, DONE is
asserted for each data block. It is asserted and negated in coincident with the ACK line for the last data transfer to the
peripheral device. It is also outputted in coincident with the
ACK line of the last bus cycle, in which the address is outputted
from the DAR, in the memory-to-memory transfer (dual
addressing mode) that uses the ACK line.
The DMAC also monitors the state of the DONE line during
the DMA bus cycle. If the device asserts DONE during ACK
active, the DMAC will terminate the operation after the transfer
of the current operand. If DONE is asserted on the first byte of
2 byte operation or the first word of long word operation. the
DMAC does not terminate the operation until the whole operand transfer is completed. If DONE" is inserted. then the D MAC
terminates the operation by clearing the ACT bit of the CSR,
and setting the COC and NDT bits of the CSR. If both the
DMAC and the device assert DONE, the device termination is
not recognized, but the channel operation does terminate.
DONE is outputted again for the retry exceptions bus cycles.
(5) Data Transfer Complete (DTC)
DTC is an active low signal which is asserted when the actual
data transfer is accomplished. It is also asserted in the bus cycle
when a chain information is read from memory in the Chaining
mode. However, if exceptions arc generated and the DMA bus
cycle terminates, DTC is not asserted. DTC is asserted one half
clock before LDS and UDS are negated, and negated one half
clock after LDS and UDS arc negated.
•

Requests
Requests may be externally generated by circuitry in the
peripheral device, or internally generated by the auto-request
mechanism. The REQG bits of the OCR determine these modes.
The DMAC also supports an operation in which the DMAC
auto-requests the first transfer and then waits for the peripheral
device to request the following transfers.
(1) Auto-request Transfers
The auto-request mechanism provides generation of requests
within the DMAC. These requests can be generated at either of
two rates: maximum-rate and limited-rate. In the former case,
the channel always has a request pending.
The limited rate auto-request functions by monitoring the
bus utilization.
Limited-rate Auto-request
TIME -+
Previous
Sample Interval

Next
Sample Interval

Figure 14 DMAC Sample Intervals
In the limited-rate auto-request the DMAC devides time into
equal length sample intervals by counting clock cycles. The end
of one sample interval makes the beginning of the next. During
a sample interval, the DMAC monitors by means of BGACK pin
the system bus activity of the DMAC and other bus master
devices. At the end of the sample interval, decision is made
whether or not to perform the channel's data transfer during
the next sample interval. Namely, based on the activity of
the DMAC or other bus master devices during the current
sample interval, the DMAC allows limited-rate auto-requests for
some initial portion of the next sample interval.
The length of the sample interval, and the portion of the
sample interval during which limited-rate auto-requests can be

~HITACHI

681

HD68450,HD68450Y---------------------------------------------------------clock cycles.
The DMAC uses the BGACK to differentiate between the
MPU bus cycle and DMAC or other bus master devices. If
BGACK is active, then the DMAC assumes that the bus is used
by a DMAC or other bus master devices. If it is inactive, then
the DMAC assumes that it is used by the MPU.
Maximum-rate Auto-request
If the REQG bits in the OCR indicate auto-request at the
maximum rate, the DMAC acquires the bus after the start bit is
set and keeps it until the data transfer is completed.
If a request is made by another channel of higher priority,
the DMAC services that channel and then resumes the autorequest sequence. If two or more channels are set to equal
priority level and maximum rate auto-request, then the channels
will rotate in a "round robbin" fashion.
If the HMCS68000 compatible device is connected to a
channel, the i\CX line is held inactive during an auto-request
operation. Consequently, any channel may be used for the
memory-to-memory transfer with the auto-request function in
addition to the operation of data transfer between memory and
peripheral device with using' the REQ pin. Refer to Figure 15
for the timing of the memory-to-memory transfer. In this mode,
the ACK,HIBYTE and DONE- outputs arc always inactive.

made (the limited-rate auto-request interval) are controlled by
the BT and BR bits in the GCR. The length in clock cycles of
the limited-rate auto-request interval is 2(BT+4) (2 raised to the
BT+4 power). For example, if BT equals 2 and the DMA utilization of the bus was low during the previous sample interval,
then the DMAC generates the auto-request transfers during the
first 64 clock cycles.
The ratio of the length of the sample interval to the length
of the limited-rate auto-request interval is controlled by the BR
bits. The ratio of the system bus utilization of the MPU to
other bus master devices including he DMAC is 2(BR+ I) (2
raised to the BR+ I power). If the fraction of DMA clock cycles
during the sample interval exceeds the programmed utilization
level, the DMAC will not allow limited-rate auto-requests during
the next sample interval.
For example, if BR equals 3, then at most one out of 16
clock cycles during a sample interval can be used by the DMAC
and other bus master devices, and still the DMAC would allow
limited rate auto-request during the next sample interval.
Therefore, from the viewpoint of long period, the ratio of the
system bus utilization of the MPU to I/O devices including the
DMAC is about 16: I. The sample interval length is not a direct
parameter, but it is equal to 2(BT+BR+5) clock cycles. Thus,
the sample interval can be programmed between 32 and 2048

ClK
1

FCo-FC2
Al -A7

2 3

xm
XIO
rm=
-::JJ~1I;:::::=====~~=======:::;;~=======
-::JJ.u"
_______ YJll
YJ.ll
rue:..

A /D

Data In
Data Out
Address Out
Address Out
Data In
Adrid~re~s~sO~ut~~~~~~~--~~~~I~~--~~~~----~ft~~~~n~~~~~~

YJlI
XIII
Vn
'IJO
~
A:3/~~-::JJ~n-;:;:;;v.~Z~I====;;;r:#\----J":#;;:;:::=====;~---I''::;;;:::::==~r:::,
XDo - XD 15l1I/lD}--J..W
mm}--(f/ID
llllll.)llll}----(111.
~ ---m
m~~=====~~

(External System Data

UAS

'UL.JIJ

W--Lll

AS
UDS

'"
\\\

lDS

\\\

m
11/
11/

~

10

'UL.JIJ
\\\

\\\

III

\\\

II,

~~

lZ1

~~~

ill

\\\

m

~~
OWN==~~--------~====================~----------nT===
R/W

\\\

DDIR

III

III

01

'"

HIBYTE

~~\

DTACK

m

~

\\\

ll7

\\\

UL.JJJ

DTC

~

\\\

DBEN-----~~----~~--~

0.7

UL.JJJ

~\

~
~

ACK
ClK
2 3

4

5

6

7 8

Read One Word
From Memory

9 10
Write One Word
to Memory

Figure 15 Memory-to-Memory Transfer
Read-Write-Read Cycles

682

~HITACHI

Read One Word
From Memory

------------------------------------------------------HD68450,HD68450Y
(2) External Requests
If the REOG bits of the OCR indicate that the REO line
generates requests. the transfer requests are generated externally. The request line associated with each channel allows the
device to externally generate requests for DMA transfers. When
the device wants an operand transferred, it makes a request by
asserting the request line. The external request mode is determined by the XRM bits of the OCR, which allows both burst
and cycle steal request modes. The burst request mode allows a
channel to request the transfer of multiple operands using
consecutive bus cycles. The cycle steal request mode allows
a channel to request the transfer of a single operand. The

following is the description of the burst and the cycle steal
modes.
Burst Request Recognition
In the burst request mode, the REO line is an active low
input. The level sampled at the rising edge of the clock. Once
the burst request is asserted, it needs to be held low until the
first DMA bus cycle starts in order to insure at least one data
transfer operation. In order to stop the burst mode transfer
after the current bus~le, the REO line has to be negated
one clock before the DTC output clock of this cycle. Refer to
Figure 16 or the burst mode timing.

REQ
BR
BG--~~~--~~--~
BGACK------~r---~I~~

~~~;;~~~::~~~~~~:=~~~;=:=:=:=~J

BUS
CYCLES=

ACK ____- +____~__-F~==~~==1\n

MPU cycle

-+-

Idle

-+---

DMA cycle

-+

MPU cycle
or Idle

--r- DMA cycle --j--

Idle

Figure 16 Burst Mode Request Timing
(Only one channel is active)

Cycle Steal Request Recognition
In the cycle steal request mode. the peripheral device requests the DMA transfer by generating an falling edge at the
REO line. 111e REO line needs to be held "low" for at least 2
clock cycles. In the cycle steal mode, if the REO line changes
from "Higll" to "Low" between ACK output and one clock before the clock that outputs DTC, then the next DMA transfer
is performed without relinquishing the bus. If the bus is not
relinquished, then maximum of 5 idle clocks is inserted between
bus cycles. Refer to Figure 17 for the request timing of the
cycle steal mode. If the XRM bits specify cycle steal without hold, the DMAC will relinquish the bus. If the XRM bits
specify cycle steal with hold, the DMAC will retain ownership.
The bus is not given up for arbitration until the channel opera-

tion terminates or until the device pauses. The device is determined to have paused if it does not make any requests during
the next full sample interval. The sample interval counter is free
running and is not reset or modified by this mode of operation.
The sample interval counter is the same counter that is used for
Limited Rate Auto Request and is programmed via the GCR.
Figure 18 shows the request timing in the cycle steal bus
hold. If the REO is inputted during the hold time, the ACK
is ou tpu tted after a maximum of 7.5 clock cycles from the
picked-up clock. On the cycle steal with hold mode, the DMAC
will hold the bus even when the transfer count is exhausted and
the last data has been transferred. If DMA transfer is requested
from other channels during this period, they are executed
normally.

micro cleanup
'~PU cycle

-+-

Idle

DMA cycle

Figure 17 Cycle Steal Mode Request Timing

~HITACHI

683

HD68450,HD68450Y--------------------------------------------------------

lJ1l1J1IUUU1JUlWl)lJU1JU1.I1IlJUlJ1JlJ1

CLKJUl.

R~LJ
__ ,
BG

--_

BGACK
BUS
CYCLES
ACK

u

,

(

f~:

\~.~---~n!_-_..JI
\

I'

II

I

--------fr:.....--,

~:

Hold the bus
U

max. 7.5 clocks:
r-----"
~ _
I

max. 5 c Ioe ks

~:

--~
~==~::::r~:"J==~::::s::::~~=~=
- ~t----\
}---f '-::;:;----',r---~~t:.~::;;_'_ _..JrII

r

\\

_ _ _ _-fI'~J

-_

U

"

\

rr-

Figure 18 Cycle Steal Bus Hold Mode Request Timing

Request Recognition in Dual-address Transfers
In the following section dual-address transfers is defined.
Dual address transfer is an exception to the request recognition
rules in the previous paragraphs. In the cycle steal request mode,
when there are two or more than transfers between the DMAC
and the peripheral device during one operand transfer. the request is not recognized until the last transfer between the
DMAC and the I/O device starts.
(3) Mixed Request Generation
A single channel can mix the two request generation
methods. By programming the REQG bits of the OCR to "II",
when the channel is started, the DMAC auto-requests the first
transfer. Subsequent requests are then generated externally by
the device. The ACK and PCl lines perform their normal functions in this operation.
•

Data Transfers
All DMAC data transfers are assumed to be between memory
and the peripheral device. The word "memory" means a 16-bit
HMCS68000 bus compatible device. By programming the OCR,
the characteristics of the peripheral device may be assigned.
Each channel can communicate using any of the following
protocols.
DTYP

00
01
IO

II

684

Device Type
HMCS68000 compatible deViCe}
HMCS6800 compatible device
Device with ACK
}
Device with ACK and READY

(1) Dual Addressing
HMCS68000 and HMCS6800 compatible devices may be
explicitly addressed. This means that before the peripheral
transfers data. a data register within the device must be addressed. Because the address bus is used to address the peripheral,
the data cannot be directly transferred to/from the memory
because the memory also requires addressing. Instead, the data
is transferred from the source to the DMAC and held in an
internal DMAC holding register. A second bus transfer between
the DMAC and the destination is then required to complete
the operation. Because both the source and destination of the
transfer are explicitly addressed, this protocol is called dualaddressed.
HMCS68000 Compatible Device Transfers
In this operation. when a request is received, the bus is
obtained and the transfer is completed using the protocol as
shown in Figures 19 and 20. Figures 21 through 24 show the
transfer timings. Figure 21 and 24 show the operation when
the memory is the source and the peripheral device is the destination. Figures 22 and 23 show the transfer in the opposite
direction. The peripheral device is a 16-bit device in Figures 21
and 22. and a 8-bit device in Figures 23 and 24.

Dual AddreSSing
Single Addressing

$

HITACHI

----------------------------------------------------------HD68450,HD68450Y
HMCS68000 Device

DMAC
Address Device
1) Set R/W to Read
2) Place Address on AI - An
3) Place Function Codes on
FCo - FC 2
4) Assert Address Strobe (AS)
5) Assert Upper Data Strobe
(uDS) and Lower Data
Strobe (LOS)
6) Assert Acknowledge (ACK)

I
prese)t Data
1) Decode Address
2) Place Data on D. - 0 ..
3) Assert Data Transfer
Acknowledge (OT ACK)

I

f
Acquire Data
1) Load Data into Holding
Register
2) Assert Device Transfer
Complete (DTC)
3) Negate DDS and LOS
4) Negate AS, ACK and DTC
Terminate Cycle
1) Remove Data from Do - 0 ..
2) Negate DTACK

,

t

Start Next Cycle

Figure 19 Word Read Cycle Flowchart HMCS68000 Type Device
DMAC

HMCS68000 Device

Address Device
1) Place Address on AI - A 23
2) Place Function Codes on
FC. - FC 2
3) Assert Address Strobe (AS)
4) Set R/W" to Write
5) Place Data on Do - 0 ..
6) Assert Acknowledge (ACK)
7) Assert Upper Data Strobe
(UDS) and Lower Data
Strobe (LOS)

~'----------------------------------------------"

Accept Data
1) Decode Address
2) Store Data on Do - 0 15
3) Assert Data Transfer
Acknowledge (OTACK)

I

f

1)
2)
3)
4)
5)

Terminate Output Transfer
Assert Device Transfer
Complete (DTC)
Negate UDS and LOS
Negate AS, ACK and DTC
Remove Data from Do - 0 ..
Set RM to Read
I

.

t

Terminate Cycle
1) Negate DTACK

I

f

Start Next Cycle

Figure 20 Word Write Cycle Flowchart HMCS68000 Type Device

$

HITACHI

685

HD68450,HD68450Y-------------------------------------------------------ClK

As/Do
-A23/D15
XDo-XD,s
(External System Data Bus)
UAS

AS
UDS

lOS

RW

OWN
DDiR
DBEN
HIBYTE
OTACK

m

\\\

"\

III

nr

\\\

-----'1Jill

t>iC

ACK
OONE
ClK
1

2

3 4

5 6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

--r-- Read One Word ----j--From Memory

----t-

Write One Word
To Device
The Last Transfer

Figure 21 Dual Addressing Mode, Read/Write Cycle,
Destination = 16-bit Device, Word Operand

ClK
10 11 12 13 14 15 16 17 18 1920 21 22

-=:::Jill

As/Do
-A23/ D '5
XDo-XD,s
(External System Data Bus)
UAS

AS
UDS
LOS

XIII

'flIC:.

Add ress Outrtr-....;;D;,..;;;a..;,;;ta;..,;l.;,:.n---..;.Address Outm-_....;;D..;;a..;.;ta_O~u;;.;t~_

'IlIL:.

~....
II _ _ _ _

~I

-::::::::JJl>-.:DO-XD'5
(External System Data Bus)

UAS

AS

UDS

lDS

RW
OWN

Low

DDIR
DBEN

High
High

HIBYTE

High

DTACK

~

ur

/0
\\\
ill ------~Il~/------~======~--

ACKo

ACK,

~--~~~\======~~mr~

'&.....JlJ

DTC
ClK

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
-+-Memory to Device ---+--Device to Memory
I
Channel 0
Channel 1

Figure 30 Single Addressing Mode with 16-Bit Devices as
Source and Destination (Read-Write Cycles)

ClK

,

BGACK

an

FCo-FC2
At-A7
Aa/Do-A23/D'5
XDo-XD'5

(External System Data Bus)

Vn

QII
JIll
------~-------~----------------QIII
lmmU/f}--(}~~II~1~~~~£:===

----~~
AS ------'~

~

UAS

~

UDS

~

lDS
OWN

\\\

0/
\\\

RjW

/Ir'-----

----- ITT'----

flT\-,

------.

DDIR
DBEN

ITT'----\\\
oumnw
001111111
\\\
\lL....1lJ
ACKo ----------_\~\\~======~'~/~/~~~~----------------------

HIBYTE

DTACK
DTC

\\\

ACK,

ClK
- - Idle ----t--- Memory to Device
Channel 0

--t-- Device to Memory --+-

Idle

Channel 1

Figure 31 Single Addressing Mode with 8-Bit Device as
Source and Destination (Read-Write Cycles)

~HITACHI

691

HD68450,HD68450Y------------------------------------------------------Device with ACK and READY Transfers
Under this protocol, the communication between peripheral
device and the DMAC is performed using a three signal
REQ/ACK/READY handshake. The READY input to the
DMAC is provided by the PCl line. The READY line is active
low. When a request is generated using the request method
programmed in the control registers, the DMAC obtains the bus
and asserts ACK to notify the device that the transfer is to take
place. The DMAC waits for READY (pCl input), which is a
response from the device, in addition to DT ACK which is a
response from memory.
When the DMAC accepts both signals, it terminates the transfer. Refer to Figures 33 and 34 for the flowcharts of the data
transfer between memory and the device with ACK and
READY. Refe~ to Figure 35 for the transfer timing of the 8-bit
device. When the data transfer is from memory to a device, data
is valid from the assertion of DT ACK to the negation of lOS
and UDS. DTC is asserted a half clock before lOS and UDS are
negated, so this line may be used for latching the data by the
peripheral device. In this case, READY (pCl input) indicates
that the device has received the data. Both DT ACK and READY
(pCl input) signals are needed for terminating the DMA cycle.
When the data transfer is from the device to memory, data
must be valid on the bus before the DMAC asserts lOS and
ODS. Therefore, READY (pCl input) is used as the signal to
indicate that the peripheral device has outputted the data on the
bus. When the DMAC detects PCl (READY input), then it

DMAC

1)
2)
3)
4)
5)
6)

asserts lDS and UDS. After asserting lOS and DDS, the DMAC
terminates the cycle when DT ACK signal from the memory is
detected.
When Array Chain or Link Array Chain is set in Device with
ACK and READY Transfer mode, READY input is also necessary during DMA bus cycles for reading the chain information
from memory. The circuit as shown in Figure 32 may be used
in order to generate READY input when reading the chain
information from memory.

ACK

1-----------.......- - - ACK

HD68450
DMAC

~-----------------

I~

\\\

[ffi;

32

f,

R/W
UDS

31

H

~~~

lACK

30

~f

A,s/Ds-A23/D,s
As/Do-Als/D7
XDo-XD,s
(External System Data Bus)

Ss{lZll

)

H-

HD68000

MPU

MAR
DAR

*
peripheral device

memory
address A
block A

address

}

BAR top address of the table
MTC
BTC

transfer
count A

*

g~i~~¥~a~~f~I~~ks

memory
address

B
transfer
count B

* to be loaded from the array table
block B
)

1..--"""-

-

Note: The number of data blocks being
transferred in this example is 3.
peripheral device

Figure 37 Transfer Example of the Array Chaining Mode
Linked Array Chaining

This type of chaining uses a list in memory consisting of
memory address, transfer counts, and link addresses. Each entry
in the chain list is ten bytes long, and consists of four bytes of
memory address, two bytes of transfer count and four bytes of
link address. The address of the first entry in the list is in the
base address register, and the base transfer counter is unused.
Before starting any block transfers, the DMAC fetches the
entry currently pointed to by the base address register. The
address information is placed in the memory address register,
the count information is placed in the memory transfer counter,

and the link address replaces the current contents of the base
address register. The channel then begins a new block transfer.
As each chaining entry is fetched, the update base address
register is examined for the terminal link which has all 32 bits
equal to zero. When the new base address is the terminal address, the chain is exhausted, and the entry just fetched determines the last block of the channel operation.
An example of the linked array chaining mode operation and
the memory format for supporting it is shown is Figure 38.
In Figure 38, the DMAC transfers data blocks in the order of
Block A, Block B, and Block C. In the linked array chaining

~HITACHI

699

HD68450,HD68450Y-------------------------------------------------------memory
Bit 15

"......---

Bit 0

memory address B (H)

link address X ......

memory address B(L)
transfer count B
link address Y (H)
link address Y(L)

memory address C (H)

link address Y ......

linked array table ......

memory address C(L)
transfer count C
"All 0" terminator
.. All 0" terminator
top address of
the table

,
memory address A(H)
memory address A (L)
transfer count A
link address X(H)

----

link address X(L)

l,....HD68450
DMAC

-

..-- memory
address C

HD68000
MPU

MAR

::>

block C

*

DAR

peripheral device address

BAR

top address of the table

MTC
BTC

*

(not used)

¢::=>

} ",",f.«,"", C

memor~

address A
block A

J ,,,",f., ,,"",A

:
• to be loaded from the linked array table

memor~

address B
block B

v-

peripheral
device address

~

---- ----------~

--+

peripheral device
or memory

1----

Figure 38 Transfer Example of the Linked Array Chaining Mode

700

~HITACHI

} ","d., """' •

--------------------------------------------------------HD68450,HD68450Y
mode, the BTC is not used. When the DMAC refers to the linked
array table, the value of the BFC is outputted as the function
code. The values of the function code registers are unchanged
by the linked array chaining operation.
This type of chaining allows entries to be easily removed or
inserted without having to reorganize data within the chain.
Since the end of the chain is indicated by a terminal link, the
number of entries in the array need not be specified to the
DMAC.
The linked array table must start at an even address in the
linked array chaining mode. Starting the table at an odd address
results in an address error. If "0" is initially loaded to the
MTC, the count error is signaled. Because the MPU can read
all of the DMAC registers, all necessary error recovery information is available to the operating system.
The comparision of both chaining modes is shown in Table 8.
Table 8 Chaining Mode Address/Count Information
Chaining Mode

Base Transfer
Counter

Base Address
Register

Array Chaining

address of the
array table

number of data
blocks being
transferred

Linked Array
Chaining

address of the
linked array
table

(unused)

Completed
When
Base Transfer
Count = 0
Linked
Address = 0

(4) Bus Exception Conditions

The DMAC has three lines for inputting bus exception conditions called BEC o , BEC t , and BEC 2 • The priority encoder can
be used to generate these signals externally. These lines are
encoded as shown in Table 9.
Table 9
Exception Condition

BEC 2

BEC t

BEC o

1

1

1

No exception condition

1

1

0

Halt

1

0
0

1

Bus error

0

Retry

1

1

Relinquish bus and retry

1

0

(undefined, reserved)

0
0

1

(undefined, reserved)

0

Reset

1

0
0
0
0

In order to guarantee, reliable decoding, the DMAC verifies that
the incoming code has been statable for two DMAC clock cycles
before acting on it. The DMAC picks up BEC o-BEC 2 at the
rising edge of the clock. If BEC o-BEC 2 is asserted to the undefined code, the operation of the DMAC does not proceed.
For example, when the DMAC is waiting for DTACK, inputting
DTACK does not result in the termination of the cycle if BEC oBEC 2 is asserted to the undefined code. In addition, when the
transfer request is received, BR is not asserted if the BEC oBEC; is not set to no exception condition.
If exception condition, except for HALT, is inputted during
the DMA bus cycle prior to, or in coincidence with DT ACK,
the DMAC terminates the current channel operation immediately. Here coincident means meeting the same set up requirements for the same sampling edge of the clock. If a bus exception condition exists, the DMAC does not generate any bus
cycles until it is removed. However, the DMAC still recognizes
requests.
Halt

The timing diagram of halt is shown in Figure 39. This
diagram shows halt being generated during a read cycle from the
68000 compatible device in the dual addressing mode. If the
halt exception is asserted during a DMA bus cycle, the DMAC
does not terminate the bus cycle immediately. The DMAC
waits for the assertion of DT ACK before terminating the
bus cycle so that the bus cycle is completed normally. In
the halted state, the DMAC puts al\ the control signals to high
impedance and relinquishes the bus to the MPU. The DMAC
does not output the BR until halt exception is negated. When
halt exception is negated, the DMAC acquires the bus again and
proceeds the DMA operation. In order to insure a halt exception operation, the BEC lines must be set to halt at least until
the assertion of DTC.
If the DMAC has the bus, but is not executing any bus
cycle, the DMAC relinqUishes the bus as soon as halt exception
is asserted.

~HITACHI

701

HD68450,HD68450Y------------------------------------------------------CLK
AID BUS

DAS
AS
UDS
LOS

R/W
OWN

------------------------~~
____________________

t~~

DDIR

tmEN

-W~~~

_______________ _

____________w~~

~-~-----------~
\\\

'LIII"\w~

____________~m--ij

~~~

_________mr__

~....
&\______.J.<~w f

HALT

(BECo-BEC21* ____________________

BGACK
BR

.u~~~

__________________

HI

i~

....._________IH

'~

BG
ClK
4567

8

9101112131415161718192021222324252627282930313233

~~~

Reoadevl'ce
from
Halt Asserted

• BECo

-

?ther
Masterl
Rearbitration
---"'I~OMA Halted

to

-il---

~~~:ry
OMA cycle

BEC. = (011)

Figure 39 Halt Operation

Bus Error
The bus error exception is generated by external circuitry
to indicate the current transfer cannot be successfully com-'
pleted and is to be aborted. The recognition of this exception
during a DMAC bus cycle signals the internal bus error condition for the channel for which the current bus cycle is being
run. As soon as the DMAC recognizes the bus error exception,
the DMAC immediately terminates the bus cycle and proceeds
to the error recovery cycle. In this cycle, the DMAC adjusts the

702

values of the MAR, the DAR, the MTC and the BTC to the
values when the bus error exception occurred. 25 clocks are
required for the error recovery cycle in the single addressing
mode and in the read cycle of the dual addressing mode. 29
clocks l!re required in the write cycle of the dual addressing
mode. If the DMAC does not have any transfer request in the
other channels after the error recovery cycle, the DMAC relinquishes the bus.
The diagram of the bus error timing is shown in Figure 40.

~HITACHI

------------------------------------------------------------HD68450,HD68450Y

ClK
K -________________~~~~t~t

AID BUS

I~

UAS
~

AS
UDS
lOS

_______

__________

~m

l~

UL- _ _ _--MJ
m
\}\
______81
\\\

JJ
JJ

l~
I~

\\\_ _ _ _ _ _ _--llJ~1

R/W
OWN

DDIR

---111
t\ll\\_ _ _ _ _ _ _ _
~1

DBEN
HIBYTE

DTACK

---'1/

,nn,\\ \\ \\ \\ \\\\\YIn

DTC
~w."_ _ _ _ _ _ _..JJ.j~\
Bus Error
(BECo- BEC2)'

ClK
1 2 3 4 5 6 7 8 9 10111213141516171819

--+-

Berr on Write to Device

~
I.

,.
Error
Recovery Cycle**

Other Channels** *

* BECo-BEC , = (101)
** In the single addressing mode and in the read cycle of the dual addressing mode: 25 clocks
In the write cycle of the dual addressing mode: 29 clocks
*** The DMAC keeps the bus because the other channels have requests pending_ If other channels
do not have requests, the DMAC relinquishes the bus after the error recovery cycle.

Figure 40 Bus Error Operation

Retry

The retry exception causes the DMAC to terminate the
present operation and retry that operation when retry is re-

moved, and thus will not honor any requests until it is removed.
However, the DMAC still recognizes requests. The retry timing
is shown in Figure 41.

~HITACHI

703

HD68450,HD68450Y-------------------------------------------------------ClK

AID BUS

OAS
AS

~

m

-..IIJ\n

ODS ~---m
[l)S

R/\I\i

OWN

DDIR
DBEN
HIBYTE

\\\

III

/0

m

m

--1lJ

\lLJJl

\\\

/U

\\\

m

Low

m

ULJ/J
ill

m
ID

or-

==H=ig=h========================~================================

\\\

IN

\\\

or-

--H~ig~h------~====================~--------~============~----

-_-_-_-_-_-_""T~\'IT'\~\\~\\~\\n\~\'IT'\~\\~\\~\\;"n\~\n\~\~\\~\\~\\~\\~\\~\n\~\TllYI~I~/=========~\\~\=:::::;;;-~nr~
ACK
m
\\\
nr(~!~).------~~----mm;m~=====~~------~=========~~-DTACK

=--1ll=~I1i["_

1m

ClK

* BEC. ·BEC, = (001)

Figure 41 Retry Operation
Relinquish and Retry (R&R)

The relinquish and retry exception causes the DMAC to
relinquish the bus and three-state all bus master controls and
when the exception is removed, rearbitrate for the bus to retry

704

the previous operation.
The diagram of the relinquish and retry timing is shown in
Figure 42.

_HITACHI

------------------------------------------------------------HD68450,HD68450Y

u-u-uuu-u--LIl

ClK

91011 12131415161718192021222324252627282930 31
L -_ _ _ _ _ _ _ _ _ _ _~~
~

AID BUS

~

UAS
AS

~

UDS

~

lOS

~
~r----'

R/W
OWN
DDIR

----------------------I\~~--------------\\
___________

.IIIfT\......t,~

t_,____

DBEN

.-~~

HIBYTE
DTACK

"""m"",,,,""_ "

---'II

ACK
R&R
(BECo-BEC2)'
BGACK
BR

\\

~

'-..(~

DTC

~f

,

\\\

\\\

r'-.

lUUmllllun

------------------.~~~------------_____
U/
~~'_

u-\...._______.-uJ

BG
ClK

u-u-uuu-u--LIl
-+--+- Read Retry -+----

5878910111213141516171819202122232425262728293031

Read
Relinquish and
Retry Asserted

* BECo·BEC,

Other Master
and
Rearbitration

= (110)

Figure 42 Relinquish and Retry Operation

Reset
The reset provides a means of resetting and initializing the
DMAC. If the DMAC is bus master when the reset is asserted,
the DMAC relinquishes the bus. Reset clears GCR, OCR, OCR,
SCR, CCR, CSR, CPR, and CER for all channels. The NIV and
the EIV are all set to (OF)16, which is the uninitialized interrupt
vector number for the HD68000 MPU. MTC, MAR, DAR, BTC,
BAR, MFC, DFC, and BFC are not affected. In order to insure a
reset, BEC o - BEC 2 must be kept at "Low" level for at least
ten clocks.
(5) Error Conditions
When an error is signaled on a channel, all activity on that
channel is stopped. The ACT bit of the CSR is cleared, and the
COC bit is set. The ERR bit of the CSR is set, and the error
code is indicated in the CER. All pending operations are cleared,
so that both the STR and CNT bits of CCR are cleared.
Enumerated below are the error signals and their sources.
(a) Configuration Error - This error occurs if the STR bit is
set in the following cases.
(i) the CNT bit is set at the same time STR bit in the
chaining mode.
(ii) DTVP specifies a single addressing mode, and the
device port size is not the same as the operand size.

.

(iii) DTVP specifies a dual addressing mode, DPS is 16
bits, SIZE is 8 bits and REQG is "10" or "II".
(iv) an undefined configuration is set in the registers.
The undefined configurations are: XRM =0 I, MAC
= II, DAC = II, CHAIN = 0 I, and SIZE = II.
(b) Operation Timing Error - An operation timing error
occurs in the following cases:
(i) when the CNT bit is set after the ACT bit has been
set by the DMAC in the chaining mode, or when
the STR and the ACT bits are not set.
(ii) the STR bit is set when ACT, COC, BTC, NDT or
ERR is set.
(iii) an attempt to write to the OCR, OCR, SCR, MAR,
DAR, MTC, MFC, or DFC is made when the STR
bit or the ACT bit is set.
(iv) an attempt to set the CNT bit is made when the
BTC and the ACT bits are set.
(c) Address Error - An address error occurs in the following
cases:
(i) an odd address is set for word or long word
operands.
(ii) CS or lACK is asserted during the DMA bus cycle.
(d) Bus Error - Bus error occurs when a bus error excep-

~ HITACHI

705

HD68450,HD68450Y---------------------------------------------------------tion is signaled during a DMA bus cycle.
(e) Count Error - A count error occurs in the folJowing
cases:
(i) The STR bit is set when zero is set in the MTC
and the MTC and the chaining mode is not used.
(ii) the STR bit is set when zero is set in BTC for the
array chaining mode.
(iii) zero is loaded from memory to the BTC or the MTC
in the chaining modes or the continue mode.
(f) External Abort - External abort occurs if an abort is
asserted by the external circuitry when the PCl line is
configured as an abort input and the STR or the ACT
bit is set.
(g) Software abort - Software abort occurs if the SAB bit
is set when the STR or the ACT bit is set.

and the channel control register. After the successful completion of any transfer, the memory and device address registers
points to the location of the next operand to be transferred and
the memory transfer counter contains the number of operands
yet to be transferred. If an error occurs during a transfer, that
transfer has not completed and the registers contain the values
they had before the transfer was attempted. If the channel
operation uses chaining, the Base Address Register points to the
next chain entry to be serviced, unless the termination occurred
while attempting to fetch an entry in the chain. In that case,
the Base Address Register points to the entry being fetched.
However, in the case of external abort, there are cases in which
the previous values are not recovered.

Error Recovery Procedures
If an error occurs during a DMA transfer, appropriate information is available to the operating system (OS) to alJow a
software failure recovery operation. The operating system must
be able to determine how much data was transferred, where the
data was transferred to, an what type of error occurred.
The information available to the operating system consists of
the present value of the Memory Address, Device Address and
Base Address Registers, the Memory Transfer and Base Transfer
Counters, the channel status register, the channel error register,

Bus Exception Operating Flow
The bus exception operating flow in the case of multiple
exception conditions occurring continuously in sequence is
shown in Figure 43. Note that the DMAC can receive and execute the next exception condition. For example, if the retry
exception occurs, and next the relinquish and retry exception
occurs while the DMAC is waiting for the retry condition to be
cleared, the DMAC relinquishes the bus and waits for the
exception condition to be cleared. If a bus error occurs during
this period. the DMAC executes the bus error exception
operation.
The flow diagram of the normal operation without exception
operation or errors is shown in Figure 44.

DTACK & HLT (DTC)
I----=:BE:..:R-'---1IDLE MODE
WAITING FOR
BEe CLEAR
TO RETRY

L-.,.-.,.--.-_..J

NON
RRT

DMAC YIELDS BUS
DMAC OWNS BUS

I START
RTY
NON
DTACK & NON
DMA MODE
L-'="':":"':"::';(~DT'=C"":'):"=':'~--IBUS CYCLE A C T I V E t - - - - - - - - - - - '

Figure 43 Bus Exception Flow Diagram

706

~HITACHI

RST
NON
HLT
BER
RTY
RRT
REO
REON
START
DTACK
DTC

: reset
: no exception
: halt
: bus error
: retrv
: relinquish and retry
: external request
: no external request
: bus cycle start
: 5fACK signal asserted
: DTC signal asserted

--------------------------------------------------------HD68450,HD68450Y

DMA Mode Waiting for

Reset All Channels

Bus Cycle to Start

Bus Cycle Start

No Transfer
DMA Mode Bus

DMA Mode Waiting for

Cycle Active

Bus Cycle to Start

Figure 44 Flow of Normal Operation Without Exception
or Error Condition
•

Channel Priorities
Each channel has a priority level, which is determined by the
contents of the Channel Priority Register (CPR). The priority
of a channel is a number from 0 to 3, with 0 being the highest
priority level. When multiple requests are pending at the DMAC,
the channel with the highest priority receives first service. The
priority of a channel is independent of the device protocol or
the request mechanism for that channel. If there are several
requesting channels at the highest priority level, a round-robin
resolution is used, that is, as long as these channels continue to
have requests, the DMAC does operand transfers in rotation.
Resetting the DMAC puts the priority level of all channels
to "0", the highest priority level.

•

APPLICATIONS INFORMATION

Examples of how to interface HD684S0 to a HD68000 based
system are shown in Figure 45 and Figure 46.
Figure 45 shows an example of how to demultiplex the
address/data bus. OWN and VAS are used to control 74LS373
for latching the address. DBEN and DDIR are used to control
the bi-directional buffer 74LS245.
Figure 46 shows an example of inter-device connection in
the HMCS68000 system.

+5V 9
~

~

~>

~

>

74LS04
~

OWN

I

UAS
16

•

G
G

I

OE
OE

16

16

As/Do-A23/D15

~

0

0

Of-+--. As - A23

(Address Busl

74LS373
x2
I-

HD68450
DMAC

+5V;>
t<> •

8

~A

DBEN

IT

DDIR

DIR

74LS245

B~
(Data Busl

8

~ A
~

G

74LS245

B~

DIR
Figure 45 An Example of the Demultiplexed Address Data Bus

~HITACHI

707

HD68450,HD68450Y
to"vo-___....;0...;0_-..;,0..;,15;;..,.-_ _..I'I,Jr-----------..., ADo-D,S,....
,.

Data & Address

,.....

As-A2l

Bus Interface
FOC,
etc.

ro

-V

I----

I---

k:

l~

l..~

f--

HOC,
etc.

:=-

L.
L...-

'---0

AEClo}
ACKo
PCLo

r--

~

Channel #0

t=
I--

10I--

FCo-FC2

+~
A

~

,..

00-0,5

LOS

UDS

i---

A/W

10-

Al-A2l

f--.

I----

r----

AS

f-o
I--

I---

LOS
UOS

f--.
f---...

I - - - - A/iN

I---

r--

I--+-+-+~ R/Vii

10-

I--

I--

I--

~

1010-

I-I--

I---

1010-

I-I--

3

@

h

L-.

The address bus and the system control bus in each device
are omitted in this Figure.
Figure 46 An Example of Inter-device Connection in
the HMCS68000 System

~HITACHI

OTACK

I----

lI-I--

VPA
VMA

Enc.

708

)

OTACK

E

f

I

'--

I-I--

AS

00-0,5

~
~

p

AI-An
H068000
MPU

)

MEM&MMU

~

101010-

I

I----+~E

IRQ
h..

6800
Periphr.

----------------------------------------------------------H D68450, HD68450Y
•

ATTENTION ON USAGE

(I) How to interface various 6800 type peripheral devices to
the DMAC based system.
When the DMAC is reading data from the 6800 device, the

DMAC latches the data when DTC is asserted and not at the
faIling edge of E clock. The 74LS373 need to be provided externally as shown in Figure 47 so that the data from the 6800
device can be held on the bus for a large period of time until
the DMAC can latch the correct data.

E
Device

CS

AS

E
00-07
6800 Type
Device

CS

RS

..
:>

CD

~
"0
"0

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