U71_8 Bit_Single Chip_Microcontroller_Data_Book U71 8 Bit Single Chip Microcontroller Data Book
User Manual: U71_8-Bit_Single-Chip_Microcontroller_Data_Book
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8-BIT SINGLE-CHIP
MICROCOMPUTER DATABOOK
$HITACHI
When using this manual. the reader should keep the following in mind:
1. This manual may, wholly or partially. be subject to change without notice.
2. All rights reserved: No one is permitted to reproduce or duplicate. in any
form. the whole or part of this manual without Hitachi's permission.
3. Hitachi will not be responsible for any damage to the user that may result
from accidents or any other reasons during operation of his unit according
to this manual.
4. This manual neither ensures the enforcement of any industrial properties
or other rights. nor sanctions the enforcement right thereof.
INDEX
• GENERAL INFORMATION
• Quick Reference Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . .. 7
• Introduction of Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 17
• Quality Assurance •...•......•....••..••.••.......•.•.••......••..•..•........•...•..••.•................•.. 25
• Reliability Test Data. . • . . . . . . . . . . • . . . . . . . . • . . . • • . . • . . . • • . . . • . . . . . . • . . • . . . • . . • . • . . . • • • . • . . . . . . . . . • • . • . . . . . . • . 31
• .Design Procedure and Support Tools for 8-bit Single-chip Microcomputers ... : . . . . . . . . . . . . . . . . . . . . . . . . . .. 36
• DATA SHEETS
H0680lS0
H06801S5
H06801VO
H06801V5
H06803
H06803·1
H06805S1
H06805S6
H06805Ul
H06805Vl
H06805T2
H06805Wl
H06301Vl
H063AOIVI
HD63BOIVI
H06301XO
H063AOIXO
H063BOIXO
HD6301YO
HD63AOIYO
HD63BOIYO
HD6303R
HD63A03R
HD63B03R
HD6303X
HD63A03X
HD63B03X
HD6303Y
HD63A03Y
H063B03Y
HD6305UO
HD63A05UO
HD63B05UO
HD6305VO
HD63A05VO
HD63B05VO
HD6305XO
HD63A05XO
HD63B05XO
HD6305Xl
HD63A05Xl
HD63B05Xl
H06305X2
HD63A05X2
HD63B05X2
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Microcomputer Unit (NMOS) .............................•.................... "
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Micro Processing Unit (NMOS) ...................................................
Micro Processing-Unit (NMOS) ...................................................
Microcomputer Unit (NMOS) ........................•...........................
Microcomputer Unit (NMOS) ....................................................
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcomputer Unit (NMOS) ....................................................
Microcomputer Unit (NMOS) ....................................................
Microcomputer Unit (NMOS) ....................................................
Microcomputer Unit (CMOS) ....................................................
Microcomputer Unit (CMOS) '" . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcomputer Unit (CMOS) ....................................................
Microcomputer Unit (CMOS) ....... . . . . . . . . . .- . . . . . . . . . . . . . . . . . . . . . . • . . . . . • . . . . . .
Microcomputer Unit (CMOS) .......•....................•..•....................
Microcomputer Unit (CMOS) ....................................................
Microcomputer Unit (CMOS) ....................................................
Microcomputer Unit (CMOS) ....................................................
Microcomputer Unit (CMOS) ....................................................
Micro Processing Unit (CMOS) ...................................................
Micro Processing Unit (CMOS) ...................................................
Micro Processing Unit (CMOS) .................. . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .
Micro Processing Unit (CMOS) ...................................................
Micro Processing Unit (CMOS) ...................................................
Micro Processing Unit (CMOS) ..................................... . . . . . . . . . . . . . .
~icro Processing Unit (CMOS) .......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Micro Processing Unit (CMOS) ...............•......................... . . . . . . . . . .
Micro Processing Unit (CMOS) ...................................................
Microcomputer Unit (CMOS) ................•...................................
Microcomputer Unit (CMOS) ......................... '. . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcomputer Unit (CMOS) ....................................................
Microcomputer Unit (CMOS) ....................................................
Microcomputer Unit (CMOS) ......................... , .•...................•....
Microcomputer Unit (CMOS) ....................................................
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcomputer Unit (CMOS) ....................................................
Microcomputer Unit (CMOS) ............................................. ; ......
Microcomputer Unit (CMOS) .................................................•..
Microcomputer Unit (CMOS) ..................................•..............•..
Microcomputer Unit (CMOS) .............. ' ......................................
Microcomputer Unit (CMOS) ., ...............•..................................
Microcomputer Unit (CMOS) ....................................................
Microcomputer Unit (CMOS) ................•............................•......
_HITACHI
41
41
75
75
109
109
136
156
176
197
218
219
247
247
247
284
284
284
321
321
321
323
323
323
353
353
353
388
388
388
391
391
391
393
393
393
395
395
395
422
422
422
422
422
422
HD630SYO
HD63AOSYO
HD63BOSYO
ijD630SYI
HD63AOSYI
HD63BOSYI
HD630SY2
HD63AOSY2
HD63BOSY2
HD63LOSFI
HD63LOSEO
HD68POIV07
HD68POIV07-1
HD68POIMO
HD68POIMO-I
HD68POSV07
HD68POSWO
HD63POIMI
HD63PAOIMI
HD63PBOIMI
HD63POSYO
HD63PAOSYO
HD63PBOSYO
HD63701XO
•
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... 451
Microcomputer Unit (CMOS) .................................................... 451
Microcomputer Unit (CMOS) .........................•.......................... 451
Microcomputer Unit (CMOS) ... . . . . . ............................................ 478
Microcomputer Unit (CMOS) .................................................... 478
Microcomputer Unit (CMOS) .................................................... 478
Microcomputer Unit (CMOS) .................................................... 478
Microcomputer Unit (CMOS) .................................................... 478
Microcomputer Unit (CMOS) .................................................... 478
Microcomputer Unit (CMOS) .................................................... 507
Evaluation Chip for HD63LOSFI (CMOS) ............................................ 538
Microcomputer Unit (NMOS) .................................................... 540
Microcomputer Unit (NMOS) .................................................... 540
Microcomputer Unit (NMOS) .................................................... 540
Microcomputer Unit (NMOS) .................................................... S40
Microcomputer Unit (NMOS) .................................................... 579
Microcomputer Unit (NMOS) .................................................... 601
Microcomputer Unit (CMOS) .................................................... 630
Microcomputer Unit (CMOS) .................................................... 630
Microcomputer Unit (CMOS) ..................................................... 630
Microcomputer Unit (CMOS) ....................... '.' ........................... 668
Microcomputer Unit (CMOS) .................................................... 668
Microcomputer Unit (CMOS) .....................................................668
Microcomputer Unit (CMOS) .................................................... 670
INTRODUCTION OF RELATED DEVICES
•
•
•
•
•
•
•
•
•
8/16-bit MuIti-chip Microcomputers, ......................................................... 675
4-bit Single-chip Microcomputer HMCS400 Series ............................ " ..................... 677
4-bit Single-chip Microcomputer HMCS40 Series ., ...............................•................ 678
LCD Driver Series ......................................... , ..........•.................. 680
IC Memories .......................................................................... 682
Gate Array ..................................................................... ...... 685
LSI for Speech Synthesizer System ................................ , .......................... 687
CODEC/Filter Combo LSI ................................................... '.' ............ 690
HITACHI SALES OFFICE LOCATIONS ..•....•.....•..•....•...•.•..••.•••.••....•...•..•.•.••..•.....•. 692
_HITACHI
GENERAL
INFORMATION
•
•
•
•
•
Quick Reference Guide
Introduction of Packages
Quality Assurance
Reliability Test Data
Design Procedure and Support Tools
for 8-bit Single-chip Microcomputers
QUICK REFERENCE GUIDE
• NMOS 8-BIT SINGLE-CHIP MICROCOMPUTER HD6801 SERIES
LSI
Characteristics
HD6803
HD6803·1
HD6801S0
HD6801S5
HD6801VO
HD6801V5
Bus Timing (MHz)
1.011.25
1.0/1.25
Supply Voltage (V)
5.0
5.0
5.0
0-+70
o -+70
0-+70
DP·40
DP·40
DP-40
2
4
-
128
128
128
Type No.
Operating Temperature * tC)
Package t
Memory
ROM (k byte)
RAM (byte)
I/O Port
Interrupt
Functions
1.011.25
29
29
13
External
2
2
2
Soft
1
1
1
Timer
3
3
3
1
1
Seria.1
Timer
• Free running counter
• Output compare register
• Input capture register
SCI
External Memory Expansion
1
16-bit x 1
16-bit x 1
16-bit x 1
Full double step-stop type
• Address/data non-multiple mode
(256 bytes)
• Address/data multiple mode
(65k bytes)
Clock Pulse Generator
• Address/data
multiple mode
(65k bytes)
Built-in (External clock useable)
Built-in RAM Holding
Yes (64 bytes)
EPROM on the Package Type**
HD68P01V07
HD68P01V07-1
Compatibility
MC6801
MC680l-l
HD68P(J1V07
HD68P01V07-1
-
MC6803
MC6803-l
• Wide Temperature Range (-40 - +85°C) version is available .
•• HD68P01MO useable.
t DP; Plastic DIP
_HITACHI
7
QUICK REFERENCE G U I D E - - - - - - - - - - - - - - - - - - - - - - - - - - - -
• NMOS 8·BIT SINGLE·CHIP MICROCOMPUTER HD6805 SERIES
Type No.
HD6805S1
HD6805S6*
1.0
1.0
1.0
5.25
5.25
5.25
0-+70
0-+70
0-+10
DP·28
DP-28
DP·40
ROM (k byte)
1.1
1.8
2
RAM (byte)
64
64
96
Clock Frequency (MHz)
LSI
Characteristics
Supply Voltage (V)
Operating Temperature *** ( DC)
Package t
Memory
1/0 Port
110 Port
-
20
Output Port
Interrupt
Functions
20
20
Input Port
HD6805Ul
-
20
24
32
8
-
Nesting
6
6
6
External
1
1
1
Soft
1
1
1
Timer
1
1
1
Serial
-
-
-
• 8-bit timer with 7-bit prescaler
• Event counter
Timer
-
SCI
Low·voltage Automatic Reset (LVI)
External Memory Expansion
-
• Resistor
• Crystal
Clock Pulse Generator
Self·check Mode
-
Yes
Yes
Yes
Available
Available
Available
-
-
-
-
-
HD68P05V07
MC6805P2
MC6805P6
-
Other Features
EPROM on the Package Type
Compatibility
* Preliminary * * Under development
* * * Wide Temperature Range (-40 - +8SoC) version is available.
t DP; Plastic DIP
8
_HITACHI
- - - - - - - - - - - - - - - - - - - - - - - - - - - - QUICK REFERENCE GUIDE
HD6805Vl
HD6805T2**
HD6805Wl*
1.0
1.0
1.0
5.25
5.25
5.25
0-+70
0-+70
0-+70
DP·40
DP·28
DP·40
4
2.5
4
96
64
96
19
24
32
8
-
19
-
23
6
29
-
6
6
12
1
1
2
1
1
1
1
1
4
-
-
• 8·bit timer
with 7·bit
prescaler
• Event counter
·8·bit
comparator
-
-
-
• Crystal
Yes
Yes
Yes
Available
Available
Available
-
PLL logic
for RF
synthesizer
HD68P05V07
-
-
MC6805T2
• 8·bit x
4·channel
internal
AID converter
• 8 bytes of
standby RAM
HD68P05WO*
-
.,.HITACHI
9
QUICK REFERENCE G U I D E - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
• CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER HD6301 SERIES
Type No.
Bus Timing (MHz)
LSI
Characteristics
HD6301V1
HD63A01V1
HD63B01V1
HD6301XO
HD63A01XO
HD63B01XO
1.0 (HD6301V1)
1.5 (HD63A01V1)
2.0 (HD63B01V1)
1.0 (HD6301XO)
1.5 (HD63A01XO)
2.0 (HD63B01XO)
Supply Voltage (V)
Package t
DP-40, FP-54, CG-40
RAM (byte)
4
128
192
Functions
-
21
2
3
2
2
Timer
3
4
Serial
1
1
16-bit x 1
(F.ee ".on;n. count.. Xl)
l6-bit x 1
( Free running counter )( 1 )
Output compare register x2
Input capture register x1
8-bit x 1
( 8-bit up counter x 1
)
Time constant register x 1
Asynchronous
Asynch ronou s/Synchronou s
Output compare register x 1
I nput capture register x 1
65k bytes
65k bytes
-Error detection
-Low power consumption
modes (sleep and standby)
-Error detection
-Low power consumption
modes (sleep and standby)
-Slow memory interface
-Halt
External Memory Expansion
HD63P01M1
HD63PA01M1 *
HD63PB01M1 *
••• Wide Temperature Range (-40 - +SSoC) version is available.
t DP; Plastic DIP, FP; Plastic Flat Package, CG; Glass-sealed Ceramic Leadless Chip Carrier
10
8
-
External
SCI
•• Under development
53
Soft
Timer
Other Features
24
29
29
Output Port
Interrupt
DP-64S, FP-80
4
1/0 Port
Input Port
I/O Port
• Preliminary
0-+70
0-+70
ROM (k byte)
Memory
EPROM on the Package Type
5.0
5.0
Operating Temperature-(oC)
eHITACHI
HD63701 XO**
(EPROM on-chip)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - QUICK REFERENCE GUIDE
HD6301YO**
HD63A01YO**
HD63B01YO**
HD6303R
HD63A03R
HD63B03R
HD6303X
HD63A03X
HD63B03X
HD6303Y**
HD63A03Y**
HD63B03Y**
1.0 (HD6301YO)
1.5 (HD63A01YO)
2.0 (HD63B01YO)
1.0 (HD6303R)
1.5 (HD63A03R)
2.0 (HD63B03R)
1.0 (H D6303X)
1.5 (HD63A03X)
2.0 (HD63B03X)
1.0 (HD6303Y)
1.5 (HD63A03Y)
2.0 (H D63B03Y)
5.0
5.0
5.0
5.0
0-+70
0-+70
0-+70
0-+70
DP-64S, FP-64
DP-40, FP-54, CG-40
DP-64S, FP-80
DP-64S, FP-64
16
-
-
-
256
128
192
256
48
-
53
13
16
-
13
24
8
-
5
24
-
-24- - - -
3
2
3
3
2
2
2
2
4
3
4
4
1
1
1
16-bit x 1
.unning counte. . l
)
Output compare register x 2
Input capture register x 1
8-bit xl
( 8-bit up counter
Time constant register x 1
cree
Xl)
1
16-bit x 1
16-bit x 1
)
.unning coun'" x I
) ( Free running counter xl
Output compare register x 1 - Output compare register x 2
Input capture register x 1
Input capture register x 1
8-bit x 1
( 8-bit up counter
Time constant register x 1
cree
Xl)
16-bit x 1
.unning counle. . I
)
Output compare ~egister x 2
Input capture register x 1
8-bit x 1
( 8-bit up counter
Time constant register x 1
cree
Xl)
Asynchronous/Synchronous
Asynchronous
Asynchronous/Synchronous
65k bytes
65k bytes
65kbytes
65k bytes
-Error detection
-low power consumption
modes (sleep and standby)
- -Slow memory interface
-Halt
-Error detection
-low power consumption
modes (sleep and standby)
-Error detection
-low power consumption
modes (sleep and standby)
-Slow memory interface
-Halt
-Error detection
-low power consumption
modes (sleep and standby)
-Slow memory interface
-Halt
$
HITACHI
Asynchronous/Synchronous
11
QUICK REFERENCE G U I D E · - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
• CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER HD6305 SERIES
Type No.
Clock Frequency (MHz)
LSI
Characteristics
HD6305UO**
HD63A05UO**
HD63B05UO**
HD6305VO**
HD63A05VO**
HD63B05VO**
HD6305XO*
HD63A05XO*
HD63B05XO*
1.0 (HD6305UO)
1.5 (HD63A05UO)
2.0 (HD63B05UO)
1.0 (HD6305VO)
1.5 (HD63A05VO)
2.0 (HD63B05VO)
1.0 (HD6305XO)
1.5 (HD63A05XO)
2.0 (HD63B05XO)
Supply Voltage (V)
Operating Temperature *** (oC)
5.0
5.0
5.0
0-+70
0-+70
0-+70
DP-40
DP·40
DP·64S, FP·64
2
4
4
128
192
128
Package t
Memory
ROM
(k byte)
RAM
(byte)
I/O Port
I/O Port
1
Output Port
31
31
-
31
Input Port
-
31
32
7
55
16
2
External
2
2
Soft
1
1
1
Timer
2
2
2
Serial
1
1
1
-
-
-
EPROM on the Package TyPe
-
-
Evaluation Ch ip
-
-
Interrupt
Functions
Timer
SCI
External Memory Expansion
Other Features
0
• Preliminary •• Under development ••• Wide Temperature Range (-46 - +85 C) version is available.
t DP; Plastic DIP, FP; Plastic Flat Package
12
$
HITACHI
HD63P05YO**
HD63PA05YO**
HD63PB05YO**
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - Q U I C K REFERENCE GUIDE
HD630SXl
HD63AOSXl
HD63BOSXl
HD630SX2
HD63AOSX2
HD63BOSX2
HD630SYO*
HD63AOSYO*
HD63BOSYO*
HD630SY1*
HD63AOSYl *
HD63BOSY1*
HD630SY2*
HD63AOSY2*
HD63BOSY2*
1.0 (H D630SX 1)
1.S (H D63AOSX 1)
2'.0 (H D63BOSX 1)
1.0 (HD630SX2)
1.S (HD63AOSX2)
2.0 (HD63BOSX2)
1.0 (H D630SYO)
1.S (HD63AOSYO)
2.0 (HD63BOSYO)
1.0 (HD630SY1)
1.S (H D63AOSY 1)
2.0 (HD63BOSY1)
1.0 (H D630SY2)
1.S (HD63AOSY2)
2.0 (HD63BOSY2)
HD63LOSFl
0.1
S.O
S.O
S.O
S.O
S.O
3.0
0-+70
0-+70
0-+70
0-+70
0-+70
-20 - +7S
DP·64S, FP·64
DP·64S, FP·64
DP·64S, FP·64
Dp·64S, Fp·64
DP·64S, Fp·64
DP·64S, FP·80
4
-
8
8
-
4
128
128
2S6
2S6
2S6
96
24
31
7
24
7
31
-
32
SS
7
-
24
31
7
24
7
31
-
16
20
-
20
-
(19)
2
2
2
2
2
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
1
1
• 8·bit x 1 (with 7·bit prescaler)
- lS·bit x 1 (combined with SCI)
- 8·bit X 1 (with
7·bit prescaler)
Synchronous
12k bytes
16k bytes
- Low power consumption modes
(Wait, stop and standby)
1
-
8 k bytes
16k bytes
- 8·bit AID converter
-LCD driver
(6 x 7 segment)
- Low power con·
sumption modes
(Standby and halt)
-
-
HD63POSYO**
HD63PAOSYO**
HD63PBOSYO**
-
-
-
-
-
-
-
~HITACHI
HD63LOSEO
13
QUICK REFERENCE
GUIDE.----------------------------
• NMOS 8·BIT SINGLE·CHIP MICROCOMPUTER EPROM ON PACKAGE TYPE
HD68P01V07 HD68P01V07·1 * HD68P01MO
Type No.
LSI
Characteristics
l Supply Voltage
(V)
IOperating Temperature*· (0 C)
I Package t
Equivalent Device
Mountable EPROM
HD68P01MO·1 * HD68POSV07
S.O
S.O
0- +70
0- +70
0-+70
DC·40P
HD6801VO
HN482732A·30
HD68POSWO*
S.O
-
-
HN482764·3
HN482764·3
HD6801VS
HN482732A·30
DC·40P
DC·40P
HD680SU1
HD680SVl
HD680SW1
HN482732A·30
HN482732A·30
HN482764·3"
• Preliminary
.. Wide Temperature Range (-40 - +85"C) version is available.
t DC; Ceramic DIP (EPROM on the package type)
• CMOS 8·BIT SINGLE·CHIP MICROCOMPUTER EPROM ON PACKAGE TYPE
Type No.
HD63P01M1
(V)
Supply Voltage
LSI
Characteristics Operating Temperature"· (oC)
Package t
Equivalent Device
Mountable EPROM
HD6301V1
HN482732A·30
HN482764·3
HN27C&4·30
HD63PA01M1· HD63PB01M1· HD63POSYO·· HD63PAOSYO" HD63PBOSYO··
S.O
S.O
0- +70
0- +70
DP·64SP
DC·40P
HD63A01V1
HD63B01V1
HD630SXO
HD6305YO
HD63AOSXO
HD63AOSYO
HD63BOSXO
HD63BOSYO
HN482732A·30
HN482764·3
HN27C64·30
HN482732A·25
HN482764
HN27C&4·25
HN482732A·30
HN482764·3
HN27C&4·30
HN482732A·30
HN482764·3
HN27C64·30
HN482732A·25
HN482764
HN27C&4·25
• Preliminary
•• Under Development
••• Wide Temperature Range (-40 - +8SoC) version is available.
t DC; Ceramic DIP (EPROM on the package type)
14
eHITACHI
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - QUICK REFERENCE GUIDE
• CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER EPROM ON-CHIP TYPE
HD63701XO*
Type No.
1.0
Bus Timing (MHz)
LSI
Characteristics
Supply Voltage
(V)
5.0
Operating Temperature (oC)
0-+70
Package t
DC-64S
4 (EPROM)
ROM (k byte)
Memory
RAM (byte)
192
I/O Port
I/O Port
24
~
Input Port
53
8
21
Output Port
Functions
External
3
Soft
2
Timer
4
Serial
1
Interrupt
-
(
Timer
)
Asynch ronous/Sy nch ronou s
SCI
External Memory Expansion
Other Features
16-bit x 1
Free running counter x 1
Output compare register x 2
Input capture register x 1
8-bit x 1
( 8-bit up counter x l )
Time constant register x 1
65k bytes
•
•
•
•
Error detection
Low power consumption modes (sleep and standby)
Slow memory interface
Halt
Equivalent Device
HD6301XO
Reference Page
720
• Under development
t DC; Ceramic DIP (Shrink typel
_HITACHI
15
INTRODUCTION OF PACKAGES
Hitac;hi microcomputer devices are offered in a variety of
packages, to meet various user requirements.
1. Package Classification
When selecting suitable packaging, please refer to the
Package Classifications given in Fig. I for pin insertion, surface
mount, and multi-function types, in plastic and ceramic.
Standard Outline
Plastic DIP
Ceramic DIP
Pin Insertion Type
Shrink Outline
Shrink Type Plastic DIP
Shrink Type Ceramic DIP
Package Classification
Flat Package
Surface Mounting Type
Chip Carrier
Multi·function Type
DIP; DUAL IN LINE PACKAGE
S·DIP; SHRINK DUAL IN LINE PACKAGE
PGA: PIN GRID ARRAY
FLAT·DIP; FLAT DUAL IN LINE PACKAGE
FLAT·QUIP; FLAT QUAD IN LINE PACKAGE
CC: CHIP CARRIER
SOP;SMALL OUTLINE PACKAGE
FPP; FLAT PLASTIC PACKAGE
PLCC;PLASTIC LEADED CHIP CARRIER
LCC ; LEADLESS CHIP CARRIER
Fig. 1
Package Classification according to Material and Printed Circuit Board Mounting Type
_HITACHI
17
INTRODUCTION OF P A C K A G E S - - - - - - - - - - - - - - - - - - - - - - - by code as follows, and illustrated in the data sheet for each
device.
When ordering, please write the package code next to the
type number.
2. Type No. and Package Code Indication
The Hitachi Type No. for single-chip microcomputer devices
is followed by package material and outline specifications, as
shown below. The package type used for each device is identified
Type No. Indication
HDx X X xP
(Note I HDXXfXXXX stands for Type No.
of EPROM on the package type
microcomputer device.
Package Classification
No Indication : Cerwnic DIP
P ; Plastic DIP
F ; FPP
CG; LCC
Peclcage Cod. Indication
DP-64S
D ;DIP
C;CC
F ;FLAT
P
G
Additional Outline
S; Shrink type
P; EPROM on the package type
C
18
_HITACHI
- - - - - - - - - - - - - - - - - - - - - - - - I N T R O D U C T I O N OF PACKAGES
3. Package Dimensional Outline
Hitachi single-chip microcomputer devices employ the packages shown in Table I according to PCB mounting method.
Table 1 Package List
Mounting method
Package classification
'.'
Standard outline (DIP)
Pin insertion type
Package material
Package code
Plastic
Dp·28
DP-40
Plastic
DP-64S
Shrink outline (S-DIP)
Ceramic
Surface mounting type
Flat package (FPP)
Plastic
Fp·54
Fp·64
Fp·80
Chip carrier (LCC)
Glass sealed ceramic
CG·40
Ceramic
DC-40P
DC·64SP
EPROM on the package type
Multi-function type
DC·64S
Plastic DIP
• DP·28
14
15
g
~- 5:~:Cu
O· -IS"
•
2.54min
0.20-0.38
(Unit: mm)
DP-40
(Unit:mm)
~HITACHI
19
I Shrink Type Plastic DIP
• DP·64S
IUnit: mm)
I Shrink Type Ceramic DIP
• DC·64S
1-- .. 11,>. - .. -
IUnit:mm)
20
$
HITACHI
---------------~--·------INTRODUCTION
OF PACKAGES
LF'atPack~
•
FP·54
~-·~·:1
21i.e±O.4
..J ( UiiiiihiihiiOh I
;
J
Jf:f
~
(Unit:mm)
•
FP·64
(Unit:mm)
• FP-80
(Unit: mm)
_HITACHI
21
INTRODUCTION OF PACKAGES - - - - - - - - - - - - - - - - - - - - - -
I bid'... Chip Carrier I
• CG·40
12,19
;D~
~IIII
000000000
H,02
CO.84,
•
J
I - ~2.&4
oiTlJ
~
1t"D.51
!D IDDCDDI1DD
=
c
c~
.;
,....
;;
(Unlt:mm)
I EPROM
011-. . . . . . . Type
• DC-40P
020·011
q"
-0_
1124
'(Unit:mm)
22
_HITACHI
- - - - - - - - - - - - - - - - - - - - - - - - I N T R O D U C T I O N OF PACKAGES
• DC-84SP
o
IUnit:mml
4. Mounting M.thocI
Package lead pins are surface treated with solder coating or
plating to facilitate PCB mounting. The lead pins are connected
to the package by eutectic solder. Common connecting method
of leads and precautions are explained as follows:
4.1 Mounting Methods of Pin Insertion Type P.ckage
Insert lead pins into the PCB through-holes (usually about
.,.0.8mm). Soak leads in a wave solder tub.
Lead pins held by the through-holes enable handling of the
package through the sqldering process, and facilitate automated
soldering. When soldering leads in the wave solder tub, do not
get solder on the package.
4.2 Mounting Method of lurfllce Mount Type P.ck. .
Apply the specified quantity of solder paste to the pattern on
any printed board by the screen printing method, to temporarily
fix the package to the board. The solder paste melts when heated
in a renowing furnace, and package leads and the pattern of the
printed board are fixed by the surface tension of the melted
solder and self alignment.
The size of the pattern where leads are attached should be 1.1
to 1.3 times the leads' width, depending on paste material or
furnace adjustment.
The temperature of the renowing furnace is dependent on
packaging material and type. Fig. 2 lists the adjustment of the
renowing furnace for FPP. Pre-heat the furnace to 1500C. Surface temperature of the resin should be kept at 2350 C maximum
for 10 minutes or less.
Time-
Fig. 2 Reflowing Furnace Adjustment
for FPP
Employ adequate heating or temperature control equipment
to prevent damage to the plastic package epoxy-resin material.
When using an infrared heater, avoid long exposure at temperatures higher than the glass transition point of epoxy-resin (about
1500 C), which may cause package damage and loss of reliability
characteristics. Equalize the temperature inside and outside of
packages by reducing the heat of the upper surface of the
packages.
FPP leads may easily bend in shipment or during handling,
and impact soldering onto the printed board. Heat the bent leads
again with a soldering iron to reshape them.
Use a rosin flux when soldering. Do not use chloric flux
because the chlorine in the flux has a tendency to remain on the
leads and reduce reliability. Use alcohol, chlorothene orfreon to
wash away rosin flux from packages. These solvents should not
remain on the packages for an excessive length of time, because
the package markings may disappear.
eHITACHI
23
5.
Package Marking
The Hitachi trademark and product type No. are printed on
packages, as shown in the following examples. Customer
marking can be added to single-chip devices upon request.
(a)
(b)
.~~~
(')B DB8DrnS DB
(d)
24
~
DD
(e)
O~B~fSI
_HITACHI
Meaning of each mark
(a)
Hitachi Trademark
(b)
Lot Code
(c)
Type No.
(d)
(e)
,ROM Code
Japan Mark
QUALITY ASSURANCE
1. VIEWS ON QUALITY AND RELIABILITY
Basic views on quality at Hitachi are to meet the
individual uers' required quality level and maintain a
general quality level equal to or above that of the
general market. The quality required by the user may
be specified by contract. or may be indefinite. In either
case. efforts are made to assure reliable performance
in actual operating circumstances. Quality control
during the manufacturing process. and quality awareness from design through production lead to product
quality and customer satisfaction. Our quality assurance technique consists basically of the following
steps:
(1) Build in reliability at the design stage of new
product development.
(2) Build in quality at all steps in the manufacturing
process.
(3) Execute stringent inspection and reliability confirmation of final products.
(4) Enhance quality levels through field data feed
back.
(5) Cooperate with research laboratories for higher
quality and reliability.
With the views and methods mentioned above.
utmost efforts are made to meet users' requirements.
2. RELIABILITY DESIGN OF
SEMICONDUCTOR DEVICES
2.1 Reliability Targets
The reliability target is an important factor in sales.
manufacturing, performance, and price. It is not adequate to set a reliability target based on a single set of
common test conditions. The reliability target is set
based on many factors:
(1) End use of semiconductor device.
(2) End use of equipment in which device is used.
(3) Device manufacturing process.
(4) End user manufacturing techniques.
(5) Quality control and screening test methods.
(6) Reliability target of system.
2.2 Reliability Design
The following steps are taken to meet the reliability
targets:
(1) Design Standardization
As for design rules, critical items pertaining to
quality and reliability are always studied at circuit
$
design. device design, layout design. etc. Therefore. as long as standardized processing and
materials are used the reliability risk is extremely
small even in the case of new development
devices. with the exception of special requirements imposed by functional needs.
(2) Device Design
It is important for the device design to consider
total balance of process, structure. circuit. and
layout design. especially in the case where new
processes and/or new materials are employed.
Rigorous technical studies are conducted prior to
device development.
(3) Reliability Evaluation by Functional Test
Functional Testing is a useful method for design
and prOCess reliability evaluation of Ie's and LSI
devices which have complicated functions.
The objectives of Functional Test are:
• Determining the fundamental failure mode.
• Analysis of relation between failure mode and
manufacturing process.
• Analysis of failure mechanism.
• Establishment of QC points in manufacturing
process.
2.3 Design Review
Design Review is an orga nized method to confirm that
a design satisfies the performance required and
meets design specifications. In addition, design review
helps to insure quality and reliability of the finished
products. At Hitachi, design review is performed from
the planning stage to production for new products.
and also for design changes on existing products.
Items discussed and considered at design review are:
(1) Description of the products based on design
documents.
(2) From the standpoint of each participant. design
~ documents are studied. and for points needing
clarificatio~. further investigation will be carried
out.
\
(3) Specify quaiity control and test methods based on
design documents and drawings.
(4) Check process and ability of manufacturing line to
achieve design goal.
(5) Preparation for production.
(6) Planning and execution of sub-programs for
design changes proposed by individual specialists.
HITACHI
25
QUALITY ASSURANCE - - - - - - - - - - - - - - - - - - - - - -
for test, experiments, and calculations to confirm
the design changes.
(7) Analysis of past failures with similar devices, discussion of methods to prevent them, and planning
and execution oftest programs to confirm success.
3. QUALITY ASSURANCE SYSTEM
3.1 Activity of Quality Assurance
General views of overall quality assurance in Hitachi
are as follows:
(1) Problems in each individual process should be
solved in lhe process. Therefore. at the finished
product stage the potential failure factors have
been removed.
(2) Feedback of information is used to insure a satisfactory level of ability process.
3.2 Quality Approval
To insure quality and reliability. quality approval is
carried out at the preproduction stage of device
l
I
Materials, Parts II
Approval
II
Design
Trial
Production
IICharacteristics Approval
,
II Quality Approval
26
Production
Quality control is accomplished through division ot
functions jn manufacturing, quality assurance, and
other related departments. The total function flow is
shown in Fig. 2. The main points are described below.
J
Characteristics of Material and
Parts
Appearance
Dimension
Heat Resistance
Mechanical
Electrical
Others
Electrical
Characteristics
Function
Voltage
Current
Temperature
Others
Appearance, Dimension
II
IIQuality Approval (1)
l~ass
Production
3.3 Quality and Reliability Control .t M •••
L Design Review
.~
I
(1) A third party executes approval objectively from
the standpoint of the customer.
(2) Full consideration is given to past failures and
information from the field.
(3) No design change or process change without QA
approval.
(4) Parts. materials. and processes are closely
monitored.
(5) Control points are established in mass production
after studying the process abilities and variables.
Contents
Step
Target
Specification
design. as described in section 2. Our views on quality
approval are:
(2)
Figure 1
Confirmation of
Characteristics and
Reliability of Materials
and Parts
I Confirmation of Target
Spec. Mainly about
Electrical Characteristics
Reliability Test
Life Test
Thermal Stress
Moisture Resistance
Mechanical Stress
Others
Confirmation of Quality
and Reliability in Design
Reliability Test
Process Check same as
Quality Approval (1)
Confirmation of Quality.
and Reliability in Mass
Production
Flow Chart of Quality Approval,
$
HITACHI
- - - - - - - - - - - - - - - - - - - - - QUALITY ASSURANCE
Process
Material
Parts
Products
I
I
I
I
I
Quality Control
Method
Inspection on Material and
Parts for Semiconductor
Devices
Lot Sampling,
Confirmation of
Quality Level
Manufacturing Equipment,
Environment, Sub-material,
Worker Control
Confirmation of
Quality Level
Inner Process
Quality Control
Lot Sampling,
Confirmation of
Quality Level
100% Inspection on
Appearance and Electrical
Characteristics
Testing,
Inspection
Sampling Inspection on
Appearance and Electrical
Characteristics
--1
Reliability Test
---
I
~----
~---------------,
I
: Quality Information
I
Claim
:
:
Field Experience
I
General Quality
L _________________
Information
I
Lot Sampling
Confirmation of
Quality Level, Lot
Sampling
Feedback of
Information
~
Figure 2 Flow Chart of Quality Control in Manufacturing Process
eHITACHI
27
QUALITY A S S U R A N C E - - - - - - - - - - - - - - - - - - - - -
3.3.1 Quality Control of Parts and Materials
3.3.2 Inner Procell Quality Control
As semiconductor devices tend towards higher performance and higher reliability, the importance of
quality control of parts and materials becomes paramount. Items such as crystals, lead frames, fine wire
for wire bonding, packages, and materials needed in
manufacturing processes such as masks and chemicals, are all subject to rigorous inspection and control.
Incoming inspection is performed based on the purchase specification and drawing. The sampling is executed based mainly on MIL-STD-105D.
Inner Process Quality Control performs very important
functions in quality assurance of semiconductor
devices. The manufacturing Inner Process Quality
Control is shown in Fig. 3.
The other activities of quality assurance are as
follows:
(1) Outside vendor technical information meeting.
(2) Approval and guidance of outside vendors.
(3) Chemical analysis and test.
The typical check points of parts and materials are
shown in Table 1.
Tillie' OuIlity Control Check Paints of Material and Parts
(Examplel
Material,
Parts
Wafer
Mask
Fine
Wire for
Wire
Bonding
Frame
Ceramic
Package
Plastic
28
Important
Control Items
Appearance
Dimension
Sheet Resistance
Defect Density
Crystal Axis
Appearance
Dimension
Resistoration
Gradation
Appearance
Dimension
Purity
Elongation Ratio
Appearance
Dimension
ProceSSing
Accuracy
Plating
Mounting
Characteristics
Appearance
Dimension
Leak Resistance
Plating
Mounting
Characteristics
Electrieel
Characteristics
Mechanical
Strength
CompOSition
Electrical
Characteristics
Thermal
Characteristics
Molding
Performance
Mounting
Characteristics
Point for Check
Damage and Contamina·
tion on Surface
Flatness
Resistanee
Defect Numbers
Defect Numbers, Scratch
Dimension Level
(1) Quality Control of Semi-final Products and Final
Products
Potential failure factors of semiconductor devices
are removed in the manufacturing process. To
achieve this, check points are set-up in each process and products which have potential failure
factors are not moved to the next process step.
Manufacturing lines are rigidly selected and tight
inner process quality controls are executed-rigid
checks in each process and each lot, 100% inspection to remove failure factors caused by manufacturing variables and high temperature aging and
temperature cycling. Elements of inner process
quality control are as follows:
• Condition control of equipment and workers
environment and random sampling of semifinal products.
• Suggestion system for improvement of work.
• Education of workers.
• Maintenance and improvement of yield.
• Determining quality problems, and implement·
ing countermeasures.
• Transfer of quality information.
Uniformity of Gradation
(2) Quality Control of Manufacturing Facilities and
Measuring Equipment
Manufacturing equipment is improving as higher
performance devices are needed. At Hitachi, the
automation of manufacturing equipment is encouraged. Maintenance Systems maintain operation of high performance equipment. There are
daily inspections which are performed based on
related specifications. Inspection points are listed
in the specification and are checked one by one to
prevent any omission. As for adjustment and
maintenance of measuring equipment, specifications are checked one by one to maintain and
improve quality.
Contamination, Scratch,
Bend, Twist
Purity Level
Mechanical Strength
Contamination, Scratch
Dimension Level
Bondability, Solderability
Heat Resistance
Contamination, Scratch
Dimension Level
Airtightness
Bondability, Solderability
Heat Resistance
Mechanical Strength
Characteristics of
Plastic Material
(3) Quality Control of Manufacturing Circumstances
and Sub-Materials
The quality and reliability of semiconductor devices
are highly affected by the manufacturing process.
Therefore, controls of manufacturing circum-
Molding Performance
Mounting Characteristics
$
HITACHI
QUALITY ASSURANCE
stances such as temperature, humidity and dust,
and the control of submaterials, like gas, and pure
water used in a manufacturing process, are intensively executed.
attention to buildings, facilities, air conditioning
systems, delivered materials, clothes, work environment, and periodic inspection of floating dust
concentration.
Dust control is essential to realize higher integration and higher reliability of devices. At Hitachi,
maintenance and improvement of cleanliness at
manufacturing sites is accomplished through
3.3.3 Final Product Inspection and Reliability
Assurance
(1) Final Product Inspection
Lot inspection is done by the quality assurance
Control Point
Process
Purpose of Control
Purchase of Material
Wafer
wafer~
, Surface Oxidation
Inspection on Surface
Oxidation
Photo Resist
Inspection on Photo Resist
<> PQC Level Check
Diffusion
Oxidation
Appearance, Thickness of
Oxide Film
Inspection on Evaporation
<> PQC Level Check
Wafer Inspection
Scratch, Removal of Crystal
Defect Wafer
Assurance of Resistance
Pinhole, Scratch
Photo
Resist
Dimension, Appearance
Diffusion
Inspection on Diffusion
<> PQC Level Check
Evaporation
Characteristics, Appearance
Diffusion Depth, Sheet
Resistance
Gate Width
Characteristics of Oxide Film
Breakt.!own Voltage
Evaporation
Thickness of Vapor Film,
Scratch, Contamination
Wafer
Thickness, VTH Characteristics
Electrical Characteristics
Dimension Level
Check of Photo Resist
Diffusion Status
Control of Basic Parameters
(VTH, etc.) Cleanness of surface,
Prior Check of VIH
Breakdown Voltage Check
Assurance of Standard
Thickness
Prevention of Crack,
Quality Assurance of Scribe
Inspection on Chip
Electrical Characteristics
Chip Scribe
Inspection on Chip
Appearance
<> PQC Lot Judgement
Chip
Assembling
Assembling
Appearance after Chip
Bonding
Appearance after Wire
Bonding
Pull Strength, Compression
Width, Shear Strength
Appearance after Assembling
Quality Check of Chip
Bonding
Quality Check of Wire
Bonding
Prevention of Open and
Short
Sealing
Sealing
<> PQC Level Check
Final Electrical Inspection
<> Failure Analysis
Appearance after Sealing
Outline, Dimension
Marking Strength
Guarantee of Appearance
and DimenSion
Marking
AnalySis of Failures, Failure
Mode, Mechanism
Feedback of Analysis Information
Appearance of Chip
Frame
<> PQC Level Check
Inspection after
Assembling
<> PQC Lot Judgement
Appearance Inspection
Sampling Inspection on
Products
Receiving
Shipment
Figure 3 Example of Inner Process Quality Control
eHITACHI
29
QUALITY ASSURANCE - - - - - - - - - - - - - - - - - - - - - department for products which were judged good
in 100% test ... the final process in manufacturing. Though 100% yield is expected. sampling
inspection is executed to prevent mixture of bad
product by mistake. The inspection is executed not
only to confirm that the products have met the
users' requirements but also to consider potential
quality factors. Lot inspection is executed based
on MIL-STO-1050.
(2) Reliability Assurance Tests
To assure the reliability of semiconductor devices.
reliability tests and tests on individual manufacturing lots that are required by the user. are periodically performed.
I
Customer
Claim
(Failures, Information)
Sales Dept.
Sales Engineering Dept.
r------------~---------------------l
Failure Analysis
Qual ity Assu ranee Dept.
1
L
Countermeasure
Execution of
Countermeasure
Design Dept.
Manufacturing Dept.
Report
Quality Assurance Dept.
L----- _______
4
I---
Follow-up and Confirmation
of Countermeasure Execution
Report
____________________
Sales Engineering Dept.
Reply
Customer
Figure 4 Process Flow Chart of Field Failure
30
$
HITACHI
~
RELIABILITY TEST DATA
1. INTRODUCTION
Microcomputers provide high reliability and quality to meet
the demands of increased functions, enlarging scale, and widening application. Hitachi has improved the quality level of
microcomputer products by evaluating reliability, building
quality into the manufacturing process, strengthening inspection
techniques, and analyzing field data.
The following reliability and quality assurance data for
Hitachi 8-bit single-chip microcomputers indicates results from
test and failure analysis.
2. PACKAGE AND CHIP STRUCTURE
2.1 Packaging
Production output and application of plastic packaging continues to increase, expanding to automobile measuring and control systems, and computer terminal equipment operating under
severe conditions. To meet this demand, Hitachi has significantly
improved moisture resistance and operational stability in the
plastic manufacturing process.
Plastic and side-brazed ceramic package structures are shown
in Figure 1 and Table I.
(11 Plastic DIP
(21 Plastic Flat Package
Bonding wire
Bonding wire
Chip
Figure 1 Package Structure
Table 1 Package Material and Properties
Item
Plastic DIP
Plastic Flat Package
Package
Epoxy
Epoxy
Lead
Solder dipping Alloy 42
Solder plating Alloy 42
Die bond
Au-Si or Ag paste
Au-Si or Ag paste
Wire bond
Thermo compression
Thermo compression
Wire
Au
Au
Cf)HITACHI
31
RELIABI LlTY TEST D A T A - - - - - - - - - - - - - - - - - - - - - - - - - - 2.2 Chip Structure
The HMCS6800 family is produced in NMOS EjD technology or low power CMOS technology. Si-gate process is used
in both types to achieve high reliability and density. Chip structure and basic circuitry are shown in Figure 2.
Si·Gate N-channel E/D
Drain
Source
FEn
Drain
Si·Gate CMOS
SiO.
Source
Source
FET2
FET2
P-channel
EMOS
N-channel
DMOS
FET2
N-channel
EMOS
N-channel
EMOS
Figure 2 Chip Structure and Basic Circuit
3. QUALITY QUALIFICATION AND EVALUATION
3.1 Reliability Test Methods
Reliability test methods shown in Table 2 are used to qualify and evaluate new products and processes.
Table 2 Reliability Test Methods
Test Items
32
Test Condition
MIl·STD·883B Method No.
Operating life Test
125°C,10oohr
1005,2
High Temp, Storage
Low Temp, Storage
Steady State Humidity
Steady State Humidity Biased
Tstg max, 1000hr
Tstg min, 1000hr
65°C 95%RH, 1oo0hr
85°C 85%RH, 1000hr
1008,1
Temperature Cycling
Temperature Cycling
Thermal Shock
Soldering Heat
MechanicaJ Shock
Vibration Fatigue
Variable Frequency
Constant Acceleration
lead Integrity
-55°C'" 150°C, 10 cycles
_20° C '" 125° C: 200 cycles
O°C'" 100°C, 100 cycles
260° C, 10 sec
1500G 0.5 msec, 3 times/X, V, Z
60Hz 20G, 32hrs/X, V, Z
2o-2000Hz 200, 4 min/X, V, Z
200000, 1 min/X, V, Z
225gr, 90° 3 times
1010,4
~HITACHI
1011,3
2002,2
2005,1
2007,1
2001,2
2004,3
- - - - - - - - - - - - - - - - - - - - - - - - - - R E L I A B I LlTY TEST DATA
3.2 ReilabiHty Test R••ults
Reliability Test Results of 8-bit single-chip microcomputer'
devices are shown in Table 3 to Table 7.
Table 3 Dynamic Life Test
Sample Size
Device
Component Hour
Failure
HD6801P
191
191000
0
114
114000
0
HD6805P
.........................................................................
, .....................................................................................................
HD6301P
92
92000
0
HD63L05FP
40
40000
0
56
56000
0
HD6305XP
22
22
HD68POl
HD68P05
o
22000
22000
o
Table 4 High Temperature. High Humidity Test (Moisture Resistance Test)
(1) 85°C 85%RH Bias Test
Device
.vcc Bias
168 hrs
500 hrs
HD6801P
HD6805P
HD6301P
Total
5.5V
5.5V
5.5V
0/22
0/22
0/176
0/220
0/22
0/22
0/131
0/175
1000 hrs
0/22
0/22
0/131
0/175
(2) High Temperature High Humidity Storage Life Test
Device
Condition
16B hrs
HD6801P
HD6805P
HD6301P
HD6301P
HD63L05FP
HD63L05FP
HD6305XP
65°C 95%RH
65°C 95%RH
65°C 95%RH
85°C 95%RH
65°C 95%RH
85°C 95%RH
65°C 95%RH
0/45
0/45
0/603
0/234
0/160
0/160
0/373
500 hrs
0/45
0/45
0/603
1*/234
0/160
1*/160
0/373
1000 hrs
0/45
0/45
0/603
0/233
0/160
0/159
0/373
* Aluminium corrosion
(3) Pressure Cooker Test
(121°C.2atm)
Device
HD6801P
HD6805P
HD6301P
HD6305XP
HD63L05FP
40hrs
60 hrs
100 hrs
200 hrs
0/13
0/44
0/135
0/83
0/80
0/13
0/44
0/135
0/83
0/80
0/13
0/44
0/135
0/83
1*/80
0/13
0/44
0/135
0/83
2**/79
* Current leakage
** Current leakage and aluminium corrosion
_HITACHI
33
RELIABILITY TEST DATA - - - - - - - - - - - - - - - - - - - - - - - - - (4) MIL-STD-883B Moisture Resistance Test
(-65°C"'" _10°C, 90%~H or more)
Device
10 cycles
20 cycles
40 cycles
HD6801P
HD6805P
HD6301P
HD63L05FP
0/50
0/32
0/75
0/22
0/50
0/32
0/75
0/22
0/50
0/32
0/75 .
0/22
100 cycles
200 cycles
Table 5 Temperature Cycling Test
(-55°C - 150°C)
Device
10 cycles
HD6801P
0/102
0/102
01102
HD6805P
0/442
0/45
0/45
HD6301P
0/258
0/258
0/258
HD6305XP
0/80
0/80
0/80
..............................................................................................................................................................................
HD68P01
0/44
0/44
0/44
HD68P05
0/68
0/19
0/19
Table 6 High Temperature, Low Temperature Storage life Test
Device
Temperature
168 hrs
500 hrs
1000 hrs
HD6801P
150°C
-55°C
0/22
0/22
0/22
0/22
0/22
H D6805P
_55° C
0/22
0/22
0/22
0/22
0/22
0/22
0/22
0/22
0/22
0/22
.......................................... ················,·50°C·················· ··················Oi"4·4·············· ············ .. ····Oi44··············· ·················0/44···············
.......................................... ················1·50°C·················· ··················o"Fii············· ··················Oi22··············· ················0/22···············
HD6301P
..........................................
HD63L05FP
-55°C
················150~C··················
··················0/2"2"············· ··················Oi22··············· ················0·i22···············
-55 C
Table 7 Mechanical and Environmental Test
Test Item
Plastic DIP
Condition
Flat Plastic Package
Sample Size
Failure
Thermal Shock
0°C-100°C
10 cycles
110
0
100
0
Sample Size
Failure
Soldering Heat
260° C. 10 sec.
164
0
20
0
Salt Water Spray
35°C, NaCI 5%
24 hrs
110
0
20
0
Solderabil ity
230°C, 5 sec.
Rosin flux
159
0
34
0
Drop Test
75cm, maple board
3 times
110
0
20
0
Mechanical Shock
1500G, 0.5ms
3 times/X, V, Z
110
0
20
0
Vibration Fatigue
60 Hz, 20G
32hrs/X, V, Z
110
0
20
0
Vibration Variable Freq.
100- 2000Hz
20G, 4 times/X, V, Z
110
0
20
0
Lead Integrity
225g,900
Bonding 3 times
110
0
20
0
34
$
HITACHI
- - - - - - - - - - - - - - - - - - - - - - - - - - RELIABI LIlY lEST DATA
4.
PRECAUTIONS
4.3 Handling for Measurement
4.1 Storage
To prevent deterioration of electrical characteristics, solderability, appearance or structure, Hitachi recommends semiconductor devices be stored as follows:
(I) Store in ambient temperatures of 5 to 300 C, with a relative
humidity of 40 to 60%.
(2) Store in a clean, dust- and active gas-free environment.
(3) Store in conductive containers to prevent static electricity.
(4) Store without any physical load.
(5) When storing devices for an extended period, store in an
unfabricated form, to minimize corrosion of pre-formed
lead wires.
(6) Unsealed chips should be stored in a cool, dry, dark and
dust-free environment. Assembly should be performed
within 5 days of unpacking. Devices can be stored for up to
20 days in dry nitrogen gas with a dew point at -300 C or less.
(7) Prevent condensation during storage due to rapid temperature changes.
Avoid static electricity, noise and voltage surge when measuring or mounting devices. Precaution should be taken against
current leakage through terminals and housings of curve tracers,
synchroscopes, pulse generators, and DC power sources.
When testing devices, prevent voltage surges from the tester,
attached clamping circuit, and any excessive voltage possible
through accidental contact.
In inspecting a printed circuit board, power should not be
applied if any solder bridges or foreign matter is present.
4.4 Soldering
Semiconductor devices should not be exposed to high
temperatures for excessive periods. Soldering must be performed
consistent with temperature conditions of 2600 C for 10 seconds,
3500 C for 3 seconds, and at a distance of I to 1.5mm from the end
of the device package.
A soldering iron with secondary voltage supplied through a
grounded transformer is recommended to protect against
leakage current. Use of alkali or acid flux, which may corrode the
leads, is not recommended.
4.2 Transportation
General precautions for electronic components are applicable in transporting semiconductors, units incorporating semi- .
conductors, and other similar systems. In addition, Hitachi
recommends the following:
(I) When transporting semiconductor devices or printed circuit
boards, minimize mechanical vibration and shock. Use containers or jigs which will not induce static electricity as a
result of vibration. Use of an electrically conductive container or aluminum foil is recommended.
(2) To prevent device deterioration from clothing-induced static
electricity, workers should be properly grounded while handling devices. Use of a I M ohm resistor is recommended to
prevent electric shock.
(3) When transporting printed curcuit boards containing semiconductor devices, suitable preventive measures against
static electricity must be taken. Voltage build-up can be
avoided by shorting the card-edge terminals. When a belt
conveyor is used, apply some surface treatment to prevent
build-up of electrical charge.
(4) Minimize mechanical vibration and shock when transporting semiconductor devices or printed circuit boards.
$
4.6 Removing Residual Flux
Detergent or ultrasonic removal of residual flux from circuit
boards is necessary to ensure system reliability. Selection of
detergent type and cleaning conditions are important factors.
When chloric detergent is used for plastic packaged devices,
care must be taken against package corrosion. Extended
cleaning periods and excessive temperature conditions can cause
the chip coating to swell due to solvent permeation. Hitachi
recommends use of Lotus and Dyfron solvents. Trichloroethylene solvent is not suitable.
The following conditions are advisable for ultrasonic
cleaning:
•
Frequency: 28 to 29 k Hz (to avoid device resonation)
•
Ultrasonic output: 15WIi
•
Keep devices from making direct contact with power
generator
•
Cleaning time: Less than 30 seconds.
HITACHI
35
DESIGN PROCEDURE AND SUPPORT TOOLS FOR
8-BIT SINGLE-CHIP MICROCOMPUTERS
The cross assmebler and hardware simulator using various
types of computers are prepared by Hitachi as supporting systems to develop user's programs.
User's programs are mask programmed into the ROM and
delivered as the LSI by the company.
Fig. I shows the typical program design procedure and Table
I shows the system development support tools for the 8-bit
single-chip microcomputer family used in these processes.
Text Editor I CRT Editor
Evaluation Kit
H68SD5
Intel MDS
PDP·11
VAX-11
IBM370
®
Crou Agembler
Evaluation Kit
H68SD5
Intel MDS
PDP-11
VAX-11
IBM370
Evaluation Kit
Evaluation Board
H68SD5
EPROM on the Package Type
Microcomputer
HD68P01V07
HD68P05V07
HD68P05WO
[ HD63P01M1
HD63P05YO
No
(E xplanat ion)
CD When the user programs the system, the predetermined functions are
assigned to the I/O pin and the RAM before the programming.
® A flow chart is designed to achieve the predetermined functions and the flow
chart is coded by using the prenumeric code.
@ The coded flow chart is punched into the card or the paper tape or written into
the floppy disk, to generate a source program.
@ The source program is assembled by the resident system (evaluation kit) or the
cross system, to generate the object program. In this case, errors during
the assembling are also detected.
® Hardware simulation is performed to confirm the program.
The company provides four kinds of hardware, the H68SD5, the evaluation kit,
the evaluation board and the EPROM on the package type microcomputer. The
consumers are able to choose the best suitable tool.
® The completed program is sent to the company in the form of EPROM or the
object tape.
Q) Options such as ROM is masked by the company, LSI
is testatively produced
and the sample is handed in to the user. After the user has evaluated the
sample and confirmed that the program is correct, mass production is
started.
Figure 1 Program Design Procedure
36
~HITACHI
DESIGN PROCEDURE AND SUPPORT TOOLS
- - - - - - - - - - - - - - - - - - - - - - - - - F O R 8-BIT SINGLE-CHIP MICROCOMPUTERS
Table 1 System Development Support Tools
Resident System
Type No.
Evaluation Kit
HD6801S0
HD6801VO
Evaluation
Board
EPROM on
the Package
Cross System
H68SDS + Emulator Set
(Hardware + Software)
IBM 370
H61 EVT2 (Hardware)
+
HD68P01V07
H68SDS + H61MIX1
S31XSY1-T
S61MIX2-R (Software)
PDP-11/
Intel
MDS220/230 VAX -11
S31MDS1-F
(ISIS-II)
S31MDS2-F
(CP/M)
H31EVT1 (Hardware)
+
HD63P01M1
H68SDS + H31MIX1
S31MIX1-R (Software)
S31XSY1-T S31MDS1-F
------+--'=-=-.:~::"O"':"..:....:.....J=:...:..:..:..:=--+--'---_+---__:-_;-------___1
(ISIS-II)
H 0630..:..;1X~O-;;*:;d·_ _ _ _-_ _ _-4---:..H-"3_1_EV~0_'_1_*t__'_'_H=.D.=.:63=-=7-=0'-'-1:.;.Xo=-t*_*-t--'-H..;...:6:....=8-=-SD~~S_+.. :. H:. . =3.. :. 1M~IX-,2'--J
S31 MDS2-F
HD6301YO**
H68SDS + H31MIX3(CP/M)
HD6301V1
HD630SUO-
**
0
o
~
~
0
H68SDS + **
HD630~~V~~_*r_-----------r_------~---------r_---------_+---------
HD630SXO*
HD630Sxf*
HD630SYO'"
HD630SY1*
H3SEVOO* HD63POSYOH3SEVT1
(Hardware + Software) 1----*-*---f-H-D-6-3-PO-S-Y-0--c::--i H68SDS + H3SMIX1
S6SMDS1-F
(ISIS-II) *~
S3SMDS1-F
(ISIS-II)
---------+----------------r--------r--------~--------------_+-----~ S3SMDS2-F*~
HD63LOSF1
* Preliminary
H3LSEVT1 (Hardware)
H3LSEVOO
+
S3LSMIX1-R (Software
** Under development
(CP/M)
-
t EPROM On-chip Type
H68SDS + H3L5MIX1
0 Available from Microtec.
~HITACHI
37
DESIGN PROCEDURE AND SUPPORT TOOLS
FOR 8-BIT SINGLE-CHIP M I C R O C O M P U T E R S - - - - - - - - - - - - - - - - - - - - - - - •
SINGLE-CHIP MICROCOMPUTER DEVELOPMENT SYSTEM
The H68S0S is a development system for Hitachi 4-bit and
8-bit single-chip microcomputers.
It is a compact H06800-based CRT/Key board microcomputer terminal, with two Floppy disk drivers, and has standard
interface for the TTY (RS-232C or TTL level) and printer (Centronics parallel interface). An optional EPROM Writer is
available.
•
Disk based low cost system
•
Provides the CRT Editor, Assembler, Emulator, and
EPROM Writer controlled by FOOS-III
•
S6k-byte RAM
•
Allows linking between the H68S0S and the I/O devices
(TTY and Printer)
•
Easy to debug user's prototype system using the Emulator
Module
Features
•
Supports system development for 8-bit and 4-bit single-chip
microcomputers.
System Configuration
H68SD5
EPROM Writer
Emulator Module
8-bit single-chip miCrO-]
computer family
HMCS40 series
1
38
~HITACHI
DATA SHEETS
Preliminary data sheets herein contain information on new products. Specifications and information are subject to change without notice.
Advance Information data sheets herein contain information on products
under development. Hitachi reserves the right to change or discontinue these
products without notice.
HD6801S0, HD6801S5--MCU (Microcomputer
The H))6801S MCU is an 8·bit microcomputer system
which is compatible with the HMCS6800 family of parts. The
H))6801S MCU is object code compatible with the H06800
with improved execution times of key instructions plus several
new. 16.oit and 8·bit instructions including an 8x8 unsigned
multiply with 16-bit result. The HD6801S MCV can operate
as a single - chip microcomputer or be expanded to 65k
words. The H06801S MCV is TTL compatible and requires
one +5.0 volt power supply. The HD6801S MCV has 2k
bytes of ROM and 128 bytes of RAM on chip. Serial Com·
munications interface (S.C.I.), and parallel I/O as well as a
three function 16-bit timer. Features and Block diagram of
the H06801S include the following:
FEATURES
Expanded HMCS6800 Instruction Set
•
•
8 x 8 Multiply
On·Chip Serial Communications Interface (S.C.I.)
•
Object Code Compatible With The HD6800 MPU
•
•
HD6801S0P
HD6801S5P
(DP-40)
•
•
•
Unit)
PIN ARRANGEMENT
o
SC,
SC2
P30
P 3,
H)·Bit Timer
Single Chip Or Expandable To 65k Words
P32
P33
• 2k Bytes Of ROM
•
128 Bytes Of RAM (64 Bytes Retainable On Power
Down)
•
•
•
29 Parallel I/O Lines And 2 Handshake Control Lines
Internal Clock/Divided-By-Four Circuitry
TTL Compatible Inputs And Outputs
P 34
P 35
HD6801S
P 38
P 37
Poe
p.,
p.2
•
Interrupt Capability
P 43
•
Compatible with MC6801 and MC6801-1
P44
•
BLOCK DIAGRAM
P4e
p. 7
P 17
1 Vee Standby
(Top View)
•
TYPE OF PRODUCTS
MCU
Bus Timing
HD6801SO
1 MHz
HD6801S5
1.25 MHz
a.---P,o
P"
PI)
~==:PII
~==:~::
1----PI6
I----P"
@HITACHI
41
HD6801S0,HD6801S5--------------------------------------------~~--~
•
ABSOLUTE MAXIMUM RATINGS
Item
Value
Symbol
Supply Voltage
*
*
Unit
-0.3-+7.0
V
V
°c
°c
Input Voltage
Vee
V ln
Operating Temperature
Topr
-0.3 - +7.0
0 -+70
Storage Temperature
TIIa
- 55 -+150
- With respect to VSS (SYSTEM GND)
[NOTE] Permanent lSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded. it- could aftect reliability of LSI.
•
ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vee -5.0V±5%, Vss - OV, Ta" 0 - +70°C, unless otherwise noted.)
Item
Input "High" Voltage
Input "Low" Voltage
Symbol
RES
Input Load Current
V 1H
Other Inputs·
All Inputs·
P40 -
VIL
P47
SCI
EXTAL
Vi" = 0- Vee
Input Leakage Current
NMI. IRQI, RES
PIO
P20
Output "High" Voltage
P30 "" P37
P40 - P47 , E, SCI. SC 2
Other Outputs
Output "Low" Voltage
Vee Standby
Standby Current
-
-
Vi" = 0 - 5.25V
TS
Vi" = 0.5 - 2.4V
II
"
V OH
VOL
-IOH
P17
P30 - P37 , P40
Other Inputs
Ilinl
P37
All Outputs
Darlington Drive Current PIO
Power Dissipation
Input Capacitance
-
P17 , P30
P24
Vi" = 0- 2.4V
lIinl
Three State (Offset)
Leakage Current
-
Test Condition
P47 , SCI
Cin
max
Unit
-
Vee
2.0
-
V
-0.3
-
Vee
0.8
V
-
-
-
-
-
-
0.8
0.8
mA
2.5
10
100
p.A
-
-
0.5
-
10.0
V
rnA
-
-
1200
rnW
-
12.5
-
10.0
5.25
2.4
V out = 1.5V
-
Powerdown
V SBB
4.0
Operating
V SB
4.75
-
5.25
Powerdown
ISBB
-
8.0
eHITACHI
-
V
-
-
V SBB = 4.0V
p.A
1.0
I LOAD = -100 p.A
I LOAD = 1.6 rnA
Vi" = OV, Ta = 25°C,
f=1.0MHz
-
0.5
-
2.4
2.4
-Except Mode Programming levels.
42
typ
I LOAD = -205 p.A
I LOAD = -145 p.A
Po
-
min
4.0
pF
V
rnA
-----------------------------------------------------HD6801S0,HD6801S5
• AC CHARACTERISTICS
BUS TIMING (Vee = 5.0V±5%, Vss '"' OV, Ta = 0 - +70°C, unless otherwise noted.)
Symbol
Item
Cycle Time
Address Strobe Pulse Width "High"
l
I
I
I
HDS801S0
typ
min
max
1
10
200
5
50
5
50
SO
50
5
5
50
450
450
SO
250
270
225
80
10
20
60
-
-
tCYC
PW ASH
Address Strobe Rise Time
Address Strobe Fall Time
Address Strobe Delay Time
Enable Rise Time
Enable Fall Time
Enable Pulse Width "High" Time
Enable Pulse Width "Low" Time
Address Strobe to Enable.Delay Time
Address Delay Time
Address Delay Time for Latch (f = 1.0MHz)
Data Set-up Write Time
Data Set-up Read Time
Read
Data Hold Time
Write
Address Set-up Time for Latch
Address Hold Time for Latch
Address Hold Time
Non-Multiplexed Bus
Peripheral Read
Access Time
Multiplexed Bus
Oscillator stabilization Time
Processor Control Set-up Time
PERIPHERAL PORT TIMING (Vee
Test Condition
-
tASr
tASf
tASO
' ter
-
tEf
PW EH
PW EL
tASEO
tAD
tAOL
tosw
tOSR
tHR
tHW
tASL
tAHL
tAH
(tACCN)
(tACCM)
-
Fig. 1
Fig. 2
-
Fig. 10
Fig. 11
tRC
tpcs
=5.0V ±S%, Vss = OV. Ta = 0 -
20
20
-
-
-
-
-
-
(510)
(600)
100
200
min
0.8
150
5
5
30
5
5
340
350
30
-
-
-
-
50
50
-
50
50
-
-
-
-
-
-
-
-
-
-
-
-
100
200
-
-
/J.s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
260
260
-
20
20
Unit
-
-
-
115
70
10
20
50
-
-
HDS801S5
typ
max
10
ns
-
ns
ns
ns
(420)
(420)
ns
-
ms
ns
-
+70°C, unless otherwise noted.)
Symbol
Test Condition
min
typ
max
Unit
Peripheral Data Setup Time
Port 1, 2,3,4
tpDSU
Fig. 3
200
Port 1,2,3,4
tpDH
Fig. 3
200
-
ns
Peripheral Data Hold Time
Delay Time, Enable Positive Transition
to 053 Negative Transition
tOS01
Fig. 5
-
-
350
ns
Delay Time, Enable Positive Transition
to 053 Positive Transition
tOSD2
Fig. 5
-
-
350
ns
Delay Time, Enable Negative
Transition to Peripheral Data
Valid
Port 1, 2*,3,4
tpwD
Fig. 4
-
-
400
ns
Delay Time, Enable Negative
Transition to Peripheral
CMOS Data Valid
Input Strobe Pulse Width
*
Port 2**, 4
tCMOS
Fig. 4
-
-
2.0
lAS
tpWIS
Fig. 6
200
Input Data Hold Time
port 3
tlH
Fig. 6
50
Port 3
tIS
Fig. 6
20
-
ns
Input Data Set-up Time
-
Item
ns
ns
ns
**'Okn pull up register required for Port 2
~HITACHI
43
H06801 SO,H06801 55
TIMER, SCI TIMING (Vee" 5.0V ±5%, vss" OV, Ta = 0"'" +70°C, unless otherwise noted.)
Symbol
Item
Timer Input Pulse Width
Delay Time, Enable Positive Transition to
Timer Out
SCI Input Clock Cycle
SCI Input Clock Pulse Width
Test Condition
tpWT
Fig. 7
tTOD
min
2t cvc+200
1
0.4
tSCYC
tpwsCK
typ
max
-
-
Unit
ns
600
ns
-
tCYC
tScYc
0.6
MODE PROGRAMMING (Vee· 5.0V ±5%, VSS'" OV, T8 - 0"'" +70°C, unless otherwise noted.)
Symbol
VMPL
Item
Mode Programming Input "Low" Voltage
Mode Programming Input "High" Voltage
RES " Low" Pulse Width
Mode Programming Set-up Time
Mode Programming
Hold Time
lm
Im
Test Condition
VMPH
PW RSTL
tMPS
Rise Time ~ 11ls
Rise Time < 11ls
tMPH
Fig. 8
min
typ
-
-
4.0
3.0
2.0
-
0
100
-
~---------------------t~----------------------~
Address Strobe
(AS)
2.2V
Enable
(E)
R/VV Aa-A15
(Sell' (Port4)
MCUWrite
Do-D,.A.-A,
(Port 3)
MCU Read
0.-0" A.-A,
(Port 3)
Figure 1 Expanded Multiplexed Bus Timing
44
_HITACHI
-
max
1.7
-
-
-
Unit
V
V
tcyc
tcyc
ns
-----------------------------------------------------HD680150,HD680155
.
2~kEnable
CEI
I
i
PWEL
~
-
-tAD-
)
.
~
,
O.5V
.
tcvc
-k-
_ _--PWEH
-(
--
-tEt
-tEr
-tAH
2.2V)f-
1\
J~
Address Valid
0.6~
-tosw2.2V ,..
MCU Write
0.-0,
(Port 3)
J
-
Data Valid
"1"l
0.6V\"
.
.
-tOSR-
hACCNI
_t_
-l~
M~~~~:d------------------------------------------2._0_V<1
-
_IHR
Dala Valid
O.BV
(Port 3)
Figure 2 Expanded Non-Multiplexed Bus Timing
1
MCUWrite
rMCURead
Enable(E)
Enable(E)
_tcMos_1
PI. - P.,
_tpwo
p •• - p ••
p.. -P.,
Inputs
-------,
All Data
Port Outputs _ _ _ _ _ _ _ _ _ _01
,If ---~:~~
0.7 VCC
Data Valid
PJO - P"
Inputs"
"Port 3 Non-Latched Operation CLATCH ENABLE
Figure 3
= 01
(NOTE)
1. 10 kn Pullup resistor required for Port 2 to reach 0.7 Vee
~: ~~r~ 'T:~~~~e~o:UUed above VCC
Data Set-up and Hold Times
(MCU Read)
Figure 4
iS3
053------
p s• - P"
Inputs
Port Data Delay Timing
(MCU Write)
2.0V
2.0V
O.BV
"Access matches OutPUt Strobe Select COSS = 0, a read;
OSS ·1. a writel
Figure 5 Port 3 Output Strobe Timing
(Single Chip Mode)
Figure 6 Port 3 Latch Timing
(Single Chip Mode)
eHITACHI
45
HD6801SO,HD6801S5---------------------------------------------------Enable
(E)
Timer
Counter _ _ _ _...J
'-~~-..,;,;.......,
' -_ __
I~,I:;':: 1.----....;.:::;~"1I:...-----~r
Pl I
Output
Figure 8
Mode Programming Timing
Figure 7 Timer Output Timing
Vee
Test Point
CO)-----l..
m
RL.Z.Zkll
30pF
TlSt Point
r
152074
®
0' EQuiv.
C
R
E. SC.. SC,
R: ~~g ::~ k.:"p'.';."r.:~;'.~E.SC .. 5C,
C· SOpF fM p .. -P.,. p •• -p...
• 30pF fM p •• -p".p.. -p,.
la) CMOS Load
Ib) TTL Load
Figure 9 Bus Timing Test Loads
LM' Ins"uc'ion
-I
In,,,nll
.~.~~_~n.-~~~~~~~_~"-_~~~~~
__
~_~n.~~~~_"~~,,-~~_~~
__ ___
~
iiiO.
*----..,
NIiI~1IUf.
~~~-------------------------------------------------------
In..'n.I~r_--_v---..,.--~r_-'""'~-'V'---~-""",...-~--'V'---..,.-"""\,..--v_-~~-_v--V"'0 ....uIJl_ _
__
_ _""__..... _ _''__.....''__
~
In,,,no' AfiV
~"__-"~_.".~-""-....J"-_~~_.A
~
_'''~_A_~~_
*IROz .... Internal Interrupt \,,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
Figure 10 Interrupt,Sequence
E
$\\\\\\\\\\\\\\\ ~\\\\\\\\\\\\\\\ LrLfl. ~ fl[l..flI
;':Ii.~2Ii:':'V---""', ------------11
~
1-------"""1, Iol-------------I)0\
Va:
__
"U
•. 7SV
' I..
.------------'AC--------~--'''CS
•
dO
"I
t
-I'CII
1I:
__
o;:,.v~
..
_ _ _ __
...::.'.''":' %§\\\w\%\%\\\t _\\\\S\\\\§\S\\\\\\~~
.
FFFE
~ ~
F
. .lUI
In,.,nII AfIR 1'I&~~rtS~S\rtS~$~~rtS'f'S\:rtS~ijrtS"&~~~....S...~I"'IS~S..'\..'\ :I"'IS:'\'S...\\I"'ISI"'l'\~S...'\...S..S~~rtS...S..\\~SI"'lSYiW'--------------------~
B\1NO,Vllod
Figure 11 Reset Timing
46
_HITACHI
:=x::=r-
-----------------------------------------------------HD6801S0,HD6801S5
• SIGNAL' DESCRIPTIONS
•
• Vee.nd Vss
These two pins are used to supply power and ground to the
chip. The voltage supplied will be +5 volts ±5%.
• XTAL.mt EXTAL
These connections are for a parallel resoll .• ( fundamental
crystal. AT cut. Divide by 4 circuitry is included with the
internal clock. so a 4 MHz crystal may be used to run the
system at 1 MHz. The divide by 4 circuitry allows for use of the
inexpensive 3.58 MHz Color TV crystal for non·time critical
applications. Two 22pF capacitors are needed from the two
crystal pins to ground to insure reliable operation. EXT AL may
be driven by an external clock source at a 4 MHz rate to run at
1 MHz with a 40/60% duty cycle. It is not restricted to 4 MHz,
IS it wnI divide by 4 any frequency less than or equal to 4 MHz.
XTAL must be grounded if an external clock is used. The
following are the recommended crystal parameters:
Nominal Crystal Parameter
~
5MHz
4MHz
Co
7 pF max.
4.7 pF max.
Rs
6Onmax.
3OnWp.
XTAL~--~-----'
CL 1 ., CL2 = 22pF :t 20%
(3.2 - 5MHz)
CJ
[Note] These are representative
AT cut parallel resonance
crystal parameters.
E)(TAL~-"'...,
Jr
CL1
tL2
Figure 12 Crystal Interface
• Vee StMldby
chip. The first 64 bytes of RAM wnI be maintained in the power
down mode with 8 mA current max. The circuit of figure 13
can be utilized to assure that Vee Standby does not go below
VSBB during power down.
To retain information in the RAM during power down the
following procedure is necessary:
I) Write "0·· into the RAM enable bit, RAM E. RAM E is bit
6 of the RAM Control Register at location $0014. This
disables the standby RAM, thereby protecting it at power
down.
2) Keep Vee Standby greater than VSBB.
i'_,LI'"
J,
Figure 13 Battery Backup for Vee Standby
Enable (E)
This supplies the external clock for the rest of the system
when the internal oscillator is used. It is a single phase, TTL
compatible clock, and will be the divide by 4 result of the'
crystal frequency. It will drive one TTL load and 90 pF.
Non·Maskable Interrupt (NMI)
A low·going edge on this input requests that a non·maskable·
interrupt sequence be generated within the processor. As with
interrupt Request signal, the processor will complete the current
instruction that is being executed before it recognizes the NMI
signal. The interrupt mask bit in the Condition Code Register
has no effect on NMI.
In response to an NMI interrupt, the Index Register, Program
Counter, Accumulators, and Condition Code Register are stored
on the stack. At the end of the sequence, a 16·bit address will
be loaded that points to a vectoring address located in memory
locations $FFFC and $FFFD. An address loaded at these loca·
tions causes the CPU to branch to a non·maskable interrupt
service routine in memory.
A 3.3 kn external resistor to Vee should be used for
wire·OR and optimum control of interrupts.
Inputs IRQl and NMI are hardware interrupt lines that are
sampled during E and will start the interrupt routine on the
E following the completion of an instruction.
•
This pin wnI supply +5 volts ±5% to the standby RAM on the
Vee Standby
•
•
Item
Reset (RES)
This input is used to reset and start the MCU from a power
down condition, resulting from a power failure or an initial
startup of the processor. On power up, the reset must be held
"Low" for at least 100 ms. During operation, REs, when
brought "Low", must be held "Low" at least 3 clock cycles.
When a "High" level is detected, the MCV does the following:
I) All the higher order address lines will be forced "High".
2) I/O Port 2 bits 2, I, and 0 are latched into programmed
control bits PC2, PC 1 and PCO.
3) The last two ($FFFE, $FFFF) locations in memory will
be used to load the program addressed by the program
counter_
4) The interrupt mask bit is set, must be cleared before the
CPU can recognize maskable interrupts.
Interrupt Request (lRQl)
This level sensitiv~ input requests that an interrupt sequence
be generated within the machine. The processor will wait until it
completes the current instruction that it being executed before
it recognizes the request. At that time, if the interrupt mask bit
in the Condition Code Register is not set, the'ml\chine will begin
an interrupt sequence. The Index Register, Progr;un Counter,
Accumulators, and Condition Code Register are stored on the
stack. Next the CPU will respond to the interrupt request by
setting the interrupt mask bit "High" so that no further mask·
able interrupts m~y occur. At the end of the cycle, a 16-bit
address will be loaded that points to a vectoring address which is
located in memory locations $FFF8 and $FFF9. An address
loaded at these locations causes the CPU to branch to an inter·
rupt routine in memory.
The IRQl requires a 3.3 kSl external resister to Vee which
should be used for wire·OR and optimum control of inte'!!!!pts.
Internal Interrupts will use an internal interrupt line (IRQ,).
This interrupt will operate the same as IRQl except that it will
use the vector address of $FFFO through $FFF7. ~ will
have priority over IRQ 2 if both occur at the same time. The
Interrupt Mask Bit in the condition code register masks both
interrupts (See Table 1).
_HITACHI
47
HD6801S0,HD6801S5--------------------------------------------------Table 1 Interrupt Vector Location
Vector
Highest
Priority
Lowest
Priority
MSB
LSB
FFFE
FFFF
FFFC
FFFD
FFFA
FFFB
• PORTS
Interrupt
rn
NMI
-
Software Interrupt (SWII
FFF8
FFF9
IRQ, (or IS3)
FFF6
FFF7
ICF (Input Capture)
OCF (Output Compare)
PFF4
FFF5
FFF2
FFF3
TOF (Timer Overflow)
FFFO
FFF1
SC, (RDRF + ORFE + TORE)
There are four I/O ports on the HD6801S MCU; three 8-bit
ports and one 5-bit port. There are two control lines associated
with one of the 8-bit ports. Each port has an associated write
only Data Direction Register which allows each I/O line to be
programmed to act as an input or an output·. A "1" iii the
corresponding Data Direction Register bit will cause that I/O
line to be an output. A "0" in the corresponding Data Direction
Register bit will cause that I/O line to be an input. There are
four ports: Port 1, Port 2, Port 3, and Port 4. Their addresses
and the addresses of their Data Direction registers are given in
Table 2.
•
The only exception is bit 1 of Port 2, which can either be data
input or Timer output.
Table 2 Port and Data Direction Register Addresses
The following pins are available in the Single Chip Mode, and
are associated with Port 3 only.
•
Input Strobe (lS3) (SCI)
This sets an interrupt for the processor when the IS3 Enable
bit is set. As shown in Figure 6 Input Strobe Tim.!!!B, IS3 will
fall tIS minimum after data is valid on Port 3. If IS3 Enable is
set in the I/O Port 3 Control/Status Register, an interrupt will
occur. If the latch enable bit in the I/O Port 3 Control/Status
Register is set, this strobe will latch the input data from another
device when that device has indicated that it has valid data.
• Output Strobe (Oft) (SC 2 )
This signal is used by the processor to strobe an external
device, indicating valid data is on the I/O pins. The timing for
the Output Strobe is shown in Figure 5 I/O Port 3 Control/
Status Register is discussed in the following section.
The following pins are available in the Expanded Modes.
ReadlWrite (RM) (SC2 )
This TTL compatible output signals the peripherals and
memory devices whether the CPU is in a Read ("High") or a
Write ("Low") state. The normal standby state of this signal is
Read ("High"). This output is capable of driving one TTL load
and 90 pF.
•
• 1/0 Strobe (iOS) (SCI)
In the expanded non-multiplexed mode of operation, lOS
internally decodes A9 through Au as zero's and As as a one.
This allows external access of the 256 locations from $0100 to
SOIFF. The timing diagrams are shown as figure 2.
• AcIdren Strobe (AS) (SCI)
In the expanded multiplexed mode of operation address
strobe is output on this pin. This signal is used to latch the 8
LSB's of address which are multiplexed with data on Port 3. An
8-bit latch is utilized in conjunction with Address Strobe, as
shoWl\ in figure 19. Expanded Multiplexed Mode. Address
Strobe siplals the latch when it is time to latch the address lines
so the lines can become data bus lines during the E pulse. The
timing for this singal is shown in Figure I of Bus Timing. This
Iipal is also used to disable the address from the multiplexed
bus allowing a deselect time, tASD before the data is enabled to
the bus.
Ports
Port Address
Data Direction
Register Addrass
1/0 Port 1
$0002
1/0 Port 2
$0003
$0000
$0001
1/0 Port 3
$0006
$0004
1/0 Port 4
$0007
$0005
• I/O Port 1
This is an 8-bit port whose individual bits may be defined as
inputs or outputs by the corresponding bit in its data direction
register. The 8 output buffers have three-state capability,
allowing them to enter a high impedance state when the.
peripheral data lines are used as inputs. In order to be read
properly, the voltage on the input lines must be greater than 2.0
V for a logic "I" and less than 0.8 V for a logic "0". As out·
puts, these lines are TTL compatible and may also be used as
a source of up to 1 rnA at 1.5 V to directly drive a Darlington
base. After Reset, the I/O lines are configured as inputs. In all
three modes, Port 1 is always parallel I/O.
• 1/0 Port 2
This port has five lines that may be defined as inputs or
outputs by its data direction register. The 5 output buffers have
three-state capability, allowing them to enter a high impedance
state when used as an input. In order to be read properly, the
voltage on the input lines must be greater than 2.0 V for a
logic "1" and less than 0.8 V for a logic "'0". As outputs, this
port has no internal pullup resistors but will drive TTL inputs
directly. For driving CMOS inputs, external pullup resistors are
required. After Reset, the I/O lines are configured as inputs.
Three pins on Port 2 (pins 10, 9, and 8 of the chip) are used
to program the mode of operation during reset. The values of
these pins at reset are latched into the three MSB's (bits 7, 6,
and 5) of Port 2 which are read only. This is explained in the
Mode Selection Section.
In all three modes, Port 2 can be configured as I/O and
provides access to the Serial Communications Interface and the
Timer. Bit 1 is the only pin restricted to data input or Timer
output.
• 1/0 Port 3
,...
This is an 8-bit port that can be configured as I/O, a data bus,
or an address bus multiplexed with the data bus - depending on
the mode of operation hardware programmed by the user at
reset. As a data bus, Port 3 is bi-directional. As an input for
peripherals, it must be supplied regular TTL levels, that is,
greater than 2.0 V for a logic "I "and less than 0.8 V for a logic
"0".
48
eHITACHI
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD680150,HD680155
Its TTL compatible three-state output buffers are capable of
driving one TTL load and 90 pF. In the Expanded Modes, after
reset, the data direction register is inhibited and data flow
depends on the state of the R/W line. The input strobe (lS3)
and the output strobe (083) used for handshaking are explained
later.
In the three modes, Port 3 assumes the following characteristics:
Single Chip Mode: Parallel Inputs/Outputs as programmed by
its associated Data Direction Register. There are two control
lines associated with this port in this mode, an input strobe and
an output strobe, that can be used for handshaking. They are
controlled by the I/O Port 3 Control/Status Register explained
at the end of this section. Three options of Port 3 operations
are sumarized as follows: (I) Port 3 input data can be latched
using IS3 (SC,) as a control signal, (2) OS3 can be generated by
either an CPU read or write to Port 3's Data Register, and (3)
and IRQI interrupt can be enabled by an IS3 negative edge.
Port 3 latch and strobe timing is shown in Fig. 5 and Fig. 6.
Expanded Non-Multiplexed Mode: In this mode, Port 3
becomes the data bus (Do -D,).
Expanded Multiplexed Mode: In this mode, Port 3 becomes
both the data bus (Do -D,) and lower bits of the address bus
(Ao"" A,). An address strobe output is true when the address is
on the port.
load and 90 pF. After reset, the lines are configured as inputs.
To use the pins as addresses, therefore, they should be
programmed as outputs. In the three modes, Port 4 assumes the
following characteristics:
Single Chip Mode: Parallel Inputs/Outputs as programmed by
its associated Data Direction Register.
Expanded Non-Multiplexed Mode: In this mode, Port 4 is
configured as the lower order address lines (Ao-A,) by writing
one's to the data direction register. When all eight address lines
are not needed, the remaining lines, starting with the most
significant bit, may be used as I/O (inputs only).
Expanded Multiplexed Mode: In this mode, Port 4 is
configured as the higher order address lines (As-Au) by writing one's to the data direction register. When all eight address
lines are not needed, the remaining lines, starting with the most
Significant bit, may be used as I/O (inputs only).
• OPERATION MODES
The mode of operation that HD680lS will operate in after
Reset is determined by hardware that the user must wire on pins
10,9, and 8 of the chip. These pins are the three LSD's (I/O 2,
I/O I, and I/O 0 respectively) of Port 2. They are latched into
programmed control bits PC2, PC I, and PeO when reset goes
high. I/O Port 2 Register is shown below.
PORT 2 DATA REGISTER
6543210
I/O PORT 3 COt,aTROL/STATUS REGISTER
7
IS3
$OOOF
Bit 0;
Bit I;
Bit 2;
Bit 3;
Bit 4;
Bit 5;
Bit 6;
Bit 7;
•
FLAG
6
5
4
3
2
TS3
X
OSS
LATCH
X
o
X
PC21 PC1
I PCO 11/0 411/0311/0211/0 1 1110 0
I
X
mer.
ENABLE
$00031
ENABLE
Not used.
Not used.
Not used.
LATCH ENABLE. This controls the input latch for I/O
Port 3. If this bit is set "High" the input data will be
latched with the falling edge of the Input Strobe, IS3.
This bit is cleared by reset, and the latch is "re-opened"
with CPU read Port 3.
OSS. (Output Strobe Select) This bit will select if the
Output Strobe should be generated at ()S3 (SC 2 ) by a
write to I/O Port 3 or a read of I/O Port 3. When this bit
is cleared the strobe is generated by a read Port 3. When
this bit is set the strobe is generated by a write Port 3.
Not used.
IS3 IRQ, ENABLE. When set, interrupt will be enabled
whenever IS3 FLAG is set; when clear, interrupt is
inhibited. This bit is· cleared by RES.
IS3 FLAG. This is a read only status bit that is set by
the falling edge of the input strobe, IS3 (SC,). It is
cleared by a read of the Control/Status Register followed by a read or write of I/O Port 3. Reset will clear
this bit.
I/O Port 4
This is an 8-bit port that can be configured as I/O or as
address lines depending on the mode of operation. In order to
be read properly, the voltage on the input lines must be greater
than 2.0 V for a logic "I" and less than 0.8 V for a logic "0".
As outputs, each line is TTL compatible and can drive 1 TTL
An example of external hardware that could be used for
Mode Selection is shown in Fig. 14. The HDI40S3B provides
the isolation between the peripheral device and MCV during
Reset, which is necessary if data conflict can occur between
peripheral device and Mode generation circuit.
As bits 5, 6 and 7 of Port 2 are read only, the mode cannot
be changed through software. The mode selections are shown in
Table 3.
The HD6801S is capable of operating in three basic modes;
(I) Single Chip Mode, (2) Expanded Multiplexed Mode (compatible with HMCS6800 peripheral family) (3) Expanded NonMultiplexed Mode.
• Single Chip Mode
In the Single Chip Mode the Ports are configured for I/O.
This is shown in Figure 16 the single Chip Mode. In this
mode, Port 3 will have two associated control lines, an input
strobe and an output strobe for handshaking data.
• Expanded Non-Multiplexed Mode
In this mode the HD680 I S will directly address HMCS6800
peripherals with no external logic. In this mode Port 3 becomes
the data bus. Port 4 becomes the Ao""A, address bus or partial
address and I/O (inputs only). Port 2 can be parallel I/O, serial
I/O, Timer, or any combination of them. Port 1 is parallel 1/0
only. In this mode the HD6801S is expandable to 256 locations.
The eight address lines associated with Port 4 may be
substituted for 1/0 (inputs only) if a fewer number of address
lines will satisfy the application (See Figure 17).
eHITACHI
49
HD6801S0,HD6801S5--------------------------------------------------Vee
(
!
A
AI RI RI
6
1ABC
TT
HD6801S
X.
Y.
X
~ Z.
Y
XI
Z
AES
8
9
10
P20 (PCOI
P2I (PC11
p •• (PC21
YI
ZI
C
C
I
???
~
Mode
Control
Switch
HD14053B
Inh
11 Mode 7 as shown
21 AC"Aeset time constant
31 A I =10kn
[NOTES)
Jr
Figure 14 Recommended Circuit for Mode Selection
Truth Table
Control Input
On Switch
Inh
Binary to 1-of-2
Decoder with
Inhibit
A
B
C
Xoo-----------------~U-~~4-~
Xlcr------------------4C~+-~--~
yoo-------------------~~~~~
ylo---------------------~~~~
Zoo-----------------------~~~
Zlcr------------------------~~
Select
Inhibit
C
x
y
z
B A
HD14053B
0
0 0
0
Z. Yo XII
0
0 0
1
Zo Vo XI
0
0
1 0
Zo Y I Xo
0
0
1
1
ZO Y I XI
0
1 0
0
ZI Yo X.
0
1 0
1
ZI Vo 'XI
0
1
1
0
ZI Y I Xo
0
1
1
1
ZI VI XI
1
X X X
-
Figure 15 HD14053B Multiplexers/Demultiplexers
Vee
Vee
2
7
40
Enable
Enable
Port 1
Port 3
81/0 Lines
Port 1
8110 Lines
Port 4
Port 2
8110 Lines
5110 Lines
Vss
SCI
Timer
Figure 16 HD6801S MCU Single-Chip Mode
50
Port 3
8 Data Lines
8 Parallel 1/0
Port 2
5 Parallel 1/0
SCI
Timer
Vss
Port 4
To 8 Address
Lines or To
8110 Lines
(Inputs On IV)
Figure 17 HD6801S MCU Expanded Non-Multiplexed Mode
~HITACHI
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD680150,HD680155
•
Expanded Multiplexed Mode
Vee
In this mode Port 4 becomes higher order address lines with
an alternative of substituting some of the address lines for I/O
(inputs only). Port 3 is the data bus multiplexed with the lower
order address lines differentiated by an output called Address
Strobe. Port 2 is 5 lines of Parallel I/O, SCI, Timer, or any
combination of them. Port I is 8 Parallel I/O lines. In this mode
it is expandable to 65k words. (See Figure 18).
•
Enable
Lower order Address Bus Latches
Port 1
81/0 Lines
Since the data bus is multiplexed with the lower order
address bus in Port 3, latches are required to latch those address
bits. The 74LS373 Transparent octal D-type latch can be used
with the HD6801S to latch the least significant address byte.
Figure 19 shows how to connect the latch to the HD6801S.
The output control to the 74LS373 may be connected to
ground.
8 Lines
Multiplexed
Data/Address
Port 2
51/0 Lines
SCI
Timer
Port 4
To 8 Address
Lines or To
8 I/O Lines
(Inputs Only)
Vss
Figure 18 HD6801S MCU Expanded Multiplexed Mode
GNO
AS
I
G OC
0,
Port 3
Address/Data
[
0,
1
08
Function Table
Add,", A. -A,
74 LS373
Output
Control
08
1~~
L
L
L
H
Enable
G
0
Output
0
H
H
H
H
L
X
X
L
00
Z
L
X
0.-0,
Figure 19 Latch Connection
•
Mode and Port Summary MCU Signal Description
This section gives a description of the MCU signals for the various modes. SCI and
that the chip is in.
MODE
SINGLE CHIP
PORT 1
Eight Lines
I/O
PORT 2
Five Lines
S~
PORT3
Eight Lines
are signals which vary with the mode
PORT 4
Eight Lines
SCI
~
I/O
I/O
I/O
1S3 (I)
083(0)
ADDRESS BUS·
(As-A Is )
AS(O)
RAY(O)
ADDRESS BUS·
(Ao-A 7 )
10S(0)
RM(O)
EXPANDED MUX
I/O
I/O
ADDRESS BUS
(Ao-A7 )
DATA BUS
(0 0 -0 7 )
EXPANDED NON-MUX
I/O
I/O
DATA BUS
(0 0 -0 7 )
-These lines can be substituted for I/O (Input Only) starting with the most significant address line.
m .. Input Strobe
SC" Strobe Control
I - Input
o .. Output
~ .. Output Strobe
AS .. Address Strobe
R/W .. Read/Wriii
iOS .. I/O Select
_HITACHI
51
HD6801S0,HD6801S5---------------------------------------_______________
Table 3 Mode Selection Summary
Pa
(PC2)
PZ1
(PC1)
Pzn
(PCO)
ROM
RAM
7
6
H
H
H
I
I
I
H
H
L
I
I
I
I
MUX(6)
5
H
L
H
I
I
I
NMUX(6)
4
H
L
L
1(2)
1(1)
I
I
3
L
H
H
E
E
E
MUX
Multiplexed/No RAM & ROM
2
L
H
L
E
I
E
MUX
Multiplexed/RAM
1
L
L
H
I
I
E
MUX
Multiplexed/RAM & ROM
0
L
L
L
I
I
1(3)
MUX
Multiplexed Test
Mode
LEGEND:
I -Internal
E - External
MUX - Multiplexed
NMUX - Non-Multiplexed
L - Logic "0"
H - Logic "1"
Interrupt
Vectors
ing on the operating mode. A memory map for each operating
mode is shown in Figure 20. The rust 32 locations of each map
are reserved for the MCV's internal register area, as shown in
Table 4. With exceptions as indicated.
Register
Direction Register···
Direction Register···
Register
Register
Port
Port
Port
Port
3
4
3
4
Direction Register"·
Direction Register···
Register
Register
Data
Data
Data
Data
00
01
02
03
04·
05··
06·
07··
08
09
OA
OB
Output Compare Register (Low Byte)
Input Capture Register (High Byte)
Input Capture Register (Low Byte)
Port 3 Control and Status Register
OC
00
OE
OF·
Rate and Mode Control Register
Transmit/Receive Control and Status Register
Receive Data Register
Transmit Data Register
10
11
12
13
14
15-1F
• External address in Mode!..2. 1,2,3, 5,6; cannot be
accessed in Mode 5 (No. lOS)
•• External addresses in Modes 0, 1, 2, 3
••• 1=Output, O"Input·
52
Single Chip Test
The Interrupt flow chart is depicted in Figure 24 and is common to every interrupt excluding reset.
Address
Timer Control and Status Register
Counter (High Byte)
Counter (Low Byte)
Output Compare Register (High Byte)
RAM Control Register
Reserved
Multiplexed/Partial Decode
Non-Multiplexed/Partial Decode
• INTERRUPT FLOWCHART
Table 4 Internal Register Area
1 Data
2 Data
1 Data
2 Data
Operating
Mode
Single Chip
(NOTES)
1) Internal RAM is addressed at $XX80
2) Internal ROM is disabled
3) RES vector is external for 2 cycles after RES goes "High"
4) Addresses associated with Ports 3 and 4 are considered external in Modes 0,
1,2, and 3
5) Addresses associated with Port 3 are considered external in Modes 5 and 6
6) Port 4 default is user data input; address output is optional by writing to Port 4
Data Direction Register
• MEMORY MAPS
The MCV can provide up to 6Sk byte address space depend-
Port
Port
Port
Port
Bus
Mode
_HITACHI
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD6801S0,HD6801S5
HD6801S
Mode
o
$0000(1)
}
$0080
$OOFF
1
Multiplexed/RAM & ROM
Multiplexed Test mode
$0000(1)
$001F
HD6801S
Mode
Internal Registers
Internal Registers
$OOlF
}
I
External Memory Space
External Memory Space
$0080
Internal RAM
Internal RAM
$OOFF
External Memory Space
External Memory Space
$F8oo
$F8oo
Internal ROM
$FFEF
Internal ROM
$FFFF(2)
Internal Interrupt Vectors(2
[NOTES!
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and $OF
2) Addresses $FFFE and $FFFF are considered
external if accessed within 2 cycles alter a
positive edge of RES and internal at all other
times.
3) After 2 CPU cycles, there must be no overlapping of internal and external memory
spaces to avoid driving the data bus with more
than one device.
4) This mode is the only mode which may be used
to examine the interrupt vectors "in internal
ROM using an external Reset vector.
$FFFO
$FFFF '--_ _ _
External Interrupt Vectors
~J
[NOTES]
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and
$OF.
2) Internal ROM addresses $FFFO to $FFFF are
not usable.
Figure 20 HD6801S Memory Maps
eHITACHI
53
HD6801S0,HD6801S5-----------------------------------------------------
HD6801S
Mode
2
HD6801S
Mode
3
Multiplexed/No RAM or ROM
Multiplexed/RAM
$0000(1)
$0000(1)
} Internal Registers
Internal Registers
$001F
$001F
External Memory Space
$0080
Internal RAM
$OOFF
External Memory Space
External Memory Space
$FFFOa----,.;}
$FFFF ' - _ _ _ _ External Interrupt Vectors
[NOTE]
1) Excludes the following addresses which may
be used externally: $04, $Os, $06, $07, and
$OF.
$FFFO
External Interrupt Vectors
[NOTE]
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and
$OF.
Figure 20 HD6801S Memory Maps
54
~----I
$FFFF ' -_ _ _-' }
_HITACHI
(Continued)
. - - - - - - - - - - - - - HD6801S0,HD6801S5
HD6801S
Mode
4
Single Chip Test
HD6801S
Mode
5
Non-Multiplexed/Partial Decode
$0000(1)
$0000
Internal Registers
} Internal Registers
$OO1F
$001F
$0080
}
$OOFF
$0100
$01FF
U
L
_~_ _...
}
Internal RAM
External Memory Space
e(1)(4)
$F8oo
Internal ROM
$XX80
$XXFF
Internal RAM
} Internal Interrupt Vectors
[NOTES)
1) The internal ROM is disabled.
2) Mode 4 may be changed to Mode 5 without
having to assert RESET by writing a "1" into
the PCO bit of Port 2 Data Register.
31 Addresses As to A •• are treated as "don't
cares" to decode internal RAM.
4) Internal RAM will appear at $XX80 to $XXFF.
$FFFF
Internal Interrupt Vectors
[NOTES)
1) Excludes the following addresses which may
not be used externally: $04, $06, and $OF.
(No 105)
2) This mode may be entered without going
through RES by using Mode 4 and subsequently writing a "1" into the PCO bit of
Port 2 Data Register.
3) Address lines Ao -A. will not contain addresses until the Data Direction Register for Port 4
has been written with "1's" in the appropriate
bits. These address lines will assert "1's" until
made outputs by writing the Data Direction
Register.
Figure 20 HD6801S Memory Maps (Continued)
eHITACHI
55
HOS801 SO,H06801 55 - - - - -
HD6801S
Mode
6
HD6801S7
Mode
Single Chip
Multiplexed/Partial Decode
$0000(1)
Internal Registers
$001F
External Memory Space
$0080
$0080
Internal RAM
Internal RAM
$ooFF
$OOFF
External Memory Space
$F8oo
$F800
j
$FFFF
lnternal ROM
$FFFF
[NOTES]
11 Excludes the following address which may be
used externally: $04, $06, $OF.
21 Address lines A.-A .. will not contain
addresses until the Data Direction Register for
Port 4 has been written with "1's" in the
appropriate bits. These address lines will
assert "1's" until made outputs by writing the
"Data Direction Register.
Figure 20 HD6801S Memory Maps (Continued)
56
I
Internal ROM
Internal Interrupt Vectors
Internal Interrupt Vectors
$
HITACHI
. - - - - - - - - - - - - - H06801 SO,HOS801 S5
• PROGRAMMABLE TIMER
The H0680lS contains an on-chip 16-bit programmable
timer which may be used to perform measurements on an input
waveform while independently generating an output waveform.
Pulse widths for both input and output signals may vary from a
few microseconds to many seconds. The timer hardware consists
of
• an 8-bit control and status register,
• a 16-bit free running counter,
• a 16-bit output compare register, and
• a 16-bit input capture register
A block diagram of the timer registen is- shown in Figure 21.
•
Free Running Counter ($OOO9:000A)
The key elen:tent in the programmable timer is a 16-bit free
running counter which is driven to increasing values by E (Enable). The counter value may be read by the CPU software at
any time. The counter is cleared to zero on RES and may be
considered a read-only register with one exception. Any CPU
write to the counter's address ($09) will always result in preset
value of $FFF8 being loaded into the counter regardless of the
value involved in the -write. This preset figure is intended for
testing operation of the part, but may be of value in some
applications.
• Output Compare Register ($OOOB:OOOC)
The Output Compare Register is a 16-bit read/write register
which is used to control an output wavefonn. The contents of
this register are constantly compared with the current value of
the free running counter. When a match is found, a flag is set
(OCF) in the Timer Control and Status Register (TCSR) and the
current value of the Output Level bit (OLVL) in the TCSR is
clocked to the Output Level Register. Providing the Data
Direction Register for Port 2, Bit 1 contains a "I" (Output),
the output level register value will appear on the pin for Port 2
Bit I. The values in the Output Compare Register and Output
level bit may then be changed to control the output level on the
next compare value. The Output Compare Register is set to
$FFFF during RES. The Compare function is inhibited for
one cycle following a write to the high byte of the Output
Compare Register to insure a valid 16-bit value is in the register
before a compare is made.
•
Input Capture Register ($OOOO:OOOE)
The Input Capture Register is a 16-bit read-only register used
to store the current value of the free running counter when the
proper transition of an external input signal occurs. The input
transition change required to trigger the counter transfer is
controlled by the input Edge bit (IEDG) in the TCSR. The Data
Direction Register bit for Port 2 Bit 0, should· be clear (zero)
in order to gate in the external input signal to the edge detect
unit in the timer.
* With Port 2 Bit 0 conIJgured as an output and set to "1". the
external input will still be seen by the edge detect unit.
•
Timer Control and Status Register (TCSR) ($0008)
The Timer Control and Status Register consists of an 8-bit
register of which all 8 bits are readable but only the low order 5
bits may be written. The upper three bits contain read-only
timer status information and indicate that:
• a proper transition has taken place on the input pin with a
subsequent transfer of the current counter value to the
input capture register.
• a match has been found between the value in the free
running counter and the output compare register, and
• when $0000 is in the free running counter.
Each of the flags' may be enabled onto the H06801 internal
bus (IRQ2) with an individual Enable bit in the TCSR. If the
HD6801S Internal Bus
Output I"pu t
Level
Edge
Figure 21
Bit 1
Sit 0
Port 2
Port 2
Block Diagram of Programable Timer
_HITACHI
57
HD6801S0,HD6801S5 - - - - Timer Control and Status Register
ICF
I
5
6
OCF
4
3
2
1
TOF I EICI I EOCI I ETOIIIEDG
I-bit in the HD6801S Condition Code Register has been cleared,
a priority vectored interrupt will occur corresponding to the flag
bit(s) set. A description for each bit follows:
Bit 0 OLVL Output Level - This value is clocked to the output
level register on a successful output compare. If
the DDR for Port 2 bit 1 is set, the value will
appear on the output pin.
Bit I IEDG Input Edge - This bit controls which transition of
an input will trigger a transfer of the counter to
the input capture register. The DDR for Port 2 Bit
o must be cle;l( for this function to operate. IEDG
= 0 Transfer takes place on a negative edge
("High" ·to-"Low" transition).
IEDG = I Transfer takes place on a positive edge
("Low"-to-"High" transition).
Bit 2 ETOI Enable Timer Overflow Interrupt - When set, ti1is
bit enables IRQ2 to occur on the internal bus for a
TOF interrupt; when clear the interrupt is inhibited.
Bit 3 EOCI Enable Output Compare Interrupt - When set,
this bit enables IRQ2 to appear on the internal bus
for an output compare interrupt; when clear the
interrupt is inhibited.
Bit 4 EICI Enable Input Capture Interrupt- When set, this
bit enables IRQ2 to occur on the internal bus for
. an input capture interrupt; when clear the interrupt is inhibited.
Bit 5 TOF Timer Overflow Flag - This read-only bit is set
when the counter contains $FFFF. It is cleared by
a read of the TCSR (with TOE set) followed by an
CPU read of the Counter ($09).
Bit 6 OCF Output Compare Flag - This read-only bit is set
when a match is found between the output
compare register and the free running counter. It is
cleared by a read of the TCSR (with OCF set)
followed by an CPU write to the output compare
register ($OB or SOC).
Bit 7 ICF Input Capture Flag - This read-only status bit is
set by a proper transition on the input; it is cleared
by a read of the TCSR (with ICF set) followed by
an CPU read of the Input Capture Register ($OD).
• SERIAL COMMUNICATIONS INTERFACE
The H06801S contains a full-duplex asynchronous serial
communications interface (SCI) on chip. The controller
comprises a transmitter and a receiver which operate independently or each other but in the same data format and at the same
data rate. Both transmitter and receiver communicate with the
I
0
OLVLI $0008
CPU via the data bus and with the outside world via pins 2, 3,
and 4 of Port 2. The hardware, software, and registers are explained in the following paragraphs.
• Wake-Up Feature
In a typical multi-processor application, the software
protocol will usually contain a destination address in the initial
byte(s) of the message. In order to permit non-selected MCU's
to ignore the remainder of the message, a wake-up feature is
included whereby all further interrupt processing may be
optionally inhibited until the beginning of the next message.
When the next message appears, the hardware re-enables (or
"wakes-up") the for the next message. The "wake-up" is
automatically triggered by a string of ten consecutive 1's which
indicates an idle transmit line. The software protocol must
provide for the short idle period between any two consecutive
messages.
• Programmable Options
The following features of the HD6801 S serial I/O section are
programmable:
· format - standard mark/space (NRZ)
• Clock - external or internal
• baud rate- one of 4 per given CPU tP2 clock frequency or
external clock x8 input
• wake-up feature - enabled or disabled
• Interrupt requests - enabled or masked individually for
transmitter and receiver data registers
• clock output - internal clock enabled or disabled to Port
2 (Bit 2)
• Port 2 (bits 3 and 4) - dedicated or not dedicated to serial
I/O individually for transmitter and receiver.
• Serial Communications Hardware
The serial conununications hardware is controlled by 4
registers as shown in Figure 22. The registers include:
• an 8-bit control and status register
• a 4-bit rate and mode control register (write only)
• an 8-bit read only receive data register and
• an 8-bit write only transmit data register.
In addi"tion to the four registers, the serial I/O section utilizes
bit 3 (serial input) and bit 4 (serial output) of Port 2. Bit 2 of
Port 2 is utilized if the internal-clock-out or external-clock-in
options are selected .
Transmit/Receive Control and Status (TRCS) Register
The TRCS register consists of an 8-bit register of which all 8
bits may be read while only bits 0-4 may be written. The
register is initialized to $20 on RES. The bits in the TRCS
register are defined as follows:
Transmit/Receive Control and Status Register
76543210
IRDREloRFEITDREI RIE I RE
58
I TIE I
eHITACHI
TE
I
wu
IADDR:SO011
--------------------------HD6801S0,HD6801S5
Bit 7
Rate and Mode Control Register
I
I I I I
CCI
CCO
SSI
Bit 0
SSO
ISlo
Transmit/Receive Control and Status Register
Port 2
Receive Shift Register
Clock
10
Bit ....----'~------~
2
Tx
Bit
I+----E
12
4
Figure 22 Serial I/O Registers
writing a new byte into the transmit data register,
TDRE is initialized to 1 by RES.
Bit 6 ORFE Over-Run-Framing Error - set by hardware when
an overrun or framing error occurs (receive only).
An overrun is defined as a new byte received with
last byte still in Data Register/Buffer. A !raming
error has occurred when the byte boundaries in bit
stream are not synchronized to bit counter. The
ORFE bit is cleared by reading the status register,
then reading the Receive Data Register, or by
RES.
Bit 7 RORF Receiver Data Register Fun - Set by hardware
when a transfer from the input shift register to the
receiver data register is made. The RDRF bit is
cleared by reading the status register, then reading
the Receive Data Register, or by RES.
BitOWU
"Wake-up" on Next Message - set by HD6801S
software and cleared by hardware on receipt of
ten consecutive 1's or reset of RE flag. It should
be noted that RE flag should be set in advance of
CPU set of WU flag.
Bit 1 TE
Transmit Enable - set by HD6801 S to produce
pre am ble of nine consecutive 1's and to enable
gating of transmitter output to Port 2, bit 4
regardless of the DDR value corresponding to this
bit; when clear, serial I/O has no effect on Port 2
bit 4.
TE set should be after at least one bit time of data
transmit rate from the set-up of transmit data
rate and mode.
Bit 2 TIE
Transmit Interrupt Enable - when set, will permit
an IRQ2 interrupt to occur when bit 5 (TDRE) is
set; when clear, the TDRE value is masked from
the bus.
Receiver Enable - when set, gates Port 2 bit 3 to
Bit 3 RE
input of receiver regardless of DDR value for this
bit; when clear, serial I/O has no effect on Port 2
bit 3.
Receiver Interrupt Enable - when set, will permit
Bit 4 RIE
an IRQ 2 interrupt to occur when bit 7 (RDRF) or
bit 6 (ORFE) is set; when clear, the interrupt is
masked.
Bit 5 TORE Transmit Data Register Empty - set by hardware
when a transfer is made from the transmit data
register to the output shift register. The TDRE bit
is cleared by reading the status register, then
Rate and Mode Control Register
The Rate and Mode Control register controls the following
serial I/O variables:
• Baud rate
• format
• clocking source, and
• Port 2 bit 2 configuration
The register consists of 4 bits all of which are write-only and
cleared on RES. The 4 bits in the register may be considered as
a pair of 2-bit fields. The two low order bits control the bit rate
for internal clocking and the remaining two bits control the
format and clock select logic. The register definition is as
follows:
Rate and Mode Control Register
7
6
5
4
x
x
x
x
3
2
I eel I eeo I S51
~HITACHI
o
sso
ADDR: $0010
59
HD6801S0,HD6801S5----------------------------------------------------Bit 0 SSO
Bit 1 SS1
Speed Select - These bits select the Baud rate for
the internal clock. The four rates which may be
selected are a function of the CPU f/>2 clock
frequency. Table 5 lists the available Baud rates.
Bit 2 CCO
Bit 3 CC1
Clock Control and Format Select - this 2-bit field
controls the format and clock select logic. Table 6
defines the bit field.
Table 5 SCI Bit Times and Rates
XTAL
2.4576 MHz
4.0 MHz
4.9152 MHz*
E
614.4 kHz
1.0 MHz
1.2288 MHz
E+ 16
E + 128
E + 1024
E + 4096
26 #5/38,400 Baud
208 #5/4,800 Baud
1.67 ms/600 Baud
16 #5/62,500 Baud
128 #5/7812.5 Baud
1.024 ms/976.6 Baud
13 #5/76,800 Baud
104.2 #s/9,600 Baud
6.67 ms/150 Baud
4.096 ms/244.1 Baud
SS1 : SSO
0
0
1
1
0
1
0
1
833.3 #5/1,200 Baud
3.33 ms/300 Baud
* HD6801S5 Only
Table 6 SCI Format and Clock Source Control
CC1:CCO
0
0
1
1
*
0
1
0
1
Clock Source
Port 2 Bit 2
Port 2 Bit 3
Port 2 Bit 4
-
-
-
NRZ
NRZ
NRZ
Internal
Internal
External
Not Used
Output*
Input
**
**
**
**
**
**
Format
Clock output is available regardless of values for bits RE and TE.
Bit 3 is used for serial input if RE = "1" in TRCS; bit 4 is used for serial output if TE = "1" in TRCS.
Internally Generated Clock
If the user wishes for the serial I/O to furnish a clock, the
following requirements are applicable:
• the values of RE and TE are immaterial.
• Cel, CCO must be set to 10
• the maximum clock rate will be E + 16.
• the clock will be at Ix the bit rate and will have a rising
edge at mid-bit.
Externally Generated Clock
If the user wishes to provide an external clock for the serial
I/O, the following requirements are applicable:
• the CCI, CCO, field in the Rate and Mode Control Register
must be set to II,
• the external clock must be set to 8 times (x8) the desired
baud rate and
• the maximum external clock frequency is .I.O MHz.
• Serial Operations
The serial I/O hardware should be initialized by the
HD6801S software prior to operation. This sequence will
normally consist of;
• writing the desired operation control bits to the Rate and
Mode Control Register and
• writing the desired operational control bits in the Transmit!
Receive Control and Status Register.
The Transmitter Enable (TE) and Receiver Enable (RE) bits
may be left set for dedicated operations.
60
**
**
Transmit Operations
The transmit operation is enabled by the TE bit in the
Transmit/Receive Control and Status Register. This bit when
set, gates the output of the serial transmit shift register to Port 2
Bit 4 and takes unconditional control over the Data Direction
Register value for Port 2, Bit 4.
Following a RES the user should configure both the Rate
and Mode Control Register and the Transmit/Receive Control
and Status Register for desired operation. Setting the TE bit
during this procedure initiates the serial output by first
transmitting a nine-bit preamble of 1'so Following the preamble,
internal synchronization is established and the transmitter
section is ready for operation.
At this point one of two situation exist:
1) if the Transmit Data Register is empty (TORE = 1), a
continuous string of ones will be sent indicating an idle
line, or,
2) if data has been loaded into the Transmit Data Register
(TORE = 0), the word is transferred to the output shift
register and transmission of the data word will begin.
During the transfer itself, the 0 start bit is first transmitted.
Then the 8 data bits (beginning with bit 0) followed by the stop
bit, are transmitted. When the Transmitter Data Register has
been emptied, the hardware sets the TORE flag bit.
If the HD6801S fails to respond to the flag within the proper
time, (TORE is still set when the next normal transfer from th~
parallel data register to the serial output register should occur)
then a I will be sent (instead of a 0) at "Start" bit time,
followed by more 1's until more data is supplied to the data
register. No O's will be sent while TORE remains a 1.
eHITACHI
------------------------------------------------------HD6801S0,HD6801S5
• Condition code register manipulation instructions - Table 10
• Instructions Execution times in machine cycles - Table
Receive Operation
The receive operation is enabled by the RE bit which gates in
the serial input through Port 2 Bit 3. The receiver section
operation is conditioned by the contents of the Transmit/
Receive Control and Status Register and the Rate and Mode
Control Register.
The receiver bit interval is divided into 8 sub-intervals for
internal synchronization. In the NRZ Mode, the received bit
stream is synchronized by the first 0 (space) encountered.
The approximate center of each bit time is strobed during
the next 10 bits. If the tenth bit is not a I (stop bit) a framing
error is assumed, and bit ORFE is set. If the tenth bit as a I, the
data is transferred to the Receive Data Register, and interrupt
flag RDRF is set.·If RDRF is still set at the next tenth bit time,
ORFE will be set, indicating an over-run has occurred. When the
HD6801S responds to either flag (RDRF or ORFE) by reading
the status register followed by reading the Data Register, RDRF
(or ORFE) will be cleared.
II
• Summary of cycle by cycle operation - Table 12
• Op codes Map - Table 13
• CPU Programming Model
The programming model for the HD6801S is shown in Figure
23. The double (D) accumulator is physically the same as the
Accumulator A concatenated with the Accumulator B so that
any operation using accumulator D will destroy information in
A and B.
8·81t Accumulators A and B
Or 16-Blt Double Accumulator 0
115
X
0
1 Index Register IX)
115
SP
0
1 Stack POinter ISP)
115
PC
ol
• RAM CONTROL REGISTER
This register, which is addressed at $0014, gives status
information about the standby RAM. A 0 in the RAM enable
bit (RAM E) will disable the standby RAM, thereby protecting
it at power down if Vee Standby is held greater than VSBB
volts, as explained previously in the signal description for Vee
Standby.
$00141 s~
I
Condition Code Register ICCR)
Carry/Borrow from MSB
RAM Control Register
RAM.
1X
I I I I II
X
X
X
X
Overflow
Zero
Negative
Interrupt
Half Carry IFrom Bit 3)
X
Bit 0 Not used.
Bit 1 Not used.
Bit 2 Not used.
Bit 3 Not used.
Bit 4 Not used.
Bit 5 Not used.
Bit 6 RAME The RAM Enable control bit allows the user the
ability to disable the standby RAM. This bit is set
to a logic "1" by RES which enables the standby
RAM and can be written to one or zero uner program control. When the RAM is disabled, data is
read from external memory.
Big 7 STBY The Standby Power bit is cleared when the standPWR by voltage is removed. This bit is a read/write status flag that the user can read which indicates that
the standby RAM voltage has been applied, and
the data in the standby RAM is valid.
• GENERAL DESCRIPTION OF INSTRUCTION SET
The HD6801S is upward object code compatible with the
HD6800 as it implements the full HMCS6800 instruction set.
The execution times of key instructions have been reduced to
increase throughout. In addition, new instructions have been
added; these include 16-bit operations and a hardware multiply.
Included in the instruction set section are the following:
• CPU Programming Model (Figure 23)
• AddreSsing modes
• Accumulator and memory instructions - Table 7
• New instructions
• Index register and stack manipulations instructions - Table
8
• Jump and branch instructions - Table 9
Program Counter IPC)
Figure 23 CPU Programming Model.
•
CPU Addressing Modes
The HD6801S eight-bit microcomputer unit has seven
address modes that can be used by a programmer, with the
addressing mode a function of both the type of instruction and
the coding within the instruction. A summary of the addressing
modes for a particular instruction can be found in Table 11
along with the associated instruction execution time that is
given in machine cycles. With a clock frequency of 4 MHz, these
times would be microseconds.
Accumulator (ACCX) Addressing
In accumulator only addressing, either accumulator A or
accumulator B is specified. These are one-byte instructions.
Immediate Addressing
In immediate addressing, the operand is contained in the
second byte of the instruction except LDS and LDX which have
the operand in the second and third bytes of the instruction.
The CPU addresses this location when it fetches the immediate
instruction for execution. These are two or three-byte instructions.
_HITACHI
61
HD6801S0,HD6801S5--------------------------------------------------Table 7 Accumulator & Memory Instructions
Condition Code
Addressing Modes
Operations
Mnemonic
IMMED.
#
OP
3
2
AB 4 2 BB
DB 3
2
EB
4
2
FB
5
2
f3
6
2
F3
-
8B
2 2 9B
ADDB
CB
2 2
Add Double
ADDD
C3
4
Add Accumulators
ABA
Add With Carry
AND
Bit Test
Clear
#
3
-
-
OP
ADDA
Add
OP
03
Register
EXTEND
INDEX
DIRECT
#
OP
#
4
3
A+B-.A
4· 3
6 3
B+M-.B
4
4
2 B9
4
3
2
F9
4
3
A4
4
2
B4
4
3
E4
4
2
F4
4
3
4
2
B5
4
3
4
2
F5
4
3
2
7F
6
3
2 2
2 2 99
09
3
2
A9
E9
2 2 94
2 2 04
3
2
C4
3
2
BITA
85
2 2 95
3 2
A5
BIT B
C5
2 2 05
3
E5
6F
6
ADCA
89
ANDA
C9
84
AN DB
3 2
2
CLR
CLRB
Compare
Accumulators
Complement, 1's
CMPA
81
2 2 91
CMPB
C1
2 2
01
3 2
3 ,2
A1
4
2
B1
4
3
E1
4
2
F1
4
3
63
COM
COMA
6
2 73
6
Decimal Adjust, A
Decrement
NEG
60
6
2 70
6
Load
Accumulator
2
1
2
1
43
2
1
53
2
1
1
2
1
DAA
19
2
1
4A
2
1
5A
2
1
6A
DEC
6
2 7A
6
3
EORA
88
2 2 98
3
2
AS
EORB
C8
2 2
3
2
E8 4
6C 6
08
INC
4
B8
4
3
2 F8
2 7C
4
3
6
3
2
INCA
4C
2
1
INCB
5C
2
1
2 2 96
2
Load Double
Accumulator
LDD
CC
3 3
Multiply Unsigned
MUL
OR,lnclusive
ORAA
8A
ORAB
CA 2 2
3
2 06 3
DC 4
2 A6 4 2 B6
2 E6 4 2 F6
4
3
4
3
FC
5
3
2
EC 5
2
3D 10 1
2 2 9A 3
DA 3
2
AA 4
2
EA 4
2 BA 4
2 FA 4
3
3
PSHA
36
3
1
PSHB
37
1
PULA
32
3
4
~ULB
33
4
1
49
2
1
59
2
1
ROL
69
6
2 79
6
ROLB
ROR
66
6
2
76
6
1
3
ROLA
3
RORA
RORB
..
The Condition Code Register notes are hsted atter Table 10.
62
5F
2
C6
Rotate Right
1
40
86
Rotate Left
2
50
LDAA
Pull Data
4F
NEGA
NEGB
LDAB
Push Data
1
3
DECB
Incrament
2
3
DECA
Exclusive OR
#
5 4
46
2
1
56
2
1
2
1 0
I N Z V C
t
t
•
•
• •
t •
A+M+C-'A
t •
B+M+C-'B
t •
A·M-.A
• •
B·M-. B
• •
A·M
• •
B·M
• •
00-. M
• •
OO-A
• •
00 -. B
• •
A-M
• •
B-M
• •
A-B
• •
M-.M
• •
A -.A
• •
B -.B
• •
OO-M-'M
• •
OO-A-.A
• •
oo-B-.B
• •
Converts binary add of BCb
• •
characters. into BCD format
M-1-'M
• •
A-1-'A
• •
B-1-'B
• •
A@ M-. A
• •
B @ M-. B
• •
M+1-.M
• •
A+1-.A
• •
B + 1--+ B
• •
M--+A
• •
M-.B
• •
M + 1 -. B. M -. A
• •
AxB-.A:B
• •
A + M-' A
• •
B + M-. B
• •
A -. Msp, SP - 1 -. SP
• •
B -. Msp, SP - 1 -. SP
• •
SP+1-SP,Msp-.A
•
SP + 1 --+ SP, Msp -. B
• •
• •
:}~IIIIII liJ
•
•
bO
• •
• •
• •
bO
:J~b) I I I I I I~
• •
A + B-. A
·
B b7
3
H
A:B+M:M+1-.A:B
11
CBA
COMB
Complement, 2's
(Negate)
OP -
1B
ADCB
Boolean/
Arithmetic Operation
-
CLRA
Compare
IMPLIED
t
t
t
t
t
t
t
t
: t
t t
t t
: :
: t
: t
t
t
:
t :
R
R
R
R
•
•
•
•
R S R R
S R R
R
S R R
R
: t t t
t t t t
t t t t
t t R S
t
t
t
t
t
t
t
t
t
t
R S
R S
the double precision ACCD· to 1•. double precision value M:M+I and places
the results in ACCD.
ASLD Shifts all bits of ACCD one place to the left. Bit 0 is loaded with zero. The C bit is
loaded from the most significant bit of ACCD.
LDD
Loads the contents of double precision memory location into the double
accumulator A:B. The condition codes are set according to the data.
LSRD Shifts ail bits of ACCD one place to the right. Bit 15 is loaded with zero. The C bit
is loaded from the least significant bit to ACCD.
MUL
Multiplies the 8 bits in accumulator A with the 8 bits in accumulator B to obtain a
l6-bit unsigned number in A:B, ACCA contains MSB of result.
PSHX The contents of the index register is pushed onto the stack at the address contained
in the stack pointer. The stack pointer is decremented by 2.
PULX The index register is pulled from the stack' beginning at the current address
contained in the stack pointer +1. The stack pointer is incremented by 2 in total.
STD
Stores the contents pf double accumulator A:B in memory. The contents of ACCD
remain unchanged.
S~BD Subtracts the contents of M:M + 1 from the contents of double accumulator AB
and places the result in ACCD.
BRN
Never branches. If effect, this instruction can be considered a two byte NOP (No
operation) requiring three cycles for execution.
CPX
Internal processing modified to permit its use with any conditional branch in·
struction.
-ACCD is the 16 bit register (A:B) formed by concatenating the A and 8 accumulators. The A-accumulator is the most significant byte.
Table 8 Index Register and Stack Manipulation Instructions
Addressing Modes
Pointer Operations
Mnemonic
IMMED.
OP
Compare Index Reg
CPX
Decrement Index Reg
DEX
Decrement Stack Pntr
Increment Index Reg
8C
-
DIRECT
-
#
# OP
4 3 9C 5 2
INDEX
OP
-
AC 6
IMPLIED
EXTND
# OP
# OP
#
2 BC 6 3
-
-
Booleanl
Arithmetic Operation
X-M: M+ 1
3
1 X-1-X
DES
34
3
1 SP - 1 - SP
INX
08
3
1 X+1-X
Increment Stack Pntr
INS
31
3
1 SP + 1 - SP
Load Index Reg
LOX
CE
3 3
LOid Stack Pntr
LOS
8E
3 3
Store Index Reg
STX
Store Stack Pntr
STS
2
2
OF 4 2
9F 4 2
DE 4
4
2
2
EF 5 2
AF 5 2
5
FE
5
3
M- XH. (M+ 1)- XL
AE 5
BE
5
3
M- SPH. (M+1)-SP L
FF
5
3
BF
5
3
EE
XH - M. XL .... (M + 1)
Index Reg -+ Stack Pntr
TXS
35
3
SP H .... M.SP L - (M+1)
1 X-1-SP
Stack Pntr -+ Index Reg
TSX
30
3
1 SP+1-X
Add
ABX
3A
Push Data
PSHX
3C
3
4
Pull Data
PULX
38
5
1 B+X-X
1 XL - Map. SP - 1 - SP
XH .... Map. SP -1 - SP
1 SP + 1- SP. Map - XH
SP + 1- SP. Map - XL
The Condition Code Register notes are listed after Table 10.
64
$
HITACHI
3 2 1 0
I N Z V C
5 4
H
09
9E
Condition Code
Register
• • t J t J
• • • J • •
• • • • • •
• • • J • •
• • • • • •
• • 'j) J R •
• • (f) J R •
•
•
•
•
•
•
•
•
• • •
• • •
• • •
• • •
• (f) J
R
• (j) J R
• •
• •
••
• •
• • • • • •
------------------------------------------------------HD6801S0,HD6801S5
Table 9 Jump and Branch Instructions
Condition Code
Register
Addressing Modes
Operations
Branch Always
Branch Never
Branch If Carry Clear
Branch If Carry Set
Branch If • Zero
Branch If .. Zero
Mnemonic
BRA
BRN
BCC
BCS
BEQ
INDEX
EXTND
RELATIVE DIRECT
OP
#
# OP
# OP
# OP
20 3 2
21 3 2
-
24
25
27
2C
2E
Branch If > Zero
Branch If Higher
BGE
BGT
BHI
Branch If < ZerO
BlE
22
2F
Branch If lower Or
Slme
BlS
Branch If < Zero
Branch If Minus
Branch If Not Equal
Zero
Branch If Overflow
Clear
Branch If Overflow Set
Branch If Plus
3
3
-
-
-
--
Branch Test
IMPLIED
OP
#
-
•
•
•
•
None
None
C=O
C=1
2=1
2
2
3 2
3 2
3 2
3 2
0
3
2
2 + IN
23
3
2
C+Z = 1
BlT
BMI
20
2B
3 2
3 2
N <±l V= 1
N=1
BNE
26
3 2
Z=O
BVC
28
3 2
v=o
BVS
BPl
3 2
3 2
80 6 2
V=1
Branch To Subroutine
BSR
Jump
JMP
Jump To Subroutine
JSR
·••
N<±>V=O
2 + IN 0 V) = 0
C+Z=O
29
2A
V) = 1
N=O
6E
90
5
2
3 2 7E 3 3
BD 6 3
AD 6 2
1
No Operation
NOP
01
Return From Interrupt
Retum From
Subroutine
Software Interrupt
RTI
3B 10 1
RTS
39
SWI
Wait for Interrupt
WAI
3F 12 1
3E 9 1
2
5
Advances Prog. Cntr.
Only
3 2 1 0
I N 2 V C
4
5
H
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • •
• • • •
• • • •
·
-@-
• • • • • •
• S • • • •
• ®. • • •
1
Table10 Condition Code Register Manipulation Instructions
iAddressingModes
Operation.
Mnemonic
OP
Clear Carry
Clear Interrupt MI.k
.Clear Overflow
Set Carry
Set Interrupt Mask
Set Overflow
AccumuletOr A - CCR
CCR - Accumulator A
ClC
Cll
CLV
OC
OE
OA
SEC
SEI
OK?
OF
SEV
TAP
TPA
06
OB
07
2
2
2
2
2
2
2
2
Condition Code Register
Boolean Operation
IMPLIED
#
1
1
1
1
1
1
1
1
O~C
0-+1
0"" V
1-+C
1-+1
,~V
CCR
CCR -+ A
A~
5
4
H
I
•
•
•
•
•
•
3
N
2
Z
• •
R
•
• •
• •
S
•
• •
•
•
•
•
•
•
1
0
V
C
• R
• •
R
•
•
S
• •
S
•
---@)---
• • • • • •
Condition Code Register Notes: (Bit set it test is true and cleared otherwise)
CD (Bit V)
@
@
@
@
@
Bus
IMMEDIATE
2
1
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Operand Data
LDS
LDX
LDD
3
1
2
3
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
CPX
SUBD
ADDD
4
1
2
3
4
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address Bus F F F F
1
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
3
1
2
3
Op Code Address
Op Code Address + 1
Address of Operand
1
1
1
Op Code
Address of Operand
Operand Data
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
DIRECT
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
STA
3
1
2
3
Op Code Address
Op Code Address + 1
Destination Address
1
1
0
Op Code
Destination Address
Data from Accumulator
LDS
LDX
LDD
4
1
2
3
4
Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
STS
STX
STD
4
1
2
3
4
Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand + 1
1
1
0
0
Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)
CPX
SUBD
ADDD
5
1
2
3
4
5
Op Code Address
Op Code Address + 1
Operand Address
Operand Address + 1
Address Bus FFFF
1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
JSR
5
1
2
3
4
5
Op Code Address
Op Code Address + 1
Subroutine Address
Stack Pointer
Stack Pointer + 1
1
1
1
0
0
Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
(Continued)
$
HITACHI
67
HD6801S0,HD6801S5----------------------------------------------------Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
Data Bus
INDEXED
3
JMP
1
2
3
ADC
ADD
AND
BIT
CMP
EOR
lOA
ORA
SBC
SUB
4
4
STA
1
2
3
4
1
2
3
4
LOS
LOX
LDD
5
STS
STX
STD
5
ASl
ASR
ClR
COM
DEC
INC
1
2
3
4
5
1
2
3
4
5
lSR
NEG
ROl
ROR
TST*
6
1
2
3
4
5
6
CPX
SUBD
ADDD
6
JSR
6
1
2
3
4
5
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
OpCode
Offset
low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
1
1
1
1
Op Code
Offset
low Byte of Restart Vector
Operand Data
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
1
1
1
0
Op Code
Offset
low Byte of Restart Vector
Operand Data
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
1
1
Op Code
Offset
low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (low Order Byte)
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
Op Code
Offset
low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (low Order Byte)
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
Address Bus F F F F
Index Register Plus Offset
0
Op Code
Offset
low Byte of Restart Vector
Current Operand Data
low Byte of Restart Vector
New Operand Data
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register + Offset
Index Register +,Dffset + 1
Address Bus F F F F
1
1
1
1
1
1
Op Code
Offset
low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (low Order Byte)
low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register + Offset
Stack Pointer
Stack Pointer - 1
1
1
1
1
Op Code
Offset
low Byte of Restart Vector
First Subroutine Op Code
Return Address (low Order Byte)
Return Address (High Order Byte)
*In the TST instruction, R/W line of the sixth cycle is "1"level, and AB
68
0
0
1
1
1
1
1
0
0
= FFFF, DB = low Byte of Reset
_HITACHI
Vector.
(Continued)
------------------------------------------------------HD6801S0,HD6801S5
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
Data Bus
EXTENDED
3
JMP
1
2
3
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
4
3
4
4
STA
1
2
1
2
3
4
LOS
LOX
LDD
5
STS
STX
STD
5
ASL
ASR
CLR
COM
DEC
INC
1
2
3
4
5
1
2
3
4
5
LSR
NEG
ROL
ROR
TST*
6
1
2
3
4
5
6
CPX
SUBD
ADDD
6
JSR
6
1
2
3
4
5
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
1
1
1
1
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
I
Op Code
Op Code
Op Code
Operand
Address
Address + 1
Address + 2
Destination Address
1
1
1
iOperand Data
lOp Code
I Destination
0
Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
1
1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)
I
0
0
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address Bus F F F F
Address of Operand
0
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Address
Operand Address + 1
Address Bus F F F F
1
1
1
1
1
1
Op Code
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
1
1
1
1
0
0
Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
1
1
1
1
1
"In the TST instruction, R/IN line of the sixth cycle is"1" level, and AB=FFFF, DB=Low Byte of Reset Vector,
eHITACHI
(Continued)
69
HD6801S0,HD6801S5--------~-------------------------------------------
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
Data Bus
IMPLIED
2
1
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Op Code of Next Instruction
3
1
2
3
1
1
1
Op Code
Irrelevant Data
low Byte of Restart Vector
ASlD
lSRD
3
DES
INS
3
INX
DEX
3
PSHA.
PSHB
3
TSX
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
Op Code Address
Op Code Address + 1
Address Bus F F F F
Op Code Address
Op Code Address + 1
Address Bus FFFF
Op Code Address
Op Code Address + 1
Previous Register Contents
Op Code Address
Op Code Address + 1
Address Bus F F F F
Op Code Address
Op Code Address + 1
Stack Pointer
Op Code Address
Op Code Address + 1
Stack Pointer
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
Op Code
Irrelevant Data
low Byte of Restart Vector
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code
Op Code of Next Instruction
low Byte of Restart Vector
Op Code
Op Code of Next Instruction
Accumulator Data
Op Code
Op Code of Next Instruction
Irrelevant Data
TXS
3
1
2
3
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Op Code of Next Instruction
low Byte of Restart Vector
PULA
PUlB
4
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
PSHX
4
1
2
3
4
5
RTS
5
1
2
3
4
5
1
2
3
4
1
1
0
0
1
1
1
1
1
1
1
1
1
Op Code
Irrelevant Data
Index Register (low Order Byte)
Index Register (High Order Byte)
PUlX
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer +2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
5
Stack Pointer + 2
1
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
0
0
ABA
ASl
ASR
CBA
ClC
Cli
ClR
ClV
COM
ABX
DAA
DEC
INC
lSR
NEG
NOP
ROl
ROR
SBA
WAI**
SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST
9
Op Code
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (low Order Byte)
OpCode
Irrelevant Data
Irrelevant Data
Address of Next Instruction
(High Order Byte)
Address of Next Instruction
(low Order Byte)
Op Code
Op Code of Next Instruction
Return Address (low Order Byte)
Return Address (H igh Order Byte)
(Contmued)
70
eHITACHI
------------------------------------------------------HD6801S0,HD6801S5
Table 12 Cvcle by Cycle Opeiation (Continued)
Address Mode &
Instructions
WAin
Cycle~
Cycle
#
5
6
7
8
9
MUL
10
1
2
.3
4
5
6
7
8
9
RTI
SWI
10
12
10
1
2
3
4
Address Bus
Stack
Stack
Stack
Stack
Stack
Pointer
Pointer
Pointer
Pointer
Pointer
-
2
3
4
5
6
Op Code Address
Op Code Address + 1
Address Bus FFFF
Address Bus F F F F
Address Bus F F FF
Address Bus F F F F
Address Bus F F F F
Address Bus F F FF
Address Bus FFFF
Address Bus F F F F
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
R/W
Line
0
0
0
0
0
1
1
1
11
1
1
1
1
1
1
1
1
1
1
5
Stack Pointer + 2
1
6
Stack Pointer + 3
1
7
Stack Pointer + 4
1
8
Stack Pointer + 5
1
9
Stack Pointer + 6
1
10
Stack Pointer + 7
1
10
11
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Stack Pointer - 7
Vector Address FFFA (Hex)
1
1
0
0
0
0
0
0
0
1
1
12
Vector Address FFF8 (Hex)
1
1
2
3
4
5
6
7
8
9
Data Bus
Index Register (low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Op Code
Irrelevant Data
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Op Code
Irrelevant Data
Irrelevant Data
Contents of Cond. Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from
Stack (High Order Byte)
Next Instruction Address from
Stack (Low Order Byte)
Op Code
Irrelevant Data
Return Address (low Order Byte)
Return Address (High Order Byte)
Index·Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)
"While the MCU is in th. "Wait" state, its bus state will appear as a series of MCU reads of an address which is seven locations less than the
original contents of the $tack Pointer. Contrary to the HD6800. none of the ports are driven to the high impedance state by a WAI instruction.
(Continued)
$
HITACHI
71
HD6801S0,HD6801S5--------------------------------------------------Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
RELATIVE
BCC BHT
BCS BlE
BEQ BlS
BGE BlT
BGT BMT
BRN
BSR
Data Bus
Address Bus
BNE
BPl
BRA
BVC
BVS
1
3
2
3
1
2
3
4
6
5
6
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
OpCode
Branch Offset
low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
1
1
1
1
0
0
OpCode
Branch Offset
low Byte of Restart Vector
Op Code of Next Instruction
Return Address (low Order Byte)
Return Address (High Order Byte)
• Sum....-y of Undefined Instruction Operations
The HD6801 S has 36 undefmed instructions. When these are
carried out, the contents of Register and Memory in MeV
change at random.
When the op codes (4E, SE) are used to execute, the MeV
continues to increase the program counter and it will not stop
until the Reset signal enters. These op codes are used to test the
LSI.
Table 13 Op codes Map
HD6801S MICROCOMPUTER INSTRUCTIONS
OP
CODE
~
0000
0
---------- --0000
0
0001
1
SBA
0001
1
0010
0011
2
3
NOP
0100
4
0101
6
0110
0111
6
7
1000
8
1001
9
INX (+11
oEX(+lI
1010
A
CLV
CBA
~
ACCAor SP
ACCB or X
ACC INo EXT
B
IMMj olRjlNo j EXT IMM DIR liND I EXT
0010
0011
0100 0101 0110 0111 1000j1001j 1010j1011 1100 11101 1111011111
4
7
2
3
5
6
C I 0 I ElF
8 I 9 I A I B
BRA
TSX
0
NEG
SUB
INS
CMP
1
BRN
2
BHI PULA (+1)
SBe
SUBD (+2)
: ADDD (+2)
3
BLS PULB (+1)
COM
4
AND
Bce
DES
LSR
ACC
A
~
ASLo (+1) ~ BCS
LSRo (+1)
TAP
TPA
TXS
TAB
BNE
PSHA
TBA
BEQ
PSHB
~ BVC PULX (+2)
DAA
BVS
RTS (+2)
~
BPL
1011
B
SEV
ABA
BMI
ABX
RTI (+7)
1100
C
CLC
~
BGE
PSHX (+1)
1101
0
SEC
/
BLT
MUL (+7)
1110
E
Cli
F
BYTE/CYCLE
1111
[NOTES)
/
BGT
WAI(+6)
SEI
~
BlE
SWI (+9)
112
1/2
2/3
1/3
-------- -
I
.
·
-----=-=-=-=
ROR
ASR
/I
6
~
STA
Aoe
9
DEC
ORA
A
TST
JMP (-3)
ClR
1/2
2/6
3/6
.:
~~I
.
ADD
CPX (+2)
JSR (+2)
LOS (+11
::. (+iil
2/2
STS(+1)
I 2/3
1 2/4 1 3/4
B
·
·
LoD (+1)
t:: (+1~
I
eHITACHI
I
0
E
LOX (+1)
STX (+1)
• (+1ij
2/2
2/3
2/4
3/4
I
I indicate that the number in parenthesis must be added to the cycle count for that instruction.
31 The instructions shown below are all 3 bytes and are marked with ......
Immediate addressing mode of SUBD, CPX, LOS, Aooo, loD and lOX instructions, and undefined op codes
(8F, CD, CFI.
41 The Op codes (4E, 6EI are 1 byte/oo cycles instructiOns. and are marked with .......
C
STD(+lI
1) Undefined Op codes are marked with ~ •
2)
72
7
8
EOR
ROL
INC
1/2
5
LOA
STA
ASL
..
BIT
I
F
e%
~
!
()
·SCI = TIE-TORE + RIE-(RORF + ORFE)
Vector-' PC
fiIMi
SWI
IRQ.
ICF
OCF
TOF
SCI
FFFC FFFO
FFFA FFFB
FFF8 FFF9
FFF6 FFF7
FFF4 FFF5
FFF2 FFF3
FFFO FFF1
Non-Maskable Interrupt
Software Interrupt
Maskable Interrupt Request 1
Input Capture Interrupt
OutpUt Compare Interrupt
Timer Overflow Interrupt
SCI Interrupt (TORE + RORF + ORFE)
~
C
0)
00
o
~
fJ)
p
~
C
0)
00
o
~
......
w
Figure 24 Interrupt Flowchart
fJ)
C1I
HD6801S0,HD6801S5----------------------------------------------------Vee
Vee
Enable
Enable
NMI
Port 3
8 Transfer
Lines
P"",1
81/0 lines
Port 1
8110
Lines
Port 2
51/0 Lines
SCI
16 Bit Timer
Port 4
8110 Lines
Por14
PorI 2
51/0 Lines "...-.,.'_ _~_ _I"'-"" 8110 lones
SCI
VSS
VSS
Figure 25 H068D1 S MCU Single-Chip Dual Processor Configuration
HD6801S
MCU
Address
Bus
Data
Bus
Figure 26 H06801 S MCU Expanded Non-Multiplexed Mode
Address Bus
Data Bus
Figure 27 H06801 S MCU Expanded Multiplexed Mode
74
_HITACHI
HD6801VO,HD6801V5
MCU (Microcomputer Unit)
The HD6801V MCU is an 8-bit microcomputer system which
is compatible with the H06801S except the ROM size. The
HD6801V MCU is object code compatible with the H06800
with improved execution times of key instructions plus several
new 16-bit and 8-bit instructions including an 8x8 unsigned
multiply with 16-bit result. The HD680lV MCU can operate as
a single chip microcomputer or be expanded to 65k words. The
HD6801V MCU is TTL compatible and requires one +5.0 volt
power supply. The H0680 1V MCU has 4k bytes of ROM and
128 bytes of RAM on chip. Serial Communications interface
(SCI), and parallel I/O as well as a three function 16-bit timer.
Features and Block diagram of the HD680lV include the
following:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
FEATURES
Expanded HMCS6800 Instruction Set
8 x 8 Multiply
On-Chip Serial Communications Interface (SCI)
Object Code Compatible With The HD6800 MPU
16-Bit Timer
Single Chip Or Expandable To 65k Words
4k Bytes Of ROM
128 Bytes Of RAM (64 Bytes Retainable On Power
Down)
29 Parallel I/O Lines And 2 Handshake Control Lines
Internal Clock/Divided-By-Four Circuitry
TTL Compatible Inputs And Outputs
Interrupt Capability
Compatible with MC6801 (except ROM size)
HD6801VOP
HD6801V5P
(DP-40)
• PIN ARRANGEMENT
0
SC,
sc,
p)(\
P"
P"
P 3~
P"
P ;\~
HD6801V
P)6
P"
P"
P"
P"
P"
P"
P.,
• BLOCK DIAGRAM
P"
P"
Vee Standby
(Top View)
.......--4-4--+--. P20
Iooh~--+--' P2I
•
J.H~""""'P22
,,*"",f-H-r-'"
~~!
$
TYPE OF PRODUCTS
MCU
Bus Timing
HD6801VO
1 MHz
HD6801V5
1.25 MHz
HITACHI
75
HD6801VO,HD6801V5-----------------------------------------------------•
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Supply Voltage
Vee
V'n
Input Voltage
Operating Temperature
*
*
Topr
TIIg
Storage Temperature
Value
Unit
-0.3-+7.0
V
-0.3 - +7.0
0 -+70
V
°c
- 55 -+150
°c
* With re~pect to VSS (SYSTEM GND)
[NOTE] Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded, it could affect reliability of LSI.
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee -S.OV±S%, Vss • OV, Ta - 0- +70°C, unless otherwise noted.)
Item
Input "High" Voltage
Input "Low" Voltage
Symbol
V'H
Other Inputs*
EXTAL
VIL
Other Inputs·
P40 - P47
SCI
EXTAl
Ibnl
Input leakage Current
NMI, IRQI, RES
Ilinl
Three State (Offset)
leaka.ge Current
P-,o P20 P 30 P40 Other
Input load Current
Output "High" Voltage
Output "low" Voltage
Vee Standby
Standby Current
-
P17 , P30 - P37
P24
P 37
P47 , E, SCI, SC 2
Outputs
IITs.!
V OH
VOL
-IDH
P I7
P30 - P 37 , P40
Other Inputs
typ
max
-
Vee
2.0
-0;3
-
-0.3
Vin = 0 - 5.2SV
-
Vin = 0.5 - 2.4V
-
I LOAO = -2051J.A
I LOAD = -1451J.A
2.4
2.4
I LOAD = -100 IJ.A
I LOAD = 1.6 mA
2.4
-
Vout = 1.5V
1.0
Vin =0-2.4V
P47 , SCI
Powerdown
Cin
Operating
VSBB
VSB
Powerdown
ISBB
Vin = OV, Ta = 25°C,
f = 1.0 MHz
VSBB = 4.0 V
$
HITACHI
-
-
-
Unit
V
Vee
0.6
0.8
V
0.5
0.8
1.2
2.5
10
100
mA
IJ.A
IJ.A
-
V
0.5
V
10.0
mA
1200
mW
-
-
-
12.5
-
10.0
4.0
-
5.25
4.75
-
5.25
-
-
8.0
-
Po
-
*Except Mode Programming Levels.
76
min
4.0
Vin = 0- Vee
All Outputs
Darlington Drive Current P IO
Power Dissipation
Input Capacitance
Test Condition
RES
pF
V
mA
-----------------------------------------------------HD6801VO,HD6801V5
• AC CHARACTERISTICS
BUS TIMING (Vee'" 5.0V±5%, Vss - OV, Ta· 0 - +70°C, unless otherwise noted.)
Symbol
Item
Cycle Time
Address Strobe Pulse Width "High"
tcyc
PW ASH
Address Strobe Rise Time
Address Strobe Fall Time
Address Strobe Delay Time
Enable Rise Time
Enable Fall Time
Enable Pulse Width "High" Time
Enable Pulse Width "Low" Time
Address Strobe to Enable Delay Time
Address Delay Time
Address Delay Time for Latch
Data Set-up Write Time
Data Set-up Read Time
Read
Data Hold Time
Write
Address Set-up Time for Latch
Address Hold Time for Latch
Address Hold Time
I
I
I
Non-Multiplexed Bus
Peripheral Read
Access Time
Multiplexed Bus
Oscillator stabilization Time
Processor Control Set-up Time
I
Test Condition
min
1
HD6801VO
typ
max
10
-
200
-
tASr
tASf
tASO
5
5
60
-
tEr
tEf
PW EH
,PW EL
5
5
450
450
60
tAsEO
tAD
tAOL
tosw
tOSR
tHR
tHW
tASL
tAHL
tAH
Fig. 1
Fig. 2
Fig. 10
Fig. 11
tRC
tpcs
-
-
-
-
20
60
-
-
-
-
100
200
-
5
5
50
50
-
50
-
-
-
-
115
-
80
-
10
20
50
20
20
-
(610)
(600)
-
-
260
270
Unit
p.s
-
-
-
-
-
HD6801V5
typ
max
10
-
30
5
5
340
350
30
-
-
-
20
50
50
-
225
80
10
(tACCN)
(tACCM)
50
50
-
20
-
min
.0.8
150
ns
ns
ns
ns
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
-
-
-
-
-
260
260
-
-
-
-
ns
ns
-
ns
-
-
(410)
-
-
(410)
-
100
-
200
ns
ns
-
ms
ns
-
PERIPHERAL PORT TIMING (Vee = 5.0V ±5%, Vss = OV, Ta" 0 - +70°C, unless otherwise noted.)
Symbol
Test Condition
min
typ
max
Unit
Peripheral Data Setup Time
Port 1,2,3,4
tposu
Fig. 3
200
Port 1, 2,3,4
tpOH
Fig. 3
200
-
ns
Peripheral Data Hold Time
-
Delay Time, Enable Positive Transition
to 053 Negative Transition
tos01
Fig. 5
-
-
350
ns
Delay Time, Enable Positive Transition
to 053 Positive Transition
tos02
Fig. 5
-
-
350
ns
Delay Time, Enable Negative
Transition to Peripheral Data
Valid
Port 1, 2*,3,4
tpwo
Fig.4
-
-
400
ns
Delay Time, Enable Negative
Transition to Peripheral
CMOS Data Valid
*
Port 2**, 4
t CMOS
Fig.4
-
-
2.0
/JS
tpWIS
Fig. 6
200
port 3
tlH
Fig. 6
50
Input Data Set-up Time
Port 3
tiS
Fig. 6
20
-
-
ns
Input Data Hold Time
Item
Input Strobe Pulse Width
ns
ns
ns
.... 'Okn pull up register required for Port 2
eHITACHI
77
HD6801VO,HD6801V5-----------------------------------------------------TIMER, SCI TIMING (Vee = 5.0V ±5%, Vss
=OV, Ta =0'" +70°C, unless otherwise noted.)
Item
Timer Input Pulse Width
Delay Time, Enable Positive Transition to
Timer Out
SCI Input Clock Cycle
Symbol
SCI Input Clock Pulse Width
tpWSCK
Test Condition
tTOo
min
2tcvc +200
tpWT
Fig. 7
t Scvc
1
0.4
typ
max
-
-
-
600
ns
-
-
t cvc
0.6
tScvc
Unit
ns
MODE PROGRAMMING (Vee = 5.0V ±5%, Vss = OV, Ta = 0'" +70°C, unless otherwise noted.)
min
typ
max
Unit
VMPL
-
1.7
VMPH
PW RSTL
4.0
3.0
2.0
-
-
-
V
V
tcyc
tcyc
Symbol
Item
Mode Programming Input "Low" Voltage
Mode Programming Input "High" Voltage
RES "Low" Pulse Width
Mode Programming Set-up Time
Fig. 8
tMPs
I m Rise Time ~ lJ.ls
I RES Rise Time < lJ.ls
Mode Programming
Hold Time
Test Gondition
tMPH
0
100
-
-
-
-
-
-
~---------------------t~----------------------~
Address Strobe
(AS)
2.4V
Enable
(E)
R/iN, Ar-A."
(SC~
(Port4)
MCU Write
Do -D? A. -A,
(Port 3)
tHR
MCU Read
0.-0,. A.-A,
(Port 3)
1+----ItACCM)---~
Figure 1 Expanded Multiplexed Bus Timing
78
$
HITACHI
ns
----------------------------------------------------HD6801VO,HD6801V5
1-----------
ENIbIe
eEl
teye
----------1
,1----- PWEL----II J
tE,
~A"Port4)
R!IiI (SC21
(set!
IO'S
-------.J
2V
MCU Writ..;e_ _ _ _ _ _ _-II-_ _ _ _ _ _ _ _2_._
-C1
0.-0,
O.6V
(Port 3)
1'-_ _ _ _+-+"1
1 + - - - - - etACCNI----..1
MCU Read_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _2_.O_V.(1
0.-0,
O.SV
(Port 3)
t------""I
Figure 2 Expanded Non-Multiplexed Bus Timing
rMCU Write
rMCURead
Enable(E)~
O.SV
Enable(E)
CMOS
t
tpwo
p •• - P"
11"
p.o - p,.
p.. -PO'
All Data
Port Outputs _ _ _ _ _ _ _. J
Inputs
- - - - 0.7 Vce
~:!~
08ta Valid
-P"
p ..
Inputs"
(Note)
1. 10 kU Pullup resistor required for Port 2 to reach 0.7 Vee
"Port 3 Non-Latched Operation (LATCH ENABLE = Ol
~: ~~r~1~i~~~~e::'Ued above Vee
Figure 3 Data Set-up and Hold Times
(MCU Read)
Figure 4 Port Data Delay Timing
(MCU Write)
rMCU access of Port 3*
Enable(E)
Add....
8us
053 ....- - - - -
PM -p ..
Inputs
...::::.:.r-1&.....----~......~::.:.---
* Access matches Output Strobe Select (OSS = 0, a read;
OSS
= 1, a write)
Figure 5 Port 3 Output Strobe Timing
(Single Chip Mode)
Figure 6 Port 3 Latch Timing
(Single Chip Mode)
eHITACHI
79
HD6801VO,HD6801V5----------------------------------------------------
Enable
(E)
Timer
Counter
-----
p ..
Output
Figure 8 Mode Programming Timing
Figure 7 Timer Output Timing
Vee
---1..,
Test Point 0 .......
m
RL.2.2kO
Test Point
30pF
152074
®
or EqUiV.
I
C
lal CMOS Load
R
Ibl TTL Load
Figure 9 Bus Timing Test loads
iRa,
*-----""\
~Or1Ra2
~---------------------------------------------------------------------
_t_
Data 8 u s J \ -.......~--.J\:~...J~~~~~~~~~~~~~~~"-A~CC""!8~-=:=-"!-"-==',~VOC~''''''''''''!'!VIC=tor~,..
..~
.. '!'''
.....
~.~-
....._______________.JI Dot.
MS8
\~
I nl~' nal R iW
* iR02
--
LA
.-.opt
Internal Interrupt
Figure 10 Interrupt Sequence
~\~\~\\\\\\\\\ ~\\\\\\\\\\\\\ ~ rtJl.JL[1..1LIl ~
_-l----41~' ~,_
~tI ~._
V~ ~~-4-.75-V------------------,~
______ ~ ~
~ __
E
-5.2W
RES
, ...
, ______________________-t,4.OV
t ....
08::,::V_ _ _ __
A.:;,o.n;,
M\\\\\\\%\\\\\\\~ SSSS\§\\\\\SSS~~
~
,on u.
FFFE
~
FFFE
'nto.n" RM
\\\\\\\\\\\\\§\\\\N: ~\\\\\\\§\\\SS\\S\§\\S\\\y .
~;,':';~: ~\\\\\\§\\\\\\%\~ I'MS\\\\\\\%\SS\\~
~
=pc:::x::x:
PCB-PC.S PCo--PCl
FI...
I....lruction
Figure 11 Reset Timing
80
::::x=:r-
_HITACHI
------------------------------------------------------HD6801VO,HD6801V5
• SIGNAL DESCRIPTIONS
•
• Vee and Vss
These two pins are used to supply power and ground to the
chip. The voltage supplied will be +5 volts ±5%.
•
XTAL and EXT AL
These connections are for a parallel resonant fundamental
crystal, AT cut. Divide by 4 circuitry is included with the
internal clock, so a 4 MHz crystal may be used to run the
system at 1 MHz. The divide by 4 circuitry allows for use of the
inexpensive 3.58 MHz Color TV crystal for non-time critical
applications. Two 22pF capacitors are needed from the two
crystal pins to ground to insure reliable operation. EXT AL may
be driven by an external TTL compatible clock source with a
50% (±IO%) duty cycle. It will divide by 4 any frequency less
than or equal to 5 MHz. XTAL must be grounded if an external
clock is used. The following are the recommended crystal parameters:
Nominal Crystal Parameter
~
·4 MHz
5 MHz
Co
7 pF max.
4.7 pF max.
Rs
600 max.
300 typo
Item
CL 1 = CL2 = 22pF ± 20%
(3.2 - 5 MHz)
[Note] These are representative
AT cut parallel resonance
crystal parameters.
t L 2 JrC
U
Figure 12 Crystal Interface
• Vcc Standby
This pin will supply +5 volts ±5% to the standby RAM on the
chip. The first 64 bytes of RAM will be maintained in the power
down mode with 8 rnA current max. The circuit of figure 13
can be utilized to assure that Vee Standby does not go below
VSBB during power down.
To retain information in the RAM during power down the
following procedure is necessary:
1) Write "0" into the RAM enable bit, RAM E. RAM E is bit
6 of the RAM Control Register at location $0014. This
disables the standby RAM, thereby protecting it at power
down.
2) Keep Vee Standby greater than VSBB.
Vee S",db,
T
Pow", L;~
Figure 13 Battery Backup for Vee Standby
• Enable (E)
This supplies the external clock for the rest of the system
when the internal oscillator is used. It is a single phase, TIL
compatible clock, and will be the divide by 4 result of the
crystal frequency. It will drive one TTL I()ad and 90 pF.
• Non-Maskable Interrupt (NMI)
XTAL~--~----~
EXTAL 1 - - -__..,
Reset (RES)
This input is used to reset and start the CPU from a power
down condition, resulting from a power failure or an initial
startup of the processor. On power up, the reset must be held
"Low" for at least 100 ms. During operation, RES, when
brought "Low" must be held "Low" at least 3 clock cycles.
When a "High" level is detected, the MCU does the following:
1) All the higher order address lines will be forced "High".
2) I/O Port 2 bits 2, I, and 0 are latched into programmed
control bits PC2, PCI and PeO.
3) The last two ($FFFE, $FFFF) locations in memory will
be used to load the program addressed by the program
counter.
4) The interrupt mask bit is set, must be cleared before the
CPU can recognize maskable interrupts.
A low-going edge on this input requests that a non-maskableinterrupt sequence be generated within the processor. As with
interrupt Request signal, the processor will complete the current
instruction that is being executed before it recognizes the NMI
signal. The interrupt mask bit in the Condition Code Register
has no effect on NMI.
In response to an NMI interrupt, the Index Register, Program
Counter, Accumulators, and Condition Code Register are stored
on the stack. At the end of the sequence, a 16-bit address will
be loaded that points to a vectoring address located in memory
locations $FFFC and $FFFD. An address loaded at these locations causes the CPU to branch to a non-maskable interrupt
service routine in memory.
A 3.3 kn external resistor to Vee should be used for
wire-OR and optimum control of interrupts.
Inputs l'RQ. and NMI are hardware interrupt lines that are
sampled during E and will start the interrupt routine on the
E following the completion of an instruction.
•
Interrupt Request (IRQ.)
This level sensitiv~ input requests that an interrupt sequence
be generated within the machine. The processor will wait until it
completes the current instruction that it being executed before
it recognizes the request. At that time, if the interrupt mask bit
in the Condition Code Register is not set, the'ml!chine will begin
an interrupt sequence. The Index Register, Progr.am Counter,
Accumulators, and Condition Code Register are stored on the
stack. Next the CPU will respond to the interrupt request by
setting the interrupt mask bit "High" so that no further maskable interrupts m~y occur. At the end of the cycle, a 16-bit
address will be loaded that points to a vectoring address which is
located in memory locations $FFF8 and $FFF9. An address
loaded at these locations causes the CPU to branch to an interrupt routine in memory.
The IRQ. requires a 3.3 kn external resister to Vee which
should be used for wire-OR and optimum control of in te.!!!Pts.
Internal Interrupts will use an internal interrupt line (IRQ2).
This interrupt will operate the same as IRQ. except that it will
use the vector address of $FFFO through $FFF7. IRQ. will
have priority over IRQz if both occur at the same time. The
Interrupt Mask Bit in the condition c()de register masks both
interrupts (See Table I).
eHITACHI
81
HD6801VO,HD6801V5----------------------------------------------------Table 1 Interrupt Vector Location
Vector
Highest
Priority
Interrupt
MSB
LSB
FFFE
FFFF
FFFC
FFFD
NM1
FFFA
FFFB
Software Interrupt (SWII
FFF8
FFF9
. FFF7
ICF (Input Capture)
FFF4
FFF5
OCF (Output Compare)
FFF2
FFF3
TOF (Timer Overflow)
FFFO
FFF1
SCI (RDRF + ORFE + TORE)
FFF6
Lowest
Priority
• PORTS
There are four I/O ports on the HD6801V MCU; three 8-bit
ports and one 5-bit port. There are two control lines associated
with one of the 8-bit ports. Each port has an associated write
only Data Direction Register which allows each I/O line to be
programmed to act as an input or an output * . A "1" in the
corresponding Data Direction Register bit will cause that I/O
line to be an output. A "0" in the corresponding Data Direction
Register bit will cause that I/O line to be an input. There are
four ports: Port 1, Port 2, Port 3, and Port 4. Their addresses
and the addresses of their Data Direction registers are given in
Table 2.
RES
IR.Q. (or IS3)
*
The only exception is bit
input or Timer output.
.1
of Port 2, which can either be data
Table 2 Port and Data Direction Register Addresses
The following pins are available in the Single Chip Mode, and
are associated with Port 3 only.
• Input Strobe (lS3) (SCd
The function of the IS3 signal depends on the I/O Port 3
Control/Status Register. If IS3 Enable bit is set, an interrupt
will occur by the fall of the IS3 signal. If the latch enable bit is
set, the data in the I/O Port 3 will be latched at the I/O Port 3
Data Register. The timing condition of the IS3 signal that is
necessary to be latched the input data normally is shown in
Figure 6.
• Output Strobe (OS3) (SC 2 )
This signal is used by the processor to strobe an external
device, indicating valid data is on the I/O pins. The timing for
the Output Strobe is shown in Figure 5 I/O Port 3 Control/
Status Register is discussed in the following section.
The follOWing pins are available in the Expanded Modes.
• Read/Write (R/Wl (SC 2 )
This TTL compatible output signals the peripherals and
memory devices whether the CPU is in a Read ("High") or a
Write ("Low") state. The normal standby state of this signal is
Read ("High"). This output is capable of driving one TTL load
and 90 pF.
• I/O Strobe (lOS) (SCI)
In the expanded non-multiplexed mode of operation, lOS
internally decodes A9 through AI5 as zero's and As as a one.
This allows external access of the 256 locations from $0100 to
$OIFF. The timing diagrams are shown as figure 2.
• Address Strobe (AS) (SCI)
In the expanded multiplexed mode of operation address
strobe is output on this pin. This signal is used to latch the 8
LS~'s of address which are multiplexed with data on Port 3. An
8-bit latch is utilized in conjunction with Address Strobe, as
shown, in figure 19. Expanded Multiplexed Mode. Address
Strobe signals the latch when it is time to latch the address lines
so the lines can become data bus lines during the E pulse. The
timing for this singal is shown in Figure 1 of Bus Timing. This
signal is also used to disable the address from the multiplexed
bus allowing a deselect time, tASD before the data is enabled to
the bus.
82
Ports
Port Address
I/O Port 1
$0002
$0003
$0006
$0007
110 Port 2
110 Port 3
110 Port 4
Data Direction
Register Address
$0000
$0001
$0004
$0005
•
I/O Port 1
This is an 8-bit port whose individual bits may be defined as
inputs or outputs by the corresponding bit in its data direction
register. The 8 output buffers have three-state capability,
allowing them to enter a high impedance state when the
peripheral data lines are used as inputs. In order to be read
properly, the voltage on the input lines must be greater than 2.0
V for a logic "1" and less than 0.8 V for a logic "0". As outputs these lines are TTL compatible and may also be used as
a source of up to 1 rnA at 1.5 V to directly drive a Darlington
base. After Reset, the I/O lines are configured as inputs. In all
three modes, Port 1 is always parallel I/O.
• I/O Port 2
This port has five lines that may be defined as inputs or
outputs by its data direction register. The 5 output buffers have
three-state capability, allowing them to enter a high impedance
state when used as an input. In order to be read properly, the
voltage on the input lines must be greater than 2.0 V for a
logic "1" and less than 0.8 V for a logic "0". As outputs, this
port has no internal pullup resistors but will drive TTL inputs·
directly. For driving CMOS inputs, external pullup resistors are
required. After Reset, the I/O lines are configured as inputs.
Three pins on Port 2 (pins 10, 9, and 8 of the chip) are used
to program the mode of operation durmg reset. The values of
these pins at reset are latched into the three MSB's (bits 7 6
and 5) of Port 2 which are read only. This is explained in th~
Mode Selection Section.
In all three modes, Port 2 can be configured as I/O and
provides access to the Serial Communications Interface and the
Timer. Bit 1 is the only pin restricted to data input or Timer
output.
• I/O Port 3
This is an 8-bit port that can be configured as I/O, a data bus,
or an address bus multiplexed with the data bus - depending on
the mode of operation hardware programmed by the user at
reset. As a data bus, Port 3 is bi-directional. As an input for
peripherals, it must be supplied regular TTL levels, that is,
greater than 2.0 V for a logic "1" and less than 0.8 V for a logic
"0".
_HITACHI
----------------------------------------------------HD6801VO,HD6801V5
Its TTL compatible three-state output buffers are capable of
driving one TTL load and 90 pF. In the Expanded Modes, after
reset, the data direction register is inhibited and data flow
depends on the state of the R/W line. The input strobe (IS3)
and the output strobe (OS3) used for handshaking are explained
later.
•
In the three modes, Port 3 assumes the following characteristics:
Single Chip Mode: Parallel Inputs/Outputs as programmed by
its associated Data Direction Register. There are two control
lines associated with this port in this mode, an input strobe and
an. output strobe, that can be used for handshaking. They are
controlled by the I/O Port 3 Control/Status Register explained
at the end of this section. Three options of Port 3 operations
are sumarized as follows: (1) Port 3 input data can be latched
using IS3 (SCI) as a control signal, (2) OS3 can be generated by
either an CPU read or write to Port 3's Data Register, and (3)
and IRQI interrupt can be enabled by an IS3 negative edge.
Port 3 latch and strobe timing is shown in Fig. 5 and Fig. 6.
Expanded Non-Multiplexed Mode: In this mode, Port 3
becomes the data bus (00 -0,).
Expanded Multiplexed Mode: In this mode, Port 3 becomes
both the data bus (Do -0,) and lower bits of the address bus
(Ao-A,). An address strobe output is true when the address is
on the port.
load and 90 pF. After reset, the lines are configured as inputs.
To use the pins as addresses, therefore, they should be
programmed as outputs. In the three modes, Port 4 assumes the
following characteristics:
Single Chip Mode: Parallel Inputs/Outputs as programmed by
its associated Data Direction Register.
Expanded Non-Multiplexed Mode: In this mode, Port 4 is
configured as the lower order address lines (Ao-A7)by writing
one's to the data direction register. When all eight address lines
are not needed, the remaining lines, starting with the most
significant bit, may be used as I/O (inputs only).
Expanded Multiplexed Mode: In this mode, Port 4 is
configured 3Slthe higher order address lines (As-Au) by writing one's to the data direction register. When all eight address
lines are not needed, the remaining lines, starting with the most
significant bit, may be used as I/O (inputs only).
• OPERATION MODES
The mode of operation that HD680lV will operate in after
Reset is determined by hardware that the user must wire on pins
10, 9, and 8 of the chip. These pins are the three LSB's (I/O 2,
I/O 1, and I/O 0 respectively) of Port 2. They are latched into
programmed control bits PC2, PC1, and PCO when reset goes
high. I/O Port 2 Register is shown below.
PORT 2 DATA REGISTER
7
I/O PORT 3 CONTROL/STATUS REGISTER
7
6
IS3
IRQ 1
FLAG ENABLE
5
4
3
2
X
OSS
LATCH
X
o
X
$0003
6
5
4
3
2
o
~-PC-2-TI-p-C-1~I-p-C-o~I~I-IO-·-4-1~1-IO--3~1~I/O--2~1-1/-O-1~1-I/-O-O~
X
IS3
$OOOF
Bit 0;
Bit 1;
Bit 2;
Bit 3;
Bit 4;
Bit 5;
Bit 6;
Bit 7;
•
ENABLE
Not used.
Not used.
Not used.
LATCH ENABLE. This controls the input latch for I/O
Port 3. If this bit is set "High" the input data will be
latched with the falling edge of the Input Strobe, IS3.
This bit is cleared by reset, and the latch is "re-opened"
with CPU read Port 3.
OSS. (Output Strobe Select) This bit will select if the
Output Strobe should be generated at OS3 (SC 2 ) by a
write to I/O Port 3 or a read of I/O Port 3. When this bit
is cleared the strobe is generated by a read Port 3. When
this bit is set the strobe is generated by a write Port 3.
Not used.
IS3 IRQ1 ENABLE. When set, interrupt will be enabled
whenever IS3 FLAG is set; when clear, interrupt is
inhibited. This bit is Cleared by RES.
IS3 FLAG. This is a read only status bit that is set by
the falling edge of the input strobe, IS3 (SC I). It is
cleared by a .read of the Control/Status Register followed by a read or write of I/O Port 3. Reset will clear
this bit.
I/O Port 4
This is an 8-bit port that can be configured as I/O or as
address lines depending on the mode of operation. In order to
be read properly, the voltage on the input lines must be greater
than 2.0 V for a logic "1" and less than 0.8 V for a logic "0" .
As outputs, each line is TTL compatible and can drive 1 TTL
An example of external hardware that could be used for
Mode Se}ection is shown in Fig 14. The HDl4053B provides
the isolation between the peripheral device and MCV during
Reset, which is necessary if data conflict can occur between
peripheral device and Mode generation circuit.
As bits 5, 6 and 7 of Port 2 are read only, the mode cannot
be changed through software. The mode selections are shown in
Table 3.
The HD6801V is capable of operating in three basic modes;
(1) Single Chip Mode, (2) Expanded Multiplexed Mode (compatible with HMCS6800 peripheral family) (3) Expanded NonMultiplexed Mode.
• Single Chip Mode
In the Single Chip Mode the Ports are configured for I/O.
This is shown in Figure 16 the single Chip Mode. In this
mode, Port 3 will have two associated, control lines, an input
strobe and an output strobe for handshaking data.
•
Expanded Non-Multiplexed Mode
In this mode the HD680-lV will directly address HMCS6800
peripherals with no external logic. In this mode Port 3 becomes
the data bus. Port 4 becomes the Ao-A 7 address bus or partial
address and I/O (inputs only). Port 2 can be parallel I/O, serial
I/O, Timer, or any combination of them. Port 1 is parallel I/O
only. In this mode the HD6801V is expandable to 256 locations. The eight address lines associated with Port 4 may be
substituted for I/O (inputs only) if a fewer number of address
lines will satisfy the application (See Figure 17).
_HITACHI
83
HD6801VO,HD6801V5----------------------------------------------------Vee
(
R
~
!
~
R, R,~ R,
6
TT T
ABC
HD6801V
Xo
..--
Yo
X
Zo
Y
X,
Z
RES
8
9
P20 (PCOI
P2 , (PC11
10 P22 (PC21
Y,
Z,
(
C
I
(
???
~
Mode
Control
Switch
HD14053B
Inh
[NOTES)
J,
11 Mode 7 as shown
21 RC",Reset time constant
31 R, =10kn
Figure 14 Recommended Circuit for Mode Selection
Truth Table
Control Input
Inh
Binary to 1-of-2
Decoder with
Inhibit
A
B
C
C B A
Xocr----------------~~~4-~~~
Xl~------------------~~+-~--~
yocr--------------------~~~--~
ylcr--------------------~C*~--~
Zocr----------------------~~~~
Zlcr-------------------------K~~
x
y
Z
On Switch
Select
Inhibit
HD14053B
0
0
0
0
Zo Yo Xu
0
0
0
1
Zo Yo X,
0
0
1 0
Zo Y, X.
0
0
1
1
Zo Y, X,
0
1 0
0
Z, Yo Xo
0
1
0
1
Z, Y. 'X,
0
1
1 0
Z, Y, Xo
0
1
1
Z, Y, X,
1
X X X
1
-
Figure 15 HD14053B Multiplexers/Demultiplexers
Vee
Vee
2
7
40
Enable
Enable
Port 1
81/0 Lines
Port 3
8110 lines
Port 4
81/0 Lines
Port 2
51/0 lines
Vss
SCI
Timer
Port 3
8 Data Lines
Port 2
5 Parallel 110
SCI
Timer
Vss
Port 4
To 8 Address
lines or To
8110 Lines
(Inputs Onlvl
Figure 17 HD6801V MCU Expanded Non-Multiplexed Mode
Figure 16 HD6801V MCU Single-Chip Mode
84
Port 1
8 Parallel 110
$
HITACHI
------------------------------------------------------HD6801VO,HD6801V5
•
Expanded Multiplexed Mode
Vee
In this mode Port 4 becomes higher order address lines with
an alternative of substituting some of the address lines for I/O
(inputs only). Port 3 is the data bus multiplexed with the lower
order address lines differentiated by an output called Address
Strobe. Port 2 is 5 lines of Parallel I/O, SCI, Timer, or any
combination of them. Port 1 is 8 Parallel I/O lines. In this mode
it is expandable to 65k words. (See Figure 18).
•
Enable
Lower order Address Bus Latches
8 Lines
Multiplexed
Data/Address
Port 1
8 I/O Lines
Since the data bus is multipfexed with the lower order
address bus in Port 3, latches are required tei latch those address
bits. The 74LS373 Transparent octal D-type latch can be used
with the HD6801V to latch the least significant address byte.
Figure 19 shows how to connect the latch to the HD6801V.
The output control to the 74LS373 may be connected to
ground.
Port 2
5 I/O Lines
SCI
Timer
Port 4
To 8 Address
Lines or To
B I/O Lines
(Inputs Only)
Vss
Figure 18 HD6801V MCU Expanded Multiplexed Mode
GND
AS
\
G OC
0,
Port 3
Address/Data
[
Q,
1
D.
Function Table
A Zero
BGE
2
BGT
2C
2E
3
> Zero
3
2
Branch If Higher
BHI
22
3
2
Branch If" Zero
BlE
2F
3
2
Branch If lower Or
Same
BlS
23
3
2
C+Z -1
BLT
20
3
2
N(±)V=1
Branch If
Branch If
< Zero
•
•
•
•
•
None
= Zero
Branch If
5 4 3 2 1 0
H I N Z V C
#
N(±)V-O
Z + (N (±) VI .. 0
C+Z-O
Z + (N (±) VI .. 1
Branch If Minus
BMI
2B
3
2
N" 1
Branch If Not Equal
Zero
BNE
26
3
2
Z=O
Branch If Overflow
Clear
BVC
28
3
2
V-O
Branch If Overflow Set
BVS
29
3
2
V-1
Branch If Plus
BPl
2A
3
2
N"O
Branch To Subroutine
BSR
80
6
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• •
• •
• •
• •
• •
• •
• •
••
• •
• •
••
• •
• •
• •
• •
• •
• •
• •
• •
• •
Jump
JMP
Jump To Subroutine
JSR
No Operation
NOP
01
Return From Interrupt
RTI
3B 10 1
-@-
Return From
Subroutine
RTS
39
5 1
Software Interrupt
SWI
3F 12 1
Wait for Interrupt
WAI
3E
• • • • • •
• S•• ••
• @. • • •
6E
90
3
2 AD 6
5
2 7E
• •
• •
• •
• •
• •
•• •
• • •
• ••
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
2
3
3
BD 6
3
--
2
9
1
Advances Prog. Cntr.
Only
1
Table10 Condition Code Register Manipulation Instructions
AddressingModes
Operations
Mnemonic
IMPLIED
OP
-
Condition Code Register
Bool.ean Operation
#
Clear Carry
ClC
Clear Interrupt Mask
Cli
OE
2
1
O-+C
0-+1
Clear Overflow
ClV
OA
2
1
O-+V
Set Carry
SEC
00
2
1
1-+C
Set Interrupt Mask
SEI
OF
2
1
1 -+ I
Set Overflow
OB
2
1
Accumulator A -+ CCR
SEV
TAP
06
2
1
1"'V
A ... CCR
CCR -+ Accumulator A
TPA
07
2
1
CCR-+ A
OC
2
1
5
4
3
2
1
0
H
I
N
Z
V
C
• • • • • R
• R • • • •
• • • • R •
• • • • • S
• S • • • •
• • • • S •
---@) ----• • • • • •
Condition Code Register Notes: (Bit set it test is true and cleared otherwisel
f double accumulator A:B in memory. The contents of ACCD
remain unchanged.
SUBD Subtracts the contents of M:M + I from the contents of double accumulator AB
and places the result in ACCD.
BRN
Never branches. If effect, this instruction can be considered a two byte NOP (No
operation) requiring three cycles for execution.
CPX
Internal processing modified to permit its use with any conditional branch instruction.
*ACCD'is the 16 bit register (A:B) formed by concatenating the A and B accumulators. The A-accumulator is the most significant byte.
Table 8 Index Register and Stack Manipulation Instructions
Condition Code
Register
Addressing Modes
Pointer Operations
Compare Index Aeg
----Decrement Index Aeg
----------Decrement Stack Pntr
Mnemonic
CPX
IMMED.
OP
-.
8C
4
DIAECT
--,- - - , . - - - -
INDEX
-.
OP
-
#
OP
3 9C
5
2
AC 6
2
EXTND
OP
-
BC 6
IMPLIED
::
OP
-
'"
09
3
1
X -1 .... X
SP - 1 .... SP
3
DEX
Booleanl
ArithmetiC OperatIOn
X-M:M+1
DES
34
3
1
Increment Index Aeg
INX
08
3
1
X + 1 .... X
Increment Stack Pntr
INS
31
3
1
SP + 1 .... SP
Load Index Reg
LOX
CE
3
3
DE 4
2 EE
5
2 FE
5
3
M .... XH. (M+1) .... XL
Load Stack Pntr
LOS
8E
3
3
9E
4
2 AE 5
5
3
Store Index Aeg
STX
OF
4
2 EF
2 BE
2 FF
5
3
M .... SP H . (M+1) .... SP L
XH .... M.XL .... (M+1)
9F
4
2 AF 5
2 BF
5
3
Store Stack Pntr
STS
Index Aeg .... Stack Pntr
TXS
--~-
Stack Pntr·" Index Aeg
TSX
5
SPH .... 'III. SP L .... (M+ 1)
35
3
1
X -1 .... SP
30
3
1
SP + 1 .... X
'-c-- --f--
Add
ABX
3A
3
1 B + X .... X
Push Data
PSHX
3C
4
1
XL .... Mw. SP - 1 .... SP
1
XH .... M sP • SP - 1 .... SP
SP + 1 .... SP. Msp .... XH
Pull Data
PULX
38
5
5 4 3
H
SP + 1 .... SP. M sP .... XL
•
•
•
•
•
•
•
2_~E
I N Z·V C
•
I
I
I
I
I
• • I • •
•••••
• • I • •
• •• • •
• .}) I
A'.
• (1) I
.(j)1
R
•
R •
•
• • V I R -•
•• • • • •
•• • • • •
• • • •
•••• • •
-
•• ••
-
-\-
The Condition Code Register notes are listed after Table 10.
125
H 0 6 8 0 3 , H 0 6 8 0 3 - 1 - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ __
Table 9 Jump and Branch Instructions
Condition Code
Register
Addressing Modes
Mnemonic
Operations
RELATIVE
OP
-
#
DIRECT
OP
2
-
#
INDEX
OP
-
#
IMPLIED
EXTND
OP
-
Branch Test
#
OP
-
It
None
Branch Always
BRA
20
Branch Never
BRN
21
3
2
None
Branch If Carry Clear
BCC
24
3
:2
C=O
3
Branch If Carry Set
BCS
25
3
2
C=1
Branch If = Zero
BEQ
27
3
2
Z=1
Branch If ;;. Zero
BGE
2C
3
2
N<±>V=O
Branch
If ....
> _._--Zero
_~~T
_ _ -t2E
-_.
__ ._
3
2
Z + (N
0
VI = 0
IC+Z=O
Branch If Higher
BHI
22
3
2
Branch If..; Zero
BlE
2F
3
2
Z + (N <±> VI = 1
Branch If lower Or
Same
BlS
23
3
2
C +Z = 1
BlT
20
3
2
N
BMI
2B
3
2
N=l
--------Branch If
< Zero
Branch If Minus
- - - - - - -----
-
<±l
-----
-
BNE
26
3
2
Z=O
BVG
28
3
2
V=O
BVS
29
3
2
V= 1
BPl
2A
3
2
N=O
Branch To Subroutine
BSR
80
6
2
Jump
JMP
Branch If Not Equal
Zero
_.. _ -
-
__
--
-----------
Branch If Plus
---.--
3
2
7E
3
3
AD 6
2
BD 6
3
6E
2
4
3
2
1
I
N Z
V
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
••
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
·•
V =1
L--.
Branch If Overflow
Clear
-_.
._--Branch If Overflow Set
5
H
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• •
·••
•
•
•
•
•
•
•
•
•
•
•
•
·••
· ·•
0
·•
•
•
•
•
•
•
Jump To Subroutine
JSR
No Operation
NOP
01
Return From Interrupti
RT!
3B 10 1
-@-
Return From
Subroutine
RTS
39
5 1
Software Interrupt
SWI
3F
12 1
Wait for Interrupt
WAI
3E
9
• • • • •
• S • • • •
~. • • •
------
---1-
- - _ .. _.-
90
Tablel0
5
2
1
Advances Prog. Cntr.
Only
·
1
Condition Code Register Manipulation Instructions
iAddressingModes
Operations
Mnemonic
Condition Code Register
Boolean Operation
IMPLIED
OP
ClC
OC
2
CLI
OE
2
00
.
OF
2
1
l-C
2
1
1 .... 1
---.Clear Overflow
1
ClV
OA
2
----------------- t - - . - - - - - - - ._- +--- f---.
------~-
SEC
Set Interrupt Mask
---_._------_._1---.
SEI
- . - f-
O .... C
-----_._-o-v
------ -.. --_._-----0-1
Set Overflow
SEV
OB
2
l .... V
Accumulator A .... CCR
TAP
06
2
A .... CCR
CCR .... Accumulator A
TPA
07
2
CCR-A
- - - - - - ..- - - - - - -
2
1
0
Z
V
C
• • • • •
•
• R •
R
·· •
126
---._----
• S
• S • • • •
• • • • S •
--~----
•
Test: Result = 10oo00oo?
Test: Result" 00000000?
Test: Decimal value of most significant BCD Character greater than nine? (Not cleared if previously set)
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
Test: Set equal to result of N <±> C after shift has occurred.
Test: Result less than zero? (Bit 15 = 1)
load Condition Code Register from Stack. (See Special Operations)
Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exit the wait state.
Set according to the contents of Accumulator A.
Set equal to result of Bit 7 (AccBI
~HITACHI
R
--t--
Condition Code Register Notes: (Bit set it test is true and cleared otherwise)
1 (Bit VI
(Bit C)
(Bit C)
(Bit VI
(Bit VI
(Bit VI
(Bit NI
(A")
(Bit I)
(A"I
(Bit CI
4
H
Clear Interrupt Mask
1
3
N
5
#
Clear Carry
Set Carry
·
• • • •
----------------------------H06803,H06803-1
Table 11
ACCX I~~:- Direct te~~~
ABA
ABX
ADC
ADD
ADDD
AND
ASL
ASLD
ASA
•
•
•
•
•
•
BCC
•
•
BCS
BEQ
BGE
BGT
BHI
BIT
BLE
BLS
BLT
BMI
BNE
BPL
BAA
BAN
BSA
BVC
BVS
CBA
CLC
CLI
CLA
CLV
CMP
COM
CPX
DAA
DEC
DES
DEX
EOA
2
•
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2
•
•
2
•
•
2
•
•
INC
2
INS
•
In-
Instruction Execution Times in Machine Cycle
1m-
dexed plied
•
•
•
•
•
•
•
2
3
2
3
4
4
4
4
5
3
6
4
6
•
•
•
•
•
•
•
•
•
6
6
•
•
•
•
•
•
2
4
2
•
•
•
•
•
•
•
•
2
•
•
•
.,i
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
4
•
3
6
6
•
•
•
•
•
•
•
•
•
•
•
•
4
4
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
6
6
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2
2
2
•
2
•
2
3
4
4
•
•
5
6
6
•
4
6
6
•
•
•
•
•
•
•
•
2
6
6
•
•
•
•
2
3
4
4
•
•
•
•
6
•
'.
•
6
•
•
3
3
•
•
3
Aelative
•
•
•
•
•
•
•
•
3
3
3
3
3
ACCX
INX
JMP
JSA
LOA
LDD
LOS
LOX
LSR
LSAD
MUL
NEG
NOP
OAA
PSH
PSHX
•
3
3
3
3
3
3
3
3
6
3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PUL
PULX
AOL
AOA
ATI
ATS
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI
~HITACHI
•
•
•
•
•
•
•
2
•
•
2
•
•
3
•
4
•
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2
•
•
•
Im-
Aelative
3
•
•
•
•
plied
•
•
•
•
2
5
3
•
3
3
3
•
•
•
•
•
4
4
4
•
•
•
•
•
•
•
3
6
4
5
5
5
6
3
5
5
5
6
•
•
•
•
6
6
•
•
6
4
2
3
4
4
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2
3
4
•
•
•
•
•
•
•
•
•
•
•
•
•
6
6
•
•
•
3
4
4
4
5
5
5
4
3
5
6
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
4
4
•
•
•
•
•
6
•
•
•
•
•
•
•
•
•
•
3
10
•
2
•
•
4
•
5
•
•
10
5
2
•
2
2
2
•
•
•
•
•
•
12
2
2
2
2
•
3
3
9
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
127
H06803,H06803-1----------------------------• Summary of Cycle by Cycle Operation
Table ) 2 provides a detailed description of the information
present on the Address Bus. Data Bus, and the Read/Write line
(R/W) during each cycle for each instruction.
This information is useful in comparing actual with expected
results during debug of both software and hardware as the
control program is executed. The information is categoriled in
groups according to addressing mode and number of cycles per
instruction. (In general. instructions with the same addressing
mode and number of cycles execute in the same manner: eXceptions are indicated in the table).
Table 12 Cycle by Cycle Operation
Address Mode &
Instructions
Address Bus
Data Bus
IMMEDIATE
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
2
LDS
LOX
LDD
3
CPX
SUBD
ADDD
4
I
1
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Operand Data
1
2
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (low Order Byte)
4
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address Bus F F F F
1
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (low Order Byte)
Low Byte of Restart Vector
1
2
3
Op Code Address
Op Code Address + 1
Address of Operand
1
1
1
3
1
2
3
DIRECT
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
3
Operand Data
I
I
STA
3
LDS
LDX
LDD
4
1
2
3
STS
STX
STD
lOP
Cod<
Address of Operand
I
4
5
JSR
5
I Op Code Address
1
1
0
Op Code
Destination Address
Data from Accumulator
I
1
2
I
3
4
I
1
2
3
4
Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand + 1
1
1
0
0
Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)
1
2
Op Code Address
Op Code Address + 1
Operand Address
Operand Address + 1
Address Bus F F F F
1
1
1
1
1
lOP Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Subroutine Address
Stack Pointer
Stack Pointer + 1
1
1
1
0
0
I
CPX
SUBD
ADDD
Op Code Address
I Op Code Address + 1
I Destination Address
I
3
4
5
1
2
3
4
5
Op Code Address + 1
; Address of Operand
Operand Address + 1
1
1
1
1
lOP
Cod<
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
R!!turn Address (High Order Byte)
(Continued)
128
_HITACHI
----------------------------H06803,H06803-1
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Data Bus
Address Bus
INDEXED
JMP
3
1
2
---1------1-
ADC EOR
4
ADD LOA
AND ORA
BIT SBC
CMP SUB
---------------------- --------STA
4
3
1
2
3
4
Op Code Address
Op Code Address + 1
Address Bus F F F F
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data
-------Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
-.--
1
2
3
4
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
0
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
1
1
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
----~
LOS
LOX
LDD
LOO
5
STS
STX
STD
5
ASL
ASR
CLR
COM
DEC
INC
3
4
5
1
2
3
4
5
LSR
NEG
ROL
ROR
TST*
----.----
CPX
SUBD
ADDD
--_.
JSR
1
2
--------
6
----
6
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
Address Bus F F F F
I-Index Register Plus Offset
------Op Code Address
1
Op Code Address + 1
2
Address Bus F F F F
3
Index Register + Offset
4
Index Register + Offset + 1
5
Address Bus F F F F
6
1
2
3
4
5
6
' Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register + Offset
Stack Pointer
Stack Pointer - 1
0
0
1
1
1
1
1
0
Op Code
Offset
Low Byte of Restar,t Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data
- - ~Op Code
1
Offset
1
Low Byte of Restart Vector
1
Operand Data (High Order Byte)
1
Operand Data (Low Order Byte)
1
Low Byte of Restart Vector
1
1
1
1
1
0
0
Op Code
Offset
Low Byte of Restart Vector
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
• In the TST Instruction, R/W line of the sixth cycle is "'" level, and AB = FFFF, DB = Low Byte of Reset Vector.
_HITACHI
(Continued)
129
HD6803,HD6803-1--------------------------Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
Data Bus
EXTENDED
3
JMP
1
2
3
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
4
1
2
3
4
4
STA
1
2
3
4
LOS
LOX
LDD
5
STS
STX
STD
5
ASL
ASR
CLR
COM
DEC
INC
1
2
3
4
5
1
2
3
4
5
6
LSR
NEG
ROL
ROR
TST-
1
2
3
4
5
6
CPX
SUBD
ADDD
6
JSR
6
1
2
3
4
5
6
-
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
1
1
1
1
OpCode
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data
Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Destination Address
1
1
1
0
Op Code
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
1
1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
0
0
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address Bus F F F F
Address of Operand
1
1
1
1
1
0
OpCode
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF
1
1
1
1
1
1
Op Code
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
1
1
1
1
0
Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
• In the TST instruction, R/W line of the sixth cvcle is "'" level, and AB
130
0
=FFFF, DB = Low Byte of Reset Vector.
~HITACHI
(Continued)
---------------------------H06803,H06803-1
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
Data Bus
IMPLIED
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM
ABX
DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA
SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST
2
1
2
I
I
3
ASLD
LSRD
3
DES
INS
3
INX
DEX
3
PSHA
PSHB
3
TSX
3
4
Op Code Address
Op Code Address + 1
Address Bus F F F F
Op Code Address
Op Code Address + 1
Address Bus FFFF
Op Code Address
Op Code Address + 1
Previous Register Contents
Op Code Address
Op Code Address + 1
Address Bus FFFF
Op Code Address
Op Code Address + 1
Stack Pointer
Op Code Address
Op Code Address + 1
Stack Pointer
Op Code Address
Op Code Address + 1
Address Bus FFFF
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer +2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
5
Stack Pointer + 2
1
1
2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
1
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
_.
3
1
2
3
PULA
PULB
4
PSHX
4
1
2
3
4
1
2
3
PULX
5
4
1
2
3
4
5
RTS
5
1
2
3
WAI--
Op Code
Op Code of Next Instruction
1
1
i
2
3
TXS
Op Code Address
Op Code Address + 1
9
3
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
0
I Op Code
i
Irrelevant Data
Low Byte of Restart Vector
Op Code
Irrelevant Data
Low Byte of Restart Vector
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
Op Code
Op Code of Next Instruction
Accumulator Data
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code
Irrelevant Data
Index Register (Low Order Byte)
Index Register (High Order Byte;
Op Code
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)
OpCode
Irrelevant Data
Irrelevant Data
Address of Next Instruction
(High Order Byte)
Address of Next Instruction
(Low Order Byte)
Op Code
OJ? Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
(Continued)
$
HITACHI
131
H06803,H06803-1----------------------------Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Cycles
WAI··
Cycle
:;:
5
6
7
8
9
MUL
10
1
2
3
4
5
6
7
RTI
10
.,..
SWI
12
Stack
Stack
Stack
Stack
Stack
Pointer
Pointer
Pointer
Pointer
Pointer
-
2
3
4
5
6
Op Code Address
Op Code Address + 1
Address Bus FFFF
Address Bus F F F F
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFf
Address Bus FFFF
R/W
Line
0
0
0
0
0
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
Stack Pointer + 2
1
6
Stack Pointer + 3
1
7
Stack Pointer + 4
1
8
Stack Pointer + 5
1
9
Stack Pointer + 6
1
10
Stack Pointer + 7
1
10
11
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Stack Pointer - 7
Vector Address FFFA (Hex)
1
1
0
0
0
0
0
0
0
1
1
12
Vector Address FFFB (Hex)
1
8
9
------.
Address Bus
10
1
2
3
4
1
2
3
4
5
6
7
8
9
Data Bus
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Op Code
Irrelevant Data
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Op Code
Irrelevant Data
Irrelevant Data
Contents of Condo Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from
Stack (High Order Byte)'
Next Instruction Address from
Stack (Low Order Byte)
Op Code
Irrelevant Data
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)
(Continued)
•• While the MPU is in the "Wait" state, its bus state will appear as a series of MPU reads of an address which is seven locations less than the
original contents of the Stack Pointer. Contrary to the HD6800, none of the ports are driven to the high impedance state by a WAI
instruction.
132
$
HITACHI
----------------------------------------------------------H06803,H06803-1
Table
12 Cycle by Cycle Operation (Continued)
RELATIVE
Address Mode &
Instructions
BCC
BCS
BEQ
BGE
BGT
BRN
BHT
BLE
BLS
BLT
BMT
Cycle
Cycles
BNE·
BPL
BRA
BVC
BVS
1
3
2
3
6
BSR
1
2
3
4
5
6
R/W
line
Address Bus
#
1
Op Code Address
Op Code Address + 1
Address Bus F F F F
Table 13
Op Code
Branch Offset
Low Byte of Restart Vector
1
1
1
1
1
1
Op Code Address
Op Code Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
• Summary of Undefined Instruction Operations
The HD6803 has 36 underfined instructions. When these are
carried out, the contents of Register and Memory in MPU
change at random.
Data Bus
Op Code
Br anch Offset
Low Byte of Restart Vector
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
0
0
When the op codes (4E. SE)are used to execute. the MPU
continues to increase the program counter and it will not stop
until the Reset signal enters. These op codes are used to test the
LSI.
Op codes Map
HD6803 MICROPROCESSOR INSTRUCTIONS
OP
CODE
ACC
A
~
0000
LO
0000
0
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
0001
1
2
3
BRA
TSX
CBA
BRN
INS
~
BHI
PULA (+1)
BLS
PULB (+1)
BCC
DES
~
BCS
TXS
------- ---NOP
~
LSRD (+1)
ASLD (+1)
0011
SBA
0
------
0010
TAP
TAB
BNE
PSHA
TPA
TBA
BEQ
PSHB
ACC IND
B
ACCA orSP
EXT
0100 0101 0110 0111
4
5
7
6
IMM
ACCB or X
I DIR IINDt EXT
1000110011'O'0j 1011
B
A j
S j
9 j
~
COM
I E~
liND
C
I
I
0
E
I
F
0
CMP
.
SBC
SUBD (+2)
I
AND
LSR
--
·
ADDD (+2)
14
' 5
6
~
STA
2
~
LOA
~
1
--
- -t---
BIT
ROR
ASR
I DIR
1100 11101111101,111
SUB
NEG
--------
IMM
STA
i 7
1000
S
INX (+1)
~
BVC
PULX (+2)
ASL
EOR
1001
9
DEX (+1)
DAA
BVS
RTS (+2)
ROl
ADC
1010
A
CLV
~
BPL
ABX
DEC
ORA
A
1011
B
SEV
ABA
8MI
RTI (+7)
ADD
~B
1100
C
CLC
~
BGE
PSHX (+1)
1101
0
SEC
/
BLT
MUL (+7)
1110
E
Cli
BGT
WAI (+61
1111
F
SEI
~-
BLE
SWI (+9)
1/2
1/2
2/3
1/3
BYTE/CYCLE
[NOTES)
~.
~
INC
- .. --
JMP (-31
CLR
1/2
i
112
.
.
CPX (+2)
BSR 1
(+4)
TST
2/6
JSR (+2)
LOS (+11
; (+lil
3/6
STS (+1)
2/2 1 2/31 2/4
i 3/4
S
9
·
·
LDD (+1)
STD (+1)
LOX (+11
• (+1~
2/2
;C
-~-
k (+111
STX (+1)
!D
I
E
F
I 2/3 I 2/4 I 3/4
11 Undefined Op codes are marked with ~ .
21 (
) indicate that the number in parenthesis must be added to the cycle count for that instruction.
31 The instructions shown below are all 3 bytes and are marked with ......
Immediate addressing mode of SUBD, CPX, LDS, ADDD, LDD and LDX instructions, and undefined op codes
(SF, CD, CFI.
41 The Op codes (4E, 5E) are 1 byte/" cycles instructions, and are marked with ......
~HITACHI
133
-
%
o
ca
~
2
%
o
CJ)
~
.-
e%
~
(')
~
·SCI = TIE·TORE + RIE'(RORF + ORFE)
Vector- PC
NMI
SWI
IRQ,
ICF
OCF
TOF
SCI
FFFC FFFO
FFFA FFF8
FFF8 FFF9
FFF6 FFF7
FFF4 FFF5
FFF2 FFF3
FFFO FFF1
A
Figure 16 Interrupt Flowchart
Non-Maskable Interrupt
Software Interrupt
Maskable Interrupt Request 1
Input Capture Interrupt
Output Compare Interrupt
Timer Overflow Interrupt
SCI Interrupt (TORE + RORF + ORFE)
----------------------------H06803,H06803-1
Address Bus
Data Bus
Fi9ure 17 HD6803 MPU Expanded Multiplexed Bus
~HITACHI
135
HD6805S1--~----------
MCU (Microcomputer Unit)
The HD680SS1 is the 8-bit Microcomputer Unit (MCU)
which contains a CPU, on-chip clock, ROM, RAM, I/O and
timer. It is designed for the user who needs an economical
microcomputer with the proven capabilities of the HD
6800-based instruction set.
The following are some of the hardware and software
highlights of the M CU.
• HARDWARE - FEATURES
• 8-Bit Architecture
• 64 Bytes of RAM
• Memory Mapped I/O
• 1100 Bytes of User ROM
• Internal 8-Bit Timer with 7·Bit Prescaler
• Vectored Interrupts - External and Timer
• 20 TTL/CMOS Compatible '1/0 Lines; 8 Lines LED
Compatible
• On-Chip Clock Circuit
• Self-Check Mode
• Master Reset
• Low Voltage Inhibit
• Complete Development System Support by Evaluation
kit
• 5 Vdc Single Supply
• Compatible with MC6B05P2
• SOFTWARE FEATURES
• Similar to HD6BOO
• Byte Efficient Instruction Set
• Easy to Program
• True Bit Manipulation
• Bit Test and Branch Instructions
• Versatile Interrupt Handing
• Powerful Indexed Addressing for Tables
• Full Set of Conditional Branches
• Memory Usable as Registers/Flags
• Single Instruction Memory Examine/Change
TlMER• 10 Powerful Addressing Modes
• All Addressing Modes Apply to ROM, RAM and I/O
• Compatible with MC6B05P2
HD6805S1P
(DP·28)
• PIN ARRANGEMENT
Vss
1
INT
A,
Vee
EXTAL
A.
A.
4
XTAL
NUM
TIMER
7
HD6805S1
C.
A.
C,
B,
a,
a.
af
a.
B,
B,
C,
C,
B.
(Top View)
• BLOCK DIAGRAM
Accumuilitor
A
Port
A
A,
1/0
A4
Llnfl
A,
Control
Indu
...
A,
A'J
cpu
8
Reglst"
X
A
Reg
Oat.
0"
Reg
Cod.
S
Register CC
10 I/O
It Lines
I,
I,
Condition
Port
I.
I,
I, Por,
I, I
cpu
A.
A,
C. Po"
C,
C
C, I/O
ALU
1100.8
ROM
Self check
ROM
136
eHITACHI
C, Linn
---------------------------------------------------------------HD6805S1
• ABSOLUTE MAXIMUM RATINGS
.
Vin
Unit
V
V
V
-0.3 - +7.0
-0.3 ..... +7.0
Vee •
Operating Temperature
Storage Temperature
•
Value
Symbol
Item
Supply Voltage
Input Voltage (EXCEPT TIMER)
Input Voltage (TIMER)
Topr
-0.3 -+12.0
o -+70
T stg
- 55-+150
°c
°c
With respect to Vss (SYSTEM GNO)
(NOTE)
Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vcc·5.25V ± O.5V, Vss=GND, Ta=D-+70°C, unless otherwise noted.)
Item
Input "High" Voltage
Input "High" Voltage Timer
Input "Low" Voltage
Symbol
RES
INT
All Other
Timer Mode
Self -Check Mode
RES
INT
-EXTAl(Crystal Mode)
min typ
Test Condition
VIH
4.0
-
3.0
2.Q
-
V
V
V
V
-
0.8
0.6
0.8
V
V
2.0
9.0
-0.3
-0.3
VIL
-0.3
-0.3
All Other
max Unit
V
Vee
Vee
Vee
Vee
11.0
0.8
-
V
V
Po
LVR
-
-
700
low Voltage Recover
-
-
4.75
V
Low Voltage Inhibit
LVI
-
4.0
-
V
Power Dissipation
-20
-
20
p.A
-50
-
50
p.A
-1200
-
0
p.A
TIMER
INT
EXTAl(Crystal Mode)
Input Leak Current
IlL
mW
V;n=0.4V-V ee
• AC CHARACTERISTICS (Vcc=5.25V ± O.5V, Vss=GND, Ta=O - +70°C, unless otherwise noted.)
Item
Clock Frequency
Cycle Time
Symbol
---.
Oscillation Frequency (External Resistor Mode)
tEXT
INT Pulse Width
tlWL
RES Pulse Width
t RwL
TIMER Pulse Width
tTWL
Oscillation Start·up Time (Crystal Mode)
tose
Delay Time Reset
Input Capacitance
tRHL
!
I
Test Condition
XTAl
All Other
C;n
$
min
typ
-
0.4
1.0
fel
tcyc
Rep =15.0kH±1%
tcyc +
250
t Cyc +
250
t Cyc +
250
C L=22pF±20%.
Rs =60n max.
External Cap. = 2.2 p.F
V;n=OV
HITACHI
-
-
3.4
1 -
I
max Unit
4.0 MHz
10 p.s
-
MHz
-
ns
--+ -
ns
-
-
ns
-
-
100
ms
,laO
-
-
ms
-
-
30
10
pF
pF
-
137
HD6805S1------------------------------------------------------------• PORT ELECTRICAL CHARACTERISTICS (Vee
Item
=5 25V ± 0 5V
Output "Low" Voltage
Port B
typ
max
Unit
2.4
IOH = -200~A
2.4
-
V
IOH = -100~A
-
-
0.4
V
0.4
V
1.0
V
VIH
2.0
-
Vee
V
VIL
-0.3
-
0.8
V
-
~A
VOH
IOH
1.5
mA
IOH = -100~A
IOL = 1.6 mA
2.4
IOL = 3.2mA
VOL
IOL
= 10mA
Port A, B, C
-500
Vin = 0.8V
Vjn = 2V
PortA
Input Leak Current
= -1
Port A and C
Port B
Ta = 0"" +70°C, unless otherWise noted;)
3.5
Test Condition
PortC
Input "High" Voltage
Input "Low" Voltage
=GND
min
Port A
Output "High" Voltage
Vss
IOH = -10~A
Symbol
IlL
Port B, C
Vjn
-300
= 0.4V"" Vee
TTL Equiv. (Port BI
-20
V
V
V
V
-
.~A
20
~A
TTL Equiv. (Port A and CI
Vee
2.4kSl
Ii s 3.2mA
Ii = 1.6mA
Test Point
Test Point
o-.----~~----~----~---.
Vi
Vi
40pF
(NOTE)
30pF
12kn
24 kn
1. Load capacitance includes the floating capacitance of the probe and the jig etc.
2. All diodes are 182074 or equivalent.
Figure 1 Bus Timing Test Loads
• SIGNAL DESCRIPTION
• TIMER
The input and output signals for the MCU, shown in PIN
ARRANGEMENT, are described in the following paragraphs.
This pin allows an external input to be used to decrement the
internal timer circuitry. Refer to TIMER for additional information about the timer circuitry.
• Vee
.ndVss
Power is supplied to the MCU using these two pins. VCC is
+5.25 V ±O.S V. VSS is the ground connection.
•
INT
This pin provides the capability for asynchronously applying
an external interrupt to the MCU. Refer to INTERRUPTS for
additional information.
•
XTAL.Rd EXTAL
These pins provide connections for the on-chip clock circuit.
A crystal (AT cut, 4 MHz maximum), a resistor or an external
signal can be connected to these pins to provide a system clock
with various stability/tost tradeoffs. Refer to INTERNAL OSCILLATOR OPTIONS for recommendations about these inputs.
138
•
RES
•
NUM
This pin allows resetting of the MCU at times other than the
automatic resetting capability already in the MCU. Refer to
RESETS for additional information.
This pin is not for user application and should be coMected
to Vss.
• Input/Output Lines (Ao .... A" Bo - B,. Co .... C])
These 20 lines are arranged into tow 8-bit ports (A and 8)
and one 4-bit port (C). All lines are programmable as either
inputs or outputs under software control of the Data Direction
Registers (DDR). Refer to INPUT/OUTPUT for additional
information.
_HITACHI
-----------------------------------------------------------------HD6805S1
• MEMORY
increments when it pulls data from the stack; A subroutine call
will cause only the program counter (PCH, PCL) contents to be
pushed onto the stack.
The MCU memory is configured as shown in Figure 2. During
the processing of an interrupt, the contents of the CPU registers
are pushed onto the stack in the order shown in Figure 3. Since
the stack pointer decrements during pushes, the low order byte
(peL) of the program counter is stacked first; then the high
order three bits (PCH) are stacked. This ensures that the
program counter is loaded correctly as the stack pointer
o
7
000
7
$00o
I/O Ports
Timer
RAM
(128 Bytes)
127
128
o
255
256
IS:
959
960
1923
1924
Port B
Interrupt
Vectors
ROM
(8 Bytes)
1
1
1
1
$000
$001
I
$002
PortC
Not Used
$003
4
Port A DDR
$004-
5
Port B DDR
$005-
6
I
$006-
Not Used
Port C DDR
7
Not Used
$007
8
Timer Data Reg
$008
9
Timer CTR L Reg
$783
$784
10
$7F 7
$7F 8
63
64
$009
$OOA
Not Used (54 Bytes)
$03F
$040
RAM (64 Bytes)
~
St~ck
12
$07F
-Write only registers
$7F F
2047
o
2
3
o
Self Check
ROM
(116 Bytes)
2039
2040
1
$3B F
$3C
Main
ROM
(964 Bytes)
3
4
Port A
$0 F
$10 o
Not Used
ROM
(704 Bytes)
5
6
o
2
$07 F
Page Zero
ROM
(128 Bytes)
Caution: - Self Test ROM Address Area
Self test ROM locations can not be used for a user program.
If the user's program is in this location, it will be removed when
manufacturing mask for production.
Figure 2 MCU Memory Configuration
6
n-4
1
5
1
1
l
4
3
n-3
n-2
Index Register
0
0
Condition
Code Register
Accumu lator
Pull
I
A
n+1
1
1
1
1
11
I Index Register
0
PCL-
I
n+3
PCH*
Accumulator
0
X
n+2
10
n-1
n
2
PC
10
n+4
10
5 4
1 0 1 0 101
111
I
I
Program Counter
0
SP
Stack Pointer
n+5
Condition Code Register
Push
* For subroutine calls. only PCH and PCL are stacked
Carry/Borrow
Figure 3 Interrupt Stacking Order
Zero
Negative
l...-_ _ _ _ _ _
Interrupt Mask
Half Carry
Figure 4 Programming Model
$
HITACHI
139
Ho8805S1---------------------------------------------------------• REGISTERS
The CPU has five registers available to the programmer.
They are shown in Figure 4 and are explained in the following
parqraphs.
• Alcumullltor (A)
The accumulator is a general purpose g·bit register used to
hold operands and results of arithmetic calculations or data
manipulations.
• Index R..ister (X)
The index register is an g·bit register used for the indexed
addressing mode. It contains an S·bit address that may be added
to an offset value to create an effective address. The index
register can also be used for lim ited calculations and data
manipulations when using read/modify/write instructions. When
not required by a code sequence being executed, the index
register can be used as a temporary storage area.
• Prognm Counter (PC)
The program counter is an Il·bit register that contains the
address of the next instruction to be executed.
• StICk Pointer (SP)
The stack pointer is an II·bit register that contains the
address of the next free'location on the stack. Initially, the
stack pointer is set to location $07F and is decremented as data
is being pushed onto the stack and incremented as data is being
pulled from the stack. The six most significant bits of the stack
pointer are permanently set to 000011. During a MCU reset or
the reset stack pointer (RSP) instruction, the stack pointer is set
to location $07F. Subroutines and interrupts may be nested
down to location $061 which allows the programmer to use up
tol S levels of subroutine calls.
• Condition Code Aegistw ICC)
The condition code register is a S-bit register in which each
bit is used to indicate or flag the results of the instruction just
executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each
individual condition code register bit is explained in the
fonowing paragraphs.
Half Carry (H)
Used during arithmetic operations (ADD and ADC) to
indicate that a carry occurred between bits 3 and 4.
Interrupt (I)
This bit is set to mask the timer and external interrupt (INT).
If an interrupt occurs while this bit is set it is latched and will be
processed as soon as the interrupt bit is reset.
Negative IN)
Used to indicate that the result of the last arithmetic, logical
or data manipulation was negative (bit 7 in result equal to a
logical one).
Zero (Z)
Used to indicate that the result of the last arithmetic. logical
or data manipulation was zero.
Carry/Borrow (C)
Used to indicate that a carry or borrow out of the arithmetic
logic unit (ALU) occurred during the last arithmetic operation.
This bit is also affected during bit test and branch instructions.
shifts, and rotates.
• TIMER
The MCU timer circuitry is shown in Figure 5. The 8-bit
counter, the Timer Data Register (TOR), is loaded under pro·
gram control and counts down toward zero as soon as the clock
input is applied. When the timer reaches zero, the timer interrupt request bit (bit 7) in the Timer Control Register (TCR) is
set. the CPU responds to this interrupt by saving the present
CPU state on the stack, fetching the timer interrupt vector from
locations $7F8 and $7F9 and executing the interrupt routine.
The timer interrupt can be masked by setting the timer inter·
rupt mask bit (bit 6) in the TCR. The interrupt bit (I bit) in the
Condition Code Register also prevents a time interrupt from
being processed.
, The clock input to the timer can be from an external source
applied to the TIMER input pin or it can be the internal qn.
signal. When the 4>2 signal is used as the source, it can be gated
by an input applied to the TIMER input pin allowing the user
1/>,
(Internal)
TIR; Timer Interrupt Request
TIM; Timer Interrupt Mask
Timer
Input
Pin
r··---.,
•••
IL _____ "
••I
I
•
Manufacturing
Mask Options
Write
Read
Figure 5 Timer Block Diagram
140
_HITACHI
Write
Read
---------------------------------------------------------------HD6805S1·
to easily perform pulse-width measurements. The TIMER input
pin must be tied to Vee, for ungated tP2 clock input to the
timer prescaler. The source of the clock input is one of the
options that has to be specified before manufacture of the
MCV. A prescaler option can be applied to the clock input that
extends the timing interval up to a maximum of 128 counts
before decrementing the counter (TDR). The timer continues
to count past zero, falling through to $FF from zero and then
continuing the count. Thus, the counter (TDR) can be read at
any time by monitoring the TDR. This allows a program to
determine the length of time since a timer interrupt has occurred and not disturb the counting process.
At power-up or reset, the prescaler and counter are initialized
with all logical ones; the timer interrupt request bit (bit 7) is
cleared, and the timer interrupt mask bit (bit 6) is set.
(NOTE) If the MCV Timer is not used, the TIMER input pin
must be grounded.
2
TNT
•
SELF CHECK
The self-check capability of the MCU provides an internal
check to determine if the part is functional.· Connect the MCU
as shown in Figure 6 and monitor the output of port C bit 3 for
an oscillation of approximately 3Hz .
•
RESETS
The MCV can be reset three ways; by initial power-up, by
the external reset input
and by an optional internal low
voltage inhibit circuit, see Figure 7. All the I/O port are initialized to input mode (DDRs are cleared) during reset.
During power-up, a minimum of 100 milliseconds is needed
before allowing the trnS input to go "High".
This time allows the internal crystal oscillator to stabilize.
Connecting a capacitor to the ~ input, as shown in Figure 8,
typically provides sufficient delay.
oms)
A7 27
A. 26
*
28 RES
A.25
A.24
2.2I'F
5
XTAL
4
EXTAL
A, 23
A, 22
A, 21
Ao 20
+9V
7
TIMER
6
NUM
Vee
HD6805S1
(Resistor option)
B7 19
B. 18
B, 17
B. 16
8
Co
B, 15
9
C,
B, 14
10 C,
B, 13
11 C,
B" 12
Vee = Pin 3
Vss = Pin 1
• Refer to Figure 9 about c;rystal option
Figure 6 Self Check Connections
RES
Pin
-------of'
Internal
Reset
Figure 7 Power Up and RES Timing
·_HITACHI
141
HD6805S11-------------------------------------------------------------• INT~RNAL OSCILLATOR OPTIONS
The internal oscillator circuit is designed to require a mini-.
mum of external components. A crystal, a resistor, a jumper
wire, or an external signal may be used to generate a system
clock with various stability/cost tradeoff. A manufacturing
mask option is required to select either the crystal oscillator or
the RC oscillator circuit. The different connection methods are
shown in Figure 9. Crystal specifications are given in Figure 10.
A resistor selection graph is given in Figure 11.
28
Figure 8 Power Up Reset Delay Circuit
5 XTAL
5 XTAL
M HZ
4 m a x c::J
4 EXTAL
HD6805S1
MCU
4 EXTAL
HD6805S1
MCU
22PF t 20%:;+;
Crystal
Approximately 25% Accuracy
External: Jumper
Vee
5
5 XTAl
XTAl
R
External
Clock
Input
4 EXTAl
HD6805S1
MCU
4 EXTAl
HD6805S1
MCU
No
Connection
External Clock
Approximately 15% Accuracy
External Resistor
CRYSTAL OPTIONS
RESISTOR OPTIONS
Figure 9 Internal Oscillator Options
5
1
j
C.
XTAL~~EXTAl
5.~~
4
\,
I
~
>
u
I
i\
4
3
C
4J
:l
AT C. =
f= 4
RS =
Cut Parallel Resonance Crystal
7 pF max.
MHz IC. =22pFt20%)
60n max.
C"
~
LL
2
\
~
~ i'-..,
~
~~
Figure 10 Crystal Parameters
o
5
10
15
20
25
30
Resistance Ikn)
35
40
Figure 11 Typical Resistor Selection Graph
142
$HI-':-ACHI
J
Vee = 5.25V
TA = 25°C -
45
50
-------------------------------------------------------------HD6805S1
1---1
7F ---SP
Stack
PC,X,A,CC
o .... DDR·s
CLR INT Logic
FF .... Timer
7F .... Presealer
7F ___ TCR
Load PC From
SWI :$7FC, $7FD
rnT':$7FA, $7FB
TIMER :$7F8, $7F9
Load PC From
Reset: $7FE. $7FF
Fetch
Instruction
SWI
Y
Execute
Instruction
Figure 12 Interrupt Processing Flowchart
Data
Direction
Register
Bit
Input to
MCU
Output
Data Bit
Output
State
0
0
0
3-State
Pin
1
Figure 13 Typical Port 1/0 Circuitry
$
HITACHI
0
143
HD6805S1-------------------------------------------------------------•
INTERRUPTS
•
The CPU can be interrupted three different ways: through
the external interrupt (INT) input pin, the internal timer
interrupt request, and a software interrupt instruction (SWI).
When any interrupt occurs, processing is suspended, the present
CPU state is pushed onto the stack, the interrupt bit (I) in the
Condition Code Register is set, the address of the interrupt
routine is obtained from the appropriate interrupt vector
address, and the interrupt routine is executed. The interrupt
service routines normally end with a return from interrupt
(RTl) instruction which allows the CPU to resume processing
of the program prior to the interrupt. Table 1 provides a listing
of the interrupts, their priority, and the vector address that
contain-the starting address of the appropriate interrupt routine.
A flowchart of the interrupt processing sequence is given in
Figure 12.
Table 1 Interrupt Priorities
Interrupt
Priority
Vector Address
RES
SWI
INT
TIMER
1
$7FE and $7FF
$7FC and $7FD
$7FA and $7FB
$7F8 and $7F9
2
3
4
INPUT/OUTPUT
There are 20 input/output pins. All pins are programmable
as either inputs or outputs under software- control of the corresponding Data Direction Register (DDR). When programmed
as outputs, all I/O pins the latched output data is readable as
input data, regardless of the logic levels at the output pin due to
output loading (see Figure 13). When port B is programmed
for outputs, it is capable of sinking lOrnA on each pin (VOL =
IV max). All input/output lines are TTL compatible as both
inputs and outputs. Port A is CMOS compatible as outputs, and
Port Band C are CMOS compatible as inputs. Figure 14 provides some examples of port connections,
•
BIT MANIPULATION
The MCU has the ability to set or clear any single random
access lVemory or input/output bit (except the data direction
registers) with a single instruction (88ET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines. The example in Figure 15
illustrates the usefulness of the bit manipulation and test
instructions. Assume that bit 0 of port A is connected to a zero
crossing detector circuit and that bit 1 of port A is connected to
the trigger of a TRIAC which powers the controlled hardware.
This program, which uses only seven ROM locations,
provides turn-on of the TRIAC within 14 microseconds of the
zero crossing. The timer could also be incorporated to provide
turn-on at some later time which would permit pulse-width
modulation of the controlled power.
Bo
Port A
···
·
Port B
_ - - - - 4 r ¥ l c· "'FE' Ie
B,
Port A Programmed as output(s), driving CMOS and TTL Load directly.
Port B Programmed as output(s), driving Darlington-base directly.
(a)
(b)
+v
+V
R
-
Port B
Port C
10 mA max
B,
t - - - -.....-
CMOS Inverter
C,
Port B Programmed as output(s), driving LED(s) directly.
(c)
Port C Programmed as output(s), driving CMOS loads, using external
(d)
pull-Up resistors.
Figure 14 Typical Port Connections
144
···•
··
_HITACHI
---------------------------------------------------------------HD6805S1
SELF 1
··
··
BRCLR 0, PORT A, SELF 1
BSET 1, PORT A
BCLR 1, PORT A
Figure 15 Bit Manipulation Example
• ADDRESSING MODES
The CPU has ten addressing modes available for use by the
programmer. They are explained and illustrated briefly in the
following paragraphs.
• Immediate
Refer to Figure 16. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte following the
opcode.
• Direct
Refer to Figure 17. In direct addressing, the address of the
operand is contained in the second byte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. All RAM space, I/O registers and 128
bytes of ROM are located in page zero to take advantage of this
efficient memory addressing mode.
• Extended
Refer to Figure 18. Extended addressing is used to reference
any location in memory space. The EA is the contents of the
two bytes following the opcode. Extended addressing instructions are three bytes long.
• Relative
Refer. to Figure 19. The relative addressing mode applies only
to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA=(pC)+2+Rel. ReI is the contents
of the location following the instruction opcode with bit 7
being the sign bit. If the branch is not taken Rel=O, when a
branch takes place, the program goes to somewhere within the
range of + 129 bytes to -127 of the present instruction. These
instructions are two bytes long.
• Indexed (No Offset)
Refer to Figure 20. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and their EA is the contents of the index register.
• Indexed (8-bit Offset)
Refer to Figure 21. The EA is calculated by adding the
contents of the byte following the opcode to the contents of
the index register. In this mode, 511 low memory locations are
accessable. These instructions occupy two bytes.
• Indexed (16-bit Offset)
Refer to Figure 22. This addressing mode calculates the EA
by adding the contents of the two bytes following the opcode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are three
bytes long.
• Bit Set/Clear
Refer to Figure 23. This mode of addressing applies to
instructions which can set or clear any bit on page zero. The
lower three bits in the opcode specify the bit to be set or
cleared while the byte following the opcode specifies the
address in page zero.
• Bit Test and Branch
Refer to Figure 24. This mode of addressing applies to
instructions which can test any bit in the first 256 locations
($OO-$FF) and branch to any location relative to the PC. The
byte to be tested is addressed by the byte following the opcode.
The individual bit within that byte to be tested is addressed by
the lower three bits of the opcode. The third byte is the relative
address to be added to the program counter if the branch condition is met. These instructions are three bytes long_ The value of
the bit tested is written to the carry bit in the condition code
register.
• Implied
Refer to Figure 25. The implied mode of addreSSing has no
EA. All the information necessary to execute an instruction is
contained in the opcode. Direct operations on the accumulator
and the index register are included in this mode of addressing.
In addition, control instructions such as SWI, RTI belong to this
group. All implied addressing instructions are one byte long.
•
INSTRUCTION SET
The MCV has a set of 59 basic instructions. They can be
divided into five different types: register/memory, read/modify/
write, branch, bit manipulation, and control. The following
paragraphs briefly explain each type. All the instructions within
a given type are presented in individual tables.
• Register/Memory Instructions
Most of these instructions use two operands. One operand is
either the accumulator or the index register. The other operand
is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR)
instructions have no register operand. Refer to Table 2.
• Read/Modity/Write Instructions
These instructions read a memory location or a register,
modify or test its contents, and write the modified value back
to memory or to the register. The test for negative or zero
(TST) instruction is an exception to the read/modify/write
instructions since it does not perform the write. Refer to Table
3.
• Branch Instructions
The branch instructions cause a branch from the program
when a certain condition is met. Refer to Table 4.
• Bit Manipulation Instructions
These instructions are lIsed on any bit in the first 256 bytes
of the memory. One group either sets or clears. The other group
performs the bit test and branch operations. Refer to Table 5.
• Control Instructions
The control mstructions control the MCV operations during
program execution. Refer to Table 6.
• Alphabetical Listing
The complete instruction set is given in alphabetical order in
Table 7.
• Opcode Map
Table 8 is an opcode map for the instructions used on the
MCV.
~HITACHI
145
HD6805S1---------------------------------------------------------------
Memory
i
I
I
I
I
§
Stack Point
I
I
I
PROG LDA #$F8 058E
05BF
A6
Prog Count
F8
05CO
'------..f
CC
I
I
§
I
I
,I
Figure 16 Immediate Addressing Example
lEA
+
Memory
I
i
I
I
I
I
I
I
I
I
I
I
CAT
FCB
32
LDA
CA T
/
1
0048
~
Adder
20
0048
'"
ol
0520
B6
052E
48
I
I
I
I
I
Figure 17 Direct Addressing Example
~HITACHI
20
I
Index Reg
Stack Point
~
146
A
-,,
I
I
PROG
I
I
Prog Count
052F
CC
I
I
I
------------------------------------------------------------------HD6805S1
,,
Memory
,
,
I
~
I
PROG
LOA
CAT
~~ J
040A
06
040B
E5
64
40
Index Reg
Stack Point
I
I
I
FCB
A
I
I
CAT
0000
Prog Count
040C
40
06E5
CC
Figure 18 Extended Addressing Example
EA
,
04C1
Memory
I
~
A
Index Reg
Stack Point
I
I
PROG
BEQ
PROG2
04A7
27
0000
i-------l
04A8
18
~
I
,
,
Figure 19
Relative Addressing Example
~HITACHI
147
HD6805S1---------------------------------------------------------------
Memory
A
TABL
FCC
t Lit 00B8
4C
4C
49
Index Reg
B8
I
PROG
LOA
X
I
Stack Point
05F4~
Prog Count
05F5
CC
§
I
Figure 20 Indexed (No Offset) Addressing Example
,
t
I
I
I
FCB
#BF
0089
BF
FCB
#86
008A
86
FCB
#OB
008B
OB
FCB
#CF
008C
CF
I
,
I
I
,
lEA
008C
I
I
TABL
,
Melory
/
Adder
I'
I
'"
A
J
I
CF
I
Index Reg
I
03
I
Stack Point
PROG
LOA
TAB L. X 075B
E6
075C
89
I
I
I
I
§
I,
I,
Figure 21
148
I
I
Prog Count
Indexed (S·Bit Offset) Addressing Example
~HITACHI
0750
CC
I
---------------------------------------------------------------HD6805S1
lEA
I
MeJory
I
i
I
I
I
§
§
LOA
TAB L. X 0692
0693
0694
FCB
#BF
Adder
~
A
DB
I
Index Reg
--.r
I
02
1
Stack Point
I
I
07
J
7E
I
TABL
/
.J
--.
I
PROG
f
I
I
0780
BF
077F
86
FCB
#86
FCB
#OB
0780
DB
FCB
#CF
0781
CF
Figure 22
I
I
0695
CC
I
077E
I
Prog Count
I
I
Indexed (16-Bit Offset) Addressing Example
Memory
PORTB
EQU
BF
0001
A
Index Reg
PROG BeLR 6. PORT B
058F
0590
10
Stack Point
I--------t
01
Prog Count
0591
I
I
CC
~
I
I
I
Figure 23 Bit Set/Clear Addressing Example
~HITACHI
149
HD680551-------------------------------
PORT C
EQU
2
0002
FO
A
Index Reg
Stack Point
PROG BRClR 2. PORT C. PROG 2
0574
05
0575
.....------4
02
0576
r--~l;-;D:;--;-l----.
Prog Count
0594
CC
C
Figure 24 Bit Test and Branch Addressing Example
Memory
I
I
I
I
~
PROG
TAX
I
I
I
I
A
E5
Index Reg
E5
D~A§
Prog Count
05B8
I
I
I
I
cc
§
Figure 25
150
Implied Addressing Example
~HITACHI
-----------------------------------------------------------------HD6805S1
Table 2
I_~"k
Function
Register/Memory Instructions
Addressing Modes
f---------
Immediate
I
Direct
It
Op
Op
#
Code 8ytes Cycles Code
~ Indexed
Indexed
I
(No Offset)
(8·8it Offset)
Extended
It
Op
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
I
It
,.
Op
Bytes Cycles Code
j
Indexed
(16·8it Offset)
It
#
Op
8ytes Cycles Code
#
#
Bytes Cycles
Load A from Memory
LOA
A6
2
2
B6
2
4
C6
3.
5
F6
1
4
E6
2
5
06
3
6
Load X from Memory
LOX
AE
2
2
BE
2
4
CE
3
5
FE
1 1-4
EE
2
5
DE
3
6
Store A in Memory
STA
-
-
B7
2
5
C7
3
6
F7
1
5
E7
2
6
07
3
7
Store X in Memory
STX
-
-
-
BF
2
5
CF
3
6
FF
1
5
EF
2
6
OF
3
7
ADD
AB
2
2
BB
2
4
C8
3
5
FB
1
4
EB
2
5
DB
3
6
Add
M~mory
to A
Add Memory and
Carry to A
AOC
A9
2
2
B9
2
4
C9
3
5
F9
1
4
E9
2
5
09
3
6
Subtract Memory
SUB
AO
2
2
BO
2
4
CO
3
5
FO
1
4
EO
2
5
DO
3
6
Subtract Memdry from
A with Borrow
S8C
A2
2
2
B2
2
4
C2
3
5
F2
1
4
E2
2
5
02
3
6
AND Memory to A
AND
A4
2
2
B4
2
4
C4
3
5
F4
1
4
E4
2
5
04
3
6
OR Memory with A
ORA
AA
2
2
BA
2
4
CA
3
5
FA
1
4
EA
2
5
OA
3
6
Exclusive OR Memory
with A
EOR
A8
2
2
88
2
4
C8
3
5
F8
1
4
E8
2
5
08
3
6
Arithmetic Compare A
with Memory
CMP
Al
2
2
Bl
2
4
Cl
3
5
Fl
1
4
El
2
5
01
3
6
Arithmetic Compare X
with Memory
5
F3
1
4
E3
2
5
03
3
6
--I-
CPX
A3
2
2
B3
2
4
C3
3
Bit Test Memory with A
(Logical Compare)
BIT
AS
2
2
B5
2
4
C5
3
5
F5
1
4
E5
2
5
05
3
6
Jump Unconditional
JMP
-
8C
2
CC
3
FC
1
3
EC
2
4
DC
3
5
JSR
-
4
Jump to Subroutine
-
3
BO
2
7
CD
3
8
FO
1
7
ED
2
8
DO
3
9
Table 3
Read/Modify/Write Instructions
Addressing Modes
Function
Implied (AI
Mnemonic
Op
Code
Implied (XI
Op
#
#
Bytes Cycles Code
Indexed
(No Offset)
Direct
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(8-Bit Offset)
Op
#
#
Bytes Cycles Code
#
#
Bytes Cycles
Increment
INC
4C
1
4
5C
1
4
3C
2
6
7C
1
6
6C
2
7
Decrement
DEC
4A
1
4
SA
1
4
3A
2
6
7A
1
6
6A
2
7
Clear
CLR
4F
1
4
SF
1
4
3F
2
6
7F
1
6
6F
2
7
Complement
COM
43
1
4
53
1
4
33
2
6
73
1
6
63
2
7
Negate
(2's Complement)
NEG
40
1
4
50
1
4
30
2
6
70
1
6
60
2
7
Rotate Left Thru Carry
ROL
49
1
4
59
1
4
39
2
6
79
1
6
69
2
7
Rotate Right Thru Carry
ROR
46
1
4
56
1
4
36
2
6
76
1
6
66
2
7
Logical Shift Left
LSL
4B
1
4
58
1
4
38
2
6
78
1
6
68
2
7
Logical Shift Right
LSR
44
1
4
54
1
4
34
2
6
74
1
6
64
2
7
Arithmetic Shift Right
ASR
47
1
4
57
1
4
37
2
6
77
1
6
67
2
7
Arithmetic Shift Left
ASL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
Test for Negative or
Zero
TST
40
1
4
50
1
4
3D
2
6
70
1
6
60
2
7
~HITACHI
151
HD6805S1---------------------------------------------------------------Table 4 Branch Instructions
Relative Addressing Mode
Mnemonic
Function
Op
Code
#
#
Bytes
Cycles
Branch Always
BRA
20
2
Branch Never
BRN
21
2
Branch I F Carry Clear
BCC
24
2
4
4
4
4
4
(Branch IF Higher or Same)
(BHS)
24
2
4
Branch I F Carry Set
BCS
25
2
4
(Branch IF lower)
(BlO)
25
2
4
Branch I F Not Equal
BNE
26
2
Branch I F Equal
BEQ
27
2
4
4
Branch I F Half Carry Clear
BHCC
28
2
4
Branch I F Half Carry Set
BHCS
29
2
4
Branch IF Higher
BHI
22
2
Branch I F lower or Same
BlS
23
2
Branch I F Plus
BPl
2A
2
4
Branch I F Minus
BMI
2B
2
4
Branch I F Interrupt Mask Bit is Clear
BMC
2C
2
4
Branch I F Interrupt Mask Bit is Set
BMS
20
2
4
Branch I F Interrupt Line is low
Bil
2E
2
4
Branch IF Interrupt Line is High
BIH
2F
2
4
Branch to Subroutine
BSR
AD
2
8
Table 5 Bit Manipulation Instructions
Addressing Modes
Function
Mnemonic
Bit Set/Clear
Op
Code
Bit Test and Branch
#
#
Bytes
Cycles
-
Op
Code
#
#
Bytes
Cycles
-
2 n
3
10
-
01+2 n
3
10
-
-
Branch I F Bit n is set
BRSET n (n=O ..... 7)
Branch I F Bit n is clear
BRClR n (n=O ..... 7)
Set Bit n
BSET n (n=O ..... 7)
10+2 n
2
7
-
Clear bit n
BClR n (n=O ..... 7)
11+2 n
2
7
-
0
0
0
0
-
Table 6 Control Instructions
Implied
Function
152
Mnemonic
Op
Code
#
#
Bytes
Cycles
Transfer A to X
TAX
97
1
2
Transfer X to A
TXA
9F
1
2
Set Carry Bit
SEC
99
1
2
Clear Carry Bit
ClC
98
1
2
Set Interrupt Mask· Bit
SEI
9B
1
2
Clear Interrupt Mask Bit
CLI
9A
1
2
Software Interrupt
SWI
83
1
11
Return from Subroutine
RTS
81
1
6
Return from Interrupt
RTI
80
1
9
Reset Stack Pointer
RSP
9C
1
2
No-Operation
NOP
90
1
2
~HITACHI
-----------------------------------------------------------------HD6805S1
Table 7 Instruction Set
Addressing Modes
Mnemonic
Implied
Immediate
Direct
Extended
Relative
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
Bit I Bit
Set/ . Test &
Clear I Branch
ADC
x
x
x
ADD
x
x
x
x
x
AND
x
x
x
x
x
x
x
!
x
x
!
ASL
x
x
x
x
ASR
x
x
I
BEQ
x
x
BHCC
BHCS
x
BHI
x
BHS
x
BIH
x
x
BIL
x
BIT
x
x
x
BLS
x
BMC
x
BMI
x
BMS
x
BNE
x
BPL
x
BRA
x
BRN
x
x
I
x
x
BRSET
x
BSET
x
CLC
x
CLI
x
x
x
CMP
COM
x
x
x
EaR
INC
x
x
x
x
x
x
x
x
CPX
DEC
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
JMP
x
x
x
x
x
JSR
x
x
x
x
x
x
x
x
x
x
x
LOA
x
x
x
LOX
x
x
x
Condition Code Symbols:
H
Half Carry (From Bit 31
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
x
BRCLR
BSR
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
x
BLO
CLR
i
x
x
1\
•
i
BCLR
BCS
I
1\
x
BCC
H
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
a
N
Z
C
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• •
• •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1\
1\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• 1\
• 1\
• •
• •
• a
• •
1 •
• a
• 1\ 1\ 1\
• 1\ 1\ 1
• 1\ 1\ 1\
• 1\ 1\ •
• 1\ 1\ •
• 1\ 1\ •
• • • •
• • • •
• • 1\ 1\ •
• • 1\ 1\ •
(to be continued)
C
1\
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
.
~HITACHI
153
HD6B05S1----------------------------------------------------------------Table 7 Instruction Set
Addressing Modes
Mnemonic
Implied
Immediate
Extended
Relative
LSL
x
x
x
x
LSR
x
x
x
x
NEG
x
x
x
x
NOP
x
x
x
x
x
x
x
x
ROR
x
x
x
x
RSP
x
RTI
x
RTS
x
x
ORA
ROL
x
SBC
SEC
x
SEI
x
x
x
x
x
x
x
x
x
x
x
STX
x
x
x
x
x
x
x
x
x
x
x
SWI
x
TAX
x
TST
x
TXA
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
I nterrupt Mask
N
Negative (Sign Bit)
Z
Zero
x
x
Bit
Set/
Clear
x
STA
SUB
154
D~rect
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
Bit
Test &
Branch
H
?
Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
N
Z
C
•
•
•
•
•
•
•
• /\ /\ /\
• 0 /\ /\
• /\ /\ /\
• • • •
• /\ /\ •
• /\ /\ /\
• /\ /\ /\
• • • • •
?
?
?
?
?
•
•
•
•
•
•
•
• • •
• /\ /\
• • •
1 • •
• /\ /\
• /\ /\
• /\ /\
1 • •
• • •
• /\ /\
• • •
•
•
•
•
•
C
/\
•
I
/\
1
•
•
•
/\
•
•
•
•
-----------------------------------------------------------------HD6805S1
Table 8
Bit Manipulation
Test &
Branch
Clear
0
0
Setl
Opcode Map
Rei
OIR
1
2
3
BRSETO
BSETO
BRA
I
I
A
4
I
X
I
5
I
I
NEG
1
BRClRO
BClRO
BRN
-
2
BRSET1
BSET1
BHI
-
,X1
6
I
:
,XC
IMP
IMP
IMM
I
OIR
I
EXT
7
8
9
A
I
B
1
C
Rn-
-
RTS-
SWI-
3
BRClR1
BClA1
BlS
COM
4
BRSET2
BSET2
BCC
lSA
-
5
BAClA2
BClR2
BCS
-
6
BASET3
BSET3
BNE
AOA
-
7
BRClA3
BClR3
BEQ
ASR
8
9
BRSET4
BSET4
BHCC
lSl/ASl
BRClA4
BClR4
BHCS
A
BRSET5
BSET5
BPl
B BAClA5
~ClA5
C BRSET6
BSET6
Register IMemory
Control
Read/Modify NVrite
Branch
I
E
SUB
I,xo
1
F
+-
1
CPX
3
l
AND
4
o
-
BIT
-
lOA
5 W
6
TAX
-
I
STA(+1)
7
EOR
AOC
8
9
ORA
A
ClC
ROl
-
SEC
DEC
-
CLI
BMI
-
-
SEI
ADD
B
BMC
INC
-
RSP
JMP(-ll
C
JSR(-3)
0
lOX
E
-
I
BSA-I
BMS
TST
-
NOP
-
-
-
F
BClA7
BIH
ClR
1/-
TXA
-
I
112
2/2
I
2/4
2/6
I 1/4
I 1/4
J 2/7 11 /6
HIGH
0
2
Bil
(NOTE)
,X1
SBC
BSET7
2/7
I
CMP
BClR6
3/10
0
-
BRClR6
BAClA7
!
,X2
-
E BASET7
0
I
F
STX(+l1
2/4
I 3/5 I 3/6 I
2/5
I 1/4
1. Undefined opcodes are marked with "_".
2. The number at the bottom of each column denote the number of bytes and the number of cycles required (Bytes/Cycles).
Mnemonics followed by a "-" require a different number of cycles as follows:
RTI
9
RTS
6
SWI
11
BSR
8
3. (
indicate that the number in parenthesis must be added to the cycle count for that instruction.
~HITACHI
155
HD6805S6------·-------MCU (Microcomputer
The HD680SS6 is the 8·bit Microcomputer Unit (MCU)
which contains a CPU, on·chip clock, ROM, RAM, I/O and
timer. It is designed for the user who needs an economical
microcomputer with the proven capabilities of the HD
6800-based instruction set.
The following are some of the hardware and software
highlights of the M CU.
• HARDWARE FEATURES
• 8-Bit Architecture
• 64 Bytes of RAM
• Memory Mapped I/O
• 1804 Bytes of User ROM
• Internal 8-Bit Timer with 7·Bit Prescaler
• 20 TTL/CMOS Compatible I/O Lines;
8 Lines LED Compatible
•
•
•
•
•
On·Chip Clock Circuit
Self-Check Mode
Master Reset
Low Voltage Inhibit
Complete Development System Support by Evaluation kit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
5 Vdc Single Supply
Compatible with MC6805P6
SOFTWARE FEATURES
Similar to HD6800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handing
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM. RAM and I/O
Compatible with MC6805P6
Unit)
-PRELIMINARY-
HD6805S6P
(DP·28)
• PIN ARRANGEMENT
A.
c,
B,
C.
B.
B.
B.
B,
B.
B,
B.
(Top View)
•
BLOCK DIAGRAM
TIMER
8.
8,
cpu
Control
8, Po,.
8,
8
8,
ItO
a, lines
8,
8,
Condition
~
Port
A
5
Regilt ... CC
R..
S
Stack
POinter
cPu
SP
C. Po,t
P'09'_m
Counter
3
··H ...... PCH
P,ogr.m
Counter
"l_" PCl
1804)1 8
ROM
"1')(,1
Sel' checll.
ROM
156
$
HITACHI
C,
C,
AlU
c)
C
ItO
lute.
HD6805S6
• ABSOLUTE MAXIMUM RATINGS
Item
Vee •
Input Voltage (EXCEPT TIMER)
Yin
Input Voltage (TIMER)
•
Value
Symbol
Supply Voltage
,
Unit
-0.3 - +7.0
V
-0.3-+7.0
V
-0.3-+12.0
V
Operating Temperature
Top/"
o -+70
°c
Storage Temperature
Tstg
- 55 - +150
°c
With respect to
(NOTE)
Vss (SYSTEM GND)
Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vcc·5.25V ± O.5V, Vss=GNO, Ta=o-+70°C, unless otherwise noted.)
Item
Input "High" Voltage
Symbol
V
V
Vee
V
V
-0.3
-
0.8
V
-0.3
-
0.6
V
V
3.0
V IH
2.0
Timer Mode
2.0
Self-Check Mode
9.0
-0.3
INT
EXTAL(Crystal Mode)
V IL
max Unit
Vee
INT
RES
Input "Low" Voltage
-
Vee
4.0
All Other
Input "High" Voltage Timer
min typ
Test Condition
RES
Vee
11.0
0.8
V
V
-0.3
-
0.8
-
-
700
Low Voltage Reoover
Po
LVR
-
4.75
V
Low Voltage Inhibit
LVI
-
4.0
-
V
-20
-
20
IJ.A
-50
-
50
IJ.A
-1200
-
0
IJ.A
All Other
Power Dissipation
TIMER
INT
I nput Leak Current
IlL
V in =0.4V-V ee
EXTAL(Crystal Mode)
mW
• AC CHARACTERISTICS (Vcc=5.25V ± O.5V, Vss=GNO, Ta=O - +70°C, unless otherwise noted.)
Symbol
Item
min
T est Condition
typ
max Unit
Clock Frequency
fel
0.4
-
Cycle Time
1.0
-
10
IJ.S
Oscillation Frequency (External Resistor Mode)
teye
f EXT
3.4
-
MHz
INT Pulse Width
tlWL
-
-
ns
RES Pulse Width
tRWL
cSc
2 0
-
-
ns
t cyc +
250
-
-
ns
-
-
100
ms
100
-
-
ms
-
35
-
-
10
pF
pF
t eyc +
250
t
TIMER Pulse Width
tTWL
Oscillation Start-up Time (Crystal Mode)
tose
C L=22pF±20%,
Rs=60n max.
Delay Time Reset
tRHL
External Cap. = 2.2 IJ.F
Input Capacitance
I
I
XTAL
All Other
Cin
-
R ep =15.0kn±1%
Vin=OV
_HITACHI
+
4.0 MHz
157
HD6805S6
• PORT ELECTRICAL CHARACTERISTICS (Vee = 5 25V
min
typ
max
Unit
3.5
2.4
IOH = -200 IJA
2.4
IOH = -1 rnA
1.5
-
'Port C
IOH = -10PIlA
2.4
-
V
IOH = -1001lA
-
Port A and C
IOl = 1.6mA
Symbol
Port A
Output "High" Voltage
Output "Low" Voltage
Port B
Port B
Input "High" Voltage
Input "Low" Voltage
VOH
VOL
Test Condition
IOl = 3.2mA
IOl = 10 mA
VIH
Port A, B, C
Vil
PortA
Input Leak Current
± 0.5V, Vss = GND, Ta = 0"'" +700C , unless otherwise noted)
IOH = -101lA
Item
III
Port B, C
V
-
0.4
V
-
0.4
V
-
1.0
V
2.0
-
Vee
V
-0.3
-
0.8
V
-
IlA
IJA
20
IJA
-500
Yin = 2V
-300
TTL Equiv. (Port B)
V
V
-
Yin = 0.8V
Yin = 0.4V"" Vee
-
V
- 20
TTL Equiv. (Port A and C)
V.cc
2.4kn
1.2kn
li= 1.6mA
Test Point
Test Point
Vi
30 pF
40pF
24 kn
(NOTE) 1. load capacitance includes the floating capacitance of the probe and the jig etc.
2. All diodes are 182074 or equivalent.
Figure 1 Bus Timing Test Loads
• SIGNAL DESCRIPTION
- TIMER
The input and output signals for the MCU, shown in PIN
ARRANGEMENT, are described in the following paragraphs.
This pin allows an external input to be used to decrement
the internal timer circuitry. Refer to TIMER for additional
information about the timer circuitry.
- VCC and VSS
Power is supplied to the MCU using these two pins. VCC is
+5.25 V ± 0.5 V. VSS is the ground connection.
-INT
This pin provides the capability for asynchronously applying
an external interrupt to the MCU. Refer to INTERRUPTS for
additional information.
• XTAL and EXTAL
Tl,ese pins provide connections for the on-chip clock circuit.
A crystal (AT cut, 4 MHz maximum), a resistor or an external
signal can be connected to these pins to provide a system clock
with various stability/cost tradeoffs. Refer to INTERNAL
OSCILLATOR OPTIONS for recommendations about these
inputs.
158
e RES
This pin allows resetting of the MCU at times other than the
automatic resetting capability already in the MCU. Refer to
RESETS for additional information.
eNUM
This pin is' not for user application and should be connected
to VSS .
e Input/Output Lines (Ao '" A7, Bo '" B7, Co '" C3)
These 20 lines are arranged into two 8-bit ports (A and B)
and one 4-bit port (C). All lines are programmable as either
inputs or outputs under software control of the data direction
registers. Refer to INPUT/OUTPUT for additional information.
~HITACHI
HD6805S6
• MEMORY
The MCU memory is configured as shown in Figure 2. During
the processing of an interrupt, the contents of the CPU registers
are pushed onto the stack in the order shown in Figure 3. Since
the stack pointer decrements during pushes, the low order byte
(PCL) of the program counter is stacked first; then the high
order three bits (PCH) are stacked. This ensures that the
program counter is loaded correctly as the stack pointer
increments when it pulls data from the stack: A subroutine call
will cause only the program counter (pCH, PCL) contents to be
pushed onto the stack.
Caution: - Self Test ROM Address Area
Self test ROM locations can not be used for a user program.
If the user's program is in this location, it will be removed when
manufacturing mask for production.
o
7
000
7
$000
I/O Ports
Timer
RAM
(128 Bytes)
127
128
1\
Page Zero
ROM
(128 Bytes)
255
256
Port A
1
Port B
$0 FF
$1 00
1
1923
1924
$7 83
$7 84
Self Check
ROM
(116 Bytes)
2039
2040
1
$000
$001
I
1
0
Port C
$002
3
Not Used
$003
4
Port A DDR
$004*
5
Port BOOR
$005*
1
$006*
Not Used
6
Main
ROM
(1668 Bytes)
1
2
3
0
2
$0 7F
80
4
5
6
Port C DDR
7
Not Used
$007
8
Timer Data Reg
$008
9
Timer CTR L Reg
$009
0
$OQA
Not Used (54 Bytes)
$7 F7
$7 F8
Interrupt
Vectors
ROM
(8 Bytes)
63
6
~
.1'
12
$07F
*Write only registers
$7 FF
2047
$03F
$040
RAM (64 Bytes)
Stack (31 Bytes Maximum)
Figure 2 MCU Memory Configuration
6
n-4
n-3
n-2
'1-1
n
1
5
1
4
3
0
2
Condition
1\ Code Register
n+3
Index Register
PCL*
PCH*
I Accumulator
A
n+1
n+2
Accumulator
1 1 1 1 11
0
Pull
n+4
0
J Index Register
X
10
I
8 7
PCH
0
PCL
10
5 4
101010 101 111
n+5
I
I
Program Counter
0
SP
Stack Pointer
Condition Code Register
Push
* For subroutine calls, only PCH and PCL are stacked.
Carry/Borrow
Figure 3 Interrupt Stacking Order
Zero
' - - - - - ~ Negative
Interrupt Mask
Half Carry
Figure 4 Programming Model
~HITACHI
159
HD6805S6--------------------------------------------------------------•
Half Carry (H)
REGISTERS
The CPU has five registers available to the programmer.
They are shown in Figure 4 and are explained in the following
paragraphs.
Used during arithmetic operations (ADD and ADC) to
indicate that a carry occurred between bits 3 and 4.
•
This bit is set to mask the timer and external interrupt (INT).
If an interrupt occurs while this bit is set it is latched and will be
processed as soon as the interrupt bit is reset.
Accumulator (A)
The accumulator is a general purpose 8-bit register used to
hold operands and results of aritlunetic calculations or data
manipulations.
•
Index Register (X)
The index register is an 8-bit register used for the indexed
addressing mode. It contains an 8-bit address that may be added
to an offset value to create an effective address. The index
register can also be used for limited calculations and data
manipulations when using read/modify/write instructions. When
not required by a code sequence being executed, the index
register can be used as a temporary storage area.
•
Program Counter (PC)
The program counter is an II-bit register that contains the
address of the next instruction to be executed.
•
Stack Pointer (SP)
The stack pointer is an II-bit register that contains the
address of the next free location on the stack. Initially, the
stack pointer is set to location $07F and is decremented as data
is being pushed onto the stack and incremented as data is being
pulled from the stack. The six most significant bits of the stack
pointer are permanently set to 000011. During a MCU reset or
the reset stack pointer (RSP) instruction, the stack pointer is set
to location $07F. Subroutines and interrupts may be nested
down to location $061 which allows the programmer to use up
to 15 levels of subroutine calls.
•
Condition Code Register (CC)
The condition code register is a 5-bit register in which each
bit is used to indicate or flag the results of the instruction just
executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each
individual condition code register bit is explained in the
following paragraphs.
Interrupt (I)
Negative (N)
Used to indicate that the result of the last arithmetic, logical
or data manipulation was negative (bit 7 in result equal to a
logical one).
Zero (Z)
Used to indicate that the result of the last aritlunetic, logical
or data manipulation was zero.
Carry/Borrow (C)
Used to indicate that a carry or borrow out of the aritlunetic
logic unit (ALU) occurred during the last aritlunetic operation.
This bit is also affected during bit test and branch instructions,
shifts, and rotates.
•
TIMER
The MCU timer circuitry is shown in Figure 5. The 8-bit
counter, the Timer Data Register (TOR), is loaded under program control and counts down toward zero as soon as the clock
input is applied. When the timer reaches zero, the timer interrupt request bit (bit 7) in the Timer Control Register (TCR), is
set. The CPU responds to this interrupt by saving the present
CPU state on the stack, fetching the timer interrupt vector from
locations $7F8 and $7F9 and executing the interrupt routine.
The timer interrupt can be maksed by setting the timer interrupt mask bit (bit 6) in the TCR. The interrupt bit (I bit) in the
Condition Code Register also prevents a timer interrupt from
being processed.
The clock tnput to the timer can be from an external source
applied to the TIMER input pin or it can be the internal 2
signal. When the 2 signal is used as the source, it can be gated
by an input applied to the TIMER input pin allowing the user
rP2
(Internal)
TI R; Timer Interrupt Request
TIM; Timer Interrupt Mask
Timer
Input
Pin
r-----.,
I
I
I
I
I
I
L
I _____ .II
Manufacturing
Mask Options
Write
Read
Figure 5 Timer Block Diagram
160
~HITACHI
Write
Read
---------------------------------------------------------------HD6805S6
to easily perform pulse-width measurements. The TIMER input
pin must be tied to Vee, for ungated tP2 clock input to the
timer prescaler. The source of the clock input is one of the
options that has to be specified before manufacture of the
MeV. A prescaler option can be applied to the clock input that
extends the timing interval up to a maximum of 128 counts
before decrementing the counter (TOR). The timer continues
to count past zero, falling through to $FF from zero, and then
continuing the count. Thus, the counter can be read at any
time by reading the TOR. This allows a program to determine
the length of time since a timer interrupt has occurred and
not disturb the counting process.
At power-up or reset, the prescaler and counter are initialized
with all logical ones; the timer interrupt request bit (bit 7) is
cleared, and the timer interrupt mask bit (bit 6) is set.
(NOTE) If the MeV Timer is not used, the TIMER input pin
must be grounded.
2
• SELF CHECK
The self-check capability of the MeU provides an internal
check to determine if the part is functional. Connect the MCV
as shown in Figure 6 and monitor the output of port C bit 3
for an oscillation of approximately 3Hz.
• RESETS
The MCV can be reset three ways: by initial power-up, by
the external reset input (RES) and by an optional internal low
voltage detect circuit, see Figure 7. All the I/O port are initialized to Input mode (DOR's are cleared) during RESET.
During power-up, a minimum of 100 milliseconds is needed
before allowing the RES input to go "High".
This time allows the internal crystal oscillator to stabilize.
Connecting a capacitor to the RES input, as shown in Figure 8,
typically provides sufficient delay.
iNT
A, 27
A. 26
'*
28 RES
As 25
A.24
2.2I'F
5 XTAL
A, 23
A, 22
4
EXTAL
A, 21
Ao 20
TIMER
+9V
HD6805~6
(Resistor option)"
B, 19
6
NUM
Vee
B. 18
Bs 17
B. 16
8
Co
B3 15
9
C,
B, 14
10 C,
B, 13
11 C 3
Bo 12
Vee = Pin 3
Vss = Pin 1
• Refer to Figure 9 about crystal option
Figure 6 Self Check Connections
REs
Pin
Internal
Reset
-------.f'
------------------~
Figure 7 Power Up and RES Timing
~HITACHI
161
HD6805S6------------------------------------------------------------• INTERNAL OSCILLATOR OPTIONS
The internal oscillator circuit is designed to require a minimum of external components. A crystal, a resistor, a jumper
wire, or an external signal may be used to generate a system
clock with various stability/cost tradeoff. A manufacturing
mask option is required to select either the crystal oscillator
or the RC oscillator circuit. The different connection methods
are shown in Figure 9. Crystal specifications are given in Figure
10. A resistor selection graph is given in Figure 11.
28
RES
Part of
HD6805S6
MCU
Figure 8 Power Up Reset Delay Circuit
5 XTAL
5 XTAL
4~:XZ c::J
4 EXTAL
4 EXTAL
HD6805S6
MCU
HD6805S6
MCU
22PF±20%=;::t;
ApproximatelV 25% Accuracy
External: Jumper
5 XTAL
5 XTAL
R
External
Clock
Input
4 EXTAL
HD6805S6
MCU
4 EXTAL
HD~~~5S6
No
Connection
External Clock
Approximately 15% Accuracy
External Resistor
CRYSTAL OPTIONS
RESISTOR OPTIONS
Figure 9 Internal Oscillator Options
5
C.
\
4
EXTAL
4
N
:r
~
~
3
11-
\~
\
I:
Q)
~
AT - Cut Parallel Resonance Crystal
Co = 7 pF max.
f = 4 MHz (e. =22pF±20%1
Rs = 60n max.
0-
f
u..
Vee = 5~25V_
TA = 25 C
2
~
"-~
Figure 10 Crystal Parameters
o
5
10
15
20
25
30
Resistance (knl
"
35
~
40
Figure 11 Typical Resistor Selection Graph
162
~HITACHI
'-
45
50
-------------------------------------------------------------HD6805S6
1-1
$7F -SP
o -DDR's
CLR 1NT Logic
$FF -Timer
$7F _ Prescaler
$7F _ TCR
Stack
PC,X,A,CC
TIMER
Load PC From
SW I: $7FC, $7FD
INT: $7FA, $7FB
TIMER: $7F8, $7F9
Load PC From
Reset: $7FE, $7FF
Fetch
Instruction
SWI
Y
Execute
Instruction
Figure 12 Interrupt Processing Flowchart
Data
Direction
Register
Bit
Output
Data Bit
Output
State
Input to
MCU
o
o
o
x
3-State
Pin
1
Figure 13 Typical Port I/O Circuitry
~HITACHI
o
163
HD6805S6--------------------------------------------------------------•
INTERRUPTS
The CPU can be interrupted three different ways: through
the external interrupt (iN'i') input pin, the internal timer
interrupt request, and a software interrupt instruction (SWI).
When any interrupt occurs, processing is suspended, the present
CPU state is pushed onto the stack, the interrupt bit (I) in the
Condition Code Register is set, the address of the interrupt
routine is obtained from the appropriate interrupt vector
address, and the interrupt routine is executed. The interrupt
service routines normally end with a return from interrupt
(RTI) instruction which allows the CPU to resume processing
of the program prior to the interrupt. Table 1 provides a listing
of the interrupts, their priority, and the vector address that
contain-the starting address of the appropriate interrupt routine.
A flowchart of the interrupt processing sequence is given in
Figure 12.
Table 1 Interrupt Priorities
Interrupt
Priority
Vector Address
RES
SWI
INT
TIMER
1
$7FE and $7FF
$7FC and $7FD
$7FA and $7FB
$7F8 and $7F9
2
3
4
•
INPUT/OUTPUT
There are 20 input/output pins. All pins are programmable
as either inputs or outputs under software control of the corresponding data direction register (DDR). When programmed as
outputs, the latched output data is readable as input data,
regardless of the logic levels at the output pin due to output
loading (see Figure 13). When port B is programmed for outputs, it is capable of sinking IO rnA on each pin (VOL = IV
max). All input/output lines are TTL compatible as both inputs
and outputs. Port A are CMOS compatible as outputs, and
Port Band C are CMOS compatible as inputs. Figure 14 provides some examples of port connections.
•
BIT MANIPULATION
The MCV has the ability to set or clear any single random
access memory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines. The example in Figure 15
illustrates the usefulness of the bit manipulation and test
instructions. Assume that bit 0 of port A is connected to a zero
crossing detector circuit and that bit 1 of port A is connected to
the trigger of a TRIAC which powers the controlled hardware.
This program, which uses only seven ROM locations,
provides turn-on of the TRIAC within 14 microseconds of the
zero crossing. The timer could also be incorporated to provide
turn-on at some later time which would permit pulse-width
modulation of the controlled power.
Ao
····
··
Port A
Port B
A,
B,
Port A ?rogrammed as output(s), driving CMOS and TTL Load directly,
Port B Programmed as output(s), driving Darlington base directly.
(a)
(b)
+V
+V
R
R
-
Port B
Port C
10 mA max
B,
1 - - - -....-.. CMOS Inverter
C,
Port B Programmed as output(s), driving LED(s)' directly_
(e)
Port C Programmed as output(s), driving CMOS loads, using external
pull-Up resistors.
(d)
Figure 14 Typical Port Connections
164
···
··
~HITACHI
-----------------------------------------------------------------HD6805S6
SELF 1
··
··
BRCLR 0, PORT A, SELF 1
BSET 1, PORT A
BClR 1, PORT A
Figure 15 Bit Manipulation Example
• ADDRESSING MODES
The CPU has ten addressing modes available for use by the
programmer. They are explained and illustrated briefly in the
following paragraphs.
• Immediate
Refer to Figure 16. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte following the
opcode.
• Direct
Refer to Figure 17. In direct addressing, the address of the
operand is contained in the second byte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. All RAM space, I/O registers and 128
bytes of ROM are located in page zero to take advantage of this
efficient memory addressing mode.
• Extended
Refer to Figure 18. Extended addressing is used to reference
any location in memory space. The EA is the contents of the
two bytes following the opcode. Extended addressing instructions are three bytes long.
• Relative
Refer to Figure 19. The relative addressing mode applies only
to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA=(pC)+2+Rel. ReI is the contents
of the location following the instruction opcode with bit 7
being the sign bit. If the branch is not taken Rel=O, when a
branch takes place, the program goes to somewhere within the
range of + 129 bytes to -127 of the present instruction. These
instructions are two bytes long.
• Indexed (No Offset)
Refer to Figure 20. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and'their EA is the contents of the index register.
• Indexed (8-bit Offset)
Refer to Figure 21. The EA is calculated by adding the
contents of the byte following the opcode to the contents of
the index register. In this mode, 511 low memory locations are
acce~sable. These instructions occupy two bytes.
• Indexed (16-bit Offset)
Refer to Figure 22. This addressing mode calculates the EA
by adding the contents of the two bytes following the opcode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are three
bytes long.
• Bit Set/Clear
Refer to Figure 23. This mode of addressing applies to
instructions which can set or clear any bit on page zero. The
lower three bits in the opcode specify the bit to be set or
cleared while the byte following the opcode specifies the
address in page zero.
• Bit Test and Branch
Refer to Figure 24. This mode of addressing applies to
instructions which can test any bit in the first 256 locations
($OO-$FF) and branch to any location relative to the PC. The
byte to be tested is addressed by the byte following the opcode.
The individual bit within that byte to be tested is addressed by
the lower three bits of the opcode. The third byte is the relative
address to be added to the program counter if the branch condition is met. These instructions are three bytes long. The value of
the bit tested is written to the carry bit in the condition code
register.
• Implied
Refer to Figure 25. The implied mode of addressing has no
EA. All the information necessary to execute an instruction is
contained in the opcode. Direct operations on the accumulator
and the index register are included in this mode of addressing.
In addition, control instructions such as SWI, RTI belong to this
group. All implied addressing instructions are one byte long.
• INSTRUCTION SET
The MCU has a set of 59 basic instructions. They can be
divided into five different types: register/memory, read/modify/
write, branch, bit manipulation, and control. The following
paragraphs briefly explain each type. All the instructions within
a given type are presented in individual tables.
• Register/Memory Instructions
Most of these instructions use two operands. One operand is
either the accumulator or the index register. The other operand
is obtained from memory' using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR)
instructions have no register operand. Refer to Table 2.
• Read/Modify/Write Instructions
These instructions read a memory location or a register,
modify or test its contents, and write the modified value back
to memory or to the register. The test for negative or zero
(TST) instruction is an exception to the read/modify/write
instructions since it does not perform the write. Refer to Table
3.
• Branch Instructions
The branch instructions cause a branch from the program
when a certain condition is met. Refer to Table 4.
• Bit Manipulation Instructions
These instructions are used on any bit in the first 256 bytes
of the memory. One group either sets or clears. The other group
performs the bit test and branch operations. Refer to Table 5.
• Control Instructions
The control instructions control the MCU operations during
program execution. Refer to Table 6.
• Alphabetical Listing
The complete instruction set is given in alphabetical order in
Table 7.
• Opcode Map
Table 8 is an opcode map for the instructions used on the
MCU.
~HITACHI
165
HD6805S6------------------------------------------------------------------
Memory
I
~
I
Stack Point
I
I
PROG LOA #$F8 05BE
05BF
A6
Prog Count
F8
05CO
I------t
CC
I
I
~
I
I
I
I
Figure 16 Immediate Addressing Example
lEA
,
Melory
I
I
CAT
FCB
32
,,,
,,
i
••,
L
/'
J
Adder
20
OO4B
I
004B
~
Jo
A
-,-,
20
I
Index Reg
PROG
LOA
CAT
I
I
I
0520
B6
052E
4B
Stack Point
I
I
I
~.
•
I
,
:,
I
Figure 17 Direct Addressing Example
166
~HITACHI
I
Prog Count
052F
CC
,
,,
I
I
---------------------------------------------------------------HD6805S6
Memory
i
I
I
I
I
~
PROG
LOA
CAT
FCB
64
A
~oo~ J
040A
06
040B
ES
•I
CAT
0000
40
Index Reg
Stack Point
I
•
Prog Count
040C
40
06ES
CC
Figure 18 Extended Addressing Example
Memory
i
I
§
PROG
BEQ
PROG2
04A 7
A
Index Reg
Stack Point
I
I
0000
27
1---------1
04A8
18
§
I,
I,
Figure 19 Relative Addressing Example
~HITACHI
167
HD6805S6----------------------------------------------------_________
Memory
A
TABL
FCC
t LIt 00B8
4C
4C
49
Index Reg
B8
I
PROG
LOA
X
I
Stack Point
05F4~
Prog Count
05F5
CC
§
,I
Figure 20 Indexed (No Offset) Addressing Example
lEA
Melory
i
,
I
TABL
PROG
i
FeB
#BF
0089
BF
FCB
#86
008A
86
FCB
#OB
008B
DB
FCB
#CF
008C
CF
LOA
,I
I
I
075C
89
t
Adder
~
A
I
I
I
E6
/
I
008C
_J
I
TABL. X 075B
I
CF
1
Index Reg
r
03
I
Stack Point
I
I
I
Prog Count
I
0750
CC
I
I
@
I
,
I
,
Figure 21
168
Indexed (S-Bit Offset) Addressing Example
~HITACHI
I
-----------------------------------------------------------------HD6805S6
lEA
Melory
i
i
i
I
~
~
I
LOA TABL. X 0692
0693
0694
/
Adder
~
~
I
~
J
BF
FCB
#86
077F
86
FCB
#OB
0780
DB
FCB
#CF
0781
CF
02
I
I
Stack Point
I
I
I
I
I
Prog Count
0695
CC
I
077E
J
Index Reg
07
#BF
DB
I
7E
FCB
A
J
I
I
TABL
0780
I
I
PROG
I
I
I
Figure 22 Indexed (16-Bit Offset) Addressing Example
Memory
PORT B
EQU
BF
0001
A
0000
Index Reg
PROG BClR 6. PORT B
058F
0590
10
Stack Point
I-------t
01
Prog Count
0591
•
I
CC
§@
i
I
I
Figure 23 Bit Set/Clear Addressing Example
~HITACHI
169
HD6805S6---------------------------------------------------------------
PORT C
EQU
2
0002
A
FO
Index Reg
Stack Point
PROG BRCLR 2. PORT C. PROG 2
0574
0575
05
Prog Count
1-------1
0000
02
05761---;1~D~-14--...,
0594
CC
C
Figure 24 Bit Test and Branch Addressing Example
Memory
i
I
I
I
i
~
A
E5
Index Reg
I
I
PROG
TAX
E5
I
I
O~A8
Prog Count
0588
CC
I
i
I
I
§
Figure 25
170
Implied Addressing Example
$
HITACHI
----------------------------------------------------------------HD6805S6
Table 2 Register/Memory Instructions
Addressing Modes
Function
Mnemonic
Immediate
Direct
Op
Op
#
#
#
#
Op
Code Bytes Cycles Code Bytes Cycles Code
Indexed
(8·Bit Offset)
Indexed
(No Offset)
Extended
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(16·Bit Offset)
#
Op
#
Bytes Cycles Code
E6
2
5
D6
#
#
Bytes Cycles
Load A from Memory
LOA
A6
2
2
B6
2
4
C6
3_
5
F6
1
4
3
6
Load X from Memory
LDX
AE
2
2
BE
2
4
CE
3
5
FE
1
4
EE
2
5
DE
3
6
Store A in Memory
STA
B7
2
5
C7
3
6
F7
1
5
E7
2
6
D7
3
7
STX
-
-
Store X in Memory
-
-
BF
2
5
CF
3
6
FF
1
5
EF
2
6
DF
3
7
Add Memory to A
ADD
AB
2
2
BB
2
4
CB
3
5
FB
1
4
EB
2
5
DB
3
6
Add Memory and
Carry to A
ADC
A9
2
2
B9
2
4
C9
3
5
F9
1
4
E9
2
5
D9
3
6
Subtract Memory
SUB
AO
2
2
BO
2
4
CO
3
5
FO
1
4
EO
2
5
DO
3
6
Subtract Memory from
A with Borrow
SBC
A2
2
2
B2
2
4
C2
3
5
F2
1
4
E2
2
5
D2
3
6
AND Memory to A
AND
A4
2
2
B4
2
4
C4
3
5
F4
1
4
E4
2
5
D4
3
6
OR Memory with A
ORA
AA
2
2
BA
2
4
CA
3
5
FA
1
4
EA
2
5
DA
3
6
E8
2
5
D8
3
6
Exclusive OR Memory
with A
EOR
A8
2
2
B8
5
F8
1
4
3
5
F1
1
4
E1
2
5
D1
3
6
C3
3
5
F3
1
4
E3
2
5
D3
3
6
4
C5
3
5
F5
1
4
E5
2
5
D5
3
6
2
3
CC
3
4
FC
1
3
EC
2
4
DC
3
5
2
7
CD
3
8
FD
1
7
ED
2
8
DD
3
9
4
2
C8
Arithmetic Compare A
with Memory
·CMP
A1
2
2
B1
2
4
C1
Arithmetic Compare X
with Memory
CPX
A3
2
2
B3
2
4
Bit Test Memory with A
(Logical Compare)
BIT
A5
2
2
B5
2
Jump Unconditional
JMP
-
BC
JSR
-
-
Jump to Subroutine
-
,BD
3
Table 3 Read/Modify/Write Instructions
Addressing Modes
Function
Implied (X)
Implied (A)
Mnemonic
Op
Code
Op
#
#
Bytes Cycles Code
Indexed
(No Offset)
Direct
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(8·Bit Offset)
Op
#
#
Bytes Cycles Code
#
#
Bytes Cycles
Increment
INC
4C
1
4
5C
1
4
3C
2
6
7C
1
6
6C
2
7
Decrement
DEC
4A
1
4
5A
1
4
3A
2
6
7A
1
6
6A
2
7
Clear
CLR
4F
1
4
5F
1
4
3F
2
6
7F
1
6
6F
2
7
Complement
COM
43
1
4
53
1
4
33
2
6
73
1
6
63
2
7
Negate
(2's Complement)
NEG
40
1
4
50
1
4
30
2
6
70
1
6
60
2
7
Rotate Left Thru Carry
ROL
49
1
4
59
1
4
39
2
6
79
1
6
69
2
7
Rotate Right Thru Carry
ROR
46
1
4
56
1
4
36
2
6
76
1
6
66
2
7
7
Logical Shift Left
LSL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
Logical Shift Right
LSR
44
1
4
54
1
4
34
2
6
74
1
6
64
2
7
Arithmetic Shift Right
ASR
47
1
4
57
1
4
37
2
6
77
1
6
67
2
7
Arithmetic Shift Left
ASL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
Test for Negative or
Zero
TST
40
1
4
50
1
4
3D
2
6
70
1
6
60
2
7
~HITACHI
171
HD6805S6--------------------------------------------------------_______
Table 4 Branch Instructions
Relative Addressing Mode
Mnemonic
Function
Op
Code
#
#
Bytes
Cycles
Branch Always
BRA
20
2
4
Branch Never
BRN
21
2
4
Branch I F Higher
BHI
22
2
4
Branch I F lower or Same
BlS
23
2
4
Branch I F Carry Clear
BCC
24
2
4
(Branch IF Higher or Same)
(BHS)
24
2
4
Branch I F Carry Set
BCS
25
2
4
(Branch IF lower)
(BlO)
25
2
4
Branch I F Not Equal
BNE
26
2
4
Branch IF Equal
BEQ
27
2
4
4
Branch I F Half Carry Clear
BHCC
28
2
Branch I F Half Carry Set
BHCS
29
2
4
Branch I F Plus
BPl
2A
2
4
Branch IF Minus
BMI
2B
2
4
Branch IF Interrupt Mask Bit is Clear
BMC
2C
2
4
Branch I F Interrupt Mask Bit is Set
BMS
20
2
4
Branch IF Interrupt line is low
Bil
2E
2
4
Branch IF Interrupt Line is High
BIH
2F
2
4
Branch to Subroutine
BSR
AO
2
8
Table 5 Bit Manipulation Instructions
Addressing Modes
Function
Mnemonic
Bit Set/Clear
Branch IF Bit n is set
BRSET n (n=O ..... 7)
Branch I F Bit n is clear
BRClR n (n=O ..... 7)
Set Bit n
BSET n (n=O ..... 7)
Clear bit n
BClR n (n=O ..... 7)
Bit Test and Branch
#
#
Bytes
Cycles
-
-
-
10+2 0n
11+2 0n
2
7
-
2
7
-
Op
Code
Op
Code
20n
01+2 0n
#
#
Bytes
Cycles
3
10
3
10
-
-
-
Table 6 Control Instructions
Implied
Function
172
Mnemonic
Op
Code
#
#
Bytes
Cycles
Transfer A to X
TAX
97
1
2
Transfer X to A
TXA
9F
1
2
Set Carry Bit
SEC
99
1
2
Clear Carry Bit
ClC
98
1
2
Set Interrupt Mask Bit
SEI
9B
1
2
Clear Interrupt Mask Bit
CLI
9A
1
2
Software Interrupt
SWI
83
1
11
Return from Subroutine
RTS
81
1
6
Return from Interrupt
RTI
80
1
9
Reset Stack Pointer
RSP
9C
1
2
No-Operation
NOP
90
1
2
$
HITACHI
-------------------------------------------------------------HD6805S6
Table 7 I nstruction Set
Addressing Modes
Mnemonic
Implied
Immediate
Direct
Extended
Relative
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
Bit
Set/
Clear
Bit
Test &
Branch
H
I
N
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1\
1\
1\
1\
1\
1\
1\
1\
1\
•
1\
1\
1\
1\
1\
ADC
x
x
x
x
x
x
/\
ADD
x
x
x
x
x
x
/\
AND
x
x
x
x
x
x
•
ASL
x
x
x
x
ASR
x
x
x
x
•
•
•
•
x
BCC
x
BCLR
BCS
x
BEQ
x
x
BHCC
BHCS
x
BHI
x
x
x
x
BHS
BIH
BIL
x
BIT
x
x
•
•
•
•
•
•
x
x
•
•
•
x
•
•
x
x
BLO
BLS
BMC
x
BMI
x
x
BMS
BNE
x
BPL
x
BRA
x
BRN
x
BRCLR
x
BRSET
x
x
BSET
x
BSR
CLC
CLI
CLR
COM
DEC
x
x
x
x
x
x
CPX
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
EOR
x
x
x
x
x
x
x
JMP
x
x
x
x
x
JSR
x
x
x
x
x
x
x
x
x
x
x
INC
•
•
•
•
•
•
•
•
•
•
• •
• •
x
x
x
CMP
•
•
•
•
•
•
•
•
•
•
x
x
LDA
x
x
x
LDX
x
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
1\ 1\ •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • 1\
• • 1\
• • •
• • •
• • 0
• • •
0
1
•
1\
1\
1\
1\
1\
1
1\
1\
1\
•
•
• 1\ 1\ •
• • • •
• • • •
• 1\ 1\ •
• 1\ 1\ •
1\
1\
1\
1\
(to be continued)
C
1\
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
~HITACHI
173
HD6805S6--------------------------------------------------------------Table 7 Instruction Set
Addressing Modes
Mnemonic
LSL
LSR
NEG
NOP
Implied
Immediate
x
x
x
x
x
ORA
Direct
x
x
x
x
x
x
x
x
x
x
x
x
x
x
ROL
x
x
x
x
RSP
x
x
x
RTS
x
SBC
SEC
SEI
tended
Condition Code
R ----, Indexed
Indexed Indexed
e(No
lative Offset) (8 Bits) (16 Bits)
x
ROR
RTI
x
x
x
x
x
x
x
x
x
STX
x
x
x
x
x
x
x
x
x
x
x
x
x
x
TAX
TST
TXA
x
x
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
Bit
Test &
Branch
·.
·.
H
I
•
•
x
Z
C
/\
/\
/\
0/\/\
/\ /\ /\
..
• • • • •
·• .• • • •
/\
/\/\
?
?
?
?
?
/\
/\
/\
•
•
•
•
1
•
1
•••
·.
•
x
N
• • • • •
x
STA
SWI
Bit
Set!
Clear
x
x
SUB
174
Ex-
1
/\
/\
/\
•
•
•
• • • • •
x
• • • • •
C
/\
•
?
Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
---------------------------------------------------------------HD6805S6
Table 8
Bit Manipulation
Opcode Map
Set/
Clear
Rei
DIR
0
1
2
3
0
BRSETO
BSETO
BRA
1 J
A
I
4
X
I
5
NEG
1
BRCLRO
BCLRO
BRN
-
2
BRSET1
BSETl
BHI
-
I
1
,Xl
6
Register /Memory
Control
Read/Modify!Write
Branch
Test &
Branch
I
J
,XO
7
IMP
IMM
8
9
A
RTI*
-
IMP
RTS*
-
I DIR I EXT I ,X2 I )<1 l,xo
I
B
I
C
I
D
I
E
I
F
SUB
+-
HIGH
0
-
CMP
1
-
SBC
2
3
BRCLR1
BCLRl
BLS
COM
-
CPX
3
L
4
BRSET2
BSET2
BCC
LSR
-
-
AND
4
o
5 W
SWI*
5
BRCLR2
BCLR2
BCS
-
-
-
BIT
6
BRSET3
BSET3
BNE
ROR
-
-
LDA
6
7
BRCLR3
BCLR3
BEQ
ASR
-
TAX
STA(+l)
7
8
9
BRSET4
BSET4
BHCC
LSL/ASL
-
CLC
EOR
BRCLR4
BCLR4
BHCS
ROL
-
SEC
ADC
8
9
DEC
-
CLI
ORA
A
SEI
ADD
B
INC
TST
-
NOP
BRSET5
BSET5
BPL
B
BRCLR5
~CLR5
BMI
-
C BRSET6
BSET6
BMC
D
BCLR6
BMS
RSP
BSR*
E BRSET7
BSET7
BIL
-
-
-
F BRCLR7
BCLR7
BIH
CLR
-
TXA
-
1/·
1/2
2/2
3/10
(NOTE)
2/7
2/4
2/6
I 1/4 I
I
-
A
BRCLR6
-
1/4
I 2/7 I 1/6
1
JMP(-lI
C
L
JSR(-3)
D
LOX
E
1
STX(+l)
F
l
2/4
I
3/5
I
3/6
I
2/5
I 1/4
1. Undefined opcodes are marked with "-".
2. The number at the bottom of each column denote the number of bytes and the number of cycles required (Bytes/Cycles).
Mnemonics followed by a "." require a different number of cycles as follows:
RTI
9
RTS
6
SWill
BSR
8
3. (
indicate that the number in parenthesis must be added to the cycle count for that instruction.
~HITACHI
175
HD6805U1
MCU (Microcomputer
Unit)
The HD6805Ul is the 8-bit Microcomputer Unit (MCU)
which contains a CPU, on·chip clock, ROM, RAM, I/O and
timer. It is designed for the user who needs an economical
microcomputer with the proven capabilities of the HD6800·
based instruction set.
The fonowing are some of the hardware and software high·
lights of the MCU.
HD6805U1P
• HARDWARE FEATURES
• 8-Bit Architecture
• 96 Bytes of RAM
• Memory Mapped I/O
• 2056 Bytes of User ROM
• Internal 8-Bit Timer with 7-Bit Prescaler
• Vectored Interrupts - External and Timer
• 24 I/O Ports + 8 Input Port
(8 Lines LED Compatible, 7 Bits Comparator Inputs),
• On·Chip Clock Circuit
• Self·Check Mode
• Master Reset
• Low Voltage Inhibit
• Complete Development System Support by Evaluation Kit
• 5 Vdc Single Supply
(DP·40)
•
• SOFTWARE FEATURES
• Similar to HD6800
• Byte Efficient Instruction Set
• Easy to Program
• True Bit Manipulation
• Bit Test and Branch Instructions
• Versatile Interrupt Handing
• Powerful Indexed Addressing for Tables
• Full Set of Conditional Branches
• Memory Usable as Registers/Flags
• Single Instruction Memory Examine/Change
• 10 Powerful Addressing Modes
• All Addressing Modes Apply to ROM, RAM and I/O
Compatible Instruction Set with MC6805P2
•
PIN ARRANGEMENT
o
c,
HD6805U1
C3
BLOCK DIAGRAM
c.
Cs
TIMER
C,
C7
0,
Os
CPU
o.
Control
Cond.tlon
POrt
D•••
A
0.,
Ret
R~
S
COd.
ReVISIt' CC
(Top View)
CPu
c,
C,
Progr.m
OIt.
Port
Counter
0.,
C
"Hie"" peH
R.g
R~
Pr09,.m
Counllf
C2
C,
g:
Pol'1
C
LI,~~
C,
C,
"Low" pel
0,
0,
0, Port
0,
°
D.
InpUt
0,
LIn"
O.
O,IVTH
176
eHITACHI
-------------------------.,r·----------------------------------HD6805Ul
• ABSOLUTE MAXIMUM RATINGS
Vee *
Input Voltage (EXCEPT TIMER)
V in *
Input Voltage (TIMER)
Unit
Value
Symbol
Item
Supply Voltage
-0.3- +7.0
V
-0.3- +7.0
V
-0.3 -+12.0
V
°c
°c
Operating Temperature
T opr
o -+70
Storage Temperature
T stll
- 55 - +150
* With respect to Vss (SYSTEM GNDI
(NOTE I
Permanent lSI damage may occur if maximum ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions are exceeded, it could affect reliability of lSI.
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vcc·5.25V ± 0.5V, Vss=GNO, Ta"o-+70°C, unless otherwise noted.)
Item
Input "High" Voltage
Symbol
min typ
-
Vee
V
INT
3.0
-
Vee
V
2.0
-
Vee
V
V
-
11.0
V
0.8
V
V IH
Timer Mode
2.0
Self·Check Mode
9.0
RES
-0.3
INT
Input "Low" Voltage
V IL
EXTAL(Crystal Mode)
All Other
Power Dissipation
Low Voltage Recover
Low Voltage Inhibit
LVI
-0.3
-
0.8
V
-
0.6
0.8
V
V
-
TIMER
V in =0.4V-V ee
IlL
700
V
4.0
-
V
-
20
IJ.A
50
IJ.A
0
IJ.A
-50
-1200 -
EXT ALtCrystal Mode)
mW
4.75
-20
INT
Vee
-0.3
-0.3
Po
LVR
I nput Leak Current
max Unit
4.0
All Other
Input "High" Voltage Timer
Test Condition
RES
• AC CHARACTERISTICS (Vcc=5.25V ± O.5V, Vss=GNO, Ta=O - +10°C, unless otherwise noted.)
Item
min
typ
Clock Frequency
fel
0.4
4.0 MHz
Cycle Time
1.0
10
IJ.s
Oscillation Frequency (External Resistor Mode)
teyc
f EXT
-
-
3.4
-
MHz
TNT Pulse Width
t lWL
t eye +
250
-
-
ns
RES Pulse Width
tRWL
t cvc +
250
-
I -
ns
TIMER Pulse Width
t TWL
t cvc +
250
-
-
ns
Oscillation Start·up Time (Crystal Mode)
tose
-
-
100
ms
Delay Time Reset
tRHL
-
ms
35
pF
pF
Input Capacitance
i
I
Symbol
XTAL
All Other
Cin
Test Condition
R ep =15.0kSH1%
C L=22pF±20%,
Rs =60n max.
External Cap. = 2.2 IJ.F
Vin=OV
~HITACHI
100
-
~
-
max Unit
i
10
177
HD6805U1--------------------------------------------------------------• PORT ELECTRICAL CHARACTERISTICS (Vee = 5.25V ± 0.5V, Vss = GNO, Ta = 0"" +70°C, unless otherwise noted.)
typ
max
Unit
Symbol
Test Condition
min
Item
Port A
Output "High" Voltage
Port
VOH
e
Port C
Port A and C
·Output "Low" Voltage
Input "High" Voltage
Input "Low" Voltage
Port
VOL
e
Port A,
and 0*
e, C,
3.5
-
IOH
2.4
-
2.4
1.5
-
O.~
V
-
0.4
V
-
1.0
V
Vee
V
0.8
V
pA
-300
-
- 20
-
20
= -10pA
= -l00pA
IOH = -200 pA
IOH = -1 mA
IOH = -100pA
IOL = 1.6mA
IOL = 3.2 mA
IOL = 10mA
2.4
-
VIH
2.0
-0.3
VIL
= 0.8V
Vin = 2V
-500
Vin
Port A
Input Leak Current
IlL
Port e, C,
and 0
Port 0**
(Do"" 0 6 )
-
IOH
Vin
= 0.4V"" Vee
-
V
V
V
V
V
pA
pA
VIH
-
VTH+0.2
-
V
Input "Low" Voltage
Port 0**
(OJl .... 0 6 )
VIL
-
VTwO.2
-
V
Threshold Voltage
Port 0**(0,)
VTH
0
0. 8xV ce
V
Input "High" Voltage
.. Input
* Port 0 as digital
-
** Port 0 as analog input
TTL Equiv. (Port A and C)
TTL Equiv. (Port e)
Vee
Vee
Ii = 3.2 rnA
1.2kn
Ii
Test Point
Test Point
= 1.6 rnA
2.4kH
Vi
40pF
(NOTE)
30 pF
12 kn
24 kn
1. Load capacitance includes the floating capacitance of the probe and the jig etc.
2. All diodes are 1520748 or equivalent.
Figure 1 Bus Timing Test Loads
• SIGNAL DESCRIPTION
The input and output signals for the MCV, shown in PIN
ARRANGEMENT, are described in the following paragraphs.
• Vee and Vss
Power is supplied to the MCV using these two pins. Vee
is +5 .25V ±O.5V. V55 is the ground connection.
• INT
This pin provides the capability for asynchronously applying
an external interrupt to the MCV. Refer to INTERRUPTS for
additional information.
• XTAL and EXTAL
These pins provide connections for the on-chip clock circuit.
A crystal (AT cut, 4 MHz maximum), a resistor or an external
signal can be connected to these pins to provide a system clock
with various stability/cost tradeoffs. Refer to INTERNAL OS-
178
CILLATOR OPTIONS for recommendations about these inputs.
• TIMER
This pin allows an external input to be used to decrement
the internal timer circuitry. Refer to TIMER for additional
information about the timer circuitry.
•
RES
This pin allows resetting of the MCV at times other than
the automatic resetting capability already in the MCV. Refer
to RESETS for additional information.
•
NUM
This pin is not for user application and should be connected
to VSS.
~HITACHI
---------------------------------------------------------------HD6805U1
• Input/Output Lines (Ao ..., A, • Bo ..., B,. Co ..., C,)
These 24 lines are arranged into three 8·bit ports (A, Band
e). All lines are programmable as either inputs or outputs under
software control of the Data Direction Register (DDR). Refer to
INPUT/OUTPUT for additional information.
• MEMORY
The MeU memory is configured as shown in Figure 2. During
the processing of an interrupt, the contents of the CPU regi·
sters are pushed onto the stack in the order shown in Figure 3.
Since the stack pointer decrements during pushes, the low order
byte (PCL) of the program counter is stacked fust; then the
high order four bits (PCH) are stacked. This ensures that the
program counter is loaded correctly as the stack pointer in·
crements when it pulls data from the stack. A subroutine call
will cause only the program counter (pCH, peL) contents to
be pushed onto the stack.
• Input Lines (Do ..., 0,)
These are 8·bit input lines, which has two functions. Firstly,
these are TTL compatible inputs, in location $003. The other
function is 7 bits comparator, in location $007. Refer to INPUT
for more detail.
Caution: - Self Test ROM Address Area
Self test ROM locations can not be used for a user program.
If the user's program is in this location, it will be removed when
manufacturing mask for production.
$000
000
110 Ports Timer
RAM (128 Bytes)
$07
127
128
K
ROM
(128 Bytes)
$OF F
$1 00
255
256
Not Used
0
Port A
$000
1
Port B
$001
2
Port C
$002
3
Port 0 (digital)
$003"
4
Port A DDR
$004'
5
Port BOOR
$005'
6
Port C DDR
$7F F
$8 00
2047
2048
$OOS'
Port 0 (analog)
$007"
8
Timer Data Reg.
$008
9
Timer CTRL Reg.
$009
7
$OOA
0
Not Used 122 Bytes)
1
ROM
$OIF
~
(1920 Bytes)
$020
RAM (96 Bytes)
Stt
Ck
$07F
12
3968
Self·Test
4087
4088
Interrupt Vectors
$FF
4095
Figure 2 MCU Memory Configuration
6
n-4
1
• Write only registers
." Read only register
$F7 F
$F 80
$FF 7
$FF 8
3967
5
1
4
Condition
11 Code Register
°
°1
Pull
L-_ _ _ _ _
A_ _ _ _...J
n+1
n-3
Accumulator
n+2
n-2
Index Register
n+3
1
n+4
°1
' -_ _ _ _ _
x_"_ _ _........ Index Register
11
n-1
1
1
11
PCl"
PCH"
Accumulator
--II°
°
' -_ _ _ _ _ _ _ _P_C_ _ _ _ _ _
11
5 4
Program Counter
l_o....l_o....l_o....I-...II_1...11_ _ _sP_ _....1Stack Pointer
LoI0...lI_o.....
n+5
Push
Condition Code Register
• For subroutine calls, only PCH and PCl are stacked.
Carry/Borrow
Figure 3 Interrupt Stacking Order
Zero
Negative
Interrupt Mask
Half Carry
Figure 4 Programming Model
~HITACHI
179
HD6805Ul----------------------------------------------------------------•
indicate that a carry occurred between bits 3 and 4.
REGISTERS
The CPU has five registers available to the programmer.
They are shown in Figure 4 and are explained in the following
paragraphs.
•
Accumulator (A)
The accumulator is a general purpose 8-bit register used to
hold operands and results of arithmetic calculations or data
rna nipulations.
•
Index Register (X)
The index register is an 8-bit register used for the indexed
addr~ssing mode. It contains an 8-bit address that may be added
to an offset value to create an effective address. The index
register can also be used for limited calculations and data
manipulations when using read/modify/write instructions. When
not required by a code sequence being executed, the index
register can be used as a temporary storage area.
•
Program Counter (PC)
The program counter is a 12-bit register that contains the
address of the next instruction to be executed.
•
Stack Pointer (SP)
The stack pointer is a 12-bit register that contains the address
of the next free location on the stack. Initially, the stack pointer is set to location $07F and is decremented as data is being
pushed onto the stack and incremented as data is being pulled
from the stack. The six most significant bits of the stack pointer
are permanently set to 0000011. During an MCU reset or the
reset stack pointer (RSP) instruction, the stack pointer is set
to location $07F. Subroutines and interrupts may be nested
down to location $061 which allows the programmer to use up
to 15 levels of subroutine calls.
•
Condition Code Register (CC)
The condition code register is a 5-bit register in which each
bit is used to indicate or nag the r~sults of the instruction just
executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each individual condition code register bit is explained in the following
paragraphs.
Half Carry (H)
Used during arithmetic operations (ADD and ADC) to
Interrupt (I)
This bit is set to mask the timer and external interrupt (iNT).
If an interrupt occurs while this bit is set it is latched and will be
processed as soon as the interrupt bit is reset.
Negatiye (N)
Used to indicate that the result of the last arithmetic, logical
or data manipulation was negative (bit 7 in result equal to a
logical one).
Zero (Z)
Used to indicate that the result of the last arithmetic, logical
or data manipulation was zero.
Carry/Borrow (C)
Used to indicate that a carry or borrow out of the arithmetic
logic unit (ALU) occurred during the last arithmetic operation.
This bit is also affected during bit test and branch instructions,
shifts, and rotates.
•
TIMER
The MCU timer circuitry is shown in Figure 5. The 8-bit
counter, the. Timer Data Register (TOR), is loaded under program control and counts down toward zero as soon as the clock
input is applied. When the timer reaches zero, the timer interrupt request bit (bit 7) in the Timer Control Register (TCR) is
set. The CPU responds to this interrupt by saving the present
CPU state on the stack, fetching the timer interrupt vector from
locations $FF8 and $FF9 and executing the interrupt routine.
The timer interrupt can be masked by setting the timer interrupt mask bit (bit 6) in the TCR. The interrupt bit (I bit) in the
Condition Code Register also prevents a time interrupt from
being processed.
The clock input to the timer can be from an external source
applied to the TIMER input pin or it can be the internal 1/>2
signal. When the 1/>2 signal is used as the source, it can be gated
by an input applied to the TIMER input pin allowing the user
to easily perform pUlse-width measurements. The TIMER input
pin must be tied to Vee, for ungated 1/>2 clock input to the
timer prescaier. The source of the clock input is one of the
options that has to be specified before manufacture of the
<1>,
(Internal)
TIR;
TIM;
Timer Interrupt Request
Timer Interrupt Mask
Timer
Input
Pin
,.-----,
•
I
I
I
I
I
1.
I _____ .1I
Manufacturing
Mask Options
Write
Read
Figure 5 Timer Block Diagram
180
~HITACHI
Write
Read
---------------------------------------------------------------HD6805Ul
•
MCU. A prescaler option can be applied to the clock input that
extends the timing interval up to a maximum of 128 counts
before decrementing the counter (TOR). The timer continues
to count past zero, falling through to $FF from zero and then
continuing the count. Thus, the counter (TOR) can be read at
any time by reading the TOR. This allows a program to determine the length of time since a timer interrupt has occurred
and not disturb the counting process.
The TDR is 8-bit Read/Write Register in location $008.
At power-up or reset, the TOR and the prescaler are initialized
with all logical ones.
The Timer Interrupt Request bit (bit 7 of the TCR) is set
by hardware when timer count reaches zero, and is cleared by
program or by hardware reset. The bit 6 of the TCR is writable
by program. Both of those bits can be read by CPU.
(NOTE) If the MCU Timer is not used, the TIMER input pin
must be grounded.
2..
INT
2
RES
SELF CHECK
The self-check capability of the MCU provides an internal
check to determine if the part is functional. Connect the MCU
as shown in Figure 6 and monitor the output of port C bit 3 for
an oscillation of approximately 3Hz.
•
RESETS
The MCU can be reset three ways; by initial power-up, by
the external reset input (RES) and by an optional internal
low voltage inhibit circuit, see Figure 7. All the I/O port are
initialized to input mode (OORs are cleared) during reset.
During power-up, a minimum of 100 milliseconds is needed
before allowing the RES input to go "High".
This time allows the internal crystal oscillator to stabilize.
Connecting a capacitor to the RES input, as shown in Figure 8,
typically provides su fficien t delay.
A, 40
A. 39
-L. 2 21lF
T
A4rE-
.
C
r
XTAL
1~,!1 ~
~3pn ~b
9
10
13fo ~ U
"
1~!P.
~ 10.12
vv
10kn
A
v
lokn
~AAv
10kn
J\&v
l°Ak~
vv v
Vcc=Pin4
Vss = Pin 1
RES Pin
A, 34
An
HD6805U1 *
8 TIMER (Resistor option)
\0'
~
B,~
NUM
v cc
A, 36
A, 35
EXTAL
+9V
As 38
B. 31
B, 30
B. 29
Co
B-,~
C.
B, Z7
C,
B, 26
C,
Bn 25
13 C.
14 C
s
15
c.
16 C,
• R fer to F, gure 9
about crystal
option
Figure 6 Self Check Connections
--------4'
Internal
Reset
---------~
Figure 7 Power Up and RES Timing
~HITACHI
181
HD6805U1--------------------------------------------------------------•
INTERNAL OSCILLATOR OPTIONS
The internal oscillator circuit is designed to require a mini·
mum of external components. A crystal, a resistor, a jumper
wire, or an external signal may be used to generate a system
clock with various stability/cost tradeoff. A manufacturing
mask option is required to select either the crystal oscillator or
the RC oscillator circuit. The different connection methods are
shown in Figure 9. Crystal specifications are given in Figure 10.
A resistor selection graph is given in Figure 11.
2
Part of
HD6805U1
MCU'
Figure 8 Power Up Reset Delay Circuit
6 XTAL
6 XTAL
4~a~Z c:J
5 EXTAL
HD6805U1
MCU
5 EXTAL
HD6805U1
MCU
22PF±20%T
Approximately 25% Accuracy
External: Jumper
Vee
6
6 XTAL
XTAL
R
External
Clock
Input
5 EXTAL
HD6805U1
MCU
5 EXTAL
HD6805U1
MCU
No
Connection
External Clock
Approximately 15% Accuracy
External Resistor
CRYSTAL OPTIONS
RESISTOR OPTIONS
Figure 9 Internal Oscillator Options
5
,
4.
f\
C,
XTAL~~EXTAL
6
~~
5
4
\
~
~
~
3
I -'-
Vee = 5.25V
TA = 25°C
\.
\
~
~
AT - Cut Parallel Resonance Crystal
CIl = 7 pF max.
f = 4 MHz
Rs = 60n max.
-
u:
Figure 10 Crystal Parameters
"'-
'"
~ '-..
~
~
1
o
5
10
15
20
25
30
Resistance (kH)
35
40
Figure 11 Typical Resistor Selection Graph
182
$
HITACHI
45
50
-----------------------------------------------------------------HD6805U1
1-1
7F -SP
o -DDR's
Stack
PC,X,A,CC
y
CLR I NT Logic
FF - Timer
7F --+ Prescaler
7F --+ TCR
Y
TIMER
Load PC From
Reset :$FFE, $FFF
Load PC From
SWI :$FFC, $FFD
iNT:$FFA, $FFB
TIMER :$FF8,$FF9
Fetch
Instruction
Y
SWI
Execute
Instruction
Figure 12 Interrupt Processing Flowchart
Data
Direction
Register
Bit
Output
Data Bit
0
Output
State
Input to
MCU
0
0
3·State
Pin
1
Figure 13 Typical Port I/O Circuitry
~HITACHI
0
183
HD6805U1--------------------------------------------------------------•
INTERRUPTS
The CPU can be interrupted three different ways: through
the external interrupt (INT) input pin, the internal timer interrupt request. and a software interrupt instruction (SWI). When
any interrupt occurs, processing is suspended, the present CPU
state is pushed onto the stack, the interrupt bit (I) in the Condition Code Register is set, the address of the interrupt routine is
obtained from the appropriate interrupt vector address, and the
interrupt routine is executed. The interrupt service routines
normally end with a return from interrupt (RTI) instruction
which allows the CPU to resume processing of the program
prior to the interrupt. Table 1 provides a listing of the interrupts, their priority, and the vector address that contain the
starting address of the appropriate interrupt routine.
A flowchart of the interrupt processing sequence is given
in Fig. 12.
Table 1 Interrupt Priorities
Interrupt
RES
Priority
Vector Address
1
$FFE and $FFF
SWI
2
$FFC and $FFD
TNT
3
$FFA and $FFB
TIMER
4
$FF8 and $FF9
outputs. Port A is CMOS compatible as outputs, and Port Band
C lines are CMOS compatible as inputs. Figure 14 provides some
examples of port connections.
•
•
•
INPUT/OUTPUT
There are 24 input/output pins. All pins are programmable
as either inputs or outputs under software control of the corresponding Data Direction Register (DDR). When programmed
as outputs, the latched output data is readable as input data,
regardless of the logic levels at the output pin due to output
loading (see Fig. 13). When Port B is programmed for outputs,
it is capable of sinking lOrnA on each pin (VOL = IV max).
All input/output lines are TTL compatible as both inputs and
Port A
INPUT
Port D can be used as either 8 TTL compatible inputs or 1
threshold input and 7 analog inputs pins. Fig. 15 (a) shows the
construction of port D. The Port D register at location $003
stores TTL compatible inputs, and those in location $007 store
the result of comparison Do to D6 inputs with D7 threshold
input. Port D has not only the conventional function as inputs
but also voltage-comparison function. Applying the latter, can
easily check that 7 analog input electric potential max. exceeds
the limit with the construction shown in Fig. 15 (b). Also, using
one output pin of MCU, after external capacity is discharged
at the preset state, charge the CR circuit of long enough time
constant, apply the charging curve to the D7 pin. The construction described above is shown in Fig. 15 (c). The compared
result of Do to D6 is regularly monitored, which gives the
analog input electric potential applied to Do to D6 pins from
inverted time. This method enables 7 inputs to be converted
from analog to digital. Furthermore, combination of two functions gives 3 level voltages from Do to D6. Fig. 15 (d) provides
the example when VTH is set to 3.SV.
BIT MANIPULATION
The MCU has the ability to set or clear any single random
access memory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines. The example in Figure 16
illustrates the usefulness of the bit manipulation and test
Port B
···
·
B7
Port A Programmed as output(sl.driving CMOS and TTL Load directly.
(a)
Port B Programmed as output(s),driving Darlington base directly.
(b)
+V
+v
R
R
Co
-
Port B
PortC
10 mA max
B7
1 - - - -........ CMOS Inverter
C7
Port B Programmed as output(S),driving LED(s) directly.
(e)
Port C Programmed as output(s), driving CMOS loads, using
external pull-up
(d)
Figure 14 Typical Port Connections
184
·
···
·
~HITACHI
-----------------------------------------------------------------HD6805U1
vides turn-on of the TRIAC within 14 microseconds of the zero
crossing. The timer could also be incorporated to provide turnon at some later time which would permit pulse·width modulation of the controlled power.
instructions. Assume that bit 0 of port A is connected to a zero
crossing detector circuit and that bit 1 of port A is connected to
the trigger of a TRIAC which power the controlled hardware.
This program, which uses only seven ROM locations, pro-
$003 Read
Internal Bus
(BitO - BitS)
+
$003 Read
Input Port (D7)
Internal Bus
(Bit 7)
(a) The logic configuration of Port D
Port
r---
Co
C
D,
Reference Level
D,
Port
Analog Input S
D,
)
D
Do
Port
D
D.
I--=----Analog Input 6
Do
1--=--Analog Input 0
Analog Input 0
(c) Application to AID convertor
(b) Seven analog inputs and a reference level input of Port D
D,
VTH (= 3.5V)
D,
Port
3 Levels Input S
~
D
D.
Input
Voltage
($003)
($007)
OV -O.8V
0
0
2.0V - 3.3V
1
0
3.7V - Vee
1
1
3 Levels Input 0
(d) Application to 3 levels input
Figure 15 Configuration and Application of Port 0
$
HITACHI
185
HD6805U1-----------------------------------------------------------------
SELF 1
··
··
·
BRClR 0, PORT A, SELF 1
BSET 1, PORT A
BClR 1, PORT A
··
·
Figure 16 Bit Manipulation Example
• ADDRESSING MODES
The CPU has ten addressing modes available for use by the
programmer. They are explained and .illustrated briefly in the
following paragraphs.
• Immediate
Refer to Figure 17. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte following the
opcode.
• Direct
Refer to Figure ] 8. In direct addressing, the address of the
operand is contained in the second byte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. All RAM space, I/O registers and 128
bytes of ROM are located in page zero to take advantage of this
efficient memory addressing mode.
• Extended
Refer to Figure 19. Extended addressing is used to reference
any location in memory space. The EA is the contents of the
two bytes following the opcode. Extended addressing instructions are three bytes long.
• Relative
Refer to Figure 20. The relative addressing mode applies only
to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA=(pC)+2+Rel. Rei is the contents
of the location following the instruction opcode with bit 7
being the sign bit. If the branch is not taken Rel=O, when a
branch takes place, the program goes to somewhere within the
range of + 129 bytes to -127 of the present instruction. These
instructions are two bytes long.
• Indexed (No Offset)
Refer to Figure 21. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and their EA is the contents of the index register.
• Indexed (S-bit Offset)
Refer to Figure 22. The EA is calculated by adding the
contents of the byte following the opcode to the contents of
the index register. In this mode, 511 low memory locations are
accessable. These instructions occupy two bytes.
• Indexed (16-bit Offset)
Refer to Figure 23. This addressing mode calculates the EA
by adding the contents of the two bytes following the opcode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are three
bytes long.
186
$
• Bit Set/Clear
Refer to Figure 24. This mode of addressing applies to
instructions which can set or clear any bit on page zero. The
lower three bits in the opcode specify the bit to be set or
cleared while the byte following the opcode specifies the
address in page zero.
• Bit Test and Branch
Refer to Figure 25. This mode of addressing applies to
instructions which can test any bit in the first 256 locations
($OO-$FF) and branch to any location relative to the PC. The
byte to be tested is addressed by the byte following the opcode.
The individual bit within that byte to be tested is addressed by
the lower three bits of the opcode. The third byte is the relative
address to be added to the program counter if the branch condition is met. These instructions are three bytes long. The value of
the bit tested is written to the carry bit in the condition code
register.
• Implied
Refer to Figure 26. The implied mode of addressing has no
EA. All the information necessary to execute an instruction is
contained in the opcode. Direct operations on the accumulator
and the index register are included in this mode of addressing.
In addition, control instructions such as SWI, RTI belong to this
group. All implied addressing instructions are one byte long.
•
INSTRUCTION SET
The MCV has a set of S9 basic instructions. They can be
divided into five different types: register/memory, read/modify/
write, branch, bit manipulation, and control. The following
paragraphs briefly explain each type. All the instructions within
a given type are presented in individual tables.
• Register/Memory Instructions
Most of these instructions use two operands. One operand is
either the accumulator or the index register. The other operand
is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR)
instructions have no register operand. Refer to Table 2.
• Read/Modity!Write Instructions
These instructions read a memory location or a register,
modify or test its contents, and write the modified value back
to memory or to the register. The test for negative or zero
(TST) instruction is an exception to the read/modify/write
instructions since it does not perform the write. Refer to Table
3.
• Branch Instructions
The branch instructions cause a branch from the program
when it certain condition is met. Refer to Table 4.
• Bit Manipulation Instructions
These instructions are used on any bit in the first 2S6 bytes
of the memory. One group either sets or clears. The other group
performs the bit test and branch operations. Refer to Table 5.
• Control Instructions
The control instructions control the Mev operations during
program execution. Refer to Table 6.
• Alphabetical listing
The complete instruction set is given in alphabetical order in
Table 7.
• Opcode Map
Table 8 is an opcode map for the instructions used on the
MCV.
HITACHI
-----------------------------------------------------------------HD6805Ul
Memory
I
a
A
Index
r
Stack Point
I
PROG LOA #$F8 058E
058F
ea'l.._ _ _ _...
I
I
A6
Prog Count
t-------i
05CO
F8
CC
I
I
~
I
I
I
I
Figure 17
,
t
Memory
I
I
I
CAT
FeB
32
LOA
CAT
,,,
,,
I
/
0048
t
Adder
.'"
I
A
ooto
20
0048
I
PROG
JEA
i
I
,
Immediate Addressing Example
I
1
I
0520
86
052E
48
20
1
Index Reg
I
I
Stack Point
I
I
I
Prog Count
I
052F
CC
I
~
,
I
,
I
I
I
:
•
I
Figure 18 Direct Addressing Example
~HITACHI
187
HD6805U1---------------------------------------------------------------
,,
Memory
I
§
PROG
LOA
CAT
0000
=~1-------'
I
FCB
64
06E5
40
Index Reg
Stack Point
I
I
CAT
A
Prog Count
I
040C
40
t-------1
CC
Figure 19 Extended Addressing Example
,
Memory
I
~
A
Index Reg
Stack Point
I
I
PROG
BEQ
PROG2
0000
04A 7
27
.-------~
04A8
18
~
I
,
I
,
Figure 20 Relative Addressing Example
188
$
HITACHI
---------------------------------------------------------------HD6805U1
Memory
A
TABL
FCC
t Lit 00B8
4C
4C
49
Index Reg
88
I
PROG
LOA
X
I
Stack Point
05F4~
Prog Count
05F5
CC
§
Figure 21
Indexed (No Offset) Addressing Example
J
lEA
Memory
i
i
I
i
i
I
TABL
FCB
#SF
0089
SF
FCB
#86
008A
86
FCB
#OB
0088
DB
FCB
#CF
008C
CF
I
f
/
1
008C
Adder
~
A
-,_I
[
i
i
I
I
CF
I
Index Reg
I
03
I
Stack Point
PROG
LOA
TABL. X 075B
E6
075C
89
I
I
,.
Prog Count
I
0750
CC
i
I
I
I
§
,J
Figure 22 Indexed (S-Bit Offset) Addressing Example
~HITACHI
189
HD6805Ul-----------------------------------------------------------------
Memory
i
I
§
PROG
LOA
A
DB
Index Reg
02
TABL.x::EB
Stack Point
06M ~ / - - - - - - - '
Prog Count
0695 ...
I
TABL
CC
I
FCB
#BF
077E
BF
FCB
#86
077F
86
FCB
#OB
07BO ~--~O~B--_t-----------------'
FCB
#CF
0781
CF
Figure 23 Indexed (16·Bit Offset) Addressing Example
Memory
PORT B EQU
BF
0001
I
A
0000
Index Reg
10
0590
Stack Point
01
Prog Count
0591
I
I
CC
§
I
I
,
I
Figure 24 Bit Set/Clear Addressing Example
190
~HITACHI
HD6805U 1
PORT C
eau
A
FO
2
I-----~
Index Reg
Stack POint
PROG BRCLR 2. PORT C. PROG 2
Prog Count
05
0594
0000
02
CC
10
I
§
I
. Example
Figure 25 B'It T est and Branch Add ressmg
EA
Memory
I
I
I
§
PROG
TAX
A
II
I
I
I
O~A~
Prog Count
JI
________~05~BB~______
CC
I
I
~
I
I
I
I
I
I
I
-!------.:
Figure 26 I mplied Addressing Example
$
HITACHI
191
HD6805U1----------------------------------------------------------------Table 2 Register/Memory Instructions
Addressing Modes
Function
Mnemonic
Op
Op
#
#
Op
#
#
Code Bytes Cycles Code Bytes Cycles Code
Indexed
(8-Bit Offset)
Indexed
(No Offset)
Extended
Direct
Immediate
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles 'Code
Indexed
(16-Bit Offset)
#
#
Op
Bytes Cycles Code
#
#
Bytes Cycles
Load A from Memory
LOA
A6
2
2
B6
2
4
C6
3_
5
F6
1
4
E6
2
5
06
3
6
Load X from Memory
LOX
AE
2
2
BE
2
4
CE
3
5
FE
1
4
EE
2
5
DE
3
6
7
Store A in Memory
STA
2
5
C7
3
6
F7
1
5
E7
2
6
07
3
-
-
B7
STX
-
-
Store X in Memory
BF
2
5
CF
3
6
FF
1
5
EF
2
6
OF
3
7
Add Memory to A
ADD
AB
2
2
BB
2
4
CB
3
5
FB
1
4
EB
2
5
DB
3
6
--
Add Memory and
AOC
A9
2
2
89
2
4
C9
3
5
F9
1
4
E9
2
5
09
3
6
Subtract Memory
SUB
AO
2
2
BO
2
4
CO
3
5
FO
1
4
EO
2
5
DO
3
6
Subtract Memory from
A with Borrow
SBC
A2
2
2
82
2
4
C2
3
5
F2
1
4
E2
2
5
02
3
6
AND Memory to A
AND
A4
2
2
B4
2
4
C4
3
5
F4
1
4
E4
2
5
04
3
6
OR Memory with A
ORA
AA
2
2
BA
2
4
CA
3
5
FA
1
4
EA
2
5
OA
3
6
4
E8
2
5
08
3
6
4
El
2
5
01
3
6
4
E3
2
5
03
3
6
~:!toA
Exclusive OR Memory
with A
Arith",etic Compare A
with Memory
Arithmetic Compare X
with Memory
EOR
A8
CMP
Al
2
2
2
2
B8
2
Bl
CPX
A3
BIT
A5
2
2
B5
Jump Unconditional
JMP
-
-
-
BC
Jump to Subroutine
JSR
-
-
-
BD
2
2
B3
3
C8
Cl
4
2
Bit Test Memory with A
(Logical Compare)
2
4
5
3
5
F8
Fl
F3
1
1
4
C3
2
4
C5
3
5
F5
1
4
E5
2
5
05
3
6
2
3
CC
3
4
FC
1
3
EC
2
4
DC
3
5
7
CD
3
8
FO
1
7
ED
2
8
DO
3
9
2
3
5
1
Table 3 Read/ModifylWrite Instructions
Addressing Modes
Function
Implied (A)
Mnemonic
Op
#
#
Bytes Cycles Code
Op
Code
192
Implied (X)
Indexed
(No Offset)
Direct
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(8-Bit Offset)
Op
#
#
Bytes Cycles Code
#
#
Bytes Cycles
Increment
INC
4C
1
4
5C
1
4
3C
2
6
7C
1
6
6C
2
7
Decrement
DEC
4A
1
4
5A
1
4
3A
2
6
7A
1
6
6A
2
7
Clear
CLR
4F
1
4
5F
1
4
3F
2
6
7F
1
6
6F
2
7
Complement
COM
43
1
4
53
1
4
33
2
6
73
1
6
63
2
7
Negate
(2'5 Complement)
NEG
40
1
4
50
1
4
30
2
6
70
1
6
60
2
7
Rotate Left Thru Carry
ROL
49
1
4
59
1
4
39
2
6
79
1
6
69
2
7
Rotate Right Thru Carry
ROR
46
1
4
56
1
4
36
2
6
76
1
6
66
2
7
Logical Shift Left
LSL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
7
I
Logical Shift Right
LSR
44
1
4
54
1
4
34
2
6
74
1
6
64
2
Arithmetic Shift Right
ASR
47
1
4
57
1
4
37
2
6
77
1
6
67
2
7
Arithmetic Shift Left
ASL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
Test for Negative or
Zero
TST
40
1
4
50
1
4
3D
2
6
70
1
6
60
2
7
i
~HITACHI
---------------------------------------------------------------HD6805U1
Table 4 Branch Instructions
Relative Addressing Mode
Function
Mnemonic
Op
Code
#
#
Bytes
Cycles
4
Branch Always
BRA
20
2
Branch Never
BRN
21
2
4
Branch I F Higher
BHI
22
2
4
Branch I F lower or Same
BlS
23
2
4
Branch I F Carry Clear
BCC
24
2
4
(Branch IF Higher or Same)
(BHS)
24
2
4
Branch I F Carry Set
BCS
25
2
4
(Branch IF lower)
(BlO)
25
2
4
Branch I F Not Equal
BNE
26
2
4
Branch I F Equal
BEQ
27
2
4
Branch I F Half Carry Clear
BHCC
28
2
4
Branch I F Half Carry Set
BHCS
29
2
4
Branch I F Plus
BPl
2A
2
4
Branch I F Minus
BMI
2B
2
4
Branch I F Interrupt Mask Bit is Clear
BMC
2C
2
4
Branch I F Interrupt Mask Bit is Set
BMS
20
2
4
Branch IF Interrupt Line is low
Bil
2E
2
4
Branch IF Interrupt Line is High
BIH
2F
2
4
Branch to Subroutine
BSR
AD
2
8
Table 5 Bit Manipulation Instructions
Addressing Modes
Function
Mnemonic
Bit Set/Clear
Op
Code
Bit Test and Branch
#
#
Bytes
Cycles
Op
Code
#
#
Bytes
Cycles
Branch IF Bit n is set
BRSET n (n=O ..... 7)
-
-
-
2 n
0
3
10
Branch IF Bit n is clear
BRClR n (n=O ..... 7)
-
-
-
01+2-n
3
10
-
Set Bit n
BSET n (n=O ..... 7)
10+2·n
2
7
-
-
Clear bit n
BClR n (n=O ..... 7)
11+2·n
2
7
-
-
Table 6 Control Instructions
Implied
Function
Mnemonic
Op
Code
#
#
Bytes
Cycles
Transfer A to X
TAX
97
1
2
Transfer X to A
TXA
9F
1
2
Set Carry Bit
SEC
99
1
Clear Carry Bit
CL.C
98
1
1
Set Interrupt Mask Bit
SEI
9B
Clear Interrupt Mask Bit
CLI
9A
1
2
2
2
2
Software Interrupt
SWI
83
1
11
Return from Subroutine
RTS
81
1
6
Return from Interrupt
RTI
80
1
9
2
2
Reset Stack Pointer
RSP
9C
1
No-Operation
NOP
90
1
~HITACHI
193
HD6805U1----------------------------------------------------------_____
Table 7 Instruction Set
Addressing Modes
Mnemonic
Implied
Immediate
Direct
Extended
Relative
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
Setl
Clear
Bit
Test &
Branch
H
I
N
Z
C
/\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
•
•
•
•
•
/\
/\
/\
/\
/\
/\
/\
/\
/\
/\
/\
•
•
•
•
•
•
•
•
•
•/\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
/\
/\
/\
/\
/\
/\
/\
ADC
x
x
x
ADD
x
x
x
x
x
x
/\
AND
x
x
x
x
x
x
x
x
x
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ASl
x
x
ASR
x
x
x
x
BCC
x
BClR
BCS
x
BEQ
x
BHCC
x
BHCS
x
BHI
x
BHS
x
BIH
x
Bil
x
x
BIT
x
x
x
BlO
x
BlS
x
BMC
x
x
x
x
BMI
---------BMS
x
BNE
x
BPl
x
BRA
x
BRN
x
BRClR
x
BRSET
x
x
BSET
x
BSR
ClC
x
CLI
x
ClR
x
COM
x
x
CPX
DEC
x
x
CMP
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
JMP
x
x
JSR
x
x
x
x
x
x
x
x
x
INC
x
x
LOA
x
lOX
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
x
x
x
x
x
x
x
x
EOR
194
Bit
x
x
x
x
x
x
x
x
x
x
/\
•/\
•
•
•
•
•
•
•
•
~
•
/\
•
/\
/\
• /\
• •
• •
• 0
•0 •1 •
•
/\
/\
/\
/\
/\
1
•
•
•
• • •
• • •
/\
/\
/\
/\
/\
/\
•
•
(to be continued)
C
/\
•
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
~HITACHI
-----------------------------------------------------------------HD6805U1
Table 7 Instruction Set
Addressing Modes
Mnemonic
Implied
Immediate
Direct
Extended
Relative
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
LSL
x
x
LSR
x
x
x
x
NEG
x
x
x
x
NOP
x
x
x
x
ROL
x
x
x
x
ROR
x
x
x
x
RSP
x
RTI
x
RTS
x
x
ORA
x
x
x
x
x
x
x
x
STA
x
x
x
x
x
x
x
x
x
x
x
STX
x
x
x
x
x
SBC
SEC
x
SEI
x
SUB
SWI
x
TAX
x
TST
x
TXA
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
I nterrupt Mask
N
Negative (Sign Bit)
Z
Zero
x
x
C
1\
•
?
Bit
Set/
Clear
x
Bit
Test &
Branch
H
I
N
Z
C
•
•
•
•
•
•
•
•
• 1\ 1\ 1\
• 0 1\ 1\
• 1\ 1\ 1\
• • • •
• 1\ 1\ •
• 1\ 1\ 1\
• 1\ 1\ 1\
• • • •
?
?
•
•
•
•
•
•
•
•
•
•
•
• • • •
• 1\ 1\ 1\
• • • 1
1 • • •
• 1\ 1\ •
• 1\ 1\ •
• 1\ 1\ 1\
1 • • •
?
?
?
• • • •
• 1\ 1\ •
• • • •
Carry!Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
195
HD6805U1----------------------~--------------------
Table 8
Bit Manipulation
0
-
Branch
Set/
Clear
Rei
OIR
Control
0
BRSETO
1
3
BSETO
2
BRA
I I
A
I
4
I
IMP
IMP
IMM
I
OIR
8
9
A
B
RTI-
I
NEG
-
I
I
7
5
I
.X1
I
6
I
I
1 BRClRO
BClRO
BRN
BRSET1
BSET1
BHI
-
RTS·
2
3
BRClR1
BClR1
BlS
COM
SWI·
4
BRSET2
BSET2
BCC
lSA
5 BAClA2
6 BASET3
7 BAClA3
BClA2
BSET3
ROA
-
BClA3
BCS
BNE
BEQ
-
ASR
8 BASET4
9 BAClA4
BSET4
BHCC
lSl/ASl
BClA4
BHCS
BPl
AOl
-
.x1
I
E
l·xO
I
F
-
-
-
-
CMP
1
SBC
2
CPX
3
l
AND
4
o
BIT
5 W
6
7
ClC
EOA
SEC
AOC
8
9
A
INC
-
ADD
JMP(-1)
C
JSA(-3)
0
lOX
STX(+1)
F
BMS
TST
Bil
-
F BAClA7
BClA7
BIH
ClA
1/4
I 2/7
I 1/6
NOP
-
I
BSA·I
-
TXA
-
1/-
1/2
2/2
I
I
2/4
I 3/5 I
3/6
J 2/5
1. Undefined opcodes are marked with "-".
2. The number at the bottom of each column denote the number of bytes and the number of cycles required (Bytes/Cycles).
Mnemonics followed by a "." require a different number of cycles as follows:
ATI
9
ATS
6
SWI
11
BSA
8
3. (
indicate that the number in parenthesis must be added to the cycle count for that instruction.
$
HITACHI
HIGH
0
lOA
STA(+1)
I
+-
OAA
BSET7
I
I
CLI
BClA6
I 1/4
0
SUB
-
TAX
.x2
SEI
ASP
E BASET7
2/6
I
-
0 BAClA6
2/4
I
-
C BASET6
2/7
C
-
BClA5 1------=- BMI
BSET6
BMC
3/10
-
EXT
DEC
BSET5
B BAClA5
(NOTE)
Register /Memory
.XO
X
A BASET5
196
Opcode Map
Read/Modify /Write
Test &
Branch
___________________
B
E
J 1/4
HD6805V1-------------MCU (Microcomputer
Unit)
The H06805Vl is the 8-bit Microcomputer Unit (MCU)
which contains a CPU. on-chip clock. ROM. RAM. I/O and
timer. It is designed for the user who needs an economical
microcomputer with the proven capabilities of the H06800based instruction set.
The foUowing are some of the hardware and software highlights of the MCU.
HD6805V1P
•
•
•
•
•
•
•
•
HARDWARE FEATURES
8-Bit Architecture
96 Bytes of RAM
Memory Mapped I/O
3848 Bytes of User ROM
Internal 8-Bit Timer with 7·Bit Prescaler
Vectored Interrupts - External and Timer
24 I/O Ports + 8 Input Port
(8 Lines LED Compatible; 7 Bits Comparator Inputs)
• On-Ghip Clock Circuit
• Self·Check Mode.
• Master Reset
• Low Voltage Inhibit
• Complete Development System Support by Evaluation Kit
• 5 Vdc Single Supply
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SOFTWARE FEATURES
Similar to HD6800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handing
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Appl~ to ROM, RAM and I/O
Compatible Instruction Set with MC6805P2
•
BLOCK DIAGRAM
(DP·40)
•
PIN ARRANGEMENT
0
A,
Ao
B,
c.
c,
c,
8s
B.
8_
8.
AI
Condition
Data
P~1
Oir
Reg
Reg.
~
Code
Register
B,
C.
B,
C,
Bo
o.
0,
D.
0,
d.
(Top View)
C.
c~
C.
Program
High
B,
C.
c.
c.
Counter
..
B.
C.
Lines
CPu
Stack
Pointer
A.
A,
Port
B
I/O
HD6805Vl
B.
B,
A.
A.
A,
A.
Index
Register
A.
110
A.
Lines A.
A.
XTAL
B.
A
A.
A.
B.
Port
A,
RES
INf
C.
C.
C,
PCH
Port
C
1/0
Lines
g;
01
Port
D.
0
o.
Input
Lines
o.
D.
O,/VTH
$
HITACHI
197
HD6805V11--------------------------------------------------------------• ABSOLUTE MAXIMUM RATINGS
Vcc *
Supply Voltage
Input Voltage (EXCEPT TIMER)
Yin *
Input Voltage (TIMER)
I
Operating Temperature
-_..
Storage Temperature
•
Value
Symbol
Item
Unit
-0.3 - +7.0
V
-0.3- +7.0
V
-0.3-+12.0
T opr
o -+70
V
DC
T stg
- 55- +150
DC
With respect to Vss (SYSTEM GNOI
(NOTE)
Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (VCC·S.25V ± O.SV, VSS·GND, Ta=G-+70DC, unless otherwise noted.)
Input "High" Voltage
max Unit
4.0
INT
3.0
-
2.0
-
Timer Mode
2.0
-
Self-Check Mode
9.0
-
-0.3
-
Vee
11.0
0.8
-
0.8
V
0.6
0.8
V
V
V IH
RES
INT
Input "Low" Voltage
min typ
RES
All Other
Input "High" Voltage Timer
Test Condition
Symbol
Item
V IL
-0.3
EXT AL(Crystal Mode)
All Other
-0.3
-0.3
Vee
-
-
V
Vee
V
Vee
V
V
V
V
-
-
700
Low Voltage Recover
Po
LVR
-
4.75
V
Low Voltage Inhibit
LVI
-
-
-
V
Power Dissipation
TIMER
INT
Input Leak Current
IlL
V in =0.4V-Vee
EXTAL(Crystal Mode)
4.0
mW
-20
-
20
IlA
-50
-
50
IlA
0
IlA
-1200
• AC CHARACTERISTICS (Vcc=5.25V ± O.SV, Vss=GND, Ta=O - +70°C, unless otherwise noted.)
Item
Symbol
Test Condition
min
typ
max Unit
Clock Frequency
fCI
0.4
-
4.0
MHz
Cycle Time
tCYC
1.0
-
10
Oscillation Frequency (External Resistor Mode)
fEXT
-
3.4
-
IlS
MHz
INT Pulse Width
tlWL
t Cyc +
250
-
-
ns
RES Pu Ise Width
tRWL
tcsc +
2 0
-
-
ns
TIMER Pulse Width
tTWL
t Cyc +
250
-
-
ns
-
-
100
ms
-
ms
35
10
pF
pF
Rcp =15.0kU±1%
-
Oscillation Start-up Time (Crystal Mode)
tose
Delay Time Reset
tRHL
Input Capacitance
198
I
I
XTAL
All Other
Cin
C L= 22pF±20%.
Rs =60n max.
External Cap. = 2.21lF
Vin=OV
_HITACHI
100
-
I
---------------------------------------------------------------HD6805V1
• PORT ELECTRICAL CHARACTERISTICS (Vee
Item
= S 2SV ± O.SV
VOH
Port B
Port C
Port A and C
------
Output "Low" Voltage
Input "High" Voltage
Input "Low" Voltage
Port B
Port A, B, C,
and 0*
VOL
min
typ
max
Unit
= -lOIlA
IOH = -lOOIlA
IOH = -200 IlA
IOH = -1 rnA
IOH = -lOOIlA
r------!2 L = 1.6 rnA
3.S
-
-
V
2.4
-
V
2.4
-
-
loS
-
-
V
-
V
-
0.4
V
0.4
V
2.4
-
r_~Qb_:}.2 rnA
-
= lOrnA
-
IOL
V'H
2.0
-0.3
V'L
Port A
Input Leak Current
= GNO, Ta = 0'" +70°C, unless otherwise noted.)
IOH
Port A
Output "High" Voltage
Vss
Test Condition
Symbol
f----
I'L
Port B; C,
and 0
Yin
= 0.8V
= 2V
-300
Yin
= 0.4V '" Vee
- 20
Yin
-SOO
V
1.0
V
Vee
V
0.8
V
IlA
-
-
IlA
-
20
IlA
Input "High" Voltage
Port 0**
(Do'" 0 6 )
V'H
-
VTH+O.2
-
V
Input "Low" Voltage
Port 0**
(Do'" 0 6 )
V'L
-
VTH-0.2
-
V
Port 0**(0,)
VTH
0
-
0. 8xV ee
V
Threshold Voltage
..
* Port 0 as dIgItal Input
** Port 0 as analog input
TTL Equiv. (port A and C)
TTL Equiv. (Port B)
Ii
=
3.2 mA
Vee
1.2k!1
Ii = 1.6 mA
TesT Point
Test Point
2.4kH
Vi
Vi
40pF
30 pF
12 kH
24 kH
(NOTE) 1. Load capacitance includes the floating capacitance of tt.a probe and the jig etc.
2. All diodes are lS20746 or equivalent.
Figure 1 Bus Timing Test Loads
•
SIGNAL DESCRIPTION
The input and output signals for the MCV, shown in PIN
ARRANGEMENT, are described in the following paragraphs.
•
Vee and Vss
Power is supplied to the MCU using these two pins. Vee
is +S.2SV ±O.5V. Vss is the ground connection.
•
INT
This pin provides the capability for asynchronously applying
an external interrupt to the MCV. Refer to INTERRUPTS for
additional information.
• XTAl and EXT Al
These pins provide connections for the on-chip clock circuit.
A crystal (AT cut, 4 MHz maximum), a resistor or an external
signal can be connected to these pins to provide a system clock
with various stability/cost tradeoffs. Refer to INTERNAL OSCILLATOR OPTIONS for recommendations about these inputs.
• TIMER
This pin allows an external input to be used to decrement
the internal timer circuitry. Refer to TIMER for additional
information about the timer circuitry.
• RES
This pin allows resetting of the MCU at times other than
the automatic resetting capability already in the MCV. Refer
to RESETS for additional information.
•
NUM
This pin is not for user application and should be connected
to Vss.
~"UTACHI
199
HD6805V11----------------------------------------------------------_____
• MEMORY
The MCU memory is configured as shown in Figure 2. During
the processing of an interrupt, the contents of the CPU registers are pushed onto the stack in the order shown in Figure 3.
Since the stack pointer decrements during pushes, the low order
byte (PCL) of the program counter is stacked rust; then the
high order four bits (PCH) are stacked. This ensures that the
program counter is loaded correctly as the stack pointer increments when it pulls data from the stack. A subroutine call
will cause only the program counter (PCH. PCL) contents to
be pushed onto the stack.
Cau tion: - Self Test ROM Address Area
Self test ROM locations can not be used for a user program.
If the user's program is in this location, it will be removed when
manufacturing mask for production.
• Input/Output Lines (Ao ,.., A,. Bo ,.., B,. Co ,.., C,)
These 24 lines are arranged into three 8-bit ports (A, Band
C). All lines are programmable as either inputs or outputs under
software con trol of the Data Direction Register (DDR). Refer to
INPUT/OUTPUT for additional information.
• Input lines (Do"" 0,)
These are 8-bit input lines, which has two functions. Firstly,
these are TTL compatible inputs, in location $003. The other
function is 7 bits comparator in location $007. Refer to INPUT
for more detail.
o
765432
000
$000
I/O Ports Timer
RAM (128 Bytes)
1271--_ _ _ _ _ _ _ _ _ _-i
12B
ROM
(3840 Bytes)
3967
3968
0
0
Port A
$000
1
Port B
$001
2
Port C
$002
3
Port 0 (digital)
$003""
4
Port A DDR
$004"
5
Port BOOR
$005"
6
Port C DDR
$006'
7
Port 0 (anall)g)
$007""
8
Timer Data Reg.
$008
9
Timer CTRL Reg.
$009
$OOA
0
Not Used (22 Bytes)
Self-test
31
3
4087
4088
~
Interrupt
Vectors
(8 Bytes)
$01F
RAM (96 Bytes)
$020
Stc~r
$07F
12
$FFF
4095
• Write only registers
•• Read only register
Figure 2 MCU Memory Configuration
6
n-4
n-3
5
1 1 1\
4
2
Condition
Code RegIster
Accumulator
o
7
o
Pull
1
' -_ _ _ _A
_ _ _ _-J Accumulator
n+l
o
,-________
....1Index Register
X
n+2
o
PC
~_--___________
....JI
11
n-2
n-1
Index Register
1 1 1 11
PCL'
PCW
n+3
n~4
11
5 4
Program Counter
o
I Stack Pointer
0 1010101
0 1 111 _ _ _
SP_ _.....
~'--~
....._"'--~.....&_"'-1
n+5
Condition Code Register
Push
• For subroutine calls, only PCH and PCL are stacked.
Carry /Borrow
Figure 3 Interrupt Stacking Order
Zero
Negative
Interrupt Mask
Half Carry
Figure 4
200
~HITACHI
Programming Model
----------------------------------------------------------------HD6805V1
•
Interrupt (I)
REGISTERS
The CPU has five registers available to the programmer.
They are shown in Figure 4 and are explained in the following
paragraphs.
This bit is set to mask the timer and external interrupt (INT).
If an interrupt occurs while this bit is set it is latched and will be
processed as soon as the interrupt bit is reset.
•
Negative (N)
Accumulator (A)
The accumulator is a general purpose 8-bit register used to
hold operands and results of arithmetic calculations or data
manipulations.
Used to indicate that the result of the last arithmetic, logical
or data manipulation was negative (bit 7 in result equal to a
logical one).
•
Zero (Z)
Index Register (X)
The index register is an 8-bit register used for the indexed
addressing mode. It contains an 8-bit address that may be added
to an offset value to create an effective address. The index
register can also be used for limited calculations and data
manipulations when using read/modify/write instructions. When
not required by a code sequence being executed, the index
register can be used as a temporary storage area.
•
Stack Pointer (SP)
The stack pointer is a 12-bit register that contains the address
of the next free location on the stack. Initially, the stack pointer is set to location $07F and is decremented as data is being
pushed onto the stack and incremented as data is being pulled
from the stack. The six most significant bits of the stack pointer
are permanently set to 0000011. During an MCU reset or the
reset stack pointer (RSP) instruction, the stack pointer is set
to location $07F. Subroutines and interrupts may be nested
down to location $061 which allows the programmer to use up
to IS levels of subroutine calls.
•
Carry/Borrow (C)
Used to indicate that a carry or borrow out of the arithmetic
logic unit (ALU) occurred during the last arithmetic operation.
This bit is also affected during bit test and branch instructions,
shifts, and rotates.
Program Counter (PC)
The program counter is a 12-bit register that contains the
address of the next instruction to be executed.
•
Used to indicate that the result of the last arithmetic. logical
or data manipulation was zero.
Condition Code Register (CC)
The condition code register is a 5-bit register in which each
bit is used to indicate or flag the r~sults of the instruction just
executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each individual condition code register bit is explained in the following
paragraphs.
Half Carry (H)
Used during arithmetic operations (ADD and AOC) to
indicate that a carry occurred between bits 3 and 4.
•
TIMER
The MCU timer circuitry is shown in Figure 5. The 8-bit
counter, the Timer Data Register (TOR), is loaded under program control and counts down toward zero as soon as the clock
input is applied. When the timer reaches zero, the timer interrupt request bit (bit 7) in the Timer Control Register (TCR) is
set. The CPU responds to this interrupt by saving the present
CPU state on the stack, fetching the timer interrupt vector from
locations $FF8 and $FF9 and executing the interrupt routine.
The timer interrupt can be masked by setting the timer interrupt mask bit (bit 6) in the TCR. The interrupt bit (I bit) in the
Condition Code Register also prevents a timer interrupt from
being processed.
The clock input to the timer can be from an external source
applied to the TIMER input pin or it can be the internal qn
signal. When the 1/>2 signal is used as the source, it can be gated
by an input applied to the TIMER input pin allowing the
user to easily perform pulse-width measurements. The TIMER
input pin must be tied to Vee, for ungated 1/>2 clock input to
the timer prescaler. The source of the clock input is one of the
options that has to be specified before manufacture of the
MCU. A prescaler option can be applied to the clock input that
extends the timing interval up to a maximum of 128 counts
(/>2
(Internal!
TIR; Timer Interrupt Request
TIM; Timer Interrupt Mask
Timer
Input
Pin
. .
,.-----.,
•
I
I
I
IL _____ .JI
Manufacturing
Mask Options
Write
Read
Figure 5 Timer Block Diagram
~HITACHI
201
HD6805V1--------------------------------------------------------------before decrementing the counter (TDR). The timer continues
to count past zero, falling through to $FF from zero and then
continuing the count. Thus, the counter (TDR) can be read at
any time by reading the TDR. This allows a program to determine the length of time since a timer interrupt has occurred
and not disturb the counting process.
The TDR is 8-bit Read/Write Register in location $008.
At power-up or reset, the TDR and the prescaler are initialized
with all logical ones.
The Timer Interrupt Request bit (bit 7 of the TCR) is set by
hardware when timer count reaches zero, and is cleared by program or by hardware reset. The bit 6 of the TCR is writable by
program. Both of those bits can be read by CPU.
(NOTE) If the MCU Timer is not used, the TIMER input pin
must be grounded.
2-
INT
2
RES
• SELF CHECK
The self-check capability of the MeU provides an internal
check to determine if the part is functional. Connect the MCU
as shown in Figure 6 and monitor the output of port C bit 3 for
an oscillation of approximately 3Hz.
•
RESETS
The MCU can be reset three ways; by initial power-up, by
the external reset input (RES) and by an optional internal
low voltage inhibit circuit, see Figure 7. All the I/O port are
initialized to input mode (DDRs are cleared) during reset.
During power-up, a minimum of 100 milliseconds is needed
before allowing th.e RES input to go "High".
This time allows the internal crystal oscillator to stabilize.
Connecting a capacitor to the RES input, as shown in Figure 8,
typically provides sufficient delay.
A, 40
A. 39
T
As 38
A.~
2.21'F
XTAL
A, 36
C
r
A, 35
A, 34
EXTAL
+9V
An
HD6805V1.
B,~
B. 31
NUM
V CC
.P"O~l
33011
J. ". i..
It:.
9
.A.A."
B• 29
C,
B, 26
C,
Bn 25
13
c.
14 C,
j0,tc0v
15
1°.l~
vvv
c.
16
C,
V cc :
vss :
B,~
Co
B, 27
~
10kO
B, 30
~ 010
C,
.p,.,ort r.:. ~"
J..32},:i \!!: ~ 12
vv
{ok'ov
~
8 TIMER (Resistor option)
Re f e rt 0 F, gure 9
Pin 4
P,n 1
Figure 6 Self Check Connections
~Pin
Intllrn.1
Rll$l!t
----------------~
Figure 7 Power Up and RES Timing
202
~HITACHI
about crystal option
--------------------~--------------------------------------------HD6805Vl
•
INTERNAL OSCILLATOR OPTIONS
The internal oscillator circuit is designed to require a minimum of external components. A crystal, a resistor, a jumper
wire, or an external signal may be used to generate a system
clock with various stability/cost tradeoff. A manufacturing
mask option is required to select either the crystal oscillator or
the RC oscillator circuit. The different connection methods are
shown in Figure 9. Crystal specifications are given in Figure 10.
A resistor selection graph is given in Figure II.
2
Part of
HD6805V1
MCU
Figure 8 Power Up Reset Delay Circuit
6
4 MHz c:::J
max
6 XTAL
XTAL
HD6805V1
5 EXTAL
5 EXTAL
HD6805V1
MCU
MCU
Crystal
Approximately 25% Accuracy
External: Jumper
Vee
6
XTAL
~'
6 XTAL
v',/'\,,----t
R
External
Clock
Input
5 EXTAL
HD6805V1
5 EXTAL
MCU
HD6805V1
MCU
No
Connection
External Clock
Approximately 15% Accuracy
External Resistor
CRYSTAL OPTIONS
RESISTOR OPTIONS
Figure 9 Internal Oscillator Options
5
,
XTAL~' ~~
6
C-
I
j~
C,
KS
o
I
I
AT - Cut Parallel Resonance Crystal
C" = 7 pF max.
1= 4 MHz
RS = 60 H max.
EXTAL
5
\,
I
~
3
\
f
'~"
u.
2
J
Vee = 5.25V
TA = 25°C -
4
"'- ~
~ ............
~
Figure 10 Crystal Parameters
o
5
10
15
20
25
30
Resistance Ikn)
35
40
,
45
50
Figure 11 Typical Resistor Selection Graph
~HITACHI
203
HD6805V1------------------------------------------------------------
1- I
7F -SP
Stack
PC,X,A,CC
o -DDR's
CLR INT Logic
FF - Timer
7 F _ Pre scaler
7F _ TCR
Y
TIMER
Load PC From
Reset :$FFE, $FFF
Load PC From
SWI :$FFC, $FFD
J1iJT:$FFA, $FFB
TIMER :$FF8,$F F9
Fetch
Instruction
Y
SWI
Execute
Instruction
Figure 12 Interrupt Processing Flowchart
Data
Direction
Register
Bit
Output
Data Bit
Output
State
Input to
MCU
o
o
o
3·State
Pin
1
Figure 13 Typical Port I/O Circuitry
204
~HITACHI
o
-----------------------------------------------------------------HD6805V1
•
INTERRUPTS
The CPU can be interrupted three different ways: through
the external interrupt (INT) input pin, the internal timer interrupt request_ and a software interrupt instruction (SWI). When
any interrupt occurs, processing is suspended, the present CPU
state is pushed onto the stack, the interrupt bit (I) in the Condition Code Register is set, the address of the interrupt routine is
obtained from the appropriate interrupt vector address, and the
interrupt routine is executed. The interrupt service routines
normally end with a return from interrupt (RTI) instruction
which allows the CPU to resume processing of the program
prior to the interrupt. Table 1 provides a listing of the interrupts, their priority, and the vector address that contain the
starting address of the appropriate interrupt routine.
A flowchart of the interrupt processing sequence is given
in Fig. 12.
Table 1 Interrupt Priorities
Priority
Vector Address
$FFE and $FFF
mT
12
3
TIMER
4
$FFB and $FF9
Interrupt
~
SWI
$FFC and $FFD
$FFA and $FFB
outputs. Port A is CMOS compatible as outputs, and Port Band
C lines are CMOS compatible as inpu ts. Figure 14 provides some
examples of port connections.
• INPUT
Port 0 can be used ,as either 8 TTL compatible inputs or 1
threshold input and 7 analog inputs pins. Fig. 15 (a) shows the
construction of port O. The Port 0 register at location $003
stores TTL compatible inputs, and those in location $007 store
the result of comparison Do to 06 inputs with 07 threshold
input. Port 0 has not only the conventional function as inputs
but also voltage-comparison function. Applying the latter, can
easily check that 7 analog input electric potential max. exceeds
the limit with the construction shown in Fig. 15 (b). Also, using
one output pin of MCU, after external capacity is discharged
at the preset state, charge the CR circuit of long enough time
constant, apply the charging curve to the 07 pin. The construction described above is shown in Fig. 15 (c). The compared
result of Do to 06 is regularly monitored, which gives the
analog input electric potential' applied to Do to 06 pins from
inverted time. This method enables 7 inputs to be converted
from analog to digital. Furthermore, combination of two func.
tions gives 3 level voltages from Do to 06. Fig. 15 (d) provides
the example when VTH is set to 3.5V.
• BIT MANIPULATION
•
INPUT/OUTPUT
There are 24 input/output pins. All pins are programmable
as either inputs or outputs under software control of the cor·
responding Data Direction Register (DOR). When programmed
as outputs, the latched output data is readable as input data,
regardless of the logic levels at the output pin due to output
loading (see Fig. 13). When Port B is programmed for outputs
it is capable of sinking lOrnA on each pin (VOL = 1V max).
All input/output lines are TTL compatible as both inputs and
The MCU has the ability to set or clear any single random
access memory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines. The example in Figure 16
illustrates the usefulness of the bit manipulation and test
Ao
Port A
···
·· '·inLI
Port B
mA Load
A,
Port A Programmed as outputls), driving CMOS and TTL Load directly.
la)
Port B Programmed as output Is). driving Darlington base directly.
Ib)
+V
+v
R
Port B
···••
·
-
t - - - -....-
Port C
CMOS Inverter
10mA max
8,
C7
Port B Programmed as output Is), driving LEDls) directly.
Ic)
Port C Programmed as outputls), driving CMOS loads, using external pull·up
resistors.
Id)
Figure 14 Typical Port Connections
$
HITACHI
205.
HD6805V1---------------------------------------------------------------vides tum-on of the TRIAC within 14 microseconds of the zero
crossing. The timer could also be incorporated to provide tumon at some later time which would permit pulse-width modUlation ofthe controlled power.
instructions. Assume that bit 0 of port A is connected to a zero
crossing detector circuit and that bit 1 of port A is connected to
the trigger of a TRIAC which power the controlled hardware.
This program, which uses only seven ROM locations, pro-
$003 Raad
Internal Bus
(BitO - Bit6)
+
$003 Read
Input Port (0 7 )
Internal Bus
(Bit 7)
(a) The logic configuration of Port 0
Port
C
0
1--"",-,- - - Reference Level
0
1-.;..'---- Analog Input 6
0,
Port
o
Port
o
0,
\--";""'--Analog Input 6
Do
0
I-~---
1-...;;.°_ _ Analog Input 0
(b) Seven analog inputs and a reference level input of Port 0
Analog Input 0
(c) Application to AID convertor
Q,
VTH (= 3.5V)
0,
Port
3 Levels Input 6
~
0
Do
Input
Voltage
($003)
($007)
OV -0.8V
0
0
2.0V - 3.3V
1
0
3.7V - Vee
1
1
3 Levels Input 0
(d) Application to 3 levels input
Figure 15 Configuration and Application of Port 0
206
~HITACHI
---------------------------------------------------------------HD6805V1
SELF 1
•
··
··
Bit Set/Clear
Refer to Figure 24. This mode of addressing applies to
instructions which can set or clear any bit on page zero. The
lower three bits in the opcode specify the bit to be set or
cleared while the byte following the opcode specifies the
address in page zero.
BRClR 0, PORT A, SELF 1
BSET 1, PORT A
BelR 1, PORT A
•
Bit Test and Branch
The CPU has ten addressing modes available for use by the
programmer. They are explained and illustrated briefly in the
following paragraphs.
Refer to Figure 25. This mode of addressing applies to
instructions which can test any bit in the first 256 locations
($OO·$FF) and branch to any location relative to the Pc. The
byte to be tested is addressed by the byte following the opcode.
The individual bit within that byte to be tested is addressed by
the lower three bits of the opcode. The third byte is the relative
address to be added to the program counter if the branch condi·
tion is met. These instructions are three bytes long. The value of
the bit tested is written to the carry bit in the condition code
register.
•
•
··
·
Figure 16 Bit Manipulation Example
•
ADDRESSING MODES
Immediate
Refer to Figure 17. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte following the
opcode.
•
Direct
Refer to Figure 18. In direct addressing, the address of the
operand is contained in the second byte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. All RAM space, I/O registers and 128
bytes of ROM are located in page zero to take advantage of this
efficient memory addressing mode.
•
Extended
Refer to Figure 19. Extended addressing is used to reference
any location in memory space. The EA is the contents of the
two bytes following the opcode. Extended addressing instruc·
tions are three bytes long.
•
Relative
Refer to Figure 20. The relative addressing mode applies only
to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA=(pC)+2+Rel. Rei is the contents
of the location following the instruction opcode with bit 7
being the sign bit. If the branch is not taken Rel=O, when a
branch takes place, the program goes to somewhere within the
range of + 129 bytes to -127 of the present instruction. These
instructions are two bytes long.
•
Indexed (No Offset)
Refer to Figure 21. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and their EA is the contents of the index register.
•
Indexed (8-bit Offset)
•
•
Register/Memory Instructions
Most of these instructions use two operands. One operand is
either the accumulator or the index register. The other operand
is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR)
instructions have no register operand. Refer to Table 2.
•
Read/ModitvlWrite Instructions
These instructions read a memory location or a register,
modify or test its contents, and write the modified value back
to memory or to the register. The test for negative or zero
(TST) instruction is an exception to the read/modify/write
instructions since it does not perform the write. Refer to Table
3.
•
Branch Instructions
The branch instructions cause a branch from the program
when a certain condition is met. Refer to Table 4.
•
Bit Manipulation Instructions
These instructions are used on any bit in the first 256 bytes
of the memory. One group either sets or clears. The other group
performs the bit test and branch operations. Refer to Table 5.
•
•
•
Refer to Figure 23. This addressing mode calculates the EA
by adding the contents of the two bytes following the opcode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are three
bytes long.
INSTRUCTION SET
The MCV has a set of 59 basic instructions. They can be
divided into five different types: register/memory, read/modify/
write, branch, bit manipulation, and control. The following
paragraphs briefly explain each type. All the instructions within
a given type are presented in individual tables.
Refer to Figure 22. The EA is calculated by adding the
contents of the byte following the opcode to the contents of
the index register. In this mode, 5 II low memory locations are
accessable. These instructions occupy two bytes.
Indexed (16-bit Offset)
Implied
Refer to Figure 26. The implied mode of addressing has no
EA. All the information necessary to execute an instruction is
contained in the opcode. Direct operations on the accumulator
and the index register are included in this mode of addressing.
In addition, control instructions such as SWI, RTI belong to this
group. All implied addressing instructions are one byte long.
Control Instructions
The control instructions control the MCU operations during
program execution. Refer to Table 6.
Alphabetical Listing
The complete instruction set is given in alphabetical order in
Table 7.
•
OpcodeMap
Table 8 is an opcode map for the instructions used on the
MCV.
~HITACHI
207
HD6805V1---------------------------------------------------------------
Memory
i
I
I
I
I
8
:::1 :
A
Fa
Ind
PROG LOA #$F8
L
Stack Point
I
I
I
1
Prog Count
05CO
CC
I
•
§
I
•
I
Figure 17 Immediate Addressing Example
lEA
+
Memory
I
i
•
I•
I
I
I
I
•I
I
CAT
FC8
32
r
~
/'
Adder
20
0048
1
0048
~
~
A
~
20
I
Index Reg
I
I
I
PROG
LOA
CA T
0520
86
052E
48
Stack Point
I
I
Prog Count
I
052F
CC
~
I
I
I
I
Figure 18 Direct Addressing Example
208
~HITACHI
I
I
I
-----------------------------------------------------------------HD6805V1
,,
Memory
••
•
~
PROG
LOA
CAT
FCB
64
A
~~J
O4OA
06
040B
E5
40
Index Reg
Stack Point
••
•
•
CAT
0000
Prog Count
040C
40
O6E5
CC
Figure 19 Extended Addressing Example
Memory
,i
@
•
27
04A8
A
I.
Index Reg
Stack Point
0000
18
§
I,
I,
Figure 20 Relative Addressing Example
~HITACHI
209
HD6805V1-------------------------------------------------------------
Memorv
A
TABL
FCC
t Lit OOBB
4C
4C
49
Index Reg
B8
I
PROG
LOA
X
I
Stack Point
~F4~
Prog Count
05F5
CC
§
Figure 21
Indexed (No Offset) Addressing Example
lEA
Melorv
i
I
i
I
FeB
#BF
0089
BF
FeB
#86
OO8A
86
FeB
#OB
oo8B
DB
FCB
#CF
008C
CF
i
I
/
I
OO8C
t
I
I
TABL
I
Adder
~
~
A
J
I
I
CF
I
Index Reg
I
I
I
03
I
Stack Point
PROG
LOA
TABl. X 075B
E6
075C
89
I
I
I
I
§
Figure 22 Indexed (S·Bit Offset) Addressing Example
210
I
I
Prog Count
~HITACHI
0750
CC
I
-----------------------------------------------------------------HD6805Vl
Memory
i
I
§
PROG
lOA
TABL. X::
A
DB
EB
Index Reg-
02
Stack Point
06M~t----~
ProgCount
0695
I
TABl
CC
I
BF
FCB
#BF
OnE
FCB
#86
OnF
86
FCB
#OB
0780
DB
FCB
#CF
0781
CF
Figure 23 Indexed (16·Bit Offset) Addressing Example
Memory
PORT BEau
BF
0001
I
A
0000
Index Reg
PROG BelR 6. PORT B
058F
0590
.------t
10
Stack Point
01
Prog Count
0591
I
I
CC
~
I
I
I
Figure 24 Bit Set/Clear Addressing Example
$
HITACHI
211
H D6805V 1 -~-
PORT C
EQU
A
2
Index Reg
Stack Point
Prog Count
PROG BRCLR 2. PORT C. PROG 2
0594
CC
I
§
I
. Example
Figure 25 B·It T est and Branch Add ressmg
EA
Memorv
I
I
I
§
PROG
TAX
A
II
I
I
I
05BA~
05BB
CC
I
I
I
I
I
I
~
I
I
_ _ _ _ _-J.I
Figure 261m p I·led Addressing E xample
212
~HITACHI
-----------------------------------------------------------------HD6805V1
Table 2 Register/Memory Instructions
Addressing Modes
-Function
Mnemonic
Immediate
Indexed
(No Offset)
Extended
Direct
Op
Op
Op
#
#
#
#
Code Bytes Cycles Code Bytes Cycles Code
Op
#
#
8ytes Cycles Code
Indexed
(8·Bit Offset)
#
#
Op
Bytes Cycles Code
Indexed
(16·8it Offset)
#
Op
#
8ytes Cycles Code
#
#
Bytes Cycles
L08d A from Memory
LOA
A6
2
2
B6
2
4
C6
3
5
F6
1
4
E6
2
5
06
3
6
L08d X from Memory
LOX
AE
2
2
BE
2
4
CE
3
5
FE
1
4
EE
2
5
DE
3
6
Store A in Memory
STA
-
-
87
2
5
C7
3
6
F7
1
5
E7
2
6
07
3
7
Store X in Memory
STX
-
-
-
BF
2
5
CF
3
6
FF
1
5
EF
2
6
OF
3
7
Add MOImory to A
ADD
AB
2
2
BB
2
4
CB
3
5
FB
1
4
EB
2
5
DB
3
6
Add Memory and
Carry to A
AOC
A9
2
2
B9
2
4
C9
3
5
F9
1
4
E9
2
5
09
3
6
Subtract Memory
SUB
AO
2
2
BO
2
4
CO
3
5
FO
1
4
EO
2
5
DO
3
6
Subtract Memory from
A with Borrow
sec
A2
2
2
B2
2
4
C2
3
5
F2
1
4
E2
2
5
02
3
6
AND Memory to A
AND
A4
2
2
B4
2
4
C4
3
5
F4
1
4
E4
2
5
04
3
6
OR Memory with A
ORA
AA
2
2
BA
2
4
CA
3
5
FA
1
4
EA
2
5
OA
3
6
Exclusive OR Memory
with A
E06
A8
2
2
B8
2
4
C8
3
5
F8
1
4
E8
2
5
08
3
6
Arithmetic Compare A
with Memory
CMP
Al
2
2
Bl
2
4
Cl
3
5
Fl
1
4
El
2
5
01
3
6
Arithmetic Compare X
with Memory
2
2
B3
2
4
C3
3
5
F3
1
4
E3
2
5
03
3
6
CPX
A3
Bit Test Memory with A
(Logical Compare)
BIT
A5
2
2
B5
2
4
C5
3
5
F5
1
4
E5
2
5
05
3
6
Jump Unconditional
JMP
-
-
BC
2
,3
CC
3
4
FC
1
3
EC
2
4
DC
3
5
Jump to Subroutine
JSR
-
-
-
SO
2
7
CD
3
8
FO
1
7
ED
2
8
DO
3
9
Table 3 Read/Modify/Write Instructions
Addressing Modes
Function
Implied (X)
Implied (A)
Mne!Tlonic
Op
Code
Op
#
#
Bytes Cycles Code
Indexed
(No Offset)
Direct
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(8·Bit Offset)
Op
#
#
Bytes Cycles Code
#
#
Bytes Cycles
Increment
INC
4C
1
4
5C
1
4
3C
2
6
7C
1
6
6C
2
7
Decrement
DEC
4A
1
4
5A
1
4
3A
2
6
7A
1
6
6A
2
7
Clear
CLR
4F
1
4
5F
1
4
3F
2
6
7F
1
6
6F
2
7
Complement
COM
43
1
4
53
1
4
33
2
6
73
1
6
63
2
7
Negate
(2'5 Complement)
NEG
40
1
4
50
1
4
30
2
6
70
1
6
60
2
7
Rotate Left Thru Carry
ROL
49
1
4
59
1
4
39
2
6
79
1
6
69
2
7
Rotate Right Thru Carry
ROR
46
1
4
56
1
4
36
2
6
76
1
6
66
2
7
Logical Shift Left
LSL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
Logical Shift Right
LSR
44
1
4
54
1
4
34
2
6
74
1
6
64
2
7
Arithmetic Shift Right
ASR
47
1
4
57
1
4
37
2
6
77
1
6
67
2
7
Arithmetic Shift Left
ASL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
Test for Negative or
Zero
TST
40
1
4
50
1
4
3D
2
6
70
1
6
60
2
7
~HITACHI
213
HD6805V1--------------------------------------------------------------Table 4 Branch Instructions
Relative Addressing Mode
Mnemonic
Function
Op
Code
#
#
Bytes
Cycles
Branch Always
BRA
20
2
4
Branch Never
BRN
21
2
4
Branch IF Higher
BHI
22
2
4
Branch IF Lower or Same
BLS
23
2
4
Branch I F Carry Clear
BCC
24
2
4
(Branch IF Higher or Same)
(BHS)
24
2
4
Branch IF Carry Set
BCS
25
2
4
(Branch IF Lower)
(BLO)
25
2
4
Branch I F Not Equal
BNE
26
2
4
Branch I F Equal
BEQ
27
2
4
Branch IF Half Carry Clear
BHCC
28
2
4
Branch I F Half Carry Set
BHCS
29
2
4
Branch I F Plus
BPL
2A
2
4
Branch IF Minus
BMI
2B
2
4
Branch IF Interrupt Mask Bit is Clear
BMC
2C
2
4
Branch I F Interrupt Mask Bit is Set
BMS
20
2
4
Branch IF Interrupt line is Low
BIL
2E
2
4
__ ~~~~!~Inte~rup~ line is High
BIH
2F
2
4
BSR
AO
2
8
Branch to Subroutine
Table 5 Bit Manipulation Instructions
Addressing Modes
Mnemonic
Function
Bit Set/Clear
Op
Code
Branch IF Bit n is set
---------------Branch I F Bit n is clear
-----.---~-
Set Bit n
------- "--Clear bit n
Bit Test and Branch
#
#
Bytes
#
#
Cycles
Op
Code
Bytes
Cycles
BRSET n (n=O ..... 7)
-
-
3
10
-
-
2-n
BRCLR n (n=O ..... 7)
.o1+2-n
3
10
BSET n (n=O ..... 7)
10+2-n
2
7
-
BCLR n (n=O ..... 7)
11+2-n
2
7
-
-
-
.--.---~
-----~---
Table 6 Control Instructions
Implied
Function
Mnemonic
Op
Code
#
#
Bytes
Cycles
Transfer A to X
------ - - - - Transfer X to A
----Set Carry Bit
TAX
97
1
2
TXA
9F
1
2
SEC
99
1
2
Clear Carry Bit
CLC
98
1
Set Interrupt Mask Bit
SEI
9B
1
Clear Interrupt Mask Bit
Cli
9A
1
2
2
2
Software Interrupt
SWI
83
1
11
Return from Subroutine
RTS
81
1
6
RTI
80
1
9
RSP
9C
1
2
NOP
90
1
2
Return from Interrupt
--------------Reset Stack Pointer
No·Operation
214
--
~HITACHI
---------------------------------------------------------------HD6805V1
Table 7 Instruction Set
Addressing Modes
Mnemonic
ImmeImplied
diate
ExDirect
tended
Relative
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
Bit
Setl
Clear
Bit
Test &
Branch
x
x
x
x
x
1\
AND
x
x
x
x
x
x
•
•
•
•
•
x
x
x
x
x
x
x
BCC
x
BClR
BCS
x
BEQ
x
BHCC
x
BHCS
x
BHI
x
BHS
x
BIH
x
•
--
x
Bil
x
BIT
x
x
BlS
x
x
x
BMC
BMI
--
- - - - - - - - - e--x
x
x
BlO
--
-------~.
•
•
•
•
•
•
----- --
BMS
x
BNE
x
BPl
x
BRA
x
BRN
x
•
•
x
•
•
--
----
x
x
BRClR
BRSET
x
BSET
x
BSR
x
ClC
CLI
x
ClR
x
x
CMP
x
COM
x
CPX
x
DEC
EaR
INC
x
--
x
x
x
x
x
x
x
x
JSR
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
JMP
x
x
x
x
x
x
x
x
x
lDA
x
x
x
x
x
x
lDX
x
x
x
x
x
x
Condition Code Symbols:
H
Half Carry (From Bit 31
I
Interrupt Mask
N
Negative (Sign Bitl
Z
Zero
/\
/\
/\
/\
/\
/\
•
/\
/\
/\
/\
/\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
/\
/\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
x
x
x
/\
/\
1\
x
x
x
/\
N
ADD
ASl
C
I
ADC
ASR
Iz
H
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• •
• 0
• •
• •
I
• •
• •
•
•
•
•
•
•
•
•
•
•
•
•
•
I •
•
•
•
•
•
•
•
•
•
•
•
•
0
1
/\
/\
•
•
•
/\
/\
•
•
0
•
•
/\
• • /\ /\ 1
• • /\ /\ /\
• • /\ /\ •
• • /\ /\ •
• • /\ /\ •
• • • • •
• • • • •
• • /\ /\ •
• • /\ /\ •
(to be continued)
C
/\
•
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
~HITACHI
215
HD6805V1--------------------------------------------------------------Table 7 Instruction Set
Addressing Modes
Mnemonic
LSL
LSR
NEG
NOP
Implied
Immediate
Direct
Extended
Condition Code
R -----, Indexed
elative
(No
Indexed Indexed
Offset) (8 Bits) (16 Bits)
Bit
Setl
Clear
Bit
Test &
Branch
H
I
N
Z
C
x
x
x
x
x
x
x
x
•
•
•
•
/\
/\
/\
0
/\
/\
x
x
x
x
•
•
/\
/\
/\
x
•
•
•
•
•
/\
•
/\
•
•
x
x
ORA
x
x
x
x
x
x
x
x
•
• 1\ /\ /\
--------~-------~----r_-----+_----~----_4~----_+------+_------+_----r_----_+--_r--~_+--_r--ROR
x
x
x
x
•
• /\ /\ /\
RO L
RSP
x
•
•
•
•
RTI
x
?
?
?
?
?
RTS
x
•
•
•
•
•
SBC
SEC
SEI
/\
/\
/\
x
x
•
•
•
•
1
•
1
•
•
•
/\
/\
•
/\
•
x
STA
x
x
x
x
x
x
x
TAX
x
x
TST
x
TXA
x
x
x
STX
SUB
SWI
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
216
x
x
x
x
x
x
x
x
x
x
x
x
·.
·.
•
x
x
C
1\
•
?
x
Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
1
•
•
• • • • •
• • • • •
-----------------------------------------------------------------HD6805Vl
Table 8
Bit Manipulation
Test &
Branch
Setl
Clear
OIR
3
I
I
A
4
I
I
X
0
1
2
5
0
BRSETO
BSETO
BRA
1
BRCLRO
BCLRO
BRN
-
2 BRSET1
BSET1
BHI
-
I
I
,X1
6
I
I
,XO
7
NEG
3
BRCLR1
BCLR1
BLS
COM
4
BRSET2
BSET2
BCC
LSR
Register /Memory
Control
Read/Modify /Write
Branch
Rei
Opcode Map
IMP
IMP
IMM
I
OIR
\
8
I
EXT
I
,X2
I
\
0
\
)<1
I
,XO
E
I
F
... HIGH
8
9
RTI·
-
SUB
RTS·
-
CMP
1
-
SBC
2
CPX
3
L
-
AND
4
o
SWI·
-
A
\
C
0
5
BRCLR2
BCLR2
BCS
-
-
-
BIT
5 W
6
BRSET3
BSET3
BNE
ROR
-
lOA
7
BRClR3
BCLR3
BEQ
ASR
-
6
7
8 BRSET4
9 BRCLR4
BSET4
BHCC
LSl/ASl
BCLR4
BHCS
ROl
-
TAX
-
I
STA(+1)
ClC
EOR
SEC
AOC
8
9
A
BRSET5
BSET5
BPl
DEC
-
CLI
ORA
B BRClR5
~CLR5
BMI
-
-
SEI
ADD
B
C BRSET6
BSET6
BMC
INC
RSP
J
JMP(-1)
C
0
BSR·j
JSR(-3)
0
A
BRCLR6
BCLR6
BMS
TST
E BRSET7
BSET7
Bil
-
-
F BRCLR7
BCLR7
BIH
CLR
-
TXA
1/·
1/2
3/10
(NOTE)
2/7
2/4
2/6
I
1/4
I
1/4
I 2/7 I 1/6
NOP
-
2/2
1
I
2/4
I
3/5
I
lOX
E
STX(+1)
F
3/6
I
2/5
I 1/4
1. Undefined opcodes are marked with "-".
2. The number at the bottom of each column denote the number of bytes and the number of cycles required (Bytes/Cycles).
Mnemonics followed by a ..... require a different number of cycles as follows:
RTI
9
RTS
6
SWI
11
BSR
8
3. (
indicate that the number in parenthesis must be added to the cycle count for that instruction.
~HITACHI
217
HD6805T2-------------MCU (Microcomputer Unit
with PLL Logic)
-ADVANCE INFORMATIONThe HD680ST2 is the 8·bit Microcomputer Unit (MCU)
which contains a CPU, on.chip clock, ROM, RAM, lID, Timer
and the PLL Logic for an RF synthesizer. It is designed for the
user who needs an economical microcomputer with the proven
capabilities of the HD6800·based instruction set.
The following are some of the hardware and software high.
lights of the MCU.
HD6805T2P
• HARDWARE FEATURES
• 8·Bit Arthitecture
• 64 Bytes of RAM
• Memory Mapped I/O
• 2508 8ytes of User ROM
• Internal 8·Bit Timer with 7·Bit Prescaler
• Timer Start/Stop and Source Select
• Vectored Interrupts - External and Timer
• 19 TTL/CMOS Compatible I/O Lines; 8 Lines are LED com·
patible
• On-Chip Clock Circuit
• Self·Check Mode
• Master Reset
• Low Voltage Inhibit
• 14·Bit Binary Variable Divider
• 10·Stage Mask·Programmable Reference Divider
• Three·State Phase and Frequency Comparator
• Suitable for TV Frequency Synthesizers
• 5" Vdc Single Supply
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SOFTWARE FEATURES
Similar to HD6800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handing
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM, RAM and I/O
Compatible with MC6805T2
(DP·28)
•
PIN ARRANGEMENT
A.
fin
B.
B,
B.
B,
B,
B.
B,
B,
(Top View)
•
BLOCK DIAGRAM
A,
A,
~!
POrt
L.lneI
A
,1(0
A.
As
A.
A·
Pon
B,
B,
BJ
B.
B.
B
I/O
lines
I!
B,
218
c,
c,
$
HITACHI
HD6805W1
MCU
(Microcomputer Unit)
The H0680SWI is an 8-bit microcomputer unit (MCU)
which contains a CPU, on-chip clock, ROM, RAM, standby
RAM, an A/D Converter, I/O and two timers. It is a member of
the H06805 family which is designed for user who needs an
economical microcomputer with proven capabilities of the
HD6800-based instruction set.
The following are some of the hardware and software highlights of the MCU.
HARDWARE FEATURES
8-Bit Architecture
96 Bytes of RAM
(8 bytes are standby RAM functions)
• Memory Mapped I/O
• 3848 Bytes of User ROM
• Internal 8-Bit Timer (Timer 1) with 7-Bit Prescaler
• Internal8-Bit Programmable Timer (Timer 2)
• Interl'upts - 2 External and 4 Timers
• 23 TTL/CMOS compatible I/O Lines; 8 Lines Directly
Drive LEOs.
• On-Chip 8-Bit, 4-Channel A/D Converter
• On-Chip Clock Circuit
• Self-Check Mode
• Master Reset
• Low Voltage Inhibit
• Complete Development System Support by Evaluation Kit
• 5 Vdc Single Supply
-PRELIMINARY-
HD6805W1P
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(DP-40)
•
PIN ARRANGEMENT
SOFTWARE FEATURES
Similar to HD6800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handing
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM, RAM and I/O
Compatible with MC6805P2, HD6805S1 and HD6805V1
~HITACHI
Vss
A,
RAME/RES
INT,
A.
A.
A.
Vee
EXTAL
XTAL
NUM
TIMER
Co
C,
C.
A.
A.
A,
Ao
HD6805Wl
B,
B.
B.
B.
B.
B.
C,
C.
IC/C.
OC/C.
B,
Bo
INT. 100
ANo/D,
AN,/D.
AN./D,
AN,/D.
AVee
AVss
VRH/D.
Vee Standby
(Top View)
219
HD6805W1--------------------------------------------------------------• BLOCK DIAGRAM
TIMER
7
8
Port B
I/O lines
TlMER-2
Prescaler Control
8 Register 2
Timer Data
a Register
Input Capture
8 Register
(lC)
Timer Control
8 Register 2
Port A
I/O Lines
Ao
Ai
A2
As
A.
As
A.
A.
CPU Control
Index Register
a
x
Timer
Status Register 2
Output Compare
(OC)
0
'ij
A
~
'So
~!
co·!!
a:II
oa:
a..
1ii2'
co
0
Bo
B.
B.
Bs
B.
Bs
Condition Code
S Register
CC
a Register 2
a
c
Accumulator
a
7 Presealer 2
CPU
Port C
I/O Lines
Stack Point
6
SP
c
a
Program Counter
4 "High"
:~o!!~
PCH
AlU
Program Counter
a
"low"
Co
C.
c.
Cs
ta·!!
0
C.
oa:
0
a..
C s (lC)
C. (OC)
1ii2'
PCl
~
'r
a:
~-~-...,
!!
'&'
I»
a:
«
0
a..
c
Port 0
Input Lines
0
'~
...
o!!
.~
!!
Do
D.
O2
0,
D.
Os
,s.
"'II
oa:
(RAME) Vee Standby
(INT.)
(AN o )
(AN.)
(AN.)
(AN,)
(VRH)
ADC Lines
AVee
AVSS
(VRH)
(AN o)
(ANd
(AN 2 )
(AN,)
A/D Control
Status Register
a
AID Result
a
(NOTE)
220
$
HITACHI
Register
The contents of ( ) items can be changed by software,
-----------------------------------------------------------------HD6805W1
•
ABSOLUTE MAXIMUM RATINGS
Symbol
Item
Supply Voltage
Input Voltage (EXCEPT TIMER)
V in
Input Voltage (TIMER)
Unit
Value
Vee
-0.3 - +7.0
V
-0.3 - +7.0
V
-0.3 - +12.0
V
Operating Temperature
T opr
o -+70
°c
Storage Temperature
T stg
-55 - +150
°c
(NOTE)
This device has an input protection circuit for high quiescent voltage and field, however, be careful not
to impress a high input voltage than the insulation maximum value to the high input impedance circuit.
To insure normal operation, the following are recommended for Vin and V out :
VSS ~ (V in or V out ) ~ Vee
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee = 5.25V ±O.5V, Vss = GND, Ta = O-+70°C, unless otherwise noted.)
typ
max
Unit
RES
4.0
-
Vee
V
INT I ,INT 2
3.0
-
Vee
V
2.0
-
Vee
V
Timer Mode
2.0
Self-Check Mode
9.0
Vee
11.0
V
0.8
V
Test Condition
Symbol
Item
Input "High" Voltage
V IH
All Others
Input "High" Voltage Timer
Input "Low" Voltage
RES
-0.3
-
INT I ,INT 2
-0.3
-
0.8
V
-0.3
-
0.8
V
V IL
All Others
(except EXTAL)
V
Po
LVR
-
-
750
mW
Low Voltage Recover
-
4.75
V
Low Voltage Inhibit
LVI
-
4.0
-
V
-20
-
20
p.A
50
p.A
0
p.A
Power Dissipation
TIMER
Input Leak Current
Standby Voltage
Standby Current
•
min
V in =0.4V-V ee
-50
INTI,INT2
EXTAL(Crystal Mode)
IlL
Nonoperation Mode
V SBB
4.0
Operation Mode
V SB
4.75
Nonoperation Mode
ISBB
-1200
VSBB=4.0V
Vee
Vee
V
-
3
min
typ
max
Unit
0.4
-
4.0
MHz
1.0
-
10
p.s
-
3.4
-
MHz
-
mA
AC CHARACTERISTICS (Vee = 5.25V ±O.5V, Vss = GND, Ta::: O-+70°C, unless otherwise noted.)
Item
Symbol
Test Condition
Clock Frequency
fel
Cycle Time
teye
Oscillation Frequency (External Resistor Mode)
fexT
TNil Pulse Width
tlWL
t eye +
250
-
-
ns
RES Pulse Width
tRWL
t eye +
250
-
-
ns
TIMER Pulse Width
tTwL
t eye +
250
-
-
ns
-
-
100
ms
100
-
-
ms
35
pF
-
10
pF
R ep =15.0kU±1%
Oscillation Start-up Time (Crystal Mode)
tose
C L =22pF±20%
Rs=60U max.
Delay Time Reset
tRHL
External Cap. = 2.2 p.F
I nput Capacitance
I
I
XTAL, VRH/Ds
All Others
Cin
Vin=OV
~HITACHI
-
221
HD6805Wl--------------------------------------------------------------•
PORT ELECTRICAL CHARACTERISTICS (Vee = 5.25V ±O.5V. Vss = GND. Ta = 0'" +70°C. unless otherwise noted.)
Symbol
Item
Port A
Output "High" Voltage
Output "Low" Voltage
Input "High" Voltage
Input "Low" Voltage
Input Leak Current
V OH
Port B
Test Condition
typ
max
Unit
3.5
-
-
V
IOH = -looJ.LA
2.4
-
IOH = -200 J.LA
2.4
IOH = ·1 mA
1.5
Port C
IOH=-l00J.LA
2.4
Ports A and C
IOL = 1.6 mA
-
IOL = 3.2 rnA
-
IOL = 10 mA
VOL
Port B
V IH
Ports A. B. C
and D
Port A
IlL
Yin
= 0.8V
Yin
= 2V
Yin
= 0.4V-V ee
---0.5
Item
Analog Input Voltage
Reference Voltage
Symbol
V
V
-
1.0
V
2.0
-
Vee
0.8
V
-0.3
-
-300
-
V
J.LA
------- -------- . _ - -
--.- 1-------- ~-.
-20
V
J.LA
---- ---- . - - - - 20
J.LA
._-
=0 -
+70°C. unless
min
typ
AVec
4.75
5.25
AV in
0
-
4.0
4.0
-
Vee
5.25
V
-
-
7.5
pF
V RH
Test Condition
4.75V ~ Vee ~ 5.25V
5.25V
< V ee ~ 5.75V
Analog Multiplexer Input
Capacitance
Resolution Power
Conversion Time
V
0.5
AID CONVERTER ELECTRICAL CHARACTERISTICS (Vee = 5.25V±O.5V. Vss = AVSS = GMD. Ta
otherwise noted.)
Analog Power Supply
Voltage
V
V
-
-500
V IL
Ports B. C and D
•
min
IOH =-10J.LA
at 4MHz
I nput Channels
max
Unit
5.75
V
V RH
V
V
-
8
-
76
76
76
Bit
tCYC
4
4
4
Channel
Absolute Accuracy
Ta = 25°C
-
-
±1.5
LSB
Off-channel Leak Current
AV in = 5.0V. AVec =4.75V. Ta= 25°C.
On-channel
AV in =OV
-
10
100
nA
Off-channel Leak Current
AV in = OV. AVec = 4.75V. Ta = 25°C.
On-channel
AV in =5V
-100
-10
-
nA
222
~HITACHI
---------------------------------------------------------------HD6805W1
TTL Equiv. (Port B)
TTL Equiv. (Ports A, C and D)
Vee
Vee
Ii = 3.2mA
1.4kn
2.4kH
Test Point
Test Point
Vi
Vi
40 pF
(NOTE)
30 pF
12 kn
1. Load capacitance includes the floating capacitance of the probe and the jig etc.
2. All diodes are 152074(9 or equivalent.
Figure 1 Bus Timing Test Loads
•
• Vee Standby
SIGNAL DESCRIPTION
The input and output signals for the MCU, shown in PIN
ARRANGEMENT, are described in the following paragraphs.
•
Vee and Vss
Voltage is supplied to the MCV using these two pins. Vee is
5 .25V ±O.5V. V55 is the ground connection.
•
INT J /INT 2
This pin provides the capability for asynchronously applying
an external interrupt to the MCU. Refer to INTERRUPTS
for additional information.
•
XTAL and EXTAL
These pins provide connections for the on-chip clock circuit.
A crystal (AT cut, 4 MHz maximum), a resistor or an external
signal can be connected to these pins to provide a system clock
with various stability/cost tradeoffs. Refer to INTERNAL OSCILLATOR OPTIONS for recommendations about these inputs.
•
TIMER
•
RES
•
NUM
•
I/O Lines (Ao ..... A 7 , 8 0
This pin allows an external input to be used to count for the
internal timer circuitry. Refer to TIMER 1 and TIMER 2 for
additional information about the timer circuitry.
Vee Standby provides power to the standby portion of the
RAM and the STBY PWR and RAME bits of the RAM Control
Register. Voltage requirements depend on whether the MCU
is in a powerup or powerdown state. In the powerup state, the
power supply should provide Vee and must reach VSB before
RES reaches 4.0V. During powerdown, Vee standby must
remain above VSBB (min) to sustain the standby RAM and
STBY PWR bit. While in powerdown operation, the standby
current will not exceed ISBB'
It is typical to power both Vee and Vee Standby from the
same source during normal operation. A diode must be used
between them to prevent supplying power to Vee during
powerdown operation shown Figure 2.
To sustain the standby RAM during powerdown, the following software or hardware are needed.
(I) Software
When clearing the RAM Enable bit (RAME) which is bit 6
of the RAM Control Register at location $OOIF, the RAM
is disabled.
Vee Standby must remain above V SSB (min).
(2) Hardware
When RAME pin is "Low" before powerdown, the RAM is
disabled. Vee Standby must remain above VSBS (min).
This pin allows resetting of the MCV at times other than the
automatic resetting capability already in the MCV. Refer to
RESETS for additional information.
This pin is not for user application and should be connected
to VSS.
.....
8 7 , Co ..... C6 )
There 23 lines are arranged into three ports (A, B and C). All
lines are programmable as either inputs or outputs under software control of the Data Direction Register (DDR). Refer to
INPUT/OUTPUT for additional information.
•
Input Lines (Do ..... Os)
These are TTL compatible input lines, in location $003.
These also allow analog inputs to be used for an AID converter.
Refer to INPUT for additional information.
Figure 2 Battery Backup for Vee Standby
•
RAME
This pin is used for the external control of the RAM. When
it is "Low" before powerdown, the RAM is disabled. If Vee
Standby remains above V SBB (min), the standby RAM is
sustained.
~HITACHI
223
HD6805W1,--------------------------------------------------------------•
AVec
This pin is used for the power supply of the AID converter.
When high accuracy is required, a different power source from
V cc is impressed as
AVec =5.25 ± O.SV
Connect to Vee for all other cases.
• ANo - AN3
These pins allow analog inputs to be used for an AID converter. These inputs are switched by the internal multiplexer
and selected by bit 0 and 1 of the AID Control Status Register
(ADCSR: $OOE).
• VAH and AVss
The input teJminal reference voltage for the AID converter is
"High" (VRH) or "Low" (AVss). AVss is fixed at OV.
•
•
MEMORY
The MCV memory is configured as shown in Figure 3. During
the interrupt processing, the contents of the CPU registers are .
pushed onto the stack in the order shown in Figure 4. Since
the stack pointer decrements during pushes. the low order byte
(PCl) of the program counter is stacked first; then the high
order three bits (PCH) are stacked. This ensures that the program counter is loaded correctly as the stack pointer increments
when it pulls data from the stack. A subroutine call will cause
only the program counter (PCH. PCl) contents to be pushed
onto the stack.
Input Capture (lC)
This pin is used for input of Timer 2 control, in this case,
Port C 5 should be configured as input. Refer to TIMER 2
for more details.
•
Compare Register is matched with the Timer Data Register
2. In this case, Port C6 should be configured as an output.
Refer to TIMER 2 for more details.
Output Compare IOC)
This pin is used for output of Timer 2 when the Output
000
Caution: - Self Test ROM Address Area
Self test ROM locations can not be used for a user program.
If the user's program is in this location, it will be removed when
manufacturing mask for production.
sooo
I/OPor1S
Port A
SOOO
Port B
SIlO I
Pone
SIlO2
Pon 0
SIlO3"
Por1 A OOR
~.
Tuner
SOIF
S020
031
032
RAM
196 81
127
128
SIlOS'
Pall 8 OOA
S07F
S080
$006'
POtl C DOR
SIlO 7
Timer Oal.Reg.l
$008
Timer CTAL Rig 1
ROM
13834 81
$009
_ _ SOOA
~neousRf!9.
1 - - - - . - - - - - - SIlO8
1--_ _ _._ _ _ _ _-l SllOC
1-______________ $000
AID CTAL Slllus Req
SODE
AID Result Reg
SOOF ••
I -____________~SOIO
1-_____________~SOl1
~---- ..- - - - - - _ _ 1 S 0 1 2
f----._________~SOI3
1-_____________1$01.
1-_ _ _ _ _ _ _ _ _ SOlS
~-----------_
S016
1-_____________1$017
1-____________1$018
:~~-------~ :::~
$019
Tim., Stilus Reg, 2
S01A-·
Tlrner CTRL Reg 2
SOl B
Tuner 011. R.g. 2
SOle
Output Comp.f. Rev
S010
\1-_...:.,:;::np.:.:.U'..::C",:::.:,.:.:.u":.;.R;:::I9~_ _..... S01E· •
~-~R=AM~C=O~""..::OI~R~.g---~:~
Soli· .... ROM 112081
____S~.:d~Y ~~~I~ ~~~ ____
.0811-_ _ _ _ _ _ _~ ,FFI
.082
Prne.I" CTRL Reg, 2
RAM 196 81
~.FFF
·W,II,R..
··R,adRII·
•• 'SI-"dby RAM UMI htll 8 by,..
Figure 3 MCU Memorv Structure
224
OCk
S'I
~
' - -_ _ _ _ _-..I._ _.....I107F
In"""1)1 Vector.
.0000'--_ _ _ _ _ _ _
1O~7
1028
.FF2
~HITACHI
o' RAM
-----------------------------------------------------------------HD6805W1
5
n-4
, , ,1
4
0
Condition
Code Register
n +'
n+2
Accumu lator
n-3
n-2
Inde~
n-'
n+3
Register
,,,,
'1
• Stack Pointer (SP)
The stack pointer is a l2-bit register that contains the address
of the next free location on the stack. Initially. the stack pointer is set to location $07F and is decremented as data is being
pushed onto the stack and incremented while data is being
pulled from the stack. The six most significant bits of the stack
pointer are permanently set to 00000 I. During an MeU reset
or reset stack pointer (RSP) instruction. the stack pointer is
set to location $07F. Subroutines and interrupts may be nested
down to location $041 which allows the programmer to use up
to 31 levels of subroutine calls.
Pull
n+4
PCH"
PCL"
n+5
Pu sh
" For subroutine calls, only PCH and PCL are stacked
Figure 4 Interrupt Stacking Order
REGISTERS
The CPU has five registers available to the programmer,
as shown in Figure 5 and explained below.
• Condition Code Register (CC)
The condition code register is a 5-bit register in which each
bit is used to indicate or flag the results of the instruction just
executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each individual condition code register bit is explained below.
•
0
I
A
Interrupt (I)
This bit is set to mask everything. If an interrupt occurs
while this bit is set. it is latched and will be processed as soon as
the interrupt bit is reset.
Accumulator
0
X
"
I
I
0
I
Inde~
Register
0
PC
6 5
"
10101010101,1
SP
Half Carry (H)
The half carry bit is used during arithmetic operations (ADD
or ADC) to indicate that a carry occurred between bits 3 and 4.
Negative (N)
The negative bit is used to indicate that the result of the last
arithmetic. logical or data manipulation was negative (bit 7 in
a result equal to a logical one).
Program Counter
Stack Pointer
Condition Code Register
Carry!Borrow
Zero
Negative
Interrupt Mask
Zero (Z)
Zero is used to indicate that the result of the last arithmetic.
logical or data manipulation was zero.
Carry/Borrow (C)
Carry/borrow is used to indicate that a carry or burrow out
of the arithmetic logic unit (ALU) occurred during the last
arithmetic operation. This bit is also affected during bit test and
branch instructions. shifts and rotates.
Half Carry
Figure 5 Programming Model
• Accumulator (A)
The accumulator is a general purpose 8-bit register used to
hold operands and results of arithmetic calculations or data
manipulations.
•
Index Register (X)
The index register is an 8-bit register used for the indexed
addressing mode and contains an 8-bit address that may be
added to an offset value to create an effective address. The
index register can also be used for limited calculations or data
manipulations when using read/modify/write instructions. When
not required by a code sequence being executed. the index
register can be used as a temporary storage area.
•
Program Counter (PC)
The program counter is a 12-bit register that contains the
address of the next instruction to be executed.
• TIMER 1
The MCU timer circuitry is shown in Figure 6. The 8-bit
counter, Timer Data Register I (TOR 1), is loaded under program control and counts down toward zero as soon as the clock
input is applied. When the TORI reaches zero, the timer interrupt request bit (bit 7) in the Timer Control Register I (TCRI)
is set. The CPU responds to this interrupt by saving the present
CPU state in the stack, fetching the timer I interrupt vector
from locations $FF8 and $FF9 and executing the interrupt
routine. The timer I interrupt can be masked by setting the
timer interrupt mask bit (bit 6) in the TCRI. The interrupt
bit (I bit) in the Condition Code Register also prevents a timer I
interrupt from being processed.
The clock input to the timer I can be from an external
source applied to the TIMER input pin or it can be the internal
cf>z signal. When cf>z is used as the source, it can be gated by an
input applied to the TIMER input pin allowing the user to
easily perform pulse-Width measurements. The timer I continues to count past zero, falling through to $FF from zero
and then continuing the count. Thus, the counter (TDRI)
can be read at any time by reading the TDRI. This allows a
~HITACHI
225
HD6805W11--------------------------------------------------------------program to determine the length of time since a timer interrupt
has occurred and not disturb the counting process.
At power-up or reset, the prescaler and the counter (TORI)
are initialized with all logical ones; the timer 1 interrupt request
bit (bit 7) is cleared and the timer 1 interrupt mask bit (bit 6)
is set. In order to release the timer 1 interrupt, bit 7 of the
TCRI must be cleared by software.
(NOTE) If the MCV Timer 1 and Timer 2 are not used, the
TIMER input pin must be grounded.
(lnternel Clock)
~2--+--L..J
3
TimeOut
Write
Read
Figure 6 Timer Clock
• Timer Control Register 1 (TCR1: $(09)
The Timer Control Register 1 (TCRI) can control selection
of clock input source and prescaler dividing ratio and timer
interrupt.
interrupt at "0" and masks at "1". Timer 1 interrupt causes
Timer 1 interrupt request bit (TIF) to be set. TIF must be
cleared by software.
Table 1 Selection of Clock Input Source
Timer Control Register 1 (TCR 1: $009)
TCRl
76543210
Bit 5
Bit 4
0
0
0
1
0
I TIFITIMI151 1 150 VlM521M511Msoi
. .
L
.
Clock Input Source
~
Prescaler Dividing Ratio
Event Input From TIMER
1
• The TIMER input pin must be tied to Vee. for uncontrolled tP2
clock input.
Table 2 Selection of Prescaler Dividing Ratio
Timer Interrupt Mask
' - - - - - - - - - - - Timer Interrupt Request Flag
Bit 2
As shown in Table I, the selection of the clock input source
is ISO. and lSI in the TCRl (bit 4 and bit 5) and 3 kinds of
input are selectable. At reset, internal clock q,2 controlled by
the TIMER input (bit 4=1 , bit5=O) is selected.
The prescaler dividing ratio is selected by MSO, MSI, and
MS2 in the TCRI (bit 0, bit I, bit 2) as shown in Table 2. The
dividing ratio is selectable from eight ways (+1, +2, +4, +8,
+16, +32, +64, +128). At reset, +1 mode is selected. The prescaler is initialized by writing in the TDRI.
Timer 1 interrupt mask bit (TIM) allows the Timer 1 into
226
--
Internal Clock q,'J *
q,2 Controlled by TIMER Input
1
1
Clock Input Source
TCRl
Bit 1
BitO
0
1
Q
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
1
_HITACHI
1
1
1
1
Prescaler Dividing Ratio
+1
+2
+4
+8
+16
+32
+64
+ 128
---------------------------------------------------------------HD6805W1
• TIMER 2
The HD680SWI includes an 8-bit programmable timer
(Timer 2) which can not only measure the input waveform but
also generate the output waveform. The pulse width for both
input and output waveform can be varied from several microseconds to several seconds.
(NOTE) If the MCV Timer I and Timer 2 are not used, the
TIMER input pin must be grounded.
Timer 2 hardware consists of the followings.
• an 8-bit control register 2
• an 8-bit status register 2
• an 8-bit timer data register 2
• an 8-bit output compare register
• an 8-bit input capture register
• as-bit prescaler control register 2
• a 7-bit pre scaler 2
A block diagram of the timer 2 is shown in Figure 7.
Output Compare Register
(OCR: $010)
8
8 bit Register
L...._ _ _ _ _....J Read/Write
Input Capture Register (lCR: $01E)
8 bit Register
8
Read
Timer Control Register 2
(TCR2: $018)
ICI
OCI TOI
Internal Interrupts Request·Signal
Figure 7 Block Diagram of Timer 2
• Timer Data Register 2 (TDR2: $01C)
The main part of the Timer 2 is the 8-bit Timer Data Register
2 (TDR2) as free-running counter, which is driven by internal
clock 2 or the TIMER input and increments the value. The
values in the counter is always readable by software.
The Timer Data Register 2 is Read/Write register and is
cleared at reset.
• Output Compare Register (OCR: $01 D)
The Output Compare Register (OCR) is an 8-bit Read/
Write register used to control an output waveform. The contents
of this register are always compared with those of the TDR2.
When these two contents conform to each other, the flag (OCF)
in the Timer Status Register 2 (TCR 2) is set and the value of
the output level bit (OLVL) in the TCR2 is transferred to Port
C6 (OC).
If Port C6 's Data Direction Register (DDR) is "1" (ou tpu t),
this value will appear at Port C6 (OC). Then the values of OCF
and OLVL can be changed for the next compare. The OCR is
set to $FF at reset.
• Input Capture Register OCR: $01E)
The Input Capture Register (lCR) is an 8-bit Read-only register used to store the value of the TDR2 when Port Cs (IC)
input transition occurs as defined by the input edge bit (IEDG)
of the TCR2.
In order to apply Port Cs (lC) input to the edge detect
circuit, the DDR of Port Cs should be cleared ("0"). *
To ensure an input capture under all condition, Port Cs (IC)
input pulse width should be 2 Enable-cycles at least.
*The edge detect circuit always senses Port Cs (IC) even if the
DDR is set with Port Cs output.
~HITACHI
227
HD6805W1--------------------------------------------------------------• Timer Control Register 2 (TCR2: $01B)
The Timer Control Register 2 (TCR2) consii>ts of an 5-bit
register of which all bits can be read and written.
Timer Control Register 2 (TCR2: $01B)
6543210
I/1ZlZI
Bit 6 OC F Output Compare Flag
This read-only bit is set when a match is found between the
OCR and the TDR2. It is cleared by reading the TSR2 and then
writing to the OCR.
Bit 7 ICF Input Capture Flag
This read-only bit is set to indicate a proper level transition
and cleared by reading the TSR2 and then reading the TCR2.
ICIM I OCIM I TOIM IIEDG I OLVL I
Bit 0 OLVL Output Level
This bit will appear at Port C6 when the value in the TDR2
equals the value in the OCR, if the DDR of Port C6 is set. It is
cleared by reset.
Bit 1 IEDG Input Edge
This bit determines which level transition of Port Cs (IC)
input will trigger a data store to ICR from the TDR2. When this
function is used, it is necessary to clear DDR of Port Cs . When
IEDG =0, the negative edge triggers ("High" to "Low" transition). When IEDG = 1, the positive edge triggers ("Low" to
"High" transition). It is cleared by reset.
Bit 2 TOIM Timer Overflow Interrupt Mask
When this bit is cleared, internal interrupt (TOI) is enabled
by TOF interrupt but when set, interrupt is inhibited.
User can write into port C6 by software.
Accordingly, after port C6 has output by hardware and is
immediately write into by software, simultaneous cyclic pulse
control with a short width is easy.
• Prescaler Control Register 2 (PCR2: $019)
The selection of clock input source and prescaler dividing
ratio are performed by the Prescaler Control Register 2 (PCR2).
Prescaler Control Register 2 (PCR2: $019)
6
5
IZIZIIS1
4
ISO
3
1ZI
o
2
MS2
MS1
MSO
Prescaler Dividing Ratio
Bit 3 OCIM Output Compare Interrupt Mask
When this bit is cleared, internal interrupt (OCI) by OCF
interrupt occurs. When set, interrupt is inhibited.
Bit 4 lelM Input Capture Interrupt Mask
When this bit is cleared, internal interrupt (lCI) by ICF
interrupt occurs. When set, interrupt is inhibited.
• Timer Status Register 2 (TSR2: $01A)
The Timer Status Register 2 (TSR2) is an 8-bit read-only
register which indicates that;
(I) A proper level transition has been detected on the input
pin with a subsequent transfer of the TDR2 value to the
ICR (ICF).
(2) A match has been found between the TDR2 and the OCR
(OCF).
(3) The TDR2 is zero (TOF).
Each of the event can generate 3 kinds of internal interrupt
request and is controlled by an individual inhibit bits in the
TCR2. If the I bit in the Condition Code Register is cleared,
priority vectors are generated in response to clearing each
interrupt ma~k bit. Each bit is described below.
Timer Status Register 2 (TSR2: SOlA)
765432
ICF
I OCF I TOF
0
1--_ _ _ _ _ _ _
The selection of clock input source is performed in three
different ways by bit 4 and bit 5 of the PCR2, as shown in
Table 3. At reset, internal clock CP2 controlled by the TIMER
input (bit 4 = I, bit 5 =0) is selected.
The prescaler dividing ratio is selected by three bits in the
PCR2 (bits 0, 1, 2), as shown in Table 4. The dividing ratio
can be selected in 8 ways (+1, +2, +4, +8, +16, +32, +64, +128).
At reset, +1 (bit 0 = bit 1 = bit 2 =0) is selected.
When writing into the PCR2, or when writing into the TDR2,
prescaier is initialized to $FF.
Table 3 Selection of Clock Input Source
PCR2
Bit 5
Bit4
0
0
0
1
0
1
1
1
Clock Input Source
Internal Clock CP2 *
CP2 Controlled by TIMER Input
Event Input from TIMER
• The TIMER input pin must be tied to Vee. for uncontrolled (/>,
clock input.
LZIZIZI/1Zl
Bit 5 TOF Timer Overflow Flag
This read-only bit is set when the TDR2 contains $00.
It is cleared by reading the TSR2 followed by reading of the
TDR2.
228
Clock Input Source
_HITACHI
---------------------------------------------------------------HD6805W1
•
Table 4 Selection of Prescaler Dividing Ratio
PCR2
SELF CHECK
The MCV self check easily determines whether the LSI
functions normally or not. When the MCV is connected as
shown in Fig. 8, the outputs of port C3 (LED) flicker in normal
operation.
Prescaler Dividing Ratio
Bit 2
Bit 1
BitO
0
0
0
+ 1
0
0
1
+2
•
0
1
0
+4
+8
The MCV can be reset three ways; by initial power-up, by
the external reset input (RES) and by an optional internal low
voltage detect circuit, see Figure 9. All the I/O ports are initialized to input mode (DDRs are cleared) during reset.
During power-up, a minimum 100 milliseconds is needed
before allowing the RES input to go "High". This time allows
the internal crystal oscillator to stabilize. Connecting a capacitor
to the RES input, as shown in Figure 10, typically provides
su fficien t delay.
0
1
1
1
0
0
+ 16
1
0
1
+32
1
1
0
+64
1
1
1
+ 128
RESETS
CAUTION
The flag of the TSR2 will be sometimes cleared when manipulating or testing the TSR2 by Read/Modify/Write instruction
shown in Table 5. Don't use these instructions for read/write/
test operation of the TSR2 flags.
7fT 2.2IJ
Table 5 Read/Modify/Write Instruction
Op Code
# Bytes
3C
2
6
DEC
3A
2
6
CLR
3F
2
6
COM
33
2
6
NEG
30
2
6
ROL
39
2
6
ROR
36
2
6
LSL
38
2
6
LSR
34
2
6
ASR
37
2
6
ASL
38
2
6
TST
3D
2
6
2
RES
F
As 38
XTAL
A, 36
A, 35
22pFr
+9V
8
33012
.A. A A
330Sr
.AA "-
HD6805W1
(Crystal option)
B. 31
B.,~
9 C"
~ ~ 10 C,
vvv
Vss = Pin 1
30
B. 29
f.::j
Vc c =Pi n 4
~
B,
132,,1 ~ ~12
0n
Ao
TIMER
NUM
~¥sr r.:; ~11
3;~?
A, 34
EXTAL
B7~
r
v cc
A4rE--
6
6
# Cycles
INC
INT
A. 39
....L
Mnemonic
A7 40
3
'--
\!:!I
B, 27
B, 26
C,
B" 25
C,
C. C s
c.
Vee Standby 21
Vee
13 14 15
1
3.3
330n.
Figure 8 Self Check Connections
2
RES
Pin
-------r
Part of
HD6805W1
MCU
Internal
Reset
------------------~
Figure 9 Power Up and Reset Timing
~HITACHI
Figure 10 Power Up Reset Delay Circuit
229
HD6805W11------------------------------------------------------------•
INTERNAL OSCILLATOR OPTIONS
The internal oscillator circuit is designed to require a minimum of external components. A crystal (AT cut, 4 MHz max),
a resistor, a jumper wire or an external signal may be used to
generate a system clock with various stability/cost tradeoffs.
A manufacturing mask option is required to select either the
crystal oscillator or the RC oscillator circuit. Four different
connection methods are shown in Figure 11. Crystal specifications are given in Figure 12. A resistor selection graph is
shown in Figure 13. EXTAL may be driven with a duty cycle
of 50% with XTAL connected to ground.
6 XTAL
6 XTAL
M HZ
4 max
c:J 5 EXTAL
HD6805W1
5 EXTAL
MCU
HD6805W1
MCU
22PF±20%=if.
Crystal
Approximately 25% Accuracy
External Jumper
Vee
6 XTAL
6 XTAL
~V,\I,\,.----I
R
HD6805W1
External
Clock
Input
MCU
No
Connection
Approximately 15% Accuracy
External Resistor
External Clock
CRYSTAL OPTIONS
RESISTOR OPTIONS
Figure 11
Internal Oscillator Options
,
5
C.
XTAL~~EXTAL
•
-
~~
5
\
X
~
>
(J
3
':)
AT Co =
f=4
Rs z
Cut Parallel Resonance Crystal
7 pF max.
MHz IC. =22pF±20%)
60n max.
u.
1\
2
'" f'
Figure 12 Crystal Parameters
o
5
10
15
20
25
Resistance
'"
30
I'.....
35
~
40
Iknl
Figure 13 Typical Resistor Selection Graph
230
~HITACHI
J.
Vee = 5.25V
Ta = 25°C
-
'\
ii
C7
~
I
1\
4
""
45
50
---------------------------------------------------------------HD6805Wl
•
Table 6 Interrupt Priorities
INTERRUPTS
The MCU can be interrupted in seven different ways: through
external interrupt input pin (INTI and 1NT2), internal timer
interrupt request (Timer 1, ICI, OCI and OFI) and a software
interrupt instruction (SWI). 002 and Timer 1 are generated by
the same vector address. When interrupt occurs, processing
of the program is suspended, the present CPU state is pushed
onto the stack in the order sho-.yn in Figure 4. The interrupt
mask bit (I) of the Condition Code Register is set and the external routine priority address is achieved from the special external vector address. After that, the external interrupt
routine is executed. The interrupt serVice routines normally
end with a return from interrupt (RTf) instruction which allows
the CPU to resume processing of the program prior to the interrupt. The priority interrupts are shown in Table 6 with the
vector address that contains the starting address of the appropriate interrupt routine. The interrupt sequence is shown as
a flowchart in Figure 14.
Interrupt
Priority
Vector Address
RES
1
$FFE,$FFF
SWI
2
INTI
TIMERI/INT2
ICI
3
$FFC,$FFD
$FFA,$FFB
4
$FF8,$FF9
5
$FF6. $FF7
$FF4.$FF5
6
7
OCI
OFI
$FF2,$FF3
Clear
y TIMER 1
y
ICi
y
OCI
1~1
7F~SP
O~DDR's
Fetch Instruction
CLR INT LogiC
7F~MR
FF
~TDRl
OO~TDR2
7 F ~ Prescaler 1
7 F ~ Prescaler 2
50~TCRl
y
lC~TCR2
OO~TSR2
10~PCR2
Stack PC, X, CC, A
Execute Instruction
Load PC From
SWI: $FFC, $FFD
INT.: $FFA, $FFB
TIMER. : $FF8, $FF9
INT2 : $FF8, $FF9
ICI: $FF6. $FF7
OCI: $FF4. $FF5
OFI: $FF2. $FF3
Figure 14 Interrupt Flowchart
~HITACHI
231
HD6805W11--------------------------------------------------------~-----
• Miscellaneous Register (MR: SOOA)
The vector address generated by the external interrupt
(1NT2) is the same as that of TIMERl as shown in Table 6.
The Miscellaneous Register (MR) controls the 1NT2 interrupt.
Bit 7 (IRF) of the MR is used as an INT2 interrupt request
flag. INT2 interrupt occurs at the 1NT2 negative edge, and IRF
is set. 1NT2 interrupt or not can be proved by checking IRF
by software in the interrupt routine of the vector address
($FF8, $FF9). IRF should be reset by software (BCLR' in·
struction).
Bit 6 (1M) of the MR is an 1NT2 interrupt mask bit. When
m is set, 1NT2 interrupt is disabled. 002 interrupt is also
disabled by bit (I) of the Condition Code Register (CC) like
other interrupts.
Miscellaneous Register (MR: SOOA)
6
IRF
1M
5
4
3
2
0
VlZVL2V1ZI
~-----
INTa Interrupt Mask
~--------INTa
Interrupt Request Flag
IRF is available for both read and write. However, IRF is
not writable by software. Therefore, IN'i2 interrupt cannot be
requested by software. At reset, IRF is cleared and 1M is set.
• INPUT IOUTPUT
There are 23 input/output pins. All pins (port A, B, and C)
are programmable as either inputs or outputs under software
control of the corresponding Data Direction Register (DDR).
The port I/O programming is accomplished by writing the
corresponding bit in the port DDR to a logic "l" for ou tpt or
a logic "0" for input. On reset, all the DDRs are initialized
to a logic "0" state to put the ports in the input mode. The port
output registers are not initialized on reset but may be written
to before setting the DDR bits to avoid undefined levels.
When programmed as outputs, the latched output data is
readable as input data, regardless of the logic levels at the
output pin due to output loading; see Figure IS. When port B
is programmed for outputs, it is capable of sinking 10 rnA and
sourcing 1 rnA on each pin.
All input/output lines are TIL compatible as both inputs
and outputs. Ports Band C are CMOS compatible as inputs.
Port A is CMOS compatible as outputs. Figure 16 provides some
examples of port connections.
Port C5 and C6 are also used for Timer 2.
When Port C5 is used as Timer 2 Input Capture (IC), Port
C5 's DDR should be cleared (Port C5 as input) and bit 4 (ICIM)
in the Timer Control Register 2 (TCR2) should be cleared too.
The Input Capture Register (ICR) stores the TDR2 when a
Port C5 input transition occurs as defined by bit 1 (IDEG) of
the TCR2.
When Port C6 is used as Timer 2 Output Compare (OC),
Port C6 's DDR should be set (Port C6 as output). When the
Output Compare Register (OCR) matches the TDR2, bit 0
(OLVL) in the TCR2 is set and OLVL will appear at Port C6.
Port C6 is writable by software. But the writing by software is
unavailable when a match between the TDR2 and the OCR is
found at the same time.
• INPUT
Port D is usable as either TTL compatible inputs or a 4·
channel input for an A/D converter. Figure 17 shows port D
logic configuration.
The Port D register at location $003 stores TTL compatible
inputs. When using as analog inputs for an A/D converter, refer
to A/D CONVERTER.
Data
Direction
Register
Bit
Output
Data Bit
Output
State
Input to
0
0
0
3·State
Pin
MCU
1
Figure 15 Typical Port I/O Circuitry
232
$
0
HITACHI
-----------------------------------------------------------------HD6805W1
A.
··
···
Port A
Port B
B,
A,
Port B Programmed as output(s), driving Darlington base directly.
Port A Programmed as output(s), driving CMOS and TTL load directly.
(b)
(a)
+v
+v
R
-
Port B
PortC
lOmA max
B,
··
CMOS Inverter
C.
Port C Programmed as output(s), driving CMOS loads, using external
pull-up resistors.
(d)
Port B Programmed as output(s), driving LEO(s) directly.
(c)
Figure 16 Typical Port Connections
CAUTION
The MCU has circuitry to protect the inputs against damage
due to high static voltages or electric field; however, the design
of the input circuitry for the AID converter, ANo '" AN3, V RH
and AVec, does not offer the same level of protection. Precautions should be taken to avoid applications of any voltage
higher than maximum-rated voltage or handled in any environment producing high-static voltages.
•
AID CONVERTER
The HD6805WI has an internal 8-bit AID converter. The
AID converter, shown in Figure 18, includes 4 analog inputs
(ANo to AN3), the Result Register (ADRR) and the Control
Status Register (AOCSR).
$003 Read
Internal Bus
DIA
. -......_ _ _ _ Port 0
D. to Os
4
~G>
Analog Input
o~
-0
~
(Xl
o
01
~
.....
Table 8 Register/Memory Instructions
Addressing Modes
Function
Mnemonic
Immediate
Op
Op
#
Op
#
#
#
Code Bytes Cycles Code Bytes Cycles Code
~
%
~
:E
()
Indexed
(8-Bit Offset)
Indexed
(No Offset)
Extended
Direct
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(16-Bit Offset)
Op
#
#
Bytes Cycles Code
#
#
Bytes Cycles
Load A from Memory
LOA
A6
2
2
B6
2
4
C6
3
5
F6
1
4
E6
2
5
06
3
Load X from Memory
LOX
AE
2
2
BE
2
4
CE
3
5
FE
1
4
EE
2
5
DE
3
6
Store A in Memory
STA
-
-
-
B7
2
5
C7
3
6
F7
1
5
E7
2
6
07
3
7
Store X in Memory
STX
-
-
-
BF
2
5
CF
3
6
FF
1
5
EF
2
6
OF
3
7
Add Memory to A
ADD
AB
2
2
BB
2
4
CB
3
5
FB
1
4
EB
2
5
DB
3
6
Add Memory and
Carry to A
AOC
A9
2
2
B9
2
4
C9
3
5
F9
1
4
E9
2
5
09
3
6
Subtract Memory
SUB
AO
2
2
BO
2
4
CO
3
5
FO
1
4
EO
2
5
DO
3
6
Subtract Memory from
A with Borrow
SBC
A2
2
2
B2
2
4
C2
3
5
F2
1
4
E2
2
5
02
3
6
AND Memory to A
AND
A4
2
2
B4
2
4
C4
3
5
F4
1
4
E4
2
5
04
3
6
2
4
CA
3
5
FA
1
4
EA
2
5
OA
3
6
3
5
F8
1
4
E8
2
5
08
3
6
3
5
Fl
1
4
E1
2
5
01
3
6
6
OR Memory with A
ORA
AA
2
2
BA
Exclusive OR Memory
with A
EOR
A8
2
2
B8
2
4
C8
Arithmetic Compare A
with Memory
CMP
Al
2
2
B1
2
4
C1
Arithmetic Compare X
with Memory
CPX
A3
2
2
B3
2
4
C3
3
5
F3
1
4
E3
2
5
03
3
6
Bit Test Memory with A
(Logical Compare)
BIT
A5
2
2
B5
2
4
C5
3
5
F5
1
4
E5
2
5
05
3
6
Jump Unconditional
JMP
2
3
CC
3
4
FC
1
3
EC
2
4
DC
3
5
-
-
BC
JSR
-
-
Jump to Subroutine
BO
2
7
CD
3
8
FD
1
7
ED
2
8
DO
3
9
Symbols:
Op: Operation Abbreviation
# : Instruction Statement
I
Table 9
Read/ModifylWrite Instructions
Addressing Modes
Function
Implied (A)
Mnemonic
Op
Code
Implied (X)
Op
#
#
Bytes Cycles Code
Indexed
(No Offset)
Direct
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(8·Bit Offset)
Op
#
#
Bytes Cycles Code
#
#
Bytes Cycles
Increment
INC
4C
1
4
5C
1
4
3C
2
6
7C
1
6
6C
2
7
Decrement
DEC
4A
1
4
5A
1
4
3A
2
6
7A
1
6
6A
2
7
Clear
ClR
4F
1
4
5F
1
4
3F
2
6
7F
1
6
6F
2
7
Complement
COM
43
1
4
53
1
4
33
2
6
73
1
6
63
2
7
~
Negate
(2's Complement)
NEG
40
1
4
50
1
4
30
2
6
70
1
6
60
2
7
;
Rotate left Thru Carry
ROl
49
1
4
59
1
4
39
2
6
79
1
6
69
2
7
Rotate Right Thr\J Carry
ROR
46
1
4
56
1
4
36
2
6
76
1
6
66
2
7
logical Sh ift left
lSl
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
l:
()
logical Shift Right
lSR
44
1
4
54
1
4
34
2
6
74
1
6
64
2
7
Arithmetic Shift Right
ASR
47
1
4
57
1
4
37
2
6
77
1
6
67
2
7
Arithmetic Shift left
ASl
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
Test for Negative or
Zero
TST
40
1
4
5.0
1
4
3D
2
6
7D
1
6
60
2
7
Symbols:
Op: Operation Abbreviation
# : Instruction Statement
I
a
0>
ex>
o
~
(,.)
01
~
HD6805W1--------------------------------------------------------------Table 10 Branch Instructions
Relative Addressing Mode
Mnemonic
Function
Op
Code
#
#
Bytes
Cycles
4
4
4
4
Branch Always
BRA
20
2
Branch Never
BRN-
21
2
Branch IF Higher
BHI
22
2
Branch I F lower or Same
BlS
23
2
Branch I F Carry Clear
BCC
24
2
4
(Branch IF Higher or Same)
(BHS)
24
2
4
Branch I F Carry Set
BCS
25
2
4
(Branch I Flower)
(BlO)
25
2
4
Branch I F Not Equal
BNE
26
4
Branch I F Equal
BEQ
27
2
2
Branch IF Half Carry Clear
BHCC
28
2
4
Branch IF Half Carry Set
BHCS
29
2
4
4
4
Branch I F Plus
BPL
2A
2
Branch IF Minus
BMI
2B
2
4
Branch IF Interrupt Mask Bit is Clear
BMC
2C
2
4
Branch I F Interrupt Mask Bit is Set
BMS
20
2
4
Branch IF Interrupt Line is low
Bil
2E
2
4
Branch IF Interrupt Line is High
BIH
2F
2
4
Branch to Subroutine
BSR
AD
2
8
Symbols: Op: Operation Abbreviation #: Instruction Statement
Table 11
Bit Manipulation Instructions
Addressing Modes
Bit Test and Branch
Bit Set/Clear
Mnemonic
Function
Op
Code
Branch IF Bit n is set
BRSET n (n=O ..... 7)
Branch I F Bit n is clear
BRClR n (n=O ..... 7)
#
#
Bytes
Cycles
Op
Code
-
-
01+2-n
-
Set Bit n
BSET n (n=O ..... 7)
10+2-n
2
7
Clear bit n
BClR n (n=O ..... 7)
11+2-n
2
7
2-n
-
#
#
Bytes
Cycles
10
3
,3
10
-
-
-
-
Symbols: Op: Operation Abbreviation #: Instruction Statement
Table 12 Control Instructions
Implied
Function
Op
Code
#
#
Bytes
Cycles
Transfer A to X
TAX
97
1
2
Transfer X to A
TXA
9F
1
2
Set Carry Bit
SEC
99
1
2
Clear Carry Bit
ClC
98
1
2
2
Set Interrupt Mask Bit
SEI
9B
1
Clear Interrupt Mask Bit
CLI
9A
1
2
Software Interrupt
SWI
83
1
11
Return from Subroutine
RTS
81
1
6
Return from Interrupt
RTI
80
1
9
Reset Stack Pointer
RSP
9C
1
2
No-Operation
NOP
90
1
2
- Symbols: Op: Operation AbbreViation
244
Mnemonic
#: Instruction Statement
~HITACHI
---------------------------------------------------------------HD6805Wl
Table 13 Instruction Set
Addressing Modes
Mnemonic
Implied
Immediate
ADC
x
ADD
x
x
AND
ASL
ASR
x
x
Direct
x
x
x
x
x
Extended
Relative
x
x
x
x
x
x
x
x
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
x
x
Bit
~t/
Clear
x
x
x
x
BCLR
x
x
x
x
x
x
x
x
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
BIL
x
BIT
x
x
x
x
x
x
x
x
x
x
x
x
x
x
BLO
BLS
BMC
BMI
BMS
BNE
BPL
BRA
BRN
x
x
BRCLR
BRSET
x
BSET
BSR
CLI
CLR
x
x
x
x
COM
x
x
CPX
DEC
x
x
EOR
INC
x
x
CMP
x
JMP
JSR
LOA
LOX
x
x
Condition Code Symbols:
Ii
Half Carry (From Bit 3)
I
Interrupt Mask
N . Negative (Sign Bit)
Z
Zero
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
C
1\
•
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
~HITACHI
H
I
N
Z
C
1\
•
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
•
• •
• •
• •
• •
• •
-. •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• 0
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
1\
x
BCC
CLC
Bit
Test &
Branch
1\
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
1\ 1\
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
•
1\
1\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1\
1\
•
•
• • 0
• • •
0
1
1\
•
1\
1\
1\
1\
1\
1\
1
1\
1\
1\
1\
1\
•
•
1\
•
• •" •
• • •
1\
"1\ ••
"
(to be continued)
245
HD6805W1--------------------------------------------------------------Table 13 Instruction Set
Addressing Modes
Mnemonic
Implied
Immediate
LSL
x
x
LSR
x
NEQ
x
x
x
NOP
x
x
ORA
x
ROR
x
x
RSP
x
RTI
x
RTS
x
x
SBC
Relative
x
H
x
x
x
x
x
x
x
x
x
Bit
Test &
Branch
x
x
x
x
Bit
Set/
Clear
x
x
x
x
x
x
ROL
Extended
Direct
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
SEC
SEI
x
x
x
STA
STX
x
SUB
x
x
x
x
SWI
TAX
TST
TXA
x
x
x
x
x
x
x
x
x
x
x
x
I
Z
N
C
•
•
•
•
•
•
•
•
• /\ /\ /\
• 0 /\ /\
• /\ /\ /\
• • • •
• /\ /\ •
• /\ /\ /\
• /\ /\ /\
• • • •
?
?
•
•
•
•
•
•
• • •
• /\ /\
• • •
1 • •
• /\ /\
• /\ /\
•
/\
/\
?
• •
?
/\
?
/\
1
•
•
•
• • •
•
• • • • •
• • /\ /\ •
• • • • •
1
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
I nterrupt Mask
N
Negative (Sign Bit)
Z
Zero
C
/\
•
?
x
Carry/Borrow
Test and Set if True. Cleared Otherwise
Not Affected
Load CC Register From Stack
Table 14 Opcode Map
Bit Manipu lation
Test &
Setl
Branch
Clear
0
0 BRSETO
1 BRClRO
2 BRSET1
3 BRClRl
4 BRSET2
5 BRClR2
6 BRSET3
7 BRClR3
B BRSET4
9 BRClR4
A BRSET5
B BRClR5
C BRSET6
o BRClR6
E BRSET7
F BRClR7
3/10
1
BSETO
BClRO
BSET1
BClRl
BSET2
BClR2
BSET3
BClR3
BSET4
BClR4
BSET5
BClR5
BSET6
BClR6
BSET7
BClR7
217
Rei
2
BRA
BRN
BHI
BlS
BCC
BCS
BNE
BEQ
BHCC
BHCS
BPl
BMI
BMC
BMS
Bil
BIH
2/4
Control
Read/Modify/Write
Brnch
OIR
3
\
j
A
4
\
I
x
5
NEO
\
I
.Xl
6
\ .XO
IMP
IMP
I
B
RTI'
9
7
-
RTS'
-
-
COM
lSR
SWI'
-
ROR
ASR
lSl/ASl
ROl
DEC
-
I
\ )(1
\.XO
I
I
I
C
-
-
-
-
-
-
TXA
-
1/'
1/2
2/2
I 217 I 1/6
B
\ EXT \ )(2
-
-
1/4
I
-
INC
TST
-
ClR
, 1/4
A
TAX
ClC
SEC
CLI
SEI
RSP
NOP
-
2/6
Register IMemory
IMM \ OIR
-
I
E
0
SUB
CMP
SBC
CPX
AND
BIT
lOA
STA(+l)
I
I
2/4
I 3/5
13/6
1 2/5
[NOTE) 1. Undefined opcodes are marked with "-".
2. The number at the bottom of each column denote the number of bytes and the number of cycles required (Bytes/Cycles).
Mnemonics followed by a "." require a different number of cycles as follows:
9
RTI
RTS
6
SWill
BSR
8
3. (
) indicate that the number in parenthesis must be added to the cycle count for that instruction.
246
$
HITACHI
F
~H
IGH
0
1
2
3 l
4 o
5 W
6
7
8
9
EOR
AOC
ORA
ADD
JMP(-l)
JSR(-3)
lOX
STX(+lI
BSR"
I
I
A
B
C
0
E
F
11/4
HD6301 V1 ,HD63A01 V1 , - - HD63B01V1
CMOS MCU (Microcomputer Unit)
The HD6301Vl is an 8-bit CMOS single-chip microcomputer unit. Object Code compatible with the 806801. 4kB
ROM. 128 bytes RAM. Serial Communication Interface (SCn,
parallel I/O ports and multi function timer are incorporated
in the HD6301Vl. It is bus compatible with HMCS6800. Execution time of key instructions are improved and several
new instructions are added to increase system throughput.
The HD6301Vl can be expanded up to 65k words. Like the
HMCS6800 family. I/O level is TTL compatible with +5.0V
single power supply. As 8D6301Vl is fabricated by the advanced CMOS process technology, power dissipation is extremely reduced. In addition to that. H0630 1V 1 has Sleep Mode and
Standby Mode at lower power dissipation mode. Therefore
flexible low power consumption application is possible.
FEATURES
Object Code Upward Compatible with HD6801 Family
Abundant On-Chip Functions Compatible with HD6801VO;
4kB ROM, 128 Bytes RAM,29 Parallel I/O Lines, 2 Lines of
Data Strobe, l6-bit Timer, Serial Communication Interface
• Low Power Consumption Mode: Sleep Mode, Standby Mode
• Minimum Instruction Execution Time
1~s (f=lMHz), 0.67~s (f=1.5MHz), O.5~s (f=2MHz)
• Bit Manipulation, Bit Test Instruction
• Protection from System Upset: Address Trap, On-Code Trap
• Up to 65k Words Address Space
• Wide Operation Range
Vcc=3 to 6V (f=O.1-'
••,,
94
· ,, ,, ~,,
· ,, ,, ,,
:} CCI IITii I r9
• tt'
·· , ,
:}o..j I IIIIIIJ~ • ,, ,,
04
1 1
0--1
ASL
68
ASLA
67
ASR
64
LSR
6
6
6
2 78
2 77
2 74
6 3
6
6
3
3
LSRD
Store
Accumulator
STAA
STAB
2 A7 4 2 B7 4 3
07 3 2 E7 4 2 F7 4 3
Store Double
Accumulator
STD
DO 4
97
3 3 93
AO 4
2 BO
4 2 FO
Subtreet
With Carrv
SBCA
82
SBCB
C2
Transfer
Accumulators
TAB
16
TBA
17
Test Zero or
Minus
TST
2 2 92 3 2
02 3 2
A:B-M:M+1-A:B
1 1 A-8-A
B2
4
3
A-M-C-A
2 F2
4
3
B-M-C-B
A2
4 2
E2
4
60
4 2
70 4
1 1 A-B
1 1 B_A
M-OO
3
TSTA
40
1
1 A -00
TSTB
50
1
1 B - 00
And Immediate
AIM
OR Immediate
OIM
EOR Immediate
ElM
Test Immediate
TIM
3
72 6 3
75 6 3
7B 4 3
71
6
61
7
62
7
3
3
M·IMM-M
M+IMM-M
M®IMM-M
3
6B 5 3
65
ao
B -M-B
5 3
10
2 2
-
3
SBA
2 B3
bO
ACC AI .~~. 1Of..P
4
Subtreet
Accumulators
5
117
A-M _A
83
4 2 A3
b7
-
3
SUBD
2 DO 3 2 EO
1-0
17.
4
SUBB
2
117
•
110
A_M
B _ M+1
2 ED 5 2 FD 5 3
2
b7
~!3:i ,,~.
B_M
Double Subtreet
SUBA
2 2 90
3
A
•
A_ M
3
80
CO
Subtreet
Booleanl
Arithmetic Operation
7
M·IMM
··
··
··
···
······ ,, ,,, ·
·• ·· ,, ,, , ··,
•
····• ,,, ,,, ,,, ,,,
•·
·· ·· ,,, ,,, ,, ,,
·· ·· ,, ,, ··
···· ,, ,,
·• ·• •
~,
R
R
6
R
R
~,
R
R
R
R
R
R R
R R
R R
••
••
••
1 1 R
1 1 R
•
•
1 1 R •
1 1 R
Notel Condition Code Register will be explained in Note of Table 11.
• New Instructions
In addition to the H06801 Instruction Set, the HD6301Vl
has the following new instructions:
AIM----(M)· (IMM)-+(M)
Evaluates the AND of the immediate data and the
memory, places the result in the memory .
OIM - -- - (M) + (IMM) -+ (M)
Evaluates the OR of the immediate data and the
memory, places the result in the memory.
EIM----(M)(!) (IMM) -+ (M)
Evaluates the EOR of the immediate data and the
contents of memory, places the result in memory.
TIM----(M)· (IMM)
Evaluates the AND of the immediate data and the
memory, changes the flag of associated condition code
register
Each instruction has three bytes; the rust is op-code, the
second is immediate data, the third is address modifier.
XGDX--(ACCD)" (IX)
Exchanges the contents of accumulator and the index
register.
SLP----The CPU is brought to the sleep mode. For sleep
mode, see the "sleep mode" section.
~HITACHI
269
HD6301V1,HD63A01V1,HD63B01V1--------------------------------------------Table 9
Index Register, Stack Manipulation Instructions
Condition Code
Register
AddressIng Modes
POInter OperatIons
MnemoniC
-
#
OP
Decrement Index Reg
CPX
8C 3 3 9C
---c-- - -
4
2
AC 5
DEX
-
#
EXTEND
#
OP
-
IMPLIED
OP
2
BC
5 3
INDEX
OP
OP
Compare Index Reg
DIRECT
IMMED.
-
-
---
#
Decrement Stack Pntr
DES
Increment Index Reg
INX
Increment Stack Pntr
""INs'
-.-
X-MM+l
'091
---,
34
.
08
"- "'3 - - .. - i-'
31
-
#
-~
--~
---------
-
Booleanl
Arithmetic Operation
1
X -1- X
1
:2 EE
2
FE
5 3
M - XH.IM + 11- XL
AE
2
BE
M- sPH.IM+lI-SP L
2
FF
5 3
5 3
2
BF
53
lOX
CE
load Stack Pntr
lOS
8E
Store Inde.. Reg
STX
Store Stack Pntr
STS
Index Reg - Stack Pntr
TXS
35
1
1
X-l-SP
Stack Pntr - Index Reg
TSX
30
1
1
SP + 1 - X
Add
ABX
3A
1
1 B + X- X
Push Data
PSHX
3C
5 1 XL - Mil>' SP - 1 - SP
Pull Data
PUlX
38
4
1
Exchange
XGDX
18
2
1
5
5
OF 4
EF
---- f - I -2- - - 5
9F 4 2 AF 5
3
DE
4
3
9E
4
2
I N Z
V
C
:
:
l
··· ··· ·· · ·· ··
·· ·· ·· · ·· ··
··· ·· ···
·· ·· · · · ··
·· ·· ·· ·· ·· ··
······
·· ····
l
l
sP+l-SP
load Index Reg
3
1 0
H
l
--11 '11 SP-l-SP
X +1- X
1
5 4 3 2
X H - M. XL -1M + 11
SP H - M,SP L -IM+ 11
XH - Mil>' SP - 1 - SP
SP + 1 - SP. Mil> - X H
SP + 1 - SP. Mil> - XL
l
R
(j) l
R
J; l
R
(t
R
• III
l
••••••
ACCD .. IX
Note) Condition Code Register will be explained in Note of Table 11.
Table 10 Jump, Branch Instruction
CondItion Code
Register
Addressing Modes
Operations
Mnemonic
RELATIVE
OP
Branch Always
Branch Never
BRA
20
-BRN --f-:21
Branch If Carry Clear
-
#
DIRECT
OP
-
#
INDEX
OP
-
EXTEND
#
OP
-
#
Branch Test
IMPLIED
OP
-
#
3
2
None
3
2
None
BCC--- 24
3
2
Branch If Carry Set
BCS
25
3
2
c=o
C =,
Branch If - Zero
BEQ
27
3
2
Branch If .. Zero
BGE
2C
3
2
> Zero
Brench If
Z - 1
N (!) V- 0
2E
3
2
Z + (N
BHI
22
3
2
C+Z-O
< Zero
BlE
2F
3
2
Z + (N (!) VI - ,
BlS
23
3
2
C+Z-'
BlT
20
3
2
BMI
2B
3
2
N -,
Branch If Not Equal
Zero
BNE
26
3
2
z=o
Branch If Overflow
Clear
BVC
28
3
2
Branch If Overflow Set
BVS
29
3
2
Branch If Plus
BPl
2A
3
2
Branch To Subroutine
BSR
80
5
2
Jump
JMP
Jump To Subroutine
JSR
Branch If
Branch If lower Or
Same
Branch If
< Zero
Branch If Minus
i--
-
VI - 0
- - - - c-'
N (!) V -,
--
v-o
V -I
--
N-O
6E
90
5
2
3
2
7E
3
3
AD 5
2
80 6
3
No Operation
NOP
01
Return From Interrupti
RTI
3B 10 1
Return From
Subroutine
RTS
J9
Softwere Interrupt
SWI
3F 12 1
Wait for Interrupt"
WAI
SlP
3E
Sleep
1 1
5
Advances Prog. Cntr.
Only
1
9
1
tA 4
t
Note) 'WAI ~~ts R/W hIgh; Address Bus goes to FFFF; Data Bus goes to the three state.
CondItIon Code Register will be explained in Note of Table 11.
270
®
BGT
Branch If Higher
~HITACHI
5
4
3
2
,
0
H
I N
Z
V
C
··· ··· ··· ··· ··· ···
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·· · ·· · · ··
·· ··· ·· ··· ··· ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
· · · ·--· ·
·· · ·· ·· ·· ··
·• • • ·• ·• ·•
--@
S
(j).
~~~~~~~~~~~~~~~~~~~~~~-HD6301V1,HD63A01V1,HD63B01V1
Table 11
Condition Code Register Manipulation Instructions
]AddressingMOde!
Operetions
Mnemonic
CINt Carry
Clelr Intlrrupt Mask
CMrOverflow
SetCllrry
Set Intlrrupt Mask
Set Owrflow
Accumul.tor A - CCR
CeR - Accumulator A
CLC
CLI
CLV
SEC
SEI
SEV
TAP
TPA
-, "1
, ,
OC
OE
OA
00
OF
OB
06
07
1
1
1
1
,
,
Condition Code Register
4
1
3
2
0
I
N Z
V C
R
R
R
Boolean Operation
IMPLIED
OP
1
,
,
O-C
0-1
O-V
l-C
, -I
1
1
1
1 -V
A_ CCR
CCR-A
5
H
·· • ·· ·· ·· ·
·· ·· ·· ·· · ·
·· · ·· ·· · ··
······
S
S
S
---
III
---
[NOTE 11 Condition Code
(D
(Bit V)
~
(Bit C)
@
(Bit C)
@
(Bit V)
@
(Bit V)
@
(Bit V)
iJ)
(Bit N)
@
(All Bit)
@
(Bit II
[NOTE
21
Register Notes: (Bit set if test is true and cleared otherwise)
Test: Result = 100000007
Test: Result \ OOOOOOOO?
Test: BCD Character of high~rder byte greater than 97 (Not cleared if previously set)
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
Test: Set equal to NeC=1 after the execution of instructions
Test: Result less than zero? (Bit 15=1)
Load Condition Code Register from Stack.
Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exit the wait
state.
@l
(All Bit) Set according to the contents of Accumulator A.
@
(Bit C)
Result of Multiplication Bit 7= 1 of ACCB?
CLI instructions and interrupt.
_ _ __
If interrupt mask-bit is set (1="1") and interrupt is requested (lRQI = "0" or IRQ2 = "0")"
and then CLI instruction is executed, the CPU responds as follows.
1 the next instruction of CLI is one-machine cycle instruction.
Subsequent two instructions are executed before the interrupt is responded.
That is, the next and the next of the next instruction are executed.
2 the next instruction of CLI is two-machine cycle (or more) instruction.
Only the next instruction is executed and then the CPU jump to the interrupt routine.
Even if TAP instruction is used, instead of CLI, the same thing occurs.
Table 12 OP-Code Map
OP
CODE
~
LO
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
lOll
1100
1101
1110
1111
0000
0
O~
I NOP
2 ~
3
~
4
lSRO
ASlO
TAP
TPA
INX
OEX
ClV
SEV
ClC
SEC
CLI
SEI
5
6
7
8
9
A
B
C
0
E
F
0
0001
I
SBA
CBA
0010
2
BRA
BRN
~ BHI
~ BlS
~ BCC
BCS
TAB
BNE
BEQ
TBA
XGOX BVC
OAA
BVS
SlP
BPl
ABA
BMI
./" BGE
~ BlT
~ BGT
~ BlE
-----
I
'1
0011
3
ACC
A
ACC
B
0100
0101
5
-----4
INO
0110
6
NEG
I~
OIR
0111
7
ACCA or SP
IMM
I
OIR liND
I
EXT
IMM
1
-r
1010
I
1011
A
i
B
1100
C
I
!
10001 1001
8
I 9
TSX
AIM
INS
I
PULA
DIM
PUlB
COM
LSR
DES
_ _ I_EI~
TXS
f-----.
PSHA
ROR
PSHB
ASR
PUlX
ASl
RTS
ROL
ABX
DEC
RTI
TIM
PSHX
INC
MUl
TST
BSR
WAI ~~
JMP
SWI
ClR
~l
I
3
4
5
7
8
I
Exi-
0
I
sac
2
3
AD 00
SUBO
AND
BIT
lOA
CPX
JSR
lOS
STS
9
I
A
4
5
EOR
AOC
, 6
7
I8
9
ORA
ADD
s-
~
STA
I
6
I
I
1101
II 10_tl III
0 'E
-F--
SUB
CMP
...-/1
----
ACCB or X
OIR liND
STA
A
LOO
STO
lOX
STX
...-/1
1
B
...........-I
C I
o
I
E
C
0
E
F
i
F
UNDEFINED OP CODE ~
* Only for instructions of AIM, OIM, ElM, TIM
~HITACHI
271
HD6301V1,HD63A01Vl,HD63B01Vl--------------------------------------------• Instruction Execution Cycles
In the HMCS6800 series, the execution cycle of each instruction is the number of cycles between the start of the
current instruction fetch and just before the start of the subsequen t instruction fetch.
The HD6301Vl uses a mechanism of the pipeline control for the instruction- fetch and the subsequent instruction
fetch is performed during the current instruction being exe-
cuted.
Therefore, the method to count instruction cycles used in
the HMCS6800 series cannot be applied to the instruction cycles such as MULT, PULL, DAA and XGDX in the HD6301Vl.
Table 13 provides the information about the reillionship
among each data on the Address Bus, Data Bus, and R/W status
in cycle-by-cycle basis during the execution of each instruction.
Table 13 Cycle-by-Cycle Operation
Address Mode &
Instructions
IMMEDIATE
ADC
ADD
BIT
AND
EOR
CMP
LOA
ORA
SBC
SUB
ADDD CPX
LDD
LOS
LOX
SUBD
DIRECT
ADC
AND
CMP
LOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
Address Bus
I
CPX
LOS
SUBD
STD
STX
STS
1
2
Op Code Address+ 1
Op Code Address+2
1
1
Operand Data
Next Op Code
1
2
3
Op Code Address+ 1
Op Code Address+2
Op Code Address+3
1
1
1
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
1
2
3
Op Code Address+ 1
Address of Operand
Op Code Address+2
1
1
1
Address of Operand (LSB)
Operand Data
Next Op Code
1
Destination Address
Accumulator Data
Next Op Code
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB) ,
First Subroutine Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Next Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
2
I
3
3
3
ADDD
LDD
LOX
4
4
1
2
3
1
72
3
4
1
2
3
4
JSR
5
1
2
3
4
5
TIM
4
1
2
3
4
AIM
OIM
Data Bus
ElM
6
1
2
3
4
5
6
Op Code Address + 1
Destination Address
Op Code Address+2
Op Code Address+ 1
Address of Operand
Address of Operand + 1
Op Code Address+2
Op Code Address+ 1
Destination Address
Destination Address+ 1
Op Code Address + 2
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer-1
Jump Address
Op Code Address + 1
Op Code Address+2
Address of Operand
Op Code Address + 3
Op Code Address+ 1
Op Code Address + 2
Address of Operand
·FFFF
Address of Operand
Op Code Address+3
0
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
- Continued -
272
~HITACHI
~~~~~~~~~~~~~~~~~~~~~~HD6301V1,HD63A01V1,HD63B01V1
Table 13 Cvcle~v-Cvcle Operation (Continued)
Address Mode &
Instructions
Data Bus
Address Bus
INDEXED
JMP
3
1
2
3
ADC
AND
CMP
LOA
SBC
TST
STA
ADD
BIT
EOR
ORA
SUB
1
2
4
4
ADDD
CPX
LOS
SUBD
STD
STX
LDD
LOX
3
4
1
2
3
4
1
2
5
STS
5
3
4
5
1
2
3
4
5
JSR
1
2
5
3
4
5
ASL
COM
INC
NEG
ROR
ASR
DEC
LSR
ROL
6
TIM
1
2
3
4
5
6
1
2
5
3
4
5
CLR
1
2
5
3
4
5
AIM
OIM
ElM
1
2
3
7
4
5
6
7
Op Code Address+ 1
FFFF
Jump Address
Op Code Address + 1
FFFF
IX + Offset
Op Code Address + 2
1
1
1
1
1
1
1
Op Code Address + 1
FFFF
IX + Offset
Op Code Address + 2
Op Code Address + 1
FFFF
IX + Offset
IX+Offset+ 1
Op Code Address + 2
Op Code Address + 1
FFFF
IX + Offset
IX+Offset+ 1
Op Code Address+2
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
IX + Offset
Op Code Address + 1
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address + 1
Op Code Address + 1
Op Code Address + 2
FFFF
IX + Offset
Op Code Address + 3
Op Code Address + 1
FFFF
IX + Offset
IX + Offset
Op Code Address + 2
Op Code Address + 1
Op Code Address + 2
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address + 3
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
Offset
Restart Address (LSB)
First Op Code of Jump Routine
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Accumulator Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Offset
. Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data
0
00
1
1
1
1
1
1
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
0
1
- Continued -
~HITACHI
273
HD6301V1,HD63A01V1,HD63B01V1--------------------------------------------Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
EXTEND
JMP
3
ADC
AND
CMP
LOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
TST
4
1
2
3
1
2
3
4
i
4
1
2
3
4
ADDD
CPX
LOS
SUBD
-STD
STX
LDD
LOX
I
5
1
2
3
4
5
STS
5
1
2
3
4
5
JSR
6
ASL
COM
INC
NEG
ROR
ASR
DEC
LSR
ROL
6
CLR
5
1
2
3
4
5
6
1
2
3
4
5
6
1
2
3
4
5
Data Bus
Op Code Address + 1
Op Code Address + 2
Jump Address
Op Code Address + 1
Op Code Address+2
Address of Operand
Op Code Address + 3
1
1
1
1
1
1
1
Jump Address (MSB)
Jump Address (LSB)
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Next Op Code
Op Code Address+ 1
Op Code Address+2
Destination Address
Op Code Address+3
Op Code Address+ 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
Destination Address
Destination Address + 1
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
FFFF
Stack Pointer
Stack Pointer - 1
Jump Address
Op Code Address + 1
Op Code Address+2
Address of Operand
FFFF
Address of Operand
Op Code Address + 3
O.p Code Address+ 1
Op Code Address+2
Address of Operand
Address of Operand
Op Code Address + 3
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
0
1
Destination Address (MSB)
Destination Address (LSB)
Accumulator Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (MSB)
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (MSB)
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
00
Next Op Code
I
- Continued -
274
~HITACHI
-----------------------HD6301V1,HD63A01V1,HD63B01V1
Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions
IMPLIED
ABA
ASL
ASR
CLC
CLR
COM
DES
INC
INX
LSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
DAA
PULA
ABX
ASLD
CBA
CLI
CLV
DEC
DEX
INS
LSR
ROL
NOP
SEC
SEV
TAP
TPA
TSX
XGDX
Address Bus
1
1
Next Op Code
1
I
2
PULB
1
2
1
2
3
PSHA
Op Code Address + 1
I
3
..
Data Bus
PSHB
4
PULX
4
PSHX
1
2
3
4
1
2
3
4
1
2
5
RTS
3
4
5
1
2
5
3
4
5
1
2
MUL
7
3
4
5
6
7
Op Code Address + 1
1
1
1
1
1
1
1
FFFF
Op Code Address + 1
FFFF
Stack Pointer + 1
Op Code Address + 1
FFFF
Stack Pointer
Op Code Address + 1
Op Code Address + 1
0
1
1
1
1
1
1
1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Op Code Address + 1
FFFF
0
0
Stack Pointer
Stack Pointer - 1
Op Code Address + 1
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Return Address
Op Code Address + 1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
~HITACHI
I
1
1
1
1
1
1
1
1
1
1
1
1
1
Next Op Code
Restart Address (lSB)
Next Op Code
Restart Address (lSB)
Data from Stack
---Next Op Code
Restart Address (lSB)
Accumulator Data
Next Op Code
.. Next Op Code
Restart Address (lSB)
Data from Stack (MSB)
Data from Stack (LSB)
Next Op Code
Restart Address (lSB)
Index Register (LSB)
Index Register (MSB)
Next Op Code
Next Op Code
Restart Address (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Restart Address (LSS)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSS)
Restart Address (LSB)
- Continued -
275
HD6301V1,HD63A01V1,HD63B01V1--------------------------------------------Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
IMPLIED
WAI
9
1
2
3
4
5
6
7
8
9
RTI
1
2
3
10
4
5
6
7
8
9
10
1
2
SWI
3
12
4
5
6
7
8
9
10
11
12
1
2
SLP
4
r
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer-1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer-4
Stack Pointer - 5
Stack Pointer - 6
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer + 1
Stack Pointer+2
Stack Pointer + 3
Stack Pointer+4
Stack Pointer + 5
Stack Pointer + 6
Return Address
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Vector Address FFFA
Vector Address FFFB
Address of SWI Routine
Op Code Address+ 1
FFFF
FFFF
Sleep
1
3
4
FFFF
Op Code Address + 1
Data Bus
I
!
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator. A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address (LSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index Register (LS8)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)
Address of SWI Routine (LSB)
First Op Code of SWI Routine
Next Op Code
Restart Address (LSB)
High Impedance-Non MPX Mode
Address Bus -MPX Mode
1
Restart Address (LSB)
Next Op Code
- Continued -
276
$
HITACHI
---------------------------------------------HD6301V1,HD63A01V1,HD63B01V1
Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
Data Bus
RELATIVE
BCC
BEQ
BGT
BLE
BLT
BNE
BRA
BVC
BSR
BCS
BGE
BHI
BLS
BMT
BPL
BRN
BVS
3
1
2
3
5
1
2
3
4
5
Op Code Address+ 1
FFFF
i Branch Address······Test= "'"
Op Code Address+ '···Test="O··
!
I
I
1
FFFF
• LOW POWER CONSUMPTION MODE
The HD630 I VI has two low power consumption modes; sleep
and standby mode.
Branch Offset
Restart Address (LSB)
First Op Code of Branch Routine
Next Op Code
1
,
00 Code Add.ess+ 1
Stack Pointer
Stack Pointer - ,
Branch Address
1
1
I
1
0
0
1
- - - -------_ .. -
I
Offset
Restart Address (lSB)
Return Address (LSB)
Return Address (MSB)
First Op Code of Subroutine
CPU.
This sleep mode is available to reduce an average power
consumption in the applications of the HD630lVI which may
not be always running .
• Sleep Mode
On execution of SLP instruction, the MCU is brought to the
sleep mode. In the sleep mode, the CPU sleeps (the CPU clock
becomes inactive), but the contents of the registers in the CPU
are retained. In this mode, the peripherals of CPU will remain
active. So the operations such as transmit and receive of the
SCI data and counter may keep in operation. In this mode,
the power consumption is reduced to about 1/6 the value of
a normal operation.
The escape from this mode can be done by interrupt, RES,
STBY. The RES resets the MCU and the STBY brings it into the
standby mode (This will be mentioned later). When interrupt is
requested to the CPU and accepted, the sleep mode is released,
then the CPU is brought in the operation mode and jumps to
the interrupt routine. When the CPU has masked the intenupt,
after recovering from the sleep mode, the next instruction of
SLP starts to execute. However, in such a case that the timer
interrupt is inhibited on the timer side, the sleep mode cannot
be released due to the absence of the interrupt request to the
•
Standby Mode
Bringing 'STBY "Low", the CPU becomes reset and all
clocks of the HD630IVI become inactive. It goes into the
standby mode. This mode remarkably reduces the power con·
sumptions of the HD6301 VI.
In the standby mode, if the HD630 I VI is continuously
supplied with power, the contents of RAM is retained. The
standby mode should escape by the reset start. The following
is the typical application of this mode.
First, NMI routine stacks the MCU's internal information and
the contents of SP in RAM, disables RAME bit of RAM control
register, sets the Standby bit, and then goes into the standby
mode. If the Standby bit keeps set on reset start, it means
that the power has been kept during standby mode and the
contents of RAM is normally guaranteed. The system recovery
may be possible by returning SP and bringing into the condition
before the standby mode has started. The timing relation for
each line in this application is shown in Figure 24.
Vee
~------~Irl----~r-
HD6301V1
I
! - -- - - - - i f
I
I
I
r--:
~:
I
~
"Stack registers
,. RAM conlrol
regIster set
Figure 24 Standby Mode Timing
~HITACHI
277
HD6301V1,HD63A01V1,HD63B01V1~~~~~~~~~~~~~~~~~~~~~~
• ERROR PROCESSING
Table 14 Address Error
When the HD6301Vl fetches an undefined instruction or
fetches an instruction from unusable memory area, it generates
the highest priority internal interrupt, that may protect from
system upset due 10 noise or a program error.
•
Mode
I
Op-Code Error
I
I
I
I
I
I
SEFFF
SEFFF
System Flow chart of HD6301 VI is shown in Fig. 25.
Addr. . Error
When an instruction is fetched from other than a resident
ROM, RAM, or an external memory area, the CPU starts the
same interrupt as op-code error. In the case which the instruction is fetched from external memory area and that area is not
usable, the address error cannot be detected.
The addresses which cause address error in particular mode
are shown in Table 14.
This feature is applicable only to the instruction fetch, not to
normal read/write of data accessing.
278
I
Address SOOIF SOOIF SOOIF SOO7F SOOIF 'OO7F
SOIOO
S0200
Fetching an undefined op-code, the HD6301Vl will stack the
CPU register as in the case of a normal interrupt and vector to
the TRAP (SFFEE, SFFEF), that has a second highest priority
(RES is the highest).
.
•
2,4
1
7
0
5
6
SOOOO SOOOO SOOOO SOOOO SOOOO SOOOO
Transitions among the active mode, sleep mode, standby
mode and reset are shown in Fig. 26.
Figures 27, 28, 29 and 30 shows a system configuration.
~HITACHI
-----------------------------------------------HD6301V1,HD63A01V1,HD63B01V1
~
PCl
PCH
-<
IXL
<
MSP
Msp·l
MSP·2
IXH· MSP·3
ACCA ·MSP·4
ACCB • MSP·5
CCR • MSP·6
Figure 25
HD6301Vl System Flow Chart
~HITACHI
279
HD6301V1,HD63A01V1,HD63B01V1---------------------------------------------
Figure 26 Transitions among Active Mode, Standby Mode,
Sleep Mode, and Reset
Vee
c:J
vee
Enable
Enable
NMI
NMI
IRO,
iJm",
POrt 3
8 Transfer
Lines
RES
Port 1
81/0
Lones
Port 1
81/0 Lines
Port 2
5110 Lines
POrt 4
8110 Lines
SCI
Port 4
81/0 Lines
Port 2
5110 Lines
SCI
vss
Vss
Figure 27 HD6301V1 MCU Single-Chip Dual Processor Configuration
280
~HITACHI
-----------------------HD6301V1,HD63A01V1,HD63B01V1
HD6301Vl
=
MCU
Address
Bus
Data
Bus
Address Bus
Figure 28 HD6301V1 MCU Expanded Non-Multiplexed Mode
(Mode 5)
Figure 29
Data Bus
HD6301 V1 MCU Expanded Multiplexed Mode
HD6301Vl MCU
16
Address Bus
8
Data Bus
Figure 30 HD6301V1 MCU Expanded Non-Multiplexed Mode (Mode 1)
~HITACHI
281
HD6301V1,HD63A01V1,HD63B01V1--------------------------------------------• Standby State
• PRECAUTION TO THE BOARD DESIGN OF OSCILLATION CIRCUIT
Only power supply pins and STBY pin are active. As for the
clock pin EXTAL, its input is fixed internally so the MCV is
not influenced by the pin conditions. XTAL is in "I" output.
All the other pins are in high impedance.
As shown in Fig. 31, there is a case that the cross talk disturbs the normal oscillation if signal lines are put near the
oscillation circuit. When designing a board, pay attention to
this. Crystal and CL must be put as near the HD6301 VI as
possible.
• DIFFERENCE BETWEEN HD6301VO and HD6301V1
The HD6301Vl is an upgraded version of the HD6301VO.
The difference between HD630IVO and HD6301Vl is shown
in Table 17.
~ ~
ii
ii
01
01
c:
c:
~ in
J7iCL. . . . . .
Table 17 Difference between HD6301VO and HD6301Vl
I
_....;....-(.1 XT AL
Item
t-<"'-+-"";""-i! EXTAL
HD6301VO
Operating
Mode
HD6301V1
HD6301Vl
Mode 2: Expanded
Multiplexed Mode
(Equivalent to Mode 4)
Mode 2: Not defined
The electrical characterElectrical
istics of 2MHz version
Character(B version) are not speciistics
fied.
Do not use this kind of print board design.
Figure 31 Precaution to the boad design of
oscillation circuit
Timer
Has problem in output
compare function.
(Can be avoided by software.)
Some characteristics
are improved.
The 2MHz version is
guaranteed.
The problem is solved.
• PIN CONDITIONS AT SLEEP AND STANDBY STATE
• Sleep State
The conditions of power supply pins, clock pins, input pins
and E clock pin are the same as those of operation. Refer to
Table 15 for the other pin conditions.
Table 15 Pin Condition in Sleep Mode
--.....:::::::.-- _
Pin
Port 1
P IO -P I7
Port 2
P2O -P 24
Port 3
Mode
-----------
6
7
.....
....
Function
1/0 Port
Lower Address Bus
1/0 Port
Keep the condition
just before sleep
Output "1"
Keep the condition
just before sleep
+-
.....
....
Function
1/0 Port
....
....
+-
+-
....
Condition
Keep the condition
just before sleep
....
....
....
+-
....
Function
E; Lower Address
Bus
E; Data Bus
Data Bus
E; Lower Address
Bus
E; Data Bus
Data Bus
Condition
E: Output "1"
E: High Impedance
High Impedance
E: Output "1"
E: High Impedance
High Impedance
E: OU':put "1"
Keep the condition
E: High Impedance just before sleep
!=unction
Upper Address
....
....
Lower Address Bus
or I nput Port
Upper Address Bus
or Input Port
Condition
Output "1"
+-
....
Address Bus: Out·
put "1"
Port: Keep the con·
dition just before
sleep
....
Keep the condition
just before sleep
SC2
Output "1"
(Read Condition)
+-
....
+-
.....
Output "1"
SCI
Output Address
Strobe
....
....
---
282
5
....
2.4
Conditi~n
p)O-P n
Port 4
P40 -P47
1
0
$
HITACHI
E; Lower Address
Output "1"
Bus
E: Data Bus
Output Address
Strobe
1/0 Port
I/O Port
Input Pin
- - - - - - - - - - - - - - - - - - - - - - HD6301V1,HD63A01V1,HD63B01V1
Table 16 Pin Condition during RESET
~e
pm
0,2,4,6
Port 1
PIO '" PI7
high impedance (input)
Port 2
P20'" P24
high impedance (input)
Port 3
P30 '" P37
E: "1" output
E: high impedance
Port 4
P40 '" P47
high impedance (input)
SC2
(RM)
SCI
(AS)
"1" output (Read)
E: "1" output
E: "0" output
1
.
..
high impedance
5
..
.
..
..
..
.
•
..
..
..
..
..
"1" output
"1" output
~HITACHI
7
high impedance (input)
283
HD6301 XO ,HD63A01 XO , - HD63B01XO
CMOS MCU (Microcomputer Unit)
-PRELIMINARYThe HD630lXO is a CMOS Single-chip microcomputer unit
(MCU) which includes it CPU compatible with the HD630lVl,
4k bytes of ROM, 192 bytes of RAM, 53 parallel I/O pins, a
Serial Communication Interface (SCI) and two timers on chip.
•
•
•
•
•
•
•
FEATURES
Instruction Set Compatible with the HD6301V1
Abundant On-chip Functions
4k Bytes of ROM, 192 Bytes of RAM
53 Parallel I/O Ports
16-Bit Programmable Timer
B·Bit Reloadable Timer
Serial Communication Interface
Memory Ready
Halt
Error·Detection (Address Trap, Op Code Trap)
Interrupts ... 3 External, 7 Internal
Operation Mode
Mode 1 ... Expanded (Internal ROM Inhibited)
Mode 2 •.. Expanded (Internal ROM Valid)
Mode 3 ... Single-chip Mode
Low Power Dissipation Mode
Sleep
Standby
Wide Range of Operation
Vee = 3 - 6V (f =0.1 - 0.5MHz).
Vee
(DP-64S)
HD6301XOF, HD63A01XOF,
HD63B01XOF
(FP-80)
=5V±10%(f =0.5 f =0.5 f
284
HD6301 XOP, HD63A01 XOP;
HD63B01XOP
1.0MHz; HD6301XO )
1.5MHz; HD63A01XO
0.5 - 2.0MHz; HD63B01XO
=
~HITACHI
---------------------------------------------HD6301XO,HD63A01XO,HD63B01XO
•
•
PIN ARRANGEMENT
HD6301XOP, HD63A01XOP, HD63B01XOP
v..
XTAl
EXTAl
iO
Pl1
1 P12
~
Ne ,
P30
p.,
P,.~
P32
~
p••
P22 11
P""
P1l
p,.
p..
p,.
lilii ,
P13
P,.
RES e
STBY 7
NMI 8
P"
HD6301XOF, HD63A01XOF, HD63B01XOF
p,.
3
MP.
MP,
•
p..
p..
l
, P37
p,.
P l1
P"
P 50 1
P12
P13
P14
p.,
PS1 '
p,.
PIO
p••
p.. 1
p••
p••
p.,
P"
Vss
1 P40
Poo
P41
p.,
p.,
Po
p.,
p..
p..
p••
Pu
p..
p••
p•• 1
p.,
P.,
Vee
(Top View)
(Top View)
•
BLOCK DIAGRAM
i
::Ii
...
i ::Iii
::Ii
v« _ __
V.. - - V.. - - -
I I
P2CJ(Tin)
P.. IToutl)'---1~
P,,{SCLK) ----¥~
p>oIiiii
P"tWA
Pu(Rx)
Pn/R/W
PN{Tx)
P,,{Tout2), --fl-t+1~
P,o(Tout3)-H++H+-I
P,,{TCLK)-'-:H+t+++-I
Pu!OR
P,.,SA
PwOo
P"dD I
Pu/0 2
Pu/o,
P).iID..
P"ID,
P./D.
P,,/O,
p.oI""
Pu/A,
Pu/Al
Pu/Al
PulA..
p."",
pt./A.
p""nm;)
p"jllllb)
P,,{MR)
P,,{iiAlT)
PI'
PI "A"
.l
P"
p..
P"
P"
POl
p..
p..
p..
P"",..
Pc,/A,
P41/"10
p.,/A'1
P.JAla
P.slA t )
P..JA t •
P.dA II
..
l
0:
g
co
t:
I.
RAM
ROM
192 By!ft
4k By!ft
P"
~HITACHI
285
HD6301XO,HD63A01XO,HD63B01XO--------------------------------------------•
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Supply Voltage
Vee
-0.3 - +7.0
Input Voltage
Yin
Operating Temperature
Topr
Tstg
-0.3 - Vee+0.3
0-+70
Storage Temperature
Unit
V
V
°c
°c
-55 - +150
INOTEI This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection
circuits. To assure the normal operation, we recommend Vin , Vout : VSS ~ IV in or Voutl ~ Vee.
, •
•
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee
=5.0V±10%, Vss =OV, T. =O-+70 o C, unless otherwise noted.)
Item
Symbol
Test Condition
RES,STBY
Input "High" Voltage
EXTAL
V 1H
Other Inputs
typ
-0.3
-
0.8
V
-
-
1.0
J.l.A
2.0
Input "Low" Voltage
All Inputs
V 1L
Input Leakage Current
NMI, RES, STBY,
MP o , MP 1 , Port 5
IIlnl
Yin = 0.5-V ee -0.5V
Three State (off-state)
Leakage Current
Ports 1,2,3,4,6,7
IITsd
Yin = 0.5-V ee -0.5V
Output "High" Voltage
min
Vee- 0 .5
Vee xO .7
-
1.0
J.l.A
-
Vee- 0 .7
-
-
V
IOH = -10J.l.A
0.4
V
10.0
mA
-
12.5
pF
3.0
15.0
1.5
3.0
J.l.A
mA
2.3
4.5
mA
3.0
6.0
mA
7.0
10.0
mA
10.5
15.0
mA
14.0
20.0
mA
-
-
V
All Outputs
VOL
IOL = 1.6mA
-
Darlington Drive
Current
Ports 2, 6
-loH
Vout = 1.5V
1.0
Input Capacitance
All Inputs
C in
Yin = OV, f = lMHz,
Ta = 25°C
Standby Current
Non Operation
ISTB
Sleeping (f = lMHz**)
Sleeping (f = 1.5MHz**)
Sleeping (f = 2MHz**)
Operating (f = lMHz**)
Operating (f = 1.5MHz**)
Operating (f = 2MHz**)
RAM Standby Voltage
V RAM
2.0
·V 1H min" Vee-1.OV, V1L max = O.SV IAII output terminals are at no load.)
··Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max.
values about Current Dissipations at x MHz operation are decided according to the following formula;
typo value If" x MHz) .. typo value If = 1MHz) x x
max. value If" x MHz) = max. value If = 1MHz) x x
Iboth the sleeping and operating)
286
V
-
Output "Low" Voltage
lee
Vee
+0.3
2.4
V OH
Current Dissipation *
Unit
IOH = -200J.l.A
All Outputs
IsLP
max
_HITACHI
V
- - - - - - - - - - - - - - - - - - - - - - - H 0630 1 XO,HD63AO 1XO,HD63B01 XO
•
AC CHARACTERISTICS (Vee = 5.0V±10%, Vss = OV, Ta = O-+70oC, unless otherwise noted.)
BUS TIMING
Item
Cycle Time
Enable Rise Time
Symbol
Test
Condition
HD6301XO
min
typ
HD63A01XO
max
min
typ
tCYC
1
-
10
0.666
tEr
-
-
25
-
25
-
Enable Fall Time
tEf
Enable Pulse Width "High" Level*
PWEH
450
-
Enable Pulse Width "Low" Level*
PWEL
450
-
Address, RIWDeiay Time*
tAD
-
Data Delay Time
toow
-
ns
-
-
ns
-
ns
190
-
160
ns
120
ns
-
ns
ns
160
70
-
50
-
-
35
-
40
-
-
0
-
300
-
-
220
-
-
ns
40
-
-
40
ns
25
ns
-
120
ns
-
ns
-
RD, WR Pulse Width*
PWRW
450
-
RD, WR Delay Time
tRWO
-
-
40
-
50
0
-
RD, WR Hold Time
tHRW
-
-
30
-
OR Delay Time
tOLR
-
200
-
rm Hold Time
-
tHLR
10
tSMR
400
-
10
MR Set-up Time*
280
M R Hold Time *
tHMR
PWEMR
-
90
E Clock Pulse Width at MR
-
-
9
Processor Control Set-up Time
tpcs
200
-
Processor· Control Rise Time
tpcr
Processor Control Fall Time
tpCf
BA Delay Time
teA
Fig. 3
-
-
Oscillator Stabilization Time
tRC
PW RST
Fig. 11
20
3
Reset Pulse Width
25
220
-
0
Fig. 2, 3
-
-
-
80
Fig. 3,
10, 11
25
200
tHR
Fig. 2
10
-
-
tHW
I
I
-
-
-
300
-
80
Fig. 1
0.5
250
80
tOSR
10
300
tAH
I Read
Unit
25
max
-
Address, R/W Hold Time*
Write*
Data Hold Time
Read
Data Set-up Time
typ
min
-
-
I Write
HD63B01XO
max
25
220
70
JJ.S
ns
ns
ns
30
-
160
10
-
-
-
-
40
ns
-
9
-
0
-
-
9
J.l.s
-
200
-
-
200
-
-
ns
100
-
ns
100
ns
-
20
-
-
3
-
100
-
-
100
250
-
100
230
100
190
-
20
3
ns
160
ns
-
ms
-
tcyc
• These timings change in approximate proportion to tcyc. The figures in this characteristics represent those when tcyc is
minimum- (= in the highest speed operation).
PERIPHERAL PORT TIMING
HD63A01XO
HD63B01XO
min
typ
max
min
typ
max
min
typ
max
tposu
Fig. 5
200
-
-
200
-
-
200
-
-
ns
tpOH
Fig. 5
200
-
-
200
-
-
200
-
-
ns
3o~ts6 '7 ' tpwo
, ., ,
Fig. 6
-
-
300
-
-
300
-
-
300
ns
Symbol
Peripheral Data
Set-upTime
Ports 2, 3, 5, 6
Peripheral Data
Hold Time
?orts 2, 3, 5, 6
Delay Time (Enable
Negative Transition to
Peripheral Data Valid)
HD6301XO
Test
Condition
Item
I
p
1 2
~HITACHI
Unit
287
HD6301XO,HD63A01XO,HD63B01XO---------------------TIMER, SCI TIMING
Item
Timer 1 Input Pulse Width
Delay Time (Enable Positive
Transition to Timer Output)
SCI Input
Clock Cycle
l
I
Async. Mode
Clock Sync.
HD6301XO
Symbol
Test
Condition
min
tPWT
Fig.B
2.0
tTOD
Fig.7
-
tScyC
tvp
HD63A01XO
max
min
-
-
2.0
400
-
typ
HD63B01XO
max
min
tvp
-
-
2.0
400
-
-
1.0
-
2.0
200
-
-
-
-
290
Fig. B
1.0
-
-
1.0
Fig.4,8
2.0
-
-
2.0
-
-
200
-
-
290
-
-
290
SCI Transmit Data Delay
Time (Clock Sync. Mode)
tTXD
SCI Receive Data Set-up
Time (Clock Sync. Mode)
tSRX
SCI Receive Data Hold Time
(Clock Sync. Mode)
tHRx
100
-
-
100
-
-
SCI Input Clock Pulse Width
Fig. 4
max
Unit
-
'tcyc
400
ns
-
tCYC
tCYc
200
ns
-
-
ns
100
-
-
ns
tSCYC
tPWSCK
0.4
-
0.6
0.4
-
0.6
0.4
-
0.6
Timer 2 Input Clock Cycle
ttcyC
2.0
-
-
-
tpwTCK
200
-
200
-
-
2.0
Timer 2 Input Clock Pulse
Width
-
2.0
200
-
-
Timer 1·2, SCI Input Clock
Rise Time
tCKr
-
-
100
-
-
100
-
-
100
ns
Timer 1·2, SCI Input Clock
Fall Time
tCKf
-
-
100
-
-
100
-
-
100
ns
288
Fig. 8
~HITACHI
tCYC
ns
----------------------HD6301XO,HD63A01XO,HD63B01XO
1-----------tCyc------------I
E
Ao-A15,
R/W
1-----PWEl---~
f-.---PWEH--------I
2.4V
O.BV
RO,WR
MCU Write
00-07
MCU Read
00-07
Figure 1 Mode 1, Mode 2 Bus Timing
I-------PWEMR-------t
\
E
\
\
'-----
O.8V
--1---1-- tHMR
MR
Figure 2 Memory Ready and E Clock Timing
$
HITACHI
289
HD6301XO,HD63A01XO,HD63B01XO---------------------------------------------Last Instruction
Execution Cycle
I
Instruction Execution
Cycle
HALT Cycle
·1
E
tBA~~,----~I~--------------------~
2.4V
SA
Figure 3 HALT and SA Timing
Synchronous Clock
Transmit Data
Receive Data
~
--(
tSRX
H
tHRXj
2.0V
___________~
~
________.
~O_.8_V
.~
_______
• 2.0V is high level when clock input.
2.4V is high level when clock output.
Figure 4 SCI Clocked Synchronous Timing
rE
E
P'O-P17. P20-P27----------~
P30- P37. P40- P47
PSO-P67. P70-P74----------(Outputs)
P30-P37
(I!'puts)
Figure 5 Port Data Set-up and Hold Times (MCU Read)
290
MCUWrite
~HITACHI
100...........- -
~~u.._ _
Figure 6 Port Data Delay Times IMCU Writ.)
----------------------HD6301XO,HD63A01XO,HD63B01XO
E
Timer 1 - - - -.... ,.-,..,L":;';;;':'==-- - - - FRC
P21 , P2S
--------.:.-..:..
Outputs - - - - - - - -.... 'Jt.~:.:....---
(a) Timer 1 Output Timing
(b) Timer 2 Output Timing
Figure 7
Timer Output Timing
Vee
m
RL =2.2kQ
Test Point
C
* Timer 2; ttcyc
SCI
1S2074(8)
or ~quiv.
C=90pF for Port 1, Port 3, Port 4, E
=30pF for Port 2, Port 6. Port 7
R= 12kQ for Port 1 - Port 4, Port 6, Port 7, E
* * Timer 1; tPWT
Timer 2; tPWTCK
;tPWSCK
; tSCYc
R
SCI
Figure 9 Bus Timing Test Loads (TTL Load)
Figure 8 Timer 1-2, SCI Input Clock Timing
Interrupt
Test
Internal
Address Bus _ _J,-I-......."-_..rI _ _"-_.J'~_J'\._...J"__J'\._......."-_J'\._......."-_-"_......."-_J\_......."-_-"...
NMI,
iimi.
iRQi.IR
When the TRCSR, TE bit is "1",
bit 4 is used as a serial output.
• Clock output regardless of the TRCSR, bit RE and TE .
•• Not used for the SCI.
Bit 6
Bit 7
TDa Transmit Data Bit a
When selecting 9·bit data fonnat in the asynchron·
ou·s mode, this bit. is transmitted as the 9th data. In
transmitting 9-bit data, write the 9th data into this bit
then write data to the receive data register.
RDa Receive Data Bit a
When selecting 9-bit data format in the asynchronous
mode, this bit stores the 9th bit data. In receiving 9·bit
data, read this bit then the receive data register.
• TIMER, SCI STATUS FLAG
Table 11 shows the set and reset conditions of each status
flag in the timer 1 , timer 2 and SCI.
Table 11 Timer 1, Timer 2 and SCI Status Flag
Timer
1
~
Set Condition
ICR by edge input to P20 •
ICF
FRC
OCFl
OCR1=FRC
2.
1.
OCF2
OCR2=FRC
2.
1.
TOF
FRC=$FFFF+1 cycle
1.
2.
Timer
2
CMF
T2CNT=TCON R
RORF
Receive Shift Register
ORFE
1.
2.
SCI
TORE
1.
2.
3.
1.
~
ROR
Framing Error (Asynchronous Mode)
Stop Bit= 0
Overrun Error (Asynchronous Mode)
Receive Shift Register ~ ROR when
RORF=l
Asynchronous Mode
TOR ~ Transmit Shift Register
Clocked Synchronous Mode
Transmit Shift Register is "empty"
FfES=o
2.
1.
2.
1.
2.
1.
2.
Reset Condition
Read the TCSR 1 or TCSR2 then ICRH,
when ICF=l
R£S=0
Read the TCSR 1 or TCSR2 then write to the
OCR1H orOCRll,when OCF1=1
R£S=0
Read the TCSR2 then write to the OCR2H or
OCR2l, when OCF2=1
m=O
Read the TCSRl then FRCH, when TOF=l
rn=O
Write "0" to CM F, when CM F = 1
rn=O
Read the TRCSR then ROR, when RORF=l
R"ES=O
Read the TRCSR then ROR, when ORFE=l
RES=O
Read the TRCSR then write to the TOR,
when TORE=l
(Notel 1. ~; transfer
2. For example; "ICRH" means High byte of ICR.
~HITACHI
307
HD6301XO,HD63A01XO,HD63B01XO--------------------------------------------for a system with no need of the HD630IXO's consecutive
operation.
• LOW POWER DISSIPATION MODE
The HD630lXO provides two low power dissipation modes;
sleep and standby.
• Standby Mode
The HD630lXO stops all the clocks and goes to the reset
state with STBY "low. In this mode, the power diSsipation is
reduced conspicuously. All pins except for the power supply,
the STBY and XTAL are detached from the MCU internally
and go to the high impedance state.
In this mode the power is supplied to the HD630IXO, so
the contents of RAM is retained. The MCU returns from this
mode during reset. The followings are typical usage of this
mode.
Save the CPU information and SP contents on RAM by NMI.
Then disable the RAME bit of the RAM control register and set
the STBY PWR bit to go to the standby mode. If the STBY
PWR bit is still set at reset start, that indicates the power is
supplied to the MCU and RAM contents are retained properly.
So system can restore itself by returning their pre-standby informations to the SP and the CPU. Fig. 24 depicts the timing at
each pin with this example.
• SleepMode
The MCU goes to the sleep mode by SLP instruction execution. In the sleep mode, the CPU stops its operation, while the
registers' contents are retained. In this mode, the peripherals
except the CPU such as timers, SCI etc. continue their functions. The power dissipation of sleep-condition is one fifth that
of operating condition.
The MCU returns from this mode by an interrupt, RES or
STBY; it goes to the reset state by RES and the standby mode
by STBY. When the CPU acknowledges an interrupt request, it
cancels the sleep mode, returns to the operation mode and
branches to the interrupt routine. When the CPU masks this
int~rrupt, it cancels the sleep mode and executes the next
instruction. However, for example if the timer 1 or 2 prohibits
a timer interrupt, the CPU doesn't cancel the sleep mode because of no interrupt request.
This sleep mode is effective to reduce the power dissipation
Vee
HD6301XO
I
-----If
....-11111
-----11
...-J
:
I
I
1
r:
(
1I&I.-----"""""1J~
111111
Il0l
1
I
:
1
~
o Save Registers
I
oIEosc·llla~tlor
o RAM/Port 5 Control
Register Set
Start Time
~
Restart
Figure 24 Standby Mode Timing
•
TRAP FUNCTION
The CPU generates an interrupt with the highest priority
(TRAP) when fetching an undefmed instruction or an instruction from non-memory space. The TRAP prevents the systemburst caused by noise or a program error.
• Op Code Error
When fetching an undefmed op code, the CPU saves CPU
registers as well as a normal interrupt and branches to the TRAP
($FFEE, $FFEF). This provides the priority next to reset.
• Address Error
When an instruction fetch is made excluding internal ROM,
RAM and external memory area, the MCU generates an interrupt as well as an op code error. But on the system with no
memory in its external memory area, this error processing is not
applicable if an instruction fetch is made from the external non-
308
memory area. Table 12 provides addresses where an address
error occurs to each mode.
This processing is available only for an instruction fetch and
is not applicable to the access of normal data read/write.
Table 12 Addresses Applicable to Address Errors
Mode
1
2
3
Address
$0000
1
$OOlF
$0000
1
$OOlF
$0000
1
$003F
$0100
1
$EFFF
~HITACHI
---------------------------------------------HD6301XO,HD63A01XO,HD63B01XO
(Note) The TRAP interrupt provides a retry function differently from other interrupts. This is a program flow return
to the address where the TRAP occurs when a sequence
returns to a main routine from the TRAP interrupt
routine by RTI. The retry can prevent the system burst
caused by noise etc.
However, if another TRAP occurs, the program repeats
the TRAP interrupt forever, so the consideration is
necessary in programming.
•
INSTRUCTION SET
The HD6301XO provides object code upward compatible
with the HD6801 to utilize all instruction set of the
HMCS6800. It also reduces the execution times of key instructions for throughput improvement.
Bit manipulation instruction, change instruction of the
index register and accumulator and sleep instruction are also
added.
The followings are explained here.
• CPU Programming Model (refer to Fig. 25)
• Addressing Mode
• Accumulator and Memory Manipulation Instruction
(refer to Table 13)
• New Instruction
• Index Register and Stack Manipulation Instruction
(refer to Table 14)
• Jump and Branch Instruction (refer to Table 15)
• Condition Code Register Manipulation
(refer to Table 16)
• Op Code Map (refer to Table 17)
B is selected. This is a one-byte instruction.
Immediate Addressing
This addressing locates a data in the second byte of an
instruction. However, LDS and LDX locate a data in the second
and third byte exceptionally. This addressing is a 2 or 3-byte
instruction.
Direct Addressing
In this addressing mode, the second byte of an instruction shows the address where a data is stored. 256 bytes ($0
through $255) can be addressed directly. Execution times
can be reduced by storing data in this area so it is recommended
to make it RAM for users' data area in configurating a system.
This is a 2-byte instruction, while 3 byte with regard to AIM,
OIM, ElM and TIM.
Extended Addressing
In this mode, the second byte shows the upper 8 bit of the
data stored address and the third byte the lower 8 bit. This
indicates the absolute address of 3 byte instruction in the
memory.
Indexed Addressing
The second byte of an instruction and the lower 8 bit of the
index register are added in this mode. As for AIM, OIM, ElM
and TIM, the third byte of an instruction and the lower 8 bits
of the index register are added.
This carry is added to the upper 8 bit of the index register
and the result is used for addressing the memory. The modified
address is retained in the temporary address register, so the contents of the index register doesn't change. This is a 2-byte
instruction except AIM, OIM, ElM and TIM (3-byte instruction).
Implied Addressing
•
Programming Model
Fig.25 depicts the HD6301XO programming model. The
double accumulator D consists of accumulator A and B, so
when using the accumulator D, the contents of A and Bare
destroyed.
E
,,- -
°U
A
-
-
-
- -
-
7
0 -
j
8
- -
- -
-
-
1.5
I"
SP
1'5
PC
7
-
0
1 Inde.ReglS'If tXt
0
1
0
1 Progr.m Count... fPCI
SllItk Po,nter IS')
Relative Addressing
The second byte of an instruction and the lower 8 bits of
the program counter are added. The carry or borrow is added to
the upper 8 bit. So addressing from -126 to +129 byte of the
current instruction is enabled. This is a 2-byte instruction.
(Note) CLI, SEI Instructions and Interrupt Operation
When accepting the IRQ at a preset timing with the help
of CLI and SEI instructions, more than 2 cycles are
necessary between the CLI and SEI instructions. For
example, the following program (a) (b) don't accept the
IRQ but (c) accepts it.
0
~
'
8·B,. Accumulo'.n A ond B
~ Or 16·81. Double Accu""ul.~or 0
An instruction itself specifies the address. That is, the
instruction addresses a stack pointer, index register etc. This is a
one-byte instruction.
H
I
N Z
V C
Condllton Code Reg.slet' leeR)
earry/Borrow trom MSB
Overflow
CLI
SEI
CLI
NOP
SEI
CLI
NOP
NOP
SEI
(a)
(b)
(c)
Z...
NeII llwe
Interrupt
Hat. Carry IFromBltll
Figure 25 CPU Programming Model
•
CPU Addressing Mode
The HD6301XO provides 7 addressing modes. The addressing
mode is decided by an instruction type and code. Table 13
through 17 show addressing modes of each instruction with
the execution times counted by the machine cycle.
When the clock frequency is 4 MHz, the machine cycle time
becomes microseconds directly.
Accumulator (ACCX) Addressing
The same thing can be said to the TAP instruction
instead of the CLI and SEI instructions.
Only an accumulator is addressed and the accumulator A or
~HITACHI
309
HD6301XO,HD63A01XO,HD63B01XO---------------------------------------------Table 13 Accumulator, Memory Manipulation Instructions
Condition Code
Addressing Modes
Operations
Mnemonic
DIRECT
IMMED
OP
EXTEND
INDEX
-
#
OP
-
#
OP
-
#
OP
-
#
2
2
9B
3
2
AB
4
2
BB
4
3
2
DB 3
2
EB
4
2
FB
4
3
Add
ADDA
8B
ADDB
CB
2
Add Double
ADDD
C3
3 3 03 4 2 E3 5 2 F3 5 3
Add Accumulators
ABA
Add With Carry
AND
Bit Test
Clear
-1--
-
--
I-
---
B+M-+B
2
2
99
3
2
A9
4
2
B9
4
3
A+M+C-A
2
2
09
3
2
E9
4
2 F9
---.-
4
3
B+M+C-B
ANDA
84
2
2
94
3
2
A4
4
2
B4
4
3
A'M-+A
ANDB
C4
2
2
04
3
2
E4
4
2
F4
4
B·M- B
BIT A
85
2
2
95
3 2 A5
4
2
B5
A·M
BIT B
C5
2
2 05
E5
4
2 ' F5
4
'4
3
3
3
B·M
6F
5 2 7F
3
2
CLR
81
CMPB
Cl
COM
2
'2
-
91
3
2
Al
4
2
Bl
4
3
2
01
3
2
El
4
2
Fl
4
3
-+- I-- f----- I--
4F
r---
SF
2
6
2
73
6
3
1--1--
COMB
6
2
70
6
~ ~~O-+A
1
1
1
1
1
1 OO-B-+B
NEGB
50
1
DAA
19
2
Decrement
DEC
6
3
--
OO-A-+A
Converts binary add of BCD
1 characters into BCD format
--I-- ~M -1-+M
DECA
4A
1
1
A-I -+ A
OECB
SA
1
1
B-l-+B
EORA
88
2
2
98
3
2
A8
4
2
B8
4
EORB
C8
2
2
08
3
2
E8
4
2
F8
6C
6
2
7C
4 3
---I-- ~.
6 3
INC
3
1---
B ~ M-+ B
M+l -+M
INCA
4C
1 1
A + 1 -+ A
INCB
5C
1
8 + 1-+ B
LDAA
86
2
2
96
3
2
A6
4
2
B6
4
3
LOAB
C6
2
2
06
3
2
E6
4
2
F6
4
3
Load Double
Accumulator
LDO
CC
3
3
DC 4
2
EC
5 2 FC 5 3
Multiply Unsigned
MUL
OR, Inclusi\ltl
ORAA
8A
2
2
9A
3
2
AA 4
ORAB
CA
2
2
OA 3
2
EA 4
I- ~- 1-- 1----2
BA 4
3
FA 4
3
M-+A
-~-------
M -+ B
30
B
1
33
4
4
3
3
49
1
36
PSHB
37
Pull Data
PULA
32
Rot.te Left
ROL
69
6
2
79
6
59
ROLB
66
6
2
76
6
1
B -+ Msp, SP - 1 -+ SP
SP + 1 -+ SP. Msp -+ A
1
SP + 1-+ SP. Msp-+ B
1
:}~IIIIII
B
C b7
1
RORA
46
1
1
RORB
56
1
1
~HITACHI
B
1
3
(Note) Condition Code Register will be explained in Note of Table 16.
+M-~
A -+ Msp, SP - 1 -+ SP
1
3
ROLA
ROR
7 1 AxB-+A:B
A+M-+A
PSHA
1i t
t t~ t
t t~ t
t t 6 t
t t 6 t
t t 6 t
R t 6 t
R t @t
R t@t
t
kID
t t
t t
R
R
t t
R
R
t
···
t t t t
t t t t
t t t t
t t t t
t t t t
t t t t
t t R
t t R
t t
t t
t t
t
I
I
t
··
R R
R R
R R
t R
t R
I
R
I
R
•
•
•
•
(Note) Condition Code Register will be explained in Note of Table 16 .
• Additional Instruction
In addition to the H06801 instruction set, the HD630lXO
prepares the fonowing new instructions.
AIM •...•. , (M)o(IMM) ... (M)
Executes "AND" operation to immediate data and the
memory contents and stores its result in the memory.
TIM . . . . . . . (M). (IMM)
Executes "AND" operation to immediate data and
changes the relative flag of the condition code register.
These area 3-byte instructions; the first byte is op code, the
second immediate data and the third address modifier.
XGDX ..... (ACCD)
OIM . . . • . . . (M) + (IMM) ... (M)
~
(IX)
Exchanges the contents of accumulator and the index
register.
Executes "OR" operation to immediate data and the
memory contents and stores its result in the memory.
SLP
ElM • • • • . • . (M) <±> (IMM) ... (M)
Executes "EaR" operation to immediate data and the
memory contents and stores its result in the memory.
~HITACHI
Goes to the sleep mode. Refer to "LOW POWER DISSIP ATION MODE" for more details of the sleep mode.
311
Table 14 Index Register, Stack Manipulation Instructions
Condition Code
Register
Addressing Modes
Pointer Operations
IMMED.
Mnemonic
OP Compare Index Reg
Decrement Index Reg
CPX
DEX
~----------~~--~~-----
Decrement Stack Pntr
Increment Index Reg
Increment Stack Pntr
DIRECT
OP -
-
t
___
1:9= tit
Load Index Reg
LOX
Store Index Reg
Store Stack Pntr
STX
STS _
~''''~---lOS .
--1-1--- I !---
---
~
INDEX
OP -
#
EXTEND
IMPLIED
OP -
OP -
#
2 AC 5 2 BC 5 3
~
+.
INX
j
INS- - -
#
81*3 3 9C 4
~E-S-._ --~-t---t-
-----~.--------~
5 4 3 2 1 0
I N Z V C
H
#
······ ·• • I.·· ··
~~'_-~i-_14f---1+s-P=-~=1="'.~S.~P========~=~=~=~~~~~~~
·· ·· ·· · · ··
··.'.·· ··
···· · · · ···
1
X-M:M+1
1 X - 1 ... X
.1--- ___
09
--f---f--
1
08 . 1
t
1 X + 1'" X
--+--j.-.,>----+,--+---I-3....,.1+1+-1+SP::-+-:-1....--=-SP=-------+-+-+-~Hf--
-
!--- .~~+_c~-+-4~~~--~~--~-4--~~~~+--
5 2
FE 5
3
M ... XH,(M+lI'"XL
(j)
t R
(f)
t R
(f) t R
~~ ~t2='_+T-E+f--.;:..5-+l-.::..2-+-=-B~E~-~5~~3~~-=-~~~~-=-~M-=--..._--=S~P.!.:H'2.-=~,-(_M-=-+-=-1-~)-..._-.::..S-!!P~:...L~-:f-.-_+i--_+:':::..-!-+.:...:...-!-+-.:...4.;---
§'
t- _ _
'OF 4_+~
_+i9~ ~
R~ ~~_
~_ f--
EF
5 2 FF 5 3
2_
_ 3
T A~ ~
~~ ~
--~----+----1--++--+-
XH"'M XL"'(M+1)
7
SP H ...
SP L-"'-(::M +-:";1
~,
35
1
1
(/" t R
)+-+-+~-:-+-::-+-
X - 1'" SP
_~---.~~~=1-=-3:::0~1~11~1~~S:--P;;-:--:--+;1=...~-:-X::--------:..----------1+--·~;·~;·~t·~t·=t·=
---+_.+.+.-+.-+.-+._
--I--f-- _1-_1-_ ++-+__+--+-+-=-3A-+.::..1+-1-+=-B_+_X_...
__X_ _ _ _ _
3C
38
PULX
5 1 XL'" M.. , SP - 1 ... SP
XH'" M.. ,SP -1'" SP
4 1 SP + 1 ... SP, Mop ... XH
SP + 1'" SP,M.. '" XL
Exchange
t : t
t
-4---~~~~--~~~~~--------~+-~+-+-+--
'CEj3 3 DE 42 EE
Index Reg ... Stack Pntr f---"!:.~~ __
Stack Pntr ... Inde"
Add
A~)( __ _
Push Data
PSHX
Pull Data
#
Booleanl
Arithmetic Operation
XGDX
18
2
1 ACCD··IX
·.....
• •••••
(Note) Condition Code Register will be explained in Note of Table 16.
Table 15 Jump, Branch Instruction
Addressing Modes
()perations
Branch Always
Branch Never
Branch If Carry Clear
Branch If Carry Set
Branch If - Zero
Branch If ;. Zero
Branch If > Zero
Branch If Higher
Branch If < Zero
Branch If Lower Or
Same
Branch If < Zero
Branch If Minus
Branch If Not Equal
Zero
Branch If Overflow
Clear
Branch If Overflow Set
Branch If Plus
Branch To Subroutine
Jump
Jump To Subroutine
Mnemonic
BRA
BRN
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
INDEX
EXTEND IMPLIED
RELATIVE DIRECT
OP
# OP
# OP
# OP
# OP
#
20 3 2 I
21 3 2
24 3 2
25 3 2
27 3 2
2C 3 2
2E 3 2
22 3 2
2F 3 2
-
3 2 .
BLS
23
BLT
BMI
20 3 2
2B 3 2
-
-
-
-
I
Branch Test
None
None
C=O
C=l
Z= 1
NGlV-O
Z + (N Gl VI = 0
C+Z=O
Z + iN Gl VI· 1
C+Z=1
NGlV=1
N -1
BNE
26
3 2
Z=O
BVC
28
3 2
V-O
BVS
BPL
BSR
JMP
JSR
29 3 2
2A 3 2
80 5 2
V= 1
N-O
6E 3 2 7E 3 3
90 5 2 AD 5 2 BD 6 3
1 1
No Operation
NOP
01
Return From Interrupt
Return From
Subroutine
Software Interrupt
Weit for InterrUPtSleep
RTI
3B 10 1
RTS
39
SWI
WAI
SLP
3F 12 1
3E 9 1
1A 4 1
Advances. Prog. Cntr.
Only
5 1
(Note) * WAI puts R/W high; Address Bus goes to FFFF; Data Bus goes to the three state.
Condition Code Register will be explained in Note of Table 16.
312
~HITACHI
Condition Code
Register
5 4 3 2 1 0
H I N Z V C
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
··· ··· ··· ··· ··· ···
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
··· ··.- ··· ··· ··· ···
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
··· ev·· ·· ·•·· ··· ···
••• ••
--@ - -
S
---------------------------------------------HD6301XO,HD63A01XO,HD63B01XO
Table 16 Condition Code Register Manipulation Instructions
\AddressingModes
Operations
Mnemonic
Condition Code Aegister
IMPLIED
Boolean Operation
OP
-
#
Clear Carry
ClC
OC
1
1
Clear Interrupt Mask
Cli
OE
1
1
O-C
0-1
Clear Overflow
ClV
OA
1
1
O-V
Set earry
SEC
1
1
Set Interrupt Mask
SEI
,
1- C
I-I
Set Overflow
Accumulator A- CCA
SEV
TAP
00
OF
OB
CCA - Accumulator A
TPA
1
06
07
4
3
2
1
H
I
N
Z
V
0
C
·· · ·· ·· ·· ·
··· ·· ··· ··· ·· ··
···· ·
······
A
A
A
S
S
1
1
1
I-V
1
A- CCA
1
1
CCA - A
LEGEND
OP Operation Code (Hexadecimal)
Number of MCU Cycles
Msp Contents of memory location pointed to by Stack Pointer
#
Number of Program Bytes
+
Arithmetic Plus
Arithmetic Minus
•
Boolean AND
+
Boolean Inclusive OR
e Boolean Exclusive OR
M Complement of M
~
Transfer into
OBit = Zero
00 Byte Zero
5
S
---
@
---
CONDITION CODE SYMBOLS
H
Half-carry from bit 3 to bit 4
I
Interrupt mask
N
Negative (sign bit)
Z
Zero (byte)
V
Overflow, 2's complement
C
Carry/Borrow from Ito bit 7
R
Reset Always
S
Set Always
Set if true after test or clear
•
Not Affected
t
=
(Note)
Condition Code Register Notes: (Bit set if test is true and cleared otherwise)
CD
(Bit V)
Test: Result = 100000007
@
@
@
(Bit C)
Test: Result ~ 000000007
(Bit C)
(Bit V)
Test: BCD Character of high-order byte greater than 107
Test: Operand = 10000000 prior to execution?
®
®
=01111111
(Not cleared if previously set!
prior to execution 7
(Bit V)
Test: Operand
(Bit V)
(Bit N)
(All Bit)
Test: Set equal to N<:D C = 1 after the execution of instructions
Test: Result less than zero? (Bit 15=1)
Load Condition Code Register from Stack.
@)
(Bit I)
(All Bit)
Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exist the wait state.
Set according to the contents of Accumulator A.
®
(Bit C)
Result of Multiplication Bit 7=17 (ACCB)
(])
®
®
Table 17 OP-Code Map
DP
ACC
ACC
CODE
A
B
0100
0101
0110
4
5
6
~ °
~
0000
lO
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
101O
1011
1100
1101
1110
1111
0001
I
~OlO
2
0011
SBA
BRA
3
TSX
CBA
BRN
INS
BHI
PULA
3
~ ~
~ ~
BlS
PUlB
4
lSRD
BCC
DES
5
ASlD
~
BCS
TXS
6
TAP
TAB
BNE
PSHA
7
TPA
TBA
BEQ
PSHB
8
INX
XGDX BVC
PUlX
°
1
Nap
2
~
IND
~ '1000DIR
0"1
7
NEG
~
-----
---
8
----------ACCB or X
ACCA or SP
-IMM ~IR
1001
_L
9
liND
I
1 1010 ¥Ol I
I
A
aiM
COM
1100 1"01
C
B
ADOD
ElM
AND
3
4
BIT
5
lOA
ROR
~I
ASR
9
RTS
ROl
BPl
ABX
DEC
ORA
RTI
PSHX
0
E
Cli
F
SEI
SEC
°
I
I:JNDEFINED OP CODE
BlT
MUl
BGT
WAI
BlE
SWI
2
3
-----
B
CPX
TST
BSR
I
ClR
6
lOD
~J
JSR
7
.------1
8
I
I
0
lOX
.------1
STS
9
C
STD
lOS
JMP
5
8
ADD
TIM
INC
~~
4
7
A
BVS
BGE
STA
EaR
SlP
BMI
6
~I
STA
ASl
DAA
ABA
1111
F
0
SUBD
lSR
DEX
~
~
~
~
1
I
ClV
SEV
E
2
9
ClC
I 11 10 I
I
SBC
A
B
0
CMP
ADC
C
I
SUB
1------1------
AIM
IM~.llOlR-T IN~
EXT
A
I
B
C
1
E
F
STX
o
1
E
1
F
~
• Only each instructions of AIM, OIM, ElM, TIM
$
HITACHI
313
HD6301 X O , H D 6 3 A 0 1 X O , H D 6 3 B 0 1 X O - - - - - - - - - - - - - - - - - - - - - • CPU OPERATION
• CPU Instruction Flow
When operating, the CPU fetches an instruction from a
memory an~ecutes the required function. This sequence
starts with RES cancel and repeats itself limitlessly if not
affected by a special instruction or a control Signal. SWI, RTI,
WAf and SLP instructions are to change this operation, while
NMI, IRQ1, IRQl, IRQ3, HALT and STBYare to control it.
Fig. 26 gives the CPU mode transition and Fig. 27 the CPU
system flow chart. Table 18 shows CPU operating states and
port sta tes.
• Operation at Each Instruction Cycle
Table 19 provides the operation at each instruction cycle.
By the pipeline control of the HD6301XO, MULT, PUL, DAA
and XGDX instructions etc. pre fetch the next instruction. So
attention is necessary to the counting of the instruction cycles
because it is different from the existent one·····op code fetch
to the next instruction op code.
Table 18 CPU Operation State and Port State
Figure 26 CPU Operation Mode Transition
Port
Mode
Reset
Port 1
lAo -A 7 )
Mode 1,2
H
Mode 3
T
Port 2
Mode 1,2
Mode 3
T
T
T
Mode 1,2
Port 4
IA •. -A IS )
Mode 1,2
H
Mode 3
T
Port 5
Port 6
Port 7
Mode 1,2
Mode 3
Mode 1,2
T
T
Mode 1,2
.
Mode 3
T
Mode 3
T
T
Port 3
(Do -0 7 )
Mode 3
STBy· .. •
T
T
T
T
H; High, L; Low, T; High Impedance
• RD,WR,RIW,LlR=H,BA=L
RD, WR, RIW-T, LIR, BAcH
HALT is unacceptable in mode 3.
E pin goes to high impedance state.
314
HALT"·
------T
Keep
-----T
T
---..
T
----Keep
Sleep
H
Keep
Keep
T
Keep
H
Keep
T
Keep
.
Keep
_HITACHI
PC.IX
ACCA
(Note)
1. The program sequence will come to the RES start from
any place of the flow during RES. When STBY=O. the
sequence will go into the standby mode regardless of the CPU
condition.
2. Refer to "FUNCTIONAL PIN DESCRIPTION" for more
details of interrupts.
~
:t:
~
()
:t:
::r:
o
0)
(,J
o
~
X
P
::r:
o
0)
N
(,J
»
o
X
,0
::r:
o
0)
(,J
O:J
~
C1I
Figure 27 HD6301XO System Flow Chart
o
~
X
o
HD6301XO,HD63A01XO,HD63B01XO---------------------Table 19 Cycle-by-Cycle Operation
Address Mode &
Instructions
IMMEDIATE
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
ADDD CPX
LDD
LDS
LDX
SUBD
DIRECT
ADC
AND
CMP
LDA
SBC
STA
ADD
BIT
EOR
ORA
SUB
Address Bus
CPX
LDS
SUBD
STD
STX
STS
1
2
Op Code Address + 1
Op Code Address + 2
1
1
1
2
3
Op Code Address + 1
Op Code Address + 2
Op Code Address + 3
1
1
1
0
0
0
1
2
3
Op Code Address + 1
Address of Operand
Op Code Address +2
1
1
1
0
0
0
1
2
3
1
2
3
Op Code Address + 1
Destination Address
Op Code Address + 2
Op Code Address + 1
Address of Operand
Address of Operand + 1
Op Code Address+2
Op Code Address+ 1
Destination Address
Destination Address + 1
Op Code Address+2
Op Code Address+ 1
1
0
1
1
1
1
1
2
3
3
3
ADDD
LDD
LDX
4
4
1
2
3
4
JSR
5
1
2
3
4
6
FFFF
1
2
3
4
FFFF
5
Address of Operand
Op Code Address + 3
1
2
3
4
ElM
I
Stack Pointer
Stack Pointer - 1
Jump Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
Address of Operand
4
5
TIM
I
1
1
1
0
Operand Data
Next Op Code
1
1
1
1
1
0
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
1
1
1
1
1
0
Address of Operand (LSB)
Operand Data
Next Op Code
0
1
1
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
Destination Address
Accumulator Data
Next Op Code
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Next Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
0
0
I
4
AIM
OIM
Data Bus
6
1
0
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
0
i
I
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
0
(Continued)
316
$
HITACHI
---------------------------------------------HD6301XO,HD63A01XO,HD63B01XO
Address Mode &
Instructions
Address Bus
INDEXED
JMP
3
ADC
AND
CMP
lOA
SBC
TST
STA
ADD
BIT
EOR
ORA
SUB
4
4
1
2
3
1
2
3
4
1
2
3
4
ADDD
CPX
lOS
SUBD
lDD
lOX
5
1
2
3
4
5
STD
STX
STS
5
1
2
3
4
5
JSR
5
1
2
3
4
5
ASl
COM
INC
NEG
ROR
ASR
DEC
lSR
ROl
6
1
2
3
4
5
6
TIM
5
1
2
3
4
5
CLR
5
1
2
3
4
5
AIM
OIM
ElM
1
2
3
7
4
5
6
7
Data Bus
Op Code Address+ 1
FFFF
Jump Address
Op Code Address+ 1
FFFF
IX + Offset
Op Code Address+2
1
1
1
1
1
1
1
0
1
0
0
1
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
Offset
Restart Address (lSB)
First Op Code of Jump Routine
Offset
Restart Address (lSB)
Operand Data
Next Op Code
Op Code Address+ 1
FFFF
IX + Offset
Op Code Address+2
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address+2
Op Code Address+ 1
FFFF
IX + Offset
IX+Offset+l
Op Code Address+2
Op Code Address+l
FFFF
Stack Pointer
Stack Pointer - 1
IX + Offset
Op Code Address+ 1
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address+ 1
Op Code Address + 1
Op Code Address+2
FFFF
IX + Offset
Op Code Address+3
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset
Op Code Address + 2
Op Code Address+ 1
Op Code Address+2
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address+3
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
0
1
1
0
0
1
0
0
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
1
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
0
Offset
Restart Address (lSB)
Accumulator Data
Next Op Code
Offset
Restart Address (lSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Offset
Restart Address (lSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Offset
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
First Subroutine Op Code
Offset
Restart Address (lSB)
Operand Data
Restart Address (lSB)
New Operand Data
Next Op Code
Immediate Data
Offset
Restart Address (lSB)
Operand Data
Next Op Code
Offset
Restart Address (lSB)
Operand Data
00
Next Op Code
Immediate Data
Offset
Restart Address (lSB)
Operand Data
Restart Address (lSB)
New ·Operand Data
Next Op Code
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
(Continued)
~HITACHI
317
HD6301XO,HD63A01XO,HD63B01XO--------------------------------------------Address Mode 8.
Instructions
Address Bus
Data Bus
EXTEND
JMP
3
ADC
AND
CMP
LDA
SBC
STA
ADD
BIT
EOR
ORA
SUB
TST
4
1
2
3
1
2
3
4
4
1
2
3
4
ADDD
CPX
LDS
SUBD
STD
STX
LDD
LDX
5
1
2
3
4
5
STS
5
1
2
3
4
5
JSR
6
ASL
COM
INC
NEG
ROR
ASR
DEC
LSR
ROL
6
CLR
5
1
2
3
4
5
6
1
2
3
4
5
6
1
2
3
4
5
Op Code Address + 1
Op Code Address + 2
Jump Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Op Code Address + 3
1
1
1
1
1
1
1
0
0
0
0
0
0
0
Op Code Address + 1
Op Code Address + 2
Destination Address
Op Code Address+3
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
Destination Address
Destination Address + 1
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
FFFF
Stack Pointer
Stack Pointer - 1
Jump Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
FFFF
Address of Operand
Op Code Address + 3
Op Code Address+ 1
Op Code Address + 2
Address of Operand
Address of Operand
Op Code Address + 3
1
1
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
1
0
1
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
Jump Address (MSB)
Jump Address (LSB)
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Next Op Code
Destination Address (MSB)
Destination Address (LSB)
Accumulator Data
Next Op Code
Address-otOperand (MSB)
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (MSB)
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
jump Address (MSB)
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
00
Next Op Code
(Continued)
318
~HITACHI
---------------------------------------------HD6301XO,HD63A01XO,HD63B01XO
Address Mode &
Instructions
IMPLIED
ABA
ASL
ASR
CLC
CLR
COM
DES
INC
INX
LSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
DAA
ABX
ASLD
CBA
CLI
CLV
DEC
DEX
INS
LSR
ROL
NOP
SEC
SEV
TAP
TPA
TSX
XGDX
PULA
PULB
PSHA
PSHB
Address Bus
1
Op Code Address + 1
1
1
2
1
2
Op Code Address+ 1
FFFF
Op Code Address+ 1
FFFF
Stack Pointer + 1
Op Code Address+ 1
FFFF
Stack Pointer
Op Code Address+ 1
Op Code Address+ 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Op Code Address+l
FFFF
Stack Pointer
Stack Pointer-l
Op Code Address+ 1
Op Code "Address+ 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Return Address
Op Code Address + 1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
0
Next Op Code
0
Next Op Code
Restart Address (LSB)
Next Op Code
Restart Address (LSB)
Data from Stack
Next Op Code
Restart Address (LSB)
Accumulator Data
Next Op Code
Next Op Code
Restart Address (LSB)
Data from Stack (MSB)
Data from Stack (LSB)
Next Op Code
Restart Address (LSB)
Index Register (LSB)
Index Register (MSB)
Next Op Code
Next Op Code
Restart Address (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
1
2
3
3
4
PULX
4
1
2
3
4
1
2
3
4
1
2
PSHX
5
3
4
5
1
2
RTS
5
MUL
Data Bus
f---
3
4
5
,2
7
3
4
5
6
7
0
1
0
1
0
0
1
1
- - ~"1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
- - c-----;"
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
1
1
1
(Continued)
~HITACHI
319
HD6301XO,HD63A01X~HD63B01XO~~~~~~~~~~~~~~~~~~~~~~
Address Mode lit
Instructions
Address Bus
Data Bus
IMPLIED
WAI
9
1
2
3
4
5 .
6
7
8
9
RTI
10
1
2
3
4
5
6
7
8
9
10
,-
SWI
12
2
3
4
5
6
7
8
9
10
11
12
1
2
SLP
4
Op Code Address + 1
FFFF
Stack Pointer
Star.k Pointer-1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer-4
Stack Pointer-5
Stack Pointer - 6
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer+4
Stack Pointer + 5
Stack Pointer + 6
Stack Pointer + 7
Return Address
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer-4
Stack
Pointer-6
..
,,' Po'0",-5
I
I
1
I
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
'+.
Vector Address FFFA
Vector Address FFFB
Address of SWI Routine
Op Code Address + 1
FFFF
r
Sleep
1
3
4
FFFF
Op Code Address + 1
Next Op Code
Restart Address ILSB)
Return Address ILSB)
Return Address IMSB)
Index Register ILSB)
Index Register IMSB)
Accumulator A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address ILSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register IMSB)
Index Register ILSB)
Return Address IMSB)
Return Address ILSB)
First OpCode of Return Routine
Next Op Code
Restart Address ILSB)
Return Address ILSB)
Return Address IMSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)
Address of SWI Routine (LSB)
First Op Code of SWI Routine
Next Op Code
Restart Address ILSB)
I
1
1
1
1
0
1
1
1
1
0
Restart Address ILSB)
Next Op Code
1
1
0
1
1
1
1
1
1
0
1
0
Branch Offset
Restart Address (LSB)
First Op Code of Branch Routine
Next Op Code
1
1
0
0
1
0
1
1
1
0
1
1
0
0
1
1
1
1
1
0
RELATIVE
BCC
BEQ
BGT
BLE
BLT
BNE
BRA
BVC
BSR
BCS
BGE
BHI
BLS
BMT
BPL
BRN
BVS
3
1
2
3
1
2
5
3
4
5
320
Op Code Address + 1
I
FFFF
Branch Address······Test=·1·
OpCode Address+1···Test=·O··I
1
Op Code Address + 1
FFFF
Stack Pointer
. Stack Pointer-l
Branch Address
$
HITACHI
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Op Code of Subroutine
HD6301 YO,HD63A01 YO,--HD63B01YO
CMOS MCU (Microcomputer Unit)
-ADVANCE INFORMATIONThe HD6301 YO is a CMOS 8-bit single-chip microcomputer
unit which contains a CPU compatible with the CMOS 8-bit
microcomputer HD6301Vl, 16k bytes of ROM, 256 bytes of
RAM, 53 parallel I/O pins, Serial Communication Interface
(SCI) and two timers.
•
FEATURES
•
•
Instruction Set Compatible with the HD6301 Family
Abundant On-chip Resources
• 16k Bytes of ROM, 256 Bytes of RAM
• 53 Parallel I/O Pins (48 I/O Pins, 5 Output Pins)
• Handshake I nterface (Port 6)
• Darlington Transistor Direct Drive (Port 2, 6)
• 16-bit Programmable Timer
1 I nput Capture Register
1 Free Running Counter
2 Output Compare Registers
• 8-Bit Reloadable Timer
1 8·bit Up Counter
1 Time Constant Register
• Serial Communication Interface
Asynchronous Mode
8 Transmit Formats
Hardware Parity
Clocked Synchronous Mode
Interrupts - 3 External, 7 Internal
CPU Functions
• Memory Ready, Auto Memory Ready
•
•
HD6301YOP, HD63A01YOP,
HD63B01YOP
(DP-64S)
HD6301YOF, HD63A01YOF,
HD63B01YOF
•
•
•
•
•
•
•
Halt
Error Detection
(Address Trap, Op-code Trap)
Operation Mode
• Mode 1; Expanded Mode
(Internal ROM Inhibited)
• Mode 2; ~xpanded Mode
(Internal ROM Valid)
• Mode 3; Single Chip Mode
Up to 65k Bytes Address Space
Low Power Dissipation Mode
• Sleep
• Standby (HardWare Set, Software Set)
Wide Range of Operation
Vee = 3 to 6V
(f = 0: 1 to 0.5 MHz)
f =0.1 to 1.0 MHz; HD6301YO )
Vee = 5V ± 10%
f = 0.1 to 1.5MHz; HD63A01YO
(
f =0.1 to 2.0 MHz; HD63BOl YO
Minimum Instruction Cycle Time; 0.5 J1.s (f 2.0 MHz)
(FP-64)
=
@HITACHI
321
• PIN ARRANGEMENT
• HD6301YOF.HD63A01YOF.HD63B01YOF
• HD6301YOP.HD63A01YOP.HD63B01YOP
V.. 1 0
XTAL ~
EXTAL 3
MPo
MP,
RES
P70
P71
1 P72
P"
P74
p.
P3,
PI2
Pn
P34
P3•
PH
, P"
P,O
P"
PI2
7 P'3
P,.
P,.
8
SfiY~
;mJ~
Pzo 9
P"1ll
P22 II
Pu 1
p•• 1
p.. 1
p•• ,
P27 ,
PIO 1
P" ,
PI2 1
PI3
p .. 1
p..
p..
P., •
PIO
P.,
p.. 7
Pu 8
p..
p..
P..
P"
V..
1 P40
P.,
3 P••
3 P'3
~Pp.,
..
~ p••
PH~
3 P47
gj
P"
Vee
(TopViewl
(Top Viewl
• BLOCK DIAGRAM
P20(Ti" )
P2I(TOUI,)
P,,(SClK)
P23(R. )
P2.(T. )
P20(Tout.)
P2.(Tou!3)
P,,(TClK)
P30100
P3'/O,
P32/0.
P33/03
P3.tO.
P35/0.
P,./o.
P,,/o,
Poo(imI, )
P5I(imI2 )
P02(MR )
P03(RArT)
Po.OS
)
Poo(OS )
Po.
Po,
P.oIA.
P.,jA.
p.o
P••/A,.
p,.
P.,/A,.
P'2/A,o
P'3/A"
P• .tA,.
P.o/A"
p.,
p ..
p..
P••
p ••
P.,
322
$
HITACHI
HD6303R, HD63A03R,---HD63B03R
CMOS MPU (Micro Processing Unit)
The HD6303R is an 8-bit CMOS micro processing unit
which has the completely compatible instruction set with the
HD6301Vl. 128 bytes RAM, Serial Communication Interface
(SCI), parallel I/O ports and multi function timer are incorporated in the HD6303R. It is bus compatible with HMCS6800 and
can be expanded up to 65k words. Like the HMCS6800 family,
I/O levels is TTL compatible with +5.0V single power supply.
As the HD6303R is CMOS MPU, power dissipation is extremely
low. And also HD6303R has Sleep Mode and Stand-by Mode
as lower power dissipation mode. Therefore, flexible low power
consumption application is possible.
• FEATURES
• Object Code· Upward Compatible with the HD6800, HD6801,
HD6802
• Multiplexed Bus (D o-D 7 /A o-A 7 ), Non Multiplexed Bus
• Abundant On-Chip Functions Compatible with the
HD6301V1; 128 Bytes RAM, 13 Parallel I/O Lines, 16-bit
Timer, Serial Communication Interface (SCI)
• Low Power Consumption Mode; Sleep Mode, Stand-By Mode
• Minimum Instruction Execution Time
11'5 (f=1MHz), 0.67ps (f=1.5MHz), 0.51ls (f=2.0MHz)
•
•
Bit Manipulation, Bit Test Instruction
Error Detecting Function; Address Trap, Op Code Trap
•
Up to 65k Words Address Space
•
TYPE OF PRODUCTS
Type No.
HD6303RP, HD63A03RP,
HD63B03RP
(DP-40)
•
HD6303RF, HD63A03RF,
HD63B03RF
(FP-54)
H D6303RCG, H D63A03RCG,
HD63B03RCG
Bus Timing
HD6303R
HD63A03R
1.0 MHz
1.5 MHz
HD63B03R
2.0 MHz
~.
~.>
(CG-40)
~HITACHI
323
HD6303R,HD63A03R,HD63B03R - - - - - - - - - - - - - - - - - - - - - - • PIN ARRANGEMENT
•
•
HD6303RP, HD63A03RP,
HD63B03RP
~
....
Ii_ Iiz ~w ~
E
0
•
HD6303RF, HD63A03RF,
HD63B03RF
X
>::l
HD6303RCG, HD63A03RCG,
HD63B03RCG
",I~ ~
w
O,/A,
D,/A,
D,/A,
D./A.
D,/A,
[~O
A7/P17
D:S As/P,s
[lz A4/p'4
A,o
~J
~J
All
A"
All
r~i
AJ/PI3 22
r':::'l r~l r~1 r~l f=1 r~l r~l r:!~ r~1
~ ~ f
A..
Vee
l f f ~ i {
f
~
en
;'~;'i.
~~~~
u
u
>
11'1
'It
M
....
-
««<
(Top View)
(Top View)
(Top View)
BLOCK DIAGRAM
..J
..J«
~~~~ 1~lal~
»xwwZ!!:a:
...___-+-~-
P20
~-....+--
P 2!
.....-+-.....-4~- P 22
Address!
.....4--Ht--- P23
P 24
Data
Buffers
.....- - -... P,o/Ao
.....- - -... PillA,
....----P'2/A2
1-----P'3/A3
.....- - -... P'4/A.
P,s/A5
.....- - -... P"/A,
PI7/A 7
Address
Buffers
324
A'4
[I,? As/P,s
A.
•
[2~
[~1 Vee
A.
A..
A'2
A13
[2:2 A,s
O,/AJ
O./A.
D./A.
D./A.
D./A.
[~~
~~
$
HITACHI
~ <:
D~
Aa/P13
-----------------------HD6303R,HD63A03R,HD63B03R
• ABSOLUTE MAXIMUM RATINGS
Unit
Value
Symbol
Item
~
Supply Voltage
Vee
-0.3
Input Voltage
Yin
Operating Temperature
Top.
-0.3 ~ Vee+0.3
O~ +70
V
°c
Storage Temperature
Tstg
-55
°c
(NOTE)
+7.0
V
~+150
This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection
circuits. To assure the normal operation, we recommend Vin, V out : VSS ;:;; (Vin or V out ) ~ Vee.
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vcc = 5.0V±10%, Vss = OV, Ta = O~+70°C, unless otherwise noted.)
Symbol
Item
Test Condition
RES, STBY
Input "High" Voltage
EXTAL
V 1H
min
typ
Vee-0.5
Vee xO.7
-
2.0
-
max
Unit
Vee
+0.3
V
Input "Low" Voltage
All Inputs
V 1L
Input Leakage Current
NMI, IRQ" RES, STBY
II in I
Yin =0.5~Vee-0.5V
-
-
Three State (off-state)
Leakage Current
Do~D7. A8~A'5
ilTSli
Yin =0.5~Vee-0.5V
-
-
1.0
p.A
2.4
-
Vee- 0.7
-
V
0.55
V
pF
Other Inputs
PlO~P17' P20~P24'
-0.3
IOH = -200p.A
0.8
V
1.0
p.A
V
Output "High" Voltage
All Outputs
V OH
Output "Low" Voltage
All Outputs
VOL
IOL = 1.6mA
-
-
Cin
Vin=OV, f=1.0MHz,
Ta = 25°C
-
-
12.5
2.0
15.0
p.A
Operating (f=l MHz**)
-
6.0
Sleeping (f=lMHz**)
-
1.0
10.0
2.0
mA
2.0
-
-
Input Capacitance
All Inputs
StI+---1-+--
0
1 0
1
Z, Yo X,
y,o-------------------~~~
0
1 1 0
Z, Y , X.
0
1
1 1
Z, Y , X,
1
X X X
XoO----------------4C+~1_~--
X
X10----------
ZoO----------------~;;?H--,
Z,O----------------------~Qr~
Z
C B A H014053B
-
Figure 12 HD14053B Multiplexers/De-Multiplexers
Vee
Vee
Enable
Port 1
To 8 Address Lines
Port 1
81/0 lines
Do - 0,
80eta Lines
Ao -A 7
Multiplexed
DatalAddress
Port 2
5110 Lines
SCI
Timer
Port 2
5 Parallel 1/0
SCI
Timer
A. -Au
8 Address
Lines
A. -Au
8 Add" ..
Lines
Vss
Vss
Figure 13 HD6303R MPU Multiplexed Mode
332
Figure 14 HD6303R MPU Non Multiplexed Mode
e HITACHI
GND
II
AS
I
G OC
a,
0,
D./A. - Q,/A,
Address/Data
Function Table
A,", •• A. -A,
74LS373
[
Output
Control
a.
D.
)
Figure 15
Multiplexed Mode
Non Multiplexed Mode
Output
G
0
a
L
L
L
H
H
H
L
H
L
X
X
H
L
x
a.
z
0 ... 0,-0,
Latch Connection
Table 3 Mode Selection
Operating Mode
Enable
tOCI
Table 4 Internal Register Area
P20
P 21
P 22
L
H
L
L
L
H
H
L
L
Register
Port 1
Port 2
Port 1
Port 2
Data
Data
Data
Data
Direction Register··
Direction Register··
Register
Register
Timer Control and Status Register
Counter (High Byte)
Counter (Low Byte)
Output Compare Register (High Byte)
L: logiC "0"
H: logic "1"
• MEMORY MAP
The MPU can provide up to 6Sk byte address space. Figure
16 shows a memory map for each operating mode. The first 32
locations of eacn map are for the CPU's internal register only,
as shown in Table 4.
Output Compare Register (Low Byte)
Input Capture Register (High Byte)
Input Capture Register (Low Byte)
Rate and Mode Control Register
Transmit/Receive Control and Status Register
Receive Data Register
Transmit Data Register
RAM Control Register
Reserved
Address
00·
01
02·
03
08
09
OA
OB
OC
00
OE
10
11
12
13
14
15·1F
• External address in Non Multiplexed Mode
1 = Output, 0 = Input
Non-Multiplexed
$0000
Internal Registers
Inte,nal Registers
SOOIF
E x:ternal Memorv Space
External Memorv Space
$0080
InlernalRAM
Internal RAM
SOOFF
External Memorv Space
External Memotv Space
SFFFF ' -_ _....IJ
[NOiE)
Excludes the following addresses which may be
used externally; $00, $02.
SFFFF~
_ _....I'
Figure 16 HD6303R Memory Maps
$
HITACHI
333
HD6303R,HD63A03R,HD63B03R----------------------• PROGRAMMABLE TIMER
The HD6303R contains 16-bit programmable timer which
may be used to make measurement of input waveform. In
addition to that it can generate an output waveform by itself.
For both input and output waveform, the pulse width may vary
from a few microseconds to several seconds.
The timer hardware consists of
• an 8-bit control and status register
• a 16-bit free running counter
• a 16-bit output compare register, and
• a 16-bit input capture register
A block diagram of the timer is shown in Figure 17.
H06303R Internal Bus
8111
Pori 2
OOR
(SAFJ written to the counterl
Figure 18 Counter Write Timing
• Output Compare Register ($OOOB:$OOOC)
This is a 16-bit read/write register which is used to control an
output waveform. The contents of this register are constantly
being compared with current value of the free running counter.
When the contents match with the value of the free running
counter, a flag (OCF) in the timer control/status register
(TCSR) is set and the current value of an output level Bit
(OLVL) in the TCSR is transferred to Port 2 bit 1. When bit I
of the Port 2 data direction register is "I" (output), the OLVL
value will appear on the bit I of Port 2. Then, the value of Output Compare Register and Output level bit may be changed
for the next compare.
The output compare register is set to $FFFF during reset.
The compare function is inhibited at the cycle of writing to
the high byte of the output compare register and at the cycle
just after that to ensure valid compare. It is also inhibited in
same manner at writing to the free running counter.
In order to write a data to Output Compare Register, a
double byte store instruction (ex.STD) must be used.
•
- - ---
-~
Output Input
Ltv.'
Edge
Bill
BIIO
Pon 2
Port2
Figure 17 Programmable Timer Block Diagram
•
Free Running Counter ($0009: $OOOA)
The key element in the' programmable timer is a J6-bit free
running counter, that is driven by an E (Enable) clock to
increment its values. The counter value will be read out by the
CPU software at any time with no effects on the counter.
Reset will clear the counter.
When the MSB of this counter is read, the LSB is stored
in temporary latch. The data is fetched from this latch by the
subsequent read of LSB. Thus consistent double byte data can
be read from the counter.
When the CPU writes arbitrary data to the MSB ($09), the
value of $FFF8 is being pre-set to the counter ($09, $OA)
regardless of the write data value. Then the CPU writes arbitrary data to the LSB ($OA), the data is set to the "Low" byte
of the counter, at the same time, the data preceedingly written
in the MSB ($09) is set to "High" byte of the counter.
When the data is written to this counter, a double byte
store instruction (ex. STD) must be used. If only the MSB of
counter is written, the counter is set to $FFF8.
The counter value written to the counter using the double
byte store instruction is shown in Figure 18.
To write to the counter can disturb serial operations, so it
should be inhibited during using the SCI. If external clock
mode is used for SCI, this will not disturb serial operations.
Input Capture Register ($0000: $OOOE)
The input capture register is a 16-bit read-only register used
to hold the current value of free running counter captured when
the proper transition of an external input signal occurs.
The input transition change required to trigger the counter
transfer is controlled by the input edge bit (IEDG).
To allow the external input signal to go in the edge detect
unit, the bit of the Data Direction Register corresponding to bit
oof Port 2 must have been cleared (to zero).
To insure input capture in all cases, the width of an input
pulse requires at least 2 Enable cycles.
• Timer Control/Status Register (TCSR) ($0008)
This is an 8-bit register. All 8-bits are readable and the lower
5 bits may be written. The upper 3 bits are read-only, indicating
the timer status information as is shown below.
(1) A proper transition has been detected on the input pin
(ICF).
(2) A match has been found between the value in the free
running counter and the output compare register (OCF).
(3) When counting up to $0000 (TO F).
Each flag has an individual enable bit in TCSR which
determines whether or not an interrupt request may occur
(IRQ2). If the I-bit in Condition Code Register has been
cleared, a priority vectored address occurs corresponding
to each flag. A description of each bit is as follows.
Timer Control I Status Register
7654
J
210
I'CF I OCF I TOF I EICI I EOCI I ETOII'EOG I OLVL I s0008
Bit 0
334
~HITACHI
OLVL (Output Level); When a match is found in the
value between the counter and the output com-
pare register, this bit is transferred to the Port 2
bit 1. If the DDR corresponding to Port 2 bit 1 is
set "1 ", the value will appear on the output pin of
Port 2 bit 1.
Bit 1 IEDG (Input Edge): This bit control which transition
of an input of Port 2 bit 0 will trigger the data
transfer from the counter to the input capture
register. The DDR corresponding to Port 2 bit 0
must be clear in advance of using this function.
When IEDG = 0, trigger takes place on a negative
edge ("High':"to-"Low" transition). When IEDG =
1, trigger takes place on a positive edge ("Low"-to"High" tranSition).
Bit 2 ETOI (Enable Timer Overflow Interrupt); When set,
this bit enables TOF interrupt to generate the
interrupt request (lRQz). When cleared, the interrupt is inhibited.
Bit 3 EOCI (Enable Output Compare Interrupt); When set,
this bit enables OCF interrupt to generate the
interrupt request (1RQ2). When cleared, the interrupt is inhibited.
Bit 4 EICI (Enable Input Capture Interrupt); When set, this
bit enables ICF interrupt to generate the interrupt
request (IRQi). When cleared, the interrupt is
inhibited.
Bit 5 TOF (Timer Over Flow Flag); This read-only bit is set
at the transition of $FFFF to $0000 of the
counter. It is cleared by CPU read of TCSR (with
TOF set) followed by a CPU read of the counter
($0009).
Bit 6 OCF (Output Compare Flag); This read-only bit is set
when a match is found in the value between the
output compare register and the counter. It is
cleared by a read of TCSR (with OCF set) followed by a CPU write to the output compare register ($OOOB or $OOOC).
Bit 7 ICF (Input Capture Flag); The read-only bit is set by a
proper transition on the input, and is cleared by
a read of TCSR (with ICF set) followed by a
CPU read of Input Capture Register ($OOOD).
Reset will clear each bit of Timer Control and Status
Register.
• SERIAL COMMUNICATION INTERFACE
The HD6303R contains a full-duplex asynchronous Serial
Communication Interface (SCI), SCI may select the several
kinds of the data rate. It consists of a transmitter and a receiver
which operate independently but with the same data format
and the same data rate. Both of transmitter and receiver communicate with the CPU via the data bus and with the outside
world through Port 2 bit 2, 3 and 4. Description of hardware,
software and register is as follows.
• Wake-Up Feature
In typical multiprocessor applications the software protocol
will usually have the designated address at the initial byte of the
message. The purpose of Wake-Up feature is to have the nonselected MPU neglect the remainder of the message. Thus
the non-selected MPU can inhibit the all further interrupt
process until the next message begins.
Wake-Up feature is re-enabled by a ten consecutive "l"s
which indicates an idle transmit line. Therefore software protocol must put an idle period between the messages and must
prevent it within the message.
With this hardware feature, the non-selected MPU is reenabled (or "waked-up") by the next message.
•
Programmable Options
'The HD6303R has the following programmable features.
• data format; standard mark/space (NRZ)
• clock source; external or internal
• baud rate; one of 4 rates per given E clock frequency or
1/8 of external clock
• wake-up feature; enabled or disabled
• interrupt requests; enabled or masked individually for
transmitter and receiver
.c1ock output; internal clock enabled or disabled to Port
2 bit 2
·Port 2 (bits 3, 4); dedicated or not dedicated to serial
I/O individually
• Serial Communication Hardware
The serial communications hardware is controlled by 4
regis.ters as shown in Figure 19. The registers include:
• an 8-bit control/status register
• a 4-bit rate/mode control register (write-only)
• an 8-bit read-only receive data register
• an 8-bit write-only transmit data register
Besides these 4 registers, Serial I/O utilizes Port 2 bit 3
(input) and bit 4 (output). Port 2 bit 2 can be used when an
option is selected for the internal-clock-out or the externalclock-in.
•
Transmit/Receive Control Status Register (TRCSR)
TRCS Register consists of 8 bits which all may be read while
only bits 0 to 4 may be written. The register is initialized to $20
on RES. The bits of the TRCS Register are explained below.
Transmit I Receive Control Status Register
76543210
I I I I I I I I wu
AOAF ORFE TORE
RIE
RE
TIE
TE
IADDR
10011
Bit 0 WU (Wake Up); Set by software and cleared by hardware
on receipt of ten consecutive "I "s. While this bit
is "I", RDRF and ORFE flags are not set even
if data are received or errors are detected. Therefore received data are ignored. It should be noted
that RE flag must have already been set in advance
ofWU flag's set.
Bit 1 TE (Transmit Enable); This bit enables transmitter. When
this bit is set, bit 4 of Port 2 DDR is also forced
to be set. It remains set even if TE is cleared.
Preamble of ten consecutive "I "s is transmitted
just after this bit is set, and then transmitter
becomes ready to send data. If this bit is cleared,
the transmitter is disabled and serial I/O affects
nothing on Port 2 bit 4.
Bit 2 TIE (Transmit Interrupt Enable); When this bit is set,
TDRE (bit 5) causes an IIDh interrupt. When
cleared, TDRE interrupt is masked.
Bit 3 RE (Receive Enable); When set, Port 2 bit 3 can be used
as an input of receive regardless of DDR value for
this bit. When cleared, the receiver is disabled.
Bit 4 RIE (Receive Interrupt Enable); When this bit is set,
RDRF (bit 7) or ORFE (bit 6) cause an TlUJ2
interrupt. When cleared, this interrupt is masked.
_HITACHI
335
ceIVmg bit stream. When Framing Error is detected, RDRF is not set. Therefore Framing Error
can be distinguished from Overrun Error. That is,
if ORFE is "1" and RDRF is "1", Overrun Error
is detected. Otherwise Framing Error occurs.
The bit is cleared by reading the status register
followed by reading the receive data register, or
by REs.
Bit 7 RDRF (Receive Data Register Full); This bit is set by
hardware when the data is transferred from the
receive shift register to the receive data register.
It is cleared by reading the status register followed
by reading the receive data register, or by RES.
Bit 5 TORE (Transmit Data Register Empty); When the data
is transferred from the Transmit Data Register
to Output Shift Register, this bit is set by hardware. The bit is cleared by reading the status register followed by writing the next new data into
the Transmit Data Register. TDRE is initialized
to 1 by RES.
Bit 6 ORFE (Over Run Framing Error); When overrun or
framing error occurs (receive only), this bit is set
by hardware. Over Run Error occurs if the attempt
is made to transfer the new byte to the receive
data register while the RDRF is "1". Framing
Error occurs when the bit counter is not synchronized with the boundary of the byte in the re-
Bit 7
Rat. and Mode ConHol Register
I
Bit 0
I cc, Icco Iss, Isso IS,
0
Transmit/Receive Control and Status Register
POll
'1
Receive Shift Register
CloCk
10
Bit . . .- - ' - - - - - - -....
....- - - E
2
~-----------Figure 19 Serial 1/0 Register
o
6
x
x
CCl
CCO
551
550
ADDR
$0010
Transfer Rate I Mode Control Register
Table 5 SCI Bit Times and Transfer Rates
SS1 : SSO
336
XTAL
2.4576 MHz
4.0 MHz
E
614.4 kHz
1.0MHz
~s/62.500 Baud
4.9152MHz
1.2288MHz
13
/ls/76.8oo8aud
0
0
E.;. 16
26 ~s/38.400 Baud
16
0
1
E.;. 128
2081Js/4.800 Baud
128 ~s/7812.5 Baud
104.2/ls/ 9.6ooBaud
1
0
E.;. 1024
1.67ms/600 Baud
1.024ms/976.6 Baud
833.3/ls/ 1.2oo8aud
1
1
E.;. 4096
6.67ms/150 Baud
4.096ms/244.1 Baud
3.333ms/
I
~HITACHI
300Baud
-----------------------HD6303R,HD63A03R,HD63B03R
Table 6 SCI Format and Clock Source Control
CC1:CCO
Format
0
0
0
-
1
NRZ
1
1
0
1
Clock Source
I
Port 2 Bit 2
-
Internal
Not Used ***
NRZ
Internal
Output"
NRZ
External
Input
Port 2 Bit 3
Port 2Bit 4
...
..
......
-
"
• Clock output is available regardless of values for bits RE and TE .
•• Bit 3 is used for serial input if RE = "1" in TRCS.
Bit 4 is used for serial output if TE= "'" in TRCS.
H O This pin can be used as I/O port.
• Transfer Rate/Mode Control Register (RMCR)
The register controls the following serial I/O functions:
• Bauds rate
·data format
• clock source
• Port 2 bit 2 feature
It is 4-bit write-only register, cleared by RES. The 4 bits are
considered as a pair of 2-bit fields. The lower 2 bits control the
bit rate of internal clock while the upper 2 bits control the
format and the clock select logic.
Bit 0 SSO}
Speed Select
Bit 1 SSI
These bits select the Baud rate for the internal clock. The
rates selectable are function of E clock frequency of the CPU.
Table 5 lists the available Baud Rates.
Bit2 CCO }
Bit 3 CCl
Clock Control/Format Select
They control the data format and the clock select logic.
Table 6 defines the bit field.
• Internally Generated Clock
If the user wish to use externally an internal clock of the
serial I/O, the following requirements should be noted.
'CCl, CCO must be set to "10".
'The maximum clock rate must be E/I6.
• The clock rate is equal to the bit rate.
• The values of RE and TE have no effect.
•
Externally Generated Clock
If the user wish to supply an external clock to the Serial
I/O, the following requirements should be noted.
• The CC 1, CCO must be set to "11" (See Table 6).
• The external clock must be set to 8 times of the desired
baud rate.
• The maximum external clock frequency is E/2 clock.
• Serial Operations
The serial I/O hardware must be initialized by the software
before operation. The sequence will be normally as follows.
'Writing the desired operation control bits of the Rate and
Mode Control Regi8ter.
• Writing the desired operation control bits of the TRCS
register.
If Port 2 bit 3, 4 are used for serial I/O, TE, RE bits may be
kept set. When TE, RE bit are cleared during SCI operation,
and subsequently set again, it should be noted that TE, RE
must be kept "0" for at least one bit time of the current baud
rate. If TE, RE are set again within one bit time, there may be
the case where the initialiZing of internal function for transmitter and receiver does not take place correctly.
• Transmit Operation
Data transmission is enabled by the TE bit in the TRCS
register. When set, the output of the transmit shift register
is connected with Port 2 bit 4 which is unconditionally configured as an output.
After RES, the user should initialize both the RMC register
and the TRCS register for desired operation. Setting the TE bit
causes a transmission of ten-bit preamble of" 1"s. Following the
preamble, internal synchronization is established and the transmitter is ready to operate. Then either of the following states
exists.
(1) If the transmit data register is empty (TDRE = 1), the
consecutive "I"s are transmitted indicating an idle
states.
(2) If the data has been loaded into the Transmit Data
Register (TDRE = 0), it is transferred to the output
shift register and data transmission begins.
During the data transfer, the start bit ("0") is !lrst trans·
ferred. Next the 8·bit data (beginning at bit 0) and finally the
stop bit ("1 "). When the contents of the Transmit D.Ha Register
is transferred to the output shift register, the hardware sets the
TDRE flag bit: If the CPU fails to respond to the flag within
the proper time, TDRE is kept set and then a continuous string
of 1's is sent until the data is supplied to the data register.
• Receive Operation
The receive operation is enabled by the RE bit. The serial
input is connected with Port 2 bit 3. The receiver operation
is determined by the contents of the TRCS and RMC register.
The received bit stream is synchronized by the first "0" (start
bit). During IO-bit time, the data is strobed approximately at
the center of each bit. If the tenth bit is not "1" (stop bit),
the system assumes a framing error and the ORFE is set.
If the tenth bit is "1 ", the data is transferred to the rec'eive
data register, and the RDRF flag is set. If the tenth bit of the
next data is received and still RDRF is preserved set, then
ORFE is set indicating that an overrun error has occurred.
After the CPU read of the status register as a response to
RDRF flag or ORFE flag, followed by the CPU read of the
receive data register, RDRF or ORFE will be cleared.
• RAM CONTROL REGISTER
The register aSSigned to the address $0014 gives a status
information about standby RAM.
RAM Control Register
8
5
4
320
Bit 0 Not used.
Bit 1 Not used.
Bit 2 Not used.
~HITACHI
337
Bit 3 Not used.
Bit 4 Not used.
Bit 5 Not used.
Bit 6 RAM Enable.
Using this control bit, the user can disable the RAM. RAM
Enable bit is' set on the positive edge of RES and RAM is
enabled. The program can write "I" or "0". If RAME is
cleared, the RAM address becomes external address and the
CPU may read the data from the outside memory.
Bit 7 Standby Bit
This bit can be read or written by the user program. It is
cleared when the Vee voltage is removed. Normally this bit
is set by the program before going into stand·by mode. When
the CPU recovers from stand·by mode, this bit should be
checked. If it is "I ", the data of the RAM is retained during
stand·by and it is valid.
• GENERAL DESCRIPTION OF INSTRUCTION SET
The HD6303R has an upward object code compatible with
the HD6801 to utilize all instruction sets of the HMCS6800.
The execution time of the key instruction is reduced to increase
the system through·put. In addition, the bit operation instruc·
tion, the exchange instruction between the index and the
accumulator, the sleep instruction are added. This section
describes:
• CPU programming model (See Fig. 20)
• Addressing modes
• Accumulator and memory manipulation instructions (See
Table 7)
• New instructions
• Index register and stack manipulation instructions (See
Table 8)
• Jump and branch instructions (See Table 9)
• Condition code register manipulation instructions (See
Table 10)
·Op-code map (See Table 11)
• Cycle-by-cycle operation (See Table 12)
• CPU Programming Model
The programming model for the HD6303R is shown in Figure 20. The double accumulator is phYSically the same as the
accumulator A concatenated with the accumulator B, so that
the contents of A and B is changed with executing operation of
an accumulator D.
E----
A____0:U: ___
,!t
0
1.5
1. 5
Sl'
1,5
PC
.! ___
3
8·Bit Accumulators A and B
~
Or 16·81t Double Accumulator 0
01
Index Register (XI
01
Stack Pointer (SP)
o1 Program Coun ter
,
every instruction is shown along with execution time given in
terms of machine cycles (Table 7 to 11). When the clock
frequency is 4 MHz, the machine cycle will be microseconds.
Accumulator (ACCX) Addressing
Only the accumulator (A or B) is addressed. Either accumulator A or B is specified by one-byte instructions.
Immediate Addressing
In this mode, the operand is stored in the second byte of the
instruction except that the operand in LDS and LDX, etc are
stored in the second and the third byte. These are two or
three-byte instructions.
Direct Addressing
In this mode, the second byte of instruction indicates the
address where the operand is stored. Direct addressing allows
the user to directly address the lowest 256 bytes in the machine;
locations zero through 255. Improyed execution times are
achieved by storing data in these locations. For system
configuration, it is recommended that these locations should be
RAM and be utilized preferably for user's data realm. These are
two-byte instructions except the AIM, OIM, ElM and TIM
which have three-byte.
Extended Addressing
In this mode, the second byte indicates the upper 8 bit
addresses where the operand is stored, while the third byte
indicates the lower 8 bits. This is an absolute address in
memory. These are three-byte instructions.
Indexed Addressing
In this mode, the contents of the second byte is added to the
lower 8 bits in the Index Register. For each of AIM, OIM, ElM
and TIM instructions, the contents of the third byte are added
to the lower 8 bits in the Index Register. In addition, the result·
ing "carry" is added to the upper 8 bits in the Index Register.
The result is used for addressing memory. Because the modified
address is held in the Temporary Address Register, there is no
change to the Index Register. These are two-byte instructions
but AIM, OIM, ElM, TIM have three-byte.
Implied Addressing
In this mode, the instruction itself gives the address; stack
pointer, index register, etc. These are. I-byte instructions .
Relative Addressing
In this mode, the contents of the second byte is added to the
lower 8 bits in the program counter. The resulting carry or
borrow is added to the upper 8 bits. This helps the user to
address the data within a range of -126 to +129 bytes of the
current execution instruction. These are two-byte instructions.
(PC)
0
'
~
HI'" Z V C
condit. ion Code Re 9.iSter (CCR)
Carry/Borrow from MSB
Overflow
Zero
Negative
Interrupt
Half Carry (From Bit 3)
Figure 20 CPU Programming Model
• CPU Addressing Modes
The HD6303R has seven address modes which depend on
both ofthe·instruction type and the code. The address mode for
338
~HITACHI
Table 7 Accumulator, Memory Manipulation Instructions
Condition Code
Addressing Modes
()peretions
Mnemonic
IMMED
OP -
DIRECT
•
OP
-
INDEX
• OP -
•
Register
EXTEND
OP
2 AB 4 2 BB
2 EB 4 2 FB
2 E3 5 2 F3
-
Boolean/
Arithmetic Operation
IMPLIED
.OP
-•
H
A+M-A
4 3
4 3
ADDA
8B
ADDB
CB
2 2 9B 3
2 2 DB 3
Add Doab..
ADDD
C3
3 3 03 4
Add Accumuletors
ABA
Add With Carry
ADCA
89
2 2 99
3 2
A9
4 2 B9
4
ADCB
2 2 09
2 2 94
2 E9
3 2 A4
3 2 E4
4 2 F9
4 2 B4
4 2 F4
4
3
B+M+C-B
4
3
A'M-A
AN DB
C9
B4
C4
4
3
B·M-B
BITA
85
Add
AND
Bit Test
ANDA
BIT B
B+M-B
2 2 04
1 1 A+B-A
A+M+C-A
3
2 2 95 3 2 AS 4 2 B5 4 3
C5 2 2 05 3 2 E5 4 2 F5 4 3
6F
7F
CLR
CLRA
4F
1
SF
1 1 OO-B
~
CLRB
CMPA
81
CMPB
Cl
Compere
Accumuletorl
Complement. I'.
Complement, 2',
(Negate'
Decimal Adjust, A
Dec_nt
ExcluliwOR
Loed
Accumuletor
3 2
3 ,2
Al
4
El
2 81
4 2 Fl
63
6
6
43
60
6
2 70
6
1 1 OO-A-A
1 1 OO-B-B
DAA
19
Converts binary add of BCD
2 1 characters into 8CD format
DEC
SA 6 2
7A 6
4A
DECB
SA
EORA
8B
C8
2 2 98
3 2
2 2 08 3
INC
AI 4 2 B8 4 3
2 E8
6C
F8
4
3
B@M ... B
6
3
M+l-M
INCA
4C
1 1 A+ l"'A
INCB
5C
1 1 8 + 1'" B
M ... A
LDAA
86
2 2 96 3 2 A6
2 2 06 3 2 E6
C6
LDD
CC 3 3 DC 4
Multiply UnlilMd
MUL
OR,lnclusiw
ORAA
ORAB
4
4
2 EC 5
4
2 F6
4
3
M-B
FC
5
3
M+ I"'B,M ... A
2
3D
A+M"'A
B +M- B
Push 0 ...
PSHA
36
PuIiDIta
PSHB
PULA
32
37
69
6
2 79
6
1 A ... Mil», SP - 1 ... SP
1 B ... Mil», SP - 1 ... SP
3
ROLA
ROLB
ROR
RORA
RORB
4
4
3 1 SP+l-SP,MIP-A
33 3 1 SP+l"'SP,MIP-B
PULl
ROL
7 1 AxB ... A:B
8A 2 2 9A 3 2 AA 4 2 BA 4 3
CA 2 2 DA 3 2 EA 4 2 FA 4 3
M
49
1
59
1 1
1
66 6 2 76 6 3
~
1
5&
1
Note) Condition Code Register will be explained in Note of Table 10,
eHITACHI
1
1
Al
•
C9f!
'
-
Ii I "
no!
'IiO
=1 Gf}fl II I "
IiO
1»7
I
I
I
I
I
I
I
I
I
"
•
R S
••
••
(~
(l)tlJ
~
t I
•
2 B6
3
t t
R S
R S
t
1 1 A -1-A
1 1 B-l-B
A@M ... A
2 7C
4 2
6
I
t t
t I
t t
t
M-l-M
3
I
t
I (ii
50
DECA
I
(j)~
OO-M-M
40
LDAB
Rotet. Rieht
1 1 A-A
1 1 8 -8
NEGA
NEG8
Load Doub..
Accumulator
Rotat. L.tt
1 1 A-8
3
I R
I
M-M
53
R
I
8-M
3
R
I
I
R S R R
A-M
11
2 73
t I
t t
I
I
I
I
I
I
R S R R
R S R R
1 OO-A
4 3
4 3
ceA
COM
COMA
COMB
NEG
EORB
Increment
2 2 91
2 2 01
I
I
I
I
I
R
B'M
OO-M
5 3
N Z V C
I
A·M
C....
5 2
I
, ,,
,·, ,
·,, ·· , ,
t t
t · t t ,
.
··..· ··
··.. , , ··
··..
···... , , ,
·· .· ,
·· .. , ,
···.·. , ,
·· .. ,
·• .• ,
·· .. ·
·· .. ·
··• .. ·•
··· ... · ·, ··
·· .. · • ••
·•• .•• ·•• ••• ·••• •••
·• .•
·• .•
I~
A:B+M:M+l-A:B
5 3
lB
3
5 4 3 2 1 0
t 00 •
t
t
@ •
I
I
I
I
I
I
I
R
I
R
@ •
R
(J) •
(J).
(J) •
R
R
t
• I{j)
R
I' I
R
I
I
I
I
I
,
I @ t
I @ I
I @II
I @I'
I (j) I
I (I) I
Ito be continued)
339
HD6303R,HD63A03R,HD63B03R----------------------Table 7 Accumulator, Memory Manipulation Instructions
Addre.inG Modes
Operltions
Mnemonic
IMMED
OP -
DIRECT
" OP
-
EXTEND
INDEX
" OP
Shift Left
Arithmetic
ASl
ASlA
ASlB
Doub/eShift
left. Arithmetic
ASlD
Shift Right
Arithmetic
ASR
ASRA
ASRB
67
Shift RiGht
lOOicel
lSR
lSRA
64
68
-
"
OP -
6 2 78
"OP
6 2 74
54
lSRD
Store
Accumulltor
STAA
STAB
97 3 2 A7 4 2 B7
07 3 2 E7 4 2 F7
Store Double
Accumulltor
Subtract
STD
DO 4 2
Double Subtract
Subtract
Accumulltors
Subtract
With Clrrv
And Immedilte
OR Imrnedilte
OlM
EDR lnimec!ilte
THt Immedilte
ElM
Test Zero or
Minus
TIM
A~IIIIIIIK;I
1
A .... M
3
4 3
B .... M
ED 5 2 FD 5 3
80 2 2 90 3 2 AO 4 2 80 4 3
CO 2 2 DO 3 2 EO 4 2 FO 4 3
83
3 3 93
4
2 A3 5 2 B3
_
, , ..,7
110
,,
, °i7 ACCAOAJI~~' eo~
4
5 3
10
SBA
SICA
S8CB
TA8
T8A
TST
TSTA
TSTI
AIM
Tren,fer
Accumulltors
04
_
, :J cg 1!Iii tn
M}
6 3
44
Double Shift
Right looicel
SUBA
SUBB
SUBD
1
M}
,
A-M
8 - M+'
A-M .... A
8 -M .... I
A:I-M:M+' .... A:8
1 A-I .... A
A-M-C-A
8-M-C .... I
16 1 1 A .... 8
17 1 1 8 .... A
M-OO
60 4 2 70 4 3
40
1 A -00
50 1 1 8 - 00
82 2 2 92 3 2 A2 4 2 82 4 3
C2 2 2 02 3 2 E2 4 2 F2 4 3
,
3
3
75 6 3 85 7 3
78 4 3 88 5 3
71
72
8 3 81
8 3 82
7
M·IMM .... M
7
M+IMM .... M
MIMM .... M
M·IMM
I N Z V C
•
•
•
•
•
•
••
••
57
6 3
lSf'B
,
H
47
58
06
2 77
-"
Condition Code
Regi,ter
5 4 3 2
0
•
1 , A '?1lllllllt-o •
110
1 , ..,7
•
, , 9"'IA7 mJ ~ • rJ-O •
•
,,
6 3
48
6
BooI..n'
Arithmetic Operltion
IMPLIED
·· ·
·• ·•
I
I
I
It> I
II!) I
I
I~
I~
I I
I I
I
R I
•
•
I
I
I
,
•
•, •
, (i).•
·• ·• , ,,, ··
••
,·
••
R
R
R
R
R
I
I
R
I
I
I
I
I
I
·· ··• •• • ••
••,,,
·• ·• ••
••
•
·•• ·• • •
•
• •I
I
I
I
I
I
I
·•
••
••
••
••
I I
I R
I R
R R
I R R
I R R
: :
% :
: t
: 1
R
•
•
R
R •
R •
Note) Condition Code' Register will be explained in Nota of Tabla 10.
• New Instructions
In addition to the H06801 Instruction Set, the HD6303R
has the following new instructions:
AIM----(M)· (IMM)-+(M)
Evaluates the AND of the immediate data and the
memory, places the result in the memory.
OIM---- (M) + (IMM) -+ (M)
Evaluates the OR of the immediate data and the
memory, places the result in the memory.
EIM----(M)(!) (IMM)-+ (M)
Evaluates the EOR of the immediate data and the
contents of memory, places the result in memory.
340
TIM----(M) • (IMM)
Evaluates the AND of the immediate data and the
memory, changes the flag of associated condition code
register
Each instruction has three bytes; the fust is op-code, the
second is immediate data, the third is address modifier.
XGDX--(ACCD) .. (IX)
Exchanges the contents of accumulator and the index
register.
'SLP----The MPU is brought to the sleep mode. For sleep
mode, see the "sleep mode" section.
eHITACHI
Table 8 Index Register, Stack Manipulation Instructions
Addressing Modes
Pointer Operation,
Mnemonic
IMMED.
OP
Compere Inde. Reg
CPX
Decrement Inde. Reg
DEX
Decrement Steck Pntr
Increment Inde. Reg
8C
-
#
DIRECT
OP
3 3 9C
-4
INDEX
-
EXTEND
IMPLIED
OP
OP
#
OP
2
AC 5 2 BC
#
-
#
5 3
-
Booleanl
Arithmetic Operation
'X-M:M+1
1 X-1 .... X
1
DES
34
1
INX
08
1
1 SP-1 .... sP
1 X + , .... X
Increment Stack Pntr
INS
31
1
1 sP+1 .... SP
Load Inete. Reg
Load Stack Pntr
LOX
CE
L-os--f&E
Store Inde. Reg
STX
Store Stack Pntr
STS
3 3 DE 4
3 3 9E 4
OF 4
9F
4
5 2 FE 5 3
2 EE
2 AE 5 2 BE
2 EF 5 2 FF
2 AF 5 2 BF
5
3
5
3
5
3
Inde. Reg .... Stack Pn_~ TXS
Steck Pntr .... Inde. Reg -T's-X---
M .... XH.IM+ 1) .... XL
M .... sPH.IM+1) .... sPL
X H .... M. XL .... 1M + 11
SPH .... M. SP L .... IM+ 11
X-1 .... sP
1 sP+ , .... X
35
1
1
30
1 B+X .... X
ABX
3A
1
1
PSHX
3C
5 1 XL .... M•• sP - 1 .... SP
Pull Data
PULX
3B
4 1 sP + , .... SP. M..... XH
Exchange
XGDX
18
2
Add
-Push
- Data
-----
XH .... M•• sP - 1 .... SP
sP+ 1 .... SP.M..... XL
1
5 4 3 2 1 0
H
#
09
--
Condition Code
Register
ACCD~IX
,, • ,
I N Z V C
•• t
• •
•
t
····· · ·• ··• ··••
··•• ·· · ,, ··•
····· ·• ·, •• ·•
···• ·• ·· • ··•
·• ·• • · · •
··
t
• (i) t
R
(])
(])
R
R
(])
R
••••••
Notel Condition Code Register will be explained in Note of Table 10.
Table 9 Jump, Branch Instruction
Addressing Modes
Operation,
Mnemonic
RELATIVE
Branch Always
BRA
Branch Never
BRN
Branch If Carry CI..r
BCC
OP - #
20 3 2
21 3 2
24 3 2
Branch If Carry Set
BCS
25
3 2
Branch If - Zero
BEQ
27
3 2
Branch If > Zero
Branch If > Zero
Branch If Higher
BGE
8GT
2C
2E
3
3
BHI
Branch If " Zero
Branch If L _ Or
Seme
BLE
22
2F
3
DIRECT
OP
#
-
INDEX
OP -
#
EXTEND
OP -
Branch Test
IMPLIED
#
# OP
-
None
None
c-o
C- 1
Z -1
N(f) V-O
Z + IN (f) VI- 0
2
2
--
3 2
2
C+Z-O
Z +-IN (f) VI- 1
f-- .
BLS
23
3 2
C+Z-1
BLT
20
N (f) V-1
Branch If Minus
BMI
2B
3 2
3 2
Branch If Not Equal
Zaro
BNE
26
3 2
Z·O
Branch If
< Zero
N -1
Branch If Oll8rflow
Clear
BVC
28 3 2
V-O
Branch If Oll8rflow Set
BVS
29
3 2
V-1
Branch If Plus
BPL
2A
3 2
N-O
Branch To Subroutine
8SR
80
5
2
3 2 7E
···•• ··• ·· ·•• ··
··• · · ·•• ·• ··
·• ··· ·····• ·· ··•
···• ·· · ·· ··
·····• ··· ··· ··• ··•
• • ·· · ·
···· •• •• ·• ••
• •••
··• ·••• •• ·•• ••• ·•••
·
Jump
JMP
Jump To Subroutln.
JSR
No ()peretlon
NOP
01
Retum From Interrupt
RT!
38 10 1
-(1)-
RTS
39
5 1
•• •• •
•S• • •
• (j) • • • •
R.tum From
Subroutine
Softwere Interrupt
6E
Condition Code
Regi'ter
5 4 3 2 1 0
H I N Z V C
3 3
90 5 2 AD 5 2 BD 6 3
1 1
SWI
3F 12 1
Weit for InterruPt-
WAI
SMO
SLP
3E 9
1A 4
Advances Prog. Cntr.
Only
1
1
Notel ·WAI putl R/W high; Address Bus goes to FFFF; Data Bus goes to the three state.
Condition Code Register will be explained in Note of Table 10.
eHITACHI
••••••
··
••••••
341
HD6303R,HD63A03R,HD63B03R----------------------Table 10 Condition Code Register Manipulation Instructions
Condition Code Regiller
I
0
4
3
2
Z
V
H
I
N
C
R
Add,euintMocles
C..... Car,y
-
ClC
Cli
ClV
SEC
SEI
SEV
TAP
TPA
Cle.. Intl"upt Mesk
CIM,Ow,fl_
Set c.r,y
$It Inte,rupt Me,k
Sat Ow,flow
Accumullto, A .... CCR
CCR .... Accumuleto' A
5
800lean Ope,at,on
IMPLIED
OP
1
1
OC
1
OE
1
1
OA
oq 1 1
1
OF
t
1
08
t
1
1
06
1
1
07
Mnemonic
()pt'ltion,
•
,
•
··· · ··· ··· ·· ··
··· ·· ··· ··· ·· ·•
···· ··
O .... C
0-1
R
---
R
0"" V
1 -C
1 .... 1
I .... V
A .... CCR
CeR-A
S
5
5
----
It
---
[NOTE 11 Condition Code
(1)
(Bit V)
~
(Bit C)
~)
(Bit C)
@
(Bit V)
@
(Bit V)
@
(Bit V)
(j)
(Bit N)
@
(All Bit)
c§)
(Bit I)
Register Notes: (Bit set if test is true and cleared otherwise)
Test: Result = 10000000?
Test: Result, OOOOOOOO?
Test: BCD Character of high-order byte greater than 9? (Not cleared if previously setl
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
Test: Set equal to NeC=1 after the execution of instructions
Test: Result less than zero? (Bit 15=1)
load Condition Code Register from Stack.
Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exit the wait
state.
(All Bitl Set according to the contents of Accumulator A.
Result of Multiplication Bit 7= 1 of ACCB?
(Bit C)
[NOTE 21 Cli instruction and interrupt.
If interrupt mask-bit is set 0="1") and interrupt is requested (TAO;' = "a" or iFiQ; = "0"),
and then CLI instruction is executed, the CPU responds as follows.
The next instruction of CLI is one-machine cycle instruction.
Subsequent two instructions are executed before the interrupt is responded.
That is, the next and the next of the next instruction are executed.
~ The _next instruction of Cli is two-machine cycle (or more) instruction.
Only the next instruction is executed and then the CPU jump to the interrupt rou~ine.
Even if TAP instruction is used, instead of CLI, the same thing occurs.
CD
Table 11 OP-Code Map
OP
ACC
ACC
CODE
A
8
0100
4
0101
5
~
0000
0
0001
2
0011
3
O~
I NOP
SIA
8RA
TSX
CIA
BRN
INS
2 ~
S ~
/"'"
/"'"
BHI
PULA
BLS
PULB
4 LSRD
5 ASLD
6 TAP
01" 7 TPA
1000 8 INX
1001 9 -DEX
1010 A CLV
1011 B SEV
1100 C CLC
1101 D SEC
"1O E CLI
1111 F SEI
0
.,/
BeC
DES
LO
0000
0001
0010
0011
0100
0101
0110
I
......-
0010
BCS
TXS
TAB
BNE
PSHA
TIA
BEQ
PSHB
XGDX BVC
PULX
OM
BVS
RTS
SLP
BPL
ABX
AlA
BMI
~ BGE
RTI
PSHX
......-
ILT
MUL
/"'"
BGT
WAI
~ BLE
I
2
SWI
S
----
INO
0110
1%
6
IMM
0111
7
1000
8
I
I
I
1001
9
I
I
I
INO
1010
A
J EXT
I
I
---
COM
----
IMM
1011
1100
B
C
T OIR I
I 1101 I
I o I
INO
I
EXT
1110] 1111
F
E
I
0
SU8
AIM
CMP
I
OIM
SBC
2
ADDD
SUBD
3
4
5
6
7
8
ANO
LSR
BIT
ElM
LOA
ROR
~I
ASR
............... l
STA
STA
ASL
EOR
ROL
AOC
9
DEC
ORA
A
TIM
ADD
TST
BSR
I
$
~
..............7
8
HITACHI
I
STD
~
STS
9
I
C
D
E
F
LOX
LOS
CLR
8
LOD
JSR
JMP
..............................
5
B
CPX
INC
UNDEFINED OP CODE ~
• Only for instructions of AIM, OIM, ElM, TIM
342
DIR
NEG
~
4
ACC8 or X
A.CCA or SP
DIR
A
I
B
C
I
STX
D
]
E
]
F
~~~~~~~~~~~~~~~~~~~~~~~HD6303R,HD63A03R,HD63B03R
•
Instruction Execution Cycles
In the HMCS6800 series, the execution cycle of each instruction is the number of cycles between the start of the current
instruction fetch and just before the start of the subsequent
instruction fetch.
The HD6303R uses a mechanism of the pipeline control
for the instruction fetch and the subsequent instruction fetch
is performed during the current instruction being executed.
Therefore, the method to count instruction cycles used in
the HMCS6800 series cannot be applied to the instruction
cycles such as MULT, PULL, DAA and XGDX in the HD6303R.
Table 12 provides the information about the rela!!onship
among each data on the Address Bus, Data Bus, and R/W status
in cycle-by-cycle basis during the execution of each instruction.
Table 12 Cycle-by-Cycle Operation
Address Mode &
Instructions
IMMEDIATE
ADD
ADC
BIT
AND
CMP
EOR
ORA
LOA
SBC
SUB
ADDD --CP)C
LDD
LOX
DIRECT
ADC
AND
CMP
1
2
--
--~
---r-
---
3
!
I'
Ii
I
3
Op Code Address+'
Op Code Address+2
Op Code Address+3
Op Code Address+'
Address of Operand
Op Code Address+2
2
3
,. ~
3
2
3
-AODO-----tpX-- -----LOS
SUBD
,
4
-op Code Add,ess+'--
2
3
4
4
- JS-R- - -------- - - - -
[
5
---tlrvC------------ ---4
I
Address of Operand
Address of Operand +'
Op Code Address+2
Op Code Address+'
2
Destination Address
3
Destination Address + ,
4
Op Code Address + 2
- , - ~ode Address+,
2
FFFF
3
Stack Pointer
4
Stack Pointer-,
5
Jump Address
Op Code Address+ 1
1---,--2
3
4
-ATfl.1--ETrVf---I---I----1
OIM
6
2
3
4
5
6
---,,
1--
,
,
,
1
-
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
I Address of Operand (LSB)
Operand Data
Next Op Code
--L,_I
1
Destination Add,es,
Destination Address
0
Accumulator Data
Op Code Address+2
~ Next Op Code
Op Code Address+ ,-----c---;
I Adcfress of Operand (LSBj-
--Sfo---sTS --- -- --- ----r---,-STX
Operand Data
Next Op Code
1
~--~---~------
2
3
~ ~~f--~ ~~~ ..~ ---LDD
LOX
,
Op Code Address+ 1
Op Code Address+2
2
LOS
SUBD
ADD
BIT
EOR
Data Bus
Address Bus
,
,
,
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
C
Destination Address (LSB)
0
Register Data (MSB)
0
Register Data (LSB)
,
Next Op Code
' . Jump Ad-;-d:-r-es-s--c('"O"L--;;;SC;;;:B:-)- - ,
Restart Address (LSB)
,0
Return Address (LSB)
11 0
Return Address (MSB)
,
I First Subroutine Op Code
--,
Immediate Data
i
Op Code Address+2
,
I Address of Operand (LSB)
i
1 I Operand Data
Address of Operand
Op Code Address + 3
,
I
Next Op Code
1-- Op Code Address+ 1 - - - - , - - -Immediate Data ~-~---Op Code Address+2
Address of Operand
-FFFF
Address of Operand
Op Code Address+3
,
,
,
0
,
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
- Continued -
eHITACHI
343
Table 12 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
INDEXED
JMP
ADC
AND
CMP
LDA
SBC
TST
STA
1
ADD
BIT
EOR
ORA
SUB
2
3
4
4
4
I
AOOO-------CPX
LOS
SUBD
Op Code Address + 1
1
Offset
FFFF
1
Restart Address (LSB)
Jump Address
_____1::-_--+--::;F:-:;irs::;-t_o...:...p_C_od_e_o_f_J__u_m_-'-p_R__ou_tin_e_
Op Code Address + 1
1
Offset
FFFF
1
Restart Address (LSB)
IX + Offset
1
Operand Data
Op Code Address+2
1
Next Op Code
1
2
3
3
LDD
LOX
5
1
2
3
4
1
2
3
4
Op Code Address + 1
--f-- 1
FFFF
1
IX+Offset
0
Op Code Address + 2
1
Op Code Address+ 1
1
FFFF
1
IX + Offset
1
IX + Offset+ 1
1
Op Code_Address+~ ____ ~_
Op Code Address+ 1
1
FFFF
1
IX + Offset
0
IX + Offset + 1
0
5
- -oS=T=D,.--------::S=T=S,.------
1
2
3
4
STX
5
Data Bus
-JSR-----[---+--}--- -g~ ~~:: ~~~::: ~}-------0~1
I
1
2
3
4
5
I
ASR
DEC
LSR
ROL
I
I
6
1
2
3
4
5
6
I
-----
I
I
2
3
4
5
AIM
OIM
ElM
7
1
2
3
4
5
6
7
Op Code Address + 1
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address+ 1
Op Code Address+1
Op Code Address+2
FFFF
IX + Offset
Op Code Address + 3
Op Code Address + 1
I
1
2
5
3
4
5
------,;;C';-L-;;;cR--------+------ - - 1 TIM
5
0
~~::tOP
Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
_~-f--~±Offset---------- 1
-----;--..-;-----co-==----t---
ASL
COM
INC
NEG
ROR
FFFF
Stack Pointer
Stack Pointer-1
Offset
Restart Address (LSB)
Accumulator Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
____________ _
Offset
Restart Address (LSB)
Register Data (MSB)
Register Data (LSB)
I
I
FFFF
IX + Offset
IX + Offset
Op Code Address+2
Op Code Address+ 1
Op Code Address+2
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address+3
First Subroutine Op Code
1
Offset
----1
Restart Address (LSB)
1 I Operand Data
1
Restart Address (LSB)
0
New Operand Data
1
Next Op Code
----'Immediate Data
1
Offset
1
Restart Address (LSB)
1
Operand Data
1
Next Op Code
1
Offset
--1
1
0
1
1
1
1
1
1
-0
1
Restart Address (LSB)
Operand Data
00
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
- Continued -
344
$
HITACHI
Table 12 Cy.cle-by-Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
EXTEND
JMP
1
I
2
3
I
--,'-
3
-ADC-ADD-rsrT ACNMDp
BEOITR
4
!
I
2
3
4
I
'I
Data Bus
Op Code Address + 1
,1
Op Code Address+2
!
1 I
Jump Address
1
Op Code Address+,-----r---,-r
I
Op Code Address+2
Address of Operand
Op Code Address+3
1 ! Address of Operand (LSB)
I Operand Data
1
Next Op Code
LOA
ORA
I
i
SUB
:
I
I
:
SBC
- STA-----------r----t---'--Top Code AddressIT----~---i
I
Jump Address (MSB)
Jump Address (LSB)
Next Op Code
Address of Operan(f(~rSBr-
i
Destination Address (rinSB)
2
! Op Code Address+2
1
Destination Address (LSB)
I 4
3
Destination Address
0
Accumulator Data
:
: 4
I Op Code Address +3
Next Op Code
-r---t-,-t--op CodeAdCfress+ 1 - - . - -------Aijcfress of Operand (MSSf
2
! Op Code Address+2
Address of Operand (LSB)
5
3
I Address of Operand
Operand Data (MSB)
4
I Address of Operand + 1
1
Operand Data (LSB)
I
.
i
ADDD
CPX
LOS'
SUBD
STD
STX
I
LDD
LOX
-'------r-}---~g~-~~~: :~~*~~~------; - }- -~--~:::i~!i~~~dreSS(MSBr
I
STS
2
3
5
4
5
-f -
J5R
: Op Code Address+2
Destination Address
Destination Address+ 1
Op Code Address+3
top CodeAddress+ 1 - - -
1
I
>--
2
3
i
ASL
COM
INC
NEG
ROR
CLR
ASR
DEC
LSR
ROL
-j---
I
I
I
I
----------.1.
I
I
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
1 ----Jump Address(~.,rS-Br
0
0
Op Code Address+2
FFFF
6
I
4
Stack Pointer
.
'5
Stack Pointer-1
i
I
6
Jump Address
!
-r --1-- - Op Code Address + 1
!
2
Op Code Address+2
i
I 3
Address of Operand
:
6
I
4
FFFF
I
5
Address of Operand
I
6
Op Code Address+3
- - - , - -Op-Code Address+ 1 - - - I.•
i 2
Op Code Address+2
i
I
3
I Address of Operand
!
5
, Address of Operand
OJ) Code Address+3
1
1
0
0
-r --,-1
t
r
i
"
1
1
1
0
1
Jump Address (LSB)
! Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Fi;rst Subroutine Op Code
Address ofOperand (MSB)Address of Operand (LSB)
,Operand Data
i Restart Address (LSB)
I New Operand Data
! Next Op Code
Address of Operand (MSB)
I Address of Operand (LSB)
'Operand Data
00
Next Op Code
i
I
n :
--l-i
-
1
1
0
1
- Continued -
_HITACHI
345
HD6303R,HD63A03R,HD63B03R----------------------
Table 12 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions
IMPLIED
ABA
ASL
ASR
CLC
CLR
COM
DES
INC
INX
LSRD
ROR
SBA
SEI
TAB
TBA
TST
Address Bus
ABX
ASLD
CBA
CLI
CLV
DEC
DEX
INS
LSR
ROL
NOP
SEC
SEV
TAP
TPA
TSX
Op Code Address+ 1
I
i
2
I
-POIA-PULEf---r--;-
T
0" Code-Adcrress + 1 --~T-T--+-NextOP Code----------
2
FFFF
I
I
4
I
3
I
2
3
---L- 4
I
I
4
i
l
___._ .___ ._______ .._
PSHX
:.
I
I
5
II
5
I
I
I
1
0
1
FFFF
Stack Pointer + 1
1_ Stack Pointer + 2
Op Code Address+ 1
2
FFFF
3
I Stack Pointer
4 , Stack Pointer-1
5
Op Code Address + 1
Op Code Address+-1
2
FFFF
3
Stack Pointer + 1
4
Stack Pointer+2
7
6
7
346
'Restart Address (LSB)
~::t~~PA~~~:SS~~-~)----
Data from Stack
Next Op Code
Restart Address (LSB)
Accumulator Data
Next Op Code
Next Op Code --------------
Restart Address (LSB)
Data from Stack (MSB)
--~-L Data from Stack (LSB)
i
1 I Next Op Code
1 I Restart Address (LSB)
:,
0
,Index Register (LSB)
!
0 _~Index Register (MSB)
: 1
Next Op Code
Next Op Code
I
1 I Restart Address (LSB)
I
1
Return Address (MSB)
!
1
Return Address (LSB)
L,
i
----r-,-
MUC-~-----t----I}-- ~~t~:d~d:~~~:ss+ 1
2
3
4
5
1
t---,-
I
----if
r
RTS~~-~-
2
3
4
i
1--['
-,
'
+--------r--rI
1
~
Stack Pointer + 1
Op Code Address + 1
FFFF
Stack Pointer
Op Code Address + 1
Op Code Address +
I
-PUCX------~
!
~:F~ode Address + 1
2
t-~+-ii
PSHB
Next Op Code
I
-- 6~!------xGDx-t ----+-,
PSHA
Data Bus
II
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
eHITACHI
!~
I
+1 ~:~~6~~d:d~ Return R~ir1~
Restart
Restart
Restart
Restart
Restart
Restart
Address (LSB)
Address (LSB)
Address (LSB)
Address (LSB)
Address (LSB)
Address (LSB)
- Continued -
---.....--------------------HD6303R,HD63A03R,HD63B03R
Table 12 Cycle-by·Cycle Operation (Continued)
Address Mode 8t
Instructions
Address Bus
IMPLIED
-WAI
1
2
3
4
9
RTI
~
3
4
5
6
10
7
8
9
10
1
2
3
4
5
6
SWI
I
12
I
I
I
7
8
9
10
11
12
SlP
I
4
~
5J.P
!
i
I
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer-4
Stack Pointer-5
Stack Pointer - 6
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer + 1
Stack Pointer+2
Stack Pointer + 3
Stack Pointer+4
Stack Pointer + 5
Stack Pointer + 6
Return Address
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Vector Address FFFA
Vector Address FFFB
Address of SWI Routine
Op Code Address + 1
FFFF
FFFF
Data Bus
1
1
0
0
0
0
0
t-~~
I
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
Next Op Code
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
Index Register (lSB)
Index Register (MSB)
Accumulator. A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address (lSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index Register (lSB)
Return Address (MSB)
Return Address (lSB)
First Op Code of Return _~utine
Next Op Code
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
Index Register (lSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)
Address of SWI Routine (lSB)
First Op Code of SWI Routine
Next Op Code
Restart Address (lSB)
High Impedance· Non MPX Mode
Address Bus -MPX Mode
I
I
FFFF
Op Code Address+ 1
1
Restart Address (lSB)
Next Op Code
- Continued -
eHITACHI
347
Table 12 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
RELATIVE
BCC
BCS
BEQ
BGE
3
I
BGT
BHI
BlE
BlS
BlT
BMT
BNE
BPl
BRA
BRN
BVC
BVS
- B S R - - - - - f-----
5
Data Bus
1
Op Code Address + 1
!
2
FFFF
I
3
{ Branch Address· .... ·Test="'"
Op Code Address+ ''''Test="O''
I
1
1
1
Branch Offset
Restart Address (lSB)
First Op Code of Branch Routine
Next Op Code
I
~
1
Op Code Address + 1
2
FFFF
3
Stack Pointer
Stack Pointer-1
Branch Address
4
5
• LOW POWER CONSUMPTION MODE
1
1
0
0
1
Offset
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
First Op Code of Subroutine
The HD6303R has two low power consumption modes; sleep
and standby mode .
This sleep mode is available to reduce an average power
consumption in the applications of the HD6303R which may
not be always running.
• SleepMocle
•
On execution of SLP instruction, the MPU is brought to the
sleep mode. In the sleep mode, the CPU sleeps (the CPU clock
becomes inactive), but the contents of the registers in the CPU
are retained. In this mode, the peripherals of CPU will remain
active. So the operations such as transmit and receive of the
SCI data and counter may keep in operation. In this mode,
the power consumption is reduced to about 1/6 the value of a
normal operation.
The escape from this mode can be done by interrupt, RES,
S'fIlY. The RES resets the MPU and the STBY brings it into the
standby mode (This will be mentioned later). When interrupt is
requested to the CPU and accepted, the sleep mode is released,
then the CPU is brought in the operation mode and jumps to
the interrupt routine. When the CPU has masked the interrupt,
after recovering from the sleep mode, the next instruction of
SLP starts to execute. However, in such a case that the timer
interrupt is inhibited on the timer side, the sleep mode cannot
be released due to the absence of the interrupt request to the
CPU.
Bringing "STBY "Low", the CPU becomes reset and all
clocks of the HD6303R become inactive. It goes into the
standby mode. This mode remarkably reduces the power consumptions of the HD6303R.
In the standby mode, if the HD6303R is continuously supplied with power, the contents of RAM is retained. The standby
mode should escape by the reset start. The foUowina is the
typical application of this mode.
First, NMi routine stacks the CPU's internal information and
the contents of SP in RAM, disables RAME bit of RAM control
register, sets the standby bit, and then goes into the standby
mode. If the standby bit keeps set on reset start, it means that
the power has been kept during stand-by mode and the contents
of RAM is normally guaranteed. The system recovery may be
possible by returning SP and bringing into the condition before
the standby mode has started. The timing relation for each line
in this application is shown in Figure 2l.
Vee
INMII
Standby,..
\~
iiMi
HD6303R
I
,RES
II
STiv
I
2STBY~~
I
I--of
\ Stack registers
, RAM control
register set
I
I
~
~~jlll~~~~ I
time
~
restart
Figure 21. Standby Mode Timing
348
_HITACHI
-----------------------HD6303R,HD63A03R,HD63B03R
• ERROR PROCESSING
When the HD6303R fetches an undefmed instruction or
fetches an instruction from unusable memory area, it generates
the highest priority internal interrupt, that may protect from
system upset due to noise or a program error.
• Op-Code Error
Fetching an undefmed op-code, the HD6303R will stack the
CPU register as in the case of a normal interrupt and vector to
the TRAP (SFFEE. SFFEF). that has a second highest priority
(RB is the highest).
• AcId,... Error
When an instruction is fetched from other than a resident
RAM, or an external memory area, the CPU starts the same
interrupt as op-code error. In the case which the instruction is
fetched from external memory area and that area is not usable,
the address error can not be detected.
The address which cause address error are shown in Table
13.
This feature is applicable only to the instruction fetch. not to
normal read/write of data acceuinJ.
Transitions among the active mode, sleep mode. standby
mode and reset are shown in Figure 22.
Figures 23, 24 show a system configuration.
The system flow chart of HD6303R is shown in Figure 25.
Figure 22
Transitions among Active Mode, Standby Mode,
Sleep Mode, and Reset
Table 13 Address Error
Address Error
$0000 - $001 F
HD6303R MPU
1e
Address Bus
Olla Bus
Address Bus
Figure 23 HD6303R MPU Multiplexed Mode
8
011. Bus
Figure 24 HD6303R MPU Non-Multiplexed Mode
eHITACHI
349
HD6303R,HD63A03R,HD63B03R----------------------
PCL~MSP
PCH
~MSP-l
IXL
-~MSP-2
IXH
~MSP-3
ACCA·MSp·4
ACCB ·MSp·5
CCR ··MSP-6
A
Figure 25 HD6303R System Flow Chart
350
eHITACHI
• PRECAUTION TO THE BOARD DESIGN OF OSCILLATION CIRCUIT
As shown in Fig. 26, there is a case that the cross talk disturbs the normal oscillation if signal lines are put near the
oscillation circuit. When designing a board, pay attention to
this. Crystal and CL must be put as near the HD6303R as
possible.
~ ~
OJ
c:
OJ
c:
'" iii'"
iii
CL
• PIN CONDITIONS AT SLEEP AND STANDBY STATE
• Sleep State
The conditions of power supply pins, clock pins, input pins
and E clock pin are the same as those of operation. Refer to
Table 14 for the other pin conditions.
• Standby State
Only power supply pins and STBY are active. As for the
clock pin EXTAL, its input is fixed internally so the MPU is
not influenced by the pin conditions. XTAL is in "}" output.
All the other pins are in high impedance.
;
~ ~-..--''-O
XTAL
~~~~~EXTAL
mCL
HD6303R
Do not use this kind of print board design.
Figure 26
Precaution to the boad design
of oscillation circuit
Table 14 Pin Condition in Sleep State
~
Pin
P20"" P24
AO/PIO A,/P17
As - AlS
Condition
Function
Condition
Function
Condition
Function
Condition
Function
Do/Ao D7/A7
R/W
-
Function
Condition
Multiplexed Mode
Non Multiplexed Mode
I/O Port
Keep the condition just before sleep
--....-Address Bus (Ao-A,)
Output "1"
Address Bus (As -A 1S )
Output "1"
Data Bus (Do -0 7)
High Impedance
RM Signal
Output "1"
I/O Port
-
I/O Port
Keep the condition just before sleep
Address Bus (As -Au)
-
E: Address Bus (Ao -A 7), E: Data Bus
E: Output "1", E: High Impedance
RIW Signal
-
-
AS
-
Output AS
Table 15 Pin Condition during RESET
~
Pin
Non-Multiplexed Mode
Multiplexed Mode
P20 '" P24
High Impedance
..
AO/PIO '" A7/P17
High Impedance
..
As'" Au
High Impedance
..
Do/Ao '" D7/A,
High Impedance
R!W
"1" Output
..
E-: "1" Output
..
AS
E : "0" Output
_HITACHI
E : "1" Output
E : High Impedance
351
HD6303R,HD63A03R,HD63B03R----------------------•
Table 16 Difference between HD6303 and HD6303R
DIFFERENCE BETWEEN HD6303 AND HD6303R
The 806303R is an upgraded version of the 806303. The
difference between H06303 and HD6303R is shown in Table
16.
Item
$
HD6303R
Mode 2: Multiplexed
Mode
(Equivalent to Mode 4)
The electrical characterElectrical
istics of 2MHz version
Character(B version) are not specistics
ified.
Some characteristics
are improved.
The 2MHz version is
guaranteed.
Timer
352
HD6303
Operating
Mode 2: Not defined
Mode
HITACHI
Has problem in output
compare function.
(Can be avoided by software.)
The problem is solved.
HD6303X, H D63A03X,
HD63B03X
CMOS MPU (Micro Processing
Unit)
-PRELIMINARY-
The HD6303X is a CMOS 8·bit microprocessing unit (MPU)
which includes a CPU compatible with the HD630IVl, 192
bytes of RAM, 24 parallel I/O pins, a Serial Communication
Interface (SCI) and two timers on chip.
HD6303XP, HD63A03XP,
HD63B03XP
• FEATURES
•
•
Instruction Set Compatible with the HD6301V1
Abundant On-chip Functions
192 Bytes of RAM
24 Parallel 1/0 Ports
l6·Bit Programmable Timer
8-Bit Reloadable Timer
Serial Communication Interface
Memory Ready
Halt
Error·Detection (Address Trap, Op Code Trap)
• Interrupts ••. 3 External, 7 Internal
Up to 65k Words Address Space
• Low Power Dissipation Mode
Sleep
Standby
• Wide Range of Operation
Vee 3 - 6V (f 0.1 - 0.5MHz).
f =0.5 -1.0MHz; HD6303X )
Vee· 5V±10%( f 0.5 -1.5MHz; HD63A03X
f 0.5 - 2.0MHz; HD63B03X
(DP-64S)
HD6303XF, HD63A03XF,
HD63B03XF
.0
=
=
=
=
(FP..sO)
• PIN ARRANGEMENT
•
HD6303XP, HD63A03XP, HD63B03XP
V.
to
XTAL
EXTAL 3
1m'
MI'.
R/'R
MI',
\Wf
IJII'
m
BA
o.
'i'fI'l
mii
0,
0,
0,
D.
.... I
1'..
1'"
Pn
1
1',.
D.
D,
1'"
1'"
1'"
1'"
1'..
Pit
Pit
1'"
I'll
I D.
A.
A,
A,
A,
A.
A,
A,
A,
t
I
Vu
1'"
1'"
....
1'"
1'"
1'..
1'..
po.
1'..
• HD6303XF, HD63A03XF, HD63B03XF
E
I A•
A.
A,.
All
All
An
A ..
All
1
Vee
1'"
(Top View)
(Top View)
$
HITACHI
353
HD6303X,HD63A03X,HD63B03X----------------------_ _
• BLOCK DIAGRAM
vc c - Vss
Vss
oa:
NO
P2o(Tin)
P21(Tout1)
0..
0
I~
a:
0
~
P22(SCLK)
00
.2:.-
N
P23(Rx)
P24(Tx)
rDl
..J
~
X
J J
ii 11 I
II
~I~ I~I~~
..J
~
X
w
O'6,aa:l~
a:a:a::E:x:
CPU
~
~
~
cf
P2s(Tout2)
A
P26(Tout3)
P27(TCLK)
'II
R/W
llR
SA
r--
...
~
£
~
.....
L--
'\
A
Qj
E
~
i=
I"
:J
m I--In
:J
m I---
!!!
10
0
A
U
I..-
V
r-v
r.n
r---
... r--
III
:l
-
Qj
V
E
.=
A
r--
In
m
III
:l
II)
Pso(iRIT11)
III
III
PS1(TFm2i
2)
PS2(M R)
-0
'C
<
I"
E
'0
«
Q)
t--
r--
...
0
PS4
I---
"'--
1.0
PS3(RAIT
ALT)
Q)
0..
~
t--
t--
:J
m t--
PS5
In
PSS
:J
m
PS7
-'"
l..-
J
I"
A
Pso -
V
PS1-
a:0
PS2 -
P SS -
'0
:J
~
r---
PS4-
t--
0
m
'\
P63 -
:J
In
£
16
r----
r-r-r--
."
II)
N
r--
I--t----
~
~
~
--
I--
"--
10
0
cf
10
1\'4
J
cf
RAM
192 Bytes
P 6S P S7 -
354
RD
' - - - WR
$
HITACHI
r--
>---
e r-=
'0
'0
t--
« r-""'"--
------------------------HD6303X,HD63A03X,HD63B03X
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Supply Voltage
Vee
-0.3 - +7.0
V
Input Voltage
Yin
V
Operating Temperature
Topr
-0.3 - Vee+0.3
0-+70
Storage Temperature
Tstg
-55 - +150
°c
°c
(NOTE) This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection
circuits. To assure the normal operation, we recommend Vln , Vout : VSS ~ (Vin or Vout ) ~ Vee.
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vee" 5.OV±10%, Vss" OV, Ta - O-+70°C, unless otherwise noted.)
Item
Test Condition
Symbol
RES, STBY
Input "High" Voltage
EXTAL
V IH
I nput Leakage Current
Three State (off·state)
Leakage Current
Output "High" Voltage
All Inputs
NMI, RES, STBY,
MP o , MP 1 , Port 5
Ao-A 1s , 0 0 -0 7 , RD,
WR, R/IN ,Port 2,Port 6
All Outputs
typ
-
Vee xO .7
2.0
Other Inputs
Input "Low" Voltage
min
Vee- 0 .5
V IL
V
0.8
V
lIinl
Yin = 0.5-V ee -0.5V
-
-
1.0
IJA
IITsl1
Yin = 0.5-V ee -0.5V
-
-
1.0
IJA
V OH
IOH = -200IJA
2.4
IOH = -10IJA
Vee-0 .7
All Outputs
VOL
IOL -= 1.6mA
-
Ports 2, 6
-IOH
Vout = 1.5V
1.0
Input Capacitance
All Inputs
C in
Yin = OV, f
Ta = 25°C
Standby Current
Non Operation
ISTB
Current Dissipation*
Icc
= 1MHz,
-
V
-
V
0.4
V
10.0
mA
-
-
12.5
pF
-
3.0
15.0
IJA
1.5
;3.0
mA
2.3
4.5
mA
Sleeping (f = 2MHz**)
-
3.0
6.0
mA
Operating (f = 1MHz**)
-
7.0
10.0
mA
Operating (f = 1.5MHz**)
-
10.5
15.0
mA
14.0
20.0
mA
2.0
-
-
V
Sleeping (f
ISLP
= 1MHz**)
Sleeping (f = '1.5MHz**)
Operating (f = 2MHz**)
V RAM
=
Vee
+0.3
-
Darlington Drive
Current
• V IH min = Vee-1,OV, VIL max
-
Unit
-0.3
Output "Low" Voltage
RAM Standby Voltage
-
max
O.8V , All output terminals are at no load .
•• Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max.
values about Current Dissipations at x MHz operation are decided according to the following formula;
typo value (f = x MHz) = typo value (f = 1MHz) x x
max. value (f = x MHz) = max. value (f = 1MHz) x x
(both the sleeping and operating)
$
HITACHI
355
HD6303X,HD63A03X,HD63B03X-----------------------•
AC CHARACTERISTICS (Vee" 5.0V±10%, Vss· OV, Ta· O-+70°C, unlen otherwise noted.)
BUS TIMING
Item
Symbol
Test
Condition
typ
max
min
typ
-
10
0.666
-
25
-
25
-
-
Cycle Time
tCYc
1
Enable Rise Time
tEr
E;nable Fall Time
tEf
-
Enable Pulse Width "High" Level·
PWEH
450
Enable Pulse Width "Low" Level·
PWEL
450
Address, R/W Delay Time·
Data Delay Time
Write
Data Set-up Time
Read
tAD
I
I
-
toow
tOSA
80
Fig. 1
80
I
tAH
tHW
80
I
tHA
0
Address, RM Hold Time·
Write·
Data Hold Time
Read
RD, WR Pulse Width·
PWAW
450
RD, WR Delay Time
tAWO
A'l), WIf Hold Time
tHAW
OR Delay Time
tOLA
-
LI R Hold Time
tHLA
10
MR Set·up Time·
tSMA
400
MR Hold Time·
tHMA
E Clock Pulse Width at MR
PWEMA
Processor Control Set-up Time
tpcs
-
Fig. 2
Fig. 3,
10 11
200
Processor Control Rise Time
tpcr
Processor Control Fall Time
tPCf
BA Delay Time
tBA
Fig. 3
-
Oscillator Stabilization Time
tAC
Fig. 11
20
Reset Pulse Width
PWAST
Fig. 2,3
HD63A03X
HD6303X
min
3
250
200
40
30
200
-
300
300
70
50
50
0
300
10
280
9
-
-
200
100
-
90
100
250
-
20
3
HD63B03X
Unit
max
min
ty!'>
10
0.5
-
10
25
-
-
25
ns
25
ns
-
ns
160
ns
120
ns
-
ns
25
-
220
190
-
160
-
220
70
35
40
0
220
160
-
-
10
-
230
40
30
40
-
9
-
-
-
200
-
100
-
100
190
-
20
3
max
I.ls
ns
ns
ns
ns
ns
40
ns
25
ns
120
ns
-
ns
ns
0
ns
9
I.ls
-
ns
100
ns
100
ns
160
ns
-
tCYC
ms
* These timings change in approximate proportion to tcyc. The figures in this characteristics represent those when tcyc is minimum
(. in the highest speed operation).
PERIPHERAL PORT TIMING
Item
Symbol
HD6303X
HD63A03X
HD63B03X
Test
Condition
min
typ
max
min
typ
max
min
typ
max
Unit
Peripheral Data
Set·upTime
Ports 2, 5, 6
tposu
Fig. 5
200
-
-
200
-
-
200
-
-
ns
Peripheral Data
Hold Time
Ports 2,5,6
I
tpOH
Fig. 5
200
-
-
200
-
-
200
-
-
ns
tpwo
Fig. 6
-
-
300
-
-
300
-
-
300
ns
DeIaV T;me (Enabl.
Negative Transition to
Peripheral Data Valid)
356
Ports 2, 6
_HITACHI
------------------------HD6303X,HD63A03X,HD63B03X
TIMER SCI TIMING
Item
Timer 1 Input Pulse Width
Delay Time (Enable Positive
Transition to Timer Output)
SCI Input
Clock Cycle
I
I
Symbol
tPWT
tTOD
Async. Mode
Clock Sync.
tSCYC
HD63A03X
HD6303X
HD63B03X
Test
Condition
min
tyJl_
max
min
t'lP
max
min
tYQ
max
Fig.8
2.0
-
-
2.0
-
-
2.0
-
-
tCyc
400
ns
Unit
Fig. 7
-
-
400
-
-
400
-
Fig.8
1.0
-
Fig. 4. 8
2.0
-
-
1.0
2.0
-
2.0
-
-
200
-
-
200
-
-
200
ns
290
-
-
290
-
-
290
-
-
ns
1.0
-
tCYC
tcyc
SCI Transmit Data Delay
Time (Clock Sync. Mode)
tTXD
SCI Receive Data Set-up
Time (Clock Sync. Mode)
tSRx
SCI Receive Data Hold Time
(Clock Sync. Mode)
tHRX
100
-
-
100
-
-
100
-
-
ns
SCI Input Clock Pulse Width
tpwSCK
0.4
0.6
0.4
0.4
-
0.6
tscyC
ttcvc
2.0
2.0
-
-
t cvc
tpwTCK
200
200
-
2.0'
Timer 2 Input Clock Pulse
Width
-
-
0.6
Timer 2 Input Clock Cycle
-
200
-
-
ns
Timer 1·2. SCI Input Clock
Rise Time
tCKr
-
-
100
-
-
100
-
-
100
ns
Timer 1·2. SCI Input Clock
Fall Time
tCKf
-
-
100
-
-
100
-
-
100
ns
Fig.4
Fig.8
~HITACHI
357
HD6303X,HD63A03X,HD63B03X----------------------1-----------tCyC-----------"I
E
t------PWEL---........
!-----PW£H----o-4
t£,
2.4V
O.BV
MPU Write
00-07
MPU Read
00-07
Figure 1 Bus Timing
t - - - - - - P W £ M R - - - - -........
\
E
\
\
'-----
-t---+--tHMR
MR
Figure 2 Memory Ready and E Clock Timing
358
_HITACHI
O.BV
------------------------HD6303X,HD63A03X,HD63B03X
Instruction Execution
Cycle
E
BA
Figure 3 HALT and BA Timing
Synchronous Clock
Transmit Data
Receive Data
* 2.0V is high level when clock input.
2.4V is high level when clock output.
Figure 4 SCI Clocked Synchronous Timing
I
MPU Write
E
P20-P27
PSO-PS7 _ _ _ _ _ _ _..I
I\o'::";':;~--
(Outputs)
Figure 5 Port Data Set-up and Hold Times (MPU Read)
~HITACHI
Figure 6 Port Data Delay Times (MPU Write)
359
HD6303X,HD63A03X,HD63B03X.---------------~--------
E
E
Timer 1 - - - - - ,.....,......-.;..;=~ , - - - FRC
T2CNT
P2I, P 25 - - - - - - . . . . : . . -... ~-,:-:~--
PH Output _ _ _ _ _-'
Outputs - - - - - - - - - ' 'Jt~:.l:...---
TCONR = N
(a) Timer 1 Output Timing
(b) Timer 2 Output Timing
Figure 7 Timer Output Timing
Vee
•*
.h
tCKf
• Timer 2; ttcyc
SCI
; tscyc
m
Rl =2.2kQ
Test Point
C
**
R
152074(8)
or Equiv.
C =90pF for 0 0 -0 7 , Ao-A I 5, E
=30pF for Port 2, Port 6, RO, WR, R/W, BA, LI R
R=12kil for 0 0 -0 7 , Ao-A I 5, E, Port 2, Port 6,
RO, W"R, R/W, BA, LI R
•• Timer 1; tPWT
Timer 2; tPWTCK
SCI
;tPWSCK
Figure 9 Bus Timing Test Loads (TTL Load)
Figure 8 Timer 1·2, SCI Input Clock Timing
Interrupt
Test
Internal
Address Bus
NMi.
iRih.
-_J,-+......"-_-" __
"-_..J'~_"'-_...J'-_J'\_....J"__J'\
___"__..r. _
_'''-_..r.__''__..J''_
iRQ..
IRQ,
Internal
DataBus ___J'\_......"__..r.__......"-_..J'~_~_...J~_J'\_ _J"__~_....J"__..r._....J"__~_~"__..r.~
IXO IX8 ACCA
ACCB
CCR
Vector Vector Forst Inst. of
IX 7
IX 15
MSB
LSB
Interrupt Routine
Inlernal
Read
Internal
Write
\~
_______________________-JI
,
_ _ _ _ _ _-.J
1
Figure 10 Interrupt Sequence
360
$
HITACHI
------------------------HD6303X,HD63A03X,HD63B03X
~~,.ss. .*\\\\\\\\\\\\\IC:X=::::x::r-----r~
FFFF
FFFF FFH FFFF FFFF FFFf FFFF _
PC
•
"'-nFF
FFFF FFFF
W,omo'
1\\S»_,\\\\i\\.
'~
\~~~r
_ _ _ _ _ _ _ _ _ __
Woma' ~lm'ltl+I"I'I;.14.1l\'l.--_J----_-_-_-_~:,~~.1--
All
_)\«\\\\\\\\\\\1\-
!~~~'
WR
_~\»»§\\\\\\\\~\\\\\\.
II
_____
J~~'l-J- - - -
~aJIII'l"lrl;IIIIIIIIII;~------~~J
,II
PC8- PCO- First
PC1S
PC7
t~r~!--------
Instruction
Figure 11 Reset Timing
•
FUNCTIONAL PIN DESCRIPTION
• Vee, Vss
Vee and Vss provide power to the MPU with 5V±IO% supply. In the case of low speed operation (fmax = 500kHz), the
MPU can operate with three through six volts. Two Vss pins
should be tied to ground.
• XTAL,EXTAL
These two PulS interface with an AT -cut parallel resonant
crystal. Divide-by-four circuit is on chip, so if 4MHz crystal
oscillator is used, the system clock is IMHz for example.
AT Cut Parallel Resonant Crystal Oscillator
Co=7pF max
Rs=60Q max
XTAL~--~----~
CJ
CL 1=CL2
= 10pF-22pF+ 20%
(3.2-SMHzl
EXTALt---..-..,
J-
CL2
.J,.CL1
(a) Crystal Interface
XTAL~N.C.
EXTAL
External Clock
(b) External Clock
Figure 12 Connection Circuit
EXT AL pin is drivable with the external clock of 45 to
50% duty, and one fourth frequency of the external clock
is produced in the LSI. The external clock frequency should
be less than four times of the maximum operable frequency.
When using the external clock, XT AL pin should be open.
Fig. 12 shows examples of connection circuit. The crystal and
Cl1 , Cl2 should be mounted as close as possible to XT AL
and EXT AL pins. Any line must not cross the line between the
crystal oscillator and XT AL, EXT AL.
• STiiY
This pin makes the MPU standby mode. In "Low" level, the
oscillation stops and the internal clock is stabilized to make
reset condition. To retain the contents of RAM at standby,
"0" should be written into RAM enable bit (RAME). RAME
is the bit 6 of the RAM/port 5 control register at $0014. RAM
is disabled by this operation and its contents is sustained.
Refer to "LOW POWER DISSIPATION MODE" for the
standby mode.
• Reset (RES)
This pin is used to reset the MPU from power OFF state
and to provide a startup procedure. During power-on, RES
pin must be held "Low" level for at least 20ms.
The CPU registers (accumulator, index register, stack pointer,
condition code register except for interrupt mask bit), RAM
and the data register of a port are not initialized during reset,
so their contents are unknown in this procedure.
To reset the MPU during operation, RES should be held
"Low" for at least 3 system-clock cycles. At the 3rd cycle
during "Low" level, all the address buses become "High". When
RES remains "Low", the address buses keep "High". If RES
becomes "High", the MPU starts the next operation.
(I) Latch the value of the mode program pins;MPo and MP t •
~HITACHI
361
HD6303X,HD63A03X,HD63B03X--------------------_ __
(2) Initialize each internal register (Refer to Table 3).
(3) Set the interrupt mask bit. For the CPU to recognize the
maskable interrupts IRQ\ , IRQ2 and IRQ3, this bit should
be cleared in advance.
(4) Put the contents (= start address) of the last two addresses
($FFFE, $FFFF) into the program counter and start the
program from this address. (Refer to Table 1).
*The MPU is usable to accept a reset input until the clock
becomes normal oscillation after power on (max. 20ms). During
this transient time, the MPU and I/O pins are undefined. Please
be aware of this for system designing.
•
Enable (EI
This pin provides a TTL-compatible system clock to external
circuits. Its frequency is one fourth that of the crystal oscillator
or extemal clock. This pin can drive one TTL load and 90pF
capacitance.
Non·Maskable Interrupt (NMI)
When the falling edge of the input signal is detected at this
pin, the CPU begins non-maskable interrupt sequence internally.
As well as the IRQ mentioned below, the instruction being
executed at NMI signal detection will proceed to its completion.
The interrupt mask bit of the condition code register doesn't
affect non-maskable interrupt at all.
When starting the acknowledge to the NMI, the contents of
the program counter, index register, accumulators and condition
code register will be saved onto the stack. Upon completion
•
of this sequence, a vector is fetched from $FFFC and $FFFD
to transfer their contents into the program counter and branch
to the non-maskable interrupt service routine. After reset start,
the stack pointer should be initialized on an appropreate memory area and then the falling edge be input to NMT pin.
•
Interrupt Request (lRQ\, IRQ2)
These are level-sensitive pins which request an internal
interrupt sequence to the CPU. At interrupt request, the CPU
will complete the current instruction before its request acknowledgement. Unless the interrupt mask in the condition code
register is set, the CPU starts an interrupt sequence; if set, the
interrupt request will be ignored. When the sequence starts, the
contents of the program counter, index register, accumulators
and condition code register will be saved onto the stack, then
the CPU sets the interrupt mask bit and will not acknowledge
the maskable request. During the last cycle, the CPU fetches
vectors depicted in Table 1 and transfers their contents to the
program counter and branches to the service routine.
The CPU uses the external interrupt pins, IRQ\ and IRQ2
also as port pins P 50 and P5), so it provides an enable bit to
Bit 0 and I of the RAM port 5 control register at $0014. Refer
to "RAM/PORT 5 CONTROL REGISTER" for the details.
When one of the internal interrupts, ICI, OCI, TOI, CMI or
SIO' is generated, the CPU produces internal interrupt signal
(IRQ3)' IRQ3 functions just the same as IRQ\ or IRQ2 except
for its vector address. Fig. 13 shows the block diagram of the
interrupt circuit.
Table 1 Interrupt Vector Memory Map
Priority
Highest
Lowest
362
Vector
MSB
Interrupt
LSB
FFFE
FFFF
RES
FFEE
FFEF
TRAP
FFFC
FFFD
NMI
FFFA
FFFB
FFF9
SWI (Software Interrupt)
FFF8
FFF6
FFF4
FFF7
FFF2
FFF3
OCI (Timer 1 Output Compare 1, 2)
TOI (Timer 1 Overflow)
FFEC
FFEA
FFED
FFEB
CM I (Timer 2 Counter Match)
IRQ 2
FFFO
FFFl
SIO (RDRF+ORFE+TDRE)
FFF5
IRQ\
ICI (Timer 1 Input Capture)
~HITACHI
------------------------HD6303X,HD63A03X,HD63B03X
Each Register's Interrupt
Enable Flag
"'''; Enable, "0"; Disable
iRQ,
1FiQ2
Condition
Code
---+-~
0-+----1 Register
I·MASK
ICF
- - - H Y " o-+-.......;.::~~·..O.. ;Enable
"''';Disabl
OCF'
OCF2
Interrupt
Request
Signal
TOF
IRQ3
CMF
RDRF
ORFE
TORE
Sleep
Cancel
Signal
TRAP
SWI
Figure 13 Interrupt Circuit Block Diagram
• Mode Program (MP o , MP.)
To operate MPU, MP o pin should be connected to "High"
level and MP. should be connected to "Low" level (refer to
Fig. 15).
•
Read/Write (R/W)
This signal, usually be in read state ("High"), shows whether
the MPU is in read ("High") or write ("Low") state to the
peripheral or memory devices. This can drive one TTL load
and 30pF capacitance.
• RD,WR
These signals show active low outputs when the CPU is
reading/writing to the peripherals or memories. This enables
the CPU easy to access the peripheral LSI with RD and WR
input pins. These pins can drive one TTL load and 30pF capacitance.
•
Load Instruction Register (lIR)
This signal shows the instruction opecode being on data
bus (active low). This pin can drive one TTL load and 30pF
capacitance.
• Memory Ready (MR; PS2 )
This is the input control signal which stretches the system
clock's "High" period to access low-speed memories. During
this Signal being in "High", the system clock operates in normal
sequence. But this signal in "Low", the "High" period of the
system clock will be stretched depending on its "Low" level
duration in integral multiples of the cycle time. This allows the
CPU to interface with low·speed memories ,see Fig. 2). Up to
9 p.s can be stretched.
During internal address space access or nonvalid memory
access, MR is prohibited internally to prevent decrease of operation speed. Even in the halt state, MR can also stretch "High"
period of system clock to allow peripheral devices to access
low-speed memories. As this signal is used also as P 52 , an enable
bit is provided at bit 2 of the RAM/port 5 control register at
$0014. Refer to "RAM/PORT 5 CONTROL REGISTER" for
more details.
•
Halt(HALT;P 53 )
This is an input control signal to stop instruction execution
and to release buses free. When this signal switches to "Low",
the CPU stops to enter into the halt state after haVing executed
the present instruction. When entering into the halt state, it
makes BA (P 74 ) "High" and also an address bus, data bus, RD,
WR, R/W in high impedance. When an interrupt is generated
in the halt state, the CPU uses the interrupt handler after the
halt is cancelled. When halted during the sleep state, the CPU
keeps the sleep state, while BA is "High" and releases the buses.
Then the CPU returns to the previous sleep state when the
HALT signal becomes "High". The same thing can be said when
the CPU is in the interrupt wait state after having executed the
WAI instruction.
• Bus Available (BA)
This is an output control signal which is normally "Low"
but "High" when the CPU accepts HALT and releases the buses.
The H06800 and H06802 make BA "High" and release the
buses at WAI execution, while the HD6303X doesn't make
_HITACHI
363
HD6303X,HD63A03X,HD63B03X-----------------------BA "High" under the same condition. But if the HALT becomes
"Low" when the CPU is in the interrupt wait state after having
executed the WAI, the CPU makes BA "High" and releases the
buses. And when the HALT becomes "High", the CPU returns
to the interrupt wait state.
• PORT
The HD6303X provides three I/O ports. Table 2 gives the
address of ports and the data direction register and Fig. 14
the block diagrams of each port.
(DDR) of port 2 is responsible for I/O state. It provides two
bits; bit 0 decides the I/O direction of P 20 and bit I the I/O
direction of P2I to P27 ("0" for input, "I" for output).
Port 2 is also used as an I/O pin for the timers and the
SCI. When used as an I/O pin for the timers and the SCI, port
2 except P 20 automatically becomes an input or an output
depending on their functions regardless of the data direction
register's value.
Port 2 Data Direction Register
Table 2 Port and Data Direction Register Address
Port
Port 2
Port 5
Port 6
654
Port Address
Data Direction Register
$0003
$0015
$0017
$0001
3
210
$0016
• Port2
An g·bit input/output port. The data direction register
A reset clears the DDR of port 2 and configures port 2 as an
input port. This port can drive one TTL and 30pF. In addition,
it can produce I rnA current when Vout = 1.5V to drive directly
the base of Darlington transistors.
Port Write Signal
Data Bus
Data Bus
Timer 1. 2.~+-_ _ _....
SCI Output
Port Read Signal
Tri·state
Control
-L.
Timer 1. 2. _ _ _ _ _ _ _ _ _<
SCI Input
Timer 1 Input _--------<
(Pl. only)
Port 2
Data Bus _ _ _...r---...._~
Figure 14 Port Block Diagram
• PortS
An 8·bit port for input only. The lower four bits are also
usable as input pins for interrupt, MR and HALT.
• Ao-A 1S
These pins are address bus and can drive one TTL load and
90pF capacitance respectively.
• Port6
An 8·bit I/O port. This port provides an 8·bit DDR corre·
sponding to each bit and can specify input or output by the
bit ("0" for input, "I" for output). This port can drive one
TTL load and 30pF. A reset clears the DDR of port 6. In
addition, it can produce ImA current when Vout =1.5V to
drive directly the base of Darlington transistors.
•
• BUS
D o...... D 7
These pins are data bus and can drive one TTL load and
90pF capacitance respectively.
RAM/PORT 5 CONTROL REGISTER
The control register located at $0014 controls on-chip
RAM and port 5.
RAM/Port 5 Control Register
7
6
4
3
2
1
0
•
364
Bit 0, Bit 1 I ROt, I R0 2 Enable Bit (I ROt E, I R0 2 E)
When using P so and Pst as interrupt pins, write "I" in
these bits. When "0", the CPU doesn't accept an external
_HITACHI
~~~~~~~~~~~~~~~~~~~~~~~~HD6303X,HD63A03X,HD63B03X
interrupt or a sleep cancellation by the external interrupt.
These bits become "0" during reset.
Bit 2 Memory Ready Enable Bit (MRE)
When using P S2 as an input for Memory Ready signal, write
"I" in this bit. When "0", the memory ready function is prohibited. This bit becomes "I" during reset.
E
m5
WR
CJ
R/W
Bit 3 Halt Enable bit (HL TE)
OR
When using P S3 as an input for Halt signal, write "I" in this
bit. When "0", the halt function is prohibited. This bit becomes
"I" during reset.
BA
Port 2
81/0 Lines
Timer 1.2
p~ftl5
Bit 4, Bit 5 Not Used.
8 Data Bus
8:m;~~
MR. HAIi
Port 6
Bit 6 RAM Enable (RAME)
16 Address
Bus
81/0 Lines
On-chip RAM can be disabled by this control bit. The
MPlJ Reset sets "1" at this bit and enables on-chip RAM
available. This bit can be written "1" or ''0'' by software.
When RAM is in disable condition (=logic ''0''), on-chip RAM
is invalid and the CPU can read data from external memory.
This bit should be "0" at the beginning of standby mode to
protect on-chip RAM data.
Figure 15 Operation Mode
Bit 7 Standby Power Bit (STBY PWR)
• MEMORY MAP
When Vee is not provided in standby mode, this bit is
cleared. This is a flag for both read/write by software. If this bit
is set before standby mode, and remains set even after returning
from standby mode, Vee voltage is provided during standby
mode and the on-chip RAM data is valid.
The MPU can address up to 65k bytes. Fig. 16 gives memory
map of HD6303X. 32 internal registers use addresses from "00"
as shown in Table 3.
Table 3 Internal Register
Address
Registers
RIW***
00
-
-
01
Port 2 Data Direction Register
03
04*
-
-
02*
W
Port 2
RIW
-
Initialize at RESET
$FC
Undefined
-
-
08
Timer Control/Status Register 1
RIW
SOO
09
Free Running Counter ("High")
OA
Free Running Counter ("Low")
RIW
RIW
$00
OB
Output Compare Register 1 ("High")
RIW
$FF
OC
00
Output Compare Register 1 ("Low")
R/W
$FF
Input Capture Register ("High")
R
$00
OE
Input Capture Register ("Low")
R
SOO
OF
Timer Control/Status Register 2
RIW
$10
10
Rate. Mode Control Register
RIW
$00
11
Tx/Rx Control Status Register
RIW
$20
12
Receive Data Register
R
$00
13
Transmit Data Register
14
RAM/Port 5 Control Register
15
Port 5
R
16
Port 6 Data Direction Register
W
05
-
-
06*
07*
W
RIW
$00
$00
$7C or $FC
SOO
(continued)
~HITACHI
365
HD6303X,HD63A03X,HD63B03X----------------------Table 3 Internal Register
Registers
Address
17
Port 6
-
18*
RIW***
Initialize at RESET
RIW
Undefined
-
-
19
Output Compare Register 2 ("High")
RIW
$FF
1A
Output Compare Register 2 ("Low")
RIW
$FF
1B
Timer Control/Status Register 3
RIW
$20
1C
Time Con.stant Register
W
$FF
10
Timer 2 Up Counter
RIW
$00
-
-
1E
1F**
Test Register
• External Address .
•• Test Register. Do not access to this-register .
••• R : Read Only Register
W : Write Only Register
RIW: Read/Write Register
and incremented by system clock. The counter value is readable
by software without affecting the counter. The counter is
cleared by reset.
When writing to the MSB byte ($09), the CPU writes the
preset value ($FFF8) into the counter (address $09, $OA)
regardless of the write data value. But when writing to the
LSB byte ($OA) after MSB byte writing, the CPU write not
only LSB byte data into lower 8 bit, but also MSB byte data
into higher 8 bit of the FRC.
The counter will be as follows when the CPU writes to it
by double store instructions (STD, STX etc.).
H06303X
Expanded Mode
Internal·
Registers
$001F
""~~~~< External
m"""":I"7'!~H Memory
Space
Internal
RAM
$OOFF F-'"'~~~:h'
$09 Write
External
Memory
Space
Counter value
$OA Write
$FFF8
$5AF3
In the case of the CPU write ($5AF31 to the FRC
Figure 17 Counter Write Timing
$FFFF &-. _ _ _.J'
• Excludes the following addresses
which may be used externally:
$02, $04, $06, $07, $18.
Figure 16 H06303X Memory Map
•
TIMER 1
The HD6303X provides a 16-bit programmable timer which
can measure an input waveform and generate two independent
output waveforms. The pulse widths of botlt input/output
waveforms vary from microseconds to seconds.
Timer 1 is configurated as follows (refer to Fig. 18).
• Control/Status Register 1 (8 bit)
• Control/Status Register 2 (7 bit)
• Free Running Counter (16 bit)
• Output Compare Register 1 (16 bit)
• Output Compare Register 2 (16 bit)
• Input Capture Register ( 16 bit)
• Free·Running Counter (FRC) ($0009 : OOOA)
The key timer element is a 16-bit free-running counter driven
366
• Output Compare Register (OCR)
($OOOB,SOOOC; OCR1) (S0019,$O01A ;OCR2)
The output compare· register is a 16-bit read/write register
which can control an output waveform. It is always compared
with the FRC.
When data matches, output compare flag (OCF) in the timer
control/status register (TCSR) is set. If an output enable bit
(OE) in the TCSR2 is "1", an output level bit (OLVL) in the
TCSR will be output to bit 1 (Tout 1) and bit 5 (Tout 2) of
port 2. To control the output level again by the next compare, a
change is necessary for the OCR and OLVL. The OCR is set to
$FFFF at reset. The compare function is inhibited for a cycle
just after a write to the OCR or to the upper byte of the
FRC. This is to set the 16-bit value valid in the register for
compare. In addition, it is because $FFF8 is set at the next
cycle of the CPU's MSB byte write to the FRC.
* For data write to the FRC or the OCR, 2-byte transfer
instruction (such as STX etc.) should be used.
• Input Capture Register (lCR) ($0000: ooOE)
The input capture register is a 16-bit read only register which
stores the FRC's value when external input signal transition
~ HITACHI
-----------------------HD6303X,HD63A03X,HD63B03X
generates an input capture pulse. Such transition is defined by
input edge bit (IEDG) in the TCSRI.
In order to input the external input signal to the edge
detecter, a bit of the DDR corresponding to bit 0 of port 2
should be cleared ("0"). When an input capture pulse occures
by input transition at the next cycle of CPU's high-byte read of
the ICR, the input capture pulse will be delayed by one cycle.
In order to ensure the input capture operation, a CPU read of
the ICR needs 2-byte transfer instruction. The input pulse width
should be at least 2 system cycles. This register is cleared
($0000) during reset.
• Timer Control/Status Register 1 (TCSR1) ($0008)
The timer control/status register 1 is an 8-bit register. All bits
are readable and the lower 5 bits are also writable. The upper 3
bits are read only which indicate the following timer status.
Bit 5 The counter value reached to $0000 as a result of
counting-up (TOF).
Bit 6 A match has occured between the FCR and the OCR 1
(OCFl).
Bit 7 Defined transition of the timer input signal causes the
counter to transfer its data to the ICR (ICF).
The followings are each bit descriptions.
Timer Control/Status Register 1
6
5
Bit 7
the OCRI ($OOOB or $OOOC) folloWing the TCSRI or
TCSR2 read.
ICF
Input Capture Flag
This read only bit is set when an input signal of
port 2, bit 0 makes a transition as defined by IEOO and
the FRC is transferred to the ICR. Cleared when reading
the MSB byte ($OOOOD) of the ICR following the
TCSRI or TCSR2 read.
• Timer Control/Status Register 2 (TCSR2) ($OOOF)
The timer control/status register 2 is a 7-bit register. All bits
are readable and the lower 4 bits are also writable. But the
upper 3 bits are read-only which indicate the follOWing timer
status.
Bit 5 A match has occured between the FRC and the OCR2
(OCF2).
Bit 6 The same status flag as the OCFI flag of the TCSRI,
bit 6.
Bit 7 The same status flag as the ICF flag of the TCSRl, bit 7.
The followings are each bit descriptions.
Timer Control/Status Register 2
76543210
ICF IOCF110CF21 -
3
~OC'fLVL21 OE21 O~$OOOF
Bit 0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
OLVL1
Output Levell
OLVLI is transferred to port 2, bit 1 when a match
occurs between the counter and the OCRI. If OEI,
namely, bit 0 of the TCSR2, is set to "1", OLVLl will
appear at bit 1 of port 2.
IEDG
Input Edge
This bit determines which rising edge or falling of
input signal of port 2, bit 0 will trigger data transfer
from the counter to the ICR. For this function, the
DDR corresponding to port 2, bit 0 should be cleared
beforehand.
IEOO=O, triggered on a falling edge
("High" to "Low")
IEDG= 1, triggered on a rising edge
("Low" to "High")
ETOI
Enable Timer Overflow Interrupt
When this bit is set, an internal interrupt (IRQ3) by
TOI interrupt is enabled. When cleared, the interrupt is
inhibited.
EOCll
Enable Output Compare Interrupt 1
When this bit is set, an internal interrupt (IRQ3) by
OCII interrupt is enabled. When cleared, the interrupt
is inhibited.
EICI
Enable Input Capture Interrupt
When this bit is set, an internal interrupt (IRQ3) by
ICI interrupt is enabled. When cleared, the interrupt is
inhibited.
TOF Timer Overflow Flag
This read only bit is set when the counter increments from $FFFF by 1. Cleared when the counter's
MSB byte ($0009) is ready by the CPU following the
TCSR 1 read.
OCF 1 Output Compare Flag 1
This read only bit is set when a match occurs between the OCRI and the FRC. Cleared by writing to
$
OEl Output Enable 1
This bit enables the OLVLl to appear at port 2, bit
1 when a match has occurred between the counter and
the output compare register 1. When this bit cleared, bit
1 of port 2 will be I/O port. When set, it will be an
output ofOLVLl automatically.
Bit 1 OE2 Output Enable 2
This bit enables the OLVL2 to appear at port 2, bit
5 when a match has occurred between the counter and
the output compare register 2. When this bit cleared,
port 2, bit 5 will be I/O port. When set, it will be an
output of OLVL2 automatically.
Bit 2 OL VL2 Output Level 2
OLVL2 is transferred to port 2, bit 5 when a match
has occurred between the counter and the OCR2. If
OE2, namely bit 5 of the TCSR2, is set to "1", OLVL2
will appear at port 2, bit 5.
Bit 3 EOCI2 Enable Output Compare Interrupt 2
When this bit is set, an internal interrupt (IRQ3) by
OCI2 interrupt is enabled. When cleared, the interrupt
is inhibited.
Bit 4 Not Used
Bit 5 OCF2 Output Compare Flag 2
This read-only bit is set when a match has occurred
between the counter ·and the OCR2. Cleared when
writing to the OCR2 ($0019 or $OOIA) following the
TCSR2 read.
Bit 6 OCFl Output Compare Flag 1
Bit 7 ICF Input Capture Flag
OCFl and ICF addresses are partially decoded.
CPU read of the TCSRl/TCSR2 makes it possible to
read OCFl and ICF into bit 6 and bit 7.
Both the TCSRI and TCSR2 will be cleared during reset.
(Note) If OEI or OE2 is set to "1" before the first output
compare match occurs after reset restart, bit I or bit 5
of port 2 will produce "0" respectively.
HITACHI
367
HD6303X,HD63A03X,HD63B03X------------------------
Figure 18 Timer 1 Block Diagram
(Note) Because the set condition of ICF precedes its reset
condition, ICF is not cleared when the set condition
and the reset condition occur simultaneously. The
same phenomenon applies to OCF I, OCF2 or TOF
respectively.
• TIMER2
In addition to the timer I, the HD6303X provides an 8·bit
reloadable timer, which is capable of counting the external
event. This timer 2 contains a timer output, so the MPU can
generate three independent waveforms (refer to Fig. 19).
The timer 2 is configured as follows:
Control/Status Register 3 (7 bit)
8·bit Up Counter
Time Constant Register (8 bit)
•
• Time Constant Register (TCONR) ($001C)
The time constant. register is an 8·bit write only register. It
is always compared with the counter.
When a match has occurred, counter match flag (CMF) of
the timer control status register 3 (TCSR3) is set and the value
selected by TOSO and TOSI of the TCSR3 wiD appeal'at port 2,
bit 6. When CMF is set, the counter will be cleared simultane·
ously and then start counting from $00. This enables regular
interrupts and waveform outputs without any software support.
The TCONR is set to "$FF" during reset.
• Timer Control/Status Register 3 (TCSR3) ($001 B)
The timer control/status register 3 is a 7·bit register. AU bits
are readable and 6 bits except for CMF can be written.
The followings are each pin descriptions.
Timer 2 Up Counter (T2CNT) ($0010)
Timer Control/Status Register 3
This is an 8·bit up counter which operates with the clock
decided by CKSO and CKSI of the TCSR3. The counter is
always readable without affecting itself. In addition, any value
can be written to the counter by software even during counting.
The counter is cleared when a match occurs between the
counter and the TCONR or during reset.
If a write operation is made by software to the counter at the
cycle of counter clear, it does not reset the counter but put the
write data to the counter.
368
$
I
HITACHI
76543210
CMF IECMI\ -
IT2E \TOS1\TOsoICKSlI CKsol$0018
-----------------------HD6303X,HD63A03X,HD63B03X
,..---- Timer1 FRC
....- - - - - Port 2
Bit 7
t-+---I------'i~
Port 2
Bit 6
Figure 19 Timer 2 Block Diagram
Bit 0
Bit 1
CKSO
CKS1
Input Clock Select 0
Input Clock Select 1
Table 5 Timer 2 Output Select
Input clock to the counter is selected as shown in
Table 4 depending on these two bits. When an external
clock is selected, bit 7 of port 2 will be a clock input
automatically. Timer 2 detects the rising edge of the
external clock and increments the counter. The external
clock is countable up to half the frequency of the
system clock.
Table 4 Input Clock Select
TOS1
TOSO
0
0
Timer Output Inhibited
0
1
Toggle Output *
1
0
Output "0"
1
1
Output "1"
Timer Output
• When a match occurs between the counter and the TCONA, timer 2
output level is reversed. This leads to production of a square wave with
50% duty to the external without any software support.
CKS1
CKSO
Input Clock to the Counter
Bit 4
0
E clock
0
0
1
1
0
E clock/128*
1
1
External clock
When this bit is cleared, a clock input to the up
counter is prohibited and the up counter stops. When set
to "I"', a clock selected by CKS) and CKSO (Table 4)
is input to the up counter.
(Note) P26 produces "0" when T2E bit cleared and timer 2 set
in output enable condition by TOSI or TOsa. It also
produces "0" when T2E bit set "I" and timer 2 set in
output enable condition before the first counter match
occurs.
E clock/S*
• These clocks come from the FAC of the timer 1. If one of these clocks
is selected as an input clock to the up counter, the CPU should not
write to the FAC of the timer 1.
Bit 2
Bit 3
TOSO
TOS1
Timer Output Select 0
Timer Output Select 1
Bit 5
Bit 6
When a match occurs between the counter and the
TCONR timer 2 outputs shown in Table 5 will appear at
port 2, bit 6 depending on these two bits. When both
TOsa and TOSI are "0", bit 6 of port 2 will be an I/O
port.
T2E
Timer 2 Enable Bit
Not Used
ECMI Enable Counter Match Interrupt
When this bit is set, an internal interrupt (IRQ3) by
CMI is enabled. When cleared, the interrupt is inhibited.
Bit 7
CMF
Counter Match Flag
This read only bit is set when a match occuts between
the up counter and the TCONR. Cleared by a software
write (unable to write "I" by software).
Each bit of the TCSR3 is cleared during reset.
_HITACHI
369
HD6303X,HD63A03X,HD63B03X-----------------------• SERIAL COMMUNICATION INTERFACE (SCt)
The HD6303X SCI contains two operation modes; one is an
asynchronous mode by the NRZ format and the other is a
clocked synchronous mode which transfer data synchronizing
with the serial clock.
The serial interface is configured as follows:
• Control/Status Register (TRCSR)
• Rate/Mode Control Register (RMCR)
• Receive Data Register (RDR)
• Receive Data Shift Register (RDSR)
• Transmit Data Register (TDR)
• Transmit Data Shift Register (TDSR)
The serial I/O hardware requires an initialization by software
for operation. The procedure is usually as follows:
I) Write a desirable operation mode into each corresponding control bit of the RMCR.
2) Write a desirable operation mode into each corresponding control bit of the TRCSR.
When using bit 3 and 4 of port 2 for serial I/O only, there is
no problem even if TE and RE bit are set. But when setting the
baud rate and operation mode, TE and RE should be "0". When
clearing TE and RE bit and setting them again, more than I bit
cycle of the current baud rate is necessary. If set in less than I
bit cycle, there may be a case that the internal transmit/receive
initialization fails.
•
Asvnchronous Mode
An asynchronous mode contains the folloWing two data
formats:
I Start Bit + 8Hit Data + I Stop Bit
I Start Bit + 9 Bit Data + I Stop Bit
In addition, if the 9th bit is set to "I" when making 9
bit data format, the format of
I Start bit + 8 Bit Data + 2 Stop Bit
is also transferred.
Data transmission is enabled by setting TE bit of the TRCSR,
then port 2, bit 4 will become a serial output independently of
the corresponding DDR.
.
For data transmit, both the RMCR and TRCSR shOUld be
set under the desirable operating conditions. When TE bit is
set during this process, 10 bit preamble will be sent in 8-bit data
format and II bit in 9-bit data format. When the preamble is
produced, the !nternal synchronization will become stable and
the transmitter is ready to act.
The conditions at this stage are as follows.
1) If the TDR is empty (TDRE=I), consecutive I's are
produced to indicate the idle state.
2) If the TDR contains data (TDRE=O), data is sent to the
transmit data shift register and data transmit starts.
During data transmit, a start bit of "0" is transmitted first.
Then 8-bit or 9-bit data (starts from bit 0) and a stop bit of "I"
370
are transmitted .
When the TDR is "empty", hardware sets TDRE flag bit. If
the CPU doesn't respond to the flag in proper timing (the TDRE
is in set condition till the next normal data transfer starts from
the 'transmit data), "I" is transferred instead of the start bit "0"
and continues to be transferred till data is provided to the data
register. While the TDRE is "1", "0" is not transferred.
Data receive is possible by setting RE bit. This makes port 2,
bit 3 be a serial input. The operation mode of data receive is
decided by the contents of the TRCSR and RMCR. The first
"0" (space) synchronizes the receive bit flow. Each bit of the
following data will be strobed in the middle. If a stop bit is not
"1", a framing error assumed and ORFE is set
When a framing error occurs, receive data is transferred to
the receive data register and the CPU can read error-generating
data. This makes it possible to detect a line break.
If the stop bit is .. 1", data is transferred to the receive data
register and an interrupt flag RDRF is set. If RDRF is still
set when receiving the stop bit of the next data, ORFE is set to
indicate overrun generation.
When the CPU read the receive data register as a response to
RDRF flag or ORFE flag after having read TRCS, RDRF or
ORFE is cleared.
(Note) Clock Source in Asynchronous Mode
When using an internal clock for serial I/O, the fonowings should be kept in mind.
• Set CC 1 and CCO to "1" and "0" respectively.
• A clock is generated regardless of the value of TE,
RE.
• Maximum clock rate is E+ 16.
• Output clock rate is the same as bit rate.
When using an external clock for serial I/O, the followings should be kept in mind.
• Set CCI and CCO in the RMCR to "I" and "I" respectively.
• The external clock frequency should be set 16 times
of the applied baud rate.
• Maximum clock frequency is that of the system
clock.
•
Clocked Synchronous Mode
.
In the clocked synchronous mode, data transmit is
synchronized with the clock pulse. The HD6303X SCI
provides functionally independent transmitter and receiver
which makes fun duplex operation possible in the asynchronous
mode. But in the clocked synchronous mode an SCI clock I/O
pin is only P22 , so the simultaneous receive and transmit
operation is not available. In this mode, TE and RE should
not be in set condition ("1") simultaneously. Fig. 21 gives a
synchronous clock and a data format in the clocked synchronousmode.
_HITACHI
------------------------HD6303X,HD63A03X,HD63B03X
HD6303X Internal Data Bus
Transmit/Receive Control and Status Register
Timerl FAC.
Timer2
Up Counter
Figure 20 Serial Communication Interface Block Diagram
Data transmit is realized by setting TE bit in the TRCSR.
Port 2, bit 4 becomes an output unconditionally independent
of the value of the corresponding DDR.
Both the RMCR and TRCSR should be set in the desirable
operating condition for data transmit.
When an external clock input is selected, data transmit is
<======::::J
performed under the TDRE flag "0" from port 2, bit 4, synchronizing with 8 clock pulses input from external to port 2,
bit 2.
Data is transmitted from bit 0 and the TDRE is set when the
transmit data shift register is "empty". More than 9th clock
pulse of external are ignored.
Transmit Direction
Synchronous
clock
Data
~NotValid
- Transmit data is produced from a falling edge of a synchronous clock to the next falling edge •
• Receive data is latched at the rising edge ..
Figure 21
Clocked Synchronous Mode Format
When data transmit is selected to the clock output, the MPU
produces transmit data and synchronous clock at TDRE flag
clear.
Data receive is enabled by setting RE bit. Port 2, bit 3 will
be a serial input. The operating mode of data receive is decided
by the TRCSR and the RMCR.
If the external clock input is selected, RE bit should be
set when P22 is "High". Then 8 external clock pulses and
the synchronized receive data are input to port 2, bit 2
and bit 3 respectively. The MPU put receive data into the
receive data shift register by this clock and set the RDRF
flag at the termination of 8 bit data receive .. More than 9th
clock pulse of external input are ignored. When RDRF is
cleared by reading the receive data register, the MPU starts
receiving the next data. So RDRF should be cleared with P22
"High".
When data receive is selected to the clock output, 8 synchronous clocks are output to the external by setting RE bit. So receive data should be input from external, synchronously with
this clock. When the first byte data is received, the RDRF flag
is set. After the second byte, receive operation is performed and
output the synchronous clock to the external by clearing the
RDRF bit.
• Transmit/Receive Control Status Register (TRCSR) ($0011)
The TRCSR is composed of 8 bits which are all readable. Bits
o to 4 are also writable. This register is initialized to $20 during
reset. Each bit functions as follows.
~HITACHI
371
HD6303X,HD63A03X,HD63B03X-----------------------Transmit/Receive Control Status Register
76543
10
I I
IRORF'ORFE'TORE' RIE 'RE 'TIE TE
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
372
WU 1$0011
WU Wake·up
In a typical multi-processor configuration, the
software protocol provides the destination address at
the first byte of the message. In order to make un·
interested MPU ignore the remaining message, a wake-up
function is available. By this, uninterested MPU can inhibit all further receive processing till the next message
starts.
Then wake-up function is triggered by consecutive
I's with I frame length (IO bits for 8·bit data, II for
9-bit). The software. protocol should provide the idle
time between messages.
By setting this bit, the MPU stops data receive till the
next message. The receive of consecutive" I" with one
frame length wakes up and clears this bit and then the
MPU restarts receive operation. However, the RE flag
should be already set before setting this bit. In the
clocked synchronous mode WU is not available, so this
bit should not be set.
TE Transmit Enable
When this bit is set, transmit data will appear at port
2. bit 4 after one frame preamble in asynchronous mode,
while in clocked synchronous mode appear immediately.
This is executed regardless of the value of the corresponding OOR. When TE is cleared, the serial I/O
doesn't affect port 2, bit 4.
TIE Transmit Interrupt Enable
When this bit is set, an internal interrupt (lRQ3) is
enabled when TORE (bit 5) is set. When cleared, the
interrupt is inhibited.
RE Receive Enable
When set, a signal is input to the receiver from port
2, bit 3 regardless of the value of the OOR. When RE
is cleared, the serial I/O doesn't affect port 2, bit 3.
RIE Receive Interrupt Enable
When this bit is set, an internal interrupt. IRQ3 is
enabled when RDRF (bit 7) or ORFE (bit 6) is set.
When cleared, the interrupt is inhibited.
TORE Transmit Data Register Empty
TORE is set when the TOR is transferred to the
transmit data shift register in the asynchronous mode,
while in clocked synchronous mode when the TOSR is
"empty". This bit is reset by reading the TRCSR and
writing new transmit data to the transmit data register.
TORE is set to "I" during reset.
ORFE Overrun Framing Error
ORFE is set by hardware when an overrun or a framing error is generated (during data receive only). An
overrun error occurs when new receive data is ready to
be transferred to the ROR during RORF still being set.
A framing error occurs when a stop bit is "0". But in
clocked synchronous mode, this bit is not affected. This
bit is cleared when reading the TRCSR, then the ROR,
or during reset.
Bit 7 RDRF Receive Data Register Full
RORF is set when the RDSR is transferred to the
RDR. Cleared when reading the TRCSR, then the RDR.
or during reset.
(Note) When a few bits are set between bit 5 to bit 7 in the
TRCSR, a read of the TRCSR is sufficient for clearing
those bits. It is not necessary to read the TRCSR every·
time to clear each bit.
• Transmit Rate/Mode Control Register (RMCR)
The RMCR controls the following serial I/O:
• Baud Rate
• Clock Source
• Data Format
• Port 2, Bit 2 Function
In addition, if 9·bit data format is set in the asynchronous
mode, the 9th bit is put in this register. All bits are readable and
writable except bit 7 (read only). This register is set to $00
during reset.
Transfer Rate/Mode Control Register
76543210
IROB ITDBI SS21 CC2' CCl
BitO
Bit 1
Bit 5
SSO}
SSl
SS2
I ISSl I
cco
sso
1$0010
Speed Select
These bits control the baud rate used for the SCI. Table
6 lists the available baud rates. The timer I FRC (SS2=O) and
the timer 2 up counter (SS2=1) provide the internal clock to the
SCI. When selecting the timer 2 as a baud rate source, it func·
tions as a baud rate generator. The timer 2 generates the baud
rate listed in Table 7 depending on the value of the TCONR.
(Note) When operating the SCI with internal clock, do not
perform write operation to the timer/counter which is
the clock source of the SCI.
Bit 2
Bit 3
Bit 4
CCO}
CCl
CC2
Clock Control/Format Select*
These bits control the data format and the clock source
(refer to Table 8).
• CCO, CC I and CC2 are cleared during reset and the MPU
goes to the clocked synchronous mode of the external
clock operation. Then the MPU forces port 2, bit 2
in the clock input state. When using port 2, bit 2 as an
output port, the DDR of port 2 should be set to "I" and
CCI and CCO to "0" and "I" respectively.
~HITACHI
------------------------HD6303X,HD63A03X,HD63B03X
Table 6 SCI Bit Times and Transfer Rates
(1) Asynchronous Mode
SS2
SSl
SSO
0
0
0
0
0
0
1
XTAL
2.4576MHz
4.0MHz
E
6l4.4kHz
1.0MHz
4.9l52MHz
1.22BBMHz
l6ps/62500Baud
l3ps/76BOOBaud
E+16
26Jls/3B400Baud
1
E+12B
20Bps/4BOOBaud
l2BJls/7B12.5Baud
104.2 ps/9600Baud
0
E+1024
1.67ms/600Baud
1.024ms/976.6Baud
B33.3ps/1200Baud
6.67ms/150Baud
4.096ms/244.l Baud
3.333ms/300Baud
*
*
*
0
1
1
E+4096
1
-
-
-
* When SS2 is "1" , Timer 2 provides SCI clocks. The baud rate is shown as follows with the TCONR as N.
Baud Rate
f
32 (N+l)
f: input clock frequency to the)
timer 2 counter
(
N =0"'" 255
(2) Clocked Synchronous Mode *
SS2 SS1
SSO
XTAL
4.0MHz
6.0MHz
8.0MHz
E
1.0MHz
1.5MHz
2.0MHz
0
0
0
E+2
0
0
1
E+16
2t/Sibit
1.33,us/bit
1ps/bit
l6ps/bit
10.7ps/bit
Bps/bit
0
1
0
E+128
12Bp s/bit
B5.3,uSibit
64ps/bit
0
1
1
E+512
512 p s/bit
341 pslbit
256p s/bit
1
-
**
**
**
-
-
* Bit rates in the case of internal clock operation. In the case of external clock operation, the external clock is
opera table up to DC ..... 1/2 system clock.
** The bit rate is shown as follows with the TCONR as N.
Bit Rate (J.ls/bit)
= 4 (~+ 1)
(
f: input clock frequency to the)
timer 2 counter
N = 0"'" 255
Table 7 Baud Rate and Time Constant Register Example
~.~
XTAL
Baud~----......
110
150
300
600
1200
2400
4800
9600
19200
3B400
2.4576MHz
3.6B64MHz
4.0MHz
4.9152MHz
8.0MHz
21127
63
31
15
7
3
1
0
32191
95
47
23
11
5
2
35207
103
51
25
12
43255
127
63
31
15
7
3
1
0
7051207
103
51
25
12
* E/8 clock is input to the timer 2 up counter and E clock otherwise.
~HITACHI
373
H06303X,H063A03X,H063B03X----------------------Table a
CC2
CC1
0
0
1
1
0
0
0
0
0
1
1
1
1
0
1
1
CCO
0
Format
a-bit data
1
0
1
0
1
0
1
8-bitdata
a-bit data
a-bit data
SCI Format and Clock Source Control
a-bit data
9-bit data
Mode
Clocked Synchronous
Asynchronou s
Asynchronous
Asynchronous
Clocked Synchronous
Asynchronous
9-bit data
9-bit data
Asynchronous
Asynchronous
Clock Source
External
Internal
Internal
External
Internal
Internal
Internal
External
Port 2, Bit 2
Input
Not Used**
Output*
Input
Output
Not Used**
Output*
Input
Port 2, Bit 3
T
Port 2, Bit 4
When the TRCSR, RE bit is "1",
bit 3 is used as a serial input.
>
When the TRCSR, TE bit is "1",
bit 4 is used as a serial output.
* Clock output regardless of the TRCSR, bit RE and TE.
** Not used for the SCI.
Bit 6
Bit 7
TD8 Transmit Data Bit a
When selecting 9-bit data format in the asynchronou'S mode, this bit is transmitted as the 9th data. In
transmitting 9-bit data, write the 9th data into this bit
then write data to the receive data register.
RDa Receive Data Bit a
When selecting 9-bit data format in the asynchronous
Table 9
Timer
1
Timer
2
mode, this bit stores the 9th bit data. In receiving 9-bit
data, read this bit then the receive data register.
• TIMER, SCI STATUS FLAG
Table 9 shows the set and reset conditions of each status
flag in the timer I , timer 2 and SCI.
Timer 1, Timer 2 and SCI Status Flag
Set Condition
ICR by edge input to P20 •
ICF
FRC
OCF1
OCR1=FRC
2.
1.
OCF2
OCR2=FRC
2.
1.
TOF
FRC=$FFFF+1 cycle
CMF
T2CNT=TCONR
RDRF
Receive Shift Register
ORFE
1.
2.
SCI
TORE
1.
2.
3.
-4
-4
RDR
Framing Error (Asynchronous Mode)
Stop Bit = 0
Overrun Error (Asynchronous Mode)
Receive Shift Register -4 RDR when
RDRF=1
Asynchronous Mode
TOR -4 Transmit Shift Register
Clocked Synchronous Mode
Transmit Shift Register is "empty"
RES=O
(Note) 1.... ; transfer
2. For example; "ICAH" means High byte of ICA.
374
$
HITACHI
1.
2.
1.
2.
1.
2.
1.
2.
1.
2.
Reset Condition
Read the TCSR 1 or TCSR2 then ICRH,
when ICF= 1
RES=O
Read the TCSR1 or TCSR2 then write to the
OC R 1 H or OC R 1 L, when OCF 1 = 1
J{£S=O
Read the TCSR2 then write to the OCR2H or
OCR2L, when OCF2= 1
m=O
Read the TCSR1 then FRCH, when TOF=1
ifES=o
Write "0" to CM F , when CM F = 1
RES=o
Read the TRCSR then RDR, when RDRF= 1
R"ES=O
Read the TRCSR then RDR, when ORFE = 1
RES=O
Read the TRCSR then write to the TOR,
when TDRE=1
~~~~~~~~~~~~~~~~~~~~~~~~HD6303X,HD63A03X,HD63B03X
•
for a system with no need of the HD6303X's consecutive
operation.
LOW POWER DISSIPATION MODE
The HD6303X provides two low power dissipation modes;
sleep and standby.
• Standby Mode
The HD6303X stops all the clocks and goes to the reset
state with STBY"Low". In this mode, the power dissipation is
reduced conspicuously. All pins except for the power supply,
the STBY and XT AL are detached from the MPU internally
and go to the high impedance state.
In this mode the power is supplied to the HD6303X, so
the contents of RAM is retained. The MPU returns from this
mode during reset. The followings are typical usage of this
mode.
Save the CPU information and SP contents on RAM by NMI.
Then disable the RAME bit of the RAM control register and set
the STBY PWR bit to go to the standby mode. If the STBY
PWR bit is still set at reset start, that indicates the power is
supplied to the MPU and RAM contents are retained properly.
So system can restore itself by returning their pre-standby informations to the SP and the CPU. Fig. 22 depicts the timing at
each pin with this example.
• Sleep Mode
The MPU goes t,o the sleep mode by SLP instruction execution. In the sleep mode, the CPU stops its operation, while the
registers' contents are retained. In this mode, the peripherals
except the CPU such as timers, SCI etc. continue their functions. The power dissipation of sleep-condition is one fifth that
of operating condition.
The MPU returns from this mode by an interrupt, RES or
STBY; it goes to the reset state by RES and the standby mode
by STBY. When the CPU acknowledges an interrupt request, it
cancels the sleep mode, returns to the operation mode and
branches to the interrupt routine. When the CPU masks this
interrupt, it cancels the sleep mode and executes the next
instruction. However, for example if the timer 1 or 2 prohibits
a timer interrupt, the CPU doesn't cancel the sleep mode because of no interrupt request.
This sleep mode is effective to reduce the power dissipation
Vee
Ipuu...11111_----'H~-----fl
HD6303X
14)
:
I
I
I
1~11111_---41~:
r:I
I
I
~
Save registers
RAM/Port 5 Control
Register Set
I
~
Oscillator
Start Time
~
Restart
Figure 22 Standby Mode Timing
•
TRAP FUNCTION
The CPU generates an interrupt with the highest priority
(TRAP) when fetching an undefined instruction or an instruction from non-memory space. The TRAP prevents the systemburst caused by noise or a program error.
•
Op Code Error
When fetching an undefined op code, the CPU saves CPU
registers as well as a normal interrupt and branches to the TRAP
($FFEE. $FFEF). This provides the priority next to reset.
•
Address Error
When an instruction fetch is made from internal register
($0000-$001 F), the MPU generates an interrupt as well as an
op code error. But on the system with no memory in its external memory area, this error processing is not applicable if
an instruction fetch is made from the external non-memory
area.
This processing is available only for an instruction fetch and
is not applicable to the access of normal data read/write.
(Note) The TRAP interrupt provides a retry function differently from other interrupts. This is a program flow return
to the address where the TRAP occurs when a sequence
returns to a main routine from the TRAP interrupt
routine by RTI. The retry can prevent the system burst
caused by noise etc.
However, if another TRAP occurs, the program repeats
the TRAP interrupt forever, so the consideration is
necessary in programming.
•
INSTRUCTION SET
The HD6303X provides object code upward compatible
with the HD6801 to utilize all instruction set of the
HMCS6800. It also reduces the execution times of key instruc-
~HITACHI
375
HD6303X,HD63A03X,HD63B03X----------------------tions for throughput improvement.
Bit manipulation instruction, change instruction of the
index register and accumulator and sleep instruction are also
added.
The followings are explained here.
CPU Programming Model (refer to Fig. 23)
• Addressing Mode
• Accumulator and Memory Manipulation Instruction
(refer to Table 10)
• New Instruction
• Index Register and Stack Manipulation Instruction
(refer to Table II)
• Jump and Branch Instruction (refer to Table 12)
• Condition Code Register Manipulation
(refer to Table 13)
• Op Code Map (refer to Table 14)
• Programming Model
Fig. 23 depicts the HD6303X programming model. The
double accumulator 0 consists of accumulator A and B, so
when using the accumulator 0, the contents of A and Bare
destroyed.
f.----"- ___o~g
8·8"Accu ..u ......
A
1. 5
1.
5
SP
1.
5
PC
7
'
01
Indr-Regl".IXI
01
SI.k Po,n'", ISP,
01
PrOW"" Coun.... IPCI
~
I N Z
V C
In this mode, the second byte shows the upper 8 bit of the
data stored address and the third byte the lower 8 bit. This
indicates the absolute address of 3 byte instruction in the
memory.
Indexed Addressing
The second byte of an instruction and the lower 8 bit of the
index register are added in this mode. As for AIM, OIM, ElM
and TIM, the third byte of an instruction and the lower 8 bits
of the index register are added.
This carry is added to the upper 8 bit of the index register
and the result is used for addressing the memory. The modified
address is retained in the temporary address register, so the contents of the index register doesn't change. This is a 2-byte
instruction except AIM, OIM, ElM and TIM (3-byte instruction).
An instruction itself specifies the address. That is, the
instruction addresses a stack pointer, index register etc. This is a
one-byte instruction.
Relative Addressing
0
H
Extended Addressing
Implied Addressing
.... 8
D O O r 16·8,1 OoubW Accumulator 0
1,
In this addressing mode, the second byte of an instruction shows the address where a data is stored. 256 bytes (SO
through $255) can be addressed directly. Execution times
can be reduced by storing data in this area so it is recommended
to make it RAM for users' data area in configurating a system.
This is a 2-byte instruction, while 3 byte with regard to AIM,
OIM, ElM and TIM.
Cond.t,onCode Ret,"" leCA,
Carty/Borrow hom MS8
-av-rtaow
Z...
,.,....v.
In••"upt
H,,'
c.r'v IF rom 81t 31
The second byte of an instruction and the lower 8 bits of
the program counter are added. The carry or borrow is added to
the upper 8 bit. So addressing from -126 to + 129 byte of the
current instruction is enabled. This is a 2-byte instruction.
(Note) CLI, SEI Instructions and Interrupt Operation
When accepting the IRQ at a preset timing with the help
of CLI and SEI instructions, more than 2 cycles are
necessary between the CLI and SEI instructions. For
example, the following program (a) (b) don't accept the
IRQ but (c) accepts it.
Figure 23 CPU Programming Model
• CPU Addressing Mode
TIle HD6303X provides 7 addressing modes. The addressing
mode is decided by an instruction type and code. Table 10
through 14 show addressing modes of each instruction with
the execution times counted by the machine cycle.
When the clock frequency is 4 MHz, the machine cycle time
becomes microseconds directly.
CLI
SEI
CLI
NOP
SEI
CLI
NOP
NOP
SEI
(a)
(b)
(c)
Accumulator (ACCX) Addressing
Only an accumulator is addressed and the accumulator A or
B is selected. This is a one-byte instruction.
Immediate Addressing
This addressing locates a data in the second byte of an
instruction. However, LOS and LOX locate a data in the second
and third byte exceptionally. This addressing is a 2 or 3-byte
instruction.
Direct Addressing
376
_HITACHI
The same thing can be said to the TAP instruction
instead of the CLI and SEI instructions.
Table 10 Accumulator, Memory Manipulation Instructions
Condition Code
Addressing Modes
Operations
Mnemonic
Add
Add Double
Bit Test
Clear
OP
-
4
2
BB
4
3
A+M~
4
2
FB
4
3
B+M~B
5
2
F3
5
3
A:B+M:M+l~A:B
4
2
B9
4
3
A+M+C~A
E9
4
2
A4
~
OP
-
#
OP
ADDA
18B
2
2
9B
3
2
AB
ADDB
CB
2
2
DB
3
2
EB
ADDD
C3
3
3
03
4
2 E3
89
2
2
99
3
2
A9
AD~~_ C9
2
2
09
3
2
~-- ~~~
2
94
3
2
3
2
E4
3
2
3
2
ABA
-
#
ANDB
C4
2
BIT A
85
2
BIT B
C5
2
i rD4
~5
2
05
81
CMPB
Cl
CBA
Complement,l's
COM
2
'2
#
1 1
A +
B~
3
B+M+C~B
4
3
A'M~A
4
3
A5
4
E5
6F
B5
4
3
4
2
F5
4
3
5
2
7F
5 3
2
91
3
2
Al
4
2
Bl
4
3
2
01
3
2
El
4
2
Fl
4
3
B'M~B
A·M
6
2
73
6
1
1
00 - B
R
S R R
A-M
B-M
1 1 I I
t 1 1 I
A-B
t t 1 1
M-M
t t
t 1
t 1
R
S
R
S
1 1
t 1
,'I; '2;
1
1
1
A
~A
1 1 OO-A-A
1
B -B
OO-M-M
--
NEG8
50
1 1 OO-B-B
Decimal Adjust, A
DAA
19
2 1 characters into BCD format
DECA
4A
1
1
DECB
5A
1
1
Exclusive OR
EORA
EORB
Increl'/)8nt
Load
Accumulator
88
CB
2
7A
6
3
3
86
4
2
B8
4
3
A@M-A
E8
4
2
F8
4
3
B@M- B
6C
6
2
7C
6
3
M+l-M
2
2
96
3
2
A6
4
2
B6
4
t
1 I
M~B
I
t
R
M + 1 - B. M~ A
t
I
R
t
1 t
R
I
I
(6.'
t
I
t
~8;
1
((I
I
(OJ
t
t
t
2
2
06
3
2
E6
4
2
F6
4
3
3
DC 4
2
EC
5
2
FC
5
3
3D
Multiply Unsigned
MUL
OR, Inclusive
ORAA
8A
2
2
9A
3
2
AA 4
2
BA
4
3
ORAB
CA
2
2
DA 3
2
EA 4
2
FA
4
3
Push Data
PSHA
36
PSHB
PULA
PULB
2
79
6
6
2
76
6
7 1
B +M- B
1
A - Msp, SP - 1 ~ SP
37
4
1
B - M,p, SP - 1 ~ SP
32
3
1
SP + 1 - SP, Msp ~ A
33
3 1 SP + 1 - SP, Msp ~ B
49
1
1
1
3
RORA
46
RORB
56
(Note) Condition Code Register will be explained in Note of Table 13.
¢!)HITACHI
1
1
1
1
B
C
b7
:)
4J.!
I
B
C b7
(5, •
R
• ilt
I
4
1
I
A.B~A:B
A+M- A
59
ROL8
66
1
3
ROLA
ROR
A + 1 - A
B + 1- B
3
6
R
1 1 ~)
1 1 @.
M-A
CC
69
R
3
C6
Rotate Right
t 1
t t
AS
2
LDD
ROL
1 1 lot) •
2
LDAB
Rotate Left
(.)
B-1 - B
3
Load Double
Accumulator
Pull Data
(.)
3
1
(2)
(3)
1
08
1. 1
(1')
1 1 t
t
98
5C
(I) '2)
1 1
2
4C
S
A-I - A
2
INCA
R
M-l -M
2
INCB
LDAA
t t
Converts binary add of BCD
2
INC
R
5F
40
SA 6
t
t
t
t
t
t
t t t
t t t
: 1 t
t t t
t t R
t 1 R
1 t R
S R R
3
I
1 1
S R
NEG
DEC
I
R
NEGA
Decrement
I
1 t
00- A
Complement, 2's
-------
I
1
1
INeptel
--
0
1
53
6
1
V C
1 1 R
COMB
70
2
R
1
1
2
3
N Z
B·M
43
6
I
00- M
COMA
60
H
4F
11
63
4
t
t
t
A
4
2
5
··
· ··
··
··. ··· ···
·· ·· ·
·· ··
··· ···
·· ··
·· ··
·· ··
·· ·· ..
·· ··
··· ··· ·.·
··· ··· ·
·· ·· ··
·· ·· · · ·
··· ··· ·· ·· ·· ···
·· ·· ·· ·· ·· ··
:)~IIIIII liJ · ·
·· ··
·· ··
··
A
F9
CLRB
CMPA
-
2 B4
--- -_._4 2 F4
~_A
Compare
Accumulators
OP
lB
CLR
Compare
IMPLIED
#
#
ADCA
Register
EXTEND
INDEX
-
Add Accumulators
----
DIRECT
OP
Add With Carry
AND
IMMED.
Boolean/
Arithmetic Operation
bO
f;l
bO
I II I I I
t 1
t 1
I t
t t
R
'$,
'6
(continued)
377
HD6303X,HD63A03X,HD63B03X----------------------Table 10 Accumulator, Memory Manipulation Instructions
Condition Code
Register
Addressing Modes
Operations
Mnemonic
IMMED.
OP
Shift Left
Arithmetic
-
#
DIRECT
op
-
INDEX
#
ASL
EXTEND
OP
-
#
OP
-
#
68
6
2
78
6
3
Booleanl
Arithmetic Operation
IMPLIED
op
-
#
M}
ASLB
58
1 1 A
1 1 8
Double Shift
Left. Arithmetic
ASLD
05
1 1
Shift Right
Arithmetic
ASR
Shift Right
LOOical
2
77
6
3
ASRA
47
1 1
ASRB
57
1 1
64
6
2
74
6
44
1 1
LSRB
54
1 1
1--
Subtract
04
-
A7
4
2
E7
4
2
ED 5
97
3
2
STAB
07
3
STD
DO 4
CO
2
2
DO
3
2
EO
2
FO
4
3
83
3 3 93 4 2 A3 5 2 B3 5 3
C2
2
2
Transfer
Accumulators
TAB
TBA
Test Zero or
Minus
TST
b7
0-.1
-
147
140 87
1 1
2
B2
4
3
A-M-C-A
02 3
2
E2
4
2
F2
4
3
B-M-C-B
16
17
70 4
40
TSTB
50
AIM
71
6
OR Immediate
OIM
72
EOR Immediate
ElM
Test Immediate
TIM
6
3 61
3 62
75
6
7B
4
7
1 1 A-B
1 1 B-A
M-OO
3
•
··· ·
•·
··· ···
·· ··
·· ··
·· · ··
·· ·· ·
·· ··
·· ··
·· ·· ·
·· ·· ·
·· ··
••
•
••
e
S S f)t
S S x
CE
load Index Reg
-----_._------ 8E
LOid Stack Pntr
- - - - - - -r -LOS
-----~
Slore Index Reg
STX
3 DE 4 2 EE 5 2 FE
---3 3 9E 4 2 Ae5 2 BE
OF 4 2 EF 5 2 FF
9F 4 2 AF 5 2 BF
3
IMPLIED
-
- ..
09
1
1
34
1
08
31
1
1
1 SP - 1- SP
1 X + 1- X
5 3
5
5
3
3
5
3
Bool•• nl
Arithmetic Oper.tion
OP
AC 5 2 BC 5 3
DEX
Decrement Stick Pntr
Increment Inde,,-~
Increment Stick Pntr
IMMED.
OP
Slore Stack Pntr
STS
Inriex Reg - Stack Pntr
TXS
35
St.ck Pntr - Index Reg
Add
Push Data
TSX
A8X
PSHX
30 1
3A 1
3C
5
Pull Oala
PULX
38
4
Exchange
XGDX
18
2
1
Condition Cod.
Regist.r
5
H
..
3 2 1 0
I N Z V C
••: l : l
l • •
•
••
•• l
X-M:M+l
X-l- X
1 SP+l-SP
M - XH. 1M + 11- XL_
M- SP H . IM+ll-SP L
XH - M. XL - 1M + 11
SP H - M.SP L - IM+lI
1 X-l-SP
1 SP+l-X
1 B + X- X
1
XL - M..,. SP - 1 XH- MIP • SP - 1 1 SP + 1 - SP. MIP SP + 1- SP.M..,-
SP
SP
XH
XL
·· ·· ·· · ··
··· · · · · ···
··· ·· · · · ···
··· ··· ··· ··· ··· ···
· · ··· ·
• ct
•
',1)
• 17
t
l
l
l
l
R
R
R
R
••••••
1 ACCD· ·IX
(Note) Condition Code Register will be explained in Note of Table 13.
Table 12 Jump, Branch Instructions
Condition Code
Register
5 4 3 2 1 0
H I N Z V C
Addressing Modes
Operations
Branch
Branch
Branch
Branch
Always
Never
If Carry Clear
If Carry Set
Branch
Branch
Branch
Branch
Branch
If = Zero
Mnemonic
-
RELATIVE DIRECT
OP
OP
- ..
- ..
~--r---
INDEX
OP
- ..
-
EXTEND
#
OP
-
----
IMPLIED
If Higher
If .; Zero
BlE
22
2F
BlS
23
3 2
BLT
BMI
20
2B
3 2
3 2
BNE
26
3 2
BVC
28
3 2
Branch If Overflow Sat
Branch If Plus
BVS
BPl
29
2A
3 2
3 2
Branch To Subroutine
Jump
BSR
JMP
80
5 2
Jump To Subroutine
JSR
No Operation
NOP
01
If
> Zero
> Zero
---"--If
Branch If lower Or
Same
Branch
Branch
Branch
Zero
Branch
Clear
If
< Zero
If Minus
If Not Equal
If OverflOW
Raturn From Interrupti
Return From
Subroutine
Software Interrupt
Wlit for Interrupt·
Sleep
(Note)
---
2C
2E
3
3
3
3
3
3
2
2
2
2
2
2
-
OP
BRA
BRN
BCC
BCS
BEC
BGE
BGT
BHI
20
21
24
25
27
Branch Test
#
None
None
c=o
C=1
Z =1
N ct> V = 0
Z + IN ct> VI = 0
C+Z=O
I Z + (N ct> VI = 1
3 2
3 2
3 2
I
-
C+Z=1
I
I
+
N@V=1
-N~l-------
--
Z=O
I
V=O
V=1
N=O
90 5
6E 3
2 AD 5
2
2
7E
3 3
BO 6 3
-
1 1
RTI
3B 10 1
RTS
39
SWI
WAI
3F 12 1
3E 9 1
lA 4 1
SLP
5
Advances Prog.
Only
1
Cn~r.
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
··· ··· ··· ··· ··· ···
·...· ·.. .· ·· ·•
·· ·· ···· ··• ··
·· ·· ·· ·· · ··
·· · · · ·
·· · ·· ·· ·· ··
·• • • ·• •· •·
--ct -S
1) •
• WAI puts R/Vil high; Address Bus goes to FFFF; Data Bus goes to the three state.
Condition Code Register will be explained in Note of Table 13.
~HITACHI
379
HD6303X,HD63A03X,HD63B03X-----------------------Table 13 Condition Code Register Manipulation Instructions
jAddreHinllModel
Operations
Mnemonic
CI_Carry
Claar Intarrupt Mask
CleerOverfiow
Set Carry
Set Interrupt Mask
Set Overflow
Accumulator A - CCR
CCR ... Accumulator A
IMPLIED
OP
#
ClC
Cli
ClV
SEC
SEI
OC
OE
OA
00
OF
SEV
TAP
TPA
OB
06
07
1
1
1
1
1
1
1
1
Condition Code
It)
(Bit V)
(21
(Bit C)
(3)
(Bit C)
(4) (Bit VI
~ (Bit VI
.'6'.
(Bit V)
~7)
(Bit NI
(8)
(All Bit)
(9;
(Bit II
(10)
(All Bitl
(Ii) (Bit C)
4
H
I
3
N
2
1
Z
V
0
C
R
R
a
a
S
R
0-1
a
O-V
l-e
I-I
I-V
A- CCR
CCR-A
1
1
1
1
1
5
·· · ·· ·· ·· ·
·· ·· ··· ··· ··
···· ·
······
O... C
1
1
1
LEGEND
OP Operation Code (Hexadecimal I
Number of MCU Cycles
Msp Contents of memory location pointed to by Stack Pointer
#
Number of Program Bytes
+
Arithmetic Plus
Arithmetic Minus
•
Boolean AND
+
Boolean Inclusive OR
e Boolean Exclusive OR
M Complement of M
~
Transfer into
OBit = Zero
00 Byte = Zero
(Notel
Condition Code Register
Boolean Operation
S
S
---@---
CONDITION CODE SYMBOLS
H
Half-carry from bit 3 to bit 4
I
Interrupt mask
N
Negative (sign bitl
Z
Zero (by tel
V
Overflow, 2's complement
C
Carry/Borrow from/to bit 7
R
Reset Always
S
Set Always
t Set if true after test or clear
•
Not Affected
Register Notes: (Bit set if test is true and cleared otherwise)
Test: Result = 1oo000oo?
Test: Result \ 00000000?
Test: BCD Character of high-order byte greater than 10? (Not cleared if previously sed
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
Test: Set equal to N~ C = 1 after the execution of instructions
Test: Result less than zero? (Bit 15=11
Load Condition Code Register from Stack.
Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exist the wait state.
Set according to the contents of Accumulator A.
Result of Multiplication Bit 7=1? (ACCB)
Table 14 OP-Code Map
OP
CODE
ACC
A
""--LOH
HII
__ ~O__ 0001
0010
LO ~
--,-- f---;-
°
0011
0100
-3--4
ACC
Eo/
BIND '/DIR' IMM
I
ACCA or SP
DIR liND
I
EXT
0101_~2~1-0~!.!.. ~_~~2~1011
r---5-6
7! 8 I 9 I A I B
IMM
I
ACCB or X
DIR
IND
T
I
EXT
1100j 1101_1 !11~Lll11
C
I
0 -TE-~-
°
0000
~ SBA
BRA
TSX
NEG
SUB
~~~~~N-O-P~~CB-A--~BR-N--~I-N-S--~_______
----~~r---A~I-M----~----------------~C~M~P~-----------------f-I
000'
0010
0011
LSRD ~ BCC
DES
LSR
AND
4
0100
0101
j..:...'---+-'---4_A_SLD
~ BCS
TXS
___
~'.~ _____ f---- ______________ . _______B_I_T_____________ .__._________ ~
TAP
TAB
BNE
.i>SHA -ROR
LOA
6
~1'0
--I---+-::T=-P-,--A-+-=T-::"BA--+--B--Eac:---+--p-,-SH-B::--+-----·-----A-=S-R:c--- ---=_=- k2:L~-==~~~,,=_~-=~==_~--STA -=-~-J0111
INX
XGDX BVe
PULX
ASL
EOR
8
1000
1001
·~:..;+-'-+-=C-:-:LV--+-=-SL:-:P:--+-=-BP:c:L-~A-,-B-=X--~------D'-E--:C:--------·---+- .
ORA
- - - - - - - - - - - .. ~
1010 A
~~I---+--S-=-EV--+--A-BA--+-BM-'---+-RT-'--+----_
-----==-r----cT-'-M-___
--+-------------A--D=-D::c--------------'a
1011 B
1100
C
~-=--=---i~+c:C_=_LC::__¥~______:::;r\__=_BG-E--_I__cPS-H-X+-- _ _ _':-:N-=C_____ ._-t---::c:::-T_ _C_PX---:-:c-=--_.___-t___~,____---L-D-D--==----- ~_
~~~·+--D-EX-+--D-A-A-+-BV-S--I---R-T-S-+-----------R-O-L----- . - - . - - - - - - - - - - - - ADC. -----------~
~f ~,---~C-,----I'~""----:;~B-LT-=-+M"C-U-L-+-----=-...---=TS..--T---.--- ~_U __ ~~___ ~F
SEI
~ BGT
~ BLE
_____S:~ ______ ~
~ ~~~___ Etf-~D-S_----I~-----~-e-!CLR
STS
~ I
STX
F
L-~-1--0--~-~--2-1--3--~--4-.-5-..--6--r,---7--- 8
9 I A I B
C I 0 I ElF
1111
·UNDEF'NED OP CODE
WAf
SWI
~
• Only each instructions of AIM, OIM, ElM, TIM
380
~HITACHI
------------------------HD6303X,HD63A03X,HD63B03X
• CPU OPERATION
• CPU Instruction Flow
When operating, the CPU fetches an instruction from a
memory and executes the required function. This sequence
starts with RES cancel and repeats itself limitlessly if not
affected by a special instruction or a control Signal. SWI, RTI,
WAI and SLP instructions are to change this operation, while
NMI, IRQ1, IRQ1, IRQ3, HALT and STBYare to control it.
Fig. 24 gives the CPU mode transition and Fig. 25 the CPU
system flow chart. Table IS shows CPU operating states and
port states.
• Operation at Each Instruction Cycle
Table 16 provides the operation at each instruction cycle.
By the pipeline control of the HD6303X, MULT, PUL, DAA
and XGDX instructions etc. prefetch the next instruction. So
attention is necessary to the counting of the instruction cycies
because it is different from the existent one ·····op code fetch
to the next instruction opcode.
Table 15 CPU Operation State and Port State
Port
Reset
STBY***
HALT
Sleep
Ao -A 7
Port 2
H
T
T
H
Keep
Do - D7
T
T
T
Keep
T
As -- AI5
Port 5
H
T
T
T
Keep
T
H
T
Keep
**
*
Port 6
Control
Signal
T
T
I
---
H ; High,
T
--
*
L; Low,
T
T
Figure 24 CPU Operation Mode Transition
-
T
I
T; High Impedance
• RD, WR, R/iii, OR = H, SA = L
•• RD, WR, R/Iii = T, LlR, SA = H
*. * E pin goes to high impedance state.
_HITACHI
381
w
co
I')
J:
C
en
~
w
X
":t:
c
en
~
o
w
X
":t:
cen
w
aJ
INotel 1. The program sequence will come to the RES start from
any place of the flow during RES. When STBY=O, the
sequence will go into the standby mode regardless of the CPU
condition.
2. Refer to "FUNCTIONAL PIN DESCRIPTION" for more
details of interrupts.
%
~
()
%
Figure 25 HD6303X System Flow Chart
oW
X
------------------------HD6303X,HD63A03X,HD63B03X
Table 16 Cycle-by-Cycle Operation
Address Mode 81
Instructions
Address Bus
Data Bus
IMMEDIATE
ADC
AND
CMP
LOA
SBC
AD DO
LDD
LOX
ADD
BIT
EOR
ORA
SUB
CPX
LOS
SUBD
1
2
Op Code Address + 1
Op Code Address + 2
1
1
0
0
1
1
1
2
1
1
1
0
0
3
Op Code Address + 1
Op Code Address + 2
Op Code Address+3
0
1
1
1
0
1
2
3
Op Code Address + 1
Address of Operand
Op Code Address+ 2
1
1
1
0
0
0
1
1
1
0
1
2
3
1
2
3
Op Code Address + 1
Destination Address
Op Code Address + 2
Op Code Address + 1
Address of Operand
Address of Operand + 1
Op Code Address + 2
Op Code Address + 1
Destination Address
Destination Address + 1
Op Code Address + 2
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Jump Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
Address of Operand
FFFF
Address of Operand
Op Code Address + 3
1
1
0
Operand Data
Next Op Code
2
3
1
1
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
DIRECT
ADC
AND
CMP
LOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
3
3
ADDD
LDD
LOX
CPX
LOS
SUBD
STD
STX
STS
4
4
4
1
2
3
4
1
2
JSR
5
3
4
5
---,-
TIM
4
2
3
4
AIM
OIM
ElM
6
1
2
3
4
5
6
1
1
0
1
0
1
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
1
0
1
1
1
0
0
1
1
0
1
1
1
1
1
1
0
1
0
Address of Operand (LSB)
Operand Data
Next Op Code
Destination Address
Accumulator Data
Next Op Code
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Next Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
(Continued)
_HITACHI
383
Address Mode &
Instructions
Address Bus
Data Bus
INDEXED
JMP
3
- -ADC--AND
CMP
LOA
SBC
TST
---.--
ADD
BIT
EOR
ORA
SUB
- 1--------
4
----
lilA-
4
1
2
3
-,-2
3
4
-r- - ap- Code-"ddress-H -2
3
4
ADDD
CPX
lOS
SUBD
STD
STX
LDD
LOX
5
1
2
3
4
5
STS
5
1
2
3
4
5
JSR
5
1
2
3
4
5
ASL
COM
INC
NEG
ROR
ASR
DEC
LSR
ROL
6
TIM
5
1
2
3
4
5
6
1
2
3
4
5
CLR
5
1
2
3
4
5
AIM
OIM
1
2
3
ElM
7
Op Code Address + 1
FFFF
Jump Address
--Op Code Address + 1
FFFF
IX + Offset
Op Code Address+2
4
5
6
7
FFFF
IX + Offset
Op Code Address+2
Op Code Address + 1
FFFF
IX + Offset
IX+Offset+ 1
Op Code Address + 2
Op Code Address + 1
FFFF
IX + Offset
IX+Offset+1
Op Code Address + 2
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
IX + Offset
Op Code Address+ 1
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address + 1
Op Code Address + 1
Op Code Address + 2
FFFF
IX + Offset
Op Code Address + 3
Op Code Address + 1
FFFF
IX + Offset
IX + Offset
Op Code Address + 2
Op Code Address+ 1
Op Code Address + 2
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address + 3
1
1
1
1
1
1
1
---
---T1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
0
0
1
0
0
O
1
1
0
u
1
0
0
0
u
1
1
1
0
0
1
1
1
0
0
1
0
1
1
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
1
0
1
0
1
0
Offset
Restart Address (LSB)
First Op Codeo!~ump~t~_
Offset
Restart Address (LSB)
Operand Data
Next Op Code
-Offset----------- ----Restart Address (LSB)
Accumulator Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data
-~----
00
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Opera!l'f'Data
Next OP Code
(Continued)
384
$
HITACHI
------------------------HD6303X,HD63A03X,HD63B03X
Address Mode 8&
Instructions
Cycle
:I
I
i Cycles
Address Bus
Data Bus
EXTEND
JMP
3
!
!
- "DC'ADD
AND BIT
CMP EOR
LOA ORA
SUB
SBC
3
-tsf f
1
2
3
4
j-
L
2
3
4
t
LDD
LOX
srb
sts
j
5
'~
STX
5
4
1
2
3
4
5
1
2
3
4
Op Code Address + 1
Op Code Address+2
!
1
1
I
Op Code Address + 2
Address of Operand
Op Code Address+3
,1
!
1
!
1
I
I
!
'--Op'COdeAddreSs+'-Op Code Addless+2
Destination Address
; Op Code Address + 3
,
+- Oi)-'COdeAddress+T
Op Code Address+2
Address of Operand
Address of Operand + 1
! Op Code Address + 3
I--OpCodeAddress+f
Op Code Address + 2
Destination Address
: Destination Address + 1
-ASe
COM
INC
NEG
ROR
-ASR
DEC
LSR
ROL
6
- CLR"
'I Op Code Address + 2
I Address of Operand
45
I AFFdFdFress of Operand
6
1
2
3
4
5
Op Code Address+3
+-Op CodeAddress+ j
Op Code Address+2
I Address of Operand
Address of Operand
Op Code Address + 3
I
1.
I
-1'~
Jump Address (MSB)
Jump Address (LSB)
1
1
(MSB) Address of Operand (LSB)
Operand Data
Next Op Code
- --
0
:
1
I
1:
0
1
1
(j)
1
1
0
1
1
0
1
-,- ~,-0- , 1
0
1
0
1
0
0
1
0
,+--
-
--,--1-!
0
Destmation-AddressIMSB)Destination Address (LSB)
Accumulator Data
Next Op Code
T - -1------0- - , ----,- -Addrljss~ofOpe':an(nMSB)
1
1
1
Address of Operand (lSB)
Operand Dafa (MSB)
Operand Data (LSB)
Next Op Code
DestmatlOn Address(MSB)
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
0
0
1
1
1
1
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
1
1
1
1
Address of Operand (LSB)
Operand Data
~ ,-~- -~-
0
2
3
5
1
1
0 - '-1-'0
1
1
1
0
1
0
1
0
1
1
FFFF
Stack Pointer
i
,Stack Pointer-1
+-
!
1
1
1
4
5
i
i
1
0
0
i
i
1
1
1
0
---'t,-- ,-+-{--~-~mgo~~A~~esS+T
i
0
0
0
1:
I
I
1
1
i Op Code Address+2
2
3
6
0
-+ '-j~~I:
I
- -+ -~~--~-~ ~~ -g~i-~~~~::: ~
;
0
j~~mgo~t:~~ess+j-- +-H~g- ~~- ~ --~~-~+e~~-;r~:erand
4
-5TA
"ADDD
CPX
LOS
SUBD
!
1
1
1
1
1
0
r--,----
r+ ~~~i)~td~~~:-(MSB)
--
+-t+ -+-- -~- -~r.:r::~:C;u~~ra~d~Md;Bf
1
o
1
1
1
1
0
1
0
1
1
1
1
0
1
0
1
0
:-O-~ - 1 - r----,0
1
1
0
1
1
1
0
1
0
1
0
I
Restart Address (LSB)
New Operand Data
Next Op Code
Add'ress ofOperand (M'SB)
Address of Operand (LSB)
Operand Data
00
Next Op Code
(Continued)
_HITACHI
385
HD6303X,HD63A03X,HD63B03X----------------------Address Mode S.
Instructions
IMPLIED
ABA
ASL
ASR
CLC
CLR
COM
DES
INC
INX
LSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
DAA
PULA
ABX
ASLD
CBA
CLI
CLV
DEC
DEX
INS
LSR
R(l)L
NOP
SEC
SEV
TAP
TPA
TSX
XGDX
1
Op Code Address + 1
1
0
1
0
1
2
1
2
Op Code Address + 1
FFFF
Op Code Address + 1
FFFF
Stack Pointer + 1
Op Code Address + 1
FFFF
Stack Pointer
Op Code Address + 1
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Op Code Address + 1
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Return Address
Op Code Address + 1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
1
1
0
1
1
0
Next-Op--Code----- ------
1
1
0
1
1
1
1
1
1
0
1
1
1
1
Restart Address_(L_~~!. ___
Next Op Code
Restart Address (LSB)
Data from Stack
Next Op Code
Restart Address (lSB)
Accumulator Data
Next Op Code
Next Op Code
Restart Address (LSB)
Data from Stack (MSB)
Data from Stack (LSBI
-Next Op cOdi!------
Next Op Code
1
2
PULB
3
3
PSHA
Data Bus
Address Bus
PSHB
4
PULX
4
1
2
3
4
1
2
3
4
1
2
PSHX
5
3
4
5
1
RTS
2
5
3
4
5
1
MUL
2
3
7
4
5
6
7
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
Restart Address (LSBI
Index Register (LSBI
Index Register (MSBI
Next Op Code
Next Op Code
Restart Address (LSBI
Return Address (MSBI
Return Address (LSBI
First Op Code of Return Routine
Nexd)pCOde---- - .- - -Restart
Restart
Restart
Restart
Restart
Restart
Address
Address
Address
Address
Address
Address
(LSBI
(LSBI
(LSB)
(lSBI
(LSBI
(LSBI
(Continued)
386
$
HITACHI
------------------------HD6303X,HD63A03X,HD63B03X
Address Mode 8t
Instructions
Data Bus
Address Bus
IMPLIED
WAI
I
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer +3
Stack Pointer+4
Stack Pointer + 5
I Stack Pointer+6
,Stack Pointer + 7
I Return Address
! Op Code Address + f-~~-
1
1
1
1
1
1
1
1
1
"
2
3
4
5
6
7
8
9
10
I FFFF
! Stack Pointer
,Stack Pointer-1
I Stack Pointer - 2
! Stack Pointer-3
i Stack Pointer-4
i Stack Pointer-5
i Stack Pointer -6
Vector Address FFFA
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1!
1
1
I
1
II
1
1 ~'
11
12
I Vector Address FFFB
I
Address of SWI Routine
1
1
0
0
1
1
1
0
FFFF
1
1
1
1
I Restart Address (LSB)
1
1I
1
11
II
i
I
9
II
r
I
..~
I
i
I
i
--~ .·-~·21
I
10
I
,
I
I
•
n
--~--
t
r-;!
!
i
i
I
,
!
12
Op Code Address + 1
3
4
5
6
7
8
9
10
i,
1
2
3
4
5
6
7
8
9
!
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
I
i
!
1
1
1
0
0
0
0
0
0
0
0FFPFFcOde~Adi:tress+T--~ 1-. 11
I FFFF
[' Stack
Star.k
'Stack
,Stack
! Stack
i Stack
I Stack
,I
Pointer
Pointer-1
Pointer - 2
Pointer-3
Pointer-4
Pointer - 5
Pointer - 6
I
I
I
I
OP
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
I
4
RELATIVE
BCC
BEQ
BGT
BLE
BLT
BNE
BRA
BVC
BSR
BCS
BGE
BHI
BLS
BMT
BPL
BRN
BVS
3
)
1
Sleep
3
4
FFFF
Op Code Address + 1
1
1
1
0
1
1
01
1
2
Op Code Address + 1
FFFF
r Branch Address'· .... Test=·l"
lop Code Address+l .. ·Test=·O"
1
1
0
1
1
1
1
1
1
0
1
0
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Branch Address
1
1
0
0
1
0
1
1
1
0
1
1
0
0
1
1
1
1
1
0
3
I
I
1
2
5
3
4
5
.,.HITACHI
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)
. Addre..ss of SWI RO.. u.t.ine.(L.SB)
First Op Code of SWI Routine
-Next Op Code- - .~- - -----
--=S,.,-L"'P------+---"11---::-+-:::--=C-od-:"e--:-A-:"dd-:"r-e-ss-+:-1=----+--,1:--+--0"---+-~1-+--'1;--
2
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Next Op Code
.
Restart Address (LSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index Register (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code·---~
I
Restart Address (LSB)
Next Op Code
Branch Offset
Restart Address (LSB)
First Op Code of Branch Routine
Next Op Code
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Op Code of Subroutine
387
HD6303Y ,HD63A03Y ,
HD63B03Y
CMOS MPU (Micro Processing
Unit)
-ADVANCE INFORMATIONThe HD6303Y is a CMOS 8·bit micro processing unit which
contains a CPU compatible with the HD6301Vl, 256 bytes of
RAM, 24 parallel I/O Pins, Serial Communication Interface
(SCI) and two timers.
•
•
•
•
•
•
•
•
•
FEATURES
Instruction Set Compatible with the HD6301 Family
Abundant On·chip Resources
• 256 Bytes of RAM
• 24 Parallel I/O Pins
• Handshake Interface (Port 6)
• Darlington Transistor Direct Drive (Port 2, 6)
• l6·bit Programmable Timer
1 Input Capture Register
1 Free Running Counter
(
2 Output Compare Registers
• 8·Bit Reloadable Timer
1 8·bit Up Counter
( 1 Time Constant Register
• Serial Communication Interface
Asynchronous Mode
8 Transmit Formats
( Hardware Parity
Clocked Synchronous Mode
Interrupt - 3 External, 7 Internal
CPU Functions
• Memory Ready, Auto Memory Ready
• Halt
• Error Detection
(Address Trap, Op·code Trap)
Up to 65k Bytes Address Space
Low Power Dissipation Mode
• Sleep
• Standby (Hardware Set, Software Set)
Wide Range of Operation
Vee=3t06V
(f=O.l to 0.5 MHz)
f = 0.1 to 1.0 MHz; HD6303Y )
Vee = 5V ± 10%
f = 0.1 to 1.5 MHz; HD63A03Y
(
f = 0.1 to 2.0 MHz; HD63B03Y
Minimum Instruction Cycle Time: 0.5 tJs (f = 2.0 MHz)
388
$
HD6303YP, H D63A03YP,
HD63B03YP
(DP-64S)
HD6303YF, HD63A03YF,
HD63B03YF
(FP-64)
HITACHI
o
o
H 6303Y, HD63A03Y, H 63B03Y
•
PIN ARRANGEMENT
• HD6303YP, HD63A03YP, HD63B03YP
•
HD6303YF, HD63A03YF, HD63B03YF
VSS
XTAl
AD
EXTAl
WR
I~Iii III>:t
Ii:
~
0
4.
~
-'
c(
~
~
-'
c(
~
)(
::
w
I~
I~ I~ a:
r5
c(
II>
1 R/W
em
0.
BA
STBY
0.
NMi
0,
O.
0,
0,
Pu
OJ
Pn
OJ
O.
D.
Os
D.
51 D.
A.
Pez
7
P'3
B
0.
Pl.
D.
Pl.
A.
p.~
A.
p.,
A,
7 A,
P'l
AJ
A.
P"
A.
P ••
A.
A.
A,
p..
O.
p ..
"'-
P ••
A.
P5 ,
Vss
A.
P60
"'-
A,.
P61
A.
p••
A..
PIS
A ..
P .. 31
AIS
P'J 32
Vee
u
4.
4.
4.
4.
4.
4.
~
c(
«
.c
.(
.(
.(
(Top View)
(Top View)
_HITACHI
389
HD6303Y,HD63A03Y,HD63B03Y'----------------------• BLOCK DIAGRAM
VCC---V55
V S5
rD1
~
~
P 10 (Tin)
x
a::
Pl. (Tout.)
Pn(SCLK)
P13 (Rx)
P'4(Tx)
P 15 (Tout,)
P l , (Tout])
Pz7 (TCLK)
aa::
0
0
N
J J J J J
...J
...J
!
RD
WR
x
w
CPU
R/W
LlR
BA
N
~
~
a::
:.
a::
0
0
0.
0.
A
....
.....-
----
'---
....
a::
w
:E
V
A
'"
..
i=
t--t--t--III
t--iii
:I
III t--!!!IV f--0 f---
...
£:I
I
If
r-----
U
(I)
it
!.--
.....-
I'\.'I
...
iii
:I
III
a::
W
:E
i=
v
1'\
P'3P'4P'5P66 P'7-
390
v
j
a::
0.
U= 5 XTAL
HDS:105XO
MCU
10-22pF±20%
Crystal Oscillator
HD6305XO
MCU
-RESET
The MCV can be reset either by external reset input (RES)
or power-on reset. (See Fig. 13.) On power .uP, the reset
input must be held "Low" for at least tose to assure that the
internal oscillator is stabilized. A sufficient time of delay can
be obtained by connecting a capacitance to the RES input as
.
shown in Fig. 14.
External
Ceramic Oscillator
Clock
Input 6 EXTAL
NC 5 XTAL HD6305XO
MCU
5V
Vee
OV------External Clock Drive
RES
Terminal
~~~al
--------f""
____________________
Figure 15
Internal Oscillator Circuit
c,
~
C:y'
s
Figure 13
AT Cut
Parallel
Resonance
Co=7pF max.
EXTAL
f=2.0-S.0MHz
6
Rs=600 max.
Power On and Reset Timing
XTAL
5
Co
Figure 16 Parameters of Crystal
2
Vec--'V'I/Iv--+----,
100kSl typ
RES
-:;;;. 2.2/IF
HD6305XO
(a)
MCU
Figure 14 Input Reset Delay Circuit
-INTERNAL OSCILLATOR
The internal oscillator circuit is designed to meet the
requirement for minimum external configurations. It can be
driven by connecting a crystal (AT cut 2.0 - 8.0MHz) or
ceramic oscillator between pins 5 and 6 depending on the required oscillation frequency stability.
Three different terminal connections are shown in Fig. IS.
Figs. 16 and 17 illustrate the specifications and typical arrangement of the crystal, respectively.
[NOTE] Use as short wirings as possible for connection of the crystal
with the EXTAL and XTAL terminals. Do not allow these
wirings to cross others.
~HITACHI
Figure 17 Typical Crystal Arrangement
407
HD6305XO,HD63A05XO,HD63B05XO----------------------LOW POWER DISSIPATION MODE
The HD6305XO has three low power dissipation modes:
wait, stop and standby.
• Wait Mode
When WAlT instruction being executed, the.,CU enters
into the wait mode. In this mode, the oscillator stays active
but the internal clock stops. The CPU stops but the peripheral
functions - the timer and the serial communication interface - stay active. (NOTE: Once the system has entered the
wait mode, the serial communication interface can no longer
be retriggered.) In the wait mode, the registers, RAM and I/O
terminals hold their condition just before entering into the
wait mode.
The escape from this mode can be done by interrupt (INT,
TIMER/INT2 or SCI/TIMER2), RES or STBY. The RES
resets the MCU and the STBY brings it into the standby
mode. (This will be mentioned later.)
When interrupt is requested to the CPU and accepted, the
wait mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt routine. If the interrupt is
masked by the I bit of the condition code register, after releasing from the wait mode the MCU executes the instruction
next to the WAIT. If an interrupt other than the INT (Le.,
TIMER/INT2 or SCI/TIMER2) is masked by the timer control
register, miscellaneous register or serial status register, there
is no interrupt request to the CPU, so the wait mode cannot
be released.
Fig. 18 shows a flowchart for the wait function.
• Stop Mode
When STOP instruction being executed, MCU enters into
the stop mode. In this mode, the oscillator stops and the CPU
and peripheral functions become inactive but the RAM,
registers and I/O terminals hold their condition just before
408
entering into the stop mode.
The escape from this mode can be done by an external
interrupt (INT or INTi), RES or STBY. The RES resets the
MCU and the STBY brings into the standby mode.
When interrupt is requested to the CPU and accepted,
the stop mode escapes, then the CPU is brought to the operation mode and vectors to the interrupt routine. If the interrupt is masked by the I bit of the condition code register,
after releasing from the stop mode, the MCU executes the
instruction next to the STOP. If the INTl interrupt is masked
by the miscellaneous register, there is no interrupt request to
the MCU, so the stop mode cannot be released.
Fig. 19 shows a flowchart for the stop function. Fig. 20
shows a timing chart of return to the operation mode from
the stop mode.
For releasing from the stop mode by an interrupt, oscillation starts upon input of the interrupt and, after the internal
delay time for stabilized oscillation, the CPU becomes active.
For restarting by RES, oscillation starts when the RES goes
"0" and the CPU restarts when the RES goes "1". The duration of RES="O" must exceed tose to assure stabilized oscillation.
• Standby Mode
The MCU enters into the standby mode when the STBY
terminal goes "Low". In this mode, all operations stop and
the internal condition is reset but the contents of the RAM are
hold. The I/O terminals turn to high-impedance state. The
standby mode should escape by bringing STBY "High". The
CPU must be restarted by reset. The timing of input signals
at the RES and STBY terminals is shown in Fig. 21 .
Table 4 lists the status of each parts of the MCU in each
low power dissipation modes. Transitions between each mode
are shown in Fig. 22.
_HITACHI
----------------------HD6305XO,HD63A05XO,HD63B05XO
Oscillator Active
Timer and Serial
Clock Active
All Other Clocks
Stop
Initialize
CPU, TIMER, SCI,
10 and All
. Other Functions
No
No
load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 18 Wait Mode Flowchart
_HITACHI
409
HD6305X~HD63A05XO.HD63B05XO~~~~~~~~~~~~~~~~~~~~~-
Oscillator and
All Clocks Stop.
No
Turn on Oscillator
Wait for Time Delay
to Stabilize
Turn on Oscillator
Wait for Time Delay
to Stabilize
1=0
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 19 Stop Mode Flowchart
410
_HITACHI
----------------------HD6305XO,HD63A05XO,HD63B05XO
Oscillator
E
111111111"" I" 111111111111
M11f111111111111111111111111111111111111111111111111111111I11
(
~~~~
t
stabilized (built-in delay time)
Interrupt
STOP instruction
executed
restart
(a) Restart by Interrupt
Oscillator 11111111111111111111111111111
E
Time required for oscillation to become
stabilized (toscl
STOP instruction
executed
Reset
start
(b) Restart by Reset
Figure 20 Timing Chart of Releasing from Stop Mode
\
I
~~
i
I
I
I
'-_oA_-'- __ I'
I
I
I
\
tosc
Figure 21
Table 4
Start
Mode
WAIT
Software
STOP
Standby
Hardware
Restart
Timing Chart of Releasing from Standby Mode
Status of Each Part of MCU in Low Power Dissipation Modes
Condition
Timer,
Register
Serial
Escape
RAM
1/0
terminal
Keep
Keep
Keep
STBY, RES, INT, IN/2,
each interrupt request of
TIMER, TIMER 2 , SCI
Stop
Keep
Keep
Keep
STBY, RES, INT, INT2
Stop
Reset
Keep
High impedance
Oscillator
CPU
WAIT instruction
Active
Stop
Active
STOP instruction
Stop
Stop
STBY="Low"
Stop
Stop
_HITACHI
STBY="High"
411
HD6305XO,HD63A05XO,HD63B05XO----------------------
Figure 22
Transitions among Active Mode, Wait Mode,
Stop Mode, Standby Mode and Reset
-BIT MANIPULATION
The HD6305XO MCV can use a single instruction (BSET
or BCLR) to set or clear one bit of the RAM or an I/O port
(except the write-only registers such as the data direction
register). Every bit of memory or I/O within page 0 ($00 ,..,
$FF) can be tested by the BRSET or BRCLR instruction;
depending on the result of the test, the program can branch to
required destinations. Since bits in the RAM, or I/O can be
manipulated, the user may use a bit within the RAM as a flag
or handle a single I/O bit as an independent I/O terminal.
Fig. 23 shows an example of bit manipulation and the validity
of test instructions. In the example, the program is configured
assuming that bit 0 of port A is connected to a zero cross
detector circuit and bit I of the same port to the trigger of a
triac.
The program shown can activate the triac within a time of
IO#ls from zero-crossing through the use of only 7 bytes on
the ROM. The onw
Branch IF Interrupt Line
is High
BIH
2F
2
3
INT=1
Branch to Subroutine
BSR
AD
2
5
--
H
I
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
. Table 8 Bit Manipulation Instructions
Operations
Branch IF Bit n is set
Branch IF Bit n is clear
Set B~t n
Clear Bit n
Addressing Modes
Bit Test and
Bit Set/Clear
OP
OP
# .-.BRSET n(n=0···7)
2·n
-- 01+2·n
BRClR n(n=0 .. ·7)
-BSET n(n=0 .. ·7)
10+2·n 2 5
-'BClR n(n =0.. ·7)
11 +2·n 2 5
Mnemonic
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
418
~HITACHI
Boolean/
Branch Arithmetic
# - Operation
3
3
5
5
-
--
--
-
-
1---Mn
O---Mn
Branch
Test
Condition Code
H
Mn=1
Mn=O
-
I
N
Z
C
• • • •
• • • •
• • • • •
• • • • •
1\
1\
----------------------HD6305XO,HD63A05XO,HD63B05XO
Table 9
Control Instructions
Addressing Modes
Operations
Mnemonic
Implied
Condition Code
Boolean Operation
OP
#
-
97
1.
X ...... A
H
Transfer A to X
TAX
Transfer X to A
TXA
9F
1
2
2
Set Carry Bit
SEC
99
1
1
1......C
Clear Carry Bit
CLC
98
1
1
O-C
Set Interrupt Mask Bit
SEI
9B
1
Clear Interrupt Mlask Bit
CLI
9A
1
2
2
0-1
Software Interrupt
SWI
83
1
10
Return from Subroutine
RTS
81
1
5
Return from Interrupt
RTI
80
1
8
Reset Stack Pointer
RSP
9C
1
2
$FF-SP
No-Operation
NOP
90
1
1
Advance Prog. Cntr. Only
Decimal Adjust A
OAA
80
1
STOP
8E
1
WAIT
8F
1
2
4
4
Converts binary add of BCD charcters into
BCD format
Stop
Wait
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
I
• •
• •
• •
• •
• 01
• 1
A ......X
1-1
• •
• • •
• • •
/\
Mnemonic
Immediate
Direct
x
x
x
x
x
x
x
x
x
x
x
x
X
x
x
x
x
X
X
X
X
Indexed
(16-Bit)
Set!
Clear
X
X
/\
X
x
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
x
X
X
X
x
X
X
x
X
X
X
X
X
BlS
BMC
BMI
X
X
X
BMS
BNE
BPL
BRA
X
X
x.
X
H
1\
X
BIH
Bil
Bit
Test &
Branch
X
X
BHCC
BHCS
BHI
(BHS)
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
/\
/\*
Condition Code
Indexed
Indexed
Extended Relative (No Offset) (S-Bit)
BCS
BEQ
BIT
(BlO)
• •1
•
• 0
• •
• •
• •
•? •?
• •
• •
• •
• •
Instruction Set (in Alphabetical Order)
Bit
ASR
BCC
BClR
• •
• •
•? •? •?
• • •
• • •
Addressing Modes
ADC
ADD
AND
ASL
Z C
•
•
•
•
•
•
* Are BCD characters of upper byte 10 or more? (They are not cleared if set in advance.)
Table 10
Implied
N
X
X
I
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
Z
C
1\
1\
1\
/\
/\
/\
/\
/\
•
/\
/\
/\
/\
/\
/\
• • •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
/\
• •
• •
• •
• •
• •
• •
• •
• •
• •
•
• •
• •
• •
• •
• •
• •
• •
••
/\
(to be continued)
C
/\
•?
Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
_HITACHI
419
HD6305XO,HD63A05XO,HD63B05XO---------------------Table 10 Instruction Set (in Alphabetical Order)
Addressing Modes
Condition Code
Bit
Indexed
Mnemonic
Implied
Immediate
Direct
Extended Relative (No Offset)
BRN
Bit
Indexed
Indexed
Setl
Test &
(S-Bit)
(18-Bit)
Clear
Branch
X
BRCLR
X
BRSET
X
BSET
X
BSR
X
CLC
X
CLI
X
CtR
X
CMP
COM
X
X
CPX
X
DEC
X
EOR
X
X
X
DAA
INC
X
X
X
X
X
X
X
X
X
X
JMP
X
JSR
X
X
X
X
X
X
X
X
X
X
X"
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
LOA
X
X
X
X
X
X
LOX
X
X
X
X
X
X
LSL
X
X
X
X
LSR
X
X
X
X
NEG
X
X
X
X
NOP
x
x
x
x
x
x
x
ORA
RSP
x
x
x
RTI
X
RTS
x
ROL
ROR
x
x
x
X
x
x
SBC
SEC
X
SEI
x
STA
STOP
x
SUB
x
x
x
x
X
x
X
X
X
X
X
X
X
X
x
X
X
X
X
X
X
TAX
X
TST
X
TXA
X
WAIT
X
Condition Code Svmbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
420
X
x
x
STX
SWI
x
X
C
1\
•
Carry /Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
eHITACHI
H
I
N
Z
C
• • • • •
• • • •
• • • •
• • • • •
• • • • •0
1\
1\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•
•
•
•
•
•0 •
•
• 0
•
•
•
•
•
•
•
• •
• •
•
•
• 0
•
•
• •
•
•
•
• •
? ?
• •
•
•1 •
•
•
•1 •
•
1\
1\
1\
1\
1
1\
1\
1\
1\
1\
1\
1\
/\
1\
1\
,\
1\
1\
1\
/\
/\
1\
•
•
•
• •
• •
•
•
/\
/\
1\
1\
/\
/\
,\
,\
1\
/\
1\
/\
/\
1\
/\
/\
• •
•
•
?
•
•
•
•
• • •
•
•1
• •
• • •
•
• • •
• • •
/\
1\
/\
1\
1\
/\
1\
1\
1\
/\
•
?
•
/\
1
•
•
•
•
•
•
•
•
1\
•
---------------------------------------------HD6305XO,HD63A05XO,HD63B05XO
Table 11 Operation Code Map
Bit Manipulation
Test &
Set/
Branch
Clear
0
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F
0
1
BRSETO
BRClRO
BRSETl
BRClR1
BRSET2
BRClR2
BRSET3
BRClR3
BRSET4
BRClR4
BRSET5
BRClR5
BRSET6
BRClR6
BRSET7
BRClR7
3/5
BSETO
BClRO
BSET1
BClR1
BSET2
BClR2
BSET3
BClR3
BSET4
BClR4
BSET5
BClR5
BSET6
BClR6
BSET7
BClR7
2/5
(NOTES)
Branch
Rei
2
BRA
BRN
BHI
BlS
BCC
BCS
BNE
BEQ
BHCC
BHCS
BPl
BMI
BMC
BMS
Bil
BIH
2/3
Read Modify Write
OIR
3
Register Memory
Control
.XO IMP IMP IMM OIR EXT .X2 .Xl .XO
B
C
D
F --;-H IGH
7
A
E
8
9
RTI"
SUB
0
RTS"
CMP
1
SBC
2
SWI"
COM
CPX
3 l
o
AND
4 W
lSR
BIT
5
ROR
lOA
6
TAX"
5TA(+11 7
ASR
STA
lSl ASl
ClC
EOR
8
ROl
SEC
AOC
9
DEC
ORA
A
CLI*
ADD
B
SEI*
RSP"
JMP(-l)
INC
C
TST
TST(-l) OAA" NOP BSR" JSR(+2) JSR(+l) JSR(+2) 0
STOP' lOX
E
WAIT' TXA"
5TX(+11 F
ClR
STX
2 I 12 2 6 1 5 1 " 1 1 2.'2 2.3 3/4 3/5 2/4 1 /3
A
4
X ,Xl
5
6
NEG
-
T5TI-I)
25
1
I. "-" is an undefined operation code.
2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles).
The number of cycles for the mnemonics asterisked (*) is as follows:
RTI
8
TAX
2
RTS
5
RSP
2
SWI
10
TXA
2
DAA
2
BSR
5
4
~I
2
WAIT
4
SEI
2
3. The parenthesized numbers must be added to the cycle count of the particular instruction.
srop
• Additional Instructions
The following new instructions are used on the HD6305XO:
DAA Converts the contents of the accumulator into BCD
code.
WAIT Causes the MCU to enter the wait mode. For this mode,
see the topic, Wait Mode.
STOP Causes the MCU to enter the stop mode. For this mode,
_HITACHI
see the topic, Stop Mode.
421
HD6305X1 ,HD63A05X1 ,HD63B05X1
HD6305X2, HD63A05X2, HD63B05X2
CMOS MCU (Microcomputer Unit)
-PRELIMINARYThe HD6305XI and the HD6305X2 are CMOS versions of
the HD6805XI and. the HD6805X2, which are NMOS 8·bit
single chip microcomputers. A CPU, a clock generator, a 128byte RAM, I/O terminals, two timers and a serial communication interface (SCI) are built in both chip of the HD6305Xl
and the HD6305X2. Their memory spaces are expandable to
16k bytes externally.
The HD6305XI and the HD6305X2 have the same functions
as the HD6305XO's except for the number of I/O terminals.
The HD6305X 1 has a 4k byte ROM and its memory space is
expandable to 12k bytes externally. The HD630SX2 is a microcomputer unit which includes no ROM and its memory space
is expandable to 16k bytes externally.
• HARDWA~E FEATURES
.8·bit based MCU
.4k·bytes of internal ROM (HD6305Xl)
No internal ROM (HD6305X2)
• 128·bytes of RAM
• A total of 31·terminals, including 24 I/O's, 7 inputs
• Two timers
- 8·bit timer with a 7·bit prescaler (programmable prescaler;
event counter)
- 15·bit timer (commonly used with the SCI clock divider)
• On-chip serial interface circuit (synchronized with clock)
.Six interrupts (two external, two timer, one serial and one
software)
• Low power dissipation modes
- Wait .... In this mode, the clock oscillator is on and the
CPU halts but the timer/serial/interrupt func·
tion is operatable.
- Stop .... In this mode, the clock stops but the RAM
data, I/O status and registers are held.
- Standby .. In this mode, the clock stops, the RAM data
is held, and the other internal condition is
reset.
• Minimum instruction cycle time
- HD6305Xl/X2 .. 11ls (f = 1 MHz)
- HD63A05Xl/X2 .. 0.671ls (f = 1.5 MHz)
- HD63805Xl/X2 .. 0.51ls (f =2 MHz)
• Wide operating range
Vce = 3 to 6V (f = 0.1 to 0.5 MHz)
- HD6305Xl/X2 .. f =0.1 to 1 MHz (VCC =5V ± l()o~)
- HD63A05Xl/X2 .. f 0.1 to 1.5 MHz (VCC 5V ± l()o~)
- HD63805Xl/X2 .. f =0.1 to 2 MHz (VCC =5V ± l()O~)
.System development fully supported by an evaluation kit
=
422
=
$
HD6305X1P, HD63A05X1P,
HD63805X1P, HD6305X2P,
HD63A05X2P, HD63805X2P
H D6305X 1F, H D63A05X 1F,
HD63805X1F, HD6305X2F,
HD63A05X2F, HD63805X2F
(FP·64}
• SOFTWARE FEATURES
.Similar to HD6800
• Byte efficient instruction set
• Powerful bit manipulation instructions (8it Set, Bit Clear, and
8it Test and 8ranch usable for all RAM bits and all I/O termi·
nals)
• A variety of interrupt operations
• Index addressing mode useful for table processing
• A variety of conditional branch instructions
• Ten powerful addressing modes
.Ail addressing modes adaptable to RAM, and I/O instructions
• Three new instructions, STOP, WAIT and DAA, added to the
HD6805 family instruction set
• Instructions that are upwar-d compatible with those of Moto·
rola's MC6805P2 and MCl46805G2
HITACHI
HD6305X1,HD6305X2
• PIN ARRANGEMENT
•
•
HD6305X1P, HD63A05X1P, HD63B05X1P, HD6305X2P,
HD63A05X2P, HD63B05X2P
Vs~~ 0
DATAo
DATA,
DATA 2
DATA,
DATA.
DATA,
DATA,
DATA 7
REs'C
INT
STBy F
XTAL
EXTAL
NUM
TIMER
A7
A,
A,
A.
A,
51
B7
B,
8,
B.
B3
B2
B,
Bo
C7/T.
C,/Rx
C,/CK
C.
DATA 7
E
R/W
R/W
ADR'3
ADR'2
ADR"
ADR,O
ADR g
ADRe
ADR1
ADR6
ADR~
ADR.
ADR3
ADR2
07
ADR,
D,/iN'f;
ADRo
C7 /Tx
C 6 /Rx
0,
D.
03
C3
C2
DATAs
E
ADR"
ADR12
ADR"
ADR,o
ADA,
ADR,
ADR7
ADR,
ADR,
ADR.
ADR,
ADR2
ADR,
ADRo
A2
A,
Ao
C,
Co
HD6305X1F, HD63A05X1F, HD63B05X1F, HD6305X2F,
HD63A05X2F,H063B05X2F
01
02
0,
~
..
.. u
~______________. - Vee
U U U u0 uu 0 0 0 0 is
>
U
(Top View)
0
(Top View)
• BLOCK DIAGRAM
XTAl EXTAl
E
I~
Rlii
TIMER
110
Terminals
CPU
Index
PoftA
e
Register
Control
x
Condition Code
Register
cc
D,
D....iNT,
D,
D.
03
CPU
g~
Port 0
Input
Terminals
Stack
6
Pointer
sp
Program
Counter
Poft B
1/0
Terminals
6
"High"
PCH
" No internal ROM in H06305X2
OATA7
DATA.
DATA,
DATA.
DATA]
OATA1
DATAl
DAT-'o
~HITACHI
423
HD6305X1,HD6305X2------------------------------------------------------• ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Supply Voltage
Vee
-0.3-+7.0
V
Input Voltage
Vin
-0.3 - Vee + 0.3
V
Operating Temperature
Topr
0-+70
°c
Storage Temperature
T stg
-55 - +150
°c
Item
[NOTE)
•
•
These products have a protection circuit in their input terminals against high electrostatic voltage or high electric fields. Notwithstanding,
be careful not to apply any voltage higher than the absolute maximum rating to these high input impedance circuits. To assure normal
operation, we recommended Vln, Vout ; Vss ~ IV ln or Vout ) ~ Vee.
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee· 5.0V±10%. Vss· OV. T. • 0 - +70°C. unleu otherwise noted.)
Item
RES,STBY
Input "High" Voltage
Input "Low" Voltage
Symbol
EXTAL
Other Inputs
V IH
All Inputs
V IL
Output "High" Voltage All Outputs
V OH
Output "Low" Voltage All Outputs
TIMER,INT,
Input Leakage Current
0 1 - D"STBY
VOL
Three-state Current
min
typ
max
Vee-0. 5
Vee xO. 7
2.0
Vee+0 .3
-
-
-
Test Condition
-0.3
2.4
IOH = -200llA
Vee- 0 .7
IOH = -101lA
IOL = 1.6mA
!lId
Ao - A" Bo - B"
C41 - C" ADRo - ADR13·,
E , RM·
Current Dissipation··
IITSII
Input Capacitance
f
Icc
Standby
All Terminals
Vee+0 .3
V
Vee+0 .3
0.8
V
-
V
0.55
V
1.0
IlA
-
1.0
IlA
5
2
10
mA
mA
Vin = 0.5 - Vee-0.5
Operating
Wait
Stop
Unit
Cin
f
=1MHz···
=1MHz, Vin =OV
5
10
10
12
2
2
-
IlA
IlA
pF
• Only at standby
•• VIH min'"' Vee-1.0V, VIL max'"' O.8V
••• The value at f = xMHz is given by using.
IcC If =xMHz) = Icc If = 1MHzI )C x
•
AC CHARACTERISTICS (Vee
Item
=5.0V ±10%, Vss = OV, T.· 0 Symbol
Cycle Time
t cvc
Enable Rise Time
tEr
tEf
PW EH
PW EL
Enable Fall Time
Enable Pulse Width("High" Level)
Enable Pulse Width ("Low" Level)
Address Delay Time
Address Hold Time
Data Set-up Time (Read)
tAD
tAH
tow
tHW
tOSR
Data Hold Time (Read)
tHR
Data Delay Time
Data Hold Time (Write)
424
Test
Condition
1
~
Fig. 1
+70°C, unless otherwise noted.)
HD6305X 1/X2
typ
min
max
HD63A05X1/X2
min
typ
max
10
0.666
-
10
-
20
20
-
-
300
300
450
450
-
-
-
250
-
20
-
-
20
20
80
0
_HITACHI
250
-
-
20
60
0
-
-
20
20
HD63B05X 1/X2
typ
min
max
Unit
-
#AS
ns
0.5
-
-
-
-
ns
ns
-
-
ns
-
TBD
ns
ns
ns
ns
-
220
-
220
190
-
-
20
160
-
-
20
TBD
0
10
20
20
TBD
-
ns
ns
-------------------------------------------------------HD6305X1,HD6305X2
• PORT TIMING (VCC=5.0V±10%, VSS=OV, Ta=O-+70°C,unlessotherwisenoted.)
Item
Port Data Set-up Time
(Port A, B, C, D)
Port Data Hold Time
(Port A, S, C, D)
Port Data Delay Time
(Port A, S, C)
•
Symbol
Test
Condition
tpDS
HD6305X 1/X2
typ
min
max
HD63A05X 1/X2
typ
min
max
HD63B05X1/X2
typ
min
max
Unit
200
-
-
200
-
-
200
-
-
ns
200
-
-
200
-
-
200
-
-
ns
-
-
300
-
-
300
-
-
300
ns
Fig. 2
tpDH
tpDw
Fig. 3
CONTROL SIGNAL TIMING (Vee = 5.0V±10%, Vss = OV, T8 = 0 - +70°C, unless otherwise noted.)
INTPuise Width
tlWL
HD6305X1/X2
typ
min
max
tcyc
+250
INT2 Pulse Width
t'WL2
tcyc
+250
-
RES Pulse Width
Control Set-up Time
tRWL
tcs
5
250
-
Item
Symbol
Timer Pulse Width
tTWL
Oscillation Start Time (Crystal)
Reset Delay Time
tose
tRHL
• CL
Test
Condition
Fig. 5
tcyc
+250
-
Fig.5.Fig.20·
-
Fig. 19
80
-
HD63A05X1/X2
typ
min
max
tcyc
+200
tcyC
+200
-
-
-
-
-
-
-
tcyc
+200
20
-
-
-
80
-
5
250
HD63B05X1/X2
typ
min
max
tcyc
+200
tcyc
+200
Unit
ns
ns
-
-
5
250
tcyc
+200
-
-
ns
20
-
-
20
-
80
-
-
ms
ms
-
-
-
t cvc
ns
=22pF ±20%, Rs = 600 max.
• SCI TIMING (Vee = 5.0V±10%, VSS= OV, Ta = 0"'" +70°C, unless otherwise noted.)
Item
Clock Cycle
Data Output Delay Time
Data Set-up Time
Data Hold Time
Symbol
Test
Condition
tScyc
tTXD
tSRX
tHRX
Fig. 6,
Fig. 7
HD63A05Xl/X2
HD6305X1/X2
HD63B05Xl/X2
Unit
typ
typ
typ
min
max
min
max
min
max
1
- 32768 0.67 - 21845 0.5 - 16384 IlS
250
250
ns
- 250 200
ns
- 200 - 200 100
ns
- 100 - 100 -
~HITACHI
425
HD6305X1,HD6305X2------------------------------------________________
....---------tcvc----------..I
E
\100011----PWEL---~J
!4----PWeHI-----..I
ter
2.4V
Ao-A13
R/W
Address Valid
O.6V
tow
MCU Write
00-07
MCU Read
00-07
Figure 1 Bus Timing
E
E
Port
A.B.C.o
Port
A.B.C
2.4V
O.6V
Data
Valid
Figure 3 Port Data Delay Time (MCU Write)
Figure 2 Port Data Set-up and Hold Times
(MCU Read)
Interrupt
Test
E
Address
Bus
PCoPC7
Data Bus
Op
Code
R/W
Vector Vector
Operand Irrelevant
Op Code Data
\~------------~I
Figure 4 Interrupt Sequence
426
First Inst. of
~::.ess~~:ress Interrupt Routine
_HITACHI
-----------------------------------------------------HD6305Xl.HD6305X2
____
~.~
__
=:=-u-1~--~ ----~,---~~~~enun
E
Vee
~tose]
tose
~~Verl-O.5V
I
Si'Bv
Vee-O.SV
RES
Address
Bus
RiW
Data Bus
--I
---
'--,- - - 1FFF
New PC
1FFF
1FFF
';:=r-&llllll/$
_~I----------------~I~~$ffjfh}____
FigureS Reset Timing
tscyC
Clock Output
2.4V
C5/CK
O.6V
Data Output
C7/TX
tSRX
Data Input
2.0V
Ca/Rx
O.BV
Figure6 SCI Timing (Internal Clock)
tscyC
Clock Input
2.0V
C5/CK
O.8V
Data Output
C7/TX
Data Input
2.0V
C6/RX
O.8V
Figure7 SCI Timing(External Clock)
_HITACHI
427
HD6305Xl,HD6305X2------------------------------------------------------• Data Bus (DATAo '" DATA,)
This TTL compatible three-state buffer can drive one TTL
load and 90pF.
Vee
TTL load
(Port)
IOl=1.6mA
Test point
terminal o----4~--......
2.4kQ
• Address Bus (ADR o '" ADR 13)
Each terminal is TTL compatible and can drive one TTL
load and 90pF.
--*"--1'
90pF
12kQ
• Input/Output Terminals (Ao '" A, • Bo '" B,. Co '" C,)
These 24 terminals consist of four 8-bit I/O ports (A, B, C).
Each of them can be used as an input or output terminal on
a bit through program control of the data direction register.
For details, refer to "I/O PORTS."
[NOTES J 1. The load capacitance includes stary capacitance caused
by the probe, etc.
2. All diodes are 1S2074
®.
Figure 8 Test Load
- DESCRIPTION OF TERMINAL FUNCTIONS
The input and output signals of the MCU are described
here.
.Vee, Vss
Voltage is applied to the MCU through these two terminals.
Vee is 5.0V ± 10%, while Vss is grounded.
.INT,INT2
External interrupt request inputs to the MCU. For details,
refer to "INTERRUPT". The INT2 terminal is also used as
the port D6 terminal.
• XTAL, EXTAL
These terminals provide input to the on-chip clock circuit.
A crystal oscillator (AT cut, 2.0 to 8.0 MHz) or ceramic
filter is connected to the terminal. Refer to "INTERNAL
OSCILLATOR" for using these input terminals.
• TIMER
This is an input terminal for event counter. Refer to
"TIMER" for details.
.RES
Used to reset the MCU. Refer to "RESET" for details.
.NUM
This terminal is not for user application. In case of the
HD6305XI, this terminal should be connected to Vee
through iOkU resistance. In case of the HD6305X2, this
terminal should be connected to Vss·
• Enable (E)
This output terminal supplies E clock. Output is a singlephase, TTL compatible and 1/4 crystal oscillation frequency
or 1/4 external clock frequency. It can drive one TTL load
and a 90pF condenser .
• Read/Write (R/W)
This TTt compatible output Signal indicates to peripheral
and memory devices whether MCU is in Read ("High"), or
in Write ("Low"). The normal standby state is Read ("High").
Its output can drive one TTL load and a 90pF condenser.
428
• Input Terminals (01 '" 0,)
These seven input-only terminals are TTL or CMOS compatible. Of the port D's, D6 is also used as INT2. If D6 is
used as a port, the INIl interrupt mask bit of the miscellaneous register must be set to "I" to prevent an INT2 interrupt
from being aCCidentally accepted .
• STBY
This terminal is used to place the MCU into the standby
mode. With STBY at "Low" level, the oscillation stops and
the internal condition is reset. For details, refer to "Standby Mode."
The terminals described in the following are I/O pins for
serial communication interface (SCI). They are also used as
ports C s , C6 and C,. For details, refer to "SERIAL COMMUNICATION INTERFACE."
.CK (Cs)
Used to input or output clocks for serial operation .
.Rx (C6)
Used to receive serial data.
.Tx (C,)
Used to transmit serial data .
-MEMORY MAP
The memory map of the MCU is shown in Fig. 9. $1000""
$IFFF of the HD6305X2 are external addresses. However,
care should be taken to assign vector addresses to $lFF6 ...,
$IFFF. During interrupt processing, the contents of the CPU
registers are saved into the stack in the sequence shown in
Fig. 10. This saving begins with the lower byte (PCL) of the
program counter. Then the value of the stack pointer is
decremented and the higher byte (PCH) of the program
counter, index register (X), accumulator (A) and condition
code register (CC) are stacked in that order. In a subroutine
call, only the contents of the program counter (PCH and peL)
are stacked.
~ HITACHI
-------------------------------------------------------HD6305X1,HD6305X2
0
12 7
12 B
25 5
25 6
I/O Ports
Timer
SCI
S007F
RAM
(12BBytes)
Stack
ROM'
(4,096Bytes)
818 2
819 1
819 2
~~080
-~n!i~~~~t-.Ve
A
B
C
0
PORT A DDR
5
PORT B DDR
6
PORT C DDR
B
9
10
$O~F
5100\6
$lFF6
Sl FFF
$2000
17
18
Timer Data Reg
Timer CTRl Reg
Mlsc Reg
SOO
$01
S02
$03"
$04"
$05"
$06"
12~~
$3FFF
$08
$09
$OA
-REGISTERS
There are five registers which the programmer can operate.
o
--11 Accumulator
7
I
7
I
1..-_ _ _ _
A ___
o
X
Iindex
L -_ _ _ _ _ _ _....... Register
o
13
:rogram
I'--_ _ _ _ _ _ _PC_ _ _ _ _ _--'.ICounter
13
6 5
0
I~0_Llo~lo~l~o~lo~lo~l~l~l-l~I____s-p____~1~~~~r
Not Used
...-...,..........--.---r...... Condition
'-r....,-..,~...,......"T-'
SCI CTRl Reg
SCI STS Reg
SCI Data Reg
Not Used
31
32 External
External
Memory Space
1638 3
PORT
PORT
PORT
PORT
Not Used
$gOFF
$ 100
External
Memory Space
409 5
409 t
0
1
2
3
4
1$0000
Memory Space
$10
$11
$12
~gg~~
Zero
' - - - - - Negative
'------Interrupt
Mask
$lF
$20
'-------Half
Carry
$7F
Figure 11 Programming Model
* Write only register
.. Read only reg ister
• ROM area ($1000 - $1 FFF) in the HD6305X2
is changed into External Memory Space.
Code
Register
e Accumulator (A)
This accumulator is an ordinary 8-bit register which holds
operands or the result of arithmetic operation or data processing.
Figure 9 Memory Map of MCU
I
7 6
543 2 1 0
1
Condition
1
n-4 1
n+l
Code Register
n-3
Accumulator
n+2
n-2
Index Register
n+3
PCH"
n+4
n-l 1 11
n
PCl"
Pull
n+5
Push
• In a subroutine call, only PCl and PCH are stacked.
Figure 10 Sequence of Interrupt Stacking
elndex Register (X)
The index register is an 8-bit register, and is used for index
addressing mode. Each of the addresses contained in the
register consists of 8 bits which, combined with an offset
value, provides an effective address.
In the case of a read/modify/write instruction, the index
register can be used like an accumulator to hold operation
data or the result of operation.
If not used in the index addressing mode, the register can
be used to store data temporarily.
_ Program Counter (PC)
The program counter is a 14-bit register that contains the
address of the next instruction to be executed.
- Stack Pointer (SP)
The stack pointer is a 14-bit register that indicates the address of the next stacking space. Just after reset, the stack
pointer is set at address SOOFF. It is decremented when data
is pushed, and incremented when pulled. The upper 8 bits
of the stack pointer are fixed to 00000011. During the MCU
being reset or during a reset stack. pointer (RSP) instruction,
the pointer is set to addresS SOOFF. Since a subroutine or
interrupt can use space up to address SOOC1 for stacking, the
subroutine can be used up to 31 levels and the interrupt up
to 12 levels.
-Condition Code Register (CC)
The condition code register is a 5-bit register, each bit
indicating the result of the instruction just executed. The
bits can be indiVidually tested by conditional branch instruc-
_ HITACHI
429
HD6305X1,HD6305X2----------------------------------------------______
tions. The CC bits are as follows:
Half Carry (H): Used to indicate that a carry occurred between bits 3 and 4 during an arithmetic operation (ADD, ADC).
Interrupt (I): Setting this bit causes all interrupts, except
a software interrupt, to be masked. If an
interrupt occurs with the bit I set, it is
latched. It will be processed the instant
the interrupt mask bit is reset. (More specifically, it will enter the interrupt processing
routine after the instruction following the
CLI has been executed.)
Negative (N): Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is negative (bit 7 is logic
"I").
Zero (Z):
Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is zero.
Carry!
Represents a carry or borrow that occurred
Borrow (C): in the most recent arithmetic operation. This
bit is also affected by the Bit Test and Branch
instruction and a Rotate instruction.
-INTERRUPT
There are six different types of interrupt: external.interrupts (00,. IN.T2), internal timer interrupts (TIMER,
TIMER2), senal mterrupt (S.CI) and interrupt by an instruction (SWI).
Of these six interrupts, the INT2 and TIMER or the SCI
and TIMER2 generate the same vector address, respectively.
When an interrupt occurs, the program in progress stops
and the then CPU status is saved onto the stack. And then,
the interrupt mask bit (I) of the condition code register is
set and the start address of the interrupt processing routine
is obtained from a particular interrupt vector address. Then
the interrupt routine starts from the start address. System
can exit from the interrupt routine by an RTI instruction.
When this instruction is executed, the CPU status before
the interrupt (saved onto the stack) is pulled and the CPU
restarts the sequence with the instruction next to the one at
which the interrupt occurred. Table I Usts the priority of
inttrrupts and their vector addresses.
Table 1
Interrupt
Priority of Interrupts
Priority
Vector Address
RES
1
SlFFE,
$lFFF
SWI
2
$lFFC,
$lFFD
INT
3
$lFFA,
$lFFB
TIMERIINT2
4
$lFFS,
$lFF9
SCI/TIMER2
5
SlFFS,
SlFF7
A flowchart of the interrupt sequence is shown in Fig. 12.
A block diagram of the interrupt request source is shown in
Fig. 13.
,--------.
y
y
1--1
SFF--SP
O--OOR's
CLR INT Logic
SFF--TDR
S7F--Timer Prescaler
S50--TCR
S3F--SSR
SOO--SCR
S7F ..... MR
TIMER
Y
Figure 12 Interrupt Flow Chart
430
!NT
Cf)HITACHI
SCI
------------------------------------------~-----------HD6305X1,HD6305X2
Bit 7 of this register is the INTi interrupt request flag.
When the fa1ling edge is detected at the INT2 terminal, "I"
is set in bit 7. Then the software in the interrupt routine
(vector addresses: SIFF8, $IFF9) checks bit 7 to see if it
is INT2 interrupt. Bit 7 can be reset by software.
In the block diagram, both the external interrupts INT and
INTi are edge trigger inputs. At the faUing edge of each input,
an interrupt request is generated and latched. The INT interrupt request is automatically cleared if jumping is made to
the iNf processing routine. Meanwhile, the INT2 request is
cleared if ''0'' is written in bit 7 of the misceUaneol. .:gister.
For the external interrupts (INT, INT2), internal timer
interrupts (TIMER, TIMER2) and serial interrupt (SCI), each
interrupt request is held, but not processed, if the I bit of the
condition code register is set. Immediately after the I bit is
cleared, the corresponding interrupt processing starts according to th~ority.
The INT2 interrupt can be masked by setting bit 6 of the
miscellaneous register; the TIMER interrupt by setting bit 6
of the timer control register; the SCI interrupt by setting bit
S of the serial status register; and the TIMERz interrupt by
setting bit 4 of the serial status register.
The status of the 00 terminal can be tested by a BIL or
BIH instruction. The INT falling edge detector circuit and
its latching circuit are independent of testing by these instructions. This is also true with the status of the INTi terminal.
Miscellaneous Register (MR;$OOOA)
76543210
IMR~MR6IZ1Z1Z1Z1ZJZI
-INT2 Interrupt Mask
l....._ _ _ _ _ _ _ _ _ _
INTl Interrupt Request Flag
Miscellaneous Register (MR; SOOOA)
Bit 6 is the INT2 interrupt mask bit. If this bit is set to "1",
then the INT2 interrupt is disabled. Both read and write are
possible with bit 7 but "I" cannot be written in this bit by
software. This means that an interrupt request by software
is impossible.
When reset, bit 7 is cleared to "0" and bit 6 is set to "1".
-Miscellaneous Register (MR; $OOOA)
The interrupt vector address for the external interrupt
INT2 is the same as that for the TIMER interrupt, as shown
in Table 1. For this reason, a special register called the miscellaneous register (MR; SOOOA) is available to control the
INTi interrupts.
-TIMER
Figure 14 shows a MCU timer block diagram. The timer
data register is loaded by software and, upon receipt of a
clock input, begins to count down. When the timer data
Vectoring generated
$1 FFA, $1 FFB
I
BIH/BIL Test
f
I
Condition Code Register (CC)
INT
,
Falling Edge Detector
~~~+----
Vectoring generated
$1FF8,$1FF9
TIMER
Serial Status
Register (SSR)
SCI/TIMER2
~----41~--
Figur~
Vectoring generated
$1FF6,$1FF7
13 Interrupt Request Generation Circuitry
$
HITACHI
431
HD6305X1,HD6305X2---------------------------------------------------register (TDR) becomes "0", the timer interrupt request
bit (bit 7) in the timer control register is set. In response to
the interrupt request, the CPU saves its status into 'the stack
and fetches timer interrupt routine address from addresses
SlFF8 and $lFF9 and execute the interrupt routine. The
timer interrupt can be masked by setting the timer interrupt
mask bit (bit 6) in the timer control register. The mask bit
(I) in the condition code register can also mask the timer
interrupt.
The source clock to the timer can be either an external
signal from the timer input terminal or the internal E signal
(the oscillator clock divided by 4). If the E signal is used as
the source, the clock input can be gated by the input to the
timer input terminal.
Once the timer count has reached "0", it starts counting
down with "SFF". The count can be monitored whenever
desired by reading the timer data register. This permits the
program to know the length of time having passed after the
occurrence of a timer interrupt, without disturbing the contents of the counter.
When the MCU is reset, both the prescaler and counter are
initialized to logic "1". The timer interrupt request bit
(bit 7) then is cleared and the timer interrupt mask bit (bit
6) is set.
To clear the timer interrupt request bit (bit 7), it is necessary to write "0" in that bit.
• Timer Control Register (TCR; $0(09)
Selection of a clock source, selection of a prescaler frequency division ratio, and a timer interrupt can be controlled
by the timer control register (TCR; $0009).
For the selection of a clock source, anyone of the four
modes (see Table 2) can be selected by bits 5 and 4 of the
timer control register (TCR).
Timer Control Register (TCR; $0009)
L Prescaler division rltio selection
Prescaler initialize
Clock input source
1...-_ _ _ _ _ _ _ _ _ _ Timer interrupt mask
1..-_ _ _ _ _ _ _ _
' - - - - - - - - - - - - - - - T i m e r interrupt request
After reset, the TCR is initialized to "E under timer terminal control" (bit 5 = 0, bit 4 = 1). If the timer terminal is
"1", the counter starts counting down with "$FF" immediately after reset.
When "1" is written in bit 3, the prescaler is initialized.
This bit always shows "0" when read.
Table 2
TCR7
Timer·interrupt request
o
Absent
TCR
Bit5
Bit4
Present
Clock input source
0
0
Internal clock E
TCR6
Timer interrupt mask
0
1
E under timer terminal control
o
Enabled
1
0
No clOGk input (counting stopped)
Disabled
1
1
Event input from timer terminal
Initialize
(Internal
Clock)
E --+-,
~
3
...._ _ _- - -.....- - - - ' Timer Interrupt
Write
Read
Figure 14 Timer Block Diagram
432
Clock Source Selection
_HITACHI
-------------------------------------------------------HD6305Xl,HD6305X2
A prescaler division ratio is selected by the combination of
three bits (bits 0, 1 and 2) of the timer control register (see
Table 3). There are eight different division ratios: +1, +2, +4,
+8, +16, +32, +64 and +128. After reset, the TCR is set to the
+1 mode.
A timer interrupt is enabled when the timer interrupt mask
bit is "0", and disabled when the bit is "1". When a timer
interrupt occurs, "1" is set in the timer interrupt request bit.
This bit can be cleared by writing "0" in that bit.
-SERIAL COMMUNICATION INTERFACE (SCI)
Table 3
Prescaler Division Ratio Selection
TCR
Bit 0
Prescaler division ratio
Bit 2
Bit 1
0
0
0
+1,
0
0
1
+2
0
1
0
+4
0
1
1
+8
1
0
0
+16
1
0
1
+32
1
1
0
+64
1
1
1
+128
This interface is used for serial transmission or reception
of 8-bit data. Sixteen transfer rates are available in the range
from 1 jJ.S to approx. 32 ms (for oscillation at 4 MHz).
The SCI consists of three registers, one eighth counter and
one prescaier. (See Fig. 15.) SCI communicates with the CPU
via the data bus, and with the outside world through bits 5,
6 and 7 of port C. Described below are the operations of
each register and data transfer.
-SCI Control Register (SCR; $0010)
SCI Control Registers (SCR; 0010)
r--~--'
'--_.....1-_,......1
Transfer
Clock
Generator
C5(CK) :
I
I
I
I
I
I
SCI Data Registers L....-L,.l---'
(SOR: $0012)
...._________~
Initialize
I
I
C6(Rx)
-----.:
I
C7(Tx)
L______ r---~=r~~~~~~~~~~~~~~~~~~~~~~==~--~
SCI Status Registers
(SSR :$0011 )
Not Used
SCI/TIMER2
Figure 15 SCI Block Diagram
~HITACHI
433
HD6305X1,HD6305X2------------------------------------------------------Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set upon
completion of transmitting or receiving 8-bit data. It is
cleared when reset or data is written to or read from the
SCI data register with the SCRS="I". The bit can also be
cleared by writing "0" in it.
C, terminal
SCR7
o
Used as I/O terminal (by DOR).
Serial data output (DDR output)
Bit 6 (SSR6)
Bit 6 is the TIMER2 interrupt request bit. TIMER2 is used
commonly with the serial clock generator, and SSR6 is set
each time the internal transfer clock falls. When reset, the
bit is cleared. It also be cleared by writing "0" in it. (For
details, see TIMER2 .)
C6 terminal
SCR6
o
Used as I/O terminal (by DDR).
Serial data input (DDR input)
SCR5 SCR4
Clock source
C5 terminal
0
0
-
0
1
-
1
0
Internal
Clock output (DDR output)
1
1
External'
Clock input (DDR input)
Used as I/O terminal (by
DDR).
Bit 7 (SCR7)
When this bit is set, the DDR corresponding to the C,
becomes" 1" and this terminal serves for output of SCI data.
After reset, the bit is cleared to "0".
Bit 6 (SCR6)
When this bit is set, the DDR corresponding to the C6
becomes "0" and this terminal serves for input of SCI data.
After reset, the bit is cleared to "0".
Bit 5 (SSRS)
Bit 5 is the SCI interrupt mask bit which can be set or
cleared by software. When it is "I", the SCI interrupt (SSR7)
is masked. When reset, it is set to "I".
Bit 4 (SSR4)
Bit 4 is the TIMER2 interrupt mask bit which can be set
or cleared by software. When the bit is "I", the TIMER2
interrupt (SSR6) is masked. When reset, it is set to "1".
Bit 3 (SSR3)
When "I" is written in this bit, the prescaler of the transfer
clock generator is initialized. When read, the bit always is "0".
Bits 2-0
Not used.
SSR7
o
Bits 5 and 4 (SCR5, SCR4)
These bits are used to select a clock source. After reset,
the bits are cleared to "0".
SCR2
0
0
SCR1
0
SCRO
0
SSR6
TIMER2 interrupt request
o
Absent
Present
Transfer clock rate
4.00 MHz
4.194 MHz
1 I1s
SSR5
o
0.9511s
0
0
0
1
211s
1.9111S
0
1
0
411s
3.8211s
0
0
1
1
Bl1s
7.6411S
SSR4
1
1
l
l
l
l
o
1
1
1
1
3276811s
1/32 s
-SCI Status Register (SSR; $0011)
76543210
434
SCI interrupt mask
Enabled
Disabled
0
-SCI Data Register (SDR; $0012)
A serial-parallel conversion register that is used for transfer
of data.
Absent
Present
Bits 3 - 0 (SCR3 - SCRO)
These bits are used to select a transfer clock rate. Mter
reset, the bits are cleared to "0".
SCR3
SCI interrupt request
TIMER2 interrupt mask
Enabled
Disabled
• Data Transmission
By writing the desired control bits into the SCI control
registers, a transfer rate and a source of transfer clock are
determined and bits 7 and 5 of port C are set at the serial
data output terminal and the serial clock terminal, respectively. The transmit data should be stored from the accumulator or index register into the SCI data register. The data
written in the SCI data register is output from the C,fTx
terminal, starting with the LSB, synchronously with the
falling edge of the serial clock. (See Fig. 16.) When 8 bit of
~HITACHI
---------------------------------------------------------HD6305Xl,HD6305X2
data have been transmitted, the interrupt request bit is set in
bit 7 of the SCI status register with the rising edge of the last
serial clock. This request can be masked by setting bit 5 of the
SCI status register. Once the data has been sent, the 8th bit
data (MSB) stays at the C7/Tx terminal. If an external clock
source has been selected, the transfer rate determined by
bits 0 - 3 of the SCI control register is ignored, and the Cs /
CK terminal is set as input. If the internal clock has been
selected, the Cs/CK terminal is set as output and clocks are
outpu t at the transfer rate selected by bits 0 - 3 of the SCI
control register.
Figure 16 SCI Timing Chart
• Data Reception
By writing the desired control bits into the SCI control
register, a transfer rate and a source of transfer clock are determined and bit 6 and 5 of port C are set at the serial data
input terminal and the serial clock terminal, respectively.
Then dummy-writing or -reading the SCI data register, the
system is ready for receiving data. (This procedure is not
needed after reading subsequent received data. It must be taken
after reset and after not reading subsequent received data.
The data from the C6 /Rx terminal is input to the SCI
data register synchronously with the rising edge of the
serial clock (see Fig. 16). When 8 bits of data have been received, the interrupt request bit is set in bit 7 of the SCI
status register. This request can be masked by setting bit 5
of the SCI status register. If an external clock source have been
selected, the transfer rate determined by bits 0 - 3 of the SCI
control register is ignored and the data is received synchronously with the clock from the Cs /CK terminal. If the internal
clock has been selected, the Cs/CK terminal is set as output
and clocks are output at the transfer rate selected by bits 0 3 of the SCI control register.
TIMER2 is commonly used with the SCI transfer clock
generator. If wanting to use TIMER2 independently of the
SCI, specify "External" (SCRS = 1, SCR4 = 1) as the SCI
clock source.
If "Internal" is selected as the clock source, reading or
writing the SDR causes the· prescaler of the transfer clock
generator to be initialized.
-I/O PORTS
There are 24 input/output terminals (ports A, B, C). Each
I/O terminal can be selected for either input or output by the
data direction register. More specifically, an I/O port will
be input if "0" is written in the data direction register, and
output if "1" is written in the data direction register. Port A,
B or C reads latched data if it has been programmed as output,
even with the output level being fluctuated by the output
load. (See Fig. 17.)
When reset, the data direction register and data register go
to "0" and all the input/output terminals are used as input.
Bit of data
direction
register
Bit of
output
data
Status of
output
Input to
CPU
1
a
0
a
1
1
1
1
a
x
Figure 17
3·state
Pin
Input/Output Port Diagram
.TIMER2
The SCI transfer clock generator can be used as a timer.
The clock selected by bits 3 - 0 of the SCI control register
(4 p.s - approx. 32 ms (for oscillation at 4 MHz» is input to
bit 6 of the SCI status register and the TIMER2 interrupt
request bit is set at each falling edge of the clock. Since interrupt requests occur periodically, TIMER2 can be used as a
reload counter or clock.
---~~:,
~____~----~t~____~
CD
: Transfer
®@
@@
L
Seven input-only terminals are available (port D). Writing
to an input terminal is invalid.
All input/output terminals and input terminals are TTL
compatible and CMOS compatible in respect of both input and
output.
If I/O ports or input ports are not used, they should be
connected to VSS via resistors. With none connected to these
terminals, there is the possibility of power being consumed
despite that they are not used.
-RESET
clock generator is reset and mask bit (bit 4
of SCI status register! is clea red.
®.@ : TIMER2 interrupt request
@.@ : TlMER2 interrupt request bit cleared
The MCV can be reset either by external reset input (RES)
or power-on reset. (See Fig. 18.) On power up, the reset
input must be held "Low" for at least tose to assure that the
internal oscillator is stabilized. A sufficient time of delay can
be obtained by connecting a capacitance to the RES input as
shown in Fig. 19.
~HITACHI
435
HD6305X1,HD6305X2------------------------------------------------------requirement for minimum external configurations. It can be
driven by connecting a crystal (AT cut 2.0 -- 8.0MHz) or
ceramic oscillator between pins 5 and 6 depending on the required oscillation frequency stability.
Three different terminal connections are shown in Fig. 20.
Figs. 21 and 22 illustrate the speCifications and typical arrangement of the crystal, respectively.
5V
Vce
OV-------
RES
Terminal
~::~al
---------r
____________
Figure 18
AT Cut
Parallel
Resonance
Co=7pF max.
f=2.0-S.0MHz
Rs=6OQ max.
~
Power On and Reset Timing
Figure 21
100kn typ
Parameters of Crystal
2
VCC ~'N"v--+----,
(a)
HD6305X
MCU
Figure 19
Input Reset Delay Circuit
-INTERNAL OSCILLATOR
The internal oscillator circuit is designed to meet the
[NOTE) Use as short wirings as possible for connection of the crystal
with the EXT AL and XTAL terminals.
not allow these
wirings to cross others.
Do
6 EXTAl
iO-~t-OM-H-Z-1c:J~-t5 XTAl
Figure 22
HD6305X
MCU
10-22pF±20%
Typical Crystal Arrangement
-LOW POWER DISSIPATION MODE
The HD6305X has three low power dissipation modes:
wait, stop and standby.
Crystal Oscillator
HD6305X
MCU
External
Ceramic Oscillator
Clock
Input 6 EXTAl
NC 5 XTAl HD6305X
MCU
External Clock Drive
Figure 20
436
Internal Oscillator Circuit
.WaitMode
When WAIT instruction being executed, the MCU enters
into the wait mode. In this mode, the oscillator stays active
but the internal clock stops. The CPU stops but the peripheral
functions - the timer and the serial communication interface - stay active. (NOTE: Once the system has entered the
wait mode, the serial communication interface can no longer
be retriggered.) In the wait mode, the registers, RAM and I/O
terminals hold their condition just before entering into the
wait mode.
The escape from this mode can be done by interrupt (INT,
TIMER/INT2 or SCI/TIMER2), RES or STBY. The RES
resets the MCU and the STBY brings it into the standby
mode. (This will be mentioned later.)
When interrupt is requested to the CPU and accepted, the
wait mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt routine. If the interrupt is
masked by the I bit of the condition code register, after releasing from the wait mode the MCU executes the instruction
next to the WAIT. If an interrupt other than the INT (Le.,
TIMER/INT2 or SCI/TIMER2) is masked by the timer control
~HITACHI
-------------------------------------------------------HD6305X1,HD6305X2
register, miscellaneous register or serial status register, there
is no interrupt request to the CPU, so the wait mode cannot
be released.
Fig. 23 shows a flowchart for the wait function.
• Stop Mode
When STOP instruction being executed, MCU enters into
the stop mode. In this mode, the oscillator stops and the CPU
and peripheral functions become inactive but the RAM,
registers and 1/0 terminals hold their condition just before
entering into the stop mode.
The escape from this mode can be done by an external
interrupt (INT or INT2), RES or STBY. The RES resets the
MCU and the STBY brings into the standby mode.
When interrupt is requested to the CPU and accepted,
the stop mode escapes, then the CPU is brought to the operation mode and vectors to the interrupt routine. If the interrupt is masked by the I bit of the condition code register,
after releasing from the stop mode, the MCU executes the
instruction next to the STOP. If the INT2 interrupt is masked
by the miscellaneous register, there is no interrupt request to
the MCU, so the stop mode cannot be released.
Fig. 24 shows a flowchart for the stop function. Fig. 25
shows a timing chart of return to the operation mode from
the stop mode.
For releasing from the stop mode by an interrupt, oscillation starts upon input of the interrupt and, after the internal
delay time for stabilized oscillation, the CPU becomes active .
For restarting by RES, oscillation starts when the RES goes
"0" and the CPU restarts when the RES goes "I". The duration of RES="O" must exceed tose to assure stabilized oscillation.
• Standby Mode
The MCU enters into the standby mode when the SrBY
terminal goes "Low". In this mode, all operations stop and
the internal condition is reset but the contents of the RAM are
hold. The I/O terminals turn to high-impedance state. The
standby mode should escape by bringing STBY "High". The
CPU must be restarted by reset. The timing of input signals
at the RES and STBY terminals is shown in Fig. 26.
Table 4 lists the status of each parts of the MCU in each
low power dissipation modes. Transitions between each mode
are shown in Fig. 27.
~HITACHI
437
HD6305X1,HD6305X2-------------------------------------------------------
Oscillator Active
Timer and Serial
Clock Active
All Other Clocks
Stop
Initialize
CPU, TIMER; SCI,
I/O and All
Other Functions
No
No
1=1
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 23 Wait Mode Flow Chart
438
_HITACHI
-------------------------------------------------------HD6305Xl,HD6305X2
Stop Oscillator
and All Clocks
No
Turn on Oscillator
Wait for Time Delay
to Stabilize
Turn on Oscillator
Wait for Time Delay
to Stabilize
1=1
load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 24 Stop Mode Flow Chart
~HITACHI
439
HD6305X1 ,HD6305X2 - - - - - - - - - - - - - - - - - - - - - - -_ _ _ __
o.:w.~~~"~~~~~~~
t
Time required for oscillation to become
stabilized (built·in delay time)
Interrupt
STOP instruction
executed
Instructions
restart
(a) Restart by Interrupt
Oscillator 11111111111111111111111111111
E
Time required for oscillation to become
stabilized (tose)
STOP instruction
executed
Reset
start
(b) Restart by Reset
Figure 25 Timing Chart of Releasing from Stop Mode
\
I
H
i
I
I
I
i,-_ ..I __IL __ I
\
tosc
Figure 26
Table 4
Mode
WAIT
-
Start
Software
STOP
Standby
440
Hardware
Restart
Timing Chart of Releasing from Standby Mode
Status of Each Part of MCU in Low Power Dissipation Modes
Condition
Timer,
Register
Serial
Oscil·
lator
CPU
WAIT in·
struction
Active
Stop
Active
STOP instruction
Stop
Stop
STBY="Low"
Stop
Stop
Escape
RAM
I/O
terminal
Keep
Keep
Keep
STBY, RES, INT, INI2,
each interrupt request of
TIMER, TIMER 2 , SCI
Stop
Keep
Keep
Keep
STBY, RES, INT, INT2
Stop
Reset
Keep
High im·
pedance
~HITACHI
STBY="High"
---------------------------------------------------------HD6305Xl,HD6305X2
Figure 27
Transitions among Active Mode, Wait Mode,
Stop Mode, Standby Mode and Reset
-BIT MANIPULATION
The MCU can use a single instruction (BSET or BCLR) to
set or clear one bit of the RAM or an I/O port (except the
write-only registers such as the data direction register). Every
bit of memory or I/O within page 0 ($00 ~ $FF) can be tested
by the BRSET or BRCLR instruction; depending on the result
of the test, the program can branch to required destinations.
Since bits in the RAM, or I/O can be manipulated, the user
may use a bit within the RAM as a flag or handle a single I/O
bit as an independent I/O terminal. Fig. 28 shows an example
of bit manipulation and the validity of test instructions. In
the example, the program is configured assuming that bit 0
of port A is connected to a zero cross detector circuit and
bit 1 of the same port to the trigger of a triac.
The program shown can activate the triac within a time of
lOllS from zero-crossing through the use of only 7 bytes on
the ROM. The on-chip timer provides a required time of
delay and pulse width modulation of power is also possible.
SELF 1.
Figure 28
BRClR 0, PORT A, SELF 1
BSET 1, PORT A
BClR 1, PORT A
Exa~ple of Bit Manipulation
the byte that follows the operation code.
e Direct
See Fig. 30. In the direct addressing mode, the address of
the operand is contained in the 2nd byte of the instruction.
The user can gain direct access to memory up to the lower
255th address. All RAM and I/O registers are on page 0 of address space so that the direct addressing mode may be utilized.
e Extended
See Fig. 31. The extended addressing is used for referencing to all addresses of memory. The EA is the contents of
the 2 bytes that follow the operation code. An extended
addressing instruction requires a length of 3 bytes.
e Relative
See Fig. 32. The relative addreSSing mode is used with
branch instructions only. When a branch occurs, the program
counter is loaded with the contents of the byte following the
operation code. EA = (PC) + 2 + ReI., where ReI. indicates a
signed 8-bit data following the operation code. If no branch
occurs, ReI. = O. When a branch occurs, the program jumps
to any byte in the range + 129 to -127. A branch instruction
requires a length of 2 bytes.
-ADDRESSING MODES
Ten different addressing modes are available to the MCU.
elmmediate
See Fig. 29. The immediate addreSSing mode provides
access to a constant which does not vary during execution of
the program.
This access requires an instruction length of 2 bytes. The
effective address (EA) is PC and the operand is fetched from
elndexed (No Offset)
See Fig. 33. The indexed addreSSing mode allows access
up to the lower 255th address of memory. In this mode, an
instruction requires a length of one byte. The EA is the
contents of the index register.
~HITACHI
441
HD6305X1,HD6305X2------------------------------------------------------elndexed (8-bit Offset)
See Fig. 34. The EA is the contents of the byte following the operation code, plus the contents of the index register.
This mode allows access up to the lower 511 th address of
memory. Each instruction when used in the index addressing
mode (8-bit offset) requires a length of2 bytes.
elndexed (16-bit Offset)
See Fig. 35. The contents of the 2 bytes following the
operation code are added to content of the index register
to compute the value of EA. In this mode, the complete
memory can be accessed. When used in the indexed addressing mode (l6-bit offset), an instruction must be 3 bytes long.
e Bit Set/Clear
See Fig. 36. This addressing mode is applied to the BSET
and BCLR instructions that can set or clear any bit on page
O. The lower 3 bits of the operation code specify the bit to
be set or cleared. The byte that follows the operation code
indicates an address within page o.
i
e Bit Test and Branch
See Fig. 37. This addressing mode is applied to the BRSET
and BRCLR instructions that can test any bit within page 0
and can be branched in the relative addressing mode. The
byte to be tested is addressed depending on the contents of
the byte following the operation code. Individual bits within
the byte to be tested are specified by the lower 3 bits of the
operation code. The 3rd byte represents a relativ~ value which
will be added to the program counter when a branch condition
is established. Each of these instructions should be 3 bytes
long. The value of the test bit is written in the carry bit of the
condition code register.
elmplied
See Fig. 38. This mode involves no EA. All information
needed for execution of an instruction is contained in the
operation code. Direct manipulation on the accumulator
and index register is included in the implied addressing mode.
Other instructions such as SWI and RTI are also used in this
mode. All instructions used in the implied addressing mode
should have a length of one byte.
A
:: _ _
~
I
Memory
~
I
CA~
F8
J
Index Reg
I
Stack Point
PROG LOA :I$F8
05BEII::::~A~6=:}_------J
05BFI
Prog Count
F8
05CO
CC
I
Figure 29
Example of Immediate Addressing
Memory
A
CATFCB32004B~~L:~~--t_---~~-----{~~2~O~:J
Index
eg
Stack kbo::!":in=-:"t- _.....
PROG LOA CAT 0520
052E
r::~=::l----.J
Prog !ount
052F
CC
.~.
:
I
:
'
Figure 30
442
Example of Direct Addressing
~HITACHI
-------------------------------------------------------HD6305Xl,HD6305X2
Memory
~
:
0000
A
:
40
PROG LOA CAT g:g!I-~~-_L
Index Reg
I
040BI---':;';"'_-t"'
Stack Point
Prog Count
CATFCB6406E5~~4~0~~!_--------------~
040C
CC
Figure 31
,
PROG BEQ PROG2 04A7
04A8
Example of Extended Addressing
Memory
~
27
18
Figure 32
Example of Relative Addressing
Memory
A
TABLFCC II
00B8~~4~C::::~--~~~-------1----------~~~4~C;;;J
49
B8
Stack POint
Prog Count
05F5
CC
Figure 33
Example of Indexed (No Offset) Addressing
~HITACHI
443
HD6305X1.HD6305X2-----------------------------------------------------
r
MeJory
BF
86
DB
CF
/
BF
86
DB
CF
0089
008A
OOBB
OOBC
----r---
Adder
-r-'
I
:
:
I
I
I
I
TABL FCB
FCB
FCB
FCB
lEA
OOBC
I
I
""
I
E6
89
PROG LOA TABL.X 075B
075C
I
I
§
A
CF
Index Reg
03
Stack Point
Figure 34
I
I
I
cc
Example of Index (8-bit Offset) Addressing
Memory
~.
.
PROG LOA TABL.X 0692
0693
0694
CC
TABL FCB
FCB
FCB
FCB
BF
B6
DB
CF
I
BF
86
DB
CF
077E
077F
0780
0781
Figure 35
Example of Index (16-bit Offset) Addressing
Memory
PORT B EQU 1 0001t---=B;;;.F_-f"1
A
PROG BCLR 6. PORT B 058F t = j l D
0590
01
r----.--J
tj
I,
Figure 36
444
Index Reg
I
Stack Point
Prog Count
0591
CC
~
I,
Example of Bit Set/Clear Addressing
~HITACHI
I
0750
Prog Count
,
,
I
-------------------------------------------------------HD6305X1,HD6305X2
PORT C EQU 2 0002 ~.....;.~--t I
A
Index Reg
I
PROG BRCLR 2.PORT C PROG 2 0574
0575 ..
1-_-_-~~~-_-_-1-1
0576
Prog
~ount
0594
t--~.;;...---t
Figure 37
•
"00'" ",.
Example of Bit Test and Branch Addressing
Memory
~
~
~
I
I
I
I
I
I
I
I
Figure 38
Example of Implied Addressing
-INSTRUCTION SET
There are 62 basic instructions available to the HD6305X
MeU. They can be classified into five categories: register/
memory, read/modify/write, branch, bit manipulation, and
control. The details of each instruction are described in
Tables 5 through 11.
• Register/Memory Instructions
Most of these instructions use two operands. One operand
is either an accumulator or index register. The other is derived
from ~emory using one of the addressing modes used on the
HD6305X MeU. There is no register operand in the unconditional jump instruction (JMP) and the subroutine jump
instruction (JSR). See Table s.
• Read/Modify/Write Instructions
These instructions read a memory or register, then modify
or test its contents, and write the modified value into the
memory or register. Zero test instruction (TST) does not
write data, and is handled as an exception in the read/modify/
write group. See Table 6.
• Branch Instructions
A branch instruction branches from the program sequence
in progress if a particular condition is established. See Table 7.
• Bit Manipulation Instructions
These instructions can be used with any bit located up to
the lower 255th address of memory. Two groups are available;
one for setting or clearing and the other for bit testing and
branching. See Table 8.
• Control Instructions
The control instructions control the operation of the MeU
which is executing a program. See Table 9.
• List of Instructions in Alphabetical Order
Table 10 lists all the instructions used on the HD6305X
MeU in the alphabetical order.
• Operation Code Map
Table 11 shows the operation code map for the instructions
used on the MeU.
~HITACHI
445
HD6305X1.HD6305X2 - - - - - - - - - - - - - - - - - - - - - - - - - - Table 5 Register/Memory Instructions
Addrelling Modes
Mnemonic
Operetions
Indexed
Indexed
Immediate
OP #
-
4 06 3
5
EE 2
4 DE 3
5
M-X
2
4 07 3
5
A-M
2
4
OF 3
5
X-M
3 EB 2
4 DB 3
5
A+M-.A
1
3 E9 2
4 09 3
5
A+M+C-A
1
3 EO 2
4 DO 3
5
A-M-A
1
3 E2
2
4 02 3
5
A-M-C-A
1
3 E4 2
4 04 3
5
A·M-A
FA
1
3 EA 2
4 OA 3
5
A+M-A
4
F8
1
3 E8 2
4 08 3
5
A(£lM-A
3
4
Fl
1
3
4 01
3
5
2 B3 2
3 C3 3
4
F3
1
3 E3 2
4 03 3
2 85
2
3 C5 3
4
F5
1
3 E5 2
BC 2
2 CC 3
3 FC
1
2 EC 2
5 CD 3
6 FO
1
5 ED 2
OP #
-
OP #
-
OP #
-
Load A from Memory
LOA
A6 2
2 B6 2
3 C6 3
4
F6
1
3 E6 2
LOld X from Memory
LOX
AE 2
2 BE 2
3 CE 3
4
FE
1
3
Store A in Memory
STA
B7 2
3 C7 3
4
F7
1
4
E7
Store X in Memory
STX
BF 2
3 CF 3
4
FF
1
4
EF
Add Memory to A
ADD
AB 2
2 BB 2
3 CB 3
4
FB
1
to A
AOC
A9 2
2 B9 2
3 C9 3
4
F9
Subtract Memory
SUB
AO 2
2 BO 2
3 CO 3
4
FO
A with Borrow
SBC
A2
2
2 B2 2
3 C2 3
4
F2
AND Memory to A
AND
A4 2
2 B4 2
3 C4 3
4
F4
OR Memorv with A
ORA
AA 2
2 BA 2
3 CA 3
4
EOR
AS 2
2 B8 2
3 C8 3
CMP
Al
2 Bl
3 Cl
CPX
A3 2
A (Logical Compare)
81T
A5 2
Jump Unconditional
JMP
Jump to Subroutine
JSR
BO 2
OP #
-
OP #
-
Condition
Coda
Booleenl
Arithmetic
Operation
Indexed
Extended (No Offset) (S·Bit Offset) (l6-SitOtlset)
Direct
H
N
Z
A
A
A
A
A
1\
• •
A
A
A
A
1\
1\
t
"
A
A
I,
1\
A
I,
1\.
"
1\
A
• •
I,
I'
A-M
• •
1\
I'
"
5
X-M
• •
A
I'
r
4 05 3
5
A·M
3 DC 3
4
5 DO 3
6
• • " •
• • • • •
• • • • •
• •
•
Add Memory and Carry
•
• •
A
Subtract Memorv from
• •
• •
• •
Exclusive OR Memorv
with A
I
• •
• •
M-A
C
•
•
•
•r,
•
•
•
Arithmetic Compare A
with Memorv
2
2
El
2
Arithmetic Compare X
with Memorv
Bit Test Memorv with
A
Symbols: Op ~ Operation
# ~ Number of bytes
- = Number of cycles
Table 6 Read/ModifylWrite Instructions
Addressing Modes
Operations
I Mnemonic
I
Indexed
Implied(A)
Implied(X)
OP II
-
OP II
-
5
7C
1
5 6C 2
6
A + 1 -A or X + 1-X or M + 1 -M
2 3A 2
5 7A
1
5 6A 2
6
A-I -A or X-I -X or M -1 -M
2
5
7F
1
5
6F
2
6
OO-A or OO-X or OO-M
2
5
73
1
5 63
2
6
A-A or x-X or M-M
-
INC
4C
1
2 5C
1
-
2 3C
Decrement
DEC
4A
1
2 5A
1
OP II
Cleer
CLR
4F
1
2
5F
1
2
Complement
COM
43
1
2 53
1
2 33
3F
2
Negate
H
NEG
40
1
2
50
1
2
30 2
5
70
1
5 60 2
6
Rotate Left Thru Carry
ROL
49
1
2 59
1
2
39
2
5
79
1
5 69
2
6
Rotate Right Thru Carry
ROR
46
1
2 56
1
2 36
2
5
76
1
5 66
2
6
Logical Shift Left
LSL
48
1
2
58
1
2 38 2
5
78
1
5 68
2
6
Logical Shift Right
LSR
44
1
2 54
1
2 34 2
5
74
1
5 64 2
6
or OO-M-M
e
b,
b,
1
5 67
2
6
L?b' -
38 2
5
78
1
5 68
2
6
Equal to LSL
4 70
1
4 60 2
1
2 57
1
2 37
Arithmetic Shift Left
ASL
48
1
2 58
1
2
TST
40 1
or Zero
2 50 1
2 3D 2
446
$
HITACHI
1\
•
•
•
1
I,
1
• • " "
1\
1\
,
1\
1\
I,
1\
I,
0
A
1\
1\
A
1\
• •
A
1\
A
• •
1\
A
•
A
~
bo
e
~
c
:1 IAH ...:t.i1 I KJ • •
Test for Negative
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
A
1\
01 1 IAr~"':MI I ro • •
77
47
Z C
1\
D-i I ~",:xr~ 11 t--0 • • "
5
ASR
A... x ... II
N
1\
0
LO-( I I I I I I I~~ • •
LEJ=t
e
I IAr3 ...:MI [bo~ • •
2
Arithmetic Shift Right
I
• •
• •
• •
• •
OO-A-A or OO-X-X
(2's Complement)
Condition
Code
BooleanlArithmetic Operation
-
OP II
Increment
OP II
Indexed
(No Offset) (8·Bit Offset)
Direct
5 A-OO or X-OO or M-OO
-------------------------------------------------------HD6305X1,HD6305X2
Table 7 Branch Instructions
Addressing Modes
Mnemonic
Operations
Relative
Condition Code
Branch Test
OP
1:*
H
I
N
Z
C
Branch Always
BRA
20
2
3
None
•
•
Branch Never
BRN
21
2
3
None
•
•
Branch IF Higher
BHI
22
2
3
C+Z=O
•
•
Branch IF Lower or Same
BLS
23
2
3
C+Z= 1
•
•
Branch IF Carry Clear
BCC
24
2
3
C =0
•
•
24
2
3
c=o
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(BHS)
•
•
•
•
•
•
•
•
•
(Branch IF Higher or Same)
Branch IF Carry Set
(Branch IF Lower)
Branch IF Not Equal
BCS
25
2
3
C= 1
•
•
(BLO)
25
2
3
C= 1
•
•
BNE
26
2
3
z=o
•
•
•
•
•
•
•
Branch IF Equal
BEQ
27
2
3
Z= 1
•
•
•
• I •
-B-r-a-nc-h-I-F-H-a-If-C-a-rr-y-C-Ie-a-r--~---B-H-C-C---+-2-8·-1--2--+--3~-H-=--0---------------------r-.-r-.-r-.-r-.-~
Branch IF Half Carry Set
Branch IF Minus
Branch IF Interrupt Mask
Bit is Clear
I 29
2
3
H= 1
•. 1
•
BPL
2A
2
3
N =0
•
•
BMI
2B
2
3
N= 1
BHCS
Branch IF Plus
•
+--------+----+--\1----+---------BMC
2C
2 I 3
I~O
•
I ••
• • •
I. •
•
,I
I_
I
•
1
I -
, -
I-
I-
Symbols: Op = Operation
# = Number of bytes
= Number of cycles
Table 8 Bit Manipulation Instructions
Addressing Modes
Operations
Mnemonic
1
I
I
Boolean/
Bit Test and Branch Arithmetic
Operation
1::1-[ OP
Bit Set Clear
OP
I
I
1::1-
Branch
Test
H
Branch IF Bit n is set
: BRSET n(n=0···7)
i
!
-
Mn=1
Branch IF Bit n is clear
\ BRCLR n(n=0···7)
I
1 ~315
I
!01+2·n:3:5
-
Mn=O
Set Bit n
I BSET n(n=0···7)
i 10+2·n I 2
Clear Bit n
I BCLR n(n=0-·-7) 111 +2·n j 2
5
1
51
I
I
I
I
1-+Mn
O-+Mn
Condition Code
I
-
i
I
·1·
• •
• •
• •
I
N'-ZTC
•
•
•
•
•
•
• •
• •
/\
II
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
~HITACHI
447
HD6305X1,HD6305X2------------------------------------------------------Table 9
Mnemonic
Operations
Control Instructions
Addressing Modes
Implied
#
-
1
Transfer A to X
TAX
OP
97
Transfer X to A
TXA
9F
1
2
2
A-X
X-A
Set Carry Bit
SEC
99
1
1
l-C
Clear Carry Bit
CLC
98
1
1
O-C
Set Interrupt Mask Bit
SEI
9B
1
1-1
Clear Interrupt Mask Bit
Software Interrupt
CLI
SWI
9A
Return from. Subroutine
RTS
83
81
1
1
2
2
Return from Interrupt
RTI
5
80
1
8
Reset Stack Pointer
RSP
9C
1
2
No-Operation
NOP
90
1
1
Decimal Adjust A
DAA
STOP
80
Stop
1
1
2
4
Wait
WAIT
1
4
Symbols: Op = Operation
# ='Number of bytes
- = Number of cycles
--
0-1
10
1
8E
8F
Condition Code
Boolean Operation
$FF-SP
Advance Prog. Cntr. Only
Converts binary add of BCD charcters Into
BCD format
H
I
Z
C
•
•
•
•
•
•
•
•
?
•
•
•
•
•
• • •
• • •
• • •
•1 • •
• •
0 • •
1
• •
• • •
? ? ?
• • •
• • •
•
• • •
• • •
•
•1
N
1\
--c--
0
•
•
•
•
?
•
•
1\*
1\
•
•
* Are BCD characters of upper byte 10 or more? (They are not cleared if set in advance.)
Table 10 Instruction Set (in Alphabetical Order)
Addressing Modes
Condition Code
Bit
Mnemonic
Indexed
Implied
Immediate
Direct
x
x
x
x
x
x
x
x
ADC
ADD
AND
ASl
ASR
x
x
Extended Relative (No Offset)
x
x
x
x
x
x
x
x
Indexed
Indexed
Set!
Test &
(8-Bit)
(16-Bit)
Clear
Branch
x
x
x
x
x
X
1\
X
1\
x
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
x
BCC
x
BClR
x
x
x
x
x
x
x
x
BCS
BEQ
BHCC
BHCS
BHI
(BHS)
BIH
Bil
BIT
x
x
BLS
BMC
BMI
BMS
BNE
BPL
BRA
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
448
x
x
x
x
x
x
x
x
x
x
(BlO)
Bit
x
x
H
I
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
Z
C
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1\
1\
•
(to be continued)
C
1\
•?
Carry/Borrow
Test and Set if True. Cleared Otherwise
Not Affected
load CC Register From Stack
~HITACHI
---------------------------------------------------------HD6305X1,HD6305X2
Table 10 Instruction Set (in Alphabetical Order)
Condition Code
Addressing Modes
Bit
Indexed
Mnemonic
Implied
Immediate
Direct
Extended Relative (No Offset)
BRN
Bit
Indexed
Indexed
Set
Test &
(S-Bit)
(16-Bit)
Clear
Branch
X
BRCLR
X
BRSET
X
BSET
X
BSR
X
CLC
X
Cli
X
CLR
X
CMP
COM
X
X
X
CPX
X
DEC
X
EOR
X
X
X
X
DAA
INC
X
X
X
X
X
X
X
X
JMP
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
I
X
X
x
X
X
X
LOA
X
X
x
x
X
x
LOX
X
X
X
X
X
X
JSR
LSL
X
X
X
X
LSR
X
X
X
X
NEG
X
X
X
X
NOP
X
ORA
X
X
ROL
X
X
ROR
X
X
RSP
X
RTI
X
RTS
X
SBC
X
X
SEC
X
SEI
X
STA
STOP
X
!
X
X
X
x
X
X
X
X
X
X
X
X
X
X
X
X
X
x
X
X
X
X
X
X
X
X
X
STX
SUB
X
SWI
X
TAX
X
TST
X
TXA
X
WAIT
X
Condition Code Symbols:
H
Half Carry (from Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
X
X
X
H
I
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
• • •
• • •
• • • •
• • • •0
• • •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•
•
•
•
•
C
(\
•
N
Z
C
/\
/\
0
• • •
• 0 1
•
•
•
•
•
•
•
• • •
• • •
•
•
•
• 0
•
• • •
•
•
•
• • •
? ? ?
• • •
•
• • •
1
• •
•
• • •
•
•
1 • •
• • •
•
• • •
• • •
•
/\
/\
/\
/\
1
/\
/\
/\
/\
/\
/\
,\
1\
/\
/\
1\
/\
/\
/\
/\
/\
/\
/,
/\
1\
/\
1\
,1\
/\
/\
/\
/\
/,
/\
/\
/\
/\
/\
/\
/\
•
•
•
•
•
•
•
/\
/\
/\
/\
/\
/\
•
•
/\
/\
•
?
•
/\
1
•
•
•
•
/\
•
•
•
•
•
Carry/Borrow
Test and Set if True. Cleared Otherwise
Not Affected
Load CC Register From Stack
$
HITACHI
449
HD6305X1,HD6305X2----------------------------------------------------Table 11
Bit Manipulation
Branch
Operation Code Map
Control
Read/Modify/Write
Register /Memory
Test &
Set/
Branch
Clear
Rei
OIR
A
X
,Xl
,XO
IMP
0
1
2
3
4
5
6
7
8
9
0
BRSETO
BSETO
BRA
NEG
RTI'·
-
SUB
1
BRCLRO
BCLRO
BRN
.-
RTS'
--
CMP
1
2
BRSETl
BSETl
BHI
--
.-
--
SBC
2
3
BRCLRl
BCLR1
BLS
COM
SWI'
CPX
3
4
BRSET2
BSET2
BCC
LSR
.. -
-
AND
4
..
IMP IMM
A
OIR
EXT
,X2
,Xl
,XO
B
C
0
E
F
+-H IGH
0
5
BRCLR2
BCLR2
BCS
-
--
BIT
5
6
BRSET3
BSET3
BNE
ROR
--
LOA
6
7
BRCLR3
BCLR3
BEQ
ASR
TAX'
STA
STAj+11 7
8
9
BRSET4
BSET4
BHCC
LSl/ASL
CLC
EOR
BRCLR4
BCLR4
BHCS
ROL
SEC
AOC
8
9
A
BRSET5
BSET5
BPL
DEC
CLI*
ORA
A
B
BRCLR5
BCLR5
BMI
SEI*
ADD
C
BRSET6
BSET6
BMC
D
BRCLR6
BCLR6
BMS
E
BRSET7
BSET7
BIL
F
BRClR7
BClR7
BIH
3/5
2/5
2/3
JNOTES)
RSP'
INC
TSTHI
TST(-l)
TST
OAA' NOP BSR'
STOP'
CLR
2i5
1/2
1/2
2/6
WAIT' TXA'
111 2/2
15 1."
B
-C-
JMP(-l)
JSR(+2)
-
JSR(+lJ~~~ 0
7
LOX
STX(+11 F
STX
2/3
L
o
W
3/4 3/5
2/4
1/3
1. "-" is an undefined operation code.
2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles).
The number of cycles for the mnemonics asterisked (+) is as follows:
RTI
8
TAX
2
RTS
5
RSP
2
SWI
10
TXA
2
DAA
2
BSR
5
STOP
4
ell
2
WAIT
4
SEI
2
3. The parenthesized numbers must be added to the cycle count of the particular instruction.
•
WAIT Causes the MCU to enter the wait mode. For this mode,
Additional Instructions
The following new instructions are used on the HD6305X:
DAA Converts the contents of the accumulator into BCD
code.
450
$
see the topic, Wait Mode.
STOP Causes the MCU to enter the stop mode. For this mode,
HITACHI
see the topic, Stop Mode.
HD6305YO,HD63A05YO,--HD63B05YO
CMOS MCU (Microcomputer Unit)
-PRELIMINARVHD6305YO is a CMOS 8-bit single-chip microcomputer
which includes a CPU upward compatible with the HD6305XO.
On the chip of the HD6305YO, 7872 byte ROM, 256 byte RAM,
55 I/O terminals, two timers and a serial communication interface (SCI) are built in. And three low power dissipation modes
(stop, wait and standby) support the low power operating.
Instruction set is upward compatible with the HD6805 family.
HD6305YOP, HD63A05YOP,
HD63B05YOP
• HARDWARE FEATURES
.8-bit based MCU
• 7872 bytes of ROM
.256 bytes of RAM
.A total of 55 terminals, including 32 I/O's, 7 inputs and 16
outputs
.Two timers
8-bit timer with a 7-bit prescaler (programmable prescaler;
event counter)
15-bit timer (commonly used with the SCI clock divider)
• On-chip serial interface circuit (synchronized with clock)
.Six interrupts (two external, two timer, one serial and one
software)
• Low power dissipation. modes
- Wait ... , In this mode, the clock oscillator is on and the
CPU halts but the timer/serial/interrupt function is operatable.
- Stop .... In this mode, the clock stops but the RAM
data, I/O status and registers are held.
- Standby .. In this mode, the clock stops, the RAM data
is held, and the other internal condition is
reset.
.Minimum instruction cycle time
HD6305YO ...'. 1
(f = 1 MHz)
(f = 1.5 MHz)
- HD63A05YO .... 0.67
(f -= 2 MHz)
- HD63B05YO .... 0.5
• Wide operating range
VCC 3 to 6V (f 0.1 to 0.5 MHz)
HD6305YO
f = 0.1 to 1 MHz (VCC 5V ± 10%)
HD63A05YO .... f
0.1 to 1.5 MHz (VCC 5V ± 100h)
HD63B05YO .... f 0.1 to 2 MHz (VCC 5V ± 100h)
.System development fully supported by an evaluation kit
"'S
"'S
"'S
=
=
=
=
(DP-64S)
_HD6305YOF, HD63A05YOF,
HD63B05YOF
(FP-64)
• Three new instructions, STOP, WAIT and DAA, added to the
HD6805 family instruction set
• Instructions that are upward compatible with those of Motorola's MC6805P2 and MC146805G2
=
=
=
• SOFTWARE FEATURES
.Similar to HD6800
• Byte efficient instruction set
• Powerful bit manipulation instructions (Bit Set, Bit Clear, and
Bit Test and Branch usable for 192 byte RAM bits within page
o and all I/O terminals)
• A variety of interrupt operations
.Index addressing mode useful for table processing
• A variety of conditional branch instructions
• Ten powerful addressing modes
• All addressing modes adaptable to RAM, and I/O instructions
~HITACHI
451
HD6305YO.HD63A05YO.HD63B05YO------------~----------------~~-----------
• PIN ARRANGEMENT
• HD6305YOP, HD63A05YOP, HD63B05YOP
•
~Go
VSS.£::: 0
RES·C
~G,
INT
DG 2
G3
STBY
XTAL
G4
EXTAL
Gs
NUM
Gs
TIMER
G7
F7
A7
Fs
As
Fs
As
A4
F4
A3l
F3
F%
A2
A,
F,
Ao
Fo
B7
E7
B6
E,
Bs
Es
B4
E4
B3
E3
B2
E2
B,
E,
Bo
Eo
C7/ Tx
07
C6/ Rx
0,/INT 2
Cs/CK
Os
C4
04
C3
03
C2
O2
C,
0,
Co ~______________' - Vee
HD6305YOF, HD63A05YOF, HD63B05YOF
L-
B5
B4
B3
B2
B,
Bo
C7/Tx
C6/Rx
(Top View)
(Top View)
•
BLOCK DIAGRAM
XTAL
EXTAL
RES
NUM
iiiiT
SriW
TIMER
Accumulator
8
PortA
I/O
Terminals
8
A
Index
Register
CPU
0,
O./iNT;""
Control
x
Condition Code
Register ·cc
Stack
CPU
Port B
I/O
Terminals
0,
D.
0,
0,
0,
Port 0
Input
Terminals
Eo
E,
E,
E,
E.
E.
E.
E,
Port E
Output
Terminals
Fo
F,
F,
F,
F.
F,
F.
F,
Port F
Output
Terminals
Go
·1
II:
c
0
.;:;
CIS
~·t
II:
G,
Go
Go
Go
Go
Go
G,
452
~HITACHI
PortG
I/O
Terminals
----------------------------------------------HD6305YO,HD63A05YO,HD63B05YO
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Supply voltage
Vee
-0.3 - +7.0
V
Input voltage
Vin
-0.3 - Vee + 0.3
V
Operating temperature
Topr
0-+70
°c
Storage temperature
T stg
-55 - +150
°c
[NOTE)
These products have a protection circuit in their input terminals against high electrostatic voltage or high electric fields. Notwithstanding,
be careful not to apply any voltage higher than the absolute maximum rating to these high input impedance circuits. To assure normal
operation, we recommended Vin, Vout ; Vss ~ (Vin or Vout ) ~ Vee .
• ELECTRICAL CHARACTERISTICS
• DC Characteristics (Vee
SymDol
Item
Input
voltage
"High"
=5.0V ± 10%, Vss =GND and T. = 0 ,... +70°C unless otherwise specified)
Test
condition
AES,S'fBV
EXTAL
VIH
min
typ
max
Unit
Vee- 0.5
-
Vee+ 0.3
V
Vee+ 0.3
V
Vee+ 0.3
V
0.8
V
5
10
mA
2
Vee x 0.7
Others
Input voltage "Low"
All Input
2.0
VIL
-0.3
5
rnA
lee
-
2
10
IlA
2
10
IlA
-
-
1
IlA
-
-
1
Il A
-
-
12
pF
Operating
Current
dissipation
Wait
= 1MHz*
f
Stop
Standby
Input
leakage
current
TIMER,
INT,
~-D7'
Threestate
current
Ao -A 7 ,
Bo - B7 ,
Co -C 7 ,
Go -G 7 ,
Eo-E7**
Fo - F7**
Input
capacity
All
terminals
IIILI
BY
Vin
IITSII
Cin
=0.5-
Vee - 0.5V
=
1MHz,
Vin OV
f
=
• The value at f = xMHz can be calculated by the following equation:
•• At standby mode
ICC
(f
= xMHz) = Icc (f = 1MHz) multiplied by x
~HITACHI
453
HD630SYO,HD63AOSYO,HD63BOSYO---------------------------------------------• AC Characteristics (Vee = 5.0V ± 10%, Vss = GND and T. = 0 - +70°C unless otherwise specified)
HD63A05YO
HD6305YO
Test
condition
Symbol
Item
min
typ
max
min
typ
HD63B05YO
max
min
typ
Unit
max
Clock
frequency
fcl
0.4
-
4
0.4
-
6
0.4
-
8
MHz
Cycle time
tCYC
1.0
-
10
0.666
-
10
0.5
-
10
p.s
-
-
tcyc
+200
-
-
ns
INT pulse
width
tlWL
tcsc
+2 0
-
-
tcyc
+200
INT2 pulse
width
tlwL2
tcyc
+250
-
-
tcyc
+200
-
-
tcyc
+200
-
-
ns
RES pulse
width
tRWL
5
-
-
5
-
-
5
-
-
t cvc
TIMER pulse
width
tTWL
tcyc
+250
-
-
tcyc
+200
-
-
tcyc
+200
-
-
ns
Oscillation
start time
(crystal)
tose
=22pF ±
200,.6
Rs = 60n
max
-
-
20
-
-
20
-
-
20
ms
Reset delay
time
tRHL
External cap.
2.2p.F
80
-
-
80
-
-
80
-
-
ms
CL
• Port Electrical Characteristics (Vee
=5.0V ± 10%, Vss =GND and Ta =0 -
Item
Output voltage "High"
Output voltage "Low"
Ports A,
B,C,D,
G
max
IOH = -200p.A
2.4
-
-
V
IOH = -10p.A
Vee - 0.7
-
-
V
IOL = 1.6mA
-
-
0.55
V
VIH
2.0
-
Vee + 0.3
V
V IL
-0.3
-
0.8
V
-1
-
1
p.A
Vin=0.5Vee - 0.5V
IlL
Unit
(Vee = 5.0V±10%, Vss= GND and Ta= 0 - +70°C unless otherwise specified)
Item
Clock ~ycle
Data Output Delay Time
Symbol
!~c
tTXD
Data Set-up Time
tSRX
Data Hold Time
tHRX
4S4
typ
VOL
Input leakage current
• SCI Timing
min
VO H
Input voltage "High"
Input voltage "Low"
Test
condition
Symbol
Ports A,
B,C,G,
E,F
+70°C unless otherwise specified)
Test
Condition
Fig. 1,
Fig. 2
HD63A05YO
HD6305YO
min
typ
1
-
-
-
200
100
max
min
32768 0.67
250
-
-
200
~HITACHI
100
HD63B05YO
Unit
typ
max
min
typ
max
-
21845
0.5
-
16384
p.s
250
-
-
250
ns
-
200
-
-
100
-
-
ns
ns
-----------------------HD6305YO,HD63A05YO,HD63B05YO
-INT,INT2
External interrupt request inputs to the HD6305YO. For
details, refer to "INTERRUPTS". The INT2 tenninal is also
used as the port D6 tenninal.
Clock Output
Cs/a<
Data Output
- XT AL, EXT AL
C1/ T X
==f:ov
ts.~x
Data Input
C./Rx
tHRX - _ .. _-
j
20V'
1
,...!LS""'V_ _ _ _ _---'O;.;.;,S:..:,.V~I-(- - - -
These tenninals provide input to the on-chip clock circuit.
A crystal oscillator (AT cut, 2.0 to 8.0 MHz) or ceramic
mter is connected to the terminal. Refer to "INTERNAL
OSCILLATOR" for using these input tenninals.
-TIMER
Figure 1 SCI Timing (Internal Clock)
This is an input tenninal for event counter. Refer to
"TIMER" for details.
-RES
Used to reset the MCU. Refer to "RESET" for details.
-NUM
This terminal is not intended for user applications. It must
be grounded to VSS.
-Input/Output Terminals (Ao ,.., A7, Bo ,.., B7, Co ,.., C7 , Go ,..,
G,)
These 32 tenninals consist of four 8-bit I/O ports (A, B, C,
G). Each of them can be used as an input or output tenninal
on a bit through program control of the data direction register.
For details, refer to "I/O PORTS."
Figure2 SCI Timing(External Clock)
Vcc
-Input Terminals (01 ,.., 07)
These seven input-only terminals are TTL or CMOS compatible. Of the port D's, D6 is also used as INT2. If D6 is
used as a port, the INT2 interrupt mask bit of the miscellaneous register must be set to ~'1" to prevent an INT2 interrupt
from being accidentally accepted.
TTL Load
2.4kQ
(Port)
10L= 1.6mA
Test point
terminal o---~t---""'----i'IIt----,
40pF
12kQ
- Output Terminals (Eo"" E7, Fo - F7)
These 16 output-only terminals are TTL or CMOS compatible.
-STBY
[NOTES J 1. The load capacitance in eludes stary capacitance caused
by the probe, etc.
2. All diodes are 152074
®
Figure 3 Test Load
This terminal is used to place the MCU into the standby
mode. With STBY at "Low" level, the oscillation stops and
the internal condition is reset. For details, refer to "Standby
Mode."
The tenninals described in the following are I/O pins for
serial communication interface (SCI). They are also used as
ports Cs , C6 and C7 • For details, refer to "SERIAL COMMUNICATION INTERFACE."
• DESCRIPTION OF TERMINAL FUNCTIONS
The input and output signals of the HD6305YO are described
here.
-CK (Cs)
Used to input or output clocks for serial operation.
-Vee, Vss
Voltage is applied to the HD6305YO through these two
tenninals. Vee is S.OV ± 10%, while Vss is grounded.
-Rx (C6)
Used to receive serial data.
-Tx (C7)
Used to transmit serial data.
$
HITACHI
455
HD6305YO,HD63A05YO,HD63B05YO-----------------------------------------------MEMORY MAP
The memory map of the HD6305YO MCU is shown in
Fig. 4. During interrupt processing, the contents of the MCU
registers are saved into the stack in the sequence shown in
Fig. 5. This saving begins with the lower byte (peL) of the
program counter. Then the value of the stack pointer is
decremented and the higher byte (PCH) of the program
counter, index register (X), accumulator (A) and condition
code register (CC) are stacked in that order. In a subroutine
call, only the contents of the program counter (PCH and PCL)
are stacked.
-REGISTERS
There are five registers which the programmer can operate.
63
64
0
1
2
3
4
5
6
7
$0000
1/0 Ports
Timer
SCI
roo
$003F
Stack
$gOFF
$ 100
RAM
(64Bytes)
8
\
$013F
319
320
$0140
~----------
8191
8192
Interrupt
Vectors
PORT
PORT
PORT
PORT
A
B
C
0
PORT A DDR
PORT BOOR
PORT C DDR
PORT G DDR
Timer Data Reg
9
10
11
12
13
Timer CTRL Reg
16
17
18
SCI CTRL Reg
ROM
(7,872Bytes)
8182
Index
/ Register
X
' - -_ _ _ _ _ _ _ _..1
13
I
~
o
Program
_______________
---,.Counter
PC
/
6 5
0
1~0_1~0.10~1_0~10.10~1~1~I_l~I____s_p____~I~~~~r
RAM
(192Bytes)
255
256
o
7
I
13
o
o
7
I'--_ _ _ _A_ _ _ _....1Accumulator
Misc Reg
PORT E
PORT F
PORT G
$00
$01
$02
$03·"
$04"
$05"
$06"
$1FFF
$2000
SCI STS Reg
SCI Data Reg
$08
$09
$OA
$3FFF
Figure 4
$10
$11
$12
$3F
" Write only regi ster
." Read only regis ter
Memory Map of H06305YO MCU
Carry
Figure 6
Programming Model
$00
Not Used
16383
~-----Half
SOB
SOC
Not Used
63
'-----Negative
'------Interrupt
Mask
$Or
Not Used
$1FF6
~ggX~
Zero
• Accumulator (A)
This accumulator is an ordinary 8-bit register which holds
operands or the result of arithmetic operation or data processing.
• Index Register (X)
The index register is an 8-bit register, and is used for index
addressing mode. Each of the addresses contained in the
register consists of 8 bits which, combined with an offset
value, provides an effective address.
In the case of a read/modify/write instruction, the index
register can be used like an accumulator to hold operation
data or the result of operation.
If not used in the index addressing mode, the register can
be used to store data temporarily.
• Program Counter (PC)
The program counter is a 14-bit register that contains the
address of the next instruction to be executed.
I
76543210
Condition
n-4 1 1 1
n+l
Code Register
n-3
Accumulator
n+2
n-2
Index Register
n+3
n-l 1 1
n
I
PCW
PCl"
Pull
n+4
n+5
Push
• In a subroutine call, only PCl and PCH are stacked.
Figure 5
456
Sequence of Interrupt Stacking
• Stack Pointer (SP)
The stack pointer is a 14-bit register that indicates the address of the next stacking space. Just after reset, the stack
pointer is set at address $OOFF. It is decremented when data
is pushed, and incremented when pulled. The upper 8 bits
of the stack pointer are fIXed to 00000011. During the MCU
being reset or during a reset stack pointer (RSP) instruction,
the pointer is set to address $OOFF. Since a subroutine or
interrupt can use space up to address $OOCI for stacking, the
subroutine can be used up to 31 levels and the interrupt up
to 12 levels.
• Condition Code Register (CC)
The condition code register is a 5-bit register, each bit
indicating the result of the instruction just executed. The
bits can be individually tested by conditional branch instruc-
~HITACHI
----------------------------------------------HD6305YO,HD63A05YO,HD63B05YO
tions. The CC bits are as follows:
Half Carry (H): Used to indicate that a carry occurred between bits 3 and 4 during an arithmetic operation (ADD, ADC).
Interrupt (I): Setting this bit causes all interr ·,ts, except
a software interrupt, to be ma~"ed. If an
interrupt occurs with the bit I set, it is
latched. It will be processed the instant
the interrupt mask bit is reset. (More specifically, it will enter the interrupt processing
routine after the instruction following the
CLI has been executed.)
Negative (N): Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is negative (bit 7 is logic
"1 ").
Z~ro (Z):
Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is zero.
Carry I
Represents a carry or borrow that occurred
Borrow (C): in the most recent arithmetic operation. This
bit is also affected by the Bit Test and Branch
instruction and a Rotate instruction.
-INTERRUPT
There are six different types of interrupt: external interrupts (INT, INTz), internal timer interrupts (TIMER,
TIMER2), serial interrupt (SCI) and interrupt by an instruction (SWI).
Of these six interrupts, the INT2 and TIMER or the SCI
and TIMER2 generate the same vector address, respectively.
When an interrupt occurs, the program in progress stops
and the then CPU status is saved onto the stack. And then,
the interrupt mask bit (I) of the condition code register is
set and the start address of the interrupt processing routine
is obtained from a particular interrupt vector address. Then
the interrupt routine starts from the start address. System
can exit from the interrupt routine by an RTI instruction.
When this instruction is executed, the CPU status before
the interrupt (saved onto the stack) is pulled and the CPU
restarts the sequence with the instruction next to the one at
which the interrupt occurred. Table 1 lists the priority of
interrupts and their vector addresses.
Table 1
Interrupt
Priority of Interrupts
Priority
Vector Address
RES
1
$1 FFE,
$1FFF
SWI
2
$1FFC,
$1FFD
INT
3
$1FFA,
$1FFB
TIMER/INT2
4
$1FF8,
$1FF9
SCI/TIMERz
5
$1FF6,
$1FF7
A flowchart of the interrupt sequence is shown in Fig. 7.
A block diagram of the interrupt request source is shown in
Fig. 8.
y
TNT
y
fNf2
y
1 .... 1
$FF .... SP
O.... DDR·S
CLR INT Logic
$FF ....TDR
$7F ....Timer Prescaler
$50 ....TCR
$3F .... SSR
$OO ....SCR
TIMER
Y
SCI
$7F-+MR
Figure 7
Interrupt Flowchart
~HITACHI
457
HD6305YO,HD63A05YO,HD63B05YO--------------------------------------------In the block diagram, both the external interrupts INT and
INT2 are edge trigger inputs. At the falling edge of each input,
an interrupt request is generated and latched. The INT interrupt request is automatically cleared if jumping is made to
the INT processing routine. Meanwhile, the INT2 request is
cleared if "0" is written in bit 7 of the miscellaneous register.
For the external interrupts (INT, INT2), internal timer
interrupts (TIMER, TIMER2) and serial interrupt (SCI), each
interrupt request is held, but not processed, if the I bit of the
condition code register is set. Immediately after the I bit is
cleared, the corresponding interrupt processing starts according to th!.E!!0rity.
The INT2 interrupt can be masked by setting bit 6 of the
miscellaneous register; the TIMER interrupt by setting bit 6
of the timer control register; the SCI interrupt by setting bit
5 of the serial status register; and the TIMER2 interrupt by
setting bit 4 of the serial status register.
The status of the INT terminal can be tested by a BIL or
BIH instruction. The INT falling edge detector circuit and
its latching circuit are independent of testing by these instructions. This is also true with the status of the INT2 terminal.
Bit 7 of this register is the INT2 interrupt request flag.
When the falling edge is detected at the INT2 terminal, "I"
is set in bit 7. Then the software in the interrupt routine
(vector addresses: $IFF8, $IFF9) checks bit 7 to see if it
is INT2 interrupt. Bit 7 can be reset by software.
Miscellaneous Register (MR;$OOOA)
76543210
1M R71MR61Z1Z1ZlZV1ZJ
t
f
L __________
INT2 Interrupt Mask
' - - - - - - - - - - - - - INTl Interrupt Request Flag
Bit 6 is the INT2 interrupt mask bit. Ifthis bit is set to "1",
then the INT2 interrupt is disabled. Both read and write are
possible with bit 7 but "I" cannot be written in this bit by
software. This means that an interrupt request by software
is impossible.
When reset, bit 7 is cleared to "0" and bit 6 is set to "I" .
• Miscellaneous Register (MR; $OOOA)
The interrupt vector address for the external interrupt
INT2 is the same as that for the TIMER interrupt, as shown
in Table I. For this reason, a special register called the miscellaneous register (MR; $OOOA) is available to control the
INT2 interrupts.
-TIMER
Figure 9 shows an MCU timer block diagram. The timer
data register is loaded by software and, upon receipt of a
clock input, begins to count down. When the timer data
Vectoring generated
$1FFA,$1FFB
BIH/BIL Test
Condition Code Register (CC)
INT Interrupt Latch
INT
Falling Edge Detector
l
Miscellaneous
Register (MR)
)-----4I~f----
Vectoring generated
$1FF8,$1FF9
TIMER
Serial Status
Register (SSR)
SCI/TIMER2
) - - - . - - - - - Vectoring generated
$1FF6,$1FF7
Figure 8
458
Interrupt Request Generation Circuitry
$
HITACHI
----------------------------------------------HD6305YO,HD63A05YO,HD63B05YO
register (TDR) becomes "0", the timer interrupt request
bit (bit 7) in the timer control register is set. In response to
the interrupt request, the MCV saves its status into the stack
and fetches timer interrupt routine address from addresses
$1 FF8 and $1 FF9 and execute the interrupt routine. The
timer interrupt can be masked by setting the timer interrupt
mask bit (bit 6) in the timer control register. The mask bit
(I) in the condition code register can also mask the timer
interrupt.
The source clock to the timer can be either an external
signal from the timer input terminal or the internal E signal
(the oscillator clock divided by 4). If the E signal is used as
the source, the clock input can be gated by the input to the
timer input terminal.
Once the timer count has reached "0", it starts counting
down with "$FF". The count can be monitored whenever
desired by reading the timer data register. This permits the
program to know the length of time having passed after the
occurrence of a timer interrupt, without disturbing the contents of the counter.
When the MCV is reset, both the prescaler and counter are
initialized to logic "1". The timer interrupt request bit
(bit 7) then is cleared and the timer interrupt mask bit (bit
6) is set.
To clear the timer interrupt request bit (bit 7), it is necessary to write "0" in that bit.
TCR7
Timer interrupt request
o
Absent
• Timer Control Register (TCR, $0009)
Selection of a clock source, selection of a prescaler frequency division ratio, and a timer interrupt can be controlled
by the timer control register (TCR; $0009).
For the selection of a clock source, anyone of the four
modes (see Table 2) can be selected by bits 5 and 4 of the
timer control register (TCR).
Timer Control Register (TCR; $0009)
4
' - - - - - - - - - - - - - - Timer interrupt mask
' - - - - - - - - - - - - - - - - - - - T i m e r interrupt request
After reset, the TCR is initialized to "E under timer terminal control" (bit 5 = 0, bit 4 = 1). If the timer terminal is
"1 ", the counter starts counting down with "$FF" immediately after reset.
When "1" is written in bit 3, the prescaler is initialized.
This bit always shows "0" when read.
Table 2
TCR
Clock Source Selection
Clock input sour:ce
Bit 5
Bit4
0
0
I nternal clock E
Present
TCR6
Timer interrupt mask
0
1
E under timer terminal control
o
Enabled
1
0
No clock input (counting stopped)
Disabled
1
1
Event input from timer terminal
Initialize
(Internal
Clock)
E --/---j
3
Timer Data
Register
....._ _..,..._ _ _ _,.-_ _-' Timer Interrupt
Write
Read
Figure 9
Timer Block Diagram
~HITACHI
459
HD6305YO,HD63A05YO,HD63B05YO-----------------_ _ _ __
A prescaler division ratio is selected by the combination of
three bits (bits 0, 1 and 2) of the timer control register (see
Table 3). There are eight different division ratios; +1, +2, +4,
+8, +16, +32, +64 and +128. After reset, the TCR is set to the
+1 mode.
Table 3
Prescaler Division Ratio Selection
TCR
Bit2
Bit 1
BitO
Prescaler division ratio
0
0
0
+1'
0
0
1
+2
0
1
0
+4
0
1
1
+8
1
0
0
+16
1
0
1
+32
1
1
0
+64
1
1
1
+128
A timer interrupt is enabled when the timer interrupt mask
bit is "0", and disabled when the bit is "1". When a timer
interrupt occurs, "1" is set in the timer interrupt request bit.
This bit can be cleared by writing "0" in that bit.
-SERIAL COMMUNICATION INTERFACE (SCI)
This interface is used for serial transmission or reception
of 8~bit data. Sixteen transfer rates are available in the range
from IllS to approx. 32 ms (for oscillation at 4 MHz).
The SCI consists of three registers, one eighth counter and
one prescaler. (See Fig. 10.) SCI communicates with the CPU
via the data bus, and with the outside world through bits 5,
6 and 7 of port C. Described below are the operations of
each register and data transfer.
eSCI Control Register (SCR; $0010)
SCI Control Registers (SCA; $0010)
E
_....
.....
Transfer
Clock
_ - - ' Generator
Initialize
SCI Status Registers
(SSR :$0011 )
Not Used
SCITIMER2
Figure 10
460
SCI Block Diagram
~HITACHI
---------------------------------------------HD6305YO,HD63A05YO,HD63B05YO
Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set upon
completion of transmitting or receiving 8-bit data. It is
cleared when reset or data is written to or read from the
SCI data register with the SCRS=" I". The bit can also be
cleared by writing "0" in it.
C7 terminal
SCR7
o
Used as I/O terminal (by DDR).
Serial data output (DDR output)
Bit 6 (SSR6)
Bit 6 is the TIMER2 interrupt request bit. TIMER2 is used
commonly with the serial clock generator, and SSR6 is set
each time the internal transfer clock falls. When reset, the
bit is cleared. It also be cleared by writing "0" in it. (For
details, see TIMER2')
C6 terminal
SCR6
o
Used as I/O terminal (by DDR).
Serial data input (DDR input)
SCR5 SCR4
Clock source
C s terminal
0
0
-
-0
1
-
1
0
Internal
Clock output (DDR output)
1
1
External
Clock input (DDR input)
Used as I/O terminal (by
DDR).
Bit 7 (SCR7)
When this bit is set, the DDR corresponding to the C7
becomes "1" and this terminal serves for output of SCI data.
After reset, the bit is cleared to "0".
Bit 6 (SCR6)
When this bit is set, the DDR corresponding to the C6
becomes "0" and this terminal serves for input of SCI data.
After reset, the bit is cleared to "0" .
Bit S (SSRS)
.Bit S is the SCI interrupt mask bit which can be set or
cleared by software. When it is "1", the SCI interrupt (SSR7)
is masked. When reset, it is set to "1".
Bit 4 (SSR4)
Bit 4 is the TIMER2 interrupt mask bit which can be set
or cleared by software. When the bit is "I", the TIMER2
interrupt (SSR6) is masked. When reset, it is set to "I".
Bit 3 (SSR3)
When "1" is written in this bit, the prescaler of the transfer
clock generator is initialized. When read, the bit always is "0".
Bits 2,..., 0
Not used.
SSR7
o
Bits Sand 4 (SCRS, SCR4)
These bits are used to select a clock source. After reset,
the bits are cleared to "0".
0
SCR2
0
SCR1
0
SCRO
0
Absent
Present
SSR6
Bits 3,..., 0 (SCR3 ,..., SCRO)
These bits are used to select a transfer clock rate. After
reset, the bits are cleared to "0".
SCR3
SCI interrupt request
o
TIMER2 interrupt request
Absent
Present
Transfer clock rate
4.00 MHz
4.194 MHz
SSR5
0.9511S
o
1 I1S
0
0
0
1
211s
1.9111S
0
1
0
411S
3.8211S
0
0
1
1
811s
7.6411s
SSR4
1
1
1
1
1
1
o
1
1
1
1
3276811S
1/32 s
eSCI Status Register (SSR; S0011)
76543210
ISSR7ISSR6ISSR5ISSR4ISSR3~
Enabled
Disabled
0
eSCI Data Register (SDR; $0012)
A serial-parallel conversion register that is used for transfer
of data.
SCI interrupt mask
TIMER2 interrupt mask
Enabled
Disabled
• Data Transmission
By writing the desired control bits into the SCI control
registers, a transfer rate and a source of transfer clock are
determined and bits 7 and S of port C are set at the serial
data output terminal and the serial clock terminal, respectively. The transmit data should be stored from the accumulator or index register into the SCI data register. The data
written in the SCI data register is output from the C7 /Tx
terminal, starting with the LSB, synchronously with the
falling edge of the serial clock. (See Fig. 11.) When 8 bits of
~HITACHI
461
HD6305YO,HD63A05YO,HD63B05YO--------------------------------------------data have been transmitted, the interrupt request bit is set in
bit 7 of the SCI status register with the rising edge of the
last serial clock. This request can be masked by setting bit 5
of the SCI status register. Once the data has been sent, the 8th
bit data (MSB) stays at the C7/Tx terminal. If an external
clock source has been selected, the transfer rate determined by
bits 0 - 3 of the SCI control register is ignored, and the Cs/
CK terminal is set as input. If the internal clock has been
selected, the Cs/CK terminal is set as output and clocks are
output at the transfer rate selected by bits 0 '" 3 of the SCI
control register.
Figure 11 SCI Timing Chart
• Data Reception
By writing the desired control bits into the SCI control
register, a transfer rate and a source of transfer clock are determined and bit 6 and 5 of port C are set at the serial data
input terminal and the serial clock terminal, respectively.
Then dummy-writing or -reading the SCI data register, the
system is ready for receiving data. (This procedure is not
needed after reading subsequent received data. It must be taken
after reset and after not reading subsequent received data.)
The data from the C6 /Rx terminal is input to the SCI
data register synchronously with the rising edge of the
serial clock (see Fig. II). When 8 bits of data have been received, the interrupt request bit is set in bit 7 of the SCI
status register. This request can be masked by setting bit 5
of the SCI status register. If an external clock source have been
selected, the transfer rate determined by bits 0 '" 3 of the SCI
control register is ignored and the data is received synchronously with the clock from the Cs /CK terminal. If the internal
clock has been selected, the Cs/CK terminal is set as output
and clocks are output at the transfer rate selected by bits 0 '"
3 of the SCI control register.
TIMER2 is commonly used with the SCI transfer clock
generator. If wanting to use TIMER2 independently of the
SCI, specify "External" (SCR5 = 1, SCR4 = 1) as the SCI
clock source.
If "Internal" is selected as the clock source, reading or
writing the SDR causes the prescaler of the transfer clock
generator to be initialized.
-I/O PORTS
There are 32 input/output terminals (ports A, B, C, G).
Each I/O terminal can be selected for either input or output
by the data direction register. More specifically, an I/O port
will be input if "0" is written in the data direction register,
and output if "1" is written in the data direction register.
Port A, B or C reads latched data if it has been programmed
as output, even with the output level being fluctuated by the
output load. (See Fig. 12-a.) For port G, in such a case, the
level of the pin is always read when it is read. (See Fig. 12-b.)
This implies that, even when "1" is being output, port G may
read "0" if the load condition causes the output voltage to
decrease to below 2 .OV .
When reset, the data direction register and data register go
to "0" and all the input/output terminals are used as input.
Bit of data
direction
register
Bit of
output
data
1
0
1
CD
CD
0
X
a. Ports A, Band C
@@
: Transfer clock generator is reset and mask bit (bit
4
of SCI status register! is cleared.
®.@ : TIMER2 interrupt request
@.@ : T1MER2 interrupt request bit cleared
b. Port G
Figure 12
462
1
3-state
_ ___Jr---.::;,L
®@
-----'!. . ._----'r---~t'-
0
1
.TIMER2
The SCI transfer clock generator can be used as a timer.
The clock selected by bits 3 '" 0 of the SCI control register
(4 JlS '" approx. 32 ms (for oscillation at 4 MHz)) is input to
bit 6 of the SCI status register and the TIMER2 interrupt
request bit is set at each falling edge of the clock. Since interrupt requests occur periodically, TIMER2 can be used as a
reload counter or clock.
Status of
output
$
HITACHI
Input/Output Port Diagram
Input to
CPU
0
1
Pin
-----------------------------------------------HD6305YO,HD63A05YO,HD63B05YO
There are 16 output-only terminals (ports E and F). Each
of them can also read. In this case, latched data is read even
with the output terminal level being fluctuated by the output
load (as with ports A, B and C).
When reset, "Low" level is output from each output terminal.
Seven input-only terminals are available (port D). Writing
to an input terminal is invalid.
All input/output terminals, output terminals and input
terminals are TTL compatible and CMOS compatible in respect of both input and output.
If I/O ports or input ports are not used, they should be
connected to Vss via resistors. With none connected to these
terminals, there is the possibility of power being consumed
despite that they are not used.
6 EXTAL
iO-:,I-OM-H-Zc::J
.......-5-t XTAL
HD6305YO
MCU
10-22pF±20%
Crystal Oscillator
HD6305YO
MCU
-RESET
The MCU can be reset either by external reset input (RES)
or power-on reset. (See Fig. 13.) On power up, the reset
input must be held "Low" for at least 30 ms to assure that the
internal oscillator is stabilized. A sufficient time of delay can
be obtained by connecting a capacitance to the RES input as
shown in Fig. 14.
External
Ceramic Oscillator
Clock
Input 6 EXTAL
NC 5 XTAL HD6305YO
MCU
5V
Vcc
OV
RES
Terminal
V
----------------~
-
tRHL
External Clock Drive
~VIH
RES
C1
~::;;al----__--------------~
Figure 13
C~
s
Power On and Reset Timing
XTAL
5
Co
Figure 16
100kSl typ 2
vcc
I nternal Oscillator Circuit
Figure 15
I---
AT Cut
Parallel
Resonance
Co=7pF max.
EXTAL
f=2.0-S.0MHz
6
Rs=600 max.
Parameters of Crystal
~"V\./'v"""'I-----,
RES*2.2.uF
HD6305YO
(a)
MCU
Figure 14
Input Reset Delay Circuit
-INTERNAL OSCILLATOR
The internal oscillator circuit is designed to meet the
requirement for minimum external configurations. It can be
driven by connecting a crystal (AT cut 2.0 '" 8.0MHz) or
ceramic oscillator between pins 5 and 6 depending on the requited oscillation frequency stability.
Three different terminal connections are shown in Fig. 15.
Figs. 16 and 17 illustrate the specifications and typical arrangement of the crystal, respectively.
[NOTE) Use as short wirings as possible for connection of the crystal
with the EXTAL and XTAL terminals. Do not allow these
wirings to cross others.
~HITACHI
Figure 17
Typical Crystal Arrangement
463
"HD6305YO,HD63A05YO,HD63B05YO----------------------------------------------LOW POWER DISSIPATION MODE
The HD6305YO has three low power dissipation modes:
wait, stop and standby.
• Wait Mode
When WAIT instruction being executed, the MCU enters
into the wait mode. In this mode, the oscillator stays active
but the internal clock stops. The CPU stops but the peripheral
functions - the timer and the serial communication interface - stay active. (NOTE: Once the system has entered the
wait mode, the serial communication interface can no longer
be retriggered.) In the wait mode, the registers, RAM and I/O
terminals hold their condition just before entering into the
wait mode.
The escape from this mode can be done by interrupt (INT,
TIMER/INT2 or SCI/TIMER2), RES or STBY. The RES
resets the MCU and the STBY brings it into the standby
mode. (This will be mentioned later.)
When interrupt is requested to the CPU and accepted, the
wait mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt routine. If the interrupt is
masked by the I bit of the condition code register, after releasing from the wait mode the MCU executes the instruction
next to the WAIT. If an interrupt other than the INT (Le.,
TIMER/INT2 or SCI/TIMER2) is masked by the timer control
register, miscellaneous register or serial status register, there
is no interrupt request to the CPU, so the wait mode cannot
be released.
Fig. 18 shows a flowchart for the wait function.
• Stop Mode
When STOP instruction being executed, MCU enters into
the stop mode. In this mode, the oscillator stops and the CPU
and peripheral functions become inactive but the RAM,
registers and I/O terminals hold their condition just before
464
$
entering into the stop mode.
The escape from this mode can be done by an external
interrupt (00 or INT2), RES or STBY. The RES resets the
MCU and the STBY brings into the standby mode.
When interrupt is requested to the CPU and accepted,
the stop mode escapes, then the CPU is brought to the operation mode and vectors to the interrupt routine. If the inter-"
rupt is masked by the I bit of the condition code register,
after releasing from the stop mode, the MCU executes the
instruction next to the STOP. If the INT2 interrupt is masked
by the miscellaneous register, there is no interrupt request to
the MCU, so the stop mode cannot be released.
Fig. 19 shows a flowchart for the stop function. Fig. 20
shows a timing chart of return to the operation mode from
the stop mode.
For releasing from the stop mode by an interrupt, oscillation starts upon input of the interrupt and, after the internal
delay time for stabilized oscillation, the CPU becomes active.
For restarting by RES, oscillation starts when the RES goes
"0" and the CPU restarts when the RES goes "1". The duration of RES="O" must exceed 30 ms to assure stabilized oscillation.
• Standby Mode
The MCU enters into the standby mode when the STBY
terminal goes "Low". In this mode, all operations stop and
the internal condition is reset but the contents of the RAM are
hold. The I/O terminals turn to high-impedance state. The
standby mode should escape by bringing STBY "High". The
CPU must be restarted by reset. The timing of input signals
at the RES and STBY terminals is shown in Fig. 21.
Table 4 lists the status of each parts of the MCU in each
low power dissipation modes. Transitions between each mode
are shown in Fig. 22.
HITACHI
----------------------------------------------HD6305YO,HD63A05YO,HD63B05YO
Oscillator Active
Timer and Serial
Clock Active
All Other Clocks
Stop
Initialize
CPU, TIMER, SCI,
I/O and All
Other Functions
No
No
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 18
Wait Mode Flow Chart
~HITACHI
465
Oscillator and
All Clocks Stop.
No
Turn on Oscillator
Wait for Time Delay
to Stabilize
Turn on Oscillator
Wait for Time Delay
to Stabilize
1=0
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 19
466
$
Stop Mode Flow Chart
HITACHI
~~~~~~~~~~~~~~~~~~~~~~-HD6305YO,HD63A05YO,HD63B05YO
O·":~'~I~:~~I~~~~
I
Time required for oscillation to become
Interrupt
STOP instruction
executed
stabilized (built-in delay time)
restart
(a) Restart by Interrupt
Oscillator IIIII111111111111111111111111
E
~Ir----+----'
Time required for oscillation to become
stabilized (toscl
STOP instruction
executed
Reset
start
RES
(b) Restart by Reset
Figure 20
Timing Chart of ReleaSing from Stop Mode
\
RES
I
H
i
I
I
I
I
I
I __ I
~_.l_-L.
\
tosc
Figure 21
Table 4
Restart
Timing Chart of Releasing from Standby Mode
Status of Each Part of MCU in Low Power Dissipation Modes
Condition
Start
Mode
WAIT
-
Software
STOP
Standby
Hardware
CPU
Timer,
Serial
Register
RAM
I/O
terminal
Active
Stop
Active
Keep
Keep
Keep
STOP instruction
Stop
Stop
Stop
Keep
Keep
Keep
STBY="Low"
Stop
Stop
Stop
Reset
Keep
High impedance
Oscillator
WAIT instruction
~HITACHI
Escape
mY, RE~, INT, INT"
each interrupt request of
TIMER TIMER~, SCI
STBY, RES, INT, INT2
STBY="High"
467
HD6305YO,HD63A05YO,HD63B05YO----------------------------------------------
Figure 22
Transitions among Active Mode, Wait Mode,
Stop Mode, Standby Mode and Reset
-BIT MANIPULATION
The HD6305YO MCV can use a single instruction (BSET
or BCLR) to set or clear one bit of the RAM within page 0 or
an I/O port (except the write-only registers such as the data
direction register). Every bit of memory or I/O within page 0
($00"'" $FF) can be tested by the BRSET or BRCLR instruction; depending on the result of the test, the program can
branch to required destinations. Since bits in the RAM on page
0, or I/O can be manipulated, the user may use a bit within the
RAM on page 0 as a flag or handle a single I/O bit as an
independent I/O terminal. Fig. 23 shows an example of bit
manipulation and the validity of test instructions. In the
example, the program is configured assuming that bit 0 of port
A is connected to a zero cross detector circuit and bit 1 of the
same port to the trigger of a triac.
The program shown can activate the triac within a time of
lOlls from zero-crossing through the use of only 7 bytes on
the ROM. The on-chip timer provides a required time of
delay and pulse width mudulation of power is also possible.
SE IF 1.
Figure 23
BRClR 0, PORT A. SELF 1
BSET 1 • PORT A
BClR 1, PORT A
Exa~ple of Bit Manipulation
-ADDRESSING MODES
Ten different addressing modes are available to the
HD6305YO MCV.
elmmediate
See Fig. 24. The immediate addressing mode provides
access to a constant which does not vary during execution of
468
the program.
This access requires an instruction length of 2 bytes. The
effective address (EA) is PC and the operand is fetched from
the byte that follows the operation code.
eDirect
See Fig. 25. In the direct addressing mode, the address of
the operand is contained in the 2nd byte of the instruction.
The user can gain direct access to memory up to the lower
255th address. 192 byte RAM and I/O registers are on page 0
of address space so that the direct addressing mode may be
utilized.
e Extended
See Fig. 26. The extended addressing is used for referenc·
ing to all addresses of memory. The EA is the contents of
the 2 bytes that follow the operation code. An extended
addressing instruction requires a length of 3 bytes.
• Relative
See Fig. 27. The relative addressing mode is used with
branch instructions only. When a branch occurs, the program
counter is loaded with the contents of the byte following the
operation code. EA = (PC) + 2 + ReI., where ReI. indicates a
signed 8·bit data following the operation code. If no branch
occurs, ReI. = O. When a branch occurs, the program jumps
to any. byte in the range + 129 to -127. A branch instruction
requires a length of 2 bytes.
• Indexed (No Offset)
See Fig. 28. The indexed addressing mode allows access
up to the lower 255th address of memory. In this mode, an
instruction requires a length of one byte. The EA is the
contents of the index register.
~HITACHI
~~~~~~~~~~~~~~~~~~~~~~-HD6305Y~HD63A05YO.HD63B05YO
e Indexed (8-bit Offset)
See Fig. 29. The EA is the contents of the byte following the operation code, plus the contents of the index register.
This mode allows access up to the lower 511 th address of
memory. Each instruction when used in the index addressing
mode (8-bit offset) requires a length of 2 bytes.
elndexed (16-bit Offset)
See Fig. 30. The contents of the 2 bytes following the
operation code are added to content of the index register
to compute the value of EA. In this mode, the complete
memory can be accessed. When used in the indexed addressing mode (16-bit offset), an instruction must be 3 bytes long.
e Bit Set/Clear
See Fig. 31. This addressing mode is applied to the BSET
and BCLR instructions that can set or clear any bit on page
O. The lower 3 bits of the operation code specify the bit to
be set or cleared. The byte that follows the operation code
indicates an address within page O.
e Bit Test and Branch
See Fig. 32. This addressing mode is applied to the BRSET
and BRCLR instructions that can test any bit within page 0
and can be branched in the relative addressing mode. The
byte to be tested is addressed depending on the contents of
the byte following the operation code. Individual bits within
the byte to be tested are specified by the lower 3 bits of the
operation code. The 3rd byte represents a relative value which
will be added to the program counter when a branch condition
is established. Each of these instructions should be 3 bytes
long. The value of the test bit is written in the carry bit of the
condition code register.
elmplied
See Fig. 33. This mode involves no EA. All information
needed for execution of an instruction is contained in the
operation code. Direct manipulation on the accumulator
and index register is included in the implied addressing mode.
Other instructions such as SWI and RTI are also used in this
mode. All instructions used in the implied addressing mode
should have a length of one byte.
ili--=~_---ltA
~:J
~
I
Memory
I
I
:
:
PROG LOA #$F8
F8
Index Reg
Stack Point
058Et::~~~f-_----~
05BFIt-""';";;--I
Prog Count
05CO
CC
~
I
•
:
I
Example of Immediate Addressing
Figure 24
Memory
A
CATFCB32004Bt:~c::jr---+----~~-----{~~2~O::J
lndex eg
Stack Point
PROG LOA CAT 0520 t-:~t::::l--~
052E ...
Prog Count
052F
CC
~:
I
I
;
I
:
Figure 25
Example of Direct Addressing
~HITACHI
469
HD6305Y~HD63A05YO,HD63B05YO~~~~~~~~~~~~~~~~~~~~~~
Memory
~
0000
A
:
:
40
Index Reg
PROG LOA CAT g:g!t-~~--L
I
040BI-""';;';;'-_...
Stack Point
tATFCB6406E5~~~::~______________~
Prog Count
040C
CC
Figure 26
Example of Extended Addressing
Memory
A
Index Reg
I
Stack Point
Prog Count
PROG BEQ PROG2 04A7
04C1
rC;,;:C~~_.,
04A8
Figure 27
Example of Relative Addressing
Memory
A
TABLFCC II
00B8t:~4~C~:j~--~~~-------1----------~~~4~C;;~
49
"06
CDA X
o'''§
§. .
B8
Stack Point
Prog Count
05F5
CC
,
Figure 28
470
Example of Indexed (No Offset) Addressing
$
HITACHI
----------------------------------------------HD6305YO,HD63A05YO,HD63B05YO
Me~Ory
:
.
I
lEA
008C
/
Adder
,
I
BF
86
DB
CF
TABL FCB II BF 0089
FCB 1186 008A
FCB 1I0B 008B
FCB IICF 008C
"'-
~
-r---
I
:
:
E6
89
PROG LOA TABl.X 075B
075C
I
A
CF
Index Reg
03
Stack Point
I
I
I
I
Prog Count
0750
CC
§
1
1
I
I
,
Figure 29
Example of Index (S·bit Offset) Addressing
Memory
@.
,
PROG LOA TABl.X ~::~t--:-=---I
0694
:~:
I-----t
g~~~ ..t::~:~:[::~---------.-l
TABL FCB :
: : 0780
1t08
08
FCB IICF 0781 ........;C;,;.F_......
Figure 30
Example of Index (16·bit Offset) Addressing
Memory
PORT B EQU 1 00011-....;B;,;.F_-r"l
A
Index Reg
PROG BCLR 6. PORT B 058F
0590
t=:.2
10t:~~_ _ _.-l
01
I
Stack Point
Prog Count
0591
CC
~
I,
Figure 31
:,
Example of Bit Set/Clear Addressing
$
HITACHI
471
A
PORT C EQU 2.0002 ...-.....;.FO:"---j I L _ _/
Index Reg
I
Stack POInt
PROG BRCLR 2.PORT C.PROG 2 g:~:"'--;~;'~_-I
Prog bount
0594
CC
0576.,.-....:.1:;;,,0_-1
C
Figure 32
,
Example of Bit Test and Branch Addressing
Memory
~
',",0 , . . " . .
~
~
I
I
I
I
I
I
I
•
Figure 33
Example of Implied Addressing
-INSTRUCTION SET
There are 62 basic instructions available to the HD6305YO
MeV. They can be classified into five categories: register/
memory, read/modify/write, branch, bit manipulation, and
control. The details of each instruction are described in
Tables 5 through 11.
• Register/Memory Instructions
Most of these instructions use two operands. One operand
is either an accumulator or index register. The other is derived
from ~emory using one of the addressing modes used on the
HD6305YO MeV. There is no register operand in the unconditional jump instruction (JMP) and the subroutine jump
instruction (JSR). See Table 5.
• Read/Modify/Write Instructions
These instructions read a memory or register, then modify
or test its contents, and write the modified value into the
memory or register. Zero test instruction (TST) does not
write data, and is handled as an exception in the read/modify/
write group. See Table 6.
472
• Branch Instructions
A branch instruction branches from the program sequence
in progress if a particular condition is established. See Table 7.
• Bit Manipulation Instructions
These instructions can be used with any bit located up to
the lower 255th address of memory. Two groups are available;
one for setting or clearing and the other for bit testing and
branching. See Table 8.
• Control Instructions
The control instructions control the operation of the MeV
which is executing a program. See Table 9.
• List of Instructions in Alphabetical Order
Table to lists all the instructions used on the HD6305YO
MeV in the alphabetical order.
• Operation Code Map
Table 11 shows the operation code map for the instructions
used on the Mev.
~HITACHI
~~~~~~~~~~~~~~~~~~~~~~-HD6305YO,HD63A05YO,HD63B05YO
Table 5
Register/Memory Instructions
Addressing Modes
Indexed
Mnemonic
Operations
Immediate
Direct
Extended
OP II
-
OP II
-
OP II
- OP II
-
OP II
-
LOA
A6 2
2 B6 2
3 C6 3
4
F6
1
3 E6 2
4 06 3
5
M~A
Load X from Memory
LOX
AE
2 BE 2
3 CE 3
4
FE
1
3
EE
2
4 DE 3
5
M~X
Store A in Memory
STA
B7
2
J. C7 3
4
F7
1
4
E7
2
4 07 3
5
A~M
Store X in Memory
STX
BF
2
3 CF 3
4
FF
1
4
EF
2
4
OF 3
5
Add Memory to A
ADD
AB 2
2 BB 2
3 CB 3
4
FB
1
3 EB 2
4 DB 3
to A
AOC
A9 2
2 B9 2
3 C9 3
4
F9
1
3 E9
2
Subtract Memory
SUB
AO 2
2 BO 2
3 CO 3
4
FO
1
3 EO 2
2 B2
2
Condition
Code
Booleanl
Arithmetic
Operation
Indexed
Load A from Memory
OP II
-
Indexed
(No Offset) (S-Bit Offset) (16-BitOffsetl
H
I
N
Z
C
f,
1\
f,
a
a
a
a
5
A+M-·A
1\
a
a
a
a
a
1\
X~M
a
a
a
a
4 09 3
5
A+M+C~A
1\
5
A-M-·A
a
a
a
1\
4 DO 3
a
a
a
1\
r
1\
1\
1\
Add Memory and Carry
f
A
Subtract Memory from
A with Borrow
SBC
A2
2
3 C2 3
4
F2
1
3 E2
2
4 02 3
5
A-M-C~A
AND Memory to A
AND
A4 2
2 B4 2
3 C4 3
4
F4
1
3 E4 2
4 04 3
5
A·M~A
OR Memory with A
ORA
AA
2
2 BA 2
3 CA 3
4
FA
1
3 EA 2
4 OA 3
5
A+M~A
a
a
a
EOR
A8 2
2 B8 2
3 C8 3
4
F8
1
3 E8 2
4 08 3
5
A'-!:JM-A
a
a
,A
CMP
AI
2 Bl
3 Cl
3
4
Fl
1
3 El
4 01
3
5
A-M
a
a
r
CPX
A3 2
2 B3 2
3 C3 3
4
F3
1
3 E3 2
4 03 3
5
X-M
a
a
1\
A5
A·M
a
a
a
a
a
a
a
a
2
/
,A
t,
a
a
"
Exclusive OR Memory
with A
a
Arithmetic Compare A
with Memory
2
2
2
Arithmetic Compare X
with Memory
Bit Test Memory with
A (Logical Compare)
BIT
2 85
2
3 C5 3
4
F5
1
3 E5 2
4 05 3
5
Jump Unconditional
JMP
BC
2
2 CC 3
3 FC
1
2 EC
2
3 DC 3
4
Jump to Subroutine
JSR
BO 2
5 CD 3
6 FO
1
5 ED
2
5 DO 3
6
2
a
a
a
1\
a
a
Symbols: Op = Operation
# = Number of bytes
- =Number of cycles
Table 6
Read/ModifylWrite Instructions
Addressing Modes
Operations
I
Indexed
Mnemonic
I
Implied(A)
OP II
-
Direct
Implied(X)
OP II
-
OP II
Indexed
(No Offset) (S-Bit Offset)
-
OP II
Increment
INC
4C
1
2 5C
1
2 3C 2
5 7C
Decrement
DEC
4A
1
2 5A
1
2 3A 2
5 7A 1
1
- OP
II
-
5 6C
2
6
A+l~A
or X+l-X or M+l-M
5 6A 2
6
A-I
or X-l-X or M-l
~A
Clear
CLR
4F
1
2
5F
1
2
3F
2
5
7F
1
5
6F
2
6
OO~A
Complement
COM
43
1
2 53
1
2 33
2
5
73
1
5 63
2
6
A~A
or
or
NEG
40
1
2 50
1
2 30 2
5
70
1
5 60
2
OO~X
X~X
OO-A~A
Negate
(2's Complement)
Condition
Code
Booleanl Arithmetic Operation
or
or
~M
or OO-M
M~M
or
Lb-t I I I I I I IboiJ
ROL
49
1
2 59
1
2 39
2
5
79
1
5 69 2
6
Rotate Right Thru Carry
ROR
46
1
2 56
1
2 36
2
5
76
1
5 66
2
6
Logical Shift Left
LSL
48
1
2 58
1
2 38
2
5
78
1
5 68
2
6
I
N
Z
C
a
a
a
a
a
a
a
a
1\
1\
1\
1\
a
a
a
0
1
a
1\
1\
1
a
1\
1\
1\
a
a
1\
/\
/\
a
a
1\
1\
1\
a
a
1\
1\
1\
a
a
0
1\
1\
OO-X~X
6
Rotate Left Thru Carry
H
OO-M~M
A 01 X or
II
!AHor:M! !bo~
b,
c
D-1 I ~or:xr~ I I 1b,
C
0-1 ! IAH~MI I 1-0
~b,!
bo
0
Logical Shift Right
LSR
44
1
2 54
1
2 34
2
5
74
,
5 64
2
6
Arithmetic Shift Right
ASR
47
1
2 57
1
2 37
2
5 77
1
5 67
2
6
a
a
1\
1\
1\
Arithmetic Shift L.lft
ASL
48
1
2 58
1
2 38
2
5
78
1
5 68
2
6
Equal to LSL
a
a
1\
1\
1\
TST
40
1
2 50 1
2 3D 2
4
70
1
4 60 2
5
A-OO or X-OO or M-OO
a
a
1\
1\
a
110
[(b'
:1 1+~or:MI 1 1-0
bo
C
Test for Negative
or Zero
Symbols: Op· Operation
# • Number of bytes
- • Number of cycles
~HITACHI
473
HD6305YO,HD63A05YO,HD63B05YO---------------------------------------------Table 7 Branch Instructions
Addressing Modes
Operations
Mnemonic
Relative
OP
#
-
Branch Always
BRA
20
2
3
None
Branch Never
BRN
21
2
3
None
Branch IF Higher
BHI
22
2
3
C+Z=O
H
Branch IF lower or Same
BlS
23
2
3
C+Z=1
Branch IF Carry Clear
BCC
24
2
3
C=O
(BHS)
24
2
3
C=O
BCS
25
2
3
C=1
(BlO)
25
2
3
C=1
Branch IF Not Equal
BNE
26
2
3
Z=O
Branch IF Equal
BEQ
27
2
3
Z=1
Branch IF Half Carry Clear
BHCC
28
2
3
H=O
Branch IF Half Carry Set
BHCS
29
2
3
H=1
Branch IF Plus
BPl
2A
2
3
N=O
Branch IF Minus
BMI
2B
2
3
N=1
BMC
2C
2
3
1=0
BMS
20
2
3
1=1
BIL
2E
2
3
INT=O
(Branch IF Higher or Same).
Branch IF Carry Set
(Branch IF
L<~wer)
Condition Code
Branch Test
Branch IF Interrupt Mask
Bit is Set
Branch IF Interrupt Line
is Low
Branch IF Interrupt Line
is High
BIH
2F
2
3
INT=1
Branch to Subroutine
BSR
AD
2
5
--
N
Z
C
• • • •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Branch IF Interrupt Mask
Bit is Clear
I
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• •
• •
• •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Symbols; Op = Operation
# = Number of bytes
- = Number of cycles
Table 8 Bit Manipulation Instructions
Operations
Branch IF Bit n is set
Branch IF Bit n is clear
Set Bit n
Clear Bit n
Addressing Modes
Bit Set Clear
Bit Test and
OP
OP
# BRSET n(n=0···7)
2·n
BRClR n(n=O··· 7)
01+2·n
BSET n(n=0···7)
10+2·n 2 5
BClR n(n=0···7)
11 +2·n 2 5
Mnemonic
Symbols; Op = Operation
# = Number of bytes
- = Number of cycles
474
~HITACHI
Booleanl
Branch Arithmetic
# - Operation
3
3
5
5
-
-
1-Mn
O-Mn
Branch
Test
Mn=1
Mn=O
-
Condition Code
H
I
N
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• •
• •
C
/\
/\
~~~~~~~~~~~~~~~~~~~~~~-HD6305YO.HD63A05YO.HD63B05YO
Table 9
Operations
Mnemonic
Transfer A to X
Transfer X to A
Set Carry Bit
Clear Carry Bit
Set Interrupt Mask Bit
Control Instructions
Addressing Modes
Implied
#
9F
1
1
2
2
SEC
99
1
1
1-+C
ClC
SEI
98
1
1
O-+C
1
1-+1
TAX
TXA
Clear Interrupt Mask Bit
Cli
9B
9A
1
2
2
Software Interrupt
Return from Subroutine
SWI
RTS
83
81
1
1
10
5
Return from Interrupt
RTI
80
1
8
Condition Code
Boolean Operation
-
OP
97
A-+X
X-+A
0-+1
- ---
Reset Stack Pointer
RSP
9C
1
2
$FF-+SP
No-Operation
NOP
OAA
90
1
1
Advance Prog. Cntr. Only
80
8E
8F
1
1
2
4
4
Converts binary add of BCD charCler-s Inlo
BCD format
STOP
WAIT
Decimal Adjust A
Stop
Wait
Symbols; Op = Operation
# = Number of bytes
- = Number of cycles
1
H
I
N
Z
C
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•1
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•1
0
1
•
?
•
•
•
•
•
1\
1\
0
•
•
•
•
?
•
•
•
•
1\*
* Are BCD characters of upper byte 10 or more? (They are not cleared if set in advance'!
Table 10 Instruction Set (in Alphabetical Order)
Addressing Modes
Condition Code
Bit
Mnemonic
Indexed
Indexed
Set!
Test &
(B-Bit)
(16-Bit)
Clear
Branch
X
X
X
/\
X
X
X
X
/\
X
X
X
X
Indexed
Implied
Immediate
Direct
ADC
X
X
X
ADD
X
X
AND
X
X
Extended Relative (No Offset)
ASl
X
X
X
X
ASR
X
X
X
X
BCC
X
....
BClR
X
BCS
X
BEQ
X
BHCC
X
BHCS
X
BHI
X
(BHS)
X
BIH
X
Bil
BIT
X
X
X
X
X
(BlO)
X
BlS
X
BMC
X
BMI
X
BMS
X
BNE
X
BPl
X
BRA
X
Condition Code Symbols;
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
Bit
X
X
H
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
I
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
Z
C
/\
/\
/\
/\
/\
/\
/\
/\
•
/\
/\
/\
1\
1\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
/\
1\
'/\
(to be continued)
C
1\
•?
Carry lBorrow
Test and Set if True, Cleared Otherwise
Not Affected
load CC Register From Stack
~HITACHI
475
HD6305YO,HD63A05YO,HD63B05YO------------------------------------_________
Table 10
Instruction Set (in Alphabetical Order)
Addressing Modes
Condition Code
Bit
Indexed
Mnemonic
Implied
Immediate
Direct
Extended Relative (No Offset)
Indexed
Indexed
Set!
Test &
(S-Bit)
(16-Bit)
Clear
Branch
x
BRN
x
x
BRCLR
BRSET
x
BSET
x
BSR
CLC
CLI
CLR
x
x
x
x
x
CPX
DAA
DEC
x
x
x
x
x
x
x
x
x
EOR
INC
x
x
x
x
x
CMP
COM
x
JMP
JSR
x
x
LOA
LOX
LSL
LSR
NEG
NOP
x
x
x
x
x
ROL
x
ROR
x
RSP
RTI
x
x
RTS
x
SEC
x
SEI
x
STA
x
SUB
TAX
TST
TXA
WAIT
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
476
x
x
x
x
x
x
STX
SWI
x
x
x
x
x
H
I
N
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•0
•
•
•
•
•
•
•1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
?
?
?
•
•
•
•
•
•
•
A
A
•
•0
•
•
II
A
A
/\
A
1
A
II
II
A
A
A
A
1\
•
•
•
• • •
• • •
•
•
A
A
/\
A
/\
II
A
A
II
A
A
0
A
A
A
A
A
• • •
•
A
A
A
II
A
A
A
II
• • • • •
x
SBC
x
x
x
x
x
x
x
x
ORA
STOP
Bit
x
C
A
•
Carry /Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
?
?
• • • • •
• •
• •1 • • 1
A
•
•
•
•
•
•
•
•
•
•
•
•
•
•1
•
•
•
•
A
A
• • •
•
• • •
•
• • •
• • •
•
• • •
• • •
II
A
A
II
A
A
II
A
A
---------------------------------------------·HD6305YO.HD63A05YO.HD63B05YO
Table 11 Operation Code Map
Bit Manipulation
Test &
Set/
Branch
Clear
0
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F
0
1
BRSETO
BRCLRO
BRSET1
BRCLR1
BRSET2
BRCLR2
BRSET3
BRCLR3
BRSET4
BRCLR4
BRSET5
BRCLR5
BRSET6
BRCLR6
BRSET7
BRCLR7
3/5
BSETO
BCLRO
BSET1
BClR1
BSET2
BCLR2
BSET3
BClR3
BSET4
BClR4
BSET5
BClR5
BSET6
BCLR6
BSET7
BCLR7
2/5
(NOTES)
Branch
Rei
2
BRA
BRN
BHI
BlS
BCC
BCS
BNE
BEQ
BHCC
BHCS
BPL
BMI
BMC
BMS
Bil
BIH
2/3
Read/Modify/Write
OIR
3
A
4
Register /Memory
Control
,X1
6
,XO IMP IMP IMM OIR EXT .X2 ,X1 ,XO
7
8
A
B
F
C
0
E
9
RTI"
NEG
SUB
RTS"
CMP
SBC
SWI"
COM
CPX
lSR
AND
BIT
ROR
LOA
ASR
TAX"
STAI+l)
STA
LSl/ASl
CLC
EOR
ROL
SEC
AOC
CLI·
DEC
ORA
ADD
SEI*
INC
RSP"
JMP(-1)
TST(-1) OAA" NOP BSR" JSR(+2) JSR(+ 1) JSRI+2)
TST
STOP" lOX
CLR
WAIT" TXA"
STXI+l)
STX
1/2 1/2 2/6 1/5 1/" 1/1 2/2 2/3 3/4 3/5 2/4 1/3
X
5
-
"-
TSTI-l)
"-
2/5
........
HIGH
0
1
2
3 L
o
4 W
5
6
7
8
9
A
B
C
0
E
F
1. "-" is an undefined operation code.
2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles).
The number of cycles for the mnemonics asterisked (*) is as follows:
RTI
8
TAX
2
RTS
5
RSP
2
SWI
10
TXA
2
DAA
2
BSR
5
STOP
4
ell
2
WAIT
4
SEI
2
3. The parenthesized numbers must be added to the cycle count of the particular instruction.
• Additional Instructions
The following new instructions are used on the HD630SYO:
DAA Converts the contents of the accumulator into BCD
code.
WAIT Causes the MCU to enter the wait mode. For this mode,
see the topic, Wait Mode.
STOP Causes the MCU to enter the stop mode. For this mode,
see the topic, Stop Mode.
·~HITACHI
477
H06305Y1 ,H063A05Y1 ,HD63B05Y1-H06305 Y2, H063A05Y2, HD63B05Y2
CMOS MCU (Microcomputer Unit)
-PREll MINARYThe HD6305YI and the HD6305Y2 are CMOS 8-bit single
chip microcomputers. A CPU, a clock generator, a 256 byte
RAM, I/O terminals, two timers and a serial communication
interface (SCI) are built in both chip of the HD6305Y 1 and
the HD6305Y2. Their memory spaces are expandable to 16k
bytes externally.
The HD6305YI and the HD6305Y2 have the same functions
as the HD630SYO's except for the number of I/O terminals.
The HD6305YI has 7872 byte ROM and its memory space is
expandable to 8k bytes externally. The HD6305Y2 is a microcomputer unit which includes no ROM and its memory space
is expandable to 16k bytes ex tern ally .
- HARDWARE FEATURES
.8·bit based MCU
.7872 bytes of internal ROM (HD6305Y1)
No internal ROM (HD6305Y2)
.256 bytes of RAM
• A total of 31 terminals, including 24 I/O's, 7 inputs
.Two timers
8·bit timer with a 7-bit prescaler (programmable prescaler;
event counter)
15·bit timer (commonly used with the SCI clock divider)
.On-chip serial interface circuit (synchronized with clock)
.Six interrupts (two external, two timer, one serial and one
software)
• Low power dissipation modes
- Wait .... In this mode, the clock oscillator is on and the
CPU halts but the timer/serial/interrupt func·
tion is operatable.
- Stop .... In this mode, the clock stops but the RAM
data, I/O status and registers are held.
- Standby.. I n this mode, the clock stops, the RAM data
is held, and the other internal condition is
reset.
• Minimum instruction cycle time
HD6305Y1/Y2 .. 11ls (f = 1 MHz)
- HD63A05Y1/Y2 .. 0.671ls (f = 1.5 MHz)
- HD63B05Y1/Y2 .. 0.51ls (f =2 MHz)
• Wide operating range
VCC 3 to 6V (f 0.1 to 0.5 MHz)
- HD6305Y1/Y2 .. f =0.1 to 1 MHz (VCC =5V ± 100J»
- HD63A05Y1/Y2 .. f = 0.1 to 1.5 MHz (VCC = 5V ± 100J»
- HD63B05Y1/Y2 .. f 0.1 to 2 MHz (VCC 5V ± 100J»
.System development fully supported by an evaluation kit
=
HD6305Y1P, HD63A05Y1P,
HD63B05Y1P, HD6305Y2P,
HD63A05Y2P, HD63B05Y2P
HD6305Y1F, HD63A05Y1F,
HD63B05Y1 F, HD6305Y2F,
HD63A05Y2F, HD63B05Y2F
(FP·64)
• Index addressing mode useful for table processing
• A variety of conditional branch instructions
• Ten powerful addressing modes
• All addressing modes adaptable to RAM, and I/O instructions
• Three new instructions, STOP, WAIT and DAA, added to the
HD6805 family instruction set
• Instructions that are upward compatible with those of Moto·
rola's MC6805P2 and MC146805G2
=
=
=
-SOFTWARE FEATURES
• Similar to HD6800
• Byte efficient instruction set
• Powerful bit manipulation instructions (Bit Set, Bit Clear, and
Bit Test and Branch usable for 192 byte RAM bits within page
o and all I/O terminals)
• A variety of interrupt operations
478
~HITACHI
HD6305Y1,HD6305Y2
• PIN ARRANGEMENT
HD6305Y1P, HD63A05Y1P, HD63B05Y1P,
HD6305Y2P, HD63A05Y2P, HD63B05Y2P
•
•
vss r--: 0
....J
c:(
~ DATAo
~ .{
~ ~
B3 DATA,
RES
INT
STBY
XTAL
EXTAL
NUM
TIMER
A7
Ae
As
A.
AJ
Az
A,
Ao
B7
Be
B5
B.
B3
Bz
B,
Bo
C7/Tx
C,/Rx
CliCK
C.
C3
Cz
C,
Co
HD6305Y1F, HD63A05Y1F, HD63B05Y1F,
HD6305Y2F, HD63A05Y2F, HD63B05Y2F
cn~
::::> X
Z w
B2 DATAz
cnc:(
>
0
J. ~.;,
~ ~
~
c:(
~
c:(
c:(
~
c:(
~
c:(
0
0
0
0
0
DATAJ
DATA.
DATAs
DATAe
DATA7
DATA6
DATA,
E
E
RtW
ADR13
ADR12
ADR"
ADR,o
ADRa
ADR,
ADR7
ADRe
ADRs
ADR.
ADR3
ADR z
ADR,
AORo
07
O,/i'N'f;
ADR.
ADR,
ADR6
ADRs
ADR4
ADR3
ADR2
ADR.
ADRo
C,/Tx
01
O.
03
Oz
0,
U uu u
VCC
u
c5 0 0 d 0
d
(Top View)
(Top View)
XTAl EXTAl
• BLOCK DIAGRAM
TIMER
CPU
Port A
Control
1/0
Terminals
Condition Code
Register
CC
6
Port B
1/0
Terminals
6
Stack
Pointer
I
L-L-_D,
O./iNT,
0,
0..
OJ
~~
Port 0
Input
Terminals
Sp
Program
Counter
"High" PCH
• No internal ROM in H06305Y2
~HITACHI
DATA,
DATA.
DATA,
DATA.
DATA,
DATA2
DATA,
DATA.
479
HD6305Yl,HD6305Y2------------------------------------------------------• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Supply Voltage
Vee
-0.3-+7.0
V
Input Voltage
Vin
-0.3 - Vee + 0.3
V
Operating Temperature
Topr
0-+70
°c
Storage Temperature
T stg
-55 - +150
°c
[NOTE)
These products heve e protection circuit in their input terminals against high electrostatic voltage or high electric fields. Notwithstanding,
be careful not to apply any voltage higher than the absolute maximum rating to these high input impedance circuits. To assure normal
operation, we recommended Vln, Vout ; Vss ~ (V ln or Vout ) ~ Vee .
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee = ~.OV±10%, Vss = OV, Ta = 0 - +70°C, unless otherwise noted.)
Item
Symbol
Test Condition
Input "High" Voltage
typ
max
Vee+0 .3
Vee- 0 .7
IOL = 1.6mA
-
-
1.0
J,LA
-
-
1.0
J,LA
-
5
10
mA
2
5
mA
2
10
J,LA
2
10
J,LA
-
12
pF
Vee xO . 7
Other Inputs
Input "Low" Voltage
2.0
V 1L
All Inputs
-0.3
Output "High" Voltage All Outputs
V OH
Output "Low" Voltage
All Outputs
VOL
Input Leakage Current
TlMER,INT,
0 1 ' " 0" STBY
Il I Li
Three-state Current
Ao-A"Bo-B"
Co'" C" ADRo '" ADRI3*,
E*, R/W*
2.4
IOH - -200J,LA
Vin
Current Dissipation * *
IITS11
f = 1MHz***
Icc
Stop
Standby
I nput Capacitance
All Terminals
f
Cin
V
Vee+ 0 . 3
Vee+0 .3
0.8
V
-
V
0.55
V
= 0.5 '" V ee-0.5
Operating
Wait
Unit
IOH = -10J,LA
V 1H
EXTAL
min
Vee- 0 .5
-
RES,STBY
= 1MHz, Vin = OV
• Only at standby
•• VIH min = Vec-1.OV. VIL max = O.BV
••• The value at f = xMHz is given by using.
ICC Ct=xMHz) = Icc (f= 1MHz) xx
•
= 0 '" +70°C, unless otherwise noted.)
AC CHARACTERISTICS (Vee = 5.OV±10%, Vss = OV, Ta
Item
Symbol
Test
Condition
HD6305Y1!Y2
typ
max
min
typ
-
10
0.666
20
20
-
-
-
300
-
250
-
-
20
Cycle Time
tcyC
1
Enable Rise Time
tEr
Enable Fall Time
tEf
-
Enable Pulse Width("High" Level)
PWEH
450
Enable Pulse Width("Low" Level)
PW EL
Address Delay Time
tAO
Address Hold Time
tAH
Data. Delay Time
tow
-
Data Hold Time (Write)
tHW
20
Data Set-up Time (Read)
tOSR
80
Data Hold Time (Read)
tHR
0
480
450
Fig. 1
HD63A05Y1/Y2
min
20
~HITACHI
250
-
-
-
20
-
60
-
300
0
HD63B05Y1!Y2
typ
Unit
max
min
10
0.5
-
10
J,Ls
20
-
20
ns
160
-
-
-
20
-
TBD
-
20
-
220
190
-
-
20
220
0
max
20
ns
-
ns
ns
TBD
ns
-
ns
TBD
ns
-
ns
-
ns
ns
-------------------------------------------------------HD6305Yl,HD6305Y2
•
PORT TIMING (Vee
=5.0V±10%, Vss =OV, Ta =0'" +70°C, unless otherwise noted.)
Item
•
Symbol
Port Data Set·up Time
(Port A, B, C, D)
tpDS
Port Data Hold Time
(Port A, B, C, D)
tpDH
Port Data Delay Time
(Port A, B, C)
tpDW
H D6305Y 1/Y2
Test
Condition
H D63B05Y 1/Y2
Unit
typ
max
min
typ
max
min
typ
max
200
-
-
200
-
-
200
-
-
ns
200
-
-
200
-
-
200
-
-
ns
-
-
300
-
-
300
-
-
300
ns
Fig.2
Fig. 3
CONTROL SIGNAL TIMING (Vee:: 5.0V±10%, Vss:: OV, Ta
Item
HD63A05Yl/Y2
min
Symbol
=0'" +70o C,
HD6305Yl/Y2
Test
Condition
unless otherwise noted.)
HD63A05Yl/Y2
HD63B05Yl/Y2
Unit
min
typ
max
min
typ
max
min
typ
max
t'WL
tcyc
+250
-
-
-
-
-
ns
INT; Pulse Width
t'WL2
-
-
-
-
-
ns
5
5
250
-
-
tcyc
+200
tcyC
+200
-
tcyc
+250
tCYc
+200
tcyc
+200
-
-
tCyc
ns
tcyc
+250
ns
-
INT Pulse Width
RES Pulse Width
tRWL
Control Set-up Time
tcs
Timer Pulse Width
tTWL
Fig. 5
Oscillation Start Time (Crystal)
tosc
Fig.5,Fig.20·
Reset Delay Time
tRHL
Fig. 19
80
5
-
-
250
-
-
250
-
-
tcyc
+200
-
-
tcyc
+200
-
-
-
20
-
-
ms
-
80
-
20
80
-
20
-
-
ms
* CL = 22pF ±20%, Rs = 600 max.
•
o
SCI TIMING (Vee = 5.0V±10%, Vss= OV, Ta = 0'" +70 C, unless otherwise noted.)
Item
Symbol
Test
Condition
HD6305Yl/Y2
min
typ
-
Clock Cycle
tScyc
1
Data Output Delay Time
tTxD
-
Data Set-up Time
tSRX
Data Hold'rime
tHRX
Fig.6,
Fig. 7
200
100
max
HD63A05Yl/Y2
min
32768 0.67
max
min
-
21845
0.5
250
-
-
250
-
-
200
-
-
100
-
~HITACHI
H D63B05Y 1/Y2
typ
max
typ
200
100
-
16384
250
Unit
JlS
ns
-
ns
-
ns
481
HD6305Y1,HD6305Y2------------------------------------------------------
14----------- t cYC----------.
E
PWEL
te,
2.4V
Ao--A13
R/W
O.6V
tow
MCU Write
00-07
MCU Read
00-07
Figure 1 Bus Timing
E
2.4V
E
'tv
/
tpow
Port
A,B,C,D
Port
A,B,C
2.4V
O.6V
Data
Valid
Figure 3 Port Data Delay Time (MCU Write)
Figure 2 Port Data Set-up and Hold Times
(MCU Read)
Interrupt
Test
E
Address
Bus
PCoPC7
Data Bus
~~~or ~s~tor
Operand Irrelevant
op
Cod. Data
AddressAddress
\~------------~I
Figure 4 Interrupt Sequence
482
$
HITACHI
First Inst. of
Interrupt Routine
-----------------------------HD6305Y1,HD6305Y2
~. ~~m
E
Vee
_~~
--;:J
tosc----l
r
------~~_+--~-----------------~
Vee- O.5V
t....--tVee-O.5V
~·~
_______
Address
Bus
-~
R/W
__
Data Bus
____
L-_I- - - -
~-JI
1FFF 1FFF 1FFF
1FFE
1FFF New PC
1FFF
'IJ~
------------iI.--~//J/l/11Ih__
:.-1
Figure5 Reset Timing
ts cvc
Clock Output
2.4V
Cs/CK
O.6V
Data Output
C7/TX
tSRX
tHRX - - - - - I
Data Input
2.0V
Cs/RX
O.8V
Figure6 SCI Timing (Internal Clock)
tscyC
2.0V
Clock Input
Cs/CK
O.8V
Data Output
C7/TX
tSRX
Data Input
2.0V
Cs/RX
O.8V
Figure7 SCI Timing(External Clock)
~HITACHI
483
HD6305Y1,HD6305Y2-----------------------------------------------------• Data Bus (DATAo ,.., DATA.,)
This TTL compatible three-state buffer can drive one TTL
load and 90pF.
TTL Load
2.4kQ
(Port)
IOL=1.6mA
Test point
terminal n---~-----<"""'---filII----'
90pF
• Address Bus (ADR o ,.., ADR 13)
Each terminal is TTL compatible and can drive one TTL
load and 90pF.
12kQ
• Input/Output Terminals (Ao ,.., A." So -- B." Co ,.., C.,)
These 24 terminals consist of four/8-bit I/O ports (A, B, C).
Each of them can be used as an input or output terminal on
a bit through program control of the data direction register.
For details, refer to "I/O PORTS."
[NOTES)
1. The load capacitance includes starv capacitance causad
bV the probe. etc.
2. All diodes are 152074
®.
Figure 8 Test Load
• DESCRIPTION OF TERMINAL FUNCTIONS
The input and output signals of the MCU are described
here.
evcc,vss
.
Voltage is applied to the MCU through these two tenrunals.
Vee is S.OV ± 10%, while Vss is grounded.
.INT,INT2
External interrupt request inputs to the MCU. For details,
refer to "INTERRUPT". The INT 2 terminal is also used as
the port 0 6 terminal.
• XTAL, EXTAL
These terminals provide input to the on-chip clock circuit.
A crystal oscillator (AT cut, 2.0 to 8.0 MHz) or ceramic
filter is connected to the terminal. Refer to "INTERNAL
OSCILLATOR" for using these input terminals.
• TIMER
This is an input terminal for event counter. Refer to
"TIMER" for details.
.RES
Used to reset the MCU. Refer to "RESET" for details.
.NUM
This terminal is not for user application. In case of the
HD630SYI, this terminal should be connected to Vee
through 10kn resistance. In case of the HD6305Y2, this
terminal should be connected to Vss.
• Enable (E)
This output terminal supplies E clock. Output is a singlephase, TTL compatible and 1/4 crystal oscillation frequency
or 1/4 external clock frequency. It can drive one TTL load
and a 90pF condenser.
• Input Terminals (01 ,.., 0.,)
These seven input-only terminals are TTL or CMOS compatible. Of the port O's, 06 is also used as INT2. If 06 is
used as a port, the INT2 interrupt mask bit of the miscellaneous register must be set to "1" to preve~1t ari 002 interrupt
from being aCCidentally accepted_
.STBY
This terminal is used to place the MCU into the standby
mode. With STBY at "Low" level, the oscillation stops and
the internal condition is reset. For details, refer to "Standby Mode."
The terminals described in the following are I/O pins for
serial communication interface (SCI). They are also used as
ports Cs , C6 and C., _ For details, refer to "SERIAL COMMUNICATION INTERFACE."
.CK (Cs)
Used to input or output clocks for serial operation .
.Rx (C6)
Used to receive serial data.
.Tx (C.,)
Used to transmit serial data .
-MEMORY MAP
The memory map of the MCU is shown in Fig. 9. $0140$1 FFF of the H0630SY2 are external addresses. However,
care should be taken to assign vector addresses to $1 FF6 $lFFF. Ouring interrupt processing, the contents of the CPU
registers are saved into the stack in the sequence shown in
Fig. 10. This saving begins with the lower byte (PCL) of the
program counter. Then the value of the stack pointer is
decremented and the higher byte (PCH) of the program
counter, index register (X), accumulator (A) and condition
code register (CC) are stacked in that order. In a subroutine
call, only the contents of the program counter (PCH and PeL)
are stacked.
• ReadlWrit. (R/W)
This TTL compatible output signal indicates to peripheral
and memory devices whether MCU is in Read ("High"), or
in Write ("Low"). The normal standby state is Read ("High").
Its output can drive one TTL load and a 90pF condenser.
484
_HITACHI
------------------------------------------------------HD6305Y1,HD6305Y2
o
63
64
255
256
319
320
-REGISTERS
0
1
2
3
4
5
6
1$0000
1,0 Ports
Timer
SCI
r
$003F
RAM
(192Bytes)
Stack
040
A
B
C
0
PORT A DDR
S04'
PORT BOOR
S05'
$06'
PORT C DDR
B
9
10
\
$013F
$0140
Timer Data Reg
Timer CTRL Reg
Mise Reg
ROM·
There are five registers which the programmer can operate.
$00
SOl
S02
S03"
Not Used
$gOFF
$ 100
RAM
(64Bytes)
PORT
PORT
PORT
PORT
$08
$09
$OA
7
0
I. .____A_ _ _~I Accumulator
7
0
X
I
IIndex
L._ _ _ _ _ _ _ _~Reglster
0
13
I
PC
Program
L.._ _ _ _ _ _ _
_ _ _ _ _ _ _..I.Counter
I
6 5
13
0
Not Used
(7.872Bytes)
8182
8191
8192
r---------1'I7!~~~~~t •
16
17
18
$lFF6
$lFFF
$2000
SCI CTRL Reg
$10
SCI STS Reg
SCI Data Reg
$11
~gg~~
$12
Zero
Not Used
31
'-----Negative
'--------Interrupt
Mask
'---------Half
Carry
$lF
$20
j~\ External
Memory Space
External
Memory Space
63
$3F
Figure 11 Programming Model
* Write only regi ster
16383
$3FFF
**
Read only regi ster
• Accumulator (A)
• ROM are a ($0140 - $1 FFF) in the HD6305Y2
is changed into External Memory Space.
This accumulator is an ordinary 8-bit register which holds
operands or the result of arithmetic operation or data processing.
Figure 9 Memory Map of MCU
• Index Register (X)
n-4 1 1
,I
n-3
Accumulator
n+2
n-2
Index Register
n+3
PCW
n+4
76543210
Condition
n+l
Code Register
n-1
n
, I
1
Pull
The index register is an 8-bit register, and is used for index
addressing mode. Each of the addresses contained in the
register consists of 8 bits which, combined with an offset
value, provides an effective address.
In the case of a read/modify/write instruction, the index
register can be used like an accumulator to hold operation
data or the result of operation.
If not used in the index addressing mode, the register can
be used to store data temporarily.
• Program Counter (PC)
PCl'
n+5
Push
• In a subroutine call. only PCl and PCH are stacked.
Figure 10 Sequence of Interrupt Stacking
The program counter is a 14-bit register that contains the
address of the next instruction to be executed.
• Stack Pointer (SP)
The stack pointer is a 14-bit register that indicates the address of the next stacking space. Just after reset, the stack
pointer is set at address SOOFF. It is decremented when data
is pushed, and incremented when pulled. The upper 8 bits
of the stack pointer are fIXed to 00000o 11. During the MCU
being reset or during a reset stack pointer (RSP) instruction,
the pointer is set to address SOOFF. Since a subroutine or
interrupt can use space up to address SOOCI for stacking, the
subroutine can be used up to 31 levels and the interrupt up
to 12 levels.
• Condition Code Register (CC)
The condition code register is a 5-bit register, each bit
indicating the result of the instruction just executed. The
bits can be individually tested by conditional branch instruc-
_HITACHI
485
HD6305Y1,HD6305Y2-----------------------------------------------------tions. The CC bits are as follows:
Half Carry (H): Used to indicate that a carry occurred between bits 3 and 4 during an arithmetic operation (ADD, ADC).
Interrupt (I): Setting this bit causes all interrupts, except
a software interrupt, to be masked. If an
interrupt occurs with the bit I set, it is
latched. It will be processed the instant
the interrupt mask bit is reset. (More specifically, it will enter the interrupt processing
routine after the instruction following the
CLI has been executed.)
Negative (N): Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is negative (bit 7 is logic
Of these six interrupts, the INT2 and TIMER or the SCI
and TIMER2 generate the same vector address, respectively.
When an interrupt occurs, the program in progress stops
and the then CPU status is saved onto the stack. And then,
the interrupt mask bit (I) of the condition code register is
set and the start address of the interrupt processing routine
is obtained from a particular interrupt vector address. Then
the interrupt routine starts from the start address. System
can exit from the interrupt routine by an RTI instruction.
When this instruction is executed, the CPU status before
the interrupt (saved onto the stack) is pulled and the CPU
restarts the sequence with the instruction next to the one at
which the interrupt occurred. Table 1 lists the priority of
interrupts and their vector addresses.
Table 1
"1 ").
Zero (Z):
Used to indicate that the result of the most
recent arithinetic operation, logical operation
or data processing is zero.
Carry/
Represents a carry or borrow that occurred
Borrow (C): in the most recent arithmetic operation. This
bit is also affected by the Bit Test and Branch
instruction and a Rotate instruction.
-INTERRUPT
There~e six different types of interrupt: external interrupts (INT,. IN.T2), internal timer interrupts (TIMER,
TIMER2), senal IOterrupt (SCI) and interrupt by an instruction (SWI).
Interrupt
Priority of Interrupts
Priority
Vector Address
RES
1
$lFFE,
SWI
2
$lFFC,
$lFFD
INT
3
$lFFA,
$lFFB
TIMER/INT2
4
$lFF8,
$lFF9
SCI/TIMER2
5
$lFF6,
$lFF7
.
fliIT
y
1---+1
TIMER
$FF--SP
O--OOR's
CLR INT Logic
SFF---.TDR
y
$7F---+ Timer Prescaler
$50-..TCR
S3F--SSR
$OO--SCR
S7F---MR
Figure 12 Interrupt Flow Chart
$
$lFFF
-
A flowchart of the interrupt sequence is shown in Fig. 12.
A block diagram of the interrupt request source is shown in
Fig. 13.
y
486
--
HITACHI
SCI
-------------------------------------------------------HD6305Y1,HD6305Y2
In the block diagram, both the external interrupts INT and
INT2 are edge trigger inputs. At the falling edge of each input,
an interrupt request is generated and latched. The INT interrupt request is automatically cleared if jumping is made to
the IN'f processing routine. Meanwhile, the INT2 request is
cleared if "0" is written in bit 7 of the miscellaneous register.
For the external interrupts (lNT, INT2), internal timer
interrupts (TIMER, TlMER2) and serial interrupt (SCI), each
interrupt request is held, but not processed, if the I bit of the
condition code register is set. Immediately after the I bit is
cleared, the corresponding interrupt processing starts according to th~ority.
The INT2 interrupt can be masked by setting bit 6 of the
miscellaneous register; the TIMER interrupt by setting bit 6
of the timer control register; the SCI interrupt by setting bit
5 of the serial status register; and the TlMER2 interrupt by
setting bit 4 of the serial status register.
The status of the INT terminal can be tested by a BIL or
BIH instruction. The INT falling edge detector circuit and
its latching circuit are independent of testing by these instructions. This is also true with the status of the INT2 terminal.
• Miscellaneous Register (MR; $OOOA)
The interrupt vector address for the external interrupt
INT2 is the same as that for the TIMER interrupt, as shown
in Table I. For this reason, a special register called the miscellaneous register (MR; $OOOA) is available to control the
INTl interrupts.
Bit 7 of this register is the INT2 interrupt request flag.
When the falling edge is detected at the INT2 terminal, "I"
is set in bit 7. Then the software in the interrupt routine
(vector addresses: $IFF8, $IFF9) checks bit 7 to see if it
is INT2 interrupt. Bit 7 can be reset by software.
Miscellaneous Register (MR;$OOOA)
76543210
IM~R61ZVV1Z1Z1Z1
~
INTi Interrupt Mask
. - - - - - - - - - - INT2 Interrupt Request Flag
Bit 6 is the INT2 interrupt mask bit. If this bit is set to "1",
then the INT2 interrupt is disabled. Both read and write are
possible with bit 7 but "I" cannot be written in this bit by
software. This means that an interrupt request by software
is impossible.
When reset, bit 7 is cleared to "0" and bit 6 is set to "1" .
-TIMER
Figure 14 shows a MCV timer block diagram. The timer
data register is loaded by software and, upon receipt of a
clock input, begins to count down. When the timer data
Vectoring generated
$1 FFA. $1 FFB
BIH/BIL Test
Condition Code Register (CC)
INT Interrupt Latch
INT
Falling Edge Detector
I
~~~~_ _ _
Vectoring generated
$lFFB.$1FF9
TIMER
Serial Status
Register (SSR)
>---.......- - -
Vectoring generated
$1FF6.$1FF7
Figure 13 Interrupt Request Generation Circuitry
~HITACHI
487
HD6305Y1,HD6305Y2------------------------------------------------------register (TDR) becomes "0", the timer interrupt request
bit (bit 7) in the timer control register is set. In response to
the interrupt request, the CPU saves its status into the str.ck
and fetches timer interrupt routine address from addresses
$1 FF8 and $1 FF9 and execute the interrupt routine. The
timer interrupt can be masked by setting the timer interrupt
mask bit (bit 6) in the timer control register. The mask bit
(I) in the condition code register can also mask the timer
interrupt.
The source clock to the timer can be either an external
signal from the timer input termin.al or the internal E signal
(the oscillator clock divided by 4). If the E signal is used as
the source, the clock input can be gated by the input to the
timer input terminal.
Once the timer count has reached "0", it starts counting
down with "$FF". The count can be monitored whenever
desired by reading the timer data register. This permits the
program to know the length of time having passed after the
occurrence of a timer interrupt, without disturbing the contents of the counter.
When the MCU is reset, both the prescaler and counter are
initialized to logic "1". The timer interrupt request bit
(bit 7) then is cleared and the timer interrupt mask bit (bit
6) is set.
To clear the timer interrupt request bit (bit 7), it is necessary to write "0" in that bit.
• Timer Control Register (TCR; $0009)
Selection of a clock source, selection of a prescaler frequency division ratio, and a timer interrupt can be controlled
by the timer control register (TCR; $0009).
For the selection of a clock source, anyone of the four
modes (see Table 2) can be selected by bits 5 and 4 of the
timer control register (TCR).
Timer Control Register (TCR; $0009)
4
' - - - - - - - - - - - - - Timer interrupt mask
- - - - - - - Timer interrupt request
After reset, the TCR is initialized to "E under timer terminal control" (bit 5 = 0, bit 4 = 1). If the timer terminal is
"1", the counter starts counting down with "$FF" immediately after reset.
When "1" is written in bit 3, the prescaler is initialized.
This bit always shows "0" when read.
Table 2
TCR7
Timer interrupt request
o
Absent
TCR
Bit 5
Bit4
Present
TCR6
o
Clock input source
0
0
I nternal clock E
Timer interrupt mask
0
1
E under timer terminal control
Enabled
1
0
No clock input (counting stopped)
Disabled
1
1
Event input from timer terminal
Initialize
(Internal
Clock)
E --+----1
3
Timer Data
Register
L---"'T'"---......,r----..J Timer Interrupt
Write
Read
Figure 14 Timer Block Diagram
488
Clock Source Selection
~HITACHI
-------------------------------------------------------HD6305Yl,HD6305Y2
A prescaler division ratio is selected by the combination of
three bits (bits 0, 1 and 2) of the timer control register (see
Table 3). There are eight different division ratios: +1, +2, +4,
+8, +16, +32, +64 and +128. After reset, the TCR is set to the
+1 mode.
Table 3
-SERIAL COMMUNICATION INTERFACE (SCI)
This interface is used for serial transmission or reception
of 8-bit data. Sixteen transfer rates are available in the range
from I iJS to approx. 32 ms (for oscillation at 4 MHz).
The SCI consists of three registers, one eighth counter and
one prescaler. (See Fig. 15.) SCI communicates with the CPU
via the data bus, and with the outside world through bits 5,
6 and 7 of port C. Described below are the operations of
each register and data transfer.
Prescaler Division Ratio Selection
TCR
Bit 0
Prescaler division ratio
Bit 2
Bit 1
0
0
0
0
1
+2
0
r
0
+4
0
1
1
+8
1
0
0
+16
1
0
1
+32
1
1
0
+64
1
1
1
+128
+1
0
A timer interrupt is enabled when the timer interrupt mask
bit is "0", and disabled when the bit is "I". When a timer
interrupt occurs, "I" is set in the timer interrupt request bit.
This bit can be cleared by writing "0" in that bit.
-SCI Control Register (SCR; $0010)
SCI Control Registers (SCR; $0010)
E
,. __-Di __,
C5(CK)
......-~
'--....-
Transfer
Clock
Generator
:
I
SCI Data Registers
(SOR: $0012)
I
I
I
1.--..,..---'
I
I
Initialize
I
I
C6(Rx)
:
C7(Tx)
:
~
I
I
L
______
~
SCI Status Registers
(SSR :$0011)
Not Used
SCI/TIMER2
Figure 15 SCI Block Diagram
~HITACHI
489
HD6305Y1,HD6305Y2-----------------------------------------------------Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set upon
completion of transmitting or receiving 8-bit data. It is
cleared when reset or data is written to or read from the
SCI data register with the SCRS="I". The bit can also be
cleared by writing "0" in it.
C7 terminal
SCR7
a
Used as I/O terminal (by DDR).
Serial data output (DDR output)
Bit 6 (SSR6)
Bit 6 is the TIMER z interrupt request bit. TIMER z is used
commonly with the serial clock generator, and SSR6 is set
each time the internal transfer clock falls. When reset, the
bit is cleared. It also be cleared by writing "0" in it. (For
details, see TIMER z .)
C6 terminal
SCRS
a
Used as I/O terminal (by DDR).
Serial data input (DDR input)
SCR5 SCR4
Clock source
Cs terminal
-
Bit 5 (SSRS)
Bit 5 is the SCI interrupt mask bit which can be set or
cleared by software. When it is "1", the SCI interrupt (SSR7)
is masked. When reset, it is set to "1".
a
a
a
1
1
0
Internal
Clock output (DDR output)
1
1
External
Clock input (DDR input)
Used as I/O terminal (by
DDR).
Bit 7 (SCR7)
When this bit is set, the DDR corresponding to the C7
becomes "1" and this terminal serves for output of SCI data.
After reset, the bit is cleared to "0".
Bit 6 (SCR6)
When this bit is set, the DDR corresponding to the C6
becomes "0" and this terminal serves for input of SCI data.
After reset, the bit is cleared to "0".
Bit 4 (SSR4)
Bit 4 is the TIMERz interrupt mask bit which can be set
or cleared by software. When the bit is "I", the TIMER z
interrupt (SSR6) is masked. When reset, it is set to "I".
Bit 3 (SSR3)
When "1" is written in this bit, the prescaler of the transfer
clock generator is initialized. When read, the bit always is "0".
Bits 2 - 0
Not used.
Bits 5 and 4 (SCRS, SCR4)
These bits are used to select a clock source. After reset,
the bits are cleared to "0".
SCR1
SCR2
a
a
0
a
a
0
SCRa
SCI interrupt request
o
Absent
Present
Bits 3 - 0 (SCR3 - SCRO)
These bits are used to select a transfer clock rate. After
reset, the bits are cleared to "0".
SCR3
SSR7
SSRS
TIMER z interrupt request
o
Absent
Present
Transfer clock rate
4.aaMHz
4.194 MHz
SSR5
0
1 Ils
O.951lS
a
a
1
21lS
1.911ls
a
1
0
41ls
3.82 1ls
a
a
1
1
81lS
7.S41ls
SSR4
I
1
1
1
1
I
a
1
1
1
1
32768lls
1/32 s
eSCI Data Register (SDR; $0012)
A serial-parallel conversion register that is used for transfer
of data.
eSCI Statui Regilter (SSR; $0011)
76543210
ISSR7ISSR6ISSR5ISSR4ISSR3~
490
SCI interrupt mask
Enabled
Disabled
TIMER z interrupt mask
Enabled
Disabled
• Data Transmission
By writing the desired control bits into the SCI control
registers, a transfer rate and a source of transfer clock are
determined and bits 7 and 5 of port C are set at the serial
data output terminal and the serial clock tenninal, respectively. The transmit data should be stored from the accumulator or index register into the SCI data register. The data
written in the SCI data register is output from the C 7 /Tx
terminal, starting with the LSB, synchronously with the
falling edge of the serial clock. (See Fig. 16.) When 8 bit of
_HITACHI
-------------------------------------------------------HD6305Y',HD6305Y2
data have been transmitted, the interrupt request bit is set in
bit 7 of the SCI status register with the rising edge of the last
serial clock. This request can be masked by setting bit 5 of the
SCI status register. Once the data has been sent, the Bth bit
data (MSB) stays at the C, /Tx terminal. If an external clock
source has been selected, the transfer rate determined by
bits 0 "'" 3 of the SCI control register is ignored, and the Cs /
CK terminal is set as input. If the internal clock has been
selected, the Cs/CK. terminal is set as output and clocks are
output at the transfer rate selected by bits 0"'" 3 of the SCI
control register.
Figure 16 SCI Timing Chart
• Data Reception
By writing the desired control bits into the SCI control
register, a transfer rate and a source of transfer clock are determined and bit 6 and 5 of port C are set at the serial data
input terminal and the serial clock terminal, respectively.
Then dummy-writing or -reading the SCI data register, the
system is ready for receiving data. (This procedure is not
needed after reading subsequent received data. It must be taken
after reset and after not reading subsequent received data.)
The data from the C6 /Rx terminal is input to the SCI
data register synchronously with the rising edge of the
serial clock (see Fig. 16). When B bits of data have been received, the interrupt request bit is set in bit 7 of the SCI
status register. This request can be masked by setting bit 5
of the SCI status register. If an external clock source have been
selected, the transfer rate determined by bits 0 .... 3 of the SCI
control register is ignored and the data is received synchronously with the clock from the C5 /CK terminal. If the internal
clock has been selected, the Cs/CK terminal is set as output
and clocks are output at the transfer rate selected by bits 0 "'"
3 of the SCI control register.
TIMER2 is commonly used with the SCI transfer clock
generator. If wanting to use TIMiRi independently of the
SCI, specify "External" (SCRS = 1, SCR4 = 1) as the SCI
clock source.
If "Internal" is selected as the clock source, reading or
writing the SDR causes the' prescaler of the transfer clock
generator to be initialized.
-I/O PORTS
There are 24 input/output terminals (ports A, B, C). Each
I/O terminal can be selected for either input or output by the
data direction register. More specifically, an I/O port will
be input if "0" is written in the data direction register, and
output if "1" is written in the data direction register. Port A,
B or C reads latched data if it has been programmed as output,
even with the output level being fluctuated by the output
load. (See Fig. 17.)
When reset, the data direction register and data register go
to "0" and all the input/output terminals are used as input .
Bit of data
direction
register
Bit of
output
data
Status of
output
Input to
CPU
1
0
0
0
1
1
0
X
Figure 17
.TIMER2
The SCI transfer clock generator can be m:ed as a timer.
The clock selected by bits 3 "'" 0 of the SCI control register
(4 p.s -- approx. 32 ms (for oscillation at 4 MHz» is input to
bit 6 of" the SCI status register and the TIMER2 interrupt
request bit is set at each falling edge of the clock. Since interrupt requests occur periodically, TIMER2 can be used as a
reload counter or clock.
CD
-----1
.......
__
CD
:Transfer
. -_ _OO;;;.,2@
....
t
@@
L
clock generator is reset and mask bit (bit 4
of SCI stiltus register) is clea red.
00. @ :TlMER2 interrupt request
@. @ : TIMER2 interrupt request bit cleared
1
1
3-state
Pin
Input/Output Port Diagram
Seven input-only terminals are available (port D). Writing
to an input terminal is invalid.
All input/output terminals and input terminals are TTL
compatible and CMOS compatible in respect of both input and
output.
If I/O ports or input ports are not used, they should be
connected to VSS via resistors. With none connected to these
terminals, there is the possibility of power being consumed
despite that they are not used.
-RESET
The MCV can be reset either by external reset input (RES)
or power-on reset. (See Fig. lB.) On power up, the reset
input must be held "Low" for at least tose to assure that the
internal oscillator is stabilized. A sufficient time of delay can
be obtained by connecting a capacitance to the RES input as
shown in Fig. 19.
~HITACHI
491
HD6305Y1,HD6305Y2-----------------------------------------------------requirement for minimum external configurations. It can be
driven by connecting a crystal (AT cut 2.0 - 8.0MHz) or
ceramic oscillator between pins 5 and 6 depending on the reo
quired oscillation frequency stability.
Three different terminal connections are shown in Fig. 20.
Figs. 21 and 22 illustrate the specifications and typical arrangement of the crystal, respectively.
SV
vcc
OV
./~ -/'
VIH RES
RES
Terminal
--------1"'"
-
~:::;al
tRHL
r--AT Cut
Parallel
Resonance
Co=7pF max.
f=2.0-8.0MHz
Rs=600 max.
____________________~
Figure 18
Power On and Reset Timing
Figure 21
100kSl typ
Vee -V'V'V---+':=::--I
RES
*
HD6305Y
MCU
Figure 19
Parameters of Crystal
2
(a)
2.2J.1F
Input Reset Delay Circuit
-INTERNAL OSCILLATOR
The internal oscillator circuit is designed to meet the
[NOTE) Use as short wirings as possible for connection of the crystal
with the EXTAL and XTAL terminals. Do not allow these
wirings to cross others.
6
EXTAL
IH:l-oM-H-zC]
. . . .-s-t XTAL
Figure 22
Typical Crystal Arrangement
HD6305Y
MCU
-LOW POWER DISSIPATION MODE
10-22pF±20%
The HD630SY has three low power dissipation modes:
wait, stop and standby.
Crystal Oscillator
HD6305Y
MCU
External
Ceramic Oscillator
Clock
Input 6 EXTAL
NC S XTAL HD6305Y
MCU
External Clock Drive
Figure 20
492
Internal Oscillator Circuit
• Wait Mode
When WAIr instruction being executed, the MCU enters
into the wait mode. In this mode, the oscillator stays active
but the internal clock stops. The CPU stops but the peripheral
functions - the timer and the serial communication inter·
face - stay active. (NOTE: Once the system has entered the
wait mode, the serial communication interface can no longer
be retriggered.) In the wait mode, the registers, RAM and I/O
terminals hold their condition just before entering into the
wait mode.
The escape from this mode can be done by interrupt (INT,
TIMER/INT2 or SCI/TIMER2), RES or STBY. The RES
resets the MCU and the STBY brings it into the standby
mode. (This will be mentioned later.)
When interrupt is requested to the CPU and accepted, the
wait mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt routine. If the interrupt is
masked by the I bit of the condition code register, after releasing from the wait mode the MCU executes the instruction
next to ~WAIT. If an interrupt other than the INT (Le.,
TIMER/INT2 or SCI/TIMER2) is masked by the timer control
~HITACHI
-------------------------------------------------------HD6305Y1,HD6305Y2
register, miscellaneous register or serial status register, there
is no interrupt request to the CPU, so the wait mode cannot
be released.
Fig. 23 shows a flowchart for the wait function.
• Stop Mode
When STOP instruction being executed, MCU enters into
the stop mode. In this mode, the oscillator stops and the CPU
and peripheral functions become inactive but the RAM,
registers and I/O terminals hold their condition just before
entering into the stop mode.
The escape from this mode can be done by an external
interrupt (INT or (NTl), RES or STBY. The RES resets the
MCU and the STBY brings into the standby mode.
When interrupt is requested to the CPU and accepted,
the stop mode escapes, then the CPU is brought to the operation mode and vectors to the interrupt routine. If the interrupt is masked by the I bit of the condition code register,
after releasing from the stop mode, the MCU executes the
instruction next to the STOP. If the INTl interrupt is masked
by the miscellaneous register, there is no interrupt request to
the MCU, so the stop mode cannot be released.
$
Fig. 24 shows a flowchart for the stop function. Fig. 25
shows a timing chart of return to the operation mode from
the stop mode.
For releasing from the stop mode by an interrupt, oscillation starts upon input of the interrupt and, after the internal
delay time for stabilized oscillation, the CPU becomes active .
For restarting by RES, oscillation starts when the RES goes
"0" and~ CPU restarts when the RES goes "I". The duration of RES="O" must exceed 30 ms to asslIre stabilized oscillation.
• Standby Mode
The MCU enters into the standby mode when the STBY
terminal goes "Low". In this mode. all operations stop and
the internal condition is reset but the contents of the RAM are
hold. The I/O terminals turn to high-impedance state. The
standby mode should escape by bringing sfBv "High". The
CPU must be restarted by reset. The timing of input signals
at the RES and STBY terminals is shown in Fig. 26.
Table 4 lists the status of each parts of the MeU in each
low power dissipation modes. Transitions between each mode
are shown in Fig. 27.
HITACHI
493
HD6305Y1,HD6305Y2------------------------------------------------------
Oscillator Active
Timer and Serial
Clock Active
All Other Clocks
Stop
Initialize
CPU, TIMER, SCI,
1/0 and All
Other Functions
No
No
1=1
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 23 Wait Mode Flow Chart
494
_HITACHI
-------------------------------------------------------HD6305Y1,HD6305Y2
Stop Oscillator
and All Clocks
No
Turn on Oscillator
Wait for Time Delay
to Stabilize
Turn on Oscillator
Wait for Time Delay
to Stabilize
1=0
1=1
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 24 Stop Mode Flow Chart
~HITACHI
495
HD6305Y1,HD6305Y2----------------------------------------------------__
Oscillator
""I"" 111111111111" 111/1
adfTlllllllllllllllllllllllllllllllllllllllllllllllllllll1111
7
II
Time required for oscillation to become
Interrupt
STOP instruction
executed
stabilized (built-in delay time)
~tions
restart
(a) Restart by Interrupt
Oscillator
E
11111111111111111111111111111
II
41111111111111111111111111111/1111/111/111111111111/1111//
/
~I~----'
~
I
Time required for oscillation to become
STOP instruction
executed
stabilized (tos c )
'~
I start
(b) Restart by Reset
Figure 25
Timing Chart of Releasing from Stop Mode
\'--------;Hr-_----'I
,
I
I
I
I
I __I __ I
~_~
~
~~
______
~~
________
~
_ _ _ _ _ _- - J
tosc
Figure 26
Table 4
Restart
Timing Chart of Releasing from Standby Mode
Status of Each Part of MCU in Low Power Dissipation Modes
Condition
Start
Mode
WAIT
-
Software
STOP
Standby
498
HardWlte
Escape
1/0
Oscillator
CPU
Timer,
Serial
Register
RAM
WAIT instruction
Active
Stop
Active
Keep
Keep
Keep
STBY, RES, INT, INI2,
each interrupt request of
TIMER, TIMER~, SCI
STOP InstrIJction
Stop
Stop
Stop
Keep
Keep
Keep
STBY,
S'fIV=" Low"
Stop
StOP
Stop
Reset
Ke&p
_HITACHI
terminal
High im-
pedante
AU, INT, INT2
STIY","High"
-----------------------------------------------------HD6305Y1,HD6305Y2
Figure 27
Transitions among Active Mode, Wait Mode,
Stop Mode, Standby Mode and Reset
-BIT MANIPULATION
The MCV can use a single instruction (BSET or BCLR) to
set or clear one bit of the RAM within page 0 or an I/O port
(except the write-only registers such as the data direction
register). Every bit of memory or I/O within page 0 ($00 '"
$FF) can be tested by the BRSET or BRCLR instruction;
depending on the result of the test, the program can branch to
required destinations. Since bits in the RAM on page 0, or I/O
can be manipulated, the user may use a bit within the RAM on
page 0 as a flag or handle a single I/O bit as an independent
I/O terminal. Fig. 28 shows an example of bit manipulation
and the validity of test instructions. In the example, the program is configured assuming that bit 0 of port A is connected
to a zero cross detector circuit and bit I of the same port to
the trigger of a triac.
The program shown can activate the triac within a time of
10/-ts from zero-crossing through the use of only 7 bytes on
the ROM. The on-chip timer provides a required time of
delay and pulse width modulation of power is also possible.
SE IF 1.
Figure 28
BRClR 0, PORT A, SELF 1
BSET 1 , PORT A
BClR 1, PORT A
Example of Bit Manipulation
-ADDRESSING MODES
Ten different addressing modes are available to the MCU.
elmmediate
See Fig. 29. The immediate addressing mode provides
access to a constant which does not vary during execution of
the program.
This access requires an instruction length of 2 bytes. The
$
effective address (EA) is PC and the operand is fetched from
the byte that follows the operation code.
eDirect
See Fig. 30. In the direct addressing mode, the address of
the operand is contained in the 2nd byte of the instruction.
The user can gain direct access to memory up to the lower
255th address. 192 byte RAM and I/O registers are on page 0
of address space so that the direct addressing mode may be
utilized.
e Extended
See Fig. 31. The extended addressing is used for referencing to all addresses of memory. The EA is the contents of
the 2 bytes that follow the operation code. An extended
addressing instruction requires a length of 3 bytes.
eRelative
See Fig. 32. The relative addressing mode is used with
branch instructions only. When a branch occurs, the program
counter is loaded with the contents of the byte following the
operation code. EA = (PC) + 2 + Rei., where ReI. indicates a
signed 8-bit data following the operation code. If no branch
occurs, ReI. = O. When a branch occurs, the program jumps
to any byte in the range + 129 to -127. A branch instruction
rt:quires a length of 2 bytes.
elndexed (No Offset)
See Fig. 33. The indexed addressing mode allows access
up to the lower 255 th address of memory. In this mode, an
instruction requires a length of one byte. The EA is the
contents of the index register.
HITACHI
497
HD6305Y1,HD6305Y2------------------------------------------------------elndexed (S·bit Offset)
See Fig. 34. The EA is the contents of the byte follow·
ing the operation code, plus the contents of the index register.
This mode allows access up to the lower 511 th address of
memory. Each instruction when used in the index addressing
mode (8·bit offset) requires a length of 2 bytes.
elndexed (16-bit Offset)
See Fig. 35. The contents of the 2 bytes following the
operation code are added to content of the index register
to compute the value of EA. In this mode, the complete
memory can be accessed. When used in the indexed address·
ing mode (16-bit offset), an instruction must be 3 bytes long.
e Bit Set/Clear
See Fig. 36. This addressing mode is applied to the BSET
and BCLR instructions that can set or clear any bit on page
O. The lower 3 bits of the operation code specify the bit to
be set or cleared. The byte' that follows the operation code
indicates an address within page O.
e Bit Test and Branch
See Fig. 37. This addressing mode is applied to the BRSET
and BRCLR instructions that can test any bit within page 0
and can be branched in the relative addressing mode. The
byte to be tested is addressed depending on the contents of
the byte following the operation code. Individual bits within
the byte to be tested are specified by the lower 3 bits of the
operation code. The 3rd byte represents a relative value which
will be added to the program counter when a branch condition
is established. Each of these instructions should be 3 bytes
long. The value of the test bit is written in the carry bit of the
condition code register.
elmplied
See Fig. 38. This mode involves no EA. All information
needed for execution of an instruction is contained in the
operation code. Direct manipulation on the accumulator
and index register is included in the implied addressing mode.
Other instructions such as SWI and RTI are also used in this
mode. All instructions used in the implied addressing mode
should have a length of one byte.
Memory
mOGC . . . .
,,~:F~:
~ I ~I
A
I
Fa
Index Reg
I
Stack Point
Prog Count
05CO
cc
··~.
,
Figure 29
Example of Immediate Addressing
Memory
A
CATFCB32004Bt:~c::j------+_------~~---------{~~2~0::J
Index eg
Stack Point
PROG LOA CAT 0520 t-::~t:::::t------.J
052E I-
Prog !ount
052F
CC
~
I•
I
II
I
I
•
I
I
Figure 30
498
Example of Direct Addressing
$
HITACHI
--------------------------------------------------------HD6305Y1,HD6305Y2
Memory
0000
A
40
Index Reg
I
Stack Point
CATFCB6406E5~::4~0L:~~--------------~
Prog Count
040C
CC
Figure 31
Example of Extended Addressing
PROG BEQ PROG2 g:~~ I--':;';"'-oof
Figure 32
Example of Relative Addressing
Memory
A
TABlFCC 1I
OOBBt:::~:::t----~~~------1_-----------[~~;:~
,"OG CDX X 0'"
§
Stack Pomt
Prog Count
05F5
CC
§
.
Figure 33
.
Example of Indexed (No Offset) Addressing
~HITACHI
499
HD6305Y1,HD6305Y2:------------------------------------------------------
r--
Memory
"" m~~ ~l:t::
rCB
CF OOBC:
A
1
CF
-----e:IndexcrReg
: ,_
,____ -1
03
Stack Pomt
OlOCE:3-'
P2 signal. When <1>2 is used as the source, it can be gated by an
input applied to the TIMER input pin allowing the user to
easily perform pulse-width measurements. The timer 1 continues to count past zero, faIling through to $FF from zero and
then continuing the count. Thus, the counter (TDRI) can be
read at any time by reading the TDRI. This allows a program
to determine the length of time since a timer interrupt has
occurred and not disturb the counting process.
At power-up or reset, the prescaler and counter are initialized
with all logical ones; the timer 1 interrupt request bit (bit 7) is
cleared and the timer 1 interrupt mask bit (bit 6) is set. In
order to release the timer 1 interrupt, bit 7 of the TCR I must
be cleared by software.
• Condition Code Register (CC)
The condition code register is a 5-bit register in which each
bit is used to indicate or flag the results of the instruction just
606
eHITACHI
-------------------------------------------------------------HD68P05WO
3
Write
Read
Figure 4 Timer Clock
• Timer Control Register 1 (TCR1: $0009)
The Timer Control Register 1 (TCRl: $0009) can control
selection of clock input source and prescaler dividing ratio and
timer interrupt.
Table 1 Selection of Clock Input Source
TCRl
Bit 5
Bit 4
0
0
0
1
1
1
Timer Control Register 1 (TCR1: $0009)
76543210
I TIF ITIMIIS1 I ISO l/1MS21 MS11 Mso
~
:
i
Clock Input Source
Internal Clock 1/>2 *
------- --
1/>2 Controlled by TIMER Input
0
1
Event Input From TIMER
* The TIMER input pin must be tied to Vee. for uncontrolled
~
clock input.
Table 2 Selection of Prescaler Dividing Ratio
L".. O",d',. "",.
ml"
Clock Input Source
Bit 2
0
0
Timer Interrupt Mask
' - - - - - - - - - - - T i m e r Interrupt Request Flag
0
As shown in Table 1, the selection of the clock input source
is ISO and IS 1 in the TCRI (bit 4 and bit 5) and 3 kinds of
input are selectable. At reset, internal clock 1/>2 controlled by
the TIMER input (bit 4 = 1, bit 5 =0) is selected.
The prescaler dividing ratio is selected by MSO, MSl, and
MS2 in the TCRI (bit 0, bit 1, bit 2) as shown in Table 2. The
dividing ratio is selectable from eight ways (+1, +2, +4, +8, +16,
+32, +64, +128). At reset, +1 mode is selected. The prescaler
is initialized by writing in the TDRI.
Timer 1 interrupt mask bit (TIM) allows the Timer 1 into
interrupt at "0" and masks at "1". Timer 1 interrupt causes
Timer· 1 interrupt request bit (TIF) to be set. TIF must be
cleared by software.
(NOTE) If the MCU Timerl and Timer2 are not used, the
TIMER input pin must be grounded.
$
0
1
1
1
1
HITACHI
TCRl
Bit 1
0
0
1
1
0
0
1
1
BitO
0
1
0
1
0
1
0
1
Prescaler Dividing Ratio
+1
+2
+4
+8
+16
+32
+64
+ 128
607
HD68P05WOI----------------------------------------------------------• TIMER 2
The HD68POSWO includes an 8-bit programmable. timer
(Timer 2) which can not only measure the input waveform
but also generate the output waveform. The pulse width for
both input and output waveform can be varied from several
microseconds to several seconds.
(NOTE) If the MCU Timer! and Timer2 are not used, the
TIMER input pin must be grounded.
Timer 2 hardware consists of the followings.
• 8-bit Control Register 2
• 8-bit Status Register 2
• 8-bit Timer Data Register 2
• 8-bit Output Compare Register
• 8-bit Input Capture Register
• S-bit Prescaler Control Register
• 7-bit Prescaler 2
Block Diagram of Timer 2 is shown in Fig. S.
Output Compare Register
(OCR: $0010)
8
8 bit Register
L-_ _ _ _ _...I Read/Write
Input Capture Register IICR: $001 E)
8 bit Register
8
Read
Timer Control Register 2
(TCR2: $001 B)
ICI
OCI TOI
Internal Interrupts Request Signal
Figure 5 Block Diagram of Timer 2
• Timer Data Register 2 (TOR2; $001C)
The main part of the Timer 2 is the 8-bit Timer Data Register
2 (TDR2) as free-running counter, which is driven by internal
clock tP2 or the TIMER input and increments the value. The
values in the counter is always readable by software.
The Timer Data Register 2 is Read/Write register and is
cleared at reset.
• Output Compare Register (OCR; $0010)
The Output Compare Register (OCR) is an 8-bit read/write
register used to control an output waveform. The contents of
this register are always compared with those of the TDR2.
When these two contents conform to each other, the flag (OCF)
in the Timer Status Register 2 (TSR2) is set and the value of the
608
output level bit (OLVL) in the TCR2 is transferred to Port C6
(OC).
If Port C6 's Data Direction Register (DDR) is "I" (output),
this value will appear at Port C6 (OC). Then the values of OCF
and OLVL can be changed for the next compare. The OCR is
set to $FF at reset.
• Input Capture Register nCR; $001 E)
The Input Capture Register (ICR) is an 8-bit read-only
register used to store the value of the TDR2 when Port Cs
(IC) input transition occurs as defined by the input edge bit
(IEDG) of the TCR2.
In order to apply Port Cs (IC) input to the edge detect
circuit, the DDR of Port Cs should be cleared ("0").·
~HITACHI
-------------------------------------------------------------HD68P05WO
To ensure an input capture under all condition, Port C 5
(IC) input pulse width should be 2 Enable-cycles at least.
*The edge detect circuit always senses Port Cs (lC) even if the DDR
is set with Port Cs output.
Bit 5 TOF Timer Overflow Flag
This read-only bit is set when the TDR2 contains $00. It
is cleared by reading the TSR2 followed by reading of the
TDR2 .
• Timer Control Register 2 (TCR2; $001B)
The Timer Control Register 2 (TCR2) consists of an 5-bit
register of which all bits can be read and written.
Bit 6 OCF Output Compare Flag
This read-only bit is set when a match is found between the
OCR and the TDR2. It is cleared by reading the TSR2 and then
writing to the OCR.
Timer Control Register 2 (TCR2: $001 B)
Bit 7 ICF Input Capture Flag
. This read-only bit is set to indicate a proper level transition
and cleared by reading the TSR2 and then reading the TCR2.
654321
I Z V I / 1 I C I M I OCIM I TOIM IIEDG
0
I I
OLVL
Bit 0 OLVL Output Level
This bit will appear at Port C6 when the value in the TDR2
equals the value in the OCR, if the DDR of Port C 6 is set. It
is cleared by reset.
Bit 1 I EDG Input Edge
This bit determines which level transition of Port Cs (Ie)
input will trigger a data store to ICR from the TDR2. When
this function is used, it is necessary to clear DDR of Port Cs .
When IEDG = 0, the negative edge triggers ("High" to "Low"
transition). When IEDG = 1, the positive edge triggers ("Low"
to "High" transition). It is cleared by reset.
User can write into port C6 by software.
Accordingly, after port C 6 has output -by hardware and is
immediately write into by software, simultaneous cyclic pulse
control with a short width is easy.
• Prescaler Control Register 2 (PCR2: $0019)
The selections of clock input source and prescaler dividing
ratio are performed by the Prescaler Control Register 2 (PCR2:
$0019).
Prescaler Control Register 2 (PCR2: $0019)
7
6
5
1//lZIIS1
4
ISO
3
IZI
o
2
MS1
MS2
MSO
'----v--------Bit 2 TOIM Timer Overflow Interrupt Mask
When this bit is cleared, internal interrupt (TOI) is enabled
by TOF interrupt but when set, interrupt is inhibited.
t
Prescaler Dividing Ratio
' - - - - - - - - - Clock Input Source
Bit 3 OCIM Output Compare Interrupt Mask
When this bit is cleared, internal interrupt (OCI) by OCF
interrupt occurs. When set, interrupt is inhibited.
Bit 41CIM Input Capture Interrupt Mask
When this bit is cleared, internal interrupt (lCI) by ICF
interrupt occurs. When set, interrupt is inhibited.
• Timer Status Register 2 (TSR2: $001 A)
The Timer Status Register 2 (TSR2) is an 8-bit read-only
register which indicates that:
(1) A proper leveltransition has been detected on the input
pin with a subsequent transfer of the TDR2 value to the
ICR (ICF).
(2) A match has been found between the TDR2 and the OCR
(OCF).
(3) The TDR2 is zero (TO F).
Each of the event can generate 3 kinds of internal interrupt
request and is controlled by an individual inhibit bits in the
TCR2. If the I bit in the Condition Code Register is cleared,
priority vectors are generated in response to clearing each
interrupt mask bit. Each bit is described below.
Timer Status Register 2 (TSR2: $001A)
7
6
5
ICF
OCF
TOF
4
3
2
0
The selection of clock input source is performed in three
different ways by bit 4 and bit 5 of the PCR2, as shown in
Table 3. At reset, internal clock ~2 controlled by the TIMER
input (bit 4 = I, bit 5 =0) is selected.
The prescaler dividing ratio is selected by three bits in the
PCR2 (bits 0, 1, 2), as shown in Table 4. The dividing ratio
can be selected in 8 ways (+1, +2, +4, +8, +16, +32, +64,
+ 128). At reset, + 1 (bit 0 =bit I =bit 2 =0) is selected.
When writing into the PCR2, or when writing into the TDR2,
prescaler is initialized to $FF.
Table 3 Selection of Clock Input Source
PCR2
Bit 5
Bit4
0
0
0
1
1
0
1
1
Clock Input Source
q,2
Internal Clock q,2 *
Controlled by TIMER Input
Event Input from TIMER
* The TIMER input pin must be tied to Vee. for uncontrolled t/>2
clock.
L212JZI2JZ1
~HITACHI
609
HD68P05WQ-------------------------------------------------------------(4) Branch Instruction
Table 4 Selection of Prescaler Dividing Ratio
PCR2
Bit 2
Bit 1
0
0
0
0
1
0
0
1
1
1
1
Prescaler Dividing Ratio
BitO
0
1
1
0
1
+1
+2
+4
+8
0
0
1
1
0
1
0
1
+16
+32
+64
+ 128
Cause:
20
2
4
BRN
BHI
BLS
BNE
BEQ
21
22
23
24
24
25
25
26
27
BHCC
BHCS
BPL
BMI
BMC
BMS
BIL
28
29
2A
2B
2C
20
2E
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
BIH
BSR
2F
AD
2
2
BCS
(BLO)
These instructions have some dummy read cycles so
the TSR2 be read when executing the instructions.
# Cycles
Op Code
BCC
(BHS)
CAUTION
(1) Don't program branch instructions shown in Table 5-(1),
(4) at address $117 to $IIC.
(2) Don't use the instructions shown in Table 5-(1), (2), (3)
for read/write/test operation of the TSR2 flags.
When these instructions are executing the TSR2, two flags
(TOF and rCF) of the TSR2 will sometimes cleared.
# Bytes
Mnemonic
BRA
4
4
4
4
8
Table 5 Instruction Inhibited to Operate the TSR2
(1 ) Bit Test and Branch Instruction
Mnemonic
BRSET n (n=0-7)
BRCLRn (n=0-7)
Op Code
# Bytes
# Cycles
2·n
01+2· n
3
3
10
10
# Bytes
# Cycles
2
2
7
7
(2) Bit Set/Clear Instruction
Mnemonic
BSET n (n=0-7)
BCLR n (n=0-7)
Op Code
10+2· n
11+2· n
• RESETS
The MCV can be reset two ways; by initial power-up and by
the external reset input (RES), see Figure 6. All the I/O ports
are initialized to input mode (DDRs are cleared) during reset.
During power-up, a minimum 100 milliseconds is needed
before allowing the RES" input to go "High". This time allows
the internal crystal oscillator to stabilize. Connecting a capacitor to the ~ input, as shown in Figure 7, typically provides
sufficient delay.
(3) Read/Modify/Write Instruction
Mnemonic
INC
DEC
CLR
Op Code
3C
3A
3F
COM
NEG
ROL
ROR
LSL
# Bytes
# Cycles
2
2
2
6
6
6
2
2
2
2
2
LSR
ASR
33
30
39
36
38
34
37
6
6
6
6
6
6
ASL
TST
38
3D
2
2
2
2
R'ES/RAME Pin
Internal
Reset
-------'i'
---------------~
Figure 6 Power Up and Reset Timing
2
6
6
6
Part of
HD68P05WO
MCU
Figure 7 Power Up Reset Delay Circuit
610
~HITACHI
-------------------------------------------------------------HD68P05WO
•
INTERNAL OSCILLATOR
The internal oscillator circuit is designed to interface with a
crystal (AT cut, 4 MHz max.) which is sufficient to drive it
with various stability. As shown in Figure 8, a 22 pF capacitor
6
4 MHz CJ
max
is required from EXT AL to ground. Crystal specifications are
given in Figure 9. Alternatively, EXTAL may be driven with
a duty cycle of 50% with XTAL connected to ground.
XTAl
5 EXTAl
6 XTAl
HD68P05WO
MCU
External
Clock
Input
22PF±20%=ifr-
5 EXTAl
HD68P05WO
MCU
External Clock
Figure 8
Internal Oscillator Options
Table 6 Interrupt Priorities
Interrupt
RES"
SWI
INT,
Timer/IN' 2
ICI
OCI
OFI
4k bytes
type
AT - Cut Parallel Resonance Crystal
Co = 7 pF max.
f = 4 MHz IC, =22pF±20%)
Interrupt
Rs= 60n max,
RES
Figure 9 Crystal parameters
SWI
INT,
Timer/mi 2
ICI
OCI
OFI
8k bytes
type
• INTERRUPTS
The MCU can be interrupted in seven different ways: through
external· interrupt input pin ~ and INT 2)' internal timer
interrupt request (Timer I, ICI, OCI and OFI) and a software
interrupt instruction (SWI). 1N'r2 and Timer I are generated
by the same vector address. When interrupt occurs, processing
of the program is suspended, the present CPU state is pushed
onto the stack. Figure 10 shows interrupt stacking order.
Moreover, the interrupt mask bit (I) of the Condition Code
Register is set and the external routine priority address is
achieved from the special external vector address. After that,
the external interrupt routine is executed. The interrupt
service routines normally end with a return from interrupt
(RTI) instruction which allows the CPU to resume processing
of the program prior to the interrupt. The priority interrupts
are shown in Table 6 with the vector address that contains
the starting address of the appropriate interrupt routine. The
interrupt sequence is shown as a flowchart in Figure 11.
Note that the Vector Address when using the 8k byte type
EPROM is'different from the 4k byte type EPROM.
6
n-4
1
5
1
4
11
Priority
1
2
3
4
5
6
7
Vector Address
$OFFE, $OFFF
$OFFC, $OFFD
$OFFA, $OFFB
$OFF8,$OFF9
$OFF6, $OFF7
$OFF4, $OFF5
$OFF2,$OFF3
Priority
1
2
3
4
5
6
7
Vector Address
$1FFE,$1FFF
$1FFC,$1FFD
$1FFA,$1FFB
$1FF8,$1FF9
$1FF6,$1FF7
$1FF4,$1FF5
$1FF2,$1FF3
3
2
Condition
Code Register
0
Pull
n+1
n-3
Accumulator
n+2
n-2
Index Register
n+3
n-1
1
1
~
PCH*
PCl*
n+4
n+5
Push
* For subroutine calls, only PCH and PCl are stacked.
Figure 10 Interrupt Stacking Order
eHITACHI
611
HD68P05WO'-----------------------------------------------------------
y
INT.
y
INT,
Clear
y TIMER 1
1-+-1
7F -+-SP
-+-DDR's
CLR INT Logic
7F-+-MR
FF-+-TDR1
00-+-TDR2
7F -+- Prescaler 1
7 F -+- Prescaler 2
50-+-TCR1
1C-+-TCR2
00-+-TSR2
10 -+-PCR2
o
y
ICI
Y
OCI
Fetch Instruction
y
Stack PC, X, CC, A
Execute Instruction
Load PC From
Type
SWI
INf";""
TIMER
INT,
ICI
OCI
OFI
4k bytes
8k bytes
$OFFC, $OFFD
$OFFA, $OFFB
$OFF8,$OFF9
$OFFS,$OFF9
$OFF6,$OFF7
$OFF4,$OFF5
$OFF2,$OFF3
I
I
I
I
I
I
I
$1 FFC, $1 FFD
$1 FFA, $1 FFB
$1FFS,$1FF9
$1FF8,$1FF9
$1FF6,$1FF7
$1FF4,$1FF5
$1FF2,$1FF3
Figure 11 Interrupt Flowchart
• Miscellaneous Register (MR: $OOOA)
The vector address generated by the external interrupt
(1NT2 ) is the same as that of TIMERI as shown in Table 6.
The miscellaneous register (MR) controls the 1NT2 interrupt.
Miscellaneous Register (MR: $OOOA)
7
IRF
6
1M
5
4
3
2
[21ZVV121ZI
L - - - - - - - I N T 2 Interrupt Mask
L - - - - - - - - - - I N T 2 Interrupt Request Flag
612
$
HITACHI
0
------~-------------------------------------------------------HD68P05WO
Bit 7 (IRF) of the MR is used as an 1NT2 interrupt request
flag. 1NT"2 interrupt occurs at the lliff2 negative edge, and
IRF is set. lNT"2 interrupt or not can be proved by checking
IRF by software in the interrupt routine of the vector address
($FF8, $FF9). IRF should be reset by software (BCLR instruction).
Bit 6 (1M) of the MR is an 1NT2 interrupt mask bit. When
1M is set, IN'f; interrupt is disabled. 1NT2 interrupt is also
disabled by bit (I) of the Condition Code Register (CC) like
other interrupts.
IRF is available for both read and write. However, IRF is
not writable by software. Therefore, 1N'F2 interrupt cannot
be requested by software. At reset, IRF is cleared and 1M is
set.
• INPUT/OUTPUT
There are 23 input/output pins. All pins are controlled by
the Data Direction Register and both input and output are
programmable. When programmed as output, the latched
output data is readable as input data, regardless of the logic
levels at the output pin due to output loading (See Figure 12.)
When Port B is programmed for output, it is capable of sinking
10 rnA on each pin (VOL max. = IV). Furthermore, Port A is
CMOS compatible as output. Ports Band C are CMOS compatible as inputs. Some examples of the Port connections are
shown in Figure 13.
Port Cs and C6 are also used for Timer 2.
When Port Cs is used as Timer 2 Input Capture (I C) , Port
Cs's DDR should be cleared (Port Cs as input) and bit 4 (ICIM)
in the Timer Control Register 2 (TCR2) should be cleared too.
The Input Capture Register (lCR) stores the TDR2 when a
Port Cs input transition occures as defined by bit 1 (IDEG) of
the TCR2.
When Port C6 is used as Timer 2 Output Compare (OC), Port
C6 's DDR should be set (port C6 as output). When the Output
Compare Register (OCR) matches the TDR2, bit 0 (OLVL) in
the TCR2 is set and OLVL will appear at Port C6 . Port C6 is
writable by software. But the writing by software is unavailable
when a match between the TDR2 and the OCR is found at the
same time.
Data
Direction
Register
Bit
1
1
0
Output
Data Bit
Output
State
Input to
0
0
0
1
x
1
1
3-State
Pin
MCU
Figure 12 Typical Port I/O Circuitry
$
HITACHI
613
HD68P05WO----------------------------------------------------------Ao
··•
··
Port A
Port B
A,
Port B Programmed as output(s), driving Darlington base directly.
Port A Programmed as output(s), driving CMOS and TTL Load directly.
(a)
(b)
+v
+v
R
R
Bo
Port B
··•
··
-
Port C
10mA max
·
·····
I - - - -.....---;~ CMOS Inverter
C.
B,
Port C Programmed as output(s), driving CMOS load(s), using external
pull-up resistors.
(d)
Port B Programmed as output(s), driving LED(s) directly.
(el
Figure 13 Typical Port Connections
• INPUT
Port D is usable as either TTL compatible inputs or a 4channel input for an AID converter. Fig. 14 shows port D logic
configuration.
The Port D register at location $003 stores TTL compatible
inputs. When using as analog inputs for an AID converter,
refer to "AID CONVERTER"
(ANo to AN3), the Result Register (ADRR) and the Control
Status Register (ADCSR).
CAUTION
The MCU has circuitry to protect the inputs against damage
due to high static voltages or electric field; however, the design
of the input circuitry for the AID converter, ANo -- AN3, VRH
and AVcc, does not offer the same level of protection. Precautions should be taken to avoid applications of any voltage
higher than maximum-rated voltage or handled in any environment producing high-static voltages.
• AID CONVERTER
The HD68P05WO has an internal 8 bit AID converter. '{he
AID converter, shown in Figure 15, includes 4 analog inputs
$0003 Read
Internal Bus
1-......_ _ _ _ Port 0
O/A
(D. to Os)
4
AVss--------l
Analog Input
ANo
AN,
AN,
Select MUX
AN3
Figure 14 Port D
AVec 0 - 0 - - - _
SV
8 Bit Register (AORR: $OOOF)
AID Control Status Register
(AOCSR, $CODE)
AID Result Register (AORR: SOOOF)
Figure 15 AID Converter Block Diagram
614
eHITACHI
-----------------------------------------------------------HD68P05WO
•
•
Analog Input (AN o to AN3 )
RAM Control Register (RCR: $001 F)
Analog inputs ANo to AN3 accept analog voltages of OV
to 5V. The resolution is 8 bits (256 divisions) with a conversion
time of 76 J.l.S at I MHz. Analog conversion starts selecting
analog inputs by bit 0 and bit I of the ADCSR analog input.
Since the CPU is not required during conversion, other user
programs can be executed.
This register at location $01 F gives the status information
about the RAM. When RAM Enable bit (RAME) is "0", the
RAM is disabled. When Vee Standby is greater than VSBB,
Standby Power bit (STBY PWR) is set and the standby RAM is
sustained during powerdown.
Table 7 Analog Input Selection
RAM Control Register (RCR: $OalF)
ADCSR
•
7
Analog Input Signal
Bit 1
Bit a
a
a
d
ANo
1
ANI
1
a
1
1
AN z
AN3
$001F
AID Control Status Register (ADCSR: $OOOE)
AID Result Register (ADRR: $OOOF)
•
STANDBY RAM
RAM"
When the AID conversion ends, the result is set in the A/D
Result Register ($OOOF). When CEND of the ADCSR is set,
converted result is obtained by reading the ADRR. Furthermore, CEND is cleared.
The portion from $020 to $027 of the RAM can be used for
the standby RAM.
When using the standby RAM, Vee Standby should remain
above VSBB (min) during powerdown. Consequently, power is
provided only to the standby RAM and STBY PWR bit of the
RAM Control Register. 8 byte RAM is sustained with small
power dissipation. The RAM including the standby RAM is
controlled by the RAM Control Register (RCR) or RAME pin.
RAME bit is set or cleared by either software or hardware.
When the MCU is reset, RAME bit is set and the RAM is enabled. If RAME bit is cleared, the user can neither read nor write
the RAM.
When the RAM is disabled (logic "0"), the RAM address is
invalid.
Bit 7 Standby Power
STBY PWR bit is cleared whenever Vee standby decreases
below VSBB (min). This bit is a read/write status bit that the
user can read. When this bit is set, it indicates that the standby
power is applied and data in the standby RAM is valid.
•
RAME Signal
RAME bit in the RCR can be cleared when RAME pin goes
"Low" by hardware (RAM is disabled). To make standby mode
by hardware, set RAME pin "Low" during Vee Standby remains above VSBB (min) and powerdown sequence should be as
shown in Fig. 17.
When RAME pin gets "Low" in the powerup state, RAME
bit of the RCR is cleared and the RAM is disabled. During
powerdown, RAME bit is sustained by Vee Standby. When
RAME pin gets "High" in the powerup state, RAME bit of the
RCR is set and the RAM is enabled.
RAME pin can be used to control the RAM externally without software.
Vee
\
RAME
RAM CTRL
~====:::::::;;;;::~~~..L..J
021/1NVl
Bit 6 RAM Enable
The Control Status Register (ADCSR) is used to select
analog input pin and confirm A/D conversion termination.
An analog input pin is selected by bit 0 and bit I as shown in
Table 7.
A/D conversion begins when the data is written into bit 0
and bit I of the ADCSR. When A/D conversion ends, bit 7
(CEND) is set. Bit 7 is reset after the ADRR is read. Even if
bit 7 is set, A/D conversion execution still continues. To end
the A/D conversion, the A/D Result Register (ADRR) stores the
most current value. During A/D conversion execution, new
data is written into the ADCSR selecting the input channel and
the A/D conversion execution at that time is suspended. CEND
is reset and new A/D conversion begins.
•
I ~ri I
6543210
Reg. 1$001 F 1
RAM Enable
vee OFF
/
~------r
~
RAMm.....
Figure 17 RAM Control Signal (RAME)
RAM
196BI
1--_ _ _
•
~$OO7F
Figure 16 Standby RAM
BIT MANIPULATION
The MCU has the ability to set or clear any single RAM or
input/output port (except the data direction registers) with a
single instruction (BSET and BCLR). Any bit in the page zero
read only memory can be tested by using the BRSET and
eHITACHI
615
HD68P05WQ------------------------------------------------------------BRCLR instructions, and the program branches as a result of
its state. This capability to work with any bit in RAM, ROM or
I/O allows the user to have individual flags in RAM or to handle
single I/O bits as control lines. The example in Figure 18 shows
the usefulness of the bit manipulation and test instructions.
Assume that bit 0 of port A is connected to a zero crossing
detector circuit and that bit 1 of port A is connected to the
trigger of a TRIAC which powers the controlled hardware.
This program, which uses only seven bytes of ROM provides tum-on of the TRIAC within 14 microseconds of the zero
crossing. The timer is also incorporated to provide tum-on at
some later time which permits pulse-width modulation of the
controlled power.
•
SELF 1
·
···
•
Indexed (No Offset)
Refer to Figure 23. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and their EA is the contents of the index register.
• Indexed (a-bit Offset)
Refer to Figure 24. The EA is calculated by adding the contents of the byte following the opcode to the contents of the
index register. In this mode, 511 low memory locations are
accessable. These instructions occupy two bytes.
BRClRO, PORTA, SELF 1
BSET 1, PORTA
BClR 1, PORTA
• Indexed U6-bit Offset)
Refer to Figure 25. This addressing mode calculates the EA
by adding the contents of the two bytes following the ope ode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are
three bytes long.
Figure 18 Bit Manipulation Example
• ADDRESSING MODES
The MeU has ten addressing modes available for use by the
programmer. These modes are explained and illustrated briefly
in the following paragraphs.
• Immediate
Refer to Figure 19. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte following the
opcode.
• Direct
Refer to Figure 20. In direct addressing, the address of the
operand is contained in the secondbyte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. AU RAM space, I/O registers and 128
bytes of ROM are located in page zero to take advantage of
this efficient memory addressing mode.
• Extended
Refer to Figure 21. Extended addressing is used to reference
any location in memory space. The EA is the contents of the
two bytes following the opcode. Extended addressing instructions are three bytes long.
• Relative
Refer to Figure 22. The relative addressing mode applies only
616
to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA =(PC) + 2 + ReI. Rei is the contents of the location following the instruction opcode with bit 7
being the sign bit. If the branch is not taken, Rei = 0, when a
branch takes place, the program goes to somewhere within the
range of + 129 bytes to -127 bytes of the present instruction.
These instructions are two bytes long.
• Bit Set/Clear
Refer to Figure 26. This mode of addressing applies to
instructions which can set or clear any bit on page zero. The
lower three bits in the opcode specify the bit to be set or
cleared while the byte following the opcode specifies the
address in page zero.
• Bit Test and Branch
Refer to Figure 27. This mode of addressing applies to
instructions which can test any bit in the fust 256 locations
($0000 through $ooFF) and branch to any location relative to
the PC. The byte to be tested is addressed by the byte following
the opcode. The individual bit within that byte to be tested
is addressed by the lower three bits of the opcode. The third
byte is the relative address to be added to the program counter
if the branch condition is met. These instructions are three
bytes long. The value of the bit to be tested is written to the
carry bit in the condition code register.
• Implied
Refer to Figure 28. The implied mode of addressing has
no EA. All of the information necessary to execute an instruction is contained in the opcode. Direct operations on the
accumulator and the index register are included in this mode
of addressing. In addition, control instructions such as SWI
and RTI belong to this group. All implied addressing instructions are one byte long.
_HITACHI
-------------------------------------------------------------HD68P05WO
Memory
i
I
I
I
I
8
I
PROG LOA #$F8 05BE
05BF
A
F8
Index
I
es
Stack Point
I
I
A6
Prog Count
F8
05CO
1-------4
§
I
I
I,
Figure 19 Immediate Addressing Example
lEA
+
Memory
I
I
I
I
I
I
I
I
I
I
I
I
CAT
FCB
32
I
004B
/'
Adder
1
20
004B
J
~
O~OO
A
J
l
20
J
Index Reg
I
I
I
PROG
LOA
CAT
0520
86
052E
4B
Stack Point
I
I
Prog Count
I
052F
I
I
I
CC
~
I
I
I
I
i
Figure 20 Direct Addressing Example
_HITACHI
617
HD68P05WO------------------------------------------------------------Memory
0000
A
40
PROG
LOA
CAT
Index Reg
Stack Point
Prog Count
CAT
FeB
64
40
06E5
040C
CC
Figure 21 Extended Addressing Example
Memory
i
I
I
~
A
Index Reg
Stack Point
I
PROG
SEQ
PROG2
04A7
27
04A8
18
§
I
,
0000
I
,
Figure 22 Relative Addressing Example
618
~HITACHI
---------------------------------------------------------------HD68P05WO
Memory
A
TABL
FCC
t Lit 00B8
4C
4C
49
Index Reg
B8
I
PROG
LOA
X
I
Stack Point
~F4~
Prog Count
05F5
CC
§
,I
Figure 23 Indexed (No Offset) Addressing Example
lEA
Melory
I
I
I
I
BF
FCB
#BF
0089
FCB
#86
008A
B6
FCB
#OB
008B
DB
FCB
#CF
008C
CF
I
I
PROG
LOA
t
J
J
TABL
I
L
Adder
E6
075C
89
'"
I
I'
I
I
I
TABL. X 075B
I
008C
L
I
CF
I
Index Reg
I
Stack Point
I
03
I
I
Prog Count
I
I
A
J
0750
CC
I
I
§
I
,
I
,
Figure 24 Indexed (8-Bit Offset) Addressing Example
_HITACHI
619
HD68P05WO-------------------------------------------------------------
Memory
i
I
§
A
DB
Index Reg
I
PROG
LOA
TABL. X 0692
0693
0694
02
I
~6
07
7E
Stack Point
f--------'
Prog Count
0695
I
TABl
CC
I
FCB
#BF
077E
BF
86
FCB
#86
077F
FCB
#DB
0780 ~--!:D~B~_
FCB
#CF
0781
_t----.:..-------------'
CF
Figure 25 Indexed (l6-Bit Offset) Addressing Example
Memory
PORT B EQU
BF
0001
A
0000
Index Reg
PROG BelR 6. PORT B
058F
0590
10
t-------I
01
Stack Point
Prog Count
0591
I
I
CC
§
I
I
I
Figure 26 Bit Set/Clear Addressing Example
620
$
HITACHI
---------------------------------------------------------------HD68P05WO
,
,,
Mem~OrY
lEA
i
I
PORT C
EQU
0002
2
I
t
I
'/
FO
I
0002
Adder
~
t
Bit
2
0000
,
Index Reg
Stack Point
I
I
I
PROG BRCLR 2. PORT C. PROG 2
A
I
I
I
I
0574
05
0575
02
0000
0594
0576
10
J
CC
I
I
I
Prog Count
~
,
I
~
"
OR
~
~
C
J
/
I
,
I
I
J
Adder
J
Figure 27 Bit Test and Branch Addressing Example
Memory
i
,,,
.~
A
E5
Index Reg
,
E5
I
PROG
TAX
05BA~
Prog Count
05BB
,,
cc
§
Figure 28 Implied Addressing Example
$
HITACHI
621
·HD68P05WO------------------------------------------------------------•
INSTRUCTION SeT
•
The MeV has a set of 59 basic instructions. These instructions can be divided into five different types; register/memory,
read/modify/write, branch, bit manipulation and control. Each
instruction is briefly explained below. All of the instructions
within a given type are presented in individual tables.
•
Register/Memory Instructions
Most of these instructions use two operands. One operand
is either the accumulator or the index register. The other
operand is obtained from memory by using one of the addressing modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Refer to
Table 8.
•
ReadlModify/Write Instructions
These instructions read a memory location or a register,
modify or test its contents and write the modified value back
to the memory or register. The TST instruction for test of
negative or zero is an exception to the read/modify/write
instructions since it does not perform the write. Refer to Table
9.
622
Bit Manipulation Instructions
These instructions are used on any bit in the first 256 bytes
of the memory. One group either sets or clears. The other
group performs the bit test and branch operations. Refer to
Table 11.
•
Controllnstructi!>ns
The control ilJstructions control the MeV operations during
program execution. Refer to Table 12.
•
•
Branch Instructions
The branch instructions cause a branch from a program
when a certain condition is met. Refer to Table 10.
Alphabetical Listing
The complete instruction set is given in alphabetical order
in Table 13.
•
OpcodeMap
Table 14 is an opcode map for the instructions used on the
MeV.
_HITACHI
Table 8 Register/Memory Instructions
Addressing Modes
Function
Mnemonic
Immediate
Op
Op
Op
#
#
#
#
Code Bytes Cycles Code Bytes Cycles Code
%
o~
!
Op
#
#
Bytes Cycles Code
Indexed
(8-Bit Offset)
Op
#
#
Bytes Cycles Code
Indexed
(16-Bit Offset)
Op
#
#
Bytes Cycles Code
#
#
Bytes Cycles
Load A from Memory
LOA
A6
2
2
B6
2
4
C6
3
5
F6
1
4
E6
2
5
06
3
6
Load X from Memory
LOX
AE
2
2
BE
2
4
CE
3
5
FE
1
4
EE
2
5
OE
3
6
Store A in Memory
STA
-
-
B7
2
5
C7
3
6
F7
1
5
E7
2
6
07
3
7
STX
-
-
-
5
CF
3
6
FF
1
5
EF
2
6
OF
3
7
1
4
EB
2
5
OB
3
6
Store X in Memory
$
Indexed
(No Offset)
Extended
Direct
BF
2
Add Memory to A
ADD
AB
2
2
BB
2
4
CB
3
5
FB
Add Memory and
carry to A
ADC
A9
2
2
B9
2
4
C9
3
5
F9
1
4
E9
2
5
09
3
6
Subtract Memory
SUB
AO
2
2
BO
2
4
CO
3
5
FO
1
4
EO
2
5
00
3
6
Subtract Memory from
A with Borrow
SBC
A2
2
2
B2
2
4
C2
3
5
F2
1
4
E2
2
5
02
3
6
AND Memory to A
AND
A4
2
2
B4
2
4
C4
3
5
F4
1
4
E4
2
5
04
3
6
OR Memory with A
ORA
AA
2
2
BA
2
4
CA
3
5
FA
1
4
EA
2
5
OA
3
6
Exclusive OR Memory
with A
EOR
A8
2
2
B8
2
4
C8
3
5
F8
1
4
E8
2
5
08
3
6
Arithmetic Compare A
with Memory
CMP
Al
2
2
Bl
2
4
Cl
3
5
Fl
1
4
El
2
5
01
3
6
Arithmetic Compare X
with Memory
CPX
A3
2
2
B3
2
4
C3
3
5
F3
1
4
E3
2
5
03
3
6
Bit Test Memory with A
(Logical Compare)
BIT
A5
2
2
B5
2
4
C5
3
5
F5
1
4
E5
2
5
05
3
6
Jump Unconditional.
JMP
-
-
-
BC
2
3
CC
3
4
FC
1
3
EC
2
4
DC
3
5
Jump to Subroutine
JSR
-
-
-
BD
2
7
CO
3
8
FO
1
7
EO
2
8
00
3
9
----
-
~~
:J:
Symbols:
Op: Operation Abbreviation
# : Instruction Statement
o
0)
(X)
"tJ
o
0)
I\)
c:.l
CJ1
~
0)
::I:
I\)
~
0)
o
00
"'0
o(11
~
Table 9
Read/Modify/Write Instructions
Addressing Modes
Function
Implied (A)
Mnemonic
Op
Code
Op
#
#
Bytes Cycles Code
Indexed
(No Offset)
Direct
Implied (X)
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(8-Bit Offset)
Op
#
#
Bytes Cycles Code
#
#
Bytes Cycles
Increment
INC
4C
1
4
5C
1
4
3C
2
6
7C
1
6
6C
2
7
Decrement
DEC
4A
1
4
5A
1
4
3A
2
6
7A
1
6
6A
2
7
Clear
CLR
4F
1
4
5F
1
4
3F
2
6
7F
1
6
6F
2
7
Complement
COM
43
1
4
53
1
4
33
2
6
73
1
6
63
2
7
%
Negate
(2's Complement)
NEG
40
1
4
50
1
4
30
2
6
70
1
6
60
2
7
o
Rotate Left Thru Carry
ROL
49
1
4
59
1
4
39
2
6
79
1
6
69
2
7
6
76
1
6
66
2
7
7
~
~
Rotate Right Thru Carry
ROR
46
1
4
56
1
4
36
2
Logical Shift Left
LSL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
Logical Shift Right
LSR
44
1
4
54
1
4
34
2
6
74
1
6
64
2
7
Arithmetic Shift Right
ASR
47
1
4
57
1
4
37
2
6
77
1
6
67
2
7
Arithmetic Shift Left
ASL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
Test for Negative or
Zero
TST
4D
1
4
5D
1
4
3D
2
6
7D
1
6
6D
2
7
Symbols:
Op: Operation Abbreviation
# : Instruction Statement
-------------------------------------------------------------HD68P05WO
Table 10 Branch Instructions
Relative Addressing Mode
Mnemonic
Function
Op
Code
#
#
Bytes
Cycles
Branch Always
BRA
20
2
Branch Never
BRN
21
2
4
4
Branch IF Higher
BHI
22
2
4
Branch I F lower or Same
BlS
23
2
4
Branch I F Carry Clear
BCC
24
2
4
(Branch IF Higher or Same)
(BHS)
24
2
4
Branch I F Carry Set
BCS
25
2
4
(Branch I Flower)
(BlO)
25
2
4
Branch I F Not Equal
BNE
26
2
4
4
Branch I F Equal
BEQ
27
2
Branch IF Half Carry Clear
BHCC
28
2
4
Branch I F Half Carry Set
BHCS
29
2
4
4
Branch IF Plus
BPl
2A
2
Branch IF Minus
BMI
2B
2
4
Branch IF Interrupt Mask Bit is Clear
BMC
2C
2
4
Branch IF Interrupt Mask Bit is Set
BMS
20
2
4
Branch IF Interrupt Line is low
Bil
2E
2
4
Branch IF Interrupt Line is High
BIH
2F
2
4
Branch to Subroutine
BSR
AD
2
8
Symbols: Op: Operation Abbreviation #: Instruction Statement
Table 11
Bit Manipulation Instructions
Addressing Modes
Bit Test and Branch
Bit Set/Clear
Mnemonic
Function
Op
Code
-
#
#
Cycles
Op
Code
Bytes
Cycles
-
2·n
3
10
-
01+2·n
3
10
-
#
#
Bytes
-
Branch IF Bit n is set
BRSET n (n=O ..... 7)
Branch I F Bit n is clear
BRClR n (n=O ..... 7)
Set Bit n
BSET n (n=O ..... 7)
10+2·n
2
7
-
-
Clear bit n
BClR n (n=O ..... 7)
11+2·n
2
7
-
-
Symbols: Op: Operation Abbreviation #: Instruction Statement
Table 12 Control Instructions
Implied
Function
Mnemonic
Op
Code
#
#
Bytes
Cycles
Transfer A to X
TAX
97
1
2
Transfer X to A
TXA
9F
1
Set Carry Bit
SEC
99
1
Clear Carry Bit
ClC
98
1
1
Set Interrupt Mask Bit
SEI
9B
Clear Interrupt Mask Bit
CLI
9A
1
2
2
2
2
2
Software Interrupt
SWI
83
1
11
Return from Subroutine
RTS
81
1
6
Return from Interrupt
RTI
80
1
9
Reset Stack Pointer
RSP
9C
1
No-Operation
NOP
90
1
2
2
..
Symbols: Op: Operation AbbreViation #: Instruction Statement
$
HITACHI
625
HD68P05WO--------------------------------~------------------------___
Table 13 Instruction Set
Mnemonic
ADC
ADD
AND
ASl
ASR
BCC
BClR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
Bil
BIT
BlO
BlS
BMC
BMI
BMS
BNE
BPl
BRA
BRN
BRCLR
BRSET
BSET
BSR
CLC
Cli
CLR
CMP
COM
CPX
DEC
EaR
INC
JMP
JSR
LDA
LOX
Implied Immediate
x
x
x
x
x
x
x
x
x
x
Relative
x
x
x
Addressing Modes
Indexed Indexed Indexed
(No
(16 Bits)
Offset) (8 Bits)
x
x
x
x
x
x
x
x
x
x
x
x
x
Condition Code
Bit
Set!
Clear
Bit
Test & H
Branch
A
A
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Condition Code Symbols:
Half carry (From Bit 3)
H
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
626
ExDirect
tended
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
C
A
•
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
_HITACHI
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
I
N
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
•
•
•
•
•
A
A
A
A
A
A
A
A
A
A
A
A
•
•
•
•
•
•
•
•
•
•
A
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
A
A
•
••
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• •
• A
• A
• •
• •
• 0
• •
1 •
A
0
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1
A
•
•
•
• • •
• • •
A A •
(to be continued)
•
---------------------------------------------------------------HD68P05WO
Table 13 Instruction Set
Addressing Modes
Mnemonic
Implied
Immediate
Direct
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
Relative
Extended
LSL
x
x
x
x
LSR
x
x
x
x
NEQ
x
x
x
x
NOP
x
x
x
x
ROL
x
x
x
x
ROR
x
x
x
x
RSP
x
x
x
ORA
Bit
Set/
Clear
Bit
Test &
Branch
H
•
•
•
•
•
x
I
• •
1\
?
x
?
x
• • •
• • 1\
• • •
• 1 •
• • 1\
• • 1\
• • 1\
• 1 •
• • •
• • 1\
• • •
x
x
x
SEI
x
x
x
x
x
STA
x
x
x
x
STX
x
x
x
x
x
x
x
x
x
x
x
SUB
SWI
x
TAX
x
TST
x
TXA
x
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
I nterrupt Mask
N
Negative (Sign Bit)
Z
Zero
C
1\
1\
• • 1\ 1\ 1\
• • • • •
RTS
SEC
C
• 1\ 1\ 1\
• 0 1\ 1\
• 1\ 1\ 1\
• • • •
• 1\ 1\ •
RTI
SBC
Z
N
x
x
?
?
?
• •
1\
1\
• 1
• •
1\ •
1\ •
1\
1\
• •
• •
1\ •
• •
Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
1\
•
?
Table 14 Opcode Map
Bit Manipulation
Test &
Branch
Setl
Brnch
Rei
OIR
I
A
I
X
2
3
I
4
I
5
BRA
I
Xl
I
I ,XO
I
7
8
9
A
RTI'
-
RTS*
-
CMP
1
-
SBC
2
1
BRCLRO
BCLRO
BRN
-
2
BRSET1
BSET1
BHI
-
3 BRCLR1
BCLR1
BLS
COM
BRSET2
BSET2
BCC
LSR
-
-
-
4
1
IMM
BRSETO
NEQ
I
J
IMP
0
6
I OiR I EXT I X2 I Xl
IMP
1
BSETO
0
Register IMemory
Control
Read/Modify/Write
Clear
SWI'
B
I
C
1
0
SUB
-
BIT
5 W
-
LOA
STA(+1)
6
7
8
9
BCS
BNE
ROR
7
BRCLR3
BCLR3
BEQ
ASR
8 BRSET4
9 BRCLR4
BSET4
BHCC
LS LIAS L
-
CLC
EOR
BCLR4
BHCS
ROL
-
SEC
AOC
BRSET5
BSET5
BPL
DEC
-
B BRCLR5
BCLR5
BSET6
BMI
-
-
CLI
SEI
o
INC
-
TST
-
TAX
RSP
I
ORA
ADD
C
BSR*I
JSR(-3)
0
LOX
E
E BRSET7
BSET7
BIL
-
-
-
F BRCLR7
BCLR7
BIH
CLR
-
TXA
-
1
1/'
1/2
2/2
I
2/7
2/4
2/6
I 1/4
I 1/4
I 2/7
I 1/6
B
I
-
STX(+1)
2/4
I 3/5
I 3/6
L
o
A
JMPH)
BCLR6
3/10
NOP
-
BRCLR6
BMS
0
3
4
BSET3
BMC
... H IGH
AND
BCLA2
C BRSET6
F
cpx
BRSET3
A
,XO
-
5 BRCLR2
-
E
-
6
-
I
I 2/5
F
I 1/4
[NOTE) 1. Undefined opcodes are marked with "-".
2. The number at the bottom of each column denotes the number of bytes and the number of cycles required (Bytes/Cycles).
Mnemonics followed by a "." require a different number of cycles as follows:
RTI
9
RTS
6
SWI
11
eSR
8.
3. (
) indicates that the number in parenthesis must be added to the cycle count for that instruction.
$
HITACHI
627
HD68P05WO------------------------------------------------------------•
HD68P05WO USED FOR HD6805W1
The HD680SWI provides mask option of the internal oscillator and low voltage inhibit, while the HD68POSWO provides
only crystal option and without low voltage inhibit function,
The address from $OF7A to $OFFI cannot be used for user
program because the self test program of the HD680SWI (on-
.......,
-
RAM
.... al
-
SOOOO
$000'
$0002
IOO'F
121
'28
chip ROM version) is located at these addresses,
In order to be pin compatible with the HD680SW1, the
address of the HD68POSWO's ROM must be located at $0080 $OFFF, Memory addresses $1000 to $1 FFF should not be
usable,
~
$0003"
$0004'
03'
032 I---------I=~
RAM
196al
$0006'
1OO7F
$007F
$0006'
SOO8O
$0007
Tim.r Oale Reg. 1
SOOO8
Timer CTRL Reg, 1
$0009
$OOOA
"OM
18050 I
$0008
10010
10011
1--_ _ _ _ _ _---1
10012
1--_ _ _ _ _ ___1
SOOOF··
10013
1001.
1001.
10018
I--_ _ _ _ _ _~
I--_ _ _ _ _ _~
1--_ _ _ _ _ ___1
I--_ _ _ _ _ _ .~
I--_ _ _ _ _ _~
10019
I----=p::::".:::".~=_'::.:.CT.:::"L:.::"~~:.:.
'_~ $0019
1OO1A"
I-----=T.:::'...:::.,:::S":::,",:.:."",,
..;..:.' _ _-I $001A··
I--~T.:::"":::.':::.CT.:.:."L:..:.";.:.:"c.:.' _ _-I $0018
I-----=T.:::'"":::.,.:::O,:=,,.:.:.:"..:::..:..,_ _-I $00IC
I-----=O.:::u,=pu.:...::Oo:..:......
=-,._".:..:.._~ $0010
10017
$0018
Timer CTRl Reg. 2
$00IC
$0010
Output Complr. RItg
- - - - - - - - - - - - - - -
SOF7A
(Self Ten)
:;I--------I:~~~
$00IE"
10016
$0017
$0018
~--=::::":=~'------l =~
Standby RAM 18BI'"
,
__________________
10027
St*,dby RAM 18 8t···
s6007
- - - - - - - - - - - - - - - - - - $0028
10028
sr
)
)
' -_ _ _ _--1.._---1 $007F
·Writ.Reg
·WrlteAIf.
'-ReadReg
"'Standby RAM uses fim B byllH of RAM
·-ReIldR".
• ··StlnCIbV RAM
UIIt
fir.t B by'" 0' RAM
Figure 29 MCU Memory Structure (For 32k bytes)
h't~uplVecton
L-_ _ _ _ _ _...J"FFF
Figure 30 MCU Memory Structure (For 64k bytes)
-CAUTION This 64k bytes type should not be used debugging
on-chip ROM of the HD6805W1.
628
$0015
\I--"::=::'=::::':.::!:...---l $00IE"
~~"=AM~C=on="O~I"~~~-__I::~
InttrruptVecton
L-_ _ _ _ _ _...JSOFFF
$0012
1--_ _ _ _ _ _---1
10016
TimerSt&lusReg.2
10011
10013
10015
Prescaler eTR l Reg. 2
I----=:.::::::.=:.=~_~ $0009
1-----===='------1
$OOOA
1--_ _ _ _ _ _ _---1 $0008
I--________---I$OOOC
1--_ _ _ _ _ ___1 $0000
I----=A::;:'O..::..CT:.:.:"::..:LS::::,,,:::u'':'::"~'''--_-l $OOOE
I---==::::::":~_ ___I $OOOF"
1--_ _ _ _ _ ___1 $0010
$OOOC
$0000
$OOOE
AID CrRL Stanll Reg
1----==_ _ _ ___1 soooo
1----==_ _ _ ___1 $0001
1----==_ _ _ ___1 $0002
I----.-:=_ _ _ _~ $0003"
I----.-:==_ _ _~ $0004'
1----===_ _ ___1 $0005'
I----.-:==_ _ _~ $0006'
.I--_ _ _ _ _ _~ $0007
I-----.:T~'me=_':::0'::.:""::;"!:..:.'~_ __I SOOO8
eHITACHI
-------------------------------------------------------------HD68P05WO
•
PRECAUTION TO USE EPROM ON THE PACKAGE 8-BIT
SINGLE-CHIP MICROCOMPUTER
As this microcomputer takes a special packaging type with
pin sockets on its surface, pay attention to the followings;
(1) Do not apply higher electro-static voltage or serge voltage
etc. than maximum rating, or it may cause permanent
damage to the device.
(2) There are 28 pin sockets on its surface. When using 32k
Let the index-side four pins open.
When using 24 pin EPROM, match
its index and insert it into lower
24 pin sockets.
EPROM (24 pins), let the index-side four pins open.
(3) When assembling this LSI into user's system products as
well as the mask ROM type 8-bit single-chipmicrocomputer, pay attention to the followings to keep the good ohmic
contact between EPROM pins and pin sockets.
(a) When soldering on a printed circuit board, etc., keep its
condition under 250°C within 10 seconds. Over-time/
temperature may cause the bonding solder of socket
pins to meet and the sockets may drop.
(b) Keep out detergent or coater from the pin sockets at
aft-solder flux removal or board coating. The flux or
coater may make pin socket contactivity worse_
(c) Avoid the permanent use of this LSI under the evervibratory place and system.
(d) Repeating insertion/removal of EPROMs may damage
the contactivity of the pin sockets, so it is recommended to assemble new ones to your system products.
Ask our sales agent about anything unclear.
$
HITACHI
629
HD63P01 M1 ,HD63PA01 M1,HD63PB01 M1
CMOS MCU (Microcomputer Unit)
The HD63POIMI is an 8-bit single chip Microcomputer Unit
(MeU) which has 4096 bytes or 8192 bytes of EPROM on
the package. It is pin and function (except ROM) compatible
with the HD6301Vl. The HD63POIMI can be used to emulate
the HD6301Vl for software development or it can be used in
production to allow for easy firmware changes with minimum
delay.
•
•
•
•
•
•
•
•
•
FEATURES
Pin Compatible with HD6301V1
On Chip Function Compatible with HD6301V1
• 128 Bytes of RAM
• 29 Parallel I/O
• 16 Bit Programmable Timer
• Serial Communication Interface
Low Power Consumption Mode
Sleep Mode, Standby Mode
Minimum Instruction Cycle Time
l~s (f = 1MHz), O.67~s (f = 1.5MHz),
0.51ts (f = 2MHz)
Bit Manipulation, Bit Test Instruction
Protection from System Upset
Address Trap, Op-Code Trap
Up to 65k Words Address Space
Applicable to 4k or 8k Bytes of EPROM
4096 Bytes: HN482732A
8192 Bytes: HN482764, HN27C64
- The specifications for HD63PA01Ml and HD63PB01Ml are preliminary. -
HD63P01M1, HD63PA01M1,
HD63PB01M1
•
PIN ARRANGEMENT
HD63P01Ml, HD63PA01M1, HD63PB01Ml
o
NMi
• TYPE OF PRODUCTS
Type No.
HD63P01M1
Bus Timing
1MHz
EPROM Type No.
HN482732A·30, HN482764·3, HN27C64-30
HD63PA01M1*
1.5MHz
HN482732A-30, HN482764-3, HN27C64-30
HD63PB01 M 1·
2MHz
HN482732A-25, HN482764, HN27C64-25
• Preliminary
OVcc
OAu
OA7
OAe
OAs
OA,
OA3
OA2
OA,
OAo
000
00,
002
OVSS
Vee
Vee
Vee
A.
At
0
0
0
0
0
A" 0
Vss 0
A,o 0
CE 0
'07 0
Oe 0
05 0
0, 0
03 0
(Top View)
(NOTE)
630
~HITACHI
EPROM is not included.
------------------------------------------HD63P01M1.HD63PA01M1.HD63PB01M1
•
BLOCK DIAGRAM
.....-~-+-+P20
h+-r-~~P2.
h++-...--...... P22
h+-4--'I'--.-_ P 23
14+-1-1-+........ P2 •
......- - - P . o
J.----Pl\
......- - - P . 2
J.----P\J
......- - - P ••
J.----Pls
J.----PI6
......- - - P 1 7
On Package
1----------- - - I
I
EPROM
HN482732Al
( HN482764
HN27C64
00
O.
02
I
1
03
O.
Os
I
~
I
•
,~
(§
~
6
R , Cil
R
6
R
, k6
R
,~,
R
R
R
R
R
S
R R
R R
S. R R
••
••
••
t
t
t R
t
R
t 1
t t
R
R
•
••
Note) Condition Code Register will be explained in Note of Table 11.
•
New Instructions
In addition to the HD6801 Instruction Set, the HD63POIMI
has the following new instructions:
AIM----(M)· (lMM)-+(M)
Evaluates the AND of the immediate data and the
memory, places the result in the memory.
OIM---- (M) + (lMM) -+ (M)
Evaluates the OR of the immediate data and the
memory, places the result in the memory.
EIM- - --(M) (!) (IMM) -+ (M)
Evaluates the EOR of the immediate data and the
contents of memory, places the result in memory.
652
TIM----(M)· (lMM)
Evaluates the AND of the immediate data and the
memory, changes the flag of associated condition code
register
Each instruction has three bytes; the fust is op-code, the
second is immediate data, the third is address modifier.
XGDX--(ACCD) ~ (IX)
Exchanges the contents of accumulator and the index
register.
SLP----The MPU is brought to the sleep mode. For sleep
mode, see the "sleep mode" section.
~HITACHI
---------------------HD63P01M1,HD63PA01M1,HD63PB01M1
Table 9 Index Register, Stack Manipulation Instructions
Acldressing Modes
Pointer Operations
Mnemonic
OP
Compare Index Reg
CPX
Decrement Index Reg
DEX
Decrement Stack Pntr
Increment Index Reg
Increment Stack Pntr
DIRECT
IMMED.
8C
-
#
OP
3 3 9C
4
INDEX
-
#
OP
2
AC 5
#
EXTEND
IMPLIED
OP
OP
2 BC
-
#
-
5 3
Booleanl
Arithmetic Operation
H
#
09
1
'X-M:M+l
1 X-l-X
DES
34
1
1 SP-l-SP
INX
OB
1
1 X + 1- X
INS
31
1
1 sP+l-SP
DE 4
2
EE
4
2
AE 5
5
2
FE
load Index Reg
lOX
CE
3
load Stack Pntr
lOS
8E
3 3 9E
Store Index Reg
STX
OF
Store Stack Pntr
STS
9F
Index Reg - Stack Pntr
TXS
35
1
SP H - M. SP L - IM+ 11
1 X-l-sP
Stack Pntr - Index Reg
TSX
30
1
1 SP+1-X
Add
ABX
3A
1
1
Push Data
PSHX
3C
5
1 XL - Mil>' SP - 1 - SP.
Pull Data
PUlX
38
4
XH - Mil>' SP - 1 - SP
1 SP+l-SP,MII>-X H
SP + 1 - SP, Mil> - XL
Exchange
XGDX
1B
2
1
3
2 BE
EF
5 2 FF
4 2 AF 5 2 BF
4
2
5
3
M-XH.IM+1I-X L
M- sP H , IM+1I-SP L
X H - M, XL - 1M + 11
5 3
5 3
5 3
Condition Code
Aegister
5 4 3 2 1 0
B+X~
X
ACCD~IX
I N Z V C
·····• ·· · ·· ··
···· ·· · ·· ··
····· , ···
··· · · ···
······ ·· ····
·· · · · ·
· ·· ·· ·
••• ••
t
~
t
~
~
~
Zero
BGT
2E
3
2
Z+ IN @ VI- 0
Branch If Higher
BHI
22
3 2
Branch If < Zero
BlE
2F
3
2
Z+ IN ~ VI- 1
Branch If lower Or
Seme
BlS
23
3
2
C+Z=1
Branch If < Zero
BlT
20
3
2
N@V-l
Branch If Minus
BMI
2B
3
2
N -1
Branch If Not Equal
Zero
BNE
26
3
2
Z=O
Branch If Overflow
Clear
BVC
28
3
2
V-O
Branch If Overflow Set
BVS
Branch If Plus
BPl
29 3 2
2A 3 2
80 5 2
N-O
Branch If
~
Branch To Subroutine
BSR
Jump
JMP
Jump To Su'broutine
JSR
No Operation
NOP
Return From Interrupt
Return From
Subroutine
Softwar. Interrupt
Wait for Interrupt*
Sleep
3
2
C+Z-O
V -I
6E
90
5
2
3
AD 5
2 7E
3 3
2 BD 6
3
01
1 1
RTI
3B 10 1
RTS
39
SWI
3F 12 1
WAI
SLP
3E
5
9
1A 4
Advances Prog. Cntr.
Only
1
1
1
N tel ·WAI· puts R/W high; Address Bus goes to FFFF; Data Bus goes to the three state.
o
Condition Code Register will be explained in Note of Table 11.
eHITACHI
5 4 3 2 1 0
H I N Z V C
·· ·· ·· ·· ·· ··
··· ···., ···.. ··· ··· ···
·· ·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·
·· ·· ·· ·· ·· ·
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
···· ·· ·· ·· ··
·· · · · ·
·· · ·· ·· ·· ··
· ···
.1.-..
--@-
S
@.
••••••
653
HD63P01M1,HD63PA01M1,HD63PB01M1--------------------Table 11
Condition Code Register Manipulation Instructions
Condition Code Register
"ddreaingModet
OperMionl
Mnemonic
C.... Carry
Clear Interrupt Mask
CleerOwrflow
Set Carry
Set Interrupt Mask
Set Owrflow
Accumulator A - CCR
CCR - Accumulator A
Boolean ()peration
IMPLIED
OP
1
1
OC
1
OE
1
1
OA
1
00
1
1
1
OF
1
1
OB
1
1
06
1
1
07
1
-
ClC
CLI
ClV
SEC
SEI
SEV
TAP
TPA
"
5
H
3
N
4
I
1
V
2
Z
0
C
R
·· · ··• ·· ·· ·
·· ·· · ·· · ·
·· · ·· ·· · ··
······
O-C
0-1
O-V
l-C
1-1
1-V
A- CCR
CCR-A
R
R
S
S
S
--@---
[NOTE 11 Condition Code
CD (Bit V)
@
(Bit C)
@
(Bit C)
@
(Bit V)
@
(Bit V)
@
(Bit V)
6240
(CGI*'
-
-
-
7360
(CGI*'
-
-
32 x8
80 x 8
200 x 8
-
-
(external
65536 x 81
512 x 8
-
12
21
21
6
6
13
21
4
5
5
5
9
-
6
5
-
18
-
-
-
33
-
-
B
6
6
-
-
12
7
-
15
-
-
20
32
-
-
64
40
-
50
-
-
-
64
-
1/8,1/12,
1/8,1/12,1/16,
1/24,1/32
1/8,1/12,1/16,
1/24,1/32
Static,
1/1 - 1/12B
- 1/64
1/48,1/64
1196,1/128
32 x 50
Dots
(1/32 Dutvl
-
-
-
64 x64
Dots
(1/64 dutyl
-
Common
Driver
Display to
524288
Dots using
HD44100H
117,1/14
1~16
16 Digits
(5 x 7 Dots
1/14 Dutyl
-
Expandable
to 32 Digits
using
HD44100H
Display to
80 Digits
using
HD44100H
Segment
Driver
Common
Driver
1/8,1/12,1/16,1/24,
1/32,1/48,1/64
~HITACHI
Segment
Driver
Common
Driver
681
[fc MEMORIES
• MOSRAM
Mode
Static
Total
Bit
16k-bit
64k-bit
682
Type No_
HM6116-2
r-HM6116-3
HM6116-4
HM6116L-2
HM6116L-3
HM6116L-4
HM6116A-12
HM6116A-15
HM6116A-20
HM6116AL-12
HM6116AL-15
HM6116AL-20
HM6117-3 HM6117-4
HM6117L-3
HM6117L-4
HM6168H-45
HM6168H-55
HM6168H-70
HM6168HL-45
HM6168HL-55
HM6168HL·70
HM6167
HM6167-6
HM6167-8
HM6167L
HM6167L-6
HM6167L-8
HM6167H-45
HM6167H-55
HM6167HL-45
HM6167HL-55
HM6267-35
HM6267-45
HM6264-10
HM6264-12
HM6264-15
HM6264L-10
HM6264L-12
HM6264L-15
Process
Organization
(word x bitl
2048 x 8
CMOS
4096 x 4
16384 x 1
8192 x 8
Access
Time
(ns) max
120
150
200
120
150
200
120
150
200
120
150
200
150
200
150
200
45
55
70
45
55
70
70
85
100
70
85
100
45
55
45
55
35
45
100
120
150
100
120
150
$
Cycle
Time
(ns) min
120
150
200
120
150
200
120
150
200
120
150
200
150
200
150
200
45
55
70
45
55
70
70
85
100
70
85
100
45
55
45
55
35
45
100
120
150
100
120
150
HITACHI
Supply
Voltage
(V)
Power
Dissipation
(W)
Package t
Pin No.
0.1m/O.2
0.1m/0.1B
20~MO.18
CG
G
• •
•
•• •
•
••
20~MO.16
0.1m/15m
24
5~/10m
0.1m/0.2
10~/0.18
+5
0.1m/0.25
20
••
•
P
FP
••
•
••
•
SP
••
•
•
•
•
• •
•
•
•
5~/0.25
5~/0.25
•
•
•
0.1m/0.15
5~/0.15
0.1m/0.2
20
• •
• •
5~/0.2
0.1m/0.25
0.1m/0.2
28
1O~/0.2
••
•
•
(Continued)
-------------------------------------------------------------IC
Total
Bit
Mode
Type No.
64k-bit
Dynamic
256k-bit
Process
HM48416A-12
HM48416A-15
HM48416A-20
HM4864-2
HM4864-3
HM4864A-12
HM4864A-15
HM4864A-20
HM50256-12
HM50256-15
HM50256-20
HM50257-12
HM50257-15
HM50257-20
Organization
(word x bit)
16384 x 4
65536 x 1
NMOS
262144 x 1
Access
Time
(ns) max
120
150
200
150
200
120
150
200
120
150
200
120
150
200
Cycle
Time
(ns) min
230
260
330
270
335
220
260
330
220
260
330
220
260
330
Supply
Voltage
(V)
Power
Dissipation
(W)
Pin No.
20m/0.3
18
Package t
CG
G
P
FP
SP
•
•
20m/0.33
+5
MEMORIES
20m/0.25
16
•• ••
• •
•
•
•
•
20m/0.35
•
•
20m/0.36
Do HM6116LP/LFP Series: 10 p.W
t The package codes of CG, G, P, FP and SP are applied to the package materials as follows.
CG: Glass-sealed Ceramic Leadless Chip Carrier, G: Cerdip, P: Plastic DIP, FP: Plastic Flat Package (SOP), SP: Skinny Type Plastic DIP
• MOS ROM
Mode
Total
Bit
64k-bit
Mask
128k-bit
256k-bit
1M-bit
32k-bit
U.V. Erasable
& Electrically
64k-bit
128k-bit
256k-bit
On Time
Electrically
Electrically
Erasable &
Programmable
64k-bit
128k-bit
64k-bit
Type No.
HN61364
HN61365
HN61366
HN613128
Process
8192 x 8
CMOS
HN61256
HN613256
HN62301 *
HN482732A-20
HN482732A-25
HN482732A-30
HN482764
HN482764-2
HN482764-3
HN27C64-15
HN27C64-20
HN27C64-25
HN27C64-30
HN4827128-25
HN4827128-30
HN482712845
HN27256-20
HN27256-25
HN27256-30
HN482764-3
HN4827128-30*
HN58064-25
HN58064-30
HN58064-45
Organization
(word x bit)
16384 x 8
32768x8 or
65536 x 4
32768 x 8
131072 x 8
Access
Time
(ns) max
250
250
250
250
Supply
Power
Voltage Dissipation
(V)
(W)
Pin No.
28
5p./50m
24
3500
5p./7.5m
250
350
200
250
300
250
200
300
150
200
250
300
250
300
450
200
250
300
300
5p./50m
2m/75m
4096 x 8
NMOS
8192 x 8
CMOS
16384 x 8
NMOS
32768 x 8
NMOS
NMOS
8192 x 8
16348 x 8
8192 x 8
300
250
300
450
* Preliminary
t The package codes of C, G, P and FP are applied to the package material as follows.
C: Side-brazed Ceramic DIP, G: Cerdip, P: Plastic DIP, FP: Plastic Flat Package
~HITACHI
+5
G
24
+5
0.55m/0.1
28
0.18/0.53
0.22/0.55
0.18/0.55
28
0.18/0.53
0.22/0.55
28
.p
FP
• •
•
•
• •
• •
• •
28
0.18/0.55
+5
C
5p./50m
0.18/0.8
+5
Package t
•
•
•
•
•
••
•
•
•
••
•
•
•
·
•
•••
•
•
683
Ie MEMORIES--------------------------------------------------------------•
BIPOLAR RAM
level
Total
Bit
256
1k
ECl
10k
4k
16k
1k
ECl
100k
4k
16k
Type No.
HM10414
HM10414-1
HM2110
HM2110-1
HM2112
HM2112-1
HM10422
HM10422-7
HM10470
HM10470-1
HM10470-25
HM2142
HM10474
HM10474-8*
HM10474-10*
HM10480
H M 10480-15 *
HM10480-20*
HM10484-15*
HM10484-20*
HM100415
HM100422
HM100470
HM100474
HM100480
HM100480-15*
HM100480-20*
H M 100484-15 *
H M 100484-20 *
Organization
(word x bit)
Output
Supply
Access
Time
Voltage
(V)
(ns) max
256 x 1
1024 x 1
256 x 4
4096 x 1
1024 x 4
-
16384 x 1
-~-
Open
Emitter
4096 x 4
i024 x 1
256 x 4
4096 x 1
1024 x 4
16384 x 1
4096 x 4
10
8
35
25
10
8
10
7
25
15
25
10
25
8
10
25
15
20
15
20
10
10
25
25
25
15
20
15
20
• Under development
t The package codes of F, G, P and CC are applied to the package materials as follows.
F: Flat Package, G: Cerdip, P: Plastic DIP, CC: Ceramic Leadless Chip Carrier.
684
~HITACHI
Power
Dissipation
!.mW/bit)
Package t
Pin No.
F
16
0.8
-5.2
0.8
1.0
24
0.2
18
0.3
0.2
20
0.3
24
0.05
0.06
-4.5
20
0.06
28
0.6
0.8
0.2
16
24
18
0.2
0.05
24
0.06
0.06
P
CC
•
2.8
0.5
G
20
28
••
•
•
•
•
•
•
•
••
•
•
•
••
•..
•
•
•
••
•
•
•
•
••
••
•
•
•
..•
/GATE ARRAY
CMOS Gate Array HD61J/HD61K/HD61L/HD61MM Series
•
•
FEATURES
Fast operation
Internal gate (2-input NAND, FO=3, Al=3mm) .. 3.5ns typ
Input buffer (FO=3, Al =.3mm) ............. 9ns typ
Output buffer (Cl =50pF). . . . . . . . . . . . . . . .. 20ns typ
Memory access time (HD61MM) ............... 60ns typ
• low power dissipation
At 10MHz operation (Internal gate) ...... 1301.tW/gate typ
• Abundant input and output configuration
Allocation of all pins except power supply pins to input/
output/input-output
Output can be CMOS/open drain/3-state
•
•
•
•
•
•
Memory on-chip (HD61MM)
Flexibility of memory capacity and word organization
Selection of single port/dual port memory
Wide operation temperature range
-20 to +75°C
Wide package selection
Especially plastic packages with high pin
count ....••.... DllP64/FPP100
Powerful design support
User-Defined-Macro
Test pattern evaluation with fault simulator
Design support at local Design Center
Quick turn around time and reasonable development cost
LINE UP
Gate count
I/O pin count
HD61K
1080
68
HD61l
1584
68
0
0
0
0
0
0
0
0
0
-
0
0
-
-
-
0*
0
0
0
0
0
0
0
0
0
-
-
0*
-
~Monchip
Package
HD61J
504
50
DP28
DP42
DP64
FP54
FP80
FP100
DC28
DC40
PGA72
PGA120
-
-
-
0
-
-
-
Power supply pin
4
-
HD61MM*
2496
104
available
-
-
-
-
4
8*
* Preliminary
Bi-CMOS Gate Array HD27K/HD27L/HD27P/HD27Q Series
•
•
•
FEATURES
High speed with super low power dissipation
• Internal gate: 4.0ns (Fan out=3)
@0.05mW
• Input buffer: 5.0ns (Fan out=3)
@2.6mW
• Output buffer: 8.0ns (Cl =15pF)
@2.6mW
lS TTL compatible input/output . . . . . . . . . . . . . . . . . . .
• Selectable totem-pole/3-state/open collector output
• IOl =8mA: Capable of driving 20 lS TTL's
$
•
Output buffer can construct logic functions.
• Saves gate stages.
• A variety of macrocelilibrary
• Internal gate: 44
• Output buffer: 9
• A variety of reliable package
• Plastic DIP 16 to 64 pins
• Plastic FP 60 to 100 pins (under development)
• A variety of DA 'system support
• Only logic diagrams and test patterns needed as an interface
with the user.
• Short development time
HITACHI
685
GATEARRAY-------------------------------------------------------------Number of gates
Number
of Vee
and GND
pins
Package
FP*
(Plastic)
I nternal gate
(2-input NAND)
Input
buffer
Output
buffer
HD27K
200
18
18
2
16,20,28,
42 pins
HD27L
528
30
30
4
28,42,64.
pins
60,80 pins
HD27P
966
40
40
4
28,42,64
pins
60,80,100
pins
HD27Q
1530
50
50
4
28,42,64
pins
60,80,100
pins
·Under development
686
~HITACHI
DIP
(Plastic)
-
LSI FOR SPEECH SYNTHESIZER SYSTEM
PMOS 3-chip System
• OUTLINE OF BASIC DEVICE
Type name
Function
HD38880B
Speech
synthesizer
HD38884P
Explanation of function
Outline
Synthesizes speech by reading out a prescribed c~aracteristic parameter
from the ROM chip according to the command from the microcomputer.
DC-28
DP-28
128k-bit
ROM
Analyzes the speech which should be synthesized in advance and stores the
extracted characteristic parameter.
DP-28
HD38882P
EPROM
interface
Capable of 1M-bit connection when using EPROM.
DP-42
HMCS40*
Series
Controller
Performs overall control to synthesize special speech under suitable
conditions.
*
*See 4-bit microcomputer item.
•
System Features
•
High speech quality
Since a PARCOR system is employed and the bit rate can be
taken up to 2400-9600 bits/sec, excellent tone quality is
made possible.
Synthesizing woman's voice
In addition to a man's voice, synthesizing woman's voice is
possible with the adoption of the vocal tract loss effect.
Variation of speaking speed
Speech can be spoken slowly or rapidly by microcomputer
control.
Vocalization with accurate scale
By producing voice pitch through external synchronization,
accurately scaled singing is possible.
•
•
•
•
•
Long-period voice capacity
A maximum of 16 ROMs can be connected without an interface Circuit. Vocal sound of 50"'100 seconds (2400 bit/sec)
can be synthesized with 1 ROM.
Speaker direct drive
The speaker is directly driven by the built-in 0/ A converter and
speaker driving circuit. Excellent tone quality and power is
possible by providing an external Of A converter and speaker
driving circuit utilizing the digital output.
• BASIC SYSTEM COMPOSITION EXAMPLES
• Case of using mask ROM
• Case of using EPROM
Ceramic
OsCillator
Ceramic
OSCillator
Analog Output
\
r====::::{11 )i)
HMCS40 Serie.
HMCS40
Seriel
(Controller)
(Controller)
H038884
(128k bit ROM)
x 16rnax
HN482764
x 16 max
AMP
I'
eHITACHI
687
LSI FOR SPEECH SYNTHESIZER S Y S T E M - - - - - - - - - - - - - - - - - - - - • SYSTEM SPECIFICATIONS
Item
Content
System
PARCOR system
Voice channel model
8th stage/10th stage digital filter . . . . . . . . . . . . • . . . . . . . . . . • . . . . .• Selectable
Vocal tract loss effect (existence/non-existence) .......•.......... Selectable
Voice source model
Voice sound ...... Rectangular wave/triangle wave
Voiceless sound ... White noise
Sampling frequency
.............
Selectable
8 kHz
Bit rate (b/s)
Frame period (ms)
2400
4800
9600
20
10/20
10
Variable speaking speed
Variation of frame period is possible from -30% to +600~ by 1OO~ steps.
Pitch
I ntegral times of 125 #Is/External synchronization " ........•.. . .. Selectable
Speaking time
50-100 sec/ROM (2400 b/s)
CMOS 1-chip System
• OUTLINE OF BASIC DEVICE
Type No.
Function
H06t885
Speech
H061887
Synthesizer
(H044881)
128k-bit ROM
Explanation of function
Synthesizes speech by reading out a prescribed characteristic parameter from the internal or external ROM according to the command
from the microcomputer or key switch.
(Expanding ROM)
Performs overall control to synthesize special speech under suitable
conditions.
Outline
OP-28
FP-54
OP-28
• SYSTEM FEATURES
•
•
1-chip system
Including synthesizer, 32k-bit ROM and interface circuit.
High speech quality
Since a PARCOR system is employed and the bit rate can be
taken to 1250-9900 bit/sec, excellent tone quality is possible.
•
•
Long-period voice capacity
A maximum 16 ROMs can be connected without an interface
circuit. Vocal sound of 50-100 seconds can be synthesized
with 1 ROM.
Low power dissipation (Standby mode)
• SYSTEM SPECIFICATIONS
Item
System
Voice channel model
Sampling frequency
Bit rate (b/s)
Frame period (ms)
Variable speaking speed
Speaking time
Supply Voltage
688
Content
PARCOR system
10th stage digital filter
10 kHz
1,250 - 9,900
10/20
-25%, 0, +25%
10 - 20 sec (internal ROM)
5V single (3.6 - 5.5V operation)
$
HITACHI
- - - - - - - - - - - - - - - - - - - - - L S I FOR SPEECH SYNTHESIZER SYSTEM
• BASIC SYSTEM COMPOSITION EXAMPLES
e Key Input
eCode Input
Ceramic
Oscillator
Filter Amp
r--
I
---
I
,
'
I
'
I
I
,
I
,
HD44881
:
I
I
I
I
I
I
I
I
I
I
I
I
I
__________________ JI
--,
I
I
I
I
,
:
{128k-blt ROM • 16m•• 1
,
IL
I
I
,
I
I
I
r-- -- -
---,
I
HD44881
I
I
I
I
I
~-----------------~
e Microcomputer Control
Vee
HMCS40 Serl ••
Filter Amp.
(Controller,
r---
I
I
:
I
I
I
~
-- -
I
I
:
I
I
:
:
HD44881
:
I
I
I
I
I
I
I
I
L
I _____________________ JI
Cf)HITACHI
689
I CODEC/F I LTER COM.BO LSI
•
LINE UP
Clock
Series
HD44210
HD44220
HD44230
HD44230C
HD44240C
Type No.
Compo
Law
HD44211A
A
HD44212A
II
HD44222
II
HD44231B
A
HD44232B
II
HD44233B
A
HD44234B
II
HD44235
A
HD44236
II
HD44237
A
HD44238
II
HD44231C
A
HD44232C
II
HD44233C
A
HD44234C
II
HD44235C
A
HD44236C
II
HD44237C
A
HD44238C
II
HD44240C
II
Power
Dissipation
(mW)
CR
Filter
Voltage
Reference
150
-
-
40
-
External
Internal
Clock
Package
64 - 2048kHz
-
DC·24
64 - 2048kHz
Decoder Shift
DC-16
1536/1544/2048kHz
-
PCM Bit
Clock Required
Both
Both
External
128 kHz req.
PLL
Sync.
60
a
a
Divider
Both
-
Sync.
50
a
a
PLL
-
64 - 2048kHz
Both
Decoder Shift
Decoder Shift
DG-16
Sync.
Divider
-
1536/1544/2048kHz
-
Both
60
a
a
-
Sync.
PLL
60
a
a
-
PLL
A-law; Europe & International Telephone.
IJ-Iaw ; U.S.A., Canada & Japan
690
Signaling
Sync.!
Async.
$
HITACHI
64 - 2048kHz
Both
Both
Decoder Shift
Decoder Shift
64 - 2048kHz
A/B Data I/O
DG-20
HITACHI AMERICA, LTO.
SEMICONDUCTOR AND IC SALES & SERVICE DIVISION
HEADQUARTERS
Hitachi, Ltd.
Nippon Bldg., 6-2, 2-chome
Ohtemachi, Chiyoda-ku, Tokyo, 100, Japan
Tel: 212-1111
Telex: J22395, J22432
REGIONAL OFFICES
NORTHEAST REGION
Hitachi America, Ltd.
5 Burlington Woods Dr.
Burlington, MA 01803
617/229-2150
SOUTHERN REGION
Hitachi America, Ltd.
Two Lincoln Centre, Suite 865
5420 LBJ Freeway
Dallas, TX 75240
214/991-4510
NORTH CENTRAL REGION
Hitachi America, Ltd.
500 Park Blvd., Suite 415
Itasca, I L 60143
3121773-4864
NORTHWEST REGION
Hitachi America, Ltd.
2099 Gateway Place, Suite 550
San Jose, CA 95110
408/277-0712
SOUTHWEST REGION
Hitachi America, Ltd.
Warner Center Plaza One
21600 Oxnard St., Suite 600
Woodland Hills, CA 91367
8181704-6500
692
U.S. SALES OFFICE
Hitachi America, Ltd.
Semiconductor and IC Sales &Service Division
1800 Bering Drive
San Jose, CA 95112
Tel: 408/292-6404
Telex: 17-1581
Twx: 910-338-2103
Fax: 408-2922133
Fax: 408-2949618
DISTRICT OFFICES
•
Hitachi America, Ltd.
1700 Galloping Hill Rd.
Kenilworth, NJ 07033
201/245-6400
•
Hitachi America, Ltd.
3500 W. 80th Street, Suite 175
Bloomington, MN 55431
612/831-0408
•
Hitachi America, Ltd.
80 Washington St., Suite 101
Poughkeepsie, NY 12601
914/485-3400
•
Hitachi America, Ltd.
1 Parkland Blvd., #1222E
Dearborn, MI 48126
313/271-4410
•
Hitachi America, Ltd.
6200 Savoy Dr., Suite 850
Houston, TX 77036
713/974-0534
•
Hitachi America, Ltd.
5775 Peachtree Dunwoody Rd.
Suite 270-C
Atlanta, GA 30342
404/843-3445
•
Hitachi America, Ltd.
4901 N.W. 17th Way
Fort Lauderdale, FL 33309
305/491-6154
•
Hitachi America, Ltd.
18004 Skypark Circle, Suite 200
Irvine, CA 92714
714/261-9034
@HITACHI
Hitachi America, Ltd
Sernlcoriductor and IC Soles and Service Divlslori
1800 Bering Drive, Son Jose, CA 95112
1408-292 -6404
t'lll l •
j II,
,J'; !\
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