UM 00070 F_DT3362_QBus_High_Performance_A D_Subsystem_Jul86 F DT3362 QBus High Performance A D Subsystem Jul86
UM-00070-F_DT3362_QBus_High_Performance_A-D_Subsystem_Jul86 UM-00070-F_DT3362_QBus_High_Performance_A-D_Subsystem_Jul86
User Manual: UM-00070-F_DT3362_QBus_High_Performance_A-D_Subsystem_Jul86
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Document UM-00070-F
User Manual
for
DT3362
SERIES
HIGH PERFORMANCE
AID SUBSYSTEMS
For Q-bus Processors
Copyright@ 1986 by Data Translation, Inc.
Data Translation, Inc.
100 Locke Drive
Marlborough, MA 01752-1192
All rights reserved.
No part of this publication may be
reproduced, stored in a retrieval system, or transmitted, in
any form by any means, electronic, mechanical, by photocopying,
recording, or otherwise, without the prior written permission
of Data Translation, Inc.
Fourth Edition
July, 1986
July, 1986 printing
Information furnished by Data Translation, Inc. is believed to
be accurate and reliable; however, no responsibility is assumed
by Data Translation;
Inc.
for its use;
nor
for
any
infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication
or otherwise under any patent rights of Data Translation, Inc.
Data Translation is a registered trademark of Data Translation,
Inc.
DT3362 series is a trademark of Data Translation, Inc.
Q-bus is a trademark of Digital Equipment Corporation.
CONTENTS
PREFACE
CHAPTER 1
1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
CHAPTER 2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.S
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.1S
2.19
CHAPTER 3
INTRODUCTION
MODEL DESCRIPTIONS . . . . . . • .
COMPATIBLE SCREW TERMINAL PANELS .
"",rn,,,,
1.1.1- I V..L
"''F.'i~
.
c.,
.. P.t,..
.,Cl\J.
DT6700 SERIES
DT709 SERIES .
DT756 SERIES ..
.
.
·
·
·
.
·
·
1-2
1-6
1-6
1-6
1-6
1-7
·
·
·
.
2-1
2-2
2-5
2-8
2-11
2-14
2-17
2-20
2-23
2-25
2-28
2- 31
2-33
2-36
2-36
2-37
2-37
2-37
SPECIFICATIONS
INTRODUCTION . . . . . . . . . . . . . . . .
DT3362-16SE/SDI AND DT3362-64SE/32DI . . . .
DT3362-16SE/SDI-PGH AND DT3362-64SE/32DI-PGH
DT3362-F-16SE AND DT3362-F-64SE
DT3362-F-SDI AND DT3362-F-32DI .
....
DT3362-G-16SE AND DT3362-G-64SE
. . . . .
DT3362-G-8DI AND DT3362-G-32DI . . . . . .
DT3362-H-16SE AND DT3362-H-64SE
. . . . .
DT3362-H-SDI AND DT3362-H-32DI . . . .
DT3362-H-16SE-PGH AND DT3362-H-64SE-PGH
. . .
DT3362-H-SDI-PGH AND DT3362-H-32DI-PGH
DT 3377 . . . . . . . . . . .
. . .
DT3368-4SE AND DT3368-12SE .
EXTERNAL TRIGGER . . . . .
INTERFACE CHARACTERISTICS
POWER REQUIREMENTS . . . . . .
PHYSICAL/ENVIRONMENTAL . . .
CONNECTORS AND CABLES
. . . .
COMPATIBLE SCREW TERMINAL PANELS
.
.
.
UNPACKING AND CONFIGURATION
3.1
3.2
3.2.1
3.2.2
3.3
3.3.1
3.3.2
3.4
3.4.1
3.4.2
3.4.3
3.4.3.1
3.4.4
INTRODUCTION . . . . .
UNPACKING . . . . .
NO APPARENT DAMAGE .
VISIBLE DAMAGE
CONFIGURATION
DEVICE BASE ADDRESS SELECTION . . . . . .
DEVICE INTERRUPT VECTOR ADDRESS SELECTION
A/D CONFIGURATION JUMPERING
. . . . .
INPUT MODE
.........
.... .
A/D INPUT RANGE
. . . . . .
SELECTION OF OUTPUT CODING .
. . . . . .
Input Gain And A/D Range .
..... .
JUMPER CONFIGURATIONS ON 22-BIT DMA ADDRESS
BOARD
. . . . . . . . . . . . . . . . .
Selection Of DMA Wrap Mode . . . . . . . . . .
3.4.4.1
iii
·
·
·
·
·
·
·
·
3-1
3-1
3-1
3-2
3-3
3-3
3-4
3-5
3-5
· 3-7
3-10
3-12
3-13
3-13
3.4.4.2
3.4.4.3
CHAPTER 4
4.1
4.2
4.2.1
4.2.2
4.2.3
4.3
4.4
4.5
4.6
4.6.1
4.6.2
4.6.3
4.7
4.7.1
4.7.2
4.7.3
CHAPTER 5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.3
5.4
5.5
5.5.1
5.5.2
5.6
5.6.1
5.6.2
CHAPTER 6
6.1
6.2
6.3
6.4
CHAPTER 7
7.1
7.2
Triggers . . . . . . . . . . .
Reference Jumpers . . . .
3-14
3-15
SYSTEM INTERCONNECTIONS
INTRODUCTION . . . . . . . . . . . . . . . . . . . 4-1
ANALOG INPUT CONNECTIONS . . . . . . . . • . • . . 4-1
J3 AND J2 CONNECTIONS ON DT3362- PREFIXED MODELS 4-1
J3 CONNECTION ON DT3377 . . . . . . . . . . . . 4-3
J3 AND J2 CONNECTIONS ON DT3368- PREFIXED MODELS 4-4
EXTERNAL PORT CONNECTION • . . . . . . . . . .
4-5
EXTERNAL TRIGGER INPUT . . • . . . . • . . . .
4-6
CONNECTIONS TO DATA ACQUISITION ACCESSORIES
. 4-6
RECOMMENDED ANALOG INPUT CONNECTION SCHEMES
. . . 4-9
SINGLE-ENDED INPUTS
. . . . .
. • •.
4-11
PSEUDO-DIFFERENTIAL INPUTS . .
4-13
DIFFERENTIAL INPUTS
4-15
CONNECTION GUIDELINES
. . . .
4-17
TWISTED PAIR INPUT LINES . .
. . . .
4-17
SHIELDED INPUT LINES. . .
. . . .
4-17
INPUT SETTLING WITH HIGH SOURCE IMPEDANCE
4-17
ARCHITECTURE
INTRODUCTION . . . . . . . . . . . . .
REGISTERS . • . . . . . . . . . • . .
AID CONTROL AND STATUS REGISTER
AID DATA BUFFER REGISTER
.....
CHANNEL-LIST PROGRAMMING REGISTER
DMA CONTROL AND STATUS REGISTER
DMA WORD COUNT REGISTER
DMA CURRENT ADDRESS REGISTER
MULTIPLEXER CHANNEL-LIST .
ADDRESS POINTERS . . . . . . . . . . .
EXTERNAL PORT . . . . . . .
DT3369 DUAL-PORT MEMORY
SKY 320 SIGNAL PROCESSOR
DMA TRANSFERS . . . . • .
DMA TRANSFERS VIA Q-BUS
. . . . .
DMA TRANSFERS VIA EXTERNAL PORT
·
. .
·
. .
. .
.
.
.
· .
.
. . 5-1
. . 5-1
5-3
. . . 5-6
5-6
· . . 5-8
5-11
..
5-11
5-11
..
5-12
5-13
. .
5-14
5-15
5-15
5-15
5-16
.
OPERATING PRINCIPLES
INTRODUCTION . . . . . . . . . .
AID CONVERSION TRIGGER .
....
DATA TRANSFER
DATA CONVERSION
.
.
.
· . .
· . .
6-1
6-1
6-2
6-3
CHANNEL-LIST PROGRAMMING
INTRODUCTION . . . . . .
PROGRAMMING PROTOCOLS
iv
· .
. 7-1
. 7-2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
.,
I
')
t:.
INITIALIZE POINTER LOGIC . . . . • .
WRITE START ADDRESS REGISTER/CURRENT ADDRESS
POINTER . . . . . . . . . . . . . .
READ CURRENT ADDRESS POINTER . ~ •
WRITING FINAL ADDRESS POINTER
. . .
READING THE FINAL ADDRESS POINTER
· . . .
.~.\J
7.3
7.3.1
7.3.2
7.3.3
CHAPTER 8
8.1
8.2
8.3
8.4
8.5
8.6
CHAPTER 9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.3
9.3.1
9.3.1.1
9.3.1.2
9.3.1.3
9.3.2
9.3.2.1
9.3.2.2
9.3.2.3
9.4
9.5
9.5.1
9.5.2
9.5.3
APPENDIX A
A.1
APPENDIX B
B.1
ENTERING CHANNEL INFORMATION INTO THE RAM
WRITING INTO THE CHANNEL-LIST RAM
.
READING THE CHANNEL-LIST FAM • • • • •
MULTIPLEXER PRELOAD AND LOGIC ENABLE . .
. .
• .
.
.
.
· 7-2
· 7-3
7-3
. 7-4
. 7-4
· 7-5
. 7-5
. 7-6
7=7
· 7-8
PROGRAMMING EXAMPLES
INTRODUCTION . .
FADEX1 - EXAMPLE
FADEX2
EXAMPLE
FADEX3
EXAMPLE
EXAMPLE
FADEX4
FADEX5
EXAMPLE
PROGRAM
PROGRAM
PROGRAM
PROGRAM
PROGRAM
1
2
3
4
5
·
.
.
.
·
·
.
·
.
.
.
.
.
.
.
.
.
·
·
·
.
.
8-1
8-1
8-1
8-2
8-2
8-3
.
.
.
.
·
·
.
•
.
.
•
.
9-1
9- 2
9-2
9-3
9-3
9-3
9-4
9- 5
9-8
9-8
9-9
9-9
9-10
9-10
9-11
9-11
9-12
9-13
9-13
9-14
9-14
AID CALIBRATION
INTRODUCTION . . . . . . . . .
GUIDELINES . . .
PREREQUISITES
EQUIPMENT REQUIRED .
PRECAUTIONS
SINGLE-ENDED INPUT OPERATION
DIFFERENTIAL INPUT OPERATION
CALIBRATION . . . . . . . . .
UNIPOLAR RANGE CALIBRATION .
.
.
(SE)
(DI)
. . .
Unipolar Zero . . . . . . . .
. .
Unipolar Full Scale
PG Zero . . . . . . . . .
BIPOLAR RANGE CALIBRATION
0
· . . .
. . . . .
. ..
·
• . . . . .
. . .
.
.
0
•
0
.
.
.
.
.
.
.
.
.
Minus Full Scale . .
Plus Full Scale . . . .
PG Zero
0
0"
0
0
•
APPLICATIONS
GROUNDING
DIFFERENTIAL INPUTS
SINGLE-ENDED INPUTS
. . . .
PSEUDO-DIFFERENTIAL INPUTS .
0
DT3362 SERIES JUMPER SUMMARY
INTRODUCTION .
.
0
•
o
0
0
0
0
•
0
•
0
•
• • • • •
0
0
0
••
0
0
0
0
••
•
A-I
DATA CODING TABLES
INTRODUCTION
0
0
0
v
B-1
APPENDIX C
TROUBLESHOOTING
TROUBLESHOOTING . . . . . . • •
C.l
SYMPTOMS AND SOLUTIONS . . . .
C.l.l
No Board Response
C.l.l.l
Digital Output Code In Plus Or Minus Full Scale
C.l.l.2
Stops
. . . . ..
.•.•
.
C.l.l.3
First Reading On A Channel Is Incorrect
.
C.l.l.4
Zero Or Full Scale Will Not Calibrate . . • . .
C.2
RMA NUMBER . • • . .
......
.
APPENDIX D
LISTING OF DT3362 SERIES DIAGNOSTICS
APPENDIX E
ENGINEERING DRAWING
INDEX
vi
C-l
C-2
C-2
C-2
C-2
C-2
C-2
FIGURES
3-1
3-2
BASE ADDRESS SELECTION OF 771300 (OCTAL) • . . . . . . 3-4
VECTOR ADDRESS SELECTION . . . . . . . . . . . . . . 3-5
4-1
CONNECTION OF DT701-20 AND DT701-50 TO THE DT3362
11 _ ..,
SERI ES BOARDS
. .. " " " " " .. " . . . . .
. . . . · ,,-,
CONNECTION OF DT709 SERIES AND DT6700 SERIES TO SE
VERSIONS OF THE DT3362 SERIES BOARDS
. . . . . . . · 4-8
CONNECTION OF DT756 SERIES WITH SE VERSIONS OF THE
DT3362 SERIES EXCEPT DT3368-4SE AND DT3368-12SE
· 4-8
CONNECTION OF SCREW TERMINAL PANELS TO THE A/D
EXPANDER OF THE DT3362 SERIES . . . . . . . . .
· 4-9
SINGLE-ENDED INPUT CONNECTION . . . .
4-12
PSEUDO-DIFFERENTIAL INPUT CONNECTION
4-14
DIFFERENTIAL INPUT CONNECTION .
4-16
4-2
4-3
4-4
4-5
4-6
4-7
5-1
5-2
5-3
5-4
5-5
9-1
9-2
9-3
B-1
B-2
ADSCR BIT ASSIGNMENTS . . . . . .
.
CLPR BIT ASSIGNMENTS
. . . . .
DMACSR BIT ASSIGNMENTS
. . . . .
DATA PATH TAKEN BY CONVENTIONAL DMA TRANSFERS . . .
DATA PATH TAKEN WITH DUAL-PORTED MEMORY STRUCTURE .
. 5-3
· 5-7
· 5-8
5-13
5-14
SINGLE-ENDED CONNECTIONS (EXCEPT DT3368-4SE AND
DT3368-12SE). . . . . . . . . . . . . . . . . . .
9-3
SINGLE-ENDED CONNECTIONS (DT3368-4SE AND DT3368-12SE) 9-4
DIFFERENTIAL CONNECTIONS
. . . . . . . . ..
9-5
CALCULATING THE INPUT VOLTAGE TO AN A/D CONVERTER
USING BINARY OR OFFSET BINARY CODING
. . • . . . .
CALCULATING THE INPUT VOLTAGE TO AN A/D CONVERTER
USING TWO'S COMPLEMENT CODING
vii
. B-2
· B-2
TABLES
1-1
DT3362 SERIES FEATURES COMPARISON .
.
.
• 1-3
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
DT3362 SERIES INPUT MODES
· . .
INPUT MODE SELECTION
· . .
DT3362 SERIES INPUT RANGES
· .
INPUT RANGE SELECTION . . .
....
· .
DT3362 SERIES OUTPUT CODES
. . • •
SELECTION OF DATA CODING
. . . • •
FULL SCALE OUTPUT CODES IN VARIOUS NOTATIONS
FULL SCALE RANGES FOR HIGH LEVEL INPUT BOARDS .
DMA WRAP MODE SELECTION
. • . • • . . . .
SELECTION OF DMA ADDRESSING ~
REFERENCE JUMPERS FOR REVISION F AND LATER BOARDS
. . . . • . . .
REFERENCE JUMPERS FOR ALL MODELS
.
.
.
.
.
.
.
•
4-1
4-2
4-3
4-4
4-5
4-6
4-7
J3 PIN ASSIGNMENTS ON ALL DT3362- PREFIXED MODELS • . 4-2
J2 EXPANDER PIN ASSIGNMENTS ON DT3362- PREFIXED
MODELS . . . . . . . . . . . . . . . . . . . . .
4-3
4-4
J3 PI ASSIGNMENTS ON DT3377
... . . . . . • .
J3 PIN ASSIGNMENTS ON DT3368-4SE AND DT3368-14SE . .
4-4
J2 EXPANDER PIN ASSIGNMENTS ON DT3368-12SE
4-5
EXTERNAL PORT CONNECTOR J1 PIN ASSIGNMENTS
4-6
DT3362 SERIES INPUT TYPES
. . . . . .
4-10
5-1
5-2
5-3
5-4
5-5
5-6
DT3362 SERIES REGISTER ASSIGNMENTS
CHANNEL-LIST CONTROL INSTRUCTION FIELD
CHANNEL-LIST OPERATION MODE FIELD .
CHANNEL-LIST PAGE SELECT . . . . . . .
MODE SELECTION USING CLPR .
DMA MODE SELECTION . . . . . . . .
e
e
e
e
e
e
e
.
.
•
e
.
.
.
·
.
.
.
.
.
.
.
.
·
.
.
.
.
.
.
.
.
.
3-6
3-7
3-8
3-9
3-11
3-12
3-13
3-13
3-14
3-14
3-15
3-16
5-2
5-4
5-4
5-6
5-7
5-11
9-1
9-2
9-3
DT3362 SERIES A/D CONVERTER MODULES
....
. 9-2
1 LSB VOLTAGE LEVELS
. . . .
. . . . 9-6
12-BIT OFFSET BINARY AND TWO'S COMPLEMENT BINARY
CODE FOR MINUS FULL SCALE PLUS 1 LSB
. . ..
. • 9-6
9-4 16-BIT TWO'S COMPLEMENT BINARY CODE FOR MINUS FULL
SCALE PLUS 1 LSB
. . . . . . . .
. . . . 9-7
9-5 PLUS FULL SCALE MINUS 2 LSB . . . . . .
• 9-7
9-6 12-BIT BINARY CODES FOR PLUS FULL SCALE MINUS 2 LSB . 9-7
9-7 16-BIT TWO'S COMPLEMENT BINARY CODES FOR PLUS FULL
• • 9-8
SCALE MINUS 2 LSB . . . . . . . . . . . .
9-8 MINUS FULL SCALE PLUS ONE LSB VOLTAGE . • . .
9-10
9-9 12-BIT OFFSET BINARY AND TWO'S COMPLEMENT BINARY
CODES FOR MINUS FULL SCALE PLUS 1 LSB . . . . . . .
9-11
9-10 16-BIT TWO'S COMPLEMENT CODES FOR MINUS FULL SCALE
PLUS 1 LSB . . . . . . . . . . • . . . . . . . . • 9-11
9-11 12-BIT OFFSET BINARY AND TWO'S COMPLEMENT BINARY
OUTPUT CODES FOR 0 VOLTS
• . • • . . . .
9-12
9-12 TYPICAL COUNT SPREAD DUE TO NOISE . . . .
9-12
A-1
DT3362-16SE/8DI AND DT3362-64SE/32DI JUMPERS
A-2
DT3362-16SE/8DI-PGH AND DT3362-64SE/32DI-PGH JUMPERS
viii
. A-2
A-3
A-3
DT3362-F-16SE AND DT3362-F-64SE JUMPERS
A-4
DT3362-F-16DI AND DT3362-F-32DI JUMPERS
A-5
DT3362-G-16SE AND DT3362-G-64SE JUMPERS
A-6
A-6
DT3362-G-16DI AND DT3362-G-32DI JUMPERS
· A-7
A-7
DT3362-H-16SE AND DT3362-H-64SE JUMPERS
A-8
DT3362-H-16DI AND DT3362-H-32DI JUMPERS
A-9
DT3362-H-16SE-PGH AND DT3362-H-64SE-PGH JUMPERS
A-10
A-10 DT3362-H-16DI-PGH AND DT3362-H-32DI-PGH JUMPERS
A-11
A-11 DT3377 JUMPERS
A-12
A-12 DT3368-4SE AND DT3368-12SE JUMPERS .
B-1
B-2
B-3
.
· A-4
.
A-5
.
.
. .
. A-8
· A-9
. ..
A-13
12-BIT AID BIPOLAR CODING TABLE
(ALL MODELS EXCEPT DT3368-4SE AND DT3368-12SE) . . . . B-3
12-BIT AjD UNIPOLAR TABLE
(ALL MODELS EXCEPT DT3377)
.....
. B-3
16-BIT AjD BIPOLAR CODING (DT3377)
. . B-4
ix
PREFACE
This hardware manual is written for users of the
Data
Translation DT3362 series data acquisition and conversion
subsystems compatible with Digital Equipment Corporation's
Q-bus-based computer systems.
It describes the configuration
of the board,
shows
system
interconnections,
discusses
the
board architecture, and provides you with information on how to
program and operate the DT3362 series. The manual assumes that
you have a general knowledge of electronic circuitry, are
familiar with the Q-bus, understand data conversion,
and
possess enough proficiency in software to write your own
application and diagnostic programs.
The following
list
provides summaries of all sections in the manual.
CHAPTER 1 - INTRODUCTION
Chapter 1 provides an overview of all the models comprising the
DT3362
series.
The chapter brle!lY describes the major
features of each model and gives a summary of compatible data
acquisition accessories.
CHAPTER 2 - SPECIFICATIONS
Chapter 2 gives the
complete
electrical
and
physical
specifications for all boards in the series. The chapter also
lists compatible data acquisition accessories, connectors,
and
cable assemblies used to interface the DT3362 series board with
signal sources.
CHAPTER 3 - UNPACKING AND CONFIGURATION
Chapter 3 describes the unpacking procedure and lists measures
to take if product is damaged.
The major portion of the
chapter discusses
the
configuration
of
user-selectable
parameters.
CHAPTER 4 - INTERCONNECTION
Chapter 4 discusses connections to the Q-bus and the user
application.
The chapter gives the bit assignments of all
connectors and discusses input connection schemes.
It also
provides diagrams showing the connections of the DT3362 series
boards to compatible screw terminal/signal conditioning panels.
x
CHAPTER 5 - ARCHITECTURE
Chapter 5 describes the board registers and the function of
each bit in each register.
The chapter also discusses the
multiplexer channel-list, the external port, and DMA transfers.
CHAPTER 6 - OPERATING PRINCIPLES
Chapter 6 describes the various stages in the operation of the
board--A/D
conversion
trigger,
data transfer, and data
conversion.
CHAPTER 7 - CHANNEL-LIST PROGRAMMING
Chapter 7 explains the use of the multiplexer channel-list
feature and presents the various protocols and sequences needed
to program the multiplexer channel-list and the pointer logic.
The chapter also describes how to enter channel information
into the RAM.
CHAPTER 8 - PROGRAMMING EXAMPLES
Chapter 8 presents five examples which describe and illustrate
various programming aspects of the DT3362 series boards both
for non-DMA applications as well as for DMA operations.
CHAPTER 9 - CALIBRATION
Chapter 9 describes calibration procedures
converters on the DT3362 series boards.
for
the
A/D
APPENDIX A - DT3362 SERIES JUMPER SUMMARY
lists
Appendix A provides the jumper
DT3362 series boards.
of
all
models
in
the
APPENDIX B - DATA CODING TABLES
Appendix B provides unipolar and bipolar data coding tables for
for key points in the input ranges of all models in the DT3362
series boards.
APPENDIX C - TROUBLESHOOTING
Appendix C lists the steps to be taken in troubleshooting
DT3362 series board and in seeking factory service.
xi
the
APPENDIX D - LISTING OF DT3362 SERIES DIAGNOSTICS
Appendix D contains the listing of the diagnostics.
APPENDIX E - ENGINEERING DRAWING
Appendix E contains the board assembly drawing
series.
xii
of
the
DT3362
CHAPTER 1
INTRODUCTION
The DT3362 series of analog to digital (A/D) converter boards
are fast, Q-bus compatible data acquisition subsystems intended
for use in a wide range of applications in industrial process
control as well as laboratory research. The series offers such
advanced features as 22-bit addressing, data transfers via DMA,
and an external port to enhance throughput.
The series includes basic boards and expanded boards.
The
maximum number of input channels on the basic boards is 16
single-ended or 8 differential.
Expanded boards are basic
boards equipped with expander modules to provide additional
input channels. Up to 64 single-ended or 32 differential input
channels can be accommodated on expanded boards. The series
uses 12-bit, as well as 16-bit A/D converters, and features
boards with simultaneous sample and hold circuits.
The DT3362 series boards are designed for both unipolar and
bipolar inputs.
The unipolar input r~nge is 0 to +10V for
models not equipped with programmable galn (PGH) and 0 to
+1.2SV to 0 to +10V for models with programmable gain. The
corresponding bipolar ranges are ±10V and ±1.2SV to ±10V,
respectively.
The programmable gain is software selectable.
The high resolution (16-bit) model in the series operates only
in a bipolar input range.
Input modes on the DT3362 series boards can be single-ended or
differential.
Four models offer selectable input modes:
DT3362-16SE/8DI, DT3362-64SE/32DI, DT3362-16SE/8DI-PGH,
and
DT3362-64SE/32DI-PGH.
The other models are configured for
either differential or single-ended inputs.
A conversion trigger initiates a single conversion, a scan of
conversions in a channel-list, or a specified number of
conversions, all under software control.
Conversion triggers
are issued either via software or by an external pulse.
The sophisticated architecture of the DT3362 series permits
data transfers to memory over a dedicated bus which is
completely independent of the system Q-bus.
This feature is
used in combination with the DT3369 dual port memory board to
further enhance subsystem throughput without adding to the
latency of the Q-bus, thus freeing the system bus to service
1-1
INTRODUCTION
other peripherals.
The DT3362 series boards require no external power to operate.
On-board dc to dc converters generate +ISV and -ISV power
required by the A/D converter modules. The dc to dc converters
and logic circuits obtain power directly from the +SV supply
line on the Q-bus backplane.
The DT3362 series board occupies 16 consecutive byte locations
in the Q-bus I/O address space.
The base address can be
assigned any value within the 760000-777760 (octal) range in
increments of 20 (octal).
1.1
MODEL DESCRIPTIONS
The DT3362 series consists of 23 models: 12 basic models and
11 expanded.
Table 1-1 lists all the models and provides a
summary of their performance characteristics.
1-2
INTRODUCTI01
MODEL DESCRIPTIONS
TABLE 1-1: DT3362 SERIES FEATURES COMPARISON
CONV. RESOLURATE(l) TION
MODEL
DT3362-16SE/8DI
DT3362-32DI/64SE
1- - - r
(1)
•
•
50kHz
I 50kHz
I
I
IDT3362-16SE/8DI-PGH
DT3362-64SE/32DI-PGH ( 2 ) !
DT3362-F-16SE
DT3362-F-64SE ( 2 )
DT3362-F-8DI
DT3362-F-32DI ( 2 )
I
ANALOG
INPUTS
12 bits 16SE/8DI
12 bits 64SE/32DI
SOFTWARE
GAIN
N/A
N/A
I
50kHz 112 bits 16SE/8DI 11,2,4,8
50kHz 12 bits 64SE/32DI 1,2,4,8
I
DT3362-G-16SE
DT3362-G-64SE ( 2 )
DT3362-G-8DI
DT3362-G-32DI ( 2 )
IDT3362-H-16SE
IDT3362-H-64SE ( 2 )
DT3362-H-8DI
DT3362-H-32DI ( 2 )
DT3362-H-16SE-PGH
IDT3362-H-64SE-PGH ( 2 )
DT3362-H-8DI-PGH
IDT3362-H-32DI-PGH ( 2 )
I
I
125kHz
125kHz
125kHz
125kHz
12
12
12
12
bits
bits
bits
bits
16SE
64SE
801
3201
1,2,4,8
1,2,4,8
1,2,4,8
1,2,4,8
250kHz
250kHz
250kHz
250kHz
12
12
12
12
bits
bits
bits
bits
16SE
64SE
801
3201
1,2,4,8
1,2,4,8
1,2,4,8
1,2,4,8
250kHZl12
250kHZ!12
250kHz 12
250kHz 12
bits
bitS!
bits
bits
16SE
64SE
8DI
32DI
N/A
N/A
N/A
N/A
200kHz
200kHz
200kHz
200kHz
bits
bits
bits
bits
16SE
64SE
801
3201
1,2,4,8
1,2,4,8
1,2,4,8
1,2,4,8
12
12
12
12
DT3377
100kHz 16 bits
4D1
N/A
DT3368-4SE ( 3 )
DT3368-12SE ( 2 , 3 )
100kHz 12 bits
100kHz 12 bits
4SE
12SE
N/A
N/A
I
I
NOTES:
1.
2.
3.
"Conversion Rate" is the
maximum
number
of
A/D
conversions per second of which the board is capable as
shipped from the factory.
This does not take into
account software latencies and the time required to read
data from the board.
Uses an expander module.
Uses a simultaneous sample and hold module.
A brief description of all the
follows.
models
in
the
DT3362
series
DT3362-16SE/8DI
High level analog input system with 12-bit resolution and
maximum
50kHz
throughput.
Jumper-selectable
for 16
single-ended or 8 differential input channels.
Accepts
unipolar
or
bipolar
inputs.
Factory-configured for
differential inputs and bipolar input range.
1-3
INTRODUCTION
MODEL DESCRIPTIONS
DT3362-64SE/32DI
Same as DT3362-16SE/BDI, but
channels.
expanded
to
64SE/32DI
input
DT3362-16SE/BDI-PGH
High level analog input system with 12-bit resolution and
maximum
50kHz
throughput.
Jumper selectable for 16
single-ended or B differential input channels.
Accepts
unipolar or bipolar inputs. Software programmable for gains
of 1, 2,
4, or B.
Factory-configured for differential
inputs and bipolar input range.
DT3362-64SE/32DI-PGH
Same as DT3362-16SE/BDI-PGH, but expanded to 64SE/32DI input
channels.
DT3362-F-16SE
Fast, high level analog input system with 12-bit resolution
and maximum 125kHz throughput.
Provides 16 single-ended
input channels.
Accepts unipolar or
bipolar
inputs.
Software programmable for gains of 1, 2, 4, or B.
DT3362-F-64SE
Same as DT3362-F-16SE, but expanded to 64SE input channels.
DT3362-F-8D!
Fast, high level analog input system with 12-bit resolution
and maximum 125kHz throughput.
Provides B differential
input channels.
Accepts unipolar or
bipolar
inputs.
Software programmable for gains of 1, 2, 4, or B.
DT3362-F-32DI
Same as DT3362-F-BOI, but expanded to 3201 input channels.
DT3362-G-16SE
Fast, high level analog input system with 12-bit resolution
and maximum 250kHz throughput.
Provides 16 single-ended
input channels.
Accepts unipolar or
bipolar
inputs.
Software programmable for gains of 1, 2, 4, or B.
OT3362-G-64SE
Same as OT3362-G-16SE, but expanded to 6401 input channels.
OT3362-G-BOI
Fast, high level analog input system with 12-bit resolution
and maximum 250kHz throughput.
Provides B differential
input channels.
Accepts unipolar or
bipolar
inputs.
Software programmable for gains of 1, 2, 4, or B.
DT3362-G-32DI
Same as DT3362-G-8DI, but expanded to 32DI input channels.
OT3362-H-16SE
Fast, high level analog input system with 12-bit resolution
and maximum 250kHz throughput.
Provides 16 single-ended
input channels. Accepts unipolar or bipolar inputs.
1-4
INTRODUCTION
MODEL DESCRIPTIONS
DT3362-H-64SE
Same as DT3362-H=16SE, but expanded to 64SE input channels.
DT3362-H-BDI
Fast, high level analog input system with 12-bit resolution
and maximum 250kHz throughput.
Provides B differential
input channels. Accepts unipolar or bipolar inputs.
DT3362-H-32DI
Same as DT3362-H-BDI-PGH,
channels.
but
expanded
to
32D!
DT3362-H-16SE-PGH
Fast, high level analog input system with 12-bit resolution
and maximum 200kHz throughput.
Provides 16 single-ended
input channels.
Accepts unipolar or
bipolar
inputs.
Software programmable for gains of 1, 2, 4, or B.
DT3362-H-64SE-PGH
Same as DT3362-H-16SE-PGH,
channels.
but
expanded
to
64SE
input
DT3362-H-8DI-PGH
Fast, high level analog input system with 12-bit resolution
and maximum 200kHz throughput.
Provides 8 differential
input channels.
Accepts unipolar or
bipolar
inputs.
Software programmable for gains of 1, 2, 4, or B.
DT3362-H-32DI
Same as DT3362-H-8DI-PGH,
channels.
but
expanded
to
3201
input
DT3368-4SE
High level analog input system featuring a simultaneous
sample and hold converter module.
Provides 4 single-ended
input channels.
Offers 12-bit resolution
and
100kHz
throughput.
Accepts unipolar or bipolar inputs.
Operates
at a gain of 1.
DT3368-12SE
Same as DT3368-4SE, but expanded to 12SE input channels.
DT3377
Fast, high level analog input system with 16-bit resolution
and
100kHz throughput.
Provides 4 differential input
channels. Accepts bipolar inputs only. Operates at a gain
of 1.
1-5
INTRODUCTION
COMPATIBLE SCREW TERMINAL PANELS
1.2
COMPATIBLE SCREW TERMINAL PANELS
The DT3362 series boards are compatible with a number of data
acquisition accessories--screw terminal panels--avai1ab1e from
Data Translation. The data acquisition accessories belong in
two groups:
those that simply interface the A/D board to the
signal source; and those that condition the input signals in
addition to providing a connection interface. The following is
a brief description of screw terminal panels that can be used
with the various models in the DT3362 series.
1.2.1
DT701 SERIES
The DT701 series of screw terminal panels are compatible with
all models of the DT3362 series. Two versions, the DT701-20
and DT701-s0, can be used. The DT701-20 is used with the J3
connector of the basic or expanded versions of the DT3362
series, while the DT701-50 is used with the expanded versions
connecting
to J2.
These panels provide standard matrix
patterns for user-installation of conditioning circuits on each
input channel.
The matrix pattern accommodates current loop
resistors, noise filters, voltage dividers, open thermocouple
detection circuit, or any circuit required which mates with the
standard pattern.
1.2.2
DT6700 SERIES
The DT6700 series of isolated signal conditioning modules are
compatible with all single-ended models of the DT3362 series.
They are suited particularly for industrial application where
noise and common mode voltage could cause serious problems.
The modules are mounted on the DT750 backplane which connects
to the J3 connector of the basic or expanded versions of the
DT3362 series.
The J2 connection of the expanded board
accommodates three DT750 backplanes.
The conversion of the
50-pin J2 connector to three 20-pin connectors of the screw
terminal panels is made via the EP164 interconnection panel.
1.2.3
DT709 SERIES
The DT709-S and DT709-Y of the DT709 series
of
screw
terminal/signal conditioning panels are compatible with all
single-ended models of the DT3362 series. The DT709-S provides
only connection points to the measurement, while the DT709-Y
also offers common mode rejection and other signal conditioning
functions.
As a result, the DT709-Y effectively converts the
single-ended inputs of the DT3362 series into differential
inputs.
The basic versions of the DT3362 series accommodate
one DT709 series screw terminal panel via the J3 connector.
The
expanded versions accommodate one panel via the J3
connector and three panels via the J2 connector using the EP164
interconnection panel.' The DT709-Y requires an external power
source capable of supplying ±11V to ±15V at ±30mA minimum.
1-6
INTRODUCTION
COMPATIBLE SCREW TERMINAL PANELS
1.2.4
DT7S6 SERIES
The DT7S6-Y and DT7S6-D of the DT7S6 series
of
screw
terminal/signal conditioning panels are compatible with all
single-ended models of the DT3362 series except the DT3368-4SE
and DT3368-12SE which feature the simultaneous sample and hold
module. Both models provide signal conditioning- functions,
including common mode rejection which converts the single-ended
channels of the A/D board into differential channels.
The
basic versions of the DT3362 series accommodate one DT756
series screw terminal panel via the J3 connector. The expanded
versions accommodate one panel via the J3 connector and three
panels via the J2 connector using the EP164 interconnection
panel as shown in Figure 1-1. The DT7S6-Y requires an external
power source capable of supplying ±11V to ±15V at ±30mA
minimum.
The DT7S6-D has an on-board dc to dc converter and
requires only a +SV input at 2S0mA.
1-7
CHAPTER 2
2.1
INTRODUCTION
This chapter lists the specifications of the DT3362 series
boards and related accessories. Specifications are provided
for the following items:
0
0
0
0
0
0
0
0
0
0
0
Analog Inputs
Accuracy
Dynamic Performance
Thermal Characteristics
on-board Clock
External Trigger
Interface Characteristics
Power Requirements
Physical/Environmental
Connectors and Cables
Compatible Screw Terminal Panels
Unless noted otherwise,
+25°C and rated voltage.
the
specifications
2-1
are
typical
at
SPECIFICATIONS
DT3362-16SE/8DI AND DT3362-64SE/32DI
2.2
DT3362-16SE/8DI AND DT3362-64SE/32DI
ANALOG INPUTS
Number of Analog Inputs
DT3362-16SE/8DI
DT3362-64SE/32DI
16SE or 8DI, user-selectable
64SE or 32DI, user-selectable
Input Ranges
o to +10V (unipolar);
±10V (bipolar)
Output Data Codes
Straight binary (unipolar);
Offset binary (bipolar);
Two's complement (bipolar);
jumper-selectable. Sign extension available
with bipolar ranges
Input Impedance
"Off" channel: 100M2
in parallel with 10pF;
"On" channel:
1002
in parallel with 100pF
Bias Current
±20nA
f""'m ............
... ~& . . & . . ~&&
M .... ,.::a""
&&~U.~
T' .......... ~
... &&t"I.&~
1:7 .... '
~ ....... ""
Y '-' . . ~Q':1""
±llV
Maximum
Common Mode Rejection Ratio
(CMRR), Gain = 1
80dB at 60Hz, 1k2
unbalanced
Maximum Input Voltage Without
Damage, Power On
±35V
Maximum Input voltage Without
Damage, Power Off
±20V
0.2 LSB rms
NOTE: Where gain is greater
than 1, input noise is
multiplied by gain.
Amplifier Input Noise
Channel-to-channel Input
voltage Error
±5pV
2-2
SPECIFICATIONS
DT3362-16SE/SDI AND DT3362-64SE/32DI
ACCURACY
Resolution
12 bits
Nonlinearity
Less than ±1/2 LSB
Differential Nonlinearity
Less than ±1/2 LSB
Inherent Quantizing Error
±1/2 LSB
System Accuracy
To within ±.O3% FSR
Channel Cross Talk
-SOdB at 1kHz
Gain Error
Adjustable to 0
Zero Error
Adjustable to 0
DYNAMIC PERFORMANCE
Channel Acquisition Time
To within 1/2 LSB
lS,us
AID Conversion Time
10,us
Max. AID Converter Throughput
50kHz
(Throughput is defined as
the maximum frequency of AID
conversions achievable by the
boarde The figure given above
does not allow for software
overhead necessary to retrieve
the converted data.)
Sample And Hold Aperture
Uncertainty
10ns
Sample And Hold Aperture
Delay
SOns
Sample And Hold Feedthrough
Attenuation
SOdB at 1kHz
Sample And Hold Droop Rate
O.lmV/ms
2-3
SPECIFICATIONS
DT3362-16SE/8DI AND DT3362-64SE/32DI
THERMAL CHARACTERISTICS
A/D Zero Drift
±lOpV/OC (unipolar);
±lOppm of FSR/oC
(bipolar)
Amplifier Zero Drift
[±20pV/oC] +
[(±3pV/oC)xGain]
Gain Drift
±30ppm of FSR/oC
Differential Linearity Drift
±3ppm of FSR/oC
Monotonicity
Monotonic, 0 to +50 o C
(32 to 122°F)
2-4
SPECIFICATION,
DT3362-16SE/8DI-PGH AND DT3362-64SE/32DI-PGJ
2.3
DT3362-16SE/8DI-PGH AND DT3362-64SE/32DI-PGH
ANALOG INPUTS
Number of Analog Inputs
DT3362-8DI/16SE-PGH
DT3362-32DI/64SE-PGH
8DI or 16SE, user-selectable
32DI or 64SE f user-selectable
Input Ranges
o
to 1.25V to 0 to +10V
(unipolar);
±1.25V to ±10V (bipolar)
Output Data Codes
Straight binary (unipolar);
Offset binary (bipolar);
Two's complement (bipolar);
jumper selectable. Sign
extension is available with
bipolar ranges
Software Programmable Gain
1, 2, 4, 8
Input Impedance
"Off" channel: 100M2
in parallel with 10pF;
"On" channel: 100M2
in parallel with 100pF
Bias Current
±20nA
Common Mode Input voltage,
Maximum
±llV
Common Mode Rejection Ratio
(CMRR), Gain = 1
80dB at 60Hz, 1kQ
unbalanced
Maximum Input Voltage Without
Damage: Power On
±35V
Maximum Input voltage Without
Damage, Power Off
±20V
0.2 LSB rms
NOTE: Where gain is greater
than 1, input noise is
multiplied by gain.
Amplifier Input Noise
Channel-to-channel Input
Voltage Error
±5pV
2-5
SPECIFICATIONS
DT3362-16SE/BDI-PGH AND DT3362-64SE/32DI-PGH
ACCURACY
Resolution
12 bits
Nonlinearity
Less than ±1/2 LSB
Differential Nonlinearity
Less than ±1/2 LSB
Inherent Quantizing Error
±1/2 LSB
System Accuracy
Gain - 1
Gain -= B
To within ±.O3% FSR
To within ±.OS% FSR
Channel Cross Talk
-BOdB at 1kHz
Gain Error
Adjustable to 0
Zero Error
Adjustable to 0
DYNAMIC PERFORMANCE
Channel Acquisition Time
To within 1/2 LSB
lSps
A/D Conversion Time
lOps
Max. A/D Converter Throughput
50kHz
(Throughput is defined as
the maximum frequency of A/D
conversions achievable by the
board. The figure given above
does not allow for software
overhead necessary to retrieve
the converted data.)
Sample And Hold Aperture
Uncertainty
lOns
Sample And Hold Aperture
Delay
SOns
Sample And Hold Feedthrough
Attenuation
BOdB at 1kHz
Sample And Hold Droop Rate
O.1mV/ms
2-6
SPECIFICATIONS
DT3362-16SE/8DI-PGH AND DT3362-64SE/32DI-PGH
THERMAL CHARACTERISTICS
A/D Zero Drift
±10pV/OC (unipolar)
±10ppm of FSR/"C
(bipolar)
Amplifier Zero Drift
[±20pV/oC] +
[(±3pV/oC)xGain]
±30ppm of FSR/oC
Differential Linearity Drift
±3ppm of FSR/oC
Monotonicity
Monotonic, 0 to +SooC
(32 to 122°C)
2-7
SPECIFICATIONS
DT3362-F-16SE AND DT3362-F-64SE
2.4
DT3362-F-16SE AND DT3362-F-64SE
ANALOG INPUTS
Number of Analog Inputs
DT3362-F-16SE
DT3362-F-64SE
16SE
64SE
Input Ranges
o
to 1.2SV to 0 to +10V
(unipolar);
±1.2SV to ±10V (bipolar)
Output Data Codes
Straight binary (unipolar)
Offset binary (bipolar);
Two's complement (bipolar);
jumper-selectable. Sign
extension is available with
bipolar ranges
Software programmable Gain
1, 2, 4, 8
Input Impedance
"Off" channel: 100M2
in parallel with SOPF;
"On" channel:
100M2
in parallel with 100pF
Bias Current
10nA
Common Mode Input Voltage,
Maximum
±10.SV
Common Mode Rejection Ratio
(CMRR), Gain = 1
80dB at 60Hz, lk2
unbalanced
Maximum Input Voltage Without
Damage, Power On
±27V
Maximum Input Voltage Without
Damage, Power Off
±12V
0.2 LSB rms
NOTE: Where gain is greater
than 1, input noise is
multiplied by gain.
Amplifier Input Noise
Channel-to-channel Input
Voltage Error
1/2 LSB
2-8
SPECIFICATION
DT3362-F-16SE AND DT3362-F-64S
ACCURACY
Resolution
12 bits
Nonlinearity
Less than ±1/2 LSB
Differential Nonlinearity
Less than 0.012% of FSR
Inherent Quantizing Error
±1/2 LSB
System Accuracy
Gain = 1
Gain = 2
Gain z: 4
Gain = 8
To
To
To
To
Channel Cross Talk
-100dB at 1kHz
Gain Error
Adjustable to 0
Zero Error
Adjustable to 0
Offset Error
Adjustable to 0
Noise
0.2 LSB rms
2-9
within
within
within
within
±.03%
±.04%
±.05%
±.07%
FSR
FSR
FSR
FSR
SPECIFICATIONS
DT3362-F-16SE AND DT3362-F-64SE
DYNAMIC PERFORMANCE
Channel Acquisition Time
To within 1/2 LSB
4,us
A/D Conversion Time
4,us
Max. A/D Converter Throughput
125kHz
(Throughput is defined as
the maximum frequency of A/D
conversions achievable by the
board. The figure given above
aoes not allow for software
overhead necessary to retrieve
the converted data.)
Sample And Hold Acquisition
Time
2.5,us
Sample And Hold Aperture
Uncertainty
0.5ns
Sample And Hold Aperture
Delay
lOOns
Sample And Hold
Attenuation
'et _ _
~""\..
_ _ •• "..\-.
S:CCUI..U"'VU~U
Sample And Hold Droop Rate
80dB at 1kHz
50pV/,us
THERMAL CHARACTERISTICS
A/D Zero Drift
±50,uV/OC (unipolar)
±10ppm of FSR/oC
(bipolar)
Amplifier Zero Drift
50pV/oC
Gain Drift
±30ppm of FSR/oC
Differential Linearity Drift
±3ppm of FSR/oC
Monotonicity
Monotonic, 0 to +70 oC
(32 to 158°C)
2-10
SPECI FICATION:
DT3362-F-8DI AND DT3362-F-32D:
2.S
DT3362-F-SDI AND DT3362-F-32DI
ANALOG INPUTS
Number of Analog Inputs
DT3362-F-SDI
DT3362-F-32DI
801
3201
Input Ranges
o
to 1.2Sv to 0 to +10V
(unipolar);
±1.2SV to ±10V (bipolar)
Output Data Codes
Straight binary (unipolar)
Offset binary (bipolar);
Two's complement (bipolar);
jumper selectable. Sign
extension is available with
bipolar ranges
Software programmable Gain
1, 2, 4, 8
Input Impedance
"Off" channel: 100M2
in parallel with SOPF;
~On" channel:
100M2
in parallel with 100pF
Bias Current
10nA
Common Mode Input voltage,
Maximum
±10.SV
Common Mode Rejection Ratio
(CMRR), Gain = 1
SOdS at 60Hz, 1k2
unbalanced
Maximum Input Voltage Without
Damage, Power On
±27V
Maximum Input voltage Without
Damage, Power Off
±12V
Amplifier Input Noise
Channel-to-channel Input
Voltage Error
0.2 LSS rms
NOTE: Where gain is greater
than 1, input noise is
multiplied by gain.
1/2 LSB
2-11
SPECIFICATIONS
DT3362-F-8DI AND DT3362-F-32DI
ACCURACY
Resolution
12 bits
Nonlinearity
Less than ±1/2 LSB
Differential Nonlinearity
Less than 0.012% of FSR
Inherent Quantizing Error
±1/2 LSB
System Accuracy
Gain = 1
Gain = 2
Gain = 4
Gain = 8
To
To
To
To
Channel Cross Talk
-100dB at 1kHz
Gain Error
Adjustable to 0
Zero Error
Adjustable to 0
Offset Error
Adjustable to 0
Noise
0.2 LSB rms
2-12
within
within
within
within
±.03% FSR
±.04% FSR
.., ...,
±.O5% ....1l'C!D
±.07% FSR
SPEcr FICATION~
DT3362-F-8DI AND DT3362-F-32D:
DYNAMIC PERFORMANCE
Channel Acquisition Time
To within 1/2 LSB
A/D Conversion Time
4ps
Max. A/D Converter Throughput
125kHz
(Throughput is defined as
the maximum frequency of AID
conversions achievable by the
board. The figure given above
does not allow for software
overhead necessary to retrieve
the converted data.)
Sample And Hold Acquisition
Time
2.Sps
Sample And Hold Aperture
Uncertainty
O.Sns
Sample And Hold Aperture
Delay
lOOns
Sample And Hold Feedthrough
Attenuation
BOdB at 1kHz
Sample And Hold Droop Rate
SOpV/ps
THERMAL CHARACTERISTICS
A/D Zero Drift
±SOpV/OC (unipolar)
±10ppm of FSR/oC
(bipolar)
Amplifier Zero Drift
sopv/oe
Gain Drift
±30ppm of FSR/oe
Differential Linearity Drift
±3ppm of FSR/oe
Monotonicity
Monotonic, 0 to +70 oe
(32 to lS8 C F)
2-13
SPECIFICATIONS
DT3362-G-16SE AND DT3362-G-64SE
2.6
DT3362-G-16SE AND DT3362-G-64SE
ANALOG INPUTS
Number of Analog Inputs
DT3362-G-16SE
DT3362-G-64SE
16SE
64SE
Input Ranges
o
to 1.2SV to 0 to +10V
(unipolar);
±1.2SV to ±10V (bipolar)
Output Data Codes
Straight binary (unipolar);
Offset binary (bipolar);
Two's complement (bipolar);
jumper selectable. Sign
extension is available with
bipolar ranges
Software Programmable Gain
1, 2, 4,
Input Impedance
"Off" channel: 100M2
in parallel with 10pF;
"On" channel: 100M2
in parallel with 50pF
Bias Current
±20nA
Common Mode Input voltage,
Maximum
±11V
Common Mode Rejection Ratio
(CMRR), Gain = 1
a
aOdB at 60Hz, 1k2
unbalanced
Maximum Input voltage Without
Damage, Power On
±16v
Maximum Input Voltage Without
Damage, Power Off
±1V
Amplifier Input Noise
100pV rms
Channel-to-channel Input
voltage Error
±100pV
2-14
SPECIFICATIONE
DT3362-G-16SE AND DT3362-G-64SE
ACCURACY
Resolution
12 bits
Nonlinearity
Less than ±1/2 LSB
Differential
. Less
than ±1/2 LSB
Inherent Quantizing Error
±1/2 LSB
System Accuracy
Gain = 1
Gain = B
To within ±.03% FSR
To within ±.05% FSR
Channel Cross Talk
-BOdB at 1kHz
Gain Error
Adjustable to 0
Zero Error
Adjustable to 0
Noise
0.2 LSB rms
DYNAMIC PERFORMANCE
Channel Acquisition Time
To within 1/2 LSB
2.5,us
AID Conversion Time
2.5,us
Max. AID Converter Throughput
250kHz
(Throughput is defined as
the maximum frequency of A/D
conversions achievable by the
board. The figure given above
does not allow for software
overhead necessary to retrieve
the converted data.)
Sample And Hold Aperture
Uncertainty
Less than 2ns
Sample And Hold Aperture
Delay
40ns
Sample Hold Feedthrough
Attenuation
BOdB at 1kHz
Sample And Hold Droop Rate
20,uV/,us
2-15
SPECIFICATIONS
DT3362-G-16SE AND DT3362-G-64SE
THERMAL CHARACTERISTICS
A/D Zero Drift
±SOpV/OC (unipolar);
±2Sppm of FSR/oC (bipolar)
Amplifier Zero Drift
[±20pV/oC] +
[(±10pV/oC)xGain]
Gain Drift
±40ppm of FSR/oC
Differential Linearity Drift
±3ppm of FSR/oC
Monotonicity
Monotonic, 0 to +SO°C
(32 to 122°F)
2-16
SPECIFICATIONS
DT3362-G-8DI AND DT3362-G-32DI
2.7
DT3362-G-8DI AND DT3362-G-32DI
ANALOG INPUTS
Number of Analog Inputs
DT3362-G-8DI
nrn""I!:"'I
,..
.., ...... -
VJ.';)';)O~-U-,;)~Ul.
Input Ranges
8DI
32DI
o
to 1.2SV to 0 to +10V
{" .... .; ........ 1 ....... \ .
\.
\"&~""'JJv.a.L.!
I
±1.2SV to ±10V (bipolar)
output Data Codes
Straight binary (unipolar)
Offset binary (bipolar);
Two's complement (bipolar);
jumper selectable. Sign
extension is available with
bipolar ranges
Software programmable Gain
1, 2, 4, 8
Input Impedance
"Off" channel: 100M2
in parallel with 10pFi
"On" channel: 1002
in parallel with SOpF
Bias Current
±20nA
Common Mode Input Voltage,
Maximum
±llV
Common Mode Rejection Ratio
(CMRR), Gain = 1
80dB at 60Hz, lk2
unbalanced
Maximum Input Voltage Without
Damage, Power On
±16V
Maximum Input Voltage Without
Damage, Power Off
±1V
Amplifier Input Noise
100pV rms
Channel-to-channel Input
voltage Error
±100,uV
2-17
SPECIFICATIONS
DT3362-G-8DI AND DT3362-G-32DI
ACCURACY
Resolution
12 bits
Nonlinearity
Less than ±1/2 LSB
Differential Nonlinearity
Less than ±1/2 LSB
Inherent Quantizing Error
±1/2 LSB
System Accuracy
Gain = 1
Gain = 8
To within ±.03% FSR
To within ±.05% FSR
Channel Cross Talk
-80dB at 1kHz
Gain Error
Adjustable to 0
Zero Error
Adjustable to 0
Noise
0.2 LSB rms
DYNAMIC PERFORMANCE
Channel Acquisition Time
To within 1/2 LSB
2.5,us
AID Conversion Time
Max. A/D Converter Throughput
250kHz
(Throughput is defined as
the maximum frequency of A/D
conversions achievable by the
board. The figure given above
does not allow for software
overhead necessary to retrieve
the converted data.)
Sample And Hold Aperture
Uncertainty
Less than 2ns
Sample And Hold Aperture
Delay
40ns
Sample Hold Feedthrough
Attenuation
80dB at 1kHz
Sample And Hold Droop Rate
20pV/ps
2-18
SPECI FI CATION~
DT3362-G-8DI AND DT3362-G-32D:
THERMAL CHARACTERISTICS
A/D Zero Drift
±SOpV/OC (unipolar);
±25ppm of FSR/oC (bipolar)
Amplifier Zero Drift
[±20pV/OC] +
[(±10pv/ g C)xGain]
Gain Drift
±40ppm of FSR/pC
Differential Linearity Drift
±3ppm of FSR/pC
Monotonicity
Monotonic, 0 to +SooC
(32 to 122°F)
2-19
SPECIFICATIONS
DT3362-H-16SE AND DT3362-H-64SE
2.S
DT3362-H-16SE AND DT3362-H-64SE
ANALOG INPUTS
Number of Analog Inputs
DT3362-H-16SE
DT3362-H-64SE
16SE
64SE
Input Ranges
o to +10V (unipolar);
±10V (bipolar)
Output Data Codes
straight binary (unipolar);
Offset binary (bipolar);
Two's complement (bipolar);
jumper selectable. Sign
extension is available with
bipolar ranges
Input Impedance
"Off" channel: 100M2
in parallel with 10pF;
"On" channel:
100M2
in parallel with SOpF
Bias Current
±20nA
Common Mode Input Voltage,
Maximum
±11V
Common Mode Rejection Ratio
(CMRR)
SOdB at 60Hz, 1k2
unbalanced
Maximum Input voltage without
Damage, Power On
±16V
Maximum Input voltage Without
Damage, Power Off
±1V
Amplifier Input Noise
100,uV rms
Channel-to-channel Input
Voltage Error
±100,uV
2-20
SPECIFICATIONS
DT3362-H-16SE AND DT3362-H-64SE
ACCURACY
Resolution
12 bits
Nonlinearity
Less than ±1/2 LSB
Differential Nonlinearity
Less than ±1/2 LSB
Inherent Quantizing Error
±1/2 LSB
System Accuracy
To within ±.03% FSR
Channel Cross Talk
-80dB at 1kHz
Gain Error
Adjustable to 0
Zero Error
Adjustable to 0
Noise
0.2 LSB rms
DYNAMIC PERFORMANCE
Channel Acquisition Time
To within 1/2 LSB
2.5ps
A/D Conversion Time
2.5ps
Max. A/D Converter Throughput
250kHz
(Throughput is defined as
the maximum frequency of A/D
conversions achievable by the
board. The figure given above
does not allow for software
overhead necessary to retrieve
the converted data.)
Sample And Hold Aperture
Uncertainty
Less than 2ns
Sample And Hold Aperture
Delay
40ns
Sample Hold Feedthrough
Attenuation
aOdB at 1kHz
Sample And Hold Droop Rate
20pV/ps
2-21
SPECIFICATIONS
DT3362-H-16SE AND DT3362-H-64SE
THERMAL CHARACTERISTICS
A/D Zero Drift
±50pV/OC (unipolar);
±25ppm of FSR/oC (bipolar)
Amplifier Zero Drift
[±20pV/oC] +
[(±10pV/oC)xGain]
Gain Drift
±40ppm of FSR/oC
Differential Linearity Drift
±3ppm of FSR/oC
Monotonicity
Monotonic, 0 to +50 oC
(32 to 122°F)
2-22
SPECIFICATIONS
DT3362-H-8DI AND DT3362-H-32DI
2.9
DT3362-H-8DI AND DT3362-H-32DI
ANALOG INPUTS
Number of Analog Inputs
DT3362-H-8DI
DT3362-H-32DI
8DI
32DI
Input Ranges
o to +10V (unipolar);
±10V (bipolar)
output Data Codes
Straight binary (unipolar)
Offset binary (bipolar);
Two's complement (bipolar);
jumper selectable. Sign
extension is available with
bipolar ranges
Input Impedance
"Off" channel: 100MQ
in parallel with 10pF;
"On" channel: 10052
in parallel with 50pF
Bias Current
±20nA
Common Mode Input Voltage,
Maximum
±11V
Common Mode Rejection Ratio
(CMRR)
aOdB at 60Hz, 1kQ
unbalanced
Maximum Input Voltage Without
Damage, Power On
±16V
Maximum Input voltage Without
Damage, Power Off
±lV
Amplifier Input Noise
100,uV rms
Channel-to-channel Input
Voltage Error
±100,uV
ACCURACY
Resolution
12 bits
Nonlinearity
Less than ±1/2 LSB
Differential Nonlinearity
Less than ±1/2 LSB
Inherent Quantizing Error
±1/2 LSB
System Accuracy
To within ±.03% FSR
2-23
SPECIFICATIONS
DT3362-H-SDI AND DT3362-H-32DI
Channel Cross Talk
-SOdS at 1kHz
Gain Error
Adjustable to 0
Zero Error
Adjustable to 0
Noise
0.2 LSS rms
DYNAMIC PERFORMANCE
Channel Acquisition Time
To within 1/2 LSB
2.5ps
A/D Conversion Time
2.5ps
Max. A/D Converter Throughput
250kHz
(Throughput is defined as
the maximum frequency of A/D
conversions achievable by the
board.
The figure given above
does not allow for software
overhead necessary to retrieve
the converted data.)
Sample And Hold
Uncertainty
Less than 2ns
Sample And Hold Aperture
Delay
40ns
Sample Hold Feedthrough
Attenuation
SOdS at 1kHz
Sample And Hold Droop Rate
20pV/ps
THERMAL CHARACTERISTICS
A/D Zero Drift
±50pV/OC (unipolar);
±25ppm of FSR/oC (bipolar)
Amplifier Zero Drift
[±20pV/oC] +
[(±10pV/oC)xGain]
Gain Drift
±40ppm of FSR/pC
Differential Linearity Drift
±3ppm of FSR/pC
Monotonicity
Monotonic, 0 to +50°C
(32 to 122°F)
2-24
SPECIFICATIONS
DT3362-H-16SE-PGH AND DT3362-H-64SE-PGH
2.10
DT3362-H-16SE-PGH AND DT3362-H-64SE-PGH
ANALOG INPUTS
Number of Analog Inputs
DT3362-H-16SE-PGH
nm~~~~
u
~A~~
n~u
U~JJV~-U-V~~~-.uu
16SE
~A~~
V~~~
o
Input Ranges
to 1.25V to 0 to +10V
(unipolar);
±1.2SV to ±10V (bipolar)
Output Data Codes
Straight binary (unipolar);
Offset binary (bipolar);
Two's complement (bipolar);
jumper selectable. Sign
extension is available with
bipolar ranges
Software Programmable Gain
1, 2, 4,
Input Impedance
"Off" channel: 100M2
in parallel with 10pFi
"On" channel: 100M2
in parallel with 50pF
Bias Current
±20nA
Common Mode Input Voltage,
Maximum
±11V
Common Mode Rejection Ratio
(CMRR), Gain = 1
a
aOda at 60Hz, lkQ
unbalanced
Maximum Input voltage Without
Damage, Power On
±16v
Maximum Input voltage Without
Damage, Power Off
±IV
Amplifier Input Noise
lOOpV rms
Channel-to-channel Input
Voltage Error
±100pV
2-25
SPECIFICATIONS
DT3362-H-16SE-PGH AND DT3362-H-64SE-PGH
ACCURACY
Resolution
12 bits
Nonlinearity
Less than ±1/2 LSS
Differential Nonlinearity
Less than ±1/2 LSS
Inherent Quantizing Error
±1/2 LSS
System Accuracy
Gain = 1
Gain = a
To within ±.03% FSR
To within ±.OS% FSR
Channel Cross Talk
-SOdS at 1kHz
Gain Error
Adjustable to 0
Zero Error
Adjustable to 0
Noise
0.2 LSS rms
DYNAMIC PERFORMANCE
Channel Acquisition Time
To within 1/2 LSS
2.Sps
A/D Conversion Time
2.Sps
Max. A/D Converter Throughput
200kHz
(Throughput is defined as
the maximum frequency of A/D
conversions achievable by the
board. The figure given above
does not allow for software
overhead necessary to retrieve
the converted data.)
Sample And Hold Aperture
Uncertainty
Less than 2ns
Sample And Hold Aperture
Delay
40ns
Sample Hold Feedthrough
Attenuation
.
aOds at 1kHz
Sample And Hold Droop Rate
20pV/ps
2-26
SPECIFICATIONS
DT3362-H-16SE-PGH AND DT3362-H-64SE-PGH
THERMAL CHARACTERISTICS
A/D Zero Drift
±50pV/OC (unipolar);
±25ppm of FSR/oC (bipolar)
Amplifier Zero Drift
[±20pV/OC] +
[(±lOpV/oC)xGainj
Gain Drift
±40ppm of FSR/oC
Differential Linearity Drift
±3ppm of FSR/oC
Monotonicity
Monotonic, 0 to +50 o C
(32 to 122°F)
2-27
SPECIFICATIONS
DT3362-H-8DI-PGH AND DT3362-H-32DI-PGH
2.11
DT3362-H-8DI-PGH AND DT3362-H-32DI-PGH
ANALOG INPUTS
Number of Analog Inputs
DT3362-H-8DI-PGH
DT3362-H-32DI-PGH
8DI
32DI
Input Ranges
o
to 1.2SV to 0 to +10V
(unipolar);
±1.2SV to ±10V (bipolar)
output Data Codes
Straight binary (unipolar)
Offset binary (bipolar);
Two'S complement (bipolar);
jumper selectable. Sign
extension is available with
bipolar ranges
Software Programmable Gain
1, 2, 4, 8
Input Impedance
"Off" channel: 100M2
in parallel with 10pF;
"On" channel: 1002
in parallel with SOpF
Bias Current
±20nA
Common Mode Input Voltage:
Maximum
±IIV
Common Mode Rejection Ratio
(CMRR), Gain = 1
80dB at 60Hz, lk2
unbalanced
Maximum Input Voltage Without
Damage, Power On
±16V
Maximum Input Voltage Without
Damage, Power Off
±IV
Amplifier Input Noise
100pV rms
Channel-to-channel Input
voltage Error
±100pV
2-28
SPECIFICATION~
DT3362-H-8DI-PGH AND DT3362-H-32DI-PGf
ACCURACY
Resolution
12 bits
Nonlinearity
Less than ±1/2 LSS
Differential Nonlinearity
Less
Inherent Quantizing Error
±1/2 LSS
System Accuracy
Gain
1
Gain = 8
To within ±.03% FSR
To within ±.OS% FSR
Channel Cross Talk
-80dS at 1kHz
Gain Error
Adjustable to 0
Zero Error
Adjustable to 0
Noise
0.2 LSS rms
:II:
+-J..""
.......... ""',.......
.,
/")
~./
~
T ~"
J.lOg
DYNAMIC PERFORMANCE
Channel Acquisition Time
To within 1/2 LSS
2.Sps
AID Conversion Time
2.S,us
Max. AID Converter Throughput
200kHz
(Throughput is defined as
the maximum frequency of AID
conversions achievable by the
board. The figure given above
does not allow for software
overhead necessary to retrieve
the converted data.)
Sample And Hold Aperture
Uncertainty
Less than 2ns
Sample And Hold Aperture
Delay
40ns
Sample Hold Feedthrough
Attenuation
BOdS at 1kHz
Sample And Hold Droop Rate
20,uV/,us
2-29
SPECIFICATIONS
DT3362-H-8DI-PGH AND DT3362-H-32DI-PGH
THERMAL CHARACTERISTICS
A/D Zero Drift
±50pV/OC (unipolar);
±25ppm of FSR/oC (bipolar)
Amplifier Zero Drift
[±20pV/oC] +
[(±10pV/oC)xGain]
Gain Drift
±40ppm of FSR/pC
Differential Linearity Drift
±3ppm of FSR/pC
Monotonicity
Monotonic, 0 to +50 0 C
(32 to 122°F)
2-30
SPECIFICATION
DT337
2.12
DT3377
ANALOG INPUTS
Number of Analog Inputs
4DI
Input Range
±10V (bipolar)
Gain Range
1 (fixed)
output Data Codes
Two's complement
Input Impedance
"Off" channel: 100M2
in parallel with 10pH;
"On" channel: 100M2
in parallel with 20pF
Bias Current
250±nA
Common Mode Input Voltage,
Maximum
±10.5V
Common Mode Rejection Ratio
(CMRR)
BOdB at 1kHz
Maximum Input Voltage Without
Damage, Power On
±27V
Maximum Input Voltage Without
Damage, Power Off
±12V
Amplifier Input Noise
0.5 LSB rms
Channel-to-channel Input
voltage Error
±100pV
ACCURACY
Resolution
16 bits
Nonlinearity
0.003% of FSR
Differential Nonlinearity
0.0015% of FSR
Inherent Quantizing Error
±1/2 LSB
System Accuracy
To within ±.003% FSR
Channel Cross Talk
-100dS at 50kHz
Gain Error
Adjustable to 0
Zero Error
Adjustable to 0
2-31
SPECIFICATIONS
DT3377
DYNAMIC PERFORMANCE
Channel Acquisition Time
To within 1/2 LSB
6ps
AID Conversion Time
6ps
Max. AID Converter Throughput
100kHz
(Throughput is defined as
the maximum frequency of AID
conversions achievable by the
board. The figure given above
does not allow for software
overhead necessary to retrieve
the converted data.)
Sample And Hold Aperture
Uncertainty
0.2ns
Sample And Hold Aperture
Delay
lOOns
Sample And Hold Feedthrough
Attenuation
94dB at 100kHz
Sample And Hold Droop Rate
7.5mV/ms
THERMAL CHARACTERISTICS
Offset Drift
Gain Drift
0.001% of FSR/pOC
Differential Linearity Drift
±1.5ppm of FSR/oC
Monotonicity
Monotonic, 0 to +60°C
(32 to 140°F)
2-32
SPECIFICATION~
DT3368-4SE AND DT3368-12S1
2.13
DT3368-4SE AND DT3368-12SE
ANALOG INPUTS
Number of Analog Inputs
DT3368-4SE
DT3368-12SE
4SE
12SE
Input Ranges
o to +10V (unipolar)
±10V (bipolar)
Output Data Codes
Straight binary (unipolar)
Offset binary (bipolar);
Two's complement (bipolar);
Jumper selectable: Sign
extension is available with
bipolar ranges
Gain
1 (fixed)
Input Impedance
"Off" channel: 10M2
in parallel with 20pF;
"On" channel: 10M2
in parallel with 20pF
Bias Current
200nA
Maximum Input Voltage Without
Damage, Power On
±31V
Maximum Input voltage Without
Damage, Power Off
±16V
Channel-to-Channel Input
Voltage Error
±10mV
2-33
SPECIFICATIONS
DT336S-4SE AND DT336S-l2SE
ACCURACY
Resolution
12 bits
Nonlinearity
Less than ±1/2 LSB
Differential Nonlinearity
±1/2 LSB
Inherent Quantizing Error
±1/2 LSB
System Accuracy
Within ±O.O4% of FSR/oC
Single Channel Accuracy
Within ±O.O3% of FSR/oC
Channel Crosstalk
-SOdB at 50kHz
Gain Error
Adjustable to 0
Zero Error
Adjustable to 0
DYNAMIC PERFORMANCE
Channel Acquisition Time
6ps
A/D Conversion Time
4ps
System Aggregate Throughput
of Channel 0
100kHz
(Throughput is defined as
the maximum frequency of A/D
conversions achievable by the
board. The figure given above
does not allow for software
overhead necessary to retrieve
the converted data.)
Sample And Hold Aperture
Uncertainty
±5ns
Sample And Hold Aperture
Delay
lOOns
Sample And Hold Feedthrough
Attenuation
SOdB
Sample And Hold Droop Rate
O.5mV/ms
Slewing Rate
5V/ps
Bandwidth
lMHz
Phase Match At 50kHz
Within .1oC
2-34
SPECIFICATION~
DT3368-4SE AND DT3368-12S1
THERMAL CHARACTERISTICS
A/D Zero Drift
Gain Tempco
±20pV/O (unipolar)
±20ppm of FSR/oC (bipolar)
Gain Drift
±30ppm of FSR/oC
Linearity Drift
±3ppm of FSR/oC
Monotonicity
Monotonic, 0 to +70 o C
(32 to 158°Fj
2-35
SPECIFICATIONS
EXTERNAL TRIGGER
2.14
EXTERNAL TRIGGER
Function
Initiate A/D conversions
Input Type
Edge sensitive;
clocks on falling edge
Logic Compatibility
TTL
Origin
User device (such as DT2769
real-time clock)
Logic Load
Presents 1 TTL load
Logic High Input Voltage
2.4V minimum
Logic Low Input voltage
Logic High Input Current
Logic Low Input Current
Minimum pulse width
Clock High
Clock Low
O.SV maximum
SOpA @ 2.4V
2mA maximum
Loading
Presents 1 TTL load to the
user driver
2.15
200ns
200ns
INTERFACE CHARACTERISTICS
Compatible Bus
Q-bus
Interface Type
I/O mapped in 4K I/O page
Bus Loading
Board presents 1 dc load;
1 ac load
Number of Locations Occupied
S word locations reserved
Base Address
Jumper-selectable
over the range 760000 (oct)
to 777760 (oct) in increments
of 20 (oct)
Factory-assigned
Base Address
771300 (oct)
Analog Data Format
12-bit Models
Right-hand justified
Data Path
16 bits
2-36
SPECIFICATIONS
POWER REQUIREMENTS
2.16
POWER REQUIREMENTS
+SV
2.17
±5%, @ 2.5A, typical
PHYSICAL/ENVIRONMENTAL
Dimensions
8.39"H X 10.34"W X 0.43"0
(21.5 X 26.5 X 1.lcm)
Weight
Non-expanded Board
Expanded Board
19.5 ounces (553g)
24.0 ounces (680g)
Maximum Altitude
7,500 feet (2286 meters)
Operating Temperature Range
o
Storage Temperature Range
-25 to +70 degrees C
(-13 to 158°F)
Humidity
To 90%, non=condensing
2.18
to +50 o c
(32 to 122°F)
CONNECTORS AND CABLES
Connector J1
26-pin header, male;
mating connector: 26-pin
header, female, 3M type,
PIN 3399 or equivalent
Connector J2
50-pin header, male;
mating connector: 50-pin
header, female, 3M type,
PIN 3425 or equivalent
Connector J3
20-pin header, male;
mating connector: 20-pin
header, female, 3M type,
PIN 3421 or equivalent
Cable Assemblies
EP097, 26-conductor,
flat ribbon;EP097, 8 ft;
EP097-1, 1.5 ft;
Connector 1: socket, PIN
3M-3399; Connector 2:
socket, PIN 3M-3399
EP035, 50-conductor,
flat ribbon; EP035, 8 ft;
Connector 1: socket, PIN
3M-3425; Connector 2:
socket, PIN 3M-3425
2-37
SPECIFICATIONS
CONNECTORS AND CABLES
EP066, 50-conductor, flat
twisted pair, 8 ft;
Connector 1: socket, P/N
3M-342S; Connector 2:
socket, P/N 3M-342S
EP164 Interconnection Panel
2.19
Used with expanded
versions of the DT3362
series; converts three
20-pin inputs into one
50-pin output
COMPATIBLE SCREW TERMINAL PANELS
DT701-20
All models
DT701-S0
Expanded models only;
connected via J2 on
DT3362 series
DT7S0/DT6700
All SE models
DT709-S
All SE models
DT709-Y
All SE models
DT7S6-Y and DT7S6-D
All SE models except
DT3368=4SE and DT3368-12SE
2-38
CHAPTER 3
UNPACKING AND CONFIGURATION
3.1
INTRODUCTION
This chapter consists of two parts. The first part explains
how to unpack the board.
The second part discusses the
configuration of user-selectable parameters which should be
done prior to installing the board.
3.2
UNPACKING
Inspect the shipping carton immediately upon receipt for
evidence of mishandling during transit.
Depending on the
condition of the shipping carton, proceed as outlined in the
next two sections.
3.2.1
NO APPARENT DAMAGE
If no visible damage is found, proceed as follows:
1.
Place the container
shipping tape.
on
a
2.
Grasp the front of the flat carton
forward and up to open the top.
3.
While placing one hand firmly on a metal ground, remove the
board from the styrofoam chips.
This will prevent any
damage to the board components from possible
static
electricity build-up during transit.
4.
After allowing a moment for the discharge of any static
electricity into the metal ground, carefully unwrap the
board or component from the anti-static bag.
5.
Examine the board again for any possible damage.
If any
sign of damage is encountered, proceed as detailed in the
next section.
3-1
stable
surface
and
underneath
cut
and
the
lift
UNPACKING AND CONFIGURATION
UNPACKING
3.2.2
VISIBLE DAMAGE
If the board container shows any visible damage, open it in the
presence of the delivering carrier's agent. Then proceed to
unpack it from the shipping container as detailed in the
previous section. Then:
1.
Examine the board for shipping damage.
If damage is
detected, do NOT perform any repair or installation of the
damaged board.
If the delivery carrier's agent was not
present during unpacking,
call for an insurance claim
inspection.
2.
Have the insurance agent inspect the damage and arrive
an agreement to repair or replace the damaged board.
3.
If the board is to be repaired, call or write:
at
Customer Service Department
Data Translation, Inc.
100 Locke Drive
Marlboro, MA 01752-1192
Tel: (617) 481-3700
Telex: 951646 (DATATRANS MARO)
Easylink 62825999
4.
Request a Return Material Authorization (RMA) number.
This
must be obtained before any board will be accepted for
return.
5.
Repackage the damaged board in the anti-static wrapping and
place it in its original shipping material or a secure
container for shipment back to the factory.
NOTE
Ensure that the board is wrapped in anti-static
(electrically conductive) packaging, and that it is
handled with ground protection. Static electricity
is potentially damaging to electrical components on
Data Translation products.
6.
Return the damaged board,
address above.
with
3-2
the
RMA
number,
to
the
UNPACKING AND
CONFIGURATIO~
CONFIGURATIO~
3.3
CONFIGURATION
certain operational parameters on the DT3362 series boards are
user-selectable and are configured via the addition or removal
of jumpers. Jumpers are installed by connecting two jumpe~
posts with a jumper plug or a wire wrap.
In this manual and on the DT3362 series board, jumpers are
designated by either a capital or a lower case "w", followed by
a number.
A
single
capital
"W"
number--as
WI4
or
W18--designates two aOJacent posts which make up the jumper.
Installing W14, for instance, consists of connecting together
the pair of posts designated by the single number. A lower
case "w" followed by a number designates a jumper post.
In
this case, the jumper is fully designated with two lower case
"w" numbers such as wI4 to wIS. This type of designation is
used when a jumper post is shared by two or more jumpers.
Installing the jumper "w14 to wlS consists of connecting
together the two separately labeled posts. Appendix C shows an
assembly drawing which identifies the locations of all user
accessible jumper.
3.3.1
DEVICE BASE ADDRESS SELECTION
The DT3362 has been designed such that its base address (the
I/O address associated with the ADCSR; see Chapter S) can be
assigned any value from 760000 to 777760 (octal) in the I/O
address range of the processor, in increments of 20 (octal).
The addresses of the other registers are fixed relative to the
location of the ADCSR. Figure 3-1 shows the factory-set value
of 771300 for the base address implemented on the board.
3-3
UNPACKING AND CONFIGURATION
CONFIGURATION
7
7
17 16 15 14 13
1
1
1
1
I
Always 1
1
3
1
0
0
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
I
I
I
0
0
0
0
0
0
0
0
0
W41 W40 W39 W43 W42 W47 W46 W51 W50
I
Select
on-board
registers
FIGURE 3-1: BASE ADDRESS SELECTION OF 771300 (OCTAL)
As shown in Figure 3-1, for an address bit, a value of 1 is
selected by installing the corresponding jumper; a value of 0
is selected by removing the jumper. Thus W41, W43, W47, and
W46 must be installed as shown to select a value of 1 for bits
12, 9, 7, and 6, respectively.
3.3.2
DEVICE INTERRUPT VECTOR ADDRESS SELECTION
The DT3362 series board can send two unique interrupts to the
processor. These interrupts can occur on the A/D Done/DMA Done
condition and on the A/D Error condition. The interrupt vector
associated with the A/D Done or DMA Done condition can be
assigned any value in the 000-770 (octal) range in increments
of 10 (octal).
The vector address associated with the A/D
Error condition is four locations higher.
Thus to set an
address of 400 bit 8 must be set requiring the installation of
jumper W45. The interrupt vector of the error condition would
then be 400 + 04
404.
Figure 3-2 shows how the factory
default value of 400 (octal) is set for the A/D Done/DMA Done
interrupt.
3-4
UNPACKING AND CONFIGURATION
CONFIGURATION
4
1171:61151141:31121111:019 8
10 10 10 10 10 10 10 10 10 1 1
I
0
I
Always
I
0
ii
v
0
0
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W45 W44 W49 W48 W53 W52
12 11 10
0 0 0
1 1 1
I
I
Always 0
FIGURE 3-2: INTERRUPT VECTOR ADDRESS SELECTION OF 400 (OCTAL)
3.4
AID CONFIGURATION JUMPERING
This section describes how the user can select
configurations for the DT3362 series board.
3.4.1
various
analog
INPUT MODE
Not all DT3362 series models offer selection of the input mode.
Table 3-1 lists all the models and indicates those with
user-selectable input modes.
3-5
UNPACKING AND CONFIGURATION
A/D CONFIGURATION JUMPERING
TABLE 3-1: DT3362 SERIES INPUT MODES
A/D BOARD
USERSELECTABLE
FACTORY-SHIPPED
CONFIGURATION
I-
DT3362-16SE/SDI
DT3362-64SE/32DI
DT3362-16SE/SDI-PGH
DT3362-64SE/32DI-PGH
Yes
Yes
Yes
Yes
Differential
Differential
Differential
Differential
DT3362-F-16SE
DT3362-F-64SE
. DT3362-F-SDI
DT3362-F-32DI
No
No
No
No
Single-ended
Single-ended
Differential
DT3362-G-16SE
DT3362-G-64SE
DT3362-G-SDI
DT3362-G-32DI
No
No
No
No
Single-ended
Single-ended
Differential
Differential
DT3362-H-16SE
DT3362-H-64SE
DT3362-H-SDI
DT3362-H-32DI
No
No
No
No
Single-ended
Single-ended
Differential
Differential
DT3362-H-16SE-PGH
DT3362-H-64SE-PGH
DT3362-H-BDI-PGH
Single-ended
Single-ended
Differential
DT3362=H~32DI-PGH
No
No
No
No
DT3377
No
Differential
DT336S-4SE
DT336S-12SE
No
No
Single-ended
Single-ended
Differential
Differential
Table 3-2 gives the setting of jumpers for the selection of
single-ended or differential input mode on these boards. The
input modes of the other boards in the series are configured at
the factory and should not be tampered with.
3-6
UNPACKING AND CONFIGURATIO~
A/D CONFIGURATION JUMPERING
TABLE 3-2: INPUT MODE SELECTION FOR
DT3362-16SE/8DI, DT3362-64SE/32DI,
DT3362-16SE/8DI-PGH, AND DT3362-64SE/32DI-PGH
INPUT MODE
I
w14
TO
w15
w16
TO
TaY1
Q
ft"'''''
w4
TO
I:
... -,
__ 1
Y'lJ
WI
WJ.O
w23
TO
w24
In
Out
Out
Out Out
In
In
9.W
w6
TO
w14
TO
Single-ended
In
In
In
Differential
Out
Out
Out Out In
~
w3
TO
w4
wS
TO
w6
In
j
NOTES:
1. Jumpers connecting to w4 and w6 need only be installed
when the board has 64SE or 32DI channels. For boards
with 16SE or 8DI channels connections to w4 and w6 are
not required.
Similarly, those connections are not
made on the DT3377 and DT3368-4SE.
3.4.2
A/D INPUT RANGE
All DT3362 series boards except the DT3377 permit selection of
unipolar or bipolar input ranges. Unipolar input ranges accept
positive voltages only. They should be used with input levels
ranging from 0 to +1.2SV to 0 to +10V, depending on the board
model and gain setting of the A/D converter's instrumentation
amplifier.
with differential inputs the high and low ends can
be reversed for zero to negative value inputs.
Bipolar input ranges accept voltages which can be positive or
negative. They should be used with input levels from ±1.2SV to
±10V, again depending on the board model and gain setting of
the instrumentation amplifier.
Table 3-3 shows that all models of the DT3362 series except the
DT3377 have user-selectable input ranges. The factory-shipped
configuration of the input range is bipolar on all models.
3-7
UNPACKING AND CONFIGURATION
A/D CONFIGURATION JUMPERING
TABLE 3-3: DT3362 SERIES INPUT RANGES
USERSELECTABLE
FACTORY-SHIPPED
CONFIGURATION
DT3362-16SE/SDI
DT3362-64SE/32DI
DT3362-16SE/SDI-PGH
DT3362-64SE/32DI-PGH
Yes
Yes
Yes
Yes
Bipolar
Bipolar
Bipolar
Bipolar
DT3362-F-16SE
DT3362-F-64SE
DT3362-F-SDI
Bipolar
Bipolar
Bipolar
DT3362~F-32DI
Yes
.Yes
Yes
Yes
DT3362-G-16SE
DT3362-G-64SE
DT3362-G-SDI
DT3362-G-32DI
Yes
Yes
Yes
Yes
Bipolar
Bipolar
Bipolar
Bipolar
DT3362-H-16SE
DT3362-H-64SE
DT3362-H-SDI
DT3362-H-32DI
Yes
Yes
Yes
Yes
Bipolar
Bipolar
Bipolar
Bipolar
DT3362-H-16SE-PGH
DT3362-H-64SE-PGH
DT3362-H-SDI-PGH
DT3362-H-32DI-PGH
Yes
Yes
Yes
Bipolar
Bipolar
Bipolar
Yes
- - t ' .... - .... -
DT3377
No
Bipolar
DT336S-4SE
DT336S-12SE
Yes
Yes
Bipolar
Bipolar
A/D BOARD
Bipolar
Rinnl.::ar
Table 3-4 indicates which jumpers on the DT3362 series should
be installed and removed to set the board for unipolar or
bipolar operation.
3-8
UNPACKING AND CONFIGURATIO
AID CONFIGURATION JUMPERIN
TABLE 3-4: INPUT RANGE SELECTION
A. DT3362-16SE/8DI, DT3362-64SE/32DI,
DT3362-16SE/8DI-PGH,
DT3362-64SE/32DI-PGH.
INPUT RANGE
W26
W13
W12
Unipolar
Out
In
In
Bipolar (Fe)
In
In
B. DT3362-F-16SE, DT3362-F-64SE,
DT3362-F-8DI, DT3362-F-32DI,
DT3362-G-16SE, DT3362-G-64SE,
DT3362-G-8DI, DT3362-G-32DI,
DT3362-H-16SE, DT3362-H-64SE,
DT3362-H-8DI, DT3362-H-32DI,
DT3362-H-16SE-PGH, DT3362-H-64SE-PGH
DT3362-H-8DI-PGH, DT3362-H-32DI-PGH
INPUT RANGE
W26
Bipolar (FC)
W13
W12
1"\.....
VUI..
T_
I"'\ ...
In
Out
Out
J.U
~
VUI..
C. DT3368-4SE and DT3368-12SE.
INPUT RANGE
W26
W13
W12
Unipolar
Out
In
In
Bipolar (FC)
In
In
Out
NOTES:
1.
The input range of the DT3377
is
bipolar and not user-selectable.
2.
FC is factory configuration.
3.
If the programmable gain is used,
the
actual
input
range
will be the
indicated range divided by the gain.
NOTE
The AID module on the 03362 series board should
be recalibrated whenever the input polarity is
changed.
3-9
UNPACKING AND CONFIGURATION
AID CONFIGURATION JUMPERING
3.4.3
SELECTION OF OUTPUT CODING
At the end of an AID conversion, the incoming analog input
signal has been changed into an equivalent digital output which
permits analog input information to
be
understood
and
manipulated by the Q-bus master.
The output of the DT3362
series board is a binary data word, the coding of which depends
on the converter module and board jumpering.
With unipolar input ranges straight binary output code should
be used.
Digital outputs for bipolar input ranges can be
represented using either offset binary or two's complement
binary coding.
Table 3-5 shows which codes are available on
which is the factory-shipped configuration.
3-10
each
model,
and
UNPACKING AND CONFIGURATION
AjD CONFIGURATION JUMPERING
TABLE 3-5: DT3362 SERIES OUTPUT CODES
AjD BOARD ( 1 )
OUTPUT CODE
DT3362-16SEj8DI
DT3362-64SEj32DI
Straight Binary
Offset Binary
Two's Complement (FC)
DT3362-16SEjSDI-PGH
DT3362-64SEj32DI-PGH
Straight Binary
Offset Binary
Two's Ccmplement (FC)
DT3362-F-16SE
DT3362-F-64SE
DT3362-F-SDI
DT3362-F-32DI
Straight Binary
Offset Binary
Two's Complement (FC)
DT3362-G-16SE
DT3362-G-64SE
DT3362-G-SDI
DT3362-G-32DI
Straight Binary
Offset Binary
Two's Complement (FC)
DT3362-H-16SE
DT3362-H-64SE
DT3362-H-SDI
DT3362-H-32DI
Straight Binary
Offset Binary
Two's Complement (FC)
DT3362-H-16SE-PGH
DT3362-H-64SE-PGH
DT3362-H-SDI-PGH
DT3362-H-32DI-PGH
Straight Binary
Offset Binary
Two's Complement (FC)
DT3377
Two's Complement
DT336S-4SE
DT336S-12SE
Straight Binary
Offset Binary
Two's
~l"\m"",,'cmcT'lr
....... ....,01. .... t' ..................... '""'
(Fe)
NOTE:
1.
FC is factory configuration.
Table 3-6 indicates the jumper configuration required to select
straight binary, offset binary,
or two's complement binary
coding.
3-11
UNPACKING AND CONFIGURATION
AID CONFIGURATION JUMPERING
TABLE 3-6: SELECTION OF DATA CODING
CODING
W37
W38
W28
W27
Two's Complement (FC)
In
Out
Out
In
Binary
Out
In
In
Out
Offset Binary
Out
In
In
Out
NOTES:
1. FC is factory configuration.
2. Output coding is two's complement for DT3377.
NOTE
The output coding and the input polarity (see
previous section) selected on the AID board
should be mutually compatible.
Offset binary
or two's complement binary output coding should
be selected for bipolar inputs, and straight
binary output coding for unipolar inputs.
3~4~3.1
Input Gain And AID Ranqe
The input range which the module will accept depends on the
gain setting of the programmable gain amplifier.
It can thus
extend from 0 to +1.2SV to 0 to +10V for unipolar ranges, and
from ±1.2SV to ±10V for bipolar ranges. The actual input
voltage range, however, depends on the resolution and the gain
of the instrumentation amplifier.
The actual full scale
voltage range is the lowest voltage which will produce the
highest digital value in the selected output code.
For all
models of the DT3362 series except the DT3377 the output code
is 12 bits wide. The maximum output of the AID converters on
these boards is all ones in straight binary or offset binary,
and zero followed by all ones in two's complement. This output
is zero followed by all one's for the DT3377 which is set for
two's complement output coding.
In all cases, the maximum
output corresponds to a reading of full scale voltage minus 1
LSB (least significant bit).
Increasing the input voltage
beyond the actual full scale input voltage will not result in a
change to the digital code output from the AID converter.
Table 3-7 gives the codes for full scale outputs in three
notations for all DT3362 series boards.
3-12
UNPACKING AND CONFIGURATION
AID CONFIGURATION JUMPERING
TABLE 3-7: FULL SCALE OUTPUT CODES IN VARIOUS NOTATIONS
FULL SCALE OUTPUT CODE
BINARY
OCTAL
OUTPUT NOTATION
0000 1111 1111 1111
1 1 1 1
1 1 1 1 1111
...........
UUUU .L.L.L •
0000 0111 1111 1111
0111 1111 1111 1111
Straight Binary (12-Bits)
Offset Binary (12-Bits)
Two's Complement (12-Bits)
Two'S Complement (16-Bits)
007777
007777
003777
077777
1'\1'\1'\1'\
Table 3-8 gives the actual full scale inputs
gains at 12-bit and 16-bit resolutions.
for
the
various
TABLE 3-8: FULL SCALE RANGES FOR
HIGH LEVEL INPUT BOARDS
GAIN
INPUT RANGE.
IACTUAL FULL SCALE INPUT
16 BITS
12 BITS
I
Unipolar
1'\
u
2
4
8
1
2
4
8
3.4.4
to
.1
n
T.LV
uv
0 to + 5
V
0 to + 2.5 V
0 to + 1.25V
Bipolar
±10
V
± 5
V
± 2.5 V
± 1.25 V
+9.9976
V
Not
+4.9988 V
+2.4994 V
+1.2497 V
Applicable
+9.9951
+4.9976
+2.4988
+1.2494
+9.99970
+4.99985
+2.49992
+1.24996
V
V
V
V
V
V
V
V
JUMPER CONFIGURATIONS ON 22-BIT DMA ADDRESS BOARD
The 22-bit DMA addressing is implemented on Revision F and
higher
revision
boards.
Unless
otherwise
noted,
the
discussions in sections 3.4.5.1, 3.4.5.2, and 3.4.5.3. pertain
to those boards only.
3.4.4.1
Selection Of DMA Wrap Mode
The wrap mode refers to the operation of the six most
significant bits of the 22-bit DMA current address.
In the
wrap mode these bits are static and the DMA "wraps" to the
beginning of the 64Kbyte segment when the lower bits overflow.
In the non-wrap mode,
the upper bits are dynamic and the
overflow from the lower 16 bits causes the upper six bits to
increment. The wrap mode is selected by removing W58,
the
3-13
UNPACKING AND CONFIGURATION
A/D CONFIGURATION JUMPERING
non-wrap
3-9.
mode
is selected by installing W58 as shown in Table
NOTE
To avoid
possible
complications,
it
is
recommended that the first and last 64Kbyte
segments of memory not be used.
The first
segment contains the vectors and the stack, and
the last segment contains the I/O page, whereas
all locations are available on all other memory
segments.
TABLE 3-9: DMA WRAP MODE SELECTION
DMA ADDRESS MODE
JUMPER w58
Wrap
No-wrap (FC)
Out
In
NOTE:
1. FC is factory configuration.
3.4.4.1.1
Selection Of 22-bit DMA Addressing
The 22-bit addressing feature of the Revision F and higher
revision boards is selected by configuring jumpers w59 and W60
as shown in Table 3-10.
TABLE 3-10: SELECTION OF DMA ADDRESSING
DMA ADDRESSING
22-bit
18-bit (FC)
3.4.4.2
JUMPERS
w59
W60
In
Out
Out
In
Triggers
In most applications;
the trigger required by
the
A/D
converters on the DT3362 series boards will be provided by the
Data Translation DT2769 clock board.
with the
standard
versions of the A/D boards, cable EP140 is used to connect
jumper post w8 on the DT3362 series with the CLK OVFL pin on
the DT2769.
3-14
UNPACKING AND CONFIGURATIOr
AID CONFIGURATION JUMPERIN(
When the LDT verSlons of the AID boards (LDT3362 and LDT3368)
are used, jumper post w8 must be connected to jumper post w9,
and the user must connect the CLK OVFL BNC connector on the
DT2769 front panel with the EXT TRIG L BNC connector on the
DT3362 series board's front panel.
To use an external clock source, connect jumper post w8 to w9.
The external trigger should be connected to pin 19 of connector
J3. The section on the external trigger in Chapter 2 gives
complete electrical specifications for the external trigger
input:
3.4.4.3
Reference Jumpers
Table 3-11 gives a list of jumpers on the etch Revision F
later boards which are set in the factory and are
user-configurable.
and
not
TABLE 3-11: REFERENCE JUMPERS
FOR REVISION F AND LATER BOARDS
JUMPER
CONFIGURATION
W1*
W2*
W54
W55
W56
W57
In
Out
In
Out
In
Out
NOTE:
1. The
asterisked
jumpers
are
present on etch revision E and F
boards.
A set of jumpers are configured in the factory for all models
of the DT3362 series and are not configurable by the user. The
configurations of these jumpers are given in Table 3-12.
See
Appendix A for a complete list of all jumpers and their
configurations on the DT3362 series board.
3-15
UNPACKING AND CONFIGURATION
AID CONFIGURATION JUMPERING
TABLE 3-12: REFERENCE JUMPERS FOR ALL MODELS
REFERENCE JUMPER
CONFIGURATION
Out
In
In
In
Out
In
Out
Out
Out
W25
W29
W30
W31
W32
W33
W34
W35
W36
3-16
CHAPTER 4
SYSTEM INTERCONNECTIONS
4.1
INTRODUCTION
This chapter describes the connections of the DT3362 series
board
to
the processing host computer system and data
acquisition accessories. The connection to the host computer
system is made by plugging directly into the edge connector of
the Q-bus computer's backplane.
Connection to the
data
acquisition
accessories--screw terminal/signal conditioning
panels--is made with appropriate cable assemblies.
4.2
ANALOG INPUT CONNECTIONS
All connections between the DT3362 series board and the analog
signal input points such as barrier terminals on a screw
terminal panel are made using connectors J3 and J2.
J3 is a
20-pin header which connects the board to a compatible data
acquisition accessory_ J2 is a 50-pin header which is present
on the expanded versions of the DT3362 series and performs the
same function as J3. Basic versions of the DT3362 series use
only connector J3 to connect to analog input channels, while
the expanded versions use both J3 and J2 connectors.
4.2.1
J3 AND J2 CONNECTIONS ON DT3362- PREFIXED MODELS
Tables 4-1 and 4-2 show the pin assignments of the J3 and J2
connectors on models of the DT3362 series prefixed with
DT3362-.
4-1
SYSTEM INTERCONNECTIONS
ANALOG INPUT CONNECTIONS
TABLE 4-1: J3 PIN ASSIGNMENTS
ON ALL DT3362- PREFIXED MODELS
SIGNAL NAME
I
CHO
CH1
CH2
CH3
CH4
CHS
CH6
CH7
A GND
EXT. TRIG L
PIN
1
3
S
7
9
11
13
1S
17
19
SIGNAL NAME
2
4
6
8
10
12
14
16
I 1820
CH8/RETO
CH9/RET1
CH10/RET2
CH11/RET3
CH12/RET4
CH13/RETS
CH14/RET6
CH1S/RET7
AMP IN
D GND
NOTES:
1. The channel numbers listed first
are
single-ended.
The differential channels
are listed second.
2. Tie all unused analog inputs to A GND.
4-2
SYSTEM INTERCONNECTIONS
ANALOG INPUT CONNECTIONS
TABLE 4-2: J2 EXPANDER PIN ASSIGNMENTS
ON DT3362- PREFIXED MODELS
SIGNAL NAME
CH24/RET8
CH25/RET9
CH26/RETI0
CH27/RETII
CH28/RETI2
,..u")n ...... ?!I""1
PIN
1
2
3
5
7
4
6
8
10
....9
L\!:o J. J..J
""
.L~
CH30/RETI4
CH31/RETI5
CH40/RETI6
CH4l/RETI7
CH42/RETI8
CH43/RETI9
CH44/RET20
CH45/RET21
CH46/RET22
CH47/RET23
CH56/RET24
CH57/RET25
CH58/RET26
CH59/RET27
CH60/RET28
CH61/RET29
CH62/RET30
CH63/RET31
A GND
13
15
17
19
21
23
25
27
29
31
33
35
37
\.on", J /
SIGNAL NAME
I
i.G
14
16
18
20
22
24
26
28
30
32
34
36
38
39
40
41
43
45
47
49
42
44
46
48
50
CHI6/CH8
CHI7/CH9
CHI8/CHI0
CHI9/CHII
CH20/CHI2
CH21/CH13
CH22/CHI4
CH23/CHI5
CH32/CHI6
CH33/CHI7
CH34/CHI8
CH35/CHI9
CH36/CH20
CH37/CH2I
CH38/CH22
CH39/CH23
CH48/CH24
CH49/CH25
CH50/CH26
CH5I/CH27
CH52/CH28
CH53/CH29
CH54/CH30
CH55/CH31
A GND
NOTES:
1. The channel numbers
listed
first
are
single-ended. The differential channels are
listed second.
2.
Tie all unused analog inputs to A GND.
4.2.2
J3 CONNECTION ON DT3377
Table 4-3 shows the pin assignments of the J3 connector on
DT3377 board.
4-3
the
SYSTEM INTERCONNECTIONS
ANALOG INPUT CONNECTIONS
TABLE 4-3: J3 PIN ASSIGNMENTS ON DT3377
SIGNAL NAME
CHO
NC
CH1
NC
CH2
NC
CH3
NC
A GND
EXT. TRIG L
PIN
1
3
5
7
9
11
13
15
17
19
SIGNAL NAME
2
4
6
8
10
12
14
16
18
20
CHO Return
NC
CH1 Return
NC
CH2 Return
NC
CH3 Return
NC
NC
o GND
NOTES:
1. NC = No Connection.
2.
Tie all unused analog inputs to A GND.
4.2.3
J3 AND J2 CONNECTIONS ON DT3368- PREFIXED MODELS
Tables 4-4 and 4-5 show Lne pin assignments or ~ne J3 and J~
connectors on the basic and expanded versions of the DT3368-4SE
and DT3368-12SE models.
TABLE 4-4: J3 PIN ASSIGNMENTS ON
DT3368-4SE AND DT3368-12SE
SIGNAL NAME
CHO
NC
CH1
NC
CH2
NC
CH3
NC
A GND
EXT. TRIG L
PIN
SIGNAL NAME
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
A GND
NC
A GND
NC
A GND
NC
A GND
NC
NC
D GND
NOTES:
1. NC = No Connection.
2. Tie all unused analog inputs to A GND.
4-4
SYSTEM INTERCONNECTIONS
ANALOG INPUT CONNECTIONS
TABLE
4-5: J2 EXPANDER PIN ASSIGNMENTS
ON DT3368-12SE
SIGNAL NAME
A GND
NC
NC
A GND
NC
NC
A GND
NC
NC
A GND
NC
NC
A GND
NC
NC
A GND
NC
NC
A GND
NC
NC
A GND
NC
NC
A GND
PIN
1
3
5
7
9
1 1
J..J..
SIGNAL NAME
2
4
6
8
10
I
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
CH 4
NC
NC
CH 5
NC
~
.,.TI'"
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
CH
NC
NC
CH
NC
NC
CH
NC
NC
CH
NC
NC
CH
1
J..':'
!'ll...
6
7
8
9
10
NC
NC
CH 11
NC
NC
A GND
NOTES:
1.
NC = No Connection.
2.
Tie all unused analog inputs to A GND.
4.3
EXTERNAL PORT CONNECTION
The DT3362 series board uses the 26-pin header J1 connector
to
mate with the DT3369 dual port memory device via the External
Port.
The pin assignments of the Jl
connector are given in
Table 4-6.
4-5
SYSTEM INTERCONNECTIONS
EXTERNAL PORT CONNECTION
TABLE 4-6: EXTERNAL PORT CONNECTOR Jl
PIN ASSIGNMENTS
SIGNAL NAME
PIN
MEM OAT 0
MEM OAT 2
MEM OAT 4
MEM OAT 6
MEM OAT 8
MEM OAT 10
MEM OAT 12
MEM OAT 14
MEM REPLY L
WRITE L
REAO L
LAST TRANS L
REAOY L
4.4
1
3
5
7
9
11
13
15
17
19
21
23
25
SIGNAL NAME
MEM OAT
MEM OAT
MEM OAT
MEM OAT
MEM OAT
MEM OAT
MEM OAT
MEM OAT
0 GNO
0 GNO
0 GNO
0 GNO
0 GNO
2
4
6
8
10
12
14
16
18
20
22
24
26
1
3
5
7
9
11
13
15
EXTERNAL TRIGGER INPUT
The external trigger
conversions
input
allows
the
user
to an external clock or event.
to
synchronize
The input requires
a TTL-compatible signal and initiates conversions on the
high-to-Iow transition of the signal. The duty cycle of the
signal is not critical.
The Oata Translation OT2769 Real-Time Clock is a possible
source of trigger inputs.
This is a software programmable
clock for the Q-bus whose output can be used to time precise
intervals between conversions. Refer to Section 3.4.6, "Using
an External Trigger", for the jumper configuration required
when using the external trigger.
4.5
CONNECTIONS TO OATA ACQUISITION ACCESSORIES
Connections to compatible data acquisition accessories are made
via the J3 connector for the non-expanded boards, and via J2
and J3 connectors on the expanded versions. The A/O expander
accommodates three compatible screw terminal panels.
The
connection to the expander requires the EP164 interconnection
panel.
4-6
SYSTEM INTERCONNECTIONS
CONNECTIONS TO DATA ACQUISITION ACCESSORIES
The screw terminal panels compatible
include the following:
1.
DT701-20
2.
DT701-50
3.
DT709 series
4.
DT756 series
5.
DT750/DT6700 series
with
the
DT3362
series
Figures 4-1 through 4-6 illustrate the connections of the
compatible screw terminal panels to the DT3362 series boards.
Figure 4-1 shows the connection of the DT701-20 and DT701-50 to
the DT3362 series boards.
~
0T701-20
DT3362-
64SE/32DI
(BASIC MODEL)
(EXPANJEA)
-.Ii
DT701-50
FIGURE 4-1: CONNECTION OF DT701-20 AND
TO DT3362 SERIES BOARDS
...... "".., 1'\ 1
1) .~.
I U J. -
~ t'\
:>
U
Figure 4-2 shows the connection of the DT709 series and the
DT6700 series screw terminal panels to single-ended versions of
the DT3362 series boards.
4-7
SYSTEM INTERCONNECTIONS
CONNECTIONS TO DATA ACQUISITION ACCESSORIES
DT709
SERIES
DT750/
DT6700
SERIES
J3 ALL SE
MODELS OF
DT3362 SERIES
J2
TPCOO048
FIGURE 4-2: CONNECTION OF DT709 SERIES AND DT6700 SERIES
TO SE VERSIONS OF THE DT3362 SERIES BOARDS
Figure 4-3 shows the connection of
single-ended
versions
of
the
DT3368-4SE and DT3368-12SE.
the DT756 series to
DT3362 series except
all
the
3 ALL SE
J MODELS OF
DT3362 SERIES
EXCEPT
DT3368-4SE
J2 AND
DT3368-12SE
DT756
SERIES
FIGURE 4-3: CONNECTION OF DT756 SERIES WITH SE VERSIONS
OF THE DT3362 SERIES EXCEPT DT3368-4SE AND DT3368-12SE
Figure 4-4 shows the connection of three screw terminal panels
to the AID expander of the DT3362 series via the EP164
interconnection panel.
4-8
SYSTEM INTERCONNECTIONS
CONNECTIONS TO DATA ACQUISITION ACCESSORIES
01709 SERIES
OT756 SERIES
OT750/0T6700 SERIES
OT701-20
EP047
20-CONOUCTOR
0T709 SERIES
OT756 SERIES
OT750/0T6700 SERIES
OT701-20
EP047
20-CONOUCTOR
J2
OT709 SERIES
OT756 SERIES
OT750/0T6700 SERIES
OT701-20
EP047
20-CONOUCTOR
J3
J1
EP164
J
TO OT3362 SERIES J2
EP035. 50-CONDUCTOR
TPCOOO48
FIGURE 4-4: CONNECTION OF SCREW TERMINAL PANELS
TO THE AjD EXPANDER OF THE DT3362 SERIES
4.6
RECOMMENDED ANALOG INPUT CONNECTION SCHEMES
This section describes analog input connection schemes to the
DT3362 series AjD boards. Each connection scheme is discussed
separately, with a diagram representing the connection.
Input
modes possible with each model of the DT3362 series are
indicated in Table 4-7.
4-9
SYSTEM INTERCONNECTIONS
RECOMMENDED ANALOG INPUT CONNECTION SCHEMES
TABLE 4-7: DT3362 SERIES INPUT MODES
INPUT MODE
SE
MODEL
PSEUDO01
01
DT3362-SDI/16SE
DT3362-320I/64SE
Yes
Yes
Yes
Yes
Yes
Yes
DT3362-SDI/16SE-PGH
DT3362-32DI/64SE-PGH
Yes
Yes
Yes
Yes
Yes
Yes
DT3362-F-SOI
DT3362-F-3201
DT3362-F-16SE
OT3362-F-64SE
No
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
No
No
OT3362-G-SDI
DT3362-G-32DI
DT3362-G-16SE
DT3362-G-64SE
No
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
No
No
DT3362-H-SDI
DT3362-H-32DI
DT3362-H-16SE
DT3362-H-64SE
No
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
No
No
DT3362-H-SDI-PGH
DT3362-H-32DI-PGH
DT3362-H-16SE-PGH
DT3362-H-64SE-PGH
No
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
No
No
DT3377
No
No
Yes
DT336S-4SE
DT336S-12SE
Yes
Yes
No
No
No
No
4-10
SYSTEM INTERCONNECTIONS
RECOMMENDED ANALOG INPUT CONNECTION SCHEMES
4.6.1
SINGLE-ENDED INPUTS
In single-ended connections, input signals have a common low
side which is connected to the Analog Ground (AGND, pin 17 of
J3, or pins 49 and 50 of J2). This connection scheme gives you
maximum
channel density.
The ma~~r d~~advantage of the
single-ended connection scheme ~5 ~nat ~ne instrumentation
amplifier does not provide common mode rejection of the input
signal, as it does in differential input connections.
The'
single-ended
connection
scheme
is
available on models
DT3362-16SE/8DI,
DT3362-64SE/32DI,
DT3362-16SE/8DI-PGH,
DT3362-64SE/32DI-PGH,
DT3362-F-16SE,
DT3362-F-64SE,
DT3362-G-16SE, DT3362-G-64SE, DT3362-H-16SE,
DT3362-H-64SE,
DT3362-H-16SE-PGH,
DT3362-H-64SE-PGH,
DT3368-4SE,
and
DT3368-12SE. Figure 4-5 shows how to connect single-ended
inputs to these boards.
NOTE
When operating in this input scheme,
the user
should always reference Amp Lo (AMP IN) to
Analog Ground.
This
is
accomplished
by
connecting Amp Lo to Analog Ground (pin 18 to
pin 17 of the J3 connector). Failure to do so
will result in inaccurate data conversions. In
expanded versions, Amp Lo is tied only on the
J3 connector.
The DT3368-4SE and DT3368-12SE
have no Amp Lo connection. In both cases the
return point of each channel should be tied
directly to Analog Ground.
Single-ended inputs should be restricted to short lead
(less than 15 feet) and gains less than 10.
4-11
lengths
SYSTEM INTERCONNECTIONS
RECOMMENDED ANALOG INPUT CONNECTION SCHEMES
Pin 1
V1~_
16 ',
.
I
-----~~----~-----1~8~Or------~~
AGNO
TPC00027
ALL MODELS EXCEPT DT3368-4SE AND DT3368-12SE
11~-~
Pin
"1
i
17
TPC00013
MODELS DT3368-4SE AND DT3368-12SE
NOTES:
1.
2.
All signal inputs must be referenced to Analog Ground.
All unused analog input channels should be connected to
Analog Ground.
Failure to do so can result in inaccurate
AID conversions on all other channels, those closest to the
floating channel(s) being affected most.
FIGURE 4-5: SINGLE-ENDED INPUT CONNECTION
4-12
SYSTEM INTERCONNECTION~
RECOMMENDED ANALOG INPUT CONNECTION SCHEME~
4.6.2
PSEUDO-DIFFERENTIAL INPUTS
The pseudo-differential input
is
a
variation
of
the
single-ended input which provides the user with some degree of
common mode noise rejection without sacrificing the number of
input channels. To implement this input mode, the user jumpers
the board for single-ended inputs and ties all the return sides
of
the
single=ended
inputs
to
the low side of the
instrumentation amplifier (Amp Lo). This is possible if the
Amp Lo connection is brought out to the user input connector,
such as a screw terminal panel. Amp Lo in turn is connected
externally to Analog Ground via i to 10 kilohm resistor.
In
this manner the input instrumentation amplifier can reject the
common mode noise.
Figure 4-6 shows how to connect the Amp Lo
(AMP IN) and AGND pin for pseudo-differential operation.
NOTE
The pseudo-differential input scheme can be
applied only to channels served by the J3
connector on DT3362-16SE/8DI, DT3362-64SE/32DI,
DT3362-16SE/8DI-PGH,
DT3362-64SE/32DI-PGH,
DT3362-F-16SE, DT3362-F-64SE,
DT3362-G-16SE,
DT3362-G-64SE,
DT3362-H-16SE, DT3362-H-64SE,
DT3362-H-16SE-PGH and DT3362-H-64SE-PGH~
It is
typically used with lead lengths not exceeding
25 feet and gains no more than 10.
Channels
served by the J2 connector cannot accommodate
pseudo-differential
connections
since
the
expansion module does not provide an Amp Lo pin
for connection of the return lines.
For the
same reason, the DT3368-4SE and DT3368-12SE do
not accommodate pseudo-differential connection
schemes.
4-13
SYSTEM INTERCONNECTIONS
RECOMMENDED ANALOG INPUT CONNECTION SCHEMES
Pin
1~
,
I
!,
.
I
I
I
I
I
:
,
I
I
I
AMP LOW
AGND
~
TPC00038
NOTES:
1.
2.
3.
All signal inputs must be referenced to Analog Ground.
All unused analog input channels should be connected to
Analog Ground.
Failure to do so can result in inaccurate
AID conversions on all other channels, those closest to the
floating channel(s) being affected most.
Rcm is user-supplied bias return resistor.
Its value is
typically between 1 and 10 kilohms.
FIGURE 4-6: PSEUDO-DIFFERENTIAL INPUT CONNECTION
4-14
SYSTEM INTERCONNECTIONS
RECOMMENDED ANALOG INPUT CONNECTION SCHEMES
4.6.3
DIFFERENTIAL INPUTS
In a differential input scheme, two multiplexer switches are
used on each channel. Thus the number of channels which can be
accommodated is cut in half. The benefits are that the common
mode voltages, that is, voltages common to both the high and
low side of an analog input, ~all be rejected
by
the
differential input instrumentation amplifier. This common mode
rejection results in a much quieter system.
This input
confiQuration can be used with inDut ranaes as low as lOmV full
scale-with twisted pair (low level) shielded--input cables.
Lead lengths may suit user requirements but should be kept as
short as possible.
NOTE
The low end of each differential input must be
referenced to Analog Ground. This can be done
by connecting a 1 to 10 kilohm resistor between
the low end of each differential input and
Analog Ground. If all inputs share a common
ground, a single 10 kilohm resistor can be
connected between the input signal common and
the board Analog Ground.
The DT3362 series boards which can be operated differentially
are
the
following:
DT3362-16SE/8DI,
DT3362-64SE/32DI,
DT3362-165E/8DI-PGH,
DT3362-64SE/32DI-PGH,
DT3362-F-8DI,
DT3362-F-32DI, DT3362-G-8DI, DT3362-G-32DI, and DT3377. Figure
4-7 shows how to connect a differential input.
4-15
SYSTEM INTERCONNECTIONS
RECOMMENDED ANALOG INPUT CONNECTION SCHEMES
RemO
VemO
17
TPC00039
NOTES:
1.
2.
3.
All signal inputs must be referenced to Analog Ground.
All unused analog input channels should be connected to
Analog Ground.
Failure to do so can result in inaccurate
AID conversions on all other channels, those closest to the
floating channel(s) being affected most.
Rcm is user-supplied bias return resistor.
Its value is
typically between 1 and 10 kilohm.
FIGURE 4-7: DIFFERENTIAL INPUT CONNECTION
4-16
SYSTEM INTERCONNECTION~
CONNECTION GUIDELINE~
4.7
CONNECTION GUIDELINES
To optimize the performance of a system,
certain guidelines
must be considered in connecting analog signals to the AID
board.
Following the guidelines and observing some precautions
will minimize the pickup of electrical noise.
4.7.1
TWISTED PAIR INPUT LINES
The effects of magnetic coupling on the input signals can be
reduced in differential input schemes by twisting the input
lines of the signal.
This is effective since the induced
voltages on the two lines are of opposite polarity and tend to
match, canceling out any common voltage.
This cable type
should not be used with single-ended inputs.
4.7.2
SHIELDED INPUT LINES
The effects of electrostatic coupling can be reduced by
shielding the input lines.
This becomes important if the
source has a high impedance. The shield should only be tied to
ground at the instrument end. This will prevent ground loop
currents.
4.7.3
INPUT SETTLING WITH HIGH SOURCE IMPEDANCE
Solid state multiplexers inject a small amount of charge into
the input lines when channels are switched.
This can cause a
transient error due to the input source impedance
time
constants.
All Data Translation A/D boards allow for input
settling upon new channel selection. The settling time varies
for the different systems available and is controlled by the
timing capacitor.
Normally, the control logic allows sufficient time for the
injected charge to settle to less than 1/2 LSB of error.
However, more time may be needed when the multiplexer is
switching
an
input channel with high source impedance,
particularly when large amounts of shunt capacitance exists in
the interconnection cables.
On 50kHz boards, for example,
source impedance/cable shunt capacitance products greater than
1 microsecond (1 kilohm-1000pF) should be avoided if less than
1/2 LSB error is desired.
Assuming a twisted pair cable
capacitance of 50pF/foot and 1 kilohm source impedance, this
condition restricts the cable length to a maximum of twenty
feet on 50kHz models.
Note also that settling error can be
minimized by increasing the internal time-out with an external
timing capacitor Ct (about 60pF/ps).
4-17
CHAPTER 5
ARCHITECTURE
5.1
INTRODUCTION
The high performance of the DT3362 series board is made
possible by certain structural and operational features built
into its
architecture.
These
include
the
registers,
multiplexer channel-list, external port for external dual port
memory access, and DMA transfer methods.
5.2
REGISTERS
The registers of the DT3362 series data acquisition systems are
designed to meet the requirements of standard DEC Q-bus
interfaces. They are structured around a Control and status
Register (see following section) for complete software control
of the AID conversion operations.
Table 5-1 summarizes the
registers on the DT3362 series boards. The term "Base" refers
to the device base address (see Section 3.2).
5-1
ARCHITECTURE
REGISTERS
TABLE 5-1: DT3362 SERIES REGISTER ASSIGNMENTS
REGISTER
ADDRESS
ACCESS
A/D Control Status
(ADCSR)
Base + 0
R/W: Byte
A/D Data Buffer
(ADBUF)
Base + 02
Read: Word
Channel-list
Programming (CLPR)
Base + 04
R/W: Byte
DMA Control Status
(DMACSR)
Base + 06
R/W: Byte
DMA Word Count
(DMAWCR)
Base + 10
R/W: Byte
DMA Address Counter
DMACAR
Base + 12
R/W: Byte
Reserved
Base + 14
Reserved
Base + 16
NOTE:
1. R/W is Read/Write.
5-2
ARCHITECTURE
REGISTERS
5.2.1
A/D CONTROL AND STATUS REGISTER
Address: Base + 0
Access: Read/Write
The AID Control and status Register (ADCSR) is a byte
read/write register which controls and monitors all
associated with the A/D converter subsystem. The ADCSR
in Figure 5-1. The functions of the bits are described
operable
activity
is shown
next.
Channel-list
Done
Control Instruction
Interrupt
Field (I2,Il,IO)
Enable
A/D
Error
Channel-list
~
R/W Control
I
I
Error
Interrupt
Enable -
I
A/D Done
Channel-list
Operation
Mode Field
(Ml,MO)
I
Channel-list
Page Select
Field (PI, PO)
FIGURE 5-1: ADCSR BIT FUNCTIONS
BIT FUNCTIONS
BIT 15 - A/D Error, Read/Write to zero
A 1 indicates the occurrence of one of
conditions:
the
following
error
1.
An attempt to start the converter with an external
trigger while the multiplexer is settling (trigger
overrun error).
2.
Any attempt to start the converter when
pipeline is full (data overrun error).
3.
End of the second conversion before the data from
previous conversion is read (overrun error).
the
data
the
This bit is cleared at initialization or by a write to zero
BIT 14
A 1
an
the
- Error Interrupt Enable, Read/Write
allows the setting of the error bit (bit 15) to generate
interrupt request to the CPU. This bit is controlled by
program. It is cleared at initialization.
5-3
ARCHITECTURE
REGISTERS
BITS 13-11 - Channel-List Control, Read/Write
This 3-bit instruction field is used to program the pointer
logic that is used to access the channel-list RAM (see
Section 5.3). It is valid only when mode 01 operation
(Program Enable Pointer Logic) is selected in the mode field
as described further below (bits 10, 9).
In mode 01
operation, the 3-bit instruction field has the functions
listed in Table 5-2. These three bits allow the user to
program
the channel-list address pointer.
Actual data
transfers are done through the high byte of the Base + 04
word location. An overview of the steps required to program
the pointer logic is given in Chapter 8.
TABLE 5-2: CHANNEL-LIST CONTROL INSTRUCTION FIELD
ADCSR 13 ADCSR 12 ADCSR 11
12
II
10
INSTRUCTION SELECTED
0
0
0
Write Control Register
0
0
1
Read Control Register
0
1
0
Read Final Address Pointer
n
v
..
1
.
1
R......... A
1
0
0
Reinitialize Counters
1
0
1
Load Current Address Pointer
1
1
0
Load Final Address Pointer
1
1
1
Not Used
I;Q,-,
C'''--._''-
o..1\,.Q.I.\,.
?t..::l,.::t ....
I""11. ...
,.
~'-''-''''~i;)i;)
n".:~~'"""' .....
.
v •.u\"~'"
BITS 10,9 - Channel-List Operation Mode, Read/Write
This 2-bit field specifies the particular operation required
of
the
channel-list
access counter logic.
The four
selectable operations are given below.
TABLE 5-3: CHANNEL-LIST OPERATION MODE FIELD
ADCSR 10
M1
ADCSR 9
MO
INSTRUCTION SELECTED
0
0
Enable Counters
0
1
Program Enable Counter Logic
1
0
Program Enable RAM File
1
1
Preload Multiplexer
5-4
ARCHITECTURE
REGISTERE
BIT 8 - Channel-list Read/Write Control, Read/Write
This bit specifies the type of programming operation to be
performed during either mode 1 or mode 2 of the channel-list
operation as defined by bits 10 and 9. A zero indicates a
read operation while a one indicates a write operation. This
bit is controlled by the program~
BIT 7 - AID Done, Read Only
When set indicates the completion of an AID conversion.
It
is cleared when the AID data buffer is read. This hit is
initialized to zero.
BIT 6 - Done Interrupt Enable, Read/Write
A 1 allows the setting of the AID Done bit (ADCSR bit 7) or
the DMA Done bit (DMACSR bit 7) to generate an interrupt
request to the Q-bus cpu. This bit is controlled by the
program. It is initialized to zero.
BITS 5,4 - Not Used
These bits are not used and read back as zero.
BIT 3 - External Trigger Enable, Read/Write
A 1 enables the TTL compatible signal applied to the External
Trigger input line to initiate device activity (single
conversion for non-DMA; single conversion, List Scan, or
Burst for DMA. See Chapter 6) on a high to low transition of
the signal. When this bit is set, the Start bit (bit 0) is
disabled
from initiating board activity.
This bit is
controlled by the program. It is initialized to zero.
BITS 2:1 - Channel-list Page Select, Read/~rite
These two bits allow the user to access statically one of
four pages in the channel-list RAM. The user can prestore
four unique sampling schemes in the list, each up to 256
entries long.
At run time anyone of the four sampling
schemes may be selected. Table 5=4 summariZeS the usage of
these bits.
5-5
ARCHITECTURE
REGISTERS
TABLE 5-4: CHANNEL-LIST PAGE SELECT
ADCSR 2
PI
ADCSR 1
PO
INSTRUCTION SELECTED
0
0
Select Page 0
0
1
Select Page 1
1
0
Select Page 2
1
1
Select page 3
BIT 0 - Start, Read/Write
When set to 1, this bit initiates an A/D conversion in either
DMA or non-DMA operating modes. This software trigger should
be used only when the external trigger input is disabled.
This bit is cleared automatically by the hardware.
If
external trigger operation is enabled then setting this bit
will not initiate device activity and the bit will read back
as 1. When this happens, you must write this bit back to a
zero
before clearing the external trigger enable bit.
Failure to use the bit in this specified way could cause an
extraneous
A/D
conversion
to be made.
This bit is
initialized to zero.
5.2.2
A/D DATA BUFFER REGISTER
Address: Base + 02
Access: Read Only
The A/D Data Buffer Register (ADBUF) is a word operable read
only register used to read A/D data for non-DMA operating modes.
This 16-bit register is the second stage in the data pipeline
and contains the next converted value to be read. Whenever this
register is updated with new data from the A/D converter,
the
A/D Done bit (ADCSR bit 7) sets. A read of this register causes
the A/D Done bit to be cleared indicating that the data has been
transferred out by the cPU.
5.2.3
CHANNEL-LIST PROGRAMMING REGISTER
Address: Base + 04
Access: Read/Write
The Channel-list Programming Register
(CLPR)
is an indirect
sub-data bus used for all data I/O operations to the multiplexer
channel-list control logic. The register is divided into two
a-bit sub-busses used for I/O data to different portions of the
channel-list control logic.
Figure 5-2 summarizes the use of
5-6
ARCHITECTURE
REGISTERS
the CLPR for channel-list programming.
Gain
Channel Address
.l-,
i
,
I
Data
i
Used for
I/O to
8-bit Channel File
Counter Logic
Used for Data I/O to
8-bit Channel File
RA.."1
FIGURE 5-2: CLPR BIT FUNCTIONS
This register is used in conjunction with the upper byte of the
ADCSR which contains the channel-list operation control bitsa
The use of this register for different programming operations is
summarized in Table 5-5.
TABLE 5-5: MODE SELECTION USING CLPR
MODE SELECTED
OPERATION REQUIRED
AID
CLPR HIGH BYTE
CLPR I.DiI BYTE
Counter Enable
Active
Not used
Not used
Channel-list Addressing
Logic programming
Write to a specified
register
Data to be written
to selected register
Not used
Channel-list Addressing
Logic Programming
Read a selected
register
Data read back from
selected register
Not used
RAM Channel-list
Programming
Write mux addresses
sequentially into RAM
Not used
Data to be written
to RAM file
Channel~list Progr~~ing
Read contents of RAM
file for verification
Address of channel
being read from RAM
Contents of RAM file
location being r~ad
operations
5-7
5.2.4
DMA CONTROL AND STATUS REGISTER
Address: Base + 06
Access: Read/Write
All DMA related board activity on the DT3362 series is set up
and controlled by the software via the DMA Control and Status
Register (DMACSR). The DT3362 series can be used to perform DMA
transactions either over the Q-bus or to dual-ported memory.
The DMA data path to be used is selected through the DMACSR. It
should be noted that the two DMA operating modes are mutually
exclusive and both cannot be enabled together. If the software
attempts to enable both DMA options simultaneously, the hardware
will default to Q-bus DMA. The bits of the DMACSR are noted in
Figure 5-3.
A detailed discussion of the function of each bit
is given next.
Not Used
List Scan
Mode Enable
DMA Mode
Select
I
DMA
Error
II
i
I.-l-,
1151141131121111101 91 81 71 61 51 41 31 2111 01
I
Scan
Done
I I I i iDMA 17i 16
I
I
Done L,-..J
21 20 19 18
I
I
Upper Four Bits
of 22-bit DMA
Address
I
DMA
Address
Bits
I
Burst
Mode
Enable
FIGURE 5-3: DMACSR BIT FUNCTIONS
BIT 15 - Scan Done, Read only
This bit sets each time the channel-list completes a scan.
The
bit
resets
automatically
when
a
channel-list
initialization occurs from either the internal circuitry or
from a reinitialization command.
BITS 14-12 - Not used
These bits of the DMACSR are not used
readback.
Therefore,
the
state
indeterminate during read operations.
5-8
and
of
are .undriven
these
bits
on
is
ARCHITECTURE
REGISTERS
BITS 11-8 - 22-bit Address, Read/Write
These bits are used in conjunction with bits 5 and 4 (see the
following discussion) and the sixteen bits of the DMA Current
Address Register to generate a 22-bit DMA address.
Bit 11
corresponds to address bit 21, bit 10 to address bit 20, bit
9 to address bit 19, and bit 8 to address bit 18. These bits
a~e
ignored if the board is jumpered for la-bit
range (jumper W59 out, W60 in).
The bits are cleared on
initialization.
If DMA no-wrap mode is selected (jumper W58
is installed)
these bits increment whenever an overflow
occurs out of address bit 17.
BIT 7 - DMA Done, Read/Write
A 1 indicates the end of the current DMA operation. This bit
can be used by the software as required, or can be made to
interrupt via the Done interrupt logic. For this interrupt
to occur the Done interrupt enable bit of the ADCSR must also
be set. Note that the base interrupt vector associated with
this interface is shared by both the AjD Done bit and the DMA
Done bit. The hardware internally arbitrates the use of this
interrupt according to the following criteria:
1.
Interrupt to be used by AjD Done when interface is not
operating in any of the DMA modes.
2.
Interrupt to be used by the DMA Done when interface is
operating in one of the DMA modes. The AjD Done line
is inhibited from interrupting during DMA operation.
The DMA logic will end operation when a block of AjD data is
transferred to memory as specified. Any memory error during
DMA transfers aborts the DMA operation. If during the DMA
operation, a memory error of any sort occurs, then the DMA
operation will be aborted. This error condition sets the DMA
Done bit in addition to the DMA Error bit. This bit can be
written to zero by the program.
It is also cleared on
initialization.
BIT 6 - DMA Error, Read/Write to zero only
A 1 indicates that one of the two following types
errors has occurred:
of
memory
1.
Bus Time Out error when operating over the Q-bus.
This error indicates that non-existent memory has been
accessed over the Q-bus.
2.
Access error to the dual-ported memory board.
This
error occurs when the AjD board is enabled to transfer
data into the dual-port memory board, while the memory
board has not been enabled.
Setting this bit during a DMA transfer ~borts the remainder
of the transfer and sets the DMA Done bit. This bit can only
be written to zero by the program. It is also cleared on
initialization.
5-9
ARCHITECTURE
REGISTERS
BITS 5,4 - Q-bus Extended Address, Read/Write
This 2-bit field forms bits 16 and 17 of the address range on
all versions of the OT3362 series boards. The field is
dynamic in nature. If the no-wrap memory access mode is
selected (jumper W58 in), the value of the field increments
by one on each overflow of the OMA Current Address Register,
and access starts on the next 64 Kbyte memory segment. If
the wrap mode of memory access is selected, (jumper W58 out),
the field value remains static and the OMA address wraps back
to the beginning of the current 64 Kbyte segment following an
overflow of the OMA Current Address Register. These bits
have no effect on the LSI-11 and LSI-11/2 systems, but
provide 18-bit memory addressing capability in LSI-11/23
systems where the la-bit memory addressing feature has been
incorporated.
Bit 4 corresponds to address bit 16; bit 5 to
address bit 17. These bits controlled by the program.
They
are cleared on initialization.
BIT 3 - List Scan Mode Enable, Read/Write
A 1 allows the board to operate in List Scan mode during OMA
operation (see Section 6.4 for a description of the List Scan
mode). This bit and bit 2 (Burst mode enable) of the OMACSR
must not be high together. If they are both set high, one
disables the other, resulting in the deactivation of the
operation in both modes.
~n~s
D~~
is controlled by the
program. It is cleared on initialization.
BIT 2 Burst Mode Enable, Read/Write
When set this bit allows the board to operate in Burst mode
during OMA operation (see Section 6.4 for a description of
the List Scan mode). This bit and bit 3 (List Scan Mode
Enable) of the OMACSR must not be high together. If they are
both set high, one disables the other, resulting in the
deactivation of the operation in both modes. This bit is
controlled by the program. It is cleared on initialization.
BITS (1, 0) OMA Mode Select, Read/Write
This 2-bit field specifies the type of OMA activity required.
In essence these bits enable or disable the OMA logic and
select whether the OMA is to occur over the Q-bus or the
External Port. Table 5-6 summarizes the use of these bits.
5-10
ARCHITECTURE
REGISTER~
TABLE 5-6: DMA MODE SELECTION
DMACSR 1
DMACSR 0
DMA MODE DESCRIPTION
o
o
NOP DMA operation disabled.
Board to operate in programmed
I/O or interrupt mode.
o
1
Enable DMA operation to Q-bus.
1
o
Enable DMA operations to
Dual-ported memory.
1
1
Enable DMA operation to Q-bus.
5.2.5
DMA WORD COUNT REGISTER
Address: Base + 10
Access: Read/write
The DMA Word Count Register (DMAWCR) is a 16-bit read/write
register used only when a DMA transfer via the Q-bus is to be
performed. The register is loaded with the two's complement of
the number of data conversions, and is incremented after each
word transfer. The DMA operation is ended and a DMA Done
interrupt issued when this register increments to zero.
5.2.6
DMA CURRENT ADDRESS REGISTER
Address: Base + 12
Access: Read/Write
The DMA Current Address Register (DMACAR) is a 16-bit read/write
register that is used only when a DMA transfer via the Q-bus is
to be performed. In this operating mode this register is loaded
with the starting word address of the reserved memory buffer
into which the data is to be transferred and is incremented
after each word transfer, thus causing data to be stored in
memory sequentially and in ascending order.
5.3
MULTIPLEXER CHANNEL-LIST
The multiplexer channel-list is an on-board 1024x8 RAM which is
divided into four 256-byte pages. The processor uses each page
to store the channel numbers in the sequence in which they are
to be sampled.
The processor accesses all four pages of the
channel-list via two static page select bits in the ADCSR.
Therefore any sampling scheme may be up to 256 bytes long and
5-11
ARCHITECTURE
MULTIPLEXER CHANNEL-LIST
the processor can preload four different sampling
the list.
schemes
into
Access to the channel-list from both the processor and the
conversion logic is controlled via the 8-bit incrementable
Current Address Pointer which has an associated 8-bit Start
Address Register and an 8-bit Final Address Register. (These
two registers are selected via the channel-list instruction
field in the ADCSR and are accessed via the Channel-list
Programming Register as explained earlier in this chapter.) The
logic is designed such that the CPU can access the channel-list
only when the latter is inactive (when no conversions are in
progress).
When the device is active, the CPU is locked out
from channel-list access.
On all DT3362- prefixed models and DT3377, the 8-bit pointer
scheme for accessing the channel-list allows the processor to
set up the board to scan only as much of the channel-list,
within a 256 byte block, as is required during a certain
operation. The channel access pointer automatically increments
after each conversion until it matches the contents of the Final
Address Register. At that time it resets back to the value held
in the Start Address Register.
On DT3368-4SE and DT3368-12SE, the multiplexer channel-list
operates differently.
Here the channel-list can have any
sampling sequence but must always start with Channel O.
No
channel address can be repeated in the list. The channel
address pointer increments automatically
~frpr
each
AjD
conversion until it matches the contents of the Final Address
Register. At the end of the current scan, the multiplexer
returns to Channel 0, all channels are placed back in the sample
mode, and the operation is terminated until a new conversion
trigger is issued.
On boards equipped with a programmable gain, each byte stored in
the channel-list contains a 2-bit field which selects the gain
to be applied on the input.
5.4
ADDRESS POINTERS
The pointer logic of the DT3362 series board contains three
pointers which indicate channel addresses in a Channel-list Scan
operation. They are the Start Address Pointer, Current Address
Pointer, and Final Address Pointer.
The three pointers are
selected via the Channel-list Control instruction field in the
ADCSR (bits 11, 12, and 13).
The Start Address Pointer holds the starting channel address of
the current Channel-list scan.
The Current Address Pointer
indicates the address to be selected from the Channel-list for
the current AjD operation. The Final Address Pointer indicates
the last channel to be selected in the current AjD conversion
cycle.
The values stored in the starting Address Pointer and
the Final Address Pointer remain constant throughout the scan
5-12
ARCHITECTURE
ADDRESS POINTER~
operation, while the content of the Current Address Pointer
increments following completion of each AID conversion.
When
the content of the Current Address Pointer equals the value
stored in the Start Address Pointer, the Current Address Pointer
automatically resets (presets) to the value stored in the Start
Address Pointer. The Start Address Pointer and the Current
Address Pointer are each a-bit wide. They are loaded with a
single 16-bit word.
~.~
EXTERNAL PORT
As Figure 5-4 illustrates, the DT3362 series use the Q-bus
(system bus) for data transfers to system memory. This type of
conventional architecture places an additional burden on the
system since the data conversion subsystem must share the Q-bus
with other peripherals requesting service from the cpu.
Added
traffic on the Q-bus creates congestion and ultimately degrades
both the performance of the system with respect to other
peripherals
and throughput of the AID conversions.
This
situation may be permissible if high demands are not made of the
system.
For many applications requiring high throughputs,
however, latencies due to high traffic on the Q-bus could be
intolerable.
OT3362 SERIES
MEMORY BOARD
>
TPCOOO43
FIGURE 5-4: DATA PATH TAKEN BY CONVENTIONAL DMA TRANSFERS
The DT3362 series board features an External Port which is
designed to be used for data transfers external to the system
bus. A memory device used in conjunction with the External Port
appreciably alleviates congestion on the Q-bus. The DT3362
series board transfers conversion data to the memory via the
External Port which operates independently of the Q-bus. The
data is then transferred to a mass storage media via the Q-bus.
5-13
ARCHITECTURE
EXTERNAL PORT
In this type of architecture, data transfers occur over the
External Port without interrupting other activity on the Q-bus.
The External Port of the DT3362 series board can be linked to a
compatible external device such as the DT3369 dual-port memory
board or the SKY 320 signal processor. Architecture including
the DT3369 dual-port memory device, for instance, dramatically
enhances the throughput of the DT3362 series board as well as
the performance of other subsystems on the Q-bus.
Figure 5-5
shows the External Port in relation to the Q-bus. The following
two subsections describe the two devices, mentioned above, that
can be used with the DT3362 series board for high performance
applications.
AID DATA PATH
II
013369
OT3362 SERIES
16KWORO RAM
<~_G-BUS_>
TPC00044
FIGURE 5-5: DATA PATH TAKEN WITH DUAL-PORTED MEMORY STRUCTURE
5.5.1
DT3369 DUAL-PORT MEMORY
The DT3369 is a dual-port RAM board.
When combined with the
DT3362 series board, it changes drastically the architecture of
the data acquisition system. The dual-port memory board appears
to the data acquisition system as a standard memory subsystem,
but it is totally independent of the Q-bus.
One port of the
DT3369 communicates with the External Port on the DT3362 series,
the other with a mass storage peripheral over the Q-bus.
In
case of a simultaneous access requests to both ports of the
external dual port memory, the DT3369 on-board controller
5-14
ARCHITECTURE
EXTERNAL POR 1
resolves the conflict so that each side is transparent to the
other. The operation of the dual port external memory is
explained in Section 5.5.
5.5.2
SKY 320 SIGNAL PROCESSOR
The SKY 320 signal processor operates over the External Port in
the same manner as the DT3369 dual port memory board discussed
in the previous subsection.
Data is acquired by the A/D
subsystem and passed through directly to the signal processor
without flowing through the Q-bus or requiring the intervention
of the host processor. Thus the addition of the SKY 320 in the
I/O space of the system processor does not increase the activity
on the Q-bus, and, therefore, does not add to the bus latency of
the system.
5.6
DMA TRANSFERS
The DT3362 series boards contain circuitry which permits direct
data transfers between the board and the system memory without
the intervention of the cpu. This type of data transfer is
termed Direct Memory Access (DMA). If the D73362 series board
is operating by itself, then all DMA transfers are performed
over the Q-bus. However, if the DT3362 series board is used in
combination with the DT3369 external memory board, then DMA
transfers can take place over the External Port as well as the
Q-bus. This section explains how data transfer operations
differ on these two busses.
5.6.1
DMA TRANSFERS VIA Q-BUS
Data transfer via the Q-bus is the conventional DMA data path
for Q-bus peripherals and allows the DT3362 series boards to be
used by themselves as high speed data acquisition peripherals.
Since the Q-bus is the transmission medium for all data
transfers, it must arbitrate the transfer of data between the
A/D board and memory, the transfer of instructions from memory
to the CPU, and the transfer of blocks of data between memory
and the storage peripherals.
Time spent in arbitration can
significantly reduce the effective bandwidth of the processor
bus.
Furthermore, use of the Q-bus DMA means that during data output
all other bus related tasks and the CPU must be temporarily
halted. As the throughput requirements increase, the amount of
time the A/D peripheral spends on the bus increases and
therefore the bus free time decreases. The limit on throughput
is achieved when the bus free time goes to zero. At that point,
the bus is being used solely to transfer data between the A/D
board and memory. No other activity can be performed. In many
applications requiring large amounts of high speed data to be
collected, stored on disk, and played back, this architecture
can be limiting, as explained above.
The DT3369 dual-port
5-15
ARCHITECTURE
DMA TRANSFERS
external memory device relieves activity
maintains high performance of the system.
5.6.2
on
the
Q-bus and
DMA TRANSFERS VIA EXTERNAL PORT
The DT3362 series board contains circuitry that allows it to
link directly with one side (port) of the DT3369 dual-port
memory, creating a data bus which operates with complete
independence from the Q-bus (processor bus). On the other side,
the dual-port memory connects to the Q-bus and appears to the
processor as a standard memory su~system.
Moving data between the board and memory over the External Port
makes
data
acquisition
rates
independent of the Q-bus
arbitration latency or performance.
with the standard DMA
approach, data moves twice over the Q-bus: first, from AID to
memory, then from memory to disk.
with the
dual
port
architecture, the Q-bus is needed only to move data from memory
to disk. Thus an equivalent number of Q-bus transactions are
handled by the dual-port system with half the usual Q-bus
overhead.
The dual port memory subsystem is further enhanced by features
available on the DT3369 memory board. The on-board address
controller can direct the system to alternately lead data into
two separate sub-buffers on the DT3369 board. The filling of
each sub-buffer can interrupt the processor,
which
then
initiates a DMA transfer via Q-bus from memory to disk. While
one buffe~ is being emptied via Q-bus, the AID can continue to
fill the other buffer via the External Port. This process can
be continued indefinitely, achieving gap-free
acquisition,
limited only by the transfer rate and size of the disk.
5-16
CHAPTER 6
OPERATING PRINCIPLES
6.1
INTRODUCTION
The data acquisition and conversion operations on the DT3362
series boards go through three processes: 1) A/D conversion
trigger; 2) Data conversion; and 3) Data transfer.
This
chapter explains the various modes of operation which the user
can define for the board by appropriately selecting between
alternatives available for each of these three processes.
6.2
A/D CONVERSION TRIGGER
The DT3362 series boards initiate A/D conversions by a trigger
issued either via software (software trigger) or an external
source (external trigger). A software trigger is enabled when
bit 0 of the ADCSR is set while bit 3 of the ADCSR is clear.
Data conversion starts as soon as the ADCSR is written to.
An
external trigger is enabled by setting bit 3. The board then
waits for an external trigger source to
initiate
data
conversion.
Once enabled, any TTL-compatible pulse train can
be tied to the external trigger input
line
to
start
conversions.
On all models a single trigger activates A/D conversions in one
of three modes: Single-channel, List Scan, or Burst. In the
Single-channel mode a trigger is required for each conversion.
In the List Scan Mode the channels selected in the multiplexer
channel-list (see Section 5.3) are scanned and converted with
each trigger.
The process ends when the last channel in the
list is converted. In the Burst mode, the trigger sets off a
series of conversions. The operation ends when the number of
conversions equals the number specified in the DMA Word Count
Register. On all models except DT3368-4SE and DT3368-12SE, the
A/D module can sample any channel in any desired sequence.
On models DT3368-4SE and DT3368-12SE,
which
feature
a
simultaneous sample and hold A/D converter module, the sampling
scheme requires that Channel 0 be sampled first, followed by at
least one other channel.
No channel can be sampled twice
without Channel 0 being sampled in between.
The sequence of
events for the simultaneous sample and hold is given below.
6-1
OPERATING PRINCIPLES
A/D CONVERSION TRIGGER
When Channel 0 is triggered:
1.
All sample and hold circuits freeze and switch to the
mode.
hold
2.
The channel-list is scanned at
analog input to a digital value.
each
3.
The multiplexer switches back to zero, the first element in
the list.
4.
Switching to Channel 0 from some other channel causes all
sample and hold circuits to be unfrozen and go back to
sample (track) mode.
100kHz,
converting
The next occurrence of a trigger will repeat this cycle.
6.3
DATA TRANSFER
There are three modes of data transfer in a data acquisition
system based on the DT3362 series board and the DT3369
dual-port memory board: Programmed I/O, DMA transfer over the
Q-bus, and DMA transfer over the External Port. The data
transfer mode is selected by loading the appropriate value into
the DMA mode select field in the DMACSR (bits 1 and 0, see
Table 5-6).
In the programmed I/O mode; the CPU transfers each word of data
to the host memory. The CPU can poll the DT3362 series board
to determine
when
each
conversion
is
complete,
or,
alternatively, the board can be made to generate an interrupt
to the processor when a conversion is complete. The CPU then
reads the converted data and stores it in the memory.
In the Q-bus DMA mode, the starting address is loaded into the
DMACAR and the DMACSR. The two's complement of the number of
words to be transferred is loaded into the DMA Word Count
Register (DMAWCR). Each time a data word is transferred across
the bus, the DMAWCR and the DMACAR increment by one.When the
DMACAR reaches 0, the board sets the DMA Done bit and either
generates an interrupt or waits to be polled.
In the External Port DMA mode the number of words to be
transferred and the destination address are set by the device
at the other end of the External Port.
Data is transferred
only over the External Port.
Consult the DT3369 Dual-Port
memory user manual for additional information on data transfer
over the External Port.
6-2
OPERATING PRINCIPLE~
DATA CONVERSIOr6.4
DATA CONVERSION
Three modes of data conversion
are
available:
Single
Conversion per trigger, List Scan per trigger, and Burst
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The Single Conversion per trigger is set by clearing bits 2 and
3 in the DMACSR. In this mode, the board collects or writes
one data point for each trigger (software or external) issued.
After the data has been collected or output, the board waits
for another trigger to acquire another data point. The single
conversion triggers operate in both the programmed I/O and DMA
modes of data transfer.
The List Scan mode is selected by setting bit 3 in the DMACSR
while bit 2 is clear. Once the process has been initiated, the
board continues automatically to perform conversions until one
scan has been done.
A scan is defined as the channel-list
Current Address Pointer reaching the value stored in the Final
Address Register. When a scan is complete, the Current Address
Pointer resets to the value held in the Start Address Register
and the board waits for another software start or external
trigger. This process continues until the total number of
conversions specified have been taken. The List Scan mode is
only available with the DMA modes of data transfer.
The Burst Conversion mode is selected by setting bit 2 in the
DMACSR while bit 3 is clear. In this mode the board proceeds
to convert another data point as soon as the
previous
conversion is complete. Once the process has been initiated,
the channel-list is scanned repeatedly until the number of
words specified have been collected or written. The Burst
Conversion mode is available only with the DMA modes of data
transfer.
6-3
CHAPTER 7
CHANNEL-LIST PROGRAMMING
7.1
INTRODUCTION
The DT3362 series offers the user a sophisticated and highly
versatile scheme for defining the channels to be sampled. This
feature, called the multiplexer channel-list, allows you to
program into the interface the channel numbers in the order in
which they are to be sampled. Furthermore, the you can at any
time request that a smaller portion of the channel-list be
scanned.
On all models, the channel-list is organized as four pages of
256 bytes per page. Page selection is done by a 2-bit code in
the ADCSR. Within a given page you can access the 256 bytes
through the 8-bit pointer logic. Programming the channel-list
logic consists of programming the pointer logic to operate
within a specified starting and ending value, then loading the
channel number information into the on-board RAM.
The processor has read/write access to the RAM so that it can
load channel numbers to effect any desired sampling sequence
For models featuring the simultaneous sample and hold module
(DT3368-4SE and DT3368-12SE), however, the channel number
sequence has two restraints: 1) the list must always start
with Channel OJ 2) no channel can be converted more than once
at the end of the sample phase (selection of Channel 0). If a
channel is to be converted twice, then the module should be
placed in the sample mode after the first conversion by
selecting Channel O. This process acquires new analog data at
all the channels. A new conversion can now be performed on the
selected channel.
In the following subsections detailed descriptions of the
various programming steps required are presented.
Actual
programming of the interfaces then consists of assembling these
operations in the required sequence.
NOTE
In programming examples, it is the convention
in this manual to underline the code which
should be entered by the user.
7-1
CHANNEL-LIST PROGRAMMING
PROGRAMMING PROTOCOLS
7.2
PROGRAMMING PROTOCOLS
The following sections present
sequences
needed
to
program
channel-list and pointer logic.
7.2.1
the various protocols anp
the
on-board multiplexer
INITIALIZE POINTER LOGIC
Following a reset or power-up, the pointer logic for the
channel-list RAM has to be initialized before the board is
used. This initialization is performed as follows:
1:
Write 003 into the high byte of the
the write
selected.
2.
control
ADCSR.
This
selects
register function in mode 1 with write
write the initialization code 002 into
(high byte) of the CLPR (Base + 04).
the
pointer
field
A typical instruction sequence for initialization would be:
MOVS #3, @#ADCSR + 1
MOVB #2, @#CLPR + 1
If the programmer wishes to read back the initialization code
from the interface for diagnostic and testing purposes, the
following sequence is required:
1.
Write 012 into the high byte of the ADCSR.
2.
Read the high byte of the CLPR to
code from the interface.
programming sequence:
MOVB #12, @#ADCSR + 1
MOVB @iCLPR ~ 1, RO -
7-2
get
the
initialization
CHANNEL-LIST PROGRAMMING
PROGRAMMING PROTOCOLS
7.2.2
WRITE START ADDRESS REGISTER/CURRENT ADDRESS POINTER
The 8-bit Start Address Pointer is loaded in parallel with the
8-bit Current Address Pointer when the program explicitly
writes to the Current Address Pointer. After initial loading
the program can at any time reset the pointer to the value held
in the start Address Pointer by issuing a reinitialization
command to the pointer logic. The pointer will also be preset
to the value in the Start Address Pointer when the content of
the pointer become equal to the content of the Final Address
Pointer during an active data acquisition cycle. The sequence
required
to
write
a
value . into
the
Start Address
Pointer/Current Address Pointer is:
1.
Write 053 into the high byte of the ADCSR.
2.
Write the 8-bit value into the high byte of the CLPR.
Programming sequence:
Move #53, @#ADCSR + 1
MOVS #7, @#CLPR ~ I
This will initialize the pointer and preset to 7.
7.2.3
READ CURRENT ADDRESS POINTER
If during the data acquisition cycle the program must determine
the value of the pointer or must read, for a diagnostic test,
the value of the pointer after having written to it, the
following sequence is required:
1.
Write 032 into high byte of ADCSR
2.
Read contents of address pointer at high byte of CLPR
Programming sequence:
Mova
Mova
#32, @#ADCSR + 1
@lfCLPR ~ 1, RO
7-3
CHANNEL-LIST PROGRAMMING
PROGRAMMING PROTOCOLS
7.2.4
WRITING FINAL ADDRESS POINTER
The Final Address Pointer specifies the value at which the
Current Address Pointer should set itself back to the (initial)
value held in the Start Address Register.
The sequence
required to write a value into the Final Address Register is:
1.
write 063 into the high byte of the ADCSR.
2.
Write the desired value into the high byte of the CLPR.
Programming sequence:
MOVB #63, @#ADCSR + 1
MOVB #20, @#CLPR +-1-
111'h;
t!!
~""!!l_
.66 .............
.... 1
....._......... ,
o.oA .... ,t' .....
~
nvu ... u
, __
...:I
.I.vau
'-1.. _ _ _ _ _ 1..._ -
\..UC
l1UlllUt::'.L
.... "
~v
into the final address
register.
7.2.5
READING THE FINAL ADDRESS POINTER
For test, diagnostic,
and verification purposes,
the final
address register may have to be used. This read operation can
be performed with the following programming sequence:
1.
Write 022 into the high byte of the ADCSR.
2.
Read the value of the final address register
byte of the CLPR.
Programming sequence:
MOVB #22, @#ADCSR + 1
MOVB @iCLPR ± 1, RO -
7-4
at
the
high
CHANNEL-LIST PROGRAMMINC
PROGRAMMING PROTOCOLE
7.2.6
RESETTING THE POINTER
At certain times during the programming of the interface it may
be necessary to reset the Current Address Pointer to the value
held in the Start Address Register. This can be accomplished
easily using the pointer reinitialization command provided. To
perform this function the following sequence is required:
1.
Write 043 to the high byte of the ADCSR
2.
Perform a write operation to the high byte of the
Since data written is not used, it can be any value.
CLPR.
Programming sequence:
MOVB #43, @#ADCSR + 1
MOVB #O,"@#CLPR + r
7.3
ENTERING CHANNEL INFORMATION INTO THE RAM
The on-board channel-list is 8-bits wide to allow the user to
select anyone of 64 channels (0 to 63) which requires a 6-bit
-field, and associate with that channel a code for
the
programmable gain amplifier (PGH = 1,2,4,8) which requires a
2-bit field. An 8-bit entry in the channel-list is organized
as indicated in Figure 7-1:
MSB
LSB
4
I
PG Bits
3
2
I
Selects One of
64 Channels
FIGURE 7-1: FORMAT OF CHANNEL-LIST ENTRIES
The bits select one of four possible gains. If a PG option is
not installed, these bits are ignored. Gain selection is done
according to Table 7-1.
7-5
CHANNEL-LIST PROGRAMMING
ENTERING CHANNEL INFORMATION INTO THE RAM
TABLE 7-1: CHANNEL-LIST GAIN SELECTION
PG BIT 7
0
0
1
1
PG BIT 6
PGH GAIN
0
1
1
2
0
4
8
1
I
Each page of the channel-list is independent of the other
three.
Each has to be individually programmed by the user to
the required sampling scheme.
During
actual
conversion
operations, only one of the four pages as selected by the
two-bit field of the ADCSR is accessed through the pointer
logic. The user can program and read back for verification the
contents of the channel-list RAM by following the programming
sequence given in the ensuing two sections.
7.3.1
WRITING INTO THE CHANNEL-LIST RAM
Following initialization, you must first select which one of
four pages in the channel-list is to be operated on by writing
a two bit naae select code into bits 2
and
1
of
rhp
Anr.~R_
Then the c~a~nel~lisf p~i~ter-io~i~-m~st-~; s;t ~~ t~~-re~~i~;~
starting address and be told of the desired ending address.
The pointer logic points to the first location in RAM that is
to be loaded. The RAM accepts data for entry in the following
manner:
1.
Write a 005 into the high byte of the ADCSR.
2.
Write the sequence of channel numbers into the low byte
the CLPR.
of
Note that the pointer will be incremented after each write
operation to the low byte of the CLPR. Thus sequential writes
to the low byte of the CLPR will place data sequentially in the
channel-list.
This incrementing operation will proceed until
the value of the pointer becomes equal to the value held in the
final address register. A write operation performed after this
condition will set the pointer back to its initial value and
the channel-list buffer will be overwritten.
7-6
CHANNEL-LIST PROGRAMMINC
ENTERING CHANNEL INFORMATION INTO THE RA~
programming sequence:
MOV
MOVB
MOVB
MOVB
MOVB
#2400, @#ADCSR
#1, @#CLPR
#3, @#CLPR
~ @#CLPR
#7, @#CLPR
This example selects page 0 of the RAM and forces a list
programming operation. Then the odd channel numbers are stored
sequentially into the channel-list.
7.3.2
READING THE CHANNEL-LIST RAM
For diagnostic testing, and verification purposes the contents
of the channel-list RAM may have to be read. To perform read
operations the program must first set the pointer logic to the
desired
starting address and specify the required final
address. Then the following sequence is required:
1.
Write 004 into the high byte of the ADCSR.
2.
Read the channel-list entries successively from the CLPR
low byte.
Note that when the CLPR is read in this mode,
for diagnostic purposes, the high byte of the register will
contain the address of the channel-list entry that is being
read while the low byte will contain the contents.
The
pointer will be incremented after each read operation.
Hence successive reads will allow the program to read
successive entries of the RAM. The pointer logic is active
during this operation.
Therefore, when
the
pointer
increments to the final address register, it will be reset
back to the starting address.
programming sequence:
MOV
MOV
MOV
MOV
#2000, @#ADCSR
@#CLPR, RO
@#CLPR, RI
@#CLPR, R2
7-7
CHANNEL-LIST PROGRAMMING
ENTERING CHANNEL INFORMATION INTO THE RAM
This example selects page a for
readback purposes and then
takes three successive entries from the list and places them in
registers RO, R1, and R2.
7.3.3
MULTIPLEXER PRELOAD AND LOGIC ENABLE
After the pointer logic has
been
programmed
and
the
Channel-list RAM has been loaded with appropriate data the
program must set the pointer logic for an active cycle.
Part
of this activation involves issuing a load command to the
actual multiplexer and then enabling the logic for
AID
conversion operations.
The following sequence is required for
this:
1.
Write 006 to the high byte of the ADCSR.
2.
Perform a write operation to the low byte of the CLPR.
Note that the data written is not critical as only the
write operation is required.
3.
Write 000 to the high byte of the ADCSR
Programming sequence:
MOVB #6, @#ADCSR + 1
MOVB fO; @#CLPR
MOVB #0, @#ADCSR + 1
After this operation you must access only bits 14 and 15 of the
high byte of the ADCSR to ensure that the channel-list is not
disturbed.
7-8
CHAPTER 8
PROGRAMMING EXAMPLES
8.1
INTRODUCTION
This chapter presents five programs that describe how the
DT3362 series board should be programmed for certain non-DMA
operations or DMA transfers via the Q-bus.
The programs are
not intended to solve any particular application problem but
have been written such that key programming issues
are
demonstrated.
Programs 1 and 2 illustrate non-DMA operations,
while programs 2, 3, and 5 illustrate DMA transfer operations.
A brief summary precedes the listing of each program. All
example programs have been written as subroutines so that you
can test them by calling them from your main program. Note
again that these example programs are given for illustration
only and should not be used for diagnostics.
8.2
FADEX1 - EXAMPLE PROGRAM 1
In this example the DT3362 series board is used in the
programmed IjO mode to perform a single conversion on Channel 5
with a gain of 4 every time it is called.
The subroutine
initializes
the
multiplexer
channel-list and loads the
appropriate channel and gain information. Following this, it
initializes the AjD section and starts a programmed conversion.
The program then loops waiting for the AjD Done status bit to
set.
When this occurs the AjD data is read back along with
status information and a return of subroutine is done.
8.3
FADEX2 - EXAMPLE PROGRAM 2
In this example the DT3362 series board is set to perform
externally clocked conversions on Channel 5 at a gain of 1,
Channel 5 at a gain of 2, Channel 7 at a gain of 1, and Channel
2
at a gain of 1.
Each external clock initiates one
conversion.
Four clock ticks complete one scan of
the
channel-list.
The board interrupts the processor after every
conversion, and the interrupt handler keeps track of the number
of interrupts received. After 100 interrupts are received (25
scans), the interrupt handler disables the AID from further
conversions and write into the status word. Thus if a main
program calls this subroutine after clearing the status, it can·
8-1
PROGRAMMING EXAMPLES
FADEX2 - EXAMPLE PROGRAM 2
then test the status word for a non-zero value signifying the
completion of an A/D conversion.
8.4
FADEX3 - EXAMPLE PROGRAM 3
In this example the DT3362 series board will be set to perform
a burst of 100 conversions and place them in main memory via
DMA over the Q-bus. The channel-list is set up to sample in
the following sequence.
1)
2j
3)
4)
Channel 5
ChannelS
Channel 7
Channel 2
@ gain
@ gain
@ gain
@ gain
= 1
2
= 1
1
Thus each scan of the channel-list will be 4 conversions
requIrIng the channel-list to be scanned 25 times to get the
100 conversions. The burst mode operation implies that the A/D
is running at its maximum speed in that each conversion is
initiated by the end of the previous conversion until the
required number of conversions have been made.
Due to bus access requirements of a 250kHz A/D converter
(DT5727) the program places the processor in the wait state to
free up the bus. To avoid having an A/D overrun error, you
must also make sure that no other DMA activity is happening
during the burst A/D. This ensures that A/D conversion is
complete when control is returned to the calling program.
8.5
FADEX4 - EXAMPLE PROGRAM 4
The example program is essentially the same as number three in
that a total of 100 conversions are to be made and put into
memory under DMA.
The channels to be sampled are also
identical. The only difference is that the rate of conversions
is now controlled by the external clock input. Thus the time
interval between conversions is equal to the period of the
externally applied clock. Here a single conversion per clock
tick is made, requiring 100 clock ticks to perform the
necessary 100 conversions. An assumption has been made that
the clock frequency should not exceed 100kHz to allow the
DT3362 series adequate time to transfer data over the bus in
the face of processor and other bus activity. The main program
should call this subroutine after having cleared the PSTAT flag
word.
Then the main program can test when PSTAT becomes
non-zero to determine that the D~~ transfer has completed.
8-2
PROGRAMMING EXAMPLES
FADEXS - EXAMPLE PROGRAM 5
8.6
FADEXS - EXAMPLE PROGRAM 5
This program is again essentially the same as the previous two
in that 100 conversions with the same channel-list are to be
made and put into main memory. The only difference is that the
external trigger with List Scan mode is selected.
In this mode
each external clock tick will cause the DT3362 series ~u ~~au
through the channel-list once. Thus each scan of the list will
produce four conversions, requiring 25 external clock ticks to
gather 100 data points.
As the DT3362 series is bursting
through the channel-list at its maximum speed, a processor wait
is required to ensure that the AID had full access to the Q-bus
to avoid overrun errors. Here again, control returns to the
calling program when the required number of data conversions
have been taken.
8-3
. ENABLE LC
. TITLE FADEX1
Fast AID (DT3362) Programming Example 1
.SBTTL Functional description
25 Mar 81
This routine is a programming example designed to operate the
Data Translation Fast AID converter: OT3362 .
In this example the Converter is r.~uir.d to make a single
conversion in Programed 110 mode. The channel and gain values
are speci~ied in the data block below.
Here channel .5 is
selected ~ith a gain of 4 .
. SBTTL
BASE
AID data block, and control block deflnitions.
= 170400
= BASE
Ba~e
addre~~
of Fast AID converter.
= BASE+2
= sASE+4
= BASE+6
= BASE+l0
= BASE+12
AID Control and Status Register
AID Data Buffer Register
Channel File Programming Register.
DMA Control & Status Register.
DMA Word Count Reg i ster. (not used)
DMA Current Address Reg ister. (not used)
I NVEC
= 400
Address of Interrupt vector.
CHAN:
005
002
ADCSR
ADBUF
CFPR
DMACSR
DMAWCR
DMACAR
GAIN:
DATA:
STATS:
.BLKW
. BLKW
(not used)
Channel desired.
1
1
Gain specifier (02 is gain of four.
Space for AID data.
Space for AID Completion status .
; This is the routines entrv point .
FADEl::
. SBTTL
Initialization (in case of
po~erup
or reset)
This initialization code need onlv be executed once after
• po~erup or hard~are reset .
MOV
MOVB
• 001400, @wADCSR
.002, @4tCFPR+1
. SBTTL
Setup Channel
~
select
~rite
~rite to channel file
requiTed setup code .
Gain Arrav
This section sets up the channel file arrav.
This array specifies
which multiplexer channels are to be selected and then converted.
First set up Preset pointers. these indicate ~hich portion of the
channel array is to be used.
This example uses the first byte of
the first page of the channel file.
MOVB
MOVB
8053,
MOVB
MOVB
ttOOO,
@
@
ttADCSR + 1
.CFPR + 1
select start addrs., mode 01
5et initial pointe .... to zero.
.063,
ttOOO,
@
@
4tADCSR + 1
.CFPR + 1
select final addrs. , mode 01
set end pointer to ze .... o.
Now to form the gain and channel byte.
MOV
GAIN. RO
Get the gain information.
Must move Gain value over to bits 6-7
SWAB
ASR
ASR
RO
Move left 8 bits
Move back (right) one
Move back (right) one bit
......
RO
"'~v
RO
Now ADD in channel value.
ADD
(ADD is Logical OR if no bits match)
CHAN,RO
;
ADD
A
OCLEO\R
A.B
branch to check if done present
read data to clear done
check for done bit
loop to read data
DT3362 TST-l1 MODULE
MACRO Ml113
TEST PARAMETER BLOCK (TPB)
03-NDV-8211:22
PAGE 5
.SBTTL
86
87
88
89
90
91 000000
Test Parameter Block (TPB)
Test-II Declaration
. LIST
. MCALL
TSTll
ME
TST 11
; EOUATED SYMBOLS
TERMINAL 110 PARAMETERS
177560
177562
177564
177566
RCSR
RBUF
XCSR
XBUF
""177560
-177562
-177564
""177566
;
RECEIVER STATUS REGISTER
RECEIVER DATA BUFFER
TRANSMITTER !;T ATUS REG I STER
TRANSMITTER DATA BUFFER
SPECIAL ASCI I CHARACTERS
;
000003
000012
000014
000015
000040
000011
000177
CTRLC
LF
FF
CR
SPACE
CTRLI
DEL
=3
=12
=14
.. 15
-40
=11
=177
,
;
000340
; PRIORITY 7 PSW
PR7
=340
;
;
,
100000
040000
020noo
010000
004000
002000
001000
000400
000200
000100
000040
000020
000010
000004
000002
000001
BIT DEFINITIONS
BITI5
BIT14
BIT13
BI112
BITll
DITIO
DIT9
BIT8
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
BITI
BITO
-100000
=40000
-20000
-10000
-4000
-2000
=1000
=400
-200
-100
=40
-20
=10
"'4
"'2
=1
CONTROL-C
LINE FEED
FORM FEED
CARRIAGE RETURN
SPACE CODE
CONTROL-I (T/a.B)
DELETE CODE
DT3362 TST-11 MODULE
MACHO M1113
TEST PARAMETER BLOCK (TPB)
03-NOV-82 11:22
PAGE 6
; TST-11 PARAMETER STORAGE
000514
000526
ODTACC
ERRCNT
=514
=526
ODT ACCUMULATOR
OF ERRORSi
*
PARAMETER STORAGE FOR CODE MODULES,
000540
000542
000544
000546
SWR
BASE
VECTOR
DELAY
=540
... 542
=544
=546
000560
TFLAG
=560
. OLOBL
92
93
94
SWITCH REGISTER
BASE ADDRESS
VECTOR ADDRESS
DELAY COUNT
DMABUF
flag ~ord for ~ests
DMIA d i t t it b u f f! • r
HACRO Hll13
IT 3362 TST-l1 MODuLE
'EST PARAH£TE~ BLOCK (TPD)
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
03-NOV-82 11:22
P~~GE
7
Test Parameter Block
000000
TPB:
000002
000003
;
000004
000010
000014
000020
000024
000030
000034
000040
000044
000050
000054
000060
000064
000070
000074
000100
000104
000110
000114
000120
000124
000130
000134
000140
000144
000150
000154
000160
· NLIST
BIN
· WORD
PARAH
· BYTE
· BYTE
377
34
of p.rameter
print-out routine
reserved
.. of 1;ests
.ddre~s
Test Address Table for use blj TST-l1
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
· WORD
TESTl,PR7
TEST2,PR7
TEST3,PR7
TEST4,PR7
TESf5,PR7
TEST6,PR7
TEST7,PR7
TESTI0,PR7
TEST11,PR7
TESTI2,PR7
TESTl3,PR7
TESTI4,PR7
TESTI5,PR7
TESTI6,PR7
TE5TI7,PR7
TEST20,PR7
TE5T21,PR7
TE5T22,PR7
TE5T23,PR7
TE5T24,0
TE8T25,0
TEST26,0
TE5T27,0
TE8T30,0
TE5T31,0
TE5T32,0
TE5T33,0
TE5T34,0
. LI5T
BIN
DT3362 TST-ll MODULE
INITIALIZATION
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
012737
000164
000172
000242
000244
000246
000250
000306
000726
000310
000314
000316
000320
000324
113700
105700
001753
122700
103750
000326
000330
000334
000340
000340
000342
000346
000352
000354
000362
000370
000376
000402
000300
042700
010037
MACRO M1113
000000
03-NOV-82 11:22
000540
.SBTTl
Initialization
INIT:
MOV
PRINT
GETOCT
1$:
CRlF
PRINTC
BR
10,@ISWR
i
pre~et SWR
<.tt of AID inpult; chan""l. (in octal): )
I
get octal input
3$
j
CR - con~inue
; Ask again
INIT
3$:
MOVB
TSTB
BEQ
CMPB
BCS
BeS
103421
010701
062701
004767
103403
152737
012737
012737
005037
000207
000514
000100
100377
000540
000164
000032
000200
170400
000400
000546
000540
000542
000544
PAGE 8
5$:
SWAB
DIC
MOV
RElMOV
MOV
ADD
. CAll
DCS
BISB
MOV
MOV
CLR
RETURN
bits 11-8:
bi t 7:
bits 0-6:
@IODTACC,RO
RO
get the input value
z arll val ue?
no .- skip
check 'or out
limits
errlor
1.
0'
1100,RO
1$
RO
II00377,RO
RO,@ISWR
IPG,Rl
PC,Rl
"PG-. ,Rl
QUERY
5.
.. 200, ... SWR
.. 170400, ... BASE
1400,@"VECTOR
@.. OELAV
put channel in high b~ta
adJ'Llst 4 bit.
preset SWR
que.,.~
user
MOVIE PC TO R 1
ADD IN RUN-TIME OFFSET
I
I
t~p,.d "N"
.et PG bit
.et de'ault addreS5
set de'ault vector
preset dela~ to max.
all done
.. of AID channels
PG option installed
not used
DT3362 TST-ll MODULE
INITIALIZATION
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
000404
000406
000410
000426
000430
000434
000436
000442
000444
000446
000504
MACRO M1113
03-NOV-82 11:22
QUERY:
122700
001427
122700
001422
PAGE 9
PUSH
PRINTS
PRINT
TTYIN
000510
000512
000514
000516
000520
000522
000524
000261
000401
000241
000526
000555
PG:
PDTA:
(Y
or IN)?
CMPB
000116
BEG
CMPB
.'Y,RO
3$
.'N,RO
BEO
1$
POP
000736
<
000131
CRLF
PRINTC
00050~
Rl
BR
1$:
3$:
5$:
save pointer
print prompt
>
a "Y"?
a "N"?
I
VIPS
(See manual for assistance.)
Rl
; restore pointlPr
OUERY
SEC
set carrv flag
BR
CLC
TTYOUT
CRLF
clear carrV 'lag
echo character
POP
Rl
resto're Rl
RETURN
000207
· NLIST
BIN
· ASC I l
· ASCll
· EVEN
"I~ PO option in~talled"
"Print thlP data"
. LIST
BIN
.SBTTL
Displav ParamlPtIPrs
This routine displaV5 the current s.ttin~
of 'BASE' and 'VECTOR' on thIP system console
terminall.
000574
000620
000624
000626
000630
000654
000660
00066:2
000664
PARAM:
013700
000542
PRINT
MOV
OCTlb
CRLF
PRINT
013700
000207
000544
MOV
OCTlb
CRLF
RETURN
<: Base address
@ttBASE,RO
)-
get base address
di5pli"~
6(Rl)
PTRINT
"S3,1(Rl)
"0,5(Rl)
"63, 1 (R 1 )
"O,S(Rl)
"5, 1 (R 1 )
"0,4(Rl)
"43, 1 (R 1 )
"0, S(Rl)
"6. 1 (R 1 )
"0,4 (Rl)
"0. 1 (R 1 )
MOVB
MOVB
MOVB
MOVB
RETURN
"53.1(Rl)
"0. 5( R 1)
"63, 1 (R 1)
"377.S(Rl)
initiali~ation
I
routines
program CFPR chip
",r II te chip initialization
re1~urn
;
I
;
c It.tar ADCSR
c 1 t!ar DMACSR
init. pointer chip
command to ",rite firlit channel
fi1r"t channel
command to ",rite last channel
la'it channel
command to ",rite channel addrelili
write it
reset pointer
write strobe
command to load mux's
strobe
do it
return to test program
I
112761
112761
112761
112761
000207
0000'53
000000
000063
000377
000001
00000'5
000001
00000'5
PTRRST:
I
write pointer ",rite comm.nd
program starting address
",rite pointer ",rite comm.nd
program end pointer
return
OT3362 TST-l1 MODULE
ERROR REPORTERS
25.2
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
MACRO H1113
03-NOV-82 11:22
.SBTTL
PAGE 11
Error reporters
This routine provides error reporting for bus
time-out errors (no DRPLY from interface).
001054
001120
001122
001124
001126
NORPLY:
010100
000207
;
001130
REG:
010100
010200
011600
074200
PRINTC
PRINT
PUSH
MOV
OCT16
CRLF
PRINT
MOV
OCT16
CRLF
PRINT
MOV
XOR
OCT16
CRLF
PRINT
POP
OCT16
CRLF
RETURN
000207
;
display address
done
This routine provides urror reporting 'or register
bit errors (one or moru incorrect bit. in a register).
00115~
001166
001170
001172
001174
001176
001212
001214
001216
001220
001234
001236
001240
001242
001244
001260
001262
001264
001266
PRINT
MOV
OCT16
CRLF
RETURN
;
RO
Rt, RO
R2,RO
RO
save I~O
get address
get e.pected value
disp1ilV
get b'ld bits
gener'lte value
displitlj
space
;
;
get e,-ror bits
display
forma1;ting
done
This routine provides error reporting for the OMA
data trans fer c h ec k test. The I ocat i on in memory
where bad data was found is reported.
;
001270
001322
001352
001354
001360
001362
001364
DMAERR:
010300
162700
000207
000002
PRINTC
PRINT
MOV
SUB
OCT16
CRLF
RETURN
R3,RO
get address
*2,RO
modify
display
DT3362 TST-ll MODULE
MACRO M1113
MODEL TESTING INFORMATION
303
304
305
306
307
308
309
310
03-NOV-8211:22
.SDTTL
. NLIST
PAGE
Model testing information
BIN
This code module contains the routines necessary
to test th~ following DTI interface models:
311
312
313
314
315
316
317
318
319
320
321
1~
DT3362
13362
T3362
AID converter board
_cINIT
==TPD
. LIST
BIN
DT3362 TST-ll MODULE
LOGIC TESTS
323
324
325
326
327
328
329
330
331
332 001366
333 001370
001370
001372
334 001376
335 001402
336 001406
337 001412
338 001414
339 001416
340 001420
341 001424
342 001426
343 001430
344 00143~
345 001436
346 001440
347 001442
348 001444
349 00145CJ
350 001452
351 001454
352 001456
353 001462
354 001464
355 001466
356 001470
357 001474
358 001476
359 001500
360 001502
361 001504
362
MACRO M1113
03-NUV-8211:22
.SBTTL
,SBTTL
Logic T.sts
Test 1:
BRPLV from all registerlj
This test verifies that the interface s~.tem responds
with a bus repl~ signal during a bus bus read and a
buss write cycl •. All registers availabl. on th.
board are checked.
TESTI :
010602
010700
062700
010037
013701
012704
011100
010411
062701
011100
010411
062701
011100
010411
062701
011100
010411
062701
011100
010411
062701
000114
000004
000542
000000
MOV
RELMOV
MOV
ADD
1$:
000002
000002
000002
000002
000002
MOV
MOV
MOV
SCOPE
MOV
MOV
011100
010411
~V,,]
SP, R!2
.. 3$,RO
PC,RO
"3$-, ,RO
save SP
set up trap to 4
MOVE PC TO RO
ADD IN RUN-TIME OFFSET
RO,@i4
@"OASE,Rl
"0,R4
(R 1), RO
R4, (R I)
ADD
.. 2.Rl
SCOPE
MOV
MOV
(R1>.RO
R4, MACSR
0'
This test check. all legal combinations
bits
in the OMACSR ( DMA Control Status register ).
002064
002070
002072
002076
002100
002102
002106
002112
002116
002122
002124
013701
005004
012703
010402
042702
010261
016100
042700
074200
001402
000542
TEST4:
000200
1$:
177700
000006
000006
177700
MOV
CLR
MOV
SCOPE
MOV
BIC
MOV
MOV
BIC
)(OR
BEG
@ttBASE,Rl
R4
tH28. , R3
R4,R2
tt177700,R2
R2,6(Rl)
6( R1), RO
tU77700, RO
R2.RO
3$
J
ge·t base address
init test reg.
se·t .. of states
dell: lare loop point
set data
cllar unnecessartJ bits
program lourer b",te
read lour urord
clear unnece.sartJ bits
test bits
no error - skip
********.**********.****+*************************
Error Code Ob - bit error,
CSR
******************~.****.*************************
002126
002132
002134
002136
002140
3$:
005204
077320
ERROR
6. REO
rl!port error
SCOPE
INC
SOB
R4
R3. 1$
lc,op point
nl'lIt state
I ClIOp until done
EXIT
ll'ave
)T33h2
rEST 5
TST-11 MODULE
MACRO M1113
BIT TEST OF DMAWCR
03-NDV-82 11:22
.SBTTL
541
PAGE 19
Test 5:
0'
Bit test
542
543
544
545
546
J
547
548
549
550
551
552
553
554
002142
002146
002150
002154
002156
002160
002164
002170
555 002172
556 002174
557
013701
005004
012703
010402
010261
016100
074200
000542
0'
This test checks all leg.1 combinations
in the DMAWCR ( DMA Word Count Register ).
TEST5:
000000
1$:
000010
000010
001402
558
DMAWCR
MOV
CLR
MOV
SCOPE
MOV
MOV
MOV
XOR
SCOPE
BEG
@ttBASE,R1
R4
ttO,R3
bits
get b~.se .ddress
init test reg.
set .. of at .. tes
dec 1a,'e loop point
set dat.
program register
read ,~egiater
test bits
declare loop point
no error - skip
R4,R2
R2,10(R1)
10(Rl),RO
R2, RO
3$
******************4*****~*************************
559
560
561
562
ETTor Code 07 - bit errol'.
DMAWCR
******************.~******************************
563
564
565
566
567
568
569
570
571
572
002176
002202
002204
002206
002210
3$:
005204
077315
ERROR
7.REG
SCOPE
INC
SOB
R4
R3,1$
EXIT
J
repor't erTor
loop point
next st.te
loop until done
leave ""hen done
DT3362
TEST 6:
574
575
576
577
578
579
580
581
582
58'1
584
585
586
587
588
589
590
591
592
593
594
595
5'16
597
598
599
TST-11 MODULE
MACRO M1113
OIT TEST OF DMAADR
.SOTTL
604
PAGE 20
Test 6:
Oit test of DMAADR
This test checks all legal combinutions of bits
in the DMAADR ( DMA AddreSfi Register ).
002212
002216
002220
002224
002226
002230
002234
002240
002242
013701
005004
012703
010402
010261
016100
074200
00140;!
000542
TEST6:
100002
1$:
000012
000012
MOV
CLR
MOV
SCOPE
MOV
MOV
MOV
XOR
OEG
@*OASE,R1
R4
*32770. ,R3
R4,R2
R2. 12(Rl)
12(R 1), RO
R2.RO
3$
g I~ t base address
init test reg.
Sl~t * of states
dl~c lare loop point
Slitt register data
program the register
rll~ad register
turst bits
nl3 error - skip
**************************************************
Error Code 10 - bit .rror, DMAADR
j
********.*********.*******************************
002244
002250
002252
bOO 002256
601
602 002260
b03
03-NOV-8211'22
3$:
062704
077315
000002
ERROR
10, REG
report error
SCOPE
ADO
SOB
tt2,R4
R3, , .
IDop point
nlrxt .tate
IDop until done
EXIT
Iltave
OT33b2
TEST 7
TST-11 MODULE
MACRO M1113
CHECK AID START BIT
03-NOV-82 1122
.SBTTL
606
607
PAGE 21
Test 7:
Ch~ck
AID START bit
This test checks the operation
The bit is checked for readback
operat ion.
608
609
610
0' the AID start
0' zero and
bit.
read-onl~
611
612 002262
613 002266
013701
614 002270
615 00227;2
616 002274
617 002300
005011
011100
042700
001402
000542
TEST7:
177776
618
619
j
620
MOV
SCOPE
CLR
MOV
BIC
BEG
ct.BASE.Rl
(Rt)
(R 1). RO
*177176.RO
1.
i
get .Iddress
dec lilre loop point
clear board
get bit
test bit
ok - skip error
******************~*****.*************************
Error Code 11 - AID START bit error
reads as .. 1
621
622
623
624
******************~.****
625
002302
002306
002312
002316
630 002320
631 002324
626
627
628
629
012711
012711
011100
042700
001001
000010
000011
1$:
177776
ERROR
MOV
MOV
MOV
BIC
DNE
11. Rt::G
•• ************************
j
tHO. (Rl)
*11. (Rt)
(R 1). RO
*177776.RO
3.
j
;
report error
.et e.t.rnal trigger bit
set start bit
get data
test bit
continue no error
632
633
634
635
J
********************************.*****************
Error Code 12 - AID START bit error
not read back as a 1
636
637
638
639
******************~*****.*************************
640
641 002326
ERROR
12
report erro'r
CLR
EXIT
(Rt>
clear CSR
642
643 002330
644 002332
645
005011
3.:
OT3362 TST-ll MODULE
lEST 10: BINITL ACTION
MACRO M1113
.SBTTL
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
03-NOV-82 11'22
I
I
PAGE 22
Test 10:
BINITL action
This test verifies that the aINITL ~ignal clears
the proper ADCSR bits. The bits that are NOT
checked are
mux address bits
002334
002340
002344
002346
002352
002354
002356
002362
002364
002366
002372
002374
002400
002402
002404
002410
002412
002414
002416
002420
002424
002426
679
680
013701
004767
005211
013700
077001
005211
013700
077001
005211
013700
077001
012702
110211
005002
013700
077001
000005
011100
042700
074200
001402
000542
176340
TESTI0:
00054,6
1'*:
00054·6
3'*:
000546
5$:
000116
000546
7$:
OOOOi,O
SOB
MOV
MOVB
CLR
MOV
SOB
SCOPE
RESET
MOV
BIC
XOR
BEG
@tmASE. Rl
LSETUP
(R 1)
@*DELAV.RO
RO. 1$
(Rt>
@*DELAV.RO
RO.3$
(Rt>
@*DELAV.RO
RO.5$
*116.112
R2. (HI)
R2
@*DELAV.RO
RO,7$
(R 1 ). RO
*bO,RO
R2.RO
9$
I
get address
initialize pointer
start. conversion
",ait a ",hile
do the ",.it
2nd conv to fill pipeline
",.it a while
do the wait
3rd conv to set error
"'. i ,t a wh i 1 e
do the wait
get bit. to be turned on
set required bits
clr test reg.
",.it a ",hil.
do the wait
declare loop point
issue BINITL
get bits
ignore some bits
test bit.
OK - skip error
****************** •• ******************************
Error Code 13 - proper bit(s) not cleared
b", BINIITL
681
682
683
684
685
MOV
CALL
INC
MOV
SOB
INC
MOV
SOB
INC
MOV
******************.~******************************
ERROR
686 002430
13, REG
report error
687
688 002434
9$:
EXIT
.11 done
DT3362 TST-ll MODULE
MACRO M1113
TEST 11: BYTE OPERATION OF ADCSR
03-NOV-82 11:22
. SBTTL
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
PAGE 23
Test 11:
Byte operation of AOCSR
This test verifies high and low byte operations
involving the ADCSR.
000542
0024~2
013701
005011
013700
077001
012702
002456
002460
002464
002466
002412
002474
002500
002502
112711
011100
013703
077301
042700
074200
001402
077516
002436
002442
002444
002450
000546
000116
000546
177600
TESTII : MOV
CLR
MOV
1$:
SOB
MOV
SCOPE
MOVD
MOV
MOV
3$:
SOB
DIC
XOR
BEG
;
@ttBA5E,Rl
(Rl)
•• DELAV,IRO
RO, 1.
ttl 16, R2
get address
clear ADCSR
wait
ini t. test register
declare loop point
set R/W bits
get A,DCSR .s word
let board 'inish
.77516, (Rl)
(Rl), RO
@.OELAV,R3
R3,3$
.177600,RO
R2,RO
ignore st.tus bits
test bits
ok - skip error
5$
**************************************************
Error Code 14 - high byte loaded during
II low byte operation
************u*****~~****.*************************
002504
ERROR
14,Rt::G
;
report error
DT33b2 TST-ll MODULE
MACRO M1113
TEST 11: BYTE OPE.RATION OF AOCSR
719
720 002510
721 002512
722 002516
723 002520
724 002524
725 002526
726 002532
727 002536
728 002540
729 002542
730 002546
731 002550
732 002554
733 002556
734
735
736
737
738
739
740
741
742 002560
743
744 002564
005011
013700
077001
112702
110261
013703
077301
011100
042700
000302
042702
074200
001402
03-NOV-82 11'22
5t:
000546
7t:
000774
000001
000546
9$:
100261
100377
CLR
MOV
SOB
MOVB
SCOPE
MOVB
MOV
SOB
MOV
BIC
SWAB
BIC
XOR
BEQ
PAGE 24
(Rt>
@*OELAV,RO
RO,7S
*774,R2
clear ADCSR
wait
init test register
dRclilre loop point
SRt R/W bits
let board finish
R2, 1 (R 1 )
@*OELAY,R3
R3,9$
(R 1), RO
ttl00261,RO
R2
*100377,R2
R2,RO
11$
get AOCSR ilS word
ignore st.tus bits
ildJust R2
clear random bits
tRst bits
ok - skip Rrror
************.*****~4******************************
Error Code 15 -
low b'Jte loaded during
a high b"te operation
******************if. ... ****_ ... ****** .. *****************
,
ERROR
lit:
EXIT
15,Rt;Q
;
rRport error
r33b2 T5T-l1 MODULE
MACRO M1113
:5T 12· TEST OF MUX/GAIN MEMORY
03-NOV-8211:22
. SDTTL
746
747
748
749
75~)
76~1
764
765
766
767
768
769
770
771
Test 12:
0'
mux/gain memory
pllinter chip.
T~9t
0'
This test checks the operation
memory pointer chip.
750
751
752
754
755
756
757
758
759
760
761
762
PAGE 25
002566
002572
002576
002602
002604
002610
002612
002616
002620
002622
002624
002630
002636
002642
002650
002654
002660
002662
013701
012711
004767
005004
012703
000542
000000
176064
004767
176:204
TESTI2: MOV
MOV
CALL
CLR
MOV
SCOPE
1$:
CALL
000377
3$:
010402
005202
042702
112761
110261
112761
116100
042700
074200
001403
INC
177400
000005
000004
000032
000005
177400
DIe
000001
5$:
000001
MOVB
MOVa
MOVa
MOVB
DIe
XOR
BEQ
772
773
774
get base address
clear eSR
initialize pOinter chip
init test reg.
set .. of states
declare loop point
init pointr max spread
R1
.. 0, (Rl)
flTR INT
R4
tt377,R3
PTRRST
f~4,
R2
n2
4tl 77400, R2
4.5, 1 (R 1 )
n2,4(Rl)
(t32,1(Rl)
:;
1$
************ .. ***** ....~ **** .... ************************
Error Code 22 - AID DONE bit not cleared
after AID data was read
**************************************************
003302
003304
ERROR
DR
000451
22
17$
J
report error
can't continue
J
003306
003310
003314
003316
003322
003324
003326
1$:
042711
105211
013700
077001
105711
100402
100000
000546
3$:
J
SCOPE
OIC
INCB
MOV
SOB
TST8
OMI
declare loop point
clear possible errOr bit
set AID st.art bit
wait
"100000, (Rt)
(Rt>
@.. DELAV,RO
RO.3t
(Rt>
5.
j
done bit set?
- skip error
~es
**************************************************
Error Code 23 - AID DONE bit not set
************************ ... ************************
003330
003332
000436
ERROR
BR
23
17$
report error
carll't continue
MACRO M1113
DT:1362 TST-1J MODULE
TEST 14. AID START BIT TRIGGERING
947
948 003334
949 003336
'i50 003342
951 00334"
952
953
954
955
956
957
958
959
960 003346
961 003350
962
963
964
965 003352
966 003354
967 003356
968 003362
969 003364
970 003366
971 003370
972 003372
973 003374
974 003376
975 003400
976 003402
977 003404
978 003406
979 003410
980 003412
981 003414
982 003420
983 003424
984 003430
985
03-NOV-82 11:22
5$:
016100
105711
100002
000002
SCOPE
MOV
TSTD
DPL
PAGE 31
declare loop pOlnt
read ,AID dati!t
done bit clear?
Ves - skip error
2 (R 1). RO
(Rl)
7$
************************4*************************
Error Code 24 -
,
******************.******.************************
ERROR
DR
000427
Board
005011
005000
013702
001022
077201
005211
005200
103410
105711
100374
006300
006300
006300
006300
006300
102002
012700
010037
016100
7$:
000546
9$:
11$:
CLR
CLR
MOV
ONE
SOD
INC
INC
BCS
TSTB
BPL
ASL
ASL
ASL
ASL
ASL
avc
177777
000546
000002
DONE bit not cleared
after AID data was read
~VD
13$:
15$:
17$:
MOV
MOV
MOV
EXIT
24
17$
Cv cle "
report error
can't continue
compute time delay for AlI>
(R1>
RO
@ttDELAY,R2
17$
R2.9$
(R1>
RO
13$
(R1>
11$
RO
RO
RO
RO
RO
15$
*-l.RO
;
;
I
;
I
RO.~*DELAY
I
2(R 1). RO
I
clear CSR
clear counte,'
..,ait to .ettle
leave if non zero
start conversion
bump counter
leavlP if overflo..,
..,ait flor dono
no dOlne
multiplV bV 32
create ne.., delav
create ne.., delay
ereat. ne.., delay
create ne ... delay
branch if! no overflo..,
force mal delalj -1
store it
clear done
T5T-l1 MO~ULE
MACRO MI113
TEST 15: ERROR Bl1 OPERATION
OT33b2
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
03-NOV-82 11:22
. SDTTL
J
00343~
003436
003442
003446
003452
003454
003456
013701
004767
042711
013700
077001
005711
100001
000542
175242
100000
000546
PAGE 32
Test 15: ErTor bit
op~ration
This test verifies that the error bit of the ADCSR
can be set and cleared properlv.
TESTI5: MOV
CALL
BIC
MOV
1.:
SOB
TST
BPL
e*BASE,Rl
LSET\JP
"100000, (Rl)
e .. OELAY,RO
RO, I .
get address
ini,t. AID section
clear error bit
l&Jait
error bit clear?
ves - skip error
(Rl)
3$
******************.~****.*************************
Error Code 25 - Error bit not clear
J
**************************************************
003460
003462
003464
003476
003500
003504
003506
003510
003514
003516
003520
003524
003526
003530
3.:
105211
013700
077001
105211
013700
077001
105211
013700
077001
005711
100402
000546
000546
7.:
000546
9$:
J
ERROR
25
SCOPE
DCLEAR
2.,4$
J
INCB
(Rl)
MOV
SOB
@.. OELAY,RO
RO,5.
INCO
(Rl)
MOV
SOB
@.. DELAY,RO
declare loop point
clear done bit
three quick triggers
dela~ for done bit
l&Jait
second trigger
dela~ for error bit
RO,7.
INCO
(Rt)
MOV
SOB
TST
@.. OELAY,RO
BMI
11$
third trigger
for error bit
dela~
RO,9$
(Rt)
erT'or bit aet?
~e~ - skip error
**************************************************
Error Code 26 - Error bit not .et
*******************~******** •• ********************
003532
003534
000473
ERROR
OR
26
25$
Of3362 TST-l1 MODULE
MACRO
TEST 15: ERROR BIT OPERATION
1032
103:l
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
003~52
03-NOV-B211:22
11$:
003536
003540
003554
003560
003562
003564
M1113
005011
013700
077001
005711
100001
000546
13$:
PAGE 33
SCOPE
DC LEAH
CLR
6$,8$
(Rt>
declare loop pOInt
clear AID DONE bit
clear ADCSR
MOV
@.. DELAV,RO
RO. 1$
6 •• 8$
.. 13$.RO
PC.RO
"13$-.• RO
RO. (R:=!)
R3, 10(Rl)
R4. 12(Rl.
10$. 112.
tUOO. RO
RO. (R 1)
"S,6(Rl)
"0,R5
RS
(Rt>
J
get address
9 et VE~C tor
setup AID section
get weird count
get buffer address
MOVE PC TO R4
ADD U4 RUN-T I ME OFFSET
clear done
clear board
wait
loop
cletlr done
get ISR ilddress
MOVE IPC TO RO
AOD IN RUN-TIME OFFSET
store
store status too
declare loop point
load DMWCR
load DHCAR
clear done
load pre.et
set INT. END bit
set OMA END. bit
loop point
setup to enable interrupts
enable CPU interrupts
start trtlns'er process
013362 TST-ll MODULE
TEST 17: DMA LOGIC
MACRO M1113
03-NOV-82 11 22
PAGE 38
llq9
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
004260
004264
004266
004270
004274
004276
004302
004304
016105
005705
001411
013700
077001
016100
020005
001365
000010
5$:
MOV
TST
nEG
MOV
7$:
SOB
000546
MOV
CMP
DNE
000010
10(Rl),R5
sample DMWCR
end of range?
yes - wait for EOR
wait
R'
9$
@tmELAY, RO
RO,7.
10(Rl), RO
RO,R5
sample OMWCR
any transfers?
yes - continue
5$
; **************************************************
Error Code 35 - DMA failing to cycle
******************~4****_*************************
004306
004310
000442
004312
004316
013700
077001
ERROR
DR
35
25.
reJl,ort error
carl't continue
MOV
@ttOELAY,RO
wait one more cycle
SOB
RO,l1$
;
000546
9$:
11$:
J
****************** •• *************~****************
Error Code 36 - No
J
004320
004322
000435
EOI~
inter1rupt
*******************~******************************
ERROR
DR
36
25$
report error
can't continue
DT33b2 TST-lt MODULE
TEST 17 DMA LOGIC
1231
1232
123:1
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
004324
004330
004334
062706
005761
001402
MACRO M1113
000004
000010
03-NOV-8211:22
13$:
J
ADD
TST
BEG
PAGE 39
tt4,SP
10(Rl>
15.
ad JU!.t stack
DMAWCR=O
-- "kip error
~es
**************************************************
Error COdff 37 - EOR interrupt without
DMWCR -= 0000
I
004336
004340
004342
004346
004346
004350
1248 004354
1249 004356
1250
1251
1252
1253
1254
1255
1256
1257 004360
**************************************************
000426
016105
010700
062700
020005
001001
000012
OOOOOOC
15.:
ERROR
BR
37
25$
MOV
RELMOV
MOV
ADD
CMP
ONE
12
IRO
IRO.23$
CLR
SOB
MOV
MTPS
trigger conversion
set ma~: delav
wait
shut down interrupts
do it
ttPR7,RO
I~O
******************~.****o*******.*****************
Error Code 45 - No interrupt when DMAWCR
zero
i
005034
005036
000406
005040
005044
005050
062706
016100
001401
**************************************************
ERROR
DR
·45
27$
report error
leave
ADD
*4.SP
10(Rl), RO
27$
adJust the .tack
get wOT'd count
if! zerClI leave
i
000004
000010
25$:
MOV
BEG
******************4*******************************
Error Code 46 - DMAWCR not zero
*************************~************************
005052
005054
005062
005066
ERROR
012761
012711
000000
000000
000006
27$·
MOV
MOV
EXIT
; report error
*0,6
MACRO M1113
DT33b2 TST-Il MODULE
CALIBRATION INITIALIZATION
1652
1653
1654
1655
1656
1657
1658 005770
1659 005774
1660 005776
005776
006000
1661 006004
Ib62 006010
1663 00601:2
1664 006014
1665 006016
1666 006022
1667 006024
1668 006030
1669 006034
1670 006040
1671 006052
1672 006054
1673 006060
1674
1675 006062
1676 006066
1677 006070
006070
006072
1678 006076
1679 006102
1680 006104
1681 006106
006106
006110
1682 006114
1683 006120
1684 006122
1685 006124
1686 006126
1687 006132
1688 006134
1689 006140
1690 006144
1691 006150
16q2 006162
1693 006164
1694 006170
1695
03-NOV-82 11:22
. SBTTL
PAGE 50
Calibration initialization
The following routines perform initialization
functions for some
the calibration tests.
0'
004767
000600
010701
062701
004767
000474
000162
010002
005003
105737
100002
004767
004767
004767
000540
0002:J4
000624
000304
005011
105061
000207
000006
004767
000506
010701
062701
004767
000300
010002
010701
062701
004767
074002
005003
105737
100002
004767
004767
004767
005011
105061
000207
GETCH:
000414
000070
000421
000052
000540
0001:24
000662
000174
000006
1.:
CALL
PUSH
RELMOV
MOV
ADD
CALL
POP
MOV
CLR
TSTB
BPL
CALL
CALL
CALL
DCLEAR
CLR
CLRB
RETURN
GETCH1: CALL
PUSH
RELMOV
MOV
ADD
CALL
SWAB
MOV
RELMOV
MOV
ADD
CALL
POP
XOR
CLR
TSTB
BPL
CALL
1$:
CALL
CALL
DCLEAR
CLR
CLRB
RETURN
MCINIT
Rl
ttCHNHI,Rl
PC,RI
ttCHNMI-. ,Rl
CHAN
Rl
RO,R2
R3
@ttSWR
I.
GAIN
CHSTUP
MODE
2.,4$
(Rt)
6(Rl )
J
J
J
MCINIT
Rl
ttCHNM~,RI
PC,Rl
ttCHNM2-. ,Rl
CHAN
RO
J
RO,R~
ttCHNi"l3, Rl
PC,Rl
ttCHNM3-. ,Rl
CHAN
Rl
RO,R2
R3
@ttSWR
1.
GAIN
CSTUP3
MODE
2.,4$
(R 1)
6(Rl)
;
;
init mux. ram
save pointer
load pointer
MOVE PC TO Rl
ADD IN RUN-TIME OFFSET
get data
rl'.tore pointer
set data
init gain
check for PO
no PO
get gain bits
set channel
get mode bits
clear DONE
clear board
clear DMACSR
init mux. ram
save pointer
load pointer
MO\l'E PC TO Rl
ADD IN RUN-TIME OFFSET
get data
position
save
10il,d pointer
MO\l'E PC TO R 1
ADt' IN RUN-TIME OFFSET
get data
restore pointer
add in ending channel
init gain
ch I't k for PO
no PO
gl't. g .. in bits
set channel
gl't. mode bits
c h'ar DONE
c I E'ar board
c le'oiIr DMACSR
MACRO M1113
DT::1362 TST-l1 MODULE
CALIBRATION INITIALIZATION
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
006250
006254
006260
006262
006264
006302
006304
006306
006330
006332
006336
006342
006344
006362
006364
1·,25 006366
1726 006424
1727
1"128 006426
1729 006432
1730 006436
1731
1732 006440
1733 006442
1734 006466
1735 006472
1736
1737
1738 006474
1739 00b506
1740 006531
1741 006552
1742
1743
1744
1745
!:ave painter
output prompt
I
get value
CR at; end - cant.
Rl
restore p'Dinter
CHAN
try again
1$:
MOV
BIC
POP
RETURN
@.OOTACC,RO
.. 177l00,RO
Rl
get value
cleaT' upper bits
ad JU!.t the .tack
retuT'n
GAIN:
PRINT
GETOCT
DCS
PRINTC
DR
MOV
DIC
RETURN
IS:
MOV
BIC
RETURN
@"OOTACC,R2
.. 177400,R2
ERROl:
CRLF
PRINT
MOV
RETURN
MODE:
103420
000747
013702
042702
000207
012711
000207
CHNMI :
CHNM2:
CHNM3:
SMSG:
000514
177400
000000
· NLISr
· ASCIZ
· ASCI Z
· ASCI Z
· ASCIZ
· EVEN
output prompt
get value
i CR at end - cant.
MODE
loop till answer correct
1.
;
get value
c leal' high byte,RO
retul'n
.. 0, (R 1 )
c leal' error bit
i
retul'n
DIN
"Channel? II
"Starting channel? "
"Ending channel? "
"Semi burst mode
..
. LIST
i
;
BIN
MACRO Ml113
OT3362 TST-ll MODuLE
CALIBRATION INITIALIZATION
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
17B4
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
006574
006600
006604
006612
006620
006626
006634
006640
006644
006646
006652
006654
006656
013701
004767
112761
112761
112761
112761
012711
012703
005000
110061
005200
077304
000207
006660
006662
006664
006666
006670
006672
006700
006704
006712
006716
006722
006726
010300
000300
006200
006200
150200
112761
110261
112761
110261
012711
110061
004767
000207
00673~
006734
006736
006740
006742
006744
006746
006750
006756
006764
006772
007000
007004
007010
007014
007016
007022
007024
000542
172062
000053
000000
000063
OOO;!OO
002400
000200
03-NOV-8211:22
000053
000005
000063
000005
002400
000004
172044
000207
000053
000000
000063
000007
002400
000010
000004
171754
load base address
1ni t. pointer chip
load first address
load beginning address
load last address
load it
write mux memor~
load counter
load channel datum
write channel data
bump channel data
decrement counter and loctp
return
CHSTUP: MOV
SWAB
ASR
ASR
BISB
MOVB
MOVB
MOVB
MOVB
MOV
MOVB
CALL
RETURN
R3, RO
RO
RO
RO
R2,RO
*53,1(Rl)
R2, 5(Rl)
*63, 1 (Rl )
R2,5(RU
*2400, (R1)
RO,4(Rl)
MUXLD
position gain
P ca i t i on bits
CSTUP2:
R3,RO
R3
RO
000001
000005
000001
000005
1$:
000001
000001
010300
000300
006200
006200
150200
112761
112761
112761
112761
012711
012703
110061
077303
004767
(!.OASE,Rl
PTR II'H
*53,1 (Rl)
.0,5(R1)
.63,1 (Rl)
*128. , 5 ( R 1 )
*2400, (R1)
*128. ,R3
RO
RO,4(Rl)
RO
R3, I.
MCINIT:
000()04
PAGE 52
000001
000005
000001
000005
2'$:
MOV
CALL
MOVB
MOVB
MOVB
MOVB
MOV
MOV
CLR
MOVB
INC
SOB
RETURN
MOV
PUSH
SWAB
ASR
ASR
BISB
MOVB
MOVB
MOVB
MOVB
MOV
MOV
MOVB
SOB
CALL
POP
RETURN
;
;
add in channel
IClad first address
l~ad beginning address
IClad last address
IClad it
w,· i te mux memor~
I c~ad gain
lctad mux channel
rllturn
p(lsition gain
s.lve data
position bits
RO
RO
R2,RO
*53, 1 (Rl )
*0, 5(Rl)
*63,1(Rl)
*7,5(Rl)
*2400, (Rl)
tHO, 113
RO,4(Rl)
R3,2S
MUXLD
R3
;
add in channel
load first address
load beginning addresa
load last address
load it
w,~ i t. mux memor~
IlJad counter
load gain
IlJop to load
load mux channel
rtl~store gain data
rll~ turn
MACRO M1113
[lT33h2 TS f-l1 MODULE
CALIBRATION INITIALIZATION
1797
1798
1799
1800
1801
1802
1803
1804
180S
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
IB21
1822
1823
1824
1825
1826
007026
007030
007032
007040
007044
007046
007054
007060
007062
007064
007066
007072
007074
007076
007100
007102
007104
007110
007114
007116
007120
007122
007121\
007126
007132
007134
010200
000300
112761
110061
010200
112761
110061
010204
000304
042704
010300
000300
006;!00
006200
074400
012711
110061
120402
001403
005200
005204
000771
004767
000207
03--NOV--82 1 1 22
CSTUP3:
000053
000005
000001
000063
000005
000001
177700
002400
000004
1$:
171644
2$:
MOV
SWAB
MOVB
MOVB
MOV
MOVB
MOVB
PUSH
MOV
SWAB
BIC
MOV
SWAB
ASR
ASR
XOR
MOV
MOVB
CMPB
BEG
INC
INC
DR
CALL
POP
RETURN
PAGE 53
R2, RO
RO
.. S3, 1 (R 1 )
RO,5(Rl)
R2,RO
"63,1 (Rt)
RO, 5CR 1)
R4
R2,R4
R4
"177700.R4
R3,RO
RO
RO
RO
R4,RO
.. 2400, (R 1)
RO,4(Rt)
R4,R2
2$
RO
R4
1.
MUXLD
R4
;
get starting address
position it
load first address
load beginning address
position last address
load last address
load it
save data
position channels
position channels
clear unwanted bits
position gain
position bits
add in channel
write mux memorlJ
load gain
check for last channel
leave
bump next channel
bump channel address
loop
load mux channel
restore data
return
DT3362 TST-ll MODULE
MACRO M1113
TEST 24: AID CALIBRATION
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
03-NOV-82 11:22
.SBTTL
PAGE 54
Test 24:
AID Calibration
This test accepts a channel addre5S from the user
and displays the data from that channel continuously.
J
007136
007160
007164
007166
007172
007174
007~00
007204
007206
007210
007212
007214
007220
007222
007224
007226
007232
007234
007240
007242
007250
007254
007256
007260
007262
TEST24:
004767
176604
032702
001002
052702
112704
000010
110211
105711
100376
016100
005711
100013
112700
005237
001005
012737
012711
105304
001750
000751
000001
000010
1$:
3.:
5$:
000002
000105
000526
1"77777
000000
000526
7$:
PRINTC
CALL
KBEXIT
DIT
ONE
DIS
MOVD
CRLF
MOVB
TSTD
DPL
MOV
OCT16
TST
BPL
MOVD
TTYOUT
INC
ONE
MOV
MOV
DECB
BEG
TAB
DR
GETCH
tUO, R2
1.
"1, R2
.. 10,R4
R2, (Rl)
(Rl)
get channel address
set up keyboard
extltrnal?
yes - no start bit
51ft start bit
; line counter
start conversion
wait for DONE
5.
2(Rl), RO
(Rl)
7.
"'E,RO
gift data
display
Ifrror bit set?
no - skip
print 'E'
...ERRCNT
7$
"-I,@*ERRCNT
increment count
no overflolll
"0, (R 1)
clear error bit
line oVlfr?
yes - nelll line
R4
1$
next conversion
DT3362 TST-11 MODULE
MACRO Mllt3
TEST 25. AID DATA DISPLAY UNDER DMA
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
03-NDV-82 11:22
.SBTTL
PAGE 55
Test 25:
AID data
displa~
under DMA
This test allows the user to actually check the
AID data acquired at high speed and transferred
directly into memory.
007264
007322
007326
007332
007332
007334
007340
007342
007366
007400
007400
007402
007406
007412
007420
007424
007426
007434
007436
007442
007450
007454
007456
007460
004767
013703
176442
000544
010700
062700
010013
000126
010700
062700
010061
012761
032702
001404
112761
000405
052702
112761
052702
110211
000001
000776
OOOOOOC
000012
177000 000010
000010
000011
000006
000001
000005
000100
000006
TEST25: PRINTC
CALL
MOV
RELMOV
MOV
ADD
MOV
1$:
PRIN'r
DCLEAR
RELMOV
MOV
ADD
MOV
MOV
BIT
BEG
MOVe
BR
3$:
BIS
Move
5$:
7$:
BIS
MOVD
WAIT
DR
7$
under DMA>
get channel address
ge1~ vee tor addresli
get ISR address
MOVE PC TO RO
ADI> IN RUN-TIME OFFSET
store
>
the done bit
load DMCAR
MOVE PC TO RO
ADD IN RUN-TIME OFFSET
load DMCAR
load DMWCR
test for external trig
no ext. t r i !II .
set semi burst bits
continue on
turn on start bit
turn on dma
set: i nt.. enb. b it
10CiId mode bits
wait for interrupt
hang until received
cl~ar
MACRO 111113
DT3362 TST-ll MODULE
lEST 25: AID DATA DISPLAY UNDER DMA
1889
1890 007462
1891 0074b4
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
007470
007472
007474
007500
007502
007502
007504
007510
007514
007520
007522
007524
007526
007530
007532
007534
007536
007540
007542
007544
007546
007550
105011
062706
005711
100003
004767
000420
03-NOV-82
9.:
000004
17~)740
11$:
010703
062703
012704
112705
OOOOOOC
001000
000010
13$:
012300
15$:
005304
001404
105305
001767
17$:
000770
19$:
005000
106400
000674
11-22
CLRB
ADD
TST
BPL
CALL
BR
RELMOV
MOV
ADD
MOV
MOVD
CRLF
MOV
OCT16
DEC
DEG
OECD
BEG
TAB
DR
CRLF
CLR
MTPS
BR
PAGE 56
(Rl>
tt4.SP
(R1>
11.
ERRBT
19.
ttOMABUF,R3
PC.R3
ttOMADUF-. ,113:
ttl000,R4
ttl0,RS
turn off mode bits
adJulit stack
error bit set?
no - skip
print error bit set
loop to nelal setup
display buffer
MOVE PC TO R3
A,DD IN RUN-TIME OFFSET
conversion count
line counter
(R3)+.RO
get data
displa"
13111 done?
Ides - nelal buffer
line done?
'.1.6 - loop
Rlore datil
R4
19$
R5
13$
15.
RO
RO
1$
rlelal buffer
Y'e-enable into
DT33b2
TEST 25.
1915
1916
1917
1918
1919
19;?O
1921
19;?;?
1923
1924
1925
19;?6
19;?7
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
194;?
1943
1944
1945
1946
1947
1948
1949
1950
MACRO M1113
T5 T-l1 MODULE
AID DATA DISPLAY UNDER DNA
03-NDV-82 1 1 .
~2
. SOTTIL
;
007552
007604
007610
007612
007616
007630
007632
007636
007640
007642
007644
007650
0076'54
007662
007664
007666
007670
007672
007674
007700
007702
007704
007706
007710
007712
007716
007720
007722
007724
176764
013701
000542
005011
105061
005002
000006
..
1$:
005003
004767
112703
177064
000010
010200
005;?11
105711
100376
016100
105303
001367
005202
123702
001350
005002
000745
3$:
'5$:
000002
000'541
Test 26:
AID input c hilOne I scan
This test scans the input channels ~lIhile
diiplaying the AID data on the termllnal.
TEST;?6:
004767
PAGE 57
PRINTC
CALL
KOEXIT
MOV
DCLEAR
CLR
CLRB
CLR
CRLF
CLR
CALL
MOVO
PRINT
NOV
OCT8
INC
TST8
OPL
MOV
TAD
OCT16
DECO
ONE
INC
CMPB
ONE
CLR
CRLF
DR
MCINIT
i ni 1~ mux. ram
set up keyboard
@IBASE.Rl
get address
2 •• 4.
c I eilr the done bit
(Rl)
clear CSR
6(Rl)
clear DI'1ACSR
R2
ini1L channel count
R3
CSTUP2
tUO. ri3
R2.RO
ini1L channel gain
setup the channels
line counter
display address
(RU
(RU
5$
2(R 1). RO
sta,rt the board
wai11; for DONE
;
R3
3$
R2
@ttSWR+l, R2
1.
R2
1$
;
get data
space over
display
line done?
no .- continue
inc. channel
end of range?
no'- continue
yes
new line
loop
MACRO Mll13
D133b2 TST-l1 MODULE
TEST 26. AID INPUT CHANNEL SCAN
1952
1953
1954
1955
1956
1957
1958
1959
1960 007726
1961 007732
1962 007734
1963 007740
1964 007776
1965 01000C
1966 010012
1967 010014
1968 010020
1969 010022
1970 010024
1971 010026
1972 010032
1973 010040
1974 010042
1975 010044
1976 010050
1977 010052
1978 010056
1979 010062
1980 010064
1981 010066
1982 010070
198:J 010074
1984 010100
1985 010102
1986 010104
1987 010106
03-NOV--82 11 22
.SBTTL
;
105737
100113
004767
005011
105061
005002
005003
000540
TEST27:
176634
000006
000007
010200
112700
000054
112700
032703
001401
105200
000060
000002
112700
032703
001401
105200
()OOObO
004767
176622
Test
~7:
A/D inpui; gain/channel scan
This test scans the inpu1. channuls while
changing the gain of the converter.
The
A/D data is displtlued on th. tel'mi nal.
1$:
112704
PAGE 58
3.:
000001
5$:
TSTO
BPL
CALL
PRINTC
KBEXIT
DCLEAR
CLR
CLRB
CLR
CLR
CRLF
MOVD
PRINT
MOV
OCT8
MOVB
TTYOUT
MOVD
BIT
BEG
INCO
TTYOUT
MOVB
BIT
BEG
INCB
TTYOUT
CALL
ctttSWR
check for gain option
11$
gain opt. not in
MCINIT
init board ram
set up ke'jboard
;
2$,4$
cletlr the done bit
; clear CSR
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