UMC_Data_Book_1986 UMC Data Book 1986
User Manual: UMC_Data_Book_1986
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PACESETTER
ELECTRONICS
inc.
HEADQUAIITE• •
5417 E. La Palma Ave
~;;~~'~~7_~:1f2817-0803
(213) 233-5800
NO. CAUFORNIA IIIIANCII
543 WeddeD Drive
Sunnyvale. CA 94089
14(8) 734-5470
. DATA lOOK
Microcomponent
&
Memory ICs
MEDICAL APPLICATIONS
UMC's products are not authorized for use in medical applications, including, but not limited to, use in life support devices without the written
consent of the appropriate officer of UMC's sales company. Buyers of
UMC's products are requested to notify UMC's sales offices when planning
to use the products in the applications which involves medical applications.
NOTICE
The information in this document has been carefully checked. However,
no responsibility is assumed for inaccuracies.
The example of an applied circuit or combination with other equipment
shown herein indicates characteristics and performance of semiconductorapplied products. The Company shall assume no responsibility 10r any
problem involving a patent caused when applying the descriptions in the
example.
SUMO
TABLE OF CONTENTS
A. Indices
D. Numerical
D Functional
D Cross-Reference
D Ordering Information
1. Mask ROM
2. SRAM
3 .. Microcontroller
4. ·Microprocessor
5. CRT Controller
6. Floppy Disk Controller
7. Peripheral IC
B. General Information
o
MOS Handling
DOC/Reliability
Packaging Information
Representatives/Distributors
o
o
eUMC
Numerical Indices
Part No.
Page
Part No.
Page
UM2147 ............................
UM2148 ............................
UM2149 .......................... "
UM23128/A .........................
UM23256/A .........................
UM2332 ............................
UM2333 ............................
UM2364 ............................
UM2366/A . . . . . . . . . . . . . . . . . . . . . . . . ..
UM2661 ............................
UM2681 ............................
UM6104 ............................
UM6104-1 ...........................
UM6114 ............................
UM6116-2/-3/-4 ...................... ,
UM6116-5 ..........................
UM6164 ............................
UM6167 ............................
UM6168 ............................
UM6502f6507/6512 ....................
UM6520fA ....... ' ..................
UM6521 fA ..........................
UM65221 A . . . . . . . . . . . . . . . . . . . . . . . . . .
UM6532/A . . . . . . . . . . . . . . . . . . . . . . . . . .
UM6551 fA ., ........................
2-3
2-8
2-13
1-15
1-18
1-3
1-6
1-9
1-12
7-3
7-18
2-18
2-23
2-28
2-33
2-38
2-43
2-50
2-55
4-3
7-41
7-52
7 -63
7 -80
7;87
UM6845/A/B . . . . . . . . . . . . . . . . . . . . . . . . .
UM6845E ...........................
UM6845R . . . . . . . . . . . . . . . . . . . . . . . . . . .
UM8048/35/49/39 . . . . . . . . . . . . . . . . . . . ..
UM8051/31 ....................... '"
UM82C01 ...........................
UM82C284 ..........................
UM82C288 ..........................
UM8237A/A-4/A-5 .....................
UM82450/8250 .......................
UM8253/8253-5. . . . . . . . . . . . . . . . . . . . . ..
UM8254 ............................
UM82C55A ..........................
UM8259A ...........................
UM82C6818 .........................
UM8272A ...........................
UM82C8167A ........................
UM82C84A ..........................
UM82C88 ...........................
UM8312 ............................
UM8321 .................. ; . . . . . . . ..
UM8326/B ..........................
UM8329/T /B/BT " ....................
UM9007 ............................
UM9228-1 . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-3
5-26
5-29
3-3
3-14
7-96
7-107
7-108
7-142
7-188
7 -143
7-154
7-109
7-169
7-186
6-3
7-187
7-128
7-135
5-71
5-57
6-29
6-34
5-56
6-24
A-l
INDICES
Functional Indices
Part No.
Page
Part No.
UM6845R
UM6845E
UM9007 .
UM8321
UM8312 .
Mask ROM
UM2332 ......................... ',"
UM2333 ............... , ........... ,
UM2364 . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
UM2366/A . . . . . . . . . . . . . . . . . . . . . . . . . .
UM23128/A .........................
UM23256/A
1-3
1-6
1-9
1'-:'12
1-15
1-18
. . . . . . . . . . . . . . . . . . . . . . . . . . , 5-26
. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39
. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-56
5-57
. . . . . . . . . . . . . . . . . . . . . . . . . .. 5-71
Floppy Disk Controller
UM8272A . . . . . . . . . . . . . . . . . . . . . . . . . . ,
UM9228-1 . . . . . . . . . . . . . . . . . . . . . . . . . . ,
UM8326/B . . . . . . . . . . . . . . . . . . . . . . . . . .
UM8329/T /B/BT . . . . . . . . . . . . . . . . . . . . ..
SRAM
UM2147 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UM2148 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UM2149 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UM6104 ....... ~ ....................
UM6104-1 . . . . . . . . . . . . . . . . . . . . . . . . . "
UM6114 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UM6116-2/-3/-4 .......................
UM6116-5 . . . . . . . . . . . . . . . . . . . . . . . . . . .
UM6164 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UM6167 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UM6168 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
2-3
2-8
2-13
2-18
2-23
2-28
2-33
2-38
2-43
2-50
2-55
6-3
6-24
6-29
6-34
Peripheral IC
UM2661 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UM2681
UM6520/A
UM6521/A
UM6522/A
UM6532/A
UM6551/A
UM82COl . . . . . . . . . . . . . . . . . . . . . . . . . . ,
UM82C284 . . . . . . . . . . . . . . . . . . . . . . . . . ,
UM82C288 . . . . . . . . . . . . . . . . . . . . . . . . . .
UM82C55A . . . . . . . . . . . . . . . . . . . . . . . . . ,
UM82C84A ..........................
UM82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . .
UM8237A/A-4/A-5 .....................
UM8253/8253-5 . . . . . . . . . . . . . . . . . . . . . ..
UM8254 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UM8259A . . . . . . . . . . . . . . . . . . . . . . . . . . .
UM82C6818 . . . . . . . . . . . . . . . . . . . . . . . . .
UM82C8167A ........................
UM82450 . . . . . . . . . . . . . . . . . . . . . . . . . . ,
UM8250 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller
UM8048/35/49/39 .................... 3-3
UM8051/31 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Microprocessor
UM6502 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
UM6507 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
UM6512 . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3
CRT Controller
UM6845/A/B . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
A-2
7-3
7-18
7-41
7-52
7-63
7-80
7--87
7-96
7-107
7-108
7-109
7-128
7-135
7-142
7 -143
7-154
7-169
7-186
7-187
7-188
7-188
SUMO
::::::::===
CROSS REFERENCE GUIDE
=
SRAM
UMC
UM2147
UM2148/UM2149
UM6167
UM6168
Synertek
SYP2147H
SYP2148H/SYP2149H
SYP2167
SYP2168
AMD
AM9247
AM2148/AM2149
Fuj itsu
MBM2147H
MBM2148/MBM2149
MB8167A
MB8168
Intel
2147
2148/2149
2167
2168
Mostek
MK4104
NS
NMC2147H
NEC
J,.LPD2147
J,.LPD4311
J,.LPD4314
Toshiba
TMM315
NMC2148H
Hitach i
TMS2147H
T.I.
AM99C68
HM6148
HM6167
TMS2149
TMS2167
TMS2168
Mitsubishi
Mask ROM
UMC
UM2366/A
UM23128/A
UM23256/A
Synertek
SYP2365
SYP23128
SYP23256
AMD
AM9265
AM92128
AMI
S2364
S23128
G.I.
RO-3-9365
RO-9128
Mostek
MK37000
MK38000
MCM63256
Motorola
NS
NEC
J,.LPD23128A
J,.LPD2364E
J,.LPD23256A
26128A
Signetics
Toshiba
TMM2364P
Intel
2364A
TMM23256
A-3
(l)UMC
===========
ORDERING INFORMATION
Microcomponent Products
Part
Number
Clock
(Speed)
Part
Number
Compatible
Devices
UMS04S-6
UMS035-6
UMS049-6
UMS039-6
UMS04S-S
UMS035-8
UMS049-S
UMS039-S
UMS04S-11
UMS035-11
UMS049-11
UMS039-11
6MHz
6MHz
6MHz
6MHz
SMHz
SMHz
SMHz
SMHz
11MHz
11MHz
11MHz
11MHz
Intel
Intel
Intel
Intel
Intel
I mel
Intel
Intel
Intel
Intel
Intel
Intel
UMS051/31
12MHz
Intel S051 /31
UMS329
UMS329T
UMS329B
UMS329BT
S04S-6
8035-6
S049-6
S039-6
S04S-S
S035-S
S049-S
S039-S
S04S-11
S035-11
S049-11
S039-11
UM2661-1
UM2661-2
UM2661-3
Clock
(Speed)
SMHz
SMHz
16MHz
16MHz
Baud Rate 1
Baud Rate 2
Baud Rate 3
Compatible
Devices
FDC9229
FDC9229T
FDC9229B
FDC9229BT
SYP2661-1
SYP2661-2
SYP2661-3
MC26S1
SCN26S1 AC1 N40
UM26S1
UM6520
UM6520A
1MHz
2MHz
SYP6520
SYP6520A
UM6521
UM6521A
1MHz
2MHz
SYP6521
SYP6521A
UM6522
UM6522A
1MHz
2MHz
SYP6522
SYP6522A
UM6502
UM6502A
UM6502B
UM6502C
1MHz
2MHz
3MHz
4MHz
SYP6502
SYP.6502A
SYP6502B
UM6507
UM6507A
1MHz
2MHz
SYP6507
SYP6507A
UM6532
UM/532A
1MHz
2MHz
SYP6532
SYP6532A
UM6512
UM6512A
UM6512B
1MHz
2MHz
3MHz
SYP6512
SYP6512A
SYP6512B
UM6551
UM6551A
lMHz
2MHz
SYP6551
SYP6551A
UM6S45
UM6S45A
UM6S45B
1MHz
L5MHz
2MHz
HD6S45S
HD6SA45S
HD6SB45S
UMS2C01
Interface
with 1-11 MHz
S04S/49
UMS2C55A
UMS2C55A-5
tRD = 250 ns
tRD = 200 ns
UM6S45R
UM6S45RA
UM6S45RB
1MHz
2MHz
3MHz
SYP6S45R
SYP6S45RA
SYP6S45RB
UM6S45E
UM6S45EA
UM6845EB
1MHz
2MHz
3MHz
SYP6S45E
SYP6S45EA
SYP6S45EB
UM9007
UMS321A
UMS321B
30MHz
2S.5MHz
SMHz
4MHz
FDC765A
UM922S-1
-
-
UMS326
UMS326B
4MHz
SMHz
FDC9216
FDC9216B
UM~272A-4
UMS237A
UMS237A-4
UMS237A-5
CRT9021A
CRT(021B
CRT9212
UMS272A
UMS2CSS
CRT9007
-
UMS312
UMS2CS4A
UMS2CS4A-1
UMS253
UMS253-5
-
UMS254
UMS259A
UMS259A-2
UMS259A-S
* T: Clock
A-4
SMHz
10MHz
3MHz
4MHz
4MHz
2.6MHz
5MHz
SMHz
tRHAx=260ns
tRHAx=235ns
tRHAX=420ns
-
HDS2C55A
HDS2CS4A
HDS2CSS
Intel S237A
Intel S237 A-4
Intel S237 A-5
iPS253
iPS253-5
iPS254
iPS259A
iPS259A-2
iPS259A-S
eUMC
ORDERING INFORMA TION
Memory Products
Part
Number
Organi·
zation
Access
Time
(ns)
Max. Current
(mA)
Oper·
ating
Stand·
by
UM2332
UM2332·1
UM2332·2
4KxB
4KxB
4KxB
450
350
250
100
100
100
UM2333
UM2333·1
UM2333·2
4KxB
4KxB
4KxB
450
350
250
100
100
100
UM2364
UM2364·1
UM2364·2
UM2364A
UM2364A·l
UM2364A·2
BKxB
BKxB
BKxB
BKxB
BKxB
BKxB
450
300
200
450
300
200
100
100
100
100
100
100
UM2366
UM2366·1
UM2366-2
UM2366A
UM2366A-l
UM2366A-2
BKxB
BKxB
8Kx8
BKx8
8KxB
BKxB
450
300
200
450
300
200
100
100
100
100
100
100
UM2312B
UM2312B-l
UM23128-2
UM2312BA
UM23128A-l
UM23128A-2
16Kx8
16KxB
16Kx8
16KxB
16Kx8
16KxB
450
300
200
450
300
200
100
100
100
100
100
100
UM23256
UM23256-1
UM23256-2
UM23256A
UM23256A-l
UM23256A-2
32Kx8
32Kx8
32Kx8
32KxB
32Kx8
32Kx8
450
300
200
450
300
200
100
100
100
100
100
100
UM6104
UM6104-2
UM61 04-3
UM6104-4
UM6104-1
lKx4
lKx4
1Kx4
1 Kx4
1Kx4
250
200
150
120
2000
7
7
7
7
5
0.01
0.01
0.01
0.01
0.003
UM6104J
UM6104J-2
UM6104J-3
UM6104J-4
lKx4
lKx4
1 Kx4
1 Kx4
250
200
150
120
7
7
7
7
0.01
0.01
0.01
0.01
UM6114
UM6114-1
UM6114-2
UM6114-3
lKx4
1 Kx4
lKx4
lKx4
90
70
55
45
40
30
30
30
0.20
0.02
0.02
0.02
Part
Number
Organi·
zation
Access
Time
(ns)
UM6114Jt
UM6114J-l
UM6114J·2
UM6114J·3
1 Kx4
1 Kx4
1 Kx4
lKx4
90
70
55
45
UM6116-2
UM6116-3
UM6116-4
UM6116-5
2Kx8·
2KxB
2KxB
2KxB
UM6116J-2
UM6116J-3
UM6116J-4
UM6116J-5
2KxB
2KxB
2KxB
2KxB
UM6164-2
UM6164-1
UM6164
BKxB
BKxB
BKxB
UM6167
UM6167-1
UM6167-2
UM6167L
UM6167L-l
UM6167L-2
Synertek
PIN
12
12
12
SYP2364
SYP2364·3
SYP2364·2
SYP2364A
SYP2364A·3
SYP2364A·2
12
12
12
SYP2365
SYP2365·3
SYP2365-2
SYP2365A
SYP2365A-3
SYP2365A·2
10
10
10
SYP23128
SYP23128-3
SYP23128-2
SYP2312BA
SYP23128A-3
SYP2312BA-2
10
10
10
SYP23256
SYP23256-3
SYP23256-2
SYP23256A
SYP23256A-3
SYP23256A-2
Max. Current
(mA)
Synertek
PIN
Oper·
ating
Stand·
by
40
30
30
30
0.02
0.02
0.02
0.02
120
90
70
55
100
100
100
100
0.5
0.5
0.05
0.05
-
120
90
70
55
100
100
100
100
0.5
0.5
0.05
0.05
-
45
55
70
100
100
100
10
10
10
-
16Kxl
16Kxl
16Kxl
16Kxl
16Kxl
16Kxl
70
55
45
70
55
45
60
60
60
50
50
50
2
2
2
0.05
0.05
0.05
-
UM6168
UM616B-l
UM616B-2
UM616BL
UM6168L-l
UM6168L-2
4Kx4
4Kx4
4Kx4
4Kx4
4Kx4
4Kx4
70
55
45
70
55
45
90
90
90
90
90
90
2
2
2
0.05
0.05
0.05
-
UM2147
UM2147-1
70
160
55
45
70
55
180
180
140
125
20
30
30
15
15
SYP2147H
SYPl147H-3
UM2147-2
UM2147L
UM2147L-l
4Kxl
4Kxl
4Kxl
4Kxl
4Kxl
SYP2147H-2
SYP2147HL
SYP2147HL-3
UM2148
UM2148-1
UM2148-2
UM2148L
UM214BL-l
1 Kx4
1 Kx4
lKx4
1 Kx4
1 Kx4
70
55
45
70
55
150
150
150
125
125
30
30
30
20
20
SYP214BH
SYP214BH-3
SYP214BH-2
SYP214BHL
SYP214BH L-3
UM2149
UM2149-1
UM2149-2
UM2149L
UM2149L-l
lKx4
lKx4
lKx4
1 Kx4
lKx4
70
55
45
70
55
150
150
150
125
125
-
SYP2149H
SYP2149H-3
SYP2149H-2
SYP2149HL
SYP2149HL-3
t: Ceramic Package
A-5
-
-
-
-
-
-
-
-
Mask ROM
Selection Guide
Descriptions
Part No.
Compatible Devices
'"
UM2332
4KxS NMOS ROM (2532)
UM2333
4KxS NMOS ROM (2732)
~PD
2332
AM 9233
Remarks
Access Time 450, 350,
250 ns
Access Time 450,350,
Page
1-3
1-6
250 ns
UM2364
8KxS NMOS ROM (2564)
SYP 2364
UM2366/A
SKxS NMOS ROM (2764)
SYP 2366
Access Time 450, 300,
200 ns
Access Time 450,300,
200 ns
UM2312S/A
*UM23256/A
16KxS NMOS ROM (2712S)
32Kx8 NMOS ROM (27256)
SYP2312S
SYP 23256
Access Time 450,300,
200 ns
Access Ti me 450, 30O,
200 ns
* Under Development
1-2
1-9
1-12
1-15
1-18
SUMO
::::::::::::=
UM2332
4K x 8 NMOS ROM rJlIIIlI.
Features
•
Access time 250/350/450ns (max.)
•
Pin compatible with 2532 EPROM
•
Single +5V ±10% power supply
•
Two programmable chip selects for output control
•
TT L compatible inputs and outputs
•
N-channel silicon gate technology
•
Three-state outputs
General Description
Programming of the device is accomplished by a custom
The UM2332 is a 32,768-bit static MOS read only memory
organized as 4096 words by 8 bits.
The device is com-
masking process.
The UM2332 is designed for memory
pletely static in operation, and operates from a single
application~
+5V power supply. All inputs and outputs are TT L com-
and simple interfacing are important· design objectives.
patible.
where high performance, large bit storage,
The two chip select inputs are programmable.
Block Diagram
Pin Configuration
-vcc
A7
vcc
A6
As
As
A9
A4
CS2/CS2
A3
CSl/CSI
A2
AlO
Al
All
Ao
07
00
06
01
05
02
04
GND
03
Au
Ao
-
ADDRESS INPUT BUFFER
X
DECODER
32,768 BIT
CELL MATRIX
1-3
Y
DECODER
Y
CATING
OUTPUT
ENABLE
LOCIC
OUTPUT
BUFFER
GND
CS1/CSI
CS2/CS2
00
01
02
03
04
Os
06
07
UM2332
Absoillte Maximum Ratings*
*Comments
o
Ambient temperature under bias, T A . . . . . -10 to +80 C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied and exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
o
Storage temperature, T STG ........... -65 to +150 C
Applied voltage on any pin with
respect to ground . . . . . . . . . . . . . . . . . -0.5 to +7V
Power dissipation, Po . . . . . . . . . . . . . . . . . . . . . 1.0W
D. C. Electrical Characteristics
(T A = 0 to 70°C, Vee = 5V
Symbol
±
10% unless otherwise specified)
Limits
Parameter
Units
Min.
Typ.
Test Conditions
Max.
VIL
Input low voltage
-.05
0.8
V
V 1H
Input high voltage
2.0
Vee
V
VOL
Output low voltage
0.4
V
IOL = 2.1mA
VO H
Output high voltage
Vee
V
IOH = -400J.LA
10
J.LA
V 1N = Vee = 5.25V
. 10
J.l.A
VOUT = Vee = 5.25V
100
mA
III
Input load current
ILO
Output leakage cLirrent
lee
Vee current
2.4
Capacitance
(T A =
25°c
Symbol
f = 1.0MHz)
Limits
Parameter'
Typ.
C1N
COUT
Max.
Input capacitance
7
Unit
Test Conditions
pF
All pins except pin under
Output capacitance
10
Note:
This parameter is periodically sampled and is not 100% tested.
1-4
pF
tied to AC ground
(l)UMC
UM2332'
A. C. Electrical Characteristics
(TA
= 0 to 70°C,
Vcc
= 5V ±
10%)
UM2332
UM2332·1
UM2332·2
Parameter
Symbol
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Address access time 1
450
350
250
ns
tco
Output enable delay from CSt ICS t or CS 2 /CS 2
150
120
120
ns
tDF
Output disable delay from CSt/CSt or CS 2 /CS 2
0
100
ns
tOH
Output hold from address change
10
tACC
100
100
0
0
10
10
ns
Test Cond itions
Timing reference levels . . . . . . . . . . . . . . . . . . . . . . . .
............. Input = 1.5V, Output = 0.8V and 2.0V
Output load .............. 1 TTL load and 100pF
Input transition time . . . . . . . . . . . . . . . . . . . ,. 20ns
Timing Diagram
ADDRESS
INPUTS
INVALID
VALID
-
tACC
·1
CHIP
SELECT
INPUTS
INVALID
VALID
_tco~
OUTPUTS
HIGH IMPEDANCE
~+--
-
1
VALID
:.
Ordering Information
Part Number
Access Time
Package
UM2332
450ns
Plastic
UM2332-1
350ns
Plastic
UM2332-2
250ns
Plastic
1-5
.(l)UMC
============
UM2333
4K x 8 NMOS ROM
Features
•
Pin compatible with 2732 EPROM
Single +5V ±1 0% power supply
•
Two programmable chip selects for output control
TT L compatible inputs and outputs
•
N-channel silicon gate technology
•
Access time 250/350/450ns (max.)
•
•
•
Three-state outputs
General Description
The UM2333 is a 32,768-bit static MOS read only memory
organized as 4096 words by 8 bits.
Programming of the device is accomplished by a custom
The device is com-
masking process.
The UM2333 is designed for memory
pletely static in operation, and operates from a single
applications where high performance, large bit storage,
+5V power supply. All inputs and outputs are TT L com-
and simple interfacing are important design objectives.
patible.
The two chip select inputs are programmable.
Pin Configuration
Block Diagram
vcc
Au
A7
VCC
A6
As
As
A9
A4
All
A3
CS1/CS1
A2
AlO
A1
CS2/CS2
Ao
07
00
06
01
Os
02
04
GND
03
Ao
GND
ADDRESS INPUT BUFFER
X
DECODER
32.768 BIT
CELL MATRIX
1-6
Y
DECODER
y
CATING
OUTPUT
ENABLE
LOGIC
OUTPUT
BUFFER
-
CS1/CS1
-
CS2/CS2
00
01
02
03
04
Os
06
07
eUMC
UM2333
Absolute Maximum Ratings*
*Comments
o
Ambient temperature under bias, TA ..... -10 to +80 C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied and exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
o
Storage temperature, T STG ........... -65 to +150 C
Applied voltage on any pin with
respect to ground . . . . . . . . . . . . . . . . . -0.5 to +7V
Power dissipation, PD . . . . . . . . . . . . . . . . . . . . . 1.0W
D.C. Electrical Characteristics
(TA = 0 to 70°C, Vee = 5V ± 10% unless otherwise specified)
Limits
Symbol
Parameter
Test Conditions
Units
Min.
Typ.
Max.
VIL
Input low voltage
-.05
0.8
VIH
Input high voltage
2.0
Vee
V
VOL
Output low voltage
IOL =2.1mA
0.4
V
VOH
Output high voltage
IOH = -400J.LA
Vee
V
III
I nput load cu rrent
V 1N = Vee = 5.25V
10
J.LA
I LO
Output leakage current
V OUT = Vee = 5.25V
10
J.LA
100
mA
ICC
2.4
. Vee current
Capacitance
(TA = 25°C
f = 1.0 MHz)
Limits
Symbol
Parameter
Unit
Test Conditions
Typ.
C1N
COUT
Input capacitance
Output capacitance
All pins except pin under
tied to AC ground
Note:
This parameter is periodically sampled and is not 100% tested.
1-7
Max.
7
pF
10
pF
UM2333
A.C. Electrical Characteristics
(TA
= 0 to 70°C,
Vcc
= 5V±
10%)
UM2333
UM2333-1
UM2333-2
Unit
Parameter
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Address access time 1
450
350
250
ns
tco
Output enable delay from CSl/CSl or CS 2 /CS 2
150
120
120
ns
tDF
Output disable delay from CSt/CSt or CS 2 /CS 2
0
100
ns
tOH
Output hold from address change
10
tACC
100
0
100
10
0
10
ns
Test Conditions
Output load .............. 1 TTL load and 100pF
I nput transition time . . . . . . . . . . . . . . . . . . . . . 20ns
Timing reference levels . . . . . . . . . . . . . . . . . . . . . . . .
............. Input = 1.5V, Output = 0.8V and 2.0V
Timing Diagram
ADDRESS
INPUTS
VALID
tACC
CHIP
SELECT
INPUTS
-1
INVALID
VALID
teo
OUTPUTS
HIGH IMPEDANCE
1
/ - tDF
-
VALID
-
Ordering Information
Part Number
Access Time
~
Package
UM2333
450ns
Plastic
UM2333-1
350ns
Plastic
UM2333-2
250ns
Plastic
1-8
r-
eUMC
UM2364/UM2364A
Features
•
•
•
•
•
•
•
•
8192 x 8 Bit organization
Single +5 Volt Supply
Access Time - 200/300/450 ns (max.)
Totally static operation
Completely TT L compatible
24 Pin JEDEC approved pinout
•
•
•
UM2364A - Automatic power down (CE)
UM2364 - non power down version
- programmable chip select (CS)
Three state outputs for wire-OR expansion
EPROMs accepted as program data input
2564 EPROM compatible
General Description
The UM2364A offers an automatic power down feature.
Power down is controlled by the Chip Enable (CE) input.
When CE goes high, the device will automatically power
down and remain in a low power standby mode as long as
CE remains high. This unique feature provides system level
power savings as much as 90%.
The UM2364 and UM2364A high performance Read Only
Memories are organ ized 8192 words by 8 b its with access
times from 200 ns to 450 ns. The ROMs are designed to
be compatible with all microprocessor and similar applications where high performance, large bit storage and simple
interfacing are important design considerations.
Both
ROMs conform to the JEDEC approved pinout for 24 pin
64K ROMs.
Both the UM2364 and UM2364A are pin compatible with
the 2564 EPROM thus eliminating the need to redesign
printed circuit boards for volume mask programmed ROMs
after prototyping with EPROMs.
The UM2364 offers the simplest operation (no power
Its programmable chip select allows two 64K
down.)
ROMs to be OR-tied without external decoding.
Pin Configuration
Block Diagram
A7
Vee
A7
A6
As
A6
A5
A9
As
A4
A12
A4
A3
es
A3
A2
AlO
A2
Al
All
Al
Ao
Os
Ao
01
07
01
02
06
02
03
Os
03
GND
04
GND
65.536 BIT
ROM ARRAY
(256 x 256)
0,
'-:-1>---0,
0,
'----:--1 :::~--'-- d.
'-------'--'--.. ~.-!-- Os
'-----;-1>--:-:--
d.
'-----~_i·~~07
'------,:>-----'---0,
• CHIP SELECT iCSI IS PROGRAMMABLE LOW ACTIVE, HIGH ACTIVE
OR DONT CARE.
1-9
eUMC
UM2364/UM2364A
*Comments
Absolute Maximum Ratings*
0
Temperature Under Bias . . . . . . . . . . . . -10 Cto 80°C
Storage Temperature . . . . . . . . . . . . . . -65°C to 150°C
Voltage on Any Pin with Respect to
Ground. . . . . . . . . . . . . . . . . . . . ..
-0.5V to + 7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. Characteristics
(TA = o°c to + 70°C, Vee
Symbol
=
+5V ± 10%)
Typ.
Parameter
Min.
Max.
Uni~s
Conditions
VO H
Output HIGH Level
2.4
V
10H = -1.0 mA
VOL
V 1H
Output LOW Level
Vee
0.4
V
10L = 3.2 mA
Input HIGH Level
2.0
V
V 1L
I nput LOW Level
-0.5
Vee
0.8
V
III
Input Leakage Current
10
/1A
VIN = OV to Vee
ILO
Output Leakage Current
10
/1A
VOUT = OVto Vee
lee
Operating Supply Current
100
mA
Note 1
IS8
Standby Supply Current
12
mA
Note 2
los
Output Short Circu it Current
90
mA
Note 3
Capacitance
(TA = 25°C, f = 1.0 MHz)
Min.
Max.
Unit
CI
I nput Capacitance
5
pf
V1N = OV
Co
Output Capacitance
5
pf
VOUT = OV
Symbol
Parameter
Conditions
Note: This parameter is periodically sampled and is not 100% tested.
A. C. Characteristics
(T A =00Cto+700C, Vee=+5V ±10%)(Note7)
Symbol
tCYC
Parameter
Cycle Time
UM2364-2
UM2364A·2
UM2364·1
UM2364A-1
Min.
Min.
Max.
200
Max.
300
UM2364
UM2364A
Min.
Unit
450
ns
tAA
Address Access Ti me
tOH
Output Hold After Address Change
tACE
Chip Enable Access Time
200
300
450
ns
tACS
Chip Select Access Time
85
100
150
ns
tLZ
Ouput LOW Z Delay
tHZ
Output HIG HZ Delay
tpu
Power Up Time
tPD
Power Down Time
200
10
300
10
10
0
150
0
100
ns
ns
10
100
0
85
450
10
10
85
Conditions
Max.
150
Note 4
ns
Note 5
ns
Note 6
ns
Note 4
ns
Note 4
Notes:
1. Measured with device selected and outputs unloaded.
2. Applies to "A" versions only and measured with CE = 2.0\1
3. For a duration not to exceed one second.
4. Applies to "A" versions (power down) only.
5. Output low impedance delay (tLZ) is measured form CE going low or CS going active.
6. Output high impedance delay (tHZ) is measured from CE going high or CS going inactive.
7. A minimum 0.5 ms time delay is required after application of Vee (+5V) before proper device operation is achieved.
1-10
(l)UMC
UM2364 / UM2364A
Timing Diagrams
Propagation Delay from Address (CE LOW or CS = Active)
A~~~~~~
t
- - - - -....
D~0~
PREVIOUS DATA
'AA
::::j,
VAUD ADD""S
~
VALID DATA
Propagation Delay from Chip Enable, Chip Select (Address Valid)
____ I4---------tACE
[4]
14------
--------.1
tACS
CS
VALID
14---- tLZ -----i~ ,...,....,....,.-,10---+---------_
+-__ ______________
[5]
~~~A
____
~
~~~~~
tLZ
+-_______JI
VCCCURRENT _ _ _ _
[5]
-------i~
50%
IS6
' - - - - tpD
A.C. Testing Input, Output Waveform
>
2AV
20V
TEST POINTS
O.BV
A.C. Testing Load Circuit
~::OU
<
20V
O.BV
DOUT
OAV
INPUT
~
775U
OUTPUT
AC TESTING: INPUTS ARE DRIVEN AT 2AV FOR A LOGIC
"1" AND OAV FOR A LOGIC "a". TIMING MEASUREMENTS
ARE MADE AT 2.0V FOR A LOGIC "1" AND O.BV FOR A
LOGIC "0". INPUT PULSE RISE AND FALL TIMES ARE 5 ns.
100pf (INCLUDING SCOPE AND JIG)
Figure 1.
Programming Instructions
All UMC Read Only Memories (ROM) utilize computer
asided techniques to manufacture and test custom bit
patterns. The customer's bit pattern and address information can be supplied to UMC in a number of different ways.
UMC can process customer inputs in EPROM, ROM,
PROM, paper tape, and computer punched cards. Contact
your UMC sales representative for complete details on
each of the various data input formats.
Package Availability
Ordering Information
Order
Number
UM2364
UM2364-1
UM2364-2
UM2364A
UM2364A-l
UM2364A-2
Programming instructions are listed at the end of the
Memory Section.
Access
Time
450
300
200
450
300
200
* Not Applicable.
1-11
ns
ns
ns
ns
ns
ns
Operating Standby
cU'rrent
Current
100mA
100mA!
100mA
100mA
100mA
100mA
N.A.*
N.A.
N.A.
12mA
12mA
12mA
Package
Type
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
(DUMC
UM2366/ UM2366A
=============
BK
x B NMOS ROM
Features
•
•
•
•
•
•
•
2765 EPROM pin compatible
8192 x 8 bit organization
Single + 5 volt supply
Access time - 200/300/450 ns (max)
Totally static operation
Completely TT L compatible
28 Pin JEDEC approved pinout
•
•
•
•
UM2366A
automatic power down (CE)
output enable function (OE)
two programmable chip selects (CS)
UM2366
non power down version
- four programmable chip sel~cts (CS)
Three state outputs for wire-or expansion
EPROMs accepted as program data input
Description
The UM2366 and UM2366A high performance Read Only
Memories are organized 8192 words by 8 bits with access
times from 200 ns to 450 ns. The ROMs are designed to be .
compatible with all microprocessor and similar applications
where high performance, large bit storage and simple interfacing are important design considerations. Both ROMs
conform to the JEDEC approved pinout for 28 pin 64K
ROMs.
The UM2366 offers the simplest operation
(no power
down.) Its four programmable chip selects allow up to
sixteen 64K ROMs to be OR-tied without external decoding.
The UM2366A offers an automatic power down feature.
Power down is controlled by the Chip Enable (CE) input.
When CE goes high, the device will automatically power
down and remain in a low power standby mode as long as
CE remains high. This unique feature provides system level
power savings as much as 90%. An additional feature of the
This
UM2366A is the Output Enable (OE) function.
eliminates bus contention in multiple bus microprocessor
systems. The two programmable Chip Selects (CS) allow
up to four 64K ROMs to be OR-tied without external
decoding.
Both the UM2366 and UM2~66A are pin compatible with
the 2764 EPROM thus eliminating the need to redesign
printed circuit boards for volume mask programmed ROMs
after prototyping with EPROMs.
Block Diagram
Pin Configuration
Ne
vee
Ne
A12
eSl*
A12
Vee
eSl*
A7
eS2*
As
A7
eS2*
A6
11.6
As
As
A9
As
A9
A4
Au
CS3*
A4
All
A3
A3
OE
A2
AlO
A2
AlO
Al
eS4*
Al
eE
Ao
Os
01
02
07
06
03
°s
°2
03
GND
04
GND
65,536 BIT
ROM ARRAY
1256 x 256)
Os
01
°7
06
°s
°4
~~~:~S~~~~.TS cs ARE PROGRAMMABLE LOW ACTIVE, HJG~ ACTIVE OR
UM2366 / UM2366A
Absolute Maximum Ratings*
*Comments
Temperature Under Bias ............ -10°C to 80°C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent demage to the device. These
are stress ratings only. Functional operation of this device
at these or any other conditions above those indicated on
the operational sections of this specification is not implied
and exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Storage Temperature . . . . . . . . . . . . . . -65°C to 150°C
Voltage on Any Pin with Respect to Ground
-O.5V +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
D.C. Characteristics
(T A = OoC to + 70°C, Vee = +5V
Symbol
± 10%)
Parameter
Min.
VOH
Output HIGH Level
2.4.
VOL
Output LOW Level
VIH
V 1L
III
Input HIGH Level
2.0
Input LOW Level
-0.5
Typ.
Max.
Units
Vee
0.4
V
Conditions
10H
V
10L
Vee
0.8
V
Input Leakage Current
10
p,A
VIN
ILO
Output Leakage Current
10
p,A
VOUT
= -1.0 mA
= 3.2 mA
V
= OV to Vee
= OV to Vee
lec
Operating Supply Current
100
mA
Note 1
IS8
Standby Supply Current
12
mA
Note 2
los
Output Short Circuit Current
70
mA
Note 3
Capacitance
(T A = 25°c f = 1.0 MHz)
Max.
Unit
CI
Input Capacitance
5
pf
VIN = OV
Co
Output Capacitance
5
pf
VOUT = OV
Symbol
Parameter
Min.
Conditions
Note: This parameter is periodically sampled and is not 100% tested.
A.C. Characteristics
(T A = ooC to + 70°C, Vee = +5V ± 10%)
Symbol
(Note 7)
Parameter
UM2366·2
UM2366A·2
Min.
teye
Cycle Time
tAA
Address Access Time
tOH
Output Hold After Address
Change
Max.
200
UM2366·1
UM2366A·1
Min.
Max.
300
200
10
UM2366
UM2366A
Min.
450
450
10
ns
ns
tAeE
Chip Enable Access Time
200
300
450
ns
tAes
Chip Select Access Time
85
100
150
ns
150
ns
tAOE
Output Enable Access Time
tLZ
Output LOW Z Delay
tHZ
Output HIGH Z Delay
tpu
Power Up Time
tpD
Power Down Time
85
10
100
10
.10
85
0
0
85
..
100
150
0
100
Condition
ns
300
10
Unit
Max.
150
Note 4
Note 4
ns
Note 5
ns
Note 6
ns
Note 4
ns
Note 4
Notes:
1. Measured with device selected and outputs unloaded.
2. Applies to "A" versions only and measured with CE = 2.0V.
3. For a duration not to exceed one second.
4. Applies to "Au versions (power down) only.
5. Output low impedance delay (tLZ) is measured from CE and CJE goJ.!:!g low and CS going active, whichever occurs last.
6. Output high impedance delay (tHZ) is measured from either CE or OE going high or CS going inactive, whichever occurs
first.
7. A minimum 0.5 ms time delay is required after application of Vee (+5V) before proper device operation is achieved.
1-13
UM2366/ UM2366A
Timing Diagrams
Propagation Delay from Address (CE = OE = LOW, CSICS = Active)
VALID DATA
Propagation Delay from Chip Enable, Chip Select (Address Valid)
(4)
(6)
CS/CS
DATA
OUT--------~~~~~~------------------t_~~~~
~~~~--~--------------JI
VCCCURRENT~
______~__________JI
IS8
A.C. Testing Input, Output Waveform
2.4V
>
2.0V
TEST POINTS
O.BV
A.C. Testing Load Circuit
~::on
<
2.0V
O.BV
DOUT
0.4V
INPUT
~
• mn
OUTPUT
AC TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC
"1" AND O.4V FOR A LOGIC "0". TIMING MEASUREMENTS
ARE MADE AT 2.0V FOR A LOGIC "1" AND O.BV FOR A
LOGIC "0". INPUT PU LSE RISE AND FALL TIMES ARE 5 ns.
. ''''''' "NCCUD'NG SCDP' AND","'
Figure 1.
Programming Instructions
Ordering Information
All UMC Read Only Memories (ROM) utilize compLl'ter
aided techniques to man~facture and test custom bit
patterns. The customer's bit pattern and address information can be supplied to UMC in a number of different
ways. UMC can process customerinputs in EPROM, ROM,
PROM, paper tape, and computer punched cards. Contact
your UMC sales representative for complete details on each
of the various data input formats.
Part
Number
UM2366
UM2366-1
UM2366-2
UM2366A
UM2366A-l
UM2366A-2
Programming instructions are listed at the end of the
Memory Section.
1-14
. Access Operating
Time
Current
450
300
200
450
300
200
ns
ns
ns
ns
ns
ns
100 mA
100mA
100 mA
100 mA
mOmA
100mA
Standby
Current
Package
Type
N.A.
N.A.
N.A.
12mA
12mA
12mA
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
(l)UMO
UM23128/UM23128A
16K X 8 NMOS ROM
Features
• EPROM pin compatible
• 16,384 x 8 bit organization
• single +5 volt supply
• Access time - 200/300/450 ns (max)
• Totally static operation
• Completely TTL compatible
• 28 pin JEDEC approved pinout
•
•
•
•
UM23128A- automatic power down (CE)
output enable function (OEl
one programmable chip select (CS)
UM23128
non power down version
three programmable chip selects (CS)
Three state outputs for wire-OR expansion
EPROMS accepted as program data input
Description
The UM23128 and UM23128A high performance Read
Only Memories are organized 16,384 words by 8 bits with
access times from 200 ns to 450 ns. The ROMs are'designed to be compatible with all microprocessor and similar
applications where high performance, large bit storage and
simple interfacing are important design considerations.
Both ROMs conform to the JEDEC approved pinout for
28 pin 128K ROMs.
The UM23128 offers the simplest operation
(no power
down.) Its three programmable chip selects allow up to
eight 128K ROMs to be OR-tied without external decoding.
The UM23128A offers an automatic power down feature.
Power dovyn is controlled by the Chip Enable (CE) input.
When CE goes high, the device will automatically power
down and remain in a low power standby mode as long as
CE remains high. This unique feature provides system level
power savings as much as 90%. An additional feature of
the UM23128A is the Output Enable (OE) function. This
eliminates bus contention in multiple bus microprocessor
systems. The programmable chip select allows two 128K
ROMs to be OR-tied without external decoding.
Both the UM23128 and UM23128A are pin compatible
with EPROMs thus eliminating the need to redesign printed
circuit boards for volume mask programmed ROMs after
prototyping with EPROMs.
Block Diagram
Pin Configuration
A3
A.
As
A.
Ne
AU
A7
A6
As
A4
A3
vee
eS1 *
Al3
As
Ne
Al2
A7
Vee
eS1*
A13
As
A9
As
A9
All
eS2*
A4
All
OE
A2
AlO
A1
eS3*
Ao
01
Os
07
°2
03
GND
06
°1
02
°s
04
GND
131,072 BIT
AS
ROM ARRAY
A9
(512x256)
All
A6
A3
A2
A1
A7
AI3
Ao
AI
A,
AIO
All
01
I..:....II"""'--_'
0,
-c-:---.~~-03
0.
Ao
'-----:-''--1>-:.-0,
~----.--I>--'--06
~---';-:--1:>--J--07
~-------'-.J>'--"!""-'Os
03
CS,
CS3
"CHIP SELECTS (CS) ARE PROGRAMMABLE LOW ACTIVE, HIGH ACTIVE, OR
DON'TeARE,
1-15
SUMC
UM23128/UM23128A
Absolute Maximum Ratings*
*Comments
Temperature Under Bias . . . . . . . . . . . . _10°C to 85°C
Storage Temperature . . . . . . . . . . . . . . -65°C to 150°C
Voltage on Any Pin with Respect to Ground
. . . . . . . . . . . . . . . . . . . . . . . . . . . . -3.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Electrostatic Discharge Rating (ESD)**
Inputs to Ground . . . . . . . . . . . . . . . . . . . ± 2000V
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress ratings only. Functional operation of this device
at these or any other conditions above those indicated on
the operational sections of this specification is not implied
and exposure to absolute maximum rating conditions for
extended periods may affect device reliabil ity.
**Test Condition: MI L-STD-883B Method 3015.1
D.C. Characteristics
(T A = ooC to + 70°C, Vee = +5V ± 10%)
Symbol
VOH
VOL
VIH
VIL
III
ILO
Icc
Iss
los
Parameter
Output HIGH Level
Output LOW Level
Input HIGH Level
Input LOW Level
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Supply Current
Output Short Circuit Current
Min.
2.4
Typ.
Max.
Vee
0.4
Vee
0.8
10
10
100
10
90
2.0
-3.0
Units
V
V
V
V
Conditions
10H =-1.0 mA
10L = 3.2 mA
VIN = OV to Vee
VOUT - OV to Vee
Note 1
Note 2
Note 3
f.l.A
f.l.A
mA
mA
mA
Capacitance
(T A = 25°c, f = 1.0 MHz)
Symbol
Parameter
I nput Capacitance
CI
Output Capacitance
Co
Min.
Max.
5
5
Unit
pf
pf
Conditions
VIN = OV
VOUT = OV
Note: This parameter is periodically sampled and is not 100% tested.
A.C. Characteristics
(T A = OOC to + 70°C, Vee = +5V ± 10%) (Note 7)
UM23128-2
UM23128A-2
Symbol
Parameter
teye
tAA
tOH
tAeE
tAes
tAOE
tLZ
tHZ
tPu
tPD
Cycle Time
Address Access Time
Output Hold After Address
Change
Chip Enable Access Time
Chip Select Access Time
Output Enable Access Time
Output LOW Z Delay
Output HIGH Z Delay
Power Up Time
Power Down Ti me
Min.
200
UM23128-1
UM23128A-1
Max.
Min.
300
200
10
'Max.
200
85
85
85
450
150
150
10
100
0
100
450
300
100
100
150
0
120
Unit
Conditions
Max.
10
10
0
Min.
450
300
10
10
UM23128
UM23128A
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 4
Note 4
Note 5
Note 6
Note 4
Note 4
Notes:
1. Measured with device selected and outputs unloaded.
2. Applies to "A" versions only and measured with CE = 2.0V.
3. For a duration not to exceed one second with VOUT = OV
4, Applies to "A" versions (power down) only.
5. Output low impedance delay (tLZ) is measured from CE and OE going low and CS going active, whichever occurs last.
6. Output high impedance delay (tHZ) is measured from either CE or OE going high or CS going inactive, whichever occurs
first.
7. A minimum 0.5 ms time delay is required after application of Vee (+5V) before proper device operation is achieved.
1-16
UM23128/UM23128A
Timing Diagrams
Propagation Delay from Address (CE
r
ADDRESS
INPUTS _ _ _ _ _
DATA
OUT
=TIE = LOW,
1
CS/CS
= Active)
r
VALID ADDRESS
,~--------------------'~
,"'V'OUSDATA:,:AA
VAUDDATA'
'0" ) - - - -
Propagation Delay from Chip Enable, Chip Select (Address Valid)
(41
cs/cs
DATA
OUT-----~--~~~~----------~~~~~
vcc CURRENT _ _ _ _- I_ _ _ _ _"""I
ISB
A.C. Testing Input, Output Waveform
2AV
>
2.0V
TEST POINTS
O.BV
<
2.0V
OU
O.BV
DOUT
OAV
INPUT
:
-=d
A.C. Testing Load Circuit
OUTPUT
775U
AC TESTING: INPUTS ARE DRIVEN AT 2AV FOR A LOGIC
"1" AND OAV FOR A LOGIC "0". TIMING MEASUREMENTS
ARE MADE AT 2.0V FOR A LOGIC "1" AND O.BV FOR A
LOG IC "0". INPUT PULSE RISE AND FALL TIMES ARE 5 ns.
lOOpf (INCLUDING SCOPE AND JIGI
Figure 1.
Ordering Information
Programming Instructions
All UMC Read Only Memories (ROM) utiliz.e computer
asided techniq'ues to manufacture and test custom bit
patterns. The customer's bit pattern and address information can be supplied to UMC in a number of different
ways. UMC can process customer inputs in EPROM, ROM,
PROM, paper tape, and computer punched cards. Contact
your UMC sales representative for complete details on
each of the various data input formats.
Part
Number
UM23128
UM23l28-l
UM23128-2
UM23l28A
UM23l28A-l
UM23l28A-2
Programming instructions are listed at the end of the
Memory Section.
1-17
Access
Time
450
300
200
450
300
200
ns
ns
ns
ns
ns
ns
Operating
Current
Standby
Current
Package
Type
100mA
100mA
100mA
100mA
100mA
100mA
N.A.
N.A.
N.A.
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
10mA
10mA
10mA
eUMC
UM23256/ UM23256A
Features
•
•
•
•
•
•
•
EPROM pin compatible
32,768 x 8 bit organization
Single +5 volt supply
Access time-200/300/450ns (max)
Totally static operation
Completely TTL compatible
28 Pin JEDEC approved pinout
•
•
•
•
UM23256A- automatic power down (CE)
output enable function (OE)
UM23256
non power down version
two programmable chip
selects (CS)
Three state outputs for wire-OR expansion
EPROMs accepted as program data input
General Description
The UM23256 and UM23256A high performance Read
Only Memories are organized 32,768 words by 8 bits with
access times from 200 ns to 450 ns. The ROMs are
designed to be compatible with all microprocessor and
similar applications where high performance, large bit
storage and simple interfacing are important design considerations. Both ROMs conform to the JEDEC approved
pinout for 28 pin 256K ROMs.
Power down is controlled by the Chip Enable (CE) input.
When CE goes high, the device will automatically power
down and remain in a low power stand-by mode as long as
CE remains high. This unique feature provides system level
power savings as much as 90%. An additional feature of
the UM23256A is the Output Enable (OE) function. This
eliminates bus contention in multiple bus microprocessor
systems.
The UM23256 offers the simplest operation (no power
down.) Its two programmable chip selects allow up to four
256K ROMs to be OR-tied without external decoding.
Both the UM23256 and UM23256A are pin compatible
with EPROMs thus eliminating the need to redesign printed
circuit boards for volume mask programmed ROMs after
prototyping with EPROMs.
The UM23256A offers an automatic power down feature.
Block Diagram
Pin Configuration
262. 144BIT
ROW'ARRAY
(512x512l
0,
t..;....I">--'--02
"---''-'---1>--;-03
L---'-I~---';-
o.
L---'-:----I:>--;--O,
·CHIP SELECTS (CS) ARE PROGRAMMABLE LOW ACTIVE,
HIGH ACTIVE OR DON'T CARE
1-18
UM23256/UM23256A
Absolute Maximum Ratings*
*Comments
Temperature Under Bias . . . . . . . . . . . . _10°C to 85°C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated on the operational sections of this specification
is not implied and exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Storage Temperature . . . . . . . . . . . . . . -65°C to 150°C
Voltage on Any Pin with Respect to Ground
. . . . . . . . . . . . . . . . . . . . . . . . . . . -3.5V to + 7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
D. C. Characteristics
(TA
= ooc to
+ 70°C, Vee
Symbol
= +5V ± 10%)
Parameter
VO H
Output HIGH Level
VOL
Output LOW Level
VIH
V 1L
Input HIGH Level
Vu
Min.
Max . .
Typ.
Conditions
Units
= -1.0 mA
= 3.2 mA
2.4
Vee
0.4
V
10H
V
10L
2.0
Vee
0.8
V
I nput Leakage Current
10
J.l.A
V 1N
ILO
Output Leakage Current
10
J.l.A
V OUT
Input LOW Level
-3.0
V
= OV to Vee
= OV to Vee
lee
Operating Supply Current
100
mA
Note 1
ISB
Standby Supply Current
10
mA
Note 2
los
Output Short Circuit Current
90
mA
Note 3
Capacitance
(TA = 25°C, f = 1.0 MHz)
Max.
Unit
Conditions
CI
I nput Capacitance
5
pf
VIN = OV
Co
Output Capacitance
5
pf
V OUT = OV
Symbol
Parameter
Min.
Note: This parameter is periodically sampled and is not 100% tested.
A. C. Characteristics
(TA = ooC to + 70°C, Vee = +5V ± 10%) (Note 7)
Symbol
Parameter
23256-2
23256A-2
Min.
tCYC
Cycle Time
tAA
Address Access Time
Max.
200
23256-1
23256A-1
Min.
Max.
300
23256
23256A
Min.
10
Conditions
ns
450
450
300
200
Unit
Max.
ns
ns
10
tOH
Output Hold After Address Change
tAcE
Chip Enable Access Time
200
300
450
ns
tAes
Chip Select Access Time
85
100
150
ns
tAOE
Output Enable Access Time
150
ns
Note 4
tLZ
Ouput LOW Z Delay
ns
Note 5
tHz
Output HIGH Z Delay
tpu
Power Up Time
tpD
Power Down Time
10
85
10
100
10
10
100
85
a
0
0
100
150
120
150
Note 4
ns
Note 6
ns
Note 4
ns
Note 4
Notes:
1. Measured with device selected and outputs unloaded.
2. Applies to "A" versions only and measured with CE = 2.0V.
3. For a duration not to exceed one second with VOUT = OV.
4. Applies to "Au versions (power down) only.
5. Output low impedance delay (tLZ) is measured from CE and OE going low and CS going active, whichever occurs last.
6. Output high impedance delay (tHZ) is measured from either CE or OE going high or CS going inactive, whichever occurs
first.
7. A minimum 0.5 ms time delay is required after application of Vce (+5V) before proper device operation is achieved.
1-19
UM23256jUM23256A
Timing Diagrams
t
Propagation Delay from Address (CE = OE = LOW, CS/CS = Active)
ADDRESS
INPUTS
~
- - - - - - 4-
VALID ADDRESS
tAA_
-to--------
DATA-----------~------~I~----------------------~-----~II,.------.--
OUT
PREVIOUS DATA VALID
VALID DATA
Propagation Delay from Chip Enable, Chip Select (Address Valid)
(4)
________~I~~---------tAeE
1_ _- - - -
tAes
es/es
DATA
OUT----------~---------t-L-z----------~,~~--~~~~-~K~----~----------'I
ICC - - - - - - - -
- - - - - - -
VeeeURRENT __________~--------'1
IS8
_--------------------+-------~,50""{'
A.C. Testing Input, Output Waveform
50%
--- --
A.C. Testing Load Circuit
+5V
2AV
2.0V
)
0.8V
OAV
<
2.0V
TEST POINTS
0.8V
INPUT
7751l
AC TESTING: INPUTS ARE DRIVEN AT 2AV FOR A LOGIC
"1" AND OAV FOR A LOGIC "0". TIMING MEASUREMENTS
ARE MADt AT 2.0V FOR A LOGIC "1" AND 0.8V FOR A
LOGIC "0". INPUT PULSE RISE AND FALL TIMES ARE 5 ns.
t
T
...
lOOp' "NClUDING SCOPE ANDJIG
'----
1-
Figure 1.
Ordering Information
Part
Number
UM23256
UM232!?6-1
UM23256-2
UM23256A
UM23256A-l
UM23256A-2
Access
Time
450
300
200
450
300
200
ns
ns
ns
ns
ns
ns
Operating
Current
Standby
Current
Package
Type
100mA
100mA
100 mA
100mA
100 mA
100mA
N.A.
N.A.
N.A.
10mA
10 mA
10mA
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
1-20
GBUMC
Static RAM
Selection Guide
Descriptions
Compatible Devices
UM2147
4Kxl High Speed NMOS SRAM
SYP 2147
UM2148
1 Kx4 High Speed NMOS SRAM
UM2149
1 Kx4 High Speed NMOS SRAM
Syp 2149
UM6104
1 Kx4 CMOS SRAM
HM 4334
Part No.
SYP 2148
Remarks
Page
Access Time 70, 55,45 ns
2-3
Access Time 70,55,45 ns
2-8
Access Time 70, 55, 45 ns
2-13
Access Time 250, 200, 150,
120 ns for 5V, 2IJ.s for
2-18
2.5V Operating
UM6104-1
1 Kx4 CMOS SRAM
UM6114
1Kx4 CMOS SRAM
UM6116-2/3/-4
2Kx8 High Speed CMOS SRAM
UM6116-5
2Kx8 High Speed CMOS SRAM
TC 5047AP
2-23
Access Time 100, 70, 55,45 ns
2-28
lOT 6116
Access Time 70, 90, 120 ns
2-33
lOT 6116
Access Time 55 ns
2-38
\
UM6164
8Kx8 H'igh Speed CMOS SRAM
IOT7164
Access Time 70, 55,45 ns
2-43
UM6167
16K.xl High Speed CMOS SRAM
HM 6167
Access Time 70,55,45 ns
2-50
UM6168
4Kx4 High Speed CMOS SRAM
HM 6168
Access Time 70,55,45 ns
2-55
2-2
SUMO
UM2147
High Speed NMOS SRAM
Features
• No clocks or strobes required
• Total TTL compatible:
All inputs and outputs
• Automatic CE power down
• Separate data input and output
•
•
• 45 ns maximum access time
Identical cycle and access times
High density 18-pin package
• Three-state output
• Single +5V supply (± 10%)
• Pinout and function compatible to SY2147
General Description
The UM2147 offers an automatic power down feature.
Power down is controlled by the Chip Enable input. When
Chip Enable (CE) goes high, thus deselecting the UM2147
the device will automatically power down and r€main
in a standby power mode as long as CE remain high. This
unique feature provides system level power savings as
much as 80%.
The UMC UM2147 is a 4096-Bit Static Random Access
Memory organized 4096 words by 1-bit and is fabricated
using UMC's new scaled N-channel silicon gate technology.
It is designed using fully static circuitry, therefore requiring
no clock or refreshing to operate. Address set-up times
are not required and the data is read out non-destructively
with the same polarity as the input data. Separate data
input and output pins provide maximum design flexibility.
The three-state output facilitates memory expansion by
allowing the outputs to be OR-tied to other devices.
Pin Configuration
The UM2147 is packaged in an 18-pin DIP for the highest
possible density. The device is fully TTL compatible and
has a si ngle +5V. power supply.
Block Diagram
A1
AO
vcc
A1
A6
A2
A7
A3
As
A4
A9
As
A10
DOUT
All
WE
DIN
GND
-VCC
_GND
ROW
SELECT
As
DIN
------I.~
CE
-11-,
CE - -.....
2-3
MEMORY ARRAY
64 ROWS
64 COLUMNS
UM2147
Absolute Maximum Ratings*
*Comments
Temperature Under Bias . . . . . . . . . . . . . -10° C to 85°C
Storage Temperature . . . . . . . . . . . . . . _65° C to 150°C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those indicated in the operational sections of this specification is
not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Voltage on Any Pin with Respect
to Ground . . . . . . . . . . . . . . . . . . . . . -3.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 1.2W
D.C. Characteristics
(TA;; O°C to +70°C, Vee;; 5V ± 10% Unless otherwise specified) (Note 8)
2147 /-1/-2
Symbol
Parameter
Units
Min.
Input Load Current
III
(All input pins)
Output Leakage Current
IILol
lee
Power Supply Current
ISB
Standby Current
Peak Power-on Current
Ipo
2147 L1L~
(Note 9)
Max.
Min.
Conditions
Max.
10
10
IJ.A
50
50
IJ.A
150
115
mA
TA = 25°C
160
125
mA
T A = O°c
20
10
mA
Vee = Min to Max, CE = V IH
50
30
mA
Vee;; Max, V,N ;; Gnd to Vee
CE;; V'H, Vee;; Max.
VOUT ;; Gnd to 4.5V
Vee =Max. CE =V,L
Outputs Open
Vee = Gnd to Vee Min
CE = Lower of Vee or V,H Min
V ,L
I nput Low Voltage
-3.0
0.8
-3.0
0.8
V
V ,H
Input High Voltage
2.0
6.0
2.0
6.0
V
VOL
Output Low Voltage
0.4
V
IOL = 8 mA
V OH
Output High Voltage
V
IOH = -4.0mA
0.4
2.4
2.4
Capacitance
(TA;;25°C, f= 1.0MHz)
Symbol
Test
COUT
C,N
Typ.
Max.
Unit
Output Capacitance
6
pF
Input Capacitance
5
pF
Note: This parameter is periodically sampled and not 100% tested.
2-4
SUMC
UM2J47
A.C. Characteristics
(TA = o°c to +70°C, Vcc = 5V ±10% Unless otherwise speCified) (Note 8,10)
READ CYCLE
2147/L
Symbol
2147·1/L·1
2147-2
Parameter
Unit
Min.
Max.
Min.
Max.
Min.
Notes
Max.
tRC
Read Cycle Time
tAA
Address Access Time
70
55
45
ns
tACE1
Chip Enable Access Time
70
55
45
ns
1
tACE2
Chip Enable Access Time
80
65
45
ns
2
tOH
Output Hold from Address Change
5
5
5
ns
tLZ
Chip Selection to Output in Low Z
10
10
5
ns
7
tHZ
Chip Deselection to Output in High Z
0
ns
7
tpu
Chip Selection to Power Up Time
0
tpo
Chip Dese'lection to Power Down Time
70
55
40
0
30
0
30
0
0
20
30
ns
45
ns
20
ns
WRITE CYCLE
twc
Write Cycle Time
70
55
45
ns
tcw
Chip Enabled to End of Write
55
45
45
ns
tAW
Address Valid to End of Write
55
45
45
ns
t AS
Address Setup Ti me
0
0
0
ns
twp
Write Pulse Width
40
25
25
ns
tWR
Write Recovery Time
15
10
0
ns
tow
Data Valid to End of Write
30
25
25
ns
tOH
Data Hold Time
10
10
10
ns
twz
Write Enabled to Output in High Z
0
tow
Output Active from End of Write
0
35
0
0
2-5
25
0
0
25
ns
7
ns
7
UM2147
Timing Diagrams
READ CYCLE NO.1 (NOTES 3 AND 4)
ADDRESS
~
:i_._____________
________________t_RC_______________
~tOH~:I.
DATA OUT PREV IOUS DATA V ALiD
~
~ XX~:::::::::::::D:A:T:A:V:A:L:I:D:::::::::::::::
READ CYCLE NO.2 (NOTES 3 AND 5)
tRC
--"10-
~k-
tACE
!---tLZ
HIGH IMPEDANCE T
DATA OUT
~
I--tpu
VCC
SUPPLY
CURRENT
~
I
-
tHZ
XXjr
:V
-
DATA VALID
HIGH
IMPEDANCE
5~-----
-tPD
------
I CC
ISS--------
,
50%
WRITE CYCLE NO.1 (WE CONTROLLED) (NOTE 6)
..
twc
ADDRESS
~~
)
•
CE
\\\
...
tcw
~k-
il
~
//L/I/
tAW
tAS
- t w P _ _ . . --tWR--
--j
WE
\:\
t=
DATA IN
,
r
tDH
-tow
DATA VALID
I
i--twzDATA OUT
"
DATA UNDEFINED
~
I--towHIGH IMPEDANCE
Notes:
1. Chip deselected for greater than 55 ns prior to selection.
2. Chip deselected for a finite time that is less than 55ns prior to selection. (If the deselect time is Qns, the chip is by
definition selected and access occurs according to Read Cycle No.1.).
3. WE is high for Read Cycles.
4. Device is continuously selected, CE = VI L.
5. Addresses valid prior to or coincident with CE transition low.
6. If CE goes high simultaneously with WE high, the outputs remain in the high impedancestate.
7. Transition is measured ± 500mV from low or high impedance voltage with load B. This parameter is sampled and not
100% tested.
8. The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute;
9. A pullup resistor to Vce on the CE input is required to keep the device deselected: otherwise, power-on current approaches Ice active.
10. A minimum 0.5 ms time delay is required after application of VCC (+5V) before proper device operation is achieved.
2-6
UM2147
WRITE CYCLE NO.2 (CE CONTROLLED) (NOTE 6)
.
twc
ADDRESS
:J~
j~
I--tAS
tcw
~~
CE
)ftAW
!-tWR-
/---twp
WE
\\\\\\\\\\\~~
)f- /
/
/
/
/
/
/
/
/
tDH
tow
~~
DATA IN
)~
DATA VALID
____________________________________·1
f..--twz-
DATA OUT
~~-------------------
DATA UNDEFINED
A.C. Testing Input, Output Waveform
3.0V
HIGH IMPEDANCE
A.C. Testing Load Circuit
<
2.0V
1.5V -TEST POINTS
+5V
0.8V
OV---INPUT
+5V
510n
510n
OUTPUT
DOUT - - , - - - - i
30pF
(INCLUDING
SCOPE AND
JIG)
A.C. TESTING: INPUTS ARE DRIVEN AT 3.0V FOR A
LOGIC "'" AND O.OV FOR A LOGIC "0". TIMING MEASUREMENTS ARE MADE AT 2.0V FOR A LOGIC "1" AND
0.8V FOR A LOGIC "0" AT THE OUTPUTS. THE INPUTS
ARE MEASURED AT 1.5V. INPUT RISE AND FALL TIMES
ARE 5 ns.
300
=
LOAD B.
LOAD A.
Ordering Information
Part
Number
Access
Time
(Max.)
5pF
Operating
Current
(Max.)
Stand by
Current
(Max.)
Package
Type
Plastic
UM2147
70 ns
160mA
20mA
UM2147-1
55 ns
180 mA
30mA
Plastic
UM2147-2
45 ns
180mA
30mA
Plastic
UM2147L
70 ns
140mA
10mA
Plastic
UM2147L-1
55 ns
125mA
15mA
Plastic
2-7
(DUMO
=========
UM2148
1K
x
4 High Speed NMOS SRAM
Features
• 45 ns maximum access time
•
Industry standard 2114 pinout
•
No cloS;ks or strobes required
•
Totally TTL compatible all inputs and outputs
•
Automatic CE power down
•
Common data input and output
•
Identical cycle and access times
•
High density 18-pin package
•
Single+5V supply (± 10%)
•
Three-state output
•
Pinout and function compatible to SY2148
General Description
The UMC UM2148 is a 4096-Bit Static Random Access
Memory organized 1024 words by 4 bits and is fabricated
using UMC's new scaled N-channel silicon.gate technology.
It is designed using fully static circuitry, therefore requiring
no clock or' refreshing to operate. Address set-up times are
not required and the data is read out non-destructively
with the same polarity as the input data. Common data
input and output pins provide maximum design flexibility.
The three-state output facilitates memory expansion by
allowing the outputs to be OR-tied to other devices.
Pin Configuration
The UM2148 offers an automatic power down feature.
Power down is controlled by the Chip Enable input. When
Chip Enable (CE) goes high, thus deselecting the UM2148
the device will automatically power down and remain in
a standby power mode as long as CE remains high. This
unique feature provides system level power savings as
much as 85%.
The UM2148 is packaged in an 18-pin DIP for ~he highest
possible density. The device is fully TTL compatible and
has a single +5V power supply.
Block Diagram
-VCC
4-'---
ROW
SELECT
2-8
MEMORY ARRAY
64 ROWS
64COLUMNS
GND
GDUMC
UM2J.48
Absolute Maximum Ratings*
* Comments
Temperature Under Bias . . . . . . . . . . . . . _10°C to 85°C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Storage Temperature . . . . . . . . . . . . . . -65°C to 150°C
Voltage on Any Pin with Respect
to Ground . . . . . . . . . . . . . . . . . . . : . -3.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
D.C. Characteristics
o
(TA=O°Cto +70 C, vee =5V ±10% Unless otherwise specified) (note 8)
Symbol
2148/-1/-2
2148L/L-1
Min.
Min.
Parameter
Units
Input Load Current
III
(All input pins)
IILol
Output Leakage Current
lee
Power Supply Current
Peak Power-on Current
Ipo
Conditions
Max.
10
10
JJ.A
50
50
JJ.A
140
115
mA
Vee = Max, V IN = Gnd to Vee
CE = VIH , Vee = Max
VOUT = Gnd to 4.5V
T A= 25°C
Vee = Max, CE = VIL
.,
Standby Current
ISB
Max.
(Note 9)
150
125
mA
TA=O°C
30
20
mA
Vee = Min to Max. CE= VIH
50
30
mA
Vee = Gnd to Vee Min
CE = Lower of Vee or VIH Min
V IL
Input Low Voltage
-3.0
O.S
-3.0
O.S
V
V 1H
Input High Voltage
2.0
6.0
2.0
6.0
V
VOL
Output Low Voltage
0.4
V
IOL = SmA
V OH
Output High Voltage
V
IOH = --4mA
0.4
2.4
2.4
Outputs Open
Capacitance
(TA = 25°C, f = 1.0 MHz)
Symbol
TeSt
C OUT
CIN
Typ.
Max.
Unit
Output Capacitance
7
pF
I nput Capacitance
5
pF
, Note: This parameter is periodically sampled and not 100% tested.
2-9
@}UMC
UM2148
A.C. Characteristics
0
(TA =0° eto +70 C, Vcc = 5V ±10% Unless otherwise specified) (Note 8)
READ CYCLE
2148/L
2148-1/L-1
2148-2
Unit
Parameter
Svmbol
Min.
Max.
70
Min.
Max.
Min.
Conditions
Max.
tRC
Read Cycle Time
45
tAA
Address Access Time
70
55
45
ns
t ACE1
Chip Enable Access Time
70
55
45
ns
Note 1
tACE2
Chip Enable Access Time
80
65
55
ns
Note 2
tOH
Output Hold from Address Change
5
5
5
ns
tLz
Chip Selection to Output in Low Z
10
10
10
ns
Note 7
tHZ
Chip Deselection to Output in High Z
0
ns
Note 7
tpu
Chip Selection to Power Up Time
0
tpo
Chip Deselection to Power Down Time
55
20
0
20
0
30
0
ns
20
ns
0
30
30
ns
WRITE CYCLE
tWE
Write Cycle Time
70
55
45
ns
tcw
Chip Enabled to End of Write
65
50
40
ns
tAW
Address Valid to End of Write
65
50
40
ns
tAS
Address Setup Time
0
0
0
ns
twp
Write Pulse Width
50
40
35
ns
tWR
Write Recovery Time
5
5
5
ns
tow
Data Valid to End of Write
25
20
20
ns
tOH
Data Hold Time
0
0
0
ns
twz
Write Enabled to Output in High Z
0
tow
Output Active from End of Write
0
25
0
0
2-10
20
0
0
15
ns
Note 7
ns
Note 7
UM2148
Timing Diagrams
READ CYCLE NO.1 (NOTES 3 AND 4)
§
-----------------t RC ----------------~1.
ADDRESS
~""---t-AA------------*'-----tOH
DATA VALID
DATAOUT PREVIOUSDATAVALID
READ CYCLE NO.2 (NOTES 3 AND 5)
----------------~
14r----------------- tRC
HIGH
DATAOUT--~~~~~~~~'~~~r~------D-A-T-A__
V_A_L_ID____~--J
IMPEDANCE
vcc
SUPPLY
CURRENT
tpuj
ICC - - - - - - IS8 - - - - -
WRITE CYCLE NO.1 (WE CONTROLLED) (NOTE 6)
twe
ADDRESS
- 1l
\
~
tew
j"- / /
tE:
tAW
tAS
J
~
DATA IN
~twp_
l
\'
r
4-
/ / / L.L
-tWR-
J~
tDH
tow
DATA VALID
~twz
~
________________________________
DATA OUT _______...;D;;,,;A..;.T;.;,A..;,...;;U.;,.N_D_E_F_IN_E_D
___________
)
HIGH
~E
IMPEDAN~:---------
I--tow
~
Notes:
1. Ch ip deselected for greater than 55ns prior to selection.
2. Chip deselected for a finite time that is less than 55ns prior to selection. (If the deselect time is Ons, the chip is by
definition selected and access occurs according to Read Cycle No.1).
3. WE is high for Read Cycles.
4. Device is continuously selected, CE = VI L .
5. Addresses valid prior to or coincident with CE transition low.
6. If CE goes high simultaneously with WE high, the outputs remain in the high impedance state.
7. Transition is measured ± 500mV from low or high impedance voltage with load B. This parameter is sampled and not
10()oA, tested.
8. The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute.
9. A pullup resistor to Vec on the IT input is required to keep the device deselected: otherwise, power-on current approaches Icc active.
10. A minimum 0.5 ms time delay is required after application of Vee (+5V) before proper device operation is achieved.
2-11
(l)UMC
UM2148
WR ITE CYCLE NO.2 (CE CONTROLLED) (NOTE 6)
.
ADDRESS
twc
-,
.......I~
.
tcw
i--tAS-
~~
-"~
)"tAW
~tWR-
I-twP
\\\\\\\\\\\~~
Jif- /
/
/
/
/ /
tDH
tow
~~
DATA IN
}~
DATA VALID
I--twz-
,
DATA UNDEFINED
DATA OUT
A.C. Testing Input, Output Waveform
3.0V
1.5V TEST
..- POINTS
HIGH IMPEDANCE
1
A.C. Testing Load Circuit
2.0V
+5V
<
0.8V
480n
OV
INPUT
OUTPUT
DOUT -
.......----. 30pF
(INCLUDING
SCOPE AND
JIG)
255n
A.C. TESTING: INPUTS ARE DR IVEN AT 3.0V FOR A
LOGIC "1" AND O.OV FOR A LOGIC "0". TIMING MEASUREMENTS ARE MADE AT 2.0V FOR A LOGIC "1" AND
0.8V FOR A LOGIC "0" AT THE OUTPUTS. THE INPUTS
ARE MEASURED AT 1.5V. INPUT RISE AND FALL TIMES
ARE 5 ns.
=
LOAD A.
Ordering Information
Access
Time
(Max.)
Operating
Current
(Max.)
Standby
Current
(Max.)
Package
Type
UM2148
70 ns
150 mA
30mA
Plastic
UM2148-1
55 ns
150 mA
30mA
Plastic
UM2148-2
45 ns
150mA
30mA
Plastic
UM2148L
70 ns
125mA
20mA
Plastic
UM2148L-1
55 ns
125mA
20mA
Plastic
Part
Number
2-12
/ / /
(l)UMC
UM2149
1K·· X 4 High Speed NMOS SRAM
Features
•
45 ns maximum address access
•
Industry standard 2114 pinout
•
Fully static operation:
•
Totally TTL compatible:
All inputs and outputs
No clocks or strobes required
•
Fast chip select access time: 20ns max.
•
•
Identical cycle and access times
Ii
High density 18-pin package
•
Three-state output
• Single +5V supply
Common data input and outputs
General Description
The UM2149 offers a chip select access that is faster than
its address access. In a typical application, the'address
The UMC UM2149 is a 4096-8it Static Random Access
Memory organized 1024 words by 4 bits and is fabricated
using UMC's new N-channel Silicon-Gate HMOS technology.
It is designed using fully static circuitry, therefore requiring
no clock or refreshing to operate. Address set-up times
are not required and the data is read out non-destructively
with the same polarity as the input data. Common data
input and output pins provide maximum design flexibility.
The three-state output facilitates memory expansion by
access begins as soon as the address is valid. At this time,
the high order addresses are decoded and the desired
memory is then selected. With the faster chip select access,
this decode time will not add to the overall access time thus
significantly improving system performance.
The UM2149 is packaged in an 18-pin DIP for the highest
possible density .. The device is fully TTL compatible and
allowing the outputs to be OR-tied to other devices.
Pin Configuration
has a single +5V power supply.
Block Diagram
A4
_Vcc
As
_GND
Vee
A6
A7
A7
As
As
A9
A9
1/01
1/0 2
1/03
1/01
1/02
1/03
1/04
1/04
WE
cs
WE
2-13
MEMORY ARRAY
64 ROWS
64 COLUMNS
UM2149
Absolute Maximum Ratings
*Comments
Temperature Under Bias ............. -10°C to 85°C
Storage Temperature .............. -65°C to 150°C
Voltage-on Any Pin with Respect
to Ground ..................... -3.5V to + 7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 1 .OW
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
D.C. Characteristics
o
(T A = oOC to +70 C, Vee = 5V ± 10% Unless otherwise specified) (Note 8)
Symbol
2149/-1/-2
2149l/L-1
Min.
Min.
Parameter
Units
Input Load Current
III
(All input pins)
/I LO /
Output Leakage Current
Max.
Conditions
Max.
10
10
p.A
Vee = Max, V IN = Gnd to Vee
50
50
p.A
CS = V IH , Vee = Max.
140
115
mA
T A = 25°C
Vee = Max, CS=VIL
150
125
mA
T A= O°C
Outputs Open
VOUT = Gnd to 4.5V
Power Supply Current
lee
V IL
Input Low Voltage
-0.3
0.8
-0.3
0.8
V
V IH
Input High Voltage
2.0
6.0
. 2.0
6.0
V
VOL
Output Low Voltage
0.4
V
10L =8mA
V OH
Output High Voltage
V
IOH =-4.0mA
mA
V OUT = GND to Vee
(Note 7)
0.4
2.4
Output Short Circuit
los
2.4
±200
±200
Current
Capacitance
(T A = 25°C, f = 1.0 MHz)
Symbol
Test
Typ.
Max.
Unit
COUT'
Output Capacitance
7
pF
CIN
Input Capacitance
5
pF
Note: This parameter is periodically sampled and not 100% tested.
2-14
UM2149
A.C. Characteristics
0
(T A = ooC to +70 C, Vcc = 5V ± 10%
Unless otherwise specified) ,(Note 6, 8)
READ CYCLE
2149-1
2149
Symbol
2149-2
Parameter
Unit
Min.
Max.
Min.
Max.
Min.
Conditions
Max.
tRC
Read Cycle Ti me
tAA
Address Access Time
70
55
45
ns
tACS
Chip Select Access Time
30
25
20
ns
tOH
Output Hold from Address Change
5
5
5
ns
tLZ
Chip Selection to Output in Low Z
5
5
5
ns
Note 5
tHZ
Chip Deselection to Output in High Z
0
ns
Note 5
70'
55
15
0
ns
45
15
0
15
WRITE CYCLE
twc
Write Cycle Time
70
55
45
ns
tcw
Chip Selection to End of Write
65
50
40
ns
tAW
Address Valid to End of Write
65
50
40
ns
0
0
0
ns
50
40
35
ns
5
5
5
ns
25
20
20
ns
0
0
ns
t AS
Address Setup Time
twp
Write Pulse Width
tWR
Write Recovery Time
tDw
Data Valid to End of Write
tDH
Data Hold Time
0
twz
Write Enabled to Output in High Z
0
tow
Output Active from End of Write
0
25
0
0
20
0
ci
15
ns
Note 5
ns
Note 5
(See following page for notes)
2-15
SUMC
UM2149
Timing Diagrams
READ CYCLE NO.1 (Notes 1 and 2)
tRC---~*_ __
ADDRESS
DATA OUT
PREVIOUS DATA VALID
)~
X X )(
DATA VALID
READ CYCLE NO.2 (Notes 1 and 3)
..
tRC
~
jl-
-~
..
tACS
tLz
HIGH IMPEDANCE
I---
tHZ
..
DATA OUT
~X
XJ(
,
DATA VALID
I
HIGH
IMPEDAN CE
WRITE CYCLE NO.1 (WE controlled) (Note 4)
twc
ADDRESS
~
;t
--l~
tcw
V '"
III
tAW
tAS
J
~twP
1
\. \
~f(
...,
.
tow
~~
DATA IN
DATA VALID
-twz-
DATA OUT
DATA UNDEFINED
IIII
tWR
tDH
1~
-tow-
HIGH IMPEDANCE
Notes:
1.
2.
3.
4.
5.
WE is high for Read Cycles.
Device is continuously selected, CS = VIL .
Addresses valid.
If CS goes high simultaneously with WE high, the outputs remain in the high impedance state.
Transition is measured ± 500 mV from low or high impedance voltage with load B. This parameter is sampled and not
100% tested.
6. The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute.
7. Duration not to exceed one minute.
S. A minimum 0.5 ms time delay is required after application of Vcc (+5V) before proper device operation is achieved.
UM2149
WRITE CYCLE NO,2 (CS controlled) (note 4)
.
twc
ADDRESS
J~
_I\.
"
J
..
tcw
-tAS- •
J
-'~
tAw
_twp
\\\\\\\\\\\
-
~
..
r--tWR-
-/-//IL/////
tDH
tDW
J~
DATA IN
~~
DATA VALID
___________________________________=:1
I-twz
DATA OUT
A.C. Testing Input, Output Waveform
3.0V
HIGH IMPEDANCE
:::)\J.---------------------------
OAT A UN DE FINE 0'
A.C. Testing Load Circuit
<
2.0V
1 .5V-TEST POINTS
+5V
O.SV
OV
INPUT
+5V
4S0U
4S0U
OUTPUT
°OUT
30pF
(INCLUDING
SCOPE AND
JIG)
255U
A.C. TESTING: INPUTS ARE DR IVEN AT 3.0V FOR A
LOGIC "1" AND O.OV FOR A LOGIC "0". TIMING MEASUREMENTS ARE MADE AT 2.0V FOR A LOGIC "1" AND
O.SV FOR A LOGIC "0" AT THE OUTPUTS. THE INPUTS
ARE MEASURED AT 1.5V. INPUT RISE AND FALL TIMES
ARE 5 ns.
Supply
Access
Time
(Max,)
Current
(Max.)
Package
Type
UM2149
70 ns
150 mA
UM2149-1
55 ns
150 mA
PlastiG
UM2149-2
45 ns
150 mA
Plastic
UM2149L
70 ns
125 mA
plastic
UM2149L-1
55 ns
125 mA
Plastic
2-17
255U
5pF
LOAD B.
LOAD A.
Ordering Information
Order
Number
DOU
Plastic
(l)UMC
============
UM61 04
1K
x
4 CMOS SRAM
Features
•
Single + 5V power supply
•
Three-state outputs
•
Low power standby
•
On-chip address register
•
Low power operation
•
Synchronous circuitry
•
Fast Access time ........ , 120/150/200/250 ns max.
•
Standard 18 pin DIP package
•
Data retention . . . . . . . . . . . . . . . . . . .. 2.0V min.
•
TTL compatible input/output
General Description
The UM6104 is a 1024x4 fu IIy stat ic CMOS. RAM.
The
On chip latches are provided for the addresses allowing
device utilizes synchronous circuitry to achieve perform-
efficient interfacing with microprocessor systems. The data
ance and low power operation.
output can be forced to a high impedance state for use in
expanded memory systems.
Pin Configuration
Block Diagram
VCC
GND
LATCHED
ADDRESS
REGISTER
1/01
1/02
1/03
ROW
DECODER
MEMORY
MATRIX
64x64
0--+----1:::::1_------1
o--H.....--I..::::I~
.------1
I--Il;:::::'::":':';:~
0-+-+_1>----'
I /04 o--t-I-+1~-----'
LATCHED
ADDRESS
REGISTER
WE 0 - - - - 1
2-18
UM61 04
Absolute Maximum Ratings*
*Comments
Ambient temperature under bias, T A . . . . -10 to + SOoC
Storage temperatu re, T ST . . . . . . . . . .. -55 to + 125° C
Input voltage, VIN . . . . . . . . . . . . . -0.3 to Vee + 0.3V
Output voltage VO UT ..... .I . .... -0.3 to Vee + 0.3V
Maximum power supply voltage, Vee max ....... +7.0V
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied and exposure to absolute maximum rating
conditions for extended periods may affect the device
reliability.
D.C. Electrical Characteristics
0
(T A = 0 to 70 C,GND = OV, Vee = 4.5 to 5.5V unless otherwise specified)
Limits
Symbol
Parameter
Test Conditions
Units
Min.
Typ.
Max.
4.5
5.0
5.5
V
Vee
Supply voltage
V IL
Input low voltage
-0.3
-
O.S
V
V IH
Input high voltage
2.4
-
Vee +0.3
V
leeSB
Standby supply current
CE = Vee, lOUT = OmA
VIN = GND or Vee
10
J.lA
leeop
Operation supply current
f = 1 MHZ, lOUT = 0 mA
VIH = Vee VIL = GND
7
mA
leeDR
Data retention supply current
Vee = IT = 3V lOUT = OmA
VIN = GND o'r Vee
5
J.lA
VeeDR
Data retention supply voltage
CE = high
III
Input leakage current
GND V IN Vee
-1.0
-
1.0
J.lA
ILO
Output leakage current
GND V OUT Vee
-1.0
-
1.0
J.lA
VOL
Output low voltage
IOL = 3.2mA
0.4
V
VOH
Output high voltage
IOH = -1.0mA
V
2.0'
V
2.4
Capacitance
(T A = 25°c f = 1.0 MHz)
Limits
Symbol
Parameter
Unit
Test Conditions
Typ.
CIN
I nput capacitance
All pins except pin under
COUT
Output capacitance
test tied to AC ground
Note: Th is parameter is period ically sampled and is not 100% tested.
2-19
Max.
7
pF
10
pF
SUMe
UM61 04
A.C. Electrical Characteristics
(T A
= 0 to
70°C, Vcc
= 4.5 to
5.5V)
Symbol
UM6104
UM6104-2
UM6104-3
UM6104-4
Max.
Min. Max.
Min. Max.
200
150
120
Parameter
Conventional
Unit
Standard
Min. Max.
Min.
tCA
T ELQV
Chip enable access time
tCOE
TELQX
Chip enable output enable time
50
tcoz
T EHOZ
Chip enable output disable time
80
80
60
50
ns
twoz
T WLQZ
Write enable output disable time
80
80
60
50
ns
tCE
T ELEH**
Chip enable pulse engative width
250
200
15.0
120
ns
teE
TEHEL
Chip enable pulse positive width
100
80
70
50
ns
tAS
TAVEL
Address setup time
20
20
20
20
ns
tAH
T ELAX
Address hold time
100
80
60
40
ns
tRS
TWHEL
Read setup time
0
0
0
0
ns
tRH
T EHWL
Read hold time
0
0
0
0
ns
tRO
TELWL
Read enable time
250
200
150
120
ns
tws
TWLEL
Write setup time
-20
-20
-20
-20
ns
two
TELWH
Write enable time
250
200
150
120
ns
tos
TOVEH
I nput data setu p time
200
150
100
70
ns
tOH
TEHOX
Input data hold time
0
0
0
0
ns
Output data hold time
0
0
0
0
ns
350
280
220
170
ns
250
20
10
20
ns
ns
TEHQX
tOH
T WLQX
tc*
T ELEL
Read or Write cycle time
Notes:
*. T ELEL = T ELEH + T EHEL + T R t T F
**: For Read Modify Write cycle, T ELEH = T ELWL + T WLEH + T F
2-20
UM61 04
A. C. Test Conditions
Input pulse levels: 0.6V to 2.4V
Input pulse rise & fall times (TR & T F ): 10 ns
Timing measurement levels: input: VIL = O.BV
output: VOL = 0.6V
output load: 1 TT L GATE and CL = 100pF
V IH = 2.2V
VO H = 2.4V
Read Cycle Timing Diagram
CE
tRS
WE
I/O
(OUT)
HIGH-Z
I/O
(IN)
HIGH-Z
VALID
Write Cycle Timing Diagram
tc
A
t AS
tAH
tCE
CE
tws
tWD
WE
tDS
I/O
(IN)
I/O,
(OUT)
-11.
VALID
HIGH-Z
2-21
DH
·.UMC
UM61 04
Read Modify Write Cycle Timing Diagram
I.
tc
A-l--tA-s-;~-A-L.l.I:--t-A-H~
---------~I~-------------tCE
~
.~}
I\" ______________________
two--a
~
,il~~-----tCE----~1
_tRS-~I/O
(OUT)
HIGH-Z
I/O
(IN)
Ordering. 1nformation
Access Time
(Max.)
Package
UM6104
250 ns
Plastic
UM6104-2
200 ns
Plastic
UM6104-3
150 ns
Plastic
UM6104-4
120 ns
Plastic
UM6104J
250ns
CERDIP
UM6104J-2
200 ns
CERDIP
UM6104J-3
150 ns
CERDIP
UM6104J-4
120 ns
CERDIP
Part Number
2-22
~
(l)UMC
UM6J.04-J.
CMOS SRAM
Features
•
2.5V minimum operating voltage
•
Three-state outputs
•
Low power standby
•
On-chip address register
•
Low power operation
• Synchronous circuitry
•
Chip access time: 2.0 /J.s
•
Standard 18 pin DIP package
•
Data retention: 2.0V min.
•
No clock required (complete static circuit)
General Description
The UM6104-1 is a nonclocked cMos static RAM organized as 1024 words by 4-bits. Since 1 Kx4 CMOS static
RAM is usually used in low voltage or low power consumption situation, such as telephonic equipments and portable
Block Diagram
Pin Configuration
A6
Vce
As
A7
A4
As
A'3
A9
Ao
1/01
Al
1/02
A2
1/03
CE
1/04
GND
equipments, UMC creates a new product version, UM6104-1
to serve these requirements. UM6104-1 dissif)ates very
little current at the data retention mode and is suitable for
use in non-volatile RAM applications with battery backup.
A4
As
A6
A7
As
A9
VCC
GND
LATCHED
ADDRESS
REGISTER
ROW
MEMORY
MATRIX
64x64
1/01
1/02
1/03
1/04
LATCHED
ADDRESS
REGISTER
WE
WE
Ao Al A2 A3
CE
2-23
UM61 04,;.1
Absolute Maximum Ratings
*Comments
Ambient temperature under bias, T A . . . . . -10 to +80°C
Storage temperature, TST .......... , - 55 to +125°C
Input voltage, VIN . . . . . . . . . . . . . . -0.3 to Vee +0.3V
Output voltage, VOUT ........... -0.3 to Vee +0.3V
Maximum power supply voltage, Vee max ........ +7.0V
Stress above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are
stress ratings only. Functional operation of this device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied and
exposure to absolute maximum rating conditions for
extended periods may affect the device reliability.
D.C. Electrical Characteristics
(T A
= 0 to 70°C, GND = OV, Vee
Symbol
= 2.5 to 5.5V unless otherwise specified)
Parameter
Limits
Test Conditions
Min.
Units
Typ.
Max.
3.0
5.5
V
Vee
Supply Voltage
VIL
I nput Low Voltage
-0.3
-
0.4
V
VIH
Input High Voltage
2.2
-
Vee +0.3
V
leesB
Standby Supply Current
CE = Vee, lOUT = OmA
VIN = GND or Vee
3.0
/-LA
leeop
Operation Supply Current
f = 400 KHz, lOUT = OmA
VIH = Vee VIL = GND
5.0
mA
leeDR
Data Retention Supply Current
Vee = CE = 1 .5V lOUT =OmA
VIN = GND or Vee
1.0
JlA
VeeDR
Data Retention Supply Voltage
CE = high
III
Input Leakage Current
GND VIN Vee
-1.0
-
1.0
JlA
ILO
Output Leakage Current
GND VO UT Vee
-1.0
-
1.0
JlA
VOL
Output Low Voltage
IOL = 3.2mA
0.4
V
VOH
Output High Voltage
IOH = -1.0mA
2.5
V
1.5
V
2.4
Capacitance
(T A = 25°C f = 400 KHz)
Limits
Symbol
Parameter
Unit
Test Conditions
Typ.
CIN
Input Capacitance
All pins except pin under
COUT
Output Capacitance
test tied to AC ground
Note:
This parameter is periodically sampled and is not 100% tested.
2-24
Max.
7
pF
10
pF
UM61 04·1
A.C. Electrical Characteristics
(T A =
a to 70°C,
Vee = 2.5 to 5.5V)
Symbol
Limits
Parameter
Units
Conventional
Standard
teA
T ELOV
Chip enable access time
2.0
fJ.s
teoE
T ELOX
Chip enable output enable time
100
ns
teoz
TEHQZ
Chip enable output disable time
500
ns
two z
T WLOZ
Write enable output disable time
500
ns
teE
T ELEH**
Chip enable pulse negative width
2.0
fJ.s
teE
TEHEL
Chip enable pulse positive width
500
ns
t AS
TAVEL
Address setup time
100
ns
tAH
T ELAX
Address hold time
a
ns
tRS
TWHEL
Read setup time
a
ns
tRH
T EHWL
Read hold time
a
ns
t RO
T ELWL
Read enable time
2.0
fJ.s
tws
TWLEL
Write setup time
-100
os
two
T ELWH
Write enable time
2.0
fJ.s
tos
TOVEH
Input data setup time
1.5
fJ.s
tOH
T EHDX
Input data hold time
a
ns
Output data hold time
a
ns
2.5
fJ.s
Min.
T EHOX
tOH
Max.
T WLOX
t c*
Read or write cycle time
T ELEL
Notes:
*. TELEL =TELEH +TEHEL +TR + TF
**. For Read Modify Write cycle, T ELEH = T ELWL + T WLEH + T F
AC Test Conditions
Input pulse levels: 0.6V to 2.4V
Input pulse rise & fall times (T R & T F): 10 ns
Timing measurement levels: input: VIL = 0.8V
output: VOL
= 0.6V
VIH = 2.2V
VOH
= 2.4V
Output load: 1 TTL GATE and C L = 100 pF
2-25
(l)UMC
UM61 04·1
READ CYCLE TIMING DIAGRAM
~11~-----------------------tc
A
~-t-A-s-V_A_L_ID_tA-H-·
-------------'1
~~-------------tCE
~tCA
----1_-----------------r--tC-O-Z:j
~i'xY0W\!I:
I/O
HIGH-Z
(OUT) ------------~--~~Q,Ox.06x~~~x~(y~~
VALID
1)..._ __
~~
!--tOHI/O
HIGH-Z
(IN)
WRITE CYCLE TIMING DIAGRAM
I~.~----------------------- tc
A~
VALID
~~"';"'tAS--
CE
------------'1 ~~------------- tCE
tws
~------------------twD
tDS
--I r--
tDH
VALID
I/O ______.:.;H~IG:::.:H~-:.:;;Z~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
(OUT)
2-26
UM6104·1
READ MODIFY WRITE CYCLE TIMING DIAGRAM
r~.~-----------------------tc
A~-tA-s-V-A-L-I-D-tA-H-~
tCE
tRS -t-------
~~~~~---------------------~ ~----------tWD
I/O
(OUT)
HIGH-Z
-------------~y~~~~~~~,~,~~---~
HIGH-Z
I/O
(IN) --------------------~
2114 COMPATIBILITY
ADD
i4---------------------------"'!"--------------------A-=-D-=-D-=R-:-:-:-V-A-L-I-D-----------------------~ NEXT
~
/111//////;
~-------------------------
TELEL'
--------------------------~·I
COMPATIBLE TIMING
ADD
)(~_______________________A_D_D_R_E_S_S_V_A_L_I_D________________________~
CS,CE
~__________________________________________________~~
2114 - REQUIRES THE ADDRESS TO REMAIN VALID
THROUGHOUT THE CYCLE,
2-27
UM6104-1 - REQUIRES VALID ADDRESS FOR ONLY
A SMALL PORTION OF THE CYCLE, BUT
REQUIRESCEtCFALL TO INITIATE
EACH CYCLE,
Vcc
~GND
ROW
DECODE
256 x 256
MEMORY ARRAY
AU
COLUMN I/O
INPUT
DATA
CIRCUIT
CS2
CSt
OE
WE
2-43
.COLUMN DECODER
UM6164
Absolute Maximum Ratings*
*Comments
Terminal Voltage with Respect to
GND (VTERM ) . . . . . . . . . . . . . . . . -O.5V to +7.0V
Temperature Under Bias (T BIAS) ...... -10°C to + 125°C
Storage Temperature (T STG) ........ -4cf' C to +150 o C
Power Dissipation (P T ) . . . . . . . . . . . . . . . . . . . . . 1.0W
DC Output Current (lOUT) . . . . . . . . . . . . . . . . . 20 mA
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
Pin Names
Operating Range
Address
Ao-A12
1/0 1-I/Os Data Input/Output
WE
Write Enable
OE
Output Enable
CS 1
Chip Select One
Vee
Power
CS 2 Chip Select Two
GND Ground
the operational sections of this specification is not implied.
Range
Ambient
Temperature
Commercial
0° C to +70°C
Vee
5V ± 10%
D.C. Electrical Characteristics
(Vee = 5V ± 10%, GND = OV, T A = 0 to 70°C)
Symbol
Parameter
Test Conditions
Min.
Typ.1
Max.
Units
III
Input leakage current
VIN =GNDtoVee
-
-
5
p.A
ILO
Output Leakage Current
CSl =V IH orCS2 =V IL orOE=V IH ,
VI/O = GND to Vee
-
-
5
p.A
Current
CS 1 = V IL , CS 2 = V IH , 11/0 =OmA
-
50
100
mA
Average Operating Current
Min, Duty Cycle = 100%, CS 1 = VI L'
CS 2 = V IH
-
60
120
mA
CS 1 = V IH or CS 2 = V I L' 11/0 = 0 mA
-
5
10
mA
lee
lec1
Operating Power Supply
ISB
ISB12
Standby Power Supply
CS 1~ V ee-0.2V, V IN ~ Vee-O.2V
Current
or VIN ~ O.2V
CS 2 ~ 0.,2V, V IN ~ V ee -O.2V or
ISB22
VIN ~ O.2V
I OL =2.1 mA
VOL
-
.02
2
mA
-
.02
2
mA
-
-
0.4
V
2.4
-
-
V
Output Voltage
V OH
10H = -1.0mA
1. Typical I imits are at Vee = 5.0V, T A = 25° C and specified loading.
2. VIL min = -0.3V
2-44
UM6164
Recommended D.C. Operating Conditions
(T A = 0 to +70°C)
Symbol
Parameter
Min.
Typ.
Max.
VCC
Supply Voltage
4.5
5.0
5.5
V
GNO
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
3.5
6.0
V
VIL
Input Low Voltage
-0.5
0
0.8
V
Capacitance (1)
Unit
A.C. Test Conditions
(T A = 25°C, f = 1.0MHz)
Parameter
Symbol
Parameter-
Conditions
Max.
Unit
CIN
Input Capacitance
VIN =OV
6
Clio
Input/Output
Capacitance
Vila =OV
8
Conditions
Input Pulse Levels
OV to 3.0V
pF
Input Rise and Fall Times
5 ns
pF
Input and Output
1.5V
Timing Reference Level
1 TTL Gate and C L = 30pF
(including scope and jig)
Output Load
Note: This parameter is sampled and not 100% tested.
A.C. Electrical Characteristic
(over the operating range)
Symbol
UM6164-2
Parameter
Min.
READ CYCLE
Read Cycle Time
Address Access Time
tRC
tAA
tACS1
tACS2
tOE
Chip Select Access Time
l CSl
I CS
2
I
I
tAS
tAW
twp
tWR1
tWR2
tWHZ
tow
tOH
tOHZ
tow
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Max.
Min.
45
-
55
-
70
-
-
45
45
45
30
-
-
70
70
70
50
5
5
5
0
0
tCLZ1
CSl
Chip Selection to Output in Low Z
tCLz2
CS 2
Output Enable to Output in Low Z
tOLZ
tCHZ1
Chip Deselection to Output in High Z ~ CSl
CS 2
tCHz2
Output Disable to Output in High Z
tOHZ
Output Hold from Address Change
tOH
WRITE CYCLE
Write Cycle Time
twc
Chip Selection to End of Write
tcw
Write to t><><><~~--2-47
UM6:1.64
WRITE CYCLE 2(1,6)
twc
ADDRESS
14------
tcw 1 11
~---- tCW 11
2
DOUT
~--~--~~--~--~~--~--~~--~---------------+--------------<
"'['DW
DIN _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Notes:
1. WE must be high during address transitions.
2. A write occurs during the overlap (twp) of a low CSl a high CS 2 and a low WE.
3. tWR is measured from the earlier of CS, or WE. going high or CS 2 going low to the end of write cycle.
4. During this period, I/O pins are in the output state SO that the input signals of opposite phase to the outputs must not
be applied.
5. If the CSl low transition or the CS 2 high transition occurs simultaneously with the WE low transitions or after the WE
transition. Outputs remain in a high impedance state.
6. OE is continuously low (OE = V IL ).
7. D OUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
.
9. If CS 1 is low and CS 2 is high during this period, I/O pins are in the output state. Then the data input signals of opposite
phase to the outputs must not be applied to them.
10. Transition is measured ± 590mV from steady state. This parameter is sampled and not 100% tested.
11. tcw is measured from the later of CS 1 going low or CS 2 going high to the end of write.
2-48
UM6J.64
Data Retention Characteristics
(T A = 0 to +70°C)
Symbol
VORl
VDR2
Min. TypJ1) Max. Units
Test Conditions
Parameter
'.
Vee for Data Retention
CSl ~ Vee -O.2V, V IN ~ V ee-0.2V or V IN ~ 0.2V
2.0
-
-
V
CS 2 ~ O.2V, VIN ~ V ee-0.2V or V IN ~ O.2V
2.0
-
-
V
CSl ~ Vee -O.2V,
leeDRl
Data Retention Current
V IN ~ Vee-O.2V or V IN ~ O.2V
CS2 ~ O.2V, V IN ~ Vee -D.2V or V IN ~ 0.2V
leeDR2
Ch ip Deselect to
teDR
tR
Data Retention Time
2
50
JJ.A
-
2
50
JJ.A
0
-
-
ns
-
-
ns
See Retention Waveform
Operation Recovery Time
tRe(2)
1. Vee =2V, TA =+25°C
2. t Re = Read Cycle Time
Low Vee Data Retention Waveform
CS I CONTROLLED
DATA RETENTION MODE
Vee
-
------_1
4.5V
VOR ~2V
eSI
~vee
- O.2V
CS 2 CONTROLLED
~--_
DATA RETENTION
MODc--_-----'~
Vee -----4"""".5-V""""'-
4.5V
VOR ~ 2V
Ordering Information
Part Number
Access Time (Max.)
Package
UM6164
70
Plastic DIP
UM6164-1
45
Plastic DIP
UM6164-2
55
Plastic DIP
2-49
eUMC
========
UM6167
16K
x
l' High Speed CMOS SRA,fd
Features'
•
High-speed - 35/45/55/70 ns
•
•
Low power dissipation
150mW (Typ.) operating
• All inputs and outputs directly TTL compatible
•
Th ree state outputs
100p.W (Typ.) stand by
•
Data retention supply voltage: 2.0 - 5.5V
Fully static operation
• Single 5V pow~r supply
General Description
performance twin tub CMOS process. I nputs and threestate outputs are TTL compatible. The UM6167 is moulded
in a standard 20-pin, 300 mil DIP.
The UMC UM6167 is a 16,384 bit static random access
memory organized as 16,384 words by 1 bit and operates
from a single 5 volt supply. It is built with UMC's high
Pin Configuration
Block Diagram
-+--- Vcc
Ao
Ao
Vce
Al
Al3
A2
A12
A3
All
A4
A10
Al
A2
A3
A4
A12
A 13
As
A9
CS
A(5
As
DIN
DOUT
A7
WE
DIN
GND
CS
ROW
SELECT
•
•
•
•
•
-GND
128x128
MEMORY ARRAY
DOUT
WE
All AlOA9 As A7 A6 As
2-50
UM6167
Absolute Maximum Ratings*
*Comments
Terminal Voltage with Respect to
GND, V T . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Operating Temperatwe, TOPR. '......... O°C to +70°C
Temperature Under Bias, TSLAS ..... -55°C to +125°C
Storage Temperature, TSTC ........ -65°C to +lbO°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 1.0W
DC Output Current, lOUT . . . . . . . . . . . . . . . . . 20mA
Stresses above those listed under "Abso lute Max imu m
Ratings" may ·cause permanent damage to the device.
These are stress ratings only. Functional operation ,of
this device at these or any other conditions above those indicated in the operation91 sections of this specification is
not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability ..
D.C. Characteristics
(TA = o°c to +70°C, Vcc-= 5V ± 10%)
UM6167
Symbol
Parameter
UM6167L
Test Conditions
Units
Min. Typ. Max.
I
i'LO!
Min.
Typ.
Max.
Input I,.eakage Current
Vcc = 5.5V, VIN =OV to V CC
-
-
2
-
-
2
J.LA
Output Leakage Current
CS = V IH, V OUT = OV to V cc
-
-
2
-
-
2
J.LA
ICC1
Operating Power
Supply Current
CS = V I L ' Output Open
-
30
60
-
25
50
mA
ICC2
Dynamic Operating
Current
Min. Duty Cycle = 100%
-
30
60
-
25
50
mA
Iss
Standby Power
Supply Current
CS ~VIH
-
5
20
-
5
20
mA
ISS1
Full Standby Power
Supply Current
CS ~ VCC = -O.2V
VIN ~VCC =-0.2V or ~·'O.2V
-
0.02
2
-
V IL
Input Low Voltage
-0.5
-
O.S
-0.5
-
O.S
V
V IH
Input High Voltage
2.2
-
6.0
2.2
6.0
V
VOL
Output LowVoltage
IOL = SmA
-
-
0.4
-
-
0.4
V
V OH
Output High Voltage
IOH = -4mA
2.4
-
-
2.4
-
-
V
II LI
Capacitance
0.002 0.05
mA
Truth Table
(TA = 25°C, f = 1.0MHz)
Symbol
C IN
COUT
Item
Input
Capacitance
Output
Capacitance
Conditions
Max.
Unit
VIN =OV
5
pF
V OUT =OV
6
pF
Note: This parameter is sampledand not 100% tested.
2-51
Mode
CS
WE
Output
Power
Standby
H
X
High Z
Standby
Read
L
H
Write
L
L
DOUT
High Z
Active
Active
. UM6167
A.C. Characteristics
(TA
= O°C to +70°C,
Vcc
=5V ± 10%)
READ CYCLE
"'
Symbol
Parameter
UM6167
Min.
UM6167·1
Max.
Min.
Max.
UM6167·2
UM6167·3
Min. Max.
Min. Max.
Unit
~c
Read Cycle Time
70
-
55
-
45
-
35
-
tAA
Address Access Ti me
-
70
-
55
-
45
-
35
ns
t ACE
Chip Enable Access Time
-
70
-
55
-
45
-
35
ns
ns
ns
tLZ
Chip Selection to Output in Low Z
5
-
5
-
5
-
5
-
tHZ
Chip Deselection to Output in High Z
0
35
0
30
0
30
0
25
ns
tpu
Chip Selection to Power Up Time
0
-
0
-
0
-
0
-
ns
25
ns
tOH
tpD
. Output Hold from Address Change
Chip Deselection to Power Down Time
5
-
-
40
5
-
-
35
5
-
-
35
5
-
ns
WRITE CYCLE
Parameter
Symbol
twc
tcw
Write Cycle Time
Chip Enabled to End of Write
UM6167
55
55
-
45
tow
Date Valid to End of Write
tOH
Data Hold Time
3
twz
Write Enabled to Output in High Z
0
25
twp
Write Pulse Width
tow
Output Active from End of Write
Min. Max.
-
Write Recovery Time
Address Set-up Time
UM6167·3
Min. Max.
70
tWR
Address Valid to End of Write
tAS
UM6167·2
Max.
Max.
-
tAw
UM6167·1
Min.
55
0
40
0
25
35
0
Min.
45
-
35
40
-
35
40
35
0
-
35
-
30
-
25
0
-
0
0
25
-
20
-
17
3
-
3
-
3
-
0
25
0
20
0
13
ns
35
0
35
0
30
ns
45
0
0
0
Timing Diagrams
READ CYCLE NO.1 (NOTES 1 AND 2)
ADDM.~~~~~~~~~~~~~tRC~~~~~~~~~~~~~
~OH ~
DATA OUT. PREVIOUS OATA3fALlD¥
}~
XX)/(
2-52
Unit
_______________________________
DATA VALID
-
ns
ns
ns
ns
ns
ns
ns
ns
UM6167
READ CYCLE NO.2 (NOTES 1 AND 3)
..
tRC
~
~I
t 7 tACS
HIGH IMPEDANCE I _ I
DATA OUT
~tPu
DATA VALID
I
- I
H~GH
IMPEDANCE
~~~~~NT ;~~----------~~----------------------------------~~~-----I-tpD
WRITE CYCLE NO.1 (WE CONTROLLED) (NOTE 4)
twc
jlf
ADDRESS
Il
tcw
I
\\\\
~
tA
I---tAS
-I
j4--twP
\.\
1\
,t
•
DATA IN
DATA OUT
-
tDHI
I - - tDW
I
*
DATA VALID
I-- tWZ.:l
DATA UNDEFINED
LLLLL~LL
LL
j4-tWR.....
I- tow ~
HIGH IMPEDANCE
Notes:
1. CS or WE must be high during address transitions.
2. If CS goes high simultaneously with WE high, the output remains in a high impedance state.
3. All write cycle timings are referenced from the last valid address to the first transition address.
4. Transition is measured ±500mV from steady state voltage with specified loading in Figure 2. This parameter
is sampled and not 100% tested.
WRITE CYCLE NO.2 (CS CONTROLLED) (NOTE 4)
.
twc
ADDRESS
1~
-lE-
I--tA",
I
I
tcw
~
'\:
tWR
tAW
\ \ \ \ \ \ \ \\ \ \ \ \
DATA IN
I-twP~
~
t:
*'
J
r-tDW
DATA VALID
I
DATA OUT
~
//I/////L~L
. tDHJ
I
X
I-twz
--------.-D-A-T-A--U-N-D-E-F-'-N-E-D---------j
2-53
HIGH IMPEDANCE
UM6167
A.C. Test Conditions
+5V
Typ.
Test
DOUT
GND to 30V
5ns
1.5V
1.5V
See Figures 1 and 2
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
~
480n
255D. ·5PF
Figure 1. Output Load
Figure 2. Output Load
(for tMZ, tLZ, twz, and tow)
* Including scope and jig.
Low Vee Data Retention Characteristics For L Version Only
(TA = 0 to 70°C)
Min.
Typ.1
Max.
Units
Vcc for Data Retention
2.0
-
-
V
ICCDA
Data Retention Current
CS ~ V cc -0.2V
-
0.52
1.0 3
202
30 3
IlA
tCDA
tR
Chip Deselect to Data Retention Time
Operation Recovery Time
V IN ~ V cc -O.2V or ~ O.2V
0
Symbol
VOR
Parameter
Test Conditions
.
tRC
4
-
-
Notes: 1. T A = 25°C, 2. at VCC = 2V, 3. V cc = 3V, 4. tRC= Read Cycle Time
Timing Waveform Low Vee Data Retention Waveform
j
~ATA RETENTION MODE~
VCC
4.5V.
I-- tCD
cs
;--Z""Z-Z""'Z-/---V-IH-\
VDR ~2V
_
4.5V
tR-1
VDR
/~~VI-H\~\--'::\~\~\-\~
Ordering Information
Part Number
UM6167
UM6167-1
UM6167-2
UM6167-3"
UM6167L·
UM6167Lc1
UM6167L-2
UM6167L-3
Access Time
(Max.)
70 ns
55 ns
45 ns
35 ns
·70 ns
55 ns
45 ns
35 ns
Operating Current
(Max.)
60mA
60mA
60mA
60mA
50mA
50mA
50mA
50mA
2-54
Standby .Current
(Max.)
2mA
2mA
2mA
2mA
50llA
50llA
50llA
50p.A
Package Type
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
-
ns
ns
SUMO
=======::
UM6168
4K x 4 High Speed CMOS SRAM
rlJ"l~
Features
•
High·speed - 35/40/45/55170 ns
•
Fully static operation
•
Low power dissipation
225mW (typ.) operating
•
All inputs and outputs directly TTL compatible
100p.W (typ.) standby
•
• Three state outputs
Data retention supply voltage: 2.0 ~ 5.5V
• Single 5V power supply
General Description
The UMC UM6168 is a 16,384 bit static random access
performance twin tub CMOS process.
memory organized as 4096 words by 4 bits and operates
state outputs are TTL compatible. The UM6168 is moulded
from a single 5 volt supply.
in a standard 20·pin, 300 mil·DIP.
It is built with UMC's high
Pin Configuration
I nputs and three·
Block Diagram
Ao
- . - - Vcc
Al
- . - - GND
A2
Vcc
ROW
SELECT
A3
All
A4
AlO
AlO
A9
Au
As
1/01
1/04
1/03
1/02
1/0 2
1/0 3
1/0 4
1/01
WE
CS
WE
2-55
MEMORY ARRAY
128 ROWS
128 COLUMNS
UM6168
A~solute
*Commen1S
Maximum Rati.ngs*
Terminal Voltage with Respect
to GND, VT . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Operating Temperature, TOPR .......... 0°Cto+70°C
Temperature Under Bias, T BLAS ..... -55°C to +125°C
Storage Temperature, TSTe ........ -65°C to +150°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 1.0W
DC Output Current, lOUT . . . . . . . . . . . . . . . . . 20mA
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
D.C. Characteristics
(TA = O°C to +70°C, vce = 5V
± 10%)
UM6168
Symbol
Parameter
UM6168L
Units
Test Conditions
Min.
Typ.
Max.
Min.
Typ.
Max.
I'll I
Input Leakage Current
Vce = 5.5V, VIN =OV to Vcc
-
-
2
-
-
2
J.l.A
IILol
Output Leakage Current
CS = V IH , VOUT =OV to V cc
-
-
2
-
-
2
J.l.A
ICCl
Operating Power
Supply Current
CS = V I L ' Output Open
-
30
60
-
25
50
mA
lec2
Dynamic Operating
Current
Min. Duty Cycle = 100%
-
30
60
-
25
50
mA
IS8
Standby Power
Supply Current
CS;;;a. V IH
-
5
20
-
5
20
mA
IS81
Full Standby Power
Supply Current
CS ;;;a. Vec = -O.2V
VIN;;;a. Vce = -O.2V or:os:;;; O.2V
-
0.02
2
-
0.002
0.05
mA
VIL
Input Low Voltage
-0.5
-
0.8
-0.5
-
0.8
V
V IH
Input High Voltage
2.2
-
6.0
2.2
-
6.0
V
VOL
Output Low Voltage
IOL =8mA
-
0.4
-
-
0.4
V
V OH
Output High Voltage
IOH =-4mA
2.4
-
-
2.4
-
-
V
Capacitance
Truth Table
(TA = 25°C, f = 1.0MHz)
Symbol
CIN
Item
Input
Capacitance
Output
COUT
Conditions
Capacitance
VIN =OV
V OUT =OV
Max.
Unit
5
pF
6
pF
Note: This parameter is sampled and not 100% tested.
2-56
Mode
CS
WE
Output
Power
Standby
H
X
High Z
Standby
Read
L
H
DOUT
Active
Write
L
L
High Z
Active
(f)UMC
UM6168
A.C. Characteristics
0
0
(TA = 0 C to +70 C, Vcc = 5V
± 10%)
READ CYCLE
Symbol
UM6168
Parameter
UM6168·1
UM6168·2
UM6168-3
UM6168·4
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
70
-
55
_.
70
-
55
Chip Enable Access Time
-
70
-
Output Hold from Address Change
5
t AC
Read Cycle Time
tAA
Address Access Time
t ACE
tOH
tLZ
Chip Selection to Output in Low Z
5
-
tHZ
Chip Deselection to Output in High Z
0
30
tpu
Chip Selection to Power Up Time
0
-
tpD
Chip Deselection to Power [}own Time
-
40
-
t ACS
Read Command Set-up Time
0
tRCH
Read Command Hold Time.
0
5
5
0
-
55
-
Unit
45
-
40
-
35
-
ns
-
45
-
40
-
35
ns
45
-
40
ns
5
-
5
-
5
-
5
25
-
20
-
-
35
-
5
-
ns
5
-
ns
20
-
15
ns
-
0
-
0
-
0
-
ns
35
-
35
-
35
-
25
ns
0
-
ns
0
-
ns
0
-
0
-
0
-
0
-
0
-
0
-
WRITE CYCLE
Symbol
UM6168
Parameter
UM6168·1
UM6168·2
UM6168·3
UM6168-4
U,nit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
twc
Write Cycle Time
60
tcw
Chip Enabled to End of Write
60
tAw
Address Valid to End of Write
60
tAS
Address Set-up Ti me
twp
Write Pulse Width
tWA
Write Recovery Time
tDW
Date Valid to End of Write
0
40
0
25
tDH
Data Hold Time
twz
Write Enabled to Output in High Z
tow
Output Active from End of Write
3
-
-
25
40
40
-
35
40
-
40
-
35
40
-
40
-
0
ns
35
-
-
0
-
ns
30
-
25
ns
-
-
ns
17
-
ns
20
-
13
ns
35
-
30
ns
50
-
0
-
0
-
35
-
30
-
0
-
0
-
0
25
20
-
20
3
-
3
-
50
50
-
25
35
40
-
20
35
3
-
0
3
Timing Diagrams
READ CYCLE NO.1 (NOTES 1 AND 2)
ADDRgS~~~~~,~~.~~~~~~tRC~~~~~~~~~~~~~
gtDH~ 1
DATA OUT
PREVIOUS DATA
VAUO¥ XX>k::::::::::::D:A..;,T-...;A-_-V:A:L;I~D::::::::::::::-_
2-57
ns
ns
ns
UM6168
READ CYCLE NO.2 (NOTES 1 AND 3)
.
tRC
It
~I
t .)ACS
HIGH IMPEDANCE I _ I
DATA OUT
~tPu
DATA VALID
I
- I
HIGH
IMPEDANCE
~~~~:NT T~~---------J------------------i.,---I
~tpD
WRITE CYCLE NO.1 (WE CONTROLLED) (NOTE 4)
twc
-:If
ADDRESS
{
I
tcw
I
-"'.\\\
~.
1
~tAS
---i
AY
~
\. \
t
DATA UNDEFINED
IIIJJJJI
tDHI
I
DATA VALID
~ tWZ.:i
DATA OUT
II
_tWR_
-tow
]{
DATA IN
-
~twP
.
~
••
tow;j
HIGH IMPEDANCE
Notes:
1. CS or WE must be high during address transitions.
2. If CS goes high simultaneously with WE high, the output remains in a high impedance state.
3. All write cycle timings are referenced from the last valid address to the first transition address.
4. Transition is measured ±500mV from steady state voltage with specified loading in Figure 2. This parameter
is sampled and not 100% tested.
WRITE CYCLE NO.2 (CS CONTROLLED) (NOTE 4)
.
twc
ADDRESS
-;if
if-
--tAS .,
tcw
~
tAW
~twP~
~
jlllllllill
,,\\\\\\\\\\\\
't:
I---tDW
if"
DATA IN
DATA VALID
I
~twz ~
________________________
DATA OUT
tD1:-I1
I
*'
HIGH IMPEDANCE
.)1...--------.. . . .---------
DATA UNQEFINEP
2-58
UM6168
A.C. Test Conditions
+5V
480U
Typ.
Test
I nput Pulse Levels
Input Rise and Fall Times
Input Timing>IAeference Levels
Output Reference Levels
Output Load
°OUT
~
255U
GND to 30V
5ns
1.5V
1.5V
See Figures 1 and 2
Figure 1. Output Load
5pF
Figure 2. Output Load
(for t MZ , tLZ, twz, and tow)
* Including scope and jig.
Low Vee Data Retention Characteristics. For L Version Only
(T A = 0 to 70°C)
Min.
Typ.1
Max.
VOR
Vcc for Data Retention
2.0
-
V
ICCDA
Data Retention Current
CS ~ VCC -0.2V
-
09
1.03
202
30 3
p.A
tCOA
tR
Chip Desel,ect to Data Retention Time
Operation Recovery Time
V IN ~ Vee -0.2V or ~ O.2V
0
tRC 4
-
-
-
~
Symbol
Parameter
Test Conditions
Notes: 1. TA = 25°C, 2.atVcc =2V, 3. Vce =3V, 4. tRC = Read Cycle Time
Timing Waveform Low Vee Data Retention Waveform
j
~ATA
4.5V.
VCC
I--tco
cs
I~""'Z""'Z"""-Z""Z""'/"""'V-IH-\
RETENTION MOOEt
VOR ~ 2V
_ 4.5V
tR-I
VOR
/"'~VI-H\~\~\~\~\~\
Ordering Information
Part Number
Access Time
(Max.)
Operating Current
(Max.)
UM6168
UM6168-1
UM6168-2'
UM6168-3
UM6168-4
70 ns
55 ns
45 ns
40 ns
35 ns
90mA
90mA
90mA
90mA
90mA
2mA
2mA
2mA
2mA
Plastic
Plastic
Plastic
Plastic
Plastic
UM6168L
UM6168L-1
UM6168L-2
UM6168L-3
UM6168L-4
70 ns
55 ns
45 ns
40 ns
35 ns
90mA
90mA
90mA
90mA
90mA
50p.A
50p.A
50J,tA
50J,tA
50J,tA
Plastic
Plastic
Plastic
Plastic
Plastic
2-59
Standby Current
(Max.)
~mA
Package Type
Units
ns
ns
Microcontroller
Selection Guide
Descriptions
Part No.
* UM8051/31
Remarks
Page
6, 8, 11 MHz Version
3-3
Intel 8048/35/ .
UM8048/35/
49/39
Compatible Devices
8 Bit Single Chip NMOS MC
8 Bit Single Chip NMOS IlC
49/39
Intel 8051/31
* Under Development.
3-2
-
3-14
(l)UMC
UM8048 /8035/8049/8039
"llfll''1I1!1iI£~/II'&.illl!~I''ff''~IIII'~!I~'''lr''II.t'j S· •
Ing.e
Ch·IP 8 - B·t
··,·crocomputer
I .If.
'1Iftlif"'~
Features
•
•
•
•
•
•
UMS04S/8049 is interchangeable with Intel's PS04S/
S049 in pin configuration and electrical characteristics
• UMS049-2Kx8 ROM
12Sx8 RAM
27 I/O Lines
UMS04S-1KxS ROM
64xB RAM
27 I/O Lines
• Internal timer/event counter
• Easily expandable memory and I/O
• Compatible with MCS memory and I/O
S-Bit CPu, ROM, RAM, I/O in single package
Single 5V supply
Up to 1.36 J1,sec instruction cycle for 11 MHz operation.
All instructions 1 or 2 cycles
Basic machine instructions: 96
1-byte instructions: 68
2-byte instructions: 2S
Single level interrupt
General Description
The UMS04S/S035/~049/8039 is a totally self-sufficient
8-bit parallel computer fabricated on a single silicon chip
using UMC N-channel silicon gate MOS process.
MCS-80 and MCS-85 peripherais.
The U MS035 is the
equivalent of an UMS04S without program memory. The
UMS039 is the equivalent to an UM8049 without program
memory.
The UMS048 contains a 1 K x S program memory, a 64 x S
RAM data memory, 27 I/O lines, and an S-bit timer/counter
in addition to on-board oscillator and clock circuits. The
UMS049 contains a 2K x S program memory, a 128 x S
RAM data memory, 27 I/O lines, and an S-bit timer/counter
in qddition to on board oscillator and clock circuits. For
systems· that requ ire extra capabi Iity, the U MS04S/8049
can be expanded using standard memories and MCS-4S,
Pin Con~iguration
TO
This microprocessor is designed to be an efficient controller
as well as an arithmetic processor. The UMS04S/S049 has
extensive bit handling capability as well as facilities for
both binary and BCD arithmetic. Efficient use of program
memory results from an instruction set consisting mostly of
single byte instructions and non instructions over two
bytes in length.
Logic Symbol
Vee
XTAL1
T!
XTAL2
RESET
P27
P26
ss
P25
INT
P24
EA
P17
RD
PSEN
WR
P16
SINGLE
STEP -
P15
P14
EXTERNAL
MEM-
ALE
P13
P12
DBo
DBl
Pll
DB2
Pl0
DB3
VDD
PROG
DB4
DBs
PORT
= 1
XTAL{:
PORT
=2
RESET
UM8048!
8049
TEST { :
INTERRUPT -
P23
DB6
P22
DB7
P21
VSS
P20
BUS
3-3
PORT
EXPANDER
STROBE
UftlB04B/B035/B049/B039
Block Diagram
P20
DBO
DB7
REGISTER 0
REGISTER 1
ARITHMETIC
•
LOGIC
IJNIT
(S)
REGISTER 2
REGISTER 3
CONOITIONAL
BRANCH
LOGIC
POWER
SUPPLY
REGISTER 4
_+
VDD
_ R A M SUPPLY
VCC
5V MAIN SUPPLY
VSS
_GND
REGISTER 5
REGISTER 6
REGISTER 7
8 LEVEL STACK
(VARIABLE LENGTH)
OPTIONAL SECOND
REGISTER BANK
CONTROL AND TIMING
DATA STORE
TO
PROG
EA
XTAL1 XTAL2
ALE
PSEN
1128 x 81
64 x 8
TIMING
OUTPUT
INTERRUPT
INITIALlZE
EXPANDER
STROBE
CPU
OSCILLATOR
MEMORY
XTAL
SEPARATE
PROGRAM
MEMORY
ENABLE
SINGLE
STEP
ADDRESS
LATCH
ENABLE
3-4
READIWRITE
STROBES
RESIDENT
RAM ARRAY
S04S:
1K x 8 ROM
64 x 8 RAM
8049:
2K x 8 ROM
128 x8 RAM
UMB04B/8035/B049/B039
Absolute Ratings*
*Comments
Operating Temperature . . . . . . . . . . . . . . . O°C to 70°C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of this
devic;e at these or any other conditions above those indicated in the operational sections of th is specification is not
implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Storage Temperature . . . . . . . . . . . . . . -65°C to 150°C
Voltage on Any Pin . . . . . . . . . . . . . . . , -0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 1.5W
D. C. Characteristics
(T = OoC - 70°C Vee = Voo = 5V ± 10%,' Vss = OV)
Limits
Parameter
Units
Symbol
Min.
Typ.
Test Conditions
Max.
Input Low Voltage
(All Except XTAL1, XTAL2, RESET)
V IL
-0.5
0.8
V
Input High Voltage
(All Except XTAL1, XTAL2, RESET)
V IH
2.0
Vee
V
Input High Voltage (RESET, XTALl, XTAL2)
VIHl
3.8
Vee
V
Input Low Voltage (RESET, XTAL1, XTAL2)
VILl
Vss.
0.5
V
Output Low Voltage (BUS)
VOL
0.45
V
IOL = 2.0 mA
Output Low Voltage
(RD, WR, PSEN, ALE)
VO Ll
0.45
V
IOL = 1.S mA
Output Low Voltage (PROG)
VO L2
0.45
V
IOL=1.0mA
Output Low Voltage (All Other Outputs)
VO L3
0.45
V
IOL = 1.6 mA
Output High Voltage (BUS)
VO H
2.4
V
IOH = -400JJ.A
Output High Voltage (RD, WR, PSEN, ALE)
VO Hl
2.4
V
IOH = -100JJ.A
Output High Voltage (All Other Outputs)
VO H2
2.4
V
IOH = -40JJ.A
iNT)
IlL
±10
JJ.A
VSS~VIN ~Vee
I nput Leakage Current
(Pl0-P17, P20-P27, EA, SS)
IILl
-500
JJ.A
Vee~ VIN ~VSS +0.45V
Input Leakage Current (R ESET)
IIL2
-300
=A
Vce~VIN ~VIL 1
Output Leakage Curreht
(BUS, TO) (High Impedance State)
IoL
±10
JJ.A
Vce~VIN~Vss+0.45V
Input Leakage Current (Tl,
20
SMHz,6MHz
S
. Power Down Supply Current
mA
100
1·1 MHz
12
35
Total Supply Current
70
45
3-5
8MHz,6MHz
mA
100 + lee
100
11 MHz
UM8048/8035/8049/8039
A.C. Characteristics
(TA =
ooc -
70°C, Vee =
voo
= +5V
± 10%,
Vss = OV)
Limits
Test
Parameter
Symbol
6MHz
8MHz
11MHz
Units
Conditions(1)
Min.
Max.
Min.
Max.
Min.
Max.
15.0
1.875
15.0
1.36
15.0
Cycle Time
tCY
2.5
ALE Pulse Width
tLL
410
270
150
ns
Address Setup Before ALE
tAL
200
140
70
ns
Address Hold From ALE
tLA
120
85
50
ns
Control Pulse Width
(RD, WR)
tCC1
1050
730
480
ns
Control Pulse Width
(PSEN)
tCC2
800
550
350
ns
Data Setup Before WR
tDW
880
610
390
ns
Data Hold After WR
tWD
115
75
40
ns
Data Hol.d (RD, PSEN)
tDR
0
RD to Data in
tRD1
800
PSEN to Data in
tRD2
550
Address Setup Before WR·
tAW
Address Setup
Before Data in (RD)
tAD1
Address Setup
Before Data in (PSEN)
tAD2
1250
Address Float to RD, WR
tAFC1
290
Address Float to PSEN
tAFC2
220
160
0
110·
ns
520
330
ns
330
190
ns
470
850
0
210
1100
730
ns
720
460
ns
ns
(2)
10
ns
(2)
140
20
(2)
ns
300
1680
40
J.l.s
..
..
Control Pulse ALE
(RD,WR)
tCA1
120
85
50
ns
Control Pulse to ALE
(PSEN)
tCA2
620
460
320
ns
Interrupt Pulse Width
tiNT
3
3
3
MC
(3)
Power on Reset Time
tRES
5
5
5
MC
(3)
3-6
..
UMS04S/S035/S049/S039
A. C. Characteristics (Continued)
Limits
Test
Symbol
Parameter
6MHz
11MHz
8MHz
Unit
Cond itions( 1 )
Min.
Max.
Min.
Max.
Min.
Max.
Port Control Setup
Before Falling Edge
of PROG
tcp
200
110
100
.ns
Port Control Hold
After Falling Edge
of PROG
tpc
460
300
160
ns
PROG to P2 Input must
be Valid
tPR
Output Data Setup Time
top
850
600
400
ns
Output Data Hold Time
tPD
200
130
90
ns
Input Data Hold Time
tPF
0
PROG Pulse Width
tpp
1500
1060
700
ns
Port 2 I/O Data Setup
to ALE
tPL
460
300
160
ns
Port 2 I/O Data Hold
to ALE
tLP
150
90
40
ns
Port Output From ALE
tpv
~.
Notes: (1) Control Outputs CL
940
1300
250
190
0
850
= 80 pf,
650
140
0
510
660
Bus Outputs CL
ns
ns
ns
= 150 pf
(2) Bus High I mpedance Load 20 pf
(3) MC means machine cycle
Waveforms
INSTRUCTION FETCH FROM EXTERNAL PROGRAM MEMORY
I::==='-
ALE
--.J
tLL
----l
..
1
tCY
"
tCC2
BUS
-----L
_ _ _" ' - -_ _ _ _ _ _ _ _ _
r""1
--1
tCA2
f---
FLOATING
FLOATING
1 - - - - - - tAD2
3-7
UMB04B/B035/B049/B039
WRITE TO EXTERNAL DATA MEMORY
ALE~
i----c----------------------------~I
WR
----to.j4--~
tCC1
L
tCAl
____________~----------------------
I
BUS
FLOATING
FLOATING
READ FROM EXTERNAL DATA MEMORY
ALE.~
L
~ tCCl _ _ _ _
·~I·-t-CA-l~.1
RD
------------------~I
----~-----------
•
tAFl
I--FLOATING
FLOATING
FLOATING
BUS
I--
tRD1
tAD1 --'--------1
PORT 2 TIMING
ALE
J
\
EXPANDER
PORT
OUTPUT
EXPANDER
PORT
PORT CONTROL
PORT 20-23 DATA
PCH
OUTPUT DATA
II
- - - - - - - - - - " " ,-------"'\ , . - - - - - - . ----"'"
PCH
INPUT
PORT 20-23 DATA
PORT CONTROL
PROG
I/O PORT TIMING
I
1ST CYCLE
ALE
PSEN
tpL -12ND CYCLE
J \ _ _ _--i{
\~------lV
o0~~~i =:J(__________
P_C_H________
~~~
r--
tpv
1
r~-I----ll
\..
I
\
I
PO_R_T_2_0_-2_3_D~AT-A-----Jf,.--N-EW--P2-0--2-3-D-A-TA--)(~_P_C_H
_____
P24-27
P10-17 _ _ _ _ _ _ _ _ _
PORT
10-17
DATA
OUTPUT
_24-27
_ _PORT
__
__
____
3-8
X
NEW PORT DATA
__
~----JI'-----------
(l)UMC
UM8048/8035/8049/8039
Pin Description
Designation
Pin
Vss
20
Circuit GND Potential
VDD
26
+5V during operation. Low power standby pin
Vee
40
Main power supply; +5V during operation
PROG
25
Port 1:
P10-P17
Functions
Output strobe for UM8243 I/O expander
27-34
8-bit quasi-bid irectional port
35-38
21-24
8-bit quasi-bidirectional port
P20-P23 contain the four high order program counter bits during an external progr.am
Port 2:
P24-P27
P20-P23
fetch and serve as a 4-bit I/O expander bus for UM8243.
BUS: DO-D7
12-19
True bidirectional port which can be written or read synchronously using the RD, WR
strQbes.
The port can also be statically latched. Contains the 8 low order program
counter bits during an external program memory fetch, and receives the addressed
instruction under control of PSEN.
They also contains the address and data during an external RAM data access instruction under control of ALE, RD, and WR.
TO
1
Input pin testable using the conditional transfer instructions JTO and JNTO. TO can
be designated as clock output using ENTO CLK instruction.
T1
39
Input pin testable using the JT1, and JNT1 instructions. Can be designated the timer/
counter input using the STRT CNT Instruction.
TNT
(Active Low)
RD
(Active Low)
6
Interrupt input.
Initiates an interrupt if interrupt is enabled. Interrupt is disabled
after a reset. Also testable with conditional jump instruction. (Active Low)
8
Output strobe activated during a BUS read. Can be used to enable data onto the BUS
from an external device. Used as a Read Strobe to External Data Memory.
WR
(Active Low)
10
Output strobe during a BUS write. Used as write strobe to External Data Memory.
RESET
(Active Low)
4
ALE
11
Input which is used to initialize the processor.
Also used during verification, and
power down.
Address Latch Enable.
This signal occurs once during each cycle and is useful as
a clock output. The negative edge of ALE strobes address into external data and
program memory.
PSEN
(Active Low)
9
SS
(Active Low)
5
EA
7
Program Store Enable.
memory.
This output occurs only during a fetch to externa'i program
Single step input can be used in conjuction with ALE to "single step" the processor
through each instruction
External Access input which for cess all program memory fetches to reference external
memory.
Useful for emulation and debug, and essential for testing and program
verification
XTAL1
2
One side of crystal input for internal oscillator Also input for external source.
XTAL2
3
Other side of crystal'input
UMS04S!S035/S049/S039
Instruction Set
Mnemonic
Functions
Descriptions
Instruction Codes
Cycles
Bytes
1
dO
2
2
07
06 05 04 03 02
01
DO
0
d7
0
d6
0
d5
0
d4
0
d3
0
d2
1
d1
Accumulntor
ADD A, #data
(A)+-(A) + data
Add immediate the specified Data to
the Accumulator
ADD A, Rr
(A) +-(A) + (Rr)
forr=0-7
Add contents of designated register
to the Accumulator
0
1
1
0
1
r
r
r
1
1
ADDA,@Rr
(A)+-(A) + ((Rr))
for r = 0-1
Add indirect the contents of the data
memory location to the Accumulator
0
1
1
0
0
0
0
r
1
1
ADDC Al#
data
(A)+-(A) + (C) + data
Add immediate with carry the specified
data to the Accumulator
.0
d7
0
d6
0
d5
1
d4
0
d3
0
d2
1
d1
1
dO
2
2
ADDC A, Rr
(A)+-(A) + (C) + (Rr)
for r = 0-7
Add with carry the contents of the
designated register to the Accumulator
0
1
1
1
1
r
r
r
1
1
ADDC A,@Rr
(A)+-(A) + (C) + ((Rr))
for r = 0-1
Add indirect with carry the contents of
0
data memory location to the Accumulator
1
1
1
0
0
0
r
1
1
ANL A, #data
(A) +- (A) AN 0 data
Logical AND specified immediate Data
with Accumulator
0
d7
1
d6
0
d5
1
d4
0
d3
0
d2
1
d1
1
dO
2
2
ANL A, Rr
(A)+-(A) AND .(Rr)
forr=0-7
Logical NAD contents of designated
register with Accumulator
0
1
0
1
1
r
r
r
1
1
ANL A,@Rr
(A)+-(A) AND ((Rd)
for r = 0-1
Logical AND indirect the contents of
data memory with Accumulator
0
1
0
1
0
0
0
r
1
1
CPL A
(A)+-NOT (A)
Complement the contents of the
Accumulator
0
0
1
1
0
1
1
1
1
1
CLR A
(A)+-O
DAA
.
Clear the contents of the Accumulator
0
0
1
0
0
1
1
1
1
1
Decimal Adjust the contents of the
Accumulator
0
1
0
1
0
1
1
1
1
1
DECA
(A)+-(A) - 1
Decrement by 1 the Accumulator's
contents
0
0
0
0
0
1
1
1
1
1
INCA
(A)+-(A) + 1
Increment by 1 the Accumulator's
contents
0
0
0
1
0
1
1
1
1
1
ORL A, #data
(A) +-(A) OR data
Logical OR specified immediate data
with Accumulator
0
1
d6
0
0
0
0
d4
d3
d2
1
dO
2
d5
1
dl
2
d7
ORL A, Rr
(A)+- (A) OR (Rr)
fror=0-7
Logical OR contents of designated
register with Accumulator
0
1
0
0
1
r
r
r
1
1
ORL A,@Rr
(A)+-(A) OR ((Rr))
for r = 0-1
Logical OR indirect the contents of data
memory location with Accumulator
0
1
0
0
0
0
0
r
1
1
RLA
(AN+l) +-(AN)
(AO)+-(A7)
for N = 0-6
Rotate Accumulator left by 1 bit
without carry
1
1
1
0
0
1
1
1
1
1
RLCA
(AN+1)+- (AN);
N = 0-6, (AO) +-(C)
(C)+- (A7)
Rotate Accumulator left by 1 bit
through carry
1
1
1
1
0
1
1
1
1
1
RR A
(AN)+-(AN+l);
N = 0-6, (A7)+-(AO)
Rotate Accumulator right by 1 bit
without carry
0
1
1
1
0
1
1
1
1
1
RRCA
(AN) +-(AN+1);
N=O-6, (A7)+-(C)
(C)+-(AO)
Rotate Accumulator right by 1 bit
through carry
0
1
1
0
0
1
1
1
1
1
SWAP A
(A4-7) ~ (AO-3)
Swap the two 4-bit nibbles in the
Accumulator
0
1
0
0
0
1
1
1
1
1
XRLA1,#
data
(A)+-(A) XOR data
Logic XO R specified immediate data
with Accumulator
1
d7
1
d6
0
d5
1
d4
0
d3
0
d2
1
dl
1
dO
2
2
XRL A, Rr
(A)+-(A) XOR (Rr)
for r = 0-7
Logical XOR contents of designated
register with Accumulator
1
1
0
1
1
r
r
r
1
1
XRLA,@Rr
(A)+-(A) XOR ((Rr))
for r = 0-1
Logical XOR indirect the contents of
data memory location with Accumulator
1
1
0
1
0
0
0
r
1
1
3-10
UMS04S/S035/S049/S039
Instruction Set (Continued)
Mnemonic
Functions
Descriptions
Instruction Codes
07
06 05
04 03 02
01
DO
Cycles
Bytes
Branch
DJNZ Rr,addr
(Rr) «-(Rr) -1; r=0-7
If (Rd ,*0
(PCO-7)«-addr
Decrement the specified register and
test contents
1
a7
1
a6
1
a5
0
a4
1
a3
r
a2
r
a1
r
aO
2
2
JBb addr
(PCO-7)«-addr if Bb= 1
(PC) «-(PC) +2 if Bb=O
Jump to specified address if
Accumulator bit is set
b2
a7
b1
a6
bO
a5
1
a4
0
a3
0
a2
1
a1
0
aO
2
2
JC addr
(PCO-7)«-addrif C=1
(PC)«-(PC)+2 if C=O
Jump to sepecified address if carry
flag is set
1
a7
1
a6
1
a5
1
a4
0
a3
1
a2
1
a1
0
aO
2
2
JFO addr
(PCO-7)«- addr if PO= 1
(PC)«-(PC) +2 if FO=O
J,ump to specified address if Flag FO
is set
1
a7
0
a6
1
a5
1
a4
0
1
a2
1
a1
0
aO
2
2
a3
JF1 addr
(PCO-7)«- addr if F1 = 1
(PC) «- (PC) +2 if F1 =0
Jump to specified address if Flag F 1
is set
0
a7
1
a6
1
a5
1
a4
0
a3
1
a2
1
a1
0
aO
2
2
JMP addr
(PC8-10)«-addr 8-10
(PCO-7)«-addr 0-7
(PC11)«-DBF
Direct Jump to specified address
with in the 2Kaddress block
al0
a7
a9
a6
a8
a5
0
a4
0
a3
1
a2
0
a1
0
aO
2
2
JMPP @A
(PCO-7)«-((A))
Jump indirect to specified address
with address page
1
0
1
1
0
0
1
1
2
1
JNC addr
(PCO-7)«- addr if C=O
(PC)«-(PC) +2 if C=1
Jump to specified address if carry flag
is low
1
a7
1
1
a5
0
a4
0
a3
1
a2
1
a1
0
aO
2
2
a6
JN1 addr
(PCO-71«-addr if 1=0
(PC)«-(PC)+2 if 1=1
Jump to specified address if interrupt
is low
1
a7
0
a6
0
a5
0
a4
0
a3
1
a2
1
a1
0
aO
2
2
JNTO addr
(PCO-7)«-addr ifTO=O
(PC) «- (PC) +2 if TO= 1
Jump to specified address if Test 0
is low
0
a7
0
a6
1
a5
0
a4
0
a3
1
a2
1
a1
0
aO
2
2
JNT1 addr
(PCO-7)«-addr ifT1 =0
(PC) «- (PC) +2 if T1 = 1
Jump to specified address if Test 1
is low
0
a7
1
a6
0
a5
0
a4
0
a3
1
a2
1
a1
0
aO
2
2
JNZ addr
(PCO-7)«-addr if A*'O
(PC)«-(PC)+2 if A=O
Jump to specified address if
Accumulator is non-zero
1
a7
0
a6
0
a5
1
a4
0
a3
1
a2
1 0
a1
aO
2
2
JTF addr
(PCO-7)«- addr if TF= 1 Jump to specified address if Timer Flag
(PC) «-(PC) +2 if TF=O is set to 1
0
a7
0
a6
0
a5
1
a4
0
a3
1
a2
1
0
a1 • aO
2
2
JTO addr
(PCO-7) «-addr if TO= 1 Jump to specified address if Test 0
(PC)«-(PC)+2 ifTO=O
is a 1
0
a7
0
a6
1
a5
1
a4
0
'a3
1
a2
1
a1
0
aO
2
2
JT1 addr
(PCO-7) «-addr if T1 = 1 Jump to specified address if Test 1
(PC)«-(PC)+2 if T1 =0
is a 1
0
'a7
1
a6
0
a5
1
a4
0
a3
1
a2
1
a1
0
aO
2
2
JZ addr
(PC07) «-addr if A=O
(PC) «- (PC) +2 if A*'O
1
a7
1
a6
0
a5
0
a4
0
a3
1
a2
1
a1
0
aO
2
2
0
0
0
0
0
1
0
1
1
1
0
1
0
1
0
1
1
1
1
Jump to specified address if
Accumulator is 0
Control
EN I
Enable the External Interrup input
DIS I
Disable the External I nterrupt input
0
0
Enable the Clock Output pin TO
0
1
1
1
0
1
0
1
1
SEL MBO
(DBF)«-O
Select Bank O-(Iocations 0-02047) of
program Memory
1
1
1
0
0
1
0
1
1
1
SEL MB1
(DBF)«-1
Select Bank 1. (locations 2048-4095) of
Program Memory
1
1
1
1
0
1
0
1
1
1
SEl RBO
(BS) «-0
Select Bank 0 (locations 0-7) of Data
Memory
1
1
0
0
0
1
0
1
1
1
SEL RB1
(BS)«-1
Select Bank 1 (iocations 24-31) of
Data Memory
1
1
0
1
0
1
0
1
1
1
MOV A. #data
(A)«-data
Move immediate the specified data into
the Accumulator
0
d7
0
d6
1
d5
0
d4
0
d3
0
d2
1
d1
1
dO
2
2
MOV A. Rr
(A)«-(Rrl; r=0-7
Move the contents of the, designated
registers into the Accumulator
1
1
1
1
1
r
r
r
1
1
ENTO ClK
Data Moves
3-11
UMS04S/S035/S049/S039
Instruction Set (Continued)
Mnemonic
Functions
Descriptions
Instruction Codes
07
06 05 04 03 02
01
DO
Cycles
Bytes
Data Moves (Cont.)
MOVA,@Rr
(A) +- ((Rr)); r=O-l
Move indirect the contents data
memory location into the Accumulator
1
1
1
1
a
a
a
r
1
1
MOV A,PSW
(A) +- (PSW)
Move contents of the Program Status
Word into the Accumulator
1
1
a
a
a
1
1
1
1
1
MOV Rr, #
data
(Rr)+- data; r=0-7
Move immediate the spocified data into
the designated register
1
d7
a
d6
1
d5
1
d4
1
d3
r
d2
r
d1
r
dO
2
2
MOV Rr, A
(Rr)+- (A); r=0-7
Move Accumulator Contents into the
designated register
1
a
1
a
1
r
r
r
1
1'
MOV@Rr,A
((Rr)) +- (A), r=O-l
Move indirect Accumulator Contents
into data memory location
1
a
1
a
a
a
a
r
1
1
MOV@ Rr, #
data
((Rr))+-data; r=0-1
Move immediate the specified data into
data memory
1
d7
0
d6
1
d5
1
d4
0
d3
a
d2
0
d1
r
dO
2
2
MOV PSW, A
(PSW) +- (A)
Move contents of Accumulator into the
program status word
1
1
a
1
0
1
1
1
1
1
MOVP A,@A
(PCO-7) +- (A)
(A) +- ((PC))
Move data in the current page into the
Accumulator
1
0
1
0
0
a
1
1
2
1
MOVP3A,@A
(PCO-7) +- (A)
(PC8~ 10) +- 011
(A)~ ((PC))
Move Program data in Page 3 into the
Accumulator
1
1
1
0
0
0
1
1
2
1
MOVX A,@ R
(A) +- ((Rr)); r=O-l
Move indirect the contents of external
data memory into the Accumulator
1
0
0
0
0
a
0
r
2
1
MOVX@R,A
((Rr)) +- (A), r=0-,1
Move indirect the contents of the
Accumulator into external data memory
1
0
0
1
0
a
0
r
2
1
XCH A, Rr
(A)
Exchange the Accumulator and
designated register's contents,
0
0
1
0
1
r
r
r
1
1
XCH A,@ Rr
(A) +- ((Rr)); r=O-1
Exchange indirect contents of Accumulator and location in data,memory
0
0
1
0
0
0
0
r
1
1
XCHD A,@ Rr
(j\O-3) ~ ((RrO-3));
Exchange indirect 4 bit contents of
Accumulator and data memory
0
0
1
1
0
0
a
r
1
1
~
(Rr); r=0-7
r=O-l
Flags
CPL C
(C) +- NOT (C)
Complement carry bit
1
0
1
0
0
1
1
1
1
1
CPL FO
(FO) +- NOT (Fa)
Complement Flag FO
1
a
a
1
0
1
0
1
1
1
CPL F1
(F1) +- NOT (F1)
Complement Flag Fl
1
0
1
1
0
1
0
1
1
1
CLR C
(C) +- 0
Clear carry bit to 0
1
0
a
1
a
1
1
1
1
1
CLR Fa
(FO) +- 0
Clear Flag a to 0
1
0
a
0
0
1
0
1
1
1
CLR F1
(Fl) +- 0
Clear Flag 1 to a
1
0
1
0
0
1
0
1
1
1
a
0
d1
0
dO
2
2
Input/Output
ANL B'US,#,
data
(BUS) +- (BUS) AND
data
Logical AND immediate specified data
with contents of Bus
1
d7
a
d6
0
d5
1
d4
1
d3
d2
ANL Pp, #
data
(Pp) +- (Pp) AND data
p=1-2
Logical AND immediate specified data
with designated port (1 or 2)
1
d7
0
d6
0
d5
1
d4
1
d3
p
d1
p
dO
2
2
d2
ANLD Pp, A
(Pp) +- (Pp) AND (AO-3)
p=4-7
Logical AND contents of Accumulator
with designated port (4-7)
1
a
a
1
1
1
p
p
2
1
IN A,Pp
(A) +- (Pp), p= 1-2
I nput data from designated port (1-2)
into Accumulator
0
0
0
0
1
a
p
p
2
1
INS A, BUS
(A)
Input strobed Bus data into
Accumulator
a
0
0
0
1
a
0
0
2
1
Move contents of designated port
(4-7) into Accumulator
0
0
0
0
1
1
p
p
2
1
Move contents of Accumulator into
designated port (4-7)
0
1
1
1
1
p
p
1
2
1
MOVD A,Pp
~(BUS)
(AO-3)~(Pp);
(A1-7)+-O
MOVD Pp, A
(Pp)~
p=4-7
AO-3;
p=4-7
3-12
a
UMS04S/S035/S049/S039
Instruction Set (Continued)
Functions
Mnemonic
Instruction Codes
Descriptions
06 05 04 03 02 01
07
DO
Cycles
Bytes
2
2
Input/Output (Cont.)
ORL BUS,
data
#
(BUS)
data
~
(BUS) OR
Logical OR immediate specified data
with contents of Bus
1
0
0
0
1
0
0
0
d7
d6
d5
d4
d3
d2
dl
dO
0
C
1
1
P
P
2
1
2
2
(Pp)+-(Pp) OR (AO-3)
p=4-7
Logical OR contents of Accumulator
with designated port (4-7)
1
0
(Pp) +- (Pp) OR data
p=1-2
Logical OR immediate specified data
with designated port (1-2)
1
d7
0
0
0
P
P
d5
d4
1
d3
0
d6
d2
dl
dO
OUTL BUS, A
(BUS) +- (A)
Output contents of Accumulator onto
Bus
0
0
o.
0
0
0
1
0
2
1
OUTL Pp, A
(Pp)
Output contents of Accumulator to
designated port (1-2)
0
0
1
1
1
0
P
P
2
1
DEC Rr
(Rr) +- (Rr) - 1;
r=0-7
Decrement by 1 contents of designated
register
1
1
0
0
1
r
r
r
1
1
INC Rr
(Rr)+-(Rr)+l;
r=0-7
Increment by 1 conents of designated
register
0
0
0
1
1
r
r
r
1
INC@R
((Rr)) ~ ((Rr)) + 1;
r=0-1
I ncrement indirect by 1 the contents
of data memory location
0
0
0
1
0
0
0
r
1
1
Call addr
((SP))+-(PC), (PSW4-7)
(SP) +- (SP) + 1
(PC8-10)+-addr 8-10
(PCO-7) +- addr 0-7
(PC11) +- DBF
Call designated Subroutine
al0
a7
a9
a6
a8
a5
1
a4
0
a3
1
a2
0
al
0
aO
2
2
RET
(SP) +- (SP) - 1
(PC) ~ ((SP))
Return from Subroutine without
restoring Program Status Word
1
0
0
0
0
0
1
1
2
1
(SP) ~ (SP) - 1
(PC) +- ((SP))
(PSW4-7) +- ((SP))
Return from Subroutine restoring
Program Status Word
1
0
0
1
0
0
1
1
2
1
ORLD Pp, A
ORL Pp,
data
#
~
(A); p=1-2
Register
1
I
Subroutine
, RETR
."
Timer/Counter
EN TCNTI
Enable Internal interrupt Flag for
Timer/Counter output
0
0
1
0
0
1
0
1
1
1
DIS TCNTI
Disable Internal interrupt Flag for
Timer/Counter output
0
0
1
1
0
1
0
1
1
1
MOV A, T
(A) +- (T)
Move contents of Timer/Counter into
Accumulator
0
1
0
0
0
0
1
0
1
1
MOV T,A
(T) +- (A)
Move contents of Accumulator into
Timer/Counter
0
1
1
0
0
0
1
0
1
1
STOP TCNT
Stop Cou nt for Event Cou nter
0
1
1
·0
0
1
0
1
1
1
STRT CNT
Start Count for Event Counter
0
1
0
0
0
1
0
1
1
1
STRTT
Start Counter foe Timer
0
1
a
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
1
1
Miscellaneous
NOP
No Operation performed
Notes: 1. Instruction Code Designations rand p form the binary representation of the Registers and Ports involved.
2. References to the address and data are specified in bytes 2 and/or 1 of the instruction.
3. Numerical Subscripts appearing in the FUNCTION column reference· the specific bits affected.
Ordering Information
Max. Freq.
Part Number
UMS035-6
6 MHz
UMS039-6
UMS035-S
S MHz
UMS039-S
UMS035-11
11 MHz
UMS039-11
3-13
eUMC
======::::
UMBOS 1 / UMB031
Single Chip 8-Bit Microcomputer
Features
• UM8048 architecture enhanced with:
• Non-paged jumps
• Direct addressing
• Four 8-register banks
• Stack depth up to 128 -bytes
• Multiply, divide, subtract, compare
• Most instructions execute in 1~s
• 4~s multiply and divide
• 4K x BROM
• 128 x 8 RAM
• Four 8-bit ports, 32 I/O lines
• Two 16-bit timer/event counters
• High-performance full-duplex serial channel
• External memory expandable to 128K
• Boolean processor
General Description
it lacks the program memory. For systems. that req.u ire
extra capability, theUM8051 can be expanded using
standard TTL compatible memories.
The UM8051/8031 is a stand-alone, high-performance
single-chip computer fabricated with UMC's highly-reliable
+5 Volt, NMOS technology and packaged in a 40-pin DIP.
It provides the hardware features, architectural enhancements and new instructions that are necessary to make
it a. powerful·and cost effective controller for applications
requiring up to 64K bytes of program memory and/or up
to 64K bytes of data storage.
The UM8051 microcomputer, like its UM8048 predecessor,
is efficient both as a controller and as an arithmetic processor. The UM8051 has extensive facilities for binary and
BCD arithmetic and excels in bit-handling capabilities.
Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and
15% three-byte instructions. With a 12 MHz crystal, 58%
of the instructions execute in 1~s, 40% in 2~s and multiply
and divide require only 4~s. Among the many instructions
added to the standard UM8048 instruction set are multiply,
divide, subtract and compare.
The UM8051/8031 contains a non-volatile 4K x 8 readonly program memory, a volatile 128 x 8 read/write data
memory; 32 I/O lines; two 16-bit timer/counters; a fivesource, two-priority-Ievel. nested interrupt structure; a
serial I/O port for either mUlti-processor communications,
I/O expansion, or full duplex UART; and on-chip oscillator
and clock circuits. The UM8031 is identical, except that
Pin Configuration
Logic Symbol
RST
Pl.0
Pl.l
Pl.2
1'1.3
Pl.4
Pl.5
Pl.6
P1.7
RST
RXD/P3.0
TXD/P3.1
INTO/P3.2
TN'i'T/P3.3
TO/P3.4
Tl/P3.4
WR/P3.6
RD/P3.7
XTAL2
XTALl
VSS
Vcc
!,!O.O/ADO
PO.l/ADl
PO.2/AD2
PO.3/AD3
PO.4/AD4
PO.5/AD5
PO.6/AD6
PO.7/AD7
EA
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A 12
P2.3/All
P2.2/Al0
P2.1/A9
P2.0/A8
PORT
o
<=>
ADDRESS
AND
DATA BUS
EA
PSEN
ALE
PORT
U'J
z
~l· RXD_~
~
:J
u.
~
«
o
6
TXDINTO- " ' INT1_ ITO- ~
T l - Cl.
WR-RD-
~
U'J
3-14
PORT
2
~
t-y
ADDRESS
BUS
UMBOS 1 / UMB031
Block 0 iagram
FREQUENCY
REFERENCE
1--
--i------------------i--r--,
COUNTERS
I
OSCI LLATOR
&
TIMING
4096 BYTES
PROGRAM
MEMORY 8051
128 BYTES
DATA MEMORY
TWO 16-BIT
TIMER/EVENT
COUNTERS
~7
'S2
\/
PROGRAMMABLE I/O
PROGRAMMABLE
SERIAL PORT
• FU LL DUPLEX
UART
• SYNCHRONOUS
SHIFTER
8051
-'CPU
64K-BYTE BUS
EXPANSION
CONTROL
INTERRUPTS
i~
L_ -
--------
INTERRUPTS
CONTROL
f---
--
--
PARALLEL PORTS.
ADDRESS/DATA BUS
AND I/O PINS
3-15
I
I
I
I
I
L~ /~ i~ ~
,-----
I
---- ---
SERIAL
IN
-- _J
SERIAL
OUT
UM8051/UMS031
Pin Description
Designation
Pin
Functions
Vss
20
Circuit ground potential.
+5V power supply during operation and program verification.
Vee
40
Port 0
32-39
Port 0 is an 8-bit open drain bidirectional I/O port. It is also the multiplexed low-order
address and data bus when using external memory. It is used for data input and output
during programming and verification. Port 0 can sink/source eight TTL loads.
Port 1
1-8
Port 1 is an 8-bit quasi-bidirectional I/O port. It is used for the low-order address byte
during program verification. Port 1 can sink/source four TTL load.
Port 2
21-28
Port 2 is an 8-bit bidirectional I/O port. It also emits the high-order address byte
when accessing external memory. It is used for the high-order address and the control
,signals during program verification. Port 2 can sink/source four TTL load.
Port 3
10-17
Port 3 is an 8-bit quasI-bidirectional I/O port with internal pullups. It also contains the
interrupt, timer, serial port and RD and WR pins that are used by various options. The
. output latch corresponding to a secondary function must be programmed to a one (1) for
that function to operate. Port 3 can sink/source four TTL.load. The secondary function are
assigned to the pins of Port 3, as follows:
-RXD/data (P3.0). Serial port's receiver data input (asynchronous).
- TXD/clock (P3.1). Serial port's transmitter data output (asynchronous).
-INTO (P3.2). Interrupt 0 input.
-INT1 (P3.3). Interrupt 1 input.
- TO (P3.4l. I nput to cou nter O.
- T1 (P3.5). Input to counter 1.
-WR (P3.6). The write control signal latches the data byte from Port 0 into the External
Data Memory.
-RD (P3.7l. The read control signal enables External Data Memory to Port O.
RST
9
A high on this pin for two machine cycles while the oscillator is running resets the device.
A small external pulldown resistor (~ 8.2kn) from RST to VSS permits power-on reset
when a capacitor (~1O J.tf) is also connected from this pin to Vee.
ALE
30
Address Latch Enable output for latching the low byte of the address during accesses to
external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except
during an external data memory access at which time one ALE pulse is skipped. ALE can
sink/source 8 LS TTL inputs.
PSEN
29
The Program Store Enable output is a con~rol signal that enables the external Program
Memory to the bus during external fetch operations. It is activated every six oscillator
periods except during external data memory access. PSEN remains high during internal
program execution.
EA
31
When held at a TTL high level, the 8051 executes instructions from the internal ROM
when the PC is less than 4096. When held at aTT L low level, the 8031/8051 fetches
all instructions from external Program Memory. Do not float EA during normal operation.
XTAL1
19
I nput to the inverting ampl ifier that forms part of the oscillator. This pin should be connected to ground when an external oscillator is used.
XTAL2
18
Output of the inverting amplifier that forms part of the oscillator, and input to the internal
clock generator. XTAL2 receives the oscillator signal when an external oscillator is used.
3-16
UMBOS 1 / UMB031
Absolute Maximum Ratings*
*Comments
Ambient Temperature Under Bias ........ OoC to 70°C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied and exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature . . . . . . . . . . . . . -65°C to + 150°C
Voltage on Any Pin With Respect to
Ground (VSS)
.......... .
-0.5Vto+7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 1 Watts
D. C. Characteristics
(TA
= ooc to 70°C;
Vee
= 5V ±
10%; Vss
= OV)
Max.
Units
20
0.8
Vee + 0.5
V
V
2.5
Vee + 0.5
V
XTALl to VSS
0.45
V
10L= 1.5mA
0.45
V
10L = 3.2mA
V
V
pA
10H = -BOpA
Min.
-0.5
VIH
Parameter
Input Low Voltage
Input High Voltage (Except RST and XTAL2)
VIHl
Input High Voltage to RST For Reset. XT AL2
VOL
Output Low
Output Low
(Note 1)
Output High
Output High
Symbol
VI L
VOLl
VOH
VOHl
Voltage Ports 1,2,3 (Note 1)
Voltage Port 0, ALE, PSEN
Voltage Ports 1,2,3
Voltage Port 0, ALE, PSEI'J
2.4
2.4
Test Conditions
10 H = -400pA
ilL
IIL2
Log ical 0 Input Cu rrent Ports 1 , 2, 3
Logical 0 Input Current for XT AL2
-800
-2.5
mA
Vin = 0.45V
XTAL 1 = VSS, Vin
III
Input Leakage Current To Port 0, EA
±10
pA
0.45V
IIH1
Input High Current to RST/VPD For Reset
500
pA
Vin
ICC
Power Supply Current
125
mA
All outputs disconnected
CIO
Capacitance of I/O Buffer
10
pF
fc
= 0.45V
< Vin < Vee
< Vee -1.5V
= 1 MHz,
TA
= 25°C
Note: VOL is degraded when the 8031/8051 rapidly discharges external capacitance. This AC noise is most pronounced
during emission of address data. When using external memory, locate the latch or buffer as close to the 8031/8051
as possible.
A.C. Characteristics
(TA = ooc to 70°C, Vee
outputs = 80 pF)
= 5V ±
10%, Vss
= OV,
CL for Port 0, ALE and PSEN Outputs = 100 pF; CL for all other
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol
Min.
TLHLL
TAVLL
.TLLAX
TLLlV
TLLPL
TPLPH
TPLIV
TPXIX
TPXIZ
TPXAV
TAVIV
TAZPL
ALE Pu Ise Width
Address Setup to ALE
Address Hold After ALE
ALE to Valid Instr In
ALE To PSEN
PSEN Pulse Width
PSEN To Valid Instr In
Input Instr Hold After PSEN
Input Instr Float After PSEN
Address Valid After PSEN
Address To Valid Instr In
Address Float To PSEN
Variable Clock
1/TCLCL = 3.5 MHz to 12 MHz
12 MHz 1Clock
Parameter
Max.
127
43
48
233
58
215
125
0
53
75
302
0
3-17
Units
ns
ns
ns
Min.
2TCLCL-40
TCLCL-40
TCLCL-35
ns
ns
TCLCL-25
Max.
4TCLCL-100
ns
ns
3TCLCL-35
ns
ns
ns
ns
ns
0
3TCLCL-125
TCLCL-20
TCLCL-8
5TCLCL-115
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UMS051 / UMS031
EXTERNAL DATA MEMORY CHARACTERISTICS
Variable Clock
1/TCLCL == 3.5 MHz to 12 MHz
12 M,Hz Clock
Parameter
Symbol
Unit
Min.
TRLRH
RD Pulse Width
400
ns
6TCLCL-100
ns
ns
Min.
Max.
Max.
Unit
TWLWH
WR Pulse Width
400
ns
6TCLCL-100
TLLAX
Address Hold After ALE
48
ns
TCLCL-35
TRLDV
RD To Valid Data In
TRHDX
Data Ho Id After RD
TRHDZ
Data Float After RD
97
ns
2TCLCL-70
TLLDV
ALE To Valid Data In
517
ns
8TCLCL-150
ns
TAVDV
Address To Valid Data In
585
ns
9TCLCL-165
ns
300
ns
3TCLCL-50
ns
4TCLCL-130
250
TLLWL
ALE To WR or RD
200
Address To WR or R D
203
TWHLH
WR or RD High To ALE High
TDVWX
Data Valid To~WR Transition
TOVWH
Data Setup Before WR
TWHOX
Data Hold After WR
TRLAZ
Address Float After RD
43
5TCLCL-165
ns
0
TAVWL
ns
123
ns
0
ns
ns
3TCLCL + 50
ns
ns
ns
TCLCL-40
23
ns
TCLCL-60
ns
433
ns
7TCLCL-150
ns
ns
TCLCL-50
33
0
TCLCL + 40
ns
ns
ns
ns
0
Datum
Emitting Ports
Degraded I/O Lines
VOL (peak) (Max.)
Address
P2, PO
P1, P3
0.8V
Write Data
PO
Pl, P3, ALE
0.8V
EXTERNAL CLOCK DRIVE CHARACTERISTICS (XTAL2)
Symbol
Variable Clock
freq = 3.5 MHz to 12 MHz
Parameter
Min.
Max.
83.3
286
TCLCL
Osci lIator Period
TCHCX
High Time
20
20
Unit
ns
ns
TCLCX
Low Time
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
3-18
ns
UMBOS 1 / UM8031
A.C. Timing Diagrams
EXTERNAL PROGRAM MEMORY READ CYCLE
EXTERNAL DATA MEMORY READ CYCLE
TWHLH
TLLDV
ALE
TLLWL
RD --------~-----_
1 4 - - - - - - TRLRH - - - - - I l r - - - ~---TAVWL~~~1'--~~---4_-----~~~-J
~TLLAX
TRHDX
DATA IN
AO-A7
POTR 0
ADDRESS AB-A15 OR SFR-P2
EXTERNAL DATA MEMORY WRITE CYCLE
TWHLH
ALE
vffi--_________~------~
I~-------
TWLWH
TDV_W_X_ _ TOVWH
DATA OUT
PORTO
ADDRESS AB-A15 OR SFR-P2
A.C. Testing Input/Output, Float Waveforms
INPUT/OUTPUT
2A=X2-O
0.45
FLOAT
TEST POINTS
2-0)<=
..O._-S_ _ _ _ _ _ _ _ _..
O-_.S
2.4
j
0_45 .
2
°
FLOAT
2
t
°
D
. . S---------------o-..s.
2.4
0.45
AC inputs during testing are driven at 2.4V for a logic "1" and 0.45V for logic "0". Timing measurements are made at
2.0V for a logic "1" and 0.8V for a logic. "0". For timing purposes, the float state is defined as the point at which a PO
pin sinks 3.2mA or sources 400 J-LA at the vo.ltage test levels.
3-19
UMB051 / UMB031
Clock Waveforms
INTERNAL
CLOCK
STATE 4
P1
I
STATE 5
P2
I
P1
STATE 6
P2
P1
I
P2
STATE 1
STATE 2
P1
P1
I
P2
I
STATE 3
P2
P1
I
STATE 4
P2
P1
I
STATE 5
P2
I
P1
P2
XTAL2
I
I
~
ALE
EXTERNAL PROGRAM MEMORY FETCH'
I
THESE SIGNALS ARE NOT
ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
I\
1
......._______----1
L
1
PO
P2(EXT)
INDICATES ADDRESS TRANSIONS
READ CYCLE
RD
DPL OR RI
OUT
PO
,':4
DOH IS EMITTED
DURING THIS PERIOD
FLOAT
PCL OUT (IF P80GRAM
MEMORY IS EXTERNAL)
S="~D-----"'.l
L
\
INDI.cATf:S OPH OR P2 SFR TO PCH TRANSITIONS
P2
WRITE CYCLE
I PCL OUT (EVEN IF PROGRAM
WR
~------------ MEMORY IS INTERNAL)
DPL OR RI
OUT
PO
P2
INDICATES DPH OR P2 SFR TO PCH TRANSITIONS
PORT OPERASTION
OLD DATA
MOV PORT SRC
MOVDEST,PO
MOV DEST PORT (P1 P2 P3)
I~
·L
f
--.~I••--'-\-.~, PCL OUT (I F PROG RAM
I MEMORY IS EXTERNAL)
..
I ....-=--=--=--=--=--=--=--=--=--=--=--=--:...-O-A-TA-O-U-T--------------------
I NEW DATA
PO PINS SAMPLED
~--------------------------- ~~----t::::I
(INCLUDES INTO, INT1, TO, T1)
...
PO PINS SAMPLED
~~--------_--------------------_I
SERIAL PORT SHIFT CLOCK
TXD
(MODE 0)
. ,
L---
~~N~2S:~PLED
P1, P2, P3 PINS SAMPLED
I~
RXD SAMPLED
RXD SAMPLED
=
This diagram indicates when signals are clocked internally,
and component to component.
The time it takes the signals to propagate to the pins,
25°C, fully loaded) RD and WR propagation delays are
however, ranges from 25 to 15 ns.
approximately 50 ns. The other signals are typically 85 ns.
This propagation
Typically though, (T A
delay is dependent on variables ~such as temperature and
Propagation delays are incorporated in the AC specifica-
pin .Ioading. Propagation also varies from output to output
tions.
3-20
UMBOS 1 / UMB031
UM8051 Instruction Set Summary
INTERRUPT RESPONSE TIME
Data
To finish execution of cummt instruction, respond
to the interrupt request, push the PC and to vector
to the first instruction of the interrupt service program
requires 38 to 81 oscillator periods (3 to 7p.s @
12 MHz).
8·bit internal data location's address. This could be
an Internal Data RAM location (0-127) or a SFR
[i.e., I/O port, control register, status register, etc.
(128 -255) J.
@Ri
INSTRUCTIONS THAT AFFECT FLAG SETTINGS*
8-bit internal data RAM location (0 - 255) addressed
indirectly through register R 1 or RO.
Flag
Instruction
C
OV
Add
X
X
AD DC
X
X
X
X
SUBB
X
X
MUL
0
X
DIV
0
X
DA
X
RRC
X
RLC
X
SETB C
1
CLR C
0
CPL C
X
ANL C, bit
X
ORLC,bit
X
ORL C, bit
X
MOV C, bit
X
CJNE
X
AC
~
# data
8-bit constant included in instruction.
X
#data 16
16-bit constant included in instruction.
Addr. 16
16-bit destination address. Used by LCALL & LJMP.
A branch can be anywher within the 64K-byte Program
Memory address space.
Addr. 11
11 -bit destination address. Used by ACALL & AJMP.
The branch will be within the same 2K-byte page
of program memory as the first byte of the following
instruction.
Rei
* Note that operations on SFR byte address 208 or bit
Signed (two's complement) 8-bit offset byte. Used
by SJMP and all conditional jumps. Range is - 128 to
+ 127 bytes relative to first byte of the following
instruction.
addresses 209-215 (i.e., the PSW or bits in the PSW)
will also affect flag settings.
Bit
Notes on instruction set and addressing modes:
Direct Addressed bit in I nternal Data RAM or Special
Function Register.
Rn
Register
Bank.
R7 - RO
of
the
currently
selected
Register
* New operation not provided by UM8048/8049.
3-21
UM8051/UM8031
ARITHMETIC OPERATIONS
Mnemonic
Descriptions
Bytes
Cycles
ADD
A,Rn
Add register to accumulator
1
1
ADD
A, direct
Add direct byte to accumulator
2
1
ADD
A,@Ri
Add indirect RAM to accumulator
1
1
ADD
A,
Add immediate data to accumulator
2
1
ADDC
A, Rn
Add register to accumulator with carry
1
1
ADDC
A, direct
Add direct byte to accumulator with carry
2
1
ADDC
A,@Ri
Add indirect RAM to accumulator with carry
1
1
AD DC
A,
Add immediate data to Acc with carry
2
1
SUBB
A, Rn
Subtract register from Acc with borrow
1
1
SUBB
A, direct
Subtract direct byte from Acc with borrow
2
1
SUBB
A,@Ri
Subtract indirect RAM from Acc with borrow
1
1
SUBB
A,
Subtract immediate data from Ace with borrow
2
1
INC
A
Increment accu mu lator
1
1
INC
Rn
I ncrement reg ister
1
1
INC
direct
Increment direct byte
2
1
INC
@Ri
Increment indirect RAM
1
1
DEC
A
Decrement accumulator
1
1
DEC
Rn
Decrement register
1
1
DEC
direct
Decrement direct byte
2
1
DEC
@Ri
Decrement indirect RAM
1
1
INC
DPTR
Increment data pointer
1
2
MUl,..
AB
Multiply A & B
1
4
DIV
AB
Divide A by B
1
4
DA
A
Decimal adjust accumulator
1
1
#
#
#
data
data
data
3-22
UMBOS 1 / UMS031
LOGICAL OPERATIONS
Mnemonic
Descriptions
Bytes
Cycles
ANL
R, Rn
AND register accumulator
1
1
ANL
A, direct
AND direct byte to accumulator
2
1
ANL
A,@Ri
AND indirect RAM to accumulator
1
1
ANL
A,
AND immediate data to accumulator
2
1
ANL
direct, A
AND accumulator to direct byte
2
1
ANL
direct,
AND immediate data to direct byte
3
2
ORL
A, Rn
OR register to accumulator
1
1
ORL
A, direct
OR direct byte to accumulator
3
1
ORL
A,@Ri
OR indirect RAM to accumulator
1
1
ORL
A,
OR immediate data to accumulator
2
1
ORL
direct, A
OR accumulator to direct byte
2
1
ORL
direct,
OR immediate data to direct byte
3
2
XRL
A,Rn
Exclusive-OR register to accumulator
1
1
XRL
A, direct
Exclusive-OR direct .byte to accumulator
2
1
XRL
A,@ Ri
Exclusive-OR indirect RAM to accumulator
1
1
XRL
A,
Exclusive-OR immediate data to accumulator
2
1
XRL
direct, A
Exclusive-OR accumulator to direct byte
2
1
XRL
direct,
Exclusive-OR immediate data to direct byte
3
2
CLR
A
Clear accumulator
1
1
CPL
A
Complement accumulator
1
1
RL
A
Rotate accumu lator left
1
1
Rotate accumulator left through the carry
1
1
1
1
1
1
1
1
RLC
_A
#
#
#
data
#
data
data
#
data
data
#
data
RR
A
Rotate accumulator right
RRC
A
Rotate accumulator right through the carry
,
SWAP
A
Swap nibbles within the accumulator
3-23
I
UM8051!UM8031
DATA TRANSFER
Mnemonic
Descriptions
Bytes
Cycles
MOV
A,Rn
Move register to accumulator
1
1
MOV
A. direct
Move direct byte to accu mu lator
2
1
MOV
A,@Ri
Move indirect RAM to accumulator
1
1
MOV
A
Move immediate data to accumulator
2
1
MOV
Rn,A
Move accumulator to register
1
1
MOV
Rn, direct
Move direct byte to reg ister
2
2
MOV
Rn,
#
Move direct byte to reg ister
2
1
MOV
direct, A
Move accu mu lator to direct byte
2
1
MOV
direct, Rn
Move register to direct byte
2
2
MOV
direct, direct
Move direct byte to direct
3
2
MOV
direct, @ Ri
Move indirect RAM to direct byte
2
2
MOV
direct,
Move immediate data to direct byte
3
2
MOV
@Ri,A
Move accumulator to indirect RAM
1
1
MOV
@ Ri, direct
Move direct byte to indirect RAM
2
2
MOV
@ Ri,
Move immediate data to indirect RAM
2
1
MOV
DPTR,
Load data pointer with a 16-bit ~onstant
3
2
MOVC
A,@A+DPTR
Move code byte relative to DPTR to Acc
1
2
MOVC A,@A+PC
Move code byte relative to PC and Acc
1
2
MOVX A,@Ri
Move external RAM (8-bit addr) to Acc
1
2
MOVX A. @ DPTR
Move external RAM (16-bit addr) to Acc
1
2
MOVX @Ri,A
Move Acc to external RAM (8-bit addr.)
1
2
MOVX @DPTR, A
Move Acc to external RAM (16-bit addr.)
1
2
PUSH
direct
Push direct byte onto stack
2
2
POP
direct
p.op direct byte from stack
2
2
XCH·
A. Rn
Exchange register with accumulator
1
1
XCH
A, direct
Exchange direct byte with accumulator
2
1
XCH
A,@Ri
Exchange indirect RAM with accumulator
1
1
XCHD
A.@Ri
Exchange low-order digit indirect RAM with Acc
1
1
#
data
direct
#
#
data
data
#
data 16
3-24
UMBOS 1 / UMB031
BOOLEAN VARIABLE MANIPULATION
Mnemonic
Descriptions
Bytes
Cycles
CLR
C
Clear carry
1
1
CLR
bit
Clear direct bit
2
1
SETB
C
Set carry
1
1
SETB
bit
Set direct bit
2
1
CPL
C
Complement carry
1
1
CPL
bit
Complement direct bit
2
1
ANL
C, bit
AN D direct b it to carry
2
2
ANL
C,/bit
AND complement of direct bit to carry
2
2
ORL
C, bit
OR direct b it to carry
2
2
ORL
C,/bit
OR complement of direct bit to carry
2
2
MOV
C, bit
Move direct b it to carry
2
2
MOV
bit, C
Move carry to direct bit
2
2
JC
rei
Jump if carry is set
2
2
JNC
rei
Jump if carry not set
2
2
JB
bit, rei
Jump if direct bit is set
3
2
JNB
bit, rei
Jump if direct but is not set
3
2
JBC
bit, rei
Jump if direct bit is set & clear bit
3
2
3-25
I
UM80S1 / UM803'1
PROGRAMING BRANCHING
Mnemonic
Descriptions
Bytes
Cycles
ACALL addr. 11
Absolute subroutine call
2
2
LCALL addr. 16
Long subroutine call
3
2
RET
Return for subrout.ine
1
2
RETI
Return for interrupt
1
2
AJMP
addr. 11
Absolute jump
2
2
LIMP
addr. 16
Long jump
3
2
SJMP,
rei
Short jump (relative addr.)
2
2
JMP
@A+DPTR
Jump indirect relative to the DPTR
1
2
JZ
rei
Jump if accumulator is zero
2
2
JNZ
rei
Jump if accumulator is not zero
2
2
CJNE
A, direct, rei
Compare direct byte to Acc and jump if not egual
3
2
CJNE
A,
Compare immediate to Acc and jump if not equal
3
2
CJNE
Rn,
Compare immediateto register and jump if not equal
3
2
CJNE
@ Ri,
Compare immediate to indirect and jump if not equal
3
2
DJNZ
Rn, rei
Decrement register and jump if not zero
3
2
DJNZ
direct, rei
Decrement direct byte and jump if not zero
3
2
No operation
1
1
NOP
#
data, rei
#
data, rei
#
data, rei
"-
3-26
Microprocessor
Selection Guide
Part No.
Descriptions
Compatible Devices
UM6502
8 Bit CPU
Syp 6502
1,2,3,4 MHz Version
4-3
UM6507
8 Bit CPU
Syp 6507
1, 2 MHz Version
4-3
UM6512
8 Bit CPU
SYP 6512
1, 2, 3 MHz Version
4-3
4-2
Remarks
Page
EDUMC
UM6502/UM6507/UM6512
=====;::~==::=;i:: 8-Bit
Microprocessors
Features
•
•
•
•
•
•
•
•
•
•
•
Single 5V ± 5% power supply
N channel, silicon gate, depletion load technology
56 instructions
Decimal and binary arithmetic
Thirteen addressing modes
True indexing capability
Programmable stack pointer
Variable length stack
Interrupt capability
Non-maskable interrupt
Bi-directional data bus
•
•
•
•
•
•
•
Addressable memory range of up to 64K bytes
"Ready" input
Direct memory access capabilitv
Bus compatible with MC6800
Choice of external or on-board clocks
1 MHz, 2MHz, 3MHz and 4MHl versions
On-chip clock options
-External single clock input
-Crystal time base input
• Pipeline architecture
General Description
phase inputs or crystals provide the time base. The
UM6512 external clock version is geared for the multiprocessor system applications where maximum timing
control is mandatory. These products are bus compatible
with the MC6800 product offering.
The UM6502/UM6507/UM6512 microprocessors are totally
software compatible with one another. These products
provide a selection of addressable memory range, interrupt
input options and on-chip clock oscillators and drivers.
The UM6502/UM6507 on-chip clock versions are aimed
at high performance, low cost applications where single
Pin Configuration
Vss
ROY
CPl
(OUT)
TAO
N.
c.
CP2
if>o
RES
if>2 (OUT)
RES
S. O.
if>o (IN)
ROY
Riw
Vcc
DBO
N. c.
NMT
N. c.
SYNC
R/IN
DBO
Vcc
ABO
ABl
DBl
DB2
AB2
DB3
Vss
(OUT)
(IN)
ABO
DBl
ABl
DB2
AB2
DB3
AB3
DB4
AB4
DB5
Vss
ROY
if> 1
RES
if>2
(OUT)
S.O.
IRQ
if>2
Vss
DBE
NMT
N. C.
SYNC
R/W
DBO
Vcc
ABO
DBl
ABl
AB2
DB2
DB3
AB3
DB4
AB5
DB6
AB3
DB4
AB4
DB5
AB6
DB7
AB4
DB5
AB5
DB6
AB7
AB12
AB5
DB6
AB6
AB7
DB7
AB8
ABll
AB15
AB14
AB9
AB10
AB6
AB7
AB8
AB9
AB8
AB13
DB7
AB15
AB14
AB12
AB9
AB10
AB13
AB10
ABll
Vss
ABll
Vss
4-3
AB12
UM65 02 / UM65 0 7 / UM6512
*Comments
Absolute Maximum Ratings*
Supply Voltage VCC ..
-0.3 to +7 .OV
Input Voltage VIN
-0.3 to + 7 .OV
.....
Operating Temperature T A .
... 0 to 70
Storage Temperature T STG .
... -55 to + 150
0
0
e
e
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Fu·nctional operation of this
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Block Diagram
_ - - - - REGISTER SECTION
CONTROL SECTION - - - - -_
ABO
AB1
AB2
t - - - - - : - - - ROY
AB3
AB4
AB5
AB6
INSTRUCTION
DECODE
AB7
ADDRESS
BUS
I
0
«
-'
«
z
AB8
AB9
-'
0
«
~
1
I~
AB10
1UN1
2 applies to UM6512, 4>0 (in) applies to UM6502/UM6507)
Symbol
VIH
Characteristics
Logic and 4>0 (in) for
{ 1,2,3 MHz
}
4>1 and 4>2 only for
4 MHz
}
UM6512
IlL
Units
+ 2.0
Vee
V
+ 3.3
Vee
V
All Speeds
Vee - 0.5/
Vee + 0.25
V
Input Low Voltage
Logic,4>o(in)
(UM6502/UM6507)
-0.3
+0.. 8
4>1,4>2
(UM6512)
-0.3
+0.2
V
-10
~300
J1A
Input Loading
(VIN
= OV,
Vee
= 5.25V)
ROY, S.O.
liN
Max.
Input High Voltage
U M6502/U M6507
VIL
Min.
I nput Leakage Current
(VIN = 0 to 5.25V, Vee = 0)
Logic (Exel. ROY, S.O.)
ITSI
-
2.5
J1A
4>1,4>2
(UM6512)
-
100
J1A
4>o(jn)
(UM6502/UM6507)
-
10.0
J1A
-
±1O
J1A
1,2 MHz
2.4
-
V
1,2 MHz
-
0.4
V
-
700
mW
-
10
Three-State (Off State) Input·Current
(VIN = 0.4 to 2.4V, Vee
= 5.25V)
DBO-DB7
VO H
Output High Voltage
(ILoAD
= -100J1Adc,
Vee
= 4.75V)
SYNC, DBO-DB7, AO-A15, R/W
VOL
Output Low Voltage
(ILOAD
= 1.6mAdc,
Vee = 4.75V)
SYNC, DBO-DB7, AO-A15, R/W
PD
1 MHz and 2MHz
Power Dissipation.
(Vee = 5.25 V)
C
Capacitance
(VIN
CIN
COUT
= 0,
RES,
TA
= 25°C,
NMT,
ROY,
f = 1 MHz)
TAO,
S.O., DBE
DBO-DB7
-
15
AO-A 15, R/W, SYNC
-
12
15
4>0 (in)
(UM6502/UM6507)
-
C4>1
4>1
(UM6512)
-
50
C4>2
4>2
(UM6512)
-
80
C4>o (in)
4-5
pF
SUMC
U M6502/U M6507
UM6502/UM6507/UM6512
~-----------TCYC -------------~
- - - - - - - 1 ' - - - - THct>o
CLOCKS
----~
cf>o (IN)
ct>l (OUT)
14---_ _ T PWH02
ct>2 (OUT)
TO
T02+
R/W
ADDR
14---------j-
TACC
-----l------r-r
DATA
(READ)
REF "A"
REF "8"
TMDS ' -_ _ _ _ _ _ _ _;-~
DATA
(WRITE)
_ _ _ TSYS
SYNC
REF
ROY
UM6512
CLOCKS
ct>l (IN)
cf>2 (IN)
4-6
"c"
eUMC
UM6502/UM6507/UM6512
Dynamic Operating Characteristics
(Vcc
= 5.0 ± 5%,
TA
= 0° to
70°C)
1 MHz
Parameter
3MHz
2MHz
4MHz
Symbol
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
0.25
40
UM6512
TCYC
1.00
40
0.50
40
0.33 .
40
<1>1 Pulse Width
TPWH I
430
-
215
-
150
-
ns
<1>2 Pulse With
TPWH2
470
-
235
-
160
-
ns
Cycle Time
J..IS
TD
0
-
0
-
0
-
ns
TR. TF
0
25
0
20
0
15
ns
Cycle Time
TCYC
1.00
40
0.50
40
0.33
40
0.25
40
J..IS
<1>0 (I N) Low Time(2)
Tut>o
480
-
240
-
160
-
110
-
ns
<1>0 (I N) High Time(2)
THcPo
460
-
240
-
160
-
115
-
ns
<1>0 Neg to' 1 Pos Delay (5)
T01+
10
70
10
70
10
70
10
70
ns
cPo Neg to <1>2
ns
Delay Between <1>1 and <1>2
<1>1 and <1>2 Rise and Fall Times(l)
UM6502/UM6507
Neg Delay(5)
T02-
5
65
5
65
5
65
5
65
<1>0 Pos to cPl Neg Delay(5)
T01-
5
65
5
65
5
65
5
65
ns
<1>0 Pos to cP2 Pos Delay(5)
T02+
15
75
15
75
15
75
15
75
ns
. ¢O(IN) Rise and Fall Time(l)
30
0
20
0
15
0
10
ns
TRO,TFO
0
<1>1 (OUT), Pulse Width
TpWH1
TLcPo·20
<1>2 (OUT). Pulse Width
TPWH2
Delay Between cP 1 and <1>2
<1>1 and <1>2 Rise and Fall Times(l, 3)
TLo TLo·20
TLo
TLo·20 TLo TL¢o·20
TLo
TLcPo· 40 TLo·10 TLo·40 TLo·40 TLcPo AO TLcPo· 10 TLo·40 TLo·10
5
5
5
5
-
TO
TR, TF
-
25
-
25
-
15
ns
ns
ns
-
15
ns
U M6502/U M6507 /U M6512
R/W Setup Time
TRWS
-
225
-
140
-
110
-
90
ns
R/W Hold Time
TRWH
30
-
30
-
15
-
10
-
ns
Address Setup Time
TADS
-
225
-
140
-
110
-
90
ns
Address Hold Time
TADH
30
-
30
-
15
-
10
-
ns
Read Access Time
TACC
-
650
-
310
-
170
-
110
ns
Read Data Setup Time
TDSU
100
-
50
-
50
-
50
-
ns
Read Data Hold Time
THR
10
-
10
-
10
-
10
-
ns
Write Data Setup Time
TMDS
20
175
20
100
20
75
-
70
ns
Write Data Hold Time
THW
60
150
60
150
30
130
20
-
ns
Sync Setup Time
TSYS
-
350
-
175
-
100
-
90
ns
Sync Hold Time
TSYH
30
-
30
-
15
-
15
-
ns
TRS
200
-
200
-
150
-
120
-
ns
RDY Setup Time(4)
Notes:
Timing Diagram Note:
1. Measured between 10010 and 90% points.
Because the clock generation for the UM6502/UM6507
2. Measured at 50% points.
and UM6512 is different. the two clock timing sections are
3. Load = 1 TTL load + 30 pF.
referenced to the main timing diagram by three reference
4. R DY must never switch states with in T RS to end of <1>2'
lines marked REF 'A', REF 'B' and REF 'C'.
5. Load = 100 pF.
6. The 2 MHz devices are identified by an "A" suffix.
Timing parameters are referred to these lines and scale
7. The 3 MHz devices are identified by an "B" suffix.
8. The 4 MHz devices are identified by an
Reference
between the two sets of clock timings is without meaning.
variations in the diagrams are of no consequence.
'·'c" suffix.
4-7
(IlUMC
UM65 02 / UM65 0 7/ UM6512
Pin Description
Non-Maskable Interr",pt(NMI)
Clocks (rJ> 1 , rJ>2 )
A negative going transition on this input requests that
a non-maskable interrupt sequence be generated within
the microprocessor.
The UM6512 requires.a two phase non-overlapping clock
that runs at the Vee voltage level.
NM I is an unconditiohal interrupt. Following completion of the current instruction, the sequence of operations
defined for IRQ will be performed, regardless of the state
interrupt mask, flag. The vector address loaded into the
program counter, low and high, are locations FFFA and
F F F B respectively, thereby transferring program control
to 'the memory vector located at these addresses.
The
instructions loaded at these locations cause the microprocessor to branch, to a non -maskable interrupt routine
in memory.
The UM6502!UM6507 clocks are supplie(j with an internal
clock generator.
The frequency of these clocks is externally controlled; Clock generator circuits are shown
elsewhere in th is data sheet.
Address Bus (Ao-A 15 )
(See sections on each micro for respective address lines
on those devices.)
These outputs are TTL compatible, capable of driving
one standard TTL load and 130 pF.
Data Bus
NMI also requires an external 3KQ resistor to Vee for
proper wire-OR operations.
(DBo~DB7)
Eight pins are used for the data bus. This is a bidirectional bus, transferring data to and from the device and
peripherals. The outputs are three-state buffers, capable
of driving one standard TTL load and 130 pF.
I nputs TAO and 1'JKiIT are hardware interrupts lines that
are sampled during 2 (Phase 2) and will begin the appropriate interrupt routine on "the 1 (phase 1) following
the completion of the current instruction.
Data Bus Enable (DBE)
Set Overflow Flag (S. 0.)
This TTL compatible input allows external control of the
three-state data output buffers and will enable the microprocessor bus driver when in the high state. In normal
operation DBE would be driven by the phase two (rJ>2)
clock, thus allowing data output from microprocessor only
during rJ>2. Du ring the read cycle, the data bus d rivers are
internally disabled, becoming essentially an open circuit.
To disable data bus drivers externally, DBE should be held
low. This signal is available on the UM6512 only.
A NEGATIVE going edge on this input sets the overflow
bit in the Status Code Register. This signal is sampled
on the trailing edge of 1'
SYNC
This output line is provided to identify those cycles in
which the microprocessor is doing an OP CODE fetch. The
SYNC line goes high during rJ>1 of an OPCODE fetch and
stays high for the remainder of that cycle. lithe ROY line
is pulled loIN during the 1 clock pulse in which SYNC
went high, the processor wilL stop in its current state and
will remain in the state until the ROY line goes high." In
this manner, the SYNC signal can be used to control ROY
to cause single instruction execution.
Ready (ROY)
This input signal allows the user to halt the miCroproCeSsor
on all cycles except write cycles. A negative transition to
the low state during or coincident with phase one, (rJ>1) will
halt the microprocessor with the output address lines reflecting the current address being fetched. This condition will
remain through a subsequent phase two (2) in which the
Ready signal is low. This feature allows microprocessor
interfacing with low speed PROMS as well as fast (max. 2
cycle) Direct Memory Access (DMA). If ready is low during a
write cycle, it is ignored until the following read operation.
Ready transitions must not be permitted during 2 time;
Reset (RES)
This input is used to reset or start the microprocessor
from a power down condition. During the time that this
line is held low, writing to or from the microprocessor
is inh ibited. When a positive edge is detected on the
input, the microprocessor will immediately begin the
reset sequence.
After a system initialization time of six clock cycles, the
mask interrupt flag will be set and the microprocessor
will load the program counter from the memory vector
locations FfFC and FFFD. This is the start locationfor
program control.
Interrupt Request (IRQ)
This TTL level input requests that an interrupt sequence
begin within the microprocessor. The microprocessor will.
complete the current instruction being executed before
recognizingOthe request. At the time, the interrupt mask bit
in the Status Code Register will be examined. If the interrupt mask flag is not set, the microprocessor will begin an
interrupt sequence. The Program Counter and Processor
Status Register are. stored in the stacK. The microprocessor
will then set the interrupt mask flag high so that no futher
interrupts may occur. At the end of this cycle, the program
counter low will be loaded from address FFFE, and program counter high from location FFFF, therefore trans. ferring program control to the memory vector located at
these addresses., The ROY signal must be in the high state
for any interrupt to be recognized. A 3KQ external resistor
should be used for proper wire-OR operation.
After Vee reaches 4.75 volts in a power up routine, reset
must be held low for at least two clock cycles. At this
time the R!Wand SYNC signal will become valid. When
the reset signal goes high following these two clock cycles,
the microprocessor will proceed with" the normal reset
procedure detailed above.
Read/Write (R/W)
This output signal is used to control the direction of data
transfers between the processor and other circuits on the
data bus. A high level on R/W signifies data .into the processor; a tow is for .the data transfer out of the processor.
4-8
UM6502/UM6507/UM6512
Programming Characteristics
INSTRUCTION SET - ALPHABETIC SEQUENCE
ADC
AND
ASL
Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift left One Bit (Memory or Accumulator)
BCC
BCS
BEQ
BIT
BM I
BN E
BPL
BN K
BVC;:
BVS
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Resu It Minus
Branch on Resu it not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set
CLC
CLD
CLI
CLV
CMP
CPX
CPY
Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear Overflow Flag
Compare Memory and Accumulator
Compare Memory and Index X
Compwe Memory and Index Y
DEC
DEX
DEY
Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One
EOR
"Exclusive-or" Memory with Accumulator
I NC
INX
INY
Increment Memory by One
I ncrement I ndex X by One
Increment Index Y by One
JMP
JSR
Jump to New Location
Jump to New Location Saving Return Address
LDA
LDX
LDY
LSR
Load
Load
Load
Shift
NOP
No Operation
ORA
"OR" Memory with Accumulator
PHA
PHP
PLA
PLP
Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack
ROL
Rotate
lator)
Rotate
Return
Return
ROR
RTI
RTS
Accumulator with Memory
I ndex X with Memory
Index Y with Memory
One Bit Right (Mell1ory or Accull1ulator)
One Bit Left (Memory or Accull1u·
One Bit Right (Memory or Accumulator)
from Interrupt
from Subroutine
SEC
SED
SEI
STA
STX
STY
Subtract Memory from Accumulator with
Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
TAX
TAY
TSX
TXA
TXS
TYA
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
SBC
Accumulator to Index X
Accumulator to Index Y
Stack Pointer to Index X
Index X to Accumulator
I ndex X to Stack Pointer
Index Y to Accumulator
ADDRESSING MODES
Accumulator Addressing
Zero Page Addressing
This form of addressing is represented with a one byte
instruction, implying an operation on the accumulator.
The zero page instructions allow for shorter code and
execution times by only fetching the second byte of the
instruction and assuming a zero high address byte. Careful
use of the zero page can result in significant increase in
code efficiency.
Immediate Addressing
In immediate addressing, the operand is contained in the
second byte of the instruction, with no further memory
addressing required.
Indexed Zero Page Addressing - (X, Y indexing)
This form of addressing is Used in conjunction with the
index register and is referred to as "Zero Page, "X" or
"Zero Page, y.." The effective address is calculated by
adding the second byte to the contents of the index
register. Since this is a form of "Zero Page" addressing,
the content of the second byte references a location in
page zero. Additionally due to the "Zero Page" addressing
Absolute Addressing
I n absolute addressing, the second byte of the instruction
specifies the eight low order bits of the effective address
while the third byte specifies the eight high order bits.
Thus, the absolute addressing mode allows access to the
entire 65K bytes of addressable memory.
4-9
(DUMC
UM6502/UM6507/UM6512
nature of this mode, no carry is added to the high order
8 bits of memory and crossing of page boundaries does
not occur.
Indexed Indirect Addressing
In indexed indirect addressing (referred to as [Indirect,
Xl), the second byte of the instruction is added to the
contents of the X index register, discarding the carry.
The result of this addition points to a memory location
on page zero whose contents is the low order eight bits
of the effective address. The next memory location in
page zero contains the high order eight bits of the effective
address. Both memory locations specifying the high and
low order bytes of the effective address must be in page
zero.
Indexed Absolute Addressing - (X, Y indexing)
This form of addressing is used in conjunction with X
and Y index register and is referred to as "Absolute, X,"
and "Absolute, Y." The effective address is formed by
adding the contents of X or Y to the address contained
in the second and th irdbytes of the instruction. This mode
allows the index register to contain the index or count
value and the instruction to contain the base address.
This type of indexing allows any location referencing and
the index to modify mu Itiple fields resulting in reduced
coding and execution time.
Indirect Indexed Addressing
In indkect indexed addressing (referred to as [Indirectl,
Y), the second byte of the instruction points to a memory
The contents of this memory
location in page zero.
location is added to the contents of the Y index register,
the ·result being the low order eight bits of the effective
address.
The carry from this addition is added to the
contents of the next page zero memory location, the result
being the high order eight bits of the effective address.
Implied Addressing
In the implied addressing mode, the address containing
the operand is implicitly stated in the operation code
of the instruction.
Relative Addressing
Relative addressing is used only with branch instructions
and establishes a destination for the conditional branch.
Absolute Indirect
The second byte of the instruction contains the low order
eight bits of a memory location. The high order eight
bits of that memory location is contained in the third
byte of the instruction. The contents of the fully specified
memory location is the low order byte of the effective
address.
The next memory location contains the high
order byte of the effective address which is loaded into
the sixteen bits of the program counter.
The second byte of the instruction becomes the operand
which is an "Offset" added to the contents of the lower
eight bits of the program counter when the counter is set
at the next instruction. The range of the offset is-128
to + 127 bytes from the next instruction.
PROGRAMMING MODEL
7
I
A
Y
X
7
15
I
PCH
I
PROCESSOR STATUS REG "P"
A
S
I PROGRAM
J
1 = TRUE
ZERO
1 = RESULT ZERO
IRQ DISABLE
X
COUNTER "PC"
STACK POINTER
CARRY
Y
PCl
7
I
I ACCUMULATOR
I INDEX REGISTER
I INDEX REGISTER
..
DECIMAL MODE 1 = TRUE
BRK COMMAND 1 = BRK
"S"
4-10
1 = DISABLE
OVERFLOW
1 = TRUE
NEGATIVE
1 = NEG.
eUMC
UM6502/UM6507/UM6512
Clock Gener~tion Circuits*
* Crystals used are CTS Knight MP Series or equivalents. (Series Model
1- -
I
-
I
- osCiLLATOR c;C~T - (ONE TTL PACKAGE REQUIRED)
-
- I
I
I
I
0.051lF
I
I
I
I
1.5K
2.2K
2.2K
OR
DlVIDEsY2
4CIRCUIT (ONE TTL PACKAGE REQUIRED)
+5V
D
I
R
5
B
13
12
D
R Q 9
1/2
74LS74
S Q
I
I
A
Q
1/2
74LS74
>O~~-+~~C
I
5V
1
2
I
I
II
II
-
11
C
I
.
I
I
I tPo (UM6502/UM650'
I tPl (UM6512)
I
I
S Q 8
10
4
I
500pF
I
I
+5V
JUMPER "A" = 4
2 _ _ ---.J
_ _JUMPER
_ _"B"
_= _
+5V
I
L ______ _
_..L _
+
+
Output Frequency
Crystal Frequency
+2
+4
3.579545 MHz
1.7897 MHz
0.894886 MHz
4.194304 MHz
2.097152 MHz
1.048576 MHz
1.8K
1.8K
U M6502/U M6507
33K
tP2
SYSTEM
CLOCK
XTAL
UM6502/
UM6507
tP2
>O~-SYSTEM
CLOCK
.....- .....
tPo~~--~~~--~NV--~
o
+5V
4-11
tP2 (UM6512)
UM65 02 / UM6507! UM6S12
Instruction Set
Instructions
Mnemonic
C
D
L
C
S
Immediate
Operation
(4) (1)
A+M+C~A
A
A
A
B
B
D
N
S
C
C
B
B
B
B
B
E ,Q
I
T
M
I
N
E
P
L
BRANCH
AIIM
BRANCH
BRANCH
BRANCH
B
B
B
C
C
R
V
V
L
L
K
C
S
C
D
BREAK
BRANCH ONV = 0 (2)
BRANCH ON V = 1 (2)
C
C
C
C
C
L
L
M
P
P
I
V
P
X
Y
0~1
D
D
D
E
I
E
E
E
0
N
C
X
Y
R
C
M-l ~M
X-l-+X
I
I
J
J
L
N
N
M
S
D
X
Y
P
R
A
X+ 1~ X
Y+ 1 ~ Y
JUMP TO NEW LOC
JUMP SUB
(1)
M
A
L
L
L
N
0
D
D
S
0
R
X
Y
R
P
A
M-X
M-+Y
P
P
P
P
R
H
H
L
L
0
A
P
A
P
L
A-+ MS S - 1 ~ S
P -+ MS S - 1 -+ S
S + 1 -+ S MS -+ A
S + 1 -+ S MS -+ P
R
R
R
S
S
S
0
T
T
B
E
E
R
I
S
C
C
D
S
S
S
S
T
E
T
T
T
A
I
A
X
Y
X
T
T
T
T
T
A
S
X
X
Y
Y
X
A
S
A
AIIM~A
(1)
C +- cz=]] +- 0
BRANCH ON C = 0
BRANCH ON C = 1
(2)
(2)
=1
(2)
ON Z
Zeropage
Absolute
OP
n
#
OP
n
#
OP
n
#
69
29
2
2
2
2
6D
2D
OE
4
4
6
3
3
3
65
25
06
3
3
5
2
2
2
2C
4
3
24
3
2
ON N = 1 (2)
ON Z = 0 (2)
ON N = 0 (2)
Implied
Accum
OP
OA
n
2
#
'.
O~V
A-M
X-M
Y-M
C9
EO
CO
2
2
2
2
2
2
CD
EC
CC
4
4
4
3
3
3
C5
E4
C4
3
3
3
2
2
2
CE
6
3
C6
5
2
4D
EE
4
6
3
3
45
E6
3
5
2
2
(1)
(1)
O~cz:=gJ~C
(1)
NO OPERATION
AVM-+A
49
2
2
A9
2
A2
AO
2
2
09
2
3
6
4
3
3
3
A5
3
2
2, AE
2 AC
4E
4
4
6
3
3
3
A6
A4
46
3
3
5
2
2
2
OD
4
3
05
3
2
2
4A
2
~[C]]+-[g~
2E
6
3
26
5
2
2A
2
1
6E
6
3
66
5
2
6A
2
1
(1)
E9
2
2
ED
4
3
E5
3
l-+D
1 -+ 1
A~M
X~M
Y~M
1
18
D8
2
2
1
1
58
B8
2
2
1
1
80
8E
8C
4
4
4
3
3
3
85
86
84
3·
3
3
2
2
EA 2
1
48
08
68
28
3
3
4
4
1
2
1
1
40
60
6
6
1
1
38
F8
2
2
1
1
78
2
1
A-+X
AA 2
1
A~Y
A8
BA
8A
9A
98
2
2
2
2
2
1
1
1
1
1
(1) ADD 1 TO N IF PAGE BOUNDARY IS CROSSED
(2) ADD 1 TO N IF BRANCH OCCURS TO SAME PAGE
ADD 2 TO N IF BRANCH OCCURS TO DIFFERENT PAGE
(3) CARRY NOT = BORROW
(4) IF IN DECIMAL MODE Z FLAG IS INVALID
ACCUMULATOR MUST BE CHECKED FOR ZERO RESULT
4 ..... 12
Yl
#
OP
n
#
61
21
6
6
2
2
71
31
5
5
2
2
Cl
6
2
Dl
5
2
41
6
2
51
5
2
Al
6
2
Bl
5
2
01
6
2
11
5
2
El
6
2
Fl
5
2
81
6
2
91
6
2
1
1
2
2
2
S-+X
X-+.A
X-+S
Y-+A
(lind.
n
1
1
2
l~C
Xl
OP
1
t;[IJ -+ rn=TI :::;J
RTRN INT
RTRN SUB
A-M-C-+A
7
E8
C8
4C
20
2: AD
lind.
#
00
CA 2
88 2
Y-l~Y
AVM-+A
M+ l~M
n
1
O~C
O~D
OP
UM6502/UM6507/UM6512
Z Page. X
OP
75
35
16
n
4
4
6
Abs. V
Abs. X
#
OP
2
2
2
70
3D
1E
n
4
4
7
#
OP
3
3
3
79
39
n
4
4
Relative
#
OP
n
Z Page. V
Indirect
#
OP
n
#
OP
n
Processor Status Codes
#
3
3
90
BO
7
2
2
2
FO
2
2
7
6
N
V
N
N
N
V
2
2
2
2
2
2
50
70
2
2
2
2
4
3
2
1
0
B
0
I
Z
C
Z
Z
Z
C
Mnemonic
M7
30
DO
10
5
Z
M6
1
1
6
ci
05
4
2
DO
4
3
06
6
2
DE
7
3
55
F6
4
6
2
2
50
FE
4
7
3
3
09
59
4
4
3
6C
B5
4
2
BD
4
3
B4
56
4
6
2
2
BC
5E
4
7
3
3
15
4
2
10
4
3
B9
4
3
BE
4
3
19
4
5
0
6
N
3
C
Z
C
C
C
4
2
3
N
Z
N
N
0
Z
Z
Z
N
Z
N
. Z
N
76
6
2
7E
7
3
N
"
....
V
N
3
C
2
90
3
5
99
5
C
Z
C
Z
(3)
1
3
96
94
2
4
X
Y
A
M
Ms
4
+
INDEX X
INDEX Y
ACCU MU LATO R
MEMORY PER EFECTIVE ADDRESS
MEMORY PER STACK POINTER
1\
V
V
ADD
SUBTRACT
AND
OR
EXCLUSIVE OR
E
E
E
N
C
X
Y
R
C
N
N
M
S
0
X
Y
P
R
A
0
0
S
X
Y
R
P
A
2
N
Z
N
N
N
Z
Z
Z
N
Z
L
L
L
N
0
1
4
I
V
P
X
Y
L
Z
;
95
L
L
M
P
P
J
J
(RESTORED)
4
C
C
C
C
C
I
I
3
F9
K
C
S
C
0
Z
Z
7
3
R
V
V
L
L
N
N
3E
4
B
B
B
C
C
0
0
0
E
I
2
FD
Q
Z
Z
Z
Z
Z
6
2
E
I
M
N
P
N
N
N
N
N
36
4
B
B
B
B
B
Z
Z
(RESTORED)
F5
C
0
L
C
S
N
N
3
B6
B
B
0
N
S
C
C
A
A
A
0
0
R
T
I
E
L
P
P
P
P
R
0
P
L
R
R
R
S
S
S
0
T
T
B
E
E
R
I
S
C
C
0
S
S
S
S
T
E
T
T
T
A
T
T
T
T
T
A
H
H
L
L
S
X
Y
Y
A
P
A
I
A
X
Y
X
Y
X
S
S
A
M7 MEMORY BIT 7
M6 MEMORY BIT 6
n
NO. CYCLES
# NO. BYTES
Ordering Information
1 MHz
2MHz
3MHz
4MHz
UM6502
UM6502A
UM6502B
UM6502C
UM6507
-
-
-
UM6512
UM6512A
UM6512B
UM6512C
Part
Number
4-13
Clocks
Pins
IRQ
UM6502
UM6507
On-Chip
UM6512
External
40
28
40
..; ..;
~
..; ..; ..;
On-Chip
NMI
RVO
Addressing
64K
8K
64K
CRT Controller
Selection Guide •
Descriptions
Part No.
Compatible Devices
UM6845/A/B
CRT Controller
HD 6845S
UM6845R
CRT Controller
UM6845E
Remarks
Page
1,1.5,2 MHz Version.
5-3
Syp 6845R
1,2,3 MHz Version
5-26
CRT Controller
Syp 6845E
1,2, 3 MHz Version
5-39
CRT Controller
SMC 9007
-
5-56
UM8321
Video Attributes Controller
SMC 9021
UM8312
Double Row Buffer
SMC 9212
*UM9007
* Under Development
5-2
30,28.5 MHz Version
-
5-57
5-71
(l)UMC
UM6845/ UM6845A/ UM6845B
CRT Controller
Features
•
•
Applications include smart, programmable, intelligent
CRT terminals; video games; information display
•
•
Alphanumeric, semi-graphic, and full graphic capa-
•
bility
•
•
Light pen registers and input strobe signal to latch the
Line buffer-less operation. No external DMA required.
Reading screen memory is mutliplexed between CRTC
density
•
Programmabfe cursor format
light pen position on screen
Fully programmable via processor data bus and can
generate timing ·for almost any alphanumeric screen
•
Provides CPU's with synchronous signals to external
device
and CPU
Single +5 volt supply, TTL compatibl-e I/O, NMOS
Technology
•
Programmable interlace or non- interlace scan
Hardware scrolling by page, line or character
•
14-bit wide display memory reading address
General Description
The CRTC UM6845 family are LSI controllers designed
CPU in both data lines and control lines.
to provide an interface for microcomputers to raster
scan type CRT displays.
The CRTC belongs to the
function is to generate timing signals which are necessary
Its primary
MC 6800 LSI
fication programmed by the .cPU.
for raster-scan type CRT displays according to the speci-
Family and has full compatibility with
Pin Configuration
VSS
VSYNC
RES
HSYNC
RAO
lPSTB
MAO
RAl
RA2
RA3
MAl
MA2
MA3
RA4
MA4
MA5
DO
Dl
MA6
MA7
D2
D3
MA8
D4
MAg
D5
D6
MAlO
D7
MAll
MA12
CS
RS
MA13
E
DISPTMG
CUDISP
R/W
ClK
VCC
5-3
UM6845/ UM6845A / UM68458
Absolute Maximum Ratings
*Comments
Supply Voltage, Vee* . . . . . . . . . . . . . . . -0.3"'+7.0V
Strees above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These
are stress. ratings only. Functional operation of this device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied
and exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Input Voltage, VIN* . . . . . . . . . . . . . . . . -0.3"'+7.0V
Operating Temperature, T OPR
. . . . . . . . . . . 0° '" 70°C
0
Storage Temperature, TSTG . . . . . . . . . . -55°"'+150 C
*With respect to VSS (SYSTEM GND)
D.C. Electrical Characteristics
Item
Supply Voltage
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Vee
-
4.75
5.0
5.25
V
VIL
-
-0.3
-
0.8
V
VIH
-
2.0
-
Vee
V
-2.5
-
2.5
J..l.A
-10
-
10
J..l.A
2.4
-
-
V
-
-
0.4
V
DO- D7
-
-
12.5
pF
Other Input
-
-
10.0
pF
-
-
10.0
pF
-
-
1000
mW
Input Voltage
VIN = 0 - 5.25V
Input Leakage Current
liN
Three-State Input
Current (Off-State)
(Except DO - D7)
VIN =OA-2.4V
ITSI
Vee = 5.25V (DO - D7)
ILO AD = 205A
(DO - D7)
Output "High" Voltage
VO H
ILOAD = -100J..l.A
(Other Outputs)
Output "Low" Voltage
VOL
I LOAD =1.6mA
VIN = 0
I nput Capacitance
CIN
TA = 25°C
F = 1.0 MHz
VIN = OV, T A= 25°C,
Output Capacitance
Power Dissipation
COUT
Po
f= 1.0MHz
T A = 25°C, Vee = 5.0V
5-4
UM6845/ UM6845A / UM68458
Block Diagram
VCC
R/iii
GND
cs
RS
E
FiESeT
DO-D7
ClK-+---------.------I~
DISPTMG
HS - - - - I - - H C E HORIZ~~6;~ SYNC
l-------------------+4--~--------_t--.,HS
ClK
VERTICAL CONTROL
~----~----------~~~~~~~;__ii_t_------_j---VS
'CUDISP
. LPSTB
CLK
RAO-RA4
MAO-MA13
5-:-5
UM6845/ UM6845A / UM6845B
A. C. Characteristics
(Vcc=5V±5%, vss=Ov, TA=-20"-'+75°C)
BUS TIMING CHARACTERISTIC
MPU READ TIMING
UM6845
Item
UM6845A
UM6845B
Symbol
Units
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Enable Cycle Time
tcyc E
1.0
-
-
0.666
-
-
0.5
-
-
J.1,S
Enable "High" Pulse Width
PWEH
0.45
-
-
0.280
-
-
0.22
-
-
J.1,S
Enable "Low" Pulse Width
PWEL
0.40
-
-
0.280
-
-
0.21
-
-
J.1,S
Enable Rise and Fall Time
tEr, tEf
-
-
25
-
-
25
-
-
25
J.1,S
tAS
140
-
-
140
-
-
70
-
-
nS
Data Delay Time
tDDR
-
-
320
-
-
200
-
-
180
nS
Data Hold Time
tH
10
-
-
10
-
-
10
-
-
nS
tAH
10
-
-
10
-
-
10
-
-
nS
-
-
460
-
-
360
-
-
250
nS
Address Set Up Time
Address Hold Time
Data Access Time
tACC
* See Fig-3
MPU WRITE TIMING
UM6845
Item
UM6845A
UM6845B
Symbol
Units
Min.
Typ.
Max.
,
Min.
Typ.
Max.
Min.
Typ.
Max.
"
Enable Cycle Time
tcyc E
1.0
-
-
0.666
-
-
0.5
-
-
J.1,S
Enable "High" Pulse Width
PWEH
0.45
-
~
0.280
-
-
0.22
-
-
J.1,S
Enable "Low" Pulse Width
PWEL
0.40
-
-
0.280
-
-
0.21
-
-
J.1,S
Enable Rise and Fall Time
tEr, tEf
-
-
25
-
-
25
-
-
25
nS
tAS
140
-
-
140
-
-
70
-
-
nS
tDSW
195
-
-
80
-
-
60
-
-
nS
tH
10
-
-
10
-
-
10
-
-
nS
tAH
10
-
-
10
-
-
10
-
-
nS
Address Set Up Time
Data Set Up Time
Data Hold Time
Address Hold Time
* See Fig-4
UM6845 / UM6845A / UM68458
f+---------tcyc E
2.0V
O.8V
E
CS
Riw, RS
1 4 - - - - tACC ---~
Figure 3. Read Sequence
1 4 - - - - - - - - tcYC E
PWEH
2.0V
O.8V
E
CS
p/W
RS (Address Register)
RS (Control
Register)
DO-1?>7
Figure 4. Write Sequence
CRTC SIGNAL TIMING
Symbol
Min.
Typ.
Max.
Unit
Clock Cycle Time
tcyc C
270
-
-
nS
Clock "High" Pulse Width
PWCH
130
-
-
nS
Clock "Low" Pulse Width
PWCL
130
-
-
nS
Rise and Fall Time for Clock Input
tCr, tCf
-
-
20
nS
Memory Address Delay Time
Item
tMAD
-
-
160
nS
Raster Address Delay Time
tRAD
-
-
160
nS
DiSPTMG Delay Time
tDTD
-
-
250
nS
CUDISP Delay Time
tCDD
-
-
250
nS
-
200
nS
-
250
nS
60
-
-
nS
Horizontal Sync Delay Time
tHSD
-
Vertical Sync Delay Time
tVSD
-
Light Pen Strobe Pulse Width
PWLPH
Light Pen Strobe
tLPD1
-
-
70
nS
tLPD2
-
-
0
nS
Uncertain Time of Acceptance
* See Fig. 5; Fig. 6
5-7
I
UM6845/ UM6845A / UM6845B
1 4 - - - - - - - - - tcyc C
O.8V
CLK
PWCH
MAO-MA13
RAO-RA4
2.4V
DISPTMG
2.4V
CUDISP
2.4V
HSYNC
VSYNC
LPSTB
_______--'k'.DV
2.0V~,,------------
PWLPH
The Figure shows the relation in time between
CLK signal and each output signal. Output
sequence is shown in Appl ication Notes.
Figure 5. CRTC Timing Chart
CLK
MAO-MAl 3
M+2
M+l
M
\_--
LPSTB
6
)
2.0V
LPSTB
tLPD1, tlPD2:
LPSTB's uncertain
time of acceptance.
When LPSTB rises in this period. Display Memory
Address "M+2" is set into the light pen register.
Figure 6. LPSTB Input Timing & Display Memory Address is Set I.nto the Light Pen Register.
5-8
UM6845/ UM6845A / UM68458
Typical Crt Controller Application Block Diagram
~----~--------~~------------~----------------------- AB
- - - - - - - - - - - - - - - - - - - - - - - - - . - - - - - - DB Primary Bus
CURSOR
DISPLAY
ENABLE
ROW ADDRESSES
5
HS VS
Figure 7. Typical CRT Controller Application
CRT Screen Format and Time Chart
REGISTERS PR.OGRAMMED VALUE
Register
Register Name
RO
Horizontal Total
Rl
Horizontal Displayed
R2
Horizontal Sync Position
R3
Sync Width
Specified Value
Programmed (Written) Value
Nht+l
Nht
Nhd
Nhd
Nhsp+ 1
Nhsp
N vsw , Nhsw
N vsw , Nhsw
R4
Vertical Total
Nvt+l
Nvt
R5
Vertical Total Adjust
Nadj
Nadj
R6
Vertical Displayed
Nvd
Nvd
Nvsp + 1
Nvsp
Nr+l/Nr+2
Nr
R7
Vertical Sync Position
R8
Interlace & Skew
R9
Max. Raster Address
Rl0
Cu rsor Start Raster
NCSTART
Rll
Cursor End Raster
NCEND
R12
Start Address (H)
0
R13
Start Address (L)
0
R14
Cursor (H)
R15
Cursor (L)
R16
Light Pen (H)
R17
Light Pen L (L)
5-9
I
UM6845/ UM6845A / UM6845B
SCREEN FORMAT
Number of Horizontal Total Char, (Nht + 1)
m{
....:
co
u
(/)
>
~
"D
E
...:
ro
]0
+-'
..c
U
ro
0
fro
,~
+-'
Q5
>
Y-
0
Q5
.D
E
::l
Z
OJ
>-
co
i=A=
:=
B= t=C
::l
E
x
ro
~
cou
'';:;
(jj
>
0
tD
..Q
t:
Display
:J
z
L
L
Vertical Retrace Period
Total Scan Line
Adjust (Nadj)
RESTRICTION ON PROGRAMMING INTERNAL REGISTER
(1)
a < Nhd < Nht + 1 ~ 256
(2)
a < Nvd < Nvt + 1 ~ 128
(3)
a ~ Nhsp ~ Nht
(4)
a ~ Nvsp ~ Nvt
"I
·1
}
c
ro
..c
U
+
Number of Horizontal Displayed Char, (Nhd)
(5) O~NCSTART~NCEND~Nr (Non-Interlace, Interlace Sync Mode)
a ~ NCSTART ~ NCEND ~ N r + 1 (Interlace Sync & Video Mode)
(6) 2 ~ N r ~30
(7) 3 ~ Nht (Except Non-Interlace Mode)
5 ~ Nht (Non-I nterlace Mode Only)
5-10
Line
UM6845 / UM6845A / UM68458
CRTe ADDRESSING FOR READING DISPLAY MEMORY
HORIZONTAL RETRACE INON·DISPLAY!
°
N vd· 1 {
~
°
NVd{
INvd-1IxNhd+Nht
INvd-l!~Nhd+l
I
I
I
I
IN vd- 1! xNhd
INvd-l!xNhd+l
Nvd xN hd- 1
NvdxNhd
INvd-1IxNhd+Nht
(NVdrNhd
NVdXihd+l
INvd+l!xNhd-l
(Nvd+',lxNhd
NvdxNhd+Nht
NvdxNhd
NvdX Nhd+ 1
INvd+l!xNhd-t
INvt +1IxNhd
NvdxNhd+Nht
NvtxNhd
NvtX~hd+l
IN vt + 11 ;Nhd-1
(Nvt+\ixNhd
Nvt x Nhd + Nht
I
I
I
I
I
I
NVdX1Nhd
:
I
Nr
>=
Nvd xN hd- 1
INvd-l,1xNhd
I
I
I
Nr
9z
~
w
u
~
Nr
...J
;:;
~>
°
Nvt{
I
NvtxNhd
NvtxNhd+l
INvt+l!xNhd-l
IN vt+ lIxNhd
NvtxNhd+Nht
INvt+li!XNhd
INvt +1If N hd+ t
IN vt+ 2 ! Nhd- 1
INvt+2i!XNhd
INvt+l!Xihd+Nht
INvt+lIxNhd
INvt+l!xNhd+l
INvt+2!xNhd-l
IN vt+ 2! xN hd
(Nvt+ 1) X Nhd+ Nht
r
Nvt+ 1 {
}
Figure 9. Display Memory Addressing (MAO-MA13) Stage Chart
Note: The initial MA is determined by the contents of state address register, R12/R13. Timing is shown for R12/R13 == O.
Only Non-' nterlace-and 'nterlace Sync Modes are shown.
CRTC HORIZONTAL TIMING
HORIZONTAL TOTAL IRO! tSL = INht + 11 x te
HORIZONTAL DISPLAY IRlI Nhd x te
"'"
HORIZONTAL RETRACE
nK~~~~~
I
1
1
I
:~INhd-lINhdl
MAO·MA13,
I
:
I~I
I
1
1
1
1
I
1°1
I
I
,
CHARACTER,
I
:
2
1
1:
I
I
~I
:
I
I
I
1
1
I"
I
1
. 1
I
:
I:
1 Nhd- 1 I Nhd I
~I
I
1
HSYNC ,
DISPEN
°
1
1
I
1
I
1~INhSP-l
I~:
1
I
I :
I Nhsp- 1
I~I'
ISYN~ELAY!
.. I
I
I
:~
I :
I
I
I
I
INht
Nht
I.
----.l
BACK
P.~ORRCCHIISCAN
-~
I
1
I
I
I~
~
l
:
I
I
I'~
'HS PULSE WIDTH IR3!
:.
I
I ...... ~_I
~ Nhsw X te
~r----IoI-------. ~
1
I
I
1
I~I
HORIZONTAL SYNC POSITION IR2!
FRONT PORCH
I
I
1
DELAY!
I
"-r--i&.______~~-----. . . .~~---. .
Figure 10. CRTC Horizontal Timing
5-11
I
UM6845/ UM6845A / UM68458
CRTC VERTICAL TIMING
'F = I N vI + 1) x tre + Nadj x lsi
FIELD TIME VERTICAL TOTAL IR4) + VERTICAL TOTAL ADJUST IR5)
RAO-RA4
I
)
VERTICAL DISPLAY = Nvd x Ire IRS)
Ire
--t
IS INTERFACE
SYNC AND
~:
VIDEO MODE
ODD FIELD
10 (1) ,
:
10
(1)
Nr
I
INvd-1)xNhd IIN r -l) I
~
MAO-MA13**
CHARACTER
ROW
(J6~-~NTERFACE)
: 0 Nht:
1
:
I
,
'I
'I
I
0
:
0
Nhll
,
I
VSYNC
IEVEN FIELD)
VSYNC
10DD FIELD)
' 0
I
I
Nr
0
~
j4- Tadl = Nad) x lsi
I
,
I
ADDRESS CONTINUES TO INCREMENT
FIELD ADJUST TIME I
I
....
~~,~--~--------~-----~,~~~------------~------------~
I
.......r ......------------...--~~~--~
Nvsp - 1
VERTICAL
I2
~
N vsp
'16 x lsi
,
N vt + 1
NVI
~
: : SYNC DELAY I
I
,..1'0~___
LI__.......
~
V.;;.E;.;.RT;.;.I,;;,;CA_L_S...;C_A...;N_D_E_LA_Y________.....
!
I
VERTICAL
!.- SYNC --+-'
I
:P~SITION(R7)~
'
__________________________~
",..;.1---------+---.....;-.01~
~
:
:
I
,
I
I
,
:
1
i
I
I
.... ___ :
I
'I
s
I ..
2
~I'
I
I
I
I
I
DISPLAY
ENABLE
Nr
IN r -1)
.......
: Nvd- 1
I
I
I
I
_.
VzzJ//;///lfzWlaZVfT///]lZZz7mavvzv_Z1///J/i;j)//~
~Nvd-1)XNhd+Nht
.
I
, .....: I
I
:
VERTICAL RETRACE
~
~~:~:--~~~--~--ll~)~~~:~:--~~~~I--~I1)~:~--~IO--Il~/~
I Nr
I
IN r -1) ,
I
.. ,_
------.I
I
:
--J
'--
I
14- l sl
:~
2
~r---------------------~
. I
~~~~~I
~ ~ ~ ~ ~---------~---------------~
Figure 11. CRTC Vertical Timing
Notes: 1. The odd-field is offset Yz horizontal scan time.
2. Vertical sync pulse may be programmed from 1 to 16 scan line times.
CURSOR DISPLAY TIMING
~:~'------------------------~-------------~-----------~----------~~~------------11i
RAO-RA4 I
I
MAO-MA13
-I-____
i - l_ _ _ _
I
CHARACTER ROW
I
:
Nhd
~~---~---~---~---~~~---~---~---TI---~~
..I:I--_-..ii~~
I
i
~
I
~
I
I Nhd+ 1 INhd+2:
I :
I
I !
I
I
Nhd+
Nht
Nhd
;Nhd+ 1 lN ghd+ 2 1
I
Nhd+
I
I
Nht
Nhd: Nhd+ 1 I
I
I
I
I
I
Nht
I
I
I
I
CHARACTER
,I
I
:::::
I
I
Nht
r---, __________________
,
r---,
CURSOR
I
~
Figure 12. Cursor Timing
Notes: 1. Timing is shown for non-interlace and interlace modes.
2. Cursor Register = Nhd
+ 2.
3. Cursor start = 1.
4. Cursor End = 3.
a for start address registers.
5-12
I
,
I
,
I
I
I
,
~--+---~~--~~
~~----~--~----~:----~~
Nht
I
5. R 12/R 13 =
I Nhd+
I
,
I
~r----1~
_________
UM6845 / UM6845A / UM68458
Example of Raster Scan Display
Fig. 13 shows an example where the same character is
and video mode.
displayed in the non-interlace mode, interlace sync mode,
SCAN LINE ADDRESS
SCAN LINE ADDRESS.
0--------------0
o
0
-9------G--1
0
0
-e------G--2
0
0
--9- - - - --€>- 3
00000
- 0- -6 -£)-0- G - 4
0
0
--6-----G-- 5
0
0
--9- - - - - -e- 6
0
0
-e-- - - -G--- 7
2
3
4
5
6
7
ODD
FIELD
EVEN
FIELD
(bl INTERLACE SYNC
(al NON-INTERLACE
- -e - - - -
0
o2 -04
0
- - 0
0
-£)- 1
0
--€)-3
0
0
}
LINE
:fro
-0-------6-5
6 0
0
-<3------e-7
~== ==~~~=: }UNE #1
--------7
EVEN
FIELD
ODD
FIELD
(Cl INTERLACE SYNC AND VIDEO
Figure 13. I nterlace Control
Interface to Display Control Unit
14 max
MA
5max
RA
>
DISPLAY
MEMORY
~
CHARACTER
GENERATOR
v
CRTC
DISPTMG
CUDISP
HSYNC
~}
D
VIDEO
CONTROL
VIDEO SIGNALS
SYNC SINGNALS
VSYNC
0
0
CLK
t
0
I
Figure 14. Interface to Display Control Unit
Fig. 14 shows the interface between the CRTC and display
control unit. Display control unit is mainly composed
of display Memory, Character Generator, and Video
Control circuit. For display memory, 14 Memory Address
lines (0 -16383) max are provided and for character generator, 5 Raster Address lines (0-31) max are provided.
For video control circuit, DISPTMG signal is used to
control the blank period of video signal. CUDISP signal
is used as video Signal to display the cursor on the CRT
5-13
screen. Moreover, HSYNC and VSYNC signals are used
as drive signals respectively for CRT horizontal and vertical
deflection circuits.
Outputs from video control circuit, (video signals and sync
signals) are provided to CRT display unit to control the
deflection and brightness of CRT, thus characters are
displayed on the screen.
SUMC
UM6845/ UM6845A / UM68458
Circuitry Standard of Display Control Unit
Fig. 15.
shows
the
detailed
display control unit.
block
diagram
of
the
When many characters are displayed in the horizontal
This shows how to use CUDISP
and DISPTMG signals.
direction on
the screen and horizontal one-character
CUDISP and DISPTMG signals
time is so short that both display memory and CG cannot
should be used being latched at least one time at external
be accessed, the circuitry shown in Fig. 16 should be
flip-flop F1 and F2.
used.
Flip-Flop F1
and F2 function
to make one-character delay time so as to synchronize
I n this case, display memory output shall be latched
and CG shall be accessed at the next cycle. The time chart
them with the video signal from parallel-serial converter.
in this case is shown in Fig. 19
High-speed D-type flip-flop as TTL is used for this
signals should be provided after being delayed by one-
purpose. After being delayed at F1 and F2 DISPTMG
character time by using skew bit of interlace & skew
CUDISP and DISPTMG
signal is OR-ed with output from AND gate. By using this
register (RS).
circuitry, blanking of horizontal and vertical retrace time is
about delay time of MA during horizontal one character
controlled and cursor video is mixed with character video
time on high speed display operation, system shown in
signal.
Moreover, when there are some troubles
Fig. 17 should be adopted.
is shown in Fig. 20
Fig. 15
shows
the
example
in
the
case that both
two-character time because each MA output and display
display memory and CG can be accessed for horizontal
one character time.
in Fig. 18
Time chart for this case is shown
This method is uded when a few characters
need to be displayed in the horizontal direction on the
The time chart in this case
Character video signal is delayed for
memory outputs are latched and are made to be in phase
with CUDISP and DISPTMG signals by delaying for twocharacter time.
Table 5 shows the circuitry selection
standard of display units.
screen.
Table 5. Circuitry Standard of Display Control Unit
Interlace & Skew Register
Bit Programming
Block
Case
Relation among tCH. RM and CG
+ CG
1
tCH> RM Access
2
RM Access
+ CG
3
RM Access
+ tMAD ~ tCH
Accwss
Access
Diagram
+ tMAD
+ tMAD ~ tCH >
RM Access
> RMAccess
tCH: CHep Period: tMAD; MA Delay
5-14
+ tMAD
C1
CO
01
DO
Fig. 15,18
0
0
0
0
Fig. 16,19
0
1
0
1
Fig. 17,20
1
0
1
0
UM6845 / UM6845A / UM68458
CUDISP
CHCP - N -
_ _- - I
DISPTMG
VIDEO
MA
CRTC
DISPLAY
MEMORY
RA
ClK
CHCP - P
DOT COUNTER
Figure 15. Display Control Unit (1)
CUDISP
DISPTMG
MA
CRTC
DISPLAY
MEMORY
RA
ClK
CHCP - P
DOT COUNTER
Figure 16. Display Control Unit (2)
CUDISP
CHCP - N - - - - I
DISPTMG
CRTC
DISPLAY
MEMORY
RA
ClK
CHCP - P
DOT COUNTER
Figure 17. Display Control Unit (For high-speed display operation) (3)
5-15
UM6845/ UM6845A / UM68458
CHCP - P
3
2
MA
4
DISPTMG
CUDISP
F2-Q
Fl-Q
RMOUT
CGOUT
VIDEO
\
CRT DISPLAY
•••••••
Figure 18. Time Chart of display Control Unit (1)
-
---,
X
MA
I
J
J
CHCP - P
X
0
r--
--
X
1
CUDISP
r--L
r---::x
~J
F2-Q
~
Fl-Q
YlIIIIIII!t.
0
-",
CGOUT
- J
- ""X
t"""-
~
...............
~
YIlIlif!fJ.
1
-----....X
2
-X
-
0
---~
2
1
X
~
•••••••
Figure 19. Time Chart of Display Control Unit (2)
5-16
4X
'IlllllllJfi
3
~
1
0
X-
".,.,.,.,.,..,
VIDEO
CRT DISPLAY
\
~
...............
FMOUT
LATCH (1)
4
3
2
J
1
lONE CHARACTER~
SKEW
DISPTMG
~
3
-
2
X
X
,
3
"
UM6845 / UM6845A / UM68458
---,
CHCP - P
~
X
MA
LJ""'~LJ"'LJ"' ~ L-I
X
0
\
CUDISP
4
X
5
I
TWO CHARACTER SKEW
\
~
LATCH (2)
,
0
\
F2-Q
F1-Q
-
I
r-
----~
\.
I
\
\
~
-
t:.
(
1
0
..- •
4
3
-
XX
D
0
• •
3
2
1
0
- pO
-
W'
2
I{
LATCH (1)
CGOUT
X
3
\r ------ ----I
DISPTMG
RMOUT
2
1
1
2
-
XX
'0
1
I\.
(
3
2
--
XX
'11///////////////I/I!
4
3
L
4
'
X
VIDEO
I~ •••
CRT DISPLAY
4t • •
Figure 20. Time Chart of Display Unit (3)
How to Decide Parameters on the CRTC
Before the determination of parameters on the CRTC
and the dot frequency of crystal, we must check the
Specification of CRT Display Unit (Monitor) and the
Screen Format, The outp'ut signal timing of CRTC, must
be in the specification of Monitor to reach the formal
display. (Such as DISPTMG, HSYNC, VSYNC,). Screen
fromat includes:
(1) Horizontal display cha~acters column number. (Nhd)
(2) Vertical display row number. (Nvd)
(3) Horiz.ontal dot numbers per character. (Dot counter
(+Na)).
(4) Vertical raster lines per row. (N r + 1)
Example: for non-interlace mode one frame = 60 Hz
then one raster line frequency
=60Hzx [(N vt +1) (N r +1)+N adjl
ClK frequency of CRTC = raster line frequency
.x (Nht + 1)
dot frequency of crystal = Na x ClK frequency of CRTC
= 60Hz x [(N vt + 1) (N r + 1) +
Nadjl x [Nht+ 1) x Na
* Relation between RO-R7 is in Figure 21.
n.-u.u
I
Horizontal Programming
RO: Horizontal Total
I_
R1: Horizontal Display
I---
R2: Horizontal Sync.
1--1-1-----
RO+1----1
R1
------l
R2 + 1
----l
Position
R3
\~):
Horizontal Sync.
Width
R4: Vertical Total
~R4+1
R3 (H): Vertical Sync. Width
R6: Vertical Display
--II--
R7: Vertical Sync.
Position
Figure 21.
5-17
,I
I
II
I
_/
. R3 ( H } - - I I -
I----
R6 ----i_~1
R5: Vertical Total Adjust
R3 (L)
lIlJr
Vertical Programming
R5
I--R7+1
-.I I---
---l
UM6845/ UM6845A / UM6845B
Pin Description
Function
Name
Symbol
Data Bus
00- 07
Pin No.
33, 32, 31, 30
~I
29, 28, 27, 26
Enable
E
23
Chip Select
CS
25
Register Select
RS
24
Read/Write
R/W
22
Vertical Sync
VSYNC
·40
Horizontal Sync
HSYNC
39
Display Enable
OISPTMG
18
Processor
Interface
CRT Control
4,
5,
6,
7,
8,
Reading
Reading Display Memory/
MAO-MA13
9, 10, 11, 12, 13,
Memory Addresses
14, 15, 16, 17
Character Generator
Addressing
Other Pins
Raster Addresses
RAO-RA4
38, 37, 36, 35, 34
Cursor
CUDISP
19
Clock
ClK
21
Light Pen Strobe
lPSTB
3
Power
VCC(+) VSS(-)
20, 1
Reset
RES
2
5-18
UM6845/ UM6845A / UM68458
PROCESSOR INTERFACE
Display Enable (OISPTMG)
This TTL compatible output is an active high signal which
indicates the CRTC is providing addressing in the active
display area.
The CRTC interfaces to a processor bus on the bidirectional
data bus (00-07) using CS. RS. E. and R/W as control
signals.
Data Bus (00-07)
READING DISPLAY/CHARACTER GENERATOR
The bidirectional data lines (00-07) allow data transfers
between the CRTC internal register file and the processor.
Data bus output drivers are 3-state buffers which remain
in the high impedance state except when the processor
performs a CRTC read operation.
ADDRESSING
The CRTC provides Memory Addresses (MAO-MA 13) to
scan the display RAM. Also provided are Raster Addresses
(RAO-RA4) for the character ROM.
Reading Memory Addresses (MAO·MA13)
These 14 outputs are used to read the display memory.
Enable (E)
The Enable pin is a high impedanceTTL/MOS compatible
input which enables the data bus input/output buffers
and clocks data to and from the CRTC. This signal is
usually derived from the processor clock and the high
to low transition is the active edge.
Raster Addresses (RAO· RA4)
These 5 outputs from the internal Raster Counter address
the character ROM for the row of a character.
OTHER PINS
Chip Select (CS)
The CS line is a high impedance TTL/MOS compatible
input which selects the CRTC, when low, to read or write
the internal Register File. This Signal should only be
active when there is a valid stable address being decoded
from the processor.
Register Select (RS)
The RS line is a high impedance TTL/MOS compatible
input which selects either the Address Register (RS =
"0") or one of the Data Registers (RS = "1") of the in-'
ternal Register File.
Read/Write (RJVii)
The R/W line is a high impedance TTL/MOS compatible
input which determines whether the internal Register
File gets written or read. A write is active at low ("0").
Cursor (CUDISP)
This output Signal indicates the cursor display signal sent
to the video processing logic to display in the proper area.
Clock (ClK)
ClK, TTL/MOS compatible input is used to synchronize
all CRT control signals. An external dot counter is usedto derive this signal which is usually the character rate
in an alphanumeric CRT. The active transition is high to
low.
Light Pen Strobe (lPSTB)
This high impedance TTl/MOS compatible input latches
the current display memory address in the register file.
latching is on the low to high edge and is synchronized
internally to character clock.
CRT CONTROL
VCC, Gnd (VCC, VSS) Power Supply Pins.
Reset (RES)
The CRTC provides horizontal sync (HS). vertical sYf')c (VS),
and DIsplay Enable (OISPTMG) signals.
The RES input is used to reset the CRTC. An input low
level on RES forces CRTC into the following status:
(a)
Vertical Sync (V SYNC)
The TTL compatible output is an active high signal which
drives the monitor directly or is fed to Video Processing
Logic for composite signal generation. This Signal determines the vertical position of the displayed' text.
Horizontal Sync (H SYNC)
(b)
(c)
All the counters in CRTC are cleared and the device
stops the display operation.
All the outputs go to low level.
Control registers in CRTC remain unchanged.
This signal is different from other MC 6800 family in the
following functions:
'(a)
This TTL compatible output is an active high signal which
drives the monitor directly or is fed to Video Processing
logic for composite generation. This signal determines
the horizontal position of the displayed text.
5-19
(b)
RES signal has capability of reset function only when
lPSTB is at low level.
The CRTC starts the display operation immediately
after the release of RES signal.
UM6845/ UM6845A / UM68458
CRTC INTERNAL REGISTER ASSIGNMENT
Table 1. CRTC Internal Register
Address Register
CS
Register
RS
4
3
2
1
0
#
1
X
X
X
X
X
X
X
Program
Register File
Unit
-
-
Number of Bits
Read
Write
7
-
-
0
0
X
X
X
X
X
AR
Address Register
-
No
Yes
0
1
0
0
0
0
0
RO
Horizontal Total *
Char.
No
Yes
0
1
0
0
0
0
1
R1
Horizontal 0 isplayed
Char.
No
Yes
0
1.
0
0
0
1
0
R2
H. Sync Position*
Char.
No
Yes
V-Raster
H-Char.
No
Yes
0
1
0
0
0
1
1
R3
Sync Width
0
1
0
0
1
0
0
R4
Vertical Total *
Char. Row
No
Yes
0
1
0
0
1
O'
1
R5
V. Total Adjust
Scan Line
No
Yes
0
1
0
0
1
1
0
R6
Vertical Displayed
Char. Row
No
Yes
0
1
0
0
1
1
1
R7
V. Sync Position*
Char. Row
No
Yes
0
1
0
1
0
0
0
R8
I nterface Mode and
Skew
-
No
Yes
0
1
0
1
0
0
1
R9
Max Scan Line Address
Scan Line
No
Yes
0
1
0
1
0
1
0
R10
Cursor Start Raster
Scan Line
No
Yes
0
1
0
1
0
1
1
R11
Cursor End Raster
Scan Line
No
Yes
0
1
0
1
1
0
0
R12
Start Address (H)
-
Yes
Yes
0
1
0
1
1
0
1
R13
Start Address (L)
-
Yes
Yes
0
1
0
1
1
1
0
R14
Cursor (H)
-
Yes
Yes
0
1
0
1
1
1
1
R15
Cursor (L)
-
Yes
Yes
0
1
1
0
0
0
0
R16
Light Pen (H)
-
Yes
No
0
1
1
0
0
0
1
R17
Light Pen (L)
-
Yes
No
6
5
4
3
2
1
0
~ I~ I~ ~ i~ ~ ~ ~
~ I~ I~
V1
V1
V1
V1
~
~ I~ I~
~
~
Cl
Co
01
DO
~ ~G
H
H
1\1\
H
H
11
10
~ B P
~ I~ G
0
0
0
0
0
0
Table 1. Shows The Reg-ister File In CRTC, The Registers Marked* (Written Value) = (Specified Value) - 1
REGISTER DESCRIPTION
Address Register (AR)
of H Sync output.
The Address Register is a 5-bit write-only register used
as an "indirect" or "pointer" register. Its contents are
the address of one of the other 18 registers in the file.
When RS and CSarelow, the Address Register itself is
addressed. When RS is high, the register file is accessed.
(see Table 1).
displayed character timeunits minus one.
It is the total of displayed plus non-
Horizontal Total Register (RO)
This 8 bit register determines the horizontal sync position
on the horizontal line.
Horizontal Displayed Register (R 1 )
This 8 bit register determines the number of displayed
characters per horizontal line.
Horizontal Sync Position Register (R2)
This 8 bit Register determines the horizontal frequency
5-20
UM6845/ UM6845A / UM68458
Sync Width Register (R3)
Vertical Sync Position (R7)
Iv Iv IvlvlH
H
H
This 7-bit write-only register controls the position of
vertical sync with respect to the reference. It is programmed in character row times. Any number equal to or less
than the vertical total (R4) may be used.
H
This 8 bit write-only register determines the width of the
vertical sync (VS) pulse and the horizontal sync (HS)
pulse.
Interlace Mode and Skew Register (RB)
The HS pulse width may be programmed from 1-to-15
The VS pulse width may be
character clock periods.
programmed from 1-to-16 Raster scan lines. (see Table 2)
10
Vertical Total Register (R4) and Vertical Total Adjust
Register (R5)
The vertical frequency of VSYNC is determined by both
R4 and R5. The calculated number of character line
times is usually an integer plus a fraction to get exactly
a 50 or 60 Hz vertical refresh rate. The integer number
of Character line times minus one is programmed in the
7 bit write-only Vertical Total Register, the fraction is
programmed in the 5 bit write-only Vertical Scan Adjust
Register as a number of scan line times.
Vertical Displayed Register (R6)
This 7-bit write-only register specifies the number of
displayed character rows on the CRT screen, and is programmed in character row times. Any number smaller
than the contents of R4 may be programmed into R6.
This is a register used to program raster scan mode and
skew of CUDISP signal and DISPTMG signal.
In the
non-interlace mode, the rasters of even number field and
odd number field are scan duplicated. In the interlace
sync mode, the rasters of odd number field are scanned
in the middle of even number field. 'Thus, the same character pattern is displayed in both fields. In the interlace
sync and video mode, the raster scan method is the same
as the interlace sync mode, but it is controlled to display
different character patterns in two fields. Skew function
is used to delay the output timing of CUDISP and DISPTMG
signals such that they are synchronized with serial video
output signal. This is due to the time delay from display
memory data to serial output character pattern. (see Table
3).
Table 2. Sync Width Register
VSW
HSW
21
20
Pulse Width
Unit: CH
0
0
0
No Used
0
0
1
1
1
0
2
27
26
2
5
24
Pulse Width
Unit: H
0
0
0
0
16H
0
0
0
0
1
1
0
0
0
1
0
2
0
0
0
0
1
1
3
0
0
1
1
3
0
1
0
0
4
0
1
0
0
4
0
1
0
1
5
0
1
0
1
5
0
1
1
0
6
0
1
1
0
6
2
3
22
0
1
1
1
7
0
1
1
1
7
1
0
0
0
8
1
0
0
0
8
1
0
0
1
9
1
0
0
1
9
1
0
1
0
10
1
0
1
0
10
1
0
1
1
11
1
0
1
1
11
1
1
0
12
1
1
0
0
12
0
1
1
0
1
13
1
1
0
1
1"3
1
1
1
0
14
1
1
1
0
14
1
1
1
1
15
1
1
1
1
15
H: Raster Period
CH: Character Clock Period
5-21
UM6845/ UM6845A / UM68458
Table 3. Interlace Mode and Skew Register
I nterlace Mode (2 1 ,20 )
Cursor Skew Bit (2 7 , 26 )
DISPTMG Skew Bit (2 5 , 24)
10
11
Raster Scan Mode
0
0
Non-Interlace Mode
1
·0
Non-I nterlace Mode
0
1
Interlace Sync Mode
1
1
I nterlace Sync & Video Mode
C1
Co
CUDISP Signal
0
0
Non-Skew
0
1
One-Character Skew
1
0
Two-Character Skew
1
1
Non-Output
Dl
Do
DISPTMG Signal
0
0
Non-Skew
0
1
One-Character Skew
1
0
Two-Character Skew
1
1
Non-Ouptut
Maximum Raster Address Register (R9)
This is a register used to program maximum raster address
within 5-bit. This register defines total number of rasters
per character including space. This register is programmed
as follows.
programmed.
For Interlace Sync & Video Mode
When total number of rasters in RN, (RN-2) shall be
programmed.
For Non-interlace Mode, Interlace Sync Mode
When total number of rasters is RN, (RN-1) shall be
Non-Interlace Mode
o
Total Number of Rasters 5
Programmed Value N r = 4
(The same as displayed total number of rasters)
1
2
3
4
Raster Address
I nterlace Sync Mode
0
-------------
0
---------
2
Total Number of Raster
Programmed Value Nr =
(In the interlace sync
odd fields is ten. On
rasters).
5
4
mode, total number of rasters in both the even and
programming, half of it is defined as total number of
----------- 2
3
----- -------- 3
4
------------- 4
Raster Address
5-22
eUMC
UM6845/ UM6845A / UM68458
Interlace Sync & Video Mode
o
Total Number of Rasters 5
Programmed Value N r = 3
(Total number of rasters is displayed in the even field and the odd field)
2
- - - - - - - - - --- 3
4
Cursor Start Raster Register (R10)
address by lower 5-bit (2°_2 4 ) and the cursor display
mode higher 2-bit (2 5 ,2 6 ), (see Table-4),
This is a register used to program the cursor start raster
Table 4. Cursor Display Mode
Cursor Display Mode
B
P
Cursor Display Mode
(2 6 ,2 5 )
0
0
Non-blink
0
1
Cursor Non-display
1
0
Blink, 16 Field Period
1
1
Blink, 32 Field Period
Cursor End Raster Register (R11)
The higher 2-bit (2 6 , 27) of R14are always "0",
This is a register used to program to cursor end raster
address,
Light Pen Register (R16, R17)
These read-only registers are used to catch the detection
address of the I ight pen, The higher 2-bit (2 6 , 27) of
Start Address Register (R12, R13)
These are used to program the first address of refresh
memory to read out,
Paging and Scrolling is easily per-
formed using this register, This re,9ister can be read but
the higher 2-bit (2 6 , 27) of R 12 are always "0:',
Cursor Register (R14, R15)
R 16 are always "0",
Its value needs to be corrected by
software because there is time delay from address output
of the CRTC to signal input LPSTB pin of the CRTC
in the process raster is lit after address output and light
pen detects it,
These two read/write registers store the cursor location,
5-23
UM6845jUM6845AjUM68458
CRTC Register Comparison Table
NON-INTERLACE
UM6845R
MC6845
MC6845 * 1
Register
MC6845R
HD6845R
UM6845
HD6845S
UM6845E
SYS6545-1
RO Htotal
Total-1
Total-1
Total-1
Total-1
Total-1
R1 Hdisp
Actual
Actual
Actual
Actual
Actual
R2 Hsync
Actual
Actual
Actual
Actual
Actual
R3 Sync Width
Horizontal
(& Vertical *1)
Horizontal
Horizontal
& Vertical
Horizontal
& Vertical
Horizontal
& Vertical
R4 Vtotal
Total-1
Total-1
Total-1
Total-1
Total-1
R5 Vtotal Adjustment
Any Value
Any Value
Any Value
Any Value
Any Value
Except R5
R6 Vdisp
Any Value
-
«
2 Pulse Width, High
440
-
200
-
150
-
ns
PWEL
ct>2 Pulse Width, Low
420
-
190
-
140
-
ns
tAS
Address Set- Up Time
80
-
40
-
30
-
ns
tAH
Address Hold Time
0
-
0
-
0
-
ns
tcs
R/W, CS Set-Up Time
80
-
40
-
30
-
tDDR
Read Access Time (Valid Data)'
-
290
-
150
-
ns
100
ns
tDHR
Read Ho Id Time
10
-
10
-
10
60
ns
tDA
Data Bus Active Time (I nvalid Data)
20
60
20
60
20
60
ns
MAO-MA 13 Switching Delay
100
(Refer to Figure Trans. Addressing)
typo
130
ns
tTAD
(t r and tf = 10 to 30 ns)
5-41
160
100
typo
90
160
typo
G)UMC
UM6845E / UM6845EA / UM6845EB
Memory and Video Interface Characteristics
(Vee = 5.0V ± 5%, TA = a to 70°C, unless otherwise noted)
MAO-MA13 _ _ _ _ _ _ _ _ _ _ _ _
RAO-RA4
~---J
------------r---J
DISPLAY ENABLE ____________
~-----J
-+-____
HSYNC, VSYNC ____________
_J
CURSOR
Symbol
Parameter
Min.
tCCH
Minimum Clock Pulse W'idth, High
130
tccv
Clock Frequency
3.7
MHz
t r , tt
Rise and Fall Time for Clock Input
20
ns
tMAD
Memory Address Delay Time
100
160
ns
tRAD
Raster Address Delay Time
100
160
ns
tOTO
Display Timing Delay Time
160
250
ns
tHSD
Horizontal Sync Delay Time
160
250
ns
tVSD
Vertical Sync Delay Time
160
250
ns
tCDD
Cursor Display Timing Delay Time
160
250
ns
Transparent Addressing (if> 1I if> 2 Interleaving)
Typ.
Max.
Units
ns
Light Pen Strobe Timing
CCLK
E
LPEN ____...-_ _ _....
x::=
X'-___n_+_'_....IX'-___n_+_2__
MAO-MA13 _______..J
UPDATE
ADDR
MAOMA13
Note: "Safe" time position for LPEN positive edge
to cause address n + 2 to load into Light Pen Register.
tLP2 and tLPl are time positions causing uncertain results.
UM6845E
Symbol
Characteristics
Min.
UM6845EA
max.
Min.
UM6845EB
Max.
Min.
Max.
Unit
tlPH
lPEN Strobe Width
100
-
100
-
100
-
ns
tlP1
lPEN to CClK Delay
-
120
-
120
-
120
ns
CClK to lPEN Delay
-
a
-
0
-
0
ns
tlP2
tr and tf = 20 ns (max.)
5-42
eUMC
UM6845£ / UM6845£A / UM6845£B
MPU Interface Signal Description
E (Enable)
The enable signal is the system input and is used to trigger
all data transfers between the system microprocessor and
the UM6845E. Since there is no maximum limit to the
allowable E cycle time, it is not necessary for it to be a
continuous clock. This capability permits the UM6845E
to be easi Iy interfaced to non-6500-compatible microprocessors.
R/W (Read/Write)
The R/Wsignal is generated by the microporocessor and is
used to control the direction of data transfers. A high on
the R/W pin allows the processor to read the data supplied
by the UM6845E, a low on the R/W pin allows a write to
the UM6845E.
CS (Chip Select)
The Chip Select input is normally connected to the processor address bus either directly or through a decoder.
The UM6845E is selected when CS is low.
RS (Register Select)
The Register Select input is used to access internal registers.
A low on this pin permits write into the Address Register
and reads from the Status Register. The contents of the
Address Register is the identity of the register accessed
when RS is high.
ENABLE may be delayed by one character time by setting
bit 4 of R8 to a "1 "
CURSOR
The CU RSOR signal is an active-high output and is used
to indicate when the scan coincides with the programmed
cursor position. The cursor position may be programmed
to be any character in the address field. F urtherillore,
with in the character, the cursor may be programmed to
be any block of scan lines, since the start scan line and the
end scan line are both programmable.
The CURSOR
position may be delayed by one character time by setting
bit 5 of R8 to a "1"
LPEN
The LPEN signal is an edge-sensitive Input and is used to load
the internal Light Pen Register with the contents of the
Refresh Scan Counter at the time the active edge occurs.
The active edge of LPEN is the low-to-high transition.
CCLK
The CCLK signal is the character timing clock input and is
used as the time base for all internal count/control functions.
DB9-DB7 (Data Bus)
The DBo-DB7 pins are the eight data lines used for transfer
of data between the processor and the UM6845E. These
lines are bi-directional and are normally high-impedance
except during read/write cycles when the chip is selected.
RES
The RES signal is an active-low input used to initialize all
internal scan counter circuits. When RES is low, all internal
counters are stopped and cleared, all scan and video outputs
are low, and control registers are unaffected. RES must
stay low for at least one CCLK period. All scan timing
is initiated when RES goes high. In this way, RES can
be used to synchronize display frame timing with line
frequency.
Video I nterface Signal Description
Memory Address Signal Description
HSYNC (Horizontal Sync)
The HSYNC signal is an active-high output used to determine the horizontal position of displayed text. It may
drive a CRT monitor directly or may be used for composite
video generation. HSYNC time position and width are
fully programmable.
MAO-MA 13 (Video Display RAM Address Lines)
These signals are active-high outputs and are used to address
the Video Display RAM for character storage and display
operations. The starting scan address is fully programmable
and the ending scan address is determined by the total
number of characters displayed, .which is also programmable, In terms of characters/line and lines/frame.
VSYNC (Vertical Sync)
The VSYNC signal is an active-high output used to determine the vertical position of displayed text. Like HSYNC,
VSYNC may be used to drive a CRT monitor or composite
video generation circuits. VSYNC position and width are
both fully programmable.
There are two selectable address modes for MAO-MA 13:
• Binary
Characters are stored in successive memory locations.
Thus, the software must be developed so ·that row and
column co-ordinates are translated to sequentially
numbered addresses for video display memory operations.
• Row/Column
In this mode, MAO-MA7 function as column addresses
CCO-CC7, and MA8-MA13, as row addresses CRO-CR5.
In this case, the software may handle addresses in terms
of row and column locations, but additional address
compression circuits are needed to convert CCO-CC7
and CRO-CR5 into a memory-efficient binary scheme.
DISPLAY ENABLE
The DISPLAY ENABLE signal is an active-high output
and is used to indicate when the UM6845E is generating
active display information. The nu mber of horizontal
displayed characters and the number of vertical displayed
characters are both fully programmable and together are
used to generate the DISPLAY ENABLE signal. DISPLAY
5-43
UM6845E / UM6845EA / UM6845EB
Description of I nternal Registers
RAO-RA4 (Raster Address Lines)
These signals are active-h igh outputs and are used to select
Figure 1 illustrates the format of a typical video display
each raster scan within an individual character row.
and is necessary to understand the functions of the various
The
number of raster scan I ines is programmable and determines
UM6845E internal registers.
the character height, including spaces between character
and horizontal timing.
Figure 2 illustrates vertical
Figure 3 summarizes the internal
registers and indicates their address selection and read/
rows.
write capabilities.
The high-order line, RA4, is unique in that it can also
function as a strobe output pin when the UM6845E is
programmed
to operate in
Address Register
the "Transparent Address
In this case the strobe is an active-high output
This is a 5-bit register which is used as a "pointer" to direct
and is true at the time the Video Display RAM update
UM6845E data transfers to and from the system MPU.
Mode".
In
Its contents is the number of the .desired register (0-31).
this way, updates and readouts of the Video Display
When RS is low, then this register may be loaded; when
address is gated on to the address lines, MAO-MA 13.
RAM can be made under control of the UM6845E with
RS is high, then the register
only a small amount of external circuitry.
identity is stored in th is register.
sel~cted
is the one whose
HaRT TOTAL
HOR DISPLAYED
I
I
A B C 0 E F G H
M N o P
VERT
DISPLAYED
VERT
TOTAL
I
r
:;;:;
J K L
I
.......
]
t7~~
~
NUMBER OF
SCAN LINES
PER
CHARACTER
ROW
~:;;:; ~J
J
VERT
TOTAL
ADJUS T
]
Figure 1. Video Display Format
Status Register
Horizontal Total (RO)
This 3-bit register is used to monitor the status of the
This 8-bit register contains the total of displayed and
CRTC, as follows:
non-displayed characters, minus one, per horizontal line.
The frequency of HSYNC is thus determined by this
register.
Horizontal Displayed (R1)
VERTICAL BLANKING
"0" Scan currently not in vertical blanking
portion of its timing
"1" Scan currently is in its vertical blanking
time.
1...-_ _ _
This
8-bit
register contains the number of displayed
characters per horizontal line.
LPEN REGISTER FULL
"9" This bit goes to "0" whenever either
register R16 or R17 is read by the MPU.
"1" This bit goes to ':1" whenever a LPEN
strobe occurs.
Horizontal Sync Position (R2)
This 8-bit register contains the position of the HSYNC
on the horizontal line, in terms of the character location
' - - - - - - UPDATE READY
"0" This bit goes to "0" when register R31
has been either read or written by the
MPU.
"1" This bit goes to "1" when an Update
Strobe occurs.
number on the line.
The position of the HSYNC deter-
mines the left-to-right location of the displayed text
on the video screen.
adjusted.
5-44
In th is way, the side margins are
UM6845£ / UM6845£A / UM6845£B
1 COMPLETE FIELD (VERTICAL TOTAL)
VERTICAL DISPLAYED
DISPLAY
ENBALE
HSYNC
VSYNC
RAO-RA4
CCLK
DISPLAY
ENABLE
HSYNC
----~--------------------------------4_----~
RAO-RA4 ____
'I~
______________________________________________
~~--
Figure 2. Vertical and Horizontal Timing
Horizontal and Vertical SYNC Widths (R3)
Vertical Total (R4)
This 8-bit register contains the widths of both HSYNC
and VSYNC, as follows:
The Vertical Total Register is a 7-bit register containing
the total number of character rows in a frame, minus
one. This register, along with R5, determines the overall
frame rate, which should be close to the line frequency
to ensure flicker-free appearance. If the frame time is
adjusted to be longer than the period of the line frequency,
then RES may be used to provide absolute snchronism.
Vertical Total Adjust (R5)
,~8____
4-.__
2 __~11 ,~8____
4-T__2__~1/
I
VSYNC WIDTH*
I
(NUMBER OF SCAN
LI NES)
The Vertical Total Adjust Register is a 5-bit write only
register containing the numper of additional scan lines
needed to complete an entire frame scan and .is intended
as a fine adjustment for the video frame time.
I
HSYNC WIDTH
I
(NUMBER OF CHARACTER
CLOCK TIMES)
Vertical Displayed (RS)
This 7-bit register contains the number of displayed
character rows in each frame. In th is way, the vertical
size of the displayed text is determined.
*IF BITS 4-7 ARE ALL "0", THEN VSYNC WILL BE
16 SCAN LINES WIDE.
Vertical Sync Position (R7)
Control of these parameters allows the UM6845E to be
interfaced to a variety of CRT monitors, since the HSYNC
and VSYNC timing signals may be accommodated without
the use of external one-shot timing.
5-45
This 7 -bit register is used to select the character row
time at which the VSYNC pulse is desired to occur and,
thus, is used to position the displayed text in the vertical
direction.
UM6845£ / UM6845£A / UM6845£B
Mode Control (RS)
Th is register is used to select the operating modes of the
UM6845E and is outlined as follows:
are used to control the character position of the cursor
over the' entire 16K address field.
Display Start Address High (R12) and low (R13)
These registers together comprise a 14-bit register whose
contents is the memory address of the first character
of the displayed scan (the character on the top left of
the video display, as in Figure 1). Subsequent memory
addresses are generated by the UM6845E as a result of
CCLK input pulses. Scrolling of the display is accompi ished by changing R 12 and R 13 to the memory address
associated with the first character of the desired line of
text to be displayed first. Entire pages of text may be
scrolled or ch,anged as well via R 12 and R 13.
tERLACE MODE CONTROL
BIT
1--.--
OPERATION
1
0
x
o
0
Non-I nterlace
1
Interlace SY NC' Raster Scan
1
1
Interlace SYNC and Video Raster
Scan
Cursor Position High (R14) and low (R15)
VIDEO DISPLAY RAM ADDRESSING
"0" for straight binary
"1" for Row/Column
"--VIDEO DISPLAY RAM ACCESS
"0" for shared memory
"1" for transparent memory addressing.
-DISPLAY ENABLE SKEW
"0" for no delay
"1" to delay Display Enable one character
time
L------CURSOR SKEW
"0" for no delay
"1" to delay Cursor one character time
L-------UPDATESTROBE (TRANSPARENT
MODE, ONLY)
"0" for pin 34 to function as memory
address
"1" for pin 34 to function as update strode
~-------UPDATE/READ
MODE TRANSPARENT
MODE, ONLY)
"0" for updates to occur during horizontal
and vertical blanking times with update
strobe
"1" for updates to be interleaved in cjJ2
portion of cycle
Scan Line (R9)
Th is 5-bit register contains the nu mber of scan Iines per
character row, including spacing minus one.
Cursor Start (R10) and Cursor End (R11)
These 5 -bit registers select the starting and ending scan
lines for the cursor. In addition, bits 5 and 6 of R 10 are
used to select the cursor mode, as follows:
5
lPEN High (R16) and low (R17)
These registers together comprise a 14-bit register whose
contents is the light pen st~obe position, in terms of the
video display address at which the strobe occurred. When
the LPEN input changes from low to high, then, on the
next negative-going edge of CC LK, the contents of the
internal scan counter is stored in registers R 16 and R 17.
Update Address High (R1S) and low (R19)
These registers together comprise a 14-bit register whose
contents is the memory address at which the next read
or update will occur (for transparent address mode, only).
Whenever a read/update occurs, the update location automatically increments to allow for fast updates or readouts
of consecutive character locations.
This is described
elsewhere in this document,
Dummy location (R31)
This register does not store any data, but is required to
detect when transparent addressing updates occur. This
is necessary to increment the Update Address Register
and to set the Update Ready bit in the status register.
BIT
6
These registers together comprise a 14-bit register whose
contents is the memory address of the current cursor
position. When the video display scan counter (MA lines)
matches the contents of th is register, and when the scan
line counter (RA lines) falls within the bounds set by
R 10 and R 11, then the CU RSO R output becomes active.
Bit 5 of the Mode Control Register (R8) may be used
to delay the CURSOR output by a full CCLK time to
accommodate slow access memories.
Cursor Mode
0
0
No Blinking
0
1
No Cursor
1
0
Blink at 16 x field period
Description of Operation
1
1
Blink at 32 x field period
Register Formats
Note that the ability to program both the start and end
scan I ine for the cursor enables either block cursor or
underline to be accommodate. Registers R14 and R15
Register pairs R12/R13, R14/R15, R16/R17, and R18/R19
are formatted in one of two ways:
1. Straight binary if register R8, bit 2 is a "0".
2. Row/Column if register R8, bit 2 is a "1 ". In this
5-46
UM6845£ / UM6845£A / UM6845£B
case the low byte is the Character Column and the
high byte is the Character Row.
block.
Figure 4 illustrates the address sequence for the video
display control for each mode.
Note from Figure 4 that the straight-binary mode has
the advantage that all display memory addresses are stored
in a continuous memory block, starting with address 0 and
ending at 1919. The disadvantage with this method is that,
if it is desired to change a displayed character location,
the row and column identity of the location must be
converted to its binary address before the memory may
be written. The row/column mode, on the other hand,
does not need to undergo th is conversion.
However,
memory is not used as efficiently, since the memory
addresses are not continuous, but gaps exist. This reguires
that the system be equipped with more memory than is
actually used and this extra memory is wasted. Alternatively, address compression logic may be employed to
translate the row/column format into a continuous address
Register Name
Notes:
In this way, the user Illay select whiChever mode is best
for the given application
The trade-offs between the
modes are software versus hardware.
Straight-binary
mode minimizes hardware requirements and row/column
requires minimum software.
Video Display RAM Addressing
There are two modes of addressing for the video display
memory:
1. Shared M€mory
In this mode the memory is shared between the MPU
address bus and the UM6845E address bus. For this
case, memory contention must. be resolved by means
of external timing and control circuits. Both the MPU
and the UM6845E must have access to the video display
RAM and the contention circuits must resolve this
mu Itiple access requ irement. F igu re 5 illustrates the
system configuration.
Stored Info.
RD
[!] Designates binary bit
~
DeSignates unused bit, Reading this bit is always "0", except for
R31, which does not drive the data bus at all, and for CS = "1"
which operates likewise.
Figure 3. Internal Register Summary
5-47
UM6845£ / UM6845£A / UM6845£B
Straight Binary Addressing Sequence
TOTAL = 90 - - - - - - - - - - - - - - - ,
DISPLAY = 80 - - - - - - - - ,
r - I- - - - - - - - - - - - -
rr
I.....----~---
0
80
160
,,
,
~ ~
II
...J
a:
(/)
~ is
~
L
L
1
81
161
2
82
162
-----
-----
---
---
77
157
237
78
158
238
79
159
239
,
,
I
,,
:
:
1760
1840
1920
2000
,
1761
1841
1921
2001
1762
1842
1922
2002
-----
2641
2642
81
161
241
---
-----
89
169
249
:,
I
,,
---
---------
1837
1917
1997
2077
1838
1918
1998
2078
1839
1919
1999
2079
1840
1920
2000
2080
1841
1921
2001
2081
---------
1849
1929
2009
2089
---
---
2217
2718
2719
2720
2721
---
2729
---
I
2640
80
160
240
:
,
I
Row/Column Addressing Sequence
r--------~-----------------TOTAL=90--------------------------~
,...----------- DISPLAY = 80 - - - - - - - - - - - - ,
. . . . . - - - - - - - COLUMN ADDR ESS (MAO-MA7) ------+--~-------------__.
r-cr-o
r
oo::t'N
oo::t
(Y)
«
II
~
:5>-
~
~
~ e; ;;
~ (3 ~
o L~
I-
L
0
~
1
2
o
0
256
512
,,
,
,
1
257
513
2
2
258
514
---
77
77
333
589
---
---
---
---
---
78
78
334
590
25
~
,
5633
5889
6145
6401
5634
5890
6146
6402
-----
I
89
89
345
601
,
,
,,
I
---
-----
8449
8450
---
-----
,
I
I
I
6477
5710
5966
6222
6478
5711
5697
6223
6479
5712
5968
6224
6480
5713
,5969
6225
6481
-------
5721
5977
6233
6489
8525
8526
8527
8528 ' 8529
---
8537
-----
5709
5965
6221
-----
---
I
8448
81
81
337
593
I
I
5632
5888
6144
6400
80
80
336
592
I
I
21
22
23
24
79
79
335
591
,,
---
I
I
Figure 4. Display Addreu Sequences (with Start Addres• ., OJ for 80 x 24 Ex.npte
VSYNC
SYSTEM
BUS
HSYNC
UM6845E
CRT CONTROLLER
DISPLAY ENABLE
RAO-RA4
CURSOR
DISPLAY ADDRESS
MPU
SCAN LINE
COUNT
SHIFT
REGISTER
VIDEO ADDRESS
CHARACTER
DATA
SCAN LINE
_ _ _. . DOT PATTERN
Figure 5. Shared Memory System Configuration
5-48
TO
VIDEO
CIRCUITS
(l)UMC
UM6845£ / UM6845£A / UM6845£8
UM6845E. All MPU accesses are made via the UM6845E
2. Transparent Memory Addreessing.
For this mode, the display RAM is not directly acces·
and a small amount ·of external circuits.
sible by the MPU, but is controlled entirely by the
shows the system
Figure 6
configuration for this approach.
SYSTEM
BUS
UM6845E
CRT CONTROLLER
RAO-RA3
MAO-MA13
RA4
UPDATE
STROBE
DISPLAY/UPDATE
ADDRESS
SCAN LINE
COUNT
MPU
MPU
DATA
BUS
CHARACTER
GENERATOR
ROM
DATA
HOLD
LATCH
CHARACTER
DATA
CHARACTER
DATA
Figure 6. Transparent Memory Addressing System Configuration (Data Hold Latch
needed for HorizontalNertical Blanking updates, only).
Memory Contention Schemes for Shared Memory
•
Addressing
This method permits both the UM6845E and the MPU
access to the video display memory by timesharing
From the diagram of Figure 4, it is clear that both the
via the system 1 and 2 clocks.
UM6845E and the system MPU must be capable of
addressing the video display memory.
repetitively
fetches character
During the 1
portion of each cycle (the time when E is low), the
The UM6845E
UM6845E address outputs are gated to the video display
information to generate
memory.
the video signals in order to keep the screen display active.
In the 2 time, the MPU address lines are
switched in.
The MPU occasionally accesses the memory to change
In this way, both the UM6845E and the
MPU have unimpeded access to the memory. Figure 7
the displayed information or to read out current data
characters.
11 2 Memory Interleaving
illustrates the timings.
Three ways of resolving this dualcontention
requirement are apparent:
•
Vertical Blanking
With this approach, the address circuitry is identical
•
MPU Priority
to the case for MPU Priority updates.
In this technique, the address lir")es to the video display
ference is that the Vertical Retrace status bit (bit 5
memory are normally driven by the UM6845E unless
of the Status Register) is used by the MPU so that access
The only dif-
the MPU needs access, in which case the MPU addresses
to the video display memory is only made during vertical
immediately overried those from the UM6845E and
blanking time (when bit 5 is a "1").
the MPU has immediate access.
visible screen perturbations result.
5-49
In this way, no
UM6845£ / UM6845£A / UM6845£B
E
VIDEO
DISPLAY
MEMORY
ADDRESSES
Figure 7. cf>1/cf>2 Interleaving
E
MAO-MA13
Figure 8. cf>1/cf>2 Transparent Interleaving
Transparent Memory Addressing
onto the MA lines during cf> 2.
In this mode of operation, the video display memory
timing.
Figure 8 shows the
address lines are not switched by contention circuits,
but are generated by the UM6845E.
contention is handled by the UM6845E.
In effect, the
•
HorizontallVertical Blanking
As a result,
1"11 this mode, the Update Address is loaded by the
the schemes for accomplishing· MPU memory access are
MPU, but is only gated onto the MA lines during
horizontal or vertical blank times, so memory accesses
different:
do not interfere with the display appearance.
To
signal when the update address is on the MA lines,
•
cf> 11 cf> 2 Interleaving
an update strobe (STR) is provided as an alternate
This mode is sim·ilar to the Interlave mode used sed
with shared memory.
In th is case, however, the
cf> 2
function of pin 34.
Data hold latches are necessary
to temporarily retain the character to be stored until
address is generated from the Update Address Register
the retrace time occurs.
(Registers R18 and R19) in the UM6845E.
is not halted waiting for the blanking time to arrive.
Thus,
In this way, the systemMPU
the MPU must first load the address to be accessed
Figure 9 illustrates the address and strobe timing for
into R 18/R 19 and then th is address is always gated
this mode.
5-50
UM6845£ / UM6845£A / UM6845£B
CCLK
DISPLAY
~ HORIZONTAL!VERTICAL
BLANKING
I
I
_______________ 1
-\
DISPLAY
ENABLE
MAOMA13
CRTDISPLAY
ADDRIESSES
I
I
I
I
I
I
1_
i
I
I
~ }pg~~ts
I
I
NON-DISPLAY
~~I---CRT DISPLAY ADDRESSES
*\ \\\\~ \\\\\\'/:rrr..
I
M
UPSTB
____________________- JI
I~~-----------------------------------
Figure 9. Retrace Update Timings
Interlace Modes
There are three raster-scan display modes (see Figure
10).
a) Non-Interlaced Mode
In this mode each scan line is refreshed at the vertical
field rate (50 or 60 Hz).
I n the interlaced scan modes, even and odd fields
alternate to generate frames.
NON-INTERLACED
The horizontal and ver-
tical timing relationship causes the scan lines in the
odd fields to be displaced from those in the even fields.
ODD
FIELD
EVEN
FIELD
The two additional raster -scan display modes pertain
to interlaced scans.
b) Interlace-Sync Mode
This mode is used when the same information is to
be displayed in both odd and even fields.
Enhanced
readability results because the spaces between adjacent
rows are filled and a higher quality character is displayed.
INTER LACED-SYNC
This is achieved with only a slight alteration in
the device operation: in alternate fields, the position
of the VSYNC signal is delayed by % of a scan line
time.
EVEN
FIELD
ODD
FIELD
This is illustrated in Figure 11 and is the only
difference in the UM6845E operation in this mode.
c) I nterlaced Sync and Video Mode
This mode is used to double the character density on
the screen by displaying the even lines in even fields
and the odd lines in odd fields.
As in the Interlace-
Sync mode, the VSYNC position is delayed in alternate
display fields.
I n addition, the address generation is
altered.
INTERLACED SYNC AND VIDEO
Figure .10. Comparison of Display Modes
5-51
UM6845£ / UM6845£A / UM6845£B
14-------------
1 COMPLETE FIELD - - - - - - - - - - - - - - l
DISPLAY
ENABLE
FOR CODD
FIELD
HSYNC
VSYNC
ODD FIELD
RAO-RA4
VSYNC
EVEN FIELD
DISPLAY
ENABLE
FOR EVEN
FIELD
1 SCAN LINE
DELAY
Figure 11. Interlace Sync Mode and Interlace 'Sync & Video Mode Timing
Cursor and Display Enable Skew Control
Bits 4 and 5 of the Mode Control register (R8) are used to delay the Display Enable and Cursor outputs, respectively.
Figure 12 illustrates the effect of the delays.
CCLK
I
I
I I
(NO DELAY)
n~:_--1_ __
.CURSOR
{
~______
~J
(WITH
DELAY) I
. - - - ,J~____
I
DISPLAY
ENABLE
POSITIVE
EDGE
(NO DELAY)
{
(WITH DELAY)
(NO DELAY)
DISPLAY
ENABLE
NEGATIVE
EDGE
{
(WITH DELAY)
Figure 12. Cursor and Display EnalbeSkew
5-52
UM6845£ / UM6845£A / UM6845£8
FRAME
FRAME
VERTICAL DISPLAYED
VERTICAL
BLANKING
DISPLAY
ENABLE
VERTICAL
BLANKING
STATUS
BIT
I·
1
I
r
(STATUS
== DISPLAY
REGISTER
.._ _"0"
__
_ _ _ACTIVE
_ _ _ _..
BIT 5)
t
, " - - 1_
\
SWITCHES STATE AT
END OF LAST DISPLAYED.
SCAN LINE.
__ _
"1" = VERTICAL
BLANKING
ACTIVE
Figure 13. Operation of VertU:a1 Blanking Status Bit
5-53
UM6845£jUM6845£AjUM6845£8
CRTC Register Comparison Table
NON-INTERLACE
UM6845R
MC6845
MC6845*1
Register
MC6845R
HD6845R
UM6845
HD6845S
UM6845E
SYS6545-1
RO Htotal
, Total-l
Total-l
Total-l
Total-l
Total-l
Rl Hdisp
'Actual
Actual
Actual
Actual
Actual
R2 Hsync
Actual
Actual
Actual
Actual
Actual
R3 Sync Width
Horizontal
(& Vertical *1)
Horizontal
Horizontal
& Vertical
Horizontal
& Vertical
& Vertical
R4 Vtotal
Total-l
Total-l
Total-l
Total-l
Total-l
R5 Vtotal Adjustment
Any Value
Any Value
Any Value
Any Value
Any Value
Except R5
R6 Vdisp
Any Value
n to be serially shifted into the serial scan
line shift register. If this signal is low for 7 or more LD/SH pulses, the
UM8321 will assume the parallel input scan line row address mode.
19
Scan line
O/Scan Line
data
SLO/SLD
This input has two separate functions depending on the way scan line
information is presented to the UM8321. Refer to Figure 2.
Parallel scan line mode - This input is the least significant bit of the
binary scan line row address.
Serial scan line mode - This input will present the scan line information
in serial form (least significant bit first) to the UM8321 and permits the
proper sGan line information to enter the serial scan line shift register
during the LD/SH pulses framed by SLG (pin 18).
LD/SH
I
I
~~.--~~--~--~~--~~r-
I
x
SLD
' - - - - - NOT USED BY UM8321
Figure 2. Serial Scan Line Mode Timing
PIN No.
Name
Symbol
20
Ground
GND
Vertical Sync
VSYNC
21
.
Functions
Ground
This input is typically connected to the vertical sync output of the CRT
controller and is used as the clock input for the two on-chip mask programmable blink rate dividers. The cursor blink rate (50/50 duty cycle)
will always be twice the character blank rate (75/25 duty cycle). In
addition, the internal attributes are reset when this input is low. The
VSYNC input is also used to determine the scan line mode (parallel or
serial) used. See the section"Scan line I nput Modes".
5-62
(l)UMC
UMB321
Attributes Func,ion
Retrace Blank
time and allowing the normal video
The RETBL input causes the VIDEO
to go to the zero (black) level regard-
for 75% of the time.
less of the state of all other inpLits.
cursor is programmed to blink (not
When the
controlled by the BLINK input), the
Reverse Video
The REVID input causes inverted
video
data to be loaded into the video
shift register.
Character Blank
Underline
-
alternates
from
normal
to
reverse video at 50%- duty cycle.
The cursor blink rate always over-
The CHABL input forces the video
rides the character bl ink rate when
to go to the current background
they both appear at the same charac-
level as defined by Reverse Video.
ter position.
MS1, MSO = 1, 1 forces the video to
Intensity
The INTIN input and the INTOUT
go to the inverse of the background
(Half Intensity)
output allow an intensity (or half
level for thescan lines(s) programmed
intensity)
for underline.
through the pipeline of theUM8321.
attribute to
be .carried
An external mixer can be used to
Blink
The BLINK input will cause charac-
combine VICEO and
ters to blink by forcing the video to
create the desired video level.
the background level 25% of the
Figure 3a and Figure 3b.
INTOUT to
See
-
THREE f - - - STATE i - - DRIVER
"-
~p.
r-L
A
T
"
c
H
OE
CHARACTER
ROM
r----V
I-
~
"'-
-j/ D7·DO
UM8321
VAC
SYSTEM RAM
OR
SINGLE ROW
BUFFER
OR
DOUBLE ROW
BUFFER
FRg~T
CONTROLLER
SL3-SLO
{Sc>&o
VIDEO
I----
INTOUT
I----
--
VSYNC
RETBL
CURSOR
I
1
I
CLOCK
GENERATOR
I
ATTEN
LD/SH
VDC
Figure 3a: UM8321 System Configuration in Parallel Scan Line Mode
5-63
M
I
x t--
VSYNC
RETBL
CURSOR
MSrp
MSl
BLINK
CHABL
INTIN
REVID
r-E
R
L..--
VIDEO
TO MONITOR
UM8321
-
THREE _
~~~VTEER
-
~o.
~
.----------1~
L
A
~
"
1--.-----,/1
1------1
1------'
OE-
H I---------,v/
T~
.. 7
r----~
r+
SYSTEM RAM
~{SLG
, 7
CHA=~~TERt-----"'-----'''/ 07-00
v
4
1-_ _ _ _-'"
~
I - - - - - - - , v / I ._ _ _.....
UM8321
8
0
J
VAC
~
OR
SINGLE ROW
:;; f-...J
SLO-+-------------------I
BUFFER
~ a: ~ VSYNC
OR
LL U fRETBL
DOUBLE ROW
CURSOR - - - - - - - - - - - - - - - - - - - - - + 1
BUFFER
1-~-t---=--------------------___1..
SLG
SLO
VSYNC
RETBL
CURSOR
MS
ROM
ADDRESS BUS
RAM
VIDEO RAM 1 ' . . - - - - - , / 1
DMAR
ACK
INT
UM9007 CRTC
=VHSS I-_ _ _
---;~} ~~N ITOR
~LV_D_7~-O~________~SL~G__~S~LD________________CC~L~K________~
1.-_ _...... "
BUFFER
CONTROLS
Lr
+ SHIFT
REGISTER
.-----~ I~_____~--------,
.----~ I~_____- - - - - - - - .
I
DATA
BUS
SCAN LINE DATA
,J
r-:A~3~_A:;::O--~C~H~A:!:R~A~CT!!E~RlJW~IQD!!TH~
WCLK RCLK
~ DIN7_0UM831~OUT7_0
r----v'
DOUBLE ROW BUFFER
+
f------'\
r-v I" 11-A4
~
r
v
I
1--------",/11
CH~~CTER
CLOCK
GENERATOR
1.-_ _......-
++
CHAR
CODE
A7-0
VDCf4:-UM8321
SHLD .....- - - - '
CHARACTER ATTRIBUTS
DOUT7-0 t - - - - - - - - - - - - ' \ . I A T T R I B U T E S VIDE0I--_ _ _ _ _ TO MONITOR
~ DIN7-0 UM8312
v
'
=
f-----
DOUBLE ROW BUFFER
t - - - - - - - - - - - , / I V I D E O ATTRIBUTES
CONTROLLER
Figure 4. UM8312 Configured With The UM9007 CRTC And The UM8321 CRT VAC
5-75
UM8312
tCYW' tCYR -------~
RCLK OR WCLK
DIN7-0
~""""""""",,"'*"
REN,WEN1,2
DOUT7-0 ______________-r~--------
~
__________
()E ______________~~----------------
WOF,ROF _____________-r~------
CLRCNT OR TOG
~
_
k
WEN 1,2
__
t.CS
~,
tWT
----------------------------1
Figure 5. UM8312 I/O Ti"!ing
5-76
@)UMC
Floppy Disk Controller
Selection Guide
Part No.
Descriptions
Compatible Devices
UM8272A
Floppy Disk Controller
J.lPD 765A
UM9228-1
Floppy Data Separator
-
UM8326/B
Floppy Data Separator
WD 9216
UM8329/T /B/BT
Floppy Data Separator
SMC 9229
Remarks
Page
4,8 MHz Version
6-3
Special Design for IBM PC
6-24
4,8 MHz Version
6-29
Clock/X' TL Input 8,
6-2
16 MHz Version
6-34
(l)UMC
UM8272A / UM8272A'-4
: : : : : : : : : : : : : Floppy Disk Controller
Features
•
•
IBM Compatible in Both Single and Double Density
•
Parallel Seek Operations on Up to Four Drives
Recording Formats
•
Compatible with all intel and Most Other Mlcroprocessors
Programmable Data Record Lengths: 128, 256, 512,
or 1024 Bytes/Sector
•
•
Multi-Sector and Multi-Track Transfer Capability
•
Drives Up to 4 Floppy or Mini-Floppy Disks
•
Data Transfers in DMA or Non-DMA Mode
SIngle-Phase
8MHz/4MHz
Clock
for
UM8272A/
UM8272A-4 respectively
•
Single + 5 Volt Power Supply (± 1COAl)
General Description
The UM8272A is an LSI Floppy DIsk Controller (FDC)
capable of supporting either IBM 3740 single density
Chip, which contains the circuitry and control functions
format (F rvi), or I BM System 34 Double Density fo rmat
for interfacing a processor to 4 Floppy Disk Drives, It is
(MFM) including double sided recording,
Pin Configuration
RESET
RD
WR
CS
AO
DBo
DBl
DB2
DB3
DB4
DBs
DB6
DB7
DRO
DACK
TC
IDX
INT
ClK
GND
The UM8272A
Block Diagram
VCC
RW/SEEK
lCT/DIR
FR/STP
HDl
RDY
WP/TS
FlT/TRo
PS o
PSl
WDA
USo
USl
HD
MFM
WE
DBO-7
TERMINAL
. COUNT
ORO
DACK
INT
AD
WR
READY
WRITE PROTECT/TWO SIDE
INDEK
•
AO
FAULT/TRACK 0
RESET
cs ___-'
veo
UNIT SELECT 0
UN IT SE LECT 1
MFM MODE
RD
RDW
WCK
RW/SEEK
HEAD LOAD
HEAD SELECT
LOW CURRENT/DIRECTION
FAULT RESET/STEP
6-3
UM8272A /UM8272A.4
provides control signals which simplify the design of an
processor wishes the FDC to perform. The following com-
external phase locked 10QP and write precompensation
mands are available:
circuitry; . The FDC simplifies and handles most of the
burdens associated with implementing a Floppy Disk Drive
Read ID
Format a Track
Read Deleted Data
Write Deleted Data
Read a Track
Seek
Hand-Shaking signals are provided in the UM8272A which
Scan Equal
Recalibrate (Restore to Track 0)
make DMA operation easy to incorporate with the aid of
Scan High or Equal
Sense interrupt Status
an external DMA Controller chip.
Scan Low or Equal
Sense Drive Status
IS
a pin-compatible upgrade to
Write Data
the 8272.
interface.
The UM8272A
Read Data
The FDC will operate'
in either DMA or Non-DMA mode. In the Non-DMA mode,
Specify
the FDC generates interrupts to the processor every time a
data byte is available.
I n the DMA mode, the processor
Address mark detection circuitry is internal to the FDC
need only load the command into the FDC and all data
which simplifies the phase locked loop and read electronics.
transfers occur under control of the UM8272A and DMA
The track stepping rate, head load time, and head unload
controller.
time may be programmed by the user.
The UM8272A
offers many additional features such as multiple sector
transfers in both read and write with a single command,
There are 15 separate commands which the UM8272A
will .execute.
8-bit
Each of these commands requires multiple
and full
bytes to fully specify the operation which the
IBM compatibility in both single and double
density models.
MEMORIES
}
(
8080 SYSTEM BUS
/~
/~
BDO_7
AO
DBO_7
RD
WR
CS
INT
RESET
MEMR
lOR
MEMW
lOW
CS
HRO
HLDA
~7
DMA
CONTROLLER
READ
DATA
WINDOW
V
I PLL
RD DATA
DRO
WR DATA
DACK
UM8272A
TC
TERMINAL
COUNT
/
l-r
"-
INPUT CONTROL
'"
"OUTPUT CONTROL
Figure 1. System Configuration
6-4
DRIVE
INTERFACE
A
/
"-
UM8272A / UM8272A·4
Absolute Maximum Ratings*
*Comments
Operating Temperature . . . . . . . . . . . . . . oOC to + 70°C
Stress above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Storage Temperature . . . . . . . . . . . . . -55°C to + 150°C
All Output Voltages ., . . . . . . . . . ..
-0.5 to + 7 Volts
All Input Voltages . . . . . . . . . . . . . . -0.5 to + 7 Volts
Supply Voltage Vee . . . . . . . . . . . .. -0.5 to + 7 Volts
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
D.C. Characteristics
(T A = ooC to + 70°C, Vee = + 5V ± 10%)
Limits
Symbol
Units
Parameter
Conditions
Max.
Min.
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee + 0.5
V
VOL
Output Low Voltage
VO H
Output High Voltage
lec
0.45
V
IOL = 2.0 mA
Vec
V
IOH = -400 IJ-A
Vee Supply Current
120
mA
IlL
Input Load Current
(All I nput Pins)
10
-10
IJ-A
IJ-A
V IN = Vee
VIN =0 V
ILOH
High Level Output
Leakage Current
10
IJ-A
V OUT = Vee
IOFL
Output Float
Leakage Current
+10
IJ-A
0.45 V ~VOUT ~V ee
Unit
Conditions
2.4
-10
Capacitance
(T A = 25°C, fc = 1 MHz, Vee = OV)
Limits
Symbol
Parameter
Max.
Min.
C IN (¢)
Clock I nput Capacitance
20
pF
CIN
I nput Capacitance
10
pF
CliO
I nput/Output Capacitance
20
pF
All Pins Except
Pin Under Test
Tied to AC
Ground
A.C. Characteristics
o
(T A = oOe to + 70 e, Vee = +5.0V
± 10%)
CLOCK TIMING
Symbol
Parameter
Notes
Min.
Max.
Units
Tcy
Clock Period
120
500
ns
Note 5
tCH
Clock High Period
40
ns
Note 4,5
tRST
Reset Width
14
tCY
tAR
Select Setup to ROt
0
ns
tRA
Select Hold from ROt
0
ns
tRR
RD Pulse width
tRD
Data Delay from ROt
tDF
9utput Float Delay
READ CYCLE
ns
250
20
6-5
200
ns
100
ns
UM8272A / UM8272A·4
A.C. Characteristics (Continued)
(T A = OoC to + 70°c, Vcc = +5.0V ± 10%)
WRITE CYCLE
Symbol
Parameter
Typ.
Select Setup to WR..t-
tAW
Min.
Max.
Units
O
ns
tWA
Select Hold from WR t
0
ns
tww
WR Pulse Width
250
ns
tDW
Data Setup to WR t
150
ns
tWD
Data Hold from WRt
10
ns
Notes
INTERRUPTS
I NT Delay from R Dt
Note 6
INT Delay fro~ WRt
Note 6
DMA
tROCY
DRO Cycle Period
tAKRO
DACK ..t- to DRO..t-
tROR
DRO t to RD
t
800
ns
Note 6
tROW
DRO t to WR ..t-
250
ns
Note 6
tRORW
DRO tto RD torWR t
/ols
Note 6
/ols
MFM=O
MFM=11\J0te2
13
/ols
200
12
Note 6
ns
FDD INTERFACE
twCY
WCK Cycle Time
2 or 4
1 or 2
'tWCH
WCK High Time
250
tcp
Pre-Shift Delay from WCKt
tCD
WDA Delay from WCK t
tWDD
Write Data Width
tWE
WE t to WCK t or WE ..t- to WCK ..t- Delay
tWWCY
80
350
ns
20
100
ns
20
100
20
100
2
1
Window Cycle Time
ns
ns
twcH-50
ns
/ols
tWRD
Window Satup to RDD t
15
ns
tRDW
Window Hold from RDD ..t-
15
ns
tRDD
RDD Active Time (HIGH)
40
ns
MFM=O
MFM= 1
FDD SEEK/DI RECTION/STEP
tus
USO,1 Setup to RW/SEEK t
12
p.s
Note 6
tsu
USO,1 Hold after RW/SEEK ..t-
15
p.s
Note 6
tSD
RW/SEEK Setup to LCT/DIR
7
p.s
Note 6
tDS
RW/SEEK Hold from LCT/DIR
30
p.s
Note 6
tDST
LCT/DIR Setup to FR/STEPt
1
p.s
Note 6
tSTD
LCT /DI R Hold from FR/STER ..t-
24
p.s
Note 6
tSTu
DS2 ,1 Hold from FR/Step ..t-
5
p.s
Note 6
tSTP
STEP Active Time (High)
p.s
Note 6
tsc
STEP Cycle Time
33
p.s
Note 3, 6
tFR
FAULT RESET Active Time (High)
8
p.s
Note 6
tlDx
INDEX Pulse Width
tTC
Terminal Count Width
5
10
tCY
1
°
10
tCY
Notes:
1. Typical values for T A = 25 C and nominal supply voltage.
2. The former values are used for standard floppy and the latter values are used for mini·floppies,
3. tsc = 33 f.ls min, is for different drive units. In the case of same unit, tsc can be ranged from 1 ms to 16 ms with 8 MHzclock
period, and 2 ms to 32 ms with 4 MHz clock, under software control.
4. From 2.0V to + 2.0V,
5. At 4 MHz, the clock duty cycle may range from 16% to 76%. Using an 8 MHz clock the duty cycle can range from 32% to 52%.
Duty cycle is defined as: D.C. = 100 (tCH ~tCY) with typical rise and fall times of 5 ns.
6. The specified values listed are foran 8 MHz clock period, Multiply timings by 2 when using a 4 MHz clock period.
6-6
UM8272A /UM8272A.4
Pin Description
Pin
Input/
Output
Connection
to
Reset
Input
Processor
Places FDC in idle state Resets
output lines to FDD to "0" (low).
Does not eHect SRT, HUT or H l T
in Specify command. If RDY pin is
held high during Reset, FDC will
generate interrupt 1.024 ms later.
To clear th is interrupt use Sense
I nterrupt Status command.
RD
Read
InputCD
Processor
Contro I signal Tor transfer of data
from FDC to Data Bus, when "0"
(low).
3
WR
Write
InputCD
Processor
Control signal for transfer of data
to FDC via Data Bus, when "0"
(low).
4
CS
Chip Select
Input
Processor
IC selected when "0" (low), allowing RD and WR to be enabled.
5
Ao
Data/Status Reg
Select
InputQ)
Processor
Selects Data Reg (Ao = 1) or Status
Reg (Ao = 0) contents of the FDC
to be sent to Data Bus.
6-13
DBo-DB7
Data Bus
Input
Output
CD
Processor
Bi-Directional 8-Bit Data Bus.
14
DRO
Data DMA
Request
Output
DMA
DMA Request is being made by
FDC when DRW = "1"
15
DACK
DMA
Acknowledge
Input
DMA
DMA cycle is active when "0"
(low) and Controller is performing
DMA transfer.
16
TC
Terminal Count
Input
DMA
Indicates the termination of a DMA
transfer when "1" (high). It terminates data transfer during Read/
Write/Scan command in OMA or
interrupt mode.
17
IDX
Index
Input
FDO
Indicates the beginning of a disk
track.
18
INT
Interrupt
Output
ProcessQr
19 .
ClK
Clock
Input
20
GND
Ground
21
WCK
Write Clock
Input
22
ROW
Read Data
Window
Input
1\10.
Symbol
Name
1
RST
2
Functions
Interrupt
FDC.
Request Generated
by
Single Phase 8 MHz Squarewave
Clock.
D.C. Power Return.
Write Data rate to FDD. FM = 500
kHz, MFM = 1 MHz, with a pulse
width of 250 ns for both FM and
MFM.
Phase lock loop
6-7
Generated by Pll, and used to
sample data from FDO.
UM8272A /UM8272A-4
Pin Description (Continued)
Pin
Input
Output
Connection
to
Read Data
Input
FDD
Read data from FDD, containing
clock and data bits.
VCO
VCO Sync
Output
Phase Lock Loop
Inhibits VCO in PLL when "0"
(low), enables VCO when "1".
No.
Symbol
Name
23
RDD
24
Functions
25
WE
Write Enable
Output
FDD
26
MFM
MFM Mode
Output
Phase Lock Loop
MFM mode when "1 ", FM mode
when "0".
27
HD
Head Select
Output
FDD
Head 1 selected when "1" (high).
Head 2 selectwd when "0" (low).
28,29
US t , US o
Unit Select
Output
FDD
FDD Unit Selected.
30
Enables write data into FDD.
WDA
Write Data
Output
FDD
Serial clock and data bits to FDD.
31,32
PSI, PS o
Precompensation
(pre-shift)
Output
FDD
Write Precompensation status during MFM mode. Determines early,
late, and normal times.
33
FLT/TRo
Fault/Track 0
Input
FDD
Senses FDD fault condition, in
ReadlWrite mode; and Track 0 condition in Seek mode.
34
WP/TS
Write Protect/
Two-Side
Input
FDD
Senses Write Protect Status in Read/
Write mode; and Two Side Media
in Seek mode.
35
RDY
Ready
Input
FDD
Indicates FDD is ready to send or
receive data.
36
HDL
Head Load
Output
FDD
Command which causes read/write
head in FDD to contact diskette.
37
FR/STP
Fit Reset/Stop
Output
FDD
Resets fault F.F. in FDD in Read/
Write mode, contains stop pulses
to move head to another cylinder in
Seek mode.
38
LCT/DIR
Low Current/
Direction
Output
FDD
Lowers Write current on inner
tracks in ReadlWrite mode, determines direction head will stop in
Seek mode. A fault reset pulse is
issued at the beginning of each
Read or Write command prior to
the occurrence of the Head Load
signal.
39
RW/SEEK
Read Write/SEEK
Output
FDD
When "1" (high) Seek mode selected and when "0" (low) ReadlWrite
mode selected.
40
Vee
+5V
DC Power.
Note: CDDisabled when CS = 1.
6-8
UM8272A / UM8272A·4
UM8272A Enhancements
UM8272A Registers - CPU Interface
On the UM8272A, after detecti ng the Index Pu Ise, the
VCO Sync output stays low for a shorter period of time.
See F igu re 2A.
The UM8272A contains two registers which may be accessed by the main system processor, a Status Register
and a Data Register. The 8-bit Main Status Register tontains the status information of the FDC, and may be
accessed at any time. The 8-bit Data Register (actually
consists of several registers in a stack with only one register
presented to the data bus at a time), stores data, COIllmands, parameters, and FDD status information. Data
bytes are read out of, or written into, the Data Register in
order to program or obtain the results after execution of
a command. The Status Register may only be read and is
used to faci I itate the transfer of data between the processor
and UM8272A.
On the 8272 there can be a problem reading data when
Gap 2A is 00 and there is no lAM. This occurs on some
older floppy formats. The UM8272A cures this problem
by adjusting the VCO Sync timing so that it is not low
during the data field. See Figure 2B.
Cap 4A 11AM 1
Gap 1
110 1 Gap 2
Data
_~"";"'--'_-'-_ _~_...L_""""'-';""""'I-.._
Track
Index Pulse
8272
veo Sync ----...._ _ _ _ _ _ _ _ _---'r----
8272A VCO
Svnc-1L_ _ _. . r - - - - - - - - - -
*560 jJ.s in FM mode; 527 jJ.s in MFM mode
A. Margin on the Index Pulse
I Track
Index Pulse
Gap 4A (00)
~L....
The relationship between the Status/Data registers and the
signals RD, WR, and Ao is shown in Table 1.
Table 1. Ao, RD, WR decoding for the selection of Status/
Data register functions.
Data
Gap 2
_ _ _ _ _ _ _ _ __
r-
8272 VCO Sync
L.......Jr-----
8272A VCO Sync
Ao
1m
WR
0
0
0
1
0
1
0
0
0
1
1
1
B. Ability to Read Data When Gap 4A Contains 00
1
0
0
0
1
0
Function
Read Main Status Register
Illegal (see note)
Illegal (see note)
Illegal (see note)
Read from Data Register,
Write into Data Reqister
Note: Design must guarantee that the UM8272A is not
subjected to illegal inputs.
Figure 2. UM8272A Enhancements over the 8272
The Main Status Register bits are defined in Table 2.
Table 2. Main Status Register bit description.
Bit Number
Name
Symbol
Descriptions
DBo
FDD 0 Busy
DoB
FDD number 0 is in the Seek mode. If any of the bits isset
FDC will not accept read or write command.
DBl
FDD 1 Busy
DlB
FDD number 1 is in th Seek mode. If any of the bits is set
FDC will not accept read or write command.
DB2
FDD 2 Busy
D2B
FDD number 2 is in the Seek mode. If any of the bits is set
FDC will not accept read or write command.
DB3
FDD 3 Busy
D3 B
FDD number 3 is in the Seek mode. If any of the bits is set
FDC will not accept read or write command.
DB4
FDC Busy
CB
A read or write command is in process. FDC will not accept
any other command.
DBs
Execution Mode
EXM
This bit is set only during execution phase in non-DMA
mode. When DBs goes low, execution phase has ended, and
result phase was started. It operates only during NON-DMA
modes of operation ..
DB6
Data I nput/Output
010
Indicates direction of data transfer between FDC and Data
Register. If 010 = "1" then transfer is from Data Register
to the Processor. If 010 = "0", then transfer is from the
Processor to Data Register.
DB7
Request for Master
ROM
I nd icates Data Register is ready to send or receive data to
or from the Processor. Both bits 010 and ROM should be
used to perform the hand-shaking functions of "ready" and
"direction" to the processor.
The 010 and ROM bits in the Status Register indicate when Data is ready and in which direction data will be transferred on
the Data Bus. The max time between the last RD or WR during command or result phase and 010 and ROM getting set or
reset is 12 Ils. For this reason every time Main Status REgister is read the CPU should wait 121ls. The max time from the
trailing edge of the last RD in the result phase to when DB, (FOe Busy) goes low is 121ls.
Note: There is a 121lS or 241lS ROM flag delay when using an 8 or 4 MHz clock respectively.
6-9
I
UM8272A jUM8272A.4
Out F.Oe and Into Processor
Data In/Out
(DIO)
Out Processor and Into FOe
I
I
I
Raquest for Master :
(ROM)
L
I
Ready
I
will reset the interrupt as well as output the Data onto
the Data Bus. For example, if the processor cannot handle
I nterrupts fast enough (every 13 J.LS for MF M mode) then it
may poll the Main Status Register and then bit 07 (ROM)
functions just like the I nterrupt signal.
I f a Write
Command is in process, then the WR signal performs the
reset to the I nterrupt signal.
I
I
Notes:
0 -
The UM8272A always .operates in a multi-sector transfer
mode. It continues to transfer data until the TC input is
active. In Non-DMA Mode, the system must supply the TC
input.
Data register ready to be written into by processor
~- Data register not ready to be written into by processor
@]- Data register ready for next data byte to be read by the processor
~- Data register not ready for next data byte to be read by processor
Figure 3. Status Register Timing
The UM8272A is capable of executing 15 different commands. Each command is initiated by a multi-byte transfer
from the processor, and the result after execution of the
command may also be a multi-byte transfer back to the
Because of this multi-byte interchange of
processor.
information between the UM8272A and the processor, it
is convenient to consider each command as consisting of
three phases:
Command Phase:
Execution Phase:
Resuit Phase:
The FOC receives all information
required to perform a particular
operation from the processor.
The FOC performs the operation it
was instructed to do.
After completion of the operation,
status and other housekeeping information are made available to the
processor.
During Command or Result Phases the Main Status Register
(described in Table 2) must be read by the processor before
each byte of information is written into or read from the
Data Register. Bits 06 and 07 in the Main Status Register
must be in a 0 and 1 state, respectively, before each byte
of the command word may be written into the UM8272A.
Many of the commands require multiple bytes, and as a
result the Main Status Register must be read prior to Ijach
byte transfer to the UM8272A. On the other hand, during
the Result Phase, 06 and 07 in the Main Status Register
must both be 1 's (06 = 1 and 07 = 1) before reading each
byte from the Data Register. Note, this reading of the Main
Status Register before each .byte transfer to the UM8272A
is required in only the Command and Result Phases, and
NOT during the Execution Phase.
During the Execution Phase, the Main Status Register need
not be read. If the UM8272A is in the non-OMA Mode,
then the receipt of each data byte (if UM8272A is reading
data from FOO) is indicated by an interrupt signal on pin
18 (I NT = 1). The generation of a Read signal (R 0 = 0)
If the UM8272A IS In the DMA Mode, no Interrupts are
generated during the Execution Phase. The UM8272A
generates ORO's (DMA· Requests) when each byte of
data is avai lab Ie. The DMA Controller responds to th is
request with both a DACK = 0 (DMA Acknowledge) and
a RD = 0 (Read signal). When the DMA Acknowledge
signal goes low (DACK = 0) then the DMA Request is reset
(ORO = 0). If a Write Command has been programmed
then a WR signal will appear instead of RD. After the
Execution Phase has been completed (Terminal Count has
occurred) then an Interrupt will occur (INT = 1). This
signifies the beginning of the Result Phase. When the first
byte of data is read during the Result Phase, the Interrupt is
automaticaily raset (INT = 0).
It is important to note that during the Resuit Phase all
bytes shown in the Command Table must be read. The
Read Data Command, for example, has seven bytes of data
in the Result Phase. All seven bytes must be read in order to
successfully complete the Read Data Command.
The
UM8272A will not accept a new commqnd until all seven
bytes have been read. Other commands may require fewer
bytes to be read during the Result Phase.
The UM8272A contains five Status Registers. The Main
Status Register mentioned above may be read by the
processor at ~ny time. The other four Status Registers
(STO, ST1, ST2, and ST3) are only available during the
Result Phase, and may be read only after successfully completing a command. The particular command which has
been executed determines how many of the Status Registers
will be read.
.
The bytes of data which are sent to the UM8272A to from
the Command Phase, and are read out of the UM8272A in
the Result Phase, must occur in the order shown in the
Table 3 That is, the Command Code must be sent first and
the other bytes sent in the prescribed sequence.
No
foreshortening of the Command or Result Phases are
allowed. After the last byte of data in the Command Phase
is sent to the UM8272A, the Execution Phase automatically
starts. In a similar fashion, when the last byte of data is
read out in the Result Phase, the command is automatically
ended and the UM8272A is ready for a new command. A
command may be aborted by simply sending a Terminal
Count signal to pin 16 (TC=l). This is a convenient means
of ensuring that the processor may always get the
UM8272A's attention even if the disk system hangs up in
an abnormal manner.
6-10
SUMC
UM8272A / UM8272A-4
Command Symbol Description
Symbol
Name
Descriptions
Ao
Address Line 0
Ao controls selection of Main Status Register (Ao = 0) or Data Register
(Ao = 1).
C
Cylinder Number
C stands for the current/selected Cylinder (track) number 0 through 76
of the medium.
D
Data
D stands for the data pattern which is going to be written into a sector.
D7- D O
Data Bus
DTL
Data Length
8-bit Data Bus, where D7 stands for a most significant bit, and Do stands
for a least significant bit.
When N is defined as 00, DT L stands for the data length which users are
going to read out or write into the Sector.
EOT
End of Track
EOT stands for the final Sector number on a Cylinder. During Read or
Write operation FDC will stop date transfer after a sector # equal to
EOT.
GPL
Gap Length
GPL stands for the length of Gap 3. During ReadIWrite commands this
value determines the number of bytes that VCOs will stay low after two
CRC bytes. During Format command it determines the size of Gap 3.
H
Head Address
HD
Head
HD stands for a selected head number 0 or 1 and controls the polarity of
pin 27. (H = HD in all command words.)
HLT
Head Load Time
HLT stands for the head load time in the FDD (2 to 254 ms in 2 ms
increments) .
HUT
Head Unload Time
HUT stands for the head unload time after a read or write operation has
occurred (16 to 240 ms in 16 ms increments).
MF
FM or MFM Mode
If MF is low, FM mode is selected, and if it is high, MFM mode is
selected.
MT
Multi-Track
N
Number
NCN
New Cylinder Number
H stands for head number 0 or 1, as specified in ID field.
If MT is high, a multi-track operation is to be performed. If MT = 1 after
finishing ReadIWrite operation on side 0 FDC will automatically start
search i ng for sector 1 on side 1.
N stands for the number of data bytes written in Sector.
NCN stands for a new Cyfinder number, which is going to be reached as a
result of the Seek operation. Desired position of Head.
ND
Non-DMA Mode
ND stands for operation in the Non-DMA Mode.
PCN
Present Cylinder
Number
PCN stands for the Cylinder number at the completion of SENSE I NTERRUPT STATUS Command. Position of Head at present time.
R
Record
RIW
ReadlWrite
SC
Sector
SK
Skip
SRT
Step Rate Time
STO
ST1
ST2
ST3
Status
Status
Status
Status
RIW stands for either Read (R) or Write (W) signal.
SC indicates the number of Sectors per Cylinder.
SK stands for Skip Deleted Data Address Mark.
0
1
2
3
STP
USD, US1
R stands for the Sector number, which will be read or written. ,
SRT stands for the Stepping Rate for the FDD. (1 t016msin1 msincrements.) Stepping Rate applies to all drives, (F = 1 ms, E = 2 ms, etc.)
ST 0-3 stand for one of four registers which store the status information
after a command has been executed. This information is available during
the result phase after command execution. These registers should not be
confused with the main status register (selected by Ao = 0); STO-3 may
be read only after a command' has been executed and contain information relevant to that particular command.
During a Scan operation, if STP = 1, the data in continguous sectors is
compared byte by byte with data sent from the processor (or DMA); and
is STP = 2, then alternate sectors are read and compared.
Unit Select
US stands for a selected drive number 0 or 1.
6-11
I
UM8272A /UM8272A.4
Table 3. UM8272A Command Set
DATABUS
PHASE
R/W
Command
W
W
06
os
MT MF
SK
a
a
X
X
X
07
X
X
w
01
Do
1
1
a
HD US1 usa
C
H
R
N
EaT
GPL
DTL
W
W
W
W
w
W
R
R
R
R
R
R
R
REMARKS
Command Codes
PHASE
R/W
Command
W
a
w
X
Data-transter between
the FDD and mainsystem
Status information
after COr.1mand
execution
Sector ID information
after Command
execution
STa
ST 1
ST2
C
H
R
N
W
W
W
W
MT MF SK
a
1
X
X
X
X
X
1
a
a
HD US1 usa
C
H
R
N
EaT
GPL
aTL
w
W
W
W
W
Result
R
R
R
R
R
R
R
Result
R
R
R
R
R
R
R
Command
W
W
W
W
W
W
W
W
W
W
W
MT MF
0
0
X
X
X
X
0
Result
X
1
1
0
HD US1 usa
R
N
EOT
GPL
DTL
R
R
R
R
R
R
R
W
W
W
w
W
W
W
W
W
MT MF
X
X
0
0
1
X
X
X
Status information
after Command
Result
Execution
Result
R
R
R
R
R
R
R
MF
0
a
1
X
X
X
X
X
R
R
R
R
R
R
STO
ST 1
ST 2
C
H
R
N
W
W
W
STa
ST 1
ST2
C
H
R
N
1
0
MF
0
0
X
X
X
X
.
X
1
1
a
HD US1 usa
Commands
The first correct 10
information on the
Cylinder is stored in
Data Register
Status information
after Command
execution
Sector 10 information
read during Execution
Phase from Floppy
Disk
ST 0
ST 1
ST2
C
H
R
N
R
R
R
Command Codes
Bytes/Sector
Sectors/Track
Gap 3
Filler Bvte
FDC formats an
entire trach
Status information
after Command
execution
In this case. the 10
information has no
meaning
N
SC
GPL
0
R
SCAN EQUAL
Command
W
W
W
W
W
W
W
w
W
Command Codes
Sector 10 information
Prior to Command
execution. The 4 by
tes are commanded
against header on
Floppy Disk.
1
0
0
HD US1 usa
R
R
R
Sector 10 information
after Command
execution
C
H
R
N
EaT
GPL
DTL
Command Codes
Data-transter between
the FDD and mainsystem. FDC reads all
data fields from index
hole to loOT
Status information
after Command
execution
Sector 10 information
after Commant1l
execution
Execution
execution
1
0
0
HD US1 usa
1
a
a
HD US1 usa
Sector 10 information
prior to Command
execution
a
W
W
WRITE DELETED DATA
Command
a
X
STa
ST 1
ST 2
C
H
R
N
R
STO
ST 1
ST2
C
H
R
N
a
X
C
H
R
N
EaT
GPL
DTL
w
Data-transter between
the main-system and
FDD
Execution
Result
X
REMARKS
FORMAT A TRACK
Command
Command Codes
Sector ID information
Prior to Command
execution. The 4 by
tes are commanded
against header on
Floppy Disk.
C
H
X
Exer.ution
WRITE DATA
Command
MF SK
00
READ 10
Data-transter between
the FDD and mainsystem
Status information
after Command
execution
Sector 10 information
after Command
execution
STO
ST 1
ST 2
C
H
R
N
Os 04 03 02 01
READ A TRACK
Command Codes
Sector 10 information
Prior to Command
execution. The 4 by
tes are commanded
against header on
Floppy Disk.
Execution
06
Execution
READ DELETED DATA
Command
07
W
W
W
W
W
W
W
Sector 10 information
prior to Command
execution. The 4 by
tes are commanded
against header on
Floppy Disk.
Execution
Result
J
DATABUS
04 03 02
READ DATA
MT MF
SK
1
a
X
X
X
X
X
C
H
R
N
EaT
GPL
STP
Execution
Data-transter between
the FDD and mainsystem
Status information
after Command
execution
Sector ID information
after Command
execution
Note: 1 Symbols used in this table are described at the and of this section.
2 AO should equal binary 1 for all operations.
3 X = Don't care, usually made to equal binary a.
6-12
Result
R
R
R
R
R
R
R
STO
ST 1
ST 2
C
H
R
N
1
a
a
HD US1 usa
Command Codes
Sector 10 information
Prior to Command
execution.
Data-compared between the FOP
and main·system
Status information
after Command
execution
Sector '0 information
after Command
execution
UM8272A /UM8272A.4
Table 3. UM8272A Command Set (Continued)
DATA BUS
PHASE
Command
RIW
07
06
MT MF
W
W
X
DATABUS
05 04 0 3 02 01 Do
SCAN LOW OR EQUAL
SK
X
X
w
, ,
X
X
0
0
HD US,
,
Sector 10 information
prior Command
execution.
Data·coMpared be·
tween the FDD
and main-system
Status information
after Command
execution
Sector 10 information
after Command
execution
Execution
Aesult
A
A
A
A
A
A
A
STO
ST 1
ST2
C
H
A
N
W
MT MF
X
W
W
W
X
SK
,
1
X
X
X
,
0
HD USl
,
w
W
W
W
A
A
A
A
A
A
R
Command
W
W
0
0
0
0
0
X
X
X
X
X
06
05 04 03 02 0 1 Do
RECALIBRATE
1
0
1
US,
1
Head retracted to
Track 0
Command
W
Aesult
A
A
Command
W
0
0
0
,
0
0
0
0
0
0
-SAT
HLT
0
0
Polling Feature of the UM8272A
0
• •
, ,
..
OS1
OSO
APPROXIMATE SCAN TIMING
0
0
220fJ.S
0
1
220fJ.S
1
0
220fJ.S
1
1
440fJ.S
Command Codes
HUTNO
SENSE DRIVE STATUS
W
0
0
0
0
0
w
X
X
X
X
X
Aesult
A
Command
W
W
,
0
HD USl
0
Status information
about FDD
SEEK
0
0
0
0
,
X
X
X
X
X
Command Codes
usa
ST 3
,
1
HD USl
1
Command Codes
usa
NCN
Head is positioned
over proper Cylinder
on Diskette
INVALID
Command
W
----Invalid Codes - - -
Aesult
A
STO
Invalid Command
Codes (NoOp - FDC
goes into Standby
State)
ST 0 = 80
(16)
Command Descriptions
_..After power-up RESET, the Drive Select Lines DSO and
DS1 will automatically go into a polling mode. In between commands (and between step pulses in the SEE K
command) the UM8272A polls all four FDDs looking for
a change in the Ready line from any of the drives. If the
Ready line changes state (usually due to a door opening or
closing) then the UM8272A will generate an interrupt.
When Status Register 0 (STO) is read (after Sense Interrupt
Status is issued), Not Ready (NR) will be indicated: The
polling of the Ready line by the UM8272A occurs continuously between instructions, thus notifying the processor which drives are on or off line. Approximate scan
timing is shown in Table 4.
Table 4. Scan Timing
Command Codes
Status information at
the end of seck-operation about the FDC
SPECIFY
W
W
0
STO
PCN
Execution
STO
ST 1
ST2
C
H
A
N
Command Codes
SENSE INTERRUPT STATUS
W
Data-compared between the FDD
and main-system
Status information
after Command
execution
Sector 10 information
after Command
execution
REMARKS
usa
Execution
Command Codes
Sector ID information
prior Command
execution
Execution
Aesult
07
usa
C
H
A
N
EOT
GPL
STP
W.
RIW
Command
SCAN HIGH OR eQUAL
Command
Command Codes
PHASE
usa
C
H
A
N
EOT
GPL
STP
W
W
W
W
W
W
REMARKS
During the Command Phase, the Main Status Register must
be polled by the CPU before each byte is written into the
Data Register. The DIO (DB6) and ROM (DB7) bits in
the Main Status Register must be in the "0" and "1" states
respectively, before each byte of the command may be
written into the UM8272A. The beginning of the execution phase for any of these commands will cause DIO
and ROM to switch to "1" and "0" states respectively.
READ DATA
A set of nine (9) byte words are required to place the FDC
into the Read Data Mode. After the Read Data command
has been issued the FDC loads the head (if it is in the
unloaded state), waits the specified head setting time
(defined in the Specify Command), and begins reading I D
address Marks and I D fields. When the current sector
number ("R") stored in the ID Register (IDR) compares
with the sector number read off the diskette, then the FDC
outputs data (from the Data field) byte-by-byte to the main
system via the data bus.
After completion of the read operation from the current
sector, the Sector Number is incremented by one, and
the data from the next sector is read and output on the
data bus. This continuous read function is called a "MultiSector Read Operation." The Read Data Command must
6-13
UM8272A /UM8272A-4
be terminated by the receipt of a Terminal Count
signal. Upon receipt of this signal, the FDC stops outputting data to th~ processor, but will continue to read data
from the current sector, check CRC (Cyclic Redundancy
Count) bytes, and then at the end of the sector terminate
the Read Data Command.
The amount of data which can be handled with a single
command to the FDC depends upon MT (multi-track),
MFM (MFM/FM), and N (Number of Bytes/Sector). Table
5 on the next page shows the Transfer Capacity. The
"multi-track" function (MT) allows the FDC to read data
from both sides of the diskette. For a particular cylinder,
Table 5. Transfer Capacity
Maximum Transfer Capacity
(Bytes/Sector) (Number of
Sectors)
Final Sector
Read
from Diskette
Multi-Track
MT
MFM/FM
MF
Bytes/Sector
0
0
0
1
00
01
(128) (26) = 3,328
(256) (26) = 6,656
26 at Side 0
or 26 at Side 1
1
1
0
1
00
01
(128) (52) = 6,656
(256) (52) = 13,312
26 at Side 1
0
0
0
1
01
02
(256)(15)= 3,840
(512) (15) = 7,680
15 at Side 0
or 15 at Side 1
1
1
0
1
01
02
(256) (30) = 7,680
(512) (30) = 15,360
15 at Side 1
0
0
0
1
02
03
(512) (8)
(1024) (8)
1
1
0
1
02
03
(512) (16) = 8,192
(1024) (16) = 16,384
N
data will be transferred starting at Sector 1. Side 0 and
completing at Sector L. Side 1 (Sector L = last sector on
the side). Note, this function pertains to only one cylinder
(the same track) on each side of the diskette.
When N = 0, then DT L defines the data length which the
FDC must treat as a sector. If DTL is smaller than the
actual data length in a Sector, the data beyond DTL in the
Sector is not sent to the Data Bus. The FDC reads (internally) the complete Sector performing the CRC check,
and depending upon the manner of command termination,
may perform a Multi-Sector Read Operation. When N is
non-zero, then DTL has no meaning and should be set to
OFFH.
At the completion of the Read Data Command, the head
is not unloaded until after Head Unload Time Interval
(specified in the Specify Command) has elapsed. If the
processor issues another command before the head unloads
then the head settling time may be saved between
subsequent reads. This time out is particularly valuable
when a diskette is copied from one drive to another.
If the F DC detects the I ndex Hole twice without find ing
the right sector, (indicated in "R"), then the FOC sets the
= 4,096
= 8,192
8atSideO
or 8 at Side 1
8 at Side 1
NO (No Data) flag in Status Register 1 to a 1 (high), and
terminates the Read Data Command. (Status Register 0
also has bits 7 and 6 set to 0 and 1 respectively.)
After read ing the ID and Data Fields in each sector, the
FDC checks the CRC bytes. If a read error is detected (incorrect CRC in ID field), the FDC sets the DE (Data Error)
flag in Status Register 1 to a 1 (high), and if a CRC error
occurs in the Data Field the FDC also sets the DO (Data
Error in Data Field) flag in Status Register 2 to a 1 (high),
and terminates the Read Data Command. (Status Register
o also has bits 7 and 6 set to 0 and 1 respectively.)
If the FDC reads a Deleted Data Address Mark off the
diskette, and the SK bit (bit 05 in the first Command
Word) is not set (SK=O), then the FDC sets the CM (Control
Mark) flag in Status Register 2 to a 1 (high), and terminates
the Read Data Command, after reading all the data in the
Sector. If SK = 1, the FDC skips the sector with the
Deleted Data Address Mark and reads the next sector.
During disk data transfers between the FDC and the
processor, via the data bus, the FDC must be serived by
the processor every 27 Jl.S in the FM Mode, and every
6-14
UM8272A /UM8272A-4
13 #J.s in the MFM Mode, or the FOC sets the OR (Over
Run) flag in Status Register 1 to a 1 (high), and terminates
the Read Data Command.
If the processor terminates a read (or write) operation in
the FOC, then the 10 Information in the Result Phase is
dependent upon the state of the MT bit and EOT byte.
Table 3 shows the values for C, H, R, and N, when the
processor terminates the Command.
Table 6. 10 Information When Processor Terminates Command
10 Information at Result Phase
MT
EOT
Final Sector Transferred to Processor
C
H
R
N
NC
NC
R+ 1
NC
C+1
NC
R = 01
NC
NC
NC
R+ 1
NC
C+1
NC
R = 01
NC
R+ 1
NC
= 01
NC
1A
OF
08
Sector 1 to 25 at Side 0
Sector 1 to 14 at Side 0
Sector 1 to 7 at Side 0
1A
OF
08
Sector 26 at Side 0
Sector 15 at Side 0
Sector 8 at Side 0
1A
OF
08
Sector 1 to 25 at Side 1
Sector 1 to 14 at Side 1
Sector 1 to 7 at Side 1
1A
OF
08
Sector 26 at Side 1
Sector 15 at Side 1
Sector 8 at Side 1
1A
OF
08
Sector 1 to 25 at Side 0
Sector 1 to 14 at Side 0
Sector 1 to 7 at Side 0
NC
NC
1A
OF
08
Sector 26 at Side 0
Sector 15 at Side 0
Sector 8 at Side 0
NC
LSB
1A
OF
08
Sector 1 to 25 at Side 1
Sector 1 to 14 at Side 1
Sector 1 to 7 at Side 1
NC
NC
R+ 1
NC
1A
OF
08
Sector 26 at Side 1
Sector 15 at Side 1
Sector 8 at Side 1
C+1
LSB
R = 01
NC
0
R
1
Note: 1. NC (no Change): The same value as the one at the beginning of command execution.
2. LSB (Least Significant Bit): The least significant bit of H is complemented.
WRITE DATA
A set of nine (9) bytes are required to set the FOC into
the Write Data mode. After the Write Data command has
been issued the FOC loads the head (if it is in the unloaded
state), waits the specified, head settling time (defined in
the Specify Command), and begins reading 10 Fields. When
the current sector number ("R "), stored in the I 0 Register.
(lOR) compares with the sector number read off the
diskette, then the FOC takes data from the processor
byte-by-byte via the data blJs, and outputs it to the FOO.
After writing data into the current sector, the Sector
Number stored in "Ru is incremented by one, and the
next data field· is written into. The FOC continues this
"Multi-Sector Write Operation" until the issuance of a
Terminal Count-signal. If a Terminal Count signal is sent
to the FOC it continues writing into the current sector
to complete the data field. If the Terminal Count signal
is received while a data field is being written then the
remainder of the data field is filled with 00 (zeros!.
6-15
UM8272A /UM8272A.4
The F DC reads the I D field of each sector and checks
the CRC bytes. If the FDC detects a read error (Incorrect CRC) in one of the ID Fields, if sets the DE (Data
Error) flag of Status Register 1 to a 1 (high), and terminates the Write Data Command.
(Status Register 0
also has bits 7 and 6 set to 0 and 1 respectively.)
The Write Command operates in much the same manner
as the Read Command. The Following items are the
same; refer to the Read Data Command for details:
•
•
•
•
•
•
Transfer Capacity
EN (End of Cylinder) Flag
ND (No Data) Flag
Head Huload Time Interval
ID Information when the proces.sor terminates command (see Table 1)
Definition of DTL when N = 0 and when N *0
In the Write Data mode, data transfers between the processor and FDC must occur every 31 J1S in the FM mode,
and every 15 J1S in the MF M mode. I f the time interval
between data transfers is longer than this then the FDC
sets the OR (Over Run) flag in Status Register 1 to a 1
(high), and terminates the Write Data Command.
For Mini-floppies, multiple track writes are usually not
permitted. This is because of the turn-off time of the
erase head coils-the head switches tracks before the
erase head turns off. Therefore the system shou Id typically
wait 1.3 mS before attempting to step or change sides.
WRITE DELETED DATA
This command is the same as the Write Data Command
except a Deleted Data Address Mark is written at the
beginning of the Data Field instead of the normal Data
Address Mark.
READ DELETED DATA
This command is the same as the Read Data Command
except that when the FDC detects a Data Address Mark
at the beginning of a Data Field (and SK = 0 (low). it will
read all the data in the sector and set the CM flag in Status
Register 2 to a 1 (high). and then terminate the command.
If SK = 1, then the FDC skips the sector with the Data
Address Mark and reads the next sector.
READ A TRACK
This command is similar to READ DATA Command
except that the entire data field is read continuously
from each of the sectors of a track. I mmediately after
encountering the INDEX HOLE the FDC starts reading
all data fields on the track as continuous blocks of data.
If the FDC finds an error in the ID or DATA CRC check
bytes, it continues to read data from the track. The FDC
compares the I D information read from each sector with
th~ value stored in the IDR, and sets the ND flag of Status
Register 1 to a 1 (high) if there is no comparison. Status
Register 1 to a 1 (high) if there is no comparison. Multitrack or skip operations are not allowed. with this command.
This command terminates when EaT number of sectors
have been read. If the FDC does not find an ID Address
Mark on the diskette after it encounters the INDEX HOLE
for the second time, then it sets the MA (missing address
mark) flag in Status Register 1 to a 1 (high), an and
terminates the command. (Status Register 0 has bits 7
and 6 set to 0 and 1 respectively.)
READ ID
The READ I D Command is used to give the present position of the recording head. The FDC stores the values
from the first I D Field it is able to read. If no proper
ID Address Mark is found on the diskette, before the
INDEX HOLE is encountered for the second time then
the MA (Missing Address Mark) flag in Status Register
1 is set to a 1 (high). and if no data is found then the ND
(No Data) flag is also set in Status Register 1 to a 1 (high)
and the command is terminated.
FORMAT A TRACK
The Format Command allows an entire track to be formatted.
After the INDEX HOLE is detected, Data is
written on the Diskette: Gaps, Address Marks, ID Fields
and Data Fields, all per the IBM System 34 (Double
Density) or System 3740 (Single Density). Format are
recorded. The particular format which will be written is
controlled by the values programmed into N (number of
bytes/sector), SC (sectors/cylinder), GPL (Gap Length),
and D (Data Pattern) which are supplied by the processor
during the Command Phase. The Data Field is filled
with the Byte of data stored in D. The ID Field for each
sector is supplied by the processor, that is, four data
requests per sector are made by the FDC for C (Cylinder
Number), H (Head Number), R (Sector Number) and
N (Number of Bytes/Sector). This allows the diskette to
be formatted with nonsequential sector numbers, if desired.
After formatting each sector, the processor must send
new values for C, H, R, and N to the UM8272A for each
sector on the track. The contents of the R Register is
incremented by one after. each sector is formatted, thus,
the R register contains a value of R + 1 when it is read
during the Result Phase. This incrementing and formatting continues for the whole track until the FDC encoiJnters the INDEX HO LE for the second time, whereupon it terminates the command.
6-16
(DUMC
UM8272A jUM8272A.4
If a FAULT signal is received from the FDD at the end
of a write operation, then the FDC sets the EC flag of
status Register 0 to a 1 (high), and terminates the command after setting bits 7 and 6 of Status Register 0 to 0
and 1 respectively. Also the loss of a READY signal at
the beginning of a command execution phase causes
Illand termination.
COlll·
Table 7 shows the relationship between N, SC, and GPL
for various sector si/es:
Table 9. Sector Size Reiationships
5~"
8" STANDARD FLOPPY
FM Mode
GPL 2
128 bytes/Sector ,00 12
128
00 10
01 06
256
02 04
512
1024
03 02
2048
04 01
07
10
18
46
D8
C8
09
19
30
87
FF
FF
12
10
08
04
OA
20
2A
80
CB
OC
32
50
FO
FF
FF
SC
GPL 1
GPL 2
Remarks
00
01
02
03
04
05
1A
OF
07
OE
1B
47
C8
C8
1B
2A
3A
8A
FF
FF
IBM Diskette 1
I BM Diskette 2
1A
OF
36
54
74
FF
4096
8192
05 02
06 01
OE
1B
35
99
C8
C8
IBM Diskette 2D
1024
2048
01
02
03
04
256
256
512
1024
2048
4096
Sector Size
128 bytes/Sector
256
512
1024
2048
4096
MFM Mode
GPL 1
N
Formlit·,
256
512
06
04
02
01
08
04
IBM Diskette 2D
FF
FF
MINI FLOPPY
Sector Size
N
01
01
02
03
04
05
SC
02
01
C8
Notes: 1. Suggested values of GPL in Read or write Commands to avoid splice point between data field and ID field of
contiguous sections.
2. Suggested values of GPL in formal command.
During the Command Phase of the Seek operation the
FDC is in the FDC BUSY state, but during the Ex'ecution
Phase it is in the NON BUSY state. While the FDC is in
the NON BUSY state, another Seek Command may be
issued, and in this manner parallel seek operations may
be done on up to 4 Drives at once.
If an FDD is in a NOT READY state at the beginning of
the command execution phase or during the seek operation, then the NR (NOT READY) flag is set in Status
Register 0 to a 1 (high), and the command is terminated.
Note that the UM8272A Read and Write Commands do
not have implied Seeks. Any R/W command should be
preceded by: 1) Seek Command; 2) sense Interrupt Status;
and 3) Read I D.
the contents of the PCN cou nter, and checks the status
of the Track 0 signal from the FDD. As long as the Track
o signal is low, the Direction signal remains 1 (high) and
Step Pulses are issued. When the Track 0 signal goes high,
the SE (SEEK END) flag in Status Register 0 is set to a
1 (high) and the command is terminated. If the Track
o signal is still low after 77 Step Pulses, have been issued,
the FDC sets the SE (SEEK END) and EC (EQUIPMENT
CHECK) flags of Status Register 0 to both 15 (highs), and
terminates the command.
The ability to overlap RECALIBRATE Commands to
multiple FDDs, and the loss of the READY signal, as
described in the SEEK Command, also applies to the
RECALIBRATE Command.
SENSE INTERRUPT STATUS
RECALIBRATE
An I nterrupt signal is generated by the FDC for one of
This command causes the read/write head within the
FDD to retract to the Track 0 position. The FDC clears
the following reasons:
6-17
CDUMC
UM8272A /UM8272A.4
1. Upon entering the Result Phase of:
a. Read Data Command
b. Read a Track Command
c. Read 10 Command
d. Read Deleted Data Command
e. Write Data Command
f. Format a Cylinder Command
g. Write Deleted Data Command
h. Scan Commands
2. Ready Line of FDD changes state
3. End of Seek or Recallbrate Command
4. During Execution Phase in the NON-DMA Mode
normal command operations and are easily discernbile
by the processor. However, interrupts caused by reasons
2 and 3 above may be uniquely identified with the aid of
the Sense I nterrupt Status Command. This command
when issued resets the interrupt signal and via bits 5, 6,
and 7 of Status Register 0 identifies the cause of the
interrupt.
Neither the Seek or Recalibrate Command have a Result
Phase. Therefore, it is mandatory to use the Sense interrupt Status Command after these commands to effectively terminate them and to provide verification of the
head position (PCN).
Interrupts caused by reasons 1 and 4 above occur during
Table 8. Seek, Interrupt Codes
Interrupt Code
Seek End
Bit 5
Bit 6
Bit 7
0
1
1
Ready Line changed
state, either polarity
1
0
0
Normal Termination
of Seek or Recal ibrate
Command
1
1
0
Abnormal Termination of
Seek or Recalibrate
Command
CAUSE
SPECIFY
The Specify Command sets the initial values for each of
the three internal timers. The HUT (Head Unload Time)
defines the time from the end of the Execution Phase of
one of the ReadMlrite Commands to the head unload
state. This timer is programmable from 16 to 240 ms in
increments of 16 ms (01 = 16 ms, 02 = 32 ms ... OF =
240 ms). The SRT (Step Rate Time) defines the time interval between adjacent step pulses. This timer is programmable from 1 to 16 ms in increments of 1 ms (F = 1
ms, E = 2 ms, 0 = 3 ms, etc.). The HlT (Head load Time)
defines the time between when the Head load signal
goes high and when the ReadMlrite operation starts. This
timer is programmable from 2 to 254 ms in increments of
2 ms (01 = 2 ms, 02 = 4 ms, 03 = 6 ms .... FE = 254 ms).
The step rate should be programmed 1 ms longer than
the minimum time required by the drive.
The time intervals mentioned above are a direct function of
the clock (ClK on pin 19), Times indicated above are for
an 8 MHz clock, if the clock was reduced to 4 MHz (minifloppy appl ication) then all time intervals are increased by
a factor of 2.
The choice of DMA or NON-DMA operation is made by
the NO (NON-DMA) bit. When this bit is high (ND = 1)
the NON-DMA mode is selected, and when NO = 0 the
DMA mode is selected.
SENSE DRIVE STATUS
This command may be used by the processor whenever
it wishes to obtain the status of the FDDs. Status Register
3 contains the Drive Status information.
INVALID
If an invalid command is sent to the FDC (a command not
defined above), then the FDC will terminate the command.
No interrupt is generated by the UM8272A during this
condition. Bit 6 and bit 7 (010 and ROM) in the Main
Status Register are both high ("1 ") indicating to the
processor that the UM8272A is in the Result Phase and the
contents of Status Register 0 (STO) must be read. When
the processor reads Status Register 0 it will find an 80H
Indicating and invalid command was received.
A Sense interrupt Status Command must be sent after a
Seek or Recalibrate interrupt, otherwise the FDC will
consider the next command to be an invalid Command.
In some applications the user may wish to use this command as a No-Op command, to place the FDC in a stand
by or no operation state.
6-18
(DUMC
UM8272A / UM8272A-4
Table 9. Status Registers
No.
Bit
Name
Symbol
Descriptions
No.
Bit
Name
a
07
STATUS REGISTER
IC
07 = 0 and 06 = 0
Normal Termination of Command, (NT). Command wa~ completed and properly executed.
Interrupt
Code
07 = 0 and D6 = 1
Abnomal Termination of Command, (AT). Execution of Command was started, but was not
successfu IIy completed.
06
STATUS REGISTER 1 (CaNT.)
01
Not
Writable
NW
Do
Missing
Address
Mark
MA
Os
Seek End
SE
When the FDC completes the
SEEK Command, this flag is
set to (high).
04
Equipment
Check
EC
03
Not Ready
NR
02
Head
Address
01
Unit Select 1
DO
Unit Select
HD
a
End of
Cylinder
Os
Data Error in
Data Field
DO
If the FOC detect a CRC error in
the data field then this flag is set.
04
Wrong
Cylinder
WC
When the FDD is in the not-ready
state and a read or write command is issued, th is flag is set.
If a read or write command is
issued to Side 1 of a single sided
drive, then this flag is set.
This flag is used to indicate the
state of the head at Interrupt.
This bit is related with the NO bit.
and when the contents of C on
the medium is different from that
stored in the IDR, this flag is set.
03
Scan Equal
Hit
SH
02
Scan Not
Satisfied
SN
During execution, the SCAN Command, if the condition of "equal"
is satisfied, this flag is set.
During executing the SCAN Command, if the FDC cannot find a
Sector on the cylinder which
meets the condition, then this
flag is set.
Dl
Bad
Cylinder
BC
This bit is related with the NO bit,
and when the content of C on the
medium is different from that
stored in the lOR and the content
of C is FF, then this flag is set.
Do
Misl>ing
Address
Mark in
Data Field
MD
When data is read from the medium, if the FDC cannot find a Data
Address Mark or Deleted Data
Address Mark, then this flag i~ set.
07
Fault
FT
This bit is used to indicate the
status of the Fault signal from
the FOD.
06
Write
Protected
WP
This bit is used to indicate the
status of the Write Protected
signal from the FDD.
Os
Ready
ROY
This bit is used to indicate the
status of the Ready signal from
the FOD.
04
Track
03
a
Drive Unit Number at Interrupt
When the FDC tries to access a
Sector beyond the final Sector
of a Cylinder, this flag is set.
Not used. This bit is always
(low).
a
Data Error
DE
When the FDC detects a CRC
error in either the 10 field or the
data field, this flag is set.
04
Over Run
OR
If the FDC is not serviced by
the main-systems during data
transfers, within a certain time
interval, this flag is set.
Not used. This bit always
No Data
NO
a (low.)
If a fault Signal is received from
the FDD, or if the Track Signal
fails to occur after 77 Step Pulses
(Recalibrate Command) then
this flag is set.
Os
02
Not used. This bit is always
During executing the READ
DATA or SCAN Command, if
the FOC encounters a Sector
which contains a Deleted Data
Address Mark, this flag is set.
usa
03
STATUS REGISTER 2
07
CM
These flags are used to indicate a
06
If the FOC cannot detect the Data
Address Mark or Deleted Data
Address Mark, this flag is set.
Also at the same time, the MD
(Missing Address Mark in Data
Field) of Status Register 2 is set.
Control
Mark
US 1
EN
If the FOC cannot detect the 10
Mark after encountering
the Index hole twice, then this
flag is set.
D6
STATUS REGISTER 1
07
During execution of WRITE DATA
WRITE DELETED DATA or
Format A Cylinder Command, if
the FOC detects a write protect
signal from the FDD, then this
flag is set.
Addre~s
07 = 1 and 06 = 0
Invalid Command issue, (IC).
Command which was issued
was never started.
07 = 1 and 06 = 1
Abnormal Termination because
during command execution the
ready signal from FDD changed
state.
Descriptions
Symbol
a (low).
During execution of READ OAT A,
WRITE DELETED DATA or SCAN
Command, if the FDC cannot
find the Sector specified in the
lOR Register, this flag is set.
During executing the READ 10
Command, if the FDC cannot
read the 10 field without an
error, then this flag is set.
During the execution of the
READ A Cylinder Command, if
the starting sector cannot be
found, then this flag is set.
STATUS REGISTER 3
a
TO
Jhis bit is used to indicate the
status of the Track 0 signal from
the FOD.
Two Side
TS
This bit is used to indicate the
status of the Two Side signal from
the FOD.
D2
Head
Address
HD
This bit is used to indicate the status of Side Select signal to the FDD.
01
Unit Select 1
US 1
This bit is used to indicate the
status of the Unit Select 1 signal
to the FDD.
DO
Unit Select
a
USO
This bit ,is used to indicate the
status of the Unit Select 0 signal
to the FDD.
6-19
(l)UMC
UM8272A / UM8272A·4
A.C. Testing Input, Output Waveform
INPUT/OUTPUT
2.4---,""X
_ _ _J
0.45
::>
<
2.0
TEST POINTS
0.8
A.c. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1" AND
0.45V FOR A LOGIC "0". TIMING MEASUREMENTS ARE MADE AT 2.0V
FOR A LOGIC "1" AND O.BV FOR A LOGIC "0"
.A.C. Testing Load Circuit
DEVICE
UNDER
TEST
~CL
I
=
100pF
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
Waveforms
PROCESSOR READ OPERATION
jC
:I---t
A
O.CSJt
DACK
_
.
-t-A-R--~~~~~~~~-tR-R-----_-_-~~~..
DATA - - - - - - - - - -
tNT
6-20
R-A
.
UM8272A / UM8272A·4
Waveforms (Continued)
PROCESSOR WRITE OPERATION
DATA
tWI
~
-~--
INT
DMA OPERATION
tROCY
--------1
DRO
tRORW - - - - - 1
WR or RD
CLOCK TIMING
ClK
6-21
UM8272A / UM8272A·4
Waveforms (Continued)
FDD WRITE OPERATION
WRITE CLOCK
(WCK)
WRITE ENABLE
(WE)
PRESHIFTOor 1
(PS O,l)
WRITE DATA
(WDA)
PRESHIFT 0 PRESHI FT 1
NORMAL
0
0
LATE
0
1
EARLY
1
0
INVALID
1
1
SEEK OPERATION
OsO"~
STABLE
'so
'os
]1----
LCT/
DIRECTION _ _ _ _ _ _ _ _,
STEP
' - - - - - - - - tsc
6-22
(l)UMC
UM8272A / UM8272A·4
Waveforms (Continued)
INDEX
FLT RESET
FDD READ OPERATION
READDA~
~
-------------I~-.=====-t-W-R-D--------~
~ t:~DW---------
READ DATA
WINDOW
tWWCy-----------...j
TERMINAL COUNT
RESET
TC_~tTC~_
X ~
_ / ~ tRST~ ' \ -
RESET
Ordering Information
Part Number
Operation Clock
Package
UM8272A - 4
4 MHz
Plastic
UM8272A
8 MHz
Plastic
6-23
ClUMC
:=::::::::::::
UM9228-1
Floppy Data Separator
Features
•
Floppy Data Separator
Performs complete data separation function with a
little external circuit for floppy disk drives
Separates MFM encoded data
5%" double density compatible
•
Early and late 250 ns write precompensation
•
External 16 MHz clock required
•
Compatible with the FOC 765A (8272A) floppy disk
controllers
• DMA inte"rface logic
• CMOS technology
• .Single + 5 Volt supply
• TT L compatible
• For IBM PC disk drives especially
General Description
The UM9228-1 is an CMOS integrated circuit desi~ned to
complement the 765A (8272A) type of floppy disk controller chip; especially for IBM PC. It incorporates a data
separator, write precompensation logic, and DMA interface
logic. A -FDC 765A together with UM9228-1 and some
Pin Configuration
RO
PFDR
Vec
buffers qrive and decoder can be formed a I BM PC diskette
adapter. The UM9228-1 operates from a +5 Volt supply
and simply requires a 16 MHz external clock input. All
input and output are TT L compatible. The UM9228-1 is
available for 5%" double density disk controller.
Block Diagram
VCO
SYNC
ClKIN
FClK
PFDV
SO
WRITE
DATA
TIMING
ORO
I-+--+-~
&
LATCH
VCOIN
OW
lATE
OACK
OROOUT
Vss
EARLY
L--r----------------_.~
WO
~--------------_.'(DRQOUT)
)----...~.:.;,:......:.:.J
- - - - - - - - - - - - - -
6-24
EXTERNAL CIRCUIT
UM9228-1
*Comments
Absolute Maximum Ratings*
Stress above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only. Functional operation of this device at these or
any other conditions above those indicated in the operational sections of this specification is not impl ied and exposure to absolute maximum rating conditions for extended periods may affect the device reliability.
Ambient temperature under bias, T A . . . . .. 0 to + 70°C
Storage temperature, T STG . . . . . . . . ..
-55 to + 125°C
Applied voltage on any pin with respect to ground
. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to + SV
Power dissipation, Po . . . . . . . . . . . . . . . . . . . . . 0.5W
D.C. Electrical Characteristics
(T A = 0 to 70°C, Vee = 5V ± 5% unless otherwise specified.)
Parameter
Test Conditions
Input Voltage
low level V IL
High level V IH
Limits
Min.
Typ.
-0.3
2.0
Standby Current 1ST
I nput Current
(for all input)
low level IlL
High level IIH
V IH = 2.7V
V IL = O.4V
Output Current
(for all input)
low level IOL
High Level IOH
VO L =O.4V
VOH = 4.5V
Power Supply
Current lee
Max.
Units
O.S
Vee
V
V
10
f.1A
-200
20
f.1A
f.1A
mA
f.1A
4
-500
ClKIN = 16 MHz
VCOIN = 4 MHz
10
mA
I nput leakage
Current IlL
10
f.1A
I nput Capacitance CIN
10
pF
A.C. Electrical Characteristics
(T A = 0 to 70°C, Vee = 5V ± 5%, ClK IN = 16 MHz, VCOIN = 4 MHz)
Parameter
Min.
Limits
Typ.
Max.
Units
ClKI N frequency
1
16
MHz
VCOIN frequency
0
4
MHz
VCOIN DUTY CYCLE
30
50
ORO to DROOUT Delay tdORQ
70
%
2.0
f.1S
tweLKH
250
ns
tWOOUT
250
ns
200
0
tdWOIN
ns
tWOE
250
ns
tWON
250
ns
tWDL
250
ns
6-25
(l)UMC
UM9228-1
Precompenl8tion
FClK
WClK
4MHz
EJ
---------.--~
~
-------~--.~i--------------------------
tWClKH
500 KHz.
WDIN'
tWDOUT
Application Circuits
EN DRIVER
24
23
VCO
VCO SYNC
ROD
SO
lCT/DIR
38
FDC
31
8272A (765A)25
/UM8272A
30
lCT/DIR
PSI
lATE
WE
WTEN
WR DATA
ORO
14
20
RD
12
RAW
DATA
L--.Q
DIR
----9
WDOUT
DIR
-[>0
FDD
WDATD
8
11
WD
10
ORO_
DACK
(from DMAC)
1
5
EARLY
PSO
32
d
3
.
16
DATA
14
SEPARATOR
15
DROOUT
ACK
DMAC
VCC~
UM9228·1
ROW
22
21
19
WR ClK
-
OW
WClK
~
ClK
FClK
17
2
18
4
PFDR
R
PFDV
...
•
o
MC 4044 AIN
t=
PO
VF
L--
PV
OF
4
ClKIN
AOUT
19
13
l
6
VCOIN FOUT
U
1
2K
2
4
3
6-26
,A
F CONTl
8
MC4024
VSS
470
V
13
r - - VI
2
16MHz
t
7
_~82P
0.047u
v
3.3K
II---<
SUMC
UM9228·1
Pin Description
Pin No.
Symbol
I/O
Descriptions
1
RD
I
Read Data: Data read from FDD.
2
PFDR
0
Reference Data Sample Pulse. This signal is applied to
the reference input of a PLL circuit. See block diagram.
3
Vee
I
+5 Volt power supply
4
PFDV
0
This output is connected to an input of a PLL circuit.
See block diagram.
5
SO
0
Separate Data: This 'output is the generated data pulse
derived from the RD input.
6
VCOIN
I
This signal is the V.C.O. 0l:ltput of a PLL circuit used
to generate data window.
7
OW
0
Data Window: This is derived from RD input to be applied
to FDC.
8
LATE
I
See Fig. 3.
9
EARLY
I
See Fig. 3.
10
WD
I
Write Data: The write data stream from the floppy disk
controller.
11
WEN
I
Write Enable: This input is from FDC starting the write
operation.
12
WDOUT
0
Write Data Output: The precompensated write data stream
to the drive.
13
Vss
I
Ground
14
DROOUT
0
Data Request Output: This is delayed ORO signal from
FOC.
15
DACK
I
DMA Acknowledge: This is direct memory access
acknowledge from OMA controller.
16
ORO
I
OMA Request: This is high when FOC make a OMA request.
17
WCLK
0
Write Clock: This signal is the write clock to the floppy
disk controller.
18
FCLK
0
FOC Clock: This output is the master clock to the floppy
disk controller.
19
CLKIN
0
Clock Input: This input is connected to a external 16 MHz
clock input.
20
VCC SYNC
I
This is connected to VCO output pin of FOC 765.
6-27
UM9228-1
Operational Description
DATA SEPARATOR
UM9228-1 is used with a external PLL circuit (see fig. 1) to detect the leading edges of the disk data pulse and adjust the
phase of the internal clock to provide the data window (OW) clock.
Fig. 1: Data Window Generator
The data window clock frequency is normally 250 KHz. See fig. 2.
bit cell
Data Pulse
from FDD
Data Window
MFM TYPE
Fig. 2: Data Window
TIME BASE LOGIC
It compromises 5 stages of ripple counter and a duty cycle clamping circuit. The write clock (WCLK) duty cycle is 1/S.
Ext. Clock
16MH~--------
-- -
-
-- -- ----
-------llfLIUL
lMHW
500KHW:...-----~===:~~~~~.,I
......- - - - - - - - - - -......
WCLK~______________________~I
1/8
DUTY CYCLE.
500 KHz
-I
250ns
~
WRITE PRECOMPENSATION
The desired precompensation delay (250 ns) is determined by the state of EAR L Y and LATE inputs of UM922S-1.
Nominal
Late
Early
Invalid
Early
0
0
1
1
Late
0
1
0
1
Fig. 3: Write Precompensation State
DMA INTERFACE
~
DRQ~________~----------------------------:----~f~~
______________
~'1L...__ _ _ __
DRQOUT,_ _ _ _ _ _ _ _ _ _ _ _ _....
J~L...__
_ _ __
DACK
Fig. 4: DMA Interface Timing
When requiring data read/write, FOC will check OACK from OMAC and will set ORO (low to high) if OACK is high.
The DMA I nterface delay ORO from FOC by 4 stage shift register as the timing shown above. This delay will prevent cpu
from being busy doing OMA without adequate system operation.
6-28
eUMC
UM8326/8326B
"""" '.I,,',,:::,,,;,,,,.,,,::,,!,,,,,:,:, "",":' "'!,
Floppy Disk Data Separator (FDDS)
Features
•
•
•
Performs complete data separation function for floppy
•
No critical adjustments required
disk drives
•
Compatible with standard microsysterns' F DC 1791,
media
•
Small 8-pin dual-in-line package
Eliminates several SSI and MSI devices normally used
•
+5 Volt only power supply
for data separation
•
TTL compatible inputs and outputs
Separates F M or MF M encoded data from any magnetic
FDC 1793 and other floppy disk controllers
General Description
The Floppy Disk Data Separator provides a low cost
package to save board real estate, the FDDS operates on
solution to the problem of converting a single stream of
+5 volts only and is TTL compatible on all inputs and
pulses from a floppy disk drive into separate clock and
outputs.
data inputs for a Floppy Disk Controller.
The UM8326 is available in two versions; the UM8326,
The FDDS consists primarily of a clock divider, a long-term
which is intended for 514" disks and the UM8326B for
timing corrector, a short-term timing corrector, and re-
514" and 8" disks.
clocking circuitry.
Sypplied in an 8-pin Dual-in-Line
Pin Configuration
Block Diagram
REFCLK
vDD
CDO
CDl
SEPD
--
-
CLOCK
DIVIDER
- + 5V
- GND
~
CDl
CDO
DSKD
-
EDGE
DETECTIOI\
LOGIC
U
6-29
DATA/CLOCK
SEPARATION
LOGIC
'---
r---
,.
PULSE
REGENERATION
LOGIC
~
SEPCLK
-
SEPD
UM8326/8326B
Absolute Maximum Ratings*
Operating Temperature Range . . . . . . . . . . OOC to + 70°C
Storage Temperature Range . . . . . . . . -55°C to + 150°C
Positive Voltage on any Pin, with respect to ground
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Negative Voltage on any Pin, with respect to ground
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V
Note:
When powering this device from laboratory or system
power supplies, it is important that the Absolute Maximum
Ratings not be exceeded or device failure can result. Some
power supplies exhibit voltage spikes or "glitches" on their
outputs when the AC power is switched on and off. In
addition, voltage transients on the AC power line may
appear on the DC output. I f this possibility exists it is
suggested that a clamp circuit be used.
*Comments
Stresses above those listed may cause permanent damage
to the device. This is a stress rating only and functional
operation of the device at these or at any other condition
above those indicated in the operational sections of this
specification is not implied.
Electrical Characteristics
D.C. CHARACTERISTICS (T A = OoC to 70°C, Voo = +5V ± 5%, unless otherwise noted)
Parameter
Min.
Typ.
Max.
Units
Conditions
INPUT VOLTAGE LEVELS
Low Level V IL
0.8
High Level VIH
2.0
V
V
OUTPUT VOLTAGE LEVELS
Low Level VOL
0.4
High Level VOH
2.4
V
IOL = 1.6 mA
V
IOH = -1001lA
INPUT CURRENT
Leakage IlL
10
IlA
10
pF
60
mA
Max.
Units
O~VIN ~Voo
INPUT CAPACITANCE
All Inputs
POWER SUPPLY CURRENT
100
A.C. CHARACTERISTICS
Symbol
Parameter
Min.
Typ.
Conditions
fCY
REFCLK Frequency
0.2
4.3
MHz
UM8326
fCY
REFCLK Frequency
0.2
8.3
MHz
UM8326B
tCKH
REFCLK High Time
50
2500
ns
tCKL
REFCLK Low Time
tSOON
REFCLK to SEPD "ON" Delay
100
tSOOFF
REFCLK to SEPD "OFF" Delay
100
tSPCK
REFCLK to SEPCLK Delay
tOLL
DSKD Active Low Time
tOLH
DSKD Active High Time
I
2500
50
ns
ns
ns
100
ns
0.1
100
Ils
0.2
100
Ils
6-30
UM8326/83268
Pin Description
Pin No.
Name
1
Disk Data
2
Function
Symbol
DSKD
Data input signal direct from disk drive. Contains combined
clock and data waveform.
Separated Clock
SEPCLK
Clock signal output from the FDDS derived from floppy disk
drive serial bit stream.
3
Reference Clock
REFCLK
4
Ground
GND
Ground
Clock Divisor
COO
COl
COO and COl control the internal clock divider circuit. The
internal clock is a submultiple of the REFCLK according to
the following table:.
5,6
Reference clock input
7
Separated Data
SEPD
8
Power Supply
VDD
--
Divisor
COO
COl
1
2
0
1
0
-1
0
0
1
1
4
8
SEPD is the data output of the FDDS
+5 volt power supply
Operational Description
Separate short and long term timing correctors assure
accurate clock separation.
A reference clock (REFCLK) of between 2 and 8 MHz is
divided by the FDDS to provide an internal clock. The
division ratio is selected by inputs ICDO and COl. The
reference clock and division ratio should be chosen per
table 1.
The F DDS detects the leading edges of the disk data
pulses and adjusts the phase of the internal clock to provide
the SEPARATED CLOCK output.
The internal clock frequency is nominally 16 times the
SEPCLK frequency.
Depending on theinternal timing
correction, the internal clock may be a minimum of 12
times to a maximum of 22 times the SEPCLK frequency.
The reference clock (REFCLK) is divided to provide the
internal clock according to pins COO and COl.
Table 1. Clock Divider Selection Table
Drive
(8" or 5%")
Density
(DO or SO)
REFCLK
MHz
CD1
COO
8
8
8
'00
8
8
0
0
0
SO
SO
4
0
5%
5%
5%
5%
5%
DO
8
DO
4
SO
8
0
0
1
0
1
SO
4
0
1
SO
2
a
a
6-31
1
a
0
Remarks
}
}
}
Select either one
Select either one
Select anyone
UM8326/8326B
Timing Diagram (1)
INTCLK
SEPCLK.-J
U
:
u
I
u
I4----.l
I
I
always two internal clock cycles
Timing Diagram (2)
REFCLK
---r
SEPCLK __________________________________________________________
\='OLL
DSKD __________________
Typical System Configuration
'OLH
1\.____________________
(5%" Drive, Double Density)
4 MHz CRYSTAL
DSCILLATOR
1 MHz
REFCLK
FLOPPY
DISK
DRIVE
DISK DATA
DERIVED CLOCK
CDO CD1
GND GND
6-32
-'-~---
UM8326/83268
Comparison of Data Separator (UM9228·1, UM8329, UM8326)
PINOUT'COMPARISON
Function
UM8329
UM9228-1
Power Supply:
Vee
Vss
Pin
Precompensation:
EARLY
LATE
Amount Control
Pin 20 Vee
10 Ground
3 Vee
13 Vss
9 EARLY
8 LATE
------
13
14
17
18
19
-----------
Read Data:
From FDD
To
FDC
Data Row
1 RD
5 SO
7 OW
Write Data:
From FDC
To
FDD
Write Enable
Write Clock
179X!765MODE
Density
MASTER CLK to FDC
10 WD
12 WDOUT
11 WEN
17 WCLK
---------------18 FCLK
EARLY
LATE
PO
P1
P2
UM8326
Pin 8 VDD
4 GND
---------------------
1 DSKD
7 SPED
2 SEPCLK
12 WDIN
7 WDOUT
--------------------5 COO
6 COl
-----------
9
2
3
4
8
CLKOUT
FDCSEL
MINI
DENS
H LT /CLK
Extermal Clock I/P
19 CLKIN
11 XTAL/CLKIN
3 REFCLK
TEST
------
16 TEST
------
179X/MODE ESP
------
15 HLD
------
DMA
16 ORO
15 BACK
14 DROO/P
-----------
-----------
------
------
2 PROR
4 PFDV
6 VCOIN
------
------
------
------
------
------
20 VCOSNC
------
------
VFO
VCO SYN
See B
------
1 DSKD
6 SPED
5 SEPCLK
------
Remarks
Sec C
See 0
See E
See F
TIME PRECOMPENSATION
It is a more advanced function to solve "peak Shift"
problem.
UM922S-1 defines compensation time to be
250ns according to IBM PC design. UMS329's compensation time is programmable, yet UMS326 does not have this
function.
and to interface different F DCs; but UM922S-1 is especially used in 5% FDD (MFM coding) interface.
DMA MODE
UM922S-1 can accept DMA request and d.efine the delay
time between two different DMA requests to be 5 /-lS to
guarantee system can work norm~lIy.
WRITE DATA
UM922S-1 and UMS329 have write data function in IC, but
, UMS326 does not; and UM922S-1 has t.he "write enable"
pin to guarantee write function unfail.
MODE SE LECT
VFO CIRCUIT
Because UM922S-1 does not have VFO and PLL circuit,
user must combine MC4024 and MC4044 to build a
complete data separator. Please see UM922S-1 application
circuit intensively.
.
UMS329 and UMS326 allow user to select different FDCs
Ordering Information
Part Number
Frequency Option
Package Type
UMS326
4MHz
Plastic
UMS326B
SMHz
Plastic
6-33
SUMO
UM832918329T 18329BI8329BT
Features
•
•
•
Digital date separator
Performs complete data separation function for
floppy disk drives
Separates FM and MFM encoded data
No critical adjustments necessary
5%" and 8" compatible
Variable write precompensation
I nternal crystal osci lIator circu it
•
•
•
•
•
•
Track-selectable write precompensation
Retriggerable head-load timer
Compatible with the FDC 179X, 8272A, and other
standard floppy disk controllers
SAN-III MOS N-CHANNEL TECHNOLOGY
Single + 5 volt supply
TTL compatible
General Description
UM8329/B operates from a +5V supply and simply requires
that a 16 or 8 MHz crystal or TT L-Ievel clock be connected
to the XTAL/CLKIN pin. All inputs and outputs are TTL
compatible.
The UM8329/B is an MOS integrated circuit designed to
complement either the 179X or 8272A (765A) type of
floppy disk controller chip. It incorporates a digital data
separator, write precompensation logic, and a head-load
timer in one O.3-inch wide 20-pin package. A single pin will
/ configure the chip to work with either the 179X or 8272A
type of controller. The UM8329/B provides a number of
different dynamically selected precompensation values so
that different values may be used when writing to the
inner and outer tracks of the floppy disk drive. The
Pin Configuration
DSKD
FDCSEl
Block Diagram
VCC
P2
MINI
Pl
DENS
PO
SEPClK
SEPD
WDOUT
TEST
HlD
lATE
Hl T/ClK
EARLY
ClKOUT
WDIN
GND
The UM8329 is available in four versions: The UM8329/T
are intended for 5%" disks and the UM8329B/T for 5%"
and 8" disks. The UM8329/B have an internal crystal
oscillator circuit; the UM8329T IBT require an external
clock.
XTAl/
ClKIN
6-34
UM8329/8329T 183298/83298 T
Absolute Maximum Ratings*
Comments*
Operating Temperature Range .......... OOC to + 70°C
Storage Temperature Range ........ -55°C to + 150°C
Positive Voltage on any I/O Pin, with respect to ground ...
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Negative Voltage on any I/O Pin, with respect to ground
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 0.75W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated .in the operational sections of this specification
is not implied and exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note: When powering this device from laboratory or
system power supplies, it is important that the Absolute
Maximum Ratings not be exceeded or device failure can
result. Some power supplies exhibit voltage spikes or
"glitches" on their outputs when the AC power is siwtched
on and off. In addition, voltage transients on the AC power
line may appear on the DC output.
Electrical Characteristics
(T A = ooc to 70°C, Vee = 5V ± 5%)
Parameter
D.C. Characteristics
INPUT VOLTAGE
Low Level VIL
High Level VIH
XTALlCLKIN INPUT VOLTAGE
Low Level
High Level
OUTPUT VOLTAGE
Low Level VOL
High Level VO H
Max.
Units
-0.3
2.0
0.8
(Vee)
V
V
-0.3
2.4
0.8
(Vee)
V
V
0.4
V
Min.
Typ.
V
2.4
POWER SUPPLY CURRENT
Icc
INPUT LEAKAGE CURREN
IlL
INPUT CAPACITANCE
CIN
Electrical Characteristics
Parameter
XT A LlC LK I N Duty Cycle
telKOH
tWdO
td
tdNEe
tWdE
tWdN
tWdL
ts
mA
10
p.A
pF
pF
10
25
Except XTAL/CLKIN
.
IOL
IOL
IOH
IOH
= 1.6 mA except H LT /CLK
= 0.4 rnA, H LT /CLK only
= -100 p.A except HLT/CLK
= -400p.A. HLT/CLK only
VIN =Oto Vee
Except ClKIN
ClKIN only
(T A = OoC to 70°C, Vee = 5V ±5%)
Min.
A.C. Characteristics
XTALlCLKIN Frequency
100
Conditions
Max.
Typ.
Conditions
Units
All times assume C lK I N = 16 MHz unless otherwise specified)
3.95
3.95
25
465
215
90
280
50
0
500
16
8
500
250
125
312.5
562.5
16.2
8.1
75
515
265
140'
350
400
400
625
MHz
MHz
%
ns
ns
ns
ns
ns
ns
ns
p.s
1.0
6-35
UM8329B
UM8329T
FDCSE l = low; MINI = high.
FDCSEl = low; MINI = low.
FDCSE l = high.
Time Doubles with MINI = 1
9 clock times ± 1 clock time
See fig. 2
See fig. 2
UM832918329T 183298/83298 T
A.C. ,Timing Characteristics
WDOUT PU LSE WI DTH
HLT/CLK (8272A MODE)
1
-i= 'WDO~---
--...01'/
1-4-----
4 or 8 MHz
CLKOUT VS. WDIN TIMING
179X MODE
~
CLKOUT
,~------~;---
/
~ j,..-.------,~------
------------SS.
WDIN
8272A(765A) MODE
CLKOUT~
l-,2_,_or_4_u_se_c,_ _ __
, _
tdNEC
WDIN _ _ _ _ _ _ _ _ _ _ _ _ _ __
SET-UP TIME PO, Pl AND P2 TO WDIN
PO,Pl,P2
WDIN
t
CLKOUT
CLKOUT~
I---
{
ts
~_ _ __
tCIKOH
----I.
PRECOMPENSATION
CLKOUT
(179X)
CLKOUT
(8272A)
tWDE
WDOUT (EAR L Y) _ _-'I
""'1
WDOUT (NOMINAL) _ _--1_ _ _
tWDL ~_ _ _ _ _ _ _ _, WDOUT (LATE)
Ref, to Fig, 2 for
tp (prtlcompensation)
value
6-36
UM8329 18329 T 183298 183298 T
Pin Description
Descriptions
Symbol
I/O
1
DSKD
I
This input is the raw read data received from the drive. (This input is
active low.)
2
FDCSE L
I
This input signal, when low programs the UM8329/B for a 179X type of
LSI controller. When FDCSE L is high, the UM8329/B is programmed for a
8272A (765A) type of controller. (See fig. 4.)
1
The state of this input determines whether the UM8329/B is configured
to support 8" or 5%" floppy disk drive interfaces. It is used in conjunction
with the DENS input to prescale the clock for the data separator. The
state of this input also alters the CLKOUT frequency, the precompensation
value, the head load delay time (when in 179X mode) and the HLT/CLK
frequency (when in 8272A mode). (See figs. 2, 3, and 4.)
The state of this input determines whether the UM8329/B is configured to
support single density (FM) or double density (MFM) floppy disk drive
interfaces. It is used in conjunction with the MINI input to prescale the clock
for the data separator. The state of this input also alters the CLKOUT
frequency when in the 8272A mode. (See figs. 2, 3, and 4.)
Pin No.
3
MINI
I
4
DENS
I
5
SEPCLK
0
A square-wave window clock signal output derived from the DSKD input.
6
SEPD
0
This output is the regenerated data pulse derived from the raw data input
(DSKD). This signal may be either active low or active high as determined
by FDCSE L (pin 2).
7
WDOUT
0
The precompensated WR ITE OAT A stream to the drive.
0
When in the 8272A mode (FDCSEL high), this output is the master clock to
the floppy disk controller. When in the 179X mode, this signal goes high
after the head load delay has occured following the HLD input going high.
This output is retriggerable. (See fig. 3.)
0
This signal is the write clock to the floppy disk controller. Its frequency
is determined by the state of the MINI, DENS, and FDCSEL input pins.
(See fig. 3.)
This input is for direct connection to a 16 MHz or 8 MHz crystal UM8329/B
()nly). The other pin of the crystal is grounded. XTAL/CLKIN may alternatively be connected to a single-phase TTL-level clock. The UM8329T and
BT require an external TTL-level clock.
)
8
HLT/CLK
9
CLKOUT
10
GND
Ground
11
XTAL/CLKIN
I
12
WDIN
I
The write data stream from the floppy disk controller.
I
When this input is high, the current WR ITE DATA pulse will be written
early to the disk.
13
EARLY
14
LATE
I
When this input is high, the current WRITE DATA pulse will be written
late to the disk.
When both EAR L Y and LATE are low, the current WRITE DATA pulse
will be written at the nominal position.
15
HLD
I'
This input is only used in 179X mode. A high level at this input causes a
high level on the H LT /CLK output after the specified head-load time delay
has elapsed. The delay is selected by the state of the MI N I output. (See
fig. 3.)
16
TEST
I
This input (when low) decreases the head-load time delay and initializess the
data separator. This pin is for test purposes only. This input has an internal
pull-up resistor and should be tied high or disconnected for normal operation.
17
PO
I
18
P1
I
19
P2
I
20
Vee
P2-PO select the amount of precompensation applied to the write data. (See
fig. 2.)
+5 VOLT SUPPLY
6-37
--
UM8329/8329T 183298/83298 T
OperationaL Description
INTCLK
SEPCLK
---.J
I
SEPD*----------~L-J
:
LJ
LJ
:
I
~
*polarity of SEPD shown for FDCSEL= low.
alw'ays two internal clock cycles
DATA SEPARATOR
The XTAL/CLKIN input clock is internally divided by the
UM8329/B to provide an internal clock. The division ratio
is selected by the FDCSEL, MINI and DENS inputs depending on the type of drive used. (See fig. 1.)
The UM8329/B detects the leading (negative) edges of the
disk data pulses and adjusts the phase of the internal clock
to provide the SE PC LK output.
Separate short- and long-term timing correctors assure accurate clock separation.
The SEPCLK frequency is nominally 1/16 the internal clock
frequency. Depending on the internal timing correction,
the duration of any SEPCLK half-cycle may vary from a
nominal of 8 to a minimum of 6 and a maximum of 11
internal.clock cycles.
FDCSEL
'0
0
0
0
1
1
1
1
Inputs
DENS
MINI
O'
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
Note:
Pl
PO
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
1
1
MINI
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
1
1
0
1
0
1
Note:
P2
0
DENS
2
4
4
8
4
8
2
4
Fig. 1.
Outputs
Inputs
FDCSEL
f(XTAL/CLKIN)
/f(lNTCLK)
PRECOMPENSATION
The desired precompensation delay is determined by the
state of the PO, P1 and P2 inputs of the UM8329/B as per
fig. 2. Logic levels present on these pins may be changed
dynamically as long as the inputs are stable during the time
the floppy disk controller is writing to the driver and the
inputs meet the minimum setup time with respect to the
write data from the floppy disk controller.
MINI
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
HEAD LOAD TIMER
The head load time delay is either 40 msor 80 ms, depending on the state of MINI. (See fig. 3.) The purpose of this
delay is,to ensure that the head has enough time to engage
properly. The head load timer is only used in the 179X
mode; it is non-functional in the 8272A mode.
The FDC 179X initiates the loading of the floppy disk drive
head by setting H LD high. The controller then waits the
programmed amount of time until the H LT signal from the
goes high' before starting a read or write operation
UM8329/B.
CLKOUT
2
1
2
1
MHz
MHz
MHz
MHz
500 KHz
250 KHz
1 MHz
500 KHz
HLT/CLK
40
80
40
80
8
4
8
4
ms*
ms*
ms*
ms*
MHz
MHz
MHz
MHz
All values shown are obtained with a 16 MHz
reference clock. Divide all frequencies and mUltiply all periods by two for 8 MHz operation.
*May be mask programmed at factory to any value from 1
to 512 min is 15.625 jJ.S increments (MINI low) or 1 to
1024 nis in 31.25 jJ.S increments (MINI high).
Fig. 3. Clock and head load time delay selection
Precomp Value
o ns
62.5 ns
125 ns
187.5 ns
250 ns
250 ns
312.5 ns
312.5 ns
o ns
125 ns
250 ns
375 ns.
500 ns
500 ns
625 ns
625 ns
Inputs
FDCSEL DENS MINI
All values shown are obtained with a 16 MHz reference clock. Multiply pre-comp values by two
for 8 MHz operation.
0
0
0
0
0
0
1
1
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
Floppy
Disk
Drive
Type
Floppy
Disk
Drive
Density
8" Drive Double
5%" Drive Double
8" Drive
Single
5%" Drive Single
Floppy
Disk
Controller
Type
179X
179X
179X
179X
8" Drive
Single 8272A
5%" Drive Single 8272A
8" Drive Double 8272A
5%" Drive Double 8272A
(765A)
(765A)
(765A)
(765A)
Fig. 4 Floppy disk. drive and controller selection
Fig. 2 Write precompensation value selection
6-38
UM8329 18329 T 183298/83298 T
Typical System Implementation - 8272A (765A) FOe
16 MHz
ROY
lOY
LATCH
WE
00-07
SIOESEL
1 - - - - - - - - - - - - - - - - - -....... MOTOR
* The UM8329T/BT, as all other Nry10S integrated circuits, presents a high impedance
on all inputls.
To avoid soft errors caused by transmission line effects and noise where there is long
cabling between the floppy dis~ drive and the controller board, the use of a (noninvertingl
TTL schmidt-trigger input gate or bus transceiver is recommended at the OSKO input to
the UM9229/B.
6-39
ON
UM8329 18329 T 183298/83298T
Typical System Implementation - 179X FDC
DRIVE
179X
TROO
WPRT
I.P.
READY
DIR
STEP
~
~
WG
00-07
INTRa
ORO
RE
WE
CS
Al
AD
RESET
W
HLD
~
L
OALO-OAL7
------
INTREO
ORO
lJi5EN
CS
Al
AO
MR
,---
WO
EARLY
LATE
TG43
CLK
HLO
UM8329
HLO
SEPO
OSKO
HLT/CLK
SEPCLK
FOC.SEL
RAWRO
HLT
RCLK
WE
TRKOO
WPRT
INDEX
READY
DIR
STEP
WRITE
GATE
DENS
MINI
WOIN
EARLY
WOOUT
TEST*
P2
LATE
P1
CLKOUT
PO
XTALlCLKIN
r--:±
~
~
RAW READ
WOATA
r----~V
~.r-
~~~
---
~---IIn--.......- - - -
C = 130 pF MAX, FDR DBO·DB7
C = 30 pF MAX. FOR ALL OTHER OUTPUTS
=
7-5
i
3kD
P'N
1
I100PF
SYNCHRONOUS MODE 7-BIT CHARACTER, NO PARITY
RxC
DCD --,~______________________________________________________________________________________________________________________
DSRI
•
c
I
n
~-----------------------------DTR
RxEN
-----,~___________________________________________________________________________________________________________________
---.J
LLL~ I
L~
RxD
U
-..J
I
en
1
n
CEIJ
WRITE ENABLE
READ SR
RECEIVER/SET 5TR
L~
I
I
Li
I LJ
I
I
I
I
~AT_A_1_ _ 1~TA_~
U
_
I
I
DATA 3
READ RxHR
DATA 1
I
I
L
I
I
I
I
I
I
DATA 4
READ RxHR
DATA 3
103
~
--------------~--~
I
I
I
I
I
DATA 5
u
READ RxHR
DATA 2
~
n
I
UU
READ SR
RxRDY
SYNDETECT
SR BIT 5
I
lJIJ
READ RxHR
DATA 4
READ RxHR
DATA 5
~~------------------------------
•
~-----------------------------------------------------------ASYNCHRONOUS MODE 7-BIT CHARACTER, NO PARITY, 1 STOP BIT
RxEN
---.J
_ _ _ _..,ti:
I~I
RxD
CEU
WRITE ENABLE
RECEIVER/SET 5TIi
RxRDY
MARK
DATA 1
I~I
DATA 2
U
READ RxHR
DATA 1
I II
U
READ RxHR
DATA 2
U
II
DATA 3
DATA 4
III
DATA 5
I ....
1..&..1_ __
U
READ RxHR
DATA 3
U
lJ
READ RxHR
DATA 5
DATA 4 LOST
c:
OVERRUN
SRBIT4 __________________________________________________________________________________________________________~
Figure 1. Receiver Operation Timing Diagram
!eft
...
eft
RxC (lX)
RTS ---,~______________________________________________________________________________________________~______________________
CTS)
•
c
I
n
----~--------------------------I
I
TxD
I
I
I
I
I
DATA 1
CEU
WRITE DATA 1
U
WRITE DATA 2
......
I
......
I
I
I
I
I
I
I
I
I
DATA 3
I
I
I
I
I
SYN 1
U
U
WRITE DATA 4
--
I
I
I
I
I
I
I
I
DATA 4
I
I
I
I
DATA 5
U
WRITE DATA 5
- - --- ---
-1________
--- --- -
u
---u-l....J
I
- [
WRITE DATA 3
TXEN..J
TxRDY
I
DATA 2
LJ
U
u
TxEMT
ASYNCHRONOUS MODE 7-BIT CHARACTER, NO PARITY, 1 STOP BIT
5:
Igl
TxD
CE]
WRITE DATA 1
TxEN
!!!!
DATAl
U
WRITE DATA 2
I~II
~
!
!
!
I
DATA 2
U
WRITE DATA 3
III
!
I
!
!
MARK
U
WRITE DATA 4
!!!
DATA 4
I
II
~-------------
U
WRITE FOR LE BREAK CMD
........J
TxEN
TxRDY
,
iI
DATA 3
L-J
n---------------------------------c:
TxEMT
!eft
Figure 2_ Transmitter Operation Timing Diagram
...
eft
•
RxC
c
I
n
RxEN OR
SR BIT 6 (DCD)
RxRDY
CE
r-
U-
READ
DATA N
U------READ
DATA N+l
11
READ
DATA N+2.
'-I
I
Figure 3. Asynchronous Receiver Operation with Loss of OeD or Disabling RxEN
00
RxC
RxD
FRAMINGERROR
SR BIT 5 ______________________________________________________
~
c:
BKDET
!
Figure 3.
Framing Error and Break Detection Timing
....
•••
UM266J.
Table 2. Baud Rate Generator Characteristics
2661-1 (BRCLK =4.9152 MHz)
MR2
3
2
1
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
a
a
a
a
,0
0
1
1
1
1
1
1
1
1
a
a
1
1
1
1
a
a
a
a
1
1
0
a
1
a
1
a
1
a
1
a
1
a
1
1
1
0
1
a
a
1
1
1
1
a
Baud Rate
Actual Frequency
16X Clock (KHz)
50
75
110
134.5
150
200
300
600
1050
1200
1800
2000
2400
4800
9600
19200
0.8
1.2
1.7598
2.152
2.4
3.2
4.8
9.6
16.8329
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2
Baud Rate
Actual Frequency
16X Clock (KHz)
45.5
50
75
110
134.5
150
300
600
1200
1800
2000
2400
4800
9600
19200
38400
0.7279
0.8
1.2
1.7598
2.152
2.4
4.8
9.6
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2
614.4
Baud Rate
Actual Frequency
16X Clock (KHz)
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
0.8
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8
Percent Error
-
-0.01
.
-
0.196
-0.19
-0.26
-
Divisor
6144
4096
2793
2284
2048
1536
1024
512
292
256
171
154
128
64
32
16
2661-2 (BRCLK =4.9152 MHz)
MR2
3
2
1
0
a
a
0
a
0
a
0
a
a
a
a
a
a
a
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
a
a
a
a
a
0
1
1
0
1
0
1
a
1
1
0
1
1
1
1
1
0
1
a
a
1
1
a
1
a
1
a
1
a
1
Percent Error
0.005
-
-0.01
-
-
-0.19
-0.26
-
-
Divisor
6752
6144
4096
2793
2284
2048
1024
512
256
171
154
128
64
32
16
8
2661-3 (BRCLK = 5.0688 MHz)
MR2
3
2
1
0
0
a
a
0
a
a
a
a
1
a
1
a
1
a
1
a
a
a
a
0
a
0
a
1
1
1
1
1
1
1
1
1
1
1
1
a
a
a
a
1
1
1
1
1
1
0
a
1
1
a
a
1
1
a
a
1
1
1
0
1
a
1
a
1
Percent Error
-
0.016
-
0.253
-;
-
3.126
Divisor
6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16
Note: 16X ClK is used in asynchronous mode, In synchronous mode, clock multiplier is 1 X and BRG can be used only
for T x C
7-9
(l)UMC
UM2661
Signal Descriptions
can be "wire OR-ed" to the CPU interrupt line.
CPU Interface
Transmitter/Receiver Signals
Reset (Reset)
A high on this input performs a master reset on the
UM266l.
This signal asynchronously terminates any
device activity and clears the mode, command and status
registers. The device assumes the idle state and remains
there until initialized with the appropriat~ control words.
Ao-, Al
(Address 0, 1)
Address lines used to select the internal registers.
RIW (ReadIWrite)
The direction of data transfers between the EPC I and the
CPU is controlled by the R/W input. When CE and R/W
are both low the contents of the selected registers will be
transferred to the data bus. With CE low and RIW high a
write to the selected register is performed.
CE (Chip Enable)
When low, the selected register will be accessed. When
high the 00-D7 lines will be placed in the high impedance
state.
DBo -DB7 (Data Bus)
An 8-bit three-state positive true data bus used to transfer
commands, data and status between the EPCI and the
CPU.
TxRDY (Transmitter Ready)
This output is the complement of status register bit SRO.
When low, it indicates that the transmit data holding
register (TxH R) is ready to accept a data character from
the CPU. It goes high when the data character is loaded.
This output is valid only when the transmitter is enabled.
It is an open drain output which can be "wire-ORed" to
the CPU interrupt.
RxRDY (Receiver Ready)
This output is the complement of status register bit SR1.
When low, it indicates that the receive data holding register
(RxHR) has a character ready for input to the CPU. It
goes high when the RxHR is read by the CPU and also
when the receiver is disabled. It is an open drain output
which can be "wire-ORed" to the CPU interrupt line.
TxEMT/DSCHG
This output is the complement of status register bit SR2.
When low, it indicates that the transmitter has completed
serialization of the last character loaded by the CPU, or
that a change of state of the DSR or DeD inputs has
occurred. This output goes high when the status register
is read by the CPU if the TxEMT condition does not
exist. Otherwise, the TxHR must be loaded by the CPU
for this line to go high. It is an open drain output which
BRCLK (Baud Rate Clock)
Clock input to the internal baud rate generator. This is
not requir~q when external receiver and transmitter clocks
are used.
RxC/BKDET (Receiver Clock, Break Detect)
When the EPCI is programmed for External Receiver
Clock, this pin will act as an input and control the rate
at which a character is received. The frequency is
program med in Mode Register 1 and may be 1 X, l6X or
64X the baud rate. Data are sampled on the rising edge.
If internal Receiver Clock is programmed this pin will
provide an output, either a 1 X/16X clock or Break Detect
signal determined by programming Mode Register 2.
TxC/XSYNC (Transmitter Clock/External SYNC)
When the EPCI is programmed for External Transmitter
clock, this pin will act as an input and control the rate at
which the character is transmitted.
The frequency is
programmed in Mode Register 1 and may be 1X, l6X or
64X the baud rate. Date changes on the falling edge of this
clock. If the UPCI is programmed for Internal Transmitter
clock, this pin can be either an output providing a lX/16X
clock or an input for External Synchronization determined
by Mode Register 2 programming.
RxD (Receive Data)
RxD is the serial data input to the receiver.
TxD (Transmit Data)
TxD is the serial data output from the transmitter. When
the transmitter is disabled the output will be in the high,
"Mark", state.
DSR (Data Set Ready)
DSR is an input that can be used to indicate to the UPCI
Data Set Ready or Ring Indicator. Its complement appears
in the Status Register as bit SR7. A change of state on
DSR will cause TxEMT/DSCHG to go low if either CRD or
CR2=1.
DCD (Data Canier-Detect)
The DCD input must be low for the receiver to operate.
If DCD goes high while receiving, the RxC is internally
inhibited. The complement of DCD appears in the Status
Register as bit SR6. A change of state in DCD will cause
TxEMT/DSCHG to go low if either CRD or CR2=1.
CTS (Clear To Sned)
The CTS input must be low for the transmitter to operate.
If CTS goes high whi Ie transmitting, the character currently
in the Transmit Shift Register will be transmitted before
termination TxO will then go to the high level (Mark).
7-10
eUMC
UM2661
DTR (Data Terminal Ready)
The DTR output is the complement of CR1. It is normally
used to indicate Data Terminal Ready.
RTS (Reguest To Send)
The RTS outp'ut is the complement of CR5. If the
Transmit Shift Register is not empty when CR5 is reset,
RTS will not go high until one TxC after the last serial
bit is transmitted.
Functional Description
The internal organization of the EPCI consists of six major
blocks, (see Fig. 1). These are the Transmitter, Receiver,
Clock Control, Operation Control, Modem Control and
SYN/DLE Control. These blocks internally communicate
over common data and control buses. The data bus is also
linked to the CPU via a bi-directional three-state interface.
Briefly, these blocks perform the following functions:
Transmitter
The Transmitter receives parallel data from the CPU and
converts it to a serial bit stream, inserting Start, Stop, and
Parity bits, as selected by the user, and outputs a composite
serial data stream.
Receiver '.
The Receiver accepts serial data from the sending device,
converts it to a parallel format checking for appropriate
Start, Stop and Parity bits and Control Characters, as
selected by the user, and sends the assembled character to
the CPU.
Timing Control
The Timing Control block contains a programmable Baud
Rate Generator (BR G) wh ich is able to accept externa I
Transmit (TxC) or Receiver (RxC) clocks or to divide
external clock (BRCLK) for controlling data transfers.
The BRCLK input allows the user to program one of 16
commonly used baud rates.
Operating Control
The Operation Control b lock contains four registers;
Mode Registers 1 and 2, (MR1, MR2) the Command
Register (CR) and Status Register (SR). These registers
are used to store configuration and operation commands
from the CPU.
They generate the necessary internal
control signals for proper device operation, and maintain
status information for the CPU.
Modem Control
The modem control section provides interfacing for
three input signals and three output signals used for
"handshaking" and status indication between the CPU and
a modem.
7-11
SYN/DLE Control
This section contains control circuitry and three 8-bit
registers storing the SYN1, SYN2, and DLE character
provided by the CPU. These registers are used in the
synchronous mode of operation to provide the characters
required for synchronization, idle fill and data transparency.
Operational Description .
The EPCI's operation is determined by programming the
Mode and Command Registers. Baud rate, asynchronous
or synchronous communication, and SYN characters are
determined before enabling the tn;lnsmitter or receiver.
Asynchronous Receiver Operation
After the Mode Registers are configured the receiver is
enabled when the RxEN bit in the Command Register
(CR2) is set to a 1 and DCD is low. The EPCI then
monitors the RxD input waiting for a high to low
transition. If a trarisition is detected, the RxD input is
again sampled one-half bit time later. If RxD is now high,
a search for a valid start bit is begun again. If RxD is still
Iowa valid start bit is assumed and the receiver continues
to sample the RxD input at one bit time intervals until the
correct number of data bits, parity bit and one stop bit
have been assembled. The character is then transferred
to the Receive Data Holding Register (R x HR); RxRDY in
the status Register is set (SR1); the RxRDY output goes
low. If the character length is less than 8 bits, the high
order unused bits in the holding register are set to zero.
The parity error, framing error, and overrun error status
bits are strobed into the status register on the positive
going edge of RxC corresponding to the received character
boundry. See Figure 6 and 8.
If the stop bit is present, the receiver will immediately
begin its search for the next start bit. If the stop bit is
absent (framing error), the receiver will interpret a space bit
if it persists into the next bit time interval. If a break
condition is detected (RxD is low for the entire characte'r as
well as the stop bit) only one character consisting of all
zeros (with the FE status bit set) wi II be transferred to the
holding register. The RxD input must return to a high
condition before a search for the next start bit begins.
See Figure 9.
Pin 25 can be programmed as a Break Detect (BKDET)
output by setting both bits 4 and 7 of Mode Register 2
(MR2). When these bits are set and a break is detected,
the BKDET output will go high. If RxD returns high for
at least one RxD time. BKDET will return low.
Synchronous Receiver Operation
When the EPCI is programmed for synchronous operation,
the receiver will remain idle until the receiver enable bit
(CR2) is set. At this time the EPCI enters the hunt mode.
Data are shifted into the receive data shift register (RxSR)
one bit at a time. The contents of RxSR are then compared to the contents of the SYN1 register. If the two are
not equal, the next bit is sh ifted in and the comparison is
repeated. When the two registers match, the hunt mode is
terminated and character assembly mode begins. If single
SYN operation is programmed, the SYN DETECT status
bit is set. If double SYN operation is programmed, the first
character assembled after SYN1 must be SYN2 in order for
the SYN DETECT bit to be set. Otherwise the EPCI
returns to the hunt mode. (Note that the sequence SY N 1SYN1-SYN2 will not achieve synchronization). SeeFigure
6.
When synchronization has been achieved, the EPCI
continues to assemble characters and transfer them to the
holding register, setting the RxRDY status bit and asserting
the RxRDY output each time a character is transferred.
The PE and OE status bits are set as appropriate. Further
receipt of the appropriate SYN sequence sets the SYN
DETECT status bit. If the SYN stripping mode is commanded, SYN characters are not transferred to the holding
register.
Note:
the SYN characters used to establish
initial synchronization are not transferred to the holding
register in any case.
By setting MR24 (MR2 bit 4) and MR27= 1 pin 9 (RxCI
SYNC) wi II be programmed as an external jam synchronization input.
When XSYNC is selected internal SYN1,
SYN1-SYN2 and DLE-SYN1 detection is disabled. Each
positive going signal on XSYNC will cause the receiver to
establish synchronization on the rising edge of the next
RxC pulse. Character assembly will start with the RxD
input at this edge. XSYNC must be lowered prior to the
next rising edge of RxC. This external synchronization will
cause the SYN DETECT status bit to be set until the status
register is read. Refer to XSYNC timing diagram.
Asynchronous Transmitter Operation
When the EPC I is programmed to transmit the transmitter
will remain idle until CTS is low and the TxEN bit (CRO)
is set. The EPC I wi II respond by setting status register
(SR) bit 0 and asserting the TxRDY output. When the CPU
writes a character into the transmit data holding register
(TxH R), SRO is reset and TxRDY returns high. The
character is then transferred to the transmit shift register
(TxSR) when it is idle or has completed transmissionDf the
previous character. SRO is again set, and TxRDY goes low.
See Figure 7.
of the data bits, a new character is not available in the
transmit holding register, the TxD output remains in the
marking (high) condition and the TxEMT/DSCHG,output
and its corresponding status bit are asserted. Transmission
resumes when the CPU loads a new character into the
holding register. The transmitter can be forced to output
a continuous low (BREAK) condition by setting CR3.
Synchronous Transmitter Operation
When the ECP I is i ni tia Ily program med for synchronous
transmission it will remain in the idle state (RxD high) until
TxEN is set. At this point TxD remains high, TxRDY will
go low and both will stay in this state until the first
character (usually a SYN character) is written into the
TxHR. This starts transmission, with TxRDY going low
each time a character is shifted from the TxHR to the
If TxRDY is not serviced before the previous
TxSR.
character is shifted out of the TxSR, the TxEMT output
will go low and the EPCI will automatically fill the pending
gap with SYN1, SYN1, SYN2 doublets, or DLE-SYN1
doublets, depending on the state of MR6 and MR17.
Transmission will be continuous until TxFN is reset to O.
See Figure 7.
If the send DLE bit (CR3) is set, the DLE character is
automatically transmitted prior to the transmission of any
character stored in the TxHR. Since this is a one time
command, CR3 does not have to be reset.
EPCI Programming
Before data communications can be started the EPCI
must be programmed by writing to its mode and command
registers. Additionally, if synchronous communication has
been selected the appropriate SYN1, SYN2 and DLE
registers must be loaded Reference the Register Addressing
Table and Initialization Flow Chart for address requirements and programming procedure.
The Register Addressing table shows MR1 and MR2 at the
same address. The EPCI has an internal pointer that
initially direat that first read or write to MR1, then on the
next access at the same address the pointer directs the
operation to MR2. A similar sequence occurs for the SYN
and DLE registers; first SYN1 then SYN2 then DLE. If
more than the required number of accesses are made the
internal pointer resets to the first register. The pointer
is also reset to MR1 and SYN1 by a RESET input or a
read of the Command Register, but 'unaffected by any
other read or write operation.
Register Formats
I n the asynchronous mode, the transm itter automatically
sends a start bit followed by the programmed number of
data bits, the least significant bit being sent first. It then
appends an optional odd or even parity bit and the programmed number of stop bits. If, following transmission
7-12
The register formats are summarized in Figures 2 through 5
MR1 and MR2 define the general operating characteristics.
The Command Register controls the basic operation
defined by MR1 and MR2. The Status Register indicates
the EPCI operating status and the condition of external
UM2661
inputs. These registers are cleared by a RESET input
(SR6 and SR7 excepted).
Mode Register 1 (M R 1 )
MRll and MR10 select the communication mode and baud
rate multiplier.
Note: the multiplier in asynchronous
mode applies only if the external input option is selected
by M R24 and RM25.
Character
MR13 and MR12 select Character length.
length does not include the parity bit, when selected, and
does not include the start and stop bits in asynchronous
operation.
MR14, when set, selects parity. A parity bit will be
transmitted with each character, and a parity check will be
performed on each character received.
M R 15 selects either odd or even parity.
In the asynchronous mode MR16 and' MR17 select the
number of stop bits; 1, 15 or 2. If 1 X baud rate is programmed 1.5 stop bits defaults to 1 on transmit.
In the synchronous mode MR17 controls the number of
SYN characters used to establish synchronization, and
the number of fill characters to be transmitted when
TxRDY and TxEMT are O.
M R 16 controls selection of the transparent mode. When
MR16 is set (transparent selected) DLE-SYNl is used for
character fill and SYN detect (SR 5), but the normal
synchronization sequence is used to establish character
sync. When transmitting in the synchronous transparent
mode, a DLE character in the TxH R will cause a second
DLE character to be transmitted .. Note: if the send DLE
command (CR3) is active when a DLE character' is in the
TxHR only one additional DLE will be transmitted.
The bits in the mode register affecting character assembly
and disassembly (MR12-MR16) can be changed dynamically (during active receive/transmit operation).
The
character mode register affects both the transmitter and
receiver; therefore in synchronous mode, changes should
be made only in half duplex mode (RxEN=l or TxEN=l,
but not both simultaneously=l). In asynchronous mode,
character changes should be made when Rx EN and
TxEN=O or when TxEN=l and the transmitter is marking
in half duplex mode (RxEN =0).
To effect assembly/disassembly of the next received/
transmitted character, MR12--15 must be changed within
n bit times of the active going state of RxDRY/TxRDY.
Transparent and non-transparent mode changes (M R 16)
must occur within n-l bit times of the character to be
affected when the receiver or transmitter is active.
(n = smaller of the' new and old character lengths.)
Mode Register 2 (MR2)
MR20 through M R23 select the internal Baud Rate
Generator (BRG). There are sixteen selectable rates for
each version as outlined in Table 1.
MR24 through MR27 define the receive and transmit
clock source and the function of pins 9 and 25. Reference
Figure 3.
Table 3. UM2661 Register Addressing
,.
CE
Ai
~
RIW
Functions
1
X
X
X
0
0
0
0
Read Receive Holding Register (RxHR)
0
0
0
1
Write Transmit Holding Register (TxHR)
0
0
1
0
Read Status' Register (SR)
0
0
1
1
Write SYN1/SYN2/DLE Registers
0
1
0
0
Read Mode Registers (MR1, MRl IMR2)
Write Mode Registers (MRl , MRl 1M R2)
Three-state Data Bus
0
1
0
1
0
1
1
0
Read Command Register
0
1
1
1
Write Command Register
7-13
UM266J.
EPCI Initialization Flow Chart
INITIAL RESET
,,~
LOAD
MODE REGISTER 2
NOTE: MODE REGISTER 1 MUST BE
WRITTEN BEFORE 2 CAN BE WRITTEN,
MODE,REGISTER 2 NEED NOT BE
PROGRAMMED IF EXTERNAL CLOCKS
ARE USED.
N
NOTE: SYN1 REGISTER
MUST BE WRITTEN
BEFORE SYN2 CAN.BE
WRITTEN AND SYN2
BEFORE OLE CAN BE
WRITTEN.
Y
LOAD
SYN2 REGISTER
N
N
LOAD
OLE REGISTER
,-------I
I
I
LOAD
COMMAN'b REGISTER
r----I
I
-----,
OPERATE
I
I
____ .J
N
7-14
SUMC
UM2661
ASYNCMODE
-IT
LOOESELECT
PARITY
7
6
STOP BITS
0
0
0
INVALID
5
4
TYPE
CONTROL
1
0
0
0
0
1
1
1
1
1%
2
1
1
0
x
ODD
x
EVEN
DISABLED
ENABLED
DISABLED
ENABLED
1
1
7
6
SYN MODE
TRANSPARENCY
CONTROL
0
0
0
1
1
0
SYN1-SYN2
SYN1-SYN2
SYNl
SYNl
NORMAL
TRANSPARENT
NORMAL
TRANSPARENT
1
0
MODE
0
0
0
1
1
0
SYNC
ASYNC
ASYNC
ASYNC
1
1
BAUD RATE
FACTOR
lx
lx
16x
64x
--CHARACTER LENGTH
SYNC MODE
1
1
FILL
CHAR.
SYN1-SYN2
DLE-SYNl
SYNl
DLE-SYNl
NO. OF
BITS
3
2
0
0
0
5
DOUBLE
SINGLE
1
1
1
0
1
6
7
8
SYNC
MODE
Figure 4. Mode Register 1
I
I
I SEE BAUD RATE TABLES
7
6
5
4
TxC
RxC
PINg
PIN25
MODE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
O·
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
E
E
I
I
E
E
I
I
I
E
I
I
I
E
I
E
I
E
I
E
I
E
I
E
I
E
I
E
I
TxC
TxC
lx
lx
TxC
TxC
l6x
l6x
XSYNC
TxC
XSYNC
lx
XSYN
TxC
XSYNC
l6x
RxC
lx
RxC
lx
RxC
l6x
RxC
l6x
RxC
BKDET
RxC
BKDET
RxG
BKDET
RxC
BKDET
SYNC/ASYNC
SYNC/ASYNC
SYNC/ASYNC
SYNC/ASYNC
SYNC/ASYNC
SYNC/ASYNC
SYNC/ASYNC
SYNC/ASYNC
SYNC
ASYNC
SYNC
ASYNC
SYNC
ASYNC
SYNC
ASYNC
E
I
I
°
In the asynchronous mode setting CR3 will force the TxD
output low (break condition) at the end of the current
transmitted character. TxD will then remain low until CR3
is cleared; at that time TxD will go high for a minimum 1
bit time before resuming normal transmission.
In the synchronous mode setting CR3 will force the
transmission of the DLE character prior to sEmding the
character in the TxHR. Because this is a one-time command, bit 3 will automatically reset.
CR5 controls the state of the RTS output. When CR5= 1,
RTS will go low and the transmit logic will be enabled. A
transition of CR5 will cause RTS to go high one
1 to
TxC time after the last serial bit is transmitted, (if the
TxSR was not already empty).
°
Command Register (CR)
CRO (TxEN) will enable or disable the transmitter. When
TxEN=O, TxD, TxRDYand TxEMT are all high, the
transmitter is disabled. When TxEN goes active, TxRDY
wi II go low requesting the first character to be written to
the TxH R, and the TxD output will be enabled to transmit.
When TxEN goes inactive, the UPCI will complete transmission of any character still in the TxSR. TxD will then go to
the marking state and TxRDY and TxEMT will go high.
Refer to Transmit timing diagram.
CRl controls the DTR output.
logical complement of CR1.
A 0 to 1 transition of RxEN will initiate a start bit search
in asynchronous mode or initiate the hunt mode in
transition of RxEN
synchronous transmission. A 1 to
immediately terminates receiver operation.
The DTR output is a
CR2 (RxEN) will enable or diable the receiver. When
RxEN 0, the receiver is in an idle mode with RxRDY high.
CR7 and C R6 provide fou r a Iternate modes of operation in
both synchronous and asynchronous operation. When both
bits are normal operation is selected.
°
In the asynchronous mode, when only CR6 is set·automatic
echo mode is selected Clocked, regenerated received data
are automatically directed to the TxD line while normal
receiver operation continues. The receiver must be enabled
(C R2 = 1), but the transmitter need not be enabled. CPU to
receiver communications continues normally, but the CPU
to transmitter link is disabled. Only the first tharacter of
a break condition is echoed. The TxD output will go high
until the next valid start is detected. The following conditions are true while in automatic echo mode:
7-15
UM2661
1.
2.
3.
4.
5.
Data assembled by the· receiver are automatically
placed in the transmit holding register and retransmitted by the transmitter on th-e TxD output.
Transm it clock = receive clock.
TxRDY output=l.
The TxEMT/DSCHG pin will reflect only the data set
change condition.
The TxEN command (eRO) is ignored.
In the synchronous mode, when only CR6 is set automatic
SYN/DLE stripping is performed. The state of MR17 and
M R16 controls wh ich characters are stripped. f1eference
Figure 6 for a detailed example of the characters stripped.
Note: automatic stripping does not affect setting of the
SYN and DLE detect status bits.
Two diagnostic modes are achievable in both synchronous
and asynchronous operation; loca I loop back with C R7 = 1
and CR6=0, and remote loopback with both bits=l.
Local Loop Back
1.
2.
3.
4.
5.
The transmitter output is connected to the receiver
input.
DTR is connected to DCD and RTS is connected to
CTS.
Transmit clock is connected to the receive clock.
The DTR, RTS and TxD outputs are held high.
The CTS, DCD, DSR and RxD inputs are ignored.
Remote Loop Back
1.
2.
3.
,
4.
5.
6.
Data assembled by the receiver are automatically
placed in the transmit holding register and retransm itted by the transmitter on the TxD output.
Receive clock is connected to the transmit clock.
No data are sent to the local CPU, but the error status
conditions (PE, OE, FE) are set.
The RxRDY, TxRDY, and TxEMT/DSCHG outputs
are held high.
CR1 (TxEN) is ignored.
All other signals operate normally.
Status Register
SR D is the transmitter ready (TxR DY) status, it is the
logical complement of the TxR DY output. This bit
indicates the state of the TxHR when the transmitter is
enabled (TxEN=l). A 0 indicates TxHR is full, a 1
indicates TxH R is empty and requires servicing by the CPU.
This bit is cleared by writing to TxHR or by disabling the
transmitter (TxEN=O). Note: SRO is not set in either the
auto echo or rembte loop ba'ck modes.
SR1 is the receiver ready (RxRDY) status. It is the logical
complement of the RxRDY output. This bit indicates the
state of the RxHR when the receiver is enabled (RxEN=l).
A 0 indicates the RxHR is emptY,a 1 indicates the RxHR is
full and requires servicing by the CPU. This bit is cleared
by writing to the TxHR or by disabling the receiver.
(RxEN =0).
Note: CR bits 0, 1 and 5 must be set, CR2 is a don't care.
17161 5 14131211101
OPERATING MODE
7
6
o
o
0
I
I
LTRANSMIT CONTROL (TxEN)
I
Io
Io
NORMAL OPERATION
ASYNC: A UTO ECHO
SYNC: SY NAND/OR
D LE STRIPPING
o
f
L--
LOCAL LO OP BACK
REMOTE LOOP BACK
REQUEST TO SEND
5
RfS
o
FORCE RT SHIGH
1 TxC AFT ER LAST
BIT IN Tx SR IS
TRANSMI TTED
i5'fA"
f
FORCE DTR LOW
FORCE i5iR HIGH
RECEIVE CONTROL (RxEN)
I
RECEIVER
DISABLED
ENABLED
ASYNC: FORCE BREAK
I3
[o
RESET ERROR
o
DATA TERMINAL READY
I1
Io
r2
Io
FORCE RTS LOW AND
ENABLE T RANSMITTER
4
TRANSMITTER
DISABLED
ENABLED
I
AFFECT 0 N SR
NONE
TxD
NORMAL
FORCED BREAK
SYNC: SEND DLE
RESETS SR BITS
50NLY
3
3,4,&
Figure 5. Command Register
7-16
CHAR SENT
NONE
DLE SENT
UM2661
SR4 indicates an overrun error when set. An overrun
condition exists when the CPU does not read the RxHR
before the next received chill'acter is transfelTed to it.
(The previous character is lost.) SR4 is cleared by the
reset error command and when the receiver is disabled.
SR2 indicates a change of state of either DSR or DCD or
that the TxSR is emc?t'b This bit is the logical complement
of the TxEMT/DS H
output.
A read of the status
register will clear bit 2 if a state change on DSR or DCD
has occurred. If a second successive read of the status
register indicates bit 2 =0, then DCD or DSR changed. If
bith 2 is still set, then the TxSR is empty. Because the
transm itter does not sta rt unt i I the fi rst character has
been written to the TxH R, TxEMT status will not be
reflected until transmission of the first character is complete, TxEMT status is cleared by Tw~tif to the TxH R or
disabling the transmitter. Note:
x M status will be set
in synchronous mode even though "fill" characters are
'being transmitted.
In the asynchronous mode SR5 indicates that the received
character was not framed by a stop bit. If the RxHR is
all O's when bit 5 is set, a break condition was present.
In synchronous non-transparent mode, it indicates receipt
of the SYNl character in single SYN mode or the SYN1SYN2 pair in double SYN mode.
In synchronous
transparent mode this bit is set upon detection of the
initial synchronizing characters (SYNl or SYN1-SYN2)
and after synchronization has been achieved, when a DLESYNl pair is received. The bit is reset when the receiver
is disabled, when the reset error command is given in
asynchronous mode, and when the status register is read by
the CPU in the synchronous mode.
SR3 when set reflects a parity error when parity checking is
enabled in both the syrichronous and asynchronous modes.
In the synchronous transparent mode, (M R16=l) and the
parity enable bit (MR14) is 0, SR3 will then indicate DLE
detect when set. This indicates that a character matching
DLE register was received and the present character is
neither SY N 1 nor D LE. This bit is cleared when the next
character following the above sequence is loaded into the
RxHR, when the receiver is disabled or by a reset error
command.
I 7 I6 I5 I4 I3 I2 I1 I0 I
SR6 and SR7 reflect the condition of the OCD and DSR
inputs respectively. Their state is the logical complement
of their respective inputs.
WHEN SET (=1) THESE BITS INDICATE
~
TxRDY
RxRDY
TxEMT/DSCHG
CONDITION
RESET BY
TxHR EMPTY
TxRDY=O
WRITING TO T HR
x
RxH.R FULL
RxRDY = 0
READ RxHR. DISABLE
RECEIVER
RxSR EMPTY OR
WRITING TO TxHR
STATE CHANGE ON
OR DSR
TxEMT/DSCHG = 0
READING STATUS REGISTER
DCEl
PE/DLEDET
OE
FE/SYNDET
ASYNC: PARITY ERROR . RESET ERROR CMD
DISABLE RECEIVER
P.E. RESET BY: RESET ERROR
CMD AND DISABLE RECEIVER
OLE DETECT RESET BY: NEXT
CHARACTER LOADING INTO RxHR
SYNC: PARITY ERROR
IF ENABLED OR
OLE DETECT
OVERRUN DETECTED
RESET ERROR CMD OR DISABLE
RECEIVER
ASYNC: FRAMING
ERROR
SYNC: SYN DETECT
RESET ERROR CMD OR DISABLE
RECEIVER
READ STATUS REGISTER OR
DISABLE RECEIVER
DCD
COMPLEMENT OF
OCDINPUT
N/A
DSR
COMPLEMENT OF
DSRINPUT
N/A
17161
MASTER RESET
RESET ERROR CMD
5
14131
2
1 1 10 1
1- 1- 1 I I I I I 1
0
1- 1-
0
10 10
0
0
0
/ 0 /- /-
0
1- I
-SYMBOL INDICATES NO EFFECT
Figure 6. Status Register
Ordering Information
Part Number
BRCLK
Baud Rate
UM2661-1
UM2661-2
UM2661-3
4.9152 MHz
4.9152 MHz
5.0688 MHz
50 '\119200
45.5'\138400
50 '\119200
7-17
(l)UMC
,===========Dual
Wfi1
UM2681 SERIES
Asynchronous
Receiver/
Transmitter
(DUART)
Features
•
•
•
•
•
•
•
•
Dual full-duplex asynchronous receiver/transmitter
Ouadruple buffered receiver data registers
Programmable data format
5 to 8 data bits plus parity
Odd, even, no parity or force parity
1, 1.5 or 2 stop bits programmable in 1/16 bit
increments'
Programmable baud rate for each receiver and
transmiter' selectable from:
18 fixed rates: 50 to 38.4K baud
One user defined rate derived from programmable
timer/counter
External 1x or 16x clock
Parity, framing, and overrun error detection
False start bit detection
Line break detection and generation
Programmable channel mode
Normal (full duplex)
Automatic echo
Localloopback
Remote loopback
•
•
•
•
•
•
•
•
•
•
•
Multi-function programmable 16-bit counter/timer
Multi-function 7-bit input port
- Can serve as clock or control inputs
- Change of state detection on four inputs
Multi-function 8-bit output port
Individual bit set/reset capability
- Outputs can be programmed to be status/interrupt
signals
Versatile interrupt system
Single interrupt output with eight maskable interrupting conditions
Output port can be configured to provide a total of
up to six separate wire-OR'able interrupt outputs
Maximum data transfer: 1 X-l MB/sec, 16X-125KB/sec
Automatic wake-up mode for multidrop applications
Start-end break interrupt/status
Detects break which originates in the middle of a
character
On-chip crystal oscillator
TTL compatible
Single +5V power supply
General Description
The UM2681 Dual Universal Asynchronous Receiver/
Transmitter (DUART) is a single chip NMOS-LSI communications device that provides two independent fullduplex asynchronous receiver/transmitter channels in a
single package. It interfaces directly with microprocessors
and may be used in a polled or interrupt driven system.
The baud rate generator and counter/timer can
clock.
operate directly from a crystal or from external clock
inputs. The ability to independently program the operating
speed 'of the receiver and transmitter make the DUART
particularly attractive for dual-speed channel applications
such as clustered terminal systems.
The operating mode and data format of each channel can
be programmed independently. Additionally, each receiver
and transmitter can select its operating speed as one of
eighteen fixed baud rates, a 16X clock derived from a
programmable counter/timer, or an external 1 X or 16X
Each receiver is quadruply buffered to minimize the
potential of receiver overrun or to reduce interrupt overhead in interrupt driven systems.
I n addition, a flow
control capability is provided to disable a remote DUART
transmitter when the buffer of the receiving device is full.
Pin Configuration
AO
VCC
Al
IP2
A2
CEN
A3
RESET
WRN
X2
RON
Xl/CLK
Al
AO
A2
Vcc
A3
CEN
WRN
RESET
RON
Kl/CLK
RXOB
RXOA
RXOB
RXOA
OP2
TXOB
TXOA
TXOB
TXOA
OP4
OPl
OP6
01
DO
DO
02
03
02
05
04
07
D6
04
06
INTRN
OPO
INTRN
GNO
7-18
01
DO
03
02
05
04
07
06
GNO
INTRN
(DUMC
UM2681 SERIES
Also provided on the UM2681 are a mUltipurpose 7-bit
input port and a multipurpose 8-bit output port. These
can be used as general purpose I/O ports or can be assigned
specific functions (such as clock inputs or status/interrupt
outputs) under program control.
The UM2681 is available in three package versions to
satisfy various system requirements.
Absolute Maximum Ratings*
*Comments
Stress above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied and exposure to absolute maximum rating
conditions for extended period~ may affect device
reliability.
Operating ambient temperature .......... 0° to +70°C
0
Storage temperature .. . . . . . . . . . . .. _65° to +150 C
All voltages with respect to ground .... -O.5V to +6.0V
Block Diagram
I
Do·D7
CHANNEL A
BUS BUFFER
_________
P=
, TRANSMIT
HOLDING REG
TRANSMIT
SHIFT REGISTER
RDN WRN - _
CEN
AO-A3--}-RESET _
OPERATION CONTROL
I
.
ADDRESS
DECODE
I
RIW CONTROL
I
RECEIVE
HOLDING REG
(3)
A
.
I
I MRA 1,2 r
I
INTERRUPT
CONTROL
IMR
..
ISR
~RxDA
RECEIVE
SHIFT REG
I
INTRN-
r------ TxDA
v
t---
CRA
SRA
I
I
CHANNEL B
TxDB
(AS ABOVE)
RxDB
INPUT PORT
TIMING
I
I
BAUD RATE
GENERATOR
CLOCK
SELECTORS
I
~~
I
...J',,----./.
i~
1--_ __.1
I
IPO-IP6
:II-~----'..IP_C_R_-I1
L-~.~A~C=R~='__j
FUNCTION
SELECT
LOGIC
A
y
X2--
I--¥--
OUTPUT PORT
ICOUNTERfTlMER I
X1/CLK_
CHANGE OF
STATE
DETECTORS (4)
XTALOSC
I
y
I
.
~
-T--- OPO-OP7
OPCR
OPR
CSRA
.---VCC
CSRB
ACR
.---GND
CTUR
CTLR
7-19
UM2681 SERIES
D.C. Electrical Characteristics
(T A = o°C to +70°C. Vee = 5.0V ±.5%)
Parameter
Limits
Test Conditions
Min.
Units
Typ.
Max.
VIL
Input low voltage
VIH
Input high voltage (except Xl/ClK)
2.0
V
VIH
Input high voltage (Xl/ClK)
4.0
V
VOL
Output low voltage
IOL=2.4mA
VOH
Output high voltage (except o.c .• outputs)
IOH = -400J.l.A
2.4
IlL
I nput'leakage current
VIN= 0 to Vee
ILL
Data bus 3-state leakage current
loe
Open collector output leakage current
Icc
Power supply current
0.8
V
0.4
V
-10
10
J.l.A
Vo = 0 to Vee
-10
10
J.l.A
Vo = 0 to Vec
-10
10
J.l.A
150
mA
V
A.C. Electrical Characteristics
(T A = O°C to
+ 70°C. V cc = 5.0V ± 5%)
Tentative Limits
Parameter
Units
Min.
Typ.
Max.
Reset Ti~ing (Figure 1)
tRES
RESET pulse width
1.0
J.l.s
Bus Timing (Figure 2)
tAS
AO-A3 setup time to RON. WRN low
10
tAH
AO-A3 hold time from RON. WRN high
0
ns
tcs
CEN setup time to RON. WRN low
0
ns
ns
tCH
CEN hold time from RON. WRN high
tRW
WRN. RON pulse width
too
Data valid after RON low
175
ns
tOF
Data bus floating after RDN high
100
ns
0
ns
225
ns
tos
Data setup time before WR N high
100
ns
tOH
Data hold time after WRN high
20
ns
tRWO
High time between READs and/or WR ITEs
200
ns
7-20
UM2681 SERIES
Tentative Limits
Parameter
Units
Min.
Typ.
Max.
Port Timing (Figure 3)
tps
Port input setup time before RON low
0
tpH
Port input hold time after RON high
0
tpD
Port output valid after WRN high
ns
ns
400
ns
Interrupt Timing (Figure 4)
tlR
INTRN (or OP3-0P7 when used as interrupts) high from:
Read RHR (RXROY IFFU LL interrupt)
300
ns
Write TH R (TX R DY interrupt)
300
ns
Reset command (delta break interrupt)
300
ns
Stop CIT command (counter interrupt)
300
ns
Read IPCR (input port change interrupt)
300
ns
Write IMR (clear of interrupt mask bit)
300
ns
4.0
MHz
4.0
MHz
0
2.0
MHz
0
1.0
MHz
Clock Timing (Figure 5)
tCLK
Xl ICLK high or low time
100
tCLK
Xl IC L K frequency
2.0
tCTC
CTCLK (IP2) high or low time
100
fCTC
CTCLK (IP2) frequency
0
ns
3.6864
ns
ns
220
tRx
high or low time
fRX
RxC frequency (16X)
tTX
TxC high or low time
220
f TX
TxC frequency (16X)
0
2.0
MHz
0
1.0
MHz
350
ns
150
ns
(lX)
(lX)
ns
Transmitter Timing (Figure 6)
tTXD
TxO output delay from TxC low
tTCS
TxC output skew from TxO output data
0
Receiver Timing (Figure 7)
tRXS
RxO data setup time to RxC high
240
ns
tRXH
RxD data hold time from RxC high
200
ns
7-21
UM2681 SERIES
RESET
-}--Fi~ure
1. Reset Timing
AO-A3
CEN
.1
RON
00-07
FLOAT
(READ)
1_ _- - - -
t
RWO - - - -...1
WRN
00-07
(WRITE)
Figure 2. Bus Timing
RON
IPO-IP6
WRN
OPO-OP7
Figure 3. Port Timing
RON
OR
WRN
INTRN
OR
OP3-0P7
\'---"---~_tIRj_
Figure 4.
Interrupt Timing
7-22
SUMC
UM2681 SERIES
+5V
Cl: 10-15pF+{STRAY(5pF)
C2: 0-5pF+{STRA Y (5pF)
lK
.-'-----1 ~.----.- CLOCK TO OTHER CHIPS
74LS04
Xl/CLK
CTCLK
RxC
TxC
.-----*----tX 1
UM2681
'---_------tX2
3.6864MHz
CRYSTAL SERIES RESISTANCE SHOULD
BELESS THAN 180 OHMS.
Figure 5. Clock Timing
1 BIT TIME
(lOR 16 CLOCKS)
TxC
(INPUT)
________________ ___
x~
TxD
I
TxC
(1 X OUTPUT)
\~--
Figure 6. Transmit
Figure 7. Receive
TxD
TRANSMITTER
ENABLED
TxRDY
(SR2)
WRN
CTS
(IPO)
1
I
RTSN2~
(OPO)
~
r'-----------------------------' ('-----OPR(O)=l
Notes: TIMING SHOWN FOR MR2(4) = 1
TIMING SHOWN FOR MR2(5) = 1
OPR{O)=l
Figure 8. Transmitter Timing
7-23
I)UMC
UM2681 SERIES
RxD
RECEIVER
ENABLED
RxRDY
(SRO)
FFUL
(SR1)
----------1------------
RxRDY FFULL _ _ _ _ __.
(OP5)2
RON
STATUS DATA
0,-""--'
OVERRUN
(SR4)
-----------------------------~----~~
RTSl
(OPO)
OP,RIO)=l
Figure 9. Receiver Timing
Notes: 1. Timing shown for MR1(7)=1.
2. Shown for OPCR(4)=1 and MR(6)=O.
MASTER STATION
BIT9
I
TxD
I
I
I
~..
T1~~~
ENABLED
I
:
.
,-I~
....~_....rf
.
I
WRN
ADD#l
;
----------~)~)~--~---------------
f
.
MR1(4-3)=11
MR1(2)=1
f)~_ _ _ _ _ _ _~~:--,
ioI IL--r.~
'DO
I
TRANSMITTER
BIT9
DIT9
I
fOO#!d
MR1(2)=0 DO
MR1(2)=1 ADD#2
PERIPHERAL STATION
S(T9
I I
RxD - - - ,
10
.......a.-_""-"
BIT9
FOO#l
HII
RECEIVER
ENABLED _ _ _ _ _ _ _ _ _ _ _ _ _
,I
DO
u.
I
I
~---~
: f=-t
.joll!
_, , "f-r.--------I)j----.J
BIT9
j
FOO#2 l
BIT9
l ! ...1 ......r--..,.......-I'f'_ ...10"",1 ~fI
I
I,
iL----
,~::: u---------~--, u=I>f-:--------....,;~
~
L
ADD#l
STATUS DATA
DO
Figure 10. Wake Up Mode
7-24
ADo#2
UM2681 SERIES
Pin Description
Mnemonic
Applicable
40
Type
Names and Functions
28 24
00-07
X
X
X
I/O
Data Bus: Bidirectional 3-state data bus used to transfer commands, data and
status between the OUART and the CPU. DO is the least significant bit.
CEN
X
X
X
I
Chip Enable: Active low input signal. When low, data transfers between the
CPU and the OUARTare enabled on 00-07 as controlled by the WRN, RNO and
AO-A3 inputs. When high, places the 00-07 lines in the 3-state condition.
WRN
X
X
X
I
Write Strobe: When low and CEN is also low, the contents of the data bus is
'loaded into the addressed register. The transfer occurs on the rising edge of the
signal.
RON
X
X
X
Read Strobe: When low and CEN is also low, causes the contents of the addressed
register to be presented on the data bus. The read cycle begins on the falling edge
of RON.
AO-A3
X
X
X
Address Inputs:
operations.
RESET
X
X
X
I
Reset: A high level clears internal registers (SRA, SRB, 1MB, ISR, OPR, OPCR),
puts OPO-OP7 in the high state, stops the counter/timer, and puts channels A and B
in the inactive state, with the TxOA and TxOS outputs in the mark (high) state.
INTRN
X
X
X
0
Interrupt Request: Active low, open drain, output which signals the CPU that one
or more of the eight maskable interrupting conditions are true.
Xl/CLK
X
X
X
X2
Crystal 1: Crystal or external clock input. A crystal or clock of the specified
limits must be supplied at all times. When a crystal is used, a capacitor must
be connected from this pin to ground (see Figure 5).
o
X X
Select the OUART internal registers and ports for read/write
Crystal 2: Conection for other side of the crystal. Should be connected to ground
if a crystal is not used. When a crystal is used, a capacitor must be connected from
this pin to ground (see Figure 5).
RxOA
X
X
X
Channel A Receiver Serial Data Input:
'Mark' is high, 'space' is low.
The least significant bit is received first.
RxOB
X
X
X
Channel S Receiver Serial Data Input:
'Mark' is high, 'space' is low.
The least significant bit is received first.
TxOA
X
X
X
0
Channel A Transmitter Serial Data Output: The least significant bit is transmitted
first. This output is held in the 'mark' condition when the transmitter is disabled,
idle, or when operating in localloopback mode. 'Mark'.is high, 'space' is I~w.
TxOB
X
X
X
0
Channel B Transmitter Serial Data Output: The least significant bit is transmitted
first. This output is held in the 'mark' condition when the transmitter is disabled,
idle, or when operating in local loopback mode. 'Mark' is high, 'space' is low.
OPO
X X
o
Output 0: General purpose output, or channel A request to send (RTSAN, active
low). Can be deactivated on receive or transmit.
OPl
X
o
Output 1: General purpose output, or channel B request to send (RTSBN, active
low). Can be deactivated on receive or transmit.
OP2
X
o
Output 2: General purpose output, or channel A transmitter 1 X or 16X clock
output, or channel A receiver 1 X clock output.
X
7-25
(DUMC
UM2681 SERIES
Pin D,escription (Continued)
Mnemonic
Applicable
40 28 24
Type
Names and Functions
OP3
X
0
Output 3: General purpose output, or open drain, active low counter/timer output,
or channel B transmitter 1X clock output, or channel B receiver 1 X clock output.
OP4
X
0
Output 4: General purpose output, or channel A open drain, active low, RxRDYA/
FFULLA output.
OP5
X
0
Output 5: General purpose output, or channel B open drain, active low, RxRDYB/
FFULLB output.
OP6
X
0
Output 6: General purpose output, or channel A open drain, active low, TxRDYA
output.
OP7
~
0
Output 7: General purpose output, or channel B open drain, active low, TxRDYB
output.
IPO
X
I
Input 0: General purpose input, or channel A clear to send active low input
(CTSAN).
IP1
X
I
Input 1: General purpose input, or channel B clear to send active low input
(CTSBN).
IP2
X
I
Input 2:
IP3
X
I
Input 3: General purpose input; or channel A transmitter external clock input
(TxCA). When the external clock is used by the transmitter, the transmitted data
is clocked on the falling edge of the clock.
IP4
X
I
Input 4: General purpose input, or channel A receiver external clock input
(RxCA). When the external clock is used by the receiver, the received data is.
sampled on the rising edge of the clock.
IP5
X
I
Input 5: General purpose input, or channel B transmitter external clock input
(TxCB). When the external clock is used by the transmitter, the transmitted data
is clocked on the falling edge of the clock.
IP6
X
I
Input 6: General purpose input or channel B receiver external clock input (RxCB).
When the external clock is used by the receiver, the received data is sampled on
the rising edge of the clock.
Vee
X
X
X
Power Supply: +5V supply input.
GND
X
X
X
Ground
X
-
General purpose input, or counter/time external clock input.
Block Diagram
The 2681 DUART consists of the following eight major
sections:
data bus buffer, operation control, interrupt
control, timing, communications channels A and B, input
.port and output port. Refer to the block diagram.
Data Bus Buffer
The data bus buffer provides the interface between the
external and internal data busses. It is controlled by the
operation control block to allow read and write operations
to take place
DUART.
between
the controlling CPU and the
Operation Control
The operation control logic receives operation commands
from the CPU and generates appropriate signals to internal
sections to control device operation. It contains address
decoding and read and write circuits to permit communications with the microprocessor via the data bus buffer.
7-26
UM2681 SERIES
Interrupt Control
A single active low interrupt output (INTRN) is provided
which is activated upon the occurrence of any of eight
internal events. Associated with the interrupt system are
the interrupt mask register (IMR) and the interrupt status
register (ISR). The IMR may be programmed to select only
certain conditions to cause INTRN to be asserted. The ISR
can be read by the CPU to determine all currently active
interrupting conditions.
Outputs OP3-0P7 can be programmed to provide discrete
interrupt outputs for the transmitters, receivers, and
counter/timer.
start, stop, and optional parity bits and outputs a
composite serial stream of data on the TxD output pin.
The receiver accepts serial data on the RxD pin, converts
this serial input to parallel format, checks for start bit,
stop bit, parity bit (if any), or break condition and sends
an assembled character to the CPU.
Input Port
The inputs to this unlatched 7-bit port can be read by
the CPU by performing a read operation at address
D 16 . A high input results in a logic 1 while a low input
results in a logic O. D7 will always be read as a logic 1.
The pins of this port can also serve as auxiliary inputs to
certain portions of the DUART logic.
Timing Circuits
The timing block consists of a crystal oscillator, a baud
rate generator, a programmable 16-bit counter/timer,
and four clock selectors. The crystal osci Ilator operates
directly from a 3.6864 MHz crystal connected across the
Xl/ClK and X2 inputs. If an external clock of the appropriate frequency is available, it may be connected to
Xl/ClK. The clock serves as the basic timing reference
for the baud rate generator (BRG), the counter/timer, and
other internal circuits. A clock signal within the limits
specified in the specifications section of this data sheet
must always be supplied to the DUART.
The baud rate generator operates from the oscillator or
external clock input and is capable of generating 18 commonly used data communications baud rates ranging from
50 to 38.4K baud. The clock outputs from the BRGare
at 16X the actual baud rate. The counter/time can be
used as a timer to produce a 16X clock for any other baud
rate by counting down the crystal clock or an external
clock. The four clock selectors allow the independent
selection, for each receiver and transm itter, of any of these
baud rates or an external timing signal.
The counter/timer (CIT) can be programmed to use one
of several timing sources as its input. The output of the
CIT is available to the clock selectors and can also be
programmed to be output at OP3. In the counter mode,
the contents of the CIT can be read by the CPU and it can
be stopped and started under program control. I n the
timer mode, the CIT acts as a programmable divider.
Communications Channels A and B
Each communications channel of the 2681 comprises a
full duplex asynchronous receiver/transmitter (UART).
The operating frequency for each receiver and transmitter
can be selected independently from the baud rate
generator, the counter timer, or from an external input.
The transmitter accepts parallel data from the CPU,
converts it to a serial bit stream, inserts the appropriate
7-27
Four change-of-state detectors are provided which are
associated with inputs IP3, IP2, IP1, and IPO. A high-tolow or low-to-high transition of these inputs lasting longer
than 25-50Jls will set the corresponding bit in the input
port wi II change register. The bits are cleared when the
register is ready by the CPU. Any change of state can also
be programmed to generate an interrupt to the CPU.
Output Port
The 8-bit mUlti-purpose output port can be used as·a
general purpose output port, in which case the outputs
are the complements of the output port register (OPR).
OPR [nl = 1 results in OP [nl = low and viceversa. Bits
of the OPR can be individually set and reset. A bit is
set by performing a write operating at address E16 with
the accompanying data specifying the bits to be set (1 =set,
O=not change). Likewise, a bit is reset by a write at address
F 16 with the accompanying data specifying the bits to be
reset (1 = reset, 0 = no change).
Outputs can be also individually assigned specific functions
by appropriate programming of the channel. A mode
registers (MR1A, MR2A), the channel B mode registers
(M R 1B, M R2B), and the output port configuration register
(OPCR).
Operational Description
Transmitter
The 2681 is conditioned to transmit data when the transmitter is enabled through the command register. The
2681 indicates to the CPU that it is ready to accept a
character by setting the TxRDY bit in the status register.
Th is condition can be programmed to generate an interrupt request at OP6 orOP7 and INTRN. When a 'character
is loaded into the transmit holding register (THR), the
above conditions are negated. Data is transferred from the
holding register to the transmit shift register when it is
idle or has completed transmission of the previous
character. The TxRDY conditionsare then asserted again
(IlUMC
UM2681 SERIES
which means one full character time of buffering is
provided. Characters cannot be loaded into the THR while
the transmitter is disabled.
The transmitter converts the parallel data from the CPU
to a serial bit stream on the TxD output pin. It
automatically sends a start bit followed by the programmed
number of data bits, an optional parity bit, and the programmed number of stop bits. The least significant bit is
sent first. Following the transmission of the stop bits, if
a new character is not available in the TH R, the TxD
output remains high and the TxEMT bit in the status
register (SR) will be set to 1. Transmission resumes and
the TxEMT bit is cleared when the CPU loads a new
character into the THR. If the transmitter is disabled, it
continues operatiRg until the character currently begin
transmitted is completely sent out. The transmitter can be
forced to send a continuous low condition by issuing a send
break command.
The transmitter can be reset through a software command.
If it is reset, operation ceases immediately and the
transmitter must be enabled through the command register
before resuming operation. If CTS operation is enabled,
the CTSN input must be low in order for the character to
be transmitted. If it goes high in the middle of a transmission, the character in the shift register is transmitted and
TxDA then remains in the marking state until CTSN goes
low. The transmi.tter can also control the deactivation of
the RTSN output. If programmed, the RTSN output will
be reset one bit time after the character in the transmit
shift register and transmit holding register (if any) are
completely transmitted, if the transmitter has been
disabled.
Receiver
The 2681 is conditioned to receive data when enabled
through the command register. The receiver looks for a
high to low (mark to space) transition of the start bit on
the RxD input pin. If a transition is detected, the state of
the RxD pin is sampled each 16X clock for 7-1/2 clocks
(16X clock mode) or at the next rising edge of the bit
time clock (1 X clock mode). ,If RxD is sampled high, the
start bit is invalid and the search for a valid start bit begins
again. If RxD is still low, a valid start bit is assumed and
the receiver continues to sample the input at one bit time
intervals at the, theoretical center of the bit, unti I the
proper number of data bits and the parity bit (if any) have
assembled, and one stop bit has been detected. The least
significant bit is received first. The data is then transferred
to the receive holding register (RHR) and the RxRDY
bit in the SR is set to a 1., This condition can be programmed to generate an interrupt at OP4 or OP5 and
INTRN. If the character legnth is less than eight bits,
the most significant unused bits in the RHR are set to
7-28
zero.
After the stop bit is detected, the receiver will immediately
look for the next start bit. However, if a non-zero
character was received without a stop bit (framing error)
and RxD remains low for one half of the bit period after
the stop bit was sampled, then the receiver operates as if a
new start bit transition had be'en detected at that point
(one-half bit time after the stop bit was sampled).
The parity error, framing error, overrun error and received
break state (if any)·are strobed into the SR at the received
character boundary, before the RxRDY status bit is set.
If a break condition is detected (RxD is low for the entire
character including the stop bit), a character consisting of
all zeros will be loaded into the RHR and the received
break bit in the SR is set to 1. The RxD input must return
to Cl high condition for at least one-half bit time before a
search for the next start bit begins.
The RHR consists of a first-in-first-out (FIFO) stack with
a capacity of three characters. Data is loaded from the
receive shift register into the topmost empty position of the
FIFO. The RxRDY bit in the status register is set whenever one or more characters are available to be read, and a
FFULL status bit is set if all three stack positions are
filled with data. Either of these bits can be selected to
cause an interrupt. A read of the R H R outputs the data at
the top of the FIFO. After the read cycle, the data FIFO
and its associated status bits (see below) are 'popped' thus
emptying a FIFO position for new data.
In addition to the data word, three status bits (parity
error, framing error, and received break) are also appended
to each data character in the FIFO (overrun is not). Status
can be provided in two ways, as programmed by the error
mode control bit in the mode register. In the 'character'
mode, status is provided on a character-by-character basis:
the status applies only to the character at the top of the
FIFO. In the 'block' mode, the status provided in the SR
for these three bits is the logical OR of the status for all
characters com i ng to the top of the F I F0 si nce the last
'reset error' command was issued. In either mode reading
the SR does not affect the FIFO, The FIFO is 'popped'
only when the RHR is read. Therefore the status register
should be read prior to reading the FI FO.
If.the FIFO is full when a new character is received, that
character is held in the receive sh ift register u nti I a FIFO
position is available. If an additional character is received
while this state exits, the contents of the FIFO are not
affected: the character previously in the shift register is
lost and the overrun error status bit (SR[4]) will be set
upon receipt of the start bit of the new (overruning)
character.
UM2681 SERIES
The receiver can control the deactivation of RTS.
If
programmed to operate in this mode, the RTSN output will
be negated when a valid start bit was received and the
FIFO is full. When a FIFO position becomes ayailable, the
RTSN output will be reasserted automatically. This feature
can be used to prevent an overrun, in the receiver, by
connecting the RTSN output to the CTSN input of the
transmitting device.
If the receiver is disabled, the F I Fa characters can be
read. However, no additional characters can be received
until the receiver is enabled again. If the receiver is reset,
the F I Fa and all of the receiver status, and the corresponding output ports and interrupt are reset. No additional
characters can be received until the receiver is enabled
again.
Multidrop Mode·
The DUART is equipped with a wake up mode used for
multidrop applications. This mode is selected by programming bits MR1A [4:3] or MR1B[4:3] to '11' for
channels A and B respectively. In this mode of operation,
a 'master' station transmits an address character followed
by data characters for the addressed 'slave' station. The
slave stations, with receivers that are normally disabled,
examine the received data stream and 'wakeup' the CPU
(by setting RxRDY) only upon receipt of an address
character. The CPU compares the received address to its
station address and enables the receiver if it wishes to
receive the subsequent data characters. Upon receipt of
another addreSS character, the CPU may disable the receiver
to initiate the process again.
A transmitted character consists of a start bit, the
programmed number of data bits, an address/data (AID)
bit, and the programmed number of stop bits. The polarity
of the transmitted A/D bit is selected by the CPU by
bit
MR1A[2] /MR1 B[2].
MR1A[2] /
programming
MR1B[2] = a transmits a zero in the A/D bit position,
which identifies the corresponding data bits as data, while
MR1A[2]/MR1B[2] =-1 transmits a one in the A/D bit
position, which identifies the corresponding data bits as
an address. The CPU should program the mode register
prior to loading the corresponding data bits into the THR.
In this mOde, the receiver continuously looks at the
received data stream, whether It is enabled or disabled. If
disabled, it sets the RxRDY status bit and loads the
character into the RHR FIFO if the received A/D bit is
a one (address tag), but discards the received character
if the received AID bit is a zero (data tag)
If enabled,
all received characters are transferred to the CPU via the
RHR. In either case, the data bits are loaded into the data
F I Fa while the A/D bit is loaded into the status F I Fa
position normally used for parity error (SRA[5] or
SRB[5]l. Framing error, overrun error, and break detect
operate normally whether or not the receiver is enabled.
Programming
The operation of .he DUART is programmed by writing
control words into the appropriate registers. Operational
feedback is provided via status registers which can be read
by the CPU. The addressing of the registers is described in
Table 1.
The contents of certain control registers are initialized to
zero on RESET. Care should be exercised if the contents
of a register are changed during operation, since certain
changes may cause operational problems. For example,
changing the number of bits per character while the transmitter is active may cause the transmission of an incorrect
character. I n general, the contents of the M R, the CSR,
and the OPCR should only be changed while the receiver(s)
and transmitter(s) are not enabled, and certain changes to
the ACR should only be made while the CIT is stopped.
Mode registers 1 and 2 of each channel are accessed via
independent auxiliary pointers. The pointer is set to MRlx
by RESET or by issuing a 'reset pointer' command via the
corresponding command register. Any read or write of the
mode register while the pointer is at -MR1 x switches the
pointer to MR2x. The pointer then remains at MR2x, so
that subsequent accesses are always to MR2x unless the
pointer is reset to MR1 x as described above.
Mode, command, clock select, and status registers are
duplicated for each channel to provide total independent
operation and control. Refer to Table 2 for register bit
d~scriptions.
MR1A-Channel A Mode Register 1
M R 1A is accessed when the channel A M R pointer points
to MR1. The pointer is set to MR1 by RESET or by a
'set pointer' command applied via CRA. After reading or
writing MR1A, the pointer will point to MR2A.
MR1A(7)-Channel A Receiver Request-to-Send Control This bit controls the deactivation of the RNSAN output
(OPO) by the receiver. This output is normally asserted by
setting aPR [0]. MR1A[71 =1 causes RTS/\N to be negated
upon receipt of a valid start bit if the channel A FIFO is
full. However, aPR [0] is not reset and RTSAN will be
asserted again when an empty F I Fa position is available.
This feature can be used for flow control to prever)t overrun in the receiver by using the RTSAN output signal to
control the CTSN input of the transmitting device.
MR1A[6] - Channel A Receiver Interrupt Select - This
bit selects either the channel A receiver .ready status
7-29
UM2681 SERIES
or
(RXRDY)
the channel A FIFO full status (FFULL) to
be used for CPU' interrupts. It also causes the selected bit
to be output on OP4 if it is programmed as an interrupt
output via the OPCR.
MR1A[5] - Channel A Error Mode Select - This bit
selects the operating mode of the three F I FOed status
bits (FE, PE, received break) for channel A. In the
'character' mode, status is provided. on a character-bycharacter basis: the status applies only to the character
at the top of the FIFO. In the 'block' mode, the status
provided in the SR for these bits is the accumulation
(logical OR) of the status for all characters coming to the
top of the FIFO since the last 'reset error' command for
channel A was issued.
grammed. It has no effect if the 'no parity' mode is programmed. In the special multidrop mode it selects the
polarity of the AID bit.
MR1A[1:0] - Channel A Bits per Character Select - This
field selects the number of data bits per character to be
transmitted and received. The character length does not
include the start, parity, and stop bits.
M R2A - Channel A Mode Register 2
MR2A is accessed when the channel A MR pointer points
to MR2, which occurs after any access to MR1A. Accesses
to MR2A do not change the pointer.
.MR1A[4:3] - Channel A Parity Mode Select - If 'with
parity' or 'force parity' is selected, a parity bit is added to
the transmitted character and the receiver performs a
parity check on incoming data. MR1 A[4:3] = 11 selects
channel A to operate in the special multidrop mode
described in the Operation section.
MR2A[7:6] - Channel A Mode Select - Each channel
of the DUART can operate in one of four modes.
MR2A[7:6] =00 is the normal mode, with the transmitter
and receiver operating independently .. MR2A[7:6] =01
places the channel in the automatic echo mode, which
automatically retransmits the received data. The following
conditions are true while in automatic echo mode:
MR1A[2] - Channel A Parity Type Select - This bit
selects the parity type (odd or even) if the 'with parity'
mode is programmed by MR1A[4:3], and the polarity
of the forced parity bit if the 'force parity' mode is pro-
1. Received data is reclocked and retransmitted on the
TxDA output.
2. The receive clock is used for the transmitter.
3. The receiver must be enabled, but the transmitter need
Table 1.UM2681 Register Addressing
A3
A2
A1
AO
Read (RDN=O)
Write (WRN =0)
0
0
0
0
Mode Register A (MR1A, MR2A)
Mode Register A (M R1A, M R2A)
0
0
0
1
Status Register A (SRA)
Clock Select Reg. A (CSRA)
0
0
1
0
* Reserved *
Command Register A (CRA)
0
0
1
1
RX Holding Register A (RHRA)
TX Holding Register A (TH RA)
0
Input Port Change Reg. (IPCR)
Aux. Control Register (ACR)
0
1
0
'0
1
0
1
Interrupt Status Reg. (ISR)
Interrupt Mask Reg. (IMR)
0
1
1
0
Counter/TimerUpper (CTU)
CIT Upper Register (CTUR)
0
1
1
1
CounterlTimer Lower (CTL)
CIT Lower Register (CTLR)
0
1
0
0
Mode Register B (MR1 B, MR2B)
Mode Register B (MR1 B, MR2B)
1
0
0
1
Status Register B (SR B)
Clock Select Reg. B (CSRB)
1
0
1
0
* Reserved *
Command Register B (CRB)
1
0
1
1
RX Holding Register B (RHRB)
TX Holding Register B (THRB)
1
1
0
0
* Reserved *
* Reserved *
1
1
0
1
Input Port
Output Port Conf. Reg. (OPCR)
1
1
1
0
Start Counter Command
Set Output Port Bits Command
1
1
1
1
Stop Counter Command
Reset Output Port Bits Command
7-30
SUMC
UM2681 SERIES
Table 2. Register Bit Formats
MR1A
MR1B
BIT7
BIT6
BIT5
RX RTS
Control
RXINT
Select
Error
Mode
O=no
1=yes
O=RXRDY
1=FFULL
BIT7
BIT6
Channel Mode
MR2A
MR2B
OO=Normal
01 =Auto echo
10=Local loop
11 =Remote loop
BIT4
BIT2
BIT3
Parity
Type
Parity Mode
O=char
1=block
OO=with parity
01 =force parity
10=no parity
11=r'nulti-drop mode
BIT5
BIT4
TxRTS
Control
CTS
Enable Tx
O=no
1=yes
O=no
1=yes
BIT1
Bits Per Char.
O=even
00=5
01=6
10=7
11=8
1=odd
BIT2
BIT3
BITO
BIT1
BITO
Stop Bit Length*
0=0.563
1=0.625
2=0.688
3=0.750
4=0.813
5=0.875
6=0.938
7=1.000
8=1.563
9=1.625
A=1.688
B=1.750
BIT2
BIT1
C=1.813
D=1.875
E=1.938
F=2.000
*Add 0.5 to values shown for 0-7 if channel is programmed for 5 bits/char.
BIT7
BIT6
BIT5
BIT4
Receiver Clock Select
CSRA
CSRB
BIT6
See text
BIT5
BIT4
Miscellaneous Commands
not usedmust be 0
BIT1
BITO
Disable Rx
Enable Rx
O=no
1=yes
O=no
1=yes
O=no
1=yes
O=no
1=yes
BIT2
BIT1
BITO
Disable Tx
See test
BIT2
BIT3
Enable Tx
BIT6
BIT5
BIT4
BIT3
Received
Break
Framing
Error
Parity
Error
Overrun
Error
TxEMT
TxRDY
FFULL
RxRDY
O=no
1=yes
*
O=no
1=yes
*
O=no
1=yes
*
O=no
1=yes
O=no
1=yes
O=no
1=yes
O=no
1=yes
O=no
1=yes
BIT7
SRA
SRB
BITO
Transmitter Clock Select
See text
BIT7
CRA
CRB
BIT3
*These status bits are appended to the corresponding data character in the receive FIFO. A read of the status register
provides these bits (7:5) from the top of the FIFO together with bits 4:0. These bits are cleared by a reset error
status command. In character mode they are discarded when the corresponding data character is read from the FIFO.
OPCR
BIT7
BIT6
BIT5
BIT4
OP7
OP6
OP5
OP4
O=OPR (7)
1=TxRDYB
0=OPR(6)
1=TxRDYA
O=OPR (5)
0=OPR(4)
1=RxRDY/ 1=RxRDY/
FFULLB
FFULLA
7-31
BIT3
BIT2
BITO
BIT1
OP3
OP2
OO=OPR (3)
01 =C/T OUTPUT
10=TxCB (lX)
11 =RxCB(1 X}
OO=OPR [2]"
01=TxCA (16X)
10=TxCA (1X)
11 =RxCA (1 X)
UM2681 SERIES
Table 2. Register Bit Formats (Continued)
BIT7
BIT6
BRG Set
Select
ACR
IPCR
ISR
IMR
BIT4
Counter/Timer
Mode and Source·
0=set1
1=set2
81T7
BIT5
BIT3
Delta
IP31nt
See table 4
BIT2
Delta
IP21nt
BIT1
BITO
Delta
IP11nt
Delta
IPO Int
O=off
1=on
O=off
1=on
O=off
1=on
O=off
1=on
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BITO
Delta
IP3
Delta
IP2
Delta
IP1
Delta
IPO
IP3
IP2
IP1
IPO
O=nO'
1=yes
O=no
l=yes
O=no
l=yes
O=no
1=yes
O=low
l=high
O=low
l=high
O=low
l=high
O=low
1=high
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BITO
Input
Port
Change
Delta
Break B
TxRDYB
Counter
Ready
Delta
BREAK
RxRDYI
FFULLA
TxRDYA
O=no
l=yes
O=no
1=yes
O=no
1=yes
O=no
l=yes
O=no
l=yes
O=no
1=yes
O=no
l=yes
O=no
l=yes
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BITO
In Port
Change
Int
Delta
Break B
Int
RxRDYI
FFULLB
Int
TxRDYB
Int
Counter
Ready
Int
Delta
Break A
Int
O=off
1=on
O=off
l=on
O=off
l=on
O=off
l=on
O=off
l=on
O=off
1=on
O=off
1=on
O=off
1=on
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BITO
C/T[15}
C/T[14]
C/T[13]
C/T[12]
C/T[11]
C/T[10]
C/T[9]
C/T[S]
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BITO
C!T[7]
C/T[6]
C!T[5]
C/T[4]
C/T[3]
C/T[2]
C/T[1]
C/T[O]
RxRDYI
FFULLB
RxRDY/
FFULLA
Int
TxRDYA
Int
CTUR
CTLR
7-32
UM2681 SERIES
MR2A[5) - Channel A Transmitter Request-to-Send
Control - This bit controls the deactivation of the RTSAN
output (OPO) by the transmitter. This output is normally
asserted by setting OPR [0] ) and negated by resetting
OPR [0] . MR2A [50=1 causes OPR [0] to be reset automatically one bit time after the characters in the channel
A transmit shift register and in the THR, if any, are completely transmitted, including the programmed number of
stop bits, if the transmitter is not enabled. This feature can
be used to automatically terminate the transmission of a
message as follows:
not be enabled.
4. The channel A TxR DY and TxEMT status bits are
inactive.
5. The received parity is checked, but is not regenerated
for transmission, i.e., transmitted parity bit is as
received.
6. Character framing is checked, but the stop bits are
retransm itted as received.
7. A received break is echoed as received until the next
valid start bit is detected.
8. CPU to receiver communication continues normally,
but the CPU to transmitter link is disabled.
Two diagnostic modes can also be configured. MR2A
[7 :6] = 1 selects local loopback mode. I n this mode:
a
1. The transmitter output is internally connected to the
receiver input.
2. The transmit clock is used for the receiver.
3. The TxDA output is held high.
4. The RxDA input is ignored.
5. The transmitter must be enabled, but the receiver need
not be enabled.
6. CPU to transmitter and receiver communications
conti nue normally.
The second diagnostic mode is the remote loopback mode,
selected by MR2A[7:6] =11. In this mode:
1. Received data is relocked and retransmitted on the
TxDA output.
2. The receive clock is used for the transmitter.
3. Received data is not sent to the local CPU, and the
error status conditions are inactive.
4. The received parity is not checked and is not regenerated
for transm ission, i.e., transm itted parity bit is as
received.
5. The receiver must be enabled.
6. Character framing is not checked, and the stop bits are
retransmitted as received.
7. A received break is echoed as received unti I the next
valid start bit is detected.
The user must exercise care when switching into and out
of the various modes. The selected mode will be activated
immediately upon mode selection, even if this occurs in
the middle of a received or transmitted character. Likewise,
if a mode is deselected, the device will switch out of the
mode immediately. An exception to this is switching out
of autoecho or remote loopback modes: if the de-selection
occurs just after the receiver has sampled the stop bit
(indicated in autoecho by assertion of RxRDYl. and the
transmitter is enabled, the transmitter will remain in
autoecho mode until the entire stop bit has been
retransm i tted.
1.
2.
3.
4.
5.
Program auto-reset mode: MR2A [5] = 1.
Enable transmitter.
Assert RTSAN: OPR [0] = 1.
Send message.
Disable transm itter after the last character is loaded
into the channel A THR.
6. The last character will be transmitted and OPR [0]
will be reset one bit time after the last stop bit, causing
RTSAN to be negated,
MR2A[4) - Channel A Clear-to-Send Control - If this
bit is 0, CTSAN has no effect on the transmitter. If this
bit is a 1, the transmitter checks the state of CTSAN
(IPO) each time it is ready to send a character. If IPO is
asserted (low), the character is transmitted. If it is negated
(high). the TxDA output remains in the marking state and
the transmission is delayed until CTSAN goes low. Changes
in CTSAN while a character is being transmitted do not
affect the transmission of that character.
MR2A[3:0) - Channel A Stop Bit Length Select - This
field programs the length of the stop bit append.ed to the
transmitted character. Stop bit lengths of 9/16 to 1 and
1-9/16 to 2 bits, in increments of 1/16 bit, can be programmed for character lengtbs of 6, 7, and 8 bits. For a
characterlength of 5 bits, 1-1/16 to 2 stop bits can be
programmed in increments of 1/16 bit. The receiver only
checks for a 'mark' condition at the center of the first
stop bit position (one bit time after the last d'ata bit, or
after the parity bit if parity is enabled) in all cases.
If an external 1 X clock is used for the transmitter, MR2A
[3] =0 selects one stop bit and M R2A [3] = 1 selects two
stop bits to be transmitted.
M R1B - Channel B Mode Register 1
M R1B is accessec;J when the channel B MR pointer points
to MR1. The pointer is set to MR1 by RESE1 or by a
'set pointer' command applied via CRB. After reading or
writing MR1 B, the pointer will point to MR2B.
The bit definitions for this register are identical 'to the bit
definitions for MR1A,except that all control actions apply
7-33
(DUMC
UM2681 SERIES
to the channel B receiver and transmitter and .the corresponding inputs and outputs.
The transmitter clock is always a 16X clock except for
CSRA[3:0] = 1111.
MR2B~ Channel B Mode Register 2
MR2B is accessed when the channel B MR pointer points
to MR2, which occurs after any ·access to MRl B. Accesses
to MR2B do not change the pointer.
CSRB - Channel B Clock Select Register
CSBR[7:4] - Channel B Receiver Clock Select - This
field selects the baud rate clock for the channel B receiver.
The field definition is as per CSRA[7:4] except as follows:
The bit definitions fot this register are identical to the bit
definitions for MR2A. except that all control actions apply
to the channel B receiver and transmitter and the corresponding inputs and outputs.
Baud Rate
ACR [7] =0
ACR [7] =1
CSRB[7:4]
o
CSRA - Channel A Clock Select Register
CSRA[7:4] - Channel A Receiver Clock Select - This
field selects the baud rate clock for the channel A receiver
as follows:
Baud Rate
CLOCK = 3.6864MHz
ACR[7] =1
ACR[7] =0
CSRA[7:4]
0
0
0
0
0
0
0
0
0
0
50
75
110
110 .
0
134.5
134.5
0
1
1
220
150
0
0
0
300
300
0
0
1
600
600
IP6 -16X
IP6 - 16X
IP6 -lX
IP6 -lX
The receiver clock is always a 16X clock except for CSR B
[7:4)=1111.
CSRB[3:0] - Channel B Transmitter Clock Select - This
field selects the baud rate clock for the channel B transmitter. The field definition is as per CSRA[7:4) except as
follows:
Baud Rate
ACR[7] =0
ACR[7] =1
CSRB[3:0]
o
IP5 - 16X
IP5-l6X
IP5 -lX
IP5- lX
0
1,200
1,200
1
1
1,050
2,000
0
0
0
2,400
2,400
0
0
1
4,800
4,800
CRA - Channel A Command Register
0
7,200
1,800
9,600
9,600
CRA is a register used to supply commands to channel A.
Multiple commands can be specified in (; sirlgle write to
CRA as long as the commands are non-conflicting, e.g.,
the enable transmitter' and 'reset transmitter' commands
cannot bespecified in a single command word.
0
0
0
0
0
0
0
0
38.4K
19.2K
Timer
Timer
IP4-16X
IP4-16X
IP4-1X
IP4-1 X
The receiver clock is always a 16X clock except for CSRA
[7:4] = 1111.
CSRA[3:0] - Channel A Transmitter Clock Select - This
field selects the baud rate clock for the channel A transmitter. The field definition is as per CSRA[7:4] except as
follows:
Baud Rate
ACR [7] =0
ACR [7] =1
CSRA[3:0]
o
IP3 - 16X
IP3 - 16X
IP3 -lX
IP3 -lX
The transmitter clock is always a 16X clock except for
CSRB[3:0) =1111.
CRA[6:4] - Channel A Miscellaneous Commands - The
encoded value of this field may be used to specify a single
command as follows:
CRA[6:4]
Command
000 No command.
0
Reset MR pointer. Causes the channel A MR
pointer to point to MR1.
0 Reset receiver. Resets the channel A receiver
as if a hardware reset had been appl ied. The
receiver is disabled and the FIFO is flushed.
o 1 1 Reset transmitter. Resets the channel A
transm itter as if a hardware reset had been
applied.
o
o
7-34
UM2681 SERIES
1 0 0
1 0 1
1 0
1 1
Reset error status.
Clears the channel A.
Received Break, Parity Error, Framing Error,
and Overrun Error bits in the status register
(SRA[7:4]). Used in character mode to clear
OE status (although RB, PE, and FE bits will
also be cleared) and in block mode to clear all
error status after a block of data has been
received.
Reset channel A break change interrupt.
Causes the channel A break detect change bit
in the interrup status register (ISR [2]) to be
cleared to zero.
Start break.
Forces the TXDA output low
(spacing).
If the transmitter is empty the
start of the break condition will be delayed up
to two bit times. If the transmitter is active
the break begins when transmission of the
character is completed. If a character is in the
TH R, the start of the brea k wi II be delayed
until that character, or any others loaded
subsequently are transmitted. The transmitter
must be enabled for this command to be
accepted.
Stop Break.
The TXDA line will go high
(marking) within two bit times. TXDA will
remain high for one bit time before the next
character, if any, is transmitted.
CRA[3] - Disable Channel A Transmitter - This command terminates transmitter operation and resets the
Tx R DY and TxEMT status bits. However, if a character
is being transmitted or if a character is in the THR when
the transmitter is disabled, the transmission of the
character(s) is completed before assuming the inactive
state.
CRA[2] - Enable Channel A Transmitter - Enables
operation of the channel A transmitter.
The TxRDY
status bit will be aserted.
CRA[1] - Disable Channel A Receiver - This command
terminates operation of the receiver immediately - a
character being received will be 100.5t. The command has
no effect on the receiver status bits or any other control
registers. If the special multidrop mode is programmed,
the receiver operates even if it is disabled. See Operation
section.
CRA[O] - Enable Channel A Receiver - Enables operation
of the channel A receiver. If not in the special wakeup
mode, this also forces the receiver into the search for startbit state.
CRB - Channel B Command Register
Multiple commands can be specified in a single write to
CRB as long as the commands are non-conflicting, e.g., the
'enable transmitter' and 'reset transmitter' commands
cannot be specified in a single command word.
The bit definitions for this register are identical to the
bit definitions for CRA, except that all control actions
apply to the channel B receiver and transmitter and the
corresponding inputs and outputs.
SRA - Channel A Status Register
SRA[7] - Channel A Received Break - This bit indicates
that an all zero character of the programmed length has
been received without a stop bit. Only a single FIFO
position is occupied when a break is received: further
entries to the FIFO are inhibited until the RxDA line
returns to the marking state for at least one-half a bit time
(two successive edges of the internal or external 1 x clock).
When this bit is set, the channel A 'change in break' bit in
the ISR (ISR[2]) is set. ISR[2] is also set when the end
of the break condition, as defined above, is detected.
The break detect circuitry can detect'breaks that originate
in the middle of a received character. However, if a break
begins in the middle of a character, .it must persist until at
least the end of the next character time in order for it to
be detected.
SRA[6] - Channel A Framing Error - This bit, when set,
indicates that a stop bit was not detected when the correspond i ng data character in the F I F 0 was received. The
stop bit check is made. in the middle of the first stop bit
.position.
SRA[5] - Channel A Parity Error - This bit is set when
the 'with parity' or 'force parity' mode is programmed and
the corresponding character in the FIFO was received with
incorrect parity.
In the special multidrop mode the parity error bit stores
the received AID bit.
SRA[4] - Channel A Overrun Error - This bit, when set,
indicates that one or more characters in the received data
stream have been lost. It is set upon receipt of a new
character when the FIFO is full· and a character is already in
the receive shift register waiting for an empty. FIFO
position. When this occurs, the character in the receive
shift register (and its break detect, parity error and framing
error status, if any) is lost.
This bit is cleared by a 'reset error status' command.
CRB is a register used to supply commands to channel B.
7-35
UM2681 SERIES
SRA[3] - Channel A Transmitter Empty (TxEMTA) This bit will be set when the channel A transmitter' underruns, i.e., both the transmit holding register (THR) and
the transmit shift register are empty. It is set after
transmission of the last stop bit of a character if no
character is in the TH R awaiting transmission. It is reset
when the TH R is loaded by the CPU or when the
transmitter is disabled.
The complement of OPR [6]
The channel A transmitter interrupt output. which is
the complement of TxRDY A. When in this mode OP6
acts as an open collector output. Note that this output
is not masked by the contents of the 1M R.
OPCR [5] - OP5 Output Select - This bit programs the
OP5 output to provide one of the following:
SRA[2] - Channel A Transmitter Ready (TxRDYA) This bit, when set, indicates that the THR is empty and
ready to be loaded with a character. ,This bit is cleared
when the TH R is loaded by the CPU and is set when the
character is transferred to the transm it sh ift register.
TxRDY is reset when the transmitter is disabled and is
set when the transmitter is first enabled, viz .. characters
loaded into the'THR while the transmitter is disabled
will not be transmitted.
The complement of OPR [5]
The channel B receiver interrupt output. which is the
complement of ISR [5]. When in this mode OP5 acts
as an open collector output. Note that this output is
not masked by the contents of the 1M R.
OPCR[4] - OP4 Output Select - This bit programs the
OP4 output to provide one of the following:
SRA[1] - Channel A FIFO Full (FFULLA) - This bit is
set when a character is transferred from the receive shift
register to the receive FIFO and the transfer causes the
FIFO to become full. i.e .. all three FIFO positions are
occupied. It is reset when the CPU reads the RHR. If a
character is waiting in the receive shift register because the
FIFO is full, FFULL will not be reset when the CPU reads
the RHR.
The complement of OPR [4]
The channel A receiver interrupt output. which is the
complement of ISR [1). When in this mode OP4 acts as
an open collector output. Note that this output is not
masked by the contents of the 1M R.
OPCR [3:2] - OP3 Output Select - This field programs
the OP3 output to privde one of the following:
SRA[O] - Channel A Receiver Ready (RxRDYA) - This
bit indicates that a character has been received and is
waiting in the FIFO to be read by the CPU. It is set when
the character is transferred from the receive shift register
to the FIFO and reset when the CPU reads the RHR. if
after this read there are no more characters still in the
FIFO.
The complement of OPR [3]
The counter/timer output. in which case OP3 acts as
an open collector output. In the timer mode. this output is a square wave at the programmed frequency.
In the counter mode. the output remains high until
terminal count is reached, at which time it goes low.
The output returns to the high state when the counter
is stopped by a stop counter command. Note that this
output is not masked by the contents of the 1M R.
The 1X clock for the channel B transmitter, which is
the clock that shifts the transmitted data. If data is
not being transmitted, a free running 1 X clock is output.
The 1 X clock for the channel B receiver, wh ich is the
clock that samples the received data. It data is not
being received, a free running 1X clock is output.
SR B - Channel B Status Register
The bit definitions for this register are identical to the bit
definitions for SRA. except that all status applies to the
channel B receiver and transmitter and the corresponding
illputs and outputs.
OPCR - Output Port Configuration Register
OPCR[7] - OP7 Output Select - This bit programs the
OP7 output to provide one of the following:
OPCR [1 :0] - OP2 Output Select - Th is field programs the
OP2 output to provide one of the followi ng:
The complement of OPR [7]
The channelB transmitter interrupt output which is the
complement of TxRDYB. When in this mode OP7
acts as an open collector output. Note that this output
is not masked by the contents of the 1M R.
The complement of OPR (2)
The 16X clock for the channel A transmitter. This is
the clock selected by CSRA[3:0), and will be a 1X
clock if CSRA [3:0) = 1111.
The 1 X clock for the channel A transmitter, which is
the clock that shifts the transmitted data. If data is
not being transmitted, a free running 1 X clock is output.
OPCR[6] - OPG Output Select - This bit programs the
OP6 output to provide one of the following:
7-36
UM2681 SERIES
The 1X clock for the channel A receiver, which is the
clock that samples the received data. If data is not being
received, a free running 1 X clock is output.
IPCR [3:0] - IP3, IP2, IP1, IPO Current State - These bits
provide the current state of the respective inputs.
The
information is .unlatched and reflects the state of the input
pins at the time the IPCR is read.
ACR - Auxiliary Control Register
ACR [7]
-
Baud Rate Generator Set Select -
ISR - Interrupt Status Register
Th is bit
selects one of two sets of baud rates to be generated by the
This register provides the status of all potential interrupt
BRG:
sources.
Set 1: 50,110,134.5,200,300,600, 1.05K, 1.2K, 2.4K,
4.8K, 7.2K,9.6K, and 38.4K baud.
The contents of this register are masked by the
interrupt mask register (IMR).
If a bit in the ISR is a '1'
and the corresponding bit in the IMR is also a '1', the
INTRN output will be asserted.
Set 2: 75,110,134.5,150,300,600, 1.2K, 1.8K, 2.0K,
If the corresponding
bit in the IMR is a zero, the state of the bit in the ISR
has no effect on the INTRN output.
2.4K, 4.8K, 9.6K, and 19.2K baud.
Note that the IMR
does not mask the reading of the ISR - the true status
The selected set of rates is available for use by the channel
will be provided regardless of the contents of the IMR.
A and B receivers and transmitters as described in CSRA
The contents of this register are initialized to 00 16 when
and CSRB. Baud rate generator characteristics are given in
the DUART is reset.
Table 3.
ACR[6:4]
Select -
-
Counter/Timer Mode and Clock Source
This field selects the operating mode of the
counter/tirner and its clock source as shown in Table
ISR[7] -
Input Port Change Stat~s -
This bit is a '1'
when a change of state has occurred at the IPO, IP1, IP2,
or IP3 inputs and that event has been selected tocause an
interrupt by the programming of ACR [3:0].
4.
The bit is
. cleared when the CPU reads the IPCR.
ACR[3:0] Enable -
IP3, IP2, IP1, IPO Change of State Interrupt
Th is field selects which bits of the I nput Port
Change register (IPCR) cause the input change bit in the
interrupt status register (ISR [7]) to be set.
ISR[6] -
Channel B Change in Break - This bit, when
set, indicates that the channel B receiver has detected the
If a bit is in
beginning or the end of a received break. It is reset when
the 'on' state, the setting of the corresponding bit in the
the CPU issues a channel B 'reset break change interrupt'
IPCR will also result in the setting of ISR [7] ,which results
command.
in the generation of an interrupt output if 1M R [7] =1. If
a bit.is in the 'off' state, the setting of that bit in the IPCR
has no effect on ISR [7] .
ISR[5] - Channel B Receiver Ready or FIFO Full .:... The
function of this bit is programmed by MR1 B[6]. If programmed as receiver ready, it indicates that a character
IPCR - Input Port Change Register
has been received in channel B and is waiting in the FI FO
to be read by the CPU.
IPCR[7:4] - IP3, IP2, IP1, IPO Change of State - These
It is set when the character is
transferred from the receive shift register to the FIFO and
bits are set when a change of state, as defined in the Input
reset when the CPU reads the R HR. If after this read there
Port section. of this data sheet, occurs at the respective
are more characters still in the FIFO the bit will be set
input pins. They are cleared when the IPCR is read by the
again after the FIFO is 'popped'. If programmed as FIFO
CPU.
fu II, it is set when a character is transferred from the
A read of the IPCR also clears ISR[7], the input
change bit in the interrupt status register.
receive holding register to the receive FIFO and the transfer
causes the channel B FIFO to become full, i.e., all three
The setting of these bits can be programmed to generate
FIFO positions are occupied.
an interrupt to the CPU.
reads the RHR.
7-37
'It is reset when the CPU
If a character is waiting in the receive
UM2681 SERIES
Table 3. Baud Rate Generator Characteristics Crystal or Clock:: 3.6864 MHz
Actual16X Clock (KHz)
Nominal Rate (Baud)
Error (Percent)
50
0.8
0
75
1.2
0
110
1.759
-0.069
134.5
2.153
0.059
150
2.4
0
200
3.2
0
300
4.8
0
600
9.6
0
1050
16.756
-0.260
1200
19.2
0
1800
28.8
2000
32.056
0
0.175
2400
38.4
0
4800
76.8
0
7200
115.2
0
9600
153.6
0
19.2K
307.2
0
38.4K
614.4
0
Table 4. ACR [6:4] Field Definition
ACR [6:4]
Clock Source
Mode
0
0
0
Counter
External (IP2)
0
0
1
Counter
TXCA - 1 X clock of channel A transmitter
0
1
0
Counter
TXCB - 1X clock of channel B transmitter
0
1
1
Counter
Crystal or external clock (Xl/ClK) divided by 16
1
0
0
Timer
External (IP2)
1
0
1
Timer
External (IP2) divided by 16
1
1
0
Timer
Crystal or external clock (Xl/ClK)
1
1
1
Timer
Crystal or external clock (Xl /ClK) divided by 16
7-38
SUMC
UM2681 SERIES
shift register because the FIFO is full, the bit will be set
ISR [0] -
again when the waiting character is loaded into the FIFO.
duplicate of TxRDYA (SRA[2]).
ISR[4] -
Channel B Transmitter Ready - This bit is a
Channel A Transmitter Ready - This bit is a
IMR - Interrupt Mask Register
duplicate of TxRDYB (SRB[2]).
The programming of this register selects which bits in the
ISR cause an interrupt output.
ISR[3] - Counter Ready - In the counter mode, this bit
If a bit in the ISR is a
'1' and the corresponding bit in the IMR is also a '1', the
is set when the counter reaches terminal count and is
INTRN output will be asserted.
reset when the counter is stopped by a stop counter
in the IMR is a zero, the state of the bit in the ISR has no
command.
effect on the I NTR N output. Note that the 1M R does not
If the corresponding bit
mask the programmable interrupt output OP3-0P7 or the
reading of the ISR.
In the timer mode, this bit is set once each cycle oJ the
generated square wave (every other time that the counter/
timer reaches zero count).
The bit is reset by a stop
CTUR and CTLR - Counter/Timer Registers
counter command. The command, however, does not stop
the counter/timer.
The CTU Rand CT L R hold the eight MSBs and .eight LSBs
respectively of the value to be used by the counter/timer in
either the counter or timer modes of operation
The
minimum value which may be loaded into the CTUR/CTLR
ISR[2] - Channel A Change in Break - This bit, when set,
indicates that the channel A receiver has detected the
registers is 0002 16 . Note that these registers are write-only
beginning or the end of a received break. It is reset when
and cannot be read by the CPU.
the CPU issues a channpl
f::"
'reset break change interrupt'
command.
In
the
timer
(programmable divider) mode, the CIT
generates a square wave with a period of twice the value
(in clock periods) to the CTUR and CTLR. If the value in
ISR[1] - Channel A Receiver Ready or FIFO Full - The
function of this bit is programmed by MR1A[6J.
If
programmed as receiver ready, it indicates that a character
It is set when the character is
transferred from the receive shift register to the F IF 0 and
reset when the CPU reads the RHR.
If after this read
be affected, but subsequent half periods will be.
mode the CIT runs continuously.
has been received in channel A and is waiting in the FIFO
to be read by the CPU.
CTUR or CTLR is changed, the current half-period will not
In this
Receipt of a start
counter command (read with A3-AO= 111 0) causes the
counter to terminate the current timing cycle and to
begin a new cycle using the values in CTUR and CTLR.
there are more characters still in the FIFO the bit will be
set again after the FIFO is 'popped'.
If programmed as
FIFO fu II, it is set when a character is transferred from the
receive holding register to the receive FIFO and the transfer
causes the channel' A FIFO to become full, i.e., a'il three
FIFO positions are occupied.
It is reset when the CPU
reads the RHR. If a character is waiting in the receive shift
The counter ready status bit (ISR [3]) is set once each
cycle of the square wave. The bit is reset by a stop counter
command (read with A3-AO=111).
ever, does not stop the CIT.
The command, how-
The generated square wave
is output on OP3 if it is programmed to be the CIT output.
register because the FIFO is full, the bit will be set again
when the waiting character is loaded into the FIFO.
7-39
UM2681 SERIES
In the counter mode, the CIT counts down the nUl1)ber of
previous count values are preserved and used for the next
pulses loaded into CTU Rand CTLR by the CPU. Counting
count cycle.
begins upon receipt of a start counter command.
reaching terminal count
Upon
(0000 16 ). the counter ready
The counter continues
In the counter mode, the current value of the upper and
counting past the terminal count until stopped by the CPU.
interrupt bit (ISR [3]) is set.
lower 8 bits of the counter (CTU, CTL) may be read by
If OP3 is programmed to be the output of the CIT, the
the CPU.
output remains high until terminal count is reached, at
when reading to prevent potential problems which may
which time it goes low.
The output returns to the high
occur if a carry from the lower 8-bits to the upper 8-bits
state and ISR [3] is cleared when the counter is stopped
occurs between the times that both halves of the counter
by a stop counter command.
The CPU may change the
are read.
It is recommended that the counter be stopped
However, note that a subsequent start counter
values of CTUR and CTLR at any time, but the new
command will cause the counter to begin a new count
count becomes effective only on the next start counter
cycle using the values in CTUR and CTLR.
command.
If new values have not been loaded, the
Ordering Information
Part Number
Package
UM2681-1
40 DIP
UM2681-2
28 DIP
UM2681-3
24 DIP
7-40
(l)UMC
UM652 0 / UM6520A
d",',,""''"'"''''''''.'''''
Peripheral Interface Adapte,(PIA)
Features
•
Direct replacement for Motorola MC6820
•
•
Single +5V power supply
•
Automatic "handshake.' control of data transfers
Programmable interrupt capability
•
Two 8-bit bi-directional I/O ports with individual data
•
Automatic initialization on power up
direction control
•
1 and 2 MHz versions
•
CMOS-compatible peripheral port A lines
General Description
The UM6520/A peripheral Interface
Adapter
(PIA)
Each I/O line may be programmed to be either an input
is
designed to provide a broad range of peripheral control to
or an output.
microcomputer systems.
are
Control of peripheral devices is
accomplished through two 8-bit bi-directional I/O ports.
Pin Configuration
In addition, four peripheral control lines
to
perform
"handshaking" during
data
transfers.
Block Diagram
VSS
PAO
CA1
CA2
PA1
IROA
PA2
IROB
PA3
RSO
PA4
RS1
PA5
PA6
RES
DO
PA7
01
02
PBO
provided
PB1
03
PB2
04
PB3
05
PB4
06
PB5
07
PB6
PB7
r/J2
CS1
CB1
CS2
CB2
VCC
CSO
RlW
1881T
CONTROL
DATA BUS
MICROPROCESSORS
UM650X
8-BIT
DATA PORT
UM6520!
6520A
8-BIT
DATA PORT
CONTROL
CONTROL
7-41
PERIPHERAL
DEVICESPRINTERS,
DISPLA YS, ETC.
(l)UMC
UM6520/ UM6520A
Absolute Maximum Ratings*
*Comments
Supply Voltage Vee . . . . . . . . . . . . . , -0.3V to +7.0V
Input Voltage VIN . . . . . . . . . . . . . . . -0.3V to +7.0V
Operating Temperature Range T A ....... O°C to +70°C
Storage Temperature Range TSTG .... -55°C to +{50°C
Note:
This device contains circuitry to protect the inputs against
damage due to high static voltages, however, it is advised
that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages to this
circuit.
Stress above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied and exposure to absolute maximum rating
conditions for extended i periods may affect device
reliability.
D.C. Characteristics
(Vee = 5.0V ± 5%, VSS = 0, T A = 0-70°C
unless otherwise noted)
Characteristics
Symbol
Input High Voltage
Note:
Min.
Max.
Units
VIH
+2.0
Vee
V
Input Low Voltage
VIL
-0.3
+0.8
V
Input Leakage Current
VIN = 0 to 5.0V
R/W, Reset, RS o , RS l , CS o , CS l , CS 2 , CAl, CB l , z Positive Transition
T AEW
180
-
90
-
Delay Time, if>z Positive Transition to Date Valid on Bus
TEDR
-
395
-
.190
ns
Peripheral Data Setup Time
TPDSU
300
-
150
ns
Data Bus Hold Time
THR
10
-
10
-
if>z Negative Transition to CA2 Negative Transition
Delay Time, if>z. Negative Transition to CA2 Positive Transition
TCA2
-
LO
-
0.5
Ils
T RS1
Ils
1.0
-
0.5
tr ,~
-
1.0
Rise ana Fall Time for CA 1 and CA2 Input Signals
0.5
Ils
Delay Time from CA1 Active Transition to CA2 Positive
Transition
T RS2
-
2.0
-
1.0
Ils
trE ' tfE
-
25
-
25
ns
0.440
Ils'
Delay Time,
Rise and Fall Timefor
if>2 Input
ns
ns
WRITE TIMING CHARACTERISTICS
if>z Pulse Width,
-
180
-
0.200
TAEW
90
-
ns
Delay Time, Data Valid to
if>2 Negative Transition
Delay Time, Read/Write Negative Transition to if>2 Positive
TDSU
300
-
150
-
ns
Transition
TWE
130
-
65
THW
10
-
10
-
ns
Data Bus Hold Time
Delay Time,
if>z Negative Transition to Peripheral Data Valid
Delay Time, if>z Negative Transition to Peripheral Data Valid
TpDW
-
1.0
-
0.5
Ils
CMOS (Vcc-30%) PAO-PA7, CA2
TCMOS
-
2.0
-
1.0
Ils'
Delay Time, if>z Positive Transition to CB2 Negative Transition
TCB2
-
1.0
-
0.5
Delay Time, Peripheral Data Valid to CB2 Negative Transition
TDC
0
1.5
0
0.75
Delay Time, Address Valid to
TE
if>z Positive Transition
ns
TRS1
-
1.0
-
0.5
Rise and Fall Time for CB1 and CB2 Input Signals
tr , tf
1.0
-
0.5
Delay Time, CB1 Active Transition to CB2 Positive Transition
TRS2
-
2.0
-
1.0
Il s
Il s
Ils
Il s
Il s
TRW
50
-
25
-
ns
Delay Time,
Delay Time,
Transition
if>z Positive T.ransition CB2 Positive Transition
if>z Negative Transition to Read/Write Positive
Test Load
5V
5V
PIN - - -___- - -.....-i2 clock and is used to trigger
all data transfers between the microprocessor and the
PIA.
R/W (ReadlWrite)
RSO, RS1 (Register Selects)
This signal is generated by the microprocessor and is used
to control the direction of data transfers. A high on the
R/IN signal permits the processor to read data supplied by
the PIA; a low on the R/W signal permits the processor to
Write into the PIA.
IROA, IAOB (Interrupt Requests)
I ROA and I ROB are interrupt lines generated by the PIA
for ports A and B respectively.· These signals are active
low signals and have open-drain outputs, thus allowing
multiple I RO signals from multiple PIA's to be wire-ORed
together before connecting to the processor I RQ signal
input.
.
These two signals are used to select the various registers
inside the PIA.
Internal Architecture
The UM6520/A is organized into two independent sections
referred to as the "A Side" and the "B Side." Each section
consists of a Control Register.(CRA, CRB), Data Direction
Register (DORA, DDRB), Output Register (ORA, ORB),
I nterrupt Status Control and the buffers necessary to drive
the Peripheral Interface buses. Figure 3 is a block diagram
of the UM6520/A.
I R O A - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - j INTERRUPTSTATUS
CONTROL A
CAl
CA2
OO __--~~-------,
01 __- - - - - .
02-------.1
03 _-----.I
04_------.
OATA BUS
BUFFERS
(OBB)
05_
06-------1
07 __- -__~__~--~
r-----~------~---PAO
_PAl
PERIPHERAL
OUTPUT
REGISTER A
(ORA)
PA2
PA3
PA4
PA5
PA6
PA7
OATAINPUT
REGISTER
(OIR)
PERIPHERAL
OUTPUT
REGISTER B
(ORB)
PB2
PB3
PB4
PB5
PB6
PB7
CSO
CSl
CS2
RSO
RSl
---..
RiW
CHIP
SELECT
ANO
R!W
CONTROL
INPUT BUS
ENABLE - - - - RESET
L -_ _ _ _ _ _- - .
INTERRUPT STATUS
CONTROL B,
.....------------..
IROB4-----------------------------------------------~
Figure 3. UM6520/UM6520A Block Diagram
7-45
CBl
CB2
UM6520/ UM6520A
CRA
7
6
IRQA1
I ROA2
4
5
CA2 Control
I
I
CRB
7
6
IROB1
IROB2
3
4
5
I
3
CB2 Control
I
I
I
2
DDRA
Access
1
CA1 Control
I
I
2
DDRB
Access
0
1
I
0
CB1 Control
I
I
I
Figure 4. Control Registers
Data Input Register
Peripheral Output Registers (ORA, ORB)
When the Microprocessor writes data into the UM6520/A,
the data which appears on the data bus during the Phase
Two clock pulse is latched into the Data Input Register.
It is then transferred into one of six internal registers of the
UM6520/A after the trailing edge of Phase Two. This assures
that the Mta on the peripheral output lines will make
smooth transitions from· high to low or from low to high
and the voltage will remain stable except when it is going
to the opposite polarity.
The Peripheral Output Registers store the output data
which appears on the Peripheral I/O port. Writing a "0"
into a bit in ORA causes the corresponding line on the
Peripheral A port to go low «
OAVl if that line is programmed to act as an output. A "1" causes the corresponding output to go high. The lines of the Peripheral
B port are controlled by ORB in the same manner.
Control Registers (CRA al"!d CRB)
Figure 4 illustrates the bit designation and functions in
the Control Registers.' The Control Registers allow the
miCroprocessor to control the operation of the Interrupt
Control inputs (CA 1, CA2, CB1, CB21. and Peripheral
Control outputs (CA2 i CB2l. Bit 2 in each register controls
the addressing of the Data Direction Registers (DDRA,
DDRB) and the Output Registers (ORA, ORBl. In
addition, two bits (bit 6 and 7) are provided in each control
register to indicate the status of the interrupt input lines
(CA 1, CA2, CB1, CB2l. These interrupt status bits (I ROA 1,
(I ROB1l are normally interrogated by the microprocessor
during the interrupt service routine to determine the source
of an active interrupt. These are the interrupt lines which
drive the interrupt input (I RO, NMll of the microprocessor.
Data Direction Registers (DORA, DDRB)
The Data Direction Registers allow the processor to
program each line in the 8-bit Peripheral I/O port to be
either an input or an output. Each bit in DDRA controls
the corresponding line in the Peripheral A port and each
.bit in DDRB controls the corresponding line in the
Peripheral B port. Placing a "0" in a bit position in the
Data Direction Register cause the corresponding Peripheral
I/O line to a-----_
--+!----I1:
1
INPUT _.
I
-=
I
L __________________________ _
______ . .: ___________________ ...i
OUTPUT MODE
INPUT MODE
NO PULL-UP IN CHIP
Figure 7. Port B Buffer Circuit (PB o -PB 7 )
7-49
TO CHIP
{lJUMC
UM652 0 / UM6520A
Interrupt Input/Peripheral Control Lines (CA1, CA2,
CB1,CB2)
In the Output mode (CRA, bit 5 = 1), CA2 can operate
independently to generate a simple pulse each time the
microprocessor reads the data on the Peripheral A I/O
port. This mode is selected by setting CRA, bit 4 to a
"0" and CRA, bit 3 to a "1". This pulse output can be
used to' control the counters, shift registers, etc. whi,ch
make sequential data available on the Peripheral input
lines.
The four interrupt input/peripheral control lines provide
a number of special peripheral control functions. These
lines greatly enhance the power of the two general purpose
interface ports (PAO-PA7, PBO-PBl). Figure 8 summarizes
the operation of these control lines.
Peripheral A Interrupt Input/Peripheral' Control Lines
(CA1, CA2)
CAl isan interrupt input only. An active transition of the
signal on this input will set bit 7 of the Control Register
A toa logic 1. The active transition can be programmed by
setting a "0" in bit 1 of the CRA if the interrupt flag
(bit 7 of CRA) is to be set on a negative transition of the
CA 1 signal or a "1" if it is to be set on a positive transition.
Note:
A negative transition is defined as a transition from
a high to a low, and a positive transition is defined as a
transition from a low to a high voltage.
Setting the interrupt flag will interrupt the processor
through IRQA if bit 0 of CRA is a 1 as described
previously.
CA2 can act as a totally independent interrupt input or as
a peripheral control output. As an input (CRA, bit 5 = 0) it
acts to set the interrupt flag, bit 6 of CRA, to a logic 1 on
the active transition selected by bit 4 of CRA.
These control register bits and interrupt inputs serve the
same basic function as that described above for CA 1.
The input signal sets the interrupt flag which serves as
the link between the peripheral device and the processor
interrupt structure. The interrupt disable bit allows the
processor to exercise control over the system interrupts.
A second output mode allows CA2 to be used in conjunction with CA 1 to "handshake" between the processor and
the peripheral device. On the A side, this technique allows
positive control of data transfers from the peripheral device
into the microprocessor. The CA 1, input signals the
processor that data is available by interrupting the
processor. The processor reads the data and sets CA2 low.
This signals the peripheral device that it can make new data
available.
The final output mode can be selected by setting bit 4 of
eRA to a 1. In this mode, CA2 is a simple peripheral
control output which can be set high or low by setting bit
3 of CRA to a 1 or a a respectively.
Peripheral B Interrupt Input/Peripheral Control Lines
(CB1, CB2)
CBl operates as an interrupt input only in the same manner
as CA 1. Bit 7 of CRB is set by the active transition selected
by bit a of CRB. Likewise, the CB2 input mode operates
exactly the same as the CA2 input modes. The CB2 output
modes, CRB bit 5 = 1, differ somewhat from those·of CA2.
The pulse output occurs when the processor writes data
into the Peripheral B Output Register. Also, the "handshaking" operates on data transfers from the processor
into the peripheral device.
CA1/CB1 CONTROL
CRA (CRB)
Active Transition
IRQA (JRQB) Interrupt Outputs
of Input Signal*
Bit 1
Bit 0
a
a
Negative
Disable - remain high
a
1
Negative
Enable - goes low when bit 7 in CRA (CRB) is set by active
transition of signal on CA 1 (CB1)
1
0
Positive
Disable - remain high
1
1
Positive
Enable - as explained' above
*.Note:. Bit 7 of CRA (CRB) will be set to a logic 1 by an active transition of the. CA 1 (CB1) signal. This is independent of
the state of Bit in CRA (CRB).
a
7-50
UM6520/ UM6520A
CA2/CB2 INPUT MODES
CRA (CRB)
BitS
Bit 4
Bit 3
Active Transition
of Input Signal*
0
0
0
Negative
Disable - remains high
0
0
1
Negative
Enable - goes low when bit 6 in CRA (CRB) is set by active
transition of signal on CA2 (CB2)
0
1
0
Positive
Disable - remains high
0
1
1
Positive
Enable - as explained above
·IRQA (lRQB) Interrupt Outputs
*Note: Bit 6 of CRA (CRB) will be set to a logic 1 by an active transition of the CA2 (CB2) signal. This is independent of
the state of Bit 3 in CRA (CRB).
CA2 OUTPUT MODES
CRA
Mode
Descriptions
0
"Handshake"
on Read
CA2 is set high on an active transition of the CA 1 interrupt
input signal and set low by a microprbce~sor "Read A Data"
operation. This allows positive control of data transfers from
the peripheral device to the microprocessor.
0
1
Pulse Output
CA2 goes low for one cycle after a "Read A Data" operation.
Th is pulse can be used to signal the peripheral device that data
was taken.
1
1
0
Manual Output
CA2 set low
1
1
1
Manual Output
CA2 set high
BitS
Bit4
Bit 3
1
0
1
CB2 OUTPUT MODES
CRB
Mode
Descriptions
0
"Handshake"
on Write
CB2 is set low on microprocessor "Write B Data" operation
and is set high by an active transition of the CB1 interrupt
input signal. This allows positive control of data transfers
from the microprocessor to the peripheral device.
0
1
Pulse Output
CB2 goes low for one cycle after a microprocessor "Write B
Data" operation. This can be used to signal the peripheral
device that data is available.
1
1
0
Manual Output
CB2 set low
1
1
1
Manual Output
CB2 set high
Bit 5
Bit4
Bit 3
1
a
1
Figure 8. Summary of Operation of Control Lines
7-51
2
CS)
TAO
TxD
RES
DB7
RxC
DB6
XTALl
DBs
¢2
XTAL2
DB4
R/W
RTS
DB3
CSI
RSo
RxC
XTALl
CTS
DB2
§
XTAL2
TxD
DB)
'iFi'Q
DCD
DSR
~o
RES
DTR
DBo
RxD
DSR
RSo
DCD
RS)
VCC
RxD
DBo
DB7
DTR
RTS
7-87
UM6551 / UM6551A
Absolute Maximum Ratings*
*Comments
Supply Voltage vee .............. -0.3V to" +7.0V
I nput/Output Voltage V IN . . . . . . . . . . -0.3V to +7 .OV
Operating Temperature Top . . . . . . . . . . . . OOC to 70°C
Storage Temperature T STG . . . . . . . . . . -55°C to 150°C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only.
Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied and exposure to absolute maximum rating
cond itions for extended periods may affect device
reliability.
Note:
All inputs contain protection circuitry to prevent damage
to high static charges. Care should be exercised to prevent
unnecessary application of voltages in excess of the ai'
lowable limits.
D.C. Characteristics
0
(Vee = 5.0V ± 5%, T~ = 0-70 C,
unless otherwise noted)
Characteristics
Symbol
Min.
Typ.
Max.
Units
V IH
2.0
-
Vec
V
Vil
-0.3
-
0.8
V
liN
-
± 1.0
±2.5
JJ.A
I nput Leakage Current for High I rnpedance State (Three State)
ITSI
-
±2.0
± 10.0
JJ.A
Output High Voltage: I lOAD == -1 OOJJ.A
(OB o -OB 7 , TxO, RxC, RTS, OTR)
V OH
2.4
-
-
V
Output Low Voltage: I LOAD == 1.6 rnA
(OB o -OB 7 , TxO, RxC, RTS, OTR, IRQ)
Val
-
-
0.4
V
Output High Current (Sourcing): VO H = 2.4 V
(OB o -OB 7 , TxO, RxC, RTS, OTR)
IOH
-100
-
-
JJ.A
Output Low Current (Sinking): VOL == O.4V
(OB o -OB 7 , TxO, RxC, RTS, OTR, TAO)
IOl
1.6
-
-
mA
Output Leakage Current (Off State): VOUT == 5V (IRQ)
IOFF
-
1.0
10.0
JJ.A
Clock Capacitance ( ¢ 2)
CClK
-
-
20
pF
CIN
-
-
10
pF
COUT
-
-
10
pF
PD
-
170
300
rnW
Input High Voltage
Input Low Voltage
Input Leakage Current: VIN == 0 to 5V
(¢2, RiW, RES, CSo, CS!, RS o , RS!, CTS, R x 0,
oco,
OSR)
I nput Capacitance (Except XT ALl and XTAL2)
Output Capacitance
Power Dissipation (See Graph) (T A == OoC) VCC = 5.25V
.
200
175
TYPICAL
POWER
~
150
~
DISSIPATION
(mW)
--
I"--
\,
125
100
o
20
40
60
Figure 1. Power Dissipation vs. Temperature
7-88
80
UM6551 / UM6551A
tCYC
tc
Jr-----VIH
VIL
,,",,~""""l'\. 1r----+-----------+--""'II or
"handshaking" signals. In mode 1, port A and port B
use the lines on port C to generate or accept these
"handshaking" signals.
MODE 1 (PORT A)
CONTROL WORD
D7 D6 D5 D4 D3 D2 01 DO
I' 1 1, I, 11I[?M
0
Mode 1 Basic Functional Definitions
•
•
•
•
PC6.7
1 = INPUT
0= OUTPU
Two Groups (Group A and Group B)
Each group contains one 8-bit port and one
4-bit control/data port.
The 8-bit data port can be either input or output.
Both inputs and outputs are latched.
The 4-bit port is used for control and status of
the 8-bit port.
Input Control Signal Definition
STB (Strobe Input)
A "low" on this input loads data into the input latch.
MODE 1 (PORT B)
IBF (Input Buffer Full F/F)
A "high" on this output indicates that the data has been
loaded into the input latch; in essence, an acknowledgement. I BF is set by STB in put being low and is reset by
the rising edge of the RD input.
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 DO
11 [XfX1)(W 111
INTR (Interrupt Request)
A "high" on this output can be used to interrupt the
CPU when an input device is requesting service. I NTR
is set by the condition; STB is a "one", IBF is a "one"
and INTE is a "one". It is reset by the falling edge of
RD. This procedure allows an input device to request
service from the CPU by simply strobing its data into
the port.
INTE A
Controlled by bit set/reset of PC 4 •
M
Figure 6. MODE 1 Input
INTE B
Controlled by bit set/reset of PC 2 '
-----tST~ v--~--~-----------------------------c~------------
------------~,I
~
STB
tSIB
IBF
~
J
1----,I~A0_----+--....(':_------------'"
J
tSIT
INTR
r-----
D-------_, I
________________-+--JJVA.
tRIT
I~
_'\
'J"
INPUT FROM
,
PERIPHERAL - - - - - "'\.
~---------------------+---~I
~----tps
•
Figure 7. MODE 1 (Strobed Input)
7-120
{J---_--.J7
/
UM82C55A
Output Control Signal Definition
MODE 1 (PORT A)
OBF (Output Buffer Full F/F). The OBF output will
go "low" to indicate that the CPU has written data out
to the specified port. The OBF F/F will be set by the
rising edge of the WR input and reset by ACK Input being
PA7·PAO
low.
ACK
(Acknowledge Input).
A
"low"
on
this
input
informs the UM82C55A that the data from port A or port
B has been accepted. I n essence, a response from the
peripheral device indicating that it has received the data
output by the CPU.
MODE 1 (PORT B)
INTR (Interrupt Request). A "high" on this output can
be used to interrupt the CPU when an output device
has accepted data transmitted by the CPU. INTR is set
when ACK is a "one", OBF is a "one" and INTE is a
"one". It is reset by the falling edge of WR.
PB7·PBO
CONTROL WORD
D7 D6D5 D4. D3 D2 D1 DO
11
1>®X1X1 1 IXI
1 0
INTE A
Controlled by Bi t Set/R eset of PC6 •
INTE B
Figure 8. MODE 1 Output
Controlled by Bit Set/Reset of PC 2 '
WR
OBF
INTR
ACK
OUTPUT
Figure 9. MODE 1 (Strobed Output)
7-121
8
(l)UMC
UM82C55A
Combinations of MODE 1; Port A and Port B can be individually defined as input or output in Mode 1 to support a wide
variety of strobed I/O applications:
PA7-PAO
PA7-PAO
PC4
RD
CONTROL WORD
WR
STI;3A
PC5
CONTROL WORD
tBFA
07 06050403 0201 DO
PC3
INTRA
2
PC6,7 _ I / O
1 = INPUT
0= OUTPUT
WR
PB7-PBO
1,1 I, Ht I, tx1
0
PC4,5
1 = INPUT
0= OUTPUT
RD
8
PCl
OBF
PC2
ACK
PCO
INTRB
B
B
PORT A - (STROBED INPUT)
PORT B - (STROBED OUTPUT)
8
PC7
OBF
PC6
ACK
PC3
INTRA
A
A
PC4-5
PB7-PBO
PC2
STB
PCl
IBFB
PCO
INTRB
B
PORT B - (STROBED INPUT)
PORT A - (STROBED OUTPUT)
Figure 10. Combinations of MODE 1
Operating Modes
MODE 2 (Strobed Bidirectional Bus 1/0)
The functional configuration provides a means for
communicating with a peripheral device or structure on a
single 8-bit bus for both transmitting and receiving data
(bidirectional bus I/O). "Handshaking" signals are provided
to maintain proper bus flow discipline similar to MODE 1.
Interrupt generation and enable/disable functions are also
available.
MODE 2 Basic Function Definitions:
•
•
•
•
Used in Group A only.
One 8-bit, bi-directional bus Port (Port A) and a
5-bit control Port (Port C).
Both inputs and outputs are latched.
The 5-bit control port (Port C) is used for control
and status for the 8-bit, bi-directional bus port
(Port A).
Bidirectional Bus I/O Control Signal Definition
INTR (Interrupt Request). A high on this output can be
used to interrupt the CPU for both input or output
operations.
Output Operations
OBF (Output Buffer Full). The OBF output will go "low"
to indicate that the CPU has written data out to port A.
ACK (Acknowledge). A "Low" on this input enables the
tri-state output buffer of port A to send out the data.
Otherwise, the output buffer will be in the high impedance
state.
INTE 1 (The INTE Flip-Flop Associated with OBF).
Controlled by bit set/reset of PC 6 •
Input Operations
STB (Strobe Input). A "low" on this input loads data into
the input latch.
IBF (Input Buffer Full F/F). A "high" on this output
indicates that data has been loaded into the input latch.
INTE 2 (The INTE Flip-Flop Associated with IBF).
Controlled by bit set/reset of PC4 '
7-122
UM82C55A
CONTROL WORD
D7 D6 D5
D4 D3 D2 D1
DO
PC2-0C
1 = INPUT
0= OUTPUT
PC4 - S T B
PORT B
1 = INPUT
0= OUTPUT
~~--------~
PC5
3
PC2-0
GROUP B MODE
0= MODE 0
1 = MODE 1
I/O
Figure 12. MODE 2
Figure 11. MODE Control Word
DATA FROM
CPU TO UM82C55A
INTR
STB
IBF
PERIPHERAL
BUS
- - - - - - - - - - - - - -
DATA FROM
PERIPHERAL TO UM82C55A
DATA FROM
.
UM82C55A TO PERIPHERAL
Figure 13. MODE 2 (Bidirectional)
Note: Any sequence where WR occurs before ACK and STB occurs before RD is permissible.
STB· RD+OBF· MASK· ACK· WR)
7-123
(INTR = IBF . MASK·
A
SUMC
UM82C55A
MODE 2 AND MODE 0 (INPUT)
MODE 2 AND MODE 0 (OUTPUT)
PC3
INTRA
CONTROL WORD
CONTROL WORD
OBF
D7 D6 D5 D4 D3 D2 D1 DO
11
11
~ 0 11
A
ACK
11/01
STB
tol
D7 D6 D5 D4 D3 D2 D1 DO
I, I, t>~Rl>(j
1 11
t>-.
/---'?-c
~
..<-----~
..<~----....
~
~
..<----'~
~
---'>-.
::;----,;:
"V
-
Figure 20.
7-126
Keyboard and Terminal Address Interface
(DUMC
UM82C55A
INTERRUPT
REQUEST
-
MODE,O
(OUTPUT) -
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7
PC4
PC5
pe6
PC7
UM82C55A~
BIT
"I
LSB
~
PC3
l2-BIT
D-A
CONVERTER
(DAC)
-
MODE 0
(OUTPUT) -
ANALOG
OUTPUT
MSB
PCO
PCl
STB DATA
OUTPUT EN
PC2
PC3
SAMPLE EN
-STB
UM82C55A
-
_
~ET/RESET
PAl
PA2
PA3
PA4
PA5
PA6
PA7
RO
Rl
CRT CONTROLLER
R2
• CHARACTER GEN
R3
• REFRESH BUFFER
R4
• CURSOR CONTROL
R5
SHIFT
CONTROL
PC7
PC6
PC5
PC4
DATA READY
ACK
BLANKED
BLACK/WHITE
PC2
PCl
PCO
ROWSTB
COLUMN STB
CURSOR H/V STB
'---
.---
MODE 0
(lNPUT)-
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
1-
PBO
PBl
MODE 0_
PB2
(OUTPUT)
PB3
PB4
PB5
PB6
PB7
'"==-
LSB
8-BIT
A-D
CONVERTER
(ADC)
-
ANALOG
INPUT
MSB
Figure 21. Digital to Analog, Analog to Digital
INTERRUPT
REQUEST
I
PC3
MODE2 -
INTERRUPT
REQUES~.
.--
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7
DO
Dl
D2
D2
D4
D5
D6
D7
PC4
PC5
PC7
PC6
DATA STB
ACK (IN)
DATA READY
ACK (OUT)
PC2
PCl
PCO
r--
MODEO
(OUTPUT) -
-
Figure 22. Basic CRT Controller Interface
PC3 ~O
PAl
PA2
PA3
PA4
PA5
MODEl
(INPUT) PA6
PA7
FLOPPY DISK
CONTROLLER
AND DRIVE
PC4
PC5
PC6
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
RO
Rl
R2
R3
R4
R5
R6
R7
8 LEVEL
PAPER
TAPE
READER
STB
ACK
STOP/GO
'----
MACHINE TOOL..
UM82C55A
'----
UM82C55A
CURSOR/ROW/COLUMN
-ADDRESS
H&V
TRACK "0" SENSOR
SYNC READY
INDEX
MODE 0
(INPUT)
-or
PCl
PC2
~O
ENGAGE HEAD
FORWARD/REV
READ ENABLE
WRITE ENABLE
DISC SELECT
ENABLE CRC
TEST
BUSY LT
MODE 0
(OUTPUT)-
PBl
PB2
PB3
PB4
PB5
PB6
PB7
START/STOP
LIMIT SENSOR (H/V)
OUT OF FLUID
CHANGE TOOL
LEFT/RIGHT
UP/DOWN
HOR. STEP STROBE
VERT. STEP STROBE
SLEW/STEP
FLUID ENABLE
EMERGENCY STOP
'----
'------
Figure 23. Basic Floppy Disk Interface
Figure 24. Machine Tool Controller Interface
7-127
SUMO
::::====:::CMOS
UM82C84A
Clock Generator Driver
Features
•
•
•
•
Generates the system clock for CMOS or NMOS
Microprocessors
Up to 25 MHz operation
Uses a parallel mode crystal circuit or external frequency
source
Provides ready synchronization
•
•
•
•
•
•
Generates system reset output from schm itt trigger
input
Capable of clock synchronization with other 8284A s
TTL compatible inputs/outputs
Very low p8wer consumption
18 Pi n package
Single +5V power supply
General Description
The UM82C84A is a high performance CMOS clock
generator-.driver which is designed to service the requirements of both CMOS and NMOS microprocessors such as
the 80C86, 80C88, 8086 and the 8088. The chip contains
a crystal controlled oscillator, a divide-by-three counter
and complete "Ready" synchronization and reset logic.
All inputs (except Xl, X2 and RES) are TTL compatible
with a VIH of 2.0 volts over the industrial temperature
and voltage ranges.
Static CMOS circuit design permits operation with an
external frequency source from DC to 25MHz. Crystal
controlled operation to 25MHz is guaranteed with the
Power consumption is a fraction of that of the equivalent
bipolar circuits. This speed-power characteristic of CMOS
permits the designer to custom tailor his system design
with respect to power and/or speed requirements.
Pin Configuration
use of a parallel, fundamental mode crystal and two small
load capacitors.
Block Diagram
CSYNC
VCC
PClK
X1
AEN1
X2
RDY1
ASYNC
READY
EFI
RDY2
Fie
AEN2
OSC
ClK
RES
GND
RESET
osc
ROY1
Control
Pin
logical 1
logical 0
FIC
External
Clock
Crystal
Drive
RES
Normal
Reset
ROY1
ROY2
Bus Ready
Bus not
Ready
AEfIT
Address
Disabled
Address
Enabled
2 Stage Ready
Synchronization
1 Stage Ready
Synchronization
AEN2
ASYNC
ASYNC~--------------------
7-128
(l)UMC
UM82C84A
Absolute Maximum Ratings*
*Comments
Supply Voltage . . . . . . . . . . . . . . . . . . . . . +8.0 Volts
Operating Voltage Range . . . . . . . . . . . . . . +4V to +7V
Applied Voltage on Any Pin
VIN . . . . . . . . . . . . . . . . . . GND -0.3V to VeeO.3V
Ambient Temperature Under Bias T A ..... O°C to + 70°C
Storage Temperature Range
TSTG . . . . . . . . . . . . . . . . . . . . . . -65°Cto+150°C
Maximum Power Dissipation . . . . . . . . . . . . . . . . 1 Watt
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of
this device at these or any other cond itions above those indicated in the operational sections of this specification is
not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. Electrical Characteristics
Vee = 5.OV
± 10%
Symbol
TA = O°C to +70°C
Parameter
Min.
VIH
logical One
Input Voltage
VIL
logical Zero
Input Voltage
VT+
Reset Input
High Voltage
0.7 Vee
Reset Input
Hysteresis
0.2 Vee
VOH
Logical One
Output Voltage
Vce- O.4
VOL
logical Zero
Output Voltage
ICL
Input leakage
Current
Icc'
Power S
Supply Current
VT+-VT-
Max.
Test Conditions
V
2.0
0.8
-1,0
Units
V
V
V
10H = -4.0mA for
ClK oU'cput
10H = -2.5mA for
all others
0.4
V
10 L = +4.0mA for
ClK output
10L = +2.5mA for
for others
1.0
p.A
OV--+-----+--1 D
two
o
D
Q
EFI
Figure 10. CSYNC Synchronization
*Note:
(TO OTHER 82C84As)
If EFI input is used, then crystal input Xl must be tied to Vcc or GND and X2 should be left open. If the crystal
inputs are used, then EF I should be tied to Vcc or GND.
7-134
SUMO
UM82C88
===~i~~=========== Bus Controller
Features
•
Pin compatible with bipolar 8288
•
High performance HCMOS process
•
Provides advanced commands for multimaster busses
•
Single 5V power supply
•
3-state command outputs
•
Low power operation
•
Bipolar drive capabil ity
ICCSB - 10llA
•
Fully TTL compatible
IccOp - 1mA/MHz
General Description
The UM82C88 is a high performance CMOS Bus Controller
need for additional bus drivers.
manufactured
standard configuration make the UM82C88 compatible
using
a self-aligned silicon gate CMOS
High speed and industry
process. The UM82C88 provides the control and command
with microprocessors such as the 80C86, 8086, 8088,
timing signals for 80C86 and 8086/88 systems. The high
8089,80186, and 80188.
output drive capability of the UM82C88 eliminates the
Block Diagram
Pin Configuration
lOB
ClK
VCC
MRDC
So
STATUS
DECODER
51
DTiR
S2
MCE/PDEN
ALE
DEN
AEN
CEN
MRDC
INTA
AMWC
10RC
MWTC
AIOWC
GND
MWTC
COMMAND
AMWC
SIGNAL
IORC
GENERATOR'
IOWC
™
}
'MULTIBUS
COMMAND
SIGNALS
Ali5WC
INTA
CLK
CONTROL
AEN
INPUT { GEN
lOB
CONTROL
LOGIC
CONTROL
SIGNAL
GENERATOR
ALE
VCC
GND
10WC
*TM Multibus is an I NTE L Corp trademark
7-135
DT/R
}
DEN
MCE PDEN
ADDRESS LATCH
DATA TRANSCEIVER
AND INTERRUPT
CONTROL SIGNALS
(DUMC
UM82C88
Absolute Maximum Ratings*
*Comments
Supply Voltage . . . . . . . . . . . . . . . . . . . . . +8.0 Volts
Operating Voltage Range . . . . . . . . . . . . . . +4V to +7V
Input Voltage Applied .......... GND -2.0V to +6.5V
Output Voltage Applied ..... GND -0.5V to Vee +0.5V
Storage Temperature Range ......... -65°C to +150°C
Operating Temperature Range . . . . . . . . . . O°C to + 70°C
Maximum Power Disipation . . . . . . . . . . . . . . . . 1 Watt
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings oniy. Functional operation of
this device at these or any other conditions above those indicated in the operational sectio~s of this specification is
not implied and exposure to absolute maximum rating conditions for extended per.iods may affect device reliability .
.D.C. Electrical Characteristics
(Vee = 5.0V ±.1 0%; T A = O°c to + 70°C)
Symbol
Parameter
Min.
VJH
Logic One
Input Voltage
2.0
VIL
Logic Zero
Input Voltage
VIHe
LCK Logical One
Input Voltage
VILe
CLK Logical Zero
Input Voltage
VOH
Output High Voltage
Command Outputs
3.0
VCC-OA
V
V
10H = -S.OmA
10H = -2.5mA
Output High Voltage
Control Outputs
3.0
VCC-OA
V
V
10H = -4.0mA
10H = -2.5mA
VOL
Max.
Units
Conditions
V
V
O.S
V
V
0.7 Vee
0.2 VCC
V
Output Low Voltage
Command Outputs
0.5
V
10L = +20.0mA
Output Low Voltage
Control Outputs
OA
V
10L = +S.OmA
1.0
J..l.A
IlL
Input Leakage
Current
-1.0
IBHH
Input Leakage
Current-Status Bus
-50
OV~VIN~Vee
except So, Sl , S2
-300
J..l.A
VIN = 2.0V
So,Sl,S2
(see Note 1)
10
Output Leakage
Current
leesB
Standby Power Supply
leeop
Operating Power
Supply Current
-10.0
10.0
J..l.A
OV~Vo~Vee
10
J..l.A
Vee = 5.5V
VIN = Vee or GND
Outputs Open
1
mA/MHz
Vee = 5.5V
Outputs Open
Max.
Unit
Conditions
Capacitance
(TA = 25°C; Vee = GND = OV; VIN = +5Vor GND)
Symbol
Parameter
Min.
CIN*
Input Capacitance
5
pf
COUT*
Output Capacitance
16
pf
*Guaranteed and sampled, but not 100% tested
7-136
.FREQ = 1MHz
Unmeasured pins
returned to GND
UM82C88
A. C. Characteristics
(Vcc=+5V±10%, GND=OV; TA=0°Ct070°C)
TIMING REQUIREMENTS
Parameter
Symbol
TCLCL
TCLCH
TCHCL
TSVCH
TCHSV
TSHCL
TCLSH
Max..'
Min.
CLK Cycle Period
CLK Low Time
CLK High Time
Status Active Setup Ti me
Status Active Hold Time
Status Inactive Setup Time
Status Inactive Hold Time
Unit
Conditions
ns
ns
ns
ns
ns
125
66
40
35
10
35
10
ns
ns
TIMING RESPONSES
Symbol
Parameter
Min.
Max.
Unit
Conditions
TCVNV
TCVNX
TCLLH
TCLMCH
TSVLH
TSVMCH
TCHLL
TCLML
TCLMH
TCHDTL
TCHDTH
T AELCH
TAEHCZ
TAELCV
TAEVNV
TCEVNV
TCELRH
Control Active Delay
Control Inactive Delay
ALE Active Delay (from ClK)
MCE Active Delay (from ClK)
ALE Active Delay (from Status)
5
10
ns
1
MCE Active Delay (from Status)
ALE Inactive Delay
Command Active Delay
Command Inactive Delay
Direction Control Active Delay
Direction Control Inactive Delay
Command Enable Time l
Command Disable Time 2
Enable Delay Time
AEN to DEN
CEN to DEN, PDEN
CEN to Command
45
45
20
25
20
30
22
35
35
50
30
40
40
250
25
25
TCLML
+10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
2
2
1
1
3
4
2
1
1
2
TLHLL
ALE High Time
ns
1
Note:
4
5
5
110
TClCH
-10
1. TAELCH measurement is between 1.5Vand 2.5V.
2. T AEHCZ measured at 0.5V change in VO.
A.C. Test Circuits
Vl
Test
Conditions
Rl
OUTPUT FROM
DEVICE - - - - - - - < t - - - -
TEST
POINT
IOH
IOL
VI
Rl
C1
1
-4.0mA + S.OmA
2.13V 220n
2
-S.OmA +20.0mA
2.29V
3
-S.OmA
-
1.50V 1S7n '300pf
4
-S.OmA
-
1.50V 1S7n
SOpf
91n 300pf
UNDER TEST
*Includes stray and jig capacitance
Test Condition Definition Table
7-137
50pf
UM82C88
A.C. Testing Input, Output Waveform
INPUT
OUTPUT
VIH+O.4V--____
,-----VOH
1,5VX~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _X1.5V
VIL-O.4V
,
_
,
.
VOL
A.~. Testing: All input signals (other than elK) must switch between VI.l -OAV and VIH +OAV. elK must switch between
OAV and 3.9V. T Rand T F must be less than or equal to 15ns.
Waveforms
STATE _
T 4 _I - - - T 1 _ _ _ T
-TCLCL _
~
CLK
)~ 1----.)
TCHSV_
r--
..
\
TSVCH
_
r-;
_
TCLC~
T3
If-;yr:svu~r-\.
~
CHLL
T4'_
~
~ f---...J
I--'1
TCLSH£.
~
CLLH ..
ALE
TCHCL
IL----I
--
[)<'ADDR
, VALID
ADDRESS/DATA
_
2
. --!rSHCL
f
WRITE
DATA VALID
TCLMH_
MRDC 10RC INTA
AMWC,AIOWC
--- 1-
PDEN (READ)
(lNTA)
-
DEN (WRITE)
PDEN (WRITE)
DT/R(READ)
(lNTA)
TCLML _
-
DEN (READ)
(INTA)
. --_..
--.r;:
_F
,!-TcUlllL
}I£"
_TCVNV
'I\..
J
,
TCVNX-
-
'{
/--TCVNV
'f
1\'
T_C~~~~-:
I--
T
\
--
\
1\
f--TCVNX
j'
.J
iL
TCHDft
MCE
TCLMCH ....
L P
~
\
TCHDTH -
I-
--;cvFx
TSVMCH
Not~s:
1 Address/data bus is shown only for reference purposes
2 Leading edge of ale and mce is determined by thefalling edge of elK or status going active whichever occurs last
3 All timing me asurements are made at 15V unless specified otherwise
7-138
UM82C88
Waveforms (Continued)
DEN, PDEN QUALIFICATION TIMING
CEN
----------------------~--'
DEN
PDEN
ADDRESS ENABLE (AEN) TIMING (3-STATE ENABLE/DISABLE)
-TAELCV-
~ ,5V
TAELCH-
}1f15V
........-
OUTPUT
COMMAND
TAEHCZ-
VOH
1
~~
\~
/V
.
..
TCELRH
~V
CEN
-
'~
-TCELRH
Note:
CEN must be low or valid prior to T2 to prevent the command from being generated.
7-139
~
O.5V
i
I
V OH
UM82C88
Pin Description
Symbol
Pin
Number
Type
Vee
20
0
GND
10
$0 :51.$2
19,3,18
I
CLK
2
I
ALE
5
0
DEN
16
0
Data Enable: This signal serves to enable data transceivers onto either the local or
system data bus. This signal is active HIGH.
DT/R
4
0
Data Transmit/Receive:
This signal esta bl ishes the direction of data flow
through the transceivers. A HIGH on this line indicates Transmit (write to I/O or
memory) and a LOW indicates Transmit (write to I/O or memory) and a LOW
indicates Receive (Read).
AEN
6
I
Address Enable: AEN enables command outputs of the UM82C88 Bus Controller a
minimum of 110ns (250ns maximum) after it becomes active (LOW). AEN going
inactive immediately 3-states the command output drivers. Am does not affect
the I/O command lines if the UM82C88 is in the I/O Bus mode (lOB tied HIGH).
CEN
15
I
Command Enable;·-When this signal LOW all UM82C88 command outputs and the
DEN and PDEN control outputs are forced to their inactive state. When this signal
is HIGH, these same outputs are enabled.
lOB
1
I
Input/Output Bus Mode: When the lOB is strapped HIGH the UM82C88 functions
in the I/O Bus mode. When it is strapped LOW, the UM82C88 functions in the
System Bus mode (See I/O Bus and System Bus sections).
AIOWC
12
a
Advanced I/O Write Command: The AIOWC issues an I/O Write Command earlier
in the machine cycle to give I/O devices an early indication of a write instruction.
Its timing is the same as a read command signal. ATOWL is active LOW.
lowe
11
a
I/O Write Command: This command line instructs an I/O device to read the data
on the data bus. The signal is active LOW.
10RC
13
a
I/O Read Command: This command line instructs an I/O device to drive its data
onto the data bus. This signal is active LOW.
AMWC
8
a
Advanced Memory Write Command: The AMWC issues a memory write command
earlier in the machine cycle to give memory devices an early indication of a write
instruction. Its timing is the same as a read command signal. AMWC is active Law.
MWTC
9
a
Memory Write Command: This command line instructs the memory to record the
data present on the data bus. This signal is active Law.
MRDC
7
a
Memory Read Command: This command line instructs the memory to drive its
data onto the data bus. MRDC is active Law.
INTA
14
a
Interrupt Acknowledge: This command line tells an interrupting device that its
interrupt has been acknowledged and that it should drive vectoring information
onto the data bus. This signal is active Law.
MCE/PDEN
17
Functions
+5V power supply
Ground
a
Status input pins: These pins are the input pins from the 80C86, 8086/88/8089
processors. The UM82C88 decodes these inputs to generate command and control
signals at the appropriate time. When Status pins are not in use (passive), command
outputs are held HIGH (See Table 1.)
Clock: This is a CMOS oompatible input which receives a clock signal from the
UM82C84A clock generator and serves to establish when command/control signals
are generated.
Add ress Latch Enable: This signal serves to strobe an address into the address
latches. This signal is active HIGH and latching occurs on the falling (H IGH to
LOW) transition. A LE is intended for use with transparent D type latches, such as
the 82C82.
This is a dual function pin. MCE (lOB is tied LOW): Master Cascade Enable occurs
during an interrupt sequence and serves to read a Cascade Address from a master
UM82C59A Priority Interrupt Controller onto the data bus. The MCE signal is
active HIGH. PDEN (lOB is tied HIGH): Peripheral Data Enable enables the data
bus transceiver for the I/O bus that DE N performs for the system bus. PDEN is
active LOW.
7-140
UM82C88
Functional Description
Command and Control Logic
The command logic decodes the three 80C86, 8086, 8088 or 8089 status lines (So~ $1, Sl) to determine what command is to
be issued (see Table 1).
Table 1. Command Decode Definition
82
81
So
Processor State
0
0
0
a
a
0
1
1
0
a
a
0
1
1
0
Interrupt Acknowledge
Read I/O Port
Write I/O Port
Halt
Code Access
Read Memory
Write Memory
Passive
a
1
1
1
1
1
1
1
1
UM82C88
Comm.. d
Il\JTA
10RC
iOWC", ALOWC
None
lVfROC
MRDC
MWTC, AlIIfWC
None
1/0 BUS Mode
Control Outputs
The UM82C88 is in the I/O Bus mode if the lOB pin is
strapped HIGH. In the I/O Bus mode, all I/O command
lines (IORC, ILWC, AIOWC, INTA) are always enabled
(i.e., not dependent on AEN). When an I/O command is
initiated by the processor, the UM82C88 immediately
activates the command lines using PDEN and DT/A" to
control the I/O bus transceiver. The I/O command lines
should not be used to control the system bus in this
configuration because no arbitration is present. This mode
allows one UM82C88 Bus Controller to handle two external
busses. No waiting is involved when the CPU wants to gain
access to the I/O bus. Normal mermory access requires a
"Bus Ready" signal (AEN LOW) before it will proceed.
It is advantageous to use the lOB mode if I/O or peripherals
dedicated to one processor exist in a mUlti-processor
system.
The control outputs of the UM82C88 are Data Enable
(DEN), Data Transmit/Receive (DT/"Fi) and Master Cascade
Enable/Peripheral Data Enable (MCE/PDEN). The Den
signal determines when the external bus should be enabled
onto the local bus and the DT/R determines the direction
of data transfer. These two signals usually go to the chip
select and direction pins of a transceiver.
System BUS Mode
The UM82C88 is in the System Bus Mode if the lOB pin is
strapped LOW. In this mode, no command is issued until a
specified time period after the AEN line is activated (LOW).
This mode assumes bus arbitration logic will inform the bus
controller (on the AEN line) when the bus is free for use.
Both memory and I/O commands wait for bus arbitration.
This mode is used when only one bus exists. Here, both
I/O and memory are shared by more than one processor.
Command Outputs
The advanced writer commands are made available to
initiate write procedures early in the machine cycle. This
signal can be used to prevent the processor from entering an
unnecessary wait state.
The MCE/PDEN pin changes function with the two modes
of the UM82C88.When the UM82C88 is in
lOB mode
(lOB HIGH), the PDEN signal serves as a dedicated data
enable signal for the I/O or PeripheraJ System bus.
me
Interrupt Acknowledge and MCE
The MCE signal is used during an interrupt acknowledge
cycle if the UM82C88 is in the System Bus mode (lOB
LOW).
During any interrupt sequence, there are two
interrupt acknowledge cycles that occur back to back.
During the first interrupt cycle no data or address transfers
take place. Logic should be provided to mask off MCE
during this cycle. Just before the second cycle begins the
MCE signal gates a master Priority Interrupt Controller'S
(P IC) cascade address onto the processor's local bus where
ALE (Address Latch Enable) strobes it into the address
latches. On the leading edge of the second interrupt cycle,
the addressed slave PIC gates an interrupt vector onto the
system data bus where it is ready by the processor.
If the system contains only one PIC, the MCE signal is not
used. In this case, the second Interrupt Acknowledge signal
gates the interrupt vector onto the processor bus.
Address Latch Enable and Halt
Address Latch Enable (ALE) occurs during each machine
cycle and serves to strobe the current address int-o the
82C82 address latches. ALE also serves to strobe .the
status (So, St, S2) into a latch for halt state decoding.
The command outputs are:
MRDC - Memory Read Command
MWTC - Memory Write Command
10RC - I/O Read Command
10WC - I/O Write Command
AMWC - Advanced Memory Write Command
AIOWC- Advanced I/O Write Command
INTA - Interrupt Acknowledge
Command Enable
INTA (Interrupt Acknowledge) acts as an I/O read during
an interrupt cycle. Its purpose is to inform an interrupting
device that its interrupt is being acknowledged and that it
should place vectoring information onto the data bus.
The Command Enable (CEN) input acts as a command
qualifier for the UM82C88. If the CEN pin is high, the
UM82C88 functions normally. If the CEN pin is pulled
LOW, all command lines are held in their inactive state
(not 3-state).
This feature can be used. to implement
memory partitioning and to eliminate address confli<:ts
between system bus devices and resident·bus devices.
7-141
eUMC
UM8237A/ 8237A-4/ 8237A-5
Programmable DMA
Controller (DMAC)
Features
•
•
•
•
•
•
•
Enable/Disable control of individual DMA requests
Four independent DMA channels
Independent autoinitialization of all channels
Memory-to-memory transfers
Memory block initialization
Single 5V power supply
High performance: transfers up to 1.6M bytes/second
with 5MHz 8237A-5
• Directly expandable to any number of channels
• End of process input for terminating transfers
• Software DMA requests
• Independent Polarity control for DREQ and DACK
signals
• Available in EXPRESS
- Standard Temperature Range
General Description
The UM8237 A Direct Memory Access Controller (DMAC)
is a peripheral interface circuit for microprocessor systems.
It is designed to improve system performance by allowing
external devices to directly transfer information from the
system memory. Memory-tb-memory' transfer capability
is also provided. The LJ M8237 A offers a wide variety of
programmable control features to enhance data throughput
Pin Configuration
A7
lOW
MEMR
A6
A5
MEMW
A4
MARK
EOP
READY
A3
HlDA
ADSTB
A2
AEN
AO
HRO
VDP
DBO
DBl
ClK
UM8237 A is fabriqlted in Si-Gate NMCS process with each
channel has a fuil 64K address and word count capability.
The 8237A-4 and 8237A-5 are 4 MHz and 5 MHz selected
versions of the standard 3 MHz 8237A respectively.
Block Diagram
TOR
cs
and system optimization and to allow dynamic reconfiguration under program control.
Al
RESET
DACK2
DB2
DACK3
DB4
DRE03
DACKO
DRE02
DREOl
DACKl
DREOO
DB6
(GND) VSS
DB7
EOP
RESET
cs
READY
CLOCK
ADSTB
MEMR
MEMW
TOR
lOW
DB3
MLDA
DB5
7-142
(l)UMC
UM8253 / UM8253-5
Features
•
•
•
•
•
•
MCS-85™ compatible UM8253-5
3 independent 16-bit counters
DC to 2.6 MHz
Programmable counter modes
Count binary or BCD
Single +5V supply
General Description
The UM8253 is a programmable counter timer device
designed for use as an microcomputer peripheral. It uses
NMOS technology with a single +5V supply and is packaged
in a 24-pin plastic DIP.
It is organized as 3 independent 16-bit counters, each with
a count rate of up to 2.6 MHz. All modes of operation
are software programmable.
*MCS-85™ is the trademark of Intel microsystem.
Block Diagram
Pin Configuration
.0 7-00
07
VCC
06
WR
Os
RO
04
CS
03
Al
O2
Ao
0,
ClK 2
00
ClK 0
OUT 0
GATE 0
GNO
OUT.2
Ao
AI
Cs
GATE 2
ClK 1
GATE 1
OUT 1
7-143
READ/
WRITE
LOGIC
UM8253/ UM8253-5
Absolut-e Maximum Ratings*
*Comments
Ambient Temperature Under Bias TA ...... O°C to 70°C
Stress above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These ·are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied and exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Tempel'ature TSTG ..........-65°C to +l50°C
Voltage on Any Pin with Respect to
Ground ., . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Power Dissipation. . . . . . . . . .. 1 Watt
D. C. Characteristics
(TA = O°C to 70°C, Vee
Symbol
= 5V!. 10%)
Min
Max.
Units
Vll
Input Low Voltage
Parameter
-0.5
0.8
V
VIH
Input High Voltage
2.2
Vee+o.5v
V
Val
Output low Voltage
0.45
V
Note 1
VOH
Output High Voltage
V
Note 2
2.4
III
Input Load Current
±.10
lOFl
Output Float Leakage
Icc
Vee Supply Current
Conditions
/J A
VIN
±.10
/JA
VOUT
140
mA
=
Vee to OV
=
Vee to 0.45V
Capacitance
(TA = 25°C, Vee = GND = OV)
Symbol
Parameter
Typ.
Conditions
Max.
Units
CIN
I nput Capacitance
10
pF
fc=lMHz
CliO
I/O Capacitance
20
pF
Unmeasured pins
returned to Vss
Min.
A.C. Characteristics
(TA = O°C to 70°C, Vee = 5.0V ± 10%, GND = OV)
Bus Parameters (Note 3)
READ CYCLE
Symbol
Parameter
UM8253
Min.
UM8253-5
Max. ,
Min.
Units
Max.
tAR
Address Stable Before READ
50
30
ns
tRA
Address Hold Time for READ
5
5
ns
tRR
READ Pulse Width
400
300
ns
tRO
Data Delay From READ(4)
tOF
READ to Data Floating
tRv
Recovery Time Between READ
and Any Other Control Singnal
300
25
1
7-144
125
25
1
200
ns
100
ns
/Js
UM8253/UM8253-5
A.C. Characteristics (Continued)
WRITE CYCLE
Symbol
UM8253
Parameter
UM8253-6
Max.
Min.
Max .
.Min.
Units
tAW
Address Stable Before WRITE
50
30
ns
tWA
Address Hold Time for WRITE
30
30
ns
tww
WR ITE Pulse Width
400
300
ns
tDW
Data Set Up Time for WR ITE
300
250
ns
tWD
Data Hold Time for WR ITE
40
30
ns
tRV
Recovery time Between WRITE
and Any Other Control Signal
1
1
/-lS
Clock and Gate Timing
Symbol
UM8253
Parameter
UM8253·5
Min.
Max.
dc
Min.
Max.
380
dc
Unit
tCLK
Clock Period
380
tPWH
High Pulse Width
230
230
ns
tpWL
Low Pu Ise Width
150
150
ns
ns
tGW
Gate Width High
150
150
ns
tGL
Gate Width Low
100
100
ns
tGS
Gate Set Up Time to CLKt
100
100
ns
tGH
Gate Hold Time After CLKt
50
50
ns
tOD
Output Delay From CLK-l-[4)
400
400
ns
tODG
Output Delay From Gate-l- [4)
300
300
ns
Notes:
1. IOL = 2.2 mA.
2. IOH = -400 JlA.
3. AC timings measured at VOH 2.2, VOL = 0.8.
4. CL = 150pF.
A.C. Testing Input, Output Waveform
2.4
>
2.2V
A.C. Testing Load Circuit
2.2V
DEVICE
UNDER
TEST
TEST POINTS<
0.45
0.8
0.8
nCL=150PF
1=-
A.C. TESTING: INPUTS ARE DRIVENIAT 2.4V FOR A LOGIC "1"
AND 0.45V FOR A LOGIC "0" TIMING MEASUREMENTS .ARE
MADE AT 2.2V FOR A LGOIC "1" AND 0.8t1! FOR A LOGIC 0
CL INCLUDES JIG CAPACITANCE
7-145
UM8253/ UM8253-5
Waveforms
WRITE TIMING
AO_i,CS
tWA
t AW DATA BUS
_
READ TIMING
CLOCK AND GATE TIMING
ClK
GATE G
OUTPUT 0
______
~
________-+__
_J
tOOG
7-146
tow ___ two
UMS253 / UMS253-5
Functional Description
WR (Write)
General
A "low" on this input informs the UM8253 that the CPU
is outputting data in the form of mode information or
loading counters.
The UM8253 is a programmable interval timer/counter
specifically designed for use with microcomputer systems.
Its function is that of a general purpose, multiming element
that can be treated as an array of I/O ports in the system
software.
The UM8253 solves one of the most common problems
in any microcomputer system the generation of accurate
time delays under software control. Instead of setting up
timing loops in systems software, the programmer
configures the UM8253 to match his requirements, initializes
one of the counters of the UM8253 with the desired
quantity, then upon command the UM8253 will count out
the delay and interrupt the UPU when it has completed its
tasks. It is easy to see that the software overhead is
minimal and that multiple delays can easily be maintained
by assignment of priority levels.
Ao ,Al
These inputs are normally connected to the address bus.
Their function is to select one of the three counters to be
operated on and to address the control word register for
mode selection.
Other counterltimer functions that are non-delay in nature
but also common to most microcomputers can be
implemented with the UM8253.
•
•
•
•
•
•
Programmable Rate Generator
Event Counter
Binary Rate Multiplier
Real Time Clock
Digital One-Shot
Complex Motor Controller
Data Bus Buffer
This 3-state, bi-directional, 8-bit buffer is used to interface
the UM8253 to the system data bus. Data is transmitted
or received by the buffer upon execution of input or OUT
put CPU instructions. The Data Bus Buffer has three basic
functions.
1. Programming the MODES of the UM8253.
2. Loading the count registers.
3. Reading the count values.
Figure 1..Block Diagram Showing Data Bus Buffer and
Read/Write Logic Functions
CS
RD
WR
Al
Ao
0
1
0
0
0
Load Cou nter No. 0
0
1
0
0
1
Load Counter NO.1
Read/Write Logic
0
1
0
1
0
Load Counter No.2
The Read/Write Logic accepts inputs from the system bus
and in turn generates control signals for overall device
operation. It is enable or disabled by CS so that no
operation can occur to change the function unless the
device has been selected by the system logic.
0
1
0
1
1
Write Mode Word
RD (Read)
A "low" on this input informs the UM8253 that the
CPU is inputting data in the form of a counters value.
7-147
0
0
1
0
0
Read Counter No. 0
0
0
1
0
1
Read Counter No.1
0
0
1
1
0
Read Counter Nb. 2
0
0
1
1
1
No-Operation 3-State
1
X
X
X
X
Disable 3-State
0
1
1
X
X
No-Operation 3-State
UM8253 / UM8253-5
CS (Chip Select)
Operational Description
A "low" on this input enables the UM8253. No reading
or writing will occur unless the device is selected. The
CS input has no effect upon the actual operation of the
counters.
General
Control Word Register
The complete functionaf definit on of the UM8253 is
programmed by the systems software. A set of control
words must be sent out by the CPU to initialize each
counter of the UM8253 with the desired MODE and
"The Control Word Register is selected when Ao, At are
11. It then accepts information from the data bus buffer
and stores it in a register. The information stored in this
register controls the operational MOOE of each counter,
selection of binary or BCD counting and the loading of
each count register.
The Control Word Register can only be written into; no
read operation of its contents is available.
Counter
#0, Counter #1, Counter #2
These three functional blocks are identical in operation
so only a single Counter will be described. Each Counter
consists of a single, 16-bit, pre-settable, DOWN counter.
The counter can operate in either binary or BCD and its
input, gate and output are configured by the selection of
MODES stored in the Control Word Register.
The counters are fully independent and each can have
separate Mode configuration and counting operation,
binary or BCD. Also, there are special features in the
control word that handle the loading of the count value
so that software overhead can be minimized for these
functions.
The reading of the contents of each counter is available to
the programmer with simple READ operations for event
counting applications and special commands and logic are
included in the UM8253 so that the contents of each
counter can be read "on the fly" without having to inhibit
the clock input.
Figure 2. Block Diagram Showing Control Word
Register and Counter Functions
UM8253 System Interface
The UM8253 is a component of the UMC Microcomputer
Systems and interfaces in the same manner as all other
peripherals of the family. It is treated by the systems
software as an array of peripheral I/O ports; three are
counters and the fourth is a control register for MODE
programming.
·Basically, the select inputs Ao ,Ai connect to the Ao. Ai
address bus signals of the CPU. The CS can be derived
directly from "the address bus using a linear select method.
Or it can be connected to the output of a decoder. such as
an 8205 for larger systems.
7-148
UM8253
COUNTER
o
COUNTER
1
Figure 3. UM8253 System Interface
(t)UMC
UM8253/ UM8253-5
quantity information, prior to initialization, the MODE,
count, and output of all counters is undefined. These
control words program the MODE, Loading sequence
and selection of binary or BCD counting.
BCD:
a
Binary Counter 16-bits
1
Binary Coded Decimal (BCD) Counter
(4 Decades)
Once programmed, the UM8253 is ready to perform
whatever t i mi ng tasks it is assigned to accompl ish.
The actual counting operation of each counter is
completely independent and additional logic is provided
on-~hip so that the usual problems associated with efficient
monitoring and management of external, asynchronous
events or rates to the microcomputer system have been
eliminated.
Programming the UM8253
Each counter of the UM8253 is individually programmed
by writing a control word into the Control Word Register.
(At, Al = 11)
Control Word Format
SCO
RL1
RLO
The count register is not loaded until the count value is
written '(one or two bytes, depending on the mode selected
by the RL bits), followed by a rising edge and a falling
edge of the clock. Any read of the counter prior to that
falling clock edge may yield invalid data.
.
MODE Definition
All of the MODES for each counter are programmed by
the systems software by simple I/O operations.
SC1
Counter Loading
M2
M1
Ma
BCD
MODE 0: Interrupt on Terminal Count. The output will
be initially low after the mode set operation. After the
count is loaded into the selected count register, the output
will remain low and the counter will count. When terminal
count is reached the output will go high and remain high
until the selected.~ount register is reload'ed with themode
or a new count 'is loaded. The counter continues to
decrement after terminal count has been reached.
Rewriting a counter register during counting results in the
following:
(1) Write 1st byte stops the current counting.
(2) Write 2nd byte starts the new count.
Definition of Control
SC - Select Counter:
SC1
sco
MODE 1: Programmable One-Shot. The output will go
low on the count following the rising edge of the gate input.
a
a
Select Counter a
0
1
Select Counter 1
1
a
Select Counter 2
1
1
Illegal
The output will go high on the terminal count. If a
count value is loaded while the output is low it will
affect the duration of the one-shot pulse until
succeeding trigger. The current count can be read at
time without affecting the one-shot pulse.
new
not
the
any
R L - Read/Load:
RL1
RLO
a
a
Counter Latching operation (see
R EAD/WR ITE procedure Section)
1
a
Read/Load most significant byte only.
a
1
Read/Load least significant byte only.
1
1
Read/ Load least signi ficant byte first,
then most significa'nt byte.
M-MODE:
M2
M1
MO
0
0
a
0
0
1
Mode 1
X
1
a
Mode2
Modea
X
1
1
Mode 3
1
a
a
Mode4
1
a
1
Mode5
The one-shot is retriggerable, hence the output will remain
low for the fu II count after any rising edge of the gate
input.
MODE 2: Rate Generator. Divide by N counter. The
output will be low for one period of the input clock. The
period from one output pulse to the next equals the
number of input counts in the count register. If the count
register is reloaded between output pulses the present
period will not be affected, but the subsequent period
will reflect the new value.
The gate input, when low, will force the output high.
When the gate input goes high, the counter wHI start
from the initial count. Thus, the gate input can be used
to synchronize the counter.
When this mode is set, the output will remain high until
after the count register is loaded. The ou~put then can
also be synchronized by software.
7-149
UMB253 / UMB253-5
MODE 3: Square Wave Rate Generator. Similar to MODE
2 except that the output will remain high until one half
the count has been completed (for even numbers) and go
low for the other half of the count. This is accomp!ished
by decrementing the counter by two on the falling edge of
each clock pulse. When the counter reaches terminal
count, the state of the output is changed and the counter
is reloaded with the full count and the whole process is
repeated.
If the count is odd and the output is high, the first clock
pulse (after the count is loaded) decrements the count by 1 .
Subsequent clock pulses decrement the clock by 2. After
timeout, the output goes low and the tu II count is reloaded.
The first clock pulse (following the reload) decrements the
counter by 3.
Subsequent clock pulses decrement the
count by 2 until timeout. Then the whole process is
repeated. In this way, if the count is odd, the output will
be high for (N+1 )/2 counts and low for (N-1 )/2 counts.
~
In Modes 2 and 3, if a ClK source other than the system
clock is used, GATE should be pulsed immediately
following WR of a new count value.
MODE 4: Software Tr.iggered Strobe. After the mode is
set, the output will be high. When the count is loaded,
the counter will begin counting. On terminal count, the
output will go low for one input clock period, then will
go high again.
If the count register is reloaded during counting, the new
count will be loaded on the nest Cl K pu Ise. The count
will be inhibited while the GATE input is low.
MODE 5: Hardware Triggered Strobe. The counter will
start counti ng after the risi ng edge of the tr igger input
and will go low for one clock period when the terminal
count is reached. The counter is retriggerable. The output
will not go low until the full count after the rising edge
of any trigger.
High
Low or Going Low
Rising
°
Disables counting
--
2
1) Disables counting
2) Sets output immediately high
1) Reloads counter
2) Initiates counting
Enables counting
3
1) Disables counting
2) . Setsoutput immediately high
1) Reloads counter
2) Initiates counting
Enables counting
4
Disables counting
Modes
1
1) Initiates counting
2) Resets output after next clock
--
5
--
-Figure 4.
Initiates counting
Enables counting
--
Enables counting
--
Gate Pin Operations Summary
UM8253 Read/Write Procedure
Write Operations
The systems software must program each counter of the
UM8253 with the mode and quantity desired. The
programmer must write out to the UM8253 a MODE
control word and the programmed number of count register
bytes (lor 2) prior to actually using the selected counter.
The actual order of the programming is quite flexible.
Writing out of the MODE control word can be in any
sequence of counter selection, e.g., counter #0 does not
have to be first or counter #2 last. Each counter's MODE
·control word register has a separate address so that its
loading is completely sequence independent. (SCO, SC1)
The loading of the Count Register with the actual count
value, however, must be done in exactly the sequence
programmed in the MODE control word (RlO, RL1). This
loading of the counter's count register is still sequence
independent I ike the MOD E control word loading, but
when a selected count register is to be loaded it must be
loaded with the number of bytes programmed in the MODE
control word (R lO, R L1). The one or two bytes to be
loaded in the count register do not have to follow the
associated MODE control word. They can be programmed
at any time following the MODE control word loading as
long as the correct number of bytes is loaded in order.
All counters are down counters. Thus, the value loaded
into the count register will actually be decremented.
loading all zeroes into a count register will result in the
4
maximum count (l6 for Binary or 10 for BCD). In
7-150
UMS253/ UMS253-5
MODE 0: INTERRUPT ON TERMINAL COUNT
MODE 3: SQUARE WAVE GENERATOR
CLOCK
CLOCK
I
I
WRn~
I
OUTPUT In=4)
I
OUTPUT In=5)
, _ _ _.....0",1- - - - - _ _ _---.,._3....
OUTPUT
(INTERRUPT)
~ n ~
In=4)
I
I
I
I
WAm
GATE
------..,:L-.J
1
OUTPUT
(INTERRUPT)
A
O~
_ __
'----.r------
'-.r-'
Im=5)
B
A+B= m
MODE 1: PROGRAMMABLE ONE-HOT
TRIGGER
~
OUTPUT
4
-----,
3
2
1
MODE 4: SOFTWARE TRIGGERED STROBE
OUTPUT
a
~I------
In=4)
LOAon~
TRIGGER~
43
OUTPUT
GATE
4 3 2 1 0 . . -_ _ __
---,
4
I
MODE 2: RATE GENERATOR
MODE 5: HARDWARE TRIGGERED STROBE
CLOCK
CLOCK
WRn
L-J 4
OUTPUT
L=!J
GATE
OUTPUT
LJ
OUTPUT In=4)
OUTPUT In =3)
RESET
----,L__-.Jr---GATE
~
OUTPUT In=4)
°LJ
Figure 5. UM8253 Timing Diagrams
°
MODE
the new count will not restart until the load has
been completed. It will accept one of two bytes depending
on how the MODE control words (R LO, RL 1) are
programmed. Then proceed with the restart operation.
are probably the most common application that uses this
function. The UM8253 contains logic that will allow the
programmer to easily read the contents of any of the three
counters without disturbing the actual count in pro~ress.
Read Operations
There are two methods that the programmer can use to
read the value of the counters. The first method involves
the use of simple I/O read operations of the selected
counter. By controlling the AO, A 1 inputs tb the UM8253
the programmer can select the cOl:.lnter to be read
In most counter applications it becomes necessary to read
the value of the count in progress and make a .computational decision based on this quantity. Event counters
7-151
I
UM8253/ UM8253-5
(remember that no read operation of the mode register is
allowed AO, A 1-11). The only requirement with this
method is that in order to assure a stable count reading
the actual operation of the selected counter must be
inhibited either by controlling the Gate input or by
external logic that inhibits the clock input. The contents
of the counter selected will be aVailable as follows:
second
(MSB).
I/O
Read
contains the most significant byte
Due to the internal logic of the UM8253 it is absolutely
necessary to complete the entire reading procedure. If two
bytes are programmed to be read then two bytes must be
read before any loading WR command can be sent to the
same counter.
first I/O Read contains the least significant byte (LSBl.
Read Operation Chart
A1
AO
RD
0
0
0
Read Counter No. 0
0
1
0
Read Counter No.1
1
0
0
Read Counter No.2
1
1
0
Illegal
Reading While Counting
In order for the programmer to read the contents of any
counter without effecting or disturbing the counting
operation the UM8253 has special internal logic that can
be accessed using simple WR commands to the MODE
register. Basically, when the programmer wishes to read
the contents of a selected counter "on the fly" he loads
the MODE register with a special code which latches the
present count value into a storage register so that its
contents contain an accurate, stable quantity.
The
programmer then issues a normal read command to the
selected counter and the contents of the latched reg·ister
is available.
MODE Control Word
Counter n
Note:
LSB
Count Register byte
Counter n
MSB
Count Register byte
Counter n
Format shown is a simple example of loading the UM8253 and does not imply
that it is the only for
Figure 6. Programming Format
MODE Register for Latching Count
AO,A1=11
The same limitation applies to this mode of reading the
counter as the previous method. That is, it is mandatory
SC1, SCO - specify counter to be latched.
05, 04
- 00 designates counter latching operation.
X
- don't care.
to complete the entire read operation as programmed.
This command has no effect on the counter's mode.
7-152
UM8253/ UM8253·5
At
Ao
No.1
MODE Control Word
Counter 0
1
1
No.2
MODE Control Word
Counter 1
1
1
No.3
MODE Control Word
Counter 2
1
1
No.4
LSB
Count Register Byte
Counter 1
0
1
No.5
MSB
Count Register Byte
Counter 1
0
1
No.6
LSB
Count Register Byte
Counter 2
1
0
No.7
MSB
Count Register Byte
Counter 2
1
0
No.8
LSB
Count Register Byte
Counter 0
0
0
No.9
MSB
Count Register Byte
Counter 0
0
0
Note: The exclusive addresses of each counter's count register make the task of programming the UM8253 a very
simple matter, and maximum effective use of the device will result if this feature is fully utilized.
Figure 7. Alternate Programming Formats
3MHz
+2
elK
1.5MHz
elK
UMSOS5
UMS253·5
If an UM8085 clock output is to drive an UM8253-5 clock input, it must be reduced to 2MHz or less.
™Clock Interface*
Figure S. MCS-S5
Ordering Information
Part Number
ClK
UM8253
2.6MHz
UM8253-5
5MHz
7-153
"" """ <
0.45
--A
0 .8
DEVICE
UNDER
TEST
20
AC TESTING INPUTS ARE DRI'VEN AT 2.4V
FOR A LOGIC 1. AND 0.45V FOR A LOGIC 0
TIMING MEASUREMENTS ARE MADE AT 2.0V
FOR A LOGIC 1 AND 0.8V FOR A LOGIC O.
L
C = 150pF
ncIL =150~F
-=
C INCLUDES JIG CAPACITANCE
L
7-156
Cl)UMC
UM8254
Waveforms
WRITE
AO_l
-
tAW
CS
DATA BUS
READ
AO_'
-
tAR--1
CS
DATABUS
-----
RECOVERY
CLOCK AND GATE
ClK
GATE
------"'"'1""1
------~-----~
OU~UTO _ _ _ _~ _ _ _ _ _ _ _ _ _ _+_--'-~-----J~~---------~----------two----------~
7-157
• lAST BYTE OF COUNT BEING WRITTEN
(gUMC
UM8254
Table 1. Pin Description
Symbol Pin No. Type
Name and Function
D7- DO
1-8
I/O
CLKO
9
I
OUTO
10
0
Output 0: Output of Counter 0,
GATE 0
11
I
Gate 0: Gate Input of Counter O.
GND
12
Symbol
Data: Bi-directional three state data bus
lines, connected to system data bus:
Pin No. Type
Name and Function
VCC
WR
24
23
I
Write Control: This Input is low during
CPU write operations.
RD
22
I
Read Control: This input is low during
CPU read operations.
CS
21
I
Chip Select: A low on this input enables
the 8254 to respond to RD and Wli
signals. RD and WR are ignored
otherwise.
20-19
I
Address: Used to select one of the three
Counters or the Control Word Register
for read or write operations. Normally
connected to the system address bus.
Power +5V power supply connection.
Clock 0: Clock Input of Counter O.
Ground: Power supply connection.
AI.AO
ClK2
18
I
OUT2
17
0
Al
Ao
Selects
0
0
1
1
0
1
0
1
Counter 0
Counter 1
Counter 2
Control Word Register
Clock 2: Clock Input of Counter 2.
Out 2: Output of Counter 2.
GATE2
16
I
Gate 2: Gate Input of Counter 2.
ClK 1
15
I
Clock 1: Clock Input of Counter 1.
GATE1
14
I
Gate 1: Gate I nput of Counter 1.
OUT 1
13
0
Out 1: Output of Counter 1.
Functional Description
Block Diagram
General
Data Bus Buffer
The UM8254 is a programmable interval timer/counter
designed for use with microcomputer systems. It is a
general purpose, mUlti-timing element that can be treated
as an array of I/O ports in the system software.
This 3-state, bi-directional, 8-bit buffer is used to interface
the UM8254 to the system bus (see Figure 1).
The UM8254 solves one of the most common problems in
any microcomputer system, the generation of accurate
time delays under software control. Instead of setting
up timing loops in software, the programmer configures
the UM8254 to match his requirements and programs
one of t:1e counters for the desired delay. After the desired
delay, the UM8254 will interrupt the CPU .. Software
overhead is minimal and variable length delays can easily
be accommodated.
ClK 0 /
D7·DO
GATE 0
OUTO
ClK 1
GATE 1
A1
OUT1
Some of the other counter/timer functions common to
microcomputers which can be implemented with the
UM8254 are:
GATE 2
•
•
•
•
•
•
•
•
R~I time clock
Event counter
Digital one-shot
Programmable rate generator
Square wave generator
Binary rate multiplier
Complex waveform generator
Complex motor controller
OUT2
Figure 1. Block Diagram Showing Data Bus Buffer and
ReadlWrite Logic Functions
7-158
UM8254
ReadlWrite Logic
The Read/Write Logic accepts inputs from the system bus
and generates control signals for the other functional
blocks of the UM8254. A1 and Ao select one of the
three counters or the Control Word Register to be read
from/written into. A "low" on the RD input tells the
Um8254 that the CPU is reading one of the counters.
A "low" on the WR input tells the UM8254 that the CPU
is writing either a Control Word or an initial count. Both
RD and WR are qualified by CS; RD and WR are ignored
unless the UM8254 has been selected by holding CS low.
Control Word Register
The Control Word Register (see Figure 2) is selected by the
Read/Write Logic when Ai, Ao = 11. If the CPU then
does a write operation to the UM8254, the data is stored
in the Control Word Register and is interpreted as a Control
Word used to define the operation of the Counters.
J"
The Control Word Register can only be written to; status
information is available with the Read-Back Command.
Figure 3.
Internal Block Diagram of a Counter
The status register, shown in the Figure, when latched,
contains the current contents of the Control Word
Register and status of the output and null count flag.
(See detailed explanation of the Read-Back command.)
The actual counter is labelled CE (for "Counting Element")'
I,t is a 16-bit presettable synchronous down counter.
OLM and OLl are two 8-bit latches. OL stands for
"Output Latch"; the subscripts M and L stand for "Most
significant byte" and "Least significant byte" respectively.
Both' are normally referred to as one unit and called just
OL. These latches normally "follow" the CE, but if a
suitable Counter Latch Command is sent to the UM8254,
the latches "latch" the present count until read by the CPU
and then return to "following" the CEo One latch at a
time is enabled by the counter's Control Logic to drive the
internal bus. This is how the 16-bit Counter communicates
over the 8-bit internal bus. Note that the CE itself cannot
be read; whenever you read the count, it is the 0 L that is
being read.
Figure 2.
Block Diagram Showing Control Word
Register and Counter Functions
Counter 0, Counter 1, Counter 2
These three functional blocks are identical in operation, so
only a single Counter will be described. The internal
block diagram of a single counter is shown in Figure 3.
The Counters are fully independent.
operate in a different Mode.
Each Counter may
The Control Word Register is shown in the figure; it is
not part of the Counter itself, but its contents determ ine
how the Counter operates.
Similarly, there are two 8-bit registers called CRM and CRl
(for "Count Register"). Both are normally referred to as
one until and called just CR. When a new count is written
to the Counter, the count is stored in the CR and later
transferred to the CEo
The Control Logic allows one
register at a time to be loaded from the internal bus.
Both bytes are transferred to the CE simultaneously. CRM
and CRl are cleared when the Counter is programmed.
In this way, if the Counter has been programmed for one
byte counts (either most significant byte only or least
significant byte only) the other byte will be zero. Note
that the CE cannot be written into; whenever a count is
written, it is written into the CR.
The Control Logic is also shown in the diagram. CLK n,
GATE n, and OUT n are all connected. to the outside
world through the Control Logic.
7-159
UM8254
Write Operations
The programming procedure for the UM8254 is very
flexible. Only two conventions need to be remembered:
1)
For each Counter, the Control Word must be written
before the initial count is written.
2)
The initial count must follow the count format
specified in the Control Word (least significant byte
only, most significant byte only, or least significant
byte and then most significant byte).
Since the Control Word Register and the three Counters
have separate addresses (selected by the At, Ao inputs),
and each Control Word specifies the Counter it applies
to (SCO, SCl bits), no special instruction sequence is
Control Word
LSB of count
MSB of count
Control Word
LSB of count
MSB of count
Control Word
LSB of cou nt
MSB of count
Control Word
Contra I Word,
Control Word
LSB of count
LSB of count
LSB of count
MSB of count
MSB of count
MSB of count
-
-
-
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
At
Ao
1
0
0
1
0
0
1
0
0
1
1
1
1
0
0
At
Ao
0
1
1
2
2
1
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
0
0
0
0
1
1
1
2
2
2
0
0
1
2
1
required.
Any programming sequence that follows the
conventions above is acceptable.
A new initial count may be written to a Counter at any
time without affecting the Counter's programmed Mode
in any way. Counting will be affected as described in
the Mode definitions. The new count must follow the
programmed count format.
If a Counter is programmed to read/wrfte two-byte counts,
the following precaution applies: A program must not
transfer control between writing the first and second byte
to another routine which also writes into that same
Counter. Otherwise, the Counter will be loaded with an
incorrect count.
Control Word
Counter 2
Control Word
Counter 1
Control Word
Counter 0
LSB of count
Counter 2
MSB of count
Counter 2
LSB of count
Counter 1
MSB of count - Counter 1
LSB of count - Counter 0
MSB of count - Counter 0
Control Word
Counter 1
Control Word
Counter 0
LSB of count
Counter 1
Control Word
Counter 2
LSB of cou-nt
Counter 0
MSB of count - Counter 1
LSB of count
Counter 2
Counter 0
MSB of count
MSB of count
Counter 2
At
Ao
1
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
At
Ao
1
1
0
1
1
1
1
0
0
1
0
1
1
0
1
1
0
0
1
Note: In all four examples, all counters are programmed to ReadIWrite two-byte counts. These are only four of
many possible programming sequences.
Figure 4. A Few Possible Programming Sequences
Read Operations
It is often desirable to read the value of a Counter without
disturbing the count in progress. This is easily done in the
UM8254.
There are three possible methods for reading the Counters.
The first is through the Read-Back command. The second
is a simple read operation of the Counter, which is selected
with the At, Ao inputs. The only requirement is that
1) the CLK input of the selected Counter must be inhibited
by using either the GATE input or external logic; or 2) the
count must first be latched. Otherwise, the count 'may be
in process of changing when it is read, giving an undefined
result.
7-160
UM8254
UM8254 System Interface
Operational Description
The UM8254 is a component of Microcomputer Systems
and interfaces in the same m~mner as a" other peripherals
of the family. It is treated by the systems software as an
array of peripheral I/O ports; three are counters and the
fourth is'a control register for MODE programming.
General
After power-up, the state of the UM8254is undefined.
The Mode, count value, ar,ld output of a" Counters are
undefined.
How each Counter operates is determined when it is
programmed. Each Counter must be programmed before
it can be l,.Ised. Unused counters need not be programmed.
Basically, the select inputs A o , Al connect to the A o , Al
address bus signals of the CPU. The CS can be derived
directly from the address bus using a linear select method.
Or it can be connected to the output of a decoder, such as
an UM8205 for larger systems.
Programming the UM8254
Counters are programmed by writing a Control Word and
then an initial count.
All Control Words are written into the Control Word
Register, which is selected when AI, Ao = 11. The Control
Word itself specifies which Counter is being programmed.
COUNTER
o!
By contrast, initial counts are written into the Counters,
not the Control Word Register. The Al , Ao inputs are
used to select the Counter to be written into. The format
of the initial count" is determined by the Control Word
used.
COUNTER
Control Word Format
Figure 5.
AI, Ao = 11, CS = 0, RD = 1, WR = 0
UM8254 System Interface
Do
SC1
sca
RWO
RW1
SCO
0
0
1
1
0
1
0
1
Select Counter 0
Select Counter 1
Select Counter 2
Read-Back Command (See Read
Operations)
RW-Read/Write:
RW1
RWO
0
a
0
1
1
0
1
1
Note:
Counter Latch Command (see Read
Operations)
ReadIWrite least significant byte only.
Read/Write most significant byte only.
Read/Write least significant byte first,
then most significant byte.
Don't care bits (X) should be
MO
BCD
M-MODE:
SC-Select Cou nter:
SC1
M1
M2
M2
M1
MO
0
0
a
0
1
X
X
0
1
1
1
1
a
a
0
1
a
1
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
BCD:
Binary Counter 1.6-bits
Binary Coded Decimal (BCD) Counter
(4 Decades)
a to insure compatibility with future UMC products.
Figure 6. Control Word Format
7-161
UM8254
Counter Lateh Command
The other method involves a special software command
called the "Counter Latch Command" Like a Control
Word, this command is written to the Control Word
Register, which is selected when A 1 , Ao = 11. Also like
a Control Word, the SCO, SC1 bits select one of the three
Counters, but two other bits, 05 and 04, distinguish this
command from a Control Word.
06
SC1
SCO
05
I0
I
04
03
O2
01
00
0
X
X
X
X
SCO
0
0
1
1
0
1
0
1
Read least significant byte.
Write new least significant byte.
Read most significant byte.
Write new most significant byte.
Read-Back Command
SC1, SCO - specify counter to be latched
SC1
1.
2.
3.
4.
If a Counter is programmed to read/write two-byte counts,
th.e following precaution applies: A program must not
transfer control between reading the first and second byte
to another routine which also reads from that same
Counter. Otherwise, an incorrect count will be read.
Al,Ao =11; CS=O; RO=1; WR=O
0,
Another feature of the UM8254 is that reads and writes
of the same Counter may be interleaved; for example, if
the Counter· is programmed for two byte counts, the
following sequence is valid.
The read-back command allows the user to check the
count value, programmed Mode, and current state of the
OUT pin and Null Count flag of the selected counter(sl.
Counter
0
1
2
Read-Back Command
The command is written into the Control Word Register
and has the format shown in Figure 8. The command
applies to the counters selected by setting their corresponding bits 03, S2, 01 = 1.
05, 04-00 designates Counter Latch Command
X - don't care
A o , Ai = 11, CS = 0, RO = 1, WR = 0
Note:
Oon't care bits (X) should be 0 to insure
compatibility with future UMC products.
02
05
I
I
11 111 COUNT STATUS CNT21 CNT1 1 CNTol 0
Figure 7.
Counter Latching Command Format
The selected Counter's output latch (0 L) latches the
count at the time the Counter Latch Command is received.
This count is held in the latch until it is read by the CPU
(or until the Counter is reprogrammed). The count is'
then unlatched automatically and th,tl OL returns to
"following" the counting element (CE).
This allows
reading the contents of the Counters "on the fly" without
affecting counting in progress. Multiple Counter Latch
Commands may be used to latch more than one Counter.
Each -latched Counter's OL holds its count until it is read.
Counter Latch Commands do not affect the programmed
Mode of the Counter in any way.
If a Counter is latched and then, some time later, latched
again before the count is read, the second Counter Latch
Command is ignored. The count read will be the count at
the time the first Counter Latch Command was issued.
With either method, the count must be read according to
the programmed format; specifically, if the Counter is
programmed for two byte counts, two bytes must be read.
The two bytes do not have to be read one right after the
other; read or write or programming operations of other
Counters may be inserted between them.
05:
04 :
03 :
O2 :
01:
00 :
0 = Latch count of selected counter(s)
0;= Latch status of selected counter(s)
1 = Select counter 2
1 = Select counter 1
1 = Select counter 0
Reserved for future expansion; must be 0
Figure 8.
Read-Back Command Format
The read-back command may be used to latch mUltiple
counter output latches (OLl by setting the COUNT bit
05 = 0 and selecting the desired counter(s). This single
command is functionally equivalent to several counter
latch commands, one for each counter latched. Each
counter's latched count is held until it is read (or the
counter is reprogrammed). That counter is automatically
unlatched when read, but other counters remain latched
until they are read. If multiple count read-back commands
are issued to the same counter without reading the count,
all but the first are ignored; i.e., the count which will be
read is the count at the time the first read-back command
was issued.
The read-back command maya Iso be used to latch status
information of selected counter(s) by setting STATUS bit
D4=0.· Status must be latched to be read; status of a
counter is accessed by a read from that counter.
7-162
(DUMC
UM8254
The counter status format is shown in Figure 9. Bits D5
. through DO contain the counter's programmed
Mode
exactly as written in the last Mode Control Word.
OUTPUT bit D7 contains the current state of the OUT pin.
This allows the user to monitor the counter's OUtput via
software, possibly eliminating some hardware from a
system.
This Action:
Causes:
A. Write to the control word register. (1)
C. New count is loaded into CE
Null count = 1
Null count = 1
B. Write to the count register (CR):(2)
(CR~CE):
Null count = 0
(1)
Only the counter specified by the control word will have
its null count set to 1. Null count bits of other counters
are unaffected.
I
OUTPUT
I
;OUULN\
I I I
RWl
RWO
M21 Ml
I I I
MO
(2)
BCD
D7 l O u t pin is 1
o Out pin is 0
D6 1
Null count
Count available for reading
Ds - Do = Cou nter progra mmed mose
(See Figure 7)
If the counter is programmed for two byte counts (least
significant byte then most significant byte) null count
goes to 1 when the second byte is written.
o
Figure 10. Null Count Operation
Figure 9. Status Byte
If mu Itiple status latch operations of the counter(s) are
performed without reading the status, all but the first
are ignored; i.e., the status that wi II be read is the_ status
of the counter at the time the first status read-back
command was issued.
NULL COUNT bit D6 indicates when the last count
written to the counter register (CR) has been loaded into
the counting element (CEI. The exact time this happens
depends on the Mode of the counter and is described in
the Mode Definitions, but until the count is loaded into
the counting element (CEl, it can't be read from the
counter. If the count is l<;Itched or read before this time,
the count value will not reflect the new count just written.
The operation of Null Count is shown in Figure 10.
Both count and status of the selected counter(s) may be
latched simultaneously by setting both COUNT
and
STATUS bits D5, D4 = O. This is folJnctionally the same
as issuing two separate read-back commands at once, and
the above discussions apply here also.
Specifically, if
multiple count and/or status read-back commands are
issued to the same counter(s) without any intervening
reads, all but the first are ignored. This is illustrated in
Figure 11.
Command
Descriptions
Results
07
06
05
04
D3
O2
01
Do
1
1
0
0
0
0
1
0
Read back count and status of
Counter 0
Cou nt and status latched for
Counter 0
1
1
1
0
0
1
0
0
Read back stat u's of Counter 1
Status latched for Counter 1
1
1
1
0
1
1
0
0
Read back status of Counters 2, 1
Status latched for Counter 2,
but not Counter 1
1
1
0
1
1
0
0
0
Read back count of Counter 2
Count latched for Counter 2
1
1
0
0
0
1
0
0
Read back count and status of
Counter 1
Count .Iatched for Counter 1,
but not status
1
1
1
0
0
0
1
a
Read back status of Counter 1
Command ignored, status
already latched for Counter 1
Figure 11. Read-Back Command Example
7-163
~UMC
UM8254
If both count and status of a counter are latched, the
first read operation of that counter will return .Iatched
status, regardless of which was latched first. The next
one or two reads (depending on whether the counter is
programmed for one or two t\ .'+: sounts) return latched
count. Subsequent reads return unla+ched count.
CS RD WR Al Ao
0
1
0
0
0
Write into Counter 0
0
1
0
0
1
Write into Counter 1
0
1
0
1
0
Write into Counter 2
0
1
0
1
1
Write Control Word
0
0
1
0
0
Read from Counter 0
0
0
1
0
1
Read from Counter 1
0
0
1
1
0
Read from Counter 2
0
0
1
1
1
No-Operation (3-State)
1
X
X
X
X
No-Operation (3-State)
0
1
1
X
X
No-Operation (3-State)
1) Writing the first byte disables counting.
low immediately (no clock pulse required).
OUT is set
2) Writing the second byte allows the new count to be
loaded on the next C l K pulse.
This allows the counting sequence to by synchronized
by software. Again, OUT does not go high until N + 1
Cl K pulses after the new count of N is written.
If an initial count is written while GATE=O, it will still be
loaded on the next ClK pulse. When GATE goes high,
QUT will go high N ClK pulses later; no ClK pulse is
needed to load the Counter as th is has a Iready been done.
cw =
10
LSB
= 4,;-_ _ _ _ _ _ _ _ _ __
WR~
ClK
GATE.
OUT
~L.._ _ _ _ _ _ ____'
I I I I I ~ I ~ I ~ I ~ I g I~~ I~~ I
N
Figure 12. ReadlWrite Operations Summary
N
N
CW = 10
WR
Mode Defin itions
The following are defined for use. in describing the
operation of the UM8254.
ClK pulse:
trigger:
a rising edge, then a falling edge, in that
order, of a Counter's ClK input.
a rising edge of a Counter's GATE input.
Counter loading:
N
lSB = 3
~---------------
ClK
GATE
r-
OUT::-l
I I I I I ~ I ~ I .~ I I
the transfer of a count from the c::R
to the CE (refer to the "Functional
Description")
N
N
N
CW
= 10
lSB
N
I~ I~~
0
=3
lSB
I
=2
WR
MODE 0: Interrupt on Terminal Count
ClK
Mode 0 is typically used for event counting. After the
Control Word is written, OUT is initially low, and will
remain low until the Counter reaches zero. OUT then
goes high and remains high until a new count or a new
Mode 0 Control Word is written into the Counter.
GATE = 1 enables counting; GATE = 0 disables counting.
GATE has no effect on OUT. '
After the Control Word and initial count are written to a
Counter, the initial count will be loaded on the next ClK
pulse. This C lK pulse does not decrement the count, so
for an initial count of N, OUT does not go high untill
N + 1 ClK pulses after the initial count is written.
If a new count is written to the Counter, it will be loaded
on the next ClK pulse and counting will continue from
the new count. If a two-byte count is written, the
following happens:
7-164
GATE
OUT
.....Ir-
::JI...-___-:--___
I I I I I I ~ I I ~ I I ~ I ~~ I
N
N
N
N
0
0
0
Note: THE FOLLOWING CONVENTIONS APPLY TO ALL MODE TIMING DIAGRAMS:
1. COUNTERS ARE PROGRAMMED FDR BINARY (NOT BCDI COUNTING AND FOR
READINGIWRITING LEAST SIGNIFICANT BYTE(LSBI ONLY
2. THE COUNTER IS ALWAYS SELECTED (CS ALWAYS LDW)
3. CW STANDS FOR "CONTROL WORD". CW=10 MEANS A CONTROL WORD OF 10. HEX
IS WR ITTEN TO THE COUNTER.
4. LSB STANDS FOR "LEAST SIGNIFICANT BYTE" OF COUNT.
5. NUMBERS BELOW DIAGRAMS ARE COUNT VALUES.
THE LOWER NUMBER IS THE LEAST SIGNIFICANT BYTE
THE UPPER NUMBER IS THE MOST SIGNIFICANT BYTE. SINCE THE COUNTER IS
PROGRAMMED TO READIWRITE LSB ONLY. THE MOST SIGNIFICANT BYTE CANNOT
BE READ.
N STANDS FOR AN UNDEFINED COUNT.
VERTICAL LINES SHOW TRANSITIONS BETWEEN COUNT VALUES.
Figure 13. Mode 0
UM8254
MODE 1: Hardware Retriggerable One·Shot
MODE 2: Rate Generator
Out will be initially high. OUT will go Iowan the ClK
pulse following a trigger to begin the one-shot pulse,
and will remain low until the Counter reaches zero. OUT
will then go high and remain high until the ClK pulse
after the next trigger.
This Mode functions like a divide-by-N counter. It is
typically used to generate a Real Time Clock interrupt.
Out will initially be high. When the initial count has
decremented to 1, OUT goes low for one ClK pulse.
OUT then goes high again, the Counter reloads the initial
count and the process is repeated. Mode 2 is periodic;
the same sequence is repeated indefinitely. For an initial
count of N, the sequence repeats every N ClK cycles.
After writing the Con.trol Word and initial count, the
Counter is armed. A trigger results in loading the Counter
and setting OUT Iowan the next ClK pulse, thus starting
the one·shot pulse. An initial count of N will result in a
one-shot pulse N Cl K cycles in duration. The one-shot
is retriggerable, hence OUT will remain low for N ClK
pulses after any trigger. The one-shot pulse can be repeated
without rewriting the same count into the counter. GATE
has no effect on OUT.
GATE = 1 enables counting; GATE = 0 disables counting.
If GATE goes low during an output pulse, OUT is set high
immediately.
A trigger reloads the Counter with the
initial count on the next ClK pulse; OUT goes low NClK
pulses after the trigger. Thus the GATE input can be used
to synchronize the Counter.
If a new count is written to the Counter during a one-shot
pulse, the current one-shot is not affected unless the
Counter is retriggered. In that case, the Counter is loaded
with the new count and the one-shot pulse continues until
the new count expires.
After writing a Control Word and initia I count, the Counter
will be loaded on the next ClK pulse. OUT goes low N
ClK Pulses after the initial count is written. This allows
the Counter to be synchronized by software also.
CW-12
lSB- 3
CW=14 lSB-3
WR~~----------------
WR~~---------------
ClK
ATE
OUT
I NI NI NI NI NI ~ I ~ I ~ I gI ~~ I ~ I ~ I
CW= 14 lSB =3
WR~~--------------CW=:12
lSB
K
3_------------
WRLJ1...J
ClK
ClK
GATE
OUT
-------1n----1n----------
:::.:J
r
INININININI~I~I~I~I~I
Igi
CW = 12
WR
lSB
=2
LJ
GATE
OUT
=.:J
CW = 14 lSB
WR
lSB =4
=4
LSB = 5
r__------
~-------
ClK
ClK
GATE
OUT
:.:..:::.J
u
OUT
I I I I I I I
0
1
0
0
FF
FF
FF
FE
0
4
0
3
Figure 14. Mode 1
Note: A GATE transition should not occur one clock
prior to terminal count.
Figure 15. Mode 2
7-165
U)UMC
UM8254
Writing a new count while counting does not affect the
current counting sequence. If a trigger is received after
writing a new ·count but before the end of the current
period, the Counter will be loaded with the new count
on the next ClK pulse and counting will continue from
the new count. Otherwise, the new count will be loaded
at the end of the current counting cycle. In mode 2, a
COUNT of 1 is illegal.
CW"16 lSB=4
WR~~-------------------ClK
GATE
OUT
ININ/
NINI~ I~ /~I~I~I~I~ I~ I~I~I
CW = 16 lSB= 5
WR~-----------------------
MODE 3: Square Wave Mode
CW" 16' lSB =4
WR~~--------------------
Mode 3 is typically used for Baud rate generation. Mode 3
is similar to Mode 2 except for the duty cycle of OUT.
OUT will initially be high. When half the initial count
has expired, OUT goes low for the remainder of the Count.
Mode 3 is periodic; the sequence above is repeated
indefinitely. An initial count of N results in a square wave
with a period of N ClK cycles.
GATE = 1 enables counting; GATE = 0 disables counting.
If GATE goes low while OUT is low, OUT is set high
immediately; no ClK pulse is required. A trigger reloads
the Counter with the initial count on the next ClK pulse.
Thus the GATE input can be used to synchron ize the
Counter.
Note: A GATE transition should not occur one clock
prior to terminal count.
Figure 16. Mode 3
After writing a Control Word and initial count, the Counter
will be loaded on the next ClK pulse. This allows the
Counter to be synchronized by software also.
MODE 4: Software Triggered Strobe
Writing a new count while counting does not affect the
current counting sequence. If a trigger is received after
writing a new count but before the end of the current
half-cycle of the square wave, the Counter will be loaded
with the new count on the next C l K pulse and counting
will continue from the new count. Otherwise, the new
count will be loaded at the end of the current half-cycle.
OUT will be initially high. When the initial count expires,
OUT will go low for one ClK pulse and then go high again.
The counting sequence is "triggered" by writing the initial
count.'
GATE
1 enables counting; GATE
GA TE has no effect on OUT.
=0
=0
0 disables counting.
Mode 3 is implemented as follows:
Even counts: OUT is initiallY high. The initial count is
loaded on one C lK pulse and then is decremented by
two on succeeding ClK pulses. When the count expires
OUT changes value and the Counter is reloaded. with the
initial count. The above process is repeated indefinitely.
Odd counts:
OUT is initially high. The initial count
minus one (an even number) is loaded on one ClK pulse
and then is decremented by two on succeeding ClK pulses.
One ClK pulse after the count expires, OUT goes low
and the Counter is reloaded with the initial count minus
one. Succeeding ClK pulses decrement the count by two.
When the count expires, OUT goes high again and the
Counter is reloaded with the initial count minus one. The
above process is repeated indefinitely. So for odd counts,
OUT willbe high for (N+1)/2 counts and low for (N-l )/2
counts.
After writing a Control Word and initial count, the Counter
will be loaded on the next ClK pulse, This ClK pulse
does not decrement the count, so for an initial count of N,
OUT does not strobe low until N+l ClK pulses after the
initial count is written.
If a new count is written during counting, it will be loaded
on ~he next C lK pulse and counting will continue from the
new count. If a two-byte count is written, the following
happens:
1) Writing the first byte has no effect on counting.
2) Writing the second byte allows the new coun) to be
loaded on the next ClK pulse.
This allows the sequence to be "retri~lgered" by software.
OUT strobes low N+l ClK pulses after the new count of
N is written.
7-166
(l)UMC
UM8254
CW-1A
CW-18 lSB-3......_ _ _ _ _ _ _ _ _ __
lSB-3
WR~----------------
WRWL.J
ClK
ClK
-------, n---------'rr..=
GATE
GATE
U
I I I I I ~ I g I ? I g I~~ I ~~ I ~61
OUT=:J
N
N
N
,
OUT
I I I I I I ~ I gI I g I~~ I g I
N
N
N
CW=18 lSB=3 ......_ _ _ _ _ _ _ _ _ __
CW=lA
WRLJ--u
WR
ClK
GATE
,
N
N
N
lSB=~3------------__
"""L.JLj
ClK
GATE - - - - - - - -
-1n:.:Jf\-- ---- -- ----
-----------~
UI I I I I gig I gig I ? I g I ~~ I
N
N
N
I I I I I I I gig I gig I? Ig I~~ I
N
N
lSB =2
WR
~
OUT:.::J
OUT:..-J
N
CW = lA
--------
N
N
N
lSB = 3
N
lSB =
5_--------
WR
ClK
ClK
GATE
GATE
UI I I I I ~ I g I I g I ?I g I ~~ I
OUT=:J
N
N
N
--------In----------'"\n-----
U
OUT=.J
I I I I I I g I ~ I ? I g I~~ I~~ I~ I ~ I
N
N
Figure 17. Mode 4
N
N
N
N
Figure 18. Mode 5
MODE 5: Hardware Triggered Strobe (Retriggerable)
OUT will initially be high. Counting is triggered by a rising
edge of GATE. When the initial count has expired, OUT
will go low for one ClK pulse and then go high again.
After writing the Control Word and initial count, the
counter will not be loaded until the C lK pulse after a
trigger. This C lK pu Ise does not decrement the count,
so for an initial count of N, OUT does not strobe low
until N+ 1 ClK pulses after a trigger.
A trigger results in the Counter being loaded with the
initial count on the next ClK pulse. The counting
sequence is retr iggera ble. OUT wi II not strobe low for
N+l ClK pulses after any trigger. GATE has no effect
on OUT.
If a new count is written during counting, the current
counting sequence will not be affected. If a trigger occurs
after the new count is written but before the current
count expires, the Counter will be loaded with the new
count on the next C L K pulse and counting wi IJ continue
from there.
7-167
(lJUMC
UM8254
Low or Going Low
Signal Status Modes
Rising
Disables counting
0
Enables counting
--
1
High
1) Initiates counting
2) Resets output after next clock
--
2
1) Disables counting
2) Sets output immed iately high
Initiates counting
Enables counting
3
1) Disables counting
2) Sets output immediately high
Initiates counting
Enables counting
Disables counting
4
5
--
Initiates counting
--
Enables counting
--
Figure 19. Gate Pin Operations Summary
Gate
I
Mode
Min
Count
Max
Count
0
1
0
1
1
0
2
2
0
3
2
0
4
1
0
5
1
0
The GATE input is always sampled on the rising edge of
ClK. In Modes 0, 2, 3, and 4 the GATE input is level
sensitive, and the logic level is sampled on the rising edge
of ClK. In Modes 1,2,3, and 5 the GATE input is risingedge sensitive. I n these Modes, a rising edge of GATE
(trigger) sets an edge-sensitive flip-flop in the Counter.
This flip-flop is then sampled on the next rising edge of
ClK; the flip-flop is'reset immediately after it is sampled.
In this way, a trigger will be detected no matter when it
occurs - a high logic level does not have to be maintained
unti I the next risi ng edge of C l K. Note that in Modes 2
and 3, the GATE input is both edge- and level- sensitive.
In Modes 2 and 3, if a C lK source other than the system
clock is used, GATE should be pulsed immediately
following WR of a new count value.
Note: 0 is equivalent to 2 16 for binary counting and
104 for BCD counting.
Counter
New counts are loaded and Counters are decremented on
the falling edge of ClK.
Figure 20. Minimum and Maximum Initial Counts
The largest possible initial count is 0; this is equivalent to
2 16 for binary counting and 104 for BCD counting.
Operation Common to All Modes
Programming
When a Control Word is written to a Counter, all Control
logic is immediately reset and OUT goes to a known
initial state; no ClK pulses are required for this.
The Cou nter does not stop when it reaches zero. I n Modes
0, 1, 4, and 5 the Counter "wraps around" to the highest
count, either FFFF hex for binary counting or 9999 for
BCD counting, and continues counting. Modes 2 and 3
are periodic; the Counter reloads itself with the initial
count and continues counting from there.
7-168
. L
-- - ---
---
-
-- -
f--- -
--
---- - - r--
- --
,,\'7
.1::>'
CS
AO
-
00·7
"
INTA
'7
r--INT
CAS 0
UM8259A
SLAVE A
SP/EN
7
6
5
4
J IIII j j
7
6
5
4
00·7
AO
I-t
n-l
CAS 1
""I
)
f+-··lI --
r-
-
CS
---------
r--
'"II
INTA
UM8259A
SLAVE B
.,
6
5
4
3
2
1
"IT
CAS 0
CAS 0
CAS 1
CAS 1
0
o~ 1 111[11!
7
INTERRUPT REQUESTS
Figure 9.
Cascading the UM8259A
7-185
",,;
0
INT
CAS 2
~/E-N
~
L
L
AO
00·7
TI\IIA
""7
INT
UM8259A
MASTER
CAS 2
rsP/EN·
M7 M6 M5
M4
"11, tIl
5
4
M3
M2
Ml
MO
,I!I
eUMC
UM82C6818
~=;:=::;==;;;=== Real
Clock
fll
Plus Time
RAM (RTC)
Features
•
•
•
•
•
•
•
•
•
•
•
Internal time base and oscillator
Counts seconds, minutes, and hours of the day
Counts days of the week, date, month, and year
3V to 6V operation
Time base input options: 4.194304 MHz, 1.048576 MHz,
or 32.768 kHz
Time base osci lIator for parallel resonant crystals
Binary or BCD representation of time, calendar, and
alarm
12 or 24-hour clock with AM and PM in 12-hour mode
automatic end of month recognition
automatic leap year compensation
Multiplexed bus for pin efficiency
•
•
•
•
•
•
Interfaced with software as 64 RAM locations
- 14 bytes of clock and control registers
- 50 bytes of general purpose RAM
Status bit indicates data integrity
Bus compatible interrupt signals (IRQ)
Three interrupts are separately software maskable and
testable
Time-of-day alarm, once-per-second to once-per-day
- Period ic rates from 30 .51ls to 500 ms
- End-of-clock update cycle
Programmable square-wave output signal
Clock output may be used as microprocessor clock input
- At ti me base frequency +1 or +4
General Description
The UM82C6818 Real-Time Clock plus RAM is fabricated
in high performance CMOS process to interface with 1MHz
processor buses. It combines three unique features: a
Pin Configuration
complete time-of-day clock with alarm and one hundred
year calendar, a programmable periodic interrupt and
square-wave generator, and 50 bytes of static RAM.
Block Diagram
7-186
(l)UMC
UM82C8167A
Real Time Clock (RTC)
Feature
•
•
•
•
•
Microprocessor compatible (8-bit data bus)
Milliseconds through month counters
56 bits of RAM with comparator to compare the real
time counter to the RAM data
2 INTERRUPT OUTPUTS with 8 possible interrupt
signals
Single +5V power supply
•
POWE R DOWN input that disables all inputs and
outputs except for one of the interrupts
• Status bit to indicate rollover during a read
• 32,768 Hz crystal oscillator
• Four-year calendar (no leap year)
• 24-hour clock
• 24 pin dual-in-line package
General Description
The UM82C8167A is a Si-gate CMOS LSI used as a real
time clock in micro system. This product includes an
addressable real time counter, 56 bits of static RAM and
two interrupt outputs. User can disable the chip from the
Pin Configuration
cs
AD
Block Diagram
VDD
POWER DOWN
WR
D7
RDY
D6
AO
D5
A1
D4
A2
D3
A3
D2
Os
AD
R5Y
I
WR
A4
D1
OSC1
DO
OSC2
STANDBY INTERRUPT
OUTPUT
D2
INTERRUPT OUTPUT
D4
Vss
rest of the system for standby low power operation by
using of a POWER DOWN inpLIt. With an on chip
oscillation circuit, it can generate the 32,768 Hz time
base.
POWER DOWN
D1
D5
7-187
SUMO
-============
fl~
UM82450 / UM825 0
Asynchronous
Communication
Element
(ACE)
Feature
•
•
•
•
•
•
•
Adds or deletes standard asynchronous communication
bits (Start, Stop, and Parity) to or from serial data
stream
Full double buffering eliminates need for precise
synchronization
Independently controlled transmit, receive, line status,
(
and data set interrupts
Programmable baud rate generator allows division of
any input clock by 1 to (2 16 - 1) and generates the
internal 16x clock
I ndependent receiver clock input
Modem control functions (CTS, RTS, DSR, DTR, RI,
and carrier detect)
Single +5 volt power supply
•
•
•
•
•
•
•
Fully programmable serial-interface characteristics
5-,6-,7-, or 8-Bit characters
- Even, Odd, or No-Parity bit generation and detection
...;.. 1-,1 %-, or 2-Stop bit generation
- Baud rate generation (DC to 56K baud)
False start bit detection
Complete status reporting capabilities
Easily interfaces to most popular microprocessors
Line break generation and detection
Internal diagnostic capabilities
- Loopback controls for communications link fault
isolation
- Break, parity, overrun, framing error simulation
Full prioritized interrupt system controls
General Description
UM82450 and UM8250 are programmable Asynchronous
Communication Element (ACE) chips fabricated with
Si -Gate NMOS process. The UM82450 is an improved
specification version of the UM8250. These two products
perform serial-to-parallel conversion on data characters
received from the CPU. The CPU can read the complete
status of the ACE at any time during the functional
operation. They also includes a programmable baud rate
generator that is capable of dividing the timing reference
clock input by divisors of 1 to (2 16 - 1), and producing
a 16x clock for driving the internal transmitter logic.
Pin Configuration
DO
VCC
01
AT
02
03
RLSO
OSR
04
CTS
05
MR
06
OUT1
07
RCLK
SIN
OTR
RTS
OUT2
INTRPT
SOUT
CSO
NC
CS1
AO
CS2
A1
A2
BAUOOUT
XTAL1
ADS
XTAL2
CSOUT
OOIS
OOSTR
DOSTR
DISTR
OISTR
VSS
7-188
UM82450/ UM8250
Block Diagram
D7.DO
~
DATA
BUS
BUFFER
INTERNAL
DATA BUS
~
,---
~
rV
AO
A1
A2
--
~
r-V
CSO) CS1 _
2_
CS
RECEIVER
BUFFER
REGISTER
V
RECEIVER
SHIFT
REGISTER
A
~
~ECEIVER
LINE
CONTROL
REGISTER
TIMING
&
-
t---
DIVISOR
LATCH (LS)
-
BAUD
GENERATOR
DIVISOR
LATCH (MS)
-
DOSTR DDI S CSOU T XTAL1 XTAL 2 -
=;
&
CONTROL
~ TRANSMITTER
HOL DING
REGISTER
=>
MODEM
CONTROL
REGISTER
~
~
IV'
~
'-----
MODEM
STATUS
REGISTER
INTERRUPT
ENABLE
REGISTER
INTERRUPT
ID
REGISTER
BAUDOUT
TRANSMITTER
TIMING
LINE
STATUS
REGISTER
-v'
I---R CLK
CONTROL
AD
S-
SELECT
MR
&
DIST R _ CONTROL
LOGIC
DIST R _
DOST R _
I'---SI N
...J\"
/
~
TRANSMITTER
SHIFT
REGISTER
r----
..,J\
)
v
"
~
~
A
'"
7-189
RTS
I - - - CTS
DIR
I - - DSR
I - - RLSD
r----
MODEM
CONTROL
LOGIC
A
r---- SOUT
J4-- AT
I---I---INTERRUPT
CONTROL
LOGIC
JJ
OUT1
OUT2
INTRPT
8-2
(l)UMC
GUIDE TO MOS HANDLING
We at UMC are continually look ing for more effective
ways to provide protection for MOS devices. Present
configurations of protective devices are the result of years,
of research and review of field problems.
G.
Transport all parts in conductive trays. Do not use
plastic containers. Store axial leaded parts in conductive foam, e.g. Velofoam #7611.
H.
All equipment used in the assembly area must be
thoroughly grounded.
Attention should be given
to equipment that may be inductively coupled and
generate stray voltages. Soldering irons must have
grounded tips.
Grounding must also be provided
for solder posts, reflow soldering equipment, etc.
I.
It is advisable to place a grounding clip across the finger
of the ~oard to ground all leads and line on the board
during assembly of I Cs to printed circuit boards.
J.
Use of carpets is discouraged in work areas, but in
other areas, carpets may be treated with anti -static
solution to reduce static generation.
K.
Handle MOS parts on condu'ctive surfaces and the
handler must touch the conductive surface first before
touching the parts.
l.
Furthermore, no power should be applied to the socket
or board when the MOS device is being inserted. This
permits any static' charge accumulated on the MOS ,
device to be safely removed before power is applied.
Even though the oxide breakdown may be far beyond the
voltage levels encountered in normal operatio'n, excessive
voltages may cause permanent damage. We recognize
that it is not 100 percent effective despite 'our evolving
the best designed protective device possible.
A large number of failed returns have been due to misapplication of biases. In particular, forward bias conditions
cause excessive current through the protective devices,
which in turn will vaporize metal lines to the inputs.
Careful inspection of the device data sheets and proper
pin designation should help reduce this failure mode.
Gate ruptures caused by static discharge .have also accounted for a large per-centage of device failures in customers' manufacturing areas. Precautions should be taken
to minimize the possibility of static charges which occur
during handling and assembly of MOS circuits.
The following guidelines for handling MOS are offered to
assist our customers in reducing the hazards which may
be detrimental to MOS circuits. Precautions listed herein
are used at UMC.
A.
B.
C.
Cover all benches~used for assembly or test of MOS circuits with conductive sheets. Warning: Never expose an
operator directly to a hard electrical ground. Forsafety
reasons, the operator must have a resistace of at least
100K Ohms between himself and hard electrical ground.
Have grounding plates on door and/or floor of all
entrances to work areas. This must be contacted by
people entering the area.
Wear conductive straps inside and outside of employees' shoes so that body charges are grounded
when entering work area.
D.
Wear Anti-static neutralized smocks to eliminate
the possibility of static charges being generated by
friction of normal wear.
The two types available
are Dupont anti-static nylon and Dupont neutralized
65 percent polyester/35 percent cotton.
E.
Wear cotton gloves while handling parts. Nylon gloves
and rubber finger cots are not allowed.
F.
To help reduce generation of static voltages, humidity
is controlled at a minimum of 35 percent.
M. Do not handle MOS leads by their leads unless absolutely necessary.
Handle MOS devices by their
packages as much as possible.
N.
In general, materials prone to static charge accumulation should not come in contact with MOS devices.
Observe these precautions even when an MOS device is
suspected of being defective. The real cause of failure
cannot be accurately determined if the device is damaged~
because of static charge build-up.
IMPORTANT REMINDER: EVEN THE MOST ELABORATE PHYSICAL PREVENTION TECHNIQUES WILL
NOT ELIMINATE DEVICE FAI LURE IF PERSONNE L
ARE NOT FULLY TRAINED IN PROPER HANDLING
OF MOS DEVICES.
For further information, please contact Quality Assurancel
Reliability Department.
United Microelectronics Corp.
NO.3 Industrial East Third .Road
Science- Based Industrial Park
Hsinchu City, Taiwan Republic of China
8-3
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