UP 7685_1106_System_Description_Apr69 7685 1106 System Description Apr69

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User Manual: UP-7685_1106_System_Description_Apr69

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UNIVAC

liDS
ERRATA SHEET TO
SYSTEM DESCRIPTION,
UP·7685
Programming Information
Exchange
Bu Iletin 1, UP·7700.1

.Page 6, Figure 2-1 -- Minimum system requirement is 2
UNISERVO* VI C or 2 UNISERVO* VIII C Magnetic Tape Units •
• Page 30, paragraph 4.7.9. -- At end of paragraph, add:
"*The j and a fields together serve to specify any of the
128 control registers."
.Page 51, Table of UNISERVO* VIII C CHARACTERISTICS - For
TAPE SPEED, change "42.5" to read "120" •
• Page 93, Appendix B -- For topmost word format, change
"MULTI PLE" to read "MULTI PLY" •
• Page 105, Appendix D -- In introductory sentence, change
"STAT-PACK" to read "MATH-PACK".
Please mark your copies of UP-7685 according to this Errata
Sheet. Bulk distribution being made is the same as distribution for UP-7685. For details refer to original bulk distribution sheet. For additional copies, this sheet and
original manual order via a Sales Help Requisition through
your local Univac Representative from Holyoke, Massachusetts.
All Holyoke stock will contain this Errata Sheet.
MANAGER, Documentation and Library Services
*Trademark of S erry Rand Cor orationp-__----------1ST UP-7700.1 to Lists lOU, 217, 630,
692 and distribution on Special Bulk
Distribution Sheet.

OAT

April 25, 1969

01 VISION OF SPERRY RAND CORPORA TION

S.P L . S, P.O. BOX 8 1 00 PHILADELPHIA, PA. 19101

U P-38C50

REV. 2

PRINTED IN U.S.A.
© 1969 _ SPERRY RAND CORPORATION

CONTENTS

1. INTRODUCTION
2. SYSTEM DESCRIPTION

2.1. GENERAL

2.2. SYSTEM COMPON ENTS
2.2.1. Central Processor
2.2.2. Main Storage
2.2.3. Auxiliary Storage
2.2.4. Operator's Control Console

3
3
3
3
4

2.3. CONFIGURATIONS

3. MAIN STORAGE

3.1. GENERAL

3.2. STORAGE MODULE

3.3. PACKAGING

3.4. STORAGE CAPACITY

3.5. STORAGE PROTECTION
3.5.1. Storage Protection Modes
3.5.1.1. Privileged Mode
3.5.1.2. User Program Mode

10
10
10
10

3.6. RELATIVE ADDRESSING

4. CENTRAL PROCESSOR UNIT

4.1. GENERAL

4.2. PRINCIPAL SECTIONS

4.3. INSTRUCTION WORD FORMAT
4.3.1. Function Code
4.3.2. Partial-Word or Immediate Operand Designator
4.3.3. Control Register Designato r
4.3.4. Index Register Designator
4.3.5. Index Modification Designator
4.3.6. Indirect Address Designator
4.3.7. Address Field

13
13
13
13
13
13
13
14

4.4. CO NTRO L REG ISTERS
4.4.1. Index Registers
4.4.2. Arithmetic Accumulators
4.4.3. Access Control Registers
4.4.4. R Registers
4.4.4.1. RO - Real Time Clock
4.4.4.2. R1 - Repeat Counter
4.4.4.3. R2 - Mask Register

14
14
15
15
15
15
17
17

4.5. ARITHMETIC SECTION
4.5.1. The Adder
4.5.2. Arithmetic Accumulators
4.5.3. Parti ai-Word Transfers
4.5.4. Split-Word Arithmetic
4.5.5. Sh i fti ng
4.5.6. Double-Precision Fixed-Point Arithmetic
4.5.7. Floating-Point Arithmetic

17
18
18
18
19
19
20
20

4.6. EXECUTIVE SYSTEM CONTROL FEATURES
4.6.1. Processor State Register
4.6.2. Interrupts
4.6.3. Guard Mode

22
22
24
24

4.7. INSTRUCTION REPERTOIRE
4.7.1. Data Transfer Instructions
4.7.2. Fixed-Poi nt Arithmeti c
4.7.3. Floating-Point Arithmetic
4.7.4. Index Regi ster Instructions
4.7.5. Logical Instructions
4.7.6. Shift Instructions
4.7.7. Repeated-Search Instructions
4.7.8. Unconditional Jump Instructions
4.7.9. Conditional Jump Instructions
4.7.10. Test (or Skip) Instructions
4.7.11. Executive System Control Instructions
4.7.12. InpuVOutput Instructions
4.7.13. Other Instructions

26
26
27
27
28
28
29
29
30
30
30
31
31
31

5. PROCESSOR INPUT/OUTPUT CONTROL SECTION

5.1. GENERAL DESCRIPTION

5.2. PERIPHERAL CONTROL

5.3. INTERNALLY SPECIFIED INDEX MODE

5.4. EXTERNALLY SPECIFIED INDEX MODE

5.5. BUFFER MODE DATA TRANSFERS

5.6. INPUT/OUTPUT INFORMATION WORDS
5.6.1. DataWords
5.6.2. Function Words
5.6.3. Identifier Words
5.6.4. Status Wo rds

35
35
36
36
36

5.7. PRIORITY CONTROL

5.B. INPUT/OUTP UT INSTRUCTIONS
5.B.1. Monitored Instructions

37
37

PERIPHERAL SUBSYSTEMS

6.1. AVAILABLE PEHIPHERAL EQUIPMENT

6.2. THE FLYING HEAD DRUMS
6.2.1. UNIVAC FH-432/FH-1782 Magnetic Drum Subsystem
6.2.2. UNIVAC FH-432 Magnetic Drum
6.2.3. UNIVAC FH-1782 Magnetic Drum
6.2.4. UNIVAC FH-880 Magnetic Drum

39
40

6.3. FASTRAND MASS STORAGE SUBSYSTEM

6.4. UNISERVO MAGNETIC TAPE SUBSYSTEMS
6.4.1. UNISERVO VI C Magnetic Tape Subsystem
6.4.2. UNISERVO VIII C Magnetic Tape Subsystem
6.4.3. UNISERVO VIII C/VI C Subsystem
6.4.4. Fully Simultaneous UNISERVO VIII C Subsystem

47
48
50

6.5. UNIVAC HIGH SPEED PRINTER SUBSYSTEM

6.6. PUNCHED CARD SUBSYSTEM
6.6.1. UNIVAC Card Reader
6.6.2. UNIVAC Card Punch

54
54

6.7. UNIVAC 9300 SUBSYSTEM

7. DATA COMMUNICATIONS

42
43

51
52

7.1. GENERAL

7.2. UNIVAC 1106 COMMUNICATIONS SUBSYSTEM

7.3. UNIVAC SYNCHRONOUS DATA TERMINALS
7.3.1. Word Terminal Synchronous
7.3.2. UN IV AC Commun i cation Terminal Synchronous

58
58
59

7.4. UNIVAC DATA COMMUNICATION TERMINAL (OCT) 2000

iii

7.5. UNISCOPE 300 VISUAL COMMUNICATION TERMINAL SUBSYSTEM
7.5.1. The Keyboard
7.5.2. CRT Display
7.5.3. Subsystem Configurations
7.5.4. Reliability
7.5.5. Special Features

63
63
64
64
64
65

7.6. UNIVAC 9200/9300 REMOTE SUBSYSTEMS
7.6.1. The UN IV AC 9200 System
7.6.2. The UNIVAC 9300 System
7.6.3. The UNIVAC Data Communication Subsystem, DCS-l

66
67
67
69

8. PROGRAMMED SYSTEMS SUPPORT

8.1. AVAILABLE SOFTWARE

8.2. TH E EXECUTIVE SYSTEM
8.2.1. Multiple Modes of Operation
8.2.1.1. Batch Pro cessi ng
8.2.1.2. Demand Processing (Time-Sharing)
8.2.1.3. Real Time
8.2.1.4. Multiprogramming
8.2.2. Techniques for Utilization of Mass Storage
8.2.3. The Primary Functional Areas of the Executive System
8.2.3.1. Executive Control Language
8.2.3.2. The Supervisor
8.2.3.3. Tim e SI i ci ng
8.2.3.4. Storage Compacting
8.2.3.5. Faci I ities Assignment
8.2.3.6. The File-Control System
8.2.3.7. Operator Communi cations
8.2.3.8. The Diagnostic System
8.2.3.9. Input/Output Device Handlers
8.2.3.10. Auxiliary Processors
8.2.3.11. Utilities
8.2.3.12. System Setup

72
72
72
73
73
73
74
74
74
74
75
75
75

8.3. THE ASSEMBLER
8.3.1. Symbolic Coding Format
8.3.2. Assembler Directives
8.3.3. Additional Features

75
75
76
76

8.4. FORTRAN V
8.4.1. Language Extensions and Enhancements
8.4.2. Compi I er 0 rgani zation

76
76
80

8.5. CONVERSATIONAL FORTRAN V
8.5.1. System Features
8.5.2. System Concepts
8.5.3. Conversational Processor and the Executive System
8.5.4. Conversational FORTRAN Language

81
81
81
82
82

71
71

71
71
72

8.6. LIFT, FORTRAN II TO FORTRAN V TRANSLATOR

8.7. COBOL
8.7.1. The P rocesso r
8.7.2. Special Features

83
84

8.8. ALGOL

8.9. SORT/MERGE

8.10. MATHEMATICAL FUNCTION PROGRAMS

8.11. APPLICATION PROGRAMS
8.11.1. Linear Programming System
8.11.2. APT III
8.11.3. PERT

87
87

88
88

8.12. MATH-PACK

8.13. STAT-PACK

APPENDICES

A. NOTATIONAL CONVENTIONS

B. SUMMARY OF WORD FORMATS

C. INSTRUCTION REPERTOIRE BY FUNCTION CODE

D. MATH-PACK ROUTINES

105

E. STAT-PACK ROUTINES

109

FIGURES

1-1. The Central Processor and Operator's Console
2-1. Minimum Multi-Module Storage Configuration

2-2. 262K Multi-Module Storage Configuration

4-1. Control Register Address Assignments

4-2. J-Determined Partial Word Operation

4-3. PJocessor State Register Format

7-1. CTMC Subsystem

TABLES

4-1. Fixed-Address Assignments

7-1. OCT 2000 Field Installable Options

INTRODUCTION

A medium-scale extension to the proven UNIVAC 1100 series of computers is provided by
the UNIVAC 1106 System. Its modular design provides growth potential within the UNIVAC
1106 .as well as possible upgrading to the larger UNIVAC 1108 System.
The UNIVAC 1106 permits the user to select an executive system most applicable to his
needs. This selection ranges from EXEC II, which provides a powerful batch processing
capability, to the UNIVAC 1106 Executive System with its real-time, multiprogramming ,
demand , and batch processing ability.
In addition to a versatile executive system, the UNIVAC 1106 utilizes the complete family
of UNIVAC 1108 unit proces sor software, application packages , and peripheral subsystems.

Figure 7 -7.

The Central Processor and Operator' s Console

SYSTEM

DESCRIPTION

2.1. GENERAL
The UNIVAC 1106 System is a general purpose, high performance unit processor system,
making good use of the latest advances in computer design, systems organization, and
programming technology. Its modular structure permits the selection of systems components to fulfill most efficiently the speed and capacity requirements for applications of
varying complexity.
As the workload increases, this modularity also enables the addition of input/ ou tput
subsystems and main storage. Among the principal features of the 1106 System are:

•

Large, modular, parity-checked, high speed main storage

•

Program address relocation

•

Storage protection

•

Partial-word addressability in 6, 9, 12, and 1S-bit portions as well as full-word
(36 bits) and doub1e- word (72 bits) addressing.

•

High speed, random access, auxiliary storage

•

Privileged mode for the Executive system

•

Guard mode for user programs.

2.2. SYSTEM COMPONENTS
The UNIVAC 1106 System is organized to allow a number of tasks to be performed
simultaneously under the direction of a common Executive control system.
The system is composed of four types of components:
•

Central Processor

•

Main Storage

•

Auxiliary Storage Subsystems

•

Peripheral Subsystems

2.2.1. Central Processor
The processor can perform all functions required for the execution of instructions
including arithmetic, input/ output, and Executive control. Included in the processor
is a set of 166-nanosecond integrated circuit control registers providing multiple
accumulators, index registers, input/output access control registers, and specialuse registers.
2.2.2. Main Storage
The main storage read/restore cycle time is 1.5 microseconds. The mInImUm
multi-module storage of the UNIVAC 1106 System is 65,536 36-bit words and is
expandable up to a maximum of 262,144 words.
2.2.3. Auxiliary Storage
The auxiliary magnetic drum storage subsystems are an integral part of each UNIVAC
1106 System. Up to eight FH-432 or FH-1782 magnetic drums, or any combination of
the two types, may be attached to one or two control units. Both types of drum can
transfer data at 1,440,000 characters per second (240,000 words per second). The average
access time of the FH-432 is 4.3 milliseconds; that of the FH-1782 is 17 milliseconds.

2.2.4. Operator's Control Console
The UNIVAC 1106 Operator's Control Console subsystem is a free-standing input/ output
device for directing and monitoring the operation of the CPU. The console is always
connected to input/ output channel 15.
The basic Control Console includes the following components:
•

Display Console
The Display Console contains a keyboard and a Cathode Ray Tube (CRT) display.
The keyboard is a standard four-bank keyboard which can generate 63 Fieldata codes.
A row of eight interrupt keys is located above the keyboard. The Cathode Ray Tube
can display 16 lines of 64 characters each. One UNIVAC PAGEWRITER printer is
required for the minimum configuration if this console is selected .

•

Day Clock
The day clock on the console displays the time of day in hours, minutes, and hundreths
of minutes. It furnishes the time of day to the CPU every 600 milliseconds and sends a
day clock interrupt signal to the CPU every 6 seconds. The day clock may be manually
disabled from the operator's console.
The day clock may be selected to be active either externally or by program.

•

Operator's Control and Indicator Panel
The Operator's Control and Indicator Panel includes fault, disable, and mode indicators
for its CPU and associated main storage modules; displays and controls associated
with selecting and releasing jumps and stops, with the Program Address Counter and
Memory Select Register, and with the time display of the Day Clock. It also includes
system controls associated with the CPU and subsystems which are logically connected
to the CPU.

•

Additional Features
- Auxiliary Console
An auxiliary right- or left-wing console can be included to accomodate control/display
panels for Communication Terminal Module Controller subsystems.
- UNIVAC PAGE WRITER Printer
The UNIVAC PAGEWRITER printer provides a hard copy of all messages for a
permanent record of all completed transactions between the operator and the Executive system. The PAGEWRITER prints lines of up to 80 characters per second.

2.3. CONFIGURATIONS
Figure 2-1 depicts the minimum multi-module storage configuration for the UNIVAC 1106
System. The CPU consists of the Command-Arithmetic Section and an Input/Output Section
with four I/O channels. Main storage provides 65K 36-bit words. The minimum peripheral
subsystems needed to support the software offered are: 1 FH-432/1782 Magnetic Drum
Subsystem with 6 FH-432 drums or 1 FH-1782 drum, 1 UNISERVO Magnetic Tape Sub7"
system with either 4 UNISERVO VI C or 4 UNISERVO VIII C Magnetic Tape Units, an
Operator's Console, and 1 online UNIVAC 9300 System.
Figure 2-2 illustrates the 262K multi-module storage configuration for the UNIVAC 1106
System.

POWER
SUPPLY
65K
STORAGE
MODULE

CENTRAL PROCESSOR UNIT

I/O
CHANNELS
12-15

r
PERIPHERAL
SUBSYSTEMS

I I I

CONSOLE

CONSOLE AND MINIMUM PERIPHERAL SUBSYSTEMS FOR 1106 OPERATING SYSTEM:
1 Operator's Console with:
Display Console and PAGEWRITER Printer
1 FH-432/1782 Magnetic Drum Subsystem with:
1 FH-1782 Drum or equivalent
1 UNISERVO Magnetic Tape Subsystem with:
4 UNISERVO VI C Magnetic Tape Units; or
4 UNISERVO VIII C Magnetic Tape Units
1 Online UNIVAC 9300 System with:
8K Main Storage
132 Print Position Printer
Multiplexer I/O Channel
600 cpm 80-Column Card Reader
Inter-Computer Control Unit
Figure 2-7. Minimum Multi-Module Storage Configuration

POWER
SUPPLY

65K
STORAGE
MODULE

65K
STORAGE
MODU LE

65K
STORAGE
MODULE

CENTRAL PROCESSOR UNIT

I I I I

I I

I
CONSOLE
PERIPHERAL
SUBSYSTEMS

USE TIME
METER

- - - - - OPTIONAL

NOTE:

EXEC 1\ supports 131K main storage maximum.

Figure 2 -2. 262 K Multi-Module Storage Configuration

3. MAIN

STORAGE

3.1. GENERAL
The main storage of the UNIVAC 1106 System is a high performance, fast access repository
for instructions and data. Its design fully supports the concepts of multiprogramming,
modularity, and reliability around which the entire UNIVAC 1106 System is constructed.
Among its featured characteristics are:
•

1.5 microsecond read/restore cycle time

•

65,536, 98,304, 131,072, 196,608, or 262,144 36-bit words of multi-module storage

•

Parity checking on all storage references

•

Hardware storage protection - lockout boundaries establishable in 512-word increments

•

Relative addressing and dynamic program relocatability through program base registers

•

Online serviceability - multi- module storage pairs may be removed for servicing withou
stopping the entire system.

Main storage performs the following functions:
•

Accepts an address from the processor.

•

Stores or retrieves a word at that address

•

Issues an acknowledgement signifying that a storage reference has been completed

•

Checks parity on all data and delivers an interrupt sig(lal to the processor should a
parity error occur.

The modular storage concept has significant advantages for the immediate as well as
the future needs of the system. Addition of banks of storage is simplified. It becomes
a simple matter to add storage elements, or to replace them with improved equipment
bank by bank, as technology advances.

3.2. STORAGE MODULE
Each module of multi-module storage includes 32,768 words of ferrite core array. Each
word is 36 bits long, and carries two additional parity bits in nonaddressable levels,
one bit for each half word. The main components of the module are a IS-bit address
register, a 36-bit read/restore register, parity checking circuits, and request/acknowledge
circuits.
The IS-bit address register of each storage module provides addressing for 32,768 words.
Since an 18-.bit address is generated within the processor at each storage reference, three
bits are available for selection of one of the four possible storage modules.
Parity is checked on reading or calculated on writing for each storage access. If a parity
error is detected, the storage bank sends a parity error interrupt signal to the processor
and rewrites the word in its incorrect form to ensure subsequent data errors when the
word is again referenced. Preservation of the error in this way facilitates fault location,
since the Executive can determine whether the failure is transient or is associated with
a marginal or complete failure of the module.
3.3. PACKAGING
For multi-module storage, one or two 32,768-word storage modules (module pair) within
a single cabinet constitute a bank. An adjacent cabinet contains DC power supplies for
operation of the bank.
3.4. STORAGE CAPACITY
Available multi- module storage capacity ranges from 65,535 words to the system maximum
of 262,144 words in accordance with the following:
65,536 words (two modules) - Minimum for system
98,304 words (three modules)
131,072 words (four modules)
196,608 words (six modules)
262,144 words (eight modules) - Maximum for system

3.5.

STORAGE PROTECTION
To prevent inadvertent program reference to out-of-range storage addresses, the 1106
processor includes a hardware storage protection feature. The controlling element in
this feature is the Storage Limits Register, the contents of which are as follows:

DATA AREA

INSTRUCTION AREA

UPPER
BOUNDARY

LOWER
BOUNDARY

UPPER
BOUNDARY

LOWER
BOUNDARY

The Storage Limits Register (SLR) can be loaded by the Executive system to establish
allowable operating areas for the program currently in execution. These areas are
termed the program instruction (I) and data (D) areas. Before control is given to a
particular program, the Executive loads the SLR with the appropriate I and D boundaries.
Before each main storage reference, the processor performs a limits check on the
address, comparing against the limits of either the I or D field of the SLR. An outof-limits address generates a guard mode interrupt, thereby allowing the Executive
to regain control and take appropriate action.
3.5.1. Storage Protection Modes
The Executive system can establish two different modes of storage protection by
means of control fields in the Processor State Register (PSR) described in Section 4.
Normally, the Executive itself operates in open mode; that is, the Storage Limits
Register may be loaded but the PSR is set to disregard this, and the Executive can
reference any location in main storage.
3.5.1.1.

Privileged Mode
Another mode can be establis4ed in the PSR for privileged programs. This
privileged mode protects against out-of-bounds writes. Privileged programs (such
as real-time programs or Executive-controlled subroutines) may enter non-alterable
(re-entrant) su brou tines, which are part of the Executive. Though these privileged
programs are assumed to be thoroughly checked out, the system is still fully
protected against unexpected occurrences since write protection is in effect.

3.5.1.2.

User Program Mode
In the user program mode, read, write, and jump storage protection is in effect.
Therefore, user programs are limited to those areas assigned by the Executive.
If the user program reads, writes, or jumps to an out-of-limits address, an interrupt
returns control to the Executive for remedial action.
Read/jump protection allows the Executive to stop the program at the point of
error, terminate it, and provide diagnos tic informa tion to the programmer thereby
minimizing wasted time and smoothing the checkout process.

3.6.

RELA TIVE ADDRESSING
Relative addressing is a feature of great significance in multiprogramming, timesharing, and real-time operations, for it allows storage assignments for one program
(the one going into execution) to be changed dynamically by the Executive to provide
continuous storage for operation of another program, and it permits programs to
dynamically request additional main storage according to processing needs. An
additional advantage is that systems programs stored in auxiliary storage may be
brought in for operation in any available area without complicated relocation
algorithms.
Relative addressing is provided for through base registers contained within the CPU.
Two separate registers control the basing of the program instruction and data bank,
and a third register controls the selection of the appropria te base register.

4. CENTR.AL PROCESSOR

UNIT

4.1. GENERAL
1:he UNIVAC 1106 Central Processor Unit (CPU) is the principal component of the
UNIVAC 1106 System and, generally, the one by which the entire sys tern is identified. It can operate under Executive or user program modes of control; it performs
both arithmetic and logical operations; and it accommodates and supervises up to 16
input/output channels.
4.2.

PRINCIPAL SECTIONS
The processor is logically divided into six interacting sections each of which is
identified and briefly described below.

•

Control Registers - The CPU has 128 program-addressable control registers
used for arithmetic operations, indexing, and input/output buffer control.

•

Arithmetic Section - This section contains the adder regis ters, and control
circuits necessary for performing fixed and floating point arithmetic, partial-word
selection, shifting, logical operations, and tests.

•

Control Section - This section provides the basic control and logic for instruction decoding and execution. It includes the Program Address Counter used
for the sequential accession of instructions; the Program Control Register in which
instructions are staticized for execution; and the Processor State Register (PSR),
which determines various processor operating modes. The Control Section also
services interrupts.

•

Input/Output Section - This section controls and multiplexes data flow
between main storage and 16 input/output channels. It includes an interrupt
priority network and paths to peripheral subsystems for both function signals
and data.

•

Indexing Section - This section contains parallel index adders and threshold
test circuitry. It is used generally for processor control functions, operand
address development, program relocation, and input/output transfer control.

•

Storage Class Control Section - The Storage Class Control section receives
the final operand address from the index adder and establishes address and
data paths to one of eight possible storage modules. Storage Class Control
also determines whether a final address refers to a control register.

4.3.

INSTRUCTION WORD FORMAT
The format of the 1106 instruction word is illustrated below followed by an explanation
of each field. Some fields have more than one meaning depending on the class of
ins truction.

4.3.1.

Function Code
These six bits specify the operation to be performed. For function codes above 70 ,
8
the f and j fields are combined to produce a 10-bit function code. An illegal function
code generates an interrupt.

4.3.2. Partial-Word or Immediate-Operand Designator
For function codes less than 70 8 , the j designator specifies partial-word or immediateoperand selection. (See Figure 4-2 for specific partial-word selections.)
4.3.3. Control Regis ter Designator
The four-bit a field designates which control register, within a group selected by
the function code, is involved in the operation. For some operations, the a field
refers to an arithmetic register; for others, it refers to either an index register or
some other control register. In input/output instructions, it specifies the channel
and its associated input or output access control register. For function code 708
the a and j designators together address one of the 128 control registers.
4.3.4. Index Register Designator
The x field specifies one of the 15 index registers to be used in address modification.
When register 00 is designated, indexing is suppressed.
4.3.5. Index Modification Designator
The h field controls modification of the index value (Xm) by the increment field
(Xi) after indexing (see 4.4.1). If h = 1, the right half of the index register is modified by the contents of its left half; if h = 0, modification is suppressed.
4.3.6. Indirect Address Designator
The i designator controls the use of indirect addressing during instruction execution.
If i = 0, the instruction functions normally. If i = 1, the 22 least significant bit
positions of the instruction (x, h, i and u fields) are replaced in the instruction
register with the contents of the 22 least significant bit positions of the word at
the effective address. Indirect addressing con tinues as long as i = 1 with full
indexing capa bility a t each level.

4.3.7.

Address Field
The u field normally specifies the operand address. However for certain instructions
it holds constants. For example, the shift instructions use the. seven least significant bit positions to hold the shift count. In all instructions, the value in the u
field may be modified by the contents of an index register.

4.4. CONTROL REGISTERS
The 128 program-addressable control registers are grouped to provide multiple index
registers, accumulators, input/output access control registers, and special registers
(see Figure 4-1).
The control registers consist of 36-bit integrated-circuit registers, with a basic cycle
time of 166 nanoseconds. Two parity bits are included with each control register.
Effective use of multiple accumulators and index registers for the development and
use of cons tan ts, index values, and operands substantially improves performance.
UNIVAC 1106 compilers, for example, perform significantly better through multiple
register usage, and can produce highly efficient. code.
In the following descriptions only programmable registers are discussed. The Executive,
through modes established by the Processor State Register, has exclusive use of tge
duplicate set o-f control registers as well as the Access Control Registers indicated
by the shaded areas in Figure 4-1.
4.4.1.

Index Registers
Control register locations DO-IS are Index Registers and have the following format:

X·I
35

MODIFIER INCREMENT OR DECREMENT

Xm
18 17

INDEX MODIFIER

The Xm portion of the index register is an 18-bit modifier to be added to the base
operand address of the ins truction. The Xi portion of the index word updates the
Xm portion, after base operand address modification.
Index register modification is specified by a 1 bit in the h field of the instruction,
while indexing itself is specified by a nonzero value in the x field. Both functions
take place within the basic instruction execution cycle.
When cascaded indirect addressing is used in a programmed operation, full indexing
capabilities are provided at each level. Indirect addressing replaces the x, h, i and
u portions of the instruction register, beginning with a new indexing cycle for each
cascaded sequence. This process continues until the i field is zero.

4.4.2. Arithmetic Accumulators
Control register locations 12-27 are arithmetic accumulators, for programmed storage
of arithmetic operands and results. The computation is performed in nonaddressable
transient registers wi thin the arithmetic section.
Depending upon the instruction, use of the accumulators results in a variety of
word formats. Double precision instructions and a number of logical instructions
reference two contiguous accumulators, i.e., A and A + 1. In arithmetic operations,
A + 1 always holds the least significant part of an operand or result. Some
ins tructions, such as single precision floating point operations, ca11 on a oneword operand from memory but produce a two-word result in the specified A
and A + 1.
4.4.3. Access Control Registers
Control register loca tions 32-63 are Input and Output Access Control Re gis ters
(ACR 's). They are guard mode protected and may be referenced only by the
Executive. Formats of the Access Control Words are detailed in Section 5.
The word-by-word transmission of data over an I/O channel is governed by the
contents of the ACR's. Two ACR's, one for input and one for output, are assigned
to each of the sixteen channels. Input ACR's (locations 32-47) control input
data transfers while output ACR's (locations 48-63) govern the transmission of
output data and Function Words.
When an input/output operation is initiated, the programmed ACR word is loaded
into the ACR corresponding to the channel associated with the specified peripheral
unit.
4.4.4.

R Registers
The sixteen control register locations 64-79 are R Registers. The first three of
these (RO, R1, R2) have specified functions and formats as described below. The
remaining R Registers are not specifically assigned; typically they are used as
loop counters, transient regis ters, or storage for intermedia te values or constants.

4.4.4.1.

RO - Real Time Clock

UNASSIGNED

CLOCK COUNT

This register is initially loaded by the program. The contents are then decremented
once each 200 microseconds. A real time clock interrupt occurs when the clock
count goes through zero. Thus, if the clock is initially loaded with the value 5000,
an interrupt occurs in exactly one second.

DECIMAL

OCTAL

I
27

33
34

16 ACCUMULATORS (A)

)

4 UN ASSIGN ED

V(BU'FER ADDRESS)

*16 INPUT ACCESS
CONTROL REGISTERS

OR
57

INPUT IDENTIFIER

OUTPUT IDENTIFtER

G
12

JII _______

*16 OUTPUT ACCESS
CONTROL REGISTERS

R.uJ.:.1J!41.~~L

_________
J..OL __________ MASK

l~I

ESI IDENTIFIER
REGISTERS

41
48

__________ ...§!

~~A~OU~~~ST~

103

_________

_ _ _ _ _ _ _ _ _ _ _6.§.

!!f~ll..R

16 SPECIAL REGISTERS (R

UNASSIGNED

117

lu.. __ -· _____ .- __.J!.NE!!., <)

•

Literals up to 132 characters

•

The ENTER Verb

•

The LOCK option on the CLOSE Verb

•

The ADVANCING option on the WRITE Verb

•

The REVERSED option of the OPEN Verb

•

Operands used in arithmetic can be up to 18 digits long.

•

AND and OR connectors in compound conditions

•

Parentheses in compound conditions

•

All abbreviations of conditional statements

•

The OBJECT-COMPUTER paragraph

•

The APPLY clause

•

RERUN

•

The DATA-COMPILED clause

•

Library provisions

•

Multiple results from arithmetic verbs

The following features, implemented in UNIVAC 1106 COBOL, are special UNIVAC
extensions to the COBOL language:
COBOL sub-program communication
MONITOR
Dynamic date
Common Storage
Page Control
A Report Generator, not part of the COBOL processor, is available for COBOL programs.
8.7.1. The Processor
The COBOL processor is a six-phase compiler. It is com pletely modular in relocatable
elements and it is handled as any program in the system for easy expandability and
maintenance. Likewise, the COBOL processor produces as its output relocatable
binary elements stored on the drum or mass storage, which are indistinguishable from
other elements in the system. Other output from the compiler includes extensive diagnostic messages, source language listings, machine language listings, and special
cross reference listings of name definitions and their references. The machine language
listing consists of side-by-side Procedure Division statements and the corresponding
generated symbolic machine code.
The compiler diagnostics are of two categories:
Warning - A minor source language error has been detected which does not
affect the program being produced. This type of diagnostic is identified by the
word ERROR preceding the actual message.
Fatal - A major source language error has been detected which very likely will
adversely affect the program being produced. The compiler will continue to
process the source language but will flag the program produced so that it cannot
easily be executed. This type of diagnostic is identified by the word ERROR*
preceding the a ctual message.

8.7.2. Special Features
Segmentation - COBOL programs can be segmented by use of priority numbers
on procedural sections.
Monitor - Provides dynamic program checkout facilities.
Library - The Procedure Definition Processor is available to store Environment,
Data and Procedure Division Descriptions so they can be retrieved by the COpy
and INCLUDE verb.
Rerun - The programmer can specify rerun after any number of records have been
processed or when an end of reel is encountered.
Common Storage - Since COBOL programs can be chained (an Executive function),
intermediate data results can be maintained between programs using the common
storage provision of UNIVAC COBOL. The elements sharing common storage may
be from another 1106 processor such as FORTRAN V.
Overpunched Sign Convention - Tapes and cards prepared in the overpunched sign
convention can be processed.
8.8.

ALGOL
The ALGOL language allows the mathematician or engineer to prepare programs for
the UNIVAC 1106 without the necessity of becoming familiar with the details of the
internal machine operation. From this pseudo-mathematical source language, the
ALGOL Compiler generates efficient coding in a relocatable binary format acceptable
to the Executive for execution, the filing system for cataloging and filing, or both.
The basis for the UNIVAC 1106 ALGOL is the "Revised Report on the Algorithmic
Language, ALGOL 60" (Communications of the ACM, Vol. 6, January 1963, 1-17).
UNIVAC 1106 ALGOL is an extended hardware representation of ALGOL 60 designed
to employ the UNIVAC 1106 processor and associated peripheral equipment efficiently.
Certain extensions to basic ALGOL have been made. It can handle the powerful input/
output logic; it has the ability to name strings; and it is capable of performing complex
and double precision arithmetic.

8.9.

SORT/MERGE
The UNIVAC 1106 Sort/Merge package is fully modular, with every functional unit
completely self-contained. This permits the various units to be individually adapted
to their own particular tasks, ena bling them to be a ssocia ted in the most effective
form, and allowing updating and augmentation.
The package is not a generator of specialized Sort/Merge routines; rather, the user
calls and adapts the independent modules for all his specific sorting needs by
presenting his parameter values on control cards at load time.

In the internal sort, the replacement selection method is used to take advantage of any
inherent sequence in the original data. Strings may be written upon magnetic tape or
drum. The UNIVAC FH-432 and FH-1782 Drums, because of their high transfer rates
and rapid access, minimize processor waiting time and thus greatly speed efficient
sort operations. Any random access unit areas may be defined by the Supervisor and
these are automatically used by the subsystem if advantage can be gained thereby.
The input data to be sorted may be stored on magnetic tape, punched cards or
magnetic drum. User own coding may be inserted on the first and final passes of
the Sort and Merge operation and may also replace the standard comparison routines.
Sorting generally requires the use of two magnetic tape units, although additional
units can be employed to give faster times.
Keys may be in multiple form and can be recorded, modified, and packed. Standard
collating sequences are intrinsically provided for, but the user may define any
collating sequences he requires, up to a maximum of seven, and any combination
of these may be utilized in the same run. Fixed or variable length items can be
handled.
The Sort/Merge Package normally uses 20,000 words of main storage, 262,000 words
of magnetic drum storage, and magnetic tape units of any kind as required; but the
user may specify more main and drum storage, and additional magnetic tape units to
increase efficiency and speed.
S.10. MATHEMATICAL FUNCTION PROGRAMS
The UNIVAC Software System includes an extensive collection of basic mathematical
subroutines and functions. This collection includes all of the standard FORTRAN
functions and has been expanded by over 50% to give the programmer a more complete
coverage of the often used mathematical routines. Each of these mathematical
routines has been carefully developed to offer the programmer maximum accuracy
and range with a minimum routine size and executive time. These routines are
available to each of the program languages, FORTRAN V, Assembler, COBOL
(through the use of the ENTER verb option), and ALGOL. One group of routines; the
series of exponentiation routines (NEXPi), are automatically referenced when the
FORTRAN V Source Prqgram indicates exponentiation with the operator **, and
inline exponentiation is not feasible.
The various mathematical function programs are:
1. Library Functions

2. The FORTRAN Built-in Function
3. The Exponentiation Functions
These routines are available to the process ors in different manners. For example,
the routine SQRT provides a single precision square root of the argument (x). To
utilize this routine the processors employ the following calling sequences:
•

FORTRAN V Calling Sequence:
ROOT = SQRT (X), when X is a FORTRAN V real variable.

•

ASSEMBLY Calling Sequence:
a

LMJ

Bl1,SQRT

a + 1
+
Add res s of X
a + 2
+
normal return
The result is left in AO.
•

COBOL Calling Sequence:
ENTER SQRT REFERENCING X

8.11

APPLICATION PROGRAMS
The UNIVAC 1106 System has an extensive library of application programs and subroutines. The major application programs such as Linear Programming (LP), Automatically Programmed Tools (APT III), and PERT are briefly described in the
following paragraphs while others are simply mentioned by titles. This is by no
means an exhaustive list of programs or subroutines. It is meant only to point out
the many types of application programs available for UNIVAC 1106 System.

8.11.1. Linear Programming System
Linear Programming eLP) has become one of the most useful and frequently used
operations research techniques in manQfacturing and transportation industries. In
the production and distribution of products, LP provides a solution to minimize
costs or maximize profits. The LP System developed for the UNIVAC 1106 System
embodies the latest advances in computer technology with the most powerful algorithm to date. The algorithm employs the "product form of the inverse" method
and is improved with an advanced path selection technique. The package is coded
in FORTRAN V and Assembly Language.
The more prominent feature of the 1106 LP System are as follows:

2. The speed and random access properties of magnetic drums place the system
at a distinct advantage over tape and disc handling procedures.
3. Both single precision and double precision computations are available. The
selection may be manual or automatic.
4.

The control language of this System is far superior to any other existing LP
System. It is an interpretive control language. The sophisticated user may
use macros in constructing his command string to implement the System. On
the other hand, the average user may still execute his basic LP problem
withou t detail knowledge of the con trol language.

5. The LP System is imbedded in the Executive System. This enhances the
System as a powerful model builder. Matrix builders and output analyzers
may be attached to the LP System to form corporate models. The entire
model may be optimized and re-optimized in cycles in one computer run.
Nonlinear programming may be accomplished by solving approximated linear
functions in each cycle.

In addition to the above features, the 1106 LP System contains the flexibilities
existing in other LP Systems. Vector levels can be specified and coefficients
may be modified. Long LP runs can be split with restart procedures. Post-optimal
parametric programming or a complete tableau can be obtained. The final output
includes the objective function value, optimal basis, vector levels, and reduced
costs.
8.11.2. APT III
APT (Automatically Programmed Tools) is a system for the computer assisted
programming of numerically controlled machine tools, flame cutters, drafting
machines, and similar equipment. It is production-oriented, written to take full
advantage of numerically controlled techniques in engineering and manufacturing
with the least expenditure of effort, time, and money.
APT enhances most of the usual advantages found in numerical control: reduced
lead time, greater design freedom and flexibility, lower direct costs, greater
accuracy, improved production forecasting, lower tooling costs, better engineering
control of the manufacturing process, and simplified introduction of changes.
The APT III program represents over one hundr~d man-years of development and
testing. After extensive experience with our earlier program, APT II, the Aerospace
Industries Association made a new start and wrote APT III from the beginning,
during the calendar year 1961. At the completion of this package, APT III was
turned over to the Illinois Institute of Technology Research Institute for further
development, under the APT long-range program. The use of certain parts of
APT requires membership in this long range program.
Univac participated in the original writing of APT III and has been a member
of the APT long-range program from the beginning. Numerical control specialists
are continually working to keep the UNIVAC 1106 APT program in the forefront of
the art. As implemented on the UNIVAC 1106 System APT III will continue to
conform to the latest APT long range program specifications.
8.11.3.

PERT
The UNIVAC 1106 PERT System is a generalized applications program based upon
the framework provided by the "DOD/NASA Guide to PERT/COST System Design".
The DOD/NASA design is based upon the concept of costing work packages rather
than individual network activities. A work package is a discrete unit of work required
to complete a specific job or process. The work packages of a research and development project are directly related to activities or groups of activities on the project
network. The work package is the basic unit of the PERT System for which actual
project costs are collected and compared with estimates for purposes of cost control.
The UNIVAC 1106 PERT System adheres rigorously to the DOD/NASA design and
satisfies the purposes of PERT/COST concept.
Many government agencies and contractors are currently processing PERT/TIME
data on existing systems. PERT is relatively new and will be subject to the inevitable modifications that will result from its initial pilot tests by DOD. In order
to lessen the impact of these changes upon existing PERT programs and to provide
for efficient integration of time and cost data, a modular design was adopted.

The modular structure of the program permits separate processing of the time
networks and of the work package costing structure while simultaneously providing for integrated time and cost reporting. The PERT/TIME Module of the
UNIVAC 1106 PERT System accepts as input a deck of cards describing the PERT
network. The cards are processed and used to update the PERT/TIME Master File.
Network computations are performed and the time reports are generated. The PERT /
COST Module accepts the cost breakdown structure, actual and estimated costs for
the project work packages, and a table of labor rates and applicable overhead percentages. Cost data is accumulated up through the cost breakdown tree, integrated
with the time information, and the required cost reports are generated.

8.12.

MATH-PACK
MATH-PACK provides the UNIVAC 1106 System with a comprehensive library of
78 fundamental mathematical subprograms coded in FORTRAN V. The purpose of
this library is to present to the mathematician, the scientist, and the engineer
many of the more frequently used tools of numerical analysis. These subroutines
and function subprograms are designed to speed up and simplify solutions to
problems encountered in many areas of scientific research.
The subprograms are grouped into fourteen categories:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)

Interpolation
Numerical Integration
Solution Of Equations
Differentiation
Polynomial Manipulation
Matrix Manipu la tion: Real Ma trices
Matrix Manipulation: Complex Matrices
Matrix Manipulation: Eigenvalues and Eigenvectors
Matrix Manipulation: Miscellaneous
Ordinary Differential Equations
Systems Of Equations
Curve Fitting
Pseudo-Random Number Generators
Specific Functions

Each of these classes contains subroutines and function subprograms that are
generally useful for problems commonly encountered by mathematicians, scientists,
and engineers.
Appendix D lists all of the MATH-PACK subprograms.
8.13.

STAT-PACK
STAT-PACK provides the UNIVAC 1106 System with a comprehensive library of
91 fundamental statistical subprograms coded in FORTRAN V. The purpose of this
library is to present to the statistician, the scientist, the operations research
specialist, and the engineer many of the more frequently used tools of statistical
analysis. These subroutines and function subprograms a re designed to speed up
the preparation of solutions to s tatis tical problems encountered within many areas
of scientific research.

The subprograms are grouped into thirteen categories:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)

Descriptive Statis tics
Elementary Population Statistics
Distribution Fitting and Plotting
Chi-Square Tests
Significance Tests
Confidence Intervals
Analysis of Variance
RegreSSion Analysis
Time Series Analysis
Multivariate Analysis
Distribution Functions
Inverse Distribution Functions
Miscellaneous

Each of these classes contains subroutines and function subprograms that are
generally useful for problems commonly encountered by statisticians, scien tis ts,
and engineers.
Appendix E lists all of the STAT-PACK subprograms.

APPENDIX A. NOTATIONAL
CONVENTIONS

Abbreviations and symbols frequently used in the description of the instruction repertoire
are given below:
( )

Contents of register or address with in parentheses.

( )'

Complement of contents of register or address.

\( )\

Absolute va lue or magnitude.

( )17-00

Subscripts indicate the bit positions involved. A full word is normally not subscripted. Subscripts
are also used to designate octal or decimal notation.

)c
( )f

Floating point biased exponent.
Final contents.

Initial contents.

Floating point fixed point part.

j-designated portion.
Function code.
Partial word designator or function code extension.

Arithmetic register designator. In input/output instructions, "att designates an I/O channel.

Ar ithmetic Register.

Index register des ignator.

Index register designator in a-field.

Index Register.

Index Register specified by coding xa.

Modifier portion of an index register.

Increment portion of an index register.
Same as rae

Designator specifying an R Register. It is coded in the a-designator position of an instruction word.

R Register.

R Register specified by coding rae

The base address of the operand (or the actual operand) as coded in u-field of an instruction.

The effective address or value of the operand after application of indexing and indirect addressing.

Destination address.

Source address.

h-designator of the instruction word. A value of 1 specifies incrementation of an index register.
i-designator of the instruction word. A value of -1 specifies indirect addressing.

PSR

Processor State Register.

BI
BS

I-Base Storage Block Number. }
Program Effective Switch point.

PSR Base
Re lative Address ing

D-Base Storage B lock Number.

Fields

SLR
CSR

Storage Limits Register.
Channel Select Register.

Program Address Register.

Bml

Symbol denoting logical product, or logical AND.

mil

Symbol denoting logical sum, or inclusive OR.

ElmI

Symbol denoting logical difference, or exclusive OR.

0 irection of data flow.

APPENDIX

B. SUMMARY OF
WORD

FORMATS

FIXED-POINT MULTIPLE SINGLE INTEGER RESULT

ADD HALVES WORD FORMA T

Carry

________________

______________

--'t

Carry _ _ _ _ _ _ _ _

ADD THIRDS WORD FORMAT

Carry

________

__________

SINGLE-PRECISION FLOATING-POINT OPERAND
S

35 34

CHARAC TERI STI C
(BIASED EXPONENT)

MANTISSA

27 26

SINGLE-PRECISION FLOATIN G-POIN T RESUL T
S

35 34

CHARACTERISTI C
(BIASED EXPONENT)

MANTISSA (NORMALIZED)

2726
A

CHARACTERISTI C

35 34

(BIASED EXPONENT)

2726

MANTISSA (NOT NECESSARILY NORMALIZED; CONTAINS RESIDUE,
LEAST SIGNIFICANT WORD OF PRODUCT, OR· REMAINDER)

A +1

DOU BL E-P RECISION FLOATIN G-POIN T OPERAN D OR RESUL T
S

35 34

CHA RAC TERI STI C
(BIASED EXPONENT)

MANTISSA

2423
A
MANTISSA

STORAGE LIMITS WORD

I-PORTION
UPPER LIMIT

2726

PROCESSOR STATE WORD

I-PORTION
LOWER LIMIT

D-PORTION
LOWER LIMIT

18 17

9 8

D-PORTION
UPPER LIMIT

NOT USED

~I----------------------~~------------------~'
•
DesignatJr Section
QUARTER-

Re lative

Addr~ss ing

Section

WORD
DESIGNATOR

INSTRU C TION WORD

INDEX REGISTER WORD

151 A CCESS CON TROL WORD
W

ESI A CC ESS CONTROL WORD (HALF WORD)

E51 ACCESS CONTROL WORD (QUARTER WORD)

SINGLE-PRECISION FIXED-POINT WORD

DOU BLE-PRECISION FIXED-POINT WORD

A+l

FI XED-POIN T IN TEGER MUL TI PLY

RESUL T

A +1

FIXED-POINT FRACTIONAL MULTIPLY RESULT

A +1

BIASED ESI VALUES IN IACR'S

BIASED OUTPUT ESI VALUE

BIASED INPUT ESI VALUE

APPENDIX C. INSTRUCTION REPERTOIRE
BY FUNCTION CODE
Function
Code
(Octo I)
Mnemonic

Instruction

Desc ri ption

Execution
Time* in
f1 sec. With
Overlap

Illegal Code

Causes illegal instruction interrupt

O-J 5

Store A

(A)~U

1.5

0-15

SN,SNA

Store Negative A

-(A)~U

1.5

0-15

SM,SMA

Store Magn itude A

I(A)I~U

1.5

0-15

S,SR

Store R

(Ra)~U

1.5

0-15

Store Zero

ZEROS~U

1.5

0-15

S,SX

Store X

(Xa)~U

1.5

Illegal Code

Causes illegal instruction interrupt
to address 2418

1.5

0-17

L,LA

Load A

(U)~A

1.5

0-17

LN,LNA

Load Negative A

-(U)~A

1.5

0-17

LM,LMA

Load Magn itude A

I(U)I~A

1.5

0-17

LNMA

Load Negative
Magnitude A

-I(U)I~A

1.5

0-17

A,AA

Add to A

(A)+(U)~A

1.5

0-17

AN,ANA

Add Negative To A

(A)-(U)~A

1.5

0-17

AM,AMA

Add Magn itude To A

(A)+I(U)I~A

1.5

0-17

ANM,ANMA

Add Negative
Magnitude to A

(A)-I(U)I~A

1.5

0-17

Add Upper

(A)+(U)~A+'

1.5

0-17

ANU

Add Negative Upper

(A)-(U)~A+1

1.5

0-15

Block Transfer

(Xx+u)~Xa+u,

0-17

L,LR

Load R

(U)~Ra

1.5

0-17

A,AX

Add To X

(Xa)+(U)~Xa

1.5

0-17

AN,ANX

Add Negative To X

(Xa)-(U)~Xa

1.5

0-17

LXM

Load X Modifier

(U)~Xa

; Xa
17-0

0-17

L,LX

0-17

*See notes at end of table.

repeat K times

unchanged

3.5+3.0K

1.666

35-18

Load X

(U)~Xa

1.5

Mu Itiply Integer

(A) • (U)~A,A+ 1

3.666

Function
Code
(Octal)

Mnemonic

Description

Instruction

0-17

MSI

Multiply Single Integer

(A) • (U)~A

3.666

0-17

Multiply Fractional

(A) • (U)~A,A+1

3.666

Illegal CoCie

Causes illegal instruction interrupt
to address 2418

0-17

Divide Integer

(A,A+1)7(U)~A; REMAINDER~A+1

13.950

0-17

DSF

Divide Single Fractional

(A)7(U)~A+ 1

13.950

0-17

Divide Fractional

(A,A+1) 7(U)~A; REMAINDER~A+1

13.950

Illega I Code

Causes illegal instruction interrupt
to address 2418

0-17

Logical OR

(A)

0-17

XOR

Logical Exclusive OR

(A)EIiII (U)~A+1

0-17

AND

Logical AND

(A)

0-17

MLU

Masked Upper Load

[(U) f.1mJ (R2~ OR [(A)
(R2),] ~ A+1

0-17

TEP

Test Even Parity

Skip NI if (U) m!] (A) have even
parity

3.00/2.166

0-17

TOP

Test Odd Par ity

Skip NI if (U) rJm] (A) have
odd parity

3.00/2.166

0-17

LXI

Load X Increment

(U)~Xa

1.833

0-17

TLEM

Test Less Than or
Equa I to Mod ifier

Skip NI if (U) $. (X a)
;
17-0

TNGM

Test Not Greater
Than Mod ifier

(Xa)

(U)~A+ 1

r..1ml

; Xa
35-18

17-0

1.5
1.5

(U)~A+ 1

always (Xa)

1.5

unchanged

1.5

17-0
3.333/1.833

+ (X a)
~
35-18

17-0

0-17

Test Zero

Skip NI if (U) =

±o

3.166/1.666

0-17

TNZ

Test Nonzero

Skip NI if (U) -#

±o

3.166/1.666

0-17

Test Equal

Skip NI if (U) = (A)

3.166/1.666

0-17

TNE

Test Not Equal

Skip NI if (U) f= (A)

3.166/1.666

0-17

TLE

Test Less Than or Equal

Skip NI if (U) ~ (A)

3.166/1.66

TNG

Test Not Greater

0-17

Test Greater

Skip NI if (U) > (A)

3.166/1.666

0-17

Test Within Range

Skip NI if (A)«U)< (A+1)

3.33/1.66

*See notes at end of table.

Execution
Time* in
flsec. With
Overlap

Function
Code
(Octal)
f

Mnemonic

Instruction

Description

Execution
Time* in
p.sec. With
Overlap

0-17

TNW

Test Not Within Range

Skip NI if (U)~ (A) or
(U»(A+l)

3.33/1.66

0-17

Test Positive

Skip NI if (U~5 = 0

3.0/1.5

0-17

Test Negative

Skip NI if (U~5 = 1

3.0/1.5

0-17

Search Equal

Skip NI if (U)=(A). else repeat

3.5+ 1.5K

0-17

SNE

Search Not Equal

Skip NI if (U):;l(A). else repeat

3.5+ 1.5K

0-17

SLE
SNG

Search Less Than or Equal
Search N at Greater

Skip NI if (U)~ (A). else repeat

3.5+1.5K

0-17

Search Greater

Skip NI if (U»

3.5+ 1.5K

0-17

Search Within Range

Skip NI if (A)«U)::;'(A+l). else
repeat

3.5+ 1.5K

0-17

SNW

Search Not Within Range

Skip NI if (U)::;' (A) or
(U» (A+ 1). else repeat

3.5+ 1.5K

JGD

Jump Greater and Decrement

Jump to U if (Control Register)ja>

3.0/1.5

(A). else repeat

0; go to NI if (Confrol Register)ja
::;. 0; always (Control Register)ja-1
~ Control Registerja

MSE

Mask Search Equal

Skip NI if (U) rJm] (R2) = (A)
(R2). else repeat

3.5+ 1.5K

Skip NI if (U) Bml (R2):;l (A)
(R2). else repeat

3.5+1.5K

Skip NI if (U) mID (R2) ~ (A)
else repeat

3.5+1.5K

mD
71

MSNE

Mask Search Not Equal

mID
71

MSLE

Mask Search Less Than or
Equal

MSNG

Mask Search Not Greater

Dml ((R2).

MSG

Mask Search Greater

Skip NI if (U) BID] (R2»(A)
flm] (R2). else repeat

3.5+1.5K

MSW

Masked Search Within Range

Skip NI if (A) amJ (R2) < (U)
Dml (R2) ~ (A+l) rJml (R2).
else repeat

3.5+ 1.5K

MSNW

Masked Search Not Within
Range

Skip NI if (U) rJml (R2)::;' (A)
or (U)
(R2) >
(A+l)
(R2). else repeat

3.5+1.5K

I.1IDl (R2)

Masked Alphanumeric Search
Less Than or Equal

Skip NI if (U) rJml (R2) ~ (A)
(R2). else repeat

3.5+1.5K

MASL

*See notes at end of table.

The j and a fields together serve to specify any of the 128 control registers.

function
Code
(Octo I)

Mnemonic

Instruction

Description

mm (R2), else repeat

Execution
Time* in
flsec. With
Overlap

J
Skip NI if (U)

(R2) > (A)

BIDl

3.5+ 1.5K

MASG

Masked Alphanumeric
Search Greater

Double Precision Fixed
Point Add

(A,A+l) + (U,U+l)

A,A+l

3.167

DAN

Double Precision Fixed
Point Add Negative

(A,A+l) - (U,U+ 1) --+ A,A+l

3.167

Double Store A

(A,A+l)

3.0

Double Load A

(U,U+l) --+ A,A+l

3.0

DLN

Double Load Negative A

-(U,U+ 1) --+ A,A+ 1)

3.0

DLM

Double Load Magnitude A

I(U,U+l)1 --+ A,A+l

3.0

DJZ

Double Precision Zero Jump

Jump to U if (A,A+ 1) = ±O;
go to NI if (A,A+l) ~ ±O

3.167/1.667

DTE

Double Precision Test Equal

Skip NI if (U,U+l) = (A,A+l)

4.667/3.167

Illegal Code

Causes i lIega I instruct ion interrupt
to address 2418

SLJ

Store Location and Jump

(P)-Base Address Modifier [BI or
BD] --+ U17 - 0 ; jump to U+ 1

3.83

JPS

Jump Positive and Shift

Jump to U if (A)3S=0; go to NI if
(A)35= 1; always shift (A) left
circularly one bit position

3.0/1.5

JNS

Jump Negative and Shift

Jump to U if (A)35= 1; go to NI if
(A)35=0; always shift (A) left
circularly one bit position

3.0/1.5

Add Halves

(A)35-18+ (U)35-18--+ A 35 - 18 ;
(A)17-0+(U)17-0--+ A I7-0

1.5

ANH

Add Negative Halves

(A)35-18 -(U)35-18--+ A 35-18;

1.5

--+

U,U+l

(A)17-o -(U)17-0--+ A 17-o
72

Add Thirds

(A)35-24+ (U)35-24--+ A 35-24
(A)23-12+ (U)23-12--+ A 23-12

1.5

(A)1l-0+ (U)l1-o--+ A ll-o

ANT

Add Negative Thirds

(A)35-24 -(U)35-24--+ A35-24
(A)23-12 -(U)23-12--+ A 23-12
(A)l1-o - (U)11-0--+ A ll-o

*See notes at end of table.

1.5

Function
Code
(Octo I)

Mnemonic

Instruction

Description

Execution
Time* in
I1sec. With
Overlap

Execute

Execute the instruction at U

1.5

Executive Return

Interrupt to address 2428

2.33

Illegal Code

Causes illegal instruction interrupt
to address 2418

PAIJ

Prevent All I/O Interrupts
and Jump

Prevent all I/O interrupts and
jump to U

1.5

SCN

Store Channel Number

If a=O: CHANNEL NUMBER ~
U3-0; If a= 1: CHANNEL NUMBER~
U3-0 and CPU NUMBER~ U5- 4

1.5

LPS

Load Processor State
Register

(U)~

PSR

1.5

LSL

Load Storage Limits
Register

(U)

SLR

1.5

Illegal Code

Causes illegal instruction interrupt
to address 2418

SSC

Single Shift Circular

Shift (A) right circularly U places

1.5

DSC

Double Shift Circular

Shift (A,A+ 1) right circularly U
places

1.5

SSL

Single Shift Logical

Sh ift (A) right U places; zerofi II

1.5

DSL

Double Shift Logical

Shift (A,A+ 1) right U places;
zerofi II

1.5

SSA

Single Shift Algebraic

Shift (A) right U places; signfill

1.5

DSA

Double Shift Algebra ic

Shift (A,A+l) right U places;
signfill

1.666

LSC

Load Shift and Count

(U)~A; shift (A) left circularly
unti I (A) 35 =i (A)34' NUMBER

2.0

OF SHIFTS
73

DLSC

Double Load Shift and
Count

A+l

(U,U+ 1) ~ A,A+ 1; Shift (A,A+ 1)
left circularly until (A,A+ 1)71 =i

3.830

(A,A+l)70; NUMBER OF SHIFTS ~
A+2
73

LSSC

Left Single Shift Circular

Shift (A) left circularly U places

1.5

LDSC

Left Double Shift Circular

Shift (A,A+ 1) left circularly U
places

1.666

*See notes at end of table.

Function
Code
(Octal)

Description

Instruction

Mnemonic

Execution
Time* in
flsec. With
Overlap

LSSL

Left Single Shift Logical

Shift (A) left U places; zerofill

1.5

LDSL

Left Double Shift Logica I

Shift (A,A+ 1) left U places;
zerofill

1.666

III
(a=O or 1)

Initiate Interprocessor
Interrupt

Initiate Interprocessor Interrupt

1.5

ALRM
(a= lOS)

Alarm

Turn on alarm

1.5

EDC
(a= llS)

Enable Day Clock

Enable day clock

1.5

DOC
(a= 12S)

Disable Day Clock

Disable day clock

1.5

Se lect Interrupt Location

(A)2-0 ~ MSR

1.5

SIL

LCR
(a=O)

Load Channel Select
Register

(U)3-0~ CSR

1.666

LLA
(a=l)

Load Last Address Register

(U)2-D ~ LAR

1.666

If (U)30= 1, interrupt to address

3.166/1.666

Test and Set

244S; if (U)30=0, go to NI; always
01 8 ~ U35-30 ; U29 -D unchanged
74

Jump Zero

Jump to U if (A)= to; go to NI if
(A) i ±O

3.0/1.5

JNZ

Jump Nonzero

Jump to U if (A)
(A) itO

= to; go to Ni if

3.0/1.5

Jump Positive

Jump to U if (A)35
(A)35

Jump Negative

Jump to U if (A)35
(A)35

3.0/1.5

= 1; go to NI if

3.0/1.5

JK
J

Jump Keys
Jump

Jump to U ifa=O or ifa=lit
SELECT JUMP indicator; go to
NI if neither is true

1.5

HKJ
HJ

Halt Keys and Jump
Halt Jump

Stop if a= 0 or if [a MfI I it
SELECT STOP indicators] 0;
on restart or continuation, jump
to U

1.5

NOP

No Operation

Proceed to next instruction

1.5

*See notes at end of table.

100

= 0; go to NI if

-i

Function
Code
(Octa I)

Mnemonic

Instruction

Description

Execution
Time* in
Ilsec. With
Overlap

AAIJ

Allow All I/O Interrupts
and Jump

Allow all I/O interrupts and jump
to U

1.5

JNB

Jump No Low Bit

Jump to U if (A)O = 0; go to NI if

3.0/1.5

(A)O= 1
74

Jump Low Bit

Jump to U if (A)O = 1; go to NI if

3.0/1.5

(A)O=O
74

JMGI

Jump Modifier Greater and
Increment

> 0; go to NI
17-0
if (Xa)
< 0; always (X a)
+
17-0 . 17-0
(X)
~X
a 35-18
a17

3.166/1.5

Jump to U if (X a)

-o

LMJ

Load Modifier and Jump

(P) - Base Address Modifier
[BI or BO] ~ Xa
; jump to U
17-0

1.666

Jump Overflow

Jump to U if 01 of PSR = 1; go to
NlifOl=O

3.0/1.5

JNO

Jump No Overflow

Jump to U if 01 of PSR = 0; go to
NI if 01 = 1

3.0/1.5

Jump Carry

Jump to U if 00 of PSR= 1; go to
NI if 00= 0

3.0/1.5

JNC

Jump No Carry

Jump to U if 00 of PSR = 0; go to
NI if 00 = 1

3.0/1.5

LlC

Load Input Channel

For channel [a rm1 CSR]: (U) ~
IACR; set input active; clear input
monitor

1.5

LlCM

Load Input Channel
and Monitor

For channel [a mil CSR]: (U) ~
IACR; set input active; set input
monitor

1.5

JIC

Jump Input Channel Busy

Jump to U if input active is set
for channel [a ImJ CSR]; go to NI
if input active is clear

1.5

OIC

Disconnect Input Channel

For channel [a ~ CSR]: clear
input active; clear input monitor

1.5

LOC

Load Output Channel

For channel [a ' lmI CSR]: (U)-+,
OACR; set output active; clear output monitor; clear external function
(lSI only)

1.5

*See notes at end of table.

101

Function
Code
(Octal)
f

Mnemonic

Description

In struction

LOCM

Load Output Channe I and
Monitor

For channel [a (ill) CSR]; (U) ~
OACR; set output monitor; clear external function (lSI only)

1.5

JOC

Jump Output Channel Busy

Jump to U if output active is set for
channel [a [i]3 CSR]; go to NI if
output active is clear

1.5

DOC

Disconnect Output Channel

For channel [a
CSR]: clear
output active; clear output monitor;
clear external function

1.5

LFC

Load Function in Channel

For channel [a [i]3 CSR]: (U) ~
OACR; set output active (lSI only),
external function, and force external
function; clear output monitor (lSI
only)

1.5

LFCM

Load Function in Channel and
Monitor

For channel [a l!m CSR]: (U) ~
OACR; set output active (lSI only),
external function, force external
function, and output monitor (lSI
only)

1.5

JFC

Jump Function in Channel

Jump to U if force external function
is set for channel [a [ill) CSR]; go
to NI if force external function is
clear

1.5

Illegal Code

If guard mode is set, causes guard
mode interrupt to address 2438. If
guard mode is not set, same as NOP

1.5

AACI

Allow All Channel External
Interrupts

Allow all external interrupts

1.5

PACI

Prevent All Channel External
Interrupts

Prevent all external interrupts

1.5

75
75

16
17

Illegal COde}
Illegal Code

If guard mode is set, causes guard
mode interrupt to address 2438. If
guard mode is not set, same as NOP

1.5

Floating Add

(A) + (U) ~ A; RESIDUE ~ A + 1

3.0

FAN

Floating Add Negative

(A) - (U) ~ A; RESIDUE ~ A + 1

3.0

Floating Multiply

(A) • (U)

Floating Divide

(A) -;- (U) ~ A; REMAINDER ~ A + 1

LUF

Load and Unpack Floating

I(U)134-2r~ A7- 0, zerofill;

A, A + 1

(U)26-0 ~ A + 126- 0 , signfill
*See notes at end of table.

102

Execution
Time* in
I1sec. With
Overlap

4.0
11.5**
1.5

Function
Code
(Octa I)

Description

In stru ction

Mnemonic

Execution
Time* in
flsec. With
Overlap

LCF

Load and Convert To Floating

(U~f5 4 A + 135 ; [NORMALIZED
(U) 26-0 4 A + 126 - 0; if (U)35 = 0,
(A)7-0 ± NORMALIZING COUNT 4

2.0

A + 134- 27 ; if (U)35 = 1, ones
complement of [(A)7-0 ± NORMALIZING COUNT]
76

MCDU

CDU

-4

A + 134- 27

Magnitude of Characteristic
Difference To Upper

II (A)35-27 I -I

(U) 135-2714
A + 18- 0; ZEROS -4 A + 135- 9

1.5

Characteristic Difference To

I(A)1 35- 27 -1(u)1 35- 27 4 A + 18- 0;

Upper

SIGN B'ITS 4 A + 135- 9

DFA

Double Precision Floating Add

(A, A + 1) + (U, U + 1) 4 A, A + 1

4.5

DFAN

Double Precision Floating Add
Negative

(A, A+ 1) - (U, U+ 1)4 A, A+ 1

4.5

DFM

Double Precision Floating
Multiply

(A, A+ 1)· (U, U+ 1) ---)A, A+ 1

6.667

DFD

Double Precision Floating
Divide

(A, A + 1) + (U, U + 1) 4 A, A + 1

24.0***

DFU

Double Load and Unpack
Floating

I(u)134-24 4 AlO- o, zerofill;

Double Load and Convert to
Floating

(U)35 4 A + 135 ; [NORMALIZED
(U, U + 1)]59-0-4 A+ 123- 0 and

DFP

3.0

(U)23-0 -4 A + 123- 0, signfill;
(lJ+1)4A+2
3.830

A + 2. If (U)35 = 0, (A)lO-O

± NORMALIZING COUNT 4 A +
134-24. If (U)35 = 1, ones complement of [(A)10-0 ± NORMALIZING
COUNT] 4 A + 134- 24
76

FEL

Floating Expand and Load

If (U)35 = 0, (U)35-27 + 160°8 4
A35- 24 ; if (U)35

= I,

1.833

(U)35-27

-1600 8 .-4 A35- 24 ; (U)26-3 4 A23 - 0 ;
(U)2-0 -4 A + 135- 33 ; (U)354 A
A+1 32 ..()
76

FCL

Floating Compress and Load

If (U)35 = 0, (U)35-24 -16008 4
A35- 27 ; if (U)35 = 1, (U)35-24

3.167

+ 16008 -4 A35 - 27 ; (U)23-0 4
A26 - 3; (U+ 1)35-33 4 A2-0

0-17

Illegal Code

Causes illegal instruction interrupt
to address 2418

*See notes at end of table.

103

NOTES:

Execution times given are cakulated using a core memory cycle time of 1.5 microseconds and a CPU clock cycle time
of 166 nanoseconds.
For all comparison instructions, the first number represents the skip or jump condition, the second number is for a no
skip or no jump condition.
For function codes 01 through 67, add .333 microseconds to execution times for 6-bit, 9-bit, and 12-bit writes.
Execution time for the Block Transfer and the search instructions depends on the number of repetitions of the instruction
required. The variance is 3.0K microseconds for Block Transfer and 1.5K microseconds for searches where K equals the
number of repetitions; that is, K equals the number of words in the block being transferred or the number of words searched
before a match is found.

104

If 28 instead of 27 subtractions are performed, add .333 microseconds.

***

If 61 instead of 60 subtractions are performed, add .333 microseconds.

APPENDIX D. MATH-PACK
ROUTINES

The following is a complete listing of STAT-PACK routines grouped according to
function:

INTERPOLATION
GN INT - Gregory-Newton Interpo lation
GNEXT - Gregory-Newton Extrapolation
GNPOL - Gregory-Newton Polynomial Evaluation
BESINT - Bessel Interpolation
ST INT - Stirling Interpolation
CDINT - Gauss Central-Difference Interpolation
AITINT - Aitken Interpolation
YLG INT - Lagrange Interpolation
SPLN 1, SPLN2 - Spl ine Interpolation>

NUMERICAL INTEGRATION
TRAPNI - Trapezoidal Rule
SIM1NI - Simpson 1/3 Rule
SIM3NI - Simpson 3/8 Rule
STEPNI - Variable Step Integration
GENNI - Generalized Numerical Quadrature
DOUBN I - Double Integration
LGAUSS - Gauss Quadrature Abscissas and Weights
SIMPTS - Simpson 1/3 Rule Abscissas and Weights

105

SOLUT ION OF EQUATIONS
NEWTIT - Newton-Raphson Iteration
WEGIT - Wegstein Iteration
AITIT - Aitken Iteration
ROOTCP - Real and Complex Roots of Real or Complex Polynomial

DIF FERENTIATION
DE R IVl - First Derivative Approximation
DERIV2 - Second Derivative Approximation
NTHDER - Nth Derivative of a Polynomial

POL YNOMIAL MANIPULATION
GIVZRS - Polynomial Coefficients Given its Zeros
CVALUE - Complex Polynomial Evaluation
POLY X - Real Polynomial Multiplication
CPOL YX - Complex Polynomial Multiplication

MATRIX MANIPULATION: REAL MATRICES
MXADD - Matrix Addition
MXSU B - Matrix Subtraction
MXTRN - Matrix Transposition
MXSCA - Matrix Multiplication by Scalar
MXML T - Matrix Multiplication
MXMDIG - Matrix Multiplication by Diagonal Matrix Stored as a Vector
GJR - Determinant; Inverse; Solution of Simultaneous Equations
MXHOI - Inverse Accuracy Improvement

106

MATRIX MANIPULATION: COMPLEX MATRICES
CMXADD - Matrix Add ition
CMXSU B - Matrix Subtraction
CMXTRN - Matrix Transposition
CMXSCA - Matrix Mu Itipl ication by Sca lar
CMXML T - Matrix Mu Itipl ication
CGJR - Determinant; Inverse; Solution of Simultaneous Equations

MATRIX MANIPULATION EIGENVALUES AND EIGENVECTORS
TR IDMX - Trid iagona I izati on of Rea I Symmetric Matrix
E I GV AL - E igenva lues of T rid iagona I Matrix by Sturm Sequences
EIGVEC - Eigenvectors of Tridiagonal Matrix by Wilkinson's Method

MATRIX MANIPULATION: MISCELLANEOUS
DGJ R - Doub le-Prec is ion Determinant; Inverse;
Solution of Simultaneous Equations
PMXTRI - Polynomial Matrix Triangularization
SCALE - Polynomial Matrix Scaling
MX ROT - Matrix Rotation

ORDINARY DIFFERENTIAL EQUATIONS
EULDE - Euler's Method
HAMDE - Hamm ing' s Method
INVAL - Initial Values for Differential Equation Solution
RKDE - Runge-Kutta Method
SODE - Second-Order Equations
MRKDE - Reduction of Mth-Order System to System of
m First-Order Equations

107

SYSTEMS OF EQUAT IONS
JACMX - Jacobi Iteration to Determine Eigenvalues and
Eigenvectors of Symmetric Matrix
HJACMX - Jacobi Iteration to Determine Eigenvalues and
Eigenvectors of Hermitian Matrix
LSIMEQ

Solution to a Set of Linear Simultaneous Equations

NSIMEQ

Functional Iteration to Determine Solution to Set
of Non-Linear Equations

CURVE F ITT ING
CFSRI E - Coefficients of Fourier Series on a Continuous Range
FTRANS - Fourier Transform
DFSRIE - Coefficients of Fourier Series on Discrete Range
FITD - Fitted Value and Derivative Values for a Least-Squares
Polynomial
ORTHLS - Orthogonal Polynomial Least-Squares Curve-Fitting
FITY - Fitted Values for a Least-Squares Polynomial
COEFS - Coefficients of a Least-Squares Polynomial

PSUEDO-RANDOM NUMBER GENERATORS
NRAND -

Interval (0,227) Generator

RANDU -

Uniform Distribution

RANDN - Normal Distribution
RANDEX - Exponential Distribution

SPECIFIC FUNCTIONS
BSSL - Zero- and First-Order Bessel Functions
BESJ - Regular Bessel Functions of Real Argument
BESY - Irregular Bessel Functions of Real Argument
BESI - Regular Bessel Functions of Imaginary Argument
BESK - Irregular Bessel Functions of Imaginary Argument
GAMMA - Gamma Function Evaluation
LEGEN - Legendre Polynomial Evaluation
ARCTNQ - Arctangent of a Quotient

108

APPENDIX E. STAT-PACK

ROUTINES

The following is a complete listing of STAT-PACK routines grouped according to
function:
DESCRIPT IVE STATISTICS
FREQP - Frequency Polygon
HIST - Histogram
MH 1ST - Mu Itivariate Histogram
GROUP - Grouping of Data

ELEMENTARY POPULATION STATISTICS
AMEAN - Arithmetic Mean
GMEAN - Geometric Mean
HMEAN - Harmon ic Mean
MEDIAN - Median
MODE - Mode
QUANT - Quantiles
OGIVE - Distribution Curve
IQRNG - I nterpercent i Ie Range
RANGE - Range
MNDEV - Mean Deviation
STDEV - Standard Deviation
CVAR - Coefficient of Variation
ORDER - Order and Rank Statistics
CMONT - Centra I Moments
AMONT - Absolute Moments
CUML T - Cumulants
SH PCOR - Sheppard's Correction s
KURSK - Skewness and Kurtosis

109

DISTRIBUTION, FITTING AND PLOTTING
BINOM - Binomial Distribution
POISON - Poisson Distribution
HYPER - Hypergeometric Distribution
PNORM - Norma I Di stribution
AFSER - Arne Fisher Series

CHI-SQUARE TESTS
CHI21S - CHI-Square Test of Sample ProportionOne Sample
CHI2JS - CHI-Square Test of Sample Proportion J Samples
CHI2P - CHI-Square Test of Fit to Poisson
Distribution
CH 12N - CH I-Square Test of Norma I ity
CHISAM - CHI-Square Test of Homogeniety
CH ICNT - CH I-Square Test for Independence
GENGOF - CH I-Square Test of Genera I Goodness of Fit

SIGNIFICANCE TESTS
SIGPRP - Test of Significance of Proportion of
Successes
SIGMN - Test of Significance of a Mean
SIGDMN - Test of Significance of the Difference
Between Two Means
SIGDVR - Test of Sign ificance of the Ratio
Between Two Variances

110 .

CONFIDENCE

INTERVALS

CFDMKV - Confidence Interval for the Mean;
Known Variance
CFDMUV - Confidence Interva I for the Mean;
Unknown Variance
C F DMSU - Confidence Interva I for, the 0 ifference
Between Two Means
CFDVAR - Confidence Interval for Variance
TOLINT - Tolerance Intervals

ANALYSIS OF

VARIANCE

ANOVl - One-Way Cross Classification
ANOV2 - Two-Way Cross Classification
ANOV3 - Three-Way Cross Classification
MISDAT - Missing Data
VTRANS - Variable Transformations
ANOVRB - Randomized Blocks
ANOVLS - Latin Squares
ANOVSP - Split Plot Design
ANOSSP - Split-Split Plot Design
ANOVN2 - Two-Way Nested Des ign
ANOVN3 - Three-Way Nested Des ign
ANOCO - Ana Iys i s of Covariance
GLH - General Linear Hypotheses

REGRESSION ANAL YSIS
RESTEM - Stepwise Multiple Regression
REBSOM - Back Solution Multiple Regression
CORAN - Correlation Analysis

111

TIME SERIES ANALYSIS
MOVAVG - Moving Averages
SE ASH I - Sh i sk in's Sea sona lity Factors
WEMAV - Weighted Moving Averages
TRELS - Trend Analysis by Least Squares
VADIME - Variate Difference Method
TSFARG - Autoregressive Model
GEXSMO - Generalized Exponential Smoothing
AUXCOR - Auto-Correlation and Cross-Correlation Analysis
POWDEN - Power Density Functions
RCPROB - Residual Probabilities

MUL TI-VARIATE ANAL YSIS
GENVAR - Generalized Variance
DISHOT - Hotelling's Distribution
DSQ - Mahalanobois' Distribution
SIGTMN - Significance of a Set of Means
DISCRA - Discriminant Analysis
FACTAN - Factor and Principal Component Analysis

DISTRIBUTION FUNCTIONS
RNORM - Normal Distribution
CHI - CHI-Square Distribution
STUD - Student's Distribution
FISH - Fisher's Distribution
POlS - Poisson Distribution
BIN - Binominal Distribution
HYGEO - Hypergeometric Distribution
GAMIN - Incomplete Gamma Distribution
BETINe - Incomplete BETA Distribution

112

INVERSE DISTRI BUTION FUNCTIONS
TINORM - Inverse Normal Distribution
STUDIN - Inverse Student's Distribution
FISHIN - Inverse Fisher's Distribution
CHIN -

Inverse CHI-Square Distribution

MISCELLANEOUS
rLOTl - Plot of One Line
JIM - Matrix Inversion
MXTML T - Left Multiplication of a Matrix
by its Transpose

113

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